2006.223.07:10:39.73;Log Opened: Mark IV Field System Version 9.7.7 2006.223.07:10:39.73;location,TSUKUB32,-140.09,36.10,61.0 2006.223.07:10:39.73;horizon1,0.,5.,360. 2006.223.07:10:39.73;antenna,32.0,180.0,180.0,10.0,710.0,5.0,88.0,azel 2006.223.07:10:39.73;equip,k42c/mk4,vlbab,vlbab,mk4,500.10,3,a/d,101,60,20,none,41,1,in,8bit,cdp,3 2006.223.07:10:39.73;drivev11,330,270,no 2006.223.07:10:39.73;drivev12,mvme117,0,11.400,2548.000,152.780,-6.655,0.014,152,10.000,54500 2006.223.07:10:39.73;drivev13,15.000,268,10.000,10.000,10.000 2006.223.07:10:39.73;drivev21,330,270,no 2006.223.07:10:39.73;drivev22,mvme117,0,11.500,2821.000,127.500,-8.640,0.015,152,14.000,54500 2006.223.07:10:39.73;drivev23,15.000,268,10.000,10.000,10.000 2006.223.07:10:39.73;head10,all,all,all,odd,adaptive,no,5.0000,1 2006.223.07:10:39.73;head11,131.5,16.4,-291.0,131.5,16.4,0.8,168.30,168.30 2006.223.07:10:39.73;head12,122.8,13.9,-150.8,122.8,14.7,2.5,167.61,167.61 2006.223.07:10:39.73;head20,all,all,all,odd,adaptive,no,5.0000,1 2006.223.07:10:39.73;head21,145.3,16.1,-209.3,137.2,16.1,58.9,165.28,165.28 2006.223.07:10:39.73;head22,157.5,17.4,-203.7,149.2,16.6,56.5,169.73,169.73 2006.223.07:10:39.73;time,-0.364,101.533,rate 2006.223.07:10:39.73;flagr,200 2006.223.07:10:39.73:" K06224 2006 TSUKUB32 T Ts 2006.223.07:10:39.73:" T TSUKUB32 AZEL .0000 180.0 14 10.0 710.0 180.0 14 5.0 88.0 32.0 Ts 108 2006.223.07:10:39.73:" Ts TSUKUB32 -3957408.75120 3310229.34660 3737494.83600 73452301 2006.223.07:10:39.73:" 108 TSUKUB32 14 17400 2006.223.07:10:39.73:" drudg version 050216 compiled under FS 9.7.07 2006.223.07:10:39.73:" Rack=K4-2/M4 Recorder 1=K5 Recorder 2=none 2006.223.07:10:39.73:exper_initi 2006.223.07:10:39.73&exper_initi/proc_library 2006.223.07:10:39.73&exper_initi/sched_initi 2006.223.07:10:39.73:!2006.224.06:29:50 2006.223.07:10:39.73&proc_library/" k06224 tsukub32 ts 2006.223.07:10:39.73&proc_library/" drudg version 050216 compiled under fs 9.7.7 2006.223.07:10:39.73&proc_library/"< k4-2/m4 rack >< k5 recorder 1> 2006.223.07:10:39.73&sched_initi/startcheck 2006.223.07:10:39.73&startcheck/sy=check_fsrun.pl & 2006.223.07:10:39.73&startcheck/" sy=/usr2/oper/temp/chmem.sh >& /dev/null & 2006.223.07:10:52.20;cable 2006.223.07:10:52.41/cable/+6.4050E-03 2006.223.07:11:40.63;cablelong 2006.223.07:11:40.86/cablelong/+6.9672E-03 2006.223.07:11:42.81;cablediff 2006.223.07:11:42.81/cablediff/562.2e-6,+ 2006.223.07:12:30.80;cable 2006.223.07:12:30.89/cable/+6.4042E-03 2006.223.07:12:46.19;wx 2006.223.07:12:46.20/wx/29.28,1005.1,85 2006.223.07:14:53.61;"Sky is cloudy. 2006.223.07:14:56.07;xfe 2006.223.07:14:56.16/xfe/off,on,15.7 2006.223.07:15:00.09;clockoff 2006.223.07:15:00.10&clockoff/"gps-fmout=1p 2006.223.07:15:00.10&clockoff/fmout-gps=1p 2006.223.07:15:01.08/fmout-gps/S +4.50E-07 2006.224.06:29:50.01:sy=/usr2/oper/k5/bin/freeze_chk.pl & 2006.224.06:29:50.04:!2006.224.07:19:50 2006.224.07:19:50.00:unstow 2006.224.07:19:50.00&unstow/antenna=e 2006.224.07:19:50.00&unstow/!+10s 2006.224.07:19:50.00&unstow/antenna=m2 2006.224.07:20:02.01:scan_name=224-0730,k06224,60 2006.224.07:20:02.01:source=3c418,203837.03,511912.7,2000.0,ccw 2006.224.07:20:02.01#antcn#PM 1 00019 2005 228 00 22 31 00 2006.224.07:20:02.01#antcn#PM 2 90.0000 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 2006.224.07:20:02.01#antcn#PM 2 -0.0279715 0.0000000 -0.0282214 -0.0241630 -0.0014011 2006.224.07:20:02.01#antcn#PM 3 -0.0059899 0.0042895 -0.0643783 0.0000000 0.0000000 2006.224.07:20:02.01#antcn#PM 4 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.224.07:20:02.01#antcn#PM 5 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.224.07:20:03.13:ready_k5 2006.224.07:20:03.13&ready_k5/obsinfo=st 2006.224.07:20:03.13&ready_k5/autoobs=1 2006.224.07:20:03.13&ready_k5/autoobs=2 2006.224.07:20:03.13&ready_k5/autoobs=3 2006.224.07:20:03.13&ready_k5/autoobs=4 2006.224.07:20:03.13&ready_k5/obsinfo 2006.224.07:20:03.13/obsinfo=st/error_log.tmp was not found (or not removed). 2006.224.07:20:03.13#flagr#flagr/antenna,new-source 2006.224.07:20:06.32/autoobs//k5ts1/ autoobs started! 2006.224.07:20:09.44/autoobs//k5ts2/ autoobs started! 2006.224.07:20:12.58/autoobs//k5ts3/ autoobs started! 2006.224.07:20:15.67/autoobs//k5ts4/ autoobs started! 2006.224.07:20:15.70/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.224.07:20:15.70:4f8m12a=1 2006.224.07:20:15.70&4f8m12a/xlog=on 2006.224.07:20:15.70&4f8m12a/echo=on 2006.224.07:20:15.70&4f8m12a/pcalon 2006.224.07:20:15.70&4f8m12a/"tpicd=stop 2006.224.07:20:15.70&4f8m12a/vc4f8 2006.224.07:20:15.70&4f8m12a/ifd4f 2006.224.07:20:15.70&4f8m12a/"form=m,16.000,1:2 2006.224.07:20:15.70&4f8m12a/"tpicd 2006.224.07:20:15.70&4f8m12a/echo=off 2006.224.07:20:15.70&4f8m12a/xlog=off 2006.224.07:20:15.70$4f8m12a/echo=on 2006.224.07:20:15.70$4f8m12a/pcalon 2006.224.07:20:15.70&pcalon/"no phase cal control is implemented here 2006.224.07:20:15.70$pcalon/"no phase cal control is implemented here 2006.224.07:20:15.70$4f8m12a/"tpicd=stop 2006.224.07:20:15.70$4f8m12a/vc4f8 2006.224.07:20:15.70&vc4f8/valo=1,532.99 2006.224.07:20:15.70&vc4f8/va=1,8 2006.224.07:20:15.70&vc4f8/valo=2,572.99 2006.224.07:20:15.70&vc4f8/va=2,7 2006.224.07:20:15.70&vc4f8/valo=3,672.99 2006.224.07:20:15.70&vc4f8/va=3,6 2006.224.07:20:15.70&vc4f8/valo=4,832.99 2006.224.07:20:15.70&vc4f8/va=4,7 2006.224.07:20:15.70&vc4f8/valo=5,652.99 2006.224.07:20:15.70&vc4f8/va=5,7 2006.224.07:20:15.70&vc4f8/valo=6,772.99 2006.224.07:20:15.70&vc4f8/va=6,6 2006.224.07:20:15.70&vc4f8/valo=7,832.99 2006.224.07:20:15.70&vc4f8/va=7,6 2006.224.07:20:15.70&vc4f8/valo=8,852.99 2006.224.07:20:15.70&vc4f8/va=8,7 2006.224.07:20:15.70&vc4f8/vblo=1,632.99 2006.224.07:20:15.70&vc4f8/vb=1,4 2006.224.07:20:15.70&vc4f8/vblo=2,640.99 2006.224.07:20:15.70&vc4f8/vb=2,4 2006.224.07:20:15.70&vc4f8/vblo=3,656.99 2006.224.07:20:15.70&vc4f8/vb=3,4 2006.224.07:20:15.70&vc4f8/vblo=4,712.99 2006.224.07:20:15.70&vc4f8/vb=4,4 2006.224.07:20:15.70&vc4f8/vblo=5,744.99 2006.224.07:20:15.70&vc4f8/vb=5,4 2006.224.07:20:15.70&vc4f8/vblo=6,752.99 2006.224.07:20:15.70&vc4f8/vb=6,4 2006.224.07:20:15.70&vc4f8/vabw=wide 2006.224.07:20:15.70&vc4f8/vbbw=wide 2006.224.07:20:15.70$vc4f8/valo=1,532.99 2006.224.07:20:15.70#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.224.07:20:15.70#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.224.07:20:15.70#ibcon#ireg 17 cls_cnt 0 2006.224.07:20:15.70#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.224.07:20:15.70#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.224.07:20:15.70#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.224.07:20:15.70#ibcon#enter wrdev, iclass 18, count 0 2006.224.07:20:15.70#ibcon#first serial, iclass 18, count 0 2006.224.07:20:15.70#ibcon#enter sib2, iclass 18, count 0 2006.224.07:20:15.70#ibcon#flushed, iclass 18, count 0 2006.224.07:20:15.70#ibcon#about to write, iclass 18, count 0 2006.224.07:20:15.70#ibcon#wrote, iclass 18, count 0 2006.224.07:20:15.70#ibcon#about to read 3, iclass 18, count 0 2006.224.07:20:15.74#ibcon#read 3, iclass 18, count 0 2006.224.07:20:15.74#ibcon#about to read 4, iclass 18, count 0 2006.224.07:20:15.74#ibcon#read 4, iclass 18, count 0 2006.224.07:20:15.74#ibcon#about to read 5, iclass 18, count 0 2006.224.07:20:15.74#ibcon#read 5, iclass 18, count 0 2006.224.07:20:15.74#ibcon#about to read 6, iclass 18, count 0 2006.224.07:20:15.74#ibcon#read 6, iclass 18, count 0 2006.224.07:20:15.74#ibcon#end of sib2, iclass 18, count 0 2006.224.07:20:15.74#ibcon#*mode == 0, iclass 18, count 0 2006.224.07:20:15.74#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.224.07:20:15.74#ibcon#[26=FRQ=01,532.99\r\n] 2006.224.07:20:15.74#ibcon#*before write, iclass 18, count 0 2006.224.07:20:15.74#ibcon#enter sib2, iclass 18, count 0 2006.224.07:20:15.74#ibcon#flushed, iclass 18, count 0 2006.224.07:20:15.74#ibcon#about to write, iclass 18, count 0 2006.224.07:20:15.74#ibcon#wrote, iclass 18, count 0 2006.224.07:20:15.74#ibcon#about to read 3, iclass 18, count 0 2006.224.07:20:15.80#ibcon#read 3, iclass 18, count 0 2006.224.07:20:15.80#ibcon#about to read 4, iclass 18, count 0 2006.224.07:20:15.80#ibcon#read 4, iclass 18, count 0 2006.224.07:20:15.80#ibcon#about to read 5, iclass 18, count 0 2006.224.07:20:15.80#ibcon#read 5, iclass 18, count 0 2006.224.07:20:15.80#ibcon#about to read 6, iclass 18, count 0 2006.224.07:20:15.80#ibcon#read 6, iclass 18, count 0 2006.224.07:20:15.80#ibcon#end of sib2, iclass 18, count 0 2006.224.07:20:15.80#ibcon#*after write, iclass 18, count 0 2006.224.07:20:15.80#ibcon#*before return 0, iclass 18, count 0 2006.224.07:20:15.80#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.224.07:20:15.80#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.224.07:20:15.80#ibcon#about to clear, iclass 18 cls_cnt 0 2006.224.07:20:15.80#ibcon#cleared, iclass 18 cls_cnt 0 2006.224.07:20:15.80$vc4f8/va=1,8 2006.224.07:20:15.80#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.224.07:20:15.80#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.224.07:20:15.80#ibcon#ireg 11 cls_cnt 2 2006.224.07:20:15.80#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.224.07:20:15.80#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.224.07:20:15.80#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.224.07:20:15.80#ibcon#enter wrdev, iclass 20, count 2 2006.224.07:20:15.80#ibcon#first serial, iclass 20, count 2 2006.224.07:20:15.80#ibcon#enter sib2, iclass 20, count 2 2006.224.07:20:15.80#ibcon#flushed, iclass 20, count 2 2006.224.07:20:15.80#ibcon#about to write, iclass 20, count 2 2006.224.07:20:15.80#ibcon#wrote, iclass 20, count 2 2006.224.07:20:15.80#ibcon#about to read 3, iclass 20, count 2 2006.224.07:20:15.82#ibcon#read 3, iclass 20, count 2 2006.224.07:20:15.82#ibcon#about to read 4, iclass 20, count 2 2006.224.07:20:15.82#ibcon#read 4, iclass 20, count 2 2006.224.07:20:15.82#ibcon#about to read 5, iclass 20, count 2 2006.224.07:20:15.82#ibcon#read 5, iclass 20, count 2 2006.224.07:20:15.82#ibcon#about to read 6, iclass 20, count 2 2006.224.07:20:15.82#ibcon#read 6, iclass 20, count 2 2006.224.07:20:15.82#ibcon#end of sib2, iclass 20, count 2 2006.224.07:20:15.82#ibcon#*mode == 0, iclass 20, count 2 2006.224.07:20:15.82#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.224.07:20:15.82#ibcon#[25=AT01-08\r\n] 2006.224.07:20:15.82#ibcon#*before write, iclass 20, count 2 2006.224.07:20:15.82#ibcon#enter sib2, iclass 20, count 2 2006.224.07:20:15.82#ibcon#flushed, iclass 20, count 2 2006.224.07:20:15.82#ibcon#about to write, iclass 20, count 2 2006.224.07:20:15.82#ibcon#wrote, iclass 20, count 2 2006.224.07:20:15.82#ibcon#about to read 3, iclass 20, count 2 2006.224.07:20:15.86#ibcon#read 3, iclass 20, count 2 2006.224.07:20:15.86#ibcon#about to read 4, iclass 20, count 2 2006.224.07:20:15.86#ibcon#read 4, iclass 20, count 2 2006.224.07:20:15.86#ibcon#about to read 5, iclass 20, count 2 2006.224.07:20:15.86#ibcon#read 5, iclass 20, count 2 2006.224.07:20:15.86#ibcon#about to read 6, iclass 20, count 2 2006.224.07:20:15.86#ibcon#read 6, iclass 20, count 2 2006.224.07:20:15.86#ibcon#end of sib2, iclass 20, count 2 2006.224.07:20:15.86#ibcon#*after write, iclass 20, count 2 2006.224.07:20:15.86#ibcon#*before return 0, iclass 20, count 2 2006.224.07:20:15.86#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.224.07:20:15.86#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.224.07:20:15.86#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.224.07:20:15.86#ibcon#ireg 7 cls_cnt 0 2006.224.07:20:15.86#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.224.07:20:15.98#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.224.07:20:15.98#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.224.07:20:15.98#ibcon#enter wrdev, iclass 20, count 0 2006.224.07:20:15.98#ibcon#first serial, iclass 20, count 0 2006.224.07:20:15.98#ibcon#enter sib2, iclass 20, count 0 2006.224.07:20:15.98#ibcon#flushed, iclass 20, count 0 2006.224.07:20:15.98#ibcon#about to write, iclass 20, count 0 2006.224.07:20:15.98#ibcon#wrote, iclass 20, count 0 2006.224.07:20:15.98#ibcon#about to read 3, iclass 20, count 0 2006.224.07:20:16.00#ibcon#read 3, iclass 20, count 0 2006.224.07:20:16.00#ibcon#about to read 4, iclass 20, count 0 2006.224.07:20:16.00#ibcon#read 4, iclass 20, count 0 2006.224.07:20:16.00#ibcon#about to read 5, iclass 20, count 0 2006.224.07:20:16.00#ibcon#read 5, iclass 20, count 0 2006.224.07:20:16.00#ibcon#about to read 6, iclass 20, count 0 2006.224.07:20:16.00#ibcon#read 6, iclass 20, count 0 2006.224.07:20:16.00#ibcon#end of sib2, iclass 20, count 0 2006.224.07:20:16.00#ibcon#*mode == 0, iclass 20, count 0 2006.224.07:20:16.00#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.224.07:20:16.00#ibcon#[25=USB\r\n] 2006.224.07:20:16.00#ibcon#*before write, iclass 20, count 0 2006.224.07:20:16.00#ibcon#enter sib2, iclass 20, count 0 2006.224.07:20:16.00#ibcon#flushed, iclass 20, count 0 2006.224.07:20:16.00#ibcon#about to write, iclass 20, count 0 2006.224.07:20:16.00#ibcon#wrote, iclass 20, count 0 2006.224.07:20:16.00#ibcon#about to read 3, iclass 20, count 0 2006.224.07:20:16.03#ibcon#read 3, iclass 20, count 0 2006.224.07:20:16.03#ibcon#about to read 4, iclass 20, count 0 2006.224.07:20:16.03#ibcon#read 4, iclass 20, count 0 2006.224.07:20:16.03#ibcon#about to read 5, iclass 20, count 0 2006.224.07:20:16.03#ibcon#read 5, iclass 20, count 0 2006.224.07:20:16.03#ibcon#about to read 6, iclass 20, count 0 2006.224.07:20:16.03#ibcon#read 6, iclass 20, count 0 2006.224.07:20:16.03#ibcon#end of sib2, iclass 20, count 0 2006.224.07:20:16.03#ibcon#*after write, iclass 20, count 0 2006.224.07:20:16.03#ibcon#*before return 0, iclass 20, count 0 2006.224.07:20:16.03#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.224.07:20:16.03#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.224.07:20:16.03#ibcon#about to clear, iclass 20 cls_cnt 0 2006.224.07:20:16.03#ibcon#cleared, iclass 20 cls_cnt 0 2006.224.07:20:16.03$vc4f8/valo=2,572.99 2006.224.07:20:16.03#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.224.07:20:16.03#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.224.07:20:16.03#ibcon#ireg 17 cls_cnt 0 2006.224.07:20:16.03#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.224.07:20:16.03#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.224.07:20:16.03#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.224.07:20:16.03#ibcon#enter wrdev, iclass 22, count 0 2006.224.07:20:16.03#ibcon#first serial, iclass 22, count 0 2006.224.07:20:16.03#ibcon#enter sib2, iclass 22, count 0 2006.224.07:20:16.03#ibcon#flushed, iclass 22, count 0 2006.224.07:20:16.03#ibcon#about to write, iclass 22, count 0 2006.224.07:20:16.03#ibcon#wrote, iclass 22, count 0 2006.224.07:20:16.03#ibcon#about to read 3, iclass 22, count 0 2006.224.07:20:16.06#ibcon#read 3, iclass 22, count 0 2006.224.07:20:16.06#ibcon#about to read 4, iclass 22, count 0 2006.224.07:20:16.06#ibcon#read 4, iclass 22, count 0 2006.224.07:20:16.06#ibcon#about to read 5, iclass 22, count 0 2006.224.07:20:16.06#ibcon#read 5, iclass 22, count 0 2006.224.07:20:16.06#ibcon#about to read 6, iclass 22, count 0 2006.224.07:20:16.06#ibcon#read 6, iclass 22, count 0 2006.224.07:20:16.06#ibcon#end of sib2, iclass 22, count 0 2006.224.07:20:16.06#ibcon#*mode == 0, iclass 22, count 0 2006.224.07:20:16.06#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.224.07:20:16.06#ibcon#[26=FRQ=02,572.99\r\n] 2006.224.07:20:16.06#ibcon#*before write, iclass 22, count 0 2006.224.07:20:16.06#ibcon#enter sib2, iclass 22, count 0 2006.224.07:20:16.06#ibcon#flushed, iclass 22, count 0 2006.224.07:20:16.06#ibcon#about to write, iclass 22, count 0 2006.224.07:20:16.06#ibcon#wrote, iclass 22, count 0 2006.224.07:20:16.06#ibcon#about to read 3, iclass 22, count 0 2006.224.07:20:16.10#ibcon#read 3, iclass 22, count 0 2006.224.07:20:16.10#ibcon#about to read 4, iclass 22, count 0 2006.224.07:20:16.10#ibcon#read 4, iclass 22, count 0 2006.224.07:20:16.10#ibcon#about to read 5, iclass 22, count 0 2006.224.07:20:16.10#ibcon#read 5, iclass 22, count 0 2006.224.07:20:16.10#ibcon#about to read 6, iclass 22, count 0 2006.224.07:20:16.10#ibcon#read 6, iclass 22, count 0 2006.224.07:20:16.10#ibcon#end of sib2, iclass 22, count 0 2006.224.07:20:16.10#ibcon#*after write, iclass 22, count 0 2006.224.07:20:16.10#ibcon#*before return 0, iclass 22, count 0 2006.224.07:20:16.10#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.224.07:20:16.10#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.224.07:20:16.10#ibcon#about to clear, iclass 22 cls_cnt 0 2006.224.07:20:16.10#ibcon#cleared, iclass 22 cls_cnt 0 2006.224.07:20:16.10$vc4f8/va=2,7 2006.224.07:20:16.10#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.224.07:20:16.10#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.224.07:20:16.10#ibcon#ireg 11 cls_cnt 2 2006.224.07:20:16.10#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.224.07:20:16.15#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.224.07:20:16.15#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.224.07:20:16.15#ibcon#enter wrdev, iclass 24, count 2 2006.224.07:20:16.15#ibcon#first serial, iclass 24, count 2 2006.224.07:20:16.15#ibcon#enter sib2, iclass 24, count 2 2006.224.07:20:16.15#ibcon#flushed, iclass 24, count 2 2006.224.07:20:16.15#ibcon#about to write, iclass 24, count 2 2006.224.07:20:16.15#ibcon#wrote, iclass 24, count 2 2006.224.07:20:16.15#ibcon#about to read 3, iclass 24, count 2 2006.224.07:20:16.17#ibcon#read 3, iclass 24, count 2 2006.224.07:20:16.17#ibcon#about to read 4, iclass 24, count 2 2006.224.07:20:16.17#ibcon#read 4, iclass 24, count 2 2006.224.07:20:16.17#ibcon#about to read 5, iclass 24, count 2 2006.224.07:20:16.17#ibcon#read 5, iclass 24, count 2 2006.224.07:20:16.17#ibcon#about to read 6, iclass 24, count 2 2006.224.07:20:16.17#ibcon#read 6, iclass 24, count 2 2006.224.07:20:16.17#ibcon#end of sib2, iclass 24, count 2 2006.224.07:20:16.17#ibcon#*mode == 0, iclass 24, count 2 2006.224.07:20:16.17#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.224.07:20:16.17#ibcon#[25=AT02-07\r\n] 2006.224.07:20:16.17#ibcon#*before write, iclass 24, count 2 2006.224.07:20:16.17#ibcon#enter sib2, iclass 24, count 2 2006.224.07:20:16.17#ibcon#flushed, iclass 24, count 2 2006.224.07:20:16.17#ibcon#about to write, iclass 24, count 2 2006.224.07:20:16.17#ibcon#wrote, iclass 24, count 2 2006.224.07:20:16.17#ibcon#about to read 3, iclass 24, count 2 2006.224.07:20:16.20#ibcon#read 3, iclass 24, count 2 2006.224.07:20:16.20#ibcon#about to read 4, iclass 24, count 2 2006.224.07:20:16.20#ibcon#read 4, iclass 24, count 2 2006.224.07:20:16.20#ibcon#about to read 5, iclass 24, count 2 2006.224.07:20:16.20#ibcon#read 5, iclass 24, count 2 2006.224.07:20:16.20#ibcon#about to read 6, iclass 24, count 2 2006.224.07:20:16.20#ibcon#read 6, iclass 24, count 2 2006.224.07:20:16.20#ibcon#end of sib2, iclass 24, count 2 2006.224.07:20:16.20#ibcon#*after write, iclass 24, count 2 2006.224.07:20:16.20#ibcon#*before return 0, iclass 24, count 2 2006.224.07:20:16.20#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.224.07:20:16.20#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.224.07:20:16.20#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.224.07:20:16.20#ibcon#ireg 7 cls_cnt 0 2006.224.07:20:16.20#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.224.07:20:16.32#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.224.07:20:16.32#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.224.07:20:16.32#ibcon#enter wrdev, iclass 24, count 0 2006.224.07:20:16.32#ibcon#first serial, iclass 24, count 0 2006.224.07:20:16.32#ibcon#enter sib2, iclass 24, count 0 2006.224.07:20:16.32#ibcon#flushed, iclass 24, count 0 2006.224.07:20:16.32#ibcon#about to write, iclass 24, count 0 2006.224.07:20:16.32#ibcon#wrote, iclass 24, count 0 2006.224.07:20:16.32#ibcon#about to read 3, iclass 24, count 0 2006.224.07:20:16.34#ibcon#read 3, iclass 24, count 0 2006.224.07:20:16.34#ibcon#about to read 4, iclass 24, count 0 2006.224.07:20:16.34#ibcon#read 4, iclass 24, count 0 2006.224.07:20:16.34#ibcon#about to read 5, iclass 24, count 0 2006.224.07:20:16.34#ibcon#read 5, iclass 24, count 0 2006.224.07:20:16.34#ibcon#about to read 6, iclass 24, count 0 2006.224.07:20:16.34#ibcon#read 6, iclass 24, count 0 2006.224.07:20:16.34#ibcon#end of sib2, iclass 24, count 0 2006.224.07:20:16.34#ibcon#*mode == 0, iclass 24, count 0 2006.224.07:20:16.34#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.224.07:20:16.34#ibcon#[25=USB\r\n] 2006.224.07:20:16.34#ibcon#*before write, iclass 24, count 0 2006.224.07:20:16.34#ibcon#enter sib2, iclass 24, count 0 2006.224.07:20:16.34#ibcon#flushed, iclass 24, count 0 2006.224.07:20:16.34#ibcon#about to write, iclass 24, count 0 2006.224.07:20:16.34#ibcon#wrote, iclass 24, count 0 2006.224.07:20:16.34#ibcon#about to read 3, iclass 24, count 0 2006.224.07:20:16.37#ibcon#read 3, iclass 24, count 0 2006.224.07:20:16.37#ibcon#about to read 4, iclass 24, count 0 2006.224.07:20:16.37#ibcon#read 4, iclass 24, count 0 2006.224.07:20:16.37#ibcon#about to read 5, iclass 24, count 0 2006.224.07:20:16.37#ibcon#read 5, iclass 24, count 0 2006.224.07:20:16.37#ibcon#about to read 6, iclass 24, count 0 2006.224.07:20:16.37#ibcon#read 6, iclass 24, count 0 2006.224.07:20:16.37#ibcon#end of sib2, iclass 24, count 0 2006.224.07:20:16.37#ibcon#*after write, iclass 24, count 0 2006.224.07:20:16.37#ibcon#*before return 0, iclass 24, count 0 2006.224.07:20:16.37#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.224.07:20:16.37#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.224.07:20:16.37#ibcon#about to clear, iclass 24 cls_cnt 0 2006.224.07:20:16.37#ibcon#cleared, iclass 24 cls_cnt 0 2006.224.07:20:16.37$vc4f8/valo=3,672.99 2006.224.07:20:16.37#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.224.07:20:16.37#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.224.07:20:16.37#ibcon#ireg 17 cls_cnt 0 2006.224.07:20:16.37#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.224.07:20:16.37#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.224.07:20:16.37#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.224.07:20:16.37#ibcon#enter wrdev, iclass 26, count 0 2006.224.07:20:16.37#ibcon#first serial, iclass 26, count 0 2006.224.07:20:16.37#ibcon#enter sib2, iclass 26, count 0 2006.224.07:20:16.37#ibcon#flushed, iclass 26, count 0 2006.224.07:20:16.37#ibcon#about to write, iclass 26, count 0 2006.224.07:20:16.37#ibcon#wrote, iclass 26, count 0 2006.224.07:20:16.37#ibcon#about to read 3, iclass 26, count 0 2006.224.07:20:16.40#ibcon#read 3, iclass 26, count 0 2006.224.07:20:16.40#ibcon#about to read 4, iclass 26, count 0 2006.224.07:20:16.40#ibcon#read 4, iclass 26, count 0 2006.224.07:20:16.40#ibcon#about to read 5, iclass 26, count 0 2006.224.07:20:16.40#ibcon#read 5, iclass 26, count 0 2006.224.07:20:16.40#ibcon#about to read 6, iclass 26, count 0 2006.224.07:20:16.40#ibcon#read 6, iclass 26, count 0 2006.224.07:20:16.40#ibcon#end of sib2, iclass 26, count 0 2006.224.07:20:16.40#ibcon#*mode == 0, iclass 26, count 0 2006.224.07:20:16.40#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.224.07:20:16.40#ibcon#[26=FRQ=03,672.99\r\n] 2006.224.07:20:16.40#ibcon#*before write, iclass 26, count 0 2006.224.07:20:16.40#ibcon#enter sib2, iclass 26, count 0 2006.224.07:20:16.40#ibcon#flushed, iclass 26, count 0 2006.224.07:20:16.40#ibcon#about to write, iclass 26, count 0 2006.224.07:20:16.40#ibcon#wrote, iclass 26, count 0 2006.224.07:20:16.40#ibcon#about to read 3, iclass 26, count 0 2006.224.07:20:16.44#ibcon#read 3, iclass 26, count 0 2006.224.07:20:16.44#ibcon#about to read 4, iclass 26, count 0 2006.224.07:20:16.44#ibcon#read 4, iclass 26, count 0 2006.224.07:20:16.44#ibcon#about to read 5, iclass 26, count 0 2006.224.07:20:16.44#ibcon#read 5, iclass 26, count 0 2006.224.07:20:16.44#ibcon#about to read 6, iclass 26, count 0 2006.224.07:20:16.44#ibcon#read 6, iclass 26, count 0 2006.224.07:20:16.44#ibcon#end of sib2, iclass 26, count 0 2006.224.07:20:16.44#ibcon#*after write, iclass 26, count 0 2006.224.07:20:16.44#ibcon#*before return 0, iclass 26, count 0 2006.224.07:20:16.44#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.224.07:20:16.44#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.224.07:20:16.44#ibcon#about to clear, iclass 26 cls_cnt 0 2006.224.07:20:16.44#ibcon#cleared, iclass 26 cls_cnt 0 2006.224.07:20:16.44$vc4f8/va=3,6 2006.224.07:20:16.44#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.224.07:20:16.44#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.224.07:20:16.44#ibcon#ireg 11 cls_cnt 2 2006.224.07:20:16.44#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.224.07:20:16.49#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.224.07:20:16.49#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.224.07:20:16.49#ibcon#enter wrdev, iclass 28, count 2 2006.224.07:20:16.49#ibcon#first serial, iclass 28, count 2 2006.224.07:20:16.49#ibcon#enter sib2, iclass 28, count 2 2006.224.07:20:16.49#ibcon#flushed, iclass 28, count 2 2006.224.07:20:16.49#ibcon#about to write, iclass 28, count 2 2006.224.07:20:16.49#ibcon#wrote, iclass 28, count 2 2006.224.07:20:16.49#ibcon#about to read 3, iclass 28, count 2 2006.224.07:20:16.51#ibcon#read 3, iclass 28, count 2 2006.224.07:20:16.51#ibcon#about to read 4, iclass 28, count 2 2006.224.07:20:16.51#ibcon#read 4, iclass 28, count 2 2006.224.07:20:16.51#ibcon#about to read 5, iclass 28, count 2 2006.224.07:20:16.51#ibcon#read 5, iclass 28, count 2 2006.224.07:20:16.51#ibcon#about to read 6, iclass 28, count 2 2006.224.07:20:16.51#ibcon#read 6, iclass 28, count 2 2006.224.07:20:16.51#ibcon#end of sib2, iclass 28, count 2 2006.224.07:20:16.51#ibcon#*mode == 0, iclass 28, count 2 2006.224.07:20:16.51#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.224.07:20:16.51#ibcon#[25=AT03-06\r\n] 2006.224.07:20:16.51#ibcon#*before write, iclass 28, count 2 2006.224.07:20:16.51#ibcon#enter sib2, iclass 28, count 2 2006.224.07:20:16.51#ibcon#flushed, iclass 28, count 2 2006.224.07:20:16.51#ibcon#about to write, iclass 28, count 2 2006.224.07:20:16.51#ibcon#wrote, iclass 28, count 2 2006.224.07:20:16.51#ibcon#about to read 3, iclass 28, count 2 2006.224.07:20:16.54#ibcon#read 3, iclass 28, count 2 2006.224.07:20:16.54#ibcon#about to read 4, iclass 28, count 2 2006.224.07:20:16.54#ibcon#read 4, iclass 28, count 2 2006.224.07:20:16.54#ibcon#about to read 5, iclass 28, count 2 2006.224.07:20:16.54#ibcon#read 5, iclass 28, count 2 2006.224.07:20:16.54#ibcon#about to read 6, iclass 28, count 2 2006.224.07:20:16.54#ibcon#read 6, iclass 28, count 2 2006.224.07:20:16.54#ibcon#end of sib2, iclass 28, count 2 2006.224.07:20:16.54#ibcon#*after write, iclass 28, count 2 2006.224.07:20:16.54#ibcon#*before return 0, iclass 28, count 2 2006.224.07:20:16.54#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.224.07:20:16.54#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.224.07:20:16.54#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.224.07:20:16.54#ibcon#ireg 7 cls_cnt 0 2006.224.07:20:16.54#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.224.07:20:16.66#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.224.07:20:16.66#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.224.07:20:16.66#ibcon#enter wrdev, iclass 28, count 0 2006.224.07:20:16.66#ibcon#first serial, iclass 28, count 0 2006.224.07:20:16.66#ibcon#enter sib2, iclass 28, count 0 2006.224.07:20:16.66#ibcon#flushed, iclass 28, count 0 2006.224.07:20:16.66#ibcon#about to write, iclass 28, count 0 2006.224.07:20:16.66#ibcon#wrote, iclass 28, count 0 2006.224.07:20:16.66#ibcon#about to read 3, iclass 28, count 0 2006.224.07:20:16.68#ibcon#read 3, iclass 28, count 0 2006.224.07:20:16.68#ibcon#about to read 4, iclass 28, count 0 2006.224.07:20:16.68#ibcon#read 4, iclass 28, count 0 2006.224.07:20:16.68#ibcon#about to read 5, iclass 28, count 0 2006.224.07:20:16.68#ibcon#read 5, iclass 28, count 0 2006.224.07:20:16.68#ibcon#about to read 6, iclass 28, count 0 2006.224.07:20:16.68#ibcon#read 6, iclass 28, count 0 2006.224.07:20:16.68#ibcon#end of sib2, iclass 28, count 0 2006.224.07:20:16.68#ibcon#*mode == 0, iclass 28, count 0 2006.224.07:20:16.68#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.224.07:20:16.68#ibcon#[25=USB\r\n] 2006.224.07:20:16.68#ibcon#*before write, iclass 28, count 0 2006.224.07:20:16.68#ibcon#enter sib2, iclass 28, count 0 2006.224.07:20:16.68#ibcon#flushed, iclass 28, count 0 2006.224.07:20:16.68#ibcon#about to write, iclass 28, count 0 2006.224.07:20:16.68#ibcon#wrote, iclass 28, count 0 2006.224.07:20:16.68#ibcon#about to read 3, iclass 28, count 0 2006.224.07:20:16.71#ibcon#read 3, iclass 28, count 0 2006.224.07:20:16.71#ibcon#about to read 4, iclass 28, count 0 2006.224.07:20:16.71#ibcon#read 4, iclass 28, count 0 2006.224.07:20:16.71#ibcon#about to read 5, iclass 28, count 0 2006.224.07:20:16.71#ibcon#read 5, iclass 28, count 0 2006.224.07:20:16.71#ibcon#about to read 6, iclass 28, count 0 2006.224.07:20:16.71#ibcon#read 6, iclass 28, count 0 2006.224.07:20:16.71#ibcon#end of sib2, iclass 28, count 0 2006.224.07:20:16.71#ibcon#*after write, iclass 28, count 0 2006.224.07:20:16.71#ibcon#*before return 0, iclass 28, count 0 2006.224.07:20:16.71#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.224.07:20:16.71#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.224.07:20:16.71#ibcon#about to clear, iclass 28 cls_cnt 0 2006.224.07:20:16.71#ibcon#cleared, iclass 28 cls_cnt 0 2006.224.07:20:16.71$vc4f8/valo=4,832.99 2006.224.07:20:16.71#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.224.07:20:16.71#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.224.07:20:16.71#ibcon#ireg 17 cls_cnt 0 2006.224.07:20:16.71#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.224.07:20:16.71#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.224.07:20:16.71#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.224.07:20:16.71#ibcon#enter wrdev, iclass 30, count 0 2006.224.07:20:16.71#ibcon#first serial, iclass 30, count 0 2006.224.07:20:16.71#ibcon#enter sib2, iclass 30, count 0 2006.224.07:20:16.71#ibcon#flushed, iclass 30, count 0 2006.224.07:20:16.71#ibcon#about to write, iclass 30, count 0 2006.224.07:20:16.71#ibcon#wrote, iclass 30, count 0 2006.224.07:20:16.71#ibcon#about to read 3, iclass 30, count 0 2006.224.07:20:16.73#ibcon#read 3, iclass 30, count 0 2006.224.07:20:16.73#ibcon#about to read 4, iclass 30, count 0 2006.224.07:20:16.73#ibcon#read 4, iclass 30, count 0 2006.224.07:20:16.73#ibcon#about to read 5, iclass 30, count 0 2006.224.07:20:16.73#ibcon#read 5, iclass 30, count 0 2006.224.07:20:16.73#ibcon#about to read 6, iclass 30, count 0 2006.224.07:20:16.73#ibcon#read 6, iclass 30, count 0 2006.224.07:20:16.73#ibcon#end of sib2, iclass 30, count 0 2006.224.07:20:16.73#ibcon#*mode == 0, iclass 30, count 0 2006.224.07:20:16.73#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.224.07:20:16.73#ibcon#[26=FRQ=04,832.99\r\n] 2006.224.07:20:16.73#ibcon#*before write, iclass 30, count 0 2006.224.07:20:16.73#ibcon#enter sib2, iclass 30, count 0 2006.224.07:20:16.73#ibcon#flushed, iclass 30, count 0 2006.224.07:20:16.73#ibcon#about to write, iclass 30, count 0 2006.224.07:20:16.73#ibcon#wrote, iclass 30, count 0 2006.224.07:20:16.73#ibcon#about to read 3, iclass 30, count 0 2006.224.07:20:16.77#ibcon#read 3, iclass 30, count 0 2006.224.07:20:16.77#ibcon#about to read 4, iclass 30, count 0 2006.224.07:20:16.77#ibcon#read 4, iclass 30, count 0 2006.224.07:20:16.77#ibcon#about to read 5, iclass 30, count 0 2006.224.07:20:16.77#ibcon#read 5, iclass 30, count 0 2006.224.07:20:16.77#ibcon#about to read 6, iclass 30, count 0 2006.224.07:20:16.77#ibcon#read 6, iclass 30, count 0 2006.224.07:20:16.77#ibcon#end of sib2, iclass 30, count 0 2006.224.07:20:16.77#ibcon#*after write, iclass 30, count 0 2006.224.07:20:16.77#ibcon#*before return 0, iclass 30, count 0 2006.224.07:20:16.77#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.224.07:20:16.77#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.224.07:20:16.77#ibcon#about to clear, iclass 30 cls_cnt 0 2006.224.07:20:16.77#ibcon#cleared, iclass 30 cls_cnt 0 2006.224.07:20:16.77$vc4f8/va=4,7 2006.224.07:20:16.77#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.224.07:20:16.77#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.224.07:20:16.77#ibcon#ireg 11 cls_cnt 2 2006.224.07:20:16.77#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.224.07:20:16.83#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.224.07:20:16.83#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.224.07:20:16.83#ibcon#enter wrdev, iclass 32, count 2 2006.224.07:20:16.83#ibcon#first serial, iclass 32, count 2 2006.224.07:20:16.83#ibcon#enter sib2, iclass 32, count 2 2006.224.07:20:16.83#ibcon#flushed, iclass 32, count 2 2006.224.07:20:16.83#ibcon#about to write, iclass 32, count 2 2006.224.07:20:16.83#ibcon#wrote, iclass 32, count 2 2006.224.07:20:16.83#ibcon#about to read 3, iclass 32, count 2 2006.224.07:20:16.85#ibcon#read 3, iclass 32, count 2 2006.224.07:20:16.85#ibcon#about to read 4, iclass 32, count 2 2006.224.07:20:16.85#ibcon#read 4, iclass 32, count 2 2006.224.07:20:16.85#ibcon#about to read 5, iclass 32, count 2 2006.224.07:20:16.85#ibcon#read 5, iclass 32, count 2 2006.224.07:20:16.85#ibcon#about to read 6, iclass 32, count 2 2006.224.07:20:16.85#ibcon#read 6, iclass 32, count 2 2006.224.07:20:16.85#ibcon#end of sib2, iclass 32, count 2 2006.224.07:20:16.85#ibcon#*mode == 0, iclass 32, count 2 2006.224.07:20:16.85#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.224.07:20:16.85#ibcon#[25=AT04-07\r\n] 2006.224.07:20:16.85#ibcon#*before write, iclass 32, count 2 2006.224.07:20:16.85#ibcon#enter sib2, iclass 32, count 2 2006.224.07:20:16.85#ibcon#flushed, iclass 32, count 2 2006.224.07:20:16.85#ibcon#about to write, iclass 32, count 2 2006.224.07:20:16.85#ibcon#wrote, iclass 32, count 2 2006.224.07:20:16.85#ibcon#about to read 3, iclass 32, count 2 2006.224.07:20:16.88#ibcon#read 3, iclass 32, count 2 2006.224.07:20:16.88#ibcon#about to read 4, iclass 32, count 2 2006.224.07:20:16.88#ibcon#read 4, iclass 32, count 2 2006.224.07:20:16.88#ibcon#about to read 5, iclass 32, count 2 2006.224.07:20:16.88#ibcon#read 5, iclass 32, count 2 2006.224.07:20:16.88#ibcon#about to read 6, iclass 32, count 2 2006.224.07:20:16.88#ibcon#read 6, iclass 32, count 2 2006.224.07:20:16.88#ibcon#end of sib2, iclass 32, count 2 2006.224.07:20:16.88#ibcon#*after write, iclass 32, count 2 2006.224.07:20:16.88#ibcon#*before return 0, iclass 32, count 2 2006.224.07:20:16.88#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.224.07:20:16.88#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.224.07:20:16.88#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.224.07:20:16.88#ibcon#ireg 7 cls_cnt 0 2006.224.07:20:16.88#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.224.07:20:17.00#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.224.07:20:17.00#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.224.07:20:17.00#ibcon#enter wrdev, iclass 32, count 0 2006.224.07:20:17.00#ibcon#first serial, iclass 32, count 0 2006.224.07:20:17.00#ibcon#enter sib2, iclass 32, count 0 2006.224.07:20:17.00#ibcon#flushed, iclass 32, count 0 2006.224.07:20:17.00#ibcon#about to write, iclass 32, count 0 2006.224.07:20:17.00#ibcon#wrote, iclass 32, count 0 2006.224.07:20:17.00#ibcon#about to read 3, iclass 32, count 0 2006.224.07:20:17.02#ibcon#read 3, iclass 32, count 0 2006.224.07:20:17.02#ibcon#about to read 4, iclass 32, count 0 2006.224.07:20:17.02#ibcon#read 4, iclass 32, count 0 2006.224.07:20:17.02#ibcon#about to read 5, iclass 32, count 0 2006.224.07:20:17.02#ibcon#read 5, iclass 32, count 0 2006.224.07:20:17.02#ibcon#about to read 6, iclass 32, count 0 2006.224.07:20:17.02#ibcon#read 6, iclass 32, count 0 2006.224.07:20:17.02#ibcon#end of sib2, iclass 32, count 0 2006.224.07:20:17.02#ibcon#*mode == 0, iclass 32, count 0 2006.224.07:20:17.02#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.224.07:20:17.02#ibcon#[25=USB\r\n] 2006.224.07:20:17.02#ibcon#*before write, iclass 32, count 0 2006.224.07:20:17.02#ibcon#enter sib2, iclass 32, count 0 2006.224.07:20:17.02#ibcon#flushed, iclass 32, count 0 2006.224.07:20:17.02#ibcon#about to write, iclass 32, count 0 2006.224.07:20:17.02#ibcon#wrote, iclass 32, count 0 2006.224.07:20:17.02#ibcon#about to read 3, iclass 32, count 0 2006.224.07:20:17.05#ibcon#read 3, iclass 32, count 0 2006.224.07:20:17.05#ibcon#about to read 4, iclass 32, count 0 2006.224.07:20:17.05#ibcon#read 4, iclass 32, count 0 2006.224.07:20:17.05#ibcon#about to read 5, iclass 32, count 0 2006.224.07:20:17.05#ibcon#read 5, iclass 32, count 0 2006.224.07:20:17.05#ibcon#about to read 6, iclass 32, count 0 2006.224.07:20:17.05#ibcon#read 6, iclass 32, count 0 2006.224.07:20:17.05#ibcon#end of sib2, iclass 32, count 0 2006.224.07:20:17.05#ibcon#*after write, iclass 32, count 0 2006.224.07:20:17.05#ibcon#*before return 0, iclass 32, count 0 2006.224.07:20:17.05#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.224.07:20:17.05#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.224.07:20:17.05#ibcon#about to clear, iclass 32 cls_cnt 0 2006.224.07:20:17.05#ibcon#cleared, iclass 32 cls_cnt 0 2006.224.07:20:17.05$vc4f8/valo=5,652.99 2006.224.07:20:17.05#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.224.07:20:17.05#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.224.07:20:17.05#ibcon#ireg 17 cls_cnt 0 2006.224.07:20:17.05#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.224.07:20:17.05#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.224.07:20:17.05#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.224.07:20:17.05#ibcon#enter wrdev, iclass 34, count 0 2006.224.07:20:17.05#ibcon#first serial, iclass 34, count 0 2006.224.07:20:17.05#ibcon#enter sib2, iclass 34, count 0 2006.224.07:20:17.05#ibcon#flushed, iclass 34, count 0 2006.224.07:20:17.05#ibcon#about to write, iclass 34, count 0 2006.224.07:20:17.05#ibcon#wrote, iclass 34, count 0 2006.224.07:20:17.05#ibcon#about to read 3, iclass 34, count 0 2006.224.07:20:17.07#ibcon#read 3, iclass 34, count 0 2006.224.07:20:17.07#ibcon#about to read 4, iclass 34, count 0 2006.224.07:20:17.07#ibcon#read 4, iclass 34, count 0 2006.224.07:20:17.07#ibcon#about to read 5, iclass 34, count 0 2006.224.07:20:17.07#ibcon#read 5, iclass 34, count 0 2006.224.07:20:17.07#ibcon#about to read 6, iclass 34, count 0 2006.224.07:20:17.07#ibcon#read 6, iclass 34, count 0 2006.224.07:20:17.07#ibcon#end of sib2, iclass 34, count 0 2006.224.07:20:17.07#ibcon#*mode == 0, iclass 34, count 0 2006.224.07:20:17.07#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.224.07:20:17.07#ibcon#[26=FRQ=05,652.99\r\n] 2006.224.07:20:17.07#ibcon#*before write, iclass 34, count 0 2006.224.07:20:17.07#ibcon#enter sib2, iclass 34, count 0 2006.224.07:20:17.07#ibcon#flushed, iclass 34, count 0 2006.224.07:20:17.07#ibcon#about to write, iclass 34, count 0 2006.224.07:20:17.07#ibcon#wrote, iclass 34, count 0 2006.224.07:20:17.07#ibcon#about to read 3, iclass 34, count 0 2006.224.07:20:17.11#ibcon#read 3, iclass 34, count 0 2006.224.07:20:17.11#ibcon#about to read 4, iclass 34, count 0 2006.224.07:20:17.11#ibcon#read 4, iclass 34, count 0 2006.224.07:20:17.11#ibcon#about to read 5, iclass 34, count 0 2006.224.07:20:17.11#ibcon#read 5, iclass 34, count 0 2006.224.07:20:17.11#ibcon#about to read 6, iclass 34, count 0 2006.224.07:20:17.11#ibcon#read 6, iclass 34, count 0 2006.224.07:20:17.11#ibcon#end of sib2, iclass 34, count 0 2006.224.07:20:17.11#ibcon#*after write, iclass 34, count 0 2006.224.07:20:17.11#ibcon#*before return 0, iclass 34, count 0 2006.224.07:20:17.11#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.224.07:20:17.11#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.224.07:20:17.11#ibcon#about to clear, iclass 34 cls_cnt 0 2006.224.07:20:17.11#ibcon#cleared, iclass 34 cls_cnt 0 2006.224.07:20:17.11$vc4f8/va=5,7 2006.224.07:20:17.11#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.224.07:20:17.11#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.224.07:20:17.11#ibcon#ireg 11 cls_cnt 2 2006.224.07:20:17.11#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.224.07:20:17.17#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.224.07:20:17.17#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.224.07:20:17.17#ibcon#enter wrdev, iclass 36, count 2 2006.224.07:20:17.17#ibcon#first serial, iclass 36, count 2 2006.224.07:20:17.17#ibcon#enter sib2, iclass 36, count 2 2006.224.07:20:17.17#ibcon#flushed, iclass 36, count 2 2006.224.07:20:17.17#ibcon#about to write, iclass 36, count 2 2006.224.07:20:17.17#ibcon#wrote, iclass 36, count 2 2006.224.07:20:17.17#ibcon#about to read 3, iclass 36, count 2 2006.224.07:20:17.19#ibcon#read 3, iclass 36, count 2 2006.224.07:20:17.19#ibcon#about to read 4, iclass 36, count 2 2006.224.07:20:17.19#ibcon#read 4, iclass 36, count 2 2006.224.07:20:17.19#ibcon#about to read 5, iclass 36, count 2 2006.224.07:20:17.19#ibcon#read 5, iclass 36, count 2 2006.224.07:20:17.19#ibcon#about to read 6, iclass 36, count 2 2006.224.07:20:17.19#ibcon#read 6, iclass 36, count 2 2006.224.07:20:17.19#ibcon#end of sib2, iclass 36, count 2 2006.224.07:20:17.19#ibcon#*mode == 0, iclass 36, count 2 2006.224.07:20:17.19#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.224.07:20:17.19#ibcon#[25=AT05-07\r\n] 2006.224.07:20:17.19#ibcon#*before write, iclass 36, count 2 2006.224.07:20:17.19#ibcon#enter sib2, iclass 36, count 2 2006.224.07:20:17.19#ibcon#flushed, iclass 36, count 2 2006.224.07:20:17.19#ibcon#about to write, iclass 36, count 2 2006.224.07:20:17.19#ibcon#wrote, iclass 36, count 2 2006.224.07:20:17.19#ibcon#about to read 3, iclass 36, count 2 2006.224.07:20:17.22#ibcon#read 3, iclass 36, count 2 2006.224.07:20:17.22#ibcon#about to read 4, iclass 36, count 2 2006.224.07:20:17.22#ibcon#read 4, iclass 36, count 2 2006.224.07:20:17.22#ibcon#about to read 5, iclass 36, count 2 2006.224.07:20:17.22#ibcon#read 5, iclass 36, count 2 2006.224.07:20:17.22#ibcon#about to read 6, iclass 36, count 2 2006.224.07:20:17.22#ibcon#read 6, iclass 36, count 2 2006.224.07:20:17.22#ibcon#end of sib2, iclass 36, count 2 2006.224.07:20:17.22#ibcon#*after write, iclass 36, count 2 2006.224.07:20:17.22#ibcon#*before return 0, iclass 36, count 2 2006.224.07:20:17.22#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.224.07:20:17.22#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.224.07:20:17.22#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.224.07:20:17.22#ibcon#ireg 7 cls_cnt 0 2006.224.07:20:17.22#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.224.07:20:17.34#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.224.07:20:17.34#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.224.07:20:17.34#ibcon#enter wrdev, iclass 36, count 0 2006.224.07:20:17.34#ibcon#first serial, iclass 36, count 0 2006.224.07:20:17.34#ibcon#enter sib2, iclass 36, count 0 2006.224.07:20:17.34#ibcon#flushed, iclass 36, count 0 2006.224.07:20:17.34#ibcon#about to write, iclass 36, count 0 2006.224.07:20:17.34#ibcon#wrote, iclass 36, count 0 2006.224.07:20:17.34#ibcon#about to read 3, iclass 36, count 0 2006.224.07:20:17.36#ibcon#read 3, iclass 36, count 0 2006.224.07:20:17.36#ibcon#about to read 4, iclass 36, count 0 2006.224.07:20:17.36#ibcon#read 4, iclass 36, count 0 2006.224.07:20:17.36#ibcon#about to read 5, iclass 36, count 0 2006.224.07:20:17.36#ibcon#read 5, iclass 36, count 0 2006.224.07:20:17.36#ibcon#about to read 6, iclass 36, count 0 2006.224.07:20:17.36#ibcon#read 6, iclass 36, count 0 2006.224.07:20:17.36#ibcon#end of sib2, iclass 36, count 0 2006.224.07:20:17.36#ibcon#*mode == 0, iclass 36, count 0 2006.224.07:20:17.36#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.224.07:20:17.36#ibcon#[25=USB\r\n] 2006.224.07:20:17.36#ibcon#*before write, iclass 36, count 0 2006.224.07:20:17.36#ibcon#enter sib2, iclass 36, count 0 2006.224.07:20:17.36#ibcon#flushed, iclass 36, count 0 2006.224.07:20:17.36#ibcon#about to write, iclass 36, count 0 2006.224.07:20:17.36#ibcon#wrote, iclass 36, count 0 2006.224.07:20:17.36#ibcon#about to read 3, iclass 36, count 0 2006.224.07:20:17.39#ibcon#read 3, iclass 36, count 0 2006.224.07:20:17.39#ibcon#about to read 4, iclass 36, count 0 2006.224.07:20:17.39#ibcon#read 4, iclass 36, count 0 2006.224.07:20:17.39#ibcon#about to read 5, iclass 36, count 0 2006.224.07:20:17.39#ibcon#read 5, iclass 36, count 0 2006.224.07:20:17.39#ibcon#about to read 6, iclass 36, count 0 2006.224.07:20:17.39#ibcon#read 6, iclass 36, count 0 2006.224.07:20:17.39#ibcon#end of sib2, iclass 36, count 0 2006.224.07:20:17.39#ibcon#*after write, iclass 36, count 0 2006.224.07:20:17.39#ibcon#*before return 0, iclass 36, count 0 2006.224.07:20:17.39#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.224.07:20:17.39#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.224.07:20:17.39#ibcon#about to clear, iclass 36 cls_cnt 0 2006.224.07:20:17.39#ibcon#cleared, iclass 36 cls_cnt 0 2006.224.07:20:17.39$vc4f8/valo=6,772.99 2006.224.07:20:17.39#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.224.07:20:17.39#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.224.07:20:17.39#ibcon#ireg 17 cls_cnt 0 2006.224.07:20:17.39#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.224.07:20:17.39#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.224.07:20:17.39#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.224.07:20:17.39#ibcon#enter wrdev, iclass 38, count 0 2006.224.07:20:17.39#ibcon#first serial, iclass 38, count 0 2006.224.07:20:17.39#ibcon#enter sib2, iclass 38, count 0 2006.224.07:20:17.39#ibcon#flushed, iclass 38, count 0 2006.224.07:20:17.39#ibcon#about to write, iclass 38, count 0 2006.224.07:20:17.39#ibcon#wrote, iclass 38, count 0 2006.224.07:20:17.39#ibcon#about to read 3, iclass 38, count 0 2006.224.07:20:17.41#ibcon#read 3, iclass 38, count 0 2006.224.07:20:17.41#ibcon#about to read 4, iclass 38, count 0 2006.224.07:20:17.41#ibcon#read 4, iclass 38, count 0 2006.224.07:20:17.41#ibcon#about to read 5, iclass 38, count 0 2006.224.07:20:17.41#ibcon#read 5, iclass 38, count 0 2006.224.07:20:17.41#ibcon#about to read 6, iclass 38, count 0 2006.224.07:20:17.41#ibcon#read 6, iclass 38, count 0 2006.224.07:20:17.41#ibcon#end of sib2, iclass 38, count 0 2006.224.07:20:17.41#ibcon#*mode == 0, iclass 38, count 0 2006.224.07:20:17.41#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.224.07:20:17.41#ibcon#[26=FRQ=06,772.99\r\n] 2006.224.07:20:17.41#ibcon#*before write, iclass 38, count 0 2006.224.07:20:17.41#ibcon#enter sib2, iclass 38, count 0 2006.224.07:20:17.41#ibcon#flushed, iclass 38, count 0 2006.224.07:20:17.41#ibcon#about to write, iclass 38, count 0 2006.224.07:20:17.41#ibcon#wrote, iclass 38, count 0 2006.224.07:20:17.41#ibcon#about to read 3, iclass 38, count 0 2006.224.07:20:17.45#ibcon#read 3, iclass 38, count 0 2006.224.07:20:17.45#ibcon#about to read 4, iclass 38, count 0 2006.224.07:20:17.45#ibcon#read 4, iclass 38, count 0 2006.224.07:20:17.45#ibcon#about to read 5, iclass 38, count 0 2006.224.07:20:17.45#ibcon#read 5, iclass 38, count 0 2006.224.07:20:17.45#ibcon#about to read 6, iclass 38, count 0 2006.224.07:20:17.45#ibcon#read 6, iclass 38, count 0 2006.224.07:20:17.45#ibcon#end of sib2, iclass 38, count 0 2006.224.07:20:17.45#ibcon#*after write, iclass 38, count 0 2006.224.07:20:17.45#ibcon#*before return 0, iclass 38, count 0 2006.224.07:20:17.45#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.224.07:20:17.45#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.224.07:20:17.45#ibcon#about to clear, iclass 38 cls_cnt 0 2006.224.07:20:17.45#ibcon#cleared, iclass 38 cls_cnt 0 2006.224.07:20:17.45$vc4f8/va=6,6 2006.224.07:20:17.45#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.224.07:20:17.45#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.224.07:20:17.45#ibcon#ireg 11 cls_cnt 2 2006.224.07:20:17.45#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.224.07:20:17.51#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.224.07:20:17.51#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.224.07:20:17.51#ibcon#enter wrdev, iclass 40, count 2 2006.224.07:20:17.51#ibcon#first serial, iclass 40, count 2 2006.224.07:20:17.51#ibcon#enter sib2, iclass 40, count 2 2006.224.07:20:17.51#ibcon#flushed, iclass 40, count 2 2006.224.07:20:17.51#ibcon#about to write, iclass 40, count 2 2006.224.07:20:17.51#ibcon#wrote, iclass 40, count 2 2006.224.07:20:17.51#ibcon#about to read 3, iclass 40, count 2 2006.224.07:20:17.53#ibcon#read 3, iclass 40, count 2 2006.224.07:20:17.53#ibcon#about to read 4, iclass 40, count 2 2006.224.07:20:17.53#ibcon#read 4, iclass 40, count 2 2006.224.07:20:17.53#ibcon#about to read 5, iclass 40, count 2 2006.224.07:20:17.53#ibcon#read 5, iclass 40, count 2 2006.224.07:20:17.53#ibcon#about to read 6, iclass 40, count 2 2006.224.07:20:17.53#ibcon#read 6, iclass 40, count 2 2006.224.07:20:17.53#ibcon#end of sib2, iclass 40, count 2 2006.224.07:20:17.53#ibcon#*mode == 0, iclass 40, count 2 2006.224.07:20:17.53#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.224.07:20:17.53#ibcon#[25=AT06-06\r\n] 2006.224.07:20:17.53#ibcon#*before write, iclass 40, count 2 2006.224.07:20:17.53#ibcon#enter sib2, iclass 40, count 2 2006.224.07:20:17.53#ibcon#flushed, iclass 40, count 2 2006.224.07:20:17.53#ibcon#about to write, iclass 40, count 2 2006.224.07:20:17.53#ibcon#wrote, iclass 40, count 2 2006.224.07:20:17.53#ibcon#about to read 3, iclass 40, count 2 2006.224.07:20:17.56#ibcon#read 3, iclass 40, count 2 2006.224.07:20:17.56#ibcon#about to read 4, iclass 40, count 2 2006.224.07:20:17.56#ibcon#read 4, iclass 40, count 2 2006.224.07:20:17.56#ibcon#about to read 5, iclass 40, count 2 2006.224.07:20:17.56#ibcon#read 5, iclass 40, count 2 2006.224.07:20:17.56#ibcon#about to read 6, iclass 40, count 2 2006.224.07:20:17.56#ibcon#read 6, iclass 40, count 2 2006.224.07:20:17.56#ibcon#end of sib2, iclass 40, count 2 2006.224.07:20:17.56#ibcon#*after write, iclass 40, count 2 2006.224.07:20:17.56#ibcon#*before return 0, iclass 40, count 2 2006.224.07:20:17.56#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.224.07:20:17.56#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.224.07:20:17.56#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.224.07:20:17.56#ibcon#ireg 7 cls_cnt 0 2006.224.07:20:17.56#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.224.07:20:17.68#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.224.07:20:17.68#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.224.07:20:17.68#ibcon#enter wrdev, iclass 40, count 0 2006.224.07:20:17.68#ibcon#first serial, iclass 40, count 0 2006.224.07:20:17.68#ibcon#enter sib2, iclass 40, count 0 2006.224.07:20:17.68#ibcon#flushed, iclass 40, count 0 2006.224.07:20:17.68#ibcon#about to write, iclass 40, count 0 2006.224.07:20:17.68#ibcon#wrote, iclass 40, count 0 2006.224.07:20:17.68#ibcon#about to read 3, iclass 40, count 0 2006.224.07:20:17.70#ibcon#read 3, iclass 40, count 0 2006.224.07:20:17.70#ibcon#about to read 4, iclass 40, count 0 2006.224.07:20:17.70#ibcon#read 4, iclass 40, count 0 2006.224.07:20:17.70#ibcon#about to read 5, iclass 40, count 0 2006.224.07:20:17.70#ibcon#read 5, iclass 40, count 0 2006.224.07:20:17.70#ibcon#about to read 6, iclass 40, count 0 2006.224.07:20:17.70#ibcon#read 6, iclass 40, count 0 2006.224.07:20:17.70#ibcon#end of sib2, iclass 40, count 0 2006.224.07:20:17.70#ibcon#*mode == 0, iclass 40, count 0 2006.224.07:20:17.70#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.224.07:20:17.70#ibcon#[25=USB\r\n] 2006.224.07:20:17.70#ibcon#*before write, iclass 40, count 0 2006.224.07:20:17.70#ibcon#enter sib2, iclass 40, count 0 2006.224.07:20:17.70#ibcon#flushed, iclass 40, count 0 2006.224.07:20:17.70#ibcon#about to write, iclass 40, count 0 2006.224.07:20:17.70#ibcon#wrote, iclass 40, count 0 2006.224.07:20:17.70#ibcon#about to read 3, iclass 40, count 0 2006.224.07:20:17.73#ibcon#read 3, iclass 40, count 0 2006.224.07:20:17.73#ibcon#about to read 4, iclass 40, count 0 2006.224.07:20:17.73#ibcon#read 4, iclass 40, count 0 2006.224.07:20:17.73#ibcon#about to read 5, iclass 40, count 0 2006.224.07:20:17.73#ibcon#read 5, iclass 40, count 0 2006.224.07:20:17.73#ibcon#about to read 6, iclass 40, count 0 2006.224.07:20:17.73#ibcon#read 6, iclass 40, count 0 2006.224.07:20:17.73#ibcon#end of sib2, iclass 40, count 0 2006.224.07:20:17.73#ibcon#*after write, iclass 40, count 0 2006.224.07:20:17.73#ibcon#*before return 0, iclass 40, count 0 2006.224.07:20:17.73#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.224.07:20:17.73#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.224.07:20:17.73#ibcon#about to clear, iclass 40 cls_cnt 0 2006.224.07:20:17.73#ibcon#cleared, iclass 40 cls_cnt 0 2006.224.07:20:17.73$vc4f8/valo=7,832.99 2006.224.07:20:17.73#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.224.07:20:17.73#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.224.07:20:17.73#ibcon#ireg 17 cls_cnt 0 2006.224.07:20:17.73#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.224.07:20:17.73#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.224.07:20:17.73#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.224.07:20:17.73#ibcon#enter wrdev, iclass 4, count 0 2006.224.07:20:17.73#ibcon#first serial, iclass 4, count 0 2006.224.07:20:17.73#ibcon#enter sib2, iclass 4, count 0 2006.224.07:20:17.73#ibcon#flushed, iclass 4, count 0 2006.224.07:20:17.73#ibcon#about to write, iclass 4, count 0 2006.224.07:20:17.73#ibcon#wrote, iclass 4, count 0 2006.224.07:20:17.73#ibcon#about to read 3, iclass 4, count 0 2006.224.07:20:17.75#ibcon#read 3, iclass 4, count 0 2006.224.07:20:17.75#ibcon#about to read 4, iclass 4, count 0 2006.224.07:20:17.75#ibcon#read 4, iclass 4, count 0 2006.224.07:20:17.75#ibcon#about to read 5, iclass 4, count 0 2006.224.07:20:17.75#ibcon#read 5, iclass 4, count 0 2006.224.07:20:17.75#ibcon#about to read 6, iclass 4, count 0 2006.224.07:20:17.75#ibcon#read 6, iclass 4, count 0 2006.224.07:20:17.75#ibcon#end of sib2, iclass 4, count 0 2006.224.07:20:17.75#ibcon#*mode == 0, iclass 4, count 0 2006.224.07:20:17.75#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.224.07:20:17.75#ibcon#[26=FRQ=07,832.99\r\n] 2006.224.07:20:17.75#ibcon#*before write, iclass 4, count 0 2006.224.07:20:17.75#ibcon#enter sib2, iclass 4, count 0 2006.224.07:20:17.75#ibcon#flushed, iclass 4, count 0 2006.224.07:20:17.75#ibcon#about to write, iclass 4, count 0 2006.224.07:20:17.75#ibcon#wrote, iclass 4, count 0 2006.224.07:20:17.75#ibcon#about to read 3, iclass 4, count 0 2006.224.07:20:17.79#ibcon#read 3, iclass 4, count 0 2006.224.07:20:17.79#ibcon#about to read 4, iclass 4, count 0 2006.224.07:20:17.79#ibcon#read 4, iclass 4, count 0 2006.224.07:20:17.79#ibcon#about to read 5, iclass 4, count 0 2006.224.07:20:17.79#ibcon#read 5, iclass 4, count 0 2006.224.07:20:17.79#ibcon#about to read 6, iclass 4, count 0 2006.224.07:20:17.79#ibcon#read 6, iclass 4, count 0 2006.224.07:20:17.79#ibcon#end of sib2, iclass 4, count 0 2006.224.07:20:17.79#ibcon#*after write, iclass 4, count 0 2006.224.07:20:17.79#ibcon#*before return 0, iclass 4, count 0 2006.224.07:20:17.79#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.224.07:20:17.79#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.224.07:20:17.79#ibcon#about to clear, iclass 4 cls_cnt 0 2006.224.07:20:17.79#ibcon#cleared, iclass 4 cls_cnt 0 2006.224.07:20:17.79$vc4f8/va=7,6 2006.224.07:20:17.79#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.224.07:20:17.79#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.224.07:20:17.79#ibcon#ireg 11 cls_cnt 2 2006.224.07:20:17.79#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.224.07:20:17.85#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.224.07:20:17.85#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.224.07:20:17.85#ibcon#enter wrdev, iclass 6, count 2 2006.224.07:20:17.85#ibcon#first serial, iclass 6, count 2 2006.224.07:20:17.85#ibcon#enter sib2, iclass 6, count 2 2006.224.07:20:17.85#ibcon#flushed, iclass 6, count 2 2006.224.07:20:17.85#ibcon#about to write, iclass 6, count 2 2006.224.07:20:17.85#ibcon#wrote, iclass 6, count 2 2006.224.07:20:17.85#ibcon#about to read 3, iclass 6, count 2 2006.224.07:20:17.87#ibcon#read 3, iclass 6, count 2 2006.224.07:20:17.87#ibcon#about to read 4, iclass 6, count 2 2006.224.07:20:17.87#ibcon#read 4, iclass 6, count 2 2006.224.07:20:17.87#ibcon#about to read 5, iclass 6, count 2 2006.224.07:20:17.87#ibcon#read 5, iclass 6, count 2 2006.224.07:20:17.87#ibcon#about to read 6, iclass 6, count 2 2006.224.07:20:17.87#ibcon#read 6, iclass 6, count 2 2006.224.07:20:17.87#ibcon#end of sib2, iclass 6, count 2 2006.224.07:20:17.87#ibcon#*mode == 0, iclass 6, count 2 2006.224.07:20:17.87#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.224.07:20:17.87#ibcon#[25=AT07-06\r\n] 2006.224.07:20:17.87#ibcon#*before write, iclass 6, count 2 2006.224.07:20:17.87#ibcon#enter sib2, iclass 6, count 2 2006.224.07:20:17.87#ibcon#flushed, iclass 6, count 2 2006.224.07:20:17.87#ibcon#about to write, iclass 6, count 2 2006.224.07:20:17.87#ibcon#wrote, iclass 6, count 2 2006.224.07:20:17.87#ibcon#about to read 3, iclass 6, count 2 2006.224.07:20:17.90#ibcon#read 3, iclass 6, count 2 2006.224.07:20:17.90#ibcon#about to read 4, iclass 6, count 2 2006.224.07:20:17.90#ibcon#read 4, iclass 6, count 2 2006.224.07:20:17.90#ibcon#about to read 5, iclass 6, count 2 2006.224.07:20:17.90#ibcon#read 5, iclass 6, count 2 2006.224.07:20:17.90#ibcon#about to read 6, iclass 6, count 2 2006.224.07:20:17.90#ibcon#read 6, iclass 6, count 2 2006.224.07:20:17.90#ibcon#end of sib2, iclass 6, count 2 2006.224.07:20:17.90#ibcon#*after write, iclass 6, count 2 2006.224.07:20:17.90#ibcon#*before return 0, iclass 6, count 2 2006.224.07:20:17.90#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.224.07:20:17.90#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.224.07:20:17.90#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.224.07:20:17.90#ibcon#ireg 7 cls_cnt 0 2006.224.07:20:17.90#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.224.07:20:18.02#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.224.07:20:18.02#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.224.07:20:18.02#ibcon#enter wrdev, iclass 6, count 0 2006.224.07:20:18.02#ibcon#first serial, iclass 6, count 0 2006.224.07:20:18.02#ibcon#enter sib2, iclass 6, count 0 2006.224.07:20:18.02#ibcon#flushed, iclass 6, count 0 2006.224.07:20:18.02#ibcon#about to write, iclass 6, count 0 2006.224.07:20:18.02#ibcon#wrote, iclass 6, count 0 2006.224.07:20:18.02#ibcon#about to read 3, iclass 6, count 0 2006.224.07:20:18.04#ibcon#read 3, iclass 6, count 0 2006.224.07:20:18.04#ibcon#about to read 4, iclass 6, count 0 2006.224.07:20:18.04#ibcon#read 4, iclass 6, count 0 2006.224.07:20:18.04#ibcon#about to read 5, iclass 6, count 0 2006.224.07:20:18.04#ibcon#read 5, iclass 6, count 0 2006.224.07:20:18.04#ibcon#about to read 6, iclass 6, count 0 2006.224.07:20:18.04#ibcon#read 6, iclass 6, count 0 2006.224.07:20:18.04#ibcon#end of sib2, iclass 6, count 0 2006.224.07:20:18.04#ibcon#*mode == 0, iclass 6, count 0 2006.224.07:20:18.04#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.224.07:20:18.04#ibcon#[25=USB\r\n] 2006.224.07:20:18.04#ibcon#*before write, iclass 6, count 0 2006.224.07:20:18.04#ibcon#enter sib2, iclass 6, count 0 2006.224.07:20:18.04#ibcon#flushed, iclass 6, count 0 2006.224.07:20:18.04#ibcon#about to write, iclass 6, count 0 2006.224.07:20:18.04#ibcon#wrote, iclass 6, count 0 2006.224.07:20:18.04#ibcon#about to read 3, iclass 6, count 0 2006.224.07:20:18.07#ibcon#read 3, iclass 6, count 0 2006.224.07:20:18.07#ibcon#about to read 4, iclass 6, count 0 2006.224.07:20:18.07#ibcon#read 4, iclass 6, count 0 2006.224.07:20:18.07#ibcon#about to read 5, iclass 6, count 0 2006.224.07:20:18.07#ibcon#read 5, iclass 6, count 0 2006.224.07:20:18.07#ibcon#about to read 6, iclass 6, count 0 2006.224.07:20:18.07#ibcon#read 6, iclass 6, count 0 2006.224.07:20:18.07#ibcon#end of sib2, iclass 6, count 0 2006.224.07:20:18.07#ibcon#*after write, iclass 6, count 0 2006.224.07:20:18.07#ibcon#*before return 0, iclass 6, count 0 2006.224.07:20:18.07#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.224.07:20:18.07#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.224.07:20:18.07#ibcon#about to clear, iclass 6 cls_cnt 0 2006.224.07:20:18.07#ibcon#cleared, iclass 6 cls_cnt 0 2006.224.07:20:18.07$vc4f8/valo=8,852.99 2006.224.07:20:18.07#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.224.07:20:18.07#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.224.07:20:18.07#ibcon#ireg 17 cls_cnt 0 2006.224.07:20:18.07#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.224.07:20:18.07#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.224.07:20:18.07#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.224.07:20:18.07#ibcon#enter wrdev, iclass 10, count 0 2006.224.07:20:18.07#ibcon#first serial, iclass 10, count 0 2006.224.07:20:18.07#ibcon#enter sib2, iclass 10, count 0 2006.224.07:20:18.07#ibcon#flushed, iclass 10, count 0 2006.224.07:20:18.07#ibcon#about to write, iclass 10, count 0 2006.224.07:20:18.07#ibcon#wrote, iclass 10, count 0 2006.224.07:20:18.07#ibcon#about to read 3, iclass 10, count 0 2006.224.07:20:18.09#ibcon#read 3, iclass 10, count 0 2006.224.07:20:18.09#ibcon#about to read 4, iclass 10, count 0 2006.224.07:20:18.09#ibcon#read 4, iclass 10, count 0 2006.224.07:20:18.09#ibcon#about to read 5, iclass 10, count 0 2006.224.07:20:18.09#ibcon#read 5, iclass 10, count 0 2006.224.07:20:18.09#ibcon#about to read 6, iclass 10, count 0 2006.224.07:20:18.09#ibcon#read 6, iclass 10, count 0 2006.224.07:20:18.09#ibcon#end of sib2, iclass 10, count 0 2006.224.07:20:18.09#ibcon#*mode == 0, iclass 10, count 0 2006.224.07:20:18.09#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.224.07:20:18.09#ibcon#[26=FRQ=08,852.99\r\n] 2006.224.07:20:18.09#ibcon#*before write, iclass 10, count 0 2006.224.07:20:18.09#ibcon#enter sib2, iclass 10, count 0 2006.224.07:20:18.09#ibcon#flushed, iclass 10, count 0 2006.224.07:20:18.09#ibcon#about to write, iclass 10, count 0 2006.224.07:20:18.09#ibcon#wrote, iclass 10, count 0 2006.224.07:20:18.09#ibcon#about to read 3, iclass 10, count 0 2006.224.07:20:18.13#ibcon#read 3, iclass 10, count 0 2006.224.07:20:18.13#ibcon#about to read 4, iclass 10, count 0 2006.224.07:20:18.13#ibcon#read 4, iclass 10, count 0 2006.224.07:20:18.13#ibcon#about to read 5, iclass 10, count 0 2006.224.07:20:18.13#ibcon#read 5, iclass 10, count 0 2006.224.07:20:18.13#ibcon#about to read 6, iclass 10, count 0 2006.224.07:20:18.13#ibcon#read 6, iclass 10, count 0 2006.224.07:20:18.13#ibcon#end of sib2, iclass 10, count 0 2006.224.07:20:18.13#ibcon#*after write, iclass 10, count 0 2006.224.07:20:18.13#ibcon#*before return 0, iclass 10, count 0 2006.224.07:20:18.13#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.224.07:20:18.13#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.224.07:20:18.13#ibcon#about to clear, iclass 10 cls_cnt 0 2006.224.07:20:18.13#ibcon#cleared, iclass 10 cls_cnt 0 2006.224.07:20:18.13$vc4f8/va=8,7 2006.224.07:20:18.13#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.224.07:20:18.13#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.224.07:20:18.13#ibcon#ireg 11 cls_cnt 2 2006.224.07:20:18.13#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.224.07:20:18.19#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.224.07:20:18.19#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.224.07:20:18.19#ibcon#enter wrdev, iclass 12, count 2 2006.224.07:20:18.19#ibcon#first serial, iclass 12, count 2 2006.224.07:20:18.19#ibcon#enter sib2, iclass 12, count 2 2006.224.07:20:18.19#ibcon#flushed, iclass 12, count 2 2006.224.07:20:18.19#ibcon#about to write, iclass 12, count 2 2006.224.07:20:18.19#ibcon#wrote, iclass 12, count 2 2006.224.07:20:18.19#ibcon#about to read 3, iclass 12, count 2 2006.224.07:20:18.21#ibcon#read 3, iclass 12, count 2 2006.224.07:20:18.21#ibcon#about to read 4, iclass 12, count 2 2006.224.07:20:18.21#ibcon#read 4, iclass 12, count 2 2006.224.07:20:18.21#ibcon#about to read 5, iclass 12, count 2 2006.224.07:20:18.21#ibcon#read 5, iclass 12, count 2 2006.224.07:20:18.21#ibcon#about to read 6, iclass 12, count 2 2006.224.07:20:18.21#ibcon#read 6, iclass 12, count 2 2006.224.07:20:18.21#ibcon#end of sib2, iclass 12, count 2 2006.224.07:20:18.21#ibcon#*mode == 0, iclass 12, count 2 2006.224.07:20:18.21#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.224.07:20:18.21#ibcon#[25=AT08-07\r\n] 2006.224.07:20:18.21#ibcon#*before write, iclass 12, count 2 2006.224.07:20:18.21#ibcon#enter sib2, iclass 12, count 2 2006.224.07:20:18.21#ibcon#flushed, iclass 12, count 2 2006.224.07:20:18.21#ibcon#about to write, iclass 12, count 2 2006.224.07:20:18.21#ibcon#wrote, iclass 12, count 2 2006.224.07:20:18.21#ibcon#about to read 3, iclass 12, count 2 2006.224.07:20:18.24#ibcon#read 3, iclass 12, count 2 2006.224.07:20:18.24#ibcon#about to read 4, iclass 12, count 2 2006.224.07:20:18.24#ibcon#read 4, iclass 12, count 2 2006.224.07:20:18.24#ibcon#about to read 5, iclass 12, count 2 2006.224.07:20:18.24#ibcon#read 5, iclass 12, count 2 2006.224.07:20:18.24#ibcon#about to read 6, iclass 12, count 2 2006.224.07:20:18.24#ibcon#read 6, iclass 12, count 2 2006.224.07:20:18.24#ibcon#end of sib2, iclass 12, count 2 2006.224.07:20:18.24#ibcon#*after write, iclass 12, count 2 2006.224.07:20:18.24#ibcon#*before return 0, iclass 12, count 2 2006.224.07:20:18.24#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.224.07:20:18.24#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.224.07:20:18.24#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.224.07:20:18.24#ibcon#ireg 7 cls_cnt 0 2006.224.07:20:18.24#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.224.07:20:18.36#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.224.07:20:18.36#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.224.07:20:18.36#ibcon#enter wrdev, iclass 12, count 0 2006.224.07:20:18.36#ibcon#first serial, iclass 12, count 0 2006.224.07:20:18.36#ibcon#enter sib2, iclass 12, count 0 2006.224.07:20:18.36#ibcon#flushed, iclass 12, count 0 2006.224.07:20:18.36#ibcon#about to write, iclass 12, count 0 2006.224.07:20:18.36#ibcon#wrote, iclass 12, count 0 2006.224.07:20:18.36#ibcon#about to read 3, iclass 12, count 0 2006.224.07:20:18.38#ibcon#read 3, iclass 12, count 0 2006.224.07:20:18.38#ibcon#about to read 4, iclass 12, count 0 2006.224.07:20:18.38#ibcon#read 4, iclass 12, count 0 2006.224.07:20:18.38#ibcon#about to read 5, iclass 12, count 0 2006.224.07:20:18.38#ibcon#read 5, iclass 12, count 0 2006.224.07:20:18.38#ibcon#about to read 6, iclass 12, count 0 2006.224.07:20:18.38#ibcon#read 6, iclass 12, count 0 2006.224.07:20:18.38#ibcon#end of sib2, iclass 12, count 0 2006.224.07:20:18.38#ibcon#*mode == 0, iclass 12, count 0 2006.224.07:20:18.38#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.224.07:20:18.38#ibcon#[25=USB\r\n] 2006.224.07:20:18.38#ibcon#*before write, iclass 12, count 0 2006.224.07:20:18.38#ibcon#enter sib2, iclass 12, count 0 2006.224.07:20:18.38#ibcon#flushed, iclass 12, count 0 2006.224.07:20:18.38#ibcon#about to write, iclass 12, count 0 2006.224.07:20:18.38#ibcon#wrote, iclass 12, count 0 2006.224.07:20:18.38#ibcon#about to read 3, iclass 12, count 0 2006.224.07:20:18.41#ibcon#read 3, iclass 12, count 0 2006.224.07:20:18.41#ibcon#about to read 4, iclass 12, count 0 2006.224.07:20:18.41#ibcon#read 4, iclass 12, count 0 2006.224.07:20:18.41#ibcon#about to read 5, iclass 12, count 0 2006.224.07:20:18.41#ibcon#read 5, iclass 12, count 0 2006.224.07:20:18.41#ibcon#about to read 6, iclass 12, count 0 2006.224.07:20:18.41#ibcon#read 6, iclass 12, count 0 2006.224.07:20:18.41#ibcon#end of sib2, iclass 12, count 0 2006.224.07:20:18.41#ibcon#*after write, iclass 12, count 0 2006.224.07:20:18.41#ibcon#*before return 0, iclass 12, count 0 2006.224.07:20:18.41#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.224.07:20:18.41#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.224.07:20:18.41#ibcon#about to clear, iclass 12 cls_cnt 0 2006.224.07:20:18.41#ibcon#cleared, iclass 12 cls_cnt 0 2006.224.07:20:18.41$vc4f8/vblo=1,632.99 2006.224.07:20:18.41#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.224.07:20:18.41#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.224.07:20:18.41#ibcon#ireg 17 cls_cnt 0 2006.224.07:20:18.41#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.224.07:20:18.41#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.224.07:20:18.41#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.224.07:20:18.41#ibcon#enter wrdev, iclass 14, count 0 2006.224.07:20:18.41#ibcon#first serial, iclass 14, count 0 2006.224.07:20:18.41#ibcon#enter sib2, iclass 14, count 0 2006.224.07:20:18.41#ibcon#flushed, iclass 14, count 0 2006.224.07:20:18.41#ibcon#about to write, iclass 14, count 0 2006.224.07:20:18.41#ibcon#wrote, iclass 14, count 0 2006.224.07:20:18.41#ibcon#about to read 3, iclass 14, count 0 2006.224.07:20:18.43#ibcon#read 3, iclass 14, count 0 2006.224.07:20:18.43#ibcon#about to read 4, iclass 14, count 0 2006.224.07:20:18.43#ibcon#read 4, iclass 14, count 0 2006.224.07:20:18.43#ibcon#about to read 5, iclass 14, count 0 2006.224.07:20:18.43#ibcon#read 5, iclass 14, count 0 2006.224.07:20:18.43#ibcon#about to read 6, iclass 14, count 0 2006.224.07:20:18.43#ibcon#read 6, iclass 14, count 0 2006.224.07:20:18.43#ibcon#end of sib2, iclass 14, count 0 2006.224.07:20:18.43#ibcon#*mode == 0, iclass 14, count 0 2006.224.07:20:18.43#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.224.07:20:18.43#ibcon#[28=FRQ=01,632.99\r\n] 2006.224.07:20:18.43#ibcon#*before write, iclass 14, count 0 2006.224.07:20:18.43#ibcon#enter sib2, iclass 14, count 0 2006.224.07:20:18.43#ibcon#flushed, iclass 14, count 0 2006.224.07:20:18.43#ibcon#about to write, iclass 14, count 0 2006.224.07:20:18.43#ibcon#wrote, iclass 14, count 0 2006.224.07:20:18.43#ibcon#about to read 3, iclass 14, count 0 2006.224.07:20:18.49#ibcon#read 3, iclass 14, count 0 2006.224.07:20:18.49#ibcon#about to read 4, iclass 14, count 0 2006.224.07:20:18.49#ibcon#read 4, iclass 14, count 0 2006.224.07:20:18.49#ibcon#about to read 5, iclass 14, count 0 2006.224.07:20:18.49#ibcon#read 5, iclass 14, count 0 2006.224.07:20:18.49#ibcon#about to read 6, iclass 14, count 0 2006.224.07:20:18.49#ibcon#read 6, iclass 14, count 0 2006.224.07:20:18.49#ibcon#end of sib2, iclass 14, count 0 2006.224.07:20:18.49#ibcon#*after write, iclass 14, count 0 2006.224.07:20:18.49#ibcon#*before return 0, iclass 14, count 0 2006.224.07:20:18.49#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.224.07:20:18.49#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.224.07:20:18.49#ibcon#about to clear, iclass 14 cls_cnt 0 2006.224.07:20:18.49#ibcon#cleared, iclass 14 cls_cnt 0 2006.224.07:20:18.49$vc4f8/vb=1,4 2006.224.07:20:18.49#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.224.07:20:18.49#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.224.07:20:18.49#ibcon#ireg 11 cls_cnt 2 2006.224.07:20:18.49#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.224.07:20:18.49#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.224.07:20:18.49#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.224.07:20:18.49#ibcon#enter wrdev, iclass 16, count 2 2006.224.07:20:18.49#ibcon#first serial, iclass 16, count 2 2006.224.07:20:18.49#ibcon#enter sib2, iclass 16, count 2 2006.224.07:20:18.49#ibcon#flushed, iclass 16, count 2 2006.224.07:20:18.49#ibcon#about to write, iclass 16, count 2 2006.224.07:20:18.49#ibcon#wrote, iclass 16, count 2 2006.224.07:20:18.49#ibcon#about to read 3, iclass 16, count 2 2006.224.07:20:18.51#ibcon#read 3, iclass 16, count 2 2006.224.07:20:18.51#ibcon#about to read 4, iclass 16, count 2 2006.224.07:20:18.51#ibcon#read 4, iclass 16, count 2 2006.224.07:20:18.51#ibcon#about to read 5, iclass 16, count 2 2006.224.07:20:18.51#ibcon#read 5, iclass 16, count 2 2006.224.07:20:18.51#ibcon#about to read 6, iclass 16, count 2 2006.224.07:20:18.51#ibcon#read 6, iclass 16, count 2 2006.224.07:20:18.51#ibcon#end of sib2, iclass 16, count 2 2006.224.07:20:18.51#ibcon#*mode == 0, iclass 16, count 2 2006.224.07:20:18.51#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.224.07:20:18.51#ibcon#[27=AT01-04\r\n] 2006.224.07:20:18.51#ibcon#*before write, iclass 16, count 2 2006.224.07:20:18.51#ibcon#enter sib2, iclass 16, count 2 2006.224.07:20:18.51#ibcon#flushed, iclass 16, count 2 2006.224.07:20:18.51#ibcon#about to write, iclass 16, count 2 2006.224.07:20:18.51#ibcon#wrote, iclass 16, count 2 2006.224.07:20:18.51#ibcon#about to read 3, iclass 16, count 2 2006.224.07:20:18.55#ibcon#read 3, iclass 16, count 2 2006.224.07:20:18.55#ibcon#about to read 4, iclass 16, count 2 2006.224.07:20:18.55#ibcon#read 4, iclass 16, count 2 2006.224.07:20:18.55#ibcon#about to read 5, iclass 16, count 2 2006.224.07:20:18.55#ibcon#read 5, iclass 16, count 2 2006.224.07:20:18.55#ibcon#about to read 6, iclass 16, count 2 2006.224.07:20:18.55#ibcon#read 6, iclass 16, count 2 2006.224.07:20:18.55#ibcon#end of sib2, iclass 16, count 2 2006.224.07:20:18.55#ibcon#*after write, iclass 16, count 2 2006.224.07:20:18.55#ibcon#*before return 0, iclass 16, count 2 2006.224.07:20:18.55#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.224.07:20:18.55#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.224.07:20:18.55#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.224.07:20:18.55#ibcon#ireg 7 cls_cnt 0 2006.224.07:20:18.55#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.224.07:20:18.67#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.224.07:20:18.67#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.224.07:20:18.67#ibcon#enter wrdev, iclass 16, count 0 2006.224.07:20:18.67#ibcon#first serial, iclass 16, count 0 2006.224.07:20:18.67#ibcon#enter sib2, iclass 16, count 0 2006.224.07:20:18.67#ibcon#flushed, iclass 16, count 0 2006.224.07:20:18.67#ibcon#about to write, iclass 16, count 0 2006.224.07:20:18.67#ibcon#wrote, iclass 16, count 0 2006.224.07:20:18.67#ibcon#about to read 3, iclass 16, count 0 2006.224.07:20:18.69#ibcon#read 3, iclass 16, count 0 2006.224.07:20:18.69#ibcon#about to read 4, iclass 16, count 0 2006.224.07:20:18.69#ibcon#read 4, iclass 16, count 0 2006.224.07:20:18.69#ibcon#about to read 5, iclass 16, count 0 2006.224.07:20:18.69#ibcon#read 5, iclass 16, count 0 2006.224.07:20:18.69#ibcon#about to read 6, iclass 16, count 0 2006.224.07:20:18.69#ibcon#read 6, iclass 16, count 0 2006.224.07:20:18.69#ibcon#end of sib2, iclass 16, count 0 2006.224.07:20:18.69#ibcon#*mode == 0, iclass 16, count 0 2006.224.07:20:18.69#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.224.07:20:18.69#ibcon#[27=USB\r\n] 2006.224.07:20:18.69#ibcon#*before write, iclass 16, count 0 2006.224.07:20:18.69#ibcon#enter sib2, iclass 16, count 0 2006.224.07:20:18.69#ibcon#flushed, iclass 16, count 0 2006.224.07:20:18.69#ibcon#about to write, iclass 16, count 0 2006.224.07:20:18.69#ibcon#wrote, iclass 16, count 0 2006.224.07:20:18.69#ibcon#about to read 3, iclass 16, count 0 2006.224.07:20:18.72#ibcon#read 3, iclass 16, count 0 2006.224.07:20:18.72#ibcon#about to read 4, iclass 16, count 0 2006.224.07:20:18.72#ibcon#read 4, iclass 16, count 0 2006.224.07:20:18.72#ibcon#about to read 5, iclass 16, count 0 2006.224.07:20:18.72#ibcon#read 5, iclass 16, count 0 2006.224.07:20:18.72#ibcon#about to read 6, iclass 16, count 0 2006.224.07:20:18.72#ibcon#read 6, iclass 16, count 0 2006.224.07:20:18.72#ibcon#end of sib2, iclass 16, count 0 2006.224.07:20:18.72#ibcon#*after write, iclass 16, count 0 2006.224.07:20:18.72#ibcon#*before return 0, iclass 16, count 0 2006.224.07:20:18.72#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.224.07:20:18.72#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.224.07:20:18.72#ibcon#about to clear, iclass 16 cls_cnt 0 2006.224.07:20:18.72#ibcon#cleared, iclass 16 cls_cnt 0 2006.224.07:20:18.72$vc4f8/vblo=2,640.99 2006.224.07:20:18.72#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.224.07:20:18.72#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.224.07:20:18.72#ibcon#ireg 17 cls_cnt 0 2006.224.07:20:18.72#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.224.07:20:18.72#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.224.07:20:18.72#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.224.07:20:18.72#ibcon#enter wrdev, iclass 18, count 0 2006.224.07:20:18.72#ibcon#first serial, iclass 18, count 0 2006.224.07:20:18.72#ibcon#enter sib2, iclass 18, count 0 2006.224.07:20:18.72#ibcon#flushed, iclass 18, count 0 2006.224.07:20:18.72#ibcon#about to write, iclass 18, count 0 2006.224.07:20:18.72#ibcon#wrote, iclass 18, count 0 2006.224.07:20:18.72#ibcon#about to read 3, iclass 18, count 0 2006.224.07:20:18.74#ibcon#read 3, iclass 18, count 0 2006.224.07:20:18.74#ibcon#about to read 4, iclass 18, count 0 2006.224.07:20:18.74#ibcon#read 4, iclass 18, count 0 2006.224.07:20:18.74#ibcon#about to read 5, iclass 18, count 0 2006.224.07:20:18.74#ibcon#read 5, iclass 18, count 0 2006.224.07:20:18.74#ibcon#about to read 6, iclass 18, count 0 2006.224.07:20:18.74#ibcon#read 6, iclass 18, count 0 2006.224.07:20:18.74#ibcon#end of sib2, iclass 18, count 0 2006.224.07:20:18.74#ibcon#*mode == 0, iclass 18, count 0 2006.224.07:20:18.74#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.224.07:20:18.74#ibcon#[28=FRQ=02,640.99\r\n] 2006.224.07:20:18.74#ibcon#*before write, iclass 18, count 0 2006.224.07:20:18.74#ibcon#enter sib2, iclass 18, count 0 2006.224.07:20:18.74#ibcon#flushed, iclass 18, count 0 2006.224.07:20:18.74#ibcon#about to write, iclass 18, count 0 2006.224.07:20:18.74#ibcon#wrote, iclass 18, count 0 2006.224.07:20:18.74#ibcon#about to read 3, iclass 18, count 0 2006.224.07:20:18.78#ibcon#read 3, iclass 18, count 0 2006.224.07:20:18.78#ibcon#about to read 4, iclass 18, count 0 2006.224.07:20:18.78#ibcon#read 4, iclass 18, count 0 2006.224.07:20:18.78#ibcon#about to read 5, iclass 18, count 0 2006.224.07:20:18.78#ibcon#read 5, iclass 18, count 0 2006.224.07:20:18.78#ibcon#about to read 6, iclass 18, count 0 2006.224.07:20:18.78#ibcon#read 6, iclass 18, count 0 2006.224.07:20:18.78#ibcon#end of sib2, iclass 18, count 0 2006.224.07:20:18.78#ibcon#*after write, iclass 18, count 0 2006.224.07:20:18.78#ibcon#*before return 0, iclass 18, count 0 2006.224.07:20:18.78#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.224.07:20:18.78#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.224.07:20:18.78#ibcon#about to clear, iclass 18 cls_cnt 0 2006.224.07:20:18.78#ibcon#cleared, iclass 18 cls_cnt 0 2006.224.07:20:18.78$vc4f8/vb=2,4 2006.224.07:20:18.78#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.224.07:20:18.78#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.224.07:20:18.78#ibcon#ireg 11 cls_cnt 2 2006.224.07:20:18.78#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.224.07:20:18.84#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.224.07:20:18.84#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.224.07:20:18.84#ibcon#enter wrdev, iclass 20, count 2 2006.224.07:20:18.84#ibcon#first serial, iclass 20, count 2 2006.224.07:20:18.84#ibcon#enter sib2, iclass 20, count 2 2006.224.07:20:18.84#ibcon#flushed, iclass 20, count 2 2006.224.07:20:18.84#ibcon#about to write, iclass 20, count 2 2006.224.07:20:18.84#ibcon#wrote, iclass 20, count 2 2006.224.07:20:18.84#ibcon#about to read 3, iclass 20, count 2 2006.224.07:20:18.86#ibcon#read 3, iclass 20, count 2 2006.224.07:20:18.86#ibcon#about to read 4, iclass 20, count 2 2006.224.07:20:18.86#ibcon#read 4, iclass 20, count 2 2006.224.07:20:18.86#ibcon#about to read 5, iclass 20, count 2 2006.224.07:20:18.86#ibcon#read 5, iclass 20, count 2 2006.224.07:20:18.86#ibcon#about to read 6, iclass 20, count 2 2006.224.07:20:18.86#ibcon#read 6, iclass 20, count 2 2006.224.07:20:18.86#ibcon#end of sib2, iclass 20, count 2 2006.224.07:20:18.86#ibcon#*mode == 0, iclass 20, count 2 2006.224.07:20:18.86#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.224.07:20:18.86#ibcon#[27=AT02-04\r\n] 2006.224.07:20:18.86#ibcon#*before write, iclass 20, count 2 2006.224.07:20:18.86#ibcon#enter sib2, iclass 20, count 2 2006.224.07:20:18.86#ibcon#flushed, iclass 20, count 2 2006.224.07:20:18.86#ibcon#about to write, iclass 20, count 2 2006.224.07:20:18.86#ibcon#wrote, iclass 20, count 2 2006.224.07:20:18.86#ibcon#about to read 3, iclass 20, count 2 2006.224.07:20:18.89#ibcon#read 3, iclass 20, count 2 2006.224.07:20:18.89#ibcon#about to read 4, iclass 20, count 2 2006.224.07:20:18.89#ibcon#read 4, iclass 20, count 2 2006.224.07:20:18.89#ibcon#about to read 5, iclass 20, count 2 2006.224.07:20:18.89#ibcon#read 5, iclass 20, count 2 2006.224.07:20:18.89#ibcon#about to read 6, iclass 20, count 2 2006.224.07:20:18.89#ibcon#read 6, iclass 20, count 2 2006.224.07:20:18.89#ibcon#end of sib2, iclass 20, count 2 2006.224.07:20:18.89#ibcon#*after write, iclass 20, count 2 2006.224.07:20:18.89#ibcon#*before return 0, iclass 20, count 2 2006.224.07:20:18.89#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.224.07:20:18.89#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.224.07:20:18.89#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.224.07:20:18.89#ibcon#ireg 7 cls_cnt 0 2006.224.07:20:18.89#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.224.07:20:19.01#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.224.07:20:19.01#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.224.07:20:19.01#ibcon#enter wrdev, iclass 20, count 0 2006.224.07:20:19.01#ibcon#first serial, iclass 20, count 0 2006.224.07:20:19.01#ibcon#enter sib2, iclass 20, count 0 2006.224.07:20:19.01#ibcon#flushed, iclass 20, count 0 2006.224.07:20:19.01#ibcon#about to write, iclass 20, count 0 2006.224.07:20:19.01#ibcon#wrote, iclass 20, count 0 2006.224.07:20:19.01#ibcon#about to read 3, iclass 20, count 0 2006.224.07:20:19.03#ibcon#read 3, iclass 20, count 0 2006.224.07:20:19.03#ibcon#about to read 4, iclass 20, count 0 2006.224.07:20:19.03#ibcon#read 4, iclass 20, count 0 2006.224.07:20:19.03#ibcon#about to read 5, iclass 20, count 0 2006.224.07:20:19.03#ibcon#read 5, iclass 20, count 0 2006.224.07:20:19.03#ibcon#about to read 6, iclass 20, count 0 2006.224.07:20:19.03#ibcon#read 6, iclass 20, count 0 2006.224.07:20:19.03#ibcon#end of sib2, iclass 20, count 0 2006.224.07:20:19.03#ibcon#*mode == 0, iclass 20, count 0 2006.224.07:20:19.03#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.224.07:20:19.03#ibcon#[27=USB\r\n] 2006.224.07:20:19.03#ibcon#*before write, iclass 20, count 0 2006.224.07:20:19.03#ibcon#enter sib2, iclass 20, count 0 2006.224.07:20:19.03#ibcon#flushed, iclass 20, count 0 2006.224.07:20:19.03#ibcon#about to write, iclass 20, count 0 2006.224.07:20:19.03#ibcon#wrote, iclass 20, count 0 2006.224.07:20:19.03#ibcon#about to read 3, iclass 20, count 0 2006.224.07:20:19.06#ibcon#read 3, iclass 20, count 0 2006.224.07:20:19.06#ibcon#about to read 4, iclass 20, count 0 2006.224.07:20:19.06#ibcon#read 4, iclass 20, count 0 2006.224.07:20:19.06#ibcon#about to read 5, iclass 20, count 0 2006.224.07:20:19.06#ibcon#read 5, iclass 20, count 0 2006.224.07:20:19.06#ibcon#about to read 6, iclass 20, count 0 2006.224.07:20:19.06#ibcon#read 6, iclass 20, count 0 2006.224.07:20:19.06#ibcon#end of sib2, iclass 20, count 0 2006.224.07:20:19.06#ibcon#*after write, iclass 20, count 0 2006.224.07:20:19.06#ibcon#*before return 0, iclass 20, count 0 2006.224.07:20:19.06#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.224.07:20:19.06#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.224.07:20:19.06#ibcon#about to clear, iclass 20 cls_cnt 0 2006.224.07:20:19.06#ibcon#cleared, iclass 20 cls_cnt 0 2006.224.07:20:19.06$vc4f8/vblo=3,656.99 2006.224.07:20:19.06#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.224.07:20:19.06#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.224.07:20:19.06#ibcon#ireg 17 cls_cnt 0 2006.224.07:20:19.06#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.224.07:20:19.06#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.224.07:20:19.06#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.224.07:20:19.06#ibcon#enter wrdev, iclass 22, count 0 2006.224.07:20:19.06#ibcon#first serial, iclass 22, count 0 2006.224.07:20:19.06#ibcon#enter sib2, iclass 22, count 0 2006.224.07:20:19.06#ibcon#flushed, iclass 22, count 0 2006.224.07:20:19.06#ibcon#about to write, iclass 22, count 0 2006.224.07:20:19.06#ibcon#wrote, iclass 22, count 0 2006.224.07:20:19.06#ibcon#about to read 3, iclass 22, count 0 2006.224.07:20:19.08#ibcon#read 3, iclass 22, count 0 2006.224.07:20:19.08#ibcon#about to read 4, iclass 22, count 0 2006.224.07:20:19.08#ibcon#read 4, iclass 22, count 0 2006.224.07:20:19.08#ibcon#about to read 5, iclass 22, count 0 2006.224.07:20:19.08#ibcon#read 5, iclass 22, count 0 2006.224.07:20:19.08#ibcon#about to read 6, iclass 22, count 0 2006.224.07:20:19.08#ibcon#read 6, iclass 22, count 0 2006.224.07:20:19.08#ibcon#end of sib2, iclass 22, count 0 2006.224.07:20:19.08#ibcon#*mode == 0, iclass 22, count 0 2006.224.07:20:19.08#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.224.07:20:19.08#ibcon#[28=FRQ=03,656.99\r\n] 2006.224.07:20:19.08#ibcon#*before write, iclass 22, count 0 2006.224.07:20:19.08#ibcon#enter sib2, iclass 22, count 0 2006.224.07:20:19.08#ibcon#flushed, iclass 22, count 0 2006.224.07:20:19.08#ibcon#about to write, iclass 22, count 0 2006.224.07:20:19.08#ibcon#wrote, iclass 22, count 0 2006.224.07:20:19.08#ibcon#about to read 3, iclass 22, count 0 2006.224.07:20:19.12#ibcon#read 3, iclass 22, count 0 2006.224.07:20:19.12#ibcon#about to read 4, iclass 22, count 0 2006.224.07:20:19.12#ibcon#read 4, iclass 22, count 0 2006.224.07:20:19.12#ibcon#about to read 5, iclass 22, count 0 2006.224.07:20:19.12#ibcon#read 5, iclass 22, count 0 2006.224.07:20:19.12#ibcon#about to read 6, iclass 22, count 0 2006.224.07:20:19.12#ibcon#read 6, iclass 22, count 0 2006.224.07:20:19.12#ibcon#end of sib2, iclass 22, count 0 2006.224.07:20:19.12#ibcon#*after write, iclass 22, count 0 2006.224.07:20:19.12#ibcon#*before return 0, iclass 22, count 0 2006.224.07:20:19.12#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.224.07:20:19.12#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.224.07:20:19.12#ibcon#about to clear, iclass 22 cls_cnt 0 2006.224.07:20:19.12#ibcon#cleared, iclass 22 cls_cnt 0 2006.224.07:20:19.12$vc4f8/vb=3,4 2006.224.07:20:19.12#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.224.07:20:19.12#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.224.07:20:19.12#ibcon#ireg 11 cls_cnt 2 2006.224.07:20:19.12#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.224.07:20:19.18#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.224.07:20:19.18#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.224.07:20:19.18#ibcon#enter wrdev, iclass 24, count 2 2006.224.07:20:19.18#ibcon#first serial, iclass 24, count 2 2006.224.07:20:19.18#ibcon#enter sib2, iclass 24, count 2 2006.224.07:20:19.18#ibcon#flushed, iclass 24, count 2 2006.224.07:20:19.18#ibcon#about to write, iclass 24, count 2 2006.224.07:20:19.18#ibcon#wrote, iclass 24, count 2 2006.224.07:20:19.18#ibcon#about to read 3, iclass 24, count 2 2006.224.07:20:19.20#ibcon#read 3, iclass 24, count 2 2006.224.07:20:19.20#ibcon#about to read 4, iclass 24, count 2 2006.224.07:20:19.20#ibcon#read 4, iclass 24, count 2 2006.224.07:20:19.20#ibcon#about to read 5, iclass 24, count 2 2006.224.07:20:19.20#ibcon#read 5, iclass 24, count 2 2006.224.07:20:19.20#ibcon#about to read 6, iclass 24, count 2 2006.224.07:20:19.20#ibcon#read 6, iclass 24, count 2 2006.224.07:20:19.20#ibcon#end of sib2, iclass 24, count 2 2006.224.07:20:19.20#ibcon#*mode == 0, iclass 24, count 2 2006.224.07:20:19.20#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.224.07:20:19.20#ibcon#[27=AT03-04\r\n] 2006.224.07:20:19.20#ibcon#*before write, iclass 24, count 2 2006.224.07:20:19.20#ibcon#enter sib2, iclass 24, count 2 2006.224.07:20:19.20#ibcon#flushed, iclass 24, count 2 2006.224.07:20:19.20#ibcon#about to write, iclass 24, count 2 2006.224.07:20:19.20#ibcon#wrote, iclass 24, count 2 2006.224.07:20:19.20#ibcon#about to read 3, iclass 24, count 2 2006.224.07:20:19.23#ibcon#read 3, iclass 24, count 2 2006.224.07:20:19.23#ibcon#about to read 4, iclass 24, count 2 2006.224.07:20:19.23#ibcon#read 4, iclass 24, count 2 2006.224.07:20:19.23#ibcon#about to read 5, iclass 24, count 2 2006.224.07:20:19.23#ibcon#read 5, iclass 24, count 2 2006.224.07:20:19.23#ibcon#about to read 6, iclass 24, count 2 2006.224.07:20:19.23#ibcon#read 6, iclass 24, count 2 2006.224.07:20:19.23#ibcon#end of sib2, iclass 24, count 2 2006.224.07:20:19.23#ibcon#*after write, iclass 24, count 2 2006.224.07:20:19.23#ibcon#*before return 0, iclass 24, count 2 2006.224.07:20:19.23#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.224.07:20:19.23#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.224.07:20:19.23#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.224.07:20:19.23#ibcon#ireg 7 cls_cnt 0 2006.224.07:20:19.23#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.224.07:20:19.35#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.224.07:20:19.35#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.224.07:20:19.35#ibcon#enter wrdev, iclass 24, count 0 2006.224.07:20:19.35#ibcon#first serial, iclass 24, count 0 2006.224.07:20:19.35#ibcon#enter sib2, iclass 24, count 0 2006.224.07:20:19.35#ibcon#flushed, iclass 24, count 0 2006.224.07:20:19.35#ibcon#about to write, iclass 24, count 0 2006.224.07:20:19.35#ibcon#wrote, iclass 24, count 0 2006.224.07:20:19.35#ibcon#about to read 3, iclass 24, count 0 2006.224.07:20:19.37#ibcon#read 3, iclass 24, count 0 2006.224.07:20:19.37#ibcon#about to read 4, iclass 24, count 0 2006.224.07:20:19.37#ibcon#read 4, iclass 24, count 0 2006.224.07:20:19.37#ibcon#about to read 5, iclass 24, count 0 2006.224.07:20:19.37#ibcon#read 5, iclass 24, count 0 2006.224.07:20:19.37#ibcon#about to read 6, iclass 24, count 0 2006.224.07:20:19.37#ibcon#read 6, iclass 24, count 0 2006.224.07:20:19.37#ibcon#end of sib2, iclass 24, count 0 2006.224.07:20:19.37#ibcon#*mode == 0, iclass 24, count 0 2006.224.07:20:19.37#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.224.07:20:19.37#ibcon#[27=USB\r\n] 2006.224.07:20:19.37#ibcon#*before write, iclass 24, count 0 2006.224.07:20:19.37#ibcon#enter sib2, iclass 24, count 0 2006.224.07:20:19.37#ibcon#flushed, iclass 24, count 0 2006.224.07:20:19.37#ibcon#about to write, iclass 24, count 0 2006.224.07:20:19.37#ibcon#wrote, iclass 24, count 0 2006.224.07:20:19.37#ibcon#about to read 3, iclass 24, count 0 2006.224.07:20:19.40#ibcon#read 3, iclass 24, count 0 2006.224.07:20:19.40#ibcon#about to read 4, iclass 24, count 0 2006.224.07:20:19.40#ibcon#read 4, iclass 24, count 0 2006.224.07:20:19.40#ibcon#about to read 5, iclass 24, count 0 2006.224.07:20:19.40#ibcon#read 5, iclass 24, count 0 2006.224.07:20:19.40#ibcon#about to read 6, iclass 24, count 0 2006.224.07:20:19.40#ibcon#read 6, iclass 24, count 0 2006.224.07:20:19.40#ibcon#end of sib2, iclass 24, count 0 2006.224.07:20:19.40#ibcon#*after write, iclass 24, count 0 2006.224.07:20:19.40#ibcon#*before return 0, iclass 24, count 0 2006.224.07:20:19.40#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.224.07:20:19.40#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.224.07:20:19.40#ibcon#about to clear, iclass 24 cls_cnt 0 2006.224.07:20:19.40#ibcon#cleared, iclass 24 cls_cnt 0 2006.224.07:20:19.40$vc4f8/vblo=4,712.99 2006.224.07:20:19.40#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.224.07:20:19.40#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.224.07:20:19.40#ibcon#ireg 17 cls_cnt 0 2006.224.07:20:19.40#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.224.07:20:19.40#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.224.07:20:19.40#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.224.07:20:19.40#ibcon#enter wrdev, iclass 26, count 0 2006.224.07:20:19.40#ibcon#first serial, iclass 26, count 0 2006.224.07:20:19.40#ibcon#enter sib2, iclass 26, count 0 2006.224.07:20:19.40#ibcon#flushed, iclass 26, count 0 2006.224.07:20:19.40#ibcon#about to write, iclass 26, count 0 2006.224.07:20:19.40#ibcon#wrote, iclass 26, count 0 2006.224.07:20:19.40#ibcon#about to read 3, iclass 26, count 0 2006.224.07:20:19.42#ibcon#read 3, iclass 26, count 0 2006.224.07:20:19.42#ibcon#about to read 4, iclass 26, count 0 2006.224.07:20:19.42#ibcon#read 4, iclass 26, count 0 2006.224.07:20:19.42#ibcon#about to read 5, iclass 26, count 0 2006.224.07:20:19.42#ibcon#read 5, iclass 26, count 0 2006.224.07:20:19.42#ibcon#about to read 6, iclass 26, count 0 2006.224.07:20:19.42#ibcon#read 6, iclass 26, count 0 2006.224.07:20:19.42#ibcon#end of sib2, iclass 26, count 0 2006.224.07:20:19.42#ibcon#*mode == 0, iclass 26, count 0 2006.224.07:20:19.42#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.224.07:20:19.42#ibcon#[28=FRQ=04,712.99\r\n] 2006.224.07:20:19.42#ibcon#*before write, iclass 26, count 0 2006.224.07:20:19.42#ibcon#enter sib2, iclass 26, count 0 2006.224.07:20:19.42#ibcon#flushed, iclass 26, count 0 2006.224.07:20:19.42#ibcon#about to write, iclass 26, count 0 2006.224.07:20:19.42#ibcon#wrote, iclass 26, count 0 2006.224.07:20:19.42#ibcon#about to read 3, iclass 26, count 0 2006.224.07:20:19.46#ibcon#read 3, iclass 26, count 0 2006.224.07:20:19.46#ibcon#about to read 4, iclass 26, count 0 2006.224.07:20:19.46#ibcon#read 4, iclass 26, count 0 2006.224.07:20:19.46#ibcon#about to read 5, iclass 26, count 0 2006.224.07:20:19.46#ibcon#read 5, iclass 26, count 0 2006.224.07:20:19.46#ibcon#about to read 6, iclass 26, count 0 2006.224.07:20:19.46#ibcon#read 6, iclass 26, count 0 2006.224.07:20:19.46#ibcon#end of sib2, iclass 26, count 0 2006.224.07:20:19.46#ibcon#*after write, iclass 26, count 0 2006.224.07:20:19.46#ibcon#*before return 0, iclass 26, count 0 2006.224.07:20:19.46#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.224.07:20:19.46#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.224.07:20:19.46#ibcon#about to clear, iclass 26 cls_cnt 0 2006.224.07:20:19.46#ibcon#cleared, iclass 26 cls_cnt 0 2006.224.07:20:19.46$vc4f8/vb=4,4 2006.224.07:20:19.46#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.224.07:20:19.46#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.224.07:20:19.46#ibcon#ireg 11 cls_cnt 2 2006.224.07:20:19.46#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.224.07:20:19.52#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.224.07:20:19.52#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.224.07:20:19.52#ibcon#enter wrdev, iclass 28, count 2 2006.224.07:20:19.52#ibcon#first serial, iclass 28, count 2 2006.224.07:20:19.52#ibcon#enter sib2, iclass 28, count 2 2006.224.07:20:19.52#ibcon#flushed, iclass 28, count 2 2006.224.07:20:19.52#ibcon#about to write, iclass 28, count 2 2006.224.07:20:19.52#ibcon#wrote, iclass 28, count 2 2006.224.07:20:19.52#ibcon#about to read 3, iclass 28, count 2 2006.224.07:20:19.54#ibcon#read 3, iclass 28, count 2 2006.224.07:20:19.54#ibcon#about to read 4, iclass 28, count 2 2006.224.07:20:19.54#ibcon#read 4, iclass 28, count 2 2006.224.07:20:19.54#ibcon#about to read 5, iclass 28, count 2 2006.224.07:20:19.54#ibcon#read 5, iclass 28, count 2 2006.224.07:20:19.54#ibcon#about to read 6, iclass 28, count 2 2006.224.07:20:19.54#ibcon#read 6, iclass 28, count 2 2006.224.07:20:19.54#ibcon#end of sib2, iclass 28, count 2 2006.224.07:20:19.54#ibcon#*mode == 0, iclass 28, count 2 2006.224.07:20:19.54#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.224.07:20:19.54#ibcon#[27=AT04-04\r\n] 2006.224.07:20:19.54#ibcon#*before write, iclass 28, count 2 2006.224.07:20:19.54#ibcon#enter sib2, iclass 28, count 2 2006.224.07:20:19.54#ibcon#flushed, iclass 28, count 2 2006.224.07:20:19.54#ibcon#about to write, iclass 28, count 2 2006.224.07:20:19.54#ibcon#wrote, iclass 28, count 2 2006.224.07:20:19.54#ibcon#about to read 3, iclass 28, count 2 2006.224.07:20:19.57#ibcon#read 3, iclass 28, count 2 2006.224.07:20:19.57#ibcon#about to read 4, iclass 28, count 2 2006.224.07:20:19.57#ibcon#read 4, iclass 28, count 2 2006.224.07:20:19.57#ibcon#about to read 5, iclass 28, count 2 2006.224.07:20:19.57#ibcon#read 5, iclass 28, count 2 2006.224.07:20:19.57#ibcon#about to read 6, iclass 28, count 2 2006.224.07:20:19.57#ibcon#read 6, iclass 28, count 2 2006.224.07:20:19.57#ibcon#end of sib2, iclass 28, count 2 2006.224.07:20:19.57#ibcon#*after write, iclass 28, count 2 2006.224.07:20:19.57#ibcon#*before return 0, iclass 28, count 2 2006.224.07:20:19.57#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.224.07:20:19.57#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.224.07:20:19.57#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.224.07:20:19.57#ibcon#ireg 7 cls_cnt 0 2006.224.07:20:19.57#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.224.07:20:19.69#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.224.07:20:19.69#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.224.07:20:19.69#ibcon#enter wrdev, iclass 28, count 0 2006.224.07:20:19.69#ibcon#first serial, iclass 28, count 0 2006.224.07:20:19.69#ibcon#enter sib2, iclass 28, count 0 2006.224.07:20:19.69#ibcon#flushed, iclass 28, count 0 2006.224.07:20:19.69#ibcon#about to write, iclass 28, count 0 2006.224.07:20:19.69#ibcon#wrote, iclass 28, count 0 2006.224.07:20:19.69#ibcon#about to read 3, iclass 28, count 0 2006.224.07:20:19.71#ibcon#read 3, iclass 28, count 0 2006.224.07:20:19.71#ibcon#about to read 4, iclass 28, count 0 2006.224.07:20:19.71#ibcon#read 4, iclass 28, count 0 2006.224.07:20:19.71#ibcon#about to read 5, iclass 28, count 0 2006.224.07:20:19.71#ibcon#read 5, iclass 28, count 0 2006.224.07:20:19.71#ibcon#about to read 6, iclass 28, count 0 2006.224.07:20:19.71#ibcon#read 6, iclass 28, count 0 2006.224.07:20:19.71#ibcon#end of sib2, iclass 28, count 0 2006.224.07:20:19.71#ibcon#*mode == 0, iclass 28, count 0 2006.224.07:20:19.71#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.224.07:20:19.71#ibcon#[27=USB\r\n] 2006.224.07:20:19.71#ibcon#*before write, iclass 28, count 0 2006.224.07:20:19.71#ibcon#enter sib2, iclass 28, count 0 2006.224.07:20:19.71#ibcon#flushed, iclass 28, count 0 2006.224.07:20:19.71#ibcon#about to write, iclass 28, count 0 2006.224.07:20:19.71#ibcon#wrote, iclass 28, count 0 2006.224.07:20:19.71#ibcon#about to read 3, iclass 28, count 0 2006.224.07:20:19.74#ibcon#read 3, iclass 28, count 0 2006.224.07:20:19.74#ibcon#about to read 4, iclass 28, count 0 2006.224.07:20:19.74#ibcon#read 4, iclass 28, count 0 2006.224.07:20:19.74#ibcon#about to read 5, iclass 28, count 0 2006.224.07:20:19.74#ibcon#read 5, iclass 28, count 0 2006.224.07:20:19.74#ibcon#about to read 6, iclass 28, count 0 2006.224.07:20:19.74#ibcon#read 6, iclass 28, count 0 2006.224.07:20:19.74#ibcon#end of sib2, iclass 28, count 0 2006.224.07:20:19.74#ibcon#*after write, iclass 28, count 0 2006.224.07:20:19.74#ibcon#*before return 0, iclass 28, count 0 2006.224.07:20:19.74#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.224.07:20:19.74#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.224.07:20:19.74#ibcon#about to clear, iclass 28 cls_cnt 0 2006.224.07:20:19.74#ibcon#cleared, iclass 28 cls_cnt 0 2006.224.07:20:19.74$vc4f8/vblo=5,744.99 2006.224.07:20:19.74#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.224.07:20:19.74#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.224.07:20:19.74#ibcon#ireg 17 cls_cnt 0 2006.224.07:20:19.74#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.224.07:20:19.74#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.224.07:20:19.74#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.224.07:20:19.74#ibcon#enter wrdev, iclass 30, count 0 2006.224.07:20:19.74#ibcon#first serial, iclass 30, count 0 2006.224.07:20:19.74#ibcon#enter sib2, iclass 30, count 0 2006.224.07:20:19.74#ibcon#flushed, iclass 30, count 0 2006.224.07:20:19.74#ibcon#about to write, iclass 30, count 0 2006.224.07:20:19.74#ibcon#wrote, iclass 30, count 0 2006.224.07:20:19.74#ibcon#about to read 3, iclass 30, count 0 2006.224.07:20:19.76#ibcon#read 3, iclass 30, count 0 2006.224.07:20:19.76#ibcon#about to read 4, iclass 30, count 0 2006.224.07:20:19.76#ibcon#read 4, iclass 30, count 0 2006.224.07:20:19.76#ibcon#about to read 5, iclass 30, count 0 2006.224.07:20:19.76#ibcon#read 5, iclass 30, count 0 2006.224.07:20:19.76#ibcon#about to read 6, iclass 30, count 0 2006.224.07:20:19.76#ibcon#read 6, iclass 30, count 0 2006.224.07:20:19.76#ibcon#end of sib2, iclass 30, count 0 2006.224.07:20:19.76#ibcon#*mode == 0, iclass 30, count 0 2006.224.07:20:19.76#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.224.07:20:19.76#ibcon#[28=FRQ=05,744.99\r\n] 2006.224.07:20:19.76#ibcon#*before write, iclass 30, count 0 2006.224.07:20:19.76#ibcon#enter sib2, iclass 30, count 0 2006.224.07:20:19.76#ibcon#flushed, iclass 30, count 0 2006.224.07:20:19.76#ibcon#about to write, iclass 30, count 0 2006.224.07:20:19.76#ibcon#wrote, iclass 30, count 0 2006.224.07:20:19.76#ibcon#about to read 3, iclass 30, count 0 2006.224.07:20:19.80#ibcon#read 3, iclass 30, count 0 2006.224.07:20:19.80#ibcon#about to read 4, iclass 30, count 0 2006.224.07:20:19.80#ibcon#read 4, iclass 30, count 0 2006.224.07:20:19.80#ibcon#about to read 5, iclass 30, count 0 2006.224.07:20:19.80#ibcon#read 5, iclass 30, count 0 2006.224.07:20:19.80#ibcon#about to read 6, iclass 30, count 0 2006.224.07:20:19.80#ibcon#read 6, iclass 30, count 0 2006.224.07:20:19.80#ibcon#end of sib2, iclass 30, count 0 2006.224.07:20:19.80#ibcon#*after write, iclass 30, count 0 2006.224.07:20:19.80#ibcon#*before return 0, iclass 30, count 0 2006.224.07:20:19.80#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.224.07:20:19.80#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.224.07:20:19.80#ibcon#about to clear, iclass 30 cls_cnt 0 2006.224.07:20:19.80#ibcon#cleared, iclass 30 cls_cnt 0 2006.224.07:20:19.80$vc4f8/vb=5,4 2006.224.07:20:19.80#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.224.07:20:19.80#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.224.07:20:19.80#ibcon#ireg 11 cls_cnt 2 2006.224.07:20:19.80#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.224.07:20:19.86#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.224.07:20:19.86#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.224.07:20:19.86#ibcon#enter wrdev, iclass 32, count 2 2006.224.07:20:19.86#ibcon#first serial, iclass 32, count 2 2006.224.07:20:19.86#ibcon#enter sib2, iclass 32, count 2 2006.224.07:20:19.86#ibcon#flushed, iclass 32, count 2 2006.224.07:20:19.86#ibcon#about to write, iclass 32, count 2 2006.224.07:20:19.86#ibcon#wrote, iclass 32, count 2 2006.224.07:20:19.86#ibcon#about to read 3, iclass 32, count 2 2006.224.07:20:19.88#ibcon#read 3, iclass 32, count 2 2006.224.07:20:19.88#ibcon#about to read 4, iclass 32, count 2 2006.224.07:20:19.88#ibcon#read 4, iclass 32, count 2 2006.224.07:20:19.88#ibcon#about to read 5, iclass 32, count 2 2006.224.07:20:19.88#ibcon#read 5, iclass 32, count 2 2006.224.07:20:19.88#ibcon#about to read 6, iclass 32, count 2 2006.224.07:20:19.88#ibcon#read 6, iclass 32, count 2 2006.224.07:20:19.88#ibcon#end of sib2, iclass 32, count 2 2006.224.07:20:19.88#ibcon#*mode == 0, iclass 32, count 2 2006.224.07:20:19.88#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.224.07:20:19.88#ibcon#[27=AT05-04\r\n] 2006.224.07:20:19.88#ibcon#*before write, iclass 32, count 2 2006.224.07:20:19.88#ibcon#enter sib2, iclass 32, count 2 2006.224.07:20:19.88#ibcon#flushed, iclass 32, count 2 2006.224.07:20:19.88#ibcon#about to write, iclass 32, count 2 2006.224.07:20:19.88#ibcon#wrote, iclass 32, count 2 2006.224.07:20:19.88#ibcon#about to read 3, iclass 32, count 2 2006.224.07:20:19.91#ibcon#read 3, iclass 32, count 2 2006.224.07:20:19.91#ibcon#about to read 4, iclass 32, count 2 2006.224.07:20:19.91#ibcon#read 4, iclass 32, count 2 2006.224.07:20:19.91#ibcon#about to read 5, iclass 32, count 2 2006.224.07:20:19.91#ibcon#read 5, iclass 32, count 2 2006.224.07:20:19.91#ibcon#about to read 6, iclass 32, count 2 2006.224.07:20:19.91#ibcon#read 6, iclass 32, count 2 2006.224.07:20:19.91#ibcon#end of sib2, iclass 32, count 2 2006.224.07:20:19.91#ibcon#*after write, iclass 32, count 2 2006.224.07:20:19.91#ibcon#*before return 0, iclass 32, count 2 2006.224.07:20:19.91#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.224.07:20:19.91#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.224.07:20:19.91#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.224.07:20:19.91#ibcon#ireg 7 cls_cnt 0 2006.224.07:20:19.91#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.224.07:20:20.03#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.224.07:20:20.03#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.224.07:20:20.03#ibcon#enter wrdev, iclass 32, count 0 2006.224.07:20:20.03#ibcon#first serial, iclass 32, count 0 2006.224.07:20:20.03#ibcon#enter sib2, iclass 32, count 0 2006.224.07:20:20.03#ibcon#flushed, iclass 32, count 0 2006.224.07:20:20.03#ibcon#about to write, iclass 32, count 0 2006.224.07:20:20.03#ibcon#wrote, iclass 32, count 0 2006.224.07:20:20.03#ibcon#about to read 3, iclass 32, count 0 2006.224.07:20:20.05#ibcon#read 3, iclass 32, count 0 2006.224.07:20:20.05#ibcon#about to read 4, iclass 32, count 0 2006.224.07:20:20.05#ibcon#read 4, iclass 32, count 0 2006.224.07:20:20.05#ibcon#about to read 5, iclass 32, count 0 2006.224.07:20:20.05#ibcon#read 5, iclass 32, count 0 2006.224.07:20:20.05#ibcon#about to read 6, iclass 32, count 0 2006.224.07:20:20.05#ibcon#read 6, iclass 32, count 0 2006.224.07:20:20.05#ibcon#end of sib2, iclass 32, count 0 2006.224.07:20:20.05#ibcon#*mode == 0, iclass 32, count 0 2006.224.07:20:20.05#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.224.07:20:20.05#ibcon#[27=USB\r\n] 2006.224.07:20:20.05#ibcon#*before write, iclass 32, count 0 2006.224.07:20:20.05#ibcon#enter sib2, iclass 32, count 0 2006.224.07:20:20.05#ibcon#flushed, iclass 32, count 0 2006.224.07:20:20.05#ibcon#about to write, iclass 32, count 0 2006.224.07:20:20.05#ibcon#wrote, iclass 32, count 0 2006.224.07:20:20.05#ibcon#about to read 3, iclass 32, count 0 2006.224.07:20:20.08#ibcon#read 3, iclass 32, count 0 2006.224.07:20:20.08#ibcon#about to read 4, iclass 32, count 0 2006.224.07:20:20.08#ibcon#read 4, iclass 32, count 0 2006.224.07:20:20.08#ibcon#about to read 5, iclass 32, count 0 2006.224.07:20:20.08#ibcon#read 5, iclass 32, count 0 2006.224.07:20:20.08#ibcon#about to read 6, iclass 32, count 0 2006.224.07:20:20.08#ibcon#read 6, iclass 32, count 0 2006.224.07:20:20.08#ibcon#end of sib2, iclass 32, count 0 2006.224.07:20:20.08#ibcon#*after write, iclass 32, count 0 2006.224.07:20:20.08#ibcon#*before return 0, iclass 32, count 0 2006.224.07:20:20.08#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.224.07:20:20.08#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.224.07:20:20.08#ibcon#about to clear, iclass 32 cls_cnt 0 2006.224.07:20:20.08#ibcon#cleared, iclass 32 cls_cnt 0 2006.224.07:20:20.08$vc4f8/vblo=6,752.99 2006.224.07:20:20.08#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.224.07:20:20.08#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.224.07:20:20.08#ibcon#ireg 17 cls_cnt 0 2006.224.07:20:20.08#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.224.07:20:20.08#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.224.07:20:20.08#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.224.07:20:20.08#ibcon#enter wrdev, iclass 34, count 0 2006.224.07:20:20.08#ibcon#first serial, iclass 34, count 0 2006.224.07:20:20.08#ibcon#enter sib2, iclass 34, count 0 2006.224.07:20:20.08#ibcon#flushed, iclass 34, count 0 2006.224.07:20:20.08#ibcon#about to write, iclass 34, count 0 2006.224.07:20:20.08#ibcon#wrote, iclass 34, count 0 2006.224.07:20:20.08#ibcon#about to read 3, iclass 34, count 0 2006.224.07:20:20.10#ibcon#read 3, iclass 34, count 0 2006.224.07:20:20.10#ibcon#about to read 4, iclass 34, count 0 2006.224.07:20:20.10#ibcon#read 4, iclass 34, count 0 2006.224.07:20:20.10#ibcon#about to read 5, iclass 34, count 0 2006.224.07:20:20.10#ibcon#read 5, iclass 34, count 0 2006.224.07:20:20.10#ibcon#about to read 6, iclass 34, count 0 2006.224.07:20:20.10#ibcon#read 6, iclass 34, count 0 2006.224.07:20:20.10#ibcon#end of sib2, iclass 34, count 0 2006.224.07:20:20.10#ibcon#*mode == 0, iclass 34, count 0 2006.224.07:20:20.10#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.224.07:20:20.10#ibcon#[28=FRQ=06,752.99\r\n] 2006.224.07:20:20.10#ibcon#*before write, iclass 34, count 0 2006.224.07:20:20.10#ibcon#enter sib2, iclass 34, count 0 2006.224.07:20:20.10#ibcon#flushed, iclass 34, count 0 2006.224.07:20:20.10#ibcon#about to write, iclass 34, count 0 2006.224.07:20:20.10#ibcon#wrote, iclass 34, count 0 2006.224.07:20:20.10#ibcon#about to read 3, iclass 34, count 0 2006.224.07:20:20.14#ibcon#read 3, iclass 34, count 0 2006.224.07:20:20.14#ibcon#about to read 4, iclass 34, count 0 2006.224.07:20:20.14#ibcon#read 4, iclass 34, count 0 2006.224.07:20:20.14#ibcon#about to read 5, iclass 34, count 0 2006.224.07:20:20.14#ibcon#read 5, iclass 34, count 0 2006.224.07:20:20.14#ibcon#about to read 6, iclass 34, count 0 2006.224.07:20:20.14#ibcon#read 6, iclass 34, count 0 2006.224.07:20:20.14#ibcon#end of sib2, iclass 34, count 0 2006.224.07:20:20.14#ibcon#*after write, iclass 34, count 0 2006.224.07:20:20.14#ibcon#*before return 0, iclass 34, count 0 2006.224.07:20:20.14#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.224.07:20:20.14#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.224.07:20:20.14#ibcon#about to clear, iclass 34 cls_cnt 0 2006.224.07:20:20.14#ibcon#cleared, iclass 34 cls_cnt 0 2006.224.07:20:20.14$vc4f8/vb=6,4 2006.224.07:20:20.14#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.224.07:20:20.14#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.224.07:20:20.14#ibcon#ireg 11 cls_cnt 2 2006.224.07:20:20.14#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.224.07:20:20.20#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.224.07:20:20.20#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.224.07:20:20.20#ibcon#enter wrdev, iclass 36, count 2 2006.224.07:20:20.20#ibcon#first serial, iclass 36, count 2 2006.224.07:20:20.20#ibcon#enter sib2, iclass 36, count 2 2006.224.07:20:20.20#ibcon#flushed, iclass 36, count 2 2006.224.07:20:20.20#ibcon#about to write, iclass 36, count 2 2006.224.07:20:20.20#ibcon#wrote, iclass 36, count 2 2006.224.07:20:20.20#ibcon#about to read 3, iclass 36, count 2 2006.224.07:20:20.22#ibcon#read 3, iclass 36, count 2 2006.224.07:20:20.22#ibcon#about to read 4, iclass 36, count 2 2006.224.07:20:20.22#ibcon#read 4, iclass 36, count 2 2006.224.07:20:20.22#ibcon#about to read 5, iclass 36, count 2 2006.224.07:20:20.22#ibcon#read 5, iclass 36, count 2 2006.224.07:20:20.22#ibcon#about to read 6, iclass 36, count 2 2006.224.07:20:20.22#ibcon#read 6, iclass 36, count 2 2006.224.07:20:20.22#ibcon#end of sib2, iclass 36, count 2 2006.224.07:20:20.22#ibcon#*mode == 0, iclass 36, count 2 2006.224.07:20:20.22#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.224.07:20:20.22#ibcon#[27=AT06-04\r\n] 2006.224.07:20:20.22#ibcon#*before write, iclass 36, count 2 2006.224.07:20:20.22#ibcon#enter sib2, iclass 36, count 2 2006.224.07:20:20.22#ibcon#flushed, iclass 36, count 2 2006.224.07:20:20.22#ibcon#about to write, iclass 36, count 2 2006.224.07:20:20.22#ibcon#wrote, iclass 36, count 2 2006.224.07:20:20.22#ibcon#about to read 3, iclass 36, count 2 2006.224.07:20:20.25#ibcon#read 3, iclass 36, count 2 2006.224.07:20:20.25#ibcon#about to read 4, iclass 36, count 2 2006.224.07:20:20.25#ibcon#read 4, iclass 36, count 2 2006.224.07:20:20.25#ibcon#about to read 5, iclass 36, count 2 2006.224.07:20:20.25#ibcon#read 5, iclass 36, count 2 2006.224.07:20:20.25#ibcon#about to read 6, iclass 36, count 2 2006.224.07:20:20.25#ibcon#read 6, iclass 36, count 2 2006.224.07:20:20.25#ibcon#end of sib2, iclass 36, count 2 2006.224.07:20:20.25#ibcon#*after write, iclass 36, count 2 2006.224.07:20:20.25#ibcon#*before return 0, iclass 36, count 2 2006.224.07:20:20.25#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.224.07:20:20.25#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.224.07:20:20.25#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.224.07:20:20.25#ibcon#ireg 7 cls_cnt 0 2006.224.07:20:20.25#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.224.07:20:20.37#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.224.07:20:20.37#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.224.07:20:20.37#ibcon#enter wrdev, iclass 36, count 0 2006.224.07:20:20.37#ibcon#first serial, iclass 36, count 0 2006.224.07:20:20.37#ibcon#enter sib2, iclass 36, count 0 2006.224.07:20:20.37#ibcon#flushed, iclass 36, count 0 2006.224.07:20:20.37#ibcon#about to write, iclass 36, count 0 2006.224.07:20:20.37#ibcon#wrote, iclass 36, count 0 2006.224.07:20:20.37#ibcon#about to read 3, iclass 36, count 0 2006.224.07:20:20.39#ibcon#read 3, iclass 36, count 0 2006.224.07:20:20.39#ibcon#about to read 4, iclass 36, count 0 2006.224.07:20:20.39#ibcon#read 4, iclass 36, count 0 2006.224.07:20:20.39#ibcon#about to read 5, iclass 36, count 0 2006.224.07:20:20.39#ibcon#read 5, iclass 36, count 0 2006.224.07:20:20.39#ibcon#about to read 6, iclass 36, count 0 2006.224.07:20:20.39#ibcon#read 6, iclass 36, count 0 2006.224.07:20:20.39#ibcon#end of sib2, iclass 36, count 0 2006.224.07:20:20.39#ibcon#*mode == 0, iclass 36, count 0 2006.224.07:20:20.39#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.224.07:20:20.39#ibcon#[27=USB\r\n] 2006.224.07:20:20.39#ibcon#*before write, iclass 36, count 0 2006.224.07:20:20.39#ibcon#enter sib2, iclass 36, count 0 2006.224.07:20:20.39#ibcon#flushed, iclass 36, count 0 2006.224.07:20:20.39#ibcon#about to write, iclass 36, count 0 2006.224.07:20:20.39#ibcon#wrote, iclass 36, count 0 2006.224.07:20:20.39#ibcon#about to read 3, iclass 36, count 0 2006.224.07:20:20.42#ibcon#read 3, iclass 36, count 0 2006.224.07:20:20.42#ibcon#about to read 4, iclass 36, count 0 2006.224.07:20:20.42#ibcon#read 4, iclass 36, count 0 2006.224.07:20:20.42#ibcon#about to read 5, iclass 36, count 0 2006.224.07:20:20.42#ibcon#read 5, iclass 36, count 0 2006.224.07:20:20.42#ibcon#about to read 6, iclass 36, count 0 2006.224.07:20:20.42#ibcon#read 6, iclass 36, count 0 2006.224.07:20:20.42#ibcon#end of sib2, iclass 36, count 0 2006.224.07:20:20.42#ibcon#*after write, iclass 36, count 0 2006.224.07:20:20.42#ibcon#*before return 0, iclass 36, count 0 2006.224.07:20:20.42#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.224.07:20:20.42#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.224.07:20:20.42#ibcon#about to clear, iclass 36 cls_cnt 0 2006.224.07:20:20.42#ibcon#cleared, iclass 36 cls_cnt 0 2006.224.07:20:20.42$vc4f8/vabw=wide 2006.224.07:20:20.42#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.224.07:20:20.42#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.224.07:20:20.42#ibcon#ireg 8 cls_cnt 0 2006.224.07:20:20.42#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.224.07:20:20.42#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.224.07:20:20.42#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.224.07:20:20.42#ibcon#enter wrdev, iclass 38, count 0 2006.224.07:20:20.42#ibcon#first serial, iclass 38, count 0 2006.224.07:20:20.42#ibcon#enter sib2, iclass 38, count 0 2006.224.07:20:20.42#ibcon#flushed, iclass 38, count 0 2006.224.07:20:20.42#ibcon#about to write, iclass 38, count 0 2006.224.07:20:20.42#ibcon#wrote, iclass 38, count 0 2006.224.07:20:20.42#ibcon#about to read 3, iclass 38, count 0 2006.224.07:20:20.44#ibcon#read 3, iclass 38, count 0 2006.224.07:20:20.44#ibcon#about to read 4, iclass 38, count 0 2006.224.07:20:20.44#ibcon#read 4, iclass 38, count 0 2006.224.07:20:20.44#ibcon#about to read 5, iclass 38, count 0 2006.224.07:20:20.44#ibcon#read 5, iclass 38, count 0 2006.224.07:20:20.44#ibcon#about to read 6, iclass 38, count 0 2006.224.07:20:20.44#ibcon#read 6, iclass 38, count 0 2006.224.07:20:20.44#ibcon#end of sib2, iclass 38, count 0 2006.224.07:20:20.44#ibcon#*mode == 0, iclass 38, count 0 2006.224.07:20:20.44#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.224.07:20:20.44#ibcon#[25=BW32\r\n] 2006.224.07:20:20.44#ibcon#*before write, iclass 38, count 0 2006.224.07:20:20.44#ibcon#enter sib2, iclass 38, count 0 2006.224.07:20:20.44#ibcon#flushed, iclass 38, count 0 2006.224.07:20:20.44#ibcon#about to write, iclass 38, count 0 2006.224.07:20:20.44#ibcon#wrote, iclass 38, count 0 2006.224.07:20:20.44#ibcon#about to read 3, iclass 38, count 0 2006.224.07:20:20.47#ibcon#read 3, iclass 38, count 0 2006.224.07:20:20.47#ibcon#about to read 4, iclass 38, count 0 2006.224.07:20:20.47#ibcon#read 4, iclass 38, count 0 2006.224.07:20:20.47#ibcon#about to read 5, iclass 38, count 0 2006.224.07:20:20.47#ibcon#read 5, iclass 38, count 0 2006.224.07:20:20.47#ibcon#about to read 6, iclass 38, count 0 2006.224.07:20:20.47#ibcon#read 6, iclass 38, count 0 2006.224.07:20:20.47#ibcon#end of sib2, iclass 38, count 0 2006.224.07:20:20.47#ibcon#*after write, iclass 38, count 0 2006.224.07:20:20.47#ibcon#*before return 0, iclass 38, count 0 2006.224.07:20:20.47#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.224.07:20:20.47#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.224.07:20:20.47#ibcon#about to clear, iclass 38 cls_cnt 0 2006.224.07:20:20.47#ibcon#cleared, iclass 38 cls_cnt 0 2006.224.07:20:20.47$vc4f8/vbbw=wide 2006.224.07:20:20.47#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.224.07:20:20.47#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.224.07:20:20.47#ibcon#ireg 8 cls_cnt 0 2006.224.07:20:20.47#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.224.07:20:20.54#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.224.07:20:20.54#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.224.07:20:20.54#ibcon#enter wrdev, iclass 40, count 0 2006.224.07:20:20.54#ibcon#first serial, iclass 40, count 0 2006.224.07:20:20.54#ibcon#enter sib2, iclass 40, count 0 2006.224.07:20:20.54#ibcon#flushed, iclass 40, count 0 2006.224.07:20:20.54#ibcon#about to write, iclass 40, count 0 2006.224.07:20:20.54#ibcon#wrote, iclass 40, count 0 2006.224.07:20:20.54#ibcon#about to read 3, iclass 40, count 0 2006.224.07:20:20.56#ibcon#read 3, iclass 40, count 0 2006.224.07:20:20.56#ibcon#about to read 4, iclass 40, count 0 2006.224.07:20:20.56#ibcon#read 4, iclass 40, count 0 2006.224.07:20:20.56#ibcon#about to read 5, iclass 40, count 0 2006.224.07:20:20.56#ibcon#read 5, iclass 40, count 0 2006.224.07:20:20.56#ibcon#about to read 6, iclass 40, count 0 2006.224.07:20:20.56#ibcon#read 6, iclass 40, count 0 2006.224.07:20:20.56#ibcon#end of sib2, iclass 40, count 0 2006.224.07:20:20.56#ibcon#*mode == 0, iclass 40, count 0 2006.224.07:20:20.56#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.224.07:20:20.56#ibcon#[27=BW32\r\n] 2006.224.07:20:20.56#ibcon#*before write, iclass 40, count 0 2006.224.07:20:20.56#ibcon#enter sib2, iclass 40, count 0 2006.224.07:20:20.56#ibcon#flushed, iclass 40, count 0 2006.224.07:20:20.56#ibcon#about to write, iclass 40, count 0 2006.224.07:20:20.56#ibcon#wrote, iclass 40, count 0 2006.224.07:20:20.56#ibcon#about to read 3, iclass 40, count 0 2006.224.07:20:20.59#ibcon#read 3, iclass 40, count 0 2006.224.07:20:20.59#ibcon#about to read 4, iclass 40, count 0 2006.224.07:20:20.59#ibcon#read 4, iclass 40, count 0 2006.224.07:20:20.59#ibcon#about to read 5, iclass 40, count 0 2006.224.07:20:20.59#ibcon#read 5, iclass 40, count 0 2006.224.07:20:20.59#ibcon#about to read 6, iclass 40, count 0 2006.224.07:20:20.59#ibcon#read 6, iclass 40, count 0 2006.224.07:20:20.59#ibcon#end of sib2, iclass 40, count 0 2006.224.07:20:20.59#ibcon#*after write, iclass 40, count 0 2006.224.07:20:20.59#ibcon#*before return 0, iclass 40, count 0 2006.224.07:20:20.59#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.224.07:20:20.59#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.224.07:20:20.59#ibcon#about to clear, iclass 40 cls_cnt 0 2006.224.07:20:20.59#ibcon#cleared, iclass 40 cls_cnt 0 2006.224.07:20:20.59$4f8m12a/ifd4f 2006.224.07:20:20.59&ifd4f/lo= 2006.224.07:20:20.59&ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.224.07:20:20.59&ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.224.07:20:20.59&ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.224.07:20:20.59&ifd4f/patch= 2006.224.07:20:20.59&ifd4f/patch=lo1,a1,a2,a3,a4 2006.224.07:20:20.59&ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.224.07:20:20.59&ifd4f/patch=lo3,a5,a6,a7,a8 2006.224.07:20:20.59$ifd4f/lo= 2006.224.07:20:20.59$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.224.07:20:20.59$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.224.07:20:20.59$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.224.07:20:20.59$ifd4f/patch= 2006.224.07:20:20.59$ifd4f/patch=lo1,a1,a2,a3,a4 2006.224.07:20:20.59$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.224.07:20:20.59$ifd4f/patch=lo3,a5,a6,a7,a8 2006.224.07:20:20.59$4f8m12a/"form=m,16.000,1:2 2006.224.07:20:20.59$4f8m12a/"tpicd 2006.224.07:20:20.59$4f8m12a/echo=off 2006.224.07:20:20.59$4f8m12a/xlog=off 2006.224.07:20:20.59:!2006.224.07:29:50 2006.224.07:20:39.13#trakl#Source acquired 2006.224.07:20:41.13#flagr#flagr/antenna,acquired 2006.224.07:29:50.00:preob 2006.224.07:29:50.00&preob/onsource 2006.224.07:29:51.13/onsource/TRACKING 2006.224.07:29:51.13:!2006.224.07:30:00 2006.224.07:30:00.00:data_valid=on 2006.224.07:30:00.00:midob 2006.224.07:30:00.00&midob/onsource 2006.224.07:30:00.00&midob/wx 2006.224.07:30:00.00&midob/cable 2006.224.07:30:00.00&midob/va 2006.224.07:30:00.00&midob/valo 2006.224.07:30:00.00&midob/vb 2006.224.07:30:00.00&midob/vblo 2006.224.07:30:00.00&midob/vabw 2006.224.07:30:00.00&midob/vbbw 2006.224.07:30:00.00&midob/"form 2006.224.07:30:00.00&midob/xfe 2006.224.07:30:00.00&midob/ifatt 2006.224.07:30:00.00&midob/clockoff 2006.224.07:30:00.00&midob/sy=logmail 2006.224.07:30:00.00&midob/"sy=run setcl adapt & 2006.224.07:30:00.13/onsource/TRACKING 2006.224.07:30:00.13/wx/23.36,1004.1,100 2006.224.07:30:00.22/cable/+6.4307E-03 2006.224.07:30:01.31/va/01,08,usb,yes,38,40 2006.224.07:30:01.31/va/02,07,usb,yes,38,40 2006.224.07:30:01.31/va/03,06,usb,yes,41,41 2006.224.07:30:01.31/va/04,07,usb,yes,40,43 2006.224.07:30:01.31/va/05,07,usb,yes,47,50 2006.224.07:30:01.31/va/06,06,usb,yes,47,46 2006.224.07:30:01.31/va/07,06,usb,yes,48,47 2006.224.07:30:01.31/va/08,07,usb,yes,45,44 2006.224.07:30:01.54/valo/01,532.99,yes,locked 2006.224.07:30:01.54/valo/02,572.99,yes,locked 2006.224.07:30:01.54/valo/03,672.99,yes,locked 2006.224.07:30:01.54/valo/04,832.99,yes,locked 2006.224.07:30:01.54/valo/05,652.99,yes,locked 2006.224.07:30:01.54/valo/06,772.99,yes,locked 2006.224.07:30:01.54/valo/07,832.99,yes,locked 2006.224.07:30:01.54/valo/08,852.99,yes,locked 2006.224.07:30:02.63/vb/01,04,usb,yes,32,31 2006.224.07:30:02.63/vb/02,04,usb,yes,34,36 2006.224.07:30:02.63/vb/03,04,usb,yes,31,35 2006.224.07:30:02.63/vb/04,04,usb,yes,31,32 2006.224.07:30:02.63/vb/05,04,usb,yes,30,34 2006.224.07:30:02.63/vb/06,04,usb,yes,31,34 2006.224.07:30:02.63/vb/07,04,usb,yes,33,33 2006.224.07:30:02.63/vb/08,04,usb,yes,30,34 2006.224.07:30:02.86/vblo/01,632.99,yes,locked 2006.224.07:30:02.86/vblo/02,640.99,yes,locked 2006.224.07:30:02.86/vblo/03,656.99,yes,locked 2006.224.07:30:02.86/vblo/04,712.99,yes,locked 2006.224.07:30:02.86/vblo/05,744.99,yes,locked 2006.224.07:30:02.86/vblo/06,752.99,yes,locked 2006.224.07:30:02.86/vblo/07,734.99,yes,locked 2006.224.07:30:02.86/vblo/08,744.99,yes,locked 2006.224.07:30:03.01/vabw/8 2006.224.07:30:03.16/vbbw/8 2006.224.07:30:03.25/xfe/off,on,15.0 2006.224.07:30:03.64/ifatt/23,28,28,28 2006.224.07:30:04.08/fmout-gps/S +4.44E-07 2006.224.07:30:04.16:!2006.224.07:31:00 2006.224.07:31:00.00:data_valid=off 2006.224.07:31:00.00:postob 2006.224.07:31:00.00&postob/cable 2006.224.07:31:00.01&postob/wx 2006.224.07:31:00.01&postob/clockoff 2006.224.07:31:00.23/cable/+6.4297E-03 2006.224.07:31:00.23/wx/23.36,1004.1,100 2006.224.07:31:01.08/fmout-gps/S +4.42E-07 2006.224.07:31:01.08:scan_name=224-0733,k06224,60 2006.224.07:31:01.09:source=0743+259,074625.87,254902.1,2000.0,ccw 2006.224.07:31:01.14#flagr#flagr/antenna,new-source 2006.224.07:31:02.14:checkk5 2006.224.07:31:02.14&checkk5/chk_autoobs=1 2006.224.07:31:02.15&checkk5/chk_autoobs=2 2006.224.07:31:02.15&checkk5/chk_autoobs=3 2006.224.07:31:02.15&checkk5/chk_autoobs=4 2006.224.07:31:02.16&checkk5/chk_obsdata=1 2006.224.07:31:02.16&checkk5/chk_obsdata=2 2006.224.07:31:02.16&checkk5/chk_obsdata=3 2006.224.07:31:02.17&checkk5/chk_obsdata=4 2006.224.07:31:02.17&checkk5/k5log=1 2006.224.07:31:02.17&checkk5/k5log=2 2006.224.07:31:02.18&checkk5/k5log=3 2006.224.07:31:02.20&checkk5/k5log=4 2006.224.07:31:02.20&checkk5/obsinfo 2006.224.07:31:02.57/chk_autoobs//k5ts1/ autoobs is running! 2006.224.07:31:03.03/chk_autoobs//k5ts2/ autoobs is running! 2006.224.07:31:03.41/chk_autoobs//k5ts3/ autoobs is running! 2006.224.07:31:03.80/chk_autoobs//k5ts4/ autoobs is running! 2006.224.07:31:04.17/chk_obsdata//k5ts1/T2240730??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.07:31:04.54/chk_obsdata//k5ts2/T2240730??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.07:31:04.91/chk_obsdata//k5ts3/T2240730??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.07:31:05.28/chk_obsdata//k5ts4/T2240730??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.07:31:05.99/k5log//k5ts1_log_newline 2006.224.07:31:06.66/k5log//k5ts2_log_newline 2006.224.07:31:07.34/k5log//k5ts3_log_newline 2006.224.07:31:08.03/k5log//k5ts4_log_newline 2006.224.07:31:08.08/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.224.07:31:08.08:4f8m12a=1 2006.224.07:31:08.08$4f8m12a/echo=on 2006.224.07:31:08.08$4f8m12a/pcalon 2006.224.07:31:08.08$pcalon/"no phase cal control is implemented here 2006.224.07:31:08.08$4f8m12a/"tpicd=stop 2006.224.07:31:08.08$4f8m12a/vc4f8 2006.224.07:31:08.08$vc4f8/valo=1,532.99 2006.224.07:31:08.08#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.224.07:31:08.08#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.224.07:31:08.08#ibcon#ireg 17 cls_cnt 0 2006.224.07:31:08.08#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.224.07:31:08.08#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.224.07:31:08.08#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.224.07:31:08.08#ibcon#enter wrdev, iclass 11, count 0 2006.224.07:31:08.08#ibcon#first serial, iclass 11, count 0 2006.224.07:31:08.08#ibcon#enter sib2, iclass 11, count 0 2006.224.07:31:08.08#ibcon#flushed, iclass 11, count 0 2006.224.07:31:08.08#ibcon#about to write, iclass 11, count 0 2006.224.07:31:08.08#ibcon#wrote, iclass 11, count 0 2006.224.07:31:08.08#ibcon#about to read 3, iclass 11, count 0 2006.224.07:31:08.10#ibcon#read 3, iclass 11, count 0 2006.224.07:31:08.10#ibcon#about to read 4, iclass 11, count 0 2006.224.07:31:08.10#ibcon#read 4, iclass 11, count 0 2006.224.07:31:08.10#ibcon#about to read 5, iclass 11, count 0 2006.224.07:31:08.10#ibcon#read 5, iclass 11, count 0 2006.224.07:31:08.10#ibcon#about to read 6, iclass 11, count 0 2006.224.07:31:08.10#ibcon#read 6, iclass 11, count 0 2006.224.07:31:08.10#ibcon#end of sib2, iclass 11, count 0 2006.224.07:31:08.10#ibcon#*mode == 0, iclass 11, count 0 2006.224.07:31:08.10#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.224.07:31:08.10#ibcon#[26=FRQ=01,532.99\r\n] 2006.224.07:31:08.10#ibcon#*before write, iclass 11, count 0 2006.224.07:31:08.10#ibcon#enter sib2, iclass 11, count 0 2006.224.07:31:08.10#ibcon#flushed, iclass 11, count 0 2006.224.07:31:08.10#ibcon#about to write, iclass 11, count 0 2006.224.07:31:08.10#ibcon#wrote, iclass 11, count 0 2006.224.07:31:08.10#ibcon#about to read 3, iclass 11, count 0 2006.224.07:31:08.15#ibcon#read 3, iclass 11, count 0 2006.224.07:31:08.15#ibcon#about to read 4, iclass 11, count 0 2006.224.07:31:08.15#ibcon#read 4, iclass 11, count 0 2006.224.07:31:08.15#ibcon#about to read 5, iclass 11, count 0 2006.224.07:31:08.15#ibcon#read 5, iclass 11, count 0 2006.224.07:31:08.15#ibcon#about to read 6, iclass 11, count 0 2006.224.07:31:08.15#ibcon#read 6, iclass 11, count 0 2006.224.07:31:08.15#ibcon#end of sib2, iclass 11, count 0 2006.224.07:31:08.15#ibcon#*after write, iclass 11, count 0 2006.224.07:31:08.15#ibcon#*before return 0, iclass 11, count 0 2006.224.07:31:08.15#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.224.07:31:08.15#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.224.07:31:08.15#ibcon#about to clear, iclass 11 cls_cnt 0 2006.224.07:31:08.15#ibcon#cleared, iclass 11 cls_cnt 0 2006.224.07:31:08.15$vc4f8/va=1,8 2006.224.07:31:08.15#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.224.07:31:08.15#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.224.07:31:08.15#ibcon#ireg 11 cls_cnt 2 2006.224.07:31:08.15#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.224.07:31:08.15#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.224.07:31:08.15#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.224.07:31:08.15#ibcon#enter wrdev, iclass 13, count 2 2006.224.07:31:08.15#ibcon#first serial, iclass 13, count 2 2006.224.07:31:08.15#ibcon#enter sib2, iclass 13, count 2 2006.224.07:31:08.15#ibcon#flushed, iclass 13, count 2 2006.224.07:31:08.15#ibcon#about to write, iclass 13, count 2 2006.224.07:31:08.15#ibcon#wrote, iclass 13, count 2 2006.224.07:31:08.15#ibcon#about to read 3, iclass 13, count 2 2006.224.07:31:08.17#ibcon#read 3, iclass 13, count 2 2006.224.07:31:08.17#ibcon#about to read 4, iclass 13, count 2 2006.224.07:31:08.17#ibcon#read 4, iclass 13, count 2 2006.224.07:31:08.17#ibcon#about to read 5, iclass 13, count 2 2006.224.07:31:08.17#ibcon#read 5, iclass 13, count 2 2006.224.07:31:08.17#ibcon#about to read 6, iclass 13, count 2 2006.224.07:31:08.17#ibcon#read 6, iclass 13, count 2 2006.224.07:31:08.17#ibcon#end of sib2, iclass 13, count 2 2006.224.07:31:08.17#ibcon#*mode == 0, iclass 13, count 2 2006.224.07:31:08.17#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.224.07:31:08.17#ibcon#[25=AT01-08\r\n] 2006.224.07:31:08.17#ibcon#*before write, iclass 13, count 2 2006.224.07:31:08.17#ibcon#enter sib2, iclass 13, count 2 2006.224.07:31:08.17#ibcon#flushed, iclass 13, count 2 2006.224.07:31:08.17#ibcon#about to write, iclass 13, count 2 2006.224.07:31:08.17#ibcon#wrote, iclass 13, count 2 2006.224.07:31:08.17#ibcon#about to read 3, iclass 13, count 2 2006.224.07:31:08.20#ibcon#read 3, iclass 13, count 2 2006.224.07:31:08.20#ibcon#about to read 4, iclass 13, count 2 2006.224.07:31:08.20#ibcon#read 4, iclass 13, count 2 2006.224.07:31:08.20#ibcon#about to read 5, iclass 13, count 2 2006.224.07:31:08.20#ibcon#read 5, iclass 13, count 2 2006.224.07:31:08.20#ibcon#about to read 6, iclass 13, count 2 2006.224.07:31:08.20#ibcon#read 6, iclass 13, count 2 2006.224.07:31:08.20#ibcon#end of sib2, iclass 13, count 2 2006.224.07:31:08.20#ibcon#*after write, iclass 13, count 2 2006.224.07:31:08.20#ibcon#*before return 0, iclass 13, count 2 2006.224.07:31:08.20#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.224.07:31:08.20#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.224.07:31:08.20#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.224.07:31:08.20#ibcon#ireg 7 cls_cnt 0 2006.224.07:31:08.20#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.224.07:31:08.32#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.224.07:31:08.32#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.224.07:31:08.32#ibcon#enter wrdev, iclass 13, count 0 2006.224.07:31:08.32#ibcon#first serial, iclass 13, count 0 2006.224.07:31:08.32#ibcon#enter sib2, iclass 13, count 0 2006.224.07:31:08.32#ibcon#flushed, iclass 13, count 0 2006.224.07:31:08.32#ibcon#about to write, iclass 13, count 0 2006.224.07:31:08.32#ibcon#wrote, iclass 13, count 0 2006.224.07:31:08.32#ibcon#about to read 3, iclass 13, count 0 2006.224.07:31:08.34#ibcon#read 3, iclass 13, count 0 2006.224.07:31:08.34#ibcon#about to read 4, iclass 13, count 0 2006.224.07:31:08.34#ibcon#read 4, iclass 13, count 0 2006.224.07:31:08.34#ibcon#about to read 5, iclass 13, count 0 2006.224.07:31:08.34#ibcon#read 5, iclass 13, count 0 2006.224.07:31:08.34#ibcon#about to read 6, iclass 13, count 0 2006.224.07:31:08.34#ibcon#read 6, iclass 13, count 0 2006.224.07:31:08.34#ibcon#end of sib2, iclass 13, count 0 2006.224.07:31:08.34#ibcon#*mode == 0, iclass 13, count 0 2006.224.07:31:08.34#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.224.07:31:08.34#ibcon#[25=USB\r\n] 2006.224.07:31:08.34#ibcon#*before write, iclass 13, count 0 2006.224.07:31:08.34#ibcon#enter sib2, iclass 13, count 0 2006.224.07:31:08.34#ibcon#flushed, iclass 13, count 0 2006.224.07:31:08.34#ibcon#about to write, iclass 13, count 0 2006.224.07:31:08.34#ibcon#wrote, iclass 13, count 0 2006.224.07:31:08.34#ibcon#about to read 3, iclass 13, count 0 2006.224.07:31:08.37#ibcon#read 3, iclass 13, count 0 2006.224.07:31:08.37#ibcon#about to read 4, iclass 13, count 0 2006.224.07:31:08.37#ibcon#read 4, iclass 13, count 0 2006.224.07:31:08.37#ibcon#about to read 5, iclass 13, count 0 2006.224.07:31:08.37#ibcon#read 5, iclass 13, count 0 2006.224.07:31:08.37#ibcon#about to read 6, iclass 13, count 0 2006.224.07:31:08.37#ibcon#read 6, iclass 13, count 0 2006.224.07:31:08.37#ibcon#end of sib2, iclass 13, count 0 2006.224.07:31:08.37#ibcon#*after write, iclass 13, count 0 2006.224.07:31:08.37#ibcon#*before return 0, iclass 13, count 0 2006.224.07:31:08.37#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.224.07:31:08.37#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.224.07:31:08.37#ibcon#about to clear, iclass 13 cls_cnt 0 2006.224.07:31:08.37#ibcon#cleared, iclass 13 cls_cnt 0 2006.224.07:31:08.37$vc4f8/valo=2,572.99 2006.224.07:31:08.37#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.224.07:31:08.37#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.224.07:31:08.37#ibcon#ireg 17 cls_cnt 0 2006.224.07:31:08.37#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.224.07:31:08.37#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.224.07:31:08.37#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.224.07:31:08.37#ibcon#enter wrdev, iclass 15, count 0 2006.224.07:31:08.37#ibcon#first serial, iclass 15, count 0 2006.224.07:31:08.37#ibcon#enter sib2, iclass 15, count 0 2006.224.07:31:08.37#ibcon#flushed, iclass 15, count 0 2006.224.07:31:08.37#ibcon#about to write, iclass 15, count 0 2006.224.07:31:08.37#ibcon#wrote, iclass 15, count 0 2006.224.07:31:08.37#ibcon#about to read 3, iclass 15, count 0 2006.224.07:31:08.39#ibcon#read 3, iclass 15, count 0 2006.224.07:31:08.39#ibcon#about to read 4, iclass 15, count 0 2006.224.07:31:08.39#ibcon#read 4, iclass 15, count 0 2006.224.07:31:08.39#ibcon#about to read 5, iclass 15, count 0 2006.224.07:31:08.39#ibcon#read 5, iclass 15, count 0 2006.224.07:31:08.39#ibcon#about to read 6, iclass 15, count 0 2006.224.07:31:08.39#ibcon#read 6, iclass 15, count 0 2006.224.07:31:08.39#ibcon#end of sib2, iclass 15, count 0 2006.224.07:31:08.39#ibcon#*mode == 0, iclass 15, count 0 2006.224.07:31:08.39#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.224.07:31:08.39#ibcon#[26=FRQ=02,572.99\r\n] 2006.224.07:31:08.39#ibcon#*before write, iclass 15, count 0 2006.224.07:31:08.39#ibcon#enter sib2, iclass 15, count 0 2006.224.07:31:08.39#ibcon#flushed, iclass 15, count 0 2006.224.07:31:08.39#ibcon#about to write, iclass 15, count 0 2006.224.07:31:08.39#ibcon#wrote, iclass 15, count 0 2006.224.07:31:08.39#ibcon#about to read 3, iclass 15, count 0 2006.224.07:31:08.44#ibcon#read 3, iclass 15, count 0 2006.224.07:31:08.44#ibcon#about to read 4, iclass 15, count 0 2006.224.07:31:08.44#ibcon#read 4, iclass 15, count 0 2006.224.07:31:08.44#ibcon#about to read 5, iclass 15, count 0 2006.224.07:31:08.44#ibcon#read 5, iclass 15, count 0 2006.224.07:31:08.44#ibcon#about to read 6, iclass 15, count 0 2006.224.07:31:08.44#ibcon#read 6, iclass 15, count 0 2006.224.07:31:08.44#ibcon#end of sib2, iclass 15, count 0 2006.224.07:31:08.44#ibcon#*after write, iclass 15, count 0 2006.224.07:31:08.44#ibcon#*before return 0, iclass 15, count 0 2006.224.07:31:08.44#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.224.07:31:08.44#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.224.07:31:08.44#ibcon#about to clear, iclass 15 cls_cnt 0 2006.224.07:31:08.44#ibcon#cleared, iclass 15 cls_cnt 0 2006.224.07:31:08.44$vc4f8/va=2,7 2006.224.07:31:08.44#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.224.07:31:08.44#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.224.07:31:08.44#ibcon#ireg 11 cls_cnt 2 2006.224.07:31:08.44#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.224.07:31:08.49#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.224.07:31:08.49#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.224.07:31:08.49#ibcon#enter wrdev, iclass 17, count 2 2006.224.07:31:08.49#ibcon#first serial, iclass 17, count 2 2006.224.07:31:08.49#ibcon#enter sib2, iclass 17, count 2 2006.224.07:31:08.49#ibcon#flushed, iclass 17, count 2 2006.224.07:31:08.49#ibcon#about to write, iclass 17, count 2 2006.224.07:31:08.49#ibcon#wrote, iclass 17, count 2 2006.224.07:31:08.49#ibcon#about to read 3, iclass 17, count 2 2006.224.07:31:08.51#ibcon#read 3, iclass 17, count 2 2006.224.07:31:08.51#ibcon#about to read 4, iclass 17, count 2 2006.224.07:31:08.51#ibcon#read 4, iclass 17, count 2 2006.224.07:31:08.51#ibcon#about to read 5, iclass 17, count 2 2006.224.07:31:08.51#ibcon#read 5, iclass 17, count 2 2006.224.07:31:08.51#ibcon#about to read 6, iclass 17, count 2 2006.224.07:31:08.51#ibcon#read 6, iclass 17, count 2 2006.224.07:31:08.51#ibcon#end of sib2, iclass 17, count 2 2006.224.07:31:08.51#ibcon#*mode == 0, iclass 17, count 2 2006.224.07:31:08.51#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.224.07:31:08.51#ibcon#[25=AT02-07\r\n] 2006.224.07:31:08.51#ibcon#*before write, iclass 17, count 2 2006.224.07:31:08.51#ibcon#enter sib2, iclass 17, count 2 2006.224.07:31:08.51#ibcon#flushed, iclass 17, count 2 2006.224.07:31:08.51#ibcon#about to write, iclass 17, count 2 2006.224.07:31:08.51#ibcon#wrote, iclass 17, count 2 2006.224.07:31:08.51#ibcon#about to read 3, iclass 17, count 2 2006.224.07:31:08.54#ibcon#read 3, iclass 17, count 2 2006.224.07:31:08.54#ibcon#about to read 4, iclass 17, count 2 2006.224.07:31:08.54#ibcon#read 4, iclass 17, count 2 2006.224.07:31:08.54#ibcon#about to read 5, iclass 17, count 2 2006.224.07:31:08.54#ibcon#read 5, iclass 17, count 2 2006.224.07:31:08.54#ibcon#about to read 6, iclass 17, count 2 2006.224.07:31:08.54#ibcon#read 6, iclass 17, count 2 2006.224.07:31:08.54#ibcon#end of sib2, iclass 17, count 2 2006.224.07:31:08.54#ibcon#*after write, iclass 17, count 2 2006.224.07:31:08.54#ibcon#*before return 0, iclass 17, count 2 2006.224.07:31:08.54#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.224.07:31:08.54#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.224.07:31:08.54#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.224.07:31:08.54#ibcon#ireg 7 cls_cnt 0 2006.224.07:31:08.54#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.224.07:31:08.66#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.224.07:31:08.66#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.224.07:31:08.66#ibcon#enter wrdev, iclass 17, count 0 2006.224.07:31:08.66#ibcon#first serial, iclass 17, count 0 2006.224.07:31:08.66#ibcon#enter sib2, iclass 17, count 0 2006.224.07:31:08.66#ibcon#flushed, iclass 17, count 0 2006.224.07:31:08.66#ibcon#about to write, iclass 17, count 0 2006.224.07:31:08.66#ibcon#wrote, iclass 17, count 0 2006.224.07:31:08.66#ibcon#about to read 3, iclass 17, count 0 2006.224.07:31:08.68#ibcon#read 3, iclass 17, count 0 2006.224.07:31:08.68#ibcon#about to read 4, iclass 17, count 0 2006.224.07:31:08.68#ibcon#read 4, iclass 17, count 0 2006.224.07:31:08.68#ibcon#about to read 5, iclass 17, count 0 2006.224.07:31:08.68#ibcon#read 5, iclass 17, count 0 2006.224.07:31:08.68#ibcon#about to read 6, iclass 17, count 0 2006.224.07:31:08.68#ibcon#read 6, iclass 17, count 0 2006.224.07:31:08.68#ibcon#end of sib2, iclass 17, count 0 2006.224.07:31:08.68#ibcon#*mode == 0, iclass 17, count 0 2006.224.07:31:08.68#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.224.07:31:08.68#ibcon#[25=USB\r\n] 2006.224.07:31:08.68#ibcon#*before write, iclass 17, count 0 2006.224.07:31:08.68#ibcon#enter sib2, iclass 17, count 0 2006.224.07:31:08.68#ibcon#flushed, iclass 17, count 0 2006.224.07:31:08.68#ibcon#about to write, iclass 17, count 0 2006.224.07:31:08.68#ibcon#wrote, iclass 17, count 0 2006.224.07:31:08.68#ibcon#about to read 3, iclass 17, count 0 2006.224.07:31:08.71#ibcon#read 3, iclass 17, count 0 2006.224.07:31:08.71#ibcon#about to read 4, iclass 17, count 0 2006.224.07:31:08.71#ibcon#read 4, iclass 17, count 0 2006.224.07:31:08.71#ibcon#about to read 5, iclass 17, count 0 2006.224.07:31:08.71#ibcon#read 5, iclass 17, count 0 2006.224.07:31:08.71#ibcon#about to read 6, iclass 17, count 0 2006.224.07:31:08.71#ibcon#read 6, iclass 17, count 0 2006.224.07:31:08.71#ibcon#end of sib2, iclass 17, count 0 2006.224.07:31:08.71#ibcon#*after write, iclass 17, count 0 2006.224.07:31:08.71#ibcon#*before return 0, iclass 17, count 0 2006.224.07:31:08.71#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.224.07:31:08.71#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.224.07:31:08.71#ibcon#about to clear, iclass 17 cls_cnt 0 2006.224.07:31:08.71#ibcon#cleared, iclass 17 cls_cnt 0 2006.224.07:31:08.71$vc4f8/valo=3,672.99 2006.224.07:31:08.71#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.224.07:31:08.71#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.224.07:31:08.71#ibcon#ireg 17 cls_cnt 0 2006.224.07:31:08.71#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.224.07:31:08.71#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.224.07:31:08.71#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.224.07:31:08.71#ibcon#enter wrdev, iclass 19, count 0 2006.224.07:31:08.71#ibcon#first serial, iclass 19, count 0 2006.224.07:31:08.71#ibcon#enter sib2, iclass 19, count 0 2006.224.07:31:08.71#ibcon#flushed, iclass 19, count 0 2006.224.07:31:08.71#ibcon#about to write, iclass 19, count 0 2006.224.07:31:08.71#ibcon#wrote, iclass 19, count 0 2006.224.07:31:08.71#ibcon#about to read 3, iclass 19, count 0 2006.224.07:31:08.73#ibcon#read 3, iclass 19, count 0 2006.224.07:31:08.73#ibcon#about to read 4, iclass 19, count 0 2006.224.07:31:08.73#ibcon#read 4, iclass 19, count 0 2006.224.07:31:08.73#ibcon#about to read 5, iclass 19, count 0 2006.224.07:31:08.73#ibcon#read 5, iclass 19, count 0 2006.224.07:31:08.73#ibcon#about to read 6, iclass 19, count 0 2006.224.07:31:08.73#ibcon#read 6, iclass 19, count 0 2006.224.07:31:08.73#ibcon#end of sib2, iclass 19, count 0 2006.224.07:31:08.73#ibcon#*mode == 0, iclass 19, count 0 2006.224.07:31:08.73#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.224.07:31:08.73#ibcon#[26=FRQ=03,672.99\r\n] 2006.224.07:31:08.73#ibcon#*before write, iclass 19, count 0 2006.224.07:31:08.73#ibcon#enter sib2, iclass 19, count 0 2006.224.07:31:08.73#ibcon#flushed, iclass 19, count 0 2006.224.07:31:08.73#ibcon#about to write, iclass 19, count 0 2006.224.07:31:08.73#ibcon#wrote, iclass 19, count 0 2006.224.07:31:08.73#ibcon#about to read 3, iclass 19, count 0 2006.224.07:31:08.78#ibcon#read 3, iclass 19, count 0 2006.224.07:31:08.78#ibcon#about to read 4, iclass 19, count 0 2006.224.07:31:08.78#ibcon#read 4, iclass 19, count 0 2006.224.07:31:08.78#ibcon#about to read 5, iclass 19, count 0 2006.224.07:31:08.78#ibcon#read 5, iclass 19, count 0 2006.224.07:31:08.78#ibcon#about to read 6, iclass 19, count 0 2006.224.07:31:08.78#ibcon#read 6, iclass 19, count 0 2006.224.07:31:08.78#ibcon#end of sib2, iclass 19, count 0 2006.224.07:31:08.78#ibcon#*after write, iclass 19, count 0 2006.224.07:31:08.78#ibcon#*before return 0, iclass 19, count 0 2006.224.07:31:08.78#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.224.07:31:08.78#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.224.07:31:08.78#ibcon#about to clear, iclass 19 cls_cnt 0 2006.224.07:31:08.78#ibcon#cleared, iclass 19 cls_cnt 0 2006.224.07:31:08.78$vc4f8/va=3,6 2006.224.07:31:08.78#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.224.07:31:08.78#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.224.07:31:08.78#ibcon#ireg 11 cls_cnt 2 2006.224.07:31:08.78#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.224.07:31:08.83#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.224.07:31:08.83#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.224.07:31:08.83#ibcon#enter wrdev, iclass 21, count 2 2006.224.07:31:08.83#ibcon#first serial, iclass 21, count 2 2006.224.07:31:08.83#ibcon#enter sib2, iclass 21, count 2 2006.224.07:31:08.83#ibcon#flushed, iclass 21, count 2 2006.224.07:31:08.83#ibcon#about to write, iclass 21, count 2 2006.224.07:31:08.83#ibcon#wrote, iclass 21, count 2 2006.224.07:31:08.83#ibcon#about to read 3, iclass 21, count 2 2006.224.07:31:08.85#ibcon#read 3, iclass 21, count 2 2006.224.07:31:08.85#ibcon#about to read 4, iclass 21, count 2 2006.224.07:31:08.85#ibcon#read 4, iclass 21, count 2 2006.224.07:31:08.85#ibcon#about to read 5, iclass 21, count 2 2006.224.07:31:08.85#ibcon#read 5, iclass 21, count 2 2006.224.07:31:08.85#ibcon#about to read 6, iclass 21, count 2 2006.224.07:31:08.85#ibcon#read 6, iclass 21, count 2 2006.224.07:31:08.85#ibcon#end of sib2, iclass 21, count 2 2006.224.07:31:08.85#ibcon#*mode == 0, iclass 21, count 2 2006.224.07:31:08.85#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.224.07:31:08.85#ibcon#[25=AT03-06\r\n] 2006.224.07:31:08.85#ibcon#*before write, iclass 21, count 2 2006.224.07:31:08.85#ibcon#enter sib2, iclass 21, count 2 2006.224.07:31:08.85#ibcon#flushed, iclass 21, count 2 2006.224.07:31:08.85#ibcon#about to write, iclass 21, count 2 2006.224.07:31:08.85#ibcon#wrote, iclass 21, count 2 2006.224.07:31:08.85#ibcon#about to read 3, iclass 21, count 2 2006.224.07:31:08.88#ibcon#read 3, iclass 21, count 2 2006.224.07:31:08.88#ibcon#about to read 4, iclass 21, count 2 2006.224.07:31:08.88#ibcon#read 4, iclass 21, count 2 2006.224.07:31:08.88#ibcon#about to read 5, iclass 21, count 2 2006.224.07:31:08.88#ibcon#read 5, iclass 21, count 2 2006.224.07:31:08.88#ibcon#about to read 6, iclass 21, count 2 2006.224.07:31:08.88#ibcon#read 6, iclass 21, count 2 2006.224.07:31:08.88#ibcon#end of sib2, iclass 21, count 2 2006.224.07:31:08.88#ibcon#*after write, iclass 21, count 2 2006.224.07:31:08.88#ibcon#*before return 0, iclass 21, count 2 2006.224.07:31:08.88#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.224.07:31:08.88#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.224.07:31:08.88#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.224.07:31:08.88#ibcon#ireg 7 cls_cnt 0 2006.224.07:31:08.88#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.224.07:31:09.00#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.224.07:31:09.00#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.224.07:31:09.00#ibcon#enter wrdev, iclass 21, count 0 2006.224.07:31:09.00#ibcon#first serial, iclass 21, count 0 2006.224.07:31:09.00#ibcon#enter sib2, iclass 21, count 0 2006.224.07:31:09.00#ibcon#flushed, iclass 21, count 0 2006.224.07:31:09.00#ibcon#about to write, iclass 21, count 0 2006.224.07:31:09.00#ibcon#wrote, iclass 21, count 0 2006.224.07:31:09.00#ibcon#about to read 3, iclass 21, count 0 2006.224.07:31:09.02#ibcon#read 3, iclass 21, count 0 2006.224.07:31:09.02#ibcon#about to read 4, iclass 21, count 0 2006.224.07:31:09.02#ibcon#read 4, iclass 21, count 0 2006.224.07:31:09.02#ibcon#about to read 5, iclass 21, count 0 2006.224.07:31:09.02#ibcon#read 5, iclass 21, count 0 2006.224.07:31:09.02#ibcon#about to read 6, iclass 21, count 0 2006.224.07:31:09.02#ibcon#read 6, iclass 21, count 0 2006.224.07:31:09.02#ibcon#end of sib2, iclass 21, count 0 2006.224.07:31:09.02#ibcon#*mode == 0, iclass 21, count 0 2006.224.07:31:09.02#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.224.07:31:09.02#ibcon#[25=USB\r\n] 2006.224.07:31:09.02#ibcon#*before write, iclass 21, count 0 2006.224.07:31:09.02#ibcon#enter sib2, iclass 21, count 0 2006.224.07:31:09.02#ibcon#flushed, iclass 21, count 0 2006.224.07:31:09.02#ibcon#about to write, iclass 21, count 0 2006.224.07:31:09.02#ibcon#wrote, iclass 21, count 0 2006.224.07:31:09.02#ibcon#about to read 3, iclass 21, count 0 2006.224.07:31:09.05#ibcon#read 3, iclass 21, count 0 2006.224.07:31:09.05#ibcon#about to read 4, iclass 21, count 0 2006.224.07:31:09.05#ibcon#read 4, iclass 21, count 0 2006.224.07:31:09.05#ibcon#about to read 5, iclass 21, count 0 2006.224.07:31:09.05#ibcon#read 5, iclass 21, count 0 2006.224.07:31:09.05#ibcon#about to read 6, iclass 21, count 0 2006.224.07:31:09.05#ibcon#read 6, iclass 21, count 0 2006.224.07:31:09.05#ibcon#end of sib2, iclass 21, count 0 2006.224.07:31:09.05#ibcon#*after write, iclass 21, count 0 2006.224.07:31:09.05#ibcon#*before return 0, iclass 21, count 0 2006.224.07:31:09.05#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.224.07:31:09.05#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.224.07:31:09.05#ibcon#about to clear, iclass 21 cls_cnt 0 2006.224.07:31:09.05#ibcon#cleared, iclass 21 cls_cnt 0 2006.224.07:31:09.05$vc4f8/valo=4,832.99 2006.224.07:31:09.05#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.224.07:31:09.05#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.224.07:31:09.05#ibcon#ireg 17 cls_cnt 0 2006.224.07:31:09.05#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.224.07:31:09.05#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.224.07:31:09.05#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.224.07:31:09.05#ibcon#enter wrdev, iclass 23, count 0 2006.224.07:31:09.05#ibcon#first serial, iclass 23, count 0 2006.224.07:31:09.05#ibcon#enter sib2, iclass 23, count 0 2006.224.07:31:09.05#ibcon#flushed, iclass 23, count 0 2006.224.07:31:09.05#ibcon#about to write, iclass 23, count 0 2006.224.07:31:09.05#ibcon#wrote, iclass 23, count 0 2006.224.07:31:09.05#ibcon#about to read 3, iclass 23, count 0 2006.224.07:31:09.07#ibcon#read 3, iclass 23, count 0 2006.224.07:31:09.07#ibcon#about to read 4, iclass 23, count 0 2006.224.07:31:09.07#ibcon#read 4, iclass 23, count 0 2006.224.07:31:09.07#ibcon#about to read 5, iclass 23, count 0 2006.224.07:31:09.07#ibcon#read 5, iclass 23, count 0 2006.224.07:31:09.07#ibcon#about to read 6, iclass 23, count 0 2006.224.07:31:09.07#ibcon#read 6, iclass 23, count 0 2006.224.07:31:09.07#ibcon#end of sib2, iclass 23, count 0 2006.224.07:31:09.07#ibcon#*mode == 0, iclass 23, count 0 2006.224.07:31:09.07#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.224.07:31:09.07#ibcon#[26=FRQ=04,832.99\r\n] 2006.224.07:31:09.07#ibcon#*before write, iclass 23, count 0 2006.224.07:31:09.07#ibcon#enter sib2, iclass 23, count 0 2006.224.07:31:09.07#ibcon#flushed, iclass 23, count 0 2006.224.07:31:09.07#ibcon#about to write, iclass 23, count 0 2006.224.07:31:09.07#ibcon#wrote, iclass 23, count 0 2006.224.07:31:09.07#ibcon#about to read 3, iclass 23, count 0 2006.224.07:31:09.12#ibcon#read 3, iclass 23, count 0 2006.224.07:31:09.12#ibcon#about to read 4, iclass 23, count 0 2006.224.07:31:09.12#ibcon#read 4, iclass 23, count 0 2006.224.07:31:09.12#ibcon#about to read 5, iclass 23, count 0 2006.224.07:31:09.12#ibcon#read 5, iclass 23, count 0 2006.224.07:31:09.12#ibcon#about to read 6, iclass 23, count 0 2006.224.07:31:09.12#ibcon#read 6, iclass 23, count 0 2006.224.07:31:09.12#ibcon#end of sib2, iclass 23, count 0 2006.224.07:31:09.12#ibcon#*after write, iclass 23, count 0 2006.224.07:31:09.12#ibcon#*before return 0, iclass 23, count 0 2006.224.07:31:09.12#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.224.07:31:09.12#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.224.07:31:09.12#ibcon#about to clear, iclass 23 cls_cnt 0 2006.224.07:31:09.12#ibcon#cleared, iclass 23 cls_cnt 0 2006.224.07:31:09.12$vc4f8/va=4,7 2006.224.07:31:09.12#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.224.07:31:09.12#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.224.07:31:09.12#ibcon#ireg 11 cls_cnt 2 2006.224.07:31:09.12#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.224.07:31:09.17#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.224.07:31:09.17#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.224.07:31:09.17#ibcon#enter wrdev, iclass 25, count 2 2006.224.07:31:09.17#ibcon#first serial, iclass 25, count 2 2006.224.07:31:09.17#ibcon#enter sib2, iclass 25, count 2 2006.224.07:31:09.17#ibcon#flushed, iclass 25, count 2 2006.224.07:31:09.17#ibcon#about to write, iclass 25, count 2 2006.224.07:31:09.17#ibcon#wrote, iclass 25, count 2 2006.224.07:31:09.17#ibcon#about to read 3, iclass 25, count 2 2006.224.07:31:09.19#ibcon#read 3, iclass 25, count 2 2006.224.07:31:09.19#ibcon#about to read 4, iclass 25, count 2 2006.224.07:31:09.19#ibcon#read 4, iclass 25, count 2 2006.224.07:31:09.19#ibcon#about to read 5, iclass 25, count 2 2006.224.07:31:09.19#ibcon#read 5, iclass 25, count 2 2006.224.07:31:09.19#ibcon#about to read 6, iclass 25, count 2 2006.224.07:31:09.19#ibcon#read 6, iclass 25, count 2 2006.224.07:31:09.19#ibcon#end of sib2, iclass 25, count 2 2006.224.07:31:09.19#ibcon#*mode == 0, iclass 25, count 2 2006.224.07:31:09.19#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.224.07:31:09.19#ibcon#[25=AT04-07\r\n] 2006.224.07:31:09.19#ibcon#*before write, iclass 25, count 2 2006.224.07:31:09.19#ibcon#enter sib2, iclass 25, count 2 2006.224.07:31:09.19#ibcon#flushed, iclass 25, count 2 2006.224.07:31:09.19#ibcon#about to write, iclass 25, count 2 2006.224.07:31:09.19#ibcon#wrote, iclass 25, count 2 2006.224.07:31:09.19#ibcon#about to read 3, iclass 25, count 2 2006.224.07:31:09.22#ibcon#read 3, iclass 25, count 2 2006.224.07:31:09.22#ibcon#about to read 4, iclass 25, count 2 2006.224.07:31:09.22#ibcon#read 4, iclass 25, count 2 2006.224.07:31:09.22#ibcon#about to read 5, iclass 25, count 2 2006.224.07:31:09.22#ibcon#read 5, iclass 25, count 2 2006.224.07:31:09.22#ibcon#about to read 6, iclass 25, count 2 2006.224.07:31:09.22#ibcon#read 6, iclass 25, count 2 2006.224.07:31:09.22#ibcon#end of sib2, iclass 25, count 2 2006.224.07:31:09.22#ibcon#*after write, iclass 25, count 2 2006.224.07:31:09.22#ibcon#*before return 0, iclass 25, count 2 2006.224.07:31:09.22#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.224.07:31:09.22#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.224.07:31:09.22#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.224.07:31:09.22#ibcon#ireg 7 cls_cnt 0 2006.224.07:31:09.22#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.224.07:31:09.34#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.224.07:31:09.34#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.224.07:31:09.34#ibcon#enter wrdev, iclass 25, count 0 2006.224.07:31:09.34#ibcon#first serial, iclass 25, count 0 2006.224.07:31:09.34#ibcon#enter sib2, iclass 25, count 0 2006.224.07:31:09.34#ibcon#flushed, iclass 25, count 0 2006.224.07:31:09.34#ibcon#about to write, iclass 25, count 0 2006.224.07:31:09.34#ibcon#wrote, iclass 25, count 0 2006.224.07:31:09.34#ibcon#about to read 3, iclass 25, count 0 2006.224.07:31:09.36#ibcon#read 3, iclass 25, count 0 2006.224.07:31:09.36#ibcon#about to read 4, iclass 25, count 0 2006.224.07:31:09.36#ibcon#read 4, iclass 25, count 0 2006.224.07:31:09.36#ibcon#about to read 5, iclass 25, count 0 2006.224.07:31:09.36#ibcon#read 5, iclass 25, count 0 2006.224.07:31:09.36#ibcon#about to read 6, iclass 25, count 0 2006.224.07:31:09.36#ibcon#read 6, iclass 25, count 0 2006.224.07:31:09.36#ibcon#end of sib2, iclass 25, count 0 2006.224.07:31:09.36#ibcon#*mode == 0, iclass 25, count 0 2006.224.07:31:09.36#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.224.07:31:09.36#ibcon#[25=USB\r\n] 2006.224.07:31:09.36#ibcon#*before write, iclass 25, count 0 2006.224.07:31:09.36#ibcon#enter sib2, iclass 25, count 0 2006.224.07:31:09.36#ibcon#flushed, iclass 25, count 0 2006.224.07:31:09.36#ibcon#about to write, iclass 25, count 0 2006.224.07:31:09.36#ibcon#wrote, iclass 25, count 0 2006.224.07:31:09.36#ibcon#about to read 3, iclass 25, count 0 2006.224.07:31:09.39#ibcon#read 3, iclass 25, count 0 2006.224.07:31:09.39#ibcon#about to read 4, iclass 25, count 0 2006.224.07:31:09.39#ibcon#read 4, iclass 25, count 0 2006.224.07:31:09.39#ibcon#about to read 5, iclass 25, count 0 2006.224.07:31:09.39#ibcon#read 5, iclass 25, count 0 2006.224.07:31:09.39#ibcon#about to read 6, iclass 25, count 0 2006.224.07:31:09.39#ibcon#read 6, iclass 25, count 0 2006.224.07:31:09.39#ibcon#end of sib2, iclass 25, count 0 2006.224.07:31:09.39#ibcon#*after write, iclass 25, count 0 2006.224.07:31:09.39#ibcon#*before return 0, iclass 25, count 0 2006.224.07:31:09.39#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.224.07:31:09.39#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.224.07:31:09.39#ibcon#about to clear, iclass 25 cls_cnt 0 2006.224.07:31:09.39#ibcon#cleared, iclass 25 cls_cnt 0 2006.224.07:31:09.39$vc4f8/valo=5,652.99 2006.224.07:31:09.39#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.224.07:31:09.39#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.224.07:31:09.39#ibcon#ireg 17 cls_cnt 0 2006.224.07:31:09.39#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.224.07:31:09.39#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.224.07:31:09.39#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.224.07:31:09.39#ibcon#enter wrdev, iclass 27, count 0 2006.224.07:31:09.39#ibcon#first serial, iclass 27, count 0 2006.224.07:31:09.39#ibcon#enter sib2, iclass 27, count 0 2006.224.07:31:09.39#ibcon#flushed, iclass 27, count 0 2006.224.07:31:09.39#ibcon#about to write, iclass 27, count 0 2006.224.07:31:09.39#ibcon#wrote, iclass 27, count 0 2006.224.07:31:09.39#ibcon#about to read 3, iclass 27, count 0 2006.224.07:31:09.41#ibcon#read 3, iclass 27, count 0 2006.224.07:31:09.41#ibcon#about to read 4, iclass 27, count 0 2006.224.07:31:09.41#ibcon#read 4, iclass 27, count 0 2006.224.07:31:09.41#ibcon#about to read 5, iclass 27, count 0 2006.224.07:31:09.41#ibcon#read 5, iclass 27, count 0 2006.224.07:31:09.41#ibcon#about to read 6, iclass 27, count 0 2006.224.07:31:09.41#ibcon#read 6, iclass 27, count 0 2006.224.07:31:09.41#ibcon#end of sib2, iclass 27, count 0 2006.224.07:31:09.41#ibcon#*mode == 0, iclass 27, count 0 2006.224.07:31:09.41#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.224.07:31:09.41#ibcon#[26=FRQ=05,652.99\r\n] 2006.224.07:31:09.41#ibcon#*before write, iclass 27, count 0 2006.224.07:31:09.41#ibcon#enter sib2, iclass 27, count 0 2006.224.07:31:09.41#ibcon#flushed, iclass 27, count 0 2006.224.07:31:09.41#ibcon#about to write, iclass 27, count 0 2006.224.07:31:09.41#ibcon#wrote, iclass 27, count 0 2006.224.07:31:09.41#ibcon#about to read 3, iclass 27, count 0 2006.224.07:31:09.45#ibcon#read 3, iclass 27, count 0 2006.224.07:31:09.45#ibcon#about to read 4, iclass 27, count 0 2006.224.07:31:09.45#ibcon#read 4, iclass 27, count 0 2006.224.07:31:09.45#ibcon#about to read 5, iclass 27, count 0 2006.224.07:31:09.45#ibcon#read 5, iclass 27, count 0 2006.224.07:31:09.45#ibcon#about to read 6, iclass 27, count 0 2006.224.07:31:09.45#ibcon#read 6, iclass 27, count 0 2006.224.07:31:09.45#ibcon#end of sib2, iclass 27, count 0 2006.224.07:31:09.45#ibcon#*after write, iclass 27, count 0 2006.224.07:31:09.45#ibcon#*before return 0, iclass 27, count 0 2006.224.07:31:09.45#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.224.07:31:09.45#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.224.07:31:09.45#ibcon#about to clear, iclass 27 cls_cnt 0 2006.224.07:31:09.45#ibcon#cleared, iclass 27 cls_cnt 0 2006.224.07:31:09.45$vc4f8/va=5,7 2006.224.07:31:09.45#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.224.07:31:09.45#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.224.07:31:09.45#ibcon#ireg 11 cls_cnt 2 2006.224.07:31:09.45#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.224.07:31:09.51#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.224.07:31:09.51#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.224.07:31:09.51#ibcon#enter wrdev, iclass 29, count 2 2006.224.07:31:09.51#ibcon#first serial, iclass 29, count 2 2006.224.07:31:09.51#ibcon#enter sib2, iclass 29, count 2 2006.224.07:31:09.51#ibcon#flushed, iclass 29, count 2 2006.224.07:31:09.51#ibcon#about to write, iclass 29, count 2 2006.224.07:31:09.51#ibcon#wrote, iclass 29, count 2 2006.224.07:31:09.51#ibcon#about to read 3, iclass 29, count 2 2006.224.07:31:09.53#ibcon#read 3, iclass 29, count 2 2006.224.07:31:09.53#ibcon#about to read 4, iclass 29, count 2 2006.224.07:31:09.53#ibcon#read 4, iclass 29, count 2 2006.224.07:31:09.53#ibcon#about to read 5, iclass 29, count 2 2006.224.07:31:09.53#ibcon#read 5, iclass 29, count 2 2006.224.07:31:09.53#ibcon#about to read 6, iclass 29, count 2 2006.224.07:31:09.53#ibcon#read 6, iclass 29, count 2 2006.224.07:31:09.53#ibcon#end of sib2, iclass 29, count 2 2006.224.07:31:09.53#ibcon#*mode == 0, iclass 29, count 2 2006.224.07:31:09.53#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.224.07:31:09.53#ibcon#[25=AT05-07\r\n] 2006.224.07:31:09.53#ibcon#*before write, iclass 29, count 2 2006.224.07:31:09.53#ibcon#enter sib2, iclass 29, count 2 2006.224.07:31:09.53#ibcon#flushed, iclass 29, count 2 2006.224.07:31:09.53#ibcon#about to write, iclass 29, count 2 2006.224.07:31:09.53#ibcon#wrote, iclass 29, count 2 2006.224.07:31:09.53#ibcon#about to read 3, iclass 29, count 2 2006.224.07:31:09.56#ibcon#read 3, iclass 29, count 2 2006.224.07:31:09.56#ibcon#about to read 4, iclass 29, count 2 2006.224.07:31:09.56#ibcon#read 4, iclass 29, count 2 2006.224.07:31:09.56#ibcon#about to read 5, iclass 29, count 2 2006.224.07:31:09.56#ibcon#read 5, iclass 29, count 2 2006.224.07:31:09.56#ibcon#about to read 6, iclass 29, count 2 2006.224.07:31:09.56#ibcon#read 6, iclass 29, count 2 2006.224.07:31:09.56#ibcon#end of sib2, iclass 29, count 2 2006.224.07:31:09.56#ibcon#*after write, iclass 29, count 2 2006.224.07:31:09.56#ibcon#*before return 0, iclass 29, count 2 2006.224.07:31:09.56#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.224.07:31:09.56#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.224.07:31:09.56#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.224.07:31:09.56#ibcon#ireg 7 cls_cnt 0 2006.224.07:31:09.56#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.224.07:31:09.68#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.224.07:31:09.68#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.224.07:31:09.68#ibcon#enter wrdev, iclass 29, count 0 2006.224.07:31:09.68#ibcon#first serial, iclass 29, count 0 2006.224.07:31:09.68#ibcon#enter sib2, iclass 29, count 0 2006.224.07:31:09.68#ibcon#flushed, iclass 29, count 0 2006.224.07:31:09.68#ibcon#about to write, iclass 29, count 0 2006.224.07:31:09.68#ibcon#wrote, iclass 29, count 0 2006.224.07:31:09.68#ibcon#about to read 3, iclass 29, count 0 2006.224.07:31:09.70#ibcon#read 3, iclass 29, count 0 2006.224.07:31:09.70#ibcon#about to read 4, iclass 29, count 0 2006.224.07:31:09.70#ibcon#read 4, iclass 29, count 0 2006.224.07:31:09.70#ibcon#about to read 5, iclass 29, count 0 2006.224.07:31:09.70#ibcon#read 5, iclass 29, count 0 2006.224.07:31:09.70#ibcon#about to read 6, iclass 29, count 0 2006.224.07:31:09.70#ibcon#read 6, iclass 29, count 0 2006.224.07:31:09.70#ibcon#end of sib2, iclass 29, count 0 2006.224.07:31:09.70#ibcon#*mode == 0, iclass 29, count 0 2006.224.07:31:09.70#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.224.07:31:09.70#ibcon#[25=USB\r\n] 2006.224.07:31:09.70#ibcon#*before write, iclass 29, count 0 2006.224.07:31:09.70#ibcon#enter sib2, iclass 29, count 0 2006.224.07:31:09.70#ibcon#flushed, iclass 29, count 0 2006.224.07:31:09.70#ibcon#about to write, iclass 29, count 0 2006.224.07:31:09.70#ibcon#wrote, iclass 29, count 0 2006.224.07:31:09.70#ibcon#about to read 3, iclass 29, count 0 2006.224.07:31:09.73#ibcon#read 3, iclass 29, count 0 2006.224.07:31:09.73#ibcon#about to read 4, iclass 29, count 0 2006.224.07:31:09.73#ibcon#read 4, iclass 29, count 0 2006.224.07:31:09.73#ibcon#about to read 5, iclass 29, count 0 2006.224.07:31:09.73#ibcon#read 5, iclass 29, count 0 2006.224.07:31:09.73#ibcon#about to read 6, iclass 29, count 0 2006.224.07:31:09.73#ibcon#read 6, iclass 29, count 0 2006.224.07:31:09.73#ibcon#end of sib2, iclass 29, count 0 2006.224.07:31:09.73#ibcon#*after write, iclass 29, count 0 2006.224.07:31:09.73#ibcon#*before return 0, iclass 29, count 0 2006.224.07:31:09.73#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.224.07:31:09.73#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.224.07:31:09.73#ibcon#about to clear, iclass 29 cls_cnt 0 2006.224.07:31:09.73#ibcon#cleared, iclass 29 cls_cnt 0 2006.224.07:31:09.73$vc4f8/valo=6,772.99 2006.224.07:31:09.73#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.224.07:31:09.73#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.224.07:31:09.73#ibcon#ireg 17 cls_cnt 0 2006.224.07:31:09.73#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.224.07:31:09.73#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.224.07:31:09.73#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.224.07:31:09.73#ibcon#enter wrdev, iclass 31, count 0 2006.224.07:31:09.73#ibcon#first serial, iclass 31, count 0 2006.224.07:31:09.73#ibcon#enter sib2, iclass 31, count 0 2006.224.07:31:09.73#ibcon#flushed, iclass 31, count 0 2006.224.07:31:09.73#ibcon#about to write, iclass 31, count 0 2006.224.07:31:09.73#ibcon#wrote, iclass 31, count 0 2006.224.07:31:09.73#ibcon#about to read 3, iclass 31, count 0 2006.224.07:31:09.75#ibcon#read 3, iclass 31, count 0 2006.224.07:31:09.75#ibcon#about to read 4, iclass 31, count 0 2006.224.07:31:09.75#ibcon#read 4, iclass 31, count 0 2006.224.07:31:09.75#ibcon#about to read 5, iclass 31, count 0 2006.224.07:31:09.75#ibcon#read 5, iclass 31, count 0 2006.224.07:31:09.75#ibcon#about to read 6, iclass 31, count 0 2006.224.07:31:09.75#ibcon#read 6, iclass 31, count 0 2006.224.07:31:09.75#ibcon#end of sib2, iclass 31, count 0 2006.224.07:31:09.75#ibcon#*mode == 0, iclass 31, count 0 2006.224.07:31:09.75#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.224.07:31:09.75#ibcon#[26=FRQ=06,772.99\r\n] 2006.224.07:31:09.75#ibcon#*before write, iclass 31, count 0 2006.224.07:31:09.75#ibcon#enter sib2, iclass 31, count 0 2006.224.07:31:09.75#ibcon#flushed, iclass 31, count 0 2006.224.07:31:09.75#ibcon#about to write, iclass 31, count 0 2006.224.07:31:09.75#ibcon#wrote, iclass 31, count 0 2006.224.07:31:09.75#ibcon#about to read 3, iclass 31, count 0 2006.224.07:31:09.80#ibcon#read 3, iclass 31, count 0 2006.224.07:31:09.80#ibcon#about to read 4, iclass 31, count 0 2006.224.07:31:09.80#ibcon#read 4, iclass 31, count 0 2006.224.07:31:09.80#ibcon#about to read 5, iclass 31, count 0 2006.224.07:31:09.80#ibcon#read 5, iclass 31, count 0 2006.224.07:31:09.80#ibcon#about to read 6, iclass 31, count 0 2006.224.07:31:09.80#ibcon#read 6, iclass 31, count 0 2006.224.07:31:09.80#ibcon#end of sib2, iclass 31, count 0 2006.224.07:31:09.80#ibcon#*after write, iclass 31, count 0 2006.224.07:31:09.80#ibcon#*before return 0, iclass 31, count 0 2006.224.07:31:09.80#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.224.07:31:09.80#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.224.07:31:09.80#ibcon#about to clear, iclass 31 cls_cnt 0 2006.224.07:31:09.80#ibcon#cleared, iclass 31 cls_cnt 0 2006.224.07:31:09.80$vc4f8/va=6,6 2006.224.07:31:09.80#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.224.07:31:09.80#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.224.07:31:09.80#ibcon#ireg 11 cls_cnt 2 2006.224.07:31:09.80#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.224.07:31:09.85#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.224.07:31:09.85#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.224.07:31:09.85#ibcon#enter wrdev, iclass 33, count 2 2006.224.07:31:09.85#ibcon#first serial, iclass 33, count 2 2006.224.07:31:09.85#ibcon#enter sib2, iclass 33, count 2 2006.224.07:31:09.85#ibcon#flushed, iclass 33, count 2 2006.224.07:31:09.85#ibcon#about to write, iclass 33, count 2 2006.224.07:31:09.85#ibcon#wrote, iclass 33, count 2 2006.224.07:31:09.85#ibcon#about to read 3, iclass 33, count 2 2006.224.07:31:09.87#ibcon#read 3, iclass 33, count 2 2006.224.07:31:09.87#ibcon#about to read 4, iclass 33, count 2 2006.224.07:31:09.87#ibcon#read 4, iclass 33, count 2 2006.224.07:31:09.87#ibcon#about to read 5, iclass 33, count 2 2006.224.07:31:09.87#ibcon#read 5, iclass 33, count 2 2006.224.07:31:09.87#ibcon#about to read 6, iclass 33, count 2 2006.224.07:31:09.87#ibcon#read 6, iclass 33, count 2 2006.224.07:31:09.87#ibcon#end of sib2, iclass 33, count 2 2006.224.07:31:09.87#ibcon#*mode == 0, iclass 33, count 2 2006.224.07:31:09.87#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.224.07:31:09.87#ibcon#[25=AT06-06\r\n] 2006.224.07:31:09.87#ibcon#*before write, iclass 33, count 2 2006.224.07:31:09.87#ibcon#enter sib2, iclass 33, count 2 2006.224.07:31:09.87#ibcon#flushed, iclass 33, count 2 2006.224.07:31:09.87#ibcon#about to write, iclass 33, count 2 2006.224.07:31:09.87#ibcon#wrote, iclass 33, count 2 2006.224.07:31:09.87#ibcon#about to read 3, iclass 33, count 2 2006.224.07:31:09.90#ibcon#read 3, iclass 33, count 2 2006.224.07:31:09.90#ibcon#about to read 4, iclass 33, count 2 2006.224.07:31:09.90#ibcon#read 4, iclass 33, count 2 2006.224.07:31:09.90#ibcon#about to read 5, iclass 33, count 2 2006.224.07:31:09.90#ibcon#read 5, iclass 33, count 2 2006.224.07:31:09.90#ibcon#about to read 6, iclass 33, count 2 2006.224.07:31:09.90#ibcon#read 6, iclass 33, count 2 2006.224.07:31:09.90#ibcon#end of sib2, iclass 33, count 2 2006.224.07:31:09.90#ibcon#*after write, iclass 33, count 2 2006.224.07:31:09.90#ibcon#*before return 0, iclass 33, count 2 2006.224.07:31:09.90#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.224.07:31:09.90#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.224.07:31:09.90#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.224.07:31:09.90#ibcon#ireg 7 cls_cnt 0 2006.224.07:31:09.90#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.224.07:31:10.02#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.224.07:31:10.02#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.224.07:31:10.02#ibcon#enter wrdev, iclass 33, count 0 2006.224.07:31:10.02#ibcon#first serial, iclass 33, count 0 2006.224.07:31:10.02#ibcon#enter sib2, iclass 33, count 0 2006.224.07:31:10.02#ibcon#flushed, iclass 33, count 0 2006.224.07:31:10.02#ibcon#about to write, iclass 33, count 0 2006.224.07:31:10.02#ibcon#wrote, iclass 33, count 0 2006.224.07:31:10.02#ibcon#about to read 3, iclass 33, count 0 2006.224.07:31:10.04#ibcon#read 3, iclass 33, count 0 2006.224.07:31:10.04#ibcon#about to read 4, iclass 33, count 0 2006.224.07:31:10.04#ibcon#read 4, iclass 33, count 0 2006.224.07:31:10.04#ibcon#about to read 5, iclass 33, count 0 2006.224.07:31:10.04#ibcon#read 5, iclass 33, count 0 2006.224.07:31:10.04#ibcon#about to read 6, iclass 33, count 0 2006.224.07:31:10.04#ibcon#read 6, iclass 33, count 0 2006.224.07:31:10.04#ibcon#end of sib2, iclass 33, count 0 2006.224.07:31:10.04#ibcon#*mode == 0, iclass 33, count 0 2006.224.07:31:10.04#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.224.07:31:10.04#ibcon#[25=USB\r\n] 2006.224.07:31:10.04#ibcon#*before write, iclass 33, count 0 2006.224.07:31:10.04#ibcon#enter sib2, iclass 33, count 0 2006.224.07:31:10.04#ibcon#flushed, iclass 33, count 0 2006.224.07:31:10.04#ibcon#about to write, iclass 33, count 0 2006.224.07:31:10.04#ibcon#wrote, iclass 33, count 0 2006.224.07:31:10.04#ibcon#about to read 3, iclass 33, count 0 2006.224.07:31:10.07#ibcon#read 3, iclass 33, count 0 2006.224.07:31:10.07#ibcon#about to read 4, iclass 33, count 0 2006.224.07:31:10.07#ibcon#read 4, iclass 33, count 0 2006.224.07:31:10.07#ibcon#about to read 5, iclass 33, count 0 2006.224.07:31:10.07#ibcon#read 5, iclass 33, count 0 2006.224.07:31:10.07#ibcon#about to read 6, iclass 33, count 0 2006.224.07:31:10.07#ibcon#read 6, iclass 33, count 0 2006.224.07:31:10.07#ibcon#end of sib2, iclass 33, count 0 2006.224.07:31:10.07#ibcon#*after write, iclass 33, count 0 2006.224.07:31:10.07#ibcon#*before return 0, iclass 33, count 0 2006.224.07:31:10.07#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.224.07:31:10.07#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.224.07:31:10.07#ibcon#about to clear, iclass 33 cls_cnt 0 2006.224.07:31:10.07#ibcon#cleared, iclass 33 cls_cnt 0 2006.224.07:31:10.07$vc4f8/valo=7,832.99 2006.224.07:31:10.07#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.224.07:31:10.07#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.224.07:31:10.07#ibcon#ireg 17 cls_cnt 0 2006.224.07:31:10.07#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.224.07:31:10.07#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.224.07:31:10.07#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.224.07:31:10.07#ibcon#enter wrdev, iclass 35, count 0 2006.224.07:31:10.07#ibcon#first serial, iclass 35, count 0 2006.224.07:31:10.07#ibcon#enter sib2, iclass 35, count 0 2006.224.07:31:10.07#ibcon#flushed, iclass 35, count 0 2006.224.07:31:10.07#ibcon#about to write, iclass 35, count 0 2006.224.07:31:10.07#ibcon#wrote, iclass 35, count 0 2006.224.07:31:10.07#ibcon#about to read 3, iclass 35, count 0 2006.224.07:31:10.09#ibcon#read 3, iclass 35, count 0 2006.224.07:31:10.09#ibcon#about to read 4, iclass 35, count 0 2006.224.07:31:10.09#ibcon#read 4, iclass 35, count 0 2006.224.07:31:10.09#ibcon#about to read 5, iclass 35, count 0 2006.224.07:31:10.09#ibcon#read 5, iclass 35, count 0 2006.224.07:31:10.09#ibcon#about to read 6, iclass 35, count 0 2006.224.07:31:10.09#ibcon#read 6, iclass 35, count 0 2006.224.07:31:10.09#ibcon#end of sib2, iclass 35, count 0 2006.224.07:31:10.09#ibcon#*mode == 0, iclass 35, count 0 2006.224.07:31:10.09#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.224.07:31:10.09#ibcon#[26=FRQ=07,832.99\r\n] 2006.224.07:31:10.09#ibcon#*before write, iclass 35, count 0 2006.224.07:31:10.09#ibcon#enter sib2, iclass 35, count 0 2006.224.07:31:10.09#ibcon#flushed, iclass 35, count 0 2006.224.07:31:10.09#ibcon#about to write, iclass 35, count 0 2006.224.07:31:10.09#ibcon#wrote, iclass 35, count 0 2006.224.07:31:10.09#ibcon#about to read 3, iclass 35, count 0 2006.224.07:31:10.13#ibcon#read 3, iclass 35, count 0 2006.224.07:31:10.13#ibcon#about to read 4, iclass 35, count 0 2006.224.07:31:10.13#ibcon#read 4, iclass 35, count 0 2006.224.07:31:10.13#ibcon#about to read 5, iclass 35, count 0 2006.224.07:31:10.13#ibcon#read 5, iclass 35, count 0 2006.224.07:31:10.13#ibcon#about to read 6, iclass 35, count 0 2006.224.07:31:10.13#ibcon#read 6, iclass 35, count 0 2006.224.07:31:10.13#ibcon#end of sib2, iclass 35, count 0 2006.224.07:31:10.13#ibcon#*after write, iclass 35, count 0 2006.224.07:31:10.13#ibcon#*before return 0, iclass 35, count 0 2006.224.07:31:10.13#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.224.07:31:10.13#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.224.07:31:10.13#ibcon#about to clear, iclass 35 cls_cnt 0 2006.224.07:31:10.13#ibcon#cleared, iclass 35 cls_cnt 0 2006.224.07:31:10.13$vc4f8/va=7,6 2006.224.07:31:10.13#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.224.07:31:10.13#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.224.07:31:10.13#ibcon#ireg 11 cls_cnt 2 2006.224.07:31:10.13#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.224.07:31:10.19#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.224.07:31:10.19#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.224.07:31:10.19#ibcon#enter wrdev, iclass 37, count 2 2006.224.07:31:10.19#ibcon#first serial, iclass 37, count 2 2006.224.07:31:10.19#ibcon#enter sib2, iclass 37, count 2 2006.224.07:31:10.19#ibcon#flushed, iclass 37, count 2 2006.224.07:31:10.19#ibcon#about to write, iclass 37, count 2 2006.224.07:31:10.19#ibcon#wrote, iclass 37, count 2 2006.224.07:31:10.19#ibcon#about to read 3, iclass 37, count 2 2006.224.07:31:10.21#ibcon#read 3, iclass 37, count 2 2006.224.07:31:10.21#ibcon#about to read 4, iclass 37, count 2 2006.224.07:31:10.21#ibcon#read 4, iclass 37, count 2 2006.224.07:31:10.21#ibcon#about to read 5, iclass 37, count 2 2006.224.07:31:10.21#ibcon#read 5, iclass 37, count 2 2006.224.07:31:10.21#ibcon#about to read 6, iclass 37, count 2 2006.224.07:31:10.21#ibcon#read 6, iclass 37, count 2 2006.224.07:31:10.21#ibcon#end of sib2, iclass 37, count 2 2006.224.07:31:10.21#ibcon#*mode == 0, iclass 37, count 2 2006.224.07:31:10.21#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.224.07:31:10.21#ibcon#[25=AT07-06\r\n] 2006.224.07:31:10.21#ibcon#*before write, iclass 37, count 2 2006.224.07:31:10.21#ibcon#enter sib2, iclass 37, count 2 2006.224.07:31:10.21#ibcon#flushed, iclass 37, count 2 2006.224.07:31:10.21#ibcon#about to write, iclass 37, count 2 2006.224.07:31:10.21#ibcon#wrote, iclass 37, count 2 2006.224.07:31:10.21#ibcon#about to read 3, iclass 37, count 2 2006.224.07:31:10.24#ibcon#read 3, iclass 37, count 2 2006.224.07:31:10.24#ibcon#about to read 4, iclass 37, count 2 2006.224.07:31:10.24#ibcon#read 4, iclass 37, count 2 2006.224.07:31:10.24#ibcon#about to read 5, iclass 37, count 2 2006.224.07:31:10.24#ibcon#read 5, iclass 37, count 2 2006.224.07:31:10.24#ibcon#about to read 6, iclass 37, count 2 2006.224.07:31:10.24#ibcon#read 6, iclass 37, count 2 2006.224.07:31:10.24#ibcon#end of sib2, iclass 37, count 2 2006.224.07:31:10.24#ibcon#*after write, iclass 37, count 2 2006.224.07:31:10.24#ibcon#*before return 0, iclass 37, count 2 2006.224.07:31:10.24#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.224.07:31:10.24#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.224.07:31:10.24#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.224.07:31:10.24#ibcon#ireg 7 cls_cnt 0 2006.224.07:31:10.24#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.224.07:31:10.36#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.224.07:31:10.36#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.224.07:31:10.36#ibcon#enter wrdev, iclass 37, count 0 2006.224.07:31:10.36#ibcon#first serial, iclass 37, count 0 2006.224.07:31:10.36#ibcon#enter sib2, iclass 37, count 0 2006.224.07:31:10.36#ibcon#flushed, iclass 37, count 0 2006.224.07:31:10.36#ibcon#about to write, iclass 37, count 0 2006.224.07:31:10.36#ibcon#wrote, iclass 37, count 0 2006.224.07:31:10.36#ibcon#about to read 3, iclass 37, count 0 2006.224.07:31:10.38#ibcon#read 3, iclass 37, count 0 2006.224.07:31:10.38#ibcon#about to read 4, iclass 37, count 0 2006.224.07:31:10.38#ibcon#read 4, iclass 37, count 0 2006.224.07:31:10.38#ibcon#about to read 5, iclass 37, count 0 2006.224.07:31:10.38#ibcon#read 5, iclass 37, count 0 2006.224.07:31:10.38#ibcon#about to read 6, iclass 37, count 0 2006.224.07:31:10.38#ibcon#read 6, iclass 37, count 0 2006.224.07:31:10.38#ibcon#end of sib2, iclass 37, count 0 2006.224.07:31:10.38#ibcon#*mode == 0, iclass 37, count 0 2006.224.07:31:10.38#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.224.07:31:10.38#ibcon#[25=USB\r\n] 2006.224.07:31:10.38#ibcon#*before write, iclass 37, count 0 2006.224.07:31:10.38#ibcon#enter sib2, iclass 37, count 0 2006.224.07:31:10.38#ibcon#flushed, iclass 37, count 0 2006.224.07:31:10.38#ibcon#about to write, iclass 37, count 0 2006.224.07:31:10.38#ibcon#wrote, iclass 37, count 0 2006.224.07:31:10.38#ibcon#about to read 3, iclass 37, count 0 2006.224.07:31:10.41#ibcon#read 3, iclass 37, count 0 2006.224.07:31:10.41#ibcon#about to read 4, iclass 37, count 0 2006.224.07:31:10.41#ibcon#read 4, iclass 37, count 0 2006.224.07:31:10.41#ibcon#about to read 5, iclass 37, count 0 2006.224.07:31:10.41#ibcon#read 5, iclass 37, count 0 2006.224.07:31:10.41#ibcon#about to read 6, iclass 37, count 0 2006.224.07:31:10.41#ibcon#read 6, iclass 37, count 0 2006.224.07:31:10.41#ibcon#end of sib2, iclass 37, count 0 2006.224.07:31:10.41#ibcon#*after write, iclass 37, count 0 2006.224.07:31:10.41#ibcon#*before return 0, iclass 37, count 0 2006.224.07:31:10.41#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.224.07:31:10.41#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.224.07:31:10.41#ibcon#about to clear, iclass 37 cls_cnt 0 2006.224.07:31:10.41#ibcon#cleared, iclass 37 cls_cnt 0 2006.224.07:31:10.41$vc4f8/valo=8,852.99 2006.224.07:31:10.41#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.224.07:31:10.41#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.224.07:31:10.41#ibcon#ireg 17 cls_cnt 0 2006.224.07:31:10.41#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.224.07:31:10.41#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.224.07:31:10.41#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.224.07:31:10.41#ibcon#enter wrdev, iclass 39, count 0 2006.224.07:31:10.41#ibcon#first serial, iclass 39, count 0 2006.224.07:31:10.41#ibcon#enter sib2, iclass 39, count 0 2006.224.07:31:10.41#ibcon#flushed, iclass 39, count 0 2006.224.07:31:10.41#ibcon#about to write, iclass 39, count 0 2006.224.07:31:10.41#ibcon#wrote, iclass 39, count 0 2006.224.07:31:10.41#ibcon#about to read 3, iclass 39, count 0 2006.224.07:31:10.43#ibcon#read 3, iclass 39, count 0 2006.224.07:31:10.43#ibcon#about to read 4, iclass 39, count 0 2006.224.07:31:10.43#ibcon#read 4, iclass 39, count 0 2006.224.07:31:10.43#ibcon#about to read 5, iclass 39, count 0 2006.224.07:31:10.43#ibcon#read 5, iclass 39, count 0 2006.224.07:31:10.43#ibcon#about to read 6, iclass 39, count 0 2006.224.07:31:10.43#ibcon#read 6, iclass 39, count 0 2006.224.07:31:10.43#ibcon#end of sib2, iclass 39, count 0 2006.224.07:31:10.43#ibcon#*mode == 0, iclass 39, count 0 2006.224.07:31:10.43#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.224.07:31:10.43#ibcon#[26=FRQ=08,852.99\r\n] 2006.224.07:31:10.43#ibcon#*before write, iclass 39, count 0 2006.224.07:31:10.43#ibcon#enter sib2, iclass 39, count 0 2006.224.07:31:10.43#ibcon#flushed, iclass 39, count 0 2006.224.07:31:10.43#ibcon#about to write, iclass 39, count 0 2006.224.07:31:10.43#ibcon#wrote, iclass 39, count 0 2006.224.07:31:10.43#ibcon#about to read 3, iclass 39, count 0 2006.224.07:31:10.47#ibcon#read 3, iclass 39, count 0 2006.224.07:31:10.47#ibcon#about to read 4, iclass 39, count 0 2006.224.07:31:10.47#ibcon#read 4, iclass 39, count 0 2006.224.07:31:10.47#ibcon#about to read 5, iclass 39, count 0 2006.224.07:31:10.47#ibcon#read 5, iclass 39, count 0 2006.224.07:31:10.47#ibcon#about to read 6, iclass 39, count 0 2006.224.07:31:10.47#ibcon#read 6, iclass 39, count 0 2006.224.07:31:10.47#ibcon#end of sib2, iclass 39, count 0 2006.224.07:31:10.47#ibcon#*after write, iclass 39, count 0 2006.224.07:31:10.47#ibcon#*before return 0, iclass 39, count 0 2006.224.07:31:10.47#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.224.07:31:10.47#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.224.07:31:10.47#ibcon#about to clear, iclass 39 cls_cnt 0 2006.224.07:31:10.47#ibcon#cleared, iclass 39 cls_cnt 0 2006.224.07:31:10.47$vc4f8/va=8,7 2006.224.07:31:10.47#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.224.07:31:10.47#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.224.07:31:10.47#ibcon#ireg 11 cls_cnt 2 2006.224.07:31:10.47#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.224.07:31:10.53#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.224.07:31:10.53#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.224.07:31:10.53#ibcon#enter wrdev, iclass 3, count 2 2006.224.07:31:10.53#ibcon#first serial, iclass 3, count 2 2006.224.07:31:10.53#ibcon#enter sib2, iclass 3, count 2 2006.224.07:31:10.53#ibcon#flushed, iclass 3, count 2 2006.224.07:31:10.53#ibcon#about to write, iclass 3, count 2 2006.224.07:31:10.53#ibcon#wrote, iclass 3, count 2 2006.224.07:31:10.53#ibcon#about to read 3, iclass 3, count 2 2006.224.07:31:10.55#ibcon#read 3, iclass 3, count 2 2006.224.07:31:10.55#ibcon#about to read 4, iclass 3, count 2 2006.224.07:31:10.55#ibcon#read 4, iclass 3, count 2 2006.224.07:31:10.55#ibcon#about to read 5, iclass 3, count 2 2006.224.07:31:10.55#ibcon#read 5, iclass 3, count 2 2006.224.07:31:10.55#ibcon#about to read 6, iclass 3, count 2 2006.224.07:31:10.55#ibcon#read 6, iclass 3, count 2 2006.224.07:31:10.55#ibcon#end of sib2, iclass 3, count 2 2006.224.07:31:10.55#ibcon#*mode == 0, iclass 3, count 2 2006.224.07:31:10.55#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.224.07:31:10.55#ibcon#[25=AT08-07\r\n] 2006.224.07:31:10.55#ibcon#*before write, iclass 3, count 2 2006.224.07:31:10.55#ibcon#enter sib2, iclass 3, count 2 2006.224.07:31:10.55#ibcon#flushed, iclass 3, count 2 2006.224.07:31:10.55#ibcon#about to write, iclass 3, count 2 2006.224.07:31:10.55#ibcon#wrote, iclass 3, count 2 2006.224.07:31:10.55#ibcon#about to read 3, iclass 3, count 2 2006.224.07:31:10.58#ibcon#read 3, iclass 3, count 2 2006.224.07:31:10.58#ibcon#about to read 4, iclass 3, count 2 2006.224.07:31:10.58#ibcon#read 4, iclass 3, count 2 2006.224.07:31:10.58#ibcon#about to read 5, iclass 3, count 2 2006.224.07:31:10.58#ibcon#read 5, iclass 3, count 2 2006.224.07:31:10.58#ibcon#about to read 6, iclass 3, count 2 2006.224.07:31:10.58#ibcon#read 6, iclass 3, count 2 2006.224.07:31:10.58#ibcon#end of sib2, iclass 3, count 2 2006.224.07:31:10.58#ibcon#*after write, iclass 3, count 2 2006.224.07:31:10.58#ibcon#*before return 0, iclass 3, count 2 2006.224.07:31:10.58#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.224.07:31:10.58#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.224.07:31:10.58#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.224.07:31:10.58#ibcon#ireg 7 cls_cnt 0 2006.224.07:31:10.58#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.224.07:31:10.70#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.224.07:31:10.70#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.224.07:31:10.70#ibcon#enter wrdev, iclass 3, count 0 2006.224.07:31:10.70#ibcon#first serial, iclass 3, count 0 2006.224.07:31:10.70#ibcon#enter sib2, iclass 3, count 0 2006.224.07:31:10.70#ibcon#flushed, iclass 3, count 0 2006.224.07:31:10.70#ibcon#about to write, iclass 3, count 0 2006.224.07:31:10.70#ibcon#wrote, iclass 3, count 0 2006.224.07:31:10.70#ibcon#about to read 3, iclass 3, count 0 2006.224.07:31:10.72#ibcon#read 3, iclass 3, count 0 2006.224.07:31:10.72#ibcon#about to read 4, iclass 3, count 0 2006.224.07:31:10.72#ibcon#read 4, iclass 3, count 0 2006.224.07:31:10.72#ibcon#about to read 5, iclass 3, count 0 2006.224.07:31:10.72#ibcon#read 5, iclass 3, count 0 2006.224.07:31:10.72#ibcon#about to read 6, iclass 3, count 0 2006.224.07:31:10.72#ibcon#read 6, iclass 3, count 0 2006.224.07:31:10.72#ibcon#end of sib2, iclass 3, count 0 2006.224.07:31:10.72#ibcon#*mode == 0, iclass 3, count 0 2006.224.07:31:10.72#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.224.07:31:10.72#ibcon#[25=USB\r\n] 2006.224.07:31:10.72#ibcon#*before write, iclass 3, count 0 2006.224.07:31:10.72#ibcon#enter sib2, iclass 3, count 0 2006.224.07:31:10.72#ibcon#flushed, iclass 3, count 0 2006.224.07:31:10.72#ibcon#about to write, iclass 3, count 0 2006.224.07:31:10.72#ibcon#wrote, iclass 3, count 0 2006.224.07:31:10.72#ibcon#about to read 3, iclass 3, count 0 2006.224.07:31:10.75#ibcon#read 3, iclass 3, count 0 2006.224.07:31:10.75#ibcon#about to read 4, iclass 3, count 0 2006.224.07:31:10.75#ibcon#read 4, iclass 3, count 0 2006.224.07:31:10.75#ibcon#about to read 5, iclass 3, count 0 2006.224.07:31:10.75#ibcon#read 5, iclass 3, count 0 2006.224.07:31:10.75#ibcon#about to read 6, iclass 3, count 0 2006.224.07:31:10.75#ibcon#read 6, iclass 3, count 0 2006.224.07:31:10.75#ibcon#end of sib2, iclass 3, count 0 2006.224.07:31:10.75#ibcon#*after write, iclass 3, count 0 2006.224.07:31:10.75#ibcon#*before return 0, iclass 3, count 0 2006.224.07:31:10.75#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.224.07:31:10.75#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.224.07:31:10.75#ibcon#about to clear, iclass 3 cls_cnt 0 2006.224.07:31:10.75#ibcon#cleared, iclass 3 cls_cnt 0 2006.224.07:31:10.75$vc4f8/vblo=1,632.99 2006.224.07:31:10.75#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.224.07:31:10.75#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.224.07:31:10.75#ibcon#ireg 17 cls_cnt 0 2006.224.07:31:10.75#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.224.07:31:10.75#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.224.07:31:10.75#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.224.07:31:10.75#ibcon#enter wrdev, iclass 5, count 0 2006.224.07:31:10.75#ibcon#first serial, iclass 5, count 0 2006.224.07:31:10.75#ibcon#enter sib2, iclass 5, count 0 2006.224.07:31:10.75#ibcon#flushed, iclass 5, count 0 2006.224.07:31:10.75#ibcon#about to write, iclass 5, count 0 2006.224.07:31:10.75#ibcon#wrote, iclass 5, count 0 2006.224.07:31:10.75#ibcon#about to read 3, iclass 5, count 0 2006.224.07:31:10.77#ibcon#read 3, iclass 5, count 0 2006.224.07:31:10.77#ibcon#about to read 4, iclass 5, count 0 2006.224.07:31:10.77#ibcon#read 4, iclass 5, count 0 2006.224.07:31:10.77#ibcon#about to read 5, iclass 5, count 0 2006.224.07:31:10.77#ibcon#read 5, iclass 5, count 0 2006.224.07:31:10.77#ibcon#about to read 6, iclass 5, count 0 2006.224.07:31:10.77#ibcon#read 6, iclass 5, count 0 2006.224.07:31:10.77#ibcon#end of sib2, iclass 5, count 0 2006.224.07:31:10.77#ibcon#*mode == 0, iclass 5, count 0 2006.224.07:31:10.77#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.224.07:31:10.77#ibcon#[28=FRQ=01,632.99\r\n] 2006.224.07:31:10.77#ibcon#*before write, iclass 5, count 0 2006.224.07:31:10.77#ibcon#enter sib2, iclass 5, count 0 2006.224.07:31:10.77#ibcon#flushed, iclass 5, count 0 2006.224.07:31:10.77#ibcon#about to write, iclass 5, count 0 2006.224.07:31:10.77#ibcon#wrote, iclass 5, count 0 2006.224.07:31:10.77#ibcon#about to read 3, iclass 5, count 0 2006.224.07:31:10.82#ibcon#read 3, iclass 5, count 0 2006.224.07:31:10.82#ibcon#about to read 4, iclass 5, count 0 2006.224.07:31:10.82#ibcon#read 4, iclass 5, count 0 2006.224.07:31:10.82#ibcon#about to read 5, iclass 5, count 0 2006.224.07:31:10.82#ibcon#read 5, iclass 5, count 0 2006.224.07:31:10.82#ibcon#about to read 6, iclass 5, count 0 2006.224.07:31:10.82#ibcon#read 6, iclass 5, count 0 2006.224.07:31:10.82#ibcon#end of sib2, iclass 5, count 0 2006.224.07:31:10.82#ibcon#*after write, iclass 5, count 0 2006.224.07:31:10.82#ibcon#*before return 0, iclass 5, count 0 2006.224.07:31:10.82#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.224.07:31:10.82#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.224.07:31:10.82#ibcon#about to clear, iclass 5 cls_cnt 0 2006.224.07:31:10.82#ibcon#cleared, iclass 5 cls_cnt 0 2006.224.07:31:10.82$vc4f8/vb=1,4 2006.224.07:31:10.82#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.224.07:31:10.82#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.224.07:31:10.82#ibcon#ireg 11 cls_cnt 2 2006.224.07:31:10.82#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.224.07:31:10.82#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.224.07:31:10.82#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.224.07:31:10.82#ibcon#enter wrdev, iclass 7, count 2 2006.224.07:31:10.82#ibcon#first serial, iclass 7, count 2 2006.224.07:31:10.82#ibcon#enter sib2, iclass 7, count 2 2006.224.07:31:10.82#ibcon#flushed, iclass 7, count 2 2006.224.07:31:10.82#ibcon#about to write, iclass 7, count 2 2006.224.07:31:10.82#ibcon#wrote, iclass 7, count 2 2006.224.07:31:10.82#ibcon#about to read 3, iclass 7, count 2 2006.224.07:31:10.84#ibcon#read 3, iclass 7, count 2 2006.224.07:31:10.84#ibcon#about to read 4, iclass 7, count 2 2006.224.07:31:10.84#ibcon#read 4, iclass 7, count 2 2006.224.07:31:10.84#ibcon#about to read 5, iclass 7, count 2 2006.224.07:31:10.84#ibcon#read 5, iclass 7, count 2 2006.224.07:31:10.84#ibcon#about to read 6, iclass 7, count 2 2006.224.07:31:10.84#ibcon#read 6, iclass 7, count 2 2006.224.07:31:10.84#ibcon#end of sib2, iclass 7, count 2 2006.224.07:31:10.84#ibcon#*mode == 0, iclass 7, count 2 2006.224.07:31:10.84#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.224.07:31:10.84#ibcon#[27=AT01-04\r\n] 2006.224.07:31:10.84#ibcon#*before write, iclass 7, count 2 2006.224.07:31:10.84#ibcon#enter sib2, iclass 7, count 2 2006.224.07:31:10.84#ibcon#flushed, iclass 7, count 2 2006.224.07:31:10.84#ibcon#about to write, iclass 7, count 2 2006.224.07:31:10.84#ibcon#wrote, iclass 7, count 2 2006.224.07:31:10.84#ibcon#about to read 3, iclass 7, count 2 2006.224.07:31:10.87#ibcon#read 3, iclass 7, count 2 2006.224.07:31:10.87#ibcon#about to read 4, iclass 7, count 2 2006.224.07:31:10.87#ibcon#read 4, iclass 7, count 2 2006.224.07:31:10.87#ibcon#about to read 5, iclass 7, count 2 2006.224.07:31:10.87#ibcon#read 5, iclass 7, count 2 2006.224.07:31:10.87#ibcon#about to read 6, iclass 7, count 2 2006.224.07:31:10.87#ibcon#read 6, iclass 7, count 2 2006.224.07:31:10.87#ibcon#end of sib2, iclass 7, count 2 2006.224.07:31:10.87#ibcon#*after write, iclass 7, count 2 2006.224.07:31:10.87#ibcon#*before return 0, iclass 7, count 2 2006.224.07:31:10.87#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.224.07:31:10.87#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.224.07:31:10.87#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.224.07:31:10.87#ibcon#ireg 7 cls_cnt 0 2006.224.07:31:10.87#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.224.07:31:10.99#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.224.07:31:10.99#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.224.07:31:10.99#ibcon#enter wrdev, iclass 7, count 0 2006.224.07:31:10.99#ibcon#first serial, iclass 7, count 0 2006.224.07:31:10.99#ibcon#enter sib2, iclass 7, count 0 2006.224.07:31:10.99#ibcon#flushed, iclass 7, count 0 2006.224.07:31:10.99#ibcon#about to write, iclass 7, count 0 2006.224.07:31:10.99#ibcon#wrote, iclass 7, count 0 2006.224.07:31:10.99#ibcon#about to read 3, iclass 7, count 0 2006.224.07:31:11.01#ibcon#read 3, iclass 7, count 0 2006.224.07:31:11.01#ibcon#about to read 4, iclass 7, count 0 2006.224.07:31:11.01#ibcon#read 4, iclass 7, count 0 2006.224.07:31:11.01#ibcon#about to read 5, iclass 7, count 0 2006.224.07:31:11.01#ibcon#read 5, iclass 7, count 0 2006.224.07:31:11.01#ibcon#about to read 6, iclass 7, count 0 2006.224.07:31:11.01#ibcon#read 6, iclass 7, count 0 2006.224.07:31:11.01#ibcon#end of sib2, iclass 7, count 0 2006.224.07:31:11.01#ibcon#*mode == 0, iclass 7, count 0 2006.224.07:31:11.01#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.224.07:31:11.01#ibcon#[27=USB\r\n] 2006.224.07:31:11.01#ibcon#*before write, iclass 7, count 0 2006.224.07:31:11.01#ibcon#enter sib2, iclass 7, count 0 2006.224.07:31:11.01#ibcon#flushed, iclass 7, count 0 2006.224.07:31:11.01#ibcon#about to write, iclass 7, count 0 2006.224.07:31:11.01#ibcon#wrote, iclass 7, count 0 2006.224.07:31:11.01#ibcon#about to read 3, iclass 7, count 0 2006.224.07:31:11.04#ibcon#read 3, iclass 7, count 0 2006.224.07:31:11.04#ibcon#about to read 4, iclass 7, count 0 2006.224.07:31:11.04#ibcon#read 4, iclass 7, count 0 2006.224.07:31:11.04#ibcon#about to read 5, iclass 7, count 0 2006.224.07:31:11.04#ibcon#read 5, iclass 7, count 0 2006.224.07:31:11.04#ibcon#about to read 6, iclass 7, count 0 2006.224.07:31:11.04#ibcon#read 6, iclass 7, count 0 2006.224.07:31:11.04#ibcon#end of sib2, iclass 7, count 0 2006.224.07:31:11.04#ibcon#*after write, iclass 7, count 0 2006.224.07:31:11.04#ibcon#*before return 0, iclass 7, count 0 2006.224.07:31:11.04#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.224.07:31:11.04#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.224.07:31:11.04#ibcon#about to clear, iclass 7 cls_cnt 0 2006.224.07:31:11.04#ibcon#cleared, iclass 7 cls_cnt 0 2006.224.07:31:11.04$vc4f8/vblo=2,640.99 2006.224.07:31:11.04#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.224.07:31:11.04#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.224.07:31:11.04#ibcon#ireg 17 cls_cnt 0 2006.224.07:31:11.04#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.224.07:31:11.04#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.224.07:31:11.04#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.224.07:31:11.04#ibcon#enter wrdev, iclass 11, count 0 2006.224.07:31:11.04#ibcon#first serial, iclass 11, count 0 2006.224.07:31:11.04#ibcon#enter sib2, iclass 11, count 0 2006.224.07:31:11.04#ibcon#flushed, iclass 11, count 0 2006.224.07:31:11.04#ibcon#about to write, iclass 11, count 0 2006.224.07:31:11.04#ibcon#wrote, iclass 11, count 0 2006.224.07:31:11.04#ibcon#about to read 3, iclass 11, count 0 2006.224.07:31:11.06#ibcon#read 3, iclass 11, count 0 2006.224.07:31:11.06#ibcon#about to read 4, iclass 11, count 0 2006.224.07:31:11.06#ibcon#read 4, iclass 11, count 0 2006.224.07:31:11.06#ibcon#about to read 5, iclass 11, count 0 2006.224.07:31:11.06#ibcon#read 5, iclass 11, count 0 2006.224.07:31:11.06#ibcon#about to read 6, iclass 11, count 0 2006.224.07:31:11.06#ibcon#read 6, iclass 11, count 0 2006.224.07:31:11.06#ibcon#end of sib2, iclass 11, count 0 2006.224.07:31:11.06#ibcon#*mode == 0, iclass 11, count 0 2006.224.07:31:11.06#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.224.07:31:11.06#ibcon#[28=FRQ=02,640.99\r\n] 2006.224.07:31:11.06#ibcon#*before write, iclass 11, count 0 2006.224.07:31:11.06#ibcon#enter sib2, iclass 11, count 0 2006.224.07:31:11.06#ibcon#flushed, iclass 11, count 0 2006.224.07:31:11.06#ibcon#about to write, iclass 11, count 0 2006.224.07:31:11.06#ibcon#wrote, iclass 11, count 0 2006.224.07:31:11.06#ibcon#about to read 3, iclass 11, count 0 2006.224.07:31:11.10#ibcon#read 3, iclass 11, count 0 2006.224.07:31:11.10#ibcon#about to read 4, iclass 11, count 0 2006.224.07:31:11.10#ibcon#read 4, iclass 11, count 0 2006.224.07:31:11.10#ibcon#about to read 5, iclass 11, count 0 2006.224.07:31:11.10#ibcon#read 5, iclass 11, count 0 2006.224.07:31:11.10#ibcon#about to read 6, iclass 11, count 0 2006.224.07:31:11.10#ibcon#read 6, iclass 11, count 0 2006.224.07:31:11.10#ibcon#end of sib2, iclass 11, count 0 2006.224.07:31:11.10#ibcon#*after write, iclass 11, count 0 2006.224.07:31:11.10#ibcon#*before return 0, iclass 11, count 0 2006.224.07:31:11.10#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.224.07:31:11.10#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.224.07:31:11.10#ibcon#about to clear, iclass 11 cls_cnt 0 2006.224.07:31:11.10#ibcon#cleared, iclass 11 cls_cnt 0 2006.224.07:31:11.10$vc4f8/vb=2,4 2006.224.07:31:11.10#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.224.07:31:11.10#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.224.07:31:11.10#ibcon#ireg 11 cls_cnt 2 2006.224.07:31:11.10#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.224.07:31:11.16#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.224.07:31:11.16#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.224.07:31:11.16#ibcon#enter wrdev, iclass 13, count 2 2006.224.07:31:11.16#ibcon#first serial, iclass 13, count 2 2006.224.07:31:11.16#ibcon#enter sib2, iclass 13, count 2 2006.224.07:31:11.16#ibcon#flushed, iclass 13, count 2 2006.224.07:31:11.16#ibcon#about to write, iclass 13, count 2 2006.224.07:31:11.16#ibcon#wrote, iclass 13, count 2 2006.224.07:31:11.16#ibcon#about to read 3, iclass 13, count 2 2006.224.07:31:11.18#ibcon#read 3, iclass 13, count 2 2006.224.07:31:11.18#ibcon#about to read 4, iclass 13, count 2 2006.224.07:31:11.18#ibcon#read 4, iclass 13, count 2 2006.224.07:31:11.18#ibcon#about to read 5, iclass 13, count 2 2006.224.07:31:11.18#ibcon#read 5, iclass 13, count 2 2006.224.07:31:11.18#ibcon#about to read 6, iclass 13, count 2 2006.224.07:31:11.18#ibcon#read 6, iclass 13, count 2 2006.224.07:31:11.18#ibcon#end of sib2, iclass 13, count 2 2006.224.07:31:11.18#ibcon#*mode == 0, iclass 13, count 2 2006.224.07:31:11.18#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.224.07:31:11.18#ibcon#[27=AT02-04\r\n] 2006.224.07:31:11.18#ibcon#*before write, iclass 13, count 2 2006.224.07:31:11.18#ibcon#enter sib2, iclass 13, count 2 2006.224.07:31:11.18#ibcon#flushed, iclass 13, count 2 2006.224.07:31:11.18#ibcon#about to write, iclass 13, count 2 2006.224.07:31:11.18#ibcon#wrote, iclass 13, count 2 2006.224.07:31:11.18#ibcon#about to read 3, iclass 13, count 2 2006.224.07:31:11.21#ibcon#read 3, iclass 13, count 2 2006.224.07:31:11.21#ibcon#about to read 4, iclass 13, count 2 2006.224.07:31:11.21#ibcon#read 4, iclass 13, count 2 2006.224.07:31:11.21#ibcon#about to read 5, iclass 13, count 2 2006.224.07:31:11.21#ibcon#read 5, iclass 13, count 2 2006.224.07:31:11.21#ibcon#about to read 6, iclass 13, count 2 2006.224.07:31:11.21#ibcon#read 6, iclass 13, count 2 2006.224.07:31:11.21#ibcon#end of sib2, iclass 13, count 2 2006.224.07:31:11.21#ibcon#*after write, iclass 13, count 2 2006.224.07:31:11.21#ibcon#*before return 0, iclass 13, count 2 2006.224.07:31:11.21#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.224.07:31:11.21#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.224.07:31:11.21#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.224.07:31:11.21#ibcon#ireg 7 cls_cnt 0 2006.224.07:31:11.21#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.224.07:31:11.33#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.224.07:31:11.33#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.224.07:31:11.33#ibcon#enter wrdev, iclass 13, count 0 2006.224.07:31:11.33#ibcon#first serial, iclass 13, count 0 2006.224.07:31:11.33#ibcon#enter sib2, iclass 13, count 0 2006.224.07:31:11.33#ibcon#flushed, iclass 13, count 0 2006.224.07:31:11.33#ibcon#about to write, iclass 13, count 0 2006.224.07:31:11.33#ibcon#wrote, iclass 13, count 0 2006.224.07:31:11.33#ibcon#about to read 3, iclass 13, count 0 2006.224.07:31:11.35#ibcon#read 3, iclass 13, count 0 2006.224.07:31:11.35#ibcon#about to read 4, iclass 13, count 0 2006.224.07:31:11.35#ibcon#read 4, iclass 13, count 0 2006.224.07:31:11.35#ibcon#about to read 5, iclass 13, count 0 2006.224.07:31:11.35#ibcon#read 5, iclass 13, count 0 2006.224.07:31:11.35#ibcon#about to read 6, iclass 13, count 0 2006.224.07:31:11.35#ibcon#read 6, iclass 13, count 0 2006.224.07:31:11.35#ibcon#end of sib2, iclass 13, count 0 2006.224.07:31:11.35#ibcon#*mode == 0, iclass 13, count 0 2006.224.07:31:11.35#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.224.07:31:11.35#ibcon#[27=USB\r\n] 2006.224.07:31:11.35#ibcon#*before write, iclass 13, count 0 2006.224.07:31:11.35#ibcon#enter sib2, iclass 13, count 0 2006.224.07:31:11.35#ibcon#flushed, iclass 13, count 0 2006.224.07:31:11.35#ibcon#about to write, iclass 13, count 0 2006.224.07:31:11.35#ibcon#wrote, iclass 13, count 0 2006.224.07:31:11.35#ibcon#about to read 3, iclass 13, count 0 2006.224.07:31:11.38#ibcon#read 3, iclass 13, count 0 2006.224.07:31:11.38#ibcon#about to read 4, iclass 13, count 0 2006.224.07:31:11.38#ibcon#read 4, iclass 13, count 0 2006.224.07:31:11.38#ibcon#about to read 5, iclass 13, count 0 2006.224.07:31:11.38#ibcon#read 5, iclass 13, count 0 2006.224.07:31:11.38#ibcon#about to read 6, iclass 13, count 0 2006.224.07:31:11.38#ibcon#read 6, iclass 13, count 0 2006.224.07:31:11.38#ibcon#end of sib2, iclass 13, count 0 2006.224.07:31:11.38#ibcon#*after write, iclass 13, count 0 2006.224.07:31:11.38#ibcon#*before return 0, iclass 13, count 0 2006.224.07:31:11.38#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.224.07:31:11.38#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.224.07:31:11.38#ibcon#about to clear, iclass 13 cls_cnt 0 2006.224.07:31:11.38#ibcon#cleared, iclass 13 cls_cnt 0 2006.224.07:31:11.38$vc4f8/vblo=3,656.99 2006.224.07:31:11.38#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.224.07:31:11.38#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.224.07:31:11.38#ibcon#ireg 17 cls_cnt 0 2006.224.07:31:11.38#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.224.07:31:11.38#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.224.07:31:11.38#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.224.07:31:11.38#ibcon#enter wrdev, iclass 15, count 0 2006.224.07:31:11.38#ibcon#first serial, iclass 15, count 0 2006.224.07:31:11.38#ibcon#enter sib2, iclass 15, count 0 2006.224.07:31:11.38#ibcon#flushed, iclass 15, count 0 2006.224.07:31:11.38#ibcon#about to write, iclass 15, count 0 2006.224.07:31:11.38#ibcon#wrote, iclass 15, count 0 2006.224.07:31:11.38#ibcon#about to read 3, iclass 15, count 0 2006.224.07:31:11.40#ibcon#read 3, iclass 15, count 0 2006.224.07:31:11.40#ibcon#about to read 4, iclass 15, count 0 2006.224.07:31:11.40#ibcon#read 4, iclass 15, count 0 2006.224.07:31:11.40#ibcon#about to read 5, iclass 15, count 0 2006.224.07:31:11.40#ibcon#read 5, iclass 15, count 0 2006.224.07:31:11.40#ibcon#about to read 6, iclass 15, count 0 2006.224.07:31:11.40#ibcon#read 6, iclass 15, count 0 2006.224.07:31:11.40#ibcon#end of sib2, iclass 15, count 0 2006.224.07:31:11.40#ibcon#*mode == 0, iclass 15, count 0 2006.224.07:31:11.40#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.224.07:31:11.40#ibcon#[28=FRQ=03,656.99\r\n] 2006.224.07:31:11.40#ibcon#*before write, iclass 15, count 0 2006.224.07:31:11.40#ibcon#enter sib2, iclass 15, count 0 2006.224.07:31:11.40#ibcon#flushed, iclass 15, count 0 2006.224.07:31:11.40#ibcon#about to write, iclass 15, count 0 2006.224.07:31:11.40#ibcon#wrote, iclass 15, count 0 2006.224.07:31:11.40#ibcon#about to read 3, iclass 15, count 0 2006.224.07:31:11.44#ibcon#read 3, iclass 15, count 0 2006.224.07:31:11.44#ibcon#about to read 4, iclass 15, count 0 2006.224.07:31:11.44#ibcon#read 4, iclass 15, count 0 2006.224.07:31:11.44#ibcon#about to read 5, iclass 15, count 0 2006.224.07:31:11.44#ibcon#read 5, iclass 15, count 0 2006.224.07:31:11.44#ibcon#about to read 6, iclass 15, count 0 2006.224.07:31:11.44#ibcon#read 6, iclass 15, count 0 2006.224.07:31:11.44#ibcon#end of sib2, iclass 15, count 0 2006.224.07:31:11.44#ibcon#*after write, iclass 15, count 0 2006.224.07:31:11.44#ibcon#*before return 0, iclass 15, count 0 2006.224.07:31:11.44#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.224.07:31:11.44#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.224.07:31:11.44#ibcon#about to clear, iclass 15 cls_cnt 0 2006.224.07:31:11.44#ibcon#cleared, iclass 15 cls_cnt 0 2006.224.07:31:11.44$vc4f8/vb=3,4 2006.224.07:31:11.44#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.224.07:31:11.44#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.224.07:31:11.44#ibcon#ireg 11 cls_cnt 2 2006.224.07:31:11.44#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.224.07:31:11.50#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.224.07:31:11.50#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.224.07:31:11.50#ibcon#enter wrdev, iclass 17, count 2 2006.224.07:31:11.50#ibcon#first serial, iclass 17, count 2 2006.224.07:31:11.50#ibcon#enter sib2, iclass 17, count 2 2006.224.07:31:11.50#ibcon#flushed, iclass 17, count 2 2006.224.07:31:11.50#ibcon#about to write, iclass 17, count 2 2006.224.07:31:11.50#ibcon#wrote, iclass 17, count 2 2006.224.07:31:11.50#ibcon#about to read 3, iclass 17, count 2 2006.224.07:31:11.52#ibcon#read 3, iclass 17, count 2 2006.224.07:31:11.52#ibcon#about to read 4, iclass 17, count 2 2006.224.07:31:11.52#ibcon#read 4, iclass 17, count 2 2006.224.07:31:11.52#ibcon#about to read 5, iclass 17, count 2 2006.224.07:31:11.52#ibcon#read 5, iclass 17, count 2 2006.224.07:31:11.52#ibcon#about to read 6, iclass 17, count 2 2006.224.07:31:11.52#ibcon#read 6, iclass 17, count 2 2006.224.07:31:11.52#ibcon#end of sib2, iclass 17, count 2 2006.224.07:31:11.52#ibcon#*mode == 0, iclass 17, count 2 2006.224.07:31:11.52#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.224.07:31:11.52#ibcon#[27=AT03-04\r\n] 2006.224.07:31:11.52#ibcon#*before write, iclass 17, count 2 2006.224.07:31:11.52#ibcon#enter sib2, iclass 17, count 2 2006.224.07:31:11.52#ibcon#flushed, iclass 17, count 2 2006.224.07:31:11.52#ibcon#about to write, iclass 17, count 2 2006.224.07:31:11.52#ibcon#wrote, iclass 17, count 2 2006.224.07:31:11.52#ibcon#about to read 3, iclass 17, count 2 2006.224.07:31:11.55#ibcon#read 3, iclass 17, count 2 2006.224.07:31:11.55#ibcon#about to read 4, iclass 17, count 2 2006.224.07:31:11.55#ibcon#read 4, iclass 17, count 2 2006.224.07:31:11.55#ibcon#about to read 5, iclass 17, count 2 2006.224.07:31:11.55#ibcon#read 5, iclass 17, count 2 2006.224.07:31:11.55#ibcon#about to read 6, iclass 17, count 2 2006.224.07:31:11.55#ibcon#read 6, iclass 17, count 2 2006.224.07:31:11.55#ibcon#end of sib2, iclass 17, count 2 2006.224.07:31:11.55#ibcon#*after write, iclass 17, count 2 2006.224.07:31:11.55#ibcon#*before return 0, iclass 17, count 2 2006.224.07:31:11.55#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.224.07:31:11.55#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.224.07:31:11.55#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.224.07:31:11.55#ibcon#ireg 7 cls_cnt 0 2006.224.07:31:11.55#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.224.07:31:11.67#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.224.07:31:11.67#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.224.07:31:11.67#ibcon#enter wrdev, iclass 17, count 0 2006.224.07:31:11.67#ibcon#first serial, iclass 17, count 0 2006.224.07:31:11.67#ibcon#enter sib2, iclass 17, count 0 2006.224.07:31:11.67#ibcon#flushed, iclass 17, count 0 2006.224.07:31:11.67#ibcon#about to write, iclass 17, count 0 2006.224.07:31:11.67#ibcon#wrote, iclass 17, count 0 2006.224.07:31:11.67#ibcon#about to read 3, iclass 17, count 0 2006.224.07:31:11.69#ibcon#read 3, iclass 17, count 0 2006.224.07:31:11.69#ibcon#about to read 4, iclass 17, count 0 2006.224.07:31:11.69#ibcon#read 4, iclass 17, count 0 2006.224.07:31:11.69#ibcon#about to read 5, iclass 17, count 0 2006.224.07:31:11.69#ibcon#read 5, iclass 17, count 0 2006.224.07:31:11.69#ibcon#about to read 6, iclass 17, count 0 2006.224.07:31:11.69#ibcon#read 6, iclass 17, count 0 2006.224.07:31:11.69#ibcon#end of sib2, iclass 17, count 0 2006.224.07:31:11.69#ibcon#*mode == 0, iclass 17, count 0 2006.224.07:31:11.69#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.224.07:31:11.69#ibcon#[27=USB\r\n] 2006.224.07:31:11.69#ibcon#*before write, iclass 17, count 0 2006.224.07:31:11.69#ibcon#enter sib2, iclass 17, count 0 2006.224.07:31:11.69#ibcon#flushed, iclass 17, count 0 2006.224.07:31:11.69#ibcon#about to write, iclass 17, count 0 2006.224.07:31:11.69#ibcon#wrote, iclass 17, count 0 2006.224.07:31:11.69#ibcon#about to read 3, iclass 17, count 0 2006.224.07:31:11.72#ibcon#read 3, iclass 17, count 0 2006.224.07:31:11.72#ibcon#about to read 4, iclass 17, count 0 2006.224.07:31:11.72#ibcon#read 4, iclass 17, count 0 2006.224.07:31:11.72#ibcon#about to read 5, iclass 17, count 0 2006.224.07:31:11.72#ibcon#read 5, iclass 17, count 0 2006.224.07:31:11.72#ibcon#about to read 6, iclass 17, count 0 2006.224.07:31:11.72#ibcon#read 6, iclass 17, count 0 2006.224.07:31:11.72#ibcon#end of sib2, iclass 17, count 0 2006.224.07:31:11.72#ibcon#*after write, iclass 17, count 0 2006.224.07:31:11.72#ibcon#*before return 0, iclass 17, count 0 2006.224.07:31:11.72#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.224.07:31:11.72#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.224.07:31:11.72#ibcon#about to clear, iclass 17 cls_cnt 0 2006.224.07:31:11.72#ibcon#cleared, iclass 17 cls_cnt 0 2006.224.07:31:11.72$vc4f8/vblo=4,712.99 2006.224.07:31:11.72#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.224.07:31:11.72#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.224.07:31:11.72#ibcon#ireg 17 cls_cnt 0 2006.224.07:31:11.72#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.224.07:31:11.72#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.224.07:31:11.72#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.224.07:31:11.72#ibcon#enter wrdev, iclass 19, count 0 2006.224.07:31:11.72#ibcon#first serial, iclass 19, count 0 2006.224.07:31:11.72#ibcon#enter sib2, iclass 19, count 0 2006.224.07:31:11.72#ibcon#flushed, iclass 19, count 0 2006.224.07:31:11.72#ibcon#about to write, iclass 19, count 0 2006.224.07:31:11.72#ibcon#wrote, iclass 19, count 0 2006.224.07:31:11.72#ibcon#about to read 3, iclass 19, count 0 2006.224.07:31:11.74#ibcon#read 3, iclass 19, count 0 2006.224.07:31:11.74#ibcon#about to read 4, iclass 19, count 0 2006.224.07:31:11.74#ibcon#read 4, iclass 19, count 0 2006.224.07:31:11.74#ibcon#about to read 5, iclass 19, count 0 2006.224.07:31:11.74#ibcon#read 5, iclass 19, count 0 2006.224.07:31:11.74#ibcon#about to read 6, iclass 19, count 0 2006.224.07:31:11.74#ibcon#read 6, iclass 19, count 0 2006.224.07:31:11.74#ibcon#end of sib2, iclass 19, count 0 2006.224.07:31:11.74#ibcon#*mode == 0, iclass 19, count 0 2006.224.07:31:11.74#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.224.07:31:11.74#ibcon#[28=FRQ=04,712.99\r\n] 2006.224.07:31:11.74#ibcon#*before write, iclass 19, count 0 2006.224.07:31:11.74#ibcon#enter sib2, iclass 19, count 0 2006.224.07:31:11.74#ibcon#flushed, iclass 19, count 0 2006.224.07:31:11.74#ibcon#about to write, iclass 19, count 0 2006.224.07:31:11.74#ibcon#wrote, iclass 19, count 0 2006.224.07:31:11.74#ibcon#about to read 3, iclass 19, count 0 2006.224.07:31:11.78#ibcon#read 3, iclass 19, count 0 2006.224.07:31:11.78#ibcon#about to read 4, iclass 19, count 0 2006.224.07:31:11.78#ibcon#read 4, iclass 19, count 0 2006.224.07:31:11.78#ibcon#about to read 5, iclass 19, count 0 2006.224.07:31:11.78#ibcon#read 5, iclass 19, count 0 2006.224.07:31:11.78#ibcon#about to read 6, iclass 19, count 0 2006.224.07:31:11.78#ibcon#read 6, iclass 19, count 0 2006.224.07:31:11.78#ibcon#end of sib2, iclass 19, count 0 2006.224.07:31:11.78#ibcon#*after write, iclass 19, count 0 2006.224.07:31:11.78#ibcon#*before return 0, iclass 19, count 0 2006.224.07:31:11.78#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.224.07:31:11.78#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.224.07:31:11.78#ibcon#about to clear, iclass 19 cls_cnt 0 2006.224.07:31:11.78#ibcon#cleared, iclass 19 cls_cnt 0 2006.224.07:31:11.78$vc4f8/vb=4,4 2006.224.07:31:11.78#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.224.07:31:11.78#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.224.07:31:11.78#ibcon#ireg 11 cls_cnt 2 2006.224.07:31:11.78#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.224.07:31:11.84#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.224.07:31:11.84#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.224.07:31:11.84#ibcon#enter wrdev, iclass 21, count 2 2006.224.07:31:11.84#ibcon#first serial, iclass 21, count 2 2006.224.07:31:11.84#ibcon#enter sib2, iclass 21, count 2 2006.224.07:31:11.84#ibcon#flushed, iclass 21, count 2 2006.224.07:31:11.84#ibcon#about to write, iclass 21, count 2 2006.224.07:31:11.84#ibcon#wrote, iclass 21, count 2 2006.224.07:31:11.84#ibcon#about to read 3, iclass 21, count 2 2006.224.07:31:11.86#ibcon#read 3, iclass 21, count 2 2006.224.07:31:11.86#ibcon#about to read 4, iclass 21, count 2 2006.224.07:31:11.86#ibcon#read 4, iclass 21, count 2 2006.224.07:31:11.86#ibcon#about to read 5, iclass 21, count 2 2006.224.07:31:11.86#ibcon#read 5, iclass 21, count 2 2006.224.07:31:11.86#ibcon#about to read 6, iclass 21, count 2 2006.224.07:31:11.86#ibcon#read 6, iclass 21, count 2 2006.224.07:31:11.86#ibcon#end of sib2, iclass 21, count 2 2006.224.07:31:11.86#ibcon#*mode == 0, iclass 21, count 2 2006.224.07:31:11.86#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.224.07:31:11.86#ibcon#[27=AT04-04\r\n] 2006.224.07:31:11.86#ibcon#*before write, iclass 21, count 2 2006.224.07:31:11.86#ibcon#enter sib2, iclass 21, count 2 2006.224.07:31:11.86#ibcon#flushed, iclass 21, count 2 2006.224.07:31:11.86#ibcon#about to write, iclass 21, count 2 2006.224.07:31:11.86#ibcon#wrote, iclass 21, count 2 2006.224.07:31:11.86#ibcon#about to read 3, iclass 21, count 2 2006.224.07:31:11.89#ibcon#read 3, iclass 21, count 2 2006.224.07:31:11.89#ibcon#about to read 4, iclass 21, count 2 2006.224.07:31:11.89#ibcon#read 4, iclass 21, count 2 2006.224.07:31:11.89#ibcon#about to read 5, iclass 21, count 2 2006.224.07:31:11.89#ibcon#read 5, iclass 21, count 2 2006.224.07:31:11.89#ibcon#about to read 6, iclass 21, count 2 2006.224.07:31:11.89#ibcon#read 6, iclass 21, count 2 2006.224.07:31:11.89#ibcon#end of sib2, iclass 21, count 2 2006.224.07:31:11.89#ibcon#*after write, iclass 21, count 2 2006.224.07:31:11.89#ibcon#*before return 0, iclass 21, count 2 2006.224.07:31:11.89#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.224.07:31:11.89#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.224.07:31:11.89#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.224.07:31:11.89#ibcon#ireg 7 cls_cnt 0 2006.224.07:31:11.89#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.224.07:31:12.01#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.224.07:31:12.01#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.224.07:31:12.01#ibcon#enter wrdev, iclass 21, count 0 2006.224.07:31:12.01#ibcon#first serial, iclass 21, count 0 2006.224.07:31:12.01#ibcon#enter sib2, iclass 21, count 0 2006.224.07:31:12.01#ibcon#flushed, iclass 21, count 0 2006.224.07:31:12.01#ibcon#about to write, iclass 21, count 0 2006.224.07:31:12.01#ibcon#wrote, iclass 21, count 0 2006.224.07:31:12.01#ibcon#about to read 3, iclass 21, count 0 2006.224.07:31:12.03#ibcon#read 3, iclass 21, count 0 2006.224.07:31:12.03#ibcon#about to read 4, iclass 21, count 0 2006.224.07:31:12.03#ibcon#read 4, iclass 21, count 0 2006.224.07:31:12.03#ibcon#about to read 5, iclass 21, count 0 2006.224.07:31:12.03#ibcon#read 5, iclass 21, count 0 2006.224.07:31:12.03#ibcon#about to read 6, iclass 21, count 0 2006.224.07:31:12.03#ibcon#read 6, iclass 21, count 0 2006.224.07:31:12.03#ibcon#end of sib2, iclass 21, count 0 2006.224.07:31:12.03#ibcon#*mode == 0, iclass 21, count 0 2006.224.07:31:12.03#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.224.07:31:12.03#ibcon#[27=USB\r\n] 2006.224.07:31:12.03#ibcon#*before write, iclass 21, count 0 2006.224.07:31:12.03#ibcon#enter sib2, iclass 21, count 0 2006.224.07:31:12.03#ibcon#flushed, iclass 21, count 0 2006.224.07:31:12.03#ibcon#about to write, iclass 21, count 0 2006.224.07:31:12.03#ibcon#wrote, iclass 21, count 0 2006.224.07:31:12.03#ibcon#about to read 3, iclass 21, count 0 2006.224.07:31:12.05#abcon#<5=/04 1.5 2.7 23.361001004.1\r\n> 2006.224.07:31:12.06#ibcon#read 3, iclass 21, count 0 2006.224.07:31:12.06#ibcon#about to read 4, iclass 21, count 0 2006.224.07:31:12.06#ibcon#read 4, iclass 21, count 0 2006.224.07:31:12.06#ibcon#about to read 5, iclass 21, count 0 2006.224.07:31:12.06#ibcon#read 5, iclass 21, count 0 2006.224.07:31:12.06#ibcon#about to read 6, iclass 21, count 0 2006.224.07:31:12.06#ibcon#read 6, iclass 21, count 0 2006.224.07:31:12.06#ibcon#end of sib2, iclass 21, count 0 2006.224.07:31:12.06#ibcon#*after write, iclass 21, count 0 2006.224.07:31:12.06#ibcon#*before return 0, iclass 21, count 0 2006.224.07:31:12.06#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.224.07:31:12.06#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.224.07:31:12.06#ibcon#about to clear, iclass 21 cls_cnt 0 2006.224.07:31:12.06#ibcon#cleared, iclass 21 cls_cnt 0 2006.224.07:31:12.06$vc4f8/vblo=5,744.99 2006.224.07:31:12.06#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.224.07:31:12.06#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.224.07:31:12.06#ibcon#ireg 17 cls_cnt 0 2006.224.07:31:12.06#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.224.07:31:12.06#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.224.07:31:12.06#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.224.07:31:12.06#ibcon#enter wrdev, iclass 26, count 0 2006.224.07:31:12.06#ibcon#first serial, iclass 26, count 0 2006.224.07:31:12.06#ibcon#enter sib2, iclass 26, count 0 2006.224.07:31:12.06#ibcon#flushed, iclass 26, count 0 2006.224.07:31:12.06#ibcon#about to write, iclass 26, count 0 2006.224.07:31:12.06#ibcon#wrote, iclass 26, count 0 2006.224.07:31:12.06#ibcon#about to read 3, iclass 26, count 0 2006.224.07:31:12.07#abcon#{5=INTERFACE CLEAR} 2006.224.07:31:12.08#ibcon#read 3, iclass 26, count 0 2006.224.07:31:12.08#ibcon#about to read 4, iclass 26, count 0 2006.224.07:31:12.08#ibcon#read 4, iclass 26, count 0 2006.224.07:31:12.08#ibcon#about to read 5, iclass 26, count 0 2006.224.07:31:12.08#ibcon#read 5, iclass 26, count 0 2006.224.07:31:12.08#ibcon#about to read 6, iclass 26, count 0 2006.224.07:31:12.08#ibcon#read 6, iclass 26, count 0 2006.224.07:31:12.08#ibcon#end of sib2, iclass 26, count 0 2006.224.07:31:12.08#ibcon#*mode == 0, iclass 26, count 0 2006.224.07:31:12.08#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.224.07:31:12.08#ibcon#[28=FRQ=05,744.99\r\n] 2006.224.07:31:12.08#ibcon#*before write, iclass 26, count 0 2006.224.07:31:12.08#ibcon#enter sib2, iclass 26, count 0 2006.224.07:31:12.08#ibcon#flushed, iclass 26, count 0 2006.224.07:31:12.08#ibcon#about to write, iclass 26, count 0 2006.224.07:31:12.08#ibcon#wrote, iclass 26, count 0 2006.224.07:31:12.08#ibcon#about to read 3, iclass 26, count 0 2006.224.07:31:12.12#ibcon#read 3, iclass 26, count 0 2006.224.07:31:12.12#ibcon#about to read 4, iclass 26, count 0 2006.224.07:31:12.12#ibcon#read 4, iclass 26, count 0 2006.224.07:31:12.12#ibcon#about to read 5, iclass 26, count 0 2006.224.07:31:12.12#ibcon#read 5, iclass 26, count 0 2006.224.07:31:12.12#ibcon#about to read 6, iclass 26, count 0 2006.224.07:31:12.12#ibcon#read 6, iclass 26, count 0 2006.224.07:31:12.12#ibcon#end of sib2, iclass 26, count 0 2006.224.07:31:12.12#ibcon#*after write, iclass 26, count 0 2006.224.07:31:12.12#ibcon#*before return 0, iclass 26, count 0 2006.224.07:31:12.12#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.224.07:31:12.12#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.224.07:31:12.12#ibcon#about to clear, iclass 26 cls_cnt 0 2006.224.07:31:12.12#ibcon#cleared, iclass 26 cls_cnt 0 2006.224.07:31:12.12$vc4f8/vb=5,4 2006.224.07:31:12.12#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.224.07:31:12.12#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.224.07:31:12.12#ibcon#ireg 11 cls_cnt 2 2006.224.07:31:12.12#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.224.07:31:12.13#abcon#[5=S1D000X0/0*\r\n] 2006.224.07:31:12.18#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.224.07:31:12.18#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.224.07:31:12.18#ibcon#enter wrdev, iclass 29, count 2 2006.224.07:31:12.18#ibcon#first serial, iclass 29, count 2 2006.224.07:31:12.18#ibcon#enter sib2, iclass 29, count 2 2006.224.07:31:12.18#ibcon#flushed, iclass 29, count 2 2006.224.07:31:12.18#ibcon#about to write, iclass 29, count 2 2006.224.07:31:12.18#ibcon#wrote, iclass 29, count 2 2006.224.07:31:12.18#ibcon#about to read 3, iclass 29, count 2 2006.224.07:31:12.20#ibcon#read 3, iclass 29, count 2 2006.224.07:31:12.20#ibcon#about to read 4, iclass 29, count 2 2006.224.07:31:12.20#ibcon#read 4, iclass 29, count 2 2006.224.07:31:12.20#ibcon#about to read 5, iclass 29, count 2 2006.224.07:31:12.20#ibcon#read 5, iclass 29, count 2 2006.224.07:31:12.20#ibcon#about to read 6, iclass 29, count 2 2006.224.07:31:12.20#ibcon#read 6, iclass 29, count 2 2006.224.07:31:12.20#ibcon#end of sib2, iclass 29, count 2 2006.224.07:31:12.20#ibcon#*mode == 0, iclass 29, count 2 2006.224.07:31:12.20#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.224.07:31:12.20#ibcon#[27=AT05-04\r\n] 2006.224.07:31:12.20#ibcon#*before write, iclass 29, count 2 2006.224.07:31:12.20#ibcon#enter sib2, iclass 29, count 2 2006.224.07:31:12.20#ibcon#flushed, iclass 29, count 2 2006.224.07:31:12.20#ibcon#about to write, iclass 29, count 2 2006.224.07:31:12.20#ibcon#wrote, iclass 29, count 2 2006.224.07:31:12.20#ibcon#about to read 3, iclass 29, count 2 2006.224.07:31:12.23#ibcon#read 3, iclass 29, count 2 2006.224.07:31:12.23#ibcon#about to read 4, iclass 29, count 2 2006.224.07:31:12.23#ibcon#read 4, iclass 29, count 2 2006.224.07:31:12.23#ibcon#about to read 5, iclass 29, count 2 2006.224.07:31:12.23#ibcon#read 5, iclass 29, count 2 2006.224.07:31:12.23#ibcon#about to read 6, iclass 29, count 2 2006.224.07:31:12.23#ibcon#read 6, iclass 29, count 2 2006.224.07:31:12.23#ibcon#end of sib2, iclass 29, count 2 2006.224.07:31:12.23#ibcon#*after write, iclass 29, count 2 2006.224.07:31:12.23#ibcon#*before return 0, iclass 29, count 2 2006.224.07:31:12.23#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.224.07:31:12.23#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.224.07:31:12.23#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.224.07:31:12.23#ibcon#ireg 7 cls_cnt 0 2006.224.07:31:12.23#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.224.07:31:12.35#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.224.07:31:12.35#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.224.07:31:12.35#ibcon#enter wrdev, iclass 29, count 0 2006.224.07:31:12.35#ibcon#first serial, iclass 29, count 0 2006.224.07:31:12.35#ibcon#enter sib2, iclass 29, count 0 2006.224.07:31:12.35#ibcon#flushed, iclass 29, count 0 2006.224.07:31:12.35#ibcon#about to write, iclass 29, count 0 2006.224.07:31:12.35#ibcon#wrote, iclass 29, count 0 2006.224.07:31:12.35#ibcon#about to read 3, iclass 29, count 0 2006.224.07:31:12.37#ibcon#read 3, iclass 29, count 0 2006.224.07:31:12.37#ibcon#about to read 4, iclass 29, count 0 2006.224.07:31:12.37#ibcon#read 4, iclass 29, count 0 2006.224.07:31:12.37#ibcon#about to read 5, iclass 29, count 0 2006.224.07:31:12.37#ibcon#read 5, iclass 29, count 0 2006.224.07:31:12.37#ibcon#about to read 6, iclass 29, count 0 2006.224.07:31:12.37#ibcon#read 6, iclass 29, count 0 2006.224.07:31:12.37#ibcon#end of sib2, iclass 29, count 0 2006.224.07:31:12.37#ibcon#*mode == 0, iclass 29, count 0 2006.224.07:31:12.37#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.224.07:31:12.37#ibcon#[27=USB\r\n] 2006.224.07:31:12.37#ibcon#*before write, iclass 29, count 0 2006.224.07:31:12.37#ibcon#enter sib2, iclass 29, count 0 2006.224.07:31:12.37#ibcon#flushed, iclass 29, count 0 2006.224.07:31:12.37#ibcon#about to write, iclass 29, count 0 2006.224.07:31:12.37#ibcon#wrote, iclass 29, count 0 2006.224.07:31:12.37#ibcon#about to read 3, iclass 29, count 0 2006.224.07:31:12.40#ibcon#read 3, iclass 29, count 0 2006.224.07:31:12.40#ibcon#about to read 4, iclass 29, count 0 2006.224.07:31:12.40#ibcon#read 4, iclass 29, count 0 2006.224.07:31:12.40#ibcon#about to read 5, iclass 29, count 0 2006.224.07:31:12.40#ibcon#read 5, iclass 29, count 0 2006.224.07:31:12.40#ibcon#about to read 6, iclass 29, count 0 2006.224.07:31:12.40#ibcon#read 6, iclass 29, count 0 2006.224.07:31:12.40#ibcon#end of sib2, iclass 29, count 0 2006.224.07:31:12.40#ibcon#*after write, iclass 29, count 0 2006.224.07:31:12.40#ibcon#*before return 0, iclass 29, count 0 2006.224.07:31:12.40#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.224.07:31:12.40#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.224.07:31:12.40#ibcon#about to clear, iclass 29 cls_cnt 0 2006.224.07:31:12.40#ibcon#cleared, iclass 29 cls_cnt 0 2006.224.07:31:12.40$vc4f8/vblo=6,752.99 2006.224.07:31:12.40#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.224.07:31:12.40#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.224.07:31:12.40#ibcon#ireg 17 cls_cnt 0 2006.224.07:31:12.40#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.224.07:31:12.40#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.224.07:31:12.40#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.224.07:31:12.40#ibcon#enter wrdev, iclass 31, count 0 2006.224.07:31:12.40#ibcon#first serial, iclass 31, count 0 2006.224.07:31:12.40#ibcon#enter sib2, iclass 31, count 0 2006.224.07:31:12.40#ibcon#flushed, iclass 31, count 0 2006.224.07:31:12.40#ibcon#about to write, iclass 31, count 0 2006.224.07:31:12.40#ibcon#wrote, iclass 31, count 0 2006.224.07:31:12.40#ibcon#about to read 3, iclass 31, count 0 2006.224.07:31:12.42#ibcon#read 3, iclass 31, count 0 2006.224.07:31:12.42#ibcon#about to read 4, iclass 31, count 0 2006.224.07:31:12.42#ibcon#read 4, iclass 31, count 0 2006.224.07:31:12.42#ibcon#about to read 5, iclass 31, count 0 2006.224.07:31:12.42#ibcon#read 5, iclass 31, count 0 2006.224.07:31:12.42#ibcon#about to read 6, iclass 31, count 0 2006.224.07:31:12.42#ibcon#read 6, iclass 31, count 0 2006.224.07:31:12.42#ibcon#end of sib2, iclass 31, count 0 2006.224.07:31:12.42#ibcon#*mode == 0, iclass 31, count 0 2006.224.07:31:12.42#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.224.07:31:12.42#ibcon#[28=FRQ=06,752.99\r\n] 2006.224.07:31:12.42#ibcon#*before write, iclass 31, count 0 2006.224.07:31:12.42#ibcon#enter sib2, iclass 31, count 0 2006.224.07:31:12.42#ibcon#flushed, iclass 31, count 0 2006.224.07:31:12.42#ibcon#about to write, iclass 31, count 0 2006.224.07:31:12.42#ibcon#wrote, iclass 31, count 0 2006.224.07:31:12.42#ibcon#about to read 3, iclass 31, count 0 2006.224.07:31:12.46#ibcon#read 3, iclass 31, count 0 2006.224.07:31:12.46#ibcon#about to read 4, iclass 31, count 0 2006.224.07:31:12.46#ibcon#read 4, iclass 31, count 0 2006.224.07:31:12.46#ibcon#about to read 5, iclass 31, count 0 2006.224.07:31:12.46#ibcon#read 5, iclass 31, count 0 2006.224.07:31:12.46#ibcon#about to read 6, iclass 31, count 0 2006.224.07:31:12.46#ibcon#read 6, iclass 31, count 0 2006.224.07:31:12.46#ibcon#end of sib2, iclass 31, count 0 2006.224.07:31:12.46#ibcon#*after write, iclass 31, count 0 2006.224.07:31:12.46#ibcon#*before return 0, iclass 31, count 0 2006.224.07:31:12.46#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.224.07:31:12.46#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.224.07:31:12.46#ibcon#about to clear, iclass 31 cls_cnt 0 2006.224.07:31:12.46#ibcon#cleared, iclass 31 cls_cnt 0 2006.224.07:31:12.46$vc4f8/vb=6,4 2006.224.07:31:12.46#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.224.07:31:12.46#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.224.07:31:12.46#ibcon#ireg 11 cls_cnt 2 2006.224.07:31:12.46#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.224.07:31:12.52#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.224.07:31:12.52#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.224.07:31:12.52#ibcon#enter wrdev, iclass 33, count 2 2006.224.07:31:12.52#ibcon#first serial, iclass 33, count 2 2006.224.07:31:12.52#ibcon#enter sib2, iclass 33, count 2 2006.224.07:31:12.52#ibcon#flushed, iclass 33, count 2 2006.224.07:31:12.52#ibcon#about to write, iclass 33, count 2 2006.224.07:31:12.52#ibcon#wrote, iclass 33, count 2 2006.224.07:31:12.52#ibcon#about to read 3, iclass 33, count 2 2006.224.07:31:12.54#ibcon#read 3, iclass 33, count 2 2006.224.07:31:12.54#ibcon#about to read 4, iclass 33, count 2 2006.224.07:31:12.54#ibcon#read 4, iclass 33, count 2 2006.224.07:31:12.54#ibcon#about to read 5, iclass 33, count 2 2006.224.07:31:12.54#ibcon#read 5, iclass 33, count 2 2006.224.07:31:12.54#ibcon#about to read 6, iclass 33, count 2 2006.224.07:31:12.54#ibcon#read 6, iclass 33, count 2 2006.224.07:31:12.54#ibcon#end of sib2, iclass 33, count 2 2006.224.07:31:12.54#ibcon#*mode == 0, iclass 33, count 2 2006.224.07:31:12.54#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.224.07:31:12.54#ibcon#[27=AT06-04\r\n] 2006.224.07:31:12.54#ibcon#*before write, iclass 33, count 2 2006.224.07:31:12.54#ibcon#enter sib2, iclass 33, count 2 2006.224.07:31:12.54#ibcon#flushed, iclass 33, count 2 2006.224.07:31:12.54#ibcon#about to write, iclass 33, count 2 2006.224.07:31:12.54#ibcon#wrote, iclass 33, count 2 2006.224.07:31:12.54#ibcon#about to read 3, iclass 33, count 2 2006.224.07:31:12.57#ibcon#read 3, iclass 33, count 2 2006.224.07:31:12.57#ibcon#about to read 4, iclass 33, count 2 2006.224.07:31:12.57#ibcon#read 4, iclass 33, count 2 2006.224.07:31:12.57#ibcon#about to read 5, iclass 33, count 2 2006.224.07:31:12.57#ibcon#read 5, iclass 33, count 2 2006.224.07:31:12.57#ibcon#about to read 6, iclass 33, count 2 2006.224.07:31:12.57#ibcon#read 6, iclass 33, count 2 2006.224.07:31:12.57#ibcon#end of sib2, iclass 33, count 2 2006.224.07:31:12.57#ibcon#*after write, iclass 33, count 2 2006.224.07:31:12.57#ibcon#*before return 0, iclass 33, count 2 2006.224.07:31:12.57#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.224.07:31:12.57#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.224.07:31:12.57#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.224.07:31:12.57#ibcon#ireg 7 cls_cnt 0 2006.224.07:31:12.57#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.224.07:31:12.69#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.224.07:31:12.69#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.224.07:31:12.69#ibcon#enter wrdev, iclass 33, count 0 2006.224.07:31:12.69#ibcon#first serial, iclass 33, count 0 2006.224.07:31:12.69#ibcon#enter sib2, iclass 33, count 0 2006.224.07:31:12.69#ibcon#flushed, iclass 33, count 0 2006.224.07:31:12.69#ibcon#about to write, iclass 33, count 0 2006.224.07:31:12.69#ibcon#wrote, iclass 33, count 0 2006.224.07:31:12.69#ibcon#about to read 3, iclass 33, count 0 2006.224.07:31:12.71#ibcon#read 3, iclass 33, count 0 2006.224.07:31:12.71#ibcon#about to read 4, iclass 33, count 0 2006.224.07:31:12.71#ibcon#read 4, iclass 33, count 0 2006.224.07:31:12.71#ibcon#about to read 5, iclass 33, count 0 2006.224.07:31:12.71#ibcon#read 5, iclass 33, count 0 2006.224.07:31:12.71#ibcon#about to read 6, iclass 33, count 0 2006.224.07:31:12.71#ibcon#read 6, iclass 33, count 0 2006.224.07:31:12.71#ibcon#end of sib2, iclass 33, count 0 2006.224.07:31:12.71#ibcon#*mode == 0, iclass 33, count 0 2006.224.07:31:12.71#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.224.07:31:12.71#ibcon#[27=USB\r\n] 2006.224.07:31:12.71#ibcon#*before write, iclass 33, count 0 2006.224.07:31:12.71#ibcon#enter sib2, iclass 33, count 0 2006.224.07:31:12.71#ibcon#flushed, iclass 33, count 0 2006.224.07:31:12.71#ibcon#about to write, iclass 33, count 0 2006.224.07:31:12.71#ibcon#wrote, iclass 33, count 0 2006.224.07:31:12.71#ibcon#about to read 3, iclass 33, count 0 2006.224.07:31:12.74#ibcon#read 3, iclass 33, count 0 2006.224.07:31:12.74#ibcon#about to read 4, iclass 33, count 0 2006.224.07:31:12.74#ibcon#read 4, iclass 33, count 0 2006.224.07:31:12.74#ibcon#about to read 5, iclass 33, count 0 2006.224.07:31:12.74#ibcon#read 5, iclass 33, count 0 2006.224.07:31:12.74#ibcon#about to read 6, iclass 33, count 0 2006.224.07:31:12.74#ibcon#read 6, iclass 33, count 0 2006.224.07:31:12.74#ibcon#end of sib2, iclass 33, count 0 2006.224.07:31:12.74#ibcon#*after write, iclass 33, count 0 2006.224.07:31:12.74#ibcon#*before return 0, iclass 33, count 0 2006.224.07:31:12.74#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.224.07:31:12.74#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.224.07:31:12.74#ibcon#about to clear, iclass 33 cls_cnt 0 2006.224.07:31:12.74#ibcon#cleared, iclass 33 cls_cnt 0 2006.224.07:31:12.74$vc4f8/vabw=wide 2006.224.07:31:12.74#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.224.07:31:12.74#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.224.07:31:12.74#ibcon#ireg 8 cls_cnt 0 2006.224.07:31:12.74#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.224.07:31:12.74#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.224.07:31:12.74#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.224.07:31:12.74#ibcon#enter wrdev, iclass 35, count 0 2006.224.07:31:12.74#ibcon#first serial, iclass 35, count 0 2006.224.07:31:12.74#ibcon#enter sib2, iclass 35, count 0 2006.224.07:31:12.74#ibcon#flushed, iclass 35, count 0 2006.224.07:31:12.74#ibcon#about to write, iclass 35, count 0 2006.224.07:31:12.74#ibcon#wrote, iclass 35, count 0 2006.224.07:31:12.74#ibcon#about to read 3, iclass 35, count 0 2006.224.07:31:12.76#ibcon#read 3, iclass 35, count 0 2006.224.07:31:12.76#ibcon#about to read 4, iclass 35, count 0 2006.224.07:31:12.76#ibcon#read 4, iclass 35, count 0 2006.224.07:31:12.76#ibcon#about to read 5, iclass 35, count 0 2006.224.07:31:12.76#ibcon#read 5, iclass 35, count 0 2006.224.07:31:12.76#ibcon#about to read 6, iclass 35, count 0 2006.224.07:31:12.76#ibcon#read 6, iclass 35, count 0 2006.224.07:31:12.76#ibcon#end of sib2, iclass 35, count 0 2006.224.07:31:12.76#ibcon#*mode == 0, iclass 35, count 0 2006.224.07:31:12.76#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.224.07:31:12.76#ibcon#[25=BW32\r\n] 2006.224.07:31:12.76#ibcon#*before write, iclass 35, count 0 2006.224.07:31:12.76#ibcon#enter sib2, iclass 35, count 0 2006.224.07:31:12.76#ibcon#flushed, iclass 35, count 0 2006.224.07:31:12.76#ibcon#about to write, iclass 35, count 0 2006.224.07:31:12.76#ibcon#wrote, iclass 35, count 0 2006.224.07:31:12.76#ibcon#about to read 3, iclass 35, count 0 2006.224.07:31:12.79#ibcon#read 3, iclass 35, count 0 2006.224.07:31:12.79#ibcon#about to read 4, iclass 35, count 0 2006.224.07:31:12.79#ibcon#read 4, iclass 35, count 0 2006.224.07:31:12.79#ibcon#about to read 5, iclass 35, count 0 2006.224.07:31:12.79#ibcon#read 5, iclass 35, count 0 2006.224.07:31:12.79#ibcon#about to read 6, iclass 35, count 0 2006.224.07:31:12.79#ibcon#read 6, iclass 35, count 0 2006.224.07:31:12.79#ibcon#end of sib2, iclass 35, count 0 2006.224.07:31:12.79#ibcon#*after write, iclass 35, count 0 2006.224.07:31:12.79#ibcon#*before return 0, iclass 35, count 0 2006.224.07:31:12.79#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.224.07:31:12.79#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.224.07:31:12.79#ibcon#about to clear, iclass 35 cls_cnt 0 2006.224.07:31:12.79#ibcon#cleared, iclass 35 cls_cnt 0 2006.224.07:31:12.79$vc4f8/vbbw=wide 2006.224.07:31:12.79#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.224.07:31:12.79#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.224.07:31:12.79#ibcon#ireg 8 cls_cnt 0 2006.224.07:31:12.79#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.224.07:31:12.86#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.224.07:31:12.86#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.224.07:31:12.86#ibcon#enter wrdev, iclass 37, count 0 2006.224.07:31:12.86#ibcon#first serial, iclass 37, count 0 2006.224.07:31:12.86#ibcon#enter sib2, iclass 37, count 0 2006.224.07:31:12.86#ibcon#flushed, iclass 37, count 0 2006.224.07:31:12.86#ibcon#about to write, iclass 37, count 0 2006.224.07:31:12.86#ibcon#wrote, iclass 37, count 0 2006.224.07:31:12.86#ibcon#about to read 3, iclass 37, count 0 2006.224.07:31:12.88#ibcon#read 3, iclass 37, count 0 2006.224.07:31:12.88#ibcon#about to read 4, iclass 37, count 0 2006.224.07:31:12.88#ibcon#read 4, iclass 37, count 0 2006.224.07:31:12.88#ibcon#about to read 5, iclass 37, count 0 2006.224.07:31:12.88#ibcon#read 5, iclass 37, count 0 2006.224.07:31:12.88#ibcon#about to read 6, iclass 37, count 0 2006.224.07:31:12.88#ibcon#read 6, iclass 37, count 0 2006.224.07:31:12.88#ibcon#end of sib2, iclass 37, count 0 2006.224.07:31:12.88#ibcon#*mode == 0, iclass 37, count 0 2006.224.07:31:12.88#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.224.07:31:12.88#ibcon#[27=BW32\r\n] 2006.224.07:31:12.88#ibcon#*before write, iclass 37, count 0 2006.224.07:31:12.88#ibcon#enter sib2, iclass 37, count 0 2006.224.07:31:12.88#ibcon#flushed, iclass 37, count 0 2006.224.07:31:12.88#ibcon#about to write, iclass 37, count 0 2006.224.07:31:12.88#ibcon#wrote, iclass 37, count 0 2006.224.07:31:12.88#ibcon#about to read 3, iclass 37, count 0 2006.224.07:31:12.91#ibcon#read 3, iclass 37, count 0 2006.224.07:31:12.91#ibcon#about to read 4, iclass 37, count 0 2006.224.07:31:12.91#ibcon#read 4, iclass 37, count 0 2006.224.07:31:12.91#ibcon#about to read 5, iclass 37, count 0 2006.224.07:31:12.91#ibcon#read 5, iclass 37, count 0 2006.224.07:31:12.91#ibcon#about to read 6, iclass 37, count 0 2006.224.07:31:12.91#ibcon#read 6, iclass 37, count 0 2006.224.07:31:12.91#ibcon#end of sib2, iclass 37, count 0 2006.224.07:31:12.91#ibcon#*after write, iclass 37, count 0 2006.224.07:31:12.91#ibcon#*before return 0, iclass 37, count 0 2006.224.07:31:12.91#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.224.07:31:12.91#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.224.07:31:12.91#ibcon#about to clear, iclass 37 cls_cnt 0 2006.224.07:31:12.91#ibcon#cleared, iclass 37 cls_cnt 0 2006.224.07:31:12.91$4f8m12a/ifd4f 2006.224.07:31:12.91$ifd4f/lo= 2006.224.07:31:12.91$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.224.07:31:12.91$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.224.07:31:12.91$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.224.07:31:12.91$ifd4f/patch= 2006.224.07:31:12.91$ifd4f/patch=lo1,a1,a2,a3,a4 2006.224.07:31:12.91$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.224.07:31:12.91$ifd4f/patch=lo3,a5,a6,a7,a8 2006.224.07:31:12.91$4f8m12a/"form=m,16.000,1:2 2006.224.07:31:12.91$4f8m12a/"tpicd 2006.224.07:31:12.91$4f8m12a/echo=off 2006.224.07:31:12.91$4f8m12a/xlog=off 2006.224.07:31:12.91:!2006.224.07:33:20 2006.224.07:31:47.14#trakl#Source acquired 2006.224.07:31:49.14#flagr#flagr/antenna,acquired 2006.224.07:33:20.00:preob 2006.224.07:33:20.14/onsource/TRACKING 2006.224.07:33:20.14:!2006.224.07:33:30 2006.224.07:33:30.00:data_valid=on 2006.224.07:33:30.00:midob 2006.224.07:33:31.14/onsource/TRACKING 2006.224.07:33:31.14/wx/23.36,1004.1,100 2006.224.07:33:31.26/cable/+6.4320E-03 2006.224.07:33:32.35/va/01,08,usb,yes,48,50 2006.224.07:33:32.35/va/02,07,usb,yes,48,51 2006.224.07:33:32.35/va/03,06,usb,yes,52,52 2006.224.07:33:32.35/va/04,07,usb,yes,51,55 2006.224.07:33:32.35/va/05,07,usb,yes,60,63 2006.224.07:33:32.35/va/06,06,usb,yes,60,59 2006.224.07:33:32.35/va/07,06,usb,yes,60,60 2006.224.07:33:32.35/va/08,07,usb,yes,58,57 2006.224.07:33:32.58/valo/01,532.99,yes,locked 2006.224.07:33:32.58/valo/02,572.99,yes,locked 2006.224.07:33:32.58/valo/03,672.99,yes,locked 2006.224.07:33:32.58/valo/04,832.99,yes,locked 2006.224.07:33:32.58/valo/05,652.99,yes,locked 2006.224.07:33:32.58/valo/06,772.99,yes,locked 2006.224.07:33:32.58/valo/07,832.99,yes,locked 2006.224.07:33:32.58/valo/08,852.99,yes,locked 2006.224.07:33:33.67/vb/01,04,usb,yes,35,34 2006.224.07:33:33.67/vb/02,04,usb,yes,37,39 2006.224.07:33:33.67/vb/03,04,usb,yes,33,38 2006.224.07:33:33.67/vb/04,04,usb,yes,34,35 2006.224.07:33:33.67/vb/05,04,usb,yes,33,37 2006.224.07:33:33.67/vb/06,04,usb,yes,34,37 2006.224.07:33:33.67/vb/07,04,usb,yes,36,36 2006.224.07:33:33.67/vb/08,04,usb,yes,33,37 2006.224.07:33:33.90/vblo/01,632.99,yes,locked 2006.224.07:33:33.90/vblo/02,640.99,yes,locked 2006.224.07:33:33.90/vblo/03,656.99,yes,locked 2006.224.07:33:33.90/vblo/04,712.99,yes,locked 2006.224.07:33:33.90/vblo/05,744.99,yes,locked 2006.224.07:33:33.90/vblo/06,752.99,yes,locked 2006.224.07:33:33.90/vblo/07,734.99,yes,locked 2006.224.07:33:33.90/vblo/08,744.99,yes,locked 2006.224.07:33:34.05/vabw/8 2006.224.07:33:34.20/vbbw/8 2006.224.07:33:34.31/xfe/off,on,15.0 2006.224.07:33:34.69/ifatt/23,28,28,28 2006.224.07:33:35.08/fmout-gps/S +4.40E-07 2006.224.07:33:35.12:!2006.224.07:34:30 2006.224.07:34:30.00:data_valid=off 2006.224.07:34:30.00:postob 2006.224.07:34:30.10/cable/+6.4336E-03 2006.224.07:34:30.10/wx/23.36,1004.1,100 2006.224.07:34:31.08/fmout-gps/S +4.40E-07 2006.224.07:34:31.08:scan_name=224-0735,k06224,60 2006.224.07:34:31.08:source=0955+476,095819.67,472507.8,2000.0,ccw 2006.224.07:34:31.14#flagr#flagr/antenna,new-source 2006.224.07:34:32.14:checkk5 2006.224.07:34:32.51/chk_autoobs//k5ts1/ autoobs is running! 2006.224.07:34:32.88/chk_autoobs//k5ts2/ autoobs is running! 2006.224.07:34:33.24/chk_autoobs//k5ts3/ autoobs is running! 2006.224.07:34:33.62/chk_autoobs//k5ts4/ autoobs is running! 2006.224.07:34:33.98/chk_obsdata//k5ts1/T2240733??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.07:34:34.35/chk_obsdata//k5ts2/T2240733??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.07:34:34.72/chk_obsdata//k5ts3/T2240733??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.07:34:35.09/chk_obsdata//k5ts4/T2240733??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.07:34:35.77/k5log//k5ts1_log_newline 2006.224.07:34:36.46/k5log//k5ts2_log_newline 2006.224.07:34:37.14/k5log//k5ts3_log_newline 2006.224.07:34:37.82/k5log//k5ts4_log_newline 2006.224.07:34:37.85/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.224.07:34:37.85:4f8m12a=1 2006.224.07:34:37.85$4f8m12a/echo=on 2006.224.07:34:37.85$4f8m12a/pcalon 2006.224.07:34:37.85$pcalon/"no phase cal control is implemented here 2006.224.07:34:37.85$4f8m12a/"tpicd=stop 2006.224.07:34:37.85$4f8m12a/vc4f8 2006.224.07:34:37.85$vc4f8/valo=1,532.99 2006.224.07:34:37.85#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.224.07:34:37.85#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.224.07:34:37.85#ibcon#ireg 17 cls_cnt 0 2006.224.07:34:37.85#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.224.07:34:37.85#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.224.07:34:37.85#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.224.07:34:37.85#ibcon#enter wrdev, iclass 12, count 0 2006.224.07:34:37.85#ibcon#first serial, iclass 12, count 0 2006.224.07:34:37.85#ibcon#enter sib2, iclass 12, count 0 2006.224.07:34:37.85#ibcon#flushed, iclass 12, count 0 2006.224.07:34:37.85#ibcon#about to write, iclass 12, count 0 2006.224.07:34:37.85#ibcon#wrote, iclass 12, count 0 2006.224.07:34:37.85#ibcon#about to read 3, iclass 12, count 0 2006.224.07:34:37.87#ibcon#read 3, iclass 12, count 0 2006.224.07:34:37.87#ibcon#about to read 4, iclass 12, count 0 2006.224.07:34:37.87#ibcon#read 4, iclass 12, count 0 2006.224.07:34:37.87#ibcon#about to read 5, iclass 12, count 0 2006.224.07:34:37.87#ibcon#read 5, iclass 12, count 0 2006.224.07:34:37.87#ibcon#about to read 6, iclass 12, count 0 2006.224.07:34:37.87#ibcon#read 6, iclass 12, count 0 2006.224.07:34:37.87#ibcon#end of sib2, iclass 12, count 0 2006.224.07:34:37.87#ibcon#*mode == 0, iclass 12, count 0 2006.224.07:34:37.87#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.224.07:34:37.87#ibcon#[26=FRQ=01,532.99\r\n] 2006.224.07:34:37.87#ibcon#*before write, iclass 12, count 0 2006.224.07:34:37.87#ibcon#enter sib2, iclass 12, count 0 2006.224.07:34:37.87#ibcon#flushed, iclass 12, count 0 2006.224.07:34:37.87#ibcon#about to write, iclass 12, count 0 2006.224.07:34:37.87#ibcon#wrote, iclass 12, count 0 2006.224.07:34:37.87#ibcon#about to read 3, iclass 12, count 0 2006.224.07:34:37.92#ibcon#read 3, iclass 12, count 0 2006.224.07:34:37.92#ibcon#about to read 4, iclass 12, count 0 2006.224.07:34:37.92#ibcon#read 4, iclass 12, count 0 2006.224.07:34:37.92#ibcon#about to read 5, iclass 12, count 0 2006.224.07:34:37.92#ibcon#read 5, iclass 12, count 0 2006.224.07:34:37.92#ibcon#about to read 6, iclass 12, count 0 2006.224.07:34:37.92#ibcon#read 6, iclass 12, count 0 2006.224.07:34:37.92#ibcon#end of sib2, iclass 12, count 0 2006.224.07:34:37.92#ibcon#*after write, iclass 12, count 0 2006.224.07:34:37.92#ibcon#*before return 0, iclass 12, count 0 2006.224.07:34:37.92#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.224.07:34:37.92#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.224.07:34:37.92#ibcon#about to clear, iclass 12 cls_cnt 0 2006.224.07:34:37.92#ibcon#cleared, iclass 12 cls_cnt 0 2006.224.07:34:37.92$vc4f8/va=1,8 2006.224.07:34:37.92#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.224.07:34:37.92#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.224.07:34:37.92#ibcon#ireg 11 cls_cnt 2 2006.224.07:34:37.92#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.224.07:34:37.92#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.224.07:34:37.92#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.224.07:34:37.92#ibcon#enter wrdev, iclass 14, count 2 2006.224.07:34:37.92#ibcon#first serial, iclass 14, count 2 2006.224.07:34:37.92#ibcon#enter sib2, iclass 14, count 2 2006.224.07:34:37.92#ibcon#flushed, iclass 14, count 2 2006.224.07:34:37.92#ibcon#about to write, iclass 14, count 2 2006.224.07:34:37.92#ibcon#wrote, iclass 14, count 2 2006.224.07:34:37.92#ibcon#about to read 3, iclass 14, count 2 2006.224.07:34:37.94#ibcon#read 3, iclass 14, count 2 2006.224.07:34:37.94#ibcon#about to read 4, iclass 14, count 2 2006.224.07:34:37.94#ibcon#read 4, iclass 14, count 2 2006.224.07:34:37.94#ibcon#about to read 5, iclass 14, count 2 2006.224.07:34:37.94#ibcon#read 5, iclass 14, count 2 2006.224.07:34:37.94#ibcon#about to read 6, iclass 14, count 2 2006.224.07:34:37.94#ibcon#read 6, iclass 14, count 2 2006.224.07:34:37.94#ibcon#end of sib2, iclass 14, count 2 2006.224.07:34:37.94#ibcon#*mode == 0, iclass 14, count 2 2006.224.07:34:37.94#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.224.07:34:37.94#ibcon#[25=AT01-08\r\n] 2006.224.07:34:37.94#ibcon#*before write, iclass 14, count 2 2006.224.07:34:37.94#ibcon#enter sib2, iclass 14, count 2 2006.224.07:34:37.94#ibcon#flushed, iclass 14, count 2 2006.224.07:34:37.94#ibcon#about to write, iclass 14, count 2 2006.224.07:34:37.94#ibcon#wrote, iclass 14, count 2 2006.224.07:34:37.94#ibcon#about to read 3, iclass 14, count 2 2006.224.07:34:37.97#ibcon#read 3, iclass 14, count 2 2006.224.07:34:37.97#ibcon#about to read 4, iclass 14, count 2 2006.224.07:34:37.97#ibcon#read 4, iclass 14, count 2 2006.224.07:34:37.97#ibcon#about to read 5, iclass 14, count 2 2006.224.07:34:37.97#ibcon#read 5, iclass 14, count 2 2006.224.07:34:37.97#ibcon#about to read 6, iclass 14, count 2 2006.224.07:34:37.97#ibcon#read 6, iclass 14, count 2 2006.224.07:34:37.97#ibcon#end of sib2, iclass 14, count 2 2006.224.07:34:37.97#ibcon#*after write, iclass 14, count 2 2006.224.07:34:37.97#ibcon#*before return 0, iclass 14, count 2 2006.224.07:34:37.97#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.224.07:34:37.97#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.224.07:34:37.97#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.224.07:34:37.97#ibcon#ireg 7 cls_cnt 0 2006.224.07:34:37.97#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.224.07:34:38.09#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.224.07:34:38.09#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.224.07:34:38.09#ibcon#enter wrdev, iclass 14, count 0 2006.224.07:34:38.09#ibcon#first serial, iclass 14, count 0 2006.224.07:34:38.09#ibcon#enter sib2, iclass 14, count 0 2006.224.07:34:38.09#ibcon#flushed, iclass 14, count 0 2006.224.07:34:38.09#ibcon#about to write, iclass 14, count 0 2006.224.07:34:38.09#ibcon#wrote, iclass 14, count 0 2006.224.07:34:38.09#ibcon#about to read 3, iclass 14, count 0 2006.224.07:34:38.11#ibcon#read 3, iclass 14, count 0 2006.224.07:34:38.11#ibcon#about to read 4, iclass 14, count 0 2006.224.07:34:38.11#ibcon#read 4, iclass 14, count 0 2006.224.07:34:38.11#ibcon#about to read 5, iclass 14, count 0 2006.224.07:34:38.11#ibcon#read 5, iclass 14, count 0 2006.224.07:34:38.11#ibcon#about to read 6, iclass 14, count 0 2006.224.07:34:38.11#ibcon#read 6, iclass 14, count 0 2006.224.07:34:38.11#ibcon#end of sib2, iclass 14, count 0 2006.224.07:34:38.11#ibcon#*mode == 0, iclass 14, count 0 2006.224.07:34:38.11#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.224.07:34:38.11#ibcon#[25=USB\r\n] 2006.224.07:34:38.11#ibcon#*before write, iclass 14, count 0 2006.224.07:34:38.11#ibcon#enter sib2, iclass 14, count 0 2006.224.07:34:38.11#ibcon#flushed, iclass 14, count 0 2006.224.07:34:38.11#ibcon#about to write, iclass 14, count 0 2006.224.07:34:38.11#ibcon#wrote, iclass 14, count 0 2006.224.07:34:38.11#ibcon#about to read 3, iclass 14, count 0 2006.224.07:34:38.14#ibcon#read 3, iclass 14, count 0 2006.224.07:34:38.14#ibcon#about to read 4, iclass 14, count 0 2006.224.07:34:38.14#ibcon#read 4, iclass 14, count 0 2006.224.07:34:38.14#ibcon#about to read 5, iclass 14, count 0 2006.224.07:34:38.14#ibcon#read 5, iclass 14, count 0 2006.224.07:34:38.14#ibcon#about to read 6, iclass 14, count 0 2006.224.07:34:38.14#ibcon#read 6, iclass 14, count 0 2006.224.07:34:38.14#ibcon#end of sib2, iclass 14, count 0 2006.224.07:34:38.14#ibcon#*after write, iclass 14, count 0 2006.224.07:34:38.14#ibcon#*before return 0, iclass 14, count 0 2006.224.07:34:38.14#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.224.07:34:38.14#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.224.07:34:38.14#ibcon#about to clear, iclass 14 cls_cnt 0 2006.224.07:34:38.14#ibcon#cleared, iclass 14 cls_cnt 0 2006.224.07:34:38.14$vc4f8/valo=2,572.99 2006.224.07:34:38.14#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.224.07:34:38.14#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.224.07:34:38.14#ibcon#ireg 17 cls_cnt 0 2006.224.07:34:38.14#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.224.07:34:38.14#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.224.07:34:38.14#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.224.07:34:38.14#ibcon#enter wrdev, iclass 16, count 0 2006.224.07:34:38.14#ibcon#first serial, iclass 16, count 0 2006.224.07:34:38.14#ibcon#enter sib2, iclass 16, count 0 2006.224.07:34:38.14#ibcon#flushed, iclass 16, count 0 2006.224.07:34:38.14#ibcon#about to write, iclass 16, count 0 2006.224.07:34:38.14#ibcon#wrote, iclass 16, count 0 2006.224.07:34:38.14#ibcon#about to read 3, iclass 16, count 0 2006.224.07:34:38.16#ibcon#read 3, iclass 16, count 0 2006.224.07:34:38.16#ibcon#about to read 4, iclass 16, count 0 2006.224.07:34:38.16#ibcon#read 4, iclass 16, count 0 2006.224.07:34:38.16#ibcon#about to read 5, iclass 16, count 0 2006.224.07:34:38.16#ibcon#read 5, iclass 16, count 0 2006.224.07:34:38.16#ibcon#about to read 6, iclass 16, count 0 2006.224.07:34:38.16#ibcon#read 6, iclass 16, count 0 2006.224.07:34:38.16#ibcon#end of sib2, iclass 16, count 0 2006.224.07:34:38.16#ibcon#*mode == 0, iclass 16, count 0 2006.224.07:34:38.16#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.224.07:34:38.16#ibcon#[26=FRQ=02,572.99\r\n] 2006.224.07:34:38.16#ibcon#*before write, iclass 16, count 0 2006.224.07:34:38.16#ibcon#enter sib2, iclass 16, count 0 2006.224.07:34:38.16#ibcon#flushed, iclass 16, count 0 2006.224.07:34:38.16#ibcon#about to write, iclass 16, count 0 2006.224.07:34:38.16#ibcon#wrote, iclass 16, count 0 2006.224.07:34:38.16#ibcon#about to read 3, iclass 16, count 0 2006.224.07:34:38.21#ibcon#read 3, iclass 16, count 0 2006.224.07:34:38.21#ibcon#about to read 4, iclass 16, count 0 2006.224.07:34:38.21#ibcon#read 4, iclass 16, count 0 2006.224.07:34:38.21#ibcon#about to read 5, iclass 16, count 0 2006.224.07:34:38.21#ibcon#read 5, iclass 16, count 0 2006.224.07:34:38.21#ibcon#about to read 6, iclass 16, count 0 2006.224.07:34:38.21#ibcon#read 6, iclass 16, count 0 2006.224.07:34:38.21#ibcon#end of sib2, iclass 16, count 0 2006.224.07:34:38.21#ibcon#*after write, iclass 16, count 0 2006.224.07:34:38.21#ibcon#*before return 0, iclass 16, count 0 2006.224.07:34:38.21#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.224.07:34:38.21#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.224.07:34:38.21#ibcon#about to clear, iclass 16 cls_cnt 0 2006.224.07:34:38.21#ibcon#cleared, iclass 16 cls_cnt 0 2006.224.07:34:38.21$vc4f8/va=2,7 2006.224.07:34:38.21#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.224.07:34:38.21#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.224.07:34:38.21#ibcon#ireg 11 cls_cnt 2 2006.224.07:34:38.21#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.224.07:34:38.26#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.224.07:34:38.26#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.224.07:34:38.26#ibcon#enter wrdev, iclass 18, count 2 2006.224.07:34:38.26#ibcon#first serial, iclass 18, count 2 2006.224.07:34:38.26#ibcon#enter sib2, iclass 18, count 2 2006.224.07:34:38.26#ibcon#flushed, iclass 18, count 2 2006.224.07:34:38.26#ibcon#about to write, iclass 18, count 2 2006.224.07:34:38.26#ibcon#wrote, iclass 18, count 2 2006.224.07:34:38.26#ibcon#about to read 3, iclass 18, count 2 2006.224.07:34:38.28#ibcon#read 3, iclass 18, count 2 2006.224.07:34:38.28#ibcon#about to read 4, iclass 18, count 2 2006.224.07:34:38.28#ibcon#read 4, iclass 18, count 2 2006.224.07:34:38.28#ibcon#about to read 5, iclass 18, count 2 2006.224.07:34:38.28#ibcon#read 5, iclass 18, count 2 2006.224.07:34:38.28#ibcon#about to read 6, iclass 18, count 2 2006.224.07:34:38.28#ibcon#read 6, iclass 18, count 2 2006.224.07:34:38.28#ibcon#end of sib2, iclass 18, count 2 2006.224.07:34:38.28#ibcon#*mode == 0, iclass 18, count 2 2006.224.07:34:38.28#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.224.07:34:38.28#ibcon#[25=AT02-07\r\n] 2006.224.07:34:38.28#ibcon#*before write, iclass 18, count 2 2006.224.07:34:38.28#ibcon#enter sib2, iclass 18, count 2 2006.224.07:34:38.28#ibcon#flushed, iclass 18, count 2 2006.224.07:34:38.28#ibcon#about to write, iclass 18, count 2 2006.224.07:34:38.28#ibcon#wrote, iclass 18, count 2 2006.224.07:34:38.28#ibcon#about to read 3, iclass 18, count 2 2006.224.07:34:38.31#ibcon#read 3, iclass 18, count 2 2006.224.07:34:38.31#ibcon#about to read 4, iclass 18, count 2 2006.224.07:34:38.31#ibcon#read 4, iclass 18, count 2 2006.224.07:34:38.31#ibcon#about to read 5, iclass 18, count 2 2006.224.07:34:38.31#ibcon#read 5, iclass 18, count 2 2006.224.07:34:38.31#ibcon#about to read 6, iclass 18, count 2 2006.224.07:34:38.31#ibcon#read 6, iclass 18, count 2 2006.224.07:34:38.31#ibcon#end of sib2, iclass 18, count 2 2006.224.07:34:38.31#ibcon#*after write, iclass 18, count 2 2006.224.07:34:38.31#ibcon#*before return 0, iclass 18, count 2 2006.224.07:34:38.31#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.224.07:34:38.31#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.224.07:34:38.31#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.224.07:34:38.31#ibcon#ireg 7 cls_cnt 0 2006.224.07:34:38.31#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.224.07:34:38.43#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.224.07:34:38.43#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.224.07:34:38.43#ibcon#enter wrdev, iclass 18, count 0 2006.224.07:34:38.43#ibcon#first serial, iclass 18, count 0 2006.224.07:34:38.43#ibcon#enter sib2, iclass 18, count 0 2006.224.07:34:38.43#ibcon#flushed, iclass 18, count 0 2006.224.07:34:38.43#ibcon#about to write, iclass 18, count 0 2006.224.07:34:38.43#ibcon#wrote, iclass 18, count 0 2006.224.07:34:38.43#ibcon#about to read 3, iclass 18, count 0 2006.224.07:34:38.45#ibcon#read 3, iclass 18, count 0 2006.224.07:34:38.45#ibcon#about to read 4, iclass 18, count 0 2006.224.07:34:38.45#ibcon#read 4, iclass 18, count 0 2006.224.07:34:38.45#ibcon#about to read 5, iclass 18, count 0 2006.224.07:34:38.45#ibcon#read 5, iclass 18, count 0 2006.224.07:34:38.45#ibcon#about to read 6, iclass 18, count 0 2006.224.07:34:38.45#ibcon#read 6, iclass 18, count 0 2006.224.07:34:38.45#ibcon#end of sib2, iclass 18, count 0 2006.224.07:34:38.45#ibcon#*mode == 0, iclass 18, count 0 2006.224.07:34:38.45#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.224.07:34:38.45#ibcon#[25=USB\r\n] 2006.224.07:34:38.45#ibcon#*before write, iclass 18, count 0 2006.224.07:34:38.45#ibcon#enter sib2, iclass 18, count 0 2006.224.07:34:38.45#ibcon#flushed, iclass 18, count 0 2006.224.07:34:38.45#ibcon#about to write, iclass 18, count 0 2006.224.07:34:38.45#ibcon#wrote, iclass 18, count 0 2006.224.07:34:38.45#ibcon#about to read 3, iclass 18, count 0 2006.224.07:34:38.48#ibcon#read 3, iclass 18, count 0 2006.224.07:34:38.48#ibcon#about to read 4, iclass 18, count 0 2006.224.07:34:38.48#ibcon#read 4, iclass 18, count 0 2006.224.07:34:38.48#ibcon#about to read 5, iclass 18, count 0 2006.224.07:34:38.48#ibcon#read 5, iclass 18, count 0 2006.224.07:34:38.48#ibcon#about to read 6, iclass 18, count 0 2006.224.07:34:38.48#ibcon#read 6, iclass 18, count 0 2006.224.07:34:38.48#ibcon#end of sib2, iclass 18, count 0 2006.224.07:34:38.48#ibcon#*after write, iclass 18, count 0 2006.224.07:34:38.48#ibcon#*before return 0, iclass 18, count 0 2006.224.07:34:38.48#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.224.07:34:38.48#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.224.07:34:38.48#ibcon#about to clear, iclass 18 cls_cnt 0 2006.224.07:34:38.48#ibcon#cleared, iclass 18 cls_cnt 0 2006.224.07:34:38.48$vc4f8/valo=3,672.99 2006.224.07:34:38.48#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.224.07:34:38.48#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.224.07:34:38.48#ibcon#ireg 17 cls_cnt 0 2006.224.07:34:38.48#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.224.07:34:38.48#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.224.07:34:38.48#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.224.07:34:38.48#ibcon#enter wrdev, iclass 20, count 0 2006.224.07:34:38.48#ibcon#first serial, iclass 20, count 0 2006.224.07:34:38.48#ibcon#enter sib2, iclass 20, count 0 2006.224.07:34:38.48#ibcon#flushed, iclass 20, count 0 2006.224.07:34:38.48#ibcon#about to write, iclass 20, count 0 2006.224.07:34:38.48#ibcon#wrote, iclass 20, count 0 2006.224.07:34:38.48#ibcon#about to read 3, iclass 20, count 0 2006.224.07:34:38.50#ibcon#read 3, iclass 20, count 0 2006.224.07:34:38.50#ibcon#about to read 4, iclass 20, count 0 2006.224.07:34:38.50#ibcon#read 4, iclass 20, count 0 2006.224.07:34:38.50#ibcon#about to read 5, iclass 20, count 0 2006.224.07:34:38.50#ibcon#read 5, iclass 20, count 0 2006.224.07:34:38.50#ibcon#about to read 6, iclass 20, count 0 2006.224.07:34:38.50#ibcon#read 6, iclass 20, count 0 2006.224.07:34:38.50#ibcon#end of sib2, iclass 20, count 0 2006.224.07:34:38.50#ibcon#*mode == 0, iclass 20, count 0 2006.224.07:34:38.50#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.224.07:34:38.50#ibcon#[26=FRQ=03,672.99\r\n] 2006.224.07:34:38.50#ibcon#*before write, iclass 20, count 0 2006.224.07:34:38.50#ibcon#enter sib2, iclass 20, count 0 2006.224.07:34:38.50#ibcon#flushed, iclass 20, count 0 2006.224.07:34:38.50#ibcon#about to write, iclass 20, count 0 2006.224.07:34:38.50#ibcon#wrote, iclass 20, count 0 2006.224.07:34:38.50#ibcon#about to read 3, iclass 20, count 0 2006.224.07:34:38.55#ibcon#read 3, iclass 20, count 0 2006.224.07:34:38.55#ibcon#about to read 4, iclass 20, count 0 2006.224.07:34:38.55#ibcon#read 4, iclass 20, count 0 2006.224.07:34:38.55#ibcon#about to read 5, iclass 20, count 0 2006.224.07:34:38.55#ibcon#read 5, iclass 20, count 0 2006.224.07:34:38.55#ibcon#about to read 6, iclass 20, count 0 2006.224.07:34:38.55#ibcon#read 6, iclass 20, count 0 2006.224.07:34:38.55#ibcon#end of sib2, iclass 20, count 0 2006.224.07:34:38.55#ibcon#*after write, iclass 20, count 0 2006.224.07:34:38.55#ibcon#*before return 0, iclass 20, count 0 2006.224.07:34:38.55#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.224.07:34:38.55#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.224.07:34:38.55#ibcon#about to clear, iclass 20 cls_cnt 0 2006.224.07:34:38.55#ibcon#cleared, iclass 20 cls_cnt 0 2006.224.07:34:38.55$vc4f8/va=3,6 2006.224.07:34:38.55#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.224.07:34:38.55#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.224.07:34:38.55#ibcon#ireg 11 cls_cnt 2 2006.224.07:34:38.55#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.224.07:34:38.60#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.224.07:34:38.60#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.224.07:34:38.60#ibcon#enter wrdev, iclass 22, count 2 2006.224.07:34:38.60#ibcon#first serial, iclass 22, count 2 2006.224.07:34:38.60#ibcon#enter sib2, iclass 22, count 2 2006.224.07:34:38.60#ibcon#flushed, iclass 22, count 2 2006.224.07:34:38.60#ibcon#about to write, iclass 22, count 2 2006.224.07:34:38.60#ibcon#wrote, iclass 22, count 2 2006.224.07:34:38.60#ibcon#about to read 3, iclass 22, count 2 2006.224.07:34:38.62#ibcon#read 3, iclass 22, count 2 2006.224.07:34:38.62#ibcon#about to read 4, iclass 22, count 2 2006.224.07:34:38.62#ibcon#read 4, iclass 22, count 2 2006.224.07:34:38.62#ibcon#about to read 5, iclass 22, count 2 2006.224.07:34:38.62#ibcon#read 5, iclass 22, count 2 2006.224.07:34:38.62#ibcon#about to read 6, iclass 22, count 2 2006.224.07:34:38.62#ibcon#read 6, iclass 22, count 2 2006.224.07:34:38.62#ibcon#end of sib2, iclass 22, count 2 2006.224.07:34:38.62#ibcon#*mode == 0, iclass 22, count 2 2006.224.07:34:38.62#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.224.07:34:38.62#ibcon#[25=AT03-06\r\n] 2006.224.07:34:38.62#ibcon#*before write, iclass 22, count 2 2006.224.07:34:38.62#ibcon#enter sib2, iclass 22, count 2 2006.224.07:34:38.62#ibcon#flushed, iclass 22, count 2 2006.224.07:34:38.62#ibcon#about to write, iclass 22, count 2 2006.224.07:34:38.62#ibcon#wrote, iclass 22, count 2 2006.224.07:34:38.62#ibcon#about to read 3, iclass 22, count 2 2006.224.07:34:38.65#ibcon#read 3, iclass 22, count 2 2006.224.07:34:38.65#ibcon#about to read 4, iclass 22, count 2 2006.224.07:34:38.65#ibcon#read 4, iclass 22, count 2 2006.224.07:34:38.65#ibcon#about to read 5, iclass 22, count 2 2006.224.07:34:38.65#ibcon#read 5, iclass 22, count 2 2006.224.07:34:38.65#ibcon#about to read 6, iclass 22, count 2 2006.224.07:34:38.65#ibcon#read 6, iclass 22, count 2 2006.224.07:34:38.65#ibcon#end of sib2, iclass 22, count 2 2006.224.07:34:38.65#ibcon#*after write, iclass 22, count 2 2006.224.07:34:38.65#ibcon#*before return 0, iclass 22, count 2 2006.224.07:34:38.65#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.224.07:34:38.65#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.224.07:34:38.65#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.224.07:34:38.65#ibcon#ireg 7 cls_cnt 0 2006.224.07:34:38.65#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.224.07:34:38.77#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.224.07:34:38.77#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.224.07:34:38.77#ibcon#enter wrdev, iclass 22, count 0 2006.224.07:34:38.77#ibcon#first serial, iclass 22, count 0 2006.224.07:34:38.77#ibcon#enter sib2, iclass 22, count 0 2006.224.07:34:38.77#ibcon#flushed, iclass 22, count 0 2006.224.07:34:38.77#ibcon#about to write, iclass 22, count 0 2006.224.07:34:38.77#ibcon#wrote, iclass 22, count 0 2006.224.07:34:38.77#ibcon#about to read 3, iclass 22, count 0 2006.224.07:34:38.79#ibcon#read 3, iclass 22, count 0 2006.224.07:34:38.79#ibcon#about to read 4, iclass 22, count 0 2006.224.07:34:38.79#ibcon#read 4, iclass 22, count 0 2006.224.07:34:38.79#ibcon#about to read 5, iclass 22, count 0 2006.224.07:34:38.79#ibcon#read 5, iclass 22, count 0 2006.224.07:34:38.79#ibcon#about to read 6, iclass 22, count 0 2006.224.07:34:38.79#ibcon#read 6, iclass 22, count 0 2006.224.07:34:38.79#ibcon#end of sib2, iclass 22, count 0 2006.224.07:34:38.79#ibcon#*mode == 0, iclass 22, count 0 2006.224.07:34:38.79#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.224.07:34:38.79#ibcon#[25=USB\r\n] 2006.224.07:34:38.79#ibcon#*before write, iclass 22, count 0 2006.224.07:34:38.79#ibcon#enter sib2, iclass 22, count 0 2006.224.07:34:38.79#ibcon#flushed, iclass 22, count 0 2006.224.07:34:38.79#ibcon#about to write, iclass 22, count 0 2006.224.07:34:38.79#ibcon#wrote, iclass 22, count 0 2006.224.07:34:38.79#ibcon#about to read 3, iclass 22, count 0 2006.224.07:34:38.82#ibcon#read 3, iclass 22, count 0 2006.224.07:34:38.82#ibcon#about to read 4, iclass 22, count 0 2006.224.07:34:38.82#ibcon#read 4, iclass 22, count 0 2006.224.07:34:38.82#ibcon#about to read 5, iclass 22, count 0 2006.224.07:34:38.82#ibcon#read 5, iclass 22, count 0 2006.224.07:34:38.82#ibcon#about to read 6, iclass 22, count 0 2006.224.07:34:38.82#ibcon#read 6, iclass 22, count 0 2006.224.07:34:38.82#ibcon#end of sib2, iclass 22, count 0 2006.224.07:34:38.82#ibcon#*after write, iclass 22, count 0 2006.224.07:34:38.82#ibcon#*before return 0, iclass 22, count 0 2006.224.07:34:38.82#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.224.07:34:38.82#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.224.07:34:38.82#ibcon#about to clear, iclass 22 cls_cnt 0 2006.224.07:34:38.82#ibcon#cleared, iclass 22 cls_cnt 0 2006.224.07:34:38.82$vc4f8/valo=4,832.99 2006.224.07:34:38.82#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.224.07:34:38.82#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.224.07:34:38.82#ibcon#ireg 17 cls_cnt 0 2006.224.07:34:38.82#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.224.07:34:38.82#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.224.07:34:38.82#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.224.07:34:38.82#ibcon#enter wrdev, iclass 24, count 0 2006.224.07:34:38.82#ibcon#first serial, iclass 24, count 0 2006.224.07:34:38.82#ibcon#enter sib2, iclass 24, count 0 2006.224.07:34:38.82#ibcon#flushed, iclass 24, count 0 2006.224.07:34:38.82#ibcon#about to write, iclass 24, count 0 2006.224.07:34:38.82#ibcon#wrote, iclass 24, count 0 2006.224.07:34:38.82#ibcon#about to read 3, iclass 24, count 0 2006.224.07:34:38.84#ibcon#read 3, iclass 24, count 0 2006.224.07:34:38.84#ibcon#about to read 4, iclass 24, count 0 2006.224.07:34:38.84#ibcon#read 4, iclass 24, count 0 2006.224.07:34:38.84#ibcon#about to read 5, iclass 24, count 0 2006.224.07:34:38.84#ibcon#read 5, iclass 24, count 0 2006.224.07:34:38.84#ibcon#about to read 6, iclass 24, count 0 2006.224.07:34:38.84#ibcon#read 6, iclass 24, count 0 2006.224.07:34:38.84#ibcon#end of sib2, iclass 24, count 0 2006.224.07:34:38.84#ibcon#*mode == 0, iclass 24, count 0 2006.224.07:34:38.84#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.224.07:34:38.84#ibcon#[26=FRQ=04,832.99\r\n] 2006.224.07:34:38.84#ibcon#*before write, iclass 24, count 0 2006.224.07:34:38.84#ibcon#enter sib2, iclass 24, count 0 2006.224.07:34:38.84#ibcon#flushed, iclass 24, count 0 2006.224.07:34:38.84#ibcon#about to write, iclass 24, count 0 2006.224.07:34:38.84#ibcon#wrote, iclass 24, count 0 2006.224.07:34:38.84#ibcon#about to read 3, iclass 24, count 0 2006.224.07:34:38.88#ibcon#read 3, iclass 24, count 0 2006.224.07:34:38.88#ibcon#about to read 4, iclass 24, count 0 2006.224.07:34:38.88#ibcon#read 4, iclass 24, count 0 2006.224.07:34:38.88#ibcon#about to read 5, iclass 24, count 0 2006.224.07:34:38.88#ibcon#read 5, iclass 24, count 0 2006.224.07:34:38.88#ibcon#about to read 6, iclass 24, count 0 2006.224.07:34:38.88#ibcon#read 6, iclass 24, count 0 2006.224.07:34:38.88#ibcon#end of sib2, iclass 24, count 0 2006.224.07:34:38.88#ibcon#*after write, iclass 24, count 0 2006.224.07:34:38.88#ibcon#*before return 0, iclass 24, count 0 2006.224.07:34:38.88#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.224.07:34:38.88#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.224.07:34:38.88#ibcon#about to clear, iclass 24 cls_cnt 0 2006.224.07:34:38.88#ibcon#cleared, iclass 24 cls_cnt 0 2006.224.07:34:38.88$vc4f8/va=4,7 2006.224.07:34:38.88#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.224.07:34:38.88#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.224.07:34:38.88#ibcon#ireg 11 cls_cnt 2 2006.224.07:34:38.88#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.224.07:34:38.94#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.224.07:34:38.94#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.224.07:34:38.94#ibcon#enter wrdev, iclass 26, count 2 2006.224.07:34:38.94#ibcon#first serial, iclass 26, count 2 2006.224.07:34:38.94#ibcon#enter sib2, iclass 26, count 2 2006.224.07:34:38.94#ibcon#flushed, iclass 26, count 2 2006.224.07:34:38.94#ibcon#about to write, iclass 26, count 2 2006.224.07:34:38.94#ibcon#wrote, iclass 26, count 2 2006.224.07:34:38.94#ibcon#about to read 3, iclass 26, count 2 2006.224.07:34:38.96#ibcon#read 3, iclass 26, count 2 2006.224.07:34:38.96#ibcon#about to read 4, iclass 26, count 2 2006.224.07:34:38.96#ibcon#read 4, iclass 26, count 2 2006.224.07:34:38.96#ibcon#about to read 5, iclass 26, count 2 2006.224.07:34:38.96#ibcon#read 5, iclass 26, count 2 2006.224.07:34:38.96#ibcon#about to read 6, iclass 26, count 2 2006.224.07:34:38.96#ibcon#read 6, iclass 26, count 2 2006.224.07:34:38.96#ibcon#end of sib2, iclass 26, count 2 2006.224.07:34:38.96#ibcon#*mode == 0, iclass 26, count 2 2006.224.07:34:38.96#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.224.07:34:38.96#ibcon#[25=AT04-07\r\n] 2006.224.07:34:38.96#ibcon#*before write, iclass 26, count 2 2006.224.07:34:38.96#ibcon#enter sib2, iclass 26, count 2 2006.224.07:34:38.96#ibcon#flushed, iclass 26, count 2 2006.224.07:34:38.96#ibcon#about to write, iclass 26, count 2 2006.224.07:34:38.96#ibcon#wrote, iclass 26, count 2 2006.224.07:34:38.96#ibcon#about to read 3, iclass 26, count 2 2006.224.07:34:38.99#ibcon#read 3, iclass 26, count 2 2006.224.07:34:38.99#ibcon#about to read 4, iclass 26, count 2 2006.224.07:34:38.99#ibcon#read 4, iclass 26, count 2 2006.224.07:34:38.99#ibcon#about to read 5, iclass 26, count 2 2006.224.07:34:38.99#ibcon#read 5, iclass 26, count 2 2006.224.07:34:38.99#ibcon#about to read 6, iclass 26, count 2 2006.224.07:34:38.99#ibcon#read 6, iclass 26, count 2 2006.224.07:34:38.99#ibcon#end of sib2, iclass 26, count 2 2006.224.07:34:38.99#ibcon#*after write, iclass 26, count 2 2006.224.07:34:38.99#ibcon#*before return 0, iclass 26, count 2 2006.224.07:34:38.99#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.224.07:34:38.99#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.224.07:34:38.99#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.224.07:34:38.99#ibcon#ireg 7 cls_cnt 0 2006.224.07:34:38.99#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.224.07:34:39.11#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.224.07:34:39.11#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.224.07:34:39.11#ibcon#enter wrdev, iclass 26, count 0 2006.224.07:34:39.11#ibcon#first serial, iclass 26, count 0 2006.224.07:34:39.11#ibcon#enter sib2, iclass 26, count 0 2006.224.07:34:39.11#ibcon#flushed, iclass 26, count 0 2006.224.07:34:39.11#ibcon#about to write, iclass 26, count 0 2006.224.07:34:39.11#ibcon#wrote, iclass 26, count 0 2006.224.07:34:39.11#ibcon#about to read 3, iclass 26, count 0 2006.224.07:34:39.13#ibcon#read 3, iclass 26, count 0 2006.224.07:34:39.13#ibcon#about to read 4, iclass 26, count 0 2006.224.07:34:39.13#ibcon#read 4, iclass 26, count 0 2006.224.07:34:39.13#ibcon#about to read 5, iclass 26, count 0 2006.224.07:34:39.13#ibcon#read 5, iclass 26, count 0 2006.224.07:34:39.13#ibcon#about to read 6, iclass 26, count 0 2006.224.07:34:39.13#ibcon#read 6, iclass 26, count 0 2006.224.07:34:39.13#ibcon#end of sib2, iclass 26, count 0 2006.224.07:34:39.13#ibcon#*mode == 0, iclass 26, count 0 2006.224.07:34:39.13#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.224.07:34:39.13#ibcon#[25=USB\r\n] 2006.224.07:34:39.13#ibcon#*before write, iclass 26, count 0 2006.224.07:34:39.13#ibcon#enter sib2, iclass 26, count 0 2006.224.07:34:39.13#ibcon#flushed, iclass 26, count 0 2006.224.07:34:39.13#ibcon#about to write, iclass 26, count 0 2006.224.07:34:39.13#ibcon#wrote, iclass 26, count 0 2006.224.07:34:39.13#ibcon#about to read 3, iclass 26, count 0 2006.224.07:34:39.16#ibcon#read 3, iclass 26, count 0 2006.224.07:34:39.16#ibcon#about to read 4, iclass 26, count 0 2006.224.07:34:39.16#ibcon#read 4, iclass 26, count 0 2006.224.07:34:39.16#ibcon#about to read 5, iclass 26, count 0 2006.224.07:34:39.16#ibcon#read 5, iclass 26, count 0 2006.224.07:34:39.16#ibcon#about to read 6, iclass 26, count 0 2006.224.07:34:39.16#ibcon#read 6, iclass 26, count 0 2006.224.07:34:39.16#ibcon#end of sib2, iclass 26, count 0 2006.224.07:34:39.16#ibcon#*after write, iclass 26, count 0 2006.224.07:34:39.16#ibcon#*before return 0, iclass 26, count 0 2006.224.07:34:39.16#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.224.07:34:39.16#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.224.07:34:39.16#ibcon#about to clear, iclass 26 cls_cnt 0 2006.224.07:34:39.16#ibcon#cleared, iclass 26 cls_cnt 0 2006.224.07:34:39.16$vc4f8/valo=5,652.99 2006.224.07:34:39.16#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.224.07:34:39.16#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.224.07:34:39.16#ibcon#ireg 17 cls_cnt 0 2006.224.07:34:39.16#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.224.07:34:39.16#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.224.07:34:39.16#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.224.07:34:39.16#ibcon#enter wrdev, iclass 28, count 0 2006.224.07:34:39.16#ibcon#first serial, iclass 28, count 0 2006.224.07:34:39.16#ibcon#enter sib2, iclass 28, count 0 2006.224.07:34:39.16#ibcon#flushed, iclass 28, count 0 2006.224.07:34:39.16#ibcon#about to write, iclass 28, count 0 2006.224.07:34:39.16#ibcon#wrote, iclass 28, count 0 2006.224.07:34:39.16#ibcon#about to read 3, iclass 28, count 0 2006.224.07:34:39.18#ibcon#read 3, iclass 28, count 0 2006.224.07:34:39.18#ibcon#about to read 4, iclass 28, count 0 2006.224.07:34:39.18#ibcon#read 4, iclass 28, count 0 2006.224.07:34:39.18#ibcon#about to read 5, iclass 28, count 0 2006.224.07:34:39.18#ibcon#read 5, iclass 28, count 0 2006.224.07:34:39.18#ibcon#about to read 6, iclass 28, count 0 2006.224.07:34:39.18#ibcon#read 6, iclass 28, count 0 2006.224.07:34:39.18#ibcon#end of sib2, iclass 28, count 0 2006.224.07:34:39.18#ibcon#*mode == 0, iclass 28, count 0 2006.224.07:34:39.18#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.224.07:34:39.18#ibcon#[26=FRQ=05,652.99\r\n] 2006.224.07:34:39.18#ibcon#*before write, iclass 28, count 0 2006.224.07:34:39.18#ibcon#enter sib2, iclass 28, count 0 2006.224.07:34:39.18#ibcon#flushed, iclass 28, count 0 2006.224.07:34:39.18#ibcon#about to write, iclass 28, count 0 2006.224.07:34:39.18#ibcon#wrote, iclass 28, count 0 2006.224.07:34:39.18#ibcon#about to read 3, iclass 28, count 0 2006.224.07:34:39.22#ibcon#read 3, iclass 28, count 0 2006.224.07:34:39.22#ibcon#about to read 4, iclass 28, count 0 2006.224.07:34:39.22#ibcon#read 4, iclass 28, count 0 2006.224.07:34:39.22#ibcon#about to read 5, iclass 28, count 0 2006.224.07:34:39.22#ibcon#read 5, iclass 28, count 0 2006.224.07:34:39.22#ibcon#about to read 6, iclass 28, count 0 2006.224.07:34:39.22#ibcon#read 6, iclass 28, count 0 2006.224.07:34:39.22#ibcon#end of sib2, iclass 28, count 0 2006.224.07:34:39.22#ibcon#*after write, iclass 28, count 0 2006.224.07:34:39.22#ibcon#*before return 0, iclass 28, count 0 2006.224.07:34:39.22#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.224.07:34:39.22#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.224.07:34:39.22#ibcon#about to clear, iclass 28 cls_cnt 0 2006.224.07:34:39.22#ibcon#cleared, iclass 28 cls_cnt 0 2006.224.07:34:39.22$vc4f8/va=5,7 2006.224.07:34:39.22#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.224.07:34:39.22#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.224.07:34:39.22#ibcon#ireg 11 cls_cnt 2 2006.224.07:34:39.22#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.224.07:34:39.28#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.224.07:34:39.28#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.224.07:34:39.28#ibcon#enter wrdev, iclass 30, count 2 2006.224.07:34:39.28#ibcon#first serial, iclass 30, count 2 2006.224.07:34:39.28#ibcon#enter sib2, iclass 30, count 2 2006.224.07:34:39.28#ibcon#flushed, iclass 30, count 2 2006.224.07:34:39.28#ibcon#about to write, iclass 30, count 2 2006.224.07:34:39.28#ibcon#wrote, iclass 30, count 2 2006.224.07:34:39.28#ibcon#about to read 3, iclass 30, count 2 2006.224.07:34:39.30#ibcon#read 3, iclass 30, count 2 2006.224.07:34:39.30#ibcon#about to read 4, iclass 30, count 2 2006.224.07:34:39.30#ibcon#read 4, iclass 30, count 2 2006.224.07:34:39.30#ibcon#about to read 5, iclass 30, count 2 2006.224.07:34:39.30#ibcon#read 5, iclass 30, count 2 2006.224.07:34:39.30#ibcon#about to read 6, iclass 30, count 2 2006.224.07:34:39.30#ibcon#read 6, iclass 30, count 2 2006.224.07:34:39.30#ibcon#end of sib2, iclass 30, count 2 2006.224.07:34:39.30#ibcon#*mode == 0, iclass 30, count 2 2006.224.07:34:39.30#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.224.07:34:39.30#ibcon#[25=AT05-07\r\n] 2006.224.07:34:39.30#ibcon#*before write, iclass 30, count 2 2006.224.07:34:39.30#ibcon#enter sib2, iclass 30, count 2 2006.224.07:34:39.30#ibcon#flushed, iclass 30, count 2 2006.224.07:34:39.30#ibcon#about to write, iclass 30, count 2 2006.224.07:34:39.30#ibcon#wrote, iclass 30, count 2 2006.224.07:34:39.30#ibcon#about to read 3, iclass 30, count 2 2006.224.07:34:39.33#ibcon#read 3, iclass 30, count 2 2006.224.07:34:39.33#ibcon#about to read 4, iclass 30, count 2 2006.224.07:34:39.33#ibcon#read 4, iclass 30, count 2 2006.224.07:34:39.33#ibcon#about to read 5, iclass 30, count 2 2006.224.07:34:39.33#ibcon#read 5, iclass 30, count 2 2006.224.07:34:39.33#ibcon#about to read 6, iclass 30, count 2 2006.224.07:34:39.33#ibcon#read 6, iclass 30, count 2 2006.224.07:34:39.33#ibcon#end of sib2, iclass 30, count 2 2006.224.07:34:39.33#ibcon#*after write, iclass 30, count 2 2006.224.07:34:39.33#ibcon#*before return 0, iclass 30, count 2 2006.224.07:34:39.33#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.224.07:34:39.33#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.224.07:34:39.33#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.224.07:34:39.33#ibcon#ireg 7 cls_cnt 0 2006.224.07:34:39.33#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.224.07:34:39.45#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.224.07:34:39.45#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.224.07:34:39.45#ibcon#enter wrdev, iclass 30, count 0 2006.224.07:34:39.45#ibcon#first serial, iclass 30, count 0 2006.224.07:34:39.45#ibcon#enter sib2, iclass 30, count 0 2006.224.07:34:39.45#ibcon#flushed, iclass 30, count 0 2006.224.07:34:39.45#ibcon#about to write, iclass 30, count 0 2006.224.07:34:39.45#ibcon#wrote, iclass 30, count 0 2006.224.07:34:39.45#ibcon#about to read 3, iclass 30, count 0 2006.224.07:34:39.47#ibcon#read 3, iclass 30, count 0 2006.224.07:34:39.47#ibcon#about to read 4, iclass 30, count 0 2006.224.07:34:39.47#ibcon#read 4, iclass 30, count 0 2006.224.07:34:39.47#ibcon#about to read 5, iclass 30, count 0 2006.224.07:34:39.47#ibcon#read 5, iclass 30, count 0 2006.224.07:34:39.47#ibcon#about to read 6, iclass 30, count 0 2006.224.07:34:39.47#ibcon#read 6, iclass 30, count 0 2006.224.07:34:39.47#ibcon#end of sib2, iclass 30, count 0 2006.224.07:34:39.47#ibcon#*mode == 0, iclass 30, count 0 2006.224.07:34:39.47#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.224.07:34:39.47#ibcon#[25=USB\r\n] 2006.224.07:34:39.47#ibcon#*before write, iclass 30, count 0 2006.224.07:34:39.47#ibcon#enter sib2, iclass 30, count 0 2006.224.07:34:39.47#ibcon#flushed, iclass 30, count 0 2006.224.07:34:39.47#ibcon#about to write, iclass 30, count 0 2006.224.07:34:39.47#ibcon#wrote, iclass 30, count 0 2006.224.07:34:39.47#ibcon#about to read 3, iclass 30, count 0 2006.224.07:34:39.50#ibcon#read 3, iclass 30, count 0 2006.224.07:34:39.50#ibcon#about to read 4, iclass 30, count 0 2006.224.07:34:39.50#ibcon#read 4, iclass 30, count 0 2006.224.07:34:39.50#ibcon#about to read 5, iclass 30, count 0 2006.224.07:34:39.50#ibcon#read 5, iclass 30, count 0 2006.224.07:34:39.50#ibcon#about to read 6, iclass 30, count 0 2006.224.07:34:39.50#ibcon#read 6, iclass 30, count 0 2006.224.07:34:39.50#ibcon#end of sib2, iclass 30, count 0 2006.224.07:34:39.50#ibcon#*after write, iclass 30, count 0 2006.224.07:34:39.50#ibcon#*before return 0, iclass 30, count 0 2006.224.07:34:39.50#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.224.07:34:39.50#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.224.07:34:39.50#ibcon#about to clear, iclass 30 cls_cnt 0 2006.224.07:34:39.50#ibcon#cleared, iclass 30 cls_cnt 0 2006.224.07:34:39.50$vc4f8/valo=6,772.99 2006.224.07:34:39.50#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.224.07:34:39.50#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.224.07:34:39.50#ibcon#ireg 17 cls_cnt 0 2006.224.07:34:39.50#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.224.07:34:39.50#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.224.07:34:39.50#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.224.07:34:39.50#ibcon#enter wrdev, iclass 32, count 0 2006.224.07:34:39.50#ibcon#first serial, iclass 32, count 0 2006.224.07:34:39.50#ibcon#enter sib2, iclass 32, count 0 2006.224.07:34:39.50#ibcon#flushed, iclass 32, count 0 2006.224.07:34:39.50#ibcon#about to write, iclass 32, count 0 2006.224.07:34:39.50#ibcon#wrote, iclass 32, count 0 2006.224.07:34:39.50#ibcon#about to read 3, iclass 32, count 0 2006.224.07:34:39.52#ibcon#read 3, iclass 32, count 0 2006.224.07:34:39.52#ibcon#about to read 4, iclass 32, count 0 2006.224.07:34:39.52#ibcon#read 4, iclass 32, count 0 2006.224.07:34:39.52#ibcon#about to read 5, iclass 32, count 0 2006.224.07:34:39.52#ibcon#read 5, iclass 32, count 0 2006.224.07:34:39.52#ibcon#about to read 6, iclass 32, count 0 2006.224.07:34:39.52#ibcon#read 6, iclass 32, count 0 2006.224.07:34:39.52#ibcon#end of sib2, iclass 32, count 0 2006.224.07:34:39.52#ibcon#*mode == 0, iclass 32, count 0 2006.224.07:34:39.52#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.224.07:34:39.52#ibcon#[26=FRQ=06,772.99\r\n] 2006.224.07:34:39.52#ibcon#*before write, iclass 32, count 0 2006.224.07:34:39.52#ibcon#enter sib2, iclass 32, count 0 2006.224.07:34:39.52#ibcon#flushed, iclass 32, count 0 2006.224.07:34:39.52#ibcon#about to write, iclass 32, count 0 2006.224.07:34:39.52#ibcon#wrote, iclass 32, count 0 2006.224.07:34:39.52#ibcon#about to read 3, iclass 32, count 0 2006.224.07:34:39.56#ibcon#read 3, iclass 32, count 0 2006.224.07:34:39.56#ibcon#about to read 4, iclass 32, count 0 2006.224.07:34:39.56#ibcon#read 4, iclass 32, count 0 2006.224.07:34:39.56#ibcon#about to read 5, iclass 32, count 0 2006.224.07:34:39.56#ibcon#read 5, iclass 32, count 0 2006.224.07:34:39.56#ibcon#about to read 6, iclass 32, count 0 2006.224.07:34:39.56#ibcon#read 6, iclass 32, count 0 2006.224.07:34:39.56#ibcon#end of sib2, iclass 32, count 0 2006.224.07:34:39.56#ibcon#*after write, iclass 32, count 0 2006.224.07:34:39.56#ibcon#*before return 0, iclass 32, count 0 2006.224.07:34:39.56#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.224.07:34:39.56#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.224.07:34:39.56#ibcon#about to clear, iclass 32 cls_cnt 0 2006.224.07:34:39.56#ibcon#cleared, iclass 32 cls_cnt 0 2006.224.07:34:39.56$vc4f8/va=6,6 2006.224.07:34:39.56#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.224.07:34:39.56#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.224.07:34:39.56#ibcon#ireg 11 cls_cnt 2 2006.224.07:34:39.56#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.224.07:34:39.62#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.224.07:34:39.62#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.224.07:34:39.62#ibcon#enter wrdev, iclass 34, count 2 2006.224.07:34:39.62#ibcon#first serial, iclass 34, count 2 2006.224.07:34:39.62#ibcon#enter sib2, iclass 34, count 2 2006.224.07:34:39.62#ibcon#flushed, iclass 34, count 2 2006.224.07:34:39.62#ibcon#about to write, iclass 34, count 2 2006.224.07:34:39.62#ibcon#wrote, iclass 34, count 2 2006.224.07:34:39.62#ibcon#about to read 3, iclass 34, count 2 2006.224.07:34:39.64#ibcon#read 3, iclass 34, count 2 2006.224.07:34:39.64#ibcon#about to read 4, iclass 34, count 2 2006.224.07:34:39.64#ibcon#read 4, iclass 34, count 2 2006.224.07:34:39.64#ibcon#about to read 5, iclass 34, count 2 2006.224.07:34:39.64#ibcon#read 5, iclass 34, count 2 2006.224.07:34:39.64#ibcon#about to read 6, iclass 34, count 2 2006.224.07:34:39.64#ibcon#read 6, iclass 34, count 2 2006.224.07:34:39.64#ibcon#end of sib2, iclass 34, count 2 2006.224.07:34:39.64#ibcon#*mode == 0, iclass 34, count 2 2006.224.07:34:39.64#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.224.07:34:39.64#ibcon#[25=AT06-06\r\n] 2006.224.07:34:39.64#ibcon#*before write, iclass 34, count 2 2006.224.07:34:39.64#ibcon#enter sib2, iclass 34, count 2 2006.224.07:34:39.64#ibcon#flushed, iclass 34, count 2 2006.224.07:34:39.64#ibcon#about to write, iclass 34, count 2 2006.224.07:34:39.64#ibcon#wrote, iclass 34, count 2 2006.224.07:34:39.64#ibcon#about to read 3, iclass 34, count 2 2006.224.07:34:39.67#ibcon#read 3, iclass 34, count 2 2006.224.07:34:39.67#ibcon#about to read 4, iclass 34, count 2 2006.224.07:34:39.67#ibcon#read 4, iclass 34, count 2 2006.224.07:34:39.67#ibcon#about to read 5, iclass 34, count 2 2006.224.07:34:39.67#ibcon#read 5, iclass 34, count 2 2006.224.07:34:39.67#ibcon#about to read 6, iclass 34, count 2 2006.224.07:34:39.67#ibcon#read 6, iclass 34, count 2 2006.224.07:34:39.67#ibcon#end of sib2, iclass 34, count 2 2006.224.07:34:39.67#ibcon#*after write, iclass 34, count 2 2006.224.07:34:39.67#ibcon#*before return 0, iclass 34, count 2 2006.224.07:34:39.67#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.224.07:34:39.67#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.224.07:34:39.67#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.224.07:34:39.67#ibcon#ireg 7 cls_cnt 0 2006.224.07:34:39.67#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.224.07:34:39.79#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.224.07:34:39.79#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.224.07:34:39.79#ibcon#enter wrdev, iclass 34, count 0 2006.224.07:34:39.79#ibcon#first serial, iclass 34, count 0 2006.224.07:34:39.79#ibcon#enter sib2, iclass 34, count 0 2006.224.07:34:39.79#ibcon#flushed, iclass 34, count 0 2006.224.07:34:39.79#ibcon#about to write, iclass 34, count 0 2006.224.07:34:39.79#ibcon#wrote, iclass 34, count 0 2006.224.07:34:39.79#ibcon#about to read 3, iclass 34, count 0 2006.224.07:34:39.81#ibcon#read 3, iclass 34, count 0 2006.224.07:34:39.81#ibcon#about to read 4, iclass 34, count 0 2006.224.07:34:39.81#ibcon#read 4, iclass 34, count 0 2006.224.07:34:39.81#ibcon#about to read 5, iclass 34, count 0 2006.224.07:34:39.81#ibcon#read 5, iclass 34, count 0 2006.224.07:34:39.81#ibcon#about to read 6, iclass 34, count 0 2006.224.07:34:39.81#ibcon#read 6, iclass 34, count 0 2006.224.07:34:39.81#ibcon#end of sib2, iclass 34, count 0 2006.224.07:34:39.81#ibcon#*mode == 0, iclass 34, count 0 2006.224.07:34:39.81#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.224.07:34:39.81#ibcon#[25=USB\r\n] 2006.224.07:34:39.81#ibcon#*before write, iclass 34, count 0 2006.224.07:34:39.81#ibcon#enter sib2, iclass 34, count 0 2006.224.07:34:39.81#ibcon#flushed, iclass 34, count 0 2006.224.07:34:39.81#ibcon#about to write, iclass 34, count 0 2006.224.07:34:39.81#ibcon#wrote, iclass 34, count 0 2006.224.07:34:39.81#ibcon#about to read 3, iclass 34, count 0 2006.224.07:34:39.84#ibcon#read 3, iclass 34, count 0 2006.224.07:34:39.84#ibcon#about to read 4, iclass 34, count 0 2006.224.07:34:39.84#ibcon#read 4, iclass 34, count 0 2006.224.07:34:39.84#ibcon#about to read 5, iclass 34, count 0 2006.224.07:34:39.84#ibcon#read 5, iclass 34, count 0 2006.224.07:34:39.84#ibcon#about to read 6, iclass 34, count 0 2006.224.07:34:39.84#ibcon#read 6, iclass 34, count 0 2006.224.07:34:39.84#ibcon#end of sib2, iclass 34, count 0 2006.224.07:34:39.84#ibcon#*after write, iclass 34, count 0 2006.224.07:34:39.84#ibcon#*before return 0, iclass 34, count 0 2006.224.07:34:39.84#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.224.07:34:39.84#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.224.07:34:39.84#ibcon#about to clear, iclass 34 cls_cnt 0 2006.224.07:34:39.84#ibcon#cleared, iclass 34 cls_cnt 0 2006.224.07:34:39.84$vc4f8/valo=7,832.99 2006.224.07:34:39.84#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.224.07:34:39.84#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.224.07:34:39.84#ibcon#ireg 17 cls_cnt 0 2006.224.07:34:39.84#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.224.07:34:39.84#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.224.07:34:39.84#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.224.07:34:39.84#ibcon#enter wrdev, iclass 36, count 0 2006.224.07:34:39.84#ibcon#first serial, iclass 36, count 0 2006.224.07:34:39.84#ibcon#enter sib2, iclass 36, count 0 2006.224.07:34:39.84#ibcon#flushed, iclass 36, count 0 2006.224.07:34:39.84#ibcon#about to write, iclass 36, count 0 2006.224.07:34:39.84#ibcon#wrote, iclass 36, count 0 2006.224.07:34:39.84#ibcon#about to read 3, iclass 36, count 0 2006.224.07:34:39.86#ibcon#read 3, iclass 36, count 0 2006.224.07:34:39.86#ibcon#about to read 4, iclass 36, count 0 2006.224.07:34:39.86#ibcon#read 4, iclass 36, count 0 2006.224.07:34:39.86#ibcon#about to read 5, iclass 36, count 0 2006.224.07:34:39.86#ibcon#read 5, iclass 36, count 0 2006.224.07:34:39.86#ibcon#about to read 6, iclass 36, count 0 2006.224.07:34:39.86#ibcon#read 6, iclass 36, count 0 2006.224.07:34:39.86#ibcon#end of sib2, iclass 36, count 0 2006.224.07:34:39.86#ibcon#*mode == 0, iclass 36, count 0 2006.224.07:34:39.86#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.224.07:34:39.86#ibcon#[26=FRQ=07,832.99\r\n] 2006.224.07:34:39.86#ibcon#*before write, iclass 36, count 0 2006.224.07:34:39.86#ibcon#enter sib2, iclass 36, count 0 2006.224.07:34:39.86#ibcon#flushed, iclass 36, count 0 2006.224.07:34:39.86#ibcon#about to write, iclass 36, count 0 2006.224.07:34:39.86#ibcon#wrote, iclass 36, count 0 2006.224.07:34:39.86#ibcon#about to read 3, iclass 36, count 0 2006.224.07:34:39.90#ibcon#read 3, iclass 36, count 0 2006.224.07:34:39.90#ibcon#about to read 4, iclass 36, count 0 2006.224.07:34:39.90#ibcon#read 4, iclass 36, count 0 2006.224.07:34:39.90#ibcon#about to read 5, iclass 36, count 0 2006.224.07:34:39.90#ibcon#read 5, iclass 36, count 0 2006.224.07:34:39.90#ibcon#about to read 6, iclass 36, count 0 2006.224.07:34:39.90#ibcon#read 6, iclass 36, count 0 2006.224.07:34:39.90#ibcon#end of sib2, iclass 36, count 0 2006.224.07:34:39.90#ibcon#*after write, iclass 36, count 0 2006.224.07:34:39.90#ibcon#*before return 0, iclass 36, count 0 2006.224.07:34:39.90#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.224.07:34:39.90#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.224.07:34:39.90#ibcon#about to clear, iclass 36 cls_cnt 0 2006.224.07:34:39.90#ibcon#cleared, iclass 36 cls_cnt 0 2006.224.07:34:39.90$vc4f8/va=7,6 2006.224.07:34:39.90#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.224.07:34:39.90#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.224.07:34:39.90#ibcon#ireg 11 cls_cnt 2 2006.224.07:34:39.90#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.224.07:34:39.96#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.224.07:34:39.96#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.224.07:34:39.96#ibcon#enter wrdev, iclass 38, count 2 2006.224.07:34:39.96#ibcon#first serial, iclass 38, count 2 2006.224.07:34:39.96#ibcon#enter sib2, iclass 38, count 2 2006.224.07:34:39.96#ibcon#flushed, iclass 38, count 2 2006.224.07:34:39.96#ibcon#about to write, iclass 38, count 2 2006.224.07:34:39.96#ibcon#wrote, iclass 38, count 2 2006.224.07:34:39.96#ibcon#about to read 3, iclass 38, count 2 2006.224.07:34:39.98#ibcon#read 3, iclass 38, count 2 2006.224.07:34:39.98#ibcon#about to read 4, iclass 38, count 2 2006.224.07:34:39.98#ibcon#read 4, iclass 38, count 2 2006.224.07:34:39.98#ibcon#about to read 5, iclass 38, count 2 2006.224.07:34:39.98#ibcon#read 5, iclass 38, count 2 2006.224.07:34:39.98#ibcon#about to read 6, iclass 38, count 2 2006.224.07:34:39.98#ibcon#read 6, iclass 38, count 2 2006.224.07:34:39.98#ibcon#end of sib2, iclass 38, count 2 2006.224.07:34:39.98#ibcon#*mode == 0, iclass 38, count 2 2006.224.07:34:39.98#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.224.07:34:39.98#ibcon#[25=AT07-06\r\n] 2006.224.07:34:39.98#ibcon#*before write, iclass 38, count 2 2006.224.07:34:39.98#ibcon#enter sib2, iclass 38, count 2 2006.224.07:34:39.98#ibcon#flushed, iclass 38, count 2 2006.224.07:34:39.98#ibcon#about to write, iclass 38, count 2 2006.224.07:34:39.98#ibcon#wrote, iclass 38, count 2 2006.224.07:34:39.98#ibcon#about to read 3, iclass 38, count 2 2006.224.07:34:40.01#ibcon#read 3, iclass 38, count 2 2006.224.07:34:40.01#ibcon#about to read 4, iclass 38, count 2 2006.224.07:34:40.01#ibcon#read 4, iclass 38, count 2 2006.224.07:34:40.01#ibcon#about to read 5, iclass 38, count 2 2006.224.07:34:40.01#ibcon#read 5, iclass 38, count 2 2006.224.07:34:40.01#ibcon#about to read 6, iclass 38, count 2 2006.224.07:34:40.01#ibcon#read 6, iclass 38, count 2 2006.224.07:34:40.01#ibcon#end of sib2, iclass 38, count 2 2006.224.07:34:40.01#ibcon#*after write, iclass 38, count 2 2006.224.07:34:40.01#ibcon#*before return 0, iclass 38, count 2 2006.224.07:34:40.01#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.224.07:34:40.01#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.224.07:34:40.01#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.224.07:34:40.01#ibcon#ireg 7 cls_cnt 0 2006.224.07:34:40.01#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.224.07:34:40.13#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.224.07:34:40.13#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.224.07:34:40.13#ibcon#enter wrdev, iclass 38, count 0 2006.224.07:34:40.13#ibcon#first serial, iclass 38, count 0 2006.224.07:34:40.13#ibcon#enter sib2, iclass 38, count 0 2006.224.07:34:40.13#ibcon#flushed, iclass 38, count 0 2006.224.07:34:40.13#ibcon#about to write, iclass 38, count 0 2006.224.07:34:40.13#ibcon#wrote, iclass 38, count 0 2006.224.07:34:40.13#ibcon#about to read 3, iclass 38, count 0 2006.224.07:34:40.15#ibcon#read 3, iclass 38, count 0 2006.224.07:34:40.15#ibcon#about to read 4, iclass 38, count 0 2006.224.07:34:40.15#ibcon#read 4, iclass 38, count 0 2006.224.07:34:40.15#ibcon#about to read 5, iclass 38, count 0 2006.224.07:34:40.15#ibcon#read 5, iclass 38, count 0 2006.224.07:34:40.15#ibcon#about to read 6, iclass 38, count 0 2006.224.07:34:40.15#ibcon#read 6, iclass 38, count 0 2006.224.07:34:40.15#ibcon#end of sib2, iclass 38, count 0 2006.224.07:34:40.15#ibcon#*mode == 0, iclass 38, count 0 2006.224.07:34:40.15#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.224.07:34:40.15#ibcon#[25=USB\r\n] 2006.224.07:34:40.15#ibcon#*before write, iclass 38, count 0 2006.224.07:34:40.15#ibcon#enter sib2, iclass 38, count 0 2006.224.07:34:40.15#ibcon#flushed, iclass 38, count 0 2006.224.07:34:40.15#ibcon#about to write, iclass 38, count 0 2006.224.07:34:40.15#ibcon#wrote, iclass 38, count 0 2006.224.07:34:40.15#ibcon#about to read 3, iclass 38, count 0 2006.224.07:34:40.18#ibcon#read 3, iclass 38, count 0 2006.224.07:34:40.18#ibcon#about to read 4, iclass 38, count 0 2006.224.07:34:40.18#ibcon#read 4, iclass 38, count 0 2006.224.07:34:40.18#ibcon#about to read 5, iclass 38, count 0 2006.224.07:34:40.18#ibcon#read 5, iclass 38, count 0 2006.224.07:34:40.18#ibcon#about to read 6, iclass 38, count 0 2006.224.07:34:40.18#ibcon#read 6, iclass 38, count 0 2006.224.07:34:40.18#ibcon#end of sib2, iclass 38, count 0 2006.224.07:34:40.18#ibcon#*after write, iclass 38, count 0 2006.224.07:34:40.18#ibcon#*before return 0, iclass 38, count 0 2006.224.07:34:40.18#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.224.07:34:40.18#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.224.07:34:40.18#ibcon#about to clear, iclass 38 cls_cnt 0 2006.224.07:34:40.18#ibcon#cleared, iclass 38 cls_cnt 0 2006.224.07:34:40.18$vc4f8/valo=8,852.99 2006.224.07:34:40.18#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.224.07:34:40.18#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.224.07:34:40.18#ibcon#ireg 17 cls_cnt 0 2006.224.07:34:40.18#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.224.07:34:40.18#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.224.07:34:40.18#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.224.07:34:40.18#ibcon#enter wrdev, iclass 40, count 0 2006.224.07:34:40.18#ibcon#first serial, iclass 40, count 0 2006.224.07:34:40.18#ibcon#enter sib2, iclass 40, count 0 2006.224.07:34:40.18#ibcon#flushed, iclass 40, count 0 2006.224.07:34:40.18#ibcon#about to write, iclass 40, count 0 2006.224.07:34:40.18#ibcon#wrote, iclass 40, count 0 2006.224.07:34:40.18#ibcon#about to read 3, iclass 40, count 0 2006.224.07:34:40.20#ibcon#read 3, iclass 40, count 0 2006.224.07:34:40.20#ibcon#about to read 4, iclass 40, count 0 2006.224.07:34:40.20#ibcon#read 4, iclass 40, count 0 2006.224.07:34:40.20#ibcon#about to read 5, iclass 40, count 0 2006.224.07:34:40.20#ibcon#read 5, iclass 40, count 0 2006.224.07:34:40.20#ibcon#about to read 6, iclass 40, count 0 2006.224.07:34:40.20#ibcon#read 6, iclass 40, count 0 2006.224.07:34:40.20#ibcon#end of sib2, iclass 40, count 0 2006.224.07:34:40.20#ibcon#*mode == 0, iclass 40, count 0 2006.224.07:34:40.20#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.224.07:34:40.20#ibcon#[26=FRQ=08,852.99\r\n] 2006.224.07:34:40.20#ibcon#*before write, iclass 40, count 0 2006.224.07:34:40.20#ibcon#enter sib2, iclass 40, count 0 2006.224.07:34:40.20#ibcon#flushed, iclass 40, count 0 2006.224.07:34:40.20#ibcon#about to write, iclass 40, count 0 2006.224.07:34:40.20#ibcon#wrote, iclass 40, count 0 2006.224.07:34:40.20#ibcon#about to read 3, iclass 40, count 0 2006.224.07:34:40.24#ibcon#read 3, iclass 40, count 0 2006.224.07:34:40.24#ibcon#about to read 4, iclass 40, count 0 2006.224.07:34:40.24#ibcon#read 4, iclass 40, count 0 2006.224.07:34:40.24#ibcon#about to read 5, iclass 40, count 0 2006.224.07:34:40.24#ibcon#read 5, iclass 40, count 0 2006.224.07:34:40.24#ibcon#about to read 6, iclass 40, count 0 2006.224.07:34:40.24#ibcon#read 6, iclass 40, count 0 2006.224.07:34:40.24#ibcon#end of sib2, iclass 40, count 0 2006.224.07:34:40.24#ibcon#*after write, iclass 40, count 0 2006.224.07:34:40.24#ibcon#*before return 0, iclass 40, count 0 2006.224.07:34:40.24#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.224.07:34:40.24#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.224.07:34:40.24#ibcon#about to clear, iclass 40 cls_cnt 0 2006.224.07:34:40.24#ibcon#cleared, iclass 40 cls_cnt 0 2006.224.07:34:40.24$vc4f8/va=8,7 2006.224.07:34:40.24#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.224.07:34:40.24#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.224.07:34:40.24#ibcon#ireg 11 cls_cnt 2 2006.224.07:34:40.24#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.224.07:34:40.30#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.224.07:34:40.30#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.224.07:34:40.30#ibcon#enter wrdev, iclass 4, count 2 2006.224.07:34:40.30#ibcon#first serial, iclass 4, count 2 2006.224.07:34:40.30#ibcon#enter sib2, iclass 4, count 2 2006.224.07:34:40.30#ibcon#flushed, iclass 4, count 2 2006.224.07:34:40.30#ibcon#about to write, iclass 4, count 2 2006.224.07:34:40.30#ibcon#wrote, iclass 4, count 2 2006.224.07:34:40.30#ibcon#about to read 3, iclass 4, count 2 2006.224.07:34:40.32#ibcon#read 3, iclass 4, count 2 2006.224.07:34:40.32#ibcon#about to read 4, iclass 4, count 2 2006.224.07:34:40.32#ibcon#read 4, iclass 4, count 2 2006.224.07:34:40.32#ibcon#about to read 5, iclass 4, count 2 2006.224.07:34:40.32#ibcon#read 5, iclass 4, count 2 2006.224.07:34:40.32#ibcon#about to read 6, iclass 4, count 2 2006.224.07:34:40.32#ibcon#read 6, iclass 4, count 2 2006.224.07:34:40.32#ibcon#end of sib2, iclass 4, count 2 2006.224.07:34:40.32#ibcon#*mode == 0, iclass 4, count 2 2006.224.07:34:40.32#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.224.07:34:40.32#ibcon#[25=AT08-07\r\n] 2006.224.07:34:40.32#ibcon#*before write, iclass 4, count 2 2006.224.07:34:40.32#ibcon#enter sib2, iclass 4, count 2 2006.224.07:34:40.32#ibcon#flushed, iclass 4, count 2 2006.224.07:34:40.32#ibcon#about to write, iclass 4, count 2 2006.224.07:34:40.32#ibcon#wrote, iclass 4, count 2 2006.224.07:34:40.32#ibcon#about to read 3, iclass 4, count 2 2006.224.07:34:40.35#ibcon#read 3, iclass 4, count 2 2006.224.07:34:40.35#ibcon#about to read 4, iclass 4, count 2 2006.224.07:34:40.35#ibcon#read 4, iclass 4, count 2 2006.224.07:34:40.35#ibcon#about to read 5, iclass 4, count 2 2006.224.07:34:40.35#ibcon#read 5, iclass 4, count 2 2006.224.07:34:40.35#ibcon#about to read 6, iclass 4, count 2 2006.224.07:34:40.35#ibcon#read 6, iclass 4, count 2 2006.224.07:34:40.35#ibcon#end of sib2, iclass 4, count 2 2006.224.07:34:40.35#ibcon#*after write, iclass 4, count 2 2006.224.07:34:40.35#ibcon#*before return 0, iclass 4, count 2 2006.224.07:34:40.35#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.224.07:34:40.35#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.224.07:34:40.35#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.224.07:34:40.35#ibcon#ireg 7 cls_cnt 0 2006.224.07:34:40.35#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.224.07:34:40.47#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.224.07:34:40.47#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.224.07:34:40.47#ibcon#enter wrdev, iclass 4, count 0 2006.224.07:34:40.47#ibcon#first serial, iclass 4, count 0 2006.224.07:34:40.47#ibcon#enter sib2, iclass 4, count 0 2006.224.07:34:40.47#ibcon#flushed, iclass 4, count 0 2006.224.07:34:40.47#ibcon#about to write, iclass 4, count 0 2006.224.07:34:40.47#ibcon#wrote, iclass 4, count 0 2006.224.07:34:40.47#ibcon#about to read 3, iclass 4, count 0 2006.224.07:34:40.49#ibcon#read 3, iclass 4, count 0 2006.224.07:34:40.49#ibcon#about to read 4, iclass 4, count 0 2006.224.07:34:40.49#ibcon#read 4, iclass 4, count 0 2006.224.07:34:40.49#ibcon#about to read 5, iclass 4, count 0 2006.224.07:34:40.49#ibcon#read 5, iclass 4, count 0 2006.224.07:34:40.49#ibcon#about to read 6, iclass 4, count 0 2006.224.07:34:40.49#ibcon#read 6, iclass 4, count 0 2006.224.07:34:40.49#ibcon#end of sib2, iclass 4, count 0 2006.224.07:34:40.49#ibcon#*mode == 0, iclass 4, count 0 2006.224.07:34:40.49#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.224.07:34:40.49#ibcon#[25=USB\r\n] 2006.224.07:34:40.49#ibcon#*before write, iclass 4, count 0 2006.224.07:34:40.49#ibcon#enter sib2, iclass 4, count 0 2006.224.07:34:40.49#ibcon#flushed, iclass 4, count 0 2006.224.07:34:40.49#ibcon#about to write, iclass 4, count 0 2006.224.07:34:40.49#ibcon#wrote, iclass 4, count 0 2006.224.07:34:40.49#ibcon#about to read 3, iclass 4, count 0 2006.224.07:34:40.52#ibcon#read 3, iclass 4, count 0 2006.224.07:34:40.52#ibcon#about to read 4, iclass 4, count 0 2006.224.07:34:40.52#ibcon#read 4, iclass 4, count 0 2006.224.07:34:40.52#ibcon#about to read 5, iclass 4, count 0 2006.224.07:34:40.52#ibcon#read 5, iclass 4, count 0 2006.224.07:34:40.52#ibcon#about to read 6, iclass 4, count 0 2006.224.07:34:40.52#ibcon#read 6, iclass 4, count 0 2006.224.07:34:40.52#ibcon#end of sib2, iclass 4, count 0 2006.224.07:34:40.52#ibcon#*after write, iclass 4, count 0 2006.224.07:34:40.52#ibcon#*before return 0, iclass 4, count 0 2006.224.07:34:40.52#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.224.07:34:40.52#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.224.07:34:40.52#ibcon#about to clear, iclass 4 cls_cnt 0 2006.224.07:34:40.52#ibcon#cleared, iclass 4 cls_cnt 0 2006.224.07:34:40.52$vc4f8/vblo=1,632.99 2006.224.07:34:40.52#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.224.07:34:40.52#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.224.07:34:40.52#ibcon#ireg 17 cls_cnt 0 2006.224.07:34:40.52#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.224.07:34:40.52#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.224.07:34:40.52#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.224.07:34:40.52#ibcon#enter wrdev, iclass 6, count 0 2006.224.07:34:40.52#ibcon#first serial, iclass 6, count 0 2006.224.07:34:40.52#ibcon#enter sib2, iclass 6, count 0 2006.224.07:34:40.52#ibcon#flushed, iclass 6, count 0 2006.224.07:34:40.52#ibcon#about to write, iclass 6, count 0 2006.224.07:34:40.52#ibcon#wrote, iclass 6, count 0 2006.224.07:34:40.52#ibcon#about to read 3, iclass 6, count 0 2006.224.07:34:40.54#ibcon#read 3, iclass 6, count 0 2006.224.07:34:40.54#ibcon#about to read 4, iclass 6, count 0 2006.224.07:34:40.54#ibcon#read 4, iclass 6, count 0 2006.224.07:34:40.54#ibcon#about to read 5, iclass 6, count 0 2006.224.07:34:40.54#ibcon#read 5, iclass 6, count 0 2006.224.07:34:40.54#ibcon#about to read 6, iclass 6, count 0 2006.224.07:34:40.54#ibcon#read 6, iclass 6, count 0 2006.224.07:34:40.54#ibcon#end of sib2, iclass 6, count 0 2006.224.07:34:40.54#ibcon#*mode == 0, iclass 6, count 0 2006.224.07:34:40.54#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.224.07:34:40.54#ibcon#[28=FRQ=01,632.99\r\n] 2006.224.07:34:40.54#ibcon#*before write, iclass 6, count 0 2006.224.07:34:40.54#ibcon#enter sib2, iclass 6, count 0 2006.224.07:34:40.54#ibcon#flushed, iclass 6, count 0 2006.224.07:34:40.54#ibcon#about to write, iclass 6, count 0 2006.224.07:34:40.54#ibcon#wrote, iclass 6, count 0 2006.224.07:34:40.54#ibcon#about to read 3, iclass 6, count 0 2006.224.07:34:40.59#ibcon#read 3, iclass 6, count 0 2006.224.07:34:40.59#ibcon#about to read 4, iclass 6, count 0 2006.224.07:34:40.59#ibcon#read 4, iclass 6, count 0 2006.224.07:34:40.59#ibcon#about to read 5, iclass 6, count 0 2006.224.07:34:40.59#ibcon#read 5, iclass 6, count 0 2006.224.07:34:40.59#ibcon#about to read 6, iclass 6, count 0 2006.224.07:34:40.59#ibcon#read 6, iclass 6, count 0 2006.224.07:34:40.59#ibcon#end of sib2, iclass 6, count 0 2006.224.07:34:40.59#ibcon#*after write, iclass 6, count 0 2006.224.07:34:40.59#ibcon#*before return 0, iclass 6, count 0 2006.224.07:34:40.59#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.224.07:34:40.59#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.224.07:34:40.59#ibcon#about to clear, iclass 6 cls_cnt 0 2006.224.07:34:40.59#ibcon#cleared, iclass 6 cls_cnt 0 2006.224.07:34:40.59$vc4f8/vb=1,4 2006.224.07:34:40.59#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.224.07:34:40.59#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.224.07:34:40.59#ibcon#ireg 11 cls_cnt 2 2006.224.07:34:40.59#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.224.07:34:40.59#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.224.07:34:40.59#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.224.07:34:40.59#ibcon#enter wrdev, iclass 10, count 2 2006.224.07:34:40.59#ibcon#first serial, iclass 10, count 2 2006.224.07:34:40.59#ibcon#enter sib2, iclass 10, count 2 2006.224.07:34:40.59#ibcon#flushed, iclass 10, count 2 2006.224.07:34:40.59#ibcon#about to write, iclass 10, count 2 2006.224.07:34:40.59#ibcon#wrote, iclass 10, count 2 2006.224.07:34:40.59#ibcon#about to read 3, iclass 10, count 2 2006.224.07:34:40.61#ibcon#read 3, iclass 10, count 2 2006.224.07:34:40.61#ibcon#about to read 4, iclass 10, count 2 2006.224.07:34:40.61#ibcon#read 4, iclass 10, count 2 2006.224.07:34:40.61#ibcon#about to read 5, iclass 10, count 2 2006.224.07:34:40.61#ibcon#read 5, iclass 10, count 2 2006.224.07:34:40.61#ibcon#about to read 6, iclass 10, count 2 2006.224.07:34:40.61#ibcon#read 6, iclass 10, count 2 2006.224.07:34:40.61#ibcon#end of sib2, iclass 10, count 2 2006.224.07:34:40.61#ibcon#*mode == 0, iclass 10, count 2 2006.224.07:34:40.61#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.224.07:34:40.61#ibcon#[27=AT01-04\r\n] 2006.224.07:34:40.61#ibcon#*before write, iclass 10, count 2 2006.224.07:34:40.61#ibcon#enter sib2, iclass 10, count 2 2006.224.07:34:40.61#ibcon#flushed, iclass 10, count 2 2006.224.07:34:40.61#ibcon#about to write, iclass 10, count 2 2006.224.07:34:40.61#ibcon#wrote, iclass 10, count 2 2006.224.07:34:40.61#ibcon#about to read 3, iclass 10, count 2 2006.224.07:34:40.64#ibcon#read 3, iclass 10, count 2 2006.224.07:34:40.64#ibcon#about to read 4, iclass 10, count 2 2006.224.07:34:40.64#ibcon#read 4, iclass 10, count 2 2006.224.07:34:40.64#ibcon#about to read 5, iclass 10, count 2 2006.224.07:34:40.64#ibcon#read 5, iclass 10, count 2 2006.224.07:34:40.64#ibcon#about to read 6, iclass 10, count 2 2006.224.07:34:40.64#ibcon#read 6, iclass 10, count 2 2006.224.07:34:40.64#ibcon#end of sib2, iclass 10, count 2 2006.224.07:34:40.64#ibcon#*after write, iclass 10, count 2 2006.224.07:34:40.64#ibcon#*before return 0, iclass 10, count 2 2006.224.07:34:40.64#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.224.07:34:40.64#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.224.07:34:40.64#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.224.07:34:40.64#ibcon#ireg 7 cls_cnt 0 2006.224.07:34:40.64#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.224.07:34:40.76#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.224.07:34:40.76#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.224.07:34:40.76#ibcon#enter wrdev, iclass 10, count 0 2006.224.07:34:40.76#ibcon#first serial, iclass 10, count 0 2006.224.07:34:40.76#ibcon#enter sib2, iclass 10, count 0 2006.224.07:34:40.76#ibcon#flushed, iclass 10, count 0 2006.224.07:34:40.76#ibcon#about to write, iclass 10, count 0 2006.224.07:34:40.76#ibcon#wrote, iclass 10, count 0 2006.224.07:34:40.76#ibcon#about to read 3, iclass 10, count 0 2006.224.07:34:40.78#ibcon#read 3, iclass 10, count 0 2006.224.07:34:40.78#ibcon#about to read 4, iclass 10, count 0 2006.224.07:34:40.78#ibcon#read 4, iclass 10, count 0 2006.224.07:34:40.78#ibcon#about to read 5, iclass 10, count 0 2006.224.07:34:40.78#ibcon#read 5, iclass 10, count 0 2006.224.07:34:40.78#ibcon#about to read 6, iclass 10, count 0 2006.224.07:34:40.78#ibcon#read 6, iclass 10, count 0 2006.224.07:34:40.78#ibcon#end of sib2, iclass 10, count 0 2006.224.07:34:40.78#ibcon#*mode == 0, iclass 10, count 0 2006.224.07:34:40.78#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.224.07:34:40.78#ibcon#[27=USB\r\n] 2006.224.07:34:40.78#ibcon#*before write, iclass 10, count 0 2006.224.07:34:40.78#ibcon#enter sib2, iclass 10, count 0 2006.224.07:34:40.78#ibcon#flushed, iclass 10, count 0 2006.224.07:34:40.78#ibcon#about to write, iclass 10, count 0 2006.224.07:34:40.78#ibcon#wrote, iclass 10, count 0 2006.224.07:34:40.78#ibcon#about to read 3, iclass 10, count 0 2006.224.07:34:40.81#ibcon#read 3, iclass 10, count 0 2006.224.07:34:40.81#ibcon#about to read 4, iclass 10, count 0 2006.224.07:34:40.81#ibcon#read 4, iclass 10, count 0 2006.224.07:34:40.81#ibcon#about to read 5, iclass 10, count 0 2006.224.07:34:40.81#ibcon#read 5, iclass 10, count 0 2006.224.07:34:40.81#ibcon#about to read 6, iclass 10, count 0 2006.224.07:34:40.81#ibcon#read 6, iclass 10, count 0 2006.224.07:34:40.81#ibcon#end of sib2, iclass 10, count 0 2006.224.07:34:40.81#ibcon#*after write, iclass 10, count 0 2006.224.07:34:40.81#ibcon#*before return 0, iclass 10, count 0 2006.224.07:34:40.81#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.224.07:34:40.81#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.224.07:34:40.81#ibcon#about to clear, iclass 10 cls_cnt 0 2006.224.07:34:40.81#ibcon#cleared, iclass 10 cls_cnt 0 2006.224.07:34:40.81$vc4f8/vblo=2,640.99 2006.224.07:34:40.81#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.224.07:34:40.81#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.224.07:34:40.81#ibcon#ireg 17 cls_cnt 0 2006.224.07:34:40.81#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.224.07:34:40.81#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.224.07:34:40.81#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.224.07:34:40.81#ibcon#enter wrdev, iclass 12, count 0 2006.224.07:34:40.81#ibcon#first serial, iclass 12, count 0 2006.224.07:34:40.81#ibcon#enter sib2, iclass 12, count 0 2006.224.07:34:40.81#ibcon#flushed, iclass 12, count 0 2006.224.07:34:40.81#ibcon#about to write, iclass 12, count 0 2006.224.07:34:40.81#ibcon#wrote, iclass 12, count 0 2006.224.07:34:40.81#ibcon#about to read 3, iclass 12, count 0 2006.224.07:34:40.83#ibcon#read 3, iclass 12, count 0 2006.224.07:34:40.83#ibcon#about to read 4, iclass 12, count 0 2006.224.07:34:40.83#ibcon#read 4, iclass 12, count 0 2006.224.07:34:40.83#ibcon#about to read 5, iclass 12, count 0 2006.224.07:34:40.83#ibcon#read 5, iclass 12, count 0 2006.224.07:34:40.83#ibcon#about to read 6, iclass 12, count 0 2006.224.07:34:40.83#ibcon#read 6, iclass 12, count 0 2006.224.07:34:40.83#ibcon#end of sib2, iclass 12, count 0 2006.224.07:34:40.83#ibcon#*mode == 0, iclass 12, count 0 2006.224.07:34:40.83#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.224.07:34:40.83#ibcon#[28=FRQ=02,640.99\r\n] 2006.224.07:34:40.83#ibcon#*before write, iclass 12, count 0 2006.224.07:34:40.83#ibcon#enter sib2, iclass 12, count 0 2006.224.07:34:40.83#ibcon#flushed, iclass 12, count 0 2006.224.07:34:40.83#ibcon#about to write, iclass 12, count 0 2006.224.07:34:40.83#ibcon#wrote, iclass 12, count 0 2006.224.07:34:40.83#ibcon#about to read 3, iclass 12, count 0 2006.224.07:34:40.87#ibcon#read 3, iclass 12, count 0 2006.224.07:34:40.87#ibcon#about to read 4, iclass 12, count 0 2006.224.07:34:40.87#ibcon#read 4, iclass 12, count 0 2006.224.07:34:40.87#ibcon#about to read 5, iclass 12, count 0 2006.224.07:34:40.87#ibcon#read 5, iclass 12, count 0 2006.224.07:34:40.87#ibcon#about to read 6, iclass 12, count 0 2006.224.07:34:40.87#ibcon#read 6, iclass 12, count 0 2006.224.07:34:40.87#ibcon#end of sib2, iclass 12, count 0 2006.224.07:34:40.87#ibcon#*after write, iclass 12, count 0 2006.224.07:34:40.87#ibcon#*before return 0, iclass 12, count 0 2006.224.07:34:40.87#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.224.07:34:40.87#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.224.07:34:40.87#ibcon#about to clear, iclass 12 cls_cnt 0 2006.224.07:34:40.87#ibcon#cleared, iclass 12 cls_cnt 0 2006.224.07:34:40.87$vc4f8/vb=2,4 2006.224.07:34:40.87#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.224.07:34:40.87#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.224.07:34:40.87#ibcon#ireg 11 cls_cnt 2 2006.224.07:34:40.87#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.224.07:34:40.93#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.224.07:34:40.93#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.224.07:34:40.93#ibcon#enter wrdev, iclass 14, count 2 2006.224.07:34:40.93#ibcon#first serial, iclass 14, count 2 2006.224.07:34:40.93#ibcon#enter sib2, iclass 14, count 2 2006.224.07:34:40.93#ibcon#flushed, iclass 14, count 2 2006.224.07:34:40.93#ibcon#about to write, iclass 14, count 2 2006.224.07:34:40.93#ibcon#wrote, iclass 14, count 2 2006.224.07:34:40.93#ibcon#about to read 3, iclass 14, count 2 2006.224.07:34:40.95#ibcon#read 3, iclass 14, count 2 2006.224.07:34:40.95#ibcon#about to read 4, iclass 14, count 2 2006.224.07:34:40.95#ibcon#read 4, iclass 14, count 2 2006.224.07:34:40.95#ibcon#about to read 5, iclass 14, count 2 2006.224.07:34:40.95#ibcon#read 5, iclass 14, count 2 2006.224.07:34:40.95#ibcon#about to read 6, iclass 14, count 2 2006.224.07:34:40.95#ibcon#read 6, iclass 14, count 2 2006.224.07:34:40.95#ibcon#end of sib2, iclass 14, count 2 2006.224.07:34:40.95#ibcon#*mode == 0, iclass 14, count 2 2006.224.07:34:40.95#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.224.07:34:40.95#ibcon#[27=AT02-04\r\n] 2006.224.07:34:40.95#ibcon#*before write, iclass 14, count 2 2006.224.07:34:40.95#ibcon#enter sib2, iclass 14, count 2 2006.224.07:34:40.95#ibcon#flushed, iclass 14, count 2 2006.224.07:34:40.95#ibcon#about to write, iclass 14, count 2 2006.224.07:34:40.95#ibcon#wrote, iclass 14, count 2 2006.224.07:34:40.95#ibcon#about to read 3, iclass 14, count 2 2006.224.07:34:40.98#ibcon#read 3, iclass 14, count 2 2006.224.07:34:40.98#ibcon#about to read 4, iclass 14, count 2 2006.224.07:34:40.98#ibcon#read 4, iclass 14, count 2 2006.224.07:34:40.98#ibcon#about to read 5, iclass 14, count 2 2006.224.07:34:40.98#ibcon#read 5, iclass 14, count 2 2006.224.07:34:40.98#ibcon#about to read 6, iclass 14, count 2 2006.224.07:34:40.98#ibcon#read 6, iclass 14, count 2 2006.224.07:34:40.98#ibcon#end of sib2, iclass 14, count 2 2006.224.07:34:40.98#ibcon#*after write, iclass 14, count 2 2006.224.07:34:40.98#ibcon#*before return 0, iclass 14, count 2 2006.224.07:34:40.98#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.224.07:34:40.98#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.224.07:34:40.98#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.224.07:34:40.98#ibcon#ireg 7 cls_cnt 0 2006.224.07:34:40.98#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.224.07:34:41.10#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.224.07:34:41.10#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.224.07:34:41.10#ibcon#enter wrdev, iclass 14, count 0 2006.224.07:34:41.10#ibcon#first serial, iclass 14, count 0 2006.224.07:34:41.10#ibcon#enter sib2, iclass 14, count 0 2006.224.07:34:41.10#ibcon#flushed, iclass 14, count 0 2006.224.07:34:41.10#ibcon#about to write, iclass 14, count 0 2006.224.07:34:41.10#ibcon#wrote, iclass 14, count 0 2006.224.07:34:41.10#ibcon#about to read 3, iclass 14, count 0 2006.224.07:34:41.12#ibcon#read 3, iclass 14, count 0 2006.224.07:34:41.12#ibcon#about to read 4, iclass 14, count 0 2006.224.07:34:41.12#ibcon#read 4, iclass 14, count 0 2006.224.07:34:41.12#ibcon#about to read 5, iclass 14, count 0 2006.224.07:34:41.12#ibcon#read 5, iclass 14, count 0 2006.224.07:34:41.12#ibcon#about to read 6, iclass 14, count 0 2006.224.07:34:41.12#ibcon#read 6, iclass 14, count 0 2006.224.07:34:41.12#ibcon#end of sib2, iclass 14, count 0 2006.224.07:34:41.12#ibcon#*mode == 0, iclass 14, count 0 2006.224.07:34:41.12#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.224.07:34:41.12#ibcon#[27=USB\r\n] 2006.224.07:34:41.12#ibcon#*before write, iclass 14, count 0 2006.224.07:34:41.12#ibcon#enter sib2, iclass 14, count 0 2006.224.07:34:41.12#ibcon#flushed, iclass 14, count 0 2006.224.07:34:41.12#ibcon#about to write, iclass 14, count 0 2006.224.07:34:41.12#ibcon#wrote, iclass 14, count 0 2006.224.07:34:41.12#ibcon#about to read 3, iclass 14, count 0 2006.224.07:34:41.15#ibcon#read 3, iclass 14, count 0 2006.224.07:34:41.15#ibcon#about to read 4, iclass 14, count 0 2006.224.07:34:41.15#ibcon#read 4, iclass 14, count 0 2006.224.07:34:41.15#ibcon#about to read 5, iclass 14, count 0 2006.224.07:34:41.15#ibcon#read 5, iclass 14, count 0 2006.224.07:34:41.15#ibcon#about to read 6, iclass 14, count 0 2006.224.07:34:41.15#ibcon#read 6, iclass 14, count 0 2006.224.07:34:41.15#ibcon#end of sib2, iclass 14, count 0 2006.224.07:34:41.15#ibcon#*after write, iclass 14, count 0 2006.224.07:34:41.15#ibcon#*before return 0, iclass 14, count 0 2006.224.07:34:41.15#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.224.07:34:41.15#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.224.07:34:41.15#ibcon#about to clear, iclass 14 cls_cnt 0 2006.224.07:34:41.15#ibcon#cleared, iclass 14 cls_cnt 0 2006.224.07:34:41.15$vc4f8/vblo=3,656.99 2006.224.07:34:41.15#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.224.07:34:41.15#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.224.07:34:41.15#ibcon#ireg 17 cls_cnt 0 2006.224.07:34:41.15#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.224.07:34:41.15#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.224.07:34:41.15#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.224.07:34:41.15#ibcon#enter wrdev, iclass 16, count 0 2006.224.07:34:41.15#ibcon#first serial, iclass 16, count 0 2006.224.07:34:41.15#ibcon#enter sib2, iclass 16, count 0 2006.224.07:34:41.15#ibcon#flushed, iclass 16, count 0 2006.224.07:34:41.15#ibcon#about to write, iclass 16, count 0 2006.224.07:34:41.15#ibcon#wrote, iclass 16, count 0 2006.224.07:34:41.15#ibcon#about to read 3, iclass 16, count 0 2006.224.07:34:41.17#ibcon#read 3, iclass 16, count 0 2006.224.07:34:41.17#ibcon#about to read 4, iclass 16, count 0 2006.224.07:34:41.17#ibcon#read 4, iclass 16, count 0 2006.224.07:34:41.17#ibcon#about to read 5, iclass 16, count 0 2006.224.07:34:41.17#ibcon#read 5, iclass 16, count 0 2006.224.07:34:41.17#ibcon#about to read 6, iclass 16, count 0 2006.224.07:34:41.17#ibcon#read 6, iclass 16, count 0 2006.224.07:34:41.17#ibcon#end of sib2, iclass 16, count 0 2006.224.07:34:41.17#ibcon#*mode == 0, iclass 16, count 0 2006.224.07:34:41.17#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.224.07:34:41.17#ibcon#[28=FRQ=03,656.99\r\n] 2006.224.07:34:41.17#ibcon#*before write, iclass 16, count 0 2006.224.07:34:41.17#ibcon#enter sib2, iclass 16, count 0 2006.224.07:34:41.17#ibcon#flushed, iclass 16, count 0 2006.224.07:34:41.17#ibcon#about to write, iclass 16, count 0 2006.224.07:34:41.17#ibcon#wrote, iclass 16, count 0 2006.224.07:34:41.17#ibcon#about to read 3, iclass 16, count 0 2006.224.07:34:41.21#ibcon#read 3, iclass 16, count 0 2006.224.07:34:41.21#ibcon#about to read 4, iclass 16, count 0 2006.224.07:34:41.21#ibcon#read 4, iclass 16, count 0 2006.224.07:34:41.21#ibcon#about to read 5, iclass 16, count 0 2006.224.07:34:41.21#ibcon#read 5, iclass 16, count 0 2006.224.07:34:41.21#ibcon#about to read 6, iclass 16, count 0 2006.224.07:34:41.21#ibcon#read 6, iclass 16, count 0 2006.224.07:34:41.21#ibcon#end of sib2, iclass 16, count 0 2006.224.07:34:41.21#ibcon#*after write, iclass 16, count 0 2006.224.07:34:41.21#ibcon#*before return 0, iclass 16, count 0 2006.224.07:34:41.21#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.224.07:34:41.21#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.224.07:34:41.21#ibcon#about to clear, iclass 16 cls_cnt 0 2006.224.07:34:41.21#ibcon#cleared, iclass 16 cls_cnt 0 2006.224.07:34:41.21$vc4f8/vb=3,4 2006.224.07:34:41.21#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.224.07:34:41.21#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.224.07:34:41.21#ibcon#ireg 11 cls_cnt 2 2006.224.07:34:41.21#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.224.07:34:41.27#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.224.07:34:41.27#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.224.07:34:41.27#ibcon#enter wrdev, iclass 18, count 2 2006.224.07:34:41.27#ibcon#first serial, iclass 18, count 2 2006.224.07:34:41.27#ibcon#enter sib2, iclass 18, count 2 2006.224.07:34:41.27#ibcon#flushed, iclass 18, count 2 2006.224.07:34:41.27#ibcon#about to write, iclass 18, count 2 2006.224.07:34:41.27#ibcon#wrote, iclass 18, count 2 2006.224.07:34:41.27#ibcon#about to read 3, iclass 18, count 2 2006.224.07:34:41.29#ibcon#read 3, iclass 18, count 2 2006.224.07:34:41.29#ibcon#about to read 4, iclass 18, count 2 2006.224.07:34:41.29#ibcon#read 4, iclass 18, count 2 2006.224.07:34:41.29#ibcon#about to read 5, iclass 18, count 2 2006.224.07:34:41.29#ibcon#read 5, iclass 18, count 2 2006.224.07:34:41.29#ibcon#about to read 6, iclass 18, count 2 2006.224.07:34:41.29#ibcon#read 6, iclass 18, count 2 2006.224.07:34:41.29#ibcon#end of sib2, iclass 18, count 2 2006.224.07:34:41.29#ibcon#*mode == 0, iclass 18, count 2 2006.224.07:34:41.29#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.224.07:34:41.29#ibcon#[27=AT03-04\r\n] 2006.224.07:34:41.29#ibcon#*before write, iclass 18, count 2 2006.224.07:34:41.29#ibcon#enter sib2, iclass 18, count 2 2006.224.07:34:41.29#ibcon#flushed, iclass 18, count 2 2006.224.07:34:41.29#ibcon#about to write, iclass 18, count 2 2006.224.07:34:41.29#ibcon#wrote, iclass 18, count 2 2006.224.07:34:41.29#ibcon#about to read 3, iclass 18, count 2 2006.224.07:34:41.32#ibcon#read 3, iclass 18, count 2 2006.224.07:34:41.32#ibcon#about to read 4, iclass 18, count 2 2006.224.07:34:41.32#ibcon#read 4, iclass 18, count 2 2006.224.07:34:41.32#ibcon#about to read 5, iclass 18, count 2 2006.224.07:34:41.32#ibcon#read 5, iclass 18, count 2 2006.224.07:34:41.32#ibcon#about to read 6, iclass 18, count 2 2006.224.07:34:41.32#ibcon#read 6, iclass 18, count 2 2006.224.07:34:41.32#ibcon#end of sib2, iclass 18, count 2 2006.224.07:34:41.32#ibcon#*after write, iclass 18, count 2 2006.224.07:34:41.32#ibcon#*before return 0, iclass 18, count 2 2006.224.07:34:41.32#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.224.07:34:41.32#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.224.07:34:41.32#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.224.07:34:41.32#ibcon#ireg 7 cls_cnt 0 2006.224.07:34:41.32#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.224.07:34:41.44#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.224.07:34:41.44#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.224.07:34:41.44#ibcon#enter wrdev, iclass 18, count 0 2006.224.07:34:41.44#ibcon#first serial, iclass 18, count 0 2006.224.07:34:41.44#ibcon#enter sib2, iclass 18, count 0 2006.224.07:34:41.44#ibcon#flushed, iclass 18, count 0 2006.224.07:34:41.44#ibcon#about to write, iclass 18, count 0 2006.224.07:34:41.44#ibcon#wrote, iclass 18, count 0 2006.224.07:34:41.44#ibcon#about to read 3, iclass 18, count 0 2006.224.07:34:41.46#ibcon#read 3, iclass 18, count 0 2006.224.07:34:41.46#ibcon#about to read 4, iclass 18, count 0 2006.224.07:34:41.46#ibcon#read 4, iclass 18, count 0 2006.224.07:34:41.46#ibcon#about to read 5, iclass 18, count 0 2006.224.07:34:41.46#ibcon#read 5, iclass 18, count 0 2006.224.07:34:41.46#ibcon#about to read 6, iclass 18, count 0 2006.224.07:34:41.46#ibcon#read 6, iclass 18, count 0 2006.224.07:34:41.46#ibcon#end of sib2, iclass 18, count 0 2006.224.07:34:41.46#ibcon#*mode == 0, iclass 18, count 0 2006.224.07:34:41.46#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.224.07:34:41.46#ibcon#[27=USB\r\n] 2006.224.07:34:41.46#ibcon#*before write, iclass 18, count 0 2006.224.07:34:41.46#ibcon#enter sib2, iclass 18, count 0 2006.224.07:34:41.46#ibcon#flushed, iclass 18, count 0 2006.224.07:34:41.46#ibcon#about to write, iclass 18, count 0 2006.224.07:34:41.46#ibcon#wrote, iclass 18, count 0 2006.224.07:34:41.46#ibcon#about to read 3, iclass 18, count 0 2006.224.07:34:41.49#ibcon#read 3, iclass 18, count 0 2006.224.07:34:41.49#ibcon#about to read 4, iclass 18, count 0 2006.224.07:34:41.49#ibcon#read 4, iclass 18, count 0 2006.224.07:34:41.49#ibcon#about to read 5, iclass 18, count 0 2006.224.07:34:41.49#ibcon#read 5, iclass 18, count 0 2006.224.07:34:41.49#ibcon#about to read 6, iclass 18, count 0 2006.224.07:34:41.49#ibcon#read 6, iclass 18, count 0 2006.224.07:34:41.49#ibcon#end of sib2, iclass 18, count 0 2006.224.07:34:41.49#ibcon#*after write, iclass 18, count 0 2006.224.07:34:41.49#ibcon#*before return 0, iclass 18, count 0 2006.224.07:34:41.49#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.224.07:34:41.49#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.224.07:34:41.49#ibcon#about to clear, iclass 18 cls_cnt 0 2006.224.07:34:41.49#ibcon#cleared, iclass 18 cls_cnt 0 2006.224.07:34:41.49$vc4f8/vblo=4,712.99 2006.224.07:34:41.49#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.224.07:34:41.49#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.224.07:34:41.49#ibcon#ireg 17 cls_cnt 0 2006.224.07:34:41.49#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.224.07:34:41.49#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.224.07:34:41.49#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.224.07:34:41.49#ibcon#enter wrdev, iclass 20, count 0 2006.224.07:34:41.49#ibcon#first serial, iclass 20, count 0 2006.224.07:34:41.49#ibcon#enter sib2, iclass 20, count 0 2006.224.07:34:41.49#ibcon#flushed, iclass 20, count 0 2006.224.07:34:41.49#ibcon#about to write, iclass 20, count 0 2006.224.07:34:41.49#ibcon#wrote, iclass 20, count 0 2006.224.07:34:41.49#ibcon#about to read 3, iclass 20, count 0 2006.224.07:34:41.51#ibcon#read 3, iclass 20, count 0 2006.224.07:34:41.51#ibcon#about to read 4, iclass 20, count 0 2006.224.07:34:41.51#ibcon#read 4, iclass 20, count 0 2006.224.07:34:41.51#ibcon#about to read 5, iclass 20, count 0 2006.224.07:34:41.51#ibcon#read 5, iclass 20, count 0 2006.224.07:34:41.51#ibcon#about to read 6, iclass 20, count 0 2006.224.07:34:41.51#ibcon#read 6, iclass 20, count 0 2006.224.07:34:41.51#ibcon#end of sib2, iclass 20, count 0 2006.224.07:34:41.51#ibcon#*mode == 0, iclass 20, count 0 2006.224.07:34:41.51#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.224.07:34:41.51#ibcon#[28=FRQ=04,712.99\r\n] 2006.224.07:34:41.51#ibcon#*before write, iclass 20, count 0 2006.224.07:34:41.51#ibcon#enter sib2, iclass 20, count 0 2006.224.07:34:41.51#ibcon#flushed, iclass 20, count 0 2006.224.07:34:41.51#ibcon#about to write, iclass 20, count 0 2006.224.07:34:41.51#ibcon#wrote, iclass 20, count 0 2006.224.07:34:41.51#ibcon#about to read 3, iclass 20, count 0 2006.224.07:34:41.55#ibcon#read 3, iclass 20, count 0 2006.224.07:34:41.55#ibcon#about to read 4, iclass 20, count 0 2006.224.07:34:41.55#ibcon#read 4, iclass 20, count 0 2006.224.07:34:41.55#ibcon#about to read 5, iclass 20, count 0 2006.224.07:34:41.55#ibcon#read 5, iclass 20, count 0 2006.224.07:34:41.55#ibcon#about to read 6, iclass 20, count 0 2006.224.07:34:41.55#ibcon#read 6, iclass 20, count 0 2006.224.07:34:41.55#ibcon#end of sib2, iclass 20, count 0 2006.224.07:34:41.55#ibcon#*after write, iclass 20, count 0 2006.224.07:34:41.55#ibcon#*before return 0, iclass 20, count 0 2006.224.07:34:41.55#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.224.07:34:41.55#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.224.07:34:41.55#ibcon#about to clear, iclass 20 cls_cnt 0 2006.224.07:34:41.55#ibcon#cleared, iclass 20 cls_cnt 0 2006.224.07:34:41.55$vc4f8/vb=4,4 2006.224.07:34:41.55#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.224.07:34:41.55#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.224.07:34:41.55#ibcon#ireg 11 cls_cnt 2 2006.224.07:34:41.55#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.224.07:34:41.61#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.224.07:34:41.61#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.224.07:34:41.61#ibcon#enter wrdev, iclass 22, count 2 2006.224.07:34:41.61#ibcon#first serial, iclass 22, count 2 2006.224.07:34:41.61#ibcon#enter sib2, iclass 22, count 2 2006.224.07:34:41.61#ibcon#flushed, iclass 22, count 2 2006.224.07:34:41.61#ibcon#about to write, iclass 22, count 2 2006.224.07:34:41.61#ibcon#wrote, iclass 22, count 2 2006.224.07:34:41.61#ibcon#about to read 3, iclass 22, count 2 2006.224.07:34:41.63#ibcon#read 3, iclass 22, count 2 2006.224.07:34:41.63#ibcon#about to read 4, iclass 22, count 2 2006.224.07:34:41.63#ibcon#read 4, iclass 22, count 2 2006.224.07:34:41.63#ibcon#about to read 5, iclass 22, count 2 2006.224.07:34:41.63#ibcon#read 5, iclass 22, count 2 2006.224.07:34:41.63#ibcon#about to read 6, iclass 22, count 2 2006.224.07:34:41.63#ibcon#read 6, iclass 22, count 2 2006.224.07:34:41.63#ibcon#end of sib2, iclass 22, count 2 2006.224.07:34:41.63#ibcon#*mode == 0, iclass 22, count 2 2006.224.07:34:41.63#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.224.07:34:41.63#ibcon#[27=AT04-04\r\n] 2006.224.07:34:41.63#ibcon#*before write, iclass 22, count 2 2006.224.07:34:41.63#ibcon#enter sib2, iclass 22, count 2 2006.224.07:34:41.63#ibcon#flushed, iclass 22, count 2 2006.224.07:34:41.63#ibcon#about to write, iclass 22, count 2 2006.224.07:34:41.63#ibcon#wrote, iclass 22, count 2 2006.224.07:34:41.63#ibcon#about to read 3, iclass 22, count 2 2006.224.07:34:41.66#ibcon#read 3, iclass 22, count 2 2006.224.07:34:41.66#ibcon#about to read 4, iclass 22, count 2 2006.224.07:34:41.66#ibcon#read 4, iclass 22, count 2 2006.224.07:34:41.66#ibcon#about to read 5, iclass 22, count 2 2006.224.07:34:41.66#ibcon#read 5, iclass 22, count 2 2006.224.07:34:41.66#ibcon#about to read 6, iclass 22, count 2 2006.224.07:34:41.66#ibcon#read 6, iclass 22, count 2 2006.224.07:34:41.66#ibcon#end of sib2, iclass 22, count 2 2006.224.07:34:41.66#ibcon#*after write, iclass 22, count 2 2006.224.07:34:41.66#ibcon#*before return 0, iclass 22, count 2 2006.224.07:34:41.66#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.224.07:34:41.66#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.224.07:34:41.66#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.224.07:34:41.66#ibcon#ireg 7 cls_cnt 0 2006.224.07:34:41.66#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.224.07:34:41.78#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.224.07:34:41.78#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.224.07:34:41.78#ibcon#enter wrdev, iclass 22, count 0 2006.224.07:34:41.78#ibcon#first serial, iclass 22, count 0 2006.224.07:34:41.78#ibcon#enter sib2, iclass 22, count 0 2006.224.07:34:41.78#ibcon#flushed, iclass 22, count 0 2006.224.07:34:41.78#ibcon#about to write, iclass 22, count 0 2006.224.07:34:41.78#ibcon#wrote, iclass 22, count 0 2006.224.07:34:41.78#ibcon#about to read 3, iclass 22, count 0 2006.224.07:34:41.80#ibcon#read 3, iclass 22, count 0 2006.224.07:34:41.80#ibcon#about to read 4, iclass 22, count 0 2006.224.07:34:41.80#ibcon#read 4, iclass 22, count 0 2006.224.07:34:41.80#ibcon#about to read 5, iclass 22, count 0 2006.224.07:34:41.80#ibcon#read 5, iclass 22, count 0 2006.224.07:34:41.80#ibcon#about to read 6, iclass 22, count 0 2006.224.07:34:41.80#ibcon#read 6, iclass 22, count 0 2006.224.07:34:41.80#ibcon#end of sib2, iclass 22, count 0 2006.224.07:34:41.80#ibcon#*mode == 0, iclass 22, count 0 2006.224.07:34:41.80#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.224.07:34:41.80#ibcon#[27=USB\r\n] 2006.224.07:34:41.80#ibcon#*before write, iclass 22, count 0 2006.224.07:34:41.80#ibcon#enter sib2, iclass 22, count 0 2006.224.07:34:41.80#ibcon#flushed, iclass 22, count 0 2006.224.07:34:41.80#ibcon#about to write, iclass 22, count 0 2006.224.07:34:41.80#ibcon#wrote, iclass 22, count 0 2006.224.07:34:41.80#ibcon#about to read 3, iclass 22, count 0 2006.224.07:34:41.83#ibcon#read 3, iclass 22, count 0 2006.224.07:34:41.83#ibcon#about to read 4, iclass 22, count 0 2006.224.07:34:41.83#ibcon#read 4, iclass 22, count 0 2006.224.07:34:41.83#ibcon#about to read 5, iclass 22, count 0 2006.224.07:34:41.83#ibcon#read 5, iclass 22, count 0 2006.224.07:34:41.83#ibcon#about to read 6, iclass 22, count 0 2006.224.07:34:41.83#ibcon#read 6, iclass 22, count 0 2006.224.07:34:41.83#ibcon#end of sib2, iclass 22, count 0 2006.224.07:34:41.83#ibcon#*after write, iclass 22, count 0 2006.224.07:34:41.83#ibcon#*before return 0, iclass 22, count 0 2006.224.07:34:41.83#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.224.07:34:41.83#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.224.07:34:41.83#ibcon#about to clear, iclass 22 cls_cnt 0 2006.224.07:34:41.83#ibcon#cleared, iclass 22 cls_cnt 0 2006.224.07:34:41.83$vc4f8/vblo=5,744.99 2006.224.07:34:41.83#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.224.07:34:41.83#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.224.07:34:41.83#ibcon#ireg 17 cls_cnt 0 2006.224.07:34:41.83#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.224.07:34:41.83#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.224.07:34:41.83#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.224.07:34:41.83#ibcon#enter wrdev, iclass 24, count 0 2006.224.07:34:41.83#ibcon#first serial, iclass 24, count 0 2006.224.07:34:41.83#ibcon#enter sib2, iclass 24, count 0 2006.224.07:34:41.83#ibcon#flushed, iclass 24, count 0 2006.224.07:34:41.83#ibcon#about to write, iclass 24, count 0 2006.224.07:34:41.83#ibcon#wrote, iclass 24, count 0 2006.224.07:34:41.83#ibcon#about to read 3, iclass 24, count 0 2006.224.07:34:41.85#ibcon#read 3, iclass 24, count 0 2006.224.07:34:41.85#ibcon#about to read 4, iclass 24, count 0 2006.224.07:34:41.85#ibcon#read 4, iclass 24, count 0 2006.224.07:34:41.85#ibcon#about to read 5, iclass 24, count 0 2006.224.07:34:41.85#ibcon#read 5, iclass 24, count 0 2006.224.07:34:41.85#ibcon#about to read 6, iclass 24, count 0 2006.224.07:34:41.85#ibcon#read 6, iclass 24, count 0 2006.224.07:34:41.85#ibcon#end of sib2, iclass 24, count 0 2006.224.07:34:41.85#ibcon#*mode == 0, iclass 24, count 0 2006.224.07:34:41.85#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.224.07:34:41.85#ibcon#[28=FRQ=05,744.99\r\n] 2006.224.07:34:41.85#ibcon#*before write, iclass 24, count 0 2006.224.07:34:41.85#ibcon#enter sib2, iclass 24, count 0 2006.224.07:34:41.85#ibcon#flushed, iclass 24, count 0 2006.224.07:34:41.85#ibcon#about to write, iclass 24, count 0 2006.224.07:34:41.85#ibcon#wrote, iclass 24, count 0 2006.224.07:34:41.85#ibcon#about to read 3, iclass 24, count 0 2006.224.07:34:41.89#ibcon#read 3, iclass 24, count 0 2006.224.07:34:41.89#ibcon#about to read 4, iclass 24, count 0 2006.224.07:34:41.89#ibcon#read 4, iclass 24, count 0 2006.224.07:34:41.89#ibcon#about to read 5, iclass 24, count 0 2006.224.07:34:41.89#ibcon#read 5, iclass 24, count 0 2006.224.07:34:41.89#ibcon#about to read 6, iclass 24, count 0 2006.224.07:34:41.89#ibcon#read 6, iclass 24, count 0 2006.224.07:34:41.89#ibcon#end of sib2, iclass 24, count 0 2006.224.07:34:41.89#ibcon#*after write, iclass 24, count 0 2006.224.07:34:41.89#ibcon#*before return 0, iclass 24, count 0 2006.224.07:34:41.89#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.224.07:34:41.89#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.224.07:34:41.89#ibcon#about to clear, iclass 24 cls_cnt 0 2006.224.07:34:41.89#ibcon#cleared, iclass 24 cls_cnt 0 2006.224.07:34:41.89$vc4f8/vb=5,4 2006.224.07:34:41.89#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.224.07:34:41.89#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.224.07:34:41.89#ibcon#ireg 11 cls_cnt 2 2006.224.07:34:41.89#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.224.07:34:41.95#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.224.07:34:41.95#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.224.07:34:41.95#ibcon#enter wrdev, iclass 26, count 2 2006.224.07:34:41.95#ibcon#first serial, iclass 26, count 2 2006.224.07:34:41.95#ibcon#enter sib2, iclass 26, count 2 2006.224.07:34:41.95#ibcon#flushed, iclass 26, count 2 2006.224.07:34:41.95#ibcon#about to write, iclass 26, count 2 2006.224.07:34:41.95#ibcon#wrote, iclass 26, count 2 2006.224.07:34:41.95#ibcon#about to read 3, iclass 26, count 2 2006.224.07:34:41.97#ibcon#read 3, iclass 26, count 2 2006.224.07:34:41.97#ibcon#about to read 4, iclass 26, count 2 2006.224.07:34:41.97#ibcon#read 4, iclass 26, count 2 2006.224.07:34:41.97#ibcon#about to read 5, iclass 26, count 2 2006.224.07:34:41.97#ibcon#read 5, iclass 26, count 2 2006.224.07:34:41.97#ibcon#about to read 6, iclass 26, count 2 2006.224.07:34:41.97#ibcon#read 6, iclass 26, count 2 2006.224.07:34:41.97#ibcon#end of sib2, iclass 26, count 2 2006.224.07:34:41.97#ibcon#*mode == 0, iclass 26, count 2 2006.224.07:34:41.97#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.224.07:34:41.97#ibcon#[27=AT05-04\r\n] 2006.224.07:34:41.97#ibcon#*before write, iclass 26, count 2 2006.224.07:34:41.97#ibcon#enter sib2, iclass 26, count 2 2006.224.07:34:41.97#ibcon#flushed, iclass 26, count 2 2006.224.07:34:41.97#ibcon#about to write, iclass 26, count 2 2006.224.07:34:41.97#ibcon#wrote, iclass 26, count 2 2006.224.07:34:41.97#ibcon#about to read 3, iclass 26, count 2 2006.224.07:34:42.00#ibcon#read 3, iclass 26, count 2 2006.224.07:34:42.00#ibcon#about to read 4, iclass 26, count 2 2006.224.07:34:42.00#ibcon#read 4, iclass 26, count 2 2006.224.07:34:42.00#ibcon#about to read 5, iclass 26, count 2 2006.224.07:34:42.00#ibcon#read 5, iclass 26, count 2 2006.224.07:34:42.00#ibcon#about to read 6, iclass 26, count 2 2006.224.07:34:42.00#ibcon#read 6, iclass 26, count 2 2006.224.07:34:42.00#ibcon#end of sib2, iclass 26, count 2 2006.224.07:34:42.00#ibcon#*after write, iclass 26, count 2 2006.224.07:34:42.00#ibcon#*before return 0, iclass 26, count 2 2006.224.07:34:42.00#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.224.07:34:42.00#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.224.07:34:42.00#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.224.07:34:42.00#ibcon#ireg 7 cls_cnt 0 2006.224.07:34:42.00#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.224.07:34:42.12#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.224.07:34:42.12#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.224.07:34:42.12#ibcon#enter wrdev, iclass 26, count 0 2006.224.07:34:42.12#ibcon#first serial, iclass 26, count 0 2006.224.07:34:42.12#ibcon#enter sib2, iclass 26, count 0 2006.224.07:34:42.12#ibcon#flushed, iclass 26, count 0 2006.224.07:34:42.12#ibcon#about to write, iclass 26, count 0 2006.224.07:34:42.12#ibcon#wrote, iclass 26, count 0 2006.224.07:34:42.12#ibcon#about to read 3, iclass 26, count 0 2006.224.07:34:42.14#ibcon#read 3, iclass 26, count 0 2006.224.07:34:42.14#ibcon#about to read 4, iclass 26, count 0 2006.224.07:34:42.14#ibcon#read 4, iclass 26, count 0 2006.224.07:34:42.14#ibcon#about to read 5, iclass 26, count 0 2006.224.07:34:42.14#ibcon#read 5, iclass 26, count 0 2006.224.07:34:42.14#ibcon#about to read 6, iclass 26, count 0 2006.224.07:34:42.14#ibcon#read 6, iclass 26, count 0 2006.224.07:34:42.14#ibcon#end of sib2, iclass 26, count 0 2006.224.07:34:42.14#ibcon#*mode == 0, iclass 26, count 0 2006.224.07:34:42.14#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.224.07:34:42.14#ibcon#[27=USB\r\n] 2006.224.07:34:42.14#ibcon#*before write, iclass 26, count 0 2006.224.07:34:42.14#ibcon#enter sib2, iclass 26, count 0 2006.224.07:34:42.14#ibcon#flushed, iclass 26, count 0 2006.224.07:34:42.14#ibcon#about to write, iclass 26, count 0 2006.224.07:34:42.14#ibcon#wrote, iclass 26, count 0 2006.224.07:34:42.14#ibcon#about to read 3, iclass 26, count 0 2006.224.07:34:42.17#ibcon#read 3, iclass 26, count 0 2006.224.07:34:42.17#ibcon#about to read 4, iclass 26, count 0 2006.224.07:34:42.17#ibcon#read 4, iclass 26, count 0 2006.224.07:34:42.17#ibcon#about to read 5, iclass 26, count 0 2006.224.07:34:42.17#ibcon#read 5, iclass 26, count 0 2006.224.07:34:42.17#ibcon#about to read 6, iclass 26, count 0 2006.224.07:34:42.17#ibcon#read 6, iclass 26, count 0 2006.224.07:34:42.17#ibcon#end of sib2, iclass 26, count 0 2006.224.07:34:42.17#ibcon#*after write, iclass 26, count 0 2006.224.07:34:42.17#ibcon#*before return 0, iclass 26, count 0 2006.224.07:34:42.17#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.224.07:34:42.17#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.224.07:34:42.17#ibcon#about to clear, iclass 26 cls_cnt 0 2006.224.07:34:42.17#ibcon#cleared, iclass 26 cls_cnt 0 2006.224.07:34:42.17$vc4f8/vblo=6,752.99 2006.224.07:34:42.17#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.224.07:34:42.17#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.224.07:34:42.17#ibcon#ireg 17 cls_cnt 0 2006.224.07:34:42.17#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.224.07:34:42.17#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.224.07:34:42.17#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.224.07:34:42.17#ibcon#enter wrdev, iclass 28, count 0 2006.224.07:34:42.17#ibcon#first serial, iclass 28, count 0 2006.224.07:34:42.17#ibcon#enter sib2, iclass 28, count 0 2006.224.07:34:42.17#ibcon#flushed, iclass 28, count 0 2006.224.07:34:42.17#ibcon#about to write, iclass 28, count 0 2006.224.07:34:42.17#ibcon#wrote, iclass 28, count 0 2006.224.07:34:42.17#ibcon#about to read 3, iclass 28, count 0 2006.224.07:34:42.19#ibcon#read 3, iclass 28, count 0 2006.224.07:34:42.19#ibcon#about to read 4, iclass 28, count 0 2006.224.07:34:42.19#ibcon#read 4, iclass 28, count 0 2006.224.07:34:42.19#ibcon#about to read 5, iclass 28, count 0 2006.224.07:34:42.19#ibcon#read 5, iclass 28, count 0 2006.224.07:34:42.19#ibcon#about to read 6, iclass 28, count 0 2006.224.07:34:42.19#ibcon#read 6, iclass 28, count 0 2006.224.07:34:42.19#ibcon#end of sib2, iclass 28, count 0 2006.224.07:34:42.19#ibcon#*mode == 0, iclass 28, count 0 2006.224.07:34:42.19#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.224.07:34:42.19#ibcon#[28=FRQ=06,752.99\r\n] 2006.224.07:34:42.19#ibcon#*before write, iclass 28, count 0 2006.224.07:34:42.19#ibcon#enter sib2, iclass 28, count 0 2006.224.07:34:42.19#ibcon#flushed, iclass 28, count 0 2006.224.07:34:42.19#ibcon#about to write, iclass 28, count 0 2006.224.07:34:42.19#ibcon#wrote, iclass 28, count 0 2006.224.07:34:42.19#ibcon#about to read 3, iclass 28, count 0 2006.224.07:34:42.24#ibcon#read 3, iclass 28, count 0 2006.224.07:34:42.24#ibcon#about to read 4, iclass 28, count 0 2006.224.07:34:42.24#ibcon#read 4, iclass 28, count 0 2006.224.07:34:42.24#ibcon#about to read 5, iclass 28, count 0 2006.224.07:34:42.24#ibcon#read 5, iclass 28, count 0 2006.224.07:34:42.24#ibcon#about to read 6, iclass 28, count 0 2006.224.07:34:42.24#ibcon#read 6, iclass 28, count 0 2006.224.07:34:42.24#ibcon#end of sib2, iclass 28, count 0 2006.224.07:34:42.24#ibcon#*after write, iclass 28, count 0 2006.224.07:34:42.24#ibcon#*before return 0, iclass 28, count 0 2006.224.07:34:42.24#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.224.07:34:42.24#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.224.07:34:42.24#ibcon#about to clear, iclass 28 cls_cnt 0 2006.224.07:34:42.24#ibcon#cleared, iclass 28 cls_cnt 0 2006.224.07:34:42.24$vc4f8/vb=6,4 2006.224.07:34:42.24#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.224.07:34:42.24#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.224.07:34:42.24#ibcon#ireg 11 cls_cnt 2 2006.224.07:34:42.24#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.224.07:34:42.29#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.224.07:34:42.29#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.224.07:34:42.29#ibcon#enter wrdev, iclass 30, count 2 2006.224.07:34:42.29#ibcon#first serial, iclass 30, count 2 2006.224.07:34:42.29#ibcon#enter sib2, iclass 30, count 2 2006.224.07:34:42.29#ibcon#flushed, iclass 30, count 2 2006.224.07:34:42.29#ibcon#about to write, iclass 30, count 2 2006.224.07:34:42.29#ibcon#wrote, iclass 30, count 2 2006.224.07:34:42.29#ibcon#about to read 3, iclass 30, count 2 2006.224.07:34:42.31#ibcon#read 3, iclass 30, count 2 2006.224.07:34:42.31#ibcon#about to read 4, iclass 30, count 2 2006.224.07:34:42.31#ibcon#read 4, iclass 30, count 2 2006.224.07:34:42.31#ibcon#about to read 5, iclass 30, count 2 2006.224.07:34:42.31#ibcon#read 5, iclass 30, count 2 2006.224.07:34:42.31#ibcon#about to read 6, iclass 30, count 2 2006.224.07:34:42.31#ibcon#read 6, iclass 30, count 2 2006.224.07:34:42.31#ibcon#end of sib2, iclass 30, count 2 2006.224.07:34:42.31#ibcon#*mode == 0, iclass 30, count 2 2006.224.07:34:42.31#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.224.07:34:42.31#ibcon#[27=AT06-04\r\n] 2006.224.07:34:42.31#ibcon#*before write, iclass 30, count 2 2006.224.07:34:42.31#ibcon#enter sib2, iclass 30, count 2 2006.224.07:34:42.31#ibcon#flushed, iclass 30, count 2 2006.224.07:34:42.31#ibcon#about to write, iclass 30, count 2 2006.224.07:34:42.31#ibcon#wrote, iclass 30, count 2 2006.224.07:34:42.31#ibcon#about to read 3, iclass 30, count 2 2006.224.07:34:42.34#ibcon#read 3, iclass 30, count 2 2006.224.07:34:42.34#ibcon#about to read 4, iclass 30, count 2 2006.224.07:34:42.34#ibcon#read 4, iclass 30, count 2 2006.224.07:34:42.34#ibcon#about to read 5, iclass 30, count 2 2006.224.07:34:42.34#ibcon#read 5, iclass 30, count 2 2006.224.07:34:42.34#ibcon#about to read 6, iclass 30, count 2 2006.224.07:34:42.34#ibcon#read 6, iclass 30, count 2 2006.224.07:34:42.34#ibcon#end of sib2, iclass 30, count 2 2006.224.07:34:42.34#ibcon#*after write, iclass 30, count 2 2006.224.07:34:42.34#ibcon#*before return 0, iclass 30, count 2 2006.224.07:34:42.34#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.224.07:34:42.34#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.224.07:34:42.34#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.224.07:34:42.34#ibcon#ireg 7 cls_cnt 0 2006.224.07:34:42.34#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.224.07:34:42.46#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.224.07:34:42.46#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.224.07:34:42.46#ibcon#enter wrdev, iclass 30, count 0 2006.224.07:34:42.46#ibcon#first serial, iclass 30, count 0 2006.224.07:34:42.46#ibcon#enter sib2, iclass 30, count 0 2006.224.07:34:42.46#ibcon#flushed, iclass 30, count 0 2006.224.07:34:42.46#ibcon#about to write, iclass 30, count 0 2006.224.07:34:42.46#ibcon#wrote, iclass 30, count 0 2006.224.07:34:42.46#ibcon#about to read 3, iclass 30, count 0 2006.224.07:34:42.48#ibcon#read 3, iclass 30, count 0 2006.224.07:34:42.48#ibcon#about to read 4, iclass 30, count 0 2006.224.07:34:42.48#ibcon#read 4, iclass 30, count 0 2006.224.07:34:42.48#ibcon#about to read 5, iclass 30, count 0 2006.224.07:34:42.48#ibcon#read 5, iclass 30, count 0 2006.224.07:34:42.48#ibcon#about to read 6, iclass 30, count 0 2006.224.07:34:42.48#ibcon#read 6, iclass 30, count 0 2006.224.07:34:42.48#ibcon#end of sib2, iclass 30, count 0 2006.224.07:34:42.48#ibcon#*mode == 0, iclass 30, count 0 2006.224.07:34:42.48#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.224.07:34:42.48#ibcon#[27=USB\r\n] 2006.224.07:34:42.48#ibcon#*before write, iclass 30, count 0 2006.224.07:34:42.48#ibcon#enter sib2, iclass 30, count 0 2006.224.07:34:42.48#ibcon#flushed, iclass 30, count 0 2006.224.07:34:42.48#ibcon#about to write, iclass 30, count 0 2006.224.07:34:42.48#ibcon#wrote, iclass 30, count 0 2006.224.07:34:42.48#ibcon#about to read 3, iclass 30, count 0 2006.224.07:34:42.51#ibcon#read 3, iclass 30, count 0 2006.224.07:34:42.51#ibcon#about to read 4, iclass 30, count 0 2006.224.07:34:42.51#ibcon#read 4, iclass 30, count 0 2006.224.07:34:42.51#ibcon#about to read 5, iclass 30, count 0 2006.224.07:34:42.51#ibcon#read 5, iclass 30, count 0 2006.224.07:34:42.51#ibcon#about to read 6, iclass 30, count 0 2006.224.07:34:42.51#ibcon#read 6, iclass 30, count 0 2006.224.07:34:42.51#ibcon#end of sib2, iclass 30, count 0 2006.224.07:34:42.51#ibcon#*after write, iclass 30, count 0 2006.224.07:34:42.51#ibcon#*before return 0, iclass 30, count 0 2006.224.07:34:42.51#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.224.07:34:42.51#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.224.07:34:42.51#ibcon#about to clear, iclass 30 cls_cnt 0 2006.224.07:34:42.51#ibcon#cleared, iclass 30 cls_cnt 0 2006.224.07:34:42.51$vc4f8/vabw=wide 2006.224.07:34:42.51#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.224.07:34:42.51#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.224.07:34:42.51#ibcon#ireg 8 cls_cnt 0 2006.224.07:34:42.51#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.224.07:34:42.51#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.224.07:34:42.51#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.224.07:34:42.51#ibcon#enter wrdev, iclass 32, count 0 2006.224.07:34:42.51#ibcon#first serial, iclass 32, count 0 2006.224.07:34:42.51#ibcon#enter sib2, iclass 32, count 0 2006.224.07:34:42.51#ibcon#flushed, iclass 32, count 0 2006.224.07:34:42.51#ibcon#about to write, iclass 32, count 0 2006.224.07:34:42.51#ibcon#wrote, iclass 32, count 0 2006.224.07:34:42.51#ibcon#about to read 3, iclass 32, count 0 2006.224.07:34:42.53#ibcon#read 3, iclass 32, count 0 2006.224.07:34:42.53#ibcon#about to read 4, iclass 32, count 0 2006.224.07:34:42.53#ibcon#read 4, iclass 32, count 0 2006.224.07:34:42.53#ibcon#about to read 5, iclass 32, count 0 2006.224.07:34:42.53#ibcon#read 5, iclass 32, count 0 2006.224.07:34:42.53#ibcon#about to read 6, iclass 32, count 0 2006.224.07:34:42.53#ibcon#read 6, iclass 32, count 0 2006.224.07:34:42.53#ibcon#end of sib2, iclass 32, count 0 2006.224.07:34:42.53#ibcon#*mode == 0, iclass 32, count 0 2006.224.07:34:42.53#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.224.07:34:42.53#ibcon#[25=BW32\r\n] 2006.224.07:34:42.53#ibcon#*before write, iclass 32, count 0 2006.224.07:34:42.53#ibcon#enter sib2, iclass 32, count 0 2006.224.07:34:42.53#ibcon#flushed, iclass 32, count 0 2006.224.07:34:42.53#ibcon#about to write, iclass 32, count 0 2006.224.07:34:42.53#ibcon#wrote, iclass 32, count 0 2006.224.07:34:42.53#ibcon#about to read 3, iclass 32, count 0 2006.224.07:34:42.56#ibcon#read 3, iclass 32, count 0 2006.224.07:34:42.56#ibcon#about to read 4, iclass 32, count 0 2006.224.07:34:42.56#ibcon#read 4, iclass 32, count 0 2006.224.07:34:42.56#ibcon#about to read 5, iclass 32, count 0 2006.224.07:34:42.56#ibcon#read 5, iclass 32, count 0 2006.224.07:34:42.56#ibcon#about to read 6, iclass 32, count 0 2006.224.07:34:42.56#ibcon#read 6, iclass 32, count 0 2006.224.07:34:42.56#ibcon#end of sib2, iclass 32, count 0 2006.224.07:34:42.56#ibcon#*after write, iclass 32, count 0 2006.224.07:34:42.56#ibcon#*before return 0, iclass 32, count 0 2006.224.07:34:42.56#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.224.07:34:42.56#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.224.07:34:42.56#ibcon#about to clear, iclass 32 cls_cnt 0 2006.224.07:34:42.56#ibcon#cleared, iclass 32 cls_cnt 0 2006.224.07:34:42.56$vc4f8/vbbw=wide 2006.224.07:34:42.56#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.224.07:34:42.56#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.224.07:34:42.56#ibcon#ireg 8 cls_cnt 0 2006.224.07:34:42.56#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.224.07:34:42.63#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.224.07:34:42.63#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.224.07:34:42.63#ibcon#enter wrdev, iclass 34, count 0 2006.224.07:34:42.63#ibcon#first serial, iclass 34, count 0 2006.224.07:34:42.63#ibcon#enter sib2, iclass 34, count 0 2006.224.07:34:42.63#ibcon#flushed, iclass 34, count 0 2006.224.07:34:42.63#ibcon#about to write, iclass 34, count 0 2006.224.07:34:42.63#ibcon#wrote, iclass 34, count 0 2006.224.07:34:42.63#ibcon#about to read 3, iclass 34, count 0 2006.224.07:34:42.65#ibcon#read 3, iclass 34, count 0 2006.224.07:34:42.65#ibcon#about to read 4, iclass 34, count 0 2006.224.07:34:42.65#ibcon#read 4, iclass 34, count 0 2006.224.07:34:42.65#ibcon#about to read 5, iclass 34, count 0 2006.224.07:34:42.65#ibcon#read 5, iclass 34, count 0 2006.224.07:34:42.65#ibcon#about to read 6, iclass 34, count 0 2006.224.07:34:42.65#ibcon#read 6, iclass 34, count 0 2006.224.07:34:42.65#ibcon#end of sib2, iclass 34, count 0 2006.224.07:34:42.65#ibcon#*mode == 0, iclass 34, count 0 2006.224.07:34:42.65#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.224.07:34:42.65#ibcon#[27=BW32\r\n] 2006.224.07:34:42.65#ibcon#*before write, iclass 34, count 0 2006.224.07:34:42.65#ibcon#enter sib2, iclass 34, count 0 2006.224.07:34:42.65#ibcon#flushed, iclass 34, count 0 2006.224.07:34:42.65#ibcon#about to write, iclass 34, count 0 2006.224.07:34:42.65#ibcon#wrote, iclass 34, count 0 2006.224.07:34:42.65#ibcon#about to read 3, iclass 34, count 0 2006.224.07:34:42.68#ibcon#read 3, iclass 34, count 0 2006.224.07:34:42.68#ibcon#about to read 4, iclass 34, count 0 2006.224.07:34:42.68#ibcon#read 4, iclass 34, count 0 2006.224.07:34:42.68#ibcon#about to read 5, iclass 34, count 0 2006.224.07:34:42.68#ibcon#read 5, iclass 34, count 0 2006.224.07:34:42.68#ibcon#about to read 6, iclass 34, count 0 2006.224.07:34:42.68#ibcon#read 6, iclass 34, count 0 2006.224.07:34:42.68#ibcon#end of sib2, iclass 34, count 0 2006.224.07:34:42.68#ibcon#*after write, iclass 34, count 0 2006.224.07:34:42.68#ibcon#*before return 0, iclass 34, count 0 2006.224.07:34:42.68#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.224.07:34:42.68#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.224.07:34:42.68#ibcon#about to clear, iclass 34 cls_cnt 0 2006.224.07:34:42.68#ibcon#cleared, iclass 34 cls_cnt 0 2006.224.07:34:42.68$4f8m12a/ifd4f 2006.224.07:34:42.68$ifd4f/lo= 2006.224.07:34:42.68$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.224.07:34:42.68$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.224.07:34:42.68$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.224.07:34:42.68$ifd4f/patch= 2006.224.07:34:42.68$ifd4f/patch=lo1,a1,a2,a3,a4 2006.224.07:34:42.68$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.224.07:34:42.68$ifd4f/patch=lo3,a5,a6,a7,a8 2006.224.07:34:42.68$4f8m12a/"form=m,16.000,1:2 2006.224.07:34:42.68$4f8m12a/"tpicd 2006.224.07:34:42.68$4f8m12a/echo=off 2006.224.07:34:42.68$4f8m12a/xlog=off 2006.224.07:34:42.68:!2006.224.07:35:10 2006.224.07:34:53.14#trakl#Source acquired 2006.224.07:34:55.14#flagr#flagr/antenna,acquired 2006.224.07:35:10.00:preob 2006.224.07:35:11.14/onsource/TRACKING 2006.224.07:35:11.14:!2006.224.07:35:20 2006.224.07:35:20.00:data_valid=on 2006.224.07:35:20.00:midob 2006.224.07:35:20.14/onsource/TRACKING 2006.224.07:35:20.14/wx/23.36,1004.2,100 2006.224.07:35:20.34/cable/+6.4328E-03 2006.224.07:35:21.43/va/01,08,usb,yes,37,39 2006.224.07:35:21.43/va/02,07,usb,yes,37,39 2006.224.07:35:21.43/va/03,06,usb,yes,40,40 2006.224.07:35:21.43/va/04,07,usb,yes,39,42 2006.224.07:35:21.43/va/05,07,usb,yes,46,49 2006.224.07:35:21.43/va/06,06,usb,yes,46,45 2006.224.07:35:21.43/va/07,06,usb,yes,47,47 2006.224.07:35:21.43/va/08,07,usb,yes,45,44 2006.224.07:35:21.66/valo/01,532.99,yes,locked 2006.224.07:35:21.66/valo/02,572.99,yes,locked 2006.224.07:35:21.66/valo/03,672.99,yes,locked 2006.224.07:35:21.66/valo/04,832.99,yes,locked 2006.224.07:35:21.66/valo/05,652.99,yes,locked 2006.224.07:35:21.66/valo/06,772.99,yes,locked 2006.224.07:35:21.66/valo/07,832.99,yes,locked 2006.224.07:35:21.66/valo/08,852.99,yes,locked 2006.224.07:35:22.75/vb/01,04,usb,yes,31,30 2006.224.07:35:22.75/vb/02,04,usb,yes,33,34 2006.224.07:35:22.75/vb/03,04,usb,yes,29,33 2006.224.07:35:22.75/vb/04,04,usb,yes,30,30 2006.224.07:35:22.75/vb/05,04,usb,yes,29,33 2006.224.07:35:22.75/vb/06,04,usb,yes,30,32 2006.224.07:35:22.75/vb/07,04,usb,yes,32,32 2006.224.07:35:22.75/vb/08,04,usb,yes,29,33 2006.224.07:35:22.98/vblo/01,632.99,yes,locked 2006.224.07:35:22.98/vblo/02,640.99,yes,locked 2006.224.07:35:22.98/vblo/03,656.99,yes,locked 2006.224.07:35:22.98/vblo/04,712.99,yes,locked 2006.224.07:35:22.98/vblo/05,744.99,yes,locked 2006.224.07:35:22.98/vblo/06,752.99,yes,locked 2006.224.07:35:22.98/vblo/07,734.99,yes,locked 2006.224.07:35:22.98/vblo/08,744.99,yes,locked 2006.224.07:35:23.13/vabw/8 2006.224.07:35:23.28/vbbw/8 2006.224.07:35:23.40/xfe/off,on,14.7 2006.224.07:35:23.77/ifatt/23,28,28,28 2006.224.07:35:24.08/fmout-gps/S +4.39E-07 2006.224.07:35:24.12:!2006.224.07:36:20 2006.224.07:36:20.00:data_valid=off 2006.224.07:36:20.00:postob 2006.224.07:36:20.19/cable/+6.4329E-03 2006.224.07:36:20.19/wx/23.37,1004.2,100 2006.224.07:36:21.07/fmout-gps/S +4.39E-07 2006.224.07:36:21.07:scan_name=224-0737,k06224,60 2006.224.07:36:21.07:source=0602+673,060752.67,672055.4,2000.0,ccw 2006.224.07:36:21.14#flagr#flagr/antenna,new-source 2006.224.07:36:22.13:checkk5 2006.224.07:36:22.50/chk_autoobs//k5ts1/ autoobs is running! 2006.224.07:36:22.87/chk_autoobs//k5ts2/ autoobs is running! 2006.224.07:36:23.24/chk_autoobs//k5ts3/ autoobs is running! 2006.224.07:36:23.61/chk_autoobs//k5ts4/ autoobs is running! 2006.224.07:36:23.97/chk_obsdata//k5ts1/T2240735??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.07:36:24.34/chk_obsdata//k5ts2/T2240735??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.07:36:24.71/chk_obsdata//k5ts3/T2240735??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.07:36:25.08/chk_obsdata//k5ts4/T2240735??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.07:36:25.76/k5log//k5ts1_log_newline 2006.224.07:36:26.46/k5log//k5ts2_log_newline 2006.224.07:36:27.14/k5log//k5ts3_log_newline 2006.224.07:36:27.83/k5log//k5ts4_log_newline 2006.224.07:36:27.85/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.224.07:36:27.85:4f8m12a=1 2006.224.07:36:27.85$4f8m12a/echo=on 2006.224.07:36:27.85$4f8m12a/pcalon 2006.224.07:36:27.85$pcalon/"no phase cal control is implemented here 2006.224.07:36:27.85$4f8m12a/"tpicd=stop 2006.224.07:36:27.85$4f8m12a/vc4f8 2006.224.07:36:27.85$vc4f8/valo=1,532.99 2006.224.07:36:27.86#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.224.07:36:27.86#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.224.07:36:27.86#ibcon#ireg 17 cls_cnt 0 2006.224.07:36:27.86#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.224.07:36:27.86#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.224.07:36:27.86#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.224.07:36:27.86#ibcon#enter wrdev, iclass 7, count 0 2006.224.07:36:27.86#ibcon#first serial, iclass 7, count 0 2006.224.07:36:27.86#ibcon#enter sib2, iclass 7, count 0 2006.224.07:36:27.86#ibcon#flushed, iclass 7, count 0 2006.224.07:36:27.86#ibcon#about to write, iclass 7, count 0 2006.224.07:36:27.86#ibcon#wrote, iclass 7, count 0 2006.224.07:36:27.86#ibcon#about to read 3, iclass 7, count 0 2006.224.07:36:27.90#ibcon#read 3, iclass 7, count 0 2006.224.07:36:27.90#ibcon#about to read 4, iclass 7, count 0 2006.224.07:36:27.90#ibcon#read 4, iclass 7, count 0 2006.224.07:36:27.90#ibcon#about to read 5, iclass 7, count 0 2006.224.07:36:27.90#ibcon#read 5, iclass 7, count 0 2006.224.07:36:27.90#ibcon#about to read 6, iclass 7, count 0 2006.224.07:36:27.90#ibcon#read 6, iclass 7, count 0 2006.224.07:36:27.90#ibcon#end of sib2, iclass 7, count 0 2006.224.07:36:27.90#ibcon#*mode == 0, iclass 7, count 0 2006.224.07:36:27.90#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.224.07:36:27.90#ibcon#[26=FRQ=01,532.99\r\n] 2006.224.07:36:27.90#ibcon#*before write, iclass 7, count 0 2006.224.07:36:27.90#ibcon#enter sib2, iclass 7, count 0 2006.224.07:36:27.90#ibcon#flushed, iclass 7, count 0 2006.224.07:36:27.90#ibcon#about to write, iclass 7, count 0 2006.224.07:36:27.90#ibcon#wrote, iclass 7, count 0 2006.224.07:36:27.90#ibcon#about to read 3, iclass 7, count 0 2006.224.07:36:27.95#ibcon#read 3, iclass 7, count 0 2006.224.07:36:27.95#ibcon#about to read 4, iclass 7, count 0 2006.224.07:36:27.95#ibcon#read 4, iclass 7, count 0 2006.224.07:36:27.95#ibcon#about to read 5, iclass 7, count 0 2006.224.07:36:27.95#ibcon#read 5, iclass 7, count 0 2006.224.07:36:27.95#ibcon#about to read 6, iclass 7, count 0 2006.224.07:36:27.95#ibcon#read 6, iclass 7, count 0 2006.224.07:36:27.95#ibcon#end of sib2, iclass 7, count 0 2006.224.07:36:27.95#ibcon#*after write, iclass 7, count 0 2006.224.07:36:27.95#ibcon#*before return 0, iclass 7, count 0 2006.224.07:36:27.95#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.224.07:36:27.95#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.224.07:36:27.95#ibcon#about to clear, iclass 7 cls_cnt 0 2006.224.07:36:27.95#ibcon#cleared, iclass 7 cls_cnt 0 2006.224.07:36:27.95$vc4f8/va=1,8 2006.224.07:36:27.95#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.224.07:36:27.95#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.224.07:36:27.95#ibcon#ireg 11 cls_cnt 2 2006.224.07:36:27.95#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.224.07:36:27.95#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.224.07:36:27.95#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.224.07:36:27.95#ibcon#enter wrdev, iclass 11, count 2 2006.224.07:36:27.95#ibcon#first serial, iclass 11, count 2 2006.224.07:36:27.95#ibcon#enter sib2, iclass 11, count 2 2006.224.07:36:27.95#ibcon#flushed, iclass 11, count 2 2006.224.07:36:27.95#ibcon#about to write, iclass 11, count 2 2006.224.07:36:27.95#ibcon#wrote, iclass 11, count 2 2006.224.07:36:27.95#ibcon#about to read 3, iclass 11, count 2 2006.224.07:36:27.97#ibcon#read 3, iclass 11, count 2 2006.224.07:36:27.97#ibcon#about to read 4, iclass 11, count 2 2006.224.07:36:27.97#ibcon#read 4, iclass 11, count 2 2006.224.07:36:27.97#ibcon#about to read 5, iclass 11, count 2 2006.224.07:36:27.97#ibcon#read 5, iclass 11, count 2 2006.224.07:36:27.97#ibcon#about to read 6, iclass 11, count 2 2006.224.07:36:27.97#ibcon#read 6, iclass 11, count 2 2006.224.07:36:27.97#ibcon#end of sib2, iclass 11, count 2 2006.224.07:36:27.97#ibcon#*mode == 0, iclass 11, count 2 2006.224.07:36:27.97#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.224.07:36:27.97#ibcon#[25=AT01-08\r\n] 2006.224.07:36:27.97#ibcon#*before write, iclass 11, count 2 2006.224.07:36:27.97#ibcon#enter sib2, iclass 11, count 2 2006.224.07:36:27.97#ibcon#flushed, iclass 11, count 2 2006.224.07:36:27.97#ibcon#about to write, iclass 11, count 2 2006.224.07:36:27.97#ibcon#wrote, iclass 11, count 2 2006.224.07:36:27.97#ibcon#about to read 3, iclass 11, count 2 2006.224.07:36:28.01#ibcon#read 3, iclass 11, count 2 2006.224.07:36:28.01#ibcon#about to read 4, iclass 11, count 2 2006.224.07:36:28.01#ibcon#read 4, iclass 11, count 2 2006.224.07:36:28.01#ibcon#about to read 5, iclass 11, count 2 2006.224.07:36:28.01#ibcon#read 5, iclass 11, count 2 2006.224.07:36:28.01#ibcon#about to read 6, iclass 11, count 2 2006.224.07:36:28.01#ibcon#read 6, iclass 11, count 2 2006.224.07:36:28.01#ibcon#end of sib2, iclass 11, count 2 2006.224.07:36:28.01#ibcon#*after write, iclass 11, count 2 2006.224.07:36:28.01#ibcon#*before return 0, iclass 11, count 2 2006.224.07:36:28.01#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.224.07:36:28.01#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.224.07:36:28.01#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.224.07:36:28.01#ibcon#ireg 7 cls_cnt 0 2006.224.07:36:28.01#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.224.07:36:28.13#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.224.07:36:28.13#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.224.07:36:28.13#ibcon#enter wrdev, iclass 11, count 0 2006.224.07:36:28.13#ibcon#first serial, iclass 11, count 0 2006.224.07:36:28.13#ibcon#enter sib2, iclass 11, count 0 2006.224.07:36:28.13#ibcon#flushed, iclass 11, count 0 2006.224.07:36:28.13#ibcon#about to write, iclass 11, count 0 2006.224.07:36:28.13#ibcon#wrote, iclass 11, count 0 2006.224.07:36:28.13#ibcon#about to read 3, iclass 11, count 0 2006.224.07:36:28.15#ibcon#read 3, iclass 11, count 0 2006.224.07:36:28.15#ibcon#about to read 4, iclass 11, count 0 2006.224.07:36:28.15#ibcon#read 4, iclass 11, count 0 2006.224.07:36:28.15#ibcon#about to read 5, iclass 11, count 0 2006.224.07:36:28.15#ibcon#read 5, iclass 11, count 0 2006.224.07:36:28.15#ibcon#about to read 6, iclass 11, count 0 2006.224.07:36:28.15#ibcon#read 6, iclass 11, count 0 2006.224.07:36:28.15#ibcon#end of sib2, iclass 11, count 0 2006.224.07:36:28.15#ibcon#*mode == 0, iclass 11, count 0 2006.224.07:36:28.15#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.224.07:36:28.15#ibcon#[25=USB\r\n] 2006.224.07:36:28.15#ibcon#*before write, iclass 11, count 0 2006.224.07:36:28.15#ibcon#enter sib2, iclass 11, count 0 2006.224.07:36:28.15#ibcon#flushed, iclass 11, count 0 2006.224.07:36:28.15#ibcon#about to write, iclass 11, count 0 2006.224.07:36:28.15#ibcon#wrote, iclass 11, count 0 2006.224.07:36:28.15#ibcon#about to read 3, iclass 11, count 0 2006.224.07:36:28.18#ibcon#read 3, iclass 11, count 0 2006.224.07:36:28.18#ibcon#about to read 4, iclass 11, count 0 2006.224.07:36:28.18#ibcon#read 4, iclass 11, count 0 2006.224.07:36:28.18#ibcon#about to read 5, iclass 11, count 0 2006.224.07:36:28.18#ibcon#read 5, iclass 11, count 0 2006.224.07:36:28.18#ibcon#about to read 6, iclass 11, count 0 2006.224.07:36:28.18#ibcon#read 6, iclass 11, count 0 2006.224.07:36:28.18#ibcon#end of sib2, iclass 11, count 0 2006.224.07:36:28.18#ibcon#*after write, iclass 11, count 0 2006.224.07:36:28.18#ibcon#*before return 0, iclass 11, count 0 2006.224.07:36:28.18#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.224.07:36:28.18#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.224.07:36:28.18#ibcon#about to clear, iclass 11 cls_cnt 0 2006.224.07:36:28.18#ibcon#cleared, iclass 11 cls_cnt 0 2006.224.07:36:28.18$vc4f8/valo=2,572.99 2006.224.07:36:28.18#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.224.07:36:28.18#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.224.07:36:28.18#ibcon#ireg 17 cls_cnt 0 2006.224.07:36:28.18#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.224.07:36:28.18#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.224.07:36:28.18#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.224.07:36:28.18#ibcon#enter wrdev, iclass 13, count 0 2006.224.07:36:28.18#ibcon#first serial, iclass 13, count 0 2006.224.07:36:28.18#ibcon#enter sib2, iclass 13, count 0 2006.224.07:36:28.18#ibcon#flushed, iclass 13, count 0 2006.224.07:36:28.18#ibcon#about to write, iclass 13, count 0 2006.224.07:36:28.18#ibcon#wrote, iclass 13, count 0 2006.224.07:36:28.18#ibcon#about to read 3, iclass 13, count 0 2006.224.07:36:28.20#ibcon#read 3, iclass 13, count 0 2006.224.07:36:28.20#ibcon#about to read 4, iclass 13, count 0 2006.224.07:36:28.20#ibcon#read 4, iclass 13, count 0 2006.224.07:36:28.20#ibcon#about to read 5, iclass 13, count 0 2006.224.07:36:28.20#ibcon#read 5, iclass 13, count 0 2006.224.07:36:28.20#ibcon#about to read 6, iclass 13, count 0 2006.224.07:36:28.20#ibcon#read 6, iclass 13, count 0 2006.224.07:36:28.20#ibcon#end of sib2, iclass 13, count 0 2006.224.07:36:28.20#ibcon#*mode == 0, iclass 13, count 0 2006.224.07:36:28.20#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.224.07:36:28.20#ibcon#[26=FRQ=02,572.99\r\n] 2006.224.07:36:28.20#ibcon#*before write, iclass 13, count 0 2006.224.07:36:28.20#ibcon#enter sib2, iclass 13, count 0 2006.224.07:36:28.20#ibcon#flushed, iclass 13, count 0 2006.224.07:36:28.20#ibcon#about to write, iclass 13, count 0 2006.224.07:36:28.20#ibcon#wrote, iclass 13, count 0 2006.224.07:36:28.20#ibcon#about to read 3, iclass 13, count 0 2006.224.07:36:28.25#ibcon#read 3, iclass 13, count 0 2006.224.07:36:28.25#ibcon#about to read 4, iclass 13, count 0 2006.224.07:36:28.25#ibcon#read 4, iclass 13, count 0 2006.224.07:36:28.25#ibcon#about to read 5, iclass 13, count 0 2006.224.07:36:28.25#ibcon#read 5, iclass 13, count 0 2006.224.07:36:28.25#ibcon#about to read 6, iclass 13, count 0 2006.224.07:36:28.25#ibcon#read 6, iclass 13, count 0 2006.224.07:36:28.25#ibcon#end of sib2, iclass 13, count 0 2006.224.07:36:28.25#ibcon#*after write, iclass 13, count 0 2006.224.07:36:28.25#ibcon#*before return 0, iclass 13, count 0 2006.224.07:36:28.25#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.224.07:36:28.25#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.224.07:36:28.25#ibcon#about to clear, iclass 13 cls_cnt 0 2006.224.07:36:28.25#ibcon#cleared, iclass 13 cls_cnt 0 2006.224.07:36:28.25$vc4f8/va=2,7 2006.224.07:36:28.25#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.224.07:36:28.25#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.224.07:36:28.25#ibcon#ireg 11 cls_cnt 2 2006.224.07:36:28.25#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.224.07:36:28.30#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.224.07:36:28.30#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.224.07:36:28.30#ibcon#enter wrdev, iclass 15, count 2 2006.224.07:36:28.30#ibcon#first serial, iclass 15, count 2 2006.224.07:36:28.30#ibcon#enter sib2, iclass 15, count 2 2006.224.07:36:28.30#ibcon#flushed, iclass 15, count 2 2006.224.07:36:28.30#ibcon#about to write, iclass 15, count 2 2006.224.07:36:28.30#ibcon#wrote, iclass 15, count 2 2006.224.07:36:28.30#ibcon#about to read 3, iclass 15, count 2 2006.224.07:36:28.32#ibcon#read 3, iclass 15, count 2 2006.224.07:36:28.32#ibcon#about to read 4, iclass 15, count 2 2006.224.07:36:28.32#ibcon#read 4, iclass 15, count 2 2006.224.07:36:28.32#ibcon#about to read 5, iclass 15, count 2 2006.224.07:36:28.32#ibcon#read 5, iclass 15, count 2 2006.224.07:36:28.32#ibcon#about to read 6, iclass 15, count 2 2006.224.07:36:28.32#ibcon#read 6, iclass 15, count 2 2006.224.07:36:28.32#ibcon#end of sib2, iclass 15, count 2 2006.224.07:36:28.32#ibcon#*mode == 0, iclass 15, count 2 2006.224.07:36:28.32#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.224.07:36:28.32#ibcon#[25=AT02-07\r\n] 2006.224.07:36:28.32#ibcon#*before write, iclass 15, count 2 2006.224.07:36:28.32#ibcon#enter sib2, iclass 15, count 2 2006.224.07:36:28.32#ibcon#flushed, iclass 15, count 2 2006.224.07:36:28.32#ibcon#about to write, iclass 15, count 2 2006.224.07:36:28.32#ibcon#wrote, iclass 15, count 2 2006.224.07:36:28.32#ibcon#about to read 3, iclass 15, count 2 2006.224.07:36:28.35#ibcon#read 3, iclass 15, count 2 2006.224.07:36:28.35#ibcon#about to read 4, iclass 15, count 2 2006.224.07:36:28.35#ibcon#read 4, iclass 15, count 2 2006.224.07:36:28.35#ibcon#about to read 5, iclass 15, count 2 2006.224.07:36:28.35#ibcon#read 5, iclass 15, count 2 2006.224.07:36:28.35#ibcon#about to read 6, iclass 15, count 2 2006.224.07:36:28.35#ibcon#read 6, iclass 15, count 2 2006.224.07:36:28.35#ibcon#end of sib2, iclass 15, count 2 2006.224.07:36:28.35#ibcon#*after write, iclass 15, count 2 2006.224.07:36:28.35#ibcon#*before return 0, iclass 15, count 2 2006.224.07:36:28.35#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.224.07:36:28.35#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.224.07:36:28.35#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.224.07:36:28.35#ibcon#ireg 7 cls_cnt 0 2006.224.07:36:28.35#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.224.07:36:28.47#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.224.07:36:28.47#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.224.07:36:28.47#ibcon#enter wrdev, iclass 15, count 0 2006.224.07:36:28.47#ibcon#first serial, iclass 15, count 0 2006.224.07:36:28.47#ibcon#enter sib2, iclass 15, count 0 2006.224.07:36:28.47#ibcon#flushed, iclass 15, count 0 2006.224.07:36:28.47#ibcon#about to write, iclass 15, count 0 2006.224.07:36:28.47#ibcon#wrote, iclass 15, count 0 2006.224.07:36:28.47#ibcon#about to read 3, iclass 15, count 0 2006.224.07:36:28.49#ibcon#read 3, iclass 15, count 0 2006.224.07:36:28.49#ibcon#about to read 4, iclass 15, count 0 2006.224.07:36:28.49#ibcon#read 4, iclass 15, count 0 2006.224.07:36:28.49#ibcon#about to read 5, iclass 15, count 0 2006.224.07:36:28.49#ibcon#read 5, iclass 15, count 0 2006.224.07:36:28.49#ibcon#about to read 6, iclass 15, count 0 2006.224.07:36:28.49#ibcon#read 6, iclass 15, count 0 2006.224.07:36:28.49#ibcon#end of sib2, iclass 15, count 0 2006.224.07:36:28.49#ibcon#*mode == 0, iclass 15, count 0 2006.224.07:36:28.49#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.224.07:36:28.49#ibcon#[25=USB\r\n] 2006.224.07:36:28.49#ibcon#*before write, iclass 15, count 0 2006.224.07:36:28.49#ibcon#enter sib2, iclass 15, count 0 2006.224.07:36:28.49#ibcon#flushed, iclass 15, count 0 2006.224.07:36:28.49#ibcon#about to write, iclass 15, count 0 2006.224.07:36:28.49#ibcon#wrote, iclass 15, count 0 2006.224.07:36:28.49#ibcon#about to read 3, iclass 15, count 0 2006.224.07:36:28.52#ibcon#read 3, iclass 15, count 0 2006.224.07:36:28.52#ibcon#about to read 4, iclass 15, count 0 2006.224.07:36:28.52#ibcon#read 4, iclass 15, count 0 2006.224.07:36:28.52#ibcon#about to read 5, iclass 15, count 0 2006.224.07:36:28.52#ibcon#read 5, iclass 15, count 0 2006.224.07:36:28.52#ibcon#about to read 6, iclass 15, count 0 2006.224.07:36:28.52#ibcon#read 6, iclass 15, count 0 2006.224.07:36:28.52#ibcon#end of sib2, iclass 15, count 0 2006.224.07:36:28.52#ibcon#*after write, iclass 15, count 0 2006.224.07:36:28.52#ibcon#*before return 0, iclass 15, count 0 2006.224.07:36:28.52#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.224.07:36:28.52#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.224.07:36:28.52#ibcon#about to clear, iclass 15 cls_cnt 0 2006.224.07:36:28.52#ibcon#cleared, iclass 15 cls_cnt 0 2006.224.07:36:28.52$vc4f8/valo=3,672.99 2006.224.07:36:28.52#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.224.07:36:28.52#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.224.07:36:28.52#ibcon#ireg 17 cls_cnt 0 2006.224.07:36:28.52#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.224.07:36:28.52#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.224.07:36:28.52#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.224.07:36:28.52#ibcon#enter wrdev, iclass 17, count 0 2006.224.07:36:28.52#ibcon#first serial, iclass 17, count 0 2006.224.07:36:28.52#ibcon#enter sib2, iclass 17, count 0 2006.224.07:36:28.52#ibcon#flushed, iclass 17, count 0 2006.224.07:36:28.52#ibcon#about to write, iclass 17, count 0 2006.224.07:36:28.52#ibcon#wrote, iclass 17, count 0 2006.224.07:36:28.52#ibcon#about to read 3, iclass 17, count 0 2006.224.07:36:28.54#ibcon#read 3, iclass 17, count 0 2006.224.07:36:28.54#ibcon#about to read 4, iclass 17, count 0 2006.224.07:36:28.54#ibcon#read 4, iclass 17, count 0 2006.224.07:36:28.54#ibcon#about to read 5, iclass 17, count 0 2006.224.07:36:28.54#ibcon#read 5, iclass 17, count 0 2006.224.07:36:28.54#ibcon#about to read 6, iclass 17, count 0 2006.224.07:36:28.54#ibcon#read 6, iclass 17, count 0 2006.224.07:36:28.54#ibcon#end of sib2, iclass 17, count 0 2006.224.07:36:28.54#ibcon#*mode == 0, iclass 17, count 0 2006.224.07:36:28.54#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.224.07:36:28.54#ibcon#[26=FRQ=03,672.99\r\n] 2006.224.07:36:28.54#ibcon#*before write, iclass 17, count 0 2006.224.07:36:28.54#ibcon#enter sib2, iclass 17, count 0 2006.224.07:36:28.54#ibcon#flushed, iclass 17, count 0 2006.224.07:36:28.54#ibcon#about to write, iclass 17, count 0 2006.224.07:36:28.54#ibcon#wrote, iclass 17, count 0 2006.224.07:36:28.54#ibcon#about to read 3, iclass 17, count 0 2006.224.07:36:28.59#ibcon#read 3, iclass 17, count 0 2006.224.07:36:28.59#ibcon#about to read 4, iclass 17, count 0 2006.224.07:36:28.59#ibcon#read 4, iclass 17, count 0 2006.224.07:36:28.59#ibcon#about to read 5, iclass 17, count 0 2006.224.07:36:28.59#ibcon#read 5, iclass 17, count 0 2006.224.07:36:28.59#ibcon#about to read 6, iclass 17, count 0 2006.224.07:36:28.59#ibcon#read 6, iclass 17, count 0 2006.224.07:36:28.59#ibcon#end of sib2, iclass 17, count 0 2006.224.07:36:28.59#ibcon#*after write, iclass 17, count 0 2006.224.07:36:28.59#ibcon#*before return 0, iclass 17, count 0 2006.224.07:36:28.59#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.224.07:36:28.59#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.224.07:36:28.59#ibcon#about to clear, iclass 17 cls_cnt 0 2006.224.07:36:28.59#ibcon#cleared, iclass 17 cls_cnt 0 2006.224.07:36:28.59$vc4f8/va=3,6 2006.224.07:36:28.59#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.224.07:36:28.59#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.224.07:36:28.59#ibcon#ireg 11 cls_cnt 2 2006.224.07:36:28.59#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.224.07:36:28.64#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.224.07:36:28.64#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.224.07:36:28.64#ibcon#enter wrdev, iclass 19, count 2 2006.224.07:36:28.64#ibcon#first serial, iclass 19, count 2 2006.224.07:36:28.64#ibcon#enter sib2, iclass 19, count 2 2006.224.07:36:28.64#ibcon#flushed, iclass 19, count 2 2006.224.07:36:28.64#ibcon#about to write, iclass 19, count 2 2006.224.07:36:28.64#ibcon#wrote, iclass 19, count 2 2006.224.07:36:28.64#ibcon#about to read 3, iclass 19, count 2 2006.224.07:36:28.66#ibcon#read 3, iclass 19, count 2 2006.224.07:36:28.66#ibcon#about to read 4, iclass 19, count 2 2006.224.07:36:28.66#ibcon#read 4, iclass 19, count 2 2006.224.07:36:28.66#ibcon#about to read 5, iclass 19, count 2 2006.224.07:36:28.66#ibcon#read 5, iclass 19, count 2 2006.224.07:36:28.66#ibcon#about to read 6, iclass 19, count 2 2006.224.07:36:28.66#ibcon#read 6, iclass 19, count 2 2006.224.07:36:28.66#ibcon#end of sib2, iclass 19, count 2 2006.224.07:36:28.66#ibcon#*mode == 0, iclass 19, count 2 2006.224.07:36:28.66#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.224.07:36:28.66#ibcon#[25=AT03-06\r\n] 2006.224.07:36:28.66#ibcon#*before write, iclass 19, count 2 2006.224.07:36:28.66#ibcon#enter sib2, iclass 19, count 2 2006.224.07:36:28.66#ibcon#flushed, iclass 19, count 2 2006.224.07:36:28.66#ibcon#about to write, iclass 19, count 2 2006.224.07:36:28.66#ibcon#wrote, iclass 19, count 2 2006.224.07:36:28.66#ibcon#about to read 3, iclass 19, count 2 2006.224.07:36:28.69#ibcon#read 3, iclass 19, count 2 2006.224.07:36:28.69#ibcon#about to read 4, iclass 19, count 2 2006.224.07:36:28.69#ibcon#read 4, iclass 19, count 2 2006.224.07:36:28.69#ibcon#about to read 5, iclass 19, count 2 2006.224.07:36:28.69#ibcon#read 5, iclass 19, count 2 2006.224.07:36:28.69#ibcon#about to read 6, iclass 19, count 2 2006.224.07:36:28.69#ibcon#read 6, iclass 19, count 2 2006.224.07:36:28.69#ibcon#end of sib2, iclass 19, count 2 2006.224.07:36:28.69#ibcon#*after write, iclass 19, count 2 2006.224.07:36:28.69#ibcon#*before return 0, iclass 19, count 2 2006.224.07:36:28.69#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.224.07:36:28.69#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.224.07:36:28.69#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.224.07:36:28.69#ibcon#ireg 7 cls_cnt 0 2006.224.07:36:28.69#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.224.07:36:28.81#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.224.07:36:28.81#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.224.07:36:28.81#ibcon#enter wrdev, iclass 19, count 0 2006.224.07:36:28.81#ibcon#first serial, iclass 19, count 0 2006.224.07:36:28.81#ibcon#enter sib2, iclass 19, count 0 2006.224.07:36:28.81#ibcon#flushed, iclass 19, count 0 2006.224.07:36:28.81#ibcon#about to write, iclass 19, count 0 2006.224.07:36:28.81#ibcon#wrote, iclass 19, count 0 2006.224.07:36:28.81#ibcon#about to read 3, iclass 19, count 0 2006.224.07:36:28.83#ibcon#read 3, iclass 19, count 0 2006.224.07:36:28.83#ibcon#about to read 4, iclass 19, count 0 2006.224.07:36:28.83#ibcon#read 4, iclass 19, count 0 2006.224.07:36:28.83#ibcon#about to read 5, iclass 19, count 0 2006.224.07:36:28.83#ibcon#read 5, iclass 19, count 0 2006.224.07:36:28.83#ibcon#about to read 6, iclass 19, count 0 2006.224.07:36:28.83#ibcon#read 6, iclass 19, count 0 2006.224.07:36:28.83#ibcon#end of sib2, iclass 19, count 0 2006.224.07:36:28.83#ibcon#*mode == 0, iclass 19, count 0 2006.224.07:36:28.83#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.224.07:36:28.83#ibcon#[25=USB\r\n] 2006.224.07:36:28.83#ibcon#*before write, iclass 19, count 0 2006.224.07:36:28.83#ibcon#enter sib2, iclass 19, count 0 2006.224.07:36:28.83#ibcon#flushed, iclass 19, count 0 2006.224.07:36:28.83#ibcon#about to write, iclass 19, count 0 2006.224.07:36:28.83#ibcon#wrote, iclass 19, count 0 2006.224.07:36:28.83#ibcon#about to read 3, iclass 19, count 0 2006.224.07:36:28.86#ibcon#read 3, iclass 19, count 0 2006.224.07:36:28.86#ibcon#about to read 4, iclass 19, count 0 2006.224.07:36:28.86#ibcon#read 4, iclass 19, count 0 2006.224.07:36:28.86#ibcon#about to read 5, iclass 19, count 0 2006.224.07:36:28.86#ibcon#read 5, iclass 19, count 0 2006.224.07:36:28.86#ibcon#about to read 6, iclass 19, count 0 2006.224.07:36:28.86#ibcon#read 6, iclass 19, count 0 2006.224.07:36:28.86#ibcon#end of sib2, iclass 19, count 0 2006.224.07:36:28.86#ibcon#*after write, iclass 19, count 0 2006.224.07:36:28.86#ibcon#*before return 0, iclass 19, count 0 2006.224.07:36:28.86#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.224.07:36:28.86#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.224.07:36:28.86#ibcon#about to clear, iclass 19 cls_cnt 0 2006.224.07:36:28.86#ibcon#cleared, iclass 19 cls_cnt 0 2006.224.07:36:28.86$vc4f8/valo=4,832.99 2006.224.07:36:28.86#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.224.07:36:28.86#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.224.07:36:28.86#ibcon#ireg 17 cls_cnt 0 2006.224.07:36:28.86#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.224.07:36:28.86#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.224.07:36:28.86#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.224.07:36:28.86#ibcon#enter wrdev, iclass 21, count 0 2006.224.07:36:28.86#ibcon#first serial, iclass 21, count 0 2006.224.07:36:28.86#ibcon#enter sib2, iclass 21, count 0 2006.224.07:36:28.86#ibcon#flushed, iclass 21, count 0 2006.224.07:36:28.86#ibcon#about to write, iclass 21, count 0 2006.224.07:36:28.86#ibcon#wrote, iclass 21, count 0 2006.224.07:36:28.86#ibcon#about to read 3, iclass 21, count 0 2006.224.07:36:28.88#ibcon#read 3, iclass 21, count 0 2006.224.07:36:28.88#ibcon#about to read 4, iclass 21, count 0 2006.224.07:36:28.88#ibcon#read 4, iclass 21, count 0 2006.224.07:36:28.88#ibcon#about to read 5, iclass 21, count 0 2006.224.07:36:28.88#ibcon#read 5, iclass 21, count 0 2006.224.07:36:28.88#ibcon#about to read 6, iclass 21, count 0 2006.224.07:36:28.88#ibcon#read 6, iclass 21, count 0 2006.224.07:36:28.88#ibcon#end of sib2, iclass 21, count 0 2006.224.07:36:28.88#ibcon#*mode == 0, iclass 21, count 0 2006.224.07:36:28.88#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.224.07:36:28.88#ibcon#[26=FRQ=04,832.99\r\n] 2006.224.07:36:28.88#ibcon#*before write, iclass 21, count 0 2006.224.07:36:28.88#ibcon#enter sib2, iclass 21, count 0 2006.224.07:36:28.88#ibcon#flushed, iclass 21, count 0 2006.224.07:36:28.88#ibcon#about to write, iclass 21, count 0 2006.224.07:36:28.88#ibcon#wrote, iclass 21, count 0 2006.224.07:36:28.88#ibcon#about to read 3, iclass 21, count 0 2006.224.07:36:28.92#ibcon#read 3, iclass 21, count 0 2006.224.07:36:28.92#ibcon#about to read 4, iclass 21, count 0 2006.224.07:36:28.92#ibcon#read 4, iclass 21, count 0 2006.224.07:36:28.92#ibcon#about to read 5, iclass 21, count 0 2006.224.07:36:28.92#ibcon#read 5, iclass 21, count 0 2006.224.07:36:28.92#ibcon#about to read 6, iclass 21, count 0 2006.224.07:36:28.92#ibcon#read 6, iclass 21, count 0 2006.224.07:36:28.92#ibcon#end of sib2, iclass 21, count 0 2006.224.07:36:28.92#ibcon#*after write, iclass 21, count 0 2006.224.07:36:28.92#ibcon#*before return 0, iclass 21, count 0 2006.224.07:36:28.92#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.224.07:36:28.92#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.224.07:36:28.92#ibcon#about to clear, iclass 21 cls_cnt 0 2006.224.07:36:28.92#ibcon#cleared, iclass 21 cls_cnt 0 2006.224.07:36:28.92$vc4f8/va=4,7 2006.224.07:36:28.92#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.224.07:36:28.92#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.224.07:36:28.92#ibcon#ireg 11 cls_cnt 2 2006.224.07:36:28.92#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.224.07:36:28.98#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.224.07:36:28.98#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.224.07:36:28.98#ibcon#enter wrdev, iclass 23, count 2 2006.224.07:36:28.98#ibcon#first serial, iclass 23, count 2 2006.224.07:36:28.98#ibcon#enter sib2, iclass 23, count 2 2006.224.07:36:28.98#ibcon#flushed, iclass 23, count 2 2006.224.07:36:28.98#ibcon#about to write, iclass 23, count 2 2006.224.07:36:28.98#ibcon#wrote, iclass 23, count 2 2006.224.07:36:28.98#ibcon#about to read 3, iclass 23, count 2 2006.224.07:36:29.00#ibcon#read 3, iclass 23, count 2 2006.224.07:36:29.00#ibcon#about to read 4, iclass 23, count 2 2006.224.07:36:29.00#ibcon#read 4, iclass 23, count 2 2006.224.07:36:29.00#ibcon#about to read 5, iclass 23, count 2 2006.224.07:36:29.00#ibcon#read 5, iclass 23, count 2 2006.224.07:36:29.00#ibcon#about to read 6, iclass 23, count 2 2006.224.07:36:29.00#ibcon#read 6, iclass 23, count 2 2006.224.07:36:29.00#ibcon#end of sib2, iclass 23, count 2 2006.224.07:36:29.00#ibcon#*mode == 0, iclass 23, count 2 2006.224.07:36:29.00#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.224.07:36:29.00#ibcon#[25=AT04-07\r\n] 2006.224.07:36:29.00#ibcon#*before write, iclass 23, count 2 2006.224.07:36:29.00#ibcon#enter sib2, iclass 23, count 2 2006.224.07:36:29.00#ibcon#flushed, iclass 23, count 2 2006.224.07:36:29.00#ibcon#about to write, iclass 23, count 2 2006.224.07:36:29.00#ibcon#wrote, iclass 23, count 2 2006.224.07:36:29.00#ibcon#about to read 3, iclass 23, count 2 2006.224.07:36:29.03#ibcon#read 3, iclass 23, count 2 2006.224.07:36:29.03#ibcon#about to read 4, iclass 23, count 2 2006.224.07:36:29.03#ibcon#read 4, iclass 23, count 2 2006.224.07:36:29.03#ibcon#about to read 5, iclass 23, count 2 2006.224.07:36:29.03#ibcon#read 5, iclass 23, count 2 2006.224.07:36:29.03#ibcon#about to read 6, iclass 23, count 2 2006.224.07:36:29.03#ibcon#read 6, iclass 23, count 2 2006.224.07:36:29.03#ibcon#end of sib2, iclass 23, count 2 2006.224.07:36:29.03#ibcon#*after write, iclass 23, count 2 2006.224.07:36:29.03#ibcon#*before return 0, iclass 23, count 2 2006.224.07:36:29.03#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.224.07:36:29.03#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.224.07:36:29.03#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.224.07:36:29.03#ibcon#ireg 7 cls_cnt 0 2006.224.07:36:29.03#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.224.07:36:29.15#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.224.07:36:29.15#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.224.07:36:29.15#ibcon#enter wrdev, iclass 23, count 0 2006.224.07:36:29.15#ibcon#first serial, iclass 23, count 0 2006.224.07:36:29.15#ibcon#enter sib2, iclass 23, count 0 2006.224.07:36:29.15#ibcon#flushed, iclass 23, count 0 2006.224.07:36:29.15#ibcon#about to write, iclass 23, count 0 2006.224.07:36:29.15#ibcon#wrote, iclass 23, count 0 2006.224.07:36:29.15#ibcon#about to read 3, iclass 23, count 0 2006.224.07:36:29.17#ibcon#read 3, iclass 23, count 0 2006.224.07:36:29.17#ibcon#about to read 4, iclass 23, count 0 2006.224.07:36:29.17#ibcon#read 4, iclass 23, count 0 2006.224.07:36:29.17#ibcon#about to read 5, iclass 23, count 0 2006.224.07:36:29.17#ibcon#read 5, iclass 23, count 0 2006.224.07:36:29.17#ibcon#about to read 6, iclass 23, count 0 2006.224.07:36:29.17#ibcon#read 6, iclass 23, count 0 2006.224.07:36:29.17#ibcon#end of sib2, iclass 23, count 0 2006.224.07:36:29.17#ibcon#*mode == 0, iclass 23, count 0 2006.224.07:36:29.17#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.224.07:36:29.17#ibcon#[25=USB\r\n] 2006.224.07:36:29.17#ibcon#*before write, iclass 23, count 0 2006.224.07:36:29.17#ibcon#enter sib2, iclass 23, count 0 2006.224.07:36:29.17#ibcon#flushed, iclass 23, count 0 2006.224.07:36:29.17#ibcon#about to write, iclass 23, count 0 2006.224.07:36:29.17#ibcon#wrote, iclass 23, count 0 2006.224.07:36:29.17#ibcon#about to read 3, iclass 23, count 0 2006.224.07:36:29.20#ibcon#read 3, iclass 23, count 0 2006.224.07:36:29.20#ibcon#about to read 4, iclass 23, count 0 2006.224.07:36:29.20#ibcon#read 4, iclass 23, count 0 2006.224.07:36:29.20#ibcon#about to read 5, iclass 23, count 0 2006.224.07:36:29.20#ibcon#read 5, iclass 23, count 0 2006.224.07:36:29.20#ibcon#about to read 6, iclass 23, count 0 2006.224.07:36:29.20#ibcon#read 6, iclass 23, count 0 2006.224.07:36:29.20#ibcon#end of sib2, iclass 23, count 0 2006.224.07:36:29.20#ibcon#*after write, iclass 23, count 0 2006.224.07:36:29.20#ibcon#*before return 0, iclass 23, count 0 2006.224.07:36:29.20#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.224.07:36:29.20#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.224.07:36:29.20#ibcon#about to clear, iclass 23 cls_cnt 0 2006.224.07:36:29.20#ibcon#cleared, iclass 23 cls_cnt 0 2006.224.07:36:29.20$vc4f8/valo=5,652.99 2006.224.07:36:29.20#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.224.07:36:29.20#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.224.07:36:29.20#ibcon#ireg 17 cls_cnt 0 2006.224.07:36:29.20#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.224.07:36:29.20#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.224.07:36:29.20#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.224.07:36:29.20#ibcon#enter wrdev, iclass 25, count 0 2006.224.07:36:29.20#ibcon#first serial, iclass 25, count 0 2006.224.07:36:29.20#ibcon#enter sib2, iclass 25, count 0 2006.224.07:36:29.20#ibcon#flushed, iclass 25, count 0 2006.224.07:36:29.20#ibcon#about to write, iclass 25, count 0 2006.224.07:36:29.20#ibcon#wrote, iclass 25, count 0 2006.224.07:36:29.20#ibcon#about to read 3, iclass 25, count 0 2006.224.07:36:29.22#ibcon#read 3, iclass 25, count 0 2006.224.07:36:29.22#ibcon#about to read 4, iclass 25, count 0 2006.224.07:36:29.22#ibcon#read 4, iclass 25, count 0 2006.224.07:36:29.22#ibcon#about to read 5, iclass 25, count 0 2006.224.07:36:29.22#ibcon#read 5, iclass 25, count 0 2006.224.07:36:29.22#ibcon#about to read 6, iclass 25, count 0 2006.224.07:36:29.22#ibcon#read 6, iclass 25, count 0 2006.224.07:36:29.22#ibcon#end of sib2, iclass 25, count 0 2006.224.07:36:29.22#ibcon#*mode == 0, iclass 25, count 0 2006.224.07:36:29.22#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.224.07:36:29.22#ibcon#[26=FRQ=05,652.99\r\n] 2006.224.07:36:29.22#ibcon#*before write, iclass 25, count 0 2006.224.07:36:29.22#ibcon#enter sib2, iclass 25, count 0 2006.224.07:36:29.22#ibcon#flushed, iclass 25, count 0 2006.224.07:36:29.22#ibcon#about to write, iclass 25, count 0 2006.224.07:36:29.22#ibcon#wrote, iclass 25, count 0 2006.224.07:36:29.22#ibcon#about to read 3, iclass 25, count 0 2006.224.07:36:29.26#ibcon#read 3, iclass 25, count 0 2006.224.07:36:29.26#ibcon#about to read 4, iclass 25, count 0 2006.224.07:36:29.26#ibcon#read 4, iclass 25, count 0 2006.224.07:36:29.26#ibcon#about to read 5, iclass 25, count 0 2006.224.07:36:29.26#ibcon#read 5, iclass 25, count 0 2006.224.07:36:29.26#ibcon#about to read 6, iclass 25, count 0 2006.224.07:36:29.26#ibcon#read 6, iclass 25, count 0 2006.224.07:36:29.26#ibcon#end of sib2, iclass 25, count 0 2006.224.07:36:29.26#ibcon#*after write, iclass 25, count 0 2006.224.07:36:29.26#ibcon#*before return 0, iclass 25, count 0 2006.224.07:36:29.26#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.224.07:36:29.26#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.224.07:36:29.26#ibcon#about to clear, iclass 25 cls_cnt 0 2006.224.07:36:29.26#ibcon#cleared, iclass 25 cls_cnt 0 2006.224.07:36:29.26$vc4f8/va=5,7 2006.224.07:36:29.26#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.224.07:36:29.26#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.224.07:36:29.26#ibcon#ireg 11 cls_cnt 2 2006.224.07:36:29.26#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.224.07:36:29.32#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.224.07:36:29.32#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.224.07:36:29.32#ibcon#enter wrdev, iclass 27, count 2 2006.224.07:36:29.32#ibcon#first serial, iclass 27, count 2 2006.224.07:36:29.32#ibcon#enter sib2, iclass 27, count 2 2006.224.07:36:29.32#ibcon#flushed, iclass 27, count 2 2006.224.07:36:29.32#ibcon#about to write, iclass 27, count 2 2006.224.07:36:29.32#ibcon#wrote, iclass 27, count 2 2006.224.07:36:29.32#ibcon#about to read 3, iclass 27, count 2 2006.224.07:36:29.34#ibcon#read 3, iclass 27, count 2 2006.224.07:36:29.34#ibcon#about to read 4, iclass 27, count 2 2006.224.07:36:29.34#ibcon#read 4, iclass 27, count 2 2006.224.07:36:29.34#ibcon#about to read 5, iclass 27, count 2 2006.224.07:36:29.34#ibcon#read 5, iclass 27, count 2 2006.224.07:36:29.34#ibcon#about to read 6, iclass 27, count 2 2006.224.07:36:29.34#ibcon#read 6, iclass 27, count 2 2006.224.07:36:29.34#ibcon#end of sib2, iclass 27, count 2 2006.224.07:36:29.34#ibcon#*mode == 0, iclass 27, count 2 2006.224.07:36:29.34#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.224.07:36:29.34#ibcon#[25=AT05-07\r\n] 2006.224.07:36:29.34#ibcon#*before write, iclass 27, count 2 2006.224.07:36:29.34#ibcon#enter sib2, iclass 27, count 2 2006.224.07:36:29.34#ibcon#flushed, iclass 27, count 2 2006.224.07:36:29.34#ibcon#about to write, iclass 27, count 2 2006.224.07:36:29.34#ibcon#wrote, iclass 27, count 2 2006.224.07:36:29.34#ibcon#about to read 3, iclass 27, count 2 2006.224.07:36:29.37#ibcon#read 3, iclass 27, count 2 2006.224.07:36:29.37#ibcon#about to read 4, iclass 27, count 2 2006.224.07:36:29.37#ibcon#read 4, iclass 27, count 2 2006.224.07:36:29.37#ibcon#about to read 5, iclass 27, count 2 2006.224.07:36:29.37#ibcon#read 5, iclass 27, count 2 2006.224.07:36:29.37#ibcon#about to read 6, iclass 27, count 2 2006.224.07:36:29.37#ibcon#read 6, iclass 27, count 2 2006.224.07:36:29.37#ibcon#end of sib2, iclass 27, count 2 2006.224.07:36:29.37#ibcon#*after write, iclass 27, count 2 2006.224.07:36:29.37#ibcon#*before return 0, iclass 27, count 2 2006.224.07:36:29.37#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.224.07:36:29.37#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.224.07:36:29.37#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.224.07:36:29.37#ibcon#ireg 7 cls_cnt 0 2006.224.07:36:29.37#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.224.07:36:29.49#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.224.07:36:29.49#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.224.07:36:29.49#ibcon#enter wrdev, iclass 27, count 0 2006.224.07:36:29.49#ibcon#first serial, iclass 27, count 0 2006.224.07:36:29.49#ibcon#enter sib2, iclass 27, count 0 2006.224.07:36:29.49#ibcon#flushed, iclass 27, count 0 2006.224.07:36:29.49#ibcon#about to write, iclass 27, count 0 2006.224.07:36:29.49#ibcon#wrote, iclass 27, count 0 2006.224.07:36:29.49#ibcon#about to read 3, iclass 27, count 0 2006.224.07:36:29.51#ibcon#read 3, iclass 27, count 0 2006.224.07:36:29.51#ibcon#about to read 4, iclass 27, count 0 2006.224.07:36:29.51#ibcon#read 4, iclass 27, count 0 2006.224.07:36:29.51#ibcon#about to read 5, iclass 27, count 0 2006.224.07:36:29.51#ibcon#read 5, iclass 27, count 0 2006.224.07:36:29.51#ibcon#about to read 6, iclass 27, count 0 2006.224.07:36:29.51#ibcon#read 6, iclass 27, count 0 2006.224.07:36:29.51#ibcon#end of sib2, iclass 27, count 0 2006.224.07:36:29.51#ibcon#*mode == 0, iclass 27, count 0 2006.224.07:36:29.51#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.224.07:36:29.51#ibcon#[25=USB\r\n] 2006.224.07:36:29.51#ibcon#*before write, iclass 27, count 0 2006.224.07:36:29.51#ibcon#enter sib2, iclass 27, count 0 2006.224.07:36:29.51#ibcon#flushed, iclass 27, count 0 2006.224.07:36:29.51#ibcon#about to write, iclass 27, count 0 2006.224.07:36:29.51#ibcon#wrote, iclass 27, count 0 2006.224.07:36:29.51#ibcon#about to read 3, iclass 27, count 0 2006.224.07:36:29.54#ibcon#read 3, iclass 27, count 0 2006.224.07:36:29.54#ibcon#about to read 4, iclass 27, count 0 2006.224.07:36:29.54#ibcon#read 4, iclass 27, count 0 2006.224.07:36:29.54#ibcon#about to read 5, iclass 27, count 0 2006.224.07:36:29.54#ibcon#read 5, iclass 27, count 0 2006.224.07:36:29.54#ibcon#about to read 6, iclass 27, count 0 2006.224.07:36:29.54#ibcon#read 6, iclass 27, count 0 2006.224.07:36:29.54#ibcon#end of sib2, iclass 27, count 0 2006.224.07:36:29.54#ibcon#*after write, iclass 27, count 0 2006.224.07:36:29.54#ibcon#*before return 0, iclass 27, count 0 2006.224.07:36:29.54#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.224.07:36:29.54#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.224.07:36:29.54#ibcon#about to clear, iclass 27 cls_cnt 0 2006.224.07:36:29.54#ibcon#cleared, iclass 27 cls_cnt 0 2006.224.07:36:29.54$vc4f8/valo=6,772.99 2006.224.07:36:29.54#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.224.07:36:29.54#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.224.07:36:29.54#ibcon#ireg 17 cls_cnt 0 2006.224.07:36:29.54#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.224.07:36:29.54#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.224.07:36:29.54#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.224.07:36:29.54#ibcon#enter wrdev, iclass 29, count 0 2006.224.07:36:29.54#ibcon#first serial, iclass 29, count 0 2006.224.07:36:29.54#ibcon#enter sib2, iclass 29, count 0 2006.224.07:36:29.54#ibcon#flushed, iclass 29, count 0 2006.224.07:36:29.54#ibcon#about to write, iclass 29, count 0 2006.224.07:36:29.54#ibcon#wrote, iclass 29, count 0 2006.224.07:36:29.54#ibcon#about to read 3, iclass 29, count 0 2006.224.07:36:29.56#ibcon#read 3, iclass 29, count 0 2006.224.07:36:29.56#ibcon#about to read 4, iclass 29, count 0 2006.224.07:36:29.56#ibcon#read 4, iclass 29, count 0 2006.224.07:36:29.56#ibcon#about to read 5, iclass 29, count 0 2006.224.07:36:29.56#ibcon#read 5, iclass 29, count 0 2006.224.07:36:29.56#ibcon#about to read 6, iclass 29, count 0 2006.224.07:36:29.56#ibcon#read 6, iclass 29, count 0 2006.224.07:36:29.56#ibcon#end of sib2, iclass 29, count 0 2006.224.07:36:29.56#ibcon#*mode == 0, iclass 29, count 0 2006.224.07:36:29.56#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.224.07:36:29.56#ibcon#[26=FRQ=06,772.99\r\n] 2006.224.07:36:29.56#ibcon#*before write, iclass 29, count 0 2006.224.07:36:29.56#ibcon#enter sib2, iclass 29, count 0 2006.224.07:36:29.56#ibcon#flushed, iclass 29, count 0 2006.224.07:36:29.56#ibcon#about to write, iclass 29, count 0 2006.224.07:36:29.56#ibcon#wrote, iclass 29, count 0 2006.224.07:36:29.56#ibcon#about to read 3, iclass 29, count 0 2006.224.07:36:29.61#ibcon#read 3, iclass 29, count 0 2006.224.07:36:29.61#ibcon#about to read 4, iclass 29, count 0 2006.224.07:36:29.61#ibcon#read 4, iclass 29, count 0 2006.224.07:36:29.61#ibcon#about to read 5, iclass 29, count 0 2006.224.07:36:29.61#ibcon#read 5, iclass 29, count 0 2006.224.07:36:29.61#ibcon#about to read 6, iclass 29, count 0 2006.224.07:36:29.61#ibcon#read 6, iclass 29, count 0 2006.224.07:36:29.61#ibcon#end of sib2, iclass 29, count 0 2006.224.07:36:29.61#ibcon#*after write, iclass 29, count 0 2006.224.07:36:29.61#ibcon#*before return 0, iclass 29, count 0 2006.224.07:36:29.61#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.224.07:36:29.61#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.224.07:36:29.61#ibcon#about to clear, iclass 29 cls_cnt 0 2006.224.07:36:29.61#ibcon#cleared, iclass 29 cls_cnt 0 2006.224.07:36:29.61$vc4f8/va=6,6 2006.224.07:36:29.61#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.224.07:36:29.61#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.224.07:36:29.61#ibcon#ireg 11 cls_cnt 2 2006.224.07:36:29.61#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.224.07:36:29.66#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.224.07:36:29.66#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.224.07:36:29.66#ibcon#enter wrdev, iclass 31, count 2 2006.224.07:36:29.66#ibcon#first serial, iclass 31, count 2 2006.224.07:36:29.66#ibcon#enter sib2, iclass 31, count 2 2006.224.07:36:29.66#ibcon#flushed, iclass 31, count 2 2006.224.07:36:29.66#ibcon#about to write, iclass 31, count 2 2006.224.07:36:29.66#ibcon#wrote, iclass 31, count 2 2006.224.07:36:29.66#ibcon#about to read 3, iclass 31, count 2 2006.224.07:36:29.68#ibcon#read 3, iclass 31, count 2 2006.224.07:36:29.68#ibcon#about to read 4, iclass 31, count 2 2006.224.07:36:29.68#ibcon#read 4, iclass 31, count 2 2006.224.07:36:29.68#ibcon#about to read 5, iclass 31, count 2 2006.224.07:36:29.68#ibcon#read 5, iclass 31, count 2 2006.224.07:36:29.68#ibcon#about to read 6, iclass 31, count 2 2006.224.07:36:29.68#ibcon#read 6, iclass 31, count 2 2006.224.07:36:29.68#ibcon#end of sib2, iclass 31, count 2 2006.224.07:36:29.68#ibcon#*mode == 0, iclass 31, count 2 2006.224.07:36:29.68#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.224.07:36:29.68#ibcon#[25=AT06-06\r\n] 2006.224.07:36:29.68#ibcon#*before write, iclass 31, count 2 2006.224.07:36:29.68#ibcon#enter sib2, iclass 31, count 2 2006.224.07:36:29.68#ibcon#flushed, iclass 31, count 2 2006.224.07:36:29.68#ibcon#about to write, iclass 31, count 2 2006.224.07:36:29.68#ibcon#wrote, iclass 31, count 2 2006.224.07:36:29.68#ibcon#about to read 3, iclass 31, count 2 2006.224.07:36:29.71#ibcon#read 3, iclass 31, count 2 2006.224.07:36:29.71#ibcon#about to read 4, iclass 31, count 2 2006.224.07:36:29.71#ibcon#read 4, iclass 31, count 2 2006.224.07:36:29.71#ibcon#about to read 5, iclass 31, count 2 2006.224.07:36:29.71#ibcon#read 5, iclass 31, count 2 2006.224.07:36:29.71#ibcon#about to read 6, iclass 31, count 2 2006.224.07:36:29.71#ibcon#read 6, iclass 31, count 2 2006.224.07:36:29.71#ibcon#end of sib2, iclass 31, count 2 2006.224.07:36:29.71#ibcon#*after write, iclass 31, count 2 2006.224.07:36:29.71#ibcon#*before return 0, iclass 31, count 2 2006.224.07:36:29.71#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.224.07:36:29.71#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.224.07:36:29.71#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.224.07:36:29.71#ibcon#ireg 7 cls_cnt 0 2006.224.07:36:29.71#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.224.07:36:29.83#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.224.07:36:29.83#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.224.07:36:29.83#ibcon#enter wrdev, iclass 31, count 0 2006.224.07:36:29.83#ibcon#first serial, iclass 31, count 0 2006.224.07:36:29.83#ibcon#enter sib2, iclass 31, count 0 2006.224.07:36:29.83#ibcon#flushed, iclass 31, count 0 2006.224.07:36:29.83#ibcon#about to write, iclass 31, count 0 2006.224.07:36:29.83#ibcon#wrote, iclass 31, count 0 2006.224.07:36:29.83#ibcon#about to read 3, iclass 31, count 0 2006.224.07:36:29.85#ibcon#read 3, iclass 31, count 0 2006.224.07:36:29.85#ibcon#about to read 4, iclass 31, count 0 2006.224.07:36:29.85#ibcon#read 4, iclass 31, count 0 2006.224.07:36:29.85#ibcon#about to read 5, iclass 31, count 0 2006.224.07:36:29.85#ibcon#read 5, iclass 31, count 0 2006.224.07:36:29.85#ibcon#about to read 6, iclass 31, count 0 2006.224.07:36:29.85#ibcon#read 6, iclass 31, count 0 2006.224.07:36:29.85#ibcon#end of sib2, iclass 31, count 0 2006.224.07:36:29.85#ibcon#*mode == 0, iclass 31, count 0 2006.224.07:36:29.85#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.224.07:36:29.85#ibcon#[25=USB\r\n] 2006.224.07:36:29.85#ibcon#*before write, iclass 31, count 0 2006.224.07:36:29.85#ibcon#enter sib2, iclass 31, count 0 2006.224.07:36:29.85#ibcon#flushed, iclass 31, count 0 2006.224.07:36:29.85#ibcon#about to write, iclass 31, count 0 2006.224.07:36:29.85#ibcon#wrote, iclass 31, count 0 2006.224.07:36:29.85#ibcon#about to read 3, iclass 31, count 0 2006.224.07:36:29.88#ibcon#read 3, iclass 31, count 0 2006.224.07:36:29.88#ibcon#about to read 4, iclass 31, count 0 2006.224.07:36:29.88#ibcon#read 4, iclass 31, count 0 2006.224.07:36:29.88#ibcon#about to read 5, iclass 31, count 0 2006.224.07:36:29.88#ibcon#read 5, iclass 31, count 0 2006.224.07:36:29.88#ibcon#about to read 6, iclass 31, count 0 2006.224.07:36:29.88#ibcon#read 6, iclass 31, count 0 2006.224.07:36:29.88#ibcon#end of sib2, iclass 31, count 0 2006.224.07:36:29.88#ibcon#*after write, iclass 31, count 0 2006.224.07:36:29.88#ibcon#*before return 0, iclass 31, count 0 2006.224.07:36:29.88#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.224.07:36:29.88#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.224.07:36:29.88#ibcon#about to clear, iclass 31 cls_cnt 0 2006.224.07:36:29.88#ibcon#cleared, iclass 31 cls_cnt 0 2006.224.07:36:29.88$vc4f8/valo=7,832.99 2006.224.07:36:29.88#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.224.07:36:29.88#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.224.07:36:29.88#ibcon#ireg 17 cls_cnt 0 2006.224.07:36:29.88#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.224.07:36:29.88#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.224.07:36:29.88#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.224.07:36:29.88#ibcon#enter wrdev, iclass 33, count 0 2006.224.07:36:29.88#ibcon#first serial, iclass 33, count 0 2006.224.07:36:29.88#ibcon#enter sib2, iclass 33, count 0 2006.224.07:36:29.88#ibcon#flushed, iclass 33, count 0 2006.224.07:36:29.88#ibcon#about to write, iclass 33, count 0 2006.224.07:36:29.88#ibcon#wrote, iclass 33, count 0 2006.224.07:36:29.88#ibcon#about to read 3, iclass 33, count 0 2006.224.07:36:29.90#ibcon#read 3, iclass 33, count 0 2006.224.07:36:29.90#ibcon#about to read 4, iclass 33, count 0 2006.224.07:36:29.90#ibcon#read 4, iclass 33, count 0 2006.224.07:36:29.90#ibcon#about to read 5, iclass 33, count 0 2006.224.07:36:29.90#ibcon#read 5, iclass 33, count 0 2006.224.07:36:29.90#ibcon#about to read 6, iclass 33, count 0 2006.224.07:36:29.90#ibcon#read 6, iclass 33, count 0 2006.224.07:36:29.90#ibcon#end of sib2, iclass 33, count 0 2006.224.07:36:29.90#ibcon#*mode == 0, iclass 33, count 0 2006.224.07:36:29.90#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.224.07:36:29.90#ibcon#[26=FRQ=07,832.99\r\n] 2006.224.07:36:29.90#ibcon#*before write, iclass 33, count 0 2006.224.07:36:29.90#ibcon#enter sib2, iclass 33, count 0 2006.224.07:36:29.90#ibcon#flushed, iclass 33, count 0 2006.224.07:36:29.90#ibcon#about to write, iclass 33, count 0 2006.224.07:36:29.90#ibcon#wrote, iclass 33, count 0 2006.224.07:36:29.90#ibcon#about to read 3, iclass 33, count 0 2006.224.07:36:29.94#ibcon#read 3, iclass 33, count 0 2006.224.07:36:29.94#ibcon#about to read 4, iclass 33, count 0 2006.224.07:36:29.94#ibcon#read 4, iclass 33, count 0 2006.224.07:36:29.94#ibcon#about to read 5, iclass 33, count 0 2006.224.07:36:29.94#ibcon#read 5, iclass 33, count 0 2006.224.07:36:29.94#ibcon#about to read 6, iclass 33, count 0 2006.224.07:36:29.94#ibcon#read 6, iclass 33, count 0 2006.224.07:36:29.94#ibcon#end of sib2, iclass 33, count 0 2006.224.07:36:29.94#ibcon#*after write, iclass 33, count 0 2006.224.07:36:29.94#ibcon#*before return 0, iclass 33, count 0 2006.224.07:36:29.94#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.224.07:36:29.94#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.224.07:36:29.94#ibcon#about to clear, iclass 33 cls_cnt 0 2006.224.07:36:29.94#ibcon#cleared, iclass 33 cls_cnt 0 2006.224.07:36:29.94$vc4f8/va=7,6 2006.224.07:36:29.94#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.224.07:36:29.94#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.224.07:36:29.94#ibcon#ireg 11 cls_cnt 2 2006.224.07:36:29.94#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.224.07:36:30.00#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.224.07:36:30.00#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.224.07:36:30.00#ibcon#enter wrdev, iclass 35, count 2 2006.224.07:36:30.00#ibcon#first serial, iclass 35, count 2 2006.224.07:36:30.00#ibcon#enter sib2, iclass 35, count 2 2006.224.07:36:30.00#ibcon#flushed, iclass 35, count 2 2006.224.07:36:30.00#ibcon#about to write, iclass 35, count 2 2006.224.07:36:30.00#ibcon#wrote, iclass 35, count 2 2006.224.07:36:30.00#ibcon#about to read 3, iclass 35, count 2 2006.224.07:36:30.02#ibcon#read 3, iclass 35, count 2 2006.224.07:36:30.02#ibcon#about to read 4, iclass 35, count 2 2006.224.07:36:30.02#ibcon#read 4, iclass 35, count 2 2006.224.07:36:30.02#ibcon#about to read 5, iclass 35, count 2 2006.224.07:36:30.02#ibcon#read 5, iclass 35, count 2 2006.224.07:36:30.02#ibcon#about to read 6, iclass 35, count 2 2006.224.07:36:30.02#ibcon#read 6, iclass 35, count 2 2006.224.07:36:30.02#ibcon#end of sib2, iclass 35, count 2 2006.224.07:36:30.02#ibcon#*mode == 0, iclass 35, count 2 2006.224.07:36:30.02#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.224.07:36:30.02#ibcon#[25=AT07-06\r\n] 2006.224.07:36:30.02#ibcon#*before write, iclass 35, count 2 2006.224.07:36:30.02#ibcon#enter sib2, iclass 35, count 2 2006.224.07:36:30.02#ibcon#flushed, iclass 35, count 2 2006.224.07:36:30.02#ibcon#about to write, iclass 35, count 2 2006.224.07:36:30.02#ibcon#wrote, iclass 35, count 2 2006.224.07:36:30.02#ibcon#about to read 3, iclass 35, count 2 2006.224.07:36:30.05#ibcon#read 3, iclass 35, count 2 2006.224.07:36:30.05#ibcon#about to read 4, iclass 35, count 2 2006.224.07:36:30.05#ibcon#read 4, iclass 35, count 2 2006.224.07:36:30.05#ibcon#about to read 5, iclass 35, count 2 2006.224.07:36:30.05#ibcon#read 5, iclass 35, count 2 2006.224.07:36:30.05#ibcon#about to read 6, iclass 35, count 2 2006.224.07:36:30.05#ibcon#read 6, iclass 35, count 2 2006.224.07:36:30.05#ibcon#end of sib2, iclass 35, count 2 2006.224.07:36:30.05#ibcon#*after write, iclass 35, count 2 2006.224.07:36:30.05#ibcon#*before return 0, iclass 35, count 2 2006.224.07:36:30.05#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.224.07:36:30.05#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.224.07:36:30.05#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.224.07:36:30.05#ibcon#ireg 7 cls_cnt 0 2006.224.07:36:30.05#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.224.07:36:30.17#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.224.07:36:30.17#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.224.07:36:30.17#ibcon#enter wrdev, iclass 35, count 0 2006.224.07:36:30.17#ibcon#first serial, iclass 35, count 0 2006.224.07:36:30.17#ibcon#enter sib2, iclass 35, count 0 2006.224.07:36:30.17#ibcon#flushed, iclass 35, count 0 2006.224.07:36:30.17#ibcon#about to write, iclass 35, count 0 2006.224.07:36:30.17#ibcon#wrote, iclass 35, count 0 2006.224.07:36:30.17#ibcon#about to read 3, iclass 35, count 0 2006.224.07:36:30.19#ibcon#read 3, iclass 35, count 0 2006.224.07:36:30.19#ibcon#about to read 4, iclass 35, count 0 2006.224.07:36:30.19#ibcon#read 4, iclass 35, count 0 2006.224.07:36:30.19#ibcon#about to read 5, iclass 35, count 0 2006.224.07:36:30.19#ibcon#read 5, iclass 35, count 0 2006.224.07:36:30.19#ibcon#about to read 6, iclass 35, count 0 2006.224.07:36:30.19#ibcon#read 6, iclass 35, count 0 2006.224.07:36:30.19#ibcon#end of sib2, iclass 35, count 0 2006.224.07:36:30.19#ibcon#*mode == 0, iclass 35, count 0 2006.224.07:36:30.19#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.224.07:36:30.19#ibcon#[25=USB\r\n] 2006.224.07:36:30.19#ibcon#*before write, iclass 35, count 0 2006.224.07:36:30.19#ibcon#enter sib2, iclass 35, count 0 2006.224.07:36:30.19#ibcon#flushed, iclass 35, count 0 2006.224.07:36:30.19#ibcon#about to write, iclass 35, count 0 2006.224.07:36:30.19#ibcon#wrote, iclass 35, count 0 2006.224.07:36:30.19#ibcon#about to read 3, iclass 35, count 0 2006.224.07:36:30.22#ibcon#read 3, iclass 35, count 0 2006.224.07:36:30.22#ibcon#about to read 4, iclass 35, count 0 2006.224.07:36:30.22#ibcon#read 4, iclass 35, count 0 2006.224.07:36:30.22#ibcon#about to read 5, iclass 35, count 0 2006.224.07:36:30.22#ibcon#read 5, iclass 35, count 0 2006.224.07:36:30.22#ibcon#about to read 6, iclass 35, count 0 2006.224.07:36:30.22#ibcon#read 6, iclass 35, count 0 2006.224.07:36:30.22#ibcon#end of sib2, iclass 35, count 0 2006.224.07:36:30.22#ibcon#*after write, iclass 35, count 0 2006.224.07:36:30.22#ibcon#*before return 0, iclass 35, count 0 2006.224.07:36:30.22#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.224.07:36:30.22#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.224.07:36:30.22#ibcon#about to clear, iclass 35 cls_cnt 0 2006.224.07:36:30.22#ibcon#cleared, iclass 35 cls_cnt 0 2006.224.07:36:30.22$vc4f8/valo=8,852.99 2006.224.07:36:30.22#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.224.07:36:30.22#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.224.07:36:30.22#ibcon#ireg 17 cls_cnt 0 2006.224.07:36:30.22#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.224.07:36:30.22#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.224.07:36:30.22#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.224.07:36:30.22#ibcon#enter wrdev, iclass 37, count 0 2006.224.07:36:30.22#ibcon#first serial, iclass 37, count 0 2006.224.07:36:30.22#ibcon#enter sib2, iclass 37, count 0 2006.224.07:36:30.22#ibcon#flushed, iclass 37, count 0 2006.224.07:36:30.22#ibcon#about to write, iclass 37, count 0 2006.224.07:36:30.22#ibcon#wrote, iclass 37, count 0 2006.224.07:36:30.22#ibcon#about to read 3, iclass 37, count 0 2006.224.07:36:30.24#ibcon#read 3, iclass 37, count 0 2006.224.07:36:30.24#ibcon#about to read 4, iclass 37, count 0 2006.224.07:36:30.24#ibcon#read 4, iclass 37, count 0 2006.224.07:36:30.24#ibcon#about to read 5, iclass 37, count 0 2006.224.07:36:30.24#ibcon#read 5, iclass 37, count 0 2006.224.07:36:30.24#ibcon#about to read 6, iclass 37, count 0 2006.224.07:36:30.24#ibcon#read 6, iclass 37, count 0 2006.224.07:36:30.24#ibcon#end of sib2, iclass 37, count 0 2006.224.07:36:30.24#ibcon#*mode == 0, iclass 37, count 0 2006.224.07:36:30.24#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.224.07:36:30.24#ibcon#[26=FRQ=08,852.99\r\n] 2006.224.07:36:30.24#ibcon#*before write, iclass 37, count 0 2006.224.07:36:30.24#ibcon#enter sib2, iclass 37, count 0 2006.224.07:36:30.24#ibcon#flushed, iclass 37, count 0 2006.224.07:36:30.24#ibcon#about to write, iclass 37, count 0 2006.224.07:36:30.24#ibcon#wrote, iclass 37, count 0 2006.224.07:36:30.24#ibcon#about to read 3, iclass 37, count 0 2006.224.07:36:30.28#ibcon#read 3, iclass 37, count 0 2006.224.07:36:30.28#ibcon#about to read 4, iclass 37, count 0 2006.224.07:36:30.28#ibcon#read 4, iclass 37, count 0 2006.224.07:36:30.28#ibcon#about to read 5, iclass 37, count 0 2006.224.07:36:30.28#ibcon#read 5, iclass 37, count 0 2006.224.07:36:30.28#ibcon#about to read 6, iclass 37, count 0 2006.224.07:36:30.28#ibcon#read 6, iclass 37, count 0 2006.224.07:36:30.28#ibcon#end of sib2, iclass 37, count 0 2006.224.07:36:30.28#ibcon#*after write, iclass 37, count 0 2006.224.07:36:30.28#ibcon#*before return 0, iclass 37, count 0 2006.224.07:36:30.28#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.224.07:36:30.28#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.224.07:36:30.28#ibcon#about to clear, iclass 37 cls_cnt 0 2006.224.07:36:30.28#ibcon#cleared, iclass 37 cls_cnt 0 2006.224.07:36:30.28$vc4f8/va=8,7 2006.224.07:36:30.28#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.224.07:36:30.28#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.224.07:36:30.28#ibcon#ireg 11 cls_cnt 2 2006.224.07:36:30.28#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.224.07:36:30.34#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.224.07:36:30.34#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.224.07:36:30.34#ibcon#enter wrdev, iclass 39, count 2 2006.224.07:36:30.34#ibcon#first serial, iclass 39, count 2 2006.224.07:36:30.34#ibcon#enter sib2, iclass 39, count 2 2006.224.07:36:30.34#ibcon#flushed, iclass 39, count 2 2006.224.07:36:30.34#ibcon#about to write, iclass 39, count 2 2006.224.07:36:30.34#ibcon#wrote, iclass 39, count 2 2006.224.07:36:30.34#ibcon#about to read 3, iclass 39, count 2 2006.224.07:36:30.36#ibcon#read 3, iclass 39, count 2 2006.224.07:36:30.36#ibcon#about to read 4, iclass 39, count 2 2006.224.07:36:30.36#ibcon#read 4, iclass 39, count 2 2006.224.07:36:30.36#ibcon#about to read 5, iclass 39, count 2 2006.224.07:36:30.36#ibcon#read 5, iclass 39, count 2 2006.224.07:36:30.36#ibcon#about to read 6, iclass 39, count 2 2006.224.07:36:30.36#ibcon#read 6, iclass 39, count 2 2006.224.07:36:30.36#ibcon#end of sib2, iclass 39, count 2 2006.224.07:36:30.36#ibcon#*mode == 0, iclass 39, count 2 2006.224.07:36:30.36#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.224.07:36:30.36#ibcon#[25=AT08-07\r\n] 2006.224.07:36:30.36#ibcon#*before write, iclass 39, count 2 2006.224.07:36:30.36#ibcon#enter sib2, iclass 39, count 2 2006.224.07:36:30.36#ibcon#flushed, iclass 39, count 2 2006.224.07:36:30.36#ibcon#about to write, iclass 39, count 2 2006.224.07:36:30.36#ibcon#wrote, iclass 39, count 2 2006.224.07:36:30.36#ibcon#about to read 3, iclass 39, count 2 2006.224.07:36:30.39#ibcon#read 3, iclass 39, count 2 2006.224.07:36:30.39#ibcon#about to read 4, iclass 39, count 2 2006.224.07:36:30.39#ibcon#read 4, iclass 39, count 2 2006.224.07:36:30.39#ibcon#about to read 5, iclass 39, count 2 2006.224.07:36:30.39#ibcon#read 5, iclass 39, count 2 2006.224.07:36:30.39#ibcon#about to read 6, iclass 39, count 2 2006.224.07:36:30.39#ibcon#read 6, iclass 39, count 2 2006.224.07:36:30.39#ibcon#end of sib2, iclass 39, count 2 2006.224.07:36:30.39#ibcon#*after write, iclass 39, count 2 2006.224.07:36:30.39#ibcon#*before return 0, iclass 39, count 2 2006.224.07:36:30.39#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.224.07:36:30.39#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.224.07:36:30.39#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.224.07:36:30.39#ibcon#ireg 7 cls_cnt 0 2006.224.07:36:30.39#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.224.07:36:30.51#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.224.07:36:30.51#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.224.07:36:30.51#ibcon#enter wrdev, iclass 39, count 0 2006.224.07:36:30.51#ibcon#first serial, iclass 39, count 0 2006.224.07:36:30.51#ibcon#enter sib2, iclass 39, count 0 2006.224.07:36:30.51#ibcon#flushed, iclass 39, count 0 2006.224.07:36:30.51#ibcon#about to write, iclass 39, count 0 2006.224.07:36:30.51#ibcon#wrote, iclass 39, count 0 2006.224.07:36:30.51#ibcon#about to read 3, iclass 39, count 0 2006.224.07:36:30.53#ibcon#read 3, iclass 39, count 0 2006.224.07:36:30.53#ibcon#about to read 4, iclass 39, count 0 2006.224.07:36:30.53#ibcon#read 4, iclass 39, count 0 2006.224.07:36:30.53#ibcon#about to read 5, iclass 39, count 0 2006.224.07:36:30.53#ibcon#read 5, iclass 39, count 0 2006.224.07:36:30.53#ibcon#about to read 6, iclass 39, count 0 2006.224.07:36:30.53#ibcon#read 6, iclass 39, count 0 2006.224.07:36:30.53#ibcon#end of sib2, iclass 39, count 0 2006.224.07:36:30.53#ibcon#*mode == 0, iclass 39, count 0 2006.224.07:36:30.53#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.224.07:36:30.53#ibcon#[25=USB\r\n] 2006.224.07:36:30.53#ibcon#*before write, iclass 39, count 0 2006.224.07:36:30.53#ibcon#enter sib2, iclass 39, count 0 2006.224.07:36:30.53#ibcon#flushed, iclass 39, count 0 2006.224.07:36:30.53#ibcon#about to write, iclass 39, count 0 2006.224.07:36:30.53#ibcon#wrote, iclass 39, count 0 2006.224.07:36:30.53#ibcon#about to read 3, iclass 39, count 0 2006.224.07:36:30.56#ibcon#read 3, iclass 39, count 0 2006.224.07:36:30.56#ibcon#about to read 4, iclass 39, count 0 2006.224.07:36:30.56#ibcon#read 4, iclass 39, count 0 2006.224.07:36:30.56#ibcon#about to read 5, iclass 39, count 0 2006.224.07:36:30.56#ibcon#read 5, iclass 39, count 0 2006.224.07:36:30.56#ibcon#about to read 6, iclass 39, count 0 2006.224.07:36:30.56#ibcon#read 6, iclass 39, count 0 2006.224.07:36:30.56#ibcon#end of sib2, iclass 39, count 0 2006.224.07:36:30.56#ibcon#*after write, iclass 39, count 0 2006.224.07:36:30.56#ibcon#*before return 0, iclass 39, count 0 2006.224.07:36:30.56#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.224.07:36:30.56#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.224.07:36:30.56#ibcon#about to clear, iclass 39 cls_cnt 0 2006.224.07:36:30.56#ibcon#cleared, iclass 39 cls_cnt 0 2006.224.07:36:30.56$vc4f8/vblo=1,632.99 2006.224.07:36:30.56#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.224.07:36:30.56#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.224.07:36:30.56#ibcon#ireg 17 cls_cnt 0 2006.224.07:36:30.56#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.224.07:36:30.56#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.224.07:36:30.56#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.224.07:36:30.56#ibcon#enter wrdev, iclass 3, count 0 2006.224.07:36:30.56#ibcon#first serial, iclass 3, count 0 2006.224.07:36:30.56#ibcon#enter sib2, iclass 3, count 0 2006.224.07:36:30.56#ibcon#flushed, iclass 3, count 0 2006.224.07:36:30.56#ibcon#about to write, iclass 3, count 0 2006.224.07:36:30.56#ibcon#wrote, iclass 3, count 0 2006.224.07:36:30.56#ibcon#about to read 3, iclass 3, count 0 2006.224.07:36:30.58#ibcon#read 3, iclass 3, count 0 2006.224.07:36:30.58#ibcon#about to read 4, iclass 3, count 0 2006.224.07:36:30.58#ibcon#read 4, iclass 3, count 0 2006.224.07:36:30.58#ibcon#about to read 5, iclass 3, count 0 2006.224.07:36:30.58#ibcon#read 5, iclass 3, count 0 2006.224.07:36:30.58#ibcon#about to read 6, iclass 3, count 0 2006.224.07:36:30.58#ibcon#read 6, iclass 3, count 0 2006.224.07:36:30.58#ibcon#end of sib2, iclass 3, count 0 2006.224.07:36:30.58#ibcon#*mode == 0, iclass 3, count 0 2006.224.07:36:30.58#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.224.07:36:30.58#ibcon#[28=FRQ=01,632.99\r\n] 2006.224.07:36:30.58#ibcon#*before write, iclass 3, count 0 2006.224.07:36:30.58#ibcon#enter sib2, iclass 3, count 0 2006.224.07:36:30.58#ibcon#flushed, iclass 3, count 0 2006.224.07:36:30.58#ibcon#about to write, iclass 3, count 0 2006.224.07:36:30.58#ibcon#wrote, iclass 3, count 0 2006.224.07:36:30.58#ibcon#about to read 3, iclass 3, count 0 2006.224.07:36:30.62#ibcon#read 3, iclass 3, count 0 2006.224.07:36:30.62#ibcon#about to read 4, iclass 3, count 0 2006.224.07:36:30.62#ibcon#read 4, iclass 3, count 0 2006.224.07:36:30.62#ibcon#about to read 5, iclass 3, count 0 2006.224.07:36:30.62#ibcon#read 5, iclass 3, count 0 2006.224.07:36:30.62#ibcon#about to read 6, iclass 3, count 0 2006.224.07:36:30.62#ibcon#read 6, iclass 3, count 0 2006.224.07:36:30.62#ibcon#end of sib2, iclass 3, count 0 2006.224.07:36:30.62#ibcon#*after write, iclass 3, count 0 2006.224.07:36:30.62#ibcon#*before return 0, iclass 3, count 0 2006.224.07:36:30.62#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.224.07:36:30.62#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.224.07:36:30.62#ibcon#about to clear, iclass 3 cls_cnt 0 2006.224.07:36:30.62#ibcon#cleared, iclass 3 cls_cnt 0 2006.224.07:36:30.62$vc4f8/vb=1,4 2006.224.07:36:30.62#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.224.07:36:30.62#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.224.07:36:30.62#ibcon#ireg 11 cls_cnt 2 2006.224.07:36:30.62#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.224.07:36:30.62#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.224.07:36:30.62#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.224.07:36:30.62#ibcon#enter wrdev, iclass 5, count 2 2006.224.07:36:30.62#ibcon#first serial, iclass 5, count 2 2006.224.07:36:30.62#ibcon#enter sib2, iclass 5, count 2 2006.224.07:36:30.62#ibcon#flushed, iclass 5, count 2 2006.224.07:36:30.62#ibcon#about to write, iclass 5, count 2 2006.224.07:36:30.62#ibcon#wrote, iclass 5, count 2 2006.224.07:36:30.62#ibcon#about to read 3, iclass 5, count 2 2006.224.07:36:30.64#ibcon#read 3, iclass 5, count 2 2006.224.07:36:30.64#ibcon#about to read 4, iclass 5, count 2 2006.224.07:36:30.64#ibcon#read 4, iclass 5, count 2 2006.224.07:36:30.64#ibcon#about to read 5, iclass 5, count 2 2006.224.07:36:30.64#ibcon#read 5, iclass 5, count 2 2006.224.07:36:30.64#ibcon#about to read 6, iclass 5, count 2 2006.224.07:36:30.64#ibcon#read 6, iclass 5, count 2 2006.224.07:36:30.64#ibcon#end of sib2, iclass 5, count 2 2006.224.07:36:30.64#ibcon#*mode == 0, iclass 5, count 2 2006.224.07:36:30.64#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.224.07:36:30.64#ibcon#[27=AT01-04\r\n] 2006.224.07:36:30.64#ibcon#*before write, iclass 5, count 2 2006.224.07:36:30.64#ibcon#enter sib2, iclass 5, count 2 2006.224.07:36:30.64#ibcon#flushed, iclass 5, count 2 2006.224.07:36:30.64#ibcon#about to write, iclass 5, count 2 2006.224.07:36:30.64#ibcon#wrote, iclass 5, count 2 2006.224.07:36:30.64#ibcon#about to read 3, iclass 5, count 2 2006.224.07:36:30.67#ibcon#read 3, iclass 5, count 2 2006.224.07:36:30.67#ibcon#about to read 4, iclass 5, count 2 2006.224.07:36:30.67#ibcon#read 4, iclass 5, count 2 2006.224.07:36:30.67#ibcon#about to read 5, iclass 5, count 2 2006.224.07:36:30.67#ibcon#read 5, iclass 5, count 2 2006.224.07:36:30.67#ibcon#about to read 6, iclass 5, count 2 2006.224.07:36:30.67#ibcon#read 6, iclass 5, count 2 2006.224.07:36:30.67#ibcon#end of sib2, iclass 5, count 2 2006.224.07:36:30.67#ibcon#*after write, iclass 5, count 2 2006.224.07:36:30.67#ibcon#*before return 0, iclass 5, count 2 2006.224.07:36:30.67#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.224.07:36:30.67#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.224.07:36:30.67#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.224.07:36:30.67#ibcon#ireg 7 cls_cnt 0 2006.224.07:36:30.67#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.224.07:36:30.79#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.224.07:36:30.79#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.224.07:36:30.79#ibcon#enter wrdev, iclass 5, count 0 2006.224.07:36:30.79#ibcon#first serial, iclass 5, count 0 2006.224.07:36:30.79#ibcon#enter sib2, iclass 5, count 0 2006.224.07:36:30.79#ibcon#flushed, iclass 5, count 0 2006.224.07:36:30.79#ibcon#about to write, iclass 5, count 0 2006.224.07:36:30.79#ibcon#wrote, iclass 5, count 0 2006.224.07:36:30.79#ibcon#about to read 3, iclass 5, count 0 2006.224.07:36:30.81#ibcon#read 3, iclass 5, count 0 2006.224.07:36:30.81#ibcon#about to read 4, iclass 5, count 0 2006.224.07:36:30.81#ibcon#read 4, iclass 5, count 0 2006.224.07:36:30.81#ibcon#about to read 5, iclass 5, count 0 2006.224.07:36:30.81#ibcon#read 5, iclass 5, count 0 2006.224.07:36:30.81#ibcon#about to read 6, iclass 5, count 0 2006.224.07:36:30.81#ibcon#read 6, iclass 5, count 0 2006.224.07:36:30.81#ibcon#end of sib2, iclass 5, count 0 2006.224.07:36:30.81#ibcon#*mode == 0, iclass 5, count 0 2006.224.07:36:30.81#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.224.07:36:30.81#ibcon#[27=USB\r\n] 2006.224.07:36:30.81#ibcon#*before write, iclass 5, count 0 2006.224.07:36:30.81#ibcon#enter sib2, iclass 5, count 0 2006.224.07:36:30.81#ibcon#flushed, iclass 5, count 0 2006.224.07:36:30.81#ibcon#about to write, iclass 5, count 0 2006.224.07:36:30.81#ibcon#wrote, iclass 5, count 0 2006.224.07:36:30.81#ibcon#about to read 3, iclass 5, count 0 2006.224.07:36:30.84#ibcon#read 3, iclass 5, count 0 2006.224.07:36:30.84#ibcon#about to read 4, iclass 5, count 0 2006.224.07:36:30.84#ibcon#read 4, iclass 5, count 0 2006.224.07:36:30.84#ibcon#about to read 5, iclass 5, count 0 2006.224.07:36:30.84#ibcon#read 5, iclass 5, count 0 2006.224.07:36:30.84#ibcon#about to read 6, iclass 5, count 0 2006.224.07:36:30.84#ibcon#read 6, iclass 5, count 0 2006.224.07:36:30.84#ibcon#end of sib2, iclass 5, count 0 2006.224.07:36:30.84#ibcon#*after write, iclass 5, count 0 2006.224.07:36:30.84#ibcon#*before return 0, iclass 5, count 0 2006.224.07:36:30.84#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.224.07:36:30.84#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.224.07:36:30.84#ibcon#about to clear, iclass 5 cls_cnt 0 2006.224.07:36:30.84#ibcon#cleared, iclass 5 cls_cnt 0 2006.224.07:36:30.84$vc4f8/vblo=2,640.99 2006.224.07:36:30.84#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.224.07:36:30.84#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.224.07:36:30.84#ibcon#ireg 17 cls_cnt 0 2006.224.07:36:30.84#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.224.07:36:30.84#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.224.07:36:30.84#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.224.07:36:30.84#ibcon#enter wrdev, iclass 7, count 0 2006.224.07:36:30.84#ibcon#first serial, iclass 7, count 0 2006.224.07:36:30.84#ibcon#enter sib2, iclass 7, count 0 2006.224.07:36:30.84#ibcon#flushed, iclass 7, count 0 2006.224.07:36:30.84#ibcon#about to write, iclass 7, count 0 2006.224.07:36:30.84#ibcon#wrote, iclass 7, count 0 2006.224.07:36:30.84#ibcon#about to read 3, iclass 7, count 0 2006.224.07:36:30.86#ibcon#read 3, iclass 7, count 0 2006.224.07:36:30.86#ibcon#about to read 4, iclass 7, count 0 2006.224.07:36:30.86#ibcon#read 4, iclass 7, count 0 2006.224.07:36:30.86#ibcon#about to read 5, iclass 7, count 0 2006.224.07:36:30.86#ibcon#read 5, iclass 7, count 0 2006.224.07:36:30.86#ibcon#about to read 6, iclass 7, count 0 2006.224.07:36:30.86#ibcon#read 6, iclass 7, count 0 2006.224.07:36:30.86#ibcon#end of sib2, iclass 7, count 0 2006.224.07:36:30.86#ibcon#*mode == 0, iclass 7, count 0 2006.224.07:36:30.86#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.224.07:36:30.86#ibcon#[28=FRQ=02,640.99\r\n] 2006.224.07:36:30.86#ibcon#*before write, iclass 7, count 0 2006.224.07:36:30.86#ibcon#enter sib2, iclass 7, count 0 2006.224.07:36:30.86#ibcon#flushed, iclass 7, count 0 2006.224.07:36:30.86#ibcon#about to write, iclass 7, count 0 2006.224.07:36:30.86#ibcon#wrote, iclass 7, count 0 2006.224.07:36:30.86#ibcon#about to read 3, iclass 7, count 0 2006.224.07:36:30.90#ibcon#read 3, iclass 7, count 0 2006.224.07:36:30.90#ibcon#about to read 4, iclass 7, count 0 2006.224.07:36:30.90#ibcon#read 4, iclass 7, count 0 2006.224.07:36:30.90#ibcon#about to read 5, iclass 7, count 0 2006.224.07:36:30.90#ibcon#read 5, iclass 7, count 0 2006.224.07:36:30.90#ibcon#about to read 6, iclass 7, count 0 2006.224.07:36:30.90#ibcon#read 6, iclass 7, count 0 2006.224.07:36:30.90#ibcon#end of sib2, iclass 7, count 0 2006.224.07:36:30.90#ibcon#*after write, iclass 7, count 0 2006.224.07:36:30.90#ibcon#*before return 0, iclass 7, count 0 2006.224.07:36:30.90#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.224.07:36:30.90#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.224.07:36:30.90#ibcon#about to clear, iclass 7 cls_cnt 0 2006.224.07:36:30.90#ibcon#cleared, iclass 7 cls_cnt 0 2006.224.07:36:30.90$vc4f8/vb=2,4 2006.224.07:36:30.90#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.224.07:36:30.90#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.224.07:36:30.90#ibcon#ireg 11 cls_cnt 2 2006.224.07:36:30.90#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.224.07:36:30.96#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.224.07:36:30.96#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.224.07:36:30.96#ibcon#enter wrdev, iclass 11, count 2 2006.224.07:36:30.96#ibcon#first serial, iclass 11, count 2 2006.224.07:36:30.96#ibcon#enter sib2, iclass 11, count 2 2006.224.07:36:30.96#ibcon#flushed, iclass 11, count 2 2006.224.07:36:30.96#ibcon#about to write, iclass 11, count 2 2006.224.07:36:30.96#ibcon#wrote, iclass 11, count 2 2006.224.07:36:30.96#ibcon#about to read 3, iclass 11, count 2 2006.224.07:36:30.98#ibcon#read 3, iclass 11, count 2 2006.224.07:36:30.98#ibcon#about to read 4, iclass 11, count 2 2006.224.07:36:30.98#ibcon#read 4, iclass 11, count 2 2006.224.07:36:30.98#ibcon#about to read 5, iclass 11, count 2 2006.224.07:36:30.98#ibcon#read 5, iclass 11, count 2 2006.224.07:36:30.98#ibcon#about to read 6, iclass 11, count 2 2006.224.07:36:30.98#ibcon#read 6, iclass 11, count 2 2006.224.07:36:30.98#ibcon#end of sib2, iclass 11, count 2 2006.224.07:36:30.98#ibcon#*mode == 0, iclass 11, count 2 2006.224.07:36:30.98#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.224.07:36:30.98#ibcon#[27=AT02-04\r\n] 2006.224.07:36:30.98#ibcon#*before write, iclass 11, count 2 2006.224.07:36:30.98#ibcon#enter sib2, iclass 11, count 2 2006.224.07:36:30.98#ibcon#flushed, iclass 11, count 2 2006.224.07:36:30.98#ibcon#about to write, iclass 11, count 2 2006.224.07:36:30.98#ibcon#wrote, iclass 11, count 2 2006.224.07:36:30.98#ibcon#about to read 3, iclass 11, count 2 2006.224.07:36:31.01#ibcon#read 3, iclass 11, count 2 2006.224.07:36:31.01#ibcon#about to read 4, iclass 11, count 2 2006.224.07:36:31.01#ibcon#read 4, iclass 11, count 2 2006.224.07:36:31.01#ibcon#about to read 5, iclass 11, count 2 2006.224.07:36:31.01#ibcon#read 5, iclass 11, count 2 2006.224.07:36:31.01#ibcon#about to read 6, iclass 11, count 2 2006.224.07:36:31.01#ibcon#read 6, iclass 11, count 2 2006.224.07:36:31.01#ibcon#end of sib2, iclass 11, count 2 2006.224.07:36:31.01#ibcon#*after write, iclass 11, count 2 2006.224.07:36:31.01#ibcon#*before return 0, iclass 11, count 2 2006.224.07:36:31.01#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.224.07:36:31.01#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.224.07:36:31.01#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.224.07:36:31.01#ibcon#ireg 7 cls_cnt 0 2006.224.07:36:31.01#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.224.07:36:31.13#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.224.07:36:31.13#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.224.07:36:31.13#ibcon#enter wrdev, iclass 11, count 0 2006.224.07:36:31.13#ibcon#first serial, iclass 11, count 0 2006.224.07:36:31.13#ibcon#enter sib2, iclass 11, count 0 2006.224.07:36:31.13#ibcon#flushed, iclass 11, count 0 2006.224.07:36:31.13#ibcon#about to write, iclass 11, count 0 2006.224.07:36:31.13#ibcon#wrote, iclass 11, count 0 2006.224.07:36:31.13#ibcon#about to read 3, iclass 11, count 0 2006.224.07:36:31.15#ibcon#read 3, iclass 11, count 0 2006.224.07:36:31.15#ibcon#about to read 4, iclass 11, count 0 2006.224.07:36:31.15#ibcon#read 4, iclass 11, count 0 2006.224.07:36:31.15#ibcon#about to read 5, iclass 11, count 0 2006.224.07:36:31.15#ibcon#read 5, iclass 11, count 0 2006.224.07:36:31.15#ibcon#about to read 6, iclass 11, count 0 2006.224.07:36:31.15#ibcon#read 6, iclass 11, count 0 2006.224.07:36:31.15#ibcon#end of sib2, iclass 11, count 0 2006.224.07:36:31.15#ibcon#*mode == 0, iclass 11, count 0 2006.224.07:36:31.15#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.224.07:36:31.15#ibcon#[27=USB\r\n] 2006.224.07:36:31.15#ibcon#*before write, iclass 11, count 0 2006.224.07:36:31.15#ibcon#enter sib2, iclass 11, count 0 2006.224.07:36:31.15#ibcon#flushed, iclass 11, count 0 2006.224.07:36:31.15#ibcon#about to write, iclass 11, count 0 2006.224.07:36:31.15#ibcon#wrote, iclass 11, count 0 2006.224.07:36:31.15#ibcon#about to read 3, iclass 11, count 0 2006.224.07:36:31.18#ibcon#read 3, iclass 11, count 0 2006.224.07:36:31.18#ibcon#about to read 4, iclass 11, count 0 2006.224.07:36:31.18#ibcon#read 4, iclass 11, count 0 2006.224.07:36:31.18#ibcon#about to read 5, iclass 11, count 0 2006.224.07:36:31.18#ibcon#read 5, iclass 11, count 0 2006.224.07:36:31.18#ibcon#about to read 6, iclass 11, count 0 2006.224.07:36:31.18#ibcon#read 6, iclass 11, count 0 2006.224.07:36:31.18#ibcon#end of sib2, iclass 11, count 0 2006.224.07:36:31.18#ibcon#*after write, iclass 11, count 0 2006.224.07:36:31.18#ibcon#*before return 0, iclass 11, count 0 2006.224.07:36:31.18#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.224.07:36:31.18#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.224.07:36:31.18#ibcon#about to clear, iclass 11 cls_cnt 0 2006.224.07:36:31.18#ibcon#cleared, iclass 11 cls_cnt 0 2006.224.07:36:31.18$vc4f8/vblo=3,656.99 2006.224.07:36:31.18#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.224.07:36:31.18#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.224.07:36:31.18#ibcon#ireg 17 cls_cnt 0 2006.224.07:36:31.18#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.224.07:36:31.18#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.224.07:36:31.18#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.224.07:36:31.18#ibcon#enter wrdev, iclass 13, count 0 2006.224.07:36:31.18#ibcon#first serial, iclass 13, count 0 2006.224.07:36:31.18#ibcon#enter sib2, iclass 13, count 0 2006.224.07:36:31.18#ibcon#flushed, iclass 13, count 0 2006.224.07:36:31.18#ibcon#about to write, iclass 13, count 0 2006.224.07:36:31.18#ibcon#wrote, iclass 13, count 0 2006.224.07:36:31.18#ibcon#about to read 3, iclass 13, count 0 2006.224.07:36:31.20#ibcon#read 3, iclass 13, count 0 2006.224.07:36:31.20#ibcon#about to read 4, iclass 13, count 0 2006.224.07:36:31.20#ibcon#read 4, iclass 13, count 0 2006.224.07:36:31.20#ibcon#about to read 5, iclass 13, count 0 2006.224.07:36:31.20#ibcon#read 5, iclass 13, count 0 2006.224.07:36:31.20#ibcon#about to read 6, iclass 13, count 0 2006.224.07:36:31.20#ibcon#read 6, iclass 13, count 0 2006.224.07:36:31.20#ibcon#end of sib2, iclass 13, count 0 2006.224.07:36:31.20#ibcon#*mode == 0, iclass 13, count 0 2006.224.07:36:31.20#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.224.07:36:31.20#ibcon#[28=FRQ=03,656.99\r\n] 2006.224.07:36:31.20#ibcon#*before write, iclass 13, count 0 2006.224.07:36:31.20#ibcon#enter sib2, iclass 13, count 0 2006.224.07:36:31.20#ibcon#flushed, iclass 13, count 0 2006.224.07:36:31.20#ibcon#about to write, iclass 13, count 0 2006.224.07:36:31.20#ibcon#wrote, iclass 13, count 0 2006.224.07:36:31.20#ibcon#about to read 3, iclass 13, count 0 2006.224.07:36:31.24#ibcon#read 3, iclass 13, count 0 2006.224.07:36:31.24#ibcon#about to read 4, iclass 13, count 0 2006.224.07:36:31.24#ibcon#read 4, iclass 13, count 0 2006.224.07:36:31.24#ibcon#about to read 5, iclass 13, count 0 2006.224.07:36:31.24#ibcon#read 5, iclass 13, count 0 2006.224.07:36:31.24#ibcon#about to read 6, iclass 13, count 0 2006.224.07:36:31.24#ibcon#read 6, iclass 13, count 0 2006.224.07:36:31.24#ibcon#end of sib2, iclass 13, count 0 2006.224.07:36:31.24#ibcon#*after write, iclass 13, count 0 2006.224.07:36:31.24#ibcon#*before return 0, iclass 13, count 0 2006.224.07:36:31.24#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.224.07:36:31.24#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.224.07:36:31.24#ibcon#about to clear, iclass 13 cls_cnt 0 2006.224.07:36:31.24#ibcon#cleared, iclass 13 cls_cnt 0 2006.224.07:36:31.24$vc4f8/vb=3,4 2006.224.07:36:31.24#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.224.07:36:31.24#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.224.07:36:31.24#ibcon#ireg 11 cls_cnt 2 2006.224.07:36:31.24#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.224.07:36:31.30#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.224.07:36:31.30#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.224.07:36:31.30#ibcon#enter wrdev, iclass 15, count 2 2006.224.07:36:31.30#ibcon#first serial, iclass 15, count 2 2006.224.07:36:31.30#ibcon#enter sib2, iclass 15, count 2 2006.224.07:36:31.30#ibcon#flushed, iclass 15, count 2 2006.224.07:36:31.30#ibcon#about to write, iclass 15, count 2 2006.224.07:36:31.30#ibcon#wrote, iclass 15, count 2 2006.224.07:36:31.30#ibcon#about to read 3, iclass 15, count 2 2006.224.07:36:31.32#ibcon#read 3, iclass 15, count 2 2006.224.07:36:31.32#ibcon#about to read 4, iclass 15, count 2 2006.224.07:36:31.32#ibcon#read 4, iclass 15, count 2 2006.224.07:36:31.32#ibcon#about to read 5, iclass 15, count 2 2006.224.07:36:31.32#ibcon#read 5, iclass 15, count 2 2006.224.07:36:31.32#ibcon#about to read 6, iclass 15, count 2 2006.224.07:36:31.32#ibcon#read 6, iclass 15, count 2 2006.224.07:36:31.32#ibcon#end of sib2, iclass 15, count 2 2006.224.07:36:31.32#ibcon#*mode == 0, iclass 15, count 2 2006.224.07:36:31.32#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.224.07:36:31.32#ibcon#[27=AT03-04\r\n] 2006.224.07:36:31.32#ibcon#*before write, iclass 15, count 2 2006.224.07:36:31.32#ibcon#enter sib2, iclass 15, count 2 2006.224.07:36:31.32#ibcon#flushed, iclass 15, count 2 2006.224.07:36:31.32#ibcon#about to write, iclass 15, count 2 2006.224.07:36:31.32#ibcon#wrote, iclass 15, count 2 2006.224.07:36:31.32#ibcon#about to read 3, iclass 15, count 2 2006.224.07:36:31.35#ibcon#read 3, iclass 15, count 2 2006.224.07:36:31.35#ibcon#about to read 4, iclass 15, count 2 2006.224.07:36:31.35#ibcon#read 4, iclass 15, count 2 2006.224.07:36:31.35#ibcon#about to read 5, iclass 15, count 2 2006.224.07:36:31.35#ibcon#read 5, iclass 15, count 2 2006.224.07:36:31.35#ibcon#about to read 6, iclass 15, count 2 2006.224.07:36:31.35#ibcon#read 6, iclass 15, count 2 2006.224.07:36:31.35#ibcon#end of sib2, iclass 15, count 2 2006.224.07:36:31.35#ibcon#*after write, iclass 15, count 2 2006.224.07:36:31.35#ibcon#*before return 0, iclass 15, count 2 2006.224.07:36:31.35#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.224.07:36:31.35#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.224.07:36:31.35#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.224.07:36:31.35#ibcon#ireg 7 cls_cnt 0 2006.224.07:36:31.35#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.224.07:36:31.47#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.224.07:36:31.47#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.224.07:36:31.47#ibcon#enter wrdev, iclass 15, count 0 2006.224.07:36:31.47#ibcon#first serial, iclass 15, count 0 2006.224.07:36:31.47#ibcon#enter sib2, iclass 15, count 0 2006.224.07:36:31.47#ibcon#flushed, iclass 15, count 0 2006.224.07:36:31.47#ibcon#about to write, iclass 15, count 0 2006.224.07:36:31.47#ibcon#wrote, iclass 15, count 0 2006.224.07:36:31.47#ibcon#about to read 3, iclass 15, count 0 2006.224.07:36:31.49#ibcon#read 3, iclass 15, count 0 2006.224.07:36:31.49#ibcon#about to read 4, iclass 15, count 0 2006.224.07:36:31.49#ibcon#read 4, iclass 15, count 0 2006.224.07:36:31.49#ibcon#about to read 5, iclass 15, count 0 2006.224.07:36:31.49#ibcon#read 5, iclass 15, count 0 2006.224.07:36:31.49#ibcon#about to read 6, iclass 15, count 0 2006.224.07:36:31.49#ibcon#read 6, iclass 15, count 0 2006.224.07:36:31.49#ibcon#end of sib2, iclass 15, count 0 2006.224.07:36:31.49#ibcon#*mode == 0, iclass 15, count 0 2006.224.07:36:31.49#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.224.07:36:31.49#ibcon#[27=USB\r\n] 2006.224.07:36:31.49#ibcon#*before write, iclass 15, count 0 2006.224.07:36:31.49#ibcon#enter sib2, iclass 15, count 0 2006.224.07:36:31.49#ibcon#flushed, iclass 15, count 0 2006.224.07:36:31.49#ibcon#about to write, iclass 15, count 0 2006.224.07:36:31.49#ibcon#wrote, iclass 15, count 0 2006.224.07:36:31.49#ibcon#about to read 3, iclass 15, count 0 2006.224.07:36:31.52#ibcon#read 3, iclass 15, count 0 2006.224.07:36:31.52#ibcon#about to read 4, iclass 15, count 0 2006.224.07:36:31.52#ibcon#read 4, iclass 15, count 0 2006.224.07:36:31.52#ibcon#about to read 5, iclass 15, count 0 2006.224.07:36:31.52#ibcon#read 5, iclass 15, count 0 2006.224.07:36:31.52#ibcon#about to read 6, iclass 15, count 0 2006.224.07:36:31.52#ibcon#read 6, iclass 15, count 0 2006.224.07:36:31.52#ibcon#end of sib2, iclass 15, count 0 2006.224.07:36:31.52#ibcon#*after write, iclass 15, count 0 2006.224.07:36:31.52#ibcon#*before return 0, iclass 15, count 0 2006.224.07:36:31.52#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.224.07:36:31.52#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.224.07:36:31.52#ibcon#about to clear, iclass 15 cls_cnt 0 2006.224.07:36:31.52#ibcon#cleared, iclass 15 cls_cnt 0 2006.224.07:36:31.52$vc4f8/vblo=4,712.99 2006.224.07:36:31.52#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.224.07:36:31.52#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.224.07:36:31.52#ibcon#ireg 17 cls_cnt 0 2006.224.07:36:31.52#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.224.07:36:31.52#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.224.07:36:31.52#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.224.07:36:31.52#ibcon#enter wrdev, iclass 17, count 0 2006.224.07:36:31.52#ibcon#first serial, iclass 17, count 0 2006.224.07:36:31.52#ibcon#enter sib2, iclass 17, count 0 2006.224.07:36:31.52#ibcon#flushed, iclass 17, count 0 2006.224.07:36:31.52#ibcon#about to write, iclass 17, count 0 2006.224.07:36:31.52#ibcon#wrote, iclass 17, count 0 2006.224.07:36:31.52#ibcon#about to read 3, iclass 17, count 0 2006.224.07:36:31.54#ibcon#read 3, iclass 17, count 0 2006.224.07:36:31.54#ibcon#about to read 4, iclass 17, count 0 2006.224.07:36:31.54#ibcon#read 4, iclass 17, count 0 2006.224.07:36:31.54#ibcon#about to read 5, iclass 17, count 0 2006.224.07:36:31.54#ibcon#read 5, iclass 17, count 0 2006.224.07:36:31.54#ibcon#about to read 6, iclass 17, count 0 2006.224.07:36:31.54#ibcon#read 6, iclass 17, count 0 2006.224.07:36:31.54#ibcon#end of sib2, iclass 17, count 0 2006.224.07:36:31.54#ibcon#*mode == 0, iclass 17, count 0 2006.224.07:36:31.54#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.224.07:36:31.54#ibcon#[28=FRQ=04,712.99\r\n] 2006.224.07:36:31.54#ibcon#*before write, iclass 17, count 0 2006.224.07:36:31.54#ibcon#enter sib2, iclass 17, count 0 2006.224.07:36:31.54#ibcon#flushed, iclass 17, count 0 2006.224.07:36:31.54#ibcon#about to write, iclass 17, count 0 2006.224.07:36:31.54#ibcon#wrote, iclass 17, count 0 2006.224.07:36:31.54#ibcon#about to read 3, iclass 17, count 0 2006.224.07:36:31.58#ibcon#read 3, iclass 17, count 0 2006.224.07:36:31.58#ibcon#about to read 4, iclass 17, count 0 2006.224.07:36:31.58#ibcon#read 4, iclass 17, count 0 2006.224.07:36:31.58#ibcon#about to read 5, iclass 17, count 0 2006.224.07:36:31.58#ibcon#read 5, iclass 17, count 0 2006.224.07:36:31.58#ibcon#about to read 6, iclass 17, count 0 2006.224.07:36:31.58#ibcon#read 6, iclass 17, count 0 2006.224.07:36:31.58#ibcon#end of sib2, iclass 17, count 0 2006.224.07:36:31.58#ibcon#*after write, iclass 17, count 0 2006.224.07:36:31.58#ibcon#*before return 0, iclass 17, count 0 2006.224.07:36:31.58#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.224.07:36:31.58#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.224.07:36:31.58#ibcon#about to clear, iclass 17 cls_cnt 0 2006.224.07:36:31.58#ibcon#cleared, iclass 17 cls_cnt 0 2006.224.07:36:31.58$vc4f8/vb=4,4 2006.224.07:36:31.58#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.224.07:36:31.58#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.224.07:36:31.58#ibcon#ireg 11 cls_cnt 2 2006.224.07:36:31.58#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.224.07:36:31.64#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.224.07:36:31.64#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.224.07:36:31.64#ibcon#enter wrdev, iclass 19, count 2 2006.224.07:36:31.64#ibcon#first serial, iclass 19, count 2 2006.224.07:36:31.64#ibcon#enter sib2, iclass 19, count 2 2006.224.07:36:31.64#ibcon#flushed, iclass 19, count 2 2006.224.07:36:31.64#ibcon#about to write, iclass 19, count 2 2006.224.07:36:31.64#ibcon#wrote, iclass 19, count 2 2006.224.07:36:31.64#ibcon#about to read 3, iclass 19, count 2 2006.224.07:36:31.66#ibcon#read 3, iclass 19, count 2 2006.224.07:36:31.66#ibcon#about to read 4, iclass 19, count 2 2006.224.07:36:31.66#ibcon#read 4, iclass 19, count 2 2006.224.07:36:31.66#ibcon#about to read 5, iclass 19, count 2 2006.224.07:36:31.66#ibcon#read 5, iclass 19, count 2 2006.224.07:36:31.66#ibcon#about to read 6, iclass 19, count 2 2006.224.07:36:31.66#ibcon#read 6, iclass 19, count 2 2006.224.07:36:31.66#ibcon#end of sib2, iclass 19, count 2 2006.224.07:36:31.66#ibcon#*mode == 0, iclass 19, count 2 2006.224.07:36:31.66#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.224.07:36:31.66#ibcon#[27=AT04-04\r\n] 2006.224.07:36:31.66#ibcon#*before write, iclass 19, count 2 2006.224.07:36:31.66#ibcon#enter sib2, iclass 19, count 2 2006.224.07:36:31.66#ibcon#flushed, iclass 19, count 2 2006.224.07:36:31.66#ibcon#about to write, iclass 19, count 2 2006.224.07:36:31.66#ibcon#wrote, iclass 19, count 2 2006.224.07:36:31.66#ibcon#about to read 3, iclass 19, count 2 2006.224.07:36:31.69#ibcon#read 3, iclass 19, count 2 2006.224.07:36:31.69#ibcon#about to read 4, iclass 19, count 2 2006.224.07:36:31.69#ibcon#read 4, iclass 19, count 2 2006.224.07:36:31.69#ibcon#about to read 5, iclass 19, count 2 2006.224.07:36:31.69#ibcon#read 5, iclass 19, count 2 2006.224.07:36:31.69#ibcon#about to read 6, iclass 19, count 2 2006.224.07:36:31.69#ibcon#read 6, iclass 19, count 2 2006.224.07:36:31.69#ibcon#end of sib2, iclass 19, count 2 2006.224.07:36:31.69#ibcon#*after write, iclass 19, count 2 2006.224.07:36:31.69#ibcon#*before return 0, iclass 19, count 2 2006.224.07:36:31.69#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.224.07:36:31.69#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.224.07:36:31.69#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.224.07:36:31.69#ibcon#ireg 7 cls_cnt 0 2006.224.07:36:31.69#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.224.07:36:31.81#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.224.07:36:31.81#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.224.07:36:31.81#ibcon#enter wrdev, iclass 19, count 0 2006.224.07:36:31.81#ibcon#first serial, iclass 19, count 0 2006.224.07:36:31.81#ibcon#enter sib2, iclass 19, count 0 2006.224.07:36:31.81#ibcon#flushed, iclass 19, count 0 2006.224.07:36:31.81#ibcon#about to write, iclass 19, count 0 2006.224.07:36:31.81#ibcon#wrote, iclass 19, count 0 2006.224.07:36:31.81#ibcon#about to read 3, iclass 19, count 0 2006.224.07:36:31.83#ibcon#read 3, iclass 19, count 0 2006.224.07:36:31.83#ibcon#about to read 4, iclass 19, count 0 2006.224.07:36:31.83#ibcon#read 4, iclass 19, count 0 2006.224.07:36:31.83#ibcon#about to read 5, iclass 19, count 0 2006.224.07:36:31.83#ibcon#read 5, iclass 19, count 0 2006.224.07:36:31.83#ibcon#about to read 6, iclass 19, count 0 2006.224.07:36:31.83#ibcon#read 6, iclass 19, count 0 2006.224.07:36:31.83#ibcon#end of sib2, iclass 19, count 0 2006.224.07:36:31.83#ibcon#*mode == 0, iclass 19, count 0 2006.224.07:36:31.83#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.224.07:36:31.83#ibcon#[27=USB\r\n] 2006.224.07:36:31.83#ibcon#*before write, iclass 19, count 0 2006.224.07:36:31.83#ibcon#enter sib2, iclass 19, count 0 2006.224.07:36:31.83#ibcon#flushed, iclass 19, count 0 2006.224.07:36:31.83#ibcon#about to write, iclass 19, count 0 2006.224.07:36:31.83#ibcon#wrote, iclass 19, count 0 2006.224.07:36:31.83#ibcon#about to read 3, iclass 19, count 0 2006.224.07:36:31.86#ibcon#read 3, iclass 19, count 0 2006.224.07:36:31.86#ibcon#about to read 4, iclass 19, count 0 2006.224.07:36:31.86#ibcon#read 4, iclass 19, count 0 2006.224.07:36:31.86#ibcon#about to read 5, iclass 19, count 0 2006.224.07:36:31.86#ibcon#read 5, iclass 19, count 0 2006.224.07:36:31.86#ibcon#about to read 6, iclass 19, count 0 2006.224.07:36:31.86#ibcon#read 6, iclass 19, count 0 2006.224.07:36:31.86#ibcon#end of sib2, iclass 19, count 0 2006.224.07:36:31.86#ibcon#*after write, iclass 19, count 0 2006.224.07:36:31.86#ibcon#*before return 0, iclass 19, count 0 2006.224.07:36:31.86#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.224.07:36:31.86#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.224.07:36:31.86#ibcon#about to clear, iclass 19 cls_cnt 0 2006.224.07:36:31.86#ibcon#cleared, iclass 19 cls_cnt 0 2006.224.07:36:31.86$vc4f8/vblo=5,744.99 2006.224.07:36:31.86#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.224.07:36:31.86#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.224.07:36:31.86#ibcon#ireg 17 cls_cnt 0 2006.224.07:36:31.86#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.224.07:36:31.86#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.224.07:36:31.86#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.224.07:36:31.86#ibcon#enter wrdev, iclass 21, count 0 2006.224.07:36:31.86#ibcon#first serial, iclass 21, count 0 2006.224.07:36:31.86#ibcon#enter sib2, iclass 21, count 0 2006.224.07:36:31.86#ibcon#flushed, iclass 21, count 0 2006.224.07:36:31.86#ibcon#about to write, iclass 21, count 0 2006.224.07:36:31.86#ibcon#wrote, iclass 21, count 0 2006.224.07:36:31.86#ibcon#about to read 3, iclass 21, count 0 2006.224.07:36:31.88#ibcon#read 3, iclass 21, count 0 2006.224.07:36:31.88#ibcon#about to read 4, iclass 21, count 0 2006.224.07:36:31.88#ibcon#read 4, iclass 21, count 0 2006.224.07:36:31.88#ibcon#about to read 5, iclass 21, count 0 2006.224.07:36:31.88#ibcon#read 5, iclass 21, count 0 2006.224.07:36:31.88#ibcon#about to read 6, iclass 21, count 0 2006.224.07:36:31.88#ibcon#read 6, iclass 21, count 0 2006.224.07:36:31.88#ibcon#end of sib2, iclass 21, count 0 2006.224.07:36:31.88#ibcon#*mode == 0, iclass 21, count 0 2006.224.07:36:31.88#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.224.07:36:31.88#ibcon#[28=FRQ=05,744.99\r\n] 2006.224.07:36:31.88#ibcon#*before write, iclass 21, count 0 2006.224.07:36:31.88#ibcon#enter sib2, iclass 21, count 0 2006.224.07:36:31.88#ibcon#flushed, iclass 21, count 0 2006.224.07:36:31.88#ibcon#about to write, iclass 21, count 0 2006.224.07:36:31.88#ibcon#wrote, iclass 21, count 0 2006.224.07:36:31.88#ibcon#about to read 3, iclass 21, count 0 2006.224.07:36:31.92#ibcon#read 3, iclass 21, count 0 2006.224.07:36:31.92#ibcon#about to read 4, iclass 21, count 0 2006.224.07:36:31.92#ibcon#read 4, iclass 21, count 0 2006.224.07:36:31.92#ibcon#about to read 5, iclass 21, count 0 2006.224.07:36:31.92#ibcon#read 5, iclass 21, count 0 2006.224.07:36:31.92#ibcon#about to read 6, iclass 21, count 0 2006.224.07:36:31.92#ibcon#read 6, iclass 21, count 0 2006.224.07:36:31.92#ibcon#end of sib2, iclass 21, count 0 2006.224.07:36:31.92#ibcon#*after write, iclass 21, count 0 2006.224.07:36:31.92#ibcon#*before return 0, iclass 21, count 0 2006.224.07:36:31.92#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.224.07:36:31.92#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.224.07:36:31.92#ibcon#about to clear, iclass 21 cls_cnt 0 2006.224.07:36:31.92#ibcon#cleared, iclass 21 cls_cnt 0 2006.224.07:36:31.92$vc4f8/vb=5,4 2006.224.07:36:31.92#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.224.07:36:31.92#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.224.07:36:31.92#ibcon#ireg 11 cls_cnt 2 2006.224.07:36:31.92#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.224.07:36:31.98#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.224.07:36:31.98#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.224.07:36:31.98#ibcon#enter wrdev, iclass 23, count 2 2006.224.07:36:31.98#ibcon#first serial, iclass 23, count 2 2006.224.07:36:31.98#ibcon#enter sib2, iclass 23, count 2 2006.224.07:36:31.98#ibcon#flushed, iclass 23, count 2 2006.224.07:36:31.98#ibcon#about to write, iclass 23, count 2 2006.224.07:36:31.98#ibcon#wrote, iclass 23, count 2 2006.224.07:36:31.98#ibcon#about to read 3, iclass 23, count 2 2006.224.07:36:32.00#ibcon#read 3, iclass 23, count 2 2006.224.07:36:32.00#ibcon#about to read 4, iclass 23, count 2 2006.224.07:36:32.00#ibcon#read 4, iclass 23, count 2 2006.224.07:36:32.00#ibcon#about to read 5, iclass 23, count 2 2006.224.07:36:32.00#ibcon#read 5, iclass 23, count 2 2006.224.07:36:32.00#ibcon#about to read 6, iclass 23, count 2 2006.224.07:36:32.00#ibcon#read 6, iclass 23, count 2 2006.224.07:36:32.00#ibcon#end of sib2, iclass 23, count 2 2006.224.07:36:32.00#ibcon#*mode == 0, iclass 23, count 2 2006.224.07:36:32.00#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.224.07:36:32.00#ibcon#[27=AT05-04\r\n] 2006.224.07:36:32.00#ibcon#*before write, iclass 23, count 2 2006.224.07:36:32.00#ibcon#enter sib2, iclass 23, count 2 2006.224.07:36:32.00#ibcon#flushed, iclass 23, count 2 2006.224.07:36:32.00#ibcon#about to write, iclass 23, count 2 2006.224.07:36:32.00#ibcon#wrote, iclass 23, count 2 2006.224.07:36:32.00#ibcon#about to read 3, iclass 23, count 2 2006.224.07:36:32.03#ibcon#read 3, iclass 23, count 2 2006.224.07:36:32.03#ibcon#about to read 4, iclass 23, count 2 2006.224.07:36:32.03#ibcon#read 4, iclass 23, count 2 2006.224.07:36:32.03#ibcon#about to read 5, iclass 23, count 2 2006.224.07:36:32.03#ibcon#read 5, iclass 23, count 2 2006.224.07:36:32.03#ibcon#about to read 6, iclass 23, count 2 2006.224.07:36:32.03#ibcon#read 6, iclass 23, count 2 2006.224.07:36:32.03#ibcon#end of sib2, iclass 23, count 2 2006.224.07:36:32.03#ibcon#*after write, iclass 23, count 2 2006.224.07:36:32.03#ibcon#*before return 0, iclass 23, count 2 2006.224.07:36:32.03#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.224.07:36:32.03#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.224.07:36:32.03#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.224.07:36:32.03#ibcon#ireg 7 cls_cnt 0 2006.224.07:36:32.03#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.224.07:36:32.15#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.224.07:36:32.15#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.224.07:36:32.15#ibcon#enter wrdev, iclass 23, count 0 2006.224.07:36:32.15#ibcon#first serial, iclass 23, count 0 2006.224.07:36:32.15#ibcon#enter sib2, iclass 23, count 0 2006.224.07:36:32.15#ibcon#flushed, iclass 23, count 0 2006.224.07:36:32.15#ibcon#about to write, iclass 23, count 0 2006.224.07:36:32.15#ibcon#wrote, iclass 23, count 0 2006.224.07:36:32.15#ibcon#about to read 3, iclass 23, count 0 2006.224.07:36:32.17#ibcon#read 3, iclass 23, count 0 2006.224.07:36:32.17#ibcon#about to read 4, iclass 23, count 0 2006.224.07:36:32.17#ibcon#read 4, iclass 23, count 0 2006.224.07:36:32.17#ibcon#about to read 5, iclass 23, count 0 2006.224.07:36:32.17#ibcon#read 5, iclass 23, count 0 2006.224.07:36:32.17#ibcon#about to read 6, iclass 23, count 0 2006.224.07:36:32.17#ibcon#read 6, iclass 23, count 0 2006.224.07:36:32.17#ibcon#end of sib2, iclass 23, count 0 2006.224.07:36:32.17#ibcon#*mode == 0, iclass 23, count 0 2006.224.07:36:32.17#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.224.07:36:32.17#ibcon#[27=USB\r\n] 2006.224.07:36:32.17#ibcon#*before write, iclass 23, count 0 2006.224.07:36:32.17#ibcon#enter sib2, iclass 23, count 0 2006.224.07:36:32.17#ibcon#flushed, iclass 23, count 0 2006.224.07:36:32.17#ibcon#about to write, iclass 23, count 0 2006.224.07:36:32.17#ibcon#wrote, iclass 23, count 0 2006.224.07:36:32.17#ibcon#about to read 3, iclass 23, count 0 2006.224.07:36:32.20#ibcon#read 3, iclass 23, count 0 2006.224.07:36:32.20#ibcon#about to read 4, iclass 23, count 0 2006.224.07:36:32.20#ibcon#read 4, iclass 23, count 0 2006.224.07:36:32.20#ibcon#about to read 5, iclass 23, count 0 2006.224.07:36:32.20#ibcon#read 5, iclass 23, count 0 2006.224.07:36:32.20#ibcon#about to read 6, iclass 23, count 0 2006.224.07:36:32.20#ibcon#read 6, iclass 23, count 0 2006.224.07:36:32.20#ibcon#end of sib2, iclass 23, count 0 2006.224.07:36:32.20#ibcon#*after write, iclass 23, count 0 2006.224.07:36:32.20#ibcon#*before return 0, iclass 23, count 0 2006.224.07:36:32.20#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.224.07:36:32.20#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.224.07:36:32.20#ibcon#about to clear, iclass 23 cls_cnt 0 2006.224.07:36:32.20#ibcon#cleared, iclass 23 cls_cnt 0 2006.224.07:36:32.20$vc4f8/vblo=6,752.99 2006.224.07:36:32.20#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.224.07:36:32.20#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.224.07:36:32.20#ibcon#ireg 17 cls_cnt 0 2006.224.07:36:32.20#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.224.07:36:32.20#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.224.07:36:32.20#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.224.07:36:32.20#ibcon#enter wrdev, iclass 25, count 0 2006.224.07:36:32.20#ibcon#first serial, iclass 25, count 0 2006.224.07:36:32.20#ibcon#enter sib2, iclass 25, count 0 2006.224.07:36:32.20#ibcon#flushed, iclass 25, count 0 2006.224.07:36:32.20#ibcon#about to write, iclass 25, count 0 2006.224.07:36:32.20#ibcon#wrote, iclass 25, count 0 2006.224.07:36:32.20#ibcon#about to read 3, iclass 25, count 0 2006.224.07:36:32.22#ibcon#read 3, iclass 25, count 0 2006.224.07:36:32.22#ibcon#about to read 4, iclass 25, count 0 2006.224.07:36:32.22#ibcon#read 4, iclass 25, count 0 2006.224.07:36:32.22#ibcon#about to read 5, iclass 25, count 0 2006.224.07:36:32.22#ibcon#read 5, iclass 25, count 0 2006.224.07:36:32.22#ibcon#about to read 6, iclass 25, count 0 2006.224.07:36:32.22#ibcon#read 6, iclass 25, count 0 2006.224.07:36:32.22#ibcon#end of sib2, iclass 25, count 0 2006.224.07:36:32.22#ibcon#*mode == 0, iclass 25, count 0 2006.224.07:36:32.22#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.224.07:36:32.22#ibcon#[28=FRQ=06,752.99\r\n] 2006.224.07:36:32.22#ibcon#*before write, iclass 25, count 0 2006.224.07:36:32.22#ibcon#enter sib2, iclass 25, count 0 2006.224.07:36:32.22#ibcon#flushed, iclass 25, count 0 2006.224.07:36:32.22#ibcon#about to write, iclass 25, count 0 2006.224.07:36:32.22#ibcon#wrote, iclass 25, count 0 2006.224.07:36:32.22#ibcon#about to read 3, iclass 25, count 0 2006.224.07:36:32.26#ibcon#read 3, iclass 25, count 0 2006.224.07:36:32.26#ibcon#about to read 4, iclass 25, count 0 2006.224.07:36:32.26#ibcon#read 4, iclass 25, count 0 2006.224.07:36:32.26#ibcon#about to read 5, iclass 25, count 0 2006.224.07:36:32.26#ibcon#read 5, iclass 25, count 0 2006.224.07:36:32.26#ibcon#about to read 6, iclass 25, count 0 2006.224.07:36:32.26#ibcon#read 6, iclass 25, count 0 2006.224.07:36:32.26#ibcon#end of sib2, iclass 25, count 0 2006.224.07:36:32.26#ibcon#*after write, iclass 25, count 0 2006.224.07:36:32.26#ibcon#*before return 0, iclass 25, count 0 2006.224.07:36:32.26#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.224.07:36:32.26#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.224.07:36:32.26#ibcon#about to clear, iclass 25 cls_cnt 0 2006.224.07:36:32.26#ibcon#cleared, iclass 25 cls_cnt 0 2006.224.07:36:32.26$vc4f8/vb=6,4 2006.224.07:36:32.26#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.224.07:36:32.26#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.224.07:36:32.26#ibcon#ireg 11 cls_cnt 2 2006.224.07:36:32.26#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.224.07:36:32.32#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.224.07:36:32.32#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.224.07:36:32.32#ibcon#enter wrdev, iclass 27, count 2 2006.224.07:36:32.32#ibcon#first serial, iclass 27, count 2 2006.224.07:36:32.32#ibcon#enter sib2, iclass 27, count 2 2006.224.07:36:32.32#ibcon#flushed, iclass 27, count 2 2006.224.07:36:32.32#ibcon#about to write, iclass 27, count 2 2006.224.07:36:32.32#ibcon#wrote, iclass 27, count 2 2006.224.07:36:32.32#ibcon#about to read 3, iclass 27, count 2 2006.224.07:36:32.34#ibcon#read 3, iclass 27, count 2 2006.224.07:36:32.34#ibcon#about to read 4, iclass 27, count 2 2006.224.07:36:32.34#ibcon#read 4, iclass 27, count 2 2006.224.07:36:32.34#ibcon#about to read 5, iclass 27, count 2 2006.224.07:36:32.34#ibcon#read 5, iclass 27, count 2 2006.224.07:36:32.34#ibcon#about to read 6, iclass 27, count 2 2006.224.07:36:32.34#ibcon#read 6, iclass 27, count 2 2006.224.07:36:32.34#ibcon#end of sib2, iclass 27, count 2 2006.224.07:36:32.34#ibcon#*mode == 0, iclass 27, count 2 2006.224.07:36:32.34#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.224.07:36:32.34#ibcon#[27=AT06-04\r\n] 2006.224.07:36:32.34#ibcon#*before write, iclass 27, count 2 2006.224.07:36:32.34#ibcon#enter sib2, iclass 27, count 2 2006.224.07:36:32.34#ibcon#flushed, iclass 27, count 2 2006.224.07:36:32.34#ibcon#about to write, iclass 27, count 2 2006.224.07:36:32.34#ibcon#wrote, iclass 27, count 2 2006.224.07:36:32.34#ibcon#about to read 3, iclass 27, count 2 2006.224.07:36:32.37#ibcon#read 3, iclass 27, count 2 2006.224.07:36:32.37#ibcon#about to read 4, iclass 27, count 2 2006.224.07:36:32.37#ibcon#read 4, iclass 27, count 2 2006.224.07:36:32.37#ibcon#about to read 5, iclass 27, count 2 2006.224.07:36:32.37#ibcon#read 5, iclass 27, count 2 2006.224.07:36:32.37#ibcon#about to read 6, iclass 27, count 2 2006.224.07:36:32.37#ibcon#read 6, iclass 27, count 2 2006.224.07:36:32.37#ibcon#end of sib2, iclass 27, count 2 2006.224.07:36:32.37#ibcon#*after write, iclass 27, count 2 2006.224.07:36:32.37#ibcon#*before return 0, iclass 27, count 2 2006.224.07:36:32.37#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.224.07:36:32.37#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.224.07:36:32.37#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.224.07:36:32.37#ibcon#ireg 7 cls_cnt 0 2006.224.07:36:32.37#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.224.07:36:32.49#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.224.07:36:32.49#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.224.07:36:32.49#ibcon#enter wrdev, iclass 27, count 0 2006.224.07:36:32.49#ibcon#first serial, iclass 27, count 0 2006.224.07:36:32.49#ibcon#enter sib2, iclass 27, count 0 2006.224.07:36:32.49#ibcon#flushed, iclass 27, count 0 2006.224.07:36:32.49#ibcon#about to write, iclass 27, count 0 2006.224.07:36:32.49#ibcon#wrote, iclass 27, count 0 2006.224.07:36:32.49#ibcon#about to read 3, iclass 27, count 0 2006.224.07:36:32.51#ibcon#read 3, iclass 27, count 0 2006.224.07:36:32.51#ibcon#about to read 4, iclass 27, count 0 2006.224.07:36:32.51#ibcon#read 4, iclass 27, count 0 2006.224.07:36:32.51#ibcon#about to read 5, iclass 27, count 0 2006.224.07:36:32.51#ibcon#read 5, iclass 27, count 0 2006.224.07:36:32.51#ibcon#about to read 6, iclass 27, count 0 2006.224.07:36:32.51#ibcon#read 6, iclass 27, count 0 2006.224.07:36:32.51#ibcon#end of sib2, iclass 27, count 0 2006.224.07:36:32.51#ibcon#*mode == 0, iclass 27, count 0 2006.224.07:36:32.51#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.224.07:36:32.51#ibcon#[27=USB\r\n] 2006.224.07:36:32.51#ibcon#*before write, iclass 27, count 0 2006.224.07:36:32.51#ibcon#enter sib2, iclass 27, count 0 2006.224.07:36:32.51#ibcon#flushed, iclass 27, count 0 2006.224.07:36:32.51#ibcon#about to write, iclass 27, count 0 2006.224.07:36:32.51#ibcon#wrote, iclass 27, count 0 2006.224.07:36:32.51#ibcon#about to read 3, iclass 27, count 0 2006.224.07:36:32.54#ibcon#read 3, iclass 27, count 0 2006.224.07:36:32.54#ibcon#about to read 4, iclass 27, count 0 2006.224.07:36:32.54#ibcon#read 4, iclass 27, count 0 2006.224.07:36:32.54#ibcon#about to read 5, iclass 27, count 0 2006.224.07:36:32.54#ibcon#read 5, iclass 27, count 0 2006.224.07:36:32.54#ibcon#about to read 6, iclass 27, count 0 2006.224.07:36:32.54#ibcon#read 6, iclass 27, count 0 2006.224.07:36:32.54#ibcon#end of sib2, iclass 27, count 0 2006.224.07:36:32.54#ibcon#*after write, iclass 27, count 0 2006.224.07:36:32.54#ibcon#*before return 0, iclass 27, count 0 2006.224.07:36:32.54#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.224.07:36:32.54#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.224.07:36:32.54#ibcon#about to clear, iclass 27 cls_cnt 0 2006.224.07:36:32.54#ibcon#cleared, iclass 27 cls_cnt 0 2006.224.07:36:32.54$vc4f8/vabw=wide 2006.224.07:36:32.54#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.224.07:36:32.54#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.224.07:36:32.54#ibcon#ireg 8 cls_cnt 0 2006.224.07:36:32.54#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.224.07:36:32.54#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.224.07:36:32.54#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.224.07:36:32.54#ibcon#enter wrdev, iclass 29, count 0 2006.224.07:36:32.54#ibcon#first serial, iclass 29, count 0 2006.224.07:36:32.54#ibcon#enter sib2, iclass 29, count 0 2006.224.07:36:32.54#ibcon#flushed, iclass 29, count 0 2006.224.07:36:32.54#ibcon#about to write, iclass 29, count 0 2006.224.07:36:32.54#ibcon#wrote, iclass 29, count 0 2006.224.07:36:32.54#ibcon#about to read 3, iclass 29, count 0 2006.224.07:36:32.56#ibcon#read 3, iclass 29, count 0 2006.224.07:36:32.56#ibcon#about to read 4, iclass 29, count 0 2006.224.07:36:32.56#ibcon#read 4, iclass 29, count 0 2006.224.07:36:32.56#ibcon#about to read 5, iclass 29, count 0 2006.224.07:36:32.56#ibcon#read 5, iclass 29, count 0 2006.224.07:36:32.56#ibcon#about to read 6, iclass 29, count 0 2006.224.07:36:32.56#ibcon#read 6, iclass 29, count 0 2006.224.07:36:32.56#ibcon#end of sib2, iclass 29, count 0 2006.224.07:36:32.56#ibcon#*mode == 0, iclass 29, count 0 2006.224.07:36:32.56#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.224.07:36:32.56#ibcon#[25=BW32\r\n] 2006.224.07:36:32.56#ibcon#*before write, iclass 29, count 0 2006.224.07:36:32.56#ibcon#enter sib2, iclass 29, count 0 2006.224.07:36:32.56#ibcon#flushed, iclass 29, count 0 2006.224.07:36:32.56#ibcon#about to write, iclass 29, count 0 2006.224.07:36:32.56#ibcon#wrote, iclass 29, count 0 2006.224.07:36:32.56#ibcon#about to read 3, iclass 29, count 0 2006.224.07:36:32.59#ibcon#read 3, iclass 29, count 0 2006.224.07:36:32.59#ibcon#about to read 4, iclass 29, count 0 2006.224.07:36:32.59#ibcon#read 4, iclass 29, count 0 2006.224.07:36:32.59#ibcon#about to read 5, iclass 29, count 0 2006.224.07:36:32.59#ibcon#read 5, iclass 29, count 0 2006.224.07:36:32.59#ibcon#about to read 6, iclass 29, count 0 2006.224.07:36:32.59#ibcon#read 6, iclass 29, count 0 2006.224.07:36:32.59#ibcon#end of sib2, iclass 29, count 0 2006.224.07:36:32.59#ibcon#*after write, iclass 29, count 0 2006.224.07:36:32.59#ibcon#*before return 0, iclass 29, count 0 2006.224.07:36:32.59#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.224.07:36:32.59#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.224.07:36:32.59#ibcon#about to clear, iclass 29 cls_cnt 0 2006.224.07:36:32.59#ibcon#cleared, iclass 29 cls_cnt 0 2006.224.07:36:32.59$vc4f8/vbbw=wide 2006.224.07:36:32.59#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.224.07:36:32.59#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.224.07:36:32.59#ibcon#ireg 8 cls_cnt 0 2006.224.07:36:32.59#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.224.07:36:32.66#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.224.07:36:32.66#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.224.07:36:32.66#ibcon#enter wrdev, iclass 31, count 0 2006.224.07:36:32.66#ibcon#first serial, iclass 31, count 0 2006.224.07:36:32.66#ibcon#enter sib2, iclass 31, count 0 2006.224.07:36:32.66#ibcon#flushed, iclass 31, count 0 2006.224.07:36:32.66#ibcon#about to write, iclass 31, count 0 2006.224.07:36:32.66#ibcon#wrote, iclass 31, count 0 2006.224.07:36:32.66#ibcon#about to read 3, iclass 31, count 0 2006.224.07:36:32.68#ibcon#read 3, iclass 31, count 0 2006.224.07:36:32.68#ibcon#about to read 4, iclass 31, count 0 2006.224.07:36:32.68#ibcon#read 4, iclass 31, count 0 2006.224.07:36:32.68#ibcon#about to read 5, iclass 31, count 0 2006.224.07:36:32.68#ibcon#read 5, iclass 31, count 0 2006.224.07:36:32.68#ibcon#about to read 6, iclass 31, count 0 2006.224.07:36:32.68#ibcon#read 6, iclass 31, count 0 2006.224.07:36:32.68#ibcon#end of sib2, iclass 31, count 0 2006.224.07:36:32.68#ibcon#*mode == 0, iclass 31, count 0 2006.224.07:36:32.68#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.224.07:36:32.68#ibcon#[27=BW32\r\n] 2006.224.07:36:32.68#ibcon#*before write, iclass 31, count 0 2006.224.07:36:32.68#ibcon#enter sib2, iclass 31, count 0 2006.224.07:36:32.68#ibcon#flushed, iclass 31, count 0 2006.224.07:36:32.68#ibcon#about to write, iclass 31, count 0 2006.224.07:36:32.68#ibcon#wrote, iclass 31, count 0 2006.224.07:36:32.68#ibcon#about to read 3, iclass 31, count 0 2006.224.07:36:32.71#ibcon#read 3, iclass 31, count 0 2006.224.07:36:32.71#ibcon#about to read 4, iclass 31, count 0 2006.224.07:36:32.71#ibcon#read 4, iclass 31, count 0 2006.224.07:36:32.71#ibcon#about to read 5, iclass 31, count 0 2006.224.07:36:32.71#ibcon#read 5, iclass 31, count 0 2006.224.07:36:32.71#ibcon#about to read 6, iclass 31, count 0 2006.224.07:36:32.71#ibcon#read 6, iclass 31, count 0 2006.224.07:36:32.71#ibcon#end of sib2, iclass 31, count 0 2006.224.07:36:32.71#ibcon#*after write, iclass 31, count 0 2006.224.07:36:32.71#ibcon#*before return 0, iclass 31, count 0 2006.224.07:36:32.71#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.224.07:36:32.71#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.224.07:36:32.71#ibcon#about to clear, iclass 31 cls_cnt 0 2006.224.07:36:32.71#ibcon#cleared, iclass 31 cls_cnt 0 2006.224.07:36:32.71$4f8m12a/ifd4f 2006.224.07:36:32.71$ifd4f/lo= 2006.224.07:36:32.71$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.224.07:36:32.71$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.224.07:36:32.71$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.224.07:36:32.71$ifd4f/patch= 2006.224.07:36:32.71$ifd4f/patch=lo1,a1,a2,a3,a4 2006.224.07:36:32.71$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.224.07:36:32.71$ifd4f/patch=lo3,a5,a6,a7,a8 2006.224.07:36:32.71$4f8m12a/"form=m,16.000,1:2 2006.224.07:36:32.71$4f8m12a/"tpicd 2006.224.07:36:32.71$4f8m12a/echo=off 2006.224.07:36:32.71$4f8m12a/xlog=off 2006.224.07:36:32.71:!2006.224.07:37:00 2006.224.07:36:42.13#trakl#Source acquired 2006.224.07:36:42.13#flagr#flagr/antenna,acquired 2006.224.07:37:00.00:preob 2006.224.07:37:01.13/onsource/TRACKING 2006.224.07:37:01.13:!2006.224.07:37:10 2006.224.07:37:10.00:data_valid=on 2006.224.07:37:10.00:midob 2006.224.07:37:10.13/onsource/TRACKING 2006.224.07:37:10.13/wx/23.38,1004.2,100 2006.224.07:37:10.22/cable/+6.4330E-03 2006.224.07:37:11.31/va/01,08,usb,yes,40,42 2006.224.07:37:11.31/va/02,07,usb,yes,41,43 2006.224.07:37:11.31/va/03,06,usb,yes,44,44 2006.224.07:37:11.31/va/04,07,usb,yes,43,46 2006.224.07:37:11.31/va/05,07,usb,yes,50,53 2006.224.07:37:11.31/va/06,06,usb,yes,50,49 2006.224.07:37:11.31/va/07,06,usb,yes,51,50 2006.224.07:37:11.31/va/08,07,usb,yes,49,48 2006.224.07:37:11.54/valo/01,532.99,yes,locked 2006.224.07:37:11.54/valo/02,572.99,yes,locked 2006.224.07:37:11.54/valo/03,672.99,yes,locked 2006.224.07:37:11.54/valo/04,832.99,yes,locked 2006.224.07:37:11.54/valo/05,652.99,yes,locked 2006.224.07:37:11.54/valo/06,772.99,yes,locked 2006.224.07:37:11.54/valo/07,832.99,yes,locked 2006.224.07:37:11.54/valo/08,852.99,yes,locked 2006.224.07:37:12.63/vb/01,04,usb,yes,33,31 2006.224.07:37:12.63/vb/02,04,usb,yes,34,36 2006.224.07:37:12.63/vb/03,04,usb,yes,31,35 2006.224.07:37:12.63/vb/04,04,usb,yes,31,32 2006.224.07:37:12.63/vb/05,04,usb,yes,30,34 2006.224.07:37:12.63/vb/06,04,usb,yes,31,34 2006.224.07:37:12.63/vb/07,04,usb,yes,33,33 2006.224.07:37:12.63/vb/08,04,usb,yes,30,34 2006.224.07:37:12.86/vblo/01,632.99,yes,locked 2006.224.07:37:12.86/vblo/02,640.99,yes,locked 2006.224.07:37:12.86/vblo/03,656.99,yes,locked 2006.224.07:37:12.86/vblo/04,712.99,yes,locked 2006.224.07:37:12.86/vblo/05,744.99,yes,locked 2006.224.07:37:12.86/vblo/06,752.99,yes,locked 2006.224.07:37:12.86/vblo/07,734.99,yes,locked 2006.224.07:37:12.86/vblo/08,744.99,yes,locked 2006.224.07:37:13.01/vabw/8 2006.224.07:37:13.16/vbbw/8 2006.224.07:37:13.25/xfe/off,on,15.0 2006.224.07:37:13.62/ifatt/23,28,28,28 2006.224.07:37:14.08/fmout-gps/S +4.38E-07 2006.224.07:37:14.12:!2006.224.07:38:10 2006.224.07:38:10.00:data_valid=off 2006.224.07:38:10.00:postob 2006.224.07:38:10.15/cable/+6.4336E-03 2006.224.07:38:10.15/wx/23.39,1004.3,100 2006.224.07:38:11.08/fmout-gps/S +4.36E-07 2006.224.07:38:11.08:scan_name=224-0739,k06224,70 2006.224.07:38:11.08:source=1116+128,111857.30,123441.7,2000.0,ccw 2006.224.07:38:11.13#flagr#flagr/antenna,new-source 2006.224.07:38:12.13:checkk5 2006.224.07:38:12.50/chk_autoobs//k5ts1/ autoobs is running! 2006.224.07:38:12.86/chk_autoobs//k5ts2/ autoobs is running! 2006.224.07:38:13.24/chk_autoobs//k5ts3/ autoobs is running! 2006.224.07:38:13.61/chk_autoobs//k5ts4/ autoobs is running! 2006.224.07:38:13.98/chk_obsdata//k5ts1/T2240737??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.07:38:14.35/chk_obsdata//k5ts2/T2240737??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.07:38:14.72/chk_obsdata//k5ts3/T2240737??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.07:38:15.09/chk_obsdata//k5ts4/T2240737??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.07:38:15.77/k5log//k5ts1_log_newline 2006.224.07:38:16.45/k5log//k5ts2_log_newline 2006.224.07:38:17.14/k5log//k5ts3_log_newline 2006.224.07:38:17.82/k5log//k5ts4_log_newline 2006.224.07:38:17.85/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.224.07:38:17.85:4f8m12a=1 2006.224.07:38:17.85$4f8m12a/echo=on 2006.224.07:38:17.85$4f8m12a/pcalon 2006.224.07:38:17.85$pcalon/"no phase cal control is implemented here 2006.224.07:38:17.85$4f8m12a/"tpicd=stop 2006.224.07:38:17.85$4f8m12a/vc4f8 2006.224.07:38:17.85$vc4f8/valo=1,532.99 2006.224.07:38:17.85#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.224.07:38:17.85#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.224.07:38:17.85#ibcon#ireg 17 cls_cnt 0 2006.224.07:38:17.85#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.224.07:38:17.85#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.224.07:38:17.85#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.224.07:38:17.85#ibcon#enter wrdev, iclass 38, count 0 2006.224.07:38:17.85#ibcon#first serial, iclass 38, count 0 2006.224.07:38:17.85#ibcon#enter sib2, iclass 38, count 0 2006.224.07:38:17.85#ibcon#flushed, iclass 38, count 0 2006.224.07:38:17.85#ibcon#about to write, iclass 38, count 0 2006.224.07:38:17.85#ibcon#wrote, iclass 38, count 0 2006.224.07:38:17.85#ibcon#about to read 3, iclass 38, count 0 2006.224.07:38:17.87#ibcon#read 3, iclass 38, count 0 2006.224.07:38:17.87#ibcon#about to read 4, iclass 38, count 0 2006.224.07:38:17.87#ibcon#read 4, iclass 38, count 0 2006.224.07:38:17.87#ibcon#about to read 5, iclass 38, count 0 2006.224.07:38:17.87#ibcon#read 5, iclass 38, count 0 2006.224.07:38:17.87#ibcon#about to read 6, iclass 38, count 0 2006.224.07:38:17.87#ibcon#read 6, iclass 38, count 0 2006.224.07:38:17.87#ibcon#end of sib2, iclass 38, count 0 2006.224.07:38:17.87#ibcon#*mode == 0, iclass 38, count 0 2006.224.07:38:17.87#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.224.07:38:17.87#ibcon#[26=FRQ=01,532.99\r\n] 2006.224.07:38:17.87#ibcon#*before write, iclass 38, count 0 2006.224.07:38:17.87#ibcon#enter sib2, iclass 38, count 0 2006.224.07:38:17.87#ibcon#flushed, iclass 38, count 0 2006.224.07:38:17.87#ibcon#about to write, iclass 38, count 0 2006.224.07:38:17.87#ibcon#wrote, iclass 38, count 0 2006.224.07:38:17.87#ibcon#about to read 3, iclass 38, count 0 2006.224.07:38:17.92#ibcon#read 3, iclass 38, count 0 2006.224.07:38:17.92#ibcon#about to read 4, iclass 38, count 0 2006.224.07:38:17.92#ibcon#read 4, iclass 38, count 0 2006.224.07:38:17.92#ibcon#about to read 5, iclass 38, count 0 2006.224.07:38:17.92#ibcon#read 5, iclass 38, count 0 2006.224.07:38:17.92#ibcon#about to read 6, iclass 38, count 0 2006.224.07:38:17.92#ibcon#read 6, iclass 38, count 0 2006.224.07:38:17.92#ibcon#end of sib2, iclass 38, count 0 2006.224.07:38:17.92#ibcon#*after write, iclass 38, count 0 2006.224.07:38:17.92#ibcon#*before return 0, iclass 38, count 0 2006.224.07:38:17.92#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.224.07:38:17.92#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.224.07:38:17.92#ibcon#about to clear, iclass 38 cls_cnt 0 2006.224.07:38:17.92#ibcon#cleared, iclass 38 cls_cnt 0 2006.224.07:38:17.92$vc4f8/va=1,8 2006.224.07:38:17.92#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.224.07:38:17.92#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.224.07:38:17.92#ibcon#ireg 11 cls_cnt 2 2006.224.07:38:17.92#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.224.07:38:17.92#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.224.07:38:17.92#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.224.07:38:17.92#ibcon#enter wrdev, iclass 40, count 2 2006.224.07:38:17.92#ibcon#first serial, iclass 40, count 2 2006.224.07:38:17.92#ibcon#enter sib2, iclass 40, count 2 2006.224.07:38:17.92#ibcon#flushed, iclass 40, count 2 2006.224.07:38:17.92#ibcon#about to write, iclass 40, count 2 2006.224.07:38:17.92#ibcon#wrote, iclass 40, count 2 2006.224.07:38:17.92#ibcon#about to read 3, iclass 40, count 2 2006.224.07:38:17.94#ibcon#read 3, iclass 40, count 2 2006.224.07:38:17.94#ibcon#about to read 4, iclass 40, count 2 2006.224.07:38:17.94#ibcon#read 4, iclass 40, count 2 2006.224.07:38:17.94#ibcon#about to read 5, iclass 40, count 2 2006.224.07:38:17.94#ibcon#read 5, iclass 40, count 2 2006.224.07:38:17.94#ibcon#about to read 6, iclass 40, count 2 2006.224.07:38:17.94#ibcon#read 6, iclass 40, count 2 2006.224.07:38:17.94#ibcon#end of sib2, iclass 40, count 2 2006.224.07:38:17.94#ibcon#*mode == 0, iclass 40, count 2 2006.224.07:38:17.94#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.224.07:38:17.94#ibcon#[25=AT01-08\r\n] 2006.224.07:38:17.94#ibcon#*before write, iclass 40, count 2 2006.224.07:38:17.94#ibcon#enter sib2, iclass 40, count 2 2006.224.07:38:17.94#ibcon#flushed, iclass 40, count 2 2006.224.07:38:17.94#ibcon#about to write, iclass 40, count 2 2006.224.07:38:17.94#ibcon#wrote, iclass 40, count 2 2006.224.07:38:17.94#ibcon#about to read 3, iclass 40, count 2 2006.224.07:38:17.97#ibcon#read 3, iclass 40, count 2 2006.224.07:38:17.97#ibcon#about to read 4, iclass 40, count 2 2006.224.07:38:17.97#ibcon#read 4, iclass 40, count 2 2006.224.07:38:17.97#ibcon#about to read 5, iclass 40, count 2 2006.224.07:38:17.97#ibcon#read 5, iclass 40, count 2 2006.224.07:38:17.97#ibcon#about to read 6, iclass 40, count 2 2006.224.07:38:17.97#ibcon#read 6, iclass 40, count 2 2006.224.07:38:17.97#ibcon#end of sib2, iclass 40, count 2 2006.224.07:38:17.97#ibcon#*after write, iclass 40, count 2 2006.224.07:38:17.97#ibcon#*before return 0, iclass 40, count 2 2006.224.07:38:17.97#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.224.07:38:17.97#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.224.07:38:17.97#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.224.07:38:17.97#ibcon#ireg 7 cls_cnt 0 2006.224.07:38:17.97#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.224.07:38:18.09#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.224.07:38:18.09#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.224.07:38:18.09#ibcon#enter wrdev, iclass 40, count 0 2006.224.07:38:18.09#ibcon#first serial, iclass 40, count 0 2006.224.07:38:18.09#ibcon#enter sib2, iclass 40, count 0 2006.224.07:38:18.09#ibcon#flushed, iclass 40, count 0 2006.224.07:38:18.09#ibcon#about to write, iclass 40, count 0 2006.224.07:38:18.09#ibcon#wrote, iclass 40, count 0 2006.224.07:38:18.09#ibcon#about to read 3, iclass 40, count 0 2006.224.07:38:18.11#ibcon#read 3, iclass 40, count 0 2006.224.07:38:18.11#ibcon#about to read 4, iclass 40, count 0 2006.224.07:38:18.11#ibcon#read 4, iclass 40, count 0 2006.224.07:38:18.11#ibcon#about to read 5, iclass 40, count 0 2006.224.07:38:18.11#ibcon#read 5, iclass 40, count 0 2006.224.07:38:18.11#ibcon#about to read 6, iclass 40, count 0 2006.224.07:38:18.11#ibcon#read 6, iclass 40, count 0 2006.224.07:38:18.11#ibcon#end of sib2, iclass 40, count 0 2006.224.07:38:18.11#ibcon#*mode == 0, iclass 40, count 0 2006.224.07:38:18.11#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.224.07:38:18.11#ibcon#[25=USB\r\n] 2006.224.07:38:18.11#ibcon#*before write, iclass 40, count 0 2006.224.07:38:18.11#ibcon#enter sib2, iclass 40, count 0 2006.224.07:38:18.11#ibcon#flushed, iclass 40, count 0 2006.224.07:38:18.11#ibcon#about to write, iclass 40, count 0 2006.224.07:38:18.11#ibcon#wrote, iclass 40, count 0 2006.224.07:38:18.11#ibcon#about to read 3, iclass 40, count 0 2006.224.07:38:18.14#ibcon#read 3, iclass 40, count 0 2006.224.07:38:18.14#ibcon#about to read 4, iclass 40, count 0 2006.224.07:38:18.14#ibcon#read 4, iclass 40, count 0 2006.224.07:38:18.14#ibcon#about to read 5, iclass 40, count 0 2006.224.07:38:18.14#ibcon#read 5, iclass 40, count 0 2006.224.07:38:18.14#ibcon#about to read 6, iclass 40, count 0 2006.224.07:38:18.14#ibcon#read 6, iclass 40, count 0 2006.224.07:38:18.14#ibcon#end of sib2, iclass 40, count 0 2006.224.07:38:18.14#ibcon#*after write, iclass 40, count 0 2006.224.07:38:18.14#ibcon#*before return 0, iclass 40, count 0 2006.224.07:38:18.14#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.224.07:38:18.14#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.224.07:38:18.14#ibcon#about to clear, iclass 40 cls_cnt 0 2006.224.07:38:18.14#ibcon#cleared, iclass 40 cls_cnt 0 2006.224.07:38:18.14$vc4f8/valo=2,572.99 2006.224.07:38:18.14#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.224.07:38:18.14#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.224.07:38:18.14#ibcon#ireg 17 cls_cnt 0 2006.224.07:38:18.14#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.224.07:38:18.14#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.224.07:38:18.14#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.224.07:38:18.14#ibcon#enter wrdev, iclass 4, count 0 2006.224.07:38:18.14#ibcon#first serial, iclass 4, count 0 2006.224.07:38:18.14#ibcon#enter sib2, iclass 4, count 0 2006.224.07:38:18.14#ibcon#flushed, iclass 4, count 0 2006.224.07:38:18.14#ibcon#about to write, iclass 4, count 0 2006.224.07:38:18.14#ibcon#wrote, iclass 4, count 0 2006.224.07:38:18.14#ibcon#about to read 3, iclass 4, count 0 2006.224.07:38:18.16#ibcon#read 3, iclass 4, count 0 2006.224.07:38:18.16#ibcon#about to read 4, iclass 4, count 0 2006.224.07:38:18.16#ibcon#read 4, iclass 4, count 0 2006.224.07:38:18.16#ibcon#about to read 5, iclass 4, count 0 2006.224.07:38:18.16#ibcon#read 5, iclass 4, count 0 2006.224.07:38:18.16#ibcon#about to read 6, iclass 4, count 0 2006.224.07:38:18.16#ibcon#read 6, iclass 4, count 0 2006.224.07:38:18.16#ibcon#end of sib2, iclass 4, count 0 2006.224.07:38:18.16#ibcon#*mode == 0, iclass 4, count 0 2006.224.07:38:18.16#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.224.07:38:18.16#ibcon#[26=FRQ=02,572.99\r\n] 2006.224.07:38:18.16#ibcon#*before write, iclass 4, count 0 2006.224.07:38:18.16#ibcon#enter sib2, iclass 4, count 0 2006.224.07:38:18.16#ibcon#flushed, iclass 4, count 0 2006.224.07:38:18.16#ibcon#about to write, iclass 4, count 0 2006.224.07:38:18.16#ibcon#wrote, iclass 4, count 0 2006.224.07:38:18.16#ibcon#about to read 3, iclass 4, count 0 2006.224.07:38:18.21#ibcon#read 3, iclass 4, count 0 2006.224.07:38:18.21#ibcon#about to read 4, iclass 4, count 0 2006.224.07:38:18.21#ibcon#read 4, iclass 4, count 0 2006.224.07:38:18.21#ibcon#about to read 5, iclass 4, count 0 2006.224.07:38:18.21#ibcon#read 5, iclass 4, count 0 2006.224.07:38:18.21#ibcon#about to read 6, iclass 4, count 0 2006.224.07:38:18.21#ibcon#read 6, iclass 4, count 0 2006.224.07:38:18.21#ibcon#end of sib2, iclass 4, count 0 2006.224.07:38:18.21#ibcon#*after write, iclass 4, count 0 2006.224.07:38:18.21#ibcon#*before return 0, iclass 4, count 0 2006.224.07:38:18.21#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.224.07:38:18.21#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.224.07:38:18.21#ibcon#about to clear, iclass 4 cls_cnt 0 2006.224.07:38:18.21#ibcon#cleared, iclass 4 cls_cnt 0 2006.224.07:38:18.21$vc4f8/va=2,7 2006.224.07:38:18.21#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.224.07:38:18.21#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.224.07:38:18.21#ibcon#ireg 11 cls_cnt 2 2006.224.07:38:18.21#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.224.07:38:18.26#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.224.07:38:18.26#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.224.07:38:18.26#ibcon#enter wrdev, iclass 6, count 2 2006.224.07:38:18.26#ibcon#first serial, iclass 6, count 2 2006.224.07:38:18.26#ibcon#enter sib2, iclass 6, count 2 2006.224.07:38:18.26#ibcon#flushed, iclass 6, count 2 2006.224.07:38:18.26#ibcon#about to write, iclass 6, count 2 2006.224.07:38:18.26#ibcon#wrote, iclass 6, count 2 2006.224.07:38:18.26#ibcon#about to read 3, iclass 6, count 2 2006.224.07:38:18.28#ibcon#read 3, iclass 6, count 2 2006.224.07:38:18.28#ibcon#about to read 4, iclass 6, count 2 2006.224.07:38:18.28#ibcon#read 4, iclass 6, count 2 2006.224.07:38:18.28#ibcon#about to read 5, iclass 6, count 2 2006.224.07:38:18.28#ibcon#read 5, iclass 6, count 2 2006.224.07:38:18.28#ibcon#about to read 6, iclass 6, count 2 2006.224.07:38:18.28#ibcon#read 6, iclass 6, count 2 2006.224.07:38:18.28#ibcon#end of sib2, iclass 6, count 2 2006.224.07:38:18.28#ibcon#*mode == 0, iclass 6, count 2 2006.224.07:38:18.28#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.224.07:38:18.28#ibcon#[25=AT02-07\r\n] 2006.224.07:38:18.28#ibcon#*before write, iclass 6, count 2 2006.224.07:38:18.28#ibcon#enter sib2, iclass 6, count 2 2006.224.07:38:18.28#ibcon#flushed, iclass 6, count 2 2006.224.07:38:18.28#ibcon#about to write, iclass 6, count 2 2006.224.07:38:18.28#ibcon#wrote, iclass 6, count 2 2006.224.07:38:18.28#ibcon#about to read 3, iclass 6, count 2 2006.224.07:38:18.31#ibcon#read 3, iclass 6, count 2 2006.224.07:38:18.31#ibcon#about to read 4, iclass 6, count 2 2006.224.07:38:18.31#ibcon#read 4, iclass 6, count 2 2006.224.07:38:18.31#ibcon#about to read 5, iclass 6, count 2 2006.224.07:38:18.31#ibcon#read 5, iclass 6, count 2 2006.224.07:38:18.31#ibcon#about to read 6, iclass 6, count 2 2006.224.07:38:18.31#ibcon#read 6, iclass 6, count 2 2006.224.07:38:18.31#ibcon#end of sib2, iclass 6, count 2 2006.224.07:38:18.31#ibcon#*after write, iclass 6, count 2 2006.224.07:38:18.31#ibcon#*before return 0, iclass 6, count 2 2006.224.07:38:18.31#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.224.07:38:18.31#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.224.07:38:18.31#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.224.07:38:18.31#ibcon#ireg 7 cls_cnt 0 2006.224.07:38:18.31#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.224.07:38:18.43#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.224.07:38:18.43#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.224.07:38:18.43#ibcon#enter wrdev, iclass 6, count 0 2006.224.07:38:18.43#ibcon#first serial, iclass 6, count 0 2006.224.07:38:18.43#ibcon#enter sib2, iclass 6, count 0 2006.224.07:38:18.43#ibcon#flushed, iclass 6, count 0 2006.224.07:38:18.43#ibcon#about to write, iclass 6, count 0 2006.224.07:38:18.43#ibcon#wrote, iclass 6, count 0 2006.224.07:38:18.43#ibcon#about to read 3, iclass 6, count 0 2006.224.07:38:18.45#ibcon#read 3, iclass 6, count 0 2006.224.07:38:18.45#ibcon#about to read 4, iclass 6, count 0 2006.224.07:38:18.45#ibcon#read 4, iclass 6, count 0 2006.224.07:38:18.45#ibcon#about to read 5, iclass 6, count 0 2006.224.07:38:18.45#ibcon#read 5, iclass 6, count 0 2006.224.07:38:18.45#ibcon#about to read 6, iclass 6, count 0 2006.224.07:38:18.45#ibcon#read 6, iclass 6, count 0 2006.224.07:38:18.45#ibcon#end of sib2, iclass 6, count 0 2006.224.07:38:18.45#ibcon#*mode == 0, iclass 6, count 0 2006.224.07:38:18.45#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.224.07:38:18.45#ibcon#[25=USB\r\n] 2006.224.07:38:18.45#ibcon#*before write, iclass 6, count 0 2006.224.07:38:18.45#ibcon#enter sib2, iclass 6, count 0 2006.224.07:38:18.45#ibcon#flushed, iclass 6, count 0 2006.224.07:38:18.45#ibcon#about to write, iclass 6, count 0 2006.224.07:38:18.45#ibcon#wrote, iclass 6, count 0 2006.224.07:38:18.45#ibcon#about to read 3, iclass 6, count 0 2006.224.07:38:18.48#ibcon#read 3, iclass 6, count 0 2006.224.07:38:18.48#ibcon#about to read 4, iclass 6, count 0 2006.224.07:38:18.48#ibcon#read 4, iclass 6, count 0 2006.224.07:38:18.48#ibcon#about to read 5, iclass 6, count 0 2006.224.07:38:18.48#ibcon#read 5, iclass 6, count 0 2006.224.07:38:18.48#ibcon#about to read 6, iclass 6, count 0 2006.224.07:38:18.48#ibcon#read 6, iclass 6, count 0 2006.224.07:38:18.48#ibcon#end of sib2, iclass 6, count 0 2006.224.07:38:18.48#ibcon#*after write, iclass 6, count 0 2006.224.07:38:18.48#ibcon#*before return 0, iclass 6, count 0 2006.224.07:38:18.48#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.224.07:38:18.48#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.224.07:38:18.48#ibcon#about to clear, iclass 6 cls_cnt 0 2006.224.07:38:18.48#ibcon#cleared, iclass 6 cls_cnt 0 2006.224.07:38:18.48$vc4f8/valo=3,672.99 2006.224.07:38:18.48#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.224.07:38:18.48#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.224.07:38:18.48#ibcon#ireg 17 cls_cnt 0 2006.224.07:38:18.48#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.224.07:38:18.48#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.224.07:38:18.48#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.224.07:38:18.48#ibcon#enter wrdev, iclass 10, count 0 2006.224.07:38:18.48#ibcon#first serial, iclass 10, count 0 2006.224.07:38:18.48#ibcon#enter sib2, iclass 10, count 0 2006.224.07:38:18.48#ibcon#flushed, iclass 10, count 0 2006.224.07:38:18.48#ibcon#about to write, iclass 10, count 0 2006.224.07:38:18.48#ibcon#wrote, iclass 10, count 0 2006.224.07:38:18.48#ibcon#about to read 3, iclass 10, count 0 2006.224.07:38:18.50#ibcon#read 3, iclass 10, count 0 2006.224.07:38:18.50#ibcon#about to read 4, iclass 10, count 0 2006.224.07:38:18.50#ibcon#read 4, iclass 10, count 0 2006.224.07:38:18.50#ibcon#about to read 5, iclass 10, count 0 2006.224.07:38:18.50#ibcon#read 5, iclass 10, count 0 2006.224.07:38:18.50#ibcon#about to read 6, iclass 10, count 0 2006.224.07:38:18.50#ibcon#read 6, iclass 10, count 0 2006.224.07:38:18.50#ibcon#end of sib2, iclass 10, count 0 2006.224.07:38:18.50#ibcon#*mode == 0, iclass 10, count 0 2006.224.07:38:18.50#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.224.07:38:18.50#ibcon#[26=FRQ=03,672.99\r\n] 2006.224.07:38:18.50#ibcon#*before write, iclass 10, count 0 2006.224.07:38:18.50#ibcon#enter sib2, iclass 10, count 0 2006.224.07:38:18.50#ibcon#flushed, iclass 10, count 0 2006.224.07:38:18.50#ibcon#about to write, iclass 10, count 0 2006.224.07:38:18.50#ibcon#wrote, iclass 10, count 0 2006.224.07:38:18.50#ibcon#about to read 3, iclass 10, count 0 2006.224.07:38:18.55#ibcon#read 3, iclass 10, count 0 2006.224.07:38:18.55#ibcon#about to read 4, iclass 10, count 0 2006.224.07:38:18.55#ibcon#read 4, iclass 10, count 0 2006.224.07:38:18.55#ibcon#about to read 5, iclass 10, count 0 2006.224.07:38:18.55#ibcon#read 5, iclass 10, count 0 2006.224.07:38:18.55#ibcon#about to read 6, iclass 10, count 0 2006.224.07:38:18.55#ibcon#read 6, iclass 10, count 0 2006.224.07:38:18.55#ibcon#end of sib2, iclass 10, count 0 2006.224.07:38:18.55#ibcon#*after write, iclass 10, count 0 2006.224.07:38:18.55#ibcon#*before return 0, iclass 10, count 0 2006.224.07:38:18.55#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.224.07:38:18.55#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.224.07:38:18.55#ibcon#about to clear, iclass 10 cls_cnt 0 2006.224.07:38:18.55#ibcon#cleared, iclass 10 cls_cnt 0 2006.224.07:38:18.55$vc4f8/va=3,6 2006.224.07:38:18.55#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.224.07:38:18.55#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.224.07:38:18.55#ibcon#ireg 11 cls_cnt 2 2006.224.07:38:18.55#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.224.07:38:18.60#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.224.07:38:18.60#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.224.07:38:18.60#ibcon#enter wrdev, iclass 12, count 2 2006.224.07:38:18.60#ibcon#first serial, iclass 12, count 2 2006.224.07:38:18.60#ibcon#enter sib2, iclass 12, count 2 2006.224.07:38:18.60#ibcon#flushed, iclass 12, count 2 2006.224.07:38:18.60#ibcon#about to write, iclass 12, count 2 2006.224.07:38:18.60#ibcon#wrote, iclass 12, count 2 2006.224.07:38:18.60#ibcon#about to read 3, iclass 12, count 2 2006.224.07:38:18.62#ibcon#read 3, iclass 12, count 2 2006.224.07:38:18.62#ibcon#about to read 4, iclass 12, count 2 2006.224.07:38:18.62#ibcon#read 4, iclass 12, count 2 2006.224.07:38:18.62#ibcon#about to read 5, iclass 12, count 2 2006.224.07:38:18.62#ibcon#read 5, iclass 12, count 2 2006.224.07:38:18.62#ibcon#about to read 6, iclass 12, count 2 2006.224.07:38:18.62#ibcon#read 6, iclass 12, count 2 2006.224.07:38:18.62#ibcon#end of sib2, iclass 12, count 2 2006.224.07:38:18.62#ibcon#*mode == 0, iclass 12, count 2 2006.224.07:38:18.62#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.224.07:38:18.62#ibcon#[25=AT03-06\r\n] 2006.224.07:38:18.62#ibcon#*before write, iclass 12, count 2 2006.224.07:38:18.62#ibcon#enter sib2, iclass 12, count 2 2006.224.07:38:18.62#ibcon#flushed, iclass 12, count 2 2006.224.07:38:18.62#ibcon#about to write, iclass 12, count 2 2006.224.07:38:18.62#ibcon#wrote, iclass 12, count 2 2006.224.07:38:18.62#ibcon#about to read 3, iclass 12, count 2 2006.224.07:38:18.65#ibcon#read 3, iclass 12, count 2 2006.224.07:38:18.65#ibcon#about to read 4, iclass 12, count 2 2006.224.07:38:18.65#ibcon#read 4, iclass 12, count 2 2006.224.07:38:18.65#ibcon#about to read 5, iclass 12, count 2 2006.224.07:38:18.65#ibcon#read 5, iclass 12, count 2 2006.224.07:38:18.65#ibcon#about to read 6, iclass 12, count 2 2006.224.07:38:18.65#ibcon#read 6, iclass 12, count 2 2006.224.07:38:18.65#ibcon#end of sib2, iclass 12, count 2 2006.224.07:38:18.65#ibcon#*after write, iclass 12, count 2 2006.224.07:38:18.65#ibcon#*before return 0, iclass 12, count 2 2006.224.07:38:18.65#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.224.07:38:18.65#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.224.07:38:18.65#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.224.07:38:18.65#ibcon#ireg 7 cls_cnt 0 2006.224.07:38:18.65#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.224.07:38:18.77#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.224.07:38:18.77#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.224.07:38:18.77#ibcon#enter wrdev, iclass 12, count 0 2006.224.07:38:18.77#ibcon#first serial, iclass 12, count 0 2006.224.07:38:18.77#ibcon#enter sib2, iclass 12, count 0 2006.224.07:38:18.77#ibcon#flushed, iclass 12, count 0 2006.224.07:38:18.77#ibcon#about to write, iclass 12, count 0 2006.224.07:38:18.77#ibcon#wrote, iclass 12, count 0 2006.224.07:38:18.77#ibcon#about to read 3, iclass 12, count 0 2006.224.07:38:18.79#ibcon#read 3, iclass 12, count 0 2006.224.07:38:18.79#ibcon#about to read 4, iclass 12, count 0 2006.224.07:38:18.79#ibcon#read 4, iclass 12, count 0 2006.224.07:38:18.79#ibcon#about to read 5, iclass 12, count 0 2006.224.07:38:18.79#ibcon#read 5, iclass 12, count 0 2006.224.07:38:18.79#ibcon#about to read 6, iclass 12, count 0 2006.224.07:38:18.79#ibcon#read 6, iclass 12, count 0 2006.224.07:38:18.79#ibcon#end of sib2, iclass 12, count 0 2006.224.07:38:18.79#ibcon#*mode == 0, iclass 12, count 0 2006.224.07:38:18.79#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.224.07:38:18.79#ibcon#[25=USB\r\n] 2006.224.07:38:18.79#ibcon#*before write, iclass 12, count 0 2006.224.07:38:18.79#ibcon#enter sib2, iclass 12, count 0 2006.224.07:38:18.79#ibcon#flushed, iclass 12, count 0 2006.224.07:38:18.79#ibcon#about to write, iclass 12, count 0 2006.224.07:38:18.79#ibcon#wrote, iclass 12, count 0 2006.224.07:38:18.79#ibcon#about to read 3, iclass 12, count 0 2006.224.07:38:18.82#ibcon#read 3, iclass 12, count 0 2006.224.07:38:18.82#ibcon#about to read 4, iclass 12, count 0 2006.224.07:38:18.82#ibcon#read 4, iclass 12, count 0 2006.224.07:38:18.82#ibcon#about to read 5, iclass 12, count 0 2006.224.07:38:18.82#ibcon#read 5, iclass 12, count 0 2006.224.07:38:18.82#ibcon#about to read 6, iclass 12, count 0 2006.224.07:38:18.82#ibcon#read 6, iclass 12, count 0 2006.224.07:38:18.82#ibcon#end of sib2, iclass 12, count 0 2006.224.07:38:18.82#ibcon#*after write, iclass 12, count 0 2006.224.07:38:18.82#ibcon#*before return 0, iclass 12, count 0 2006.224.07:38:18.82#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.224.07:38:18.82#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.224.07:38:18.82#ibcon#about to clear, iclass 12 cls_cnt 0 2006.224.07:38:18.82#ibcon#cleared, iclass 12 cls_cnt 0 2006.224.07:38:18.82$vc4f8/valo=4,832.99 2006.224.07:38:18.82#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.224.07:38:18.82#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.224.07:38:18.82#ibcon#ireg 17 cls_cnt 0 2006.224.07:38:18.82#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.224.07:38:18.82#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.224.07:38:18.82#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.224.07:38:18.82#ibcon#enter wrdev, iclass 14, count 0 2006.224.07:38:18.82#ibcon#first serial, iclass 14, count 0 2006.224.07:38:18.82#ibcon#enter sib2, iclass 14, count 0 2006.224.07:38:18.82#ibcon#flushed, iclass 14, count 0 2006.224.07:38:18.82#ibcon#about to write, iclass 14, count 0 2006.224.07:38:18.82#ibcon#wrote, iclass 14, count 0 2006.224.07:38:18.82#ibcon#about to read 3, iclass 14, count 0 2006.224.07:38:18.84#ibcon#read 3, iclass 14, count 0 2006.224.07:38:18.84#ibcon#about to read 4, iclass 14, count 0 2006.224.07:38:18.84#ibcon#read 4, iclass 14, count 0 2006.224.07:38:18.84#ibcon#about to read 5, iclass 14, count 0 2006.224.07:38:18.84#ibcon#read 5, iclass 14, count 0 2006.224.07:38:18.84#ibcon#about to read 6, iclass 14, count 0 2006.224.07:38:18.84#ibcon#read 6, iclass 14, count 0 2006.224.07:38:18.84#ibcon#end of sib2, iclass 14, count 0 2006.224.07:38:18.84#ibcon#*mode == 0, iclass 14, count 0 2006.224.07:38:18.84#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.224.07:38:18.84#ibcon#[26=FRQ=04,832.99\r\n] 2006.224.07:38:18.84#ibcon#*before write, iclass 14, count 0 2006.224.07:38:18.84#ibcon#enter sib2, iclass 14, count 0 2006.224.07:38:18.84#ibcon#flushed, iclass 14, count 0 2006.224.07:38:18.84#ibcon#about to write, iclass 14, count 0 2006.224.07:38:18.84#ibcon#wrote, iclass 14, count 0 2006.224.07:38:18.84#ibcon#about to read 3, iclass 14, count 0 2006.224.07:38:18.89#ibcon#read 3, iclass 14, count 0 2006.224.07:38:18.89#ibcon#about to read 4, iclass 14, count 0 2006.224.07:38:18.89#ibcon#read 4, iclass 14, count 0 2006.224.07:38:18.89#ibcon#about to read 5, iclass 14, count 0 2006.224.07:38:18.89#ibcon#read 5, iclass 14, count 0 2006.224.07:38:18.89#ibcon#about to read 6, iclass 14, count 0 2006.224.07:38:18.89#ibcon#read 6, iclass 14, count 0 2006.224.07:38:18.89#ibcon#end of sib2, iclass 14, count 0 2006.224.07:38:18.89#ibcon#*after write, iclass 14, count 0 2006.224.07:38:18.89#ibcon#*before return 0, iclass 14, count 0 2006.224.07:38:18.89#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.224.07:38:18.89#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.224.07:38:18.89#ibcon#about to clear, iclass 14 cls_cnt 0 2006.224.07:38:18.89#ibcon#cleared, iclass 14 cls_cnt 0 2006.224.07:38:18.89$vc4f8/va=4,7 2006.224.07:38:18.89#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.224.07:38:18.89#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.224.07:38:18.89#ibcon#ireg 11 cls_cnt 2 2006.224.07:38:18.89#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.224.07:38:18.94#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.224.07:38:18.94#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.224.07:38:18.94#ibcon#enter wrdev, iclass 16, count 2 2006.224.07:38:18.94#ibcon#first serial, iclass 16, count 2 2006.224.07:38:18.94#ibcon#enter sib2, iclass 16, count 2 2006.224.07:38:18.94#ibcon#flushed, iclass 16, count 2 2006.224.07:38:18.94#ibcon#about to write, iclass 16, count 2 2006.224.07:38:18.94#ibcon#wrote, iclass 16, count 2 2006.224.07:38:18.94#ibcon#about to read 3, iclass 16, count 2 2006.224.07:38:18.96#ibcon#read 3, iclass 16, count 2 2006.224.07:38:18.96#ibcon#about to read 4, iclass 16, count 2 2006.224.07:38:18.96#ibcon#read 4, iclass 16, count 2 2006.224.07:38:18.96#ibcon#about to read 5, iclass 16, count 2 2006.224.07:38:18.96#ibcon#read 5, iclass 16, count 2 2006.224.07:38:18.96#ibcon#about to read 6, iclass 16, count 2 2006.224.07:38:18.96#ibcon#read 6, iclass 16, count 2 2006.224.07:38:18.96#ibcon#end of sib2, iclass 16, count 2 2006.224.07:38:18.96#ibcon#*mode == 0, iclass 16, count 2 2006.224.07:38:18.96#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.224.07:38:18.96#ibcon#[25=AT04-07\r\n] 2006.224.07:38:18.96#ibcon#*before write, iclass 16, count 2 2006.224.07:38:18.96#ibcon#enter sib2, iclass 16, count 2 2006.224.07:38:18.96#ibcon#flushed, iclass 16, count 2 2006.224.07:38:18.96#ibcon#about to write, iclass 16, count 2 2006.224.07:38:18.96#ibcon#wrote, iclass 16, count 2 2006.224.07:38:18.96#ibcon#about to read 3, iclass 16, count 2 2006.224.07:38:18.99#ibcon#read 3, iclass 16, count 2 2006.224.07:38:18.99#ibcon#about to read 4, iclass 16, count 2 2006.224.07:38:18.99#ibcon#read 4, iclass 16, count 2 2006.224.07:38:18.99#ibcon#about to read 5, iclass 16, count 2 2006.224.07:38:18.99#ibcon#read 5, iclass 16, count 2 2006.224.07:38:18.99#ibcon#about to read 6, iclass 16, count 2 2006.224.07:38:18.99#ibcon#read 6, iclass 16, count 2 2006.224.07:38:18.99#ibcon#end of sib2, iclass 16, count 2 2006.224.07:38:18.99#ibcon#*after write, iclass 16, count 2 2006.224.07:38:18.99#ibcon#*before return 0, iclass 16, count 2 2006.224.07:38:18.99#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.224.07:38:18.99#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.224.07:38:18.99#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.224.07:38:18.99#ibcon#ireg 7 cls_cnt 0 2006.224.07:38:18.99#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.224.07:38:19.11#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.224.07:38:19.11#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.224.07:38:19.11#ibcon#enter wrdev, iclass 16, count 0 2006.224.07:38:19.11#ibcon#first serial, iclass 16, count 0 2006.224.07:38:19.11#ibcon#enter sib2, iclass 16, count 0 2006.224.07:38:19.11#ibcon#flushed, iclass 16, count 0 2006.224.07:38:19.11#ibcon#about to write, iclass 16, count 0 2006.224.07:38:19.11#ibcon#wrote, iclass 16, count 0 2006.224.07:38:19.11#ibcon#about to read 3, iclass 16, count 0 2006.224.07:38:19.13#ibcon#read 3, iclass 16, count 0 2006.224.07:38:19.13#ibcon#about to read 4, iclass 16, count 0 2006.224.07:38:19.13#ibcon#read 4, iclass 16, count 0 2006.224.07:38:19.13#ibcon#about to read 5, iclass 16, count 0 2006.224.07:38:19.13#ibcon#read 5, iclass 16, count 0 2006.224.07:38:19.13#ibcon#about to read 6, iclass 16, count 0 2006.224.07:38:19.13#ibcon#read 6, iclass 16, count 0 2006.224.07:38:19.13#ibcon#end of sib2, iclass 16, count 0 2006.224.07:38:19.13#ibcon#*mode == 0, iclass 16, count 0 2006.224.07:38:19.13#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.224.07:38:19.13#ibcon#[25=USB\r\n] 2006.224.07:38:19.13#ibcon#*before write, iclass 16, count 0 2006.224.07:38:19.13#ibcon#enter sib2, iclass 16, count 0 2006.224.07:38:19.13#ibcon#flushed, iclass 16, count 0 2006.224.07:38:19.13#ibcon#about to write, iclass 16, count 0 2006.224.07:38:19.13#ibcon#wrote, iclass 16, count 0 2006.224.07:38:19.13#ibcon#about to read 3, iclass 16, count 0 2006.224.07:38:19.16#ibcon#read 3, iclass 16, count 0 2006.224.07:38:19.16#ibcon#about to read 4, iclass 16, count 0 2006.224.07:38:19.16#ibcon#read 4, iclass 16, count 0 2006.224.07:38:19.16#ibcon#about to read 5, iclass 16, count 0 2006.224.07:38:19.16#ibcon#read 5, iclass 16, count 0 2006.224.07:38:19.16#ibcon#about to read 6, iclass 16, count 0 2006.224.07:38:19.16#ibcon#read 6, iclass 16, count 0 2006.224.07:38:19.16#ibcon#end of sib2, iclass 16, count 0 2006.224.07:38:19.16#ibcon#*after write, iclass 16, count 0 2006.224.07:38:19.16#ibcon#*before return 0, iclass 16, count 0 2006.224.07:38:19.16#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.224.07:38:19.16#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.224.07:38:19.16#ibcon#about to clear, iclass 16 cls_cnt 0 2006.224.07:38:19.16#ibcon#cleared, iclass 16 cls_cnt 0 2006.224.07:38:19.16$vc4f8/valo=5,652.99 2006.224.07:38:19.16#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.224.07:38:19.16#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.224.07:38:19.16#ibcon#ireg 17 cls_cnt 0 2006.224.07:38:19.16#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.224.07:38:19.16#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.224.07:38:19.16#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.224.07:38:19.16#ibcon#enter wrdev, iclass 18, count 0 2006.224.07:38:19.16#ibcon#first serial, iclass 18, count 0 2006.224.07:38:19.16#ibcon#enter sib2, iclass 18, count 0 2006.224.07:38:19.16#ibcon#flushed, iclass 18, count 0 2006.224.07:38:19.16#ibcon#about to write, iclass 18, count 0 2006.224.07:38:19.16#ibcon#wrote, iclass 18, count 0 2006.224.07:38:19.16#ibcon#about to read 3, iclass 18, count 0 2006.224.07:38:19.18#ibcon#read 3, iclass 18, count 0 2006.224.07:38:19.18#ibcon#about to read 4, iclass 18, count 0 2006.224.07:38:19.18#ibcon#read 4, iclass 18, count 0 2006.224.07:38:19.18#ibcon#about to read 5, iclass 18, count 0 2006.224.07:38:19.18#ibcon#read 5, iclass 18, count 0 2006.224.07:38:19.18#ibcon#about to read 6, iclass 18, count 0 2006.224.07:38:19.18#ibcon#read 6, iclass 18, count 0 2006.224.07:38:19.18#ibcon#end of sib2, iclass 18, count 0 2006.224.07:38:19.18#ibcon#*mode == 0, iclass 18, count 0 2006.224.07:38:19.18#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.224.07:38:19.18#ibcon#[26=FRQ=05,652.99\r\n] 2006.224.07:38:19.18#ibcon#*before write, iclass 18, count 0 2006.224.07:38:19.18#ibcon#enter sib2, iclass 18, count 0 2006.224.07:38:19.18#ibcon#flushed, iclass 18, count 0 2006.224.07:38:19.18#ibcon#about to write, iclass 18, count 0 2006.224.07:38:19.18#ibcon#wrote, iclass 18, count 0 2006.224.07:38:19.18#ibcon#about to read 3, iclass 18, count 0 2006.224.07:38:19.22#ibcon#read 3, iclass 18, count 0 2006.224.07:38:19.22#ibcon#about to read 4, iclass 18, count 0 2006.224.07:38:19.22#ibcon#read 4, iclass 18, count 0 2006.224.07:38:19.22#ibcon#about to read 5, iclass 18, count 0 2006.224.07:38:19.22#ibcon#read 5, iclass 18, count 0 2006.224.07:38:19.22#ibcon#about to read 6, iclass 18, count 0 2006.224.07:38:19.22#ibcon#read 6, iclass 18, count 0 2006.224.07:38:19.22#ibcon#end of sib2, iclass 18, count 0 2006.224.07:38:19.22#ibcon#*after write, iclass 18, count 0 2006.224.07:38:19.22#ibcon#*before return 0, iclass 18, count 0 2006.224.07:38:19.22#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.224.07:38:19.22#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.224.07:38:19.22#ibcon#about to clear, iclass 18 cls_cnt 0 2006.224.07:38:19.22#ibcon#cleared, iclass 18 cls_cnt 0 2006.224.07:38:19.22$vc4f8/va=5,7 2006.224.07:38:19.22#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.224.07:38:19.22#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.224.07:38:19.22#ibcon#ireg 11 cls_cnt 2 2006.224.07:38:19.22#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.224.07:38:19.28#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.224.07:38:19.28#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.224.07:38:19.28#ibcon#enter wrdev, iclass 20, count 2 2006.224.07:38:19.28#ibcon#first serial, iclass 20, count 2 2006.224.07:38:19.28#ibcon#enter sib2, iclass 20, count 2 2006.224.07:38:19.28#ibcon#flushed, iclass 20, count 2 2006.224.07:38:19.28#ibcon#about to write, iclass 20, count 2 2006.224.07:38:19.28#ibcon#wrote, iclass 20, count 2 2006.224.07:38:19.28#ibcon#about to read 3, iclass 20, count 2 2006.224.07:38:19.30#ibcon#read 3, iclass 20, count 2 2006.224.07:38:19.30#ibcon#about to read 4, iclass 20, count 2 2006.224.07:38:19.30#ibcon#read 4, iclass 20, count 2 2006.224.07:38:19.30#ibcon#about to read 5, iclass 20, count 2 2006.224.07:38:19.30#ibcon#read 5, iclass 20, count 2 2006.224.07:38:19.30#ibcon#about to read 6, iclass 20, count 2 2006.224.07:38:19.30#ibcon#read 6, iclass 20, count 2 2006.224.07:38:19.30#ibcon#end of sib2, iclass 20, count 2 2006.224.07:38:19.30#ibcon#*mode == 0, iclass 20, count 2 2006.224.07:38:19.30#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.224.07:38:19.30#ibcon#[25=AT05-07\r\n] 2006.224.07:38:19.30#ibcon#*before write, iclass 20, count 2 2006.224.07:38:19.30#ibcon#enter sib2, iclass 20, count 2 2006.224.07:38:19.30#ibcon#flushed, iclass 20, count 2 2006.224.07:38:19.30#ibcon#about to write, iclass 20, count 2 2006.224.07:38:19.30#ibcon#wrote, iclass 20, count 2 2006.224.07:38:19.30#ibcon#about to read 3, iclass 20, count 2 2006.224.07:38:19.33#ibcon#read 3, iclass 20, count 2 2006.224.07:38:19.33#ibcon#about to read 4, iclass 20, count 2 2006.224.07:38:19.33#ibcon#read 4, iclass 20, count 2 2006.224.07:38:19.33#ibcon#about to read 5, iclass 20, count 2 2006.224.07:38:19.33#ibcon#read 5, iclass 20, count 2 2006.224.07:38:19.33#ibcon#about to read 6, iclass 20, count 2 2006.224.07:38:19.33#ibcon#read 6, iclass 20, count 2 2006.224.07:38:19.33#ibcon#end of sib2, iclass 20, count 2 2006.224.07:38:19.33#ibcon#*after write, iclass 20, count 2 2006.224.07:38:19.33#ibcon#*before return 0, iclass 20, count 2 2006.224.07:38:19.33#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.224.07:38:19.33#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.224.07:38:19.33#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.224.07:38:19.33#ibcon#ireg 7 cls_cnt 0 2006.224.07:38:19.33#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.224.07:38:19.45#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.224.07:38:19.45#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.224.07:38:19.45#ibcon#enter wrdev, iclass 20, count 0 2006.224.07:38:19.45#ibcon#first serial, iclass 20, count 0 2006.224.07:38:19.45#ibcon#enter sib2, iclass 20, count 0 2006.224.07:38:19.45#ibcon#flushed, iclass 20, count 0 2006.224.07:38:19.45#ibcon#about to write, iclass 20, count 0 2006.224.07:38:19.45#ibcon#wrote, iclass 20, count 0 2006.224.07:38:19.45#ibcon#about to read 3, iclass 20, count 0 2006.224.07:38:19.47#ibcon#read 3, iclass 20, count 0 2006.224.07:38:19.47#ibcon#about to read 4, iclass 20, count 0 2006.224.07:38:19.47#ibcon#read 4, iclass 20, count 0 2006.224.07:38:19.47#ibcon#about to read 5, iclass 20, count 0 2006.224.07:38:19.47#ibcon#read 5, iclass 20, count 0 2006.224.07:38:19.47#ibcon#about to read 6, iclass 20, count 0 2006.224.07:38:19.47#ibcon#read 6, iclass 20, count 0 2006.224.07:38:19.47#ibcon#end of sib2, iclass 20, count 0 2006.224.07:38:19.47#ibcon#*mode == 0, iclass 20, count 0 2006.224.07:38:19.47#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.224.07:38:19.47#ibcon#[25=USB\r\n] 2006.224.07:38:19.47#ibcon#*before write, iclass 20, count 0 2006.224.07:38:19.47#ibcon#enter sib2, iclass 20, count 0 2006.224.07:38:19.47#ibcon#flushed, iclass 20, count 0 2006.224.07:38:19.47#ibcon#about to write, iclass 20, count 0 2006.224.07:38:19.47#ibcon#wrote, iclass 20, count 0 2006.224.07:38:19.47#ibcon#about to read 3, iclass 20, count 0 2006.224.07:38:19.50#ibcon#read 3, iclass 20, count 0 2006.224.07:38:19.50#ibcon#about to read 4, iclass 20, count 0 2006.224.07:38:19.50#ibcon#read 4, iclass 20, count 0 2006.224.07:38:19.50#ibcon#about to read 5, iclass 20, count 0 2006.224.07:38:19.50#ibcon#read 5, iclass 20, count 0 2006.224.07:38:19.50#ibcon#about to read 6, iclass 20, count 0 2006.224.07:38:19.50#ibcon#read 6, iclass 20, count 0 2006.224.07:38:19.50#ibcon#end of sib2, iclass 20, count 0 2006.224.07:38:19.50#ibcon#*after write, iclass 20, count 0 2006.224.07:38:19.50#ibcon#*before return 0, iclass 20, count 0 2006.224.07:38:19.50#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.224.07:38:19.50#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.224.07:38:19.50#ibcon#about to clear, iclass 20 cls_cnt 0 2006.224.07:38:19.50#ibcon#cleared, iclass 20 cls_cnt 0 2006.224.07:38:19.50$vc4f8/valo=6,772.99 2006.224.07:38:19.50#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.224.07:38:19.50#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.224.07:38:19.50#ibcon#ireg 17 cls_cnt 0 2006.224.07:38:19.50#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.224.07:38:19.50#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.224.07:38:19.50#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.224.07:38:19.50#ibcon#enter wrdev, iclass 23, count 0 2006.224.07:38:19.50#ibcon#first serial, iclass 23, count 0 2006.224.07:38:19.50#ibcon#enter sib2, iclass 23, count 0 2006.224.07:38:19.50#ibcon#flushed, iclass 23, count 0 2006.224.07:38:19.50#ibcon#about to write, iclass 23, count 0 2006.224.07:38:19.50#ibcon#wrote, iclass 23, count 0 2006.224.07:38:19.50#ibcon#about to read 3, iclass 23, count 0 2006.224.07:38:19.52#ibcon#read 3, iclass 23, count 0 2006.224.07:38:19.52#ibcon#about to read 4, iclass 23, count 0 2006.224.07:38:19.52#ibcon#read 4, iclass 23, count 0 2006.224.07:38:19.52#ibcon#about to read 5, iclass 23, count 0 2006.224.07:38:19.52#ibcon#read 5, iclass 23, count 0 2006.224.07:38:19.52#ibcon#about to read 6, iclass 23, count 0 2006.224.07:38:19.52#ibcon#read 6, iclass 23, count 0 2006.224.07:38:19.52#ibcon#end of sib2, iclass 23, count 0 2006.224.07:38:19.52#ibcon#*mode == 0, iclass 23, count 0 2006.224.07:38:19.52#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.224.07:38:19.52#ibcon#[26=FRQ=06,772.99\r\n] 2006.224.07:38:19.52#ibcon#*before write, iclass 23, count 0 2006.224.07:38:19.52#ibcon#enter sib2, iclass 23, count 0 2006.224.07:38:19.52#ibcon#flushed, iclass 23, count 0 2006.224.07:38:19.52#ibcon#about to write, iclass 23, count 0 2006.224.07:38:19.52#ibcon#wrote, iclass 23, count 0 2006.224.07:38:19.52#ibcon#about to read 3, iclass 23, count 0 2006.224.07:38:19.53#abcon#<5=/03 0.5 1.8 23.391001004.3\r\n> 2006.224.07:38:19.55#abcon#{5=INTERFACE CLEAR} 2006.224.07:38:19.57#ibcon#read 3, iclass 23, count 0 2006.224.07:38:19.57#ibcon#about to read 4, iclass 23, count 0 2006.224.07:38:19.57#ibcon#read 4, iclass 23, count 0 2006.224.07:38:19.57#ibcon#about to read 5, iclass 23, count 0 2006.224.07:38:19.57#ibcon#read 5, iclass 23, count 0 2006.224.07:38:19.57#ibcon#about to read 6, iclass 23, count 0 2006.224.07:38:19.57#ibcon#read 6, iclass 23, count 0 2006.224.07:38:19.57#ibcon#end of sib2, iclass 23, count 0 2006.224.07:38:19.57#ibcon#*after write, iclass 23, count 0 2006.224.07:38:19.57#ibcon#*before return 0, iclass 23, count 0 2006.224.07:38:19.57#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.224.07:38:19.57#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.224.07:38:19.57#ibcon#about to clear, iclass 23 cls_cnt 0 2006.224.07:38:19.57#ibcon#cleared, iclass 23 cls_cnt 0 2006.224.07:38:19.57$vc4f8/va=6,6 2006.224.07:38:19.57#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.224.07:38:19.57#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.224.07:38:19.57#ibcon#ireg 11 cls_cnt 2 2006.224.07:38:19.57#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.224.07:38:19.61#abcon#[5=S1D000X0/0*\r\n] 2006.224.07:38:19.62#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.224.07:38:19.62#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.224.07:38:19.62#ibcon#enter wrdev, iclass 27, count 2 2006.224.07:38:19.62#ibcon#first serial, iclass 27, count 2 2006.224.07:38:19.62#ibcon#enter sib2, iclass 27, count 2 2006.224.07:38:19.62#ibcon#flushed, iclass 27, count 2 2006.224.07:38:19.62#ibcon#about to write, iclass 27, count 2 2006.224.07:38:19.62#ibcon#wrote, iclass 27, count 2 2006.224.07:38:19.62#ibcon#about to read 3, iclass 27, count 2 2006.224.07:38:19.64#ibcon#read 3, iclass 27, count 2 2006.224.07:38:19.64#ibcon#about to read 4, iclass 27, count 2 2006.224.07:38:19.64#ibcon#read 4, iclass 27, count 2 2006.224.07:38:19.64#ibcon#about to read 5, iclass 27, count 2 2006.224.07:38:19.64#ibcon#read 5, iclass 27, count 2 2006.224.07:38:19.64#ibcon#about to read 6, iclass 27, count 2 2006.224.07:38:19.64#ibcon#read 6, iclass 27, count 2 2006.224.07:38:19.64#ibcon#end of sib2, iclass 27, count 2 2006.224.07:38:19.64#ibcon#*mode == 0, iclass 27, count 2 2006.224.07:38:19.64#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.224.07:38:19.64#ibcon#[25=AT06-06\r\n] 2006.224.07:38:19.64#ibcon#*before write, iclass 27, count 2 2006.224.07:38:19.64#ibcon#enter sib2, iclass 27, count 2 2006.224.07:38:19.64#ibcon#flushed, iclass 27, count 2 2006.224.07:38:19.64#ibcon#about to write, iclass 27, count 2 2006.224.07:38:19.64#ibcon#wrote, iclass 27, count 2 2006.224.07:38:19.64#ibcon#about to read 3, iclass 27, count 2 2006.224.07:38:19.67#ibcon#read 3, iclass 27, count 2 2006.224.07:38:19.67#ibcon#about to read 4, iclass 27, count 2 2006.224.07:38:19.67#ibcon#read 4, iclass 27, count 2 2006.224.07:38:19.67#ibcon#about to read 5, iclass 27, count 2 2006.224.07:38:19.67#ibcon#read 5, iclass 27, count 2 2006.224.07:38:19.67#ibcon#about to read 6, iclass 27, count 2 2006.224.07:38:19.67#ibcon#read 6, iclass 27, count 2 2006.224.07:38:19.67#ibcon#end of sib2, iclass 27, count 2 2006.224.07:38:19.67#ibcon#*after write, iclass 27, count 2 2006.224.07:38:19.67#ibcon#*before return 0, iclass 27, count 2 2006.224.07:38:19.67#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.224.07:38:19.67#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.224.07:38:19.67#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.224.07:38:19.67#ibcon#ireg 7 cls_cnt 0 2006.224.07:38:19.67#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.224.07:38:19.79#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.224.07:38:19.79#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.224.07:38:19.79#ibcon#enter wrdev, iclass 27, count 0 2006.224.07:38:19.79#ibcon#first serial, iclass 27, count 0 2006.224.07:38:19.79#ibcon#enter sib2, iclass 27, count 0 2006.224.07:38:19.79#ibcon#flushed, iclass 27, count 0 2006.224.07:38:19.79#ibcon#about to write, iclass 27, count 0 2006.224.07:38:19.79#ibcon#wrote, iclass 27, count 0 2006.224.07:38:19.79#ibcon#about to read 3, iclass 27, count 0 2006.224.07:38:19.81#ibcon#read 3, iclass 27, count 0 2006.224.07:38:19.81#ibcon#about to read 4, iclass 27, count 0 2006.224.07:38:19.81#ibcon#read 4, iclass 27, count 0 2006.224.07:38:19.81#ibcon#about to read 5, iclass 27, count 0 2006.224.07:38:19.81#ibcon#read 5, iclass 27, count 0 2006.224.07:38:19.81#ibcon#about to read 6, iclass 27, count 0 2006.224.07:38:19.81#ibcon#read 6, iclass 27, count 0 2006.224.07:38:19.81#ibcon#end of sib2, iclass 27, count 0 2006.224.07:38:19.81#ibcon#*mode == 0, iclass 27, count 0 2006.224.07:38:19.81#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.224.07:38:19.81#ibcon#[25=USB\r\n] 2006.224.07:38:19.81#ibcon#*before write, iclass 27, count 0 2006.224.07:38:19.81#ibcon#enter sib2, iclass 27, count 0 2006.224.07:38:19.81#ibcon#flushed, iclass 27, count 0 2006.224.07:38:19.81#ibcon#about to write, iclass 27, count 0 2006.224.07:38:19.81#ibcon#wrote, iclass 27, count 0 2006.224.07:38:19.81#ibcon#about to read 3, iclass 27, count 0 2006.224.07:38:19.84#ibcon#read 3, iclass 27, count 0 2006.224.07:38:19.84#ibcon#about to read 4, iclass 27, count 0 2006.224.07:38:19.84#ibcon#read 4, iclass 27, count 0 2006.224.07:38:19.84#ibcon#about to read 5, iclass 27, count 0 2006.224.07:38:19.84#ibcon#read 5, iclass 27, count 0 2006.224.07:38:19.84#ibcon#about to read 6, iclass 27, count 0 2006.224.07:38:19.84#ibcon#read 6, iclass 27, count 0 2006.224.07:38:19.84#ibcon#end of sib2, iclass 27, count 0 2006.224.07:38:19.84#ibcon#*after write, iclass 27, count 0 2006.224.07:38:19.84#ibcon#*before return 0, iclass 27, count 0 2006.224.07:38:19.84#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.224.07:38:19.84#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.224.07:38:19.84#ibcon#about to clear, iclass 27 cls_cnt 0 2006.224.07:38:19.84#ibcon#cleared, iclass 27 cls_cnt 0 2006.224.07:38:19.84$vc4f8/valo=7,832.99 2006.224.07:38:19.84#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.224.07:38:19.84#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.224.07:38:19.84#ibcon#ireg 17 cls_cnt 0 2006.224.07:38:19.84#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.224.07:38:19.84#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.224.07:38:19.84#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.224.07:38:19.84#ibcon#enter wrdev, iclass 30, count 0 2006.224.07:38:19.84#ibcon#first serial, iclass 30, count 0 2006.224.07:38:19.84#ibcon#enter sib2, iclass 30, count 0 2006.224.07:38:19.84#ibcon#flushed, iclass 30, count 0 2006.224.07:38:19.84#ibcon#about to write, iclass 30, count 0 2006.224.07:38:19.84#ibcon#wrote, iclass 30, count 0 2006.224.07:38:19.84#ibcon#about to read 3, iclass 30, count 0 2006.224.07:38:19.86#ibcon#read 3, iclass 30, count 0 2006.224.07:38:19.86#ibcon#about to read 4, iclass 30, count 0 2006.224.07:38:19.86#ibcon#read 4, iclass 30, count 0 2006.224.07:38:19.86#ibcon#about to read 5, iclass 30, count 0 2006.224.07:38:19.86#ibcon#read 5, iclass 30, count 0 2006.224.07:38:19.86#ibcon#about to read 6, iclass 30, count 0 2006.224.07:38:19.86#ibcon#read 6, iclass 30, count 0 2006.224.07:38:19.86#ibcon#end of sib2, iclass 30, count 0 2006.224.07:38:19.86#ibcon#*mode == 0, iclass 30, count 0 2006.224.07:38:19.86#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.224.07:38:19.86#ibcon#[26=FRQ=07,832.99\r\n] 2006.224.07:38:19.86#ibcon#*before write, iclass 30, count 0 2006.224.07:38:19.86#ibcon#enter sib2, iclass 30, count 0 2006.224.07:38:19.86#ibcon#flushed, iclass 30, count 0 2006.224.07:38:19.86#ibcon#about to write, iclass 30, count 0 2006.224.07:38:19.86#ibcon#wrote, iclass 30, count 0 2006.224.07:38:19.86#ibcon#about to read 3, iclass 30, count 0 2006.224.07:38:19.90#ibcon#read 3, iclass 30, count 0 2006.224.07:38:19.90#ibcon#about to read 4, iclass 30, count 0 2006.224.07:38:19.90#ibcon#read 4, iclass 30, count 0 2006.224.07:38:19.90#ibcon#about to read 5, iclass 30, count 0 2006.224.07:38:19.90#ibcon#read 5, iclass 30, count 0 2006.224.07:38:19.90#ibcon#about to read 6, iclass 30, count 0 2006.224.07:38:19.90#ibcon#read 6, iclass 30, count 0 2006.224.07:38:19.90#ibcon#end of sib2, iclass 30, count 0 2006.224.07:38:19.90#ibcon#*after write, iclass 30, count 0 2006.224.07:38:19.90#ibcon#*before return 0, iclass 30, count 0 2006.224.07:38:19.90#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.224.07:38:19.90#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.224.07:38:19.90#ibcon#about to clear, iclass 30 cls_cnt 0 2006.224.07:38:19.90#ibcon#cleared, iclass 30 cls_cnt 0 2006.224.07:38:19.90$vc4f8/va=7,6 2006.224.07:38:19.90#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.224.07:38:19.90#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.224.07:38:19.90#ibcon#ireg 11 cls_cnt 2 2006.224.07:38:19.90#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.224.07:38:19.96#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.224.07:38:19.96#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.224.07:38:19.96#ibcon#enter wrdev, iclass 32, count 2 2006.224.07:38:19.96#ibcon#first serial, iclass 32, count 2 2006.224.07:38:19.96#ibcon#enter sib2, iclass 32, count 2 2006.224.07:38:19.96#ibcon#flushed, iclass 32, count 2 2006.224.07:38:19.96#ibcon#about to write, iclass 32, count 2 2006.224.07:38:19.96#ibcon#wrote, iclass 32, count 2 2006.224.07:38:19.96#ibcon#about to read 3, iclass 32, count 2 2006.224.07:38:19.98#ibcon#read 3, iclass 32, count 2 2006.224.07:38:19.98#ibcon#about to read 4, iclass 32, count 2 2006.224.07:38:19.98#ibcon#read 4, iclass 32, count 2 2006.224.07:38:19.98#ibcon#about to read 5, iclass 32, count 2 2006.224.07:38:19.98#ibcon#read 5, iclass 32, count 2 2006.224.07:38:19.98#ibcon#about to read 6, iclass 32, count 2 2006.224.07:38:19.98#ibcon#read 6, iclass 32, count 2 2006.224.07:38:19.98#ibcon#end of sib2, iclass 32, count 2 2006.224.07:38:19.98#ibcon#*mode == 0, iclass 32, count 2 2006.224.07:38:19.98#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.224.07:38:19.98#ibcon#[25=AT07-06\r\n] 2006.224.07:38:19.98#ibcon#*before write, iclass 32, count 2 2006.224.07:38:19.98#ibcon#enter sib2, iclass 32, count 2 2006.224.07:38:19.98#ibcon#flushed, iclass 32, count 2 2006.224.07:38:19.98#ibcon#about to write, iclass 32, count 2 2006.224.07:38:19.98#ibcon#wrote, iclass 32, count 2 2006.224.07:38:19.98#ibcon#about to read 3, iclass 32, count 2 2006.224.07:38:20.01#ibcon#read 3, iclass 32, count 2 2006.224.07:38:20.01#ibcon#about to read 4, iclass 32, count 2 2006.224.07:38:20.01#ibcon#read 4, iclass 32, count 2 2006.224.07:38:20.01#ibcon#about to read 5, iclass 32, count 2 2006.224.07:38:20.01#ibcon#read 5, iclass 32, count 2 2006.224.07:38:20.01#ibcon#about to read 6, iclass 32, count 2 2006.224.07:38:20.01#ibcon#read 6, iclass 32, count 2 2006.224.07:38:20.01#ibcon#end of sib2, iclass 32, count 2 2006.224.07:38:20.01#ibcon#*after write, iclass 32, count 2 2006.224.07:38:20.01#ibcon#*before return 0, iclass 32, count 2 2006.224.07:38:20.01#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.224.07:38:20.01#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.224.07:38:20.01#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.224.07:38:20.01#ibcon#ireg 7 cls_cnt 0 2006.224.07:38:20.01#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.224.07:38:20.13#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.224.07:38:20.13#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.224.07:38:20.13#ibcon#enter wrdev, iclass 32, count 0 2006.224.07:38:20.13#ibcon#first serial, iclass 32, count 0 2006.224.07:38:20.13#ibcon#enter sib2, iclass 32, count 0 2006.224.07:38:20.13#ibcon#flushed, iclass 32, count 0 2006.224.07:38:20.13#ibcon#about to write, iclass 32, count 0 2006.224.07:38:20.13#ibcon#wrote, iclass 32, count 0 2006.224.07:38:20.13#ibcon#about to read 3, iclass 32, count 0 2006.224.07:38:20.15#ibcon#read 3, iclass 32, count 0 2006.224.07:38:20.15#ibcon#about to read 4, iclass 32, count 0 2006.224.07:38:20.15#ibcon#read 4, iclass 32, count 0 2006.224.07:38:20.15#ibcon#about to read 5, iclass 32, count 0 2006.224.07:38:20.15#ibcon#read 5, iclass 32, count 0 2006.224.07:38:20.15#ibcon#about to read 6, iclass 32, count 0 2006.224.07:38:20.15#ibcon#read 6, iclass 32, count 0 2006.224.07:38:20.15#ibcon#end of sib2, iclass 32, count 0 2006.224.07:38:20.15#ibcon#*mode == 0, iclass 32, count 0 2006.224.07:38:20.15#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.224.07:38:20.15#ibcon#[25=USB\r\n] 2006.224.07:38:20.15#ibcon#*before write, iclass 32, count 0 2006.224.07:38:20.15#ibcon#enter sib2, iclass 32, count 0 2006.224.07:38:20.15#ibcon#flushed, iclass 32, count 0 2006.224.07:38:20.15#ibcon#about to write, iclass 32, count 0 2006.224.07:38:20.15#ibcon#wrote, iclass 32, count 0 2006.224.07:38:20.15#ibcon#about to read 3, iclass 32, count 0 2006.224.07:38:20.18#ibcon#read 3, iclass 32, count 0 2006.224.07:38:20.18#ibcon#about to read 4, iclass 32, count 0 2006.224.07:38:20.18#ibcon#read 4, iclass 32, count 0 2006.224.07:38:20.18#ibcon#about to read 5, iclass 32, count 0 2006.224.07:38:20.18#ibcon#read 5, iclass 32, count 0 2006.224.07:38:20.18#ibcon#about to read 6, iclass 32, count 0 2006.224.07:38:20.18#ibcon#read 6, iclass 32, count 0 2006.224.07:38:20.18#ibcon#end of sib2, iclass 32, count 0 2006.224.07:38:20.18#ibcon#*after write, iclass 32, count 0 2006.224.07:38:20.18#ibcon#*before return 0, iclass 32, count 0 2006.224.07:38:20.18#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.224.07:38:20.18#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.224.07:38:20.18#ibcon#about to clear, iclass 32 cls_cnt 0 2006.224.07:38:20.18#ibcon#cleared, iclass 32 cls_cnt 0 2006.224.07:38:20.18$vc4f8/valo=8,852.99 2006.224.07:38:20.18#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.224.07:38:20.18#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.224.07:38:20.18#ibcon#ireg 17 cls_cnt 0 2006.224.07:38:20.18#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.224.07:38:20.18#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.224.07:38:20.18#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.224.07:38:20.18#ibcon#enter wrdev, iclass 34, count 0 2006.224.07:38:20.18#ibcon#first serial, iclass 34, count 0 2006.224.07:38:20.18#ibcon#enter sib2, iclass 34, count 0 2006.224.07:38:20.18#ibcon#flushed, iclass 34, count 0 2006.224.07:38:20.18#ibcon#about to write, iclass 34, count 0 2006.224.07:38:20.18#ibcon#wrote, iclass 34, count 0 2006.224.07:38:20.18#ibcon#about to read 3, iclass 34, count 0 2006.224.07:38:20.20#ibcon#read 3, iclass 34, count 0 2006.224.07:38:20.20#ibcon#about to read 4, iclass 34, count 0 2006.224.07:38:20.20#ibcon#read 4, iclass 34, count 0 2006.224.07:38:20.20#ibcon#about to read 5, iclass 34, count 0 2006.224.07:38:20.20#ibcon#read 5, iclass 34, count 0 2006.224.07:38:20.20#ibcon#about to read 6, iclass 34, count 0 2006.224.07:38:20.20#ibcon#read 6, iclass 34, count 0 2006.224.07:38:20.20#ibcon#end of sib2, iclass 34, count 0 2006.224.07:38:20.20#ibcon#*mode == 0, iclass 34, count 0 2006.224.07:38:20.20#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.224.07:38:20.20#ibcon#[26=FRQ=08,852.99\r\n] 2006.224.07:38:20.20#ibcon#*before write, iclass 34, count 0 2006.224.07:38:20.20#ibcon#enter sib2, iclass 34, count 0 2006.224.07:38:20.20#ibcon#flushed, iclass 34, count 0 2006.224.07:38:20.20#ibcon#about to write, iclass 34, count 0 2006.224.07:38:20.20#ibcon#wrote, iclass 34, count 0 2006.224.07:38:20.20#ibcon#about to read 3, iclass 34, count 0 2006.224.07:38:20.24#ibcon#read 3, iclass 34, count 0 2006.224.07:38:20.24#ibcon#about to read 4, iclass 34, count 0 2006.224.07:38:20.24#ibcon#read 4, iclass 34, count 0 2006.224.07:38:20.24#ibcon#about to read 5, iclass 34, count 0 2006.224.07:38:20.24#ibcon#read 5, iclass 34, count 0 2006.224.07:38:20.24#ibcon#about to read 6, iclass 34, count 0 2006.224.07:38:20.24#ibcon#read 6, iclass 34, count 0 2006.224.07:38:20.24#ibcon#end of sib2, iclass 34, count 0 2006.224.07:38:20.24#ibcon#*after write, iclass 34, count 0 2006.224.07:38:20.24#ibcon#*before return 0, iclass 34, count 0 2006.224.07:38:20.24#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.224.07:38:20.24#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.224.07:38:20.24#ibcon#about to clear, iclass 34 cls_cnt 0 2006.224.07:38:20.24#ibcon#cleared, iclass 34 cls_cnt 0 2006.224.07:38:20.24$vc4f8/va=8,7 2006.224.07:38:20.24#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.224.07:38:20.24#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.224.07:38:20.24#ibcon#ireg 11 cls_cnt 2 2006.224.07:38:20.24#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.224.07:38:20.30#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.224.07:38:20.30#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.224.07:38:20.30#ibcon#enter wrdev, iclass 36, count 2 2006.224.07:38:20.30#ibcon#first serial, iclass 36, count 2 2006.224.07:38:20.30#ibcon#enter sib2, iclass 36, count 2 2006.224.07:38:20.30#ibcon#flushed, iclass 36, count 2 2006.224.07:38:20.30#ibcon#about to write, iclass 36, count 2 2006.224.07:38:20.30#ibcon#wrote, iclass 36, count 2 2006.224.07:38:20.30#ibcon#about to read 3, iclass 36, count 2 2006.224.07:38:20.32#ibcon#read 3, iclass 36, count 2 2006.224.07:38:20.32#ibcon#about to read 4, iclass 36, count 2 2006.224.07:38:20.32#ibcon#read 4, iclass 36, count 2 2006.224.07:38:20.32#ibcon#about to read 5, iclass 36, count 2 2006.224.07:38:20.32#ibcon#read 5, iclass 36, count 2 2006.224.07:38:20.32#ibcon#about to read 6, iclass 36, count 2 2006.224.07:38:20.32#ibcon#read 6, iclass 36, count 2 2006.224.07:38:20.32#ibcon#end of sib2, iclass 36, count 2 2006.224.07:38:20.32#ibcon#*mode == 0, iclass 36, count 2 2006.224.07:38:20.32#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.224.07:38:20.32#ibcon#[25=AT08-07\r\n] 2006.224.07:38:20.32#ibcon#*before write, iclass 36, count 2 2006.224.07:38:20.32#ibcon#enter sib2, iclass 36, count 2 2006.224.07:38:20.32#ibcon#flushed, iclass 36, count 2 2006.224.07:38:20.32#ibcon#about to write, iclass 36, count 2 2006.224.07:38:20.32#ibcon#wrote, iclass 36, count 2 2006.224.07:38:20.32#ibcon#about to read 3, iclass 36, count 2 2006.224.07:38:20.35#ibcon#read 3, iclass 36, count 2 2006.224.07:38:20.35#ibcon#about to read 4, iclass 36, count 2 2006.224.07:38:20.35#ibcon#read 4, iclass 36, count 2 2006.224.07:38:20.35#ibcon#about to read 5, iclass 36, count 2 2006.224.07:38:20.35#ibcon#read 5, iclass 36, count 2 2006.224.07:38:20.35#ibcon#about to read 6, iclass 36, count 2 2006.224.07:38:20.35#ibcon#read 6, iclass 36, count 2 2006.224.07:38:20.35#ibcon#end of sib2, iclass 36, count 2 2006.224.07:38:20.35#ibcon#*after write, iclass 36, count 2 2006.224.07:38:20.35#ibcon#*before return 0, iclass 36, count 2 2006.224.07:38:20.35#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.224.07:38:20.35#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.224.07:38:20.35#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.224.07:38:20.35#ibcon#ireg 7 cls_cnt 0 2006.224.07:38:20.35#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.224.07:38:20.47#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.224.07:38:20.47#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.224.07:38:20.47#ibcon#enter wrdev, iclass 36, count 0 2006.224.07:38:20.47#ibcon#first serial, iclass 36, count 0 2006.224.07:38:20.47#ibcon#enter sib2, iclass 36, count 0 2006.224.07:38:20.47#ibcon#flushed, iclass 36, count 0 2006.224.07:38:20.47#ibcon#about to write, iclass 36, count 0 2006.224.07:38:20.47#ibcon#wrote, iclass 36, count 0 2006.224.07:38:20.47#ibcon#about to read 3, iclass 36, count 0 2006.224.07:38:20.49#ibcon#read 3, iclass 36, count 0 2006.224.07:38:20.49#ibcon#about to read 4, iclass 36, count 0 2006.224.07:38:20.49#ibcon#read 4, iclass 36, count 0 2006.224.07:38:20.49#ibcon#about to read 5, iclass 36, count 0 2006.224.07:38:20.49#ibcon#read 5, iclass 36, count 0 2006.224.07:38:20.49#ibcon#about to read 6, iclass 36, count 0 2006.224.07:38:20.49#ibcon#read 6, iclass 36, count 0 2006.224.07:38:20.49#ibcon#end of sib2, iclass 36, count 0 2006.224.07:38:20.49#ibcon#*mode == 0, iclass 36, count 0 2006.224.07:38:20.49#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.224.07:38:20.49#ibcon#[25=USB\r\n] 2006.224.07:38:20.49#ibcon#*before write, iclass 36, count 0 2006.224.07:38:20.49#ibcon#enter sib2, iclass 36, count 0 2006.224.07:38:20.49#ibcon#flushed, iclass 36, count 0 2006.224.07:38:20.49#ibcon#about to write, iclass 36, count 0 2006.224.07:38:20.49#ibcon#wrote, iclass 36, count 0 2006.224.07:38:20.49#ibcon#about to read 3, iclass 36, count 0 2006.224.07:38:20.52#ibcon#read 3, iclass 36, count 0 2006.224.07:38:20.52#ibcon#about to read 4, iclass 36, count 0 2006.224.07:38:20.52#ibcon#read 4, iclass 36, count 0 2006.224.07:38:20.52#ibcon#about to read 5, iclass 36, count 0 2006.224.07:38:20.52#ibcon#read 5, iclass 36, count 0 2006.224.07:38:20.52#ibcon#about to read 6, iclass 36, count 0 2006.224.07:38:20.52#ibcon#read 6, iclass 36, count 0 2006.224.07:38:20.52#ibcon#end of sib2, iclass 36, count 0 2006.224.07:38:20.52#ibcon#*after write, iclass 36, count 0 2006.224.07:38:20.52#ibcon#*before return 0, iclass 36, count 0 2006.224.07:38:20.52#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.224.07:38:20.52#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.224.07:38:20.52#ibcon#about to clear, iclass 36 cls_cnt 0 2006.224.07:38:20.52#ibcon#cleared, iclass 36 cls_cnt 0 2006.224.07:38:20.52$vc4f8/vblo=1,632.99 2006.224.07:38:20.52#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.224.07:38:20.52#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.224.07:38:20.52#ibcon#ireg 17 cls_cnt 0 2006.224.07:38:20.52#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.224.07:38:20.52#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.224.07:38:20.52#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.224.07:38:20.52#ibcon#enter wrdev, iclass 38, count 0 2006.224.07:38:20.52#ibcon#first serial, iclass 38, count 0 2006.224.07:38:20.52#ibcon#enter sib2, iclass 38, count 0 2006.224.07:38:20.52#ibcon#flushed, iclass 38, count 0 2006.224.07:38:20.52#ibcon#about to write, iclass 38, count 0 2006.224.07:38:20.52#ibcon#wrote, iclass 38, count 0 2006.224.07:38:20.52#ibcon#about to read 3, iclass 38, count 0 2006.224.07:38:20.54#ibcon#read 3, iclass 38, count 0 2006.224.07:38:20.54#ibcon#about to read 4, iclass 38, count 0 2006.224.07:38:20.54#ibcon#read 4, iclass 38, count 0 2006.224.07:38:20.54#ibcon#about to read 5, iclass 38, count 0 2006.224.07:38:20.54#ibcon#read 5, iclass 38, count 0 2006.224.07:38:20.54#ibcon#about to read 6, iclass 38, count 0 2006.224.07:38:20.54#ibcon#read 6, iclass 38, count 0 2006.224.07:38:20.54#ibcon#end of sib2, iclass 38, count 0 2006.224.07:38:20.54#ibcon#*mode == 0, iclass 38, count 0 2006.224.07:38:20.54#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.224.07:38:20.54#ibcon#[28=FRQ=01,632.99\r\n] 2006.224.07:38:20.54#ibcon#*before write, iclass 38, count 0 2006.224.07:38:20.54#ibcon#enter sib2, iclass 38, count 0 2006.224.07:38:20.54#ibcon#flushed, iclass 38, count 0 2006.224.07:38:20.54#ibcon#about to write, iclass 38, count 0 2006.224.07:38:20.54#ibcon#wrote, iclass 38, count 0 2006.224.07:38:20.54#ibcon#about to read 3, iclass 38, count 0 2006.224.07:38:20.58#ibcon#read 3, iclass 38, count 0 2006.224.07:38:20.58#ibcon#about to read 4, iclass 38, count 0 2006.224.07:38:20.58#ibcon#read 4, iclass 38, count 0 2006.224.07:38:20.58#ibcon#about to read 5, iclass 38, count 0 2006.224.07:38:20.58#ibcon#read 5, iclass 38, count 0 2006.224.07:38:20.58#ibcon#about to read 6, iclass 38, count 0 2006.224.07:38:20.58#ibcon#read 6, iclass 38, count 0 2006.224.07:38:20.58#ibcon#end of sib2, iclass 38, count 0 2006.224.07:38:20.58#ibcon#*after write, iclass 38, count 0 2006.224.07:38:20.58#ibcon#*before return 0, iclass 38, count 0 2006.224.07:38:20.58#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.224.07:38:20.58#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.224.07:38:20.58#ibcon#about to clear, iclass 38 cls_cnt 0 2006.224.07:38:20.58#ibcon#cleared, iclass 38 cls_cnt 0 2006.224.07:38:20.58$vc4f8/vb=1,4 2006.224.07:38:20.58#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.224.07:38:20.58#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.224.07:38:20.58#ibcon#ireg 11 cls_cnt 2 2006.224.07:38:20.58#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.224.07:38:20.58#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.224.07:38:20.58#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.224.07:38:20.58#ibcon#enter wrdev, iclass 40, count 2 2006.224.07:38:20.58#ibcon#first serial, iclass 40, count 2 2006.224.07:38:20.58#ibcon#enter sib2, iclass 40, count 2 2006.224.07:38:20.58#ibcon#flushed, iclass 40, count 2 2006.224.07:38:20.58#ibcon#about to write, iclass 40, count 2 2006.224.07:38:20.58#ibcon#wrote, iclass 40, count 2 2006.224.07:38:20.58#ibcon#about to read 3, iclass 40, count 2 2006.224.07:38:20.60#ibcon#read 3, iclass 40, count 2 2006.224.07:38:20.60#ibcon#about to read 4, iclass 40, count 2 2006.224.07:38:20.60#ibcon#read 4, iclass 40, count 2 2006.224.07:38:20.60#ibcon#about to read 5, iclass 40, count 2 2006.224.07:38:20.60#ibcon#read 5, iclass 40, count 2 2006.224.07:38:20.60#ibcon#about to read 6, iclass 40, count 2 2006.224.07:38:20.60#ibcon#read 6, iclass 40, count 2 2006.224.07:38:20.60#ibcon#end of sib2, iclass 40, count 2 2006.224.07:38:20.60#ibcon#*mode == 0, iclass 40, count 2 2006.224.07:38:20.60#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.224.07:38:20.60#ibcon#[27=AT01-04\r\n] 2006.224.07:38:20.60#ibcon#*before write, iclass 40, count 2 2006.224.07:38:20.60#ibcon#enter sib2, iclass 40, count 2 2006.224.07:38:20.60#ibcon#flushed, iclass 40, count 2 2006.224.07:38:20.60#ibcon#about to write, iclass 40, count 2 2006.224.07:38:20.60#ibcon#wrote, iclass 40, count 2 2006.224.07:38:20.60#ibcon#about to read 3, iclass 40, count 2 2006.224.07:38:20.63#ibcon#read 3, iclass 40, count 2 2006.224.07:38:20.63#ibcon#about to read 4, iclass 40, count 2 2006.224.07:38:20.63#ibcon#read 4, iclass 40, count 2 2006.224.07:38:20.63#ibcon#about to read 5, iclass 40, count 2 2006.224.07:38:20.63#ibcon#read 5, iclass 40, count 2 2006.224.07:38:20.63#ibcon#about to read 6, iclass 40, count 2 2006.224.07:38:20.63#ibcon#read 6, iclass 40, count 2 2006.224.07:38:20.63#ibcon#end of sib2, iclass 40, count 2 2006.224.07:38:20.63#ibcon#*after write, iclass 40, count 2 2006.224.07:38:20.63#ibcon#*before return 0, iclass 40, count 2 2006.224.07:38:20.63#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.224.07:38:20.63#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.224.07:38:20.63#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.224.07:38:20.63#ibcon#ireg 7 cls_cnt 0 2006.224.07:38:20.63#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.224.07:38:20.75#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.224.07:38:20.75#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.224.07:38:20.75#ibcon#enter wrdev, iclass 40, count 0 2006.224.07:38:20.75#ibcon#first serial, iclass 40, count 0 2006.224.07:38:20.75#ibcon#enter sib2, iclass 40, count 0 2006.224.07:38:20.75#ibcon#flushed, iclass 40, count 0 2006.224.07:38:20.75#ibcon#about to write, iclass 40, count 0 2006.224.07:38:20.75#ibcon#wrote, iclass 40, count 0 2006.224.07:38:20.75#ibcon#about to read 3, iclass 40, count 0 2006.224.07:38:20.77#ibcon#read 3, iclass 40, count 0 2006.224.07:38:20.77#ibcon#about to read 4, iclass 40, count 0 2006.224.07:38:20.77#ibcon#read 4, iclass 40, count 0 2006.224.07:38:20.77#ibcon#about to read 5, iclass 40, count 0 2006.224.07:38:20.77#ibcon#read 5, iclass 40, count 0 2006.224.07:38:20.77#ibcon#about to read 6, iclass 40, count 0 2006.224.07:38:20.77#ibcon#read 6, iclass 40, count 0 2006.224.07:38:20.77#ibcon#end of sib2, iclass 40, count 0 2006.224.07:38:20.77#ibcon#*mode == 0, iclass 40, count 0 2006.224.07:38:20.77#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.224.07:38:20.77#ibcon#[27=USB\r\n] 2006.224.07:38:20.77#ibcon#*before write, iclass 40, count 0 2006.224.07:38:20.77#ibcon#enter sib2, iclass 40, count 0 2006.224.07:38:20.77#ibcon#flushed, iclass 40, count 0 2006.224.07:38:20.77#ibcon#about to write, iclass 40, count 0 2006.224.07:38:20.77#ibcon#wrote, iclass 40, count 0 2006.224.07:38:20.77#ibcon#about to read 3, iclass 40, count 0 2006.224.07:38:20.80#ibcon#read 3, iclass 40, count 0 2006.224.07:38:20.80#ibcon#about to read 4, iclass 40, count 0 2006.224.07:38:20.80#ibcon#read 4, iclass 40, count 0 2006.224.07:38:20.80#ibcon#about to read 5, iclass 40, count 0 2006.224.07:38:20.80#ibcon#read 5, iclass 40, count 0 2006.224.07:38:20.80#ibcon#about to read 6, iclass 40, count 0 2006.224.07:38:20.80#ibcon#read 6, iclass 40, count 0 2006.224.07:38:20.80#ibcon#end of sib2, iclass 40, count 0 2006.224.07:38:20.80#ibcon#*after write, iclass 40, count 0 2006.224.07:38:20.80#ibcon#*before return 0, iclass 40, count 0 2006.224.07:38:20.80#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.224.07:38:20.80#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.224.07:38:20.80#ibcon#about to clear, iclass 40 cls_cnt 0 2006.224.07:38:20.80#ibcon#cleared, iclass 40 cls_cnt 0 2006.224.07:38:20.80$vc4f8/vblo=2,640.99 2006.224.07:38:20.80#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.224.07:38:20.80#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.224.07:38:20.80#ibcon#ireg 17 cls_cnt 0 2006.224.07:38:20.80#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.224.07:38:20.80#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.224.07:38:20.80#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.224.07:38:20.80#ibcon#enter wrdev, iclass 4, count 0 2006.224.07:38:20.80#ibcon#first serial, iclass 4, count 0 2006.224.07:38:20.80#ibcon#enter sib2, iclass 4, count 0 2006.224.07:38:20.80#ibcon#flushed, iclass 4, count 0 2006.224.07:38:20.80#ibcon#about to write, iclass 4, count 0 2006.224.07:38:20.80#ibcon#wrote, iclass 4, count 0 2006.224.07:38:20.80#ibcon#about to read 3, iclass 4, count 0 2006.224.07:38:20.82#ibcon#read 3, iclass 4, count 0 2006.224.07:38:20.82#ibcon#about to read 4, iclass 4, count 0 2006.224.07:38:20.82#ibcon#read 4, iclass 4, count 0 2006.224.07:38:20.82#ibcon#about to read 5, iclass 4, count 0 2006.224.07:38:20.82#ibcon#read 5, iclass 4, count 0 2006.224.07:38:20.82#ibcon#about to read 6, iclass 4, count 0 2006.224.07:38:20.82#ibcon#read 6, iclass 4, count 0 2006.224.07:38:20.82#ibcon#end of sib2, iclass 4, count 0 2006.224.07:38:20.82#ibcon#*mode == 0, iclass 4, count 0 2006.224.07:38:20.82#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.224.07:38:20.82#ibcon#[28=FRQ=02,640.99\r\n] 2006.224.07:38:20.82#ibcon#*before write, iclass 4, count 0 2006.224.07:38:20.82#ibcon#enter sib2, iclass 4, count 0 2006.224.07:38:20.82#ibcon#flushed, iclass 4, count 0 2006.224.07:38:20.82#ibcon#about to write, iclass 4, count 0 2006.224.07:38:20.82#ibcon#wrote, iclass 4, count 0 2006.224.07:38:20.82#ibcon#about to read 3, iclass 4, count 0 2006.224.07:38:20.86#ibcon#read 3, iclass 4, count 0 2006.224.07:38:20.86#ibcon#about to read 4, iclass 4, count 0 2006.224.07:38:20.86#ibcon#read 4, iclass 4, count 0 2006.224.07:38:20.86#ibcon#about to read 5, iclass 4, count 0 2006.224.07:38:20.86#ibcon#read 5, iclass 4, count 0 2006.224.07:38:20.86#ibcon#about to read 6, iclass 4, count 0 2006.224.07:38:20.86#ibcon#read 6, iclass 4, count 0 2006.224.07:38:20.86#ibcon#end of sib2, iclass 4, count 0 2006.224.07:38:20.86#ibcon#*after write, iclass 4, count 0 2006.224.07:38:20.86#ibcon#*before return 0, iclass 4, count 0 2006.224.07:38:20.86#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.224.07:38:20.86#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.224.07:38:20.86#ibcon#about to clear, iclass 4 cls_cnt 0 2006.224.07:38:20.86#ibcon#cleared, iclass 4 cls_cnt 0 2006.224.07:38:20.86$vc4f8/vb=2,4 2006.224.07:38:20.86#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.224.07:38:20.86#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.224.07:38:20.86#ibcon#ireg 11 cls_cnt 2 2006.224.07:38:20.86#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.224.07:38:20.92#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.224.07:38:20.92#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.224.07:38:20.92#ibcon#enter wrdev, iclass 6, count 2 2006.224.07:38:20.92#ibcon#first serial, iclass 6, count 2 2006.224.07:38:20.92#ibcon#enter sib2, iclass 6, count 2 2006.224.07:38:20.92#ibcon#flushed, iclass 6, count 2 2006.224.07:38:20.92#ibcon#about to write, iclass 6, count 2 2006.224.07:38:20.92#ibcon#wrote, iclass 6, count 2 2006.224.07:38:20.92#ibcon#about to read 3, iclass 6, count 2 2006.224.07:38:20.94#ibcon#read 3, iclass 6, count 2 2006.224.07:38:20.94#ibcon#about to read 4, iclass 6, count 2 2006.224.07:38:20.94#ibcon#read 4, iclass 6, count 2 2006.224.07:38:20.94#ibcon#about to read 5, iclass 6, count 2 2006.224.07:38:20.94#ibcon#read 5, iclass 6, count 2 2006.224.07:38:20.94#ibcon#about to read 6, iclass 6, count 2 2006.224.07:38:20.94#ibcon#read 6, iclass 6, count 2 2006.224.07:38:20.94#ibcon#end of sib2, iclass 6, count 2 2006.224.07:38:20.94#ibcon#*mode == 0, iclass 6, count 2 2006.224.07:38:20.94#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.224.07:38:20.94#ibcon#[27=AT02-04\r\n] 2006.224.07:38:20.94#ibcon#*before write, iclass 6, count 2 2006.224.07:38:20.94#ibcon#enter sib2, iclass 6, count 2 2006.224.07:38:20.94#ibcon#flushed, iclass 6, count 2 2006.224.07:38:20.94#ibcon#about to write, iclass 6, count 2 2006.224.07:38:20.94#ibcon#wrote, iclass 6, count 2 2006.224.07:38:20.94#ibcon#about to read 3, iclass 6, count 2 2006.224.07:38:20.97#ibcon#read 3, iclass 6, count 2 2006.224.07:38:20.97#ibcon#about to read 4, iclass 6, count 2 2006.224.07:38:20.97#ibcon#read 4, iclass 6, count 2 2006.224.07:38:20.97#ibcon#about to read 5, iclass 6, count 2 2006.224.07:38:20.97#ibcon#read 5, iclass 6, count 2 2006.224.07:38:20.97#ibcon#about to read 6, iclass 6, count 2 2006.224.07:38:20.97#ibcon#read 6, iclass 6, count 2 2006.224.07:38:20.97#ibcon#end of sib2, iclass 6, count 2 2006.224.07:38:20.97#ibcon#*after write, iclass 6, count 2 2006.224.07:38:20.97#ibcon#*before return 0, iclass 6, count 2 2006.224.07:38:20.97#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.224.07:38:20.97#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.224.07:38:20.97#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.224.07:38:20.97#ibcon#ireg 7 cls_cnt 0 2006.224.07:38:20.97#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.224.07:38:21.09#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.224.07:38:21.09#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.224.07:38:21.09#ibcon#enter wrdev, iclass 6, count 0 2006.224.07:38:21.09#ibcon#first serial, iclass 6, count 0 2006.224.07:38:21.09#ibcon#enter sib2, iclass 6, count 0 2006.224.07:38:21.09#ibcon#flushed, iclass 6, count 0 2006.224.07:38:21.09#ibcon#about to write, iclass 6, count 0 2006.224.07:38:21.09#ibcon#wrote, iclass 6, count 0 2006.224.07:38:21.09#ibcon#about to read 3, iclass 6, count 0 2006.224.07:38:21.11#ibcon#read 3, iclass 6, count 0 2006.224.07:38:21.11#ibcon#about to read 4, iclass 6, count 0 2006.224.07:38:21.11#ibcon#read 4, iclass 6, count 0 2006.224.07:38:21.11#ibcon#about to read 5, iclass 6, count 0 2006.224.07:38:21.11#ibcon#read 5, iclass 6, count 0 2006.224.07:38:21.11#ibcon#about to read 6, iclass 6, count 0 2006.224.07:38:21.11#ibcon#read 6, iclass 6, count 0 2006.224.07:38:21.11#ibcon#end of sib2, iclass 6, count 0 2006.224.07:38:21.11#ibcon#*mode == 0, iclass 6, count 0 2006.224.07:38:21.11#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.224.07:38:21.11#ibcon#[27=USB\r\n] 2006.224.07:38:21.11#ibcon#*before write, iclass 6, count 0 2006.224.07:38:21.11#ibcon#enter sib2, iclass 6, count 0 2006.224.07:38:21.11#ibcon#flushed, iclass 6, count 0 2006.224.07:38:21.11#ibcon#about to write, iclass 6, count 0 2006.224.07:38:21.11#ibcon#wrote, iclass 6, count 0 2006.224.07:38:21.11#ibcon#about to read 3, iclass 6, count 0 2006.224.07:38:21.14#ibcon#read 3, iclass 6, count 0 2006.224.07:38:21.14#ibcon#about to read 4, iclass 6, count 0 2006.224.07:38:21.14#ibcon#read 4, iclass 6, count 0 2006.224.07:38:21.14#ibcon#about to read 5, iclass 6, count 0 2006.224.07:38:21.14#ibcon#read 5, iclass 6, count 0 2006.224.07:38:21.14#ibcon#about to read 6, iclass 6, count 0 2006.224.07:38:21.14#ibcon#read 6, iclass 6, count 0 2006.224.07:38:21.14#ibcon#end of sib2, iclass 6, count 0 2006.224.07:38:21.14#ibcon#*after write, iclass 6, count 0 2006.224.07:38:21.14#ibcon#*before return 0, iclass 6, count 0 2006.224.07:38:21.14#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.224.07:38:21.14#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.224.07:38:21.14#ibcon#about to clear, iclass 6 cls_cnt 0 2006.224.07:38:21.14#ibcon#cleared, iclass 6 cls_cnt 0 2006.224.07:38:21.14$vc4f8/vblo=3,656.99 2006.224.07:38:21.14#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.224.07:38:21.14#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.224.07:38:21.14#ibcon#ireg 17 cls_cnt 0 2006.224.07:38:21.14#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.224.07:38:21.14#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.224.07:38:21.14#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.224.07:38:21.14#ibcon#enter wrdev, iclass 10, count 0 2006.224.07:38:21.14#ibcon#first serial, iclass 10, count 0 2006.224.07:38:21.14#ibcon#enter sib2, iclass 10, count 0 2006.224.07:38:21.14#ibcon#flushed, iclass 10, count 0 2006.224.07:38:21.14#ibcon#about to write, iclass 10, count 0 2006.224.07:38:21.14#ibcon#wrote, iclass 10, count 0 2006.224.07:38:21.14#ibcon#about to read 3, iclass 10, count 0 2006.224.07:38:21.16#ibcon#read 3, iclass 10, count 0 2006.224.07:38:21.16#ibcon#about to read 4, iclass 10, count 0 2006.224.07:38:21.16#ibcon#read 4, iclass 10, count 0 2006.224.07:38:21.16#ibcon#about to read 5, iclass 10, count 0 2006.224.07:38:21.16#ibcon#read 5, iclass 10, count 0 2006.224.07:38:21.16#ibcon#about to read 6, iclass 10, count 0 2006.224.07:38:21.16#ibcon#read 6, iclass 10, count 0 2006.224.07:38:21.16#ibcon#end of sib2, iclass 10, count 0 2006.224.07:38:21.16#ibcon#*mode == 0, iclass 10, count 0 2006.224.07:38:21.16#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.224.07:38:21.16#ibcon#[28=FRQ=03,656.99\r\n] 2006.224.07:38:21.16#ibcon#*before write, iclass 10, count 0 2006.224.07:38:21.16#ibcon#enter sib2, iclass 10, count 0 2006.224.07:38:21.16#ibcon#flushed, iclass 10, count 0 2006.224.07:38:21.16#ibcon#about to write, iclass 10, count 0 2006.224.07:38:21.16#ibcon#wrote, iclass 10, count 0 2006.224.07:38:21.16#ibcon#about to read 3, iclass 10, count 0 2006.224.07:38:21.20#ibcon#read 3, iclass 10, count 0 2006.224.07:38:21.20#ibcon#about to read 4, iclass 10, count 0 2006.224.07:38:21.20#ibcon#read 4, iclass 10, count 0 2006.224.07:38:21.20#ibcon#about to read 5, iclass 10, count 0 2006.224.07:38:21.20#ibcon#read 5, iclass 10, count 0 2006.224.07:38:21.20#ibcon#about to read 6, iclass 10, count 0 2006.224.07:38:21.20#ibcon#read 6, iclass 10, count 0 2006.224.07:38:21.20#ibcon#end of sib2, iclass 10, count 0 2006.224.07:38:21.20#ibcon#*after write, iclass 10, count 0 2006.224.07:38:21.20#ibcon#*before return 0, iclass 10, count 0 2006.224.07:38:21.20#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.224.07:38:21.20#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.224.07:38:21.20#ibcon#about to clear, iclass 10 cls_cnt 0 2006.224.07:38:21.20#ibcon#cleared, iclass 10 cls_cnt 0 2006.224.07:38:21.20$vc4f8/vb=3,4 2006.224.07:38:21.20#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.224.07:38:21.20#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.224.07:38:21.20#ibcon#ireg 11 cls_cnt 2 2006.224.07:38:21.20#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.224.07:38:21.26#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.224.07:38:21.26#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.224.07:38:21.26#ibcon#enter wrdev, iclass 12, count 2 2006.224.07:38:21.26#ibcon#first serial, iclass 12, count 2 2006.224.07:38:21.26#ibcon#enter sib2, iclass 12, count 2 2006.224.07:38:21.26#ibcon#flushed, iclass 12, count 2 2006.224.07:38:21.26#ibcon#about to write, iclass 12, count 2 2006.224.07:38:21.26#ibcon#wrote, iclass 12, count 2 2006.224.07:38:21.26#ibcon#about to read 3, iclass 12, count 2 2006.224.07:38:21.28#ibcon#read 3, iclass 12, count 2 2006.224.07:38:21.28#ibcon#about to read 4, iclass 12, count 2 2006.224.07:38:21.28#ibcon#read 4, iclass 12, count 2 2006.224.07:38:21.28#ibcon#about to read 5, iclass 12, count 2 2006.224.07:38:21.28#ibcon#read 5, iclass 12, count 2 2006.224.07:38:21.28#ibcon#about to read 6, iclass 12, count 2 2006.224.07:38:21.28#ibcon#read 6, iclass 12, count 2 2006.224.07:38:21.28#ibcon#end of sib2, iclass 12, count 2 2006.224.07:38:21.28#ibcon#*mode == 0, iclass 12, count 2 2006.224.07:38:21.28#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.224.07:38:21.28#ibcon#[27=AT03-04\r\n] 2006.224.07:38:21.28#ibcon#*before write, iclass 12, count 2 2006.224.07:38:21.28#ibcon#enter sib2, iclass 12, count 2 2006.224.07:38:21.28#ibcon#flushed, iclass 12, count 2 2006.224.07:38:21.28#ibcon#about to write, iclass 12, count 2 2006.224.07:38:21.28#ibcon#wrote, iclass 12, count 2 2006.224.07:38:21.28#ibcon#about to read 3, iclass 12, count 2 2006.224.07:38:21.32#ibcon#read 3, iclass 12, count 2 2006.224.07:38:21.32#ibcon#about to read 4, iclass 12, count 2 2006.224.07:38:21.32#ibcon#read 4, iclass 12, count 2 2006.224.07:38:21.32#ibcon#about to read 5, iclass 12, count 2 2006.224.07:38:21.32#ibcon#read 5, iclass 12, count 2 2006.224.07:38:21.32#ibcon#about to read 6, iclass 12, count 2 2006.224.07:38:21.32#ibcon#read 6, iclass 12, count 2 2006.224.07:38:21.32#ibcon#end of sib2, iclass 12, count 2 2006.224.07:38:21.32#ibcon#*after write, iclass 12, count 2 2006.224.07:38:21.32#ibcon#*before return 0, iclass 12, count 2 2006.224.07:38:21.32#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.224.07:38:21.32#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.224.07:38:21.32#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.224.07:38:21.32#ibcon#ireg 7 cls_cnt 0 2006.224.07:38:21.32#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.224.07:38:21.44#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.224.07:38:21.44#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.224.07:38:21.44#ibcon#enter wrdev, iclass 12, count 0 2006.224.07:38:21.44#ibcon#first serial, iclass 12, count 0 2006.224.07:38:21.44#ibcon#enter sib2, iclass 12, count 0 2006.224.07:38:21.44#ibcon#flushed, iclass 12, count 0 2006.224.07:38:21.44#ibcon#about to write, iclass 12, count 0 2006.224.07:38:21.44#ibcon#wrote, iclass 12, count 0 2006.224.07:38:21.44#ibcon#about to read 3, iclass 12, count 0 2006.224.07:38:21.46#ibcon#read 3, iclass 12, count 0 2006.224.07:38:21.46#ibcon#about to read 4, iclass 12, count 0 2006.224.07:38:21.46#ibcon#read 4, iclass 12, count 0 2006.224.07:38:21.46#ibcon#about to read 5, iclass 12, count 0 2006.224.07:38:21.46#ibcon#read 5, iclass 12, count 0 2006.224.07:38:21.46#ibcon#about to read 6, iclass 12, count 0 2006.224.07:38:21.46#ibcon#read 6, iclass 12, count 0 2006.224.07:38:21.46#ibcon#end of sib2, iclass 12, count 0 2006.224.07:38:21.46#ibcon#*mode == 0, iclass 12, count 0 2006.224.07:38:21.46#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.224.07:38:21.46#ibcon#[27=USB\r\n] 2006.224.07:38:21.46#ibcon#*before write, iclass 12, count 0 2006.224.07:38:21.46#ibcon#enter sib2, iclass 12, count 0 2006.224.07:38:21.46#ibcon#flushed, iclass 12, count 0 2006.224.07:38:21.46#ibcon#about to write, iclass 12, count 0 2006.224.07:38:21.46#ibcon#wrote, iclass 12, count 0 2006.224.07:38:21.46#ibcon#about to read 3, iclass 12, count 0 2006.224.07:38:21.49#ibcon#read 3, iclass 12, count 0 2006.224.07:38:21.49#ibcon#about to read 4, iclass 12, count 0 2006.224.07:38:21.49#ibcon#read 4, iclass 12, count 0 2006.224.07:38:21.49#ibcon#about to read 5, iclass 12, count 0 2006.224.07:38:21.49#ibcon#read 5, iclass 12, count 0 2006.224.07:38:21.49#ibcon#about to read 6, iclass 12, count 0 2006.224.07:38:21.49#ibcon#read 6, iclass 12, count 0 2006.224.07:38:21.49#ibcon#end of sib2, iclass 12, count 0 2006.224.07:38:21.49#ibcon#*after write, iclass 12, count 0 2006.224.07:38:21.49#ibcon#*before return 0, iclass 12, count 0 2006.224.07:38:21.49#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.224.07:38:21.49#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.224.07:38:21.49#ibcon#about to clear, iclass 12 cls_cnt 0 2006.224.07:38:21.49#ibcon#cleared, iclass 12 cls_cnt 0 2006.224.07:38:21.49$vc4f8/vblo=4,712.99 2006.224.07:38:21.49#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.224.07:38:21.49#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.224.07:38:21.49#ibcon#ireg 17 cls_cnt 0 2006.224.07:38:21.49#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.224.07:38:21.49#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.224.07:38:21.49#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.224.07:38:21.49#ibcon#enter wrdev, iclass 14, count 0 2006.224.07:38:21.49#ibcon#first serial, iclass 14, count 0 2006.224.07:38:21.49#ibcon#enter sib2, iclass 14, count 0 2006.224.07:38:21.49#ibcon#flushed, iclass 14, count 0 2006.224.07:38:21.49#ibcon#about to write, iclass 14, count 0 2006.224.07:38:21.49#ibcon#wrote, iclass 14, count 0 2006.224.07:38:21.49#ibcon#about to read 3, iclass 14, count 0 2006.224.07:38:21.51#ibcon#read 3, iclass 14, count 0 2006.224.07:38:21.51#ibcon#about to read 4, iclass 14, count 0 2006.224.07:38:21.51#ibcon#read 4, iclass 14, count 0 2006.224.07:38:21.51#ibcon#about to read 5, iclass 14, count 0 2006.224.07:38:21.51#ibcon#read 5, iclass 14, count 0 2006.224.07:38:21.51#ibcon#about to read 6, iclass 14, count 0 2006.224.07:38:21.51#ibcon#read 6, iclass 14, count 0 2006.224.07:38:21.51#ibcon#end of sib2, iclass 14, count 0 2006.224.07:38:21.51#ibcon#*mode == 0, iclass 14, count 0 2006.224.07:38:21.51#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.224.07:38:21.51#ibcon#[28=FRQ=04,712.99\r\n] 2006.224.07:38:21.51#ibcon#*before write, iclass 14, count 0 2006.224.07:38:21.51#ibcon#enter sib2, iclass 14, count 0 2006.224.07:38:21.51#ibcon#flushed, iclass 14, count 0 2006.224.07:38:21.51#ibcon#about to write, iclass 14, count 0 2006.224.07:38:21.51#ibcon#wrote, iclass 14, count 0 2006.224.07:38:21.51#ibcon#about to read 3, iclass 14, count 0 2006.224.07:38:21.55#ibcon#read 3, iclass 14, count 0 2006.224.07:38:21.55#ibcon#about to read 4, iclass 14, count 0 2006.224.07:38:21.55#ibcon#read 4, iclass 14, count 0 2006.224.07:38:21.55#ibcon#about to read 5, iclass 14, count 0 2006.224.07:38:21.55#ibcon#read 5, iclass 14, count 0 2006.224.07:38:21.55#ibcon#about to read 6, iclass 14, count 0 2006.224.07:38:21.55#ibcon#read 6, iclass 14, count 0 2006.224.07:38:21.55#ibcon#end of sib2, iclass 14, count 0 2006.224.07:38:21.55#ibcon#*after write, iclass 14, count 0 2006.224.07:38:21.55#ibcon#*before return 0, iclass 14, count 0 2006.224.07:38:21.55#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.224.07:38:21.55#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.224.07:38:21.55#ibcon#about to clear, iclass 14 cls_cnt 0 2006.224.07:38:21.55#ibcon#cleared, iclass 14 cls_cnt 0 2006.224.07:38:21.55$vc4f8/vb=4,4 2006.224.07:38:21.55#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.224.07:38:21.55#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.224.07:38:21.55#ibcon#ireg 11 cls_cnt 2 2006.224.07:38:21.55#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.224.07:38:21.61#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.224.07:38:21.61#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.224.07:38:21.61#ibcon#enter wrdev, iclass 16, count 2 2006.224.07:38:21.61#ibcon#first serial, iclass 16, count 2 2006.224.07:38:21.61#ibcon#enter sib2, iclass 16, count 2 2006.224.07:38:21.61#ibcon#flushed, iclass 16, count 2 2006.224.07:38:21.61#ibcon#about to write, iclass 16, count 2 2006.224.07:38:21.61#ibcon#wrote, iclass 16, count 2 2006.224.07:38:21.61#ibcon#about to read 3, iclass 16, count 2 2006.224.07:38:21.63#ibcon#read 3, iclass 16, count 2 2006.224.07:38:21.63#ibcon#about to read 4, iclass 16, count 2 2006.224.07:38:21.63#ibcon#read 4, iclass 16, count 2 2006.224.07:38:21.63#ibcon#about to read 5, iclass 16, count 2 2006.224.07:38:21.63#ibcon#read 5, iclass 16, count 2 2006.224.07:38:21.63#ibcon#about to read 6, iclass 16, count 2 2006.224.07:38:21.63#ibcon#read 6, iclass 16, count 2 2006.224.07:38:21.63#ibcon#end of sib2, iclass 16, count 2 2006.224.07:38:21.63#ibcon#*mode == 0, iclass 16, count 2 2006.224.07:38:21.63#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.224.07:38:21.63#ibcon#[27=AT04-04\r\n] 2006.224.07:38:21.63#ibcon#*before write, iclass 16, count 2 2006.224.07:38:21.63#ibcon#enter sib2, iclass 16, count 2 2006.224.07:38:21.63#ibcon#flushed, iclass 16, count 2 2006.224.07:38:21.63#ibcon#about to write, iclass 16, count 2 2006.224.07:38:21.63#ibcon#wrote, iclass 16, count 2 2006.224.07:38:21.63#ibcon#about to read 3, iclass 16, count 2 2006.224.07:38:21.66#ibcon#read 3, iclass 16, count 2 2006.224.07:38:21.66#ibcon#about to read 4, iclass 16, count 2 2006.224.07:38:21.66#ibcon#read 4, iclass 16, count 2 2006.224.07:38:21.66#ibcon#about to read 5, iclass 16, count 2 2006.224.07:38:21.66#ibcon#read 5, iclass 16, count 2 2006.224.07:38:21.66#ibcon#about to read 6, iclass 16, count 2 2006.224.07:38:21.66#ibcon#read 6, iclass 16, count 2 2006.224.07:38:21.66#ibcon#end of sib2, iclass 16, count 2 2006.224.07:38:21.66#ibcon#*after write, iclass 16, count 2 2006.224.07:38:21.66#ibcon#*before return 0, iclass 16, count 2 2006.224.07:38:21.66#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.224.07:38:21.66#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.224.07:38:21.66#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.224.07:38:21.66#ibcon#ireg 7 cls_cnt 0 2006.224.07:38:21.66#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.224.07:38:21.78#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.224.07:38:21.78#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.224.07:38:21.78#ibcon#enter wrdev, iclass 16, count 0 2006.224.07:38:21.78#ibcon#first serial, iclass 16, count 0 2006.224.07:38:21.78#ibcon#enter sib2, iclass 16, count 0 2006.224.07:38:21.78#ibcon#flushed, iclass 16, count 0 2006.224.07:38:21.78#ibcon#about to write, iclass 16, count 0 2006.224.07:38:21.78#ibcon#wrote, iclass 16, count 0 2006.224.07:38:21.78#ibcon#about to read 3, iclass 16, count 0 2006.224.07:38:21.80#ibcon#read 3, iclass 16, count 0 2006.224.07:38:21.80#ibcon#about to read 4, iclass 16, count 0 2006.224.07:38:21.80#ibcon#read 4, iclass 16, count 0 2006.224.07:38:21.80#ibcon#about to read 5, iclass 16, count 0 2006.224.07:38:21.80#ibcon#read 5, iclass 16, count 0 2006.224.07:38:21.80#ibcon#about to read 6, iclass 16, count 0 2006.224.07:38:21.80#ibcon#read 6, iclass 16, count 0 2006.224.07:38:21.80#ibcon#end of sib2, iclass 16, count 0 2006.224.07:38:21.80#ibcon#*mode == 0, iclass 16, count 0 2006.224.07:38:21.80#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.224.07:38:21.80#ibcon#[27=USB\r\n] 2006.224.07:38:21.80#ibcon#*before write, iclass 16, count 0 2006.224.07:38:21.80#ibcon#enter sib2, iclass 16, count 0 2006.224.07:38:21.80#ibcon#flushed, iclass 16, count 0 2006.224.07:38:21.80#ibcon#about to write, iclass 16, count 0 2006.224.07:38:21.80#ibcon#wrote, iclass 16, count 0 2006.224.07:38:21.80#ibcon#about to read 3, iclass 16, count 0 2006.224.07:38:21.83#ibcon#read 3, iclass 16, count 0 2006.224.07:38:21.83#ibcon#about to read 4, iclass 16, count 0 2006.224.07:38:21.83#ibcon#read 4, iclass 16, count 0 2006.224.07:38:21.83#ibcon#about to read 5, iclass 16, count 0 2006.224.07:38:21.83#ibcon#read 5, iclass 16, count 0 2006.224.07:38:21.83#ibcon#about to read 6, iclass 16, count 0 2006.224.07:38:21.83#ibcon#read 6, iclass 16, count 0 2006.224.07:38:21.83#ibcon#end of sib2, iclass 16, count 0 2006.224.07:38:21.83#ibcon#*after write, iclass 16, count 0 2006.224.07:38:21.83#ibcon#*before return 0, iclass 16, count 0 2006.224.07:38:21.83#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.224.07:38:21.83#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.224.07:38:21.83#ibcon#about to clear, iclass 16 cls_cnt 0 2006.224.07:38:21.83#ibcon#cleared, iclass 16 cls_cnt 0 2006.224.07:38:21.83$vc4f8/vblo=5,744.99 2006.224.07:38:21.83#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.224.07:38:21.83#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.224.07:38:21.83#ibcon#ireg 17 cls_cnt 0 2006.224.07:38:21.83#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.224.07:38:21.83#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.224.07:38:21.83#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.224.07:38:21.83#ibcon#enter wrdev, iclass 18, count 0 2006.224.07:38:21.83#ibcon#first serial, iclass 18, count 0 2006.224.07:38:21.83#ibcon#enter sib2, iclass 18, count 0 2006.224.07:38:21.83#ibcon#flushed, iclass 18, count 0 2006.224.07:38:21.83#ibcon#about to write, iclass 18, count 0 2006.224.07:38:21.83#ibcon#wrote, iclass 18, count 0 2006.224.07:38:21.83#ibcon#about to read 3, iclass 18, count 0 2006.224.07:38:21.85#ibcon#read 3, iclass 18, count 0 2006.224.07:38:21.85#ibcon#about to read 4, iclass 18, count 0 2006.224.07:38:21.85#ibcon#read 4, iclass 18, count 0 2006.224.07:38:21.85#ibcon#about to read 5, iclass 18, count 0 2006.224.07:38:21.85#ibcon#read 5, iclass 18, count 0 2006.224.07:38:21.85#ibcon#about to read 6, iclass 18, count 0 2006.224.07:38:21.85#ibcon#read 6, iclass 18, count 0 2006.224.07:38:21.85#ibcon#end of sib2, iclass 18, count 0 2006.224.07:38:21.85#ibcon#*mode == 0, iclass 18, count 0 2006.224.07:38:21.85#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.224.07:38:21.85#ibcon#[28=FRQ=05,744.99\r\n] 2006.224.07:38:21.85#ibcon#*before write, iclass 18, count 0 2006.224.07:38:21.85#ibcon#enter sib2, iclass 18, count 0 2006.224.07:38:21.85#ibcon#flushed, iclass 18, count 0 2006.224.07:38:21.85#ibcon#about to write, iclass 18, count 0 2006.224.07:38:21.85#ibcon#wrote, iclass 18, count 0 2006.224.07:38:21.85#ibcon#about to read 3, iclass 18, count 0 2006.224.07:38:21.89#ibcon#read 3, iclass 18, count 0 2006.224.07:38:21.89#ibcon#about to read 4, iclass 18, count 0 2006.224.07:38:21.89#ibcon#read 4, iclass 18, count 0 2006.224.07:38:21.89#ibcon#about to read 5, iclass 18, count 0 2006.224.07:38:21.89#ibcon#read 5, iclass 18, count 0 2006.224.07:38:21.89#ibcon#about to read 6, iclass 18, count 0 2006.224.07:38:21.89#ibcon#read 6, iclass 18, count 0 2006.224.07:38:21.89#ibcon#end of sib2, iclass 18, count 0 2006.224.07:38:21.89#ibcon#*after write, iclass 18, count 0 2006.224.07:38:21.89#ibcon#*before return 0, iclass 18, count 0 2006.224.07:38:21.89#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.224.07:38:21.89#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.224.07:38:21.89#ibcon#about to clear, iclass 18 cls_cnt 0 2006.224.07:38:21.89#ibcon#cleared, iclass 18 cls_cnt 0 2006.224.07:38:21.89$vc4f8/vb=5,4 2006.224.07:38:21.89#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.224.07:38:21.89#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.224.07:38:21.89#ibcon#ireg 11 cls_cnt 2 2006.224.07:38:21.89#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.224.07:38:21.95#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.224.07:38:21.95#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.224.07:38:21.95#ibcon#enter wrdev, iclass 20, count 2 2006.224.07:38:21.95#ibcon#first serial, iclass 20, count 2 2006.224.07:38:21.95#ibcon#enter sib2, iclass 20, count 2 2006.224.07:38:21.95#ibcon#flushed, iclass 20, count 2 2006.224.07:38:21.95#ibcon#about to write, iclass 20, count 2 2006.224.07:38:21.95#ibcon#wrote, iclass 20, count 2 2006.224.07:38:21.95#ibcon#about to read 3, iclass 20, count 2 2006.224.07:38:21.97#ibcon#read 3, iclass 20, count 2 2006.224.07:38:21.97#ibcon#about to read 4, iclass 20, count 2 2006.224.07:38:21.97#ibcon#read 4, iclass 20, count 2 2006.224.07:38:21.97#ibcon#about to read 5, iclass 20, count 2 2006.224.07:38:21.97#ibcon#read 5, iclass 20, count 2 2006.224.07:38:21.97#ibcon#about to read 6, iclass 20, count 2 2006.224.07:38:21.97#ibcon#read 6, iclass 20, count 2 2006.224.07:38:21.97#ibcon#end of sib2, iclass 20, count 2 2006.224.07:38:21.97#ibcon#*mode == 0, iclass 20, count 2 2006.224.07:38:21.97#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.224.07:38:21.97#ibcon#[27=AT05-04\r\n] 2006.224.07:38:21.97#ibcon#*before write, iclass 20, count 2 2006.224.07:38:21.97#ibcon#enter sib2, iclass 20, count 2 2006.224.07:38:21.97#ibcon#flushed, iclass 20, count 2 2006.224.07:38:21.97#ibcon#about to write, iclass 20, count 2 2006.224.07:38:21.97#ibcon#wrote, iclass 20, count 2 2006.224.07:38:21.97#ibcon#about to read 3, iclass 20, count 2 2006.224.07:38:22.00#ibcon#read 3, iclass 20, count 2 2006.224.07:38:22.00#ibcon#about to read 4, iclass 20, count 2 2006.224.07:38:22.00#ibcon#read 4, iclass 20, count 2 2006.224.07:38:22.00#ibcon#about to read 5, iclass 20, count 2 2006.224.07:38:22.00#ibcon#read 5, iclass 20, count 2 2006.224.07:38:22.00#ibcon#about to read 6, iclass 20, count 2 2006.224.07:38:22.00#ibcon#read 6, iclass 20, count 2 2006.224.07:38:22.00#ibcon#end of sib2, iclass 20, count 2 2006.224.07:38:22.00#ibcon#*after write, iclass 20, count 2 2006.224.07:38:22.00#ibcon#*before return 0, iclass 20, count 2 2006.224.07:38:22.00#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.224.07:38:22.00#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.224.07:38:22.00#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.224.07:38:22.00#ibcon#ireg 7 cls_cnt 0 2006.224.07:38:22.00#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.224.07:38:22.12#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.224.07:38:22.12#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.224.07:38:22.12#ibcon#enter wrdev, iclass 20, count 0 2006.224.07:38:22.12#ibcon#first serial, iclass 20, count 0 2006.224.07:38:22.12#ibcon#enter sib2, iclass 20, count 0 2006.224.07:38:22.12#ibcon#flushed, iclass 20, count 0 2006.224.07:38:22.12#ibcon#about to write, iclass 20, count 0 2006.224.07:38:22.12#ibcon#wrote, iclass 20, count 0 2006.224.07:38:22.12#ibcon#about to read 3, iclass 20, count 0 2006.224.07:38:22.14#ibcon#read 3, iclass 20, count 0 2006.224.07:38:22.14#ibcon#about to read 4, iclass 20, count 0 2006.224.07:38:22.14#ibcon#read 4, iclass 20, count 0 2006.224.07:38:22.14#ibcon#about to read 5, iclass 20, count 0 2006.224.07:38:22.14#ibcon#read 5, iclass 20, count 0 2006.224.07:38:22.14#ibcon#about to read 6, iclass 20, count 0 2006.224.07:38:22.14#ibcon#read 6, iclass 20, count 0 2006.224.07:38:22.14#ibcon#end of sib2, iclass 20, count 0 2006.224.07:38:22.14#ibcon#*mode == 0, iclass 20, count 0 2006.224.07:38:22.14#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.224.07:38:22.14#ibcon#[27=USB\r\n] 2006.224.07:38:22.14#ibcon#*before write, iclass 20, count 0 2006.224.07:38:22.14#ibcon#enter sib2, iclass 20, count 0 2006.224.07:38:22.14#ibcon#flushed, iclass 20, count 0 2006.224.07:38:22.14#ibcon#about to write, iclass 20, count 0 2006.224.07:38:22.14#ibcon#wrote, iclass 20, count 0 2006.224.07:38:22.14#ibcon#about to read 3, iclass 20, count 0 2006.224.07:38:22.17#ibcon#read 3, iclass 20, count 0 2006.224.07:38:22.17#ibcon#about to read 4, iclass 20, count 0 2006.224.07:38:22.17#ibcon#read 4, iclass 20, count 0 2006.224.07:38:22.17#ibcon#about to read 5, iclass 20, count 0 2006.224.07:38:22.17#ibcon#read 5, iclass 20, count 0 2006.224.07:38:22.17#ibcon#about to read 6, iclass 20, count 0 2006.224.07:38:22.17#ibcon#read 6, iclass 20, count 0 2006.224.07:38:22.17#ibcon#end of sib2, iclass 20, count 0 2006.224.07:38:22.17#ibcon#*after write, iclass 20, count 0 2006.224.07:38:22.17#ibcon#*before return 0, iclass 20, count 0 2006.224.07:38:22.17#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.224.07:38:22.17#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.224.07:38:22.17#ibcon#about to clear, iclass 20 cls_cnt 0 2006.224.07:38:22.17#ibcon#cleared, iclass 20 cls_cnt 0 2006.224.07:38:22.17$vc4f8/vblo=6,752.99 2006.224.07:38:22.17#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.224.07:38:22.17#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.224.07:38:22.17#ibcon#ireg 17 cls_cnt 0 2006.224.07:38:22.17#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.224.07:38:22.17#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.224.07:38:22.17#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.224.07:38:22.17#ibcon#enter wrdev, iclass 22, count 0 2006.224.07:38:22.17#ibcon#first serial, iclass 22, count 0 2006.224.07:38:22.17#ibcon#enter sib2, iclass 22, count 0 2006.224.07:38:22.17#ibcon#flushed, iclass 22, count 0 2006.224.07:38:22.17#ibcon#about to write, iclass 22, count 0 2006.224.07:38:22.17#ibcon#wrote, iclass 22, count 0 2006.224.07:38:22.17#ibcon#about to read 3, iclass 22, count 0 2006.224.07:38:22.19#ibcon#read 3, iclass 22, count 0 2006.224.07:38:22.19#ibcon#about to read 4, iclass 22, count 0 2006.224.07:38:22.19#ibcon#read 4, iclass 22, count 0 2006.224.07:38:22.19#ibcon#about to read 5, iclass 22, count 0 2006.224.07:38:22.19#ibcon#read 5, iclass 22, count 0 2006.224.07:38:22.19#ibcon#about to read 6, iclass 22, count 0 2006.224.07:38:22.19#ibcon#read 6, iclass 22, count 0 2006.224.07:38:22.19#ibcon#end of sib2, iclass 22, count 0 2006.224.07:38:22.19#ibcon#*mode == 0, iclass 22, count 0 2006.224.07:38:22.19#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.224.07:38:22.19#ibcon#[28=FRQ=06,752.99\r\n] 2006.224.07:38:22.19#ibcon#*before write, iclass 22, count 0 2006.224.07:38:22.19#ibcon#enter sib2, iclass 22, count 0 2006.224.07:38:22.19#ibcon#flushed, iclass 22, count 0 2006.224.07:38:22.19#ibcon#about to write, iclass 22, count 0 2006.224.07:38:22.19#ibcon#wrote, iclass 22, count 0 2006.224.07:38:22.19#ibcon#about to read 3, iclass 22, count 0 2006.224.07:38:22.24#ibcon#read 3, iclass 22, count 0 2006.224.07:38:22.24#ibcon#about to read 4, iclass 22, count 0 2006.224.07:38:22.24#ibcon#read 4, iclass 22, count 0 2006.224.07:38:22.24#ibcon#about to read 5, iclass 22, count 0 2006.224.07:38:22.24#ibcon#read 5, iclass 22, count 0 2006.224.07:38:22.24#ibcon#about to read 6, iclass 22, count 0 2006.224.07:38:22.24#ibcon#read 6, iclass 22, count 0 2006.224.07:38:22.24#ibcon#end of sib2, iclass 22, count 0 2006.224.07:38:22.24#ibcon#*after write, iclass 22, count 0 2006.224.07:38:22.24#ibcon#*before return 0, iclass 22, count 0 2006.224.07:38:22.24#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.224.07:38:22.24#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.224.07:38:22.24#ibcon#about to clear, iclass 22 cls_cnt 0 2006.224.07:38:22.24#ibcon#cleared, iclass 22 cls_cnt 0 2006.224.07:38:22.24$vc4f8/vb=6,4 2006.224.07:38:22.24#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.224.07:38:22.24#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.224.07:38:22.24#ibcon#ireg 11 cls_cnt 2 2006.224.07:38:22.24#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.224.07:38:22.29#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.224.07:38:22.29#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.224.07:38:22.29#ibcon#enter wrdev, iclass 24, count 2 2006.224.07:38:22.29#ibcon#first serial, iclass 24, count 2 2006.224.07:38:22.29#ibcon#enter sib2, iclass 24, count 2 2006.224.07:38:22.29#ibcon#flushed, iclass 24, count 2 2006.224.07:38:22.29#ibcon#about to write, iclass 24, count 2 2006.224.07:38:22.29#ibcon#wrote, iclass 24, count 2 2006.224.07:38:22.29#ibcon#about to read 3, iclass 24, count 2 2006.224.07:38:22.31#ibcon#read 3, iclass 24, count 2 2006.224.07:38:22.31#ibcon#about to read 4, iclass 24, count 2 2006.224.07:38:22.31#ibcon#read 4, iclass 24, count 2 2006.224.07:38:22.31#ibcon#about to read 5, iclass 24, count 2 2006.224.07:38:22.31#ibcon#read 5, iclass 24, count 2 2006.224.07:38:22.31#ibcon#about to read 6, iclass 24, count 2 2006.224.07:38:22.31#ibcon#read 6, iclass 24, count 2 2006.224.07:38:22.31#ibcon#end of sib2, iclass 24, count 2 2006.224.07:38:22.31#ibcon#*mode == 0, iclass 24, count 2 2006.224.07:38:22.31#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.224.07:38:22.31#ibcon#[27=AT06-04\r\n] 2006.224.07:38:22.31#ibcon#*before write, iclass 24, count 2 2006.224.07:38:22.31#ibcon#enter sib2, iclass 24, count 2 2006.224.07:38:22.31#ibcon#flushed, iclass 24, count 2 2006.224.07:38:22.31#ibcon#about to write, iclass 24, count 2 2006.224.07:38:22.31#ibcon#wrote, iclass 24, count 2 2006.224.07:38:22.31#ibcon#about to read 3, iclass 24, count 2 2006.224.07:38:22.34#ibcon#read 3, iclass 24, count 2 2006.224.07:38:22.34#ibcon#about to read 4, iclass 24, count 2 2006.224.07:38:22.34#ibcon#read 4, iclass 24, count 2 2006.224.07:38:22.34#ibcon#about to read 5, iclass 24, count 2 2006.224.07:38:22.34#ibcon#read 5, iclass 24, count 2 2006.224.07:38:22.34#ibcon#about to read 6, iclass 24, count 2 2006.224.07:38:22.34#ibcon#read 6, iclass 24, count 2 2006.224.07:38:22.34#ibcon#end of sib2, iclass 24, count 2 2006.224.07:38:22.34#ibcon#*after write, iclass 24, count 2 2006.224.07:38:22.34#ibcon#*before return 0, iclass 24, count 2 2006.224.07:38:22.34#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.224.07:38:22.34#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.224.07:38:22.34#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.224.07:38:22.34#ibcon#ireg 7 cls_cnt 0 2006.224.07:38:22.34#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.224.07:38:22.46#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.224.07:38:22.46#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.224.07:38:22.46#ibcon#enter wrdev, iclass 24, count 0 2006.224.07:38:22.46#ibcon#first serial, iclass 24, count 0 2006.224.07:38:22.46#ibcon#enter sib2, iclass 24, count 0 2006.224.07:38:22.46#ibcon#flushed, iclass 24, count 0 2006.224.07:38:22.46#ibcon#about to write, iclass 24, count 0 2006.224.07:38:22.46#ibcon#wrote, iclass 24, count 0 2006.224.07:38:22.46#ibcon#about to read 3, iclass 24, count 0 2006.224.07:38:22.48#ibcon#read 3, iclass 24, count 0 2006.224.07:38:22.48#ibcon#about to read 4, iclass 24, count 0 2006.224.07:38:22.48#ibcon#read 4, iclass 24, count 0 2006.224.07:38:22.48#ibcon#about to read 5, iclass 24, count 0 2006.224.07:38:22.48#ibcon#read 5, iclass 24, count 0 2006.224.07:38:22.48#ibcon#about to read 6, iclass 24, count 0 2006.224.07:38:22.48#ibcon#read 6, iclass 24, count 0 2006.224.07:38:22.48#ibcon#end of sib2, iclass 24, count 0 2006.224.07:38:22.48#ibcon#*mode == 0, iclass 24, count 0 2006.224.07:38:22.48#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.224.07:38:22.48#ibcon#[27=USB\r\n] 2006.224.07:38:22.48#ibcon#*before write, iclass 24, count 0 2006.224.07:38:22.48#ibcon#enter sib2, iclass 24, count 0 2006.224.07:38:22.48#ibcon#flushed, iclass 24, count 0 2006.224.07:38:22.48#ibcon#about to write, iclass 24, count 0 2006.224.07:38:22.48#ibcon#wrote, iclass 24, count 0 2006.224.07:38:22.48#ibcon#about to read 3, iclass 24, count 0 2006.224.07:38:22.51#ibcon#read 3, iclass 24, count 0 2006.224.07:38:22.51#ibcon#about to read 4, iclass 24, count 0 2006.224.07:38:22.51#ibcon#read 4, iclass 24, count 0 2006.224.07:38:22.51#ibcon#about to read 5, iclass 24, count 0 2006.224.07:38:22.51#ibcon#read 5, iclass 24, count 0 2006.224.07:38:22.51#ibcon#about to read 6, iclass 24, count 0 2006.224.07:38:22.51#ibcon#read 6, iclass 24, count 0 2006.224.07:38:22.51#ibcon#end of sib2, iclass 24, count 0 2006.224.07:38:22.51#ibcon#*after write, iclass 24, count 0 2006.224.07:38:22.51#ibcon#*before return 0, iclass 24, count 0 2006.224.07:38:22.51#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.224.07:38:22.51#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.224.07:38:22.51#ibcon#about to clear, iclass 24 cls_cnt 0 2006.224.07:38:22.51#ibcon#cleared, iclass 24 cls_cnt 0 2006.224.07:38:22.51$vc4f8/vabw=wide 2006.224.07:38:22.51#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.224.07:38:22.51#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.224.07:38:22.51#ibcon#ireg 8 cls_cnt 0 2006.224.07:38:22.51#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.224.07:38:22.51#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.224.07:38:22.51#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.224.07:38:22.51#ibcon#enter wrdev, iclass 26, count 0 2006.224.07:38:22.51#ibcon#first serial, iclass 26, count 0 2006.224.07:38:22.51#ibcon#enter sib2, iclass 26, count 0 2006.224.07:38:22.51#ibcon#flushed, iclass 26, count 0 2006.224.07:38:22.51#ibcon#about to write, iclass 26, count 0 2006.224.07:38:22.51#ibcon#wrote, iclass 26, count 0 2006.224.07:38:22.51#ibcon#about to read 3, iclass 26, count 0 2006.224.07:38:22.53#ibcon#read 3, iclass 26, count 0 2006.224.07:38:22.53#ibcon#about to read 4, iclass 26, count 0 2006.224.07:38:22.53#ibcon#read 4, iclass 26, count 0 2006.224.07:38:22.53#ibcon#about to read 5, iclass 26, count 0 2006.224.07:38:22.53#ibcon#read 5, iclass 26, count 0 2006.224.07:38:22.53#ibcon#about to read 6, iclass 26, count 0 2006.224.07:38:22.53#ibcon#read 6, iclass 26, count 0 2006.224.07:38:22.53#ibcon#end of sib2, iclass 26, count 0 2006.224.07:38:22.53#ibcon#*mode == 0, iclass 26, count 0 2006.224.07:38:22.53#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.224.07:38:22.53#ibcon#[25=BW32\r\n] 2006.224.07:38:22.53#ibcon#*before write, iclass 26, count 0 2006.224.07:38:22.53#ibcon#enter sib2, iclass 26, count 0 2006.224.07:38:22.53#ibcon#flushed, iclass 26, count 0 2006.224.07:38:22.53#ibcon#about to write, iclass 26, count 0 2006.224.07:38:22.53#ibcon#wrote, iclass 26, count 0 2006.224.07:38:22.53#ibcon#about to read 3, iclass 26, count 0 2006.224.07:38:22.56#ibcon#read 3, iclass 26, count 0 2006.224.07:38:22.56#ibcon#about to read 4, iclass 26, count 0 2006.224.07:38:22.56#ibcon#read 4, iclass 26, count 0 2006.224.07:38:22.56#ibcon#about to read 5, iclass 26, count 0 2006.224.07:38:22.56#ibcon#read 5, iclass 26, count 0 2006.224.07:38:22.56#ibcon#about to read 6, iclass 26, count 0 2006.224.07:38:22.56#ibcon#read 6, iclass 26, count 0 2006.224.07:38:22.56#ibcon#end of sib2, iclass 26, count 0 2006.224.07:38:22.56#ibcon#*after write, iclass 26, count 0 2006.224.07:38:22.56#ibcon#*before return 0, iclass 26, count 0 2006.224.07:38:22.56#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.224.07:38:22.56#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.224.07:38:22.56#ibcon#about to clear, iclass 26 cls_cnt 0 2006.224.07:38:22.56#ibcon#cleared, iclass 26 cls_cnt 0 2006.224.07:38:22.56$vc4f8/vbbw=wide 2006.224.07:38:22.56#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.224.07:38:22.56#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.224.07:38:22.56#ibcon#ireg 8 cls_cnt 0 2006.224.07:38:22.56#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.224.07:38:22.63#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.224.07:38:22.63#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.224.07:38:22.63#ibcon#enter wrdev, iclass 28, count 0 2006.224.07:38:22.63#ibcon#first serial, iclass 28, count 0 2006.224.07:38:22.63#ibcon#enter sib2, iclass 28, count 0 2006.224.07:38:22.63#ibcon#flushed, iclass 28, count 0 2006.224.07:38:22.63#ibcon#about to write, iclass 28, count 0 2006.224.07:38:22.63#ibcon#wrote, iclass 28, count 0 2006.224.07:38:22.63#ibcon#about to read 3, iclass 28, count 0 2006.224.07:38:22.65#ibcon#read 3, iclass 28, count 0 2006.224.07:38:22.65#ibcon#about to read 4, iclass 28, count 0 2006.224.07:38:22.65#ibcon#read 4, iclass 28, count 0 2006.224.07:38:22.65#ibcon#about to read 5, iclass 28, count 0 2006.224.07:38:22.65#ibcon#read 5, iclass 28, count 0 2006.224.07:38:22.65#ibcon#about to read 6, iclass 28, count 0 2006.224.07:38:22.65#ibcon#read 6, iclass 28, count 0 2006.224.07:38:22.65#ibcon#end of sib2, iclass 28, count 0 2006.224.07:38:22.65#ibcon#*mode == 0, iclass 28, count 0 2006.224.07:38:22.65#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.224.07:38:22.65#ibcon#[27=BW32\r\n] 2006.224.07:38:22.65#ibcon#*before write, iclass 28, count 0 2006.224.07:38:22.65#ibcon#enter sib2, iclass 28, count 0 2006.224.07:38:22.65#ibcon#flushed, iclass 28, count 0 2006.224.07:38:22.65#ibcon#about to write, iclass 28, count 0 2006.224.07:38:22.65#ibcon#wrote, iclass 28, count 0 2006.224.07:38:22.65#ibcon#about to read 3, iclass 28, count 0 2006.224.07:38:22.68#ibcon#read 3, iclass 28, count 0 2006.224.07:38:22.68#ibcon#about to read 4, iclass 28, count 0 2006.224.07:38:22.68#ibcon#read 4, iclass 28, count 0 2006.224.07:38:22.68#ibcon#about to read 5, iclass 28, count 0 2006.224.07:38:22.68#ibcon#read 5, iclass 28, count 0 2006.224.07:38:22.68#ibcon#about to read 6, iclass 28, count 0 2006.224.07:38:22.68#ibcon#read 6, iclass 28, count 0 2006.224.07:38:22.68#ibcon#end of sib2, iclass 28, count 0 2006.224.07:38:22.68#ibcon#*after write, iclass 28, count 0 2006.224.07:38:22.68#ibcon#*before return 0, iclass 28, count 0 2006.224.07:38:22.68#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.224.07:38:22.68#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.224.07:38:22.68#ibcon#about to clear, iclass 28 cls_cnt 0 2006.224.07:38:22.68#ibcon#cleared, iclass 28 cls_cnt 0 2006.224.07:38:22.68$4f8m12a/ifd4f 2006.224.07:38:22.68$ifd4f/lo= 2006.224.07:38:22.68$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.224.07:38:22.68$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.224.07:38:22.68$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.224.07:38:22.68$ifd4f/patch= 2006.224.07:38:22.68$ifd4f/patch=lo1,a1,a2,a3,a4 2006.224.07:38:22.68$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.224.07:38:22.68$ifd4f/patch=lo3,a5,a6,a7,a8 2006.224.07:38:22.68$4f8m12a/"form=m,16.000,1:2 2006.224.07:38:22.68$4f8m12a/"tpicd 2006.224.07:38:22.68$4f8m12a/echo=off 2006.224.07:38:22.68$4f8m12a/xlog=off 2006.224.07:38:22.68:!2006.224.07:39:10 2006.224.07:38:49.14#trakl#Source acquired 2006.224.07:38:50.14#flagr#flagr/antenna,acquired 2006.224.07:39:10.00:preob 2006.224.07:39:10.14/onsource/TRACKING 2006.224.07:39:10.14:!2006.224.07:39:20 2006.224.07:39:20.00:data_valid=on 2006.224.07:39:20.00:midob 2006.224.07:39:20.14/onsource/TRACKING 2006.224.07:39:20.14/wx/23.40,1004.3,100 2006.224.07:39:20.31/cable/+6.4354E-03 2006.224.07:39:21.40/va/01,08,usb,yes,41,43 2006.224.07:39:21.40/va/02,07,usb,yes,41,43 2006.224.07:39:21.40/va/03,06,usb,yes,44,44 2006.224.07:39:21.40/va/04,07,usb,yes,43,46 2006.224.07:39:21.40/va/05,07,usb,yes,50,52 2006.224.07:39:21.40/va/06,06,usb,yes,50,49 2006.224.07:39:21.40/va/07,06,usb,yes,51,50 2006.224.07:39:21.40/va/08,07,usb,yes,48,48 2006.224.07:39:21.63/valo/01,532.99,yes,locked 2006.224.07:39:21.63/valo/02,572.99,yes,locked 2006.224.07:39:21.63/valo/03,672.99,yes,locked 2006.224.07:39:21.63/valo/04,832.99,yes,locked 2006.224.07:39:21.63/valo/05,652.99,yes,locked 2006.224.07:39:21.63/valo/06,772.99,yes,locked 2006.224.07:39:21.63/valo/07,832.99,yes,locked 2006.224.07:39:21.63/valo/08,852.99,yes,locked 2006.224.07:39:22.72/vb/01,04,usb,yes,31,30 2006.224.07:39:22.72/vb/02,04,usb,yes,33,35 2006.224.07:39:22.72/vb/03,04,usb,yes,30,33 2006.224.07:39:22.72/vb/04,04,usb,yes,30,31 2006.224.07:39:22.72/vb/05,04,usb,yes,29,33 2006.224.07:39:22.72/vb/06,04,usb,yes,30,33 2006.224.07:39:22.72/vb/07,04,usb,yes,32,32 2006.224.07:39:22.72/vb/08,04,usb,yes,29,33 2006.224.07:39:22.95/vblo/01,632.99,yes,locked 2006.224.07:39:22.95/vblo/02,640.99,yes,locked 2006.224.07:39:22.95/vblo/03,656.99,yes,locked 2006.224.07:39:22.95/vblo/04,712.99,yes,locked 2006.224.07:39:22.95/vblo/05,744.99,yes,locked 2006.224.07:39:22.95/vblo/06,752.99,yes,locked 2006.224.07:39:22.95/vblo/07,734.99,yes,locked 2006.224.07:39:22.95/vblo/08,744.99,yes,locked 2006.224.07:39:23.10/vabw/8 2006.224.07:39:23.25/vbbw/8 2006.224.07:39:23.34/xfe/off,on,15.2 2006.224.07:39:23.71/ifatt/23,28,28,28 2006.224.07:39:24.07/fmout-gps/S +4.34E-07 2006.224.07:39:24.11:!2006.224.07:40:30 2006.224.07:40:30.02:data_valid=off 2006.224.07:40:30.02:postob 2006.224.07:40:30.22/cable/+6.4344E-03 2006.224.07:40:30.22/wx/23.42,1004.4,100 2006.224.07:40:31.07/fmout-gps/S +4.33E-07 2006.224.07:40:31.07:scan_name=224-0741,k06224,60 2006.224.07:40:31.07:source=1417+385,141946.61,382148.5,2000.0,ccw 2006.224.07:40:32.14#flagr#flagr/antenna,new-source 2006.224.07:40:32.14:checkk5 2006.224.07:40:32.52/chk_autoobs//k5ts1/ autoobs is running! 2006.224.07:40:32.89/chk_autoobs//k5ts2/ autoobs is running! 2006.224.07:40:33.27/chk_autoobs//k5ts3/ autoobs is running! 2006.224.07:40:33.63/chk_autoobs//k5ts4/ autoobs is running! 2006.224.07:40:34.00/chk_obsdata//k5ts1/T2240739??a.dat file size is correct (nominal:560MB, actual:560MB). 2006.224.07:40:34.37/chk_obsdata//k5ts2/T2240739??b.dat file size is correct (nominal:560MB, actual:560MB). 2006.224.07:40:34.73/chk_obsdata//k5ts3/T2240739??c.dat file size is correct (nominal:560MB, actual:560MB). 2006.224.07:40:35.10/chk_obsdata//k5ts4/T2240739??d.dat file size is correct (nominal:560MB, actual:560MB). 2006.224.07:40:35.79/k5log//k5ts1_log_newline 2006.224.07:40:36.48/k5log//k5ts2_log_newline 2006.224.07:40:37.16/k5log//k5ts3_log_newline 2006.224.07:40:37.85/k5log//k5ts4_log_newline 2006.224.07:40:37.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.224.07:40:37.87:4f8m12a=1 2006.224.07:40:37.87$4f8m12a/echo=on 2006.224.07:40:37.87$4f8m12a/pcalon 2006.224.07:40:37.87$pcalon/"no phase cal control is implemented here 2006.224.07:40:37.87$4f8m12a/"tpicd=stop 2006.224.07:40:37.87$4f8m12a/vc4f8 2006.224.07:40:37.87$vc4f8/valo=1,532.99 2006.224.07:40:37.88#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.224.07:40:37.88#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.224.07:40:37.88#ibcon#ireg 17 cls_cnt 0 2006.224.07:40:37.88#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.224.07:40:37.88#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.224.07:40:37.88#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.224.07:40:37.88#ibcon#enter wrdev, iclass 11, count 0 2006.224.07:40:37.88#ibcon#first serial, iclass 11, count 0 2006.224.07:40:37.88#ibcon#enter sib2, iclass 11, count 0 2006.224.07:40:37.88#ibcon#flushed, iclass 11, count 0 2006.224.07:40:37.88#ibcon#about to write, iclass 11, count 0 2006.224.07:40:37.88#ibcon#wrote, iclass 11, count 0 2006.224.07:40:37.88#ibcon#about to read 3, iclass 11, count 0 2006.224.07:40:37.91#ibcon#read 3, iclass 11, count 0 2006.224.07:40:37.91#ibcon#about to read 4, iclass 11, count 0 2006.224.07:40:37.91#ibcon#read 4, iclass 11, count 0 2006.224.07:40:37.91#ibcon#about to read 5, iclass 11, count 0 2006.224.07:40:37.91#ibcon#read 5, iclass 11, count 0 2006.224.07:40:37.91#ibcon#about to read 6, iclass 11, count 0 2006.224.07:40:37.91#ibcon#read 6, iclass 11, count 0 2006.224.07:40:37.91#ibcon#end of sib2, iclass 11, count 0 2006.224.07:40:37.91#ibcon#*mode == 0, iclass 11, count 0 2006.224.07:40:37.91#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.224.07:40:37.91#ibcon#[26=FRQ=01,532.99\r\n] 2006.224.07:40:37.91#ibcon#*before write, iclass 11, count 0 2006.224.07:40:37.91#ibcon#enter sib2, iclass 11, count 0 2006.224.07:40:37.91#ibcon#flushed, iclass 11, count 0 2006.224.07:40:37.91#ibcon#about to write, iclass 11, count 0 2006.224.07:40:37.91#ibcon#wrote, iclass 11, count 0 2006.224.07:40:37.92#ibcon#about to read 3, iclass 11, count 0 2006.224.07:40:37.97#ibcon#read 3, iclass 11, count 0 2006.224.07:40:37.97#ibcon#about to read 4, iclass 11, count 0 2006.224.07:40:37.97#ibcon#read 4, iclass 11, count 0 2006.224.07:40:37.97#ibcon#about to read 5, iclass 11, count 0 2006.224.07:40:37.97#ibcon#read 5, iclass 11, count 0 2006.224.07:40:37.97#ibcon#about to read 6, iclass 11, count 0 2006.224.07:40:37.97#ibcon#read 6, iclass 11, count 0 2006.224.07:40:37.97#ibcon#end of sib2, iclass 11, count 0 2006.224.07:40:37.97#ibcon#*after write, iclass 11, count 0 2006.224.07:40:37.97#ibcon#*before return 0, iclass 11, count 0 2006.224.07:40:37.97#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.224.07:40:37.97#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.224.07:40:37.97#ibcon#about to clear, iclass 11 cls_cnt 0 2006.224.07:40:37.97#ibcon#cleared, iclass 11 cls_cnt 0 2006.224.07:40:37.97$vc4f8/va=1,8 2006.224.07:40:37.97#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.224.07:40:37.97#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.224.07:40:37.97#ibcon#ireg 11 cls_cnt 2 2006.224.07:40:37.97#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.224.07:40:37.97#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.224.07:40:37.97#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.224.07:40:37.97#ibcon#enter wrdev, iclass 13, count 2 2006.224.07:40:37.97#ibcon#first serial, iclass 13, count 2 2006.224.07:40:37.97#ibcon#enter sib2, iclass 13, count 2 2006.224.07:40:37.97#ibcon#flushed, iclass 13, count 2 2006.224.07:40:37.97#ibcon#about to write, iclass 13, count 2 2006.224.07:40:37.97#ibcon#wrote, iclass 13, count 2 2006.224.07:40:37.97#ibcon#about to read 3, iclass 13, count 2 2006.224.07:40:37.99#ibcon#read 3, iclass 13, count 2 2006.224.07:40:37.99#ibcon#about to read 4, iclass 13, count 2 2006.224.07:40:37.99#ibcon#read 4, iclass 13, count 2 2006.224.07:40:37.99#ibcon#about to read 5, iclass 13, count 2 2006.224.07:40:37.99#ibcon#read 5, iclass 13, count 2 2006.224.07:40:37.99#ibcon#about to read 6, iclass 13, count 2 2006.224.07:40:37.99#ibcon#read 6, iclass 13, count 2 2006.224.07:40:37.99#ibcon#end of sib2, iclass 13, count 2 2006.224.07:40:37.99#ibcon#*mode == 0, iclass 13, count 2 2006.224.07:40:37.99#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.224.07:40:37.99#ibcon#[25=AT01-08\r\n] 2006.224.07:40:37.99#ibcon#*before write, iclass 13, count 2 2006.224.07:40:37.99#ibcon#enter sib2, iclass 13, count 2 2006.224.07:40:37.99#ibcon#flushed, iclass 13, count 2 2006.224.07:40:37.99#ibcon#about to write, iclass 13, count 2 2006.224.07:40:37.99#ibcon#wrote, iclass 13, count 2 2006.224.07:40:37.99#ibcon#about to read 3, iclass 13, count 2 2006.224.07:40:38.02#ibcon#read 3, iclass 13, count 2 2006.224.07:40:38.03#ibcon#about to read 4, iclass 13, count 2 2006.224.07:40:38.03#ibcon#read 4, iclass 13, count 2 2006.224.07:40:38.03#ibcon#about to read 5, iclass 13, count 2 2006.224.07:40:38.03#ibcon#read 5, iclass 13, count 2 2006.224.07:40:38.03#ibcon#about to read 6, iclass 13, count 2 2006.224.07:40:38.03#ibcon#read 6, iclass 13, count 2 2006.224.07:40:38.03#ibcon#end of sib2, iclass 13, count 2 2006.224.07:40:38.03#ibcon#*after write, iclass 13, count 2 2006.224.07:40:38.03#ibcon#*before return 0, iclass 13, count 2 2006.224.07:40:38.03#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.224.07:40:38.03#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.224.07:40:38.03#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.224.07:40:38.03#ibcon#ireg 7 cls_cnt 0 2006.224.07:40:38.03#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.224.07:40:38.14#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.224.07:40:38.14#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.224.07:40:38.14#ibcon#enter wrdev, iclass 13, count 0 2006.224.07:40:38.14#ibcon#first serial, iclass 13, count 0 2006.224.07:40:38.14#ibcon#enter sib2, iclass 13, count 0 2006.224.07:40:38.14#ibcon#flushed, iclass 13, count 0 2006.224.07:40:38.14#ibcon#about to write, iclass 13, count 0 2006.224.07:40:38.15#ibcon#wrote, iclass 13, count 0 2006.224.07:40:38.15#ibcon#about to read 3, iclass 13, count 0 2006.224.07:40:38.16#ibcon#read 3, iclass 13, count 0 2006.224.07:40:38.16#ibcon#about to read 4, iclass 13, count 0 2006.224.07:40:38.16#ibcon#read 4, iclass 13, count 0 2006.224.07:40:38.16#ibcon#about to read 5, iclass 13, count 0 2006.224.07:40:38.17#ibcon#read 5, iclass 13, count 0 2006.224.07:40:38.17#ibcon#about to read 6, iclass 13, count 0 2006.224.07:40:38.17#ibcon#read 6, iclass 13, count 0 2006.224.07:40:38.17#ibcon#end of sib2, iclass 13, count 0 2006.224.07:40:38.17#ibcon#*mode == 0, iclass 13, count 0 2006.224.07:40:38.17#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.224.07:40:38.17#ibcon#[25=USB\r\n] 2006.224.07:40:38.17#ibcon#*before write, iclass 13, count 0 2006.224.07:40:38.17#ibcon#enter sib2, iclass 13, count 0 2006.224.07:40:38.17#ibcon#flushed, iclass 13, count 0 2006.224.07:40:38.17#ibcon#about to write, iclass 13, count 0 2006.224.07:40:38.17#ibcon#wrote, iclass 13, count 0 2006.224.07:40:38.17#ibcon#about to read 3, iclass 13, count 0 2006.224.07:40:38.20#ibcon#read 3, iclass 13, count 0 2006.224.07:40:38.20#ibcon#about to read 4, iclass 13, count 0 2006.224.07:40:38.20#ibcon#read 4, iclass 13, count 0 2006.224.07:40:38.20#ibcon#about to read 5, iclass 13, count 0 2006.224.07:40:38.20#ibcon#read 5, iclass 13, count 0 2006.224.07:40:38.20#ibcon#about to read 6, iclass 13, count 0 2006.224.07:40:38.20#ibcon#read 6, iclass 13, count 0 2006.224.07:40:38.20#ibcon#end of sib2, iclass 13, count 0 2006.224.07:40:38.20#ibcon#*after write, iclass 13, count 0 2006.224.07:40:38.20#ibcon#*before return 0, iclass 13, count 0 2006.224.07:40:38.20#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.224.07:40:38.20#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.224.07:40:38.20#ibcon#about to clear, iclass 13 cls_cnt 0 2006.224.07:40:38.20#ibcon#cleared, iclass 13 cls_cnt 0 2006.224.07:40:38.20$vc4f8/valo=2,572.99 2006.224.07:40:38.20#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.224.07:40:38.20#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.224.07:40:38.20#ibcon#ireg 17 cls_cnt 0 2006.224.07:40:38.20#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.224.07:40:38.20#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.224.07:40:38.20#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.224.07:40:38.20#ibcon#enter wrdev, iclass 15, count 0 2006.224.07:40:38.20#ibcon#first serial, iclass 15, count 0 2006.224.07:40:38.20#ibcon#enter sib2, iclass 15, count 0 2006.224.07:40:38.20#ibcon#flushed, iclass 15, count 0 2006.224.07:40:38.20#ibcon#about to write, iclass 15, count 0 2006.224.07:40:38.20#ibcon#wrote, iclass 15, count 0 2006.224.07:40:38.20#ibcon#about to read 3, iclass 15, count 0 2006.224.07:40:38.21#ibcon#read 3, iclass 15, count 0 2006.224.07:40:38.21#ibcon#about to read 4, iclass 15, count 0 2006.224.07:40:38.22#ibcon#read 4, iclass 15, count 0 2006.224.07:40:38.22#ibcon#about to read 5, iclass 15, count 0 2006.224.07:40:38.22#ibcon#read 5, iclass 15, count 0 2006.224.07:40:38.22#ibcon#about to read 6, iclass 15, count 0 2006.224.07:40:38.22#ibcon#read 6, iclass 15, count 0 2006.224.07:40:38.22#ibcon#end of sib2, iclass 15, count 0 2006.224.07:40:38.22#ibcon#*mode == 0, iclass 15, count 0 2006.224.07:40:38.22#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.224.07:40:38.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.224.07:40:38.22#ibcon#*before write, iclass 15, count 0 2006.224.07:40:38.22#ibcon#enter sib2, iclass 15, count 0 2006.224.07:40:38.22#ibcon#flushed, iclass 15, count 0 2006.224.07:40:38.22#ibcon#about to write, iclass 15, count 0 2006.224.07:40:38.22#ibcon#wrote, iclass 15, count 0 2006.224.07:40:38.22#ibcon#about to read 3, iclass 15, count 0 2006.224.07:40:38.25#ibcon#read 3, iclass 15, count 0 2006.224.07:40:38.25#ibcon#about to read 4, iclass 15, count 0 2006.224.07:40:38.25#ibcon#read 4, iclass 15, count 0 2006.224.07:40:38.25#ibcon#about to read 5, iclass 15, count 0 2006.224.07:40:38.26#ibcon#read 5, iclass 15, count 0 2006.224.07:40:38.26#ibcon#about to read 6, iclass 15, count 0 2006.224.07:40:38.26#ibcon#read 6, iclass 15, count 0 2006.224.07:40:38.26#ibcon#end of sib2, iclass 15, count 0 2006.224.07:40:38.26#ibcon#*after write, iclass 15, count 0 2006.224.07:40:38.26#ibcon#*before return 0, iclass 15, count 0 2006.224.07:40:38.26#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.224.07:40:38.26#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.224.07:40:38.26#ibcon#about to clear, iclass 15 cls_cnt 0 2006.224.07:40:38.26#ibcon#cleared, iclass 15 cls_cnt 0 2006.224.07:40:38.26$vc4f8/va=2,7 2006.224.07:40:38.26#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.224.07:40:38.26#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.224.07:40:38.26#ibcon#ireg 11 cls_cnt 2 2006.224.07:40:38.26#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.224.07:40:38.31#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.224.07:40:38.31#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.224.07:40:38.31#ibcon#enter wrdev, iclass 17, count 2 2006.224.07:40:38.31#ibcon#first serial, iclass 17, count 2 2006.224.07:40:38.31#ibcon#enter sib2, iclass 17, count 2 2006.224.07:40:38.32#ibcon#flushed, iclass 17, count 2 2006.224.07:40:38.32#ibcon#about to write, iclass 17, count 2 2006.224.07:40:38.32#ibcon#wrote, iclass 17, count 2 2006.224.07:40:38.32#ibcon#about to read 3, iclass 17, count 2 2006.224.07:40:38.33#ibcon#read 3, iclass 17, count 2 2006.224.07:40:38.33#ibcon#about to read 4, iclass 17, count 2 2006.224.07:40:38.34#ibcon#read 4, iclass 17, count 2 2006.224.07:40:38.34#ibcon#about to read 5, iclass 17, count 2 2006.224.07:40:38.34#ibcon#read 5, iclass 17, count 2 2006.224.07:40:38.34#ibcon#about to read 6, iclass 17, count 2 2006.224.07:40:38.34#ibcon#read 6, iclass 17, count 2 2006.224.07:40:38.34#ibcon#end of sib2, iclass 17, count 2 2006.224.07:40:38.34#ibcon#*mode == 0, iclass 17, count 2 2006.224.07:40:38.34#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.224.07:40:38.34#ibcon#[25=AT02-07\r\n] 2006.224.07:40:38.34#ibcon#*before write, iclass 17, count 2 2006.224.07:40:38.34#ibcon#enter sib2, iclass 17, count 2 2006.224.07:40:38.34#ibcon#flushed, iclass 17, count 2 2006.224.07:40:38.34#ibcon#about to write, iclass 17, count 2 2006.224.07:40:38.34#ibcon#wrote, iclass 17, count 2 2006.224.07:40:38.34#ibcon#about to read 3, iclass 17, count 2 2006.224.07:40:38.36#ibcon#read 3, iclass 17, count 2 2006.224.07:40:38.36#ibcon#about to read 4, iclass 17, count 2 2006.224.07:40:38.36#ibcon#read 4, iclass 17, count 2 2006.224.07:40:38.36#ibcon#about to read 5, iclass 17, count 2 2006.224.07:40:38.37#ibcon#read 5, iclass 17, count 2 2006.224.07:40:38.37#ibcon#about to read 6, iclass 17, count 2 2006.224.07:40:38.37#ibcon#read 6, iclass 17, count 2 2006.224.07:40:38.37#ibcon#end of sib2, iclass 17, count 2 2006.224.07:40:38.37#ibcon#*after write, iclass 17, count 2 2006.224.07:40:38.37#ibcon#*before return 0, iclass 17, count 2 2006.224.07:40:38.37#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.224.07:40:38.37#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.224.07:40:38.37#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.224.07:40:38.37#ibcon#ireg 7 cls_cnt 0 2006.224.07:40:38.37#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.224.07:40:38.49#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.224.07:40:38.49#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.224.07:40:38.49#ibcon#enter wrdev, iclass 17, count 0 2006.224.07:40:38.49#ibcon#first serial, iclass 17, count 0 2006.224.07:40:38.49#ibcon#enter sib2, iclass 17, count 0 2006.224.07:40:38.49#ibcon#flushed, iclass 17, count 0 2006.224.07:40:38.49#ibcon#about to write, iclass 17, count 0 2006.224.07:40:38.49#ibcon#wrote, iclass 17, count 0 2006.224.07:40:38.49#ibcon#about to read 3, iclass 17, count 0 2006.224.07:40:38.50#ibcon#read 3, iclass 17, count 0 2006.224.07:40:38.51#ibcon#about to read 4, iclass 17, count 0 2006.224.07:40:38.51#ibcon#read 4, iclass 17, count 0 2006.224.07:40:38.51#ibcon#about to read 5, iclass 17, count 0 2006.224.07:40:38.51#ibcon#read 5, iclass 17, count 0 2006.224.07:40:38.51#ibcon#about to read 6, iclass 17, count 0 2006.224.07:40:38.51#ibcon#read 6, iclass 17, count 0 2006.224.07:40:38.51#ibcon#end of sib2, iclass 17, count 0 2006.224.07:40:38.51#ibcon#*mode == 0, iclass 17, count 0 2006.224.07:40:38.51#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.224.07:40:38.51#ibcon#[25=USB\r\n] 2006.224.07:40:38.51#ibcon#*before write, iclass 17, count 0 2006.224.07:40:38.51#ibcon#enter sib2, iclass 17, count 0 2006.224.07:40:38.51#ibcon#flushed, iclass 17, count 0 2006.224.07:40:38.51#ibcon#about to write, iclass 17, count 0 2006.224.07:40:38.51#ibcon#wrote, iclass 17, count 0 2006.224.07:40:38.51#ibcon#about to read 3, iclass 17, count 0 2006.224.07:40:38.53#ibcon#read 3, iclass 17, count 0 2006.224.07:40:38.53#ibcon#about to read 4, iclass 17, count 0 2006.224.07:40:38.53#ibcon#read 4, iclass 17, count 0 2006.224.07:40:38.53#ibcon#about to read 5, iclass 17, count 0 2006.224.07:40:38.54#ibcon#read 5, iclass 17, count 0 2006.224.07:40:38.54#ibcon#about to read 6, iclass 17, count 0 2006.224.07:40:38.54#ibcon#read 6, iclass 17, count 0 2006.224.07:40:38.54#ibcon#end of sib2, iclass 17, count 0 2006.224.07:40:38.54#ibcon#*after write, iclass 17, count 0 2006.224.07:40:38.54#ibcon#*before return 0, iclass 17, count 0 2006.224.07:40:38.54#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.224.07:40:38.54#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.224.07:40:38.54#ibcon#about to clear, iclass 17 cls_cnt 0 2006.224.07:40:38.54#ibcon#cleared, iclass 17 cls_cnt 0 2006.224.07:40:38.54$vc4f8/valo=3,672.99 2006.224.07:40:38.54#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.224.07:40:38.54#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.224.07:40:38.54#ibcon#ireg 17 cls_cnt 0 2006.224.07:40:38.54#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.224.07:40:38.54#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.224.07:40:38.54#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.224.07:40:38.54#ibcon#enter wrdev, iclass 19, count 0 2006.224.07:40:38.54#ibcon#first serial, iclass 19, count 0 2006.224.07:40:38.54#ibcon#enter sib2, iclass 19, count 0 2006.224.07:40:38.54#ibcon#flushed, iclass 19, count 0 2006.224.07:40:38.54#ibcon#about to write, iclass 19, count 0 2006.224.07:40:38.54#ibcon#wrote, iclass 19, count 0 2006.224.07:40:38.54#ibcon#about to read 3, iclass 19, count 0 2006.224.07:40:38.55#ibcon#read 3, iclass 19, count 0 2006.224.07:40:38.55#ibcon#about to read 4, iclass 19, count 0 2006.224.07:40:38.55#ibcon#read 4, iclass 19, count 0 2006.224.07:40:38.55#ibcon#about to read 5, iclass 19, count 0 2006.224.07:40:38.56#ibcon#read 5, iclass 19, count 0 2006.224.07:40:38.56#ibcon#about to read 6, iclass 19, count 0 2006.224.07:40:38.56#ibcon#read 6, iclass 19, count 0 2006.224.07:40:38.56#ibcon#end of sib2, iclass 19, count 0 2006.224.07:40:38.56#ibcon#*mode == 0, iclass 19, count 0 2006.224.07:40:38.56#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.224.07:40:38.56#ibcon#[26=FRQ=03,672.99\r\n] 2006.224.07:40:38.56#ibcon#*before write, iclass 19, count 0 2006.224.07:40:38.56#ibcon#enter sib2, iclass 19, count 0 2006.224.07:40:38.56#ibcon#flushed, iclass 19, count 0 2006.224.07:40:38.56#ibcon#about to write, iclass 19, count 0 2006.224.07:40:38.56#ibcon#wrote, iclass 19, count 0 2006.224.07:40:38.56#ibcon#about to read 3, iclass 19, count 0 2006.224.07:40:38.60#ibcon#read 3, iclass 19, count 0 2006.224.07:40:38.60#ibcon#about to read 4, iclass 19, count 0 2006.224.07:40:38.60#ibcon#read 4, iclass 19, count 0 2006.224.07:40:38.60#ibcon#about to read 5, iclass 19, count 0 2006.224.07:40:38.60#ibcon#read 5, iclass 19, count 0 2006.224.07:40:38.60#ibcon#about to read 6, iclass 19, count 0 2006.224.07:40:38.60#ibcon#read 6, iclass 19, count 0 2006.224.07:40:38.60#ibcon#end of sib2, iclass 19, count 0 2006.224.07:40:38.60#ibcon#*after write, iclass 19, count 0 2006.224.07:40:38.60#ibcon#*before return 0, iclass 19, count 0 2006.224.07:40:38.60#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.224.07:40:38.60#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.224.07:40:38.60#ibcon#about to clear, iclass 19 cls_cnt 0 2006.224.07:40:38.60#ibcon#cleared, iclass 19 cls_cnt 0 2006.224.07:40:38.60$vc4f8/va=3,6 2006.224.07:40:38.60#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.224.07:40:38.60#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.224.07:40:38.60#ibcon#ireg 11 cls_cnt 2 2006.224.07:40:38.60#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.224.07:40:38.65#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.224.07:40:38.65#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.224.07:40:38.65#ibcon#enter wrdev, iclass 21, count 2 2006.224.07:40:38.65#ibcon#first serial, iclass 21, count 2 2006.224.07:40:38.65#ibcon#enter sib2, iclass 21, count 2 2006.224.07:40:38.66#ibcon#flushed, iclass 21, count 2 2006.224.07:40:38.66#ibcon#about to write, iclass 21, count 2 2006.224.07:40:38.66#ibcon#wrote, iclass 21, count 2 2006.224.07:40:38.66#ibcon#about to read 3, iclass 21, count 2 2006.224.07:40:38.68#ibcon#read 3, iclass 21, count 2 2006.224.07:40:38.68#ibcon#about to read 4, iclass 21, count 2 2006.224.07:40:38.68#ibcon#read 4, iclass 21, count 2 2006.224.07:40:38.68#ibcon#about to read 5, iclass 21, count 2 2006.224.07:40:38.68#ibcon#read 5, iclass 21, count 2 2006.224.07:40:38.68#ibcon#about to read 6, iclass 21, count 2 2006.224.07:40:38.68#ibcon#read 6, iclass 21, count 2 2006.224.07:40:38.68#ibcon#end of sib2, iclass 21, count 2 2006.224.07:40:38.68#ibcon#*mode == 0, iclass 21, count 2 2006.224.07:40:38.68#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.224.07:40:38.68#ibcon#[25=AT03-06\r\n] 2006.224.07:40:38.68#ibcon#*before write, iclass 21, count 2 2006.224.07:40:38.68#ibcon#enter sib2, iclass 21, count 2 2006.224.07:40:38.68#ibcon#flushed, iclass 21, count 2 2006.224.07:40:38.68#ibcon#about to write, iclass 21, count 2 2006.224.07:40:38.68#ibcon#wrote, iclass 21, count 2 2006.224.07:40:38.68#ibcon#about to read 3, iclass 21, count 2 2006.224.07:40:38.71#ibcon#read 3, iclass 21, count 2 2006.224.07:40:38.72#ibcon#about to read 4, iclass 21, count 2 2006.224.07:40:38.72#ibcon#read 4, iclass 21, count 2 2006.224.07:40:38.72#ibcon#about to read 5, iclass 21, count 2 2006.224.07:40:38.72#ibcon#read 5, iclass 21, count 2 2006.224.07:40:38.72#ibcon#about to read 6, iclass 21, count 2 2006.224.07:40:38.72#ibcon#read 6, iclass 21, count 2 2006.224.07:40:38.72#ibcon#end of sib2, iclass 21, count 2 2006.224.07:40:38.72#ibcon#*after write, iclass 21, count 2 2006.224.07:40:38.72#ibcon#*before return 0, iclass 21, count 2 2006.224.07:40:38.72#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.224.07:40:38.72#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.224.07:40:38.72#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.224.07:40:38.72#ibcon#ireg 7 cls_cnt 0 2006.224.07:40:38.72#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.224.07:40:38.83#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.224.07:40:38.83#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.224.07:40:38.83#ibcon#enter wrdev, iclass 21, count 0 2006.224.07:40:38.83#ibcon#first serial, iclass 21, count 0 2006.224.07:40:38.83#ibcon#enter sib2, iclass 21, count 0 2006.224.07:40:38.84#ibcon#flushed, iclass 21, count 0 2006.224.07:40:38.84#ibcon#about to write, iclass 21, count 0 2006.224.07:40:38.84#ibcon#wrote, iclass 21, count 0 2006.224.07:40:38.84#ibcon#about to read 3, iclass 21, count 0 2006.224.07:40:38.85#ibcon#read 3, iclass 21, count 0 2006.224.07:40:38.85#ibcon#about to read 4, iclass 21, count 0 2006.224.07:40:38.85#ibcon#read 4, iclass 21, count 0 2006.224.07:40:38.85#ibcon#about to read 5, iclass 21, count 0 2006.224.07:40:38.86#ibcon#read 5, iclass 21, count 0 2006.224.07:40:38.86#ibcon#about to read 6, iclass 21, count 0 2006.224.07:40:38.86#ibcon#read 6, iclass 21, count 0 2006.224.07:40:38.86#ibcon#end of sib2, iclass 21, count 0 2006.224.07:40:38.86#ibcon#*mode == 0, iclass 21, count 0 2006.224.07:40:38.86#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.224.07:40:38.86#ibcon#[25=USB\r\n] 2006.224.07:40:38.86#ibcon#*before write, iclass 21, count 0 2006.224.07:40:38.86#ibcon#enter sib2, iclass 21, count 0 2006.224.07:40:38.86#ibcon#flushed, iclass 21, count 0 2006.224.07:40:38.86#ibcon#about to write, iclass 21, count 0 2006.224.07:40:38.86#ibcon#wrote, iclass 21, count 0 2006.224.07:40:38.86#ibcon#about to read 3, iclass 21, count 0 2006.224.07:40:38.88#ibcon#read 3, iclass 21, count 0 2006.224.07:40:38.88#ibcon#about to read 4, iclass 21, count 0 2006.224.07:40:38.88#ibcon#read 4, iclass 21, count 0 2006.224.07:40:38.88#ibcon#about to read 5, iclass 21, count 0 2006.224.07:40:38.89#ibcon#read 5, iclass 21, count 0 2006.224.07:40:38.89#ibcon#about to read 6, iclass 21, count 0 2006.224.07:40:38.89#ibcon#read 6, iclass 21, count 0 2006.224.07:40:38.89#ibcon#end of sib2, iclass 21, count 0 2006.224.07:40:38.89#ibcon#*after write, iclass 21, count 0 2006.224.07:40:38.89#ibcon#*before return 0, iclass 21, count 0 2006.224.07:40:38.89#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.224.07:40:38.89#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.224.07:40:38.89#ibcon#about to clear, iclass 21 cls_cnt 0 2006.224.07:40:38.89#ibcon#cleared, iclass 21 cls_cnt 0 2006.224.07:40:38.89$vc4f8/valo=4,832.99 2006.224.07:40:38.89#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.224.07:40:38.89#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.224.07:40:38.89#ibcon#ireg 17 cls_cnt 0 2006.224.07:40:38.89#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.224.07:40:38.89#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.224.07:40:38.89#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.224.07:40:38.89#ibcon#enter wrdev, iclass 23, count 0 2006.224.07:40:38.89#ibcon#first serial, iclass 23, count 0 2006.224.07:40:38.89#ibcon#enter sib2, iclass 23, count 0 2006.224.07:40:38.89#ibcon#flushed, iclass 23, count 0 2006.224.07:40:38.89#ibcon#about to write, iclass 23, count 0 2006.224.07:40:38.89#ibcon#wrote, iclass 23, count 0 2006.224.07:40:38.89#ibcon#about to read 3, iclass 23, count 0 2006.224.07:40:38.91#ibcon#read 3, iclass 23, count 0 2006.224.07:40:38.91#ibcon#about to read 4, iclass 23, count 0 2006.224.07:40:38.91#ibcon#read 4, iclass 23, count 0 2006.224.07:40:38.91#ibcon#about to read 5, iclass 23, count 0 2006.224.07:40:38.91#ibcon#read 5, iclass 23, count 0 2006.224.07:40:38.91#ibcon#about to read 6, iclass 23, count 0 2006.224.07:40:38.91#ibcon#read 6, iclass 23, count 0 2006.224.07:40:38.91#ibcon#end of sib2, iclass 23, count 0 2006.224.07:40:38.91#ibcon#*mode == 0, iclass 23, count 0 2006.224.07:40:38.91#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.224.07:40:38.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.224.07:40:38.91#ibcon#*before write, iclass 23, count 0 2006.224.07:40:38.91#ibcon#enter sib2, iclass 23, count 0 2006.224.07:40:38.91#ibcon#flushed, iclass 23, count 0 2006.224.07:40:38.91#ibcon#about to write, iclass 23, count 0 2006.224.07:40:38.91#ibcon#wrote, iclass 23, count 0 2006.224.07:40:38.91#ibcon#about to read 3, iclass 23, count 0 2006.224.07:40:38.95#ibcon#read 3, iclass 23, count 0 2006.224.07:40:38.95#ibcon#about to read 4, iclass 23, count 0 2006.224.07:40:38.96#ibcon#read 4, iclass 23, count 0 2006.224.07:40:38.96#ibcon#about to read 5, iclass 23, count 0 2006.224.07:40:38.96#ibcon#read 5, iclass 23, count 0 2006.224.07:40:38.96#ibcon#about to read 6, iclass 23, count 0 2006.224.07:40:38.96#ibcon#read 6, iclass 23, count 0 2006.224.07:40:38.96#ibcon#end of sib2, iclass 23, count 0 2006.224.07:40:38.96#ibcon#*after write, iclass 23, count 0 2006.224.07:40:38.96#ibcon#*before return 0, iclass 23, count 0 2006.224.07:40:38.96#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.224.07:40:38.96#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.224.07:40:38.96#ibcon#about to clear, iclass 23 cls_cnt 0 2006.224.07:40:38.96#ibcon#cleared, iclass 23 cls_cnt 0 2006.224.07:40:38.96$vc4f8/va=4,7 2006.224.07:40:38.96#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.224.07:40:38.96#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.224.07:40:38.96#ibcon#ireg 11 cls_cnt 2 2006.224.07:40:38.96#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.224.07:40:39.01#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.224.07:40:39.01#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.224.07:40:39.01#ibcon#enter wrdev, iclass 25, count 2 2006.224.07:40:39.01#ibcon#first serial, iclass 25, count 2 2006.224.07:40:39.01#ibcon#enter sib2, iclass 25, count 2 2006.224.07:40:39.01#ibcon#flushed, iclass 25, count 2 2006.224.07:40:39.01#ibcon#about to write, iclass 25, count 2 2006.224.07:40:39.01#ibcon#wrote, iclass 25, count 2 2006.224.07:40:39.01#ibcon#about to read 3, iclass 25, count 2 2006.224.07:40:39.02#ibcon#read 3, iclass 25, count 2 2006.224.07:40:39.02#ibcon#about to read 4, iclass 25, count 2 2006.224.07:40:39.02#ibcon#read 4, iclass 25, count 2 2006.224.07:40:39.02#ibcon#about to read 5, iclass 25, count 2 2006.224.07:40:39.03#ibcon#read 5, iclass 25, count 2 2006.224.07:40:39.03#ibcon#about to read 6, iclass 25, count 2 2006.224.07:40:39.03#ibcon#read 6, iclass 25, count 2 2006.224.07:40:39.03#ibcon#end of sib2, iclass 25, count 2 2006.224.07:40:39.03#ibcon#*mode == 0, iclass 25, count 2 2006.224.07:40:39.03#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.224.07:40:39.03#ibcon#[25=AT04-07\r\n] 2006.224.07:40:39.03#ibcon#*before write, iclass 25, count 2 2006.224.07:40:39.03#ibcon#enter sib2, iclass 25, count 2 2006.224.07:40:39.03#ibcon#flushed, iclass 25, count 2 2006.224.07:40:39.03#ibcon#about to write, iclass 25, count 2 2006.224.07:40:39.03#ibcon#wrote, iclass 25, count 2 2006.224.07:40:39.03#ibcon#about to read 3, iclass 25, count 2 2006.224.07:40:39.05#ibcon#read 3, iclass 25, count 2 2006.224.07:40:39.05#ibcon#about to read 4, iclass 25, count 2 2006.224.07:40:39.06#ibcon#read 4, iclass 25, count 2 2006.224.07:40:39.06#ibcon#about to read 5, iclass 25, count 2 2006.224.07:40:39.06#ibcon#read 5, iclass 25, count 2 2006.224.07:40:39.06#ibcon#about to read 6, iclass 25, count 2 2006.224.07:40:39.06#ibcon#read 6, iclass 25, count 2 2006.224.07:40:39.06#ibcon#end of sib2, iclass 25, count 2 2006.224.07:40:39.06#ibcon#*after write, iclass 25, count 2 2006.224.07:40:39.06#ibcon#*before return 0, iclass 25, count 2 2006.224.07:40:39.06#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.224.07:40:39.06#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.224.07:40:39.06#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.224.07:40:39.06#ibcon#ireg 7 cls_cnt 0 2006.224.07:40:39.06#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.224.07:40:39.17#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.224.07:40:39.17#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.224.07:40:39.17#ibcon#enter wrdev, iclass 25, count 0 2006.224.07:40:39.17#ibcon#first serial, iclass 25, count 0 2006.224.07:40:39.17#ibcon#enter sib2, iclass 25, count 0 2006.224.07:40:39.17#ibcon#flushed, iclass 25, count 0 2006.224.07:40:39.17#ibcon#about to write, iclass 25, count 0 2006.224.07:40:39.18#ibcon#wrote, iclass 25, count 0 2006.224.07:40:39.18#ibcon#about to read 3, iclass 25, count 0 2006.224.07:40:39.19#ibcon#read 3, iclass 25, count 0 2006.224.07:40:39.19#ibcon#about to read 4, iclass 25, count 0 2006.224.07:40:39.19#ibcon#read 4, iclass 25, count 0 2006.224.07:40:39.19#ibcon#about to read 5, iclass 25, count 0 2006.224.07:40:39.19#ibcon#read 5, iclass 25, count 0 2006.224.07:40:39.20#ibcon#about to read 6, iclass 25, count 0 2006.224.07:40:39.20#ibcon#read 6, iclass 25, count 0 2006.224.07:40:39.20#ibcon#end of sib2, iclass 25, count 0 2006.224.07:40:39.20#ibcon#*mode == 0, iclass 25, count 0 2006.224.07:40:39.20#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.224.07:40:39.20#ibcon#[25=USB\r\n] 2006.224.07:40:39.20#ibcon#*before write, iclass 25, count 0 2006.224.07:40:39.20#ibcon#enter sib2, iclass 25, count 0 2006.224.07:40:39.20#ibcon#flushed, iclass 25, count 0 2006.224.07:40:39.20#ibcon#about to write, iclass 25, count 0 2006.224.07:40:39.20#ibcon#wrote, iclass 25, count 0 2006.224.07:40:39.20#ibcon#about to read 3, iclass 25, count 0 2006.224.07:40:39.22#ibcon#read 3, iclass 25, count 0 2006.224.07:40:39.23#ibcon#about to read 4, iclass 25, count 0 2006.224.07:40:39.23#ibcon#read 4, iclass 25, count 0 2006.224.07:40:39.23#ibcon#about to read 5, iclass 25, count 0 2006.224.07:40:39.23#ibcon#read 5, iclass 25, count 0 2006.224.07:40:39.23#ibcon#about to read 6, iclass 25, count 0 2006.224.07:40:39.23#ibcon#read 6, iclass 25, count 0 2006.224.07:40:39.23#ibcon#end of sib2, iclass 25, count 0 2006.224.07:40:39.23#ibcon#*after write, iclass 25, count 0 2006.224.07:40:39.23#ibcon#*before return 0, iclass 25, count 0 2006.224.07:40:39.23#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.224.07:40:39.23#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.224.07:40:39.23#ibcon#about to clear, iclass 25 cls_cnt 0 2006.224.07:40:39.23#ibcon#cleared, iclass 25 cls_cnt 0 2006.224.07:40:39.23$vc4f8/valo=5,652.99 2006.224.07:40:39.23#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.224.07:40:39.23#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.224.07:40:39.23#ibcon#ireg 17 cls_cnt 0 2006.224.07:40:39.23#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.224.07:40:39.23#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.224.07:40:39.23#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.224.07:40:39.23#ibcon#enter wrdev, iclass 27, count 0 2006.224.07:40:39.23#ibcon#first serial, iclass 27, count 0 2006.224.07:40:39.23#ibcon#enter sib2, iclass 27, count 0 2006.224.07:40:39.23#ibcon#flushed, iclass 27, count 0 2006.224.07:40:39.23#ibcon#about to write, iclass 27, count 0 2006.224.07:40:39.23#ibcon#wrote, iclass 27, count 0 2006.224.07:40:39.23#ibcon#about to read 3, iclass 27, count 0 2006.224.07:40:39.24#ibcon#read 3, iclass 27, count 0 2006.224.07:40:39.24#ibcon#about to read 4, iclass 27, count 0 2006.224.07:40:39.24#ibcon#read 4, iclass 27, count 0 2006.224.07:40:39.24#ibcon#about to read 5, iclass 27, count 0 2006.224.07:40:39.25#ibcon#read 5, iclass 27, count 0 2006.224.07:40:39.25#ibcon#about to read 6, iclass 27, count 0 2006.224.07:40:39.25#ibcon#read 6, iclass 27, count 0 2006.224.07:40:39.25#ibcon#end of sib2, iclass 27, count 0 2006.224.07:40:39.25#ibcon#*mode == 0, iclass 27, count 0 2006.224.07:40:39.25#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.224.07:40:39.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.224.07:40:39.25#ibcon#*before write, iclass 27, count 0 2006.224.07:40:39.25#ibcon#enter sib2, iclass 27, count 0 2006.224.07:40:39.25#ibcon#flushed, iclass 27, count 0 2006.224.07:40:39.25#ibcon#about to write, iclass 27, count 0 2006.224.07:40:39.25#ibcon#wrote, iclass 27, count 0 2006.224.07:40:39.25#ibcon#about to read 3, iclass 27, count 0 2006.224.07:40:39.28#ibcon#read 3, iclass 27, count 0 2006.224.07:40:39.28#ibcon#about to read 4, iclass 27, count 0 2006.224.07:40:39.29#ibcon#read 4, iclass 27, count 0 2006.224.07:40:39.29#ibcon#about to read 5, iclass 27, count 0 2006.224.07:40:39.29#ibcon#read 5, iclass 27, count 0 2006.224.07:40:39.29#ibcon#about to read 6, iclass 27, count 0 2006.224.07:40:39.29#ibcon#read 6, iclass 27, count 0 2006.224.07:40:39.29#ibcon#end of sib2, iclass 27, count 0 2006.224.07:40:39.29#ibcon#*after write, iclass 27, count 0 2006.224.07:40:39.29#ibcon#*before return 0, iclass 27, count 0 2006.224.07:40:39.29#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.224.07:40:39.29#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.224.07:40:39.29#ibcon#about to clear, iclass 27 cls_cnt 0 2006.224.07:40:39.29#ibcon#cleared, iclass 27 cls_cnt 0 2006.224.07:40:39.29$vc4f8/va=5,7 2006.224.07:40:39.29#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.224.07:40:39.29#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.224.07:40:39.29#ibcon#ireg 11 cls_cnt 2 2006.224.07:40:39.29#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.224.07:40:39.34#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.224.07:40:39.34#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.224.07:40:39.34#ibcon#enter wrdev, iclass 29, count 2 2006.224.07:40:39.34#ibcon#first serial, iclass 29, count 2 2006.224.07:40:39.34#ibcon#enter sib2, iclass 29, count 2 2006.224.07:40:39.35#ibcon#flushed, iclass 29, count 2 2006.224.07:40:39.35#ibcon#about to write, iclass 29, count 2 2006.224.07:40:39.35#ibcon#wrote, iclass 29, count 2 2006.224.07:40:39.35#ibcon#about to read 3, iclass 29, count 2 2006.224.07:40:39.36#ibcon#read 3, iclass 29, count 2 2006.224.07:40:39.36#ibcon#about to read 4, iclass 29, count 2 2006.224.07:40:39.36#ibcon#read 4, iclass 29, count 2 2006.224.07:40:39.37#ibcon#about to read 5, iclass 29, count 2 2006.224.07:40:39.37#ibcon#read 5, iclass 29, count 2 2006.224.07:40:39.37#ibcon#about to read 6, iclass 29, count 2 2006.224.07:40:39.37#ibcon#read 6, iclass 29, count 2 2006.224.07:40:39.37#ibcon#end of sib2, iclass 29, count 2 2006.224.07:40:39.37#ibcon#*mode == 0, iclass 29, count 2 2006.224.07:40:39.37#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.224.07:40:39.37#ibcon#[25=AT05-07\r\n] 2006.224.07:40:39.37#ibcon#*before write, iclass 29, count 2 2006.224.07:40:39.37#ibcon#enter sib2, iclass 29, count 2 2006.224.07:40:39.37#ibcon#flushed, iclass 29, count 2 2006.224.07:40:39.37#ibcon#about to write, iclass 29, count 2 2006.224.07:40:39.37#ibcon#wrote, iclass 29, count 2 2006.224.07:40:39.37#ibcon#about to read 3, iclass 29, count 2 2006.224.07:40:39.39#ibcon#read 3, iclass 29, count 2 2006.224.07:40:39.39#ibcon#about to read 4, iclass 29, count 2 2006.224.07:40:39.39#ibcon#read 4, iclass 29, count 2 2006.224.07:40:39.39#ibcon#about to read 5, iclass 29, count 2 2006.224.07:40:39.40#ibcon#read 5, iclass 29, count 2 2006.224.07:40:39.40#ibcon#about to read 6, iclass 29, count 2 2006.224.07:40:39.40#ibcon#read 6, iclass 29, count 2 2006.224.07:40:39.40#ibcon#end of sib2, iclass 29, count 2 2006.224.07:40:39.40#ibcon#*after write, iclass 29, count 2 2006.224.07:40:39.40#ibcon#*before return 0, iclass 29, count 2 2006.224.07:40:39.40#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.224.07:40:39.40#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.224.07:40:39.40#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.224.07:40:39.40#ibcon#ireg 7 cls_cnt 0 2006.224.07:40:39.40#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.224.07:40:39.51#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.224.07:40:39.51#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.224.07:40:39.51#ibcon#enter wrdev, iclass 29, count 0 2006.224.07:40:39.51#ibcon#first serial, iclass 29, count 0 2006.224.07:40:39.51#ibcon#enter sib2, iclass 29, count 0 2006.224.07:40:39.51#ibcon#flushed, iclass 29, count 0 2006.224.07:40:39.52#ibcon#about to write, iclass 29, count 0 2006.224.07:40:39.52#ibcon#wrote, iclass 29, count 0 2006.224.07:40:39.52#ibcon#about to read 3, iclass 29, count 0 2006.224.07:40:39.53#ibcon#read 3, iclass 29, count 0 2006.224.07:40:39.53#ibcon#about to read 4, iclass 29, count 0 2006.224.07:40:39.53#ibcon#read 4, iclass 29, count 0 2006.224.07:40:39.53#ibcon#about to read 5, iclass 29, count 0 2006.224.07:40:39.54#ibcon#read 5, iclass 29, count 0 2006.224.07:40:39.54#ibcon#about to read 6, iclass 29, count 0 2006.224.07:40:39.54#ibcon#read 6, iclass 29, count 0 2006.224.07:40:39.54#ibcon#end of sib2, iclass 29, count 0 2006.224.07:40:39.54#ibcon#*mode == 0, iclass 29, count 0 2006.224.07:40:39.54#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.224.07:40:39.54#ibcon#[25=USB\r\n] 2006.224.07:40:39.54#ibcon#*before write, iclass 29, count 0 2006.224.07:40:39.54#ibcon#enter sib2, iclass 29, count 0 2006.224.07:40:39.54#ibcon#flushed, iclass 29, count 0 2006.224.07:40:39.54#ibcon#about to write, iclass 29, count 0 2006.224.07:40:39.54#ibcon#wrote, iclass 29, count 0 2006.224.07:40:39.54#ibcon#about to read 3, iclass 29, count 0 2006.224.07:40:39.56#ibcon#read 3, iclass 29, count 0 2006.224.07:40:39.56#ibcon#about to read 4, iclass 29, count 0 2006.224.07:40:39.56#ibcon#read 4, iclass 29, count 0 2006.224.07:40:39.56#ibcon#about to read 5, iclass 29, count 0 2006.224.07:40:39.57#ibcon#read 5, iclass 29, count 0 2006.224.07:40:39.57#ibcon#about to read 6, iclass 29, count 0 2006.224.07:40:39.57#ibcon#read 6, iclass 29, count 0 2006.224.07:40:39.57#ibcon#end of sib2, iclass 29, count 0 2006.224.07:40:39.57#ibcon#*after write, iclass 29, count 0 2006.224.07:40:39.57#ibcon#*before return 0, iclass 29, count 0 2006.224.07:40:39.57#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.224.07:40:39.57#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.224.07:40:39.57#ibcon#about to clear, iclass 29 cls_cnt 0 2006.224.07:40:39.57#ibcon#cleared, iclass 29 cls_cnt 0 2006.224.07:40:39.57$vc4f8/valo=6,772.99 2006.224.07:40:39.57#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.224.07:40:39.57#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.224.07:40:39.57#ibcon#ireg 17 cls_cnt 0 2006.224.07:40:39.57#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.224.07:40:39.57#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.224.07:40:39.57#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.224.07:40:39.57#ibcon#enter wrdev, iclass 31, count 0 2006.224.07:40:39.57#ibcon#first serial, iclass 31, count 0 2006.224.07:40:39.57#ibcon#enter sib2, iclass 31, count 0 2006.224.07:40:39.57#ibcon#flushed, iclass 31, count 0 2006.224.07:40:39.57#ibcon#about to write, iclass 31, count 0 2006.224.07:40:39.57#ibcon#wrote, iclass 31, count 0 2006.224.07:40:39.57#ibcon#about to read 3, iclass 31, count 0 2006.224.07:40:39.58#ibcon#read 3, iclass 31, count 0 2006.224.07:40:39.58#ibcon#about to read 4, iclass 31, count 0 2006.224.07:40:39.58#ibcon#read 4, iclass 31, count 0 2006.224.07:40:39.58#ibcon#about to read 5, iclass 31, count 0 2006.224.07:40:39.59#ibcon#read 5, iclass 31, count 0 2006.224.07:40:39.59#ibcon#about to read 6, iclass 31, count 0 2006.224.07:40:39.59#ibcon#read 6, iclass 31, count 0 2006.224.07:40:39.59#ibcon#end of sib2, iclass 31, count 0 2006.224.07:40:39.59#ibcon#*mode == 0, iclass 31, count 0 2006.224.07:40:39.59#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.224.07:40:39.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.224.07:40:39.59#ibcon#*before write, iclass 31, count 0 2006.224.07:40:39.59#ibcon#enter sib2, iclass 31, count 0 2006.224.07:40:39.59#ibcon#flushed, iclass 31, count 0 2006.224.07:40:39.59#ibcon#about to write, iclass 31, count 0 2006.224.07:40:39.59#ibcon#wrote, iclass 31, count 0 2006.224.07:40:39.59#ibcon#about to read 3, iclass 31, count 0 2006.224.07:40:39.62#ibcon#read 3, iclass 31, count 0 2006.224.07:40:39.62#ibcon#about to read 4, iclass 31, count 0 2006.224.07:40:39.62#ibcon#read 4, iclass 31, count 0 2006.224.07:40:39.62#ibcon#about to read 5, iclass 31, count 0 2006.224.07:40:39.63#ibcon#read 5, iclass 31, count 0 2006.224.07:40:39.63#ibcon#about to read 6, iclass 31, count 0 2006.224.07:40:39.63#ibcon#read 6, iclass 31, count 0 2006.224.07:40:39.63#ibcon#end of sib2, iclass 31, count 0 2006.224.07:40:39.63#ibcon#*after write, iclass 31, count 0 2006.224.07:40:39.63#ibcon#*before return 0, iclass 31, count 0 2006.224.07:40:39.63#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.224.07:40:39.63#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.224.07:40:39.63#ibcon#about to clear, iclass 31 cls_cnt 0 2006.224.07:40:39.63#ibcon#cleared, iclass 31 cls_cnt 0 2006.224.07:40:39.63$vc4f8/va=6,6 2006.224.07:40:39.63#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.224.07:40:39.63#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.224.07:40:39.63#ibcon#ireg 11 cls_cnt 2 2006.224.07:40:39.63#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.224.07:40:39.69#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.224.07:40:39.69#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.224.07:40:39.69#ibcon#enter wrdev, iclass 33, count 2 2006.224.07:40:39.69#ibcon#first serial, iclass 33, count 2 2006.224.07:40:39.69#ibcon#enter sib2, iclass 33, count 2 2006.224.07:40:39.69#ibcon#flushed, iclass 33, count 2 2006.224.07:40:39.69#ibcon#about to write, iclass 33, count 2 2006.224.07:40:39.69#ibcon#wrote, iclass 33, count 2 2006.224.07:40:39.69#ibcon#about to read 3, iclass 33, count 2 2006.224.07:40:39.70#ibcon#read 3, iclass 33, count 2 2006.224.07:40:39.70#ibcon#about to read 4, iclass 33, count 2 2006.224.07:40:39.70#ibcon#read 4, iclass 33, count 2 2006.224.07:40:39.70#ibcon#about to read 5, iclass 33, count 2 2006.224.07:40:39.71#ibcon#read 5, iclass 33, count 2 2006.224.07:40:39.71#ibcon#about to read 6, iclass 33, count 2 2006.224.07:40:39.71#ibcon#read 6, iclass 33, count 2 2006.224.07:40:39.71#ibcon#end of sib2, iclass 33, count 2 2006.224.07:40:39.71#ibcon#*mode == 0, iclass 33, count 2 2006.224.07:40:39.71#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.224.07:40:39.71#ibcon#[25=AT06-06\r\n] 2006.224.07:40:39.71#ibcon#*before write, iclass 33, count 2 2006.224.07:40:39.71#ibcon#enter sib2, iclass 33, count 2 2006.224.07:40:39.71#ibcon#flushed, iclass 33, count 2 2006.224.07:40:39.71#ibcon#about to write, iclass 33, count 2 2006.224.07:40:39.71#ibcon#wrote, iclass 33, count 2 2006.224.07:40:39.71#ibcon#about to read 3, iclass 33, count 2 2006.224.07:40:39.73#ibcon#read 3, iclass 33, count 2 2006.224.07:40:39.73#ibcon#about to read 4, iclass 33, count 2 2006.224.07:40:39.74#ibcon#read 4, iclass 33, count 2 2006.224.07:40:39.74#ibcon#about to read 5, iclass 33, count 2 2006.224.07:40:39.74#ibcon#read 5, iclass 33, count 2 2006.224.07:40:39.74#ibcon#about to read 6, iclass 33, count 2 2006.224.07:40:39.74#ibcon#read 6, iclass 33, count 2 2006.224.07:40:39.74#ibcon#end of sib2, iclass 33, count 2 2006.224.07:40:39.74#ibcon#*after write, iclass 33, count 2 2006.224.07:40:39.74#ibcon#*before return 0, iclass 33, count 2 2006.224.07:40:39.74#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.224.07:40:39.74#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.224.07:40:39.74#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.224.07:40:39.74#ibcon#ireg 7 cls_cnt 0 2006.224.07:40:39.74#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.224.07:40:39.85#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.224.07:40:39.85#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.224.07:40:39.85#ibcon#enter wrdev, iclass 33, count 0 2006.224.07:40:39.85#ibcon#first serial, iclass 33, count 0 2006.224.07:40:39.85#ibcon#enter sib2, iclass 33, count 0 2006.224.07:40:39.86#ibcon#flushed, iclass 33, count 0 2006.224.07:40:39.86#ibcon#about to write, iclass 33, count 0 2006.224.07:40:39.86#ibcon#wrote, iclass 33, count 0 2006.224.07:40:39.86#ibcon#about to read 3, iclass 33, count 0 2006.224.07:40:39.87#ibcon#read 3, iclass 33, count 0 2006.224.07:40:39.87#ibcon#about to read 4, iclass 33, count 0 2006.224.07:40:39.87#ibcon#read 4, iclass 33, count 0 2006.224.07:40:39.87#ibcon#about to read 5, iclass 33, count 0 2006.224.07:40:39.88#ibcon#read 5, iclass 33, count 0 2006.224.07:40:39.88#ibcon#about to read 6, iclass 33, count 0 2006.224.07:40:39.88#ibcon#read 6, iclass 33, count 0 2006.224.07:40:39.88#ibcon#end of sib2, iclass 33, count 0 2006.224.07:40:39.88#ibcon#*mode == 0, iclass 33, count 0 2006.224.07:40:39.88#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.224.07:40:39.88#ibcon#[25=USB\r\n] 2006.224.07:40:39.88#ibcon#*before write, iclass 33, count 0 2006.224.07:40:39.88#ibcon#enter sib2, iclass 33, count 0 2006.224.07:40:39.88#ibcon#flushed, iclass 33, count 0 2006.224.07:40:39.88#ibcon#about to write, iclass 33, count 0 2006.224.07:40:39.88#ibcon#wrote, iclass 33, count 0 2006.224.07:40:39.88#ibcon#about to read 3, iclass 33, count 0 2006.224.07:40:39.90#ibcon#read 3, iclass 33, count 0 2006.224.07:40:39.90#ibcon#about to read 4, iclass 33, count 0 2006.224.07:40:39.90#ibcon#read 4, iclass 33, count 0 2006.224.07:40:39.90#ibcon#about to read 5, iclass 33, count 0 2006.224.07:40:39.91#ibcon#read 5, iclass 33, count 0 2006.224.07:40:39.91#ibcon#about to read 6, iclass 33, count 0 2006.224.07:40:39.91#ibcon#read 6, iclass 33, count 0 2006.224.07:40:39.91#ibcon#end of sib2, iclass 33, count 0 2006.224.07:40:39.91#ibcon#*after write, iclass 33, count 0 2006.224.07:40:39.91#ibcon#*before return 0, iclass 33, count 0 2006.224.07:40:39.91#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.224.07:40:39.91#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.224.07:40:39.91#ibcon#about to clear, iclass 33 cls_cnt 0 2006.224.07:40:39.91#ibcon#cleared, iclass 33 cls_cnt 0 2006.224.07:40:39.91$vc4f8/valo=7,832.99 2006.224.07:40:39.91#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.224.07:40:39.91#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.224.07:40:39.91#ibcon#ireg 17 cls_cnt 0 2006.224.07:40:39.91#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.224.07:40:39.91#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.224.07:40:39.91#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.224.07:40:39.91#ibcon#enter wrdev, iclass 35, count 0 2006.224.07:40:39.91#ibcon#first serial, iclass 35, count 0 2006.224.07:40:39.91#ibcon#enter sib2, iclass 35, count 0 2006.224.07:40:39.91#ibcon#flushed, iclass 35, count 0 2006.224.07:40:39.91#ibcon#about to write, iclass 35, count 0 2006.224.07:40:39.91#ibcon#wrote, iclass 35, count 0 2006.224.07:40:39.91#ibcon#about to read 3, iclass 35, count 0 2006.224.07:40:39.92#ibcon#read 3, iclass 35, count 0 2006.224.07:40:39.92#ibcon#about to read 4, iclass 35, count 0 2006.224.07:40:39.92#ibcon#read 4, iclass 35, count 0 2006.224.07:40:39.92#ibcon#about to read 5, iclass 35, count 0 2006.224.07:40:39.93#ibcon#read 5, iclass 35, count 0 2006.224.07:40:39.93#ibcon#about to read 6, iclass 35, count 0 2006.224.07:40:39.93#ibcon#read 6, iclass 35, count 0 2006.224.07:40:39.93#ibcon#end of sib2, iclass 35, count 0 2006.224.07:40:39.93#ibcon#*mode == 0, iclass 35, count 0 2006.224.07:40:39.93#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.224.07:40:39.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.224.07:40:39.93#ibcon#*before write, iclass 35, count 0 2006.224.07:40:39.93#ibcon#enter sib2, iclass 35, count 0 2006.224.07:40:39.93#ibcon#flushed, iclass 35, count 0 2006.224.07:40:39.93#ibcon#about to write, iclass 35, count 0 2006.224.07:40:39.93#ibcon#wrote, iclass 35, count 0 2006.224.07:40:39.93#ibcon#about to read 3, iclass 35, count 0 2006.224.07:40:39.96#ibcon#read 3, iclass 35, count 0 2006.224.07:40:39.96#ibcon#about to read 4, iclass 35, count 0 2006.224.07:40:39.96#ibcon#read 4, iclass 35, count 0 2006.224.07:40:39.96#ibcon#about to read 5, iclass 35, count 0 2006.224.07:40:39.97#ibcon#read 5, iclass 35, count 0 2006.224.07:40:39.97#ibcon#about to read 6, iclass 35, count 0 2006.224.07:40:39.97#ibcon#read 6, iclass 35, count 0 2006.224.07:40:39.97#ibcon#end of sib2, iclass 35, count 0 2006.224.07:40:39.97#ibcon#*after write, iclass 35, count 0 2006.224.07:40:39.97#ibcon#*before return 0, iclass 35, count 0 2006.224.07:40:39.97#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.224.07:40:39.97#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.224.07:40:39.97#ibcon#about to clear, iclass 35 cls_cnt 0 2006.224.07:40:39.97#ibcon#cleared, iclass 35 cls_cnt 0 2006.224.07:40:39.97$vc4f8/va=7,6 2006.224.07:40:39.97#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.224.07:40:39.97#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.224.07:40:39.97#ibcon#ireg 11 cls_cnt 2 2006.224.07:40:39.97#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.224.07:40:40.02#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.224.07:40:40.02#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.224.07:40:40.02#ibcon#enter wrdev, iclass 37, count 2 2006.224.07:40:40.02#ibcon#first serial, iclass 37, count 2 2006.224.07:40:40.02#ibcon#enter sib2, iclass 37, count 2 2006.224.07:40:40.03#ibcon#flushed, iclass 37, count 2 2006.224.07:40:40.03#ibcon#about to write, iclass 37, count 2 2006.224.07:40:40.03#ibcon#wrote, iclass 37, count 2 2006.224.07:40:40.03#ibcon#about to read 3, iclass 37, count 2 2006.224.07:40:40.04#ibcon#read 3, iclass 37, count 2 2006.224.07:40:40.04#ibcon#about to read 4, iclass 37, count 2 2006.224.07:40:40.04#ibcon#read 4, iclass 37, count 2 2006.224.07:40:40.04#ibcon#about to read 5, iclass 37, count 2 2006.224.07:40:40.05#ibcon#read 5, iclass 37, count 2 2006.224.07:40:40.05#ibcon#about to read 6, iclass 37, count 2 2006.224.07:40:40.05#ibcon#read 6, iclass 37, count 2 2006.224.07:40:40.05#ibcon#end of sib2, iclass 37, count 2 2006.224.07:40:40.05#ibcon#*mode == 0, iclass 37, count 2 2006.224.07:40:40.05#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.224.07:40:40.05#ibcon#[25=AT07-06\r\n] 2006.224.07:40:40.05#ibcon#*before write, iclass 37, count 2 2006.224.07:40:40.05#ibcon#enter sib2, iclass 37, count 2 2006.224.07:40:40.05#ibcon#flushed, iclass 37, count 2 2006.224.07:40:40.05#ibcon#about to write, iclass 37, count 2 2006.224.07:40:40.05#ibcon#wrote, iclass 37, count 2 2006.224.07:40:40.05#ibcon#about to read 3, iclass 37, count 2 2006.224.07:40:40.07#ibcon#read 3, iclass 37, count 2 2006.224.07:40:40.07#ibcon#about to read 4, iclass 37, count 2 2006.224.07:40:40.08#ibcon#read 4, iclass 37, count 2 2006.224.07:40:40.08#ibcon#about to read 5, iclass 37, count 2 2006.224.07:40:40.08#ibcon#read 5, iclass 37, count 2 2006.224.07:40:40.08#ibcon#about to read 6, iclass 37, count 2 2006.224.07:40:40.08#ibcon#read 6, iclass 37, count 2 2006.224.07:40:40.08#ibcon#end of sib2, iclass 37, count 2 2006.224.07:40:40.08#ibcon#*after write, iclass 37, count 2 2006.224.07:40:40.08#ibcon#*before return 0, iclass 37, count 2 2006.224.07:40:40.08#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.224.07:40:40.08#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.224.07:40:40.08#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.224.07:40:40.08#ibcon#ireg 7 cls_cnt 0 2006.224.07:40:40.08#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.224.07:40:40.19#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.224.07:40:40.19#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.224.07:40:40.19#ibcon#enter wrdev, iclass 37, count 0 2006.224.07:40:40.19#ibcon#first serial, iclass 37, count 0 2006.224.07:40:40.19#ibcon#enter sib2, iclass 37, count 0 2006.224.07:40:40.19#ibcon#flushed, iclass 37, count 0 2006.224.07:40:40.20#ibcon#about to write, iclass 37, count 0 2006.224.07:40:40.20#ibcon#wrote, iclass 37, count 0 2006.224.07:40:40.20#ibcon#about to read 3, iclass 37, count 0 2006.224.07:40:40.21#ibcon#read 3, iclass 37, count 0 2006.224.07:40:40.21#ibcon#about to read 4, iclass 37, count 0 2006.224.07:40:40.21#ibcon#read 4, iclass 37, count 0 2006.224.07:40:40.21#ibcon#about to read 5, iclass 37, count 0 2006.224.07:40:40.21#ibcon#read 5, iclass 37, count 0 2006.224.07:40:40.22#ibcon#about to read 6, iclass 37, count 0 2006.224.07:40:40.22#ibcon#read 6, iclass 37, count 0 2006.224.07:40:40.22#ibcon#end of sib2, iclass 37, count 0 2006.224.07:40:40.22#ibcon#*mode == 0, iclass 37, count 0 2006.224.07:40:40.22#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.224.07:40:40.22#ibcon#[25=USB\r\n] 2006.224.07:40:40.22#ibcon#*before write, iclass 37, count 0 2006.224.07:40:40.22#ibcon#enter sib2, iclass 37, count 0 2006.224.07:40:40.22#ibcon#flushed, iclass 37, count 0 2006.224.07:40:40.22#ibcon#about to write, iclass 37, count 0 2006.224.07:40:40.22#ibcon#wrote, iclass 37, count 0 2006.224.07:40:40.22#ibcon#about to read 3, iclass 37, count 0 2006.224.07:40:40.24#ibcon#read 3, iclass 37, count 0 2006.224.07:40:40.25#ibcon#about to read 4, iclass 37, count 0 2006.224.07:40:40.25#ibcon#read 4, iclass 37, count 0 2006.224.07:40:40.25#ibcon#about to read 5, iclass 37, count 0 2006.224.07:40:40.25#ibcon#read 5, iclass 37, count 0 2006.224.07:40:40.25#ibcon#about to read 6, iclass 37, count 0 2006.224.07:40:40.25#ibcon#read 6, iclass 37, count 0 2006.224.07:40:40.25#ibcon#end of sib2, iclass 37, count 0 2006.224.07:40:40.25#ibcon#*after write, iclass 37, count 0 2006.224.07:40:40.25#ibcon#*before return 0, iclass 37, count 0 2006.224.07:40:40.25#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.224.07:40:40.25#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.224.07:40:40.25#ibcon#about to clear, iclass 37 cls_cnt 0 2006.224.07:40:40.25#ibcon#cleared, iclass 37 cls_cnt 0 2006.224.07:40:40.25$vc4f8/valo=8,852.99 2006.224.07:40:40.25#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.224.07:40:40.25#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.224.07:40:40.25#ibcon#ireg 17 cls_cnt 0 2006.224.07:40:40.25#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.224.07:40:40.25#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.224.07:40:40.25#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.224.07:40:40.25#ibcon#enter wrdev, iclass 39, count 0 2006.224.07:40:40.25#ibcon#first serial, iclass 39, count 0 2006.224.07:40:40.25#ibcon#enter sib2, iclass 39, count 0 2006.224.07:40:40.25#ibcon#flushed, iclass 39, count 0 2006.224.07:40:40.25#ibcon#about to write, iclass 39, count 0 2006.224.07:40:40.25#ibcon#wrote, iclass 39, count 0 2006.224.07:40:40.25#ibcon#about to read 3, iclass 39, count 0 2006.224.07:40:40.26#ibcon#read 3, iclass 39, count 0 2006.224.07:40:40.26#ibcon#about to read 4, iclass 39, count 0 2006.224.07:40:40.26#ibcon#read 4, iclass 39, count 0 2006.224.07:40:40.26#ibcon#about to read 5, iclass 39, count 0 2006.224.07:40:40.27#ibcon#read 5, iclass 39, count 0 2006.224.07:40:40.27#ibcon#about to read 6, iclass 39, count 0 2006.224.07:40:40.27#ibcon#read 6, iclass 39, count 0 2006.224.07:40:40.27#ibcon#end of sib2, iclass 39, count 0 2006.224.07:40:40.27#ibcon#*mode == 0, iclass 39, count 0 2006.224.07:40:40.27#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.224.07:40:40.27#ibcon#[26=FRQ=08,852.99\r\n] 2006.224.07:40:40.27#ibcon#*before write, iclass 39, count 0 2006.224.07:40:40.27#ibcon#enter sib2, iclass 39, count 0 2006.224.07:40:40.27#ibcon#flushed, iclass 39, count 0 2006.224.07:40:40.27#ibcon#about to write, iclass 39, count 0 2006.224.07:40:40.27#ibcon#wrote, iclass 39, count 0 2006.224.07:40:40.27#ibcon#about to read 3, iclass 39, count 0 2006.224.07:40:40.30#ibcon#read 3, iclass 39, count 0 2006.224.07:40:40.30#ibcon#about to read 4, iclass 39, count 0 2006.224.07:40:40.30#ibcon#read 4, iclass 39, count 0 2006.224.07:40:40.30#ibcon#about to read 5, iclass 39, count 0 2006.224.07:40:40.31#ibcon#read 5, iclass 39, count 0 2006.224.07:40:40.31#ibcon#about to read 6, iclass 39, count 0 2006.224.07:40:40.31#ibcon#read 6, iclass 39, count 0 2006.224.07:40:40.31#ibcon#end of sib2, iclass 39, count 0 2006.224.07:40:40.31#ibcon#*after write, iclass 39, count 0 2006.224.07:40:40.31#ibcon#*before return 0, iclass 39, count 0 2006.224.07:40:40.31#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.224.07:40:40.31#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.224.07:40:40.31#ibcon#about to clear, iclass 39 cls_cnt 0 2006.224.07:40:40.31#ibcon#cleared, iclass 39 cls_cnt 0 2006.224.07:40:40.31$vc4f8/va=8,7 2006.224.07:40:40.31#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.224.07:40:40.31#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.224.07:40:40.31#ibcon#ireg 11 cls_cnt 2 2006.224.07:40:40.31#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.224.07:40:40.36#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.224.07:40:40.36#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.224.07:40:40.36#ibcon#enter wrdev, iclass 3, count 2 2006.224.07:40:40.36#ibcon#first serial, iclass 3, count 2 2006.224.07:40:40.36#ibcon#enter sib2, iclass 3, count 2 2006.224.07:40:40.37#ibcon#flushed, iclass 3, count 2 2006.224.07:40:40.37#ibcon#about to write, iclass 3, count 2 2006.224.07:40:40.37#ibcon#wrote, iclass 3, count 2 2006.224.07:40:40.37#ibcon#about to read 3, iclass 3, count 2 2006.224.07:40:40.38#ibcon#read 3, iclass 3, count 2 2006.224.07:40:40.38#ibcon#about to read 4, iclass 3, count 2 2006.224.07:40:40.38#ibcon#read 4, iclass 3, count 2 2006.224.07:40:40.38#ibcon#about to read 5, iclass 3, count 2 2006.224.07:40:40.39#ibcon#read 5, iclass 3, count 2 2006.224.07:40:40.39#ibcon#about to read 6, iclass 3, count 2 2006.224.07:40:40.39#ibcon#read 6, iclass 3, count 2 2006.224.07:40:40.39#ibcon#end of sib2, iclass 3, count 2 2006.224.07:40:40.39#ibcon#*mode == 0, iclass 3, count 2 2006.224.07:40:40.39#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.224.07:40:40.39#ibcon#[25=AT08-07\r\n] 2006.224.07:40:40.39#ibcon#*before write, iclass 3, count 2 2006.224.07:40:40.39#ibcon#enter sib2, iclass 3, count 2 2006.224.07:40:40.39#ibcon#flushed, iclass 3, count 2 2006.224.07:40:40.39#ibcon#about to write, iclass 3, count 2 2006.224.07:40:40.39#ibcon#wrote, iclass 3, count 2 2006.224.07:40:40.39#ibcon#about to read 3, iclass 3, count 2 2006.224.07:40:40.41#ibcon#read 3, iclass 3, count 2 2006.224.07:40:40.41#ibcon#about to read 4, iclass 3, count 2 2006.224.07:40:40.41#ibcon#read 4, iclass 3, count 2 2006.224.07:40:40.41#ibcon#about to read 5, iclass 3, count 2 2006.224.07:40:40.42#ibcon#read 5, iclass 3, count 2 2006.224.07:40:40.42#ibcon#about to read 6, iclass 3, count 2 2006.224.07:40:40.42#ibcon#read 6, iclass 3, count 2 2006.224.07:40:40.42#ibcon#end of sib2, iclass 3, count 2 2006.224.07:40:40.42#ibcon#*after write, iclass 3, count 2 2006.224.07:40:40.42#ibcon#*before return 0, iclass 3, count 2 2006.224.07:40:40.42#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.224.07:40:40.42#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.224.07:40:40.42#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.224.07:40:40.42#ibcon#ireg 7 cls_cnt 0 2006.224.07:40:40.42#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.224.07:40:40.53#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.224.07:40:40.53#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.224.07:40:40.53#ibcon#enter wrdev, iclass 3, count 0 2006.224.07:40:40.53#ibcon#first serial, iclass 3, count 0 2006.224.07:40:40.53#ibcon#enter sib2, iclass 3, count 0 2006.224.07:40:40.54#ibcon#flushed, iclass 3, count 0 2006.224.07:40:40.54#ibcon#about to write, iclass 3, count 0 2006.224.07:40:40.54#ibcon#wrote, iclass 3, count 0 2006.224.07:40:40.54#ibcon#about to read 3, iclass 3, count 0 2006.224.07:40:40.55#ibcon#read 3, iclass 3, count 0 2006.224.07:40:40.55#ibcon#about to read 4, iclass 3, count 0 2006.224.07:40:40.55#ibcon#read 4, iclass 3, count 0 2006.224.07:40:40.55#ibcon#about to read 5, iclass 3, count 0 2006.224.07:40:40.56#ibcon#read 5, iclass 3, count 0 2006.224.07:40:40.56#ibcon#about to read 6, iclass 3, count 0 2006.224.07:40:40.56#ibcon#read 6, iclass 3, count 0 2006.224.07:40:40.56#ibcon#end of sib2, iclass 3, count 0 2006.224.07:40:40.56#ibcon#*mode == 0, iclass 3, count 0 2006.224.07:40:40.56#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.224.07:40:40.56#ibcon#[25=USB\r\n] 2006.224.07:40:40.56#ibcon#*before write, iclass 3, count 0 2006.224.07:40:40.56#ibcon#enter sib2, iclass 3, count 0 2006.224.07:40:40.56#ibcon#flushed, iclass 3, count 0 2006.224.07:40:40.56#ibcon#about to write, iclass 3, count 0 2006.224.07:40:40.56#ibcon#wrote, iclass 3, count 0 2006.224.07:40:40.56#ibcon#about to read 3, iclass 3, count 0 2006.224.07:40:40.58#ibcon#read 3, iclass 3, count 0 2006.224.07:40:40.58#ibcon#about to read 4, iclass 3, count 0 2006.224.07:40:40.58#ibcon#read 4, iclass 3, count 0 2006.224.07:40:40.58#ibcon#about to read 5, iclass 3, count 0 2006.224.07:40:40.59#ibcon#read 5, iclass 3, count 0 2006.224.07:40:40.59#ibcon#about to read 6, iclass 3, count 0 2006.224.07:40:40.59#ibcon#read 6, iclass 3, count 0 2006.224.07:40:40.59#ibcon#end of sib2, iclass 3, count 0 2006.224.07:40:40.59#ibcon#*after write, iclass 3, count 0 2006.224.07:40:40.59#ibcon#*before return 0, iclass 3, count 0 2006.224.07:40:40.59#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.224.07:40:40.59#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.224.07:40:40.59#ibcon#about to clear, iclass 3 cls_cnt 0 2006.224.07:40:40.59#ibcon#cleared, iclass 3 cls_cnt 0 2006.224.07:40:40.59$vc4f8/vblo=1,632.99 2006.224.07:40:40.59#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.224.07:40:40.59#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.224.07:40:40.59#ibcon#ireg 17 cls_cnt 0 2006.224.07:40:40.59#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.224.07:40:40.59#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.224.07:40:40.59#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.224.07:40:40.59#ibcon#enter wrdev, iclass 5, count 0 2006.224.07:40:40.59#ibcon#first serial, iclass 5, count 0 2006.224.07:40:40.59#ibcon#enter sib2, iclass 5, count 0 2006.224.07:40:40.59#ibcon#flushed, iclass 5, count 0 2006.224.07:40:40.59#ibcon#about to write, iclass 5, count 0 2006.224.07:40:40.59#ibcon#wrote, iclass 5, count 0 2006.224.07:40:40.59#ibcon#about to read 3, iclass 5, count 0 2006.224.07:40:40.60#ibcon#read 3, iclass 5, count 0 2006.224.07:40:40.60#ibcon#about to read 4, iclass 5, count 0 2006.224.07:40:40.60#ibcon#read 4, iclass 5, count 0 2006.224.07:40:40.60#ibcon#about to read 5, iclass 5, count 0 2006.224.07:40:40.61#ibcon#read 5, iclass 5, count 0 2006.224.07:40:40.61#ibcon#about to read 6, iclass 5, count 0 2006.224.07:40:40.61#ibcon#read 6, iclass 5, count 0 2006.224.07:40:40.61#ibcon#end of sib2, iclass 5, count 0 2006.224.07:40:40.61#ibcon#*mode == 0, iclass 5, count 0 2006.224.07:40:40.61#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.224.07:40:40.61#ibcon#[28=FRQ=01,632.99\r\n] 2006.224.07:40:40.61#ibcon#*before write, iclass 5, count 0 2006.224.07:40:40.61#ibcon#enter sib2, iclass 5, count 0 2006.224.07:40:40.61#ibcon#flushed, iclass 5, count 0 2006.224.07:40:40.61#ibcon#about to write, iclass 5, count 0 2006.224.07:40:40.61#ibcon#wrote, iclass 5, count 0 2006.224.07:40:40.61#ibcon#about to read 3, iclass 5, count 0 2006.224.07:40:40.64#ibcon#read 3, iclass 5, count 0 2006.224.07:40:40.64#ibcon#about to read 4, iclass 5, count 0 2006.224.07:40:40.64#ibcon#read 4, iclass 5, count 0 2006.224.07:40:40.64#ibcon#about to read 5, iclass 5, count 0 2006.224.07:40:40.65#ibcon#read 5, iclass 5, count 0 2006.224.07:40:40.65#ibcon#about to read 6, iclass 5, count 0 2006.224.07:40:40.65#ibcon#read 6, iclass 5, count 0 2006.224.07:40:40.65#ibcon#end of sib2, iclass 5, count 0 2006.224.07:40:40.65#ibcon#*after write, iclass 5, count 0 2006.224.07:40:40.65#ibcon#*before return 0, iclass 5, count 0 2006.224.07:40:40.65#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.224.07:40:40.65#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.224.07:40:40.65#ibcon#about to clear, iclass 5 cls_cnt 0 2006.224.07:40:40.65#ibcon#cleared, iclass 5 cls_cnt 0 2006.224.07:40:40.65$vc4f8/vb=1,4 2006.224.07:40:40.65#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.224.07:40:40.65#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.224.07:40:40.65#ibcon#ireg 11 cls_cnt 2 2006.224.07:40:40.65#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.224.07:40:40.65#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.224.07:40:40.65#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.224.07:40:40.65#ibcon#enter wrdev, iclass 7, count 2 2006.224.07:40:40.65#ibcon#first serial, iclass 7, count 2 2006.224.07:40:40.65#ibcon#enter sib2, iclass 7, count 2 2006.224.07:40:40.65#ibcon#flushed, iclass 7, count 2 2006.224.07:40:40.65#ibcon#about to write, iclass 7, count 2 2006.224.07:40:40.65#ibcon#wrote, iclass 7, count 2 2006.224.07:40:40.65#ibcon#about to read 3, iclass 7, count 2 2006.224.07:40:40.66#ibcon#read 3, iclass 7, count 2 2006.224.07:40:40.66#ibcon#about to read 4, iclass 7, count 2 2006.224.07:40:40.66#ibcon#read 4, iclass 7, count 2 2006.224.07:40:40.66#ibcon#about to read 5, iclass 7, count 2 2006.224.07:40:40.67#ibcon#read 5, iclass 7, count 2 2006.224.07:40:40.67#ibcon#about to read 6, iclass 7, count 2 2006.224.07:40:40.67#ibcon#read 6, iclass 7, count 2 2006.224.07:40:40.67#ibcon#end of sib2, iclass 7, count 2 2006.224.07:40:40.67#ibcon#*mode == 0, iclass 7, count 2 2006.224.07:40:40.67#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.224.07:40:40.67#ibcon#[27=AT01-04\r\n] 2006.224.07:40:40.67#ibcon#*before write, iclass 7, count 2 2006.224.07:40:40.67#ibcon#enter sib2, iclass 7, count 2 2006.224.07:40:40.67#ibcon#flushed, iclass 7, count 2 2006.224.07:40:40.67#ibcon#about to write, iclass 7, count 2 2006.224.07:40:40.67#ibcon#wrote, iclass 7, count 2 2006.224.07:40:40.67#ibcon#about to read 3, iclass 7, count 2 2006.224.07:40:40.69#ibcon#read 3, iclass 7, count 2 2006.224.07:40:40.69#ibcon#about to read 4, iclass 7, count 2 2006.224.07:40:40.69#ibcon#read 4, iclass 7, count 2 2006.224.07:40:40.69#ibcon#about to read 5, iclass 7, count 2 2006.224.07:40:40.70#ibcon#read 5, iclass 7, count 2 2006.224.07:40:40.70#ibcon#about to read 6, iclass 7, count 2 2006.224.07:40:40.70#ibcon#read 6, iclass 7, count 2 2006.224.07:40:40.70#ibcon#end of sib2, iclass 7, count 2 2006.224.07:40:40.70#ibcon#*after write, iclass 7, count 2 2006.224.07:40:40.70#ibcon#*before return 0, iclass 7, count 2 2006.224.07:40:40.70#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.224.07:40:40.70#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.224.07:40:40.70#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.224.07:40:40.70#ibcon#ireg 7 cls_cnt 0 2006.224.07:40:40.70#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.224.07:40:40.81#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.224.07:40:40.81#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.224.07:40:40.81#ibcon#enter wrdev, iclass 7, count 0 2006.224.07:40:40.81#ibcon#first serial, iclass 7, count 0 2006.224.07:40:40.81#ibcon#enter sib2, iclass 7, count 0 2006.224.07:40:40.82#ibcon#flushed, iclass 7, count 0 2006.224.07:40:40.82#ibcon#about to write, iclass 7, count 0 2006.224.07:40:40.82#ibcon#wrote, iclass 7, count 0 2006.224.07:40:40.82#ibcon#about to read 3, iclass 7, count 0 2006.224.07:40:40.83#ibcon#read 3, iclass 7, count 0 2006.224.07:40:40.83#ibcon#about to read 4, iclass 7, count 0 2006.224.07:40:40.84#ibcon#read 4, iclass 7, count 0 2006.224.07:40:40.84#ibcon#about to read 5, iclass 7, count 0 2006.224.07:40:40.84#ibcon#read 5, iclass 7, count 0 2006.224.07:40:40.84#ibcon#about to read 6, iclass 7, count 0 2006.224.07:40:40.84#ibcon#read 6, iclass 7, count 0 2006.224.07:40:40.84#ibcon#end of sib2, iclass 7, count 0 2006.224.07:40:40.84#ibcon#*mode == 0, iclass 7, count 0 2006.224.07:40:40.84#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.224.07:40:40.84#ibcon#[27=USB\r\n] 2006.224.07:40:40.84#ibcon#*before write, iclass 7, count 0 2006.224.07:40:40.84#ibcon#enter sib2, iclass 7, count 0 2006.224.07:40:40.84#ibcon#flushed, iclass 7, count 0 2006.224.07:40:40.84#ibcon#about to write, iclass 7, count 0 2006.224.07:40:40.84#ibcon#wrote, iclass 7, count 0 2006.224.07:40:40.84#ibcon#about to read 3, iclass 7, count 0 2006.224.07:40:40.86#ibcon#read 3, iclass 7, count 0 2006.224.07:40:40.86#ibcon#about to read 4, iclass 7, count 0 2006.224.07:40:40.86#ibcon#read 4, iclass 7, count 0 2006.224.07:40:40.86#ibcon#about to read 5, iclass 7, count 0 2006.224.07:40:40.87#ibcon#read 5, iclass 7, count 0 2006.224.07:40:40.87#ibcon#about to read 6, iclass 7, count 0 2006.224.07:40:40.87#ibcon#read 6, iclass 7, count 0 2006.224.07:40:40.87#ibcon#end of sib2, iclass 7, count 0 2006.224.07:40:40.87#ibcon#*after write, iclass 7, count 0 2006.224.07:40:40.87#ibcon#*before return 0, iclass 7, count 0 2006.224.07:40:40.87#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.224.07:40:40.87#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.224.07:40:40.87#ibcon#about to clear, iclass 7 cls_cnt 0 2006.224.07:40:40.87#ibcon#cleared, iclass 7 cls_cnt 0 2006.224.07:40:40.87$vc4f8/vblo=2,640.99 2006.224.07:40:40.87#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.224.07:40:40.87#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.224.07:40:40.87#ibcon#ireg 17 cls_cnt 0 2006.224.07:40:40.87#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.224.07:40:40.87#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.224.07:40:40.87#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.224.07:40:40.87#ibcon#enter wrdev, iclass 11, count 0 2006.224.07:40:40.87#ibcon#first serial, iclass 11, count 0 2006.224.07:40:40.87#ibcon#enter sib2, iclass 11, count 0 2006.224.07:40:40.87#ibcon#flushed, iclass 11, count 0 2006.224.07:40:40.87#ibcon#about to write, iclass 11, count 0 2006.224.07:40:40.87#ibcon#wrote, iclass 11, count 0 2006.224.07:40:40.87#ibcon#about to read 3, iclass 11, count 0 2006.224.07:40:40.88#ibcon#read 3, iclass 11, count 0 2006.224.07:40:40.88#ibcon#about to read 4, iclass 11, count 0 2006.224.07:40:40.88#ibcon#read 4, iclass 11, count 0 2006.224.07:40:40.88#ibcon#about to read 5, iclass 11, count 0 2006.224.07:40:40.89#ibcon#read 5, iclass 11, count 0 2006.224.07:40:40.89#ibcon#about to read 6, iclass 11, count 0 2006.224.07:40:40.89#ibcon#read 6, iclass 11, count 0 2006.224.07:40:40.89#ibcon#end of sib2, iclass 11, count 0 2006.224.07:40:40.89#ibcon#*mode == 0, iclass 11, count 0 2006.224.07:40:40.89#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.224.07:40:40.89#ibcon#[28=FRQ=02,640.99\r\n] 2006.224.07:40:40.89#ibcon#*before write, iclass 11, count 0 2006.224.07:40:40.89#ibcon#enter sib2, iclass 11, count 0 2006.224.07:40:40.89#ibcon#flushed, iclass 11, count 0 2006.224.07:40:40.89#ibcon#about to write, iclass 11, count 0 2006.224.07:40:40.89#ibcon#wrote, iclass 11, count 0 2006.224.07:40:40.89#ibcon#about to read 3, iclass 11, count 0 2006.224.07:40:40.92#ibcon#read 3, iclass 11, count 0 2006.224.07:40:40.92#ibcon#about to read 4, iclass 11, count 0 2006.224.07:40:40.92#ibcon#read 4, iclass 11, count 0 2006.224.07:40:40.92#ibcon#about to read 5, iclass 11, count 0 2006.224.07:40:40.93#ibcon#read 5, iclass 11, count 0 2006.224.07:40:40.93#ibcon#about to read 6, iclass 11, count 0 2006.224.07:40:40.93#ibcon#read 6, iclass 11, count 0 2006.224.07:40:40.93#ibcon#end of sib2, iclass 11, count 0 2006.224.07:40:40.93#ibcon#*after write, iclass 11, count 0 2006.224.07:40:40.93#ibcon#*before return 0, iclass 11, count 0 2006.224.07:40:40.93#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.224.07:40:40.93#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.224.07:40:40.93#ibcon#about to clear, iclass 11 cls_cnt 0 2006.224.07:40:40.93#ibcon#cleared, iclass 11 cls_cnt 0 2006.224.07:40:40.93$vc4f8/vb=2,4 2006.224.07:40:40.93#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.224.07:40:40.93#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.224.07:40:40.93#ibcon#ireg 11 cls_cnt 2 2006.224.07:40:40.93#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.224.07:40:40.98#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.224.07:40:40.98#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.224.07:40:40.98#ibcon#enter wrdev, iclass 13, count 2 2006.224.07:40:40.98#ibcon#first serial, iclass 13, count 2 2006.224.07:40:40.98#ibcon#enter sib2, iclass 13, count 2 2006.224.07:40:40.98#ibcon#flushed, iclass 13, count 2 2006.224.07:40:40.99#ibcon#about to write, iclass 13, count 2 2006.224.07:40:40.99#ibcon#wrote, iclass 13, count 2 2006.224.07:40:40.99#ibcon#about to read 3, iclass 13, count 2 2006.224.07:40:41.00#ibcon#read 3, iclass 13, count 2 2006.224.07:40:41.00#ibcon#about to read 4, iclass 13, count 2 2006.224.07:40:41.00#ibcon#read 4, iclass 13, count 2 2006.224.07:40:41.00#ibcon#about to read 5, iclass 13, count 2 2006.224.07:40:41.01#ibcon#read 5, iclass 13, count 2 2006.224.07:40:41.01#ibcon#about to read 6, iclass 13, count 2 2006.224.07:40:41.01#ibcon#read 6, iclass 13, count 2 2006.224.07:40:41.01#ibcon#end of sib2, iclass 13, count 2 2006.224.07:40:41.01#ibcon#*mode == 0, iclass 13, count 2 2006.224.07:40:41.01#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.224.07:40:41.01#ibcon#[27=AT02-04\r\n] 2006.224.07:40:41.01#ibcon#*before write, iclass 13, count 2 2006.224.07:40:41.01#ibcon#enter sib2, iclass 13, count 2 2006.224.07:40:41.01#ibcon#flushed, iclass 13, count 2 2006.224.07:40:41.01#ibcon#about to write, iclass 13, count 2 2006.224.07:40:41.01#ibcon#wrote, iclass 13, count 2 2006.224.07:40:41.01#ibcon#about to read 3, iclass 13, count 2 2006.224.07:40:41.03#ibcon#read 3, iclass 13, count 2 2006.224.07:40:41.03#ibcon#about to read 4, iclass 13, count 2 2006.224.07:40:41.04#ibcon#read 4, iclass 13, count 2 2006.224.07:40:41.04#ibcon#about to read 5, iclass 13, count 2 2006.224.07:40:41.04#ibcon#read 5, iclass 13, count 2 2006.224.07:40:41.04#ibcon#about to read 6, iclass 13, count 2 2006.224.07:40:41.04#ibcon#read 6, iclass 13, count 2 2006.224.07:40:41.04#ibcon#end of sib2, iclass 13, count 2 2006.224.07:40:41.04#ibcon#*after write, iclass 13, count 2 2006.224.07:40:41.04#ibcon#*before return 0, iclass 13, count 2 2006.224.07:40:41.04#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.224.07:40:41.04#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.224.07:40:41.04#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.224.07:40:41.04#ibcon#ireg 7 cls_cnt 0 2006.224.07:40:41.04#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.224.07:40:41.15#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.224.07:40:41.15#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.224.07:40:41.15#ibcon#enter wrdev, iclass 13, count 0 2006.224.07:40:41.15#ibcon#first serial, iclass 13, count 0 2006.224.07:40:41.15#ibcon#enter sib2, iclass 13, count 0 2006.224.07:40:41.15#ibcon#flushed, iclass 13, count 0 2006.224.07:40:41.15#ibcon#about to write, iclass 13, count 0 2006.224.07:40:41.16#ibcon#wrote, iclass 13, count 0 2006.224.07:40:41.16#ibcon#about to read 3, iclass 13, count 0 2006.224.07:40:41.17#ibcon#read 3, iclass 13, count 0 2006.224.07:40:41.17#ibcon#about to read 4, iclass 13, count 0 2006.224.07:40:41.17#ibcon#read 4, iclass 13, count 0 2006.224.07:40:41.17#ibcon#about to read 5, iclass 13, count 0 2006.224.07:40:41.17#ibcon#read 5, iclass 13, count 0 2006.224.07:40:41.18#ibcon#about to read 6, iclass 13, count 0 2006.224.07:40:41.18#ibcon#read 6, iclass 13, count 0 2006.224.07:40:41.18#ibcon#end of sib2, iclass 13, count 0 2006.224.07:40:41.18#ibcon#*mode == 0, iclass 13, count 0 2006.224.07:40:41.18#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.224.07:40:41.18#ibcon#[27=USB\r\n] 2006.224.07:40:41.18#ibcon#*before write, iclass 13, count 0 2006.224.07:40:41.18#ibcon#enter sib2, iclass 13, count 0 2006.224.07:40:41.18#ibcon#flushed, iclass 13, count 0 2006.224.07:40:41.18#ibcon#about to write, iclass 13, count 0 2006.224.07:40:41.18#ibcon#wrote, iclass 13, count 0 2006.224.07:40:41.18#ibcon#about to read 3, iclass 13, count 0 2006.224.07:40:41.20#ibcon#read 3, iclass 13, count 0 2006.224.07:40:41.20#ibcon#about to read 4, iclass 13, count 0 2006.224.07:40:41.20#ibcon#read 4, iclass 13, count 0 2006.224.07:40:41.20#ibcon#about to read 5, iclass 13, count 0 2006.224.07:40:41.21#ibcon#read 5, iclass 13, count 0 2006.224.07:40:41.21#ibcon#about to read 6, iclass 13, count 0 2006.224.07:40:41.21#ibcon#read 6, iclass 13, count 0 2006.224.07:40:41.21#ibcon#end of sib2, iclass 13, count 0 2006.224.07:40:41.21#ibcon#*after write, iclass 13, count 0 2006.224.07:40:41.21#ibcon#*before return 0, iclass 13, count 0 2006.224.07:40:41.21#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.224.07:40:41.21#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.224.07:40:41.21#ibcon#about to clear, iclass 13 cls_cnt 0 2006.224.07:40:41.21#ibcon#cleared, iclass 13 cls_cnt 0 2006.224.07:40:41.21$vc4f8/vblo=3,656.99 2006.224.07:40:41.21#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.224.07:40:41.21#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.224.07:40:41.21#ibcon#ireg 17 cls_cnt 0 2006.224.07:40:41.21#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.224.07:40:41.21#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.224.07:40:41.21#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.224.07:40:41.21#ibcon#enter wrdev, iclass 15, count 0 2006.224.07:40:41.21#ibcon#first serial, iclass 15, count 0 2006.224.07:40:41.21#ibcon#enter sib2, iclass 15, count 0 2006.224.07:40:41.21#ibcon#flushed, iclass 15, count 0 2006.224.07:40:41.21#ibcon#about to write, iclass 15, count 0 2006.224.07:40:41.21#ibcon#wrote, iclass 15, count 0 2006.224.07:40:41.21#ibcon#about to read 3, iclass 15, count 0 2006.224.07:40:41.22#ibcon#read 3, iclass 15, count 0 2006.224.07:40:41.22#ibcon#about to read 4, iclass 15, count 0 2006.224.07:40:41.22#ibcon#read 4, iclass 15, count 0 2006.224.07:40:41.23#ibcon#about to read 5, iclass 15, count 0 2006.224.07:40:41.23#ibcon#read 5, iclass 15, count 0 2006.224.07:40:41.23#ibcon#about to read 6, iclass 15, count 0 2006.224.07:40:41.23#ibcon#read 6, iclass 15, count 0 2006.224.07:40:41.23#ibcon#end of sib2, iclass 15, count 0 2006.224.07:40:41.23#ibcon#*mode == 0, iclass 15, count 0 2006.224.07:40:41.23#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.224.07:40:41.23#ibcon#[28=FRQ=03,656.99\r\n] 2006.224.07:40:41.23#ibcon#*before write, iclass 15, count 0 2006.224.07:40:41.23#ibcon#enter sib2, iclass 15, count 0 2006.224.07:40:41.23#ibcon#flushed, iclass 15, count 0 2006.224.07:40:41.23#ibcon#about to write, iclass 15, count 0 2006.224.07:40:41.23#ibcon#wrote, iclass 15, count 0 2006.224.07:40:41.23#ibcon#about to read 3, iclass 15, count 0 2006.224.07:40:41.26#ibcon#read 3, iclass 15, count 0 2006.224.07:40:41.26#ibcon#about to read 4, iclass 15, count 0 2006.224.07:40:41.26#ibcon#read 4, iclass 15, count 0 2006.224.07:40:41.26#ibcon#about to read 5, iclass 15, count 0 2006.224.07:40:41.27#ibcon#read 5, iclass 15, count 0 2006.224.07:40:41.27#ibcon#about to read 6, iclass 15, count 0 2006.224.07:40:41.27#ibcon#read 6, iclass 15, count 0 2006.224.07:40:41.27#ibcon#end of sib2, iclass 15, count 0 2006.224.07:40:41.27#ibcon#*after write, iclass 15, count 0 2006.224.07:40:41.27#ibcon#*before return 0, iclass 15, count 0 2006.224.07:40:41.27#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.224.07:40:41.27#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.224.07:40:41.27#ibcon#about to clear, iclass 15 cls_cnt 0 2006.224.07:40:41.27#ibcon#cleared, iclass 15 cls_cnt 0 2006.224.07:40:41.27$vc4f8/vb=3,4 2006.224.07:40:41.27#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.224.07:40:41.27#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.224.07:40:41.27#ibcon#ireg 11 cls_cnt 2 2006.224.07:40:41.27#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.224.07:40:41.32#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.224.07:40:41.32#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.224.07:40:41.32#ibcon#enter wrdev, iclass 17, count 2 2006.224.07:40:41.32#ibcon#first serial, iclass 17, count 2 2006.224.07:40:41.32#ibcon#enter sib2, iclass 17, count 2 2006.224.07:40:41.33#ibcon#flushed, iclass 17, count 2 2006.224.07:40:41.33#ibcon#about to write, iclass 17, count 2 2006.224.07:40:41.33#ibcon#wrote, iclass 17, count 2 2006.224.07:40:41.33#ibcon#about to read 3, iclass 17, count 2 2006.224.07:40:41.34#ibcon#read 3, iclass 17, count 2 2006.224.07:40:41.34#ibcon#about to read 4, iclass 17, count 2 2006.224.07:40:41.34#ibcon#read 4, iclass 17, count 2 2006.224.07:40:41.34#ibcon#about to read 5, iclass 17, count 2 2006.224.07:40:41.35#ibcon#read 5, iclass 17, count 2 2006.224.07:40:41.35#ibcon#about to read 6, iclass 17, count 2 2006.224.07:40:41.35#ibcon#read 6, iclass 17, count 2 2006.224.07:40:41.35#ibcon#end of sib2, iclass 17, count 2 2006.224.07:40:41.35#ibcon#*mode == 0, iclass 17, count 2 2006.224.07:40:41.35#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.224.07:40:41.35#ibcon#[27=AT03-04\r\n] 2006.224.07:40:41.35#ibcon#*before write, iclass 17, count 2 2006.224.07:40:41.35#ibcon#enter sib2, iclass 17, count 2 2006.224.07:40:41.35#ibcon#flushed, iclass 17, count 2 2006.224.07:40:41.35#ibcon#about to write, iclass 17, count 2 2006.224.07:40:41.35#ibcon#wrote, iclass 17, count 2 2006.224.07:40:41.35#ibcon#about to read 3, iclass 17, count 2 2006.224.07:40:41.37#ibcon#read 3, iclass 17, count 2 2006.224.07:40:41.37#ibcon#about to read 4, iclass 17, count 2 2006.224.07:40:41.37#ibcon#read 4, iclass 17, count 2 2006.224.07:40:41.37#ibcon#about to read 5, iclass 17, count 2 2006.224.07:40:41.37#ibcon#read 5, iclass 17, count 2 2006.224.07:40:41.38#ibcon#about to read 6, iclass 17, count 2 2006.224.07:40:41.38#ibcon#read 6, iclass 17, count 2 2006.224.07:40:41.38#ibcon#end of sib2, iclass 17, count 2 2006.224.07:40:41.38#ibcon#*after write, iclass 17, count 2 2006.224.07:40:41.38#ibcon#*before return 0, iclass 17, count 2 2006.224.07:40:41.38#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.224.07:40:41.38#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.224.07:40:41.38#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.224.07:40:41.38#ibcon#ireg 7 cls_cnt 0 2006.224.07:40:41.38#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.224.07:40:41.49#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.224.07:40:41.49#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.224.07:40:41.49#ibcon#enter wrdev, iclass 17, count 0 2006.224.07:40:41.49#ibcon#first serial, iclass 17, count 0 2006.224.07:40:41.49#ibcon#enter sib2, iclass 17, count 0 2006.224.07:40:41.49#ibcon#flushed, iclass 17, count 0 2006.224.07:40:41.50#ibcon#about to write, iclass 17, count 0 2006.224.07:40:41.50#ibcon#wrote, iclass 17, count 0 2006.224.07:40:41.50#ibcon#about to read 3, iclass 17, count 0 2006.224.07:40:41.51#ibcon#read 3, iclass 17, count 0 2006.224.07:40:41.51#ibcon#about to read 4, iclass 17, count 0 2006.224.07:40:41.51#ibcon#read 4, iclass 17, count 0 2006.224.07:40:41.51#ibcon#about to read 5, iclass 17, count 0 2006.224.07:40:41.52#ibcon#read 5, iclass 17, count 0 2006.224.07:40:41.52#ibcon#about to read 6, iclass 17, count 0 2006.224.07:40:41.52#ibcon#read 6, iclass 17, count 0 2006.224.07:40:41.52#ibcon#end of sib2, iclass 17, count 0 2006.224.07:40:41.52#ibcon#*mode == 0, iclass 17, count 0 2006.224.07:40:41.52#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.224.07:40:41.52#ibcon#[27=USB\r\n] 2006.224.07:40:41.52#ibcon#*before write, iclass 17, count 0 2006.224.07:40:41.52#ibcon#enter sib2, iclass 17, count 0 2006.224.07:40:41.52#ibcon#flushed, iclass 17, count 0 2006.224.07:40:41.52#ibcon#about to write, iclass 17, count 0 2006.224.07:40:41.52#ibcon#wrote, iclass 17, count 0 2006.224.07:40:41.52#ibcon#about to read 3, iclass 17, count 0 2006.224.07:40:41.54#ibcon#read 3, iclass 17, count 0 2006.224.07:40:41.54#ibcon#about to read 4, iclass 17, count 0 2006.224.07:40:41.54#ibcon#read 4, iclass 17, count 0 2006.224.07:40:41.54#ibcon#about to read 5, iclass 17, count 0 2006.224.07:40:41.55#ibcon#read 5, iclass 17, count 0 2006.224.07:40:41.55#ibcon#about to read 6, iclass 17, count 0 2006.224.07:40:41.55#ibcon#read 6, iclass 17, count 0 2006.224.07:40:41.55#ibcon#end of sib2, iclass 17, count 0 2006.224.07:40:41.55#ibcon#*after write, iclass 17, count 0 2006.224.07:40:41.55#ibcon#*before return 0, iclass 17, count 0 2006.224.07:40:41.55#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.224.07:40:41.55#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.224.07:40:41.55#ibcon#about to clear, iclass 17 cls_cnt 0 2006.224.07:40:41.55#ibcon#cleared, iclass 17 cls_cnt 0 2006.224.07:40:41.55$vc4f8/vblo=4,712.99 2006.224.07:40:41.55#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.224.07:40:41.55#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.224.07:40:41.55#ibcon#ireg 17 cls_cnt 0 2006.224.07:40:41.55#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.224.07:40:41.55#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.224.07:40:41.55#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.224.07:40:41.55#ibcon#enter wrdev, iclass 19, count 0 2006.224.07:40:41.55#ibcon#first serial, iclass 19, count 0 2006.224.07:40:41.55#ibcon#enter sib2, iclass 19, count 0 2006.224.07:40:41.55#ibcon#flushed, iclass 19, count 0 2006.224.07:40:41.55#ibcon#about to write, iclass 19, count 0 2006.224.07:40:41.55#ibcon#wrote, iclass 19, count 0 2006.224.07:40:41.55#ibcon#about to read 3, iclass 19, count 0 2006.224.07:40:41.56#ibcon#read 3, iclass 19, count 0 2006.224.07:40:41.56#ibcon#about to read 4, iclass 19, count 0 2006.224.07:40:41.56#ibcon#read 4, iclass 19, count 0 2006.224.07:40:41.56#ibcon#about to read 5, iclass 19, count 0 2006.224.07:40:41.56#ibcon#read 5, iclass 19, count 0 2006.224.07:40:41.57#ibcon#about to read 6, iclass 19, count 0 2006.224.07:40:41.57#ibcon#read 6, iclass 19, count 0 2006.224.07:40:41.57#ibcon#end of sib2, iclass 19, count 0 2006.224.07:40:41.57#ibcon#*mode == 0, iclass 19, count 0 2006.224.07:40:41.57#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.224.07:40:41.57#ibcon#[28=FRQ=04,712.99\r\n] 2006.224.07:40:41.57#ibcon#*before write, iclass 19, count 0 2006.224.07:40:41.57#ibcon#enter sib2, iclass 19, count 0 2006.224.07:40:41.57#ibcon#flushed, iclass 19, count 0 2006.224.07:40:41.57#ibcon#about to write, iclass 19, count 0 2006.224.07:40:41.57#ibcon#wrote, iclass 19, count 0 2006.224.07:40:41.57#ibcon#about to read 3, iclass 19, count 0 2006.224.07:40:41.60#ibcon#read 3, iclass 19, count 0 2006.224.07:40:41.60#ibcon#about to read 4, iclass 19, count 0 2006.224.07:40:41.60#ibcon#read 4, iclass 19, count 0 2006.224.07:40:41.60#ibcon#about to read 5, iclass 19, count 0 2006.224.07:40:41.61#ibcon#read 5, iclass 19, count 0 2006.224.07:40:41.61#ibcon#about to read 6, iclass 19, count 0 2006.224.07:40:41.61#ibcon#read 6, iclass 19, count 0 2006.224.07:40:41.61#ibcon#end of sib2, iclass 19, count 0 2006.224.07:40:41.61#ibcon#*after write, iclass 19, count 0 2006.224.07:40:41.61#ibcon#*before return 0, iclass 19, count 0 2006.224.07:40:41.61#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.224.07:40:41.61#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.224.07:40:41.61#ibcon#about to clear, iclass 19 cls_cnt 0 2006.224.07:40:41.61#ibcon#cleared, iclass 19 cls_cnt 0 2006.224.07:40:41.61$vc4f8/vb=4,4 2006.224.07:40:41.61#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.224.07:40:41.61#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.224.07:40:41.61#ibcon#ireg 11 cls_cnt 2 2006.224.07:40:41.61#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.224.07:40:41.66#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.224.07:40:41.66#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.224.07:40:41.66#ibcon#enter wrdev, iclass 21, count 2 2006.224.07:40:41.66#ibcon#first serial, iclass 21, count 2 2006.224.07:40:41.66#ibcon#enter sib2, iclass 21, count 2 2006.224.07:40:41.66#ibcon#flushed, iclass 21, count 2 2006.224.07:40:41.67#ibcon#about to write, iclass 21, count 2 2006.224.07:40:41.67#ibcon#wrote, iclass 21, count 2 2006.224.07:40:41.67#ibcon#about to read 3, iclass 21, count 2 2006.224.07:40:41.68#ibcon#read 3, iclass 21, count 2 2006.224.07:40:41.68#ibcon#about to read 4, iclass 21, count 2 2006.224.07:40:41.68#ibcon#read 4, iclass 21, count 2 2006.224.07:40:41.68#ibcon#about to read 5, iclass 21, count 2 2006.224.07:40:41.68#ibcon#read 5, iclass 21, count 2 2006.224.07:40:41.69#ibcon#about to read 6, iclass 21, count 2 2006.224.07:40:41.69#ibcon#read 6, iclass 21, count 2 2006.224.07:40:41.69#ibcon#end of sib2, iclass 21, count 2 2006.224.07:40:41.69#ibcon#*mode == 0, iclass 21, count 2 2006.224.07:40:41.69#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.224.07:40:41.69#ibcon#[27=AT04-04\r\n] 2006.224.07:40:41.69#ibcon#*before write, iclass 21, count 2 2006.224.07:40:41.69#ibcon#enter sib2, iclass 21, count 2 2006.224.07:40:41.69#ibcon#flushed, iclass 21, count 2 2006.224.07:40:41.69#ibcon#about to write, iclass 21, count 2 2006.224.07:40:41.69#ibcon#wrote, iclass 21, count 2 2006.224.07:40:41.69#ibcon#about to read 3, iclass 21, count 2 2006.224.07:40:41.71#ibcon#read 3, iclass 21, count 2 2006.224.07:40:41.71#ibcon#about to read 4, iclass 21, count 2 2006.224.07:40:41.72#ibcon#read 4, iclass 21, count 2 2006.224.07:40:41.72#ibcon#about to read 5, iclass 21, count 2 2006.224.07:40:41.72#ibcon#read 5, iclass 21, count 2 2006.224.07:40:41.72#ibcon#about to read 6, iclass 21, count 2 2006.224.07:40:41.72#ibcon#read 6, iclass 21, count 2 2006.224.07:40:41.72#ibcon#end of sib2, iclass 21, count 2 2006.224.07:40:41.72#ibcon#*after write, iclass 21, count 2 2006.224.07:40:41.72#ibcon#*before return 0, iclass 21, count 2 2006.224.07:40:41.72#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.224.07:40:41.72#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.224.07:40:41.72#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.224.07:40:41.72#ibcon#ireg 7 cls_cnt 0 2006.224.07:40:41.72#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.224.07:40:41.83#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.224.07:40:41.83#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.224.07:40:41.83#ibcon#enter wrdev, iclass 21, count 0 2006.224.07:40:41.83#ibcon#first serial, iclass 21, count 0 2006.224.07:40:41.83#ibcon#enter sib2, iclass 21, count 0 2006.224.07:40:41.83#ibcon#flushed, iclass 21, count 0 2006.224.07:40:41.84#ibcon#about to write, iclass 21, count 0 2006.224.07:40:41.84#ibcon#wrote, iclass 21, count 0 2006.224.07:40:41.84#ibcon#about to read 3, iclass 21, count 0 2006.224.07:40:41.85#ibcon#read 3, iclass 21, count 0 2006.224.07:40:41.85#ibcon#about to read 4, iclass 21, count 0 2006.224.07:40:41.85#ibcon#read 4, iclass 21, count 0 2006.224.07:40:41.85#ibcon#about to read 5, iclass 21, count 0 2006.224.07:40:41.85#ibcon#read 5, iclass 21, count 0 2006.224.07:40:41.86#ibcon#about to read 6, iclass 21, count 0 2006.224.07:40:41.86#ibcon#read 6, iclass 21, count 0 2006.224.07:40:41.86#ibcon#end of sib2, iclass 21, count 0 2006.224.07:40:41.86#ibcon#*mode == 0, iclass 21, count 0 2006.224.07:40:41.86#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.224.07:40:41.86#ibcon#[27=USB\r\n] 2006.224.07:40:41.86#ibcon#*before write, iclass 21, count 0 2006.224.07:40:41.86#ibcon#enter sib2, iclass 21, count 0 2006.224.07:40:41.86#ibcon#flushed, iclass 21, count 0 2006.224.07:40:41.86#ibcon#about to write, iclass 21, count 0 2006.224.07:40:41.86#ibcon#wrote, iclass 21, count 0 2006.224.07:40:41.86#ibcon#about to read 3, iclass 21, count 0 2006.224.07:40:41.88#ibcon#read 3, iclass 21, count 0 2006.224.07:40:41.88#ibcon#about to read 4, iclass 21, count 0 2006.224.07:40:41.88#ibcon#read 4, iclass 21, count 0 2006.224.07:40:41.88#ibcon#about to read 5, iclass 21, count 0 2006.224.07:40:41.88#ibcon#read 5, iclass 21, count 0 2006.224.07:40:41.88#ibcon#about to read 6, iclass 21, count 0 2006.224.07:40:41.88#ibcon#read 6, iclass 21, count 0 2006.224.07:40:41.89#ibcon#end of sib2, iclass 21, count 0 2006.224.07:40:41.89#ibcon#*after write, iclass 21, count 0 2006.224.07:40:41.89#ibcon#*before return 0, iclass 21, count 0 2006.224.07:40:41.89#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.224.07:40:41.89#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.224.07:40:41.89#ibcon#about to clear, iclass 21 cls_cnt 0 2006.224.07:40:41.89#ibcon#cleared, iclass 21 cls_cnt 0 2006.224.07:40:41.89$vc4f8/vblo=5,744.99 2006.224.07:40:41.89#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.224.07:40:41.89#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.224.07:40:41.89#ibcon#ireg 17 cls_cnt 0 2006.224.07:40:41.89#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.224.07:40:41.89#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.224.07:40:41.89#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.224.07:40:41.89#ibcon#enter wrdev, iclass 24, count 0 2006.224.07:40:41.89#ibcon#first serial, iclass 24, count 0 2006.224.07:40:41.89#ibcon#enter sib2, iclass 24, count 0 2006.224.07:40:41.89#ibcon#flushed, iclass 24, count 0 2006.224.07:40:41.89#ibcon#about to write, iclass 24, count 0 2006.224.07:40:41.89#ibcon#wrote, iclass 24, count 0 2006.224.07:40:41.89#ibcon#about to read 3, iclass 24, count 0 2006.224.07:40:41.90#ibcon#read 3, iclass 24, count 0 2006.224.07:40:41.90#ibcon#about to read 4, iclass 24, count 0 2006.224.07:40:41.90#ibcon#read 4, iclass 24, count 0 2006.224.07:40:41.90#ibcon#about to read 5, iclass 24, count 0 2006.224.07:40:41.90#ibcon#read 5, iclass 24, count 0 2006.224.07:40:41.91#ibcon#about to read 6, iclass 24, count 0 2006.224.07:40:41.91#ibcon#read 6, iclass 24, count 0 2006.224.07:40:41.91#ibcon#end of sib2, iclass 24, count 0 2006.224.07:40:41.91#ibcon#*mode == 0, iclass 24, count 0 2006.224.07:40:41.91#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.224.07:40:41.91#ibcon#[28=FRQ=05,744.99\r\n] 2006.224.07:40:41.91#ibcon#*before write, iclass 24, count 0 2006.224.07:40:41.91#ibcon#enter sib2, iclass 24, count 0 2006.224.07:40:41.91#ibcon#flushed, iclass 24, count 0 2006.224.07:40:41.91#ibcon#about to write, iclass 24, count 0 2006.224.07:40:41.91#ibcon#wrote, iclass 24, count 0 2006.224.07:40:41.91#ibcon#about to read 3, iclass 24, count 0 2006.224.07:40:41.91#abcon#<5=/04 0.4 1.6 23.431001004.4\r\n> 2006.224.07:40:41.92#abcon#{5=INTERFACE CLEAR} 2006.224.07:40:41.94#ibcon#read 3, iclass 24, count 0 2006.224.07:40:41.94#ibcon#about to read 4, iclass 24, count 0 2006.224.07:40:41.94#ibcon#read 4, iclass 24, count 0 2006.224.07:40:41.94#ibcon#about to read 5, iclass 24, count 0 2006.224.07:40:41.95#ibcon#read 5, iclass 24, count 0 2006.224.07:40:41.95#ibcon#about to read 6, iclass 24, count 0 2006.224.07:40:41.95#ibcon#read 6, iclass 24, count 0 2006.224.07:40:41.95#ibcon#end of sib2, iclass 24, count 0 2006.224.07:40:41.95#ibcon#*after write, iclass 24, count 0 2006.224.07:40:41.95#ibcon#*before return 0, iclass 24, count 0 2006.224.07:40:41.95#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.224.07:40:41.95#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.224.07:40:41.95#ibcon#about to clear, iclass 24 cls_cnt 0 2006.224.07:40:41.95#ibcon#cleared, iclass 24 cls_cnt 0 2006.224.07:40:41.95$vc4f8/vb=5,4 2006.224.07:40:41.95#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.224.07:40:41.95#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.224.07:40:41.95#ibcon#ireg 11 cls_cnt 2 2006.224.07:40:41.95#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.224.07:40:41.98#abcon#[5=S1D000X0/0*\r\n] 2006.224.07:40:42.01#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.224.07:40:42.01#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.224.07:40:42.01#ibcon#enter wrdev, iclass 28, count 2 2006.224.07:40:42.01#ibcon#first serial, iclass 28, count 2 2006.224.07:40:42.01#ibcon#enter sib2, iclass 28, count 2 2006.224.07:40:42.01#ibcon#flushed, iclass 28, count 2 2006.224.07:40:42.01#ibcon#about to write, iclass 28, count 2 2006.224.07:40:42.01#ibcon#wrote, iclass 28, count 2 2006.224.07:40:42.01#ibcon#about to read 3, iclass 28, count 2 2006.224.07:40:42.02#ibcon#read 3, iclass 28, count 2 2006.224.07:40:42.02#ibcon#about to read 4, iclass 28, count 2 2006.224.07:40:42.02#ibcon#read 4, iclass 28, count 2 2006.224.07:40:42.02#ibcon#about to read 5, iclass 28, count 2 2006.224.07:40:42.02#ibcon#read 5, iclass 28, count 2 2006.224.07:40:42.03#ibcon#about to read 6, iclass 28, count 2 2006.224.07:40:42.03#ibcon#read 6, iclass 28, count 2 2006.224.07:40:42.03#ibcon#end of sib2, iclass 28, count 2 2006.224.07:40:42.03#ibcon#*mode == 0, iclass 28, count 2 2006.224.07:40:42.03#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.224.07:40:42.03#ibcon#[27=AT05-04\r\n] 2006.224.07:40:42.03#ibcon#*before write, iclass 28, count 2 2006.224.07:40:42.03#ibcon#enter sib2, iclass 28, count 2 2006.224.07:40:42.03#ibcon#flushed, iclass 28, count 2 2006.224.07:40:42.03#ibcon#about to write, iclass 28, count 2 2006.224.07:40:42.03#ibcon#wrote, iclass 28, count 2 2006.224.07:40:42.03#ibcon#about to read 3, iclass 28, count 2 2006.224.07:40:42.05#ibcon#read 3, iclass 28, count 2 2006.224.07:40:42.05#ibcon#about to read 4, iclass 28, count 2 2006.224.07:40:42.06#ibcon#read 4, iclass 28, count 2 2006.224.07:40:42.06#ibcon#about to read 5, iclass 28, count 2 2006.224.07:40:42.06#ibcon#read 5, iclass 28, count 2 2006.224.07:40:42.06#ibcon#about to read 6, iclass 28, count 2 2006.224.07:40:42.06#ibcon#read 6, iclass 28, count 2 2006.224.07:40:42.06#ibcon#end of sib2, iclass 28, count 2 2006.224.07:40:42.06#ibcon#*after write, iclass 28, count 2 2006.224.07:40:42.06#ibcon#*before return 0, iclass 28, count 2 2006.224.07:40:42.06#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.224.07:40:42.06#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.224.07:40:42.06#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.224.07:40:42.06#ibcon#ireg 7 cls_cnt 0 2006.224.07:40:42.06#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.224.07:40:42.17#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.224.07:40:42.17#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.224.07:40:42.17#ibcon#enter wrdev, iclass 28, count 0 2006.224.07:40:42.17#ibcon#first serial, iclass 28, count 0 2006.224.07:40:42.17#ibcon#enter sib2, iclass 28, count 0 2006.224.07:40:42.17#ibcon#flushed, iclass 28, count 0 2006.224.07:40:42.17#ibcon#about to write, iclass 28, count 0 2006.224.07:40:42.18#ibcon#wrote, iclass 28, count 0 2006.224.07:40:42.18#ibcon#about to read 3, iclass 28, count 0 2006.224.07:40:42.19#ibcon#read 3, iclass 28, count 0 2006.224.07:40:42.19#ibcon#about to read 4, iclass 28, count 0 2006.224.07:40:42.19#ibcon#read 4, iclass 28, count 0 2006.224.07:40:42.19#ibcon#about to read 5, iclass 28, count 0 2006.224.07:40:42.19#ibcon#read 5, iclass 28, count 0 2006.224.07:40:42.19#ibcon#about to read 6, iclass 28, count 0 2006.224.07:40:42.20#ibcon#read 6, iclass 28, count 0 2006.224.07:40:42.20#ibcon#end of sib2, iclass 28, count 0 2006.224.07:40:42.20#ibcon#*mode == 0, iclass 28, count 0 2006.224.07:40:42.20#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.224.07:40:42.20#ibcon#[27=USB\r\n] 2006.224.07:40:42.20#ibcon#*before write, iclass 28, count 0 2006.224.07:40:42.20#ibcon#enter sib2, iclass 28, count 0 2006.224.07:40:42.20#ibcon#flushed, iclass 28, count 0 2006.224.07:40:42.20#ibcon#about to write, iclass 28, count 0 2006.224.07:40:42.20#ibcon#wrote, iclass 28, count 0 2006.224.07:40:42.20#ibcon#about to read 3, iclass 28, count 0 2006.224.07:40:42.22#ibcon#read 3, iclass 28, count 0 2006.224.07:40:42.22#ibcon#about to read 4, iclass 28, count 0 2006.224.07:40:42.23#ibcon#read 4, iclass 28, count 0 2006.224.07:40:42.23#ibcon#about to read 5, iclass 28, count 0 2006.224.07:40:42.23#ibcon#read 5, iclass 28, count 0 2006.224.07:40:42.23#ibcon#about to read 6, iclass 28, count 0 2006.224.07:40:42.23#ibcon#read 6, iclass 28, count 0 2006.224.07:40:42.23#ibcon#end of sib2, iclass 28, count 0 2006.224.07:40:42.23#ibcon#*after write, iclass 28, count 0 2006.224.07:40:42.23#ibcon#*before return 0, iclass 28, count 0 2006.224.07:40:42.23#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.224.07:40:42.23#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.224.07:40:42.23#ibcon#about to clear, iclass 28 cls_cnt 0 2006.224.07:40:42.23#ibcon#cleared, iclass 28 cls_cnt 0 2006.224.07:40:42.23$vc4f8/vblo=6,752.99 2006.224.07:40:42.23#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.224.07:40:42.23#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.224.07:40:42.23#ibcon#ireg 17 cls_cnt 0 2006.224.07:40:42.23#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.224.07:40:42.23#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.224.07:40:42.23#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.224.07:40:42.23#ibcon#enter wrdev, iclass 31, count 0 2006.224.07:40:42.23#ibcon#first serial, iclass 31, count 0 2006.224.07:40:42.23#ibcon#enter sib2, iclass 31, count 0 2006.224.07:40:42.23#ibcon#flushed, iclass 31, count 0 2006.224.07:40:42.23#ibcon#about to write, iclass 31, count 0 2006.224.07:40:42.23#ibcon#wrote, iclass 31, count 0 2006.224.07:40:42.23#ibcon#about to read 3, iclass 31, count 0 2006.224.07:40:42.24#ibcon#read 3, iclass 31, count 0 2006.224.07:40:42.24#ibcon#about to read 4, iclass 31, count 0 2006.224.07:40:42.24#ibcon#read 4, iclass 31, count 0 2006.224.07:40:42.24#ibcon#about to read 5, iclass 31, count 0 2006.224.07:40:42.25#ibcon#read 5, iclass 31, count 0 2006.224.07:40:42.25#ibcon#about to read 6, iclass 31, count 0 2006.224.07:40:42.25#ibcon#read 6, iclass 31, count 0 2006.224.07:40:42.25#ibcon#end of sib2, iclass 31, count 0 2006.224.07:40:42.25#ibcon#*mode == 0, iclass 31, count 0 2006.224.07:40:42.25#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.224.07:40:42.25#ibcon#[28=FRQ=06,752.99\r\n] 2006.224.07:40:42.25#ibcon#*before write, iclass 31, count 0 2006.224.07:40:42.25#ibcon#enter sib2, iclass 31, count 0 2006.224.07:40:42.25#ibcon#flushed, iclass 31, count 0 2006.224.07:40:42.25#ibcon#about to write, iclass 31, count 0 2006.224.07:40:42.25#ibcon#wrote, iclass 31, count 0 2006.224.07:40:42.25#ibcon#about to read 3, iclass 31, count 0 2006.224.07:40:42.28#ibcon#read 3, iclass 31, count 0 2006.224.07:40:42.28#ibcon#about to read 4, iclass 31, count 0 2006.224.07:40:42.29#ibcon#read 4, iclass 31, count 0 2006.224.07:40:42.29#ibcon#about to read 5, iclass 31, count 0 2006.224.07:40:42.29#ibcon#read 5, iclass 31, count 0 2006.224.07:40:42.29#ibcon#about to read 6, iclass 31, count 0 2006.224.07:40:42.29#ibcon#read 6, iclass 31, count 0 2006.224.07:40:42.29#ibcon#end of sib2, iclass 31, count 0 2006.224.07:40:42.29#ibcon#*after write, iclass 31, count 0 2006.224.07:40:42.29#ibcon#*before return 0, iclass 31, count 0 2006.224.07:40:42.29#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.224.07:40:42.29#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.224.07:40:42.29#ibcon#about to clear, iclass 31 cls_cnt 0 2006.224.07:40:42.29#ibcon#cleared, iclass 31 cls_cnt 0 2006.224.07:40:42.29$vc4f8/vb=6,4 2006.224.07:40:42.29#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.224.07:40:42.29#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.224.07:40:42.29#ibcon#ireg 11 cls_cnt 2 2006.224.07:40:42.29#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.224.07:40:42.34#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.224.07:40:42.34#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.224.07:40:42.34#ibcon#enter wrdev, iclass 33, count 2 2006.224.07:40:42.34#ibcon#first serial, iclass 33, count 2 2006.224.07:40:42.34#ibcon#enter sib2, iclass 33, count 2 2006.224.07:40:42.34#ibcon#flushed, iclass 33, count 2 2006.224.07:40:42.35#ibcon#about to write, iclass 33, count 2 2006.224.07:40:42.35#ibcon#wrote, iclass 33, count 2 2006.224.07:40:42.35#ibcon#about to read 3, iclass 33, count 2 2006.224.07:40:42.36#ibcon#read 3, iclass 33, count 2 2006.224.07:40:42.36#ibcon#about to read 4, iclass 33, count 2 2006.224.07:40:42.36#ibcon#read 4, iclass 33, count 2 2006.224.07:40:42.36#ibcon#about to read 5, iclass 33, count 2 2006.224.07:40:42.37#ibcon#read 5, iclass 33, count 2 2006.224.07:40:42.37#ibcon#about to read 6, iclass 33, count 2 2006.224.07:40:42.37#ibcon#read 6, iclass 33, count 2 2006.224.07:40:42.37#ibcon#end of sib2, iclass 33, count 2 2006.224.07:40:42.37#ibcon#*mode == 0, iclass 33, count 2 2006.224.07:40:42.37#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.224.07:40:42.37#ibcon#[27=AT06-04\r\n] 2006.224.07:40:42.37#ibcon#*before write, iclass 33, count 2 2006.224.07:40:42.37#ibcon#enter sib2, iclass 33, count 2 2006.224.07:40:42.37#ibcon#flushed, iclass 33, count 2 2006.224.07:40:42.37#ibcon#about to write, iclass 33, count 2 2006.224.07:40:42.37#ibcon#wrote, iclass 33, count 2 2006.224.07:40:42.37#ibcon#about to read 3, iclass 33, count 2 2006.224.07:40:42.39#ibcon#read 3, iclass 33, count 2 2006.224.07:40:42.39#ibcon#about to read 4, iclass 33, count 2 2006.224.07:40:42.39#ibcon#read 4, iclass 33, count 2 2006.224.07:40:42.39#ibcon#about to read 5, iclass 33, count 2 2006.224.07:40:42.39#ibcon#read 5, iclass 33, count 2 2006.224.07:40:42.40#ibcon#about to read 6, iclass 33, count 2 2006.224.07:40:42.40#ibcon#read 6, iclass 33, count 2 2006.224.07:40:42.40#ibcon#end of sib2, iclass 33, count 2 2006.224.07:40:42.40#ibcon#*after write, iclass 33, count 2 2006.224.07:40:42.40#ibcon#*before return 0, iclass 33, count 2 2006.224.07:40:42.40#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.224.07:40:42.40#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.224.07:40:42.40#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.224.07:40:42.40#ibcon#ireg 7 cls_cnt 0 2006.224.07:40:42.40#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.224.07:40:42.51#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.224.07:40:42.51#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.224.07:40:42.51#ibcon#enter wrdev, iclass 33, count 0 2006.224.07:40:42.51#ibcon#first serial, iclass 33, count 0 2006.224.07:40:42.51#ibcon#enter sib2, iclass 33, count 0 2006.224.07:40:42.51#ibcon#flushed, iclass 33, count 0 2006.224.07:40:42.52#ibcon#about to write, iclass 33, count 0 2006.224.07:40:42.52#ibcon#wrote, iclass 33, count 0 2006.224.07:40:42.52#ibcon#about to read 3, iclass 33, count 0 2006.224.07:40:42.53#ibcon#read 3, iclass 33, count 0 2006.224.07:40:42.53#ibcon#about to read 4, iclass 33, count 0 2006.224.07:40:42.53#ibcon#read 4, iclass 33, count 0 2006.224.07:40:42.53#ibcon#about to read 5, iclass 33, count 0 2006.224.07:40:42.53#ibcon#read 5, iclass 33, count 0 2006.224.07:40:42.54#ibcon#about to read 6, iclass 33, count 0 2006.224.07:40:42.54#ibcon#read 6, iclass 33, count 0 2006.224.07:40:42.54#ibcon#end of sib2, iclass 33, count 0 2006.224.07:40:42.54#ibcon#*mode == 0, iclass 33, count 0 2006.224.07:40:42.54#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.224.07:40:42.54#ibcon#[27=USB\r\n] 2006.224.07:40:42.54#ibcon#*before write, iclass 33, count 0 2006.224.07:40:42.54#ibcon#enter sib2, iclass 33, count 0 2006.224.07:40:42.54#ibcon#flushed, iclass 33, count 0 2006.224.07:40:42.54#ibcon#about to write, iclass 33, count 0 2006.224.07:40:42.54#ibcon#wrote, iclass 33, count 0 2006.224.07:40:42.54#ibcon#about to read 3, iclass 33, count 0 2006.224.07:40:42.56#ibcon#read 3, iclass 33, count 0 2006.224.07:40:42.56#ibcon#about to read 4, iclass 33, count 0 2006.224.07:40:42.56#ibcon#read 4, iclass 33, count 0 2006.224.07:40:42.56#ibcon#about to read 5, iclass 33, count 0 2006.224.07:40:42.56#ibcon#read 5, iclass 33, count 0 2006.224.07:40:42.57#ibcon#about to read 6, iclass 33, count 0 2006.224.07:40:42.57#ibcon#read 6, iclass 33, count 0 2006.224.07:40:42.57#ibcon#end of sib2, iclass 33, count 0 2006.224.07:40:42.57#ibcon#*after write, iclass 33, count 0 2006.224.07:40:42.57#ibcon#*before return 0, iclass 33, count 0 2006.224.07:40:42.57#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.224.07:40:42.57#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.224.07:40:42.57#ibcon#about to clear, iclass 33 cls_cnt 0 2006.224.07:40:42.57#ibcon#cleared, iclass 33 cls_cnt 0 2006.224.07:40:42.57$vc4f8/vabw=wide 2006.224.07:40:42.57#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.224.07:40:42.57#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.224.07:40:42.57#ibcon#ireg 8 cls_cnt 0 2006.224.07:40:42.57#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.224.07:40:42.57#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.224.07:40:42.57#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.224.07:40:42.57#ibcon#enter wrdev, iclass 35, count 0 2006.224.07:40:42.57#ibcon#first serial, iclass 35, count 0 2006.224.07:40:42.57#ibcon#enter sib2, iclass 35, count 0 2006.224.07:40:42.57#ibcon#flushed, iclass 35, count 0 2006.224.07:40:42.57#ibcon#about to write, iclass 35, count 0 2006.224.07:40:42.57#ibcon#wrote, iclass 35, count 0 2006.224.07:40:42.57#ibcon#about to read 3, iclass 35, count 0 2006.224.07:40:42.58#ibcon#read 3, iclass 35, count 0 2006.224.07:40:42.58#ibcon#about to read 4, iclass 35, count 0 2006.224.07:40:42.58#ibcon#read 4, iclass 35, count 0 2006.224.07:40:42.58#ibcon#about to read 5, iclass 35, count 0 2006.224.07:40:42.58#ibcon#read 5, iclass 35, count 0 2006.224.07:40:42.59#ibcon#about to read 6, iclass 35, count 0 2006.224.07:40:42.59#ibcon#read 6, iclass 35, count 0 2006.224.07:40:42.59#ibcon#end of sib2, iclass 35, count 0 2006.224.07:40:42.59#ibcon#*mode == 0, iclass 35, count 0 2006.224.07:40:42.59#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.224.07:40:42.59#ibcon#[25=BW32\r\n] 2006.224.07:40:42.59#ibcon#*before write, iclass 35, count 0 2006.224.07:40:42.59#ibcon#enter sib2, iclass 35, count 0 2006.224.07:40:42.59#ibcon#flushed, iclass 35, count 0 2006.224.07:40:42.59#ibcon#about to write, iclass 35, count 0 2006.224.07:40:42.59#ibcon#wrote, iclass 35, count 0 2006.224.07:40:42.59#ibcon#about to read 3, iclass 35, count 0 2006.224.07:40:42.61#ibcon#read 3, iclass 35, count 0 2006.224.07:40:42.61#ibcon#about to read 4, iclass 35, count 0 2006.224.07:40:42.61#ibcon#read 4, iclass 35, count 0 2006.224.07:40:42.61#ibcon#about to read 5, iclass 35, count 0 2006.224.07:40:42.61#ibcon#read 5, iclass 35, count 0 2006.224.07:40:42.62#ibcon#about to read 6, iclass 35, count 0 2006.224.07:40:42.62#ibcon#read 6, iclass 35, count 0 2006.224.07:40:42.62#ibcon#end of sib2, iclass 35, count 0 2006.224.07:40:42.62#ibcon#*after write, iclass 35, count 0 2006.224.07:40:42.62#ibcon#*before return 0, iclass 35, count 0 2006.224.07:40:42.62#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.224.07:40:42.62#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.224.07:40:42.62#ibcon#about to clear, iclass 35 cls_cnt 0 2006.224.07:40:42.62#ibcon#cleared, iclass 35 cls_cnt 0 2006.224.07:40:42.62$vc4f8/vbbw=wide 2006.224.07:40:42.62#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.224.07:40:42.62#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.224.07:40:42.62#ibcon#ireg 8 cls_cnt 0 2006.224.07:40:42.62#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.224.07:40:42.68#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.224.07:40:42.68#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.224.07:40:42.68#ibcon#enter wrdev, iclass 37, count 0 2006.224.07:40:42.68#ibcon#first serial, iclass 37, count 0 2006.224.07:40:42.68#ibcon#enter sib2, iclass 37, count 0 2006.224.07:40:42.68#ibcon#flushed, iclass 37, count 0 2006.224.07:40:42.69#ibcon#about to write, iclass 37, count 0 2006.224.07:40:42.69#ibcon#wrote, iclass 37, count 0 2006.224.07:40:42.69#ibcon#about to read 3, iclass 37, count 0 2006.224.07:40:42.70#ibcon#read 3, iclass 37, count 0 2006.224.07:40:42.70#ibcon#about to read 4, iclass 37, count 0 2006.224.07:40:42.70#ibcon#read 4, iclass 37, count 0 2006.224.07:40:42.70#ibcon#about to read 5, iclass 37, count 0 2006.224.07:40:42.71#ibcon#read 5, iclass 37, count 0 2006.224.07:40:42.71#ibcon#about to read 6, iclass 37, count 0 2006.224.07:40:42.71#ibcon#read 6, iclass 37, count 0 2006.224.07:40:42.71#ibcon#end of sib2, iclass 37, count 0 2006.224.07:40:42.71#ibcon#*mode == 0, iclass 37, count 0 2006.224.07:40:42.71#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.224.07:40:42.71#ibcon#[27=BW32\r\n] 2006.224.07:40:42.71#ibcon#*before write, iclass 37, count 0 2006.224.07:40:42.71#ibcon#enter sib2, iclass 37, count 0 2006.224.07:40:42.71#ibcon#flushed, iclass 37, count 0 2006.224.07:40:42.71#ibcon#about to write, iclass 37, count 0 2006.224.07:40:42.71#ibcon#wrote, iclass 37, count 0 2006.224.07:40:42.71#ibcon#about to read 3, iclass 37, count 0 2006.224.07:40:42.73#ibcon#read 3, iclass 37, count 0 2006.224.07:40:42.73#ibcon#about to read 4, iclass 37, count 0 2006.224.07:40:42.73#ibcon#read 4, iclass 37, count 0 2006.224.07:40:42.74#ibcon#about to read 5, iclass 37, count 0 2006.224.07:40:42.74#ibcon#read 5, iclass 37, count 0 2006.224.07:40:42.74#ibcon#about to read 6, iclass 37, count 0 2006.224.07:40:42.74#ibcon#read 6, iclass 37, count 0 2006.224.07:40:42.74#ibcon#end of sib2, iclass 37, count 0 2006.224.07:40:42.74#ibcon#*after write, iclass 37, count 0 2006.224.07:40:42.74#ibcon#*before return 0, iclass 37, count 0 2006.224.07:40:42.74#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.224.07:40:42.74#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.224.07:40:42.74#ibcon#about to clear, iclass 37 cls_cnt 0 2006.224.07:40:42.74#ibcon#cleared, iclass 37 cls_cnt 0 2006.224.07:40:42.74$4f8m12a/ifd4f 2006.224.07:40:42.74$ifd4f/lo= 2006.224.07:40:42.74$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.224.07:40:42.74$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.224.07:40:42.74$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.224.07:40:42.74$ifd4f/patch= 2006.224.07:40:42.74$ifd4f/patch=lo1,a1,a2,a3,a4 2006.224.07:40:42.74$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.224.07:40:42.74$ifd4f/patch=lo3,a5,a6,a7,a8 2006.224.07:40:42.74$4f8m12a/"form=m,16.000,1:2 2006.224.07:40:42.74$4f8m12a/"tpicd 2006.224.07:40:42.74$4f8m12a/echo=off 2006.224.07:40:42.74$4f8m12a/xlog=off 2006.224.07:40:42.74:!2006.224.07:41:30 2006.224.07:41:09.14#trakl#Source acquired 2006.224.07:41:09.15#flagr#flagr/antenna,acquired 2006.224.07:41:30.02:preob 2006.224.07:41:31.15/onsource/TRACKING 2006.224.07:41:31.15:!2006.224.07:41:40 2006.224.07:41:40.02:data_valid=on 2006.224.07:41:40.02:midob 2006.224.07:41:41.15/onsource/TRACKING 2006.224.07:41:41.15/wx/23.44,1004.4,100 2006.224.07:41:41.25/cable/+6.4341E-03 2006.224.07:41:42.34/va/01,08,usb,yes,56,59 2006.224.07:41:42.34/va/02,07,usb,yes,57,60 2006.224.07:41:42.34/va/03,06,usb,yes,61,61 2006.224.07:41:42.34/va/04,07,usb,yes,59,64 2006.224.07:41:42.34/va/05,07,usb,yes,69,73 2006.224.07:41:42.34/va/06,06,usb,yes,69,68 2006.224.07:41:42.34/va/07,06,usb,yes,70,69 2006.224.07:41:42.34/va/08,07,usb,yes,66,65 2006.224.07:41:42.57/valo/01,532.99,yes,locked 2006.224.07:41:42.57/valo/02,572.99,yes,locked 2006.224.07:41:42.57/valo/03,672.99,yes,locked 2006.224.07:41:42.57/valo/04,832.99,yes,locked 2006.224.07:41:42.57/valo/05,652.99,yes,locked 2006.224.07:41:42.57/valo/06,772.99,yes,locked 2006.224.07:41:42.57/valo/07,832.99,yes,locked 2006.224.07:41:42.57/valo/08,852.99,yes,locked 2006.224.07:41:43.66/vb/01,04,usb,yes,35,33 2006.224.07:41:43.66/vb/02,04,usb,yes,37,38 2006.224.07:41:43.66/vb/03,04,usb,yes,33,37 2006.224.07:41:43.66/vb/04,04,usb,yes,34,34 2006.224.07:41:43.66/vb/05,04,usb,yes,32,37 2006.224.07:41:43.66/vb/06,04,usb,yes,33,36 2006.224.07:41:43.66/vb/07,04,usb,yes,36,36 2006.224.07:41:43.66/vb/08,04,usb,yes,33,37 2006.224.07:41:43.90/vblo/01,632.99,yes,locked 2006.224.07:41:43.90/vblo/02,640.99,yes,locked 2006.224.07:41:43.90/vblo/03,656.99,yes,locked 2006.224.07:41:43.90/vblo/04,712.99,yes,locked 2006.224.07:41:43.90/vblo/05,744.99,yes,locked 2006.224.07:41:43.90/vblo/06,752.99,yes,locked 2006.224.07:41:43.90/vblo/07,734.99,yes,locked 2006.224.07:41:43.90/vblo/08,744.99,yes,locked 2006.224.07:41:44.05/vabw/8 2006.224.07:41:44.20/vbbw/8 2006.224.07:41:44.29/xfe/off,on,14.7 2006.224.07:41:44.68/ifatt/23,28,28,28 2006.224.07:41:45.07/fmout-gps/S +4.31E-07 2006.224.07:41:45.12:!2006.224.07:42:40 2006.224.07:42:40.02:data_valid=off 2006.224.07:42:40.02:postob 2006.224.07:42:40.13/cable/+6.4347E-03 2006.224.07:42:40.14/wx/23.46,1004.4,100 2006.224.07:42:41.07/fmout-gps/S +4.30E-07 2006.224.07:42:41.08:scan_name=224-0743,k06224,60 2006.224.07:42:41.08:source=1300+580,130252.47,574837.6,2000.0,ccw 2006.224.07:42:42.15#flagr#flagr/antenna,new-source 2006.224.07:42:42.15:checkk5 2006.224.07:42:42.53/chk_autoobs//k5ts1/ autoobs is running! 2006.224.07:42:42.90/chk_autoobs//k5ts2/ autoobs is running! 2006.224.07:42:43.28/chk_autoobs//k5ts3/ autoobs is running! 2006.224.07:42:43.64/chk_autoobs//k5ts4/ autoobs is running! 2006.224.07:42:44.01/chk_obsdata//k5ts1/T2240741??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.07:42:44.37/chk_obsdata//k5ts2/T2240741??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.07:42:44.73/chk_obsdata//k5ts3/T2240741??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.07:42:45.10/chk_obsdata//k5ts4/T2240741??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.07:42:45.79/k5log//k5ts1_log_newline 2006.224.07:42:46.47/k5log//k5ts2_log_newline 2006.224.07:42:47.15/k5log//k5ts3_log_newline 2006.224.07:42:47.84/k5log//k5ts4_log_newline 2006.224.07:42:47.86/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.224.07:42:47.86:4f8m12a=1 2006.224.07:42:47.86$4f8m12a/echo=on 2006.224.07:42:47.86$4f8m12a/pcalon 2006.224.07:42:47.86$pcalon/"no phase cal control is implemented here 2006.224.07:42:47.86$4f8m12a/"tpicd=stop 2006.224.07:42:47.86$4f8m12a/vc4f8 2006.224.07:42:47.86$vc4f8/valo=1,532.99 2006.224.07:42:47.87#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.224.07:42:47.87#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.224.07:42:47.87#ibcon#ireg 17 cls_cnt 0 2006.224.07:42:47.87#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.224.07:42:47.87#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.224.07:42:47.87#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.224.07:42:47.87#ibcon#enter wrdev, iclass 16, count 0 2006.224.07:42:47.87#ibcon#first serial, iclass 16, count 0 2006.224.07:42:47.87#ibcon#enter sib2, iclass 16, count 0 2006.224.07:42:47.87#ibcon#flushed, iclass 16, count 0 2006.224.07:42:47.87#ibcon#about to write, iclass 16, count 0 2006.224.07:42:47.87#ibcon#wrote, iclass 16, count 0 2006.224.07:42:47.87#ibcon#about to read 3, iclass 16, count 0 2006.224.07:42:47.90#ibcon#read 3, iclass 16, count 0 2006.224.07:42:47.90#ibcon#about to read 4, iclass 16, count 0 2006.224.07:42:47.90#ibcon#read 4, iclass 16, count 0 2006.224.07:42:47.90#ibcon#about to read 5, iclass 16, count 0 2006.224.07:42:47.90#ibcon#read 5, iclass 16, count 0 2006.224.07:42:47.90#ibcon#about to read 6, iclass 16, count 0 2006.224.07:42:47.90#ibcon#read 6, iclass 16, count 0 2006.224.07:42:47.90#ibcon#end of sib2, iclass 16, count 0 2006.224.07:42:47.90#ibcon#*mode == 0, iclass 16, count 0 2006.224.07:42:47.90#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.224.07:42:47.90#ibcon#[26=FRQ=01,532.99\r\n] 2006.224.07:42:47.90#ibcon#*before write, iclass 16, count 0 2006.224.07:42:47.90#ibcon#enter sib2, iclass 16, count 0 2006.224.07:42:47.90#ibcon#flushed, iclass 16, count 0 2006.224.07:42:47.90#ibcon#about to write, iclass 16, count 0 2006.224.07:42:47.90#ibcon#wrote, iclass 16, count 0 2006.224.07:42:47.90#ibcon#about to read 3, iclass 16, count 0 2006.224.07:42:47.95#ibcon#read 3, iclass 16, count 0 2006.224.07:42:47.95#ibcon#about to read 4, iclass 16, count 0 2006.224.07:42:47.95#ibcon#read 4, iclass 16, count 0 2006.224.07:42:47.95#ibcon#about to read 5, iclass 16, count 0 2006.224.07:42:47.95#ibcon#read 5, iclass 16, count 0 2006.224.07:42:47.95#ibcon#about to read 6, iclass 16, count 0 2006.224.07:42:47.95#ibcon#read 6, iclass 16, count 0 2006.224.07:42:47.95#ibcon#end of sib2, iclass 16, count 0 2006.224.07:42:47.95#ibcon#*after write, iclass 16, count 0 2006.224.07:42:47.95#ibcon#*before return 0, iclass 16, count 0 2006.224.07:42:47.95#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.224.07:42:47.95#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.224.07:42:47.95#ibcon#about to clear, iclass 16 cls_cnt 0 2006.224.07:42:47.95#ibcon#cleared, iclass 16 cls_cnt 0 2006.224.07:42:47.95$vc4f8/va=1,8 2006.224.07:42:47.96#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.224.07:42:47.96#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.224.07:42:47.96#ibcon#ireg 11 cls_cnt 2 2006.224.07:42:47.96#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.224.07:42:47.96#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.224.07:42:47.96#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.224.07:42:47.96#ibcon#enter wrdev, iclass 18, count 2 2006.224.07:42:47.96#ibcon#first serial, iclass 18, count 2 2006.224.07:42:47.96#ibcon#enter sib2, iclass 18, count 2 2006.224.07:42:47.96#ibcon#flushed, iclass 18, count 2 2006.224.07:42:47.96#ibcon#about to write, iclass 18, count 2 2006.224.07:42:47.96#ibcon#wrote, iclass 18, count 2 2006.224.07:42:47.96#ibcon#about to read 3, iclass 18, count 2 2006.224.07:42:47.98#ibcon#read 3, iclass 18, count 2 2006.224.07:42:47.98#ibcon#about to read 4, iclass 18, count 2 2006.224.07:42:47.98#ibcon#read 4, iclass 18, count 2 2006.224.07:42:47.98#ibcon#about to read 5, iclass 18, count 2 2006.224.07:42:47.98#ibcon#read 5, iclass 18, count 2 2006.224.07:42:47.98#ibcon#about to read 6, iclass 18, count 2 2006.224.07:42:47.98#ibcon#read 6, iclass 18, count 2 2006.224.07:42:47.98#ibcon#end of sib2, iclass 18, count 2 2006.224.07:42:47.98#ibcon#*mode == 0, iclass 18, count 2 2006.224.07:42:47.98#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.224.07:42:47.98#ibcon#[25=AT01-08\r\n] 2006.224.07:42:47.98#ibcon#*before write, iclass 18, count 2 2006.224.07:42:47.98#ibcon#enter sib2, iclass 18, count 2 2006.224.07:42:47.98#ibcon#flushed, iclass 18, count 2 2006.224.07:42:47.98#ibcon#about to write, iclass 18, count 2 2006.224.07:42:47.98#ibcon#wrote, iclass 18, count 2 2006.224.07:42:47.98#ibcon#about to read 3, iclass 18, count 2 2006.224.07:42:48.01#ibcon#read 3, iclass 18, count 2 2006.224.07:42:48.02#ibcon#about to read 4, iclass 18, count 2 2006.224.07:42:48.02#ibcon#read 4, iclass 18, count 2 2006.224.07:42:48.02#ibcon#about to read 5, iclass 18, count 2 2006.224.07:42:48.02#ibcon#read 5, iclass 18, count 2 2006.224.07:42:48.02#ibcon#about to read 6, iclass 18, count 2 2006.224.07:42:48.02#ibcon#read 6, iclass 18, count 2 2006.224.07:42:48.02#ibcon#end of sib2, iclass 18, count 2 2006.224.07:42:48.02#ibcon#*after write, iclass 18, count 2 2006.224.07:42:48.02#ibcon#*before return 0, iclass 18, count 2 2006.224.07:42:48.02#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.224.07:42:48.02#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.224.07:42:48.02#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.224.07:42:48.02#ibcon#ireg 7 cls_cnt 0 2006.224.07:42:48.02#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.224.07:42:48.13#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.224.07:42:48.13#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.224.07:42:48.13#ibcon#enter wrdev, iclass 18, count 0 2006.224.07:42:48.13#ibcon#first serial, iclass 18, count 0 2006.224.07:42:48.13#ibcon#enter sib2, iclass 18, count 0 2006.224.07:42:48.13#ibcon#flushed, iclass 18, count 0 2006.224.07:42:48.13#ibcon#about to write, iclass 18, count 0 2006.224.07:42:48.13#ibcon#wrote, iclass 18, count 0 2006.224.07:42:48.13#ibcon#about to read 3, iclass 18, count 0 2006.224.07:42:48.15#ibcon#read 3, iclass 18, count 0 2006.224.07:42:48.15#ibcon#about to read 4, iclass 18, count 0 2006.224.07:42:48.15#ibcon#read 4, iclass 18, count 0 2006.224.07:42:48.15#ibcon#about to read 5, iclass 18, count 0 2006.224.07:42:48.15#ibcon#read 5, iclass 18, count 0 2006.224.07:42:48.15#ibcon#about to read 6, iclass 18, count 0 2006.224.07:42:48.15#ibcon#read 6, iclass 18, count 0 2006.224.07:42:48.15#ibcon#end of sib2, iclass 18, count 0 2006.224.07:42:48.15#ibcon#*mode == 0, iclass 18, count 0 2006.224.07:42:48.15#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.224.07:42:48.15#ibcon#[25=USB\r\n] 2006.224.07:42:48.15#ibcon#*before write, iclass 18, count 0 2006.224.07:42:48.15#ibcon#enter sib2, iclass 18, count 0 2006.224.07:42:48.15#ibcon#flushed, iclass 18, count 0 2006.224.07:42:48.15#ibcon#about to write, iclass 18, count 0 2006.224.07:42:48.15#ibcon#wrote, iclass 18, count 0 2006.224.07:42:48.15#ibcon#about to read 3, iclass 18, count 0 2006.224.07:42:48.18#ibcon#read 3, iclass 18, count 0 2006.224.07:42:48.18#ibcon#about to read 4, iclass 18, count 0 2006.224.07:42:48.18#ibcon#read 4, iclass 18, count 0 2006.224.07:42:48.18#ibcon#about to read 5, iclass 18, count 0 2006.224.07:42:48.18#ibcon#read 5, iclass 18, count 0 2006.224.07:42:48.18#ibcon#about to read 6, iclass 18, count 0 2006.224.07:42:48.18#ibcon#read 6, iclass 18, count 0 2006.224.07:42:48.18#ibcon#end of sib2, iclass 18, count 0 2006.224.07:42:48.18#ibcon#*after write, iclass 18, count 0 2006.224.07:42:48.18#ibcon#*before return 0, iclass 18, count 0 2006.224.07:42:48.18#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.224.07:42:48.18#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.224.07:42:48.18#ibcon#about to clear, iclass 18 cls_cnt 0 2006.224.07:42:48.18#ibcon#cleared, iclass 18 cls_cnt 0 2006.224.07:42:48.18$vc4f8/valo=2,572.99 2006.224.07:42:48.19#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.224.07:42:48.19#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.224.07:42:48.19#ibcon#ireg 17 cls_cnt 0 2006.224.07:42:48.19#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.224.07:42:48.19#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.224.07:42:48.19#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.224.07:42:48.19#ibcon#enter wrdev, iclass 20, count 0 2006.224.07:42:48.19#ibcon#first serial, iclass 20, count 0 2006.224.07:42:48.19#ibcon#enter sib2, iclass 20, count 0 2006.224.07:42:48.19#ibcon#flushed, iclass 20, count 0 2006.224.07:42:48.19#ibcon#about to write, iclass 20, count 0 2006.224.07:42:48.19#ibcon#wrote, iclass 20, count 0 2006.224.07:42:48.19#ibcon#about to read 3, iclass 20, count 0 2006.224.07:42:48.20#ibcon#read 3, iclass 20, count 0 2006.224.07:42:48.20#ibcon#about to read 4, iclass 20, count 0 2006.224.07:42:48.20#ibcon#read 4, iclass 20, count 0 2006.224.07:42:48.20#ibcon#about to read 5, iclass 20, count 0 2006.224.07:42:48.20#ibcon#read 5, iclass 20, count 0 2006.224.07:42:48.20#ibcon#about to read 6, iclass 20, count 0 2006.224.07:42:48.20#ibcon#read 6, iclass 20, count 0 2006.224.07:42:48.20#ibcon#end of sib2, iclass 20, count 0 2006.224.07:42:48.20#ibcon#*mode == 0, iclass 20, count 0 2006.224.07:42:48.20#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.224.07:42:48.20#ibcon#[26=FRQ=02,572.99\r\n] 2006.224.07:42:48.20#ibcon#*before write, iclass 20, count 0 2006.224.07:42:48.20#ibcon#enter sib2, iclass 20, count 0 2006.224.07:42:48.20#ibcon#flushed, iclass 20, count 0 2006.224.07:42:48.20#ibcon#about to write, iclass 20, count 0 2006.224.07:42:48.20#ibcon#wrote, iclass 20, count 0 2006.224.07:42:48.20#ibcon#about to read 3, iclass 20, count 0 2006.224.07:42:48.24#ibcon#read 3, iclass 20, count 0 2006.224.07:42:48.24#ibcon#about to read 4, iclass 20, count 0 2006.224.07:42:48.24#ibcon#read 4, iclass 20, count 0 2006.224.07:42:48.24#ibcon#about to read 5, iclass 20, count 0 2006.224.07:42:48.24#ibcon#read 5, iclass 20, count 0 2006.224.07:42:48.24#ibcon#about to read 6, iclass 20, count 0 2006.224.07:42:48.24#ibcon#read 6, iclass 20, count 0 2006.224.07:42:48.24#ibcon#end of sib2, iclass 20, count 0 2006.224.07:42:48.24#ibcon#*after write, iclass 20, count 0 2006.224.07:42:48.24#ibcon#*before return 0, iclass 20, count 0 2006.224.07:42:48.24#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.224.07:42:48.24#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.224.07:42:48.24#ibcon#about to clear, iclass 20 cls_cnt 0 2006.224.07:42:48.24#ibcon#cleared, iclass 20 cls_cnt 0 2006.224.07:42:48.24$vc4f8/va=2,7 2006.224.07:42:48.25#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.224.07:42:48.25#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.224.07:42:48.25#ibcon#ireg 11 cls_cnt 2 2006.224.07:42:48.25#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.224.07:42:48.30#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.224.07:42:48.30#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.224.07:42:48.30#ibcon#enter wrdev, iclass 22, count 2 2006.224.07:42:48.30#ibcon#first serial, iclass 22, count 2 2006.224.07:42:48.30#ibcon#enter sib2, iclass 22, count 2 2006.224.07:42:48.30#ibcon#flushed, iclass 22, count 2 2006.224.07:42:48.30#ibcon#about to write, iclass 22, count 2 2006.224.07:42:48.30#ibcon#wrote, iclass 22, count 2 2006.224.07:42:48.30#ibcon#about to read 3, iclass 22, count 2 2006.224.07:42:48.31#ibcon#read 3, iclass 22, count 2 2006.224.07:42:48.31#ibcon#about to read 4, iclass 22, count 2 2006.224.07:42:48.31#ibcon#read 4, iclass 22, count 2 2006.224.07:42:48.31#ibcon#about to read 5, iclass 22, count 2 2006.224.07:42:48.31#ibcon#read 5, iclass 22, count 2 2006.224.07:42:48.31#ibcon#about to read 6, iclass 22, count 2 2006.224.07:42:48.31#ibcon#read 6, iclass 22, count 2 2006.224.07:42:48.31#ibcon#end of sib2, iclass 22, count 2 2006.224.07:42:48.31#ibcon#*mode == 0, iclass 22, count 2 2006.224.07:42:48.31#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.224.07:42:48.31#ibcon#[25=AT02-07\r\n] 2006.224.07:42:48.31#ibcon#*before write, iclass 22, count 2 2006.224.07:42:48.31#ibcon#enter sib2, iclass 22, count 2 2006.224.07:42:48.31#ibcon#flushed, iclass 22, count 2 2006.224.07:42:48.31#ibcon#about to write, iclass 22, count 2 2006.224.07:42:48.31#ibcon#wrote, iclass 22, count 2 2006.224.07:42:48.31#ibcon#about to read 3, iclass 22, count 2 2006.224.07:42:48.34#ibcon#read 3, iclass 22, count 2 2006.224.07:42:48.34#ibcon#about to read 4, iclass 22, count 2 2006.224.07:42:48.34#ibcon#read 4, iclass 22, count 2 2006.224.07:42:48.34#ibcon#about to read 5, iclass 22, count 2 2006.224.07:42:48.34#ibcon#read 5, iclass 22, count 2 2006.224.07:42:48.34#ibcon#about to read 6, iclass 22, count 2 2006.224.07:42:48.34#ibcon#read 6, iclass 22, count 2 2006.224.07:42:48.34#ibcon#end of sib2, iclass 22, count 2 2006.224.07:42:48.34#ibcon#*after write, iclass 22, count 2 2006.224.07:42:48.34#ibcon#*before return 0, iclass 22, count 2 2006.224.07:42:48.34#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.224.07:42:48.34#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.224.07:42:48.34#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.224.07:42:48.34#ibcon#ireg 7 cls_cnt 0 2006.224.07:42:48.34#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.224.07:42:48.46#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.224.07:42:48.46#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.224.07:42:48.46#ibcon#enter wrdev, iclass 22, count 0 2006.224.07:42:48.46#ibcon#first serial, iclass 22, count 0 2006.224.07:42:48.46#ibcon#enter sib2, iclass 22, count 0 2006.224.07:42:48.46#ibcon#flushed, iclass 22, count 0 2006.224.07:42:48.46#ibcon#about to write, iclass 22, count 0 2006.224.07:42:48.46#ibcon#wrote, iclass 22, count 0 2006.224.07:42:48.46#ibcon#about to read 3, iclass 22, count 0 2006.224.07:42:48.48#ibcon#read 3, iclass 22, count 0 2006.224.07:42:48.48#ibcon#about to read 4, iclass 22, count 0 2006.224.07:42:48.48#ibcon#read 4, iclass 22, count 0 2006.224.07:42:48.48#ibcon#about to read 5, iclass 22, count 0 2006.224.07:42:48.48#ibcon#read 5, iclass 22, count 0 2006.224.07:42:48.48#ibcon#about to read 6, iclass 22, count 0 2006.224.07:42:48.48#ibcon#read 6, iclass 22, count 0 2006.224.07:42:48.48#ibcon#end of sib2, iclass 22, count 0 2006.224.07:42:48.48#ibcon#*mode == 0, iclass 22, count 0 2006.224.07:42:48.48#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.224.07:42:48.48#ibcon#[25=USB\r\n] 2006.224.07:42:48.48#ibcon#*before write, iclass 22, count 0 2006.224.07:42:48.48#ibcon#enter sib2, iclass 22, count 0 2006.224.07:42:48.48#ibcon#flushed, iclass 22, count 0 2006.224.07:42:48.48#ibcon#about to write, iclass 22, count 0 2006.224.07:42:48.48#ibcon#wrote, iclass 22, count 0 2006.224.07:42:48.48#ibcon#about to read 3, iclass 22, count 0 2006.224.07:42:48.51#ibcon#read 3, iclass 22, count 0 2006.224.07:42:48.51#ibcon#about to read 4, iclass 22, count 0 2006.224.07:42:48.51#ibcon#read 4, iclass 22, count 0 2006.224.07:42:48.51#ibcon#about to read 5, iclass 22, count 0 2006.224.07:42:48.51#ibcon#read 5, iclass 22, count 0 2006.224.07:42:48.51#ibcon#about to read 6, iclass 22, count 0 2006.224.07:42:48.51#ibcon#read 6, iclass 22, count 0 2006.224.07:42:48.51#ibcon#end of sib2, iclass 22, count 0 2006.224.07:42:48.51#ibcon#*after write, iclass 22, count 0 2006.224.07:42:48.51#ibcon#*before return 0, iclass 22, count 0 2006.224.07:42:48.51#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.224.07:42:48.51#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.224.07:42:48.51#ibcon#about to clear, iclass 22 cls_cnt 0 2006.224.07:42:48.51#ibcon#cleared, iclass 22 cls_cnt 0 2006.224.07:42:48.51$vc4f8/valo=3,672.99 2006.224.07:42:48.52#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.224.07:42:48.52#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.224.07:42:48.52#ibcon#ireg 17 cls_cnt 0 2006.224.07:42:48.52#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.224.07:42:48.52#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.224.07:42:48.52#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.224.07:42:48.52#ibcon#enter wrdev, iclass 24, count 0 2006.224.07:42:48.52#ibcon#first serial, iclass 24, count 0 2006.224.07:42:48.52#ibcon#enter sib2, iclass 24, count 0 2006.224.07:42:48.52#ibcon#flushed, iclass 24, count 0 2006.224.07:42:48.52#ibcon#about to write, iclass 24, count 0 2006.224.07:42:48.52#ibcon#wrote, iclass 24, count 0 2006.224.07:42:48.52#ibcon#about to read 3, iclass 24, count 0 2006.224.07:42:48.53#ibcon#read 3, iclass 24, count 0 2006.224.07:42:48.53#ibcon#about to read 4, iclass 24, count 0 2006.224.07:42:48.53#ibcon#read 4, iclass 24, count 0 2006.224.07:42:48.53#ibcon#about to read 5, iclass 24, count 0 2006.224.07:42:48.53#ibcon#read 5, iclass 24, count 0 2006.224.07:42:48.53#ibcon#about to read 6, iclass 24, count 0 2006.224.07:42:48.53#ibcon#read 6, iclass 24, count 0 2006.224.07:42:48.53#ibcon#end of sib2, iclass 24, count 0 2006.224.07:42:48.53#ibcon#*mode == 0, iclass 24, count 0 2006.224.07:42:48.53#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.224.07:42:48.53#ibcon#[26=FRQ=03,672.99\r\n] 2006.224.07:42:48.53#ibcon#*before write, iclass 24, count 0 2006.224.07:42:48.53#ibcon#enter sib2, iclass 24, count 0 2006.224.07:42:48.53#ibcon#flushed, iclass 24, count 0 2006.224.07:42:48.53#ibcon#about to write, iclass 24, count 0 2006.224.07:42:48.53#ibcon#wrote, iclass 24, count 0 2006.224.07:42:48.53#ibcon#about to read 3, iclass 24, count 0 2006.224.07:42:48.57#ibcon#read 3, iclass 24, count 0 2006.224.07:42:48.57#ibcon#about to read 4, iclass 24, count 0 2006.224.07:42:48.57#ibcon#read 4, iclass 24, count 0 2006.224.07:42:48.57#ibcon#about to read 5, iclass 24, count 0 2006.224.07:42:48.57#ibcon#read 5, iclass 24, count 0 2006.224.07:42:48.57#ibcon#about to read 6, iclass 24, count 0 2006.224.07:42:48.57#ibcon#read 6, iclass 24, count 0 2006.224.07:42:48.57#ibcon#end of sib2, iclass 24, count 0 2006.224.07:42:48.57#ibcon#*after write, iclass 24, count 0 2006.224.07:42:48.57#ibcon#*before return 0, iclass 24, count 0 2006.224.07:42:48.57#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.224.07:42:48.57#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.224.07:42:48.57#ibcon#about to clear, iclass 24 cls_cnt 0 2006.224.07:42:48.57#ibcon#cleared, iclass 24 cls_cnt 0 2006.224.07:42:48.57$vc4f8/va=3,6 2006.224.07:42:48.58#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.224.07:42:48.58#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.224.07:42:48.58#ibcon#ireg 11 cls_cnt 2 2006.224.07:42:48.58#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.224.07:42:48.63#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.224.07:42:48.63#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.224.07:42:48.63#ibcon#enter wrdev, iclass 26, count 2 2006.224.07:42:48.63#ibcon#first serial, iclass 26, count 2 2006.224.07:42:48.63#ibcon#enter sib2, iclass 26, count 2 2006.224.07:42:48.63#ibcon#flushed, iclass 26, count 2 2006.224.07:42:48.63#ibcon#about to write, iclass 26, count 2 2006.224.07:42:48.63#ibcon#wrote, iclass 26, count 2 2006.224.07:42:48.63#ibcon#about to read 3, iclass 26, count 2 2006.224.07:42:48.64#ibcon#read 3, iclass 26, count 2 2006.224.07:42:48.64#ibcon#about to read 4, iclass 26, count 2 2006.224.07:42:48.64#ibcon#read 4, iclass 26, count 2 2006.224.07:42:48.64#ibcon#about to read 5, iclass 26, count 2 2006.224.07:42:48.64#ibcon#read 5, iclass 26, count 2 2006.224.07:42:48.64#ibcon#about to read 6, iclass 26, count 2 2006.224.07:42:48.64#ibcon#read 6, iclass 26, count 2 2006.224.07:42:48.64#ibcon#end of sib2, iclass 26, count 2 2006.224.07:42:48.64#ibcon#*mode == 0, iclass 26, count 2 2006.224.07:42:48.64#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.224.07:42:48.64#ibcon#[25=AT03-06\r\n] 2006.224.07:42:48.64#ibcon#*before write, iclass 26, count 2 2006.224.07:42:48.64#ibcon#enter sib2, iclass 26, count 2 2006.224.07:42:48.64#ibcon#flushed, iclass 26, count 2 2006.224.07:42:48.64#ibcon#about to write, iclass 26, count 2 2006.224.07:42:48.64#ibcon#wrote, iclass 26, count 2 2006.224.07:42:48.64#ibcon#about to read 3, iclass 26, count 2 2006.224.07:42:48.67#ibcon#read 3, iclass 26, count 2 2006.224.07:42:48.67#ibcon#about to read 4, iclass 26, count 2 2006.224.07:42:48.67#ibcon#read 4, iclass 26, count 2 2006.224.07:42:48.67#ibcon#about to read 5, iclass 26, count 2 2006.224.07:42:48.67#ibcon#read 5, iclass 26, count 2 2006.224.07:42:48.67#ibcon#about to read 6, iclass 26, count 2 2006.224.07:42:48.67#ibcon#read 6, iclass 26, count 2 2006.224.07:42:48.67#ibcon#end of sib2, iclass 26, count 2 2006.224.07:42:48.67#ibcon#*after write, iclass 26, count 2 2006.224.07:42:48.67#ibcon#*before return 0, iclass 26, count 2 2006.224.07:42:48.67#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.224.07:42:48.67#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.224.07:42:48.67#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.224.07:42:48.67#ibcon#ireg 7 cls_cnt 0 2006.224.07:42:48.67#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.224.07:42:48.79#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.224.07:42:48.79#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.224.07:42:48.79#ibcon#enter wrdev, iclass 26, count 0 2006.224.07:42:48.79#ibcon#first serial, iclass 26, count 0 2006.224.07:42:48.79#ibcon#enter sib2, iclass 26, count 0 2006.224.07:42:48.79#ibcon#flushed, iclass 26, count 0 2006.224.07:42:48.79#ibcon#about to write, iclass 26, count 0 2006.224.07:42:48.79#ibcon#wrote, iclass 26, count 0 2006.224.07:42:48.79#ibcon#about to read 3, iclass 26, count 0 2006.224.07:42:48.81#ibcon#read 3, iclass 26, count 0 2006.224.07:42:48.81#ibcon#about to read 4, iclass 26, count 0 2006.224.07:42:48.81#ibcon#read 4, iclass 26, count 0 2006.224.07:42:48.81#ibcon#about to read 5, iclass 26, count 0 2006.224.07:42:48.81#ibcon#read 5, iclass 26, count 0 2006.224.07:42:48.81#ibcon#about to read 6, iclass 26, count 0 2006.224.07:42:48.81#ibcon#read 6, iclass 26, count 0 2006.224.07:42:48.81#ibcon#end of sib2, iclass 26, count 0 2006.224.07:42:48.81#ibcon#*mode == 0, iclass 26, count 0 2006.224.07:42:48.81#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.224.07:42:48.81#ibcon#[25=USB\r\n] 2006.224.07:42:48.81#ibcon#*before write, iclass 26, count 0 2006.224.07:42:48.81#ibcon#enter sib2, iclass 26, count 0 2006.224.07:42:48.81#ibcon#flushed, iclass 26, count 0 2006.224.07:42:48.81#ibcon#about to write, iclass 26, count 0 2006.224.07:42:48.81#ibcon#wrote, iclass 26, count 0 2006.224.07:42:48.81#ibcon#about to read 3, iclass 26, count 0 2006.224.07:42:48.84#ibcon#read 3, iclass 26, count 0 2006.224.07:42:48.84#ibcon#about to read 4, iclass 26, count 0 2006.224.07:42:48.84#ibcon#read 4, iclass 26, count 0 2006.224.07:42:48.84#ibcon#about to read 5, iclass 26, count 0 2006.224.07:42:48.84#ibcon#read 5, iclass 26, count 0 2006.224.07:42:48.84#ibcon#about to read 6, iclass 26, count 0 2006.224.07:42:48.84#ibcon#read 6, iclass 26, count 0 2006.224.07:42:48.84#ibcon#end of sib2, iclass 26, count 0 2006.224.07:42:48.84#ibcon#*after write, iclass 26, count 0 2006.224.07:42:48.84#ibcon#*before return 0, iclass 26, count 0 2006.224.07:42:48.84#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.224.07:42:48.84#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.224.07:42:48.84#ibcon#about to clear, iclass 26 cls_cnt 0 2006.224.07:42:48.84#ibcon#cleared, iclass 26 cls_cnt 0 2006.224.07:42:48.84$vc4f8/valo=4,832.99 2006.224.07:42:48.85#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.224.07:42:48.85#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.224.07:42:48.85#ibcon#ireg 17 cls_cnt 0 2006.224.07:42:48.85#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.224.07:42:48.85#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.224.07:42:48.85#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.224.07:42:48.85#ibcon#enter wrdev, iclass 28, count 0 2006.224.07:42:48.85#ibcon#first serial, iclass 28, count 0 2006.224.07:42:48.85#ibcon#enter sib2, iclass 28, count 0 2006.224.07:42:48.85#ibcon#flushed, iclass 28, count 0 2006.224.07:42:48.85#ibcon#about to write, iclass 28, count 0 2006.224.07:42:48.85#ibcon#wrote, iclass 28, count 0 2006.224.07:42:48.85#ibcon#about to read 3, iclass 28, count 0 2006.224.07:42:48.86#ibcon#read 3, iclass 28, count 0 2006.224.07:42:48.86#ibcon#about to read 4, iclass 28, count 0 2006.224.07:42:48.86#ibcon#read 4, iclass 28, count 0 2006.224.07:42:48.86#ibcon#about to read 5, iclass 28, count 0 2006.224.07:42:48.86#ibcon#read 5, iclass 28, count 0 2006.224.07:42:48.86#ibcon#about to read 6, iclass 28, count 0 2006.224.07:42:48.86#ibcon#read 6, iclass 28, count 0 2006.224.07:42:48.86#ibcon#end of sib2, iclass 28, count 0 2006.224.07:42:48.86#ibcon#*mode == 0, iclass 28, count 0 2006.224.07:42:48.86#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.224.07:42:48.86#ibcon#[26=FRQ=04,832.99\r\n] 2006.224.07:42:48.86#ibcon#*before write, iclass 28, count 0 2006.224.07:42:48.86#ibcon#enter sib2, iclass 28, count 0 2006.224.07:42:48.86#ibcon#flushed, iclass 28, count 0 2006.224.07:42:48.86#ibcon#about to write, iclass 28, count 0 2006.224.07:42:48.86#ibcon#wrote, iclass 28, count 0 2006.224.07:42:48.86#ibcon#about to read 3, iclass 28, count 0 2006.224.07:42:48.90#ibcon#read 3, iclass 28, count 0 2006.224.07:42:48.90#ibcon#about to read 4, iclass 28, count 0 2006.224.07:42:48.90#ibcon#read 4, iclass 28, count 0 2006.224.07:42:48.90#ibcon#about to read 5, iclass 28, count 0 2006.224.07:42:48.90#ibcon#read 5, iclass 28, count 0 2006.224.07:42:48.90#ibcon#about to read 6, iclass 28, count 0 2006.224.07:42:48.90#ibcon#read 6, iclass 28, count 0 2006.224.07:42:48.90#ibcon#end of sib2, iclass 28, count 0 2006.224.07:42:48.90#ibcon#*after write, iclass 28, count 0 2006.224.07:42:48.90#ibcon#*before return 0, iclass 28, count 0 2006.224.07:42:48.90#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.224.07:42:48.90#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.224.07:42:48.90#ibcon#about to clear, iclass 28 cls_cnt 0 2006.224.07:42:48.90#ibcon#cleared, iclass 28 cls_cnt 0 2006.224.07:42:48.90$vc4f8/va=4,7 2006.224.07:42:48.91#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.224.07:42:48.91#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.224.07:42:48.91#ibcon#ireg 11 cls_cnt 2 2006.224.07:42:48.91#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.224.07:42:48.96#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.224.07:42:48.96#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.224.07:42:48.96#ibcon#enter wrdev, iclass 30, count 2 2006.224.07:42:48.96#ibcon#first serial, iclass 30, count 2 2006.224.07:42:48.96#ibcon#enter sib2, iclass 30, count 2 2006.224.07:42:48.96#ibcon#flushed, iclass 30, count 2 2006.224.07:42:48.96#ibcon#about to write, iclass 30, count 2 2006.224.07:42:48.96#ibcon#wrote, iclass 30, count 2 2006.224.07:42:48.96#ibcon#about to read 3, iclass 30, count 2 2006.224.07:42:48.97#ibcon#read 3, iclass 30, count 2 2006.224.07:42:48.97#ibcon#about to read 4, iclass 30, count 2 2006.224.07:42:48.97#ibcon#read 4, iclass 30, count 2 2006.224.07:42:48.97#ibcon#about to read 5, iclass 30, count 2 2006.224.07:42:48.97#ibcon#read 5, iclass 30, count 2 2006.224.07:42:48.97#ibcon#about to read 6, iclass 30, count 2 2006.224.07:42:48.97#ibcon#read 6, iclass 30, count 2 2006.224.07:42:48.97#ibcon#end of sib2, iclass 30, count 2 2006.224.07:42:48.97#ibcon#*mode == 0, iclass 30, count 2 2006.224.07:42:48.97#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.224.07:42:48.97#ibcon#[25=AT04-07\r\n] 2006.224.07:42:48.97#ibcon#*before write, iclass 30, count 2 2006.224.07:42:48.97#ibcon#enter sib2, iclass 30, count 2 2006.224.07:42:48.97#ibcon#flushed, iclass 30, count 2 2006.224.07:42:48.97#ibcon#about to write, iclass 30, count 2 2006.224.07:42:48.97#ibcon#wrote, iclass 30, count 2 2006.224.07:42:48.97#ibcon#about to read 3, iclass 30, count 2 2006.224.07:42:49.00#ibcon#read 3, iclass 30, count 2 2006.224.07:42:49.00#ibcon#about to read 4, iclass 30, count 2 2006.224.07:42:49.00#ibcon#read 4, iclass 30, count 2 2006.224.07:42:49.00#ibcon#about to read 5, iclass 30, count 2 2006.224.07:42:49.00#ibcon#read 5, iclass 30, count 2 2006.224.07:42:49.00#ibcon#about to read 6, iclass 30, count 2 2006.224.07:42:49.00#ibcon#read 6, iclass 30, count 2 2006.224.07:42:49.00#ibcon#end of sib2, iclass 30, count 2 2006.224.07:42:49.00#ibcon#*after write, iclass 30, count 2 2006.224.07:42:49.00#ibcon#*before return 0, iclass 30, count 2 2006.224.07:42:49.00#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.224.07:42:49.00#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.224.07:42:49.00#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.224.07:42:49.00#ibcon#ireg 7 cls_cnt 0 2006.224.07:42:49.00#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.224.07:42:49.12#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.224.07:42:49.12#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.224.07:42:49.12#ibcon#enter wrdev, iclass 30, count 0 2006.224.07:42:49.12#ibcon#first serial, iclass 30, count 0 2006.224.07:42:49.12#ibcon#enter sib2, iclass 30, count 0 2006.224.07:42:49.12#ibcon#flushed, iclass 30, count 0 2006.224.07:42:49.12#ibcon#about to write, iclass 30, count 0 2006.224.07:42:49.12#ibcon#wrote, iclass 30, count 0 2006.224.07:42:49.12#ibcon#about to read 3, iclass 30, count 0 2006.224.07:42:49.15#ibcon#read 3, iclass 30, count 0 2006.224.07:42:49.15#ibcon#about to read 4, iclass 30, count 0 2006.224.07:42:49.15#ibcon#read 4, iclass 30, count 0 2006.224.07:42:49.15#ibcon#about to read 5, iclass 30, count 0 2006.224.07:42:49.15#ibcon#read 5, iclass 30, count 0 2006.224.07:42:49.15#ibcon#about to read 6, iclass 30, count 0 2006.224.07:42:49.15#ibcon#read 6, iclass 30, count 0 2006.224.07:42:49.15#ibcon#end of sib2, iclass 30, count 0 2006.224.07:42:49.15#ibcon#*mode == 0, iclass 30, count 0 2006.224.07:42:49.15#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.224.07:42:49.15#ibcon#[25=USB\r\n] 2006.224.07:42:49.15#ibcon#*before write, iclass 30, count 0 2006.224.07:42:49.15#ibcon#enter sib2, iclass 30, count 0 2006.224.07:42:49.15#ibcon#flushed, iclass 30, count 0 2006.224.07:42:49.15#ibcon#about to write, iclass 30, count 0 2006.224.07:42:49.15#ibcon#wrote, iclass 30, count 0 2006.224.07:42:49.15#ibcon#about to read 3, iclass 30, count 0 2006.224.07:42:49.17#ibcon#read 3, iclass 30, count 0 2006.224.07:42:49.17#ibcon#about to read 4, iclass 30, count 0 2006.224.07:42:49.17#ibcon#read 4, iclass 30, count 0 2006.224.07:42:49.17#ibcon#about to read 5, iclass 30, count 0 2006.224.07:42:49.17#ibcon#read 5, iclass 30, count 0 2006.224.07:42:49.17#ibcon#about to read 6, iclass 30, count 0 2006.224.07:42:49.17#ibcon#read 6, iclass 30, count 0 2006.224.07:42:49.17#ibcon#end of sib2, iclass 30, count 0 2006.224.07:42:49.17#ibcon#*after write, iclass 30, count 0 2006.224.07:42:49.17#ibcon#*before return 0, iclass 30, count 0 2006.224.07:42:49.17#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.224.07:42:49.17#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.224.07:42:49.17#ibcon#about to clear, iclass 30 cls_cnt 0 2006.224.07:42:49.17#ibcon#cleared, iclass 30 cls_cnt 0 2006.224.07:42:49.17$vc4f8/valo=5,652.99 2006.224.07:42:49.18#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.224.07:42:49.18#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.224.07:42:49.18#ibcon#ireg 17 cls_cnt 0 2006.224.07:42:49.18#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.224.07:42:49.18#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.224.07:42:49.18#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.224.07:42:49.18#ibcon#enter wrdev, iclass 32, count 0 2006.224.07:42:49.18#ibcon#first serial, iclass 32, count 0 2006.224.07:42:49.18#ibcon#enter sib2, iclass 32, count 0 2006.224.07:42:49.18#ibcon#flushed, iclass 32, count 0 2006.224.07:42:49.18#ibcon#about to write, iclass 32, count 0 2006.224.07:42:49.18#ibcon#wrote, iclass 32, count 0 2006.224.07:42:49.18#ibcon#about to read 3, iclass 32, count 0 2006.224.07:42:49.19#ibcon#read 3, iclass 32, count 0 2006.224.07:42:49.19#ibcon#about to read 4, iclass 32, count 0 2006.224.07:42:49.19#ibcon#read 4, iclass 32, count 0 2006.224.07:42:49.19#ibcon#about to read 5, iclass 32, count 0 2006.224.07:42:49.19#ibcon#read 5, iclass 32, count 0 2006.224.07:42:49.19#ibcon#about to read 6, iclass 32, count 0 2006.224.07:42:49.19#ibcon#read 6, iclass 32, count 0 2006.224.07:42:49.19#ibcon#end of sib2, iclass 32, count 0 2006.224.07:42:49.19#ibcon#*mode == 0, iclass 32, count 0 2006.224.07:42:49.19#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.224.07:42:49.19#ibcon#[26=FRQ=05,652.99\r\n] 2006.224.07:42:49.19#ibcon#*before write, iclass 32, count 0 2006.224.07:42:49.19#ibcon#enter sib2, iclass 32, count 0 2006.224.07:42:49.19#ibcon#flushed, iclass 32, count 0 2006.224.07:42:49.19#ibcon#about to write, iclass 32, count 0 2006.224.07:42:49.19#ibcon#wrote, iclass 32, count 0 2006.224.07:42:49.19#ibcon#about to read 3, iclass 32, count 0 2006.224.07:42:49.23#ibcon#read 3, iclass 32, count 0 2006.224.07:42:49.23#ibcon#about to read 4, iclass 32, count 0 2006.224.07:42:49.23#ibcon#read 4, iclass 32, count 0 2006.224.07:42:49.23#ibcon#about to read 5, iclass 32, count 0 2006.224.07:42:49.23#ibcon#read 5, iclass 32, count 0 2006.224.07:42:49.23#ibcon#about to read 6, iclass 32, count 0 2006.224.07:42:49.23#ibcon#read 6, iclass 32, count 0 2006.224.07:42:49.23#ibcon#end of sib2, iclass 32, count 0 2006.224.07:42:49.23#ibcon#*after write, iclass 32, count 0 2006.224.07:42:49.23#ibcon#*before return 0, iclass 32, count 0 2006.224.07:42:49.23#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.224.07:42:49.23#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.224.07:42:49.23#ibcon#about to clear, iclass 32 cls_cnt 0 2006.224.07:42:49.23#ibcon#cleared, iclass 32 cls_cnt 0 2006.224.07:42:49.23$vc4f8/va=5,7 2006.224.07:42:49.24#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.224.07:42:49.24#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.224.07:42:49.24#ibcon#ireg 11 cls_cnt 2 2006.224.07:42:49.24#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.224.07:42:49.28#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.224.07:42:49.28#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.224.07:42:49.28#ibcon#enter wrdev, iclass 34, count 2 2006.224.07:42:49.28#ibcon#first serial, iclass 34, count 2 2006.224.07:42:49.28#ibcon#enter sib2, iclass 34, count 2 2006.224.07:42:49.28#ibcon#flushed, iclass 34, count 2 2006.224.07:42:49.28#ibcon#about to write, iclass 34, count 2 2006.224.07:42:49.28#ibcon#wrote, iclass 34, count 2 2006.224.07:42:49.28#ibcon#about to read 3, iclass 34, count 2 2006.224.07:42:49.30#ibcon#read 3, iclass 34, count 2 2006.224.07:42:49.30#ibcon#about to read 4, iclass 34, count 2 2006.224.07:42:49.30#ibcon#read 4, iclass 34, count 2 2006.224.07:42:49.30#ibcon#about to read 5, iclass 34, count 2 2006.224.07:42:49.30#ibcon#read 5, iclass 34, count 2 2006.224.07:42:49.30#ibcon#about to read 6, iclass 34, count 2 2006.224.07:42:49.30#ibcon#read 6, iclass 34, count 2 2006.224.07:42:49.30#ibcon#end of sib2, iclass 34, count 2 2006.224.07:42:49.30#ibcon#*mode == 0, iclass 34, count 2 2006.224.07:42:49.30#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.224.07:42:49.30#ibcon#[25=AT05-07\r\n] 2006.224.07:42:49.30#ibcon#*before write, iclass 34, count 2 2006.224.07:42:49.30#ibcon#enter sib2, iclass 34, count 2 2006.224.07:42:49.30#ibcon#flushed, iclass 34, count 2 2006.224.07:42:49.30#ibcon#about to write, iclass 34, count 2 2006.224.07:42:49.30#ibcon#wrote, iclass 34, count 2 2006.224.07:42:49.30#ibcon#about to read 3, iclass 34, count 2 2006.224.07:42:49.33#ibcon#read 3, iclass 34, count 2 2006.224.07:42:49.33#ibcon#about to read 4, iclass 34, count 2 2006.224.07:42:49.33#ibcon#read 4, iclass 34, count 2 2006.224.07:42:49.33#ibcon#about to read 5, iclass 34, count 2 2006.224.07:42:49.33#ibcon#read 5, iclass 34, count 2 2006.224.07:42:49.33#ibcon#about to read 6, iclass 34, count 2 2006.224.07:42:49.33#ibcon#read 6, iclass 34, count 2 2006.224.07:42:49.33#ibcon#end of sib2, iclass 34, count 2 2006.224.07:42:49.33#ibcon#*after write, iclass 34, count 2 2006.224.07:42:49.33#ibcon#*before return 0, iclass 34, count 2 2006.224.07:42:49.33#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.224.07:42:49.33#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.224.07:42:49.33#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.224.07:42:49.33#ibcon#ireg 7 cls_cnt 0 2006.224.07:42:49.33#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.224.07:42:49.45#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.224.07:42:49.45#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.224.07:42:49.45#ibcon#enter wrdev, iclass 34, count 0 2006.224.07:42:49.45#ibcon#first serial, iclass 34, count 0 2006.224.07:42:49.45#ibcon#enter sib2, iclass 34, count 0 2006.224.07:42:49.45#ibcon#flushed, iclass 34, count 0 2006.224.07:42:49.45#ibcon#about to write, iclass 34, count 0 2006.224.07:42:49.45#ibcon#wrote, iclass 34, count 0 2006.224.07:42:49.45#ibcon#about to read 3, iclass 34, count 0 2006.224.07:42:49.47#ibcon#read 3, iclass 34, count 0 2006.224.07:42:49.47#ibcon#about to read 4, iclass 34, count 0 2006.224.07:42:49.47#ibcon#read 4, iclass 34, count 0 2006.224.07:42:49.47#ibcon#about to read 5, iclass 34, count 0 2006.224.07:42:49.47#ibcon#read 5, iclass 34, count 0 2006.224.07:42:49.47#ibcon#about to read 6, iclass 34, count 0 2006.224.07:42:49.47#ibcon#read 6, iclass 34, count 0 2006.224.07:42:49.47#ibcon#end of sib2, iclass 34, count 0 2006.224.07:42:49.47#ibcon#*mode == 0, iclass 34, count 0 2006.224.07:42:49.47#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.224.07:42:49.47#ibcon#[25=USB\r\n] 2006.224.07:42:49.47#ibcon#*before write, iclass 34, count 0 2006.224.07:42:49.47#ibcon#enter sib2, iclass 34, count 0 2006.224.07:42:49.47#ibcon#flushed, iclass 34, count 0 2006.224.07:42:49.47#ibcon#about to write, iclass 34, count 0 2006.224.07:42:49.47#ibcon#wrote, iclass 34, count 0 2006.224.07:42:49.47#ibcon#about to read 3, iclass 34, count 0 2006.224.07:42:49.50#ibcon#read 3, iclass 34, count 0 2006.224.07:42:49.50#ibcon#about to read 4, iclass 34, count 0 2006.224.07:42:49.50#ibcon#read 4, iclass 34, count 0 2006.224.07:42:49.50#ibcon#about to read 5, iclass 34, count 0 2006.224.07:42:49.50#ibcon#read 5, iclass 34, count 0 2006.224.07:42:49.50#ibcon#about to read 6, iclass 34, count 0 2006.224.07:42:49.50#ibcon#read 6, iclass 34, count 0 2006.224.07:42:49.50#ibcon#end of sib2, iclass 34, count 0 2006.224.07:42:49.50#ibcon#*after write, iclass 34, count 0 2006.224.07:42:49.50#ibcon#*before return 0, iclass 34, count 0 2006.224.07:42:49.50#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.224.07:42:49.50#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.224.07:42:49.50#ibcon#about to clear, iclass 34 cls_cnt 0 2006.224.07:42:49.50#ibcon#cleared, iclass 34 cls_cnt 0 2006.224.07:42:49.50$vc4f8/valo=6,772.99 2006.224.07:42:49.50#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.224.07:42:49.50#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.224.07:42:49.50#ibcon#ireg 17 cls_cnt 0 2006.224.07:42:49.51#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.224.07:42:49.51#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.224.07:42:49.51#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.224.07:42:49.51#ibcon#enter wrdev, iclass 36, count 0 2006.224.07:42:49.51#ibcon#first serial, iclass 36, count 0 2006.224.07:42:49.51#ibcon#enter sib2, iclass 36, count 0 2006.224.07:42:49.51#ibcon#flushed, iclass 36, count 0 2006.224.07:42:49.51#ibcon#about to write, iclass 36, count 0 2006.224.07:42:49.51#ibcon#wrote, iclass 36, count 0 2006.224.07:42:49.51#ibcon#about to read 3, iclass 36, count 0 2006.224.07:42:49.52#ibcon#read 3, iclass 36, count 0 2006.224.07:42:49.52#ibcon#about to read 4, iclass 36, count 0 2006.224.07:42:49.52#ibcon#read 4, iclass 36, count 0 2006.224.07:42:49.52#ibcon#about to read 5, iclass 36, count 0 2006.224.07:42:49.52#ibcon#read 5, iclass 36, count 0 2006.224.07:42:49.52#ibcon#about to read 6, iclass 36, count 0 2006.224.07:42:49.52#ibcon#read 6, iclass 36, count 0 2006.224.07:42:49.52#ibcon#end of sib2, iclass 36, count 0 2006.224.07:42:49.52#ibcon#*mode == 0, iclass 36, count 0 2006.224.07:42:49.52#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.224.07:42:49.52#ibcon#[26=FRQ=06,772.99\r\n] 2006.224.07:42:49.52#ibcon#*before write, iclass 36, count 0 2006.224.07:42:49.52#ibcon#enter sib2, iclass 36, count 0 2006.224.07:42:49.52#ibcon#flushed, iclass 36, count 0 2006.224.07:42:49.52#ibcon#about to write, iclass 36, count 0 2006.224.07:42:49.52#ibcon#wrote, iclass 36, count 0 2006.224.07:42:49.52#ibcon#about to read 3, iclass 36, count 0 2006.224.07:42:49.56#ibcon#read 3, iclass 36, count 0 2006.224.07:42:49.56#ibcon#about to read 4, iclass 36, count 0 2006.224.07:42:49.56#ibcon#read 4, iclass 36, count 0 2006.224.07:42:49.56#ibcon#about to read 5, iclass 36, count 0 2006.224.07:42:49.56#ibcon#read 5, iclass 36, count 0 2006.224.07:42:49.56#ibcon#about to read 6, iclass 36, count 0 2006.224.07:42:49.56#ibcon#read 6, iclass 36, count 0 2006.224.07:42:49.56#ibcon#end of sib2, iclass 36, count 0 2006.224.07:42:49.56#ibcon#*after write, iclass 36, count 0 2006.224.07:42:49.56#ibcon#*before return 0, iclass 36, count 0 2006.224.07:42:49.56#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.224.07:42:49.56#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.224.07:42:49.56#ibcon#about to clear, iclass 36 cls_cnt 0 2006.224.07:42:49.56#ibcon#cleared, iclass 36 cls_cnt 0 2006.224.07:42:49.56$vc4f8/va=6,6 2006.224.07:42:49.56#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.224.07:42:49.57#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.224.07:42:49.57#ibcon#ireg 11 cls_cnt 2 2006.224.07:42:49.57#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.224.07:42:49.62#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.224.07:42:49.62#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.224.07:42:49.62#ibcon#enter wrdev, iclass 38, count 2 2006.224.07:42:49.62#ibcon#first serial, iclass 38, count 2 2006.224.07:42:49.62#ibcon#enter sib2, iclass 38, count 2 2006.224.07:42:49.62#ibcon#flushed, iclass 38, count 2 2006.224.07:42:49.62#ibcon#about to write, iclass 38, count 2 2006.224.07:42:49.62#ibcon#wrote, iclass 38, count 2 2006.224.07:42:49.62#ibcon#about to read 3, iclass 38, count 2 2006.224.07:42:49.63#ibcon#read 3, iclass 38, count 2 2006.224.07:42:49.63#ibcon#about to read 4, iclass 38, count 2 2006.224.07:42:49.63#ibcon#read 4, iclass 38, count 2 2006.224.07:42:49.63#ibcon#about to read 5, iclass 38, count 2 2006.224.07:42:49.63#ibcon#read 5, iclass 38, count 2 2006.224.07:42:49.63#ibcon#about to read 6, iclass 38, count 2 2006.224.07:42:49.63#ibcon#read 6, iclass 38, count 2 2006.224.07:42:49.63#ibcon#end of sib2, iclass 38, count 2 2006.224.07:42:49.63#ibcon#*mode == 0, iclass 38, count 2 2006.224.07:42:49.63#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.224.07:42:49.63#ibcon#[25=AT06-06\r\n] 2006.224.07:42:49.63#ibcon#*before write, iclass 38, count 2 2006.224.07:42:49.63#ibcon#enter sib2, iclass 38, count 2 2006.224.07:42:49.63#ibcon#flushed, iclass 38, count 2 2006.224.07:42:49.63#ibcon#about to write, iclass 38, count 2 2006.224.07:42:49.63#ibcon#wrote, iclass 38, count 2 2006.224.07:42:49.63#ibcon#about to read 3, iclass 38, count 2 2006.224.07:42:49.66#ibcon#read 3, iclass 38, count 2 2006.224.07:42:49.66#ibcon#about to read 4, iclass 38, count 2 2006.224.07:42:49.66#ibcon#read 4, iclass 38, count 2 2006.224.07:42:49.66#ibcon#about to read 5, iclass 38, count 2 2006.224.07:42:49.66#ibcon#read 5, iclass 38, count 2 2006.224.07:42:49.66#ibcon#about to read 6, iclass 38, count 2 2006.224.07:42:49.66#ibcon#read 6, iclass 38, count 2 2006.224.07:42:49.66#ibcon#end of sib2, iclass 38, count 2 2006.224.07:42:49.66#ibcon#*after write, iclass 38, count 2 2006.224.07:42:49.66#ibcon#*before return 0, iclass 38, count 2 2006.224.07:42:49.66#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.224.07:42:49.66#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.224.07:42:49.66#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.224.07:42:49.66#ibcon#ireg 7 cls_cnt 0 2006.224.07:42:49.66#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.224.07:42:49.78#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.224.07:42:49.78#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.224.07:42:49.78#ibcon#enter wrdev, iclass 38, count 0 2006.224.07:42:49.78#ibcon#first serial, iclass 38, count 0 2006.224.07:42:49.78#ibcon#enter sib2, iclass 38, count 0 2006.224.07:42:49.78#ibcon#flushed, iclass 38, count 0 2006.224.07:42:49.78#ibcon#about to write, iclass 38, count 0 2006.224.07:42:49.78#ibcon#wrote, iclass 38, count 0 2006.224.07:42:49.78#ibcon#about to read 3, iclass 38, count 0 2006.224.07:42:49.80#ibcon#read 3, iclass 38, count 0 2006.224.07:42:49.80#ibcon#about to read 4, iclass 38, count 0 2006.224.07:42:49.80#ibcon#read 4, iclass 38, count 0 2006.224.07:42:49.80#ibcon#about to read 5, iclass 38, count 0 2006.224.07:42:49.80#ibcon#read 5, iclass 38, count 0 2006.224.07:42:49.80#ibcon#about to read 6, iclass 38, count 0 2006.224.07:42:49.80#ibcon#read 6, iclass 38, count 0 2006.224.07:42:49.80#ibcon#end of sib2, iclass 38, count 0 2006.224.07:42:49.80#ibcon#*mode == 0, iclass 38, count 0 2006.224.07:42:49.80#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.224.07:42:49.80#ibcon#[25=USB\r\n] 2006.224.07:42:49.80#ibcon#*before write, iclass 38, count 0 2006.224.07:42:49.80#ibcon#enter sib2, iclass 38, count 0 2006.224.07:42:49.80#ibcon#flushed, iclass 38, count 0 2006.224.07:42:49.80#ibcon#about to write, iclass 38, count 0 2006.224.07:42:49.80#ibcon#wrote, iclass 38, count 0 2006.224.07:42:49.80#ibcon#about to read 3, iclass 38, count 0 2006.224.07:42:49.83#ibcon#read 3, iclass 38, count 0 2006.224.07:42:49.83#ibcon#about to read 4, iclass 38, count 0 2006.224.07:42:49.83#ibcon#read 4, iclass 38, count 0 2006.224.07:42:49.83#ibcon#about to read 5, iclass 38, count 0 2006.224.07:42:49.83#ibcon#read 5, iclass 38, count 0 2006.224.07:42:49.83#ibcon#about to read 6, iclass 38, count 0 2006.224.07:42:49.83#ibcon#read 6, iclass 38, count 0 2006.224.07:42:49.83#ibcon#end of sib2, iclass 38, count 0 2006.224.07:42:49.83#ibcon#*after write, iclass 38, count 0 2006.224.07:42:49.83#ibcon#*before return 0, iclass 38, count 0 2006.224.07:42:49.83#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.224.07:42:49.83#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.224.07:42:49.83#ibcon#about to clear, iclass 38 cls_cnt 0 2006.224.07:42:49.83#ibcon#cleared, iclass 38 cls_cnt 0 2006.224.07:42:49.83$vc4f8/valo=7,832.99 2006.224.07:42:49.83#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.224.07:42:49.83#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.224.07:42:49.83#ibcon#ireg 17 cls_cnt 0 2006.224.07:42:49.83#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.224.07:42:49.84#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.224.07:42:49.84#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.224.07:42:49.84#ibcon#enter wrdev, iclass 40, count 0 2006.224.07:42:49.84#ibcon#first serial, iclass 40, count 0 2006.224.07:42:49.84#ibcon#enter sib2, iclass 40, count 0 2006.224.07:42:49.84#ibcon#flushed, iclass 40, count 0 2006.224.07:42:49.84#ibcon#about to write, iclass 40, count 0 2006.224.07:42:49.84#ibcon#wrote, iclass 40, count 0 2006.224.07:42:49.84#ibcon#about to read 3, iclass 40, count 0 2006.224.07:42:49.85#ibcon#read 3, iclass 40, count 0 2006.224.07:42:49.85#ibcon#about to read 4, iclass 40, count 0 2006.224.07:42:49.85#ibcon#read 4, iclass 40, count 0 2006.224.07:42:49.85#ibcon#about to read 5, iclass 40, count 0 2006.224.07:42:49.85#ibcon#read 5, iclass 40, count 0 2006.224.07:42:49.85#ibcon#about to read 6, iclass 40, count 0 2006.224.07:42:49.85#ibcon#read 6, iclass 40, count 0 2006.224.07:42:49.85#ibcon#end of sib2, iclass 40, count 0 2006.224.07:42:49.85#ibcon#*mode == 0, iclass 40, count 0 2006.224.07:42:49.85#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.224.07:42:49.85#ibcon#[26=FRQ=07,832.99\r\n] 2006.224.07:42:49.85#ibcon#*before write, iclass 40, count 0 2006.224.07:42:49.85#ibcon#enter sib2, iclass 40, count 0 2006.224.07:42:49.85#ibcon#flushed, iclass 40, count 0 2006.224.07:42:49.85#ibcon#about to write, iclass 40, count 0 2006.224.07:42:49.85#ibcon#wrote, iclass 40, count 0 2006.224.07:42:49.85#ibcon#about to read 3, iclass 40, count 0 2006.224.07:42:49.89#ibcon#read 3, iclass 40, count 0 2006.224.07:42:49.89#ibcon#about to read 4, iclass 40, count 0 2006.224.07:42:49.89#ibcon#read 4, iclass 40, count 0 2006.224.07:42:49.89#ibcon#about to read 5, iclass 40, count 0 2006.224.07:42:49.89#ibcon#read 5, iclass 40, count 0 2006.224.07:42:49.89#ibcon#about to read 6, iclass 40, count 0 2006.224.07:42:49.89#ibcon#read 6, iclass 40, count 0 2006.224.07:42:49.89#ibcon#end of sib2, iclass 40, count 0 2006.224.07:42:49.89#ibcon#*after write, iclass 40, count 0 2006.224.07:42:49.89#ibcon#*before return 0, iclass 40, count 0 2006.224.07:42:49.89#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.224.07:42:49.89#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.224.07:42:49.89#ibcon#about to clear, iclass 40 cls_cnt 0 2006.224.07:42:49.89#ibcon#cleared, iclass 40 cls_cnt 0 2006.224.07:42:49.89$vc4f8/va=7,6 2006.224.07:42:49.89#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.224.07:42:49.90#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.224.07:42:49.90#ibcon#ireg 11 cls_cnt 2 2006.224.07:42:49.90#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.224.07:42:49.94#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.224.07:42:49.94#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.224.07:42:49.94#ibcon#enter wrdev, iclass 4, count 2 2006.224.07:42:49.94#ibcon#first serial, iclass 4, count 2 2006.224.07:42:49.94#ibcon#enter sib2, iclass 4, count 2 2006.224.07:42:49.94#ibcon#flushed, iclass 4, count 2 2006.224.07:42:49.94#ibcon#about to write, iclass 4, count 2 2006.224.07:42:49.94#ibcon#wrote, iclass 4, count 2 2006.224.07:42:49.94#ibcon#about to read 3, iclass 4, count 2 2006.224.07:42:49.96#ibcon#read 3, iclass 4, count 2 2006.224.07:42:49.96#ibcon#about to read 4, iclass 4, count 2 2006.224.07:42:49.96#ibcon#read 4, iclass 4, count 2 2006.224.07:42:49.96#ibcon#about to read 5, iclass 4, count 2 2006.224.07:42:49.96#ibcon#read 5, iclass 4, count 2 2006.224.07:42:49.96#ibcon#about to read 6, iclass 4, count 2 2006.224.07:42:49.96#ibcon#read 6, iclass 4, count 2 2006.224.07:42:49.96#ibcon#end of sib2, iclass 4, count 2 2006.224.07:42:49.96#ibcon#*mode == 0, iclass 4, count 2 2006.224.07:42:49.96#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.224.07:42:49.96#ibcon#[25=AT07-06\r\n] 2006.224.07:42:49.96#ibcon#*before write, iclass 4, count 2 2006.224.07:42:49.96#ibcon#enter sib2, iclass 4, count 2 2006.224.07:42:49.96#ibcon#flushed, iclass 4, count 2 2006.224.07:42:49.96#ibcon#about to write, iclass 4, count 2 2006.224.07:42:49.96#ibcon#wrote, iclass 4, count 2 2006.224.07:42:49.96#ibcon#about to read 3, iclass 4, count 2 2006.224.07:42:49.99#ibcon#read 3, iclass 4, count 2 2006.224.07:42:49.99#ibcon#about to read 4, iclass 4, count 2 2006.224.07:42:49.99#ibcon#read 4, iclass 4, count 2 2006.224.07:42:49.99#ibcon#about to read 5, iclass 4, count 2 2006.224.07:42:49.99#ibcon#read 5, iclass 4, count 2 2006.224.07:42:49.99#ibcon#about to read 6, iclass 4, count 2 2006.224.07:42:49.99#ibcon#read 6, iclass 4, count 2 2006.224.07:42:49.99#ibcon#end of sib2, iclass 4, count 2 2006.224.07:42:49.99#ibcon#*after write, iclass 4, count 2 2006.224.07:42:49.99#ibcon#*before return 0, iclass 4, count 2 2006.224.07:42:49.99#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.224.07:42:49.99#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.224.07:42:49.99#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.224.07:42:49.99#ibcon#ireg 7 cls_cnt 0 2006.224.07:42:49.99#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.224.07:42:50.11#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.224.07:42:50.11#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.224.07:42:50.11#ibcon#enter wrdev, iclass 4, count 0 2006.224.07:42:50.11#ibcon#first serial, iclass 4, count 0 2006.224.07:42:50.11#ibcon#enter sib2, iclass 4, count 0 2006.224.07:42:50.11#ibcon#flushed, iclass 4, count 0 2006.224.07:42:50.11#ibcon#about to write, iclass 4, count 0 2006.224.07:42:50.11#ibcon#wrote, iclass 4, count 0 2006.224.07:42:50.11#ibcon#about to read 3, iclass 4, count 0 2006.224.07:42:50.13#ibcon#read 3, iclass 4, count 0 2006.224.07:42:50.13#ibcon#about to read 4, iclass 4, count 0 2006.224.07:42:50.13#ibcon#read 4, iclass 4, count 0 2006.224.07:42:50.13#ibcon#about to read 5, iclass 4, count 0 2006.224.07:42:50.13#ibcon#read 5, iclass 4, count 0 2006.224.07:42:50.13#ibcon#about to read 6, iclass 4, count 0 2006.224.07:42:50.13#ibcon#read 6, iclass 4, count 0 2006.224.07:42:50.13#ibcon#end of sib2, iclass 4, count 0 2006.224.07:42:50.13#ibcon#*mode == 0, iclass 4, count 0 2006.224.07:42:50.13#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.224.07:42:50.13#ibcon#[25=USB\r\n] 2006.224.07:42:50.13#ibcon#*before write, iclass 4, count 0 2006.224.07:42:50.13#ibcon#enter sib2, iclass 4, count 0 2006.224.07:42:50.13#ibcon#flushed, iclass 4, count 0 2006.224.07:42:50.13#ibcon#about to write, iclass 4, count 0 2006.224.07:42:50.13#ibcon#wrote, iclass 4, count 0 2006.224.07:42:50.13#ibcon#about to read 3, iclass 4, count 0 2006.224.07:42:50.16#ibcon#read 3, iclass 4, count 0 2006.224.07:42:50.16#ibcon#about to read 4, iclass 4, count 0 2006.224.07:42:50.16#ibcon#read 4, iclass 4, count 0 2006.224.07:42:50.16#ibcon#about to read 5, iclass 4, count 0 2006.224.07:42:50.16#ibcon#read 5, iclass 4, count 0 2006.224.07:42:50.16#ibcon#about to read 6, iclass 4, count 0 2006.224.07:42:50.16#ibcon#read 6, iclass 4, count 0 2006.224.07:42:50.16#ibcon#end of sib2, iclass 4, count 0 2006.224.07:42:50.16#ibcon#*after write, iclass 4, count 0 2006.224.07:42:50.16#ibcon#*before return 0, iclass 4, count 0 2006.224.07:42:50.16#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.224.07:42:50.16#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.224.07:42:50.16#ibcon#about to clear, iclass 4 cls_cnt 0 2006.224.07:42:50.16#ibcon#cleared, iclass 4 cls_cnt 0 2006.224.07:42:50.16$vc4f8/valo=8,852.99 2006.224.07:42:50.16#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.224.07:42:50.16#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.224.07:42:50.16#ibcon#ireg 17 cls_cnt 0 2006.224.07:42:50.17#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.224.07:42:50.17#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.224.07:42:50.17#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.224.07:42:50.17#ibcon#enter wrdev, iclass 6, count 0 2006.224.07:42:50.17#ibcon#first serial, iclass 6, count 0 2006.224.07:42:50.17#ibcon#enter sib2, iclass 6, count 0 2006.224.07:42:50.17#ibcon#flushed, iclass 6, count 0 2006.224.07:42:50.17#ibcon#about to write, iclass 6, count 0 2006.224.07:42:50.17#ibcon#wrote, iclass 6, count 0 2006.224.07:42:50.17#ibcon#about to read 3, iclass 6, count 0 2006.224.07:42:50.18#ibcon#read 3, iclass 6, count 0 2006.224.07:42:50.18#ibcon#about to read 4, iclass 6, count 0 2006.224.07:42:50.18#ibcon#read 4, iclass 6, count 0 2006.224.07:42:50.18#ibcon#about to read 5, iclass 6, count 0 2006.224.07:42:50.18#ibcon#read 5, iclass 6, count 0 2006.224.07:42:50.18#ibcon#about to read 6, iclass 6, count 0 2006.224.07:42:50.18#ibcon#read 6, iclass 6, count 0 2006.224.07:42:50.18#ibcon#end of sib2, iclass 6, count 0 2006.224.07:42:50.18#ibcon#*mode == 0, iclass 6, count 0 2006.224.07:42:50.18#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.224.07:42:50.18#ibcon#[26=FRQ=08,852.99\r\n] 2006.224.07:42:50.18#ibcon#*before write, iclass 6, count 0 2006.224.07:42:50.18#ibcon#enter sib2, iclass 6, count 0 2006.224.07:42:50.18#ibcon#flushed, iclass 6, count 0 2006.224.07:42:50.18#ibcon#about to write, iclass 6, count 0 2006.224.07:42:50.18#ibcon#wrote, iclass 6, count 0 2006.224.07:42:50.18#ibcon#about to read 3, iclass 6, count 0 2006.224.07:42:50.22#ibcon#read 3, iclass 6, count 0 2006.224.07:42:50.22#ibcon#about to read 4, iclass 6, count 0 2006.224.07:42:50.22#ibcon#read 4, iclass 6, count 0 2006.224.07:42:50.22#ibcon#about to read 5, iclass 6, count 0 2006.224.07:42:50.22#ibcon#read 5, iclass 6, count 0 2006.224.07:42:50.22#ibcon#about to read 6, iclass 6, count 0 2006.224.07:42:50.22#ibcon#read 6, iclass 6, count 0 2006.224.07:42:50.22#ibcon#end of sib2, iclass 6, count 0 2006.224.07:42:50.22#ibcon#*after write, iclass 6, count 0 2006.224.07:42:50.22#ibcon#*before return 0, iclass 6, count 0 2006.224.07:42:50.22#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.224.07:42:50.22#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.224.07:42:50.22#ibcon#about to clear, iclass 6 cls_cnt 0 2006.224.07:42:50.22#ibcon#cleared, iclass 6 cls_cnt 0 2006.224.07:42:50.22$vc4f8/va=8,7 2006.224.07:42:50.22#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.224.07:42:50.23#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.224.07:42:50.23#ibcon#ireg 11 cls_cnt 2 2006.224.07:42:50.23#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.224.07:42:50.28#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.224.07:42:50.28#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.224.07:42:50.28#ibcon#enter wrdev, iclass 10, count 2 2006.224.07:42:50.28#ibcon#first serial, iclass 10, count 2 2006.224.07:42:50.28#ibcon#enter sib2, iclass 10, count 2 2006.224.07:42:50.28#ibcon#flushed, iclass 10, count 2 2006.224.07:42:50.28#ibcon#about to write, iclass 10, count 2 2006.224.07:42:50.28#ibcon#wrote, iclass 10, count 2 2006.224.07:42:50.28#ibcon#about to read 3, iclass 10, count 2 2006.224.07:42:50.29#ibcon#read 3, iclass 10, count 2 2006.224.07:42:50.29#ibcon#about to read 4, iclass 10, count 2 2006.224.07:42:50.29#ibcon#read 4, iclass 10, count 2 2006.224.07:42:50.29#ibcon#about to read 5, iclass 10, count 2 2006.224.07:42:50.29#ibcon#read 5, iclass 10, count 2 2006.224.07:42:50.29#ibcon#about to read 6, iclass 10, count 2 2006.224.07:42:50.29#ibcon#read 6, iclass 10, count 2 2006.224.07:42:50.29#ibcon#end of sib2, iclass 10, count 2 2006.224.07:42:50.29#ibcon#*mode == 0, iclass 10, count 2 2006.224.07:42:50.29#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.224.07:42:50.29#ibcon#[25=AT08-07\r\n] 2006.224.07:42:50.29#ibcon#*before write, iclass 10, count 2 2006.224.07:42:50.29#ibcon#enter sib2, iclass 10, count 2 2006.224.07:42:50.29#ibcon#flushed, iclass 10, count 2 2006.224.07:42:50.29#ibcon#about to write, iclass 10, count 2 2006.224.07:42:50.29#ibcon#wrote, iclass 10, count 2 2006.224.07:42:50.29#ibcon#about to read 3, iclass 10, count 2 2006.224.07:42:50.32#ibcon#read 3, iclass 10, count 2 2006.224.07:42:50.32#ibcon#about to read 4, iclass 10, count 2 2006.224.07:42:50.32#ibcon#read 4, iclass 10, count 2 2006.224.07:42:50.32#ibcon#about to read 5, iclass 10, count 2 2006.224.07:42:50.32#ibcon#read 5, iclass 10, count 2 2006.224.07:42:50.32#ibcon#about to read 6, iclass 10, count 2 2006.224.07:42:50.32#ibcon#read 6, iclass 10, count 2 2006.224.07:42:50.32#ibcon#end of sib2, iclass 10, count 2 2006.224.07:42:50.32#ibcon#*after write, iclass 10, count 2 2006.224.07:42:50.32#ibcon#*before return 0, iclass 10, count 2 2006.224.07:42:50.32#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.224.07:42:50.32#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.224.07:42:50.32#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.224.07:42:50.32#ibcon#ireg 7 cls_cnt 0 2006.224.07:42:50.32#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.224.07:42:50.44#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.224.07:42:50.44#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.224.07:42:50.44#ibcon#enter wrdev, iclass 10, count 0 2006.224.07:42:50.44#ibcon#first serial, iclass 10, count 0 2006.224.07:42:50.44#ibcon#enter sib2, iclass 10, count 0 2006.224.07:42:50.44#ibcon#flushed, iclass 10, count 0 2006.224.07:42:50.44#ibcon#about to write, iclass 10, count 0 2006.224.07:42:50.44#ibcon#wrote, iclass 10, count 0 2006.224.07:42:50.44#ibcon#about to read 3, iclass 10, count 0 2006.224.07:42:50.46#ibcon#read 3, iclass 10, count 0 2006.224.07:42:50.46#ibcon#about to read 4, iclass 10, count 0 2006.224.07:42:50.46#ibcon#read 4, iclass 10, count 0 2006.224.07:42:50.46#ibcon#about to read 5, iclass 10, count 0 2006.224.07:42:50.46#ibcon#read 5, iclass 10, count 0 2006.224.07:42:50.46#ibcon#about to read 6, iclass 10, count 0 2006.224.07:42:50.46#ibcon#read 6, iclass 10, count 0 2006.224.07:42:50.46#ibcon#end of sib2, iclass 10, count 0 2006.224.07:42:50.46#ibcon#*mode == 0, iclass 10, count 0 2006.224.07:42:50.46#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.224.07:42:50.46#ibcon#[25=USB\r\n] 2006.224.07:42:50.46#ibcon#*before write, iclass 10, count 0 2006.224.07:42:50.46#ibcon#enter sib2, iclass 10, count 0 2006.224.07:42:50.46#ibcon#flushed, iclass 10, count 0 2006.224.07:42:50.46#ibcon#about to write, iclass 10, count 0 2006.224.07:42:50.46#ibcon#wrote, iclass 10, count 0 2006.224.07:42:50.46#ibcon#about to read 3, iclass 10, count 0 2006.224.07:42:50.49#ibcon#read 3, iclass 10, count 0 2006.224.07:42:50.49#ibcon#about to read 4, iclass 10, count 0 2006.224.07:42:50.49#ibcon#read 4, iclass 10, count 0 2006.224.07:42:50.49#ibcon#about to read 5, iclass 10, count 0 2006.224.07:42:50.49#ibcon#read 5, iclass 10, count 0 2006.224.07:42:50.49#ibcon#about to read 6, iclass 10, count 0 2006.224.07:42:50.49#ibcon#read 6, iclass 10, count 0 2006.224.07:42:50.49#ibcon#end of sib2, iclass 10, count 0 2006.224.07:42:50.49#ibcon#*after write, iclass 10, count 0 2006.224.07:42:50.49#ibcon#*before return 0, iclass 10, count 0 2006.224.07:42:50.49#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.224.07:42:50.49#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.224.07:42:50.49#ibcon#about to clear, iclass 10 cls_cnt 0 2006.224.07:42:50.49#ibcon#cleared, iclass 10 cls_cnt 0 2006.224.07:42:50.49$vc4f8/vblo=1,632.99 2006.224.07:42:50.49#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.224.07:42:50.49#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.224.07:42:50.49#ibcon#ireg 17 cls_cnt 0 2006.224.07:42:50.49#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.224.07:42:50.50#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.224.07:42:50.50#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.224.07:42:50.50#ibcon#enter wrdev, iclass 12, count 0 2006.224.07:42:50.50#ibcon#first serial, iclass 12, count 0 2006.224.07:42:50.50#ibcon#enter sib2, iclass 12, count 0 2006.224.07:42:50.50#ibcon#flushed, iclass 12, count 0 2006.224.07:42:50.50#ibcon#about to write, iclass 12, count 0 2006.224.07:42:50.50#ibcon#wrote, iclass 12, count 0 2006.224.07:42:50.50#ibcon#about to read 3, iclass 12, count 0 2006.224.07:42:50.51#ibcon#read 3, iclass 12, count 0 2006.224.07:42:50.51#ibcon#about to read 4, iclass 12, count 0 2006.224.07:42:50.51#ibcon#read 4, iclass 12, count 0 2006.224.07:42:50.51#ibcon#about to read 5, iclass 12, count 0 2006.224.07:42:50.51#ibcon#read 5, iclass 12, count 0 2006.224.07:42:50.51#ibcon#about to read 6, iclass 12, count 0 2006.224.07:42:50.51#ibcon#read 6, iclass 12, count 0 2006.224.07:42:50.51#ibcon#end of sib2, iclass 12, count 0 2006.224.07:42:50.51#ibcon#*mode == 0, iclass 12, count 0 2006.224.07:42:50.51#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.224.07:42:50.51#ibcon#[28=FRQ=01,632.99\r\n] 2006.224.07:42:50.51#ibcon#*before write, iclass 12, count 0 2006.224.07:42:50.51#ibcon#enter sib2, iclass 12, count 0 2006.224.07:42:50.51#ibcon#flushed, iclass 12, count 0 2006.224.07:42:50.51#ibcon#about to write, iclass 12, count 0 2006.224.07:42:50.51#ibcon#wrote, iclass 12, count 0 2006.224.07:42:50.51#ibcon#about to read 3, iclass 12, count 0 2006.224.07:42:50.55#ibcon#read 3, iclass 12, count 0 2006.224.07:42:50.55#ibcon#about to read 4, iclass 12, count 0 2006.224.07:42:50.55#ibcon#read 4, iclass 12, count 0 2006.224.07:42:50.55#ibcon#about to read 5, iclass 12, count 0 2006.224.07:42:50.55#ibcon#read 5, iclass 12, count 0 2006.224.07:42:50.55#ibcon#about to read 6, iclass 12, count 0 2006.224.07:42:50.55#ibcon#read 6, iclass 12, count 0 2006.224.07:42:50.55#ibcon#end of sib2, iclass 12, count 0 2006.224.07:42:50.55#ibcon#*after write, iclass 12, count 0 2006.224.07:42:50.55#ibcon#*before return 0, iclass 12, count 0 2006.224.07:42:50.55#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.224.07:42:50.55#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.224.07:42:50.55#ibcon#about to clear, iclass 12 cls_cnt 0 2006.224.07:42:50.55#ibcon#cleared, iclass 12 cls_cnt 0 2006.224.07:42:50.55$vc4f8/vb=1,4 2006.224.07:42:50.55#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.224.07:42:50.56#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.224.07:42:50.56#ibcon#ireg 11 cls_cnt 2 2006.224.07:42:50.56#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.224.07:42:50.56#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.224.07:42:50.56#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.224.07:42:50.56#ibcon#enter wrdev, iclass 14, count 2 2006.224.07:42:50.56#ibcon#first serial, iclass 14, count 2 2006.224.07:42:50.56#ibcon#enter sib2, iclass 14, count 2 2006.224.07:42:50.56#ibcon#flushed, iclass 14, count 2 2006.224.07:42:50.56#ibcon#about to write, iclass 14, count 2 2006.224.07:42:50.56#ibcon#wrote, iclass 14, count 2 2006.224.07:42:50.56#ibcon#about to read 3, iclass 14, count 2 2006.224.07:42:50.57#ibcon#read 3, iclass 14, count 2 2006.224.07:42:50.57#ibcon#about to read 4, iclass 14, count 2 2006.224.07:42:50.57#ibcon#read 4, iclass 14, count 2 2006.224.07:42:50.57#ibcon#about to read 5, iclass 14, count 2 2006.224.07:42:50.57#ibcon#read 5, iclass 14, count 2 2006.224.07:42:50.57#ibcon#about to read 6, iclass 14, count 2 2006.224.07:42:50.57#ibcon#read 6, iclass 14, count 2 2006.224.07:42:50.57#ibcon#end of sib2, iclass 14, count 2 2006.224.07:42:50.57#ibcon#*mode == 0, iclass 14, count 2 2006.224.07:42:50.57#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.224.07:42:50.57#ibcon#[27=AT01-04\r\n] 2006.224.07:42:50.57#ibcon#*before write, iclass 14, count 2 2006.224.07:42:50.57#ibcon#enter sib2, iclass 14, count 2 2006.224.07:42:50.57#ibcon#flushed, iclass 14, count 2 2006.224.07:42:50.57#ibcon#about to write, iclass 14, count 2 2006.224.07:42:50.57#ibcon#wrote, iclass 14, count 2 2006.224.07:42:50.57#ibcon#about to read 3, iclass 14, count 2 2006.224.07:42:50.60#ibcon#read 3, iclass 14, count 2 2006.224.07:42:50.60#ibcon#about to read 4, iclass 14, count 2 2006.224.07:42:50.60#ibcon#read 4, iclass 14, count 2 2006.224.07:42:50.60#ibcon#about to read 5, iclass 14, count 2 2006.224.07:42:50.60#ibcon#read 5, iclass 14, count 2 2006.224.07:42:50.60#ibcon#about to read 6, iclass 14, count 2 2006.224.07:42:50.60#ibcon#read 6, iclass 14, count 2 2006.224.07:42:50.60#ibcon#end of sib2, iclass 14, count 2 2006.224.07:42:50.60#ibcon#*after write, iclass 14, count 2 2006.224.07:42:50.60#ibcon#*before return 0, iclass 14, count 2 2006.224.07:42:50.60#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.224.07:42:50.60#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.224.07:42:50.60#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.224.07:42:50.60#ibcon#ireg 7 cls_cnt 0 2006.224.07:42:50.60#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.224.07:42:50.72#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.224.07:42:50.72#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.224.07:42:50.72#ibcon#enter wrdev, iclass 14, count 0 2006.224.07:42:50.72#ibcon#first serial, iclass 14, count 0 2006.224.07:42:50.72#ibcon#enter sib2, iclass 14, count 0 2006.224.07:42:50.72#ibcon#flushed, iclass 14, count 0 2006.224.07:42:50.72#ibcon#about to write, iclass 14, count 0 2006.224.07:42:50.72#ibcon#wrote, iclass 14, count 0 2006.224.07:42:50.72#ibcon#about to read 3, iclass 14, count 0 2006.224.07:42:50.74#ibcon#read 3, iclass 14, count 0 2006.224.07:42:50.74#ibcon#about to read 4, iclass 14, count 0 2006.224.07:42:50.74#ibcon#read 4, iclass 14, count 0 2006.224.07:42:50.74#ibcon#about to read 5, iclass 14, count 0 2006.224.07:42:50.74#ibcon#read 5, iclass 14, count 0 2006.224.07:42:50.74#ibcon#about to read 6, iclass 14, count 0 2006.224.07:42:50.74#ibcon#read 6, iclass 14, count 0 2006.224.07:42:50.74#ibcon#end of sib2, iclass 14, count 0 2006.224.07:42:50.74#ibcon#*mode == 0, iclass 14, count 0 2006.224.07:42:50.74#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.224.07:42:50.74#ibcon#[27=USB\r\n] 2006.224.07:42:50.74#ibcon#*before write, iclass 14, count 0 2006.224.07:42:50.74#ibcon#enter sib2, iclass 14, count 0 2006.224.07:42:50.74#ibcon#flushed, iclass 14, count 0 2006.224.07:42:50.74#ibcon#about to write, iclass 14, count 0 2006.224.07:42:50.74#ibcon#wrote, iclass 14, count 0 2006.224.07:42:50.74#ibcon#about to read 3, iclass 14, count 0 2006.224.07:42:50.77#ibcon#read 3, iclass 14, count 0 2006.224.07:42:50.77#ibcon#about to read 4, iclass 14, count 0 2006.224.07:42:50.77#ibcon#read 4, iclass 14, count 0 2006.224.07:42:50.77#ibcon#about to read 5, iclass 14, count 0 2006.224.07:42:50.77#ibcon#read 5, iclass 14, count 0 2006.224.07:42:50.77#ibcon#about to read 6, iclass 14, count 0 2006.224.07:42:50.77#ibcon#read 6, iclass 14, count 0 2006.224.07:42:50.77#ibcon#end of sib2, iclass 14, count 0 2006.224.07:42:50.77#ibcon#*after write, iclass 14, count 0 2006.224.07:42:50.77#ibcon#*before return 0, iclass 14, count 0 2006.224.07:42:50.77#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.224.07:42:50.77#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.224.07:42:50.77#ibcon#about to clear, iclass 14 cls_cnt 0 2006.224.07:42:50.77#ibcon#cleared, iclass 14 cls_cnt 0 2006.224.07:42:50.77$vc4f8/vblo=2,640.99 2006.224.07:42:50.77#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.224.07:42:50.77#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.224.07:42:50.78#ibcon#ireg 17 cls_cnt 0 2006.224.07:42:50.78#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.224.07:42:50.78#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.224.07:42:50.78#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.224.07:42:50.78#ibcon#enter wrdev, iclass 16, count 0 2006.224.07:42:50.78#ibcon#first serial, iclass 16, count 0 2006.224.07:42:50.78#ibcon#enter sib2, iclass 16, count 0 2006.224.07:42:50.78#ibcon#flushed, iclass 16, count 0 2006.224.07:42:50.78#ibcon#about to write, iclass 16, count 0 2006.224.07:42:50.78#ibcon#wrote, iclass 16, count 0 2006.224.07:42:50.78#ibcon#about to read 3, iclass 16, count 0 2006.224.07:42:50.79#ibcon#read 3, iclass 16, count 0 2006.224.07:42:50.79#ibcon#about to read 4, iclass 16, count 0 2006.224.07:42:50.79#ibcon#read 4, iclass 16, count 0 2006.224.07:42:50.79#ibcon#about to read 5, iclass 16, count 0 2006.224.07:42:50.79#ibcon#read 5, iclass 16, count 0 2006.224.07:42:50.79#ibcon#about to read 6, iclass 16, count 0 2006.224.07:42:50.79#ibcon#read 6, iclass 16, count 0 2006.224.07:42:50.79#ibcon#end of sib2, iclass 16, count 0 2006.224.07:42:50.79#ibcon#*mode == 0, iclass 16, count 0 2006.224.07:42:50.79#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.224.07:42:50.79#ibcon#[28=FRQ=02,640.99\r\n] 2006.224.07:42:50.79#ibcon#*before write, iclass 16, count 0 2006.224.07:42:50.79#ibcon#enter sib2, iclass 16, count 0 2006.224.07:42:50.79#ibcon#flushed, iclass 16, count 0 2006.224.07:42:50.79#ibcon#about to write, iclass 16, count 0 2006.224.07:42:50.79#ibcon#wrote, iclass 16, count 0 2006.224.07:42:50.79#ibcon#about to read 3, iclass 16, count 0 2006.224.07:42:50.83#ibcon#read 3, iclass 16, count 0 2006.224.07:42:50.83#ibcon#about to read 4, iclass 16, count 0 2006.224.07:42:50.83#ibcon#read 4, iclass 16, count 0 2006.224.07:42:50.83#ibcon#about to read 5, iclass 16, count 0 2006.224.07:42:50.83#ibcon#read 5, iclass 16, count 0 2006.224.07:42:50.83#ibcon#about to read 6, iclass 16, count 0 2006.224.07:42:50.83#ibcon#read 6, iclass 16, count 0 2006.224.07:42:50.83#ibcon#end of sib2, iclass 16, count 0 2006.224.07:42:50.83#ibcon#*after write, iclass 16, count 0 2006.224.07:42:50.83#ibcon#*before return 0, iclass 16, count 0 2006.224.07:42:50.83#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.224.07:42:50.83#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.224.07:42:50.83#ibcon#about to clear, iclass 16 cls_cnt 0 2006.224.07:42:50.83#ibcon#cleared, iclass 16 cls_cnt 0 2006.224.07:42:50.83$vc4f8/vb=2,4 2006.224.07:42:50.83#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.224.07:42:50.84#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.224.07:42:50.84#ibcon#ireg 11 cls_cnt 2 2006.224.07:42:50.84#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.224.07:42:50.88#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.224.07:42:50.88#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.224.07:42:50.88#ibcon#enter wrdev, iclass 18, count 2 2006.224.07:42:50.88#ibcon#first serial, iclass 18, count 2 2006.224.07:42:50.88#ibcon#enter sib2, iclass 18, count 2 2006.224.07:42:50.88#ibcon#flushed, iclass 18, count 2 2006.224.07:42:50.88#ibcon#about to write, iclass 18, count 2 2006.224.07:42:50.88#ibcon#wrote, iclass 18, count 2 2006.224.07:42:50.88#ibcon#about to read 3, iclass 18, count 2 2006.224.07:42:50.90#ibcon#read 3, iclass 18, count 2 2006.224.07:42:50.90#ibcon#about to read 4, iclass 18, count 2 2006.224.07:42:50.90#ibcon#read 4, iclass 18, count 2 2006.224.07:42:50.90#ibcon#about to read 5, iclass 18, count 2 2006.224.07:42:50.90#ibcon#read 5, iclass 18, count 2 2006.224.07:42:50.90#ibcon#about to read 6, iclass 18, count 2 2006.224.07:42:50.90#ibcon#read 6, iclass 18, count 2 2006.224.07:42:50.90#ibcon#end of sib2, iclass 18, count 2 2006.224.07:42:50.90#ibcon#*mode == 0, iclass 18, count 2 2006.224.07:42:50.90#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.224.07:42:50.90#ibcon#[27=AT02-04\r\n] 2006.224.07:42:50.90#ibcon#*before write, iclass 18, count 2 2006.224.07:42:50.90#ibcon#enter sib2, iclass 18, count 2 2006.224.07:42:50.90#ibcon#flushed, iclass 18, count 2 2006.224.07:42:50.90#ibcon#about to write, iclass 18, count 2 2006.224.07:42:50.90#ibcon#wrote, iclass 18, count 2 2006.224.07:42:50.90#ibcon#about to read 3, iclass 18, count 2 2006.224.07:42:50.93#ibcon#read 3, iclass 18, count 2 2006.224.07:42:50.93#ibcon#about to read 4, iclass 18, count 2 2006.224.07:42:50.93#ibcon#read 4, iclass 18, count 2 2006.224.07:42:50.93#ibcon#about to read 5, iclass 18, count 2 2006.224.07:42:50.93#ibcon#read 5, iclass 18, count 2 2006.224.07:42:50.93#ibcon#about to read 6, iclass 18, count 2 2006.224.07:42:50.93#ibcon#read 6, iclass 18, count 2 2006.224.07:42:50.93#ibcon#end of sib2, iclass 18, count 2 2006.224.07:42:50.93#ibcon#*after write, iclass 18, count 2 2006.224.07:42:50.93#ibcon#*before return 0, iclass 18, count 2 2006.224.07:42:50.93#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.224.07:42:50.93#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.224.07:42:50.93#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.224.07:42:50.93#ibcon#ireg 7 cls_cnt 0 2006.224.07:42:50.93#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.224.07:42:51.05#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.224.07:42:51.05#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.224.07:42:51.05#ibcon#enter wrdev, iclass 18, count 0 2006.224.07:42:51.05#ibcon#first serial, iclass 18, count 0 2006.224.07:42:51.05#ibcon#enter sib2, iclass 18, count 0 2006.224.07:42:51.05#ibcon#flushed, iclass 18, count 0 2006.224.07:42:51.05#ibcon#about to write, iclass 18, count 0 2006.224.07:42:51.05#ibcon#wrote, iclass 18, count 0 2006.224.07:42:51.05#ibcon#about to read 3, iclass 18, count 0 2006.224.07:42:51.09#ibcon#read 3, iclass 18, count 0 2006.224.07:42:51.09#ibcon#about to read 4, iclass 18, count 0 2006.224.07:42:51.09#ibcon#read 4, iclass 18, count 0 2006.224.07:42:51.09#ibcon#about to read 5, iclass 18, count 0 2006.224.07:42:51.09#ibcon#read 5, iclass 18, count 0 2006.224.07:42:51.09#ibcon#about to read 6, iclass 18, count 0 2006.224.07:42:51.09#ibcon#read 6, iclass 18, count 0 2006.224.07:42:51.09#ibcon#end of sib2, iclass 18, count 0 2006.224.07:42:51.09#ibcon#*mode == 0, iclass 18, count 0 2006.224.07:42:51.09#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.224.07:42:51.09#ibcon#[27=USB\r\n] 2006.224.07:42:51.09#ibcon#*before write, iclass 18, count 0 2006.224.07:42:51.09#ibcon#enter sib2, iclass 18, count 0 2006.224.07:42:51.09#ibcon#flushed, iclass 18, count 0 2006.224.07:42:51.09#ibcon#about to write, iclass 18, count 0 2006.224.07:42:51.09#ibcon#wrote, iclass 18, count 0 2006.224.07:42:51.09#ibcon#about to read 3, iclass 18, count 0 2006.224.07:42:51.11#ibcon#read 3, iclass 18, count 0 2006.224.07:42:51.11#ibcon#about to read 4, iclass 18, count 0 2006.224.07:42:51.11#ibcon#read 4, iclass 18, count 0 2006.224.07:42:51.11#ibcon#about to read 5, iclass 18, count 0 2006.224.07:42:51.11#ibcon#read 5, iclass 18, count 0 2006.224.07:42:51.11#ibcon#about to read 6, iclass 18, count 0 2006.224.07:42:51.11#ibcon#read 6, iclass 18, count 0 2006.224.07:42:51.11#ibcon#end of sib2, iclass 18, count 0 2006.224.07:42:51.11#ibcon#*after write, iclass 18, count 0 2006.224.07:42:51.11#ibcon#*before return 0, iclass 18, count 0 2006.224.07:42:51.11#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.224.07:42:51.11#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.224.07:42:51.11#ibcon#about to clear, iclass 18 cls_cnt 0 2006.224.07:42:51.11#ibcon#cleared, iclass 18 cls_cnt 0 2006.224.07:42:51.11$vc4f8/vblo=3,656.99 2006.224.07:42:51.11#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.224.07:42:51.11#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.224.07:42:51.11#ibcon#ireg 17 cls_cnt 0 2006.224.07:42:51.12#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.224.07:42:51.12#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.224.07:42:51.12#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.224.07:42:51.12#ibcon#enter wrdev, iclass 20, count 0 2006.224.07:42:51.12#ibcon#first serial, iclass 20, count 0 2006.224.07:42:51.12#ibcon#enter sib2, iclass 20, count 0 2006.224.07:42:51.12#ibcon#flushed, iclass 20, count 0 2006.224.07:42:51.12#ibcon#about to write, iclass 20, count 0 2006.224.07:42:51.12#ibcon#wrote, iclass 20, count 0 2006.224.07:42:51.12#ibcon#about to read 3, iclass 20, count 0 2006.224.07:42:51.13#ibcon#read 3, iclass 20, count 0 2006.224.07:42:51.13#ibcon#about to read 4, iclass 20, count 0 2006.224.07:42:51.13#ibcon#read 4, iclass 20, count 0 2006.224.07:42:51.13#ibcon#about to read 5, iclass 20, count 0 2006.224.07:42:51.13#ibcon#read 5, iclass 20, count 0 2006.224.07:42:51.13#ibcon#about to read 6, iclass 20, count 0 2006.224.07:42:51.13#ibcon#read 6, iclass 20, count 0 2006.224.07:42:51.13#ibcon#end of sib2, iclass 20, count 0 2006.224.07:42:51.13#ibcon#*mode == 0, iclass 20, count 0 2006.224.07:42:51.13#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.224.07:42:51.13#ibcon#[28=FRQ=03,656.99\r\n] 2006.224.07:42:51.13#ibcon#*before write, iclass 20, count 0 2006.224.07:42:51.13#ibcon#enter sib2, iclass 20, count 0 2006.224.07:42:51.13#ibcon#flushed, iclass 20, count 0 2006.224.07:42:51.13#ibcon#about to write, iclass 20, count 0 2006.224.07:42:51.13#ibcon#wrote, iclass 20, count 0 2006.224.07:42:51.13#ibcon#about to read 3, iclass 20, count 0 2006.224.07:42:51.17#ibcon#read 3, iclass 20, count 0 2006.224.07:42:51.17#ibcon#about to read 4, iclass 20, count 0 2006.224.07:42:51.17#ibcon#read 4, iclass 20, count 0 2006.224.07:42:51.17#ibcon#about to read 5, iclass 20, count 0 2006.224.07:42:51.17#ibcon#read 5, iclass 20, count 0 2006.224.07:42:51.17#ibcon#about to read 6, iclass 20, count 0 2006.224.07:42:51.17#ibcon#read 6, iclass 20, count 0 2006.224.07:42:51.17#ibcon#end of sib2, iclass 20, count 0 2006.224.07:42:51.17#ibcon#*after write, iclass 20, count 0 2006.224.07:42:51.17#ibcon#*before return 0, iclass 20, count 0 2006.224.07:42:51.17#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.224.07:42:51.17#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.224.07:42:51.17#ibcon#about to clear, iclass 20 cls_cnt 0 2006.224.07:42:51.17#ibcon#cleared, iclass 20 cls_cnt 0 2006.224.07:42:51.18$vc4f8/vb=3,4 2006.224.07:42:51.18#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.224.07:42:51.18#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.224.07:42:51.18#ibcon#ireg 11 cls_cnt 2 2006.224.07:42:51.18#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.224.07:42:51.22#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.224.07:42:51.22#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.224.07:42:51.22#ibcon#enter wrdev, iclass 22, count 2 2006.224.07:42:51.22#ibcon#first serial, iclass 22, count 2 2006.224.07:42:51.22#ibcon#enter sib2, iclass 22, count 2 2006.224.07:42:51.22#ibcon#flushed, iclass 22, count 2 2006.224.07:42:51.22#ibcon#about to write, iclass 22, count 2 2006.224.07:42:51.22#ibcon#wrote, iclass 22, count 2 2006.224.07:42:51.22#ibcon#about to read 3, iclass 22, count 2 2006.224.07:42:51.25#ibcon#read 3, iclass 22, count 2 2006.224.07:42:51.25#ibcon#about to read 4, iclass 22, count 2 2006.224.07:42:51.25#ibcon#read 4, iclass 22, count 2 2006.224.07:42:51.25#ibcon#about to read 5, iclass 22, count 2 2006.224.07:42:51.25#ibcon#read 5, iclass 22, count 2 2006.224.07:42:51.25#ibcon#about to read 6, iclass 22, count 2 2006.224.07:42:51.25#ibcon#read 6, iclass 22, count 2 2006.224.07:42:51.25#ibcon#end of sib2, iclass 22, count 2 2006.224.07:42:51.25#ibcon#*mode == 0, iclass 22, count 2 2006.224.07:42:51.25#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.224.07:42:51.25#ibcon#[27=AT03-04\r\n] 2006.224.07:42:51.25#ibcon#*before write, iclass 22, count 2 2006.224.07:42:51.25#ibcon#enter sib2, iclass 22, count 2 2006.224.07:42:51.25#ibcon#flushed, iclass 22, count 2 2006.224.07:42:51.25#ibcon#about to write, iclass 22, count 2 2006.224.07:42:51.25#ibcon#wrote, iclass 22, count 2 2006.224.07:42:51.25#ibcon#about to read 3, iclass 22, count 2 2006.224.07:42:51.28#ibcon#read 3, iclass 22, count 2 2006.224.07:42:51.28#ibcon#about to read 4, iclass 22, count 2 2006.224.07:42:51.28#ibcon#read 4, iclass 22, count 2 2006.224.07:42:51.28#ibcon#about to read 5, iclass 22, count 2 2006.224.07:42:51.28#ibcon#read 5, iclass 22, count 2 2006.224.07:42:51.28#ibcon#about to read 6, iclass 22, count 2 2006.224.07:42:51.28#ibcon#read 6, iclass 22, count 2 2006.224.07:42:51.28#ibcon#end of sib2, iclass 22, count 2 2006.224.07:42:51.28#ibcon#*after write, iclass 22, count 2 2006.224.07:42:51.28#ibcon#*before return 0, iclass 22, count 2 2006.224.07:42:51.28#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.224.07:42:51.28#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.224.07:42:51.28#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.224.07:42:51.28#ibcon#ireg 7 cls_cnt 0 2006.224.07:42:51.28#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.224.07:42:51.40#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.224.07:42:51.40#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.224.07:42:51.40#ibcon#enter wrdev, iclass 22, count 0 2006.224.07:42:51.40#ibcon#first serial, iclass 22, count 0 2006.224.07:42:51.40#ibcon#enter sib2, iclass 22, count 0 2006.224.07:42:51.40#ibcon#flushed, iclass 22, count 0 2006.224.07:42:51.40#ibcon#about to write, iclass 22, count 0 2006.224.07:42:51.40#ibcon#wrote, iclass 22, count 0 2006.224.07:42:51.40#ibcon#about to read 3, iclass 22, count 0 2006.224.07:42:51.42#ibcon#read 3, iclass 22, count 0 2006.224.07:42:51.42#ibcon#about to read 4, iclass 22, count 0 2006.224.07:42:51.42#ibcon#read 4, iclass 22, count 0 2006.224.07:42:51.42#ibcon#about to read 5, iclass 22, count 0 2006.224.07:42:51.42#ibcon#read 5, iclass 22, count 0 2006.224.07:42:51.42#ibcon#about to read 6, iclass 22, count 0 2006.224.07:42:51.42#ibcon#read 6, iclass 22, count 0 2006.224.07:42:51.42#ibcon#end of sib2, iclass 22, count 0 2006.224.07:42:51.42#ibcon#*mode == 0, iclass 22, count 0 2006.224.07:42:51.42#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.224.07:42:51.42#ibcon#[27=USB\r\n] 2006.224.07:42:51.42#ibcon#*before write, iclass 22, count 0 2006.224.07:42:51.42#ibcon#enter sib2, iclass 22, count 0 2006.224.07:42:51.42#ibcon#flushed, iclass 22, count 0 2006.224.07:42:51.42#ibcon#about to write, iclass 22, count 0 2006.224.07:42:51.42#ibcon#wrote, iclass 22, count 0 2006.224.07:42:51.42#ibcon#about to read 3, iclass 22, count 0 2006.224.07:42:51.45#ibcon#read 3, iclass 22, count 0 2006.224.07:42:51.45#ibcon#about to read 4, iclass 22, count 0 2006.224.07:42:51.45#ibcon#read 4, iclass 22, count 0 2006.224.07:42:51.45#ibcon#about to read 5, iclass 22, count 0 2006.224.07:42:51.45#ibcon#read 5, iclass 22, count 0 2006.224.07:42:51.45#ibcon#about to read 6, iclass 22, count 0 2006.224.07:42:51.45#ibcon#read 6, iclass 22, count 0 2006.224.07:42:51.45#ibcon#end of sib2, iclass 22, count 0 2006.224.07:42:51.45#ibcon#*after write, iclass 22, count 0 2006.224.07:42:51.45#ibcon#*before return 0, iclass 22, count 0 2006.224.07:42:51.45#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.224.07:42:51.45#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.224.07:42:51.45#ibcon#about to clear, iclass 22 cls_cnt 0 2006.224.07:42:51.45#ibcon#cleared, iclass 22 cls_cnt 0 2006.224.07:42:51.45$vc4f8/vblo=4,712.99 2006.224.07:42:51.45#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.224.07:42:51.45#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.224.07:42:51.45#ibcon#ireg 17 cls_cnt 0 2006.224.07:42:51.45#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.224.07:42:51.46#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.224.07:42:51.46#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.224.07:42:51.46#ibcon#enter wrdev, iclass 24, count 0 2006.224.07:42:51.46#ibcon#first serial, iclass 24, count 0 2006.224.07:42:51.46#ibcon#enter sib2, iclass 24, count 0 2006.224.07:42:51.46#ibcon#flushed, iclass 24, count 0 2006.224.07:42:51.46#ibcon#about to write, iclass 24, count 0 2006.224.07:42:51.46#ibcon#wrote, iclass 24, count 0 2006.224.07:42:51.46#ibcon#about to read 3, iclass 24, count 0 2006.224.07:42:51.47#ibcon#read 3, iclass 24, count 0 2006.224.07:42:51.47#ibcon#about to read 4, iclass 24, count 0 2006.224.07:42:51.47#ibcon#read 4, iclass 24, count 0 2006.224.07:42:51.47#ibcon#about to read 5, iclass 24, count 0 2006.224.07:42:51.47#ibcon#read 5, iclass 24, count 0 2006.224.07:42:51.47#ibcon#about to read 6, iclass 24, count 0 2006.224.07:42:51.47#ibcon#read 6, iclass 24, count 0 2006.224.07:42:51.47#ibcon#end of sib2, iclass 24, count 0 2006.224.07:42:51.47#ibcon#*mode == 0, iclass 24, count 0 2006.224.07:42:51.47#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.224.07:42:51.47#ibcon#[28=FRQ=04,712.99\r\n] 2006.224.07:42:51.47#ibcon#*before write, iclass 24, count 0 2006.224.07:42:51.47#ibcon#enter sib2, iclass 24, count 0 2006.224.07:42:51.47#ibcon#flushed, iclass 24, count 0 2006.224.07:42:51.47#ibcon#about to write, iclass 24, count 0 2006.224.07:42:51.47#ibcon#wrote, iclass 24, count 0 2006.224.07:42:51.47#ibcon#about to read 3, iclass 24, count 0 2006.224.07:42:51.51#ibcon#read 3, iclass 24, count 0 2006.224.07:42:51.51#ibcon#about to read 4, iclass 24, count 0 2006.224.07:42:51.51#ibcon#read 4, iclass 24, count 0 2006.224.07:42:51.51#ibcon#about to read 5, iclass 24, count 0 2006.224.07:42:51.51#ibcon#read 5, iclass 24, count 0 2006.224.07:42:51.51#ibcon#about to read 6, iclass 24, count 0 2006.224.07:42:51.51#ibcon#read 6, iclass 24, count 0 2006.224.07:42:51.51#ibcon#end of sib2, iclass 24, count 0 2006.224.07:42:51.51#ibcon#*after write, iclass 24, count 0 2006.224.07:42:51.51#ibcon#*before return 0, iclass 24, count 0 2006.224.07:42:51.51#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.224.07:42:51.51#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.224.07:42:51.51#ibcon#about to clear, iclass 24 cls_cnt 0 2006.224.07:42:51.51#ibcon#cleared, iclass 24 cls_cnt 0 2006.224.07:42:51.51$vc4f8/vb=4,4 2006.224.07:42:51.51#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.224.07:42:51.52#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.224.07:42:51.52#ibcon#ireg 11 cls_cnt 2 2006.224.07:42:51.52#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.224.07:42:51.56#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.224.07:42:51.56#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.224.07:42:51.56#ibcon#enter wrdev, iclass 26, count 2 2006.224.07:42:51.56#ibcon#first serial, iclass 26, count 2 2006.224.07:42:51.56#ibcon#enter sib2, iclass 26, count 2 2006.224.07:42:51.56#ibcon#flushed, iclass 26, count 2 2006.224.07:42:51.56#ibcon#about to write, iclass 26, count 2 2006.224.07:42:51.56#ibcon#wrote, iclass 26, count 2 2006.224.07:42:51.56#ibcon#about to read 3, iclass 26, count 2 2006.224.07:42:51.58#ibcon#read 3, iclass 26, count 2 2006.224.07:42:51.58#ibcon#about to read 4, iclass 26, count 2 2006.224.07:42:51.58#ibcon#read 4, iclass 26, count 2 2006.224.07:42:51.58#ibcon#about to read 5, iclass 26, count 2 2006.224.07:42:51.58#ibcon#read 5, iclass 26, count 2 2006.224.07:42:51.58#ibcon#about to read 6, iclass 26, count 2 2006.224.07:42:51.58#ibcon#read 6, iclass 26, count 2 2006.224.07:42:51.58#ibcon#end of sib2, iclass 26, count 2 2006.224.07:42:51.58#ibcon#*mode == 0, iclass 26, count 2 2006.224.07:42:51.58#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.224.07:42:51.58#ibcon#[27=AT04-04\r\n] 2006.224.07:42:51.58#ibcon#*before write, iclass 26, count 2 2006.224.07:42:51.58#ibcon#enter sib2, iclass 26, count 2 2006.224.07:42:51.58#ibcon#flushed, iclass 26, count 2 2006.224.07:42:51.58#ibcon#about to write, iclass 26, count 2 2006.224.07:42:51.58#ibcon#wrote, iclass 26, count 2 2006.224.07:42:51.58#ibcon#about to read 3, iclass 26, count 2 2006.224.07:42:51.61#ibcon#read 3, iclass 26, count 2 2006.224.07:42:51.61#ibcon#about to read 4, iclass 26, count 2 2006.224.07:42:51.61#ibcon#read 4, iclass 26, count 2 2006.224.07:42:51.61#ibcon#about to read 5, iclass 26, count 2 2006.224.07:42:51.61#ibcon#read 5, iclass 26, count 2 2006.224.07:42:51.61#ibcon#about to read 6, iclass 26, count 2 2006.224.07:42:51.61#ibcon#read 6, iclass 26, count 2 2006.224.07:42:51.61#ibcon#end of sib2, iclass 26, count 2 2006.224.07:42:51.61#ibcon#*after write, iclass 26, count 2 2006.224.07:42:51.61#ibcon#*before return 0, iclass 26, count 2 2006.224.07:42:51.61#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.224.07:42:51.61#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.224.07:42:51.61#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.224.07:42:51.61#ibcon#ireg 7 cls_cnt 0 2006.224.07:42:51.61#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.224.07:42:51.73#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.224.07:42:51.73#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.224.07:42:51.73#ibcon#enter wrdev, iclass 26, count 0 2006.224.07:42:51.73#ibcon#first serial, iclass 26, count 0 2006.224.07:42:51.73#ibcon#enter sib2, iclass 26, count 0 2006.224.07:42:51.73#ibcon#flushed, iclass 26, count 0 2006.224.07:42:51.73#ibcon#about to write, iclass 26, count 0 2006.224.07:42:51.73#ibcon#wrote, iclass 26, count 0 2006.224.07:42:51.73#ibcon#about to read 3, iclass 26, count 0 2006.224.07:42:51.75#ibcon#read 3, iclass 26, count 0 2006.224.07:42:51.75#ibcon#about to read 4, iclass 26, count 0 2006.224.07:42:51.75#ibcon#read 4, iclass 26, count 0 2006.224.07:42:51.75#ibcon#about to read 5, iclass 26, count 0 2006.224.07:42:51.75#ibcon#read 5, iclass 26, count 0 2006.224.07:42:51.75#ibcon#about to read 6, iclass 26, count 0 2006.224.07:42:51.75#ibcon#read 6, iclass 26, count 0 2006.224.07:42:51.75#ibcon#end of sib2, iclass 26, count 0 2006.224.07:42:51.75#ibcon#*mode == 0, iclass 26, count 0 2006.224.07:42:51.75#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.224.07:42:51.75#ibcon#[27=USB\r\n] 2006.224.07:42:51.75#ibcon#*before write, iclass 26, count 0 2006.224.07:42:51.75#ibcon#enter sib2, iclass 26, count 0 2006.224.07:42:51.75#ibcon#flushed, iclass 26, count 0 2006.224.07:42:51.75#ibcon#about to write, iclass 26, count 0 2006.224.07:42:51.75#ibcon#wrote, iclass 26, count 0 2006.224.07:42:51.75#ibcon#about to read 3, iclass 26, count 0 2006.224.07:42:51.78#ibcon#read 3, iclass 26, count 0 2006.224.07:42:51.78#ibcon#about to read 4, iclass 26, count 0 2006.224.07:42:51.78#ibcon#read 4, iclass 26, count 0 2006.224.07:42:51.78#ibcon#about to read 5, iclass 26, count 0 2006.224.07:42:51.78#ibcon#read 5, iclass 26, count 0 2006.224.07:42:51.78#ibcon#about to read 6, iclass 26, count 0 2006.224.07:42:51.78#ibcon#read 6, iclass 26, count 0 2006.224.07:42:51.78#ibcon#end of sib2, iclass 26, count 0 2006.224.07:42:51.78#ibcon#*after write, iclass 26, count 0 2006.224.07:42:51.78#ibcon#*before return 0, iclass 26, count 0 2006.224.07:42:51.78#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.224.07:42:51.78#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.224.07:42:51.78#ibcon#about to clear, iclass 26 cls_cnt 0 2006.224.07:42:51.78#ibcon#cleared, iclass 26 cls_cnt 0 2006.224.07:42:51.78$vc4f8/vblo=5,744.99 2006.224.07:42:51.78#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.224.07:42:51.78#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.224.07:42:51.78#ibcon#ireg 17 cls_cnt 0 2006.224.07:42:51.78#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.224.07:42:51.79#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.224.07:42:51.79#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.224.07:42:51.79#ibcon#enter wrdev, iclass 28, count 0 2006.224.07:42:51.79#ibcon#first serial, iclass 28, count 0 2006.224.07:42:51.79#ibcon#enter sib2, iclass 28, count 0 2006.224.07:42:51.79#ibcon#flushed, iclass 28, count 0 2006.224.07:42:51.79#ibcon#about to write, iclass 28, count 0 2006.224.07:42:51.79#ibcon#wrote, iclass 28, count 0 2006.224.07:42:51.79#ibcon#about to read 3, iclass 28, count 0 2006.224.07:42:51.80#ibcon#read 3, iclass 28, count 0 2006.224.07:42:51.80#ibcon#about to read 4, iclass 28, count 0 2006.224.07:42:51.80#ibcon#read 4, iclass 28, count 0 2006.224.07:42:51.80#ibcon#about to read 5, iclass 28, count 0 2006.224.07:42:51.80#ibcon#read 5, iclass 28, count 0 2006.224.07:42:51.80#ibcon#about to read 6, iclass 28, count 0 2006.224.07:42:51.80#ibcon#read 6, iclass 28, count 0 2006.224.07:42:51.80#ibcon#end of sib2, iclass 28, count 0 2006.224.07:42:51.80#ibcon#*mode == 0, iclass 28, count 0 2006.224.07:42:51.80#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.224.07:42:51.80#ibcon#[28=FRQ=05,744.99\r\n] 2006.224.07:42:51.80#ibcon#*before write, iclass 28, count 0 2006.224.07:42:51.80#ibcon#enter sib2, iclass 28, count 0 2006.224.07:42:51.80#ibcon#flushed, iclass 28, count 0 2006.224.07:42:51.80#ibcon#about to write, iclass 28, count 0 2006.224.07:42:51.80#ibcon#wrote, iclass 28, count 0 2006.224.07:42:51.80#ibcon#about to read 3, iclass 28, count 0 2006.224.07:42:51.84#ibcon#read 3, iclass 28, count 0 2006.224.07:42:51.84#ibcon#about to read 4, iclass 28, count 0 2006.224.07:42:51.84#ibcon#read 4, iclass 28, count 0 2006.224.07:42:51.84#ibcon#about to read 5, iclass 28, count 0 2006.224.07:42:51.84#ibcon#read 5, iclass 28, count 0 2006.224.07:42:51.84#ibcon#about to read 6, iclass 28, count 0 2006.224.07:42:51.84#ibcon#read 6, iclass 28, count 0 2006.224.07:42:51.84#ibcon#end of sib2, iclass 28, count 0 2006.224.07:42:51.84#ibcon#*after write, iclass 28, count 0 2006.224.07:42:51.84#ibcon#*before return 0, iclass 28, count 0 2006.224.07:42:51.84#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.224.07:42:51.84#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.224.07:42:51.84#ibcon#about to clear, iclass 28 cls_cnt 0 2006.224.07:42:51.84#ibcon#cleared, iclass 28 cls_cnt 0 2006.224.07:42:51.84$vc4f8/vb=5,4 2006.224.07:42:51.84#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.224.07:42:51.84#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.224.07:42:51.85#ibcon#ireg 11 cls_cnt 2 2006.224.07:42:51.85#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.224.07:42:51.90#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.224.07:42:51.90#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.224.07:42:51.90#ibcon#enter wrdev, iclass 30, count 2 2006.224.07:42:51.90#ibcon#first serial, iclass 30, count 2 2006.224.07:42:51.90#ibcon#enter sib2, iclass 30, count 2 2006.224.07:42:51.90#ibcon#flushed, iclass 30, count 2 2006.224.07:42:51.90#ibcon#about to write, iclass 30, count 2 2006.224.07:42:51.90#ibcon#wrote, iclass 30, count 2 2006.224.07:42:51.90#ibcon#about to read 3, iclass 30, count 2 2006.224.07:42:51.91#ibcon#read 3, iclass 30, count 2 2006.224.07:42:51.91#ibcon#about to read 4, iclass 30, count 2 2006.224.07:42:51.91#ibcon#read 4, iclass 30, count 2 2006.224.07:42:51.91#ibcon#about to read 5, iclass 30, count 2 2006.224.07:42:51.91#ibcon#read 5, iclass 30, count 2 2006.224.07:42:51.91#ibcon#about to read 6, iclass 30, count 2 2006.224.07:42:51.91#ibcon#read 6, iclass 30, count 2 2006.224.07:42:51.91#ibcon#end of sib2, iclass 30, count 2 2006.224.07:42:51.91#ibcon#*mode == 0, iclass 30, count 2 2006.224.07:42:51.91#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.224.07:42:51.91#ibcon#[27=AT05-04\r\n] 2006.224.07:42:51.91#ibcon#*before write, iclass 30, count 2 2006.224.07:42:51.91#ibcon#enter sib2, iclass 30, count 2 2006.224.07:42:51.91#ibcon#flushed, iclass 30, count 2 2006.224.07:42:51.91#ibcon#about to write, iclass 30, count 2 2006.224.07:42:51.91#ibcon#wrote, iclass 30, count 2 2006.224.07:42:51.91#ibcon#about to read 3, iclass 30, count 2 2006.224.07:42:51.94#ibcon#read 3, iclass 30, count 2 2006.224.07:42:51.94#ibcon#about to read 4, iclass 30, count 2 2006.224.07:42:51.94#ibcon#read 4, iclass 30, count 2 2006.224.07:42:51.94#ibcon#about to read 5, iclass 30, count 2 2006.224.07:42:51.94#ibcon#read 5, iclass 30, count 2 2006.224.07:42:51.94#ibcon#about to read 6, iclass 30, count 2 2006.224.07:42:51.94#ibcon#read 6, iclass 30, count 2 2006.224.07:42:51.94#ibcon#end of sib2, iclass 30, count 2 2006.224.07:42:51.94#ibcon#*after write, iclass 30, count 2 2006.224.07:42:51.94#ibcon#*before return 0, iclass 30, count 2 2006.224.07:42:51.94#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.224.07:42:51.94#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.224.07:42:51.94#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.224.07:42:51.94#ibcon#ireg 7 cls_cnt 0 2006.224.07:42:51.94#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.224.07:42:52.06#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.224.07:42:52.06#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.224.07:42:52.06#ibcon#enter wrdev, iclass 30, count 0 2006.224.07:42:52.06#ibcon#first serial, iclass 30, count 0 2006.224.07:42:52.06#ibcon#enter sib2, iclass 30, count 0 2006.224.07:42:52.06#ibcon#flushed, iclass 30, count 0 2006.224.07:42:52.06#ibcon#about to write, iclass 30, count 0 2006.224.07:42:52.06#ibcon#wrote, iclass 30, count 0 2006.224.07:42:52.06#ibcon#about to read 3, iclass 30, count 0 2006.224.07:42:52.08#ibcon#read 3, iclass 30, count 0 2006.224.07:42:52.08#ibcon#about to read 4, iclass 30, count 0 2006.224.07:42:52.08#ibcon#read 4, iclass 30, count 0 2006.224.07:42:52.08#ibcon#about to read 5, iclass 30, count 0 2006.224.07:42:52.08#ibcon#read 5, iclass 30, count 0 2006.224.07:42:52.08#ibcon#about to read 6, iclass 30, count 0 2006.224.07:42:52.08#ibcon#read 6, iclass 30, count 0 2006.224.07:42:52.08#ibcon#end of sib2, iclass 30, count 0 2006.224.07:42:52.08#ibcon#*mode == 0, iclass 30, count 0 2006.224.07:42:52.08#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.224.07:42:52.08#ibcon#[27=USB\r\n] 2006.224.07:42:52.08#ibcon#*before write, iclass 30, count 0 2006.224.07:42:52.08#ibcon#enter sib2, iclass 30, count 0 2006.224.07:42:52.08#ibcon#flushed, iclass 30, count 0 2006.224.07:42:52.08#ibcon#about to write, iclass 30, count 0 2006.224.07:42:52.08#ibcon#wrote, iclass 30, count 0 2006.224.07:42:52.08#ibcon#about to read 3, iclass 30, count 0 2006.224.07:42:52.11#ibcon#read 3, iclass 30, count 0 2006.224.07:42:52.11#ibcon#about to read 4, iclass 30, count 0 2006.224.07:42:52.11#ibcon#read 4, iclass 30, count 0 2006.224.07:42:52.11#ibcon#about to read 5, iclass 30, count 0 2006.224.07:42:52.11#ibcon#read 5, iclass 30, count 0 2006.224.07:42:52.11#ibcon#about to read 6, iclass 30, count 0 2006.224.07:42:52.11#ibcon#read 6, iclass 30, count 0 2006.224.07:42:52.11#ibcon#end of sib2, iclass 30, count 0 2006.224.07:42:52.11#ibcon#*after write, iclass 30, count 0 2006.224.07:42:52.11#ibcon#*before return 0, iclass 30, count 0 2006.224.07:42:52.11#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.224.07:42:52.11#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.224.07:42:52.11#ibcon#about to clear, iclass 30 cls_cnt 0 2006.224.07:42:52.11#ibcon#cleared, iclass 30 cls_cnt 0 2006.224.07:42:52.11$vc4f8/vblo=6,752.99 2006.224.07:42:52.12#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.224.07:42:52.12#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.224.07:42:52.12#ibcon#ireg 17 cls_cnt 0 2006.224.07:42:52.12#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.224.07:42:52.12#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.224.07:42:52.12#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.224.07:42:52.12#ibcon#enter wrdev, iclass 32, count 0 2006.224.07:42:52.12#ibcon#first serial, iclass 32, count 0 2006.224.07:42:52.12#ibcon#enter sib2, iclass 32, count 0 2006.224.07:42:52.12#ibcon#flushed, iclass 32, count 0 2006.224.07:42:52.12#ibcon#about to write, iclass 32, count 0 2006.224.07:42:52.12#ibcon#wrote, iclass 32, count 0 2006.224.07:42:52.12#ibcon#about to read 3, iclass 32, count 0 2006.224.07:42:52.13#ibcon#read 3, iclass 32, count 0 2006.224.07:42:52.13#ibcon#about to read 4, iclass 32, count 0 2006.224.07:42:52.13#ibcon#read 4, iclass 32, count 0 2006.224.07:42:52.13#ibcon#about to read 5, iclass 32, count 0 2006.224.07:42:52.13#ibcon#read 5, iclass 32, count 0 2006.224.07:42:52.13#ibcon#about to read 6, iclass 32, count 0 2006.224.07:42:52.13#ibcon#read 6, iclass 32, count 0 2006.224.07:42:52.13#ibcon#end of sib2, iclass 32, count 0 2006.224.07:42:52.13#ibcon#*mode == 0, iclass 32, count 0 2006.224.07:42:52.13#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.224.07:42:52.13#ibcon#[28=FRQ=06,752.99\r\n] 2006.224.07:42:52.13#ibcon#*before write, iclass 32, count 0 2006.224.07:42:52.13#ibcon#enter sib2, iclass 32, count 0 2006.224.07:42:52.13#ibcon#flushed, iclass 32, count 0 2006.224.07:42:52.13#ibcon#about to write, iclass 32, count 0 2006.224.07:42:52.13#ibcon#wrote, iclass 32, count 0 2006.224.07:42:52.13#ibcon#about to read 3, iclass 32, count 0 2006.224.07:42:52.17#ibcon#read 3, iclass 32, count 0 2006.224.07:42:52.17#ibcon#about to read 4, iclass 32, count 0 2006.224.07:42:52.17#ibcon#read 4, iclass 32, count 0 2006.224.07:42:52.17#ibcon#about to read 5, iclass 32, count 0 2006.224.07:42:52.17#ibcon#read 5, iclass 32, count 0 2006.224.07:42:52.17#ibcon#about to read 6, iclass 32, count 0 2006.224.07:42:52.17#ibcon#read 6, iclass 32, count 0 2006.224.07:42:52.17#ibcon#end of sib2, iclass 32, count 0 2006.224.07:42:52.17#ibcon#*after write, iclass 32, count 0 2006.224.07:42:52.17#ibcon#*before return 0, iclass 32, count 0 2006.224.07:42:52.17#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.224.07:42:52.17#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.224.07:42:52.17#ibcon#about to clear, iclass 32 cls_cnt 0 2006.224.07:42:52.17#ibcon#cleared, iclass 32 cls_cnt 0 2006.224.07:42:52.17$vc4f8/vb=6,4 2006.224.07:42:52.17#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.224.07:42:52.17#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.224.07:42:52.17#ibcon#ireg 11 cls_cnt 2 2006.224.07:42:52.17#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.224.07:42:52.23#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.224.07:42:52.23#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.224.07:42:52.23#ibcon#enter wrdev, iclass 34, count 2 2006.224.07:42:52.23#ibcon#first serial, iclass 34, count 2 2006.224.07:42:52.23#ibcon#enter sib2, iclass 34, count 2 2006.224.07:42:52.23#ibcon#flushed, iclass 34, count 2 2006.224.07:42:52.23#ibcon#about to write, iclass 34, count 2 2006.224.07:42:52.23#ibcon#wrote, iclass 34, count 2 2006.224.07:42:52.23#ibcon#about to read 3, iclass 34, count 2 2006.224.07:42:52.25#ibcon#read 3, iclass 34, count 2 2006.224.07:42:52.25#ibcon#about to read 4, iclass 34, count 2 2006.224.07:42:52.25#ibcon#read 4, iclass 34, count 2 2006.224.07:42:52.25#ibcon#about to read 5, iclass 34, count 2 2006.224.07:42:52.25#ibcon#read 5, iclass 34, count 2 2006.224.07:42:52.25#ibcon#about to read 6, iclass 34, count 2 2006.224.07:42:52.25#ibcon#read 6, iclass 34, count 2 2006.224.07:42:52.25#ibcon#end of sib2, iclass 34, count 2 2006.224.07:42:52.25#ibcon#*mode == 0, iclass 34, count 2 2006.224.07:42:52.25#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.224.07:42:52.25#ibcon#[27=AT06-04\r\n] 2006.224.07:42:52.25#ibcon#*before write, iclass 34, count 2 2006.224.07:42:52.25#ibcon#enter sib2, iclass 34, count 2 2006.224.07:42:52.25#ibcon#flushed, iclass 34, count 2 2006.224.07:42:52.25#ibcon#about to write, iclass 34, count 2 2006.224.07:42:52.25#ibcon#wrote, iclass 34, count 2 2006.224.07:42:52.25#ibcon#about to read 3, iclass 34, count 2 2006.224.07:42:52.28#ibcon#read 3, iclass 34, count 2 2006.224.07:42:52.28#ibcon#about to read 4, iclass 34, count 2 2006.224.07:42:52.28#ibcon#read 4, iclass 34, count 2 2006.224.07:42:52.28#ibcon#about to read 5, iclass 34, count 2 2006.224.07:42:52.28#ibcon#read 5, iclass 34, count 2 2006.224.07:42:52.28#ibcon#about to read 6, iclass 34, count 2 2006.224.07:42:52.28#ibcon#read 6, iclass 34, count 2 2006.224.07:42:52.28#ibcon#end of sib2, iclass 34, count 2 2006.224.07:42:52.28#ibcon#*after write, iclass 34, count 2 2006.224.07:42:52.28#ibcon#*before return 0, iclass 34, count 2 2006.224.07:42:52.28#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.224.07:42:52.28#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.224.07:42:52.28#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.224.07:42:52.28#ibcon#ireg 7 cls_cnt 0 2006.224.07:42:52.28#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.224.07:42:52.40#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.224.07:42:52.40#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.224.07:42:52.40#ibcon#enter wrdev, iclass 34, count 0 2006.224.07:42:52.40#ibcon#first serial, iclass 34, count 0 2006.224.07:42:52.40#ibcon#enter sib2, iclass 34, count 0 2006.224.07:42:52.40#ibcon#flushed, iclass 34, count 0 2006.224.07:42:52.40#ibcon#about to write, iclass 34, count 0 2006.224.07:42:52.40#ibcon#wrote, iclass 34, count 0 2006.224.07:42:52.40#ibcon#about to read 3, iclass 34, count 0 2006.224.07:42:52.42#ibcon#read 3, iclass 34, count 0 2006.224.07:42:52.42#ibcon#about to read 4, iclass 34, count 0 2006.224.07:42:52.42#ibcon#read 4, iclass 34, count 0 2006.224.07:42:52.42#ibcon#about to read 5, iclass 34, count 0 2006.224.07:42:52.42#ibcon#read 5, iclass 34, count 0 2006.224.07:42:52.42#ibcon#about to read 6, iclass 34, count 0 2006.224.07:42:52.42#ibcon#read 6, iclass 34, count 0 2006.224.07:42:52.42#ibcon#end of sib2, iclass 34, count 0 2006.224.07:42:52.42#ibcon#*mode == 0, iclass 34, count 0 2006.224.07:42:52.42#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.224.07:42:52.42#ibcon#[27=USB\r\n] 2006.224.07:42:52.42#ibcon#*before write, iclass 34, count 0 2006.224.07:42:52.42#ibcon#enter sib2, iclass 34, count 0 2006.224.07:42:52.42#ibcon#flushed, iclass 34, count 0 2006.224.07:42:52.42#ibcon#about to write, iclass 34, count 0 2006.224.07:42:52.42#ibcon#wrote, iclass 34, count 0 2006.224.07:42:52.42#ibcon#about to read 3, iclass 34, count 0 2006.224.07:42:52.45#ibcon#read 3, iclass 34, count 0 2006.224.07:42:52.45#ibcon#about to read 4, iclass 34, count 0 2006.224.07:42:52.45#ibcon#read 4, iclass 34, count 0 2006.224.07:42:52.45#ibcon#about to read 5, iclass 34, count 0 2006.224.07:42:52.45#ibcon#read 5, iclass 34, count 0 2006.224.07:42:52.45#ibcon#about to read 6, iclass 34, count 0 2006.224.07:42:52.45#ibcon#read 6, iclass 34, count 0 2006.224.07:42:52.45#ibcon#end of sib2, iclass 34, count 0 2006.224.07:42:52.45#ibcon#*after write, iclass 34, count 0 2006.224.07:42:52.45#ibcon#*before return 0, iclass 34, count 0 2006.224.07:42:52.45#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.224.07:42:52.45#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.224.07:42:52.45#ibcon#about to clear, iclass 34 cls_cnt 0 2006.224.07:42:52.45#ibcon#cleared, iclass 34 cls_cnt 0 2006.224.07:42:52.45$vc4f8/vabw=wide 2006.224.07:42:52.45#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.224.07:42:52.45#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.224.07:42:52.45#ibcon#ireg 8 cls_cnt 0 2006.224.07:42:52.45#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.224.07:42:52.45#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.224.07:42:52.45#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.224.07:42:52.45#ibcon#enter wrdev, iclass 36, count 0 2006.224.07:42:52.46#ibcon#first serial, iclass 36, count 0 2006.224.07:42:52.46#ibcon#enter sib2, iclass 36, count 0 2006.224.07:42:52.46#ibcon#flushed, iclass 36, count 0 2006.224.07:42:52.46#ibcon#about to write, iclass 36, count 0 2006.224.07:42:52.46#ibcon#wrote, iclass 36, count 0 2006.224.07:42:52.46#ibcon#about to read 3, iclass 36, count 0 2006.224.07:42:52.47#ibcon#read 3, iclass 36, count 0 2006.224.07:42:52.47#ibcon#about to read 4, iclass 36, count 0 2006.224.07:42:52.47#ibcon#read 4, iclass 36, count 0 2006.224.07:42:52.47#ibcon#about to read 5, iclass 36, count 0 2006.224.07:42:52.47#ibcon#read 5, iclass 36, count 0 2006.224.07:42:52.47#ibcon#about to read 6, iclass 36, count 0 2006.224.07:42:52.47#ibcon#read 6, iclass 36, count 0 2006.224.07:42:52.47#ibcon#end of sib2, iclass 36, count 0 2006.224.07:42:52.47#ibcon#*mode == 0, iclass 36, count 0 2006.224.07:42:52.47#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.224.07:42:52.47#ibcon#[25=BW32\r\n] 2006.224.07:42:52.47#ibcon#*before write, iclass 36, count 0 2006.224.07:42:52.47#ibcon#enter sib2, iclass 36, count 0 2006.224.07:42:52.47#ibcon#flushed, iclass 36, count 0 2006.224.07:42:52.47#ibcon#about to write, iclass 36, count 0 2006.224.07:42:52.47#ibcon#wrote, iclass 36, count 0 2006.224.07:42:52.47#ibcon#about to read 3, iclass 36, count 0 2006.224.07:42:52.50#ibcon#read 3, iclass 36, count 0 2006.224.07:42:52.50#ibcon#about to read 4, iclass 36, count 0 2006.224.07:42:52.50#ibcon#read 4, iclass 36, count 0 2006.224.07:42:52.50#ibcon#about to read 5, iclass 36, count 0 2006.224.07:42:52.50#ibcon#read 5, iclass 36, count 0 2006.224.07:42:52.50#ibcon#about to read 6, iclass 36, count 0 2006.224.07:42:52.50#ibcon#read 6, iclass 36, count 0 2006.224.07:42:52.50#ibcon#end of sib2, iclass 36, count 0 2006.224.07:42:52.50#ibcon#*after write, iclass 36, count 0 2006.224.07:42:52.50#ibcon#*before return 0, iclass 36, count 0 2006.224.07:42:52.50#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.224.07:42:52.50#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.224.07:42:52.50#ibcon#about to clear, iclass 36 cls_cnt 0 2006.224.07:42:52.50#ibcon#cleared, iclass 36 cls_cnt 0 2006.224.07:42:52.50$vc4f8/vbbw=wide 2006.224.07:42:52.51#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.224.07:42:52.51#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.224.07:42:52.51#ibcon#ireg 8 cls_cnt 0 2006.224.07:42:52.51#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.224.07:42:52.56#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.224.07:42:52.56#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.224.07:42:52.56#ibcon#enter wrdev, iclass 38, count 0 2006.224.07:42:52.56#ibcon#first serial, iclass 38, count 0 2006.224.07:42:52.56#ibcon#enter sib2, iclass 38, count 0 2006.224.07:42:52.56#ibcon#flushed, iclass 38, count 0 2006.224.07:42:52.56#ibcon#about to write, iclass 38, count 0 2006.224.07:42:52.56#ibcon#wrote, iclass 38, count 0 2006.224.07:42:52.56#ibcon#about to read 3, iclass 38, count 0 2006.224.07:42:52.58#ibcon#read 3, iclass 38, count 0 2006.224.07:42:52.58#ibcon#about to read 4, iclass 38, count 0 2006.224.07:42:52.58#ibcon#read 4, iclass 38, count 0 2006.224.07:42:52.58#ibcon#about to read 5, iclass 38, count 0 2006.224.07:42:52.58#ibcon#read 5, iclass 38, count 0 2006.224.07:42:52.58#ibcon#about to read 6, iclass 38, count 0 2006.224.07:42:52.58#ibcon#read 6, iclass 38, count 0 2006.224.07:42:52.58#ibcon#end of sib2, iclass 38, count 0 2006.224.07:42:52.58#ibcon#*mode == 0, iclass 38, count 0 2006.224.07:42:52.58#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.224.07:42:52.58#ibcon#[27=BW32\r\n] 2006.224.07:42:52.58#ibcon#*before write, iclass 38, count 0 2006.224.07:42:52.58#ibcon#enter sib2, iclass 38, count 0 2006.224.07:42:52.58#ibcon#flushed, iclass 38, count 0 2006.224.07:42:52.58#ibcon#about to write, iclass 38, count 0 2006.224.07:42:52.58#ibcon#wrote, iclass 38, count 0 2006.224.07:42:52.58#ibcon#about to read 3, iclass 38, count 0 2006.224.07:42:52.61#ibcon#read 3, iclass 38, count 0 2006.224.07:42:52.61#ibcon#about to read 4, iclass 38, count 0 2006.224.07:42:52.61#ibcon#read 4, iclass 38, count 0 2006.224.07:42:52.61#ibcon#about to read 5, iclass 38, count 0 2006.224.07:42:52.61#ibcon#read 5, iclass 38, count 0 2006.224.07:42:52.61#ibcon#about to read 6, iclass 38, count 0 2006.224.07:42:52.61#ibcon#read 6, iclass 38, count 0 2006.224.07:42:52.61#ibcon#end of sib2, iclass 38, count 0 2006.224.07:42:52.61#ibcon#*after write, iclass 38, count 0 2006.224.07:42:52.61#ibcon#*before return 0, iclass 38, count 0 2006.224.07:42:52.61#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.224.07:42:52.61#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.224.07:42:52.61#ibcon#about to clear, iclass 38 cls_cnt 0 2006.224.07:42:52.61#ibcon#cleared, iclass 38 cls_cnt 0 2006.224.07:42:52.61$4f8m12a/ifd4f 2006.224.07:42:52.62$ifd4f/lo= 2006.224.07:42:52.62$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.224.07:42:52.62$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.224.07:42:52.62$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.224.07:42:52.62$ifd4f/patch= 2006.224.07:42:52.62$ifd4f/patch=lo1,a1,a2,a3,a4 2006.224.07:42:52.62$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.224.07:42:52.62$ifd4f/patch=lo3,a5,a6,a7,a8 2006.224.07:42:52.62$4f8m12a/"form=m,16.000,1:2 2006.224.07:42:52.62$4f8m12a/"tpicd 2006.224.07:42:52.62$4f8m12a/echo=off 2006.224.07:42:52.62$4f8m12a/xlog=off 2006.224.07:42:52.62:!2006.224.07:43:20 2006.224.07:43:00.14#trakl#Source acquired 2006.224.07:43:02.14#flagr#flagr/antenna,acquired 2006.224.07:43:20.01:preob 2006.224.07:43:21.14/onsource/TRACKING 2006.224.07:43:21.15:!2006.224.07:43:30 2006.224.07:43:30.01:data_valid=on 2006.224.07:43:30.02:midob 2006.224.07:43:31.14/onsource/TRACKING 2006.224.07:43:31.15/wx/23.50,1004.4,100 2006.224.07:43:31.30/cable/+6.4330E-03 2006.224.07:43:32.39/va/01,08,usb,yes,48,51 2006.224.07:43:32.39/va/02,07,usb,yes,49,51 2006.224.07:43:32.39/va/03,06,usb,yes,52,52 2006.224.07:43:32.39/va/04,07,usb,yes,51,55 2006.224.07:43:32.39/va/05,07,usb,yes,59,63 2006.224.07:43:32.39/va/06,06,usb,yes,59,59 2006.224.07:43:32.39/va/07,06,usb,yes,60,60 2006.224.07:43:32.39/va/08,07,usb,yes,57,57 2006.224.07:43:32.62/valo/01,532.99,yes,locked 2006.224.07:43:32.62/valo/02,572.99,yes,locked 2006.224.07:43:32.62/valo/03,672.99,yes,locked 2006.224.07:43:32.62/valo/04,832.99,yes,locked 2006.224.07:43:32.62/valo/05,652.99,yes,locked 2006.224.07:43:32.62/valo/06,772.99,yes,locked 2006.224.07:43:32.62/valo/07,832.99,yes,locked 2006.224.07:43:32.62/valo/08,852.99,yes,locked 2006.224.07:43:33.71/vb/01,04,usb,yes,33,33 2006.224.07:43:33.71/vb/02,04,usb,yes,34,38 2006.224.07:43:33.71/vb/03,04,usb,yes,30,34 2006.224.07:43:33.71/vb/04,04,usb,yes,31,32 2006.224.07:43:33.71/vb/05,04,usb,yes,30,34 2006.224.07:43:33.71/vb/06,04,usb,yes,31,34 2006.224.07:43:33.71/vb/07,04,usb,yes,33,33 2006.224.07:43:33.71/vb/08,04,usb,yes,30,34 2006.224.07:43:33.95/vblo/01,632.99,yes,locked 2006.224.07:43:33.95/vblo/02,640.99,yes,locked 2006.224.07:43:33.95/vblo/03,656.99,yes,locked 2006.224.07:43:33.95/vblo/04,712.99,yes,locked 2006.224.07:43:33.95/vblo/05,744.99,yes,locked 2006.224.07:43:33.95/vblo/06,752.99,yes,locked 2006.224.07:43:33.95/vblo/07,734.99,yes,locked 2006.224.07:43:33.95/vblo/08,744.99,yes,locked 2006.224.07:43:34.10/vabw/8 2006.224.07:43:34.25/vbbw/8 2006.224.07:43:34.34/xfe/off,on,14.7 2006.224.07:43:34.71/ifatt/23,28,28,28 2006.224.07:43:35.07/fmout-gps/S +4.29E-07 2006.224.07:43:35.12:!2006.224.07:44:30 2006.224.07:44:30.01:data_valid=off 2006.224.07:44:30.02:postob 2006.224.07:44:30.21/cable/+6.4355E-03 2006.224.07:44:30.22/wx/23.54,1004.4,100 2006.224.07:44:30.30/fmout-gps/S +4.28E-07 2006.224.07:44:30.30:scan_name=224-0745,k06224,60 2006.224.07:44:30.30:source=0804+499,080839.67,495036.5,2000.0,ccw 2006.224.07:44:31.14#flagr#flagr/antenna,new-source 2006.224.07:44:31.15:checkk5 2006.224.07:44:31.52/chk_autoobs//k5ts1/ autoobs is running! 2006.224.07:44:31.89/chk_autoobs//k5ts2/ autoobs is running! 2006.224.07:44:32.26/chk_autoobs//k5ts3/ autoobs is running! 2006.224.07:44:32.63/chk_autoobs//k5ts4/ autoobs is running! 2006.224.07:44:33.00/chk_obsdata//k5ts1/T2240743??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.07:44:33.36/chk_obsdata//k5ts2/T2240743??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.07:44:33.72/chk_obsdata//k5ts3/T2240743??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.07:44:34.09/chk_obsdata//k5ts4/T2240743??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.07:44:34.77/k5log//k5ts1_log_newline 2006.224.07:44:35.46/k5log//k5ts2_log_newline 2006.224.07:44:36.14/k5log//k5ts3_log_newline 2006.224.07:44:36.83/k5log//k5ts4_log_newline 2006.224.07:44:36.85/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.224.07:44:36.85:4f8m12a=1 2006.224.07:44:36.85$4f8m12a/echo=on 2006.224.07:44:36.85$4f8m12a/pcalon 2006.224.07:44:36.85$pcalon/"no phase cal control is implemented here 2006.224.07:44:36.85$4f8m12a/"tpicd=stop 2006.224.07:44:36.85$4f8m12a/vc4f8 2006.224.07:44:36.85$vc4f8/valo=1,532.99 2006.224.07:44:36.86#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.224.07:44:36.86#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.224.07:44:36.86#ibcon#ireg 17 cls_cnt 0 2006.224.07:44:36.86#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.224.07:44:36.86#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.224.07:44:36.86#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.224.07:44:36.86#ibcon#enter wrdev, iclass 13, count 0 2006.224.07:44:36.86#ibcon#first serial, iclass 13, count 0 2006.224.07:44:36.86#ibcon#enter sib2, iclass 13, count 0 2006.224.07:44:36.86#ibcon#flushed, iclass 13, count 0 2006.224.07:44:36.86#ibcon#about to write, iclass 13, count 0 2006.224.07:44:36.86#ibcon#wrote, iclass 13, count 0 2006.224.07:44:36.86#ibcon#about to read 3, iclass 13, count 0 2006.224.07:44:36.89#ibcon#read 3, iclass 13, count 0 2006.224.07:44:36.89#ibcon#about to read 4, iclass 13, count 0 2006.224.07:44:36.89#ibcon#read 4, iclass 13, count 0 2006.224.07:44:36.89#ibcon#about to read 5, iclass 13, count 0 2006.224.07:44:36.89#ibcon#read 5, iclass 13, count 0 2006.224.07:44:36.89#ibcon#about to read 6, iclass 13, count 0 2006.224.07:44:36.89#ibcon#read 6, iclass 13, count 0 2006.224.07:44:36.89#ibcon#end of sib2, iclass 13, count 0 2006.224.07:44:36.89#ibcon#*mode == 0, iclass 13, count 0 2006.224.07:44:36.89#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.224.07:44:36.89#ibcon#[26=FRQ=01,532.99\r\n] 2006.224.07:44:36.89#ibcon#*before write, iclass 13, count 0 2006.224.07:44:36.89#ibcon#enter sib2, iclass 13, count 0 2006.224.07:44:36.89#ibcon#flushed, iclass 13, count 0 2006.224.07:44:36.89#ibcon#about to write, iclass 13, count 0 2006.224.07:44:36.89#ibcon#wrote, iclass 13, count 0 2006.224.07:44:36.89#ibcon#about to read 3, iclass 13, count 0 2006.224.07:44:36.94#ibcon#read 3, iclass 13, count 0 2006.224.07:44:36.94#ibcon#about to read 4, iclass 13, count 0 2006.224.07:44:36.94#ibcon#read 4, iclass 13, count 0 2006.224.07:44:36.94#ibcon#about to read 5, iclass 13, count 0 2006.224.07:44:36.94#ibcon#read 5, iclass 13, count 0 2006.224.07:44:36.94#ibcon#about to read 6, iclass 13, count 0 2006.224.07:44:36.94#ibcon#read 6, iclass 13, count 0 2006.224.07:44:36.94#ibcon#end of sib2, iclass 13, count 0 2006.224.07:44:36.94#ibcon#*after write, iclass 13, count 0 2006.224.07:44:36.94#ibcon#*before return 0, iclass 13, count 0 2006.224.07:44:36.94#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.224.07:44:36.94#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.224.07:44:36.94#ibcon#about to clear, iclass 13 cls_cnt 0 2006.224.07:44:36.94#ibcon#cleared, iclass 13 cls_cnt 0 2006.224.07:44:36.94$vc4f8/va=1,8 2006.224.07:44:36.94#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.224.07:44:36.94#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.224.07:44:36.94#ibcon#ireg 11 cls_cnt 2 2006.224.07:44:36.94#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.224.07:44:36.94#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.224.07:44:36.94#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.224.07:44:36.94#ibcon#enter wrdev, iclass 15, count 2 2006.224.07:44:36.94#ibcon#first serial, iclass 15, count 2 2006.224.07:44:36.94#ibcon#enter sib2, iclass 15, count 2 2006.224.07:44:36.94#ibcon#flushed, iclass 15, count 2 2006.224.07:44:36.94#ibcon#about to write, iclass 15, count 2 2006.224.07:44:36.94#ibcon#wrote, iclass 15, count 2 2006.224.07:44:36.94#ibcon#about to read 3, iclass 15, count 2 2006.224.07:44:36.97#ibcon#read 3, iclass 15, count 2 2006.224.07:44:36.97#ibcon#about to read 4, iclass 15, count 2 2006.224.07:44:36.97#ibcon#read 4, iclass 15, count 2 2006.224.07:44:36.97#ibcon#about to read 5, iclass 15, count 2 2006.224.07:44:36.97#ibcon#read 5, iclass 15, count 2 2006.224.07:44:36.97#ibcon#about to read 6, iclass 15, count 2 2006.224.07:44:36.97#ibcon#read 6, iclass 15, count 2 2006.224.07:44:36.97#ibcon#end of sib2, iclass 15, count 2 2006.224.07:44:36.97#ibcon#*mode == 0, iclass 15, count 2 2006.224.07:44:36.97#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.224.07:44:36.97#ibcon#[25=AT01-08\r\n] 2006.224.07:44:36.97#ibcon#*before write, iclass 15, count 2 2006.224.07:44:36.97#ibcon#enter sib2, iclass 15, count 2 2006.224.07:44:36.97#ibcon#flushed, iclass 15, count 2 2006.224.07:44:36.97#ibcon#about to write, iclass 15, count 2 2006.224.07:44:36.97#ibcon#wrote, iclass 15, count 2 2006.224.07:44:36.97#ibcon#about to read 3, iclass 15, count 2 2006.224.07:44:37.00#ibcon#read 3, iclass 15, count 2 2006.224.07:44:37.00#ibcon#about to read 4, iclass 15, count 2 2006.224.07:44:37.00#ibcon#read 4, iclass 15, count 2 2006.224.07:44:37.00#ibcon#about to read 5, iclass 15, count 2 2006.224.07:44:37.00#ibcon#read 5, iclass 15, count 2 2006.224.07:44:37.00#ibcon#about to read 6, iclass 15, count 2 2006.224.07:44:37.00#ibcon#read 6, iclass 15, count 2 2006.224.07:44:37.00#ibcon#end of sib2, iclass 15, count 2 2006.224.07:44:37.00#ibcon#*after write, iclass 15, count 2 2006.224.07:44:37.00#ibcon#*before return 0, iclass 15, count 2 2006.224.07:44:37.00#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.224.07:44:37.00#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.224.07:44:37.00#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.224.07:44:37.00#ibcon#ireg 7 cls_cnt 0 2006.224.07:44:37.00#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.224.07:44:37.12#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.224.07:44:37.12#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.224.07:44:37.12#ibcon#enter wrdev, iclass 15, count 0 2006.224.07:44:37.12#ibcon#first serial, iclass 15, count 0 2006.224.07:44:37.12#ibcon#enter sib2, iclass 15, count 0 2006.224.07:44:37.12#ibcon#flushed, iclass 15, count 0 2006.224.07:44:37.12#ibcon#about to write, iclass 15, count 0 2006.224.07:44:37.12#ibcon#wrote, iclass 15, count 0 2006.224.07:44:37.12#ibcon#about to read 3, iclass 15, count 0 2006.224.07:44:37.14#ibcon#read 3, iclass 15, count 0 2006.224.07:44:37.14#ibcon#about to read 4, iclass 15, count 0 2006.224.07:44:37.14#ibcon#read 4, iclass 15, count 0 2006.224.07:44:37.14#ibcon#about to read 5, iclass 15, count 0 2006.224.07:44:37.14#ibcon#read 5, iclass 15, count 0 2006.224.07:44:37.14#ibcon#about to read 6, iclass 15, count 0 2006.224.07:44:37.14#ibcon#read 6, iclass 15, count 0 2006.224.07:44:37.14#ibcon#end of sib2, iclass 15, count 0 2006.224.07:44:37.14#ibcon#*mode == 0, iclass 15, count 0 2006.224.07:44:37.14#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.224.07:44:37.14#ibcon#[25=USB\r\n] 2006.224.07:44:37.14#ibcon#*before write, iclass 15, count 0 2006.224.07:44:37.14#ibcon#enter sib2, iclass 15, count 0 2006.224.07:44:37.14#ibcon#flushed, iclass 15, count 0 2006.224.07:44:37.14#ibcon#about to write, iclass 15, count 0 2006.224.07:44:37.14#ibcon#wrote, iclass 15, count 0 2006.224.07:44:37.14#ibcon#about to read 3, iclass 15, count 0 2006.224.07:44:37.17#ibcon#read 3, iclass 15, count 0 2006.224.07:44:37.17#ibcon#about to read 4, iclass 15, count 0 2006.224.07:44:37.17#ibcon#read 4, iclass 15, count 0 2006.224.07:44:37.17#ibcon#about to read 5, iclass 15, count 0 2006.224.07:44:37.17#ibcon#read 5, iclass 15, count 0 2006.224.07:44:37.17#ibcon#about to read 6, iclass 15, count 0 2006.224.07:44:37.17#ibcon#read 6, iclass 15, count 0 2006.224.07:44:37.17#ibcon#end of sib2, iclass 15, count 0 2006.224.07:44:37.17#ibcon#*after write, iclass 15, count 0 2006.224.07:44:37.17#ibcon#*before return 0, iclass 15, count 0 2006.224.07:44:37.17#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.224.07:44:37.17#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.224.07:44:37.17#ibcon#about to clear, iclass 15 cls_cnt 0 2006.224.07:44:37.17#ibcon#cleared, iclass 15 cls_cnt 0 2006.224.07:44:37.17$vc4f8/valo=2,572.99 2006.224.07:44:37.17#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.224.07:44:37.17#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.224.07:44:37.17#ibcon#ireg 17 cls_cnt 0 2006.224.07:44:37.17#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.224.07:44:37.17#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.224.07:44:37.17#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.224.07:44:37.17#ibcon#enter wrdev, iclass 17, count 0 2006.224.07:44:37.17#ibcon#first serial, iclass 17, count 0 2006.224.07:44:37.17#ibcon#enter sib2, iclass 17, count 0 2006.224.07:44:37.17#ibcon#flushed, iclass 17, count 0 2006.224.07:44:37.17#ibcon#about to write, iclass 17, count 0 2006.224.07:44:37.17#ibcon#wrote, iclass 17, count 0 2006.224.07:44:37.17#ibcon#about to read 3, iclass 17, count 0 2006.224.07:44:37.20#ibcon#read 3, iclass 17, count 0 2006.224.07:44:37.20#ibcon#about to read 4, iclass 17, count 0 2006.224.07:44:37.20#ibcon#read 4, iclass 17, count 0 2006.224.07:44:37.20#ibcon#about to read 5, iclass 17, count 0 2006.224.07:44:37.20#ibcon#read 5, iclass 17, count 0 2006.224.07:44:37.20#ibcon#about to read 6, iclass 17, count 0 2006.224.07:44:37.20#ibcon#read 6, iclass 17, count 0 2006.224.07:44:37.20#ibcon#end of sib2, iclass 17, count 0 2006.224.07:44:37.20#ibcon#*mode == 0, iclass 17, count 0 2006.224.07:44:37.20#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.224.07:44:37.20#ibcon#[26=FRQ=02,572.99\r\n] 2006.224.07:44:37.20#ibcon#*before write, iclass 17, count 0 2006.224.07:44:37.20#ibcon#enter sib2, iclass 17, count 0 2006.224.07:44:37.20#ibcon#flushed, iclass 17, count 0 2006.224.07:44:37.20#ibcon#about to write, iclass 17, count 0 2006.224.07:44:37.20#ibcon#wrote, iclass 17, count 0 2006.224.07:44:37.20#ibcon#about to read 3, iclass 17, count 0 2006.224.07:44:37.24#ibcon#read 3, iclass 17, count 0 2006.224.07:44:37.24#ibcon#about to read 4, iclass 17, count 0 2006.224.07:44:37.24#ibcon#read 4, iclass 17, count 0 2006.224.07:44:37.24#ibcon#about to read 5, iclass 17, count 0 2006.224.07:44:37.24#ibcon#read 5, iclass 17, count 0 2006.224.07:44:37.24#ibcon#about to read 6, iclass 17, count 0 2006.224.07:44:37.24#ibcon#read 6, iclass 17, count 0 2006.224.07:44:37.24#ibcon#end of sib2, iclass 17, count 0 2006.224.07:44:37.24#ibcon#*after write, iclass 17, count 0 2006.224.07:44:37.24#ibcon#*before return 0, iclass 17, count 0 2006.224.07:44:37.24#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.224.07:44:37.24#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.224.07:44:37.24#ibcon#about to clear, iclass 17 cls_cnt 0 2006.224.07:44:37.24#ibcon#cleared, iclass 17 cls_cnt 0 2006.224.07:44:37.24$vc4f8/va=2,7 2006.224.07:44:37.24#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.224.07:44:37.24#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.224.07:44:37.24#ibcon#ireg 11 cls_cnt 2 2006.224.07:44:37.24#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.224.07:44:37.30#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.224.07:44:37.30#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.224.07:44:37.30#ibcon#enter wrdev, iclass 19, count 2 2006.224.07:44:37.30#ibcon#first serial, iclass 19, count 2 2006.224.07:44:37.30#ibcon#enter sib2, iclass 19, count 2 2006.224.07:44:37.30#ibcon#flushed, iclass 19, count 2 2006.224.07:44:37.30#ibcon#about to write, iclass 19, count 2 2006.224.07:44:37.30#ibcon#wrote, iclass 19, count 2 2006.224.07:44:37.30#ibcon#about to read 3, iclass 19, count 2 2006.224.07:44:37.31#ibcon#read 3, iclass 19, count 2 2006.224.07:44:37.31#ibcon#about to read 4, iclass 19, count 2 2006.224.07:44:37.31#ibcon#read 4, iclass 19, count 2 2006.224.07:44:37.31#ibcon#about to read 5, iclass 19, count 2 2006.224.07:44:37.31#ibcon#read 5, iclass 19, count 2 2006.224.07:44:37.31#ibcon#about to read 6, iclass 19, count 2 2006.224.07:44:37.31#ibcon#read 6, iclass 19, count 2 2006.224.07:44:37.31#ibcon#end of sib2, iclass 19, count 2 2006.224.07:44:37.31#ibcon#*mode == 0, iclass 19, count 2 2006.224.07:44:37.31#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.224.07:44:37.31#ibcon#[25=AT02-07\r\n] 2006.224.07:44:37.31#ibcon#*before write, iclass 19, count 2 2006.224.07:44:37.31#ibcon#enter sib2, iclass 19, count 2 2006.224.07:44:37.31#ibcon#flushed, iclass 19, count 2 2006.224.07:44:37.31#ibcon#about to write, iclass 19, count 2 2006.224.07:44:37.31#ibcon#wrote, iclass 19, count 2 2006.224.07:44:37.31#ibcon#about to read 3, iclass 19, count 2 2006.224.07:44:37.34#ibcon#read 3, iclass 19, count 2 2006.224.07:44:37.34#ibcon#about to read 4, iclass 19, count 2 2006.224.07:44:37.34#ibcon#read 4, iclass 19, count 2 2006.224.07:44:37.34#ibcon#about to read 5, iclass 19, count 2 2006.224.07:44:37.34#ibcon#read 5, iclass 19, count 2 2006.224.07:44:37.34#ibcon#about to read 6, iclass 19, count 2 2006.224.07:44:37.34#ibcon#read 6, iclass 19, count 2 2006.224.07:44:37.34#ibcon#end of sib2, iclass 19, count 2 2006.224.07:44:37.34#ibcon#*after write, iclass 19, count 2 2006.224.07:44:37.34#ibcon#*before return 0, iclass 19, count 2 2006.224.07:44:37.34#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.224.07:44:37.34#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.224.07:44:37.34#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.224.07:44:37.34#ibcon#ireg 7 cls_cnt 0 2006.224.07:44:37.34#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.224.07:44:37.46#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.224.07:44:37.46#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.224.07:44:37.46#ibcon#enter wrdev, iclass 19, count 0 2006.224.07:44:37.46#ibcon#first serial, iclass 19, count 0 2006.224.07:44:37.46#ibcon#enter sib2, iclass 19, count 0 2006.224.07:44:37.46#ibcon#flushed, iclass 19, count 0 2006.224.07:44:37.46#ibcon#about to write, iclass 19, count 0 2006.224.07:44:37.46#ibcon#wrote, iclass 19, count 0 2006.224.07:44:37.46#ibcon#about to read 3, iclass 19, count 0 2006.224.07:44:37.48#ibcon#read 3, iclass 19, count 0 2006.224.07:44:37.48#ibcon#about to read 4, iclass 19, count 0 2006.224.07:44:37.48#ibcon#read 4, iclass 19, count 0 2006.224.07:44:37.48#ibcon#about to read 5, iclass 19, count 0 2006.224.07:44:37.48#ibcon#read 5, iclass 19, count 0 2006.224.07:44:37.48#ibcon#about to read 6, iclass 19, count 0 2006.224.07:44:37.48#ibcon#read 6, iclass 19, count 0 2006.224.07:44:37.48#ibcon#end of sib2, iclass 19, count 0 2006.224.07:44:37.48#ibcon#*mode == 0, iclass 19, count 0 2006.224.07:44:37.48#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.224.07:44:37.48#ibcon#[25=USB\r\n] 2006.224.07:44:37.48#ibcon#*before write, iclass 19, count 0 2006.224.07:44:37.48#ibcon#enter sib2, iclass 19, count 0 2006.224.07:44:37.48#ibcon#flushed, iclass 19, count 0 2006.224.07:44:37.48#ibcon#about to write, iclass 19, count 0 2006.224.07:44:37.48#ibcon#wrote, iclass 19, count 0 2006.224.07:44:37.48#ibcon#about to read 3, iclass 19, count 0 2006.224.07:44:37.51#ibcon#read 3, iclass 19, count 0 2006.224.07:44:37.51#ibcon#about to read 4, iclass 19, count 0 2006.224.07:44:37.51#ibcon#read 4, iclass 19, count 0 2006.224.07:44:37.51#ibcon#about to read 5, iclass 19, count 0 2006.224.07:44:37.51#ibcon#read 5, iclass 19, count 0 2006.224.07:44:37.51#ibcon#about to read 6, iclass 19, count 0 2006.224.07:44:37.51#ibcon#read 6, iclass 19, count 0 2006.224.07:44:37.51#ibcon#end of sib2, iclass 19, count 0 2006.224.07:44:37.51#ibcon#*after write, iclass 19, count 0 2006.224.07:44:37.51#ibcon#*before return 0, iclass 19, count 0 2006.224.07:44:37.51#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.224.07:44:37.51#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.224.07:44:37.51#ibcon#about to clear, iclass 19 cls_cnt 0 2006.224.07:44:37.51#ibcon#cleared, iclass 19 cls_cnt 0 2006.224.07:44:37.51$vc4f8/valo=3,672.99 2006.224.07:44:37.51#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.224.07:44:37.51#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.224.07:44:37.51#ibcon#ireg 17 cls_cnt 0 2006.224.07:44:37.51#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.224.07:44:37.51#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.224.07:44:37.51#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.224.07:44:37.51#ibcon#enter wrdev, iclass 21, count 0 2006.224.07:44:37.51#ibcon#first serial, iclass 21, count 0 2006.224.07:44:37.51#ibcon#enter sib2, iclass 21, count 0 2006.224.07:44:37.51#ibcon#flushed, iclass 21, count 0 2006.224.07:44:37.51#ibcon#about to write, iclass 21, count 0 2006.224.07:44:37.51#ibcon#wrote, iclass 21, count 0 2006.224.07:44:37.51#ibcon#about to read 3, iclass 21, count 0 2006.224.07:44:37.54#ibcon#read 3, iclass 21, count 0 2006.224.07:44:37.54#ibcon#about to read 4, iclass 21, count 0 2006.224.07:44:37.54#ibcon#read 4, iclass 21, count 0 2006.224.07:44:37.54#ibcon#about to read 5, iclass 21, count 0 2006.224.07:44:37.54#ibcon#read 5, iclass 21, count 0 2006.224.07:44:37.54#ibcon#about to read 6, iclass 21, count 0 2006.224.07:44:37.54#ibcon#read 6, iclass 21, count 0 2006.224.07:44:37.54#ibcon#end of sib2, iclass 21, count 0 2006.224.07:44:37.54#ibcon#*mode == 0, iclass 21, count 0 2006.224.07:44:37.54#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.224.07:44:37.54#ibcon#[26=FRQ=03,672.99\r\n] 2006.224.07:44:37.54#ibcon#*before write, iclass 21, count 0 2006.224.07:44:37.54#ibcon#enter sib2, iclass 21, count 0 2006.224.07:44:37.54#ibcon#flushed, iclass 21, count 0 2006.224.07:44:37.54#ibcon#about to write, iclass 21, count 0 2006.224.07:44:37.54#ibcon#wrote, iclass 21, count 0 2006.224.07:44:37.54#ibcon#about to read 3, iclass 21, count 0 2006.224.07:44:37.58#ibcon#read 3, iclass 21, count 0 2006.224.07:44:37.58#ibcon#about to read 4, iclass 21, count 0 2006.224.07:44:37.58#ibcon#read 4, iclass 21, count 0 2006.224.07:44:37.58#ibcon#about to read 5, iclass 21, count 0 2006.224.07:44:37.58#ibcon#read 5, iclass 21, count 0 2006.224.07:44:37.58#ibcon#about to read 6, iclass 21, count 0 2006.224.07:44:37.58#ibcon#read 6, iclass 21, count 0 2006.224.07:44:37.58#ibcon#end of sib2, iclass 21, count 0 2006.224.07:44:37.58#ibcon#*after write, iclass 21, count 0 2006.224.07:44:37.58#ibcon#*before return 0, iclass 21, count 0 2006.224.07:44:37.58#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.224.07:44:37.58#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.224.07:44:37.58#ibcon#about to clear, iclass 21 cls_cnt 0 2006.224.07:44:37.58#ibcon#cleared, iclass 21 cls_cnt 0 2006.224.07:44:37.58$vc4f8/va=3,6 2006.224.07:44:37.58#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.224.07:44:37.58#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.224.07:44:37.58#ibcon#ireg 11 cls_cnt 2 2006.224.07:44:37.58#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.224.07:44:37.64#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.224.07:44:37.64#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.224.07:44:37.64#ibcon#enter wrdev, iclass 23, count 2 2006.224.07:44:37.64#ibcon#first serial, iclass 23, count 2 2006.224.07:44:37.64#ibcon#enter sib2, iclass 23, count 2 2006.224.07:44:37.64#ibcon#flushed, iclass 23, count 2 2006.224.07:44:37.64#ibcon#about to write, iclass 23, count 2 2006.224.07:44:37.64#ibcon#wrote, iclass 23, count 2 2006.224.07:44:37.64#ibcon#about to read 3, iclass 23, count 2 2006.224.07:44:37.65#ibcon#read 3, iclass 23, count 2 2006.224.07:44:37.65#ibcon#about to read 4, iclass 23, count 2 2006.224.07:44:37.65#ibcon#read 4, iclass 23, count 2 2006.224.07:44:37.65#ibcon#about to read 5, iclass 23, count 2 2006.224.07:44:37.65#ibcon#read 5, iclass 23, count 2 2006.224.07:44:37.65#ibcon#about to read 6, iclass 23, count 2 2006.224.07:44:37.65#ibcon#read 6, iclass 23, count 2 2006.224.07:44:37.65#ibcon#end of sib2, iclass 23, count 2 2006.224.07:44:37.65#ibcon#*mode == 0, iclass 23, count 2 2006.224.07:44:37.65#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.224.07:44:37.65#ibcon#[25=AT03-06\r\n] 2006.224.07:44:37.65#ibcon#*before write, iclass 23, count 2 2006.224.07:44:37.65#ibcon#enter sib2, iclass 23, count 2 2006.224.07:44:37.65#ibcon#flushed, iclass 23, count 2 2006.224.07:44:37.65#ibcon#about to write, iclass 23, count 2 2006.224.07:44:37.65#ibcon#wrote, iclass 23, count 2 2006.224.07:44:37.65#ibcon#about to read 3, iclass 23, count 2 2006.224.07:44:37.68#ibcon#read 3, iclass 23, count 2 2006.224.07:44:37.68#ibcon#about to read 4, iclass 23, count 2 2006.224.07:44:37.68#ibcon#read 4, iclass 23, count 2 2006.224.07:44:37.68#ibcon#about to read 5, iclass 23, count 2 2006.224.07:44:37.68#ibcon#read 5, iclass 23, count 2 2006.224.07:44:37.68#ibcon#about to read 6, iclass 23, count 2 2006.224.07:44:37.68#ibcon#read 6, iclass 23, count 2 2006.224.07:44:37.68#ibcon#end of sib2, iclass 23, count 2 2006.224.07:44:37.68#ibcon#*after write, iclass 23, count 2 2006.224.07:44:37.68#ibcon#*before return 0, iclass 23, count 2 2006.224.07:44:37.68#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.224.07:44:37.68#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.224.07:44:37.68#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.224.07:44:37.68#ibcon#ireg 7 cls_cnt 0 2006.224.07:44:37.68#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.224.07:44:37.80#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.224.07:44:37.80#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.224.07:44:37.80#ibcon#enter wrdev, iclass 23, count 0 2006.224.07:44:37.80#ibcon#first serial, iclass 23, count 0 2006.224.07:44:37.80#ibcon#enter sib2, iclass 23, count 0 2006.224.07:44:37.80#ibcon#flushed, iclass 23, count 0 2006.224.07:44:37.80#ibcon#about to write, iclass 23, count 0 2006.224.07:44:37.80#ibcon#wrote, iclass 23, count 0 2006.224.07:44:37.80#ibcon#about to read 3, iclass 23, count 0 2006.224.07:44:37.82#ibcon#read 3, iclass 23, count 0 2006.224.07:44:37.82#ibcon#about to read 4, iclass 23, count 0 2006.224.07:44:37.82#ibcon#read 4, iclass 23, count 0 2006.224.07:44:37.82#ibcon#about to read 5, iclass 23, count 0 2006.224.07:44:37.82#ibcon#read 5, iclass 23, count 0 2006.224.07:44:37.82#ibcon#about to read 6, iclass 23, count 0 2006.224.07:44:37.82#ibcon#read 6, iclass 23, count 0 2006.224.07:44:37.82#ibcon#end of sib2, iclass 23, count 0 2006.224.07:44:37.82#ibcon#*mode == 0, iclass 23, count 0 2006.224.07:44:37.82#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.224.07:44:37.82#ibcon#[25=USB\r\n] 2006.224.07:44:37.82#ibcon#*before write, iclass 23, count 0 2006.224.07:44:37.82#ibcon#enter sib2, iclass 23, count 0 2006.224.07:44:37.82#ibcon#flushed, iclass 23, count 0 2006.224.07:44:37.82#ibcon#about to write, iclass 23, count 0 2006.224.07:44:37.82#ibcon#wrote, iclass 23, count 0 2006.224.07:44:37.82#ibcon#about to read 3, iclass 23, count 0 2006.224.07:44:37.85#ibcon#read 3, iclass 23, count 0 2006.224.07:44:37.85#ibcon#about to read 4, iclass 23, count 0 2006.224.07:44:37.85#ibcon#read 4, iclass 23, count 0 2006.224.07:44:37.85#ibcon#about to read 5, iclass 23, count 0 2006.224.07:44:37.85#ibcon#read 5, iclass 23, count 0 2006.224.07:44:37.85#ibcon#about to read 6, iclass 23, count 0 2006.224.07:44:37.85#ibcon#read 6, iclass 23, count 0 2006.224.07:44:37.85#ibcon#end of sib2, iclass 23, count 0 2006.224.07:44:37.85#ibcon#*after write, iclass 23, count 0 2006.224.07:44:37.85#ibcon#*before return 0, iclass 23, count 0 2006.224.07:44:37.85#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.224.07:44:37.85#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.224.07:44:37.85#ibcon#about to clear, iclass 23 cls_cnt 0 2006.224.07:44:37.85#ibcon#cleared, iclass 23 cls_cnt 0 2006.224.07:44:37.85$vc4f8/valo=4,832.99 2006.224.07:44:37.85#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.224.07:44:37.85#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.224.07:44:37.85#ibcon#ireg 17 cls_cnt 0 2006.224.07:44:37.85#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.224.07:44:37.85#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.224.07:44:37.85#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.224.07:44:37.85#ibcon#enter wrdev, iclass 25, count 0 2006.224.07:44:37.85#ibcon#first serial, iclass 25, count 0 2006.224.07:44:37.85#ibcon#enter sib2, iclass 25, count 0 2006.224.07:44:37.85#ibcon#flushed, iclass 25, count 0 2006.224.07:44:37.85#ibcon#about to write, iclass 25, count 0 2006.224.07:44:37.85#ibcon#wrote, iclass 25, count 0 2006.224.07:44:37.85#ibcon#about to read 3, iclass 25, count 0 2006.224.07:44:37.87#ibcon#read 3, iclass 25, count 0 2006.224.07:44:37.87#ibcon#about to read 4, iclass 25, count 0 2006.224.07:44:37.87#ibcon#read 4, iclass 25, count 0 2006.224.07:44:37.87#ibcon#about to read 5, iclass 25, count 0 2006.224.07:44:37.87#ibcon#read 5, iclass 25, count 0 2006.224.07:44:37.87#ibcon#about to read 6, iclass 25, count 0 2006.224.07:44:37.87#ibcon#read 6, iclass 25, count 0 2006.224.07:44:37.87#ibcon#end of sib2, iclass 25, count 0 2006.224.07:44:37.87#ibcon#*mode == 0, iclass 25, count 0 2006.224.07:44:37.87#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.224.07:44:37.87#ibcon#[26=FRQ=04,832.99\r\n] 2006.224.07:44:37.87#ibcon#*before write, iclass 25, count 0 2006.224.07:44:37.87#ibcon#enter sib2, iclass 25, count 0 2006.224.07:44:37.87#ibcon#flushed, iclass 25, count 0 2006.224.07:44:37.87#ibcon#about to write, iclass 25, count 0 2006.224.07:44:37.87#ibcon#wrote, iclass 25, count 0 2006.224.07:44:37.87#ibcon#about to read 3, iclass 25, count 0 2006.224.07:44:37.91#ibcon#read 3, iclass 25, count 0 2006.224.07:44:37.91#ibcon#about to read 4, iclass 25, count 0 2006.224.07:44:37.91#ibcon#read 4, iclass 25, count 0 2006.224.07:44:37.91#ibcon#about to read 5, iclass 25, count 0 2006.224.07:44:37.91#ibcon#read 5, iclass 25, count 0 2006.224.07:44:37.91#ibcon#about to read 6, iclass 25, count 0 2006.224.07:44:37.91#ibcon#read 6, iclass 25, count 0 2006.224.07:44:37.91#ibcon#end of sib2, iclass 25, count 0 2006.224.07:44:37.91#ibcon#*after write, iclass 25, count 0 2006.224.07:44:37.91#ibcon#*before return 0, iclass 25, count 0 2006.224.07:44:37.91#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.224.07:44:37.91#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.224.07:44:37.91#ibcon#about to clear, iclass 25 cls_cnt 0 2006.224.07:44:37.91#ibcon#cleared, iclass 25 cls_cnt 0 2006.224.07:44:37.91$vc4f8/va=4,7 2006.224.07:44:37.91#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.224.07:44:37.91#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.224.07:44:37.91#ibcon#ireg 11 cls_cnt 2 2006.224.07:44:37.91#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.224.07:44:37.97#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.224.07:44:37.97#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.224.07:44:37.97#ibcon#enter wrdev, iclass 27, count 2 2006.224.07:44:37.97#ibcon#first serial, iclass 27, count 2 2006.224.07:44:37.97#ibcon#enter sib2, iclass 27, count 2 2006.224.07:44:37.97#ibcon#flushed, iclass 27, count 2 2006.224.07:44:37.97#ibcon#about to write, iclass 27, count 2 2006.224.07:44:37.97#ibcon#wrote, iclass 27, count 2 2006.224.07:44:37.97#ibcon#about to read 3, iclass 27, count 2 2006.224.07:44:37.99#ibcon#read 3, iclass 27, count 2 2006.224.07:44:37.99#ibcon#about to read 4, iclass 27, count 2 2006.224.07:44:37.99#ibcon#read 4, iclass 27, count 2 2006.224.07:44:37.99#ibcon#about to read 5, iclass 27, count 2 2006.224.07:44:37.99#ibcon#read 5, iclass 27, count 2 2006.224.07:44:37.99#ibcon#about to read 6, iclass 27, count 2 2006.224.07:44:37.99#ibcon#read 6, iclass 27, count 2 2006.224.07:44:37.99#ibcon#end of sib2, iclass 27, count 2 2006.224.07:44:37.99#ibcon#*mode == 0, iclass 27, count 2 2006.224.07:44:37.99#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.224.07:44:37.99#ibcon#[25=AT04-07\r\n] 2006.224.07:44:37.99#ibcon#*before write, iclass 27, count 2 2006.224.07:44:37.99#ibcon#enter sib2, iclass 27, count 2 2006.224.07:44:37.99#ibcon#flushed, iclass 27, count 2 2006.224.07:44:37.99#ibcon#about to write, iclass 27, count 2 2006.224.07:44:37.99#ibcon#wrote, iclass 27, count 2 2006.224.07:44:37.99#ibcon#about to read 3, iclass 27, count 2 2006.224.07:44:38.02#ibcon#read 3, iclass 27, count 2 2006.224.07:44:38.02#ibcon#about to read 4, iclass 27, count 2 2006.224.07:44:38.02#ibcon#read 4, iclass 27, count 2 2006.224.07:44:38.02#ibcon#about to read 5, iclass 27, count 2 2006.224.07:44:38.02#ibcon#read 5, iclass 27, count 2 2006.224.07:44:38.02#ibcon#about to read 6, iclass 27, count 2 2006.224.07:44:38.02#ibcon#read 6, iclass 27, count 2 2006.224.07:44:38.02#ibcon#end of sib2, iclass 27, count 2 2006.224.07:44:38.02#ibcon#*after write, iclass 27, count 2 2006.224.07:44:38.02#ibcon#*before return 0, iclass 27, count 2 2006.224.07:44:38.02#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.224.07:44:38.02#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.224.07:44:38.02#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.224.07:44:38.02#ibcon#ireg 7 cls_cnt 0 2006.224.07:44:38.02#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.224.07:44:38.14#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.224.07:44:38.14#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.224.07:44:38.14#ibcon#enter wrdev, iclass 27, count 0 2006.224.07:44:38.14#ibcon#first serial, iclass 27, count 0 2006.224.07:44:38.14#ibcon#enter sib2, iclass 27, count 0 2006.224.07:44:38.14#ibcon#flushed, iclass 27, count 0 2006.224.07:44:38.14#ibcon#about to write, iclass 27, count 0 2006.224.07:44:38.14#ibcon#wrote, iclass 27, count 0 2006.224.07:44:38.14#ibcon#about to read 3, iclass 27, count 0 2006.224.07:44:38.16#ibcon#read 3, iclass 27, count 0 2006.224.07:44:38.16#ibcon#about to read 4, iclass 27, count 0 2006.224.07:44:38.16#ibcon#read 4, iclass 27, count 0 2006.224.07:44:38.16#ibcon#about to read 5, iclass 27, count 0 2006.224.07:44:38.16#ibcon#read 5, iclass 27, count 0 2006.224.07:44:38.16#ibcon#about to read 6, iclass 27, count 0 2006.224.07:44:38.16#ibcon#read 6, iclass 27, count 0 2006.224.07:44:38.16#ibcon#end of sib2, iclass 27, count 0 2006.224.07:44:38.16#ibcon#*mode == 0, iclass 27, count 0 2006.224.07:44:38.16#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.224.07:44:38.16#ibcon#[25=USB\r\n] 2006.224.07:44:38.16#ibcon#*before write, iclass 27, count 0 2006.224.07:44:38.16#ibcon#enter sib2, iclass 27, count 0 2006.224.07:44:38.16#ibcon#flushed, iclass 27, count 0 2006.224.07:44:38.16#ibcon#about to write, iclass 27, count 0 2006.224.07:44:38.16#ibcon#wrote, iclass 27, count 0 2006.224.07:44:38.16#ibcon#about to read 3, iclass 27, count 0 2006.224.07:44:38.19#ibcon#read 3, iclass 27, count 0 2006.224.07:44:38.19#ibcon#about to read 4, iclass 27, count 0 2006.224.07:44:38.19#ibcon#read 4, iclass 27, count 0 2006.224.07:44:38.19#ibcon#about to read 5, iclass 27, count 0 2006.224.07:44:38.19#ibcon#read 5, iclass 27, count 0 2006.224.07:44:38.19#ibcon#about to read 6, iclass 27, count 0 2006.224.07:44:38.19#ibcon#read 6, iclass 27, count 0 2006.224.07:44:38.19#ibcon#end of sib2, iclass 27, count 0 2006.224.07:44:38.19#ibcon#*after write, iclass 27, count 0 2006.224.07:44:38.19#ibcon#*before return 0, iclass 27, count 0 2006.224.07:44:38.19#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.224.07:44:38.19#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.224.07:44:38.19#ibcon#about to clear, iclass 27 cls_cnt 0 2006.224.07:44:38.19#ibcon#cleared, iclass 27 cls_cnt 0 2006.224.07:44:38.19$vc4f8/valo=5,652.99 2006.224.07:44:38.19#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.224.07:44:38.19#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.224.07:44:38.19#ibcon#ireg 17 cls_cnt 0 2006.224.07:44:38.19#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.224.07:44:38.19#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.224.07:44:38.19#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.224.07:44:38.19#ibcon#enter wrdev, iclass 29, count 0 2006.224.07:44:38.19#ibcon#first serial, iclass 29, count 0 2006.224.07:44:38.19#ibcon#enter sib2, iclass 29, count 0 2006.224.07:44:38.19#ibcon#flushed, iclass 29, count 0 2006.224.07:44:38.19#ibcon#about to write, iclass 29, count 0 2006.224.07:44:38.19#ibcon#wrote, iclass 29, count 0 2006.224.07:44:38.19#ibcon#about to read 3, iclass 29, count 0 2006.224.07:44:38.21#ibcon#read 3, iclass 29, count 0 2006.224.07:44:38.21#ibcon#about to read 4, iclass 29, count 0 2006.224.07:44:38.21#ibcon#read 4, iclass 29, count 0 2006.224.07:44:38.21#ibcon#about to read 5, iclass 29, count 0 2006.224.07:44:38.21#ibcon#read 5, iclass 29, count 0 2006.224.07:44:38.21#ibcon#about to read 6, iclass 29, count 0 2006.224.07:44:38.21#ibcon#read 6, iclass 29, count 0 2006.224.07:44:38.21#ibcon#end of sib2, iclass 29, count 0 2006.224.07:44:38.21#ibcon#*mode == 0, iclass 29, count 0 2006.224.07:44:38.21#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.224.07:44:38.21#ibcon#[26=FRQ=05,652.99\r\n] 2006.224.07:44:38.21#ibcon#*before write, iclass 29, count 0 2006.224.07:44:38.21#ibcon#enter sib2, iclass 29, count 0 2006.224.07:44:38.21#ibcon#flushed, iclass 29, count 0 2006.224.07:44:38.21#ibcon#about to write, iclass 29, count 0 2006.224.07:44:38.21#ibcon#wrote, iclass 29, count 0 2006.224.07:44:38.21#ibcon#about to read 3, iclass 29, count 0 2006.224.07:44:38.25#ibcon#read 3, iclass 29, count 0 2006.224.07:44:38.25#ibcon#about to read 4, iclass 29, count 0 2006.224.07:44:38.25#ibcon#read 4, iclass 29, count 0 2006.224.07:44:38.25#ibcon#about to read 5, iclass 29, count 0 2006.224.07:44:38.25#ibcon#read 5, iclass 29, count 0 2006.224.07:44:38.25#ibcon#about to read 6, iclass 29, count 0 2006.224.07:44:38.25#ibcon#read 6, iclass 29, count 0 2006.224.07:44:38.25#ibcon#end of sib2, iclass 29, count 0 2006.224.07:44:38.25#ibcon#*after write, iclass 29, count 0 2006.224.07:44:38.25#ibcon#*before return 0, iclass 29, count 0 2006.224.07:44:38.25#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.224.07:44:38.25#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.224.07:44:38.25#ibcon#about to clear, iclass 29 cls_cnt 0 2006.224.07:44:38.25#ibcon#cleared, iclass 29 cls_cnt 0 2006.224.07:44:38.25$vc4f8/va=5,7 2006.224.07:44:38.25#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.224.07:44:38.25#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.224.07:44:38.25#ibcon#ireg 11 cls_cnt 2 2006.224.07:44:38.25#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.224.07:44:38.31#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.224.07:44:38.31#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.224.07:44:38.31#ibcon#enter wrdev, iclass 31, count 2 2006.224.07:44:38.31#ibcon#first serial, iclass 31, count 2 2006.224.07:44:38.31#ibcon#enter sib2, iclass 31, count 2 2006.224.07:44:38.31#ibcon#flushed, iclass 31, count 2 2006.224.07:44:38.31#ibcon#about to write, iclass 31, count 2 2006.224.07:44:38.31#ibcon#wrote, iclass 31, count 2 2006.224.07:44:38.31#ibcon#about to read 3, iclass 31, count 2 2006.224.07:44:38.33#ibcon#read 3, iclass 31, count 2 2006.224.07:44:38.33#ibcon#about to read 4, iclass 31, count 2 2006.224.07:44:38.33#ibcon#read 4, iclass 31, count 2 2006.224.07:44:38.33#ibcon#about to read 5, iclass 31, count 2 2006.224.07:44:38.33#ibcon#read 5, iclass 31, count 2 2006.224.07:44:38.33#ibcon#about to read 6, iclass 31, count 2 2006.224.07:44:38.33#ibcon#read 6, iclass 31, count 2 2006.224.07:44:38.33#ibcon#end of sib2, iclass 31, count 2 2006.224.07:44:38.33#ibcon#*mode == 0, iclass 31, count 2 2006.224.07:44:38.33#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.224.07:44:38.33#ibcon#[25=AT05-07\r\n] 2006.224.07:44:38.33#ibcon#*before write, iclass 31, count 2 2006.224.07:44:38.33#ibcon#enter sib2, iclass 31, count 2 2006.224.07:44:38.33#ibcon#flushed, iclass 31, count 2 2006.224.07:44:38.33#ibcon#about to write, iclass 31, count 2 2006.224.07:44:38.33#ibcon#wrote, iclass 31, count 2 2006.224.07:44:38.33#ibcon#about to read 3, iclass 31, count 2 2006.224.07:44:38.36#ibcon#read 3, iclass 31, count 2 2006.224.07:44:38.36#ibcon#about to read 4, iclass 31, count 2 2006.224.07:44:38.36#ibcon#read 4, iclass 31, count 2 2006.224.07:44:38.36#ibcon#about to read 5, iclass 31, count 2 2006.224.07:44:38.36#ibcon#read 5, iclass 31, count 2 2006.224.07:44:38.36#ibcon#about to read 6, iclass 31, count 2 2006.224.07:44:38.36#ibcon#read 6, iclass 31, count 2 2006.224.07:44:38.36#ibcon#end of sib2, iclass 31, count 2 2006.224.07:44:38.36#ibcon#*after write, iclass 31, count 2 2006.224.07:44:38.36#ibcon#*before return 0, iclass 31, count 2 2006.224.07:44:38.36#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.224.07:44:38.36#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.224.07:44:38.36#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.224.07:44:38.36#ibcon#ireg 7 cls_cnt 0 2006.224.07:44:38.36#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.224.07:44:38.48#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.224.07:44:38.48#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.224.07:44:38.48#ibcon#enter wrdev, iclass 31, count 0 2006.224.07:44:38.48#ibcon#first serial, iclass 31, count 0 2006.224.07:44:38.48#ibcon#enter sib2, iclass 31, count 0 2006.224.07:44:38.48#ibcon#flushed, iclass 31, count 0 2006.224.07:44:38.48#ibcon#about to write, iclass 31, count 0 2006.224.07:44:38.48#ibcon#wrote, iclass 31, count 0 2006.224.07:44:38.48#ibcon#about to read 3, iclass 31, count 0 2006.224.07:44:38.50#ibcon#read 3, iclass 31, count 0 2006.224.07:44:38.50#ibcon#about to read 4, iclass 31, count 0 2006.224.07:44:38.50#ibcon#read 4, iclass 31, count 0 2006.224.07:44:38.50#ibcon#about to read 5, iclass 31, count 0 2006.224.07:44:38.50#ibcon#read 5, iclass 31, count 0 2006.224.07:44:38.50#ibcon#about to read 6, iclass 31, count 0 2006.224.07:44:38.50#ibcon#read 6, iclass 31, count 0 2006.224.07:44:38.50#ibcon#end of sib2, iclass 31, count 0 2006.224.07:44:38.50#ibcon#*mode == 0, iclass 31, count 0 2006.224.07:44:38.50#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.224.07:44:38.50#ibcon#[25=USB\r\n] 2006.224.07:44:38.50#ibcon#*before write, iclass 31, count 0 2006.224.07:44:38.50#ibcon#enter sib2, iclass 31, count 0 2006.224.07:44:38.50#ibcon#flushed, iclass 31, count 0 2006.224.07:44:38.50#ibcon#about to write, iclass 31, count 0 2006.224.07:44:38.50#ibcon#wrote, iclass 31, count 0 2006.224.07:44:38.50#ibcon#about to read 3, iclass 31, count 0 2006.224.07:44:38.53#ibcon#read 3, iclass 31, count 0 2006.224.07:44:38.53#ibcon#about to read 4, iclass 31, count 0 2006.224.07:44:38.53#ibcon#read 4, iclass 31, count 0 2006.224.07:44:38.53#ibcon#about to read 5, iclass 31, count 0 2006.224.07:44:38.53#ibcon#read 5, iclass 31, count 0 2006.224.07:44:38.53#ibcon#about to read 6, iclass 31, count 0 2006.224.07:44:38.53#ibcon#read 6, iclass 31, count 0 2006.224.07:44:38.53#ibcon#end of sib2, iclass 31, count 0 2006.224.07:44:38.53#ibcon#*after write, iclass 31, count 0 2006.224.07:44:38.53#ibcon#*before return 0, iclass 31, count 0 2006.224.07:44:38.53#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.224.07:44:38.53#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.224.07:44:38.53#ibcon#about to clear, iclass 31 cls_cnt 0 2006.224.07:44:38.53#ibcon#cleared, iclass 31 cls_cnt 0 2006.224.07:44:38.53$vc4f8/valo=6,772.99 2006.224.07:44:38.53#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.224.07:44:38.53#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.224.07:44:38.53#ibcon#ireg 17 cls_cnt 0 2006.224.07:44:38.53#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.224.07:44:38.53#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.224.07:44:38.53#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.224.07:44:38.53#ibcon#enter wrdev, iclass 33, count 0 2006.224.07:44:38.53#ibcon#first serial, iclass 33, count 0 2006.224.07:44:38.53#ibcon#enter sib2, iclass 33, count 0 2006.224.07:44:38.53#ibcon#flushed, iclass 33, count 0 2006.224.07:44:38.53#ibcon#about to write, iclass 33, count 0 2006.224.07:44:38.53#ibcon#wrote, iclass 33, count 0 2006.224.07:44:38.53#ibcon#about to read 3, iclass 33, count 0 2006.224.07:44:38.55#ibcon#read 3, iclass 33, count 0 2006.224.07:44:38.55#ibcon#about to read 4, iclass 33, count 0 2006.224.07:44:38.55#ibcon#read 4, iclass 33, count 0 2006.224.07:44:38.55#ibcon#about to read 5, iclass 33, count 0 2006.224.07:44:38.55#ibcon#read 5, iclass 33, count 0 2006.224.07:44:38.55#ibcon#about to read 6, iclass 33, count 0 2006.224.07:44:38.55#ibcon#read 6, iclass 33, count 0 2006.224.07:44:38.55#ibcon#end of sib2, iclass 33, count 0 2006.224.07:44:38.55#ibcon#*mode == 0, iclass 33, count 0 2006.224.07:44:38.55#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.224.07:44:38.55#ibcon#[26=FRQ=06,772.99\r\n] 2006.224.07:44:38.55#ibcon#*before write, iclass 33, count 0 2006.224.07:44:38.55#ibcon#enter sib2, iclass 33, count 0 2006.224.07:44:38.55#ibcon#flushed, iclass 33, count 0 2006.224.07:44:38.55#ibcon#about to write, iclass 33, count 0 2006.224.07:44:38.55#ibcon#wrote, iclass 33, count 0 2006.224.07:44:38.55#ibcon#about to read 3, iclass 33, count 0 2006.224.07:44:38.59#ibcon#read 3, iclass 33, count 0 2006.224.07:44:38.59#ibcon#about to read 4, iclass 33, count 0 2006.224.07:44:38.59#ibcon#read 4, iclass 33, count 0 2006.224.07:44:38.59#ibcon#about to read 5, iclass 33, count 0 2006.224.07:44:38.59#ibcon#read 5, iclass 33, count 0 2006.224.07:44:38.59#ibcon#about to read 6, iclass 33, count 0 2006.224.07:44:38.59#ibcon#read 6, iclass 33, count 0 2006.224.07:44:38.59#ibcon#end of sib2, iclass 33, count 0 2006.224.07:44:38.59#ibcon#*after write, iclass 33, count 0 2006.224.07:44:38.59#ibcon#*before return 0, iclass 33, count 0 2006.224.07:44:38.59#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.224.07:44:38.59#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.224.07:44:38.59#ibcon#about to clear, iclass 33 cls_cnt 0 2006.224.07:44:38.59#ibcon#cleared, iclass 33 cls_cnt 0 2006.224.07:44:38.59$vc4f8/va=6,6 2006.224.07:44:38.59#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.224.07:44:38.59#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.224.07:44:38.59#ibcon#ireg 11 cls_cnt 2 2006.224.07:44:38.59#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.224.07:44:38.66#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.224.07:44:38.66#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.224.07:44:38.66#ibcon#enter wrdev, iclass 35, count 2 2006.224.07:44:38.66#ibcon#first serial, iclass 35, count 2 2006.224.07:44:38.66#ibcon#enter sib2, iclass 35, count 2 2006.224.07:44:38.66#ibcon#flushed, iclass 35, count 2 2006.224.07:44:38.66#ibcon#about to write, iclass 35, count 2 2006.224.07:44:38.66#ibcon#wrote, iclass 35, count 2 2006.224.07:44:38.66#ibcon#about to read 3, iclass 35, count 2 2006.224.07:44:38.67#ibcon#read 3, iclass 35, count 2 2006.224.07:44:38.67#ibcon#about to read 4, iclass 35, count 2 2006.224.07:44:38.67#ibcon#read 4, iclass 35, count 2 2006.224.07:44:38.67#ibcon#about to read 5, iclass 35, count 2 2006.224.07:44:38.67#ibcon#read 5, iclass 35, count 2 2006.224.07:44:38.67#ibcon#about to read 6, iclass 35, count 2 2006.224.07:44:38.67#ibcon#read 6, iclass 35, count 2 2006.224.07:44:38.67#ibcon#end of sib2, iclass 35, count 2 2006.224.07:44:38.67#ibcon#*mode == 0, iclass 35, count 2 2006.224.07:44:38.67#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.224.07:44:38.67#ibcon#[25=AT06-06\r\n] 2006.224.07:44:38.67#ibcon#*before write, iclass 35, count 2 2006.224.07:44:38.67#ibcon#enter sib2, iclass 35, count 2 2006.224.07:44:38.67#ibcon#flushed, iclass 35, count 2 2006.224.07:44:38.67#ibcon#about to write, iclass 35, count 2 2006.224.07:44:38.67#ibcon#wrote, iclass 35, count 2 2006.224.07:44:38.67#ibcon#about to read 3, iclass 35, count 2 2006.224.07:44:38.70#ibcon#read 3, iclass 35, count 2 2006.224.07:44:38.70#ibcon#about to read 4, iclass 35, count 2 2006.224.07:44:38.70#ibcon#read 4, iclass 35, count 2 2006.224.07:44:38.70#ibcon#about to read 5, iclass 35, count 2 2006.224.07:44:38.70#ibcon#read 5, iclass 35, count 2 2006.224.07:44:38.70#ibcon#about to read 6, iclass 35, count 2 2006.224.07:44:38.70#ibcon#read 6, iclass 35, count 2 2006.224.07:44:38.70#ibcon#end of sib2, iclass 35, count 2 2006.224.07:44:38.70#ibcon#*after write, iclass 35, count 2 2006.224.07:44:38.70#ibcon#*before return 0, iclass 35, count 2 2006.224.07:44:38.70#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.224.07:44:38.70#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.224.07:44:38.70#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.224.07:44:38.70#ibcon#ireg 7 cls_cnt 0 2006.224.07:44:38.70#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.224.07:44:38.82#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.224.07:44:38.82#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.224.07:44:38.82#ibcon#enter wrdev, iclass 35, count 0 2006.224.07:44:38.82#ibcon#first serial, iclass 35, count 0 2006.224.07:44:38.82#ibcon#enter sib2, iclass 35, count 0 2006.224.07:44:38.82#ibcon#flushed, iclass 35, count 0 2006.224.07:44:38.82#ibcon#about to write, iclass 35, count 0 2006.224.07:44:38.82#ibcon#wrote, iclass 35, count 0 2006.224.07:44:38.82#ibcon#about to read 3, iclass 35, count 0 2006.224.07:44:38.84#ibcon#read 3, iclass 35, count 0 2006.224.07:44:38.84#ibcon#about to read 4, iclass 35, count 0 2006.224.07:44:38.84#ibcon#read 4, iclass 35, count 0 2006.224.07:44:38.84#ibcon#about to read 5, iclass 35, count 0 2006.224.07:44:38.84#ibcon#read 5, iclass 35, count 0 2006.224.07:44:38.84#ibcon#about to read 6, iclass 35, count 0 2006.224.07:44:38.84#ibcon#read 6, iclass 35, count 0 2006.224.07:44:38.84#ibcon#end of sib2, iclass 35, count 0 2006.224.07:44:38.84#ibcon#*mode == 0, iclass 35, count 0 2006.224.07:44:38.84#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.224.07:44:38.84#ibcon#[25=USB\r\n] 2006.224.07:44:38.84#ibcon#*before write, iclass 35, count 0 2006.224.07:44:38.84#ibcon#enter sib2, iclass 35, count 0 2006.224.07:44:38.84#ibcon#flushed, iclass 35, count 0 2006.224.07:44:38.84#ibcon#about to write, iclass 35, count 0 2006.224.07:44:38.84#ibcon#wrote, iclass 35, count 0 2006.224.07:44:38.84#ibcon#about to read 3, iclass 35, count 0 2006.224.07:44:38.87#ibcon#read 3, iclass 35, count 0 2006.224.07:44:38.87#ibcon#about to read 4, iclass 35, count 0 2006.224.07:44:38.87#ibcon#read 4, iclass 35, count 0 2006.224.07:44:38.87#ibcon#about to read 5, iclass 35, count 0 2006.224.07:44:38.87#ibcon#read 5, iclass 35, count 0 2006.224.07:44:38.87#ibcon#about to read 6, iclass 35, count 0 2006.224.07:44:38.87#ibcon#read 6, iclass 35, count 0 2006.224.07:44:38.87#ibcon#end of sib2, iclass 35, count 0 2006.224.07:44:38.87#ibcon#*after write, iclass 35, count 0 2006.224.07:44:38.87#ibcon#*before return 0, iclass 35, count 0 2006.224.07:44:38.87#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.224.07:44:38.87#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.224.07:44:38.87#ibcon#about to clear, iclass 35 cls_cnt 0 2006.224.07:44:38.87#ibcon#cleared, iclass 35 cls_cnt 0 2006.224.07:44:38.87$vc4f8/valo=7,832.99 2006.224.07:44:38.87#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.224.07:44:38.87#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.224.07:44:38.87#ibcon#ireg 17 cls_cnt 0 2006.224.07:44:38.87#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.224.07:44:38.87#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.224.07:44:38.87#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.224.07:44:38.87#ibcon#enter wrdev, iclass 37, count 0 2006.224.07:44:38.87#ibcon#first serial, iclass 37, count 0 2006.224.07:44:38.87#ibcon#enter sib2, iclass 37, count 0 2006.224.07:44:38.87#ibcon#flushed, iclass 37, count 0 2006.224.07:44:38.87#ibcon#about to write, iclass 37, count 0 2006.224.07:44:38.87#ibcon#wrote, iclass 37, count 0 2006.224.07:44:38.87#ibcon#about to read 3, iclass 37, count 0 2006.224.07:44:38.89#ibcon#read 3, iclass 37, count 0 2006.224.07:44:38.89#ibcon#about to read 4, iclass 37, count 0 2006.224.07:44:38.89#ibcon#read 4, iclass 37, count 0 2006.224.07:44:38.89#ibcon#about to read 5, iclass 37, count 0 2006.224.07:44:38.89#ibcon#read 5, iclass 37, count 0 2006.224.07:44:38.89#ibcon#about to read 6, iclass 37, count 0 2006.224.07:44:38.89#ibcon#read 6, iclass 37, count 0 2006.224.07:44:38.89#ibcon#end of sib2, iclass 37, count 0 2006.224.07:44:38.89#ibcon#*mode == 0, iclass 37, count 0 2006.224.07:44:38.89#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.224.07:44:38.89#ibcon#[26=FRQ=07,832.99\r\n] 2006.224.07:44:38.89#ibcon#*before write, iclass 37, count 0 2006.224.07:44:38.89#ibcon#enter sib2, iclass 37, count 0 2006.224.07:44:38.89#ibcon#flushed, iclass 37, count 0 2006.224.07:44:38.89#ibcon#about to write, iclass 37, count 0 2006.224.07:44:38.89#ibcon#wrote, iclass 37, count 0 2006.224.07:44:38.89#ibcon#about to read 3, iclass 37, count 0 2006.224.07:44:38.93#ibcon#read 3, iclass 37, count 0 2006.224.07:44:38.93#ibcon#about to read 4, iclass 37, count 0 2006.224.07:44:38.93#ibcon#read 4, iclass 37, count 0 2006.224.07:44:38.93#ibcon#about to read 5, iclass 37, count 0 2006.224.07:44:38.93#ibcon#read 5, iclass 37, count 0 2006.224.07:44:38.93#ibcon#about to read 6, iclass 37, count 0 2006.224.07:44:38.93#ibcon#read 6, iclass 37, count 0 2006.224.07:44:38.93#ibcon#end of sib2, iclass 37, count 0 2006.224.07:44:38.93#ibcon#*after write, iclass 37, count 0 2006.224.07:44:38.93#ibcon#*before return 0, iclass 37, count 0 2006.224.07:44:38.93#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.224.07:44:38.93#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.224.07:44:38.93#ibcon#about to clear, iclass 37 cls_cnt 0 2006.224.07:44:38.93#ibcon#cleared, iclass 37 cls_cnt 0 2006.224.07:44:38.93$vc4f8/va=7,6 2006.224.07:44:38.93#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.224.07:44:38.93#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.224.07:44:38.93#ibcon#ireg 11 cls_cnt 2 2006.224.07:44:38.93#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.224.07:44:38.99#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.224.07:44:38.99#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.224.07:44:38.99#ibcon#enter wrdev, iclass 39, count 2 2006.224.07:44:38.99#ibcon#first serial, iclass 39, count 2 2006.224.07:44:38.99#ibcon#enter sib2, iclass 39, count 2 2006.224.07:44:38.99#ibcon#flushed, iclass 39, count 2 2006.224.07:44:38.99#ibcon#about to write, iclass 39, count 2 2006.224.07:44:38.99#ibcon#wrote, iclass 39, count 2 2006.224.07:44:38.99#ibcon#about to read 3, iclass 39, count 2 2006.224.07:44:39.01#ibcon#read 3, iclass 39, count 2 2006.224.07:44:39.01#ibcon#about to read 4, iclass 39, count 2 2006.224.07:44:39.01#ibcon#read 4, iclass 39, count 2 2006.224.07:44:39.01#ibcon#about to read 5, iclass 39, count 2 2006.224.07:44:39.01#ibcon#read 5, iclass 39, count 2 2006.224.07:44:39.01#ibcon#about to read 6, iclass 39, count 2 2006.224.07:44:39.01#ibcon#read 6, iclass 39, count 2 2006.224.07:44:39.01#ibcon#end of sib2, iclass 39, count 2 2006.224.07:44:39.01#ibcon#*mode == 0, iclass 39, count 2 2006.224.07:44:39.01#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.224.07:44:39.01#ibcon#[25=AT07-06\r\n] 2006.224.07:44:39.01#ibcon#*before write, iclass 39, count 2 2006.224.07:44:39.01#ibcon#enter sib2, iclass 39, count 2 2006.224.07:44:39.01#ibcon#flushed, iclass 39, count 2 2006.224.07:44:39.01#ibcon#about to write, iclass 39, count 2 2006.224.07:44:39.01#ibcon#wrote, iclass 39, count 2 2006.224.07:44:39.01#ibcon#about to read 3, iclass 39, count 2 2006.224.07:44:39.04#ibcon#read 3, iclass 39, count 2 2006.224.07:44:39.04#ibcon#about to read 4, iclass 39, count 2 2006.224.07:44:39.04#ibcon#read 4, iclass 39, count 2 2006.224.07:44:39.04#ibcon#about to read 5, iclass 39, count 2 2006.224.07:44:39.04#ibcon#read 5, iclass 39, count 2 2006.224.07:44:39.04#ibcon#about to read 6, iclass 39, count 2 2006.224.07:44:39.04#ibcon#read 6, iclass 39, count 2 2006.224.07:44:39.04#ibcon#end of sib2, iclass 39, count 2 2006.224.07:44:39.04#ibcon#*after write, iclass 39, count 2 2006.224.07:44:39.04#ibcon#*before return 0, iclass 39, count 2 2006.224.07:44:39.04#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.224.07:44:39.04#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.224.07:44:39.04#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.224.07:44:39.04#ibcon#ireg 7 cls_cnt 0 2006.224.07:44:39.04#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.224.07:44:39.16#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.224.07:44:39.16#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.224.07:44:39.16#ibcon#enter wrdev, iclass 39, count 0 2006.224.07:44:39.16#ibcon#first serial, iclass 39, count 0 2006.224.07:44:39.16#ibcon#enter sib2, iclass 39, count 0 2006.224.07:44:39.16#ibcon#flushed, iclass 39, count 0 2006.224.07:44:39.16#ibcon#about to write, iclass 39, count 0 2006.224.07:44:39.16#ibcon#wrote, iclass 39, count 0 2006.224.07:44:39.16#ibcon#about to read 3, iclass 39, count 0 2006.224.07:44:39.18#ibcon#read 3, iclass 39, count 0 2006.224.07:44:39.18#ibcon#about to read 4, iclass 39, count 0 2006.224.07:44:39.18#ibcon#read 4, iclass 39, count 0 2006.224.07:44:39.18#ibcon#about to read 5, iclass 39, count 0 2006.224.07:44:39.18#ibcon#read 5, iclass 39, count 0 2006.224.07:44:39.18#ibcon#about to read 6, iclass 39, count 0 2006.224.07:44:39.18#ibcon#read 6, iclass 39, count 0 2006.224.07:44:39.18#ibcon#end of sib2, iclass 39, count 0 2006.224.07:44:39.18#ibcon#*mode == 0, iclass 39, count 0 2006.224.07:44:39.18#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.224.07:44:39.18#ibcon#[25=USB\r\n] 2006.224.07:44:39.18#ibcon#*before write, iclass 39, count 0 2006.224.07:44:39.18#ibcon#enter sib2, iclass 39, count 0 2006.224.07:44:39.18#ibcon#flushed, iclass 39, count 0 2006.224.07:44:39.18#ibcon#about to write, iclass 39, count 0 2006.224.07:44:39.18#ibcon#wrote, iclass 39, count 0 2006.224.07:44:39.18#ibcon#about to read 3, iclass 39, count 0 2006.224.07:44:39.21#ibcon#read 3, iclass 39, count 0 2006.224.07:44:39.21#ibcon#about to read 4, iclass 39, count 0 2006.224.07:44:39.21#ibcon#read 4, iclass 39, count 0 2006.224.07:44:39.21#ibcon#about to read 5, iclass 39, count 0 2006.224.07:44:39.21#ibcon#read 5, iclass 39, count 0 2006.224.07:44:39.21#ibcon#about to read 6, iclass 39, count 0 2006.224.07:44:39.21#ibcon#read 6, iclass 39, count 0 2006.224.07:44:39.21#ibcon#end of sib2, iclass 39, count 0 2006.224.07:44:39.21#ibcon#*after write, iclass 39, count 0 2006.224.07:44:39.21#ibcon#*before return 0, iclass 39, count 0 2006.224.07:44:39.21#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.224.07:44:39.21#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.224.07:44:39.21#ibcon#about to clear, iclass 39 cls_cnt 0 2006.224.07:44:39.21#ibcon#cleared, iclass 39 cls_cnt 0 2006.224.07:44:39.21$vc4f8/valo=8,852.99 2006.224.07:44:39.21#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.224.07:44:39.21#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.224.07:44:39.21#ibcon#ireg 17 cls_cnt 0 2006.224.07:44:39.21#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.224.07:44:39.21#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.224.07:44:39.21#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.224.07:44:39.21#ibcon#enter wrdev, iclass 3, count 0 2006.224.07:44:39.21#ibcon#first serial, iclass 3, count 0 2006.224.07:44:39.21#ibcon#enter sib2, iclass 3, count 0 2006.224.07:44:39.21#ibcon#flushed, iclass 3, count 0 2006.224.07:44:39.21#ibcon#about to write, iclass 3, count 0 2006.224.07:44:39.21#ibcon#wrote, iclass 3, count 0 2006.224.07:44:39.21#ibcon#about to read 3, iclass 3, count 0 2006.224.07:44:39.23#ibcon#read 3, iclass 3, count 0 2006.224.07:44:39.23#ibcon#about to read 4, iclass 3, count 0 2006.224.07:44:39.23#ibcon#read 4, iclass 3, count 0 2006.224.07:44:39.23#ibcon#about to read 5, iclass 3, count 0 2006.224.07:44:39.23#ibcon#read 5, iclass 3, count 0 2006.224.07:44:39.23#ibcon#about to read 6, iclass 3, count 0 2006.224.07:44:39.23#ibcon#read 6, iclass 3, count 0 2006.224.07:44:39.23#ibcon#end of sib2, iclass 3, count 0 2006.224.07:44:39.23#ibcon#*mode == 0, iclass 3, count 0 2006.224.07:44:39.23#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.224.07:44:39.23#ibcon#[26=FRQ=08,852.99\r\n] 2006.224.07:44:39.23#ibcon#*before write, iclass 3, count 0 2006.224.07:44:39.23#ibcon#enter sib2, iclass 3, count 0 2006.224.07:44:39.23#ibcon#flushed, iclass 3, count 0 2006.224.07:44:39.23#ibcon#about to write, iclass 3, count 0 2006.224.07:44:39.23#ibcon#wrote, iclass 3, count 0 2006.224.07:44:39.23#ibcon#about to read 3, iclass 3, count 0 2006.224.07:44:39.27#ibcon#read 3, iclass 3, count 0 2006.224.07:44:39.27#ibcon#about to read 4, iclass 3, count 0 2006.224.07:44:39.27#ibcon#read 4, iclass 3, count 0 2006.224.07:44:39.27#ibcon#about to read 5, iclass 3, count 0 2006.224.07:44:39.27#ibcon#read 5, iclass 3, count 0 2006.224.07:44:39.27#ibcon#about to read 6, iclass 3, count 0 2006.224.07:44:39.27#ibcon#read 6, iclass 3, count 0 2006.224.07:44:39.27#ibcon#end of sib2, iclass 3, count 0 2006.224.07:44:39.27#ibcon#*after write, iclass 3, count 0 2006.224.07:44:39.27#ibcon#*before return 0, iclass 3, count 0 2006.224.07:44:39.27#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.224.07:44:39.27#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.224.07:44:39.27#ibcon#about to clear, iclass 3 cls_cnt 0 2006.224.07:44:39.27#ibcon#cleared, iclass 3 cls_cnt 0 2006.224.07:44:39.27$vc4f8/va=8,7 2006.224.07:44:39.27#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.224.07:44:39.27#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.224.07:44:39.27#ibcon#ireg 11 cls_cnt 2 2006.224.07:44:39.27#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.224.07:44:39.33#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.224.07:44:39.33#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.224.07:44:39.33#ibcon#enter wrdev, iclass 5, count 2 2006.224.07:44:39.33#ibcon#first serial, iclass 5, count 2 2006.224.07:44:39.33#ibcon#enter sib2, iclass 5, count 2 2006.224.07:44:39.33#ibcon#flushed, iclass 5, count 2 2006.224.07:44:39.33#ibcon#about to write, iclass 5, count 2 2006.224.07:44:39.33#ibcon#wrote, iclass 5, count 2 2006.224.07:44:39.33#ibcon#about to read 3, iclass 5, count 2 2006.224.07:44:39.35#ibcon#read 3, iclass 5, count 2 2006.224.07:44:39.35#ibcon#about to read 4, iclass 5, count 2 2006.224.07:44:39.35#ibcon#read 4, iclass 5, count 2 2006.224.07:44:39.35#ibcon#about to read 5, iclass 5, count 2 2006.224.07:44:39.35#ibcon#read 5, iclass 5, count 2 2006.224.07:44:39.35#ibcon#about to read 6, iclass 5, count 2 2006.224.07:44:39.35#ibcon#read 6, iclass 5, count 2 2006.224.07:44:39.35#ibcon#end of sib2, iclass 5, count 2 2006.224.07:44:39.35#ibcon#*mode == 0, iclass 5, count 2 2006.224.07:44:39.35#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.224.07:44:39.35#ibcon#[25=AT08-07\r\n] 2006.224.07:44:39.35#ibcon#*before write, iclass 5, count 2 2006.224.07:44:39.35#ibcon#enter sib2, iclass 5, count 2 2006.224.07:44:39.35#ibcon#flushed, iclass 5, count 2 2006.224.07:44:39.35#ibcon#about to write, iclass 5, count 2 2006.224.07:44:39.35#ibcon#wrote, iclass 5, count 2 2006.224.07:44:39.35#ibcon#about to read 3, iclass 5, count 2 2006.224.07:44:39.38#ibcon#read 3, iclass 5, count 2 2006.224.07:44:39.38#ibcon#about to read 4, iclass 5, count 2 2006.224.07:44:39.38#ibcon#read 4, iclass 5, count 2 2006.224.07:44:39.38#ibcon#about to read 5, iclass 5, count 2 2006.224.07:44:39.38#ibcon#read 5, iclass 5, count 2 2006.224.07:44:39.38#ibcon#about to read 6, iclass 5, count 2 2006.224.07:44:39.38#ibcon#read 6, iclass 5, count 2 2006.224.07:44:39.38#ibcon#end of sib2, iclass 5, count 2 2006.224.07:44:39.38#ibcon#*after write, iclass 5, count 2 2006.224.07:44:39.38#ibcon#*before return 0, iclass 5, count 2 2006.224.07:44:39.38#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.224.07:44:39.38#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.224.07:44:39.38#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.224.07:44:39.38#ibcon#ireg 7 cls_cnt 0 2006.224.07:44:39.38#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.224.07:44:39.51#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.224.07:44:39.51#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.224.07:44:39.51#ibcon#enter wrdev, iclass 5, count 0 2006.224.07:44:39.51#ibcon#first serial, iclass 5, count 0 2006.224.07:44:39.51#ibcon#enter sib2, iclass 5, count 0 2006.224.07:44:39.51#ibcon#flushed, iclass 5, count 0 2006.224.07:44:39.51#ibcon#about to write, iclass 5, count 0 2006.224.07:44:39.51#ibcon#wrote, iclass 5, count 0 2006.224.07:44:39.51#ibcon#about to read 3, iclass 5, count 0 2006.224.07:44:39.52#ibcon#read 3, iclass 5, count 0 2006.224.07:44:39.52#ibcon#about to read 4, iclass 5, count 0 2006.224.07:44:39.52#ibcon#read 4, iclass 5, count 0 2006.224.07:44:39.52#ibcon#about to read 5, iclass 5, count 0 2006.224.07:44:39.52#ibcon#read 5, iclass 5, count 0 2006.224.07:44:39.52#ibcon#about to read 6, iclass 5, count 0 2006.224.07:44:39.52#ibcon#read 6, iclass 5, count 0 2006.224.07:44:39.52#ibcon#end of sib2, iclass 5, count 0 2006.224.07:44:39.52#ibcon#*mode == 0, iclass 5, count 0 2006.224.07:44:39.52#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.224.07:44:39.52#ibcon#[25=USB\r\n] 2006.224.07:44:39.52#ibcon#*before write, iclass 5, count 0 2006.224.07:44:39.52#ibcon#enter sib2, iclass 5, count 0 2006.224.07:44:39.52#ibcon#flushed, iclass 5, count 0 2006.224.07:44:39.52#ibcon#about to write, iclass 5, count 0 2006.224.07:44:39.52#ibcon#wrote, iclass 5, count 0 2006.224.07:44:39.52#ibcon#about to read 3, iclass 5, count 0 2006.224.07:44:39.55#ibcon#read 3, iclass 5, count 0 2006.224.07:44:39.55#ibcon#about to read 4, iclass 5, count 0 2006.224.07:44:39.55#ibcon#read 4, iclass 5, count 0 2006.224.07:44:39.55#ibcon#about to read 5, iclass 5, count 0 2006.224.07:44:39.55#ibcon#read 5, iclass 5, count 0 2006.224.07:44:39.55#ibcon#about to read 6, iclass 5, count 0 2006.224.07:44:39.55#ibcon#read 6, iclass 5, count 0 2006.224.07:44:39.55#ibcon#end of sib2, iclass 5, count 0 2006.224.07:44:39.55#ibcon#*after write, iclass 5, count 0 2006.224.07:44:39.55#ibcon#*before return 0, iclass 5, count 0 2006.224.07:44:39.55#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.224.07:44:39.55#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.224.07:44:39.55#ibcon#about to clear, iclass 5 cls_cnt 0 2006.224.07:44:39.55#ibcon#cleared, iclass 5 cls_cnt 0 2006.224.07:44:39.55$vc4f8/vblo=1,632.99 2006.224.07:44:39.55#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.224.07:44:39.55#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.224.07:44:39.55#ibcon#ireg 17 cls_cnt 0 2006.224.07:44:39.55#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.224.07:44:39.55#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.224.07:44:39.55#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.224.07:44:39.55#ibcon#enter wrdev, iclass 7, count 0 2006.224.07:44:39.55#ibcon#first serial, iclass 7, count 0 2006.224.07:44:39.55#ibcon#enter sib2, iclass 7, count 0 2006.224.07:44:39.55#ibcon#flushed, iclass 7, count 0 2006.224.07:44:39.55#ibcon#about to write, iclass 7, count 0 2006.224.07:44:39.55#ibcon#wrote, iclass 7, count 0 2006.224.07:44:39.55#ibcon#about to read 3, iclass 7, count 0 2006.224.07:44:39.57#ibcon#read 3, iclass 7, count 0 2006.224.07:44:39.57#ibcon#about to read 4, iclass 7, count 0 2006.224.07:44:39.57#ibcon#read 4, iclass 7, count 0 2006.224.07:44:39.57#ibcon#about to read 5, iclass 7, count 0 2006.224.07:44:39.57#ibcon#read 5, iclass 7, count 0 2006.224.07:44:39.57#ibcon#about to read 6, iclass 7, count 0 2006.224.07:44:39.57#ibcon#read 6, iclass 7, count 0 2006.224.07:44:39.57#ibcon#end of sib2, iclass 7, count 0 2006.224.07:44:39.57#ibcon#*mode == 0, iclass 7, count 0 2006.224.07:44:39.57#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.224.07:44:39.57#ibcon#[28=FRQ=01,632.99\r\n] 2006.224.07:44:39.57#ibcon#*before write, iclass 7, count 0 2006.224.07:44:39.57#ibcon#enter sib2, iclass 7, count 0 2006.224.07:44:39.57#ibcon#flushed, iclass 7, count 0 2006.224.07:44:39.57#ibcon#about to write, iclass 7, count 0 2006.224.07:44:39.57#ibcon#wrote, iclass 7, count 0 2006.224.07:44:39.57#ibcon#about to read 3, iclass 7, count 0 2006.224.07:44:39.61#ibcon#read 3, iclass 7, count 0 2006.224.07:44:39.61#ibcon#about to read 4, iclass 7, count 0 2006.224.07:44:39.61#ibcon#read 4, iclass 7, count 0 2006.224.07:44:39.61#ibcon#about to read 5, iclass 7, count 0 2006.224.07:44:39.61#ibcon#read 5, iclass 7, count 0 2006.224.07:44:39.61#ibcon#about to read 6, iclass 7, count 0 2006.224.07:44:39.61#ibcon#read 6, iclass 7, count 0 2006.224.07:44:39.61#ibcon#end of sib2, iclass 7, count 0 2006.224.07:44:39.61#ibcon#*after write, iclass 7, count 0 2006.224.07:44:39.61#ibcon#*before return 0, iclass 7, count 0 2006.224.07:44:39.61#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.224.07:44:39.61#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.224.07:44:39.61#ibcon#about to clear, iclass 7 cls_cnt 0 2006.224.07:44:39.61#ibcon#cleared, iclass 7 cls_cnt 0 2006.224.07:44:39.61$vc4f8/vb=1,4 2006.224.07:44:39.61#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.224.07:44:39.61#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.224.07:44:39.61#ibcon#ireg 11 cls_cnt 2 2006.224.07:44:39.61#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.224.07:44:39.61#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.224.07:44:39.61#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.224.07:44:39.61#ibcon#enter wrdev, iclass 11, count 2 2006.224.07:44:39.61#ibcon#first serial, iclass 11, count 2 2006.224.07:44:39.61#ibcon#enter sib2, iclass 11, count 2 2006.224.07:44:39.61#ibcon#flushed, iclass 11, count 2 2006.224.07:44:39.61#ibcon#about to write, iclass 11, count 2 2006.224.07:44:39.61#ibcon#wrote, iclass 11, count 2 2006.224.07:44:39.61#ibcon#about to read 3, iclass 11, count 2 2006.224.07:44:39.63#ibcon#read 3, iclass 11, count 2 2006.224.07:44:39.63#ibcon#about to read 4, iclass 11, count 2 2006.224.07:44:39.63#ibcon#read 4, iclass 11, count 2 2006.224.07:44:39.63#ibcon#about to read 5, iclass 11, count 2 2006.224.07:44:39.63#ibcon#read 5, iclass 11, count 2 2006.224.07:44:39.63#ibcon#about to read 6, iclass 11, count 2 2006.224.07:44:39.63#ibcon#read 6, iclass 11, count 2 2006.224.07:44:39.63#ibcon#end of sib2, iclass 11, count 2 2006.224.07:44:39.63#ibcon#*mode == 0, iclass 11, count 2 2006.224.07:44:39.63#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.224.07:44:39.63#ibcon#[27=AT01-04\r\n] 2006.224.07:44:39.63#ibcon#*before write, iclass 11, count 2 2006.224.07:44:39.63#ibcon#enter sib2, iclass 11, count 2 2006.224.07:44:39.63#ibcon#flushed, iclass 11, count 2 2006.224.07:44:39.63#ibcon#about to write, iclass 11, count 2 2006.224.07:44:39.63#ibcon#wrote, iclass 11, count 2 2006.224.07:44:39.63#ibcon#about to read 3, iclass 11, count 2 2006.224.07:44:39.66#ibcon#read 3, iclass 11, count 2 2006.224.07:44:39.66#ibcon#about to read 4, iclass 11, count 2 2006.224.07:44:39.66#ibcon#read 4, iclass 11, count 2 2006.224.07:44:39.66#ibcon#about to read 5, iclass 11, count 2 2006.224.07:44:39.66#ibcon#read 5, iclass 11, count 2 2006.224.07:44:39.66#ibcon#about to read 6, iclass 11, count 2 2006.224.07:44:39.66#ibcon#read 6, iclass 11, count 2 2006.224.07:44:39.66#ibcon#end of sib2, iclass 11, count 2 2006.224.07:44:39.66#ibcon#*after write, iclass 11, count 2 2006.224.07:44:39.66#ibcon#*before return 0, iclass 11, count 2 2006.224.07:44:39.66#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.224.07:44:39.66#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.224.07:44:39.66#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.224.07:44:39.66#ibcon#ireg 7 cls_cnt 0 2006.224.07:44:39.66#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.224.07:44:39.78#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.224.07:44:39.78#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.224.07:44:39.78#ibcon#enter wrdev, iclass 11, count 0 2006.224.07:44:39.78#ibcon#first serial, iclass 11, count 0 2006.224.07:44:39.78#ibcon#enter sib2, iclass 11, count 0 2006.224.07:44:39.78#ibcon#flushed, iclass 11, count 0 2006.224.07:44:39.78#ibcon#about to write, iclass 11, count 0 2006.224.07:44:39.78#ibcon#wrote, iclass 11, count 0 2006.224.07:44:39.78#ibcon#about to read 3, iclass 11, count 0 2006.224.07:44:39.80#ibcon#read 3, iclass 11, count 0 2006.224.07:44:39.80#ibcon#about to read 4, iclass 11, count 0 2006.224.07:44:39.80#ibcon#read 4, iclass 11, count 0 2006.224.07:44:39.80#ibcon#about to read 5, iclass 11, count 0 2006.224.07:44:39.80#ibcon#read 5, iclass 11, count 0 2006.224.07:44:39.80#ibcon#about to read 6, iclass 11, count 0 2006.224.07:44:39.80#ibcon#read 6, iclass 11, count 0 2006.224.07:44:39.80#ibcon#end of sib2, iclass 11, count 0 2006.224.07:44:39.80#ibcon#*mode == 0, iclass 11, count 0 2006.224.07:44:39.80#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.224.07:44:39.80#ibcon#[27=USB\r\n] 2006.224.07:44:39.80#ibcon#*before write, iclass 11, count 0 2006.224.07:44:39.80#ibcon#enter sib2, iclass 11, count 0 2006.224.07:44:39.80#ibcon#flushed, iclass 11, count 0 2006.224.07:44:39.80#ibcon#about to write, iclass 11, count 0 2006.224.07:44:39.80#ibcon#wrote, iclass 11, count 0 2006.224.07:44:39.80#ibcon#about to read 3, iclass 11, count 0 2006.224.07:44:39.83#ibcon#read 3, iclass 11, count 0 2006.224.07:44:39.83#ibcon#about to read 4, iclass 11, count 0 2006.224.07:44:39.83#ibcon#read 4, iclass 11, count 0 2006.224.07:44:39.83#ibcon#about to read 5, iclass 11, count 0 2006.224.07:44:39.83#ibcon#read 5, iclass 11, count 0 2006.224.07:44:39.83#ibcon#about to read 6, iclass 11, count 0 2006.224.07:44:39.83#ibcon#read 6, iclass 11, count 0 2006.224.07:44:39.83#ibcon#end of sib2, iclass 11, count 0 2006.224.07:44:39.83#ibcon#*after write, iclass 11, count 0 2006.224.07:44:39.83#ibcon#*before return 0, iclass 11, count 0 2006.224.07:44:39.83#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.224.07:44:39.83#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.224.07:44:39.83#ibcon#about to clear, iclass 11 cls_cnt 0 2006.224.07:44:39.83#ibcon#cleared, iclass 11 cls_cnt 0 2006.224.07:44:39.83$vc4f8/vblo=2,640.99 2006.224.07:44:39.83#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.224.07:44:39.83#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.224.07:44:39.83#ibcon#ireg 17 cls_cnt 0 2006.224.07:44:39.83#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.224.07:44:39.83#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.224.07:44:39.83#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.224.07:44:39.83#ibcon#enter wrdev, iclass 13, count 0 2006.224.07:44:39.83#ibcon#first serial, iclass 13, count 0 2006.224.07:44:39.83#ibcon#enter sib2, iclass 13, count 0 2006.224.07:44:39.83#ibcon#flushed, iclass 13, count 0 2006.224.07:44:39.83#ibcon#about to write, iclass 13, count 0 2006.224.07:44:39.83#ibcon#wrote, iclass 13, count 0 2006.224.07:44:39.83#ibcon#about to read 3, iclass 13, count 0 2006.224.07:44:39.85#ibcon#read 3, iclass 13, count 0 2006.224.07:44:39.85#ibcon#about to read 4, iclass 13, count 0 2006.224.07:44:39.85#ibcon#read 4, iclass 13, count 0 2006.224.07:44:39.85#ibcon#about to read 5, iclass 13, count 0 2006.224.07:44:39.85#ibcon#read 5, iclass 13, count 0 2006.224.07:44:39.85#ibcon#about to read 6, iclass 13, count 0 2006.224.07:44:39.85#ibcon#read 6, iclass 13, count 0 2006.224.07:44:39.85#ibcon#end of sib2, iclass 13, count 0 2006.224.07:44:39.85#ibcon#*mode == 0, iclass 13, count 0 2006.224.07:44:39.85#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.224.07:44:39.85#ibcon#[28=FRQ=02,640.99\r\n] 2006.224.07:44:39.85#ibcon#*before write, iclass 13, count 0 2006.224.07:44:39.85#ibcon#enter sib2, iclass 13, count 0 2006.224.07:44:39.85#ibcon#flushed, iclass 13, count 0 2006.224.07:44:39.85#ibcon#about to write, iclass 13, count 0 2006.224.07:44:39.85#ibcon#wrote, iclass 13, count 0 2006.224.07:44:39.85#ibcon#about to read 3, iclass 13, count 0 2006.224.07:44:39.89#ibcon#read 3, iclass 13, count 0 2006.224.07:44:39.89#ibcon#about to read 4, iclass 13, count 0 2006.224.07:44:39.89#ibcon#read 4, iclass 13, count 0 2006.224.07:44:39.89#ibcon#about to read 5, iclass 13, count 0 2006.224.07:44:39.89#ibcon#read 5, iclass 13, count 0 2006.224.07:44:39.89#ibcon#about to read 6, iclass 13, count 0 2006.224.07:44:39.89#ibcon#read 6, iclass 13, count 0 2006.224.07:44:39.89#ibcon#end of sib2, iclass 13, count 0 2006.224.07:44:39.89#ibcon#*after write, iclass 13, count 0 2006.224.07:44:39.89#ibcon#*before return 0, iclass 13, count 0 2006.224.07:44:39.89#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.224.07:44:39.89#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.224.07:44:39.89#ibcon#about to clear, iclass 13 cls_cnt 0 2006.224.07:44:39.89#ibcon#cleared, iclass 13 cls_cnt 0 2006.224.07:44:39.89$vc4f8/vb=2,4 2006.224.07:44:39.89#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.224.07:44:39.89#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.224.07:44:39.89#ibcon#ireg 11 cls_cnt 2 2006.224.07:44:39.89#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.224.07:44:39.95#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.224.07:44:39.95#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.224.07:44:39.95#ibcon#enter wrdev, iclass 15, count 2 2006.224.07:44:39.95#ibcon#first serial, iclass 15, count 2 2006.224.07:44:39.95#ibcon#enter sib2, iclass 15, count 2 2006.224.07:44:39.95#ibcon#flushed, iclass 15, count 2 2006.224.07:44:39.95#ibcon#about to write, iclass 15, count 2 2006.224.07:44:39.95#ibcon#wrote, iclass 15, count 2 2006.224.07:44:39.95#ibcon#about to read 3, iclass 15, count 2 2006.224.07:44:39.97#ibcon#read 3, iclass 15, count 2 2006.224.07:44:39.97#ibcon#about to read 4, iclass 15, count 2 2006.224.07:44:39.97#ibcon#read 4, iclass 15, count 2 2006.224.07:44:39.97#ibcon#about to read 5, iclass 15, count 2 2006.224.07:44:39.97#ibcon#read 5, iclass 15, count 2 2006.224.07:44:39.97#ibcon#about to read 6, iclass 15, count 2 2006.224.07:44:39.97#ibcon#read 6, iclass 15, count 2 2006.224.07:44:39.97#ibcon#end of sib2, iclass 15, count 2 2006.224.07:44:39.97#ibcon#*mode == 0, iclass 15, count 2 2006.224.07:44:39.97#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.224.07:44:39.97#ibcon#[27=AT02-04\r\n] 2006.224.07:44:39.97#ibcon#*before write, iclass 15, count 2 2006.224.07:44:39.97#ibcon#enter sib2, iclass 15, count 2 2006.224.07:44:39.97#ibcon#flushed, iclass 15, count 2 2006.224.07:44:39.97#ibcon#about to write, iclass 15, count 2 2006.224.07:44:39.97#ibcon#wrote, iclass 15, count 2 2006.224.07:44:39.97#ibcon#about to read 3, iclass 15, count 2 2006.224.07:44:40.00#ibcon#read 3, iclass 15, count 2 2006.224.07:44:40.00#ibcon#about to read 4, iclass 15, count 2 2006.224.07:44:40.00#ibcon#read 4, iclass 15, count 2 2006.224.07:44:40.00#ibcon#about to read 5, iclass 15, count 2 2006.224.07:44:40.00#ibcon#read 5, iclass 15, count 2 2006.224.07:44:40.00#ibcon#about to read 6, iclass 15, count 2 2006.224.07:44:40.00#ibcon#read 6, iclass 15, count 2 2006.224.07:44:40.00#ibcon#end of sib2, iclass 15, count 2 2006.224.07:44:40.00#ibcon#*after write, iclass 15, count 2 2006.224.07:44:40.00#ibcon#*before return 0, iclass 15, count 2 2006.224.07:44:40.00#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.224.07:44:40.00#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.224.07:44:40.00#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.224.07:44:40.00#ibcon#ireg 7 cls_cnt 0 2006.224.07:44:40.00#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.224.07:44:40.12#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.224.07:44:40.12#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.224.07:44:40.12#ibcon#enter wrdev, iclass 15, count 0 2006.224.07:44:40.12#ibcon#first serial, iclass 15, count 0 2006.224.07:44:40.12#ibcon#enter sib2, iclass 15, count 0 2006.224.07:44:40.12#ibcon#flushed, iclass 15, count 0 2006.224.07:44:40.12#ibcon#about to write, iclass 15, count 0 2006.224.07:44:40.12#ibcon#wrote, iclass 15, count 0 2006.224.07:44:40.12#ibcon#about to read 3, iclass 15, count 0 2006.224.07:44:40.14#ibcon#read 3, iclass 15, count 0 2006.224.07:44:40.14#ibcon#about to read 4, iclass 15, count 0 2006.224.07:44:40.14#ibcon#read 4, iclass 15, count 0 2006.224.07:44:40.14#ibcon#about to read 5, iclass 15, count 0 2006.224.07:44:40.14#ibcon#read 5, iclass 15, count 0 2006.224.07:44:40.14#ibcon#about to read 6, iclass 15, count 0 2006.224.07:44:40.14#ibcon#read 6, iclass 15, count 0 2006.224.07:44:40.14#ibcon#end of sib2, iclass 15, count 0 2006.224.07:44:40.14#ibcon#*mode == 0, iclass 15, count 0 2006.224.07:44:40.14#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.224.07:44:40.14#ibcon#[27=USB\r\n] 2006.224.07:44:40.14#ibcon#*before write, iclass 15, count 0 2006.224.07:44:40.14#ibcon#enter sib2, iclass 15, count 0 2006.224.07:44:40.14#ibcon#flushed, iclass 15, count 0 2006.224.07:44:40.14#ibcon#about to write, iclass 15, count 0 2006.224.07:44:40.14#ibcon#wrote, iclass 15, count 0 2006.224.07:44:40.14#ibcon#about to read 3, iclass 15, count 0 2006.224.07:44:40.17#ibcon#read 3, iclass 15, count 0 2006.224.07:44:40.17#ibcon#about to read 4, iclass 15, count 0 2006.224.07:44:40.17#ibcon#read 4, iclass 15, count 0 2006.224.07:44:40.17#ibcon#about to read 5, iclass 15, count 0 2006.224.07:44:40.17#ibcon#read 5, iclass 15, count 0 2006.224.07:44:40.17#ibcon#about to read 6, iclass 15, count 0 2006.224.07:44:40.17#ibcon#read 6, iclass 15, count 0 2006.224.07:44:40.17#ibcon#end of sib2, iclass 15, count 0 2006.224.07:44:40.17#ibcon#*after write, iclass 15, count 0 2006.224.07:44:40.17#ibcon#*before return 0, iclass 15, count 0 2006.224.07:44:40.17#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.224.07:44:40.17#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.224.07:44:40.17#ibcon#about to clear, iclass 15 cls_cnt 0 2006.224.07:44:40.17#ibcon#cleared, iclass 15 cls_cnt 0 2006.224.07:44:40.17$vc4f8/vblo=3,656.99 2006.224.07:44:40.17#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.224.07:44:40.17#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.224.07:44:40.17#ibcon#ireg 17 cls_cnt 0 2006.224.07:44:40.17#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.224.07:44:40.17#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.224.07:44:40.17#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.224.07:44:40.17#ibcon#enter wrdev, iclass 17, count 0 2006.224.07:44:40.17#ibcon#first serial, iclass 17, count 0 2006.224.07:44:40.17#ibcon#enter sib2, iclass 17, count 0 2006.224.07:44:40.17#ibcon#flushed, iclass 17, count 0 2006.224.07:44:40.17#ibcon#about to write, iclass 17, count 0 2006.224.07:44:40.17#ibcon#wrote, iclass 17, count 0 2006.224.07:44:40.17#ibcon#about to read 3, iclass 17, count 0 2006.224.07:44:40.19#ibcon#read 3, iclass 17, count 0 2006.224.07:44:40.19#ibcon#about to read 4, iclass 17, count 0 2006.224.07:44:40.19#ibcon#read 4, iclass 17, count 0 2006.224.07:44:40.19#ibcon#about to read 5, iclass 17, count 0 2006.224.07:44:40.19#ibcon#read 5, iclass 17, count 0 2006.224.07:44:40.19#ibcon#about to read 6, iclass 17, count 0 2006.224.07:44:40.19#ibcon#read 6, iclass 17, count 0 2006.224.07:44:40.19#ibcon#end of sib2, iclass 17, count 0 2006.224.07:44:40.19#ibcon#*mode == 0, iclass 17, count 0 2006.224.07:44:40.19#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.224.07:44:40.19#ibcon#[28=FRQ=03,656.99\r\n] 2006.224.07:44:40.19#ibcon#*before write, iclass 17, count 0 2006.224.07:44:40.19#ibcon#enter sib2, iclass 17, count 0 2006.224.07:44:40.19#ibcon#flushed, iclass 17, count 0 2006.224.07:44:40.19#ibcon#about to write, iclass 17, count 0 2006.224.07:44:40.19#ibcon#wrote, iclass 17, count 0 2006.224.07:44:40.19#ibcon#about to read 3, iclass 17, count 0 2006.224.07:44:40.23#ibcon#read 3, iclass 17, count 0 2006.224.07:44:40.23#ibcon#about to read 4, iclass 17, count 0 2006.224.07:44:40.23#ibcon#read 4, iclass 17, count 0 2006.224.07:44:40.23#ibcon#about to read 5, iclass 17, count 0 2006.224.07:44:40.23#ibcon#read 5, iclass 17, count 0 2006.224.07:44:40.23#ibcon#about to read 6, iclass 17, count 0 2006.224.07:44:40.23#ibcon#read 6, iclass 17, count 0 2006.224.07:44:40.23#ibcon#end of sib2, iclass 17, count 0 2006.224.07:44:40.23#ibcon#*after write, iclass 17, count 0 2006.224.07:44:40.23#ibcon#*before return 0, iclass 17, count 0 2006.224.07:44:40.23#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.224.07:44:40.23#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.224.07:44:40.23#ibcon#about to clear, iclass 17 cls_cnt 0 2006.224.07:44:40.23#ibcon#cleared, iclass 17 cls_cnt 0 2006.224.07:44:40.23$vc4f8/vb=3,4 2006.224.07:44:40.23#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.224.07:44:40.23#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.224.07:44:40.23#ibcon#ireg 11 cls_cnt 2 2006.224.07:44:40.23#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.224.07:44:40.30#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.224.07:44:40.30#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.224.07:44:40.30#ibcon#enter wrdev, iclass 19, count 2 2006.224.07:44:40.30#ibcon#first serial, iclass 19, count 2 2006.224.07:44:40.30#ibcon#enter sib2, iclass 19, count 2 2006.224.07:44:40.30#ibcon#flushed, iclass 19, count 2 2006.224.07:44:40.30#ibcon#about to write, iclass 19, count 2 2006.224.07:44:40.30#ibcon#wrote, iclass 19, count 2 2006.224.07:44:40.30#ibcon#about to read 3, iclass 19, count 2 2006.224.07:44:40.31#ibcon#read 3, iclass 19, count 2 2006.224.07:44:40.31#ibcon#about to read 4, iclass 19, count 2 2006.224.07:44:40.31#ibcon#read 4, iclass 19, count 2 2006.224.07:44:40.31#ibcon#about to read 5, iclass 19, count 2 2006.224.07:44:40.31#ibcon#read 5, iclass 19, count 2 2006.224.07:44:40.31#ibcon#about to read 6, iclass 19, count 2 2006.224.07:44:40.31#ibcon#read 6, iclass 19, count 2 2006.224.07:44:40.31#ibcon#end of sib2, iclass 19, count 2 2006.224.07:44:40.31#ibcon#*mode == 0, iclass 19, count 2 2006.224.07:44:40.31#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.224.07:44:40.31#ibcon#[27=AT03-04\r\n] 2006.224.07:44:40.31#ibcon#*before write, iclass 19, count 2 2006.224.07:44:40.31#ibcon#enter sib2, iclass 19, count 2 2006.224.07:44:40.31#ibcon#flushed, iclass 19, count 2 2006.224.07:44:40.31#ibcon#about to write, iclass 19, count 2 2006.224.07:44:40.31#ibcon#wrote, iclass 19, count 2 2006.224.07:44:40.31#ibcon#about to read 3, iclass 19, count 2 2006.224.07:44:40.34#ibcon#read 3, iclass 19, count 2 2006.224.07:44:40.34#ibcon#about to read 4, iclass 19, count 2 2006.224.07:44:40.34#ibcon#read 4, iclass 19, count 2 2006.224.07:44:40.34#ibcon#about to read 5, iclass 19, count 2 2006.224.07:44:40.34#ibcon#read 5, iclass 19, count 2 2006.224.07:44:40.34#ibcon#about to read 6, iclass 19, count 2 2006.224.07:44:40.34#ibcon#read 6, iclass 19, count 2 2006.224.07:44:40.34#ibcon#end of sib2, iclass 19, count 2 2006.224.07:44:40.34#ibcon#*after write, iclass 19, count 2 2006.224.07:44:40.34#ibcon#*before return 0, iclass 19, count 2 2006.224.07:44:40.34#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.224.07:44:40.34#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.224.07:44:40.34#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.224.07:44:40.34#ibcon#ireg 7 cls_cnt 0 2006.224.07:44:40.34#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.224.07:44:40.46#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.224.07:44:40.46#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.224.07:44:40.46#ibcon#enter wrdev, iclass 19, count 0 2006.224.07:44:40.46#ibcon#first serial, iclass 19, count 0 2006.224.07:44:40.46#ibcon#enter sib2, iclass 19, count 0 2006.224.07:44:40.46#ibcon#flushed, iclass 19, count 0 2006.224.07:44:40.46#ibcon#about to write, iclass 19, count 0 2006.224.07:44:40.46#ibcon#wrote, iclass 19, count 0 2006.224.07:44:40.46#ibcon#about to read 3, iclass 19, count 0 2006.224.07:44:40.48#ibcon#read 3, iclass 19, count 0 2006.224.07:44:40.48#ibcon#about to read 4, iclass 19, count 0 2006.224.07:44:40.48#ibcon#read 4, iclass 19, count 0 2006.224.07:44:40.48#ibcon#about to read 5, iclass 19, count 0 2006.224.07:44:40.48#ibcon#read 5, iclass 19, count 0 2006.224.07:44:40.48#ibcon#about to read 6, iclass 19, count 0 2006.224.07:44:40.48#ibcon#read 6, iclass 19, count 0 2006.224.07:44:40.48#ibcon#end of sib2, iclass 19, count 0 2006.224.07:44:40.48#ibcon#*mode == 0, iclass 19, count 0 2006.224.07:44:40.48#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.224.07:44:40.48#ibcon#[27=USB\r\n] 2006.224.07:44:40.48#ibcon#*before write, iclass 19, count 0 2006.224.07:44:40.48#ibcon#enter sib2, iclass 19, count 0 2006.224.07:44:40.48#ibcon#flushed, iclass 19, count 0 2006.224.07:44:40.48#ibcon#about to write, iclass 19, count 0 2006.224.07:44:40.48#ibcon#wrote, iclass 19, count 0 2006.224.07:44:40.48#ibcon#about to read 3, iclass 19, count 0 2006.224.07:44:40.51#ibcon#read 3, iclass 19, count 0 2006.224.07:44:40.51#ibcon#about to read 4, iclass 19, count 0 2006.224.07:44:40.51#ibcon#read 4, iclass 19, count 0 2006.224.07:44:40.51#ibcon#about to read 5, iclass 19, count 0 2006.224.07:44:40.51#ibcon#read 5, iclass 19, count 0 2006.224.07:44:40.51#ibcon#about to read 6, iclass 19, count 0 2006.224.07:44:40.51#ibcon#read 6, iclass 19, count 0 2006.224.07:44:40.51#ibcon#end of sib2, iclass 19, count 0 2006.224.07:44:40.51#ibcon#*after write, iclass 19, count 0 2006.224.07:44:40.51#ibcon#*before return 0, iclass 19, count 0 2006.224.07:44:40.51#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.224.07:44:40.51#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.224.07:44:40.51#ibcon#about to clear, iclass 19 cls_cnt 0 2006.224.07:44:40.51#ibcon#cleared, iclass 19 cls_cnt 0 2006.224.07:44:40.51$vc4f8/vblo=4,712.99 2006.224.07:44:40.51#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.224.07:44:40.51#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.224.07:44:40.51#ibcon#ireg 17 cls_cnt 0 2006.224.07:44:40.51#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.224.07:44:40.51#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.224.07:44:40.51#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.224.07:44:40.51#ibcon#enter wrdev, iclass 21, count 0 2006.224.07:44:40.51#ibcon#first serial, iclass 21, count 0 2006.224.07:44:40.51#ibcon#enter sib2, iclass 21, count 0 2006.224.07:44:40.51#ibcon#flushed, iclass 21, count 0 2006.224.07:44:40.51#ibcon#about to write, iclass 21, count 0 2006.224.07:44:40.51#ibcon#wrote, iclass 21, count 0 2006.224.07:44:40.51#ibcon#about to read 3, iclass 21, count 0 2006.224.07:44:40.53#ibcon#read 3, iclass 21, count 0 2006.224.07:44:40.53#ibcon#about to read 4, iclass 21, count 0 2006.224.07:44:40.53#ibcon#read 4, iclass 21, count 0 2006.224.07:44:40.53#ibcon#about to read 5, iclass 21, count 0 2006.224.07:44:40.53#ibcon#read 5, iclass 21, count 0 2006.224.07:44:40.53#ibcon#about to read 6, iclass 21, count 0 2006.224.07:44:40.53#ibcon#read 6, iclass 21, count 0 2006.224.07:44:40.53#ibcon#end of sib2, iclass 21, count 0 2006.224.07:44:40.53#ibcon#*mode == 0, iclass 21, count 0 2006.224.07:44:40.53#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.224.07:44:40.53#ibcon#[28=FRQ=04,712.99\r\n] 2006.224.07:44:40.53#ibcon#*before write, iclass 21, count 0 2006.224.07:44:40.53#ibcon#enter sib2, iclass 21, count 0 2006.224.07:44:40.53#ibcon#flushed, iclass 21, count 0 2006.224.07:44:40.53#ibcon#about to write, iclass 21, count 0 2006.224.07:44:40.53#ibcon#wrote, iclass 21, count 0 2006.224.07:44:40.53#ibcon#about to read 3, iclass 21, count 0 2006.224.07:44:40.57#ibcon#read 3, iclass 21, count 0 2006.224.07:44:40.57#ibcon#about to read 4, iclass 21, count 0 2006.224.07:44:40.57#ibcon#read 4, iclass 21, count 0 2006.224.07:44:40.57#ibcon#about to read 5, iclass 21, count 0 2006.224.07:44:40.57#ibcon#read 5, iclass 21, count 0 2006.224.07:44:40.57#ibcon#about to read 6, iclass 21, count 0 2006.224.07:44:40.57#ibcon#read 6, iclass 21, count 0 2006.224.07:44:40.57#ibcon#end of sib2, iclass 21, count 0 2006.224.07:44:40.57#ibcon#*after write, iclass 21, count 0 2006.224.07:44:40.57#ibcon#*before return 0, iclass 21, count 0 2006.224.07:44:40.57#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.224.07:44:40.57#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.224.07:44:40.57#ibcon#about to clear, iclass 21 cls_cnt 0 2006.224.07:44:40.57#ibcon#cleared, iclass 21 cls_cnt 0 2006.224.07:44:40.57$vc4f8/vb=4,4 2006.224.07:44:40.57#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.224.07:44:40.57#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.224.07:44:40.57#ibcon#ireg 11 cls_cnt 2 2006.224.07:44:40.57#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.224.07:44:40.63#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.224.07:44:40.63#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.224.07:44:40.63#ibcon#enter wrdev, iclass 23, count 2 2006.224.07:44:40.63#ibcon#first serial, iclass 23, count 2 2006.224.07:44:40.63#ibcon#enter sib2, iclass 23, count 2 2006.224.07:44:40.63#ibcon#flushed, iclass 23, count 2 2006.224.07:44:40.63#ibcon#about to write, iclass 23, count 2 2006.224.07:44:40.63#ibcon#wrote, iclass 23, count 2 2006.224.07:44:40.63#ibcon#about to read 3, iclass 23, count 2 2006.224.07:44:40.65#ibcon#read 3, iclass 23, count 2 2006.224.07:44:40.65#ibcon#about to read 4, iclass 23, count 2 2006.224.07:44:40.65#ibcon#read 4, iclass 23, count 2 2006.224.07:44:40.65#ibcon#about to read 5, iclass 23, count 2 2006.224.07:44:40.65#ibcon#read 5, iclass 23, count 2 2006.224.07:44:40.65#ibcon#about to read 6, iclass 23, count 2 2006.224.07:44:40.65#ibcon#read 6, iclass 23, count 2 2006.224.07:44:40.65#ibcon#end of sib2, iclass 23, count 2 2006.224.07:44:40.65#ibcon#*mode == 0, iclass 23, count 2 2006.224.07:44:40.65#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.224.07:44:40.65#ibcon#[27=AT04-04\r\n] 2006.224.07:44:40.65#ibcon#*before write, iclass 23, count 2 2006.224.07:44:40.65#ibcon#enter sib2, iclass 23, count 2 2006.224.07:44:40.65#ibcon#flushed, iclass 23, count 2 2006.224.07:44:40.65#ibcon#about to write, iclass 23, count 2 2006.224.07:44:40.65#ibcon#wrote, iclass 23, count 2 2006.224.07:44:40.65#ibcon#about to read 3, iclass 23, count 2 2006.224.07:44:40.68#ibcon#read 3, iclass 23, count 2 2006.224.07:44:40.68#ibcon#about to read 4, iclass 23, count 2 2006.224.07:44:40.68#ibcon#read 4, iclass 23, count 2 2006.224.07:44:40.68#ibcon#about to read 5, iclass 23, count 2 2006.224.07:44:40.68#ibcon#read 5, iclass 23, count 2 2006.224.07:44:40.68#ibcon#about to read 6, iclass 23, count 2 2006.224.07:44:40.68#ibcon#read 6, iclass 23, count 2 2006.224.07:44:40.68#ibcon#end of sib2, iclass 23, count 2 2006.224.07:44:40.68#ibcon#*after write, iclass 23, count 2 2006.224.07:44:40.68#ibcon#*before return 0, iclass 23, count 2 2006.224.07:44:40.68#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.224.07:44:40.68#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.224.07:44:40.68#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.224.07:44:40.68#ibcon#ireg 7 cls_cnt 0 2006.224.07:44:40.68#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.224.07:44:40.80#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.224.07:44:40.80#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.224.07:44:40.80#ibcon#enter wrdev, iclass 23, count 0 2006.224.07:44:40.80#ibcon#first serial, iclass 23, count 0 2006.224.07:44:40.80#ibcon#enter sib2, iclass 23, count 0 2006.224.07:44:40.80#ibcon#flushed, iclass 23, count 0 2006.224.07:44:40.80#ibcon#about to write, iclass 23, count 0 2006.224.07:44:40.80#ibcon#wrote, iclass 23, count 0 2006.224.07:44:40.80#ibcon#about to read 3, iclass 23, count 0 2006.224.07:44:40.82#ibcon#read 3, iclass 23, count 0 2006.224.07:44:40.82#ibcon#about to read 4, iclass 23, count 0 2006.224.07:44:40.82#ibcon#read 4, iclass 23, count 0 2006.224.07:44:40.82#ibcon#about to read 5, iclass 23, count 0 2006.224.07:44:40.82#ibcon#read 5, iclass 23, count 0 2006.224.07:44:40.82#ibcon#about to read 6, iclass 23, count 0 2006.224.07:44:40.82#ibcon#read 6, iclass 23, count 0 2006.224.07:44:40.82#ibcon#end of sib2, iclass 23, count 0 2006.224.07:44:40.82#ibcon#*mode == 0, iclass 23, count 0 2006.224.07:44:40.82#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.224.07:44:40.82#ibcon#[27=USB\r\n] 2006.224.07:44:40.82#ibcon#*before write, iclass 23, count 0 2006.224.07:44:40.82#ibcon#enter sib2, iclass 23, count 0 2006.224.07:44:40.82#ibcon#flushed, iclass 23, count 0 2006.224.07:44:40.82#ibcon#about to write, iclass 23, count 0 2006.224.07:44:40.82#ibcon#wrote, iclass 23, count 0 2006.224.07:44:40.82#ibcon#about to read 3, iclass 23, count 0 2006.224.07:44:40.85#ibcon#read 3, iclass 23, count 0 2006.224.07:44:40.85#ibcon#about to read 4, iclass 23, count 0 2006.224.07:44:40.85#ibcon#read 4, iclass 23, count 0 2006.224.07:44:40.85#ibcon#about to read 5, iclass 23, count 0 2006.224.07:44:40.85#ibcon#read 5, iclass 23, count 0 2006.224.07:44:40.85#ibcon#about to read 6, iclass 23, count 0 2006.224.07:44:40.85#ibcon#read 6, iclass 23, count 0 2006.224.07:44:40.85#ibcon#end of sib2, iclass 23, count 0 2006.224.07:44:40.85#ibcon#*after write, iclass 23, count 0 2006.224.07:44:40.85#ibcon#*before return 0, iclass 23, count 0 2006.224.07:44:40.85#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.224.07:44:40.85#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.224.07:44:40.85#ibcon#about to clear, iclass 23 cls_cnt 0 2006.224.07:44:40.85#ibcon#cleared, iclass 23 cls_cnt 0 2006.224.07:44:40.85$vc4f8/vblo=5,744.99 2006.224.07:44:40.85#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.224.07:44:40.85#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.224.07:44:40.85#ibcon#ireg 17 cls_cnt 0 2006.224.07:44:40.85#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.224.07:44:40.85#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.224.07:44:40.85#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.224.07:44:40.85#ibcon#enter wrdev, iclass 25, count 0 2006.224.07:44:40.85#ibcon#first serial, iclass 25, count 0 2006.224.07:44:40.85#ibcon#enter sib2, iclass 25, count 0 2006.224.07:44:40.85#ibcon#flushed, iclass 25, count 0 2006.224.07:44:40.85#ibcon#about to write, iclass 25, count 0 2006.224.07:44:40.85#ibcon#wrote, iclass 25, count 0 2006.224.07:44:40.85#ibcon#about to read 3, iclass 25, count 0 2006.224.07:44:40.87#ibcon#read 3, iclass 25, count 0 2006.224.07:44:40.87#ibcon#about to read 4, iclass 25, count 0 2006.224.07:44:40.87#ibcon#read 4, iclass 25, count 0 2006.224.07:44:40.87#ibcon#about to read 5, iclass 25, count 0 2006.224.07:44:40.87#ibcon#read 5, iclass 25, count 0 2006.224.07:44:40.87#ibcon#about to read 6, iclass 25, count 0 2006.224.07:44:40.87#ibcon#read 6, iclass 25, count 0 2006.224.07:44:40.87#ibcon#end of sib2, iclass 25, count 0 2006.224.07:44:40.87#ibcon#*mode == 0, iclass 25, count 0 2006.224.07:44:40.87#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.224.07:44:40.87#ibcon#[28=FRQ=05,744.99\r\n] 2006.224.07:44:40.87#ibcon#*before write, iclass 25, count 0 2006.224.07:44:40.87#ibcon#enter sib2, iclass 25, count 0 2006.224.07:44:40.87#ibcon#flushed, iclass 25, count 0 2006.224.07:44:40.87#ibcon#about to write, iclass 25, count 0 2006.224.07:44:40.87#ibcon#wrote, iclass 25, count 0 2006.224.07:44:40.87#ibcon#about to read 3, iclass 25, count 0 2006.224.07:44:40.91#ibcon#read 3, iclass 25, count 0 2006.224.07:44:40.91#ibcon#about to read 4, iclass 25, count 0 2006.224.07:44:40.91#ibcon#read 4, iclass 25, count 0 2006.224.07:44:40.91#ibcon#about to read 5, iclass 25, count 0 2006.224.07:44:40.91#ibcon#read 5, iclass 25, count 0 2006.224.07:44:40.91#ibcon#about to read 6, iclass 25, count 0 2006.224.07:44:40.91#ibcon#read 6, iclass 25, count 0 2006.224.07:44:40.91#ibcon#end of sib2, iclass 25, count 0 2006.224.07:44:40.91#ibcon#*after write, iclass 25, count 0 2006.224.07:44:40.91#ibcon#*before return 0, iclass 25, count 0 2006.224.07:44:40.91#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.224.07:44:40.91#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.224.07:44:40.91#ibcon#about to clear, iclass 25 cls_cnt 0 2006.224.07:44:40.91#ibcon#cleared, iclass 25 cls_cnt 0 2006.224.07:44:40.91$vc4f8/vb=5,4 2006.224.07:44:40.91#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.224.07:44:40.91#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.224.07:44:40.91#ibcon#ireg 11 cls_cnt 2 2006.224.07:44:40.91#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.224.07:44:40.97#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.224.07:44:40.97#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.224.07:44:40.97#ibcon#enter wrdev, iclass 27, count 2 2006.224.07:44:40.97#ibcon#first serial, iclass 27, count 2 2006.224.07:44:40.97#ibcon#enter sib2, iclass 27, count 2 2006.224.07:44:40.97#ibcon#flushed, iclass 27, count 2 2006.224.07:44:40.97#ibcon#about to write, iclass 27, count 2 2006.224.07:44:40.97#ibcon#wrote, iclass 27, count 2 2006.224.07:44:40.97#ibcon#about to read 3, iclass 27, count 2 2006.224.07:44:40.99#ibcon#read 3, iclass 27, count 2 2006.224.07:44:40.99#ibcon#about to read 4, iclass 27, count 2 2006.224.07:44:40.99#ibcon#read 4, iclass 27, count 2 2006.224.07:44:40.99#ibcon#about to read 5, iclass 27, count 2 2006.224.07:44:40.99#ibcon#read 5, iclass 27, count 2 2006.224.07:44:40.99#ibcon#about to read 6, iclass 27, count 2 2006.224.07:44:40.99#ibcon#read 6, iclass 27, count 2 2006.224.07:44:40.99#ibcon#end of sib2, iclass 27, count 2 2006.224.07:44:40.99#ibcon#*mode == 0, iclass 27, count 2 2006.224.07:44:40.99#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.224.07:44:40.99#ibcon#[27=AT05-04\r\n] 2006.224.07:44:40.99#ibcon#*before write, iclass 27, count 2 2006.224.07:44:40.99#ibcon#enter sib2, iclass 27, count 2 2006.224.07:44:40.99#ibcon#flushed, iclass 27, count 2 2006.224.07:44:40.99#ibcon#about to write, iclass 27, count 2 2006.224.07:44:40.99#ibcon#wrote, iclass 27, count 2 2006.224.07:44:40.99#ibcon#about to read 3, iclass 27, count 2 2006.224.07:44:41.02#ibcon#read 3, iclass 27, count 2 2006.224.07:44:41.02#ibcon#about to read 4, iclass 27, count 2 2006.224.07:44:41.02#ibcon#read 4, iclass 27, count 2 2006.224.07:44:41.02#ibcon#about to read 5, iclass 27, count 2 2006.224.07:44:41.02#ibcon#read 5, iclass 27, count 2 2006.224.07:44:41.02#ibcon#about to read 6, iclass 27, count 2 2006.224.07:44:41.02#ibcon#read 6, iclass 27, count 2 2006.224.07:44:41.02#ibcon#end of sib2, iclass 27, count 2 2006.224.07:44:41.02#ibcon#*after write, iclass 27, count 2 2006.224.07:44:41.02#ibcon#*before return 0, iclass 27, count 2 2006.224.07:44:41.02#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.224.07:44:41.02#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.224.07:44:41.02#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.224.07:44:41.02#ibcon#ireg 7 cls_cnt 0 2006.224.07:44:41.02#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.224.07:44:41.14#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.224.07:44:41.14#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.224.07:44:41.14#ibcon#enter wrdev, iclass 27, count 0 2006.224.07:44:41.14#ibcon#first serial, iclass 27, count 0 2006.224.07:44:41.14#ibcon#enter sib2, iclass 27, count 0 2006.224.07:44:41.14#ibcon#flushed, iclass 27, count 0 2006.224.07:44:41.14#ibcon#about to write, iclass 27, count 0 2006.224.07:44:41.14#ibcon#wrote, iclass 27, count 0 2006.224.07:44:41.14#ibcon#about to read 3, iclass 27, count 0 2006.224.07:44:41.16#ibcon#read 3, iclass 27, count 0 2006.224.07:44:41.16#ibcon#about to read 4, iclass 27, count 0 2006.224.07:44:41.16#ibcon#read 4, iclass 27, count 0 2006.224.07:44:41.16#ibcon#about to read 5, iclass 27, count 0 2006.224.07:44:41.16#ibcon#read 5, iclass 27, count 0 2006.224.07:44:41.16#ibcon#about to read 6, iclass 27, count 0 2006.224.07:44:41.16#ibcon#read 6, iclass 27, count 0 2006.224.07:44:41.16#ibcon#end of sib2, iclass 27, count 0 2006.224.07:44:41.16#ibcon#*mode == 0, iclass 27, count 0 2006.224.07:44:41.16#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.224.07:44:41.16#ibcon#[27=USB\r\n] 2006.224.07:44:41.16#ibcon#*before write, iclass 27, count 0 2006.224.07:44:41.16#ibcon#enter sib2, iclass 27, count 0 2006.224.07:44:41.16#ibcon#flushed, iclass 27, count 0 2006.224.07:44:41.16#ibcon#about to write, iclass 27, count 0 2006.224.07:44:41.16#ibcon#wrote, iclass 27, count 0 2006.224.07:44:41.16#ibcon#about to read 3, iclass 27, count 0 2006.224.07:44:41.19#ibcon#read 3, iclass 27, count 0 2006.224.07:44:41.19#ibcon#about to read 4, iclass 27, count 0 2006.224.07:44:41.19#ibcon#read 4, iclass 27, count 0 2006.224.07:44:41.19#ibcon#about to read 5, iclass 27, count 0 2006.224.07:44:41.19#ibcon#read 5, iclass 27, count 0 2006.224.07:44:41.19#ibcon#about to read 6, iclass 27, count 0 2006.224.07:44:41.19#ibcon#read 6, iclass 27, count 0 2006.224.07:44:41.19#ibcon#end of sib2, iclass 27, count 0 2006.224.07:44:41.19#ibcon#*after write, iclass 27, count 0 2006.224.07:44:41.19#ibcon#*before return 0, iclass 27, count 0 2006.224.07:44:41.19#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.224.07:44:41.19#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.224.07:44:41.19#ibcon#about to clear, iclass 27 cls_cnt 0 2006.224.07:44:41.19#ibcon#cleared, iclass 27 cls_cnt 0 2006.224.07:44:41.19$vc4f8/vblo=6,752.99 2006.224.07:44:41.19#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.224.07:44:41.19#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.224.07:44:41.19#ibcon#ireg 17 cls_cnt 0 2006.224.07:44:41.19#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.224.07:44:41.19#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.224.07:44:41.19#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.224.07:44:41.19#ibcon#enter wrdev, iclass 29, count 0 2006.224.07:44:41.19#ibcon#first serial, iclass 29, count 0 2006.224.07:44:41.19#ibcon#enter sib2, iclass 29, count 0 2006.224.07:44:41.19#ibcon#flushed, iclass 29, count 0 2006.224.07:44:41.19#ibcon#about to write, iclass 29, count 0 2006.224.07:44:41.19#ibcon#wrote, iclass 29, count 0 2006.224.07:44:41.19#ibcon#about to read 3, iclass 29, count 0 2006.224.07:44:41.22#ibcon#read 3, iclass 29, count 0 2006.224.07:44:41.22#ibcon#about to read 4, iclass 29, count 0 2006.224.07:44:41.22#ibcon#read 4, iclass 29, count 0 2006.224.07:44:41.22#ibcon#about to read 5, iclass 29, count 0 2006.224.07:44:41.22#ibcon#read 5, iclass 29, count 0 2006.224.07:44:41.22#ibcon#about to read 6, iclass 29, count 0 2006.224.07:44:41.22#ibcon#read 6, iclass 29, count 0 2006.224.07:44:41.22#ibcon#end of sib2, iclass 29, count 0 2006.224.07:44:41.22#ibcon#*mode == 0, iclass 29, count 0 2006.224.07:44:41.22#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.224.07:44:41.22#ibcon#[28=FRQ=06,752.99\r\n] 2006.224.07:44:41.22#ibcon#*before write, iclass 29, count 0 2006.224.07:44:41.22#ibcon#enter sib2, iclass 29, count 0 2006.224.07:44:41.22#ibcon#flushed, iclass 29, count 0 2006.224.07:44:41.22#ibcon#about to write, iclass 29, count 0 2006.224.07:44:41.22#ibcon#wrote, iclass 29, count 0 2006.224.07:44:41.22#ibcon#about to read 3, iclass 29, count 0 2006.224.07:44:41.26#ibcon#read 3, iclass 29, count 0 2006.224.07:44:41.26#ibcon#about to read 4, iclass 29, count 0 2006.224.07:44:41.26#ibcon#read 4, iclass 29, count 0 2006.224.07:44:41.26#ibcon#about to read 5, iclass 29, count 0 2006.224.07:44:41.26#ibcon#read 5, iclass 29, count 0 2006.224.07:44:41.26#ibcon#about to read 6, iclass 29, count 0 2006.224.07:44:41.26#ibcon#read 6, iclass 29, count 0 2006.224.07:44:41.26#ibcon#end of sib2, iclass 29, count 0 2006.224.07:44:41.26#ibcon#*after write, iclass 29, count 0 2006.224.07:44:41.26#ibcon#*before return 0, iclass 29, count 0 2006.224.07:44:41.26#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.224.07:44:41.26#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.224.07:44:41.26#ibcon#about to clear, iclass 29 cls_cnt 0 2006.224.07:44:41.26#ibcon#cleared, iclass 29 cls_cnt 0 2006.224.07:44:41.26$vc4f8/vb=6,4 2006.224.07:44:41.26#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.224.07:44:41.26#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.224.07:44:41.26#ibcon#ireg 11 cls_cnt 2 2006.224.07:44:41.26#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.224.07:44:41.32#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.224.07:44:41.32#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.224.07:44:41.32#ibcon#enter wrdev, iclass 31, count 2 2006.224.07:44:41.32#ibcon#first serial, iclass 31, count 2 2006.224.07:44:41.32#ibcon#enter sib2, iclass 31, count 2 2006.224.07:44:41.32#ibcon#flushed, iclass 31, count 2 2006.224.07:44:41.32#ibcon#about to write, iclass 31, count 2 2006.224.07:44:41.32#ibcon#wrote, iclass 31, count 2 2006.224.07:44:41.32#ibcon#about to read 3, iclass 31, count 2 2006.224.07:44:41.33#ibcon#read 3, iclass 31, count 2 2006.224.07:44:41.33#ibcon#about to read 4, iclass 31, count 2 2006.224.07:44:41.33#ibcon#read 4, iclass 31, count 2 2006.224.07:44:41.33#ibcon#about to read 5, iclass 31, count 2 2006.224.07:44:41.33#ibcon#read 5, iclass 31, count 2 2006.224.07:44:41.33#ibcon#about to read 6, iclass 31, count 2 2006.224.07:44:41.33#ibcon#read 6, iclass 31, count 2 2006.224.07:44:41.33#ibcon#end of sib2, iclass 31, count 2 2006.224.07:44:41.33#ibcon#*mode == 0, iclass 31, count 2 2006.224.07:44:41.33#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.224.07:44:41.33#ibcon#[27=AT06-04\r\n] 2006.224.07:44:41.33#ibcon#*before write, iclass 31, count 2 2006.224.07:44:41.33#ibcon#enter sib2, iclass 31, count 2 2006.224.07:44:41.33#ibcon#flushed, iclass 31, count 2 2006.224.07:44:41.33#ibcon#about to write, iclass 31, count 2 2006.224.07:44:41.33#ibcon#wrote, iclass 31, count 2 2006.224.07:44:41.33#ibcon#about to read 3, iclass 31, count 2 2006.224.07:44:41.36#ibcon#read 3, iclass 31, count 2 2006.224.07:44:41.36#ibcon#about to read 4, iclass 31, count 2 2006.224.07:44:41.36#ibcon#read 4, iclass 31, count 2 2006.224.07:44:41.36#ibcon#about to read 5, iclass 31, count 2 2006.224.07:44:41.36#ibcon#read 5, iclass 31, count 2 2006.224.07:44:41.36#ibcon#about to read 6, iclass 31, count 2 2006.224.07:44:41.36#ibcon#read 6, iclass 31, count 2 2006.224.07:44:41.36#ibcon#end of sib2, iclass 31, count 2 2006.224.07:44:41.36#ibcon#*after write, iclass 31, count 2 2006.224.07:44:41.36#ibcon#*before return 0, iclass 31, count 2 2006.224.07:44:41.36#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.224.07:44:41.36#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.224.07:44:41.36#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.224.07:44:41.36#ibcon#ireg 7 cls_cnt 0 2006.224.07:44:41.36#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.224.07:44:41.48#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.224.07:44:41.48#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.224.07:44:41.48#ibcon#enter wrdev, iclass 31, count 0 2006.224.07:44:41.48#ibcon#first serial, iclass 31, count 0 2006.224.07:44:41.48#ibcon#enter sib2, iclass 31, count 0 2006.224.07:44:41.48#ibcon#flushed, iclass 31, count 0 2006.224.07:44:41.48#ibcon#about to write, iclass 31, count 0 2006.224.07:44:41.48#ibcon#wrote, iclass 31, count 0 2006.224.07:44:41.48#ibcon#about to read 3, iclass 31, count 0 2006.224.07:44:41.50#ibcon#read 3, iclass 31, count 0 2006.224.07:44:41.50#ibcon#about to read 4, iclass 31, count 0 2006.224.07:44:41.50#ibcon#read 4, iclass 31, count 0 2006.224.07:44:41.50#ibcon#about to read 5, iclass 31, count 0 2006.224.07:44:41.50#ibcon#read 5, iclass 31, count 0 2006.224.07:44:41.50#ibcon#about to read 6, iclass 31, count 0 2006.224.07:44:41.50#ibcon#read 6, iclass 31, count 0 2006.224.07:44:41.50#ibcon#end of sib2, iclass 31, count 0 2006.224.07:44:41.50#ibcon#*mode == 0, iclass 31, count 0 2006.224.07:44:41.50#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.224.07:44:41.50#ibcon#[27=USB\r\n] 2006.224.07:44:41.50#ibcon#*before write, iclass 31, count 0 2006.224.07:44:41.50#ibcon#enter sib2, iclass 31, count 0 2006.224.07:44:41.50#ibcon#flushed, iclass 31, count 0 2006.224.07:44:41.50#ibcon#about to write, iclass 31, count 0 2006.224.07:44:41.50#ibcon#wrote, iclass 31, count 0 2006.224.07:44:41.50#ibcon#about to read 3, iclass 31, count 0 2006.224.07:44:41.53#ibcon#read 3, iclass 31, count 0 2006.224.07:44:41.53#ibcon#about to read 4, iclass 31, count 0 2006.224.07:44:41.53#ibcon#read 4, iclass 31, count 0 2006.224.07:44:41.53#ibcon#about to read 5, iclass 31, count 0 2006.224.07:44:41.53#ibcon#read 5, iclass 31, count 0 2006.224.07:44:41.53#ibcon#about to read 6, iclass 31, count 0 2006.224.07:44:41.53#ibcon#read 6, iclass 31, count 0 2006.224.07:44:41.53#ibcon#end of sib2, iclass 31, count 0 2006.224.07:44:41.53#ibcon#*after write, iclass 31, count 0 2006.224.07:44:41.53#ibcon#*before return 0, iclass 31, count 0 2006.224.07:44:41.53#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.224.07:44:41.53#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.224.07:44:41.53#ibcon#about to clear, iclass 31 cls_cnt 0 2006.224.07:44:41.53#ibcon#cleared, iclass 31 cls_cnt 0 2006.224.07:44:41.53$vc4f8/vabw=wide 2006.224.07:44:41.53#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.224.07:44:41.53#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.224.07:44:41.53#ibcon#ireg 8 cls_cnt 0 2006.224.07:44:41.53#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.224.07:44:41.53#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.224.07:44:41.53#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.224.07:44:41.53#ibcon#enter wrdev, iclass 33, count 0 2006.224.07:44:41.53#ibcon#first serial, iclass 33, count 0 2006.224.07:44:41.53#ibcon#enter sib2, iclass 33, count 0 2006.224.07:44:41.53#ibcon#flushed, iclass 33, count 0 2006.224.07:44:41.53#ibcon#about to write, iclass 33, count 0 2006.224.07:44:41.53#ibcon#wrote, iclass 33, count 0 2006.224.07:44:41.53#ibcon#about to read 3, iclass 33, count 0 2006.224.07:44:41.55#ibcon#read 3, iclass 33, count 0 2006.224.07:44:41.55#ibcon#about to read 4, iclass 33, count 0 2006.224.07:44:41.55#ibcon#read 4, iclass 33, count 0 2006.224.07:44:41.55#ibcon#about to read 5, iclass 33, count 0 2006.224.07:44:41.55#ibcon#read 5, iclass 33, count 0 2006.224.07:44:41.55#ibcon#about to read 6, iclass 33, count 0 2006.224.07:44:41.55#ibcon#read 6, iclass 33, count 0 2006.224.07:44:41.55#ibcon#end of sib2, iclass 33, count 0 2006.224.07:44:41.55#ibcon#*mode == 0, iclass 33, count 0 2006.224.07:44:41.55#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.224.07:44:41.55#ibcon#[25=BW32\r\n] 2006.224.07:44:41.55#ibcon#*before write, iclass 33, count 0 2006.224.07:44:41.55#ibcon#enter sib2, iclass 33, count 0 2006.224.07:44:41.55#ibcon#flushed, iclass 33, count 0 2006.224.07:44:41.55#ibcon#about to write, iclass 33, count 0 2006.224.07:44:41.55#ibcon#wrote, iclass 33, count 0 2006.224.07:44:41.55#ibcon#about to read 3, iclass 33, count 0 2006.224.07:44:41.58#ibcon#read 3, iclass 33, count 0 2006.224.07:44:41.58#ibcon#about to read 4, iclass 33, count 0 2006.224.07:44:41.58#ibcon#read 4, iclass 33, count 0 2006.224.07:44:41.58#ibcon#about to read 5, iclass 33, count 0 2006.224.07:44:41.58#ibcon#read 5, iclass 33, count 0 2006.224.07:44:41.58#ibcon#about to read 6, iclass 33, count 0 2006.224.07:44:41.58#ibcon#read 6, iclass 33, count 0 2006.224.07:44:41.58#ibcon#end of sib2, iclass 33, count 0 2006.224.07:44:41.58#ibcon#*after write, iclass 33, count 0 2006.224.07:44:41.58#ibcon#*before return 0, iclass 33, count 0 2006.224.07:44:41.58#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.224.07:44:41.58#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.224.07:44:41.58#ibcon#about to clear, iclass 33 cls_cnt 0 2006.224.07:44:41.58#ibcon#cleared, iclass 33 cls_cnt 0 2006.224.07:44:41.58$vc4f8/vbbw=wide 2006.224.07:44:41.58#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.224.07:44:41.58#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.224.07:44:41.58#ibcon#ireg 8 cls_cnt 0 2006.224.07:44:41.58#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.224.07:44:41.65#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.224.07:44:41.65#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.224.07:44:41.65#ibcon#enter wrdev, iclass 35, count 0 2006.224.07:44:41.65#ibcon#first serial, iclass 35, count 0 2006.224.07:44:41.65#ibcon#enter sib2, iclass 35, count 0 2006.224.07:44:41.65#ibcon#flushed, iclass 35, count 0 2006.224.07:44:41.65#ibcon#about to write, iclass 35, count 0 2006.224.07:44:41.65#ibcon#wrote, iclass 35, count 0 2006.224.07:44:41.65#ibcon#about to read 3, iclass 35, count 0 2006.224.07:44:41.67#ibcon#read 3, iclass 35, count 0 2006.224.07:44:41.67#ibcon#about to read 4, iclass 35, count 0 2006.224.07:44:41.67#ibcon#read 4, iclass 35, count 0 2006.224.07:44:41.67#ibcon#about to read 5, iclass 35, count 0 2006.224.07:44:41.67#ibcon#read 5, iclass 35, count 0 2006.224.07:44:41.67#ibcon#about to read 6, iclass 35, count 0 2006.224.07:44:41.67#ibcon#read 6, iclass 35, count 0 2006.224.07:44:41.67#ibcon#end of sib2, iclass 35, count 0 2006.224.07:44:41.67#ibcon#*mode == 0, iclass 35, count 0 2006.224.07:44:41.67#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.224.07:44:41.67#ibcon#[27=BW32\r\n] 2006.224.07:44:41.67#ibcon#*before write, iclass 35, count 0 2006.224.07:44:41.67#ibcon#enter sib2, iclass 35, count 0 2006.224.07:44:41.67#ibcon#flushed, iclass 35, count 0 2006.224.07:44:41.67#ibcon#about to write, iclass 35, count 0 2006.224.07:44:41.67#ibcon#wrote, iclass 35, count 0 2006.224.07:44:41.67#ibcon#about to read 3, iclass 35, count 0 2006.224.07:44:41.70#ibcon#read 3, iclass 35, count 0 2006.224.07:44:41.70#ibcon#about to read 4, iclass 35, count 0 2006.224.07:44:41.70#ibcon#read 4, iclass 35, count 0 2006.224.07:44:41.70#ibcon#about to read 5, iclass 35, count 0 2006.224.07:44:41.70#ibcon#read 5, iclass 35, count 0 2006.224.07:44:41.70#ibcon#about to read 6, iclass 35, count 0 2006.224.07:44:41.70#ibcon#read 6, iclass 35, count 0 2006.224.07:44:41.70#ibcon#end of sib2, iclass 35, count 0 2006.224.07:44:41.70#ibcon#*after write, iclass 35, count 0 2006.224.07:44:41.70#ibcon#*before return 0, iclass 35, count 0 2006.224.07:44:41.70#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.224.07:44:41.70#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.224.07:44:41.70#ibcon#about to clear, iclass 35 cls_cnt 0 2006.224.07:44:41.70#ibcon#cleared, iclass 35 cls_cnt 0 2006.224.07:44:41.70$4f8m12a/ifd4f 2006.224.07:44:41.70$ifd4f/lo= 2006.224.07:44:41.70$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.224.07:44:41.70$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.224.07:44:41.71$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.224.07:44:41.71$ifd4f/patch= 2006.224.07:44:41.71$ifd4f/patch=lo1,a1,a2,a3,a4 2006.224.07:44:41.71$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.224.07:44:41.71$ifd4f/patch=lo3,a5,a6,a7,a8 2006.224.07:44:41.71$4f8m12a/"form=m,16.000,1:2 2006.224.07:44:41.71$4f8m12a/"tpicd 2006.224.07:44:41.71$4f8m12a/echo=off 2006.224.07:44:41.71$4f8m12a/xlog=off 2006.224.07:44:41.71:!2006.224.07:45:10 2006.224.07:44:56.13#trakl#Source acquired 2006.224.07:44:56.13#flagr#flagr/antenna,acquired 2006.224.07:45:10.01:preob 2006.224.07:45:11.13/onsource/TRACKING 2006.224.07:45:11.13:!2006.224.07:45:20 2006.224.07:45:20.00:data_valid=on 2006.224.07:45:20.00:midob 2006.224.07:45:20.13/onsource/TRACKING 2006.224.07:45:20.14/wx/23.57,1004.3,100 2006.224.07:45:20.18/cable/+6.4343E-03 2006.224.07:45:21.27/va/01,08,usb,yes,45,47 2006.224.07:45:21.27/va/02,07,usb,yes,46,48 2006.224.07:45:21.27/va/03,06,usb,yes,49,49 2006.224.07:45:21.27/va/04,07,usb,yes,48,52 2006.224.07:45:21.27/va/05,07,usb,yes,56,59 2006.224.07:45:21.27/va/06,06,usb,yes,56,56 2006.224.07:45:21.27/va/07,06,usb,yes,57,57 2006.224.07:45:21.27/va/08,07,usb,yes,55,54 2006.224.07:45:21.50/valo/01,532.99,yes,locked 2006.224.07:45:21.50/valo/02,572.99,yes,locked 2006.224.07:45:21.50/valo/03,672.99,yes,locked 2006.224.07:45:21.50/valo/04,832.99,yes,locked 2006.224.07:45:21.50/valo/05,652.99,yes,locked 2006.224.07:45:21.50/valo/06,772.99,yes,locked 2006.224.07:45:21.50/valo/07,832.99,yes,locked 2006.224.07:45:21.50/valo/08,852.99,yes,locked 2006.224.07:45:22.59/vb/01,04,usb,yes,33,31 2006.224.07:45:22.59/vb/02,04,usb,yes,34,36 2006.224.07:45:22.59/vb/03,04,usb,yes,31,35 2006.224.07:45:22.59/vb/04,04,usb,yes,32,32 2006.224.07:45:22.59/vb/05,04,usb,yes,30,34 2006.224.07:45:22.59/vb/06,04,usb,yes,31,34 2006.224.07:45:22.59/vb/07,04,usb,yes,33,33 2006.224.07:45:22.59/vb/08,04,usb,yes,31,34 2006.224.07:45:22.82/vblo/01,632.99,yes,locked 2006.224.07:45:22.82/vblo/02,640.99,yes,locked 2006.224.07:45:22.82/vblo/03,656.99,yes,locked 2006.224.07:45:22.82/vblo/04,712.99,yes,locked 2006.224.07:45:22.82/vblo/05,744.99,yes,locked 2006.224.07:45:22.82/vblo/06,752.99,yes,locked 2006.224.07:45:22.82/vblo/07,734.99,yes,locked 2006.224.07:45:22.82/vblo/08,744.99,yes,locked 2006.224.07:45:22.97/vabw/8 2006.224.07:45:23.12/vbbw/8 2006.224.07:45:23.21/xfe/off,on,14.7 2006.224.07:45:23.59/ifatt/23,28,28,28 2006.224.07:45:24.07/fmout-gps/S +4.28E-07 2006.224.07:45:24.11:!2006.224.07:46:20 2006.224.07:46:20.01:data_valid=off 2006.224.07:46:20.01:postob 2006.224.07:46:20.17/cable/+6.4330E-03 2006.224.07:46:20.17/wx/23.60,1004.3,100 2006.224.07:46:21.06/fmout-gps/S +4.28E-07 2006.224.07:46:21.06:scan_name=224-0747,k06224,60 2006.224.07:46:21.06:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.224.07:46:22.13#flagr#flagr/antenna,new-source 2006.224.07:46:22.13:checkk5 2006.224.07:46:22.52/chk_autoobs//k5ts1/ autoobs is running! 2006.224.07:46:22.89/chk_autoobs//k5ts2/ autoobs is running! 2006.224.07:46:23.27/chk_autoobs//k5ts3/ autoobs is running! 2006.224.07:46:23.63/chk_autoobs//k5ts4/ autoobs is running! 2006.224.07:46:24.00/chk_obsdata//k5ts1/T2240745??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.224.07:46:24.36/chk_obsdata//k5ts2/T2240745??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.224.07:46:24.73/chk_obsdata//k5ts3/T2240745??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.224.07:46:25.09/chk_obsdata//k5ts4/T2240745??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.224.07:46:25.77/k5log//k5ts1_log_newline 2006.224.07:46:26.45/k5log//k5ts2_log_newline 2006.224.07:46:27.14/k5log//k5ts3_log_newline 2006.224.07:46:27.82/k5log//k5ts4_log_newline 2006.224.07:46:27.84/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.224.07:46:27.84:4f8m12a=1 2006.224.07:46:27.84$4f8m12a/echo=on 2006.224.07:46:27.84$4f8m12a/pcalon 2006.224.07:46:27.84$pcalon/"no phase cal control is implemented here 2006.224.07:46:27.84$4f8m12a/"tpicd=stop 2006.224.07:46:27.84$4f8m12a/vc4f8 2006.224.07:46:27.84$vc4f8/valo=1,532.99 2006.224.07:46:27.84#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.224.07:46:27.84#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.224.07:46:27.84#ibcon#ireg 17 cls_cnt 0 2006.224.07:46:27.84#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.224.07:46:27.84#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.224.07:46:27.84#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.224.07:46:27.84#ibcon#enter wrdev, iclass 4, count 0 2006.224.07:46:27.84#ibcon#first serial, iclass 4, count 0 2006.224.07:46:27.84#ibcon#enter sib2, iclass 4, count 0 2006.224.07:46:27.84#ibcon#flushed, iclass 4, count 0 2006.224.07:46:27.84#ibcon#about to write, iclass 4, count 0 2006.224.07:46:27.84#ibcon#wrote, iclass 4, count 0 2006.224.07:46:27.84#ibcon#about to read 3, iclass 4, count 0 2006.224.07:46:27.88#ibcon#read 3, iclass 4, count 0 2006.224.07:46:27.88#ibcon#about to read 4, iclass 4, count 0 2006.224.07:46:27.88#ibcon#read 4, iclass 4, count 0 2006.224.07:46:27.88#ibcon#about to read 5, iclass 4, count 0 2006.224.07:46:27.88#ibcon#read 5, iclass 4, count 0 2006.224.07:46:27.88#ibcon#about to read 6, iclass 4, count 0 2006.224.07:46:27.88#ibcon#read 6, iclass 4, count 0 2006.224.07:46:27.88#ibcon#end of sib2, iclass 4, count 0 2006.224.07:46:27.88#ibcon#*mode == 0, iclass 4, count 0 2006.224.07:46:27.88#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.224.07:46:27.88#ibcon#[26=FRQ=01,532.99\r\n] 2006.224.07:46:27.88#ibcon#*before write, iclass 4, count 0 2006.224.07:46:27.88#ibcon#enter sib2, iclass 4, count 0 2006.224.07:46:27.88#ibcon#flushed, iclass 4, count 0 2006.224.07:46:27.88#ibcon#about to write, iclass 4, count 0 2006.224.07:46:27.88#ibcon#wrote, iclass 4, count 0 2006.224.07:46:27.88#ibcon#about to read 3, iclass 4, count 0 2006.224.07:46:27.93#ibcon#read 3, iclass 4, count 0 2006.224.07:46:27.93#ibcon#about to read 4, iclass 4, count 0 2006.224.07:46:27.93#ibcon#read 4, iclass 4, count 0 2006.224.07:46:27.93#ibcon#about to read 5, iclass 4, count 0 2006.224.07:46:27.93#ibcon#read 5, iclass 4, count 0 2006.224.07:46:27.93#ibcon#about to read 6, iclass 4, count 0 2006.224.07:46:27.93#ibcon#read 6, iclass 4, count 0 2006.224.07:46:27.93#ibcon#end of sib2, iclass 4, count 0 2006.224.07:46:27.93#ibcon#*after write, iclass 4, count 0 2006.224.07:46:27.93#ibcon#*before return 0, iclass 4, count 0 2006.224.07:46:27.93#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.224.07:46:27.93#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.224.07:46:27.93#ibcon#about to clear, iclass 4 cls_cnt 0 2006.224.07:46:27.93#ibcon#cleared, iclass 4 cls_cnt 0 2006.224.07:46:27.93$vc4f8/va=1,8 2006.224.07:46:27.93#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.224.07:46:27.93#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.224.07:46:27.93#ibcon#ireg 11 cls_cnt 2 2006.224.07:46:27.93#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.224.07:46:27.93#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.224.07:46:27.93#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.224.07:46:27.93#ibcon#enter wrdev, iclass 6, count 2 2006.224.07:46:27.93#ibcon#first serial, iclass 6, count 2 2006.224.07:46:27.93#ibcon#enter sib2, iclass 6, count 2 2006.224.07:46:27.93#ibcon#flushed, iclass 6, count 2 2006.224.07:46:27.93#ibcon#about to write, iclass 6, count 2 2006.224.07:46:27.93#ibcon#wrote, iclass 6, count 2 2006.224.07:46:27.93#ibcon#about to read 3, iclass 6, count 2 2006.224.07:46:27.96#ibcon#read 3, iclass 6, count 2 2006.224.07:46:27.96#ibcon#about to read 4, iclass 6, count 2 2006.224.07:46:27.96#ibcon#read 4, iclass 6, count 2 2006.224.07:46:27.96#ibcon#about to read 5, iclass 6, count 2 2006.224.07:46:27.96#ibcon#read 5, iclass 6, count 2 2006.224.07:46:27.96#ibcon#about to read 6, iclass 6, count 2 2006.224.07:46:27.96#ibcon#read 6, iclass 6, count 2 2006.224.07:46:27.96#ibcon#end of sib2, iclass 6, count 2 2006.224.07:46:27.96#ibcon#*mode == 0, iclass 6, count 2 2006.224.07:46:27.96#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.224.07:46:27.96#ibcon#[25=AT01-08\r\n] 2006.224.07:46:27.96#ibcon#*before write, iclass 6, count 2 2006.224.07:46:27.96#ibcon#enter sib2, iclass 6, count 2 2006.224.07:46:27.96#ibcon#flushed, iclass 6, count 2 2006.224.07:46:27.96#ibcon#about to write, iclass 6, count 2 2006.224.07:46:27.96#ibcon#wrote, iclass 6, count 2 2006.224.07:46:27.96#ibcon#about to read 3, iclass 6, count 2 2006.224.07:46:27.98#abcon#<5=/00 0.2 0.8 23.601001004.3\r\n> 2006.224.07:46:27.99#ibcon#read 3, iclass 6, count 2 2006.224.07:46:27.99#ibcon#about to read 4, iclass 6, count 2 2006.224.07:46:27.99#ibcon#read 4, iclass 6, count 2 2006.224.07:46:27.99#ibcon#about to read 5, iclass 6, count 2 2006.224.07:46:27.99#ibcon#read 5, iclass 6, count 2 2006.224.07:46:27.99#ibcon#about to read 6, iclass 6, count 2 2006.224.07:46:27.99#ibcon#read 6, iclass 6, count 2 2006.224.07:46:27.99#ibcon#end of sib2, iclass 6, count 2 2006.224.07:46:27.99#ibcon#*after write, iclass 6, count 2 2006.224.07:46:27.99#ibcon#*before return 0, iclass 6, count 2 2006.224.07:46:27.99#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.224.07:46:27.99#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.224.07:46:27.99#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.224.07:46:27.99#ibcon#ireg 7 cls_cnt 0 2006.224.07:46:27.99#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.224.07:46:28.00#abcon#{5=INTERFACE CLEAR} 2006.224.07:46:28.07#abcon#[5=S1D000X0/0*\r\n] 2006.224.07:46:28.11#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.224.07:46:28.11#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.224.07:46:28.11#ibcon#enter wrdev, iclass 6, count 0 2006.224.07:46:28.11#ibcon#first serial, iclass 6, count 0 2006.224.07:46:28.11#ibcon#enter sib2, iclass 6, count 0 2006.224.07:46:28.11#ibcon#flushed, iclass 6, count 0 2006.224.07:46:28.11#ibcon#about to write, iclass 6, count 0 2006.224.07:46:28.11#ibcon#wrote, iclass 6, count 0 2006.224.07:46:28.11#ibcon#about to read 3, iclass 6, count 0 2006.224.07:46:28.15#ibcon#read 3, iclass 6, count 0 2006.224.07:46:28.15#ibcon#about to read 4, iclass 6, count 0 2006.224.07:46:28.15#ibcon#read 4, iclass 6, count 0 2006.224.07:46:28.15#ibcon#about to read 5, iclass 6, count 0 2006.224.07:46:28.15#ibcon#read 5, iclass 6, count 0 2006.224.07:46:28.15#ibcon#about to read 6, iclass 6, count 0 2006.224.07:46:28.15#ibcon#read 6, iclass 6, count 0 2006.224.07:46:28.15#ibcon#end of sib2, iclass 6, count 0 2006.224.07:46:28.15#ibcon#*mode == 0, iclass 6, count 0 2006.224.07:46:28.15#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.224.07:46:28.15#ibcon#[25=USB\r\n] 2006.224.07:46:28.15#ibcon#*before write, iclass 6, count 0 2006.224.07:46:28.15#ibcon#enter sib2, iclass 6, count 0 2006.224.07:46:28.15#ibcon#flushed, iclass 6, count 0 2006.224.07:46:28.15#ibcon#about to write, iclass 6, count 0 2006.224.07:46:28.15#ibcon#wrote, iclass 6, count 0 2006.224.07:46:28.15#ibcon#about to read 3, iclass 6, count 0 2006.224.07:46:28.17#ibcon#read 3, iclass 6, count 0 2006.224.07:46:28.17#ibcon#about to read 4, iclass 6, count 0 2006.224.07:46:28.17#ibcon#read 4, iclass 6, count 0 2006.224.07:46:28.17#ibcon#about to read 5, iclass 6, count 0 2006.224.07:46:28.17#ibcon#read 5, iclass 6, count 0 2006.224.07:46:28.17#ibcon#about to read 6, iclass 6, count 0 2006.224.07:46:28.17#ibcon#read 6, iclass 6, count 0 2006.224.07:46:28.17#ibcon#end of sib2, iclass 6, count 0 2006.224.07:46:28.17#ibcon#*after write, iclass 6, count 0 2006.224.07:46:28.17#ibcon#*before return 0, iclass 6, count 0 2006.224.07:46:28.17#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.224.07:46:28.17#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.224.07:46:28.17#ibcon#about to clear, iclass 6 cls_cnt 0 2006.224.07:46:28.17#ibcon#cleared, iclass 6 cls_cnt 0 2006.224.07:46:28.17$vc4f8/valo=2,572.99 2006.224.07:46:28.17#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.224.07:46:28.17#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.224.07:46:28.17#ibcon#ireg 17 cls_cnt 0 2006.224.07:46:28.17#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.224.07:46:28.17#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.224.07:46:28.17#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.224.07:46:28.17#ibcon#enter wrdev, iclass 14, count 0 2006.224.07:46:28.17#ibcon#first serial, iclass 14, count 0 2006.224.07:46:28.17#ibcon#enter sib2, iclass 14, count 0 2006.224.07:46:28.17#ibcon#flushed, iclass 14, count 0 2006.224.07:46:28.17#ibcon#about to write, iclass 14, count 0 2006.224.07:46:28.17#ibcon#wrote, iclass 14, count 0 2006.224.07:46:28.17#ibcon#about to read 3, iclass 14, count 0 2006.224.07:46:28.19#ibcon#read 3, iclass 14, count 0 2006.224.07:46:28.19#ibcon#about to read 4, iclass 14, count 0 2006.224.07:46:28.19#ibcon#read 4, iclass 14, count 0 2006.224.07:46:28.19#ibcon#about to read 5, iclass 14, count 0 2006.224.07:46:28.19#ibcon#read 5, iclass 14, count 0 2006.224.07:46:28.19#ibcon#about to read 6, iclass 14, count 0 2006.224.07:46:28.19#ibcon#read 6, iclass 14, count 0 2006.224.07:46:28.19#ibcon#end of sib2, iclass 14, count 0 2006.224.07:46:28.19#ibcon#*mode == 0, iclass 14, count 0 2006.224.07:46:28.19#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.224.07:46:28.19#ibcon#[26=FRQ=02,572.99\r\n] 2006.224.07:46:28.19#ibcon#*before write, iclass 14, count 0 2006.224.07:46:28.19#ibcon#enter sib2, iclass 14, count 0 2006.224.07:46:28.19#ibcon#flushed, iclass 14, count 0 2006.224.07:46:28.19#ibcon#about to write, iclass 14, count 0 2006.224.07:46:28.19#ibcon#wrote, iclass 14, count 0 2006.224.07:46:28.19#ibcon#about to read 3, iclass 14, count 0 2006.224.07:46:28.24#ibcon#read 3, iclass 14, count 0 2006.224.07:46:28.24#ibcon#about to read 4, iclass 14, count 0 2006.224.07:46:28.24#ibcon#read 4, iclass 14, count 0 2006.224.07:46:28.24#ibcon#about to read 5, iclass 14, count 0 2006.224.07:46:28.24#ibcon#read 5, iclass 14, count 0 2006.224.07:46:28.24#ibcon#about to read 6, iclass 14, count 0 2006.224.07:46:28.24#ibcon#read 6, iclass 14, count 0 2006.224.07:46:28.24#ibcon#end of sib2, iclass 14, count 0 2006.224.07:46:28.24#ibcon#*after write, iclass 14, count 0 2006.224.07:46:28.24#ibcon#*before return 0, iclass 14, count 0 2006.224.07:46:28.24#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.224.07:46:28.24#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.224.07:46:28.24#ibcon#about to clear, iclass 14 cls_cnt 0 2006.224.07:46:28.24#ibcon#cleared, iclass 14 cls_cnt 0 2006.224.07:46:28.24$vc4f8/va=2,7 2006.224.07:46:28.24#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.224.07:46:28.24#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.224.07:46:28.24#ibcon#ireg 11 cls_cnt 2 2006.224.07:46:28.24#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.224.07:46:28.28#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.224.07:46:28.28#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.224.07:46:28.28#ibcon#enter wrdev, iclass 16, count 2 2006.224.07:46:28.28#ibcon#first serial, iclass 16, count 2 2006.224.07:46:28.28#ibcon#enter sib2, iclass 16, count 2 2006.224.07:46:28.28#ibcon#flushed, iclass 16, count 2 2006.224.07:46:28.28#ibcon#about to write, iclass 16, count 2 2006.224.07:46:28.28#ibcon#wrote, iclass 16, count 2 2006.224.07:46:28.28#ibcon#about to read 3, iclass 16, count 2 2006.224.07:46:28.30#ibcon#read 3, iclass 16, count 2 2006.224.07:46:28.30#ibcon#about to read 4, iclass 16, count 2 2006.224.07:46:28.30#ibcon#read 4, iclass 16, count 2 2006.224.07:46:28.30#ibcon#about to read 5, iclass 16, count 2 2006.224.07:46:28.30#ibcon#read 5, iclass 16, count 2 2006.224.07:46:28.30#ibcon#about to read 6, iclass 16, count 2 2006.224.07:46:28.30#ibcon#read 6, iclass 16, count 2 2006.224.07:46:28.30#ibcon#end of sib2, iclass 16, count 2 2006.224.07:46:28.30#ibcon#*mode == 0, iclass 16, count 2 2006.224.07:46:28.30#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.224.07:46:28.30#ibcon#[25=AT02-07\r\n] 2006.224.07:46:28.30#ibcon#*before write, iclass 16, count 2 2006.224.07:46:28.30#ibcon#enter sib2, iclass 16, count 2 2006.224.07:46:28.30#ibcon#flushed, iclass 16, count 2 2006.224.07:46:28.30#ibcon#about to write, iclass 16, count 2 2006.224.07:46:28.30#ibcon#wrote, iclass 16, count 2 2006.224.07:46:28.30#ibcon#about to read 3, iclass 16, count 2 2006.224.07:46:28.33#ibcon#read 3, iclass 16, count 2 2006.224.07:46:28.33#ibcon#about to read 4, iclass 16, count 2 2006.224.07:46:28.33#ibcon#read 4, iclass 16, count 2 2006.224.07:46:28.33#ibcon#about to read 5, iclass 16, count 2 2006.224.07:46:28.33#ibcon#read 5, iclass 16, count 2 2006.224.07:46:28.33#ibcon#about to read 6, iclass 16, count 2 2006.224.07:46:28.33#ibcon#read 6, iclass 16, count 2 2006.224.07:46:28.33#ibcon#end of sib2, iclass 16, count 2 2006.224.07:46:28.33#ibcon#*after write, iclass 16, count 2 2006.224.07:46:28.33#ibcon#*before return 0, iclass 16, count 2 2006.224.07:46:28.33#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.224.07:46:28.33#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.224.07:46:28.33#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.224.07:46:28.33#ibcon#ireg 7 cls_cnt 0 2006.224.07:46:28.33#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.224.07:46:28.45#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.224.07:46:28.45#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.224.07:46:28.45#ibcon#enter wrdev, iclass 16, count 0 2006.224.07:46:28.45#ibcon#first serial, iclass 16, count 0 2006.224.07:46:28.45#ibcon#enter sib2, iclass 16, count 0 2006.224.07:46:28.45#ibcon#flushed, iclass 16, count 0 2006.224.07:46:28.45#ibcon#about to write, iclass 16, count 0 2006.224.07:46:28.45#ibcon#wrote, iclass 16, count 0 2006.224.07:46:28.45#ibcon#about to read 3, iclass 16, count 0 2006.224.07:46:28.47#ibcon#read 3, iclass 16, count 0 2006.224.07:46:28.47#ibcon#about to read 4, iclass 16, count 0 2006.224.07:46:28.47#ibcon#read 4, iclass 16, count 0 2006.224.07:46:28.47#ibcon#about to read 5, iclass 16, count 0 2006.224.07:46:28.47#ibcon#read 5, iclass 16, count 0 2006.224.07:46:28.47#ibcon#about to read 6, iclass 16, count 0 2006.224.07:46:28.47#ibcon#read 6, iclass 16, count 0 2006.224.07:46:28.47#ibcon#end of sib2, iclass 16, count 0 2006.224.07:46:28.47#ibcon#*mode == 0, iclass 16, count 0 2006.224.07:46:28.47#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.224.07:46:28.47#ibcon#[25=USB\r\n] 2006.224.07:46:28.47#ibcon#*before write, iclass 16, count 0 2006.224.07:46:28.47#ibcon#enter sib2, iclass 16, count 0 2006.224.07:46:28.47#ibcon#flushed, iclass 16, count 0 2006.224.07:46:28.47#ibcon#about to write, iclass 16, count 0 2006.224.07:46:28.47#ibcon#wrote, iclass 16, count 0 2006.224.07:46:28.47#ibcon#about to read 3, iclass 16, count 0 2006.224.07:46:28.50#ibcon#read 3, iclass 16, count 0 2006.224.07:46:28.50#ibcon#about to read 4, iclass 16, count 0 2006.224.07:46:28.50#ibcon#read 4, iclass 16, count 0 2006.224.07:46:28.50#ibcon#about to read 5, iclass 16, count 0 2006.224.07:46:28.50#ibcon#read 5, iclass 16, count 0 2006.224.07:46:28.50#ibcon#about to read 6, iclass 16, count 0 2006.224.07:46:28.50#ibcon#read 6, iclass 16, count 0 2006.224.07:46:28.50#ibcon#end of sib2, iclass 16, count 0 2006.224.07:46:28.50#ibcon#*after write, iclass 16, count 0 2006.224.07:46:28.50#ibcon#*before return 0, iclass 16, count 0 2006.224.07:46:28.50#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.224.07:46:28.50#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.224.07:46:28.50#ibcon#about to clear, iclass 16 cls_cnt 0 2006.224.07:46:28.50#ibcon#cleared, iclass 16 cls_cnt 0 2006.224.07:46:28.50$vc4f8/valo=3,672.99 2006.224.07:46:28.50#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.224.07:46:28.50#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.224.07:46:28.50#ibcon#ireg 17 cls_cnt 0 2006.224.07:46:28.50#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.224.07:46:28.50#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.224.07:46:28.50#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.224.07:46:28.50#ibcon#enter wrdev, iclass 18, count 0 2006.224.07:46:28.50#ibcon#first serial, iclass 18, count 0 2006.224.07:46:28.50#ibcon#enter sib2, iclass 18, count 0 2006.224.07:46:28.50#ibcon#flushed, iclass 18, count 0 2006.224.07:46:28.50#ibcon#about to write, iclass 18, count 0 2006.224.07:46:28.50#ibcon#wrote, iclass 18, count 0 2006.224.07:46:28.50#ibcon#about to read 3, iclass 18, count 0 2006.224.07:46:28.52#ibcon#read 3, iclass 18, count 0 2006.224.07:46:28.52#ibcon#about to read 4, iclass 18, count 0 2006.224.07:46:28.52#ibcon#read 4, iclass 18, count 0 2006.224.07:46:28.52#ibcon#about to read 5, iclass 18, count 0 2006.224.07:46:28.52#ibcon#read 5, iclass 18, count 0 2006.224.07:46:28.52#ibcon#about to read 6, iclass 18, count 0 2006.224.07:46:28.52#ibcon#read 6, iclass 18, count 0 2006.224.07:46:28.52#ibcon#end of sib2, iclass 18, count 0 2006.224.07:46:28.52#ibcon#*mode == 0, iclass 18, count 0 2006.224.07:46:28.52#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.224.07:46:28.52#ibcon#[26=FRQ=03,672.99\r\n] 2006.224.07:46:28.52#ibcon#*before write, iclass 18, count 0 2006.224.07:46:28.52#ibcon#enter sib2, iclass 18, count 0 2006.224.07:46:28.52#ibcon#flushed, iclass 18, count 0 2006.224.07:46:28.52#ibcon#about to write, iclass 18, count 0 2006.224.07:46:28.52#ibcon#wrote, iclass 18, count 0 2006.224.07:46:28.52#ibcon#about to read 3, iclass 18, count 0 2006.224.07:46:28.56#ibcon#read 3, iclass 18, count 0 2006.224.07:46:28.56#ibcon#about to read 4, iclass 18, count 0 2006.224.07:46:28.56#ibcon#read 4, iclass 18, count 0 2006.224.07:46:28.56#ibcon#about to read 5, iclass 18, count 0 2006.224.07:46:28.56#ibcon#read 5, iclass 18, count 0 2006.224.07:46:28.56#ibcon#about to read 6, iclass 18, count 0 2006.224.07:46:28.56#ibcon#read 6, iclass 18, count 0 2006.224.07:46:28.56#ibcon#end of sib2, iclass 18, count 0 2006.224.07:46:28.56#ibcon#*after write, iclass 18, count 0 2006.224.07:46:28.56#ibcon#*before return 0, iclass 18, count 0 2006.224.07:46:28.56#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.224.07:46:28.56#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.224.07:46:28.56#ibcon#about to clear, iclass 18 cls_cnt 0 2006.224.07:46:28.56#ibcon#cleared, iclass 18 cls_cnt 0 2006.224.07:46:28.56$vc4f8/va=3,6 2006.224.07:46:28.56#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.224.07:46:28.56#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.224.07:46:28.56#ibcon#ireg 11 cls_cnt 2 2006.224.07:46:28.56#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.224.07:46:28.63#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.224.07:46:28.63#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.224.07:46:28.63#ibcon#enter wrdev, iclass 20, count 2 2006.224.07:46:28.63#ibcon#first serial, iclass 20, count 2 2006.224.07:46:28.63#ibcon#enter sib2, iclass 20, count 2 2006.224.07:46:28.63#ibcon#flushed, iclass 20, count 2 2006.224.07:46:28.63#ibcon#about to write, iclass 20, count 2 2006.224.07:46:28.63#ibcon#wrote, iclass 20, count 2 2006.224.07:46:28.63#ibcon#about to read 3, iclass 20, count 2 2006.224.07:46:28.64#ibcon#read 3, iclass 20, count 2 2006.224.07:46:28.64#ibcon#about to read 4, iclass 20, count 2 2006.224.07:46:28.64#ibcon#read 4, iclass 20, count 2 2006.224.07:46:28.64#ibcon#about to read 5, iclass 20, count 2 2006.224.07:46:28.64#ibcon#read 5, iclass 20, count 2 2006.224.07:46:28.64#ibcon#about to read 6, iclass 20, count 2 2006.224.07:46:28.64#ibcon#read 6, iclass 20, count 2 2006.224.07:46:28.64#ibcon#end of sib2, iclass 20, count 2 2006.224.07:46:28.64#ibcon#*mode == 0, iclass 20, count 2 2006.224.07:46:28.64#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.224.07:46:28.64#ibcon#[25=AT03-06\r\n] 2006.224.07:46:28.64#ibcon#*before write, iclass 20, count 2 2006.224.07:46:28.64#ibcon#enter sib2, iclass 20, count 2 2006.224.07:46:28.64#ibcon#flushed, iclass 20, count 2 2006.224.07:46:28.64#ibcon#about to write, iclass 20, count 2 2006.224.07:46:28.64#ibcon#wrote, iclass 20, count 2 2006.224.07:46:28.64#ibcon#about to read 3, iclass 20, count 2 2006.224.07:46:28.67#ibcon#read 3, iclass 20, count 2 2006.224.07:46:28.67#ibcon#about to read 4, iclass 20, count 2 2006.224.07:46:28.67#ibcon#read 4, iclass 20, count 2 2006.224.07:46:28.67#ibcon#about to read 5, iclass 20, count 2 2006.224.07:46:28.67#ibcon#read 5, iclass 20, count 2 2006.224.07:46:28.67#ibcon#about to read 6, iclass 20, count 2 2006.224.07:46:28.67#ibcon#read 6, iclass 20, count 2 2006.224.07:46:28.67#ibcon#end of sib2, iclass 20, count 2 2006.224.07:46:28.67#ibcon#*after write, iclass 20, count 2 2006.224.07:46:28.67#ibcon#*before return 0, iclass 20, count 2 2006.224.07:46:28.67#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.224.07:46:28.67#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.224.07:46:28.67#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.224.07:46:28.67#ibcon#ireg 7 cls_cnt 0 2006.224.07:46:28.67#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.224.07:46:28.79#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.224.07:46:28.79#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.224.07:46:28.79#ibcon#enter wrdev, iclass 20, count 0 2006.224.07:46:28.79#ibcon#first serial, iclass 20, count 0 2006.224.07:46:28.79#ibcon#enter sib2, iclass 20, count 0 2006.224.07:46:28.79#ibcon#flushed, iclass 20, count 0 2006.224.07:46:28.79#ibcon#about to write, iclass 20, count 0 2006.224.07:46:28.79#ibcon#wrote, iclass 20, count 0 2006.224.07:46:28.79#ibcon#about to read 3, iclass 20, count 0 2006.224.07:46:28.81#ibcon#read 3, iclass 20, count 0 2006.224.07:46:28.81#ibcon#about to read 4, iclass 20, count 0 2006.224.07:46:28.81#ibcon#read 4, iclass 20, count 0 2006.224.07:46:28.81#ibcon#about to read 5, iclass 20, count 0 2006.224.07:46:28.81#ibcon#read 5, iclass 20, count 0 2006.224.07:46:28.81#ibcon#about to read 6, iclass 20, count 0 2006.224.07:46:28.81#ibcon#read 6, iclass 20, count 0 2006.224.07:46:28.81#ibcon#end of sib2, iclass 20, count 0 2006.224.07:46:28.81#ibcon#*mode == 0, iclass 20, count 0 2006.224.07:46:28.81#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.224.07:46:28.81#ibcon#[25=USB\r\n] 2006.224.07:46:28.81#ibcon#*before write, iclass 20, count 0 2006.224.07:46:28.81#ibcon#enter sib2, iclass 20, count 0 2006.224.07:46:28.81#ibcon#flushed, iclass 20, count 0 2006.224.07:46:28.81#ibcon#about to write, iclass 20, count 0 2006.224.07:46:28.81#ibcon#wrote, iclass 20, count 0 2006.224.07:46:28.81#ibcon#about to read 3, iclass 20, count 0 2006.224.07:46:28.84#ibcon#read 3, iclass 20, count 0 2006.224.07:46:28.84#ibcon#about to read 4, iclass 20, count 0 2006.224.07:46:28.84#ibcon#read 4, iclass 20, count 0 2006.224.07:46:28.84#ibcon#about to read 5, iclass 20, count 0 2006.224.07:46:28.84#ibcon#read 5, iclass 20, count 0 2006.224.07:46:28.84#ibcon#about to read 6, iclass 20, count 0 2006.224.07:46:28.84#ibcon#read 6, iclass 20, count 0 2006.224.07:46:28.84#ibcon#end of sib2, iclass 20, count 0 2006.224.07:46:28.84#ibcon#*after write, iclass 20, count 0 2006.224.07:46:28.84#ibcon#*before return 0, iclass 20, count 0 2006.224.07:46:28.84#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.224.07:46:28.84#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.224.07:46:28.84#ibcon#about to clear, iclass 20 cls_cnt 0 2006.224.07:46:28.84#ibcon#cleared, iclass 20 cls_cnt 0 2006.224.07:46:28.84$vc4f8/valo=4,832.99 2006.224.07:46:28.84#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.224.07:46:28.84#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.224.07:46:28.84#ibcon#ireg 17 cls_cnt 0 2006.224.07:46:28.84#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.224.07:46:28.84#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.224.07:46:28.84#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.224.07:46:28.84#ibcon#enter wrdev, iclass 22, count 0 2006.224.07:46:28.84#ibcon#first serial, iclass 22, count 0 2006.224.07:46:28.84#ibcon#enter sib2, iclass 22, count 0 2006.224.07:46:28.84#ibcon#flushed, iclass 22, count 0 2006.224.07:46:28.84#ibcon#about to write, iclass 22, count 0 2006.224.07:46:28.84#ibcon#wrote, iclass 22, count 0 2006.224.07:46:28.84#ibcon#about to read 3, iclass 22, count 0 2006.224.07:46:28.86#ibcon#read 3, iclass 22, count 0 2006.224.07:46:28.86#ibcon#about to read 4, iclass 22, count 0 2006.224.07:46:28.86#ibcon#read 4, iclass 22, count 0 2006.224.07:46:28.86#ibcon#about to read 5, iclass 22, count 0 2006.224.07:46:28.86#ibcon#read 5, iclass 22, count 0 2006.224.07:46:28.86#ibcon#about to read 6, iclass 22, count 0 2006.224.07:46:28.86#ibcon#read 6, iclass 22, count 0 2006.224.07:46:28.86#ibcon#end of sib2, iclass 22, count 0 2006.224.07:46:28.86#ibcon#*mode == 0, iclass 22, count 0 2006.224.07:46:28.86#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.224.07:46:28.86#ibcon#[26=FRQ=04,832.99\r\n] 2006.224.07:46:28.86#ibcon#*before write, iclass 22, count 0 2006.224.07:46:28.86#ibcon#enter sib2, iclass 22, count 0 2006.224.07:46:28.86#ibcon#flushed, iclass 22, count 0 2006.224.07:46:28.86#ibcon#about to write, iclass 22, count 0 2006.224.07:46:28.86#ibcon#wrote, iclass 22, count 0 2006.224.07:46:28.86#ibcon#about to read 3, iclass 22, count 0 2006.224.07:46:28.90#ibcon#read 3, iclass 22, count 0 2006.224.07:46:28.90#ibcon#about to read 4, iclass 22, count 0 2006.224.07:46:28.90#ibcon#read 4, iclass 22, count 0 2006.224.07:46:28.90#ibcon#about to read 5, iclass 22, count 0 2006.224.07:46:28.90#ibcon#read 5, iclass 22, count 0 2006.224.07:46:28.90#ibcon#about to read 6, iclass 22, count 0 2006.224.07:46:28.90#ibcon#read 6, iclass 22, count 0 2006.224.07:46:28.90#ibcon#end of sib2, iclass 22, count 0 2006.224.07:46:28.90#ibcon#*after write, iclass 22, count 0 2006.224.07:46:28.90#ibcon#*before return 0, iclass 22, count 0 2006.224.07:46:28.90#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.224.07:46:28.90#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.224.07:46:28.90#ibcon#about to clear, iclass 22 cls_cnt 0 2006.224.07:46:28.90#ibcon#cleared, iclass 22 cls_cnt 0 2006.224.07:46:28.90$vc4f8/va=4,7 2006.224.07:46:28.90#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.224.07:46:28.90#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.224.07:46:28.90#ibcon#ireg 11 cls_cnt 2 2006.224.07:46:28.90#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.224.07:46:28.96#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.224.07:46:28.96#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.224.07:46:28.96#ibcon#enter wrdev, iclass 24, count 2 2006.224.07:46:28.96#ibcon#first serial, iclass 24, count 2 2006.224.07:46:28.96#ibcon#enter sib2, iclass 24, count 2 2006.224.07:46:28.96#ibcon#flushed, iclass 24, count 2 2006.224.07:46:28.96#ibcon#about to write, iclass 24, count 2 2006.224.07:46:28.96#ibcon#wrote, iclass 24, count 2 2006.224.07:46:28.96#ibcon#about to read 3, iclass 24, count 2 2006.224.07:46:28.98#ibcon#read 3, iclass 24, count 2 2006.224.07:46:28.98#ibcon#about to read 4, iclass 24, count 2 2006.224.07:46:28.98#ibcon#read 4, iclass 24, count 2 2006.224.07:46:28.98#ibcon#about to read 5, iclass 24, count 2 2006.224.07:46:28.98#ibcon#read 5, iclass 24, count 2 2006.224.07:46:28.98#ibcon#about to read 6, iclass 24, count 2 2006.224.07:46:28.98#ibcon#read 6, iclass 24, count 2 2006.224.07:46:28.98#ibcon#end of sib2, iclass 24, count 2 2006.224.07:46:28.98#ibcon#*mode == 0, iclass 24, count 2 2006.224.07:46:28.98#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.224.07:46:28.98#ibcon#[25=AT04-07\r\n] 2006.224.07:46:28.98#ibcon#*before write, iclass 24, count 2 2006.224.07:46:28.98#ibcon#enter sib2, iclass 24, count 2 2006.224.07:46:28.98#ibcon#flushed, iclass 24, count 2 2006.224.07:46:28.98#ibcon#about to write, iclass 24, count 2 2006.224.07:46:28.98#ibcon#wrote, iclass 24, count 2 2006.224.07:46:28.98#ibcon#about to read 3, iclass 24, count 2 2006.224.07:46:29.01#ibcon#read 3, iclass 24, count 2 2006.224.07:46:29.01#ibcon#about to read 4, iclass 24, count 2 2006.224.07:46:29.01#ibcon#read 4, iclass 24, count 2 2006.224.07:46:29.01#ibcon#about to read 5, iclass 24, count 2 2006.224.07:46:29.01#ibcon#read 5, iclass 24, count 2 2006.224.07:46:29.01#ibcon#about to read 6, iclass 24, count 2 2006.224.07:46:29.01#ibcon#read 6, iclass 24, count 2 2006.224.07:46:29.01#ibcon#end of sib2, iclass 24, count 2 2006.224.07:46:29.01#ibcon#*after write, iclass 24, count 2 2006.224.07:46:29.01#ibcon#*before return 0, iclass 24, count 2 2006.224.07:46:29.01#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.224.07:46:29.01#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.224.07:46:29.01#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.224.07:46:29.01#ibcon#ireg 7 cls_cnt 0 2006.224.07:46:29.01#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.224.07:46:29.13#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.224.07:46:29.13#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.224.07:46:29.13#ibcon#enter wrdev, iclass 24, count 0 2006.224.07:46:29.13#ibcon#first serial, iclass 24, count 0 2006.224.07:46:29.13#ibcon#enter sib2, iclass 24, count 0 2006.224.07:46:29.13#ibcon#flushed, iclass 24, count 0 2006.224.07:46:29.13#ibcon#about to write, iclass 24, count 0 2006.224.07:46:29.13#ibcon#wrote, iclass 24, count 0 2006.224.07:46:29.13#ibcon#about to read 3, iclass 24, count 0 2006.224.07:46:29.15#ibcon#read 3, iclass 24, count 0 2006.224.07:46:29.15#ibcon#about to read 4, iclass 24, count 0 2006.224.07:46:29.15#ibcon#read 4, iclass 24, count 0 2006.224.07:46:29.15#ibcon#about to read 5, iclass 24, count 0 2006.224.07:46:29.15#ibcon#read 5, iclass 24, count 0 2006.224.07:46:29.15#ibcon#about to read 6, iclass 24, count 0 2006.224.07:46:29.15#ibcon#read 6, iclass 24, count 0 2006.224.07:46:29.15#ibcon#end of sib2, iclass 24, count 0 2006.224.07:46:29.15#ibcon#*mode == 0, iclass 24, count 0 2006.224.07:46:29.15#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.224.07:46:29.15#ibcon#[25=USB\r\n] 2006.224.07:46:29.15#ibcon#*before write, iclass 24, count 0 2006.224.07:46:29.15#ibcon#enter sib2, iclass 24, count 0 2006.224.07:46:29.15#ibcon#flushed, iclass 24, count 0 2006.224.07:46:29.15#ibcon#about to write, iclass 24, count 0 2006.224.07:46:29.15#ibcon#wrote, iclass 24, count 0 2006.224.07:46:29.15#ibcon#about to read 3, iclass 24, count 0 2006.224.07:46:29.18#ibcon#read 3, iclass 24, count 0 2006.224.07:46:29.18#ibcon#about to read 4, iclass 24, count 0 2006.224.07:46:29.18#ibcon#read 4, iclass 24, count 0 2006.224.07:46:29.18#ibcon#about to read 5, iclass 24, count 0 2006.224.07:46:29.18#ibcon#read 5, iclass 24, count 0 2006.224.07:46:29.18#ibcon#about to read 6, iclass 24, count 0 2006.224.07:46:29.18#ibcon#read 6, iclass 24, count 0 2006.224.07:46:29.18#ibcon#end of sib2, iclass 24, count 0 2006.224.07:46:29.18#ibcon#*after write, iclass 24, count 0 2006.224.07:46:29.18#ibcon#*before return 0, iclass 24, count 0 2006.224.07:46:29.18#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.224.07:46:29.18#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.224.07:46:29.18#ibcon#about to clear, iclass 24 cls_cnt 0 2006.224.07:46:29.18#ibcon#cleared, iclass 24 cls_cnt 0 2006.224.07:46:29.18$vc4f8/valo=5,652.99 2006.224.07:46:29.18#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.224.07:46:29.18#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.224.07:46:29.18#ibcon#ireg 17 cls_cnt 0 2006.224.07:46:29.18#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.224.07:46:29.18#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.224.07:46:29.18#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.224.07:46:29.18#ibcon#enter wrdev, iclass 26, count 0 2006.224.07:46:29.18#ibcon#first serial, iclass 26, count 0 2006.224.07:46:29.18#ibcon#enter sib2, iclass 26, count 0 2006.224.07:46:29.18#ibcon#flushed, iclass 26, count 0 2006.224.07:46:29.18#ibcon#about to write, iclass 26, count 0 2006.224.07:46:29.18#ibcon#wrote, iclass 26, count 0 2006.224.07:46:29.18#ibcon#about to read 3, iclass 26, count 0 2006.224.07:46:29.20#ibcon#read 3, iclass 26, count 0 2006.224.07:46:29.20#ibcon#about to read 4, iclass 26, count 0 2006.224.07:46:29.20#ibcon#read 4, iclass 26, count 0 2006.224.07:46:29.20#ibcon#about to read 5, iclass 26, count 0 2006.224.07:46:29.20#ibcon#read 5, iclass 26, count 0 2006.224.07:46:29.20#ibcon#about to read 6, iclass 26, count 0 2006.224.07:46:29.20#ibcon#read 6, iclass 26, count 0 2006.224.07:46:29.20#ibcon#end of sib2, iclass 26, count 0 2006.224.07:46:29.20#ibcon#*mode == 0, iclass 26, count 0 2006.224.07:46:29.20#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.224.07:46:29.20#ibcon#[26=FRQ=05,652.99\r\n] 2006.224.07:46:29.20#ibcon#*before write, iclass 26, count 0 2006.224.07:46:29.20#ibcon#enter sib2, iclass 26, count 0 2006.224.07:46:29.20#ibcon#flushed, iclass 26, count 0 2006.224.07:46:29.20#ibcon#about to write, iclass 26, count 0 2006.224.07:46:29.20#ibcon#wrote, iclass 26, count 0 2006.224.07:46:29.20#ibcon#about to read 3, iclass 26, count 0 2006.224.07:46:29.24#ibcon#read 3, iclass 26, count 0 2006.224.07:46:29.24#ibcon#about to read 4, iclass 26, count 0 2006.224.07:46:29.24#ibcon#read 4, iclass 26, count 0 2006.224.07:46:29.24#ibcon#about to read 5, iclass 26, count 0 2006.224.07:46:29.24#ibcon#read 5, iclass 26, count 0 2006.224.07:46:29.24#ibcon#about to read 6, iclass 26, count 0 2006.224.07:46:29.24#ibcon#read 6, iclass 26, count 0 2006.224.07:46:29.24#ibcon#end of sib2, iclass 26, count 0 2006.224.07:46:29.24#ibcon#*after write, iclass 26, count 0 2006.224.07:46:29.24#ibcon#*before return 0, iclass 26, count 0 2006.224.07:46:29.24#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.224.07:46:29.24#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.224.07:46:29.24#ibcon#about to clear, iclass 26 cls_cnt 0 2006.224.07:46:29.24#ibcon#cleared, iclass 26 cls_cnt 0 2006.224.07:46:29.24$vc4f8/va=5,7 2006.224.07:46:29.24#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.224.07:46:29.24#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.224.07:46:29.24#ibcon#ireg 11 cls_cnt 2 2006.224.07:46:29.24#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.224.07:46:29.30#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.224.07:46:29.30#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.224.07:46:29.30#ibcon#enter wrdev, iclass 28, count 2 2006.224.07:46:29.30#ibcon#first serial, iclass 28, count 2 2006.224.07:46:29.30#ibcon#enter sib2, iclass 28, count 2 2006.224.07:46:29.30#ibcon#flushed, iclass 28, count 2 2006.224.07:46:29.30#ibcon#about to write, iclass 28, count 2 2006.224.07:46:29.30#ibcon#wrote, iclass 28, count 2 2006.224.07:46:29.30#ibcon#about to read 3, iclass 28, count 2 2006.224.07:46:29.32#ibcon#read 3, iclass 28, count 2 2006.224.07:46:29.32#ibcon#about to read 4, iclass 28, count 2 2006.224.07:46:29.32#ibcon#read 4, iclass 28, count 2 2006.224.07:46:29.32#ibcon#about to read 5, iclass 28, count 2 2006.224.07:46:29.32#ibcon#read 5, iclass 28, count 2 2006.224.07:46:29.32#ibcon#about to read 6, iclass 28, count 2 2006.224.07:46:29.32#ibcon#read 6, iclass 28, count 2 2006.224.07:46:29.32#ibcon#end of sib2, iclass 28, count 2 2006.224.07:46:29.32#ibcon#*mode == 0, iclass 28, count 2 2006.224.07:46:29.32#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.224.07:46:29.32#ibcon#[25=AT05-07\r\n] 2006.224.07:46:29.32#ibcon#*before write, iclass 28, count 2 2006.224.07:46:29.32#ibcon#enter sib2, iclass 28, count 2 2006.224.07:46:29.32#ibcon#flushed, iclass 28, count 2 2006.224.07:46:29.32#ibcon#about to write, iclass 28, count 2 2006.224.07:46:29.32#ibcon#wrote, iclass 28, count 2 2006.224.07:46:29.32#ibcon#about to read 3, iclass 28, count 2 2006.224.07:46:29.35#ibcon#read 3, iclass 28, count 2 2006.224.07:46:29.35#ibcon#about to read 4, iclass 28, count 2 2006.224.07:46:29.35#ibcon#read 4, iclass 28, count 2 2006.224.07:46:29.35#ibcon#about to read 5, iclass 28, count 2 2006.224.07:46:29.35#ibcon#read 5, iclass 28, count 2 2006.224.07:46:29.35#ibcon#about to read 6, iclass 28, count 2 2006.224.07:46:29.35#ibcon#read 6, iclass 28, count 2 2006.224.07:46:29.35#ibcon#end of sib2, iclass 28, count 2 2006.224.07:46:29.35#ibcon#*after write, iclass 28, count 2 2006.224.07:46:29.35#ibcon#*before return 0, iclass 28, count 2 2006.224.07:46:29.35#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.224.07:46:29.35#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.224.07:46:29.35#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.224.07:46:29.35#ibcon#ireg 7 cls_cnt 0 2006.224.07:46:29.35#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.224.07:46:29.47#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.224.07:46:29.47#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.224.07:46:29.47#ibcon#enter wrdev, iclass 28, count 0 2006.224.07:46:29.47#ibcon#first serial, iclass 28, count 0 2006.224.07:46:29.47#ibcon#enter sib2, iclass 28, count 0 2006.224.07:46:29.47#ibcon#flushed, iclass 28, count 0 2006.224.07:46:29.47#ibcon#about to write, iclass 28, count 0 2006.224.07:46:29.47#ibcon#wrote, iclass 28, count 0 2006.224.07:46:29.47#ibcon#about to read 3, iclass 28, count 0 2006.224.07:46:29.49#ibcon#read 3, iclass 28, count 0 2006.224.07:46:29.49#ibcon#about to read 4, iclass 28, count 0 2006.224.07:46:29.49#ibcon#read 4, iclass 28, count 0 2006.224.07:46:29.49#ibcon#about to read 5, iclass 28, count 0 2006.224.07:46:29.49#ibcon#read 5, iclass 28, count 0 2006.224.07:46:29.49#ibcon#about to read 6, iclass 28, count 0 2006.224.07:46:29.49#ibcon#read 6, iclass 28, count 0 2006.224.07:46:29.49#ibcon#end of sib2, iclass 28, count 0 2006.224.07:46:29.49#ibcon#*mode == 0, iclass 28, count 0 2006.224.07:46:29.49#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.224.07:46:29.49#ibcon#[25=USB\r\n] 2006.224.07:46:29.49#ibcon#*before write, iclass 28, count 0 2006.224.07:46:29.49#ibcon#enter sib2, iclass 28, count 0 2006.224.07:46:29.49#ibcon#flushed, iclass 28, count 0 2006.224.07:46:29.49#ibcon#about to write, iclass 28, count 0 2006.224.07:46:29.49#ibcon#wrote, iclass 28, count 0 2006.224.07:46:29.49#ibcon#about to read 3, iclass 28, count 0 2006.224.07:46:29.52#ibcon#read 3, iclass 28, count 0 2006.224.07:46:29.52#ibcon#about to read 4, iclass 28, count 0 2006.224.07:46:29.52#ibcon#read 4, iclass 28, count 0 2006.224.07:46:29.52#ibcon#about to read 5, iclass 28, count 0 2006.224.07:46:29.52#ibcon#read 5, iclass 28, count 0 2006.224.07:46:29.52#ibcon#about to read 6, iclass 28, count 0 2006.224.07:46:29.52#ibcon#read 6, iclass 28, count 0 2006.224.07:46:29.52#ibcon#end of sib2, iclass 28, count 0 2006.224.07:46:29.52#ibcon#*after write, iclass 28, count 0 2006.224.07:46:29.52#ibcon#*before return 0, iclass 28, count 0 2006.224.07:46:29.52#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.224.07:46:29.52#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.224.07:46:29.52#ibcon#about to clear, iclass 28 cls_cnt 0 2006.224.07:46:29.52#ibcon#cleared, iclass 28 cls_cnt 0 2006.224.07:46:29.52$vc4f8/valo=6,772.99 2006.224.07:46:29.52#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.224.07:46:29.52#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.224.07:46:29.52#ibcon#ireg 17 cls_cnt 0 2006.224.07:46:29.52#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.224.07:46:29.52#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.224.07:46:29.52#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.224.07:46:29.52#ibcon#enter wrdev, iclass 30, count 0 2006.224.07:46:29.52#ibcon#first serial, iclass 30, count 0 2006.224.07:46:29.52#ibcon#enter sib2, iclass 30, count 0 2006.224.07:46:29.52#ibcon#flushed, iclass 30, count 0 2006.224.07:46:29.52#ibcon#about to write, iclass 30, count 0 2006.224.07:46:29.52#ibcon#wrote, iclass 30, count 0 2006.224.07:46:29.52#ibcon#about to read 3, iclass 30, count 0 2006.224.07:46:29.54#ibcon#read 3, iclass 30, count 0 2006.224.07:46:29.54#ibcon#about to read 4, iclass 30, count 0 2006.224.07:46:29.54#ibcon#read 4, iclass 30, count 0 2006.224.07:46:29.54#ibcon#about to read 5, iclass 30, count 0 2006.224.07:46:29.54#ibcon#read 5, iclass 30, count 0 2006.224.07:46:29.54#ibcon#about to read 6, iclass 30, count 0 2006.224.07:46:29.54#ibcon#read 6, iclass 30, count 0 2006.224.07:46:29.54#ibcon#end of sib2, iclass 30, count 0 2006.224.07:46:29.54#ibcon#*mode == 0, iclass 30, count 0 2006.224.07:46:29.54#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.224.07:46:29.54#ibcon#[26=FRQ=06,772.99\r\n] 2006.224.07:46:29.54#ibcon#*before write, iclass 30, count 0 2006.224.07:46:29.54#ibcon#enter sib2, iclass 30, count 0 2006.224.07:46:29.54#ibcon#flushed, iclass 30, count 0 2006.224.07:46:29.54#ibcon#about to write, iclass 30, count 0 2006.224.07:46:29.54#ibcon#wrote, iclass 30, count 0 2006.224.07:46:29.54#ibcon#about to read 3, iclass 30, count 0 2006.224.07:46:29.58#ibcon#read 3, iclass 30, count 0 2006.224.07:46:29.58#ibcon#about to read 4, iclass 30, count 0 2006.224.07:46:29.58#ibcon#read 4, iclass 30, count 0 2006.224.07:46:29.58#ibcon#about to read 5, iclass 30, count 0 2006.224.07:46:29.58#ibcon#read 5, iclass 30, count 0 2006.224.07:46:29.58#ibcon#about to read 6, iclass 30, count 0 2006.224.07:46:29.58#ibcon#read 6, iclass 30, count 0 2006.224.07:46:29.58#ibcon#end of sib2, iclass 30, count 0 2006.224.07:46:29.58#ibcon#*after write, iclass 30, count 0 2006.224.07:46:29.58#ibcon#*before return 0, iclass 30, count 0 2006.224.07:46:29.58#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.224.07:46:29.58#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.224.07:46:29.58#ibcon#about to clear, iclass 30 cls_cnt 0 2006.224.07:46:29.58#ibcon#cleared, iclass 30 cls_cnt 0 2006.224.07:46:29.58$vc4f8/va=6,6 2006.224.07:46:29.58#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.224.07:46:29.58#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.224.07:46:29.58#ibcon#ireg 11 cls_cnt 2 2006.224.07:46:29.58#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.224.07:46:29.65#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.224.07:46:29.65#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.224.07:46:29.65#ibcon#enter wrdev, iclass 32, count 2 2006.224.07:46:29.65#ibcon#first serial, iclass 32, count 2 2006.224.07:46:29.65#ibcon#enter sib2, iclass 32, count 2 2006.224.07:46:29.65#ibcon#flushed, iclass 32, count 2 2006.224.07:46:29.65#ibcon#about to write, iclass 32, count 2 2006.224.07:46:29.65#ibcon#wrote, iclass 32, count 2 2006.224.07:46:29.65#ibcon#about to read 3, iclass 32, count 2 2006.224.07:46:29.66#ibcon#read 3, iclass 32, count 2 2006.224.07:46:29.66#ibcon#about to read 4, iclass 32, count 2 2006.224.07:46:29.66#ibcon#read 4, iclass 32, count 2 2006.224.07:46:29.66#ibcon#about to read 5, iclass 32, count 2 2006.224.07:46:29.66#ibcon#read 5, iclass 32, count 2 2006.224.07:46:29.66#ibcon#about to read 6, iclass 32, count 2 2006.224.07:46:29.66#ibcon#read 6, iclass 32, count 2 2006.224.07:46:29.66#ibcon#end of sib2, iclass 32, count 2 2006.224.07:46:29.66#ibcon#*mode == 0, iclass 32, count 2 2006.224.07:46:29.66#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.224.07:46:29.66#ibcon#[25=AT06-06\r\n] 2006.224.07:46:29.66#ibcon#*before write, iclass 32, count 2 2006.224.07:46:29.66#ibcon#enter sib2, iclass 32, count 2 2006.224.07:46:29.66#ibcon#flushed, iclass 32, count 2 2006.224.07:46:29.66#ibcon#about to write, iclass 32, count 2 2006.224.07:46:29.66#ibcon#wrote, iclass 32, count 2 2006.224.07:46:29.66#ibcon#about to read 3, iclass 32, count 2 2006.224.07:46:29.69#ibcon#read 3, iclass 32, count 2 2006.224.07:46:29.69#ibcon#about to read 4, iclass 32, count 2 2006.224.07:46:29.69#ibcon#read 4, iclass 32, count 2 2006.224.07:46:29.69#ibcon#about to read 5, iclass 32, count 2 2006.224.07:46:29.69#ibcon#read 5, iclass 32, count 2 2006.224.07:46:29.69#ibcon#about to read 6, iclass 32, count 2 2006.224.07:46:29.69#ibcon#read 6, iclass 32, count 2 2006.224.07:46:29.69#ibcon#end of sib2, iclass 32, count 2 2006.224.07:46:29.69#ibcon#*after write, iclass 32, count 2 2006.224.07:46:29.69#ibcon#*before return 0, iclass 32, count 2 2006.224.07:46:29.69#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.224.07:46:29.69#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.224.07:46:29.69#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.224.07:46:29.69#ibcon#ireg 7 cls_cnt 0 2006.224.07:46:29.69#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.224.07:46:29.81#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.224.07:46:29.81#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.224.07:46:29.81#ibcon#enter wrdev, iclass 32, count 0 2006.224.07:46:29.81#ibcon#first serial, iclass 32, count 0 2006.224.07:46:29.81#ibcon#enter sib2, iclass 32, count 0 2006.224.07:46:29.81#ibcon#flushed, iclass 32, count 0 2006.224.07:46:29.81#ibcon#about to write, iclass 32, count 0 2006.224.07:46:29.81#ibcon#wrote, iclass 32, count 0 2006.224.07:46:29.81#ibcon#about to read 3, iclass 32, count 0 2006.224.07:46:29.83#ibcon#read 3, iclass 32, count 0 2006.224.07:46:29.83#ibcon#about to read 4, iclass 32, count 0 2006.224.07:46:29.83#ibcon#read 4, iclass 32, count 0 2006.224.07:46:29.83#ibcon#about to read 5, iclass 32, count 0 2006.224.07:46:29.83#ibcon#read 5, iclass 32, count 0 2006.224.07:46:29.83#ibcon#about to read 6, iclass 32, count 0 2006.224.07:46:29.83#ibcon#read 6, iclass 32, count 0 2006.224.07:46:29.83#ibcon#end of sib2, iclass 32, count 0 2006.224.07:46:29.83#ibcon#*mode == 0, iclass 32, count 0 2006.224.07:46:29.83#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.224.07:46:29.83#ibcon#[25=USB\r\n] 2006.224.07:46:29.83#ibcon#*before write, iclass 32, count 0 2006.224.07:46:29.83#ibcon#enter sib2, iclass 32, count 0 2006.224.07:46:29.83#ibcon#flushed, iclass 32, count 0 2006.224.07:46:29.83#ibcon#about to write, iclass 32, count 0 2006.224.07:46:29.83#ibcon#wrote, iclass 32, count 0 2006.224.07:46:29.83#ibcon#about to read 3, iclass 32, count 0 2006.224.07:46:29.86#ibcon#read 3, iclass 32, count 0 2006.224.07:46:29.86#ibcon#about to read 4, iclass 32, count 0 2006.224.07:46:29.86#ibcon#read 4, iclass 32, count 0 2006.224.07:46:29.86#ibcon#about to read 5, iclass 32, count 0 2006.224.07:46:29.86#ibcon#read 5, iclass 32, count 0 2006.224.07:46:29.86#ibcon#about to read 6, iclass 32, count 0 2006.224.07:46:29.86#ibcon#read 6, iclass 32, count 0 2006.224.07:46:29.86#ibcon#end of sib2, iclass 32, count 0 2006.224.07:46:29.86#ibcon#*after write, iclass 32, count 0 2006.224.07:46:29.86#ibcon#*before return 0, iclass 32, count 0 2006.224.07:46:29.86#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.224.07:46:29.86#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.224.07:46:29.86#ibcon#about to clear, iclass 32 cls_cnt 0 2006.224.07:46:29.86#ibcon#cleared, iclass 32 cls_cnt 0 2006.224.07:46:29.86$vc4f8/valo=7,832.99 2006.224.07:46:29.86#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.224.07:46:29.86#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.224.07:46:29.86#ibcon#ireg 17 cls_cnt 0 2006.224.07:46:29.86#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.224.07:46:29.86#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.224.07:46:29.86#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.224.07:46:29.86#ibcon#enter wrdev, iclass 34, count 0 2006.224.07:46:29.86#ibcon#first serial, iclass 34, count 0 2006.224.07:46:29.86#ibcon#enter sib2, iclass 34, count 0 2006.224.07:46:29.86#ibcon#flushed, iclass 34, count 0 2006.224.07:46:29.86#ibcon#about to write, iclass 34, count 0 2006.224.07:46:29.86#ibcon#wrote, iclass 34, count 0 2006.224.07:46:29.86#ibcon#about to read 3, iclass 34, count 0 2006.224.07:46:29.88#ibcon#read 3, iclass 34, count 0 2006.224.07:46:29.88#ibcon#about to read 4, iclass 34, count 0 2006.224.07:46:29.88#ibcon#read 4, iclass 34, count 0 2006.224.07:46:29.88#ibcon#about to read 5, iclass 34, count 0 2006.224.07:46:29.88#ibcon#read 5, iclass 34, count 0 2006.224.07:46:29.88#ibcon#about to read 6, iclass 34, count 0 2006.224.07:46:29.88#ibcon#read 6, iclass 34, count 0 2006.224.07:46:29.88#ibcon#end of sib2, iclass 34, count 0 2006.224.07:46:29.88#ibcon#*mode == 0, iclass 34, count 0 2006.224.07:46:29.88#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.224.07:46:29.88#ibcon#[26=FRQ=07,832.99\r\n] 2006.224.07:46:29.88#ibcon#*before write, iclass 34, count 0 2006.224.07:46:29.88#ibcon#enter sib2, iclass 34, count 0 2006.224.07:46:29.88#ibcon#flushed, iclass 34, count 0 2006.224.07:46:29.88#ibcon#about to write, iclass 34, count 0 2006.224.07:46:29.88#ibcon#wrote, iclass 34, count 0 2006.224.07:46:29.88#ibcon#about to read 3, iclass 34, count 0 2006.224.07:46:29.92#ibcon#read 3, iclass 34, count 0 2006.224.07:46:29.92#ibcon#about to read 4, iclass 34, count 0 2006.224.07:46:29.92#ibcon#read 4, iclass 34, count 0 2006.224.07:46:29.92#ibcon#about to read 5, iclass 34, count 0 2006.224.07:46:29.92#ibcon#read 5, iclass 34, count 0 2006.224.07:46:29.92#ibcon#about to read 6, iclass 34, count 0 2006.224.07:46:29.92#ibcon#read 6, iclass 34, count 0 2006.224.07:46:29.92#ibcon#end of sib2, iclass 34, count 0 2006.224.07:46:29.92#ibcon#*after write, iclass 34, count 0 2006.224.07:46:29.92#ibcon#*before return 0, iclass 34, count 0 2006.224.07:46:29.92#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.224.07:46:29.92#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.224.07:46:29.92#ibcon#about to clear, iclass 34 cls_cnt 0 2006.224.07:46:29.92#ibcon#cleared, iclass 34 cls_cnt 0 2006.224.07:46:29.92$vc4f8/va=7,6 2006.224.07:46:29.92#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.224.07:46:29.92#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.224.07:46:29.92#ibcon#ireg 11 cls_cnt 2 2006.224.07:46:29.92#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.224.07:46:29.98#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.224.07:46:29.98#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.224.07:46:29.98#ibcon#enter wrdev, iclass 36, count 2 2006.224.07:46:29.98#ibcon#first serial, iclass 36, count 2 2006.224.07:46:29.98#ibcon#enter sib2, iclass 36, count 2 2006.224.07:46:29.98#ibcon#flushed, iclass 36, count 2 2006.224.07:46:29.98#ibcon#about to write, iclass 36, count 2 2006.224.07:46:29.98#ibcon#wrote, iclass 36, count 2 2006.224.07:46:29.98#ibcon#about to read 3, iclass 36, count 2 2006.224.07:46:30.00#ibcon#read 3, iclass 36, count 2 2006.224.07:46:30.00#ibcon#about to read 4, iclass 36, count 2 2006.224.07:46:30.00#ibcon#read 4, iclass 36, count 2 2006.224.07:46:30.00#ibcon#about to read 5, iclass 36, count 2 2006.224.07:46:30.00#ibcon#read 5, iclass 36, count 2 2006.224.07:46:30.00#ibcon#about to read 6, iclass 36, count 2 2006.224.07:46:30.00#ibcon#read 6, iclass 36, count 2 2006.224.07:46:30.00#ibcon#end of sib2, iclass 36, count 2 2006.224.07:46:30.00#ibcon#*mode == 0, iclass 36, count 2 2006.224.07:46:30.00#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.224.07:46:30.00#ibcon#[25=AT07-06\r\n] 2006.224.07:46:30.00#ibcon#*before write, iclass 36, count 2 2006.224.07:46:30.00#ibcon#enter sib2, iclass 36, count 2 2006.224.07:46:30.00#ibcon#flushed, iclass 36, count 2 2006.224.07:46:30.00#ibcon#about to write, iclass 36, count 2 2006.224.07:46:30.00#ibcon#wrote, iclass 36, count 2 2006.224.07:46:30.00#ibcon#about to read 3, iclass 36, count 2 2006.224.07:46:30.03#ibcon#read 3, iclass 36, count 2 2006.224.07:46:30.03#ibcon#about to read 4, iclass 36, count 2 2006.224.07:46:30.03#ibcon#read 4, iclass 36, count 2 2006.224.07:46:30.03#ibcon#about to read 5, iclass 36, count 2 2006.224.07:46:30.03#ibcon#read 5, iclass 36, count 2 2006.224.07:46:30.03#ibcon#about to read 6, iclass 36, count 2 2006.224.07:46:30.03#ibcon#read 6, iclass 36, count 2 2006.224.07:46:30.03#ibcon#end of sib2, iclass 36, count 2 2006.224.07:46:30.03#ibcon#*after write, iclass 36, count 2 2006.224.07:46:30.03#ibcon#*before return 0, iclass 36, count 2 2006.224.07:46:30.03#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.224.07:46:30.03#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.224.07:46:30.03#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.224.07:46:30.03#ibcon#ireg 7 cls_cnt 0 2006.224.07:46:30.03#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.224.07:46:30.15#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.224.07:46:30.15#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.224.07:46:30.15#ibcon#enter wrdev, iclass 36, count 0 2006.224.07:46:30.15#ibcon#first serial, iclass 36, count 0 2006.224.07:46:30.15#ibcon#enter sib2, iclass 36, count 0 2006.224.07:46:30.15#ibcon#flushed, iclass 36, count 0 2006.224.07:46:30.15#ibcon#about to write, iclass 36, count 0 2006.224.07:46:30.15#ibcon#wrote, iclass 36, count 0 2006.224.07:46:30.15#ibcon#about to read 3, iclass 36, count 0 2006.224.07:46:30.17#ibcon#read 3, iclass 36, count 0 2006.224.07:46:30.17#ibcon#about to read 4, iclass 36, count 0 2006.224.07:46:30.17#ibcon#read 4, iclass 36, count 0 2006.224.07:46:30.17#ibcon#about to read 5, iclass 36, count 0 2006.224.07:46:30.17#ibcon#read 5, iclass 36, count 0 2006.224.07:46:30.17#ibcon#about to read 6, iclass 36, count 0 2006.224.07:46:30.17#ibcon#read 6, iclass 36, count 0 2006.224.07:46:30.17#ibcon#end of sib2, iclass 36, count 0 2006.224.07:46:30.17#ibcon#*mode == 0, iclass 36, count 0 2006.224.07:46:30.17#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.224.07:46:30.17#ibcon#[25=USB\r\n] 2006.224.07:46:30.17#ibcon#*before write, iclass 36, count 0 2006.224.07:46:30.17#ibcon#enter sib2, iclass 36, count 0 2006.224.07:46:30.17#ibcon#flushed, iclass 36, count 0 2006.224.07:46:30.17#ibcon#about to write, iclass 36, count 0 2006.224.07:46:30.17#ibcon#wrote, iclass 36, count 0 2006.224.07:46:30.17#ibcon#about to read 3, iclass 36, count 0 2006.224.07:46:30.20#ibcon#read 3, iclass 36, count 0 2006.224.07:46:30.20#ibcon#about to read 4, iclass 36, count 0 2006.224.07:46:30.20#ibcon#read 4, iclass 36, count 0 2006.224.07:46:30.20#ibcon#about to read 5, iclass 36, count 0 2006.224.07:46:30.20#ibcon#read 5, iclass 36, count 0 2006.224.07:46:30.20#ibcon#about to read 6, iclass 36, count 0 2006.224.07:46:30.20#ibcon#read 6, iclass 36, count 0 2006.224.07:46:30.20#ibcon#end of sib2, iclass 36, count 0 2006.224.07:46:30.20#ibcon#*after write, iclass 36, count 0 2006.224.07:46:30.20#ibcon#*before return 0, iclass 36, count 0 2006.224.07:46:30.20#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.224.07:46:30.20#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.224.07:46:30.20#ibcon#about to clear, iclass 36 cls_cnt 0 2006.224.07:46:30.20#ibcon#cleared, iclass 36 cls_cnt 0 2006.224.07:46:30.20$vc4f8/valo=8,852.99 2006.224.07:46:30.20#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.224.07:46:30.20#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.224.07:46:30.20#ibcon#ireg 17 cls_cnt 0 2006.224.07:46:30.20#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.224.07:46:30.20#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.224.07:46:30.20#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.224.07:46:30.20#ibcon#enter wrdev, iclass 38, count 0 2006.224.07:46:30.20#ibcon#first serial, iclass 38, count 0 2006.224.07:46:30.20#ibcon#enter sib2, iclass 38, count 0 2006.224.07:46:30.20#ibcon#flushed, iclass 38, count 0 2006.224.07:46:30.20#ibcon#about to write, iclass 38, count 0 2006.224.07:46:30.20#ibcon#wrote, iclass 38, count 0 2006.224.07:46:30.20#ibcon#about to read 3, iclass 38, count 0 2006.224.07:46:30.22#ibcon#read 3, iclass 38, count 0 2006.224.07:46:30.22#ibcon#about to read 4, iclass 38, count 0 2006.224.07:46:30.22#ibcon#read 4, iclass 38, count 0 2006.224.07:46:30.22#ibcon#about to read 5, iclass 38, count 0 2006.224.07:46:30.22#ibcon#read 5, iclass 38, count 0 2006.224.07:46:30.22#ibcon#about to read 6, iclass 38, count 0 2006.224.07:46:30.22#ibcon#read 6, iclass 38, count 0 2006.224.07:46:30.22#ibcon#end of sib2, iclass 38, count 0 2006.224.07:46:30.22#ibcon#*mode == 0, iclass 38, count 0 2006.224.07:46:30.22#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.224.07:46:30.22#ibcon#[26=FRQ=08,852.99\r\n] 2006.224.07:46:30.22#ibcon#*before write, iclass 38, count 0 2006.224.07:46:30.22#ibcon#enter sib2, iclass 38, count 0 2006.224.07:46:30.22#ibcon#flushed, iclass 38, count 0 2006.224.07:46:30.22#ibcon#about to write, iclass 38, count 0 2006.224.07:46:30.22#ibcon#wrote, iclass 38, count 0 2006.224.07:46:30.22#ibcon#about to read 3, iclass 38, count 0 2006.224.07:46:30.26#ibcon#read 3, iclass 38, count 0 2006.224.07:46:30.26#ibcon#about to read 4, iclass 38, count 0 2006.224.07:46:30.26#ibcon#read 4, iclass 38, count 0 2006.224.07:46:30.26#ibcon#about to read 5, iclass 38, count 0 2006.224.07:46:30.26#ibcon#read 5, iclass 38, count 0 2006.224.07:46:30.26#ibcon#about to read 6, iclass 38, count 0 2006.224.07:46:30.26#ibcon#read 6, iclass 38, count 0 2006.224.07:46:30.26#ibcon#end of sib2, iclass 38, count 0 2006.224.07:46:30.26#ibcon#*after write, iclass 38, count 0 2006.224.07:46:30.26#ibcon#*before return 0, iclass 38, count 0 2006.224.07:46:30.26#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.224.07:46:30.26#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.224.07:46:30.26#ibcon#about to clear, iclass 38 cls_cnt 0 2006.224.07:46:30.26#ibcon#cleared, iclass 38 cls_cnt 0 2006.224.07:46:30.26$vc4f8/va=8,7 2006.224.07:46:30.26#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.224.07:46:30.26#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.224.07:46:30.26#ibcon#ireg 11 cls_cnt 2 2006.224.07:46:30.26#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.224.07:46:30.32#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.224.07:46:30.32#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.224.07:46:30.32#ibcon#enter wrdev, iclass 40, count 2 2006.224.07:46:30.32#ibcon#first serial, iclass 40, count 2 2006.224.07:46:30.32#ibcon#enter sib2, iclass 40, count 2 2006.224.07:46:30.32#ibcon#flushed, iclass 40, count 2 2006.224.07:46:30.32#ibcon#about to write, iclass 40, count 2 2006.224.07:46:30.32#ibcon#wrote, iclass 40, count 2 2006.224.07:46:30.32#ibcon#about to read 3, iclass 40, count 2 2006.224.07:46:30.34#ibcon#read 3, iclass 40, count 2 2006.224.07:46:30.34#ibcon#about to read 4, iclass 40, count 2 2006.224.07:46:30.34#ibcon#read 4, iclass 40, count 2 2006.224.07:46:30.34#ibcon#about to read 5, iclass 40, count 2 2006.224.07:46:30.34#ibcon#read 5, iclass 40, count 2 2006.224.07:46:30.34#ibcon#about to read 6, iclass 40, count 2 2006.224.07:46:30.34#ibcon#read 6, iclass 40, count 2 2006.224.07:46:30.34#ibcon#end of sib2, iclass 40, count 2 2006.224.07:46:30.34#ibcon#*mode == 0, iclass 40, count 2 2006.224.07:46:30.34#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.224.07:46:30.34#ibcon#[25=AT08-07\r\n] 2006.224.07:46:30.34#ibcon#*before write, iclass 40, count 2 2006.224.07:46:30.34#ibcon#enter sib2, iclass 40, count 2 2006.224.07:46:30.34#ibcon#flushed, iclass 40, count 2 2006.224.07:46:30.34#ibcon#about to write, iclass 40, count 2 2006.224.07:46:30.34#ibcon#wrote, iclass 40, count 2 2006.224.07:46:30.34#ibcon#about to read 3, iclass 40, count 2 2006.224.07:46:30.37#ibcon#read 3, iclass 40, count 2 2006.224.07:46:30.37#ibcon#about to read 4, iclass 40, count 2 2006.224.07:46:30.37#ibcon#read 4, iclass 40, count 2 2006.224.07:46:30.37#ibcon#about to read 5, iclass 40, count 2 2006.224.07:46:30.37#ibcon#read 5, iclass 40, count 2 2006.224.07:46:30.37#ibcon#about to read 6, iclass 40, count 2 2006.224.07:46:30.37#ibcon#read 6, iclass 40, count 2 2006.224.07:46:30.37#ibcon#end of sib2, iclass 40, count 2 2006.224.07:46:30.37#ibcon#*after write, iclass 40, count 2 2006.224.07:46:30.37#ibcon#*before return 0, iclass 40, count 2 2006.224.07:46:30.37#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.224.07:46:30.37#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.224.07:46:30.37#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.224.07:46:30.37#ibcon#ireg 7 cls_cnt 0 2006.224.07:46:30.37#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.224.07:46:30.50#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.224.07:46:30.50#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.224.07:46:30.50#ibcon#enter wrdev, iclass 40, count 0 2006.224.07:46:30.50#ibcon#first serial, iclass 40, count 0 2006.224.07:46:30.50#ibcon#enter sib2, iclass 40, count 0 2006.224.07:46:30.50#ibcon#flushed, iclass 40, count 0 2006.224.07:46:30.50#ibcon#about to write, iclass 40, count 0 2006.224.07:46:30.50#ibcon#wrote, iclass 40, count 0 2006.224.07:46:30.50#ibcon#about to read 3, iclass 40, count 0 2006.224.07:46:30.51#ibcon#read 3, iclass 40, count 0 2006.224.07:46:30.51#ibcon#about to read 4, iclass 40, count 0 2006.224.07:46:30.51#ibcon#read 4, iclass 40, count 0 2006.224.07:46:30.51#ibcon#about to read 5, iclass 40, count 0 2006.224.07:46:30.51#ibcon#read 5, iclass 40, count 0 2006.224.07:46:30.51#ibcon#about to read 6, iclass 40, count 0 2006.224.07:46:30.51#ibcon#read 6, iclass 40, count 0 2006.224.07:46:30.51#ibcon#end of sib2, iclass 40, count 0 2006.224.07:46:30.51#ibcon#*mode == 0, iclass 40, count 0 2006.224.07:46:30.51#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.224.07:46:30.51#ibcon#[25=USB\r\n] 2006.224.07:46:30.51#ibcon#*before write, iclass 40, count 0 2006.224.07:46:30.51#ibcon#enter sib2, iclass 40, count 0 2006.224.07:46:30.51#ibcon#flushed, iclass 40, count 0 2006.224.07:46:30.51#ibcon#about to write, iclass 40, count 0 2006.224.07:46:30.51#ibcon#wrote, iclass 40, count 0 2006.224.07:46:30.51#ibcon#about to read 3, iclass 40, count 0 2006.224.07:46:30.54#ibcon#read 3, iclass 40, count 0 2006.224.07:46:30.54#ibcon#about to read 4, iclass 40, count 0 2006.224.07:46:30.54#ibcon#read 4, iclass 40, count 0 2006.224.07:46:30.54#ibcon#about to read 5, iclass 40, count 0 2006.224.07:46:30.54#ibcon#read 5, iclass 40, count 0 2006.224.07:46:30.54#ibcon#about to read 6, iclass 40, count 0 2006.224.07:46:30.54#ibcon#read 6, iclass 40, count 0 2006.224.07:46:30.54#ibcon#end of sib2, iclass 40, count 0 2006.224.07:46:30.54#ibcon#*after write, iclass 40, count 0 2006.224.07:46:30.54#ibcon#*before return 0, iclass 40, count 0 2006.224.07:46:30.54#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.224.07:46:30.54#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.224.07:46:30.54#ibcon#about to clear, iclass 40 cls_cnt 0 2006.224.07:46:30.54#ibcon#cleared, iclass 40 cls_cnt 0 2006.224.07:46:30.54$vc4f8/vblo=1,632.99 2006.224.07:46:30.54#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.224.07:46:30.54#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.224.07:46:30.54#ibcon#ireg 17 cls_cnt 0 2006.224.07:46:30.54#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.224.07:46:30.54#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.224.07:46:30.54#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.224.07:46:30.54#ibcon#enter wrdev, iclass 4, count 0 2006.224.07:46:30.54#ibcon#first serial, iclass 4, count 0 2006.224.07:46:30.54#ibcon#enter sib2, iclass 4, count 0 2006.224.07:46:30.54#ibcon#flushed, iclass 4, count 0 2006.224.07:46:30.54#ibcon#about to write, iclass 4, count 0 2006.224.07:46:30.54#ibcon#wrote, iclass 4, count 0 2006.224.07:46:30.54#ibcon#about to read 3, iclass 4, count 0 2006.224.07:46:30.56#ibcon#read 3, iclass 4, count 0 2006.224.07:46:30.56#ibcon#about to read 4, iclass 4, count 0 2006.224.07:46:30.56#ibcon#read 4, iclass 4, count 0 2006.224.07:46:30.56#ibcon#about to read 5, iclass 4, count 0 2006.224.07:46:30.56#ibcon#read 5, iclass 4, count 0 2006.224.07:46:30.56#ibcon#about to read 6, iclass 4, count 0 2006.224.07:46:30.56#ibcon#read 6, iclass 4, count 0 2006.224.07:46:30.56#ibcon#end of sib2, iclass 4, count 0 2006.224.07:46:30.56#ibcon#*mode == 0, iclass 4, count 0 2006.224.07:46:30.56#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.224.07:46:30.56#ibcon#[28=FRQ=01,632.99\r\n] 2006.224.07:46:30.56#ibcon#*before write, iclass 4, count 0 2006.224.07:46:30.56#ibcon#enter sib2, iclass 4, count 0 2006.224.07:46:30.56#ibcon#flushed, iclass 4, count 0 2006.224.07:46:30.56#ibcon#about to write, iclass 4, count 0 2006.224.07:46:30.56#ibcon#wrote, iclass 4, count 0 2006.224.07:46:30.56#ibcon#about to read 3, iclass 4, count 0 2006.224.07:46:30.60#ibcon#read 3, iclass 4, count 0 2006.224.07:46:30.60#ibcon#about to read 4, iclass 4, count 0 2006.224.07:46:30.60#ibcon#read 4, iclass 4, count 0 2006.224.07:46:30.60#ibcon#about to read 5, iclass 4, count 0 2006.224.07:46:30.60#ibcon#read 5, iclass 4, count 0 2006.224.07:46:30.60#ibcon#about to read 6, iclass 4, count 0 2006.224.07:46:30.60#ibcon#read 6, iclass 4, count 0 2006.224.07:46:30.60#ibcon#end of sib2, iclass 4, count 0 2006.224.07:46:30.60#ibcon#*after write, iclass 4, count 0 2006.224.07:46:30.60#ibcon#*before return 0, iclass 4, count 0 2006.224.07:46:30.60#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.224.07:46:30.60#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.224.07:46:30.60#ibcon#about to clear, iclass 4 cls_cnt 0 2006.224.07:46:30.60#ibcon#cleared, iclass 4 cls_cnt 0 2006.224.07:46:30.60$vc4f8/vb=1,4 2006.224.07:46:30.60#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.224.07:46:30.60#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.224.07:46:30.60#ibcon#ireg 11 cls_cnt 2 2006.224.07:46:30.60#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.224.07:46:30.60#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.224.07:46:30.60#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.224.07:46:30.60#ibcon#enter wrdev, iclass 6, count 2 2006.224.07:46:30.60#ibcon#first serial, iclass 6, count 2 2006.224.07:46:30.60#ibcon#enter sib2, iclass 6, count 2 2006.224.07:46:30.60#ibcon#flushed, iclass 6, count 2 2006.224.07:46:30.60#ibcon#about to write, iclass 6, count 2 2006.224.07:46:30.60#ibcon#wrote, iclass 6, count 2 2006.224.07:46:30.60#ibcon#about to read 3, iclass 6, count 2 2006.224.07:46:30.62#ibcon#read 3, iclass 6, count 2 2006.224.07:46:30.62#ibcon#about to read 4, iclass 6, count 2 2006.224.07:46:30.62#ibcon#read 4, iclass 6, count 2 2006.224.07:46:30.62#ibcon#about to read 5, iclass 6, count 2 2006.224.07:46:30.62#ibcon#read 5, iclass 6, count 2 2006.224.07:46:30.62#ibcon#about to read 6, iclass 6, count 2 2006.224.07:46:30.62#ibcon#read 6, iclass 6, count 2 2006.224.07:46:30.62#ibcon#end of sib2, iclass 6, count 2 2006.224.07:46:30.62#ibcon#*mode == 0, iclass 6, count 2 2006.224.07:46:30.62#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.224.07:46:30.62#ibcon#[27=AT01-04\r\n] 2006.224.07:46:30.62#ibcon#*before write, iclass 6, count 2 2006.224.07:46:30.62#ibcon#enter sib2, iclass 6, count 2 2006.224.07:46:30.62#ibcon#flushed, iclass 6, count 2 2006.224.07:46:30.62#ibcon#about to write, iclass 6, count 2 2006.224.07:46:30.62#ibcon#wrote, iclass 6, count 2 2006.224.07:46:30.62#ibcon#about to read 3, iclass 6, count 2 2006.224.07:46:30.65#ibcon#read 3, iclass 6, count 2 2006.224.07:46:30.65#ibcon#about to read 4, iclass 6, count 2 2006.224.07:46:30.65#ibcon#read 4, iclass 6, count 2 2006.224.07:46:30.65#ibcon#about to read 5, iclass 6, count 2 2006.224.07:46:30.65#ibcon#read 5, iclass 6, count 2 2006.224.07:46:30.65#ibcon#about to read 6, iclass 6, count 2 2006.224.07:46:30.65#ibcon#read 6, iclass 6, count 2 2006.224.07:46:30.65#ibcon#end of sib2, iclass 6, count 2 2006.224.07:46:30.65#ibcon#*after write, iclass 6, count 2 2006.224.07:46:30.65#ibcon#*before return 0, iclass 6, count 2 2006.224.07:46:30.65#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.224.07:46:30.65#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.224.07:46:30.65#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.224.07:46:30.65#ibcon#ireg 7 cls_cnt 0 2006.224.07:46:30.65#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.224.07:46:30.77#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.224.07:46:30.77#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.224.07:46:30.77#ibcon#enter wrdev, iclass 6, count 0 2006.224.07:46:30.77#ibcon#first serial, iclass 6, count 0 2006.224.07:46:30.77#ibcon#enter sib2, iclass 6, count 0 2006.224.07:46:30.77#ibcon#flushed, iclass 6, count 0 2006.224.07:46:30.77#ibcon#about to write, iclass 6, count 0 2006.224.07:46:30.77#ibcon#wrote, iclass 6, count 0 2006.224.07:46:30.77#ibcon#about to read 3, iclass 6, count 0 2006.224.07:46:30.79#ibcon#read 3, iclass 6, count 0 2006.224.07:46:30.79#ibcon#about to read 4, iclass 6, count 0 2006.224.07:46:30.79#ibcon#read 4, iclass 6, count 0 2006.224.07:46:30.79#ibcon#about to read 5, iclass 6, count 0 2006.224.07:46:30.79#ibcon#read 5, iclass 6, count 0 2006.224.07:46:30.79#ibcon#about to read 6, iclass 6, count 0 2006.224.07:46:30.79#ibcon#read 6, iclass 6, count 0 2006.224.07:46:30.79#ibcon#end of sib2, iclass 6, count 0 2006.224.07:46:30.79#ibcon#*mode == 0, iclass 6, count 0 2006.224.07:46:30.79#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.224.07:46:30.79#ibcon#[27=USB\r\n] 2006.224.07:46:30.79#ibcon#*before write, iclass 6, count 0 2006.224.07:46:30.79#ibcon#enter sib2, iclass 6, count 0 2006.224.07:46:30.79#ibcon#flushed, iclass 6, count 0 2006.224.07:46:30.79#ibcon#about to write, iclass 6, count 0 2006.224.07:46:30.79#ibcon#wrote, iclass 6, count 0 2006.224.07:46:30.79#ibcon#about to read 3, iclass 6, count 0 2006.224.07:46:30.82#ibcon#read 3, iclass 6, count 0 2006.224.07:46:30.82#ibcon#about to read 4, iclass 6, count 0 2006.224.07:46:30.82#ibcon#read 4, iclass 6, count 0 2006.224.07:46:30.82#ibcon#about to read 5, iclass 6, count 0 2006.224.07:46:30.82#ibcon#read 5, iclass 6, count 0 2006.224.07:46:30.82#ibcon#about to read 6, iclass 6, count 0 2006.224.07:46:30.82#ibcon#read 6, iclass 6, count 0 2006.224.07:46:30.82#ibcon#end of sib2, iclass 6, count 0 2006.224.07:46:30.82#ibcon#*after write, iclass 6, count 0 2006.224.07:46:30.82#ibcon#*before return 0, iclass 6, count 0 2006.224.07:46:30.82#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.224.07:46:30.82#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.224.07:46:30.82#ibcon#about to clear, iclass 6 cls_cnt 0 2006.224.07:46:30.82#ibcon#cleared, iclass 6 cls_cnt 0 2006.224.07:46:30.82$vc4f8/vblo=2,640.99 2006.224.07:46:30.82#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.224.07:46:30.82#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.224.07:46:30.82#ibcon#ireg 17 cls_cnt 0 2006.224.07:46:30.82#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.224.07:46:30.82#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.224.07:46:30.82#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.224.07:46:30.82#ibcon#enter wrdev, iclass 10, count 0 2006.224.07:46:30.82#ibcon#first serial, iclass 10, count 0 2006.224.07:46:30.82#ibcon#enter sib2, iclass 10, count 0 2006.224.07:46:30.82#ibcon#flushed, iclass 10, count 0 2006.224.07:46:30.82#ibcon#about to write, iclass 10, count 0 2006.224.07:46:30.82#ibcon#wrote, iclass 10, count 0 2006.224.07:46:30.82#ibcon#about to read 3, iclass 10, count 0 2006.224.07:46:30.84#ibcon#read 3, iclass 10, count 0 2006.224.07:46:30.84#ibcon#about to read 4, iclass 10, count 0 2006.224.07:46:30.84#ibcon#read 4, iclass 10, count 0 2006.224.07:46:30.84#ibcon#about to read 5, iclass 10, count 0 2006.224.07:46:30.84#ibcon#read 5, iclass 10, count 0 2006.224.07:46:30.84#ibcon#about to read 6, iclass 10, count 0 2006.224.07:46:30.84#ibcon#read 6, iclass 10, count 0 2006.224.07:46:30.84#ibcon#end of sib2, iclass 10, count 0 2006.224.07:46:30.84#ibcon#*mode == 0, iclass 10, count 0 2006.224.07:46:30.84#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.224.07:46:30.84#ibcon#[28=FRQ=02,640.99\r\n] 2006.224.07:46:30.84#ibcon#*before write, iclass 10, count 0 2006.224.07:46:30.84#ibcon#enter sib2, iclass 10, count 0 2006.224.07:46:30.84#ibcon#flushed, iclass 10, count 0 2006.224.07:46:30.84#ibcon#about to write, iclass 10, count 0 2006.224.07:46:30.84#ibcon#wrote, iclass 10, count 0 2006.224.07:46:30.84#ibcon#about to read 3, iclass 10, count 0 2006.224.07:46:30.88#ibcon#read 3, iclass 10, count 0 2006.224.07:46:30.88#ibcon#about to read 4, iclass 10, count 0 2006.224.07:46:30.88#ibcon#read 4, iclass 10, count 0 2006.224.07:46:30.88#ibcon#about to read 5, iclass 10, count 0 2006.224.07:46:30.88#ibcon#read 5, iclass 10, count 0 2006.224.07:46:30.88#ibcon#about to read 6, iclass 10, count 0 2006.224.07:46:30.88#ibcon#read 6, iclass 10, count 0 2006.224.07:46:30.88#ibcon#end of sib2, iclass 10, count 0 2006.224.07:46:30.88#ibcon#*after write, iclass 10, count 0 2006.224.07:46:30.88#ibcon#*before return 0, iclass 10, count 0 2006.224.07:46:30.88#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.224.07:46:30.88#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.224.07:46:30.88#ibcon#about to clear, iclass 10 cls_cnt 0 2006.224.07:46:30.88#ibcon#cleared, iclass 10 cls_cnt 0 2006.224.07:46:30.88$vc4f8/vb=2,4 2006.224.07:46:30.88#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.224.07:46:30.88#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.224.07:46:30.88#ibcon#ireg 11 cls_cnt 2 2006.224.07:46:30.88#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.224.07:46:30.94#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.224.07:46:30.94#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.224.07:46:30.94#ibcon#enter wrdev, iclass 12, count 2 2006.224.07:46:30.94#ibcon#first serial, iclass 12, count 2 2006.224.07:46:30.94#ibcon#enter sib2, iclass 12, count 2 2006.224.07:46:30.94#ibcon#flushed, iclass 12, count 2 2006.224.07:46:30.94#ibcon#about to write, iclass 12, count 2 2006.224.07:46:30.94#ibcon#wrote, iclass 12, count 2 2006.224.07:46:30.94#ibcon#about to read 3, iclass 12, count 2 2006.224.07:46:30.96#ibcon#read 3, iclass 12, count 2 2006.224.07:46:30.96#ibcon#about to read 4, iclass 12, count 2 2006.224.07:46:30.96#ibcon#read 4, iclass 12, count 2 2006.224.07:46:30.96#ibcon#about to read 5, iclass 12, count 2 2006.224.07:46:30.96#ibcon#read 5, iclass 12, count 2 2006.224.07:46:30.96#ibcon#about to read 6, iclass 12, count 2 2006.224.07:46:30.96#ibcon#read 6, iclass 12, count 2 2006.224.07:46:30.96#ibcon#end of sib2, iclass 12, count 2 2006.224.07:46:30.96#ibcon#*mode == 0, iclass 12, count 2 2006.224.07:46:30.96#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.224.07:46:30.96#ibcon#[27=AT02-04\r\n] 2006.224.07:46:30.96#ibcon#*before write, iclass 12, count 2 2006.224.07:46:30.96#ibcon#enter sib2, iclass 12, count 2 2006.224.07:46:30.96#ibcon#flushed, iclass 12, count 2 2006.224.07:46:30.96#ibcon#about to write, iclass 12, count 2 2006.224.07:46:30.96#ibcon#wrote, iclass 12, count 2 2006.224.07:46:30.96#ibcon#about to read 3, iclass 12, count 2 2006.224.07:46:30.99#ibcon#read 3, iclass 12, count 2 2006.224.07:46:30.99#ibcon#about to read 4, iclass 12, count 2 2006.224.07:46:30.99#ibcon#read 4, iclass 12, count 2 2006.224.07:46:30.99#ibcon#about to read 5, iclass 12, count 2 2006.224.07:46:30.99#ibcon#read 5, iclass 12, count 2 2006.224.07:46:30.99#ibcon#about to read 6, iclass 12, count 2 2006.224.07:46:30.99#ibcon#read 6, iclass 12, count 2 2006.224.07:46:30.99#ibcon#end of sib2, iclass 12, count 2 2006.224.07:46:30.99#ibcon#*after write, iclass 12, count 2 2006.224.07:46:30.99#ibcon#*before return 0, iclass 12, count 2 2006.224.07:46:30.99#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.224.07:46:30.99#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.224.07:46:30.99#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.224.07:46:30.99#ibcon#ireg 7 cls_cnt 0 2006.224.07:46:30.99#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.224.07:46:31.11#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.224.07:46:31.11#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.224.07:46:31.11#ibcon#enter wrdev, iclass 12, count 0 2006.224.07:46:31.11#ibcon#first serial, iclass 12, count 0 2006.224.07:46:31.11#ibcon#enter sib2, iclass 12, count 0 2006.224.07:46:31.11#ibcon#flushed, iclass 12, count 0 2006.224.07:46:31.11#ibcon#about to write, iclass 12, count 0 2006.224.07:46:31.11#ibcon#wrote, iclass 12, count 0 2006.224.07:46:31.11#ibcon#about to read 3, iclass 12, count 0 2006.224.07:46:31.13#ibcon#read 3, iclass 12, count 0 2006.224.07:46:31.13#ibcon#about to read 4, iclass 12, count 0 2006.224.07:46:31.13#ibcon#read 4, iclass 12, count 0 2006.224.07:46:31.13#ibcon#about to read 5, iclass 12, count 0 2006.224.07:46:31.13#ibcon#read 5, iclass 12, count 0 2006.224.07:46:31.13#ibcon#about to read 6, iclass 12, count 0 2006.224.07:46:31.13#ibcon#read 6, iclass 12, count 0 2006.224.07:46:31.13#ibcon#end of sib2, iclass 12, count 0 2006.224.07:46:31.13#ibcon#*mode == 0, iclass 12, count 0 2006.224.07:46:31.13#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.224.07:46:31.13#ibcon#[27=USB\r\n] 2006.224.07:46:31.13#ibcon#*before write, iclass 12, count 0 2006.224.07:46:31.13#ibcon#enter sib2, iclass 12, count 0 2006.224.07:46:31.13#ibcon#flushed, iclass 12, count 0 2006.224.07:46:31.13#ibcon#about to write, iclass 12, count 0 2006.224.07:46:31.13#ibcon#wrote, iclass 12, count 0 2006.224.07:46:31.13#ibcon#about to read 3, iclass 12, count 0 2006.224.07:46:31.16#ibcon#read 3, iclass 12, count 0 2006.224.07:46:31.16#ibcon#about to read 4, iclass 12, count 0 2006.224.07:46:31.16#ibcon#read 4, iclass 12, count 0 2006.224.07:46:31.16#ibcon#about to read 5, iclass 12, count 0 2006.224.07:46:31.16#ibcon#read 5, iclass 12, count 0 2006.224.07:46:31.16#ibcon#about to read 6, iclass 12, count 0 2006.224.07:46:31.16#ibcon#read 6, iclass 12, count 0 2006.224.07:46:31.16#ibcon#end of sib2, iclass 12, count 0 2006.224.07:46:31.16#ibcon#*after write, iclass 12, count 0 2006.224.07:46:31.16#ibcon#*before return 0, iclass 12, count 0 2006.224.07:46:31.16#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.224.07:46:31.16#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.224.07:46:31.16#ibcon#about to clear, iclass 12 cls_cnt 0 2006.224.07:46:31.16#ibcon#cleared, iclass 12 cls_cnt 0 2006.224.07:46:31.16$vc4f8/vblo=3,656.99 2006.224.07:46:31.16#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.224.07:46:31.16#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.224.07:46:31.16#ibcon#ireg 17 cls_cnt 0 2006.224.07:46:31.16#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.224.07:46:31.16#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.224.07:46:31.16#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.224.07:46:31.16#ibcon#enter wrdev, iclass 14, count 0 2006.224.07:46:31.16#ibcon#first serial, iclass 14, count 0 2006.224.07:46:31.16#ibcon#enter sib2, iclass 14, count 0 2006.224.07:46:31.16#ibcon#flushed, iclass 14, count 0 2006.224.07:46:31.16#ibcon#about to write, iclass 14, count 0 2006.224.07:46:31.16#ibcon#wrote, iclass 14, count 0 2006.224.07:46:31.16#ibcon#about to read 3, iclass 14, count 0 2006.224.07:46:31.18#ibcon#read 3, iclass 14, count 0 2006.224.07:46:31.18#ibcon#about to read 4, iclass 14, count 0 2006.224.07:46:31.18#ibcon#read 4, iclass 14, count 0 2006.224.07:46:31.18#ibcon#about to read 5, iclass 14, count 0 2006.224.07:46:31.18#ibcon#read 5, iclass 14, count 0 2006.224.07:46:31.18#ibcon#about to read 6, iclass 14, count 0 2006.224.07:46:31.18#ibcon#read 6, iclass 14, count 0 2006.224.07:46:31.18#ibcon#end of sib2, iclass 14, count 0 2006.224.07:46:31.18#ibcon#*mode == 0, iclass 14, count 0 2006.224.07:46:31.18#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.224.07:46:31.18#ibcon#[28=FRQ=03,656.99\r\n] 2006.224.07:46:31.18#ibcon#*before write, iclass 14, count 0 2006.224.07:46:31.18#ibcon#enter sib2, iclass 14, count 0 2006.224.07:46:31.18#ibcon#flushed, iclass 14, count 0 2006.224.07:46:31.18#ibcon#about to write, iclass 14, count 0 2006.224.07:46:31.18#ibcon#wrote, iclass 14, count 0 2006.224.07:46:31.18#ibcon#about to read 3, iclass 14, count 0 2006.224.07:46:31.22#ibcon#read 3, iclass 14, count 0 2006.224.07:46:31.22#ibcon#about to read 4, iclass 14, count 0 2006.224.07:46:31.22#ibcon#read 4, iclass 14, count 0 2006.224.07:46:31.22#ibcon#about to read 5, iclass 14, count 0 2006.224.07:46:31.22#ibcon#read 5, iclass 14, count 0 2006.224.07:46:31.22#ibcon#about to read 6, iclass 14, count 0 2006.224.07:46:31.22#ibcon#read 6, iclass 14, count 0 2006.224.07:46:31.22#ibcon#end of sib2, iclass 14, count 0 2006.224.07:46:31.22#ibcon#*after write, iclass 14, count 0 2006.224.07:46:31.22#ibcon#*before return 0, iclass 14, count 0 2006.224.07:46:31.22#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.224.07:46:31.22#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.224.07:46:31.22#ibcon#about to clear, iclass 14 cls_cnt 0 2006.224.07:46:31.22#ibcon#cleared, iclass 14 cls_cnt 0 2006.224.07:46:31.22$vc4f8/vb=3,4 2006.224.07:46:31.22#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.224.07:46:31.22#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.224.07:46:31.22#ibcon#ireg 11 cls_cnt 2 2006.224.07:46:31.22#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.224.07:46:31.29#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.224.07:46:31.29#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.224.07:46:31.29#ibcon#enter wrdev, iclass 16, count 2 2006.224.07:46:31.29#ibcon#first serial, iclass 16, count 2 2006.224.07:46:31.29#ibcon#enter sib2, iclass 16, count 2 2006.224.07:46:31.29#ibcon#flushed, iclass 16, count 2 2006.224.07:46:31.29#ibcon#about to write, iclass 16, count 2 2006.224.07:46:31.29#ibcon#wrote, iclass 16, count 2 2006.224.07:46:31.29#ibcon#about to read 3, iclass 16, count 2 2006.224.07:46:31.30#ibcon#read 3, iclass 16, count 2 2006.224.07:46:31.30#ibcon#about to read 4, iclass 16, count 2 2006.224.07:46:31.30#ibcon#read 4, iclass 16, count 2 2006.224.07:46:31.30#ibcon#about to read 5, iclass 16, count 2 2006.224.07:46:31.30#ibcon#read 5, iclass 16, count 2 2006.224.07:46:31.30#ibcon#about to read 6, iclass 16, count 2 2006.224.07:46:31.30#ibcon#read 6, iclass 16, count 2 2006.224.07:46:31.30#ibcon#end of sib2, iclass 16, count 2 2006.224.07:46:31.30#ibcon#*mode == 0, iclass 16, count 2 2006.224.07:46:31.30#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.224.07:46:31.30#ibcon#[27=AT03-04\r\n] 2006.224.07:46:31.30#ibcon#*before write, iclass 16, count 2 2006.224.07:46:31.30#ibcon#enter sib2, iclass 16, count 2 2006.224.07:46:31.30#ibcon#flushed, iclass 16, count 2 2006.224.07:46:31.30#ibcon#about to write, iclass 16, count 2 2006.224.07:46:31.30#ibcon#wrote, iclass 16, count 2 2006.224.07:46:31.30#ibcon#about to read 3, iclass 16, count 2 2006.224.07:46:31.33#ibcon#read 3, iclass 16, count 2 2006.224.07:46:31.33#ibcon#about to read 4, iclass 16, count 2 2006.224.07:46:31.33#ibcon#read 4, iclass 16, count 2 2006.224.07:46:31.33#ibcon#about to read 5, iclass 16, count 2 2006.224.07:46:31.33#ibcon#read 5, iclass 16, count 2 2006.224.07:46:31.33#ibcon#about to read 6, iclass 16, count 2 2006.224.07:46:31.33#ibcon#read 6, iclass 16, count 2 2006.224.07:46:31.33#ibcon#end of sib2, iclass 16, count 2 2006.224.07:46:31.33#ibcon#*after write, iclass 16, count 2 2006.224.07:46:31.33#ibcon#*before return 0, iclass 16, count 2 2006.224.07:46:31.33#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.224.07:46:31.33#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.224.07:46:31.33#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.224.07:46:31.33#ibcon#ireg 7 cls_cnt 0 2006.224.07:46:31.33#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.224.07:46:31.45#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.224.07:46:31.45#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.224.07:46:31.45#ibcon#enter wrdev, iclass 16, count 0 2006.224.07:46:31.45#ibcon#first serial, iclass 16, count 0 2006.224.07:46:31.45#ibcon#enter sib2, iclass 16, count 0 2006.224.07:46:31.45#ibcon#flushed, iclass 16, count 0 2006.224.07:46:31.45#ibcon#about to write, iclass 16, count 0 2006.224.07:46:31.45#ibcon#wrote, iclass 16, count 0 2006.224.07:46:31.45#ibcon#about to read 3, iclass 16, count 0 2006.224.07:46:31.47#ibcon#read 3, iclass 16, count 0 2006.224.07:46:31.47#ibcon#about to read 4, iclass 16, count 0 2006.224.07:46:31.47#ibcon#read 4, iclass 16, count 0 2006.224.07:46:31.47#ibcon#about to read 5, iclass 16, count 0 2006.224.07:46:31.47#ibcon#read 5, iclass 16, count 0 2006.224.07:46:31.47#ibcon#about to read 6, iclass 16, count 0 2006.224.07:46:31.47#ibcon#read 6, iclass 16, count 0 2006.224.07:46:31.47#ibcon#end of sib2, iclass 16, count 0 2006.224.07:46:31.47#ibcon#*mode == 0, iclass 16, count 0 2006.224.07:46:31.47#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.224.07:46:31.47#ibcon#[27=USB\r\n] 2006.224.07:46:31.47#ibcon#*before write, iclass 16, count 0 2006.224.07:46:31.47#ibcon#enter sib2, iclass 16, count 0 2006.224.07:46:31.47#ibcon#flushed, iclass 16, count 0 2006.224.07:46:31.47#ibcon#about to write, iclass 16, count 0 2006.224.07:46:31.47#ibcon#wrote, iclass 16, count 0 2006.224.07:46:31.47#ibcon#about to read 3, iclass 16, count 0 2006.224.07:46:31.50#ibcon#read 3, iclass 16, count 0 2006.224.07:46:31.50#ibcon#about to read 4, iclass 16, count 0 2006.224.07:46:31.50#ibcon#read 4, iclass 16, count 0 2006.224.07:46:31.50#ibcon#about to read 5, iclass 16, count 0 2006.224.07:46:31.50#ibcon#read 5, iclass 16, count 0 2006.224.07:46:31.50#ibcon#about to read 6, iclass 16, count 0 2006.224.07:46:31.50#ibcon#read 6, iclass 16, count 0 2006.224.07:46:31.50#ibcon#end of sib2, iclass 16, count 0 2006.224.07:46:31.50#ibcon#*after write, iclass 16, count 0 2006.224.07:46:31.50#ibcon#*before return 0, iclass 16, count 0 2006.224.07:46:31.50#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.224.07:46:31.50#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.224.07:46:31.50#ibcon#about to clear, iclass 16 cls_cnt 0 2006.224.07:46:31.50#ibcon#cleared, iclass 16 cls_cnt 0 2006.224.07:46:31.50$vc4f8/vblo=4,712.99 2006.224.07:46:31.50#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.224.07:46:31.50#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.224.07:46:31.50#ibcon#ireg 17 cls_cnt 0 2006.224.07:46:31.50#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.224.07:46:31.50#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.224.07:46:31.50#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.224.07:46:31.50#ibcon#enter wrdev, iclass 18, count 0 2006.224.07:46:31.50#ibcon#first serial, iclass 18, count 0 2006.224.07:46:31.50#ibcon#enter sib2, iclass 18, count 0 2006.224.07:46:31.50#ibcon#flushed, iclass 18, count 0 2006.224.07:46:31.50#ibcon#about to write, iclass 18, count 0 2006.224.07:46:31.50#ibcon#wrote, iclass 18, count 0 2006.224.07:46:31.50#ibcon#about to read 3, iclass 18, count 0 2006.224.07:46:31.52#ibcon#read 3, iclass 18, count 0 2006.224.07:46:31.52#ibcon#about to read 4, iclass 18, count 0 2006.224.07:46:31.52#ibcon#read 4, iclass 18, count 0 2006.224.07:46:31.52#ibcon#about to read 5, iclass 18, count 0 2006.224.07:46:31.52#ibcon#read 5, iclass 18, count 0 2006.224.07:46:31.52#ibcon#about to read 6, iclass 18, count 0 2006.224.07:46:31.52#ibcon#read 6, iclass 18, count 0 2006.224.07:46:31.52#ibcon#end of sib2, iclass 18, count 0 2006.224.07:46:31.52#ibcon#*mode == 0, iclass 18, count 0 2006.224.07:46:31.52#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.224.07:46:31.52#ibcon#[28=FRQ=04,712.99\r\n] 2006.224.07:46:31.52#ibcon#*before write, iclass 18, count 0 2006.224.07:46:31.52#ibcon#enter sib2, iclass 18, count 0 2006.224.07:46:31.52#ibcon#flushed, iclass 18, count 0 2006.224.07:46:31.52#ibcon#about to write, iclass 18, count 0 2006.224.07:46:31.52#ibcon#wrote, iclass 18, count 0 2006.224.07:46:31.52#ibcon#about to read 3, iclass 18, count 0 2006.224.07:46:31.56#ibcon#read 3, iclass 18, count 0 2006.224.07:46:31.56#ibcon#about to read 4, iclass 18, count 0 2006.224.07:46:31.56#ibcon#read 4, iclass 18, count 0 2006.224.07:46:31.56#ibcon#about to read 5, iclass 18, count 0 2006.224.07:46:31.56#ibcon#read 5, iclass 18, count 0 2006.224.07:46:31.56#ibcon#about to read 6, iclass 18, count 0 2006.224.07:46:31.56#ibcon#read 6, iclass 18, count 0 2006.224.07:46:31.56#ibcon#end of sib2, iclass 18, count 0 2006.224.07:46:31.56#ibcon#*after write, iclass 18, count 0 2006.224.07:46:31.56#ibcon#*before return 0, iclass 18, count 0 2006.224.07:46:31.56#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.224.07:46:31.56#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.224.07:46:31.56#ibcon#about to clear, iclass 18 cls_cnt 0 2006.224.07:46:31.56#ibcon#cleared, iclass 18 cls_cnt 0 2006.224.07:46:31.56$vc4f8/vb=4,4 2006.224.07:46:31.56#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.224.07:46:31.56#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.224.07:46:31.56#ibcon#ireg 11 cls_cnt 2 2006.224.07:46:31.56#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.224.07:46:31.62#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.224.07:46:31.62#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.224.07:46:31.62#ibcon#enter wrdev, iclass 20, count 2 2006.224.07:46:31.62#ibcon#first serial, iclass 20, count 2 2006.224.07:46:31.62#ibcon#enter sib2, iclass 20, count 2 2006.224.07:46:31.62#ibcon#flushed, iclass 20, count 2 2006.224.07:46:31.62#ibcon#about to write, iclass 20, count 2 2006.224.07:46:31.62#ibcon#wrote, iclass 20, count 2 2006.224.07:46:31.62#ibcon#about to read 3, iclass 20, count 2 2006.224.07:46:31.64#ibcon#read 3, iclass 20, count 2 2006.224.07:46:31.64#ibcon#about to read 4, iclass 20, count 2 2006.224.07:46:31.64#ibcon#read 4, iclass 20, count 2 2006.224.07:46:31.64#ibcon#about to read 5, iclass 20, count 2 2006.224.07:46:31.64#ibcon#read 5, iclass 20, count 2 2006.224.07:46:31.64#ibcon#about to read 6, iclass 20, count 2 2006.224.07:46:31.64#ibcon#read 6, iclass 20, count 2 2006.224.07:46:31.64#ibcon#end of sib2, iclass 20, count 2 2006.224.07:46:31.64#ibcon#*mode == 0, iclass 20, count 2 2006.224.07:46:31.64#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.224.07:46:31.64#ibcon#[27=AT04-04\r\n] 2006.224.07:46:31.64#ibcon#*before write, iclass 20, count 2 2006.224.07:46:31.64#ibcon#enter sib2, iclass 20, count 2 2006.224.07:46:31.64#ibcon#flushed, iclass 20, count 2 2006.224.07:46:31.64#ibcon#about to write, iclass 20, count 2 2006.224.07:46:31.64#ibcon#wrote, iclass 20, count 2 2006.224.07:46:31.64#ibcon#about to read 3, iclass 20, count 2 2006.224.07:46:31.67#ibcon#read 3, iclass 20, count 2 2006.224.07:46:31.67#ibcon#about to read 4, iclass 20, count 2 2006.224.07:46:31.67#ibcon#read 4, iclass 20, count 2 2006.224.07:46:31.67#ibcon#about to read 5, iclass 20, count 2 2006.224.07:46:31.67#ibcon#read 5, iclass 20, count 2 2006.224.07:46:31.67#ibcon#about to read 6, iclass 20, count 2 2006.224.07:46:31.67#ibcon#read 6, iclass 20, count 2 2006.224.07:46:31.67#ibcon#end of sib2, iclass 20, count 2 2006.224.07:46:31.67#ibcon#*after write, iclass 20, count 2 2006.224.07:46:31.67#ibcon#*before return 0, iclass 20, count 2 2006.224.07:46:31.67#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.224.07:46:31.67#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.224.07:46:31.67#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.224.07:46:31.67#ibcon#ireg 7 cls_cnt 0 2006.224.07:46:31.67#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.224.07:46:31.79#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.224.07:46:31.79#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.224.07:46:31.79#ibcon#enter wrdev, iclass 20, count 0 2006.224.07:46:31.79#ibcon#first serial, iclass 20, count 0 2006.224.07:46:31.79#ibcon#enter sib2, iclass 20, count 0 2006.224.07:46:31.79#ibcon#flushed, iclass 20, count 0 2006.224.07:46:31.79#ibcon#about to write, iclass 20, count 0 2006.224.07:46:31.79#ibcon#wrote, iclass 20, count 0 2006.224.07:46:31.79#ibcon#about to read 3, iclass 20, count 0 2006.224.07:46:31.81#ibcon#read 3, iclass 20, count 0 2006.224.07:46:31.81#ibcon#about to read 4, iclass 20, count 0 2006.224.07:46:31.81#ibcon#read 4, iclass 20, count 0 2006.224.07:46:31.81#ibcon#about to read 5, iclass 20, count 0 2006.224.07:46:31.81#ibcon#read 5, iclass 20, count 0 2006.224.07:46:31.81#ibcon#about to read 6, iclass 20, count 0 2006.224.07:46:31.81#ibcon#read 6, iclass 20, count 0 2006.224.07:46:31.81#ibcon#end of sib2, iclass 20, count 0 2006.224.07:46:31.81#ibcon#*mode == 0, iclass 20, count 0 2006.224.07:46:31.81#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.224.07:46:31.81#ibcon#[27=USB\r\n] 2006.224.07:46:31.81#ibcon#*before write, iclass 20, count 0 2006.224.07:46:31.81#ibcon#enter sib2, iclass 20, count 0 2006.224.07:46:31.81#ibcon#flushed, iclass 20, count 0 2006.224.07:46:31.81#ibcon#about to write, iclass 20, count 0 2006.224.07:46:31.81#ibcon#wrote, iclass 20, count 0 2006.224.07:46:31.81#ibcon#about to read 3, iclass 20, count 0 2006.224.07:46:31.84#ibcon#read 3, iclass 20, count 0 2006.224.07:46:31.84#ibcon#about to read 4, iclass 20, count 0 2006.224.07:46:31.84#ibcon#read 4, iclass 20, count 0 2006.224.07:46:31.84#ibcon#about to read 5, iclass 20, count 0 2006.224.07:46:31.84#ibcon#read 5, iclass 20, count 0 2006.224.07:46:31.84#ibcon#about to read 6, iclass 20, count 0 2006.224.07:46:31.84#ibcon#read 6, iclass 20, count 0 2006.224.07:46:31.84#ibcon#end of sib2, iclass 20, count 0 2006.224.07:46:31.84#ibcon#*after write, iclass 20, count 0 2006.224.07:46:31.84#ibcon#*before return 0, iclass 20, count 0 2006.224.07:46:31.84#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.224.07:46:31.84#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.224.07:46:31.84#ibcon#about to clear, iclass 20 cls_cnt 0 2006.224.07:46:31.84#ibcon#cleared, iclass 20 cls_cnt 0 2006.224.07:46:31.84$vc4f8/vblo=5,744.99 2006.224.07:46:31.84#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.224.07:46:31.84#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.224.07:46:31.84#ibcon#ireg 17 cls_cnt 0 2006.224.07:46:31.84#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.224.07:46:31.84#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.224.07:46:31.84#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.224.07:46:31.84#ibcon#enter wrdev, iclass 22, count 0 2006.224.07:46:31.84#ibcon#first serial, iclass 22, count 0 2006.224.07:46:31.84#ibcon#enter sib2, iclass 22, count 0 2006.224.07:46:31.84#ibcon#flushed, iclass 22, count 0 2006.224.07:46:31.84#ibcon#about to write, iclass 22, count 0 2006.224.07:46:31.84#ibcon#wrote, iclass 22, count 0 2006.224.07:46:31.84#ibcon#about to read 3, iclass 22, count 0 2006.224.07:46:31.86#ibcon#read 3, iclass 22, count 0 2006.224.07:46:31.86#ibcon#about to read 4, iclass 22, count 0 2006.224.07:46:31.86#ibcon#read 4, iclass 22, count 0 2006.224.07:46:31.86#ibcon#about to read 5, iclass 22, count 0 2006.224.07:46:31.86#ibcon#read 5, iclass 22, count 0 2006.224.07:46:31.86#ibcon#about to read 6, iclass 22, count 0 2006.224.07:46:31.86#ibcon#read 6, iclass 22, count 0 2006.224.07:46:31.86#ibcon#end of sib2, iclass 22, count 0 2006.224.07:46:31.86#ibcon#*mode == 0, iclass 22, count 0 2006.224.07:46:31.86#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.224.07:46:31.86#ibcon#[28=FRQ=05,744.99\r\n] 2006.224.07:46:31.86#ibcon#*before write, iclass 22, count 0 2006.224.07:46:31.86#ibcon#enter sib2, iclass 22, count 0 2006.224.07:46:31.86#ibcon#flushed, iclass 22, count 0 2006.224.07:46:31.86#ibcon#about to write, iclass 22, count 0 2006.224.07:46:31.86#ibcon#wrote, iclass 22, count 0 2006.224.07:46:31.86#ibcon#about to read 3, iclass 22, count 0 2006.224.07:46:31.90#ibcon#read 3, iclass 22, count 0 2006.224.07:46:31.90#ibcon#about to read 4, iclass 22, count 0 2006.224.07:46:31.90#ibcon#read 4, iclass 22, count 0 2006.224.07:46:31.90#ibcon#about to read 5, iclass 22, count 0 2006.224.07:46:31.90#ibcon#read 5, iclass 22, count 0 2006.224.07:46:31.90#ibcon#about to read 6, iclass 22, count 0 2006.224.07:46:31.90#ibcon#read 6, iclass 22, count 0 2006.224.07:46:31.90#ibcon#end of sib2, iclass 22, count 0 2006.224.07:46:31.90#ibcon#*after write, iclass 22, count 0 2006.224.07:46:31.90#ibcon#*before return 0, iclass 22, count 0 2006.224.07:46:31.90#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.224.07:46:31.90#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.224.07:46:31.90#ibcon#about to clear, iclass 22 cls_cnt 0 2006.224.07:46:31.90#ibcon#cleared, iclass 22 cls_cnt 0 2006.224.07:46:31.90$vc4f8/vb=5,4 2006.224.07:46:31.90#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.224.07:46:31.90#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.224.07:46:31.90#ibcon#ireg 11 cls_cnt 2 2006.224.07:46:31.90#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.224.07:46:31.96#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.224.07:46:31.96#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.224.07:46:31.96#ibcon#enter wrdev, iclass 24, count 2 2006.224.07:46:31.96#ibcon#first serial, iclass 24, count 2 2006.224.07:46:31.96#ibcon#enter sib2, iclass 24, count 2 2006.224.07:46:31.96#ibcon#flushed, iclass 24, count 2 2006.224.07:46:31.96#ibcon#about to write, iclass 24, count 2 2006.224.07:46:31.96#ibcon#wrote, iclass 24, count 2 2006.224.07:46:31.96#ibcon#about to read 3, iclass 24, count 2 2006.224.07:46:31.98#ibcon#read 3, iclass 24, count 2 2006.224.07:46:31.98#ibcon#about to read 4, iclass 24, count 2 2006.224.07:46:31.98#ibcon#read 4, iclass 24, count 2 2006.224.07:46:31.98#ibcon#about to read 5, iclass 24, count 2 2006.224.07:46:31.98#ibcon#read 5, iclass 24, count 2 2006.224.07:46:31.98#ibcon#about to read 6, iclass 24, count 2 2006.224.07:46:31.98#ibcon#read 6, iclass 24, count 2 2006.224.07:46:31.98#ibcon#end of sib2, iclass 24, count 2 2006.224.07:46:31.98#ibcon#*mode == 0, iclass 24, count 2 2006.224.07:46:31.98#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.224.07:46:31.98#ibcon#[27=AT05-04\r\n] 2006.224.07:46:31.98#ibcon#*before write, iclass 24, count 2 2006.224.07:46:31.98#ibcon#enter sib2, iclass 24, count 2 2006.224.07:46:31.98#ibcon#flushed, iclass 24, count 2 2006.224.07:46:31.98#ibcon#about to write, iclass 24, count 2 2006.224.07:46:31.98#ibcon#wrote, iclass 24, count 2 2006.224.07:46:31.98#ibcon#about to read 3, iclass 24, count 2 2006.224.07:46:32.01#ibcon#read 3, iclass 24, count 2 2006.224.07:46:32.01#ibcon#about to read 4, iclass 24, count 2 2006.224.07:46:32.01#ibcon#read 4, iclass 24, count 2 2006.224.07:46:32.01#ibcon#about to read 5, iclass 24, count 2 2006.224.07:46:32.01#ibcon#read 5, iclass 24, count 2 2006.224.07:46:32.01#ibcon#about to read 6, iclass 24, count 2 2006.224.07:46:32.01#ibcon#read 6, iclass 24, count 2 2006.224.07:46:32.01#ibcon#end of sib2, iclass 24, count 2 2006.224.07:46:32.01#ibcon#*after write, iclass 24, count 2 2006.224.07:46:32.01#ibcon#*before return 0, iclass 24, count 2 2006.224.07:46:32.01#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.224.07:46:32.01#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.224.07:46:32.01#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.224.07:46:32.01#ibcon#ireg 7 cls_cnt 0 2006.224.07:46:32.01#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.224.07:46:32.13#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.224.07:46:32.13#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.224.07:46:32.13#ibcon#enter wrdev, iclass 24, count 0 2006.224.07:46:32.13#ibcon#first serial, iclass 24, count 0 2006.224.07:46:32.13#ibcon#enter sib2, iclass 24, count 0 2006.224.07:46:32.13#ibcon#flushed, iclass 24, count 0 2006.224.07:46:32.13#ibcon#about to write, iclass 24, count 0 2006.224.07:46:32.13#ibcon#wrote, iclass 24, count 0 2006.224.07:46:32.13#ibcon#about to read 3, iclass 24, count 0 2006.224.07:46:32.15#ibcon#read 3, iclass 24, count 0 2006.224.07:46:32.15#ibcon#about to read 4, iclass 24, count 0 2006.224.07:46:32.15#ibcon#read 4, iclass 24, count 0 2006.224.07:46:32.15#ibcon#about to read 5, iclass 24, count 0 2006.224.07:46:32.15#ibcon#read 5, iclass 24, count 0 2006.224.07:46:32.15#ibcon#about to read 6, iclass 24, count 0 2006.224.07:46:32.15#ibcon#read 6, iclass 24, count 0 2006.224.07:46:32.15#ibcon#end of sib2, iclass 24, count 0 2006.224.07:46:32.15#ibcon#*mode == 0, iclass 24, count 0 2006.224.07:46:32.15#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.224.07:46:32.15#ibcon#[27=USB\r\n] 2006.224.07:46:32.15#ibcon#*before write, iclass 24, count 0 2006.224.07:46:32.15#ibcon#enter sib2, iclass 24, count 0 2006.224.07:46:32.15#ibcon#flushed, iclass 24, count 0 2006.224.07:46:32.15#ibcon#about to write, iclass 24, count 0 2006.224.07:46:32.15#ibcon#wrote, iclass 24, count 0 2006.224.07:46:32.15#ibcon#about to read 3, iclass 24, count 0 2006.224.07:46:32.18#ibcon#read 3, iclass 24, count 0 2006.224.07:46:32.18#ibcon#about to read 4, iclass 24, count 0 2006.224.07:46:32.18#ibcon#read 4, iclass 24, count 0 2006.224.07:46:32.18#ibcon#about to read 5, iclass 24, count 0 2006.224.07:46:32.18#ibcon#read 5, iclass 24, count 0 2006.224.07:46:32.18#ibcon#about to read 6, iclass 24, count 0 2006.224.07:46:32.18#ibcon#read 6, iclass 24, count 0 2006.224.07:46:32.18#ibcon#end of sib2, iclass 24, count 0 2006.224.07:46:32.18#ibcon#*after write, iclass 24, count 0 2006.224.07:46:32.18#ibcon#*before return 0, iclass 24, count 0 2006.224.07:46:32.18#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.224.07:46:32.18#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.224.07:46:32.18#ibcon#about to clear, iclass 24 cls_cnt 0 2006.224.07:46:32.18#ibcon#cleared, iclass 24 cls_cnt 0 2006.224.07:46:32.18$vc4f8/vblo=6,752.99 2006.224.07:46:32.18#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.224.07:46:32.18#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.224.07:46:32.18#ibcon#ireg 17 cls_cnt 0 2006.224.07:46:32.18#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.224.07:46:32.18#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.224.07:46:32.18#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.224.07:46:32.18#ibcon#enter wrdev, iclass 26, count 0 2006.224.07:46:32.18#ibcon#first serial, iclass 26, count 0 2006.224.07:46:32.18#ibcon#enter sib2, iclass 26, count 0 2006.224.07:46:32.18#ibcon#flushed, iclass 26, count 0 2006.224.07:46:32.18#ibcon#about to write, iclass 26, count 0 2006.224.07:46:32.18#ibcon#wrote, iclass 26, count 0 2006.224.07:46:32.18#ibcon#about to read 3, iclass 26, count 0 2006.224.07:46:32.20#ibcon#read 3, iclass 26, count 0 2006.224.07:46:32.20#ibcon#about to read 4, iclass 26, count 0 2006.224.07:46:32.20#ibcon#read 4, iclass 26, count 0 2006.224.07:46:32.20#ibcon#about to read 5, iclass 26, count 0 2006.224.07:46:32.20#ibcon#read 5, iclass 26, count 0 2006.224.07:46:32.20#ibcon#about to read 6, iclass 26, count 0 2006.224.07:46:32.20#ibcon#read 6, iclass 26, count 0 2006.224.07:46:32.20#ibcon#end of sib2, iclass 26, count 0 2006.224.07:46:32.20#ibcon#*mode == 0, iclass 26, count 0 2006.224.07:46:32.20#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.224.07:46:32.20#ibcon#[28=FRQ=06,752.99\r\n] 2006.224.07:46:32.20#ibcon#*before write, iclass 26, count 0 2006.224.07:46:32.20#ibcon#enter sib2, iclass 26, count 0 2006.224.07:46:32.20#ibcon#flushed, iclass 26, count 0 2006.224.07:46:32.20#ibcon#about to write, iclass 26, count 0 2006.224.07:46:32.20#ibcon#wrote, iclass 26, count 0 2006.224.07:46:32.20#ibcon#about to read 3, iclass 26, count 0 2006.224.07:46:32.24#ibcon#read 3, iclass 26, count 0 2006.224.07:46:32.24#ibcon#about to read 4, iclass 26, count 0 2006.224.07:46:32.24#ibcon#read 4, iclass 26, count 0 2006.224.07:46:32.24#ibcon#about to read 5, iclass 26, count 0 2006.224.07:46:32.24#ibcon#read 5, iclass 26, count 0 2006.224.07:46:32.24#ibcon#about to read 6, iclass 26, count 0 2006.224.07:46:32.24#ibcon#read 6, iclass 26, count 0 2006.224.07:46:32.24#ibcon#end of sib2, iclass 26, count 0 2006.224.07:46:32.24#ibcon#*after write, iclass 26, count 0 2006.224.07:46:32.24#ibcon#*before return 0, iclass 26, count 0 2006.224.07:46:32.24#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.224.07:46:32.24#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.224.07:46:32.24#ibcon#about to clear, iclass 26 cls_cnt 0 2006.224.07:46:32.24#ibcon#cleared, iclass 26 cls_cnt 0 2006.224.07:46:32.24$vc4f8/vb=6,4 2006.224.07:46:32.24#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.224.07:46:32.24#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.224.07:46:32.24#ibcon#ireg 11 cls_cnt 2 2006.224.07:46:32.24#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.224.07:46:32.30#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.224.07:46:32.30#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.224.07:46:32.30#ibcon#enter wrdev, iclass 28, count 2 2006.224.07:46:32.30#ibcon#first serial, iclass 28, count 2 2006.224.07:46:32.30#ibcon#enter sib2, iclass 28, count 2 2006.224.07:46:32.30#ibcon#flushed, iclass 28, count 2 2006.224.07:46:32.30#ibcon#about to write, iclass 28, count 2 2006.224.07:46:32.30#ibcon#wrote, iclass 28, count 2 2006.224.07:46:32.30#ibcon#about to read 3, iclass 28, count 2 2006.224.07:46:32.32#ibcon#read 3, iclass 28, count 2 2006.224.07:46:32.32#ibcon#about to read 4, iclass 28, count 2 2006.224.07:46:32.32#ibcon#read 4, iclass 28, count 2 2006.224.07:46:32.32#ibcon#about to read 5, iclass 28, count 2 2006.224.07:46:32.32#ibcon#read 5, iclass 28, count 2 2006.224.07:46:32.32#ibcon#about to read 6, iclass 28, count 2 2006.224.07:46:32.32#ibcon#read 6, iclass 28, count 2 2006.224.07:46:32.32#ibcon#end of sib2, iclass 28, count 2 2006.224.07:46:32.32#ibcon#*mode == 0, iclass 28, count 2 2006.224.07:46:32.32#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.224.07:46:32.32#ibcon#[27=AT06-04\r\n] 2006.224.07:46:32.32#ibcon#*before write, iclass 28, count 2 2006.224.07:46:32.32#ibcon#enter sib2, iclass 28, count 2 2006.224.07:46:32.32#ibcon#flushed, iclass 28, count 2 2006.224.07:46:32.32#ibcon#about to write, iclass 28, count 2 2006.224.07:46:32.32#ibcon#wrote, iclass 28, count 2 2006.224.07:46:32.32#ibcon#about to read 3, iclass 28, count 2 2006.224.07:46:32.35#ibcon#read 3, iclass 28, count 2 2006.224.07:46:32.35#ibcon#about to read 4, iclass 28, count 2 2006.224.07:46:32.35#ibcon#read 4, iclass 28, count 2 2006.224.07:46:32.35#ibcon#about to read 5, iclass 28, count 2 2006.224.07:46:32.35#ibcon#read 5, iclass 28, count 2 2006.224.07:46:32.35#ibcon#about to read 6, iclass 28, count 2 2006.224.07:46:32.35#ibcon#read 6, iclass 28, count 2 2006.224.07:46:32.35#ibcon#end of sib2, iclass 28, count 2 2006.224.07:46:32.35#ibcon#*after write, iclass 28, count 2 2006.224.07:46:32.35#ibcon#*before return 0, iclass 28, count 2 2006.224.07:46:32.35#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.224.07:46:32.35#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.224.07:46:32.35#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.224.07:46:32.35#ibcon#ireg 7 cls_cnt 0 2006.224.07:46:32.35#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.224.07:46:32.47#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.224.07:46:32.47#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.224.07:46:32.47#ibcon#enter wrdev, iclass 28, count 0 2006.224.07:46:32.47#ibcon#first serial, iclass 28, count 0 2006.224.07:46:32.47#ibcon#enter sib2, iclass 28, count 0 2006.224.07:46:32.47#ibcon#flushed, iclass 28, count 0 2006.224.07:46:32.47#ibcon#about to write, iclass 28, count 0 2006.224.07:46:32.47#ibcon#wrote, iclass 28, count 0 2006.224.07:46:32.47#ibcon#about to read 3, iclass 28, count 0 2006.224.07:46:32.49#ibcon#read 3, iclass 28, count 0 2006.224.07:46:32.49#ibcon#about to read 4, iclass 28, count 0 2006.224.07:46:32.49#ibcon#read 4, iclass 28, count 0 2006.224.07:46:32.49#ibcon#about to read 5, iclass 28, count 0 2006.224.07:46:32.49#ibcon#read 5, iclass 28, count 0 2006.224.07:46:32.49#ibcon#about to read 6, iclass 28, count 0 2006.224.07:46:32.49#ibcon#read 6, iclass 28, count 0 2006.224.07:46:32.49#ibcon#end of sib2, iclass 28, count 0 2006.224.07:46:32.49#ibcon#*mode == 0, iclass 28, count 0 2006.224.07:46:32.49#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.224.07:46:32.49#ibcon#[27=USB\r\n] 2006.224.07:46:32.49#ibcon#*before write, iclass 28, count 0 2006.224.07:46:32.49#ibcon#enter sib2, iclass 28, count 0 2006.224.07:46:32.49#ibcon#flushed, iclass 28, count 0 2006.224.07:46:32.49#ibcon#about to write, iclass 28, count 0 2006.224.07:46:32.49#ibcon#wrote, iclass 28, count 0 2006.224.07:46:32.49#ibcon#about to read 3, iclass 28, count 0 2006.224.07:46:32.52#ibcon#read 3, iclass 28, count 0 2006.224.07:46:32.52#ibcon#about to read 4, iclass 28, count 0 2006.224.07:46:32.52#ibcon#read 4, iclass 28, count 0 2006.224.07:46:32.52#ibcon#about to read 5, iclass 28, count 0 2006.224.07:46:32.52#ibcon#read 5, iclass 28, count 0 2006.224.07:46:32.52#ibcon#about to read 6, iclass 28, count 0 2006.224.07:46:32.52#ibcon#read 6, iclass 28, count 0 2006.224.07:46:32.52#ibcon#end of sib2, iclass 28, count 0 2006.224.07:46:32.52#ibcon#*after write, iclass 28, count 0 2006.224.07:46:32.52#ibcon#*before return 0, iclass 28, count 0 2006.224.07:46:32.52#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.224.07:46:32.52#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.224.07:46:32.52#ibcon#about to clear, iclass 28 cls_cnt 0 2006.224.07:46:32.52#ibcon#cleared, iclass 28 cls_cnt 0 2006.224.07:46:32.52$vc4f8/vabw=wide 2006.224.07:46:32.52#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.224.07:46:32.52#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.224.07:46:32.52#ibcon#ireg 8 cls_cnt 0 2006.224.07:46:32.52#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.224.07:46:32.52#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.224.07:46:32.52#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.224.07:46:32.52#ibcon#enter wrdev, iclass 30, count 0 2006.224.07:46:32.52#ibcon#first serial, iclass 30, count 0 2006.224.07:46:32.52#ibcon#enter sib2, iclass 30, count 0 2006.224.07:46:32.52#ibcon#flushed, iclass 30, count 0 2006.224.07:46:32.52#ibcon#about to write, iclass 30, count 0 2006.224.07:46:32.52#ibcon#wrote, iclass 30, count 0 2006.224.07:46:32.52#ibcon#about to read 3, iclass 30, count 0 2006.224.07:46:32.54#ibcon#read 3, iclass 30, count 0 2006.224.07:46:32.54#ibcon#about to read 4, iclass 30, count 0 2006.224.07:46:32.54#ibcon#read 4, iclass 30, count 0 2006.224.07:46:32.54#ibcon#about to read 5, iclass 30, count 0 2006.224.07:46:32.54#ibcon#read 5, iclass 30, count 0 2006.224.07:46:32.54#ibcon#about to read 6, iclass 30, count 0 2006.224.07:46:32.54#ibcon#read 6, iclass 30, count 0 2006.224.07:46:32.54#ibcon#end of sib2, iclass 30, count 0 2006.224.07:46:32.54#ibcon#*mode == 0, iclass 30, count 0 2006.224.07:46:32.54#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.224.07:46:32.54#ibcon#[25=BW32\r\n] 2006.224.07:46:32.54#ibcon#*before write, iclass 30, count 0 2006.224.07:46:32.54#ibcon#enter sib2, iclass 30, count 0 2006.224.07:46:32.54#ibcon#flushed, iclass 30, count 0 2006.224.07:46:32.54#ibcon#about to write, iclass 30, count 0 2006.224.07:46:32.54#ibcon#wrote, iclass 30, count 0 2006.224.07:46:32.54#ibcon#about to read 3, iclass 30, count 0 2006.224.07:46:32.57#ibcon#read 3, iclass 30, count 0 2006.224.07:46:32.57#ibcon#about to read 4, iclass 30, count 0 2006.224.07:46:32.57#ibcon#read 4, iclass 30, count 0 2006.224.07:46:32.57#ibcon#about to read 5, iclass 30, count 0 2006.224.07:46:32.57#ibcon#read 5, iclass 30, count 0 2006.224.07:46:32.57#ibcon#about to read 6, iclass 30, count 0 2006.224.07:46:32.57#ibcon#read 6, iclass 30, count 0 2006.224.07:46:32.57#ibcon#end of sib2, iclass 30, count 0 2006.224.07:46:32.57#ibcon#*after write, iclass 30, count 0 2006.224.07:46:32.57#ibcon#*before return 0, iclass 30, count 0 2006.224.07:46:32.57#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.224.07:46:32.57#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.224.07:46:32.57#ibcon#about to clear, iclass 30 cls_cnt 0 2006.224.07:46:32.57#ibcon#cleared, iclass 30 cls_cnt 0 2006.224.07:46:32.57$vc4f8/vbbw=wide 2006.224.07:46:32.57#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.224.07:46:32.57#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.224.07:46:32.57#ibcon#ireg 8 cls_cnt 0 2006.224.07:46:32.57#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.224.07:46:32.64#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.224.07:46:32.64#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.224.07:46:32.64#ibcon#enter wrdev, iclass 32, count 0 2006.224.07:46:32.64#ibcon#first serial, iclass 32, count 0 2006.224.07:46:32.64#ibcon#enter sib2, iclass 32, count 0 2006.224.07:46:32.64#ibcon#flushed, iclass 32, count 0 2006.224.07:46:32.64#ibcon#about to write, iclass 32, count 0 2006.224.07:46:32.64#ibcon#wrote, iclass 32, count 0 2006.224.07:46:32.64#ibcon#about to read 3, iclass 32, count 0 2006.224.07:46:32.66#ibcon#read 3, iclass 32, count 0 2006.224.07:46:32.66#ibcon#about to read 4, iclass 32, count 0 2006.224.07:46:32.66#ibcon#read 4, iclass 32, count 0 2006.224.07:46:32.66#ibcon#about to read 5, iclass 32, count 0 2006.224.07:46:32.66#ibcon#read 5, iclass 32, count 0 2006.224.07:46:32.66#ibcon#about to read 6, iclass 32, count 0 2006.224.07:46:32.66#ibcon#read 6, iclass 32, count 0 2006.224.07:46:32.66#ibcon#end of sib2, iclass 32, count 0 2006.224.07:46:32.66#ibcon#*mode == 0, iclass 32, count 0 2006.224.07:46:32.66#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.224.07:46:32.66#ibcon#[27=BW32\r\n] 2006.224.07:46:32.66#ibcon#*before write, iclass 32, count 0 2006.224.07:46:32.66#ibcon#enter sib2, iclass 32, count 0 2006.224.07:46:32.66#ibcon#flushed, iclass 32, count 0 2006.224.07:46:32.66#ibcon#about to write, iclass 32, count 0 2006.224.07:46:32.66#ibcon#wrote, iclass 32, count 0 2006.224.07:46:32.66#ibcon#about to read 3, iclass 32, count 0 2006.224.07:46:32.69#ibcon#read 3, iclass 32, count 0 2006.224.07:46:32.69#ibcon#about to read 4, iclass 32, count 0 2006.224.07:46:32.69#ibcon#read 4, iclass 32, count 0 2006.224.07:46:32.69#ibcon#about to read 5, iclass 32, count 0 2006.224.07:46:32.69#ibcon#read 5, iclass 32, count 0 2006.224.07:46:32.69#ibcon#about to read 6, iclass 32, count 0 2006.224.07:46:32.69#ibcon#read 6, iclass 32, count 0 2006.224.07:46:32.69#ibcon#end of sib2, iclass 32, count 0 2006.224.07:46:32.69#ibcon#*after write, iclass 32, count 0 2006.224.07:46:32.69#ibcon#*before return 0, iclass 32, count 0 2006.224.07:46:32.69#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.224.07:46:32.69#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.224.07:46:32.69#ibcon#about to clear, iclass 32 cls_cnt 0 2006.224.07:46:32.69#ibcon#cleared, iclass 32 cls_cnt 0 2006.224.07:46:32.69$4f8m12a/ifd4f 2006.224.07:46:32.69$ifd4f/lo= 2006.224.07:46:32.69$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.224.07:46:32.69$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.224.07:46:32.69$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.224.07:46:32.69$ifd4f/patch= 2006.224.07:46:32.69$ifd4f/patch=lo1,a1,a2,a3,a4 2006.224.07:46:32.70$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.224.07:46:32.70$ifd4f/patch=lo3,a5,a6,a7,a8 2006.224.07:46:32.70$4f8m12a/"form=m,16.000,1:2 2006.224.07:46:32.70$4f8m12a/"tpicd 2006.224.07:46:32.70$4f8m12a/echo=off 2006.224.07:46:32.70$4f8m12a/xlog=off 2006.224.07:46:32.70:!2006.224.07:47:00 2006.224.07:46:42.13#trakl#Source acquired 2006.224.07:46:44.13#flagr#flagr/antenna,acquired 2006.224.07:47:00.01:preob 2006.224.07:47:01.14/onsource/TRACKING 2006.224.07:47:01.14:!2006.224.07:47:10 2006.224.07:47:10.00:data_valid=on 2006.224.07:47:10.00:midob 2006.224.07:47:10.14/onsource/TRACKING 2006.224.07:47:10.14/wx/23.60,1004.3,100 2006.224.07:47:10.30/cable/+6.4330E-03 2006.224.07:47:11.39/va/01,08,usb,yes,42,44 2006.224.07:47:11.39/va/02,07,usb,yes,42,44 2006.224.07:47:11.39/va/03,06,usb,yes,45,45 2006.224.07:47:11.39/va/04,07,usb,yes,44,47 2006.224.07:47:11.39/va/05,07,usb,yes,52,55 2006.224.07:47:11.39/va/06,06,usb,yes,52,51 2006.224.07:47:11.39/va/07,06,usb,yes,53,52 2006.224.07:47:11.39/va/08,07,usb,yes,50,49 2006.224.07:47:11.62/valo/01,532.99,yes,locked 2006.224.07:47:11.62/valo/02,572.99,yes,locked 2006.224.07:47:11.62/valo/03,672.99,yes,locked 2006.224.07:47:11.62/valo/04,832.99,yes,locked 2006.224.07:47:11.62/valo/05,652.99,yes,locked 2006.224.07:47:11.62/valo/06,772.99,yes,locked 2006.224.07:47:11.62/valo/07,832.99,yes,locked 2006.224.07:47:11.62/valo/08,852.99,yes,locked 2006.224.07:47:12.71/vb/01,04,usb,yes,32,30 2006.224.07:47:12.71/vb/02,04,usb,yes,33,35 2006.224.07:47:12.71/vb/03,04,usb,yes,30,34 2006.224.07:47:12.71/vb/04,04,usb,yes,30,31 2006.224.07:47:12.71/vb/05,04,usb,yes,29,33 2006.224.07:47:12.71/vb/06,04,usb,yes,30,33 2006.224.07:47:12.71/vb/07,04,usb,yes,32,32 2006.224.07:47:12.71/vb/08,04,usb,yes,29,33 2006.224.07:47:12.94/vblo/01,632.99,yes,locked 2006.224.07:47:12.94/vblo/02,640.99,yes,locked 2006.224.07:47:12.94/vblo/03,656.99,yes,locked 2006.224.07:47:12.94/vblo/04,712.99,yes,locked 2006.224.07:47:12.94/vblo/05,744.99,yes,locked 2006.224.07:47:12.94/vblo/06,752.99,yes,locked 2006.224.07:47:12.94/vblo/07,734.99,yes,locked 2006.224.07:47:12.94/vblo/08,744.99,yes,locked 2006.224.07:47:13.09/vabw/8 2006.224.07:47:13.24/vbbw/8 2006.224.07:47:13.33/xfe/off,on,15.2 2006.224.07:47:13.71/ifatt/23,28,28,28 2006.224.07:47:14.07/fmout-gps/S +4.28E-07 2006.224.07:47:14.11:!2006.224.07:48:10 2006.224.07:48:10.01:data_valid=off 2006.224.07:48:10.02:postob 2006.224.07:48:10.22/cable/+6.4339E-03 2006.224.07:48:10.23/wx/23.60,1004.2,100 2006.224.07:48:11.07/fmout-gps/S +4.27E-07 2006.224.07:48:11.08:scan_name=224-0749,k06224,60 2006.224.07:48:11.08:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.224.07:48:12.14#flagr#flagr/antenna,new-source 2006.224.07:48:12.15:checkk5 2006.224.07:48:12.52/chk_autoobs//k5ts1/ autoobs is running! 2006.224.07:48:12.89/chk_autoobs//k5ts2/ autoobs is running! 2006.224.07:48:13.27/chk_autoobs//k5ts3/ autoobs is running! 2006.224.07:48:13.65/chk_autoobs//k5ts4/ autoobs is running! 2006.224.07:48:14.01/chk_obsdata//k5ts1/T2240747??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.07:48:14.38/chk_obsdata//k5ts2/T2240747??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.07:48:14.73/chk_obsdata//k5ts3/T2240747??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.07:48:15.10/chk_obsdata//k5ts4/T2240747??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.07:48:15.79/k5log//k5ts1_log_newline 2006.224.07:48:16.47/k5log//k5ts2_log_newline 2006.224.07:48:17.16/k5log//k5ts3_log_newline 2006.224.07:48:17.84/k5log//k5ts4_log_newline 2006.224.07:48:17.86/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.224.07:48:17.86:4f8m12a=1 2006.224.07:48:17.86$4f8m12a/echo=on 2006.224.07:48:17.86$4f8m12a/pcalon 2006.224.07:48:17.86$pcalon/"no phase cal control is implemented here 2006.224.07:48:17.86$4f8m12a/"tpicd=stop 2006.224.07:48:17.86$4f8m12a/vc4f8 2006.224.07:48:17.86$vc4f8/valo=1,532.99 2006.224.07:48:17.86#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.224.07:48:17.86#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.224.07:48:17.86#ibcon#ireg 17 cls_cnt 0 2006.224.07:48:17.86#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.224.07:48:17.86#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.224.07:48:17.86#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.224.07:48:17.86#ibcon#enter wrdev, iclass 39, count 0 2006.224.07:48:17.86#ibcon#first serial, iclass 39, count 0 2006.224.07:48:17.86#ibcon#enter sib2, iclass 39, count 0 2006.224.07:48:17.86#ibcon#flushed, iclass 39, count 0 2006.224.07:48:17.86#ibcon#about to write, iclass 39, count 0 2006.224.07:48:17.86#ibcon#wrote, iclass 39, count 0 2006.224.07:48:17.86#ibcon#about to read 3, iclass 39, count 0 2006.224.07:48:17.90#ibcon#read 3, iclass 39, count 0 2006.224.07:48:17.90#ibcon#about to read 4, iclass 39, count 0 2006.224.07:48:17.90#ibcon#read 4, iclass 39, count 0 2006.224.07:48:17.90#ibcon#about to read 5, iclass 39, count 0 2006.224.07:48:17.90#ibcon#read 5, iclass 39, count 0 2006.224.07:48:17.90#ibcon#about to read 6, iclass 39, count 0 2006.224.07:48:17.90#ibcon#read 6, iclass 39, count 0 2006.224.07:48:17.90#ibcon#end of sib2, iclass 39, count 0 2006.224.07:48:17.90#ibcon#*mode == 0, iclass 39, count 0 2006.224.07:48:17.90#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.224.07:48:17.90#ibcon#[26=FRQ=01,532.99\r\n] 2006.224.07:48:17.90#ibcon#*before write, iclass 39, count 0 2006.224.07:48:17.90#ibcon#enter sib2, iclass 39, count 0 2006.224.07:48:17.90#ibcon#flushed, iclass 39, count 0 2006.224.07:48:17.90#ibcon#about to write, iclass 39, count 0 2006.224.07:48:17.90#ibcon#wrote, iclass 39, count 0 2006.224.07:48:17.90#ibcon#about to read 3, iclass 39, count 0 2006.224.07:48:17.95#ibcon#read 3, iclass 39, count 0 2006.224.07:48:17.95#ibcon#about to read 4, iclass 39, count 0 2006.224.07:48:17.95#ibcon#read 4, iclass 39, count 0 2006.224.07:48:17.95#ibcon#about to read 5, iclass 39, count 0 2006.224.07:48:17.95#ibcon#read 5, iclass 39, count 0 2006.224.07:48:17.95#ibcon#about to read 6, iclass 39, count 0 2006.224.07:48:17.95#ibcon#read 6, iclass 39, count 0 2006.224.07:48:17.95#ibcon#end of sib2, iclass 39, count 0 2006.224.07:48:17.95#ibcon#*after write, iclass 39, count 0 2006.224.07:48:17.95#ibcon#*before return 0, iclass 39, count 0 2006.224.07:48:17.95#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.224.07:48:17.95#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.224.07:48:17.95#ibcon#about to clear, iclass 39 cls_cnt 0 2006.224.07:48:17.95#ibcon#cleared, iclass 39 cls_cnt 0 2006.224.07:48:17.95$vc4f8/va=1,8 2006.224.07:48:17.95#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.224.07:48:17.95#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.224.07:48:17.95#ibcon#ireg 11 cls_cnt 2 2006.224.07:48:17.95#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.224.07:48:17.95#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.224.07:48:17.95#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.224.07:48:17.95#ibcon#enter wrdev, iclass 3, count 2 2006.224.07:48:17.95#ibcon#first serial, iclass 3, count 2 2006.224.07:48:17.95#ibcon#enter sib2, iclass 3, count 2 2006.224.07:48:17.95#ibcon#flushed, iclass 3, count 2 2006.224.07:48:17.95#ibcon#about to write, iclass 3, count 2 2006.224.07:48:17.95#ibcon#wrote, iclass 3, count 2 2006.224.07:48:17.95#ibcon#about to read 3, iclass 3, count 2 2006.224.07:48:17.98#ibcon#read 3, iclass 3, count 2 2006.224.07:48:17.98#ibcon#about to read 4, iclass 3, count 2 2006.224.07:48:17.98#ibcon#read 4, iclass 3, count 2 2006.224.07:48:17.98#ibcon#about to read 5, iclass 3, count 2 2006.224.07:48:17.98#ibcon#read 5, iclass 3, count 2 2006.224.07:48:17.98#ibcon#about to read 6, iclass 3, count 2 2006.224.07:48:17.98#ibcon#read 6, iclass 3, count 2 2006.224.07:48:17.98#ibcon#end of sib2, iclass 3, count 2 2006.224.07:48:17.98#ibcon#*mode == 0, iclass 3, count 2 2006.224.07:48:17.98#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.224.07:48:17.98#ibcon#[25=AT01-08\r\n] 2006.224.07:48:17.98#ibcon#*before write, iclass 3, count 2 2006.224.07:48:17.98#ibcon#enter sib2, iclass 3, count 2 2006.224.07:48:17.98#ibcon#flushed, iclass 3, count 2 2006.224.07:48:17.98#ibcon#about to write, iclass 3, count 2 2006.224.07:48:17.98#ibcon#wrote, iclass 3, count 2 2006.224.07:48:17.98#ibcon#about to read 3, iclass 3, count 2 2006.224.07:48:18.01#ibcon#read 3, iclass 3, count 2 2006.224.07:48:18.01#ibcon#about to read 4, iclass 3, count 2 2006.224.07:48:18.01#ibcon#read 4, iclass 3, count 2 2006.224.07:48:18.01#ibcon#about to read 5, iclass 3, count 2 2006.224.07:48:18.01#ibcon#read 5, iclass 3, count 2 2006.224.07:48:18.01#ibcon#about to read 6, iclass 3, count 2 2006.224.07:48:18.01#ibcon#read 6, iclass 3, count 2 2006.224.07:48:18.01#ibcon#end of sib2, iclass 3, count 2 2006.224.07:48:18.01#ibcon#*after write, iclass 3, count 2 2006.224.07:48:18.01#ibcon#*before return 0, iclass 3, count 2 2006.224.07:48:18.01#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.224.07:48:18.01#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.224.07:48:18.01#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.224.07:48:18.01#ibcon#ireg 7 cls_cnt 0 2006.224.07:48:18.01#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.224.07:48:18.13#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.224.07:48:18.13#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.224.07:48:18.13#ibcon#enter wrdev, iclass 3, count 0 2006.224.07:48:18.13#ibcon#first serial, iclass 3, count 0 2006.224.07:48:18.13#ibcon#enter sib2, iclass 3, count 0 2006.224.07:48:18.13#ibcon#flushed, iclass 3, count 0 2006.224.07:48:18.13#ibcon#about to write, iclass 3, count 0 2006.224.07:48:18.13#ibcon#wrote, iclass 3, count 0 2006.224.07:48:18.13#ibcon#about to read 3, iclass 3, count 0 2006.224.07:48:18.15#ibcon#read 3, iclass 3, count 0 2006.224.07:48:18.15#ibcon#about to read 4, iclass 3, count 0 2006.224.07:48:18.15#ibcon#read 4, iclass 3, count 0 2006.224.07:48:18.15#ibcon#about to read 5, iclass 3, count 0 2006.224.07:48:18.15#ibcon#read 5, iclass 3, count 0 2006.224.07:48:18.15#ibcon#about to read 6, iclass 3, count 0 2006.224.07:48:18.15#ibcon#read 6, iclass 3, count 0 2006.224.07:48:18.15#ibcon#end of sib2, iclass 3, count 0 2006.224.07:48:18.15#ibcon#*mode == 0, iclass 3, count 0 2006.224.07:48:18.15#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.224.07:48:18.15#ibcon#[25=USB\r\n] 2006.224.07:48:18.15#ibcon#*before write, iclass 3, count 0 2006.224.07:48:18.15#ibcon#enter sib2, iclass 3, count 0 2006.224.07:48:18.15#ibcon#flushed, iclass 3, count 0 2006.224.07:48:18.15#ibcon#about to write, iclass 3, count 0 2006.224.07:48:18.15#ibcon#wrote, iclass 3, count 0 2006.224.07:48:18.15#ibcon#about to read 3, iclass 3, count 0 2006.224.07:48:18.18#ibcon#read 3, iclass 3, count 0 2006.224.07:48:18.18#ibcon#about to read 4, iclass 3, count 0 2006.224.07:48:18.18#ibcon#read 4, iclass 3, count 0 2006.224.07:48:18.18#ibcon#about to read 5, iclass 3, count 0 2006.224.07:48:18.18#ibcon#read 5, iclass 3, count 0 2006.224.07:48:18.18#ibcon#about to read 6, iclass 3, count 0 2006.224.07:48:18.18#ibcon#read 6, iclass 3, count 0 2006.224.07:48:18.18#ibcon#end of sib2, iclass 3, count 0 2006.224.07:48:18.18#ibcon#*after write, iclass 3, count 0 2006.224.07:48:18.18#ibcon#*before return 0, iclass 3, count 0 2006.224.07:48:18.18#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.224.07:48:18.18#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.224.07:48:18.18#ibcon#about to clear, iclass 3 cls_cnt 0 2006.224.07:48:18.18#ibcon#cleared, iclass 3 cls_cnt 0 2006.224.07:48:18.18$vc4f8/valo=2,572.99 2006.224.07:48:18.18#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.224.07:48:18.18#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.224.07:48:18.18#ibcon#ireg 17 cls_cnt 0 2006.224.07:48:18.18#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.224.07:48:18.18#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.224.07:48:18.18#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.224.07:48:18.18#ibcon#enter wrdev, iclass 5, count 0 2006.224.07:48:18.18#ibcon#first serial, iclass 5, count 0 2006.224.07:48:18.18#ibcon#enter sib2, iclass 5, count 0 2006.224.07:48:18.18#ibcon#flushed, iclass 5, count 0 2006.224.07:48:18.18#ibcon#about to write, iclass 5, count 0 2006.224.07:48:18.18#ibcon#wrote, iclass 5, count 0 2006.224.07:48:18.18#ibcon#about to read 3, iclass 5, count 0 2006.224.07:48:18.21#ibcon#read 3, iclass 5, count 0 2006.224.07:48:18.21#ibcon#about to read 4, iclass 5, count 0 2006.224.07:48:18.21#ibcon#read 4, iclass 5, count 0 2006.224.07:48:18.21#ibcon#about to read 5, iclass 5, count 0 2006.224.07:48:18.21#ibcon#read 5, iclass 5, count 0 2006.224.07:48:18.21#ibcon#about to read 6, iclass 5, count 0 2006.224.07:48:18.21#ibcon#read 6, iclass 5, count 0 2006.224.07:48:18.21#ibcon#end of sib2, iclass 5, count 0 2006.224.07:48:18.21#ibcon#*mode == 0, iclass 5, count 0 2006.224.07:48:18.21#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.224.07:48:18.21#ibcon#[26=FRQ=02,572.99\r\n] 2006.224.07:48:18.21#ibcon#*before write, iclass 5, count 0 2006.224.07:48:18.21#ibcon#enter sib2, iclass 5, count 0 2006.224.07:48:18.21#ibcon#flushed, iclass 5, count 0 2006.224.07:48:18.21#ibcon#about to write, iclass 5, count 0 2006.224.07:48:18.21#ibcon#wrote, iclass 5, count 0 2006.224.07:48:18.21#ibcon#about to read 3, iclass 5, count 0 2006.224.07:48:18.25#ibcon#read 3, iclass 5, count 0 2006.224.07:48:18.25#ibcon#about to read 4, iclass 5, count 0 2006.224.07:48:18.25#ibcon#read 4, iclass 5, count 0 2006.224.07:48:18.25#ibcon#about to read 5, iclass 5, count 0 2006.224.07:48:18.25#ibcon#read 5, iclass 5, count 0 2006.224.07:48:18.25#ibcon#about to read 6, iclass 5, count 0 2006.224.07:48:18.25#ibcon#read 6, iclass 5, count 0 2006.224.07:48:18.25#ibcon#end of sib2, iclass 5, count 0 2006.224.07:48:18.25#ibcon#*after write, iclass 5, count 0 2006.224.07:48:18.25#ibcon#*before return 0, iclass 5, count 0 2006.224.07:48:18.25#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.224.07:48:18.25#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.224.07:48:18.25#ibcon#about to clear, iclass 5 cls_cnt 0 2006.224.07:48:18.25#ibcon#cleared, iclass 5 cls_cnt 0 2006.224.07:48:18.25$vc4f8/va=2,7 2006.224.07:48:18.25#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.224.07:48:18.25#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.224.07:48:18.25#ibcon#ireg 11 cls_cnt 2 2006.224.07:48:18.25#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.224.07:48:18.30#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.224.07:48:18.30#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.224.07:48:18.30#ibcon#enter wrdev, iclass 7, count 2 2006.224.07:48:18.30#ibcon#first serial, iclass 7, count 2 2006.224.07:48:18.30#ibcon#enter sib2, iclass 7, count 2 2006.224.07:48:18.30#ibcon#flushed, iclass 7, count 2 2006.224.07:48:18.30#ibcon#about to write, iclass 7, count 2 2006.224.07:48:18.31#ibcon#wrote, iclass 7, count 2 2006.224.07:48:18.31#ibcon#about to read 3, iclass 7, count 2 2006.224.07:48:18.32#ibcon#read 3, iclass 7, count 2 2006.224.07:48:18.32#ibcon#about to read 4, iclass 7, count 2 2006.224.07:48:18.32#ibcon#read 4, iclass 7, count 2 2006.224.07:48:18.32#ibcon#about to read 5, iclass 7, count 2 2006.224.07:48:18.32#ibcon#read 5, iclass 7, count 2 2006.224.07:48:18.32#ibcon#about to read 6, iclass 7, count 2 2006.224.07:48:18.32#ibcon#read 6, iclass 7, count 2 2006.224.07:48:18.32#ibcon#end of sib2, iclass 7, count 2 2006.224.07:48:18.32#ibcon#*mode == 0, iclass 7, count 2 2006.224.07:48:18.32#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.224.07:48:18.32#ibcon#[25=AT02-07\r\n] 2006.224.07:48:18.32#ibcon#*before write, iclass 7, count 2 2006.224.07:48:18.32#ibcon#enter sib2, iclass 7, count 2 2006.224.07:48:18.32#ibcon#flushed, iclass 7, count 2 2006.224.07:48:18.32#ibcon#about to write, iclass 7, count 2 2006.224.07:48:18.32#ibcon#wrote, iclass 7, count 2 2006.224.07:48:18.32#ibcon#about to read 3, iclass 7, count 2 2006.224.07:48:18.35#ibcon#read 3, iclass 7, count 2 2006.224.07:48:18.35#ibcon#about to read 4, iclass 7, count 2 2006.224.07:48:18.35#ibcon#read 4, iclass 7, count 2 2006.224.07:48:18.35#ibcon#about to read 5, iclass 7, count 2 2006.224.07:48:18.35#ibcon#read 5, iclass 7, count 2 2006.224.07:48:18.35#ibcon#about to read 6, iclass 7, count 2 2006.224.07:48:18.35#ibcon#read 6, iclass 7, count 2 2006.224.07:48:18.35#ibcon#end of sib2, iclass 7, count 2 2006.224.07:48:18.35#ibcon#*after write, iclass 7, count 2 2006.224.07:48:18.35#ibcon#*before return 0, iclass 7, count 2 2006.224.07:48:18.35#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.224.07:48:18.35#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.224.07:48:18.35#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.224.07:48:18.35#ibcon#ireg 7 cls_cnt 0 2006.224.07:48:18.35#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.224.07:48:18.47#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.224.07:48:18.47#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.224.07:48:18.47#ibcon#enter wrdev, iclass 7, count 0 2006.224.07:48:18.47#ibcon#first serial, iclass 7, count 0 2006.224.07:48:18.47#ibcon#enter sib2, iclass 7, count 0 2006.224.07:48:18.47#ibcon#flushed, iclass 7, count 0 2006.224.07:48:18.47#ibcon#about to write, iclass 7, count 0 2006.224.07:48:18.47#ibcon#wrote, iclass 7, count 0 2006.224.07:48:18.47#ibcon#about to read 3, iclass 7, count 0 2006.224.07:48:18.49#ibcon#read 3, iclass 7, count 0 2006.224.07:48:18.49#ibcon#about to read 4, iclass 7, count 0 2006.224.07:48:18.49#ibcon#read 4, iclass 7, count 0 2006.224.07:48:18.49#ibcon#about to read 5, iclass 7, count 0 2006.224.07:48:18.49#ibcon#read 5, iclass 7, count 0 2006.224.07:48:18.49#ibcon#about to read 6, iclass 7, count 0 2006.224.07:48:18.49#ibcon#read 6, iclass 7, count 0 2006.224.07:48:18.49#ibcon#end of sib2, iclass 7, count 0 2006.224.07:48:18.49#ibcon#*mode == 0, iclass 7, count 0 2006.224.07:48:18.49#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.224.07:48:18.49#ibcon#[25=USB\r\n] 2006.224.07:48:18.49#ibcon#*before write, iclass 7, count 0 2006.224.07:48:18.49#ibcon#enter sib2, iclass 7, count 0 2006.224.07:48:18.49#ibcon#flushed, iclass 7, count 0 2006.224.07:48:18.49#ibcon#about to write, iclass 7, count 0 2006.224.07:48:18.49#ibcon#wrote, iclass 7, count 0 2006.224.07:48:18.49#ibcon#about to read 3, iclass 7, count 0 2006.224.07:48:18.52#ibcon#read 3, iclass 7, count 0 2006.224.07:48:18.52#ibcon#about to read 4, iclass 7, count 0 2006.224.07:48:18.52#ibcon#read 4, iclass 7, count 0 2006.224.07:48:18.52#ibcon#about to read 5, iclass 7, count 0 2006.224.07:48:18.52#ibcon#read 5, iclass 7, count 0 2006.224.07:48:18.52#ibcon#about to read 6, iclass 7, count 0 2006.224.07:48:18.52#ibcon#read 6, iclass 7, count 0 2006.224.07:48:18.52#ibcon#end of sib2, iclass 7, count 0 2006.224.07:48:18.52#ibcon#*after write, iclass 7, count 0 2006.224.07:48:18.52#ibcon#*before return 0, iclass 7, count 0 2006.224.07:48:18.52#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.224.07:48:18.52#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.224.07:48:18.52#ibcon#about to clear, iclass 7 cls_cnt 0 2006.224.07:48:18.52#ibcon#cleared, iclass 7 cls_cnt 0 2006.224.07:48:18.52$vc4f8/valo=3,672.99 2006.224.07:48:18.52#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.224.07:48:18.52#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.224.07:48:18.52#ibcon#ireg 17 cls_cnt 0 2006.224.07:48:18.52#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.224.07:48:18.52#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.224.07:48:18.52#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.224.07:48:18.52#ibcon#enter wrdev, iclass 11, count 0 2006.224.07:48:18.52#ibcon#first serial, iclass 11, count 0 2006.224.07:48:18.52#ibcon#enter sib2, iclass 11, count 0 2006.224.07:48:18.52#ibcon#flushed, iclass 11, count 0 2006.224.07:48:18.52#ibcon#about to write, iclass 11, count 0 2006.224.07:48:18.52#ibcon#wrote, iclass 11, count 0 2006.224.07:48:18.52#ibcon#about to read 3, iclass 11, count 0 2006.224.07:48:18.55#ibcon#read 3, iclass 11, count 0 2006.224.07:48:18.55#ibcon#about to read 4, iclass 11, count 0 2006.224.07:48:18.55#ibcon#read 4, iclass 11, count 0 2006.224.07:48:18.55#ibcon#about to read 5, iclass 11, count 0 2006.224.07:48:18.55#ibcon#read 5, iclass 11, count 0 2006.224.07:48:18.55#ibcon#about to read 6, iclass 11, count 0 2006.224.07:48:18.55#ibcon#read 6, iclass 11, count 0 2006.224.07:48:18.55#ibcon#end of sib2, iclass 11, count 0 2006.224.07:48:18.55#ibcon#*mode == 0, iclass 11, count 0 2006.224.07:48:18.55#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.224.07:48:18.55#ibcon#[26=FRQ=03,672.99\r\n] 2006.224.07:48:18.55#ibcon#*before write, iclass 11, count 0 2006.224.07:48:18.55#ibcon#enter sib2, iclass 11, count 0 2006.224.07:48:18.55#ibcon#flushed, iclass 11, count 0 2006.224.07:48:18.55#ibcon#about to write, iclass 11, count 0 2006.224.07:48:18.55#ibcon#wrote, iclass 11, count 0 2006.224.07:48:18.55#ibcon#about to read 3, iclass 11, count 0 2006.224.07:48:18.59#ibcon#read 3, iclass 11, count 0 2006.224.07:48:18.59#ibcon#about to read 4, iclass 11, count 0 2006.224.07:48:18.59#ibcon#read 4, iclass 11, count 0 2006.224.07:48:18.59#ibcon#about to read 5, iclass 11, count 0 2006.224.07:48:18.59#ibcon#read 5, iclass 11, count 0 2006.224.07:48:18.59#ibcon#about to read 6, iclass 11, count 0 2006.224.07:48:18.59#ibcon#read 6, iclass 11, count 0 2006.224.07:48:18.59#ibcon#end of sib2, iclass 11, count 0 2006.224.07:48:18.59#ibcon#*after write, iclass 11, count 0 2006.224.07:48:18.59#ibcon#*before return 0, iclass 11, count 0 2006.224.07:48:18.59#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.224.07:48:18.59#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.224.07:48:18.59#ibcon#about to clear, iclass 11 cls_cnt 0 2006.224.07:48:18.59#ibcon#cleared, iclass 11 cls_cnt 0 2006.224.07:48:18.59$vc4f8/va=3,6 2006.224.07:48:18.59#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.224.07:48:18.59#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.224.07:48:18.59#ibcon#ireg 11 cls_cnt 2 2006.224.07:48:18.59#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.224.07:48:18.64#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.224.07:48:18.64#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.224.07:48:18.64#ibcon#enter wrdev, iclass 13, count 2 2006.224.07:48:18.64#ibcon#first serial, iclass 13, count 2 2006.224.07:48:18.64#ibcon#enter sib2, iclass 13, count 2 2006.224.07:48:18.64#ibcon#flushed, iclass 13, count 2 2006.224.07:48:18.64#ibcon#about to write, iclass 13, count 2 2006.224.07:48:18.64#ibcon#wrote, iclass 13, count 2 2006.224.07:48:18.64#ibcon#about to read 3, iclass 13, count 2 2006.224.07:48:18.66#ibcon#read 3, iclass 13, count 2 2006.224.07:48:18.66#ibcon#about to read 4, iclass 13, count 2 2006.224.07:48:18.66#ibcon#read 4, iclass 13, count 2 2006.224.07:48:18.66#ibcon#about to read 5, iclass 13, count 2 2006.224.07:48:18.66#ibcon#read 5, iclass 13, count 2 2006.224.07:48:18.66#ibcon#about to read 6, iclass 13, count 2 2006.224.07:48:18.66#ibcon#read 6, iclass 13, count 2 2006.224.07:48:18.66#ibcon#end of sib2, iclass 13, count 2 2006.224.07:48:18.66#ibcon#*mode == 0, iclass 13, count 2 2006.224.07:48:18.66#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.224.07:48:18.66#ibcon#[25=AT03-06\r\n] 2006.224.07:48:18.66#ibcon#*before write, iclass 13, count 2 2006.224.07:48:18.66#ibcon#enter sib2, iclass 13, count 2 2006.224.07:48:18.66#ibcon#flushed, iclass 13, count 2 2006.224.07:48:18.66#ibcon#about to write, iclass 13, count 2 2006.224.07:48:18.66#ibcon#wrote, iclass 13, count 2 2006.224.07:48:18.66#ibcon#about to read 3, iclass 13, count 2 2006.224.07:48:18.69#ibcon#read 3, iclass 13, count 2 2006.224.07:48:18.69#ibcon#about to read 4, iclass 13, count 2 2006.224.07:48:18.69#ibcon#read 4, iclass 13, count 2 2006.224.07:48:18.69#ibcon#about to read 5, iclass 13, count 2 2006.224.07:48:18.69#ibcon#read 5, iclass 13, count 2 2006.224.07:48:18.69#ibcon#about to read 6, iclass 13, count 2 2006.224.07:48:18.69#ibcon#read 6, iclass 13, count 2 2006.224.07:48:18.69#ibcon#end of sib2, iclass 13, count 2 2006.224.07:48:18.69#ibcon#*after write, iclass 13, count 2 2006.224.07:48:18.69#ibcon#*before return 0, iclass 13, count 2 2006.224.07:48:18.69#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.224.07:48:18.69#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.224.07:48:18.69#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.224.07:48:18.69#ibcon#ireg 7 cls_cnt 0 2006.224.07:48:18.69#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.224.07:48:18.81#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.224.07:48:18.81#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.224.07:48:18.81#ibcon#enter wrdev, iclass 13, count 0 2006.224.07:48:18.81#ibcon#first serial, iclass 13, count 0 2006.224.07:48:18.81#ibcon#enter sib2, iclass 13, count 0 2006.224.07:48:18.81#ibcon#flushed, iclass 13, count 0 2006.224.07:48:18.81#ibcon#about to write, iclass 13, count 0 2006.224.07:48:18.81#ibcon#wrote, iclass 13, count 0 2006.224.07:48:18.81#ibcon#about to read 3, iclass 13, count 0 2006.224.07:48:18.83#ibcon#read 3, iclass 13, count 0 2006.224.07:48:18.83#ibcon#about to read 4, iclass 13, count 0 2006.224.07:48:18.83#ibcon#read 4, iclass 13, count 0 2006.224.07:48:18.83#ibcon#about to read 5, iclass 13, count 0 2006.224.07:48:18.83#ibcon#read 5, iclass 13, count 0 2006.224.07:48:18.83#ibcon#about to read 6, iclass 13, count 0 2006.224.07:48:18.83#ibcon#read 6, iclass 13, count 0 2006.224.07:48:18.83#ibcon#end of sib2, iclass 13, count 0 2006.224.07:48:18.83#ibcon#*mode == 0, iclass 13, count 0 2006.224.07:48:18.83#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.224.07:48:18.83#ibcon#[25=USB\r\n] 2006.224.07:48:18.83#ibcon#*before write, iclass 13, count 0 2006.224.07:48:18.83#ibcon#enter sib2, iclass 13, count 0 2006.224.07:48:18.83#ibcon#flushed, iclass 13, count 0 2006.224.07:48:18.83#ibcon#about to write, iclass 13, count 0 2006.224.07:48:18.83#ibcon#wrote, iclass 13, count 0 2006.224.07:48:18.83#ibcon#about to read 3, iclass 13, count 0 2006.224.07:48:18.86#ibcon#read 3, iclass 13, count 0 2006.224.07:48:18.86#ibcon#about to read 4, iclass 13, count 0 2006.224.07:48:18.86#ibcon#read 4, iclass 13, count 0 2006.224.07:48:18.86#ibcon#about to read 5, iclass 13, count 0 2006.224.07:48:18.86#ibcon#read 5, iclass 13, count 0 2006.224.07:48:18.86#ibcon#about to read 6, iclass 13, count 0 2006.224.07:48:18.86#ibcon#read 6, iclass 13, count 0 2006.224.07:48:18.86#ibcon#end of sib2, iclass 13, count 0 2006.224.07:48:18.86#ibcon#*after write, iclass 13, count 0 2006.224.07:48:18.86#ibcon#*before return 0, iclass 13, count 0 2006.224.07:48:18.86#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.224.07:48:18.86#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.224.07:48:18.86#ibcon#about to clear, iclass 13 cls_cnt 0 2006.224.07:48:18.86#ibcon#cleared, iclass 13 cls_cnt 0 2006.224.07:48:18.86$vc4f8/valo=4,832.99 2006.224.07:48:18.86#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.224.07:48:18.86#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.224.07:48:18.86#ibcon#ireg 17 cls_cnt 0 2006.224.07:48:18.86#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.224.07:48:18.86#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.224.07:48:18.86#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.224.07:48:18.86#ibcon#enter wrdev, iclass 15, count 0 2006.224.07:48:18.86#ibcon#first serial, iclass 15, count 0 2006.224.07:48:18.86#ibcon#enter sib2, iclass 15, count 0 2006.224.07:48:18.86#ibcon#flushed, iclass 15, count 0 2006.224.07:48:18.86#ibcon#about to write, iclass 15, count 0 2006.224.07:48:18.86#ibcon#wrote, iclass 15, count 0 2006.224.07:48:18.86#ibcon#about to read 3, iclass 15, count 0 2006.224.07:48:18.88#ibcon#read 3, iclass 15, count 0 2006.224.07:48:18.88#ibcon#about to read 4, iclass 15, count 0 2006.224.07:48:18.88#ibcon#read 4, iclass 15, count 0 2006.224.07:48:18.88#ibcon#about to read 5, iclass 15, count 0 2006.224.07:48:18.88#ibcon#read 5, iclass 15, count 0 2006.224.07:48:18.88#ibcon#about to read 6, iclass 15, count 0 2006.224.07:48:18.88#ibcon#read 6, iclass 15, count 0 2006.224.07:48:18.88#ibcon#end of sib2, iclass 15, count 0 2006.224.07:48:18.88#ibcon#*mode == 0, iclass 15, count 0 2006.224.07:48:18.88#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.224.07:48:18.88#ibcon#[26=FRQ=04,832.99\r\n] 2006.224.07:48:18.88#ibcon#*before write, iclass 15, count 0 2006.224.07:48:18.88#ibcon#enter sib2, iclass 15, count 0 2006.224.07:48:18.88#ibcon#flushed, iclass 15, count 0 2006.224.07:48:18.88#ibcon#about to write, iclass 15, count 0 2006.224.07:48:18.88#ibcon#wrote, iclass 15, count 0 2006.224.07:48:18.88#ibcon#about to read 3, iclass 15, count 0 2006.224.07:48:18.92#ibcon#read 3, iclass 15, count 0 2006.224.07:48:18.92#ibcon#about to read 4, iclass 15, count 0 2006.224.07:48:18.92#ibcon#read 4, iclass 15, count 0 2006.224.07:48:18.92#ibcon#about to read 5, iclass 15, count 0 2006.224.07:48:18.92#ibcon#read 5, iclass 15, count 0 2006.224.07:48:18.92#ibcon#about to read 6, iclass 15, count 0 2006.224.07:48:18.92#ibcon#read 6, iclass 15, count 0 2006.224.07:48:18.92#ibcon#end of sib2, iclass 15, count 0 2006.224.07:48:18.92#ibcon#*after write, iclass 15, count 0 2006.224.07:48:18.92#ibcon#*before return 0, iclass 15, count 0 2006.224.07:48:18.92#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.224.07:48:18.92#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.224.07:48:18.92#ibcon#about to clear, iclass 15 cls_cnt 0 2006.224.07:48:18.92#ibcon#cleared, iclass 15 cls_cnt 0 2006.224.07:48:18.92$vc4f8/va=4,7 2006.224.07:48:18.92#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.224.07:48:18.92#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.224.07:48:18.92#ibcon#ireg 11 cls_cnt 2 2006.224.07:48:18.92#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.224.07:48:18.98#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.224.07:48:18.98#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.224.07:48:18.98#ibcon#enter wrdev, iclass 17, count 2 2006.224.07:48:18.98#ibcon#first serial, iclass 17, count 2 2006.224.07:48:18.98#ibcon#enter sib2, iclass 17, count 2 2006.224.07:48:18.98#ibcon#flushed, iclass 17, count 2 2006.224.07:48:18.98#ibcon#about to write, iclass 17, count 2 2006.224.07:48:18.98#ibcon#wrote, iclass 17, count 2 2006.224.07:48:18.98#ibcon#about to read 3, iclass 17, count 2 2006.224.07:48:19.00#ibcon#read 3, iclass 17, count 2 2006.224.07:48:19.00#ibcon#about to read 4, iclass 17, count 2 2006.224.07:48:19.00#ibcon#read 4, iclass 17, count 2 2006.224.07:48:19.00#ibcon#about to read 5, iclass 17, count 2 2006.224.07:48:19.00#ibcon#read 5, iclass 17, count 2 2006.224.07:48:19.00#ibcon#about to read 6, iclass 17, count 2 2006.224.07:48:19.00#ibcon#read 6, iclass 17, count 2 2006.224.07:48:19.00#ibcon#end of sib2, iclass 17, count 2 2006.224.07:48:19.00#ibcon#*mode == 0, iclass 17, count 2 2006.224.07:48:19.00#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.224.07:48:19.00#ibcon#[25=AT04-07\r\n] 2006.224.07:48:19.00#ibcon#*before write, iclass 17, count 2 2006.224.07:48:19.00#ibcon#enter sib2, iclass 17, count 2 2006.224.07:48:19.00#ibcon#flushed, iclass 17, count 2 2006.224.07:48:19.00#ibcon#about to write, iclass 17, count 2 2006.224.07:48:19.00#ibcon#wrote, iclass 17, count 2 2006.224.07:48:19.00#ibcon#about to read 3, iclass 17, count 2 2006.224.07:48:19.03#ibcon#read 3, iclass 17, count 2 2006.224.07:48:19.03#ibcon#about to read 4, iclass 17, count 2 2006.224.07:48:19.03#ibcon#read 4, iclass 17, count 2 2006.224.07:48:19.03#ibcon#about to read 5, iclass 17, count 2 2006.224.07:48:19.03#ibcon#read 5, iclass 17, count 2 2006.224.07:48:19.03#ibcon#about to read 6, iclass 17, count 2 2006.224.07:48:19.03#ibcon#read 6, iclass 17, count 2 2006.224.07:48:19.03#ibcon#end of sib2, iclass 17, count 2 2006.224.07:48:19.03#ibcon#*after write, iclass 17, count 2 2006.224.07:48:19.03#ibcon#*before return 0, iclass 17, count 2 2006.224.07:48:19.03#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.224.07:48:19.03#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.224.07:48:19.03#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.224.07:48:19.03#ibcon#ireg 7 cls_cnt 0 2006.224.07:48:19.03#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.224.07:48:19.15#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.224.07:48:19.15#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.224.07:48:19.15#ibcon#enter wrdev, iclass 17, count 0 2006.224.07:48:19.15#ibcon#first serial, iclass 17, count 0 2006.224.07:48:19.15#ibcon#enter sib2, iclass 17, count 0 2006.224.07:48:19.15#ibcon#flushed, iclass 17, count 0 2006.224.07:48:19.15#ibcon#about to write, iclass 17, count 0 2006.224.07:48:19.15#ibcon#wrote, iclass 17, count 0 2006.224.07:48:19.15#ibcon#about to read 3, iclass 17, count 0 2006.224.07:48:19.17#ibcon#read 3, iclass 17, count 0 2006.224.07:48:19.17#ibcon#about to read 4, iclass 17, count 0 2006.224.07:48:19.17#ibcon#read 4, iclass 17, count 0 2006.224.07:48:19.17#ibcon#about to read 5, iclass 17, count 0 2006.224.07:48:19.17#ibcon#read 5, iclass 17, count 0 2006.224.07:48:19.17#ibcon#about to read 6, iclass 17, count 0 2006.224.07:48:19.17#ibcon#read 6, iclass 17, count 0 2006.224.07:48:19.17#ibcon#end of sib2, iclass 17, count 0 2006.224.07:48:19.17#ibcon#*mode == 0, iclass 17, count 0 2006.224.07:48:19.17#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.224.07:48:19.17#ibcon#[25=USB\r\n] 2006.224.07:48:19.17#ibcon#*before write, iclass 17, count 0 2006.224.07:48:19.17#ibcon#enter sib2, iclass 17, count 0 2006.224.07:48:19.17#ibcon#flushed, iclass 17, count 0 2006.224.07:48:19.17#ibcon#about to write, iclass 17, count 0 2006.224.07:48:19.17#ibcon#wrote, iclass 17, count 0 2006.224.07:48:19.17#ibcon#about to read 3, iclass 17, count 0 2006.224.07:48:19.20#ibcon#read 3, iclass 17, count 0 2006.224.07:48:19.20#ibcon#about to read 4, iclass 17, count 0 2006.224.07:48:19.20#ibcon#read 4, iclass 17, count 0 2006.224.07:48:19.20#ibcon#about to read 5, iclass 17, count 0 2006.224.07:48:19.20#ibcon#read 5, iclass 17, count 0 2006.224.07:48:19.20#ibcon#about to read 6, iclass 17, count 0 2006.224.07:48:19.20#ibcon#read 6, iclass 17, count 0 2006.224.07:48:19.20#ibcon#end of sib2, iclass 17, count 0 2006.224.07:48:19.20#ibcon#*after write, iclass 17, count 0 2006.224.07:48:19.20#ibcon#*before return 0, iclass 17, count 0 2006.224.07:48:19.20#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.224.07:48:19.20#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.224.07:48:19.20#ibcon#about to clear, iclass 17 cls_cnt 0 2006.224.07:48:19.20#ibcon#cleared, iclass 17 cls_cnt 0 2006.224.07:48:19.20$vc4f8/valo=5,652.99 2006.224.07:48:19.20#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.224.07:48:19.20#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.224.07:48:19.20#ibcon#ireg 17 cls_cnt 0 2006.224.07:48:19.20#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.224.07:48:19.20#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.224.07:48:19.20#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.224.07:48:19.20#ibcon#enter wrdev, iclass 19, count 0 2006.224.07:48:19.20#ibcon#first serial, iclass 19, count 0 2006.224.07:48:19.20#ibcon#enter sib2, iclass 19, count 0 2006.224.07:48:19.20#ibcon#flushed, iclass 19, count 0 2006.224.07:48:19.20#ibcon#about to write, iclass 19, count 0 2006.224.07:48:19.20#ibcon#wrote, iclass 19, count 0 2006.224.07:48:19.20#ibcon#about to read 3, iclass 19, count 0 2006.224.07:48:19.22#ibcon#read 3, iclass 19, count 0 2006.224.07:48:19.22#ibcon#about to read 4, iclass 19, count 0 2006.224.07:48:19.22#ibcon#read 4, iclass 19, count 0 2006.224.07:48:19.22#ibcon#about to read 5, iclass 19, count 0 2006.224.07:48:19.22#ibcon#read 5, iclass 19, count 0 2006.224.07:48:19.22#ibcon#about to read 6, iclass 19, count 0 2006.224.07:48:19.22#ibcon#read 6, iclass 19, count 0 2006.224.07:48:19.22#ibcon#end of sib2, iclass 19, count 0 2006.224.07:48:19.22#ibcon#*mode == 0, iclass 19, count 0 2006.224.07:48:19.22#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.224.07:48:19.22#ibcon#[26=FRQ=05,652.99\r\n] 2006.224.07:48:19.22#ibcon#*before write, iclass 19, count 0 2006.224.07:48:19.22#ibcon#enter sib2, iclass 19, count 0 2006.224.07:48:19.22#ibcon#flushed, iclass 19, count 0 2006.224.07:48:19.22#ibcon#about to write, iclass 19, count 0 2006.224.07:48:19.22#ibcon#wrote, iclass 19, count 0 2006.224.07:48:19.22#ibcon#about to read 3, iclass 19, count 0 2006.224.07:48:19.26#ibcon#read 3, iclass 19, count 0 2006.224.07:48:19.26#ibcon#about to read 4, iclass 19, count 0 2006.224.07:48:19.26#ibcon#read 4, iclass 19, count 0 2006.224.07:48:19.26#ibcon#about to read 5, iclass 19, count 0 2006.224.07:48:19.26#ibcon#read 5, iclass 19, count 0 2006.224.07:48:19.26#ibcon#about to read 6, iclass 19, count 0 2006.224.07:48:19.26#ibcon#read 6, iclass 19, count 0 2006.224.07:48:19.26#ibcon#end of sib2, iclass 19, count 0 2006.224.07:48:19.26#ibcon#*after write, iclass 19, count 0 2006.224.07:48:19.26#ibcon#*before return 0, iclass 19, count 0 2006.224.07:48:19.26#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.224.07:48:19.26#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.224.07:48:19.26#ibcon#about to clear, iclass 19 cls_cnt 0 2006.224.07:48:19.26#ibcon#cleared, iclass 19 cls_cnt 0 2006.224.07:48:19.26$vc4f8/va=5,7 2006.224.07:48:19.26#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.224.07:48:19.26#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.224.07:48:19.26#ibcon#ireg 11 cls_cnt 2 2006.224.07:48:19.26#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.224.07:48:19.32#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.224.07:48:19.32#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.224.07:48:19.32#ibcon#enter wrdev, iclass 21, count 2 2006.224.07:48:19.32#ibcon#first serial, iclass 21, count 2 2006.224.07:48:19.32#ibcon#enter sib2, iclass 21, count 2 2006.224.07:48:19.32#ibcon#flushed, iclass 21, count 2 2006.224.07:48:19.32#ibcon#about to write, iclass 21, count 2 2006.224.07:48:19.32#ibcon#wrote, iclass 21, count 2 2006.224.07:48:19.32#ibcon#about to read 3, iclass 21, count 2 2006.224.07:48:19.34#ibcon#read 3, iclass 21, count 2 2006.224.07:48:19.34#ibcon#about to read 4, iclass 21, count 2 2006.224.07:48:19.34#ibcon#read 4, iclass 21, count 2 2006.224.07:48:19.34#ibcon#about to read 5, iclass 21, count 2 2006.224.07:48:19.34#ibcon#read 5, iclass 21, count 2 2006.224.07:48:19.34#ibcon#about to read 6, iclass 21, count 2 2006.224.07:48:19.34#ibcon#read 6, iclass 21, count 2 2006.224.07:48:19.34#ibcon#end of sib2, iclass 21, count 2 2006.224.07:48:19.34#ibcon#*mode == 0, iclass 21, count 2 2006.224.07:48:19.34#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.224.07:48:19.34#ibcon#[25=AT05-07\r\n] 2006.224.07:48:19.34#ibcon#*before write, iclass 21, count 2 2006.224.07:48:19.34#ibcon#enter sib2, iclass 21, count 2 2006.224.07:48:19.34#ibcon#flushed, iclass 21, count 2 2006.224.07:48:19.34#ibcon#about to write, iclass 21, count 2 2006.224.07:48:19.34#ibcon#wrote, iclass 21, count 2 2006.224.07:48:19.34#ibcon#about to read 3, iclass 21, count 2 2006.224.07:48:19.37#ibcon#read 3, iclass 21, count 2 2006.224.07:48:19.37#ibcon#about to read 4, iclass 21, count 2 2006.224.07:48:19.37#ibcon#read 4, iclass 21, count 2 2006.224.07:48:19.37#ibcon#about to read 5, iclass 21, count 2 2006.224.07:48:19.37#ibcon#read 5, iclass 21, count 2 2006.224.07:48:19.37#ibcon#about to read 6, iclass 21, count 2 2006.224.07:48:19.37#ibcon#read 6, iclass 21, count 2 2006.224.07:48:19.37#ibcon#end of sib2, iclass 21, count 2 2006.224.07:48:19.37#ibcon#*after write, iclass 21, count 2 2006.224.07:48:19.37#ibcon#*before return 0, iclass 21, count 2 2006.224.07:48:19.37#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.224.07:48:19.37#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.224.07:48:19.37#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.224.07:48:19.37#ibcon#ireg 7 cls_cnt 0 2006.224.07:48:19.37#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.224.07:48:19.49#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.224.07:48:19.49#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.224.07:48:19.49#ibcon#enter wrdev, iclass 21, count 0 2006.224.07:48:19.49#ibcon#first serial, iclass 21, count 0 2006.224.07:48:19.49#ibcon#enter sib2, iclass 21, count 0 2006.224.07:48:19.49#ibcon#flushed, iclass 21, count 0 2006.224.07:48:19.49#ibcon#about to write, iclass 21, count 0 2006.224.07:48:19.49#ibcon#wrote, iclass 21, count 0 2006.224.07:48:19.49#ibcon#about to read 3, iclass 21, count 0 2006.224.07:48:19.51#ibcon#read 3, iclass 21, count 0 2006.224.07:48:19.51#ibcon#about to read 4, iclass 21, count 0 2006.224.07:48:19.51#ibcon#read 4, iclass 21, count 0 2006.224.07:48:19.51#ibcon#about to read 5, iclass 21, count 0 2006.224.07:48:19.51#ibcon#read 5, iclass 21, count 0 2006.224.07:48:19.51#ibcon#about to read 6, iclass 21, count 0 2006.224.07:48:19.51#ibcon#read 6, iclass 21, count 0 2006.224.07:48:19.51#ibcon#end of sib2, iclass 21, count 0 2006.224.07:48:19.51#ibcon#*mode == 0, iclass 21, count 0 2006.224.07:48:19.51#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.224.07:48:19.51#ibcon#[25=USB\r\n] 2006.224.07:48:19.51#ibcon#*before write, iclass 21, count 0 2006.224.07:48:19.51#ibcon#enter sib2, iclass 21, count 0 2006.224.07:48:19.51#ibcon#flushed, iclass 21, count 0 2006.224.07:48:19.51#ibcon#about to write, iclass 21, count 0 2006.224.07:48:19.51#ibcon#wrote, iclass 21, count 0 2006.224.07:48:19.51#ibcon#about to read 3, iclass 21, count 0 2006.224.07:48:19.54#ibcon#read 3, iclass 21, count 0 2006.224.07:48:19.54#ibcon#about to read 4, iclass 21, count 0 2006.224.07:48:19.54#ibcon#read 4, iclass 21, count 0 2006.224.07:48:19.54#ibcon#about to read 5, iclass 21, count 0 2006.224.07:48:19.54#ibcon#read 5, iclass 21, count 0 2006.224.07:48:19.54#ibcon#about to read 6, iclass 21, count 0 2006.224.07:48:19.54#ibcon#read 6, iclass 21, count 0 2006.224.07:48:19.54#ibcon#end of sib2, iclass 21, count 0 2006.224.07:48:19.54#ibcon#*after write, iclass 21, count 0 2006.224.07:48:19.54#ibcon#*before return 0, iclass 21, count 0 2006.224.07:48:19.54#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.224.07:48:19.54#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.224.07:48:19.54#ibcon#about to clear, iclass 21 cls_cnt 0 2006.224.07:48:19.54#ibcon#cleared, iclass 21 cls_cnt 0 2006.224.07:48:19.54$vc4f8/valo=6,772.99 2006.224.07:48:19.54#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.224.07:48:19.54#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.224.07:48:19.54#ibcon#ireg 17 cls_cnt 0 2006.224.07:48:19.54#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.224.07:48:19.54#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.224.07:48:19.54#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.224.07:48:19.54#ibcon#enter wrdev, iclass 23, count 0 2006.224.07:48:19.54#ibcon#first serial, iclass 23, count 0 2006.224.07:48:19.54#ibcon#enter sib2, iclass 23, count 0 2006.224.07:48:19.54#ibcon#flushed, iclass 23, count 0 2006.224.07:48:19.54#ibcon#about to write, iclass 23, count 0 2006.224.07:48:19.54#ibcon#wrote, iclass 23, count 0 2006.224.07:48:19.54#ibcon#about to read 3, iclass 23, count 0 2006.224.07:48:19.56#ibcon#read 3, iclass 23, count 0 2006.224.07:48:19.56#ibcon#about to read 4, iclass 23, count 0 2006.224.07:48:19.56#ibcon#read 4, iclass 23, count 0 2006.224.07:48:19.56#ibcon#about to read 5, iclass 23, count 0 2006.224.07:48:19.56#ibcon#read 5, iclass 23, count 0 2006.224.07:48:19.56#ibcon#about to read 6, iclass 23, count 0 2006.224.07:48:19.56#ibcon#read 6, iclass 23, count 0 2006.224.07:48:19.56#ibcon#end of sib2, iclass 23, count 0 2006.224.07:48:19.56#ibcon#*mode == 0, iclass 23, count 0 2006.224.07:48:19.56#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.224.07:48:19.56#ibcon#[26=FRQ=06,772.99\r\n] 2006.224.07:48:19.56#ibcon#*before write, iclass 23, count 0 2006.224.07:48:19.56#ibcon#enter sib2, iclass 23, count 0 2006.224.07:48:19.56#ibcon#flushed, iclass 23, count 0 2006.224.07:48:19.56#ibcon#about to write, iclass 23, count 0 2006.224.07:48:19.57#ibcon#wrote, iclass 23, count 0 2006.224.07:48:19.57#ibcon#about to read 3, iclass 23, count 0 2006.224.07:48:19.61#ibcon#read 3, iclass 23, count 0 2006.224.07:48:19.61#ibcon#about to read 4, iclass 23, count 0 2006.224.07:48:19.61#ibcon#read 4, iclass 23, count 0 2006.224.07:48:19.61#ibcon#about to read 5, iclass 23, count 0 2006.224.07:48:19.61#ibcon#read 5, iclass 23, count 0 2006.224.07:48:19.61#ibcon#about to read 6, iclass 23, count 0 2006.224.07:48:19.61#ibcon#read 6, iclass 23, count 0 2006.224.07:48:19.61#ibcon#end of sib2, iclass 23, count 0 2006.224.07:48:19.61#ibcon#*after write, iclass 23, count 0 2006.224.07:48:19.61#ibcon#*before return 0, iclass 23, count 0 2006.224.07:48:19.61#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.224.07:48:19.61#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.224.07:48:19.61#ibcon#about to clear, iclass 23 cls_cnt 0 2006.224.07:48:19.61#ibcon#cleared, iclass 23 cls_cnt 0 2006.224.07:48:19.61$vc4f8/va=6,6 2006.224.07:48:19.61#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.224.07:48:19.61#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.224.07:48:19.61#ibcon#ireg 11 cls_cnt 2 2006.224.07:48:19.61#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.224.07:48:19.65#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.224.07:48:19.65#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.224.07:48:19.65#ibcon#enter wrdev, iclass 25, count 2 2006.224.07:48:19.65#ibcon#first serial, iclass 25, count 2 2006.224.07:48:19.65#ibcon#enter sib2, iclass 25, count 2 2006.224.07:48:19.65#ibcon#flushed, iclass 25, count 2 2006.224.07:48:19.65#ibcon#about to write, iclass 25, count 2 2006.224.07:48:19.65#ibcon#wrote, iclass 25, count 2 2006.224.07:48:19.65#ibcon#about to read 3, iclass 25, count 2 2006.224.07:48:19.67#ibcon#read 3, iclass 25, count 2 2006.224.07:48:19.67#ibcon#about to read 4, iclass 25, count 2 2006.224.07:48:19.67#ibcon#read 4, iclass 25, count 2 2006.224.07:48:19.67#ibcon#about to read 5, iclass 25, count 2 2006.224.07:48:19.67#ibcon#read 5, iclass 25, count 2 2006.224.07:48:19.67#ibcon#about to read 6, iclass 25, count 2 2006.224.07:48:19.67#ibcon#read 6, iclass 25, count 2 2006.224.07:48:19.67#ibcon#end of sib2, iclass 25, count 2 2006.224.07:48:19.67#ibcon#*mode == 0, iclass 25, count 2 2006.224.07:48:19.67#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.224.07:48:19.67#ibcon#[25=AT06-06\r\n] 2006.224.07:48:19.67#ibcon#*before write, iclass 25, count 2 2006.224.07:48:19.67#ibcon#enter sib2, iclass 25, count 2 2006.224.07:48:19.67#ibcon#flushed, iclass 25, count 2 2006.224.07:48:19.67#ibcon#about to write, iclass 25, count 2 2006.224.07:48:19.67#ibcon#wrote, iclass 25, count 2 2006.224.07:48:19.67#ibcon#about to read 3, iclass 25, count 2 2006.224.07:48:19.70#ibcon#read 3, iclass 25, count 2 2006.224.07:48:19.70#ibcon#about to read 4, iclass 25, count 2 2006.224.07:48:19.70#ibcon#read 4, iclass 25, count 2 2006.224.07:48:19.70#ibcon#about to read 5, iclass 25, count 2 2006.224.07:48:19.70#ibcon#read 5, iclass 25, count 2 2006.224.07:48:19.70#ibcon#about to read 6, iclass 25, count 2 2006.224.07:48:19.70#ibcon#read 6, iclass 25, count 2 2006.224.07:48:19.70#ibcon#end of sib2, iclass 25, count 2 2006.224.07:48:19.70#ibcon#*after write, iclass 25, count 2 2006.224.07:48:19.70#ibcon#*before return 0, iclass 25, count 2 2006.224.07:48:19.70#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.224.07:48:19.70#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.224.07:48:19.70#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.224.07:48:19.70#ibcon#ireg 7 cls_cnt 0 2006.224.07:48:19.70#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.224.07:48:19.82#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.224.07:48:19.82#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.224.07:48:19.82#ibcon#enter wrdev, iclass 25, count 0 2006.224.07:48:19.82#ibcon#first serial, iclass 25, count 0 2006.224.07:48:19.82#ibcon#enter sib2, iclass 25, count 0 2006.224.07:48:19.82#ibcon#flushed, iclass 25, count 0 2006.224.07:48:19.82#ibcon#about to write, iclass 25, count 0 2006.224.07:48:19.82#ibcon#wrote, iclass 25, count 0 2006.224.07:48:19.82#ibcon#about to read 3, iclass 25, count 0 2006.224.07:48:19.84#ibcon#read 3, iclass 25, count 0 2006.224.07:48:19.84#ibcon#about to read 4, iclass 25, count 0 2006.224.07:48:19.84#ibcon#read 4, iclass 25, count 0 2006.224.07:48:19.84#ibcon#about to read 5, iclass 25, count 0 2006.224.07:48:19.84#ibcon#read 5, iclass 25, count 0 2006.224.07:48:19.84#ibcon#about to read 6, iclass 25, count 0 2006.224.07:48:19.84#ibcon#read 6, iclass 25, count 0 2006.224.07:48:19.84#ibcon#end of sib2, iclass 25, count 0 2006.224.07:48:19.84#ibcon#*mode == 0, iclass 25, count 0 2006.224.07:48:19.84#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.224.07:48:19.84#ibcon#[25=USB\r\n] 2006.224.07:48:19.84#ibcon#*before write, iclass 25, count 0 2006.224.07:48:19.84#ibcon#enter sib2, iclass 25, count 0 2006.224.07:48:19.84#ibcon#flushed, iclass 25, count 0 2006.224.07:48:19.84#ibcon#about to write, iclass 25, count 0 2006.224.07:48:19.84#ibcon#wrote, iclass 25, count 0 2006.224.07:48:19.84#ibcon#about to read 3, iclass 25, count 0 2006.224.07:48:19.86#abcon#<5=/08 0.3 0.9 23.601001004.2\r\n> 2006.224.07:48:19.87#ibcon#read 3, iclass 25, count 0 2006.224.07:48:19.87#ibcon#about to read 4, iclass 25, count 0 2006.224.07:48:19.87#ibcon#read 4, iclass 25, count 0 2006.224.07:48:19.87#ibcon#about to read 5, iclass 25, count 0 2006.224.07:48:19.87#ibcon#read 5, iclass 25, count 0 2006.224.07:48:19.87#ibcon#about to read 6, iclass 25, count 0 2006.224.07:48:19.87#ibcon#read 6, iclass 25, count 0 2006.224.07:48:19.87#ibcon#end of sib2, iclass 25, count 0 2006.224.07:48:19.87#ibcon#*after write, iclass 25, count 0 2006.224.07:48:19.87#ibcon#*before return 0, iclass 25, count 0 2006.224.07:48:19.87#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.224.07:48:19.87#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.224.07:48:19.87#ibcon#about to clear, iclass 25 cls_cnt 0 2006.224.07:48:19.87#ibcon#cleared, iclass 25 cls_cnt 0 2006.224.07:48:19.87$vc4f8/valo=7,832.99 2006.224.07:48:19.87#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.224.07:48:19.87#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.224.07:48:19.87#ibcon#ireg 17 cls_cnt 0 2006.224.07:48:19.87#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.224.07:48:19.87#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.224.07:48:19.87#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.224.07:48:19.87#ibcon#enter wrdev, iclass 30, count 0 2006.224.07:48:19.87#ibcon#first serial, iclass 30, count 0 2006.224.07:48:19.87#ibcon#enter sib2, iclass 30, count 0 2006.224.07:48:19.87#ibcon#flushed, iclass 30, count 0 2006.224.07:48:19.87#ibcon#about to write, iclass 30, count 0 2006.224.07:48:19.87#ibcon#wrote, iclass 30, count 0 2006.224.07:48:19.87#ibcon#about to read 3, iclass 30, count 0 2006.224.07:48:19.88#abcon#{5=INTERFACE CLEAR} 2006.224.07:48:19.89#ibcon#read 3, iclass 30, count 0 2006.224.07:48:19.89#ibcon#about to read 4, iclass 30, count 0 2006.224.07:48:19.89#ibcon#read 4, iclass 30, count 0 2006.224.07:48:19.89#ibcon#about to read 5, iclass 30, count 0 2006.224.07:48:19.89#ibcon#read 5, iclass 30, count 0 2006.224.07:48:19.89#ibcon#about to read 6, iclass 30, count 0 2006.224.07:48:19.89#ibcon#read 6, iclass 30, count 0 2006.224.07:48:19.89#ibcon#end of sib2, iclass 30, count 0 2006.224.07:48:19.89#ibcon#*mode == 0, iclass 30, count 0 2006.224.07:48:19.89#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.224.07:48:19.89#ibcon#[26=FRQ=07,832.99\r\n] 2006.224.07:48:19.89#ibcon#*before write, iclass 30, count 0 2006.224.07:48:19.89#ibcon#enter sib2, iclass 30, count 0 2006.224.07:48:19.89#ibcon#flushed, iclass 30, count 0 2006.224.07:48:19.89#ibcon#about to write, iclass 30, count 0 2006.224.07:48:19.89#ibcon#wrote, iclass 30, count 0 2006.224.07:48:19.89#ibcon#about to read 3, iclass 30, count 0 2006.224.07:48:19.93#ibcon#read 3, iclass 30, count 0 2006.224.07:48:19.93#ibcon#about to read 4, iclass 30, count 0 2006.224.07:48:19.93#ibcon#read 4, iclass 30, count 0 2006.224.07:48:19.93#ibcon#about to read 5, iclass 30, count 0 2006.224.07:48:19.93#ibcon#read 5, iclass 30, count 0 2006.224.07:48:19.93#ibcon#about to read 6, iclass 30, count 0 2006.224.07:48:19.93#ibcon#read 6, iclass 30, count 0 2006.224.07:48:19.93#ibcon#end of sib2, iclass 30, count 0 2006.224.07:48:19.93#ibcon#*after write, iclass 30, count 0 2006.224.07:48:19.93#ibcon#*before return 0, iclass 30, count 0 2006.224.07:48:19.93#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.224.07:48:19.93#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.224.07:48:19.93#ibcon#about to clear, iclass 30 cls_cnt 0 2006.224.07:48:19.93#ibcon#cleared, iclass 30 cls_cnt 0 2006.224.07:48:19.93$vc4f8/va=7,6 2006.224.07:48:19.93#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.224.07:48:19.93#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.224.07:48:19.93#ibcon#ireg 11 cls_cnt 2 2006.224.07:48:19.93#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.224.07:48:19.94#abcon#[5=S1D000X0/0*\r\n] 2006.224.07:48:19.99#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.224.07:48:19.99#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.224.07:48:19.99#ibcon#enter wrdev, iclass 33, count 2 2006.224.07:48:19.99#ibcon#first serial, iclass 33, count 2 2006.224.07:48:19.99#ibcon#enter sib2, iclass 33, count 2 2006.224.07:48:19.99#ibcon#flushed, iclass 33, count 2 2006.224.07:48:19.99#ibcon#about to write, iclass 33, count 2 2006.224.07:48:19.99#ibcon#wrote, iclass 33, count 2 2006.224.07:48:19.99#ibcon#about to read 3, iclass 33, count 2 2006.224.07:48:20.01#ibcon#read 3, iclass 33, count 2 2006.224.07:48:20.01#ibcon#about to read 4, iclass 33, count 2 2006.224.07:48:20.01#ibcon#read 4, iclass 33, count 2 2006.224.07:48:20.01#ibcon#about to read 5, iclass 33, count 2 2006.224.07:48:20.01#ibcon#read 5, iclass 33, count 2 2006.224.07:48:20.01#ibcon#about to read 6, iclass 33, count 2 2006.224.07:48:20.01#ibcon#read 6, iclass 33, count 2 2006.224.07:48:20.01#ibcon#end of sib2, iclass 33, count 2 2006.224.07:48:20.01#ibcon#*mode == 0, iclass 33, count 2 2006.224.07:48:20.01#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.224.07:48:20.01#ibcon#[25=AT07-06\r\n] 2006.224.07:48:20.01#ibcon#*before write, iclass 33, count 2 2006.224.07:48:20.01#ibcon#enter sib2, iclass 33, count 2 2006.224.07:48:20.01#ibcon#flushed, iclass 33, count 2 2006.224.07:48:20.01#ibcon#about to write, iclass 33, count 2 2006.224.07:48:20.01#ibcon#wrote, iclass 33, count 2 2006.224.07:48:20.01#ibcon#about to read 3, iclass 33, count 2 2006.224.07:48:20.04#ibcon#read 3, iclass 33, count 2 2006.224.07:48:20.04#ibcon#about to read 4, iclass 33, count 2 2006.224.07:48:20.04#ibcon#read 4, iclass 33, count 2 2006.224.07:48:20.04#ibcon#about to read 5, iclass 33, count 2 2006.224.07:48:20.04#ibcon#read 5, iclass 33, count 2 2006.224.07:48:20.04#ibcon#about to read 6, iclass 33, count 2 2006.224.07:48:20.04#ibcon#read 6, iclass 33, count 2 2006.224.07:48:20.04#ibcon#end of sib2, iclass 33, count 2 2006.224.07:48:20.04#ibcon#*after write, iclass 33, count 2 2006.224.07:48:20.04#ibcon#*before return 0, iclass 33, count 2 2006.224.07:48:20.04#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.224.07:48:20.04#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.224.07:48:20.04#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.224.07:48:20.04#ibcon#ireg 7 cls_cnt 0 2006.224.07:48:20.04#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.224.07:48:20.16#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.224.07:48:20.16#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.224.07:48:20.16#ibcon#enter wrdev, iclass 33, count 0 2006.224.07:48:20.16#ibcon#first serial, iclass 33, count 0 2006.224.07:48:20.16#ibcon#enter sib2, iclass 33, count 0 2006.224.07:48:20.16#ibcon#flushed, iclass 33, count 0 2006.224.07:48:20.16#ibcon#about to write, iclass 33, count 0 2006.224.07:48:20.16#ibcon#wrote, iclass 33, count 0 2006.224.07:48:20.16#ibcon#about to read 3, iclass 33, count 0 2006.224.07:48:20.18#ibcon#read 3, iclass 33, count 0 2006.224.07:48:20.18#ibcon#about to read 4, iclass 33, count 0 2006.224.07:48:20.18#ibcon#read 4, iclass 33, count 0 2006.224.07:48:20.18#ibcon#about to read 5, iclass 33, count 0 2006.224.07:48:20.18#ibcon#read 5, iclass 33, count 0 2006.224.07:48:20.18#ibcon#about to read 6, iclass 33, count 0 2006.224.07:48:20.18#ibcon#read 6, iclass 33, count 0 2006.224.07:48:20.18#ibcon#end of sib2, iclass 33, count 0 2006.224.07:48:20.18#ibcon#*mode == 0, iclass 33, count 0 2006.224.07:48:20.18#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.224.07:48:20.18#ibcon#[25=USB\r\n] 2006.224.07:48:20.18#ibcon#*before write, iclass 33, count 0 2006.224.07:48:20.18#ibcon#enter sib2, iclass 33, count 0 2006.224.07:48:20.18#ibcon#flushed, iclass 33, count 0 2006.224.07:48:20.18#ibcon#about to write, iclass 33, count 0 2006.224.07:48:20.18#ibcon#wrote, iclass 33, count 0 2006.224.07:48:20.18#ibcon#about to read 3, iclass 33, count 0 2006.224.07:48:20.21#ibcon#read 3, iclass 33, count 0 2006.224.07:48:20.21#ibcon#about to read 4, iclass 33, count 0 2006.224.07:48:20.21#ibcon#read 4, iclass 33, count 0 2006.224.07:48:20.21#ibcon#about to read 5, iclass 33, count 0 2006.224.07:48:20.21#ibcon#read 5, iclass 33, count 0 2006.224.07:48:20.21#ibcon#about to read 6, iclass 33, count 0 2006.224.07:48:20.21#ibcon#read 6, iclass 33, count 0 2006.224.07:48:20.21#ibcon#end of sib2, iclass 33, count 0 2006.224.07:48:20.21#ibcon#*after write, iclass 33, count 0 2006.224.07:48:20.21#ibcon#*before return 0, iclass 33, count 0 2006.224.07:48:20.21#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.224.07:48:20.21#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.224.07:48:20.21#ibcon#about to clear, iclass 33 cls_cnt 0 2006.224.07:48:20.21#ibcon#cleared, iclass 33 cls_cnt 0 2006.224.07:48:20.21$vc4f8/valo=8,852.99 2006.224.07:48:20.21#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.224.07:48:20.21#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.224.07:48:20.21#ibcon#ireg 17 cls_cnt 0 2006.224.07:48:20.21#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.224.07:48:20.21#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.224.07:48:20.21#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.224.07:48:20.21#ibcon#enter wrdev, iclass 35, count 0 2006.224.07:48:20.21#ibcon#first serial, iclass 35, count 0 2006.224.07:48:20.21#ibcon#enter sib2, iclass 35, count 0 2006.224.07:48:20.21#ibcon#flushed, iclass 35, count 0 2006.224.07:48:20.21#ibcon#about to write, iclass 35, count 0 2006.224.07:48:20.21#ibcon#wrote, iclass 35, count 0 2006.224.07:48:20.21#ibcon#about to read 3, iclass 35, count 0 2006.224.07:48:20.23#ibcon#read 3, iclass 35, count 0 2006.224.07:48:20.23#ibcon#about to read 4, iclass 35, count 0 2006.224.07:48:20.23#ibcon#read 4, iclass 35, count 0 2006.224.07:48:20.23#ibcon#about to read 5, iclass 35, count 0 2006.224.07:48:20.23#ibcon#read 5, iclass 35, count 0 2006.224.07:48:20.23#ibcon#about to read 6, iclass 35, count 0 2006.224.07:48:20.23#ibcon#read 6, iclass 35, count 0 2006.224.07:48:20.23#ibcon#end of sib2, iclass 35, count 0 2006.224.07:48:20.23#ibcon#*mode == 0, iclass 35, count 0 2006.224.07:48:20.23#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.224.07:48:20.23#ibcon#[26=FRQ=08,852.99\r\n] 2006.224.07:48:20.23#ibcon#*before write, iclass 35, count 0 2006.224.07:48:20.23#ibcon#enter sib2, iclass 35, count 0 2006.224.07:48:20.23#ibcon#flushed, iclass 35, count 0 2006.224.07:48:20.23#ibcon#about to write, iclass 35, count 0 2006.224.07:48:20.23#ibcon#wrote, iclass 35, count 0 2006.224.07:48:20.23#ibcon#about to read 3, iclass 35, count 0 2006.224.07:48:20.27#ibcon#read 3, iclass 35, count 0 2006.224.07:48:20.27#ibcon#about to read 4, iclass 35, count 0 2006.224.07:48:20.27#ibcon#read 4, iclass 35, count 0 2006.224.07:48:20.27#ibcon#about to read 5, iclass 35, count 0 2006.224.07:48:20.27#ibcon#read 5, iclass 35, count 0 2006.224.07:48:20.27#ibcon#about to read 6, iclass 35, count 0 2006.224.07:48:20.27#ibcon#read 6, iclass 35, count 0 2006.224.07:48:20.27#ibcon#end of sib2, iclass 35, count 0 2006.224.07:48:20.27#ibcon#*after write, iclass 35, count 0 2006.224.07:48:20.27#ibcon#*before return 0, iclass 35, count 0 2006.224.07:48:20.27#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.224.07:48:20.27#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.224.07:48:20.27#ibcon#about to clear, iclass 35 cls_cnt 0 2006.224.07:48:20.27#ibcon#cleared, iclass 35 cls_cnt 0 2006.224.07:48:20.27$vc4f8/va=8,7 2006.224.07:48:20.27#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.224.07:48:20.27#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.224.07:48:20.27#ibcon#ireg 11 cls_cnt 2 2006.224.07:48:20.27#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.224.07:48:20.33#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.224.07:48:20.33#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.224.07:48:20.33#ibcon#enter wrdev, iclass 37, count 2 2006.224.07:48:20.33#ibcon#first serial, iclass 37, count 2 2006.224.07:48:20.33#ibcon#enter sib2, iclass 37, count 2 2006.224.07:48:20.33#ibcon#flushed, iclass 37, count 2 2006.224.07:48:20.33#ibcon#about to write, iclass 37, count 2 2006.224.07:48:20.33#ibcon#wrote, iclass 37, count 2 2006.224.07:48:20.33#ibcon#about to read 3, iclass 37, count 2 2006.224.07:48:20.35#ibcon#read 3, iclass 37, count 2 2006.224.07:48:20.35#ibcon#about to read 4, iclass 37, count 2 2006.224.07:48:20.35#ibcon#read 4, iclass 37, count 2 2006.224.07:48:20.35#ibcon#about to read 5, iclass 37, count 2 2006.224.07:48:20.35#ibcon#read 5, iclass 37, count 2 2006.224.07:48:20.35#ibcon#about to read 6, iclass 37, count 2 2006.224.07:48:20.35#ibcon#read 6, iclass 37, count 2 2006.224.07:48:20.35#ibcon#end of sib2, iclass 37, count 2 2006.224.07:48:20.35#ibcon#*mode == 0, iclass 37, count 2 2006.224.07:48:20.35#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.224.07:48:20.35#ibcon#[25=AT08-07\r\n] 2006.224.07:48:20.35#ibcon#*before write, iclass 37, count 2 2006.224.07:48:20.35#ibcon#enter sib2, iclass 37, count 2 2006.224.07:48:20.35#ibcon#flushed, iclass 37, count 2 2006.224.07:48:20.35#ibcon#about to write, iclass 37, count 2 2006.224.07:48:20.35#ibcon#wrote, iclass 37, count 2 2006.224.07:48:20.35#ibcon#about to read 3, iclass 37, count 2 2006.224.07:48:20.38#ibcon#read 3, iclass 37, count 2 2006.224.07:48:20.38#ibcon#about to read 4, iclass 37, count 2 2006.224.07:48:20.38#ibcon#read 4, iclass 37, count 2 2006.224.07:48:20.38#ibcon#about to read 5, iclass 37, count 2 2006.224.07:48:20.38#ibcon#read 5, iclass 37, count 2 2006.224.07:48:20.38#ibcon#about to read 6, iclass 37, count 2 2006.224.07:48:20.38#ibcon#read 6, iclass 37, count 2 2006.224.07:48:20.38#ibcon#end of sib2, iclass 37, count 2 2006.224.07:48:20.38#ibcon#*after write, iclass 37, count 2 2006.224.07:48:20.38#ibcon#*before return 0, iclass 37, count 2 2006.224.07:48:20.38#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.224.07:48:20.38#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.224.07:48:20.38#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.224.07:48:20.38#ibcon#ireg 7 cls_cnt 0 2006.224.07:48:20.38#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.224.07:48:20.51#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.224.07:48:20.51#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.224.07:48:20.51#ibcon#enter wrdev, iclass 37, count 0 2006.224.07:48:20.51#ibcon#first serial, iclass 37, count 0 2006.224.07:48:20.51#ibcon#enter sib2, iclass 37, count 0 2006.224.07:48:20.51#ibcon#flushed, iclass 37, count 0 2006.224.07:48:20.51#ibcon#about to write, iclass 37, count 0 2006.224.07:48:20.51#ibcon#wrote, iclass 37, count 0 2006.224.07:48:20.51#ibcon#about to read 3, iclass 37, count 0 2006.224.07:48:20.52#ibcon#read 3, iclass 37, count 0 2006.224.07:48:20.52#ibcon#about to read 4, iclass 37, count 0 2006.224.07:48:20.52#ibcon#read 4, iclass 37, count 0 2006.224.07:48:20.52#ibcon#about to read 5, iclass 37, count 0 2006.224.07:48:20.52#ibcon#read 5, iclass 37, count 0 2006.224.07:48:20.52#ibcon#about to read 6, iclass 37, count 0 2006.224.07:48:20.52#ibcon#read 6, iclass 37, count 0 2006.224.07:48:20.52#ibcon#end of sib2, iclass 37, count 0 2006.224.07:48:20.52#ibcon#*mode == 0, iclass 37, count 0 2006.224.07:48:20.52#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.224.07:48:20.52#ibcon#[25=USB\r\n] 2006.224.07:48:20.52#ibcon#*before write, iclass 37, count 0 2006.224.07:48:20.52#ibcon#enter sib2, iclass 37, count 0 2006.224.07:48:20.52#ibcon#flushed, iclass 37, count 0 2006.224.07:48:20.52#ibcon#about to write, iclass 37, count 0 2006.224.07:48:20.52#ibcon#wrote, iclass 37, count 0 2006.224.07:48:20.52#ibcon#about to read 3, iclass 37, count 0 2006.224.07:48:20.55#ibcon#read 3, iclass 37, count 0 2006.224.07:48:20.55#ibcon#about to read 4, iclass 37, count 0 2006.224.07:48:20.55#ibcon#read 4, iclass 37, count 0 2006.224.07:48:20.55#ibcon#about to read 5, iclass 37, count 0 2006.224.07:48:20.55#ibcon#read 5, iclass 37, count 0 2006.224.07:48:20.55#ibcon#about to read 6, iclass 37, count 0 2006.224.07:48:20.55#ibcon#read 6, iclass 37, count 0 2006.224.07:48:20.55#ibcon#end of sib2, iclass 37, count 0 2006.224.07:48:20.55#ibcon#*after write, iclass 37, count 0 2006.224.07:48:20.55#ibcon#*before return 0, iclass 37, count 0 2006.224.07:48:20.55#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.224.07:48:20.55#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.224.07:48:20.55#ibcon#about to clear, iclass 37 cls_cnt 0 2006.224.07:48:20.55#ibcon#cleared, iclass 37 cls_cnt 0 2006.224.07:48:20.55$vc4f8/vblo=1,632.99 2006.224.07:48:20.55#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.224.07:48:20.55#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.224.07:48:20.55#ibcon#ireg 17 cls_cnt 0 2006.224.07:48:20.55#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.224.07:48:20.55#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.224.07:48:20.55#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.224.07:48:20.55#ibcon#enter wrdev, iclass 39, count 0 2006.224.07:48:20.55#ibcon#first serial, iclass 39, count 0 2006.224.07:48:20.55#ibcon#enter sib2, iclass 39, count 0 2006.224.07:48:20.55#ibcon#flushed, iclass 39, count 0 2006.224.07:48:20.55#ibcon#about to write, iclass 39, count 0 2006.224.07:48:20.55#ibcon#wrote, iclass 39, count 0 2006.224.07:48:20.55#ibcon#about to read 3, iclass 39, count 0 2006.224.07:48:20.57#ibcon#read 3, iclass 39, count 0 2006.224.07:48:20.57#ibcon#about to read 4, iclass 39, count 0 2006.224.07:48:20.57#ibcon#read 4, iclass 39, count 0 2006.224.07:48:20.57#ibcon#about to read 5, iclass 39, count 0 2006.224.07:48:20.57#ibcon#read 5, iclass 39, count 0 2006.224.07:48:20.57#ibcon#about to read 6, iclass 39, count 0 2006.224.07:48:20.57#ibcon#read 6, iclass 39, count 0 2006.224.07:48:20.57#ibcon#end of sib2, iclass 39, count 0 2006.224.07:48:20.57#ibcon#*mode == 0, iclass 39, count 0 2006.224.07:48:20.57#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.224.07:48:20.57#ibcon#[28=FRQ=01,632.99\r\n] 2006.224.07:48:20.57#ibcon#*before write, iclass 39, count 0 2006.224.07:48:20.57#ibcon#enter sib2, iclass 39, count 0 2006.224.07:48:20.57#ibcon#flushed, iclass 39, count 0 2006.224.07:48:20.57#ibcon#about to write, iclass 39, count 0 2006.224.07:48:20.57#ibcon#wrote, iclass 39, count 0 2006.224.07:48:20.57#ibcon#about to read 3, iclass 39, count 0 2006.224.07:48:20.61#ibcon#read 3, iclass 39, count 0 2006.224.07:48:20.61#ibcon#about to read 4, iclass 39, count 0 2006.224.07:48:20.61#ibcon#read 4, iclass 39, count 0 2006.224.07:48:20.61#ibcon#about to read 5, iclass 39, count 0 2006.224.07:48:20.61#ibcon#read 5, iclass 39, count 0 2006.224.07:48:20.61#ibcon#about to read 6, iclass 39, count 0 2006.224.07:48:20.61#ibcon#read 6, iclass 39, count 0 2006.224.07:48:20.61#ibcon#end of sib2, iclass 39, count 0 2006.224.07:48:20.61#ibcon#*after write, iclass 39, count 0 2006.224.07:48:20.61#ibcon#*before return 0, iclass 39, count 0 2006.224.07:48:20.61#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.224.07:48:20.61#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.224.07:48:20.61#ibcon#about to clear, iclass 39 cls_cnt 0 2006.224.07:48:20.61#ibcon#cleared, iclass 39 cls_cnt 0 2006.224.07:48:20.61$vc4f8/vb=1,4 2006.224.07:48:20.61#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.224.07:48:20.61#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.224.07:48:20.61#ibcon#ireg 11 cls_cnt 2 2006.224.07:48:20.61#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.224.07:48:20.61#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.224.07:48:20.61#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.224.07:48:20.61#ibcon#enter wrdev, iclass 3, count 2 2006.224.07:48:20.61#ibcon#first serial, iclass 3, count 2 2006.224.07:48:20.61#ibcon#enter sib2, iclass 3, count 2 2006.224.07:48:20.61#ibcon#flushed, iclass 3, count 2 2006.224.07:48:20.61#ibcon#about to write, iclass 3, count 2 2006.224.07:48:20.61#ibcon#wrote, iclass 3, count 2 2006.224.07:48:20.61#ibcon#about to read 3, iclass 3, count 2 2006.224.07:48:20.63#ibcon#read 3, iclass 3, count 2 2006.224.07:48:20.63#ibcon#about to read 4, iclass 3, count 2 2006.224.07:48:20.63#ibcon#read 4, iclass 3, count 2 2006.224.07:48:20.63#ibcon#about to read 5, iclass 3, count 2 2006.224.07:48:20.63#ibcon#read 5, iclass 3, count 2 2006.224.07:48:20.63#ibcon#about to read 6, iclass 3, count 2 2006.224.07:48:20.63#ibcon#read 6, iclass 3, count 2 2006.224.07:48:20.63#ibcon#end of sib2, iclass 3, count 2 2006.224.07:48:20.63#ibcon#*mode == 0, iclass 3, count 2 2006.224.07:48:20.63#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.224.07:48:20.63#ibcon#[27=AT01-04\r\n] 2006.224.07:48:20.63#ibcon#*before write, iclass 3, count 2 2006.224.07:48:20.63#ibcon#enter sib2, iclass 3, count 2 2006.224.07:48:20.63#ibcon#flushed, iclass 3, count 2 2006.224.07:48:20.63#ibcon#about to write, iclass 3, count 2 2006.224.07:48:20.63#ibcon#wrote, iclass 3, count 2 2006.224.07:48:20.63#ibcon#about to read 3, iclass 3, count 2 2006.224.07:48:20.66#ibcon#read 3, iclass 3, count 2 2006.224.07:48:20.66#ibcon#about to read 4, iclass 3, count 2 2006.224.07:48:20.66#ibcon#read 4, iclass 3, count 2 2006.224.07:48:20.66#ibcon#about to read 5, iclass 3, count 2 2006.224.07:48:20.66#ibcon#read 5, iclass 3, count 2 2006.224.07:48:20.66#ibcon#about to read 6, iclass 3, count 2 2006.224.07:48:20.66#ibcon#read 6, iclass 3, count 2 2006.224.07:48:20.66#ibcon#end of sib2, iclass 3, count 2 2006.224.07:48:20.66#ibcon#*after write, iclass 3, count 2 2006.224.07:48:20.66#ibcon#*before return 0, iclass 3, count 2 2006.224.07:48:20.66#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.224.07:48:20.66#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.224.07:48:20.66#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.224.07:48:20.66#ibcon#ireg 7 cls_cnt 0 2006.224.07:48:20.66#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.224.07:48:20.78#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.224.07:48:20.78#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.224.07:48:20.78#ibcon#enter wrdev, iclass 3, count 0 2006.224.07:48:20.78#ibcon#first serial, iclass 3, count 0 2006.224.07:48:20.78#ibcon#enter sib2, iclass 3, count 0 2006.224.07:48:20.78#ibcon#flushed, iclass 3, count 0 2006.224.07:48:20.78#ibcon#about to write, iclass 3, count 0 2006.224.07:48:20.78#ibcon#wrote, iclass 3, count 0 2006.224.07:48:20.78#ibcon#about to read 3, iclass 3, count 0 2006.224.07:48:20.80#ibcon#read 3, iclass 3, count 0 2006.224.07:48:20.80#ibcon#about to read 4, iclass 3, count 0 2006.224.07:48:20.80#ibcon#read 4, iclass 3, count 0 2006.224.07:48:20.80#ibcon#about to read 5, iclass 3, count 0 2006.224.07:48:20.80#ibcon#read 5, iclass 3, count 0 2006.224.07:48:20.80#ibcon#about to read 6, iclass 3, count 0 2006.224.07:48:20.80#ibcon#read 6, iclass 3, count 0 2006.224.07:48:20.80#ibcon#end of sib2, iclass 3, count 0 2006.224.07:48:20.80#ibcon#*mode == 0, iclass 3, count 0 2006.224.07:48:20.80#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.224.07:48:20.80#ibcon#[27=USB\r\n] 2006.224.07:48:20.80#ibcon#*before write, iclass 3, count 0 2006.224.07:48:20.80#ibcon#enter sib2, iclass 3, count 0 2006.224.07:48:20.80#ibcon#flushed, iclass 3, count 0 2006.224.07:48:20.80#ibcon#about to write, iclass 3, count 0 2006.224.07:48:20.80#ibcon#wrote, iclass 3, count 0 2006.224.07:48:20.80#ibcon#about to read 3, iclass 3, count 0 2006.224.07:48:20.83#ibcon#read 3, iclass 3, count 0 2006.224.07:48:20.83#ibcon#about to read 4, iclass 3, count 0 2006.224.07:48:20.83#ibcon#read 4, iclass 3, count 0 2006.224.07:48:20.83#ibcon#about to read 5, iclass 3, count 0 2006.224.07:48:20.83#ibcon#read 5, iclass 3, count 0 2006.224.07:48:20.83#ibcon#about to read 6, iclass 3, count 0 2006.224.07:48:20.83#ibcon#read 6, iclass 3, count 0 2006.224.07:48:20.83#ibcon#end of sib2, iclass 3, count 0 2006.224.07:48:20.83#ibcon#*after write, iclass 3, count 0 2006.224.07:48:20.83#ibcon#*before return 0, iclass 3, count 0 2006.224.07:48:20.83#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.224.07:48:20.83#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.224.07:48:20.83#ibcon#about to clear, iclass 3 cls_cnt 0 2006.224.07:48:20.83#ibcon#cleared, iclass 3 cls_cnt 0 2006.224.07:48:20.83$vc4f8/vblo=2,640.99 2006.224.07:48:20.83#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.224.07:48:20.83#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.224.07:48:20.83#ibcon#ireg 17 cls_cnt 0 2006.224.07:48:20.83#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.224.07:48:20.83#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.224.07:48:20.83#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.224.07:48:20.83#ibcon#enter wrdev, iclass 5, count 0 2006.224.07:48:20.83#ibcon#first serial, iclass 5, count 0 2006.224.07:48:20.83#ibcon#enter sib2, iclass 5, count 0 2006.224.07:48:20.83#ibcon#flushed, iclass 5, count 0 2006.224.07:48:20.83#ibcon#about to write, iclass 5, count 0 2006.224.07:48:20.83#ibcon#wrote, iclass 5, count 0 2006.224.07:48:20.83#ibcon#about to read 3, iclass 5, count 0 2006.224.07:48:20.85#ibcon#read 3, iclass 5, count 0 2006.224.07:48:20.85#ibcon#about to read 4, iclass 5, count 0 2006.224.07:48:20.85#ibcon#read 4, iclass 5, count 0 2006.224.07:48:20.85#ibcon#about to read 5, iclass 5, count 0 2006.224.07:48:20.85#ibcon#read 5, iclass 5, count 0 2006.224.07:48:20.85#ibcon#about to read 6, iclass 5, count 0 2006.224.07:48:20.85#ibcon#read 6, iclass 5, count 0 2006.224.07:48:20.85#ibcon#end of sib2, iclass 5, count 0 2006.224.07:48:20.85#ibcon#*mode == 0, iclass 5, count 0 2006.224.07:48:20.85#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.224.07:48:20.85#ibcon#[28=FRQ=02,640.99\r\n] 2006.224.07:48:20.85#ibcon#*before write, iclass 5, count 0 2006.224.07:48:20.85#ibcon#enter sib2, iclass 5, count 0 2006.224.07:48:20.85#ibcon#flushed, iclass 5, count 0 2006.224.07:48:20.85#ibcon#about to write, iclass 5, count 0 2006.224.07:48:20.85#ibcon#wrote, iclass 5, count 0 2006.224.07:48:20.85#ibcon#about to read 3, iclass 5, count 0 2006.224.07:48:20.89#ibcon#read 3, iclass 5, count 0 2006.224.07:48:20.89#ibcon#about to read 4, iclass 5, count 0 2006.224.07:48:20.89#ibcon#read 4, iclass 5, count 0 2006.224.07:48:20.89#ibcon#about to read 5, iclass 5, count 0 2006.224.07:48:20.89#ibcon#read 5, iclass 5, count 0 2006.224.07:48:20.89#ibcon#about to read 6, iclass 5, count 0 2006.224.07:48:20.89#ibcon#read 6, iclass 5, count 0 2006.224.07:48:20.89#ibcon#end of sib2, iclass 5, count 0 2006.224.07:48:20.89#ibcon#*after write, iclass 5, count 0 2006.224.07:48:20.89#ibcon#*before return 0, iclass 5, count 0 2006.224.07:48:20.89#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.224.07:48:20.89#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.224.07:48:20.89#ibcon#about to clear, iclass 5 cls_cnt 0 2006.224.07:48:20.89#ibcon#cleared, iclass 5 cls_cnt 0 2006.224.07:48:20.89$vc4f8/vb=2,4 2006.224.07:48:20.89#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.224.07:48:20.89#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.224.07:48:20.89#ibcon#ireg 11 cls_cnt 2 2006.224.07:48:20.89#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.224.07:48:20.95#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.224.07:48:20.95#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.224.07:48:20.95#ibcon#enter wrdev, iclass 7, count 2 2006.224.07:48:20.95#ibcon#first serial, iclass 7, count 2 2006.224.07:48:20.95#ibcon#enter sib2, iclass 7, count 2 2006.224.07:48:20.95#ibcon#flushed, iclass 7, count 2 2006.224.07:48:20.95#ibcon#about to write, iclass 7, count 2 2006.224.07:48:20.95#ibcon#wrote, iclass 7, count 2 2006.224.07:48:20.95#ibcon#about to read 3, iclass 7, count 2 2006.224.07:48:20.97#ibcon#read 3, iclass 7, count 2 2006.224.07:48:20.97#ibcon#about to read 4, iclass 7, count 2 2006.224.07:48:20.97#ibcon#read 4, iclass 7, count 2 2006.224.07:48:20.97#ibcon#about to read 5, iclass 7, count 2 2006.224.07:48:20.97#ibcon#read 5, iclass 7, count 2 2006.224.07:48:20.97#ibcon#about to read 6, iclass 7, count 2 2006.224.07:48:20.97#ibcon#read 6, iclass 7, count 2 2006.224.07:48:20.97#ibcon#end of sib2, iclass 7, count 2 2006.224.07:48:20.97#ibcon#*mode == 0, iclass 7, count 2 2006.224.07:48:20.97#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.224.07:48:20.97#ibcon#[27=AT02-04\r\n] 2006.224.07:48:20.97#ibcon#*before write, iclass 7, count 2 2006.224.07:48:20.97#ibcon#enter sib2, iclass 7, count 2 2006.224.07:48:20.97#ibcon#flushed, iclass 7, count 2 2006.224.07:48:20.97#ibcon#about to write, iclass 7, count 2 2006.224.07:48:20.97#ibcon#wrote, iclass 7, count 2 2006.224.07:48:20.97#ibcon#about to read 3, iclass 7, count 2 2006.224.07:48:21.00#ibcon#read 3, iclass 7, count 2 2006.224.07:48:21.00#ibcon#about to read 4, iclass 7, count 2 2006.224.07:48:21.00#ibcon#read 4, iclass 7, count 2 2006.224.07:48:21.00#ibcon#about to read 5, iclass 7, count 2 2006.224.07:48:21.00#ibcon#read 5, iclass 7, count 2 2006.224.07:48:21.00#ibcon#about to read 6, iclass 7, count 2 2006.224.07:48:21.00#ibcon#read 6, iclass 7, count 2 2006.224.07:48:21.00#ibcon#end of sib2, iclass 7, count 2 2006.224.07:48:21.00#ibcon#*after write, iclass 7, count 2 2006.224.07:48:21.00#ibcon#*before return 0, iclass 7, count 2 2006.224.07:48:21.00#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.224.07:48:21.00#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.224.07:48:21.00#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.224.07:48:21.00#ibcon#ireg 7 cls_cnt 0 2006.224.07:48:21.00#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.224.07:48:21.12#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.224.07:48:21.12#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.224.07:48:21.12#ibcon#enter wrdev, iclass 7, count 0 2006.224.07:48:21.12#ibcon#first serial, iclass 7, count 0 2006.224.07:48:21.12#ibcon#enter sib2, iclass 7, count 0 2006.224.07:48:21.12#ibcon#flushed, iclass 7, count 0 2006.224.07:48:21.12#ibcon#about to write, iclass 7, count 0 2006.224.07:48:21.12#ibcon#wrote, iclass 7, count 0 2006.224.07:48:21.12#ibcon#about to read 3, iclass 7, count 0 2006.224.07:48:21.14#ibcon#read 3, iclass 7, count 0 2006.224.07:48:21.14#ibcon#about to read 4, iclass 7, count 0 2006.224.07:48:21.14#ibcon#read 4, iclass 7, count 0 2006.224.07:48:21.14#ibcon#about to read 5, iclass 7, count 0 2006.224.07:48:21.14#ibcon#read 5, iclass 7, count 0 2006.224.07:48:21.14#ibcon#about to read 6, iclass 7, count 0 2006.224.07:48:21.14#ibcon#read 6, iclass 7, count 0 2006.224.07:48:21.14#ibcon#end of sib2, iclass 7, count 0 2006.224.07:48:21.14#ibcon#*mode == 0, iclass 7, count 0 2006.224.07:48:21.14#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.224.07:48:21.14#ibcon#[27=USB\r\n] 2006.224.07:48:21.14#ibcon#*before write, iclass 7, count 0 2006.224.07:48:21.14#ibcon#enter sib2, iclass 7, count 0 2006.224.07:48:21.14#ibcon#flushed, iclass 7, count 0 2006.224.07:48:21.14#ibcon#about to write, iclass 7, count 0 2006.224.07:48:21.14#ibcon#wrote, iclass 7, count 0 2006.224.07:48:21.14#ibcon#about to read 3, iclass 7, count 0 2006.224.07:48:21.17#ibcon#read 3, iclass 7, count 0 2006.224.07:48:21.17#ibcon#about to read 4, iclass 7, count 0 2006.224.07:48:21.17#ibcon#read 4, iclass 7, count 0 2006.224.07:48:21.17#ibcon#about to read 5, iclass 7, count 0 2006.224.07:48:21.17#ibcon#read 5, iclass 7, count 0 2006.224.07:48:21.17#ibcon#about to read 6, iclass 7, count 0 2006.224.07:48:21.17#ibcon#read 6, iclass 7, count 0 2006.224.07:48:21.17#ibcon#end of sib2, iclass 7, count 0 2006.224.07:48:21.17#ibcon#*after write, iclass 7, count 0 2006.224.07:48:21.17#ibcon#*before return 0, iclass 7, count 0 2006.224.07:48:21.17#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.224.07:48:21.17#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.224.07:48:21.17#ibcon#about to clear, iclass 7 cls_cnt 0 2006.224.07:48:21.17#ibcon#cleared, iclass 7 cls_cnt 0 2006.224.07:48:21.17$vc4f8/vblo=3,656.99 2006.224.07:48:21.17#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.224.07:48:21.17#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.224.07:48:21.17#ibcon#ireg 17 cls_cnt 0 2006.224.07:48:21.17#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.224.07:48:21.17#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.224.07:48:21.17#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.224.07:48:21.17#ibcon#enter wrdev, iclass 11, count 0 2006.224.07:48:21.17#ibcon#first serial, iclass 11, count 0 2006.224.07:48:21.17#ibcon#enter sib2, iclass 11, count 0 2006.224.07:48:21.17#ibcon#flushed, iclass 11, count 0 2006.224.07:48:21.17#ibcon#about to write, iclass 11, count 0 2006.224.07:48:21.17#ibcon#wrote, iclass 11, count 0 2006.224.07:48:21.17#ibcon#about to read 3, iclass 11, count 0 2006.224.07:48:21.19#ibcon#read 3, iclass 11, count 0 2006.224.07:48:21.19#ibcon#about to read 4, iclass 11, count 0 2006.224.07:48:21.19#ibcon#read 4, iclass 11, count 0 2006.224.07:48:21.19#ibcon#about to read 5, iclass 11, count 0 2006.224.07:48:21.19#ibcon#read 5, iclass 11, count 0 2006.224.07:48:21.19#ibcon#about to read 6, iclass 11, count 0 2006.224.07:48:21.19#ibcon#read 6, iclass 11, count 0 2006.224.07:48:21.19#ibcon#end of sib2, iclass 11, count 0 2006.224.07:48:21.19#ibcon#*mode == 0, iclass 11, count 0 2006.224.07:48:21.19#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.224.07:48:21.19#ibcon#[28=FRQ=03,656.99\r\n] 2006.224.07:48:21.19#ibcon#*before write, iclass 11, count 0 2006.224.07:48:21.19#ibcon#enter sib2, iclass 11, count 0 2006.224.07:48:21.19#ibcon#flushed, iclass 11, count 0 2006.224.07:48:21.19#ibcon#about to write, iclass 11, count 0 2006.224.07:48:21.19#ibcon#wrote, iclass 11, count 0 2006.224.07:48:21.19#ibcon#about to read 3, iclass 11, count 0 2006.224.07:48:21.23#ibcon#read 3, iclass 11, count 0 2006.224.07:48:21.23#ibcon#about to read 4, iclass 11, count 0 2006.224.07:48:21.23#ibcon#read 4, iclass 11, count 0 2006.224.07:48:21.23#ibcon#about to read 5, iclass 11, count 0 2006.224.07:48:21.23#ibcon#read 5, iclass 11, count 0 2006.224.07:48:21.23#ibcon#about to read 6, iclass 11, count 0 2006.224.07:48:21.23#ibcon#read 6, iclass 11, count 0 2006.224.07:48:21.23#ibcon#end of sib2, iclass 11, count 0 2006.224.07:48:21.23#ibcon#*after write, iclass 11, count 0 2006.224.07:48:21.23#ibcon#*before return 0, iclass 11, count 0 2006.224.07:48:21.23#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.224.07:48:21.23#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.224.07:48:21.23#ibcon#about to clear, iclass 11 cls_cnt 0 2006.224.07:48:21.23#ibcon#cleared, iclass 11 cls_cnt 0 2006.224.07:48:21.23$vc4f8/vb=3,4 2006.224.07:48:21.23#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.224.07:48:21.23#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.224.07:48:21.23#ibcon#ireg 11 cls_cnt 2 2006.224.07:48:21.23#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.224.07:48:21.29#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.224.07:48:21.29#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.224.07:48:21.29#ibcon#enter wrdev, iclass 13, count 2 2006.224.07:48:21.29#ibcon#first serial, iclass 13, count 2 2006.224.07:48:21.29#ibcon#enter sib2, iclass 13, count 2 2006.224.07:48:21.29#ibcon#flushed, iclass 13, count 2 2006.224.07:48:21.29#ibcon#about to write, iclass 13, count 2 2006.224.07:48:21.29#ibcon#wrote, iclass 13, count 2 2006.224.07:48:21.29#ibcon#about to read 3, iclass 13, count 2 2006.224.07:48:21.31#ibcon#read 3, iclass 13, count 2 2006.224.07:48:21.31#ibcon#about to read 4, iclass 13, count 2 2006.224.07:48:21.31#ibcon#read 4, iclass 13, count 2 2006.224.07:48:21.31#ibcon#about to read 5, iclass 13, count 2 2006.224.07:48:21.31#ibcon#read 5, iclass 13, count 2 2006.224.07:48:21.31#ibcon#about to read 6, iclass 13, count 2 2006.224.07:48:21.31#ibcon#read 6, iclass 13, count 2 2006.224.07:48:21.31#ibcon#end of sib2, iclass 13, count 2 2006.224.07:48:21.31#ibcon#*mode == 0, iclass 13, count 2 2006.224.07:48:21.31#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.224.07:48:21.31#ibcon#[27=AT03-04\r\n] 2006.224.07:48:21.31#ibcon#*before write, iclass 13, count 2 2006.224.07:48:21.31#ibcon#enter sib2, iclass 13, count 2 2006.224.07:48:21.31#ibcon#flushed, iclass 13, count 2 2006.224.07:48:21.31#ibcon#about to write, iclass 13, count 2 2006.224.07:48:21.31#ibcon#wrote, iclass 13, count 2 2006.224.07:48:21.31#ibcon#about to read 3, iclass 13, count 2 2006.224.07:48:21.34#ibcon#read 3, iclass 13, count 2 2006.224.07:48:21.34#ibcon#about to read 4, iclass 13, count 2 2006.224.07:48:21.34#ibcon#read 4, iclass 13, count 2 2006.224.07:48:21.34#ibcon#about to read 5, iclass 13, count 2 2006.224.07:48:21.34#ibcon#read 5, iclass 13, count 2 2006.224.07:48:21.34#ibcon#about to read 6, iclass 13, count 2 2006.224.07:48:21.34#ibcon#read 6, iclass 13, count 2 2006.224.07:48:21.34#ibcon#end of sib2, iclass 13, count 2 2006.224.07:48:21.34#ibcon#*after write, iclass 13, count 2 2006.224.07:48:21.34#ibcon#*before return 0, iclass 13, count 2 2006.224.07:48:21.34#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.224.07:48:21.34#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.224.07:48:21.34#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.224.07:48:21.34#ibcon#ireg 7 cls_cnt 0 2006.224.07:48:21.34#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.224.07:48:21.46#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.224.07:48:21.46#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.224.07:48:21.46#ibcon#enter wrdev, iclass 13, count 0 2006.224.07:48:21.46#ibcon#first serial, iclass 13, count 0 2006.224.07:48:21.46#ibcon#enter sib2, iclass 13, count 0 2006.224.07:48:21.46#ibcon#flushed, iclass 13, count 0 2006.224.07:48:21.46#ibcon#about to write, iclass 13, count 0 2006.224.07:48:21.46#ibcon#wrote, iclass 13, count 0 2006.224.07:48:21.46#ibcon#about to read 3, iclass 13, count 0 2006.224.07:48:21.48#ibcon#read 3, iclass 13, count 0 2006.224.07:48:21.48#ibcon#about to read 4, iclass 13, count 0 2006.224.07:48:21.48#ibcon#read 4, iclass 13, count 0 2006.224.07:48:21.48#ibcon#about to read 5, iclass 13, count 0 2006.224.07:48:21.48#ibcon#read 5, iclass 13, count 0 2006.224.07:48:21.48#ibcon#about to read 6, iclass 13, count 0 2006.224.07:48:21.48#ibcon#read 6, iclass 13, count 0 2006.224.07:48:21.48#ibcon#end of sib2, iclass 13, count 0 2006.224.07:48:21.48#ibcon#*mode == 0, iclass 13, count 0 2006.224.07:48:21.48#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.224.07:48:21.48#ibcon#[27=USB\r\n] 2006.224.07:48:21.48#ibcon#*before write, iclass 13, count 0 2006.224.07:48:21.48#ibcon#enter sib2, iclass 13, count 0 2006.224.07:48:21.48#ibcon#flushed, iclass 13, count 0 2006.224.07:48:21.48#ibcon#about to write, iclass 13, count 0 2006.224.07:48:21.48#ibcon#wrote, iclass 13, count 0 2006.224.07:48:21.48#ibcon#about to read 3, iclass 13, count 0 2006.224.07:48:21.51#ibcon#read 3, iclass 13, count 0 2006.224.07:48:21.51#ibcon#about to read 4, iclass 13, count 0 2006.224.07:48:21.51#ibcon#read 4, iclass 13, count 0 2006.224.07:48:21.51#ibcon#about to read 5, iclass 13, count 0 2006.224.07:48:21.51#ibcon#read 5, iclass 13, count 0 2006.224.07:48:21.51#ibcon#about to read 6, iclass 13, count 0 2006.224.07:48:21.51#ibcon#read 6, iclass 13, count 0 2006.224.07:48:21.51#ibcon#end of sib2, iclass 13, count 0 2006.224.07:48:21.51#ibcon#*after write, iclass 13, count 0 2006.224.07:48:21.51#ibcon#*before return 0, iclass 13, count 0 2006.224.07:48:21.51#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.224.07:48:21.51#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.224.07:48:21.51#ibcon#about to clear, iclass 13 cls_cnt 0 2006.224.07:48:21.51#ibcon#cleared, iclass 13 cls_cnt 0 2006.224.07:48:21.51$vc4f8/vblo=4,712.99 2006.224.07:48:21.51#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.224.07:48:21.51#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.224.07:48:21.51#ibcon#ireg 17 cls_cnt 0 2006.224.07:48:21.51#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.224.07:48:21.51#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.224.07:48:21.51#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.224.07:48:21.51#ibcon#enter wrdev, iclass 15, count 0 2006.224.07:48:21.51#ibcon#first serial, iclass 15, count 0 2006.224.07:48:21.51#ibcon#enter sib2, iclass 15, count 0 2006.224.07:48:21.51#ibcon#flushed, iclass 15, count 0 2006.224.07:48:21.51#ibcon#about to write, iclass 15, count 0 2006.224.07:48:21.51#ibcon#wrote, iclass 15, count 0 2006.224.07:48:21.51#ibcon#about to read 3, iclass 15, count 0 2006.224.07:48:21.53#ibcon#read 3, iclass 15, count 0 2006.224.07:48:21.53#ibcon#about to read 4, iclass 15, count 0 2006.224.07:48:21.53#ibcon#read 4, iclass 15, count 0 2006.224.07:48:21.53#ibcon#about to read 5, iclass 15, count 0 2006.224.07:48:21.53#ibcon#read 5, iclass 15, count 0 2006.224.07:48:21.53#ibcon#about to read 6, iclass 15, count 0 2006.224.07:48:21.53#ibcon#read 6, iclass 15, count 0 2006.224.07:48:21.53#ibcon#end of sib2, iclass 15, count 0 2006.224.07:48:21.53#ibcon#*mode == 0, iclass 15, count 0 2006.224.07:48:21.53#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.224.07:48:21.53#ibcon#[28=FRQ=04,712.99\r\n] 2006.224.07:48:21.53#ibcon#*before write, iclass 15, count 0 2006.224.07:48:21.53#ibcon#enter sib2, iclass 15, count 0 2006.224.07:48:21.53#ibcon#flushed, iclass 15, count 0 2006.224.07:48:21.53#ibcon#about to write, iclass 15, count 0 2006.224.07:48:21.53#ibcon#wrote, iclass 15, count 0 2006.224.07:48:21.53#ibcon#about to read 3, iclass 15, count 0 2006.224.07:48:21.57#ibcon#read 3, iclass 15, count 0 2006.224.07:48:21.57#ibcon#about to read 4, iclass 15, count 0 2006.224.07:48:21.57#ibcon#read 4, iclass 15, count 0 2006.224.07:48:21.57#ibcon#about to read 5, iclass 15, count 0 2006.224.07:48:21.57#ibcon#read 5, iclass 15, count 0 2006.224.07:48:21.57#ibcon#about to read 6, iclass 15, count 0 2006.224.07:48:21.57#ibcon#read 6, iclass 15, count 0 2006.224.07:48:21.57#ibcon#end of sib2, iclass 15, count 0 2006.224.07:48:21.57#ibcon#*after write, iclass 15, count 0 2006.224.07:48:21.57#ibcon#*before return 0, iclass 15, count 0 2006.224.07:48:21.57#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.224.07:48:21.57#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.224.07:48:21.57#ibcon#about to clear, iclass 15 cls_cnt 0 2006.224.07:48:21.57#ibcon#cleared, iclass 15 cls_cnt 0 2006.224.07:48:21.57$vc4f8/vb=4,4 2006.224.07:48:21.57#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.224.07:48:21.57#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.224.07:48:21.57#ibcon#ireg 11 cls_cnt 2 2006.224.07:48:21.57#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.224.07:48:21.63#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.224.07:48:21.63#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.224.07:48:21.63#ibcon#enter wrdev, iclass 17, count 2 2006.224.07:48:21.63#ibcon#first serial, iclass 17, count 2 2006.224.07:48:21.63#ibcon#enter sib2, iclass 17, count 2 2006.224.07:48:21.63#ibcon#flushed, iclass 17, count 2 2006.224.07:48:21.63#ibcon#about to write, iclass 17, count 2 2006.224.07:48:21.63#ibcon#wrote, iclass 17, count 2 2006.224.07:48:21.63#ibcon#about to read 3, iclass 17, count 2 2006.224.07:48:21.65#ibcon#read 3, iclass 17, count 2 2006.224.07:48:21.65#ibcon#about to read 4, iclass 17, count 2 2006.224.07:48:21.65#ibcon#read 4, iclass 17, count 2 2006.224.07:48:21.65#ibcon#about to read 5, iclass 17, count 2 2006.224.07:48:21.65#ibcon#read 5, iclass 17, count 2 2006.224.07:48:21.65#ibcon#about to read 6, iclass 17, count 2 2006.224.07:48:21.65#ibcon#read 6, iclass 17, count 2 2006.224.07:48:21.65#ibcon#end of sib2, iclass 17, count 2 2006.224.07:48:21.65#ibcon#*mode == 0, iclass 17, count 2 2006.224.07:48:21.65#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.224.07:48:21.65#ibcon#[27=AT04-04\r\n] 2006.224.07:48:21.65#ibcon#*before write, iclass 17, count 2 2006.224.07:48:21.65#ibcon#enter sib2, iclass 17, count 2 2006.224.07:48:21.65#ibcon#flushed, iclass 17, count 2 2006.224.07:48:21.65#ibcon#about to write, iclass 17, count 2 2006.224.07:48:21.65#ibcon#wrote, iclass 17, count 2 2006.224.07:48:21.65#ibcon#about to read 3, iclass 17, count 2 2006.224.07:48:21.68#ibcon#read 3, iclass 17, count 2 2006.224.07:48:21.68#ibcon#about to read 4, iclass 17, count 2 2006.224.07:48:21.68#ibcon#read 4, iclass 17, count 2 2006.224.07:48:21.68#ibcon#about to read 5, iclass 17, count 2 2006.224.07:48:21.68#ibcon#read 5, iclass 17, count 2 2006.224.07:48:21.68#ibcon#about to read 6, iclass 17, count 2 2006.224.07:48:21.68#ibcon#read 6, iclass 17, count 2 2006.224.07:48:21.68#ibcon#end of sib2, iclass 17, count 2 2006.224.07:48:21.68#ibcon#*after write, iclass 17, count 2 2006.224.07:48:21.68#ibcon#*before return 0, iclass 17, count 2 2006.224.07:48:21.68#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.224.07:48:21.68#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.224.07:48:21.68#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.224.07:48:21.68#ibcon#ireg 7 cls_cnt 0 2006.224.07:48:21.68#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.224.07:48:21.80#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.224.07:48:21.80#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.224.07:48:21.80#ibcon#enter wrdev, iclass 17, count 0 2006.224.07:48:21.80#ibcon#first serial, iclass 17, count 0 2006.224.07:48:21.80#ibcon#enter sib2, iclass 17, count 0 2006.224.07:48:21.80#ibcon#flushed, iclass 17, count 0 2006.224.07:48:21.80#ibcon#about to write, iclass 17, count 0 2006.224.07:48:21.80#ibcon#wrote, iclass 17, count 0 2006.224.07:48:21.80#ibcon#about to read 3, iclass 17, count 0 2006.224.07:48:21.82#ibcon#read 3, iclass 17, count 0 2006.224.07:48:21.82#ibcon#about to read 4, iclass 17, count 0 2006.224.07:48:21.82#ibcon#read 4, iclass 17, count 0 2006.224.07:48:21.82#ibcon#about to read 5, iclass 17, count 0 2006.224.07:48:21.82#ibcon#read 5, iclass 17, count 0 2006.224.07:48:21.82#ibcon#about to read 6, iclass 17, count 0 2006.224.07:48:21.82#ibcon#read 6, iclass 17, count 0 2006.224.07:48:21.82#ibcon#end of sib2, iclass 17, count 0 2006.224.07:48:21.82#ibcon#*mode == 0, iclass 17, count 0 2006.224.07:48:21.82#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.224.07:48:21.82#ibcon#[27=USB\r\n] 2006.224.07:48:21.82#ibcon#*before write, iclass 17, count 0 2006.224.07:48:21.82#ibcon#enter sib2, iclass 17, count 0 2006.224.07:48:21.82#ibcon#flushed, iclass 17, count 0 2006.224.07:48:21.82#ibcon#about to write, iclass 17, count 0 2006.224.07:48:21.82#ibcon#wrote, iclass 17, count 0 2006.224.07:48:21.82#ibcon#about to read 3, iclass 17, count 0 2006.224.07:48:21.85#ibcon#read 3, iclass 17, count 0 2006.224.07:48:21.85#ibcon#about to read 4, iclass 17, count 0 2006.224.07:48:21.85#ibcon#read 4, iclass 17, count 0 2006.224.07:48:21.85#ibcon#about to read 5, iclass 17, count 0 2006.224.07:48:21.85#ibcon#read 5, iclass 17, count 0 2006.224.07:48:21.85#ibcon#about to read 6, iclass 17, count 0 2006.224.07:48:21.85#ibcon#read 6, iclass 17, count 0 2006.224.07:48:21.85#ibcon#end of sib2, iclass 17, count 0 2006.224.07:48:21.85#ibcon#*after write, iclass 17, count 0 2006.224.07:48:21.85#ibcon#*before return 0, iclass 17, count 0 2006.224.07:48:21.85#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.224.07:48:21.85#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.224.07:48:21.85#ibcon#about to clear, iclass 17 cls_cnt 0 2006.224.07:48:21.85#ibcon#cleared, iclass 17 cls_cnt 0 2006.224.07:48:21.85$vc4f8/vblo=5,744.99 2006.224.07:48:21.85#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.224.07:48:21.85#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.224.07:48:21.85#ibcon#ireg 17 cls_cnt 0 2006.224.07:48:21.85#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.224.07:48:21.85#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.224.07:48:21.85#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.224.07:48:21.85#ibcon#enter wrdev, iclass 19, count 0 2006.224.07:48:21.85#ibcon#first serial, iclass 19, count 0 2006.224.07:48:21.85#ibcon#enter sib2, iclass 19, count 0 2006.224.07:48:21.85#ibcon#flushed, iclass 19, count 0 2006.224.07:48:21.85#ibcon#about to write, iclass 19, count 0 2006.224.07:48:21.85#ibcon#wrote, iclass 19, count 0 2006.224.07:48:21.85#ibcon#about to read 3, iclass 19, count 0 2006.224.07:48:21.87#ibcon#read 3, iclass 19, count 0 2006.224.07:48:21.87#ibcon#about to read 4, iclass 19, count 0 2006.224.07:48:21.87#ibcon#read 4, iclass 19, count 0 2006.224.07:48:21.87#ibcon#about to read 5, iclass 19, count 0 2006.224.07:48:21.87#ibcon#read 5, iclass 19, count 0 2006.224.07:48:21.87#ibcon#about to read 6, iclass 19, count 0 2006.224.07:48:21.87#ibcon#read 6, iclass 19, count 0 2006.224.07:48:21.87#ibcon#end of sib2, iclass 19, count 0 2006.224.07:48:21.87#ibcon#*mode == 0, iclass 19, count 0 2006.224.07:48:21.87#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.224.07:48:21.87#ibcon#[28=FRQ=05,744.99\r\n] 2006.224.07:48:21.87#ibcon#*before write, iclass 19, count 0 2006.224.07:48:21.87#ibcon#enter sib2, iclass 19, count 0 2006.224.07:48:21.87#ibcon#flushed, iclass 19, count 0 2006.224.07:48:21.87#ibcon#about to write, iclass 19, count 0 2006.224.07:48:21.87#ibcon#wrote, iclass 19, count 0 2006.224.07:48:21.87#ibcon#about to read 3, iclass 19, count 0 2006.224.07:48:21.91#ibcon#read 3, iclass 19, count 0 2006.224.07:48:21.91#ibcon#about to read 4, iclass 19, count 0 2006.224.07:48:21.91#ibcon#read 4, iclass 19, count 0 2006.224.07:48:21.91#ibcon#about to read 5, iclass 19, count 0 2006.224.07:48:21.91#ibcon#read 5, iclass 19, count 0 2006.224.07:48:21.91#ibcon#about to read 6, iclass 19, count 0 2006.224.07:48:21.91#ibcon#read 6, iclass 19, count 0 2006.224.07:48:21.91#ibcon#end of sib2, iclass 19, count 0 2006.224.07:48:21.91#ibcon#*after write, iclass 19, count 0 2006.224.07:48:21.91#ibcon#*before return 0, iclass 19, count 0 2006.224.07:48:21.91#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.224.07:48:21.91#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.224.07:48:21.91#ibcon#about to clear, iclass 19 cls_cnt 0 2006.224.07:48:21.91#ibcon#cleared, iclass 19 cls_cnt 0 2006.224.07:48:21.91$vc4f8/vb=5,4 2006.224.07:48:21.91#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.224.07:48:21.91#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.224.07:48:21.91#ibcon#ireg 11 cls_cnt 2 2006.224.07:48:21.91#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.224.07:48:21.97#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.224.07:48:21.97#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.224.07:48:21.97#ibcon#enter wrdev, iclass 21, count 2 2006.224.07:48:21.97#ibcon#first serial, iclass 21, count 2 2006.224.07:48:21.97#ibcon#enter sib2, iclass 21, count 2 2006.224.07:48:21.97#ibcon#flushed, iclass 21, count 2 2006.224.07:48:21.97#ibcon#about to write, iclass 21, count 2 2006.224.07:48:21.97#ibcon#wrote, iclass 21, count 2 2006.224.07:48:21.97#ibcon#about to read 3, iclass 21, count 2 2006.224.07:48:21.99#ibcon#read 3, iclass 21, count 2 2006.224.07:48:21.99#ibcon#about to read 4, iclass 21, count 2 2006.224.07:48:21.99#ibcon#read 4, iclass 21, count 2 2006.224.07:48:21.99#ibcon#about to read 5, iclass 21, count 2 2006.224.07:48:21.99#ibcon#read 5, iclass 21, count 2 2006.224.07:48:21.99#ibcon#about to read 6, iclass 21, count 2 2006.224.07:48:21.99#ibcon#read 6, iclass 21, count 2 2006.224.07:48:21.99#ibcon#end of sib2, iclass 21, count 2 2006.224.07:48:21.99#ibcon#*mode == 0, iclass 21, count 2 2006.224.07:48:21.99#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.224.07:48:21.99#ibcon#[27=AT05-04\r\n] 2006.224.07:48:21.99#ibcon#*before write, iclass 21, count 2 2006.224.07:48:21.99#ibcon#enter sib2, iclass 21, count 2 2006.224.07:48:21.99#ibcon#flushed, iclass 21, count 2 2006.224.07:48:21.99#ibcon#about to write, iclass 21, count 2 2006.224.07:48:21.99#ibcon#wrote, iclass 21, count 2 2006.224.07:48:21.99#ibcon#about to read 3, iclass 21, count 2 2006.224.07:48:22.02#ibcon#read 3, iclass 21, count 2 2006.224.07:48:22.02#ibcon#about to read 4, iclass 21, count 2 2006.224.07:48:22.02#ibcon#read 4, iclass 21, count 2 2006.224.07:48:22.02#ibcon#about to read 5, iclass 21, count 2 2006.224.07:48:22.02#ibcon#read 5, iclass 21, count 2 2006.224.07:48:22.02#ibcon#about to read 6, iclass 21, count 2 2006.224.07:48:22.02#ibcon#read 6, iclass 21, count 2 2006.224.07:48:22.02#ibcon#end of sib2, iclass 21, count 2 2006.224.07:48:22.02#ibcon#*after write, iclass 21, count 2 2006.224.07:48:22.02#ibcon#*before return 0, iclass 21, count 2 2006.224.07:48:22.02#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.224.07:48:22.02#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.224.07:48:22.02#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.224.07:48:22.02#ibcon#ireg 7 cls_cnt 0 2006.224.07:48:22.02#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.224.07:48:22.14#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.224.07:48:22.14#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.224.07:48:22.14#ibcon#enter wrdev, iclass 21, count 0 2006.224.07:48:22.14#ibcon#first serial, iclass 21, count 0 2006.224.07:48:22.14#ibcon#enter sib2, iclass 21, count 0 2006.224.07:48:22.14#ibcon#flushed, iclass 21, count 0 2006.224.07:48:22.14#ibcon#about to write, iclass 21, count 0 2006.224.07:48:22.14#ibcon#wrote, iclass 21, count 0 2006.224.07:48:22.14#ibcon#about to read 3, iclass 21, count 0 2006.224.07:48:22.16#ibcon#read 3, iclass 21, count 0 2006.224.07:48:22.16#ibcon#about to read 4, iclass 21, count 0 2006.224.07:48:22.16#ibcon#read 4, iclass 21, count 0 2006.224.07:48:22.16#ibcon#about to read 5, iclass 21, count 0 2006.224.07:48:22.16#ibcon#read 5, iclass 21, count 0 2006.224.07:48:22.16#ibcon#about to read 6, iclass 21, count 0 2006.224.07:48:22.16#ibcon#read 6, iclass 21, count 0 2006.224.07:48:22.16#ibcon#end of sib2, iclass 21, count 0 2006.224.07:48:22.16#ibcon#*mode == 0, iclass 21, count 0 2006.224.07:48:22.16#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.224.07:48:22.16#ibcon#[27=USB\r\n] 2006.224.07:48:22.16#ibcon#*before write, iclass 21, count 0 2006.224.07:48:22.16#ibcon#enter sib2, iclass 21, count 0 2006.224.07:48:22.16#ibcon#flushed, iclass 21, count 0 2006.224.07:48:22.16#ibcon#about to write, iclass 21, count 0 2006.224.07:48:22.16#ibcon#wrote, iclass 21, count 0 2006.224.07:48:22.16#ibcon#about to read 3, iclass 21, count 0 2006.224.07:48:22.19#ibcon#read 3, iclass 21, count 0 2006.224.07:48:22.19#ibcon#about to read 4, iclass 21, count 0 2006.224.07:48:22.19#ibcon#read 4, iclass 21, count 0 2006.224.07:48:22.19#ibcon#about to read 5, iclass 21, count 0 2006.224.07:48:22.19#ibcon#read 5, iclass 21, count 0 2006.224.07:48:22.19#ibcon#about to read 6, iclass 21, count 0 2006.224.07:48:22.19#ibcon#read 6, iclass 21, count 0 2006.224.07:48:22.19#ibcon#end of sib2, iclass 21, count 0 2006.224.07:48:22.19#ibcon#*after write, iclass 21, count 0 2006.224.07:48:22.19#ibcon#*before return 0, iclass 21, count 0 2006.224.07:48:22.19#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.224.07:48:22.19#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.224.07:48:22.19#ibcon#about to clear, iclass 21 cls_cnt 0 2006.224.07:48:22.19#ibcon#cleared, iclass 21 cls_cnt 0 2006.224.07:48:22.19$vc4f8/vblo=6,752.99 2006.224.07:48:22.19#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.224.07:48:22.19#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.224.07:48:22.19#ibcon#ireg 17 cls_cnt 0 2006.224.07:48:22.19#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.224.07:48:22.19#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.224.07:48:22.19#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.224.07:48:22.19#ibcon#enter wrdev, iclass 23, count 0 2006.224.07:48:22.19#ibcon#first serial, iclass 23, count 0 2006.224.07:48:22.19#ibcon#enter sib2, iclass 23, count 0 2006.224.07:48:22.19#ibcon#flushed, iclass 23, count 0 2006.224.07:48:22.19#ibcon#about to write, iclass 23, count 0 2006.224.07:48:22.19#ibcon#wrote, iclass 23, count 0 2006.224.07:48:22.19#ibcon#about to read 3, iclass 23, count 0 2006.224.07:48:22.21#ibcon#read 3, iclass 23, count 0 2006.224.07:48:22.21#ibcon#about to read 4, iclass 23, count 0 2006.224.07:48:22.21#ibcon#read 4, iclass 23, count 0 2006.224.07:48:22.21#ibcon#about to read 5, iclass 23, count 0 2006.224.07:48:22.21#ibcon#read 5, iclass 23, count 0 2006.224.07:48:22.21#ibcon#about to read 6, iclass 23, count 0 2006.224.07:48:22.21#ibcon#read 6, iclass 23, count 0 2006.224.07:48:22.21#ibcon#end of sib2, iclass 23, count 0 2006.224.07:48:22.21#ibcon#*mode == 0, iclass 23, count 0 2006.224.07:48:22.21#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.224.07:48:22.21#ibcon#[28=FRQ=06,752.99\r\n] 2006.224.07:48:22.21#ibcon#*before write, iclass 23, count 0 2006.224.07:48:22.21#ibcon#enter sib2, iclass 23, count 0 2006.224.07:48:22.21#ibcon#flushed, iclass 23, count 0 2006.224.07:48:22.21#ibcon#about to write, iclass 23, count 0 2006.224.07:48:22.21#ibcon#wrote, iclass 23, count 0 2006.224.07:48:22.21#ibcon#about to read 3, iclass 23, count 0 2006.224.07:48:22.25#ibcon#read 3, iclass 23, count 0 2006.224.07:48:22.25#ibcon#about to read 4, iclass 23, count 0 2006.224.07:48:22.25#ibcon#read 4, iclass 23, count 0 2006.224.07:48:22.25#ibcon#about to read 5, iclass 23, count 0 2006.224.07:48:22.25#ibcon#read 5, iclass 23, count 0 2006.224.07:48:22.25#ibcon#about to read 6, iclass 23, count 0 2006.224.07:48:22.25#ibcon#read 6, iclass 23, count 0 2006.224.07:48:22.25#ibcon#end of sib2, iclass 23, count 0 2006.224.07:48:22.25#ibcon#*after write, iclass 23, count 0 2006.224.07:48:22.25#ibcon#*before return 0, iclass 23, count 0 2006.224.07:48:22.25#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.224.07:48:22.25#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.224.07:48:22.25#ibcon#about to clear, iclass 23 cls_cnt 0 2006.224.07:48:22.25#ibcon#cleared, iclass 23 cls_cnt 0 2006.224.07:48:22.25$vc4f8/vb=6,4 2006.224.07:48:22.25#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.224.07:48:22.25#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.224.07:48:22.25#ibcon#ireg 11 cls_cnt 2 2006.224.07:48:22.25#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.224.07:48:22.31#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.224.07:48:22.31#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.224.07:48:22.31#ibcon#enter wrdev, iclass 25, count 2 2006.224.07:48:22.31#ibcon#first serial, iclass 25, count 2 2006.224.07:48:22.31#ibcon#enter sib2, iclass 25, count 2 2006.224.07:48:22.31#ibcon#flushed, iclass 25, count 2 2006.224.07:48:22.31#ibcon#about to write, iclass 25, count 2 2006.224.07:48:22.32#ibcon#wrote, iclass 25, count 2 2006.224.07:48:22.32#ibcon#about to read 3, iclass 25, count 2 2006.224.07:48:22.33#ibcon#read 3, iclass 25, count 2 2006.224.07:48:22.33#ibcon#about to read 4, iclass 25, count 2 2006.224.07:48:22.33#ibcon#read 4, iclass 25, count 2 2006.224.07:48:22.33#ibcon#about to read 5, iclass 25, count 2 2006.224.07:48:22.33#ibcon#read 5, iclass 25, count 2 2006.224.07:48:22.33#ibcon#about to read 6, iclass 25, count 2 2006.224.07:48:22.33#ibcon#read 6, iclass 25, count 2 2006.224.07:48:22.33#ibcon#end of sib2, iclass 25, count 2 2006.224.07:48:22.33#ibcon#*mode == 0, iclass 25, count 2 2006.224.07:48:22.33#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.224.07:48:22.33#ibcon#[27=AT06-04\r\n] 2006.224.07:48:22.33#ibcon#*before write, iclass 25, count 2 2006.224.07:48:22.33#ibcon#enter sib2, iclass 25, count 2 2006.224.07:48:22.33#ibcon#flushed, iclass 25, count 2 2006.224.07:48:22.33#ibcon#about to write, iclass 25, count 2 2006.224.07:48:22.33#ibcon#wrote, iclass 25, count 2 2006.224.07:48:22.33#ibcon#about to read 3, iclass 25, count 2 2006.224.07:48:22.36#ibcon#read 3, iclass 25, count 2 2006.224.07:48:22.36#ibcon#about to read 4, iclass 25, count 2 2006.224.07:48:22.36#ibcon#read 4, iclass 25, count 2 2006.224.07:48:22.36#ibcon#about to read 5, iclass 25, count 2 2006.224.07:48:22.36#ibcon#read 5, iclass 25, count 2 2006.224.07:48:22.36#ibcon#about to read 6, iclass 25, count 2 2006.224.07:48:22.36#ibcon#read 6, iclass 25, count 2 2006.224.07:48:22.36#ibcon#end of sib2, iclass 25, count 2 2006.224.07:48:22.36#ibcon#*after write, iclass 25, count 2 2006.224.07:48:22.36#ibcon#*before return 0, iclass 25, count 2 2006.224.07:48:22.36#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.224.07:48:22.36#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.224.07:48:22.36#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.224.07:48:22.36#ibcon#ireg 7 cls_cnt 0 2006.224.07:48:22.36#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.224.07:48:22.48#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.224.07:48:22.48#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.224.07:48:22.48#ibcon#enter wrdev, iclass 25, count 0 2006.224.07:48:22.48#ibcon#first serial, iclass 25, count 0 2006.224.07:48:22.48#ibcon#enter sib2, iclass 25, count 0 2006.224.07:48:22.48#ibcon#flushed, iclass 25, count 0 2006.224.07:48:22.48#ibcon#about to write, iclass 25, count 0 2006.224.07:48:22.48#ibcon#wrote, iclass 25, count 0 2006.224.07:48:22.48#ibcon#about to read 3, iclass 25, count 0 2006.224.07:48:22.50#ibcon#read 3, iclass 25, count 0 2006.224.07:48:22.50#ibcon#about to read 4, iclass 25, count 0 2006.224.07:48:22.50#ibcon#read 4, iclass 25, count 0 2006.224.07:48:22.50#ibcon#about to read 5, iclass 25, count 0 2006.224.07:48:22.50#ibcon#read 5, iclass 25, count 0 2006.224.07:48:22.50#ibcon#about to read 6, iclass 25, count 0 2006.224.07:48:22.50#ibcon#read 6, iclass 25, count 0 2006.224.07:48:22.50#ibcon#end of sib2, iclass 25, count 0 2006.224.07:48:22.50#ibcon#*mode == 0, iclass 25, count 0 2006.224.07:48:22.50#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.224.07:48:22.50#ibcon#[27=USB\r\n] 2006.224.07:48:22.50#ibcon#*before write, iclass 25, count 0 2006.224.07:48:22.50#ibcon#enter sib2, iclass 25, count 0 2006.224.07:48:22.50#ibcon#flushed, iclass 25, count 0 2006.224.07:48:22.50#ibcon#about to write, iclass 25, count 0 2006.224.07:48:22.50#ibcon#wrote, iclass 25, count 0 2006.224.07:48:22.50#ibcon#about to read 3, iclass 25, count 0 2006.224.07:48:22.53#ibcon#read 3, iclass 25, count 0 2006.224.07:48:22.53#ibcon#about to read 4, iclass 25, count 0 2006.224.07:48:22.53#ibcon#read 4, iclass 25, count 0 2006.224.07:48:22.53#ibcon#about to read 5, iclass 25, count 0 2006.224.07:48:22.53#ibcon#read 5, iclass 25, count 0 2006.224.07:48:22.53#ibcon#about to read 6, iclass 25, count 0 2006.224.07:48:22.53#ibcon#read 6, iclass 25, count 0 2006.224.07:48:22.53#ibcon#end of sib2, iclass 25, count 0 2006.224.07:48:22.53#ibcon#*after write, iclass 25, count 0 2006.224.07:48:22.53#ibcon#*before return 0, iclass 25, count 0 2006.224.07:48:22.53#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.224.07:48:22.53#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.224.07:48:22.53#ibcon#about to clear, iclass 25 cls_cnt 0 2006.224.07:48:22.53#ibcon#cleared, iclass 25 cls_cnt 0 2006.224.07:48:22.53$vc4f8/vabw=wide 2006.224.07:48:22.53#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.224.07:48:22.53#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.224.07:48:22.53#ibcon#ireg 8 cls_cnt 0 2006.224.07:48:22.53#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.224.07:48:22.53#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.224.07:48:22.53#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.224.07:48:22.53#ibcon#enter wrdev, iclass 27, count 0 2006.224.07:48:22.53#ibcon#first serial, iclass 27, count 0 2006.224.07:48:22.53#ibcon#enter sib2, iclass 27, count 0 2006.224.07:48:22.53#ibcon#flushed, iclass 27, count 0 2006.224.07:48:22.53#ibcon#about to write, iclass 27, count 0 2006.224.07:48:22.53#ibcon#wrote, iclass 27, count 0 2006.224.07:48:22.53#ibcon#about to read 3, iclass 27, count 0 2006.224.07:48:22.55#ibcon#read 3, iclass 27, count 0 2006.224.07:48:22.55#ibcon#about to read 4, iclass 27, count 0 2006.224.07:48:22.55#ibcon#read 4, iclass 27, count 0 2006.224.07:48:22.55#ibcon#about to read 5, iclass 27, count 0 2006.224.07:48:22.55#ibcon#read 5, iclass 27, count 0 2006.224.07:48:22.55#ibcon#about to read 6, iclass 27, count 0 2006.224.07:48:22.55#ibcon#read 6, iclass 27, count 0 2006.224.07:48:22.55#ibcon#end of sib2, iclass 27, count 0 2006.224.07:48:22.55#ibcon#*mode == 0, iclass 27, count 0 2006.224.07:48:22.55#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.224.07:48:22.55#ibcon#[25=BW32\r\n] 2006.224.07:48:22.55#ibcon#*before write, iclass 27, count 0 2006.224.07:48:22.55#ibcon#enter sib2, iclass 27, count 0 2006.224.07:48:22.55#ibcon#flushed, iclass 27, count 0 2006.224.07:48:22.55#ibcon#about to write, iclass 27, count 0 2006.224.07:48:22.55#ibcon#wrote, iclass 27, count 0 2006.224.07:48:22.55#ibcon#about to read 3, iclass 27, count 0 2006.224.07:48:22.58#ibcon#read 3, iclass 27, count 0 2006.224.07:48:22.58#ibcon#about to read 4, iclass 27, count 0 2006.224.07:48:22.58#ibcon#read 4, iclass 27, count 0 2006.224.07:48:22.58#ibcon#about to read 5, iclass 27, count 0 2006.224.07:48:22.58#ibcon#read 5, iclass 27, count 0 2006.224.07:48:22.58#ibcon#about to read 6, iclass 27, count 0 2006.224.07:48:22.58#ibcon#read 6, iclass 27, count 0 2006.224.07:48:22.58#ibcon#end of sib2, iclass 27, count 0 2006.224.07:48:22.58#ibcon#*after write, iclass 27, count 0 2006.224.07:48:22.58#ibcon#*before return 0, iclass 27, count 0 2006.224.07:48:22.58#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.224.07:48:22.58#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.224.07:48:22.58#ibcon#about to clear, iclass 27 cls_cnt 0 2006.224.07:48:22.58#ibcon#cleared, iclass 27 cls_cnt 0 2006.224.07:48:22.58$vc4f8/vbbw=wide 2006.224.07:48:22.58#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.224.07:48:22.58#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.224.07:48:22.58#ibcon#ireg 8 cls_cnt 0 2006.224.07:48:22.58#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.224.07:48:22.65#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.224.07:48:22.65#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.224.07:48:22.65#ibcon#enter wrdev, iclass 29, count 0 2006.224.07:48:22.65#ibcon#first serial, iclass 29, count 0 2006.224.07:48:22.65#ibcon#enter sib2, iclass 29, count 0 2006.224.07:48:22.65#ibcon#flushed, iclass 29, count 0 2006.224.07:48:22.65#ibcon#about to write, iclass 29, count 0 2006.224.07:48:22.65#ibcon#wrote, iclass 29, count 0 2006.224.07:48:22.65#ibcon#about to read 3, iclass 29, count 0 2006.224.07:48:22.67#ibcon#read 3, iclass 29, count 0 2006.224.07:48:22.67#ibcon#about to read 4, iclass 29, count 0 2006.224.07:48:22.67#ibcon#read 4, iclass 29, count 0 2006.224.07:48:22.67#ibcon#about to read 5, iclass 29, count 0 2006.224.07:48:22.67#ibcon#read 5, iclass 29, count 0 2006.224.07:48:22.67#ibcon#about to read 6, iclass 29, count 0 2006.224.07:48:22.67#ibcon#read 6, iclass 29, count 0 2006.224.07:48:22.67#ibcon#end of sib2, iclass 29, count 0 2006.224.07:48:22.67#ibcon#*mode == 0, iclass 29, count 0 2006.224.07:48:22.67#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.224.07:48:22.67#ibcon#[27=BW32\r\n] 2006.224.07:48:22.67#ibcon#*before write, iclass 29, count 0 2006.224.07:48:22.67#ibcon#enter sib2, iclass 29, count 0 2006.224.07:48:22.67#ibcon#flushed, iclass 29, count 0 2006.224.07:48:22.67#ibcon#about to write, iclass 29, count 0 2006.224.07:48:22.67#ibcon#wrote, iclass 29, count 0 2006.224.07:48:22.67#ibcon#about to read 3, iclass 29, count 0 2006.224.07:48:22.70#ibcon#read 3, iclass 29, count 0 2006.224.07:48:22.70#ibcon#about to read 4, iclass 29, count 0 2006.224.07:48:22.70#ibcon#read 4, iclass 29, count 0 2006.224.07:48:22.70#ibcon#about to read 5, iclass 29, count 0 2006.224.07:48:22.70#ibcon#read 5, iclass 29, count 0 2006.224.07:48:22.70#ibcon#about to read 6, iclass 29, count 0 2006.224.07:48:22.70#ibcon#read 6, iclass 29, count 0 2006.224.07:48:22.70#ibcon#end of sib2, iclass 29, count 0 2006.224.07:48:22.70#ibcon#*after write, iclass 29, count 0 2006.224.07:48:22.70#ibcon#*before return 0, iclass 29, count 0 2006.224.07:48:22.70#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.224.07:48:22.70#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.224.07:48:22.70#ibcon#about to clear, iclass 29 cls_cnt 0 2006.224.07:48:22.70#ibcon#cleared, iclass 29 cls_cnt 0 2006.224.07:48:22.70$4f8m12a/ifd4f 2006.224.07:48:22.70$ifd4f/lo= 2006.224.07:48:22.70$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.224.07:48:22.70$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.224.07:48:22.70$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.224.07:48:22.70$ifd4f/patch= 2006.224.07:48:22.70$ifd4f/patch=lo1,a1,a2,a3,a4 2006.224.07:48:22.70$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.224.07:48:22.70$ifd4f/patch=lo3,a5,a6,a7,a8 2006.224.07:48:22.70$4f8m12a/"form=m,16.000,1:2 2006.224.07:48:22.70$4f8m12a/"tpicd 2006.224.07:48:22.71$4f8m12a/echo=off 2006.224.07:48:22.71$4f8m12a/xlog=off 2006.224.07:48:22.71:!2006.224.07:48:50 2006.224.07:48:31.14#trakl#Source acquired 2006.224.07:48:31.14#flagr#flagr/antenna,acquired 2006.224.07:48:50.01:preob 2006.224.07:48:51.14/onsource/TRACKING 2006.224.07:48:51.14:!2006.224.07:49:00 2006.224.07:49:00.00:data_valid=on 2006.224.07:49:00.00:midob 2006.224.07:49:00.14/onsource/TRACKING 2006.224.07:49:00.14/wx/23.61,1004.2,100 2006.224.07:49:00.21/cable/+6.4322E-03 2006.224.07:49:01.30/va/01,08,usb,yes,43,45 2006.224.07:49:01.30/va/02,07,usb,yes,43,45 2006.224.07:49:01.30/va/03,06,usb,yes,46,46 2006.224.07:49:01.30/va/04,07,usb,yes,45,49 2006.224.07:49:01.30/va/05,07,usb,yes,53,56 2006.224.07:49:01.30/va/06,06,usb,yes,53,52 2006.224.07:49:01.30/va/07,06,usb,yes,54,54 2006.224.07:49:01.30/va/08,07,usb,yes,52,51 2006.224.07:49:01.53/valo/01,532.99,yes,locked 2006.224.07:49:01.53/valo/02,572.99,yes,locked 2006.224.07:49:01.53/valo/03,672.99,yes,locked 2006.224.07:49:01.53/valo/04,832.99,yes,locked 2006.224.07:49:01.53/valo/05,652.99,yes,locked 2006.224.07:49:01.53/valo/06,772.99,yes,locked 2006.224.07:49:01.53/valo/07,832.99,yes,locked 2006.224.07:49:01.53/valo/08,852.99,yes,locked 2006.224.07:49:02.62/vb/01,04,usb,yes,32,31 2006.224.07:49:02.62/vb/02,04,usb,yes,34,36 2006.224.07:49:02.62/vb/03,04,usb,yes,30,34 2006.224.07:49:02.62/vb/04,04,usb,yes,31,31 2006.224.07:49:02.62/vb/05,04,usb,yes,30,34 2006.224.07:49:02.62/vb/06,04,usb,yes,31,34 2006.224.07:49:02.62/vb/07,04,usb,yes,33,33 2006.224.07:49:02.62/vb/08,04,usb,yes,30,34 2006.224.07:49:02.85/vblo/01,632.99,yes,locked 2006.224.07:49:02.85/vblo/02,640.99,yes,locked 2006.224.07:49:02.85/vblo/03,656.99,yes,locked 2006.224.07:49:02.85/vblo/04,712.99,yes,locked 2006.224.07:49:02.85/vblo/05,744.99,yes,locked 2006.224.07:49:02.85/vblo/06,752.99,yes,locked 2006.224.07:49:02.85/vblo/07,734.99,yes,locked 2006.224.07:49:02.85/vblo/08,744.99,yes,locked 2006.224.07:49:03.00/vabw/8 2006.224.07:49:03.15/vbbw/8 2006.224.07:49:03.30/xfe/off,on,15.2 2006.224.07:49:03.69/ifatt/23,28,28,28 2006.224.07:49:04.08/fmout-gps/S +4.26E-07 2006.224.07:49:04.12:!2006.224.07:50:00 2006.224.07:50:00.00:data_valid=off 2006.224.07:50:00.00:postob 2006.224.07:50:00.09/cable/+6.4327E-03 2006.224.07:50:00.09/wx/23.61,1004.1,100 2006.224.07:50:01.07/fmout-gps/S +4.26E-07 2006.224.07:50:01.07:scan_name=224-0750,k06224,60 2006.224.07:50:01.07:source=0642+449,064632.03,445116.6,2000.0,ccw 2006.224.07:50:02.14#flagr#flagr/antenna,new-source 2006.224.07:50:02.14:checkk5 2006.224.07:50:02.52/chk_autoobs//k5ts1/ autoobs is running! 2006.224.07:50:02.89/chk_autoobs//k5ts2/ autoobs is running! 2006.224.07:50:03.27/chk_autoobs//k5ts3/ autoobs is running! 2006.224.07:50:03.65/chk_autoobs//k5ts4/ autoobs is running! 2006.224.07:50:04.01/chk_obsdata//k5ts1/T2240749??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.07:50:04.37/chk_obsdata//k5ts2/T2240749??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.07:50:04.74/chk_obsdata//k5ts3/T2240749??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.07:50:05.10/chk_obsdata//k5ts4/T2240749??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.07:50:05.79/k5log//k5ts1_log_newline 2006.224.07:50:06.47/k5log//k5ts2_log_newline 2006.224.07:50:07.16/k5log//k5ts3_log_newline 2006.224.07:50:07.84/k5log//k5ts4_log_newline 2006.224.07:50:07.86/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.224.07:50:07.86:4f8m12a=1 2006.224.07:50:07.86$4f8m12a/echo=on 2006.224.07:50:07.86$4f8m12a/pcalon 2006.224.07:50:07.86$pcalon/"no phase cal control is implemented here 2006.224.07:50:07.86$4f8m12a/"tpicd=stop 2006.224.07:50:07.86$4f8m12a/vc4f8 2006.224.07:50:07.86$vc4f8/valo=1,532.99 2006.224.07:50:07.87#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.224.07:50:07.87#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.224.07:50:07.87#ibcon#ireg 17 cls_cnt 0 2006.224.07:50:07.87#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.224.07:50:07.87#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.224.07:50:07.87#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.224.07:50:07.87#ibcon#enter wrdev, iclass 36, count 0 2006.224.07:50:07.87#ibcon#first serial, iclass 36, count 0 2006.224.07:50:07.87#ibcon#enter sib2, iclass 36, count 0 2006.224.07:50:07.87#ibcon#flushed, iclass 36, count 0 2006.224.07:50:07.87#ibcon#about to write, iclass 36, count 0 2006.224.07:50:07.87#ibcon#wrote, iclass 36, count 0 2006.224.07:50:07.87#ibcon#about to read 3, iclass 36, count 0 2006.224.07:50:07.91#ibcon#read 3, iclass 36, count 0 2006.224.07:50:07.91#ibcon#about to read 4, iclass 36, count 0 2006.224.07:50:07.91#ibcon#read 4, iclass 36, count 0 2006.224.07:50:07.91#ibcon#about to read 5, iclass 36, count 0 2006.224.07:50:07.91#ibcon#read 5, iclass 36, count 0 2006.224.07:50:07.91#ibcon#about to read 6, iclass 36, count 0 2006.224.07:50:07.91#ibcon#read 6, iclass 36, count 0 2006.224.07:50:07.91#ibcon#end of sib2, iclass 36, count 0 2006.224.07:50:07.91#ibcon#*mode == 0, iclass 36, count 0 2006.224.07:50:07.91#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.224.07:50:07.91#ibcon#[26=FRQ=01,532.99\r\n] 2006.224.07:50:07.91#ibcon#*before write, iclass 36, count 0 2006.224.07:50:07.91#ibcon#enter sib2, iclass 36, count 0 2006.224.07:50:07.91#ibcon#flushed, iclass 36, count 0 2006.224.07:50:07.91#ibcon#about to write, iclass 36, count 0 2006.224.07:50:07.91#ibcon#wrote, iclass 36, count 0 2006.224.07:50:07.91#ibcon#about to read 3, iclass 36, count 0 2006.224.07:50:07.95#ibcon#read 3, iclass 36, count 0 2006.224.07:50:07.95#ibcon#about to read 4, iclass 36, count 0 2006.224.07:50:07.95#ibcon#read 4, iclass 36, count 0 2006.224.07:50:07.95#ibcon#about to read 5, iclass 36, count 0 2006.224.07:50:07.95#ibcon#read 5, iclass 36, count 0 2006.224.07:50:07.95#ibcon#about to read 6, iclass 36, count 0 2006.224.07:50:07.95#ibcon#read 6, iclass 36, count 0 2006.224.07:50:07.95#ibcon#end of sib2, iclass 36, count 0 2006.224.07:50:07.95#ibcon#*after write, iclass 36, count 0 2006.224.07:50:07.95#ibcon#*before return 0, iclass 36, count 0 2006.224.07:50:07.95#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.224.07:50:07.95#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.224.07:50:07.95#ibcon#about to clear, iclass 36 cls_cnt 0 2006.224.07:50:07.95#ibcon#cleared, iclass 36 cls_cnt 0 2006.224.07:50:07.95$vc4f8/va=1,8 2006.224.07:50:07.95#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.224.07:50:07.95#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.224.07:50:07.95#ibcon#ireg 11 cls_cnt 2 2006.224.07:50:07.95#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.224.07:50:07.95#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.224.07:50:07.95#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.224.07:50:07.95#ibcon#enter wrdev, iclass 38, count 2 2006.224.07:50:07.95#ibcon#first serial, iclass 38, count 2 2006.224.07:50:07.95#ibcon#enter sib2, iclass 38, count 2 2006.224.07:50:07.95#ibcon#flushed, iclass 38, count 2 2006.224.07:50:07.95#ibcon#about to write, iclass 38, count 2 2006.224.07:50:07.95#ibcon#wrote, iclass 38, count 2 2006.224.07:50:07.95#ibcon#about to read 3, iclass 38, count 2 2006.224.07:50:07.97#ibcon#read 3, iclass 38, count 2 2006.224.07:50:07.97#ibcon#about to read 4, iclass 38, count 2 2006.224.07:50:07.97#ibcon#read 4, iclass 38, count 2 2006.224.07:50:07.97#ibcon#about to read 5, iclass 38, count 2 2006.224.07:50:07.97#ibcon#read 5, iclass 38, count 2 2006.224.07:50:07.97#ibcon#about to read 6, iclass 38, count 2 2006.224.07:50:07.97#ibcon#read 6, iclass 38, count 2 2006.224.07:50:07.97#ibcon#end of sib2, iclass 38, count 2 2006.224.07:50:07.97#ibcon#*mode == 0, iclass 38, count 2 2006.224.07:50:07.97#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.224.07:50:07.97#ibcon#[25=AT01-08\r\n] 2006.224.07:50:07.97#ibcon#*before write, iclass 38, count 2 2006.224.07:50:07.97#ibcon#enter sib2, iclass 38, count 2 2006.224.07:50:07.97#ibcon#flushed, iclass 38, count 2 2006.224.07:50:07.97#ibcon#about to write, iclass 38, count 2 2006.224.07:50:07.97#ibcon#wrote, iclass 38, count 2 2006.224.07:50:07.97#ibcon#about to read 3, iclass 38, count 2 2006.224.07:50:08.00#ibcon#read 3, iclass 38, count 2 2006.224.07:50:08.00#ibcon#about to read 4, iclass 38, count 2 2006.224.07:50:08.00#ibcon#read 4, iclass 38, count 2 2006.224.07:50:08.00#ibcon#about to read 5, iclass 38, count 2 2006.224.07:50:08.00#ibcon#read 5, iclass 38, count 2 2006.224.07:50:08.00#ibcon#about to read 6, iclass 38, count 2 2006.224.07:50:08.00#ibcon#read 6, iclass 38, count 2 2006.224.07:50:08.00#ibcon#end of sib2, iclass 38, count 2 2006.224.07:50:08.00#ibcon#*after write, iclass 38, count 2 2006.224.07:50:08.00#ibcon#*before return 0, iclass 38, count 2 2006.224.07:50:08.00#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.224.07:50:08.00#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.224.07:50:08.00#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.224.07:50:08.00#ibcon#ireg 7 cls_cnt 0 2006.224.07:50:08.00#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.224.07:50:08.12#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.224.07:50:08.12#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.224.07:50:08.12#ibcon#enter wrdev, iclass 38, count 0 2006.224.07:50:08.12#ibcon#first serial, iclass 38, count 0 2006.224.07:50:08.12#ibcon#enter sib2, iclass 38, count 0 2006.224.07:50:08.12#ibcon#flushed, iclass 38, count 0 2006.224.07:50:08.12#ibcon#about to write, iclass 38, count 0 2006.224.07:50:08.12#ibcon#wrote, iclass 38, count 0 2006.224.07:50:08.12#ibcon#about to read 3, iclass 38, count 0 2006.224.07:50:08.14#ibcon#read 3, iclass 38, count 0 2006.224.07:50:08.14#ibcon#about to read 4, iclass 38, count 0 2006.224.07:50:08.14#ibcon#read 4, iclass 38, count 0 2006.224.07:50:08.14#ibcon#about to read 5, iclass 38, count 0 2006.224.07:50:08.14#ibcon#read 5, iclass 38, count 0 2006.224.07:50:08.14#ibcon#about to read 6, iclass 38, count 0 2006.224.07:50:08.14#ibcon#read 6, iclass 38, count 0 2006.224.07:50:08.14#ibcon#end of sib2, iclass 38, count 0 2006.224.07:50:08.14#ibcon#*mode == 0, iclass 38, count 0 2006.224.07:50:08.14#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.224.07:50:08.14#ibcon#[25=USB\r\n] 2006.224.07:50:08.14#ibcon#*before write, iclass 38, count 0 2006.224.07:50:08.14#ibcon#enter sib2, iclass 38, count 0 2006.224.07:50:08.14#ibcon#flushed, iclass 38, count 0 2006.224.07:50:08.14#ibcon#about to write, iclass 38, count 0 2006.224.07:50:08.14#ibcon#wrote, iclass 38, count 0 2006.224.07:50:08.14#ibcon#about to read 3, iclass 38, count 0 2006.224.07:50:08.17#ibcon#read 3, iclass 38, count 0 2006.224.07:50:08.17#ibcon#about to read 4, iclass 38, count 0 2006.224.07:50:08.17#ibcon#read 4, iclass 38, count 0 2006.224.07:50:08.17#ibcon#about to read 5, iclass 38, count 0 2006.224.07:50:08.17#ibcon#read 5, iclass 38, count 0 2006.224.07:50:08.17#ibcon#about to read 6, iclass 38, count 0 2006.224.07:50:08.17#ibcon#read 6, iclass 38, count 0 2006.224.07:50:08.17#ibcon#end of sib2, iclass 38, count 0 2006.224.07:50:08.17#ibcon#*after write, iclass 38, count 0 2006.224.07:50:08.17#ibcon#*before return 0, iclass 38, count 0 2006.224.07:50:08.17#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.224.07:50:08.17#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.224.07:50:08.17#ibcon#about to clear, iclass 38 cls_cnt 0 2006.224.07:50:08.17#ibcon#cleared, iclass 38 cls_cnt 0 2006.224.07:50:08.17$vc4f8/valo=2,572.99 2006.224.07:50:08.17#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.224.07:50:08.17#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.224.07:50:08.17#ibcon#ireg 17 cls_cnt 0 2006.224.07:50:08.17#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.224.07:50:08.17#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.224.07:50:08.17#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.224.07:50:08.17#ibcon#enter wrdev, iclass 40, count 0 2006.224.07:50:08.17#ibcon#first serial, iclass 40, count 0 2006.224.07:50:08.17#ibcon#enter sib2, iclass 40, count 0 2006.224.07:50:08.17#ibcon#flushed, iclass 40, count 0 2006.224.07:50:08.17#ibcon#about to write, iclass 40, count 0 2006.224.07:50:08.17#ibcon#wrote, iclass 40, count 0 2006.224.07:50:08.17#ibcon#about to read 3, iclass 40, count 0 2006.224.07:50:08.19#ibcon#read 3, iclass 40, count 0 2006.224.07:50:08.19#ibcon#about to read 4, iclass 40, count 0 2006.224.07:50:08.19#ibcon#read 4, iclass 40, count 0 2006.224.07:50:08.19#ibcon#about to read 5, iclass 40, count 0 2006.224.07:50:08.19#ibcon#read 5, iclass 40, count 0 2006.224.07:50:08.19#ibcon#about to read 6, iclass 40, count 0 2006.224.07:50:08.19#ibcon#read 6, iclass 40, count 0 2006.224.07:50:08.19#ibcon#end of sib2, iclass 40, count 0 2006.224.07:50:08.19#ibcon#*mode == 0, iclass 40, count 0 2006.224.07:50:08.19#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.224.07:50:08.19#ibcon#[26=FRQ=02,572.99\r\n] 2006.224.07:50:08.19#ibcon#*before write, iclass 40, count 0 2006.224.07:50:08.19#ibcon#enter sib2, iclass 40, count 0 2006.224.07:50:08.19#ibcon#flushed, iclass 40, count 0 2006.224.07:50:08.19#ibcon#about to write, iclass 40, count 0 2006.224.07:50:08.19#ibcon#wrote, iclass 40, count 0 2006.224.07:50:08.19#ibcon#about to read 3, iclass 40, count 0 2006.224.07:50:08.23#ibcon#read 3, iclass 40, count 0 2006.224.07:50:08.23#ibcon#about to read 4, iclass 40, count 0 2006.224.07:50:08.23#ibcon#read 4, iclass 40, count 0 2006.224.07:50:08.23#ibcon#about to read 5, iclass 40, count 0 2006.224.07:50:08.23#ibcon#read 5, iclass 40, count 0 2006.224.07:50:08.23#ibcon#about to read 6, iclass 40, count 0 2006.224.07:50:08.23#ibcon#read 6, iclass 40, count 0 2006.224.07:50:08.23#ibcon#end of sib2, iclass 40, count 0 2006.224.07:50:08.23#ibcon#*after write, iclass 40, count 0 2006.224.07:50:08.23#ibcon#*before return 0, iclass 40, count 0 2006.224.07:50:08.23#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.224.07:50:08.23#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.224.07:50:08.23#ibcon#about to clear, iclass 40 cls_cnt 0 2006.224.07:50:08.23#ibcon#cleared, iclass 40 cls_cnt 0 2006.224.07:50:08.23$vc4f8/va=2,7 2006.224.07:50:08.23#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.224.07:50:08.23#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.224.07:50:08.23#ibcon#ireg 11 cls_cnt 2 2006.224.07:50:08.23#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.224.07:50:08.30#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.224.07:50:08.30#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.224.07:50:08.30#ibcon#enter wrdev, iclass 4, count 2 2006.224.07:50:08.30#ibcon#first serial, iclass 4, count 2 2006.224.07:50:08.30#ibcon#enter sib2, iclass 4, count 2 2006.224.07:50:08.30#ibcon#flushed, iclass 4, count 2 2006.224.07:50:08.30#ibcon#about to write, iclass 4, count 2 2006.224.07:50:08.30#ibcon#wrote, iclass 4, count 2 2006.224.07:50:08.30#ibcon#about to read 3, iclass 4, count 2 2006.224.07:50:08.31#ibcon#read 3, iclass 4, count 2 2006.224.07:50:08.31#ibcon#about to read 4, iclass 4, count 2 2006.224.07:50:08.31#ibcon#read 4, iclass 4, count 2 2006.224.07:50:08.31#ibcon#about to read 5, iclass 4, count 2 2006.224.07:50:08.31#ibcon#read 5, iclass 4, count 2 2006.224.07:50:08.31#ibcon#about to read 6, iclass 4, count 2 2006.224.07:50:08.31#ibcon#read 6, iclass 4, count 2 2006.224.07:50:08.31#ibcon#end of sib2, iclass 4, count 2 2006.224.07:50:08.31#ibcon#*mode == 0, iclass 4, count 2 2006.224.07:50:08.31#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.224.07:50:08.31#ibcon#[25=AT02-07\r\n] 2006.224.07:50:08.31#ibcon#*before write, iclass 4, count 2 2006.224.07:50:08.31#ibcon#enter sib2, iclass 4, count 2 2006.224.07:50:08.31#ibcon#flushed, iclass 4, count 2 2006.224.07:50:08.31#ibcon#about to write, iclass 4, count 2 2006.224.07:50:08.31#ibcon#wrote, iclass 4, count 2 2006.224.07:50:08.31#ibcon#about to read 3, iclass 4, count 2 2006.224.07:50:08.34#ibcon#read 3, iclass 4, count 2 2006.224.07:50:08.34#ibcon#about to read 4, iclass 4, count 2 2006.224.07:50:08.34#ibcon#read 4, iclass 4, count 2 2006.224.07:50:08.34#ibcon#about to read 5, iclass 4, count 2 2006.224.07:50:08.34#ibcon#read 5, iclass 4, count 2 2006.224.07:50:08.34#ibcon#about to read 6, iclass 4, count 2 2006.224.07:50:08.34#ibcon#read 6, iclass 4, count 2 2006.224.07:50:08.34#ibcon#end of sib2, iclass 4, count 2 2006.224.07:50:08.34#ibcon#*after write, iclass 4, count 2 2006.224.07:50:08.34#ibcon#*before return 0, iclass 4, count 2 2006.224.07:50:08.34#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.224.07:50:08.34#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.224.07:50:08.34#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.224.07:50:08.34#ibcon#ireg 7 cls_cnt 0 2006.224.07:50:08.34#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.224.07:50:08.46#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.224.07:50:08.46#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.224.07:50:08.46#ibcon#enter wrdev, iclass 4, count 0 2006.224.07:50:08.46#ibcon#first serial, iclass 4, count 0 2006.224.07:50:08.46#ibcon#enter sib2, iclass 4, count 0 2006.224.07:50:08.46#ibcon#flushed, iclass 4, count 0 2006.224.07:50:08.46#ibcon#about to write, iclass 4, count 0 2006.224.07:50:08.46#ibcon#wrote, iclass 4, count 0 2006.224.07:50:08.46#ibcon#about to read 3, iclass 4, count 0 2006.224.07:50:08.48#ibcon#read 3, iclass 4, count 0 2006.224.07:50:08.48#ibcon#about to read 4, iclass 4, count 0 2006.224.07:50:08.48#ibcon#read 4, iclass 4, count 0 2006.224.07:50:08.48#ibcon#about to read 5, iclass 4, count 0 2006.224.07:50:08.48#ibcon#read 5, iclass 4, count 0 2006.224.07:50:08.48#ibcon#about to read 6, iclass 4, count 0 2006.224.07:50:08.48#ibcon#read 6, iclass 4, count 0 2006.224.07:50:08.48#ibcon#end of sib2, iclass 4, count 0 2006.224.07:50:08.48#ibcon#*mode == 0, iclass 4, count 0 2006.224.07:50:08.48#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.224.07:50:08.48#ibcon#[25=USB\r\n] 2006.224.07:50:08.48#ibcon#*before write, iclass 4, count 0 2006.224.07:50:08.48#ibcon#enter sib2, iclass 4, count 0 2006.224.07:50:08.48#ibcon#flushed, iclass 4, count 0 2006.224.07:50:08.48#ibcon#about to write, iclass 4, count 0 2006.224.07:50:08.48#ibcon#wrote, iclass 4, count 0 2006.224.07:50:08.48#ibcon#about to read 3, iclass 4, count 0 2006.224.07:50:08.51#ibcon#read 3, iclass 4, count 0 2006.224.07:50:08.51#ibcon#about to read 4, iclass 4, count 0 2006.224.07:50:08.51#ibcon#read 4, iclass 4, count 0 2006.224.07:50:08.51#ibcon#about to read 5, iclass 4, count 0 2006.224.07:50:08.51#ibcon#read 5, iclass 4, count 0 2006.224.07:50:08.51#ibcon#about to read 6, iclass 4, count 0 2006.224.07:50:08.51#ibcon#read 6, iclass 4, count 0 2006.224.07:50:08.51#ibcon#end of sib2, iclass 4, count 0 2006.224.07:50:08.51#ibcon#*after write, iclass 4, count 0 2006.224.07:50:08.51#ibcon#*before return 0, iclass 4, count 0 2006.224.07:50:08.51#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.224.07:50:08.51#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.224.07:50:08.51#ibcon#about to clear, iclass 4 cls_cnt 0 2006.224.07:50:08.51#ibcon#cleared, iclass 4 cls_cnt 0 2006.224.07:50:08.51$vc4f8/valo=3,672.99 2006.224.07:50:08.51#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.224.07:50:08.51#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.224.07:50:08.51#ibcon#ireg 17 cls_cnt 0 2006.224.07:50:08.51#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.224.07:50:08.51#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.224.07:50:08.51#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.224.07:50:08.51#ibcon#enter wrdev, iclass 6, count 0 2006.224.07:50:08.51#ibcon#first serial, iclass 6, count 0 2006.224.07:50:08.51#ibcon#enter sib2, iclass 6, count 0 2006.224.07:50:08.51#ibcon#flushed, iclass 6, count 0 2006.224.07:50:08.51#ibcon#about to write, iclass 6, count 0 2006.224.07:50:08.51#ibcon#wrote, iclass 6, count 0 2006.224.07:50:08.51#ibcon#about to read 3, iclass 6, count 0 2006.224.07:50:08.53#ibcon#read 3, iclass 6, count 0 2006.224.07:50:08.53#ibcon#about to read 4, iclass 6, count 0 2006.224.07:50:08.53#ibcon#read 4, iclass 6, count 0 2006.224.07:50:08.53#ibcon#about to read 5, iclass 6, count 0 2006.224.07:50:08.53#ibcon#read 5, iclass 6, count 0 2006.224.07:50:08.53#ibcon#about to read 6, iclass 6, count 0 2006.224.07:50:08.53#ibcon#read 6, iclass 6, count 0 2006.224.07:50:08.53#ibcon#end of sib2, iclass 6, count 0 2006.224.07:50:08.53#ibcon#*mode == 0, iclass 6, count 0 2006.224.07:50:08.53#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.224.07:50:08.53#ibcon#[26=FRQ=03,672.99\r\n] 2006.224.07:50:08.53#ibcon#*before write, iclass 6, count 0 2006.224.07:50:08.53#ibcon#enter sib2, iclass 6, count 0 2006.224.07:50:08.53#ibcon#flushed, iclass 6, count 0 2006.224.07:50:08.53#ibcon#about to write, iclass 6, count 0 2006.224.07:50:08.53#ibcon#wrote, iclass 6, count 0 2006.224.07:50:08.53#ibcon#about to read 3, iclass 6, count 0 2006.224.07:50:08.57#ibcon#read 3, iclass 6, count 0 2006.224.07:50:08.57#ibcon#about to read 4, iclass 6, count 0 2006.224.07:50:08.57#ibcon#read 4, iclass 6, count 0 2006.224.07:50:08.57#ibcon#about to read 5, iclass 6, count 0 2006.224.07:50:08.57#ibcon#read 5, iclass 6, count 0 2006.224.07:50:08.57#ibcon#about to read 6, iclass 6, count 0 2006.224.07:50:08.57#ibcon#read 6, iclass 6, count 0 2006.224.07:50:08.57#ibcon#end of sib2, iclass 6, count 0 2006.224.07:50:08.57#ibcon#*after write, iclass 6, count 0 2006.224.07:50:08.57#ibcon#*before return 0, iclass 6, count 0 2006.224.07:50:08.57#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.224.07:50:08.57#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.224.07:50:08.57#ibcon#about to clear, iclass 6 cls_cnt 0 2006.224.07:50:08.57#ibcon#cleared, iclass 6 cls_cnt 0 2006.224.07:50:08.57$vc4f8/va=3,6 2006.224.07:50:08.57#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.224.07:50:08.57#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.224.07:50:08.57#ibcon#ireg 11 cls_cnt 2 2006.224.07:50:08.57#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.224.07:50:08.64#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.224.07:50:08.64#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.224.07:50:08.64#ibcon#enter wrdev, iclass 10, count 2 2006.224.07:50:08.64#ibcon#first serial, iclass 10, count 2 2006.224.07:50:08.64#ibcon#enter sib2, iclass 10, count 2 2006.224.07:50:08.64#ibcon#flushed, iclass 10, count 2 2006.224.07:50:08.64#ibcon#about to write, iclass 10, count 2 2006.224.07:50:08.64#ibcon#wrote, iclass 10, count 2 2006.224.07:50:08.64#ibcon#about to read 3, iclass 10, count 2 2006.224.07:50:08.65#ibcon#read 3, iclass 10, count 2 2006.224.07:50:08.65#ibcon#about to read 4, iclass 10, count 2 2006.224.07:50:08.65#ibcon#read 4, iclass 10, count 2 2006.224.07:50:08.65#ibcon#about to read 5, iclass 10, count 2 2006.224.07:50:08.65#ibcon#read 5, iclass 10, count 2 2006.224.07:50:08.65#ibcon#about to read 6, iclass 10, count 2 2006.224.07:50:08.65#ibcon#read 6, iclass 10, count 2 2006.224.07:50:08.65#ibcon#end of sib2, iclass 10, count 2 2006.224.07:50:08.65#ibcon#*mode == 0, iclass 10, count 2 2006.224.07:50:08.65#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.224.07:50:08.65#ibcon#[25=AT03-06\r\n] 2006.224.07:50:08.65#ibcon#*before write, iclass 10, count 2 2006.224.07:50:08.65#ibcon#enter sib2, iclass 10, count 2 2006.224.07:50:08.65#ibcon#flushed, iclass 10, count 2 2006.224.07:50:08.65#ibcon#about to write, iclass 10, count 2 2006.224.07:50:08.65#ibcon#wrote, iclass 10, count 2 2006.224.07:50:08.65#ibcon#about to read 3, iclass 10, count 2 2006.224.07:50:08.68#ibcon#read 3, iclass 10, count 2 2006.224.07:50:08.68#ibcon#about to read 4, iclass 10, count 2 2006.224.07:50:08.68#ibcon#read 4, iclass 10, count 2 2006.224.07:50:08.68#ibcon#about to read 5, iclass 10, count 2 2006.224.07:50:08.68#ibcon#read 5, iclass 10, count 2 2006.224.07:50:08.68#ibcon#about to read 6, iclass 10, count 2 2006.224.07:50:08.68#ibcon#read 6, iclass 10, count 2 2006.224.07:50:08.68#ibcon#end of sib2, iclass 10, count 2 2006.224.07:50:08.68#ibcon#*after write, iclass 10, count 2 2006.224.07:50:08.68#ibcon#*before return 0, iclass 10, count 2 2006.224.07:50:08.68#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.224.07:50:08.68#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.224.07:50:08.68#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.224.07:50:08.68#ibcon#ireg 7 cls_cnt 0 2006.224.07:50:08.68#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.224.07:50:08.80#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.224.07:50:08.80#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.224.07:50:08.80#ibcon#enter wrdev, iclass 10, count 0 2006.224.07:50:08.80#ibcon#first serial, iclass 10, count 0 2006.224.07:50:08.80#ibcon#enter sib2, iclass 10, count 0 2006.224.07:50:08.80#ibcon#flushed, iclass 10, count 0 2006.224.07:50:08.80#ibcon#about to write, iclass 10, count 0 2006.224.07:50:08.80#ibcon#wrote, iclass 10, count 0 2006.224.07:50:08.80#ibcon#about to read 3, iclass 10, count 0 2006.224.07:50:08.82#ibcon#read 3, iclass 10, count 0 2006.224.07:50:08.82#ibcon#about to read 4, iclass 10, count 0 2006.224.07:50:08.82#ibcon#read 4, iclass 10, count 0 2006.224.07:50:08.82#ibcon#about to read 5, iclass 10, count 0 2006.224.07:50:08.82#ibcon#read 5, iclass 10, count 0 2006.224.07:50:08.82#ibcon#about to read 6, iclass 10, count 0 2006.224.07:50:08.82#ibcon#read 6, iclass 10, count 0 2006.224.07:50:08.82#ibcon#end of sib2, iclass 10, count 0 2006.224.07:50:08.82#ibcon#*mode == 0, iclass 10, count 0 2006.224.07:50:08.82#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.224.07:50:08.82#ibcon#[25=USB\r\n] 2006.224.07:50:08.82#ibcon#*before write, iclass 10, count 0 2006.224.07:50:08.82#ibcon#enter sib2, iclass 10, count 0 2006.224.07:50:08.82#ibcon#flushed, iclass 10, count 0 2006.224.07:50:08.82#ibcon#about to write, iclass 10, count 0 2006.224.07:50:08.82#ibcon#wrote, iclass 10, count 0 2006.224.07:50:08.82#ibcon#about to read 3, iclass 10, count 0 2006.224.07:50:08.85#ibcon#read 3, iclass 10, count 0 2006.224.07:50:08.85#ibcon#about to read 4, iclass 10, count 0 2006.224.07:50:08.85#ibcon#read 4, iclass 10, count 0 2006.224.07:50:08.85#ibcon#about to read 5, iclass 10, count 0 2006.224.07:50:08.85#ibcon#read 5, iclass 10, count 0 2006.224.07:50:08.85#ibcon#about to read 6, iclass 10, count 0 2006.224.07:50:08.85#ibcon#read 6, iclass 10, count 0 2006.224.07:50:08.85#ibcon#end of sib2, iclass 10, count 0 2006.224.07:50:08.85#ibcon#*after write, iclass 10, count 0 2006.224.07:50:08.85#ibcon#*before return 0, iclass 10, count 0 2006.224.07:50:08.85#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.224.07:50:08.85#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.224.07:50:08.85#ibcon#about to clear, iclass 10 cls_cnt 0 2006.224.07:50:08.85#ibcon#cleared, iclass 10 cls_cnt 0 2006.224.07:50:08.85$vc4f8/valo=4,832.99 2006.224.07:50:08.85#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.224.07:50:08.85#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.224.07:50:08.85#ibcon#ireg 17 cls_cnt 0 2006.224.07:50:08.85#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.224.07:50:08.85#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.224.07:50:08.85#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.224.07:50:08.85#ibcon#enter wrdev, iclass 12, count 0 2006.224.07:50:08.85#ibcon#first serial, iclass 12, count 0 2006.224.07:50:08.85#ibcon#enter sib2, iclass 12, count 0 2006.224.07:50:08.85#ibcon#flushed, iclass 12, count 0 2006.224.07:50:08.85#ibcon#about to write, iclass 12, count 0 2006.224.07:50:08.85#ibcon#wrote, iclass 12, count 0 2006.224.07:50:08.85#ibcon#about to read 3, iclass 12, count 0 2006.224.07:50:08.87#ibcon#read 3, iclass 12, count 0 2006.224.07:50:08.87#ibcon#about to read 4, iclass 12, count 0 2006.224.07:50:08.87#ibcon#read 4, iclass 12, count 0 2006.224.07:50:08.87#ibcon#about to read 5, iclass 12, count 0 2006.224.07:50:08.87#ibcon#read 5, iclass 12, count 0 2006.224.07:50:08.87#ibcon#about to read 6, iclass 12, count 0 2006.224.07:50:08.87#ibcon#read 6, iclass 12, count 0 2006.224.07:50:08.87#ibcon#end of sib2, iclass 12, count 0 2006.224.07:50:08.87#ibcon#*mode == 0, iclass 12, count 0 2006.224.07:50:08.87#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.224.07:50:08.87#ibcon#[26=FRQ=04,832.99\r\n] 2006.224.07:50:08.87#ibcon#*before write, iclass 12, count 0 2006.224.07:50:08.87#ibcon#enter sib2, iclass 12, count 0 2006.224.07:50:08.87#ibcon#flushed, iclass 12, count 0 2006.224.07:50:08.87#ibcon#about to write, iclass 12, count 0 2006.224.07:50:08.87#ibcon#wrote, iclass 12, count 0 2006.224.07:50:08.87#ibcon#about to read 3, iclass 12, count 0 2006.224.07:50:08.91#ibcon#read 3, iclass 12, count 0 2006.224.07:50:08.91#ibcon#about to read 4, iclass 12, count 0 2006.224.07:50:08.91#ibcon#read 4, iclass 12, count 0 2006.224.07:50:08.91#ibcon#about to read 5, iclass 12, count 0 2006.224.07:50:08.91#ibcon#read 5, iclass 12, count 0 2006.224.07:50:08.91#ibcon#about to read 6, iclass 12, count 0 2006.224.07:50:08.91#ibcon#read 6, iclass 12, count 0 2006.224.07:50:08.91#ibcon#end of sib2, iclass 12, count 0 2006.224.07:50:08.91#ibcon#*after write, iclass 12, count 0 2006.224.07:50:08.91#ibcon#*before return 0, iclass 12, count 0 2006.224.07:50:08.91#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.224.07:50:08.91#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.224.07:50:08.91#ibcon#about to clear, iclass 12 cls_cnt 0 2006.224.07:50:08.91#ibcon#cleared, iclass 12 cls_cnt 0 2006.224.07:50:08.91$vc4f8/va=4,7 2006.224.07:50:08.91#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.224.07:50:08.91#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.224.07:50:08.91#ibcon#ireg 11 cls_cnt 2 2006.224.07:50:08.91#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.224.07:50:08.97#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.224.07:50:08.97#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.224.07:50:08.97#ibcon#enter wrdev, iclass 14, count 2 2006.224.07:50:08.97#ibcon#first serial, iclass 14, count 2 2006.224.07:50:08.97#ibcon#enter sib2, iclass 14, count 2 2006.224.07:50:08.97#ibcon#flushed, iclass 14, count 2 2006.224.07:50:08.97#ibcon#about to write, iclass 14, count 2 2006.224.07:50:08.97#ibcon#wrote, iclass 14, count 2 2006.224.07:50:08.97#ibcon#about to read 3, iclass 14, count 2 2006.224.07:50:08.99#ibcon#read 3, iclass 14, count 2 2006.224.07:50:08.99#ibcon#about to read 4, iclass 14, count 2 2006.224.07:50:08.99#ibcon#read 4, iclass 14, count 2 2006.224.07:50:08.99#ibcon#about to read 5, iclass 14, count 2 2006.224.07:50:08.99#ibcon#read 5, iclass 14, count 2 2006.224.07:50:08.99#ibcon#about to read 6, iclass 14, count 2 2006.224.07:50:08.99#ibcon#read 6, iclass 14, count 2 2006.224.07:50:08.99#ibcon#end of sib2, iclass 14, count 2 2006.224.07:50:08.99#ibcon#*mode == 0, iclass 14, count 2 2006.224.07:50:08.99#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.224.07:50:08.99#ibcon#[25=AT04-07\r\n] 2006.224.07:50:08.99#ibcon#*before write, iclass 14, count 2 2006.224.07:50:08.99#ibcon#enter sib2, iclass 14, count 2 2006.224.07:50:08.99#ibcon#flushed, iclass 14, count 2 2006.224.07:50:08.99#ibcon#about to write, iclass 14, count 2 2006.224.07:50:08.99#ibcon#wrote, iclass 14, count 2 2006.224.07:50:08.99#ibcon#about to read 3, iclass 14, count 2 2006.224.07:50:09.02#ibcon#read 3, iclass 14, count 2 2006.224.07:50:09.02#ibcon#about to read 4, iclass 14, count 2 2006.224.07:50:09.02#ibcon#read 4, iclass 14, count 2 2006.224.07:50:09.02#ibcon#about to read 5, iclass 14, count 2 2006.224.07:50:09.02#ibcon#read 5, iclass 14, count 2 2006.224.07:50:09.02#ibcon#about to read 6, iclass 14, count 2 2006.224.07:50:09.02#ibcon#read 6, iclass 14, count 2 2006.224.07:50:09.02#ibcon#end of sib2, iclass 14, count 2 2006.224.07:50:09.02#ibcon#*after write, iclass 14, count 2 2006.224.07:50:09.02#ibcon#*before return 0, iclass 14, count 2 2006.224.07:50:09.02#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.224.07:50:09.02#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.224.07:50:09.02#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.224.07:50:09.02#ibcon#ireg 7 cls_cnt 0 2006.224.07:50:09.02#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.224.07:50:09.14#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.224.07:50:09.14#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.224.07:50:09.14#ibcon#enter wrdev, iclass 14, count 0 2006.224.07:50:09.14#ibcon#first serial, iclass 14, count 0 2006.224.07:50:09.14#ibcon#enter sib2, iclass 14, count 0 2006.224.07:50:09.14#ibcon#flushed, iclass 14, count 0 2006.224.07:50:09.14#ibcon#about to write, iclass 14, count 0 2006.224.07:50:09.14#ibcon#wrote, iclass 14, count 0 2006.224.07:50:09.14#ibcon#about to read 3, iclass 14, count 0 2006.224.07:50:09.16#ibcon#read 3, iclass 14, count 0 2006.224.07:50:09.16#ibcon#about to read 4, iclass 14, count 0 2006.224.07:50:09.16#ibcon#read 4, iclass 14, count 0 2006.224.07:50:09.16#ibcon#about to read 5, iclass 14, count 0 2006.224.07:50:09.16#ibcon#read 5, iclass 14, count 0 2006.224.07:50:09.16#ibcon#about to read 6, iclass 14, count 0 2006.224.07:50:09.16#ibcon#read 6, iclass 14, count 0 2006.224.07:50:09.16#ibcon#end of sib2, iclass 14, count 0 2006.224.07:50:09.16#ibcon#*mode == 0, iclass 14, count 0 2006.224.07:50:09.16#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.224.07:50:09.16#ibcon#[25=USB\r\n] 2006.224.07:50:09.16#ibcon#*before write, iclass 14, count 0 2006.224.07:50:09.16#ibcon#enter sib2, iclass 14, count 0 2006.224.07:50:09.16#ibcon#flushed, iclass 14, count 0 2006.224.07:50:09.16#ibcon#about to write, iclass 14, count 0 2006.224.07:50:09.16#ibcon#wrote, iclass 14, count 0 2006.224.07:50:09.16#ibcon#about to read 3, iclass 14, count 0 2006.224.07:50:09.19#ibcon#read 3, iclass 14, count 0 2006.224.07:50:09.19#ibcon#about to read 4, iclass 14, count 0 2006.224.07:50:09.19#ibcon#read 4, iclass 14, count 0 2006.224.07:50:09.19#ibcon#about to read 5, iclass 14, count 0 2006.224.07:50:09.19#ibcon#read 5, iclass 14, count 0 2006.224.07:50:09.19#ibcon#about to read 6, iclass 14, count 0 2006.224.07:50:09.19#ibcon#read 6, iclass 14, count 0 2006.224.07:50:09.19#ibcon#end of sib2, iclass 14, count 0 2006.224.07:50:09.19#ibcon#*after write, iclass 14, count 0 2006.224.07:50:09.19#ibcon#*before return 0, iclass 14, count 0 2006.224.07:50:09.19#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.224.07:50:09.19#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.224.07:50:09.19#ibcon#about to clear, iclass 14 cls_cnt 0 2006.224.07:50:09.19#ibcon#cleared, iclass 14 cls_cnt 0 2006.224.07:50:09.19$vc4f8/valo=5,652.99 2006.224.07:50:09.19#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.224.07:50:09.19#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.224.07:50:09.19#ibcon#ireg 17 cls_cnt 0 2006.224.07:50:09.19#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.224.07:50:09.19#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.224.07:50:09.19#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.224.07:50:09.19#ibcon#enter wrdev, iclass 16, count 0 2006.224.07:50:09.19#ibcon#first serial, iclass 16, count 0 2006.224.07:50:09.19#ibcon#enter sib2, iclass 16, count 0 2006.224.07:50:09.19#ibcon#flushed, iclass 16, count 0 2006.224.07:50:09.19#ibcon#about to write, iclass 16, count 0 2006.224.07:50:09.19#ibcon#wrote, iclass 16, count 0 2006.224.07:50:09.19#ibcon#about to read 3, iclass 16, count 0 2006.224.07:50:09.21#ibcon#read 3, iclass 16, count 0 2006.224.07:50:09.21#ibcon#about to read 4, iclass 16, count 0 2006.224.07:50:09.21#ibcon#read 4, iclass 16, count 0 2006.224.07:50:09.21#ibcon#about to read 5, iclass 16, count 0 2006.224.07:50:09.21#ibcon#read 5, iclass 16, count 0 2006.224.07:50:09.21#ibcon#about to read 6, iclass 16, count 0 2006.224.07:50:09.21#ibcon#read 6, iclass 16, count 0 2006.224.07:50:09.21#ibcon#end of sib2, iclass 16, count 0 2006.224.07:50:09.21#ibcon#*mode == 0, iclass 16, count 0 2006.224.07:50:09.21#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.224.07:50:09.21#ibcon#[26=FRQ=05,652.99\r\n] 2006.224.07:50:09.21#ibcon#*before write, iclass 16, count 0 2006.224.07:50:09.21#ibcon#enter sib2, iclass 16, count 0 2006.224.07:50:09.21#ibcon#flushed, iclass 16, count 0 2006.224.07:50:09.21#ibcon#about to write, iclass 16, count 0 2006.224.07:50:09.21#ibcon#wrote, iclass 16, count 0 2006.224.07:50:09.21#ibcon#about to read 3, iclass 16, count 0 2006.224.07:50:09.25#ibcon#read 3, iclass 16, count 0 2006.224.07:50:09.25#ibcon#about to read 4, iclass 16, count 0 2006.224.07:50:09.25#ibcon#read 4, iclass 16, count 0 2006.224.07:50:09.25#ibcon#about to read 5, iclass 16, count 0 2006.224.07:50:09.25#ibcon#read 5, iclass 16, count 0 2006.224.07:50:09.25#ibcon#about to read 6, iclass 16, count 0 2006.224.07:50:09.25#ibcon#read 6, iclass 16, count 0 2006.224.07:50:09.25#ibcon#end of sib2, iclass 16, count 0 2006.224.07:50:09.25#ibcon#*after write, iclass 16, count 0 2006.224.07:50:09.25#ibcon#*before return 0, iclass 16, count 0 2006.224.07:50:09.25#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.224.07:50:09.25#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.224.07:50:09.25#ibcon#about to clear, iclass 16 cls_cnt 0 2006.224.07:50:09.25#ibcon#cleared, iclass 16 cls_cnt 0 2006.224.07:50:09.25$vc4f8/va=5,7 2006.224.07:50:09.25#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.224.07:50:09.25#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.224.07:50:09.25#ibcon#ireg 11 cls_cnt 2 2006.224.07:50:09.25#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.224.07:50:09.31#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.224.07:50:09.31#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.224.07:50:09.31#ibcon#enter wrdev, iclass 18, count 2 2006.224.07:50:09.31#ibcon#first serial, iclass 18, count 2 2006.224.07:50:09.31#ibcon#enter sib2, iclass 18, count 2 2006.224.07:50:09.31#ibcon#flushed, iclass 18, count 2 2006.224.07:50:09.31#ibcon#about to write, iclass 18, count 2 2006.224.07:50:09.31#ibcon#wrote, iclass 18, count 2 2006.224.07:50:09.31#ibcon#about to read 3, iclass 18, count 2 2006.224.07:50:09.33#ibcon#read 3, iclass 18, count 2 2006.224.07:50:09.33#ibcon#about to read 4, iclass 18, count 2 2006.224.07:50:09.33#ibcon#read 4, iclass 18, count 2 2006.224.07:50:09.33#ibcon#about to read 5, iclass 18, count 2 2006.224.07:50:09.33#ibcon#read 5, iclass 18, count 2 2006.224.07:50:09.33#ibcon#about to read 6, iclass 18, count 2 2006.224.07:50:09.33#ibcon#read 6, iclass 18, count 2 2006.224.07:50:09.33#ibcon#end of sib2, iclass 18, count 2 2006.224.07:50:09.33#ibcon#*mode == 0, iclass 18, count 2 2006.224.07:50:09.33#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.224.07:50:09.33#ibcon#[25=AT05-07\r\n] 2006.224.07:50:09.33#ibcon#*before write, iclass 18, count 2 2006.224.07:50:09.33#ibcon#enter sib2, iclass 18, count 2 2006.224.07:50:09.33#ibcon#flushed, iclass 18, count 2 2006.224.07:50:09.33#ibcon#about to write, iclass 18, count 2 2006.224.07:50:09.33#ibcon#wrote, iclass 18, count 2 2006.224.07:50:09.33#ibcon#about to read 3, iclass 18, count 2 2006.224.07:50:09.36#ibcon#read 3, iclass 18, count 2 2006.224.07:50:09.36#ibcon#about to read 4, iclass 18, count 2 2006.224.07:50:09.36#ibcon#read 4, iclass 18, count 2 2006.224.07:50:09.36#ibcon#about to read 5, iclass 18, count 2 2006.224.07:50:09.36#ibcon#read 5, iclass 18, count 2 2006.224.07:50:09.36#ibcon#about to read 6, iclass 18, count 2 2006.224.07:50:09.36#ibcon#read 6, iclass 18, count 2 2006.224.07:50:09.36#ibcon#end of sib2, iclass 18, count 2 2006.224.07:50:09.36#ibcon#*after write, iclass 18, count 2 2006.224.07:50:09.36#ibcon#*before return 0, iclass 18, count 2 2006.224.07:50:09.36#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.224.07:50:09.36#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.224.07:50:09.36#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.224.07:50:09.36#ibcon#ireg 7 cls_cnt 0 2006.224.07:50:09.36#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.224.07:50:09.48#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.224.07:50:09.48#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.224.07:50:09.48#ibcon#enter wrdev, iclass 18, count 0 2006.224.07:50:09.48#ibcon#first serial, iclass 18, count 0 2006.224.07:50:09.48#ibcon#enter sib2, iclass 18, count 0 2006.224.07:50:09.48#ibcon#flushed, iclass 18, count 0 2006.224.07:50:09.48#ibcon#about to write, iclass 18, count 0 2006.224.07:50:09.48#ibcon#wrote, iclass 18, count 0 2006.224.07:50:09.48#ibcon#about to read 3, iclass 18, count 0 2006.224.07:50:09.50#ibcon#read 3, iclass 18, count 0 2006.224.07:50:09.50#ibcon#about to read 4, iclass 18, count 0 2006.224.07:50:09.50#ibcon#read 4, iclass 18, count 0 2006.224.07:50:09.50#ibcon#about to read 5, iclass 18, count 0 2006.224.07:50:09.50#ibcon#read 5, iclass 18, count 0 2006.224.07:50:09.50#ibcon#about to read 6, iclass 18, count 0 2006.224.07:50:09.50#ibcon#read 6, iclass 18, count 0 2006.224.07:50:09.50#ibcon#end of sib2, iclass 18, count 0 2006.224.07:50:09.50#ibcon#*mode == 0, iclass 18, count 0 2006.224.07:50:09.50#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.224.07:50:09.50#ibcon#[25=USB\r\n] 2006.224.07:50:09.50#ibcon#*before write, iclass 18, count 0 2006.224.07:50:09.50#ibcon#enter sib2, iclass 18, count 0 2006.224.07:50:09.50#ibcon#flushed, iclass 18, count 0 2006.224.07:50:09.50#ibcon#about to write, iclass 18, count 0 2006.224.07:50:09.50#ibcon#wrote, iclass 18, count 0 2006.224.07:50:09.50#ibcon#about to read 3, iclass 18, count 0 2006.224.07:50:09.53#ibcon#read 3, iclass 18, count 0 2006.224.07:50:09.53#ibcon#about to read 4, iclass 18, count 0 2006.224.07:50:09.53#ibcon#read 4, iclass 18, count 0 2006.224.07:50:09.53#ibcon#about to read 5, iclass 18, count 0 2006.224.07:50:09.53#ibcon#read 5, iclass 18, count 0 2006.224.07:50:09.53#ibcon#about to read 6, iclass 18, count 0 2006.224.07:50:09.53#ibcon#read 6, iclass 18, count 0 2006.224.07:50:09.53#ibcon#end of sib2, iclass 18, count 0 2006.224.07:50:09.53#ibcon#*after write, iclass 18, count 0 2006.224.07:50:09.53#ibcon#*before return 0, iclass 18, count 0 2006.224.07:50:09.53#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.224.07:50:09.53#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.224.07:50:09.53#ibcon#about to clear, iclass 18 cls_cnt 0 2006.224.07:50:09.53#ibcon#cleared, iclass 18 cls_cnt 0 2006.224.07:50:09.53$vc4f8/valo=6,772.99 2006.224.07:50:09.53#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.224.07:50:09.53#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.224.07:50:09.53#ibcon#ireg 17 cls_cnt 0 2006.224.07:50:09.53#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.224.07:50:09.53#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.224.07:50:09.53#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.224.07:50:09.53#ibcon#enter wrdev, iclass 20, count 0 2006.224.07:50:09.53#ibcon#first serial, iclass 20, count 0 2006.224.07:50:09.53#ibcon#enter sib2, iclass 20, count 0 2006.224.07:50:09.53#ibcon#flushed, iclass 20, count 0 2006.224.07:50:09.53#ibcon#about to write, iclass 20, count 0 2006.224.07:50:09.53#ibcon#wrote, iclass 20, count 0 2006.224.07:50:09.53#ibcon#about to read 3, iclass 20, count 0 2006.224.07:50:09.55#ibcon#read 3, iclass 20, count 0 2006.224.07:50:09.55#ibcon#about to read 4, iclass 20, count 0 2006.224.07:50:09.55#ibcon#read 4, iclass 20, count 0 2006.224.07:50:09.55#ibcon#about to read 5, iclass 20, count 0 2006.224.07:50:09.55#ibcon#read 5, iclass 20, count 0 2006.224.07:50:09.55#ibcon#about to read 6, iclass 20, count 0 2006.224.07:50:09.55#ibcon#read 6, iclass 20, count 0 2006.224.07:50:09.55#ibcon#end of sib2, iclass 20, count 0 2006.224.07:50:09.55#ibcon#*mode == 0, iclass 20, count 0 2006.224.07:50:09.55#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.224.07:50:09.55#ibcon#[26=FRQ=06,772.99\r\n] 2006.224.07:50:09.55#ibcon#*before write, iclass 20, count 0 2006.224.07:50:09.55#ibcon#enter sib2, iclass 20, count 0 2006.224.07:50:09.55#ibcon#flushed, iclass 20, count 0 2006.224.07:50:09.55#ibcon#about to write, iclass 20, count 0 2006.224.07:50:09.55#ibcon#wrote, iclass 20, count 0 2006.224.07:50:09.55#ibcon#about to read 3, iclass 20, count 0 2006.224.07:50:09.59#ibcon#read 3, iclass 20, count 0 2006.224.07:50:09.59#ibcon#about to read 4, iclass 20, count 0 2006.224.07:50:09.59#ibcon#read 4, iclass 20, count 0 2006.224.07:50:09.59#ibcon#about to read 5, iclass 20, count 0 2006.224.07:50:09.59#ibcon#read 5, iclass 20, count 0 2006.224.07:50:09.59#ibcon#about to read 6, iclass 20, count 0 2006.224.07:50:09.59#ibcon#read 6, iclass 20, count 0 2006.224.07:50:09.59#ibcon#end of sib2, iclass 20, count 0 2006.224.07:50:09.59#ibcon#*after write, iclass 20, count 0 2006.224.07:50:09.59#ibcon#*before return 0, iclass 20, count 0 2006.224.07:50:09.59#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.224.07:50:09.59#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.224.07:50:09.59#ibcon#about to clear, iclass 20 cls_cnt 0 2006.224.07:50:09.59#ibcon#cleared, iclass 20 cls_cnt 0 2006.224.07:50:09.59$vc4f8/va=6,6 2006.224.07:50:09.59#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.224.07:50:09.59#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.224.07:50:09.59#ibcon#ireg 11 cls_cnt 2 2006.224.07:50:09.59#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.224.07:50:09.66#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.224.07:50:09.66#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.224.07:50:09.66#ibcon#enter wrdev, iclass 22, count 2 2006.224.07:50:09.66#ibcon#first serial, iclass 22, count 2 2006.224.07:50:09.66#ibcon#enter sib2, iclass 22, count 2 2006.224.07:50:09.66#ibcon#flushed, iclass 22, count 2 2006.224.07:50:09.66#ibcon#about to write, iclass 22, count 2 2006.224.07:50:09.66#ibcon#wrote, iclass 22, count 2 2006.224.07:50:09.66#ibcon#about to read 3, iclass 22, count 2 2006.224.07:50:09.67#ibcon#read 3, iclass 22, count 2 2006.224.07:50:09.67#ibcon#about to read 4, iclass 22, count 2 2006.224.07:50:09.67#ibcon#read 4, iclass 22, count 2 2006.224.07:50:09.67#ibcon#about to read 5, iclass 22, count 2 2006.224.07:50:09.67#ibcon#read 5, iclass 22, count 2 2006.224.07:50:09.67#ibcon#about to read 6, iclass 22, count 2 2006.224.07:50:09.67#ibcon#read 6, iclass 22, count 2 2006.224.07:50:09.67#ibcon#end of sib2, iclass 22, count 2 2006.224.07:50:09.67#ibcon#*mode == 0, iclass 22, count 2 2006.224.07:50:09.67#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.224.07:50:09.67#ibcon#[25=AT06-06\r\n] 2006.224.07:50:09.67#ibcon#*before write, iclass 22, count 2 2006.224.07:50:09.67#ibcon#enter sib2, iclass 22, count 2 2006.224.07:50:09.67#ibcon#flushed, iclass 22, count 2 2006.224.07:50:09.67#ibcon#about to write, iclass 22, count 2 2006.224.07:50:09.67#ibcon#wrote, iclass 22, count 2 2006.224.07:50:09.67#ibcon#about to read 3, iclass 22, count 2 2006.224.07:50:09.70#ibcon#read 3, iclass 22, count 2 2006.224.07:50:09.70#ibcon#about to read 4, iclass 22, count 2 2006.224.07:50:09.70#ibcon#read 4, iclass 22, count 2 2006.224.07:50:09.70#ibcon#about to read 5, iclass 22, count 2 2006.224.07:50:09.70#ibcon#read 5, iclass 22, count 2 2006.224.07:50:09.70#ibcon#about to read 6, iclass 22, count 2 2006.224.07:50:09.70#ibcon#read 6, iclass 22, count 2 2006.224.07:50:09.70#ibcon#end of sib2, iclass 22, count 2 2006.224.07:50:09.70#ibcon#*after write, iclass 22, count 2 2006.224.07:50:09.70#ibcon#*before return 0, iclass 22, count 2 2006.224.07:50:09.70#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.224.07:50:09.70#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.224.07:50:09.70#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.224.07:50:09.70#ibcon#ireg 7 cls_cnt 0 2006.224.07:50:09.70#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.224.07:50:09.82#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.224.07:50:09.82#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.224.07:50:09.82#ibcon#enter wrdev, iclass 22, count 0 2006.224.07:50:09.82#ibcon#first serial, iclass 22, count 0 2006.224.07:50:09.82#ibcon#enter sib2, iclass 22, count 0 2006.224.07:50:09.82#ibcon#flushed, iclass 22, count 0 2006.224.07:50:09.82#ibcon#about to write, iclass 22, count 0 2006.224.07:50:09.82#ibcon#wrote, iclass 22, count 0 2006.224.07:50:09.82#ibcon#about to read 3, iclass 22, count 0 2006.224.07:50:09.84#ibcon#read 3, iclass 22, count 0 2006.224.07:50:09.84#ibcon#about to read 4, iclass 22, count 0 2006.224.07:50:09.84#ibcon#read 4, iclass 22, count 0 2006.224.07:50:09.84#ibcon#about to read 5, iclass 22, count 0 2006.224.07:50:09.84#ibcon#read 5, iclass 22, count 0 2006.224.07:50:09.84#ibcon#about to read 6, iclass 22, count 0 2006.224.07:50:09.84#ibcon#read 6, iclass 22, count 0 2006.224.07:50:09.84#ibcon#end of sib2, iclass 22, count 0 2006.224.07:50:09.84#ibcon#*mode == 0, iclass 22, count 0 2006.224.07:50:09.84#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.224.07:50:09.84#ibcon#[25=USB\r\n] 2006.224.07:50:09.84#ibcon#*before write, iclass 22, count 0 2006.224.07:50:09.84#ibcon#enter sib2, iclass 22, count 0 2006.224.07:50:09.84#ibcon#flushed, iclass 22, count 0 2006.224.07:50:09.84#ibcon#about to write, iclass 22, count 0 2006.224.07:50:09.84#ibcon#wrote, iclass 22, count 0 2006.224.07:50:09.84#ibcon#about to read 3, iclass 22, count 0 2006.224.07:50:09.87#ibcon#read 3, iclass 22, count 0 2006.224.07:50:09.87#ibcon#about to read 4, iclass 22, count 0 2006.224.07:50:09.87#ibcon#read 4, iclass 22, count 0 2006.224.07:50:09.87#ibcon#about to read 5, iclass 22, count 0 2006.224.07:50:09.87#ibcon#read 5, iclass 22, count 0 2006.224.07:50:09.87#ibcon#about to read 6, iclass 22, count 0 2006.224.07:50:09.87#ibcon#read 6, iclass 22, count 0 2006.224.07:50:09.87#ibcon#end of sib2, iclass 22, count 0 2006.224.07:50:09.87#ibcon#*after write, iclass 22, count 0 2006.224.07:50:09.87#ibcon#*before return 0, iclass 22, count 0 2006.224.07:50:09.87#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.224.07:50:09.87#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.224.07:50:09.87#ibcon#about to clear, iclass 22 cls_cnt 0 2006.224.07:50:09.87#ibcon#cleared, iclass 22 cls_cnt 0 2006.224.07:50:09.87$vc4f8/valo=7,832.99 2006.224.07:50:09.87#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.224.07:50:09.87#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.224.07:50:09.87#ibcon#ireg 17 cls_cnt 0 2006.224.07:50:09.87#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.224.07:50:09.87#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.224.07:50:09.87#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.224.07:50:09.87#ibcon#enter wrdev, iclass 24, count 0 2006.224.07:50:09.87#ibcon#first serial, iclass 24, count 0 2006.224.07:50:09.87#ibcon#enter sib2, iclass 24, count 0 2006.224.07:50:09.87#ibcon#flushed, iclass 24, count 0 2006.224.07:50:09.87#ibcon#about to write, iclass 24, count 0 2006.224.07:50:09.87#ibcon#wrote, iclass 24, count 0 2006.224.07:50:09.87#ibcon#about to read 3, iclass 24, count 0 2006.224.07:50:09.89#ibcon#read 3, iclass 24, count 0 2006.224.07:50:09.89#ibcon#about to read 4, iclass 24, count 0 2006.224.07:50:09.89#ibcon#read 4, iclass 24, count 0 2006.224.07:50:09.89#ibcon#about to read 5, iclass 24, count 0 2006.224.07:50:09.89#ibcon#read 5, iclass 24, count 0 2006.224.07:50:09.89#ibcon#about to read 6, iclass 24, count 0 2006.224.07:50:09.89#ibcon#read 6, iclass 24, count 0 2006.224.07:50:09.89#ibcon#end of sib2, iclass 24, count 0 2006.224.07:50:09.89#ibcon#*mode == 0, iclass 24, count 0 2006.224.07:50:09.89#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.224.07:50:09.89#ibcon#[26=FRQ=07,832.99\r\n] 2006.224.07:50:09.89#ibcon#*before write, iclass 24, count 0 2006.224.07:50:09.89#ibcon#enter sib2, iclass 24, count 0 2006.224.07:50:09.89#ibcon#flushed, iclass 24, count 0 2006.224.07:50:09.89#ibcon#about to write, iclass 24, count 0 2006.224.07:50:09.89#ibcon#wrote, iclass 24, count 0 2006.224.07:50:09.89#ibcon#about to read 3, iclass 24, count 0 2006.224.07:50:09.93#ibcon#read 3, iclass 24, count 0 2006.224.07:50:09.93#ibcon#about to read 4, iclass 24, count 0 2006.224.07:50:09.93#ibcon#read 4, iclass 24, count 0 2006.224.07:50:09.93#ibcon#about to read 5, iclass 24, count 0 2006.224.07:50:09.93#ibcon#read 5, iclass 24, count 0 2006.224.07:50:09.93#ibcon#about to read 6, iclass 24, count 0 2006.224.07:50:09.93#ibcon#read 6, iclass 24, count 0 2006.224.07:50:09.93#ibcon#end of sib2, iclass 24, count 0 2006.224.07:50:09.93#ibcon#*after write, iclass 24, count 0 2006.224.07:50:09.93#ibcon#*before return 0, iclass 24, count 0 2006.224.07:50:09.93#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.224.07:50:09.93#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.224.07:50:09.93#ibcon#about to clear, iclass 24 cls_cnt 0 2006.224.07:50:09.93#ibcon#cleared, iclass 24 cls_cnt 0 2006.224.07:50:09.93$vc4f8/va=7,6 2006.224.07:50:09.93#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.224.07:50:09.93#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.224.07:50:09.93#ibcon#ireg 11 cls_cnt 2 2006.224.07:50:09.93#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.224.07:50:09.99#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.224.07:50:09.99#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.224.07:50:09.99#ibcon#enter wrdev, iclass 26, count 2 2006.224.07:50:09.99#ibcon#first serial, iclass 26, count 2 2006.224.07:50:09.99#ibcon#enter sib2, iclass 26, count 2 2006.224.07:50:09.99#ibcon#flushed, iclass 26, count 2 2006.224.07:50:09.99#ibcon#about to write, iclass 26, count 2 2006.224.07:50:09.99#ibcon#wrote, iclass 26, count 2 2006.224.07:50:09.99#ibcon#about to read 3, iclass 26, count 2 2006.224.07:50:10.01#ibcon#read 3, iclass 26, count 2 2006.224.07:50:10.01#ibcon#about to read 4, iclass 26, count 2 2006.224.07:50:10.01#ibcon#read 4, iclass 26, count 2 2006.224.07:50:10.01#ibcon#about to read 5, iclass 26, count 2 2006.224.07:50:10.01#ibcon#read 5, iclass 26, count 2 2006.224.07:50:10.01#ibcon#about to read 6, iclass 26, count 2 2006.224.07:50:10.01#ibcon#read 6, iclass 26, count 2 2006.224.07:50:10.01#ibcon#end of sib2, iclass 26, count 2 2006.224.07:50:10.01#ibcon#*mode == 0, iclass 26, count 2 2006.224.07:50:10.01#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.224.07:50:10.01#ibcon#[25=AT07-06\r\n] 2006.224.07:50:10.01#ibcon#*before write, iclass 26, count 2 2006.224.07:50:10.01#ibcon#enter sib2, iclass 26, count 2 2006.224.07:50:10.01#ibcon#flushed, iclass 26, count 2 2006.224.07:50:10.01#ibcon#about to write, iclass 26, count 2 2006.224.07:50:10.01#ibcon#wrote, iclass 26, count 2 2006.224.07:50:10.01#ibcon#about to read 3, iclass 26, count 2 2006.224.07:50:10.04#ibcon#read 3, iclass 26, count 2 2006.224.07:50:10.04#ibcon#about to read 4, iclass 26, count 2 2006.224.07:50:10.04#ibcon#read 4, iclass 26, count 2 2006.224.07:50:10.04#ibcon#about to read 5, iclass 26, count 2 2006.224.07:50:10.04#ibcon#read 5, iclass 26, count 2 2006.224.07:50:10.04#ibcon#about to read 6, iclass 26, count 2 2006.224.07:50:10.04#ibcon#read 6, iclass 26, count 2 2006.224.07:50:10.04#ibcon#end of sib2, iclass 26, count 2 2006.224.07:50:10.04#ibcon#*after write, iclass 26, count 2 2006.224.07:50:10.04#ibcon#*before return 0, iclass 26, count 2 2006.224.07:50:10.04#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.224.07:50:10.04#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.224.07:50:10.04#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.224.07:50:10.04#ibcon#ireg 7 cls_cnt 0 2006.224.07:50:10.04#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.224.07:50:10.16#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.224.07:50:10.16#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.224.07:50:10.16#ibcon#enter wrdev, iclass 26, count 0 2006.224.07:50:10.16#ibcon#first serial, iclass 26, count 0 2006.224.07:50:10.16#ibcon#enter sib2, iclass 26, count 0 2006.224.07:50:10.16#ibcon#flushed, iclass 26, count 0 2006.224.07:50:10.16#ibcon#about to write, iclass 26, count 0 2006.224.07:50:10.16#ibcon#wrote, iclass 26, count 0 2006.224.07:50:10.16#ibcon#about to read 3, iclass 26, count 0 2006.224.07:50:10.18#ibcon#read 3, iclass 26, count 0 2006.224.07:50:10.18#ibcon#about to read 4, iclass 26, count 0 2006.224.07:50:10.18#ibcon#read 4, iclass 26, count 0 2006.224.07:50:10.18#ibcon#about to read 5, iclass 26, count 0 2006.224.07:50:10.18#ibcon#read 5, iclass 26, count 0 2006.224.07:50:10.18#ibcon#about to read 6, iclass 26, count 0 2006.224.07:50:10.18#ibcon#read 6, iclass 26, count 0 2006.224.07:50:10.18#ibcon#end of sib2, iclass 26, count 0 2006.224.07:50:10.18#ibcon#*mode == 0, iclass 26, count 0 2006.224.07:50:10.18#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.224.07:50:10.18#ibcon#[25=USB\r\n] 2006.224.07:50:10.18#ibcon#*before write, iclass 26, count 0 2006.224.07:50:10.18#ibcon#enter sib2, iclass 26, count 0 2006.224.07:50:10.18#ibcon#flushed, iclass 26, count 0 2006.224.07:50:10.18#ibcon#about to write, iclass 26, count 0 2006.224.07:50:10.18#ibcon#wrote, iclass 26, count 0 2006.224.07:50:10.18#ibcon#about to read 3, iclass 26, count 0 2006.224.07:50:10.21#ibcon#read 3, iclass 26, count 0 2006.224.07:50:10.21#ibcon#about to read 4, iclass 26, count 0 2006.224.07:50:10.21#ibcon#read 4, iclass 26, count 0 2006.224.07:50:10.21#ibcon#about to read 5, iclass 26, count 0 2006.224.07:50:10.21#ibcon#read 5, iclass 26, count 0 2006.224.07:50:10.21#ibcon#about to read 6, iclass 26, count 0 2006.224.07:50:10.21#ibcon#read 6, iclass 26, count 0 2006.224.07:50:10.21#ibcon#end of sib2, iclass 26, count 0 2006.224.07:50:10.21#ibcon#*after write, iclass 26, count 0 2006.224.07:50:10.21#ibcon#*before return 0, iclass 26, count 0 2006.224.07:50:10.21#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.224.07:50:10.21#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.224.07:50:10.21#ibcon#about to clear, iclass 26 cls_cnt 0 2006.224.07:50:10.21#ibcon#cleared, iclass 26 cls_cnt 0 2006.224.07:50:10.21$vc4f8/valo=8,852.99 2006.224.07:50:10.21#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.224.07:50:10.21#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.224.07:50:10.21#ibcon#ireg 17 cls_cnt 0 2006.224.07:50:10.21#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.224.07:50:10.21#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.224.07:50:10.21#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.224.07:50:10.21#ibcon#enter wrdev, iclass 28, count 0 2006.224.07:50:10.21#ibcon#first serial, iclass 28, count 0 2006.224.07:50:10.21#ibcon#enter sib2, iclass 28, count 0 2006.224.07:50:10.21#ibcon#flushed, iclass 28, count 0 2006.224.07:50:10.21#ibcon#about to write, iclass 28, count 0 2006.224.07:50:10.21#ibcon#wrote, iclass 28, count 0 2006.224.07:50:10.21#ibcon#about to read 3, iclass 28, count 0 2006.224.07:50:10.23#ibcon#read 3, iclass 28, count 0 2006.224.07:50:10.23#ibcon#about to read 4, iclass 28, count 0 2006.224.07:50:10.23#ibcon#read 4, iclass 28, count 0 2006.224.07:50:10.23#ibcon#about to read 5, iclass 28, count 0 2006.224.07:50:10.23#ibcon#read 5, iclass 28, count 0 2006.224.07:50:10.23#ibcon#about to read 6, iclass 28, count 0 2006.224.07:50:10.23#ibcon#read 6, iclass 28, count 0 2006.224.07:50:10.23#ibcon#end of sib2, iclass 28, count 0 2006.224.07:50:10.23#ibcon#*mode == 0, iclass 28, count 0 2006.224.07:50:10.23#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.224.07:50:10.23#ibcon#[26=FRQ=08,852.99\r\n] 2006.224.07:50:10.23#ibcon#*before write, iclass 28, count 0 2006.224.07:50:10.23#ibcon#enter sib2, iclass 28, count 0 2006.224.07:50:10.23#ibcon#flushed, iclass 28, count 0 2006.224.07:50:10.23#ibcon#about to write, iclass 28, count 0 2006.224.07:50:10.23#ibcon#wrote, iclass 28, count 0 2006.224.07:50:10.23#ibcon#about to read 3, iclass 28, count 0 2006.224.07:50:10.27#ibcon#read 3, iclass 28, count 0 2006.224.07:50:10.27#ibcon#about to read 4, iclass 28, count 0 2006.224.07:50:10.27#ibcon#read 4, iclass 28, count 0 2006.224.07:50:10.27#ibcon#about to read 5, iclass 28, count 0 2006.224.07:50:10.27#ibcon#read 5, iclass 28, count 0 2006.224.07:50:10.27#ibcon#about to read 6, iclass 28, count 0 2006.224.07:50:10.27#ibcon#read 6, iclass 28, count 0 2006.224.07:50:10.27#ibcon#end of sib2, iclass 28, count 0 2006.224.07:50:10.27#ibcon#*after write, iclass 28, count 0 2006.224.07:50:10.27#ibcon#*before return 0, iclass 28, count 0 2006.224.07:50:10.27#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.224.07:50:10.27#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.224.07:50:10.27#ibcon#about to clear, iclass 28 cls_cnt 0 2006.224.07:50:10.27#ibcon#cleared, iclass 28 cls_cnt 0 2006.224.07:50:10.27$vc4f8/va=8,7 2006.224.07:50:10.27#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.224.07:50:10.27#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.224.07:50:10.27#ibcon#ireg 11 cls_cnt 2 2006.224.07:50:10.27#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.224.07:50:10.33#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.224.07:50:10.33#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.224.07:50:10.33#ibcon#enter wrdev, iclass 30, count 2 2006.224.07:50:10.33#ibcon#first serial, iclass 30, count 2 2006.224.07:50:10.33#ibcon#enter sib2, iclass 30, count 2 2006.224.07:50:10.33#ibcon#flushed, iclass 30, count 2 2006.224.07:50:10.33#ibcon#about to write, iclass 30, count 2 2006.224.07:50:10.33#ibcon#wrote, iclass 30, count 2 2006.224.07:50:10.33#ibcon#about to read 3, iclass 30, count 2 2006.224.07:50:10.35#ibcon#read 3, iclass 30, count 2 2006.224.07:50:10.35#ibcon#about to read 4, iclass 30, count 2 2006.224.07:50:10.35#ibcon#read 4, iclass 30, count 2 2006.224.07:50:10.35#ibcon#about to read 5, iclass 30, count 2 2006.224.07:50:10.35#ibcon#read 5, iclass 30, count 2 2006.224.07:50:10.35#ibcon#about to read 6, iclass 30, count 2 2006.224.07:50:10.35#ibcon#read 6, iclass 30, count 2 2006.224.07:50:10.35#ibcon#end of sib2, iclass 30, count 2 2006.224.07:50:10.35#ibcon#*mode == 0, iclass 30, count 2 2006.224.07:50:10.35#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.224.07:50:10.35#ibcon#[25=AT08-07\r\n] 2006.224.07:50:10.35#ibcon#*before write, iclass 30, count 2 2006.224.07:50:10.35#ibcon#enter sib2, iclass 30, count 2 2006.224.07:50:10.35#ibcon#flushed, iclass 30, count 2 2006.224.07:50:10.35#ibcon#about to write, iclass 30, count 2 2006.224.07:50:10.35#ibcon#wrote, iclass 30, count 2 2006.224.07:50:10.35#ibcon#about to read 3, iclass 30, count 2 2006.224.07:50:10.38#ibcon#read 3, iclass 30, count 2 2006.224.07:50:10.38#ibcon#about to read 4, iclass 30, count 2 2006.224.07:50:10.38#ibcon#read 4, iclass 30, count 2 2006.224.07:50:10.38#ibcon#about to read 5, iclass 30, count 2 2006.224.07:50:10.38#ibcon#read 5, iclass 30, count 2 2006.224.07:50:10.38#ibcon#about to read 6, iclass 30, count 2 2006.224.07:50:10.38#ibcon#read 6, iclass 30, count 2 2006.224.07:50:10.38#ibcon#end of sib2, iclass 30, count 2 2006.224.07:50:10.38#ibcon#*after write, iclass 30, count 2 2006.224.07:50:10.38#ibcon#*before return 0, iclass 30, count 2 2006.224.07:50:10.38#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.224.07:50:10.38#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.224.07:50:10.38#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.224.07:50:10.38#ibcon#ireg 7 cls_cnt 0 2006.224.07:50:10.38#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.224.07:50:10.50#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.224.07:50:10.50#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.224.07:50:10.50#ibcon#enter wrdev, iclass 30, count 0 2006.224.07:50:10.50#ibcon#first serial, iclass 30, count 0 2006.224.07:50:10.50#ibcon#enter sib2, iclass 30, count 0 2006.224.07:50:10.50#ibcon#flushed, iclass 30, count 0 2006.224.07:50:10.50#ibcon#about to write, iclass 30, count 0 2006.224.07:50:10.50#ibcon#wrote, iclass 30, count 0 2006.224.07:50:10.50#ibcon#about to read 3, iclass 30, count 0 2006.224.07:50:10.52#ibcon#read 3, iclass 30, count 0 2006.224.07:50:10.52#ibcon#about to read 4, iclass 30, count 0 2006.224.07:50:10.52#ibcon#read 4, iclass 30, count 0 2006.224.07:50:10.52#ibcon#about to read 5, iclass 30, count 0 2006.224.07:50:10.52#ibcon#read 5, iclass 30, count 0 2006.224.07:50:10.52#ibcon#about to read 6, iclass 30, count 0 2006.224.07:50:10.52#ibcon#read 6, iclass 30, count 0 2006.224.07:50:10.52#ibcon#end of sib2, iclass 30, count 0 2006.224.07:50:10.52#ibcon#*mode == 0, iclass 30, count 0 2006.224.07:50:10.52#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.224.07:50:10.52#ibcon#[25=USB\r\n] 2006.224.07:50:10.52#ibcon#*before write, iclass 30, count 0 2006.224.07:50:10.52#ibcon#enter sib2, iclass 30, count 0 2006.224.07:50:10.52#ibcon#flushed, iclass 30, count 0 2006.224.07:50:10.52#ibcon#about to write, iclass 30, count 0 2006.224.07:50:10.52#ibcon#wrote, iclass 30, count 0 2006.224.07:50:10.52#ibcon#about to read 3, iclass 30, count 0 2006.224.07:50:10.55#ibcon#read 3, iclass 30, count 0 2006.224.07:50:10.55#ibcon#about to read 4, iclass 30, count 0 2006.224.07:50:10.55#ibcon#read 4, iclass 30, count 0 2006.224.07:50:10.55#ibcon#about to read 5, iclass 30, count 0 2006.224.07:50:10.55#ibcon#read 5, iclass 30, count 0 2006.224.07:50:10.55#ibcon#about to read 6, iclass 30, count 0 2006.224.07:50:10.55#ibcon#read 6, iclass 30, count 0 2006.224.07:50:10.55#ibcon#end of sib2, iclass 30, count 0 2006.224.07:50:10.55#ibcon#*after write, iclass 30, count 0 2006.224.07:50:10.55#ibcon#*before return 0, iclass 30, count 0 2006.224.07:50:10.55#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.224.07:50:10.55#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.224.07:50:10.55#ibcon#about to clear, iclass 30 cls_cnt 0 2006.224.07:50:10.55#ibcon#cleared, iclass 30 cls_cnt 0 2006.224.07:50:10.55$vc4f8/vblo=1,632.99 2006.224.07:50:10.55#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.224.07:50:10.55#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.224.07:50:10.55#ibcon#ireg 17 cls_cnt 0 2006.224.07:50:10.55#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.224.07:50:10.55#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.224.07:50:10.55#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.224.07:50:10.55#ibcon#enter wrdev, iclass 32, count 0 2006.224.07:50:10.55#ibcon#first serial, iclass 32, count 0 2006.224.07:50:10.55#ibcon#enter sib2, iclass 32, count 0 2006.224.07:50:10.55#ibcon#flushed, iclass 32, count 0 2006.224.07:50:10.55#ibcon#about to write, iclass 32, count 0 2006.224.07:50:10.55#ibcon#wrote, iclass 32, count 0 2006.224.07:50:10.55#ibcon#about to read 3, iclass 32, count 0 2006.224.07:50:10.58#ibcon#read 3, iclass 32, count 0 2006.224.07:50:10.58#ibcon#about to read 4, iclass 32, count 0 2006.224.07:50:10.58#ibcon#read 4, iclass 32, count 0 2006.224.07:50:10.58#ibcon#about to read 5, iclass 32, count 0 2006.224.07:50:10.58#ibcon#read 5, iclass 32, count 0 2006.224.07:50:10.58#ibcon#about to read 6, iclass 32, count 0 2006.224.07:50:10.58#ibcon#read 6, iclass 32, count 0 2006.224.07:50:10.58#ibcon#end of sib2, iclass 32, count 0 2006.224.07:50:10.58#ibcon#*mode == 0, iclass 32, count 0 2006.224.07:50:10.58#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.224.07:50:10.58#ibcon#[28=FRQ=01,632.99\r\n] 2006.224.07:50:10.58#ibcon#*before write, iclass 32, count 0 2006.224.07:50:10.58#ibcon#enter sib2, iclass 32, count 0 2006.224.07:50:10.58#ibcon#flushed, iclass 32, count 0 2006.224.07:50:10.58#ibcon#about to write, iclass 32, count 0 2006.224.07:50:10.58#ibcon#wrote, iclass 32, count 0 2006.224.07:50:10.58#ibcon#about to read 3, iclass 32, count 0 2006.224.07:50:10.62#ibcon#read 3, iclass 32, count 0 2006.224.07:50:10.62#ibcon#about to read 4, iclass 32, count 0 2006.224.07:50:10.62#ibcon#read 4, iclass 32, count 0 2006.224.07:50:10.62#ibcon#about to read 5, iclass 32, count 0 2006.224.07:50:10.62#ibcon#read 5, iclass 32, count 0 2006.224.07:50:10.62#ibcon#about to read 6, iclass 32, count 0 2006.224.07:50:10.62#ibcon#read 6, iclass 32, count 0 2006.224.07:50:10.62#ibcon#end of sib2, iclass 32, count 0 2006.224.07:50:10.62#ibcon#*after write, iclass 32, count 0 2006.224.07:50:10.62#ibcon#*before return 0, iclass 32, count 0 2006.224.07:50:10.62#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.224.07:50:10.62#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.224.07:50:10.62#ibcon#about to clear, iclass 32 cls_cnt 0 2006.224.07:50:10.62#ibcon#cleared, iclass 32 cls_cnt 0 2006.224.07:50:10.62$vc4f8/vb=1,4 2006.224.07:50:10.62#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.224.07:50:10.62#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.224.07:50:10.62#ibcon#ireg 11 cls_cnt 2 2006.224.07:50:10.62#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.224.07:50:10.62#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.224.07:50:10.62#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.224.07:50:10.62#ibcon#enter wrdev, iclass 34, count 2 2006.224.07:50:10.62#ibcon#first serial, iclass 34, count 2 2006.224.07:50:10.62#ibcon#enter sib2, iclass 34, count 2 2006.224.07:50:10.62#ibcon#flushed, iclass 34, count 2 2006.224.07:50:10.62#ibcon#about to write, iclass 34, count 2 2006.224.07:50:10.62#ibcon#wrote, iclass 34, count 2 2006.224.07:50:10.62#ibcon#about to read 3, iclass 34, count 2 2006.224.07:50:10.64#ibcon#read 3, iclass 34, count 2 2006.224.07:50:10.64#ibcon#about to read 4, iclass 34, count 2 2006.224.07:50:10.64#ibcon#read 4, iclass 34, count 2 2006.224.07:50:10.64#ibcon#about to read 5, iclass 34, count 2 2006.224.07:50:10.64#ibcon#read 5, iclass 34, count 2 2006.224.07:50:10.64#ibcon#about to read 6, iclass 34, count 2 2006.224.07:50:10.64#ibcon#read 6, iclass 34, count 2 2006.224.07:50:10.64#ibcon#end of sib2, iclass 34, count 2 2006.224.07:50:10.64#ibcon#*mode == 0, iclass 34, count 2 2006.224.07:50:10.64#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.224.07:50:10.64#ibcon#[27=AT01-04\r\n] 2006.224.07:50:10.64#ibcon#*before write, iclass 34, count 2 2006.224.07:50:10.64#ibcon#enter sib2, iclass 34, count 2 2006.224.07:50:10.64#ibcon#flushed, iclass 34, count 2 2006.224.07:50:10.64#ibcon#about to write, iclass 34, count 2 2006.224.07:50:10.64#ibcon#wrote, iclass 34, count 2 2006.224.07:50:10.64#ibcon#about to read 3, iclass 34, count 2 2006.224.07:50:10.67#ibcon#read 3, iclass 34, count 2 2006.224.07:50:10.67#ibcon#about to read 4, iclass 34, count 2 2006.224.07:50:10.67#ibcon#read 4, iclass 34, count 2 2006.224.07:50:10.67#ibcon#about to read 5, iclass 34, count 2 2006.224.07:50:10.67#ibcon#read 5, iclass 34, count 2 2006.224.07:50:10.67#ibcon#about to read 6, iclass 34, count 2 2006.224.07:50:10.67#ibcon#read 6, iclass 34, count 2 2006.224.07:50:10.67#ibcon#end of sib2, iclass 34, count 2 2006.224.07:50:10.67#ibcon#*after write, iclass 34, count 2 2006.224.07:50:10.67#ibcon#*before return 0, iclass 34, count 2 2006.224.07:50:10.67#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.224.07:50:10.67#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.224.07:50:10.67#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.224.07:50:10.67#ibcon#ireg 7 cls_cnt 0 2006.224.07:50:10.67#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.224.07:50:10.79#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.224.07:50:10.79#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.224.07:50:10.79#ibcon#enter wrdev, iclass 34, count 0 2006.224.07:50:10.79#ibcon#first serial, iclass 34, count 0 2006.224.07:50:10.79#ibcon#enter sib2, iclass 34, count 0 2006.224.07:50:10.79#ibcon#flushed, iclass 34, count 0 2006.224.07:50:10.79#ibcon#about to write, iclass 34, count 0 2006.224.07:50:10.79#ibcon#wrote, iclass 34, count 0 2006.224.07:50:10.79#ibcon#about to read 3, iclass 34, count 0 2006.224.07:50:10.81#ibcon#read 3, iclass 34, count 0 2006.224.07:50:10.81#ibcon#about to read 4, iclass 34, count 0 2006.224.07:50:10.81#ibcon#read 4, iclass 34, count 0 2006.224.07:50:10.81#ibcon#about to read 5, iclass 34, count 0 2006.224.07:50:10.81#ibcon#read 5, iclass 34, count 0 2006.224.07:50:10.81#ibcon#about to read 6, iclass 34, count 0 2006.224.07:50:10.81#ibcon#read 6, iclass 34, count 0 2006.224.07:50:10.81#ibcon#end of sib2, iclass 34, count 0 2006.224.07:50:10.81#ibcon#*mode == 0, iclass 34, count 0 2006.224.07:50:10.81#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.224.07:50:10.81#ibcon#[27=USB\r\n] 2006.224.07:50:10.81#ibcon#*before write, iclass 34, count 0 2006.224.07:50:10.81#ibcon#enter sib2, iclass 34, count 0 2006.224.07:50:10.81#ibcon#flushed, iclass 34, count 0 2006.224.07:50:10.81#ibcon#about to write, iclass 34, count 0 2006.224.07:50:10.81#ibcon#wrote, iclass 34, count 0 2006.224.07:50:10.81#ibcon#about to read 3, iclass 34, count 0 2006.224.07:50:10.84#ibcon#read 3, iclass 34, count 0 2006.224.07:50:10.84#ibcon#about to read 4, iclass 34, count 0 2006.224.07:50:10.84#ibcon#read 4, iclass 34, count 0 2006.224.07:50:10.84#ibcon#about to read 5, iclass 34, count 0 2006.224.07:50:10.84#ibcon#read 5, iclass 34, count 0 2006.224.07:50:10.84#ibcon#about to read 6, iclass 34, count 0 2006.224.07:50:10.84#ibcon#read 6, iclass 34, count 0 2006.224.07:50:10.84#ibcon#end of sib2, iclass 34, count 0 2006.224.07:50:10.84#ibcon#*after write, iclass 34, count 0 2006.224.07:50:10.84#ibcon#*before return 0, iclass 34, count 0 2006.224.07:50:10.84#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.224.07:50:10.84#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.224.07:50:10.84#ibcon#about to clear, iclass 34 cls_cnt 0 2006.224.07:50:10.84#ibcon#cleared, iclass 34 cls_cnt 0 2006.224.07:50:10.84$vc4f8/vblo=2,640.99 2006.224.07:50:10.84#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.224.07:50:10.84#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.224.07:50:10.84#ibcon#ireg 17 cls_cnt 0 2006.224.07:50:10.84#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.224.07:50:10.84#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.224.07:50:10.84#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.224.07:50:10.84#ibcon#enter wrdev, iclass 36, count 0 2006.224.07:50:10.84#ibcon#first serial, iclass 36, count 0 2006.224.07:50:10.84#ibcon#enter sib2, iclass 36, count 0 2006.224.07:50:10.84#ibcon#flushed, iclass 36, count 0 2006.224.07:50:10.84#ibcon#about to write, iclass 36, count 0 2006.224.07:50:10.84#ibcon#wrote, iclass 36, count 0 2006.224.07:50:10.84#ibcon#about to read 3, iclass 36, count 0 2006.224.07:50:10.86#ibcon#read 3, iclass 36, count 0 2006.224.07:50:10.86#ibcon#about to read 4, iclass 36, count 0 2006.224.07:50:10.86#ibcon#read 4, iclass 36, count 0 2006.224.07:50:10.86#ibcon#about to read 5, iclass 36, count 0 2006.224.07:50:10.86#ibcon#read 5, iclass 36, count 0 2006.224.07:50:10.86#ibcon#about to read 6, iclass 36, count 0 2006.224.07:50:10.86#ibcon#read 6, iclass 36, count 0 2006.224.07:50:10.86#ibcon#end of sib2, iclass 36, count 0 2006.224.07:50:10.86#ibcon#*mode == 0, iclass 36, count 0 2006.224.07:50:10.86#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.224.07:50:10.86#ibcon#[28=FRQ=02,640.99\r\n] 2006.224.07:50:10.86#ibcon#*before write, iclass 36, count 0 2006.224.07:50:10.86#ibcon#enter sib2, iclass 36, count 0 2006.224.07:50:10.86#ibcon#flushed, iclass 36, count 0 2006.224.07:50:10.86#ibcon#about to write, iclass 36, count 0 2006.224.07:50:10.86#ibcon#wrote, iclass 36, count 0 2006.224.07:50:10.86#ibcon#about to read 3, iclass 36, count 0 2006.224.07:50:10.90#ibcon#read 3, iclass 36, count 0 2006.224.07:50:10.90#ibcon#about to read 4, iclass 36, count 0 2006.224.07:50:10.90#ibcon#read 4, iclass 36, count 0 2006.224.07:50:10.90#ibcon#about to read 5, iclass 36, count 0 2006.224.07:50:10.90#ibcon#read 5, iclass 36, count 0 2006.224.07:50:10.90#ibcon#about to read 6, iclass 36, count 0 2006.224.07:50:10.90#ibcon#read 6, iclass 36, count 0 2006.224.07:50:10.90#ibcon#end of sib2, iclass 36, count 0 2006.224.07:50:10.90#ibcon#*after write, iclass 36, count 0 2006.224.07:50:10.90#ibcon#*before return 0, iclass 36, count 0 2006.224.07:50:10.90#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.224.07:50:10.90#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.224.07:50:10.90#ibcon#about to clear, iclass 36 cls_cnt 0 2006.224.07:50:10.90#ibcon#cleared, iclass 36 cls_cnt 0 2006.224.07:50:10.90$vc4f8/vb=2,4 2006.224.07:50:10.90#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.224.07:50:10.90#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.224.07:50:10.90#ibcon#ireg 11 cls_cnt 2 2006.224.07:50:10.90#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.224.07:50:10.96#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.224.07:50:10.96#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.224.07:50:10.96#ibcon#enter wrdev, iclass 38, count 2 2006.224.07:50:10.96#ibcon#first serial, iclass 38, count 2 2006.224.07:50:10.96#ibcon#enter sib2, iclass 38, count 2 2006.224.07:50:10.96#ibcon#flushed, iclass 38, count 2 2006.224.07:50:10.96#ibcon#about to write, iclass 38, count 2 2006.224.07:50:10.96#ibcon#wrote, iclass 38, count 2 2006.224.07:50:10.96#ibcon#about to read 3, iclass 38, count 2 2006.224.07:50:10.98#ibcon#read 3, iclass 38, count 2 2006.224.07:50:10.98#ibcon#about to read 4, iclass 38, count 2 2006.224.07:50:10.98#ibcon#read 4, iclass 38, count 2 2006.224.07:50:10.98#ibcon#about to read 5, iclass 38, count 2 2006.224.07:50:10.98#ibcon#read 5, iclass 38, count 2 2006.224.07:50:10.98#ibcon#about to read 6, iclass 38, count 2 2006.224.07:50:10.98#ibcon#read 6, iclass 38, count 2 2006.224.07:50:10.98#ibcon#end of sib2, iclass 38, count 2 2006.224.07:50:10.98#ibcon#*mode == 0, iclass 38, count 2 2006.224.07:50:10.98#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.224.07:50:10.98#ibcon#[27=AT02-04\r\n] 2006.224.07:50:10.98#ibcon#*before write, iclass 38, count 2 2006.224.07:50:10.98#ibcon#enter sib2, iclass 38, count 2 2006.224.07:50:10.98#ibcon#flushed, iclass 38, count 2 2006.224.07:50:10.98#ibcon#about to write, iclass 38, count 2 2006.224.07:50:10.98#ibcon#wrote, iclass 38, count 2 2006.224.07:50:10.98#ibcon#about to read 3, iclass 38, count 2 2006.224.07:50:11.01#ibcon#read 3, iclass 38, count 2 2006.224.07:50:11.01#ibcon#about to read 4, iclass 38, count 2 2006.224.07:50:11.01#ibcon#read 4, iclass 38, count 2 2006.224.07:50:11.01#ibcon#about to read 5, iclass 38, count 2 2006.224.07:50:11.01#ibcon#read 5, iclass 38, count 2 2006.224.07:50:11.01#ibcon#about to read 6, iclass 38, count 2 2006.224.07:50:11.01#ibcon#read 6, iclass 38, count 2 2006.224.07:50:11.01#ibcon#end of sib2, iclass 38, count 2 2006.224.07:50:11.01#ibcon#*after write, iclass 38, count 2 2006.224.07:50:11.01#ibcon#*before return 0, iclass 38, count 2 2006.224.07:50:11.01#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.224.07:50:11.01#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.224.07:50:11.01#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.224.07:50:11.01#ibcon#ireg 7 cls_cnt 0 2006.224.07:50:11.01#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.224.07:50:11.13#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.224.07:50:11.13#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.224.07:50:11.13#ibcon#enter wrdev, iclass 38, count 0 2006.224.07:50:11.13#ibcon#first serial, iclass 38, count 0 2006.224.07:50:11.13#ibcon#enter sib2, iclass 38, count 0 2006.224.07:50:11.13#ibcon#flushed, iclass 38, count 0 2006.224.07:50:11.13#ibcon#about to write, iclass 38, count 0 2006.224.07:50:11.13#ibcon#wrote, iclass 38, count 0 2006.224.07:50:11.13#ibcon#about to read 3, iclass 38, count 0 2006.224.07:50:11.15#ibcon#read 3, iclass 38, count 0 2006.224.07:50:11.15#ibcon#about to read 4, iclass 38, count 0 2006.224.07:50:11.15#ibcon#read 4, iclass 38, count 0 2006.224.07:50:11.15#ibcon#about to read 5, iclass 38, count 0 2006.224.07:50:11.15#ibcon#read 5, iclass 38, count 0 2006.224.07:50:11.15#ibcon#about to read 6, iclass 38, count 0 2006.224.07:50:11.15#ibcon#read 6, iclass 38, count 0 2006.224.07:50:11.15#ibcon#end of sib2, iclass 38, count 0 2006.224.07:50:11.15#ibcon#*mode == 0, iclass 38, count 0 2006.224.07:50:11.15#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.224.07:50:11.15#ibcon#[27=USB\r\n] 2006.224.07:50:11.15#ibcon#*before write, iclass 38, count 0 2006.224.07:50:11.15#ibcon#enter sib2, iclass 38, count 0 2006.224.07:50:11.15#ibcon#flushed, iclass 38, count 0 2006.224.07:50:11.15#ibcon#about to write, iclass 38, count 0 2006.224.07:50:11.15#ibcon#wrote, iclass 38, count 0 2006.224.07:50:11.15#ibcon#about to read 3, iclass 38, count 0 2006.224.07:50:11.18#ibcon#read 3, iclass 38, count 0 2006.224.07:50:11.18#ibcon#about to read 4, iclass 38, count 0 2006.224.07:50:11.18#ibcon#read 4, iclass 38, count 0 2006.224.07:50:11.18#ibcon#about to read 5, iclass 38, count 0 2006.224.07:50:11.18#ibcon#read 5, iclass 38, count 0 2006.224.07:50:11.18#ibcon#about to read 6, iclass 38, count 0 2006.224.07:50:11.18#ibcon#read 6, iclass 38, count 0 2006.224.07:50:11.18#ibcon#end of sib2, iclass 38, count 0 2006.224.07:50:11.18#ibcon#*after write, iclass 38, count 0 2006.224.07:50:11.18#ibcon#*before return 0, iclass 38, count 0 2006.224.07:50:11.18#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.224.07:50:11.18#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.224.07:50:11.18#ibcon#about to clear, iclass 38 cls_cnt 0 2006.224.07:50:11.18#ibcon#cleared, iclass 38 cls_cnt 0 2006.224.07:50:11.18$vc4f8/vblo=3,656.99 2006.224.07:50:11.18#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.224.07:50:11.18#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.224.07:50:11.18#ibcon#ireg 17 cls_cnt 0 2006.224.07:50:11.18#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.224.07:50:11.18#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.224.07:50:11.18#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.224.07:50:11.18#ibcon#enter wrdev, iclass 40, count 0 2006.224.07:50:11.18#ibcon#first serial, iclass 40, count 0 2006.224.07:50:11.18#ibcon#enter sib2, iclass 40, count 0 2006.224.07:50:11.18#ibcon#flushed, iclass 40, count 0 2006.224.07:50:11.18#ibcon#about to write, iclass 40, count 0 2006.224.07:50:11.18#ibcon#wrote, iclass 40, count 0 2006.224.07:50:11.18#ibcon#about to read 3, iclass 40, count 0 2006.224.07:50:11.20#ibcon#read 3, iclass 40, count 0 2006.224.07:50:11.20#ibcon#about to read 4, iclass 40, count 0 2006.224.07:50:11.20#ibcon#read 4, iclass 40, count 0 2006.224.07:50:11.20#ibcon#about to read 5, iclass 40, count 0 2006.224.07:50:11.20#ibcon#read 5, iclass 40, count 0 2006.224.07:50:11.20#ibcon#about to read 6, iclass 40, count 0 2006.224.07:50:11.20#ibcon#read 6, iclass 40, count 0 2006.224.07:50:11.20#ibcon#end of sib2, iclass 40, count 0 2006.224.07:50:11.20#ibcon#*mode == 0, iclass 40, count 0 2006.224.07:50:11.20#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.224.07:50:11.20#ibcon#[28=FRQ=03,656.99\r\n] 2006.224.07:50:11.20#ibcon#*before write, iclass 40, count 0 2006.224.07:50:11.20#ibcon#enter sib2, iclass 40, count 0 2006.224.07:50:11.20#ibcon#flushed, iclass 40, count 0 2006.224.07:50:11.20#ibcon#about to write, iclass 40, count 0 2006.224.07:50:11.20#ibcon#wrote, iclass 40, count 0 2006.224.07:50:11.20#ibcon#about to read 3, iclass 40, count 0 2006.224.07:50:11.24#ibcon#read 3, iclass 40, count 0 2006.224.07:50:11.24#ibcon#about to read 4, iclass 40, count 0 2006.224.07:50:11.24#ibcon#read 4, iclass 40, count 0 2006.224.07:50:11.24#ibcon#about to read 5, iclass 40, count 0 2006.224.07:50:11.24#ibcon#read 5, iclass 40, count 0 2006.224.07:50:11.24#ibcon#about to read 6, iclass 40, count 0 2006.224.07:50:11.24#ibcon#read 6, iclass 40, count 0 2006.224.07:50:11.24#ibcon#end of sib2, iclass 40, count 0 2006.224.07:50:11.24#ibcon#*after write, iclass 40, count 0 2006.224.07:50:11.24#ibcon#*before return 0, iclass 40, count 0 2006.224.07:50:11.24#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.224.07:50:11.24#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.224.07:50:11.24#ibcon#about to clear, iclass 40 cls_cnt 0 2006.224.07:50:11.24#ibcon#cleared, iclass 40 cls_cnt 0 2006.224.07:50:11.24$vc4f8/vb=3,4 2006.224.07:50:11.24#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.224.07:50:11.24#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.224.07:50:11.24#ibcon#ireg 11 cls_cnt 2 2006.224.07:50:11.24#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.224.07:50:11.30#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.224.07:50:11.30#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.224.07:50:11.30#ibcon#enter wrdev, iclass 4, count 2 2006.224.07:50:11.30#ibcon#first serial, iclass 4, count 2 2006.224.07:50:11.30#ibcon#enter sib2, iclass 4, count 2 2006.224.07:50:11.30#ibcon#flushed, iclass 4, count 2 2006.224.07:50:11.30#ibcon#about to write, iclass 4, count 2 2006.224.07:50:11.30#ibcon#wrote, iclass 4, count 2 2006.224.07:50:11.30#ibcon#about to read 3, iclass 4, count 2 2006.224.07:50:11.32#ibcon#read 3, iclass 4, count 2 2006.224.07:50:11.32#ibcon#about to read 4, iclass 4, count 2 2006.224.07:50:11.32#ibcon#read 4, iclass 4, count 2 2006.224.07:50:11.32#ibcon#about to read 5, iclass 4, count 2 2006.224.07:50:11.32#ibcon#read 5, iclass 4, count 2 2006.224.07:50:11.32#ibcon#about to read 6, iclass 4, count 2 2006.224.07:50:11.32#ibcon#read 6, iclass 4, count 2 2006.224.07:50:11.32#ibcon#end of sib2, iclass 4, count 2 2006.224.07:50:11.32#ibcon#*mode == 0, iclass 4, count 2 2006.224.07:50:11.32#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.224.07:50:11.32#ibcon#[27=AT03-04\r\n] 2006.224.07:50:11.32#ibcon#*before write, iclass 4, count 2 2006.224.07:50:11.32#ibcon#enter sib2, iclass 4, count 2 2006.224.07:50:11.32#ibcon#flushed, iclass 4, count 2 2006.224.07:50:11.32#ibcon#about to write, iclass 4, count 2 2006.224.07:50:11.32#ibcon#wrote, iclass 4, count 2 2006.224.07:50:11.32#ibcon#about to read 3, iclass 4, count 2 2006.224.07:50:11.35#ibcon#read 3, iclass 4, count 2 2006.224.07:50:11.35#ibcon#about to read 4, iclass 4, count 2 2006.224.07:50:11.35#ibcon#read 4, iclass 4, count 2 2006.224.07:50:11.35#ibcon#about to read 5, iclass 4, count 2 2006.224.07:50:11.35#ibcon#read 5, iclass 4, count 2 2006.224.07:50:11.35#ibcon#about to read 6, iclass 4, count 2 2006.224.07:50:11.35#ibcon#read 6, iclass 4, count 2 2006.224.07:50:11.35#ibcon#end of sib2, iclass 4, count 2 2006.224.07:50:11.35#ibcon#*after write, iclass 4, count 2 2006.224.07:50:11.35#ibcon#*before return 0, iclass 4, count 2 2006.224.07:50:11.35#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.224.07:50:11.35#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.224.07:50:11.35#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.224.07:50:11.35#ibcon#ireg 7 cls_cnt 0 2006.224.07:50:11.35#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.224.07:50:11.47#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.224.07:50:11.47#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.224.07:50:11.47#ibcon#enter wrdev, iclass 4, count 0 2006.224.07:50:11.47#ibcon#first serial, iclass 4, count 0 2006.224.07:50:11.47#ibcon#enter sib2, iclass 4, count 0 2006.224.07:50:11.47#ibcon#flushed, iclass 4, count 0 2006.224.07:50:11.47#ibcon#about to write, iclass 4, count 0 2006.224.07:50:11.47#ibcon#wrote, iclass 4, count 0 2006.224.07:50:11.47#ibcon#about to read 3, iclass 4, count 0 2006.224.07:50:11.49#ibcon#read 3, iclass 4, count 0 2006.224.07:50:11.49#ibcon#about to read 4, iclass 4, count 0 2006.224.07:50:11.49#ibcon#read 4, iclass 4, count 0 2006.224.07:50:11.49#ibcon#about to read 5, iclass 4, count 0 2006.224.07:50:11.49#ibcon#read 5, iclass 4, count 0 2006.224.07:50:11.49#ibcon#about to read 6, iclass 4, count 0 2006.224.07:50:11.49#ibcon#read 6, iclass 4, count 0 2006.224.07:50:11.49#ibcon#end of sib2, iclass 4, count 0 2006.224.07:50:11.49#ibcon#*mode == 0, iclass 4, count 0 2006.224.07:50:11.49#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.224.07:50:11.49#ibcon#[27=USB\r\n] 2006.224.07:50:11.49#ibcon#*before write, iclass 4, count 0 2006.224.07:50:11.49#ibcon#enter sib2, iclass 4, count 0 2006.224.07:50:11.49#ibcon#flushed, iclass 4, count 0 2006.224.07:50:11.49#ibcon#about to write, iclass 4, count 0 2006.224.07:50:11.49#ibcon#wrote, iclass 4, count 0 2006.224.07:50:11.49#ibcon#about to read 3, iclass 4, count 0 2006.224.07:50:11.52#ibcon#read 3, iclass 4, count 0 2006.224.07:50:11.52#ibcon#about to read 4, iclass 4, count 0 2006.224.07:50:11.52#ibcon#read 4, iclass 4, count 0 2006.224.07:50:11.52#ibcon#about to read 5, iclass 4, count 0 2006.224.07:50:11.52#ibcon#read 5, iclass 4, count 0 2006.224.07:50:11.52#ibcon#about to read 6, iclass 4, count 0 2006.224.07:50:11.52#ibcon#read 6, iclass 4, count 0 2006.224.07:50:11.52#ibcon#end of sib2, iclass 4, count 0 2006.224.07:50:11.52#ibcon#*after write, iclass 4, count 0 2006.224.07:50:11.52#ibcon#*before return 0, iclass 4, count 0 2006.224.07:50:11.52#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.224.07:50:11.52#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.224.07:50:11.52#ibcon#about to clear, iclass 4 cls_cnt 0 2006.224.07:50:11.52#ibcon#cleared, iclass 4 cls_cnt 0 2006.224.07:50:11.52$vc4f8/vblo=4,712.99 2006.224.07:50:11.52#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.224.07:50:11.52#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.224.07:50:11.52#ibcon#ireg 17 cls_cnt 0 2006.224.07:50:11.52#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.224.07:50:11.52#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.224.07:50:11.52#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.224.07:50:11.52#ibcon#enter wrdev, iclass 6, count 0 2006.224.07:50:11.52#ibcon#first serial, iclass 6, count 0 2006.224.07:50:11.52#ibcon#enter sib2, iclass 6, count 0 2006.224.07:50:11.52#ibcon#flushed, iclass 6, count 0 2006.224.07:50:11.52#ibcon#about to write, iclass 6, count 0 2006.224.07:50:11.52#ibcon#wrote, iclass 6, count 0 2006.224.07:50:11.52#ibcon#about to read 3, iclass 6, count 0 2006.224.07:50:11.54#ibcon#read 3, iclass 6, count 0 2006.224.07:50:11.54#ibcon#about to read 4, iclass 6, count 0 2006.224.07:50:11.54#ibcon#read 4, iclass 6, count 0 2006.224.07:50:11.54#ibcon#about to read 5, iclass 6, count 0 2006.224.07:50:11.54#ibcon#read 5, iclass 6, count 0 2006.224.07:50:11.54#ibcon#about to read 6, iclass 6, count 0 2006.224.07:50:11.54#ibcon#read 6, iclass 6, count 0 2006.224.07:50:11.54#ibcon#end of sib2, iclass 6, count 0 2006.224.07:50:11.54#ibcon#*mode == 0, iclass 6, count 0 2006.224.07:50:11.54#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.224.07:50:11.54#ibcon#[28=FRQ=04,712.99\r\n] 2006.224.07:50:11.54#ibcon#*before write, iclass 6, count 0 2006.224.07:50:11.54#ibcon#enter sib2, iclass 6, count 0 2006.224.07:50:11.54#ibcon#flushed, iclass 6, count 0 2006.224.07:50:11.54#ibcon#about to write, iclass 6, count 0 2006.224.07:50:11.54#ibcon#wrote, iclass 6, count 0 2006.224.07:50:11.54#ibcon#about to read 3, iclass 6, count 0 2006.224.07:50:11.58#ibcon#read 3, iclass 6, count 0 2006.224.07:50:11.58#ibcon#about to read 4, iclass 6, count 0 2006.224.07:50:11.58#ibcon#read 4, iclass 6, count 0 2006.224.07:50:11.58#ibcon#about to read 5, iclass 6, count 0 2006.224.07:50:11.58#ibcon#read 5, iclass 6, count 0 2006.224.07:50:11.58#ibcon#about to read 6, iclass 6, count 0 2006.224.07:50:11.58#ibcon#read 6, iclass 6, count 0 2006.224.07:50:11.58#ibcon#end of sib2, iclass 6, count 0 2006.224.07:50:11.58#ibcon#*after write, iclass 6, count 0 2006.224.07:50:11.58#ibcon#*before return 0, iclass 6, count 0 2006.224.07:50:11.58#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.224.07:50:11.58#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.224.07:50:11.58#ibcon#about to clear, iclass 6 cls_cnt 0 2006.224.07:50:11.58#ibcon#cleared, iclass 6 cls_cnt 0 2006.224.07:50:11.58$vc4f8/vb=4,4 2006.224.07:50:11.58#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.224.07:50:11.58#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.224.07:50:11.58#ibcon#ireg 11 cls_cnt 2 2006.224.07:50:11.58#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.224.07:50:11.64#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.224.07:50:11.64#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.224.07:50:11.64#ibcon#enter wrdev, iclass 10, count 2 2006.224.07:50:11.64#ibcon#first serial, iclass 10, count 2 2006.224.07:50:11.64#ibcon#enter sib2, iclass 10, count 2 2006.224.07:50:11.64#ibcon#flushed, iclass 10, count 2 2006.224.07:50:11.64#ibcon#about to write, iclass 10, count 2 2006.224.07:50:11.64#ibcon#wrote, iclass 10, count 2 2006.224.07:50:11.64#ibcon#about to read 3, iclass 10, count 2 2006.224.07:50:11.66#ibcon#read 3, iclass 10, count 2 2006.224.07:50:11.66#ibcon#about to read 4, iclass 10, count 2 2006.224.07:50:11.66#ibcon#read 4, iclass 10, count 2 2006.224.07:50:11.66#ibcon#about to read 5, iclass 10, count 2 2006.224.07:50:11.66#ibcon#read 5, iclass 10, count 2 2006.224.07:50:11.66#ibcon#about to read 6, iclass 10, count 2 2006.224.07:50:11.66#ibcon#read 6, iclass 10, count 2 2006.224.07:50:11.66#ibcon#end of sib2, iclass 10, count 2 2006.224.07:50:11.66#ibcon#*mode == 0, iclass 10, count 2 2006.224.07:50:11.66#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.224.07:50:11.66#ibcon#[27=AT04-04\r\n] 2006.224.07:50:11.66#ibcon#*before write, iclass 10, count 2 2006.224.07:50:11.66#ibcon#enter sib2, iclass 10, count 2 2006.224.07:50:11.66#ibcon#flushed, iclass 10, count 2 2006.224.07:50:11.66#ibcon#about to write, iclass 10, count 2 2006.224.07:50:11.66#ibcon#wrote, iclass 10, count 2 2006.224.07:50:11.66#ibcon#about to read 3, iclass 10, count 2 2006.224.07:50:11.69#ibcon#read 3, iclass 10, count 2 2006.224.07:50:11.69#ibcon#about to read 4, iclass 10, count 2 2006.224.07:50:11.69#ibcon#read 4, iclass 10, count 2 2006.224.07:50:11.69#ibcon#about to read 5, iclass 10, count 2 2006.224.07:50:11.69#ibcon#read 5, iclass 10, count 2 2006.224.07:50:11.69#ibcon#about to read 6, iclass 10, count 2 2006.224.07:50:11.69#ibcon#read 6, iclass 10, count 2 2006.224.07:50:11.69#ibcon#end of sib2, iclass 10, count 2 2006.224.07:50:11.69#ibcon#*after write, iclass 10, count 2 2006.224.07:50:11.69#ibcon#*before return 0, iclass 10, count 2 2006.224.07:50:11.69#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.224.07:50:11.69#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.224.07:50:11.69#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.224.07:50:11.69#ibcon#ireg 7 cls_cnt 0 2006.224.07:50:11.69#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.224.07:50:11.73#abcon#<5=/07 0.4 1.5 23.601001004.1\r\n> 2006.224.07:50:11.75#abcon#{5=INTERFACE CLEAR} 2006.224.07:50:11.81#abcon#[5=S1D000X0/0*\r\n] 2006.224.07:50:11.81#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.224.07:50:11.81#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.224.07:50:11.81#ibcon#enter wrdev, iclass 10, count 0 2006.224.07:50:11.81#ibcon#first serial, iclass 10, count 0 2006.224.07:50:11.81#ibcon#enter sib2, iclass 10, count 0 2006.224.07:50:11.81#ibcon#flushed, iclass 10, count 0 2006.224.07:50:11.81#ibcon#about to write, iclass 10, count 0 2006.224.07:50:11.81#ibcon#wrote, iclass 10, count 0 2006.224.07:50:11.81#ibcon#about to read 3, iclass 10, count 0 2006.224.07:50:11.83#ibcon#read 3, iclass 10, count 0 2006.224.07:50:11.83#ibcon#about to read 4, iclass 10, count 0 2006.224.07:50:11.83#ibcon#read 4, iclass 10, count 0 2006.224.07:50:11.83#ibcon#about to read 5, iclass 10, count 0 2006.224.07:50:11.83#ibcon#read 5, iclass 10, count 0 2006.224.07:50:11.83#ibcon#about to read 6, iclass 10, count 0 2006.224.07:50:11.83#ibcon#read 6, iclass 10, count 0 2006.224.07:50:11.83#ibcon#end of sib2, iclass 10, count 0 2006.224.07:50:11.83#ibcon#*mode == 0, iclass 10, count 0 2006.224.07:50:11.83#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.224.07:50:11.83#ibcon#[27=USB\r\n] 2006.224.07:50:11.83#ibcon#*before write, iclass 10, count 0 2006.224.07:50:11.83#ibcon#enter sib2, iclass 10, count 0 2006.224.07:50:11.83#ibcon#flushed, iclass 10, count 0 2006.224.07:50:11.83#ibcon#about to write, iclass 10, count 0 2006.224.07:50:11.83#ibcon#wrote, iclass 10, count 0 2006.224.07:50:11.83#ibcon#about to read 3, iclass 10, count 0 2006.224.07:50:11.86#ibcon#read 3, iclass 10, count 0 2006.224.07:50:11.86#ibcon#about to read 4, iclass 10, count 0 2006.224.07:50:11.86#ibcon#read 4, iclass 10, count 0 2006.224.07:50:11.86#ibcon#about to read 5, iclass 10, count 0 2006.224.07:50:11.86#ibcon#read 5, iclass 10, count 0 2006.224.07:50:11.86#ibcon#about to read 6, iclass 10, count 0 2006.224.07:50:11.86#ibcon#read 6, iclass 10, count 0 2006.224.07:50:11.86#ibcon#end of sib2, iclass 10, count 0 2006.224.07:50:11.86#ibcon#*after write, iclass 10, count 0 2006.224.07:50:11.86#ibcon#*before return 0, iclass 10, count 0 2006.224.07:50:11.86#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.224.07:50:11.86#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.224.07:50:11.86#ibcon#about to clear, iclass 10 cls_cnt 0 2006.224.07:50:11.86#ibcon#cleared, iclass 10 cls_cnt 0 2006.224.07:50:11.86$vc4f8/vblo=5,744.99 2006.224.07:50:11.86#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.224.07:50:11.86#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.224.07:50:11.86#ibcon#ireg 17 cls_cnt 0 2006.224.07:50:11.86#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.224.07:50:11.86#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.224.07:50:11.86#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.224.07:50:11.86#ibcon#enter wrdev, iclass 16, count 0 2006.224.07:50:11.86#ibcon#first serial, iclass 16, count 0 2006.224.07:50:11.86#ibcon#enter sib2, iclass 16, count 0 2006.224.07:50:11.86#ibcon#flushed, iclass 16, count 0 2006.224.07:50:11.86#ibcon#about to write, iclass 16, count 0 2006.224.07:50:11.86#ibcon#wrote, iclass 16, count 0 2006.224.07:50:11.86#ibcon#about to read 3, iclass 16, count 0 2006.224.07:50:11.88#ibcon#read 3, iclass 16, count 0 2006.224.07:50:11.88#ibcon#about to read 4, iclass 16, count 0 2006.224.07:50:11.88#ibcon#read 4, iclass 16, count 0 2006.224.07:50:11.88#ibcon#about to read 5, iclass 16, count 0 2006.224.07:50:11.88#ibcon#read 5, iclass 16, count 0 2006.224.07:50:11.88#ibcon#about to read 6, iclass 16, count 0 2006.224.07:50:11.88#ibcon#read 6, iclass 16, count 0 2006.224.07:50:11.88#ibcon#end of sib2, iclass 16, count 0 2006.224.07:50:11.88#ibcon#*mode == 0, iclass 16, count 0 2006.224.07:50:11.88#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.224.07:50:11.88#ibcon#[28=FRQ=05,744.99\r\n] 2006.224.07:50:11.88#ibcon#*before write, iclass 16, count 0 2006.224.07:50:11.88#ibcon#enter sib2, iclass 16, count 0 2006.224.07:50:11.88#ibcon#flushed, iclass 16, count 0 2006.224.07:50:11.88#ibcon#about to write, iclass 16, count 0 2006.224.07:50:11.88#ibcon#wrote, iclass 16, count 0 2006.224.07:50:11.88#ibcon#about to read 3, iclass 16, count 0 2006.224.07:50:11.92#ibcon#read 3, iclass 16, count 0 2006.224.07:50:11.92#ibcon#about to read 4, iclass 16, count 0 2006.224.07:50:11.92#ibcon#read 4, iclass 16, count 0 2006.224.07:50:11.92#ibcon#about to read 5, iclass 16, count 0 2006.224.07:50:11.92#ibcon#read 5, iclass 16, count 0 2006.224.07:50:11.92#ibcon#about to read 6, iclass 16, count 0 2006.224.07:50:11.92#ibcon#read 6, iclass 16, count 0 2006.224.07:50:11.92#ibcon#end of sib2, iclass 16, count 0 2006.224.07:50:11.92#ibcon#*after write, iclass 16, count 0 2006.224.07:50:11.92#ibcon#*before return 0, iclass 16, count 0 2006.224.07:50:11.92#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.224.07:50:11.92#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.224.07:50:11.92#ibcon#about to clear, iclass 16 cls_cnt 0 2006.224.07:50:11.92#ibcon#cleared, iclass 16 cls_cnt 0 2006.224.07:50:11.92$vc4f8/vb=5,4 2006.224.07:50:11.92#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.224.07:50:11.92#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.224.07:50:11.92#ibcon#ireg 11 cls_cnt 2 2006.224.07:50:11.92#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.224.07:50:11.98#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.224.07:50:11.98#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.224.07:50:11.98#ibcon#enter wrdev, iclass 18, count 2 2006.224.07:50:11.98#ibcon#first serial, iclass 18, count 2 2006.224.07:50:11.98#ibcon#enter sib2, iclass 18, count 2 2006.224.07:50:11.98#ibcon#flushed, iclass 18, count 2 2006.224.07:50:11.98#ibcon#about to write, iclass 18, count 2 2006.224.07:50:11.98#ibcon#wrote, iclass 18, count 2 2006.224.07:50:11.98#ibcon#about to read 3, iclass 18, count 2 2006.224.07:50:12.00#ibcon#read 3, iclass 18, count 2 2006.224.07:50:12.00#ibcon#about to read 4, iclass 18, count 2 2006.224.07:50:12.00#ibcon#read 4, iclass 18, count 2 2006.224.07:50:12.00#ibcon#about to read 5, iclass 18, count 2 2006.224.07:50:12.00#ibcon#read 5, iclass 18, count 2 2006.224.07:50:12.00#ibcon#about to read 6, iclass 18, count 2 2006.224.07:50:12.00#ibcon#read 6, iclass 18, count 2 2006.224.07:50:12.00#ibcon#end of sib2, iclass 18, count 2 2006.224.07:50:12.00#ibcon#*mode == 0, iclass 18, count 2 2006.224.07:50:12.00#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.224.07:50:12.00#ibcon#[27=AT05-04\r\n] 2006.224.07:50:12.00#ibcon#*before write, iclass 18, count 2 2006.224.07:50:12.00#ibcon#enter sib2, iclass 18, count 2 2006.224.07:50:12.00#ibcon#flushed, iclass 18, count 2 2006.224.07:50:12.00#ibcon#about to write, iclass 18, count 2 2006.224.07:50:12.00#ibcon#wrote, iclass 18, count 2 2006.224.07:50:12.00#ibcon#about to read 3, iclass 18, count 2 2006.224.07:50:12.03#ibcon#read 3, iclass 18, count 2 2006.224.07:50:12.03#ibcon#about to read 4, iclass 18, count 2 2006.224.07:50:12.03#ibcon#read 4, iclass 18, count 2 2006.224.07:50:12.03#ibcon#about to read 5, iclass 18, count 2 2006.224.07:50:12.03#ibcon#read 5, iclass 18, count 2 2006.224.07:50:12.03#ibcon#about to read 6, iclass 18, count 2 2006.224.07:50:12.03#ibcon#read 6, iclass 18, count 2 2006.224.07:50:12.03#ibcon#end of sib2, iclass 18, count 2 2006.224.07:50:12.03#ibcon#*after write, iclass 18, count 2 2006.224.07:50:12.03#ibcon#*before return 0, iclass 18, count 2 2006.224.07:50:12.03#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.224.07:50:12.03#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.224.07:50:12.03#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.224.07:50:12.03#ibcon#ireg 7 cls_cnt 0 2006.224.07:50:12.03#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.224.07:50:12.15#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.224.07:50:12.15#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.224.07:50:12.15#ibcon#enter wrdev, iclass 18, count 0 2006.224.07:50:12.15#ibcon#first serial, iclass 18, count 0 2006.224.07:50:12.15#ibcon#enter sib2, iclass 18, count 0 2006.224.07:50:12.15#ibcon#flushed, iclass 18, count 0 2006.224.07:50:12.15#ibcon#about to write, iclass 18, count 0 2006.224.07:50:12.15#ibcon#wrote, iclass 18, count 0 2006.224.07:50:12.15#ibcon#about to read 3, iclass 18, count 0 2006.224.07:50:12.17#ibcon#read 3, iclass 18, count 0 2006.224.07:50:12.17#ibcon#about to read 4, iclass 18, count 0 2006.224.07:50:12.17#ibcon#read 4, iclass 18, count 0 2006.224.07:50:12.17#ibcon#about to read 5, iclass 18, count 0 2006.224.07:50:12.17#ibcon#read 5, iclass 18, count 0 2006.224.07:50:12.17#ibcon#about to read 6, iclass 18, count 0 2006.224.07:50:12.17#ibcon#read 6, iclass 18, count 0 2006.224.07:50:12.17#ibcon#end of sib2, iclass 18, count 0 2006.224.07:50:12.17#ibcon#*mode == 0, iclass 18, count 0 2006.224.07:50:12.17#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.224.07:50:12.17#ibcon#[27=USB\r\n] 2006.224.07:50:12.17#ibcon#*before write, iclass 18, count 0 2006.224.07:50:12.17#ibcon#enter sib2, iclass 18, count 0 2006.224.07:50:12.17#ibcon#flushed, iclass 18, count 0 2006.224.07:50:12.17#ibcon#about to write, iclass 18, count 0 2006.224.07:50:12.17#ibcon#wrote, iclass 18, count 0 2006.224.07:50:12.17#ibcon#about to read 3, iclass 18, count 0 2006.224.07:50:12.20#ibcon#read 3, iclass 18, count 0 2006.224.07:50:12.20#ibcon#about to read 4, iclass 18, count 0 2006.224.07:50:12.20#ibcon#read 4, iclass 18, count 0 2006.224.07:50:12.20#ibcon#about to read 5, iclass 18, count 0 2006.224.07:50:12.20#ibcon#read 5, iclass 18, count 0 2006.224.07:50:12.20#ibcon#about to read 6, iclass 18, count 0 2006.224.07:50:12.20#ibcon#read 6, iclass 18, count 0 2006.224.07:50:12.20#ibcon#end of sib2, iclass 18, count 0 2006.224.07:50:12.20#ibcon#*after write, iclass 18, count 0 2006.224.07:50:12.20#ibcon#*before return 0, iclass 18, count 0 2006.224.07:50:12.20#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.224.07:50:12.20#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.224.07:50:12.20#ibcon#about to clear, iclass 18 cls_cnt 0 2006.224.07:50:12.20#ibcon#cleared, iclass 18 cls_cnt 0 2006.224.07:50:12.20$vc4f8/vblo=6,752.99 2006.224.07:50:12.20#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.224.07:50:12.20#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.224.07:50:12.20#ibcon#ireg 17 cls_cnt 0 2006.224.07:50:12.20#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.224.07:50:12.20#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.224.07:50:12.20#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.224.07:50:12.20#ibcon#enter wrdev, iclass 20, count 0 2006.224.07:50:12.20#ibcon#first serial, iclass 20, count 0 2006.224.07:50:12.20#ibcon#enter sib2, iclass 20, count 0 2006.224.07:50:12.20#ibcon#flushed, iclass 20, count 0 2006.224.07:50:12.20#ibcon#about to write, iclass 20, count 0 2006.224.07:50:12.20#ibcon#wrote, iclass 20, count 0 2006.224.07:50:12.20#ibcon#about to read 3, iclass 20, count 0 2006.224.07:50:12.22#ibcon#read 3, iclass 20, count 0 2006.224.07:50:12.22#ibcon#about to read 4, iclass 20, count 0 2006.224.07:50:12.22#ibcon#read 4, iclass 20, count 0 2006.224.07:50:12.22#ibcon#about to read 5, iclass 20, count 0 2006.224.07:50:12.22#ibcon#read 5, iclass 20, count 0 2006.224.07:50:12.22#ibcon#about to read 6, iclass 20, count 0 2006.224.07:50:12.22#ibcon#read 6, iclass 20, count 0 2006.224.07:50:12.22#ibcon#end of sib2, iclass 20, count 0 2006.224.07:50:12.22#ibcon#*mode == 0, iclass 20, count 0 2006.224.07:50:12.22#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.224.07:50:12.22#ibcon#[28=FRQ=06,752.99\r\n] 2006.224.07:50:12.22#ibcon#*before write, iclass 20, count 0 2006.224.07:50:12.22#ibcon#enter sib2, iclass 20, count 0 2006.224.07:50:12.22#ibcon#flushed, iclass 20, count 0 2006.224.07:50:12.22#ibcon#about to write, iclass 20, count 0 2006.224.07:50:12.22#ibcon#wrote, iclass 20, count 0 2006.224.07:50:12.22#ibcon#about to read 3, iclass 20, count 0 2006.224.07:50:12.26#ibcon#read 3, iclass 20, count 0 2006.224.07:50:12.26#ibcon#about to read 4, iclass 20, count 0 2006.224.07:50:12.26#ibcon#read 4, iclass 20, count 0 2006.224.07:50:12.26#ibcon#about to read 5, iclass 20, count 0 2006.224.07:50:12.26#ibcon#read 5, iclass 20, count 0 2006.224.07:50:12.26#ibcon#about to read 6, iclass 20, count 0 2006.224.07:50:12.26#ibcon#read 6, iclass 20, count 0 2006.224.07:50:12.26#ibcon#end of sib2, iclass 20, count 0 2006.224.07:50:12.26#ibcon#*after write, iclass 20, count 0 2006.224.07:50:12.26#ibcon#*before return 0, iclass 20, count 0 2006.224.07:50:12.26#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.224.07:50:12.26#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.224.07:50:12.26#ibcon#about to clear, iclass 20 cls_cnt 0 2006.224.07:50:12.26#ibcon#cleared, iclass 20 cls_cnt 0 2006.224.07:50:12.26$vc4f8/vb=6,4 2006.224.07:50:12.26#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.224.07:50:12.26#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.224.07:50:12.26#ibcon#ireg 11 cls_cnt 2 2006.224.07:50:12.26#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.224.07:50:12.32#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.224.07:50:12.32#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.224.07:50:12.32#ibcon#enter wrdev, iclass 22, count 2 2006.224.07:50:12.32#ibcon#first serial, iclass 22, count 2 2006.224.07:50:12.32#ibcon#enter sib2, iclass 22, count 2 2006.224.07:50:12.32#ibcon#flushed, iclass 22, count 2 2006.224.07:50:12.32#ibcon#about to write, iclass 22, count 2 2006.224.07:50:12.32#ibcon#wrote, iclass 22, count 2 2006.224.07:50:12.32#ibcon#about to read 3, iclass 22, count 2 2006.224.07:50:12.34#ibcon#read 3, iclass 22, count 2 2006.224.07:50:12.34#ibcon#about to read 4, iclass 22, count 2 2006.224.07:50:12.34#ibcon#read 4, iclass 22, count 2 2006.224.07:50:12.34#ibcon#about to read 5, iclass 22, count 2 2006.224.07:50:12.34#ibcon#read 5, iclass 22, count 2 2006.224.07:50:12.34#ibcon#about to read 6, iclass 22, count 2 2006.224.07:50:12.34#ibcon#read 6, iclass 22, count 2 2006.224.07:50:12.34#ibcon#end of sib2, iclass 22, count 2 2006.224.07:50:12.34#ibcon#*mode == 0, iclass 22, count 2 2006.224.07:50:12.34#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.224.07:50:12.34#ibcon#[27=AT06-04\r\n] 2006.224.07:50:12.34#ibcon#*before write, iclass 22, count 2 2006.224.07:50:12.34#ibcon#enter sib2, iclass 22, count 2 2006.224.07:50:12.34#ibcon#flushed, iclass 22, count 2 2006.224.07:50:12.34#ibcon#about to write, iclass 22, count 2 2006.224.07:50:12.34#ibcon#wrote, iclass 22, count 2 2006.224.07:50:12.34#ibcon#about to read 3, iclass 22, count 2 2006.224.07:50:12.37#ibcon#read 3, iclass 22, count 2 2006.224.07:50:12.37#ibcon#about to read 4, iclass 22, count 2 2006.224.07:50:12.37#ibcon#read 4, iclass 22, count 2 2006.224.07:50:12.37#ibcon#about to read 5, iclass 22, count 2 2006.224.07:50:12.37#ibcon#read 5, iclass 22, count 2 2006.224.07:50:12.37#ibcon#about to read 6, iclass 22, count 2 2006.224.07:50:12.37#ibcon#read 6, iclass 22, count 2 2006.224.07:50:12.37#ibcon#end of sib2, iclass 22, count 2 2006.224.07:50:12.37#ibcon#*after write, iclass 22, count 2 2006.224.07:50:12.37#ibcon#*before return 0, iclass 22, count 2 2006.224.07:50:12.37#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.224.07:50:12.37#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.224.07:50:12.37#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.224.07:50:12.37#ibcon#ireg 7 cls_cnt 0 2006.224.07:50:12.37#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.224.07:50:12.49#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.224.07:50:12.49#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.224.07:50:12.49#ibcon#enter wrdev, iclass 22, count 0 2006.224.07:50:12.49#ibcon#first serial, iclass 22, count 0 2006.224.07:50:12.49#ibcon#enter sib2, iclass 22, count 0 2006.224.07:50:12.49#ibcon#flushed, iclass 22, count 0 2006.224.07:50:12.49#ibcon#about to write, iclass 22, count 0 2006.224.07:50:12.49#ibcon#wrote, iclass 22, count 0 2006.224.07:50:12.49#ibcon#about to read 3, iclass 22, count 0 2006.224.07:50:12.51#ibcon#read 3, iclass 22, count 0 2006.224.07:50:12.51#ibcon#about to read 4, iclass 22, count 0 2006.224.07:50:12.51#ibcon#read 4, iclass 22, count 0 2006.224.07:50:12.51#ibcon#about to read 5, iclass 22, count 0 2006.224.07:50:12.51#ibcon#read 5, iclass 22, count 0 2006.224.07:50:12.51#ibcon#about to read 6, iclass 22, count 0 2006.224.07:50:12.51#ibcon#read 6, iclass 22, count 0 2006.224.07:50:12.51#ibcon#end of sib2, iclass 22, count 0 2006.224.07:50:12.51#ibcon#*mode == 0, iclass 22, count 0 2006.224.07:50:12.51#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.224.07:50:12.51#ibcon#[27=USB\r\n] 2006.224.07:50:12.51#ibcon#*before write, iclass 22, count 0 2006.224.07:50:12.51#ibcon#enter sib2, iclass 22, count 0 2006.224.07:50:12.51#ibcon#flushed, iclass 22, count 0 2006.224.07:50:12.51#ibcon#about to write, iclass 22, count 0 2006.224.07:50:12.51#ibcon#wrote, iclass 22, count 0 2006.224.07:50:12.51#ibcon#about to read 3, iclass 22, count 0 2006.224.07:50:12.54#ibcon#read 3, iclass 22, count 0 2006.224.07:50:12.54#ibcon#about to read 4, iclass 22, count 0 2006.224.07:50:12.54#ibcon#read 4, iclass 22, count 0 2006.224.07:50:12.54#ibcon#about to read 5, iclass 22, count 0 2006.224.07:50:12.54#ibcon#read 5, iclass 22, count 0 2006.224.07:50:12.54#ibcon#about to read 6, iclass 22, count 0 2006.224.07:50:12.54#ibcon#read 6, iclass 22, count 0 2006.224.07:50:12.54#ibcon#end of sib2, iclass 22, count 0 2006.224.07:50:12.54#ibcon#*after write, iclass 22, count 0 2006.224.07:50:12.54#ibcon#*before return 0, iclass 22, count 0 2006.224.07:50:12.54#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.224.07:50:12.54#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.224.07:50:12.54#ibcon#about to clear, iclass 22 cls_cnt 0 2006.224.07:50:12.54#ibcon#cleared, iclass 22 cls_cnt 0 2006.224.07:50:12.54$vc4f8/vabw=wide 2006.224.07:50:12.54#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.224.07:50:12.54#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.224.07:50:12.54#ibcon#ireg 8 cls_cnt 0 2006.224.07:50:12.54#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.224.07:50:12.54#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.224.07:50:12.54#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.224.07:50:12.54#ibcon#enter wrdev, iclass 24, count 0 2006.224.07:50:12.54#ibcon#first serial, iclass 24, count 0 2006.224.07:50:12.54#ibcon#enter sib2, iclass 24, count 0 2006.224.07:50:12.54#ibcon#flushed, iclass 24, count 0 2006.224.07:50:12.54#ibcon#about to write, iclass 24, count 0 2006.224.07:50:12.54#ibcon#wrote, iclass 24, count 0 2006.224.07:50:12.54#ibcon#about to read 3, iclass 24, count 0 2006.224.07:50:12.56#ibcon#read 3, iclass 24, count 0 2006.224.07:50:12.56#ibcon#about to read 4, iclass 24, count 0 2006.224.07:50:12.56#ibcon#read 4, iclass 24, count 0 2006.224.07:50:12.56#ibcon#about to read 5, iclass 24, count 0 2006.224.07:50:12.56#ibcon#read 5, iclass 24, count 0 2006.224.07:50:12.56#ibcon#about to read 6, iclass 24, count 0 2006.224.07:50:12.56#ibcon#read 6, iclass 24, count 0 2006.224.07:50:12.56#ibcon#end of sib2, iclass 24, count 0 2006.224.07:50:12.56#ibcon#*mode == 0, iclass 24, count 0 2006.224.07:50:12.56#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.224.07:50:12.56#ibcon#[25=BW32\r\n] 2006.224.07:50:12.56#ibcon#*before write, iclass 24, count 0 2006.224.07:50:12.56#ibcon#enter sib2, iclass 24, count 0 2006.224.07:50:12.56#ibcon#flushed, iclass 24, count 0 2006.224.07:50:12.56#ibcon#about to write, iclass 24, count 0 2006.224.07:50:12.56#ibcon#wrote, iclass 24, count 0 2006.224.07:50:12.56#ibcon#about to read 3, iclass 24, count 0 2006.224.07:50:12.59#ibcon#read 3, iclass 24, count 0 2006.224.07:50:12.59#ibcon#about to read 4, iclass 24, count 0 2006.224.07:50:12.59#ibcon#read 4, iclass 24, count 0 2006.224.07:50:12.59#ibcon#about to read 5, iclass 24, count 0 2006.224.07:50:12.59#ibcon#read 5, iclass 24, count 0 2006.224.07:50:12.59#ibcon#about to read 6, iclass 24, count 0 2006.224.07:50:12.59#ibcon#read 6, iclass 24, count 0 2006.224.07:50:12.59#ibcon#end of sib2, iclass 24, count 0 2006.224.07:50:12.59#ibcon#*after write, iclass 24, count 0 2006.224.07:50:12.59#ibcon#*before return 0, iclass 24, count 0 2006.224.07:50:12.59#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.224.07:50:12.59#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.224.07:50:12.59#ibcon#about to clear, iclass 24 cls_cnt 0 2006.224.07:50:12.59#ibcon#cleared, iclass 24 cls_cnt 0 2006.224.07:50:12.59$vc4f8/vbbw=wide 2006.224.07:50:12.59#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.224.07:50:12.59#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.224.07:50:12.59#ibcon#ireg 8 cls_cnt 0 2006.224.07:50:12.59#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.224.07:50:12.66#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.224.07:50:12.66#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.224.07:50:12.66#ibcon#enter wrdev, iclass 26, count 0 2006.224.07:50:12.66#ibcon#first serial, iclass 26, count 0 2006.224.07:50:12.66#ibcon#enter sib2, iclass 26, count 0 2006.224.07:50:12.66#ibcon#flushed, iclass 26, count 0 2006.224.07:50:12.66#ibcon#about to write, iclass 26, count 0 2006.224.07:50:12.66#ibcon#wrote, iclass 26, count 0 2006.224.07:50:12.66#ibcon#about to read 3, iclass 26, count 0 2006.224.07:50:12.68#ibcon#read 3, iclass 26, count 0 2006.224.07:50:12.68#ibcon#about to read 4, iclass 26, count 0 2006.224.07:50:12.68#ibcon#read 4, iclass 26, count 0 2006.224.07:50:12.68#ibcon#about to read 5, iclass 26, count 0 2006.224.07:50:12.68#ibcon#read 5, iclass 26, count 0 2006.224.07:50:12.68#ibcon#about to read 6, iclass 26, count 0 2006.224.07:50:12.68#ibcon#read 6, iclass 26, count 0 2006.224.07:50:12.68#ibcon#end of sib2, iclass 26, count 0 2006.224.07:50:12.68#ibcon#*mode == 0, iclass 26, count 0 2006.224.07:50:12.68#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.224.07:50:12.68#ibcon#[27=BW32\r\n] 2006.224.07:50:12.68#ibcon#*before write, iclass 26, count 0 2006.224.07:50:12.68#ibcon#enter sib2, iclass 26, count 0 2006.224.07:50:12.68#ibcon#flushed, iclass 26, count 0 2006.224.07:50:12.68#ibcon#about to write, iclass 26, count 0 2006.224.07:50:12.68#ibcon#wrote, iclass 26, count 0 2006.224.07:50:12.68#ibcon#about to read 3, iclass 26, count 0 2006.224.07:50:12.71#ibcon#read 3, iclass 26, count 0 2006.224.07:50:12.71#ibcon#about to read 4, iclass 26, count 0 2006.224.07:50:12.71#ibcon#read 4, iclass 26, count 0 2006.224.07:50:12.71#ibcon#about to read 5, iclass 26, count 0 2006.224.07:50:12.71#ibcon#read 5, iclass 26, count 0 2006.224.07:50:12.71#ibcon#about to read 6, iclass 26, count 0 2006.224.07:50:12.71#ibcon#read 6, iclass 26, count 0 2006.224.07:50:12.71#ibcon#end of sib2, iclass 26, count 0 2006.224.07:50:12.71#ibcon#*after write, iclass 26, count 0 2006.224.07:50:12.71#ibcon#*before return 0, iclass 26, count 0 2006.224.07:50:12.71#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.224.07:50:12.71#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.224.07:50:12.71#ibcon#about to clear, iclass 26 cls_cnt 0 2006.224.07:50:12.71#ibcon#cleared, iclass 26 cls_cnt 0 2006.224.07:50:12.71$4f8m12a/ifd4f 2006.224.07:50:12.71$ifd4f/lo= 2006.224.07:50:12.71$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.224.07:50:12.71$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.224.07:50:12.71$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.224.07:50:12.71$ifd4f/patch= 2006.224.07:50:12.71$ifd4f/patch=lo1,a1,a2,a3,a4 2006.224.07:50:12.71$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.224.07:50:12.71$ifd4f/patch=lo3,a5,a6,a7,a8 2006.224.07:50:12.71$4f8m12a/"form=m,16.000,1:2 2006.224.07:50:12.71$4f8m12a/"tpicd 2006.224.07:50:12.71$4f8m12a/echo=off 2006.224.07:50:12.71$4f8m12a/xlog=off 2006.224.07:50:12.71:!2006.224.07:50:40 2006.224.07:50:21.14#trakl#Source acquired 2006.224.07:50:21.14#flagr#flagr/antenna,acquired 2006.224.07:50:40.00:preob 2006.224.07:50:40.14/onsource/TRACKING 2006.224.07:50:40.14:!2006.224.07:50:50 2006.224.07:50:50.00:data_valid=on 2006.224.07:50:50.00:midob 2006.224.07:50:51.14/onsource/TRACKING 2006.224.07:50:51.14/wx/23.60,1004.0,100 2006.224.07:50:51.22/cable/+6.4324E-03 2006.224.07:50:52.31/va/01,08,usb,yes,50,52 2006.224.07:50:52.31/va/02,07,usb,yes,50,52 2006.224.07:50:52.31/va/03,06,usb,yes,53,53 2006.224.07:50:52.31/va/04,07,usb,yes,53,56 2006.224.07:50:52.31/va/05,07,usb,yes,62,65 2006.224.07:50:52.31/va/06,06,usb,yes,61,61 2006.224.07:50:52.31/va/07,06,usb,yes,62,61 2006.224.07:50:52.31/va/08,07,usb,yes,59,58 2006.224.07:50:52.54/valo/01,532.99,yes,locked 2006.224.07:50:52.54/valo/02,572.99,yes,locked 2006.224.07:50:52.54/valo/03,672.99,yes,locked 2006.224.07:50:52.54/valo/04,832.99,yes,locked 2006.224.07:50:52.54/valo/05,652.99,yes,locked 2006.224.07:50:52.54/valo/06,772.99,yes,locked 2006.224.07:50:52.54/valo/07,832.99,yes,locked 2006.224.07:50:52.54/valo/08,852.99,yes,locked 2006.224.07:50:53.63/vb/01,04,usb,yes,37,35 2006.224.07:50:53.63/vb/02,04,usb,yes,39,41 2006.224.07:50:53.63/vb/03,04,usb,yes,35,39 2006.224.07:50:53.63/vb/04,04,usb,yes,36,36 2006.224.07:50:53.63/vb/05,04,usb,yes,34,39 2006.224.07:50:53.63/vb/06,04,usb,yes,36,39 2006.224.07:50:53.63/vb/07,04,usb,yes,38,38 2006.224.07:50:53.63/vb/08,04,usb,yes,35,39 2006.224.07:50:53.87/vblo/01,632.99,yes,locked 2006.224.07:50:53.87/vblo/02,640.99,yes,locked 2006.224.07:50:53.87/vblo/03,656.99,yes,locked 2006.224.07:50:53.87/vblo/04,712.99,yes,locked 2006.224.07:50:53.87/vblo/05,744.99,yes,locked 2006.224.07:50:53.87/vblo/06,752.99,yes,locked 2006.224.07:50:53.87/vblo/07,734.99,yes,locked 2006.224.07:50:53.87/vblo/08,744.99,yes,locked 2006.224.07:50:54.02/vabw/8 2006.224.07:50:54.17/vbbw/8 2006.224.07:50:54.26/xfe/off,on,15.5 2006.224.07:50:54.64/ifatt/23,28,28,28 2006.224.07:50:55.07/fmout-gps/S +4.27E-07 2006.224.07:50:55.11:!2006.224.07:51:50 2006.224.07:51:50.00:data_valid=off 2006.224.07:51:50.00:postob 2006.224.07:51:50.14/cable/+6.4351E-03 2006.224.07:51:50.14/wx/23.61,1004.0,100 2006.224.07:51:51.07/fmout-gps/S +4.28E-07 2006.224.07:51:51.07:scan_name=224-0752,k06224,60 2006.224.07:51:51.07:source=0955+476,095819.67,472507.8,2000.0,ccw 2006.224.07:51:51.14#flagr#flagr/antenna,new-source 2006.224.07:51:52.14:checkk5 2006.224.07:51:52.52/chk_autoobs//k5ts1/ autoobs is running! 2006.224.07:51:52.90/chk_autoobs//k5ts2/ autoobs is running! 2006.224.07:51:53.27/chk_autoobs//k5ts3/ autoobs is running! 2006.224.07:51:53.65/chk_autoobs//k5ts4/ autoobs is running! 2006.224.07:51:54.01/chk_obsdata//k5ts1/T2240750??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.224.07:51:54.38/chk_obsdata//k5ts2/T2240750??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.224.07:51:54.74/chk_obsdata//k5ts3/T2240750??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.224.07:51:55.11/chk_obsdata//k5ts4/T2240750??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.224.07:51:55.80/k5log//k5ts1_log_newline 2006.224.07:51:56.48/k5log//k5ts2_log_newline 2006.224.07:51:57.17/k5log//k5ts3_log_newline 2006.224.07:51:57.85/k5log//k5ts4_log_newline 2006.224.07:51:57.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.224.07:51:57.87:4f8m12a=1 2006.224.07:51:57.87$4f8m12a/echo=on 2006.224.07:51:57.87$4f8m12a/pcalon 2006.224.07:51:57.87$pcalon/"no phase cal control is implemented here 2006.224.07:51:57.87$4f8m12a/"tpicd=stop 2006.224.07:51:57.87$4f8m12a/vc4f8 2006.224.07:51:57.87$vc4f8/valo=1,532.99 2006.224.07:51:57.87#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.224.07:51:57.87#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.224.07:51:57.87#ibcon#ireg 17 cls_cnt 0 2006.224.07:51:57.88#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.224.07:51:57.88#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.224.07:51:57.88#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.224.07:51:57.88#ibcon#enter wrdev, iclass 33, count 0 2006.224.07:51:57.88#ibcon#first serial, iclass 33, count 0 2006.224.07:51:57.88#ibcon#enter sib2, iclass 33, count 0 2006.224.07:51:57.88#ibcon#flushed, iclass 33, count 0 2006.224.07:51:57.88#ibcon#about to write, iclass 33, count 0 2006.224.07:51:57.88#ibcon#wrote, iclass 33, count 0 2006.224.07:51:57.88#ibcon#about to read 3, iclass 33, count 0 2006.224.07:51:57.91#ibcon#read 3, iclass 33, count 0 2006.224.07:51:57.91#ibcon#about to read 4, iclass 33, count 0 2006.224.07:51:57.91#ibcon#read 4, iclass 33, count 0 2006.224.07:51:57.91#ibcon#about to read 5, iclass 33, count 0 2006.224.07:51:57.91#ibcon#read 5, iclass 33, count 0 2006.224.07:51:57.92#ibcon#about to read 6, iclass 33, count 0 2006.224.07:51:57.92#ibcon#read 6, iclass 33, count 0 2006.224.07:51:57.92#ibcon#end of sib2, iclass 33, count 0 2006.224.07:51:57.92#ibcon#*mode == 0, iclass 33, count 0 2006.224.07:51:57.92#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.224.07:51:57.92#ibcon#[26=FRQ=01,532.99\r\n] 2006.224.07:51:57.92#ibcon#*before write, iclass 33, count 0 2006.224.07:51:57.92#ibcon#enter sib2, iclass 33, count 0 2006.224.07:51:57.92#ibcon#flushed, iclass 33, count 0 2006.224.07:51:57.92#ibcon#about to write, iclass 33, count 0 2006.224.07:51:57.92#ibcon#wrote, iclass 33, count 0 2006.224.07:51:57.92#ibcon#about to read 3, iclass 33, count 0 2006.224.07:51:57.96#ibcon#read 3, iclass 33, count 0 2006.224.07:51:57.96#ibcon#about to read 4, iclass 33, count 0 2006.224.07:51:57.96#ibcon#read 4, iclass 33, count 0 2006.224.07:51:57.96#ibcon#about to read 5, iclass 33, count 0 2006.224.07:51:57.96#ibcon#read 5, iclass 33, count 0 2006.224.07:51:57.96#ibcon#about to read 6, iclass 33, count 0 2006.224.07:51:57.96#ibcon#read 6, iclass 33, count 0 2006.224.07:51:57.96#ibcon#end of sib2, iclass 33, count 0 2006.224.07:51:57.96#ibcon#*after write, iclass 33, count 0 2006.224.07:51:57.96#ibcon#*before return 0, iclass 33, count 0 2006.224.07:51:57.96#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.224.07:51:57.96#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.224.07:51:57.96#ibcon#about to clear, iclass 33 cls_cnt 0 2006.224.07:51:57.96#ibcon#cleared, iclass 33 cls_cnt 0 2006.224.07:51:57.96$vc4f8/va=1,8 2006.224.07:51:57.96#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.224.07:51:57.96#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.224.07:51:57.96#ibcon#ireg 11 cls_cnt 2 2006.224.07:51:57.96#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.224.07:51:57.96#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.224.07:51:57.96#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.224.07:51:57.96#ibcon#enter wrdev, iclass 35, count 2 2006.224.07:51:57.96#ibcon#first serial, iclass 35, count 2 2006.224.07:51:57.96#ibcon#enter sib2, iclass 35, count 2 2006.224.07:51:57.96#ibcon#flushed, iclass 35, count 2 2006.224.07:51:57.96#ibcon#about to write, iclass 35, count 2 2006.224.07:51:57.96#ibcon#wrote, iclass 35, count 2 2006.224.07:51:57.96#ibcon#about to read 3, iclass 35, count 2 2006.224.07:51:57.98#ibcon#read 3, iclass 35, count 2 2006.224.07:51:57.98#ibcon#about to read 4, iclass 35, count 2 2006.224.07:51:57.98#ibcon#read 4, iclass 35, count 2 2006.224.07:51:57.98#ibcon#about to read 5, iclass 35, count 2 2006.224.07:51:57.98#ibcon#read 5, iclass 35, count 2 2006.224.07:51:57.98#ibcon#about to read 6, iclass 35, count 2 2006.224.07:51:57.98#ibcon#read 6, iclass 35, count 2 2006.224.07:51:57.98#ibcon#end of sib2, iclass 35, count 2 2006.224.07:51:57.98#ibcon#*mode == 0, iclass 35, count 2 2006.224.07:51:57.98#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.224.07:51:57.98#ibcon#[25=AT01-08\r\n] 2006.224.07:51:57.98#ibcon#*before write, iclass 35, count 2 2006.224.07:51:57.98#ibcon#enter sib2, iclass 35, count 2 2006.224.07:51:57.98#ibcon#flushed, iclass 35, count 2 2006.224.07:51:57.98#ibcon#about to write, iclass 35, count 2 2006.224.07:51:57.98#ibcon#wrote, iclass 35, count 2 2006.224.07:51:57.98#ibcon#about to read 3, iclass 35, count 2 2006.224.07:51:58.01#ibcon#read 3, iclass 35, count 2 2006.224.07:51:58.01#ibcon#about to read 4, iclass 35, count 2 2006.224.07:51:58.01#ibcon#read 4, iclass 35, count 2 2006.224.07:51:58.01#ibcon#about to read 5, iclass 35, count 2 2006.224.07:51:58.01#ibcon#read 5, iclass 35, count 2 2006.224.07:51:58.01#ibcon#about to read 6, iclass 35, count 2 2006.224.07:51:58.01#ibcon#read 6, iclass 35, count 2 2006.224.07:51:58.01#ibcon#end of sib2, iclass 35, count 2 2006.224.07:51:58.01#ibcon#*after write, iclass 35, count 2 2006.224.07:51:58.01#ibcon#*before return 0, iclass 35, count 2 2006.224.07:51:58.01#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.224.07:51:58.01#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.224.07:51:58.01#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.224.07:51:58.01#ibcon#ireg 7 cls_cnt 0 2006.224.07:51:58.01#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.224.07:51:58.13#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.224.07:51:58.13#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.224.07:51:58.13#ibcon#enter wrdev, iclass 35, count 0 2006.224.07:51:58.13#ibcon#first serial, iclass 35, count 0 2006.224.07:51:58.13#ibcon#enter sib2, iclass 35, count 0 2006.224.07:51:58.13#ibcon#flushed, iclass 35, count 0 2006.224.07:51:58.13#ibcon#about to write, iclass 35, count 0 2006.224.07:51:58.13#ibcon#wrote, iclass 35, count 0 2006.224.07:51:58.13#ibcon#about to read 3, iclass 35, count 0 2006.224.07:51:58.15#ibcon#read 3, iclass 35, count 0 2006.224.07:51:58.15#ibcon#about to read 4, iclass 35, count 0 2006.224.07:51:58.15#ibcon#read 4, iclass 35, count 0 2006.224.07:51:58.15#ibcon#about to read 5, iclass 35, count 0 2006.224.07:51:58.15#ibcon#read 5, iclass 35, count 0 2006.224.07:51:58.15#ibcon#about to read 6, iclass 35, count 0 2006.224.07:51:58.15#ibcon#read 6, iclass 35, count 0 2006.224.07:51:58.15#ibcon#end of sib2, iclass 35, count 0 2006.224.07:51:58.15#ibcon#*mode == 0, iclass 35, count 0 2006.224.07:51:58.15#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.224.07:51:58.15#ibcon#[25=USB\r\n] 2006.224.07:51:58.15#ibcon#*before write, iclass 35, count 0 2006.224.07:51:58.15#ibcon#enter sib2, iclass 35, count 0 2006.224.07:51:58.15#ibcon#flushed, iclass 35, count 0 2006.224.07:51:58.15#ibcon#about to write, iclass 35, count 0 2006.224.07:51:58.15#ibcon#wrote, iclass 35, count 0 2006.224.07:51:58.15#ibcon#about to read 3, iclass 35, count 0 2006.224.07:51:58.18#ibcon#read 3, iclass 35, count 0 2006.224.07:51:58.18#ibcon#about to read 4, iclass 35, count 0 2006.224.07:51:58.18#ibcon#read 4, iclass 35, count 0 2006.224.07:51:58.18#ibcon#about to read 5, iclass 35, count 0 2006.224.07:51:58.18#ibcon#read 5, iclass 35, count 0 2006.224.07:51:58.18#ibcon#about to read 6, iclass 35, count 0 2006.224.07:51:58.18#ibcon#read 6, iclass 35, count 0 2006.224.07:51:58.18#ibcon#end of sib2, iclass 35, count 0 2006.224.07:51:58.18#ibcon#*after write, iclass 35, count 0 2006.224.07:51:58.18#ibcon#*before return 0, iclass 35, count 0 2006.224.07:51:58.18#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.224.07:51:58.18#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.224.07:51:58.18#ibcon#about to clear, iclass 35 cls_cnt 0 2006.224.07:51:58.18#ibcon#cleared, iclass 35 cls_cnt 0 2006.224.07:51:58.18$vc4f8/valo=2,572.99 2006.224.07:51:58.18#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.224.07:51:58.18#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.224.07:51:58.18#ibcon#ireg 17 cls_cnt 0 2006.224.07:51:58.18#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.224.07:51:58.18#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.224.07:51:58.18#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.224.07:51:58.18#ibcon#enter wrdev, iclass 37, count 0 2006.224.07:51:58.18#ibcon#first serial, iclass 37, count 0 2006.224.07:51:58.18#ibcon#enter sib2, iclass 37, count 0 2006.224.07:51:58.18#ibcon#flushed, iclass 37, count 0 2006.224.07:51:58.18#ibcon#about to write, iclass 37, count 0 2006.224.07:51:58.18#ibcon#wrote, iclass 37, count 0 2006.224.07:51:58.18#ibcon#about to read 3, iclass 37, count 0 2006.224.07:51:58.21#ibcon#read 3, iclass 37, count 0 2006.224.07:51:58.21#ibcon#about to read 4, iclass 37, count 0 2006.224.07:51:58.21#ibcon#read 4, iclass 37, count 0 2006.224.07:51:58.21#ibcon#about to read 5, iclass 37, count 0 2006.224.07:51:58.21#ibcon#read 5, iclass 37, count 0 2006.224.07:51:58.21#ibcon#about to read 6, iclass 37, count 0 2006.224.07:51:58.21#ibcon#read 6, iclass 37, count 0 2006.224.07:51:58.21#ibcon#end of sib2, iclass 37, count 0 2006.224.07:51:58.21#ibcon#*mode == 0, iclass 37, count 0 2006.224.07:51:58.21#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.224.07:51:58.21#ibcon#[26=FRQ=02,572.99\r\n] 2006.224.07:51:58.21#ibcon#*before write, iclass 37, count 0 2006.224.07:51:58.21#ibcon#enter sib2, iclass 37, count 0 2006.224.07:51:58.21#ibcon#flushed, iclass 37, count 0 2006.224.07:51:58.21#ibcon#about to write, iclass 37, count 0 2006.224.07:51:58.21#ibcon#wrote, iclass 37, count 0 2006.224.07:51:58.21#ibcon#about to read 3, iclass 37, count 0 2006.224.07:51:58.25#ibcon#read 3, iclass 37, count 0 2006.224.07:51:58.25#ibcon#about to read 4, iclass 37, count 0 2006.224.07:51:58.25#ibcon#read 4, iclass 37, count 0 2006.224.07:51:58.25#ibcon#about to read 5, iclass 37, count 0 2006.224.07:51:58.25#ibcon#read 5, iclass 37, count 0 2006.224.07:51:58.25#ibcon#about to read 6, iclass 37, count 0 2006.224.07:51:58.25#ibcon#read 6, iclass 37, count 0 2006.224.07:51:58.25#ibcon#end of sib2, iclass 37, count 0 2006.224.07:51:58.25#ibcon#*after write, iclass 37, count 0 2006.224.07:51:58.25#ibcon#*before return 0, iclass 37, count 0 2006.224.07:51:58.25#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.224.07:51:58.25#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.224.07:51:58.25#ibcon#about to clear, iclass 37 cls_cnt 0 2006.224.07:51:58.25#ibcon#cleared, iclass 37 cls_cnt 0 2006.224.07:51:58.25$vc4f8/va=2,7 2006.224.07:51:58.25#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.224.07:51:58.25#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.224.07:51:58.25#ibcon#ireg 11 cls_cnt 2 2006.224.07:51:58.25#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.224.07:51:58.30#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.224.07:51:58.30#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.224.07:51:58.30#ibcon#enter wrdev, iclass 39, count 2 2006.224.07:51:58.30#ibcon#first serial, iclass 39, count 2 2006.224.07:51:58.30#ibcon#enter sib2, iclass 39, count 2 2006.224.07:51:58.30#ibcon#flushed, iclass 39, count 2 2006.224.07:51:58.30#ibcon#about to write, iclass 39, count 2 2006.224.07:51:58.30#ibcon#wrote, iclass 39, count 2 2006.224.07:51:58.30#ibcon#about to read 3, iclass 39, count 2 2006.224.07:51:58.32#ibcon#read 3, iclass 39, count 2 2006.224.07:51:58.32#ibcon#about to read 4, iclass 39, count 2 2006.224.07:51:58.32#ibcon#read 4, iclass 39, count 2 2006.224.07:51:58.32#ibcon#about to read 5, iclass 39, count 2 2006.224.07:51:58.32#ibcon#read 5, iclass 39, count 2 2006.224.07:51:58.32#ibcon#about to read 6, iclass 39, count 2 2006.224.07:51:58.32#ibcon#read 6, iclass 39, count 2 2006.224.07:51:58.32#ibcon#end of sib2, iclass 39, count 2 2006.224.07:51:58.32#ibcon#*mode == 0, iclass 39, count 2 2006.224.07:51:58.32#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.224.07:51:58.32#ibcon#[25=AT02-07\r\n] 2006.224.07:51:58.32#ibcon#*before write, iclass 39, count 2 2006.224.07:51:58.32#ibcon#enter sib2, iclass 39, count 2 2006.224.07:51:58.32#ibcon#flushed, iclass 39, count 2 2006.224.07:51:58.32#ibcon#about to write, iclass 39, count 2 2006.224.07:51:58.32#ibcon#wrote, iclass 39, count 2 2006.224.07:51:58.32#ibcon#about to read 3, iclass 39, count 2 2006.224.07:51:58.35#ibcon#read 3, iclass 39, count 2 2006.224.07:51:58.35#ibcon#about to read 4, iclass 39, count 2 2006.224.07:51:58.35#ibcon#read 4, iclass 39, count 2 2006.224.07:51:58.35#ibcon#about to read 5, iclass 39, count 2 2006.224.07:51:58.35#ibcon#read 5, iclass 39, count 2 2006.224.07:51:58.35#ibcon#about to read 6, iclass 39, count 2 2006.224.07:51:58.35#ibcon#read 6, iclass 39, count 2 2006.224.07:51:58.35#ibcon#end of sib2, iclass 39, count 2 2006.224.07:51:58.35#ibcon#*after write, iclass 39, count 2 2006.224.07:51:58.35#ibcon#*before return 0, iclass 39, count 2 2006.224.07:51:58.35#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.224.07:51:58.35#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.224.07:51:58.35#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.224.07:51:58.35#ibcon#ireg 7 cls_cnt 0 2006.224.07:51:58.35#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.224.07:51:58.47#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.224.07:51:58.47#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.224.07:51:58.47#ibcon#enter wrdev, iclass 39, count 0 2006.224.07:51:58.47#ibcon#first serial, iclass 39, count 0 2006.224.07:51:58.47#ibcon#enter sib2, iclass 39, count 0 2006.224.07:51:58.47#ibcon#flushed, iclass 39, count 0 2006.224.07:51:58.47#ibcon#about to write, iclass 39, count 0 2006.224.07:51:58.47#ibcon#wrote, iclass 39, count 0 2006.224.07:51:58.47#ibcon#about to read 3, iclass 39, count 0 2006.224.07:51:58.49#ibcon#read 3, iclass 39, count 0 2006.224.07:51:58.49#ibcon#about to read 4, iclass 39, count 0 2006.224.07:51:58.49#ibcon#read 4, iclass 39, count 0 2006.224.07:51:58.49#ibcon#about to read 5, iclass 39, count 0 2006.224.07:51:58.49#ibcon#read 5, iclass 39, count 0 2006.224.07:51:58.49#ibcon#about to read 6, iclass 39, count 0 2006.224.07:51:58.49#ibcon#read 6, iclass 39, count 0 2006.224.07:51:58.49#ibcon#end of sib2, iclass 39, count 0 2006.224.07:51:58.49#ibcon#*mode == 0, iclass 39, count 0 2006.224.07:51:58.49#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.224.07:51:58.49#ibcon#[25=USB\r\n] 2006.224.07:51:58.49#ibcon#*before write, iclass 39, count 0 2006.224.07:51:58.49#ibcon#enter sib2, iclass 39, count 0 2006.224.07:51:58.49#ibcon#flushed, iclass 39, count 0 2006.224.07:51:58.49#ibcon#about to write, iclass 39, count 0 2006.224.07:51:58.49#ibcon#wrote, iclass 39, count 0 2006.224.07:51:58.49#ibcon#about to read 3, iclass 39, count 0 2006.224.07:51:58.52#ibcon#read 3, iclass 39, count 0 2006.224.07:51:58.52#ibcon#about to read 4, iclass 39, count 0 2006.224.07:51:58.52#ibcon#read 4, iclass 39, count 0 2006.224.07:51:58.52#ibcon#about to read 5, iclass 39, count 0 2006.224.07:51:58.52#ibcon#read 5, iclass 39, count 0 2006.224.07:51:58.52#ibcon#about to read 6, iclass 39, count 0 2006.224.07:51:58.52#ibcon#read 6, iclass 39, count 0 2006.224.07:51:58.52#ibcon#end of sib2, iclass 39, count 0 2006.224.07:51:58.52#ibcon#*after write, iclass 39, count 0 2006.224.07:51:58.52#ibcon#*before return 0, iclass 39, count 0 2006.224.07:51:58.52#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.224.07:51:58.52#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.224.07:51:58.52#ibcon#about to clear, iclass 39 cls_cnt 0 2006.224.07:51:58.52#ibcon#cleared, iclass 39 cls_cnt 0 2006.224.07:51:58.52$vc4f8/valo=3,672.99 2006.224.07:51:58.52#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.224.07:51:58.52#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.224.07:51:58.52#ibcon#ireg 17 cls_cnt 0 2006.224.07:51:58.52#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.224.07:51:58.52#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.224.07:51:58.52#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.224.07:51:58.52#ibcon#enter wrdev, iclass 3, count 0 2006.224.07:51:58.52#ibcon#first serial, iclass 3, count 0 2006.224.07:51:58.52#ibcon#enter sib2, iclass 3, count 0 2006.224.07:51:58.52#ibcon#flushed, iclass 3, count 0 2006.224.07:51:58.52#ibcon#about to write, iclass 3, count 0 2006.224.07:51:58.52#ibcon#wrote, iclass 3, count 0 2006.224.07:51:58.52#ibcon#about to read 3, iclass 3, count 0 2006.224.07:51:58.55#ibcon#read 3, iclass 3, count 0 2006.224.07:51:58.55#ibcon#about to read 4, iclass 3, count 0 2006.224.07:51:58.55#ibcon#read 4, iclass 3, count 0 2006.224.07:51:58.55#ibcon#about to read 5, iclass 3, count 0 2006.224.07:51:58.55#ibcon#read 5, iclass 3, count 0 2006.224.07:51:58.55#ibcon#about to read 6, iclass 3, count 0 2006.224.07:51:58.55#ibcon#read 6, iclass 3, count 0 2006.224.07:51:58.55#ibcon#end of sib2, iclass 3, count 0 2006.224.07:51:58.55#ibcon#*mode == 0, iclass 3, count 0 2006.224.07:51:58.55#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.224.07:51:58.55#ibcon#[26=FRQ=03,672.99\r\n] 2006.224.07:51:58.55#ibcon#*before write, iclass 3, count 0 2006.224.07:51:58.55#ibcon#enter sib2, iclass 3, count 0 2006.224.07:51:58.55#ibcon#flushed, iclass 3, count 0 2006.224.07:51:58.55#ibcon#about to write, iclass 3, count 0 2006.224.07:51:58.55#ibcon#wrote, iclass 3, count 0 2006.224.07:51:58.55#ibcon#about to read 3, iclass 3, count 0 2006.224.07:51:58.59#ibcon#read 3, iclass 3, count 0 2006.224.07:51:58.59#ibcon#about to read 4, iclass 3, count 0 2006.224.07:51:58.59#ibcon#read 4, iclass 3, count 0 2006.224.07:51:58.59#ibcon#about to read 5, iclass 3, count 0 2006.224.07:51:58.59#ibcon#read 5, iclass 3, count 0 2006.224.07:51:58.59#ibcon#about to read 6, iclass 3, count 0 2006.224.07:51:58.59#ibcon#read 6, iclass 3, count 0 2006.224.07:51:58.59#ibcon#end of sib2, iclass 3, count 0 2006.224.07:51:58.59#ibcon#*after write, iclass 3, count 0 2006.224.07:51:58.59#ibcon#*before return 0, iclass 3, count 0 2006.224.07:51:58.59#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.224.07:51:58.59#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.224.07:51:58.59#ibcon#about to clear, iclass 3 cls_cnt 0 2006.224.07:51:58.59#ibcon#cleared, iclass 3 cls_cnt 0 2006.224.07:51:58.59$vc4f8/va=3,6 2006.224.07:51:58.59#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.224.07:51:58.59#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.224.07:51:58.59#ibcon#ireg 11 cls_cnt 2 2006.224.07:51:58.59#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.224.07:51:58.64#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.224.07:51:58.64#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.224.07:51:58.64#ibcon#enter wrdev, iclass 5, count 2 2006.224.07:51:58.64#ibcon#first serial, iclass 5, count 2 2006.224.07:51:58.64#ibcon#enter sib2, iclass 5, count 2 2006.224.07:51:58.64#ibcon#flushed, iclass 5, count 2 2006.224.07:51:58.64#ibcon#about to write, iclass 5, count 2 2006.224.07:51:58.64#ibcon#wrote, iclass 5, count 2 2006.224.07:51:58.64#ibcon#about to read 3, iclass 5, count 2 2006.224.07:51:58.66#ibcon#read 3, iclass 5, count 2 2006.224.07:51:58.66#ibcon#about to read 4, iclass 5, count 2 2006.224.07:51:58.66#ibcon#read 4, iclass 5, count 2 2006.224.07:51:58.66#ibcon#about to read 5, iclass 5, count 2 2006.224.07:51:58.66#ibcon#read 5, iclass 5, count 2 2006.224.07:51:58.66#ibcon#about to read 6, iclass 5, count 2 2006.224.07:51:58.66#ibcon#read 6, iclass 5, count 2 2006.224.07:51:58.66#ibcon#end of sib2, iclass 5, count 2 2006.224.07:51:58.66#ibcon#*mode == 0, iclass 5, count 2 2006.224.07:51:58.66#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.224.07:51:58.66#ibcon#[25=AT03-06\r\n] 2006.224.07:51:58.66#ibcon#*before write, iclass 5, count 2 2006.224.07:51:58.66#ibcon#enter sib2, iclass 5, count 2 2006.224.07:51:58.66#ibcon#flushed, iclass 5, count 2 2006.224.07:51:58.66#ibcon#about to write, iclass 5, count 2 2006.224.07:51:58.66#ibcon#wrote, iclass 5, count 2 2006.224.07:51:58.66#ibcon#about to read 3, iclass 5, count 2 2006.224.07:51:58.69#ibcon#read 3, iclass 5, count 2 2006.224.07:51:58.69#ibcon#about to read 4, iclass 5, count 2 2006.224.07:51:58.69#ibcon#read 4, iclass 5, count 2 2006.224.07:51:58.69#ibcon#about to read 5, iclass 5, count 2 2006.224.07:51:58.69#ibcon#read 5, iclass 5, count 2 2006.224.07:51:58.69#ibcon#about to read 6, iclass 5, count 2 2006.224.07:51:58.69#ibcon#read 6, iclass 5, count 2 2006.224.07:51:58.69#ibcon#end of sib2, iclass 5, count 2 2006.224.07:51:58.69#ibcon#*after write, iclass 5, count 2 2006.224.07:51:58.69#ibcon#*before return 0, iclass 5, count 2 2006.224.07:51:58.69#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.224.07:51:58.69#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.224.07:51:58.69#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.224.07:51:58.69#ibcon#ireg 7 cls_cnt 0 2006.224.07:51:58.69#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.224.07:51:58.81#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.224.07:51:58.81#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.224.07:51:58.81#ibcon#enter wrdev, iclass 5, count 0 2006.224.07:51:58.81#ibcon#first serial, iclass 5, count 0 2006.224.07:51:58.81#ibcon#enter sib2, iclass 5, count 0 2006.224.07:51:58.81#ibcon#flushed, iclass 5, count 0 2006.224.07:51:58.81#ibcon#about to write, iclass 5, count 0 2006.224.07:51:58.81#ibcon#wrote, iclass 5, count 0 2006.224.07:51:58.81#ibcon#about to read 3, iclass 5, count 0 2006.224.07:51:58.83#ibcon#read 3, iclass 5, count 0 2006.224.07:51:58.83#ibcon#about to read 4, iclass 5, count 0 2006.224.07:51:58.83#ibcon#read 4, iclass 5, count 0 2006.224.07:51:58.83#ibcon#about to read 5, iclass 5, count 0 2006.224.07:51:58.83#ibcon#read 5, iclass 5, count 0 2006.224.07:51:58.83#ibcon#about to read 6, iclass 5, count 0 2006.224.07:51:58.83#ibcon#read 6, iclass 5, count 0 2006.224.07:51:58.83#ibcon#end of sib2, iclass 5, count 0 2006.224.07:51:58.83#ibcon#*mode == 0, iclass 5, count 0 2006.224.07:51:58.83#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.224.07:51:58.83#ibcon#[25=USB\r\n] 2006.224.07:51:58.83#ibcon#*before write, iclass 5, count 0 2006.224.07:51:58.83#ibcon#enter sib2, iclass 5, count 0 2006.224.07:51:58.83#ibcon#flushed, iclass 5, count 0 2006.224.07:51:58.83#ibcon#about to write, iclass 5, count 0 2006.224.07:51:58.83#ibcon#wrote, iclass 5, count 0 2006.224.07:51:58.83#ibcon#about to read 3, iclass 5, count 0 2006.224.07:51:58.86#ibcon#read 3, iclass 5, count 0 2006.224.07:51:58.86#ibcon#about to read 4, iclass 5, count 0 2006.224.07:51:58.86#ibcon#read 4, iclass 5, count 0 2006.224.07:51:58.86#ibcon#about to read 5, iclass 5, count 0 2006.224.07:51:58.86#ibcon#read 5, iclass 5, count 0 2006.224.07:51:58.86#ibcon#about to read 6, iclass 5, count 0 2006.224.07:51:58.86#ibcon#read 6, iclass 5, count 0 2006.224.07:51:58.86#ibcon#end of sib2, iclass 5, count 0 2006.224.07:51:58.86#ibcon#*after write, iclass 5, count 0 2006.224.07:51:58.86#ibcon#*before return 0, iclass 5, count 0 2006.224.07:51:58.86#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.224.07:51:58.86#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.224.07:51:58.86#ibcon#about to clear, iclass 5 cls_cnt 0 2006.224.07:51:58.86#ibcon#cleared, iclass 5 cls_cnt 0 2006.224.07:51:58.86$vc4f8/valo=4,832.99 2006.224.07:51:58.86#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.224.07:51:58.86#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.224.07:51:58.86#ibcon#ireg 17 cls_cnt 0 2006.224.07:51:58.86#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.224.07:51:58.86#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.224.07:51:58.86#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.224.07:51:58.86#ibcon#enter wrdev, iclass 7, count 0 2006.224.07:51:58.86#ibcon#first serial, iclass 7, count 0 2006.224.07:51:58.86#ibcon#enter sib2, iclass 7, count 0 2006.224.07:51:58.86#ibcon#flushed, iclass 7, count 0 2006.224.07:51:58.86#ibcon#about to write, iclass 7, count 0 2006.224.07:51:58.86#ibcon#wrote, iclass 7, count 0 2006.224.07:51:58.86#ibcon#about to read 3, iclass 7, count 0 2006.224.07:51:58.88#ibcon#read 3, iclass 7, count 0 2006.224.07:51:58.88#ibcon#about to read 4, iclass 7, count 0 2006.224.07:51:58.88#ibcon#read 4, iclass 7, count 0 2006.224.07:51:58.88#ibcon#about to read 5, iclass 7, count 0 2006.224.07:51:58.88#ibcon#read 5, iclass 7, count 0 2006.224.07:51:58.88#ibcon#about to read 6, iclass 7, count 0 2006.224.07:51:58.88#ibcon#read 6, iclass 7, count 0 2006.224.07:51:58.88#ibcon#end of sib2, iclass 7, count 0 2006.224.07:51:58.88#ibcon#*mode == 0, iclass 7, count 0 2006.224.07:51:58.88#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.224.07:51:58.88#ibcon#[26=FRQ=04,832.99\r\n] 2006.224.07:51:58.88#ibcon#*before write, iclass 7, count 0 2006.224.07:51:58.88#ibcon#enter sib2, iclass 7, count 0 2006.224.07:51:58.88#ibcon#flushed, iclass 7, count 0 2006.224.07:51:58.88#ibcon#about to write, iclass 7, count 0 2006.224.07:51:58.88#ibcon#wrote, iclass 7, count 0 2006.224.07:51:58.88#ibcon#about to read 3, iclass 7, count 0 2006.224.07:51:58.92#ibcon#read 3, iclass 7, count 0 2006.224.07:51:58.92#ibcon#about to read 4, iclass 7, count 0 2006.224.07:51:58.92#ibcon#read 4, iclass 7, count 0 2006.224.07:51:58.92#ibcon#about to read 5, iclass 7, count 0 2006.224.07:51:58.92#ibcon#read 5, iclass 7, count 0 2006.224.07:51:58.92#ibcon#about to read 6, iclass 7, count 0 2006.224.07:51:58.92#ibcon#read 6, iclass 7, count 0 2006.224.07:51:58.92#ibcon#end of sib2, iclass 7, count 0 2006.224.07:51:58.92#ibcon#*after write, iclass 7, count 0 2006.224.07:51:58.92#ibcon#*before return 0, iclass 7, count 0 2006.224.07:51:58.92#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.224.07:51:58.92#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.224.07:51:58.92#ibcon#about to clear, iclass 7 cls_cnt 0 2006.224.07:51:58.92#ibcon#cleared, iclass 7 cls_cnt 0 2006.224.07:51:58.92$vc4f8/va=4,7 2006.224.07:51:58.92#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.224.07:51:58.92#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.224.07:51:58.92#ibcon#ireg 11 cls_cnt 2 2006.224.07:51:58.92#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.224.07:51:58.98#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.224.07:51:58.98#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.224.07:51:58.98#ibcon#enter wrdev, iclass 11, count 2 2006.224.07:51:58.98#ibcon#first serial, iclass 11, count 2 2006.224.07:51:58.98#ibcon#enter sib2, iclass 11, count 2 2006.224.07:51:58.98#ibcon#flushed, iclass 11, count 2 2006.224.07:51:58.98#ibcon#about to write, iclass 11, count 2 2006.224.07:51:58.98#ibcon#wrote, iclass 11, count 2 2006.224.07:51:58.98#ibcon#about to read 3, iclass 11, count 2 2006.224.07:51:59.00#ibcon#read 3, iclass 11, count 2 2006.224.07:51:59.00#ibcon#about to read 4, iclass 11, count 2 2006.224.07:51:59.00#ibcon#read 4, iclass 11, count 2 2006.224.07:51:59.00#ibcon#about to read 5, iclass 11, count 2 2006.224.07:51:59.00#ibcon#read 5, iclass 11, count 2 2006.224.07:51:59.00#ibcon#about to read 6, iclass 11, count 2 2006.224.07:51:59.00#ibcon#read 6, iclass 11, count 2 2006.224.07:51:59.00#ibcon#end of sib2, iclass 11, count 2 2006.224.07:51:59.00#ibcon#*mode == 0, iclass 11, count 2 2006.224.07:51:59.00#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.224.07:51:59.00#ibcon#[25=AT04-07\r\n] 2006.224.07:51:59.00#ibcon#*before write, iclass 11, count 2 2006.224.07:51:59.00#ibcon#enter sib2, iclass 11, count 2 2006.224.07:51:59.00#ibcon#flushed, iclass 11, count 2 2006.224.07:51:59.00#ibcon#about to write, iclass 11, count 2 2006.224.07:51:59.00#ibcon#wrote, iclass 11, count 2 2006.224.07:51:59.00#ibcon#about to read 3, iclass 11, count 2 2006.224.07:51:59.03#ibcon#read 3, iclass 11, count 2 2006.224.07:51:59.03#ibcon#about to read 4, iclass 11, count 2 2006.224.07:51:59.03#ibcon#read 4, iclass 11, count 2 2006.224.07:51:59.03#ibcon#about to read 5, iclass 11, count 2 2006.224.07:51:59.03#ibcon#read 5, iclass 11, count 2 2006.224.07:51:59.03#ibcon#about to read 6, iclass 11, count 2 2006.224.07:51:59.03#ibcon#read 6, iclass 11, count 2 2006.224.07:51:59.03#ibcon#end of sib2, iclass 11, count 2 2006.224.07:51:59.03#ibcon#*after write, iclass 11, count 2 2006.224.07:51:59.03#ibcon#*before return 0, iclass 11, count 2 2006.224.07:51:59.03#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.224.07:51:59.03#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.224.07:51:59.03#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.224.07:51:59.03#ibcon#ireg 7 cls_cnt 0 2006.224.07:51:59.03#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.224.07:51:59.15#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.224.07:51:59.15#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.224.07:51:59.15#ibcon#enter wrdev, iclass 11, count 0 2006.224.07:51:59.15#ibcon#first serial, iclass 11, count 0 2006.224.07:51:59.15#ibcon#enter sib2, iclass 11, count 0 2006.224.07:51:59.15#ibcon#flushed, iclass 11, count 0 2006.224.07:51:59.15#ibcon#about to write, iclass 11, count 0 2006.224.07:51:59.15#ibcon#wrote, iclass 11, count 0 2006.224.07:51:59.15#ibcon#about to read 3, iclass 11, count 0 2006.224.07:51:59.17#ibcon#read 3, iclass 11, count 0 2006.224.07:51:59.17#ibcon#about to read 4, iclass 11, count 0 2006.224.07:51:59.17#ibcon#read 4, iclass 11, count 0 2006.224.07:51:59.17#ibcon#about to read 5, iclass 11, count 0 2006.224.07:51:59.17#ibcon#read 5, iclass 11, count 0 2006.224.07:51:59.17#ibcon#about to read 6, iclass 11, count 0 2006.224.07:51:59.17#ibcon#read 6, iclass 11, count 0 2006.224.07:51:59.17#ibcon#end of sib2, iclass 11, count 0 2006.224.07:51:59.17#ibcon#*mode == 0, iclass 11, count 0 2006.224.07:51:59.17#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.224.07:51:59.17#ibcon#[25=USB\r\n] 2006.224.07:51:59.17#ibcon#*before write, iclass 11, count 0 2006.224.07:51:59.17#ibcon#enter sib2, iclass 11, count 0 2006.224.07:51:59.17#ibcon#flushed, iclass 11, count 0 2006.224.07:51:59.17#ibcon#about to write, iclass 11, count 0 2006.224.07:51:59.17#ibcon#wrote, iclass 11, count 0 2006.224.07:51:59.17#ibcon#about to read 3, iclass 11, count 0 2006.224.07:51:59.20#ibcon#read 3, iclass 11, count 0 2006.224.07:51:59.20#ibcon#about to read 4, iclass 11, count 0 2006.224.07:51:59.20#ibcon#read 4, iclass 11, count 0 2006.224.07:51:59.20#ibcon#about to read 5, iclass 11, count 0 2006.224.07:51:59.20#ibcon#read 5, iclass 11, count 0 2006.224.07:51:59.20#ibcon#about to read 6, iclass 11, count 0 2006.224.07:51:59.20#ibcon#read 6, iclass 11, count 0 2006.224.07:51:59.20#ibcon#end of sib2, iclass 11, count 0 2006.224.07:51:59.20#ibcon#*after write, iclass 11, count 0 2006.224.07:51:59.20#ibcon#*before return 0, iclass 11, count 0 2006.224.07:51:59.20#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.224.07:51:59.20#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.224.07:51:59.20#ibcon#about to clear, iclass 11 cls_cnt 0 2006.224.07:51:59.20#ibcon#cleared, iclass 11 cls_cnt 0 2006.224.07:51:59.20$vc4f8/valo=5,652.99 2006.224.07:51:59.20#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.224.07:51:59.20#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.224.07:51:59.20#ibcon#ireg 17 cls_cnt 0 2006.224.07:51:59.20#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.224.07:51:59.20#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.224.07:51:59.20#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.224.07:51:59.20#ibcon#enter wrdev, iclass 13, count 0 2006.224.07:51:59.20#ibcon#first serial, iclass 13, count 0 2006.224.07:51:59.20#ibcon#enter sib2, iclass 13, count 0 2006.224.07:51:59.20#ibcon#flushed, iclass 13, count 0 2006.224.07:51:59.20#ibcon#about to write, iclass 13, count 0 2006.224.07:51:59.20#ibcon#wrote, iclass 13, count 0 2006.224.07:51:59.20#ibcon#about to read 3, iclass 13, count 0 2006.224.07:51:59.22#ibcon#read 3, iclass 13, count 0 2006.224.07:51:59.22#ibcon#about to read 4, iclass 13, count 0 2006.224.07:51:59.22#ibcon#read 4, iclass 13, count 0 2006.224.07:51:59.22#ibcon#about to read 5, iclass 13, count 0 2006.224.07:51:59.22#ibcon#read 5, iclass 13, count 0 2006.224.07:51:59.22#ibcon#about to read 6, iclass 13, count 0 2006.224.07:51:59.22#ibcon#read 6, iclass 13, count 0 2006.224.07:51:59.22#ibcon#end of sib2, iclass 13, count 0 2006.224.07:51:59.22#ibcon#*mode == 0, iclass 13, count 0 2006.224.07:51:59.22#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.224.07:51:59.22#ibcon#[26=FRQ=05,652.99\r\n] 2006.224.07:51:59.22#ibcon#*before write, iclass 13, count 0 2006.224.07:51:59.22#ibcon#enter sib2, iclass 13, count 0 2006.224.07:51:59.22#ibcon#flushed, iclass 13, count 0 2006.224.07:51:59.22#ibcon#about to write, iclass 13, count 0 2006.224.07:51:59.22#ibcon#wrote, iclass 13, count 0 2006.224.07:51:59.22#ibcon#about to read 3, iclass 13, count 0 2006.224.07:51:59.26#ibcon#read 3, iclass 13, count 0 2006.224.07:51:59.26#ibcon#about to read 4, iclass 13, count 0 2006.224.07:51:59.26#ibcon#read 4, iclass 13, count 0 2006.224.07:51:59.26#ibcon#about to read 5, iclass 13, count 0 2006.224.07:51:59.26#ibcon#read 5, iclass 13, count 0 2006.224.07:51:59.26#ibcon#about to read 6, iclass 13, count 0 2006.224.07:51:59.26#ibcon#read 6, iclass 13, count 0 2006.224.07:51:59.26#ibcon#end of sib2, iclass 13, count 0 2006.224.07:51:59.26#ibcon#*after write, iclass 13, count 0 2006.224.07:51:59.26#ibcon#*before return 0, iclass 13, count 0 2006.224.07:51:59.26#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.224.07:51:59.26#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.224.07:51:59.26#ibcon#about to clear, iclass 13 cls_cnt 0 2006.224.07:51:59.26#ibcon#cleared, iclass 13 cls_cnt 0 2006.224.07:51:59.26$vc4f8/va=5,7 2006.224.07:51:59.26#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.224.07:51:59.26#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.224.07:51:59.26#ibcon#ireg 11 cls_cnt 2 2006.224.07:51:59.26#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.224.07:51:59.32#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.224.07:51:59.32#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.224.07:51:59.32#ibcon#enter wrdev, iclass 15, count 2 2006.224.07:51:59.32#ibcon#first serial, iclass 15, count 2 2006.224.07:51:59.32#ibcon#enter sib2, iclass 15, count 2 2006.224.07:51:59.32#ibcon#flushed, iclass 15, count 2 2006.224.07:51:59.32#ibcon#about to write, iclass 15, count 2 2006.224.07:51:59.32#ibcon#wrote, iclass 15, count 2 2006.224.07:51:59.32#ibcon#about to read 3, iclass 15, count 2 2006.224.07:51:59.34#ibcon#read 3, iclass 15, count 2 2006.224.07:51:59.34#ibcon#about to read 4, iclass 15, count 2 2006.224.07:51:59.34#ibcon#read 4, iclass 15, count 2 2006.224.07:51:59.34#ibcon#about to read 5, iclass 15, count 2 2006.224.07:51:59.34#ibcon#read 5, iclass 15, count 2 2006.224.07:51:59.34#ibcon#about to read 6, iclass 15, count 2 2006.224.07:51:59.34#ibcon#read 6, iclass 15, count 2 2006.224.07:51:59.34#ibcon#end of sib2, iclass 15, count 2 2006.224.07:51:59.34#ibcon#*mode == 0, iclass 15, count 2 2006.224.07:51:59.34#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.224.07:51:59.34#ibcon#[25=AT05-07\r\n] 2006.224.07:51:59.34#ibcon#*before write, iclass 15, count 2 2006.224.07:51:59.34#ibcon#enter sib2, iclass 15, count 2 2006.224.07:51:59.34#ibcon#flushed, iclass 15, count 2 2006.224.07:51:59.34#ibcon#about to write, iclass 15, count 2 2006.224.07:51:59.34#ibcon#wrote, iclass 15, count 2 2006.224.07:51:59.34#ibcon#about to read 3, iclass 15, count 2 2006.224.07:51:59.37#ibcon#read 3, iclass 15, count 2 2006.224.07:51:59.37#ibcon#about to read 4, iclass 15, count 2 2006.224.07:51:59.37#ibcon#read 4, iclass 15, count 2 2006.224.07:51:59.37#ibcon#about to read 5, iclass 15, count 2 2006.224.07:51:59.37#ibcon#read 5, iclass 15, count 2 2006.224.07:51:59.37#ibcon#about to read 6, iclass 15, count 2 2006.224.07:51:59.37#ibcon#read 6, iclass 15, count 2 2006.224.07:51:59.37#ibcon#end of sib2, iclass 15, count 2 2006.224.07:51:59.37#ibcon#*after write, iclass 15, count 2 2006.224.07:51:59.37#ibcon#*before return 0, iclass 15, count 2 2006.224.07:51:59.37#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.224.07:51:59.37#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.224.07:51:59.37#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.224.07:51:59.37#ibcon#ireg 7 cls_cnt 0 2006.224.07:51:59.37#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.224.07:51:59.49#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.224.07:51:59.49#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.224.07:51:59.49#ibcon#enter wrdev, iclass 15, count 0 2006.224.07:51:59.49#ibcon#first serial, iclass 15, count 0 2006.224.07:51:59.49#ibcon#enter sib2, iclass 15, count 0 2006.224.07:51:59.49#ibcon#flushed, iclass 15, count 0 2006.224.07:51:59.49#ibcon#about to write, iclass 15, count 0 2006.224.07:51:59.49#ibcon#wrote, iclass 15, count 0 2006.224.07:51:59.49#ibcon#about to read 3, iclass 15, count 0 2006.224.07:51:59.51#ibcon#read 3, iclass 15, count 0 2006.224.07:51:59.51#ibcon#about to read 4, iclass 15, count 0 2006.224.07:51:59.51#ibcon#read 4, iclass 15, count 0 2006.224.07:51:59.51#ibcon#about to read 5, iclass 15, count 0 2006.224.07:51:59.51#ibcon#read 5, iclass 15, count 0 2006.224.07:51:59.51#ibcon#about to read 6, iclass 15, count 0 2006.224.07:51:59.51#ibcon#read 6, iclass 15, count 0 2006.224.07:51:59.51#ibcon#end of sib2, iclass 15, count 0 2006.224.07:51:59.51#ibcon#*mode == 0, iclass 15, count 0 2006.224.07:51:59.51#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.224.07:51:59.51#ibcon#[25=USB\r\n] 2006.224.07:51:59.51#ibcon#*before write, iclass 15, count 0 2006.224.07:51:59.51#ibcon#enter sib2, iclass 15, count 0 2006.224.07:51:59.51#ibcon#flushed, iclass 15, count 0 2006.224.07:51:59.51#ibcon#about to write, iclass 15, count 0 2006.224.07:51:59.51#ibcon#wrote, iclass 15, count 0 2006.224.07:51:59.51#ibcon#about to read 3, iclass 15, count 0 2006.224.07:51:59.54#ibcon#read 3, iclass 15, count 0 2006.224.07:51:59.54#ibcon#about to read 4, iclass 15, count 0 2006.224.07:51:59.54#ibcon#read 4, iclass 15, count 0 2006.224.07:51:59.54#ibcon#about to read 5, iclass 15, count 0 2006.224.07:51:59.54#ibcon#read 5, iclass 15, count 0 2006.224.07:51:59.54#ibcon#about to read 6, iclass 15, count 0 2006.224.07:51:59.54#ibcon#read 6, iclass 15, count 0 2006.224.07:51:59.54#ibcon#end of sib2, iclass 15, count 0 2006.224.07:51:59.54#ibcon#*after write, iclass 15, count 0 2006.224.07:51:59.54#ibcon#*before return 0, iclass 15, count 0 2006.224.07:51:59.54#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.224.07:51:59.54#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.224.07:51:59.54#ibcon#about to clear, iclass 15 cls_cnt 0 2006.224.07:51:59.54#ibcon#cleared, iclass 15 cls_cnt 0 2006.224.07:51:59.54$vc4f8/valo=6,772.99 2006.224.07:51:59.54#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.224.07:51:59.54#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.224.07:51:59.54#ibcon#ireg 17 cls_cnt 0 2006.224.07:51:59.54#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.224.07:51:59.54#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.224.07:51:59.54#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.224.07:51:59.54#ibcon#enter wrdev, iclass 17, count 0 2006.224.07:51:59.54#ibcon#first serial, iclass 17, count 0 2006.224.07:51:59.54#ibcon#enter sib2, iclass 17, count 0 2006.224.07:51:59.54#ibcon#flushed, iclass 17, count 0 2006.224.07:51:59.54#ibcon#about to write, iclass 17, count 0 2006.224.07:51:59.54#ibcon#wrote, iclass 17, count 0 2006.224.07:51:59.54#ibcon#about to read 3, iclass 17, count 0 2006.224.07:51:59.56#ibcon#read 3, iclass 17, count 0 2006.224.07:51:59.56#ibcon#about to read 4, iclass 17, count 0 2006.224.07:51:59.56#ibcon#read 4, iclass 17, count 0 2006.224.07:51:59.56#ibcon#about to read 5, iclass 17, count 0 2006.224.07:51:59.56#ibcon#read 5, iclass 17, count 0 2006.224.07:51:59.56#ibcon#about to read 6, iclass 17, count 0 2006.224.07:51:59.56#ibcon#read 6, iclass 17, count 0 2006.224.07:51:59.56#ibcon#end of sib2, iclass 17, count 0 2006.224.07:51:59.56#ibcon#*mode == 0, iclass 17, count 0 2006.224.07:51:59.56#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.224.07:51:59.56#ibcon#[26=FRQ=06,772.99\r\n] 2006.224.07:51:59.56#ibcon#*before write, iclass 17, count 0 2006.224.07:51:59.56#ibcon#enter sib2, iclass 17, count 0 2006.224.07:51:59.56#ibcon#flushed, iclass 17, count 0 2006.224.07:51:59.56#ibcon#about to write, iclass 17, count 0 2006.224.07:51:59.56#ibcon#wrote, iclass 17, count 0 2006.224.07:51:59.56#ibcon#about to read 3, iclass 17, count 0 2006.224.07:51:59.60#ibcon#read 3, iclass 17, count 0 2006.224.07:51:59.60#ibcon#about to read 4, iclass 17, count 0 2006.224.07:51:59.60#ibcon#read 4, iclass 17, count 0 2006.224.07:51:59.60#ibcon#about to read 5, iclass 17, count 0 2006.224.07:51:59.60#ibcon#read 5, iclass 17, count 0 2006.224.07:51:59.60#ibcon#about to read 6, iclass 17, count 0 2006.224.07:51:59.60#ibcon#read 6, iclass 17, count 0 2006.224.07:51:59.60#ibcon#end of sib2, iclass 17, count 0 2006.224.07:51:59.60#ibcon#*after write, iclass 17, count 0 2006.224.07:51:59.60#ibcon#*before return 0, iclass 17, count 0 2006.224.07:51:59.60#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.224.07:51:59.60#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.224.07:51:59.60#ibcon#about to clear, iclass 17 cls_cnt 0 2006.224.07:51:59.60#ibcon#cleared, iclass 17 cls_cnt 0 2006.224.07:51:59.60$vc4f8/va=6,6 2006.224.07:51:59.60#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.224.07:51:59.60#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.224.07:51:59.60#ibcon#ireg 11 cls_cnt 2 2006.224.07:51:59.60#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.224.07:51:59.66#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.224.07:51:59.66#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.224.07:51:59.66#ibcon#enter wrdev, iclass 19, count 2 2006.224.07:51:59.66#ibcon#first serial, iclass 19, count 2 2006.224.07:51:59.66#ibcon#enter sib2, iclass 19, count 2 2006.224.07:51:59.66#ibcon#flushed, iclass 19, count 2 2006.224.07:51:59.66#ibcon#about to write, iclass 19, count 2 2006.224.07:51:59.66#ibcon#wrote, iclass 19, count 2 2006.224.07:51:59.66#ibcon#about to read 3, iclass 19, count 2 2006.224.07:51:59.68#ibcon#read 3, iclass 19, count 2 2006.224.07:51:59.68#ibcon#about to read 4, iclass 19, count 2 2006.224.07:51:59.68#ibcon#read 4, iclass 19, count 2 2006.224.07:51:59.68#ibcon#about to read 5, iclass 19, count 2 2006.224.07:51:59.68#ibcon#read 5, iclass 19, count 2 2006.224.07:51:59.68#ibcon#about to read 6, iclass 19, count 2 2006.224.07:51:59.68#ibcon#read 6, iclass 19, count 2 2006.224.07:51:59.68#ibcon#end of sib2, iclass 19, count 2 2006.224.07:51:59.68#ibcon#*mode == 0, iclass 19, count 2 2006.224.07:51:59.68#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.224.07:51:59.68#ibcon#[25=AT06-06\r\n] 2006.224.07:51:59.68#ibcon#*before write, iclass 19, count 2 2006.224.07:51:59.68#ibcon#enter sib2, iclass 19, count 2 2006.224.07:51:59.68#ibcon#flushed, iclass 19, count 2 2006.224.07:51:59.68#ibcon#about to write, iclass 19, count 2 2006.224.07:51:59.68#ibcon#wrote, iclass 19, count 2 2006.224.07:51:59.68#ibcon#about to read 3, iclass 19, count 2 2006.224.07:51:59.71#ibcon#read 3, iclass 19, count 2 2006.224.07:51:59.71#ibcon#about to read 4, iclass 19, count 2 2006.224.07:51:59.71#ibcon#read 4, iclass 19, count 2 2006.224.07:51:59.71#ibcon#about to read 5, iclass 19, count 2 2006.224.07:51:59.71#ibcon#read 5, iclass 19, count 2 2006.224.07:51:59.71#ibcon#about to read 6, iclass 19, count 2 2006.224.07:51:59.71#ibcon#read 6, iclass 19, count 2 2006.224.07:51:59.71#ibcon#end of sib2, iclass 19, count 2 2006.224.07:51:59.71#ibcon#*after write, iclass 19, count 2 2006.224.07:51:59.71#ibcon#*before return 0, iclass 19, count 2 2006.224.07:51:59.71#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.224.07:51:59.71#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.224.07:51:59.71#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.224.07:51:59.71#ibcon#ireg 7 cls_cnt 0 2006.224.07:51:59.71#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.224.07:51:59.83#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.224.07:51:59.83#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.224.07:51:59.83#ibcon#enter wrdev, iclass 19, count 0 2006.224.07:51:59.83#ibcon#first serial, iclass 19, count 0 2006.224.07:51:59.83#ibcon#enter sib2, iclass 19, count 0 2006.224.07:51:59.83#ibcon#flushed, iclass 19, count 0 2006.224.07:51:59.83#ibcon#about to write, iclass 19, count 0 2006.224.07:51:59.83#ibcon#wrote, iclass 19, count 0 2006.224.07:51:59.83#ibcon#about to read 3, iclass 19, count 0 2006.224.07:51:59.85#ibcon#read 3, iclass 19, count 0 2006.224.07:51:59.85#ibcon#about to read 4, iclass 19, count 0 2006.224.07:51:59.85#ibcon#read 4, iclass 19, count 0 2006.224.07:51:59.85#ibcon#about to read 5, iclass 19, count 0 2006.224.07:51:59.85#ibcon#read 5, iclass 19, count 0 2006.224.07:51:59.85#ibcon#about to read 6, iclass 19, count 0 2006.224.07:51:59.85#ibcon#read 6, iclass 19, count 0 2006.224.07:51:59.85#ibcon#end of sib2, iclass 19, count 0 2006.224.07:51:59.85#ibcon#*mode == 0, iclass 19, count 0 2006.224.07:51:59.85#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.224.07:51:59.85#ibcon#[25=USB\r\n] 2006.224.07:51:59.85#ibcon#*before write, iclass 19, count 0 2006.224.07:51:59.85#ibcon#enter sib2, iclass 19, count 0 2006.224.07:51:59.85#ibcon#flushed, iclass 19, count 0 2006.224.07:51:59.85#ibcon#about to write, iclass 19, count 0 2006.224.07:51:59.85#ibcon#wrote, iclass 19, count 0 2006.224.07:51:59.85#ibcon#about to read 3, iclass 19, count 0 2006.224.07:51:59.88#ibcon#read 3, iclass 19, count 0 2006.224.07:51:59.88#ibcon#about to read 4, iclass 19, count 0 2006.224.07:51:59.88#ibcon#read 4, iclass 19, count 0 2006.224.07:51:59.88#ibcon#about to read 5, iclass 19, count 0 2006.224.07:51:59.88#ibcon#read 5, iclass 19, count 0 2006.224.07:51:59.88#ibcon#about to read 6, iclass 19, count 0 2006.224.07:51:59.88#ibcon#read 6, iclass 19, count 0 2006.224.07:51:59.88#ibcon#end of sib2, iclass 19, count 0 2006.224.07:51:59.88#ibcon#*after write, iclass 19, count 0 2006.224.07:51:59.88#ibcon#*before return 0, iclass 19, count 0 2006.224.07:51:59.88#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.224.07:51:59.88#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.224.07:51:59.88#ibcon#about to clear, iclass 19 cls_cnt 0 2006.224.07:51:59.88#ibcon#cleared, iclass 19 cls_cnt 0 2006.224.07:51:59.88$vc4f8/valo=7,832.99 2006.224.07:51:59.88#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.224.07:51:59.88#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.224.07:51:59.88#ibcon#ireg 17 cls_cnt 0 2006.224.07:51:59.88#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.224.07:51:59.88#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.224.07:51:59.88#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.224.07:51:59.88#ibcon#enter wrdev, iclass 21, count 0 2006.224.07:51:59.88#ibcon#first serial, iclass 21, count 0 2006.224.07:51:59.88#ibcon#enter sib2, iclass 21, count 0 2006.224.07:51:59.88#ibcon#flushed, iclass 21, count 0 2006.224.07:51:59.88#ibcon#about to write, iclass 21, count 0 2006.224.07:51:59.88#ibcon#wrote, iclass 21, count 0 2006.224.07:51:59.88#ibcon#about to read 3, iclass 21, count 0 2006.224.07:51:59.90#ibcon#read 3, iclass 21, count 0 2006.224.07:51:59.90#ibcon#about to read 4, iclass 21, count 0 2006.224.07:51:59.90#ibcon#read 4, iclass 21, count 0 2006.224.07:51:59.90#ibcon#about to read 5, iclass 21, count 0 2006.224.07:51:59.90#ibcon#read 5, iclass 21, count 0 2006.224.07:51:59.90#ibcon#about to read 6, iclass 21, count 0 2006.224.07:51:59.90#ibcon#read 6, iclass 21, count 0 2006.224.07:51:59.90#ibcon#end of sib2, iclass 21, count 0 2006.224.07:51:59.90#ibcon#*mode == 0, iclass 21, count 0 2006.224.07:51:59.90#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.224.07:51:59.90#ibcon#[26=FRQ=07,832.99\r\n] 2006.224.07:51:59.90#ibcon#*before write, iclass 21, count 0 2006.224.07:51:59.90#ibcon#enter sib2, iclass 21, count 0 2006.224.07:51:59.90#ibcon#flushed, iclass 21, count 0 2006.224.07:51:59.90#ibcon#about to write, iclass 21, count 0 2006.224.07:51:59.90#ibcon#wrote, iclass 21, count 0 2006.224.07:51:59.90#ibcon#about to read 3, iclass 21, count 0 2006.224.07:51:59.94#ibcon#read 3, iclass 21, count 0 2006.224.07:51:59.94#ibcon#about to read 4, iclass 21, count 0 2006.224.07:51:59.94#ibcon#read 4, iclass 21, count 0 2006.224.07:51:59.94#ibcon#about to read 5, iclass 21, count 0 2006.224.07:51:59.94#ibcon#read 5, iclass 21, count 0 2006.224.07:51:59.94#ibcon#about to read 6, iclass 21, count 0 2006.224.07:51:59.94#ibcon#read 6, iclass 21, count 0 2006.224.07:51:59.94#ibcon#end of sib2, iclass 21, count 0 2006.224.07:51:59.94#ibcon#*after write, iclass 21, count 0 2006.224.07:51:59.94#ibcon#*before return 0, iclass 21, count 0 2006.224.07:51:59.94#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.224.07:51:59.94#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.224.07:51:59.94#ibcon#about to clear, iclass 21 cls_cnt 0 2006.224.07:51:59.94#ibcon#cleared, iclass 21 cls_cnt 0 2006.224.07:51:59.94$vc4f8/va=7,6 2006.224.07:51:59.94#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.224.07:51:59.94#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.224.07:51:59.94#ibcon#ireg 11 cls_cnt 2 2006.224.07:51:59.94#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.224.07:52:00.00#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.224.07:52:00.00#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.224.07:52:00.00#ibcon#enter wrdev, iclass 23, count 2 2006.224.07:52:00.00#ibcon#first serial, iclass 23, count 2 2006.224.07:52:00.00#ibcon#enter sib2, iclass 23, count 2 2006.224.07:52:00.00#ibcon#flushed, iclass 23, count 2 2006.224.07:52:00.00#ibcon#about to write, iclass 23, count 2 2006.224.07:52:00.00#ibcon#wrote, iclass 23, count 2 2006.224.07:52:00.00#ibcon#about to read 3, iclass 23, count 2 2006.224.07:52:00.02#ibcon#read 3, iclass 23, count 2 2006.224.07:52:00.02#ibcon#about to read 4, iclass 23, count 2 2006.224.07:52:00.02#ibcon#read 4, iclass 23, count 2 2006.224.07:52:00.02#ibcon#about to read 5, iclass 23, count 2 2006.224.07:52:00.02#ibcon#read 5, iclass 23, count 2 2006.224.07:52:00.02#ibcon#about to read 6, iclass 23, count 2 2006.224.07:52:00.02#ibcon#read 6, iclass 23, count 2 2006.224.07:52:00.02#ibcon#end of sib2, iclass 23, count 2 2006.224.07:52:00.02#ibcon#*mode == 0, iclass 23, count 2 2006.224.07:52:00.02#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.224.07:52:00.02#ibcon#[25=AT07-06\r\n] 2006.224.07:52:00.02#ibcon#*before write, iclass 23, count 2 2006.224.07:52:00.02#ibcon#enter sib2, iclass 23, count 2 2006.224.07:52:00.02#ibcon#flushed, iclass 23, count 2 2006.224.07:52:00.02#ibcon#about to write, iclass 23, count 2 2006.224.07:52:00.02#ibcon#wrote, iclass 23, count 2 2006.224.07:52:00.02#ibcon#about to read 3, iclass 23, count 2 2006.224.07:52:00.05#ibcon#read 3, iclass 23, count 2 2006.224.07:52:00.05#ibcon#about to read 4, iclass 23, count 2 2006.224.07:52:00.05#ibcon#read 4, iclass 23, count 2 2006.224.07:52:00.05#ibcon#about to read 5, iclass 23, count 2 2006.224.07:52:00.05#ibcon#read 5, iclass 23, count 2 2006.224.07:52:00.05#ibcon#about to read 6, iclass 23, count 2 2006.224.07:52:00.05#ibcon#read 6, iclass 23, count 2 2006.224.07:52:00.05#ibcon#end of sib2, iclass 23, count 2 2006.224.07:52:00.05#ibcon#*after write, iclass 23, count 2 2006.224.07:52:00.05#ibcon#*before return 0, iclass 23, count 2 2006.224.07:52:00.05#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.224.07:52:00.05#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.224.07:52:00.05#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.224.07:52:00.05#ibcon#ireg 7 cls_cnt 0 2006.224.07:52:00.05#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.224.07:52:00.17#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.224.07:52:00.17#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.224.07:52:00.17#ibcon#enter wrdev, iclass 23, count 0 2006.224.07:52:00.17#ibcon#first serial, iclass 23, count 0 2006.224.07:52:00.17#ibcon#enter sib2, iclass 23, count 0 2006.224.07:52:00.17#ibcon#flushed, iclass 23, count 0 2006.224.07:52:00.17#ibcon#about to write, iclass 23, count 0 2006.224.07:52:00.17#ibcon#wrote, iclass 23, count 0 2006.224.07:52:00.17#ibcon#about to read 3, iclass 23, count 0 2006.224.07:52:00.19#ibcon#read 3, iclass 23, count 0 2006.224.07:52:00.19#ibcon#about to read 4, iclass 23, count 0 2006.224.07:52:00.19#ibcon#read 4, iclass 23, count 0 2006.224.07:52:00.19#ibcon#about to read 5, iclass 23, count 0 2006.224.07:52:00.19#ibcon#read 5, iclass 23, count 0 2006.224.07:52:00.19#ibcon#about to read 6, iclass 23, count 0 2006.224.07:52:00.19#ibcon#read 6, iclass 23, count 0 2006.224.07:52:00.19#ibcon#end of sib2, iclass 23, count 0 2006.224.07:52:00.19#ibcon#*mode == 0, iclass 23, count 0 2006.224.07:52:00.19#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.224.07:52:00.19#ibcon#[25=USB\r\n] 2006.224.07:52:00.19#ibcon#*before write, iclass 23, count 0 2006.224.07:52:00.19#ibcon#enter sib2, iclass 23, count 0 2006.224.07:52:00.19#ibcon#flushed, iclass 23, count 0 2006.224.07:52:00.19#ibcon#about to write, iclass 23, count 0 2006.224.07:52:00.19#ibcon#wrote, iclass 23, count 0 2006.224.07:52:00.19#ibcon#about to read 3, iclass 23, count 0 2006.224.07:52:00.22#ibcon#read 3, iclass 23, count 0 2006.224.07:52:00.22#ibcon#about to read 4, iclass 23, count 0 2006.224.07:52:00.22#ibcon#read 4, iclass 23, count 0 2006.224.07:52:00.22#ibcon#about to read 5, iclass 23, count 0 2006.224.07:52:00.22#ibcon#read 5, iclass 23, count 0 2006.224.07:52:00.22#ibcon#about to read 6, iclass 23, count 0 2006.224.07:52:00.22#ibcon#read 6, iclass 23, count 0 2006.224.07:52:00.22#ibcon#end of sib2, iclass 23, count 0 2006.224.07:52:00.22#ibcon#*after write, iclass 23, count 0 2006.224.07:52:00.22#ibcon#*before return 0, iclass 23, count 0 2006.224.07:52:00.22#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.224.07:52:00.22#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.224.07:52:00.22#ibcon#about to clear, iclass 23 cls_cnt 0 2006.224.07:52:00.22#ibcon#cleared, iclass 23 cls_cnt 0 2006.224.07:52:00.22$vc4f8/valo=8,852.99 2006.224.07:52:00.22#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.224.07:52:00.22#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.224.07:52:00.22#ibcon#ireg 17 cls_cnt 0 2006.224.07:52:00.22#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.224.07:52:00.22#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.224.07:52:00.22#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.224.07:52:00.22#ibcon#enter wrdev, iclass 25, count 0 2006.224.07:52:00.22#ibcon#first serial, iclass 25, count 0 2006.224.07:52:00.22#ibcon#enter sib2, iclass 25, count 0 2006.224.07:52:00.22#ibcon#flushed, iclass 25, count 0 2006.224.07:52:00.22#ibcon#about to write, iclass 25, count 0 2006.224.07:52:00.22#ibcon#wrote, iclass 25, count 0 2006.224.07:52:00.22#ibcon#about to read 3, iclass 25, count 0 2006.224.07:52:00.24#ibcon#read 3, iclass 25, count 0 2006.224.07:52:00.24#ibcon#about to read 4, iclass 25, count 0 2006.224.07:52:00.24#ibcon#read 4, iclass 25, count 0 2006.224.07:52:00.24#ibcon#about to read 5, iclass 25, count 0 2006.224.07:52:00.24#ibcon#read 5, iclass 25, count 0 2006.224.07:52:00.24#ibcon#about to read 6, iclass 25, count 0 2006.224.07:52:00.24#ibcon#read 6, iclass 25, count 0 2006.224.07:52:00.24#ibcon#end of sib2, iclass 25, count 0 2006.224.07:52:00.24#ibcon#*mode == 0, iclass 25, count 0 2006.224.07:52:00.24#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.224.07:52:00.24#ibcon#[26=FRQ=08,852.99\r\n] 2006.224.07:52:00.24#ibcon#*before write, iclass 25, count 0 2006.224.07:52:00.24#ibcon#enter sib2, iclass 25, count 0 2006.224.07:52:00.24#ibcon#flushed, iclass 25, count 0 2006.224.07:52:00.24#ibcon#about to write, iclass 25, count 0 2006.224.07:52:00.24#ibcon#wrote, iclass 25, count 0 2006.224.07:52:00.24#ibcon#about to read 3, iclass 25, count 0 2006.224.07:52:00.28#ibcon#read 3, iclass 25, count 0 2006.224.07:52:00.28#ibcon#about to read 4, iclass 25, count 0 2006.224.07:52:00.28#ibcon#read 4, iclass 25, count 0 2006.224.07:52:00.28#ibcon#about to read 5, iclass 25, count 0 2006.224.07:52:00.28#ibcon#read 5, iclass 25, count 0 2006.224.07:52:00.28#ibcon#about to read 6, iclass 25, count 0 2006.224.07:52:00.28#ibcon#read 6, iclass 25, count 0 2006.224.07:52:00.28#ibcon#end of sib2, iclass 25, count 0 2006.224.07:52:00.28#ibcon#*after write, iclass 25, count 0 2006.224.07:52:00.28#ibcon#*before return 0, iclass 25, count 0 2006.224.07:52:00.28#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.224.07:52:00.28#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.224.07:52:00.28#ibcon#about to clear, iclass 25 cls_cnt 0 2006.224.07:52:00.28#ibcon#cleared, iclass 25 cls_cnt 0 2006.224.07:52:00.28$vc4f8/va=8,7 2006.224.07:52:00.28#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.224.07:52:00.28#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.224.07:52:00.28#ibcon#ireg 11 cls_cnt 2 2006.224.07:52:00.28#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.224.07:52:00.34#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.224.07:52:00.34#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.224.07:52:00.34#ibcon#enter wrdev, iclass 27, count 2 2006.224.07:52:00.34#ibcon#first serial, iclass 27, count 2 2006.224.07:52:00.34#ibcon#enter sib2, iclass 27, count 2 2006.224.07:52:00.34#ibcon#flushed, iclass 27, count 2 2006.224.07:52:00.34#ibcon#about to write, iclass 27, count 2 2006.224.07:52:00.34#ibcon#wrote, iclass 27, count 2 2006.224.07:52:00.34#ibcon#about to read 3, iclass 27, count 2 2006.224.07:52:00.36#ibcon#read 3, iclass 27, count 2 2006.224.07:52:00.36#ibcon#about to read 4, iclass 27, count 2 2006.224.07:52:00.36#ibcon#read 4, iclass 27, count 2 2006.224.07:52:00.36#ibcon#about to read 5, iclass 27, count 2 2006.224.07:52:00.36#ibcon#read 5, iclass 27, count 2 2006.224.07:52:00.36#ibcon#about to read 6, iclass 27, count 2 2006.224.07:52:00.36#ibcon#read 6, iclass 27, count 2 2006.224.07:52:00.36#ibcon#end of sib2, iclass 27, count 2 2006.224.07:52:00.36#ibcon#*mode == 0, iclass 27, count 2 2006.224.07:52:00.36#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.224.07:52:00.36#ibcon#[25=AT08-07\r\n] 2006.224.07:52:00.36#ibcon#*before write, iclass 27, count 2 2006.224.07:52:00.36#ibcon#enter sib2, iclass 27, count 2 2006.224.07:52:00.36#ibcon#flushed, iclass 27, count 2 2006.224.07:52:00.36#ibcon#about to write, iclass 27, count 2 2006.224.07:52:00.36#ibcon#wrote, iclass 27, count 2 2006.224.07:52:00.36#ibcon#about to read 3, iclass 27, count 2 2006.224.07:52:00.39#ibcon#read 3, iclass 27, count 2 2006.224.07:52:00.39#ibcon#about to read 4, iclass 27, count 2 2006.224.07:52:00.39#ibcon#read 4, iclass 27, count 2 2006.224.07:52:00.39#ibcon#about to read 5, iclass 27, count 2 2006.224.07:52:00.39#ibcon#read 5, iclass 27, count 2 2006.224.07:52:00.39#ibcon#about to read 6, iclass 27, count 2 2006.224.07:52:00.39#ibcon#read 6, iclass 27, count 2 2006.224.07:52:00.39#ibcon#end of sib2, iclass 27, count 2 2006.224.07:52:00.39#ibcon#*after write, iclass 27, count 2 2006.224.07:52:00.39#ibcon#*before return 0, iclass 27, count 2 2006.224.07:52:00.39#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.224.07:52:00.39#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.224.07:52:00.39#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.224.07:52:00.39#ibcon#ireg 7 cls_cnt 0 2006.224.07:52:00.39#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.224.07:52:00.51#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.224.07:52:00.51#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.224.07:52:00.51#ibcon#enter wrdev, iclass 27, count 0 2006.224.07:52:00.51#ibcon#first serial, iclass 27, count 0 2006.224.07:52:00.51#ibcon#enter sib2, iclass 27, count 0 2006.224.07:52:00.51#ibcon#flushed, iclass 27, count 0 2006.224.07:52:00.51#ibcon#about to write, iclass 27, count 0 2006.224.07:52:00.51#ibcon#wrote, iclass 27, count 0 2006.224.07:52:00.51#ibcon#about to read 3, iclass 27, count 0 2006.224.07:52:00.53#ibcon#read 3, iclass 27, count 0 2006.224.07:52:00.53#ibcon#about to read 4, iclass 27, count 0 2006.224.07:52:00.53#ibcon#read 4, iclass 27, count 0 2006.224.07:52:00.53#ibcon#about to read 5, iclass 27, count 0 2006.224.07:52:00.53#ibcon#read 5, iclass 27, count 0 2006.224.07:52:00.53#ibcon#about to read 6, iclass 27, count 0 2006.224.07:52:00.53#ibcon#read 6, iclass 27, count 0 2006.224.07:52:00.53#ibcon#end of sib2, iclass 27, count 0 2006.224.07:52:00.53#ibcon#*mode == 0, iclass 27, count 0 2006.224.07:52:00.53#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.224.07:52:00.53#ibcon#[25=USB\r\n] 2006.224.07:52:00.53#ibcon#*before write, iclass 27, count 0 2006.224.07:52:00.53#ibcon#enter sib2, iclass 27, count 0 2006.224.07:52:00.53#ibcon#flushed, iclass 27, count 0 2006.224.07:52:00.53#ibcon#about to write, iclass 27, count 0 2006.224.07:52:00.53#ibcon#wrote, iclass 27, count 0 2006.224.07:52:00.53#ibcon#about to read 3, iclass 27, count 0 2006.224.07:52:00.56#ibcon#read 3, iclass 27, count 0 2006.224.07:52:00.56#ibcon#about to read 4, iclass 27, count 0 2006.224.07:52:00.56#ibcon#read 4, iclass 27, count 0 2006.224.07:52:00.56#ibcon#about to read 5, iclass 27, count 0 2006.224.07:52:00.56#ibcon#read 5, iclass 27, count 0 2006.224.07:52:00.56#ibcon#about to read 6, iclass 27, count 0 2006.224.07:52:00.56#ibcon#read 6, iclass 27, count 0 2006.224.07:52:00.56#ibcon#end of sib2, iclass 27, count 0 2006.224.07:52:00.56#ibcon#*after write, iclass 27, count 0 2006.224.07:52:00.56#ibcon#*before return 0, iclass 27, count 0 2006.224.07:52:00.56#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.224.07:52:00.56#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.224.07:52:00.56#ibcon#about to clear, iclass 27 cls_cnt 0 2006.224.07:52:00.56#ibcon#cleared, iclass 27 cls_cnt 0 2006.224.07:52:00.56$vc4f8/vblo=1,632.99 2006.224.07:52:00.56#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.224.07:52:00.56#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.224.07:52:00.56#ibcon#ireg 17 cls_cnt 0 2006.224.07:52:00.56#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.224.07:52:00.56#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.224.07:52:00.56#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.224.07:52:00.56#ibcon#enter wrdev, iclass 29, count 0 2006.224.07:52:00.56#ibcon#first serial, iclass 29, count 0 2006.224.07:52:00.56#ibcon#enter sib2, iclass 29, count 0 2006.224.07:52:00.56#ibcon#flushed, iclass 29, count 0 2006.224.07:52:00.56#ibcon#about to write, iclass 29, count 0 2006.224.07:52:00.56#ibcon#wrote, iclass 29, count 0 2006.224.07:52:00.56#ibcon#about to read 3, iclass 29, count 0 2006.224.07:52:00.58#ibcon#read 3, iclass 29, count 0 2006.224.07:52:00.58#ibcon#about to read 4, iclass 29, count 0 2006.224.07:52:00.58#ibcon#read 4, iclass 29, count 0 2006.224.07:52:00.58#ibcon#about to read 5, iclass 29, count 0 2006.224.07:52:00.58#ibcon#read 5, iclass 29, count 0 2006.224.07:52:00.58#ibcon#about to read 6, iclass 29, count 0 2006.224.07:52:00.58#ibcon#read 6, iclass 29, count 0 2006.224.07:52:00.58#ibcon#end of sib2, iclass 29, count 0 2006.224.07:52:00.58#ibcon#*mode == 0, iclass 29, count 0 2006.224.07:52:00.58#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.224.07:52:00.58#ibcon#[28=FRQ=01,632.99\r\n] 2006.224.07:52:00.58#ibcon#*before write, iclass 29, count 0 2006.224.07:52:00.58#ibcon#enter sib2, iclass 29, count 0 2006.224.07:52:00.58#ibcon#flushed, iclass 29, count 0 2006.224.07:52:00.58#ibcon#about to write, iclass 29, count 0 2006.224.07:52:00.58#ibcon#wrote, iclass 29, count 0 2006.224.07:52:00.58#ibcon#about to read 3, iclass 29, count 0 2006.224.07:52:00.62#ibcon#read 3, iclass 29, count 0 2006.224.07:52:00.62#ibcon#about to read 4, iclass 29, count 0 2006.224.07:52:00.62#ibcon#read 4, iclass 29, count 0 2006.224.07:52:00.62#ibcon#about to read 5, iclass 29, count 0 2006.224.07:52:00.62#ibcon#read 5, iclass 29, count 0 2006.224.07:52:00.62#ibcon#about to read 6, iclass 29, count 0 2006.224.07:52:00.62#ibcon#read 6, iclass 29, count 0 2006.224.07:52:00.62#ibcon#end of sib2, iclass 29, count 0 2006.224.07:52:00.62#ibcon#*after write, iclass 29, count 0 2006.224.07:52:00.62#ibcon#*before return 0, iclass 29, count 0 2006.224.07:52:00.62#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.224.07:52:00.62#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.224.07:52:00.62#ibcon#about to clear, iclass 29 cls_cnt 0 2006.224.07:52:00.62#ibcon#cleared, iclass 29 cls_cnt 0 2006.224.07:52:00.62$vc4f8/vb=1,4 2006.224.07:52:00.62#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.224.07:52:00.62#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.224.07:52:00.62#ibcon#ireg 11 cls_cnt 2 2006.224.07:52:00.62#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.224.07:52:00.62#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.224.07:52:00.62#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.224.07:52:00.62#ibcon#enter wrdev, iclass 31, count 2 2006.224.07:52:00.62#ibcon#first serial, iclass 31, count 2 2006.224.07:52:00.62#ibcon#enter sib2, iclass 31, count 2 2006.224.07:52:00.62#ibcon#flushed, iclass 31, count 2 2006.224.07:52:00.62#ibcon#about to write, iclass 31, count 2 2006.224.07:52:00.62#ibcon#wrote, iclass 31, count 2 2006.224.07:52:00.62#ibcon#about to read 3, iclass 31, count 2 2006.224.07:52:00.64#ibcon#read 3, iclass 31, count 2 2006.224.07:52:00.64#ibcon#about to read 4, iclass 31, count 2 2006.224.07:52:00.64#ibcon#read 4, iclass 31, count 2 2006.224.07:52:00.64#ibcon#about to read 5, iclass 31, count 2 2006.224.07:52:00.64#ibcon#read 5, iclass 31, count 2 2006.224.07:52:00.64#ibcon#about to read 6, iclass 31, count 2 2006.224.07:52:00.64#ibcon#read 6, iclass 31, count 2 2006.224.07:52:00.64#ibcon#end of sib2, iclass 31, count 2 2006.224.07:52:00.64#ibcon#*mode == 0, iclass 31, count 2 2006.224.07:52:00.64#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.224.07:52:00.64#ibcon#[27=AT01-04\r\n] 2006.224.07:52:00.64#ibcon#*before write, iclass 31, count 2 2006.224.07:52:00.64#ibcon#enter sib2, iclass 31, count 2 2006.224.07:52:00.64#ibcon#flushed, iclass 31, count 2 2006.224.07:52:00.64#ibcon#about to write, iclass 31, count 2 2006.224.07:52:00.64#ibcon#wrote, iclass 31, count 2 2006.224.07:52:00.64#ibcon#about to read 3, iclass 31, count 2 2006.224.07:52:00.67#ibcon#read 3, iclass 31, count 2 2006.224.07:52:00.67#ibcon#about to read 4, iclass 31, count 2 2006.224.07:52:00.67#ibcon#read 4, iclass 31, count 2 2006.224.07:52:00.67#ibcon#about to read 5, iclass 31, count 2 2006.224.07:52:00.67#ibcon#read 5, iclass 31, count 2 2006.224.07:52:00.67#ibcon#about to read 6, iclass 31, count 2 2006.224.07:52:00.67#ibcon#read 6, iclass 31, count 2 2006.224.07:52:00.67#ibcon#end of sib2, iclass 31, count 2 2006.224.07:52:00.67#ibcon#*after write, iclass 31, count 2 2006.224.07:52:00.67#ibcon#*before return 0, iclass 31, count 2 2006.224.07:52:00.67#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.224.07:52:00.67#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.224.07:52:00.67#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.224.07:52:00.67#ibcon#ireg 7 cls_cnt 0 2006.224.07:52:00.67#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.224.07:52:00.79#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.224.07:52:00.79#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.224.07:52:00.79#ibcon#enter wrdev, iclass 31, count 0 2006.224.07:52:00.79#ibcon#first serial, iclass 31, count 0 2006.224.07:52:00.79#ibcon#enter sib2, iclass 31, count 0 2006.224.07:52:00.79#ibcon#flushed, iclass 31, count 0 2006.224.07:52:00.79#ibcon#about to write, iclass 31, count 0 2006.224.07:52:00.79#ibcon#wrote, iclass 31, count 0 2006.224.07:52:00.79#ibcon#about to read 3, iclass 31, count 0 2006.224.07:52:00.81#ibcon#read 3, iclass 31, count 0 2006.224.07:52:00.81#ibcon#about to read 4, iclass 31, count 0 2006.224.07:52:00.81#ibcon#read 4, iclass 31, count 0 2006.224.07:52:00.81#ibcon#about to read 5, iclass 31, count 0 2006.224.07:52:00.81#ibcon#read 5, iclass 31, count 0 2006.224.07:52:00.81#ibcon#about to read 6, iclass 31, count 0 2006.224.07:52:00.81#ibcon#read 6, iclass 31, count 0 2006.224.07:52:00.81#ibcon#end of sib2, iclass 31, count 0 2006.224.07:52:00.81#ibcon#*mode == 0, iclass 31, count 0 2006.224.07:52:00.81#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.224.07:52:00.81#ibcon#[27=USB\r\n] 2006.224.07:52:00.81#ibcon#*before write, iclass 31, count 0 2006.224.07:52:00.81#ibcon#enter sib2, iclass 31, count 0 2006.224.07:52:00.81#ibcon#flushed, iclass 31, count 0 2006.224.07:52:00.81#ibcon#about to write, iclass 31, count 0 2006.224.07:52:00.81#ibcon#wrote, iclass 31, count 0 2006.224.07:52:00.81#ibcon#about to read 3, iclass 31, count 0 2006.224.07:52:00.84#ibcon#read 3, iclass 31, count 0 2006.224.07:52:00.84#ibcon#about to read 4, iclass 31, count 0 2006.224.07:52:00.84#ibcon#read 4, iclass 31, count 0 2006.224.07:52:00.84#ibcon#about to read 5, iclass 31, count 0 2006.224.07:52:00.84#ibcon#read 5, iclass 31, count 0 2006.224.07:52:00.84#ibcon#about to read 6, iclass 31, count 0 2006.224.07:52:00.84#ibcon#read 6, iclass 31, count 0 2006.224.07:52:00.84#ibcon#end of sib2, iclass 31, count 0 2006.224.07:52:00.84#ibcon#*after write, iclass 31, count 0 2006.224.07:52:00.84#ibcon#*before return 0, iclass 31, count 0 2006.224.07:52:00.84#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.224.07:52:00.84#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.224.07:52:00.84#ibcon#about to clear, iclass 31 cls_cnt 0 2006.224.07:52:00.84#ibcon#cleared, iclass 31 cls_cnt 0 2006.224.07:52:00.84$vc4f8/vblo=2,640.99 2006.224.07:52:00.84#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.224.07:52:00.84#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.224.07:52:00.84#ibcon#ireg 17 cls_cnt 0 2006.224.07:52:00.84#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.224.07:52:00.84#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.224.07:52:00.84#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.224.07:52:00.84#ibcon#enter wrdev, iclass 33, count 0 2006.224.07:52:00.84#ibcon#first serial, iclass 33, count 0 2006.224.07:52:00.84#ibcon#enter sib2, iclass 33, count 0 2006.224.07:52:00.84#ibcon#flushed, iclass 33, count 0 2006.224.07:52:00.84#ibcon#about to write, iclass 33, count 0 2006.224.07:52:00.84#ibcon#wrote, iclass 33, count 0 2006.224.07:52:00.84#ibcon#about to read 3, iclass 33, count 0 2006.224.07:52:00.86#ibcon#read 3, iclass 33, count 0 2006.224.07:52:00.86#ibcon#about to read 4, iclass 33, count 0 2006.224.07:52:00.86#ibcon#read 4, iclass 33, count 0 2006.224.07:52:00.86#ibcon#about to read 5, iclass 33, count 0 2006.224.07:52:00.86#ibcon#read 5, iclass 33, count 0 2006.224.07:52:00.86#ibcon#about to read 6, iclass 33, count 0 2006.224.07:52:00.86#ibcon#read 6, iclass 33, count 0 2006.224.07:52:00.86#ibcon#end of sib2, iclass 33, count 0 2006.224.07:52:00.86#ibcon#*mode == 0, iclass 33, count 0 2006.224.07:52:00.86#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.224.07:52:00.86#ibcon#[28=FRQ=02,640.99\r\n] 2006.224.07:52:00.86#ibcon#*before write, iclass 33, count 0 2006.224.07:52:00.86#ibcon#enter sib2, iclass 33, count 0 2006.224.07:52:00.86#ibcon#flushed, iclass 33, count 0 2006.224.07:52:00.86#ibcon#about to write, iclass 33, count 0 2006.224.07:52:00.86#ibcon#wrote, iclass 33, count 0 2006.224.07:52:00.86#ibcon#about to read 3, iclass 33, count 0 2006.224.07:52:00.90#ibcon#read 3, iclass 33, count 0 2006.224.07:52:00.90#ibcon#about to read 4, iclass 33, count 0 2006.224.07:52:00.90#ibcon#read 4, iclass 33, count 0 2006.224.07:52:00.90#ibcon#about to read 5, iclass 33, count 0 2006.224.07:52:00.90#ibcon#read 5, iclass 33, count 0 2006.224.07:52:00.90#ibcon#about to read 6, iclass 33, count 0 2006.224.07:52:00.90#ibcon#read 6, iclass 33, count 0 2006.224.07:52:00.90#ibcon#end of sib2, iclass 33, count 0 2006.224.07:52:00.90#ibcon#*after write, iclass 33, count 0 2006.224.07:52:00.90#ibcon#*before return 0, iclass 33, count 0 2006.224.07:52:00.90#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.224.07:52:00.90#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.224.07:52:00.90#ibcon#about to clear, iclass 33 cls_cnt 0 2006.224.07:52:00.90#ibcon#cleared, iclass 33 cls_cnt 0 2006.224.07:52:00.90$vc4f8/vb=2,4 2006.224.07:52:00.90#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.224.07:52:00.90#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.224.07:52:00.90#ibcon#ireg 11 cls_cnt 2 2006.224.07:52:00.90#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.224.07:52:00.96#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.224.07:52:00.96#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.224.07:52:00.96#ibcon#enter wrdev, iclass 35, count 2 2006.224.07:52:00.96#ibcon#first serial, iclass 35, count 2 2006.224.07:52:00.96#ibcon#enter sib2, iclass 35, count 2 2006.224.07:52:00.96#ibcon#flushed, iclass 35, count 2 2006.224.07:52:00.96#ibcon#about to write, iclass 35, count 2 2006.224.07:52:00.96#ibcon#wrote, iclass 35, count 2 2006.224.07:52:00.96#ibcon#about to read 3, iclass 35, count 2 2006.224.07:52:00.98#ibcon#read 3, iclass 35, count 2 2006.224.07:52:00.98#ibcon#about to read 4, iclass 35, count 2 2006.224.07:52:00.98#ibcon#read 4, iclass 35, count 2 2006.224.07:52:00.98#ibcon#about to read 5, iclass 35, count 2 2006.224.07:52:00.98#ibcon#read 5, iclass 35, count 2 2006.224.07:52:00.98#ibcon#about to read 6, iclass 35, count 2 2006.224.07:52:00.98#ibcon#read 6, iclass 35, count 2 2006.224.07:52:00.98#ibcon#end of sib2, iclass 35, count 2 2006.224.07:52:00.98#ibcon#*mode == 0, iclass 35, count 2 2006.224.07:52:00.98#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.224.07:52:00.98#ibcon#[27=AT02-04\r\n] 2006.224.07:52:00.98#ibcon#*before write, iclass 35, count 2 2006.224.07:52:00.98#ibcon#enter sib2, iclass 35, count 2 2006.224.07:52:00.98#ibcon#flushed, iclass 35, count 2 2006.224.07:52:00.98#ibcon#about to write, iclass 35, count 2 2006.224.07:52:00.98#ibcon#wrote, iclass 35, count 2 2006.224.07:52:00.98#ibcon#about to read 3, iclass 35, count 2 2006.224.07:52:01.01#ibcon#read 3, iclass 35, count 2 2006.224.07:52:01.01#ibcon#about to read 4, iclass 35, count 2 2006.224.07:52:01.01#ibcon#read 4, iclass 35, count 2 2006.224.07:52:01.01#ibcon#about to read 5, iclass 35, count 2 2006.224.07:52:01.01#ibcon#read 5, iclass 35, count 2 2006.224.07:52:01.01#ibcon#about to read 6, iclass 35, count 2 2006.224.07:52:01.01#ibcon#read 6, iclass 35, count 2 2006.224.07:52:01.01#ibcon#end of sib2, iclass 35, count 2 2006.224.07:52:01.01#ibcon#*after write, iclass 35, count 2 2006.224.07:52:01.01#ibcon#*before return 0, iclass 35, count 2 2006.224.07:52:01.01#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.224.07:52:01.01#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.224.07:52:01.01#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.224.07:52:01.01#ibcon#ireg 7 cls_cnt 0 2006.224.07:52:01.01#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.224.07:52:01.13#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.224.07:52:01.13#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.224.07:52:01.13#ibcon#enter wrdev, iclass 35, count 0 2006.224.07:52:01.13#ibcon#first serial, iclass 35, count 0 2006.224.07:52:01.13#ibcon#enter sib2, iclass 35, count 0 2006.224.07:52:01.13#ibcon#flushed, iclass 35, count 0 2006.224.07:52:01.13#ibcon#about to write, iclass 35, count 0 2006.224.07:52:01.13#ibcon#wrote, iclass 35, count 0 2006.224.07:52:01.13#ibcon#about to read 3, iclass 35, count 0 2006.224.07:52:01.15#ibcon#read 3, iclass 35, count 0 2006.224.07:52:01.15#ibcon#about to read 4, iclass 35, count 0 2006.224.07:52:01.15#ibcon#read 4, iclass 35, count 0 2006.224.07:52:01.15#ibcon#about to read 5, iclass 35, count 0 2006.224.07:52:01.15#ibcon#read 5, iclass 35, count 0 2006.224.07:52:01.15#ibcon#about to read 6, iclass 35, count 0 2006.224.07:52:01.15#ibcon#read 6, iclass 35, count 0 2006.224.07:52:01.15#ibcon#end of sib2, iclass 35, count 0 2006.224.07:52:01.15#ibcon#*mode == 0, iclass 35, count 0 2006.224.07:52:01.15#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.224.07:52:01.15#ibcon#[27=USB\r\n] 2006.224.07:52:01.15#ibcon#*before write, iclass 35, count 0 2006.224.07:52:01.15#ibcon#enter sib2, iclass 35, count 0 2006.224.07:52:01.15#ibcon#flushed, iclass 35, count 0 2006.224.07:52:01.15#ibcon#about to write, iclass 35, count 0 2006.224.07:52:01.15#ibcon#wrote, iclass 35, count 0 2006.224.07:52:01.15#ibcon#about to read 3, iclass 35, count 0 2006.224.07:52:01.18#ibcon#read 3, iclass 35, count 0 2006.224.07:52:01.18#ibcon#about to read 4, iclass 35, count 0 2006.224.07:52:01.18#ibcon#read 4, iclass 35, count 0 2006.224.07:52:01.18#ibcon#about to read 5, iclass 35, count 0 2006.224.07:52:01.18#ibcon#read 5, iclass 35, count 0 2006.224.07:52:01.18#ibcon#about to read 6, iclass 35, count 0 2006.224.07:52:01.18#ibcon#read 6, iclass 35, count 0 2006.224.07:52:01.18#ibcon#end of sib2, iclass 35, count 0 2006.224.07:52:01.18#ibcon#*after write, iclass 35, count 0 2006.224.07:52:01.18#ibcon#*before return 0, iclass 35, count 0 2006.224.07:52:01.18#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.224.07:52:01.18#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.224.07:52:01.18#ibcon#about to clear, iclass 35 cls_cnt 0 2006.224.07:52:01.18#ibcon#cleared, iclass 35 cls_cnt 0 2006.224.07:52:01.18$vc4f8/vblo=3,656.99 2006.224.07:52:01.18#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.224.07:52:01.18#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.224.07:52:01.18#ibcon#ireg 17 cls_cnt 0 2006.224.07:52:01.18#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.224.07:52:01.18#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.224.07:52:01.18#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.224.07:52:01.18#ibcon#enter wrdev, iclass 37, count 0 2006.224.07:52:01.18#ibcon#first serial, iclass 37, count 0 2006.224.07:52:01.18#ibcon#enter sib2, iclass 37, count 0 2006.224.07:52:01.18#ibcon#flushed, iclass 37, count 0 2006.224.07:52:01.18#ibcon#about to write, iclass 37, count 0 2006.224.07:52:01.18#ibcon#wrote, iclass 37, count 0 2006.224.07:52:01.18#ibcon#about to read 3, iclass 37, count 0 2006.224.07:52:01.20#ibcon#read 3, iclass 37, count 0 2006.224.07:52:01.20#ibcon#about to read 4, iclass 37, count 0 2006.224.07:52:01.20#ibcon#read 4, iclass 37, count 0 2006.224.07:52:01.20#ibcon#about to read 5, iclass 37, count 0 2006.224.07:52:01.20#ibcon#read 5, iclass 37, count 0 2006.224.07:52:01.20#ibcon#about to read 6, iclass 37, count 0 2006.224.07:52:01.20#ibcon#read 6, iclass 37, count 0 2006.224.07:52:01.20#ibcon#end of sib2, iclass 37, count 0 2006.224.07:52:01.20#ibcon#*mode == 0, iclass 37, count 0 2006.224.07:52:01.20#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.224.07:52:01.20#ibcon#[28=FRQ=03,656.99\r\n] 2006.224.07:52:01.20#ibcon#*before write, iclass 37, count 0 2006.224.07:52:01.20#ibcon#enter sib2, iclass 37, count 0 2006.224.07:52:01.20#ibcon#flushed, iclass 37, count 0 2006.224.07:52:01.20#ibcon#about to write, iclass 37, count 0 2006.224.07:52:01.20#ibcon#wrote, iclass 37, count 0 2006.224.07:52:01.20#ibcon#about to read 3, iclass 37, count 0 2006.224.07:52:01.24#ibcon#read 3, iclass 37, count 0 2006.224.07:52:01.24#ibcon#about to read 4, iclass 37, count 0 2006.224.07:52:01.24#ibcon#read 4, iclass 37, count 0 2006.224.07:52:01.24#ibcon#about to read 5, iclass 37, count 0 2006.224.07:52:01.24#ibcon#read 5, iclass 37, count 0 2006.224.07:52:01.24#ibcon#about to read 6, iclass 37, count 0 2006.224.07:52:01.24#ibcon#read 6, iclass 37, count 0 2006.224.07:52:01.24#ibcon#end of sib2, iclass 37, count 0 2006.224.07:52:01.24#ibcon#*after write, iclass 37, count 0 2006.224.07:52:01.24#ibcon#*before return 0, iclass 37, count 0 2006.224.07:52:01.24#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.224.07:52:01.24#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.224.07:52:01.24#ibcon#about to clear, iclass 37 cls_cnt 0 2006.224.07:52:01.24#ibcon#cleared, iclass 37 cls_cnt 0 2006.224.07:52:01.24$vc4f8/vb=3,4 2006.224.07:52:01.24#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.224.07:52:01.24#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.224.07:52:01.24#ibcon#ireg 11 cls_cnt 2 2006.224.07:52:01.24#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.224.07:52:01.30#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.224.07:52:01.30#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.224.07:52:01.30#ibcon#enter wrdev, iclass 39, count 2 2006.224.07:52:01.30#ibcon#first serial, iclass 39, count 2 2006.224.07:52:01.30#ibcon#enter sib2, iclass 39, count 2 2006.224.07:52:01.30#ibcon#flushed, iclass 39, count 2 2006.224.07:52:01.30#ibcon#about to write, iclass 39, count 2 2006.224.07:52:01.30#ibcon#wrote, iclass 39, count 2 2006.224.07:52:01.30#ibcon#about to read 3, iclass 39, count 2 2006.224.07:52:01.32#ibcon#read 3, iclass 39, count 2 2006.224.07:52:01.32#ibcon#about to read 4, iclass 39, count 2 2006.224.07:52:01.32#ibcon#read 4, iclass 39, count 2 2006.224.07:52:01.32#ibcon#about to read 5, iclass 39, count 2 2006.224.07:52:01.32#ibcon#read 5, iclass 39, count 2 2006.224.07:52:01.32#ibcon#about to read 6, iclass 39, count 2 2006.224.07:52:01.32#ibcon#read 6, iclass 39, count 2 2006.224.07:52:01.32#ibcon#end of sib2, iclass 39, count 2 2006.224.07:52:01.32#ibcon#*mode == 0, iclass 39, count 2 2006.224.07:52:01.32#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.224.07:52:01.32#ibcon#[27=AT03-04\r\n] 2006.224.07:52:01.32#ibcon#*before write, iclass 39, count 2 2006.224.07:52:01.32#ibcon#enter sib2, iclass 39, count 2 2006.224.07:52:01.32#ibcon#flushed, iclass 39, count 2 2006.224.07:52:01.32#ibcon#about to write, iclass 39, count 2 2006.224.07:52:01.32#ibcon#wrote, iclass 39, count 2 2006.224.07:52:01.32#ibcon#about to read 3, iclass 39, count 2 2006.224.07:52:01.35#ibcon#read 3, iclass 39, count 2 2006.224.07:52:01.35#ibcon#about to read 4, iclass 39, count 2 2006.224.07:52:01.35#ibcon#read 4, iclass 39, count 2 2006.224.07:52:01.35#ibcon#about to read 5, iclass 39, count 2 2006.224.07:52:01.35#ibcon#read 5, iclass 39, count 2 2006.224.07:52:01.35#ibcon#about to read 6, iclass 39, count 2 2006.224.07:52:01.35#ibcon#read 6, iclass 39, count 2 2006.224.07:52:01.35#ibcon#end of sib2, iclass 39, count 2 2006.224.07:52:01.35#ibcon#*after write, iclass 39, count 2 2006.224.07:52:01.35#ibcon#*before return 0, iclass 39, count 2 2006.224.07:52:01.35#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.224.07:52:01.35#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.224.07:52:01.35#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.224.07:52:01.35#ibcon#ireg 7 cls_cnt 0 2006.224.07:52:01.35#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.224.07:52:01.47#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.224.07:52:01.47#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.224.07:52:01.47#ibcon#enter wrdev, iclass 39, count 0 2006.224.07:52:01.47#ibcon#first serial, iclass 39, count 0 2006.224.07:52:01.47#ibcon#enter sib2, iclass 39, count 0 2006.224.07:52:01.47#ibcon#flushed, iclass 39, count 0 2006.224.07:52:01.47#ibcon#about to write, iclass 39, count 0 2006.224.07:52:01.47#ibcon#wrote, iclass 39, count 0 2006.224.07:52:01.47#ibcon#about to read 3, iclass 39, count 0 2006.224.07:52:01.49#ibcon#read 3, iclass 39, count 0 2006.224.07:52:01.49#ibcon#about to read 4, iclass 39, count 0 2006.224.07:52:01.49#ibcon#read 4, iclass 39, count 0 2006.224.07:52:01.49#ibcon#about to read 5, iclass 39, count 0 2006.224.07:52:01.49#ibcon#read 5, iclass 39, count 0 2006.224.07:52:01.49#ibcon#about to read 6, iclass 39, count 0 2006.224.07:52:01.49#ibcon#read 6, iclass 39, count 0 2006.224.07:52:01.49#ibcon#end of sib2, iclass 39, count 0 2006.224.07:52:01.49#ibcon#*mode == 0, iclass 39, count 0 2006.224.07:52:01.49#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.224.07:52:01.49#ibcon#[27=USB\r\n] 2006.224.07:52:01.49#ibcon#*before write, iclass 39, count 0 2006.224.07:52:01.49#ibcon#enter sib2, iclass 39, count 0 2006.224.07:52:01.49#ibcon#flushed, iclass 39, count 0 2006.224.07:52:01.49#ibcon#about to write, iclass 39, count 0 2006.224.07:52:01.49#ibcon#wrote, iclass 39, count 0 2006.224.07:52:01.49#ibcon#about to read 3, iclass 39, count 0 2006.224.07:52:01.52#ibcon#read 3, iclass 39, count 0 2006.224.07:52:01.52#ibcon#about to read 4, iclass 39, count 0 2006.224.07:52:01.52#ibcon#read 4, iclass 39, count 0 2006.224.07:52:01.52#ibcon#about to read 5, iclass 39, count 0 2006.224.07:52:01.52#ibcon#read 5, iclass 39, count 0 2006.224.07:52:01.52#ibcon#about to read 6, iclass 39, count 0 2006.224.07:52:01.52#ibcon#read 6, iclass 39, count 0 2006.224.07:52:01.52#ibcon#end of sib2, iclass 39, count 0 2006.224.07:52:01.52#ibcon#*after write, iclass 39, count 0 2006.224.07:52:01.52#ibcon#*before return 0, iclass 39, count 0 2006.224.07:52:01.52#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.224.07:52:01.52#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.224.07:52:01.52#ibcon#about to clear, iclass 39 cls_cnt 0 2006.224.07:52:01.52#ibcon#cleared, iclass 39 cls_cnt 0 2006.224.07:52:01.52$vc4f8/vblo=4,712.99 2006.224.07:52:01.52#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.224.07:52:01.52#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.224.07:52:01.52#ibcon#ireg 17 cls_cnt 0 2006.224.07:52:01.52#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.224.07:52:01.52#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.224.07:52:01.52#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.224.07:52:01.52#ibcon#enter wrdev, iclass 3, count 0 2006.224.07:52:01.52#ibcon#first serial, iclass 3, count 0 2006.224.07:52:01.52#ibcon#enter sib2, iclass 3, count 0 2006.224.07:52:01.52#ibcon#flushed, iclass 3, count 0 2006.224.07:52:01.52#ibcon#about to write, iclass 3, count 0 2006.224.07:52:01.52#ibcon#wrote, iclass 3, count 0 2006.224.07:52:01.52#ibcon#about to read 3, iclass 3, count 0 2006.224.07:52:01.54#ibcon#read 3, iclass 3, count 0 2006.224.07:52:01.54#ibcon#about to read 4, iclass 3, count 0 2006.224.07:52:01.54#ibcon#read 4, iclass 3, count 0 2006.224.07:52:01.54#ibcon#about to read 5, iclass 3, count 0 2006.224.07:52:01.54#ibcon#read 5, iclass 3, count 0 2006.224.07:52:01.54#ibcon#about to read 6, iclass 3, count 0 2006.224.07:52:01.54#ibcon#read 6, iclass 3, count 0 2006.224.07:52:01.54#ibcon#end of sib2, iclass 3, count 0 2006.224.07:52:01.54#ibcon#*mode == 0, iclass 3, count 0 2006.224.07:52:01.54#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.224.07:52:01.54#ibcon#[28=FRQ=04,712.99\r\n] 2006.224.07:52:01.54#ibcon#*before write, iclass 3, count 0 2006.224.07:52:01.54#ibcon#enter sib2, iclass 3, count 0 2006.224.07:52:01.54#ibcon#flushed, iclass 3, count 0 2006.224.07:52:01.54#ibcon#about to write, iclass 3, count 0 2006.224.07:52:01.54#ibcon#wrote, iclass 3, count 0 2006.224.07:52:01.54#ibcon#about to read 3, iclass 3, count 0 2006.224.07:52:01.58#ibcon#read 3, iclass 3, count 0 2006.224.07:52:01.58#ibcon#about to read 4, iclass 3, count 0 2006.224.07:52:01.58#ibcon#read 4, iclass 3, count 0 2006.224.07:52:01.58#ibcon#about to read 5, iclass 3, count 0 2006.224.07:52:01.58#ibcon#read 5, iclass 3, count 0 2006.224.07:52:01.58#ibcon#about to read 6, iclass 3, count 0 2006.224.07:52:01.58#ibcon#read 6, iclass 3, count 0 2006.224.07:52:01.58#ibcon#end of sib2, iclass 3, count 0 2006.224.07:52:01.58#ibcon#*after write, iclass 3, count 0 2006.224.07:52:01.58#ibcon#*before return 0, iclass 3, count 0 2006.224.07:52:01.58#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.224.07:52:01.58#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.224.07:52:01.58#ibcon#about to clear, iclass 3 cls_cnt 0 2006.224.07:52:01.58#ibcon#cleared, iclass 3 cls_cnt 0 2006.224.07:52:01.58$vc4f8/vb=4,4 2006.224.07:52:01.58#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.224.07:52:01.58#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.224.07:52:01.58#ibcon#ireg 11 cls_cnt 2 2006.224.07:52:01.58#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.224.07:52:01.64#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.224.07:52:01.64#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.224.07:52:01.64#ibcon#enter wrdev, iclass 5, count 2 2006.224.07:52:01.64#ibcon#first serial, iclass 5, count 2 2006.224.07:52:01.64#ibcon#enter sib2, iclass 5, count 2 2006.224.07:52:01.64#ibcon#flushed, iclass 5, count 2 2006.224.07:52:01.64#ibcon#about to write, iclass 5, count 2 2006.224.07:52:01.64#ibcon#wrote, iclass 5, count 2 2006.224.07:52:01.64#ibcon#about to read 3, iclass 5, count 2 2006.224.07:52:01.66#ibcon#read 3, iclass 5, count 2 2006.224.07:52:01.66#ibcon#about to read 4, iclass 5, count 2 2006.224.07:52:01.66#ibcon#read 4, iclass 5, count 2 2006.224.07:52:01.66#ibcon#about to read 5, iclass 5, count 2 2006.224.07:52:01.66#ibcon#read 5, iclass 5, count 2 2006.224.07:52:01.66#ibcon#about to read 6, iclass 5, count 2 2006.224.07:52:01.66#ibcon#read 6, iclass 5, count 2 2006.224.07:52:01.66#ibcon#end of sib2, iclass 5, count 2 2006.224.07:52:01.66#ibcon#*mode == 0, iclass 5, count 2 2006.224.07:52:01.66#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.224.07:52:01.66#ibcon#[27=AT04-04\r\n] 2006.224.07:52:01.66#ibcon#*before write, iclass 5, count 2 2006.224.07:52:01.66#ibcon#enter sib2, iclass 5, count 2 2006.224.07:52:01.66#ibcon#flushed, iclass 5, count 2 2006.224.07:52:01.66#ibcon#about to write, iclass 5, count 2 2006.224.07:52:01.66#ibcon#wrote, iclass 5, count 2 2006.224.07:52:01.66#ibcon#about to read 3, iclass 5, count 2 2006.224.07:52:01.69#ibcon#read 3, iclass 5, count 2 2006.224.07:52:01.69#ibcon#about to read 4, iclass 5, count 2 2006.224.07:52:01.69#ibcon#read 4, iclass 5, count 2 2006.224.07:52:01.69#ibcon#about to read 5, iclass 5, count 2 2006.224.07:52:01.69#ibcon#read 5, iclass 5, count 2 2006.224.07:52:01.69#ibcon#about to read 6, iclass 5, count 2 2006.224.07:52:01.69#ibcon#read 6, iclass 5, count 2 2006.224.07:52:01.69#ibcon#end of sib2, iclass 5, count 2 2006.224.07:52:01.69#ibcon#*after write, iclass 5, count 2 2006.224.07:52:01.69#ibcon#*before return 0, iclass 5, count 2 2006.224.07:52:01.69#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.224.07:52:01.69#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.224.07:52:01.69#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.224.07:52:01.69#ibcon#ireg 7 cls_cnt 0 2006.224.07:52:01.69#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.224.07:52:01.81#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.224.07:52:01.81#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.224.07:52:01.81#ibcon#enter wrdev, iclass 5, count 0 2006.224.07:52:01.81#ibcon#first serial, iclass 5, count 0 2006.224.07:52:01.81#ibcon#enter sib2, iclass 5, count 0 2006.224.07:52:01.81#ibcon#flushed, iclass 5, count 0 2006.224.07:52:01.81#ibcon#about to write, iclass 5, count 0 2006.224.07:52:01.81#ibcon#wrote, iclass 5, count 0 2006.224.07:52:01.81#ibcon#about to read 3, iclass 5, count 0 2006.224.07:52:01.83#ibcon#read 3, iclass 5, count 0 2006.224.07:52:01.83#ibcon#about to read 4, iclass 5, count 0 2006.224.07:52:01.83#ibcon#read 4, iclass 5, count 0 2006.224.07:52:01.83#ibcon#about to read 5, iclass 5, count 0 2006.224.07:52:01.83#ibcon#read 5, iclass 5, count 0 2006.224.07:52:01.83#ibcon#about to read 6, iclass 5, count 0 2006.224.07:52:01.83#ibcon#read 6, iclass 5, count 0 2006.224.07:52:01.83#ibcon#end of sib2, iclass 5, count 0 2006.224.07:52:01.83#ibcon#*mode == 0, iclass 5, count 0 2006.224.07:52:01.83#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.224.07:52:01.83#ibcon#[27=USB\r\n] 2006.224.07:52:01.83#ibcon#*before write, iclass 5, count 0 2006.224.07:52:01.83#ibcon#enter sib2, iclass 5, count 0 2006.224.07:52:01.83#ibcon#flushed, iclass 5, count 0 2006.224.07:52:01.83#ibcon#about to write, iclass 5, count 0 2006.224.07:52:01.83#ibcon#wrote, iclass 5, count 0 2006.224.07:52:01.83#ibcon#about to read 3, iclass 5, count 0 2006.224.07:52:01.86#ibcon#read 3, iclass 5, count 0 2006.224.07:52:01.86#ibcon#about to read 4, iclass 5, count 0 2006.224.07:52:01.86#ibcon#read 4, iclass 5, count 0 2006.224.07:52:01.86#ibcon#about to read 5, iclass 5, count 0 2006.224.07:52:01.86#ibcon#read 5, iclass 5, count 0 2006.224.07:52:01.86#ibcon#about to read 6, iclass 5, count 0 2006.224.07:52:01.86#ibcon#read 6, iclass 5, count 0 2006.224.07:52:01.86#ibcon#end of sib2, iclass 5, count 0 2006.224.07:52:01.86#ibcon#*after write, iclass 5, count 0 2006.224.07:52:01.86#ibcon#*before return 0, iclass 5, count 0 2006.224.07:52:01.86#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.224.07:52:01.86#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.224.07:52:01.86#ibcon#about to clear, iclass 5 cls_cnt 0 2006.224.07:52:01.86#ibcon#cleared, iclass 5 cls_cnt 0 2006.224.07:52:01.86$vc4f8/vblo=5,744.99 2006.224.07:52:01.86#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.224.07:52:01.86#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.224.07:52:01.86#ibcon#ireg 17 cls_cnt 0 2006.224.07:52:01.86#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.224.07:52:01.86#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.224.07:52:01.86#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.224.07:52:01.86#ibcon#enter wrdev, iclass 7, count 0 2006.224.07:52:01.86#ibcon#first serial, iclass 7, count 0 2006.224.07:52:01.86#ibcon#enter sib2, iclass 7, count 0 2006.224.07:52:01.86#ibcon#flushed, iclass 7, count 0 2006.224.07:52:01.86#ibcon#about to write, iclass 7, count 0 2006.224.07:52:01.86#ibcon#wrote, iclass 7, count 0 2006.224.07:52:01.86#ibcon#about to read 3, iclass 7, count 0 2006.224.07:52:01.88#ibcon#read 3, iclass 7, count 0 2006.224.07:52:01.88#ibcon#about to read 4, iclass 7, count 0 2006.224.07:52:01.88#ibcon#read 4, iclass 7, count 0 2006.224.07:52:01.88#ibcon#about to read 5, iclass 7, count 0 2006.224.07:52:01.88#ibcon#read 5, iclass 7, count 0 2006.224.07:52:01.88#ibcon#about to read 6, iclass 7, count 0 2006.224.07:52:01.88#ibcon#read 6, iclass 7, count 0 2006.224.07:52:01.88#ibcon#end of sib2, iclass 7, count 0 2006.224.07:52:01.88#ibcon#*mode == 0, iclass 7, count 0 2006.224.07:52:01.88#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.224.07:52:01.88#ibcon#[28=FRQ=05,744.99\r\n] 2006.224.07:52:01.88#ibcon#*before write, iclass 7, count 0 2006.224.07:52:01.88#ibcon#enter sib2, iclass 7, count 0 2006.224.07:52:01.88#ibcon#flushed, iclass 7, count 0 2006.224.07:52:01.88#ibcon#about to write, iclass 7, count 0 2006.224.07:52:01.88#ibcon#wrote, iclass 7, count 0 2006.224.07:52:01.88#ibcon#about to read 3, iclass 7, count 0 2006.224.07:52:01.92#ibcon#read 3, iclass 7, count 0 2006.224.07:52:01.92#ibcon#about to read 4, iclass 7, count 0 2006.224.07:52:01.92#ibcon#read 4, iclass 7, count 0 2006.224.07:52:01.92#ibcon#about to read 5, iclass 7, count 0 2006.224.07:52:01.92#ibcon#read 5, iclass 7, count 0 2006.224.07:52:01.92#ibcon#about to read 6, iclass 7, count 0 2006.224.07:52:01.92#ibcon#read 6, iclass 7, count 0 2006.224.07:52:01.92#ibcon#end of sib2, iclass 7, count 0 2006.224.07:52:01.92#ibcon#*after write, iclass 7, count 0 2006.224.07:52:01.92#ibcon#*before return 0, iclass 7, count 0 2006.224.07:52:01.92#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.224.07:52:01.92#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.224.07:52:01.92#ibcon#about to clear, iclass 7 cls_cnt 0 2006.224.07:52:01.92#ibcon#cleared, iclass 7 cls_cnt 0 2006.224.07:52:01.92$vc4f8/vb=5,4 2006.224.07:52:01.92#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.224.07:52:01.92#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.224.07:52:01.92#ibcon#ireg 11 cls_cnt 2 2006.224.07:52:01.92#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.224.07:52:01.98#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.224.07:52:01.98#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.224.07:52:01.98#ibcon#enter wrdev, iclass 11, count 2 2006.224.07:52:01.98#ibcon#first serial, iclass 11, count 2 2006.224.07:52:01.98#ibcon#enter sib2, iclass 11, count 2 2006.224.07:52:01.98#ibcon#flushed, iclass 11, count 2 2006.224.07:52:01.98#ibcon#about to write, iclass 11, count 2 2006.224.07:52:01.98#ibcon#wrote, iclass 11, count 2 2006.224.07:52:01.98#ibcon#about to read 3, iclass 11, count 2 2006.224.07:52:02.00#ibcon#read 3, iclass 11, count 2 2006.224.07:52:02.00#ibcon#about to read 4, iclass 11, count 2 2006.224.07:52:02.00#ibcon#read 4, iclass 11, count 2 2006.224.07:52:02.00#ibcon#about to read 5, iclass 11, count 2 2006.224.07:52:02.00#ibcon#read 5, iclass 11, count 2 2006.224.07:52:02.00#ibcon#about to read 6, iclass 11, count 2 2006.224.07:52:02.00#ibcon#read 6, iclass 11, count 2 2006.224.07:52:02.00#ibcon#end of sib2, iclass 11, count 2 2006.224.07:52:02.00#ibcon#*mode == 0, iclass 11, count 2 2006.224.07:52:02.00#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.224.07:52:02.00#ibcon#[27=AT05-04\r\n] 2006.224.07:52:02.00#ibcon#*before write, iclass 11, count 2 2006.224.07:52:02.00#ibcon#enter sib2, iclass 11, count 2 2006.224.07:52:02.00#ibcon#flushed, iclass 11, count 2 2006.224.07:52:02.00#ibcon#about to write, iclass 11, count 2 2006.224.07:52:02.00#ibcon#wrote, iclass 11, count 2 2006.224.07:52:02.00#ibcon#about to read 3, iclass 11, count 2 2006.224.07:52:02.03#ibcon#read 3, iclass 11, count 2 2006.224.07:52:02.03#ibcon#about to read 4, iclass 11, count 2 2006.224.07:52:02.03#ibcon#read 4, iclass 11, count 2 2006.224.07:52:02.03#ibcon#about to read 5, iclass 11, count 2 2006.224.07:52:02.03#ibcon#read 5, iclass 11, count 2 2006.224.07:52:02.03#ibcon#about to read 6, iclass 11, count 2 2006.224.07:52:02.03#ibcon#read 6, iclass 11, count 2 2006.224.07:52:02.03#ibcon#end of sib2, iclass 11, count 2 2006.224.07:52:02.03#ibcon#*after write, iclass 11, count 2 2006.224.07:52:02.03#ibcon#*before return 0, iclass 11, count 2 2006.224.07:52:02.03#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.224.07:52:02.03#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.224.07:52:02.03#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.224.07:52:02.03#ibcon#ireg 7 cls_cnt 0 2006.224.07:52:02.03#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.224.07:52:02.15#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.224.07:52:02.15#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.224.07:52:02.15#ibcon#enter wrdev, iclass 11, count 0 2006.224.07:52:02.15#ibcon#first serial, iclass 11, count 0 2006.224.07:52:02.15#ibcon#enter sib2, iclass 11, count 0 2006.224.07:52:02.15#ibcon#flushed, iclass 11, count 0 2006.224.07:52:02.15#ibcon#about to write, iclass 11, count 0 2006.224.07:52:02.15#ibcon#wrote, iclass 11, count 0 2006.224.07:52:02.15#ibcon#about to read 3, iclass 11, count 0 2006.224.07:52:02.17#ibcon#read 3, iclass 11, count 0 2006.224.07:52:02.17#ibcon#about to read 4, iclass 11, count 0 2006.224.07:52:02.17#ibcon#read 4, iclass 11, count 0 2006.224.07:52:02.17#ibcon#about to read 5, iclass 11, count 0 2006.224.07:52:02.17#ibcon#read 5, iclass 11, count 0 2006.224.07:52:02.17#ibcon#about to read 6, iclass 11, count 0 2006.224.07:52:02.17#ibcon#read 6, iclass 11, count 0 2006.224.07:52:02.17#ibcon#end of sib2, iclass 11, count 0 2006.224.07:52:02.17#ibcon#*mode == 0, iclass 11, count 0 2006.224.07:52:02.17#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.224.07:52:02.17#ibcon#[27=USB\r\n] 2006.224.07:52:02.17#ibcon#*before write, iclass 11, count 0 2006.224.07:52:02.17#ibcon#enter sib2, iclass 11, count 0 2006.224.07:52:02.17#ibcon#flushed, iclass 11, count 0 2006.224.07:52:02.17#ibcon#about to write, iclass 11, count 0 2006.224.07:52:02.17#ibcon#wrote, iclass 11, count 0 2006.224.07:52:02.17#ibcon#about to read 3, iclass 11, count 0 2006.224.07:52:02.20#ibcon#read 3, iclass 11, count 0 2006.224.07:52:02.20#ibcon#about to read 4, iclass 11, count 0 2006.224.07:52:02.20#ibcon#read 4, iclass 11, count 0 2006.224.07:52:02.20#ibcon#about to read 5, iclass 11, count 0 2006.224.07:52:02.20#ibcon#read 5, iclass 11, count 0 2006.224.07:52:02.20#ibcon#about to read 6, iclass 11, count 0 2006.224.07:52:02.20#ibcon#read 6, iclass 11, count 0 2006.224.07:52:02.20#ibcon#end of sib2, iclass 11, count 0 2006.224.07:52:02.20#ibcon#*after write, iclass 11, count 0 2006.224.07:52:02.20#ibcon#*before return 0, iclass 11, count 0 2006.224.07:52:02.20#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.224.07:52:02.20#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.224.07:52:02.20#ibcon#about to clear, iclass 11 cls_cnt 0 2006.224.07:52:02.20#ibcon#cleared, iclass 11 cls_cnt 0 2006.224.07:52:02.20$vc4f8/vblo=6,752.99 2006.224.07:52:02.20#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.224.07:52:02.20#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.224.07:52:02.20#ibcon#ireg 17 cls_cnt 0 2006.224.07:52:02.20#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.224.07:52:02.20#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.224.07:52:02.20#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.224.07:52:02.20#ibcon#enter wrdev, iclass 13, count 0 2006.224.07:52:02.20#ibcon#first serial, iclass 13, count 0 2006.224.07:52:02.20#ibcon#enter sib2, iclass 13, count 0 2006.224.07:52:02.20#ibcon#flushed, iclass 13, count 0 2006.224.07:52:02.20#ibcon#about to write, iclass 13, count 0 2006.224.07:52:02.20#ibcon#wrote, iclass 13, count 0 2006.224.07:52:02.20#ibcon#about to read 3, iclass 13, count 0 2006.224.07:52:02.22#ibcon#read 3, iclass 13, count 0 2006.224.07:52:02.22#ibcon#about to read 4, iclass 13, count 0 2006.224.07:52:02.22#ibcon#read 4, iclass 13, count 0 2006.224.07:52:02.22#ibcon#about to read 5, iclass 13, count 0 2006.224.07:52:02.22#ibcon#read 5, iclass 13, count 0 2006.224.07:52:02.22#ibcon#about to read 6, iclass 13, count 0 2006.224.07:52:02.22#ibcon#read 6, iclass 13, count 0 2006.224.07:52:02.22#ibcon#end of sib2, iclass 13, count 0 2006.224.07:52:02.22#ibcon#*mode == 0, iclass 13, count 0 2006.224.07:52:02.22#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.224.07:52:02.22#ibcon#[28=FRQ=06,752.99\r\n] 2006.224.07:52:02.22#ibcon#*before write, iclass 13, count 0 2006.224.07:52:02.22#ibcon#enter sib2, iclass 13, count 0 2006.224.07:52:02.22#ibcon#flushed, iclass 13, count 0 2006.224.07:52:02.22#ibcon#about to write, iclass 13, count 0 2006.224.07:52:02.22#ibcon#wrote, iclass 13, count 0 2006.224.07:52:02.22#ibcon#about to read 3, iclass 13, count 0 2006.224.07:52:02.26#ibcon#read 3, iclass 13, count 0 2006.224.07:52:02.26#ibcon#about to read 4, iclass 13, count 0 2006.224.07:52:02.26#ibcon#read 4, iclass 13, count 0 2006.224.07:52:02.26#ibcon#about to read 5, iclass 13, count 0 2006.224.07:52:02.26#ibcon#read 5, iclass 13, count 0 2006.224.07:52:02.26#ibcon#about to read 6, iclass 13, count 0 2006.224.07:52:02.26#ibcon#read 6, iclass 13, count 0 2006.224.07:52:02.26#ibcon#end of sib2, iclass 13, count 0 2006.224.07:52:02.26#ibcon#*after write, iclass 13, count 0 2006.224.07:52:02.26#ibcon#*before return 0, iclass 13, count 0 2006.224.07:52:02.26#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.224.07:52:02.26#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.224.07:52:02.26#ibcon#about to clear, iclass 13 cls_cnt 0 2006.224.07:52:02.26#ibcon#cleared, iclass 13 cls_cnt 0 2006.224.07:52:02.26$vc4f8/vb=6,4 2006.224.07:52:02.26#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.224.07:52:02.26#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.224.07:52:02.26#ibcon#ireg 11 cls_cnt 2 2006.224.07:52:02.26#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.224.07:52:02.32#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.224.07:52:02.32#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.224.07:52:02.32#ibcon#enter wrdev, iclass 15, count 2 2006.224.07:52:02.32#ibcon#first serial, iclass 15, count 2 2006.224.07:52:02.32#ibcon#enter sib2, iclass 15, count 2 2006.224.07:52:02.32#ibcon#flushed, iclass 15, count 2 2006.224.07:52:02.32#ibcon#about to write, iclass 15, count 2 2006.224.07:52:02.32#ibcon#wrote, iclass 15, count 2 2006.224.07:52:02.32#ibcon#about to read 3, iclass 15, count 2 2006.224.07:52:02.34#ibcon#read 3, iclass 15, count 2 2006.224.07:52:02.34#ibcon#about to read 4, iclass 15, count 2 2006.224.07:52:02.34#ibcon#read 4, iclass 15, count 2 2006.224.07:52:02.34#ibcon#about to read 5, iclass 15, count 2 2006.224.07:52:02.34#ibcon#read 5, iclass 15, count 2 2006.224.07:52:02.34#ibcon#about to read 6, iclass 15, count 2 2006.224.07:52:02.34#ibcon#read 6, iclass 15, count 2 2006.224.07:52:02.34#ibcon#end of sib2, iclass 15, count 2 2006.224.07:52:02.34#ibcon#*mode == 0, iclass 15, count 2 2006.224.07:52:02.34#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.224.07:52:02.34#ibcon#[27=AT06-04\r\n] 2006.224.07:52:02.34#ibcon#*before write, iclass 15, count 2 2006.224.07:52:02.34#ibcon#enter sib2, iclass 15, count 2 2006.224.07:52:02.34#ibcon#flushed, iclass 15, count 2 2006.224.07:52:02.34#ibcon#about to write, iclass 15, count 2 2006.224.07:52:02.34#ibcon#wrote, iclass 15, count 2 2006.224.07:52:02.34#ibcon#about to read 3, iclass 15, count 2 2006.224.07:52:02.37#ibcon#read 3, iclass 15, count 2 2006.224.07:52:02.37#ibcon#about to read 4, iclass 15, count 2 2006.224.07:52:02.37#ibcon#read 4, iclass 15, count 2 2006.224.07:52:02.37#ibcon#about to read 5, iclass 15, count 2 2006.224.07:52:02.37#ibcon#read 5, iclass 15, count 2 2006.224.07:52:02.37#ibcon#about to read 6, iclass 15, count 2 2006.224.07:52:02.37#ibcon#read 6, iclass 15, count 2 2006.224.07:52:02.37#ibcon#end of sib2, iclass 15, count 2 2006.224.07:52:02.37#ibcon#*after write, iclass 15, count 2 2006.224.07:52:02.37#ibcon#*before return 0, iclass 15, count 2 2006.224.07:52:02.37#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.224.07:52:02.37#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.224.07:52:02.37#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.224.07:52:02.37#ibcon#ireg 7 cls_cnt 0 2006.224.07:52:02.37#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.224.07:52:02.49#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.224.07:52:02.49#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.224.07:52:02.49#ibcon#enter wrdev, iclass 15, count 0 2006.224.07:52:02.49#ibcon#first serial, iclass 15, count 0 2006.224.07:52:02.49#ibcon#enter sib2, iclass 15, count 0 2006.224.07:52:02.49#ibcon#flushed, iclass 15, count 0 2006.224.07:52:02.49#ibcon#about to write, iclass 15, count 0 2006.224.07:52:02.49#ibcon#wrote, iclass 15, count 0 2006.224.07:52:02.49#ibcon#about to read 3, iclass 15, count 0 2006.224.07:52:02.51#ibcon#read 3, iclass 15, count 0 2006.224.07:52:02.51#ibcon#about to read 4, iclass 15, count 0 2006.224.07:52:02.51#ibcon#read 4, iclass 15, count 0 2006.224.07:52:02.51#ibcon#about to read 5, iclass 15, count 0 2006.224.07:52:02.51#ibcon#read 5, iclass 15, count 0 2006.224.07:52:02.51#ibcon#about to read 6, iclass 15, count 0 2006.224.07:52:02.51#ibcon#read 6, iclass 15, count 0 2006.224.07:52:02.51#ibcon#end of sib2, iclass 15, count 0 2006.224.07:52:02.51#ibcon#*mode == 0, iclass 15, count 0 2006.224.07:52:02.51#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.224.07:52:02.51#ibcon#[27=USB\r\n] 2006.224.07:52:02.51#ibcon#*before write, iclass 15, count 0 2006.224.07:52:02.51#ibcon#enter sib2, iclass 15, count 0 2006.224.07:52:02.51#ibcon#flushed, iclass 15, count 0 2006.224.07:52:02.51#ibcon#about to write, iclass 15, count 0 2006.224.07:52:02.51#ibcon#wrote, iclass 15, count 0 2006.224.07:52:02.51#ibcon#about to read 3, iclass 15, count 0 2006.224.07:52:02.54#ibcon#read 3, iclass 15, count 0 2006.224.07:52:02.54#ibcon#about to read 4, iclass 15, count 0 2006.224.07:52:02.54#ibcon#read 4, iclass 15, count 0 2006.224.07:52:02.54#ibcon#about to read 5, iclass 15, count 0 2006.224.07:52:02.54#ibcon#read 5, iclass 15, count 0 2006.224.07:52:02.54#ibcon#about to read 6, iclass 15, count 0 2006.224.07:52:02.54#ibcon#read 6, iclass 15, count 0 2006.224.07:52:02.54#ibcon#end of sib2, iclass 15, count 0 2006.224.07:52:02.54#ibcon#*after write, iclass 15, count 0 2006.224.07:52:02.54#ibcon#*before return 0, iclass 15, count 0 2006.224.07:52:02.54#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.224.07:52:02.54#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.224.07:52:02.54#ibcon#about to clear, iclass 15 cls_cnt 0 2006.224.07:52:02.54#ibcon#cleared, iclass 15 cls_cnt 0 2006.224.07:52:02.54$vc4f8/vabw=wide 2006.224.07:52:02.54#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.224.07:52:02.54#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.224.07:52:02.54#ibcon#ireg 8 cls_cnt 0 2006.224.07:52:02.54#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.224.07:52:02.54#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.224.07:52:02.54#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.224.07:52:02.54#ibcon#enter wrdev, iclass 17, count 0 2006.224.07:52:02.54#ibcon#first serial, iclass 17, count 0 2006.224.07:52:02.54#ibcon#enter sib2, iclass 17, count 0 2006.224.07:52:02.54#ibcon#flushed, iclass 17, count 0 2006.224.07:52:02.54#ibcon#about to write, iclass 17, count 0 2006.224.07:52:02.54#ibcon#wrote, iclass 17, count 0 2006.224.07:52:02.54#ibcon#about to read 3, iclass 17, count 0 2006.224.07:52:02.56#ibcon#read 3, iclass 17, count 0 2006.224.07:52:02.56#ibcon#about to read 4, iclass 17, count 0 2006.224.07:52:02.56#ibcon#read 4, iclass 17, count 0 2006.224.07:52:02.56#ibcon#about to read 5, iclass 17, count 0 2006.224.07:52:02.56#ibcon#read 5, iclass 17, count 0 2006.224.07:52:02.56#ibcon#about to read 6, iclass 17, count 0 2006.224.07:52:02.56#ibcon#read 6, iclass 17, count 0 2006.224.07:52:02.56#ibcon#end of sib2, iclass 17, count 0 2006.224.07:52:02.56#ibcon#*mode == 0, iclass 17, count 0 2006.224.07:52:02.56#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.224.07:52:02.56#ibcon#[25=BW32\r\n] 2006.224.07:52:02.56#ibcon#*before write, iclass 17, count 0 2006.224.07:52:02.56#ibcon#enter sib2, iclass 17, count 0 2006.224.07:52:02.56#ibcon#flushed, iclass 17, count 0 2006.224.07:52:02.56#ibcon#about to write, iclass 17, count 0 2006.224.07:52:02.56#ibcon#wrote, iclass 17, count 0 2006.224.07:52:02.56#ibcon#about to read 3, iclass 17, count 0 2006.224.07:52:02.59#ibcon#read 3, iclass 17, count 0 2006.224.07:52:02.59#ibcon#about to read 4, iclass 17, count 0 2006.224.07:52:02.59#ibcon#read 4, iclass 17, count 0 2006.224.07:52:02.59#ibcon#about to read 5, iclass 17, count 0 2006.224.07:52:02.59#ibcon#read 5, iclass 17, count 0 2006.224.07:52:02.59#ibcon#about to read 6, iclass 17, count 0 2006.224.07:52:02.59#ibcon#read 6, iclass 17, count 0 2006.224.07:52:02.59#ibcon#end of sib2, iclass 17, count 0 2006.224.07:52:02.59#ibcon#*after write, iclass 17, count 0 2006.224.07:52:02.59#ibcon#*before return 0, iclass 17, count 0 2006.224.07:52:02.59#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.224.07:52:02.59#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.224.07:52:02.59#ibcon#about to clear, iclass 17 cls_cnt 0 2006.224.07:52:02.59#ibcon#cleared, iclass 17 cls_cnt 0 2006.224.07:52:02.59$vc4f8/vbbw=wide 2006.224.07:52:02.59#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.224.07:52:02.59#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.224.07:52:02.59#ibcon#ireg 8 cls_cnt 0 2006.224.07:52:02.59#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.224.07:52:02.66#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.224.07:52:02.66#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.224.07:52:02.66#ibcon#enter wrdev, iclass 19, count 0 2006.224.07:52:02.66#ibcon#first serial, iclass 19, count 0 2006.224.07:52:02.66#ibcon#enter sib2, iclass 19, count 0 2006.224.07:52:02.66#ibcon#flushed, iclass 19, count 0 2006.224.07:52:02.66#ibcon#about to write, iclass 19, count 0 2006.224.07:52:02.66#ibcon#wrote, iclass 19, count 0 2006.224.07:52:02.66#ibcon#about to read 3, iclass 19, count 0 2006.224.07:52:02.68#ibcon#read 3, iclass 19, count 0 2006.224.07:52:02.68#ibcon#about to read 4, iclass 19, count 0 2006.224.07:52:02.68#ibcon#read 4, iclass 19, count 0 2006.224.07:52:02.68#ibcon#about to read 5, iclass 19, count 0 2006.224.07:52:02.68#ibcon#read 5, iclass 19, count 0 2006.224.07:52:02.68#ibcon#about to read 6, iclass 19, count 0 2006.224.07:52:02.68#ibcon#read 6, iclass 19, count 0 2006.224.07:52:02.68#ibcon#end of sib2, iclass 19, count 0 2006.224.07:52:02.68#ibcon#*mode == 0, iclass 19, count 0 2006.224.07:52:02.68#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.224.07:52:02.68#ibcon#[27=BW32\r\n] 2006.224.07:52:02.68#ibcon#*before write, iclass 19, count 0 2006.224.07:52:02.68#ibcon#enter sib2, iclass 19, count 0 2006.224.07:52:02.68#ibcon#flushed, iclass 19, count 0 2006.224.07:52:02.68#ibcon#about to write, iclass 19, count 0 2006.224.07:52:02.68#ibcon#wrote, iclass 19, count 0 2006.224.07:52:02.68#ibcon#about to read 3, iclass 19, count 0 2006.224.07:52:02.71#ibcon#read 3, iclass 19, count 0 2006.224.07:52:02.71#ibcon#about to read 4, iclass 19, count 0 2006.224.07:52:02.71#ibcon#read 4, iclass 19, count 0 2006.224.07:52:02.71#ibcon#about to read 5, iclass 19, count 0 2006.224.07:52:02.71#ibcon#read 5, iclass 19, count 0 2006.224.07:52:02.71#ibcon#about to read 6, iclass 19, count 0 2006.224.07:52:02.71#ibcon#read 6, iclass 19, count 0 2006.224.07:52:02.71#ibcon#end of sib2, iclass 19, count 0 2006.224.07:52:02.71#ibcon#*after write, iclass 19, count 0 2006.224.07:52:02.71#ibcon#*before return 0, iclass 19, count 0 2006.224.07:52:02.71#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.224.07:52:02.71#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.224.07:52:02.71#ibcon#about to clear, iclass 19 cls_cnt 0 2006.224.07:52:02.71#ibcon#cleared, iclass 19 cls_cnt 0 2006.224.07:52:02.71$4f8m12a/ifd4f 2006.224.07:52:02.71$ifd4f/lo= 2006.224.07:52:02.71$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.224.07:52:02.71$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.224.07:52:02.71$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.224.07:52:02.71$ifd4f/patch= 2006.224.07:52:02.71$ifd4f/patch=lo1,a1,a2,a3,a4 2006.224.07:52:02.71$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.224.07:52:02.71$ifd4f/patch=lo3,a5,a6,a7,a8 2006.224.07:52:02.71$4f8m12a/"form=m,16.000,1:2 2006.224.07:52:02.71$4f8m12a/"tpicd 2006.224.07:52:02.71$4f8m12a/echo=off 2006.224.07:52:02.71$4f8m12a/xlog=off 2006.224.07:52:02.71:!2006.224.07:52:30 2006.224.07:52:12.14#trakl#Source acquired 2006.224.07:52:12.14#flagr#flagr/antenna,acquired 2006.224.07:52:30.00:preob 2006.224.07:52:31.14/onsource/TRACKING 2006.224.07:52:31.14:!2006.224.07:52:40 2006.224.07:52:40.00:data_valid=on 2006.224.07:52:40.00:midob 2006.224.07:52:40.14/onsource/TRACKING 2006.224.07:52:40.14/wx/23.62,1003.9,100 2006.224.07:52:40.33/cable/+6.4342E-03 2006.224.07:52:41.42/va/01,08,usb,yes,39,41 2006.224.07:52:41.42/va/02,07,usb,yes,40,42 2006.224.07:52:41.42/va/03,06,usb,yes,42,42 2006.224.07:52:41.42/va/04,07,usb,yes,42,45 2006.224.07:52:41.42/va/05,07,usb,yes,49,51 2006.224.07:52:41.42/va/06,06,usb,yes,48,48 2006.224.07:52:41.42/va/07,06,usb,yes,49,49 2006.224.07:52:41.42/va/08,07,usb,yes,46,46 2006.224.07:52:41.65/valo/01,532.99,yes,locked 2006.224.07:52:41.65/valo/02,572.99,yes,locked 2006.224.07:52:41.65/valo/03,672.99,yes,locked 2006.224.07:52:41.65/valo/04,832.99,yes,locked 2006.224.07:52:41.65/valo/05,652.99,yes,locked 2006.224.07:52:41.65/valo/06,772.99,yes,locked 2006.224.07:52:41.65/valo/07,832.99,yes,locked 2006.224.07:52:41.65/valo/08,852.99,yes,locked 2006.224.07:52:42.74/vb/01,04,usb,yes,31,30 2006.224.07:52:42.74/vb/02,04,usb,yes,33,35 2006.224.07:52:42.74/vb/03,04,usb,yes,30,33 2006.224.07:52:42.74/vb/04,04,usb,yes,30,31 2006.224.07:52:42.74/vb/05,04,usb,yes,29,33 2006.224.07:52:42.74/vb/06,04,usb,yes,30,33 2006.224.07:52:42.74/vb/07,04,usb,yes,32,32 2006.224.07:52:42.74/vb/08,04,usb,yes,29,33 2006.224.07:52:42.98/vblo/01,632.99,yes,locked 2006.224.07:52:42.98/vblo/02,640.99,yes,locked 2006.224.07:52:42.98/vblo/03,656.99,yes,locked 2006.224.07:52:42.98/vblo/04,712.99,yes,locked 2006.224.07:52:42.98/vblo/05,744.99,yes,locked 2006.224.07:52:42.98/vblo/06,752.99,yes,locked 2006.224.07:52:42.98/vblo/07,734.99,yes,locked 2006.224.07:52:42.98/vblo/08,744.99,yes,locked 2006.224.07:52:43.13/vabw/8 2006.224.07:52:43.28/vbbw/8 2006.224.07:52:43.37/xfe/off,on,15.2 2006.224.07:52:43.74/ifatt/23,28,28,28 2006.224.07:52:44.07/fmout-gps/S +4.28E-07 2006.224.07:52:44.11:!2006.224.07:53:40 2006.224.07:53:40.01:data_valid=off 2006.224.07:53:40.02:postob 2006.224.07:53:40.18/cable/+6.4344E-03 2006.224.07:53:40.18/wx/23.63,1003.8,100 2006.224.07:53:41.07/fmout-gps/S +4.29E-07 2006.224.07:53:41.07:scan_name=224-0755,k06224,60 2006.224.07:53:41.07:source=3c418,203837.03,511912.7,2000.0,cw 2006.224.07:53:41.13#flagr#flagr/antenna,new-source 2006.224.07:53:42.13:checkk5 2006.224.07:53:42.50/chk_autoobs//k5ts1/ autoobs is running! 2006.224.07:53:42.88/chk_autoobs//k5ts2/ autoobs is running! 2006.224.07:53:43.25/chk_autoobs//k5ts3/ autoobs is running! 2006.224.07:53:43.62/chk_autoobs//k5ts4/ autoobs is running! 2006.224.07:53:43.99/chk_obsdata//k5ts1/T2240752??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.07:53:44.36/chk_obsdata//k5ts2/T2240752??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.07:53:44.72/chk_obsdata//k5ts3/T2240752??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.07:53:45.09/chk_obsdata//k5ts4/T2240752??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.07:53:45.78/k5log//k5ts1_log_newline 2006.224.07:53:46.48/k5log//k5ts2_log_newline 2006.224.07:53:47.16/k5log//k5ts3_log_newline 2006.224.07:53:47.85/k5log//k5ts4_log_newline 2006.224.07:53:47.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.224.07:53:47.87:4f8m12a=2 2006.224.07:53:47.87$4f8m12a/echo=on 2006.224.07:53:47.87$4f8m12a/pcalon 2006.224.07:53:47.87$pcalon/"no phase cal control is implemented here 2006.224.07:53:47.87$4f8m12a/"tpicd=stop 2006.224.07:53:47.87$4f8m12a/vc4f8 2006.224.07:53:47.87$vc4f8/valo=1,532.99 2006.224.07:53:47.88#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.224.07:53:47.88#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.224.07:53:47.88#ibcon#ireg 17 cls_cnt 0 2006.224.07:53:47.88#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.224.07:53:47.88#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.224.07:53:47.88#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.224.07:53:47.88#ibcon#enter wrdev, iclass 21, count 0 2006.224.07:53:47.88#ibcon#first serial, iclass 21, count 0 2006.224.07:53:47.88#ibcon#enter sib2, iclass 21, count 0 2006.224.07:53:47.88#ibcon#flushed, iclass 21, count 0 2006.224.07:53:47.88#ibcon#about to write, iclass 21, count 0 2006.224.07:53:47.88#ibcon#wrote, iclass 21, count 0 2006.224.07:53:47.88#ibcon#about to read 3, iclass 21, count 0 2006.224.07:53:47.92#ibcon#read 3, iclass 21, count 0 2006.224.07:53:47.92#ibcon#about to read 4, iclass 21, count 0 2006.224.07:53:47.92#ibcon#read 4, iclass 21, count 0 2006.224.07:53:47.92#ibcon#about to read 5, iclass 21, count 0 2006.224.07:53:47.92#ibcon#read 5, iclass 21, count 0 2006.224.07:53:47.92#ibcon#about to read 6, iclass 21, count 0 2006.224.07:53:47.92#ibcon#read 6, iclass 21, count 0 2006.224.07:53:47.92#ibcon#end of sib2, iclass 21, count 0 2006.224.07:53:47.92#ibcon#*mode == 0, iclass 21, count 0 2006.224.07:53:47.92#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.224.07:53:47.92#ibcon#[26=FRQ=01,532.99\r\n] 2006.224.07:53:47.92#ibcon#*before write, iclass 21, count 0 2006.224.07:53:47.92#ibcon#enter sib2, iclass 21, count 0 2006.224.07:53:47.92#ibcon#flushed, iclass 21, count 0 2006.224.07:53:47.92#ibcon#about to write, iclass 21, count 0 2006.224.07:53:47.92#ibcon#wrote, iclass 21, count 0 2006.224.07:53:47.92#ibcon#about to read 3, iclass 21, count 0 2006.224.07:53:47.96#ibcon#read 3, iclass 21, count 0 2006.224.07:53:47.96#ibcon#about to read 4, iclass 21, count 0 2006.224.07:53:47.96#ibcon#read 4, iclass 21, count 0 2006.224.07:53:47.96#ibcon#about to read 5, iclass 21, count 0 2006.224.07:53:47.96#ibcon#read 5, iclass 21, count 0 2006.224.07:53:47.96#ibcon#about to read 6, iclass 21, count 0 2006.224.07:53:47.96#ibcon#read 6, iclass 21, count 0 2006.224.07:53:47.96#ibcon#end of sib2, iclass 21, count 0 2006.224.07:53:47.96#ibcon#*after write, iclass 21, count 0 2006.224.07:53:47.96#ibcon#*before return 0, iclass 21, count 0 2006.224.07:53:47.96#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.224.07:53:47.96#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.224.07:53:47.96#ibcon#about to clear, iclass 21 cls_cnt 0 2006.224.07:53:47.96#ibcon#cleared, iclass 21 cls_cnt 0 2006.224.07:53:47.96$vc4f8/va=1,8 2006.224.07:53:47.96#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.224.07:53:47.96#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.224.07:53:47.96#ibcon#ireg 11 cls_cnt 2 2006.224.07:53:47.96#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.224.07:53:47.96#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.224.07:53:47.96#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.224.07:53:47.96#ibcon#enter wrdev, iclass 23, count 2 2006.224.07:53:47.96#ibcon#first serial, iclass 23, count 2 2006.224.07:53:47.96#ibcon#enter sib2, iclass 23, count 2 2006.224.07:53:47.96#ibcon#flushed, iclass 23, count 2 2006.224.07:53:47.96#ibcon#about to write, iclass 23, count 2 2006.224.07:53:47.96#ibcon#wrote, iclass 23, count 2 2006.224.07:53:47.96#ibcon#about to read 3, iclass 23, count 2 2006.224.07:53:47.98#ibcon#read 3, iclass 23, count 2 2006.224.07:53:47.98#ibcon#about to read 4, iclass 23, count 2 2006.224.07:53:47.98#ibcon#read 4, iclass 23, count 2 2006.224.07:53:47.98#ibcon#about to read 5, iclass 23, count 2 2006.224.07:53:47.98#ibcon#read 5, iclass 23, count 2 2006.224.07:53:47.98#ibcon#about to read 6, iclass 23, count 2 2006.224.07:53:47.98#ibcon#read 6, iclass 23, count 2 2006.224.07:53:47.98#ibcon#end of sib2, iclass 23, count 2 2006.224.07:53:47.98#ibcon#*mode == 0, iclass 23, count 2 2006.224.07:53:47.98#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.224.07:53:47.98#ibcon#[25=AT01-08\r\n] 2006.224.07:53:47.98#ibcon#*before write, iclass 23, count 2 2006.224.07:53:47.98#ibcon#enter sib2, iclass 23, count 2 2006.224.07:53:47.98#ibcon#flushed, iclass 23, count 2 2006.224.07:53:47.98#ibcon#about to write, iclass 23, count 2 2006.224.07:53:47.98#ibcon#wrote, iclass 23, count 2 2006.224.07:53:47.98#ibcon#about to read 3, iclass 23, count 2 2006.224.07:53:48.01#ibcon#read 3, iclass 23, count 2 2006.224.07:53:48.01#ibcon#about to read 4, iclass 23, count 2 2006.224.07:53:48.01#ibcon#read 4, iclass 23, count 2 2006.224.07:53:48.01#ibcon#about to read 5, iclass 23, count 2 2006.224.07:53:48.01#ibcon#read 5, iclass 23, count 2 2006.224.07:53:48.01#ibcon#about to read 6, iclass 23, count 2 2006.224.07:53:48.01#ibcon#read 6, iclass 23, count 2 2006.224.07:53:48.01#ibcon#end of sib2, iclass 23, count 2 2006.224.07:53:48.01#ibcon#*after write, iclass 23, count 2 2006.224.07:53:48.01#ibcon#*before return 0, iclass 23, count 2 2006.224.07:53:48.01#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.224.07:53:48.01#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.224.07:53:48.01#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.224.07:53:48.01#ibcon#ireg 7 cls_cnt 0 2006.224.07:53:48.01#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.224.07:53:48.13#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.224.07:53:48.13#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.224.07:53:48.13#ibcon#enter wrdev, iclass 23, count 0 2006.224.07:53:48.13#ibcon#first serial, iclass 23, count 0 2006.224.07:53:48.13#ibcon#enter sib2, iclass 23, count 0 2006.224.07:53:48.13#ibcon#flushed, iclass 23, count 0 2006.224.07:53:48.13#ibcon#about to write, iclass 23, count 0 2006.224.07:53:48.13#ibcon#wrote, iclass 23, count 0 2006.224.07:53:48.13#ibcon#about to read 3, iclass 23, count 0 2006.224.07:53:48.14#abcon#<5=/05 0.9 2.1 23.631001003.9\r\n> 2006.224.07:53:48.15#ibcon#read 3, iclass 23, count 0 2006.224.07:53:48.15#ibcon#about to read 4, iclass 23, count 0 2006.224.07:53:48.15#ibcon#read 4, iclass 23, count 0 2006.224.07:53:48.15#ibcon#about to read 5, iclass 23, count 0 2006.224.07:53:48.15#ibcon#read 5, iclass 23, count 0 2006.224.07:53:48.15#ibcon#about to read 6, iclass 23, count 0 2006.224.07:53:48.15#ibcon#read 6, iclass 23, count 0 2006.224.07:53:48.15#ibcon#end of sib2, iclass 23, count 0 2006.224.07:53:48.15#ibcon#*mode == 0, iclass 23, count 0 2006.224.07:53:48.15#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.224.07:53:48.15#ibcon#[25=USB\r\n] 2006.224.07:53:48.15#ibcon#*before write, iclass 23, count 0 2006.224.07:53:48.15#ibcon#enter sib2, iclass 23, count 0 2006.224.07:53:48.15#ibcon#flushed, iclass 23, count 0 2006.224.07:53:48.15#ibcon#about to write, iclass 23, count 0 2006.224.07:53:48.15#ibcon#wrote, iclass 23, count 0 2006.224.07:53:48.15#ibcon#about to read 3, iclass 23, count 0 2006.224.07:53:48.16#abcon#{5=INTERFACE CLEAR} 2006.224.07:53:48.18#ibcon#read 3, iclass 23, count 0 2006.224.07:53:48.18#ibcon#about to read 4, iclass 23, count 0 2006.224.07:53:48.18#ibcon#read 4, iclass 23, count 0 2006.224.07:53:48.18#ibcon#about to read 5, iclass 23, count 0 2006.224.07:53:48.18#ibcon#read 5, iclass 23, count 0 2006.224.07:53:48.18#ibcon#about to read 6, iclass 23, count 0 2006.224.07:53:48.18#ibcon#read 6, iclass 23, count 0 2006.224.07:53:48.18#ibcon#end of sib2, iclass 23, count 0 2006.224.07:53:48.18#ibcon#*after write, iclass 23, count 0 2006.224.07:53:48.18#ibcon#*before return 0, iclass 23, count 0 2006.224.07:53:48.18#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.224.07:53:48.18#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.224.07:53:48.18#ibcon#about to clear, iclass 23 cls_cnt 0 2006.224.07:53:48.18#ibcon#cleared, iclass 23 cls_cnt 0 2006.224.07:53:48.18$vc4f8/valo=2,572.99 2006.224.07:53:48.18#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.224.07:53:48.18#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.224.07:53:48.18#ibcon#ireg 17 cls_cnt 0 2006.224.07:53:48.18#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.224.07:53:48.18#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.224.07:53:48.18#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.224.07:53:48.18#ibcon#enter wrdev, iclass 28, count 0 2006.224.07:53:48.18#ibcon#first serial, iclass 28, count 0 2006.224.07:53:48.18#ibcon#enter sib2, iclass 28, count 0 2006.224.07:53:48.18#ibcon#flushed, iclass 28, count 0 2006.224.07:53:48.18#ibcon#about to write, iclass 28, count 0 2006.224.07:53:48.18#ibcon#wrote, iclass 28, count 0 2006.224.07:53:48.18#ibcon#about to read 3, iclass 28, count 0 2006.224.07:53:48.20#ibcon#read 3, iclass 28, count 0 2006.224.07:53:48.20#ibcon#about to read 4, iclass 28, count 0 2006.224.07:53:48.20#ibcon#read 4, iclass 28, count 0 2006.224.07:53:48.20#ibcon#about to read 5, iclass 28, count 0 2006.224.07:53:48.20#ibcon#read 5, iclass 28, count 0 2006.224.07:53:48.20#ibcon#about to read 6, iclass 28, count 0 2006.224.07:53:48.20#ibcon#read 6, iclass 28, count 0 2006.224.07:53:48.20#ibcon#end of sib2, iclass 28, count 0 2006.224.07:53:48.20#ibcon#*mode == 0, iclass 28, count 0 2006.224.07:53:48.20#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.224.07:53:48.20#ibcon#[26=FRQ=02,572.99\r\n] 2006.224.07:53:48.20#ibcon#*before write, iclass 28, count 0 2006.224.07:53:48.20#ibcon#enter sib2, iclass 28, count 0 2006.224.07:53:48.20#ibcon#flushed, iclass 28, count 0 2006.224.07:53:48.20#ibcon#about to write, iclass 28, count 0 2006.224.07:53:48.20#ibcon#wrote, iclass 28, count 0 2006.224.07:53:48.20#ibcon#about to read 3, iclass 28, count 0 2006.224.07:53:48.22#abcon#[5=S1D000X0/0*\r\n] 2006.224.07:53:48.24#ibcon#read 3, iclass 28, count 0 2006.224.07:53:48.24#ibcon#about to read 4, iclass 28, count 0 2006.224.07:53:48.24#ibcon#read 4, iclass 28, count 0 2006.224.07:53:48.24#ibcon#about to read 5, iclass 28, count 0 2006.224.07:53:48.24#ibcon#read 5, iclass 28, count 0 2006.224.07:53:48.24#ibcon#about to read 6, iclass 28, count 0 2006.224.07:53:48.24#ibcon#read 6, iclass 28, count 0 2006.224.07:53:48.24#ibcon#end of sib2, iclass 28, count 0 2006.224.07:53:48.24#ibcon#*after write, iclass 28, count 0 2006.224.07:53:48.24#ibcon#*before return 0, iclass 28, count 0 2006.224.07:53:48.24#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.224.07:53:48.24#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.224.07:53:48.24#ibcon#about to clear, iclass 28 cls_cnt 0 2006.224.07:53:48.24#ibcon#cleared, iclass 28 cls_cnt 0 2006.224.07:53:48.24$vc4f8/va=2,7 2006.224.07:53:48.24#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.224.07:53:48.24#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.224.07:53:48.24#ibcon#ireg 11 cls_cnt 2 2006.224.07:53:48.24#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.224.07:53:48.31#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.224.07:53:48.31#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.224.07:53:48.31#ibcon#enter wrdev, iclass 31, count 2 2006.224.07:53:48.31#ibcon#first serial, iclass 31, count 2 2006.224.07:53:48.31#ibcon#enter sib2, iclass 31, count 2 2006.224.07:53:48.31#ibcon#flushed, iclass 31, count 2 2006.224.07:53:48.31#ibcon#about to write, iclass 31, count 2 2006.224.07:53:48.31#ibcon#wrote, iclass 31, count 2 2006.224.07:53:48.31#ibcon#about to read 3, iclass 31, count 2 2006.224.07:53:48.32#ibcon#read 3, iclass 31, count 2 2006.224.07:53:48.32#ibcon#about to read 4, iclass 31, count 2 2006.224.07:53:48.32#ibcon#read 4, iclass 31, count 2 2006.224.07:53:48.32#ibcon#about to read 5, iclass 31, count 2 2006.224.07:53:48.32#ibcon#read 5, iclass 31, count 2 2006.224.07:53:48.32#ibcon#about to read 6, iclass 31, count 2 2006.224.07:53:48.32#ibcon#read 6, iclass 31, count 2 2006.224.07:53:48.32#ibcon#end of sib2, iclass 31, count 2 2006.224.07:53:48.32#ibcon#*mode == 0, iclass 31, count 2 2006.224.07:53:48.32#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.224.07:53:48.32#ibcon#[25=AT02-07\r\n] 2006.224.07:53:48.32#ibcon#*before write, iclass 31, count 2 2006.224.07:53:48.32#ibcon#enter sib2, iclass 31, count 2 2006.224.07:53:48.32#ibcon#flushed, iclass 31, count 2 2006.224.07:53:48.32#ibcon#about to write, iclass 31, count 2 2006.224.07:53:48.32#ibcon#wrote, iclass 31, count 2 2006.224.07:53:48.32#ibcon#about to read 3, iclass 31, count 2 2006.224.07:53:48.35#ibcon#read 3, iclass 31, count 2 2006.224.07:53:48.35#ibcon#about to read 4, iclass 31, count 2 2006.224.07:53:48.35#ibcon#read 4, iclass 31, count 2 2006.224.07:53:48.35#ibcon#about to read 5, iclass 31, count 2 2006.224.07:53:48.35#ibcon#read 5, iclass 31, count 2 2006.224.07:53:48.35#ibcon#about to read 6, iclass 31, count 2 2006.224.07:53:48.35#ibcon#read 6, iclass 31, count 2 2006.224.07:53:48.35#ibcon#end of sib2, iclass 31, count 2 2006.224.07:53:48.35#ibcon#*after write, iclass 31, count 2 2006.224.07:53:48.35#ibcon#*before return 0, iclass 31, count 2 2006.224.07:53:48.35#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.224.07:53:48.35#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.224.07:53:48.35#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.224.07:53:48.35#ibcon#ireg 7 cls_cnt 0 2006.224.07:53:48.35#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.224.07:53:48.47#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.224.07:53:48.47#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.224.07:53:48.47#ibcon#enter wrdev, iclass 31, count 0 2006.224.07:53:48.47#ibcon#first serial, iclass 31, count 0 2006.224.07:53:48.47#ibcon#enter sib2, iclass 31, count 0 2006.224.07:53:48.47#ibcon#flushed, iclass 31, count 0 2006.224.07:53:48.47#ibcon#about to write, iclass 31, count 0 2006.224.07:53:48.47#ibcon#wrote, iclass 31, count 0 2006.224.07:53:48.47#ibcon#about to read 3, iclass 31, count 0 2006.224.07:53:48.49#ibcon#read 3, iclass 31, count 0 2006.224.07:53:48.49#ibcon#about to read 4, iclass 31, count 0 2006.224.07:53:48.49#ibcon#read 4, iclass 31, count 0 2006.224.07:53:48.49#ibcon#about to read 5, iclass 31, count 0 2006.224.07:53:48.49#ibcon#read 5, iclass 31, count 0 2006.224.07:53:48.49#ibcon#about to read 6, iclass 31, count 0 2006.224.07:53:48.49#ibcon#read 6, iclass 31, count 0 2006.224.07:53:48.49#ibcon#end of sib2, iclass 31, count 0 2006.224.07:53:48.49#ibcon#*mode == 0, iclass 31, count 0 2006.224.07:53:48.49#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.224.07:53:48.49#ibcon#[25=USB\r\n] 2006.224.07:53:48.49#ibcon#*before write, iclass 31, count 0 2006.224.07:53:48.49#ibcon#enter sib2, iclass 31, count 0 2006.224.07:53:48.49#ibcon#flushed, iclass 31, count 0 2006.224.07:53:48.49#ibcon#about to write, iclass 31, count 0 2006.224.07:53:48.49#ibcon#wrote, iclass 31, count 0 2006.224.07:53:48.49#ibcon#about to read 3, iclass 31, count 0 2006.224.07:53:48.52#ibcon#read 3, iclass 31, count 0 2006.224.07:53:48.52#ibcon#about to read 4, iclass 31, count 0 2006.224.07:53:48.52#ibcon#read 4, iclass 31, count 0 2006.224.07:53:48.52#ibcon#about to read 5, iclass 31, count 0 2006.224.07:53:48.52#ibcon#read 5, iclass 31, count 0 2006.224.07:53:48.52#ibcon#about to read 6, iclass 31, count 0 2006.224.07:53:48.52#ibcon#read 6, iclass 31, count 0 2006.224.07:53:48.52#ibcon#end of sib2, iclass 31, count 0 2006.224.07:53:48.52#ibcon#*after write, iclass 31, count 0 2006.224.07:53:48.52#ibcon#*before return 0, iclass 31, count 0 2006.224.07:53:48.52#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.224.07:53:48.52#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.224.07:53:48.52#ibcon#about to clear, iclass 31 cls_cnt 0 2006.224.07:53:48.52#ibcon#cleared, iclass 31 cls_cnt 0 2006.224.07:53:48.52$vc4f8/valo=3,672.99 2006.224.07:53:48.52#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.224.07:53:48.52#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.224.07:53:48.52#ibcon#ireg 17 cls_cnt 0 2006.224.07:53:48.52#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.224.07:53:48.52#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.224.07:53:48.52#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.224.07:53:48.52#ibcon#enter wrdev, iclass 33, count 0 2006.224.07:53:48.52#ibcon#first serial, iclass 33, count 0 2006.224.07:53:48.52#ibcon#enter sib2, iclass 33, count 0 2006.224.07:53:48.52#ibcon#flushed, iclass 33, count 0 2006.224.07:53:48.52#ibcon#about to write, iclass 33, count 0 2006.224.07:53:48.52#ibcon#wrote, iclass 33, count 0 2006.224.07:53:48.52#ibcon#about to read 3, iclass 33, count 0 2006.224.07:53:48.54#ibcon#read 3, iclass 33, count 0 2006.224.07:53:48.54#ibcon#about to read 4, iclass 33, count 0 2006.224.07:53:48.54#ibcon#read 4, iclass 33, count 0 2006.224.07:53:48.54#ibcon#about to read 5, iclass 33, count 0 2006.224.07:53:48.54#ibcon#read 5, iclass 33, count 0 2006.224.07:53:48.54#ibcon#about to read 6, iclass 33, count 0 2006.224.07:53:48.54#ibcon#read 6, iclass 33, count 0 2006.224.07:53:48.54#ibcon#end of sib2, iclass 33, count 0 2006.224.07:53:48.54#ibcon#*mode == 0, iclass 33, count 0 2006.224.07:53:48.54#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.224.07:53:48.54#ibcon#[26=FRQ=03,672.99\r\n] 2006.224.07:53:48.54#ibcon#*before write, iclass 33, count 0 2006.224.07:53:48.54#ibcon#enter sib2, iclass 33, count 0 2006.224.07:53:48.54#ibcon#flushed, iclass 33, count 0 2006.224.07:53:48.54#ibcon#about to write, iclass 33, count 0 2006.224.07:53:48.54#ibcon#wrote, iclass 33, count 0 2006.224.07:53:48.54#ibcon#about to read 3, iclass 33, count 0 2006.224.07:53:48.58#ibcon#read 3, iclass 33, count 0 2006.224.07:53:48.58#ibcon#about to read 4, iclass 33, count 0 2006.224.07:53:48.58#ibcon#read 4, iclass 33, count 0 2006.224.07:53:48.58#ibcon#about to read 5, iclass 33, count 0 2006.224.07:53:48.58#ibcon#read 5, iclass 33, count 0 2006.224.07:53:48.58#ibcon#about to read 6, iclass 33, count 0 2006.224.07:53:48.58#ibcon#read 6, iclass 33, count 0 2006.224.07:53:48.58#ibcon#end of sib2, iclass 33, count 0 2006.224.07:53:48.58#ibcon#*after write, iclass 33, count 0 2006.224.07:53:48.58#ibcon#*before return 0, iclass 33, count 0 2006.224.07:53:48.58#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.224.07:53:48.58#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.224.07:53:48.58#ibcon#about to clear, iclass 33 cls_cnt 0 2006.224.07:53:48.58#ibcon#cleared, iclass 33 cls_cnt 0 2006.224.07:53:48.58$vc4f8/va=3,6 2006.224.07:53:48.58#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.224.07:53:48.58#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.224.07:53:48.58#ibcon#ireg 11 cls_cnt 2 2006.224.07:53:48.58#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.224.07:53:48.65#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.224.07:53:48.65#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.224.07:53:48.65#ibcon#enter wrdev, iclass 35, count 2 2006.224.07:53:48.65#ibcon#first serial, iclass 35, count 2 2006.224.07:53:48.65#ibcon#enter sib2, iclass 35, count 2 2006.224.07:53:48.65#ibcon#flushed, iclass 35, count 2 2006.224.07:53:48.65#ibcon#about to write, iclass 35, count 2 2006.224.07:53:48.65#ibcon#wrote, iclass 35, count 2 2006.224.07:53:48.65#ibcon#about to read 3, iclass 35, count 2 2006.224.07:53:48.66#ibcon#read 3, iclass 35, count 2 2006.224.07:53:48.66#ibcon#about to read 4, iclass 35, count 2 2006.224.07:53:48.66#ibcon#read 4, iclass 35, count 2 2006.224.07:53:48.66#ibcon#about to read 5, iclass 35, count 2 2006.224.07:53:48.66#ibcon#read 5, iclass 35, count 2 2006.224.07:53:48.66#ibcon#about to read 6, iclass 35, count 2 2006.224.07:53:48.66#ibcon#read 6, iclass 35, count 2 2006.224.07:53:48.66#ibcon#end of sib2, iclass 35, count 2 2006.224.07:53:48.66#ibcon#*mode == 0, iclass 35, count 2 2006.224.07:53:48.66#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.224.07:53:48.66#ibcon#[25=AT03-06\r\n] 2006.224.07:53:48.66#ibcon#*before write, iclass 35, count 2 2006.224.07:53:48.66#ibcon#enter sib2, iclass 35, count 2 2006.224.07:53:48.66#ibcon#flushed, iclass 35, count 2 2006.224.07:53:48.66#ibcon#about to write, iclass 35, count 2 2006.224.07:53:48.66#ibcon#wrote, iclass 35, count 2 2006.224.07:53:48.66#ibcon#about to read 3, iclass 35, count 2 2006.224.07:53:48.69#ibcon#read 3, iclass 35, count 2 2006.224.07:53:48.69#ibcon#about to read 4, iclass 35, count 2 2006.224.07:53:48.69#ibcon#read 4, iclass 35, count 2 2006.224.07:53:48.69#ibcon#about to read 5, iclass 35, count 2 2006.224.07:53:48.69#ibcon#read 5, iclass 35, count 2 2006.224.07:53:48.69#ibcon#about to read 6, iclass 35, count 2 2006.224.07:53:48.69#ibcon#read 6, iclass 35, count 2 2006.224.07:53:48.69#ibcon#end of sib2, iclass 35, count 2 2006.224.07:53:48.69#ibcon#*after write, iclass 35, count 2 2006.224.07:53:48.69#ibcon#*before return 0, iclass 35, count 2 2006.224.07:53:48.69#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.224.07:53:48.69#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.224.07:53:48.69#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.224.07:53:48.69#ibcon#ireg 7 cls_cnt 0 2006.224.07:53:48.69#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.224.07:53:48.81#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.224.07:53:48.81#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.224.07:53:48.81#ibcon#enter wrdev, iclass 35, count 0 2006.224.07:53:48.81#ibcon#first serial, iclass 35, count 0 2006.224.07:53:48.81#ibcon#enter sib2, iclass 35, count 0 2006.224.07:53:48.81#ibcon#flushed, iclass 35, count 0 2006.224.07:53:48.81#ibcon#about to write, iclass 35, count 0 2006.224.07:53:48.81#ibcon#wrote, iclass 35, count 0 2006.224.07:53:48.81#ibcon#about to read 3, iclass 35, count 0 2006.224.07:53:48.83#ibcon#read 3, iclass 35, count 0 2006.224.07:53:48.83#ibcon#about to read 4, iclass 35, count 0 2006.224.07:53:48.83#ibcon#read 4, iclass 35, count 0 2006.224.07:53:48.83#ibcon#about to read 5, iclass 35, count 0 2006.224.07:53:48.83#ibcon#read 5, iclass 35, count 0 2006.224.07:53:48.83#ibcon#about to read 6, iclass 35, count 0 2006.224.07:53:48.83#ibcon#read 6, iclass 35, count 0 2006.224.07:53:48.83#ibcon#end of sib2, iclass 35, count 0 2006.224.07:53:48.83#ibcon#*mode == 0, iclass 35, count 0 2006.224.07:53:48.83#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.224.07:53:48.83#ibcon#[25=USB\r\n] 2006.224.07:53:48.83#ibcon#*before write, iclass 35, count 0 2006.224.07:53:48.83#ibcon#enter sib2, iclass 35, count 0 2006.224.07:53:48.83#ibcon#flushed, iclass 35, count 0 2006.224.07:53:48.83#ibcon#about to write, iclass 35, count 0 2006.224.07:53:48.83#ibcon#wrote, iclass 35, count 0 2006.224.07:53:48.83#ibcon#about to read 3, iclass 35, count 0 2006.224.07:53:48.86#ibcon#read 3, iclass 35, count 0 2006.224.07:53:48.86#ibcon#about to read 4, iclass 35, count 0 2006.224.07:53:48.86#ibcon#read 4, iclass 35, count 0 2006.224.07:53:48.86#ibcon#about to read 5, iclass 35, count 0 2006.224.07:53:48.86#ibcon#read 5, iclass 35, count 0 2006.224.07:53:48.86#ibcon#about to read 6, iclass 35, count 0 2006.224.07:53:48.86#ibcon#read 6, iclass 35, count 0 2006.224.07:53:48.86#ibcon#end of sib2, iclass 35, count 0 2006.224.07:53:48.86#ibcon#*after write, iclass 35, count 0 2006.224.07:53:48.86#ibcon#*before return 0, iclass 35, count 0 2006.224.07:53:48.86#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.224.07:53:48.86#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.224.07:53:48.86#ibcon#about to clear, iclass 35 cls_cnt 0 2006.224.07:53:48.86#ibcon#cleared, iclass 35 cls_cnt 0 2006.224.07:53:48.86$vc4f8/valo=4,832.99 2006.224.07:53:48.86#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.224.07:53:48.86#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.224.07:53:48.86#ibcon#ireg 17 cls_cnt 0 2006.224.07:53:48.86#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.224.07:53:48.86#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.224.07:53:48.86#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.224.07:53:48.86#ibcon#enter wrdev, iclass 37, count 0 2006.224.07:53:48.86#ibcon#first serial, iclass 37, count 0 2006.224.07:53:48.86#ibcon#enter sib2, iclass 37, count 0 2006.224.07:53:48.86#ibcon#flushed, iclass 37, count 0 2006.224.07:53:48.86#ibcon#about to write, iclass 37, count 0 2006.224.07:53:48.86#ibcon#wrote, iclass 37, count 0 2006.224.07:53:48.86#ibcon#about to read 3, iclass 37, count 0 2006.224.07:53:48.88#ibcon#read 3, iclass 37, count 0 2006.224.07:53:48.88#ibcon#about to read 4, iclass 37, count 0 2006.224.07:53:48.88#ibcon#read 4, iclass 37, count 0 2006.224.07:53:48.88#ibcon#about to read 5, iclass 37, count 0 2006.224.07:53:48.88#ibcon#read 5, iclass 37, count 0 2006.224.07:53:48.88#ibcon#about to read 6, iclass 37, count 0 2006.224.07:53:48.88#ibcon#read 6, iclass 37, count 0 2006.224.07:53:48.88#ibcon#end of sib2, iclass 37, count 0 2006.224.07:53:48.88#ibcon#*mode == 0, iclass 37, count 0 2006.224.07:53:48.88#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.224.07:53:48.88#ibcon#[26=FRQ=04,832.99\r\n] 2006.224.07:53:48.88#ibcon#*before write, iclass 37, count 0 2006.224.07:53:48.88#ibcon#enter sib2, iclass 37, count 0 2006.224.07:53:48.88#ibcon#flushed, iclass 37, count 0 2006.224.07:53:48.88#ibcon#about to write, iclass 37, count 0 2006.224.07:53:48.88#ibcon#wrote, iclass 37, count 0 2006.224.07:53:48.88#ibcon#about to read 3, iclass 37, count 0 2006.224.07:53:48.92#ibcon#read 3, iclass 37, count 0 2006.224.07:53:48.92#ibcon#about to read 4, iclass 37, count 0 2006.224.07:53:48.92#ibcon#read 4, iclass 37, count 0 2006.224.07:53:48.92#ibcon#about to read 5, iclass 37, count 0 2006.224.07:53:48.92#ibcon#read 5, iclass 37, count 0 2006.224.07:53:48.92#ibcon#about to read 6, iclass 37, count 0 2006.224.07:53:48.92#ibcon#read 6, iclass 37, count 0 2006.224.07:53:48.92#ibcon#end of sib2, iclass 37, count 0 2006.224.07:53:48.92#ibcon#*after write, iclass 37, count 0 2006.224.07:53:48.92#ibcon#*before return 0, iclass 37, count 0 2006.224.07:53:48.92#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.224.07:53:48.92#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.224.07:53:48.92#ibcon#about to clear, iclass 37 cls_cnt 0 2006.224.07:53:48.92#ibcon#cleared, iclass 37 cls_cnt 0 2006.224.07:53:48.92$vc4f8/va=4,7 2006.224.07:53:48.92#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.224.07:53:48.92#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.224.07:53:48.92#ibcon#ireg 11 cls_cnt 2 2006.224.07:53:48.92#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.224.07:53:48.98#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.224.07:53:48.98#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.224.07:53:48.98#ibcon#enter wrdev, iclass 39, count 2 2006.224.07:53:48.98#ibcon#first serial, iclass 39, count 2 2006.224.07:53:48.98#ibcon#enter sib2, iclass 39, count 2 2006.224.07:53:48.98#ibcon#flushed, iclass 39, count 2 2006.224.07:53:48.98#ibcon#about to write, iclass 39, count 2 2006.224.07:53:48.98#ibcon#wrote, iclass 39, count 2 2006.224.07:53:48.98#ibcon#about to read 3, iclass 39, count 2 2006.224.07:53:49.00#ibcon#read 3, iclass 39, count 2 2006.224.07:53:49.00#ibcon#about to read 4, iclass 39, count 2 2006.224.07:53:49.00#ibcon#read 4, iclass 39, count 2 2006.224.07:53:49.00#ibcon#about to read 5, iclass 39, count 2 2006.224.07:53:49.00#ibcon#read 5, iclass 39, count 2 2006.224.07:53:49.00#ibcon#about to read 6, iclass 39, count 2 2006.224.07:53:49.00#ibcon#read 6, iclass 39, count 2 2006.224.07:53:49.00#ibcon#end of sib2, iclass 39, count 2 2006.224.07:53:49.00#ibcon#*mode == 0, iclass 39, count 2 2006.224.07:53:49.00#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.224.07:53:49.00#ibcon#[25=AT04-07\r\n] 2006.224.07:53:49.00#ibcon#*before write, iclass 39, count 2 2006.224.07:53:49.00#ibcon#enter sib2, iclass 39, count 2 2006.224.07:53:49.00#ibcon#flushed, iclass 39, count 2 2006.224.07:53:49.00#ibcon#about to write, iclass 39, count 2 2006.224.07:53:49.00#ibcon#wrote, iclass 39, count 2 2006.224.07:53:49.00#ibcon#about to read 3, iclass 39, count 2 2006.224.07:53:49.03#ibcon#read 3, iclass 39, count 2 2006.224.07:53:49.03#ibcon#about to read 4, iclass 39, count 2 2006.224.07:53:49.03#ibcon#read 4, iclass 39, count 2 2006.224.07:53:49.03#ibcon#about to read 5, iclass 39, count 2 2006.224.07:53:49.03#ibcon#read 5, iclass 39, count 2 2006.224.07:53:49.03#ibcon#about to read 6, iclass 39, count 2 2006.224.07:53:49.03#ibcon#read 6, iclass 39, count 2 2006.224.07:53:49.03#ibcon#end of sib2, iclass 39, count 2 2006.224.07:53:49.03#ibcon#*after write, iclass 39, count 2 2006.224.07:53:49.03#ibcon#*before return 0, iclass 39, count 2 2006.224.07:53:49.03#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.224.07:53:49.03#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.224.07:53:49.03#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.224.07:53:49.03#ibcon#ireg 7 cls_cnt 0 2006.224.07:53:49.03#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.224.07:53:49.15#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.224.07:53:49.15#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.224.07:53:49.15#ibcon#enter wrdev, iclass 39, count 0 2006.224.07:53:49.15#ibcon#first serial, iclass 39, count 0 2006.224.07:53:49.15#ibcon#enter sib2, iclass 39, count 0 2006.224.07:53:49.15#ibcon#flushed, iclass 39, count 0 2006.224.07:53:49.15#ibcon#about to write, iclass 39, count 0 2006.224.07:53:49.15#ibcon#wrote, iclass 39, count 0 2006.224.07:53:49.15#ibcon#about to read 3, iclass 39, count 0 2006.224.07:53:49.17#ibcon#read 3, iclass 39, count 0 2006.224.07:53:49.17#ibcon#about to read 4, iclass 39, count 0 2006.224.07:53:49.17#ibcon#read 4, iclass 39, count 0 2006.224.07:53:49.17#ibcon#about to read 5, iclass 39, count 0 2006.224.07:53:49.17#ibcon#read 5, iclass 39, count 0 2006.224.07:53:49.17#ibcon#about to read 6, iclass 39, count 0 2006.224.07:53:49.17#ibcon#read 6, iclass 39, count 0 2006.224.07:53:49.17#ibcon#end of sib2, iclass 39, count 0 2006.224.07:53:49.17#ibcon#*mode == 0, iclass 39, count 0 2006.224.07:53:49.17#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.224.07:53:49.17#ibcon#[25=USB\r\n] 2006.224.07:53:49.17#ibcon#*before write, iclass 39, count 0 2006.224.07:53:49.17#ibcon#enter sib2, iclass 39, count 0 2006.224.07:53:49.17#ibcon#flushed, iclass 39, count 0 2006.224.07:53:49.17#ibcon#about to write, iclass 39, count 0 2006.224.07:53:49.17#ibcon#wrote, iclass 39, count 0 2006.224.07:53:49.17#ibcon#about to read 3, iclass 39, count 0 2006.224.07:53:49.20#ibcon#read 3, iclass 39, count 0 2006.224.07:53:49.20#ibcon#about to read 4, iclass 39, count 0 2006.224.07:53:49.20#ibcon#read 4, iclass 39, count 0 2006.224.07:53:49.20#ibcon#about to read 5, iclass 39, count 0 2006.224.07:53:49.20#ibcon#read 5, iclass 39, count 0 2006.224.07:53:49.20#ibcon#about to read 6, iclass 39, count 0 2006.224.07:53:49.20#ibcon#read 6, iclass 39, count 0 2006.224.07:53:49.20#ibcon#end of sib2, iclass 39, count 0 2006.224.07:53:49.20#ibcon#*after write, iclass 39, count 0 2006.224.07:53:49.20#ibcon#*before return 0, iclass 39, count 0 2006.224.07:53:49.20#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.224.07:53:49.20#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.224.07:53:49.20#ibcon#about to clear, iclass 39 cls_cnt 0 2006.224.07:53:49.20#ibcon#cleared, iclass 39 cls_cnt 0 2006.224.07:53:49.20$vc4f8/valo=5,652.99 2006.224.07:53:49.20#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.224.07:53:49.20#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.224.07:53:49.20#ibcon#ireg 17 cls_cnt 0 2006.224.07:53:49.20#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.224.07:53:49.20#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.224.07:53:49.20#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.224.07:53:49.20#ibcon#enter wrdev, iclass 3, count 0 2006.224.07:53:49.20#ibcon#first serial, iclass 3, count 0 2006.224.07:53:49.20#ibcon#enter sib2, iclass 3, count 0 2006.224.07:53:49.20#ibcon#flushed, iclass 3, count 0 2006.224.07:53:49.20#ibcon#about to write, iclass 3, count 0 2006.224.07:53:49.20#ibcon#wrote, iclass 3, count 0 2006.224.07:53:49.20#ibcon#about to read 3, iclass 3, count 0 2006.224.07:53:49.22#ibcon#read 3, iclass 3, count 0 2006.224.07:53:49.22#ibcon#about to read 4, iclass 3, count 0 2006.224.07:53:49.22#ibcon#read 4, iclass 3, count 0 2006.224.07:53:49.22#ibcon#about to read 5, iclass 3, count 0 2006.224.07:53:49.22#ibcon#read 5, iclass 3, count 0 2006.224.07:53:49.22#ibcon#about to read 6, iclass 3, count 0 2006.224.07:53:49.22#ibcon#read 6, iclass 3, count 0 2006.224.07:53:49.22#ibcon#end of sib2, iclass 3, count 0 2006.224.07:53:49.22#ibcon#*mode == 0, iclass 3, count 0 2006.224.07:53:49.22#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.224.07:53:49.22#ibcon#[26=FRQ=05,652.99\r\n] 2006.224.07:53:49.22#ibcon#*before write, iclass 3, count 0 2006.224.07:53:49.22#ibcon#enter sib2, iclass 3, count 0 2006.224.07:53:49.22#ibcon#flushed, iclass 3, count 0 2006.224.07:53:49.22#ibcon#about to write, iclass 3, count 0 2006.224.07:53:49.22#ibcon#wrote, iclass 3, count 0 2006.224.07:53:49.22#ibcon#about to read 3, iclass 3, count 0 2006.224.07:53:49.26#ibcon#read 3, iclass 3, count 0 2006.224.07:53:49.26#ibcon#about to read 4, iclass 3, count 0 2006.224.07:53:49.26#ibcon#read 4, iclass 3, count 0 2006.224.07:53:49.26#ibcon#about to read 5, iclass 3, count 0 2006.224.07:53:49.26#ibcon#read 5, iclass 3, count 0 2006.224.07:53:49.26#ibcon#about to read 6, iclass 3, count 0 2006.224.07:53:49.26#ibcon#read 6, iclass 3, count 0 2006.224.07:53:49.26#ibcon#end of sib2, iclass 3, count 0 2006.224.07:53:49.26#ibcon#*after write, iclass 3, count 0 2006.224.07:53:49.26#ibcon#*before return 0, iclass 3, count 0 2006.224.07:53:49.26#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.224.07:53:49.26#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.224.07:53:49.26#ibcon#about to clear, iclass 3 cls_cnt 0 2006.224.07:53:49.26#ibcon#cleared, iclass 3 cls_cnt 0 2006.224.07:53:49.26$vc4f8/va=5,7 2006.224.07:53:49.26#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.224.07:53:49.26#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.224.07:53:49.26#ibcon#ireg 11 cls_cnt 2 2006.224.07:53:49.26#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.224.07:53:49.32#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.224.07:53:49.32#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.224.07:53:49.32#ibcon#enter wrdev, iclass 5, count 2 2006.224.07:53:49.32#ibcon#first serial, iclass 5, count 2 2006.224.07:53:49.32#ibcon#enter sib2, iclass 5, count 2 2006.224.07:53:49.32#ibcon#flushed, iclass 5, count 2 2006.224.07:53:49.32#ibcon#about to write, iclass 5, count 2 2006.224.07:53:49.32#ibcon#wrote, iclass 5, count 2 2006.224.07:53:49.32#ibcon#about to read 3, iclass 5, count 2 2006.224.07:53:49.34#ibcon#read 3, iclass 5, count 2 2006.224.07:53:49.34#ibcon#about to read 4, iclass 5, count 2 2006.224.07:53:49.34#ibcon#read 4, iclass 5, count 2 2006.224.07:53:49.34#ibcon#about to read 5, iclass 5, count 2 2006.224.07:53:49.34#ibcon#read 5, iclass 5, count 2 2006.224.07:53:49.34#ibcon#about to read 6, iclass 5, count 2 2006.224.07:53:49.34#ibcon#read 6, iclass 5, count 2 2006.224.07:53:49.34#ibcon#end of sib2, iclass 5, count 2 2006.224.07:53:49.34#ibcon#*mode == 0, iclass 5, count 2 2006.224.07:53:49.34#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.224.07:53:49.34#ibcon#[25=AT05-07\r\n] 2006.224.07:53:49.34#ibcon#*before write, iclass 5, count 2 2006.224.07:53:49.34#ibcon#enter sib2, iclass 5, count 2 2006.224.07:53:49.34#ibcon#flushed, iclass 5, count 2 2006.224.07:53:49.34#ibcon#about to write, iclass 5, count 2 2006.224.07:53:49.34#ibcon#wrote, iclass 5, count 2 2006.224.07:53:49.34#ibcon#about to read 3, iclass 5, count 2 2006.224.07:53:49.37#ibcon#read 3, iclass 5, count 2 2006.224.07:53:49.37#ibcon#about to read 4, iclass 5, count 2 2006.224.07:53:49.37#ibcon#read 4, iclass 5, count 2 2006.224.07:53:49.37#ibcon#about to read 5, iclass 5, count 2 2006.224.07:53:49.37#ibcon#read 5, iclass 5, count 2 2006.224.07:53:49.37#ibcon#about to read 6, iclass 5, count 2 2006.224.07:53:49.37#ibcon#read 6, iclass 5, count 2 2006.224.07:53:49.37#ibcon#end of sib2, iclass 5, count 2 2006.224.07:53:49.37#ibcon#*after write, iclass 5, count 2 2006.224.07:53:49.37#ibcon#*before return 0, iclass 5, count 2 2006.224.07:53:49.37#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.224.07:53:49.37#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.224.07:53:49.37#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.224.07:53:49.37#ibcon#ireg 7 cls_cnt 0 2006.224.07:53:49.37#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.224.07:53:49.49#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.224.07:53:49.49#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.224.07:53:49.49#ibcon#enter wrdev, iclass 5, count 0 2006.224.07:53:49.49#ibcon#first serial, iclass 5, count 0 2006.224.07:53:49.49#ibcon#enter sib2, iclass 5, count 0 2006.224.07:53:49.49#ibcon#flushed, iclass 5, count 0 2006.224.07:53:49.49#ibcon#about to write, iclass 5, count 0 2006.224.07:53:49.49#ibcon#wrote, iclass 5, count 0 2006.224.07:53:49.49#ibcon#about to read 3, iclass 5, count 0 2006.224.07:53:49.51#ibcon#read 3, iclass 5, count 0 2006.224.07:53:49.51#ibcon#about to read 4, iclass 5, count 0 2006.224.07:53:49.51#ibcon#read 4, iclass 5, count 0 2006.224.07:53:49.51#ibcon#about to read 5, iclass 5, count 0 2006.224.07:53:49.51#ibcon#read 5, iclass 5, count 0 2006.224.07:53:49.51#ibcon#about to read 6, iclass 5, count 0 2006.224.07:53:49.51#ibcon#read 6, iclass 5, count 0 2006.224.07:53:49.51#ibcon#end of sib2, iclass 5, count 0 2006.224.07:53:49.51#ibcon#*mode == 0, iclass 5, count 0 2006.224.07:53:49.51#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.224.07:53:49.51#ibcon#[25=USB\r\n] 2006.224.07:53:49.51#ibcon#*before write, iclass 5, count 0 2006.224.07:53:49.51#ibcon#enter sib2, iclass 5, count 0 2006.224.07:53:49.51#ibcon#flushed, iclass 5, count 0 2006.224.07:53:49.51#ibcon#about to write, iclass 5, count 0 2006.224.07:53:49.51#ibcon#wrote, iclass 5, count 0 2006.224.07:53:49.51#ibcon#about to read 3, iclass 5, count 0 2006.224.07:53:49.54#ibcon#read 3, iclass 5, count 0 2006.224.07:53:49.54#ibcon#about to read 4, iclass 5, count 0 2006.224.07:53:49.54#ibcon#read 4, iclass 5, count 0 2006.224.07:53:49.54#ibcon#about to read 5, iclass 5, count 0 2006.224.07:53:49.54#ibcon#read 5, iclass 5, count 0 2006.224.07:53:49.54#ibcon#about to read 6, iclass 5, count 0 2006.224.07:53:49.54#ibcon#read 6, iclass 5, count 0 2006.224.07:53:49.54#ibcon#end of sib2, iclass 5, count 0 2006.224.07:53:49.54#ibcon#*after write, iclass 5, count 0 2006.224.07:53:49.54#ibcon#*before return 0, iclass 5, count 0 2006.224.07:53:49.54#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.224.07:53:49.54#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.224.07:53:49.54#ibcon#about to clear, iclass 5 cls_cnt 0 2006.224.07:53:49.54#ibcon#cleared, iclass 5 cls_cnt 0 2006.224.07:53:49.54$vc4f8/valo=6,772.99 2006.224.07:53:49.54#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.224.07:53:49.54#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.224.07:53:49.54#ibcon#ireg 17 cls_cnt 0 2006.224.07:53:49.54#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.224.07:53:49.54#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.224.07:53:49.54#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.224.07:53:49.54#ibcon#enter wrdev, iclass 7, count 0 2006.224.07:53:49.54#ibcon#first serial, iclass 7, count 0 2006.224.07:53:49.54#ibcon#enter sib2, iclass 7, count 0 2006.224.07:53:49.54#ibcon#flushed, iclass 7, count 0 2006.224.07:53:49.54#ibcon#about to write, iclass 7, count 0 2006.224.07:53:49.54#ibcon#wrote, iclass 7, count 0 2006.224.07:53:49.54#ibcon#about to read 3, iclass 7, count 0 2006.224.07:53:49.57#ibcon#read 3, iclass 7, count 0 2006.224.07:53:49.57#ibcon#about to read 4, iclass 7, count 0 2006.224.07:53:49.57#ibcon#read 4, iclass 7, count 0 2006.224.07:53:49.57#ibcon#about to read 5, iclass 7, count 0 2006.224.07:53:49.57#ibcon#read 5, iclass 7, count 0 2006.224.07:53:49.57#ibcon#about to read 6, iclass 7, count 0 2006.224.07:53:49.57#ibcon#read 6, iclass 7, count 0 2006.224.07:53:49.57#ibcon#end of sib2, iclass 7, count 0 2006.224.07:53:49.57#ibcon#*mode == 0, iclass 7, count 0 2006.224.07:53:49.57#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.224.07:53:49.57#ibcon#[26=FRQ=06,772.99\r\n] 2006.224.07:53:49.57#ibcon#*before write, iclass 7, count 0 2006.224.07:53:49.57#ibcon#enter sib2, iclass 7, count 0 2006.224.07:53:49.57#ibcon#flushed, iclass 7, count 0 2006.224.07:53:49.57#ibcon#about to write, iclass 7, count 0 2006.224.07:53:49.57#ibcon#wrote, iclass 7, count 0 2006.224.07:53:49.57#ibcon#about to read 3, iclass 7, count 0 2006.224.07:53:49.61#ibcon#read 3, iclass 7, count 0 2006.224.07:53:49.61#ibcon#about to read 4, iclass 7, count 0 2006.224.07:53:49.61#ibcon#read 4, iclass 7, count 0 2006.224.07:53:49.61#ibcon#about to read 5, iclass 7, count 0 2006.224.07:53:49.61#ibcon#read 5, iclass 7, count 0 2006.224.07:53:49.61#ibcon#about to read 6, iclass 7, count 0 2006.224.07:53:49.61#ibcon#read 6, iclass 7, count 0 2006.224.07:53:49.61#ibcon#end of sib2, iclass 7, count 0 2006.224.07:53:49.61#ibcon#*after write, iclass 7, count 0 2006.224.07:53:49.61#ibcon#*before return 0, iclass 7, count 0 2006.224.07:53:49.61#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.224.07:53:49.61#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.224.07:53:49.61#ibcon#about to clear, iclass 7 cls_cnt 0 2006.224.07:53:49.61#ibcon#cleared, iclass 7 cls_cnt 0 2006.224.07:53:49.61$vc4f8/va=6,6 2006.224.07:53:49.61#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.224.07:53:49.61#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.224.07:53:49.61#ibcon#ireg 11 cls_cnt 2 2006.224.07:53:49.61#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.224.07:53:49.66#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.224.07:53:49.66#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.224.07:53:49.66#ibcon#enter wrdev, iclass 11, count 2 2006.224.07:53:49.66#ibcon#first serial, iclass 11, count 2 2006.224.07:53:49.66#ibcon#enter sib2, iclass 11, count 2 2006.224.07:53:49.66#ibcon#flushed, iclass 11, count 2 2006.224.07:53:49.66#ibcon#about to write, iclass 11, count 2 2006.224.07:53:49.66#ibcon#wrote, iclass 11, count 2 2006.224.07:53:49.66#ibcon#about to read 3, iclass 11, count 2 2006.224.07:53:49.68#ibcon#read 3, iclass 11, count 2 2006.224.07:53:49.68#ibcon#about to read 4, iclass 11, count 2 2006.224.07:53:49.68#ibcon#read 4, iclass 11, count 2 2006.224.07:53:49.68#ibcon#about to read 5, iclass 11, count 2 2006.224.07:53:49.68#ibcon#read 5, iclass 11, count 2 2006.224.07:53:49.68#ibcon#about to read 6, iclass 11, count 2 2006.224.07:53:49.68#ibcon#read 6, iclass 11, count 2 2006.224.07:53:49.68#ibcon#end of sib2, iclass 11, count 2 2006.224.07:53:49.68#ibcon#*mode == 0, iclass 11, count 2 2006.224.07:53:49.68#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.224.07:53:49.68#ibcon#[25=AT06-06\r\n] 2006.224.07:53:49.68#ibcon#*before write, iclass 11, count 2 2006.224.07:53:49.68#ibcon#enter sib2, iclass 11, count 2 2006.224.07:53:49.68#ibcon#flushed, iclass 11, count 2 2006.224.07:53:49.68#ibcon#about to write, iclass 11, count 2 2006.224.07:53:49.68#ibcon#wrote, iclass 11, count 2 2006.224.07:53:49.68#ibcon#about to read 3, iclass 11, count 2 2006.224.07:53:49.71#ibcon#read 3, iclass 11, count 2 2006.224.07:53:49.71#ibcon#about to read 4, iclass 11, count 2 2006.224.07:53:49.71#ibcon#read 4, iclass 11, count 2 2006.224.07:53:49.71#ibcon#about to read 5, iclass 11, count 2 2006.224.07:53:49.71#ibcon#read 5, iclass 11, count 2 2006.224.07:53:49.71#ibcon#about to read 6, iclass 11, count 2 2006.224.07:53:49.71#ibcon#read 6, iclass 11, count 2 2006.224.07:53:49.71#ibcon#end of sib2, iclass 11, count 2 2006.224.07:53:49.71#ibcon#*after write, iclass 11, count 2 2006.224.07:53:49.71#ibcon#*before return 0, iclass 11, count 2 2006.224.07:53:49.71#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.224.07:53:49.71#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.224.07:53:49.71#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.224.07:53:49.71#ibcon#ireg 7 cls_cnt 0 2006.224.07:53:49.71#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.224.07:53:49.83#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.224.07:53:49.83#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.224.07:53:49.83#ibcon#enter wrdev, iclass 11, count 0 2006.224.07:53:49.83#ibcon#first serial, iclass 11, count 0 2006.224.07:53:49.83#ibcon#enter sib2, iclass 11, count 0 2006.224.07:53:49.83#ibcon#flushed, iclass 11, count 0 2006.224.07:53:49.83#ibcon#about to write, iclass 11, count 0 2006.224.07:53:49.83#ibcon#wrote, iclass 11, count 0 2006.224.07:53:49.83#ibcon#about to read 3, iclass 11, count 0 2006.224.07:53:49.85#ibcon#read 3, iclass 11, count 0 2006.224.07:53:49.85#ibcon#about to read 4, iclass 11, count 0 2006.224.07:53:49.85#ibcon#read 4, iclass 11, count 0 2006.224.07:53:49.85#ibcon#about to read 5, iclass 11, count 0 2006.224.07:53:49.85#ibcon#read 5, iclass 11, count 0 2006.224.07:53:49.85#ibcon#about to read 6, iclass 11, count 0 2006.224.07:53:49.85#ibcon#read 6, iclass 11, count 0 2006.224.07:53:49.85#ibcon#end of sib2, iclass 11, count 0 2006.224.07:53:49.85#ibcon#*mode == 0, iclass 11, count 0 2006.224.07:53:49.85#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.224.07:53:49.85#ibcon#[25=USB\r\n] 2006.224.07:53:49.85#ibcon#*before write, iclass 11, count 0 2006.224.07:53:49.85#ibcon#enter sib2, iclass 11, count 0 2006.224.07:53:49.85#ibcon#flushed, iclass 11, count 0 2006.224.07:53:49.85#ibcon#about to write, iclass 11, count 0 2006.224.07:53:49.85#ibcon#wrote, iclass 11, count 0 2006.224.07:53:49.85#ibcon#about to read 3, iclass 11, count 0 2006.224.07:53:49.88#ibcon#read 3, iclass 11, count 0 2006.224.07:53:49.88#ibcon#about to read 4, iclass 11, count 0 2006.224.07:53:49.88#ibcon#read 4, iclass 11, count 0 2006.224.07:53:49.88#ibcon#about to read 5, iclass 11, count 0 2006.224.07:53:49.88#ibcon#read 5, iclass 11, count 0 2006.224.07:53:49.88#ibcon#about to read 6, iclass 11, count 0 2006.224.07:53:49.88#ibcon#read 6, iclass 11, count 0 2006.224.07:53:49.88#ibcon#end of sib2, iclass 11, count 0 2006.224.07:53:49.88#ibcon#*after write, iclass 11, count 0 2006.224.07:53:49.88#ibcon#*before return 0, iclass 11, count 0 2006.224.07:53:49.88#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.224.07:53:49.88#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.224.07:53:49.88#ibcon#about to clear, iclass 11 cls_cnt 0 2006.224.07:53:49.88#ibcon#cleared, iclass 11 cls_cnt 0 2006.224.07:53:49.88$vc4f8/valo=7,832.99 2006.224.07:53:49.88#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.224.07:53:49.88#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.224.07:53:49.88#ibcon#ireg 17 cls_cnt 0 2006.224.07:53:49.88#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.224.07:53:49.88#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.224.07:53:49.88#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.224.07:53:49.88#ibcon#enter wrdev, iclass 13, count 0 2006.224.07:53:49.88#ibcon#first serial, iclass 13, count 0 2006.224.07:53:49.88#ibcon#enter sib2, iclass 13, count 0 2006.224.07:53:49.88#ibcon#flushed, iclass 13, count 0 2006.224.07:53:49.88#ibcon#about to write, iclass 13, count 0 2006.224.07:53:49.88#ibcon#wrote, iclass 13, count 0 2006.224.07:53:49.88#ibcon#about to read 3, iclass 13, count 0 2006.224.07:53:49.90#ibcon#read 3, iclass 13, count 0 2006.224.07:53:49.90#ibcon#about to read 4, iclass 13, count 0 2006.224.07:53:49.90#ibcon#read 4, iclass 13, count 0 2006.224.07:53:49.90#ibcon#about to read 5, iclass 13, count 0 2006.224.07:53:49.90#ibcon#read 5, iclass 13, count 0 2006.224.07:53:49.90#ibcon#about to read 6, iclass 13, count 0 2006.224.07:53:49.90#ibcon#read 6, iclass 13, count 0 2006.224.07:53:49.90#ibcon#end of sib2, iclass 13, count 0 2006.224.07:53:49.90#ibcon#*mode == 0, iclass 13, count 0 2006.224.07:53:49.90#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.224.07:53:49.90#ibcon#[26=FRQ=07,832.99\r\n] 2006.224.07:53:49.90#ibcon#*before write, iclass 13, count 0 2006.224.07:53:49.90#ibcon#enter sib2, iclass 13, count 0 2006.224.07:53:49.90#ibcon#flushed, iclass 13, count 0 2006.224.07:53:49.90#ibcon#about to write, iclass 13, count 0 2006.224.07:53:49.90#ibcon#wrote, iclass 13, count 0 2006.224.07:53:49.90#ibcon#about to read 3, iclass 13, count 0 2006.224.07:53:49.94#ibcon#read 3, iclass 13, count 0 2006.224.07:53:49.94#ibcon#about to read 4, iclass 13, count 0 2006.224.07:53:49.94#ibcon#read 4, iclass 13, count 0 2006.224.07:53:49.94#ibcon#about to read 5, iclass 13, count 0 2006.224.07:53:49.94#ibcon#read 5, iclass 13, count 0 2006.224.07:53:49.94#ibcon#about to read 6, iclass 13, count 0 2006.224.07:53:49.94#ibcon#read 6, iclass 13, count 0 2006.224.07:53:49.94#ibcon#end of sib2, iclass 13, count 0 2006.224.07:53:49.94#ibcon#*after write, iclass 13, count 0 2006.224.07:53:49.94#ibcon#*before return 0, iclass 13, count 0 2006.224.07:53:49.94#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.224.07:53:49.94#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.224.07:53:49.94#ibcon#about to clear, iclass 13 cls_cnt 0 2006.224.07:53:49.94#ibcon#cleared, iclass 13 cls_cnt 0 2006.224.07:53:49.94$vc4f8/va=7,6 2006.224.07:53:49.94#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.224.07:53:49.94#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.224.07:53:49.94#ibcon#ireg 11 cls_cnt 2 2006.224.07:53:49.94#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.224.07:53:50.00#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.224.07:53:50.00#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.224.07:53:50.00#ibcon#enter wrdev, iclass 15, count 2 2006.224.07:53:50.00#ibcon#first serial, iclass 15, count 2 2006.224.07:53:50.00#ibcon#enter sib2, iclass 15, count 2 2006.224.07:53:50.00#ibcon#flushed, iclass 15, count 2 2006.224.07:53:50.00#ibcon#about to write, iclass 15, count 2 2006.224.07:53:50.00#ibcon#wrote, iclass 15, count 2 2006.224.07:53:50.00#ibcon#about to read 3, iclass 15, count 2 2006.224.07:53:50.02#ibcon#read 3, iclass 15, count 2 2006.224.07:53:50.02#ibcon#about to read 4, iclass 15, count 2 2006.224.07:53:50.02#ibcon#read 4, iclass 15, count 2 2006.224.07:53:50.02#ibcon#about to read 5, iclass 15, count 2 2006.224.07:53:50.02#ibcon#read 5, iclass 15, count 2 2006.224.07:53:50.02#ibcon#about to read 6, iclass 15, count 2 2006.224.07:53:50.02#ibcon#read 6, iclass 15, count 2 2006.224.07:53:50.02#ibcon#end of sib2, iclass 15, count 2 2006.224.07:53:50.02#ibcon#*mode == 0, iclass 15, count 2 2006.224.07:53:50.02#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.224.07:53:50.02#ibcon#[25=AT07-06\r\n] 2006.224.07:53:50.02#ibcon#*before write, iclass 15, count 2 2006.224.07:53:50.02#ibcon#enter sib2, iclass 15, count 2 2006.224.07:53:50.02#ibcon#flushed, iclass 15, count 2 2006.224.07:53:50.02#ibcon#about to write, iclass 15, count 2 2006.224.07:53:50.02#ibcon#wrote, iclass 15, count 2 2006.224.07:53:50.02#ibcon#about to read 3, iclass 15, count 2 2006.224.07:53:50.05#ibcon#read 3, iclass 15, count 2 2006.224.07:53:50.05#ibcon#about to read 4, iclass 15, count 2 2006.224.07:53:50.05#ibcon#read 4, iclass 15, count 2 2006.224.07:53:50.05#ibcon#about to read 5, iclass 15, count 2 2006.224.07:53:50.05#ibcon#read 5, iclass 15, count 2 2006.224.07:53:50.05#ibcon#about to read 6, iclass 15, count 2 2006.224.07:53:50.05#ibcon#read 6, iclass 15, count 2 2006.224.07:53:50.05#ibcon#end of sib2, iclass 15, count 2 2006.224.07:53:50.05#ibcon#*after write, iclass 15, count 2 2006.224.07:53:50.05#ibcon#*before return 0, iclass 15, count 2 2006.224.07:53:50.05#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.224.07:53:50.05#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.224.07:53:50.05#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.224.07:53:50.05#ibcon#ireg 7 cls_cnt 0 2006.224.07:53:50.05#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.224.07:53:50.17#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.224.07:53:50.17#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.224.07:53:50.17#ibcon#enter wrdev, iclass 15, count 0 2006.224.07:53:50.17#ibcon#first serial, iclass 15, count 0 2006.224.07:53:50.17#ibcon#enter sib2, iclass 15, count 0 2006.224.07:53:50.17#ibcon#flushed, iclass 15, count 0 2006.224.07:53:50.17#ibcon#about to write, iclass 15, count 0 2006.224.07:53:50.17#ibcon#wrote, iclass 15, count 0 2006.224.07:53:50.17#ibcon#about to read 3, iclass 15, count 0 2006.224.07:53:50.19#ibcon#read 3, iclass 15, count 0 2006.224.07:53:50.19#ibcon#about to read 4, iclass 15, count 0 2006.224.07:53:50.19#ibcon#read 4, iclass 15, count 0 2006.224.07:53:50.19#ibcon#about to read 5, iclass 15, count 0 2006.224.07:53:50.19#ibcon#read 5, iclass 15, count 0 2006.224.07:53:50.19#ibcon#about to read 6, iclass 15, count 0 2006.224.07:53:50.19#ibcon#read 6, iclass 15, count 0 2006.224.07:53:50.19#ibcon#end of sib2, iclass 15, count 0 2006.224.07:53:50.19#ibcon#*mode == 0, iclass 15, count 0 2006.224.07:53:50.19#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.224.07:53:50.19#ibcon#[25=USB\r\n] 2006.224.07:53:50.19#ibcon#*before write, iclass 15, count 0 2006.224.07:53:50.19#ibcon#enter sib2, iclass 15, count 0 2006.224.07:53:50.19#ibcon#flushed, iclass 15, count 0 2006.224.07:53:50.19#ibcon#about to write, iclass 15, count 0 2006.224.07:53:50.19#ibcon#wrote, iclass 15, count 0 2006.224.07:53:50.19#ibcon#about to read 3, iclass 15, count 0 2006.224.07:53:50.22#ibcon#read 3, iclass 15, count 0 2006.224.07:53:50.22#ibcon#about to read 4, iclass 15, count 0 2006.224.07:53:50.22#ibcon#read 4, iclass 15, count 0 2006.224.07:53:50.22#ibcon#about to read 5, iclass 15, count 0 2006.224.07:53:50.22#ibcon#read 5, iclass 15, count 0 2006.224.07:53:50.22#ibcon#about to read 6, iclass 15, count 0 2006.224.07:53:50.22#ibcon#read 6, iclass 15, count 0 2006.224.07:53:50.22#ibcon#end of sib2, iclass 15, count 0 2006.224.07:53:50.22#ibcon#*after write, iclass 15, count 0 2006.224.07:53:50.22#ibcon#*before return 0, iclass 15, count 0 2006.224.07:53:50.22#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.224.07:53:50.22#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.224.07:53:50.22#ibcon#about to clear, iclass 15 cls_cnt 0 2006.224.07:53:50.22#ibcon#cleared, iclass 15 cls_cnt 0 2006.224.07:53:50.22$vc4f8/valo=8,852.99 2006.224.07:53:50.22#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.224.07:53:50.22#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.224.07:53:50.22#ibcon#ireg 17 cls_cnt 0 2006.224.07:53:50.22#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.224.07:53:50.22#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.224.07:53:50.22#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.224.07:53:50.22#ibcon#enter wrdev, iclass 17, count 0 2006.224.07:53:50.22#ibcon#first serial, iclass 17, count 0 2006.224.07:53:50.22#ibcon#enter sib2, iclass 17, count 0 2006.224.07:53:50.22#ibcon#flushed, iclass 17, count 0 2006.224.07:53:50.22#ibcon#about to write, iclass 17, count 0 2006.224.07:53:50.22#ibcon#wrote, iclass 17, count 0 2006.224.07:53:50.22#ibcon#about to read 3, iclass 17, count 0 2006.224.07:53:50.24#ibcon#read 3, iclass 17, count 0 2006.224.07:53:50.24#ibcon#about to read 4, iclass 17, count 0 2006.224.07:53:50.24#ibcon#read 4, iclass 17, count 0 2006.224.07:53:50.24#ibcon#about to read 5, iclass 17, count 0 2006.224.07:53:50.24#ibcon#read 5, iclass 17, count 0 2006.224.07:53:50.24#ibcon#about to read 6, iclass 17, count 0 2006.224.07:53:50.24#ibcon#read 6, iclass 17, count 0 2006.224.07:53:50.24#ibcon#end of sib2, iclass 17, count 0 2006.224.07:53:50.24#ibcon#*mode == 0, iclass 17, count 0 2006.224.07:53:50.24#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.224.07:53:50.24#ibcon#[26=FRQ=08,852.99\r\n] 2006.224.07:53:50.24#ibcon#*before write, iclass 17, count 0 2006.224.07:53:50.24#ibcon#enter sib2, iclass 17, count 0 2006.224.07:53:50.24#ibcon#flushed, iclass 17, count 0 2006.224.07:53:50.24#ibcon#about to write, iclass 17, count 0 2006.224.07:53:50.24#ibcon#wrote, iclass 17, count 0 2006.224.07:53:50.24#ibcon#about to read 3, iclass 17, count 0 2006.224.07:53:50.28#ibcon#read 3, iclass 17, count 0 2006.224.07:53:50.28#ibcon#about to read 4, iclass 17, count 0 2006.224.07:53:50.28#ibcon#read 4, iclass 17, count 0 2006.224.07:53:50.28#ibcon#about to read 5, iclass 17, count 0 2006.224.07:53:50.28#ibcon#read 5, iclass 17, count 0 2006.224.07:53:50.28#ibcon#about to read 6, iclass 17, count 0 2006.224.07:53:50.28#ibcon#read 6, iclass 17, count 0 2006.224.07:53:50.28#ibcon#end of sib2, iclass 17, count 0 2006.224.07:53:50.28#ibcon#*after write, iclass 17, count 0 2006.224.07:53:50.28#ibcon#*before return 0, iclass 17, count 0 2006.224.07:53:50.28#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.224.07:53:50.28#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.224.07:53:50.28#ibcon#about to clear, iclass 17 cls_cnt 0 2006.224.07:53:50.28#ibcon#cleared, iclass 17 cls_cnt 0 2006.224.07:53:50.28$vc4f8/va=8,7 2006.224.07:53:50.28#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.224.07:53:50.28#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.224.07:53:50.28#ibcon#ireg 11 cls_cnt 2 2006.224.07:53:50.28#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.224.07:53:50.34#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.224.07:53:50.34#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.224.07:53:50.34#ibcon#enter wrdev, iclass 19, count 2 2006.224.07:53:50.34#ibcon#first serial, iclass 19, count 2 2006.224.07:53:50.34#ibcon#enter sib2, iclass 19, count 2 2006.224.07:53:50.34#ibcon#flushed, iclass 19, count 2 2006.224.07:53:50.34#ibcon#about to write, iclass 19, count 2 2006.224.07:53:50.34#ibcon#wrote, iclass 19, count 2 2006.224.07:53:50.34#ibcon#about to read 3, iclass 19, count 2 2006.224.07:53:50.36#ibcon#read 3, iclass 19, count 2 2006.224.07:53:50.36#ibcon#about to read 4, iclass 19, count 2 2006.224.07:53:50.36#ibcon#read 4, iclass 19, count 2 2006.224.07:53:50.36#ibcon#about to read 5, iclass 19, count 2 2006.224.07:53:50.36#ibcon#read 5, iclass 19, count 2 2006.224.07:53:50.36#ibcon#about to read 6, iclass 19, count 2 2006.224.07:53:50.36#ibcon#read 6, iclass 19, count 2 2006.224.07:53:50.36#ibcon#end of sib2, iclass 19, count 2 2006.224.07:53:50.36#ibcon#*mode == 0, iclass 19, count 2 2006.224.07:53:50.36#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.224.07:53:50.36#ibcon#[25=AT08-07\r\n] 2006.224.07:53:50.36#ibcon#*before write, iclass 19, count 2 2006.224.07:53:50.36#ibcon#enter sib2, iclass 19, count 2 2006.224.07:53:50.36#ibcon#flushed, iclass 19, count 2 2006.224.07:53:50.36#ibcon#about to write, iclass 19, count 2 2006.224.07:53:50.36#ibcon#wrote, iclass 19, count 2 2006.224.07:53:50.36#ibcon#about to read 3, iclass 19, count 2 2006.224.07:53:50.39#ibcon#read 3, iclass 19, count 2 2006.224.07:53:50.39#ibcon#about to read 4, iclass 19, count 2 2006.224.07:53:50.39#ibcon#read 4, iclass 19, count 2 2006.224.07:53:50.39#ibcon#about to read 5, iclass 19, count 2 2006.224.07:53:50.39#ibcon#read 5, iclass 19, count 2 2006.224.07:53:50.39#ibcon#about to read 6, iclass 19, count 2 2006.224.07:53:50.39#ibcon#read 6, iclass 19, count 2 2006.224.07:53:50.39#ibcon#end of sib2, iclass 19, count 2 2006.224.07:53:50.39#ibcon#*after write, iclass 19, count 2 2006.224.07:53:50.39#ibcon#*before return 0, iclass 19, count 2 2006.224.07:53:50.39#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.224.07:53:50.39#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.224.07:53:50.39#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.224.07:53:50.39#ibcon#ireg 7 cls_cnt 0 2006.224.07:53:50.39#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.224.07:53:50.51#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.224.07:53:50.51#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.224.07:53:50.51#ibcon#enter wrdev, iclass 19, count 0 2006.224.07:53:50.51#ibcon#first serial, iclass 19, count 0 2006.224.07:53:50.51#ibcon#enter sib2, iclass 19, count 0 2006.224.07:53:50.51#ibcon#flushed, iclass 19, count 0 2006.224.07:53:50.51#ibcon#about to write, iclass 19, count 0 2006.224.07:53:50.51#ibcon#wrote, iclass 19, count 0 2006.224.07:53:50.51#ibcon#about to read 3, iclass 19, count 0 2006.224.07:53:50.53#ibcon#read 3, iclass 19, count 0 2006.224.07:53:50.53#ibcon#about to read 4, iclass 19, count 0 2006.224.07:53:50.53#ibcon#read 4, iclass 19, count 0 2006.224.07:53:50.53#ibcon#about to read 5, iclass 19, count 0 2006.224.07:53:50.53#ibcon#read 5, iclass 19, count 0 2006.224.07:53:50.53#ibcon#about to read 6, iclass 19, count 0 2006.224.07:53:50.53#ibcon#read 6, iclass 19, count 0 2006.224.07:53:50.53#ibcon#end of sib2, iclass 19, count 0 2006.224.07:53:50.53#ibcon#*mode == 0, iclass 19, count 0 2006.224.07:53:50.53#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.224.07:53:50.53#ibcon#[25=USB\r\n] 2006.224.07:53:50.53#ibcon#*before write, iclass 19, count 0 2006.224.07:53:50.53#ibcon#enter sib2, iclass 19, count 0 2006.224.07:53:50.53#ibcon#flushed, iclass 19, count 0 2006.224.07:53:50.53#ibcon#about to write, iclass 19, count 0 2006.224.07:53:50.53#ibcon#wrote, iclass 19, count 0 2006.224.07:53:50.53#ibcon#about to read 3, iclass 19, count 0 2006.224.07:53:50.56#ibcon#read 3, iclass 19, count 0 2006.224.07:53:50.56#ibcon#about to read 4, iclass 19, count 0 2006.224.07:53:50.56#ibcon#read 4, iclass 19, count 0 2006.224.07:53:50.56#ibcon#about to read 5, iclass 19, count 0 2006.224.07:53:50.56#ibcon#read 5, iclass 19, count 0 2006.224.07:53:50.56#ibcon#about to read 6, iclass 19, count 0 2006.224.07:53:50.56#ibcon#read 6, iclass 19, count 0 2006.224.07:53:50.56#ibcon#end of sib2, iclass 19, count 0 2006.224.07:53:50.56#ibcon#*after write, iclass 19, count 0 2006.224.07:53:50.56#ibcon#*before return 0, iclass 19, count 0 2006.224.07:53:50.56#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.224.07:53:50.56#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.224.07:53:50.56#ibcon#about to clear, iclass 19 cls_cnt 0 2006.224.07:53:50.56#ibcon#cleared, iclass 19 cls_cnt 0 2006.224.07:53:50.56$vc4f8/vblo=1,632.99 2006.224.07:53:50.56#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.224.07:53:50.56#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.224.07:53:50.56#ibcon#ireg 17 cls_cnt 0 2006.224.07:53:50.56#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.224.07:53:50.56#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.224.07:53:50.56#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.224.07:53:50.56#ibcon#enter wrdev, iclass 21, count 0 2006.224.07:53:50.56#ibcon#first serial, iclass 21, count 0 2006.224.07:53:50.56#ibcon#enter sib2, iclass 21, count 0 2006.224.07:53:50.56#ibcon#flushed, iclass 21, count 0 2006.224.07:53:50.56#ibcon#about to write, iclass 21, count 0 2006.224.07:53:50.56#ibcon#wrote, iclass 21, count 0 2006.224.07:53:50.56#ibcon#about to read 3, iclass 21, count 0 2006.224.07:53:50.58#ibcon#read 3, iclass 21, count 0 2006.224.07:53:50.58#ibcon#about to read 4, iclass 21, count 0 2006.224.07:53:50.58#ibcon#read 4, iclass 21, count 0 2006.224.07:53:50.58#ibcon#about to read 5, iclass 21, count 0 2006.224.07:53:50.58#ibcon#read 5, iclass 21, count 0 2006.224.07:53:50.58#ibcon#about to read 6, iclass 21, count 0 2006.224.07:53:50.58#ibcon#read 6, iclass 21, count 0 2006.224.07:53:50.58#ibcon#end of sib2, iclass 21, count 0 2006.224.07:53:50.58#ibcon#*mode == 0, iclass 21, count 0 2006.224.07:53:50.58#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.224.07:53:50.58#ibcon#[28=FRQ=01,632.99\r\n] 2006.224.07:53:50.58#ibcon#*before write, iclass 21, count 0 2006.224.07:53:50.58#ibcon#enter sib2, iclass 21, count 0 2006.224.07:53:50.58#ibcon#flushed, iclass 21, count 0 2006.224.07:53:50.58#ibcon#about to write, iclass 21, count 0 2006.224.07:53:50.58#ibcon#wrote, iclass 21, count 0 2006.224.07:53:50.58#ibcon#about to read 3, iclass 21, count 0 2006.224.07:53:50.62#ibcon#read 3, iclass 21, count 0 2006.224.07:53:50.62#ibcon#about to read 4, iclass 21, count 0 2006.224.07:53:50.62#ibcon#read 4, iclass 21, count 0 2006.224.07:53:50.62#ibcon#about to read 5, iclass 21, count 0 2006.224.07:53:50.62#ibcon#read 5, iclass 21, count 0 2006.224.07:53:50.62#ibcon#about to read 6, iclass 21, count 0 2006.224.07:53:50.62#ibcon#read 6, iclass 21, count 0 2006.224.07:53:50.62#ibcon#end of sib2, iclass 21, count 0 2006.224.07:53:50.62#ibcon#*after write, iclass 21, count 0 2006.224.07:53:50.62#ibcon#*before return 0, iclass 21, count 0 2006.224.07:53:50.62#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.224.07:53:50.62#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.224.07:53:50.62#ibcon#about to clear, iclass 21 cls_cnt 0 2006.224.07:53:50.62#ibcon#cleared, iclass 21 cls_cnt 0 2006.224.07:53:50.62$vc4f8/vb=1,4 2006.224.07:53:50.62#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.224.07:53:50.62#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.224.07:53:50.62#ibcon#ireg 11 cls_cnt 2 2006.224.07:53:50.62#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.224.07:53:50.62#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.224.07:53:50.62#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.224.07:53:50.62#ibcon#enter wrdev, iclass 23, count 2 2006.224.07:53:50.62#ibcon#first serial, iclass 23, count 2 2006.224.07:53:50.62#ibcon#enter sib2, iclass 23, count 2 2006.224.07:53:50.62#ibcon#flushed, iclass 23, count 2 2006.224.07:53:50.62#ibcon#about to write, iclass 23, count 2 2006.224.07:53:50.62#ibcon#wrote, iclass 23, count 2 2006.224.07:53:50.62#ibcon#about to read 3, iclass 23, count 2 2006.224.07:53:50.64#ibcon#read 3, iclass 23, count 2 2006.224.07:53:50.64#ibcon#about to read 4, iclass 23, count 2 2006.224.07:53:50.64#ibcon#read 4, iclass 23, count 2 2006.224.07:53:50.64#ibcon#about to read 5, iclass 23, count 2 2006.224.07:53:50.64#ibcon#read 5, iclass 23, count 2 2006.224.07:53:50.64#ibcon#about to read 6, iclass 23, count 2 2006.224.07:53:50.64#ibcon#read 6, iclass 23, count 2 2006.224.07:53:50.64#ibcon#end of sib2, iclass 23, count 2 2006.224.07:53:50.64#ibcon#*mode == 0, iclass 23, count 2 2006.224.07:53:50.64#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.224.07:53:50.64#ibcon#[27=AT01-04\r\n] 2006.224.07:53:50.64#ibcon#*before write, iclass 23, count 2 2006.224.07:53:50.64#ibcon#enter sib2, iclass 23, count 2 2006.224.07:53:50.64#ibcon#flushed, iclass 23, count 2 2006.224.07:53:50.64#ibcon#about to write, iclass 23, count 2 2006.224.07:53:50.64#ibcon#wrote, iclass 23, count 2 2006.224.07:53:50.64#ibcon#about to read 3, iclass 23, count 2 2006.224.07:53:50.67#ibcon#read 3, iclass 23, count 2 2006.224.07:53:50.67#ibcon#about to read 4, iclass 23, count 2 2006.224.07:53:50.67#ibcon#read 4, iclass 23, count 2 2006.224.07:53:50.67#ibcon#about to read 5, iclass 23, count 2 2006.224.07:53:50.67#ibcon#read 5, iclass 23, count 2 2006.224.07:53:50.67#ibcon#about to read 6, iclass 23, count 2 2006.224.07:53:50.67#ibcon#read 6, iclass 23, count 2 2006.224.07:53:50.67#ibcon#end of sib2, iclass 23, count 2 2006.224.07:53:50.67#ibcon#*after write, iclass 23, count 2 2006.224.07:53:50.67#ibcon#*before return 0, iclass 23, count 2 2006.224.07:53:50.67#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.224.07:53:50.67#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.224.07:53:50.67#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.224.07:53:50.67#ibcon#ireg 7 cls_cnt 0 2006.224.07:53:50.67#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.224.07:53:50.79#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.224.07:53:50.79#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.224.07:53:50.79#ibcon#enter wrdev, iclass 23, count 0 2006.224.07:53:50.79#ibcon#first serial, iclass 23, count 0 2006.224.07:53:50.79#ibcon#enter sib2, iclass 23, count 0 2006.224.07:53:50.79#ibcon#flushed, iclass 23, count 0 2006.224.07:53:50.79#ibcon#about to write, iclass 23, count 0 2006.224.07:53:50.79#ibcon#wrote, iclass 23, count 0 2006.224.07:53:50.79#ibcon#about to read 3, iclass 23, count 0 2006.224.07:53:50.81#ibcon#read 3, iclass 23, count 0 2006.224.07:53:50.81#ibcon#about to read 4, iclass 23, count 0 2006.224.07:53:50.81#ibcon#read 4, iclass 23, count 0 2006.224.07:53:50.81#ibcon#about to read 5, iclass 23, count 0 2006.224.07:53:50.81#ibcon#read 5, iclass 23, count 0 2006.224.07:53:50.81#ibcon#about to read 6, iclass 23, count 0 2006.224.07:53:50.81#ibcon#read 6, iclass 23, count 0 2006.224.07:53:50.81#ibcon#end of sib2, iclass 23, count 0 2006.224.07:53:50.81#ibcon#*mode == 0, iclass 23, count 0 2006.224.07:53:50.81#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.224.07:53:50.81#ibcon#[27=USB\r\n] 2006.224.07:53:50.81#ibcon#*before write, iclass 23, count 0 2006.224.07:53:50.81#ibcon#enter sib2, iclass 23, count 0 2006.224.07:53:50.81#ibcon#flushed, iclass 23, count 0 2006.224.07:53:50.81#ibcon#about to write, iclass 23, count 0 2006.224.07:53:50.81#ibcon#wrote, iclass 23, count 0 2006.224.07:53:50.81#ibcon#about to read 3, iclass 23, count 0 2006.224.07:53:50.84#ibcon#read 3, iclass 23, count 0 2006.224.07:53:50.84#ibcon#about to read 4, iclass 23, count 0 2006.224.07:53:50.84#ibcon#read 4, iclass 23, count 0 2006.224.07:53:50.84#ibcon#about to read 5, iclass 23, count 0 2006.224.07:53:50.84#ibcon#read 5, iclass 23, count 0 2006.224.07:53:50.84#ibcon#about to read 6, iclass 23, count 0 2006.224.07:53:50.84#ibcon#read 6, iclass 23, count 0 2006.224.07:53:50.84#ibcon#end of sib2, iclass 23, count 0 2006.224.07:53:50.84#ibcon#*after write, iclass 23, count 0 2006.224.07:53:50.84#ibcon#*before return 0, iclass 23, count 0 2006.224.07:53:50.84#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.224.07:53:50.84#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.224.07:53:50.84#ibcon#about to clear, iclass 23 cls_cnt 0 2006.224.07:53:50.84#ibcon#cleared, iclass 23 cls_cnt 0 2006.224.07:53:50.84$vc4f8/vblo=2,640.99 2006.224.07:53:50.84#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.224.07:53:50.84#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.224.07:53:50.84#ibcon#ireg 17 cls_cnt 0 2006.224.07:53:50.84#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.224.07:53:50.84#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.224.07:53:50.84#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.224.07:53:50.84#ibcon#enter wrdev, iclass 25, count 0 2006.224.07:53:50.84#ibcon#first serial, iclass 25, count 0 2006.224.07:53:50.84#ibcon#enter sib2, iclass 25, count 0 2006.224.07:53:50.84#ibcon#flushed, iclass 25, count 0 2006.224.07:53:50.84#ibcon#about to write, iclass 25, count 0 2006.224.07:53:50.84#ibcon#wrote, iclass 25, count 0 2006.224.07:53:50.84#ibcon#about to read 3, iclass 25, count 0 2006.224.07:53:50.86#ibcon#read 3, iclass 25, count 0 2006.224.07:53:50.86#ibcon#about to read 4, iclass 25, count 0 2006.224.07:53:50.86#ibcon#read 4, iclass 25, count 0 2006.224.07:53:50.86#ibcon#about to read 5, iclass 25, count 0 2006.224.07:53:50.86#ibcon#read 5, iclass 25, count 0 2006.224.07:53:50.86#ibcon#about to read 6, iclass 25, count 0 2006.224.07:53:50.86#ibcon#read 6, iclass 25, count 0 2006.224.07:53:50.86#ibcon#end of sib2, iclass 25, count 0 2006.224.07:53:50.86#ibcon#*mode == 0, iclass 25, count 0 2006.224.07:53:50.86#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.224.07:53:50.86#ibcon#[28=FRQ=02,640.99\r\n] 2006.224.07:53:50.86#ibcon#*before write, iclass 25, count 0 2006.224.07:53:50.86#ibcon#enter sib2, iclass 25, count 0 2006.224.07:53:50.86#ibcon#flushed, iclass 25, count 0 2006.224.07:53:50.86#ibcon#about to write, iclass 25, count 0 2006.224.07:53:50.86#ibcon#wrote, iclass 25, count 0 2006.224.07:53:50.86#ibcon#about to read 3, iclass 25, count 0 2006.224.07:53:50.90#ibcon#read 3, iclass 25, count 0 2006.224.07:53:50.90#ibcon#about to read 4, iclass 25, count 0 2006.224.07:53:50.90#ibcon#read 4, iclass 25, count 0 2006.224.07:53:50.90#ibcon#about to read 5, iclass 25, count 0 2006.224.07:53:50.90#ibcon#read 5, iclass 25, count 0 2006.224.07:53:50.90#ibcon#about to read 6, iclass 25, count 0 2006.224.07:53:50.90#ibcon#read 6, iclass 25, count 0 2006.224.07:53:50.90#ibcon#end of sib2, iclass 25, count 0 2006.224.07:53:50.90#ibcon#*after write, iclass 25, count 0 2006.224.07:53:50.90#ibcon#*before return 0, iclass 25, count 0 2006.224.07:53:50.90#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.224.07:53:50.90#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.224.07:53:50.90#ibcon#about to clear, iclass 25 cls_cnt 0 2006.224.07:53:50.90#ibcon#cleared, iclass 25 cls_cnt 0 2006.224.07:53:50.90$vc4f8/vb=2,4 2006.224.07:53:50.90#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.224.07:53:50.90#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.224.07:53:50.90#ibcon#ireg 11 cls_cnt 2 2006.224.07:53:50.90#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.224.07:53:50.96#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.224.07:53:50.96#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.224.07:53:50.96#ibcon#enter wrdev, iclass 27, count 2 2006.224.07:53:50.96#ibcon#first serial, iclass 27, count 2 2006.224.07:53:50.96#ibcon#enter sib2, iclass 27, count 2 2006.224.07:53:50.96#ibcon#flushed, iclass 27, count 2 2006.224.07:53:50.96#ibcon#about to write, iclass 27, count 2 2006.224.07:53:50.96#ibcon#wrote, iclass 27, count 2 2006.224.07:53:50.96#ibcon#about to read 3, iclass 27, count 2 2006.224.07:53:50.98#ibcon#read 3, iclass 27, count 2 2006.224.07:53:50.98#ibcon#about to read 4, iclass 27, count 2 2006.224.07:53:50.98#ibcon#read 4, iclass 27, count 2 2006.224.07:53:50.98#ibcon#about to read 5, iclass 27, count 2 2006.224.07:53:50.98#ibcon#read 5, iclass 27, count 2 2006.224.07:53:50.98#ibcon#about to read 6, iclass 27, count 2 2006.224.07:53:50.98#ibcon#read 6, iclass 27, count 2 2006.224.07:53:50.98#ibcon#end of sib2, iclass 27, count 2 2006.224.07:53:50.98#ibcon#*mode == 0, iclass 27, count 2 2006.224.07:53:50.98#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.224.07:53:50.98#ibcon#[27=AT02-04\r\n] 2006.224.07:53:50.98#ibcon#*before write, iclass 27, count 2 2006.224.07:53:50.98#ibcon#enter sib2, iclass 27, count 2 2006.224.07:53:50.98#ibcon#flushed, iclass 27, count 2 2006.224.07:53:50.98#ibcon#about to write, iclass 27, count 2 2006.224.07:53:50.98#ibcon#wrote, iclass 27, count 2 2006.224.07:53:50.98#ibcon#about to read 3, iclass 27, count 2 2006.224.07:53:51.01#ibcon#read 3, iclass 27, count 2 2006.224.07:53:51.01#ibcon#about to read 4, iclass 27, count 2 2006.224.07:53:51.01#ibcon#read 4, iclass 27, count 2 2006.224.07:53:51.01#ibcon#about to read 5, iclass 27, count 2 2006.224.07:53:51.01#ibcon#read 5, iclass 27, count 2 2006.224.07:53:51.01#ibcon#about to read 6, iclass 27, count 2 2006.224.07:53:51.01#ibcon#read 6, iclass 27, count 2 2006.224.07:53:51.01#ibcon#end of sib2, iclass 27, count 2 2006.224.07:53:51.01#ibcon#*after write, iclass 27, count 2 2006.224.07:53:51.01#ibcon#*before return 0, iclass 27, count 2 2006.224.07:53:51.01#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.224.07:53:51.01#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.224.07:53:51.01#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.224.07:53:51.01#ibcon#ireg 7 cls_cnt 0 2006.224.07:53:51.01#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.224.07:53:51.13#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.224.07:53:51.13#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.224.07:53:51.13#ibcon#enter wrdev, iclass 27, count 0 2006.224.07:53:51.13#ibcon#first serial, iclass 27, count 0 2006.224.07:53:51.13#ibcon#enter sib2, iclass 27, count 0 2006.224.07:53:51.13#ibcon#flushed, iclass 27, count 0 2006.224.07:53:51.13#ibcon#about to write, iclass 27, count 0 2006.224.07:53:51.13#ibcon#wrote, iclass 27, count 0 2006.224.07:53:51.13#ibcon#about to read 3, iclass 27, count 0 2006.224.07:53:51.15#ibcon#read 3, iclass 27, count 0 2006.224.07:53:51.15#ibcon#about to read 4, iclass 27, count 0 2006.224.07:53:51.15#ibcon#read 4, iclass 27, count 0 2006.224.07:53:51.15#ibcon#about to read 5, iclass 27, count 0 2006.224.07:53:51.15#ibcon#read 5, iclass 27, count 0 2006.224.07:53:51.15#ibcon#about to read 6, iclass 27, count 0 2006.224.07:53:51.15#ibcon#read 6, iclass 27, count 0 2006.224.07:53:51.15#ibcon#end of sib2, iclass 27, count 0 2006.224.07:53:51.15#ibcon#*mode == 0, iclass 27, count 0 2006.224.07:53:51.15#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.224.07:53:51.15#ibcon#[27=USB\r\n] 2006.224.07:53:51.15#ibcon#*before write, iclass 27, count 0 2006.224.07:53:51.15#ibcon#enter sib2, iclass 27, count 0 2006.224.07:53:51.15#ibcon#flushed, iclass 27, count 0 2006.224.07:53:51.15#ibcon#about to write, iclass 27, count 0 2006.224.07:53:51.15#ibcon#wrote, iclass 27, count 0 2006.224.07:53:51.15#ibcon#about to read 3, iclass 27, count 0 2006.224.07:53:51.18#ibcon#read 3, iclass 27, count 0 2006.224.07:53:51.18#ibcon#about to read 4, iclass 27, count 0 2006.224.07:53:51.18#ibcon#read 4, iclass 27, count 0 2006.224.07:53:51.18#ibcon#about to read 5, iclass 27, count 0 2006.224.07:53:51.18#ibcon#read 5, iclass 27, count 0 2006.224.07:53:51.18#ibcon#about to read 6, iclass 27, count 0 2006.224.07:53:51.18#ibcon#read 6, iclass 27, count 0 2006.224.07:53:51.18#ibcon#end of sib2, iclass 27, count 0 2006.224.07:53:51.18#ibcon#*after write, iclass 27, count 0 2006.224.07:53:51.18#ibcon#*before return 0, iclass 27, count 0 2006.224.07:53:51.18#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.224.07:53:51.18#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.224.07:53:51.18#ibcon#about to clear, iclass 27 cls_cnt 0 2006.224.07:53:51.18#ibcon#cleared, iclass 27 cls_cnt 0 2006.224.07:53:51.18$vc4f8/vblo=3,656.99 2006.224.07:53:51.18#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.224.07:53:51.18#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.224.07:53:51.18#ibcon#ireg 17 cls_cnt 0 2006.224.07:53:51.18#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.224.07:53:51.18#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.224.07:53:51.18#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.224.07:53:51.18#ibcon#enter wrdev, iclass 29, count 0 2006.224.07:53:51.18#ibcon#first serial, iclass 29, count 0 2006.224.07:53:51.18#ibcon#enter sib2, iclass 29, count 0 2006.224.07:53:51.18#ibcon#flushed, iclass 29, count 0 2006.224.07:53:51.18#ibcon#about to write, iclass 29, count 0 2006.224.07:53:51.18#ibcon#wrote, iclass 29, count 0 2006.224.07:53:51.18#ibcon#about to read 3, iclass 29, count 0 2006.224.07:53:51.20#ibcon#read 3, iclass 29, count 0 2006.224.07:53:51.20#ibcon#about to read 4, iclass 29, count 0 2006.224.07:53:51.20#ibcon#read 4, iclass 29, count 0 2006.224.07:53:51.20#ibcon#about to read 5, iclass 29, count 0 2006.224.07:53:51.20#ibcon#read 5, iclass 29, count 0 2006.224.07:53:51.20#ibcon#about to read 6, iclass 29, count 0 2006.224.07:53:51.20#ibcon#read 6, iclass 29, count 0 2006.224.07:53:51.20#ibcon#end of sib2, iclass 29, count 0 2006.224.07:53:51.20#ibcon#*mode == 0, iclass 29, count 0 2006.224.07:53:51.20#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.224.07:53:51.20#ibcon#[28=FRQ=03,656.99\r\n] 2006.224.07:53:51.20#ibcon#*before write, iclass 29, count 0 2006.224.07:53:51.20#ibcon#enter sib2, iclass 29, count 0 2006.224.07:53:51.20#ibcon#flushed, iclass 29, count 0 2006.224.07:53:51.20#ibcon#about to write, iclass 29, count 0 2006.224.07:53:51.20#ibcon#wrote, iclass 29, count 0 2006.224.07:53:51.20#ibcon#about to read 3, iclass 29, count 0 2006.224.07:53:51.24#ibcon#read 3, iclass 29, count 0 2006.224.07:53:51.24#ibcon#about to read 4, iclass 29, count 0 2006.224.07:53:51.24#ibcon#read 4, iclass 29, count 0 2006.224.07:53:51.24#ibcon#about to read 5, iclass 29, count 0 2006.224.07:53:51.24#ibcon#read 5, iclass 29, count 0 2006.224.07:53:51.24#ibcon#about to read 6, iclass 29, count 0 2006.224.07:53:51.24#ibcon#read 6, iclass 29, count 0 2006.224.07:53:51.24#ibcon#end of sib2, iclass 29, count 0 2006.224.07:53:51.24#ibcon#*after write, iclass 29, count 0 2006.224.07:53:51.24#ibcon#*before return 0, iclass 29, count 0 2006.224.07:53:51.24#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.224.07:53:51.24#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.224.07:53:51.24#ibcon#about to clear, iclass 29 cls_cnt 0 2006.224.07:53:51.24#ibcon#cleared, iclass 29 cls_cnt 0 2006.224.07:53:51.24$vc4f8/vb=3,4 2006.224.07:53:51.24#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.224.07:53:51.24#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.224.07:53:51.24#ibcon#ireg 11 cls_cnt 2 2006.224.07:53:51.24#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.224.07:53:51.30#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.224.07:53:51.30#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.224.07:53:51.30#ibcon#enter wrdev, iclass 31, count 2 2006.224.07:53:51.30#ibcon#first serial, iclass 31, count 2 2006.224.07:53:51.30#ibcon#enter sib2, iclass 31, count 2 2006.224.07:53:51.30#ibcon#flushed, iclass 31, count 2 2006.224.07:53:51.30#ibcon#about to write, iclass 31, count 2 2006.224.07:53:51.30#ibcon#wrote, iclass 31, count 2 2006.224.07:53:51.30#ibcon#about to read 3, iclass 31, count 2 2006.224.07:53:51.32#ibcon#read 3, iclass 31, count 2 2006.224.07:53:51.32#ibcon#about to read 4, iclass 31, count 2 2006.224.07:53:51.32#ibcon#read 4, iclass 31, count 2 2006.224.07:53:51.32#ibcon#about to read 5, iclass 31, count 2 2006.224.07:53:51.32#ibcon#read 5, iclass 31, count 2 2006.224.07:53:51.32#ibcon#about to read 6, iclass 31, count 2 2006.224.07:53:51.32#ibcon#read 6, iclass 31, count 2 2006.224.07:53:51.32#ibcon#end of sib2, iclass 31, count 2 2006.224.07:53:51.32#ibcon#*mode == 0, iclass 31, count 2 2006.224.07:53:51.32#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.224.07:53:51.32#ibcon#[27=AT03-04\r\n] 2006.224.07:53:51.32#ibcon#*before write, iclass 31, count 2 2006.224.07:53:51.32#ibcon#enter sib2, iclass 31, count 2 2006.224.07:53:51.32#ibcon#flushed, iclass 31, count 2 2006.224.07:53:51.32#ibcon#about to write, iclass 31, count 2 2006.224.07:53:51.32#ibcon#wrote, iclass 31, count 2 2006.224.07:53:51.32#ibcon#about to read 3, iclass 31, count 2 2006.224.07:53:51.35#ibcon#read 3, iclass 31, count 2 2006.224.07:53:51.35#ibcon#about to read 4, iclass 31, count 2 2006.224.07:53:51.35#ibcon#read 4, iclass 31, count 2 2006.224.07:53:51.35#ibcon#about to read 5, iclass 31, count 2 2006.224.07:53:51.35#ibcon#read 5, iclass 31, count 2 2006.224.07:53:51.35#ibcon#about to read 6, iclass 31, count 2 2006.224.07:53:51.35#ibcon#read 6, iclass 31, count 2 2006.224.07:53:51.35#ibcon#end of sib2, iclass 31, count 2 2006.224.07:53:51.35#ibcon#*after write, iclass 31, count 2 2006.224.07:53:51.35#ibcon#*before return 0, iclass 31, count 2 2006.224.07:53:51.35#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.224.07:53:51.35#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.224.07:53:51.35#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.224.07:53:51.35#ibcon#ireg 7 cls_cnt 0 2006.224.07:53:51.35#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.224.07:53:51.47#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.224.07:53:51.47#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.224.07:53:51.47#ibcon#enter wrdev, iclass 31, count 0 2006.224.07:53:51.47#ibcon#first serial, iclass 31, count 0 2006.224.07:53:51.47#ibcon#enter sib2, iclass 31, count 0 2006.224.07:53:51.47#ibcon#flushed, iclass 31, count 0 2006.224.07:53:51.47#ibcon#about to write, iclass 31, count 0 2006.224.07:53:51.47#ibcon#wrote, iclass 31, count 0 2006.224.07:53:51.47#ibcon#about to read 3, iclass 31, count 0 2006.224.07:53:51.49#ibcon#read 3, iclass 31, count 0 2006.224.07:53:51.49#ibcon#about to read 4, iclass 31, count 0 2006.224.07:53:51.49#ibcon#read 4, iclass 31, count 0 2006.224.07:53:51.49#ibcon#about to read 5, iclass 31, count 0 2006.224.07:53:51.49#ibcon#read 5, iclass 31, count 0 2006.224.07:53:51.49#ibcon#about to read 6, iclass 31, count 0 2006.224.07:53:51.49#ibcon#read 6, iclass 31, count 0 2006.224.07:53:51.49#ibcon#end of sib2, iclass 31, count 0 2006.224.07:53:51.49#ibcon#*mode == 0, iclass 31, count 0 2006.224.07:53:51.49#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.224.07:53:51.49#ibcon#[27=USB\r\n] 2006.224.07:53:51.49#ibcon#*before write, iclass 31, count 0 2006.224.07:53:51.49#ibcon#enter sib2, iclass 31, count 0 2006.224.07:53:51.49#ibcon#flushed, iclass 31, count 0 2006.224.07:53:51.49#ibcon#about to write, iclass 31, count 0 2006.224.07:53:51.49#ibcon#wrote, iclass 31, count 0 2006.224.07:53:51.49#ibcon#about to read 3, iclass 31, count 0 2006.224.07:53:51.52#ibcon#read 3, iclass 31, count 0 2006.224.07:53:51.52#ibcon#about to read 4, iclass 31, count 0 2006.224.07:53:51.52#ibcon#read 4, iclass 31, count 0 2006.224.07:53:51.52#ibcon#about to read 5, iclass 31, count 0 2006.224.07:53:51.52#ibcon#read 5, iclass 31, count 0 2006.224.07:53:51.52#ibcon#about to read 6, iclass 31, count 0 2006.224.07:53:51.52#ibcon#read 6, iclass 31, count 0 2006.224.07:53:51.52#ibcon#end of sib2, iclass 31, count 0 2006.224.07:53:51.52#ibcon#*after write, iclass 31, count 0 2006.224.07:53:51.52#ibcon#*before return 0, iclass 31, count 0 2006.224.07:53:51.52#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.224.07:53:51.52#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.224.07:53:51.52#ibcon#about to clear, iclass 31 cls_cnt 0 2006.224.07:53:51.52#ibcon#cleared, iclass 31 cls_cnt 0 2006.224.07:53:51.52$vc4f8/vblo=4,712.99 2006.224.07:53:51.52#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.224.07:53:51.52#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.224.07:53:51.52#ibcon#ireg 17 cls_cnt 0 2006.224.07:53:51.52#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.224.07:53:51.52#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.224.07:53:51.52#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.224.07:53:51.52#ibcon#enter wrdev, iclass 33, count 0 2006.224.07:53:51.52#ibcon#first serial, iclass 33, count 0 2006.224.07:53:51.52#ibcon#enter sib2, iclass 33, count 0 2006.224.07:53:51.52#ibcon#flushed, iclass 33, count 0 2006.224.07:53:51.52#ibcon#about to write, iclass 33, count 0 2006.224.07:53:51.52#ibcon#wrote, iclass 33, count 0 2006.224.07:53:51.52#ibcon#about to read 3, iclass 33, count 0 2006.224.07:53:51.54#ibcon#read 3, iclass 33, count 0 2006.224.07:53:51.54#ibcon#about to read 4, iclass 33, count 0 2006.224.07:53:51.54#ibcon#read 4, iclass 33, count 0 2006.224.07:53:51.54#ibcon#about to read 5, iclass 33, count 0 2006.224.07:53:51.54#ibcon#read 5, iclass 33, count 0 2006.224.07:53:51.54#ibcon#about to read 6, iclass 33, count 0 2006.224.07:53:51.54#ibcon#read 6, iclass 33, count 0 2006.224.07:53:51.54#ibcon#end of sib2, iclass 33, count 0 2006.224.07:53:51.54#ibcon#*mode == 0, iclass 33, count 0 2006.224.07:53:51.54#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.224.07:53:51.54#ibcon#[28=FRQ=04,712.99\r\n] 2006.224.07:53:51.54#ibcon#*before write, iclass 33, count 0 2006.224.07:53:51.54#ibcon#enter sib2, iclass 33, count 0 2006.224.07:53:51.54#ibcon#flushed, iclass 33, count 0 2006.224.07:53:51.54#ibcon#about to write, iclass 33, count 0 2006.224.07:53:51.54#ibcon#wrote, iclass 33, count 0 2006.224.07:53:51.54#ibcon#about to read 3, iclass 33, count 0 2006.224.07:53:51.58#ibcon#read 3, iclass 33, count 0 2006.224.07:53:51.58#ibcon#about to read 4, iclass 33, count 0 2006.224.07:53:51.58#ibcon#read 4, iclass 33, count 0 2006.224.07:53:51.58#ibcon#about to read 5, iclass 33, count 0 2006.224.07:53:51.58#ibcon#read 5, iclass 33, count 0 2006.224.07:53:51.58#ibcon#about to read 6, iclass 33, count 0 2006.224.07:53:51.58#ibcon#read 6, iclass 33, count 0 2006.224.07:53:51.58#ibcon#end of sib2, iclass 33, count 0 2006.224.07:53:51.58#ibcon#*after write, iclass 33, count 0 2006.224.07:53:51.58#ibcon#*before return 0, iclass 33, count 0 2006.224.07:53:51.58#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.224.07:53:51.58#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.224.07:53:51.58#ibcon#about to clear, iclass 33 cls_cnt 0 2006.224.07:53:51.58#ibcon#cleared, iclass 33 cls_cnt 0 2006.224.07:53:51.58$vc4f8/vb=4,4 2006.224.07:53:51.58#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.224.07:53:51.58#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.224.07:53:51.58#ibcon#ireg 11 cls_cnt 2 2006.224.07:53:51.58#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.224.07:53:51.64#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.224.07:53:51.64#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.224.07:53:51.64#ibcon#enter wrdev, iclass 35, count 2 2006.224.07:53:51.64#ibcon#first serial, iclass 35, count 2 2006.224.07:53:51.64#ibcon#enter sib2, iclass 35, count 2 2006.224.07:53:51.64#ibcon#flushed, iclass 35, count 2 2006.224.07:53:51.64#ibcon#about to write, iclass 35, count 2 2006.224.07:53:51.64#ibcon#wrote, iclass 35, count 2 2006.224.07:53:51.64#ibcon#about to read 3, iclass 35, count 2 2006.224.07:53:51.66#ibcon#read 3, iclass 35, count 2 2006.224.07:53:51.66#ibcon#about to read 4, iclass 35, count 2 2006.224.07:53:51.66#ibcon#read 4, iclass 35, count 2 2006.224.07:53:51.66#ibcon#about to read 5, iclass 35, count 2 2006.224.07:53:51.66#ibcon#read 5, iclass 35, count 2 2006.224.07:53:51.66#ibcon#about to read 6, iclass 35, count 2 2006.224.07:53:51.66#ibcon#read 6, iclass 35, count 2 2006.224.07:53:51.66#ibcon#end of sib2, iclass 35, count 2 2006.224.07:53:51.66#ibcon#*mode == 0, iclass 35, count 2 2006.224.07:53:51.66#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.224.07:53:51.66#ibcon#[27=AT04-04\r\n] 2006.224.07:53:51.66#ibcon#*before write, iclass 35, count 2 2006.224.07:53:51.66#ibcon#enter sib2, iclass 35, count 2 2006.224.07:53:51.66#ibcon#flushed, iclass 35, count 2 2006.224.07:53:51.66#ibcon#about to write, iclass 35, count 2 2006.224.07:53:51.66#ibcon#wrote, iclass 35, count 2 2006.224.07:53:51.66#ibcon#about to read 3, iclass 35, count 2 2006.224.07:53:51.69#ibcon#read 3, iclass 35, count 2 2006.224.07:53:51.69#ibcon#about to read 4, iclass 35, count 2 2006.224.07:53:51.69#ibcon#read 4, iclass 35, count 2 2006.224.07:53:51.69#ibcon#about to read 5, iclass 35, count 2 2006.224.07:53:51.69#ibcon#read 5, iclass 35, count 2 2006.224.07:53:51.69#ibcon#about to read 6, iclass 35, count 2 2006.224.07:53:51.69#ibcon#read 6, iclass 35, count 2 2006.224.07:53:51.69#ibcon#end of sib2, iclass 35, count 2 2006.224.07:53:51.69#ibcon#*after write, iclass 35, count 2 2006.224.07:53:51.69#ibcon#*before return 0, iclass 35, count 2 2006.224.07:53:51.69#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.224.07:53:51.69#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.224.07:53:51.69#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.224.07:53:51.69#ibcon#ireg 7 cls_cnt 0 2006.224.07:53:51.69#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.224.07:53:51.81#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.224.07:53:51.81#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.224.07:53:51.81#ibcon#enter wrdev, iclass 35, count 0 2006.224.07:53:51.81#ibcon#first serial, iclass 35, count 0 2006.224.07:53:51.81#ibcon#enter sib2, iclass 35, count 0 2006.224.07:53:51.81#ibcon#flushed, iclass 35, count 0 2006.224.07:53:51.81#ibcon#about to write, iclass 35, count 0 2006.224.07:53:51.81#ibcon#wrote, iclass 35, count 0 2006.224.07:53:51.81#ibcon#about to read 3, iclass 35, count 0 2006.224.07:53:51.83#ibcon#read 3, iclass 35, count 0 2006.224.07:53:51.83#ibcon#about to read 4, iclass 35, count 0 2006.224.07:53:51.83#ibcon#read 4, iclass 35, count 0 2006.224.07:53:51.83#ibcon#about to read 5, iclass 35, count 0 2006.224.07:53:51.83#ibcon#read 5, iclass 35, count 0 2006.224.07:53:51.83#ibcon#about to read 6, iclass 35, count 0 2006.224.07:53:51.83#ibcon#read 6, iclass 35, count 0 2006.224.07:53:51.83#ibcon#end of sib2, iclass 35, count 0 2006.224.07:53:51.83#ibcon#*mode == 0, iclass 35, count 0 2006.224.07:53:51.83#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.224.07:53:51.83#ibcon#[27=USB\r\n] 2006.224.07:53:51.83#ibcon#*before write, iclass 35, count 0 2006.224.07:53:51.83#ibcon#enter sib2, iclass 35, count 0 2006.224.07:53:51.83#ibcon#flushed, iclass 35, count 0 2006.224.07:53:51.83#ibcon#about to write, iclass 35, count 0 2006.224.07:53:51.83#ibcon#wrote, iclass 35, count 0 2006.224.07:53:51.83#ibcon#about to read 3, iclass 35, count 0 2006.224.07:53:51.86#ibcon#read 3, iclass 35, count 0 2006.224.07:53:51.86#ibcon#about to read 4, iclass 35, count 0 2006.224.07:53:51.86#ibcon#read 4, iclass 35, count 0 2006.224.07:53:51.86#ibcon#about to read 5, iclass 35, count 0 2006.224.07:53:51.86#ibcon#read 5, iclass 35, count 0 2006.224.07:53:51.86#ibcon#about to read 6, iclass 35, count 0 2006.224.07:53:51.86#ibcon#read 6, iclass 35, count 0 2006.224.07:53:51.86#ibcon#end of sib2, iclass 35, count 0 2006.224.07:53:51.86#ibcon#*after write, iclass 35, count 0 2006.224.07:53:51.86#ibcon#*before return 0, iclass 35, count 0 2006.224.07:53:51.86#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.224.07:53:51.86#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.224.07:53:51.86#ibcon#about to clear, iclass 35 cls_cnt 0 2006.224.07:53:51.86#ibcon#cleared, iclass 35 cls_cnt 0 2006.224.07:53:51.86$vc4f8/vblo=5,744.99 2006.224.07:53:51.86#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.224.07:53:51.86#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.224.07:53:51.86#ibcon#ireg 17 cls_cnt 0 2006.224.07:53:51.86#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.224.07:53:51.86#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.224.07:53:51.86#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.224.07:53:51.86#ibcon#enter wrdev, iclass 37, count 0 2006.224.07:53:51.86#ibcon#first serial, iclass 37, count 0 2006.224.07:53:51.86#ibcon#enter sib2, iclass 37, count 0 2006.224.07:53:51.86#ibcon#flushed, iclass 37, count 0 2006.224.07:53:51.86#ibcon#about to write, iclass 37, count 0 2006.224.07:53:51.86#ibcon#wrote, iclass 37, count 0 2006.224.07:53:51.86#ibcon#about to read 3, iclass 37, count 0 2006.224.07:53:51.88#ibcon#read 3, iclass 37, count 0 2006.224.07:53:51.88#ibcon#about to read 4, iclass 37, count 0 2006.224.07:53:51.88#ibcon#read 4, iclass 37, count 0 2006.224.07:53:51.88#ibcon#about to read 5, iclass 37, count 0 2006.224.07:53:51.88#ibcon#read 5, iclass 37, count 0 2006.224.07:53:51.88#ibcon#about to read 6, iclass 37, count 0 2006.224.07:53:51.88#ibcon#read 6, iclass 37, count 0 2006.224.07:53:51.88#ibcon#end of sib2, iclass 37, count 0 2006.224.07:53:51.88#ibcon#*mode == 0, iclass 37, count 0 2006.224.07:53:51.88#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.224.07:53:51.88#ibcon#[28=FRQ=05,744.99\r\n] 2006.224.07:53:51.88#ibcon#*before write, iclass 37, count 0 2006.224.07:53:51.88#ibcon#enter sib2, iclass 37, count 0 2006.224.07:53:51.88#ibcon#flushed, iclass 37, count 0 2006.224.07:53:51.88#ibcon#about to write, iclass 37, count 0 2006.224.07:53:51.88#ibcon#wrote, iclass 37, count 0 2006.224.07:53:51.88#ibcon#about to read 3, iclass 37, count 0 2006.224.07:53:51.92#ibcon#read 3, iclass 37, count 0 2006.224.07:53:51.92#ibcon#about to read 4, iclass 37, count 0 2006.224.07:53:51.92#ibcon#read 4, iclass 37, count 0 2006.224.07:53:51.92#ibcon#about to read 5, iclass 37, count 0 2006.224.07:53:51.92#ibcon#read 5, iclass 37, count 0 2006.224.07:53:51.92#ibcon#about to read 6, iclass 37, count 0 2006.224.07:53:51.92#ibcon#read 6, iclass 37, count 0 2006.224.07:53:51.92#ibcon#end of sib2, iclass 37, count 0 2006.224.07:53:51.92#ibcon#*after write, iclass 37, count 0 2006.224.07:53:51.92#ibcon#*before return 0, iclass 37, count 0 2006.224.07:53:51.92#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.224.07:53:51.92#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.224.07:53:51.92#ibcon#about to clear, iclass 37 cls_cnt 0 2006.224.07:53:51.92#ibcon#cleared, iclass 37 cls_cnt 0 2006.224.07:53:51.92$vc4f8/vb=5,4 2006.224.07:53:51.92#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.224.07:53:51.92#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.224.07:53:51.92#ibcon#ireg 11 cls_cnt 2 2006.224.07:53:51.92#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.224.07:53:51.98#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.224.07:53:51.98#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.224.07:53:51.98#ibcon#enter wrdev, iclass 39, count 2 2006.224.07:53:51.98#ibcon#first serial, iclass 39, count 2 2006.224.07:53:51.98#ibcon#enter sib2, iclass 39, count 2 2006.224.07:53:51.98#ibcon#flushed, iclass 39, count 2 2006.224.07:53:51.98#ibcon#about to write, iclass 39, count 2 2006.224.07:53:51.98#ibcon#wrote, iclass 39, count 2 2006.224.07:53:51.98#ibcon#about to read 3, iclass 39, count 2 2006.224.07:53:52.00#ibcon#read 3, iclass 39, count 2 2006.224.07:53:52.00#ibcon#about to read 4, iclass 39, count 2 2006.224.07:53:52.00#ibcon#read 4, iclass 39, count 2 2006.224.07:53:52.00#ibcon#about to read 5, iclass 39, count 2 2006.224.07:53:52.00#ibcon#read 5, iclass 39, count 2 2006.224.07:53:52.00#ibcon#about to read 6, iclass 39, count 2 2006.224.07:53:52.00#ibcon#read 6, iclass 39, count 2 2006.224.07:53:52.00#ibcon#end of sib2, iclass 39, count 2 2006.224.07:53:52.00#ibcon#*mode == 0, iclass 39, count 2 2006.224.07:53:52.00#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.224.07:53:52.00#ibcon#[27=AT05-04\r\n] 2006.224.07:53:52.00#ibcon#*before write, iclass 39, count 2 2006.224.07:53:52.00#ibcon#enter sib2, iclass 39, count 2 2006.224.07:53:52.00#ibcon#flushed, iclass 39, count 2 2006.224.07:53:52.00#ibcon#about to write, iclass 39, count 2 2006.224.07:53:52.00#ibcon#wrote, iclass 39, count 2 2006.224.07:53:52.00#ibcon#about to read 3, iclass 39, count 2 2006.224.07:53:52.03#ibcon#read 3, iclass 39, count 2 2006.224.07:53:52.03#ibcon#about to read 4, iclass 39, count 2 2006.224.07:53:52.03#ibcon#read 4, iclass 39, count 2 2006.224.07:53:52.03#ibcon#about to read 5, iclass 39, count 2 2006.224.07:53:52.03#ibcon#read 5, iclass 39, count 2 2006.224.07:53:52.03#ibcon#about to read 6, iclass 39, count 2 2006.224.07:53:52.03#ibcon#read 6, iclass 39, count 2 2006.224.07:53:52.03#ibcon#end of sib2, iclass 39, count 2 2006.224.07:53:52.03#ibcon#*after write, iclass 39, count 2 2006.224.07:53:52.03#ibcon#*before return 0, iclass 39, count 2 2006.224.07:53:52.03#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.224.07:53:52.03#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.224.07:53:52.03#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.224.07:53:52.03#ibcon#ireg 7 cls_cnt 0 2006.224.07:53:52.03#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.224.07:53:52.15#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.224.07:53:52.15#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.224.07:53:52.15#ibcon#enter wrdev, iclass 39, count 0 2006.224.07:53:52.15#ibcon#first serial, iclass 39, count 0 2006.224.07:53:52.15#ibcon#enter sib2, iclass 39, count 0 2006.224.07:53:52.15#ibcon#flushed, iclass 39, count 0 2006.224.07:53:52.15#ibcon#about to write, iclass 39, count 0 2006.224.07:53:52.15#ibcon#wrote, iclass 39, count 0 2006.224.07:53:52.15#ibcon#about to read 3, iclass 39, count 0 2006.224.07:53:52.17#ibcon#read 3, iclass 39, count 0 2006.224.07:53:52.17#ibcon#about to read 4, iclass 39, count 0 2006.224.07:53:52.17#ibcon#read 4, iclass 39, count 0 2006.224.07:53:52.17#ibcon#about to read 5, iclass 39, count 0 2006.224.07:53:52.17#ibcon#read 5, iclass 39, count 0 2006.224.07:53:52.17#ibcon#about to read 6, iclass 39, count 0 2006.224.07:53:52.17#ibcon#read 6, iclass 39, count 0 2006.224.07:53:52.17#ibcon#end of sib2, iclass 39, count 0 2006.224.07:53:52.17#ibcon#*mode == 0, iclass 39, count 0 2006.224.07:53:52.17#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.224.07:53:52.17#ibcon#[27=USB\r\n] 2006.224.07:53:52.17#ibcon#*before write, iclass 39, count 0 2006.224.07:53:52.17#ibcon#enter sib2, iclass 39, count 0 2006.224.07:53:52.17#ibcon#flushed, iclass 39, count 0 2006.224.07:53:52.17#ibcon#about to write, iclass 39, count 0 2006.224.07:53:52.17#ibcon#wrote, iclass 39, count 0 2006.224.07:53:52.17#ibcon#about to read 3, iclass 39, count 0 2006.224.07:53:52.20#ibcon#read 3, iclass 39, count 0 2006.224.07:53:52.20#ibcon#about to read 4, iclass 39, count 0 2006.224.07:53:52.20#ibcon#read 4, iclass 39, count 0 2006.224.07:53:52.20#ibcon#about to read 5, iclass 39, count 0 2006.224.07:53:52.20#ibcon#read 5, iclass 39, count 0 2006.224.07:53:52.20#ibcon#about to read 6, iclass 39, count 0 2006.224.07:53:52.20#ibcon#read 6, iclass 39, count 0 2006.224.07:53:52.20#ibcon#end of sib2, iclass 39, count 0 2006.224.07:53:52.20#ibcon#*after write, iclass 39, count 0 2006.224.07:53:52.20#ibcon#*before return 0, iclass 39, count 0 2006.224.07:53:52.20#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.224.07:53:52.20#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.224.07:53:52.20#ibcon#about to clear, iclass 39 cls_cnt 0 2006.224.07:53:52.20#ibcon#cleared, iclass 39 cls_cnt 0 2006.224.07:53:52.20$vc4f8/vblo=6,752.99 2006.224.07:53:52.20#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.224.07:53:52.20#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.224.07:53:52.20#ibcon#ireg 17 cls_cnt 0 2006.224.07:53:52.20#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.224.07:53:52.20#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.224.07:53:52.20#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.224.07:53:52.20#ibcon#enter wrdev, iclass 3, count 0 2006.224.07:53:52.20#ibcon#first serial, iclass 3, count 0 2006.224.07:53:52.20#ibcon#enter sib2, iclass 3, count 0 2006.224.07:53:52.20#ibcon#flushed, iclass 3, count 0 2006.224.07:53:52.20#ibcon#about to write, iclass 3, count 0 2006.224.07:53:52.20#ibcon#wrote, iclass 3, count 0 2006.224.07:53:52.20#ibcon#about to read 3, iclass 3, count 0 2006.224.07:53:52.22#ibcon#read 3, iclass 3, count 0 2006.224.07:53:52.22#ibcon#about to read 4, iclass 3, count 0 2006.224.07:53:52.22#ibcon#read 4, iclass 3, count 0 2006.224.07:53:52.22#ibcon#about to read 5, iclass 3, count 0 2006.224.07:53:52.22#ibcon#read 5, iclass 3, count 0 2006.224.07:53:52.22#ibcon#about to read 6, iclass 3, count 0 2006.224.07:53:52.22#ibcon#read 6, iclass 3, count 0 2006.224.07:53:52.22#ibcon#end of sib2, iclass 3, count 0 2006.224.07:53:52.22#ibcon#*mode == 0, iclass 3, count 0 2006.224.07:53:52.22#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.224.07:53:52.22#ibcon#[28=FRQ=06,752.99\r\n] 2006.224.07:53:52.22#ibcon#*before write, iclass 3, count 0 2006.224.07:53:52.22#ibcon#enter sib2, iclass 3, count 0 2006.224.07:53:52.22#ibcon#flushed, iclass 3, count 0 2006.224.07:53:52.22#ibcon#about to write, iclass 3, count 0 2006.224.07:53:52.22#ibcon#wrote, iclass 3, count 0 2006.224.07:53:52.22#ibcon#about to read 3, iclass 3, count 0 2006.224.07:53:52.26#ibcon#read 3, iclass 3, count 0 2006.224.07:53:52.26#ibcon#about to read 4, iclass 3, count 0 2006.224.07:53:52.26#ibcon#read 4, iclass 3, count 0 2006.224.07:53:52.26#ibcon#about to read 5, iclass 3, count 0 2006.224.07:53:52.26#ibcon#read 5, iclass 3, count 0 2006.224.07:53:52.26#ibcon#about to read 6, iclass 3, count 0 2006.224.07:53:52.26#ibcon#read 6, iclass 3, count 0 2006.224.07:53:52.26#ibcon#end of sib2, iclass 3, count 0 2006.224.07:53:52.26#ibcon#*after write, iclass 3, count 0 2006.224.07:53:52.26#ibcon#*before return 0, iclass 3, count 0 2006.224.07:53:52.26#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.224.07:53:52.26#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.224.07:53:52.26#ibcon#about to clear, iclass 3 cls_cnt 0 2006.224.07:53:52.26#ibcon#cleared, iclass 3 cls_cnt 0 2006.224.07:53:52.26$vc4f8/vb=6,4 2006.224.07:53:52.26#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.224.07:53:52.26#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.224.07:53:52.26#ibcon#ireg 11 cls_cnt 2 2006.224.07:53:52.26#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.224.07:53:52.32#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.224.07:53:52.32#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.224.07:53:52.32#ibcon#enter wrdev, iclass 5, count 2 2006.224.07:53:52.32#ibcon#first serial, iclass 5, count 2 2006.224.07:53:52.32#ibcon#enter sib2, iclass 5, count 2 2006.224.07:53:52.32#ibcon#flushed, iclass 5, count 2 2006.224.07:53:52.32#ibcon#about to write, iclass 5, count 2 2006.224.07:53:52.32#ibcon#wrote, iclass 5, count 2 2006.224.07:53:52.32#ibcon#about to read 3, iclass 5, count 2 2006.224.07:53:52.34#ibcon#read 3, iclass 5, count 2 2006.224.07:53:52.34#ibcon#about to read 4, iclass 5, count 2 2006.224.07:53:52.34#ibcon#read 4, iclass 5, count 2 2006.224.07:53:52.34#ibcon#about to read 5, iclass 5, count 2 2006.224.07:53:52.34#ibcon#read 5, iclass 5, count 2 2006.224.07:53:52.34#ibcon#about to read 6, iclass 5, count 2 2006.224.07:53:52.34#ibcon#read 6, iclass 5, count 2 2006.224.07:53:52.34#ibcon#end of sib2, iclass 5, count 2 2006.224.07:53:52.34#ibcon#*mode == 0, iclass 5, count 2 2006.224.07:53:52.34#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.224.07:53:52.34#ibcon#[27=AT06-04\r\n] 2006.224.07:53:52.34#ibcon#*before write, iclass 5, count 2 2006.224.07:53:52.34#ibcon#enter sib2, iclass 5, count 2 2006.224.07:53:52.34#ibcon#flushed, iclass 5, count 2 2006.224.07:53:52.34#ibcon#about to write, iclass 5, count 2 2006.224.07:53:52.34#ibcon#wrote, iclass 5, count 2 2006.224.07:53:52.34#ibcon#about to read 3, iclass 5, count 2 2006.224.07:53:52.37#ibcon#read 3, iclass 5, count 2 2006.224.07:53:52.37#ibcon#about to read 4, iclass 5, count 2 2006.224.07:53:52.37#ibcon#read 4, iclass 5, count 2 2006.224.07:53:52.37#ibcon#about to read 5, iclass 5, count 2 2006.224.07:53:52.37#ibcon#read 5, iclass 5, count 2 2006.224.07:53:52.37#ibcon#about to read 6, iclass 5, count 2 2006.224.07:53:52.37#ibcon#read 6, iclass 5, count 2 2006.224.07:53:52.37#ibcon#end of sib2, iclass 5, count 2 2006.224.07:53:52.37#ibcon#*after write, iclass 5, count 2 2006.224.07:53:52.37#ibcon#*before return 0, iclass 5, count 2 2006.224.07:53:52.37#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.224.07:53:52.37#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.224.07:53:52.37#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.224.07:53:52.37#ibcon#ireg 7 cls_cnt 0 2006.224.07:53:52.37#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.224.07:53:52.49#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.224.07:53:52.49#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.224.07:53:52.49#ibcon#enter wrdev, iclass 5, count 0 2006.224.07:53:52.49#ibcon#first serial, iclass 5, count 0 2006.224.07:53:52.49#ibcon#enter sib2, iclass 5, count 0 2006.224.07:53:52.49#ibcon#flushed, iclass 5, count 0 2006.224.07:53:52.49#ibcon#about to write, iclass 5, count 0 2006.224.07:53:52.49#ibcon#wrote, iclass 5, count 0 2006.224.07:53:52.49#ibcon#about to read 3, iclass 5, count 0 2006.224.07:53:52.51#ibcon#read 3, iclass 5, count 0 2006.224.07:53:52.51#ibcon#about to read 4, iclass 5, count 0 2006.224.07:53:52.51#ibcon#read 4, iclass 5, count 0 2006.224.07:53:52.51#ibcon#about to read 5, iclass 5, count 0 2006.224.07:53:52.51#ibcon#read 5, iclass 5, count 0 2006.224.07:53:52.51#ibcon#about to read 6, iclass 5, count 0 2006.224.07:53:52.51#ibcon#read 6, iclass 5, count 0 2006.224.07:53:52.51#ibcon#end of sib2, iclass 5, count 0 2006.224.07:53:52.51#ibcon#*mode == 0, iclass 5, count 0 2006.224.07:53:52.51#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.224.07:53:52.51#ibcon#[27=USB\r\n] 2006.224.07:53:52.51#ibcon#*before write, iclass 5, count 0 2006.224.07:53:52.51#ibcon#enter sib2, iclass 5, count 0 2006.224.07:53:52.51#ibcon#flushed, iclass 5, count 0 2006.224.07:53:52.51#ibcon#about to write, iclass 5, count 0 2006.224.07:53:52.51#ibcon#wrote, iclass 5, count 0 2006.224.07:53:52.51#ibcon#about to read 3, iclass 5, count 0 2006.224.07:53:52.54#ibcon#read 3, iclass 5, count 0 2006.224.07:53:52.54#ibcon#about to read 4, iclass 5, count 0 2006.224.07:53:52.54#ibcon#read 4, iclass 5, count 0 2006.224.07:53:52.54#ibcon#about to read 5, iclass 5, count 0 2006.224.07:53:52.54#ibcon#read 5, iclass 5, count 0 2006.224.07:53:52.54#ibcon#about to read 6, iclass 5, count 0 2006.224.07:53:52.54#ibcon#read 6, iclass 5, count 0 2006.224.07:53:52.54#ibcon#end of sib2, iclass 5, count 0 2006.224.07:53:52.54#ibcon#*after write, iclass 5, count 0 2006.224.07:53:52.54#ibcon#*before return 0, iclass 5, count 0 2006.224.07:53:52.54#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.224.07:53:52.54#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.224.07:53:52.54#ibcon#about to clear, iclass 5 cls_cnt 0 2006.224.07:53:52.54#ibcon#cleared, iclass 5 cls_cnt 0 2006.224.07:53:52.54$vc4f8/vabw=wide 2006.224.07:53:52.54#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.224.07:53:52.54#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.224.07:53:52.54#ibcon#ireg 8 cls_cnt 0 2006.224.07:53:52.54#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.224.07:53:52.54#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.224.07:53:52.54#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.224.07:53:52.54#ibcon#enter wrdev, iclass 7, count 0 2006.224.07:53:52.54#ibcon#first serial, iclass 7, count 0 2006.224.07:53:52.54#ibcon#enter sib2, iclass 7, count 0 2006.224.07:53:52.54#ibcon#flushed, iclass 7, count 0 2006.224.07:53:52.54#ibcon#about to write, iclass 7, count 0 2006.224.07:53:52.54#ibcon#wrote, iclass 7, count 0 2006.224.07:53:52.54#ibcon#about to read 3, iclass 7, count 0 2006.224.07:53:52.56#ibcon#read 3, iclass 7, count 0 2006.224.07:53:52.56#ibcon#about to read 4, iclass 7, count 0 2006.224.07:53:52.56#ibcon#read 4, iclass 7, count 0 2006.224.07:53:52.56#ibcon#about to read 5, iclass 7, count 0 2006.224.07:53:52.56#ibcon#read 5, iclass 7, count 0 2006.224.07:53:52.56#ibcon#about to read 6, iclass 7, count 0 2006.224.07:53:52.56#ibcon#read 6, iclass 7, count 0 2006.224.07:53:52.56#ibcon#end of sib2, iclass 7, count 0 2006.224.07:53:52.56#ibcon#*mode == 0, iclass 7, count 0 2006.224.07:53:52.56#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.224.07:53:52.56#ibcon#[25=BW32\r\n] 2006.224.07:53:52.56#ibcon#*before write, iclass 7, count 0 2006.224.07:53:52.56#ibcon#enter sib2, iclass 7, count 0 2006.224.07:53:52.56#ibcon#flushed, iclass 7, count 0 2006.224.07:53:52.56#ibcon#about to write, iclass 7, count 0 2006.224.07:53:52.56#ibcon#wrote, iclass 7, count 0 2006.224.07:53:52.56#ibcon#about to read 3, iclass 7, count 0 2006.224.07:53:52.59#ibcon#read 3, iclass 7, count 0 2006.224.07:53:52.59#ibcon#about to read 4, iclass 7, count 0 2006.224.07:53:52.59#ibcon#read 4, iclass 7, count 0 2006.224.07:53:52.59#ibcon#about to read 5, iclass 7, count 0 2006.224.07:53:52.59#ibcon#read 5, iclass 7, count 0 2006.224.07:53:52.59#ibcon#about to read 6, iclass 7, count 0 2006.224.07:53:52.59#ibcon#read 6, iclass 7, count 0 2006.224.07:53:52.59#ibcon#end of sib2, iclass 7, count 0 2006.224.07:53:52.59#ibcon#*after write, iclass 7, count 0 2006.224.07:53:52.59#ibcon#*before return 0, iclass 7, count 0 2006.224.07:53:52.59#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.224.07:53:52.59#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.224.07:53:52.59#ibcon#about to clear, iclass 7 cls_cnt 0 2006.224.07:53:52.59#ibcon#cleared, iclass 7 cls_cnt 0 2006.224.07:53:52.59$vc4f8/vbbw=wide 2006.224.07:53:52.59#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.224.07:53:52.59#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.224.07:53:52.59#ibcon#ireg 8 cls_cnt 0 2006.224.07:53:52.59#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.224.07:53:52.66#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.224.07:53:52.66#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.224.07:53:52.66#ibcon#enter wrdev, iclass 11, count 0 2006.224.07:53:52.66#ibcon#first serial, iclass 11, count 0 2006.224.07:53:52.66#ibcon#enter sib2, iclass 11, count 0 2006.224.07:53:52.66#ibcon#flushed, iclass 11, count 0 2006.224.07:53:52.66#ibcon#about to write, iclass 11, count 0 2006.224.07:53:52.66#ibcon#wrote, iclass 11, count 0 2006.224.07:53:52.66#ibcon#about to read 3, iclass 11, count 0 2006.224.07:53:52.68#ibcon#read 3, iclass 11, count 0 2006.224.07:53:52.68#ibcon#about to read 4, iclass 11, count 0 2006.224.07:53:52.68#ibcon#read 4, iclass 11, count 0 2006.224.07:53:52.68#ibcon#about to read 5, iclass 11, count 0 2006.224.07:53:52.68#ibcon#read 5, iclass 11, count 0 2006.224.07:53:52.68#ibcon#about to read 6, iclass 11, count 0 2006.224.07:53:52.68#ibcon#read 6, iclass 11, count 0 2006.224.07:53:52.68#ibcon#end of sib2, iclass 11, count 0 2006.224.07:53:52.68#ibcon#*mode == 0, iclass 11, count 0 2006.224.07:53:52.68#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.224.07:53:52.68#ibcon#[27=BW32\r\n] 2006.224.07:53:52.68#ibcon#*before write, iclass 11, count 0 2006.224.07:53:52.68#ibcon#enter sib2, iclass 11, count 0 2006.224.07:53:52.68#ibcon#flushed, iclass 11, count 0 2006.224.07:53:52.68#ibcon#about to write, iclass 11, count 0 2006.224.07:53:52.68#ibcon#wrote, iclass 11, count 0 2006.224.07:53:52.68#ibcon#about to read 3, iclass 11, count 0 2006.224.07:53:52.71#ibcon#read 3, iclass 11, count 0 2006.224.07:53:52.71#ibcon#about to read 4, iclass 11, count 0 2006.224.07:53:52.71#ibcon#read 4, iclass 11, count 0 2006.224.07:53:52.71#ibcon#about to read 5, iclass 11, count 0 2006.224.07:53:52.71#ibcon#read 5, iclass 11, count 0 2006.224.07:53:52.71#ibcon#about to read 6, iclass 11, count 0 2006.224.07:53:52.71#ibcon#read 6, iclass 11, count 0 2006.224.07:53:52.71#ibcon#end of sib2, iclass 11, count 0 2006.224.07:53:52.71#ibcon#*after write, iclass 11, count 0 2006.224.07:53:52.71#ibcon#*before return 0, iclass 11, count 0 2006.224.07:53:52.71#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.224.07:53:52.71#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.224.07:53:52.71#ibcon#about to clear, iclass 11 cls_cnt 0 2006.224.07:53:52.71#ibcon#cleared, iclass 11 cls_cnt 0 2006.224.07:53:52.71$4f8m12a/ifd4f 2006.224.07:53:52.71$ifd4f/lo= 2006.224.07:53:52.71$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.224.07:53:52.71$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.224.07:53:52.71$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.224.07:53:52.71$ifd4f/patch= 2006.224.07:53:52.71$ifd4f/patch=lo1,a1,a2,a3,a4 2006.224.07:53:52.71$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.224.07:53:52.71$ifd4f/patch=lo3,a5,a6,a7,a8 2006.224.07:53:52.71$4f8m12a/"form=m,16.000,1:2 2006.224.07:53:52.71$4f8m12a/"tpicd 2006.224.07:53:52.71$4f8m12a/echo=off 2006.224.07:53:52.71$4f8m12a/xlog=off 2006.224.07:53:52.71:!2006.224.07:55:20 2006.224.07:54:22.13#trakl#Source acquired 2006.224.07:54:23.13#flagr#flagr/antenna,acquired 2006.224.07:55:20.00:preob 2006.224.07:55:21.13/onsource/TRACKING 2006.224.07:55:21.13:!2006.224.07:55:30 2006.224.07:55:30.00:data_valid=on 2006.224.07:55:30.00:midob 2006.224.07:55:30.14/onsource/TRACKING 2006.224.07:55:30.14/wx/23.65,1003.9,100 2006.224.07:55:30.23/cable/+6.4326E-03 2006.224.07:55:31.32/va/01,08,usb,yes,39,41 2006.224.07:55:31.32/va/02,07,usb,yes,39,41 2006.224.07:55:31.32/va/03,06,usb,yes,42,42 2006.224.07:55:31.32/va/04,07,usb,yes,41,44 2006.224.07:55:31.32/va/05,07,usb,yes,49,51 2006.224.07:55:31.32/va/06,06,usb,yes,48,48 2006.224.07:55:31.32/va/07,06,usb,yes,49,48 2006.224.07:55:31.32/va/08,07,usb,yes,46,46 2006.224.07:55:31.55/valo/01,532.99,yes,locked 2006.224.07:55:31.55/valo/02,572.99,yes,locked 2006.224.07:55:31.55/valo/03,672.99,yes,locked 2006.224.07:55:31.55/valo/04,832.99,yes,locked 2006.224.07:55:31.55/valo/05,652.99,yes,locked 2006.224.07:55:31.55/valo/06,772.99,yes,locked 2006.224.07:55:31.55/valo/07,832.99,yes,locked 2006.224.07:55:31.55/valo/08,852.99,yes,locked 2006.224.07:55:32.64/vb/01,04,usb,yes,32,31 2006.224.07:55:32.64/vb/02,04,usb,yes,34,36 2006.224.07:55:32.64/vb/03,04,usb,yes,30,34 2006.224.07:55:32.64/vb/04,04,usb,yes,31,31 2006.224.07:55:32.64/vb/05,04,usb,yes,30,34 2006.224.07:55:32.64/vb/06,04,usb,yes,31,34 2006.224.07:55:32.64/vb/07,04,usb,yes,33,33 2006.224.07:55:32.64/vb/08,04,usb,yes,30,34 2006.224.07:55:32.88/vblo/01,632.99,yes,locked 2006.224.07:55:32.88/vblo/02,640.99,yes,locked 2006.224.07:55:32.88/vblo/03,656.99,yes,locked 2006.224.07:55:32.88/vblo/04,712.99,yes,locked 2006.224.07:55:32.88/vblo/05,744.99,yes,locked 2006.224.07:55:32.88/vblo/06,752.99,yes,locked 2006.224.07:55:32.88/vblo/07,734.99,yes,locked 2006.224.07:55:32.88/vblo/08,744.99,yes,locked 2006.224.07:55:33.03/vabw/8 2006.224.07:55:33.18/vbbw/8 2006.224.07:55:33.27/xfe/off,on,15.0 2006.224.07:55:33.65/ifatt/23,28,28,28 2006.224.07:55:34.07/fmout-gps/S +4.31E-07 2006.224.07:55:34.11:!2006.224.07:56:30 2006.224.07:56:30.00:data_valid=off 2006.224.07:56:30.00:postob 2006.224.07:56:30.05/cable/+6.4349E-03 2006.224.07:56:30.05/wx/23.64,1004.0,100 2006.224.07:56:31.07/fmout-gps/S +4.32E-07 2006.224.07:56:31.07:scan_name=224-0759,k06224,60 2006.224.07:56:31.07:source=1417+385,141946.61,382148.5,2000.0,ccw 2006.224.07:56:31.14#flagr#flagr/antenna,new-source 2006.224.07:56:32.14:checkk5 2006.224.07:56:32.51/chk_autoobs//k5ts1/ autoobs is running! 2006.224.07:56:32.89/chk_autoobs//k5ts2/ autoobs is running! 2006.224.07:56:33.27/chk_autoobs//k5ts3/ autoobs is running! 2006.224.07:56:33.64/chk_autoobs//k5ts4/ autoobs is running! 2006.224.07:56:34.00/chk_obsdata//k5ts1/T2240755??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.07:56:34.36/chk_obsdata//k5ts2/T2240755??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.07:56:34.72/chk_obsdata//k5ts3/T2240755??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.07:56:35.09/chk_obsdata//k5ts4/T2240755??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.07:56:35.77/k5log//k5ts1_log_newline 2006.224.07:56:36.46/k5log//k5ts2_log_newline 2006.224.07:56:37.14/k5log//k5ts3_log_newline 2006.224.07:56:37.83/k5log//k5ts4_log_newline 2006.224.07:56:37.85/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.224.07:56:37.85:4f8m12a=2 2006.224.07:56:37.85$4f8m12a/echo=on 2006.224.07:56:37.85$4f8m12a/pcalon 2006.224.07:56:37.85$pcalon/"no phase cal control is implemented here 2006.224.07:56:37.85$4f8m12a/"tpicd=stop 2006.224.07:56:37.85$4f8m12a/vc4f8 2006.224.07:56:37.85$vc4f8/valo=1,532.99 2006.224.07:56:37.85#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.224.07:56:37.85#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.224.07:56:37.85#ibcon#ireg 17 cls_cnt 0 2006.224.07:56:37.85#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.224.07:56:37.85#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.224.07:56:37.85#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.224.07:56:37.85#ibcon#enter wrdev, iclass 4, count 0 2006.224.07:56:37.85#ibcon#first serial, iclass 4, count 0 2006.224.07:56:37.85#ibcon#enter sib2, iclass 4, count 0 2006.224.07:56:37.85#ibcon#flushed, iclass 4, count 0 2006.224.07:56:37.85#ibcon#about to write, iclass 4, count 0 2006.224.07:56:37.85#ibcon#wrote, iclass 4, count 0 2006.224.07:56:37.85#ibcon#about to read 3, iclass 4, count 0 2006.224.07:56:37.87#ibcon#read 3, iclass 4, count 0 2006.224.07:56:37.87#ibcon#about to read 4, iclass 4, count 0 2006.224.07:56:37.87#ibcon#read 4, iclass 4, count 0 2006.224.07:56:37.87#ibcon#about to read 5, iclass 4, count 0 2006.224.07:56:37.87#ibcon#read 5, iclass 4, count 0 2006.224.07:56:37.87#ibcon#about to read 6, iclass 4, count 0 2006.224.07:56:37.87#ibcon#read 6, iclass 4, count 0 2006.224.07:56:37.87#ibcon#end of sib2, iclass 4, count 0 2006.224.07:56:37.87#ibcon#*mode == 0, iclass 4, count 0 2006.224.07:56:37.87#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.224.07:56:37.87#ibcon#[26=FRQ=01,532.99\r\n] 2006.224.07:56:37.87#ibcon#*before write, iclass 4, count 0 2006.224.07:56:37.87#ibcon#enter sib2, iclass 4, count 0 2006.224.07:56:37.87#ibcon#flushed, iclass 4, count 0 2006.224.07:56:37.87#ibcon#about to write, iclass 4, count 0 2006.224.07:56:37.87#ibcon#wrote, iclass 4, count 0 2006.224.07:56:37.87#ibcon#about to read 3, iclass 4, count 0 2006.224.07:56:37.92#ibcon#read 3, iclass 4, count 0 2006.224.07:56:37.92#ibcon#about to read 4, iclass 4, count 0 2006.224.07:56:37.92#ibcon#read 4, iclass 4, count 0 2006.224.07:56:37.92#ibcon#about to read 5, iclass 4, count 0 2006.224.07:56:37.92#ibcon#read 5, iclass 4, count 0 2006.224.07:56:37.92#ibcon#about to read 6, iclass 4, count 0 2006.224.07:56:37.92#ibcon#read 6, iclass 4, count 0 2006.224.07:56:37.92#ibcon#end of sib2, iclass 4, count 0 2006.224.07:56:37.92#ibcon#*after write, iclass 4, count 0 2006.224.07:56:37.92#ibcon#*before return 0, iclass 4, count 0 2006.224.07:56:37.92#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.224.07:56:37.92#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.224.07:56:37.92#ibcon#about to clear, iclass 4 cls_cnt 0 2006.224.07:56:37.92#ibcon#cleared, iclass 4 cls_cnt 0 2006.224.07:56:37.92$vc4f8/va=1,8 2006.224.07:56:37.92#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.224.07:56:37.92#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.224.07:56:37.92#ibcon#ireg 11 cls_cnt 2 2006.224.07:56:37.92#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.224.07:56:37.92#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.224.07:56:37.92#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.224.07:56:37.92#ibcon#enter wrdev, iclass 6, count 2 2006.224.07:56:37.92#ibcon#first serial, iclass 6, count 2 2006.224.07:56:37.92#ibcon#enter sib2, iclass 6, count 2 2006.224.07:56:37.92#ibcon#flushed, iclass 6, count 2 2006.224.07:56:37.92#ibcon#about to write, iclass 6, count 2 2006.224.07:56:37.92#ibcon#wrote, iclass 6, count 2 2006.224.07:56:37.92#ibcon#about to read 3, iclass 6, count 2 2006.224.07:56:37.94#ibcon#read 3, iclass 6, count 2 2006.224.07:56:37.94#ibcon#about to read 4, iclass 6, count 2 2006.224.07:56:37.94#ibcon#read 4, iclass 6, count 2 2006.224.07:56:37.94#ibcon#about to read 5, iclass 6, count 2 2006.224.07:56:37.94#ibcon#read 5, iclass 6, count 2 2006.224.07:56:37.94#ibcon#about to read 6, iclass 6, count 2 2006.224.07:56:37.94#ibcon#read 6, iclass 6, count 2 2006.224.07:56:37.94#ibcon#end of sib2, iclass 6, count 2 2006.224.07:56:37.94#ibcon#*mode == 0, iclass 6, count 2 2006.224.07:56:37.94#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.224.07:56:37.94#ibcon#[25=AT01-08\r\n] 2006.224.07:56:37.94#ibcon#*before write, iclass 6, count 2 2006.224.07:56:37.94#ibcon#enter sib2, iclass 6, count 2 2006.224.07:56:37.94#ibcon#flushed, iclass 6, count 2 2006.224.07:56:37.94#ibcon#about to write, iclass 6, count 2 2006.224.07:56:37.94#ibcon#wrote, iclass 6, count 2 2006.224.07:56:37.94#ibcon#about to read 3, iclass 6, count 2 2006.224.07:56:37.98#ibcon#read 3, iclass 6, count 2 2006.224.07:56:37.98#ibcon#about to read 4, iclass 6, count 2 2006.224.07:56:37.98#ibcon#read 4, iclass 6, count 2 2006.224.07:56:37.98#ibcon#about to read 5, iclass 6, count 2 2006.224.07:56:37.98#ibcon#read 5, iclass 6, count 2 2006.224.07:56:37.98#ibcon#about to read 6, iclass 6, count 2 2006.224.07:56:37.98#ibcon#read 6, iclass 6, count 2 2006.224.07:56:37.98#ibcon#end of sib2, iclass 6, count 2 2006.224.07:56:37.98#ibcon#*after write, iclass 6, count 2 2006.224.07:56:37.98#ibcon#*before return 0, iclass 6, count 2 2006.224.07:56:37.98#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.224.07:56:37.98#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.224.07:56:37.98#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.224.07:56:37.98#ibcon#ireg 7 cls_cnt 0 2006.224.07:56:37.98#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.224.07:56:38.09#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.224.07:56:38.09#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.224.07:56:38.09#ibcon#enter wrdev, iclass 6, count 0 2006.224.07:56:38.09#ibcon#first serial, iclass 6, count 0 2006.224.07:56:38.09#ibcon#enter sib2, iclass 6, count 0 2006.224.07:56:38.09#ibcon#flushed, iclass 6, count 0 2006.224.07:56:38.09#ibcon#about to write, iclass 6, count 0 2006.224.07:56:38.09#ibcon#wrote, iclass 6, count 0 2006.224.07:56:38.09#ibcon#about to read 3, iclass 6, count 0 2006.224.07:56:38.11#ibcon#read 3, iclass 6, count 0 2006.224.07:56:38.11#ibcon#about to read 4, iclass 6, count 0 2006.224.07:56:38.11#ibcon#read 4, iclass 6, count 0 2006.224.07:56:38.11#ibcon#about to read 5, iclass 6, count 0 2006.224.07:56:38.11#ibcon#read 5, iclass 6, count 0 2006.224.07:56:38.11#ibcon#about to read 6, iclass 6, count 0 2006.224.07:56:38.11#ibcon#read 6, iclass 6, count 0 2006.224.07:56:38.11#ibcon#end of sib2, iclass 6, count 0 2006.224.07:56:38.11#ibcon#*mode == 0, iclass 6, count 0 2006.224.07:56:38.11#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.224.07:56:38.11#ibcon#[25=USB\r\n] 2006.224.07:56:38.11#ibcon#*before write, iclass 6, count 0 2006.224.07:56:38.11#ibcon#enter sib2, iclass 6, count 0 2006.224.07:56:38.11#ibcon#flushed, iclass 6, count 0 2006.224.07:56:38.11#ibcon#about to write, iclass 6, count 0 2006.224.07:56:38.11#ibcon#wrote, iclass 6, count 0 2006.224.07:56:38.11#ibcon#about to read 3, iclass 6, count 0 2006.224.07:56:38.14#ibcon#read 3, iclass 6, count 0 2006.224.07:56:38.14#ibcon#about to read 4, iclass 6, count 0 2006.224.07:56:38.14#ibcon#read 4, iclass 6, count 0 2006.224.07:56:38.14#ibcon#about to read 5, iclass 6, count 0 2006.224.07:56:38.14#ibcon#read 5, iclass 6, count 0 2006.224.07:56:38.14#ibcon#about to read 6, iclass 6, count 0 2006.224.07:56:38.14#ibcon#read 6, iclass 6, count 0 2006.224.07:56:38.14#ibcon#end of sib2, iclass 6, count 0 2006.224.07:56:38.14#ibcon#*after write, iclass 6, count 0 2006.224.07:56:38.14#ibcon#*before return 0, iclass 6, count 0 2006.224.07:56:38.14#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.224.07:56:38.14#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.224.07:56:38.14#ibcon#about to clear, iclass 6 cls_cnt 0 2006.224.07:56:38.14#ibcon#cleared, iclass 6 cls_cnt 0 2006.224.07:56:38.14$vc4f8/valo=2,572.99 2006.224.07:56:38.14#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.224.07:56:38.14#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.224.07:56:38.14#ibcon#ireg 17 cls_cnt 0 2006.224.07:56:38.14#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.224.07:56:38.14#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.224.07:56:38.14#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.224.07:56:38.14#ibcon#enter wrdev, iclass 10, count 0 2006.224.07:56:38.14#ibcon#first serial, iclass 10, count 0 2006.224.07:56:38.14#ibcon#enter sib2, iclass 10, count 0 2006.224.07:56:38.14#ibcon#flushed, iclass 10, count 0 2006.224.07:56:38.14#ibcon#about to write, iclass 10, count 0 2006.224.07:56:38.14#ibcon#wrote, iclass 10, count 0 2006.224.07:56:38.14#ibcon#about to read 3, iclass 10, count 0 2006.224.07:56:38.17#ibcon#read 3, iclass 10, count 0 2006.224.07:56:38.17#ibcon#about to read 4, iclass 10, count 0 2006.224.07:56:38.17#ibcon#read 4, iclass 10, count 0 2006.224.07:56:38.17#ibcon#about to read 5, iclass 10, count 0 2006.224.07:56:38.17#ibcon#read 5, iclass 10, count 0 2006.224.07:56:38.17#ibcon#about to read 6, iclass 10, count 0 2006.224.07:56:38.17#ibcon#read 6, iclass 10, count 0 2006.224.07:56:38.17#ibcon#end of sib2, iclass 10, count 0 2006.224.07:56:38.17#ibcon#*mode == 0, iclass 10, count 0 2006.224.07:56:38.17#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.224.07:56:38.17#ibcon#[26=FRQ=02,572.99\r\n] 2006.224.07:56:38.17#ibcon#*before write, iclass 10, count 0 2006.224.07:56:38.17#ibcon#enter sib2, iclass 10, count 0 2006.224.07:56:38.17#ibcon#flushed, iclass 10, count 0 2006.224.07:56:38.17#ibcon#about to write, iclass 10, count 0 2006.224.07:56:38.17#ibcon#wrote, iclass 10, count 0 2006.224.07:56:38.17#ibcon#about to read 3, iclass 10, count 0 2006.224.07:56:38.21#ibcon#read 3, iclass 10, count 0 2006.224.07:56:38.21#ibcon#about to read 4, iclass 10, count 0 2006.224.07:56:38.21#ibcon#read 4, iclass 10, count 0 2006.224.07:56:38.21#ibcon#about to read 5, iclass 10, count 0 2006.224.07:56:38.21#ibcon#read 5, iclass 10, count 0 2006.224.07:56:38.21#ibcon#about to read 6, iclass 10, count 0 2006.224.07:56:38.21#ibcon#read 6, iclass 10, count 0 2006.224.07:56:38.21#ibcon#end of sib2, iclass 10, count 0 2006.224.07:56:38.21#ibcon#*after write, iclass 10, count 0 2006.224.07:56:38.21#ibcon#*before return 0, iclass 10, count 0 2006.224.07:56:38.21#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.224.07:56:38.21#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.224.07:56:38.21#ibcon#about to clear, iclass 10 cls_cnt 0 2006.224.07:56:38.21#ibcon#cleared, iclass 10 cls_cnt 0 2006.224.07:56:38.21$vc4f8/va=2,7 2006.224.07:56:38.21#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.224.07:56:38.21#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.224.07:56:38.21#ibcon#ireg 11 cls_cnt 2 2006.224.07:56:38.21#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.224.07:56:38.26#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.224.07:56:38.26#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.224.07:56:38.26#ibcon#enter wrdev, iclass 12, count 2 2006.224.07:56:38.26#ibcon#first serial, iclass 12, count 2 2006.224.07:56:38.26#ibcon#enter sib2, iclass 12, count 2 2006.224.07:56:38.26#ibcon#flushed, iclass 12, count 2 2006.224.07:56:38.26#ibcon#about to write, iclass 12, count 2 2006.224.07:56:38.26#ibcon#wrote, iclass 12, count 2 2006.224.07:56:38.26#ibcon#about to read 3, iclass 12, count 2 2006.224.07:56:38.28#ibcon#read 3, iclass 12, count 2 2006.224.07:56:38.28#ibcon#about to read 4, iclass 12, count 2 2006.224.07:56:38.28#ibcon#read 4, iclass 12, count 2 2006.224.07:56:38.28#ibcon#about to read 5, iclass 12, count 2 2006.224.07:56:38.28#ibcon#read 5, iclass 12, count 2 2006.224.07:56:38.28#ibcon#about to read 6, iclass 12, count 2 2006.224.07:56:38.28#ibcon#read 6, iclass 12, count 2 2006.224.07:56:38.28#ibcon#end of sib2, iclass 12, count 2 2006.224.07:56:38.28#ibcon#*mode == 0, iclass 12, count 2 2006.224.07:56:38.28#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.224.07:56:38.28#ibcon#[25=AT02-07\r\n] 2006.224.07:56:38.28#ibcon#*before write, iclass 12, count 2 2006.224.07:56:38.28#ibcon#enter sib2, iclass 12, count 2 2006.224.07:56:38.28#ibcon#flushed, iclass 12, count 2 2006.224.07:56:38.28#ibcon#about to write, iclass 12, count 2 2006.224.07:56:38.28#ibcon#wrote, iclass 12, count 2 2006.224.07:56:38.28#ibcon#about to read 3, iclass 12, count 2 2006.224.07:56:38.31#ibcon#read 3, iclass 12, count 2 2006.224.07:56:38.31#ibcon#about to read 4, iclass 12, count 2 2006.224.07:56:38.31#ibcon#read 4, iclass 12, count 2 2006.224.07:56:38.31#ibcon#about to read 5, iclass 12, count 2 2006.224.07:56:38.31#ibcon#read 5, iclass 12, count 2 2006.224.07:56:38.31#ibcon#about to read 6, iclass 12, count 2 2006.224.07:56:38.31#ibcon#read 6, iclass 12, count 2 2006.224.07:56:38.31#ibcon#end of sib2, iclass 12, count 2 2006.224.07:56:38.31#ibcon#*after write, iclass 12, count 2 2006.224.07:56:38.31#ibcon#*before return 0, iclass 12, count 2 2006.224.07:56:38.31#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.224.07:56:38.31#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.224.07:56:38.31#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.224.07:56:38.31#ibcon#ireg 7 cls_cnt 0 2006.224.07:56:38.31#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.224.07:56:38.43#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.224.07:56:38.43#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.224.07:56:38.43#ibcon#enter wrdev, iclass 12, count 0 2006.224.07:56:38.43#ibcon#first serial, iclass 12, count 0 2006.224.07:56:38.43#ibcon#enter sib2, iclass 12, count 0 2006.224.07:56:38.43#ibcon#flushed, iclass 12, count 0 2006.224.07:56:38.43#ibcon#about to write, iclass 12, count 0 2006.224.07:56:38.43#ibcon#wrote, iclass 12, count 0 2006.224.07:56:38.43#ibcon#about to read 3, iclass 12, count 0 2006.224.07:56:38.45#ibcon#read 3, iclass 12, count 0 2006.224.07:56:38.45#ibcon#about to read 4, iclass 12, count 0 2006.224.07:56:38.45#ibcon#read 4, iclass 12, count 0 2006.224.07:56:38.45#ibcon#about to read 5, iclass 12, count 0 2006.224.07:56:38.45#ibcon#read 5, iclass 12, count 0 2006.224.07:56:38.45#ibcon#about to read 6, iclass 12, count 0 2006.224.07:56:38.45#ibcon#read 6, iclass 12, count 0 2006.224.07:56:38.45#ibcon#end of sib2, iclass 12, count 0 2006.224.07:56:38.45#ibcon#*mode == 0, iclass 12, count 0 2006.224.07:56:38.45#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.224.07:56:38.45#ibcon#[25=USB\r\n] 2006.224.07:56:38.45#ibcon#*before write, iclass 12, count 0 2006.224.07:56:38.45#ibcon#enter sib2, iclass 12, count 0 2006.224.07:56:38.45#ibcon#flushed, iclass 12, count 0 2006.224.07:56:38.45#ibcon#about to write, iclass 12, count 0 2006.224.07:56:38.45#ibcon#wrote, iclass 12, count 0 2006.224.07:56:38.45#ibcon#about to read 3, iclass 12, count 0 2006.224.07:56:38.48#ibcon#read 3, iclass 12, count 0 2006.224.07:56:38.48#ibcon#about to read 4, iclass 12, count 0 2006.224.07:56:38.48#ibcon#read 4, iclass 12, count 0 2006.224.07:56:38.48#ibcon#about to read 5, iclass 12, count 0 2006.224.07:56:38.48#ibcon#read 5, iclass 12, count 0 2006.224.07:56:38.48#ibcon#about to read 6, iclass 12, count 0 2006.224.07:56:38.48#ibcon#read 6, iclass 12, count 0 2006.224.07:56:38.48#ibcon#end of sib2, iclass 12, count 0 2006.224.07:56:38.48#ibcon#*after write, iclass 12, count 0 2006.224.07:56:38.48#ibcon#*before return 0, iclass 12, count 0 2006.224.07:56:38.48#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.224.07:56:38.48#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.224.07:56:38.48#ibcon#about to clear, iclass 12 cls_cnt 0 2006.224.07:56:38.48#ibcon#cleared, iclass 12 cls_cnt 0 2006.224.07:56:38.48$vc4f8/valo=3,672.99 2006.224.07:56:38.48#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.224.07:56:38.48#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.224.07:56:38.48#ibcon#ireg 17 cls_cnt 0 2006.224.07:56:38.48#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.224.07:56:38.48#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.224.07:56:38.48#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.224.07:56:38.48#ibcon#enter wrdev, iclass 14, count 0 2006.224.07:56:38.48#ibcon#first serial, iclass 14, count 0 2006.224.07:56:38.48#ibcon#enter sib2, iclass 14, count 0 2006.224.07:56:38.48#ibcon#flushed, iclass 14, count 0 2006.224.07:56:38.48#ibcon#about to write, iclass 14, count 0 2006.224.07:56:38.48#ibcon#wrote, iclass 14, count 0 2006.224.07:56:38.48#ibcon#about to read 3, iclass 14, count 0 2006.224.07:56:38.51#ibcon#read 3, iclass 14, count 0 2006.224.07:56:38.51#ibcon#about to read 4, iclass 14, count 0 2006.224.07:56:38.51#ibcon#read 4, iclass 14, count 0 2006.224.07:56:38.51#ibcon#about to read 5, iclass 14, count 0 2006.224.07:56:38.51#ibcon#read 5, iclass 14, count 0 2006.224.07:56:38.51#ibcon#about to read 6, iclass 14, count 0 2006.224.07:56:38.51#ibcon#read 6, iclass 14, count 0 2006.224.07:56:38.51#ibcon#end of sib2, iclass 14, count 0 2006.224.07:56:38.51#ibcon#*mode == 0, iclass 14, count 0 2006.224.07:56:38.51#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.224.07:56:38.51#ibcon#[26=FRQ=03,672.99\r\n] 2006.224.07:56:38.51#ibcon#*before write, iclass 14, count 0 2006.224.07:56:38.51#ibcon#enter sib2, iclass 14, count 0 2006.224.07:56:38.51#ibcon#flushed, iclass 14, count 0 2006.224.07:56:38.51#ibcon#about to write, iclass 14, count 0 2006.224.07:56:38.51#ibcon#wrote, iclass 14, count 0 2006.224.07:56:38.51#ibcon#about to read 3, iclass 14, count 0 2006.224.07:56:38.55#ibcon#read 3, iclass 14, count 0 2006.224.07:56:38.55#ibcon#about to read 4, iclass 14, count 0 2006.224.07:56:38.55#ibcon#read 4, iclass 14, count 0 2006.224.07:56:38.55#ibcon#about to read 5, iclass 14, count 0 2006.224.07:56:38.55#ibcon#read 5, iclass 14, count 0 2006.224.07:56:38.55#ibcon#about to read 6, iclass 14, count 0 2006.224.07:56:38.55#ibcon#read 6, iclass 14, count 0 2006.224.07:56:38.55#ibcon#end of sib2, iclass 14, count 0 2006.224.07:56:38.55#ibcon#*after write, iclass 14, count 0 2006.224.07:56:38.55#ibcon#*before return 0, iclass 14, count 0 2006.224.07:56:38.55#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.224.07:56:38.55#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.224.07:56:38.55#ibcon#about to clear, iclass 14 cls_cnt 0 2006.224.07:56:38.55#ibcon#cleared, iclass 14 cls_cnt 0 2006.224.07:56:38.55$vc4f8/va=3,6 2006.224.07:56:38.55#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.224.07:56:38.55#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.224.07:56:38.55#ibcon#ireg 11 cls_cnt 2 2006.224.07:56:38.55#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.224.07:56:38.60#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.224.07:56:38.60#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.224.07:56:38.60#ibcon#enter wrdev, iclass 16, count 2 2006.224.07:56:38.60#ibcon#first serial, iclass 16, count 2 2006.224.07:56:38.60#ibcon#enter sib2, iclass 16, count 2 2006.224.07:56:38.60#ibcon#flushed, iclass 16, count 2 2006.224.07:56:38.60#ibcon#about to write, iclass 16, count 2 2006.224.07:56:38.60#ibcon#wrote, iclass 16, count 2 2006.224.07:56:38.60#ibcon#about to read 3, iclass 16, count 2 2006.224.07:56:38.62#ibcon#read 3, iclass 16, count 2 2006.224.07:56:38.62#ibcon#about to read 4, iclass 16, count 2 2006.224.07:56:38.62#ibcon#read 4, iclass 16, count 2 2006.224.07:56:38.62#ibcon#about to read 5, iclass 16, count 2 2006.224.07:56:38.62#ibcon#read 5, iclass 16, count 2 2006.224.07:56:38.62#ibcon#about to read 6, iclass 16, count 2 2006.224.07:56:38.62#ibcon#read 6, iclass 16, count 2 2006.224.07:56:38.62#ibcon#end of sib2, iclass 16, count 2 2006.224.07:56:38.62#ibcon#*mode == 0, iclass 16, count 2 2006.224.07:56:38.62#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.224.07:56:38.62#ibcon#[25=AT03-06\r\n] 2006.224.07:56:38.62#ibcon#*before write, iclass 16, count 2 2006.224.07:56:38.62#ibcon#enter sib2, iclass 16, count 2 2006.224.07:56:38.62#ibcon#flushed, iclass 16, count 2 2006.224.07:56:38.62#ibcon#about to write, iclass 16, count 2 2006.224.07:56:38.62#ibcon#wrote, iclass 16, count 2 2006.224.07:56:38.62#ibcon#about to read 3, iclass 16, count 2 2006.224.07:56:38.65#ibcon#read 3, iclass 16, count 2 2006.224.07:56:38.65#ibcon#about to read 4, iclass 16, count 2 2006.224.07:56:38.65#ibcon#read 4, iclass 16, count 2 2006.224.07:56:38.65#ibcon#about to read 5, iclass 16, count 2 2006.224.07:56:38.65#ibcon#read 5, iclass 16, count 2 2006.224.07:56:38.65#ibcon#about to read 6, iclass 16, count 2 2006.224.07:56:38.65#ibcon#read 6, iclass 16, count 2 2006.224.07:56:38.65#ibcon#end of sib2, iclass 16, count 2 2006.224.07:56:38.65#ibcon#*after write, iclass 16, count 2 2006.224.07:56:38.65#ibcon#*before return 0, iclass 16, count 2 2006.224.07:56:38.65#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.224.07:56:38.65#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.224.07:56:38.65#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.224.07:56:38.65#ibcon#ireg 7 cls_cnt 0 2006.224.07:56:38.65#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.224.07:56:38.77#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.224.07:56:38.77#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.224.07:56:38.77#ibcon#enter wrdev, iclass 16, count 0 2006.224.07:56:38.77#ibcon#first serial, iclass 16, count 0 2006.224.07:56:38.77#ibcon#enter sib2, iclass 16, count 0 2006.224.07:56:38.77#ibcon#flushed, iclass 16, count 0 2006.224.07:56:38.77#ibcon#about to write, iclass 16, count 0 2006.224.07:56:38.77#ibcon#wrote, iclass 16, count 0 2006.224.07:56:38.77#ibcon#about to read 3, iclass 16, count 0 2006.224.07:56:38.79#ibcon#read 3, iclass 16, count 0 2006.224.07:56:38.79#ibcon#about to read 4, iclass 16, count 0 2006.224.07:56:38.79#ibcon#read 4, iclass 16, count 0 2006.224.07:56:38.79#ibcon#about to read 5, iclass 16, count 0 2006.224.07:56:38.79#ibcon#read 5, iclass 16, count 0 2006.224.07:56:38.79#ibcon#about to read 6, iclass 16, count 0 2006.224.07:56:38.79#ibcon#read 6, iclass 16, count 0 2006.224.07:56:38.79#ibcon#end of sib2, iclass 16, count 0 2006.224.07:56:38.79#ibcon#*mode == 0, iclass 16, count 0 2006.224.07:56:38.79#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.224.07:56:38.79#ibcon#[25=USB\r\n] 2006.224.07:56:38.79#ibcon#*before write, iclass 16, count 0 2006.224.07:56:38.79#ibcon#enter sib2, iclass 16, count 0 2006.224.07:56:38.79#ibcon#flushed, iclass 16, count 0 2006.224.07:56:38.79#ibcon#about to write, iclass 16, count 0 2006.224.07:56:38.79#ibcon#wrote, iclass 16, count 0 2006.224.07:56:38.79#ibcon#about to read 3, iclass 16, count 0 2006.224.07:56:38.82#ibcon#read 3, iclass 16, count 0 2006.224.07:56:38.82#ibcon#about to read 4, iclass 16, count 0 2006.224.07:56:38.82#ibcon#read 4, iclass 16, count 0 2006.224.07:56:38.82#ibcon#about to read 5, iclass 16, count 0 2006.224.07:56:38.82#ibcon#read 5, iclass 16, count 0 2006.224.07:56:38.82#ibcon#about to read 6, iclass 16, count 0 2006.224.07:56:38.82#ibcon#read 6, iclass 16, count 0 2006.224.07:56:38.82#ibcon#end of sib2, iclass 16, count 0 2006.224.07:56:38.82#ibcon#*after write, iclass 16, count 0 2006.224.07:56:38.82#ibcon#*before return 0, iclass 16, count 0 2006.224.07:56:38.82#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.224.07:56:38.82#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.224.07:56:38.82#ibcon#about to clear, iclass 16 cls_cnt 0 2006.224.07:56:38.82#ibcon#cleared, iclass 16 cls_cnt 0 2006.224.07:56:38.82$vc4f8/valo=4,832.99 2006.224.07:56:38.82#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.224.07:56:38.82#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.224.07:56:38.82#ibcon#ireg 17 cls_cnt 0 2006.224.07:56:38.82#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.224.07:56:38.82#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.224.07:56:38.82#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.224.07:56:38.82#ibcon#enter wrdev, iclass 18, count 0 2006.224.07:56:38.82#ibcon#first serial, iclass 18, count 0 2006.224.07:56:38.82#ibcon#enter sib2, iclass 18, count 0 2006.224.07:56:38.82#ibcon#flushed, iclass 18, count 0 2006.224.07:56:38.82#ibcon#about to write, iclass 18, count 0 2006.224.07:56:38.82#ibcon#wrote, iclass 18, count 0 2006.224.07:56:38.82#ibcon#about to read 3, iclass 18, count 0 2006.224.07:56:38.84#ibcon#read 3, iclass 18, count 0 2006.224.07:56:38.84#ibcon#about to read 4, iclass 18, count 0 2006.224.07:56:38.84#ibcon#read 4, iclass 18, count 0 2006.224.07:56:38.84#ibcon#about to read 5, iclass 18, count 0 2006.224.07:56:38.84#ibcon#read 5, iclass 18, count 0 2006.224.07:56:38.84#ibcon#about to read 6, iclass 18, count 0 2006.224.07:56:38.84#ibcon#read 6, iclass 18, count 0 2006.224.07:56:38.84#ibcon#end of sib2, iclass 18, count 0 2006.224.07:56:38.84#ibcon#*mode == 0, iclass 18, count 0 2006.224.07:56:38.84#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.224.07:56:38.84#ibcon#[26=FRQ=04,832.99\r\n] 2006.224.07:56:38.84#ibcon#*before write, iclass 18, count 0 2006.224.07:56:38.84#ibcon#enter sib2, iclass 18, count 0 2006.224.07:56:38.84#ibcon#flushed, iclass 18, count 0 2006.224.07:56:38.84#ibcon#about to write, iclass 18, count 0 2006.224.07:56:38.84#ibcon#wrote, iclass 18, count 0 2006.224.07:56:38.84#ibcon#about to read 3, iclass 18, count 0 2006.224.07:56:38.88#ibcon#read 3, iclass 18, count 0 2006.224.07:56:38.88#ibcon#about to read 4, iclass 18, count 0 2006.224.07:56:38.88#ibcon#read 4, iclass 18, count 0 2006.224.07:56:38.88#ibcon#about to read 5, iclass 18, count 0 2006.224.07:56:38.88#ibcon#read 5, iclass 18, count 0 2006.224.07:56:38.88#ibcon#about to read 6, iclass 18, count 0 2006.224.07:56:38.88#ibcon#read 6, iclass 18, count 0 2006.224.07:56:38.88#ibcon#end of sib2, iclass 18, count 0 2006.224.07:56:38.88#ibcon#*after write, iclass 18, count 0 2006.224.07:56:38.88#ibcon#*before return 0, iclass 18, count 0 2006.224.07:56:38.88#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.224.07:56:38.88#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.224.07:56:38.88#ibcon#about to clear, iclass 18 cls_cnt 0 2006.224.07:56:38.88#ibcon#cleared, iclass 18 cls_cnt 0 2006.224.07:56:38.88$vc4f8/va=4,7 2006.224.07:56:38.88#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.224.07:56:38.88#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.224.07:56:38.88#ibcon#ireg 11 cls_cnt 2 2006.224.07:56:38.88#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.224.07:56:38.94#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.224.07:56:38.94#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.224.07:56:38.94#ibcon#enter wrdev, iclass 20, count 2 2006.224.07:56:38.94#ibcon#first serial, iclass 20, count 2 2006.224.07:56:38.94#ibcon#enter sib2, iclass 20, count 2 2006.224.07:56:38.94#ibcon#flushed, iclass 20, count 2 2006.224.07:56:38.94#ibcon#about to write, iclass 20, count 2 2006.224.07:56:38.94#ibcon#wrote, iclass 20, count 2 2006.224.07:56:38.94#ibcon#about to read 3, iclass 20, count 2 2006.224.07:56:38.96#ibcon#read 3, iclass 20, count 2 2006.224.07:56:38.96#ibcon#about to read 4, iclass 20, count 2 2006.224.07:56:38.96#ibcon#read 4, iclass 20, count 2 2006.224.07:56:38.96#ibcon#about to read 5, iclass 20, count 2 2006.224.07:56:38.96#ibcon#read 5, iclass 20, count 2 2006.224.07:56:38.96#ibcon#about to read 6, iclass 20, count 2 2006.224.07:56:38.96#ibcon#read 6, iclass 20, count 2 2006.224.07:56:38.96#ibcon#end of sib2, iclass 20, count 2 2006.224.07:56:38.96#ibcon#*mode == 0, iclass 20, count 2 2006.224.07:56:38.96#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.224.07:56:38.96#ibcon#[25=AT04-07\r\n] 2006.224.07:56:38.96#ibcon#*before write, iclass 20, count 2 2006.224.07:56:38.96#ibcon#enter sib2, iclass 20, count 2 2006.224.07:56:38.96#ibcon#flushed, iclass 20, count 2 2006.224.07:56:38.96#ibcon#about to write, iclass 20, count 2 2006.224.07:56:38.96#ibcon#wrote, iclass 20, count 2 2006.224.07:56:38.96#ibcon#about to read 3, iclass 20, count 2 2006.224.07:56:38.99#ibcon#read 3, iclass 20, count 2 2006.224.07:56:38.99#ibcon#about to read 4, iclass 20, count 2 2006.224.07:56:38.99#ibcon#read 4, iclass 20, count 2 2006.224.07:56:38.99#ibcon#about to read 5, iclass 20, count 2 2006.224.07:56:38.99#ibcon#read 5, iclass 20, count 2 2006.224.07:56:38.99#ibcon#about to read 6, iclass 20, count 2 2006.224.07:56:38.99#ibcon#read 6, iclass 20, count 2 2006.224.07:56:38.99#ibcon#end of sib2, iclass 20, count 2 2006.224.07:56:38.99#ibcon#*after write, iclass 20, count 2 2006.224.07:56:38.99#ibcon#*before return 0, iclass 20, count 2 2006.224.07:56:38.99#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.224.07:56:38.99#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.224.07:56:38.99#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.224.07:56:38.99#ibcon#ireg 7 cls_cnt 0 2006.224.07:56:38.99#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.224.07:56:39.11#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.224.07:56:39.11#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.224.07:56:39.11#ibcon#enter wrdev, iclass 20, count 0 2006.224.07:56:39.11#ibcon#first serial, iclass 20, count 0 2006.224.07:56:39.11#ibcon#enter sib2, iclass 20, count 0 2006.224.07:56:39.11#ibcon#flushed, iclass 20, count 0 2006.224.07:56:39.11#ibcon#about to write, iclass 20, count 0 2006.224.07:56:39.11#ibcon#wrote, iclass 20, count 0 2006.224.07:56:39.11#ibcon#about to read 3, iclass 20, count 0 2006.224.07:56:39.13#ibcon#read 3, iclass 20, count 0 2006.224.07:56:39.13#ibcon#about to read 4, iclass 20, count 0 2006.224.07:56:39.13#ibcon#read 4, iclass 20, count 0 2006.224.07:56:39.13#ibcon#about to read 5, iclass 20, count 0 2006.224.07:56:39.13#ibcon#read 5, iclass 20, count 0 2006.224.07:56:39.13#ibcon#about to read 6, iclass 20, count 0 2006.224.07:56:39.13#ibcon#read 6, iclass 20, count 0 2006.224.07:56:39.13#ibcon#end of sib2, iclass 20, count 0 2006.224.07:56:39.13#ibcon#*mode == 0, iclass 20, count 0 2006.224.07:56:39.13#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.224.07:56:39.13#ibcon#[25=USB\r\n] 2006.224.07:56:39.13#ibcon#*before write, iclass 20, count 0 2006.224.07:56:39.13#ibcon#enter sib2, iclass 20, count 0 2006.224.07:56:39.13#ibcon#flushed, iclass 20, count 0 2006.224.07:56:39.13#ibcon#about to write, iclass 20, count 0 2006.224.07:56:39.13#ibcon#wrote, iclass 20, count 0 2006.224.07:56:39.13#ibcon#about to read 3, iclass 20, count 0 2006.224.07:56:39.16#ibcon#read 3, iclass 20, count 0 2006.224.07:56:39.16#ibcon#about to read 4, iclass 20, count 0 2006.224.07:56:39.16#ibcon#read 4, iclass 20, count 0 2006.224.07:56:39.16#ibcon#about to read 5, iclass 20, count 0 2006.224.07:56:39.16#ibcon#read 5, iclass 20, count 0 2006.224.07:56:39.16#ibcon#about to read 6, iclass 20, count 0 2006.224.07:56:39.16#ibcon#read 6, iclass 20, count 0 2006.224.07:56:39.16#ibcon#end of sib2, iclass 20, count 0 2006.224.07:56:39.16#ibcon#*after write, iclass 20, count 0 2006.224.07:56:39.16#ibcon#*before return 0, iclass 20, count 0 2006.224.07:56:39.16#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.224.07:56:39.16#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.224.07:56:39.16#ibcon#about to clear, iclass 20 cls_cnt 0 2006.224.07:56:39.16#ibcon#cleared, iclass 20 cls_cnt 0 2006.224.07:56:39.16$vc4f8/valo=5,652.99 2006.224.07:56:39.16#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.224.07:56:39.16#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.224.07:56:39.16#ibcon#ireg 17 cls_cnt 0 2006.224.07:56:39.16#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.224.07:56:39.16#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.224.07:56:39.16#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.224.07:56:39.16#ibcon#enter wrdev, iclass 22, count 0 2006.224.07:56:39.16#ibcon#first serial, iclass 22, count 0 2006.224.07:56:39.16#ibcon#enter sib2, iclass 22, count 0 2006.224.07:56:39.16#ibcon#flushed, iclass 22, count 0 2006.224.07:56:39.16#ibcon#about to write, iclass 22, count 0 2006.224.07:56:39.16#ibcon#wrote, iclass 22, count 0 2006.224.07:56:39.16#ibcon#about to read 3, iclass 22, count 0 2006.224.07:56:39.18#ibcon#read 3, iclass 22, count 0 2006.224.07:56:39.18#ibcon#about to read 4, iclass 22, count 0 2006.224.07:56:39.18#ibcon#read 4, iclass 22, count 0 2006.224.07:56:39.18#ibcon#about to read 5, iclass 22, count 0 2006.224.07:56:39.18#ibcon#read 5, iclass 22, count 0 2006.224.07:56:39.18#ibcon#about to read 6, iclass 22, count 0 2006.224.07:56:39.18#ibcon#read 6, iclass 22, count 0 2006.224.07:56:39.18#ibcon#end of sib2, iclass 22, count 0 2006.224.07:56:39.18#ibcon#*mode == 0, iclass 22, count 0 2006.224.07:56:39.18#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.224.07:56:39.18#ibcon#[26=FRQ=05,652.99\r\n] 2006.224.07:56:39.18#ibcon#*before write, iclass 22, count 0 2006.224.07:56:39.18#ibcon#enter sib2, iclass 22, count 0 2006.224.07:56:39.18#ibcon#flushed, iclass 22, count 0 2006.224.07:56:39.18#ibcon#about to write, iclass 22, count 0 2006.224.07:56:39.18#ibcon#wrote, iclass 22, count 0 2006.224.07:56:39.18#ibcon#about to read 3, iclass 22, count 0 2006.224.07:56:39.22#ibcon#read 3, iclass 22, count 0 2006.224.07:56:39.22#ibcon#about to read 4, iclass 22, count 0 2006.224.07:56:39.22#ibcon#read 4, iclass 22, count 0 2006.224.07:56:39.22#ibcon#about to read 5, iclass 22, count 0 2006.224.07:56:39.22#ibcon#read 5, iclass 22, count 0 2006.224.07:56:39.22#ibcon#about to read 6, iclass 22, count 0 2006.224.07:56:39.22#ibcon#read 6, iclass 22, count 0 2006.224.07:56:39.22#ibcon#end of sib2, iclass 22, count 0 2006.224.07:56:39.22#ibcon#*after write, iclass 22, count 0 2006.224.07:56:39.22#ibcon#*before return 0, iclass 22, count 0 2006.224.07:56:39.22#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.224.07:56:39.22#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.224.07:56:39.22#ibcon#about to clear, iclass 22 cls_cnt 0 2006.224.07:56:39.22#ibcon#cleared, iclass 22 cls_cnt 0 2006.224.07:56:39.22$vc4f8/va=5,7 2006.224.07:56:39.22#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.224.07:56:39.22#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.224.07:56:39.22#ibcon#ireg 11 cls_cnt 2 2006.224.07:56:39.22#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.224.07:56:39.28#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.224.07:56:39.28#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.224.07:56:39.28#ibcon#enter wrdev, iclass 24, count 2 2006.224.07:56:39.28#ibcon#first serial, iclass 24, count 2 2006.224.07:56:39.28#ibcon#enter sib2, iclass 24, count 2 2006.224.07:56:39.28#ibcon#flushed, iclass 24, count 2 2006.224.07:56:39.28#ibcon#about to write, iclass 24, count 2 2006.224.07:56:39.28#ibcon#wrote, iclass 24, count 2 2006.224.07:56:39.28#ibcon#about to read 3, iclass 24, count 2 2006.224.07:56:39.30#ibcon#read 3, iclass 24, count 2 2006.224.07:56:39.30#ibcon#about to read 4, iclass 24, count 2 2006.224.07:56:39.30#ibcon#read 4, iclass 24, count 2 2006.224.07:56:39.30#ibcon#about to read 5, iclass 24, count 2 2006.224.07:56:39.30#ibcon#read 5, iclass 24, count 2 2006.224.07:56:39.30#ibcon#about to read 6, iclass 24, count 2 2006.224.07:56:39.30#ibcon#read 6, iclass 24, count 2 2006.224.07:56:39.30#ibcon#end of sib2, iclass 24, count 2 2006.224.07:56:39.30#ibcon#*mode == 0, iclass 24, count 2 2006.224.07:56:39.30#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.224.07:56:39.30#ibcon#[25=AT05-07\r\n] 2006.224.07:56:39.30#ibcon#*before write, iclass 24, count 2 2006.224.07:56:39.30#ibcon#enter sib2, iclass 24, count 2 2006.224.07:56:39.30#ibcon#flushed, iclass 24, count 2 2006.224.07:56:39.30#ibcon#about to write, iclass 24, count 2 2006.224.07:56:39.30#ibcon#wrote, iclass 24, count 2 2006.224.07:56:39.30#ibcon#about to read 3, iclass 24, count 2 2006.224.07:56:39.33#ibcon#read 3, iclass 24, count 2 2006.224.07:56:39.33#ibcon#about to read 4, iclass 24, count 2 2006.224.07:56:39.33#ibcon#read 4, iclass 24, count 2 2006.224.07:56:39.33#ibcon#about to read 5, iclass 24, count 2 2006.224.07:56:39.33#ibcon#read 5, iclass 24, count 2 2006.224.07:56:39.33#ibcon#about to read 6, iclass 24, count 2 2006.224.07:56:39.33#ibcon#read 6, iclass 24, count 2 2006.224.07:56:39.33#ibcon#end of sib2, iclass 24, count 2 2006.224.07:56:39.33#ibcon#*after write, iclass 24, count 2 2006.224.07:56:39.33#ibcon#*before return 0, iclass 24, count 2 2006.224.07:56:39.33#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.224.07:56:39.33#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.224.07:56:39.33#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.224.07:56:39.33#ibcon#ireg 7 cls_cnt 0 2006.224.07:56:39.33#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.224.07:56:39.45#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.224.07:56:39.45#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.224.07:56:39.45#ibcon#enter wrdev, iclass 24, count 0 2006.224.07:56:39.45#ibcon#first serial, iclass 24, count 0 2006.224.07:56:39.45#ibcon#enter sib2, iclass 24, count 0 2006.224.07:56:39.45#ibcon#flushed, iclass 24, count 0 2006.224.07:56:39.45#ibcon#about to write, iclass 24, count 0 2006.224.07:56:39.45#ibcon#wrote, iclass 24, count 0 2006.224.07:56:39.45#ibcon#about to read 3, iclass 24, count 0 2006.224.07:56:39.47#ibcon#read 3, iclass 24, count 0 2006.224.07:56:39.47#ibcon#about to read 4, iclass 24, count 0 2006.224.07:56:39.47#ibcon#read 4, iclass 24, count 0 2006.224.07:56:39.47#ibcon#about to read 5, iclass 24, count 0 2006.224.07:56:39.47#ibcon#read 5, iclass 24, count 0 2006.224.07:56:39.47#ibcon#about to read 6, iclass 24, count 0 2006.224.07:56:39.47#ibcon#read 6, iclass 24, count 0 2006.224.07:56:39.47#ibcon#end of sib2, iclass 24, count 0 2006.224.07:56:39.47#ibcon#*mode == 0, iclass 24, count 0 2006.224.07:56:39.47#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.224.07:56:39.47#ibcon#[25=USB\r\n] 2006.224.07:56:39.47#ibcon#*before write, iclass 24, count 0 2006.224.07:56:39.47#ibcon#enter sib2, iclass 24, count 0 2006.224.07:56:39.47#ibcon#flushed, iclass 24, count 0 2006.224.07:56:39.47#ibcon#about to write, iclass 24, count 0 2006.224.07:56:39.47#ibcon#wrote, iclass 24, count 0 2006.224.07:56:39.47#ibcon#about to read 3, iclass 24, count 0 2006.224.07:56:39.50#ibcon#read 3, iclass 24, count 0 2006.224.07:56:39.50#ibcon#about to read 4, iclass 24, count 0 2006.224.07:56:39.50#ibcon#read 4, iclass 24, count 0 2006.224.07:56:39.50#ibcon#about to read 5, iclass 24, count 0 2006.224.07:56:39.50#ibcon#read 5, iclass 24, count 0 2006.224.07:56:39.50#ibcon#about to read 6, iclass 24, count 0 2006.224.07:56:39.50#ibcon#read 6, iclass 24, count 0 2006.224.07:56:39.50#ibcon#end of sib2, iclass 24, count 0 2006.224.07:56:39.50#ibcon#*after write, iclass 24, count 0 2006.224.07:56:39.50#ibcon#*before return 0, iclass 24, count 0 2006.224.07:56:39.50#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.224.07:56:39.50#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.224.07:56:39.50#ibcon#about to clear, iclass 24 cls_cnt 0 2006.224.07:56:39.50#ibcon#cleared, iclass 24 cls_cnt 0 2006.224.07:56:39.50$vc4f8/valo=6,772.99 2006.224.07:56:39.50#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.224.07:56:39.50#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.224.07:56:39.50#ibcon#ireg 17 cls_cnt 0 2006.224.07:56:39.50#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.224.07:56:39.50#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.224.07:56:39.50#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.224.07:56:39.50#ibcon#enter wrdev, iclass 26, count 0 2006.224.07:56:39.50#ibcon#first serial, iclass 26, count 0 2006.224.07:56:39.50#ibcon#enter sib2, iclass 26, count 0 2006.224.07:56:39.50#ibcon#flushed, iclass 26, count 0 2006.224.07:56:39.50#ibcon#about to write, iclass 26, count 0 2006.224.07:56:39.50#ibcon#wrote, iclass 26, count 0 2006.224.07:56:39.50#ibcon#about to read 3, iclass 26, count 0 2006.224.07:56:39.53#ibcon#read 3, iclass 26, count 0 2006.224.07:56:39.53#ibcon#about to read 4, iclass 26, count 0 2006.224.07:56:39.53#ibcon#read 4, iclass 26, count 0 2006.224.07:56:39.53#ibcon#about to read 5, iclass 26, count 0 2006.224.07:56:39.53#ibcon#read 5, iclass 26, count 0 2006.224.07:56:39.53#ibcon#about to read 6, iclass 26, count 0 2006.224.07:56:39.53#ibcon#read 6, iclass 26, count 0 2006.224.07:56:39.53#ibcon#end of sib2, iclass 26, count 0 2006.224.07:56:39.53#ibcon#*mode == 0, iclass 26, count 0 2006.224.07:56:39.53#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.224.07:56:39.53#ibcon#[26=FRQ=06,772.99\r\n] 2006.224.07:56:39.53#ibcon#*before write, iclass 26, count 0 2006.224.07:56:39.53#ibcon#enter sib2, iclass 26, count 0 2006.224.07:56:39.53#ibcon#flushed, iclass 26, count 0 2006.224.07:56:39.53#ibcon#about to write, iclass 26, count 0 2006.224.07:56:39.53#ibcon#wrote, iclass 26, count 0 2006.224.07:56:39.53#ibcon#about to read 3, iclass 26, count 0 2006.224.07:56:39.57#ibcon#read 3, iclass 26, count 0 2006.224.07:56:39.57#ibcon#about to read 4, iclass 26, count 0 2006.224.07:56:39.57#ibcon#read 4, iclass 26, count 0 2006.224.07:56:39.57#ibcon#about to read 5, iclass 26, count 0 2006.224.07:56:39.57#ibcon#read 5, iclass 26, count 0 2006.224.07:56:39.57#ibcon#about to read 6, iclass 26, count 0 2006.224.07:56:39.57#ibcon#read 6, iclass 26, count 0 2006.224.07:56:39.57#ibcon#end of sib2, iclass 26, count 0 2006.224.07:56:39.57#ibcon#*after write, iclass 26, count 0 2006.224.07:56:39.57#ibcon#*before return 0, iclass 26, count 0 2006.224.07:56:39.57#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.224.07:56:39.57#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.224.07:56:39.57#ibcon#about to clear, iclass 26 cls_cnt 0 2006.224.07:56:39.57#ibcon#cleared, iclass 26 cls_cnt 0 2006.224.07:56:39.57$vc4f8/va=6,6 2006.224.07:56:39.57#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.224.07:56:39.57#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.224.07:56:39.57#ibcon#ireg 11 cls_cnt 2 2006.224.07:56:39.57#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.224.07:56:39.62#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.224.07:56:39.62#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.224.07:56:39.62#ibcon#enter wrdev, iclass 28, count 2 2006.224.07:56:39.62#ibcon#first serial, iclass 28, count 2 2006.224.07:56:39.62#ibcon#enter sib2, iclass 28, count 2 2006.224.07:56:39.62#ibcon#flushed, iclass 28, count 2 2006.224.07:56:39.62#ibcon#about to write, iclass 28, count 2 2006.224.07:56:39.62#ibcon#wrote, iclass 28, count 2 2006.224.07:56:39.62#ibcon#about to read 3, iclass 28, count 2 2006.224.07:56:39.64#ibcon#read 3, iclass 28, count 2 2006.224.07:56:39.64#ibcon#about to read 4, iclass 28, count 2 2006.224.07:56:39.64#ibcon#read 4, iclass 28, count 2 2006.224.07:56:39.64#ibcon#about to read 5, iclass 28, count 2 2006.224.07:56:39.64#ibcon#read 5, iclass 28, count 2 2006.224.07:56:39.64#ibcon#about to read 6, iclass 28, count 2 2006.224.07:56:39.64#ibcon#read 6, iclass 28, count 2 2006.224.07:56:39.64#ibcon#end of sib2, iclass 28, count 2 2006.224.07:56:39.64#ibcon#*mode == 0, iclass 28, count 2 2006.224.07:56:39.64#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.224.07:56:39.64#ibcon#[25=AT06-06\r\n] 2006.224.07:56:39.64#ibcon#*before write, iclass 28, count 2 2006.224.07:56:39.64#ibcon#enter sib2, iclass 28, count 2 2006.224.07:56:39.64#ibcon#flushed, iclass 28, count 2 2006.224.07:56:39.64#ibcon#about to write, iclass 28, count 2 2006.224.07:56:39.64#ibcon#wrote, iclass 28, count 2 2006.224.07:56:39.64#ibcon#about to read 3, iclass 28, count 2 2006.224.07:56:39.67#ibcon#read 3, iclass 28, count 2 2006.224.07:56:39.67#ibcon#about to read 4, iclass 28, count 2 2006.224.07:56:39.67#ibcon#read 4, iclass 28, count 2 2006.224.07:56:39.67#ibcon#about to read 5, iclass 28, count 2 2006.224.07:56:39.67#ibcon#read 5, iclass 28, count 2 2006.224.07:56:39.67#ibcon#about to read 6, iclass 28, count 2 2006.224.07:56:39.67#ibcon#read 6, iclass 28, count 2 2006.224.07:56:39.67#ibcon#end of sib2, iclass 28, count 2 2006.224.07:56:39.67#ibcon#*after write, iclass 28, count 2 2006.224.07:56:39.67#ibcon#*before return 0, iclass 28, count 2 2006.224.07:56:39.67#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.224.07:56:39.67#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.224.07:56:39.67#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.224.07:56:39.67#ibcon#ireg 7 cls_cnt 0 2006.224.07:56:39.67#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.224.07:56:39.79#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.224.07:56:39.79#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.224.07:56:39.79#ibcon#enter wrdev, iclass 28, count 0 2006.224.07:56:39.79#ibcon#first serial, iclass 28, count 0 2006.224.07:56:39.79#ibcon#enter sib2, iclass 28, count 0 2006.224.07:56:39.79#ibcon#flushed, iclass 28, count 0 2006.224.07:56:39.79#ibcon#about to write, iclass 28, count 0 2006.224.07:56:39.79#ibcon#wrote, iclass 28, count 0 2006.224.07:56:39.79#ibcon#about to read 3, iclass 28, count 0 2006.224.07:56:39.81#ibcon#read 3, iclass 28, count 0 2006.224.07:56:39.81#ibcon#about to read 4, iclass 28, count 0 2006.224.07:56:39.81#ibcon#read 4, iclass 28, count 0 2006.224.07:56:39.81#ibcon#about to read 5, iclass 28, count 0 2006.224.07:56:39.81#ibcon#read 5, iclass 28, count 0 2006.224.07:56:39.81#ibcon#about to read 6, iclass 28, count 0 2006.224.07:56:39.81#ibcon#read 6, iclass 28, count 0 2006.224.07:56:39.81#ibcon#end of sib2, iclass 28, count 0 2006.224.07:56:39.81#ibcon#*mode == 0, iclass 28, count 0 2006.224.07:56:39.81#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.224.07:56:39.81#ibcon#[25=USB\r\n] 2006.224.07:56:39.81#ibcon#*before write, iclass 28, count 0 2006.224.07:56:39.81#ibcon#enter sib2, iclass 28, count 0 2006.224.07:56:39.81#ibcon#flushed, iclass 28, count 0 2006.224.07:56:39.81#ibcon#about to write, iclass 28, count 0 2006.224.07:56:39.81#ibcon#wrote, iclass 28, count 0 2006.224.07:56:39.81#ibcon#about to read 3, iclass 28, count 0 2006.224.07:56:39.84#ibcon#read 3, iclass 28, count 0 2006.224.07:56:39.84#ibcon#about to read 4, iclass 28, count 0 2006.224.07:56:39.84#ibcon#read 4, iclass 28, count 0 2006.224.07:56:39.84#ibcon#about to read 5, iclass 28, count 0 2006.224.07:56:39.84#ibcon#read 5, iclass 28, count 0 2006.224.07:56:39.84#ibcon#about to read 6, iclass 28, count 0 2006.224.07:56:39.84#ibcon#read 6, iclass 28, count 0 2006.224.07:56:39.84#ibcon#end of sib2, iclass 28, count 0 2006.224.07:56:39.84#ibcon#*after write, iclass 28, count 0 2006.224.07:56:39.84#ibcon#*before return 0, iclass 28, count 0 2006.224.07:56:39.84#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.224.07:56:39.84#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.224.07:56:39.84#ibcon#about to clear, iclass 28 cls_cnt 0 2006.224.07:56:39.84#ibcon#cleared, iclass 28 cls_cnt 0 2006.224.07:56:39.84$vc4f8/valo=7,832.99 2006.224.07:56:39.84#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.224.07:56:39.84#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.224.07:56:39.84#ibcon#ireg 17 cls_cnt 0 2006.224.07:56:39.84#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.224.07:56:39.84#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.224.07:56:39.84#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.224.07:56:39.84#ibcon#enter wrdev, iclass 30, count 0 2006.224.07:56:39.84#ibcon#first serial, iclass 30, count 0 2006.224.07:56:39.84#ibcon#enter sib2, iclass 30, count 0 2006.224.07:56:39.84#ibcon#flushed, iclass 30, count 0 2006.224.07:56:39.84#ibcon#about to write, iclass 30, count 0 2006.224.07:56:39.84#ibcon#wrote, iclass 30, count 0 2006.224.07:56:39.84#ibcon#about to read 3, iclass 30, count 0 2006.224.07:56:39.86#ibcon#read 3, iclass 30, count 0 2006.224.07:56:39.86#ibcon#about to read 4, iclass 30, count 0 2006.224.07:56:39.86#ibcon#read 4, iclass 30, count 0 2006.224.07:56:39.86#ibcon#about to read 5, iclass 30, count 0 2006.224.07:56:39.86#ibcon#read 5, iclass 30, count 0 2006.224.07:56:39.86#ibcon#about to read 6, iclass 30, count 0 2006.224.07:56:39.86#ibcon#read 6, iclass 30, count 0 2006.224.07:56:39.86#ibcon#end of sib2, iclass 30, count 0 2006.224.07:56:39.86#ibcon#*mode == 0, iclass 30, count 0 2006.224.07:56:39.86#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.224.07:56:39.86#ibcon#[26=FRQ=07,832.99\r\n] 2006.224.07:56:39.86#ibcon#*before write, iclass 30, count 0 2006.224.07:56:39.86#ibcon#enter sib2, iclass 30, count 0 2006.224.07:56:39.86#ibcon#flushed, iclass 30, count 0 2006.224.07:56:39.86#ibcon#about to write, iclass 30, count 0 2006.224.07:56:39.86#ibcon#wrote, iclass 30, count 0 2006.224.07:56:39.86#ibcon#about to read 3, iclass 30, count 0 2006.224.07:56:39.90#ibcon#read 3, iclass 30, count 0 2006.224.07:56:39.90#ibcon#about to read 4, iclass 30, count 0 2006.224.07:56:39.90#ibcon#read 4, iclass 30, count 0 2006.224.07:56:39.90#ibcon#about to read 5, iclass 30, count 0 2006.224.07:56:39.90#ibcon#read 5, iclass 30, count 0 2006.224.07:56:39.90#ibcon#about to read 6, iclass 30, count 0 2006.224.07:56:39.90#ibcon#read 6, iclass 30, count 0 2006.224.07:56:39.90#ibcon#end of sib2, iclass 30, count 0 2006.224.07:56:39.90#ibcon#*after write, iclass 30, count 0 2006.224.07:56:39.90#ibcon#*before return 0, iclass 30, count 0 2006.224.07:56:39.90#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.224.07:56:39.90#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.224.07:56:39.90#ibcon#about to clear, iclass 30 cls_cnt 0 2006.224.07:56:39.90#ibcon#cleared, iclass 30 cls_cnt 0 2006.224.07:56:39.90$vc4f8/va=7,6 2006.224.07:56:39.90#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.224.07:56:39.90#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.224.07:56:39.90#ibcon#ireg 11 cls_cnt 2 2006.224.07:56:39.90#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.224.07:56:39.96#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.224.07:56:39.96#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.224.07:56:39.96#ibcon#enter wrdev, iclass 32, count 2 2006.224.07:56:39.96#ibcon#first serial, iclass 32, count 2 2006.224.07:56:39.96#ibcon#enter sib2, iclass 32, count 2 2006.224.07:56:39.96#ibcon#flushed, iclass 32, count 2 2006.224.07:56:39.96#ibcon#about to write, iclass 32, count 2 2006.224.07:56:39.96#ibcon#wrote, iclass 32, count 2 2006.224.07:56:39.96#ibcon#about to read 3, iclass 32, count 2 2006.224.07:56:39.98#ibcon#read 3, iclass 32, count 2 2006.224.07:56:39.98#ibcon#about to read 4, iclass 32, count 2 2006.224.07:56:39.98#ibcon#read 4, iclass 32, count 2 2006.224.07:56:39.98#ibcon#about to read 5, iclass 32, count 2 2006.224.07:56:39.98#ibcon#read 5, iclass 32, count 2 2006.224.07:56:39.98#ibcon#about to read 6, iclass 32, count 2 2006.224.07:56:39.98#ibcon#read 6, iclass 32, count 2 2006.224.07:56:39.98#ibcon#end of sib2, iclass 32, count 2 2006.224.07:56:39.98#ibcon#*mode == 0, iclass 32, count 2 2006.224.07:56:39.98#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.224.07:56:39.98#ibcon#[25=AT07-06\r\n] 2006.224.07:56:39.98#ibcon#*before write, iclass 32, count 2 2006.224.07:56:39.98#ibcon#enter sib2, iclass 32, count 2 2006.224.07:56:39.98#ibcon#flushed, iclass 32, count 2 2006.224.07:56:39.98#ibcon#about to write, iclass 32, count 2 2006.224.07:56:39.98#ibcon#wrote, iclass 32, count 2 2006.224.07:56:39.98#ibcon#about to read 3, iclass 32, count 2 2006.224.07:56:40.01#ibcon#read 3, iclass 32, count 2 2006.224.07:56:40.01#ibcon#about to read 4, iclass 32, count 2 2006.224.07:56:40.01#ibcon#read 4, iclass 32, count 2 2006.224.07:56:40.01#ibcon#about to read 5, iclass 32, count 2 2006.224.07:56:40.01#ibcon#read 5, iclass 32, count 2 2006.224.07:56:40.01#ibcon#about to read 6, iclass 32, count 2 2006.224.07:56:40.01#ibcon#read 6, iclass 32, count 2 2006.224.07:56:40.01#ibcon#end of sib2, iclass 32, count 2 2006.224.07:56:40.01#ibcon#*after write, iclass 32, count 2 2006.224.07:56:40.01#ibcon#*before return 0, iclass 32, count 2 2006.224.07:56:40.01#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.224.07:56:40.01#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.224.07:56:40.01#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.224.07:56:40.01#ibcon#ireg 7 cls_cnt 0 2006.224.07:56:40.01#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.224.07:56:40.13#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.224.07:56:40.13#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.224.07:56:40.13#ibcon#enter wrdev, iclass 32, count 0 2006.224.07:56:40.13#ibcon#first serial, iclass 32, count 0 2006.224.07:56:40.13#ibcon#enter sib2, iclass 32, count 0 2006.224.07:56:40.13#ibcon#flushed, iclass 32, count 0 2006.224.07:56:40.13#ibcon#about to write, iclass 32, count 0 2006.224.07:56:40.13#ibcon#wrote, iclass 32, count 0 2006.224.07:56:40.13#ibcon#about to read 3, iclass 32, count 0 2006.224.07:56:40.15#ibcon#read 3, iclass 32, count 0 2006.224.07:56:40.15#ibcon#about to read 4, iclass 32, count 0 2006.224.07:56:40.15#ibcon#read 4, iclass 32, count 0 2006.224.07:56:40.15#ibcon#about to read 5, iclass 32, count 0 2006.224.07:56:40.15#ibcon#read 5, iclass 32, count 0 2006.224.07:56:40.15#ibcon#about to read 6, iclass 32, count 0 2006.224.07:56:40.15#ibcon#read 6, iclass 32, count 0 2006.224.07:56:40.15#ibcon#end of sib2, iclass 32, count 0 2006.224.07:56:40.15#ibcon#*mode == 0, iclass 32, count 0 2006.224.07:56:40.15#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.224.07:56:40.15#ibcon#[25=USB\r\n] 2006.224.07:56:40.15#ibcon#*before write, iclass 32, count 0 2006.224.07:56:40.15#ibcon#enter sib2, iclass 32, count 0 2006.224.07:56:40.15#ibcon#flushed, iclass 32, count 0 2006.224.07:56:40.15#ibcon#about to write, iclass 32, count 0 2006.224.07:56:40.15#ibcon#wrote, iclass 32, count 0 2006.224.07:56:40.15#ibcon#about to read 3, iclass 32, count 0 2006.224.07:56:40.18#ibcon#read 3, iclass 32, count 0 2006.224.07:56:40.18#ibcon#about to read 4, iclass 32, count 0 2006.224.07:56:40.18#ibcon#read 4, iclass 32, count 0 2006.224.07:56:40.18#ibcon#about to read 5, iclass 32, count 0 2006.224.07:56:40.18#ibcon#read 5, iclass 32, count 0 2006.224.07:56:40.18#ibcon#about to read 6, iclass 32, count 0 2006.224.07:56:40.18#ibcon#read 6, iclass 32, count 0 2006.224.07:56:40.18#ibcon#end of sib2, iclass 32, count 0 2006.224.07:56:40.18#ibcon#*after write, iclass 32, count 0 2006.224.07:56:40.18#ibcon#*before return 0, iclass 32, count 0 2006.224.07:56:40.18#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.224.07:56:40.18#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.224.07:56:40.18#ibcon#about to clear, iclass 32 cls_cnt 0 2006.224.07:56:40.18#ibcon#cleared, iclass 32 cls_cnt 0 2006.224.07:56:40.18$vc4f8/valo=8,852.99 2006.224.07:56:40.18#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.224.07:56:40.18#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.224.07:56:40.18#ibcon#ireg 17 cls_cnt 0 2006.224.07:56:40.18#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.224.07:56:40.18#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.224.07:56:40.18#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.224.07:56:40.18#ibcon#enter wrdev, iclass 34, count 0 2006.224.07:56:40.18#ibcon#first serial, iclass 34, count 0 2006.224.07:56:40.18#ibcon#enter sib2, iclass 34, count 0 2006.224.07:56:40.18#ibcon#flushed, iclass 34, count 0 2006.224.07:56:40.18#ibcon#about to write, iclass 34, count 0 2006.224.07:56:40.18#ibcon#wrote, iclass 34, count 0 2006.224.07:56:40.18#ibcon#about to read 3, iclass 34, count 0 2006.224.07:56:40.20#ibcon#read 3, iclass 34, count 0 2006.224.07:56:40.20#ibcon#about to read 4, iclass 34, count 0 2006.224.07:56:40.20#ibcon#read 4, iclass 34, count 0 2006.224.07:56:40.20#ibcon#about to read 5, iclass 34, count 0 2006.224.07:56:40.20#ibcon#read 5, iclass 34, count 0 2006.224.07:56:40.20#ibcon#about to read 6, iclass 34, count 0 2006.224.07:56:40.20#ibcon#read 6, iclass 34, count 0 2006.224.07:56:40.20#ibcon#end of sib2, iclass 34, count 0 2006.224.07:56:40.20#ibcon#*mode == 0, iclass 34, count 0 2006.224.07:56:40.20#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.224.07:56:40.20#ibcon#[26=FRQ=08,852.99\r\n] 2006.224.07:56:40.20#ibcon#*before write, iclass 34, count 0 2006.224.07:56:40.20#ibcon#enter sib2, iclass 34, count 0 2006.224.07:56:40.20#ibcon#flushed, iclass 34, count 0 2006.224.07:56:40.20#ibcon#about to write, iclass 34, count 0 2006.224.07:56:40.20#ibcon#wrote, iclass 34, count 0 2006.224.07:56:40.20#ibcon#about to read 3, iclass 34, count 0 2006.224.07:56:40.24#ibcon#read 3, iclass 34, count 0 2006.224.07:56:40.24#ibcon#about to read 4, iclass 34, count 0 2006.224.07:56:40.24#ibcon#read 4, iclass 34, count 0 2006.224.07:56:40.24#ibcon#about to read 5, iclass 34, count 0 2006.224.07:56:40.24#ibcon#read 5, iclass 34, count 0 2006.224.07:56:40.24#ibcon#about to read 6, iclass 34, count 0 2006.224.07:56:40.24#ibcon#read 6, iclass 34, count 0 2006.224.07:56:40.24#ibcon#end of sib2, iclass 34, count 0 2006.224.07:56:40.24#ibcon#*after write, iclass 34, count 0 2006.224.07:56:40.24#ibcon#*before return 0, iclass 34, count 0 2006.224.07:56:40.24#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.224.07:56:40.24#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.224.07:56:40.24#ibcon#about to clear, iclass 34 cls_cnt 0 2006.224.07:56:40.24#ibcon#cleared, iclass 34 cls_cnt 0 2006.224.07:56:40.24$vc4f8/va=8,7 2006.224.07:56:40.24#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.224.07:56:40.24#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.224.07:56:40.24#ibcon#ireg 11 cls_cnt 2 2006.224.07:56:40.24#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.224.07:56:40.30#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.224.07:56:40.30#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.224.07:56:40.30#ibcon#enter wrdev, iclass 36, count 2 2006.224.07:56:40.30#ibcon#first serial, iclass 36, count 2 2006.224.07:56:40.30#ibcon#enter sib2, iclass 36, count 2 2006.224.07:56:40.30#ibcon#flushed, iclass 36, count 2 2006.224.07:56:40.30#ibcon#about to write, iclass 36, count 2 2006.224.07:56:40.30#ibcon#wrote, iclass 36, count 2 2006.224.07:56:40.30#ibcon#about to read 3, iclass 36, count 2 2006.224.07:56:40.32#ibcon#read 3, iclass 36, count 2 2006.224.07:56:40.32#ibcon#about to read 4, iclass 36, count 2 2006.224.07:56:40.32#ibcon#read 4, iclass 36, count 2 2006.224.07:56:40.32#ibcon#about to read 5, iclass 36, count 2 2006.224.07:56:40.32#ibcon#read 5, iclass 36, count 2 2006.224.07:56:40.32#ibcon#about to read 6, iclass 36, count 2 2006.224.07:56:40.32#ibcon#read 6, iclass 36, count 2 2006.224.07:56:40.32#ibcon#end of sib2, iclass 36, count 2 2006.224.07:56:40.32#ibcon#*mode == 0, iclass 36, count 2 2006.224.07:56:40.32#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.224.07:56:40.32#ibcon#[25=AT08-07\r\n] 2006.224.07:56:40.32#ibcon#*before write, iclass 36, count 2 2006.224.07:56:40.32#ibcon#enter sib2, iclass 36, count 2 2006.224.07:56:40.32#ibcon#flushed, iclass 36, count 2 2006.224.07:56:40.32#ibcon#about to write, iclass 36, count 2 2006.224.07:56:40.32#ibcon#wrote, iclass 36, count 2 2006.224.07:56:40.32#ibcon#about to read 3, iclass 36, count 2 2006.224.07:56:40.35#ibcon#read 3, iclass 36, count 2 2006.224.07:56:40.35#ibcon#about to read 4, iclass 36, count 2 2006.224.07:56:40.35#ibcon#read 4, iclass 36, count 2 2006.224.07:56:40.35#ibcon#about to read 5, iclass 36, count 2 2006.224.07:56:40.35#ibcon#read 5, iclass 36, count 2 2006.224.07:56:40.35#ibcon#about to read 6, iclass 36, count 2 2006.224.07:56:40.35#ibcon#read 6, iclass 36, count 2 2006.224.07:56:40.35#ibcon#end of sib2, iclass 36, count 2 2006.224.07:56:40.35#ibcon#*after write, iclass 36, count 2 2006.224.07:56:40.35#ibcon#*before return 0, iclass 36, count 2 2006.224.07:56:40.35#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.224.07:56:40.35#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.224.07:56:40.35#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.224.07:56:40.35#ibcon#ireg 7 cls_cnt 0 2006.224.07:56:40.35#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.224.07:56:40.47#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.224.07:56:40.47#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.224.07:56:40.47#ibcon#enter wrdev, iclass 36, count 0 2006.224.07:56:40.47#ibcon#first serial, iclass 36, count 0 2006.224.07:56:40.47#ibcon#enter sib2, iclass 36, count 0 2006.224.07:56:40.47#ibcon#flushed, iclass 36, count 0 2006.224.07:56:40.47#ibcon#about to write, iclass 36, count 0 2006.224.07:56:40.47#ibcon#wrote, iclass 36, count 0 2006.224.07:56:40.47#ibcon#about to read 3, iclass 36, count 0 2006.224.07:56:40.49#ibcon#read 3, iclass 36, count 0 2006.224.07:56:40.49#ibcon#about to read 4, iclass 36, count 0 2006.224.07:56:40.49#ibcon#read 4, iclass 36, count 0 2006.224.07:56:40.49#ibcon#about to read 5, iclass 36, count 0 2006.224.07:56:40.49#ibcon#read 5, iclass 36, count 0 2006.224.07:56:40.49#ibcon#about to read 6, iclass 36, count 0 2006.224.07:56:40.49#ibcon#read 6, iclass 36, count 0 2006.224.07:56:40.49#ibcon#end of sib2, iclass 36, count 0 2006.224.07:56:40.49#ibcon#*mode == 0, iclass 36, count 0 2006.224.07:56:40.49#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.224.07:56:40.49#ibcon#[25=USB\r\n] 2006.224.07:56:40.49#ibcon#*before write, iclass 36, count 0 2006.224.07:56:40.49#ibcon#enter sib2, iclass 36, count 0 2006.224.07:56:40.49#ibcon#flushed, iclass 36, count 0 2006.224.07:56:40.49#ibcon#about to write, iclass 36, count 0 2006.224.07:56:40.49#ibcon#wrote, iclass 36, count 0 2006.224.07:56:40.49#ibcon#about to read 3, iclass 36, count 0 2006.224.07:56:40.52#ibcon#read 3, iclass 36, count 0 2006.224.07:56:40.52#ibcon#about to read 4, iclass 36, count 0 2006.224.07:56:40.52#ibcon#read 4, iclass 36, count 0 2006.224.07:56:40.52#ibcon#about to read 5, iclass 36, count 0 2006.224.07:56:40.52#ibcon#read 5, iclass 36, count 0 2006.224.07:56:40.52#ibcon#about to read 6, iclass 36, count 0 2006.224.07:56:40.52#ibcon#read 6, iclass 36, count 0 2006.224.07:56:40.52#ibcon#end of sib2, iclass 36, count 0 2006.224.07:56:40.52#ibcon#*after write, iclass 36, count 0 2006.224.07:56:40.52#ibcon#*before return 0, iclass 36, count 0 2006.224.07:56:40.52#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.224.07:56:40.52#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.224.07:56:40.52#ibcon#about to clear, iclass 36 cls_cnt 0 2006.224.07:56:40.52#ibcon#cleared, iclass 36 cls_cnt 0 2006.224.07:56:40.52$vc4f8/vblo=1,632.99 2006.224.07:56:40.52#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.224.07:56:40.52#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.224.07:56:40.52#ibcon#ireg 17 cls_cnt 0 2006.224.07:56:40.52#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.224.07:56:40.52#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.224.07:56:40.52#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.224.07:56:40.52#ibcon#enter wrdev, iclass 38, count 0 2006.224.07:56:40.52#ibcon#first serial, iclass 38, count 0 2006.224.07:56:40.52#ibcon#enter sib2, iclass 38, count 0 2006.224.07:56:40.52#ibcon#flushed, iclass 38, count 0 2006.224.07:56:40.52#ibcon#about to write, iclass 38, count 0 2006.224.07:56:40.52#ibcon#wrote, iclass 38, count 0 2006.224.07:56:40.52#ibcon#about to read 3, iclass 38, count 0 2006.224.07:56:40.55#ibcon#read 3, iclass 38, count 0 2006.224.07:56:40.55#ibcon#about to read 4, iclass 38, count 0 2006.224.07:56:40.55#ibcon#read 4, iclass 38, count 0 2006.224.07:56:40.55#ibcon#about to read 5, iclass 38, count 0 2006.224.07:56:40.55#ibcon#read 5, iclass 38, count 0 2006.224.07:56:40.55#ibcon#about to read 6, iclass 38, count 0 2006.224.07:56:40.55#ibcon#read 6, iclass 38, count 0 2006.224.07:56:40.55#ibcon#end of sib2, iclass 38, count 0 2006.224.07:56:40.55#ibcon#*mode == 0, iclass 38, count 0 2006.224.07:56:40.55#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.224.07:56:40.55#ibcon#[28=FRQ=01,632.99\r\n] 2006.224.07:56:40.55#ibcon#*before write, iclass 38, count 0 2006.224.07:56:40.55#ibcon#enter sib2, iclass 38, count 0 2006.224.07:56:40.55#ibcon#flushed, iclass 38, count 0 2006.224.07:56:40.55#ibcon#about to write, iclass 38, count 0 2006.224.07:56:40.55#ibcon#wrote, iclass 38, count 0 2006.224.07:56:40.55#ibcon#about to read 3, iclass 38, count 0 2006.224.07:56:40.59#ibcon#read 3, iclass 38, count 0 2006.224.07:56:40.59#ibcon#about to read 4, iclass 38, count 0 2006.224.07:56:40.59#ibcon#read 4, iclass 38, count 0 2006.224.07:56:40.59#ibcon#about to read 5, iclass 38, count 0 2006.224.07:56:40.59#ibcon#read 5, iclass 38, count 0 2006.224.07:56:40.59#ibcon#about to read 6, iclass 38, count 0 2006.224.07:56:40.59#ibcon#read 6, iclass 38, count 0 2006.224.07:56:40.59#ibcon#end of sib2, iclass 38, count 0 2006.224.07:56:40.59#ibcon#*after write, iclass 38, count 0 2006.224.07:56:40.59#ibcon#*before return 0, iclass 38, count 0 2006.224.07:56:40.59#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.224.07:56:40.59#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.224.07:56:40.59#ibcon#about to clear, iclass 38 cls_cnt 0 2006.224.07:56:40.59#ibcon#cleared, iclass 38 cls_cnt 0 2006.224.07:56:40.59$vc4f8/vb=1,4 2006.224.07:56:40.59#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.224.07:56:40.59#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.224.07:56:40.59#ibcon#ireg 11 cls_cnt 2 2006.224.07:56:40.59#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.224.07:56:40.59#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.224.07:56:40.59#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.224.07:56:40.59#ibcon#enter wrdev, iclass 40, count 2 2006.224.07:56:40.59#ibcon#first serial, iclass 40, count 2 2006.224.07:56:40.59#ibcon#enter sib2, iclass 40, count 2 2006.224.07:56:40.59#ibcon#flushed, iclass 40, count 2 2006.224.07:56:40.59#ibcon#about to write, iclass 40, count 2 2006.224.07:56:40.59#ibcon#wrote, iclass 40, count 2 2006.224.07:56:40.59#ibcon#about to read 3, iclass 40, count 2 2006.224.07:56:40.61#ibcon#read 3, iclass 40, count 2 2006.224.07:56:40.61#ibcon#about to read 4, iclass 40, count 2 2006.224.07:56:40.61#ibcon#read 4, iclass 40, count 2 2006.224.07:56:40.61#ibcon#about to read 5, iclass 40, count 2 2006.224.07:56:40.61#ibcon#read 5, iclass 40, count 2 2006.224.07:56:40.61#ibcon#about to read 6, iclass 40, count 2 2006.224.07:56:40.61#ibcon#read 6, iclass 40, count 2 2006.224.07:56:40.61#ibcon#end of sib2, iclass 40, count 2 2006.224.07:56:40.61#ibcon#*mode == 0, iclass 40, count 2 2006.224.07:56:40.61#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.224.07:56:40.61#ibcon#[27=AT01-04\r\n] 2006.224.07:56:40.61#ibcon#*before write, iclass 40, count 2 2006.224.07:56:40.61#ibcon#enter sib2, iclass 40, count 2 2006.224.07:56:40.61#ibcon#flushed, iclass 40, count 2 2006.224.07:56:40.61#ibcon#about to write, iclass 40, count 2 2006.224.07:56:40.61#ibcon#wrote, iclass 40, count 2 2006.224.07:56:40.61#ibcon#about to read 3, iclass 40, count 2 2006.224.07:56:40.64#ibcon#read 3, iclass 40, count 2 2006.224.07:56:40.64#ibcon#about to read 4, iclass 40, count 2 2006.224.07:56:40.64#ibcon#read 4, iclass 40, count 2 2006.224.07:56:40.64#ibcon#about to read 5, iclass 40, count 2 2006.224.07:56:40.64#ibcon#read 5, iclass 40, count 2 2006.224.07:56:40.64#ibcon#about to read 6, iclass 40, count 2 2006.224.07:56:40.64#ibcon#read 6, iclass 40, count 2 2006.224.07:56:40.64#ibcon#end of sib2, iclass 40, count 2 2006.224.07:56:40.64#ibcon#*after write, iclass 40, count 2 2006.224.07:56:40.64#ibcon#*before return 0, iclass 40, count 2 2006.224.07:56:40.64#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.224.07:56:40.64#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.224.07:56:40.64#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.224.07:56:40.64#ibcon#ireg 7 cls_cnt 0 2006.224.07:56:40.64#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.224.07:56:40.76#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.224.07:56:40.76#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.224.07:56:40.76#ibcon#enter wrdev, iclass 40, count 0 2006.224.07:56:40.76#ibcon#first serial, iclass 40, count 0 2006.224.07:56:40.76#ibcon#enter sib2, iclass 40, count 0 2006.224.07:56:40.76#ibcon#flushed, iclass 40, count 0 2006.224.07:56:40.76#ibcon#about to write, iclass 40, count 0 2006.224.07:56:40.76#ibcon#wrote, iclass 40, count 0 2006.224.07:56:40.76#ibcon#about to read 3, iclass 40, count 0 2006.224.07:56:40.78#ibcon#read 3, iclass 40, count 0 2006.224.07:56:40.78#ibcon#about to read 4, iclass 40, count 0 2006.224.07:56:40.78#ibcon#read 4, iclass 40, count 0 2006.224.07:56:40.78#ibcon#about to read 5, iclass 40, count 0 2006.224.07:56:40.78#ibcon#read 5, iclass 40, count 0 2006.224.07:56:40.78#ibcon#about to read 6, iclass 40, count 0 2006.224.07:56:40.78#ibcon#read 6, iclass 40, count 0 2006.224.07:56:40.78#ibcon#end of sib2, iclass 40, count 0 2006.224.07:56:40.78#ibcon#*mode == 0, iclass 40, count 0 2006.224.07:56:40.78#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.224.07:56:40.78#ibcon#[27=USB\r\n] 2006.224.07:56:40.78#ibcon#*before write, iclass 40, count 0 2006.224.07:56:40.78#ibcon#enter sib2, iclass 40, count 0 2006.224.07:56:40.78#ibcon#flushed, iclass 40, count 0 2006.224.07:56:40.78#ibcon#about to write, iclass 40, count 0 2006.224.07:56:40.78#ibcon#wrote, iclass 40, count 0 2006.224.07:56:40.78#ibcon#about to read 3, iclass 40, count 0 2006.224.07:56:40.81#ibcon#read 3, iclass 40, count 0 2006.224.07:56:40.81#ibcon#about to read 4, iclass 40, count 0 2006.224.07:56:40.81#ibcon#read 4, iclass 40, count 0 2006.224.07:56:40.81#ibcon#about to read 5, iclass 40, count 0 2006.224.07:56:40.81#ibcon#read 5, iclass 40, count 0 2006.224.07:56:40.81#ibcon#about to read 6, iclass 40, count 0 2006.224.07:56:40.81#ibcon#read 6, iclass 40, count 0 2006.224.07:56:40.81#ibcon#end of sib2, iclass 40, count 0 2006.224.07:56:40.81#ibcon#*after write, iclass 40, count 0 2006.224.07:56:40.81#ibcon#*before return 0, iclass 40, count 0 2006.224.07:56:40.81#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.224.07:56:40.81#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.224.07:56:40.81#ibcon#about to clear, iclass 40 cls_cnt 0 2006.224.07:56:40.81#ibcon#cleared, iclass 40 cls_cnt 0 2006.224.07:56:40.81$vc4f8/vblo=2,640.99 2006.224.07:56:40.81#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.224.07:56:40.81#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.224.07:56:40.81#ibcon#ireg 17 cls_cnt 0 2006.224.07:56:40.81#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.224.07:56:40.81#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.224.07:56:40.81#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.224.07:56:40.81#ibcon#enter wrdev, iclass 4, count 0 2006.224.07:56:40.81#ibcon#first serial, iclass 4, count 0 2006.224.07:56:40.81#ibcon#enter sib2, iclass 4, count 0 2006.224.07:56:40.81#ibcon#flushed, iclass 4, count 0 2006.224.07:56:40.81#ibcon#about to write, iclass 4, count 0 2006.224.07:56:40.81#ibcon#wrote, iclass 4, count 0 2006.224.07:56:40.81#ibcon#about to read 3, iclass 4, count 0 2006.224.07:56:40.83#ibcon#read 3, iclass 4, count 0 2006.224.07:56:40.83#ibcon#about to read 4, iclass 4, count 0 2006.224.07:56:40.83#ibcon#read 4, iclass 4, count 0 2006.224.07:56:40.83#ibcon#about to read 5, iclass 4, count 0 2006.224.07:56:40.83#ibcon#read 5, iclass 4, count 0 2006.224.07:56:40.83#ibcon#about to read 6, iclass 4, count 0 2006.224.07:56:40.83#ibcon#read 6, iclass 4, count 0 2006.224.07:56:40.83#ibcon#end of sib2, iclass 4, count 0 2006.224.07:56:40.83#ibcon#*mode == 0, iclass 4, count 0 2006.224.07:56:40.83#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.224.07:56:40.83#ibcon#[28=FRQ=02,640.99\r\n] 2006.224.07:56:40.83#ibcon#*before write, iclass 4, count 0 2006.224.07:56:40.83#ibcon#enter sib2, iclass 4, count 0 2006.224.07:56:40.83#ibcon#flushed, iclass 4, count 0 2006.224.07:56:40.83#ibcon#about to write, iclass 4, count 0 2006.224.07:56:40.83#ibcon#wrote, iclass 4, count 0 2006.224.07:56:40.83#ibcon#about to read 3, iclass 4, count 0 2006.224.07:56:40.87#ibcon#read 3, iclass 4, count 0 2006.224.07:56:40.87#ibcon#about to read 4, iclass 4, count 0 2006.224.07:56:40.87#ibcon#read 4, iclass 4, count 0 2006.224.07:56:40.87#ibcon#about to read 5, iclass 4, count 0 2006.224.07:56:40.87#ibcon#read 5, iclass 4, count 0 2006.224.07:56:40.87#ibcon#about to read 6, iclass 4, count 0 2006.224.07:56:40.87#ibcon#read 6, iclass 4, count 0 2006.224.07:56:40.87#ibcon#end of sib2, iclass 4, count 0 2006.224.07:56:40.87#ibcon#*after write, iclass 4, count 0 2006.224.07:56:40.87#ibcon#*before return 0, iclass 4, count 0 2006.224.07:56:40.87#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.224.07:56:40.87#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.224.07:56:40.87#ibcon#about to clear, iclass 4 cls_cnt 0 2006.224.07:56:40.87#ibcon#cleared, iclass 4 cls_cnt 0 2006.224.07:56:40.87$vc4f8/vb=2,4 2006.224.07:56:40.87#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.224.07:56:40.87#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.224.07:56:40.87#ibcon#ireg 11 cls_cnt 2 2006.224.07:56:40.87#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.224.07:56:40.93#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.224.07:56:40.93#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.224.07:56:40.93#ibcon#enter wrdev, iclass 6, count 2 2006.224.07:56:40.93#ibcon#first serial, iclass 6, count 2 2006.224.07:56:40.93#ibcon#enter sib2, iclass 6, count 2 2006.224.07:56:40.93#ibcon#flushed, iclass 6, count 2 2006.224.07:56:40.93#ibcon#about to write, iclass 6, count 2 2006.224.07:56:40.93#ibcon#wrote, iclass 6, count 2 2006.224.07:56:40.93#ibcon#about to read 3, iclass 6, count 2 2006.224.07:56:40.95#ibcon#read 3, iclass 6, count 2 2006.224.07:56:40.95#ibcon#about to read 4, iclass 6, count 2 2006.224.07:56:40.95#ibcon#read 4, iclass 6, count 2 2006.224.07:56:40.95#ibcon#about to read 5, iclass 6, count 2 2006.224.07:56:40.95#ibcon#read 5, iclass 6, count 2 2006.224.07:56:40.95#ibcon#about to read 6, iclass 6, count 2 2006.224.07:56:40.95#ibcon#read 6, iclass 6, count 2 2006.224.07:56:40.95#ibcon#end of sib2, iclass 6, count 2 2006.224.07:56:40.95#ibcon#*mode == 0, iclass 6, count 2 2006.224.07:56:40.95#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.224.07:56:40.95#ibcon#[27=AT02-04\r\n] 2006.224.07:56:40.95#ibcon#*before write, iclass 6, count 2 2006.224.07:56:40.95#ibcon#enter sib2, iclass 6, count 2 2006.224.07:56:40.95#ibcon#flushed, iclass 6, count 2 2006.224.07:56:40.95#ibcon#about to write, iclass 6, count 2 2006.224.07:56:40.95#ibcon#wrote, iclass 6, count 2 2006.224.07:56:40.95#ibcon#about to read 3, iclass 6, count 2 2006.224.07:56:40.98#ibcon#read 3, iclass 6, count 2 2006.224.07:56:40.98#ibcon#about to read 4, iclass 6, count 2 2006.224.07:56:40.98#ibcon#read 4, iclass 6, count 2 2006.224.07:56:40.98#ibcon#about to read 5, iclass 6, count 2 2006.224.07:56:40.98#ibcon#read 5, iclass 6, count 2 2006.224.07:56:40.98#ibcon#about to read 6, iclass 6, count 2 2006.224.07:56:40.98#ibcon#read 6, iclass 6, count 2 2006.224.07:56:40.98#ibcon#end of sib2, iclass 6, count 2 2006.224.07:56:40.98#ibcon#*after write, iclass 6, count 2 2006.224.07:56:40.98#ibcon#*before return 0, iclass 6, count 2 2006.224.07:56:40.98#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.224.07:56:40.98#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.224.07:56:40.98#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.224.07:56:40.98#ibcon#ireg 7 cls_cnt 0 2006.224.07:56:40.98#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.224.07:56:41.03#abcon#<5=/04 1.2 2.1 23.631001004.0\r\n> 2006.224.07:56:41.05#abcon#{5=INTERFACE CLEAR} 2006.224.07:56:41.10#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.224.07:56:41.10#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.224.07:56:41.10#ibcon#enter wrdev, iclass 6, count 0 2006.224.07:56:41.10#ibcon#first serial, iclass 6, count 0 2006.224.07:56:41.10#ibcon#enter sib2, iclass 6, count 0 2006.224.07:56:41.10#ibcon#flushed, iclass 6, count 0 2006.224.07:56:41.10#ibcon#about to write, iclass 6, count 0 2006.224.07:56:41.10#ibcon#wrote, iclass 6, count 0 2006.224.07:56:41.10#ibcon#about to read 3, iclass 6, count 0 2006.224.07:56:41.11#abcon#[5=S1D000X0/0*\r\n] 2006.224.07:56:41.12#ibcon#read 3, iclass 6, count 0 2006.224.07:56:41.12#ibcon#about to read 4, iclass 6, count 0 2006.224.07:56:41.12#ibcon#read 4, iclass 6, count 0 2006.224.07:56:41.12#ibcon#about to read 5, iclass 6, count 0 2006.224.07:56:41.12#ibcon#read 5, iclass 6, count 0 2006.224.07:56:41.12#ibcon#about to read 6, iclass 6, count 0 2006.224.07:56:41.12#ibcon#read 6, iclass 6, count 0 2006.224.07:56:41.12#ibcon#end of sib2, iclass 6, count 0 2006.224.07:56:41.12#ibcon#*mode == 0, iclass 6, count 0 2006.224.07:56:41.12#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.224.07:56:41.12#ibcon#[27=USB\r\n] 2006.224.07:56:41.12#ibcon#*before write, iclass 6, count 0 2006.224.07:56:41.12#ibcon#enter sib2, iclass 6, count 0 2006.224.07:56:41.12#ibcon#flushed, iclass 6, count 0 2006.224.07:56:41.12#ibcon#about to write, iclass 6, count 0 2006.224.07:56:41.12#ibcon#wrote, iclass 6, count 0 2006.224.07:56:41.12#ibcon#about to read 3, iclass 6, count 0 2006.224.07:56:41.15#ibcon#read 3, iclass 6, count 0 2006.224.07:56:41.15#ibcon#about to read 4, iclass 6, count 0 2006.224.07:56:41.15#ibcon#read 4, iclass 6, count 0 2006.224.07:56:41.15#ibcon#about to read 5, iclass 6, count 0 2006.224.07:56:41.15#ibcon#read 5, iclass 6, count 0 2006.224.07:56:41.15#ibcon#about to read 6, iclass 6, count 0 2006.224.07:56:41.15#ibcon#read 6, iclass 6, count 0 2006.224.07:56:41.15#ibcon#end of sib2, iclass 6, count 0 2006.224.07:56:41.15#ibcon#*after write, iclass 6, count 0 2006.224.07:56:41.15#ibcon#*before return 0, iclass 6, count 0 2006.224.07:56:41.15#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.224.07:56:41.15#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.224.07:56:41.15#ibcon#about to clear, iclass 6 cls_cnt 0 2006.224.07:56:41.15#ibcon#cleared, iclass 6 cls_cnt 0 2006.224.07:56:41.15$vc4f8/vblo=3,656.99 2006.224.07:56:41.15#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.224.07:56:41.15#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.224.07:56:41.15#ibcon#ireg 17 cls_cnt 0 2006.224.07:56:41.15#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.224.07:56:41.15#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.224.07:56:41.15#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.224.07:56:41.15#ibcon#enter wrdev, iclass 14, count 0 2006.224.07:56:41.15#ibcon#first serial, iclass 14, count 0 2006.224.07:56:41.15#ibcon#enter sib2, iclass 14, count 0 2006.224.07:56:41.15#ibcon#flushed, iclass 14, count 0 2006.224.07:56:41.15#ibcon#about to write, iclass 14, count 0 2006.224.07:56:41.15#ibcon#wrote, iclass 14, count 0 2006.224.07:56:41.15#ibcon#about to read 3, iclass 14, count 0 2006.224.07:56:41.17#ibcon#read 3, iclass 14, count 0 2006.224.07:56:41.17#ibcon#about to read 4, iclass 14, count 0 2006.224.07:56:41.17#ibcon#read 4, iclass 14, count 0 2006.224.07:56:41.17#ibcon#about to read 5, iclass 14, count 0 2006.224.07:56:41.17#ibcon#read 5, iclass 14, count 0 2006.224.07:56:41.17#ibcon#about to read 6, iclass 14, count 0 2006.224.07:56:41.17#ibcon#read 6, iclass 14, count 0 2006.224.07:56:41.17#ibcon#end of sib2, iclass 14, count 0 2006.224.07:56:41.17#ibcon#*mode == 0, iclass 14, count 0 2006.224.07:56:41.17#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.224.07:56:41.17#ibcon#[28=FRQ=03,656.99\r\n] 2006.224.07:56:41.17#ibcon#*before write, iclass 14, count 0 2006.224.07:56:41.17#ibcon#enter sib2, iclass 14, count 0 2006.224.07:56:41.17#ibcon#flushed, iclass 14, count 0 2006.224.07:56:41.17#ibcon#about to write, iclass 14, count 0 2006.224.07:56:41.17#ibcon#wrote, iclass 14, count 0 2006.224.07:56:41.17#ibcon#about to read 3, iclass 14, count 0 2006.224.07:56:41.21#ibcon#read 3, iclass 14, count 0 2006.224.07:56:41.21#ibcon#about to read 4, iclass 14, count 0 2006.224.07:56:41.21#ibcon#read 4, iclass 14, count 0 2006.224.07:56:41.21#ibcon#about to read 5, iclass 14, count 0 2006.224.07:56:41.21#ibcon#read 5, iclass 14, count 0 2006.224.07:56:41.21#ibcon#about to read 6, iclass 14, count 0 2006.224.07:56:41.21#ibcon#read 6, iclass 14, count 0 2006.224.07:56:41.21#ibcon#end of sib2, iclass 14, count 0 2006.224.07:56:41.21#ibcon#*after write, iclass 14, count 0 2006.224.07:56:41.21#ibcon#*before return 0, iclass 14, count 0 2006.224.07:56:41.21#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.224.07:56:41.21#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.224.07:56:41.21#ibcon#about to clear, iclass 14 cls_cnt 0 2006.224.07:56:41.21#ibcon#cleared, iclass 14 cls_cnt 0 2006.224.07:56:41.21$vc4f8/vb=3,4 2006.224.07:56:41.21#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.224.07:56:41.21#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.224.07:56:41.21#ibcon#ireg 11 cls_cnt 2 2006.224.07:56:41.21#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.224.07:56:41.27#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.224.07:56:41.27#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.224.07:56:41.27#ibcon#enter wrdev, iclass 16, count 2 2006.224.07:56:41.27#ibcon#first serial, iclass 16, count 2 2006.224.07:56:41.27#ibcon#enter sib2, iclass 16, count 2 2006.224.07:56:41.27#ibcon#flushed, iclass 16, count 2 2006.224.07:56:41.27#ibcon#about to write, iclass 16, count 2 2006.224.07:56:41.27#ibcon#wrote, iclass 16, count 2 2006.224.07:56:41.27#ibcon#about to read 3, iclass 16, count 2 2006.224.07:56:41.29#ibcon#read 3, iclass 16, count 2 2006.224.07:56:41.29#ibcon#about to read 4, iclass 16, count 2 2006.224.07:56:41.29#ibcon#read 4, iclass 16, count 2 2006.224.07:56:41.29#ibcon#about to read 5, iclass 16, count 2 2006.224.07:56:41.29#ibcon#read 5, iclass 16, count 2 2006.224.07:56:41.29#ibcon#about to read 6, iclass 16, count 2 2006.224.07:56:41.29#ibcon#read 6, iclass 16, count 2 2006.224.07:56:41.29#ibcon#end of sib2, iclass 16, count 2 2006.224.07:56:41.29#ibcon#*mode == 0, iclass 16, count 2 2006.224.07:56:41.29#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.224.07:56:41.29#ibcon#[27=AT03-04\r\n] 2006.224.07:56:41.29#ibcon#*before write, iclass 16, count 2 2006.224.07:56:41.29#ibcon#enter sib2, iclass 16, count 2 2006.224.07:56:41.29#ibcon#flushed, iclass 16, count 2 2006.224.07:56:41.29#ibcon#about to write, iclass 16, count 2 2006.224.07:56:41.29#ibcon#wrote, iclass 16, count 2 2006.224.07:56:41.29#ibcon#about to read 3, iclass 16, count 2 2006.224.07:56:41.32#ibcon#read 3, iclass 16, count 2 2006.224.07:56:41.32#ibcon#about to read 4, iclass 16, count 2 2006.224.07:56:41.32#ibcon#read 4, iclass 16, count 2 2006.224.07:56:41.32#ibcon#about to read 5, iclass 16, count 2 2006.224.07:56:41.32#ibcon#read 5, iclass 16, count 2 2006.224.07:56:41.32#ibcon#about to read 6, iclass 16, count 2 2006.224.07:56:41.32#ibcon#read 6, iclass 16, count 2 2006.224.07:56:41.32#ibcon#end of sib2, iclass 16, count 2 2006.224.07:56:41.32#ibcon#*after write, iclass 16, count 2 2006.224.07:56:41.32#ibcon#*before return 0, iclass 16, count 2 2006.224.07:56:41.32#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.224.07:56:41.32#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.224.07:56:41.32#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.224.07:56:41.32#ibcon#ireg 7 cls_cnt 0 2006.224.07:56:41.32#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.224.07:56:41.44#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.224.07:56:41.44#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.224.07:56:41.44#ibcon#enter wrdev, iclass 16, count 0 2006.224.07:56:41.44#ibcon#first serial, iclass 16, count 0 2006.224.07:56:41.44#ibcon#enter sib2, iclass 16, count 0 2006.224.07:56:41.44#ibcon#flushed, iclass 16, count 0 2006.224.07:56:41.44#ibcon#about to write, iclass 16, count 0 2006.224.07:56:41.44#ibcon#wrote, iclass 16, count 0 2006.224.07:56:41.44#ibcon#about to read 3, iclass 16, count 0 2006.224.07:56:41.46#ibcon#read 3, iclass 16, count 0 2006.224.07:56:41.46#ibcon#about to read 4, iclass 16, count 0 2006.224.07:56:41.46#ibcon#read 4, iclass 16, count 0 2006.224.07:56:41.46#ibcon#about to read 5, iclass 16, count 0 2006.224.07:56:41.46#ibcon#read 5, iclass 16, count 0 2006.224.07:56:41.46#ibcon#about to read 6, iclass 16, count 0 2006.224.07:56:41.46#ibcon#read 6, iclass 16, count 0 2006.224.07:56:41.46#ibcon#end of sib2, iclass 16, count 0 2006.224.07:56:41.46#ibcon#*mode == 0, iclass 16, count 0 2006.224.07:56:41.46#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.224.07:56:41.46#ibcon#[27=USB\r\n] 2006.224.07:56:41.46#ibcon#*before write, iclass 16, count 0 2006.224.07:56:41.46#ibcon#enter sib2, iclass 16, count 0 2006.224.07:56:41.46#ibcon#flushed, iclass 16, count 0 2006.224.07:56:41.46#ibcon#about to write, iclass 16, count 0 2006.224.07:56:41.46#ibcon#wrote, iclass 16, count 0 2006.224.07:56:41.46#ibcon#about to read 3, iclass 16, count 0 2006.224.07:56:41.49#ibcon#read 3, iclass 16, count 0 2006.224.07:56:41.49#ibcon#about to read 4, iclass 16, count 0 2006.224.07:56:41.49#ibcon#read 4, iclass 16, count 0 2006.224.07:56:41.49#ibcon#about to read 5, iclass 16, count 0 2006.224.07:56:41.49#ibcon#read 5, iclass 16, count 0 2006.224.07:56:41.49#ibcon#about to read 6, iclass 16, count 0 2006.224.07:56:41.49#ibcon#read 6, iclass 16, count 0 2006.224.07:56:41.49#ibcon#end of sib2, iclass 16, count 0 2006.224.07:56:41.49#ibcon#*after write, iclass 16, count 0 2006.224.07:56:41.49#ibcon#*before return 0, iclass 16, count 0 2006.224.07:56:41.49#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.224.07:56:41.49#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.224.07:56:41.49#ibcon#about to clear, iclass 16 cls_cnt 0 2006.224.07:56:41.49#ibcon#cleared, iclass 16 cls_cnt 0 2006.224.07:56:41.49$vc4f8/vblo=4,712.99 2006.224.07:56:41.49#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.224.07:56:41.49#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.224.07:56:41.49#ibcon#ireg 17 cls_cnt 0 2006.224.07:56:41.49#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.224.07:56:41.49#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.224.07:56:41.49#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.224.07:56:41.49#ibcon#enter wrdev, iclass 18, count 0 2006.224.07:56:41.49#ibcon#first serial, iclass 18, count 0 2006.224.07:56:41.49#ibcon#enter sib2, iclass 18, count 0 2006.224.07:56:41.49#ibcon#flushed, iclass 18, count 0 2006.224.07:56:41.49#ibcon#about to write, iclass 18, count 0 2006.224.07:56:41.49#ibcon#wrote, iclass 18, count 0 2006.224.07:56:41.49#ibcon#about to read 3, iclass 18, count 0 2006.224.07:56:41.51#ibcon#read 3, iclass 18, count 0 2006.224.07:56:41.51#ibcon#about to read 4, iclass 18, count 0 2006.224.07:56:41.51#ibcon#read 4, iclass 18, count 0 2006.224.07:56:41.51#ibcon#about to read 5, iclass 18, count 0 2006.224.07:56:41.51#ibcon#read 5, iclass 18, count 0 2006.224.07:56:41.51#ibcon#about to read 6, iclass 18, count 0 2006.224.07:56:41.51#ibcon#read 6, iclass 18, count 0 2006.224.07:56:41.51#ibcon#end of sib2, iclass 18, count 0 2006.224.07:56:41.51#ibcon#*mode == 0, iclass 18, count 0 2006.224.07:56:41.51#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.224.07:56:41.51#ibcon#[28=FRQ=04,712.99\r\n] 2006.224.07:56:41.51#ibcon#*before write, iclass 18, count 0 2006.224.07:56:41.51#ibcon#enter sib2, iclass 18, count 0 2006.224.07:56:41.51#ibcon#flushed, iclass 18, count 0 2006.224.07:56:41.51#ibcon#about to write, iclass 18, count 0 2006.224.07:56:41.51#ibcon#wrote, iclass 18, count 0 2006.224.07:56:41.51#ibcon#about to read 3, iclass 18, count 0 2006.224.07:56:41.55#ibcon#read 3, iclass 18, count 0 2006.224.07:56:41.55#ibcon#about to read 4, iclass 18, count 0 2006.224.07:56:41.55#ibcon#read 4, iclass 18, count 0 2006.224.07:56:41.55#ibcon#about to read 5, iclass 18, count 0 2006.224.07:56:41.55#ibcon#read 5, iclass 18, count 0 2006.224.07:56:41.55#ibcon#about to read 6, iclass 18, count 0 2006.224.07:56:41.55#ibcon#read 6, iclass 18, count 0 2006.224.07:56:41.55#ibcon#end of sib2, iclass 18, count 0 2006.224.07:56:41.55#ibcon#*after write, iclass 18, count 0 2006.224.07:56:41.55#ibcon#*before return 0, iclass 18, count 0 2006.224.07:56:41.55#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.224.07:56:41.55#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.224.07:56:41.55#ibcon#about to clear, iclass 18 cls_cnt 0 2006.224.07:56:41.55#ibcon#cleared, iclass 18 cls_cnt 0 2006.224.07:56:41.55$vc4f8/vb=4,4 2006.224.07:56:41.55#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.224.07:56:41.55#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.224.07:56:41.55#ibcon#ireg 11 cls_cnt 2 2006.224.07:56:41.55#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.224.07:56:41.61#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.224.07:56:41.61#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.224.07:56:41.61#ibcon#enter wrdev, iclass 20, count 2 2006.224.07:56:41.61#ibcon#first serial, iclass 20, count 2 2006.224.07:56:41.61#ibcon#enter sib2, iclass 20, count 2 2006.224.07:56:41.61#ibcon#flushed, iclass 20, count 2 2006.224.07:56:41.61#ibcon#about to write, iclass 20, count 2 2006.224.07:56:41.61#ibcon#wrote, iclass 20, count 2 2006.224.07:56:41.61#ibcon#about to read 3, iclass 20, count 2 2006.224.07:56:41.63#ibcon#read 3, iclass 20, count 2 2006.224.07:56:41.63#ibcon#about to read 4, iclass 20, count 2 2006.224.07:56:41.63#ibcon#read 4, iclass 20, count 2 2006.224.07:56:41.63#ibcon#about to read 5, iclass 20, count 2 2006.224.07:56:41.63#ibcon#read 5, iclass 20, count 2 2006.224.07:56:41.63#ibcon#about to read 6, iclass 20, count 2 2006.224.07:56:41.63#ibcon#read 6, iclass 20, count 2 2006.224.07:56:41.63#ibcon#end of sib2, iclass 20, count 2 2006.224.07:56:41.63#ibcon#*mode == 0, iclass 20, count 2 2006.224.07:56:41.63#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.224.07:56:41.63#ibcon#[27=AT04-04\r\n] 2006.224.07:56:41.63#ibcon#*before write, iclass 20, count 2 2006.224.07:56:41.63#ibcon#enter sib2, iclass 20, count 2 2006.224.07:56:41.63#ibcon#flushed, iclass 20, count 2 2006.224.07:56:41.63#ibcon#about to write, iclass 20, count 2 2006.224.07:56:41.63#ibcon#wrote, iclass 20, count 2 2006.224.07:56:41.63#ibcon#about to read 3, iclass 20, count 2 2006.224.07:56:41.66#ibcon#read 3, iclass 20, count 2 2006.224.07:56:41.66#ibcon#about to read 4, iclass 20, count 2 2006.224.07:56:41.66#ibcon#read 4, iclass 20, count 2 2006.224.07:56:41.66#ibcon#about to read 5, iclass 20, count 2 2006.224.07:56:41.66#ibcon#read 5, iclass 20, count 2 2006.224.07:56:41.66#ibcon#about to read 6, iclass 20, count 2 2006.224.07:56:41.66#ibcon#read 6, iclass 20, count 2 2006.224.07:56:41.66#ibcon#end of sib2, iclass 20, count 2 2006.224.07:56:41.66#ibcon#*after write, iclass 20, count 2 2006.224.07:56:41.66#ibcon#*before return 0, iclass 20, count 2 2006.224.07:56:41.66#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.224.07:56:41.66#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.224.07:56:41.66#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.224.07:56:41.66#ibcon#ireg 7 cls_cnt 0 2006.224.07:56:41.66#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.224.07:56:41.78#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.224.07:56:41.78#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.224.07:56:41.78#ibcon#enter wrdev, iclass 20, count 0 2006.224.07:56:41.78#ibcon#first serial, iclass 20, count 0 2006.224.07:56:41.78#ibcon#enter sib2, iclass 20, count 0 2006.224.07:56:41.78#ibcon#flushed, iclass 20, count 0 2006.224.07:56:41.78#ibcon#about to write, iclass 20, count 0 2006.224.07:56:41.78#ibcon#wrote, iclass 20, count 0 2006.224.07:56:41.78#ibcon#about to read 3, iclass 20, count 0 2006.224.07:56:41.80#ibcon#read 3, iclass 20, count 0 2006.224.07:56:41.80#ibcon#about to read 4, iclass 20, count 0 2006.224.07:56:41.80#ibcon#read 4, iclass 20, count 0 2006.224.07:56:41.80#ibcon#about to read 5, iclass 20, count 0 2006.224.07:56:41.80#ibcon#read 5, iclass 20, count 0 2006.224.07:56:41.80#ibcon#about to read 6, iclass 20, count 0 2006.224.07:56:41.80#ibcon#read 6, iclass 20, count 0 2006.224.07:56:41.80#ibcon#end of sib2, iclass 20, count 0 2006.224.07:56:41.80#ibcon#*mode == 0, iclass 20, count 0 2006.224.07:56:41.80#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.224.07:56:41.80#ibcon#[27=USB\r\n] 2006.224.07:56:41.80#ibcon#*before write, iclass 20, count 0 2006.224.07:56:41.80#ibcon#enter sib2, iclass 20, count 0 2006.224.07:56:41.80#ibcon#flushed, iclass 20, count 0 2006.224.07:56:41.80#ibcon#about to write, iclass 20, count 0 2006.224.07:56:41.80#ibcon#wrote, iclass 20, count 0 2006.224.07:56:41.80#ibcon#about to read 3, iclass 20, count 0 2006.224.07:56:41.83#ibcon#read 3, iclass 20, count 0 2006.224.07:56:41.83#ibcon#about to read 4, iclass 20, count 0 2006.224.07:56:41.83#ibcon#read 4, iclass 20, count 0 2006.224.07:56:41.83#ibcon#about to read 5, iclass 20, count 0 2006.224.07:56:41.83#ibcon#read 5, iclass 20, count 0 2006.224.07:56:41.83#ibcon#about to read 6, iclass 20, count 0 2006.224.07:56:41.83#ibcon#read 6, iclass 20, count 0 2006.224.07:56:41.83#ibcon#end of sib2, iclass 20, count 0 2006.224.07:56:41.83#ibcon#*after write, iclass 20, count 0 2006.224.07:56:41.83#ibcon#*before return 0, iclass 20, count 0 2006.224.07:56:41.83#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.224.07:56:41.83#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.224.07:56:41.83#ibcon#about to clear, iclass 20 cls_cnt 0 2006.224.07:56:41.83#ibcon#cleared, iclass 20 cls_cnt 0 2006.224.07:56:41.83$vc4f8/vblo=5,744.99 2006.224.07:56:41.83#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.224.07:56:41.83#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.224.07:56:41.83#ibcon#ireg 17 cls_cnt 0 2006.224.07:56:41.83#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.224.07:56:41.83#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.224.07:56:41.83#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.224.07:56:41.83#ibcon#enter wrdev, iclass 22, count 0 2006.224.07:56:41.83#ibcon#first serial, iclass 22, count 0 2006.224.07:56:41.83#ibcon#enter sib2, iclass 22, count 0 2006.224.07:56:41.83#ibcon#flushed, iclass 22, count 0 2006.224.07:56:41.83#ibcon#about to write, iclass 22, count 0 2006.224.07:56:41.83#ibcon#wrote, iclass 22, count 0 2006.224.07:56:41.83#ibcon#about to read 3, iclass 22, count 0 2006.224.07:56:41.85#ibcon#read 3, iclass 22, count 0 2006.224.07:56:41.85#ibcon#about to read 4, iclass 22, count 0 2006.224.07:56:41.85#ibcon#read 4, iclass 22, count 0 2006.224.07:56:41.85#ibcon#about to read 5, iclass 22, count 0 2006.224.07:56:41.85#ibcon#read 5, iclass 22, count 0 2006.224.07:56:41.85#ibcon#about to read 6, iclass 22, count 0 2006.224.07:56:41.85#ibcon#read 6, iclass 22, count 0 2006.224.07:56:41.85#ibcon#end of sib2, iclass 22, count 0 2006.224.07:56:41.85#ibcon#*mode == 0, iclass 22, count 0 2006.224.07:56:41.85#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.224.07:56:41.85#ibcon#[28=FRQ=05,744.99\r\n] 2006.224.07:56:41.85#ibcon#*before write, iclass 22, count 0 2006.224.07:56:41.85#ibcon#enter sib2, iclass 22, count 0 2006.224.07:56:41.85#ibcon#flushed, iclass 22, count 0 2006.224.07:56:41.85#ibcon#about to write, iclass 22, count 0 2006.224.07:56:41.85#ibcon#wrote, iclass 22, count 0 2006.224.07:56:41.85#ibcon#about to read 3, iclass 22, count 0 2006.224.07:56:41.89#ibcon#read 3, iclass 22, count 0 2006.224.07:56:41.89#ibcon#about to read 4, iclass 22, count 0 2006.224.07:56:41.89#ibcon#read 4, iclass 22, count 0 2006.224.07:56:41.89#ibcon#about to read 5, iclass 22, count 0 2006.224.07:56:41.89#ibcon#read 5, iclass 22, count 0 2006.224.07:56:41.89#ibcon#about to read 6, iclass 22, count 0 2006.224.07:56:41.89#ibcon#read 6, iclass 22, count 0 2006.224.07:56:41.89#ibcon#end of sib2, iclass 22, count 0 2006.224.07:56:41.89#ibcon#*after write, iclass 22, count 0 2006.224.07:56:41.89#ibcon#*before return 0, iclass 22, count 0 2006.224.07:56:41.89#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.224.07:56:41.89#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.224.07:56:41.89#ibcon#about to clear, iclass 22 cls_cnt 0 2006.224.07:56:41.89#ibcon#cleared, iclass 22 cls_cnt 0 2006.224.07:56:41.89$vc4f8/vb=5,4 2006.224.07:56:41.89#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.224.07:56:41.89#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.224.07:56:41.89#ibcon#ireg 11 cls_cnt 2 2006.224.07:56:41.89#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.224.07:56:41.95#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.224.07:56:41.95#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.224.07:56:41.95#ibcon#enter wrdev, iclass 24, count 2 2006.224.07:56:41.95#ibcon#first serial, iclass 24, count 2 2006.224.07:56:41.95#ibcon#enter sib2, iclass 24, count 2 2006.224.07:56:41.95#ibcon#flushed, iclass 24, count 2 2006.224.07:56:41.95#ibcon#about to write, iclass 24, count 2 2006.224.07:56:41.95#ibcon#wrote, iclass 24, count 2 2006.224.07:56:41.95#ibcon#about to read 3, iclass 24, count 2 2006.224.07:56:41.97#ibcon#read 3, iclass 24, count 2 2006.224.07:56:41.97#ibcon#about to read 4, iclass 24, count 2 2006.224.07:56:41.97#ibcon#read 4, iclass 24, count 2 2006.224.07:56:41.97#ibcon#about to read 5, iclass 24, count 2 2006.224.07:56:41.97#ibcon#read 5, iclass 24, count 2 2006.224.07:56:41.97#ibcon#about to read 6, iclass 24, count 2 2006.224.07:56:41.97#ibcon#read 6, iclass 24, count 2 2006.224.07:56:41.97#ibcon#end of sib2, iclass 24, count 2 2006.224.07:56:41.97#ibcon#*mode == 0, iclass 24, count 2 2006.224.07:56:41.97#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.224.07:56:41.97#ibcon#[27=AT05-04\r\n] 2006.224.07:56:41.97#ibcon#*before write, iclass 24, count 2 2006.224.07:56:41.97#ibcon#enter sib2, iclass 24, count 2 2006.224.07:56:41.97#ibcon#flushed, iclass 24, count 2 2006.224.07:56:41.97#ibcon#about to write, iclass 24, count 2 2006.224.07:56:41.97#ibcon#wrote, iclass 24, count 2 2006.224.07:56:41.97#ibcon#about to read 3, iclass 24, count 2 2006.224.07:56:42.00#ibcon#read 3, iclass 24, count 2 2006.224.07:56:42.00#ibcon#about to read 4, iclass 24, count 2 2006.224.07:56:42.00#ibcon#read 4, iclass 24, count 2 2006.224.07:56:42.00#ibcon#about to read 5, iclass 24, count 2 2006.224.07:56:42.00#ibcon#read 5, iclass 24, count 2 2006.224.07:56:42.00#ibcon#about to read 6, iclass 24, count 2 2006.224.07:56:42.00#ibcon#read 6, iclass 24, count 2 2006.224.07:56:42.00#ibcon#end of sib2, iclass 24, count 2 2006.224.07:56:42.00#ibcon#*after write, iclass 24, count 2 2006.224.07:56:42.00#ibcon#*before return 0, iclass 24, count 2 2006.224.07:56:42.00#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.224.07:56:42.00#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.224.07:56:42.00#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.224.07:56:42.00#ibcon#ireg 7 cls_cnt 0 2006.224.07:56:42.00#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.224.07:56:42.12#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.224.07:56:42.12#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.224.07:56:42.12#ibcon#enter wrdev, iclass 24, count 0 2006.224.07:56:42.12#ibcon#first serial, iclass 24, count 0 2006.224.07:56:42.12#ibcon#enter sib2, iclass 24, count 0 2006.224.07:56:42.12#ibcon#flushed, iclass 24, count 0 2006.224.07:56:42.12#ibcon#about to write, iclass 24, count 0 2006.224.07:56:42.12#ibcon#wrote, iclass 24, count 0 2006.224.07:56:42.12#ibcon#about to read 3, iclass 24, count 0 2006.224.07:56:42.14#ibcon#read 3, iclass 24, count 0 2006.224.07:56:42.14#ibcon#about to read 4, iclass 24, count 0 2006.224.07:56:42.14#ibcon#read 4, iclass 24, count 0 2006.224.07:56:42.14#ibcon#about to read 5, iclass 24, count 0 2006.224.07:56:42.14#ibcon#read 5, iclass 24, count 0 2006.224.07:56:42.14#ibcon#about to read 6, iclass 24, count 0 2006.224.07:56:42.14#ibcon#read 6, iclass 24, count 0 2006.224.07:56:42.14#ibcon#end of sib2, iclass 24, count 0 2006.224.07:56:42.14#ibcon#*mode == 0, iclass 24, count 0 2006.224.07:56:42.14#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.224.07:56:42.14#ibcon#[27=USB\r\n] 2006.224.07:56:42.14#ibcon#*before write, iclass 24, count 0 2006.224.07:56:42.14#ibcon#enter sib2, iclass 24, count 0 2006.224.07:56:42.14#ibcon#flushed, iclass 24, count 0 2006.224.07:56:42.14#ibcon#about to write, iclass 24, count 0 2006.224.07:56:42.14#ibcon#wrote, iclass 24, count 0 2006.224.07:56:42.14#ibcon#about to read 3, iclass 24, count 0 2006.224.07:56:42.17#ibcon#read 3, iclass 24, count 0 2006.224.07:56:42.17#ibcon#about to read 4, iclass 24, count 0 2006.224.07:56:42.17#ibcon#read 4, iclass 24, count 0 2006.224.07:56:42.17#ibcon#about to read 5, iclass 24, count 0 2006.224.07:56:42.17#ibcon#read 5, iclass 24, count 0 2006.224.07:56:42.17#ibcon#about to read 6, iclass 24, count 0 2006.224.07:56:42.17#ibcon#read 6, iclass 24, count 0 2006.224.07:56:42.17#ibcon#end of sib2, iclass 24, count 0 2006.224.07:56:42.17#ibcon#*after write, iclass 24, count 0 2006.224.07:56:42.17#ibcon#*before return 0, iclass 24, count 0 2006.224.07:56:42.17#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.224.07:56:42.17#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.224.07:56:42.17#ibcon#about to clear, iclass 24 cls_cnt 0 2006.224.07:56:42.17#ibcon#cleared, iclass 24 cls_cnt 0 2006.224.07:56:42.17$vc4f8/vblo=6,752.99 2006.224.07:56:42.17#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.224.07:56:42.17#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.224.07:56:42.17#ibcon#ireg 17 cls_cnt 0 2006.224.07:56:42.17#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.224.07:56:42.17#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.224.07:56:42.17#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.224.07:56:42.17#ibcon#enter wrdev, iclass 26, count 0 2006.224.07:56:42.17#ibcon#first serial, iclass 26, count 0 2006.224.07:56:42.17#ibcon#enter sib2, iclass 26, count 0 2006.224.07:56:42.17#ibcon#flushed, iclass 26, count 0 2006.224.07:56:42.17#ibcon#about to write, iclass 26, count 0 2006.224.07:56:42.17#ibcon#wrote, iclass 26, count 0 2006.224.07:56:42.17#ibcon#about to read 3, iclass 26, count 0 2006.224.07:56:42.20#ibcon#read 3, iclass 26, count 0 2006.224.07:56:42.20#ibcon#about to read 4, iclass 26, count 0 2006.224.07:56:42.20#ibcon#read 4, iclass 26, count 0 2006.224.07:56:42.20#ibcon#about to read 5, iclass 26, count 0 2006.224.07:56:42.20#ibcon#read 5, iclass 26, count 0 2006.224.07:56:42.20#ibcon#about to read 6, iclass 26, count 0 2006.224.07:56:42.20#ibcon#read 6, iclass 26, count 0 2006.224.07:56:42.20#ibcon#end of sib2, iclass 26, count 0 2006.224.07:56:42.20#ibcon#*mode == 0, iclass 26, count 0 2006.224.07:56:42.20#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.224.07:56:42.20#ibcon#[28=FRQ=06,752.99\r\n] 2006.224.07:56:42.20#ibcon#*before write, iclass 26, count 0 2006.224.07:56:42.20#ibcon#enter sib2, iclass 26, count 0 2006.224.07:56:42.20#ibcon#flushed, iclass 26, count 0 2006.224.07:56:42.20#ibcon#about to write, iclass 26, count 0 2006.224.07:56:42.20#ibcon#wrote, iclass 26, count 0 2006.224.07:56:42.20#ibcon#about to read 3, iclass 26, count 0 2006.224.07:56:42.24#ibcon#read 3, iclass 26, count 0 2006.224.07:56:42.24#ibcon#about to read 4, iclass 26, count 0 2006.224.07:56:42.24#ibcon#read 4, iclass 26, count 0 2006.224.07:56:42.24#ibcon#about to read 5, iclass 26, count 0 2006.224.07:56:42.24#ibcon#read 5, iclass 26, count 0 2006.224.07:56:42.24#ibcon#about to read 6, iclass 26, count 0 2006.224.07:56:42.24#ibcon#read 6, iclass 26, count 0 2006.224.07:56:42.24#ibcon#end of sib2, iclass 26, count 0 2006.224.07:56:42.24#ibcon#*after write, iclass 26, count 0 2006.224.07:56:42.24#ibcon#*before return 0, iclass 26, count 0 2006.224.07:56:42.24#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.224.07:56:42.24#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.224.07:56:42.24#ibcon#about to clear, iclass 26 cls_cnt 0 2006.224.07:56:42.24#ibcon#cleared, iclass 26 cls_cnt 0 2006.224.07:56:42.24$vc4f8/vb=6,4 2006.224.07:56:42.24#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.224.07:56:42.24#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.224.07:56:42.24#ibcon#ireg 11 cls_cnt 2 2006.224.07:56:42.24#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.224.07:56:42.29#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.224.07:56:42.29#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.224.07:56:42.29#ibcon#enter wrdev, iclass 28, count 2 2006.224.07:56:42.29#ibcon#first serial, iclass 28, count 2 2006.224.07:56:42.29#ibcon#enter sib2, iclass 28, count 2 2006.224.07:56:42.29#ibcon#flushed, iclass 28, count 2 2006.224.07:56:42.29#ibcon#about to write, iclass 28, count 2 2006.224.07:56:42.29#ibcon#wrote, iclass 28, count 2 2006.224.07:56:42.29#ibcon#about to read 3, iclass 28, count 2 2006.224.07:56:42.31#ibcon#read 3, iclass 28, count 2 2006.224.07:56:42.31#ibcon#about to read 4, iclass 28, count 2 2006.224.07:56:42.31#ibcon#read 4, iclass 28, count 2 2006.224.07:56:42.31#ibcon#about to read 5, iclass 28, count 2 2006.224.07:56:42.31#ibcon#read 5, iclass 28, count 2 2006.224.07:56:42.31#ibcon#about to read 6, iclass 28, count 2 2006.224.07:56:42.31#ibcon#read 6, iclass 28, count 2 2006.224.07:56:42.31#ibcon#end of sib2, iclass 28, count 2 2006.224.07:56:42.31#ibcon#*mode == 0, iclass 28, count 2 2006.224.07:56:42.31#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.224.07:56:42.31#ibcon#[27=AT06-04\r\n] 2006.224.07:56:42.31#ibcon#*before write, iclass 28, count 2 2006.224.07:56:42.31#ibcon#enter sib2, iclass 28, count 2 2006.224.07:56:42.31#ibcon#flushed, iclass 28, count 2 2006.224.07:56:42.31#ibcon#about to write, iclass 28, count 2 2006.224.07:56:42.31#ibcon#wrote, iclass 28, count 2 2006.224.07:56:42.31#ibcon#about to read 3, iclass 28, count 2 2006.224.07:56:42.34#ibcon#read 3, iclass 28, count 2 2006.224.07:56:42.34#ibcon#about to read 4, iclass 28, count 2 2006.224.07:56:42.34#ibcon#read 4, iclass 28, count 2 2006.224.07:56:42.34#ibcon#about to read 5, iclass 28, count 2 2006.224.07:56:42.34#ibcon#read 5, iclass 28, count 2 2006.224.07:56:42.34#ibcon#about to read 6, iclass 28, count 2 2006.224.07:56:42.34#ibcon#read 6, iclass 28, count 2 2006.224.07:56:42.34#ibcon#end of sib2, iclass 28, count 2 2006.224.07:56:42.34#ibcon#*after write, iclass 28, count 2 2006.224.07:56:42.34#ibcon#*before return 0, iclass 28, count 2 2006.224.07:56:42.34#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.224.07:56:42.34#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.224.07:56:42.34#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.224.07:56:42.34#ibcon#ireg 7 cls_cnt 0 2006.224.07:56:42.34#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.224.07:56:42.46#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.224.07:56:42.46#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.224.07:56:42.46#ibcon#enter wrdev, iclass 28, count 0 2006.224.07:56:42.46#ibcon#first serial, iclass 28, count 0 2006.224.07:56:42.46#ibcon#enter sib2, iclass 28, count 0 2006.224.07:56:42.46#ibcon#flushed, iclass 28, count 0 2006.224.07:56:42.46#ibcon#about to write, iclass 28, count 0 2006.224.07:56:42.46#ibcon#wrote, iclass 28, count 0 2006.224.07:56:42.46#ibcon#about to read 3, iclass 28, count 0 2006.224.07:56:42.48#ibcon#read 3, iclass 28, count 0 2006.224.07:56:42.48#ibcon#about to read 4, iclass 28, count 0 2006.224.07:56:42.48#ibcon#read 4, iclass 28, count 0 2006.224.07:56:42.48#ibcon#about to read 5, iclass 28, count 0 2006.224.07:56:42.48#ibcon#read 5, iclass 28, count 0 2006.224.07:56:42.48#ibcon#about to read 6, iclass 28, count 0 2006.224.07:56:42.48#ibcon#read 6, iclass 28, count 0 2006.224.07:56:42.48#ibcon#end of sib2, iclass 28, count 0 2006.224.07:56:42.48#ibcon#*mode == 0, iclass 28, count 0 2006.224.07:56:42.48#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.224.07:56:42.48#ibcon#[27=USB\r\n] 2006.224.07:56:42.48#ibcon#*before write, iclass 28, count 0 2006.224.07:56:42.48#ibcon#enter sib2, iclass 28, count 0 2006.224.07:56:42.48#ibcon#flushed, iclass 28, count 0 2006.224.07:56:42.48#ibcon#about to write, iclass 28, count 0 2006.224.07:56:42.48#ibcon#wrote, iclass 28, count 0 2006.224.07:56:42.48#ibcon#about to read 3, iclass 28, count 0 2006.224.07:56:42.51#ibcon#read 3, iclass 28, count 0 2006.224.07:56:42.51#ibcon#about to read 4, iclass 28, count 0 2006.224.07:56:42.51#ibcon#read 4, iclass 28, count 0 2006.224.07:56:42.51#ibcon#about to read 5, iclass 28, count 0 2006.224.07:56:42.51#ibcon#read 5, iclass 28, count 0 2006.224.07:56:42.51#ibcon#about to read 6, iclass 28, count 0 2006.224.07:56:42.51#ibcon#read 6, iclass 28, count 0 2006.224.07:56:42.51#ibcon#end of sib2, iclass 28, count 0 2006.224.07:56:42.51#ibcon#*after write, iclass 28, count 0 2006.224.07:56:42.51#ibcon#*before return 0, iclass 28, count 0 2006.224.07:56:42.51#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.224.07:56:42.51#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.224.07:56:42.51#ibcon#about to clear, iclass 28 cls_cnt 0 2006.224.07:56:42.51#ibcon#cleared, iclass 28 cls_cnt 0 2006.224.07:56:42.51$vc4f8/vabw=wide 2006.224.07:56:42.51#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.224.07:56:42.51#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.224.07:56:42.51#ibcon#ireg 8 cls_cnt 0 2006.224.07:56:42.51#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.224.07:56:42.51#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.224.07:56:42.51#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.224.07:56:42.51#ibcon#enter wrdev, iclass 30, count 0 2006.224.07:56:42.51#ibcon#first serial, iclass 30, count 0 2006.224.07:56:42.51#ibcon#enter sib2, iclass 30, count 0 2006.224.07:56:42.51#ibcon#flushed, iclass 30, count 0 2006.224.07:56:42.51#ibcon#about to write, iclass 30, count 0 2006.224.07:56:42.51#ibcon#wrote, iclass 30, count 0 2006.224.07:56:42.51#ibcon#about to read 3, iclass 30, count 0 2006.224.07:56:42.53#ibcon#read 3, iclass 30, count 0 2006.224.07:56:42.53#ibcon#about to read 4, iclass 30, count 0 2006.224.07:56:42.53#ibcon#read 4, iclass 30, count 0 2006.224.07:56:42.53#ibcon#about to read 5, iclass 30, count 0 2006.224.07:56:42.53#ibcon#read 5, iclass 30, count 0 2006.224.07:56:42.53#ibcon#about to read 6, iclass 30, count 0 2006.224.07:56:42.53#ibcon#read 6, iclass 30, count 0 2006.224.07:56:42.53#ibcon#end of sib2, iclass 30, count 0 2006.224.07:56:42.53#ibcon#*mode == 0, iclass 30, count 0 2006.224.07:56:42.53#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.224.07:56:42.53#ibcon#[25=BW32\r\n] 2006.224.07:56:42.53#ibcon#*before write, iclass 30, count 0 2006.224.07:56:42.53#ibcon#enter sib2, iclass 30, count 0 2006.224.07:56:42.53#ibcon#flushed, iclass 30, count 0 2006.224.07:56:42.53#ibcon#about to write, iclass 30, count 0 2006.224.07:56:42.53#ibcon#wrote, iclass 30, count 0 2006.224.07:56:42.53#ibcon#about to read 3, iclass 30, count 0 2006.224.07:56:42.56#ibcon#read 3, iclass 30, count 0 2006.224.07:56:42.56#ibcon#about to read 4, iclass 30, count 0 2006.224.07:56:42.56#ibcon#read 4, iclass 30, count 0 2006.224.07:56:42.56#ibcon#about to read 5, iclass 30, count 0 2006.224.07:56:42.56#ibcon#read 5, iclass 30, count 0 2006.224.07:56:42.56#ibcon#about to read 6, iclass 30, count 0 2006.224.07:56:42.56#ibcon#read 6, iclass 30, count 0 2006.224.07:56:42.56#ibcon#end of sib2, iclass 30, count 0 2006.224.07:56:42.56#ibcon#*after write, iclass 30, count 0 2006.224.07:56:42.56#ibcon#*before return 0, iclass 30, count 0 2006.224.07:56:42.56#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.224.07:56:42.56#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.224.07:56:42.56#ibcon#about to clear, iclass 30 cls_cnt 0 2006.224.07:56:42.56#ibcon#cleared, iclass 30 cls_cnt 0 2006.224.07:56:42.56$vc4f8/vbbw=wide 2006.224.07:56:42.56#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.224.07:56:42.56#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.224.07:56:42.56#ibcon#ireg 8 cls_cnt 0 2006.224.07:56:42.56#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.224.07:56:42.63#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.224.07:56:42.63#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.224.07:56:42.63#ibcon#enter wrdev, iclass 32, count 0 2006.224.07:56:42.63#ibcon#first serial, iclass 32, count 0 2006.224.07:56:42.63#ibcon#enter sib2, iclass 32, count 0 2006.224.07:56:42.63#ibcon#flushed, iclass 32, count 0 2006.224.07:56:42.63#ibcon#about to write, iclass 32, count 0 2006.224.07:56:42.63#ibcon#wrote, iclass 32, count 0 2006.224.07:56:42.63#ibcon#about to read 3, iclass 32, count 0 2006.224.07:56:42.65#ibcon#read 3, iclass 32, count 0 2006.224.07:56:42.65#ibcon#about to read 4, iclass 32, count 0 2006.224.07:56:42.65#ibcon#read 4, iclass 32, count 0 2006.224.07:56:42.65#ibcon#about to read 5, iclass 32, count 0 2006.224.07:56:42.65#ibcon#read 5, iclass 32, count 0 2006.224.07:56:42.65#ibcon#about to read 6, iclass 32, count 0 2006.224.07:56:42.65#ibcon#read 6, iclass 32, count 0 2006.224.07:56:42.65#ibcon#end of sib2, iclass 32, count 0 2006.224.07:56:42.65#ibcon#*mode == 0, iclass 32, count 0 2006.224.07:56:42.65#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.224.07:56:42.65#ibcon#[27=BW32\r\n] 2006.224.07:56:42.65#ibcon#*before write, iclass 32, count 0 2006.224.07:56:42.65#ibcon#enter sib2, iclass 32, count 0 2006.224.07:56:42.65#ibcon#flushed, iclass 32, count 0 2006.224.07:56:42.65#ibcon#about to write, iclass 32, count 0 2006.224.07:56:42.65#ibcon#wrote, iclass 32, count 0 2006.224.07:56:42.65#ibcon#about to read 3, iclass 32, count 0 2006.224.07:56:42.68#ibcon#read 3, iclass 32, count 0 2006.224.07:56:42.68#ibcon#about to read 4, iclass 32, count 0 2006.224.07:56:42.68#ibcon#read 4, iclass 32, count 0 2006.224.07:56:42.68#ibcon#about to read 5, iclass 32, count 0 2006.224.07:56:42.68#ibcon#read 5, iclass 32, count 0 2006.224.07:56:42.68#ibcon#about to read 6, iclass 32, count 0 2006.224.07:56:42.68#ibcon#read 6, iclass 32, count 0 2006.224.07:56:42.68#ibcon#end of sib2, iclass 32, count 0 2006.224.07:56:42.68#ibcon#*after write, iclass 32, count 0 2006.224.07:56:42.68#ibcon#*before return 0, iclass 32, count 0 2006.224.07:56:42.68#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.224.07:56:42.68#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.224.07:56:42.68#ibcon#about to clear, iclass 32 cls_cnt 0 2006.224.07:56:42.68#ibcon#cleared, iclass 32 cls_cnt 0 2006.224.07:56:42.68$4f8m12a/ifd4f 2006.224.07:56:42.68$ifd4f/lo= 2006.224.07:56:42.68$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.224.07:56:42.68$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.224.07:56:42.68$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.224.07:56:42.68$ifd4f/patch= 2006.224.07:56:42.68$ifd4f/patch=lo1,a1,a2,a3,a4 2006.224.07:56:42.68$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.224.07:56:42.68$ifd4f/patch=lo3,a5,a6,a7,a8 2006.224.07:56:42.68$4f8m12a/"form=m,16.000,1:2 2006.224.07:56:42.68$4f8m12a/"tpicd 2006.224.07:56:42.68$4f8m12a/echo=off 2006.224.07:56:42.68$4f8m12a/xlog=off 2006.224.07:56:42.68:!2006.224.07:58:50 2006.224.07:57:13.14#trakl#Source acquired 2006.224.07:57:13.14#flagr#flagr/antenna,acquired 2006.224.07:58:50.00:preob 2006.224.07:58:50.14/onsource/TRACKING 2006.224.07:58:50.14:!2006.224.07:59:00 2006.224.07:59:00.00:data_valid=on 2006.224.07:59:00.00:midob 2006.224.07:59:01.14/onsource/TRACKING 2006.224.07:59:01.14/wx/23.61,1004.4,100 2006.224.07:59:01.29/cable/+6.4341E-03 2006.224.07:59:02.38/va/01,08,usb,yes,43,46 2006.224.07:59:02.38/va/02,07,usb,yes,44,46 2006.224.07:59:02.38/va/03,06,usb,yes,47,47 2006.224.07:59:02.38/va/04,07,usb,yes,46,49 2006.224.07:59:02.38/va/05,07,usb,yes,53,56 2006.224.07:59:02.38/va/06,06,usb,yes,53,52 2006.224.07:59:02.38/va/07,06,usb,yes,54,53 2006.224.07:59:02.38/va/08,07,usb,yes,51,50 2006.224.07:59:02.61/valo/01,532.99,yes,locked 2006.224.07:59:02.61/valo/02,572.99,yes,locked 2006.224.07:59:02.61/valo/03,672.99,yes,locked 2006.224.07:59:02.61/valo/04,832.99,yes,locked 2006.224.07:59:02.61/valo/05,652.99,yes,locked 2006.224.07:59:02.61/valo/06,772.99,yes,locked 2006.224.07:59:02.61/valo/07,832.99,yes,locked 2006.224.07:59:02.61/valo/08,852.99,yes,locked 2006.224.07:59:03.70/vb/01,04,usb,yes,32,30 2006.224.07:59:03.70/vb/02,04,usb,yes,33,35 2006.224.07:59:03.70/vb/03,04,usb,yes,30,34 2006.224.07:59:03.70/vb/04,04,usb,yes,31,31 2006.224.07:59:03.70/vb/05,04,usb,yes,29,33 2006.224.07:59:03.70/vb/06,04,usb,yes,30,33 2006.224.07:59:03.70/vb/07,04,usb,yes,32,32 2006.224.07:59:03.70/vb/08,04,usb,yes,30,33 2006.224.07:59:03.93/vblo/01,632.99,yes,locked 2006.224.07:59:03.93/vblo/02,640.99,yes,locked 2006.224.07:59:03.93/vblo/03,656.99,yes,locked 2006.224.07:59:03.93/vblo/04,712.99,yes,locked 2006.224.07:59:03.93/vblo/05,744.99,yes,locked 2006.224.07:59:03.93/vblo/06,752.99,yes,locked 2006.224.07:59:03.93/vblo/07,734.99,yes,locked 2006.224.07:59:03.93/vblo/08,744.99,yes,locked 2006.224.07:59:04.08/vabw/8 2006.224.07:59:04.23/vbbw/8 2006.224.07:59:04.32/xfe/off,on,15.0 2006.224.07:59:04.69/ifatt/23,28,28,28 2006.224.07:59:05.07/fmout-gps/S +4.34E-07 2006.224.07:59:05.11:!2006.224.08:00:00 2006.224.08:00:00.00:data_valid=off 2006.224.08:00:00.00:postob 2006.224.08:00:00.17/cable/+6.4339E-03 2006.224.08:00:00.17/wx/23.62,1004.5,100 2006.224.08:00:01.07/fmout-gps/S +4.34E-07 2006.224.08:00:01.07:scan_name=224-0800,k06224,60 2006.224.08:00:01.07:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.224.08:00:01.14#flagr#flagr/antenna,new-source 2006.224.08:00:02.14:checkk5 2006.224.08:00:02.51/chk_autoobs//k5ts1/ autoobs is running! 2006.224.08:00:02.89/chk_autoobs//k5ts2/ autoobs is running! 2006.224.08:00:03.27/chk_autoobs//k5ts3/ autoobs is running! 2006.224.08:00:03.65/chk_autoobs//k5ts4/ autoobs is running! 2006.224.08:00:04.01/chk_obsdata//k5ts1/T2240759??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.224.08:00:04.38/chk_obsdata//k5ts2/T2240759??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.224.08:00:04.75/chk_obsdata//k5ts3/T2240759??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.224.08:00:05.11/chk_obsdata//k5ts4/T2240759??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.224.08:00:05.80/k5log//k5ts1_log_newline 2006.224.08:00:06.49/k5log//k5ts2_log_newline 2006.224.08:00:07.17/k5log//k5ts3_log_newline 2006.224.08:00:07.86/k5log//k5ts4_log_newline 2006.224.08:00:07.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.224.08:00:07.88:4f8m12a=2 2006.224.08:00:07.88$4f8m12a/echo=on 2006.224.08:00:07.88$4f8m12a/pcalon 2006.224.08:00:07.88$pcalon/"no phase cal control is implemented here 2006.224.08:00:07.88$4f8m12a/"tpicd=stop 2006.224.08:00:07.88$4f8m12a/vc4f8 2006.224.08:00:07.88$vc4f8/valo=1,532.99 2006.224.08:00:07.88#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.224.08:00:07.88#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.224.08:00:07.88#ibcon#ireg 17 cls_cnt 0 2006.224.08:00:07.88#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.224.08:00:07.88#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.224.08:00:07.88#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.224.08:00:07.88#ibcon#enter wrdev, iclass 5, count 0 2006.224.08:00:07.88#ibcon#first serial, iclass 5, count 0 2006.224.08:00:07.88#ibcon#enter sib2, iclass 5, count 0 2006.224.08:00:07.88#ibcon#flushed, iclass 5, count 0 2006.224.08:00:07.88#ibcon#about to write, iclass 5, count 0 2006.224.08:00:07.88#ibcon#wrote, iclass 5, count 0 2006.224.08:00:07.88#ibcon#about to read 3, iclass 5, count 0 2006.224.08:00:07.90#ibcon#read 3, iclass 5, count 0 2006.224.08:00:07.90#ibcon#about to read 4, iclass 5, count 0 2006.224.08:00:07.90#ibcon#read 4, iclass 5, count 0 2006.224.08:00:07.90#ibcon#about to read 5, iclass 5, count 0 2006.224.08:00:07.90#ibcon#read 5, iclass 5, count 0 2006.224.08:00:07.90#ibcon#about to read 6, iclass 5, count 0 2006.224.08:00:07.90#ibcon#read 6, iclass 5, count 0 2006.224.08:00:07.90#ibcon#end of sib2, iclass 5, count 0 2006.224.08:00:07.90#ibcon#*mode == 0, iclass 5, count 0 2006.224.08:00:07.90#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.224.08:00:07.90#ibcon#[26=FRQ=01,532.99\r\n] 2006.224.08:00:07.90#ibcon#*before write, iclass 5, count 0 2006.224.08:00:07.90#ibcon#enter sib2, iclass 5, count 0 2006.224.08:00:07.90#ibcon#flushed, iclass 5, count 0 2006.224.08:00:07.90#ibcon#about to write, iclass 5, count 0 2006.224.08:00:07.90#ibcon#wrote, iclass 5, count 0 2006.224.08:00:07.90#ibcon#about to read 3, iclass 5, count 0 2006.224.08:00:07.95#ibcon#read 3, iclass 5, count 0 2006.224.08:00:07.95#ibcon#about to read 4, iclass 5, count 0 2006.224.08:00:07.95#ibcon#read 4, iclass 5, count 0 2006.224.08:00:07.95#ibcon#about to read 5, iclass 5, count 0 2006.224.08:00:07.95#ibcon#read 5, iclass 5, count 0 2006.224.08:00:07.95#ibcon#about to read 6, iclass 5, count 0 2006.224.08:00:07.95#ibcon#read 6, iclass 5, count 0 2006.224.08:00:07.95#ibcon#end of sib2, iclass 5, count 0 2006.224.08:00:07.95#ibcon#*after write, iclass 5, count 0 2006.224.08:00:07.95#ibcon#*before return 0, iclass 5, count 0 2006.224.08:00:07.95#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.224.08:00:07.95#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.224.08:00:07.95#ibcon#about to clear, iclass 5 cls_cnt 0 2006.224.08:00:07.95#ibcon#cleared, iclass 5 cls_cnt 0 2006.224.08:00:07.95$vc4f8/va=1,8 2006.224.08:00:07.95#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.224.08:00:07.95#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.224.08:00:07.95#ibcon#ireg 11 cls_cnt 2 2006.224.08:00:07.95#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.224.08:00:07.95#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.224.08:00:07.95#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.224.08:00:07.95#ibcon#enter wrdev, iclass 7, count 2 2006.224.08:00:07.95#ibcon#first serial, iclass 7, count 2 2006.224.08:00:07.95#ibcon#enter sib2, iclass 7, count 2 2006.224.08:00:07.95#ibcon#flushed, iclass 7, count 2 2006.224.08:00:07.95#ibcon#about to write, iclass 7, count 2 2006.224.08:00:07.95#ibcon#wrote, iclass 7, count 2 2006.224.08:00:07.95#ibcon#about to read 3, iclass 7, count 2 2006.224.08:00:07.97#ibcon#read 3, iclass 7, count 2 2006.224.08:00:07.97#ibcon#about to read 4, iclass 7, count 2 2006.224.08:00:07.97#ibcon#read 4, iclass 7, count 2 2006.224.08:00:07.97#ibcon#about to read 5, iclass 7, count 2 2006.224.08:00:07.97#ibcon#read 5, iclass 7, count 2 2006.224.08:00:07.97#ibcon#about to read 6, iclass 7, count 2 2006.224.08:00:07.97#ibcon#read 6, iclass 7, count 2 2006.224.08:00:07.97#ibcon#end of sib2, iclass 7, count 2 2006.224.08:00:07.97#ibcon#*mode == 0, iclass 7, count 2 2006.224.08:00:07.97#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.224.08:00:07.97#ibcon#[25=AT01-08\r\n] 2006.224.08:00:07.97#ibcon#*before write, iclass 7, count 2 2006.224.08:00:07.97#ibcon#enter sib2, iclass 7, count 2 2006.224.08:00:07.97#ibcon#flushed, iclass 7, count 2 2006.224.08:00:07.97#ibcon#about to write, iclass 7, count 2 2006.224.08:00:07.97#ibcon#wrote, iclass 7, count 2 2006.224.08:00:07.97#ibcon#about to read 3, iclass 7, count 2 2006.224.08:00:08.00#ibcon#read 3, iclass 7, count 2 2006.224.08:00:08.00#ibcon#about to read 4, iclass 7, count 2 2006.224.08:00:08.00#ibcon#read 4, iclass 7, count 2 2006.224.08:00:08.00#ibcon#about to read 5, iclass 7, count 2 2006.224.08:00:08.00#ibcon#read 5, iclass 7, count 2 2006.224.08:00:08.00#ibcon#about to read 6, iclass 7, count 2 2006.224.08:00:08.00#ibcon#read 6, iclass 7, count 2 2006.224.08:00:08.00#ibcon#end of sib2, iclass 7, count 2 2006.224.08:00:08.00#ibcon#*after write, iclass 7, count 2 2006.224.08:00:08.00#ibcon#*before return 0, iclass 7, count 2 2006.224.08:00:08.00#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.224.08:00:08.00#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.224.08:00:08.00#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.224.08:00:08.00#ibcon#ireg 7 cls_cnt 0 2006.224.08:00:08.00#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.224.08:00:08.12#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.224.08:00:08.12#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.224.08:00:08.12#ibcon#enter wrdev, iclass 7, count 0 2006.224.08:00:08.12#ibcon#first serial, iclass 7, count 0 2006.224.08:00:08.12#ibcon#enter sib2, iclass 7, count 0 2006.224.08:00:08.12#ibcon#flushed, iclass 7, count 0 2006.224.08:00:08.12#ibcon#about to write, iclass 7, count 0 2006.224.08:00:08.12#ibcon#wrote, iclass 7, count 0 2006.224.08:00:08.12#ibcon#about to read 3, iclass 7, count 0 2006.224.08:00:08.14#ibcon#read 3, iclass 7, count 0 2006.224.08:00:08.14#ibcon#about to read 4, iclass 7, count 0 2006.224.08:00:08.14#ibcon#read 4, iclass 7, count 0 2006.224.08:00:08.14#ibcon#about to read 5, iclass 7, count 0 2006.224.08:00:08.14#ibcon#read 5, iclass 7, count 0 2006.224.08:00:08.14#ibcon#about to read 6, iclass 7, count 0 2006.224.08:00:08.14#ibcon#read 6, iclass 7, count 0 2006.224.08:00:08.14#ibcon#end of sib2, iclass 7, count 0 2006.224.08:00:08.14#ibcon#*mode == 0, iclass 7, count 0 2006.224.08:00:08.14#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.224.08:00:08.14#ibcon#[25=USB\r\n] 2006.224.08:00:08.14#ibcon#*before write, iclass 7, count 0 2006.224.08:00:08.14#ibcon#enter sib2, iclass 7, count 0 2006.224.08:00:08.14#ibcon#flushed, iclass 7, count 0 2006.224.08:00:08.14#ibcon#about to write, iclass 7, count 0 2006.224.08:00:08.14#ibcon#wrote, iclass 7, count 0 2006.224.08:00:08.14#ibcon#about to read 3, iclass 7, count 0 2006.224.08:00:08.17#ibcon#read 3, iclass 7, count 0 2006.224.08:00:08.17#ibcon#about to read 4, iclass 7, count 0 2006.224.08:00:08.17#ibcon#read 4, iclass 7, count 0 2006.224.08:00:08.17#ibcon#about to read 5, iclass 7, count 0 2006.224.08:00:08.17#ibcon#read 5, iclass 7, count 0 2006.224.08:00:08.17#ibcon#about to read 6, iclass 7, count 0 2006.224.08:00:08.17#ibcon#read 6, iclass 7, count 0 2006.224.08:00:08.17#ibcon#end of sib2, iclass 7, count 0 2006.224.08:00:08.17#ibcon#*after write, iclass 7, count 0 2006.224.08:00:08.17#ibcon#*before return 0, iclass 7, count 0 2006.224.08:00:08.17#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.224.08:00:08.17#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.224.08:00:08.17#ibcon#about to clear, iclass 7 cls_cnt 0 2006.224.08:00:08.17#ibcon#cleared, iclass 7 cls_cnt 0 2006.224.08:00:08.17$vc4f8/valo=2,572.99 2006.224.08:00:08.17#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.224.08:00:08.17#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.224.08:00:08.17#ibcon#ireg 17 cls_cnt 0 2006.224.08:00:08.17#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.224.08:00:08.17#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.224.08:00:08.17#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.224.08:00:08.17#ibcon#enter wrdev, iclass 11, count 0 2006.224.08:00:08.17#ibcon#first serial, iclass 11, count 0 2006.224.08:00:08.17#ibcon#enter sib2, iclass 11, count 0 2006.224.08:00:08.17#ibcon#flushed, iclass 11, count 0 2006.224.08:00:08.17#ibcon#about to write, iclass 11, count 0 2006.224.08:00:08.17#ibcon#wrote, iclass 11, count 0 2006.224.08:00:08.17#ibcon#about to read 3, iclass 11, count 0 2006.224.08:00:08.20#ibcon#read 3, iclass 11, count 0 2006.224.08:00:08.20#ibcon#about to read 4, iclass 11, count 0 2006.224.08:00:08.20#ibcon#read 4, iclass 11, count 0 2006.224.08:00:08.20#ibcon#about to read 5, iclass 11, count 0 2006.224.08:00:08.20#ibcon#read 5, iclass 11, count 0 2006.224.08:00:08.20#ibcon#about to read 6, iclass 11, count 0 2006.224.08:00:08.20#ibcon#read 6, iclass 11, count 0 2006.224.08:00:08.20#ibcon#end of sib2, iclass 11, count 0 2006.224.08:00:08.20#ibcon#*mode == 0, iclass 11, count 0 2006.224.08:00:08.20#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.224.08:00:08.20#ibcon#[26=FRQ=02,572.99\r\n] 2006.224.08:00:08.20#ibcon#*before write, iclass 11, count 0 2006.224.08:00:08.20#ibcon#enter sib2, iclass 11, count 0 2006.224.08:00:08.20#ibcon#flushed, iclass 11, count 0 2006.224.08:00:08.20#ibcon#about to write, iclass 11, count 0 2006.224.08:00:08.20#ibcon#wrote, iclass 11, count 0 2006.224.08:00:08.20#ibcon#about to read 3, iclass 11, count 0 2006.224.08:00:08.24#ibcon#read 3, iclass 11, count 0 2006.224.08:00:08.24#ibcon#about to read 4, iclass 11, count 0 2006.224.08:00:08.24#ibcon#read 4, iclass 11, count 0 2006.224.08:00:08.24#ibcon#about to read 5, iclass 11, count 0 2006.224.08:00:08.24#ibcon#read 5, iclass 11, count 0 2006.224.08:00:08.24#ibcon#about to read 6, iclass 11, count 0 2006.224.08:00:08.24#ibcon#read 6, iclass 11, count 0 2006.224.08:00:08.24#ibcon#end of sib2, iclass 11, count 0 2006.224.08:00:08.24#ibcon#*after write, iclass 11, count 0 2006.224.08:00:08.24#ibcon#*before return 0, iclass 11, count 0 2006.224.08:00:08.24#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.224.08:00:08.24#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.224.08:00:08.24#ibcon#about to clear, iclass 11 cls_cnt 0 2006.224.08:00:08.24#ibcon#cleared, iclass 11 cls_cnt 0 2006.224.08:00:08.24$vc4f8/va=2,7 2006.224.08:00:08.24#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.224.08:00:08.24#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.224.08:00:08.24#ibcon#ireg 11 cls_cnt 2 2006.224.08:00:08.24#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.224.08:00:08.29#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.224.08:00:08.29#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.224.08:00:08.29#ibcon#enter wrdev, iclass 13, count 2 2006.224.08:00:08.29#ibcon#first serial, iclass 13, count 2 2006.224.08:00:08.29#ibcon#enter sib2, iclass 13, count 2 2006.224.08:00:08.29#ibcon#flushed, iclass 13, count 2 2006.224.08:00:08.29#ibcon#about to write, iclass 13, count 2 2006.224.08:00:08.29#ibcon#wrote, iclass 13, count 2 2006.224.08:00:08.29#ibcon#about to read 3, iclass 13, count 2 2006.224.08:00:08.31#ibcon#read 3, iclass 13, count 2 2006.224.08:00:08.31#ibcon#about to read 4, iclass 13, count 2 2006.224.08:00:08.31#ibcon#read 4, iclass 13, count 2 2006.224.08:00:08.31#ibcon#about to read 5, iclass 13, count 2 2006.224.08:00:08.31#ibcon#read 5, iclass 13, count 2 2006.224.08:00:08.31#ibcon#about to read 6, iclass 13, count 2 2006.224.08:00:08.31#ibcon#read 6, iclass 13, count 2 2006.224.08:00:08.31#ibcon#end of sib2, iclass 13, count 2 2006.224.08:00:08.31#ibcon#*mode == 0, iclass 13, count 2 2006.224.08:00:08.31#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.224.08:00:08.31#ibcon#[25=AT02-07\r\n] 2006.224.08:00:08.31#ibcon#*before write, iclass 13, count 2 2006.224.08:00:08.31#ibcon#enter sib2, iclass 13, count 2 2006.224.08:00:08.31#ibcon#flushed, iclass 13, count 2 2006.224.08:00:08.31#ibcon#about to write, iclass 13, count 2 2006.224.08:00:08.31#ibcon#wrote, iclass 13, count 2 2006.224.08:00:08.31#ibcon#about to read 3, iclass 13, count 2 2006.224.08:00:08.34#ibcon#read 3, iclass 13, count 2 2006.224.08:00:08.34#ibcon#about to read 4, iclass 13, count 2 2006.224.08:00:08.34#ibcon#read 4, iclass 13, count 2 2006.224.08:00:08.34#ibcon#about to read 5, iclass 13, count 2 2006.224.08:00:08.34#ibcon#read 5, iclass 13, count 2 2006.224.08:00:08.34#ibcon#about to read 6, iclass 13, count 2 2006.224.08:00:08.34#ibcon#read 6, iclass 13, count 2 2006.224.08:00:08.34#ibcon#end of sib2, iclass 13, count 2 2006.224.08:00:08.34#ibcon#*after write, iclass 13, count 2 2006.224.08:00:08.34#ibcon#*before return 0, iclass 13, count 2 2006.224.08:00:08.34#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.224.08:00:08.34#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.224.08:00:08.34#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.224.08:00:08.34#ibcon#ireg 7 cls_cnt 0 2006.224.08:00:08.34#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.224.08:00:08.46#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.224.08:00:08.46#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.224.08:00:08.46#ibcon#enter wrdev, iclass 13, count 0 2006.224.08:00:08.46#ibcon#first serial, iclass 13, count 0 2006.224.08:00:08.46#ibcon#enter sib2, iclass 13, count 0 2006.224.08:00:08.46#ibcon#flushed, iclass 13, count 0 2006.224.08:00:08.46#ibcon#about to write, iclass 13, count 0 2006.224.08:00:08.46#ibcon#wrote, iclass 13, count 0 2006.224.08:00:08.46#ibcon#about to read 3, iclass 13, count 0 2006.224.08:00:08.48#ibcon#read 3, iclass 13, count 0 2006.224.08:00:08.48#ibcon#about to read 4, iclass 13, count 0 2006.224.08:00:08.48#ibcon#read 4, iclass 13, count 0 2006.224.08:00:08.48#ibcon#about to read 5, iclass 13, count 0 2006.224.08:00:08.48#ibcon#read 5, iclass 13, count 0 2006.224.08:00:08.48#ibcon#about to read 6, iclass 13, count 0 2006.224.08:00:08.48#ibcon#read 6, iclass 13, count 0 2006.224.08:00:08.48#ibcon#end of sib2, iclass 13, count 0 2006.224.08:00:08.48#ibcon#*mode == 0, iclass 13, count 0 2006.224.08:00:08.48#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.224.08:00:08.48#ibcon#[25=USB\r\n] 2006.224.08:00:08.48#ibcon#*before write, iclass 13, count 0 2006.224.08:00:08.48#ibcon#enter sib2, iclass 13, count 0 2006.224.08:00:08.48#ibcon#flushed, iclass 13, count 0 2006.224.08:00:08.48#ibcon#about to write, iclass 13, count 0 2006.224.08:00:08.48#ibcon#wrote, iclass 13, count 0 2006.224.08:00:08.48#ibcon#about to read 3, iclass 13, count 0 2006.224.08:00:08.51#ibcon#read 3, iclass 13, count 0 2006.224.08:00:08.51#ibcon#about to read 4, iclass 13, count 0 2006.224.08:00:08.51#ibcon#read 4, iclass 13, count 0 2006.224.08:00:08.51#ibcon#about to read 5, iclass 13, count 0 2006.224.08:00:08.51#ibcon#read 5, iclass 13, count 0 2006.224.08:00:08.51#ibcon#about to read 6, iclass 13, count 0 2006.224.08:00:08.51#ibcon#read 6, iclass 13, count 0 2006.224.08:00:08.51#ibcon#end of sib2, iclass 13, count 0 2006.224.08:00:08.51#ibcon#*after write, iclass 13, count 0 2006.224.08:00:08.51#ibcon#*before return 0, iclass 13, count 0 2006.224.08:00:08.51#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.224.08:00:08.51#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.224.08:00:08.51#ibcon#about to clear, iclass 13 cls_cnt 0 2006.224.08:00:08.51#ibcon#cleared, iclass 13 cls_cnt 0 2006.224.08:00:08.51$vc4f8/valo=3,672.99 2006.224.08:00:08.51#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.224.08:00:08.51#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.224.08:00:08.51#ibcon#ireg 17 cls_cnt 0 2006.224.08:00:08.51#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.224.08:00:08.51#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.224.08:00:08.51#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.224.08:00:08.51#ibcon#enter wrdev, iclass 15, count 0 2006.224.08:00:08.51#ibcon#first serial, iclass 15, count 0 2006.224.08:00:08.51#ibcon#enter sib2, iclass 15, count 0 2006.224.08:00:08.51#ibcon#flushed, iclass 15, count 0 2006.224.08:00:08.51#ibcon#about to write, iclass 15, count 0 2006.224.08:00:08.51#ibcon#wrote, iclass 15, count 0 2006.224.08:00:08.51#ibcon#about to read 3, iclass 15, count 0 2006.224.08:00:08.54#ibcon#read 3, iclass 15, count 0 2006.224.08:00:08.54#ibcon#about to read 4, iclass 15, count 0 2006.224.08:00:08.54#ibcon#read 4, iclass 15, count 0 2006.224.08:00:08.54#ibcon#about to read 5, iclass 15, count 0 2006.224.08:00:08.54#ibcon#read 5, iclass 15, count 0 2006.224.08:00:08.54#ibcon#about to read 6, iclass 15, count 0 2006.224.08:00:08.54#ibcon#read 6, iclass 15, count 0 2006.224.08:00:08.54#ibcon#end of sib2, iclass 15, count 0 2006.224.08:00:08.54#ibcon#*mode == 0, iclass 15, count 0 2006.224.08:00:08.54#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.224.08:00:08.54#ibcon#[26=FRQ=03,672.99\r\n] 2006.224.08:00:08.54#ibcon#*before write, iclass 15, count 0 2006.224.08:00:08.54#ibcon#enter sib2, iclass 15, count 0 2006.224.08:00:08.54#ibcon#flushed, iclass 15, count 0 2006.224.08:00:08.54#ibcon#about to write, iclass 15, count 0 2006.224.08:00:08.54#ibcon#wrote, iclass 15, count 0 2006.224.08:00:08.54#ibcon#about to read 3, iclass 15, count 0 2006.224.08:00:08.58#ibcon#read 3, iclass 15, count 0 2006.224.08:00:08.58#ibcon#about to read 4, iclass 15, count 0 2006.224.08:00:08.58#ibcon#read 4, iclass 15, count 0 2006.224.08:00:08.58#ibcon#about to read 5, iclass 15, count 0 2006.224.08:00:08.58#ibcon#read 5, iclass 15, count 0 2006.224.08:00:08.58#ibcon#about to read 6, iclass 15, count 0 2006.224.08:00:08.58#ibcon#read 6, iclass 15, count 0 2006.224.08:00:08.58#ibcon#end of sib2, iclass 15, count 0 2006.224.08:00:08.58#ibcon#*after write, iclass 15, count 0 2006.224.08:00:08.58#ibcon#*before return 0, iclass 15, count 0 2006.224.08:00:08.58#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.224.08:00:08.58#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.224.08:00:08.58#ibcon#about to clear, iclass 15 cls_cnt 0 2006.224.08:00:08.58#ibcon#cleared, iclass 15 cls_cnt 0 2006.224.08:00:08.58$vc4f8/va=3,6 2006.224.08:00:08.58#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.224.08:00:08.58#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.224.08:00:08.58#ibcon#ireg 11 cls_cnt 2 2006.224.08:00:08.58#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.224.08:00:08.63#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.224.08:00:08.63#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.224.08:00:08.63#ibcon#enter wrdev, iclass 17, count 2 2006.224.08:00:08.63#ibcon#first serial, iclass 17, count 2 2006.224.08:00:08.63#ibcon#enter sib2, iclass 17, count 2 2006.224.08:00:08.63#ibcon#flushed, iclass 17, count 2 2006.224.08:00:08.63#ibcon#about to write, iclass 17, count 2 2006.224.08:00:08.63#ibcon#wrote, iclass 17, count 2 2006.224.08:00:08.63#ibcon#about to read 3, iclass 17, count 2 2006.224.08:00:08.65#ibcon#read 3, iclass 17, count 2 2006.224.08:00:08.65#ibcon#about to read 4, iclass 17, count 2 2006.224.08:00:08.65#ibcon#read 4, iclass 17, count 2 2006.224.08:00:08.65#ibcon#about to read 5, iclass 17, count 2 2006.224.08:00:08.65#ibcon#read 5, iclass 17, count 2 2006.224.08:00:08.65#ibcon#about to read 6, iclass 17, count 2 2006.224.08:00:08.65#ibcon#read 6, iclass 17, count 2 2006.224.08:00:08.65#ibcon#end of sib2, iclass 17, count 2 2006.224.08:00:08.65#ibcon#*mode == 0, iclass 17, count 2 2006.224.08:00:08.65#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.224.08:00:08.65#ibcon#[25=AT03-06\r\n] 2006.224.08:00:08.65#ibcon#*before write, iclass 17, count 2 2006.224.08:00:08.65#ibcon#enter sib2, iclass 17, count 2 2006.224.08:00:08.65#ibcon#flushed, iclass 17, count 2 2006.224.08:00:08.65#ibcon#about to write, iclass 17, count 2 2006.224.08:00:08.65#ibcon#wrote, iclass 17, count 2 2006.224.08:00:08.65#ibcon#about to read 3, iclass 17, count 2 2006.224.08:00:08.68#ibcon#read 3, iclass 17, count 2 2006.224.08:00:08.68#ibcon#about to read 4, iclass 17, count 2 2006.224.08:00:08.68#ibcon#read 4, iclass 17, count 2 2006.224.08:00:08.68#ibcon#about to read 5, iclass 17, count 2 2006.224.08:00:08.68#ibcon#read 5, iclass 17, count 2 2006.224.08:00:08.68#ibcon#about to read 6, iclass 17, count 2 2006.224.08:00:08.68#ibcon#read 6, iclass 17, count 2 2006.224.08:00:08.68#ibcon#end of sib2, iclass 17, count 2 2006.224.08:00:08.68#ibcon#*after write, iclass 17, count 2 2006.224.08:00:08.68#ibcon#*before return 0, iclass 17, count 2 2006.224.08:00:08.68#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.224.08:00:08.68#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.224.08:00:08.68#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.224.08:00:08.68#ibcon#ireg 7 cls_cnt 0 2006.224.08:00:08.68#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.224.08:00:08.80#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.224.08:00:08.80#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.224.08:00:08.80#ibcon#enter wrdev, iclass 17, count 0 2006.224.08:00:08.80#ibcon#first serial, iclass 17, count 0 2006.224.08:00:08.80#ibcon#enter sib2, iclass 17, count 0 2006.224.08:00:08.80#ibcon#flushed, iclass 17, count 0 2006.224.08:00:08.80#ibcon#about to write, iclass 17, count 0 2006.224.08:00:08.80#ibcon#wrote, iclass 17, count 0 2006.224.08:00:08.80#ibcon#about to read 3, iclass 17, count 0 2006.224.08:00:08.82#ibcon#read 3, iclass 17, count 0 2006.224.08:00:08.82#ibcon#about to read 4, iclass 17, count 0 2006.224.08:00:08.82#ibcon#read 4, iclass 17, count 0 2006.224.08:00:08.82#ibcon#about to read 5, iclass 17, count 0 2006.224.08:00:08.82#ibcon#read 5, iclass 17, count 0 2006.224.08:00:08.82#ibcon#about to read 6, iclass 17, count 0 2006.224.08:00:08.82#ibcon#read 6, iclass 17, count 0 2006.224.08:00:08.82#ibcon#end of sib2, iclass 17, count 0 2006.224.08:00:08.82#ibcon#*mode == 0, iclass 17, count 0 2006.224.08:00:08.82#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.224.08:00:08.82#ibcon#[25=USB\r\n] 2006.224.08:00:08.82#ibcon#*before write, iclass 17, count 0 2006.224.08:00:08.82#ibcon#enter sib2, iclass 17, count 0 2006.224.08:00:08.82#ibcon#flushed, iclass 17, count 0 2006.224.08:00:08.82#ibcon#about to write, iclass 17, count 0 2006.224.08:00:08.82#ibcon#wrote, iclass 17, count 0 2006.224.08:00:08.82#ibcon#about to read 3, iclass 17, count 0 2006.224.08:00:08.85#ibcon#read 3, iclass 17, count 0 2006.224.08:00:08.85#ibcon#about to read 4, iclass 17, count 0 2006.224.08:00:08.85#ibcon#read 4, iclass 17, count 0 2006.224.08:00:08.85#ibcon#about to read 5, iclass 17, count 0 2006.224.08:00:08.85#ibcon#read 5, iclass 17, count 0 2006.224.08:00:08.85#ibcon#about to read 6, iclass 17, count 0 2006.224.08:00:08.85#ibcon#read 6, iclass 17, count 0 2006.224.08:00:08.85#ibcon#end of sib2, iclass 17, count 0 2006.224.08:00:08.85#ibcon#*after write, iclass 17, count 0 2006.224.08:00:08.85#ibcon#*before return 0, iclass 17, count 0 2006.224.08:00:08.85#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.224.08:00:08.85#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.224.08:00:08.85#ibcon#about to clear, iclass 17 cls_cnt 0 2006.224.08:00:08.85#ibcon#cleared, iclass 17 cls_cnt 0 2006.224.08:00:08.85$vc4f8/valo=4,832.99 2006.224.08:00:08.85#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.224.08:00:08.85#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.224.08:00:08.85#ibcon#ireg 17 cls_cnt 0 2006.224.08:00:08.85#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.224.08:00:08.85#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.224.08:00:08.85#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.224.08:00:08.85#ibcon#enter wrdev, iclass 19, count 0 2006.224.08:00:08.85#ibcon#first serial, iclass 19, count 0 2006.224.08:00:08.85#ibcon#enter sib2, iclass 19, count 0 2006.224.08:00:08.85#ibcon#flushed, iclass 19, count 0 2006.224.08:00:08.85#ibcon#about to write, iclass 19, count 0 2006.224.08:00:08.85#ibcon#wrote, iclass 19, count 0 2006.224.08:00:08.85#ibcon#about to read 3, iclass 19, count 0 2006.224.08:00:08.88#ibcon#read 3, iclass 19, count 0 2006.224.08:00:08.88#ibcon#about to read 4, iclass 19, count 0 2006.224.08:00:08.88#ibcon#read 4, iclass 19, count 0 2006.224.08:00:08.88#ibcon#about to read 5, iclass 19, count 0 2006.224.08:00:08.88#ibcon#read 5, iclass 19, count 0 2006.224.08:00:08.88#ibcon#about to read 6, iclass 19, count 0 2006.224.08:00:08.88#ibcon#read 6, iclass 19, count 0 2006.224.08:00:08.88#ibcon#end of sib2, iclass 19, count 0 2006.224.08:00:08.88#ibcon#*mode == 0, iclass 19, count 0 2006.224.08:00:08.88#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.224.08:00:08.88#ibcon#[26=FRQ=04,832.99\r\n] 2006.224.08:00:08.88#ibcon#*before write, iclass 19, count 0 2006.224.08:00:08.88#ibcon#enter sib2, iclass 19, count 0 2006.224.08:00:08.88#ibcon#flushed, iclass 19, count 0 2006.224.08:00:08.88#ibcon#about to write, iclass 19, count 0 2006.224.08:00:08.88#ibcon#wrote, iclass 19, count 0 2006.224.08:00:08.88#ibcon#about to read 3, iclass 19, count 0 2006.224.08:00:08.92#ibcon#read 3, iclass 19, count 0 2006.224.08:00:08.92#ibcon#about to read 4, iclass 19, count 0 2006.224.08:00:08.92#ibcon#read 4, iclass 19, count 0 2006.224.08:00:08.92#ibcon#about to read 5, iclass 19, count 0 2006.224.08:00:08.92#ibcon#read 5, iclass 19, count 0 2006.224.08:00:08.92#ibcon#about to read 6, iclass 19, count 0 2006.224.08:00:08.92#ibcon#read 6, iclass 19, count 0 2006.224.08:00:08.92#ibcon#end of sib2, iclass 19, count 0 2006.224.08:00:08.92#ibcon#*after write, iclass 19, count 0 2006.224.08:00:08.92#ibcon#*before return 0, iclass 19, count 0 2006.224.08:00:08.92#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.224.08:00:08.92#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.224.08:00:08.92#ibcon#about to clear, iclass 19 cls_cnt 0 2006.224.08:00:08.92#ibcon#cleared, iclass 19 cls_cnt 0 2006.224.08:00:08.92$vc4f8/va=4,7 2006.224.08:00:08.92#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.224.08:00:08.92#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.224.08:00:08.92#ibcon#ireg 11 cls_cnt 2 2006.224.08:00:08.92#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.224.08:00:08.97#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.224.08:00:08.97#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.224.08:00:08.97#ibcon#enter wrdev, iclass 21, count 2 2006.224.08:00:08.97#ibcon#first serial, iclass 21, count 2 2006.224.08:00:08.97#ibcon#enter sib2, iclass 21, count 2 2006.224.08:00:08.97#ibcon#flushed, iclass 21, count 2 2006.224.08:00:08.97#ibcon#about to write, iclass 21, count 2 2006.224.08:00:08.97#ibcon#wrote, iclass 21, count 2 2006.224.08:00:08.97#ibcon#about to read 3, iclass 21, count 2 2006.224.08:00:08.99#ibcon#read 3, iclass 21, count 2 2006.224.08:00:08.99#ibcon#about to read 4, iclass 21, count 2 2006.224.08:00:08.99#ibcon#read 4, iclass 21, count 2 2006.224.08:00:08.99#ibcon#about to read 5, iclass 21, count 2 2006.224.08:00:08.99#ibcon#read 5, iclass 21, count 2 2006.224.08:00:08.99#ibcon#about to read 6, iclass 21, count 2 2006.224.08:00:08.99#ibcon#read 6, iclass 21, count 2 2006.224.08:00:08.99#ibcon#end of sib2, iclass 21, count 2 2006.224.08:00:08.99#ibcon#*mode == 0, iclass 21, count 2 2006.224.08:00:08.99#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.224.08:00:08.99#ibcon#[25=AT04-07\r\n] 2006.224.08:00:08.99#ibcon#*before write, iclass 21, count 2 2006.224.08:00:08.99#ibcon#enter sib2, iclass 21, count 2 2006.224.08:00:08.99#ibcon#flushed, iclass 21, count 2 2006.224.08:00:08.99#ibcon#about to write, iclass 21, count 2 2006.224.08:00:08.99#ibcon#wrote, iclass 21, count 2 2006.224.08:00:08.99#ibcon#about to read 3, iclass 21, count 2 2006.224.08:00:09.02#ibcon#read 3, iclass 21, count 2 2006.224.08:00:09.02#ibcon#about to read 4, iclass 21, count 2 2006.224.08:00:09.02#ibcon#read 4, iclass 21, count 2 2006.224.08:00:09.02#ibcon#about to read 5, iclass 21, count 2 2006.224.08:00:09.02#ibcon#read 5, iclass 21, count 2 2006.224.08:00:09.02#ibcon#about to read 6, iclass 21, count 2 2006.224.08:00:09.02#ibcon#read 6, iclass 21, count 2 2006.224.08:00:09.02#ibcon#end of sib2, iclass 21, count 2 2006.224.08:00:09.02#ibcon#*after write, iclass 21, count 2 2006.224.08:00:09.02#ibcon#*before return 0, iclass 21, count 2 2006.224.08:00:09.02#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.224.08:00:09.02#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.224.08:00:09.02#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.224.08:00:09.02#ibcon#ireg 7 cls_cnt 0 2006.224.08:00:09.02#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.224.08:00:09.14#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.224.08:00:09.14#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.224.08:00:09.14#ibcon#enter wrdev, iclass 21, count 0 2006.224.08:00:09.14#ibcon#first serial, iclass 21, count 0 2006.224.08:00:09.14#ibcon#enter sib2, iclass 21, count 0 2006.224.08:00:09.14#ibcon#flushed, iclass 21, count 0 2006.224.08:00:09.14#ibcon#about to write, iclass 21, count 0 2006.224.08:00:09.14#ibcon#wrote, iclass 21, count 0 2006.224.08:00:09.14#ibcon#about to read 3, iclass 21, count 0 2006.224.08:00:09.16#ibcon#read 3, iclass 21, count 0 2006.224.08:00:09.16#ibcon#about to read 4, iclass 21, count 0 2006.224.08:00:09.16#ibcon#read 4, iclass 21, count 0 2006.224.08:00:09.16#ibcon#about to read 5, iclass 21, count 0 2006.224.08:00:09.16#ibcon#read 5, iclass 21, count 0 2006.224.08:00:09.16#ibcon#about to read 6, iclass 21, count 0 2006.224.08:00:09.16#ibcon#read 6, iclass 21, count 0 2006.224.08:00:09.16#ibcon#end of sib2, iclass 21, count 0 2006.224.08:00:09.16#ibcon#*mode == 0, iclass 21, count 0 2006.224.08:00:09.16#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.224.08:00:09.16#ibcon#[25=USB\r\n] 2006.224.08:00:09.16#ibcon#*before write, iclass 21, count 0 2006.224.08:00:09.16#ibcon#enter sib2, iclass 21, count 0 2006.224.08:00:09.16#ibcon#flushed, iclass 21, count 0 2006.224.08:00:09.16#ibcon#about to write, iclass 21, count 0 2006.224.08:00:09.16#ibcon#wrote, iclass 21, count 0 2006.224.08:00:09.16#ibcon#about to read 3, iclass 21, count 0 2006.224.08:00:09.19#ibcon#read 3, iclass 21, count 0 2006.224.08:00:09.19#ibcon#about to read 4, iclass 21, count 0 2006.224.08:00:09.19#ibcon#read 4, iclass 21, count 0 2006.224.08:00:09.19#ibcon#about to read 5, iclass 21, count 0 2006.224.08:00:09.19#ibcon#read 5, iclass 21, count 0 2006.224.08:00:09.19#ibcon#about to read 6, iclass 21, count 0 2006.224.08:00:09.19#ibcon#read 6, iclass 21, count 0 2006.224.08:00:09.19#ibcon#end of sib2, iclass 21, count 0 2006.224.08:00:09.19#ibcon#*after write, iclass 21, count 0 2006.224.08:00:09.19#ibcon#*before return 0, iclass 21, count 0 2006.224.08:00:09.19#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.224.08:00:09.19#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.224.08:00:09.19#ibcon#about to clear, iclass 21 cls_cnt 0 2006.224.08:00:09.19#ibcon#cleared, iclass 21 cls_cnt 0 2006.224.08:00:09.19$vc4f8/valo=5,652.99 2006.224.08:00:09.19#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.224.08:00:09.19#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.224.08:00:09.19#ibcon#ireg 17 cls_cnt 0 2006.224.08:00:09.19#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.224.08:00:09.19#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.224.08:00:09.19#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.224.08:00:09.19#ibcon#enter wrdev, iclass 23, count 0 2006.224.08:00:09.19#ibcon#first serial, iclass 23, count 0 2006.224.08:00:09.19#ibcon#enter sib2, iclass 23, count 0 2006.224.08:00:09.19#ibcon#flushed, iclass 23, count 0 2006.224.08:00:09.19#ibcon#about to write, iclass 23, count 0 2006.224.08:00:09.19#ibcon#wrote, iclass 23, count 0 2006.224.08:00:09.19#ibcon#about to read 3, iclass 23, count 0 2006.224.08:00:09.21#ibcon#read 3, iclass 23, count 0 2006.224.08:00:09.21#ibcon#about to read 4, iclass 23, count 0 2006.224.08:00:09.21#ibcon#read 4, iclass 23, count 0 2006.224.08:00:09.21#ibcon#about to read 5, iclass 23, count 0 2006.224.08:00:09.21#ibcon#read 5, iclass 23, count 0 2006.224.08:00:09.21#ibcon#about to read 6, iclass 23, count 0 2006.224.08:00:09.21#ibcon#read 6, iclass 23, count 0 2006.224.08:00:09.21#ibcon#end of sib2, iclass 23, count 0 2006.224.08:00:09.21#ibcon#*mode == 0, iclass 23, count 0 2006.224.08:00:09.21#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.224.08:00:09.21#ibcon#[26=FRQ=05,652.99\r\n] 2006.224.08:00:09.21#ibcon#*before write, iclass 23, count 0 2006.224.08:00:09.21#ibcon#enter sib2, iclass 23, count 0 2006.224.08:00:09.21#ibcon#flushed, iclass 23, count 0 2006.224.08:00:09.21#ibcon#about to write, iclass 23, count 0 2006.224.08:00:09.21#ibcon#wrote, iclass 23, count 0 2006.224.08:00:09.21#ibcon#about to read 3, iclass 23, count 0 2006.224.08:00:09.25#ibcon#read 3, iclass 23, count 0 2006.224.08:00:09.25#ibcon#about to read 4, iclass 23, count 0 2006.224.08:00:09.25#ibcon#read 4, iclass 23, count 0 2006.224.08:00:09.25#ibcon#about to read 5, iclass 23, count 0 2006.224.08:00:09.25#ibcon#read 5, iclass 23, count 0 2006.224.08:00:09.25#ibcon#about to read 6, iclass 23, count 0 2006.224.08:00:09.25#ibcon#read 6, iclass 23, count 0 2006.224.08:00:09.25#ibcon#end of sib2, iclass 23, count 0 2006.224.08:00:09.25#ibcon#*after write, iclass 23, count 0 2006.224.08:00:09.25#ibcon#*before return 0, iclass 23, count 0 2006.224.08:00:09.25#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.224.08:00:09.25#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.224.08:00:09.25#ibcon#about to clear, iclass 23 cls_cnt 0 2006.224.08:00:09.25#ibcon#cleared, iclass 23 cls_cnt 0 2006.224.08:00:09.25$vc4f8/va=5,7 2006.224.08:00:09.25#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.224.08:00:09.25#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.224.08:00:09.25#ibcon#ireg 11 cls_cnt 2 2006.224.08:00:09.25#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.224.08:00:09.31#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.224.08:00:09.31#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.224.08:00:09.31#ibcon#enter wrdev, iclass 25, count 2 2006.224.08:00:09.31#ibcon#first serial, iclass 25, count 2 2006.224.08:00:09.31#ibcon#enter sib2, iclass 25, count 2 2006.224.08:00:09.31#ibcon#flushed, iclass 25, count 2 2006.224.08:00:09.31#ibcon#about to write, iclass 25, count 2 2006.224.08:00:09.31#ibcon#wrote, iclass 25, count 2 2006.224.08:00:09.31#ibcon#about to read 3, iclass 25, count 2 2006.224.08:00:09.33#ibcon#read 3, iclass 25, count 2 2006.224.08:00:09.33#ibcon#about to read 4, iclass 25, count 2 2006.224.08:00:09.33#ibcon#read 4, iclass 25, count 2 2006.224.08:00:09.33#ibcon#about to read 5, iclass 25, count 2 2006.224.08:00:09.33#ibcon#read 5, iclass 25, count 2 2006.224.08:00:09.33#ibcon#about to read 6, iclass 25, count 2 2006.224.08:00:09.33#ibcon#read 6, iclass 25, count 2 2006.224.08:00:09.33#ibcon#end of sib2, iclass 25, count 2 2006.224.08:00:09.33#ibcon#*mode == 0, iclass 25, count 2 2006.224.08:00:09.33#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.224.08:00:09.33#ibcon#[25=AT05-07\r\n] 2006.224.08:00:09.33#ibcon#*before write, iclass 25, count 2 2006.224.08:00:09.33#ibcon#enter sib2, iclass 25, count 2 2006.224.08:00:09.33#ibcon#flushed, iclass 25, count 2 2006.224.08:00:09.33#ibcon#about to write, iclass 25, count 2 2006.224.08:00:09.33#ibcon#wrote, iclass 25, count 2 2006.224.08:00:09.33#ibcon#about to read 3, iclass 25, count 2 2006.224.08:00:09.36#ibcon#read 3, iclass 25, count 2 2006.224.08:00:09.36#ibcon#about to read 4, iclass 25, count 2 2006.224.08:00:09.36#ibcon#read 4, iclass 25, count 2 2006.224.08:00:09.36#ibcon#about to read 5, iclass 25, count 2 2006.224.08:00:09.36#ibcon#read 5, iclass 25, count 2 2006.224.08:00:09.36#ibcon#about to read 6, iclass 25, count 2 2006.224.08:00:09.36#ibcon#read 6, iclass 25, count 2 2006.224.08:00:09.36#ibcon#end of sib2, iclass 25, count 2 2006.224.08:00:09.36#ibcon#*after write, iclass 25, count 2 2006.224.08:00:09.36#ibcon#*before return 0, iclass 25, count 2 2006.224.08:00:09.36#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.224.08:00:09.36#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.224.08:00:09.36#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.224.08:00:09.36#ibcon#ireg 7 cls_cnt 0 2006.224.08:00:09.36#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.224.08:00:09.48#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.224.08:00:09.48#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.224.08:00:09.48#ibcon#enter wrdev, iclass 25, count 0 2006.224.08:00:09.48#ibcon#first serial, iclass 25, count 0 2006.224.08:00:09.48#ibcon#enter sib2, iclass 25, count 0 2006.224.08:00:09.48#ibcon#flushed, iclass 25, count 0 2006.224.08:00:09.48#ibcon#about to write, iclass 25, count 0 2006.224.08:00:09.48#ibcon#wrote, iclass 25, count 0 2006.224.08:00:09.48#ibcon#about to read 3, iclass 25, count 0 2006.224.08:00:09.50#ibcon#read 3, iclass 25, count 0 2006.224.08:00:09.50#ibcon#about to read 4, iclass 25, count 0 2006.224.08:00:09.50#ibcon#read 4, iclass 25, count 0 2006.224.08:00:09.50#ibcon#about to read 5, iclass 25, count 0 2006.224.08:00:09.50#ibcon#read 5, iclass 25, count 0 2006.224.08:00:09.50#ibcon#about to read 6, iclass 25, count 0 2006.224.08:00:09.50#ibcon#read 6, iclass 25, count 0 2006.224.08:00:09.50#ibcon#end of sib2, iclass 25, count 0 2006.224.08:00:09.50#ibcon#*mode == 0, iclass 25, count 0 2006.224.08:00:09.50#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.224.08:00:09.50#ibcon#[25=USB\r\n] 2006.224.08:00:09.50#ibcon#*before write, iclass 25, count 0 2006.224.08:00:09.50#ibcon#enter sib2, iclass 25, count 0 2006.224.08:00:09.50#ibcon#flushed, iclass 25, count 0 2006.224.08:00:09.50#ibcon#about to write, iclass 25, count 0 2006.224.08:00:09.50#ibcon#wrote, iclass 25, count 0 2006.224.08:00:09.50#ibcon#about to read 3, iclass 25, count 0 2006.224.08:00:09.53#ibcon#read 3, iclass 25, count 0 2006.224.08:00:09.53#ibcon#about to read 4, iclass 25, count 0 2006.224.08:00:09.53#ibcon#read 4, iclass 25, count 0 2006.224.08:00:09.53#ibcon#about to read 5, iclass 25, count 0 2006.224.08:00:09.53#ibcon#read 5, iclass 25, count 0 2006.224.08:00:09.53#ibcon#about to read 6, iclass 25, count 0 2006.224.08:00:09.53#ibcon#read 6, iclass 25, count 0 2006.224.08:00:09.53#ibcon#end of sib2, iclass 25, count 0 2006.224.08:00:09.53#ibcon#*after write, iclass 25, count 0 2006.224.08:00:09.53#ibcon#*before return 0, iclass 25, count 0 2006.224.08:00:09.53#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.224.08:00:09.53#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.224.08:00:09.53#ibcon#about to clear, iclass 25 cls_cnt 0 2006.224.08:00:09.53#ibcon#cleared, iclass 25 cls_cnt 0 2006.224.08:00:09.53$vc4f8/valo=6,772.99 2006.224.08:00:09.53#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.224.08:00:09.53#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.224.08:00:09.53#ibcon#ireg 17 cls_cnt 0 2006.224.08:00:09.53#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.224.08:00:09.53#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.224.08:00:09.53#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.224.08:00:09.53#ibcon#enter wrdev, iclass 27, count 0 2006.224.08:00:09.53#ibcon#first serial, iclass 27, count 0 2006.224.08:00:09.53#ibcon#enter sib2, iclass 27, count 0 2006.224.08:00:09.53#ibcon#flushed, iclass 27, count 0 2006.224.08:00:09.53#ibcon#about to write, iclass 27, count 0 2006.224.08:00:09.53#ibcon#wrote, iclass 27, count 0 2006.224.08:00:09.53#ibcon#about to read 3, iclass 27, count 0 2006.224.08:00:09.56#ibcon#read 3, iclass 27, count 0 2006.224.08:00:09.56#ibcon#about to read 4, iclass 27, count 0 2006.224.08:00:09.56#ibcon#read 4, iclass 27, count 0 2006.224.08:00:09.56#ibcon#about to read 5, iclass 27, count 0 2006.224.08:00:09.56#ibcon#read 5, iclass 27, count 0 2006.224.08:00:09.56#ibcon#about to read 6, iclass 27, count 0 2006.224.08:00:09.56#ibcon#read 6, iclass 27, count 0 2006.224.08:00:09.56#ibcon#end of sib2, iclass 27, count 0 2006.224.08:00:09.56#ibcon#*mode == 0, iclass 27, count 0 2006.224.08:00:09.56#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.224.08:00:09.56#ibcon#[26=FRQ=06,772.99\r\n] 2006.224.08:00:09.56#ibcon#*before write, iclass 27, count 0 2006.224.08:00:09.56#ibcon#enter sib2, iclass 27, count 0 2006.224.08:00:09.56#ibcon#flushed, iclass 27, count 0 2006.224.08:00:09.56#ibcon#about to write, iclass 27, count 0 2006.224.08:00:09.56#ibcon#wrote, iclass 27, count 0 2006.224.08:00:09.56#ibcon#about to read 3, iclass 27, count 0 2006.224.08:00:09.60#ibcon#read 3, iclass 27, count 0 2006.224.08:00:09.60#ibcon#about to read 4, iclass 27, count 0 2006.224.08:00:09.60#ibcon#read 4, iclass 27, count 0 2006.224.08:00:09.60#ibcon#about to read 5, iclass 27, count 0 2006.224.08:00:09.60#ibcon#read 5, iclass 27, count 0 2006.224.08:00:09.60#ibcon#about to read 6, iclass 27, count 0 2006.224.08:00:09.60#ibcon#read 6, iclass 27, count 0 2006.224.08:00:09.60#ibcon#end of sib2, iclass 27, count 0 2006.224.08:00:09.60#ibcon#*after write, iclass 27, count 0 2006.224.08:00:09.60#ibcon#*before return 0, iclass 27, count 0 2006.224.08:00:09.60#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.224.08:00:09.60#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.224.08:00:09.60#ibcon#about to clear, iclass 27 cls_cnt 0 2006.224.08:00:09.60#ibcon#cleared, iclass 27 cls_cnt 0 2006.224.08:00:09.60$vc4f8/va=6,6 2006.224.08:00:09.60#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.224.08:00:09.60#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.224.08:00:09.60#ibcon#ireg 11 cls_cnt 2 2006.224.08:00:09.60#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.224.08:00:09.65#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.224.08:00:09.65#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.224.08:00:09.65#ibcon#enter wrdev, iclass 29, count 2 2006.224.08:00:09.65#ibcon#first serial, iclass 29, count 2 2006.224.08:00:09.65#ibcon#enter sib2, iclass 29, count 2 2006.224.08:00:09.65#ibcon#flushed, iclass 29, count 2 2006.224.08:00:09.65#ibcon#about to write, iclass 29, count 2 2006.224.08:00:09.65#ibcon#wrote, iclass 29, count 2 2006.224.08:00:09.65#ibcon#about to read 3, iclass 29, count 2 2006.224.08:00:09.67#ibcon#read 3, iclass 29, count 2 2006.224.08:00:09.67#ibcon#about to read 4, iclass 29, count 2 2006.224.08:00:09.67#ibcon#read 4, iclass 29, count 2 2006.224.08:00:09.67#ibcon#about to read 5, iclass 29, count 2 2006.224.08:00:09.67#ibcon#read 5, iclass 29, count 2 2006.224.08:00:09.67#ibcon#about to read 6, iclass 29, count 2 2006.224.08:00:09.67#ibcon#read 6, iclass 29, count 2 2006.224.08:00:09.67#ibcon#end of sib2, iclass 29, count 2 2006.224.08:00:09.67#ibcon#*mode == 0, iclass 29, count 2 2006.224.08:00:09.67#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.224.08:00:09.67#ibcon#[25=AT06-06\r\n] 2006.224.08:00:09.67#ibcon#*before write, iclass 29, count 2 2006.224.08:00:09.67#ibcon#enter sib2, iclass 29, count 2 2006.224.08:00:09.67#ibcon#flushed, iclass 29, count 2 2006.224.08:00:09.67#ibcon#about to write, iclass 29, count 2 2006.224.08:00:09.67#ibcon#wrote, iclass 29, count 2 2006.224.08:00:09.67#ibcon#about to read 3, iclass 29, count 2 2006.224.08:00:09.70#ibcon#read 3, iclass 29, count 2 2006.224.08:00:09.70#ibcon#about to read 4, iclass 29, count 2 2006.224.08:00:09.70#ibcon#read 4, iclass 29, count 2 2006.224.08:00:09.70#ibcon#about to read 5, iclass 29, count 2 2006.224.08:00:09.70#ibcon#read 5, iclass 29, count 2 2006.224.08:00:09.70#ibcon#about to read 6, iclass 29, count 2 2006.224.08:00:09.70#ibcon#read 6, iclass 29, count 2 2006.224.08:00:09.70#ibcon#end of sib2, iclass 29, count 2 2006.224.08:00:09.70#ibcon#*after write, iclass 29, count 2 2006.224.08:00:09.70#ibcon#*before return 0, iclass 29, count 2 2006.224.08:00:09.70#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.224.08:00:09.70#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.224.08:00:09.70#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.224.08:00:09.70#ibcon#ireg 7 cls_cnt 0 2006.224.08:00:09.70#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.224.08:00:09.82#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.224.08:00:09.82#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.224.08:00:09.82#ibcon#enter wrdev, iclass 29, count 0 2006.224.08:00:09.82#ibcon#first serial, iclass 29, count 0 2006.224.08:00:09.82#ibcon#enter sib2, iclass 29, count 0 2006.224.08:00:09.82#ibcon#flushed, iclass 29, count 0 2006.224.08:00:09.82#ibcon#about to write, iclass 29, count 0 2006.224.08:00:09.82#ibcon#wrote, iclass 29, count 0 2006.224.08:00:09.82#ibcon#about to read 3, iclass 29, count 0 2006.224.08:00:09.84#ibcon#read 3, iclass 29, count 0 2006.224.08:00:09.84#ibcon#about to read 4, iclass 29, count 0 2006.224.08:00:09.84#ibcon#read 4, iclass 29, count 0 2006.224.08:00:09.84#ibcon#about to read 5, iclass 29, count 0 2006.224.08:00:09.84#ibcon#read 5, iclass 29, count 0 2006.224.08:00:09.84#ibcon#about to read 6, iclass 29, count 0 2006.224.08:00:09.84#ibcon#read 6, iclass 29, count 0 2006.224.08:00:09.84#ibcon#end of sib2, iclass 29, count 0 2006.224.08:00:09.84#ibcon#*mode == 0, iclass 29, count 0 2006.224.08:00:09.84#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.224.08:00:09.84#ibcon#[25=USB\r\n] 2006.224.08:00:09.84#ibcon#*before write, iclass 29, count 0 2006.224.08:00:09.84#ibcon#enter sib2, iclass 29, count 0 2006.224.08:00:09.84#ibcon#flushed, iclass 29, count 0 2006.224.08:00:09.84#ibcon#about to write, iclass 29, count 0 2006.224.08:00:09.84#ibcon#wrote, iclass 29, count 0 2006.224.08:00:09.84#ibcon#about to read 3, iclass 29, count 0 2006.224.08:00:09.87#ibcon#read 3, iclass 29, count 0 2006.224.08:00:09.87#ibcon#about to read 4, iclass 29, count 0 2006.224.08:00:09.87#ibcon#read 4, iclass 29, count 0 2006.224.08:00:09.87#ibcon#about to read 5, iclass 29, count 0 2006.224.08:00:09.87#ibcon#read 5, iclass 29, count 0 2006.224.08:00:09.87#ibcon#about to read 6, iclass 29, count 0 2006.224.08:00:09.87#ibcon#read 6, iclass 29, count 0 2006.224.08:00:09.87#ibcon#end of sib2, iclass 29, count 0 2006.224.08:00:09.87#ibcon#*after write, iclass 29, count 0 2006.224.08:00:09.87#ibcon#*before return 0, iclass 29, count 0 2006.224.08:00:09.87#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.224.08:00:09.87#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.224.08:00:09.87#ibcon#about to clear, iclass 29 cls_cnt 0 2006.224.08:00:09.87#ibcon#cleared, iclass 29 cls_cnt 0 2006.224.08:00:09.87$vc4f8/valo=7,832.99 2006.224.08:00:09.87#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.224.08:00:09.87#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.224.08:00:09.87#ibcon#ireg 17 cls_cnt 0 2006.224.08:00:09.87#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.224.08:00:09.87#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.224.08:00:09.87#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.224.08:00:09.87#ibcon#enter wrdev, iclass 31, count 0 2006.224.08:00:09.87#ibcon#first serial, iclass 31, count 0 2006.224.08:00:09.87#ibcon#enter sib2, iclass 31, count 0 2006.224.08:00:09.87#ibcon#flushed, iclass 31, count 0 2006.224.08:00:09.87#ibcon#about to write, iclass 31, count 0 2006.224.08:00:09.87#ibcon#wrote, iclass 31, count 0 2006.224.08:00:09.87#ibcon#about to read 3, iclass 31, count 0 2006.224.08:00:09.89#ibcon#read 3, iclass 31, count 0 2006.224.08:00:09.89#ibcon#about to read 4, iclass 31, count 0 2006.224.08:00:09.89#ibcon#read 4, iclass 31, count 0 2006.224.08:00:09.89#ibcon#about to read 5, iclass 31, count 0 2006.224.08:00:09.89#ibcon#read 5, iclass 31, count 0 2006.224.08:00:09.89#ibcon#about to read 6, iclass 31, count 0 2006.224.08:00:09.89#ibcon#read 6, iclass 31, count 0 2006.224.08:00:09.89#ibcon#end of sib2, iclass 31, count 0 2006.224.08:00:09.89#ibcon#*mode == 0, iclass 31, count 0 2006.224.08:00:09.89#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.224.08:00:09.89#ibcon#[26=FRQ=07,832.99\r\n] 2006.224.08:00:09.89#ibcon#*before write, iclass 31, count 0 2006.224.08:00:09.89#ibcon#enter sib2, iclass 31, count 0 2006.224.08:00:09.89#ibcon#flushed, iclass 31, count 0 2006.224.08:00:09.89#ibcon#about to write, iclass 31, count 0 2006.224.08:00:09.89#ibcon#wrote, iclass 31, count 0 2006.224.08:00:09.89#ibcon#about to read 3, iclass 31, count 0 2006.224.08:00:09.93#ibcon#read 3, iclass 31, count 0 2006.224.08:00:09.93#ibcon#about to read 4, iclass 31, count 0 2006.224.08:00:09.93#ibcon#read 4, iclass 31, count 0 2006.224.08:00:09.93#ibcon#about to read 5, iclass 31, count 0 2006.224.08:00:09.93#ibcon#read 5, iclass 31, count 0 2006.224.08:00:09.93#ibcon#about to read 6, iclass 31, count 0 2006.224.08:00:09.93#ibcon#read 6, iclass 31, count 0 2006.224.08:00:09.93#ibcon#end of sib2, iclass 31, count 0 2006.224.08:00:09.93#ibcon#*after write, iclass 31, count 0 2006.224.08:00:09.93#ibcon#*before return 0, iclass 31, count 0 2006.224.08:00:09.93#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.224.08:00:09.93#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.224.08:00:09.93#ibcon#about to clear, iclass 31 cls_cnt 0 2006.224.08:00:09.93#ibcon#cleared, iclass 31 cls_cnt 0 2006.224.08:00:09.93$vc4f8/va=7,6 2006.224.08:00:09.93#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.224.08:00:09.93#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.224.08:00:09.93#ibcon#ireg 11 cls_cnt 2 2006.224.08:00:09.93#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.224.08:00:09.99#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.224.08:00:09.99#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.224.08:00:09.99#ibcon#enter wrdev, iclass 33, count 2 2006.224.08:00:09.99#ibcon#first serial, iclass 33, count 2 2006.224.08:00:09.99#ibcon#enter sib2, iclass 33, count 2 2006.224.08:00:09.99#ibcon#flushed, iclass 33, count 2 2006.224.08:00:09.99#ibcon#about to write, iclass 33, count 2 2006.224.08:00:09.99#ibcon#wrote, iclass 33, count 2 2006.224.08:00:09.99#ibcon#about to read 3, iclass 33, count 2 2006.224.08:00:10.01#ibcon#read 3, iclass 33, count 2 2006.224.08:00:10.01#ibcon#about to read 4, iclass 33, count 2 2006.224.08:00:10.01#ibcon#read 4, iclass 33, count 2 2006.224.08:00:10.01#ibcon#about to read 5, iclass 33, count 2 2006.224.08:00:10.01#ibcon#read 5, iclass 33, count 2 2006.224.08:00:10.01#ibcon#about to read 6, iclass 33, count 2 2006.224.08:00:10.01#ibcon#read 6, iclass 33, count 2 2006.224.08:00:10.01#ibcon#end of sib2, iclass 33, count 2 2006.224.08:00:10.01#ibcon#*mode == 0, iclass 33, count 2 2006.224.08:00:10.01#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.224.08:00:10.01#ibcon#[25=AT07-06\r\n] 2006.224.08:00:10.01#ibcon#*before write, iclass 33, count 2 2006.224.08:00:10.01#ibcon#enter sib2, iclass 33, count 2 2006.224.08:00:10.01#ibcon#flushed, iclass 33, count 2 2006.224.08:00:10.01#ibcon#about to write, iclass 33, count 2 2006.224.08:00:10.01#ibcon#wrote, iclass 33, count 2 2006.224.08:00:10.01#ibcon#about to read 3, iclass 33, count 2 2006.224.08:00:10.04#ibcon#read 3, iclass 33, count 2 2006.224.08:00:10.04#ibcon#about to read 4, iclass 33, count 2 2006.224.08:00:10.04#ibcon#read 4, iclass 33, count 2 2006.224.08:00:10.04#ibcon#about to read 5, iclass 33, count 2 2006.224.08:00:10.04#ibcon#read 5, iclass 33, count 2 2006.224.08:00:10.04#ibcon#about to read 6, iclass 33, count 2 2006.224.08:00:10.04#ibcon#read 6, iclass 33, count 2 2006.224.08:00:10.04#ibcon#end of sib2, iclass 33, count 2 2006.224.08:00:10.04#ibcon#*after write, iclass 33, count 2 2006.224.08:00:10.04#ibcon#*before return 0, iclass 33, count 2 2006.224.08:00:10.04#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.224.08:00:10.04#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.224.08:00:10.04#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.224.08:00:10.04#ibcon#ireg 7 cls_cnt 0 2006.224.08:00:10.04#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.224.08:00:10.16#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.224.08:00:10.16#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.224.08:00:10.16#ibcon#enter wrdev, iclass 33, count 0 2006.224.08:00:10.16#ibcon#first serial, iclass 33, count 0 2006.224.08:00:10.16#ibcon#enter sib2, iclass 33, count 0 2006.224.08:00:10.16#ibcon#flushed, iclass 33, count 0 2006.224.08:00:10.16#ibcon#about to write, iclass 33, count 0 2006.224.08:00:10.16#ibcon#wrote, iclass 33, count 0 2006.224.08:00:10.16#ibcon#about to read 3, iclass 33, count 0 2006.224.08:00:10.18#ibcon#read 3, iclass 33, count 0 2006.224.08:00:10.18#ibcon#about to read 4, iclass 33, count 0 2006.224.08:00:10.18#ibcon#read 4, iclass 33, count 0 2006.224.08:00:10.18#ibcon#about to read 5, iclass 33, count 0 2006.224.08:00:10.18#ibcon#read 5, iclass 33, count 0 2006.224.08:00:10.18#ibcon#about to read 6, iclass 33, count 0 2006.224.08:00:10.18#ibcon#read 6, iclass 33, count 0 2006.224.08:00:10.18#ibcon#end of sib2, iclass 33, count 0 2006.224.08:00:10.18#ibcon#*mode == 0, iclass 33, count 0 2006.224.08:00:10.18#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.224.08:00:10.18#ibcon#[25=USB\r\n] 2006.224.08:00:10.18#ibcon#*before write, iclass 33, count 0 2006.224.08:00:10.18#ibcon#enter sib2, iclass 33, count 0 2006.224.08:00:10.18#ibcon#flushed, iclass 33, count 0 2006.224.08:00:10.18#ibcon#about to write, iclass 33, count 0 2006.224.08:00:10.18#ibcon#wrote, iclass 33, count 0 2006.224.08:00:10.18#ibcon#about to read 3, iclass 33, count 0 2006.224.08:00:10.21#ibcon#read 3, iclass 33, count 0 2006.224.08:00:10.21#ibcon#about to read 4, iclass 33, count 0 2006.224.08:00:10.21#ibcon#read 4, iclass 33, count 0 2006.224.08:00:10.21#ibcon#about to read 5, iclass 33, count 0 2006.224.08:00:10.21#ibcon#read 5, iclass 33, count 0 2006.224.08:00:10.21#ibcon#about to read 6, iclass 33, count 0 2006.224.08:00:10.21#ibcon#read 6, iclass 33, count 0 2006.224.08:00:10.21#ibcon#end of sib2, iclass 33, count 0 2006.224.08:00:10.21#ibcon#*after write, iclass 33, count 0 2006.224.08:00:10.21#ibcon#*before return 0, iclass 33, count 0 2006.224.08:00:10.21#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.224.08:00:10.21#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.224.08:00:10.21#ibcon#about to clear, iclass 33 cls_cnt 0 2006.224.08:00:10.21#ibcon#cleared, iclass 33 cls_cnt 0 2006.224.08:00:10.21$vc4f8/valo=8,852.99 2006.224.08:00:10.21#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.224.08:00:10.21#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.224.08:00:10.21#ibcon#ireg 17 cls_cnt 0 2006.224.08:00:10.21#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.224.08:00:10.21#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.224.08:00:10.21#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.224.08:00:10.21#ibcon#enter wrdev, iclass 35, count 0 2006.224.08:00:10.21#ibcon#first serial, iclass 35, count 0 2006.224.08:00:10.21#ibcon#enter sib2, iclass 35, count 0 2006.224.08:00:10.21#ibcon#flushed, iclass 35, count 0 2006.224.08:00:10.21#ibcon#about to write, iclass 35, count 0 2006.224.08:00:10.21#ibcon#wrote, iclass 35, count 0 2006.224.08:00:10.21#ibcon#about to read 3, iclass 35, count 0 2006.224.08:00:10.23#ibcon#read 3, iclass 35, count 0 2006.224.08:00:10.23#ibcon#about to read 4, iclass 35, count 0 2006.224.08:00:10.23#ibcon#read 4, iclass 35, count 0 2006.224.08:00:10.23#ibcon#about to read 5, iclass 35, count 0 2006.224.08:00:10.23#ibcon#read 5, iclass 35, count 0 2006.224.08:00:10.23#ibcon#about to read 6, iclass 35, count 0 2006.224.08:00:10.23#ibcon#read 6, iclass 35, count 0 2006.224.08:00:10.23#ibcon#end of sib2, iclass 35, count 0 2006.224.08:00:10.23#ibcon#*mode == 0, iclass 35, count 0 2006.224.08:00:10.23#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.224.08:00:10.23#ibcon#[26=FRQ=08,852.99\r\n] 2006.224.08:00:10.23#ibcon#*before write, iclass 35, count 0 2006.224.08:00:10.23#ibcon#enter sib2, iclass 35, count 0 2006.224.08:00:10.23#ibcon#flushed, iclass 35, count 0 2006.224.08:00:10.23#ibcon#about to write, iclass 35, count 0 2006.224.08:00:10.23#ibcon#wrote, iclass 35, count 0 2006.224.08:00:10.23#ibcon#about to read 3, iclass 35, count 0 2006.224.08:00:10.27#ibcon#read 3, iclass 35, count 0 2006.224.08:00:10.27#ibcon#about to read 4, iclass 35, count 0 2006.224.08:00:10.27#ibcon#read 4, iclass 35, count 0 2006.224.08:00:10.27#ibcon#about to read 5, iclass 35, count 0 2006.224.08:00:10.27#ibcon#read 5, iclass 35, count 0 2006.224.08:00:10.27#ibcon#about to read 6, iclass 35, count 0 2006.224.08:00:10.27#ibcon#read 6, iclass 35, count 0 2006.224.08:00:10.27#ibcon#end of sib2, iclass 35, count 0 2006.224.08:00:10.27#ibcon#*after write, iclass 35, count 0 2006.224.08:00:10.27#ibcon#*before return 0, iclass 35, count 0 2006.224.08:00:10.27#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.224.08:00:10.27#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.224.08:00:10.27#ibcon#about to clear, iclass 35 cls_cnt 0 2006.224.08:00:10.27#ibcon#cleared, iclass 35 cls_cnt 0 2006.224.08:00:10.27$vc4f8/va=8,7 2006.224.08:00:10.27#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.224.08:00:10.27#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.224.08:00:10.27#ibcon#ireg 11 cls_cnt 2 2006.224.08:00:10.27#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.224.08:00:10.33#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.224.08:00:10.33#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.224.08:00:10.33#ibcon#enter wrdev, iclass 37, count 2 2006.224.08:00:10.33#ibcon#first serial, iclass 37, count 2 2006.224.08:00:10.33#ibcon#enter sib2, iclass 37, count 2 2006.224.08:00:10.33#ibcon#flushed, iclass 37, count 2 2006.224.08:00:10.33#ibcon#about to write, iclass 37, count 2 2006.224.08:00:10.33#ibcon#wrote, iclass 37, count 2 2006.224.08:00:10.33#ibcon#about to read 3, iclass 37, count 2 2006.224.08:00:10.35#ibcon#read 3, iclass 37, count 2 2006.224.08:00:10.35#ibcon#about to read 4, iclass 37, count 2 2006.224.08:00:10.35#ibcon#read 4, iclass 37, count 2 2006.224.08:00:10.35#ibcon#about to read 5, iclass 37, count 2 2006.224.08:00:10.35#ibcon#read 5, iclass 37, count 2 2006.224.08:00:10.35#ibcon#about to read 6, iclass 37, count 2 2006.224.08:00:10.35#ibcon#read 6, iclass 37, count 2 2006.224.08:00:10.35#ibcon#end of sib2, iclass 37, count 2 2006.224.08:00:10.35#ibcon#*mode == 0, iclass 37, count 2 2006.224.08:00:10.35#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.224.08:00:10.35#ibcon#[25=AT08-07\r\n] 2006.224.08:00:10.35#ibcon#*before write, iclass 37, count 2 2006.224.08:00:10.35#ibcon#enter sib2, iclass 37, count 2 2006.224.08:00:10.35#ibcon#flushed, iclass 37, count 2 2006.224.08:00:10.35#ibcon#about to write, iclass 37, count 2 2006.224.08:00:10.35#ibcon#wrote, iclass 37, count 2 2006.224.08:00:10.35#ibcon#about to read 3, iclass 37, count 2 2006.224.08:00:10.38#ibcon#read 3, iclass 37, count 2 2006.224.08:00:10.38#ibcon#about to read 4, iclass 37, count 2 2006.224.08:00:10.38#ibcon#read 4, iclass 37, count 2 2006.224.08:00:10.38#ibcon#about to read 5, iclass 37, count 2 2006.224.08:00:10.38#ibcon#read 5, iclass 37, count 2 2006.224.08:00:10.38#ibcon#about to read 6, iclass 37, count 2 2006.224.08:00:10.38#ibcon#read 6, iclass 37, count 2 2006.224.08:00:10.38#ibcon#end of sib2, iclass 37, count 2 2006.224.08:00:10.38#ibcon#*after write, iclass 37, count 2 2006.224.08:00:10.38#ibcon#*before return 0, iclass 37, count 2 2006.224.08:00:10.38#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.224.08:00:10.38#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.224.08:00:10.38#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.224.08:00:10.38#ibcon#ireg 7 cls_cnt 0 2006.224.08:00:10.38#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.224.08:00:10.50#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.224.08:00:10.50#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.224.08:00:10.50#ibcon#enter wrdev, iclass 37, count 0 2006.224.08:00:10.50#ibcon#first serial, iclass 37, count 0 2006.224.08:00:10.50#ibcon#enter sib2, iclass 37, count 0 2006.224.08:00:10.50#ibcon#flushed, iclass 37, count 0 2006.224.08:00:10.50#ibcon#about to write, iclass 37, count 0 2006.224.08:00:10.50#ibcon#wrote, iclass 37, count 0 2006.224.08:00:10.50#ibcon#about to read 3, iclass 37, count 0 2006.224.08:00:10.52#ibcon#read 3, iclass 37, count 0 2006.224.08:00:10.52#ibcon#about to read 4, iclass 37, count 0 2006.224.08:00:10.52#ibcon#read 4, iclass 37, count 0 2006.224.08:00:10.52#ibcon#about to read 5, iclass 37, count 0 2006.224.08:00:10.52#ibcon#read 5, iclass 37, count 0 2006.224.08:00:10.52#ibcon#about to read 6, iclass 37, count 0 2006.224.08:00:10.52#ibcon#read 6, iclass 37, count 0 2006.224.08:00:10.52#ibcon#end of sib2, iclass 37, count 0 2006.224.08:00:10.52#ibcon#*mode == 0, iclass 37, count 0 2006.224.08:00:10.52#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.224.08:00:10.52#ibcon#[25=USB\r\n] 2006.224.08:00:10.52#ibcon#*before write, iclass 37, count 0 2006.224.08:00:10.52#ibcon#enter sib2, iclass 37, count 0 2006.224.08:00:10.52#ibcon#flushed, iclass 37, count 0 2006.224.08:00:10.52#ibcon#about to write, iclass 37, count 0 2006.224.08:00:10.52#ibcon#wrote, iclass 37, count 0 2006.224.08:00:10.52#ibcon#about to read 3, iclass 37, count 0 2006.224.08:00:10.55#ibcon#read 3, iclass 37, count 0 2006.224.08:00:10.55#ibcon#about to read 4, iclass 37, count 0 2006.224.08:00:10.55#ibcon#read 4, iclass 37, count 0 2006.224.08:00:10.55#ibcon#about to read 5, iclass 37, count 0 2006.224.08:00:10.55#ibcon#read 5, iclass 37, count 0 2006.224.08:00:10.55#ibcon#about to read 6, iclass 37, count 0 2006.224.08:00:10.55#ibcon#read 6, iclass 37, count 0 2006.224.08:00:10.55#ibcon#end of sib2, iclass 37, count 0 2006.224.08:00:10.55#ibcon#*after write, iclass 37, count 0 2006.224.08:00:10.55#ibcon#*before return 0, iclass 37, count 0 2006.224.08:00:10.55#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.224.08:00:10.55#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.224.08:00:10.55#ibcon#about to clear, iclass 37 cls_cnt 0 2006.224.08:00:10.55#ibcon#cleared, iclass 37 cls_cnt 0 2006.224.08:00:10.55$vc4f8/vblo=1,632.99 2006.224.08:00:10.55#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.224.08:00:10.55#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.224.08:00:10.55#ibcon#ireg 17 cls_cnt 0 2006.224.08:00:10.55#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.224.08:00:10.55#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.224.08:00:10.55#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.224.08:00:10.55#ibcon#enter wrdev, iclass 39, count 0 2006.224.08:00:10.55#ibcon#first serial, iclass 39, count 0 2006.224.08:00:10.55#ibcon#enter sib2, iclass 39, count 0 2006.224.08:00:10.55#ibcon#flushed, iclass 39, count 0 2006.224.08:00:10.55#ibcon#about to write, iclass 39, count 0 2006.224.08:00:10.55#ibcon#wrote, iclass 39, count 0 2006.224.08:00:10.55#ibcon#about to read 3, iclass 39, count 0 2006.224.08:00:10.57#ibcon#read 3, iclass 39, count 0 2006.224.08:00:10.57#ibcon#about to read 4, iclass 39, count 0 2006.224.08:00:10.57#ibcon#read 4, iclass 39, count 0 2006.224.08:00:10.57#ibcon#about to read 5, iclass 39, count 0 2006.224.08:00:10.57#ibcon#read 5, iclass 39, count 0 2006.224.08:00:10.57#ibcon#about to read 6, iclass 39, count 0 2006.224.08:00:10.57#ibcon#read 6, iclass 39, count 0 2006.224.08:00:10.57#ibcon#end of sib2, iclass 39, count 0 2006.224.08:00:10.57#ibcon#*mode == 0, iclass 39, count 0 2006.224.08:00:10.57#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.224.08:00:10.57#ibcon#[28=FRQ=01,632.99\r\n] 2006.224.08:00:10.57#ibcon#*before write, iclass 39, count 0 2006.224.08:00:10.57#ibcon#enter sib2, iclass 39, count 0 2006.224.08:00:10.57#ibcon#flushed, iclass 39, count 0 2006.224.08:00:10.57#ibcon#about to write, iclass 39, count 0 2006.224.08:00:10.57#ibcon#wrote, iclass 39, count 0 2006.224.08:00:10.57#ibcon#about to read 3, iclass 39, count 0 2006.224.08:00:10.61#ibcon#read 3, iclass 39, count 0 2006.224.08:00:10.61#ibcon#about to read 4, iclass 39, count 0 2006.224.08:00:10.61#ibcon#read 4, iclass 39, count 0 2006.224.08:00:10.61#ibcon#about to read 5, iclass 39, count 0 2006.224.08:00:10.61#ibcon#read 5, iclass 39, count 0 2006.224.08:00:10.61#ibcon#about to read 6, iclass 39, count 0 2006.224.08:00:10.61#ibcon#read 6, iclass 39, count 0 2006.224.08:00:10.61#ibcon#end of sib2, iclass 39, count 0 2006.224.08:00:10.61#ibcon#*after write, iclass 39, count 0 2006.224.08:00:10.61#ibcon#*before return 0, iclass 39, count 0 2006.224.08:00:10.61#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.224.08:00:10.61#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.224.08:00:10.61#ibcon#about to clear, iclass 39 cls_cnt 0 2006.224.08:00:10.61#ibcon#cleared, iclass 39 cls_cnt 0 2006.224.08:00:10.61$vc4f8/vb=1,4 2006.224.08:00:10.61#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.224.08:00:10.61#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.224.08:00:10.61#ibcon#ireg 11 cls_cnt 2 2006.224.08:00:10.61#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.224.08:00:10.61#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.224.08:00:10.61#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.224.08:00:10.61#ibcon#enter wrdev, iclass 3, count 2 2006.224.08:00:10.61#ibcon#first serial, iclass 3, count 2 2006.224.08:00:10.61#ibcon#enter sib2, iclass 3, count 2 2006.224.08:00:10.61#ibcon#flushed, iclass 3, count 2 2006.224.08:00:10.61#ibcon#about to write, iclass 3, count 2 2006.224.08:00:10.61#ibcon#wrote, iclass 3, count 2 2006.224.08:00:10.61#ibcon#about to read 3, iclass 3, count 2 2006.224.08:00:10.63#ibcon#read 3, iclass 3, count 2 2006.224.08:00:10.63#ibcon#about to read 4, iclass 3, count 2 2006.224.08:00:10.63#ibcon#read 4, iclass 3, count 2 2006.224.08:00:10.63#ibcon#about to read 5, iclass 3, count 2 2006.224.08:00:10.63#ibcon#read 5, iclass 3, count 2 2006.224.08:00:10.63#ibcon#about to read 6, iclass 3, count 2 2006.224.08:00:10.63#ibcon#read 6, iclass 3, count 2 2006.224.08:00:10.63#ibcon#end of sib2, iclass 3, count 2 2006.224.08:00:10.63#ibcon#*mode == 0, iclass 3, count 2 2006.224.08:00:10.63#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.224.08:00:10.63#ibcon#[27=AT01-04\r\n] 2006.224.08:00:10.63#ibcon#*before write, iclass 3, count 2 2006.224.08:00:10.63#ibcon#enter sib2, iclass 3, count 2 2006.224.08:00:10.63#ibcon#flushed, iclass 3, count 2 2006.224.08:00:10.63#ibcon#about to write, iclass 3, count 2 2006.224.08:00:10.63#ibcon#wrote, iclass 3, count 2 2006.224.08:00:10.63#ibcon#about to read 3, iclass 3, count 2 2006.224.08:00:10.66#ibcon#read 3, iclass 3, count 2 2006.224.08:00:10.66#ibcon#about to read 4, iclass 3, count 2 2006.224.08:00:10.66#ibcon#read 4, iclass 3, count 2 2006.224.08:00:10.66#ibcon#about to read 5, iclass 3, count 2 2006.224.08:00:10.66#ibcon#read 5, iclass 3, count 2 2006.224.08:00:10.66#ibcon#about to read 6, iclass 3, count 2 2006.224.08:00:10.66#ibcon#read 6, iclass 3, count 2 2006.224.08:00:10.66#ibcon#end of sib2, iclass 3, count 2 2006.224.08:00:10.66#ibcon#*after write, iclass 3, count 2 2006.224.08:00:10.66#ibcon#*before return 0, iclass 3, count 2 2006.224.08:00:10.66#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.224.08:00:10.66#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.224.08:00:10.66#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.224.08:00:10.66#ibcon#ireg 7 cls_cnt 0 2006.224.08:00:10.66#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.224.08:00:10.78#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.224.08:00:10.78#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.224.08:00:10.78#ibcon#enter wrdev, iclass 3, count 0 2006.224.08:00:10.78#ibcon#first serial, iclass 3, count 0 2006.224.08:00:10.78#ibcon#enter sib2, iclass 3, count 0 2006.224.08:00:10.78#ibcon#flushed, iclass 3, count 0 2006.224.08:00:10.78#ibcon#about to write, iclass 3, count 0 2006.224.08:00:10.78#ibcon#wrote, iclass 3, count 0 2006.224.08:00:10.78#ibcon#about to read 3, iclass 3, count 0 2006.224.08:00:10.80#ibcon#read 3, iclass 3, count 0 2006.224.08:00:10.80#ibcon#about to read 4, iclass 3, count 0 2006.224.08:00:10.80#ibcon#read 4, iclass 3, count 0 2006.224.08:00:10.80#ibcon#about to read 5, iclass 3, count 0 2006.224.08:00:10.80#ibcon#read 5, iclass 3, count 0 2006.224.08:00:10.80#ibcon#about to read 6, iclass 3, count 0 2006.224.08:00:10.80#ibcon#read 6, iclass 3, count 0 2006.224.08:00:10.80#ibcon#end of sib2, iclass 3, count 0 2006.224.08:00:10.80#ibcon#*mode == 0, iclass 3, count 0 2006.224.08:00:10.80#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.224.08:00:10.80#ibcon#[27=USB\r\n] 2006.224.08:00:10.80#ibcon#*before write, iclass 3, count 0 2006.224.08:00:10.80#ibcon#enter sib2, iclass 3, count 0 2006.224.08:00:10.80#ibcon#flushed, iclass 3, count 0 2006.224.08:00:10.80#ibcon#about to write, iclass 3, count 0 2006.224.08:00:10.80#ibcon#wrote, iclass 3, count 0 2006.224.08:00:10.80#ibcon#about to read 3, iclass 3, count 0 2006.224.08:00:10.83#ibcon#read 3, iclass 3, count 0 2006.224.08:00:10.83#ibcon#about to read 4, iclass 3, count 0 2006.224.08:00:10.83#ibcon#read 4, iclass 3, count 0 2006.224.08:00:10.83#ibcon#about to read 5, iclass 3, count 0 2006.224.08:00:10.83#ibcon#read 5, iclass 3, count 0 2006.224.08:00:10.83#ibcon#about to read 6, iclass 3, count 0 2006.224.08:00:10.83#ibcon#read 6, iclass 3, count 0 2006.224.08:00:10.83#ibcon#end of sib2, iclass 3, count 0 2006.224.08:00:10.83#ibcon#*after write, iclass 3, count 0 2006.224.08:00:10.83#ibcon#*before return 0, iclass 3, count 0 2006.224.08:00:10.83#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.224.08:00:10.83#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.224.08:00:10.83#ibcon#about to clear, iclass 3 cls_cnt 0 2006.224.08:00:10.83#ibcon#cleared, iclass 3 cls_cnt 0 2006.224.08:00:10.83$vc4f8/vblo=2,640.99 2006.224.08:00:10.83#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.224.08:00:10.83#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.224.08:00:10.83#ibcon#ireg 17 cls_cnt 0 2006.224.08:00:10.83#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.224.08:00:10.83#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.224.08:00:10.83#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.224.08:00:10.83#ibcon#enter wrdev, iclass 5, count 0 2006.224.08:00:10.83#ibcon#first serial, iclass 5, count 0 2006.224.08:00:10.83#ibcon#enter sib2, iclass 5, count 0 2006.224.08:00:10.83#ibcon#flushed, iclass 5, count 0 2006.224.08:00:10.83#ibcon#about to write, iclass 5, count 0 2006.224.08:00:10.83#ibcon#wrote, iclass 5, count 0 2006.224.08:00:10.83#ibcon#about to read 3, iclass 5, count 0 2006.224.08:00:10.85#ibcon#read 3, iclass 5, count 0 2006.224.08:00:10.85#ibcon#about to read 4, iclass 5, count 0 2006.224.08:00:10.85#ibcon#read 4, iclass 5, count 0 2006.224.08:00:10.85#ibcon#about to read 5, iclass 5, count 0 2006.224.08:00:10.85#ibcon#read 5, iclass 5, count 0 2006.224.08:00:10.85#ibcon#about to read 6, iclass 5, count 0 2006.224.08:00:10.85#ibcon#read 6, iclass 5, count 0 2006.224.08:00:10.85#ibcon#end of sib2, iclass 5, count 0 2006.224.08:00:10.85#ibcon#*mode == 0, iclass 5, count 0 2006.224.08:00:10.85#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.224.08:00:10.85#ibcon#[28=FRQ=02,640.99\r\n] 2006.224.08:00:10.85#ibcon#*before write, iclass 5, count 0 2006.224.08:00:10.85#ibcon#enter sib2, iclass 5, count 0 2006.224.08:00:10.85#ibcon#flushed, iclass 5, count 0 2006.224.08:00:10.85#ibcon#about to write, iclass 5, count 0 2006.224.08:00:10.85#ibcon#wrote, iclass 5, count 0 2006.224.08:00:10.85#ibcon#about to read 3, iclass 5, count 0 2006.224.08:00:10.89#ibcon#read 3, iclass 5, count 0 2006.224.08:00:10.89#ibcon#about to read 4, iclass 5, count 0 2006.224.08:00:10.89#ibcon#read 4, iclass 5, count 0 2006.224.08:00:10.89#ibcon#about to read 5, iclass 5, count 0 2006.224.08:00:10.89#ibcon#read 5, iclass 5, count 0 2006.224.08:00:10.89#ibcon#about to read 6, iclass 5, count 0 2006.224.08:00:10.89#ibcon#read 6, iclass 5, count 0 2006.224.08:00:10.89#ibcon#end of sib2, iclass 5, count 0 2006.224.08:00:10.89#ibcon#*after write, iclass 5, count 0 2006.224.08:00:10.89#ibcon#*before return 0, iclass 5, count 0 2006.224.08:00:10.89#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.224.08:00:10.89#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.224.08:00:10.89#ibcon#about to clear, iclass 5 cls_cnt 0 2006.224.08:00:10.89#ibcon#cleared, iclass 5 cls_cnt 0 2006.224.08:00:10.89$vc4f8/vb=2,4 2006.224.08:00:10.89#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.224.08:00:10.89#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.224.08:00:10.89#ibcon#ireg 11 cls_cnt 2 2006.224.08:00:10.89#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.224.08:00:10.95#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.224.08:00:10.95#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.224.08:00:10.95#ibcon#enter wrdev, iclass 7, count 2 2006.224.08:00:10.95#ibcon#first serial, iclass 7, count 2 2006.224.08:00:10.95#ibcon#enter sib2, iclass 7, count 2 2006.224.08:00:10.95#ibcon#flushed, iclass 7, count 2 2006.224.08:00:10.95#ibcon#about to write, iclass 7, count 2 2006.224.08:00:10.95#ibcon#wrote, iclass 7, count 2 2006.224.08:00:10.95#ibcon#about to read 3, iclass 7, count 2 2006.224.08:00:10.97#ibcon#read 3, iclass 7, count 2 2006.224.08:00:10.97#ibcon#about to read 4, iclass 7, count 2 2006.224.08:00:10.97#ibcon#read 4, iclass 7, count 2 2006.224.08:00:10.97#ibcon#about to read 5, iclass 7, count 2 2006.224.08:00:10.97#ibcon#read 5, iclass 7, count 2 2006.224.08:00:10.97#ibcon#about to read 6, iclass 7, count 2 2006.224.08:00:10.97#ibcon#read 6, iclass 7, count 2 2006.224.08:00:10.97#ibcon#end of sib2, iclass 7, count 2 2006.224.08:00:10.97#ibcon#*mode == 0, iclass 7, count 2 2006.224.08:00:10.97#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.224.08:00:10.97#ibcon#[27=AT02-04\r\n] 2006.224.08:00:10.97#ibcon#*before write, iclass 7, count 2 2006.224.08:00:10.97#ibcon#enter sib2, iclass 7, count 2 2006.224.08:00:10.97#ibcon#flushed, iclass 7, count 2 2006.224.08:00:10.97#ibcon#about to write, iclass 7, count 2 2006.224.08:00:10.97#ibcon#wrote, iclass 7, count 2 2006.224.08:00:10.97#ibcon#about to read 3, iclass 7, count 2 2006.224.08:00:11.00#ibcon#read 3, iclass 7, count 2 2006.224.08:00:11.00#ibcon#about to read 4, iclass 7, count 2 2006.224.08:00:11.00#ibcon#read 4, iclass 7, count 2 2006.224.08:00:11.00#ibcon#about to read 5, iclass 7, count 2 2006.224.08:00:11.00#ibcon#read 5, iclass 7, count 2 2006.224.08:00:11.00#ibcon#about to read 6, iclass 7, count 2 2006.224.08:00:11.00#ibcon#read 6, iclass 7, count 2 2006.224.08:00:11.00#ibcon#end of sib2, iclass 7, count 2 2006.224.08:00:11.00#ibcon#*after write, iclass 7, count 2 2006.224.08:00:11.00#ibcon#*before return 0, iclass 7, count 2 2006.224.08:00:11.00#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.224.08:00:11.00#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.224.08:00:11.00#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.224.08:00:11.00#ibcon#ireg 7 cls_cnt 0 2006.224.08:00:11.00#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.224.08:00:11.12#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.224.08:00:11.12#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.224.08:00:11.12#ibcon#enter wrdev, iclass 7, count 0 2006.224.08:00:11.12#ibcon#first serial, iclass 7, count 0 2006.224.08:00:11.12#ibcon#enter sib2, iclass 7, count 0 2006.224.08:00:11.12#ibcon#flushed, iclass 7, count 0 2006.224.08:00:11.12#ibcon#about to write, iclass 7, count 0 2006.224.08:00:11.12#ibcon#wrote, iclass 7, count 0 2006.224.08:00:11.12#ibcon#about to read 3, iclass 7, count 0 2006.224.08:00:11.14#ibcon#read 3, iclass 7, count 0 2006.224.08:00:11.14#ibcon#about to read 4, iclass 7, count 0 2006.224.08:00:11.14#ibcon#read 4, iclass 7, count 0 2006.224.08:00:11.14#ibcon#about to read 5, iclass 7, count 0 2006.224.08:00:11.14#ibcon#read 5, iclass 7, count 0 2006.224.08:00:11.14#ibcon#about to read 6, iclass 7, count 0 2006.224.08:00:11.14#ibcon#read 6, iclass 7, count 0 2006.224.08:00:11.14#ibcon#end of sib2, iclass 7, count 0 2006.224.08:00:11.14#ibcon#*mode == 0, iclass 7, count 0 2006.224.08:00:11.14#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.224.08:00:11.14#ibcon#[27=USB\r\n] 2006.224.08:00:11.14#ibcon#*before write, iclass 7, count 0 2006.224.08:00:11.14#ibcon#enter sib2, iclass 7, count 0 2006.224.08:00:11.14#ibcon#flushed, iclass 7, count 0 2006.224.08:00:11.14#ibcon#about to write, iclass 7, count 0 2006.224.08:00:11.14#ibcon#wrote, iclass 7, count 0 2006.224.08:00:11.14#ibcon#about to read 3, iclass 7, count 0 2006.224.08:00:11.17#ibcon#read 3, iclass 7, count 0 2006.224.08:00:11.17#ibcon#about to read 4, iclass 7, count 0 2006.224.08:00:11.17#ibcon#read 4, iclass 7, count 0 2006.224.08:00:11.17#ibcon#about to read 5, iclass 7, count 0 2006.224.08:00:11.17#ibcon#read 5, iclass 7, count 0 2006.224.08:00:11.17#ibcon#about to read 6, iclass 7, count 0 2006.224.08:00:11.17#ibcon#read 6, iclass 7, count 0 2006.224.08:00:11.17#ibcon#end of sib2, iclass 7, count 0 2006.224.08:00:11.17#ibcon#*after write, iclass 7, count 0 2006.224.08:00:11.17#ibcon#*before return 0, iclass 7, count 0 2006.224.08:00:11.17#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.224.08:00:11.17#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.224.08:00:11.17#ibcon#about to clear, iclass 7 cls_cnt 0 2006.224.08:00:11.17#ibcon#cleared, iclass 7 cls_cnt 0 2006.224.08:00:11.17$vc4f8/vblo=3,656.99 2006.224.08:00:11.17#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.224.08:00:11.17#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.224.08:00:11.17#ibcon#ireg 17 cls_cnt 0 2006.224.08:00:11.17#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.224.08:00:11.17#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.224.08:00:11.17#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.224.08:00:11.17#ibcon#enter wrdev, iclass 11, count 0 2006.224.08:00:11.17#ibcon#first serial, iclass 11, count 0 2006.224.08:00:11.17#ibcon#enter sib2, iclass 11, count 0 2006.224.08:00:11.17#ibcon#flushed, iclass 11, count 0 2006.224.08:00:11.17#ibcon#about to write, iclass 11, count 0 2006.224.08:00:11.17#ibcon#wrote, iclass 11, count 0 2006.224.08:00:11.17#ibcon#about to read 3, iclass 11, count 0 2006.224.08:00:11.20#ibcon#read 3, iclass 11, count 0 2006.224.08:00:11.20#ibcon#about to read 4, iclass 11, count 0 2006.224.08:00:11.20#ibcon#read 4, iclass 11, count 0 2006.224.08:00:11.20#ibcon#about to read 5, iclass 11, count 0 2006.224.08:00:11.20#ibcon#read 5, iclass 11, count 0 2006.224.08:00:11.20#ibcon#about to read 6, iclass 11, count 0 2006.224.08:00:11.20#ibcon#read 6, iclass 11, count 0 2006.224.08:00:11.20#ibcon#end of sib2, iclass 11, count 0 2006.224.08:00:11.20#ibcon#*mode == 0, iclass 11, count 0 2006.224.08:00:11.20#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.224.08:00:11.20#ibcon#[28=FRQ=03,656.99\r\n] 2006.224.08:00:11.20#ibcon#*before write, iclass 11, count 0 2006.224.08:00:11.20#ibcon#enter sib2, iclass 11, count 0 2006.224.08:00:11.20#ibcon#flushed, iclass 11, count 0 2006.224.08:00:11.20#ibcon#about to write, iclass 11, count 0 2006.224.08:00:11.20#ibcon#wrote, iclass 11, count 0 2006.224.08:00:11.20#ibcon#about to read 3, iclass 11, count 0 2006.224.08:00:11.24#ibcon#read 3, iclass 11, count 0 2006.224.08:00:11.24#ibcon#about to read 4, iclass 11, count 0 2006.224.08:00:11.24#ibcon#read 4, iclass 11, count 0 2006.224.08:00:11.24#ibcon#about to read 5, iclass 11, count 0 2006.224.08:00:11.24#ibcon#read 5, iclass 11, count 0 2006.224.08:00:11.24#ibcon#about to read 6, iclass 11, count 0 2006.224.08:00:11.24#ibcon#read 6, iclass 11, count 0 2006.224.08:00:11.24#ibcon#end of sib2, iclass 11, count 0 2006.224.08:00:11.24#ibcon#*after write, iclass 11, count 0 2006.224.08:00:11.24#ibcon#*before return 0, iclass 11, count 0 2006.224.08:00:11.24#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.224.08:00:11.24#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.224.08:00:11.24#ibcon#about to clear, iclass 11 cls_cnt 0 2006.224.08:00:11.24#ibcon#cleared, iclass 11 cls_cnt 0 2006.224.08:00:11.24$vc4f8/vb=3,4 2006.224.08:00:11.24#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.224.08:00:11.24#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.224.08:00:11.24#ibcon#ireg 11 cls_cnt 2 2006.224.08:00:11.24#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.224.08:00:11.29#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.224.08:00:11.29#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.224.08:00:11.29#ibcon#enter wrdev, iclass 13, count 2 2006.224.08:00:11.29#ibcon#first serial, iclass 13, count 2 2006.224.08:00:11.29#ibcon#enter sib2, iclass 13, count 2 2006.224.08:00:11.29#ibcon#flushed, iclass 13, count 2 2006.224.08:00:11.29#ibcon#about to write, iclass 13, count 2 2006.224.08:00:11.29#ibcon#wrote, iclass 13, count 2 2006.224.08:00:11.29#ibcon#about to read 3, iclass 13, count 2 2006.224.08:00:11.31#ibcon#read 3, iclass 13, count 2 2006.224.08:00:11.31#ibcon#about to read 4, iclass 13, count 2 2006.224.08:00:11.31#ibcon#read 4, iclass 13, count 2 2006.224.08:00:11.31#ibcon#about to read 5, iclass 13, count 2 2006.224.08:00:11.31#ibcon#read 5, iclass 13, count 2 2006.224.08:00:11.31#ibcon#about to read 6, iclass 13, count 2 2006.224.08:00:11.31#ibcon#read 6, iclass 13, count 2 2006.224.08:00:11.31#ibcon#end of sib2, iclass 13, count 2 2006.224.08:00:11.31#ibcon#*mode == 0, iclass 13, count 2 2006.224.08:00:11.31#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.224.08:00:11.31#ibcon#[27=AT03-04\r\n] 2006.224.08:00:11.31#ibcon#*before write, iclass 13, count 2 2006.224.08:00:11.31#ibcon#enter sib2, iclass 13, count 2 2006.224.08:00:11.31#ibcon#flushed, iclass 13, count 2 2006.224.08:00:11.31#ibcon#about to write, iclass 13, count 2 2006.224.08:00:11.31#ibcon#wrote, iclass 13, count 2 2006.224.08:00:11.31#ibcon#about to read 3, iclass 13, count 2 2006.224.08:00:11.34#ibcon#read 3, iclass 13, count 2 2006.224.08:00:11.34#ibcon#about to read 4, iclass 13, count 2 2006.224.08:00:11.34#ibcon#read 4, iclass 13, count 2 2006.224.08:00:11.34#ibcon#about to read 5, iclass 13, count 2 2006.224.08:00:11.34#ibcon#read 5, iclass 13, count 2 2006.224.08:00:11.34#ibcon#about to read 6, iclass 13, count 2 2006.224.08:00:11.34#ibcon#read 6, iclass 13, count 2 2006.224.08:00:11.34#ibcon#end of sib2, iclass 13, count 2 2006.224.08:00:11.34#ibcon#*after write, iclass 13, count 2 2006.224.08:00:11.34#ibcon#*before return 0, iclass 13, count 2 2006.224.08:00:11.34#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.224.08:00:11.34#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.224.08:00:11.34#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.224.08:00:11.34#ibcon#ireg 7 cls_cnt 0 2006.224.08:00:11.34#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.224.08:00:11.46#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.224.08:00:11.46#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.224.08:00:11.46#ibcon#enter wrdev, iclass 13, count 0 2006.224.08:00:11.46#ibcon#first serial, iclass 13, count 0 2006.224.08:00:11.46#ibcon#enter sib2, iclass 13, count 0 2006.224.08:00:11.46#ibcon#flushed, iclass 13, count 0 2006.224.08:00:11.46#ibcon#about to write, iclass 13, count 0 2006.224.08:00:11.46#ibcon#wrote, iclass 13, count 0 2006.224.08:00:11.46#ibcon#about to read 3, iclass 13, count 0 2006.224.08:00:11.48#ibcon#read 3, iclass 13, count 0 2006.224.08:00:11.48#ibcon#about to read 4, iclass 13, count 0 2006.224.08:00:11.48#ibcon#read 4, iclass 13, count 0 2006.224.08:00:11.48#ibcon#about to read 5, iclass 13, count 0 2006.224.08:00:11.48#ibcon#read 5, iclass 13, count 0 2006.224.08:00:11.48#ibcon#about to read 6, iclass 13, count 0 2006.224.08:00:11.48#ibcon#read 6, iclass 13, count 0 2006.224.08:00:11.48#ibcon#end of sib2, iclass 13, count 0 2006.224.08:00:11.48#ibcon#*mode == 0, iclass 13, count 0 2006.224.08:00:11.48#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.224.08:00:11.48#ibcon#[27=USB\r\n] 2006.224.08:00:11.48#ibcon#*before write, iclass 13, count 0 2006.224.08:00:11.48#ibcon#enter sib2, iclass 13, count 0 2006.224.08:00:11.48#ibcon#flushed, iclass 13, count 0 2006.224.08:00:11.48#ibcon#about to write, iclass 13, count 0 2006.224.08:00:11.48#ibcon#wrote, iclass 13, count 0 2006.224.08:00:11.48#ibcon#about to read 3, iclass 13, count 0 2006.224.08:00:11.51#ibcon#read 3, iclass 13, count 0 2006.224.08:00:11.51#ibcon#about to read 4, iclass 13, count 0 2006.224.08:00:11.51#ibcon#read 4, iclass 13, count 0 2006.224.08:00:11.51#ibcon#about to read 5, iclass 13, count 0 2006.224.08:00:11.51#ibcon#read 5, iclass 13, count 0 2006.224.08:00:11.51#ibcon#about to read 6, iclass 13, count 0 2006.224.08:00:11.51#ibcon#read 6, iclass 13, count 0 2006.224.08:00:11.51#ibcon#end of sib2, iclass 13, count 0 2006.224.08:00:11.51#ibcon#*after write, iclass 13, count 0 2006.224.08:00:11.51#ibcon#*before return 0, iclass 13, count 0 2006.224.08:00:11.51#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.224.08:00:11.51#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.224.08:00:11.51#ibcon#about to clear, iclass 13 cls_cnt 0 2006.224.08:00:11.51#ibcon#cleared, iclass 13 cls_cnt 0 2006.224.08:00:11.51$vc4f8/vblo=4,712.99 2006.224.08:00:11.51#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.224.08:00:11.51#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.224.08:00:11.51#ibcon#ireg 17 cls_cnt 0 2006.224.08:00:11.51#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.224.08:00:11.51#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.224.08:00:11.51#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.224.08:00:11.51#ibcon#enter wrdev, iclass 15, count 0 2006.224.08:00:11.51#ibcon#first serial, iclass 15, count 0 2006.224.08:00:11.51#ibcon#enter sib2, iclass 15, count 0 2006.224.08:00:11.51#ibcon#flushed, iclass 15, count 0 2006.224.08:00:11.51#ibcon#about to write, iclass 15, count 0 2006.224.08:00:11.51#ibcon#wrote, iclass 15, count 0 2006.224.08:00:11.51#ibcon#about to read 3, iclass 15, count 0 2006.224.08:00:11.53#ibcon#read 3, iclass 15, count 0 2006.224.08:00:11.53#ibcon#about to read 4, iclass 15, count 0 2006.224.08:00:11.53#ibcon#read 4, iclass 15, count 0 2006.224.08:00:11.53#ibcon#about to read 5, iclass 15, count 0 2006.224.08:00:11.53#ibcon#read 5, iclass 15, count 0 2006.224.08:00:11.53#ibcon#about to read 6, iclass 15, count 0 2006.224.08:00:11.53#ibcon#read 6, iclass 15, count 0 2006.224.08:00:11.53#ibcon#end of sib2, iclass 15, count 0 2006.224.08:00:11.53#ibcon#*mode == 0, iclass 15, count 0 2006.224.08:00:11.53#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.224.08:00:11.53#ibcon#[28=FRQ=04,712.99\r\n] 2006.224.08:00:11.53#ibcon#*before write, iclass 15, count 0 2006.224.08:00:11.53#ibcon#enter sib2, iclass 15, count 0 2006.224.08:00:11.53#ibcon#flushed, iclass 15, count 0 2006.224.08:00:11.53#ibcon#about to write, iclass 15, count 0 2006.224.08:00:11.53#ibcon#wrote, iclass 15, count 0 2006.224.08:00:11.53#ibcon#about to read 3, iclass 15, count 0 2006.224.08:00:11.57#ibcon#read 3, iclass 15, count 0 2006.224.08:00:11.57#ibcon#about to read 4, iclass 15, count 0 2006.224.08:00:11.57#ibcon#read 4, iclass 15, count 0 2006.224.08:00:11.57#ibcon#about to read 5, iclass 15, count 0 2006.224.08:00:11.57#ibcon#read 5, iclass 15, count 0 2006.224.08:00:11.57#ibcon#about to read 6, iclass 15, count 0 2006.224.08:00:11.57#ibcon#read 6, iclass 15, count 0 2006.224.08:00:11.57#ibcon#end of sib2, iclass 15, count 0 2006.224.08:00:11.57#ibcon#*after write, iclass 15, count 0 2006.224.08:00:11.57#ibcon#*before return 0, iclass 15, count 0 2006.224.08:00:11.57#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.224.08:00:11.57#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.224.08:00:11.57#ibcon#about to clear, iclass 15 cls_cnt 0 2006.224.08:00:11.57#ibcon#cleared, iclass 15 cls_cnt 0 2006.224.08:00:11.57$vc4f8/vb=4,4 2006.224.08:00:11.57#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.224.08:00:11.57#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.224.08:00:11.57#ibcon#ireg 11 cls_cnt 2 2006.224.08:00:11.57#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.224.08:00:11.63#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.224.08:00:11.63#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.224.08:00:11.63#ibcon#enter wrdev, iclass 17, count 2 2006.224.08:00:11.63#ibcon#first serial, iclass 17, count 2 2006.224.08:00:11.63#ibcon#enter sib2, iclass 17, count 2 2006.224.08:00:11.63#ibcon#flushed, iclass 17, count 2 2006.224.08:00:11.63#ibcon#about to write, iclass 17, count 2 2006.224.08:00:11.63#ibcon#wrote, iclass 17, count 2 2006.224.08:00:11.63#ibcon#about to read 3, iclass 17, count 2 2006.224.08:00:11.65#ibcon#read 3, iclass 17, count 2 2006.224.08:00:11.65#ibcon#about to read 4, iclass 17, count 2 2006.224.08:00:11.65#ibcon#read 4, iclass 17, count 2 2006.224.08:00:11.65#ibcon#about to read 5, iclass 17, count 2 2006.224.08:00:11.65#ibcon#read 5, iclass 17, count 2 2006.224.08:00:11.65#ibcon#about to read 6, iclass 17, count 2 2006.224.08:00:11.65#ibcon#read 6, iclass 17, count 2 2006.224.08:00:11.65#ibcon#end of sib2, iclass 17, count 2 2006.224.08:00:11.65#ibcon#*mode == 0, iclass 17, count 2 2006.224.08:00:11.65#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.224.08:00:11.65#ibcon#[27=AT04-04\r\n] 2006.224.08:00:11.65#ibcon#*before write, iclass 17, count 2 2006.224.08:00:11.65#ibcon#enter sib2, iclass 17, count 2 2006.224.08:00:11.65#ibcon#flushed, iclass 17, count 2 2006.224.08:00:11.65#ibcon#about to write, iclass 17, count 2 2006.224.08:00:11.65#ibcon#wrote, iclass 17, count 2 2006.224.08:00:11.65#ibcon#about to read 3, iclass 17, count 2 2006.224.08:00:11.68#ibcon#read 3, iclass 17, count 2 2006.224.08:00:11.68#ibcon#about to read 4, iclass 17, count 2 2006.224.08:00:11.68#ibcon#read 4, iclass 17, count 2 2006.224.08:00:11.68#ibcon#about to read 5, iclass 17, count 2 2006.224.08:00:11.68#ibcon#read 5, iclass 17, count 2 2006.224.08:00:11.68#ibcon#about to read 6, iclass 17, count 2 2006.224.08:00:11.68#ibcon#read 6, iclass 17, count 2 2006.224.08:00:11.68#ibcon#end of sib2, iclass 17, count 2 2006.224.08:00:11.68#ibcon#*after write, iclass 17, count 2 2006.224.08:00:11.68#ibcon#*before return 0, iclass 17, count 2 2006.224.08:00:11.68#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.224.08:00:11.68#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.224.08:00:11.68#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.224.08:00:11.68#ibcon#ireg 7 cls_cnt 0 2006.224.08:00:11.68#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.224.08:00:11.80#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.224.08:00:11.80#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.224.08:00:11.80#ibcon#enter wrdev, iclass 17, count 0 2006.224.08:00:11.80#ibcon#first serial, iclass 17, count 0 2006.224.08:00:11.80#ibcon#enter sib2, iclass 17, count 0 2006.224.08:00:11.80#ibcon#flushed, iclass 17, count 0 2006.224.08:00:11.80#ibcon#about to write, iclass 17, count 0 2006.224.08:00:11.80#ibcon#wrote, iclass 17, count 0 2006.224.08:00:11.80#ibcon#about to read 3, iclass 17, count 0 2006.224.08:00:11.82#ibcon#read 3, iclass 17, count 0 2006.224.08:00:11.82#ibcon#about to read 4, iclass 17, count 0 2006.224.08:00:11.82#ibcon#read 4, iclass 17, count 0 2006.224.08:00:11.82#ibcon#about to read 5, iclass 17, count 0 2006.224.08:00:11.82#ibcon#read 5, iclass 17, count 0 2006.224.08:00:11.82#ibcon#about to read 6, iclass 17, count 0 2006.224.08:00:11.82#ibcon#read 6, iclass 17, count 0 2006.224.08:00:11.82#ibcon#end of sib2, iclass 17, count 0 2006.224.08:00:11.82#ibcon#*mode == 0, iclass 17, count 0 2006.224.08:00:11.82#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.224.08:00:11.82#ibcon#[27=USB\r\n] 2006.224.08:00:11.82#ibcon#*before write, iclass 17, count 0 2006.224.08:00:11.82#ibcon#enter sib2, iclass 17, count 0 2006.224.08:00:11.82#ibcon#flushed, iclass 17, count 0 2006.224.08:00:11.82#ibcon#about to write, iclass 17, count 0 2006.224.08:00:11.82#ibcon#wrote, iclass 17, count 0 2006.224.08:00:11.82#ibcon#about to read 3, iclass 17, count 0 2006.224.08:00:11.85#ibcon#read 3, iclass 17, count 0 2006.224.08:00:11.85#ibcon#about to read 4, iclass 17, count 0 2006.224.08:00:11.85#ibcon#read 4, iclass 17, count 0 2006.224.08:00:11.85#ibcon#about to read 5, iclass 17, count 0 2006.224.08:00:11.85#ibcon#read 5, iclass 17, count 0 2006.224.08:00:11.85#ibcon#about to read 6, iclass 17, count 0 2006.224.08:00:11.85#ibcon#read 6, iclass 17, count 0 2006.224.08:00:11.85#ibcon#end of sib2, iclass 17, count 0 2006.224.08:00:11.85#ibcon#*after write, iclass 17, count 0 2006.224.08:00:11.85#ibcon#*before return 0, iclass 17, count 0 2006.224.08:00:11.85#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.224.08:00:11.85#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.224.08:00:11.85#ibcon#about to clear, iclass 17 cls_cnt 0 2006.224.08:00:11.85#ibcon#cleared, iclass 17 cls_cnt 0 2006.224.08:00:11.85$vc4f8/vblo=5,744.99 2006.224.08:00:11.85#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.224.08:00:11.85#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.224.08:00:11.85#ibcon#ireg 17 cls_cnt 0 2006.224.08:00:11.85#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.224.08:00:11.85#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.224.08:00:11.85#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.224.08:00:11.85#ibcon#enter wrdev, iclass 19, count 0 2006.224.08:00:11.85#ibcon#first serial, iclass 19, count 0 2006.224.08:00:11.85#ibcon#enter sib2, iclass 19, count 0 2006.224.08:00:11.85#ibcon#flushed, iclass 19, count 0 2006.224.08:00:11.85#ibcon#about to write, iclass 19, count 0 2006.224.08:00:11.85#ibcon#wrote, iclass 19, count 0 2006.224.08:00:11.85#ibcon#about to read 3, iclass 19, count 0 2006.224.08:00:11.87#ibcon#read 3, iclass 19, count 0 2006.224.08:00:11.87#ibcon#about to read 4, iclass 19, count 0 2006.224.08:00:11.87#ibcon#read 4, iclass 19, count 0 2006.224.08:00:11.87#ibcon#about to read 5, iclass 19, count 0 2006.224.08:00:11.87#ibcon#read 5, iclass 19, count 0 2006.224.08:00:11.87#ibcon#about to read 6, iclass 19, count 0 2006.224.08:00:11.87#ibcon#read 6, iclass 19, count 0 2006.224.08:00:11.87#ibcon#end of sib2, iclass 19, count 0 2006.224.08:00:11.87#ibcon#*mode == 0, iclass 19, count 0 2006.224.08:00:11.87#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.224.08:00:11.87#ibcon#[28=FRQ=05,744.99\r\n] 2006.224.08:00:11.87#ibcon#*before write, iclass 19, count 0 2006.224.08:00:11.87#ibcon#enter sib2, iclass 19, count 0 2006.224.08:00:11.87#ibcon#flushed, iclass 19, count 0 2006.224.08:00:11.87#ibcon#about to write, iclass 19, count 0 2006.224.08:00:11.87#ibcon#wrote, iclass 19, count 0 2006.224.08:00:11.87#ibcon#about to read 3, iclass 19, count 0 2006.224.08:00:11.91#ibcon#read 3, iclass 19, count 0 2006.224.08:00:11.91#ibcon#about to read 4, iclass 19, count 0 2006.224.08:00:11.91#ibcon#read 4, iclass 19, count 0 2006.224.08:00:11.91#ibcon#about to read 5, iclass 19, count 0 2006.224.08:00:11.91#ibcon#read 5, iclass 19, count 0 2006.224.08:00:11.91#ibcon#about to read 6, iclass 19, count 0 2006.224.08:00:11.91#ibcon#read 6, iclass 19, count 0 2006.224.08:00:11.91#ibcon#end of sib2, iclass 19, count 0 2006.224.08:00:11.91#ibcon#*after write, iclass 19, count 0 2006.224.08:00:11.91#ibcon#*before return 0, iclass 19, count 0 2006.224.08:00:11.91#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.224.08:00:11.91#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.224.08:00:11.91#ibcon#about to clear, iclass 19 cls_cnt 0 2006.224.08:00:11.91#ibcon#cleared, iclass 19 cls_cnt 0 2006.224.08:00:11.91$vc4f8/vb=5,4 2006.224.08:00:11.91#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.224.08:00:11.91#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.224.08:00:11.91#ibcon#ireg 11 cls_cnt 2 2006.224.08:00:11.91#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.224.08:00:11.97#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.224.08:00:11.97#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.224.08:00:11.97#ibcon#enter wrdev, iclass 21, count 2 2006.224.08:00:11.97#ibcon#first serial, iclass 21, count 2 2006.224.08:00:11.97#ibcon#enter sib2, iclass 21, count 2 2006.224.08:00:11.97#ibcon#flushed, iclass 21, count 2 2006.224.08:00:11.97#ibcon#about to write, iclass 21, count 2 2006.224.08:00:11.97#ibcon#wrote, iclass 21, count 2 2006.224.08:00:11.97#ibcon#about to read 3, iclass 21, count 2 2006.224.08:00:11.99#ibcon#read 3, iclass 21, count 2 2006.224.08:00:11.99#ibcon#about to read 4, iclass 21, count 2 2006.224.08:00:11.99#ibcon#read 4, iclass 21, count 2 2006.224.08:00:11.99#ibcon#about to read 5, iclass 21, count 2 2006.224.08:00:11.99#ibcon#read 5, iclass 21, count 2 2006.224.08:00:11.99#ibcon#about to read 6, iclass 21, count 2 2006.224.08:00:11.99#ibcon#read 6, iclass 21, count 2 2006.224.08:00:11.99#ibcon#end of sib2, iclass 21, count 2 2006.224.08:00:11.99#ibcon#*mode == 0, iclass 21, count 2 2006.224.08:00:11.99#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.224.08:00:11.99#ibcon#[27=AT05-04\r\n] 2006.224.08:00:11.99#ibcon#*before write, iclass 21, count 2 2006.224.08:00:11.99#ibcon#enter sib2, iclass 21, count 2 2006.224.08:00:11.99#ibcon#flushed, iclass 21, count 2 2006.224.08:00:11.99#ibcon#about to write, iclass 21, count 2 2006.224.08:00:11.99#ibcon#wrote, iclass 21, count 2 2006.224.08:00:11.99#ibcon#about to read 3, iclass 21, count 2 2006.224.08:00:12.02#ibcon#read 3, iclass 21, count 2 2006.224.08:00:12.02#ibcon#about to read 4, iclass 21, count 2 2006.224.08:00:12.02#ibcon#read 4, iclass 21, count 2 2006.224.08:00:12.02#ibcon#about to read 5, iclass 21, count 2 2006.224.08:00:12.02#ibcon#read 5, iclass 21, count 2 2006.224.08:00:12.02#ibcon#about to read 6, iclass 21, count 2 2006.224.08:00:12.02#ibcon#read 6, iclass 21, count 2 2006.224.08:00:12.02#ibcon#end of sib2, iclass 21, count 2 2006.224.08:00:12.02#ibcon#*after write, iclass 21, count 2 2006.224.08:00:12.02#ibcon#*before return 0, iclass 21, count 2 2006.224.08:00:12.02#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.224.08:00:12.02#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.224.08:00:12.02#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.224.08:00:12.02#ibcon#ireg 7 cls_cnt 0 2006.224.08:00:12.02#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.224.08:00:12.14#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.224.08:00:12.14#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.224.08:00:12.14#ibcon#enter wrdev, iclass 21, count 0 2006.224.08:00:12.14#ibcon#first serial, iclass 21, count 0 2006.224.08:00:12.14#ibcon#enter sib2, iclass 21, count 0 2006.224.08:00:12.14#ibcon#flushed, iclass 21, count 0 2006.224.08:00:12.14#ibcon#about to write, iclass 21, count 0 2006.224.08:00:12.14#ibcon#wrote, iclass 21, count 0 2006.224.08:00:12.14#ibcon#about to read 3, iclass 21, count 0 2006.224.08:00:12.16#ibcon#read 3, iclass 21, count 0 2006.224.08:00:12.16#ibcon#about to read 4, iclass 21, count 0 2006.224.08:00:12.16#ibcon#read 4, iclass 21, count 0 2006.224.08:00:12.16#ibcon#about to read 5, iclass 21, count 0 2006.224.08:00:12.16#ibcon#read 5, iclass 21, count 0 2006.224.08:00:12.16#ibcon#about to read 6, iclass 21, count 0 2006.224.08:00:12.16#ibcon#read 6, iclass 21, count 0 2006.224.08:00:12.16#ibcon#end of sib2, iclass 21, count 0 2006.224.08:00:12.16#ibcon#*mode == 0, iclass 21, count 0 2006.224.08:00:12.16#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.224.08:00:12.16#ibcon#[27=USB\r\n] 2006.224.08:00:12.16#ibcon#*before write, iclass 21, count 0 2006.224.08:00:12.16#ibcon#enter sib2, iclass 21, count 0 2006.224.08:00:12.16#ibcon#flushed, iclass 21, count 0 2006.224.08:00:12.16#ibcon#about to write, iclass 21, count 0 2006.224.08:00:12.16#ibcon#wrote, iclass 21, count 0 2006.224.08:00:12.16#ibcon#about to read 3, iclass 21, count 0 2006.224.08:00:12.19#ibcon#read 3, iclass 21, count 0 2006.224.08:00:12.19#ibcon#about to read 4, iclass 21, count 0 2006.224.08:00:12.19#ibcon#read 4, iclass 21, count 0 2006.224.08:00:12.19#ibcon#about to read 5, iclass 21, count 0 2006.224.08:00:12.19#ibcon#read 5, iclass 21, count 0 2006.224.08:00:12.19#ibcon#about to read 6, iclass 21, count 0 2006.224.08:00:12.19#ibcon#read 6, iclass 21, count 0 2006.224.08:00:12.19#ibcon#end of sib2, iclass 21, count 0 2006.224.08:00:12.19#ibcon#*after write, iclass 21, count 0 2006.224.08:00:12.19#ibcon#*before return 0, iclass 21, count 0 2006.224.08:00:12.19#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.224.08:00:12.19#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.224.08:00:12.19#ibcon#about to clear, iclass 21 cls_cnt 0 2006.224.08:00:12.19#ibcon#cleared, iclass 21 cls_cnt 0 2006.224.08:00:12.19$vc4f8/vblo=6,752.99 2006.224.08:00:12.19#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.224.08:00:12.19#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.224.08:00:12.19#ibcon#ireg 17 cls_cnt 0 2006.224.08:00:12.19#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.224.08:00:12.19#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.224.08:00:12.19#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.224.08:00:12.19#ibcon#enter wrdev, iclass 23, count 0 2006.224.08:00:12.19#ibcon#first serial, iclass 23, count 0 2006.224.08:00:12.19#ibcon#enter sib2, iclass 23, count 0 2006.224.08:00:12.19#ibcon#flushed, iclass 23, count 0 2006.224.08:00:12.19#ibcon#about to write, iclass 23, count 0 2006.224.08:00:12.19#ibcon#wrote, iclass 23, count 0 2006.224.08:00:12.19#ibcon#about to read 3, iclass 23, count 0 2006.224.08:00:12.21#ibcon#read 3, iclass 23, count 0 2006.224.08:00:12.21#ibcon#about to read 4, iclass 23, count 0 2006.224.08:00:12.21#ibcon#read 4, iclass 23, count 0 2006.224.08:00:12.21#ibcon#about to read 5, iclass 23, count 0 2006.224.08:00:12.21#ibcon#read 5, iclass 23, count 0 2006.224.08:00:12.21#ibcon#about to read 6, iclass 23, count 0 2006.224.08:00:12.21#ibcon#read 6, iclass 23, count 0 2006.224.08:00:12.21#ibcon#end of sib2, iclass 23, count 0 2006.224.08:00:12.21#ibcon#*mode == 0, iclass 23, count 0 2006.224.08:00:12.21#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.224.08:00:12.21#ibcon#[28=FRQ=06,752.99\r\n] 2006.224.08:00:12.21#ibcon#*before write, iclass 23, count 0 2006.224.08:00:12.21#ibcon#enter sib2, iclass 23, count 0 2006.224.08:00:12.21#ibcon#flushed, iclass 23, count 0 2006.224.08:00:12.21#ibcon#about to write, iclass 23, count 0 2006.224.08:00:12.21#ibcon#wrote, iclass 23, count 0 2006.224.08:00:12.21#ibcon#about to read 3, iclass 23, count 0 2006.224.08:00:12.25#ibcon#read 3, iclass 23, count 0 2006.224.08:00:12.25#ibcon#about to read 4, iclass 23, count 0 2006.224.08:00:12.25#ibcon#read 4, iclass 23, count 0 2006.224.08:00:12.25#ibcon#about to read 5, iclass 23, count 0 2006.224.08:00:12.25#ibcon#read 5, iclass 23, count 0 2006.224.08:00:12.25#ibcon#about to read 6, iclass 23, count 0 2006.224.08:00:12.25#ibcon#read 6, iclass 23, count 0 2006.224.08:00:12.25#ibcon#end of sib2, iclass 23, count 0 2006.224.08:00:12.25#ibcon#*after write, iclass 23, count 0 2006.224.08:00:12.25#ibcon#*before return 0, iclass 23, count 0 2006.224.08:00:12.25#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.224.08:00:12.25#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.224.08:00:12.25#ibcon#about to clear, iclass 23 cls_cnt 0 2006.224.08:00:12.25#ibcon#cleared, iclass 23 cls_cnt 0 2006.224.08:00:12.25$vc4f8/vb=6,4 2006.224.08:00:12.25#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.224.08:00:12.25#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.224.08:00:12.25#ibcon#ireg 11 cls_cnt 2 2006.224.08:00:12.25#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.224.08:00:12.31#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.224.08:00:12.31#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.224.08:00:12.31#ibcon#enter wrdev, iclass 25, count 2 2006.224.08:00:12.31#ibcon#first serial, iclass 25, count 2 2006.224.08:00:12.31#ibcon#enter sib2, iclass 25, count 2 2006.224.08:00:12.31#ibcon#flushed, iclass 25, count 2 2006.224.08:00:12.31#ibcon#about to write, iclass 25, count 2 2006.224.08:00:12.31#ibcon#wrote, iclass 25, count 2 2006.224.08:00:12.31#ibcon#about to read 3, iclass 25, count 2 2006.224.08:00:12.33#ibcon#read 3, iclass 25, count 2 2006.224.08:00:12.33#ibcon#about to read 4, iclass 25, count 2 2006.224.08:00:12.33#ibcon#read 4, iclass 25, count 2 2006.224.08:00:12.33#ibcon#about to read 5, iclass 25, count 2 2006.224.08:00:12.33#ibcon#read 5, iclass 25, count 2 2006.224.08:00:12.33#ibcon#about to read 6, iclass 25, count 2 2006.224.08:00:12.33#ibcon#read 6, iclass 25, count 2 2006.224.08:00:12.33#ibcon#end of sib2, iclass 25, count 2 2006.224.08:00:12.33#ibcon#*mode == 0, iclass 25, count 2 2006.224.08:00:12.33#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.224.08:00:12.33#ibcon#[27=AT06-04\r\n] 2006.224.08:00:12.33#ibcon#*before write, iclass 25, count 2 2006.224.08:00:12.33#ibcon#enter sib2, iclass 25, count 2 2006.224.08:00:12.33#ibcon#flushed, iclass 25, count 2 2006.224.08:00:12.33#ibcon#about to write, iclass 25, count 2 2006.224.08:00:12.33#ibcon#wrote, iclass 25, count 2 2006.224.08:00:12.33#ibcon#about to read 3, iclass 25, count 2 2006.224.08:00:12.36#ibcon#read 3, iclass 25, count 2 2006.224.08:00:12.36#ibcon#about to read 4, iclass 25, count 2 2006.224.08:00:12.36#ibcon#read 4, iclass 25, count 2 2006.224.08:00:12.36#ibcon#about to read 5, iclass 25, count 2 2006.224.08:00:12.36#ibcon#read 5, iclass 25, count 2 2006.224.08:00:12.36#ibcon#about to read 6, iclass 25, count 2 2006.224.08:00:12.36#ibcon#read 6, iclass 25, count 2 2006.224.08:00:12.36#ibcon#end of sib2, iclass 25, count 2 2006.224.08:00:12.36#ibcon#*after write, iclass 25, count 2 2006.224.08:00:12.36#ibcon#*before return 0, iclass 25, count 2 2006.224.08:00:12.36#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.224.08:00:12.36#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.224.08:00:12.36#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.224.08:00:12.36#ibcon#ireg 7 cls_cnt 0 2006.224.08:00:12.36#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.224.08:00:12.48#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.224.08:00:12.48#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.224.08:00:12.48#ibcon#enter wrdev, iclass 25, count 0 2006.224.08:00:12.48#ibcon#first serial, iclass 25, count 0 2006.224.08:00:12.48#ibcon#enter sib2, iclass 25, count 0 2006.224.08:00:12.48#ibcon#flushed, iclass 25, count 0 2006.224.08:00:12.48#ibcon#about to write, iclass 25, count 0 2006.224.08:00:12.48#ibcon#wrote, iclass 25, count 0 2006.224.08:00:12.48#ibcon#about to read 3, iclass 25, count 0 2006.224.08:00:12.50#ibcon#read 3, iclass 25, count 0 2006.224.08:00:12.50#ibcon#about to read 4, iclass 25, count 0 2006.224.08:00:12.50#ibcon#read 4, iclass 25, count 0 2006.224.08:00:12.50#ibcon#about to read 5, iclass 25, count 0 2006.224.08:00:12.50#ibcon#read 5, iclass 25, count 0 2006.224.08:00:12.50#ibcon#about to read 6, iclass 25, count 0 2006.224.08:00:12.50#ibcon#read 6, iclass 25, count 0 2006.224.08:00:12.50#ibcon#end of sib2, iclass 25, count 0 2006.224.08:00:12.50#ibcon#*mode == 0, iclass 25, count 0 2006.224.08:00:12.50#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.224.08:00:12.50#ibcon#[27=USB\r\n] 2006.224.08:00:12.50#ibcon#*before write, iclass 25, count 0 2006.224.08:00:12.50#ibcon#enter sib2, iclass 25, count 0 2006.224.08:00:12.50#ibcon#flushed, iclass 25, count 0 2006.224.08:00:12.50#ibcon#about to write, iclass 25, count 0 2006.224.08:00:12.50#ibcon#wrote, iclass 25, count 0 2006.224.08:00:12.50#ibcon#about to read 3, iclass 25, count 0 2006.224.08:00:12.53#ibcon#read 3, iclass 25, count 0 2006.224.08:00:12.53#ibcon#about to read 4, iclass 25, count 0 2006.224.08:00:12.53#ibcon#read 4, iclass 25, count 0 2006.224.08:00:12.53#ibcon#about to read 5, iclass 25, count 0 2006.224.08:00:12.53#ibcon#read 5, iclass 25, count 0 2006.224.08:00:12.53#ibcon#about to read 6, iclass 25, count 0 2006.224.08:00:12.53#ibcon#read 6, iclass 25, count 0 2006.224.08:00:12.53#ibcon#end of sib2, iclass 25, count 0 2006.224.08:00:12.53#ibcon#*after write, iclass 25, count 0 2006.224.08:00:12.53#ibcon#*before return 0, iclass 25, count 0 2006.224.08:00:12.53#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.224.08:00:12.53#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.224.08:00:12.53#ibcon#about to clear, iclass 25 cls_cnt 0 2006.224.08:00:12.53#ibcon#cleared, iclass 25 cls_cnt 0 2006.224.08:00:12.53$vc4f8/vabw=wide 2006.224.08:00:12.53#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.224.08:00:12.53#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.224.08:00:12.53#ibcon#ireg 8 cls_cnt 0 2006.224.08:00:12.53#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.224.08:00:12.53#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.224.08:00:12.53#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.224.08:00:12.53#ibcon#enter wrdev, iclass 27, count 0 2006.224.08:00:12.53#ibcon#first serial, iclass 27, count 0 2006.224.08:00:12.53#ibcon#enter sib2, iclass 27, count 0 2006.224.08:00:12.53#ibcon#flushed, iclass 27, count 0 2006.224.08:00:12.53#ibcon#about to write, iclass 27, count 0 2006.224.08:00:12.53#ibcon#wrote, iclass 27, count 0 2006.224.08:00:12.53#ibcon#about to read 3, iclass 27, count 0 2006.224.08:00:12.55#ibcon#read 3, iclass 27, count 0 2006.224.08:00:12.55#ibcon#about to read 4, iclass 27, count 0 2006.224.08:00:12.55#ibcon#read 4, iclass 27, count 0 2006.224.08:00:12.55#ibcon#about to read 5, iclass 27, count 0 2006.224.08:00:12.55#ibcon#read 5, iclass 27, count 0 2006.224.08:00:12.55#ibcon#about to read 6, iclass 27, count 0 2006.224.08:00:12.55#ibcon#read 6, iclass 27, count 0 2006.224.08:00:12.55#ibcon#end of sib2, iclass 27, count 0 2006.224.08:00:12.55#ibcon#*mode == 0, iclass 27, count 0 2006.224.08:00:12.55#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.224.08:00:12.55#ibcon#[25=BW32\r\n] 2006.224.08:00:12.55#ibcon#*before write, iclass 27, count 0 2006.224.08:00:12.55#ibcon#enter sib2, iclass 27, count 0 2006.224.08:00:12.55#ibcon#flushed, iclass 27, count 0 2006.224.08:00:12.55#ibcon#about to write, iclass 27, count 0 2006.224.08:00:12.55#ibcon#wrote, iclass 27, count 0 2006.224.08:00:12.55#ibcon#about to read 3, iclass 27, count 0 2006.224.08:00:12.58#ibcon#read 3, iclass 27, count 0 2006.224.08:00:12.58#ibcon#about to read 4, iclass 27, count 0 2006.224.08:00:12.58#ibcon#read 4, iclass 27, count 0 2006.224.08:00:12.58#ibcon#about to read 5, iclass 27, count 0 2006.224.08:00:12.58#ibcon#read 5, iclass 27, count 0 2006.224.08:00:12.58#ibcon#about to read 6, iclass 27, count 0 2006.224.08:00:12.58#ibcon#read 6, iclass 27, count 0 2006.224.08:00:12.58#ibcon#end of sib2, iclass 27, count 0 2006.224.08:00:12.58#ibcon#*after write, iclass 27, count 0 2006.224.08:00:12.58#ibcon#*before return 0, iclass 27, count 0 2006.224.08:00:12.58#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.224.08:00:12.58#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.224.08:00:12.58#ibcon#about to clear, iclass 27 cls_cnt 0 2006.224.08:00:12.58#ibcon#cleared, iclass 27 cls_cnt 0 2006.224.08:00:12.58$vc4f8/vbbw=wide 2006.224.08:00:12.58#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.224.08:00:12.58#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.224.08:00:12.58#ibcon#ireg 8 cls_cnt 0 2006.224.08:00:12.58#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.224.08:00:12.65#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.224.08:00:12.65#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.224.08:00:12.65#ibcon#enter wrdev, iclass 29, count 0 2006.224.08:00:12.65#ibcon#first serial, iclass 29, count 0 2006.224.08:00:12.65#ibcon#enter sib2, iclass 29, count 0 2006.224.08:00:12.65#ibcon#flushed, iclass 29, count 0 2006.224.08:00:12.65#ibcon#about to write, iclass 29, count 0 2006.224.08:00:12.65#ibcon#wrote, iclass 29, count 0 2006.224.08:00:12.65#ibcon#about to read 3, iclass 29, count 0 2006.224.08:00:12.67#ibcon#read 3, iclass 29, count 0 2006.224.08:00:12.67#ibcon#about to read 4, iclass 29, count 0 2006.224.08:00:12.67#ibcon#read 4, iclass 29, count 0 2006.224.08:00:12.67#ibcon#about to read 5, iclass 29, count 0 2006.224.08:00:12.67#ibcon#read 5, iclass 29, count 0 2006.224.08:00:12.67#ibcon#about to read 6, iclass 29, count 0 2006.224.08:00:12.67#ibcon#read 6, iclass 29, count 0 2006.224.08:00:12.67#ibcon#end of sib2, iclass 29, count 0 2006.224.08:00:12.67#ibcon#*mode == 0, iclass 29, count 0 2006.224.08:00:12.67#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.224.08:00:12.67#ibcon#[27=BW32\r\n] 2006.224.08:00:12.67#ibcon#*before write, iclass 29, count 0 2006.224.08:00:12.67#ibcon#enter sib2, iclass 29, count 0 2006.224.08:00:12.67#ibcon#flushed, iclass 29, count 0 2006.224.08:00:12.67#ibcon#about to write, iclass 29, count 0 2006.224.08:00:12.67#ibcon#wrote, iclass 29, count 0 2006.224.08:00:12.67#ibcon#about to read 3, iclass 29, count 0 2006.224.08:00:12.70#ibcon#read 3, iclass 29, count 0 2006.224.08:00:12.70#ibcon#about to read 4, iclass 29, count 0 2006.224.08:00:12.70#ibcon#read 4, iclass 29, count 0 2006.224.08:00:12.70#ibcon#about to read 5, iclass 29, count 0 2006.224.08:00:12.70#ibcon#read 5, iclass 29, count 0 2006.224.08:00:12.70#ibcon#about to read 6, iclass 29, count 0 2006.224.08:00:12.70#ibcon#read 6, iclass 29, count 0 2006.224.08:00:12.70#ibcon#end of sib2, iclass 29, count 0 2006.224.08:00:12.70#ibcon#*after write, iclass 29, count 0 2006.224.08:00:12.70#ibcon#*before return 0, iclass 29, count 0 2006.224.08:00:12.70#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.224.08:00:12.70#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.224.08:00:12.70#ibcon#about to clear, iclass 29 cls_cnt 0 2006.224.08:00:12.70#ibcon#cleared, iclass 29 cls_cnt 0 2006.224.08:00:12.70$4f8m12a/ifd4f 2006.224.08:00:12.70$ifd4f/lo= 2006.224.08:00:12.70$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.224.08:00:12.70$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.224.08:00:12.70$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.224.08:00:12.70$ifd4f/patch= 2006.224.08:00:12.70$ifd4f/patch=lo1,a1,a2,a3,a4 2006.224.08:00:12.70$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.224.08:00:12.70$ifd4f/patch=lo3,a5,a6,a7,a8 2006.224.08:00:12.70$4f8m12a/"form=m,16.000,1:2 2006.224.08:00:12.70$4f8m12a/"tpicd 2006.224.08:00:12.70$4f8m12a/echo=off 2006.224.08:00:12.70$4f8m12a/xlog=off 2006.224.08:00:12.70:!2006.224.08:00:40 2006.224.08:00:25.14#trakl#Source acquired 2006.224.08:00:25.14#flagr#flagr/antenna,acquired 2006.224.08:00:40.00:preob 2006.224.08:00:41.14/onsource/TRACKING 2006.224.08:00:41.14:!2006.224.08:00:50 2006.224.08:00:50.00:data_valid=on 2006.224.08:00:50.00:midob 2006.224.08:00:50.14/onsource/TRACKING 2006.224.08:00:50.14/wx/23.63,1004.6,100 2006.224.08:00:50.21/cable/+6.4371E-03 2006.224.08:00:51.30/va/01,08,usb,yes,48,51 2006.224.08:00:51.30/va/02,07,usb,yes,49,51 2006.224.08:00:51.30/va/03,06,usb,yes,52,52 2006.224.08:00:51.30/va/04,07,usb,yes,51,55 2006.224.08:00:51.30/va/05,07,usb,yes,59,63 2006.224.08:00:51.30/va/06,06,usb,yes,59,58 2006.224.08:00:51.30/va/07,06,usb,yes,60,59 2006.224.08:00:51.30/va/08,07,usb,yes,57,56 2006.224.08:00:51.53/valo/01,532.99,yes,locked 2006.224.08:00:51.53/valo/02,572.99,yes,locked 2006.224.08:00:51.53/valo/03,672.99,yes,locked 2006.224.08:00:51.53/valo/04,832.99,yes,locked 2006.224.08:00:51.53/valo/05,652.99,yes,locked 2006.224.08:00:51.53/valo/06,772.99,yes,locked 2006.224.08:00:51.53/valo/07,832.99,yes,locked 2006.224.08:00:51.53/valo/08,852.99,yes,locked 2006.224.08:00:52.62/vb/01,04,usb,yes,33,31 2006.224.08:00:52.62/vb/02,04,usb,yes,34,36 2006.224.08:00:52.62/vb/03,04,usb,yes,31,35 2006.224.08:00:52.62/vb/04,04,usb,yes,32,32 2006.224.08:00:52.62/vb/05,04,usb,yes,30,34 2006.224.08:00:52.62/vb/06,04,usb,yes,31,34 2006.224.08:00:52.62/vb/07,04,usb,yes,33,33 2006.224.08:00:52.62/vb/08,04,usb,yes,31,34 2006.224.08:00:52.85/vblo/01,632.99,yes,locked 2006.224.08:00:52.85/vblo/02,640.99,yes,locked 2006.224.08:00:52.85/vblo/03,656.99,yes,locked 2006.224.08:00:52.85/vblo/04,712.99,yes,locked 2006.224.08:00:52.85/vblo/05,744.99,yes,locked 2006.224.08:00:52.85/vblo/06,752.99,yes,locked 2006.224.08:00:52.85/vblo/07,734.99,yes,locked 2006.224.08:00:52.85/vblo/08,744.99,yes,locked 2006.224.08:00:53.00/vabw/8 2006.224.08:00:53.15/vbbw/8 2006.224.08:00:53.24/xfe/off,on,15.0 2006.224.08:00:53.61/ifatt/23,28,28,28 2006.224.08:00:54.07/fmout-gps/S +4.36E-07 2006.224.08:00:54.11:!2006.224.08:01:50 2006.224.08:01:50.00:data_valid=off 2006.224.08:01:50.00:postob 2006.224.08:01:50.19/cable/+6.4323E-03 2006.224.08:01:50.19/wx/23.63,1004.7,100 2006.224.08:01:51.07/fmout-gps/S +4.37E-07 2006.224.08:01:51.07:scan_name=224-0802,k06224,60 2006.224.08:01:51.07:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.224.08:01:51.13#flagr#flagr/antenna,new-source 2006.224.08:01:52.13:checkk5 2006.224.08:01:52.50/chk_autoobs//k5ts1/ autoobs is running! 2006.224.08:01:52.87/chk_autoobs//k5ts2/ autoobs is running! 2006.224.08:01:53.25/chk_autoobs//k5ts3/ autoobs is running! 2006.224.08:01:53.62/chk_autoobs//k5ts4/ autoobs is running! 2006.224.08:01:53.98/chk_obsdata//k5ts1/T2240800??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.08:01:54.35/chk_obsdata//k5ts2/T2240800??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.08:01:54.72/chk_obsdata//k5ts3/T2240800??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.08:01:55.08/chk_obsdata//k5ts4/T2240800??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.08:01:55.77/k5log//k5ts1_log_newline 2006.224.08:01:56.46/k5log//k5ts2_log_newline 2006.224.08:01:57.14/k5log//k5ts3_log_newline 2006.224.08:01:57.83/k5log//k5ts4_log_newline 2006.224.08:01:57.85/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.224.08:01:57.85:4f8m12a=2 2006.224.08:01:57.85$4f8m12a/echo=on 2006.224.08:01:57.85$4f8m12a/pcalon 2006.224.08:01:57.85$pcalon/"no phase cal control is implemented here 2006.224.08:01:57.85$4f8m12a/"tpicd=stop 2006.224.08:01:57.85$4f8m12a/vc4f8 2006.224.08:01:57.85$vc4f8/valo=1,532.99 2006.224.08:01:57.85#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.224.08:01:57.85#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.224.08:01:57.85#ibcon#ireg 17 cls_cnt 0 2006.224.08:01:57.85#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.224.08:01:57.85#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.224.08:01:57.85#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.224.08:01:57.85#ibcon#enter wrdev, iclass 40, count 0 2006.224.08:01:57.85#ibcon#first serial, iclass 40, count 0 2006.224.08:01:57.85#ibcon#enter sib2, iclass 40, count 0 2006.224.08:01:57.85#ibcon#flushed, iclass 40, count 0 2006.224.08:01:57.85#ibcon#about to write, iclass 40, count 0 2006.224.08:01:57.85#ibcon#wrote, iclass 40, count 0 2006.224.08:01:57.85#ibcon#about to read 3, iclass 40, count 0 2006.224.08:01:57.87#ibcon#read 3, iclass 40, count 0 2006.224.08:01:57.87#ibcon#about to read 4, iclass 40, count 0 2006.224.08:01:57.87#ibcon#read 4, iclass 40, count 0 2006.224.08:01:57.87#ibcon#about to read 5, iclass 40, count 0 2006.224.08:01:57.87#ibcon#read 5, iclass 40, count 0 2006.224.08:01:57.87#ibcon#about to read 6, iclass 40, count 0 2006.224.08:01:57.87#ibcon#read 6, iclass 40, count 0 2006.224.08:01:57.87#ibcon#end of sib2, iclass 40, count 0 2006.224.08:01:57.87#ibcon#*mode == 0, iclass 40, count 0 2006.224.08:01:57.87#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.224.08:01:57.87#ibcon#[26=FRQ=01,532.99\r\n] 2006.224.08:01:57.87#ibcon#*before write, iclass 40, count 0 2006.224.08:01:57.87#ibcon#enter sib2, iclass 40, count 0 2006.224.08:01:57.87#ibcon#flushed, iclass 40, count 0 2006.224.08:01:57.87#ibcon#about to write, iclass 40, count 0 2006.224.08:01:57.87#ibcon#wrote, iclass 40, count 0 2006.224.08:01:57.87#ibcon#about to read 3, iclass 40, count 0 2006.224.08:01:57.92#ibcon#read 3, iclass 40, count 0 2006.224.08:01:57.92#ibcon#about to read 4, iclass 40, count 0 2006.224.08:01:57.92#ibcon#read 4, iclass 40, count 0 2006.224.08:01:57.92#ibcon#about to read 5, iclass 40, count 0 2006.224.08:01:57.92#ibcon#read 5, iclass 40, count 0 2006.224.08:01:57.92#ibcon#about to read 6, iclass 40, count 0 2006.224.08:01:57.92#ibcon#read 6, iclass 40, count 0 2006.224.08:01:57.92#ibcon#end of sib2, iclass 40, count 0 2006.224.08:01:57.92#ibcon#*after write, iclass 40, count 0 2006.224.08:01:57.92#ibcon#*before return 0, iclass 40, count 0 2006.224.08:01:57.92#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.224.08:01:57.92#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.224.08:01:57.92#ibcon#about to clear, iclass 40 cls_cnt 0 2006.224.08:01:57.92#ibcon#cleared, iclass 40 cls_cnt 0 2006.224.08:01:57.92$vc4f8/va=1,8 2006.224.08:01:57.92#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.224.08:01:57.92#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.224.08:01:57.92#ibcon#ireg 11 cls_cnt 2 2006.224.08:01:57.92#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.224.08:01:57.92#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.224.08:01:57.92#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.224.08:01:57.92#ibcon#enter wrdev, iclass 4, count 2 2006.224.08:01:57.92#ibcon#first serial, iclass 4, count 2 2006.224.08:01:57.92#ibcon#enter sib2, iclass 4, count 2 2006.224.08:01:57.92#ibcon#flushed, iclass 4, count 2 2006.224.08:01:57.92#ibcon#about to write, iclass 4, count 2 2006.224.08:01:57.92#ibcon#wrote, iclass 4, count 2 2006.224.08:01:57.92#ibcon#about to read 3, iclass 4, count 2 2006.224.08:01:57.94#ibcon#read 3, iclass 4, count 2 2006.224.08:01:57.94#ibcon#about to read 4, iclass 4, count 2 2006.224.08:01:57.94#ibcon#read 4, iclass 4, count 2 2006.224.08:01:57.94#ibcon#about to read 5, iclass 4, count 2 2006.224.08:01:57.94#ibcon#read 5, iclass 4, count 2 2006.224.08:01:57.94#ibcon#about to read 6, iclass 4, count 2 2006.224.08:01:57.94#ibcon#read 6, iclass 4, count 2 2006.224.08:01:57.94#ibcon#end of sib2, iclass 4, count 2 2006.224.08:01:57.94#ibcon#*mode == 0, iclass 4, count 2 2006.224.08:01:57.94#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.224.08:01:57.94#ibcon#[25=AT01-08\r\n] 2006.224.08:01:57.94#ibcon#*before write, iclass 4, count 2 2006.224.08:01:57.94#ibcon#enter sib2, iclass 4, count 2 2006.224.08:01:57.94#ibcon#flushed, iclass 4, count 2 2006.224.08:01:57.94#ibcon#about to write, iclass 4, count 2 2006.224.08:01:57.94#ibcon#wrote, iclass 4, count 2 2006.224.08:01:57.94#ibcon#about to read 3, iclass 4, count 2 2006.224.08:01:57.97#ibcon#read 3, iclass 4, count 2 2006.224.08:01:57.97#ibcon#about to read 4, iclass 4, count 2 2006.224.08:01:57.97#ibcon#read 4, iclass 4, count 2 2006.224.08:01:57.97#ibcon#about to read 5, iclass 4, count 2 2006.224.08:01:57.97#ibcon#read 5, iclass 4, count 2 2006.224.08:01:57.97#ibcon#about to read 6, iclass 4, count 2 2006.224.08:01:57.97#ibcon#read 6, iclass 4, count 2 2006.224.08:01:57.97#ibcon#end of sib2, iclass 4, count 2 2006.224.08:01:57.97#ibcon#*after write, iclass 4, count 2 2006.224.08:01:57.97#ibcon#*before return 0, iclass 4, count 2 2006.224.08:01:57.97#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.224.08:01:57.97#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.224.08:01:57.97#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.224.08:01:57.97#ibcon#ireg 7 cls_cnt 0 2006.224.08:01:57.97#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.224.08:01:58.09#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.224.08:01:58.09#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.224.08:01:58.09#ibcon#enter wrdev, iclass 4, count 0 2006.224.08:01:58.09#ibcon#first serial, iclass 4, count 0 2006.224.08:01:58.09#ibcon#enter sib2, iclass 4, count 0 2006.224.08:01:58.09#ibcon#flushed, iclass 4, count 0 2006.224.08:01:58.09#ibcon#about to write, iclass 4, count 0 2006.224.08:01:58.09#ibcon#wrote, iclass 4, count 0 2006.224.08:01:58.09#ibcon#about to read 3, iclass 4, count 0 2006.224.08:01:58.11#ibcon#read 3, iclass 4, count 0 2006.224.08:01:58.11#ibcon#about to read 4, iclass 4, count 0 2006.224.08:01:58.11#ibcon#read 4, iclass 4, count 0 2006.224.08:01:58.11#ibcon#about to read 5, iclass 4, count 0 2006.224.08:01:58.11#ibcon#read 5, iclass 4, count 0 2006.224.08:01:58.11#ibcon#about to read 6, iclass 4, count 0 2006.224.08:01:58.11#ibcon#read 6, iclass 4, count 0 2006.224.08:01:58.11#ibcon#end of sib2, iclass 4, count 0 2006.224.08:01:58.11#ibcon#*mode == 0, iclass 4, count 0 2006.224.08:01:58.11#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.224.08:01:58.11#ibcon#[25=USB\r\n] 2006.224.08:01:58.11#ibcon#*before write, iclass 4, count 0 2006.224.08:01:58.11#ibcon#enter sib2, iclass 4, count 0 2006.224.08:01:58.11#ibcon#flushed, iclass 4, count 0 2006.224.08:01:58.11#ibcon#about to write, iclass 4, count 0 2006.224.08:01:58.11#ibcon#wrote, iclass 4, count 0 2006.224.08:01:58.11#ibcon#about to read 3, iclass 4, count 0 2006.224.08:01:58.14#ibcon#read 3, iclass 4, count 0 2006.224.08:01:58.14#ibcon#about to read 4, iclass 4, count 0 2006.224.08:01:58.14#ibcon#read 4, iclass 4, count 0 2006.224.08:01:58.14#ibcon#about to read 5, iclass 4, count 0 2006.224.08:01:58.14#ibcon#read 5, iclass 4, count 0 2006.224.08:01:58.14#ibcon#about to read 6, iclass 4, count 0 2006.224.08:01:58.14#ibcon#read 6, iclass 4, count 0 2006.224.08:01:58.14#ibcon#end of sib2, iclass 4, count 0 2006.224.08:01:58.14#ibcon#*after write, iclass 4, count 0 2006.224.08:01:58.14#ibcon#*before return 0, iclass 4, count 0 2006.224.08:01:58.14#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.224.08:01:58.14#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.224.08:01:58.14#ibcon#about to clear, iclass 4 cls_cnt 0 2006.224.08:01:58.14#ibcon#cleared, iclass 4 cls_cnt 0 2006.224.08:01:58.14$vc4f8/valo=2,572.99 2006.224.08:01:58.14#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.224.08:01:58.14#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.224.08:01:58.14#ibcon#ireg 17 cls_cnt 0 2006.224.08:01:58.14#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.224.08:01:58.14#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.224.08:01:58.14#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.224.08:01:58.14#ibcon#enter wrdev, iclass 6, count 0 2006.224.08:01:58.14#ibcon#first serial, iclass 6, count 0 2006.224.08:01:58.14#ibcon#enter sib2, iclass 6, count 0 2006.224.08:01:58.14#ibcon#flushed, iclass 6, count 0 2006.224.08:01:58.14#ibcon#about to write, iclass 6, count 0 2006.224.08:01:58.14#ibcon#wrote, iclass 6, count 0 2006.224.08:01:58.14#ibcon#about to read 3, iclass 6, count 0 2006.224.08:01:58.17#ibcon#read 3, iclass 6, count 0 2006.224.08:01:58.17#ibcon#about to read 4, iclass 6, count 0 2006.224.08:01:58.17#ibcon#read 4, iclass 6, count 0 2006.224.08:01:58.17#ibcon#about to read 5, iclass 6, count 0 2006.224.08:01:58.17#ibcon#read 5, iclass 6, count 0 2006.224.08:01:58.17#ibcon#about to read 6, iclass 6, count 0 2006.224.08:01:58.17#ibcon#read 6, iclass 6, count 0 2006.224.08:01:58.17#ibcon#end of sib2, iclass 6, count 0 2006.224.08:01:58.17#ibcon#*mode == 0, iclass 6, count 0 2006.224.08:01:58.17#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.224.08:01:58.17#ibcon#[26=FRQ=02,572.99\r\n] 2006.224.08:01:58.17#ibcon#*before write, iclass 6, count 0 2006.224.08:01:58.17#ibcon#enter sib2, iclass 6, count 0 2006.224.08:01:58.17#ibcon#flushed, iclass 6, count 0 2006.224.08:01:58.17#ibcon#about to write, iclass 6, count 0 2006.224.08:01:58.17#ibcon#wrote, iclass 6, count 0 2006.224.08:01:58.17#ibcon#about to read 3, iclass 6, count 0 2006.224.08:01:58.21#ibcon#read 3, iclass 6, count 0 2006.224.08:01:58.21#ibcon#about to read 4, iclass 6, count 0 2006.224.08:01:58.21#ibcon#read 4, iclass 6, count 0 2006.224.08:01:58.21#ibcon#about to read 5, iclass 6, count 0 2006.224.08:01:58.21#ibcon#read 5, iclass 6, count 0 2006.224.08:01:58.21#ibcon#about to read 6, iclass 6, count 0 2006.224.08:01:58.21#ibcon#read 6, iclass 6, count 0 2006.224.08:01:58.21#ibcon#end of sib2, iclass 6, count 0 2006.224.08:01:58.21#ibcon#*after write, iclass 6, count 0 2006.224.08:01:58.21#ibcon#*before return 0, iclass 6, count 0 2006.224.08:01:58.21#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.224.08:01:58.21#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.224.08:01:58.21#ibcon#about to clear, iclass 6 cls_cnt 0 2006.224.08:01:58.21#ibcon#cleared, iclass 6 cls_cnt 0 2006.224.08:01:58.21$vc4f8/va=2,7 2006.224.08:01:58.21#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.224.08:01:58.21#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.224.08:01:58.21#ibcon#ireg 11 cls_cnt 2 2006.224.08:01:58.21#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.224.08:01:58.26#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.224.08:01:58.26#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.224.08:01:58.26#ibcon#enter wrdev, iclass 10, count 2 2006.224.08:01:58.26#ibcon#first serial, iclass 10, count 2 2006.224.08:01:58.26#ibcon#enter sib2, iclass 10, count 2 2006.224.08:01:58.26#ibcon#flushed, iclass 10, count 2 2006.224.08:01:58.26#ibcon#about to write, iclass 10, count 2 2006.224.08:01:58.26#ibcon#wrote, iclass 10, count 2 2006.224.08:01:58.26#ibcon#about to read 3, iclass 10, count 2 2006.224.08:01:58.28#ibcon#read 3, iclass 10, count 2 2006.224.08:01:58.28#ibcon#about to read 4, iclass 10, count 2 2006.224.08:01:58.28#ibcon#read 4, iclass 10, count 2 2006.224.08:01:58.28#ibcon#about to read 5, iclass 10, count 2 2006.224.08:01:58.28#ibcon#read 5, iclass 10, count 2 2006.224.08:01:58.28#ibcon#about to read 6, iclass 10, count 2 2006.224.08:01:58.28#ibcon#read 6, iclass 10, count 2 2006.224.08:01:58.28#ibcon#end of sib2, iclass 10, count 2 2006.224.08:01:58.28#ibcon#*mode == 0, iclass 10, count 2 2006.224.08:01:58.28#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.224.08:01:58.28#ibcon#[25=AT02-07\r\n] 2006.224.08:01:58.28#ibcon#*before write, iclass 10, count 2 2006.224.08:01:58.28#ibcon#enter sib2, iclass 10, count 2 2006.224.08:01:58.28#ibcon#flushed, iclass 10, count 2 2006.224.08:01:58.28#ibcon#about to write, iclass 10, count 2 2006.224.08:01:58.28#ibcon#wrote, iclass 10, count 2 2006.224.08:01:58.28#ibcon#about to read 3, iclass 10, count 2 2006.224.08:01:58.31#ibcon#read 3, iclass 10, count 2 2006.224.08:01:58.31#ibcon#about to read 4, iclass 10, count 2 2006.224.08:01:58.31#ibcon#read 4, iclass 10, count 2 2006.224.08:01:58.31#ibcon#about to read 5, iclass 10, count 2 2006.224.08:01:58.31#ibcon#read 5, iclass 10, count 2 2006.224.08:01:58.31#ibcon#about to read 6, iclass 10, count 2 2006.224.08:01:58.31#ibcon#read 6, iclass 10, count 2 2006.224.08:01:58.31#ibcon#end of sib2, iclass 10, count 2 2006.224.08:01:58.31#ibcon#*after write, iclass 10, count 2 2006.224.08:01:58.31#ibcon#*before return 0, iclass 10, count 2 2006.224.08:01:58.31#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.224.08:01:58.31#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.224.08:01:58.31#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.224.08:01:58.31#ibcon#ireg 7 cls_cnt 0 2006.224.08:01:58.31#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.224.08:01:58.43#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.224.08:01:58.43#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.224.08:01:58.43#ibcon#enter wrdev, iclass 10, count 0 2006.224.08:01:58.43#ibcon#first serial, iclass 10, count 0 2006.224.08:01:58.43#ibcon#enter sib2, iclass 10, count 0 2006.224.08:01:58.43#ibcon#flushed, iclass 10, count 0 2006.224.08:01:58.43#ibcon#about to write, iclass 10, count 0 2006.224.08:01:58.43#ibcon#wrote, iclass 10, count 0 2006.224.08:01:58.43#ibcon#about to read 3, iclass 10, count 0 2006.224.08:01:58.45#ibcon#read 3, iclass 10, count 0 2006.224.08:01:58.45#ibcon#about to read 4, iclass 10, count 0 2006.224.08:01:58.45#ibcon#read 4, iclass 10, count 0 2006.224.08:01:58.45#ibcon#about to read 5, iclass 10, count 0 2006.224.08:01:58.45#ibcon#read 5, iclass 10, count 0 2006.224.08:01:58.45#ibcon#about to read 6, iclass 10, count 0 2006.224.08:01:58.45#ibcon#read 6, iclass 10, count 0 2006.224.08:01:58.45#ibcon#end of sib2, iclass 10, count 0 2006.224.08:01:58.45#ibcon#*mode == 0, iclass 10, count 0 2006.224.08:01:58.45#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.224.08:01:58.45#ibcon#[25=USB\r\n] 2006.224.08:01:58.45#ibcon#*before write, iclass 10, count 0 2006.224.08:01:58.45#ibcon#enter sib2, iclass 10, count 0 2006.224.08:01:58.45#ibcon#flushed, iclass 10, count 0 2006.224.08:01:58.45#ibcon#about to write, iclass 10, count 0 2006.224.08:01:58.45#ibcon#wrote, iclass 10, count 0 2006.224.08:01:58.45#ibcon#about to read 3, iclass 10, count 0 2006.224.08:01:58.48#ibcon#read 3, iclass 10, count 0 2006.224.08:01:58.48#ibcon#about to read 4, iclass 10, count 0 2006.224.08:01:58.48#ibcon#read 4, iclass 10, count 0 2006.224.08:01:58.48#ibcon#about to read 5, iclass 10, count 0 2006.224.08:01:58.48#ibcon#read 5, iclass 10, count 0 2006.224.08:01:58.48#ibcon#about to read 6, iclass 10, count 0 2006.224.08:01:58.48#ibcon#read 6, iclass 10, count 0 2006.224.08:01:58.48#ibcon#end of sib2, iclass 10, count 0 2006.224.08:01:58.48#ibcon#*after write, iclass 10, count 0 2006.224.08:01:58.48#ibcon#*before return 0, iclass 10, count 0 2006.224.08:01:58.48#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.224.08:01:58.48#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.224.08:01:58.48#ibcon#about to clear, iclass 10 cls_cnt 0 2006.224.08:01:58.48#ibcon#cleared, iclass 10 cls_cnt 0 2006.224.08:01:58.48$vc4f8/valo=3,672.99 2006.224.08:01:58.48#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.224.08:01:58.48#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.224.08:01:58.48#ibcon#ireg 17 cls_cnt 0 2006.224.08:01:58.48#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.224.08:01:58.48#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.224.08:01:58.48#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.224.08:01:58.48#ibcon#enter wrdev, iclass 12, count 0 2006.224.08:01:58.48#ibcon#first serial, iclass 12, count 0 2006.224.08:01:58.48#ibcon#enter sib2, iclass 12, count 0 2006.224.08:01:58.48#ibcon#flushed, iclass 12, count 0 2006.224.08:01:58.48#ibcon#about to write, iclass 12, count 0 2006.224.08:01:58.48#ibcon#wrote, iclass 12, count 0 2006.224.08:01:58.48#ibcon#about to read 3, iclass 12, count 0 2006.224.08:01:58.51#ibcon#read 3, iclass 12, count 0 2006.224.08:01:58.51#ibcon#about to read 4, iclass 12, count 0 2006.224.08:01:58.51#ibcon#read 4, iclass 12, count 0 2006.224.08:01:58.51#ibcon#about to read 5, iclass 12, count 0 2006.224.08:01:58.51#ibcon#read 5, iclass 12, count 0 2006.224.08:01:58.51#ibcon#about to read 6, iclass 12, count 0 2006.224.08:01:58.51#ibcon#read 6, iclass 12, count 0 2006.224.08:01:58.51#ibcon#end of sib2, iclass 12, count 0 2006.224.08:01:58.51#ibcon#*mode == 0, iclass 12, count 0 2006.224.08:01:58.51#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.224.08:01:58.51#ibcon#[26=FRQ=03,672.99\r\n] 2006.224.08:01:58.51#ibcon#*before write, iclass 12, count 0 2006.224.08:01:58.51#ibcon#enter sib2, iclass 12, count 0 2006.224.08:01:58.51#ibcon#flushed, iclass 12, count 0 2006.224.08:01:58.51#ibcon#about to write, iclass 12, count 0 2006.224.08:01:58.51#ibcon#wrote, iclass 12, count 0 2006.224.08:01:58.51#ibcon#about to read 3, iclass 12, count 0 2006.224.08:01:58.55#ibcon#read 3, iclass 12, count 0 2006.224.08:01:58.55#ibcon#about to read 4, iclass 12, count 0 2006.224.08:01:58.55#ibcon#read 4, iclass 12, count 0 2006.224.08:01:58.55#ibcon#about to read 5, iclass 12, count 0 2006.224.08:01:58.55#ibcon#read 5, iclass 12, count 0 2006.224.08:01:58.55#ibcon#about to read 6, iclass 12, count 0 2006.224.08:01:58.55#ibcon#read 6, iclass 12, count 0 2006.224.08:01:58.55#ibcon#end of sib2, iclass 12, count 0 2006.224.08:01:58.55#ibcon#*after write, iclass 12, count 0 2006.224.08:01:58.55#ibcon#*before return 0, iclass 12, count 0 2006.224.08:01:58.55#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.224.08:01:58.55#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.224.08:01:58.55#ibcon#about to clear, iclass 12 cls_cnt 0 2006.224.08:01:58.55#ibcon#cleared, iclass 12 cls_cnt 0 2006.224.08:01:58.55$vc4f8/va=3,6 2006.224.08:01:58.55#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.224.08:01:58.55#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.224.08:01:58.55#ibcon#ireg 11 cls_cnt 2 2006.224.08:01:58.55#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.224.08:01:58.60#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.224.08:01:58.60#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.224.08:01:58.60#ibcon#enter wrdev, iclass 14, count 2 2006.224.08:01:58.60#ibcon#first serial, iclass 14, count 2 2006.224.08:01:58.60#ibcon#enter sib2, iclass 14, count 2 2006.224.08:01:58.60#ibcon#flushed, iclass 14, count 2 2006.224.08:01:58.60#ibcon#about to write, iclass 14, count 2 2006.224.08:01:58.60#ibcon#wrote, iclass 14, count 2 2006.224.08:01:58.60#ibcon#about to read 3, iclass 14, count 2 2006.224.08:01:58.62#ibcon#read 3, iclass 14, count 2 2006.224.08:01:58.62#ibcon#about to read 4, iclass 14, count 2 2006.224.08:01:58.62#ibcon#read 4, iclass 14, count 2 2006.224.08:01:58.62#ibcon#about to read 5, iclass 14, count 2 2006.224.08:01:58.62#ibcon#read 5, iclass 14, count 2 2006.224.08:01:58.62#ibcon#about to read 6, iclass 14, count 2 2006.224.08:01:58.62#ibcon#read 6, iclass 14, count 2 2006.224.08:01:58.62#ibcon#end of sib2, iclass 14, count 2 2006.224.08:01:58.62#ibcon#*mode == 0, iclass 14, count 2 2006.224.08:01:58.62#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.224.08:01:58.62#ibcon#[25=AT03-06\r\n] 2006.224.08:01:58.62#ibcon#*before write, iclass 14, count 2 2006.224.08:01:58.62#ibcon#enter sib2, iclass 14, count 2 2006.224.08:01:58.62#ibcon#flushed, iclass 14, count 2 2006.224.08:01:58.62#ibcon#about to write, iclass 14, count 2 2006.224.08:01:58.62#ibcon#wrote, iclass 14, count 2 2006.224.08:01:58.62#ibcon#about to read 3, iclass 14, count 2 2006.224.08:01:58.65#ibcon#read 3, iclass 14, count 2 2006.224.08:01:58.65#ibcon#about to read 4, iclass 14, count 2 2006.224.08:01:58.65#ibcon#read 4, iclass 14, count 2 2006.224.08:01:58.65#ibcon#about to read 5, iclass 14, count 2 2006.224.08:01:58.65#ibcon#read 5, iclass 14, count 2 2006.224.08:01:58.65#ibcon#about to read 6, iclass 14, count 2 2006.224.08:01:58.65#ibcon#read 6, iclass 14, count 2 2006.224.08:01:58.65#ibcon#end of sib2, iclass 14, count 2 2006.224.08:01:58.65#ibcon#*after write, iclass 14, count 2 2006.224.08:01:58.65#ibcon#*before return 0, iclass 14, count 2 2006.224.08:01:58.65#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.224.08:01:58.65#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.224.08:01:58.65#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.224.08:01:58.65#ibcon#ireg 7 cls_cnt 0 2006.224.08:01:58.65#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.224.08:01:58.77#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.224.08:01:58.77#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.224.08:01:58.77#ibcon#enter wrdev, iclass 14, count 0 2006.224.08:01:58.77#ibcon#first serial, iclass 14, count 0 2006.224.08:01:58.77#ibcon#enter sib2, iclass 14, count 0 2006.224.08:01:58.77#ibcon#flushed, iclass 14, count 0 2006.224.08:01:58.77#ibcon#about to write, iclass 14, count 0 2006.224.08:01:58.77#ibcon#wrote, iclass 14, count 0 2006.224.08:01:58.77#ibcon#about to read 3, iclass 14, count 0 2006.224.08:01:58.79#ibcon#read 3, iclass 14, count 0 2006.224.08:01:58.79#ibcon#about to read 4, iclass 14, count 0 2006.224.08:01:58.79#ibcon#read 4, iclass 14, count 0 2006.224.08:01:58.79#ibcon#about to read 5, iclass 14, count 0 2006.224.08:01:58.79#ibcon#read 5, iclass 14, count 0 2006.224.08:01:58.79#ibcon#about to read 6, iclass 14, count 0 2006.224.08:01:58.79#ibcon#read 6, iclass 14, count 0 2006.224.08:01:58.79#ibcon#end of sib2, iclass 14, count 0 2006.224.08:01:58.79#ibcon#*mode == 0, iclass 14, count 0 2006.224.08:01:58.79#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.224.08:01:58.79#ibcon#[25=USB\r\n] 2006.224.08:01:58.79#ibcon#*before write, iclass 14, count 0 2006.224.08:01:58.79#ibcon#enter sib2, iclass 14, count 0 2006.224.08:01:58.79#ibcon#flushed, iclass 14, count 0 2006.224.08:01:58.79#ibcon#about to write, iclass 14, count 0 2006.224.08:01:58.79#ibcon#wrote, iclass 14, count 0 2006.224.08:01:58.79#ibcon#about to read 3, iclass 14, count 0 2006.224.08:01:58.82#ibcon#read 3, iclass 14, count 0 2006.224.08:01:58.82#ibcon#about to read 4, iclass 14, count 0 2006.224.08:01:58.82#ibcon#read 4, iclass 14, count 0 2006.224.08:01:58.82#ibcon#about to read 5, iclass 14, count 0 2006.224.08:01:58.82#ibcon#read 5, iclass 14, count 0 2006.224.08:01:58.82#ibcon#about to read 6, iclass 14, count 0 2006.224.08:01:58.82#ibcon#read 6, iclass 14, count 0 2006.224.08:01:58.82#ibcon#end of sib2, iclass 14, count 0 2006.224.08:01:58.82#ibcon#*after write, iclass 14, count 0 2006.224.08:01:58.82#ibcon#*before return 0, iclass 14, count 0 2006.224.08:01:58.82#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.224.08:01:58.82#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.224.08:01:58.82#ibcon#about to clear, iclass 14 cls_cnt 0 2006.224.08:01:58.82#ibcon#cleared, iclass 14 cls_cnt 0 2006.224.08:01:58.82$vc4f8/valo=4,832.99 2006.224.08:01:58.82#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.224.08:01:58.82#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.224.08:01:58.82#ibcon#ireg 17 cls_cnt 0 2006.224.08:01:58.82#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.224.08:01:58.82#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.224.08:01:58.82#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.224.08:01:58.82#ibcon#enter wrdev, iclass 16, count 0 2006.224.08:01:58.82#ibcon#first serial, iclass 16, count 0 2006.224.08:01:58.82#ibcon#enter sib2, iclass 16, count 0 2006.224.08:01:58.82#ibcon#flushed, iclass 16, count 0 2006.224.08:01:58.82#ibcon#about to write, iclass 16, count 0 2006.224.08:01:58.82#ibcon#wrote, iclass 16, count 0 2006.224.08:01:58.82#ibcon#about to read 3, iclass 16, count 0 2006.224.08:01:58.84#ibcon#read 3, iclass 16, count 0 2006.224.08:01:58.84#ibcon#about to read 4, iclass 16, count 0 2006.224.08:01:58.84#ibcon#read 4, iclass 16, count 0 2006.224.08:01:58.84#ibcon#about to read 5, iclass 16, count 0 2006.224.08:01:58.84#ibcon#read 5, iclass 16, count 0 2006.224.08:01:58.84#ibcon#about to read 6, iclass 16, count 0 2006.224.08:01:58.84#ibcon#read 6, iclass 16, count 0 2006.224.08:01:58.84#ibcon#end of sib2, iclass 16, count 0 2006.224.08:01:58.84#ibcon#*mode == 0, iclass 16, count 0 2006.224.08:01:58.84#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.224.08:01:58.84#ibcon#[26=FRQ=04,832.99\r\n] 2006.224.08:01:58.84#ibcon#*before write, iclass 16, count 0 2006.224.08:01:58.84#ibcon#enter sib2, iclass 16, count 0 2006.224.08:01:58.84#ibcon#flushed, iclass 16, count 0 2006.224.08:01:58.84#ibcon#about to write, iclass 16, count 0 2006.224.08:01:58.84#ibcon#wrote, iclass 16, count 0 2006.224.08:01:58.84#ibcon#about to read 3, iclass 16, count 0 2006.224.08:01:58.88#ibcon#read 3, iclass 16, count 0 2006.224.08:01:58.88#ibcon#about to read 4, iclass 16, count 0 2006.224.08:01:58.88#ibcon#read 4, iclass 16, count 0 2006.224.08:01:58.88#ibcon#about to read 5, iclass 16, count 0 2006.224.08:01:58.88#ibcon#read 5, iclass 16, count 0 2006.224.08:01:58.88#ibcon#about to read 6, iclass 16, count 0 2006.224.08:01:58.88#ibcon#read 6, iclass 16, count 0 2006.224.08:01:58.88#ibcon#end of sib2, iclass 16, count 0 2006.224.08:01:58.88#ibcon#*after write, iclass 16, count 0 2006.224.08:01:58.88#ibcon#*before return 0, iclass 16, count 0 2006.224.08:01:58.88#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.224.08:01:58.88#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.224.08:01:58.88#ibcon#about to clear, iclass 16 cls_cnt 0 2006.224.08:01:58.88#ibcon#cleared, iclass 16 cls_cnt 0 2006.224.08:01:58.88$vc4f8/va=4,7 2006.224.08:01:58.88#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.224.08:01:58.88#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.224.08:01:58.88#ibcon#ireg 11 cls_cnt 2 2006.224.08:01:58.88#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.224.08:01:58.94#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.224.08:01:58.94#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.224.08:01:58.94#ibcon#enter wrdev, iclass 18, count 2 2006.224.08:01:58.94#ibcon#first serial, iclass 18, count 2 2006.224.08:01:58.94#ibcon#enter sib2, iclass 18, count 2 2006.224.08:01:58.94#ibcon#flushed, iclass 18, count 2 2006.224.08:01:58.94#ibcon#about to write, iclass 18, count 2 2006.224.08:01:58.94#ibcon#wrote, iclass 18, count 2 2006.224.08:01:58.94#ibcon#about to read 3, iclass 18, count 2 2006.224.08:01:58.96#ibcon#read 3, iclass 18, count 2 2006.224.08:01:58.96#ibcon#about to read 4, iclass 18, count 2 2006.224.08:01:58.96#ibcon#read 4, iclass 18, count 2 2006.224.08:01:58.96#ibcon#about to read 5, iclass 18, count 2 2006.224.08:01:58.96#ibcon#read 5, iclass 18, count 2 2006.224.08:01:58.96#ibcon#about to read 6, iclass 18, count 2 2006.224.08:01:58.96#ibcon#read 6, iclass 18, count 2 2006.224.08:01:58.96#ibcon#end of sib2, iclass 18, count 2 2006.224.08:01:58.96#ibcon#*mode == 0, iclass 18, count 2 2006.224.08:01:58.96#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.224.08:01:58.96#ibcon#[25=AT04-07\r\n] 2006.224.08:01:58.96#ibcon#*before write, iclass 18, count 2 2006.224.08:01:58.96#ibcon#enter sib2, iclass 18, count 2 2006.224.08:01:58.96#ibcon#flushed, iclass 18, count 2 2006.224.08:01:58.96#ibcon#about to write, iclass 18, count 2 2006.224.08:01:58.96#ibcon#wrote, iclass 18, count 2 2006.224.08:01:58.96#ibcon#about to read 3, iclass 18, count 2 2006.224.08:01:58.99#ibcon#read 3, iclass 18, count 2 2006.224.08:01:58.99#ibcon#about to read 4, iclass 18, count 2 2006.224.08:01:58.99#ibcon#read 4, iclass 18, count 2 2006.224.08:01:58.99#ibcon#about to read 5, iclass 18, count 2 2006.224.08:01:58.99#ibcon#read 5, iclass 18, count 2 2006.224.08:01:58.99#ibcon#about to read 6, iclass 18, count 2 2006.224.08:01:58.99#ibcon#read 6, iclass 18, count 2 2006.224.08:01:58.99#ibcon#end of sib2, iclass 18, count 2 2006.224.08:01:58.99#ibcon#*after write, iclass 18, count 2 2006.224.08:01:58.99#ibcon#*before return 0, iclass 18, count 2 2006.224.08:01:58.99#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.224.08:01:58.99#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.224.08:01:58.99#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.224.08:01:58.99#ibcon#ireg 7 cls_cnt 0 2006.224.08:01:58.99#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.224.08:01:59.11#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.224.08:01:59.11#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.224.08:01:59.11#ibcon#enter wrdev, iclass 18, count 0 2006.224.08:01:59.11#ibcon#first serial, iclass 18, count 0 2006.224.08:01:59.11#ibcon#enter sib2, iclass 18, count 0 2006.224.08:01:59.11#ibcon#flushed, iclass 18, count 0 2006.224.08:01:59.11#ibcon#about to write, iclass 18, count 0 2006.224.08:01:59.11#ibcon#wrote, iclass 18, count 0 2006.224.08:01:59.11#ibcon#about to read 3, iclass 18, count 0 2006.224.08:01:59.13#ibcon#read 3, iclass 18, count 0 2006.224.08:01:59.13#ibcon#about to read 4, iclass 18, count 0 2006.224.08:01:59.13#ibcon#read 4, iclass 18, count 0 2006.224.08:01:59.13#ibcon#about to read 5, iclass 18, count 0 2006.224.08:01:59.13#ibcon#read 5, iclass 18, count 0 2006.224.08:01:59.13#ibcon#about to read 6, iclass 18, count 0 2006.224.08:01:59.13#ibcon#read 6, iclass 18, count 0 2006.224.08:01:59.13#ibcon#end of sib2, iclass 18, count 0 2006.224.08:01:59.13#ibcon#*mode == 0, iclass 18, count 0 2006.224.08:01:59.13#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.224.08:01:59.13#ibcon#[25=USB\r\n] 2006.224.08:01:59.13#ibcon#*before write, iclass 18, count 0 2006.224.08:01:59.13#ibcon#enter sib2, iclass 18, count 0 2006.224.08:01:59.13#ibcon#flushed, iclass 18, count 0 2006.224.08:01:59.13#ibcon#about to write, iclass 18, count 0 2006.224.08:01:59.13#ibcon#wrote, iclass 18, count 0 2006.224.08:01:59.13#ibcon#about to read 3, iclass 18, count 0 2006.224.08:01:59.16#ibcon#read 3, iclass 18, count 0 2006.224.08:01:59.16#ibcon#about to read 4, iclass 18, count 0 2006.224.08:01:59.16#ibcon#read 4, iclass 18, count 0 2006.224.08:01:59.16#ibcon#about to read 5, iclass 18, count 0 2006.224.08:01:59.16#ibcon#read 5, iclass 18, count 0 2006.224.08:01:59.16#ibcon#about to read 6, iclass 18, count 0 2006.224.08:01:59.16#ibcon#read 6, iclass 18, count 0 2006.224.08:01:59.16#ibcon#end of sib2, iclass 18, count 0 2006.224.08:01:59.16#ibcon#*after write, iclass 18, count 0 2006.224.08:01:59.16#ibcon#*before return 0, iclass 18, count 0 2006.224.08:01:59.16#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.224.08:01:59.16#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.224.08:01:59.16#ibcon#about to clear, iclass 18 cls_cnt 0 2006.224.08:01:59.16#ibcon#cleared, iclass 18 cls_cnt 0 2006.224.08:01:59.16$vc4f8/valo=5,652.99 2006.224.08:01:59.16#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.224.08:01:59.16#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.224.08:01:59.16#ibcon#ireg 17 cls_cnt 0 2006.224.08:01:59.16#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.224.08:01:59.16#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.224.08:01:59.16#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.224.08:01:59.16#ibcon#enter wrdev, iclass 20, count 0 2006.224.08:01:59.16#ibcon#first serial, iclass 20, count 0 2006.224.08:01:59.16#ibcon#enter sib2, iclass 20, count 0 2006.224.08:01:59.16#ibcon#flushed, iclass 20, count 0 2006.224.08:01:59.16#ibcon#about to write, iclass 20, count 0 2006.224.08:01:59.16#ibcon#wrote, iclass 20, count 0 2006.224.08:01:59.16#ibcon#about to read 3, iclass 20, count 0 2006.224.08:01:59.18#ibcon#read 3, iclass 20, count 0 2006.224.08:01:59.18#ibcon#about to read 4, iclass 20, count 0 2006.224.08:01:59.18#ibcon#read 4, iclass 20, count 0 2006.224.08:01:59.18#ibcon#about to read 5, iclass 20, count 0 2006.224.08:01:59.18#ibcon#read 5, iclass 20, count 0 2006.224.08:01:59.18#ibcon#about to read 6, iclass 20, count 0 2006.224.08:01:59.18#ibcon#read 6, iclass 20, count 0 2006.224.08:01:59.18#ibcon#end of sib2, iclass 20, count 0 2006.224.08:01:59.18#ibcon#*mode == 0, iclass 20, count 0 2006.224.08:01:59.18#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.224.08:01:59.18#ibcon#[26=FRQ=05,652.99\r\n] 2006.224.08:01:59.18#ibcon#*before write, iclass 20, count 0 2006.224.08:01:59.18#ibcon#enter sib2, iclass 20, count 0 2006.224.08:01:59.18#ibcon#flushed, iclass 20, count 0 2006.224.08:01:59.18#ibcon#about to write, iclass 20, count 0 2006.224.08:01:59.18#ibcon#wrote, iclass 20, count 0 2006.224.08:01:59.18#ibcon#about to read 3, iclass 20, count 0 2006.224.08:01:59.22#ibcon#read 3, iclass 20, count 0 2006.224.08:01:59.22#ibcon#about to read 4, iclass 20, count 0 2006.224.08:01:59.22#ibcon#read 4, iclass 20, count 0 2006.224.08:01:59.22#ibcon#about to read 5, iclass 20, count 0 2006.224.08:01:59.22#ibcon#read 5, iclass 20, count 0 2006.224.08:01:59.22#ibcon#about to read 6, iclass 20, count 0 2006.224.08:01:59.22#ibcon#read 6, iclass 20, count 0 2006.224.08:01:59.22#ibcon#end of sib2, iclass 20, count 0 2006.224.08:01:59.22#ibcon#*after write, iclass 20, count 0 2006.224.08:01:59.22#ibcon#*before return 0, iclass 20, count 0 2006.224.08:01:59.22#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.224.08:01:59.22#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.224.08:01:59.22#ibcon#about to clear, iclass 20 cls_cnt 0 2006.224.08:01:59.22#ibcon#cleared, iclass 20 cls_cnt 0 2006.224.08:01:59.22$vc4f8/va=5,7 2006.224.08:01:59.22#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.224.08:01:59.22#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.224.08:01:59.22#ibcon#ireg 11 cls_cnt 2 2006.224.08:01:59.22#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.224.08:01:59.28#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.224.08:01:59.28#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.224.08:01:59.28#ibcon#enter wrdev, iclass 22, count 2 2006.224.08:01:59.28#ibcon#first serial, iclass 22, count 2 2006.224.08:01:59.28#ibcon#enter sib2, iclass 22, count 2 2006.224.08:01:59.28#ibcon#flushed, iclass 22, count 2 2006.224.08:01:59.28#ibcon#about to write, iclass 22, count 2 2006.224.08:01:59.28#ibcon#wrote, iclass 22, count 2 2006.224.08:01:59.28#ibcon#about to read 3, iclass 22, count 2 2006.224.08:01:59.30#ibcon#read 3, iclass 22, count 2 2006.224.08:01:59.30#ibcon#about to read 4, iclass 22, count 2 2006.224.08:01:59.30#ibcon#read 4, iclass 22, count 2 2006.224.08:01:59.30#ibcon#about to read 5, iclass 22, count 2 2006.224.08:01:59.30#ibcon#read 5, iclass 22, count 2 2006.224.08:01:59.30#ibcon#about to read 6, iclass 22, count 2 2006.224.08:01:59.30#ibcon#read 6, iclass 22, count 2 2006.224.08:01:59.30#ibcon#end of sib2, iclass 22, count 2 2006.224.08:01:59.30#ibcon#*mode == 0, iclass 22, count 2 2006.224.08:01:59.30#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.224.08:01:59.30#ibcon#[25=AT05-07\r\n] 2006.224.08:01:59.30#ibcon#*before write, iclass 22, count 2 2006.224.08:01:59.30#ibcon#enter sib2, iclass 22, count 2 2006.224.08:01:59.30#ibcon#flushed, iclass 22, count 2 2006.224.08:01:59.30#ibcon#about to write, iclass 22, count 2 2006.224.08:01:59.30#ibcon#wrote, iclass 22, count 2 2006.224.08:01:59.30#ibcon#about to read 3, iclass 22, count 2 2006.224.08:01:59.33#ibcon#read 3, iclass 22, count 2 2006.224.08:01:59.33#ibcon#about to read 4, iclass 22, count 2 2006.224.08:01:59.33#ibcon#read 4, iclass 22, count 2 2006.224.08:01:59.33#ibcon#about to read 5, iclass 22, count 2 2006.224.08:01:59.33#ibcon#read 5, iclass 22, count 2 2006.224.08:01:59.33#ibcon#about to read 6, iclass 22, count 2 2006.224.08:01:59.33#ibcon#read 6, iclass 22, count 2 2006.224.08:01:59.33#ibcon#end of sib2, iclass 22, count 2 2006.224.08:01:59.33#ibcon#*after write, iclass 22, count 2 2006.224.08:01:59.33#ibcon#*before return 0, iclass 22, count 2 2006.224.08:01:59.33#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.224.08:01:59.33#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.224.08:01:59.33#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.224.08:01:59.33#ibcon#ireg 7 cls_cnt 0 2006.224.08:01:59.33#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.224.08:01:59.45#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.224.08:01:59.45#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.224.08:01:59.45#ibcon#enter wrdev, iclass 22, count 0 2006.224.08:01:59.45#ibcon#first serial, iclass 22, count 0 2006.224.08:01:59.45#ibcon#enter sib2, iclass 22, count 0 2006.224.08:01:59.45#ibcon#flushed, iclass 22, count 0 2006.224.08:01:59.45#ibcon#about to write, iclass 22, count 0 2006.224.08:01:59.45#ibcon#wrote, iclass 22, count 0 2006.224.08:01:59.45#ibcon#about to read 3, iclass 22, count 0 2006.224.08:01:59.47#ibcon#read 3, iclass 22, count 0 2006.224.08:01:59.47#ibcon#about to read 4, iclass 22, count 0 2006.224.08:01:59.47#ibcon#read 4, iclass 22, count 0 2006.224.08:01:59.47#ibcon#about to read 5, iclass 22, count 0 2006.224.08:01:59.47#ibcon#read 5, iclass 22, count 0 2006.224.08:01:59.47#ibcon#about to read 6, iclass 22, count 0 2006.224.08:01:59.47#ibcon#read 6, iclass 22, count 0 2006.224.08:01:59.47#ibcon#end of sib2, iclass 22, count 0 2006.224.08:01:59.47#ibcon#*mode == 0, iclass 22, count 0 2006.224.08:01:59.47#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.224.08:01:59.47#ibcon#[25=USB\r\n] 2006.224.08:01:59.47#ibcon#*before write, iclass 22, count 0 2006.224.08:01:59.47#ibcon#enter sib2, iclass 22, count 0 2006.224.08:01:59.47#ibcon#flushed, iclass 22, count 0 2006.224.08:01:59.47#ibcon#about to write, iclass 22, count 0 2006.224.08:01:59.47#ibcon#wrote, iclass 22, count 0 2006.224.08:01:59.47#ibcon#about to read 3, iclass 22, count 0 2006.224.08:01:59.50#ibcon#read 3, iclass 22, count 0 2006.224.08:01:59.50#ibcon#about to read 4, iclass 22, count 0 2006.224.08:01:59.50#ibcon#read 4, iclass 22, count 0 2006.224.08:01:59.50#ibcon#about to read 5, iclass 22, count 0 2006.224.08:01:59.50#ibcon#read 5, iclass 22, count 0 2006.224.08:01:59.50#ibcon#about to read 6, iclass 22, count 0 2006.224.08:01:59.50#ibcon#read 6, iclass 22, count 0 2006.224.08:01:59.50#ibcon#end of sib2, iclass 22, count 0 2006.224.08:01:59.50#ibcon#*after write, iclass 22, count 0 2006.224.08:01:59.50#ibcon#*before return 0, iclass 22, count 0 2006.224.08:01:59.50#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.224.08:01:59.50#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.224.08:01:59.50#ibcon#about to clear, iclass 22 cls_cnt 0 2006.224.08:01:59.50#ibcon#cleared, iclass 22 cls_cnt 0 2006.224.08:01:59.50$vc4f8/valo=6,772.99 2006.224.08:01:59.50#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.224.08:01:59.50#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.224.08:01:59.50#ibcon#ireg 17 cls_cnt 0 2006.224.08:01:59.50#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.224.08:01:59.50#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.224.08:01:59.50#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.224.08:01:59.50#ibcon#enter wrdev, iclass 24, count 0 2006.224.08:01:59.50#ibcon#first serial, iclass 24, count 0 2006.224.08:01:59.50#ibcon#enter sib2, iclass 24, count 0 2006.224.08:01:59.50#ibcon#flushed, iclass 24, count 0 2006.224.08:01:59.50#ibcon#about to write, iclass 24, count 0 2006.224.08:01:59.50#ibcon#wrote, iclass 24, count 0 2006.224.08:01:59.50#ibcon#about to read 3, iclass 24, count 0 2006.224.08:01:59.53#ibcon#read 3, iclass 24, count 0 2006.224.08:01:59.53#ibcon#about to read 4, iclass 24, count 0 2006.224.08:01:59.53#ibcon#read 4, iclass 24, count 0 2006.224.08:01:59.53#ibcon#about to read 5, iclass 24, count 0 2006.224.08:01:59.53#ibcon#read 5, iclass 24, count 0 2006.224.08:01:59.53#ibcon#about to read 6, iclass 24, count 0 2006.224.08:01:59.53#ibcon#read 6, iclass 24, count 0 2006.224.08:01:59.53#ibcon#end of sib2, iclass 24, count 0 2006.224.08:01:59.53#ibcon#*mode == 0, iclass 24, count 0 2006.224.08:01:59.53#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.224.08:01:59.53#ibcon#[26=FRQ=06,772.99\r\n] 2006.224.08:01:59.53#ibcon#*before write, iclass 24, count 0 2006.224.08:01:59.53#ibcon#enter sib2, iclass 24, count 0 2006.224.08:01:59.53#ibcon#flushed, iclass 24, count 0 2006.224.08:01:59.53#ibcon#about to write, iclass 24, count 0 2006.224.08:01:59.53#ibcon#wrote, iclass 24, count 0 2006.224.08:01:59.53#ibcon#about to read 3, iclass 24, count 0 2006.224.08:01:59.57#ibcon#read 3, iclass 24, count 0 2006.224.08:01:59.57#ibcon#about to read 4, iclass 24, count 0 2006.224.08:01:59.57#ibcon#read 4, iclass 24, count 0 2006.224.08:01:59.57#ibcon#about to read 5, iclass 24, count 0 2006.224.08:01:59.57#ibcon#read 5, iclass 24, count 0 2006.224.08:01:59.57#ibcon#about to read 6, iclass 24, count 0 2006.224.08:01:59.57#ibcon#read 6, iclass 24, count 0 2006.224.08:01:59.57#ibcon#end of sib2, iclass 24, count 0 2006.224.08:01:59.57#ibcon#*after write, iclass 24, count 0 2006.224.08:01:59.57#ibcon#*before return 0, iclass 24, count 0 2006.224.08:01:59.57#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.224.08:01:59.57#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.224.08:01:59.57#ibcon#about to clear, iclass 24 cls_cnt 0 2006.224.08:01:59.57#ibcon#cleared, iclass 24 cls_cnt 0 2006.224.08:01:59.57$vc4f8/va=6,6 2006.224.08:01:59.57#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.224.08:01:59.57#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.224.08:01:59.57#ibcon#ireg 11 cls_cnt 2 2006.224.08:01:59.57#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.224.08:01:59.62#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.224.08:01:59.62#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.224.08:01:59.62#ibcon#enter wrdev, iclass 26, count 2 2006.224.08:01:59.62#ibcon#first serial, iclass 26, count 2 2006.224.08:01:59.62#ibcon#enter sib2, iclass 26, count 2 2006.224.08:01:59.62#ibcon#flushed, iclass 26, count 2 2006.224.08:01:59.62#ibcon#about to write, iclass 26, count 2 2006.224.08:01:59.62#ibcon#wrote, iclass 26, count 2 2006.224.08:01:59.62#ibcon#about to read 3, iclass 26, count 2 2006.224.08:01:59.64#ibcon#read 3, iclass 26, count 2 2006.224.08:01:59.64#ibcon#about to read 4, iclass 26, count 2 2006.224.08:01:59.64#ibcon#read 4, iclass 26, count 2 2006.224.08:01:59.64#ibcon#about to read 5, iclass 26, count 2 2006.224.08:01:59.64#ibcon#read 5, iclass 26, count 2 2006.224.08:01:59.64#ibcon#about to read 6, iclass 26, count 2 2006.224.08:01:59.64#ibcon#read 6, iclass 26, count 2 2006.224.08:01:59.64#ibcon#end of sib2, iclass 26, count 2 2006.224.08:01:59.64#ibcon#*mode == 0, iclass 26, count 2 2006.224.08:01:59.64#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.224.08:01:59.64#ibcon#[25=AT06-06\r\n] 2006.224.08:01:59.64#ibcon#*before write, iclass 26, count 2 2006.224.08:01:59.64#ibcon#enter sib2, iclass 26, count 2 2006.224.08:01:59.64#ibcon#flushed, iclass 26, count 2 2006.224.08:01:59.64#ibcon#about to write, iclass 26, count 2 2006.224.08:01:59.64#ibcon#wrote, iclass 26, count 2 2006.224.08:01:59.64#ibcon#about to read 3, iclass 26, count 2 2006.224.08:01:59.67#ibcon#read 3, iclass 26, count 2 2006.224.08:01:59.67#ibcon#about to read 4, iclass 26, count 2 2006.224.08:01:59.67#ibcon#read 4, iclass 26, count 2 2006.224.08:01:59.67#ibcon#about to read 5, iclass 26, count 2 2006.224.08:01:59.67#ibcon#read 5, iclass 26, count 2 2006.224.08:01:59.67#ibcon#about to read 6, iclass 26, count 2 2006.224.08:01:59.67#ibcon#read 6, iclass 26, count 2 2006.224.08:01:59.67#ibcon#end of sib2, iclass 26, count 2 2006.224.08:01:59.67#ibcon#*after write, iclass 26, count 2 2006.224.08:01:59.67#ibcon#*before return 0, iclass 26, count 2 2006.224.08:01:59.67#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.224.08:01:59.67#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.224.08:01:59.67#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.224.08:01:59.67#ibcon#ireg 7 cls_cnt 0 2006.224.08:01:59.67#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.224.08:01:59.79#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.224.08:01:59.79#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.224.08:01:59.79#ibcon#enter wrdev, iclass 26, count 0 2006.224.08:01:59.79#ibcon#first serial, iclass 26, count 0 2006.224.08:01:59.79#ibcon#enter sib2, iclass 26, count 0 2006.224.08:01:59.79#ibcon#flushed, iclass 26, count 0 2006.224.08:01:59.79#ibcon#about to write, iclass 26, count 0 2006.224.08:01:59.79#ibcon#wrote, iclass 26, count 0 2006.224.08:01:59.79#ibcon#about to read 3, iclass 26, count 0 2006.224.08:01:59.81#ibcon#read 3, iclass 26, count 0 2006.224.08:01:59.81#ibcon#about to read 4, iclass 26, count 0 2006.224.08:01:59.81#ibcon#read 4, iclass 26, count 0 2006.224.08:01:59.81#ibcon#about to read 5, iclass 26, count 0 2006.224.08:01:59.81#ibcon#read 5, iclass 26, count 0 2006.224.08:01:59.81#ibcon#about to read 6, iclass 26, count 0 2006.224.08:01:59.81#ibcon#read 6, iclass 26, count 0 2006.224.08:01:59.81#ibcon#end of sib2, iclass 26, count 0 2006.224.08:01:59.81#ibcon#*mode == 0, iclass 26, count 0 2006.224.08:01:59.81#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.224.08:01:59.81#ibcon#[25=USB\r\n] 2006.224.08:01:59.81#ibcon#*before write, iclass 26, count 0 2006.224.08:01:59.81#ibcon#enter sib2, iclass 26, count 0 2006.224.08:01:59.81#ibcon#flushed, iclass 26, count 0 2006.224.08:01:59.81#ibcon#about to write, iclass 26, count 0 2006.224.08:01:59.81#ibcon#wrote, iclass 26, count 0 2006.224.08:01:59.81#ibcon#about to read 3, iclass 26, count 0 2006.224.08:01:59.84#ibcon#read 3, iclass 26, count 0 2006.224.08:01:59.84#ibcon#about to read 4, iclass 26, count 0 2006.224.08:01:59.84#ibcon#read 4, iclass 26, count 0 2006.224.08:01:59.84#ibcon#about to read 5, iclass 26, count 0 2006.224.08:01:59.84#ibcon#read 5, iclass 26, count 0 2006.224.08:01:59.84#ibcon#about to read 6, iclass 26, count 0 2006.224.08:01:59.84#ibcon#read 6, iclass 26, count 0 2006.224.08:01:59.84#ibcon#end of sib2, iclass 26, count 0 2006.224.08:01:59.84#ibcon#*after write, iclass 26, count 0 2006.224.08:01:59.84#ibcon#*before return 0, iclass 26, count 0 2006.224.08:01:59.84#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.224.08:01:59.84#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.224.08:01:59.84#ibcon#about to clear, iclass 26 cls_cnt 0 2006.224.08:01:59.84#ibcon#cleared, iclass 26 cls_cnt 0 2006.224.08:01:59.84$vc4f8/valo=7,832.99 2006.224.08:01:59.84#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.224.08:01:59.84#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.224.08:01:59.84#ibcon#ireg 17 cls_cnt 0 2006.224.08:01:59.84#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.224.08:01:59.84#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.224.08:01:59.84#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.224.08:01:59.84#ibcon#enter wrdev, iclass 28, count 0 2006.224.08:01:59.84#ibcon#first serial, iclass 28, count 0 2006.224.08:01:59.84#ibcon#enter sib2, iclass 28, count 0 2006.224.08:01:59.84#ibcon#flushed, iclass 28, count 0 2006.224.08:01:59.84#ibcon#about to write, iclass 28, count 0 2006.224.08:01:59.84#ibcon#wrote, iclass 28, count 0 2006.224.08:01:59.84#ibcon#about to read 3, iclass 28, count 0 2006.224.08:01:59.86#ibcon#read 3, iclass 28, count 0 2006.224.08:01:59.86#ibcon#about to read 4, iclass 28, count 0 2006.224.08:01:59.86#ibcon#read 4, iclass 28, count 0 2006.224.08:01:59.86#ibcon#about to read 5, iclass 28, count 0 2006.224.08:01:59.86#ibcon#read 5, iclass 28, count 0 2006.224.08:01:59.86#ibcon#about to read 6, iclass 28, count 0 2006.224.08:01:59.86#ibcon#read 6, iclass 28, count 0 2006.224.08:01:59.86#ibcon#end of sib2, iclass 28, count 0 2006.224.08:01:59.86#ibcon#*mode == 0, iclass 28, count 0 2006.224.08:01:59.86#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.224.08:01:59.86#ibcon#[26=FRQ=07,832.99\r\n] 2006.224.08:01:59.86#ibcon#*before write, iclass 28, count 0 2006.224.08:01:59.86#ibcon#enter sib2, iclass 28, count 0 2006.224.08:01:59.86#ibcon#flushed, iclass 28, count 0 2006.224.08:01:59.86#ibcon#about to write, iclass 28, count 0 2006.224.08:01:59.86#ibcon#wrote, iclass 28, count 0 2006.224.08:01:59.86#ibcon#about to read 3, iclass 28, count 0 2006.224.08:01:59.90#ibcon#read 3, iclass 28, count 0 2006.224.08:01:59.90#ibcon#about to read 4, iclass 28, count 0 2006.224.08:01:59.90#ibcon#read 4, iclass 28, count 0 2006.224.08:01:59.90#ibcon#about to read 5, iclass 28, count 0 2006.224.08:01:59.90#ibcon#read 5, iclass 28, count 0 2006.224.08:01:59.90#ibcon#about to read 6, iclass 28, count 0 2006.224.08:01:59.90#ibcon#read 6, iclass 28, count 0 2006.224.08:01:59.90#ibcon#end of sib2, iclass 28, count 0 2006.224.08:01:59.90#ibcon#*after write, iclass 28, count 0 2006.224.08:01:59.90#ibcon#*before return 0, iclass 28, count 0 2006.224.08:01:59.90#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.224.08:01:59.90#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.224.08:01:59.90#ibcon#about to clear, iclass 28 cls_cnt 0 2006.224.08:01:59.90#ibcon#cleared, iclass 28 cls_cnt 0 2006.224.08:01:59.90$vc4f8/va=7,6 2006.224.08:01:59.90#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.224.08:01:59.90#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.224.08:01:59.90#ibcon#ireg 11 cls_cnt 2 2006.224.08:01:59.90#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.224.08:01:59.96#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.224.08:01:59.96#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.224.08:01:59.96#ibcon#enter wrdev, iclass 30, count 2 2006.224.08:01:59.96#ibcon#first serial, iclass 30, count 2 2006.224.08:01:59.96#ibcon#enter sib2, iclass 30, count 2 2006.224.08:01:59.96#ibcon#flushed, iclass 30, count 2 2006.224.08:01:59.96#ibcon#about to write, iclass 30, count 2 2006.224.08:01:59.96#ibcon#wrote, iclass 30, count 2 2006.224.08:01:59.96#ibcon#about to read 3, iclass 30, count 2 2006.224.08:01:59.98#ibcon#read 3, iclass 30, count 2 2006.224.08:01:59.98#ibcon#about to read 4, iclass 30, count 2 2006.224.08:01:59.98#ibcon#read 4, iclass 30, count 2 2006.224.08:01:59.98#ibcon#about to read 5, iclass 30, count 2 2006.224.08:01:59.98#ibcon#read 5, iclass 30, count 2 2006.224.08:01:59.98#ibcon#about to read 6, iclass 30, count 2 2006.224.08:01:59.98#ibcon#read 6, iclass 30, count 2 2006.224.08:01:59.98#ibcon#end of sib2, iclass 30, count 2 2006.224.08:01:59.98#ibcon#*mode == 0, iclass 30, count 2 2006.224.08:01:59.98#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.224.08:01:59.98#ibcon#[25=AT07-06\r\n] 2006.224.08:01:59.98#ibcon#*before write, iclass 30, count 2 2006.224.08:01:59.98#ibcon#enter sib2, iclass 30, count 2 2006.224.08:01:59.98#ibcon#flushed, iclass 30, count 2 2006.224.08:01:59.98#ibcon#about to write, iclass 30, count 2 2006.224.08:01:59.98#ibcon#wrote, iclass 30, count 2 2006.224.08:01:59.98#ibcon#about to read 3, iclass 30, count 2 2006.224.08:02:00.01#ibcon#read 3, iclass 30, count 2 2006.224.08:02:00.01#ibcon#about to read 4, iclass 30, count 2 2006.224.08:02:00.01#ibcon#read 4, iclass 30, count 2 2006.224.08:02:00.01#ibcon#about to read 5, iclass 30, count 2 2006.224.08:02:00.01#ibcon#read 5, iclass 30, count 2 2006.224.08:02:00.01#ibcon#about to read 6, iclass 30, count 2 2006.224.08:02:00.01#ibcon#read 6, iclass 30, count 2 2006.224.08:02:00.01#ibcon#end of sib2, iclass 30, count 2 2006.224.08:02:00.01#ibcon#*after write, iclass 30, count 2 2006.224.08:02:00.01#ibcon#*before return 0, iclass 30, count 2 2006.224.08:02:00.01#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.224.08:02:00.01#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.224.08:02:00.01#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.224.08:02:00.01#ibcon#ireg 7 cls_cnt 0 2006.224.08:02:00.01#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.224.08:02:00.13#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.224.08:02:00.13#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.224.08:02:00.13#ibcon#enter wrdev, iclass 30, count 0 2006.224.08:02:00.13#ibcon#first serial, iclass 30, count 0 2006.224.08:02:00.13#ibcon#enter sib2, iclass 30, count 0 2006.224.08:02:00.13#ibcon#flushed, iclass 30, count 0 2006.224.08:02:00.13#ibcon#about to write, iclass 30, count 0 2006.224.08:02:00.13#ibcon#wrote, iclass 30, count 0 2006.224.08:02:00.13#ibcon#about to read 3, iclass 30, count 0 2006.224.08:02:00.15#ibcon#read 3, iclass 30, count 0 2006.224.08:02:00.15#ibcon#about to read 4, iclass 30, count 0 2006.224.08:02:00.15#ibcon#read 4, iclass 30, count 0 2006.224.08:02:00.15#ibcon#about to read 5, iclass 30, count 0 2006.224.08:02:00.15#ibcon#read 5, iclass 30, count 0 2006.224.08:02:00.15#ibcon#about to read 6, iclass 30, count 0 2006.224.08:02:00.15#ibcon#read 6, iclass 30, count 0 2006.224.08:02:00.15#ibcon#end of sib2, iclass 30, count 0 2006.224.08:02:00.15#ibcon#*mode == 0, iclass 30, count 0 2006.224.08:02:00.15#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.224.08:02:00.15#ibcon#[25=USB\r\n] 2006.224.08:02:00.15#ibcon#*before write, iclass 30, count 0 2006.224.08:02:00.15#ibcon#enter sib2, iclass 30, count 0 2006.224.08:02:00.15#ibcon#flushed, iclass 30, count 0 2006.224.08:02:00.15#ibcon#about to write, iclass 30, count 0 2006.224.08:02:00.15#ibcon#wrote, iclass 30, count 0 2006.224.08:02:00.15#ibcon#about to read 3, iclass 30, count 0 2006.224.08:02:00.18#ibcon#read 3, iclass 30, count 0 2006.224.08:02:00.18#ibcon#about to read 4, iclass 30, count 0 2006.224.08:02:00.18#ibcon#read 4, iclass 30, count 0 2006.224.08:02:00.18#ibcon#about to read 5, iclass 30, count 0 2006.224.08:02:00.18#ibcon#read 5, iclass 30, count 0 2006.224.08:02:00.18#ibcon#about to read 6, iclass 30, count 0 2006.224.08:02:00.18#ibcon#read 6, iclass 30, count 0 2006.224.08:02:00.18#ibcon#end of sib2, iclass 30, count 0 2006.224.08:02:00.18#ibcon#*after write, iclass 30, count 0 2006.224.08:02:00.18#ibcon#*before return 0, iclass 30, count 0 2006.224.08:02:00.18#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.224.08:02:00.18#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.224.08:02:00.18#ibcon#about to clear, iclass 30 cls_cnt 0 2006.224.08:02:00.18#ibcon#cleared, iclass 30 cls_cnt 0 2006.224.08:02:00.18$vc4f8/valo=8,852.99 2006.224.08:02:00.18#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.224.08:02:00.18#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.224.08:02:00.18#ibcon#ireg 17 cls_cnt 0 2006.224.08:02:00.18#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.224.08:02:00.18#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.224.08:02:00.18#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.224.08:02:00.18#ibcon#enter wrdev, iclass 32, count 0 2006.224.08:02:00.18#ibcon#first serial, iclass 32, count 0 2006.224.08:02:00.18#ibcon#enter sib2, iclass 32, count 0 2006.224.08:02:00.18#ibcon#flushed, iclass 32, count 0 2006.224.08:02:00.18#ibcon#about to write, iclass 32, count 0 2006.224.08:02:00.18#ibcon#wrote, iclass 32, count 0 2006.224.08:02:00.18#ibcon#about to read 3, iclass 32, count 0 2006.224.08:02:00.20#ibcon#read 3, iclass 32, count 0 2006.224.08:02:00.20#ibcon#about to read 4, iclass 32, count 0 2006.224.08:02:00.20#ibcon#read 4, iclass 32, count 0 2006.224.08:02:00.20#ibcon#about to read 5, iclass 32, count 0 2006.224.08:02:00.20#ibcon#read 5, iclass 32, count 0 2006.224.08:02:00.20#ibcon#about to read 6, iclass 32, count 0 2006.224.08:02:00.20#ibcon#read 6, iclass 32, count 0 2006.224.08:02:00.20#ibcon#end of sib2, iclass 32, count 0 2006.224.08:02:00.20#ibcon#*mode == 0, iclass 32, count 0 2006.224.08:02:00.20#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.224.08:02:00.20#ibcon#[26=FRQ=08,852.99\r\n] 2006.224.08:02:00.20#ibcon#*before write, iclass 32, count 0 2006.224.08:02:00.20#ibcon#enter sib2, iclass 32, count 0 2006.224.08:02:00.20#ibcon#flushed, iclass 32, count 0 2006.224.08:02:00.20#ibcon#about to write, iclass 32, count 0 2006.224.08:02:00.20#ibcon#wrote, iclass 32, count 0 2006.224.08:02:00.20#ibcon#about to read 3, iclass 32, count 0 2006.224.08:02:00.24#ibcon#read 3, iclass 32, count 0 2006.224.08:02:00.24#ibcon#about to read 4, iclass 32, count 0 2006.224.08:02:00.24#ibcon#read 4, iclass 32, count 0 2006.224.08:02:00.24#ibcon#about to read 5, iclass 32, count 0 2006.224.08:02:00.24#ibcon#read 5, iclass 32, count 0 2006.224.08:02:00.24#ibcon#about to read 6, iclass 32, count 0 2006.224.08:02:00.24#ibcon#read 6, iclass 32, count 0 2006.224.08:02:00.24#ibcon#end of sib2, iclass 32, count 0 2006.224.08:02:00.24#ibcon#*after write, iclass 32, count 0 2006.224.08:02:00.24#ibcon#*before return 0, iclass 32, count 0 2006.224.08:02:00.24#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.224.08:02:00.24#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.224.08:02:00.24#ibcon#about to clear, iclass 32 cls_cnt 0 2006.224.08:02:00.24#ibcon#cleared, iclass 32 cls_cnt 0 2006.224.08:02:00.24$vc4f8/va=8,7 2006.224.08:02:00.24#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.224.08:02:00.24#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.224.08:02:00.24#ibcon#ireg 11 cls_cnt 2 2006.224.08:02:00.24#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.224.08:02:00.30#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.224.08:02:00.30#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.224.08:02:00.30#ibcon#enter wrdev, iclass 34, count 2 2006.224.08:02:00.30#ibcon#first serial, iclass 34, count 2 2006.224.08:02:00.30#ibcon#enter sib2, iclass 34, count 2 2006.224.08:02:00.30#ibcon#flushed, iclass 34, count 2 2006.224.08:02:00.30#ibcon#about to write, iclass 34, count 2 2006.224.08:02:00.30#ibcon#wrote, iclass 34, count 2 2006.224.08:02:00.30#ibcon#about to read 3, iclass 34, count 2 2006.224.08:02:00.32#ibcon#read 3, iclass 34, count 2 2006.224.08:02:00.32#ibcon#about to read 4, iclass 34, count 2 2006.224.08:02:00.32#ibcon#read 4, iclass 34, count 2 2006.224.08:02:00.32#ibcon#about to read 5, iclass 34, count 2 2006.224.08:02:00.32#ibcon#read 5, iclass 34, count 2 2006.224.08:02:00.32#ibcon#about to read 6, iclass 34, count 2 2006.224.08:02:00.32#ibcon#read 6, iclass 34, count 2 2006.224.08:02:00.32#ibcon#end of sib2, iclass 34, count 2 2006.224.08:02:00.32#ibcon#*mode == 0, iclass 34, count 2 2006.224.08:02:00.32#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.224.08:02:00.32#ibcon#[25=AT08-07\r\n] 2006.224.08:02:00.32#ibcon#*before write, iclass 34, count 2 2006.224.08:02:00.32#ibcon#enter sib2, iclass 34, count 2 2006.224.08:02:00.32#ibcon#flushed, iclass 34, count 2 2006.224.08:02:00.32#ibcon#about to write, iclass 34, count 2 2006.224.08:02:00.32#ibcon#wrote, iclass 34, count 2 2006.224.08:02:00.32#ibcon#about to read 3, iclass 34, count 2 2006.224.08:02:00.35#ibcon#read 3, iclass 34, count 2 2006.224.08:02:00.35#ibcon#about to read 4, iclass 34, count 2 2006.224.08:02:00.35#ibcon#read 4, iclass 34, count 2 2006.224.08:02:00.35#ibcon#about to read 5, iclass 34, count 2 2006.224.08:02:00.35#ibcon#read 5, iclass 34, count 2 2006.224.08:02:00.35#ibcon#about to read 6, iclass 34, count 2 2006.224.08:02:00.35#ibcon#read 6, iclass 34, count 2 2006.224.08:02:00.35#ibcon#end of sib2, iclass 34, count 2 2006.224.08:02:00.35#ibcon#*after write, iclass 34, count 2 2006.224.08:02:00.35#ibcon#*before return 0, iclass 34, count 2 2006.224.08:02:00.35#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.224.08:02:00.35#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.224.08:02:00.35#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.224.08:02:00.35#ibcon#ireg 7 cls_cnt 0 2006.224.08:02:00.35#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.224.08:02:00.47#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.224.08:02:00.47#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.224.08:02:00.47#ibcon#enter wrdev, iclass 34, count 0 2006.224.08:02:00.47#ibcon#first serial, iclass 34, count 0 2006.224.08:02:00.47#ibcon#enter sib2, iclass 34, count 0 2006.224.08:02:00.47#ibcon#flushed, iclass 34, count 0 2006.224.08:02:00.47#ibcon#about to write, iclass 34, count 0 2006.224.08:02:00.47#ibcon#wrote, iclass 34, count 0 2006.224.08:02:00.47#ibcon#about to read 3, iclass 34, count 0 2006.224.08:02:00.49#ibcon#read 3, iclass 34, count 0 2006.224.08:02:00.49#ibcon#about to read 4, iclass 34, count 0 2006.224.08:02:00.49#ibcon#read 4, iclass 34, count 0 2006.224.08:02:00.49#ibcon#about to read 5, iclass 34, count 0 2006.224.08:02:00.49#ibcon#read 5, iclass 34, count 0 2006.224.08:02:00.49#ibcon#about to read 6, iclass 34, count 0 2006.224.08:02:00.49#ibcon#read 6, iclass 34, count 0 2006.224.08:02:00.49#ibcon#end of sib2, iclass 34, count 0 2006.224.08:02:00.49#ibcon#*mode == 0, iclass 34, count 0 2006.224.08:02:00.49#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.224.08:02:00.49#ibcon#[25=USB\r\n] 2006.224.08:02:00.49#ibcon#*before write, iclass 34, count 0 2006.224.08:02:00.49#ibcon#enter sib2, iclass 34, count 0 2006.224.08:02:00.49#ibcon#flushed, iclass 34, count 0 2006.224.08:02:00.49#ibcon#about to write, iclass 34, count 0 2006.224.08:02:00.49#ibcon#wrote, iclass 34, count 0 2006.224.08:02:00.49#ibcon#about to read 3, iclass 34, count 0 2006.224.08:02:00.52#ibcon#read 3, iclass 34, count 0 2006.224.08:02:00.52#ibcon#about to read 4, iclass 34, count 0 2006.224.08:02:00.52#ibcon#read 4, iclass 34, count 0 2006.224.08:02:00.52#ibcon#about to read 5, iclass 34, count 0 2006.224.08:02:00.52#ibcon#read 5, iclass 34, count 0 2006.224.08:02:00.52#ibcon#about to read 6, iclass 34, count 0 2006.224.08:02:00.52#ibcon#read 6, iclass 34, count 0 2006.224.08:02:00.52#ibcon#end of sib2, iclass 34, count 0 2006.224.08:02:00.52#ibcon#*after write, iclass 34, count 0 2006.224.08:02:00.52#ibcon#*before return 0, iclass 34, count 0 2006.224.08:02:00.52#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.224.08:02:00.52#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.224.08:02:00.52#ibcon#about to clear, iclass 34 cls_cnt 0 2006.224.08:02:00.52#ibcon#cleared, iclass 34 cls_cnt 0 2006.224.08:02:00.52$vc4f8/vblo=1,632.99 2006.224.08:02:00.52#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.224.08:02:00.52#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.224.08:02:00.52#ibcon#ireg 17 cls_cnt 0 2006.224.08:02:00.52#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.224.08:02:00.52#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.224.08:02:00.52#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.224.08:02:00.52#ibcon#enter wrdev, iclass 36, count 0 2006.224.08:02:00.52#ibcon#first serial, iclass 36, count 0 2006.224.08:02:00.52#ibcon#enter sib2, iclass 36, count 0 2006.224.08:02:00.52#ibcon#flushed, iclass 36, count 0 2006.224.08:02:00.52#ibcon#about to write, iclass 36, count 0 2006.224.08:02:00.52#ibcon#wrote, iclass 36, count 0 2006.224.08:02:00.52#ibcon#about to read 3, iclass 36, count 0 2006.224.08:02:00.55#ibcon#read 3, iclass 36, count 0 2006.224.08:02:00.55#ibcon#about to read 4, iclass 36, count 0 2006.224.08:02:00.55#ibcon#read 4, iclass 36, count 0 2006.224.08:02:00.55#ibcon#about to read 5, iclass 36, count 0 2006.224.08:02:00.55#ibcon#read 5, iclass 36, count 0 2006.224.08:02:00.55#ibcon#about to read 6, iclass 36, count 0 2006.224.08:02:00.55#ibcon#read 6, iclass 36, count 0 2006.224.08:02:00.55#ibcon#end of sib2, iclass 36, count 0 2006.224.08:02:00.55#ibcon#*mode == 0, iclass 36, count 0 2006.224.08:02:00.55#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.224.08:02:00.55#ibcon#[28=FRQ=01,632.99\r\n] 2006.224.08:02:00.55#ibcon#*before write, iclass 36, count 0 2006.224.08:02:00.55#ibcon#enter sib2, iclass 36, count 0 2006.224.08:02:00.55#ibcon#flushed, iclass 36, count 0 2006.224.08:02:00.55#ibcon#about to write, iclass 36, count 0 2006.224.08:02:00.55#ibcon#wrote, iclass 36, count 0 2006.224.08:02:00.55#ibcon#about to read 3, iclass 36, count 0 2006.224.08:02:00.59#ibcon#read 3, iclass 36, count 0 2006.224.08:02:00.59#ibcon#about to read 4, iclass 36, count 0 2006.224.08:02:00.59#ibcon#read 4, iclass 36, count 0 2006.224.08:02:00.59#ibcon#about to read 5, iclass 36, count 0 2006.224.08:02:00.59#ibcon#read 5, iclass 36, count 0 2006.224.08:02:00.59#ibcon#about to read 6, iclass 36, count 0 2006.224.08:02:00.59#ibcon#read 6, iclass 36, count 0 2006.224.08:02:00.59#ibcon#end of sib2, iclass 36, count 0 2006.224.08:02:00.59#ibcon#*after write, iclass 36, count 0 2006.224.08:02:00.59#ibcon#*before return 0, iclass 36, count 0 2006.224.08:02:00.59#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.224.08:02:00.59#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.224.08:02:00.59#ibcon#about to clear, iclass 36 cls_cnt 0 2006.224.08:02:00.59#ibcon#cleared, iclass 36 cls_cnt 0 2006.224.08:02:00.59$vc4f8/vb=1,4 2006.224.08:02:00.59#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.224.08:02:00.59#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.224.08:02:00.59#ibcon#ireg 11 cls_cnt 2 2006.224.08:02:00.59#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.224.08:02:00.59#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.224.08:02:00.59#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.224.08:02:00.59#ibcon#enter wrdev, iclass 38, count 2 2006.224.08:02:00.59#ibcon#first serial, iclass 38, count 2 2006.224.08:02:00.59#ibcon#enter sib2, iclass 38, count 2 2006.224.08:02:00.59#ibcon#flushed, iclass 38, count 2 2006.224.08:02:00.59#ibcon#about to write, iclass 38, count 2 2006.224.08:02:00.59#ibcon#wrote, iclass 38, count 2 2006.224.08:02:00.59#ibcon#about to read 3, iclass 38, count 2 2006.224.08:02:00.61#ibcon#read 3, iclass 38, count 2 2006.224.08:02:00.61#ibcon#about to read 4, iclass 38, count 2 2006.224.08:02:00.61#ibcon#read 4, iclass 38, count 2 2006.224.08:02:00.61#ibcon#about to read 5, iclass 38, count 2 2006.224.08:02:00.61#ibcon#read 5, iclass 38, count 2 2006.224.08:02:00.61#ibcon#about to read 6, iclass 38, count 2 2006.224.08:02:00.61#ibcon#read 6, iclass 38, count 2 2006.224.08:02:00.61#ibcon#end of sib2, iclass 38, count 2 2006.224.08:02:00.61#ibcon#*mode == 0, iclass 38, count 2 2006.224.08:02:00.61#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.224.08:02:00.61#ibcon#[27=AT01-04\r\n] 2006.224.08:02:00.61#ibcon#*before write, iclass 38, count 2 2006.224.08:02:00.61#ibcon#enter sib2, iclass 38, count 2 2006.224.08:02:00.61#ibcon#flushed, iclass 38, count 2 2006.224.08:02:00.61#ibcon#about to write, iclass 38, count 2 2006.224.08:02:00.61#ibcon#wrote, iclass 38, count 2 2006.224.08:02:00.61#ibcon#about to read 3, iclass 38, count 2 2006.224.08:02:00.64#ibcon#read 3, iclass 38, count 2 2006.224.08:02:00.64#ibcon#about to read 4, iclass 38, count 2 2006.224.08:02:00.64#ibcon#read 4, iclass 38, count 2 2006.224.08:02:00.64#ibcon#about to read 5, iclass 38, count 2 2006.224.08:02:00.64#ibcon#read 5, iclass 38, count 2 2006.224.08:02:00.64#ibcon#about to read 6, iclass 38, count 2 2006.224.08:02:00.64#ibcon#read 6, iclass 38, count 2 2006.224.08:02:00.64#ibcon#end of sib2, iclass 38, count 2 2006.224.08:02:00.64#ibcon#*after write, iclass 38, count 2 2006.224.08:02:00.64#ibcon#*before return 0, iclass 38, count 2 2006.224.08:02:00.64#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.224.08:02:00.64#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.224.08:02:00.64#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.224.08:02:00.64#ibcon#ireg 7 cls_cnt 0 2006.224.08:02:00.64#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.224.08:02:00.76#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.224.08:02:00.76#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.224.08:02:00.76#ibcon#enter wrdev, iclass 38, count 0 2006.224.08:02:00.76#ibcon#first serial, iclass 38, count 0 2006.224.08:02:00.76#ibcon#enter sib2, iclass 38, count 0 2006.224.08:02:00.76#ibcon#flushed, iclass 38, count 0 2006.224.08:02:00.76#ibcon#about to write, iclass 38, count 0 2006.224.08:02:00.76#ibcon#wrote, iclass 38, count 0 2006.224.08:02:00.76#ibcon#about to read 3, iclass 38, count 0 2006.224.08:02:00.78#ibcon#read 3, iclass 38, count 0 2006.224.08:02:00.78#ibcon#about to read 4, iclass 38, count 0 2006.224.08:02:00.78#ibcon#read 4, iclass 38, count 0 2006.224.08:02:00.78#ibcon#about to read 5, iclass 38, count 0 2006.224.08:02:00.78#ibcon#read 5, iclass 38, count 0 2006.224.08:02:00.78#ibcon#about to read 6, iclass 38, count 0 2006.224.08:02:00.78#ibcon#read 6, iclass 38, count 0 2006.224.08:02:00.78#ibcon#end of sib2, iclass 38, count 0 2006.224.08:02:00.78#ibcon#*mode == 0, iclass 38, count 0 2006.224.08:02:00.78#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.224.08:02:00.78#ibcon#[27=USB\r\n] 2006.224.08:02:00.78#ibcon#*before write, iclass 38, count 0 2006.224.08:02:00.78#ibcon#enter sib2, iclass 38, count 0 2006.224.08:02:00.78#ibcon#flushed, iclass 38, count 0 2006.224.08:02:00.78#ibcon#about to write, iclass 38, count 0 2006.224.08:02:00.78#ibcon#wrote, iclass 38, count 0 2006.224.08:02:00.78#ibcon#about to read 3, iclass 38, count 0 2006.224.08:02:00.81#ibcon#read 3, iclass 38, count 0 2006.224.08:02:00.81#ibcon#about to read 4, iclass 38, count 0 2006.224.08:02:00.81#ibcon#read 4, iclass 38, count 0 2006.224.08:02:00.81#ibcon#about to read 5, iclass 38, count 0 2006.224.08:02:00.81#ibcon#read 5, iclass 38, count 0 2006.224.08:02:00.81#ibcon#about to read 6, iclass 38, count 0 2006.224.08:02:00.81#ibcon#read 6, iclass 38, count 0 2006.224.08:02:00.81#ibcon#end of sib2, iclass 38, count 0 2006.224.08:02:00.81#ibcon#*after write, iclass 38, count 0 2006.224.08:02:00.81#ibcon#*before return 0, iclass 38, count 0 2006.224.08:02:00.81#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.224.08:02:00.81#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.224.08:02:00.81#ibcon#about to clear, iclass 38 cls_cnt 0 2006.224.08:02:00.81#ibcon#cleared, iclass 38 cls_cnt 0 2006.224.08:02:00.81$vc4f8/vblo=2,640.99 2006.224.08:02:00.81#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.224.08:02:00.81#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.224.08:02:00.81#ibcon#ireg 17 cls_cnt 0 2006.224.08:02:00.81#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.224.08:02:00.81#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.224.08:02:00.81#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.224.08:02:00.81#ibcon#enter wrdev, iclass 40, count 0 2006.224.08:02:00.81#ibcon#first serial, iclass 40, count 0 2006.224.08:02:00.81#ibcon#enter sib2, iclass 40, count 0 2006.224.08:02:00.81#ibcon#flushed, iclass 40, count 0 2006.224.08:02:00.81#ibcon#about to write, iclass 40, count 0 2006.224.08:02:00.81#ibcon#wrote, iclass 40, count 0 2006.224.08:02:00.81#ibcon#about to read 3, iclass 40, count 0 2006.224.08:02:00.83#ibcon#read 3, iclass 40, count 0 2006.224.08:02:00.83#ibcon#about to read 4, iclass 40, count 0 2006.224.08:02:00.83#ibcon#read 4, iclass 40, count 0 2006.224.08:02:00.83#ibcon#about to read 5, iclass 40, count 0 2006.224.08:02:00.83#ibcon#read 5, iclass 40, count 0 2006.224.08:02:00.83#ibcon#about to read 6, iclass 40, count 0 2006.224.08:02:00.83#ibcon#read 6, iclass 40, count 0 2006.224.08:02:00.83#ibcon#end of sib2, iclass 40, count 0 2006.224.08:02:00.83#ibcon#*mode == 0, iclass 40, count 0 2006.224.08:02:00.83#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.224.08:02:00.83#ibcon#[28=FRQ=02,640.99\r\n] 2006.224.08:02:00.83#ibcon#*before write, iclass 40, count 0 2006.224.08:02:00.83#ibcon#enter sib2, iclass 40, count 0 2006.224.08:02:00.83#ibcon#flushed, iclass 40, count 0 2006.224.08:02:00.83#ibcon#about to write, iclass 40, count 0 2006.224.08:02:00.83#ibcon#wrote, iclass 40, count 0 2006.224.08:02:00.83#ibcon#about to read 3, iclass 40, count 0 2006.224.08:02:00.87#ibcon#read 3, iclass 40, count 0 2006.224.08:02:00.87#ibcon#about to read 4, iclass 40, count 0 2006.224.08:02:00.87#ibcon#read 4, iclass 40, count 0 2006.224.08:02:00.87#ibcon#about to read 5, iclass 40, count 0 2006.224.08:02:00.87#ibcon#read 5, iclass 40, count 0 2006.224.08:02:00.87#ibcon#about to read 6, iclass 40, count 0 2006.224.08:02:00.87#ibcon#read 6, iclass 40, count 0 2006.224.08:02:00.87#ibcon#end of sib2, iclass 40, count 0 2006.224.08:02:00.87#ibcon#*after write, iclass 40, count 0 2006.224.08:02:00.87#ibcon#*before return 0, iclass 40, count 0 2006.224.08:02:00.87#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.224.08:02:00.87#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.224.08:02:00.87#ibcon#about to clear, iclass 40 cls_cnt 0 2006.224.08:02:00.87#ibcon#cleared, iclass 40 cls_cnt 0 2006.224.08:02:00.87$vc4f8/vb=2,4 2006.224.08:02:00.87#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.224.08:02:00.87#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.224.08:02:00.87#ibcon#ireg 11 cls_cnt 2 2006.224.08:02:00.87#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.224.08:02:00.93#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.224.08:02:00.93#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.224.08:02:00.93#ibcon#enter wrdev, iclass 4, count 2 2006.224.08:02:00.93#ibcon#first serial, iclass 4, count 2 2006.224.08:02:00.93#ibcon#enter sib2, iclass 4, count 2 2006.224.08:02:00.93#ibcon#flushed, iclass 4, count 2 2006.224.08:02:00.93#ibcon#about to write, iclass 4, count 2 2006.224.08:02:00.93#ibcon#wrote, iclass 4, count 2 2006.224.08:02:00.93#ibcon#about to read 3, iclass 4, count 2 2006.224.08:02:00.95#ibcon#read 3, iclass 4, count 2 2006.224.08:02:00.95#ibcon#about to read 4, iclass 4, count 2 2006.224.08:02:00.95#ibcon#read 4, iclass 4, count 2 2006.224.08:02:00.95#ibcon#about to read 5, iclass 4, count 2 2006.224.08:02:00.95#ibcon#read 5, iclass 4, count 2 2006.224.08:02:00.95#ibcon#about to read 6, iclass 4, count 2 2006.224.08:02:00.95#ibcon#read 6, iclass 4, count 2 2006.224.08:02:00.95#ibcon#end of sib2, iclass 4, count 2 2006.224.08:02:00.95#ibcon#*mode == 0, iclass 4, count 2 2006.224.08:02:00.95#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.224.08:02:00.95#ibcon#[27=AT02-04\r\n] 2006.224.08:02:00.95#ibcon#*before write, iclass 4, count 2 2006.224.08:02:00.95#ibcon#enter sib2, iclass 4, count 2 2006.224.08:02:00.95#ibcon#flushed, iclass 4, count 2 2006.224.08:02:00.95#ibcon#about to write, iclass 4, count 2 2006.224.08:02:00.95#ibcon#wrote, iclass 4, count 2 2006.224.08:02:00.95#ibcon#about to read 3, iclass 4, count 2 2006.224.08:02:00.98#ibcon#read 3, iclass 4, count 2 2006.224.08:02:00.98#ibcon#about to read 4, iclass 4, count 2 2006.224.08:02:00.98#ibcon#read 4, iclass 4, count 2 2006.224.08:02:00.98#ibcon#about to read 5, iclass 4, count 2 2006.224.08:02:00.98#ibcon#read 5, iclass 4, count 2 2006.224.08:02:00.98#ibcon#about to read 6, iclass 4, count 2 2006.224.08:02:00.98#ibcon#read 6, iclass 4, count 2 2006.224.08:02:00.98#ibcon#end of sib2, iclass 4, count 2 2006.224.08:02:00.98#ibcon#*after write, iclass 4, count 2 2006.224.08:02:00.98#ibcon#*before return 0, iclass 4, count 2 2006.224.08:02:00.98#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.224.08:02:00.98#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.224.08:02:00.98#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.224.08:02:00.98#ibcon#ireg 7 cls_cnt 0 2006.224.08:02:00.98#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.224.08:02:01.10#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.224.08:02:01.10#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.224.08:02:01.10#ibcon#enter wrdev, iclass 4, count 0 2006.224.08:02:01.10#ibcon#first serial, iclass 4, count 0 2006.224.08:02:01.10#ibcon#enter sib2, iclass 4, count 0 2006.224.08:02:01.10#ibcon#flushed, iclass 4, count 0 2006.224.08:02:01.10#ibcon#about to write, iclass 4, count 0 2006.224.08:02:01.10#ibcon#wrote, iclass 4, count 0 2006.224.08:02:01.10#ibcon#about to read 3, iclass 4, count 0 2006.224.08:02:01.12#ibcon#read 3, iclass 4, count 0 2006.224.08:02:01.12#ibcon#about to read 4, iclass 4, count 0 2006.224.08:02:01.12#ibcon#read 4, iclass 4, count 0 2006.224.08:02:01.12#ibcon#about to read 5, iclass 4, count 0 2006.224.08:02:01.12#ibcon#read 5, iclass 4, count 0 2006.224.08:02:01.12#ibcon#about to read 6, iclass 4, count 0 2006.224.08:02:01.12#ibcon#read 6, iclass 4, count 0 2006.224.08:02:01.12#ibcon#end of sib2, iclass 4, count 0 2006.224.08:02:01.12#ibcon#*mode == 0, iclass 4, count 0 2006.224.08:02:01.12#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.224.08:02:01.12#ibcon#[27=USB\r\n] 2006.224.08:02:01.12#ibcon#*before write, iclass 4, count 0 2006.224.08:02:01.12#ibcon#enter sib2, iclass 4, count 0 2006.224.08:02:01.12#ibcon#flushed, iclass 4, count 0 2006.224.08:02:01.12#ibcon#about to write, iclass 4, count 0 2006.224.08:02:01.12#ibcon#wrote, iclass 4, count 0 2006.224.08:02:01.12#ibcon#about to read 3, iclass 4, count 0 2006.224.08:02:01.15#ibcon#read 3, iclass 4, count 0 2006.224.08:02:01.15#ibcon#about to read 4, iclass 4, count 0 2006.224.08:02:01.15#ibcon#read 4, iclass 4, count 0 2006.224.08:02:01.15#ibcon#about to read 5, iclass 4, count 0 2006.224.08:02:01.15#ibcon#read 5, iclass 4, count 0 2006.224.08:02:01.15#ibcon#about to read 6, iclass 4, count 0 2006.224.08:02:01.15#ibcon#read 6, iclass 4, count 0 2006.224.08:02:01.15#ibcon#end of sib2, iclass 4, count 0 2006.224.08:02:01.15#ibcon#*after write, iclass 4, count 0 2006.224.08:02:01.15#ibcon#*before return 0, iclass 4, count 0 2006.224.08:02:01.15#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.224.08:02:01.15#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.224.08:02:01.15#ibcon#about to clear, iclass 4 cls_cnt 0 2006.224.08:02:01.15#ibcon#cleared, iclass 4 cls_cnt 0 2006.224.08:02:01.15$vc4f8/vblo=3,656.99 2006.224.08:02:01.15#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.224.08:02:01.15#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.224.08:02:01.15#ibcon#ireg 17 cls_cnt 0 2006.224.08:02:01.15#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.224.08:02:01.15#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.224.08:02:01.15#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.224.08:02:01.15#ibcon#enter wrdev, iclass 6, count 0 2006.224.08:02:01.15#ibcon#first serial, iclass 6, count 0 2006.224.08:02:01.15#ibcon#enter sib2, iclass 6, count 0 2006.224.08:02:01.15#ibcon#flushed, iclass 6, count 0 2006.224.08:02:01.15#ibcon#about to write, iclass 6, count 0 2006.224.08:02:01.15#ibcon#wrote, iclass 6, count 0 2006.224.08:02:01.15#ibcon#about to read 3, iclass 6, count 0 2006.224.08:02:01.18#ibcon#read 3, iclass 6, count 0 2006.224.08:02:01.18#ibcon#about to read 4, iclass 6, count 0 2006.224.08:02:01.18#ibcon#read 4, iclass 6, count 0 2006.224.08:02:01.18#ibcon#about to read 5, iclass 6, count 0 2006.224.08:02:01.18#ibcon#read 5, iclass 6, count 0 2006.224.08:02:01.18#ibcon#about to read 6, iclass 6, count 0 2006.224.08:02:01.18#ibcon#read 6, iclass 6, count 0 2006.224.08:02:01.18#ibcon#end of sib2, iclass 6, count 0 2006.224.08:02:01.18#ibcon#*mode == 0, iclass 6, count 0 2006.224.08:02:01.18#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.224.08:02:01.18#ibcon#[28=FRQ=03,656.99\r\n] 2006.224.08:02:01.18#ibcon#*before write, iclass 6, count 0 2006.224.08:02:01.18#ibcon#enter sib2, iclass 6, count 0 2006.224.08:02:01.18#ibcon#flushed, iclass 6, count 0 2006.224.08:02:01.18#ibcon#about to write, iclass 6, count 0 2006.224.08:02:01.18#ibcon#wrote, iclass 6, count 0 2006.224.08:02:01.18#ibcon#about to read 3, iclass 6, count 0 2006.224.08:02:01.22#ibcon#read 3, iclass 6, count 0 2006.224.08:02:01.22#ibcon#about to read 4, iclass 6, count 0 2006.224.08:02:01.22#ibcon#read 4, iclass 6, count 0 2006.224.08:02:01.22#ibcon#about to read 5, iclass 6, count 0 2006.224.08:02:01.22#ibcon#read 5, iclass 6, count 0 2006.224.08:02:01.22#ibcon#about to read 6, iclass 6, count 0 2006.224.08:02:01.22#ibcon#read 6, iclass 6, count 0 2006.224.08:02:01.22#ibcon#end of sib2, iclass 6, count 0 2006.224.08:02:01.22#ibcon#*after write, iclass 6, count 0 2006.224.08:02:01.22#ibcon#*before return 0, iclass 6, count 0 2006.224.08:02:01.22#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.224.08:02:01.22#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.224.08:02:01.22#ibcon#about to clear, iclass 6 cls_cnt 0 2006.224.08:02:01.22#ibcon#cleared, iclass 6 cls_cnt 0 2006.224.08:02:01.22$vc4f8/vb=3,4 2006.224.08:02:01.22#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.224.08:02:01.22#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.224.08:02:01.22#ibcon#ireg 11 cls_cnt 2 2006.224.08:02:01.22#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.224.08:02:01.27#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.224.08:02:01.27#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.224.08:02:01.27#ibcon#enter wrdev, iclass 10, count 2 2006.224.08:02:01.27#ibcon#first serial, iclass 10, count 2 2006.224.08:02:01.27#ibcon#enter sib2, iclass 10, count 2 2006.224.08:02:01.27#ibcon#flushed, iclass 10, count 2 2006.224.08:02:01.27#ibcon#about to write, iclass 10, count 2 2006.224.08:02:01.27#ibcon#wrote, iclass 10, count 2 2006.224.08:02:01.27#ibcon#about to read 3, iclass 10, count 2 2006.224.08:02:01.29#ibcon#read 3, iclass 10, count 2 2006.224.08:02:01.29#ibcon#about to read 4, iclass 10, count 2 2006.224.08:02:01.29#ibcon#read 4, iclass 10, count 2 2006.224.08:02:01.29#ibcon#about to read 5, iclass 10, count 2 2006.224.08:02:01.29#ibcon#read 5, iclass 10, count 2 2006.224.08:02:01.29#ibcon#about to read 6, iclass 10, count 2 2006.224.08:02:01.29#ibcon#read 6, iclass 10, count 2 2006.224.08:02:01.29#ibcon#end of sib2, iclass 10, count 2 2006.224.08:02:01.29#ibcon#*mode == 0, iclass 10, count 2 2006.224.08:02:01.29#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.224.08:02:01.29#ibcon#[27=AT03-04\r\n] 2006.224.08:02:01.29#ibcon#*before write, iclass 10, count 2 2006.224.08:02:01.29#ibcon#enter sib2, iclass 10, count 2 2006.224.08:02:01.29#ibcon#flushed, iclass 10, count 2 2006.224.08:02:01.29#ibcon#about to write, iclass 10, count 2 2006.224.08:02:01.29#ibcon#wrote, iclass 10, count 2 2006.224.08:02:01.29#ibcon#about to read 3, iclass 10, count 2 2006.224.08:02:01.32#ibcon#read 3, iclass 10, count 2 2006.224.08:02:01.32#ibcon#about to read 4, iclass 10, count 2 2006.224.08:02:01.32#ibcon#read 4, iclass 10, count 2 2006.224.08:02:01.32#ibcon#about to read 5, iclass 10, count 2 2006.224.08:02:01.32#ibcon#read 5, iclass 10, count 2 2006.224.08:02:01.32#ibcon#about to read 6, iclass 10, count 2 2006.224.08:02:01.32#ibcon#read 6, iclass 10, count 2 2006.224.08:02:01.32#ibcon#end of sib2, iclass 10, count 2 2006.224.08:02:01.32#ibcon#*after write, iclass 10, count 2 2006.224.08:02:01.32#ibcon#*before return 0, iclass 10, count 2 2006.224.08:02:01.32#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.224.08:02:01.32#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.224.08:02:01.32#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.224.08:02:01.32#ibcon#ireg 7 cls_cnt 0 2006.224.08:02:01.32#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.224.08:02:01.44#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.224.08:02:01.44#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.224.08:02:01.44#ibcon#enter wrdev, iclass 10, count 0 2006.224.08:02:01.44#ibcon#first serial, iclass 10, count 0 2006.224.08:02:01.44#ibcon#enter sib2, iclass 10, count 0 2006.224.08:02:01.44#ibcon#flushed, iclass 10, count 0 2006.224.08:02:01.44#ibcon#about to write, iclass 10, count 0 2006.224.08:02:01.44#ibcon#wrote, iclass 10, count 0 2006.224.08:02:01.44#ibcon#about to read 3, iclass 10, count 0 2006.224.08:02:01.46#ibcon#read 3, iclass 10, count 0 2006.224.08:02:01.46#ibcon#about to read 4, iclass 10, count 0 2006.224.08:02:01.46#ibcon#read 4, iclass 10, count 0 2006.224.08:02:01.46#ibcon#about to read 5, iclass 10, count 0 2006.224.08:02:01.46#ibcon#read 5, iclass 10, count 0 2006.224.08:02:01.46#ibcon#about to read 6, iclass 10, count 0 2006.224.08:02:01.46#ibcon#read 6, iclass 10, count 0 2006.224.08:02:01.46#ibcon#end of sib2, iclass 10, count 0 2006.224.08:02:01.46#ibcon#*mode == 0, iclass 10, count 0 2006.224.08:02:01.46#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.224.08:02:01.46#ibcon#[27=USB\r\n] 2006.224.08:02:01.46#ibcon#*before write, iclass 10, count 0 2006.224.08:02:01.46#ibcon#enter sib2, iclass 10, count 0 2006.224.08:02:01.46#ibcon#flushed, iclass 10, count 0 2006.224.08:02:01.46#ibcon#about to write, iclass 10, count 0 2006.224.08:02:01.46#ibcon#wrote, iclass 10, count 0 2006.224.08:02:01.46#ibcon#about to read 3, iclass 10, count 0 2006.224.08:02:01.49#ibcon#read 3, iclass 10, count 0 2006.224.08:02:01.49#ibcon#about to read 4, iclass 10, count 0 2006.224.08:02:01.49#ibcon#read 4, iclass 10, count 0 2006.224.08:02:01.49#ibcon#about to read 5, iclass 10, count 0 2006.224.08:02:01.49#ibcon#read 5, iclass 10, count 0 2006.224.08:02:01.49#ibcon#about to read 6, iclass 10, count 0 2006.224.08:02:01.49#ibcon#read 6, iclass 10, count 0 2006.224.08:02:01.49#ibcon#end of sib2, iclass 10, count 0 2006.224.08:02:01.49#ibcon#*after write, iclass 10, count 0 2006.224.08:02:01.49#ibcon#*before return 0, iclass 10, count 0 2006.224.08:02:01.49#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.224.08:02:01.49#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.224.08:02:01.49#ibcon#about to clear, iclass 10 cls_cnt 0 2006.224.08:02:01.49#ibcon#cleared, iclass 10 cls_cnt 0 2006.224.08:02:01.49$vc4f8/vblo=4,712.99 2006.224.08:02:01.49#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.224.08:02:01.49#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.224.08:02:01.49#ibcon#ireg 17 cls_cnt 0 2006.224.08:02:01.49#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.224.08:02:01.49#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.224.08:02:01.49#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.224.08:02:01.49#ibcon#enter wrdev, iclass 12, count 0 2006.224.08:02:01.49#ibcon#first serial, iclass 12, count 0 2006.224.08:02:01.49#ibcon#enter sib2, iclass 12, count 0 2006.224.08:02:01.49#ibcon#flushed, iclass 12, count 0 2006.224.08:02:01.49#ibcon#about to write, iclass 12, count 0 2006.224.08:02:01.49#ibcon#wrote, iclass 12, count 0 2006.224.08:02:01.49#ibcon#about to read 3, iclass 12, count 0 2006.224.08:02:01.51#ibcon#read 3, iclass 12, count 0 2006.224.08:02:01.51#ibcon#about to read 4, iclass 12, count 0 2006.224.08:02:01.51#ibcon#read 4, iclass 12, count 0 2006.224.08:02:01.51#ibcon#about to read 5, iclass 12, count 0 2006.224.08:02:01.51#ibcon#read 5, iclass 12, count 0 2006.224.08:02:01.51#ibcon#about to read 6, iclass 12, count 0 2006.224.08:02:01.51#ibcon#read 6, iclass 12, count 0 2006.224.08:02:01.51#ibcon#end of sib2, iclass 12, count 0 2006.224.08:02:01.51#ibcon#*mode == 0, iclass 12, count 0 2006.224.08:02:01.51#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.224.08:02:01.51#ibcon#[28=FRQ=04,712.99\r\n] 2006.224.08:02:01.51#ibcon#*before write, iclass 12, count 0 2006.224.08:02:01.51#ibcon#enter sib2, iclass 12, count 0 2006.224.08:02:01.51#ibcon#flushed, iclass 12, count 0 2006.224.08:02:01.51#ibcon#about to write, iclass 12, count 0 2006.224.08:02:01.51#ibcon#wrote, iclass 12, count 0 2006.224.08:02:01.51#ibcon#about to read 3, iclass 12, count 0 2006.224.08:02:01.55#ibcon#read 3, iclass 12, count 0 2006.224.08:02:01.55#ibcon#about to read 4, iclass 12, count 0 2006.224.08:02:01.55#ibcon#read 4, iclass 12, count 0 2006.224.08:02:01.55#ibcon#about to read 5, iclass 12, count 0 2006.224.08:02:01.55#ibcon#read 5, iclass 12, count 0 2006.224.08:02:01.55#ibcon#about to read 6, iclass 12, count 0 2006.224.08:02:01.55#ibcon#read 6, iclass 12, count 0 2006.224.08:02:01.55#ibcon#end of sib2, iclass 12, count 0 2006.224.08:02:01.55#ibcon#*after write, iclass 12, count 0 2006.224.08:02:01.55#ibcon#*before return 0, iclass 12, count 0 2006.224.08:02:01.55#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.224.08:02:01.55#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.224.08:02:01.55#ibcon#about to clear, iclass 12 cls_cnt 0 2006.224.08:02:01.55#ibcon#cleared, iclass 12 cls_cnt 0 2006.224.08:02:01.55$vc4f8/vb=4,4 2006.224.08:02:01.55#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.224.08:02:01.55#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.224.08:02:01.55#ibcon#ireg 11 cls_cnt 2 2006.224.08:02:01.55#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.224.08:02:01.61#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.224.08:02:01.61#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.224.08:02:01.61#ibcon#enter wrdev, iclass 14, count 2 2006.224.08:02:01.61#ibcon#first serial, iclass 14, count 2 2006.224.08:02:01.61#ibcon#enter sib2, iclass 14, count 2 2006.224.08:02:01.61#ibcon#flushed, iclass 14, count 2 2006.224.08:02:01.61#ibcon#about to write, iclass 14, count 2 2006.224.08:02:01.61#ibcon#wrote, iclass 14, count 2 2006.224.08:02:01.61#ibcon#about to read 3, iclass 14, count 2 2006.224.08:02:01.63#ibcon#read 3, iclass 14, count 2 2006.224.08:02:01.63#ibcon#about to read 4, iclass 14, count 2 2006.224.08:02:01.63#ibcon#read 4, iclass 14, count 2 2006.224.08:02:01.63#ibcon#about to read 5, iclass 14, count 2 2006.224.08:02:01.63#ibcon#read 5, iclass 14, count 2 2006.224.08:02:01.63#ibcon#about to read 6, iclass 14, count 2 2006.224.08:02:01.63#ibcon#read 6, iclass 14, count 2 2006.224.08:02:01.63#ibcon#end of sib2, iclass 14, count 2 2006.224.08:02:01.63#ibcon#*mode == 0, iclass 14, count 2 2006.224.08:02:01.63#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.224.08:02:01.63#ibcon#[27=AT04-04\r\n] 2006.224.08:02:01.63#ibcon#*before write, iclass 14, count 2 2006.224.08:02:01.63#ibcon#enter sib2, iclass 14, count 2 2006.224.08:02:01.63#ibcon#flushed, iclass 14, count 2 2006.224.08:02:01.63#ibcon#about to write, iclass 14, count 2 2006.224.08:02:01.63#ibcon#wrote, iclass 14, count 2 2006.224.08:02:01.63#ibcon#about to read 3, iclass 14, count 2 2006.224.08:02:01.66#ibcon#read 3, iclass 14, count 2 2006.224.08:02:01.66#ibcon#about to read 4, iclass 14, count 2 2006.224.08:02:01.66#ibcon#read 4, iclass 14, count 2 2006.224.08:02:01.66#ibcon#about to read 5, iclass 14, count 2 2006.224.08:02:01.66#ibcon#read 5, iclass 14, count 2 2006.224.08:02:01.66#ibcon#about to read 6, iclass 14, count 2 2006.224.08:02:01.66#ibcon#read 6, iclass 14, count 2 2006.224.08:02:01.66#ibcon#end of sib2, iclass 14, count 2 2006.224.08:02:01.66#ibcon#*after write, iclass 14, count 2 2006.224.08:02:01.66#ibcon#*before return 0, iclass 14, count 2 2006.224.08:02:01.66#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.224.08:02:01.66#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.224.08:02:01.66#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.224.08:02:01.66#ibcon#ireg 7 cls_cnt 0 2006.224.08:02:01.66#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.224.08:02:01.78#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.224.08:02:01.78#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.224.08:02:01.78#ibcon#enter wrdev, iclass 14, count 0 2006.224.08:02:01.78#ibcon#first serial, iclass 14, count 0 2006.224.08:02:01.78#ibcon#enter sib2, iclass 14, count 0 2006.224.08:02:01.78#ibcon#flushed, iclass 14, count 0 2006.224.08:02:01.78#ibcon#about to write, iclass 14, count 0 2006.224.08:02:01.78#ibcon#wrote, iclass 14, count 0 2006.224.08:02:01.78#ibcon#about to read 3, iclass 14, count 0 2006.224.08:02:01.80#ibcon#read 3, iclass 14, count 0 2006.224.08:02:01.80#ibcon#about to read 4, iclass 14, count 0 2006.224.08:02:01.80#ibcon#read 4, iclass 14, count 0 2006.224.08:02:01.80#ibcon#about to read 5, iclass 14, count 0 2006.224.08:02:01.80#ibcon#read 5, iclass 14, count 0 2006.224.08:02:01.80#ibcon#about to read 6, iclass 14, count 0 2006.224.08:02:01.80#ibcon#read 6, iclass 14, count 0 2006.224.08:02:01.80#ibcon#end of sib2, iclass 14, count 0 2006.224.08:02:01.80#ibcon#*mode == 0, iclass 14, count 0 2006.224.08:02:01.80#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.224.08:02:01.80#ibcon#[27=USB\r\n] 2006.224.08:02:01.80#ibcon#*before write, iclass 14, count 0 2006.224.08:02:01.80#ibcon#enter sib2, iclass 14, count 0 2006.224.08:02:01.80#ibcon#flushed, iclass 14, count 0 2006.224.08:02:01.80#ibcon#about to write, iclass 14, count 0 2006.224.08:02:01.80#ibcon#wrote, iclass 14, count 0 2006.224.08:02:01.80#ibcon#about to read 3, iclass 14, count 0 2006.224.08:02:01.83#ibcon#read 3, iclass 14, count 0 2006.224.08:02:01.83#ibcon#about to read 4, iclass 14, count 0 2006.224.08:02:01.83#ibcon#read 4, iclass 14, count 0 2006.224.08:02:01.83#ibcon#about to read 5, iclass 14, count 0 2006.224.08:02:01.83#ibcon#read 5, iclass 14, count 0 2006.224.08:02:01.83#ibcon#about to read 6, iclass 14, count 0 2006.224.08:02:01.83#ibcon#read 6, iclass 14, count 0 2006.224.08:02:01.83#ibcon#end of sib2, iclass 14, count 0 2006.224.08:02:01.83#ibcon#*after write, iclass 14, count 0 2006.224.08:02:01.83#ibcon#*before return 0, iclass 14, count 0 2006.224.08:02:01.83#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.224.08:02:01.83#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.224.08:02:01.83#ibcon#about to clear, iclass 14 cls_cnt 0 2006.224.08:02:01.83#ibcon#cleared, iclass 14 cls_cnt 0 2006.224.08:02:01.83$vc4f8/vblo=5,744.99 2006.224.08:02:01.83#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.224.08:02:01.83#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.224.08:02:01.83#ibcon#ireg 17 cls_cnt 0 2006.224.08:02:01.83#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.224.08:02:01.83#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.224.08:02:01.83#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.224.08:02:01.83#ibcon#enter wrdev, iclass 16, count 0 2006.224.08:02:01.83#ibcon#first serial, iclass 16, count 0 2006.224.08:02:01.83#ibcon#enter sib2, iclass 16, count 0 2006.224.08:02:01.83#ibcon#flushed, iclass 16, count 0 2006.224.08:02:01.83#ibcon#about to write, iclass 16, count 0 2006.224.08:02:01.83#ibcon#wrote, iclass 16, count 0 2006.224.08:02:01.83#ibcon#about to read 3, iclass 16, count 0 2006.224.08:02:01.85#ibcon#read 3, iclass 16, count 0 2006.224.08:02:01.85#ibcon#about to read 4, iclass 16, count 0 2006.224.08:02:01.85#ibcon#read 4, iclass 16, count 0 2006.224.08:02:01.85#ibcon#about to read 5, iclass 16, count 0 2006.224.08:02:01.85#ibcon#read 5, iclass 16, count 0 2006.224.08:02:01.85#ibcon#about to read 6, iclass 16, count 0 2006.224.08:02:01.85#ibcon#read 6, iclass 16, count 0 2006.224.08:02:01.85#ibcon#end of sib2, iclass 16, count 0 2006.224.08:02:01.85#ibcon#*mode == 0, iclass 16, count 0 2006.224.08:02:01.85#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.224.08:02:01.85#ibcon#[28=FRQ=05,744.99\r\n] 2006.224.08:02:01.85#ibcon#*before write, iclass 16, count 0 2006.224.08:02:01.85#ibcon#enter sib2, iclass 16, count 0 2006.224.08:02:01.85#ibcon#flushed, iclass 16, count 0 2006.224.08:02:01.85#ibcon#about to write, iclass 16, count 0 2006.224.08:02:01.85#ibcon#wrote, iclass 16, count 0 2006.224.08:02:01.85#ibcon#about to read 3, iclass 16, count 0 2006.224.08:02:01.89#ibcon#read 3, iclass 16, count 0 2006.224.08:02:01.89#ibcon#about to read 4, iclass 16, count 0 2006.224.08:02:01.89#ibcon#read 4, iclass 16, count 0 2006.224.08:02:01.89#ibcon#about to read 5, iclass 16, count 0 2006.224.08:02:01.89#ibcon#read 5, iclass 16, count 0 2006.224.08:02:01.89#ibcon#about to read 6, iclass 16, count 0 2006.224.08:02:01.89#ibcon#read 6, iclass 16, count 0 2006.224.08:02:01.89#ibcon#end of sib2, iclass 16, count 0 2006.224.08:02:01.89#ibcon#*after write, iclass 16, count 0 2006.224.08:02:01.89#ibcon#*before return 0, iclass 16, count 0 2006.224.08:02:01.89#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.224.08:02:01.89#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.224.08:02:01.89#ibcon#about to clear, iclass 16 cls_cnt 0 2006.224.08:02:01.89#ibcon#cleared, iclass 16 cls_cnt 0 2006.224.08:02:01.89$vc4f8/vb=5,4 2006.224.08:02:01.89#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.224.08:02:01.89#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.224.08:02:01.89#ibcon#ireg 11 cls_cnt 2 2006.224.08:02:01.89#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.224.08:02:01.95#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.224.08:02:01.95#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.224.08:02:01.95#ibcon#enter wrdev, iclass 18, count 2 2006.224.08:02:01.95#ibcon#first serial, iclass 18, count 2 2006.224.08:02:01.95#ibcon#enter sib2, iclass 18, count 2 2006.224.08:02:01.95#ibcon#flushed, iclass 18, count 2 2006.224.08:02:01.95#ibcon#about to write, iclass 18, count 2 2006.224.08:02:01.95#ibcon#wrote, iclass 18, count 2 2006.224.08:02:01.95#ibcon#about to read 3, iclass 18, count 2 2006.224.08:02:01.97#ibcon#read 3, iclass 18, count 2 2006.224.08:02:01.97#ibcon#about to read 4, iclass 18, count 2 2006.224.08:02:01.97#ibcon#read 4, iclass 18, count 2 2006.224.08:02:01.97#ibcon#about to read 5, iclass 18, count 2 2006.224.08:02:01.97#ibcon#read 5, iclass 18, count 2 2006.224.08:02:01.97#ibcon#about to read 6, iclass 18, count 2 2006.224.08:02:01.97#ibcon#read 6, iclass 18, count 2 2006.224.08:02:01.97#ibcon#end of sib2, iclass 18, count 2 2006.224.08:02:01.97#ibcon#*mode == 0, iclass 18, count 2 2006.224.08:02:01.97#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.224.08:02:01.97#ibcon#[27=AT05-04\r\n] 2006.224.08:02:01.97#ibcon#*before write, iclass 18, count 2 2006.224.08:02:01.97#ibcon#enter sib2, iclass 18, count 2 2006.224.08:02:01.97#ibcon#flushed, iclass 18, count 2 2006.224.08:02:01.97#ibcon#about to write, iclass 18, count 2 2006.224.08:02:01.97#ibcon#wrote, iclass 18, count 2 2006.224.08:02:01.97#ibcon#about to read 3, iclass 18, count 2 2006.224.08:02:02.00#ibcon#read 3, iclass 18, count 2 2006.224.08:02:02.00#ibcon#about to read 4, iclass 18, count 2 2006.224.08:02:02.00#ibcon#read 4, iclass 18, count 2 2006.224.08:02:02.00#ibcon#about to read 5, iclass 18, count 2 2006.224.08:02:02.00#ibcon#read 5, iclass 18, count 2 2006.224.08:02:02.00#ibcon#about to read 6, iclass 18, count 2 2006.224.08:02:02.00#ibcon#read 6, iclass 18, count 2 2006.224.08:02:02.00#ibcon#end of sib2, iclass 18, count 2 2006.224.08:02:02.00#ibcon#*after write, iclass 18, count 2 2006.224.08:02:02.00#ibcon#*before return 0, iclass 18, count 2 2006.224.08:02:02.00#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.224.08:02:02.00#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.224.08:02:02.00#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.224.08:02:02.00#ibcon#ireg 7 cls_cnt 0 2006.224.08:02:02.00#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.224.08:02:02.12#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.224.08:02:02.12#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.224.08:02:02.12#ibcon#enter wrdev, iclass 18, count 0 2006.224.08:02:02.12#ibcon#first serial, iclass 18, count 0 2006.224.08:02:02.12#ibcon#enter sib2, iclass 18, count 0 2006.224.08:02:02.12#ibcon#flushed, iclass 18, count 0 2006.224.08:02:02.12#ibcon#about to write, iclass 18, count 0 2006.224.08:02:02.12#ibcon#wrote, iclass 18, count 0 2006.224.08:02:02.12#ibcon#about to read 3, iclass 18, count 0 2006.224.08:02:02.14#ibcon#read 3, iclass 18, count 0 2006.224.08:02:02.14#ibcon#about to read 4, iclass 18, count 0 2006.224.08:02:02.14#ibcon#read 4, iclass 18, count 0 2006.224.08:02:02.14#ibcon#about to read 5, iclass 18, count 0 2006.224.08:02:02.14#ibcon#read 5, iclass 18, count 0 2006.224.08:02:02.14#ibcon#about to read 6, iclass 18, count 0 2006.224.08:02:02.14#ibcon#read 6, iclass 18, count 0 2006.224.08:02:02.14#ibcon#end of sib2, iclass 18, count 0 2006.224.08:02:02.14#ibcon#*mode == 0, iclass 18, count 0 2006.224.08:02:02.14#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.224.08:02:02.14#ibcon#[27=USB\r\n] 2006.224.08:02:02.14#ibcon#*before write, iclass 18, count 0 2006.224.08:02:02.14#ibcon#enter sib2, iclass 18, count 0 2006.224.08:02:02.14#ibcon#flushed, iclass 18, count 0 2006.224.08:02:02.14#ibcon#about to write, iclass 18, count 0 2006.224.08:02:02.14#ibcon#wrote, iclass 18, count 0 2006.224.08:02:02.14#ibcon#about to read 3, iclass 18, count 0 2006.224.08:02:02.17#ibcon#read 3, iclass 18, count 0 2006.224.08:02:02.17#ibcon#about to read 4, iclass 18, count 0 2006.224.08:02:02.17#ibcon#read 4, iclass 18, count 0 2006.224.08:02:02.17#ibcon#about to read 5, iclass 18, count 0 2006.224.08:02:02.17#ibcon#read 5, iclass 18, count 0 2006.224.08:02:02.17#ibcon#about to read 6, iclass 18, count 0 2006.224.08:02:02.17#ibcon#read 6, iclass 18, count 0 2006.224.08:02:02.17#ibcon#end of sib2, iclass 18, count 0 2006.224.08:02:02.17#ibcon#*after write, iclass 18, count 0 2006.224.08:02:02.17#ibcon#*before return 0, iclass 18, count 0 2006.224.08:02:02.17#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.224.08:02:02.17#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.224.08:02:02.17#ibcon#about to clear, iclass 18 cls_cnt 0 2006.224.08:02:02.17#ibcon#cleared, iclass 18 cls_cnt 0 2006.224.08:02:02.17$vc4f8/vblo=6,752.99 2006.224.08:02:02.17#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.224.08:02:02.17#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.224.08:02:02.17#ibcon#ireg 17 cls_cnt 0 2006.224.08:02:02.17#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.224.08:02:02.17#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.224.08:02:02.17#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.224.08:02:02.17#ibcon#enter wrdev, iclass 20, count 0 2006.224.08:02:02.17#ibcon#first serial, iclass 20, count 0 2006.224.08:02:02.17#ibcon#enter sib2, iclass 20, count 0 2006.224.08:02:02.17#ibcon#flushed, iclass 20, count 0 2006.224.08:02:02.17#ibcon#about to write, iclass 20, count 0 2006.224.08:02:02.17#ibcon#wrote, iclass 20, count 0 2006.224.08:02:02.17#ibcon#about to read 3, iclass 20, count 0 2006.224.08:02:02.20#ibcon#read 3, iclass 20, count 0 2006.224.08:02:02.20#ibcon#about to read 4, iclass 20, count 0 2006.224.08:02:02.20#ibcon#read 4, iclass 20, count 0 2006.224.08:02:02.20#ibcon#about to read 5, iclass 20, count 0 2006.224.08:02:02.20#ibcon#read 5, iclass 20, count 0 2006.224.08:02:02.20#ibcon#about to read 6, iclass 20, count 0 2006.224.08:02:02.20#ibcon#read 6, iclass 20, count 0 2006.224.08:02:02.20#ibcon#end of sib2, iclass 20, count 0 2006.224.08:02:02.20#ibcon#*mode == 0, iclass 20, count 0 2006.224.08:02:02.20#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.224.08:02:02.20#ibcon#[28=FRQ=06,752.99\r\n] 2006.224.08:02:02.20#ibcon#*before write, iclass 20, count 0 2006.224.08:02:02.20#ibcon#enter sib2, iclass 20, count 0 2006.224.08:02:02.20#ibcon#flushed, iclass 20, count 0 2006.224.08:02:02.20#ibcon#about to write, iclass 20, count 0 2006.224.08:02:02.20#ibcon#wrote, iclass 20, count 0 2006.224.08:02:02.20#ibcon#about to read 3, iclass 20, count 0 2006.224.08:02:02.24#ibcon#read 3, iclass 20, count 0 2006.224.08:02:02.24#ibcon#about to read 4, iclass 20, count 0 2006.224.08:02:02.24#ibcon#read 4, iclass 20, count 0 2006.224.08:02:02.24#ibcon#about to read 5, iclass 20, count 0 2006.224.08:02:02.24#ibcon#read 5, iclass 20, count 0 2006.224.08:02:02.24#ibcon#about to read 6, iclass 20, count 0 2006.224.08:02:02.24#ibcon#read 6, iclass 20, count 0 2006.224.08:02:02.24#ibcon#end of sib2, iclass 20, count 0 2006.224.08:02:02.24#ibcon#*after write, iclass 20, count 0 2006.224.08:02:02.24#ibcon#*before return 0, iclass 20, count 0 2006.224.08:02:02.24#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.224.08:02:02.24#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.224.08:02:02.24#ibcon#about to clear, iclass 20 cls_cnt 0 2006.224.08:02:02.24#ibcon#cleared, iclass 20 cls_cnt 0 2006.224.08:02:02.24$vc4f8/vb=6,4 2006.224.08:02:02.24#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.224.08:02:02.24#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.224.08:02:02.24#ibcon#ireg 11 cls_cnt 2 2006.224.08:02:02.24#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.224.08:02:02.29#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.224.08:02:02.29#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.224.08:02:02.29#ibcon#enter wrdev, iclass 22, count 2 2006.224.08:02:02.29#ibcon#first serial, iclass 22, count 2 2006.224.08:02:02.29#ibcon#enter sib2, iclass 22, count 2 2006.224.08:02:02.29#ibcon#flushed, iclass 22, count 2 2006.224.08:02:02.29#ibcon#about to write, iclass 22, count 2 2006.224.08:02:02.29#ibcon#wrote, iclass 22, count 2 2006.224.08:02:02.29#ibcon#about to read 3, iclass 22, count 2 2006.224.08:02:02.31#ibcon#read 3, iclass 22, count 2 2006.224.08:02:02.31#ibcon#about to read 4, iclass 22, count 2 2006.224.08:02:02.31#ibcon#read 4, iclass 22, count 2 2006.224.08:02:02.31#ibcon#about to read 5, iclass 22, count 2 2006.224.08:02:02.31#ibcon#read 5, iclass 22, count 2 2006.224.08:02:02.31#ibcon#about to read 6, iclass 22, count 2 2006.224.08:02:02.31#ibcon#read 6, iclass 22, count 2 2006.224.08:02:02.31#ibcon#end of sib2, iclass 22, count 2 2006.224.08:02:02.31#ibcon#*mode == 0, iclass 22, count 2 2006.224.08:02:02.31#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.224.08:02:02.31#ibcon#[27=AT06-04\r\n] 2006.224.08:02:02.31#ibcon#*before write, iclass 22, count 2 2006.224.08:02:02.31#ibcon#enter sib2, iclass 22, count 2 2006.224.08:02:02.31#ibcon#flushed, iclass 22, count 2 2006.224.08:02:02.31#ibcon#about to write, iclass 22, count 2 2006.224.08:02:02.31#ibcon#wrote, iclass 22, count 2 2006.224.08:02:02.31#ibcon#about to read 3, iclass 22, count 2 2006.224.08:02:02.34#ibcon#read 3, iclass 22, count 2 2006.224.08:02:02.34#ibcon#about to read 4, iclass 22, count 2 2006.224.08:02:02.34#ibcon#read 4, iclass 22, count 2 2006.224.08:02:02.34#ibcon#about to read 5, iclass 22, count 2 2006.224.08:02:02.34#ibcon#read 5, iclass 22, count 2 2006.224.08:02:02.34#ibcon#about to read 6, iclass 22, count 2 2006.224.08:02:02.34#ibcon#read 6, iclass 22, count 2 2006.224.08:02:02.34#ibcon#end of sib2, iclass 22, count 2 2006.224.08:02:02.34#ibcon#*after write, iclass 22, count 2 2006.224.08:02:02.34#ibcon#*before return 0, iclass 22, count 2 2006.224.08:02:02.34#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.224.08:02:02.34#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.224.08:02:02.34#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.224.08:02:02.34#ibcon#ireg 7 cls_cnt 0 2006.224.08:02:02.34#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.224.08:02:02.46#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.224.08:02:02.46#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.224.08:02:02.46#ibcon#enter wrdev, iclass 22, count 0 2006.224.08:02:02.46#ibcon#first serial, iclass 22, count 0 2006.224.08:02:02.46#ibcon#enter sib2, iclass 22, count 0 2006.224.08:02:02.46#ibcon#flushed, iclass 22, count 0 2006.224.08:02:02.46#ibcon#about to write, iclass 22, count 0 2006.224.08:02:02.46#ibcon#wrote, iclass 22, count 0 2006.224.08:02:02.46#ibcon#about to read 3, iclass 22, count 0 2006.224.08:02:02.48#ibcon#read 3, iclass 22, count 0 2006.224.08:02:02.48#ibcon#about to read 4, iclass 22, count 0 2006.224.08:02:02.48#ibcon#read 4, iclass 22, count 0 2006.224.08:02:02.48#ibcon#about to read 5, iclass 22, count 0 2006.224.08:02:02.48#ibcon#read 5, iclass 22, count 0 2006.224.08:02:02.48#ibcon#about to read 6, iclass 22, count 0 2006.224.08:02:02.48#ibcon#read 6, iclass 22, count 0 2006.224.08:02:02.48#ibcon#end of sib2, iclass 22, count 0 2006.224.08:02:02.48#ibcon#*mode == 0, iclass 22, count 0 2006.224.08:02:02.48#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.224.08:02:02.48#ibcon#[27=USB\r\n] 2006.224.08:02:02.48#ibcon#*before write, iclass 22, count 0 2006.224.08:02:02.48#ibcon#enter sib2, iclass 22, count 0 2006.224.08:02:02.48#ibcon#flushed, iclass 22, count 0 2006.224.08:02:02.48#ibcon#about to write, iclass 22, count 0 2006.224.08:02:02.48#ibcon#wrote, iclass 22, count 0 2006.224.08:02:02.48#ibcon#about to read 3, iclass 22, count 0 2006.224.08:02:02.51#ibcon#read 3, iclass 22, count 0 2006.224.08:02:02.51#ibcon#about to read 4, iclass 22, count 0 2006.224.08:02:02.51#ibcon#read 4, iclass 22, count 0 2006.224.08:02:02.51#ibcon#about to read 5, iclass 22, count 0 2006.224.08:02:02.51#ibcon#read 5, iclass 22, count 0 2006.224.08:02:02.51#ibcon#about to read 6, iclass 22, count 0 2006.224.08:02:02.51#ibcon#read 6, iclass 22, count 0 2006.224.08:02:02.51#ibcon#end of sib2, iclass 22, count 0 2006.224.08:02:02.51#ibcon#*after write, iclass 22, count 0 2006.224.08:02:02.51#ibcon#*before return 0, iclass 22, count 0 2006.224.08:02:02.51#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.224.08:02:02.51#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.224.08:02:02.51#ibcon#about to clear, iclass 22 cls_cnt 0 2006.224.08:02:02.51#ibcon#cleared, iclass 22 cls_cnt 0 2006.224.08:02:02.51$vc4f8/vabw=wide 2006.224.08:02:02.51#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.224.08:02:02.51#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.224.08:02:02.51#ibcon#ireg 8 cls_cnt 0 2006.224.08:02:02.51#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.224.08:02:02.51#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.224.08:02:02.51#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.224.08:02:02.51#ibcon#enter wrdev, iclass 24, count 0 2006.224.08:02:02.51#ibcon#first serial, iclass 24, count 0 2006.224.08:02:02.51#ibcon#enter sib2, iclass 24, count 0 2006.224.08:02:02.51#ibcon#flushed, iclass 24, count 0 2006.224.08:02:02.51#ibcon#about to write, iclass 24, count 0 2006.224.08:02:02.51#ibcon#wrote, iclass 24, count 0 2006.224.08:02:02.51#ibcon#about to read 3, iclass 24, count 0 2006.224.08:02:02.53#ibcon#read 3, iclass 24, count 0 2006.224.08:02:02.53#ibcon#about to read 4, iclass 24, count 0 2006.224.08:02:02.53#ibcon#read 4, iclass 24, count 0 2006.224.08:02:02.53#ibcon#about to read 5, iclass 24, count 0 2006.224.08:02:02.53#ibcon#read 5, iclass 24, count 0 2006.224.08:02:02.53#ibcon#about to read 6, iclass 24, count 0 2006.224.08:02:02.53#ibcon#read 6, iclass 24, count 0 2006.224.08:02:02.53#ibcon#end of sib2, iclass 24, count 0 2006.224.08:02:02.53#ibcon#*mode == 0, iclass 24, count 0 2006.224.08:02:02.53#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.224.08:02:02.53#ibcon#[25=BW32\r\n] 2006.224.08:02:02.53#ibcon#*before write, iclass 24, count 0 2006.224.08:02:02.53#ibcon#enter sib2, iclass 24, count 0 2006.224.08:02:02.53#ibcon#flushed, iclass 24, count 0 2006.224.08:02:02.53#ibcon#about to write, iclass 24, count 0 2006.224.08:02:02.53#ibcon#wrote, iclass 24, count 0 2006.224.08:02:02.53#ibcon#about to read 3, iclass 24, count 0 2006.224.08:02:02.56#ibcon#read 3, iclass 24, count 0 2006.224.08:02:02.56#ibcon#about to read 4, iclass 24, count 0 2006.224.08:02:02.56#ibcon#read 4, iclass 24, count 0 2006.224.08:02:02.56#ibcon#about to read 5, iclass 24, count 0 2006.224.08:02:02.56#ibcon#read 5, iclass 24, count 0 2006.224.08:02:02.56#ibcon#about to read 6, iclass 24, count 0 2006.224.08:02:02.56#ibcon#read 6, iclass 24, count 0 2006.224.08:02:02.56#ibcon#end of sib2, iclass 24, count 0 2006.224.08:02:02.56#ibcon#*after write, iclass 24, count 0 2006.224.08:02:02.56#ibcon#*before return 0, iclass 24, count 0 2006.224.08:02:02.56#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.224.08:02:02.56#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.224.08:02:02.56#ibcon#about to clear, iclass 24 cls_cnt 0 2006.224.08:02:02.56#ibcon#cleared, iclass 24 cls_cnt 0 2006.224.08:02:02.56$vc4f8/vbbw=wide 2006.224.08:02:02.56#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.224.08:02:02.56#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.224.08:02:02.56#ibcon#ireg 8 cls_cnt 0 2006.224.08:02:02.56#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.224.08:02:02.63#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.224.08:02:02.63#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.224.08:02:02.63#ibcon#enter wrdev, iclass 26, count 0 2006.224.08:02:02.63#ibcon#first serial, iclass 26, count 0 2006.224.08:02:02.63#ibcon#enter sib2, iclass 26, count 0 2006.224.08:02:02.63#ibcon#flushed, iclass 26, count 0 2006.224.08:02:02.63#ibcon#about to write, iclass 26, count 0 2006.224.08:02:02.63#ibcon#wrote, iclass 26, count 0 2006.224.08:02:02.63#ibcon#about to read 3, iclass 26, count 0 2006.224.08:02:02.65#ibcon#read 3, iclass 26, count 0 2006.224.08:02:02.65#ibcon#about to read 4, iclass 26, count 0 2006.224.08:02:02.65#ibcon#read 4, iclass 26, count 0 2006.224.08:02:02.65#ibcon#about to read 5, iclass 26, count 0 2006.224.08:02:02.65#ibcon#read 5, iclass 26, count 0 2006.224.08:02:02.65#ibcon#about to read 6, iclass 26, count 0 2006.224.08:02:02.65#ibcon#read 6, iclass 26, count 0 2006.224.08:02:02.65#ibcon#end of sib2, iclass 26, count 0 2006.224.08:02:02.65#ibcon#*mode == 0, iclass 26, count 0 2006.224.08:02:02.65#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.224.08:02:02.65#ibcon#[27=BW32\r\n] 2006.224.08:02:02.65#ibcon#*before write, iclass 26, count 0 2006.224.08:02:02.65#ibcon#enter sib2, iclass 26, count 0 2006.224.08:02:02.65#ibcon#flushed, iclass 26, count 0 2006.224.08:02:02.65#ibcon#about to write, iclass 26, count 0 2006.224.08:02:02.65#ibcon#wrote, iclass 26, count 0 2006.224.08:02:02.65#ibcon#about to read 3, iclass 26, count 0 2006.224.08:02:02.68#ibcon#read 3, iclass 26, count 0 2006.224.08:02:02.68#ibcon#about to read 4, iclass 26, count 0 2006.224.08:02:02.68#ibcon#read 4, iclass 26, count 0 2006.224.08:02:02.68#ibcon#about to read 5, iclass 26, count 0 2006.224.08:02:02.68#ibcon#read 5, iclass 26, count 0 2006.224.08:02:02.68#ibcon#about to read 6, iclass 26, count 0 2006.224.08:02:02.68#ibcon#read 6, iclass 26, count 0 2006.224.08:02:02.68#ibcon#end of sib2, iclass 26, count 0 2006.224.08:02:02.68#ibcon#*after write, iclass 26, count 0 2006.224.08:02:02.68#ibcon#*before return 0, iclass 26, count 0 2006.224.08:02:02.68#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.224.08:02:02.68#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.224.08:02:02.68#ibcon#about to clear, iclass 26 cls_cnt 0 2006.224.08:02:02.68#ibcon#cleared, iclass 26 cls_cnt 0 2006.224.08:02:02.68$4f8m12a/ifd4f 2006.224.08:02:02.68$ifd4f/lo= 2006.224.08:02:02.68$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.224.08:02:02.68$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.224.08:02:02.68$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.224.08:02:02.68$ifd4f/patch= 2006.224.08:02:02.68$ifd4f/patch=lo1,a1,a2,a3,a4 2006.224.08:02:02.68$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.224.08:02:02.68$ifd4f/patch=lo3,a5,a6,a7,a8 2006.224.08:02:02.68$4f8m12a/"form=m,16.000,1:2 2006.224.08:02:02.68$4f8m12a/"tpicd 2006.224.08:02:02.68$4f8m12a/echo=off 2006.224.08:02:02.68$4f8m12a/xlog=off 2006.224.08:02:02.68:!2006.224.08:02:30 2006.224.08:02:11.13#trakl#Source acquired 2006.224.08:02:12.13#flagr#flagr/antenna,acquired 2006.224.08:02:30.00:preob 2006.224.08:02:31.13/onsource/TRACKING 2006.224.08:02:31.13:!2006.224.08:02:40 2006.224.08:02:40.00:data_valid=on 2006.224.08:02:40.00:midob 2006.224.08:02:40.13/onsource/TRACKING 2006.224.08:02:40.13/wx/23.62,1004.7,100 2006.224.08:02:40.31/cable/+6.4338E-03 2006.224.08:02:41.40/va/01,08,usb,yes,45,48 2006.224.08:02:41.40/va/02,07,usb,yes,46,48 2006.224.08:02:41.40/va/03,06,usb,yes,49,49 2006.224.08:02:41.40/va/04,07,usb,yes,48,51 2006.224.08:02:41.40/va/05,07,usb,yes,56,59 2006.224.08:02:41.40/va/06,06,usb,yes,55,55 2006.224.08:02:41.40/va/07,06,usb,yes,56,56 2006.224.08:02:41.40/va/08,07,usb,yes,53,52 2006.224.08:02:41.63/valo/01,532.99,yes,locked 2006.224.08:02:41.63/valo/02,572.99,yes,locked 2006.224.08:02:41.63/valo/03,672.99,yes,locked 2006.224.08:02:41.63/valo/04,832.99,yes,locked 2006.224.08:02:41.63/valo/05,652.99,yes,locked 2006.224.08:02:41.63/valo/06,772.99,yes,locked 2006.224.08:02:41.63/valo/07,832.99,yes,locked 2006.224.08:02:41.63/valo/08,852.99,yes,locked 2006.224.08:02:42.72/vb/01,04,usb,yes,33,31 2006.224.08:02:42.72/vb/02,04,usb,yes,35,36 2006.224.08:02:42.72/vb/03,04,usb,yes,31,35 2006.224.08:02:42.72/vb/04,04,usb,yes,32,32 2006.224.08:02:42.72/vb/05,04,usb,yes,30,35 2006.224.08:02:42.72/vb/06,04,usb,yes,31,34 2006.224.08:02:42.72/vb/07,04,usb,yes,34,33 2006.224.08:02:42.72/vb/08,04,usb,yes,31,35 2006.224.08:02:42.95/vblo/01,632.99,yes,locked 2006.224.08:02:42.95/vblo/02,640.99,yes,locked 2006.224.08:02:42.95/vblo/03,656.99,yes,locked 2006.224.08:02:42.95/vblo/04,712.99,yes,locked 2006.224.08:02:42.95/vblo/05,744.99,yes,locked 2006.224.08:02:42.95/vblo/06,752.99,yes,locked 2006.224.08:02:42.95/vblo/07,734.99,yes,locked 2006.224.08:02:42.95/vblo/08,744.99,yes,locked 2006.224.08:02:43.10/vabw/8 2006.224.08:02:43.25/vbbw/8 2006.224.08:02:43.34/xfe/off,on,15.2 2006.224.08:02:43.72/ifatt/23,28,28,28 2006.224.08:02:44.07/fmout-gps/S +4.37E-07 2006.224.08:02:44.11:!2006.224.08:03:40 2006.224.08:03:40.01:data_valid=off 2006.224.08:03:40.01:postob 2006.224.08:03:40.19/cable/+6.4368E-03 2006.224.08:03:40.19/wx/23.63,1004.7,100 2006.224.08:03:41.07/fmout-gps/S +4.40E-07 2006.224.08:03:41.07:scan_name=224-0804,k06224,60 2006.224.08:03:41.08:source=1044+719,104827.62,714335.9,2000.0,ccw 2006.224.08:03:41.13#flagr#flagr/antenna,new-source 2006.224.08:03:42.13:checkk5 2006.224.08:03:42.50/chk_autoobs//k5ts1/ autoobs is running! 2006.224.08:03:42.87/chk_autoobs//k5ts2/ autoobs is running! 2006.224.08:03:43.25/chk_autoobs//k5ts3/ autoobs is running! 2006.224.08:03:43.62/chk_autoobs//k5ts4/ autoobs is running! 2006.224.08:03:43.98/chk_obsdata//k5ts1/T2240802??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.08:03:44.35/chk_obsdata//k5ts2/T2240802??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.08:03:44.72/chk_obsdata//k5ts3/T2240802??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.08:03:45.08/chk_obsdata//k5ts4/T2240802??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.08:03:45.77/k5log//k5ts1_log_newline 2006.224.08:03:46.45/k5log//k5ts2_log_newline 2006.224.08:03:47.14/k5log//k5ts3_log_newline 2006.224.08:03:47.82/k5log//k5ts4_log_newline 2006.224.08:03:47.84/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.224.08:03:47.84:4f8m12a=2 2006.224.08:03:47.84$4f8m12a/echo=on 2006.224.08:03:47.84$4f8m12a/pcalon 2006.224.08:03:47.84$pcalon/"no phase cal control is implemented here 2006.224.08:03:47.84$4f8m12a/"tpicd=stop 2006.224.08:03:47.84$4f8m12a/vc4f8 2006.224.08:03:47.84$vc4f8/valo=1,532.99 2006.224.08:03:47.85#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.224.08:03:47.85#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.224.08:03:47.85#ibcon#ireg 17 cls_cnt 0 2006.224.08:03:47.85#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.224.08:03:47.85#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.224.08:03:47.85#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.224.08:03:47.85#ibcon#enter wrdev, iclass 33, count 0 2006.224.08:03:47.85#ibcon#first serial, iclass 33, count 0 2006.224.08:03:47.85#ibcon#enter sib2, iclass 33, count 0 2006.224.08:03:47.85#ibcon#flushed, iclass 33, count 0 2006.224.08:03:47.85#ibcon#about to write, iclass 33, count 0 2006.224.08:03:47.85#ibcon#wrote, iclass 33, count 0 2006.224.08:03:47.85#ibcon#about to read 3, iclass 33, count 0 2006.224.08:03:47.89#ibcon#read 3, iclass 33, count 0 2006.224.08:03:47.89#ibcon#about to read 4, iclass 33, count 0 2006.224.08:03:47.89#ibcon#read 4, iclass 33, count 0 2006.224.08:03:47.89#ibcon#about to read 5, iclass 33, count 0 2006.224.08:03:47.89#ibcon#read 5, iclass 33, count 0 2006.224.08:03:47.89#ibcon#about to read 6, iclass 33, count 0 2006.224.08:03:47.89#ibcon#read 6, iclass 33, count 0 2006.224.08:03:47.89#ibcon#end of sib2, iclass 33, count 0 2006.224.08:03:47.89#ibcon#*mode == 0, iclass 33, count 0 2006.224.08:03:47.89#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.224.08:03:47.89#ibcon#[26=FRQ=01,532.99\r\n] 2006.224.08:03:47.89#ibcon#*before write, iclass 33, count 0 2006.224.08:03:47.89#ibcon#enter sib2, iclass 33, count 0 2006.224.08:03:47.89#ibcon#flushed, iclass 33, count 0 2006.224.08:03:47.89#ibcon#about to write, iclass 33, count 0 2006.224.08:03:47.89#ibcon#wrote, iclass 33, count 0 2006.224.08:03:47.89#ibcon#about to read 3, iclass 33, count 0 2006.224.08:03:47.94#ibcon#read 3, iclass 33, count 0 2006.224.08:03:47.94#ibcon#about to read 4, iclass 33, count 0 2006.224.08:03:47.94#ibcon#read 4, iclass 33, count 0 2006.224.08:03:47.94#ibcon#about to read 5, iclass 33, count 0 2006.224.08:03:47.94#ibcon#read 5, iclass 33, count 0 2006.224.08:03:47.94#ibcon#about to read 6, iclass 33, count 0 2006.224.08:03:47.94#ibcon#read 6, iclass 33, count 0 2006.224.08:03:47.94#ibcon#end of sib2, iclass 33, count 0 2006.224.08:03:47.94#ibcon#*after write, iclass 33, count 0 2006.224.08:03:47.94#ibcon#*before return 0, iclass 33, count 0 2006.224.08:03:47.94#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.224.08:03:47.94#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.224.08:03:47.94#ibcon#about to clear, iclass 33 cls_cnt 0 2006.224.08:03:47.94#ibcon#cleared, iclass 33 cls_cnt 0 2006.224.08:03:47.94$vc4f8/va=1,8 2006.224.08:03:47.94#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.224.08:03:47.94#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.224.08:03:47.94#ibcon#ireg 11 cls_cnt 2 2006.224.08:03:47.94#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.224.08:03:47.94#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.224.08:03:47.94#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.224.08:03:47.94#ibcon#enter wrdev, iclass 35, count 2 2006.224.08:03:47.94#ibcon#first serial, iclass 35, count 2 2006.224.08:03:47.94#ibcon#enter sib2, iclass 35, count 2 2006.224.08:03:47.94#ibcon#flushed, iclass 35, count 2 2006.224.08:03:47.94#ibcon#about to write, iclass 35, count 2 2006.224.08:03:47.94#ibcon#wrote, iclass 35, count 2 2006.224.08:03:47.94#ibcon#about to read 3, iclass 35, count 2 2006.224.08:03:47.97#ibcon#read 3, iclass 35, count 2 2006.224.08:03:47.97#ibcon#about to read 4, iclass 35, count 2 2006.224.08:03:47.97#ibcon#read 4, iclass 35, count 2 2006.224.08:03:47.97#ibcon#about to read 5, iclass 35, count 2 2006.224.08:03:47.97#ibcon#read 5, iclass 35, count 2 2006.224.08:03:47.97#ibcon#about to read 6, iclass 35, count 2 2006.224.08:03:47.97#ibcon#read 6, iclass 35, count 2 2006.224.08:03:47.97#ibcon#end of sib2, iclass 35, count 2 2006.224.08:03:47.97#ibcon#*mode == 0, iclass 35, count 2 2006.224.08:03:47.97#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.224.08:03:47.97#ibcon#[25=AT01-08\r\n] 2006.224.08:03:47.97#ibcon#*before write, iclass 35, count 2 2006.224.08:03:47.97#ibcon#enter sib2, iclass 35, count 2 2006.224.08:03:47.97#ibcon#flushed, iclass 35, count 2 2006.224.08:03:47.97#ibcon#about to write, iclass 35, count 2 2006.224.08:03:47.97#ibcon#wrote, iclass 35, count 2 2006.224.08:03:47.97#ibcon#about to read 3, iclass 35, count 2 2006.224.08:03:48.00#ibcon#read 3, iclass 35, count 2 2006.224.08:03:48.00#ibcon#about to read 4, iclass 35, count 2 2006.224.08:03:48.00#ibcon#read 4, iclass 35, count 2 2006.224.08:03:48.00#ibcon#about to read 5, iclass 35, count 2 2006.224.08:03:48.00#ibcon#read 5, iclass 35, count 2 2006.224.08:03:48.00#ibcon#about to read 6, iclass 35, count 2 2006.224.08:03:48.00#ibcon#read 6, iclass 35, count 2 2006.224.08:03:48.00#ibcon#end of sib2, iclass 35, count 2 2006.224.08:03:48.00#ibcon#*after write, iclass 35, count 2 2006.224.08:03:48.00#ibcon#*before return 0, iclass 35, count 2 2006.224.08:03:48.00#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.224.08:03:48.00#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.224.08:03:48.00#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.224.08:03:48.00#ibcon#ireg 7 cls_cnt 0 2006.224.08:03:48.00#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.224.08:03:48.12#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.224.08:03:48.12#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.224.08:03:48.12#ibcon#enter wrdev, iclass 35, count 0 2006.224.08:03:48.12#ibcon#first serial, iclass 35, count 0 2006.224.08:03:48.12#ibcon#enter sib2, iclass 35, count 0 2006.224.08:03:48.12#ibcon#flushed, iclass 35, count 0 2006.224.08:03:48.12#ibcon#about to write, iclass 35, count 0 2006.224.08:03:48.12#ibcon#wrote, iclass 35, count 0 2006.224.08:03:48.12#ibcon#about to read 3, iclass 35, count 0 2006.224.08:03:48.14#ibcon#read 3, iclass 35, count 0 2006.224.08:03:48.14#ibcon#about to read 4, iclass 35, count 0 2006.224.08:03:48.14#ibcon#read 4, iclass 35, count 0 2006.224.08:03:48.14#ibcon#about to read 5, iclass 35, count 0 2006.224.08:03:48.14#ibcon#read 5, iclass 35, count 0 2006.224.08:03:48.14#ibcon#about to read 6, iclass 35, count 0 2006.224.08:03:48.14#ibcon#read 6, iclass 35, count 0 2006.224.08:03:48.14#ibcon#end of sib2, iclass 35, count 0 2006.224.08:03:48.14#ibcon#*mode == 0, iclass 35, count 0 2006.224.08:03:48.14#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.224.08:03:48.14#ibcon#[25=USB\r\n] 2006.224.08:03:48.14#ibcon#*before write, iclass 35, count 0 2006.224.08:03:48.14#ibcon#enter sib2, iclass 35, count 0 2006.224.08:03:48.14#ibcon#flushed, iclass 35, count 0 2006.224.08:03:48.14#ibcon#about to write, iclass 35, count 0 2006.224.08:03:48.14#ibcon#wrote, iclass 35, count 0 2006.224.08:03:48.14#ibcon#about to read 3, iclass 35, count 0 2006.224.08:03:48.17#ibcon#read 3, iclass 35, count 0 2006.224.08:03:48.17#ibcon#about to read 4, iclass 35, count 0 2006.224.08:03:48.17#ibcon#read 4, iclass 35, count 0 2006.224.08:03:48.17#ibcon#about to read 5, iclass 35, count 0 2006.224.08:03:48.17#ibcon#read 5, iclass 35, count 0 2006.224.08:03:48.17#ibcon#about to read 6, iclass 35, count 0 2006.224.08:03:48.17#ibcon#read 6, iclass 35, count 0 2006.224.08:03:48.17#ibcon#end of sib2, iclass 35, count 0 2006.224.08:03:48.17#ibcon#*after write, iclass 35, count 0 2006.224.08:03:48.17#ibcon#*before return 0, iclass 35, count 0 2006.224.08:03:48.17#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.224.08:03:48.17#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.224.08:03:48.17#ibcon#about to clear, iclass 35 cls_cnt 0 2006.224.08:03:48.17#ibcon#cleared, iclass 35 cls_cnt 0 2006.224.08:03:48.17$vc4f8/valo=2,572.99 2006.224.08:03:48.17#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.224.08:03:48.17#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.224.08:03:48.17#ibcon#ireg 17 cls_cnt 0 2006.224.08:03:48.17#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.224.08:03:48.17#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.224.08:03:48.17#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.224.08:03:48.17#ibcon#enter wrdev, iclass 37, count 0 2006.224.08:03:48.17#ibcon#first serial, iclass 37, count 0 2006.224.08:03:48.17#ibcon#enter sib2, iclass 37, count 0 2006.224.08:03:48.17#ibcon#flushed, iclass 37, count 0 2006.224.08:03:48.17#ibcon#about to write, iclass 37, count 0 2006.224.08:03:48.17#ibcon#wrote, iclass 37, count 0 2006.224.08:03:48.17#ibcon#about to read 3, iclass 37, count 0 2006.224.08:03:48.20#ibcon#read 3, iclass 37, count 0 2006.224.08:03:48.20#ibcon#about to read 4, iclass 37, count 0 2006.224.08:03:48.20#ibcon#read 4, iclass 37, count 0 2006.224.08:03:48.20#ibcon#about to read 5, iclass 37, count 0 2006.224.08:03:48.20#ibcon#read 5, iclass 37, count 0 2006.224.08:03:48.20#ibcon#about to read 6, iclass 37, count 0 2006.224.08:03:48.20#ibcon#read 6, iclass 37, count 0 2006.224.08:03:48.20#ibcon#end of sib2, iclass 37, count 0 2006.224.08:03:48.20#ibcon#*mode == 0, iclass 37, count 0 2006.224.08:03:48.20#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.224.08:03:48.20#ibcon#[26=FRQ=02,572.99\r\n] 2006.224.08:03:48.20#ibcon#*before write, iclass 37, count 0 2006.224.08:03:48.20#ibcon#enter sib2, iclass 37, count 0 2006.224.08:03:48.20#ibcon#flushed, iclass 37, count 0 2006.224.08:03:48.20#ibcon#about to write, iclass 37, count 0 2006.224.08:03:48.20#ibcon#wrote, iclass 37, count 0 2006.224.08:03:48.20#ibcon#about to read 3, iclass 37, count 0 2006.224.08:03:48.24#ibcon#read 3, iclass 37, count 0 2006.224.08:03:48.24#ibcon#about to read 4, iclass 37, count 0 2006.224.08:03:48.24#ibcon#read 4, iclass 37, count 0 2006.224.08:03:48.24#ibcon#about to read 5, iclass 37, count 0 2006.224.08:03:48.24#ibcon#read 5, iclass 37, count 0 2006.224.08:03:48.24#ibcon#about to read 6, iclass 37, count 0 2006.224.08:03:48.24#ibcon#read 6, iclass 37, count 0 2006.224.08:03:48.24#ibcon#end of sib2, iclass 37, count 0 2006.224.08:03:48.24#ibcon#*after write, iclass 37, count 0 2006.224.08:03:48.24#ibcon#*before return 0, iclass 37, count 0 2006.224.08:03:48.24#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.224.08:03:48.24#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.224.08:03:48.24#ibcon#about to clear, iclass 37 cls_cnt 0 2006.224.08:03:48.24#ibcon#cleared, iclass 37 cls_cnt 0 2006.224.08:03:48.24$vc4f8/va=2,7 2006.224.08:03:48.24#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.224.08:03:48.24#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.224.08:03:48.24#ibcon#ireg 11 cls_cnt 2 2006.224.08:03:48.24#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.224.08:03:48.29#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.224.08:03:48.29#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.224.08:03:48.29#ibcon#enter wrdev, iclass 39, count 2 2006.224.08:03:48.29#ibcon#first serial, iclass 39, count 2 2006.224.08:03:48.29#ibcon#enter sib2, iclass 39, count 2 2006.224.08:03:48.29#ibcon#flushed, iclass 39, count 2 2006.224.08:03:48.29#ibcon#about to write, iclass 39, count 2 2006.224.08:03:48.29#ibcon#wrote, iclass 39, count 2 2006.224.08:03:48.29#ibcon#about to read 3, iclass 39, count 2 2006.224.08:03:48.31#ibcon#read 3, iclass 39, count 2 2006.224.08:03:48.31#ibcon#about to read 4, iclass 39, count 2 2006.224.08:03:48.31#ibcon#read 4, iclass 39, count 2 2006.224.08:03:48.31#ibcon#about to read 5, iclass 39, count 2 2006.224.08:03:48.31#ibcon#read 5, iclass 39, count 2 2006.224.08:03:48.31#ibcon#about to read 6, iclass 39, count 2 2006.224.08:03:48.31#ibcon#read 6, iclass 39, count 2 2006.224.08:03:48.31#ibcon#end of sib2, iclass 39, count 2 2006.224.08:03:48.31#ibcon#*mode == 0, iclass 39, count 2 2006.224.08:03:48.31#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.224.08:03:48.31#ibcon#[25=AT02-07\r\n] 2006.224.08:03:48.31#ibcon#*before write, iclass 39, count 2 2006.224.08:03:48.31#ibcon#enter sib2, iclass 39, count 2 2006.224.08:03:48.31#ibcon#flushed, iclass 39, count 2 2006.224.08:03:48.31#ibcon#about to write, iclass 39, count 2 2006.224.08:03:48.31#ibcon#wrote, iclass 39, count 2 2006.224.08:03:48.31#ibcon#about to read 3, iclass 39, count 2 2006.224.08:03:48.32#abcon#<5=/09 1.3 2.6 23.631001004.8\r\n> 2006.224.08:03:48.34#abcon#{5=INTERFACE CLEAR} 2006.224.08:03:48.34#ibcon#read 3, iclass 39, count 2 2006.224.08:03:48.34#ibcon#about to read 4, iclass 39, count 2 2006.224.08:03:48.34#ibcon#read 4, iclass 39, count 2 2006.224.08:03:48.34#ibcon#about to read 5, iclass 39, count 2 2006.224.08:03:48.34#ibcon#read 5, iclass 39, count 2 2006.224.08:03:48.34#ibcon#about to read 6, iclass 39, count 2 2006.224.08:03:48.34#ibcon#read 6, iclass 39, count 2 2006.224.08:03:48.34#ibcon#end of sib2, iclass 39, count 2 2006.224.08:03:48.34#ibcon#*after write, iclass 39, count 2 2006.224.08:03:48.34#ibcon#*before return 0, iclass 39, count 2 2006.224.08:03:48.34#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.224.08:03:48.34#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.224.08:03:48.34#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.224.08:03:48.34#ibcon#ireg 7 cls_cnt 0 2006.224.08:03:48.34#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.224.08:03:48.41#abcon#[5=S1D000X0/0*\r\n] 2006.224.08:03:48.46#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.224.08:03:48.46#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.224.08:03:48.46#ibcon#enter wrdev, iclass 39, count 0 2006.224.08:03:48.46#ibcon#first serial, iclass 39, count 0 2006.224.08:03:48.46#ibcon#enter sib2, iclass 39, count 0 2006.224.08:03:48.46#ibcon#flushed, iclass 39, count 0 2006.224.08:03:48.46#ibcon#about to write, iclass 39, count 0 2006.224.08:03:48.46#ibcon#wrote, iclass 39, count 0 2006.224.08:03:48.46#ibcon#about to read 3, iclass 39, count 0 2006.224.08:03:48.49#ibcon#read 3, iclass 39, count 0 2006.224.08:03:48.49#ibcon#about to read 4, iclass 39, count 0 2006.224.08:03:48.49#ibcon#read 4, iclass 39, count 0 2006.224.08:03:48.49#ibcon#about to read 5, iclass 39, count 0 2006.224.08:03:48.49#ibcon#read 5, iclass 39, count 0 2006.224.08:03:48.49#ibcon#about to read 6, iclass 39, count 0 2006.224.08:03:48.49#ibcon#read 6, iclass 39, count 0 2006.224.08:03:48.49#ibcon#end of sib2, iclass 39, count 0 2006.224.08:03:48.49#ibcon#*mode == 0, iclass 39, count 0 2006.224.08:03:48.49#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.224.08:03:48.49#ibcon#[25=USB\r\n] 2006.224.08:03:48.49#ibcon#*before write, iclass 39, count 0 2006.224.08:03:48.49#ibcon#enter sib2, iclass 39, count 0 2006.224.08:03:48.49#ibcon#flushed, iclass 39, count 0 2006.224.08:03:48.49#ibcon#about to write, iclass 39, count 0 2006.224.08:03:48.49#ibcon#wrote, iclass 39, count 0 2006.224.08:03:48.49#ibcon#about to read 3, iclass 39, count 0 2006.224.08:03:48.52#ibcon#read 3, iclass 39, count 0 2006.224.08:03:48.52#ibcon#about to read 4, iclass 39, count 0 2006.224.08:03:48.52#ibcon#read 4, iclass 39, count 0 2006.224.08:03:48.52#ibcon#about to read 5, iclass 39, count 0 2006.224.08:03:48.52#ibcon#read 5, iclass 39, count 0 2006.224.08:03:48.52#ibcon#about to read 6, iclass 39, count 0 2006.224.08:03:48.52#ibcon#read 6, iclass 39, count 0 2006.224.08:03:48.52#ibcon#end of sib2, iclass 39, count 0 2006.224.08:03:48.52#ibcon#*after write, iclass 39, count 0 2006.224.08:03:48.52#ibcon#*before return 0, iclass 39, count 0 2006.224.08:03:48.52#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.224.08:03:48.52#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.224.08:03:48.52#ibcon#about to clear, iclass 39 cls_cnt 0 2006.224.08:03:48.52#ibcon#cleared, iclass 39 cls_cnt 0 2006.224.08:03:48.52$vc4f8/valo=3,672.99 2006.224.08:03:48.52#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.224.08:03:48.52#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.224.08:03:48.52#ibcon#ireg 17 cls_cnt 0 2006.224.08:03:48.52#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.224.08:03:48.52#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.224.08:03:48.52#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.224.08:03:48.52#ibcon#enter wrdev, iclass 7, count 0 2006.224.08:03:48.52#ibcon#first serial, iclass 7, count 0 2006.224.08:03:48.52#ibcon#enter sib2, iclass 7, count 0 2006.224.08:03:48.52#ibcon#flushed, iclass 7, count 0 2006.224.08:03:48.52#ibcon#about to write, iclass 7, count 0 2006.224.08:03:48.52#ibcon#wrote, iclass 7, count 0 2006.224.08:03:48.52#ibcon#about to read 3, iclass 7, count 0 2006.224.08:03:48.54#ibcon#read 3, iclass 7, count 0 2006.224.08:03:48.54#ibcon#about to read 4, iclass 7, count 0 2006.224.08:03:48.54#ibcon#read 4, iclass 7, count 0 2006.224.08:03:48.54#ibcon#about to read 5, iclass 7, count 0 2006.224.08:03:48.54#ibcon#read 5, iclass 7, count 0 2006.224.08:03:48.54#ibcon#about to read 6, iclass 7, count 0 2006.224.08:03:48.54#ibcon#read 6, iclass 7, count 0 2006.224.08:03:48.54#ibcon#end of sib2, iclass 7, count 0 2006.224.08:03:48.54#ibcon#*mode == 0, iclass 7, count 0 2006.224.08:03:48.54#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.224.08:03:48.54#ibcon#[26=FRQ=03,672.99\r\n] 2006.224.08:03:48.54#ibcon#*before write, iclass 7, count 0 2006.224.08:03:48.54#ibcon#enter sib2, iclass 7, count 0 2006.224.08:03:48.54#ibcon#flushed, iclass 7, count 0 2006.224.08:03:48.54#ibcon#about to write, iclass 7, count 0 2006.224.08:03:48.54#ibcon#wrote, iclass 7, count 0 2006.224.08:03:48.54#ibcon#about to read 3, iclass 7, count 0 2006.224.08:03:48.58#ibcon#read 3, iclass 7, count 0 2006.224.08:03:48.58#ibcon#about to read 4, iclass 7, count 0 2006.224.08:03:48.58#ibcon#read 4, iclass 7, count 0 2006.224.08:03:48.58#ibcon#about to read 5, iclass 7, count 0 2006.224.08:03:48.58#ibcon#read 5, iclass 7, count 0 2006.224.08:03:48.58#ibcon#about to read 6, iclass 7, count 0 2006.224.08:03:48.58#ibcon#read 6, iclass 7, count 0 2006.224.08:03:48.58#ibcon#end of sib2, iclass 7, count 0 2006.224.08:03:48.58#ibcon#*after write, iclass 7, count 0 2006.224.08:03:48.58#ibcon#*before return 0, iclass 7, count 0 2006.224.08:03:48.58#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.224.08:03:48.58#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.224.08:03:48.58#ibcon#about to clear, iclass 7 cls_cnt 0 2006.224.08:03:48.58#ibcon#cleared, iclass 7 cls_cnt 0 2006.224.08:03:48.58$vc4f8/va=3,6 2006.224.08:03:48.58#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.224.08:03:48.58#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.224.08:03:48.58#ibcon#ireg 11 cls_cnt 2 2006.224.08:03:48.58#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.224.08:03:48.64#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.224.08:03:48.64#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.224.08:03:48.64#ibcon#enter wrdev, iclass 11, count 2 2006.224.08:03:48.64#ibcon#first serial, iclass 11, count 2 2006.224.08:03:48.64#ibcon#enter sib2, iclass 11, count 2 2006.224.08:03:48.64#ibcon#flushed, iclass 11, count 2 2006.224.08:03:48.64#ibcon#about to write, iclass 11, count 2 2006.224.08:03:48.64#ibcon#wrote, iclass 11, count 2 2006.224.08:03:48.64#ibcon#about to read 3, iclass 11, count 2 2006.224.08:03:48.66#ibcon#read 3, iclass 11, count 2 2006.224.08:03:48.66#ibcon#about to read 4, iclass 11, count 2 2006.224.08:03:48.66#ibcon#read 4, iclass 11, count 2 2006.224.08:03:48.66#ibcon#about to read 5, iclass 11, count 2 2006.224.08:03:48.66#ibcon#read 5, iclass 11, count 2 2006.224.08:03:48.66#ibcon#about to read 6, iclass 11, count 2 2006.224.08:03:48.66#ibcon#read 6, iclass 11, count 2 2006.224.08:03:48.66#ibcon#end of sib2, iclass 11, count 2 2006.224.08:03:48.66#ibcon#*mode == 0, iclass 11, count 2 2006.224.08:03:48.66#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.224.08:03:48.66#ibcon#[25=AT03-06\r\n] 2006.224.08:03:48.66#ibcon#*before write, iclass 11, count 2 2006.224.08:03:48.66#ibcon#enter sib2, iclass 11, count 2 2006.224.08:03:48.66#ibcon#flushed, iclass 11, count 2 2006.224.08:03:48.66#ibcon#about to write, iclass 11, count 2 2006.224.08:03:48.66#ibcon#wrote, iclass 11, count 2 2006.224.08:03:48.66#ibcon#about to read 3, iclass 11, count 2 2006.224.08:03:48.70#ibcon#read 3, iclass 11, count 2 2006.224.08:03:48.70#ibcon#about to read 4, iclass 11, count 2 2006.224.08:03:48.70#ibcon#read 4, iclass 11, count 2 2006.224.08:03:48.70#ibcon#about to read 5, iclass 11, count 2 2006.224.08:03:48.70#ibcon#read 5, iclass 11, count 2 2006.224.08:03:48.70#ibcon#about to read 6, iclass 11, count 2 2006.224.08:03:48.70#ibcon#read 6, iclass 11, count 2 2006.224.08:03:48.70#ibcon#end of sib2, iclass 11, count 2 2006.224.08:03:48.70#ibcon#*after write, iclass 11, count 2 2006.224.08:03:48.70#ibcon#*before return 0, iclass 11, count 2 2006.224.08:03:48.70#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.224.08:03:48.70#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.224.08:03:48.70#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.224.08:03:48.70#ibcon#ireg 7 cls_cnt 0 2006.224.08:03:48.70#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.224.08:03:48.82#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.224.08:03:48.82#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.224.08:03:48.82#ibcon#enter wrdev, iclass 11, count 0 2006.224.08:03:48.82#ibcon#first serial, iclass 11, count 0 2006.224.08:03:48.82#ibcon#enter sib2, iclass 11, count 0 2006.224.08:03:48.82#ibcon#flushed, iclass 11, count 0 2006.224.08:03:48.82#ibcon#about to write, iclass 11, count 0 2006.224.08:03:48.82#ibcon#wrote, iclass 11, count 0 2006.224.08:03:48.82#ibcon#about to read 3, iclass 11, count 0 2006.224.08:03:48.84#ibcon#read 3, iclass 11, count 0 2006.224.08:03:48.84#ibcon#about to read 4, iclass 11, count 0 2006.224.08:03:48.84#ibcon#read 4, iclass 11, count 0 2006.224.08:03:48.84#ibcon#about to read 5, iclass 11, count 0 2006.224.08:03:48.84#ibcon#read 5, iclass 11, count 0 2006.224.08:03:48.84#ibcon#about to read 6, iclass 11, count 0 2006.224.08:03:48.84#ibcon#read 6, iclass 11, count 0 2006.224.08:03:48.84#ibcon#end of sib2, iclass 11, count 0 2006.224.08:03:48.84#ibcon#*mode == 0, iclass 11, count 0 2006.224.08:03:48.84#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.224.08:03:48.84#ibcon#[25=USB\r\n] 2006.224.08:03:48.84#ibcon#*before write, iclass 11, count 0 2006.224.08:03:48.84#ibcon#enter sib2, iclass 11, count 0 2006.224.08:03:48.84#ibcon#flushed, iclass 11, count 0 2006.224.08:03:48.84#ibcon#about to write, iclass 11, count 0 2006.224.08:03:48.84#ibcon#wrote, iclass 11, count 0 2006.224.08:03:48.84#ibcon#about to read 3, iclass 11, count 0 2006.224.08:03:48.87#ibcon#read 3, iclass 11, count 0 2006.224.08:03:48.87#ibcon#about to read 4, iclass 11, count 0 2006.224.08:03:48.87#ibcon#read 4, iclass 11, count 0 2006.224.08:03:48.87#ibcon#about to read 5, iclass 11, count 0 2006.224.08:03:48.87#ibcon#read 5, iclass 11, count 0 2006.224.08:03:48.87#ibcon#about to read 6, iclass 11, count 0 2006.224.08:03:48.87#ibcon#read 6, iclass 11, count 0 2006.224.08:03:48.87#ibcon#end of sib2, iclass 11, count 0 2006.224.08:03:48.87#ibcon#*after write, iclass 11, count 0 2006.224.08:03:48.87#ibcon#*before return 0, iclass 11, count 0 2006.224.08:03:48.87#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.224.08:03:48.87#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.224.08:03:48.87#ibcon#about to clear, iclass 11 cls_cnt 0 2006.224.08:03:48.87#ibcon#cleared, iclass 11 cls_cnt 0 2006.224.08:03:48.87$vc4f8/valo=4,832.99 2006.224.08:03:48.87#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.224.08:03:48.87#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.224.08:03:48.87#ibcon#ireg 17 cls_cnt 0 2006.224.08:03:48.87#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.224.08:03:48.87#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.224.08:03:48.87#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.224.08:03:48.87#ibcon#enter wrdev, iclass 13, count 0 2006.224.08:03:48.87#ibcon#first serial, iclass 13, count 0 2006.224.08:03:48.87#ibcon#enter sib2, iclass 13, count 0 2006.224.08:03:48.87#ibcon#flushed, iclass 13, count 0 2006.224.08:03:48.87#ibcon#about to write, iclass 13, count 0 2006.224.08:03:48.87#ibcon#wrote, iclass 13, count 0 2006.224.08:03:48.87#ibcon#about to read 3, iclass 13, count 0 2006.224.08:03:48.89#ibcon#read 3, iclass 13, count 0 2006.224.08:03:48.89#ibcon#about to read 4, iclass 13, count 0 2006.224.08:03:48.89#ibcon#read 4, iclass 13, count 0 2006.224.08:03:48.89#ibcon#about to read 5, iclass 13, count 0 2006.224.08:03:48.89#ibcon#read 5, iclass 13, count 0 2006.224.08:03:48.89#ibcon#about to read 6, iclass 13, count 0 2006.224.08:03:48.89#ibcon#read 6, iclass 13, count 0 2006.224.08:03:48.89#ibcon#end of sib2, iclass 13, count 0 2006.224.08:03:48.89#ibcon#*mode == 0, iclass 13, count 0 2006.224.08:03:48.89#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.224.08:03:48.89#ibcon#[26=FRQ=04,832.99\r\n] 2006.224.08:03:48.89#ibcon#*before write, iclass 13, count 0 2006.224.08:03:48.89#ibcon#enter sib2, iclass 13, count 0 2006.224.08:03:48.89#ibcon#flushed, iclass 13, count 0 2006.224.08:03:48.89#ibcon#about to write, iclass 13, count 0 2006.224.08:03:48.89#ibcon#wrote, iclass 13, count 0 2006.224.08:03:48.89#ibcon#about to read 3, iclass 13, count 0 2006.224.08:03:48.93#ibcon#read 3, iclass 13, count 0 2006.224.08:03:48.93#ibcon#about to read 4, iclass 13, count 0 2006.224.08:03:48.93#ibcon#read 4, iclass 13, count 0 2006.224.08:03:48.93#ibcon#about to read 5, iclass 13, count 0 2006.224.08:03:48.93#ibcon#read 5, iclass 13, count 0 2006.224.08:03:48.93#ibcon#about to read 6, iclass 13, count 0 2006.224.08:03:48.93#ibcon#read 6, iclass 13, count 0 2006.224.08:03:48.93#ibcon#end of sib2, iclass 13, count 0 2006.224.08:03:48.93#ibcon#*after write, iclass 13, count 0 2006.224.08:03:48.93#ibcon#*before return 0, iclass 13, count 0 2006.224.08:03:48.93#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.224.08:03:48.93#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.224.08:03:48.93#ibcon#about to clear, iclass 13 cls_cnt 0 2006.224.08:03:48.93#ibcon#cleared, iclass 13 cls_cnt 0 2006.224.08:03:48.93$vc4f8/va=4,7 2006.224.08:03:48.93#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.224.08:03:48.93#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.224.08:03:48.93#ibcon#ireg 11 cls_cnt 2 2006.224.08:03:48.93#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.224.08:03:48.99#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.224.08:03:48.99#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.224.08:03:48.99#ibcon#enter wrdev, iclass 15, count 2 2006.224.08:03:48.99#ibcon#first serial, iclass 15, count 2 2006.224.08:03:48.99#ibcon#enter sib2, iclass 15, count 2 2006.224.08:03:48.99#ibcon#flushed, iclass 15, count 2 2006.224.08:03:48.99#ibcon#about to write, iclass 15, count 2 2006.224.08:03:48.99#ibcon#wrote, iclass 15, count 2 2006.224.08:03:48.99#ibcon#about to read 3, iclass 15, count 2 2006.224.08:03:49.01#ibcon#read 3, iclass 15, count 2 2006.224.08:03:49.01#ibcon#about to read 4, iclass 15, count 2 2006.224.08:03:49.01#ibcon#read 4, iclass 15, count 2 2006.224.08:03:49.01#ibcon#about to read 5, iclass 15, count 2 2006.224.08:03:49.01#ibcon#read 5, iclass 15, count 2 2006.224.08:03:49.01#ibcon#about to read 6, iclass 15, count 2 2006.224.08:03:49.01#ibcon#read 6, iclass 15, count 2 2006.224.08:03:49.01#ibcon#end of sib2, iclass 15, count 2 2006.224.08:03:49.01#ibcon#*mode == 0, iclass 15, count 2 2006.224.08:03:49.01#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.224.08:03:49.01#ibcon#[25=AT04-07\r\n] 2006.224.08:03:49.01#ibcon#*before write, iclass 15, count 2 2006.224.08:03:49.01#ibcon#enter sib2, iclass 15, count 2 2006.224.08:03:49.01#ibcon#flushed, iclass 15, count 2 2006.224.08:03:49.01#ibcon#about to write, iclass 15, count 2 2006.224.08:03:49.01#ibcon#wrote, iclass 15, count 2 2006.224.08:03:49.01#ibcon#about to read 3, iclass 15, count 2 2006.224.08:03:49.04#ibcon#read 3, iclass 15, count 2 2006.224.08:03:49.04#ibcon#about to read 4, iclass 15, count 2 2006.224.08:03:49.04#ibcon#read 4, iclass 15, count 2 2006.224.08:03:49.04#ibcon#about to read 5, iclass 15, count 2 2006.224.08:03:49.04#ibcon#read 5, iclass 15, count 2 2006.224.08:03:49.04#ibcon#about to read 6, iclass 15, count 2 2006.224.08:03:49.04#ibcon#read 6, iclass 15, count 2 2006.224.08:03:49.04#ibcon#end of sib2, iclass 15, count 2 2006.224.08:03:49.04#ibcon#*after write, iclass 15, count 2 2006.224.08:03:49.04#ibcon#*before return 0, iclass 15, count 2 2006.224.08:03:49.04#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.224.08:03:49.04#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.224.08:03:49.04#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.224.08:03:49.04#ibcon#ireg 7 cls_cnt 0 2006.224.08:03:49.04#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.224.08:03:49.16#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.224.08:03:49.16#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.224.08:03:49.16#ibcon#enter wrdev, iclass 15, count 0 2006.224.08:03:49.16#ibcon#first serial, iclass 15, count 0 2006.224.08:03:49.16#ibcon#enter sib2, iclass 15, count 0 2006.224.08:03:49.16#ibcon#flushed, iclass 15, count 0 2006.224.08:03:49.16#ibcon#about to write, iclass 15, count 0 2006.224.08:03:49.16#ibcon#wrote, iclass 15, count 0 2006.224.08:03:49.16#ibcon#about to read 3, iclass 15, count 0 2006.224.08:03:49.18#ibcon#read 3, iclass 15, count 0 2006.224.08:03:49.18#ibcon#about to read 4, iclass 15, count 0 2006.224.08:03:49.18#ibcon#read 4, iclass 15, count 0 2006.224.08:03:49.18#ibcon#about to read 5, iclass 15, count 0 2006.224.08:03:49.18#ibcon#read 5, iclass 15, count 0 2006.224.08:03:49.18#ibcon#about to read 6, iclass 15, count 0 2006.224.08:03:49.18#ibcon#read 6, iclass 15, count 0 2006.224.08:03:49.18#ibcon#end of sib2, iclass 15, count 0 2006.224.08:03:49.18#ibcon#*mode == 0, iclass 15, count 0 2006.224.08:03:49.18#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.224.08:03:49.18#ibcon#[25=USB\r\n] 2006.224.08:03:49.18#ibcon#*before write, iclass 15, count 0 2006.224.08:03:49.18#ibcon#enter sib2, iclass 15, count 0 2006.224.08:03:49.18#ibcon#flushed, iclass 15, count 0 2006.224.08:03:49.18#ibcon#about to write, iclass 15, count 0 2006.224.08:03:49.18#ibcon#wrote, iclass 15, count 0 2006.224.08:03:49.18#ibcon#about to read 3, iclass 15, count 0 2006.224.08:03:49.21#ibcon#read 3, iclass 15, count 0 2006.224.08:03:49.21#ibcon#about to read 4, iclass 15, count 0 2006.224.08:03:49.21#ibcon#read 4, iclass 15, count 0 2006.224.08:03:49.21#ibcon#about to read 5, iclass 15, count 0 2006.224.08:03:49.21#ibcon#read 5, iclass 15, count 0 2006.224.08:03:49.21#ibcon#about to read 6, iclass 15, count 0 2006.224.08:03:49.21#ibcon#read 6, iclass 15, count 0 2006.224.08:03:49.21#ibcon#end of sib2, iclass 15, count 0 2006.224.08:03:49.21#ibcon#*after write, iclass 15, count 0 2006.224.08:03:49.21#ibcon#*before return 0, iclass 15, count 0 2006.224.08:03:49.21#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.224.08:03:49.21#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.224.08:03:49.21#ibcon#about to clear, iclass 15 cls_cnt 0 2006.224.08:03:49.21#ibcon#cleared, iclass 15 cls_cnt 0 2006.224.08:03:49.21$vc4f8/valo=5,652.99 2006.224.08:03:49.21#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.224.08:03:49.21#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.224.08:03:49.21#ibcon#ireg 17 cls_cnt 0 2006.224.08:03:49.21#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.224.08:03:49.21#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.224.08:03:49.21#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.224.08:03:49.21#ibcon#enter wrdev, iclass 17, count 0 2006.224.08:03:49.21#ibcon#first serial, iclass 17, count 0 2006.224.08:03:49.21#ibcon#enter sib2, iclass 17, count 0 2006.224.08:03:49.21#ibcon#flushed, iclass 17, count 0 2006.224.08:03:49.21#ibcon#about to write, iclass 17, count 0 2006.224.08:03:49.21#ibcon#wrote, iclass 17, count 0 2006.224.08:03:49.21#ibcon#about to read 3, iclass 17, count 0 2006.224.08:03:49.23#ibcon#read 3, iclass 17, count 0 2006.224.08:03:49.23#ibcon#about to read 4, iclass 17, count 0 2006.224.08:03:49.23#ibcon#read 4, iclass 17, count 0 2006.224.08:03:49.23#ibcon#about to read 5, iclass 17, count 0 2006.224.08:03:49.23#ibcon#read 5, iclass 17, count 0 2006.224.08:03:49.23#ibcon#about to read 6, iclass 17, count 0 2006.224.08:03:49.23#ibcon#read 6, iclass 17, count 0 2006.224.08:03:49.23#ibcon#end of sib2, iclass 17, count 0 2006.224.08:03:49.23#ibcon#*mode == 0, iclass 17, count 0 2006.224.08:03:49.23#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.224.08:03:49.23#ibcon#[26=FRQ=05,652.99\r\n] 2006.224.08:03:49.23#ibcon#*before write, iclass 17, count 0 2006.224.08:03:49.23#ibcon#enter sib2, iclass 17, count 0 2006.224.08:03:49.23#ibcon#flushed, iclass 17, count 0 2006.224.08:03:49.23#ibcon#about to write, iclass 17, count 0 2006.224.08:03:49.23#ibcon#wrote, iclass 17, count 0 2006.224.08:03:49.23#ibcon#about to read 3, iclass 17, count 0 2006.224.08:03:49.27#ibcon#read 3, iclass 17, count 0 2006.224.08:03:49.27#ibcon#about to read 4, iclass 17, count 0 2006.224.08:03:49.27#ibcon#read 4, iclass 17, count 0 2006.224.08:03:49.27#ibcon#about to read 5, iclass 17, count 0 2006.224.08:03:49.27#ibcon#read 5, iclass 17, count 0 2006.224.08:03:49.27#ibcon#about to read 6, iclass 17, count 0 2006.224.08:03:49.27#ibcon#read 6, iclass 17, count 0 2006.224.08:03:49.27#ibcon#end of sib2, iclass 17, count 0 2006.224.08:03:49.27#ibcon#*after write, iclass 17, count 0 2006.224.08:03:49.27#ibcon#*before return 0, iclass 17, count 0 2006.224.08:03:49.27#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.224.08:03:49.27#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.224.08:03:49.27#ibcon#about to clear, iclass 17 cls_cnt 0 2006.224.08:03:49.27#ibcon#cleared, iclass 17 cls_cnt 0 2006.224.08:03:49.27$vc4f8/va=5,7 2006.224.08:03:49.27#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.224.08:03:49.27#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.224.08:03:49.27#ibcon#ireg 11 cls_cnt 2 2006.224.08:03:49.27#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.224.08:03:49.33#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.224.08:03:49.33#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.224.08:03:49.33#ibcon#enter wrdev, iclass 19, count 2 2006.224.08:03:49.33#ibcon#first serial, iclass 19, count 2 2006.224.08:03:49.33#ibcon#enter sib2, iclass 19, count 2 2006.224.08:03:49.33#ibcon#flushed, iclass 19, count 2 2006.224.08:03:49.33#ibcon#about to write, iclass 19, count 2 2006.224.08:03:49.33#ibcon#wrote, iclass 19, count 2 2006.224.08:03:49.33#ibcon#about to read 3, iclass 19, count 2 2006.224.08:03:49.35#ibcon#read 3, iclass 19, count 2 2006.224.08:03:49.35#ibcon#about to read 4, iclass 19, count 2 2006.224.08:03:49.35#ibcon#read 4, iclass 19, count 2 2006.224.08:03:49.35#ibcon#about to read 5, iclass 19, count 2 2006.224.08:03:49.35#ibcon#read 5, iclass 19, count 2 2006.224.08:03:49.35#ibcon#about to read 6, iclass 19, count 2 2006.224.08:03:49.35#ibcon#read 6, iclass 19, count 2 2006.224.08:03:49.35#ibcon#end of sib2, iclass 19, count 2 2006.224.08:03:49.35#ibcon#*mode == 0, iclass 19, count 2 2006.224.08:03:49.35#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.224.08:03:49.35#ibcon#[25=AT05-07\r\n] 2006.224.08:03:49.35#ibcon#*before write, iclass 19, count 2 2006.224.08:03:49.35#ibcon#enter sib2, iclass 19, count 2 2006.224.08:03:49.35#ibcon#flushed, iclass 19, count 2 2006.224.08:03:49.35#ibcon#about to write, iclass 19, count 2 2006.224.08:03:49.35#ibcon#wrote, iclass 19, count 2 2006.224.08:03:49.35#ibcon#about to read 3, iclass 19, count 2 2006.224.08:03:49.38#ibcon#read 3, iclass 19, count 2 2006.224.08:03:49.38#ibcon#about to read 4, iclass 19, count 2 2006.224.08:03:49.38#ibcon#read 4, iclass 19, count 2 2006.224.08:03:49.38#ibcon#about to read 5, iclass 19, count 2 2006.224.08:03:49.38#ibcon#read 5, iclass 19, count 2 2006.224.08:03:49.38#ibcon#about to read 6, iclass 19, count 2 2006.224.08:03:49.38#ibcon#read 6, iclass 19, count 2 2006.224.08:03:49.38#ibcon#end of sib2, iclass 19, count 2 2006.224.08:03:49.38#ibcon#*after write, iclass 19, count 2 2006.224.08:03:49.38#ibcon#*before return 0, iclass 19, count 2 2006.224.08:03:49.38#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.224.08:03:49.38#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.224.08:03:49.38#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.224.08:03:49.38#ibcon#ireg 7 cls_cnt 0 2006.224.08:03:49.38#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.224.08:03:49.50#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.224.08:03:49.50#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.224.08:03:49.50#ibcon#enter wrdev, iclass 19, count 0 2006.224.08:03:49.50#ibcon#first serial, iclass 19, count 0 2006.224.08:03:49.50#ibcon#enter sib2, iclass 19, count 0 2006.224.08:03:49.50#ibcon#flushed, iclass 19, count 0 2006.224.08:03:49.50#ibcon#about to write, iclass 19, count 0 2006.224.08:03:49.50#ibcon#wrote, iclass 19, count 0 2006.224.08:03:49.50#ibcon#about to read 3, iclass 19, count 0 2006.224.08:03:49.52#ibcon#read 3, iclass 19, count 0 2006.224.08:03:49.52#ibcon#about to read 4, iclass 19, count 0 2006.224.08:03:49.52#ibcon#read 4, iclass 19, count 0 2006.224.08:03:49.52#ibcon#about to read 5, iclass 19, count 0 2006.224.08:03:49.52#ibcon#read 5, iclass 19, count 0 2006.224.08:03:49.52#ibcon#about to read 6, iclass 19, count 0 2006.224.08:03:49.52#ibcon#read 6, iclass 19, count 0 2006.224.08:03:49.52#ibcon#end of sib2, iclass 19, count 0 2006.224.08:03:49.52#ibcon#*mode == 0, iclass 19, count 0 2006.224.08:03:49.52#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.224.08:03:49.52#ibcon#[25=USB\r\n] 2006.224.08:03:49.52#ibcon#*before write, iclass 19, count 0 2006.224.08:03:49.52#ibcon#enter sib2, iclass 19, count 0 2006.224.08:03:49.52#ibcon#flushed, iclass 19, count 0 2006.224.08:03:49.52#ibcon#about to write, iclass 19, count 0 2006.224.08:03:49.52#ibcon#wrote, iclass 19, count 0 2006.224.08:03:49.52#ibcon#about to read 3, iclass 19, count 0 2006.224.08:03:49.55#ibcon#read 3, iclass 19, count 0 2006.224.08:03:49.55#ibcon#about to read 4, iclass 19, count 0 2006.224.08:03:49.55#ibcon#read 4, iclass 19, count 0 2006.224.08:03:49.55#ibcon#about to read 5, iclass 19, count 0 2006.224.08:03:49.55#ibcon#read 5, iclass 19, count 0 2006.224.08:03:49.55#ibcon#about to read 6, iclass 19, count 0 2006.224.08:03:49.55#ibcon#read 6, iclass 19, count 0 2006.224.08:03:49.55#ibcon#end of sib2, iclass 19, count 0 2006.224.08:03:49.55#ibcon#*after write, iclass 19, count 0 2006.224.08:03:49.55#ibcon#*before return 0, iclass 19, count 0 2006.224.08:03:49.55#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.224.08:03:49.55#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.224.08:03:49.55#ibcon#about to clear, iclass 19 cls_cnt 0 2006.224.08:03:49.55#ibcon#cleared, iclass 19 cls_cnt 0 2006.224.08:03:49.55$vc4f8/valo=6,772.99 2006.224.08:03:49.55#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.224.08:03:49.55#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.224.08:03:49.55#ibcon#ireg 17 cls_cnt 0 2006.224.08:03:49.55#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.224.08:03:49.55#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.224.08:03:49.55#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.224.08:03:49.55#ibcon#enter wrdev, iclass 21, count 0 2006.224.08:03:49.55#ibcon#first serial, iclass 21, count 0 2006.224.08:03:49.55#ibcon#enter sib2, iclass 21, count 0 2006.224.08:03:49.55#ibcon#flushed, iclass 21, count 0 2006.224.08:03:49.55#ibcon#about to write, iclass 21, count 0 2006.224.08:03:49.55#ibcon#wrote, iclass 21, count 0 2006.224.08:03:49.55#ibcon#about to read 3, iclass 21, count 0 2006.224.08:03:49.58#ibcon#read 3, iclass 21, count 0 2006.224.08:03:49.58#ibcon#about to read 4, iclass 21, count 0 2006.224.08:03:49.58#ibcon#read 4, iclass 21, count 0 2006.224.08:03:49.58#ibcon#about to read 5, iclass 21, count 0 2006.224.08:03:49.58#ibcon#read 5, iclass 21, count 0 2006.224.08:03:49.58#ibcon#about to read 6, iclass 21, count 0 2006.224.08:03:49.58#ibcon#read 6, iclass 21, count 0 2006.224.08:03:49.58#ibcon#end of sib2, iclass 21, count 0 2006.224.08:03:49.58#ibcon#*mode == 0, iclass 21, count 0 2006.224.08:03:49.58#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.224.08:03:49.58#ibcon#[26=FRQ=06,772.99\r\n] 2006.224.08:03:49.58#ibcon#*before write, iclass 21, count 0 2006.224.08:03:49.58#ibcon#enter sib2, iclass 21, count 0 2006.224.08:03:49.58#ibcon#flushed, iclass 21, count 0 2006.224.08:03:49.58#ibcon#about to write, iclass 21, count 0 2006.224.08:03:49.58#ibcon#wrote, iclass 21, count 0 2006.224.08:03:49.58#ibcon#about to read 3, iclass 21, count 0 2006.224.08:03:49.62#ibcon#read 3, iclass 21, count 0 2006.224.08:03:49.62#ibcon#about to read 4, iclass 21, count 0 2006.224.08:03:49.62#ibcon#read 4, iclass 21, count 0 2006.224.08:03:49.62#ibcon#about to read 5, iclass 21, count 0 2006.224.08:03:49.62#ibcon#read 5, iclass 21, count 0 2006.224.08:03:49.62#ibcon#about to read 6, iclass 21, count 0 2006.224.08:03:49.62#ibcon#read 6, iclass 21, count 0 2006.224.08:03:49.62#ibcon#end of sib2, iclass 21, count 0 2006.224.08:03:49.62#ibcon#*after write, iclass 21, count 0 2006.224.08:03:49.62#ibcon#*before return 0, iclass 21, count 0 2006.224.08:03:49.62#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.224.08:03:49.62#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.224.08:03:49.62#ibcon#about to clear, iclass 21 cls_cnt 0 2006.224.08:03:49.62#ibcon#cleared, iclass 21 cls_cnt 0 2006.224.08:03:49.62$vc4f8/va=6,6 2006.224.08:03:49.62#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.224.08:03:49.62#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.224.08:03:49.62#ibcon#ireg 11 cls_cnt 2 2006.224.08:03:49.62#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.224.08:03:49.67#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.224.08:03:49.67#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.224.08:03:49.67#ibcon#enter wrdev, iclass 23, count 2 2006.224.08:03:49.67#ibcon#first serial, iclass 23, count 2 2006.224.08:03:49.67#ibcon#enter sib2, iclass 23, count 2 2006.224.08:03:49.67#ibcon#flushed, iclass 23, count 2 2006.224.08:03:49.67#ibcon#about to write, iclass 23, count 2 2006.224.08:03:49.67#ibcon#wrote, iclass 23, count 2 2006.224.08:03:49.67#ibcon#about to read 3, iclass 23, count 2 2006.224.08:03:49.69#ibcon#read 3, iclass 23, count 2 2006.224.08:03:49.69#ibcon#about to read 4, iclass 23, count 2 2006.224.08:03:49.69#ibcon#read 4, iclass 23, count 2 2006.224.08:03:49.69#ibcon#about to read 5, iclass 23, count 2 2006.224.08:03:49.69#ibcon#read 5, iclass 23, count 2 2006.224.08:03:49.69#ibcon#about to read 6, iclass 23, count 2 2006.224.08:03:49.69#ibcon#read 6, iclass 23, count 2 2006.224.08:03:49.69#ibcon#end of sib2, iclass 23, count 2 2006.224.08:03:49.69#ibcon#*mode == 0, iclass 23, count 2 2006.224.08:03:49.69#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.224.08:03:49.69#ibcon#[25=AT06-06\r\n] 2006.224.08:03:49.69#ibcon#*before write, iclass 23, count 2 2006.224.08:03:49.69#ibcon#enter sib2, iclass 23, count 2 2006.224.08:03:49.69#ibcon#flushed, iclass 23, count 2 2006.224.08:03:49.69#ibcon#about to write, iclass 23, count 2 2006.224.08:03:49.69#ibcon#wrote, iclass 23, count 2 2006.224.08:03:49.69#ibcon#about to read 3, iclass 23, count 2 2006.224.08:03:49.72#ibcon#read 3, iclass 23, count 2 2006.224.08:03:49.72#ibcon#about to read 4, iclass 23, count 2 2006.224.08:03:49.72#ibcon#read 4, iclass 23, count 2 2006.224.08:03:49.72#ibcon#about to read 5, iclass 23, count 2 2006.224.08:03:49.72#ibcon#read 5, iclass 23, count 2 2006.224.08:03:49.72#ibcon#about to read 6, iclass 23, count 2 2006.224.08:03:49.72#ibcon#read 6, iclass 23, count 2 2006.224.08:03:49.72#ibcon#end of sib2, iclass 23, count 2 2006.224.08:03:49.72#ibcon#*after write, iclass 23, count 2 2006.224.08:03:49.72#ibcon#*before return 0, iclass 23, count 2 2006.224.08:03:49.72#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.224.08:03:49.72#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.224.08:03:49.72#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.224.08:03:49.72#ibcon#ireg 7 cls_cnt 0 2006.224.08:03:49.72#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.224.08:03:49.84#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.224.08:03:49.84#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.224.08:03:49.84#ibcon#enter wrdev, iclass 23, count 0 2006.224.08:03:49.84#ibcon#first serial, iclass 23, count 0 2006.224.08:03:49.84#ibcon#enter sib2, iclass 23, count 0 2006.224.08:03:49.84#ibcon#flushed, iclass 23, count 0 2006.224.08:03:49.84#ibcon#about to write, iclass 23, count 0 2006.224.08:03:49.84#ibcon#wrote, iclass 23, count 0 2006.224.08:03:49.84#ibcon#about to read 3, iclass 23, count 0 2006.224.08:03:49.86#ibcon#read 3, iclass 23, count 0 2006.224.08:03:49.86#ibcon#about to read 4, iclass 23, count 0 2006.224.08:03:49.86#ibcon#read 4, iclass 23, count 0 2006.224.08:03:49.86#ibcon#about to read 5, iclass 23, count 0 2006.224.08:03:49.86#ibcon#read 5, iclass 23, count 0 2006.224.08:03:49.86#ibcon#about to read 6, iclass 23, count 0 2006.224.08:03:49.86#ibcon#read 6, iclass 23, count 0 2006.224.08:03:49.86#ibcon#end of sib2, iclass 23, count 0 2006.224.08:03:49.86#ibcon#*mode == 0, iclass 23, count 0 2006.224.08:03:49.86#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.224.08:03:49.86#ibcon#[25=USB\r\n] 2006.224.08:03:49.86#ibcon#*before write, iclass 23, count 0 2006.224.08:03:49.86#ibcon#enter sib2, iclass 23, count 0 2006.224.08:03:49.86#ibcon#flushed, iclass 23, count 0 2006.224.08:03:49.86#ibcon#about to write, iclass 23, count 0 2006.224.08:03:49.86#ibcon#wrote, iclass 23, count 0 2006.224.08:03:49.86#ibcon#about to read 3, iclass 23, count 0 2006.224.08:03:49.89#ibcon#read 3, iclass 23, count 0 2006.224.08:03:49.89#ibcon#about to read 4, iclass 23, count 0 2006.224.08:03:49.89#ibcon#read 4, iclass 23, count 0 2006.224.08:03:49.89#ibcon#about to read 5, iclass 23, count 0 2006.224.08:03:49.89#ibcon#read 5, iclass 23, count 0 2006.224.08:03:49.89#ibcon#about to read 6, iclass 23, count 0 2006.224.08:03:49.89#ibcon#read 6, iclass 23, count 0 2006.224.08:03:49.89#ibcon#end of sib2, iclass 23, count 0 2006.224.08:03:49.89#ibcon#*after write, iclass 23, count 0 2006.224.08:03:49.89#ibcon#*before return 0, iclass 23, count 0 2006.224.08:03:49.89#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.224.08:03:49.89#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.224.08:03:49.89#ibcon#about to clear, iclass 23 cls_cnt 0 2006.224.08:03:49.89#ibcon#cleared, iclass 23 cls_cnt 0 2006.224.08:03:49.89$vc4f8/valo=7,832.99 2006.224.08:03:49.89#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.224.08:03:49.89#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.224.08:03:49.89#ibcon#ireg 17 cls_cnt 0 2006.224.08:03:49.89#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.224.08:03:49.89#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.224.08:03:49.89#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.224.08:03:49.89#ibcon#enter wrdev, iclass 25, count 0 2006.224.08:03:49.89#ibcon#first serial, iclass 25, count 0 2006.224.08:03:49.89#ibcon#enter sib2, iclass 25, count 0 2006.224.08:03:49.89#ibcon#flushed, iclass 25, count 0 2006.224.08:03:49.89#ibcon#about to write, iclass 25, count 0 2006.224.08:03:49.89#ibcon#wrote, iclass 25, count 0 2006.224.08:03:49.89#ibcon#about to read 3, iclass 25, count 0 2006.224.08:03:49.91#ibcon#read 3, iclass 25, count 0 2006.224.08:03:49.91#ibcon#about to read 4, iclass 25, count 0 2006.224.08:03:49.91#ibcon#read 4, iclass 25, count 0 2006.224.08:03:49.91#ibcon#about to read 5, iclass 25, count 0 2006.224.08:03:49.91#ibcon#read 5, iclass 25, count 0 2006.224.08:03:49.91#ibcon#about to read 6, iclass 25, count 0 2006.224.08:03:49.91#ibcon#read 6, iclass 25, count 0 2006.224.08:03:49.91#ibcon#end of sib2, iclass 25, count 0 2006.224.08:03:49.91#ibcon#*mode == 0, iclass 25, count 0 2006.224.08:03:49.91#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.224.08:03:49.91#ibcon#[26=FRQ=07,832.99\r\n] 2006.224.08:03:49.91#ibcon#*before write, iclass 25, count 0 2006.224.08:03:49.91#ibcon#enter sib2, iclass 25, count 0 2006.224.08:03:49.91#ibcon#flushed, iclass 25, count 0 2006.224.08:03:49.91#ibcon#about to write, iclass 25, count 0 2006.224.08:03:49.91#ibcon#wrote, iclass 25, count 0 2006.224.08:03:49.91#ibcon#about to read 3, iclass 25, count 0 2006.224.08:03:49.95#ibcon#read 3, iclass 25, count 0 2006.224.08:03:49.95#ibcon#about to read 4, iclass 25, count 0 2006.224.08:03:49.95#ibcon#read 4, iclass 25, count 0 2006.224.08:03:49.95#ibcon#about to read 5, iclass 25, count 0 2006.224.08:03:49.95#ibcon#read 5, iclass 25, count 0 2006.224.08:03:49.95#ibcon#about to read 6, iclass 25, count 0 2006.224.08:03:49.95#ibcon#read 6, iclass 25, count 0 2006.224.08:03:49.95#ibcon#end of sib2, iclass 25, count 0 2006.224.08:03:49.95#ibcon#*after write, iclass 25, count 0 2006.224.08:03:49.95#ibcon#*before return 0, iclass 25, count 0 2006.224.08:03:49.95#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.224.08:03:49.95#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.224.08:03:49.95#ibcon#about to clear, iclass 25 cls_cnt 0 2006.224.08:03:49.95#ibcon#cleared, iclass 25 cls_cnt 0 2006.224.08:03:49.95$vc4f8/va=7,6 2006.224.08:03:49.95#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.224.08:03:49.95#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.224.08:03:49.95#ibcon#ireg 11 cls_cnt 2 2006.224.08:03:49.95#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.224.08:03:50.01#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.224.08:03:50.01#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.224.08:03:50.01#ibcon#enter wrdev, iclass 27, count 2 2006.224.08:03:50.01#ibcon#first serial, iclass 27, count 2 2006.224.08:03:50.01#ibcon#enter sib2, iclass 27, count 2 2006.224.08:03:50.01#ibcon#flushed, iclass 27, count 2 2006.224.08:03:50.01#ibcon#about to write, iclass 27, count 2 2006.224.08:03:50.01#ibcon#wrote, iclass 27, count 2 2006.224.08:03:50.01#ibcon#about to read 3, iclass 27, count 2 2006.224.08:03:50.03#ibcon#read 3, iclass 27, count 2 2006.224.08:03:50.03#ibcon#about to read 4, iclass 27, count 2 2006.224.08:03:50.03#ibcon#read 4, iclass 27, count 2 2006.224.08:03:50.03#ibcon#about to read 5, iclass 27, count 2 2006.224.08:03:50.03#ibcon#read 5, iclass 27, count 2 2006.224.08:03:50.03#ibcon#about to read 6, iclass 27, count 2 2006.224.08:03:50.03#ibcon#read 6, iclass 27, count 2 2006.224.08:03:50.03#ibcon#end of sib2, iclass 27, count 2 2006.224.08:03:50.03#ibcon#*mode == 0, iclass 27, count 2 2006.224.08:03:50.03#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.224.08:03:50.03#ibcon#[25=AT07-06\r\n] 2006.224.08:03:50.03#ibcon#*before write, iclass 27, count 2 2006.224.08:03:50.03#ibcon#enter sib2, iclass 27, count 2 2006.224.08:03:50.03#ibcon#flushed, iclass 27, count 2 2006.224.08:03:50.03#ibcon#about to write, iclass 27, count 2 2006.224.08:03:50.03#ibcon#wrote, iclass 27, count 2 2006.224.08:03:50.03#ibcon#about to read 3, iclass 27, count 2 2006.224.08:03:50.06#ibcon#read 3, iclass 27, count 2 2006.224.08:03:50.06#ibcon#about to read 4, iclass 27, count 2 2006.224.08:03:50.06#ibcon#read 4, iclass 27, count 2 2006.224.08:03:50.06#ibcon#about to read 5, iclass 27, count 2 2006.224.08:03:50.06#ibcon#read 5, iclass 27, count 2 2006.224.08:03:50.06#ibcon#about to read 6, iclass 27, count 2 2006.224.08:03:50.06#ibcon#read 6, iclass 27, count 2 2006.224.08:03:50.06#ibcon#end of sib2, iclass 27, count 2 2006.224.08:03:50.06#ibcon#*after write, iclass 27, count 2 2006.224.08:03:50.06#ibcon#*before return 0, iclass 27, count 2 2006.224.08:03:50.06#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.224.08:03:50.06#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.224.08:03:50.06#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.224.08:03:50.06#ibcon#ireg 7 cls_cnt 0 2006.224.08:03:50.06#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.224.08:03:50.18#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.224.08:03:50.18#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.224.08:03:50.18#ibcon#enter wrdev, iclass 27, count 0 2006.224.08:03:50.18#ibcon#first serial, iclass 27, count 0 2006.224.08:03:50.18#ibcon#enter sib2, iclass 27, count 0 2006.224.08:03:50.18#ibcon#flushed, iclass 27, count 0 2006.224.08:03:50.18#ibcon#about to write, iclass 27, count 0 2006.224.08:03:50.18#ibcon#wrote, iclass 27, count 0 2006.224.08:03:50.18#ibcon#about to read 3, iclass 27, count 0 2006.224.08:03:50.20#ibcon#read 3, iclass 27, count 0 2006.224.08:03:50.20#ibcon#about to read 4, iclass 27, count 0 2006.224.08:03:50.20#ibcon#read 4, iclass 27, count 0 2006.224.08:03:50.20#ibcon#about to read 5, iclass 27, count 0 2006.224.08:03:50.20#ibcon#read 5, iclass 27, count 0 2006.224.08:03:50.20#ibcon#about to read 6, iclass 27, count 0 2006.224.08:03:50.20#ibcon#read 6, iclass 27, count 0 2006.224.08:03:50.20#ibcon#end of sib2, iclass 27, count 0 2006.224.08:03:50.20#ibcon#*mode == 0, iclass 27, count 0 2006.224.08:03:50.20#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.224.08:03:50.20#ibcon#[25=USB\r\n] 2006.224.08:03:50.20#ibcon#*before write, iclass 27, count 0 2006.224.08:03:50.20#ibcon#enter sib2, iclass 27, count 0 2006.224.08:03:50.20#ibcon#flushed, iclass 27, count 0 2006.224.08:03:50.20#ibcon#about to write, iclass 27, count 0 2006.224.08:03:50.20#ibcon#wrote, iclass 27, count 0 2006.224.08:03:50.20#ibcon#about to read 3, iclass 27, count 0 2006.224.08:03:50.23#ibcon#read 3, iclass 27, count 0 2006.224.08:03:50.23#ibcon#about to read 4, iclass 27, count 0 2006.224.08:03:50.23#ibcon#read 4, iclass 27, count 0 2006.224.08:03:50.23#ibcon#about to read 5, iclass 27, count 0 2006.224.08:03:50.23#ibcon#read 5, iclass 27, count 0 2006.224.08:03:50.23#ibcon#about to read 6, iclass 27, count 0 2006.224.08:03:50.23#ibcon#read 6, iclass 27, count 0 2006.224.08:03:50.23#ibcon#end of sib2, iclass 27, count 0 2006.224.08:03:50.23#ibcon#*after write, iclass 27, count 0 2006.224.08:03:50.23#ibcon#*before return 0, iclass 27, count 0 2006.224.08:03:50.23#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.224.08:03:50.23#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.224.08:03:50.23#ibcon#about to clear, iclass 27 cls_cnt 0 2006.224.08:03:50.23#ibcon#cleared, iclass 27 cls_cnt 0 2006.224.08:03:50.23$vc4f8/valo=8,852.99 2006.224.08:03:50.23#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.224.08:03:50.23#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.224.08:03:50.23#ibcon#ireg 17 cls_cnt 0 2006.224.08:03:50.23#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.224.08:03:50.23#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.224.08:03:50.23#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.224.08:03:50.23#ibcon#enter wrdev, iclass 29, count 0 2006.224.08:03:50.23#ibcon#first serial, iclass 29, count 0 2006.224.08:03:50.23#ibcon#enter sib2, iclass 29, count 0 2006.224.08:03:50.23#ibcon#flushed, iclass 29, count 0 2006.224.08:03:50.23#ibcon#about to write, iclass 29, count 0 2006.224.08:03:50.23#ibcon#wrote, iclass 29, count 0 2006.224.08:03:50.23#ibcon#about to read 3, iclass 29, count 0 2006.224.08:03:50.25#ibcon#read 3, iclass 29, count 0 2006.224.08:03:50.25#ibcon#about to read 4, iclass 29, count 0 2006.224.08:03:50.25#ibcon#read 4, iclass 29, count 0 2006.224.08:03:50.25#ibcon#about to read 5, iclass 29, count 0 2006.224.08:03:50.25#ibcon#read 5, iclass 29, count 0 2006.224.08:03:50.25#ibcon#about to read 6, iclass 29, count 0 2006.224.08:03:50.25#ibcon#read 6, iclass 29, count 0 2006.224.08:03:50.25#ibcon#end of sib2, iclass 29, count 0 2006.224.08:03:50.25#ibcon#*mode == 0, iclass 29, count 0 2006.224.08:03:50.25#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.224.08:03:50.25#ibcon#[26=FRQ=08,852.99\r\n] 2006.224.08:03:50.25#ibcon#*before write, iclass 29, count 0 2006.224.08:03:50.25#ibcon#enter sib2, iclass 29, count 0 2006.224.08:03:50.25#ibcon#flushed, iclass 29, count 0 2006.224.08:03:50.25#ibcon#about to write, iclass 29, count 0 2006.224.08:03:50.25#ibcon#wrote, iclass 29, count 0 2006.224.08:03:50.25#ibcon#about to read 3, iclass 29, count 0 2006.224.08:03:50.29#ibcon#read 3, iclass 29, count 0 2006.224.08:03:50.29#ibcon#about to read 4, iclass 29, count 0 2006.224.08:03:50.29#ibcon#read 4, iclass 29, count 0 2006.224.08:03:50.29#ibcon#about to read 5, iclass 29, count 0 2006.224.08:03:50.29#ibcon#read 5, iclass 29, count 0 2006.224.08:03:50.29#ibcon#about to read 6, iclass 29, count 0 2006.224.08:03:50.29#ibcon#read 6, iclass 29, count 0 2006.224.08:03:50.29#ibcon#end of sib2, iclass 29, count 0 2006.224.08:03:50.29#ibcon#*after write, iclass 29, count 0 2006.224.08:03:50.29#ibcon#*before return 0, iclass 29, count 0 2006.224.08:03:50.29#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.224.08:03:50.29#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.224.08:03:50.29#ibcon#about to clear, iclass 29 cls_cnt 0 2006.224.08:03:50.29#ibcon#cleared, iclass 29 cls_cnt 0 2006.224.08:03:50.29$vc4f8/va=8,7 2006.224.08:03:50.29#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.224.08:03:50.29#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.224.08:03:50.29#ibcon#ireg 11 cls_cnt 2 2006.224.08:03:50.29#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.224.08:03:50.35#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.224.08:03:50.35#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.224.08:03:50.35#ibcon#enter wrdev, iclass 31, count 2 2006.224.08:03:50.35#ibcon#first serial, iclass 31, count 2 2006.224.08:03:50.35#ibcon#enter sib2, iclass 31, count 2 2006.224.08:03:50.35#ibcon#flushed, iclass 31, count 2 2006.224.08:03:50.35#ibcon#about to write, iclass 31, count 2 2006.224.08:03:50.35#ibcon#wrote, iclass 31, count 2 2006.224.08:03:50.35#ibcon#about to read 3, iclass 31, count 2 2006.224.08:03:50.37#ibcon#read 3, iclass 31, count 2 2006.224.08:03:50.37#ibcon#about to read 4, iclass 31, count 2 2006.224.08:03:50.37#ibcon#read 4, iclass 31, count 2 2006.224.08:03:50.37#ibcon#about to read 5, iclass 31, count 2 2006.224.08:03:50.37#ibcon#read 5, iclass 31, count 2 2006.224.08:03:50.37#ibcon#about to read 6, iclass 31, count 2 2006.224.08:03:50.37#ibcon#read 6, iclass 31, count 2 2006.224.08:03:50.37#ibcon#end of sib2, iclass 31, count 2 2006.224.08:03:50.37#ibcon#*mode == 0, iclass 31, count 2 2006.224.08:03:50.37#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.224.08:03:50.37#ibcon#[25=AT08-07\r\n] 2006.224.08:03:50.37#ibcon#*before write, iclass 31, count 2 2006.224.08:03:50.37#ibcon#enter sib2, iclass 31, count 2 2006.224.08:03:50.37#ibcon#flushed, iclass 31, count 2 2006.224.08:03:50.37#ibcon#about to write, iclass 31, count 2 2006.224.08:03:50.37#ibcon#wrote, iclass 31, count 2 2006.224.08:03:50.37#ibcon#about to read 3, iclass 31, count 2 2006.224.08:03:50.41#ibcon#read 3, iclass 31, count 2 2006.224.08:03:50.41#ibcon#about to read 4, iclass 31, count 2 2006.224.08:03:50.41#ibcon#read 4, iclass 31, count 2 2006.224.08:03:50.41#ibcon#about to read 5, iclass 31, count 2 2006.224.08:03:50.41#ibcon#read 5, iclass 31, count 2 2006.224.08:03:50.41#ibcon#about to read 6, iclass 31, count 2 2006.224.08:03:50.41#ibcon#read 6, iclass 31, count 2 2006.224.08:03:50.41#ibcon#end of sib2, iclass 31, count 2 2006.224.08:03:50.41#ibcon#*after write, iclass 31, count 2 2006.224.08:03:50.41#ibcon#*before return 0, iclass 31, count 2 2006.224.08:03:50.41#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.224.08:03:50.41#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.224.08:03:50.41#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.224.08:03:50.41#ibcon#ireg 7 cls_cnt 0 2006.224.08:03:50.41#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.224.08:03:50.53#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.224.08:03:50.53#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.224.08:03:50.53#ibcon#enter wrdev, iclass 31, count 0 2006.224.08:03:50.53#ibcon#first serial, iclass 31, count 0 2006.224.08:03:50.53#ibcon#enter sib2, iclass 31, count 0 2006.224.08:03:50.53#ibcon#flushed, iclass 31, count 0 2006.224.08:03:50.53#ibcon#about to write, iclass 31, count 0 2006.224.08:03:50.53#ibcon#wrote, iclass 31, count 0 2006.224.08:03:50.53#ibcon#about to read 3, iclass 31, count 0 2006.224.08:03:50.55#ibcon#read 3, iclass 31, count 0 2006.224.08:03:50.55#ibcon#about to read 4, iclass 31, count 0 2006.224.08:03:50.55#ibcon#read 4, iclass 31, count 0 2006.224.08:03:50.55#ibcon#about to read 5, iclass 31, count 0 2006.224.08:03:50.55#ibcon#read 5, iclass 31, count 0 2006.224.08:03:50.55#ibcon#about to read 6, iclass 31, count 0 2006.224.08:03:50.55#ibcon#read 6, iclass 31, count 0 2006.224.08:03:50.55#ibcon#end of sib2, iclass 31, count 0 2006.224.08:03:50.55#ibcon#*mode == 0, iclass 31, count 0 2006.224.08:03:50.55#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.224.08:03:50.55#ibcon#[25=USB\r\n] 2006.224.08:03:50.55#ibcon#*before write, iclass 31, count 0 2006.224.08:03:50.55#ibcon#enter sib2, iclass 31, count 0 2006.224.08:03:50.55#ibcon#flushed, iclass 31, count 0 2006.224.08:03:50.55#ibcon#about to write, iclass 31, count 0 2006.224.08:03:50.55#ibcon#wrote, iclass 31, count 0 2006.224.08:03:50.55#ibcon#about to read 3, iclass 31, count 0 2006.224.08:03:50.58#ibcon#read 3, iclass 31, count 0 2006.224.08:03:50.58#ibcon#about to read 4, iclass 31, count 0 2006.224.08:03:50.58#ibcon#read 4, iclass 31, count 0 2006.224.08:03:50.58#ibcon#about to read 5, iclass 31, count 0 2006.224.08:03:50.58#ibcon#read 5, iclass 31, count 0 2006.224.08:03:50.58#ibcon#about to read 6, iclass 31, count 0 2006.224.08:03:50.58#ibcon#read 6, iclass 31, count 0 2006.224.08:03:50.58#ibcon#end of sib2, iclass 31, count 0 2006.224.08:03:50.58#ibcon#*after write, iclass 31, count 0 2006.224.08:03:50.58#ibcon#*before return 0, iclass 31, count 0 2006.224.08:03:50.58#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.224.08:03:50.58#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.224.08:03:50.58#ibcon#about to clear, iclass 31 cls_cnt 0 2006.224.08:03:50.58#ibcon#cleared, iclass 31 cls_cnt 0 2006.224.08:03:50.58$vc4f8/vblo=1,632.99 2006.224.08:03:50.58#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.224.08:03:50.58#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.224.08:03:50.58#ibcon#ireg 17 cls_cnt 0 2006.224.08:03:50.58#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.224.08:03:50.58#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.224.08:03:50.58#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.224.08:03:50.58#ibcon#enter wrdev, iclass 33, count 0 2006.224.08:03:50.58#ibcon#first serial, iclass 33, count 0 2006.224.08:03:50.58#ibcon#enter sib2, iclass 33, count 0 2006.224.08:03:50.58#ibcon#flushed, iclass 33, count 0 2006.224.08:03:50.58#ibcon#about to write, iclass 33, count 0 2006.224.08:03:50.58#ibcon#wrote, iclass 33, count 0 2006.224.08:03:50.58#ibcon#about to read 3, iclass 33, count 0 2006.224.08:03:50.60#ibcon#read 3, iclass 33, count 0 2006.224.08:03:50.60#ibcon#about to read 4, iclass 33, count 0 2006.224.08:03:50.60#ibcon#read 4, iclass 33, count 0 2006.224.08:03:50.60#ibcon#about to read 5, iclass 33, count 0 2006.224.08:03:50.60#ibcon#read 5, iclass 33, count 0 2006.224.08:03:50.60#ibcon#about to read 6, iclass 33, count 0 2006.224.08:03:50.60#ibcon#read 6, iclass 33, count 0 2006.224.08:03:50.60#ibcon#end of sib2, iclass 33, count 0 2006.224.08:03:50.60#ibcon#*mode == 0, iclass 33, count 0 2006.224.08:03:50.60#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.224.08:03:50.60#ibcon#[28=FRQ=01,632.99\r\n] 2006.224.08:03:50.60#ibcon#*before write, iclass 33, count 0 2006.224.08:03:50.60#ibcon#enter sib2, iclass 33, count 0 2006.224.08:03:50.60#ibcon#flushed, iclass 33, count 0 2006.224.08:03:50.60#ibcon#about to write, iclass 33, count 0 2006.224.08:03:50.60#ibcon#wrote, iclass 33, count 0 2006.224.08:03:50.60#ibcon#about to read 3, iclass 33, count 0 2006.224.08:03:50.64#ibcon#read 3, iclass 33, count 0 2006.224.08:03:50.64#ibcon#about to read 4, iclass 33, count 0 2006.224.08:03:50.64#ibcon#read 4, iclass 33, count 0 2006.224.08:03:50.64#ibcon#about to read 5, iclass 33, count 0 2006.224.08:03:50.64#ibcon#read 5, iclass 33, count 0 2006.224.08:03:50.64#ibcon#about to read 6, iclass 33, count 0 2006.224.08:03:50.64#ibcon#read 6, iclass 33, count 0 2006.224.08:03:50.64#ibcon#end of sib2, iclass 33, count 0 2006.224.08:03:50.64#ibcon#*after write, iclass 33, count 0 2006.224.08:03:50.64#ibcon#*before return 0, iclass 33, count 0 2006.224.08:03:50.64#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.224.08:03:50.64#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.224.08:03:50.64#ibcon#about to clear, iclass 33 cls_cnt 0 2006.224.08:03:50.64#ibcon#cleared, iclass 33 cls_cnt 0 2006.224.08:03:50.64$vc4f8/vb=1,4 2006.224.08:03:50.64#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.224.08:03:50.64#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.224.08:03:50.64#ibcon#ireg 11 cls_cnt 2 2006.224.08:03:50.64#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.224.08:03:50.64#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.224.08:03:50.64#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.224.08:03:50.64#ibcon#enter wrdev, iclass 35, count 2 2006.224.08:03:50.64#ibcon#first serial, iclass 35, count 2 2006.224.08:03:50.64#ibcon#enter sib2, iclass 35, count 2 2006.224.08:03:50.64#ibcon#flushed, iclass 35, count 2 2006.224.08:03:50.64#ibcon#about to write, iclass 35, count 2 2006.224.08:03:50.64#ibcon#wrote, iclass 35, count 2 2006.224.08:03:50.64#ibcon#about to read 3, iclass 35, count 2 2006.224.08:03:50.66#ibcon#read 3, iclass 35, count 2 2006.224.08:03:50.66#ibcon#about to read 4, iclass 35, count 2 2006.224.08:03:50.66#ibcon#read 4, iclass 35, count 2 2006.224.08:03:50.66#ibcon#about to read 5, iclass 35, count 2 2006.224.08:03:50.66#ibcon#read 5, iclass 35, count 2 2006.224.08:03:50.66#ibcon#about to read 6, iclass 35, count 2 2006.224.08:03:50.66#ibcon#read 6, iclass 35, count 2 2006.224.08:03:50.66#ibcon#end of sib2, iclass 35, count 2 2006.224.08:03:50.66#ibcon#*mode == 0, iclass 35, count 2 2006.224.08:03:50.66#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.224.08:03:50.66#ibcon#[27=AT01-04\r\n] 2006.224.08:03:50.66#ibcon#*before write, iclass 35, count 2 2006.224.08:03:50.66#ibcon#enter sib2, iclass 35, count 2 2006.224.08:03:50.66#ibcon#flushed, iclass 35, count 2 2006.224.08:03:50.66#ibcon#about to write, iclass 35, count 2 2006.224.08:03:50.66#ibcon#wrote, iclass 35, count 2 2006.224.08:03:50.66#ibcon#about to read 3, iclass 35, count 2 2006.224.08:03:50.69#ibcon#read 3, iclass 35, count 2 2006.224.08:03:50.69#ibcon#about to read 4, iclass 35, count 2 2006.224.08:03:50.69#ibcon#read 4, iclass 35, count 2 2006.224.08:03:50.69#ibcon#about to read 5, iclass 35, count 2 2006.224.08:03:50.69#ibcon#read 5, iclass 35, count 2 2006.224.08:03:50.69#ibcon#about to read 6, iclass 35, count 2 2006.224.08:03:50.69#ibcon#read 6, iclass 35, count 2 2006.224.08:03:50.69#ibcon#end of sib2, iclass 35, count 2 2006.224.08:03:50.69#ibcon#*after write, iclass 35, count 2 2006.224.08:03:50.69#ibcon#*before return 0, iclass 35, count 2 2006.224.08:03:50.69#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.224.08:03:50.69#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.224.08:03:50.69#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.224.08:03:50.69#ibcon#ireg 7 cls_cnt 0 2006.224.08:03:50.69#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.224.08:03:50.81#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.224.08:03:50.81#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.224.08:03:50.81#ibcon#enter wrdev, iclass 35, count 0 2006.224.08:03:50.81#ibcon#first serial, iclass 35, count 0 2006.224.08:03:50.81#ibcon#enter sib2, iclass 35, count 0 2006.224.08:03:50.81#ibcon#flushed, iclass 35, count 0 2006.224.08:03:50.81#ibcon#about to write, iclass 35, count 0 2006.224.08:03:50.81#ibcon#wrote, iclass 35, count 0 2006.224.08:03:50.81#ibcon#about to read 3, iclass 35, count 0 2006.224.08:03:50.83#ibcon#read 3, iclass 35, count 0 2006.224.08:03:50.83#ibcon#about to read 4, iclass 35, count 0 2006.224.08:03:50.83#ibcon#read 4, iclass 35, count 0 2006.224.08:03:50.83#ibcon#about to read 5, iclass 35, count 0 2006.224.08:03:50.83#ibcon#read 5, iclass 35, count 0 2006.224.08:03:50.83#ibcon#about to read 6, iclass 35, count 0 2006.224.08:03:50.83#ibcon#read 6, iclass 35, count 0 2006.224.08:03:50.83#ibcon#end of sib2, iclass 35, count 0 2006.224.08:03:50.83#ibcon#*mode == 0, iclass 35, count 0 2006.224.08:03:50.83#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.224.08:03:50.83#ibcon#[27=USB\r\n] 2006.224.08:03:50.83#ibcon#*before write, iclass 35, count 0 2006.224.08:03:50.83#ibcon#enter sib2, iclass 35, count 0 2006.224.08:03:50.83#ibcon#flushed, iclass 35, count 0 2006.224.08:03:50.83#ibcon#about to write, iclass 35, count 0 2006.224.08:03:50.83#ibcon#wrote, iclass 35, count 0 2006.224.08:03:50.83#ibcon#about to read 3, iclass 35, count 0 2006.224.08:03:50.86#ibcon#read 3, iclass 35, count 0 2006.224.08:03:50.86#ibcon#about to read 4, iclass 35, count 0 2006.224.08:03:50.86#ibcon#read 4, iclass 35, count 0 2006.224.08:03:50.86#ibcon#about to read 5, iclass 35, count 0 2006.224.08:03:50.86#ibcon#read 5, iclass 35, count 0 2006.224.08:03:50.86#ibcon#about to read 6, iclass 35, count 0 2006.224.08:03:50.86#ibcon#read 6, iclass 35, count 0 2006.224.08:03:50.86#ibcon#end of sib2, iclass 35, count 0 2006.224.08:03:50.86#ibcon#*after write, iclass 35, count 0 2006.224.08:03:50.86#ibcon#*before return 0, iclass 35, count 0 2006.224.08:03:50.86#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.224.08:03:50.86#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.224.08:03:50.86#ibcon#about to clear, iclass 35 cls_cnt 0 2006.224.08:03:50.86#ibcon#cleared, iclass 35 cls_cnt 0 2006.224.08:03:50.86$vc4f8/vblo=2,640.99 2006.224.08:03:50.86#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.224.08:03:50.86#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.224.08:03:50.86#ibcon#ireg 17 cls_cnt 0 2006.224.08:03:50.86#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.224.08:03:50.86#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.224.08:03:50.86#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.224.08:03:50.86#ibcon#enter wrdev, iclass 37, count 0 2006.224.08:03:50.86#ibcon#first serial, iclass 37, count 0 2006.224.08:03:50.86#ibcon#enter sib2, iclass 37, count 0 2006.224.08:03:50.86#ibcon#flushed, iclass 37, count 0 2006.224.08:03:50.86#ibcon#about to write, iclass 37, count 0 2006.224.08:03:50.86#ibcon#wrote, iclass 37, count 0 2006.224.08:03:50.86#ibcon#about to read 3, iclass 37, count 0 2006.224.08:03:50.88#ibcon#read 3, iclass 37, count 0 2006.224.08:03:50.88#ibcon#about to read 4, iclass 37, count 0 2006.224.08:03:50.88#ibcon#read 4, iclass 37, count 0 2006.224.08:03:50.88#ibcon#about to read 5, iclass 37, count 0 2006.224.08:03:50.88#ibcon#read 5, iclass 37, count 0 2006.224.08:03:50.88#ibcon#about to read 6, iclass 37, count 0 2006.224.08:03:50.88#ibcon#read 6, iclass 37, count 0 2006.224.08:03:50.88#ibcon#end of sib2, iclass 37, count 0 2006.224.08:03:50.88#ibcon#*mode == 0, iclass 37, count 0 2006.224.08:03:50.88#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.224.08:03:50.88#ibcon#[28=FRQ=02,640.99\r\n] 2006.224.08:03:50.88#ibcon#*before write, iclass 37, count 0 2006.224.08:03:50.88#ibcon#enter sib2, iclass 37, count 0 2006.224.08:03:50.88#ibcon#flushed, iclass 37, count 0 2006.224.08:03:50.88#ibcon#about to write, iclass 37, count 0 2006.224.08:03:50.88#ibcon#wrote, iclass 37, count 0 2006.224.08:03:50.88#ibcon#about to read 3, iclass 37, count 0 2006.224.08:03:50.92#ibcon#read 3, iclass 37, count 0 2006.224.08:03:50.92#ibcon#about to read 4, iclass 37, count 0 2006.224.08:03:50.92#ibcon#read 4, iclass 37, count 0 2006.224.08:03:50.92#ibcon#about to read 5, iclass 37, count 0 2006.224.08:03:50.92#ibcon#read 5, iclass 37, count 0 2006.224.08:03:50.92#ibcon#about to read 6, iclass 37, count 0 2006.224.08:03:50.92#ibcon#read 6, iclass 37, count 0 2006.224.08:03:50.92#ibcon#end of sib2, iclass 37, count 0 2006.224.08:03:50.92#ibcon#*after write, iclass 37, count 0 2006.224.08:03:50.92#ibcon#*before return 0, iclass 37, count 0 2006.224.08:03:50.92#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.224.08:03:50.92#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.224.08:03:50.92#ibcon#about to clear, iclass 37 cls_cnt 0 2006.224.08:03:50.92#ibcon#cleared, iclass 37 cls_cnt 0 2006.224.08:03:50.92$vc4f8/vb=2,4 2006.224.08:03:50.92#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.224.08:03:50.92#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.224.08:03:50.92#ibcon#ireg 11 cls_cnt 2 2006.224.08:03:50.92#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.224.08:03:50.98#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.224.08:03:50.98#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.224.08:03:50.98#ibcon#enter wrdev, iclass 39, count 2 2006.224.08:03:50.98#ibcon#first serial, iclass 39, count 2 2006.224.08:03:50.98#ibcon#enter sib2, iclass 39, count 2 2006.224.08:03:50.98#ibcon#flushed, iclass 39, count 2 2006.224.08:03:50.98#ibcon#about to write, iclass 39, count 2 2006.224.08:03:50.98#ibcon#wrote, iclass 39, count 2 2006.224.08:03:50.98#ibcon#about to read 3, iclass 39, count 2 2006.224.08:03:51.00#ibcon#read 3, iclass 39, count 2 2006.224.08:03:51.00#ibcon#about to read 4, iclass 39, count 2 2006.224.08:03:51.00#ibcon#read 4, iclass 39, count 2 2006.224.08:03:51.00#ibcon#about to read 5, iclass 39, count 2 2006.224.08:03:51.00#ibcon#read 5, iclass 39, count 2 2006.224.08:03:51.00#ibcon#about to read 6, iclass 39, count 2 2006.224.08:03:51.00#ibcon#read 6, iclass 39, count 2 2006.224.08:03:51.00#ibcon#end of sib2, iclass 39, count 2 2006.224.08:03:51.00#ibcon#*mode == 0, iclass 39, count 2 2006.224.08:03:51.00#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.224.08:03:51.00#ibcon#[27=AT02-04\r\n] 2006.224.08:03:51.00#ibcon#*before write, iclass 39, count 2 2006.224.08:03:51.00#ibcon#enter sib2, iclass 39, count 2 2006.224.08:03:51.00#ibcon#flushed, iclass 39, count 2 2006.224.08:03:51.00#ibcon#about to write, iclass 39, count 2 2006.224.08:03:51.00#ibcon#wrote, iclass 39, count 2 2006.224.08:03:51.00#ibcon#about to read 3, iclass 39, count 2 2006.224.08:03:51.03#ibcon#read 3, iclass 39, count 2 2006.224.08:03:51.03#ibcon#about to read 4, iclass 39, count 2 2006.224.08:03:51.03#ibcon#read 4, iclass 39, count 2 2006.224.08:03:51.03#ibcon#about to read 5, iclass 39, count 2 2006.224.08:03:51.03#ibcon#read 5, iclass 39, count 2 2006.224.08:03:51.03#ibcon#about to read 6, iclass 39, count 2 2006.224.08:03:51.03#ibcon#read 6, iclass 39, count 2 2006.224.08:03:51.03#ibcon#end of sib2, iclass 39, count 2 2006.224.08:03:51.03#ibcon#*after write, iclass 39, count 2 2006.224.08:03:51.03#ibcon#*before return 0, iclass 39, count 2 2006.224.08:03:51.03#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.224.08:03:51.03#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.224.08:03:51.03#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.224.08:03:51.03#ibcon#ireg 7 cls_cnt 0 2006.224.08:03:51.03#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.224.08:03:51.15#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.224.08:03:51.15#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.224.08:03:51.15#ibcon#enter wrdev, iclass 39, count 0 2006.224.08:03:51.15#ibcon#first serial, iclass 39, count 0 2006.224.08:03:51.15#ibcon#enter sib2, iclass 39, count 0 2006.224.08:03:51.15#ibcon#flushed, iclass 39, count 0 2006.224.08:03:51.15#ibcon#about to write, iclass 39, count 0 2006.224.08:03:51.15#ibcon#wrote, iclass 39, count 0 2006.224.08:03:51.15#ibcon#about to read 3, iclass 39, count 0 2006.224.08:03:51.17#ibcon#read 3, iclass 39, count 0 2006.224.08:03:51.17#ibcon#about to read 4, iclass 39, count 0 2006.224.08:03:51.17#ibcon#read 4, iclass 39, count 0 2006.224.08:03:51.17#ibcon#about to read 5, iclass 39, count 0 2006.224.08:03:51.17#ibcon#read 5, iclass 39, count 0 2006.224.08:03:51.17#ibcon#about to read 6, iclass 39, count 0 2006.224.08:03:51.17#ibcon#read 6, iclass 39, count 0 2006.224.08:03:51.17#ibcon#end of sib2, iclass 39, count 0 2006.224.08:03:51.17#ibcon#*mode == 0, iclass 39, count 0 2006.224.08:03:51.17#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.224.08:03:51.17#ibcon#[27=USB\r\n] 2006.224.08:03:51.17#ibcon#*before write, iclass 39, count 0 2006.224.08:03:51.17#ibcon#enter sib2, iclass 39, count 0 2006.224.08:03:51.17#ibcon#flushed, iclass 39, count 0 2006.224.08:03:51.17#ibcon#about to write, iclass 39, count 0 2006.224.08:03:51.17#ibcon#wrote, iclass 39, count 0 2006.224.08:03:51.17#ibcon#about to read 3, iclass 39, count 0 2006.224.08:03:51.20#ibcon#read 3, iclass 39, count 0 2006.224.08:03:51.20#ibcon#about to read 4, iclass 39, count 0 2006.224.08:03:51.20#ibcon#read 4, iclass 39, count 0 2006.224.08:03:51.20#ibcon#about to read 5, iclass 39, count 0 2006.224.08:03:51.20#ibcon#read 5, iclass 39, count 0 2006.224.08:03:51.20#ibcon#about to read 6, iclass 39, count 0 2006.224.08:03:51.20#ibcon#read 6, iclass 39, count 0 2006.224.08:03:51.20#ibcon#end of sib2, iclass 39, count 0 2006.224.08:03:51.20#ibcon#*after write, iclass 39, count 0 2006.224.08:03:51.20#ibcon#*before return 0, iclass 39, count 0 2006.224.08:03:51.20#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.224.08:03:51.20#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.224.08:03:51.20#ibcon#about to clear, iclass 39 cls_cnt 0 2006.224.08:03:51.20#ibcon#cleared, iclass 39 cls_cnt 0 2006.224.08:03:51.20$vc4f8/vblo=3,656.99 2006.224.08:03:51.20#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.224.08:03:51.20#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.224.08:03:51.20#ibcon#ireg 17 cls_cnt 0 2006.224.08:03:51.20#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.224.08:03:51.20#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.224.08:03:51.20#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.224.08:03:51.20#ibcon#enter wrdev, iclass 3, count 0 2006.224.08:03:51.20#ibcon#first serial, iclass 3, count 0 2006.224.08:03:51.20#ibcon#enter sib2, iclass 3, count 0 2006.224.08:03:51.20#ibcon#flushed, iclass 3, count 0 2006.224.08:03:51.20#ibcon#about to write, iclass 3, count 0 2006.224.08:03:51.20#ibcon#wrote, iclass 3, count 0 2006.224.08:03:51.20#ibcon#about to read 3, iclass 3, count 0 2006.224.08:03:51.22#ibcon#read 3, iclass 3, count 0 2006.224.08:03:51.22#ibcon#about to read 4, iclass 3, count 0 2006.224.08:03:51.22#ibcon#read 4, iclass 3, count 0 2006.224.08:03:51.22#ibcon#about to read 5, iclass 3, count 0 2006.224.08:03:51.22#ibcon#read 5, iclass 3, count 0 2006.224.08:03:51.22#ibcon#about to read 6, iclass 3, count 0 2006.224.08:03:51.22#ibcon#read 6, iclass 3, count 0 2006.224.08:03:51.22#ibcon#end of sib2, iclass 3, count 0 2006.224.08:03:51.22#ibcon#*mode == 0, iclass 3, count 0 2006.224.08:03:51.22#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.224.08:03:51.22#ibcon#[28=FRQ=03,656.99\r\n] 2006.224.08:03:51.22#ibcon#*before write, iclass 3, count 0 2006.224.08:03:51.22#ibcon#enter sib2, iclass 3, count 0 2006.224.08:03:51.22#ibcon#flushed, iclass 3, count 0 2006.224.08:03:51.22#ibcon#about to write, iclass 3, count 0 2006.224.08:03:51.22#ibcon#wrote, iclass 3, count 0 2006.224.08:03:51.22#ibcon#about to read 3, iclass 3, count 0 2006.224.08:03:51.26#ibcon#read 3, iclass 3, count 0 2006.224.08:03:51.26#ibcon#about to read 4, iclass 3, count 0 2006.224.08:03:51.26#ibcon#read 4, iclass 3, count 0 2006.224.08:03:51.26#ibcon#about to read 5, iclass 3, count 0 2006.224.08:03:51.26#ibcon#read 5, iclass 3, count 0 2006.224.08:03:51.26#ibcon#about to read 6, iclass 3, count 0 2006.224.08:03:51.26#ibcon#read 6, iclass 3, count 0 2006.224.08:03:51.26#ibcon#end of sib2, iclass 3, count 0 2006.224.08:03:51.26#ibcon#*after write, iclass 3, count 0 2006.224.08:03:51.26#ibcon#*before return 0, iclass 3, count 0 2006.224.08:03:51.26#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.224.08:03:51.26#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.224.08:03:51.26#ibcon#about to clear, iclass 3 cls_cnt 0 2006.224.08:03:51.26#ibcon#cleared, iclass 3 cls_cnt 0 2006.224.08:03:51.26$vc4f8/vb=3,4 2006.224.08:03:51.26#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.224.08:03:51.26#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.224.08:03:51.26#ibcon#ireg 11 cls_cnt 2 2006.224.08:03:51.26#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.224.08:03:51.32#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.224.08:03:51.32#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.224.08:03:51.32#ibcon#enter wrdev, iclass 5, count 2 2006.224.08:03:51.32#ibcon#first serial, iclass 5, count 2 2006.224.08:03:51.32#ibcon#enter sib2, iclass 5, count 2 2006.224.08:03:51.32#ibcon#flushed, iclass 5, count 2 2006.224.08:03:51.32#ibcon#about to write, iclass 5, count 2 2006.224.08:03:51.32#ibcon#wrote, iclass 5, count 2 2006.224.08:03:51.32#ibcon#about to read 3, iclass 5, count 2 2006.224.08:03:51.34#ibcon#read 3, iclass 5, count 2 2006.224.08:03:51.34#ibcon#about to read 4, iclass 5, count 2 2006.224.08:03:51.34#ibcon#read 4, iclass 5, count 2 2006.224.08:03:51.34#ibcon#about to read 5, iclass 5, count 2 2006.224.08:03:51.34#ibcon#read 5, iclass 5, count 2 2006.224.08:03:51.34#ibcon#about to read 6, iclass 5, count 2 2006.224.08:03:51.34#ibcon#read 6, iclass 5, count 2 2006.224.08:03:51.34#ibcon#end of sib2, iclass 5, count 2 2006.224.08:03:51.34#ibcon#*mode == 0, iclass 5, count 2 2006.224.08:03:51.34#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.224.08:03:51.34#ibcon#[27=AT03-04\r\n] 2006.224.08:03:51.34#ibcon#*before write, iclass 5, count 2 2006.224.08:03:51.34#ibcon#enter sib2, iclass 5, count 2 2006.224.08:03:51.34#ibcon#flushed, iclass 5, count 2 2006.224.08:03:51.34#ibcon#about to write, iclass 5, count 2 2006.224.08:03:51.34#ibcon#wrote, iclass 5, count 2 2006.224.08:03:51.34#ibcon#about to read 3, iclass 5, count 2 2006.224.08:03:51.37#ibcon#read 3, iclass 5, count 2 2006.224.08:03:51.37#ibcon#about to read 4, iclass 5, count 2 2006.224.08:03:51.37#ibcon#read 4, iclass 5, count 2 2006.224.08:03:51.37#ibcon#about to read 5, iclass 5, count 2 2006.224.08:03:51.37#ibcon#read 5, iclass 5, count 2 2006.224.08:03:51.37#ibcon#about to read 6, iclass 5, count 2 2006.224.08:03:51.37#ibcon#read 6, iclass 5, count 2 2006.224.08:03:51.37#ibcon#end of sib2, iclass 5, count 2 2006.224.08:03:51.37#ibcon#*after write, iclass 5, count 2 2006.224.08:03:51.37#ibcon#*before return 0, iclass 5, count 2 2006.224.08:03:51.37#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.224.08:03:51.37#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.224.08:03:51.37#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.224.08:03:51.37#ibcon#ireg 7 cls_cnt 0 2006.224.08:03:51.37#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.224.08:03:51.49#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.224.08:03:51.49#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.224.08:03:51.49#ibcon#enter wrdev, iclass 5, count 0 2006.224.08:03:51.49#ibcon#first serial, iclass 5, count 0 2006.224.08:03:51.49#ibcon#enter sib2, iclass 5, count 0 2006.224.08:03:51.49#ibcon#flushed, iclass 5, count 0 2006.224.08:03:51.49#ibcon#about to write, iclass 5, count 0 2006.224.08:03:51.49#ibcon#wrote, iclass 5, count 0 2006.224.08:03:51.49#ibcon#about to read 3, iclass 5, count 0 2006.224.08:03:51.51#ibcon#read 3, iclass 5, count 0 2006.224.08:03:51.51#ibcon#about to read 4, iclass 5, count 0 2006.224.08:03:51.51#ibcon#read 4, iclass 5, count 0 2006.224.08:03:51.51#ibcon#about to read 5, iclass 5, count 0 2006.224.08:03:51.51#ibcon#read 5, iclass 5, count 0 2006.224.08:03:51.51#ibcon#about to read 6, iclass 5, count 0 2006.224.08:03:51.51#ibcon#read 6, iclass 5, count 0 2006.224.08:03:51.51#ibcon#end of sib2, iclass 5, count 0 2006.224.08:03:51.51#ibcon#*mode == 0, iclass 5, count 0 2006.224.08:03:51.51#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.224.08:03:51.51#ibcon#[27=USB\r\n] 2006.224.08:03:51.51#ibcon#*before write, iclass 5, count 0 2006.224.08:03:51.51#ibcon#enter sib2, iclass 5, count 0 2006.224.08:03:51.51#ibcon#flushed, iclass 5, count 0 2006.224.08:03:51.51#ibcon#about to write, iclass 5, count 0 2006.224.08:03:51.51#ibcon#wrote, iclass 5, count 0 2006.224.08:03:51.51#ibcon#about to read 3, iclass 5, count 0 2006.224.08:03:51.54#ibcon#read 3, iclass 5, count 0 2006.224.08:03:51.54#ibcon#about to read 4, iclass 5, count 0 2006.224.08:03:51.54#ibcon#read 4, iclass 5, count 0 2006.224.08:03:51.54#ibcon#about to read 5, iclass 5, count 0 2006.224.08:03:51.54#ibcon#read 5, iclass 5, count 0 2006.224.08:03:51.54#ibcon#about to read 6, iclass 5, count 0 2006.224.08:03:51.54#ibcon#read 6, iclass 5, count 0 2006.224.08:03:51.54#ibcon#end of sib2, iclass 5, count 0 2006.224.08:03:51.54#ibcon#*after write, iclass 5, count 0 2006.224.08:03:51.54#ibcon#*before return 0, iclass 5, count 0 2006.224.08:03:51.54#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.224.08:03:51.54#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.224.08:03:51.54#ibcon#about to clear, iclass 5 cls_cnt 0 2006.224.08:03:51.54#ibcon#cleared, iclass 5 cls_cnt 0 2006.224.08:03:51.54$vc4f8/vblo=4,712.99 2006.224.08:03:51.54#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.224.08:03:51.54#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.224.08:03:51.54#ibcon#ireg 17 cls_cnt 0 2006.224.08:03:51.54#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.224.08:03:51.54#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.224.08:03:51.54#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.224.08:03:51.54#ibcon#enter wrdev, iclass 7, count 0 2006.224.08:03:51.54#ibcon#first serial, iclass 7, count 0 2006.224.08:03:51.54#ibcon#enter sib2, iclass 7, count 0 2006.224.08:03:51.54#ibcon#flushed, iclass 7, count 0 2006.224.08:03:51.54#ibcon#about to write, iclass 7, count 0 2006.224.08:03:51.54#ibcon#wrote, iclass 7, count 0 2006.224.08:03:51.54#ibcon#about to read 3, iclass 7, count 0 2006.224.08:03:51.56#ibcon#read 3, iclass 7, count 0 2006.224.08:03:51.56#ibcon#about to read 4, iclass 7, count 0 2006.224.08:03:51.56#ibcon#read 4, iclass 7, count 0 2006.224.08:03:51.56#ibcon#about to read 5, iclass 7, count 0 2006.224.08:03:51.56#ibcon#read 5, iclass 7, count 0 2006.224.08:03:51.56#ibcon#about to read 6, iclass 7, count 0 2006.224.08:03:51.56#ibcon#read 6, iclass 7, count 0 2006.224.08:03:51.56#ibcon#end of sib2, iclass 7, count 0 2006.224.08:03:51.56#ibcon#*mode == 0, iclass 7, count 0 2006.224.08:03:51.56#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.224.08:03:51.56#ibcon#[28=FRQ=04,712.99\r\n] 2006.224.08:03:51.56#ibcon#*before write, iclass 7, count 0 2006.224.08:03:51.56#ibcon#enter sib2, iclass 7, count 0 2006.224.08:03:51.56#ibcon#flushed, iclass 7, count 0 2006.224.08:03:51.56#ibcon#about to write, iclass 7, count 0 2006.224.08:03:51.56#ibcon#wrote, iclass 7, count 0 2006.224.08:03:51.56#ibcon#about to read 3, iclass 7, count 0 2006.224.08:03:51.60#ibcon#read 3, iclass 7, count 0 2006.224.08:03:51.60#ibcon#about to read 4, iclass 7, count 0 2006.224.08:03:51.60#ibcon#read 4, iclass 7, count 0 2006.224.08:03:51.60#ibcon#about to read 5, iclass 7, count 0 2006.224.08:03:51.60#ibcon#read 5, iclass 7, count 0 2006.224.08:03:51.60#ibcon#about to read 6, iclass 7, count 0 2006.224.08:03:51.60#ibcon#read 6, iclass 7, count 0 2006.224.08:03:51.60#ibcon#end of sib2, iclass 7, count 0 2006.224.08:03:51.60#ibcon#*after write, iclass 7, count 0 2006.224.08:03:51.60#ibcon#*before return 0, iclass 7, count 0 2006.224.08:03:51.60#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.224.08:03:51.60#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.224.08:03:51.60#ibcon#about to clear, iclass 7 cls_cnt 0 2006.224.08:03:51.60#ibcon#cleared, iclass 7 cls_cnt 0 2006.224.08:03:51.60$vc4f8/vb=4,4 2006.224.08:03:51.60#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.224.08:03:51.60#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.224.08:03:51.60#ibcon#ireg 11 cls_cnt 2 2006.224.08:03:51.60#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.224.08:03:51.66#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.224.08:03:51.66#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.224.08:03:51.66#ibcon#enter wrdev, iclass 11, count 2 2006.224.08:03:51.66#ibcon#first serial, iclass 11, count 2 2006.224.08:03:51.66#ibcon#enter sib2, iclass 11, count 2 2006.224.08:03:51.66#ibcon#flushed, iclass 11, count 2 2006.224.08:03:51.66#ibcon#about to write, iclass 11, count 2 2006.224.08:03:51.66#ibcon#wrote, iclass 11, count 2 2006.224.08:03:51.66#ibcon#about to read 3, iclass 11, count 2 2006.224.08:03:51.68#ibcon#read 3, iclass 11, count 2 2006.224.08:03:51.68#ibcon#about to read 4, iclass 11, count 2 2006.224.08:03:51.68#ibcon#read 4, iclass 11, count 2 2006.224.08:03:51.68#ibcon#about to read 5, iclass 11, count 2 2006.224.08:03:51.68#ibcon#read 5, iclass 11, count 2 2006.224.08:03:51.68#ibcon#about to read 6, iclass 11, count 2 2006.224.08:03:51.68#ibcon#read 6, iclass 11, count 2 2006.224.08:03:51.68#ibcon#end of sib2, iclass 11, count 2 2006.224.08:03:51.68#ibcon#*mode == 0, iclass 11, count 2 2006.224.08:03:51.68#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.224.08:03:51.68#ibcon#[27=AT04-04\r\n] 2006.224.08:03:51.68#ibcon#*before write, iclass 11, count 2 2006.224.08:03:51.68#ibcon#enter sib2, iclass 11, count 2 2006.224.08:03:51.68#ibcon#flushed, iclass 11, count 2 2006.224.08:03:51.68#ibcon#about to write, iclass 11, count 2 2006.224.08:03:51.68#ibcon#wrote, iclass 11, count 2 2006.224.08:03:51.68#ibcon#about to read 3, iclass 11, count 2 2006.224.08:03:51.71#ibcon#read 3, iclass 11, count 2 2006.224.08:03:51.71#ibcon#about to read 4, iclass 11, count 2 2006.224.08:03:51.71#ibcon#read 4, iclass 11, count 2 2006.224.08:03:51.71#ibcon#about to read 5, iclass 11, count 2 2006.224.08:03:51.71#ibcon#read 5, iclass 11, count 2 2006.224.08:03:51.71#ibcon#about to read 6, iclass 11, count 2 2006.224.08:03:51.71#ibcon#read 6, iclass 11, count 2 2006.224.08:03:51.71#ibcon#end of sib2, iclass 11, count 2 2006.224.08:03:51.71#ibcon#*after write, iclass 11, count 2 2006.224.08:03:51.71#ibcon#*before return 0, iclass 11, count 2 2006.224.08:03:51.71#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.224.08:03:51.71#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.224.08:03:51.71#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.224.08:03:51.71#ibcon#ireg 7 cls_cnt 0 2006.224.08:03:51.71#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.224.08:03:51.83#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.224.08:03:51.83#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.224.08:03:51.83#ibcon#enter wrdev, iclass 11, count 0 2006.224.08:03:51.83#ibcon#first serial, iclass 11, count 0 2006.224.08:03:51.83#ibcon#enter sib2, iclass 11, count 0 2006.224.08:03:51.83#ibcon#flushed, iclass 11, count 0 2006.224.08:03:51.83#ibcon#about to write, iclass 11, count 0 2006.224.08:03:51.83#ibcon#wrote, iclass 11, count 0 2006.224.08:03:51.83#ibcon#about to read 3, iclass 11, count 0 2006.224.08:03:51.85#ibcon#read 3, iclass 11, count 0 2006.224.08:03:51.85#ibcon#about to read 4, iclass 11, count 0 2006.224.08:03:51.85#ibcon#read 4, iclass 11, count 0 2006.224.08:03:51.85#ibcon#about to read 5, iclass 11, count 0 2006.224.08:03:51.85#ibcon#read 5, iclass 11, count 0 2006.224.08:03:51.85#ibcon#about to read 6, iclass 11, count 0 2006.224.08:03:51.85#ibcon#read 6, iclass 11, count 0 2006.224.08:03:51.85#ibcon#end of sib2, iclass 11, count 0 2006.224.08:03:51.85#ibcon#*mode == 0, iclass 11, count 0 2006.224.08:03:51.85#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.224.08:03:51.85#ibcon#[27=USB\r\n] 2006.224.08:03:51.85#ibcon#*before write, iclass 11, count 0 2006.224.08:03:51.85#ibcon#enter sib2, iclass 11, count 0 2006.224.08:03:51.85#ibcon#flushed, iclass 11, count 0 2006.224.08:03:51.85#ibcon#about to write, iclass 11, count 0 2006.224.08:03:51.85#ibcon#wrote, iclass 11, count 0 2006.224.08:03:51.85#ibcon#about to read 3, iclass 11, count 0 2006.224.08:03:51.88#ibcon#read 3, iclass 11, count 0 2006.224.08:03:51.88#ibcon#about to read 4, iclass 11, count 0 2006.224.08:03:51.88#ibcon#read 4, iclass 11, count 0 2006.224.08:03:51.88#ibcon#about to read 5, iclass 11, count 0 2006.224.08:03:51.88#ibcon#read 5, iclass 11, count 0 2006.224.08:03:51.88#ibcon#about to read 6, iclass 11, count 0 2006.224.08:03:51.88#ibcon#read 6, iclass 11, count 0 2006.224.08:03:51.88#ibcon#end of sib2, iclass 11, count 0 2006.224.08:03:51.88#ibcon#*after write, iclass 11, count 0 2006.224.08:03:51.88#ibcon#*before return 0, iclass 11, count 0 2006.224.08:03:51.88#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.224.08:03:51.88#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.224.08:03:51.88#ibcon#about to clear, iclass 11 cls_cnt 0 2006.224.08:03:51.88#ibcon#cleared, iclass 11 cls_cnt 0 2006.224.08:03:51.88$vc4f8/vblo=5,744.99 2006.224.08:03:51.88#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.224.08:03:51.88#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.224.08:03:51.88#ibcon#ireg 17 cls_cnt 0 2006.224.08:03:51.88#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.224.08:03:51.88#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.224.08:03:51.88#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.224.08:03:51.88#ibcon#enter wrdev, iclass 13, count 0 2006.224.08:03:51.88#ibcon#first serial, iclass 13, count 0 2006.224.08:03:51.88#ibcon#enter sib2, iclass 13, count 0 2006.224.08:03:51.88#ibcon#flushed, iclass 13, count 0 2006.224.08:03:51.88#ibcon#about to write, iclass 13, count 0 2006.224.08:03:51.88#ibcon#wrote, iclass 13, count 0 2006.224.08:03:51.88#ibcon#about to read 3, iclass 13, count 0 2006.224.08:03:51.90#ibcon#read 3, iclass 13, count 0 2006.224.08:03:51.90#ibcon#about to read 4, iclass 13, count 0 2006.224.08:03:51.90#ibcon#read 4, iclass 13, count 0 2006.224.08:03:51.90#ibcon#about to read 5, iclass 13, count 0 2006.224.08:03:51.90#ibcon#read 5, iclass 13, count 0 2006.224.08:03:51.90#ibcon#about to read 6, iclass 13, count 0 2006.224.08:03:51.90#ibcon#read 6, iclass 13, count 0 2006.224.08:03:51.90#ibcon#end of sib2, iclass 13, count 0 2006.224.08:03:51.90#ibcon#*mode == 0, iclass 13, count 0 2006.224.08:03:51.90#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.224.08:03:51.90#ibcon#[28=FRQ=05,744.99\r\n] 2006.224.08:03:51.90#ibcon#*before write, iclass 13, count 0 2006.224.08:03:51.90#ibcon#enter sib2, iclass 13, count 0 2006.224.08:03:51.90#ibcon#flushed, iclass 13, count 0 2006.224.08:03:51.90#ibcon#about to write, iclass 13, count 0 2006.224.08:03:51.90#ibcon#wrote, iclass 13, count 0 2006.224.08:03:51.90#ibcon#about to read 3, iclass 13, count 0 2006.224.08:03:51.94#ibcon#read 3, iclass 13, count 0 2006.224.08:03:51.94#ibcon#about to read 4, iclass 13, count 0 2006.224.08:03:51.94#ibcon#read 4, iclass 13, count 0 2006.224.08:03:51.94#ibcon#about to read 5, iclass 13, count 0 2006.224.08:03:51.94#ibcon#read 5, iclass 13, count 0 2006.224.08:03:51.94#ibcon#about to read 6, iclass 13, count 0 2006.224.08:03:51.94#ibcon#read 6, iclass 13, count 0 2006.224.08:03:51.94#ibcon#end of sib2, iclass 13, count 0 2006.224.08:03:51.94#ibcon#*after write, iclass 13, count 0 2006.224.08:03:51.94#ibcon#*before return 0, iclass 13, count 0 2006.224.08:03:51.94#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.224.08:03:51.94#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.224.08:03:51.94#ibcon#about to clear, iclass 13 cls_cnt 0 2006.224.08:03:51.94#ibcon#cleared, iclass 13 cls_cnt 0 2006.224.08:03:51.94$vc4f8/vb=5,4 2006.224.08:03:51.94#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.224.08:03:51.94#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.224.08:03:51.94#ibcon#ireg 11 cls_cnt 2 2006.224.08:03:51.94#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.224.08:03:52.00#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.224.08:03:52.00#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.224.08:03:52.00#ibcon#enter wrdev, iclass 15, count 2 2006.224.08:03:52.00#ibcon#first serial, iclass 15, count 2 2006.224.08:03:52.00#ibcon#enter sib2, iclass 15, count 2 2006.224.08:03:52.00#ibcon#flushed, iclass 15, count 2 2006.224.08:03:52.00#ibcon#about to write, iclass 15, count 2 2006.224.08:03:52.00#ibcon#wrote, iclass 15, count 2 2006.224.08:03:52.00#ibcon#about to read 3, iclass 15, count 2 2006.224.08:03:52.02#ibcon#read 3, iclass 15, count 2 2006.224.08:03:52.02#ibcon#about to read 4, iclass 15, count 2 2006.224.08:03:52.02#ibcon#read 4, iclass 15, count 2 2006.224.08:03:52.02#ibcon#about to read 5, iclass 15, count 2 2006.224.08:03:52.02#ibcon#read 5, iclass 15, count 2 2006.224.08:03:52.02#ibcon#about to read 6, iclass 15, count 2 2006.224.08:03:52.02#ibcon#read 6, iclass 15, count 2 2006.224.08:03:52.02#ibcon#end of sib2, iclass 15, count 2 2006.224.08:03:52.02#ibcon#*mode == 0, iclass 15, count 2 2006.224.08:03:52.02#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.224.08:03:52.02#ibcon#[27=AT05-04\r\n] 2006.224.08:03:52.02#ibcon#*before write, iclass 15, count 2 2006.224.08:03:52.02#ibcon#enter sib2, iclass 15, count 2 2006.224.08:03:52.02#ibcon#flushed, iclass 15, count 2 2006.224.08:03:52.02#ibcon#about to write, iclass 15, count 2 2006.224.08:03:52.02#ibcon#wrote, iclass 15, count 2 2006.224.08:03:52.02#ibcon#about to read 3, iclass 15, count 2 2006.224.08:03:52.05#ibcon#read 3, iclass 15, count 2 2006.224.08:03:52.05#ibcon#about to read 4, iclass 15, count 2 2006.224.08:03:52.05#ibcon#read 4, iclass 15, count 2 2006.224.08:03:52.05#ibcon#about to read 5, iclass 15, count 2 2006.224.08:03:52.05#ibcon#read 5, iclass 15, count 2 2006.224.08:03:52.05#ibcon#about to read 6, iclass 15, count 2 2006.224.08:03:52.05#ibcon#read 6, iclass 15, count 2 2006.224.08:03:52.05#ibcon#end of sib2, iclass 15, count 2 2006.224.08:03:52.05#ibcon#*after write, iclass 15, count 2 2006.224.08:03:52.05#ibcon#*before return 0, iclass 15, count 2 2006.224.08:03:52.05#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.224.08:03:52.05#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.224.08:03:52.05#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.224.08:03:52.05#ibcon#ireg 7 cls_cnt 0 2006.224.08:03:52.05#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.224.08:03:52.17#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.224.08:03:52.17#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.224.08:03:52.17#ibcon#enter wrdev, iclass 15, count 0 2006.224.08:03:52.17#ibcon#first serial, iclass 15, count 0 2006.224.08:03:52.17#ibcon#enter sib2, iclass 15, count 0 2006.224.08:03:52.17#ibcon#flushed, iclass 15, count 0 2006.224.08:03:52.17#ibcon#about to write, iclass 15, count 0 2006.224.08:03:52.17#ibcon#wrote, iclass 15, count 0 2006.224.08:03:52.17#ibcon#about to read 3, iclass 15, count 0 2006.224.08:03:52.19#ibcon#read 3, iclass 15, count 0 2006.224.08:03:52.19#ibcon#about to read 4, iclass 15, count 0 2006.224.08:03:52.19#ibcon#read 4, iclass 15, count 0 2006.224.08:03:52.19#ibcon#about to read 5, iclass 15, count 0 2006.224.08:03:52.19#ibcon#read 5, iclass 15, count 0 2006.224.08:03:52.19#ibcon#about to read 6, iclass 15, count 0 2006.224.08:03:52.19#ibcon#read 6, iclass 15, count 0 2006.224.08:03:52.19#ibcon#end of sib2, iclass 15, count 0 2006.224.08:03:52.19#ibcon#*mode == 0, iclass 15, count 0 2006.224.08:03:52.19#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.224.08:03:52.19#ibcon#[27=USB\r\n] 2006.224.08:03:52.19#ibcon#*before write, iclass 15, count 0 2006.224.08:03:52.19#ibcon#enter sib2, iclass 15, count 0 2006.224.08:03:52.19#ibcon#flushed, iclass 15, count 0 2006.224.08:03:52.19#ibcon#about to write, iclass 15, count 0 2006.224.08:03:52.19#ibcon#wrote, iclass 15, count 0 2006.224.08:03:52.19#ibcon#about to read 3, iclass 15, count 0 2006.224.08:03:52.22#ibcon#read 3, iclass 15, count 0 2006.224.08:03:52.22#ibcon#about to read 4, iclass 15, count 0 2006.224.08:03:52.22#ibcon#read 4, iclass 15, count 0 2006.224.08:03:52.22#ibcon#about to read 5, iclass 15, count 0 2006.224.08:03:52.22#ibcon#read 5, iclass 15, count 0 2006.224.08:03:52.22#ibcon#about to read 6, iclass 15, count 0 2006.224.08:03:52.22#ibcon#read 6, iclass 15, count 0 2006.224.08:03:52.22#ibcon#end of sib2, iclass 15, count 0 2006.224.08:03:52.22#ibcon#*after write, iclass 15, count 0 2006.224.08:03:52.22#ibcon#*before return 0, iclass 15, count 0 2006.224.08:03:52.22#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.224.08:03:52.22#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.224.08:03:52.22#ibcon#about to clear, iclass 15 cls_cnt 0 2006.224.08:03:52.22#ibcon#cleared, iclass 15 cls_cnt 0 2006.224.08:03:52.22$vc4f8/vblo=6,752.99 2006.224.08:03:52.22#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.224.08:03:52.22#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.224.08:03:52.22#ibcon#ireg 17 cls_cnt 0 2006.224.08:03:52.22#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.224.08:03:52.22#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.224.08:03:52.22#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.224.08:03:52.22#ibcon#enter wrdev, iclass 17, count 0 2006.224.08:03:52.22#ibcon#first serial, iclass 17, count 0 2006.224.08:03:52.22#ibcon#enter sib2, iclass 17, count 0 2006.224.08:03:52.22#ibcon#flushed, iclass 17, count 0 2006.224.08:03:52.22#ibcon#about to write, iclass 17, count 0 2006.224.08:03:52.22#ibcon#wrote, iclass 17, count 0 2006.224.08:03:52.22#ibcon#about to read 3, iclass 17, count 0 2006.224.08:03:52.24#ibcon#read 3, iclass 17, count 0 2006.224.08:03:52.24#ibcon#about to read 4, iclass 17, count 0 2006.224.08:03:52.24#ibcon#read 4, iclass 17, count 0 2006.224.08:03:52.24#ibcon#about to read 5, iclass 17, count 0 2006.224.08:03:52.24#ibcon#read 5, iclass 17, count 0 2006.224.08:03:52.24#ibcon#about to read 6, iclass 17, count 0 2006.224.08:03:52.24#ibcon#read 6, iclass 17, count 0 2006.224.08:03:52.24#ibcon#end of sib2, iclass 17, count 0 2006.224.08:03:52.24#ibcon#*mode == 0, iclass 17, count 0 2006.224.08:03:52.24#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.224.08:03:52.24#ibcon#[28=FRQ=06,752.99\r\n] 2006.224.08:03:52.24#ibcon#*before write, iclass 17, count 0 2006.224.08:03:52.24#ibcon#enter sib2, iclass 17, count 0 2006.224.08:03:52.24#ibcon#flushed, iclass 17, count 0 2006.224.08:03:52.24#ibcon#about to write, iclass 17, count 0 2006.224.08:03:52.24#ibcon#wrote, iclass 17, count 0 2006.224.08:03:52.24#ibcon#about to read 3, iclass 17, count 0 2006.224.08:03:52.28#ibcon#read 3, iclass 17, count 0 2006.224.08:03:52.28#ibcon#about to read 4, iclass 17, count 0 2006.224.08:03:52.28#ibcon#read 4, iclass 17, count 0 2006.224.08:03:52.28#ibcon#about to read 5, iclass 17, count 0 2006.224.08:03:52.28#ibcon#read 5, iclass 17, count 0 2006.224.08:03:52.28#ibcon#about to read 6, iclass 17, count 0 2006.224.08:03:52.28#ibcon#read 6, iclass 17, count 0 2006.224.08:03:52.28#ibcon#end of sib2, iclass 17, count 0 2006.224.08:03:52.28#ibcon#*after write, iclass 17, count 0 2006.224.08:03:52.28#ibcon#*before return 0, iclass 17, count 0 2006.224.08:03:52.28#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.224.08:03:52.28#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.224.08:03:52.28#ibcon#about to clear, iclass 17 cls_cnt 0 2006.224.08:03:52.28#ibcon#cleared, iclass 17 cls_cnt 0 2006.224.08:03:52.28$vc4f8/vb=6,4 2006.224.08:03:52.28#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.224.08:03:52.28#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.224.08:03:52.28#ibcon#ireg 11 cls_cnt 2 2006.224.08:03:52.28#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.224.08:03:52.34#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.224.08:03:52.34#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.224.08:03:52.34#ibcon#enter wrdev, iclass 19, count 2 2006.224.08:03:52.34#ibcon#first serial, iclass 19, count 2 2006.224.08:03:52.34#ibcon#enter sib2, iclass 19, count 2 2006.224.08:03:52.34#ibcon#flushed, iclass 19, count 2 2006.224.08:03:52.34#ibcon#about to write, iclass 19, count 2 2006.224.08:03:52.34#ibcon#wrote, iclass 19, count 2 2006.224.08:03:52.34#ibcon#about to read 3, iclass 19, count 2 2006.224.08:03:52.36#ibcon#read 3, iclass 19, count 2 2006.224.08:03:52.36#ibcon#about to read 4, iclass 19, count 2 2006.224.08:03:52.36#ibcon#read 4, iclass 19, count 2 2006.224.08:03:52.36#ibcon#about to read 5, iclass 19, count 2 2006.224.08:03:52.36#ibcon#read 5, iclass 19, count 2 2006.224.08:03:52.36#ibcon#about to read 6, iclass 19, count 2 2006.224.08:03:52.36#ibcon#read 6, iclass 19, count 2 2006.224.08:03:52.36#ibcon#end of sib2, iclass 19, count 2 2006.224.08:03:52.36#ibcon#*mode == 0, iclass 19, count 2 2006.224.08:03:52.36#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.224.08:03:52.36#ibcon#[27=AT06-04\r\n] 2006.224.08:03:52.36#ibcon#*before write, iclass 19, count 2 2006.224.08:03:52.36#ibcon#enter sib2, iclass 19, count 2 2006.224.08:03:52.36#ibcon#flushed, iclass 19, count 2 2006.224.08:03:52.36#ibcon#about to write, iclass 19, count 2 2006.224.08:03:52.36#ibcon#wrote, iclass 19, count 2 2006.224.08:03:52.36#ibcon#about to read 3, iclass 19, count 2 2006.224.08:03:52.39#ibcon#read 3, iclass 19, count 2 2006.224.08:03:52.39#ibcon#about to read 4, iclass 19, count 2 2006.224.08:03:52.39#ibcon#read 4, iclass 19, count 2 2006.224.08:03:52.39#ibcon#about to read 5, iclass 19, count 2 2006.224.08:03:52.39#ibcon#read 5, iclass 19, count 2 2006.224.08:03:52.39#ibcon#about to read 6, iclass 19, count 2 2006.224.08:03:52.39#ibcon#read 6, iclass 19, count 2 2006.224.08:03:52.39#ibcon#end of sib2, iclass 19, count 2 2006.224.08:03:52.39#ibcon#*after write, iclass 19, count 2 2006.224.08:03:52.39#ibcon#*before return 0, iclass 19, count 2 2006.224.08:03:52.39#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.224.08:03:52.39#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.224.08:03:52.39#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.224.08:03:52.39#ibcon#ireg 7 cls_cnt 0 2006.224.08:03:52.39#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.224.08:03:52.51#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.224.08:03:52.51#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.224.08:03:52.51#ibcon#enter wrdev, iclass 19, count 0 2006.224.08:03:52.51#ibcon#first serial, iclass 19, count 0 2006.224.08:03:52.51#ibcon#enter sib2, iclass 19, count 0 2006.224.08:03:52.51#ibcon#flushed, iclass 19, count 0 2006.224.08:03:52.51#ibcon#about to write, iclass 19, count 0 2006.224.08:03:52.51#ibcon#wrote, iclass 19, count 0 2006.224.08:03:52.51#ibcon#about to read 3, iclass 19, count 0 2006.224.08:03:52.53#ibcon#read 3, iclass 19, count 0 2006.224.08:03:52.53#ibcon#about to read 4, iclass 19, count 0 2006.224.08:03:52.53#ibcon#read 4, iclass 19, count 0 2006.224.08:03:52.53#ibcon#about to read 5, iclass 19, count 0 2006.224.08:03:52.53#ibcon#read 5, iclass 19, count 0 2006.224.08:03:52.53#ibcon#about to read 6, iclass 19, count 0 2006.224.08:03:52.53#ibcon#read 6, iclass 19, count 0 2006.224.08:03:52.53#ibcon#end of sib2, iclass 19, count 0 2006.224.08:03:52.53#ibcon#*mode == 0, iclass 19, count 0 2006.224.08:03:52.53#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.224.08:03:52.53#ibcon#[27=USB\r\n] 2006.224.08:03:52.53#ibcon#*before write, iclass 19, count 0 2006.224.08:03:52.53#ibcon#enter sib2, iclass 19, count 0 2006.224.08:03:52.53#ibcon#flushed, iclass 19, count 0 2006.224.08:03:52.53#ibcon#about to write, iclass 19, count 0 2006.224.08:03:52.53#ibcon#wrote, iclass 19, count 0 2006.224.08:03:52.53#ibcon#about to read 3, iclass 19, count 0 2006.224.08:03:52.56#ibcon#read 3, iclass 19, count 0 2006.224.08:03:52.56#ibcon#about to read 4, iclass 19, count 0 2006.224.08:03:52.56#ibcon#read 4, iclass 19, count 0 2006.224.08:03:52.56#ibcon#about to read 5, iclass 19, count 0 2006.224.08:03:52.56#ibcon#read 5, iclass 19, count 0 2006.224.08:03:52.56#ibcon#about to read 6, iclass 19, count 0 2006.224.08:03:52.56#ibcon#read 6, iclass 19, count 0 2006.224.08:03:52.56#ibcon#end of sib2, iclass 19, count 0 2006.224.08:03:52.56#ibcon#*after write, iclass 19, count 0 2006.224.08:03:52.56#ibcon#*before return 0, iclass 19, count 0 2006.224.08:03:52.56#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.224.08:03:52.56#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.224.08:03:52.56#ibcon#about to clear, iclass 19 cls_cnt 0 2006.224.08:03:52.56#ibcon#cleared, iclass 19 cls_cnt 0 2006.224.08:03:52.56$vc4f8/vabw=wide 2006.224.08:03:52.56#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.224.08:03:52.56#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.224.08:03:52.56#ibcon#ireg 8 cls_cnt 0 2006.224.08:03:52.56#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.224.08:03:52.56#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.224.08:03:52.56#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.224.08:03:52.56#ibcon#enter wrdev, iclass 21, count 0 2006.224.08:03:52.56#ibcon#first serial, iclass 21, count 0 2006.224.08:03:52.56#ibcon#enter sib2, iclass 21, count 0 2006.224.08:03:52.56#ibcon#flushed, iclass 21, count 0 2006.224.08:03:52.56#ibcon#about to write, iclass 21, count 0 2006.224.08:03:52.56#ibcon#wrote, iclass 21, count 0 2006.224.08:03:52.56#ibcon#about to read 3, iclass 21, count 0 2006.224.08:03:52.58#ibcon#read 3, iclass 21, count 0 2006.224.08:03:52.58#ibcon#about to read 4, iclass 21, count 0 2006.224.08:03:52.58#ibcon#read 4, iclass 21, count 0 2006.224.08:03:52.58#ibcon#about to read 5, iclass 21, count 0 2006.224.08:03:52.58#ibcon#read 5, iclass 21, count 0 2006.224.08:03:52.58#ibcon#about to read 6, iclass 21, count 0 2006.224.08:03:52.58#ibcon#read 6, iclass 21, count 0 2006.224.08:03:52.58#ibcon#end of sib2, iclass 21, count 0 2006.224.08:03:52.58#ibcon#*mode == 0, iclass 21, count 0 2006.224.08:03:52.58#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.224.08:03:52.58#ibcon#[25=BW32\r\n] 2006.224.08:03:52.58#ibcon#*before write, iclass 21, count 0 2006.224.08:03:52.58#ibcon#enter sib2, iclass 21, count 0 2006.224.08:03:52.58#ibcon#flushed, iclass 21, count 0 2006.224.08:03:52.58#ibcon#about to write, iclass 21, count 0 2006.224.08:03:52.58#ibcon#wrote, iclass 21, count 0 2006.224.08:03:52.58#ibcon#about to read 3, iclass 21, count 0 2006.224.08:03:52.61#ibcon#read 3, iclass 21, count 0 2006.224.08:03:52.61#ibcon#about to read 4, iclass 21, count 0 2006.224.08:03:52.61#ibcon#read 4, iclass 21, count 0 2006.224.08:03:52.61#ibcon#about to read 5, iclass 21, count 0 2006.224.08:03:52.61#ibcon#read 5, iclass 21, count 0 2006.224.08:03:52.61#ibcon#about to read 6, iclass 21, count 0 2006.224.08:03:52.61#ibcon#read 6, iclass 21, count 0 2006.224.08:03:52.61#ibcon#end of sib2, iclass 21, count 0 2006.224.08:03:52.61#ibcon#*after write, iclass 21, count 0 2006.224.08:03:52.61#ibcon#*before return 0, iclass 21, count 0 2006.224.08:03:52.61#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.224.08:03:52.61#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.224.08:03:52.61#ibcon#about to clear, iclass 21 cls_cnt 0 2006.224.08:03:52.61#ibcon#cleared, iclass 21 cls_cnt 0 2006.224.08:03:52.61$vc4f8/vbbw=wide 2006.224.08:03:52.61#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.224.08:03:52.61#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.224.08:03:52.61#ibcon#ireg 8 cls_cnt 0 2006.224.08:03:52.61#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.224.08:03:52.68#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.224.08:03:52.68#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.224.08:03:52.68#ibcon#enter wrdev, iclass 23, count 0 2006.224.08:03:52.68#ibcon#first serial, iclass 23, count 0 2006.224.08:03:52.68#ibcon#enter sib2, iclass 23, count 0 2006.224.08:03:52.68#ibcon#flushed, iclass 23, count 0 2006.224.08:03:52.68#ibcon#about to write, iclass 23, count 0 2006.224.08:03:52.68#ibcon#wrote, iclass 23, count 0 2006.224.08:03:52.68#ibcon#about to read 3, iclass 23, count 0 2006.224.08:03:52.70#ibcon#read 3, iclass 23, count 0 2006.224.08:03:52.70#ibcon#about to read 4, iclass 23, count 0 2006.224.08:03:52.70#ibcon#read 4, iclass 23, count 0 2006.224.08:03:52.70#ibcon#about to read 5, iclass 23, count 0 2006.224.08:03:52.70#ibcon#read 5, iclass 23, count 0 2006.224.08:03:52.70#ibcon#about to read 6, iclass 23, count 0 2006.224.08:03:52.70#ibcon#read 6, iclass 23, count 0 2006.224.08:03:52.70#ibcon#end of sib2, iclass 23, count 0 2006.224.08:03:52.70#ibcon#*mode == 0, iclass 23, count 0 2006.224.08:03:52.70#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.224.08:03:52.70#ibcon#[27=BW32\r\n] 2006.224.08:03:52.70#ibcon#*before write, iclass 23, count 0 2006.224.08:03:52.70#ibcon#enter sib2, iclass 23, count 0 2006.224.08:03:52.70#ibcon#flushed, iclass 23, count 0 2006.224.08:03:52.70#ibcon#about to write, iclass 23, count 0 2006.224.08:03:52.70#ibcon#wrote, iclass 23, count 0 2006.224.08:03:52.70#ibcon#about to read 3, iclass 23, count 0 2006.224.08:03:52.73#ibcon#read 3, iclass 23, count 0 2006.224.08:03:52.73#ibcon#about to read 4, iclass 23, count 0 2006.224.08:03:52.73#ibcon#read 4, iclass 23, count 0 2006.224.08:03:52.73#ibcon#about to read 5, iclass 23, count 0 2006.224.08:03:52.73#ibcon#read 5, iclass 23, count 0 2006.224.08:03:52.73#ibcon#about to read 6, iclass 23, count 0 2006.224.08:03:52.73#ibcon#read 6, iclass 23, count 0 2006.224.08:03:52.73#ibcon#end of sib2, iclass 23, count 0 2006.224.08:03:52.73#ibcon#*after write, iclass 23, count 0 2006.224.08:03:52.73#ibcon#*before return 0, iclass 23, count 0 2006.224.08:03:52.73#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.224.08:03:52.73#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.224.08:03:52.73#ibcon#about to clear, iclass 23 cls_cnt 0 2006.224.08:03:52.73#ibcon#cleared, iclass 23 cls_cnt 0 2006.224.08:03:52.73$4f8m12a/ifd4f 2006.224.08:03:52.73$ifd4f/lo= 2006.224.08:03:52.73$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.224.08:03:52.73$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.224.08:03:52.73$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.224.08:03:52.73$ifd4f/patch= 2006.224.08:03:52.73$ifd4f/patch=lo1,a1,a2,a3,a4 2006.224.08:03:52.73$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.224.08:03:52.73$ifd4f/patch=lo3,a5,a6,a7,a8 2006.224.08:03:52.73$4f8m12a/"form=m,16.000,1:2 2006.224.08:03:52.73$4f8m12a/"tpicd 2006.224.08:03:52.73$4f8m12a/echo=off 2006.224.08:03:52.73$4f8m12a/xlog=off 2006.224.08:03:52.73:!2006.224.08:04:20 2006.224.08:04:04.14#trakl#Source acquired 2006.224.08:04:05.14#flagr#flagr/antenna,acquired 2006.224.08:04:20.00:preob 2006.224.08:04:21.14/onsource/TRACKING 2006.224.08:04:21.14:!2006.224.08:04:30 2006.224.08:04:30.00:data_valid=on 2006.224.08:04:30.00:midob 2006.224.08:04:30.14/onsource/TRACKING 2006.224.08:04:30.14/wx/23.64,1004.7,100 2006.224.08:04:30.22/cable/+6.4363E-03 2006.224.08:04:31.31/va/01,08,usb,yes,43,45 2006.224.08:04:31.31/va/02,07,usb,yes,43,45 2006.224.08:04:31.31/va/03,06,usb,yes,46,46 2006.224.08:04:31.31/va/04,07,usb,yes,45,49 2006.224.08:04:31.31/va/05,07,usb,yes,52,55 2006.224.08:04:31.31/va/06,06,usb,yes,52,51 2006.224.08:04:31.31/va/07,06,usb,yes,53,52 2006.224.08:04:31.31/va/08,07,usb,yes,50,49 2006.224.08:04:31.54/valo/01,532.99,yes,locked 2006.224.08:04:31.54/valo/02,572.99,yes,locked 2006.224.08:04:31.54/valo/03,672.99,yes,locked 2006.224.08:04:31.54/valo/04,832.99,yes,locked 2006.224.08:04:31.54/valo/05,652.99,yes,locked 2006.224.08:04:31.54/valo/06,772.99,yes,locked 2006.224.08:04:31.54/valo/07,832.99,yes,locked 2006.224.08:04:31.54/valo/08,852.99,yes,locked 2006.224.08:04:32.63/vb/01,04,usb,yes,32,30 2006.224.08:04:32.63/vb/02,04,usb,yes,33,35 2006.224.08:04:32.63/vb/03,04,usb,yes,30,34 2006.224.08:04:32.63/vb/04,04,usb,yes,31,31 2006.224.08:04:32.63/vb/05,04,usb,yes,29,33 2006.224.08:04:32.63/vb/06,04,usb,yes,30,33 2006.224.08:04:32.63/vb/07,04,usb,yes,32,32 2006.224.08:04:32.63/vb/08,04,usb,yes,30,33 2006.224.08:04:32.86/vblo/01,632.99,yes,locked 2006.224.08:04:32.86/vblo/02,640.99,yes,locked 2006.224.08:04:32.86/vblo/03,656.99,yes,locked 2006.224.08:04:32.86/vblo/04,712.99,yes,locked 2006.224.08:04:32.86/vblo/05,744.99,yes,locked 2006.224.08:04:32.86/vblo/06,752.99,yes,locked 2006.224.08:04:32.86/vblo/07,734.99,yes,locked 2006.224.08:04:32.86/vblo/08,744.99,yes,locked 2006.224.08:04:33.01/vabw/8 2006.224.08:04:33.16/vbbw/8 2006.224.08:04:33.25/xfe/off,on,15.5 2006.224.08:04:33.63/ifatt/23,28,28,28 2006.224.08:04:34.07/fmout-gps/S +4.42E-07 2006.224.08:04:34.11:!2006.224.08:05:30 2006.224.08:05:30.01:data_valid=off 2006.224.08:05:30.01:postob 2006.224.08:05:30.14/cable/+6.4340E-03 2006.224.08:05:30.14/wx/23.65,1004.8,100 2006.224.08:05:31.07/fmout-gps/S +4.44E-07 2006.224.08:05:31.07:scan_name=224-0806,k06224,60 2006.224.08:05:31.08:source=1803+784,180045.68,782804.0,2000.0,cw 2006.224.08:05:31.14#flagr#flagr/antenna,new-source 2006.224.08:05:32.14:checkk5 2006.224.08:05:32.50/chk_autoobs//k5ts1/ autoobs is running! 2006.224.08:05:32.88/chk_autoobs//k5ts2/ autoobs is running! 2006.224.08:05:33.26/chk_autoobs//k5ts3/ autoobs is running! 2006.224.08:05:33.63/chk_autoobs//k5ts4/ autoobs is running! 2006.224.08:05:33.99/chk_obsdata//k5ts1/T2240804??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.08:05:34.35/chk_obsdata//k5ts2/T2240804??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.08:05:34.72/chk_obsdata//k5ts3/T2240804??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.08:05:35.08/chk_obsdata//k5ts4/T2240804??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.08:05:35.77/k5log//k5ts1_log_newline 2006.224.08:05:36.45/k5log//k5ts2_log_newline 2006.224.08:05:37.14/k5log//k5ts3_log_newline 2006.224.08:05:37.82/k5log//k5ts4_log_newline 2006.224.08:05:37.85/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.224.08:05:37.85:4f8m12a=2 2006.224.08:05:37.85$4f8m12a/echo=on 2006.224.08:05:37.85$4f8m12a/pcalon 2006.224.08:05:37.85$pcalon/"no phase cal control is implemented here 2006.224.08:05:37.85$4f8m12a/"tpicd=stop 2006.224.08:05:37.85$4f8m12a/vc4f8 2006.224.08:05:37.85$vc4f8/valo=1,532.99 2006.224.08:05:37.85#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.224.08:05:37.85#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.224.08:05:37.85#ibcon#ireg 17 cls_cnt 0 2006.224.08:05:37.85#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.224.08:05:37.85#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.224.08:05:37.85#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.224.08:05:37.85#ibcon#enter wrdev, iclass 30, count 0 2006.224.08:05:37.85#ibcon#first serial, iclass 30, count 0 2006.224.08:05:37.85#ibcon#enter sib2, iclass 30, count 0 2006.224.08:05:37.85#ibcon#flushed, iclass 30, count 0 2006.224.08:05:37.85#ibcon#about to write, iclass 30, count 0 2006.224.08:05:37.85#ibcon#wrote, iclass 30, count 0 2006.224.08:05:37.85#ibcon#about to read 3, iclass 30, count 0 2006.224.08:05:37.89#ibcon#read 3, iclass 30, count 0 2006.224.08:05:37.89#ibcon#about to read 4, iclass 30, count 0 2006.224.08:05:37.89#ibcon#read 4, iclass 30, count 0 2006.224.08:05:37.89#ibcon#about to read 5, iclass 30, count 0 2006.224.08:05:37.89#ibcon#read 5, iclass 30, count 0 2006.224.08:05:37.89#ibcon#about to read 6, iclass 30, count 0 2006.224.08:05:37.89#ibcon#read 6, iclass 30, count 0 2006.224.08:05:37.89#ibcon#end of sib2, iclass 30, count 0 2006.224.08:05:37.89#ibcon#*mode == 0, iclass 30, count 0 2006.224.08:05:37.89#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.224.08:05:37.89#ibcon#[26=FRQ=01,532.99\r\n] 2006.224.08:05:37.89#ibcon#*before write, iclass 30, count 0 2006.224.08:05:37.89#ibcon#enter sib2, iclass 30, count 0 2006.224.08:05:37.89#ibcon#flushed, iclass 30, count 0 2006.224.08:05:37.89#ibcon#about to write, iclass 30, count 0 2006.224.08:05:37.89#ibcon#wrote, iclass 30, count 0 2006.224.08:05:37.89#ibcon#about to read 3, iclass 30, count 0 2006.224.08:05:37.94#ibcon#read 3, iclass 30, count 0 2006.224.08:05:37.94#ibcon#about to read 4, iclass 30, count 0 2006.224.08:05:37.94#ibcon#read 4, iclass 30, count 0 2006.224.08:05:37.94#ibcon#about to read 5, iclass 30, count 0 2006.224.08:05:37.94#ibcon#read 5, iclass 30, count 0 2006.224.08:05:37.94#ibcon#about to read 6, iclass 30, count 0 2006.224.08:05:37.94#ibcon#read 6, iclass 30, count 0 2006.224.08:05:37.94#ibcon#end of sib2, iclass 30, count 0 2006.224.08:05:37.94#ibcon#*after write, iclass 30, count 0 2006.224.08:05:37.94#ibcon#*before return 0, iclass 30, count 0 2006.224.08:05:37.94#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.224.08:05:37.94#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.224.08:05:37.94#ibcon#about to clear, iclass 30 cls_cnt 0 2006.224.08:05:37.94#ibcon#cleared, iclass 30 cls_cnt 0 2006.224.08:05:37.94$vc4f8/va=1,8 2006.224.08:05:37.94#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.224.08:05:37.94#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.224.08:05:37.94#ibcon#ireg 11 cls_cnt 2 2006.224.08:05:37.94#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.224.08:05:37.94#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.224.08:05:37.94#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.224.08:05:37.94#ibcon#enter wrdev, iclass 32, count 2 2006.224.08:05:37.94#ibcon#first serial, iclass 32, count 2 2006.224.08:05:37.94#ibcon#enter sib2, iclass 32, count 2 2006.224.08:05:37.94#ibcon#flushed, iclass 32, count 2 2006.224.08:05:37.94#ibcon#about to write, iclass 32, count 2 2006.224.08:05:37.94#ibcon#wrote, iclass 32, count 2 2006.224.08:05:37.94#ibcon#about to read 3, iclass 32, count 2 2006.224.08:05:37.96#ibcon#read 3, iclass 32, count 2 2006.224.08:05:37.96#ibcon#about to read 4, iclass 32, count 2 2006.224.08:05:37.96#ibcon#read 4, iclass 32, count 2 2006.224.08:05:37.96#ibcon#about to read 5, iclass 32, count 2 2006.224.08:05:37.96#ibcon#read 5, iclass 32, count 2 2006.224.08:05:37.96#ibcon#about to read 6, iclass 32, count 2 2006.224.08:05:37.96#ibcon#read 6, iclass 32, count 2 2006.224.08:05:37.96#ibcon#end of sib2, iclass 32, count 2 2006.224.08:05:37.96#ibcon#*mode == 0, iclass 32, count 2 2006.224.08:05:37.96#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.224.08:05:37.97#ibcon#[25=AT01-08\r\n] 2006.224.08:05:37.97#ibcon#*before write, iclass 32, count 2 2006.224.08:05:37.97#ibcon#enter sib2, iclass 32, count 2 2006.224.08:05:37.97#ibcon#flushed, iclass 32, count 2 2006.224.08:05:37.97#ibcon#about to write, iclass 32, count 2 2006.224.08:05:37.97#ibcon#wrote, iclass 32, count 2 2006.224.08:05:37.97#ibcon#about to read 3, iclass 32, count 2 2006.224.08:05:38.00#ibcon#read 3, iclass 32, count 2 2006.224.08:05:38.00#ibcon#about to read 4, iclass 32, count 2 2006.224.08:05:38.00#ibcon#read 4, iclass 32, count 2 2006.224.08:05:38.00#ibcon#about to read 5, iclass 32, count 2 2006.224.08:05:38.00#ibcon#read 5, iclass 32, count 2 2006.224.08:05:38.00#ibcon#about to read 6, iclass 32, count 2 2006.224.08:05:38.00#ibcon#read 6, iclass 32, count 2 2006.224.08:05:38.00#ibcon#end of sib2, iclass 32, count 2 2006.224.08:05:38.00#ibcon#*after write, iclass 32, count 2 2006.224.08:05:38.00#ibcon#*before return 0, iclass 32, count 2 2006.224.08:05:38.00#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.224.08:05:38.00#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.224.08:05:38.00#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.224.08:05:38.00#ibcon#ireg 7 cls_cnt 0 2006.224.08:05:38.00#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.224.08:05:38.12#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.224.08:05:38.12#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.224.08:05:38.12#ibcon#enter wrdev, iclass 32, count 0 2006.224.08:05:38.12#ibcon#first serial, iclass 32, count 0 2006.224.08:05:38.12#ibcon#enter sib2, iclass 32, count 0 2006.224.08:05:38.12#ibcon#flushed, iclass 32, count 0 2006.224.08:05:38.12#ibcon#about to write, iclass 32, count 0 2006.224.08:05:38.12#ibcon#wrote, iclass 32, count 0 2006.224.08:05:38.12#ibcon#about to read 3, iclass 32, count 0 2006.224.08:05:38.14#ibcon#read 3, iclass 32, count 0 2006.224.08:05:38.14#ibcon#about to read 4, iclass 32, count 0 2006.224.08:05:38.14#ibcon#read 4, iclass 32, count 0 2006.224.08:05:38.14#ibcon#about to read 5, iclass 32, count 0 2006.224.08:05:38.14#ibcon#read 5, iclass 32, count 0 2006.224.08:05:38.14#ibcon#about to read 6, iclass 32, count 0 2006.224.08:05:38.14#ibcon#read 6, iclass 32, count 0 2006.224.08:05:38.14#ibcon#end of sib2, iclass 32, count 0 2006.224.08:05:38.14#ibcon#*mode == 0, iclass 32, count 0 2006.224.08:05:38.14#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.224.08:05:38.14#ibcon#[25=USB\r\n] 2006.224.08:05:38.14#ibcon#*before write, iclass 32, count 0 2006.224.08:05:38.14#ibcon#enter sib2, iclass 32, count 0 2006.224.08:05:38.14#ibcon#flushed, iclass 32, count 0 2006.224.08:05:38.14#ibcon#about to write, iclass 32, count 0 2006.224.08:05:38.14#ibcon#wrote, iclass 32, count 0 2006.224.08:05:38.14#ibcon#about to read 3, iclass 32, count 0 2006.224.08:05:38.17#ibcon#read 3, iclass 32, count 0 2006.224.08:05:38.17#ibcon#about to read 4, iclass 32, count 0 2006.224.08:05:38.17#ibcon#read 4, iclass 32, count 0 2006.224.08:05:38.17#ibcon#about to read 5, iclass 32, count 0 2006.224.08:05:38.17#ibcon#read 5, iclass 32, count 0 2006.224.08:05:38.17#ibcon#about to read 6, iclass 32, count 0 2006.224.08:05:38.17#ibcon#read 6, iclass 32, count 0 2006.224.08:05:38.17#ibcon#end of sib2, iclass 32, count 0 2006.224.08:05:38.17#ibcon#*after write, iclass 32, count 0 2006.224.08:05:38.17#ibcon#*before return 0, iclass 32, count 0 2006.224.08:05:38.17#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.224.08:05:38.17#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.224.08:05:38.17#ibcon#about to clear, iclass 32 cls_cnt 0 2006.224.08:05:38.17#ibcon#cleared, iclass 32 cls_cnt 0 2006.224.08:05:38.17$vc4f8/valo=2,572.99 2006.224.08:05:38.17#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.224.08:05:38.17#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.224.08:05:38.17#ibcon#ireg 17 cls_cnt 0 2006.224.08:05:38.17#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.224.08:05:38.17#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.224.08:05:38.17#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.224.08:05:38.17#ibcon#enter wrdev, iclass 34, count 0 2006.224.08:05:38.17#ibcon#first serial, iclass 34, count 0 2006.224.08:05:38.17#ibcon#enter sib2, iclass 34, count 0 2006.224.08:05:38.17#ibcon#flushed, iclass 34, count 0 2006.224.08:05:38.17#ibcon#about to write, iclass 34, count 0 2006.224.08:05:38.17#ibcon#wrote, iclass 34, count 0 2006.224.08:05:38.17#ibcon#about to read 3, iclass 34, count 0 2006.224.08:05:38.19#ibcon#read 3, iclass 34, count 0 2006.224.08:05:38.19#ibcon#about to read 4, iclass 34, count 0 2006.224.08:05:38.19#ibcon#read 4, iclass 34, count 0 2006.224.08:05:38.19#ibcon#about to read 5, iclass 34, count 0 2006.224.08:05:38.19#ibcon#read 5, iclass 34, count 0 2006.224.08:05:38.19#ibcon#about to read 6, iclass 34, count 0 2006.224.08:05:38.19#ibcon#read 6, iclass 34, count 0 2006.224.08:05:38.19#ibcon#end of sib2, iclass 34, count 0 2006.224.08:05:38.19#ibcon#*mode == 0, iclass 34, count 0 2006.224.08:05:38.20#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.224.08:05:38.20#ibcon#[26=FRQ=02,572.99\r\n] 2006.224.08:05:38.20#ibcon#*before write, iclass 34, count 0 2006.224.08:05:38.20#ibcon#enter sib2, iclass 34, count 0 2006.224.08:05:38.20#ibcon#flushed, iclass 34, count 0 2006.224.08:05:38.20#ibcon#about to write, iclass 34, count 0 2006.224.08:05:38.20#ibcon#wrote, iclass 34, count 0 2006.224.08:05:38.20#ibcon#about to read 3, iclass 34, count 0 2006.224.08:05:38.24#ibcon#read 3, iclass 34, count 0 2006.224.08:05:38.24#ibcon#about to read 4, iclass 34, count 0 2006.224.08:05:38.24#ibcon#read 4, iclass 34, count 0 2006.224.08:05:38.24#ibcon#about to read 5, iclass 34, count 0 2006.224.08:05:38.24#ibcon#read 5, iclass 34, count 0 2006.224.08:05:38.24#ibcon#about to read 6, iclass 34, count 0 2006.224.08:05:38.24#ibcon#read 6, iclass 34, count 0 2006.224.08:05:38.24#ibcon#end of sib2, iclass 34, count 0 2006.224.08:05:38.24#ibcon#*after write, iclass 34, count 0 2006.224.08:05:38.24#ibcon#*before return 0, iclass 34, count 0 2006.224.08:05:38.24#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.224.08:05:38.24#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.224.08:05:38.24#ibcon#about to clear, iclass 34 cls_cnt 0 2006.224.08:05:38.24#ibcon#cleared, iclass 34 cls_cnt 0 2006.224.08:05:38.24$vc4f8/va=2,7 2006.224.08:05:38.24#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.224.08:05:38.24#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.224.08:05:38.24#ibcon#ireg 11 cls_cnt 2 2006.224.08:05:38.24#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.224.08:05:38.29#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.224.08:05:38.29#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.224.08:05:38.29#ibcon#enter wrdev, iclass 36, count 2 2006.224.08:05:38.29#ibcon#first serial, iclass 36, count 2 2006.224.08:05:38.29#ibcon#enter sib2, iclass 36, count 2 2006.224.08:05:38.29#ibcon#flushed, iclass 36, count 2 2006.224.08:05:38.29#ibcon#about to write, iclass 36, count 2 2006.224.08:05:38.29#ibcon#wrote, iclass 36, count 2 2006.224.08:05:38.29#ibcon#about to read 3, iclass 36, count 2 2006.224.08:05:38.31#ibcon#read 3, iclass 36, count 2 2006.224.08:05:38.31#ibcon#about to read 4, iclass 36, count 2 2006.224.08:05:38.31#ibcon#read 4, iclass 36, count 2 2006.224.08:05:38.31#ibcon#about to read 5, iclass 36, count 2 2006.224.08:05:38.31#ibcon#read 5, iclass 36, count 2 2006.224.08:05:38.31#ibcon#about to read 6, iclass 36, count 2 2006.224.08:05:38.31#ibcon#read 6, iclass 36, count 2 2006.224.08:05:38.31#ibcon#end of sib2, iclass 36, count 2 2006.224.08:05:38.31#ibcon#*mode == 0, iclass 36, count 2 2006.224.08:05:38.31#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.224.08:05:38.31#ibcon#[25=AT02-07\r\n] 2006.224.08:05:38.31#ibcon#*before write, iclass 36, count 2 2006.224.08:05:38.31#ibcon#enter sib2, iclass 36, count 2 2006.224.08:05:38.31#ibcon#flushed, iclass 36, count 2 2006.224.08:05:38.31#ibcon#about to write, iclass 36, count 2 2006.224.08:05:38.31#ibcon#wrote, iclass 36, count 2 2006.224.08:05:38.31#ibcon#about to read 3, iclass 36, count 2 2006.224.08:05:38.34#ibcon#read 3, iclass 36, count 2 2006.224.08:05:38.34#ibcon#about to read 4, iclass 36, count 2 2006.224.08:05:38.34#ibcon#read 4, iclass 36, count 2 2006.224.08:05:38.34#ibcon#about to read 5, iclass 36, count 2 2006.224.08:05:38.34#ibcon#read 5, iclass 36, count 2 2006.224.08:05:38.34#ibcon#about to read 6, iclass 36, count 2 2006.224.08:05:38.34#ibcon#read 6, iclass 36, count 2 2006.224.08:05:38.34#ibcon#end of sib2, iclass 36, count 2 2006.224.08:05:38.34#ibcon#*after write, iclass 36, count 2 2006.224.08:05:38.34#ibcon#*before return 0, iclass 36, count 2 2006.224.08:05:38.34#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.224.08:05:38.34#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.224.08:05:38.34#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.224.08:05:38.34#ibcon#ireg 7 cls_cnt 0 2006.224.08:05:38.34#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.224.08:05:38.46#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.224.08:05:38.46#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.224.08:05:38.46#ibcon#enter wrdev, iclass 36, count 0 2006.224.08:05:38.46#ibcon#first serial, iclass 36, count 0 2006.224.08:05:38.46#ibcon#enter sib2, iclass 36, count 0 2006.224.08:05:38.46#ibcon#flushed, iclass 36, count 0 2006.224.08:05:38.46#ibcon#about to write, iclass 36, count 0 2006.224.08:05:38.46#ibcon#wrote, iclass 36, count 0 2006.224.08:05:38.46#ibcon#about to read 3, iclass 36, count 0 2006.224.08:05:38.48#ibcon#read 3, iclass 36, count 0 2006.224.08:05:38.48#ibcon#about to read 4, iclass 36, count 0 2006.224.08:05:38.48#ibcon#read 4, iclass 36, count 0 2006.224.08:05:38.48#ibcon#about to read 5, iclass 36, count 0 2006.224.08:05:38.48#ibcon#read 5, iclass 36, count 0 2006.224.08:05:38.48#ibcon#about to read 6, iclass 36, count 0 2006.224.08:05:38.48#ibcon#read 6, iclass 36, count 0 2006.224.08:05:38.48#ibcon#end of sib2, iclass 36, count 0 2006.224.08:05:38.48#ibcon#*mode == 0, iclass 36, count 0 2006.224.08:05:38.48#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.224.08:05:38.48#ibcon#[25=USB\r\n] 2006.224.08:05:38.48#ibcon#*before write, iclass 36, count 0 2006.224.08:05:38.48#ibcon#enter sib2, iclass 36, count 0 2006.224.08:05:38.48#ibcon#flushed, iclass 36, count 0 2006.224.08:05:38.48#ibcon#about to write, iclass 36, count 0 2006.224.08:05:38.48#ibcon#wrote, iclass 36, count 0 2006.224.08:05:38.48#ibcon#about to read 3, iclass 36, count 0 2006.224.08:05:38.51#ibcon#read 3, iclass 36, count 0 2006.224.08:05:38.51#ibcon#about to read 4, iclass 36, count 0 2006.224.08:05:38.51#ibcon#read 4, iclass 36, count 0 2006.224.08:05:38.51#ibcon#about to read 5, iclass 36, count 0 2006.224.08:05:38.51#ibcon#read 5, iclass 36, count 0 2006.224.08:05:38.51#ibcon#about to read 6, iclass 36, count 0 2006.224.08:05:38.51#ibcon#read 6, iclass 36, count 0 2006.224.08:05:38.51#ibcon#end of sib2, iclass 36, count 0 2006.224.08:05:38.51#ibcon#*after write, iclass 36, count 0 2006.224.08:05:38.51#ibcon#*before return 0, iclass 36, count 0 2006.224.08:05:38.51#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.224.08:05:38.51#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.224.08:05:38.51#ibcon#about to clear, iclass 36 cls_cnt 0 2006.224.08:05:38.51#ibcon#cleared, iclass 36 cls_cnt 0 2006.224.08:05:38.51$vc4f8/valo=3,672.99 2006.224.08:05:38.51#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.224.08:05:38.51#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.224.08:05:38.51#ibcon#ireg 17 cls_cnt 0 2006.224.08:05:38.51#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.224.08:05:38.51#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.224.08:05:38.51#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.224.08:05:38.51#ibcon#enter wrdev, iclass 38, count 0 2006.224.08:05:38.51#ibcon#first serial, iclass 38, count 0 2006.224.08:05:38.51#ibcon#enter sib2, iclass 38, count 0 2006.224.08:05:38.51#ibcon#flushed, iclass 38, count 0 2006.224.08:05:38.51#ibcon#about to write, iclass 38, count 0 2006.224.08:05:38.51#ibcon#wrote, iclass 38, count 0 2006.224.08:05:38.51#ibcon#about to read 3, iclass 38, count 0 2006.224.08:05:38.53#ibcon#read 3, iclass 38, count 0 2006.224.08:05:38.53#ibcon#about to read 4, iclass 38, count 0 2006.224.08:05:38.54#ibcon#read 4, iclass 38, count 0 2006.224.08:05:38.54#ibcon#about to read 5, iclass 38, count 0 2006.224.08:05:38.54#ibcon#read 5, iclass 38, count 0 2006.224.08:05:38.54#ibcon#about to read 6, iclass 38, count 0 2006.224.08:05:38.54#ibcon#read 6, iclass 38, count 0 2006.224.08:05:38.54#ibcon#end of sib2, iclass 38, count 0 2006.224.08:05:38.54#ibcon#*mode == 0, iclass 38, count 0 2006.224.08:05:38.54#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.224.08:05:38.54#ibcon#[26=FRQ=03,672.99\r\n] 2006.224.08:05:38.54#ibcon#*before write, iclass 38, count 0 2006.224.08:05:38.54#ibcon#enter sib2, iclass 38, count 0 2006.224.08:05:38.54#ibcon#flushed, iclass 38, count 0 2006.224.08:05:38.54#ibcon#about to write, iclass 38, count 0 2006.224.08:05:38.54#ibcon#wrote, iclass 38, count 0 2006.224.08:05:38.54#ibcon#about to read 3, iclass 38, count 0 2006.224.08:05:38.58#ibcon#read 3, iclass 38, count 0 2006.224.08:05:38.58#ibcon#about to read 4, iclass 38, count 0 2006.224.08:05:38.58#ibcon#read 4, iclass 38, count 0 2006.224.08:05:38.58#ibcon#about to read 5, iclass 38, count 0 2006.224.08:05:38.58#ibcon#read 5, iclass 38, count 0 2006.224.08:05:38.58#ibcon#about to read 6, iclass 38, count 0 2006.224.08:05:38.58#ibcon#read 6, iclass 38, count 0 2006.224.08:05:38.58#ibcon#end of sib2, iclass 38, count 0 2006.224.08:05:38.58#ibcon#*after write, iclass 38, count 0 2006.224.08:05:38.58#ibcon#*before return 0, iclass 38, count 0 2006.224.08:05:38.58#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.224.08:05:38.58#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.224.08:05:38.58#ibcon#about to clear, iclass 38 cls_cnt 0 2006.224.08:05:38.58#ibcon#cleared, iclass 38 cls_cnt 0 2006.224.08:05:38.58$vc4f8/va=3,6 2006.224.08:05:38.58#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.224.08:05:38.58#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.224.08:05:38.58#ibcon#ireg 11 cls_cnt 2 2006.224.08:05:38.58#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.224.08:05:38.63#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.224.08:05:38.63#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.224.08:05:38.63#ibcon#enter wrdev, iclass 40, count 2 2006.224.08:05:38.63#ibcon#first serial, iclass 40, count 2 2006.224.08:05:38.63#ibcon#enter sib2, iclass 40, count 2 2006.224.08:05:38.63#ibcon#flushed, iclass 40, count 2 2006.224.08:05:38.63#ibcon#about to write, iclass 40, count 2 2006.224.08:05:38.63#ibcon#wrote, iclass 40, count 2 2006.224.08:05:38.63#ibcon#about to read 3, iclass 40, count 2 2006.224.08:05:38.65#ibcon#read 3, iclass 40, count 2 2006.224.08:05:38.65#ibcon#about to read 4, iclass 40, count 2 2006.224.08:05:38.65#ibcon#read 4, iclass 40, count 2 2006.224.08:05:38.65#ibcon#about to read 5, iclass 40, count 2 2006.224.08:05:38.65#ibcon#read 5, iclass 40, count 2 2006.224.08:05:38.65#ibcon#about to read 6, iclass 40, count 2 2006.224.08:05:38.65#ibcon#read 6, iclass 40, count 2 2006.224.08:05:38.65#ibcon#end of sib2, iclass 40, count 2 2006.224.08:05:38.65#ibcon#*mode == 0, iclass 40, count 2 2006.224.08:05:38.65#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.224.08:05:38.65#ibcon#[25=AT03-06\r\n] 2006.224.08:05:38.65#ibcon#*before write, iclass 40, count 2 2006.224.08:05:38.65#ibcon#enter sib2, iclass 40, count 2 2006.224.08:05:38.65#ibcon#flushed, iclass 40, count 2 2006.224.08:05:38.65#ibcon#about to write, iclass 40, count 2 2006.224.08:05:38.65#ibcon#wrote, iclass 40, count 2 2006.224.08:05:38.65#ibcon#about to read 3, iclass 40, count 2 2006.224.08:05:38.68#ibcon#read 3, iclass 40, count 2 2006.224.08:05:38.68#ibcon#about to read 4, iclass 40, count 2 2006.224.08:05:38.68#ibcon#read 4, iclass 40, count 2 2006.224.08:05:38.68#ibcon#about to read 5, iclass 40, count 2 2006.224.08:05:38.68#ibcon#read 5, iclass 40, count 2 2006.224.08:05:38.68#ibcon#about to read 6, iclass 40, count 2 2006.224.08:05:38.68#ibcon#read 6, iclass 40, count 2 2006.224.08:05:38.68#ibcon#end of sib2, iclass 40, count 2 2006.224.08:05:38.68#ibcon#*after write, iclass 40, count 2 2006.224.08:05:38.68#ibcon#*before return 0, iclass 40, count 2 2006.224.08:05:38.68#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.224.08:05:38.68#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.224.08:05:38.68#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.224.08:05:38.68#ibcon#ireg 7 cls_cnt 0 2006.224.08:05:38.68#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.224.08:05:38.80#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.224.08:05:38.80#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.224.08:05:38.80#ibcon#enter wrdev, iclass 40, count 0 2006.224.08:05:38.80#ibcon#first serial, iclass 40, count 0 2006.224.08:05:38.80#ibcon#enter sib2, iclass 40, count 0 2006.224.08:05:38.80#ibcon#flushed, iclass 40, count 0 2006.224.08:05:38.80#ibcon#about to write, iclass 40, count 0 2006.224.08:05:38.80#ibcon#wrote, iclass 40, count 0 2006.224.08:05:38.80#ibcon#about to read 3, iclass 40, count 0 2006.224.08:05:38.82#ibcon#read 3, iclass 40, count 0 2006.224.08:05:38.82#ibcon#about to read 4, iclass 40, count 0 2006.224.08:05:38.82#ibcon#read 4, iclass 40, count 0 2006.224.08:05:38.82#ibcon#about to read 5, iclass 40, count 0 2006.224.08:05:38.82#ibcon#read 5, iclass 40, count 0 2006.224.08:05:38.82#ibcon#about to read 6, iclass 40, count 0 2006.224.08:05:38.82#ibcon#read 6, iclass 40, count 0 2006.224.08:05:38.82#ibcon#end of sib2, iclass 40, count 0 2006.224.08:05:38.82#ibcon#*mode == 0, iclass 40, count 0 2006.224.08:05:38.82#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.224.08:05:38.82#ibcon#[25=USB\r\n] 2006.224.08:05:38.82#ibcon#*before write, iclass 40, count 0 2006.224.08:05:38.82#ibcon#enter sib2, iclass 40, count 0 2006.224.08:05:38.82#ibcon#flushed, iclass 40, count 0 2006.224.08:05:38.82#ibcon#about to write, iclass 40, count 0 2006.224.08:05:38.82#ibcon#wrote, iclass 40, count 0 2006.224.08:05:38.82#ibcon#about to read 3, iclass 40, count 0 2006.224.08:05:38.85#ibcon#read 3, iclass 40, count 0 2006.224.08:05:38.85#ibcon#about to read 4, iclass 40, count 0 2006.224.08:05:38.85#ibcon#read 4, iclass 40, count 0 2006.224.08:05:38.85#ibcon#about to read 5, iclass 40, count 0 2006.224.08:05:38.85#ibcon#read 5, iclass 40, count 0 2006.224.08:05:38.85#ibcon#about to read 6, iclass 40, count 0 2006.224.08:05:38.85#ibcon#read 6, iclass 40, count 0 2006.224.08:05:38.85#ibcon#end of sib2, iclass 40, count 0 2006.224.08:05:38.85#ibcon#*after write, iclass 40, count 0 2006.224.08:05:38.85#ibcon#*before return 0, iclass 40, count 0 2006.224.08:05:38.85#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.224.08:05:38.85#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.224.08:05:38.85#ibcon#about to clear, iclass 40 cls_cnt 0 2006.224.08:05:38.85#ibcon#cleared, iclass 40 cls_cnt 0 2006.224.08:05:38.85$vc4f8/valo=4,832.99 2006.224.08:05:38.85#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.224.08:05:38.85#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.224.08:05:38.85#ibcon#ireg 17 cls_cnt 0 2006.224.08:05:38.85#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.224.08:05:38.85#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.224.08:05:38.85#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.224.08:05:38.85#ibcon#enter wrdev, iclass 4, count 0 2006.224.08:05:38.85#ibcon#first serial, iclass 4, count 0 2006.224.08:05:38.85#ibcon#enter sib2, iclass 4, count 0 2006.224.08:05:38.85#ibcon#flushed, iclass 4, count 0 2006.224.08:05:38.85#ibcon#about to write, iclass 4, count 0 2006.224.08:05:38.85#ibcon#wrote, iclass 4, count 0 2006.224.08:05:38.85#ibcon#about to read 3, iclass 4, count 0 2006.224.08:05:38.87#ibcon#read 3, iclass 4, count 0 2006.224.08:05:38.87#ibcon#about to read 4, iclass 4, count 0 2006.224.08:05:38.87#ibcon#read 4, iclass 4, count 0 2006.224.08:05:38.87#ibcon#about to read 5, iclass 4, count 0 2006.224.08:05:38.87#ibcon#read 5, iclass 4, count 0 2006.224.08:05:38.87#ibcon#about to read 6, iclass 4, count 0 2006.224.08:05:38.87#ibcon#read 6, iclass 4, count 0 2006.224.08:05:38.87#ibcon#end of sib2, iclass 4, count 0 2006.224.08:05:38.87#ibcon#*mode == 0, iclass 4, count 0 2006.224.08:05:38.87#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.224.08:05:38.87#ibcon#[26=FRQ=04,832.99\r\n] 2006.224.08:05:38.87#ibcon#*before write, iclass 4, count 0 2006.224.08:05:38.87#ibcon#enter sib2, iclass 4, count 0 2006.224.08:05:38.87#ibcon#flushed, iclass 4, count 0 2006.224.08:05:38.87#ibcon#about to write, iclass 4, count 0 2006.224.08:05:38.87#ibcon#wrote, iclass 4, count 0 2006.224.08:05:38.87#ibcon#about to read 3, iclass 4, count 0 2006.224.08:05:38.91#ibcon#read 3, iclass 4, count 0 2006.224.08:05:38.91#ibcon#about to read 4, iclass 4, count 0 2006.224.08:05:38.91#ibcon#read 4, iclass 4, count 0 2006.224.08:05:38.91#ibcon#about to read 5, iclass 4, count 0 2006.224.08:05:38.91#ibcon#read 5, iclass 4, count 0 2006.224.08:05:38.91#ibcon#about to read 6, iclass 4, count 0 2006.224.08:05:38.91#ibcon#read 6, iclass 4, count 0 2006.224.08:05:38.91#ibcon#end of sib2, iclass 4, count 0 2006.224.08:05:38.91#ibcon#*after write, iclass 4, count 0 2006.224.08:05:38.91#ibcon#*before return 0, iclass 4, count 0 2006.224.08:05:38.91#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.224.08:05:38.91#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.224.08:05:38.91#ibcon#about to clear, iclass 4 cls_cnt 0 2006.224.08:05:38.91#ibcon#cleared, iclass 4 cls_cnt 0 2006.224.08:05:38.91$vc4f8/va=4,7 2006.224.08:05:38.91#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.224.08:05:38.91#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.224.08:05:38.91#ibcon#ireg 11 cls_cnt 2 2006.224.08:05:38.91#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.224.08:05:38.97#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.224.08:05:38.97#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.224.08:05:38.97#ibcon#enter wrdev, iclass 6, count 2 2006.224.08:05:38.97#ibcon#first serial, iclass 6, count 2 2006.224.08:05:38.97#ibcon#enter sib2, iclass 6, count 2 2006.224.08:05:38.97#ibcon#flushed, iclass 6, count 2 2006.224.08:05:38.97#ibcon#about to write, iclass 6, count 2 2006.224.08:05:38.97#ibcon#wrote, iclass 6, count 2 2006.224.08:05:38.97#ibcon#about to read 3, iclass 6, count 2 2006.224.08:05:38.99#ibcon#read 3, iclass 6, count 2 2006.224.08:05:38.99#ibcon#about to read 4, iclass 6, count 2 2006.224.08:05:38.99#ibcon#read 4, iclass 6, count 2 2006.224.08:05:38.99#ibcon#about to read 5, iclass 6, count 2 2006.224.08:05:38.99#ibcon#read 5, iclass 6, count 2 2006.224.08:05:38.99#ibcon#about to read 6, iclass 6, count 2 2006.224.08:05:38.99#ibcon#read 6, iclass 6, count 2 2006.224.08:05:38.99#ibcon#end of sib2, iclass 6, count 2 2006.224.08:05:38.99#ibcon#*mode == 0, iclass 6, count 2 2006.224.08:05:38.99#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.224.08:05:38.99#ibcon#[25=AT04-07\r\n] 2006.224.08:05:38.99#ibcon#*before write, iclass 6, count 2 2006.224.08:05:38.99#ibcon#enter sib2, iclass 6, count 2 2006.224.08:05:38.99#ibcon#flushed, iclass 6, count 2 2006.224.08:05:38.99#ibcon#about to write, iclass 6, count 2 2006.224.08:05:38.99#ibcon#wrote, iclass 6, count 2 2006.224.08:05:38.99#ibcon#about to read 3, iclass 6, count 2 2006.224.08:05:39.02#ibcon#read 3, iclass 6, count 2 2006.224.08:05:39.02#ibcon#about to read 4, iclass 6, count 2 2006.224.08:05:39.02#ibcon#read 4, iclass 6, count 2 2006.224.08:05:39.02#ibcon#about to read 5, iclass 6, count 2 2006.224.08:05:39.02#ibcon#read 5, iclass 6, count 2 2006.224.08:05:39.02#ibcon#about to read 6, iclass 6, count 2 2006.224.08:05:39.02#ibcon#read 6, iclass 6, count 2 2006.224.08:05:39.02#ibcon#end of sib2, iclass 6, count 2 2006.224.08:05:39.02#ibcon#*after write, iclass 6, count 2 2006.224.08:05:39.02#ibcon#*before return 0, iclass 6, count 2 2006.224.08:05:39.02#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.224.08:05:39.02#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.224.08:05:39.02#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.224.08:05:39.02#ibcon#ireg 7 cls_cnt 0 2006.224.08:05:39.02#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.224.08:05:39.14#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.224.08:05:39.14#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.224.08:05:39.14#ibcon#enter wrdev, iclass 6, count 0 2006.224.08:05:39.14#ibcon#first serial, iclass 6, count 0 2006.224.08:05:39.14#ibcon#enter sib2, iclass 6, count 0 2006.224.08:05:39.14#ibcon#flushed, iclass 6, count 0 2006.224.08:05:39.14#ibcon#about to write, iclass 6, count 0 2006.224.08:05:39.14#ibcon#wrote, iclass 6, count 0 2006.224.08:05:39.14#ibcon#about to read 3, iclass 6, count 0 2006.224.08:05:39.16#ibcon#read 3, iclass 6, count 0 2006.224.08:05:39.16#ibcon#about to read 4, iclass 6, count 0 2006.224.08:05:39.16#ibcon#read 4, iclass 6, count 0 2006.224.08:05:39.16#ibcon#about to read 5, iclass 6, count 0 2006.224.08:05:39.16#ibcon#read 5, iclass 6, count 0 2006.224.08:05:39.16#ibcon#about to read 6, iclass 6, count 0 2006.224.08:05:39.16#ibcon#read 6, iclass 6, count 0 2006.224.08:05:39.16#ibcon#end of sib2, iclass 6, count 0 2006.224.08:05:39.16#ibcon#*mode == 0, iclass 6, count 0 2006.224.08:05:39.16#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.224.08:05:39.16#ibcon#[25=USB\r\n] 2006.224.08:05:39.16#ibcon#*before write, iclass 6, count 0 2006.224.08:05:39.16#ibcon#enter sib2, iclass 6, count 0 2006.224.08:05:39.16#ibcon#flushed, iclass 6, count 0 2006.224.08:05:39.16#ibcon#about to write, iclass 6, count 0 2006.224.08:05:39.16#ibcon#wrote, iclass 6, count 0 2006.224.08:05:39.16#ibcon#about to read 3, iclass 6, count 0 2006.224.08:05:39.19#ibcon#read 3, iclass 6, count 0 2006.224.08:05:39.19#ibcon#about to read 4, iclass 6, count 0 2006.224.08:05:39.19#ibcon#read 4, iclass 6, count 0 2006.224.08:05:39.19#ibcon#about to read 5, iclass 6, count 0 2006.224.08:05:39.19#ibcon#read 5, iclass 6, count 0 2006.224.08:05:39.19#ibcon#about to read 6, iclass 6, count 0 2006.224.08:05:39.19#ibcon#read 6, iclass 6, count 0 2006.224.08:05:39.19#ibcon#end of sib2, iclass 6, count 0 2006.224.08:05:39.19#ibcon#*after write, iclass 6, count 0 2006.224.08:05:39.19#ibcon#*before return 0, iclass 6, count 0 2006.224.08:05:39.19#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.224.08:05:39.19#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.224.08:05:39.19#ibcon#about to clear, iclass 6 cls_cnt 0 2006.224.08:05:39.19#ibcon#cleared, iclass 6 cls_cnt 0 2006.224.08:05:39.19$vc4f8/valo=5,652.99 2006.224.08:05:39.19#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.224.08:05:39.19#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.224.08:05:39.19#ibcon#ireg 17 cls_cnt 0 2006.224.08:05:39.19#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.224.08:05:39.19#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.224.08:05:39.19#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.224.08:05:39.19#ibcon#enter wrdev, iclass 10, count 0 2006.224.08:05:39.19#ibcon#first serial, iclass 10, count 0 2006.224.08:05:39.19#ibcon#enter sib2, iclass 10, count 0 2006.224.08:05:39.19#ibcon#flushed, iclass 10, count 0 2006.224.08:05:39.19#ibcon#about to write, iclass 10, count 0 2006.224.08:05:39.19#ibcon#wrote, iclass 10, count 0 2006.224.08:05:39.19#ibcon#about to read 3, iclass 10, count 0 2006.224.08:05:39.21#ibcon#read 3, iclass 10, count 0 2006.224.08:05:39.21#ibcon#about to read 4, iclass 10, count 0 2006.224.08:05:39.21#ibcon#read 4, iclass 10, count 0 2006.224.08:05:39.21#ibcon#about to read 5, iclass 10, count 0 2006.224.08:05:39.21#ibcon#read 5, iclass 10, count 0 2006.224.08:05:39.21#ibcon#about to read 6, iclass 10, count 0 2006.224.08:05:39.21#ibcon#read 6, iclass 10, count 0 2006.224.08:05:39.21#ibcon#end of sib2, iclass 10, count 0 2006.224.08:05:39.21#ibcon#*mode == 0, iclass 10, count 0 2006.224.08:05:39.21#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.224.08:05:39.21#ibcon#[26=FRQ=05,652.99\r\n] 2006.224.08:05:39.21#ibcon#*before write, iclass 10, count 0 2006.224.08:05:39.21#ibcon#enter sib2, iclass 10, count 0 2006.224.08:05:39.21#ibcon#flushed, iclass 10, count 0 2006.224.08:05:39.21#ibcon#about to write, iclass 10, count 0 2006.224.08:05:39.21#ibcon#wrote, iclass 10, count 0 2006.224.08:05:39.21#ibcon#about to read 3, iclass 10, count 0 2006.224.08:05:39.25#ibcon#read 3, iclass 10, count 0 2006.224.08:05:39.25#ibcon#about to read 4, iclass 10, count 0 2006.224.08:05:39.25#ibcon#read 4, iclass 10, count 0 2006.224.08:05:39.25#ibcon#about to read 5, iclass 10, count 0 2006.224.08:05:39.25#ibcon#read 5, iclass 10, count 0 2006.224.08:05:39.25#ibcon#about to read 6, iclass 10, count 0 2006.224.08:05:39.25#ibcon#read 6, iclass 10, count 0 2006.224.08:05:39.25#ibcon#end of sib2, iclass 10, count 0 2006.224.08:05:39.25#ibcon#*after write, iclass 10, count 0 2006.224.08:05:39.25#ibcon#*before return 0, iclass 10, count 0 2006.224.08:05:39.25#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.224.08:05:39.25#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.224.08:05:39.25#ibcon#about to clear, iclass 10 cls_cnt 0 2006.224.08:05:39.25#ibcon#cleared, iclass 10 cls_cnt 0 2006.224.08:05:39.25$vc4f8/va=5,7 2006.224.08:05:39.25#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.224.08:05:39.25#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.224.08:05:39.25#ibcon#ireg 11 cls_cnt 2 2006.224.08:05:39.25#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.224.08:05:39.31#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.224.08:05:39.31#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.224.08:05:39.31#ibcon#enter wrdev, iclass 12, count 2 2006.224.08:05:39.31#ibcon#first serial, iclass 12, count 2 2006.224.08:05:39.31#ibcon#enter sib2, iclass 12, count 2 2006.224.08:05:39.31#ibcon#flushed, iclass 12, count 2 2006.224.08:05:39.31#ibcon#about to write, iclass 12, count 2 2006.224.08:05:39.31#ibcon#wrote, iclass 12, count 2 2006.224.08:05:39.31#ibcon#about to read 3, iclass 12, count 2 2006.224.08:05:39.33#ibcon#read 3, iclass 12, count 2 2006.224.08:05:39.33#ibcon#about to read 4, iclass 12, count 2 2006.224.08:05:39.33#ibcon#read 4, iclass 12, count 2 2006.224.08:05:39.33#ibcon#about to read 5, iclass 12, count 2 2006.224.08:05:39.33#ibcon#read 5, iclass 12, count 2 2006.224.08:05:39.33#ibcon#about to read 6, iclass 12, count 2 2006.224.08:05:39.33#ibcon#read 6, iclass 12, count 2 2006.224.08:05:39.33#ibcon#end of sib2, iclass 12, count 2 2006.224.08:05:39.33#ibcon#*mode == 0, iclass 12, count 2 2006.224.08:05:39.33#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.224.08:05:39.33#ibcon#[25=AT05-07\r\n] 2006.224.08:05:39.33#ibcon#*before write, iclass 12, count 2 2006.224.08:05:39.33#ibcon#enter sib2, iclass 12, count 2 2006.224.08:05:39.33#ibcon#flushed, iclass 12, count 2 2006.224.08:05:39.33#ibcon#about to write, iclass 12, count 2 2006.224.08:05:39.33#ibcon#wrote, iclass 12, count 2 2006.224.08:05:39.33#ibcon#about to read 3, iclass 12, count 2 2006.224.08:05:39.36#ibcon#read 3, iclass 12, count 2 2006.224.08:05:39.36#ibcon#about to read 4, iclass 12, count 2 2006.224.08:05:39.36#ibcon#read 4, iclass 12, count 2 2006.224.08:05:39.36#ibcon#about to read 5, iclass 12, count 2 2006.224.08:05:39.36#ibcon#read 5, iclass 12, count 2 2006.224.08:05:39.36#ibcon#about to read 6, iclass 12, count 2 2006.224.08:05:39.36#ibcon#read 6, iclass 12, count 2 2006.224.08:05:39.36#ibcon#end of sib2, iclass 12, count 2 2006.224.08:05:39.36#ibcon#*after write, iclass 12, count 2 2006.224.08:05:39.36#ibcon#*before return 0, iclass 12, count 2 2006.224.08:05:39.36#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.224.08:05:39.36#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.224.08:05:39.36#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.224.08:05:39.36#ibcon#ireg 7 cls_cnt 0 2006.224.08:05:39.36#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.224.08:05:39.48#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.224.08:05:39.48#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.224.08:05:39.48#ibcon#enter wrdev, iclass 12, count 0 2006.224.08:05:39.48#ibcon#first serial, iclass 12, count 0 2006.224.08:05:39.48#ibcon#enter sib2, iclass 12, count 0 2006.224.08:05:39.48#ibcon#flushed, iclass 12, count 0 2006.224.08:05:39.48#ibcon#about to write, iclass 12, count 0 2006.224.08:05:39.48#ibcon#wrote, iclass 12, count 0 2006.224.08:05:39.48#ibcon#about to read 3, iclass 12, count 0 2006.224.08:05:39.50#ibcon#read 3, iclass 12, count 0 2006.224.08:05:39.50#ibcon#about to read 4, iclass 12, count 0 2006.224.08:05:39.50#ibcon#read 4, iclass 12, count 0 2006.224.08:05:39.50#ibcon#about to read 5, iclass 12, count 0 2006.224.08:05:39.50#ibcon#read 5, iclass 12, count 0 2006.224.08:05:39.50#ibcon#about to read 6, iclass 12, count 0 2006.224.08:05:39.50#ibcon#read 6, iclass 12, count 0 2006.224.08:05:39.50#ibcon#end of sib2, iclass 12, count 0 2006.224.08:05:39.50#ibcon#*mode == 0, iclass 12, count 0 2006.224.08:05:39.50#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.224.08:05:39.50#ibcon#[25=USB\r\n] 2006.224.08:05:39.50#ibcon#*before write, iclass 12, count 0 2006.224.08:05:39.50#ibcon#enter sib2, iclass 12, count 0 2006.224.08:05:39.50#ibcon#flushed, iclass 12, count 0 2006.224.08:05:39.50#ibcon#about to write, iclass 12, count 0 2006.224.08:05:39.50#ibcon#wrote, iclass 12, count 0 2006.224.08:05:39.50#ibcon#about to read 3, iclass 12, count 0 2006.224.08:05:39.53#ibcon#read 3, iclass 12, count 0 2006.224.08:05:39.53#ibcon#about to read 4, iclass 12, count 0 2006.224.08:05:39.53#ibcon#read 4, iclass 12, count 0 2006.224.08:05:39.53#ibcon#about to read 5, iclass 12, count 0 2006.224.08:05:39.53#ibcon#read 5, iclass 12, count 0 2006.224.08:05:39.53#ibcon#about to read 6, iclass 12, count 0 2006.224.08:05:39.53#ibcon#read 6, iclass 12, count 0 2006.224.08:05:39.53#ibcon#end of sib2, iclass 12, count 0 2006.224.08:05:39.53#ibcon#*after write, iclass 12, count 0 2006.224.08:05:39.53#ibcon#*before return 0, iclass 12, count 0 2006.224.08:05:39.53#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.224.08:05:39.53#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.224.08:05:39.53#ibcon#about to clear, iclass 12 cls_cnt 0 2006.224.08:05:39.53#ibcon#cleared, iclass 12 cls_cnt 0 2006.224.08:05:39.53$vc4f8/valo=6,772.99 2006.224.08:05:39.53#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.224.08:05:39.53#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.224.08:05:39.53#ibcon#ireg 17 cls_cnt 0 2006.224.08:05:39.53#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.224.08:05:39.53#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.224.08:05:39.53#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.224.08:05:39.53#ibcon#enter wrdev, iclass 14, count 0 2006.224.08:05:39.53#ibcon#first serial, iclass 14, count 0 2006.224.08:05:39.53#ibcon#enter sib2, iclass 14, count 0 2006.224.08:05:39.53#ibcon#flushed, iclass 14, count 0 2006.224.08:05:39.53#ibcon#about to write, iclass 14, count 0 2006.224.08:05:39.53#ibcon#wrote, iclass 14, count 0 2006.224.08:05:39.53#ibcon#about to read 3, iclass 14, count 0 2006.224.08:05:39.55#ibcon#read 3, iclass 14, count 0 2006.224.08:05:39.55#ibcon#about to read 4, iclass 14, count 0 2006.224.08:05:39.55#ibcon#read 4, iclass 14, count 0 2006.224.08:05:39.55#ibcon#about to read 5, iclass 14, count 0 2006.224.08:05:39.55#ibcon#read 5, iclass 14, count 0 2006.224.08:05:39.55#ibcon#about to read 6, iclass 14, count 0 2006.224.08:05:39.55#ibcon#read 6, iclass 14, count 0 2006.224.08:05:39.55#ibcon#end of sib2, iclass 14, count 0 2006.224.08:05:39.55#ibcon#*mode == 0, iclass 14, count 0 2006.224.08:05:39.55#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.224.08:05:39.55#ibcon#[26=FRQ=06,772.99\r\n] 2006.224.08:05:39.55#ibcon#*before write, iclass 14, count 0 2006.224.08:05:39.55#ibcon#enter sib2, iclass 14, count 0 2006.224.08:05:39.55#ibcon#flushed, iclass 14, count 0 2006.224.08:05:39.55#ibcon#about to write, iclass 14, count 0 2006.224.08:05:39.55#ibcon#wrote, iclass 14, count 0 2006.224.08:05:39.55#ibcon#about to read 3, iclass 14, count 0 2006.224.08:05:39.59#ibcon#read 3, iclass 14, count 0 2006.224.08:05:39.59#ibcon#about to read 4, iclass 14, count 0 2006.224.08:05:39.59#ibcon#read 4, iclass 14, count 0 2006.224.08:05:39.59#ibcon#about to read 5, iclass 14, count 0 2006.224.08:05:39.59#ibcon#read 5, iclass 14, count 0 2006.224.08:05:39.59#ibcon#about to read 6, iclass 14, count 0 2006.224.08:05:39.59#ibcon#read 6, iclass 14, count 0 2006.224.08:05:39.59#ibcon#end of sib2, iclass 14, count 0 2006.224.08:05:39.59#ibcon#*after write, iclass 14, count 0 2006.224.08:05:39.59#ibcon#*before return 0, iclass 14, count 0 2006.224.08:05:39.59#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.224.08:05:39.59#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.224.08:05:39.59#ibcon#about to clear, iclass 14 cls_cnt 0 2006.224.08:05:39.59#ibcon#cleared, iclass 14 cls_cnt 0 2006.224.08:05:39.59$vc4f8/va=6,6 2006.224.08:05:39.59#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.224.08:05:39.59#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.224.08:05:39.59#ibcon#ireg 11 cls_cnt 2 2006.224.08:05:39.59#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.224.08:05:39.65#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.224.08:05:39.65#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.224.08:05:39.65#ibcon#enter wrdev, iclass 16, count 2 2006.224.08:05:39.65#ibcon#first serial, iclass 16, count 2 2006.224.08:05:39.65#ibcon#enter sib2, iclass 16, count 2 2006.224.08:05:39.65#ibcon#flushed, iclass 16, count 2 2006.224.08:05:39.65#ibcon#about to write, iclass 16, count 2 2006.224.08:05:39.65#ibcon#wrote, iclass 16, count 2 2006.224.08:05:39.65#ibcon#about to read 3, iclass 16, count 2 2006.224.08:05:39.67#ibcon#read 3, iclass 16, count 2 2006.224.08:05:39.67#ibcon#about to read 4, iclass 16, count 2 2006.224.08:05:39.67#ibcon#read 4, iclass 16, count 2 2006.224.08:05:39.67#ibcon#about to read 5, iclass 16, count 2 2006.224.08:05:39.67#ibcon#read 5, iclass 16, count 2 2006.224.08:05:39.67#ibcon#about to read 6, iclass 16, count 2 2006.224.08:05:39.67#ibcon#read 6, iclass 16, count 2 2006.224.08:05:39.67#ibcon#end of sib2, iclass 16, count 2 2006.224.08:05:39.67#ibcon#*mode == 0, iclass 16, count 2 2006.224.08:05:39.67#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.224.08:05:39.67#ibcon#[25=AT06-06\r\n] 2006.224.08:05:39.67#ibcon#*before write, iclass 16, count 2 2006.224.08:05:39.67#ibcon#enter sib2, iclass 16, count 2 2006.224.08:05:39.67#ibcon#flushed, iclass 16, count 2 2006.224.08:05:39.67#ibcon#about to write, iclass 16, count 2 2006.224.08:05:39.67#ibcon#wrote, iclass 16, count 2 2006.224.08:05:39.67#ibcon#about to read 3, iclass 16, count 2 2006.224.08:05:39.70#ibcon#read 3, iclass 16, count 2 2006.224.08:05:39.70#ibcon#about to read 4, iclass 16, count 2 2006.224.08:05:39.70#ibcon#read 4, iclass 16, count 2 2006.224.08:05:39.70#ibcon#about to read 5, iclass 16, count 2 2006.224.08:05:39.70#ibcon#read 5, iclass 16, count 2 2006.224.08:05:39.70#ibcon#about to read 6, iclass 16, count 2 2006.224.08:05:39.70#ibcon#read 6, iclass 16, count 2 2006.224.08:05:39.70#ibcon#end of sib2, iclass 16, count 2 2006.224.08:05:39.70#ibcon#*after write, iclass 16, count 2 2006.224.08:05:39.70#ibcon#*before return 0, iclass 16, count 2 2006.224.08:05:39.70#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.224.08:05:39.70#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.224.08:05:39.70#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.224.08:05:39.70#ibcon#ireg 7 cls_cnt 0 2006.224.08:05:39.70#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.224.08:05:39.82#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.224.08:05:39.82#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.224.08:05:39.82#ibcon#enter wrdev, iclass 16, count 0 2006.224.08:05:39.82#ibcon#first serial, iclass 16, count 0 2006.224.08:05:39.82#ibcon#enter sib2, iclass 16, count 0 2006.224.08:05:39.82#ibcon#flushed, iclass 16, count 0 2006.224.08:05:39.82#ibcon#about to write, iclass 16, count 0 2006.224.08:05:39.82#ibcon#wrote, iclass 16, count 0 2006.224.08:05:39.82#ibcon#about to read 3, iclass 16, count 0 2006.224.08:05:39.84#ibcon#read 3, iclass 16, count 0 2006.224.08:05:39.84#ibcon#about to read 4, iclass 16, count 0 2006.224.08:05:39.84#ibcon#read 4, iclass 16, count 0 2006.224.08:05:39.84#ibcon#about to read 5, iclass 16, count 0 2006.224.08:05:39.84#ibcon#read 5, iclass 16, count 0 2006.224.08:05:39.84#ibcon#about to read 6, iclass 16, count 0 2006.224.08:05:39.84#ibcon#read 6, iclass 16, count 0 2006.224.08:05:39.84#ibcon#end of sib2, iclass 16, count 0 2006.224.08:05:39.84#ibcon#*mode == 0, iclass 16, count 0 2006.224.08:05:39.84#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.224.08:05:39.84#ibcon#[25=USB\r\n] 2006.224.08:05:39.84#ibcon#*before write, iclass 16, count 0 2006.224.08:05:39.84#ibcon#enter sib2, iclass 16, count 0 2006.224.08:05:39.84#ibcon#flushed, iclass 16, count 0 2006.224.08:05:39.84#ibcon#about to write, iclass 16, count 0 2006.224.08:05:39.84#ibcon#wrote, iclass 16, count 0 2006.224.08:05:39.84#ibcon#about to read 3, iclass 16, count 0 2006.224.08:05:39.87#ibcon#read 3, iclass 16, count 0 2006.224.08:05:39.87#ibcon#about to read 4, iclass 16, count 0 2006.224.08:05:39.87#ibcon#read 4, iclass 16, count 0 2006.224.08:05:39.87#ibcon#about to read 5, iclass 16, count 0 2006.224.08:05:39.87#ibcon#read 5, iclass 16, count 0 2006.224.08:05:39.87#ibcon#about to read 6, iclass 16, count 0 2006.224.08:05:39.87#ibcon#read 6, iclass 16, count 0 2006.224.08:05:39.87#ibcon#end of sib2, iclass 16, count 0 2006.224.08:05:39.87#ibcon#*after write, iclass 16, count 0 2006.224.08:05:39.87#ibcon#*before return 0, iclass 16, count 0 2006.224.08:05:39.87#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.224.08:05:39.87#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.224.08:05:39.87#ibcon#about to clear, iclass 16 cls_cnt 0 2006.224.08:05:39.87#ibcon#cleared, iclass 16 cls_cnt 0 2006.224.08:05:39.87$vc4f8/valo=7,832.99 2006.224.08:05:39.87#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.224.08:05:39.87#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.224.08:05:39.87#ibcon#ireg 17 cls_cnt 0 2006.224.08:05:39.87#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.224.08:05:39.87#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.224.08:05:39.87#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.224.08:05:39.87#ibcon#enter wrdev, iclass 18, count 0 2006.224.08:05:39.87#ibcon#first serial, iclass 18, count 0 2006.224.08:05:39.87#ibcon#enter sib2, iclass 18, count 0 2006.224.08:05:39.87#ibcon#flushed, iclass 18, count 0 2006.224.08:05:39.87#ibcon#about to write, iclass 18, count 0 2006.224.08:05:39.87#ibcon#wrote, iclass 18, count 0 2006.224.08:05:39.87#ibcon#about to read 3, iclass 18, count 0 2006.224.08:05:39.89#ibcon#read 3, iclass 18, count 0 2006.224.08:05:39.89#ibcon#about to read 4, iclass 18, count 0 2006.224.08:05:39.89#ibcon#read 4, iclass 18, count 0 2006.224.08:05:39.89#ibcon#about to read 5, iclass 18, count 0 2006.224.08:05:39.89#ibcon#read 5, iclass 18, count 0 2006.224.08:05:39.89#ibcon#about to read 6, iclass 18, count 0 2006.224.08:05:39.89#ibcon#read 6, iclass 18, count 0 2006.224.08:05:39.89#ibcon#end of sib2, iclass 18, count 0 2006.224.08:05:39.89#ibcon#*mode == 0, iclass 18, count 0 2006.224.08:05:39.89#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.224.08:05:39.89#ibcon#[26=FRQ=07,832.99\r\n] 2006.224.08:05:39.89#ibcon#*before write, iclass 18, count 0 2006.224.08:05:39.89#ibcon#enter sib2, iclass 18, count 0 2006.224.08:05:39.89#ibcon#flushed, iclass 18, count 0 2006.224.08:05:39.89#ibcon#about to write, iclass 18, count 0 2006.224.08:05:39.89#ibcon#wrote, iclass 18, count 0 2006.224.08:05:39.89#ibcon#about to read 3, iclass 18, count 0 2006.224.08:05:39.93#ibcon#read 3, iclass 18, count 0 2006.224.08:05:39.93#ibcon#about to read 4, iclass 18, count 0 2006.224.08:05:39.93#ibcon#read 4, iclass 18, count 0 2006.224.08:05:39.93#ibcon#about to read 5, iclass 18, count 0 2006.224.08:05:39.93#ibcon#read 5, iclass 18, count 0 2006.224.08:05:39.93#ibcon#about to read 6, iclass 18, count 0 2006.224.08:05:39.93#ibcon#read 6, iclass 18, count 0 2006.224.08:05:39.93#ibcon#end of sib2, iclass 18, count 0 2006.224.08:05:39.93#ibcon#*after write, iclass 18, count 0 2006.224.08:05:39.93#ibcon#*before return 0, iclass 18, count 0 2006.224.08:05:39.93#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.224.08:05:39.93#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.224.08:05:39.93#ibcon#about to clear, iclass 18 cls_cnt 0 2006.224.08:05:39.93#ibcon#cleared, iclass 18 cls_cnt 0 2006.224.08:05:39.93$vc4f8/va=7,6 2006.224.08:05:39.93#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.224.08:05:39.93#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.224.08:05:39.93#ibcon#ireg 11 cls_cnt 2 2006.224.08:05:39.93#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.224.08:05:39.99#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.224.08:05:39.99#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.224.08:05:39.99#ibcon#enter wrdev, iclass 20, count 2 2006.224.08:05:39.99#ibcon#first serial, iclass 20, count 2 2006.224.08:05:39.99#ibcon#enter sib2, iclass 20, count 2 2006.224.08:05:39.99#ibcon#flushed, iclass 20, count 2 2006.224.08:05:39.99#ibcon#about to write, iclass 20, count 2 2006.224.08:05:39.99#ibcon#wrote, iclass 20, count 2 2006.224.08:05:39.99#ibcon#about to read 3, iclass 20, count 2 2006.224.08:05:40.01#ibcon#read 3, iclass 20, count 2 2006.224.08:05:40.01#ibcon#about to read 4, iclass 20, count 2 2006.224.08:05:40.01#ibcon#read 4, iclass 20, count 2 2006.224.08:05:40.01#ibcon#about to read 5, iclass 20, count 2 2006.224.08:05:40.01#ibcon#read 5, iclass 20, count 2 2006.224.08:05:40.01#ibcon#about to read 6, iclass 20, count 2 2006.224.08:05:40.01#ibcon#read 6, iclass 20, count 2 2006.224.08:05:40.01#ibcon#end of sib2, iclass 20, count 2 2006.224.08:05:40.01#ibcon#*mode == 0, iclass 20, count 2 2006.224.08:05:40.01#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.224.08:05:40.01#ibcon#[25=AT07-06\r\n] 2006.224.08:05:40.01#ibcon#*before write, iclass 20, count 2 2006.224.08:05:40.01#ibcon#enter sib2, iclass 20, count 2 2006.224.08:05:40.01#ibcon#flushed, iclass 20, count 2 2006.224.08:05:40.01#ibcon#about to write, iclass 20, count 2 2006.224.08:05:40.01#ibcon#wrote, iclass 20, count 2 2006.224.08:05:40.01#ibcon#about to read 3, iclass 20, count 2 2006.224.08:05:40.04#ibcon#read 3, iclass 20, count 2 2006.224.08:05:40.04#ibcon#about to read 4, iclass 20, count 2 2006.224.08:05:40.04#ibcon#read 4, iclass 20, count 2 2006.224.08:05:40.04#ibcon#about to read 5, iclass 20, count 2 2006.224.08:05:40.04#ibcon#read 5, iclass 20, count 2 2006.224.08:05:40.04#ibcon#about to read 6, iclass 20, count 2 2006.224.08:05:40.04#ibcon#read 6, iclass 20, count 2 2006.224.08:05:40.04#ibcon#end of sib2, iclass 20, count 2 2006.224.08:05:40.04#ibcon#*after write, iclass 20, count 2 2006.224.08:05:40.04#ibcon#*before return 0, iclass 20, count 2 2006.224.08:05:40.04#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.224.08:05:40.04#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.224.08:05:40.04#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.224.08:05:40.04#ibcon#ireg 7 cls_cnt 0 2006.224.08:05:40.04#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.224.08:05:40.16#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.224.08:05:40.16#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.224.08:05:40.16#ibcon#enter wrdev, iclass 20, count 0 2006.224.08:05:40.16#ibcon#first serial, iclass 20, count 0 2006.224.08:05:40.16#ibcon#enter sib2, iclass 20, count 0 2006.224.08:05:40.16#ibcon#flushed, iclass 20, count 0 2006.224.08:05:40.16#ibcon#about to write, iclass 20, count 0 2006.224.08:05:40.16#ibcon#wrote, iclass 20, count 0 2006.224.08:05:40.16#ibcon#about to read 3, iclass 20, count 0 2006.224.08:05:40.18#ibcon#read 3, iclass 20, count 0 2006.224.08:05:40.18#ibcon#about to read 4, iclass 20, count 0 2006.224.08:05:40.18#ibcon#read 4, iclass 20, count 0 2006.224.08:05:40.18#ibcon#about to read 5, iclass 20, count 0 2006.224.08:05:40.18#ibcon#read 5, iclass 20, count 0 2006.224.08:05:40.18#ibcon#about to read 6, iclass 20, count 0 2006.224.08:05:40.18#ibcon#read 6, iclass 20, count 0 2006.224.08:05:40.18#ibcon#end of sib2, iclass 20, count 0 2006.224.08:05:40.18#ibcon#*mode == 0, iclass 20, count 0 2006.224.08:05:40.18#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.224.08:05:40.18#ibcon#[25=USB\r\n] 2006.224.08:05:40.18#ibcon#*before write, iclass 20, count 0 2006.224.08:05:40.18#ibcon#enter sib2, iclass 20, count 0 2006.224.08:05:40.18#ibcon#flushed, iclass 20, count 0 2006.224.08:05:40.18#ibcon#about to write, iclass 20, count 0 2006.224.08:05:40.18#ibcon#wrote, iclass 20, count 0 2006.224.08:05:40.18#ibcon#about to read 3, iclass 20, count 0 2006.224.08:05:40.20#abcon#<5=/10 1.3 2.6 23.651001004.8\r\n> 2006.224.08:05:40.21#ibcon#read 3, iclass 20, count 0 2006.224.08:05:40.21#ibcon#about to read 4, iclass 20, count 0 2006.224.08:05:40.21#ibcon#read 4, iclass 20, count 0 2006.224.08:05:40.21#ibcon#about to read 5, iclass 20, count 0 2006.224.08:05:40.21#ibcon#read 5, iclass 20, count 0 2006.224.08:05:40.21#ibcon#about to read 6, iclass 20, count 0 2006.224.08:05:40.21#ibcon#read 6, iclass 20, count 0 2006.224.08:05:40.21#ibcon#end of sib2, iclass 20, count 0 2006.224.08:05:40.21#ibcon#*after write, iclass 20, count 0 2006.224.08:05:40.21#ibcon#*before return 0, iclass 20, count 0 2006.224.08:05:40.21#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.224.08:05:40.21#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.224.08:05:40.21#ibcon#about to clear, iclass 20 cls_cnt 0 2006.224.08:05:40.21#ibcon#cleared, iclass 20 cls_cnt 0 2006.224.08:05:40.21$vc4f8/valo=8,852.99 2006.224.08:05:40.21#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.224.08:05:40.21#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.224.08:05:40.21#ibcon#ireg 17 cls_cnt 0 2006.224.08:05:40.21#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.224.08:05:40.21#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.224.08:05:40.21#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.224.08:05:40.21#ibcon#enter wrdev, iclass 25, count 0 2006.224.08:05:40.21#ibcon#first serial, iclass 25, count 0 2006.224.08:05:40.21#ibcon#enter sib2, iclass 25, count 0 2006.224.08:05:40.21#ibcon#flushed, iclass 25, count 0 2006.224.08:05:40.21#ibcon#about to write, iclass 25, count 0 2006.224.08:05:40.21#ibcon#wrote, iclass 25, count 0 2006.224.08:05:40.21#ibcon#about to read 3, iclass 25, count 0 2006.224.08:05:40.22#abcon#{5=INTERFACE CLEAR} 2006.224.08:05:40.23#ibcon#read 3, iclass 25, count 0 2006.224.08:05:40.23#ibcon#about to read 4, iclass 25, count 0 2006.224.08:05:40.23#ibcon#read 4, iclass 25, count 0 2006.224.08:05:40.23#ibcon#about to read 5, iclass 25, count 0 2006.224.08:05:40.23#ibcon#read 5, iclass 25, count 0 2006.224.08:05:40.23#ibcon#about to read 6, iclass 25, count 0 2006.224.08:05:40.23#ibcon#read 6, iclass 25, count 0 2006.224.08:05:40.23#ibcon#end of sib2, iclass 25, count 0 2006.224.08:05:40.23#ibcon#*mode == 0, iclass 25, count 0 2006.224.08:05:40.23#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.224.08:05:40.23#ibcon#[26=FRQ=08,852.99\r\n] 2006.224.08:05:40.23#ibcon#*before write, iclass 25, count 0 2006.224.08:05:40.23#ibcon#enter sib2, iclass 25, count 0 2006.224.08:05:40.23#ibcon#flushed, iclass 25, count 0 2006.224.08:05:40.23#ibcon#about to write, iclass 25, count 0 2006.224.08:05:40.23#ibcon#wrote, iclass 25, count 0 2006.224.08:05:40.23#ibcon#about to read 3, iclass 25, count 0 2006.224.08:05:40.27#ibcon#read 3, iclass 25, count 0 2006.224.08:05:40.27#ibcon#about to read 4, iclass 25, count 0 2006.224.08:05:40.27#ibcon#read 4, iclass 25, count 0 2006.224.08:05:40.27#ibcon#about to read 5, iclass 25, count 0 2006.224.08:05:40.27#ibcon#read 5, iclass 25, count 0 2006.224.08:05:40.27#ibcon#about to read 6, iclass 25, count 0 2006.224.08:05:40.27#ibcon#read 6, iclass 25, count 0 2006.224.08:05:40.27#ibcon#end of sib2, iclass 25, count 0 2006.224.08:05:40.27#ibcon#*after write, iclass 25, count 0 2006.224.08:05:40.27#ibcon#*before return 0, iclass 25, count 0 2006.224.08:05:40.27#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.224.08:05:40.27#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.224.08:05:40.27#ibcon#about to clear, iclass 25 cls_cnt 0 2006.224.08:05:40.27#ibcon#cleared, iclass 25 cls_cnt 0 2006.224.08:05:40.27$vc4f8/va=8,7 2006.224.08:05:40.27#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.224.08:05:40.27#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.224.08:05:40.27#ibcon#ireg 11 cls_cnt 2 2006.224.08:05:40.27#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.224.08:05:40.28#abcon#[5=S1D000X0/0*\r\n] 2006.224.08:05:40.33#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.224.08:05:40.33#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.224.08:05:40.33#ibcon#enter wrdev, iclass 28, count 2 2006.224.08:05:40.33#ibcon#first serial, iclass 28, count 2 2006.224.08:05:40.33#ibcon#enter sib2, iclass 28, count 2 2006.224.08:05:40.33#ibcon#flushed, iclass 28, count 2 2006.224.08:05:40.33#ibcon#about to write, iclass 28, count 2 2006.224.08:05:40.33#ibcon#wrote, iclass 28, count 2 2006.224.08:05:40.33#ibcon#about to read 3, iclass 28, count 2 2006.224.08:05:40.35#ibcon#read 3, iclass 28, count 2 2006.224.08:05:40.35#ibcon#about to read 4, iclass 28, count 2 2006.224.08:05:40.35#ibcon#read 4, iclass 28, count 2 2006.224.08:05:40.35#ibcon#about to read 5, iclass 28, count 2 2006.224.08:05:40.35#ibcon#read 5, iclass 28, count 2 2006.224.08:05:40.35#ibcon#about to read 6, iclass 28, count 2 2006.224.08:05:40.35#ibcon#read 6, iclass 28, count 2 2006.224.08:05:40.35#ibcon#end of sib2, iclass 28, count 2 2006.224.08:05:40.35#ibcon#*mode == 0, iclass 28, count 2 2006.224.08:05:40.35#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.224.08:05:40.35#ibcon#[25=AT08-07\r\n] 2006.224.08:05:40.35#ibcon#*before write, iclass 28, count 2 2006.224.08:05:40.35#ibcon#enter sib2, iclass 28, count 2 2006.224.08:05:40.35#ibcon#flushed, iclass 28, count 2 2006.224.08:05:40.35#ibcon#about to write, iclass 28, count 2 2006.224.08:05:40.35#ibcon#wrote, iclass 28, count 2 2006.224.08:05:40.35#ibcon#about to read 3, iclass 28, count 2 2006.224.08:05:40.38#ibcon#read 3, iclass 28, count 2 2006.224.08:05:40.38#ibcon#about to read 4, iclass 28, count 2 2006.224.08:05:40.38#ibcon#read 4, iclass 28, count 2 2006.224.08:05:40.38#ibcon#about to read 5, iclass 28, count 2 2006.224.08:05:40.38#ibcon#read 5, iclass 28, count 2 2006.224.08:05:40.38#ibcon#about to read 6, iclass 28, count 2 2006.224.08:05:40.38#ibcon#read 6, iclass 28, count 2 2006.224.08:05:40.38#ibcon#end of sib2, iclass 28, count 2 2006.224.08:05:40.38#ibcon#*after write, iclass 28, count 2 2006.224.08:05:40.38#ibcon#*before return 0, iclass 28, count 2 2006.224.08:05:40.38#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.224.08:05:40.38#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.224.08:05:40.38#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.224.08:05:40.38#ibcon#ireg 7 cls_cnt 0 2006.224.08:05:40.38#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.224.08:05:40.50#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.224.08:05:40.50#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.224.08:05:40.50#ibcon#enter wrdev, iclass 28, count 0 2006.224.08:05:40.50#ibcon#first serial, iclass 28, count 0 2006.224.08:05:40.50#ibcon#enter sib2, iclass 28, count 0 2006.224.08:05:40.50#ibcon#flushed, iclass 28, count 0 2006.224.08:05:40.50#ibcon#about to write, iclass 28, count 0 2006.224.08:05:40.50#ibcon#wrote, iclass 28, count 0 2006.224.08:05:40.50#ibcon#about to read 3, iclass 28, count 0 2006.224.08:05:40.52#ibcon#read 3, iclass 28, count 0 2006.224.08:05:40.52#ibcon#about to read 4, iclass 28, count 0 2006.224.08:05:40.52#ibcon#read 4, iclass 28, count 0 2006.224.08:05:40.52#ibcon#about to read 5, iclass 28, count 0 2006.224.08:05:40.52#ibcon#read 5, iclass 28, count 0 2006.224.08:05:40.52#ibcon#about to read 6, iclass 28, count 0 2006.224.08:05:40.52#ibcon#read 6, iclass 28, count 0 2006.224.08:05:40.52#ibcon#end of sib2, iclass 28, count 0 2006.224.08:05:40.52#ibcon#*mode == 0, iclass 28, count 0 2006.224.08:05:40.52#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.224.08:05:40.52#ibcon#[25=USB\r\n] 2006.224.08:05:40.52#ibcon#*before write, iclass 28, count 0 2006.224.08:05:40.52#ibcon#enter sib2, iclass 28, count 0 2006.224.08:05:40.52#ibcon#flushed, iclass 28, count 0 2006.224.08:05:40.52#ibcon#about to write, iclass 28, count 0 2006.224.08:05:40.52#ibcon#wrote, iclass 28, count 0 2006.224.08:05:40.52#ibcon#about to read 3, iclass 28, count 0 2006.224.08:05:40.55#ibcon#read 3, iclass 28, count 0 2006.224.08:05:40.55#ibcon#about to read 4, iclass 28, count 0 2006.224.08:05:40.55#ibcon#read 4, iclass 28, count 0 2006.224.08:05:40.55#ibcon#about to read 5, iclass 28, count 0 2006.224.08:05:40.55#ibcon#read 5, iclass 28, count 0 2006.224.08:05:40.55#ibcon#about to read 6, iclass 28, count 0 2006.224.08:05:40.55#ibcon#read 6, iclass 28, count 0 2006.224.08:05:40.55#ibcon#end of sib2, iclass 28, count 0 2006.224.08:05:40.55#ibcon#*after write, iclass 28, count 0 2006.224.08:05:40.55#ibcon#*before return 0, iclass 28, count 0 2006.224.08:05:40.55#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.224.08:05:40.55#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.224.08:05:40.55#ibcon#about to clear, iclass 28 cls_cnt 0 2006.224.08:05:40.55#ibcon#cleared, iclass 28 cls_cnt 0 2006.224.08:05:40.55$vc4f8/vblo=1,632.99 2006.224.08:05:40.55#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.224.08:05:40.55#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.224.08:05:40.55#ibcon#ireg 17 cls_cnt 0 2006.224.08:05:40.55#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.224.08:05:40.55#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.224.08:05:40.55#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.224.08:05:40.55#ibcon#enter wrdev, iclass 30, count 0 2006.224.08:05:40.55#ibcon#first serial, iclass 30, count 0 2006.224.08:05:40.55#ibcon#enter sib2, iclass 30, count 0 2006.224.08:05:40.55#ibcon#flushed, iclass 30, count 0 2006.224.08:05:40.55#ibcon#about to write, iclass 30, count 0 2006.224.08:05:40.55#ibcon#wrote, iclass 30, count 0 2006.224.08:05:40.55#ibcon#about to read 3, iclass 30, count 0 2006.224.08:05:40.57#ibcon#read 3, iclass 30, count 0 2006.224.08:05:40.57#ibcon#about to read 4, iclass 30, count 0 2006.224.08:05:40.57#ibcon#read 4, iclass 30, count 0 2006.224.08:05:40.57#ibcon#about to read 5, iclass 30, count 0 2006.224.08:05:40.57#ibcon#read 5, iclass 30, count 0 2006.224.08:05:40.57#ibcon#about to read 6, iclass 30, count 0 2006.224.08:05:40.57#ibcon#read 6, iclass 30, count 0 2006.224.08:05:40.57#ibcon#end of sib2, iclass 30, count 0 2006.224.08:05:40.57#ibcon#*mode == 0, iclass 30, count 0 2006.224.08:05:40.57#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.224.08:05:40.57#ibcon#[28=FRQ=01,632.99\r\n] 2006.224.08:05:40.57#ibcon#*before write, iclass 30, count 0 2006.224.08:05:40.57#ibcon#enter sib2, iclass 30, count 0 2006.224.08:05:40.57#ibcon#flushed, iclass 30, count 0 2006.224.08:05:40.57#ibcon#about to write, iclass 30, count 0 2006.224.08:05:40.57#ibcon#wrote, iclass 30, count 0 2006.224.08:05:40.57#ibcon#about to read 3, iclass 30, count 0 2006.224.08:05:40.61#ibcon#read 3, iclass 30, count 0 2006.224.08:05:40.61#ibcon#about to read 4, iclass 30, count 0 2006.224.08:05:40.61#ibcon#read 4, iclass 30, count 0 2006.224.08:05:40.61#ibcon#about to read 5, iclass 30, count 0 2006.224.08:05:40.61#ibcon#read 5, iclass 30, count 0 2006.224.08:05:40.61#ibcon#about to read 6, iclass 30, count 0 2006.224.08:05:40.61#ibcon#read 6, iclass 30, count 0 2006.224.08:05:40.61#ibcon#end of sib2, iclass 30, count 0 2006.224.08:05:40.61#ibcon#*after write, iclass 30, count 0 2006.224.08:05:40.61#ibcon#*before return 0, iclass 30, count 0 2006.224.08:05:40.61#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.224.08:05:40.61#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.224.08:05:40.61#ibcon#about to clear, iclass 30 cls_cnt 0 2006.224.08:05:40.61#ibcon#cleared, iclass 30 cls_cnt 0 2006.224.08:05:40.61$vc4f8/vb=1,4 2006.224.08:05:40.61#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.224.08:05:40.61#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.224.08:05:40.61#ibcon#ireg 11 cls_cnt 2 2006.224.08:05:40.61#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.224.08:05:40.61#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.224.08:05:40.61#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.224.08:05:40.61#ibcon#enter wrdev, iclass 32, count 2 2006.224.08:05:40.61#ibcon#first serial, iclass 32, count 2 2006.224.08:05:40.61#ibcon#enter sib2, iclass 32, count 2 2006.224.08:05:40.61#ibcon#flushed, iclass 32, count 2 2006.224.08:05:40.61#ibcon#about to write, iclass 32, count 2 2006.224.08:05:40.61#ibcon#wrote, iclass 32, count 2 2006.224.08:05:40.61#ibcon#about to read 3, iclass 32, count 2 2006.224.08:05:40.63#ibcon#read 3, iclass 32, count 2 2006.224.08:05:40.63#ibcon#about to read 4, iclass 32, count 2 2006.224.08:05:40.63#ibcon#read 4, iclass 32, count 2 2006.224.08:05:40.63#ibcon#about to read 5, iclass 32, count 2 2006.224.08:05:40.63#ibcon#read 5, iclass 32, count 2 2006.224.08:05:40.63#ibcon#about to read 6, iclass 32, count 2 2006.224.08:05:40.63#ibcon#read 6, iclass 32, count 2 2006.224.08:05:40.63#ibcon#end of sib2, iclass 32, count 2 2006.224.08:05:40.63#ibcon#*mode == 0, iclass 32, count 2 2006.224.08:05:40.63#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.224.08:05:40.63#ibcon#[27=AT01-04\r\n] 2006.224.08:05:40.63#ibcon#*before write, iclass 32, count 2 2006.224.08:05:40.63#ibcon#enter sib2, iclass 32, count 2 2006.224.08:05:40.63#ibcon#flushed, iclass 32, count 2 2006.224.08:05:40.63#ibcon#about to write, iclass 32, count 2 2006.224.08:05:40.63#ibcon#wrote, iclass 32, count 2 2006.224.08:05:40.63#ibcon#about to read 3, iclass 32, count 2 2006.224.08:05:40.66#ibcon#read 3, iclass 32, count 2 2006.224.08:05:40.66#ibcon#about to read 4, iclass 32, count 2 2006.224.08:05:40.66#ibcon#read 4, iclass 32, count 2 2006.224.08:05:40.66#ibcon#about to read 5, iclass 32, count 2 2006.224.08:05:40.66#ibcon#read 5, iclass 32, count 2 2006.224.08:05:40.66#ibcon#about to read 6, iclass 32, count 2 2006.224.08:05:40.66#ibcon#read 6, iclass 32, count 2 2006.224.08:05:40.66#ibcon#end of sib2, iclass 32, count 2 2006.224.08:05:40.66#ibcon#*after write, iclass 32, count 2 2006.224.08:05:40.66#ibcon#*before return 0, iclass 32, count 2 2006.224.08:05:40.66#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.224.08:05:40.66#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.224.08:05:40.66#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.224.08:05:40.66#ibcon#ireg 7 cls_cnt 0 2006.224.08:05:40.66#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.224.08:05:40.78#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.224.08:05:40.78#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.224.08:05:40.78#ibcon#enter wrdev, iclass 32, count 0 2006.224.08:05:40.78#ibcon#first serial, iclass 32, count 0 2006.224.08:05:40.78#ibcon#enter sib2, iclass 32, count 0 2006.224.08:05:40.78#ibcon#flushed, iclass 32, count 0 2006.224.08:05:40.78#ibcon#about to write, iclass 32, count 0 2006.224.08:05:40.78#ibcon#wrote, iclass 32, count 0 2006.224.08:05:40.78#ibcon#about to read 3, iclass 32, count 0 2006.224.08:05:40.80#ibcon#read 3, iclass 32, count 0 2006.224.08:05:40.80#ibcon#about to read 4, iclass 32, count 0 2006.224.08:05:40.80#ibcon#read 4, iclass 32, count 0 2006.224.08:05:40.80#ibcon#about to read 5, iclass 32, count 0 2006.224.08:05:40.80#ibcon#read 5, iclass 32, count 0 2006.224.08:05:40.80#ibcon#about to read 6, iclass 32, count 0 2006.224.08:05:40.80#ibcon#read 6, iclass 32, count 0 2006.224.08:05:40.80#ibcon#end of sib2, iclass 32, count 0 2006.224.08:05:40.80#ibcon#*mode == 0, iclass 32, count 0 2006.224.08:05:40.80#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.224.08:05:40.80#ibcon#[27=USB\r\n] 2006.224.08:05:40.80#ibcon#*before write, iclass 32, count 0 2006.224.08:05:40.80#ibcon#enter sib2, iclass 32, count 0 2006.224.08:05:40.80#ibcon#flushed, iclass 32, count 0 2006.224.08:05:40.80#ibcon#about to write, iclass 32, count 0 2006.224.08:05:40.80#ibcon#wrote, iclass 32, count 0 2006.224.08:05:40.80#ibcon#about to read 3, iclass 32, count 0 2006.224.08:05:40.83#ibcon#read 3, iclass 32, count 0 2006.224.08:05:40.83#ibcon#about to read 4, iclass 32, count 0 2006.224.08:05:40.83#ibcon#read 4, iclass 32, count 0 2006.224.08:05:40.83#ibcon#about to read 5, iclass 32, count 0 2006.224.08:05:40.83#ibcon#read 5, iclass 32, count 0 2006.224.08:05:40.83#ibcon#about to read 6, iclass 32, count 0 2006.224.08:05:40.83#ibcon#read 6, iclass 32, count 0 2006.224.08:05:40.83#ibcon#end of sib2, iclass 32, count 0 2006.224.08:05:40.83#ibcon#*after write, iclass 32, count 0 2006.224.08:05:40.83#ibcon#*before return 0, iclass 32, count 0 2006.224.08:05:40.83#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.224.08:05:40.83#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.224.08:05:40.83#ibcon#about to clear, iclass 32 cls_cnt 0 2006.224.08:05:40.83#ibcon#cleared, iclass 32 cls_cnt 0 2006.224.08:05:40.83$vc4f8/vblo=2,640.99 2006.224.08:05:40.83#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.224.08:05:40.83#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.224.08:05:40.83#ibcon#ireg 17 cls_cnt 0 2006.224.08:05:40.83#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.224.08:05:40.83#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.224.08:05:40.83#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.224.08:05:40.83#ibcon#enter wrdev, iclass 34, count 0 2006.224.08:05:40.83#ibcon#first serial, iclass 34, count 0 2006.224.08:05:40.83#ibcon#enter sib2, iclass 34, count 0 2006.224.08:05:40.83#ibcon#flushed, iclass 34, count 0 2006.224.08:05:40.83#ibcon#about to write, iclass 34, count 0 2006.224.08:05:40.83#ibcon#wrote, iclass 34, count 0 2006.224.08:05:40.83#ibcon#about to read 3, iclass 34, count 0 2006.224.08:05:40.85#ibcon#read 3, iclass 34, count 0 2006.224.08:05:40.85#ibcon#about to read 4, iclass 34, count 0 2006.224.08:05:40.85#ibcon#read 4, iclass 34, count 0 2006.224.08:05:40.85#ibcon#about to read 5, iclass 34, count 0 2006.224.08:05:40.85#ibcon#read 5, iclass 34, count 0 2006.224.08:05:40.85#ibcon#about to read 6, iclass 34, count 0 2006.224.08:05:40.85#ibcon#read 6, iclass 34, count 0 2006.224.08:05:40.85#ibcon#end of sib2, iclass 34, count 0 2006.224.08:05:40.85#ibcon#*mode == 0, iclass 34, count 0 2006.224.08:05:40.85#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.224.08:05:40.85#ibcon#[28=FRQ=02,640.99\r\n] 2006.224.08:05:40.85#ibcon#*before write, iclass 34, count 0 2006.224.08:05:40.85#ibcon#enter sib2, iclass 34, count 0 2006.224.08:05:40.85#ibcon#flushed, iclass 34, count 0 2006.224.08:05:40.85#ibcon#about to write, iclass 34, count 0 2006.224.08:05:40.85#ibcon#wrote, iclass 34, count 0 2006.224.08:05:40.85#ibcon#about to read 3, iclass 34, count 0 2006.224.08:05:40.89#ibcon#read 3, iclass 34, count 0 2006.224.08:05:40.89#ibcon#about to read 4, iclass 34, count 0 2006.224.08:05:40.89#ibcon#read 4, iclass 34, count 0 2006.224.08:05:40.89#ibcon#about to read 5, iclass 34, count 0 2006.224.08:05:40.89#ibcon#read 5, iclass 34, count 0 2006.224.08:05:40.89#ibcon#about to read 6, iclass 34, count 0 2006.224.08:05:40.89#ibcon#read 6, iclass 34, count 0 2006.224.08:05:40.89#ibcon#end of sib2, iclass 34, count 0 2006.224.08:05:40.89#ibcon#*after write, iclass 34, count 0 2006.224.08:05:40.89#ibcon#*before return 0, iclass 34, count 0 2006.224.08:05:40.89#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.224.08:05:40.89#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.224.08:05:40.89#ibcon#about to clear, iclass 34 cls_cnt 0 2006.224.08:05:40.89#ibcon#cleared, iclass 34 cls_cnt 0 2006.224.08:05:40.89$vc4f8/vb=2,4 2006.224.08:05:40.89#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.224.08:05:40.89#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.224.08:05:40.89#ibcon#ireg 11 cls_cnt 2 2006.224.08:05:40.89#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.224.08:05:40.95#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.224.08:05:40.95#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.224.08:05:40.95#ibcon#enter wrdev, iclass 36, count 2 2006.224.08:05:40.95#ibcon#first serial, iclass 36, count 2 2006.224.08:05:40.95#ibcon#enter sib2, iclass 36, count 2 2006.224.08:05:40.95#ibcon#flushed, iclass 36, count 2 2006.224.08:05:40.95#ibcon#about to write, iclass 36, count 2 2006.224.08:05:40.95#ibcon#wrote, iclass 36, count 2 2006.224.08:05:40.95#ibcon#about to read 3, iclass 36, count 2 2006.224.08:05:40.97#ibcon#read 3, iclass 36, count 2 2006.224.08:05:40.97#ibcon#about to read 4, iclass 36, count 2 2006.224.08:05:40.97#ibcon#read 4, iclass 36, count 2 2006.224.08:05:40.97#ibcon#about to read 5, iclass 36, count 2 2006.224.08:05:40.97#ibcon#read 5, iclass 36, count 2 2006.224.08:05:40.97#ibcon#about to read 6, iclass 36, count 2 2006.224.08:05:40.97#ibcon#read 6, iclass 36, count 2 2006.224.08:05:40.97#ibcon#end of sib2, iclass 36, count 2 2006.224.08:05:40.97#ibcon#*mode == 0, iclass 36, count 2 2006.224.08:05:40.97#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.224.08:05:40.97#ibcon#[27=AT02-04\r\n] 2006.224.08:05:40.97#ibcon#*before write, iclass 36, count 2 2006.224.08:05:40.97#ibcon#enter sib2, iclass 36, count 2 2006.224.08:05:40.97#ibcon#flushed, iclass 36, count 2 2006.224.08:05:40.97#ibcon#about to write, iclass 36, count 2 2006.224.08:05:40.97#ibcon#wrote, iclass 36, count 2 2006.224.08:05:40.97#ibcon#about to read 3, iclass 36, count 2 2006.224.08:05:41.00#ibcon#read 3, iclass 36, count 2 2006.224.08:05:41.00#ibcon#about to read 4, iclass 36, count 2 2006.224.08:05:41.00#ibcon#read 4, iclass 36, count 2 2006.224.08:05:41.00#ibcon#about to read 5, iclass 36, count 2 2006.224.08:05:41.00#ibcon#read 5, iclass 36, count 2 2006.224.08:05:41.00#ibcon#about to read 6, iclass 36, count 2 2006.224.08:05:41.00#ibcon#read 6, iclass 36, count 2 2006.224.08:05:41.00#ibcon#end of sib2, iclass 36, count 2 2006.224.08:05:41.00#ibcon#*after write, iclass 36, count 2 2006.224.08:05:41.00#ibcon#*before return 0, iclass 36, count 2 2006.224.08:05:41.00#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.224.08:05:41.00#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.224.08:05:41.00#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.224.08:05:41.00#ibcon#ireg 7 cls_cnt 0 2006.224.08:05:41.00#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.224.08:05:41.12#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.224.08:05:41.12#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.224.08:05:41.12#ibcon#enter wrdev, iclass 36, count 0 2006.224.08:05:41.12#ibcon#first serial, iclass 36, count 0 2006.224.08:05:41.12#ibcon#enter sib2, iclass 36, count 0 2006.224.08:05:41.12#ibcon#flushed, iclass 36, count 0 2006.224.08:05:41.12#ibcon#about to write, iclass 36, count 0 2006.224.08:05:41.12#ibcon#wrote, iclass 36, count 0 2006.224.08:05:41.12#ibcon#about to read 3, iclass 36, count 0 2006.224.08:05:41.14#ibcon#read 3, iclass 36, count 0 2006.224.08:05:41.14#ibcon#about to read 4, iclass 36, count 0 2006.224.08:05:41.14#ibcon#read 4, iclass 36, count 0 2006.224.08:05:41.14#ibcon#about to read 5, iclass 36, count 0 2006.224.08:05:41.14#ibcon#read 5, iclass 36, count 0 2006.224.08:05:41.14#ibcon#about to read 6, iclass 36, count 0 2006.224.08:05:41.14#ibcon#read 6, iclass 36, count 0 2006.224.08:05:41.14#ibcon#end of sib2, iclass 36, count 0 2006.224.08:05:41.14#ibcon#*mode == 0, iclass 36, count 0 2006.224.08:05:41.14#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.224.08:05:41.14#ibcon#[27=USB\r\n] 2006.224.08:05:41.14#ibcon#*before write, iclass 36, count 0 2006.224.08:05:41.14#ibcon#enter sib2, iclass 36, count 0 2006.224.08:05:41.14#ibcon#flushed, iclass 36, count 0 2006.224.08:05:41.14#ibcon#about to write, iclass 36, count 0 2006.224.08:05:41.14#ibcon#wrote, iclass 36, count 0 2006.224.08:05:41.14#ibcon#about to read 3, iclass 36, count 0 2006.224.08:05:41.17#ibcon#read 3, iclass 36, count 0 2006.224.08:05:41.17#ibcon#about to read 4, iclass 36, count 0 2006.224.08:05:41.17#ibcon#read 4, iclass 36, count 0 2006.224.08:05:41.17#ibcon#about to read 5, iclass 36, count 0 2006.224.08:05:41.17#ibcon#read 5, iclass 36, count 0 2006.224.08:05:41.17#ibcon#about to read 6, iclass 36, count 0 2006.224.08:05:41.17#ibcon#read 6, iclass 36, count 0 2006.224.08:05:41.17#ibcon#end of sib2, iclass 36, count 0 2006.224.08:05:41.17#ibcon#*after write, iclass 36, count 0 2006.224.08:05:41.17#ibcon#*before return 0, iclass 36, count 0 2006.224.08:05:41.17#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.224.08:05:41.17#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.224.08:05:41.17#ibcon#about to clear, iclass 36 cls_cnt 0 2006.224.08:05:41.17#ibcon#cleared, iclass 36 cls_cnt 0 2006.224.08:05:41.17$vc4f8/vblo=3,656.99 2006.224.08:05:41.17#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.224.08:05:41.17#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.224.08:05:41.17#ibcon#ireg 17 cls_cnt 0 2006.224.08:05:41.17#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.224.08:05:41.17#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.224.08:05:41.17#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.224.08:05:41.17#ibcon#enter wrdev, iclass 38, count 0 2006.224.08:05:41.17#ibcon#first serial, iclass 38, count 0 2006.224.08:05:41.17#ibcon#enter sib2, iclass 38, count 0 2006.224.08:05:41.17#ibcon#flushed, iclass 38, count 0 2006.224.08:05:41.17#ibcon#about to write, iclass 38, count 0 2006.224.08:05:41.17#ibcon#wrote, iclass 38, count 0 2006.224.08:05:41.17#ibcon#about to read 3, iclass 38, count 0 2006.224.08:05:41.19#ibcon#read 3, iclass 38, count 0 2006.224.08:05:41.19#ibcon#about to read 4, iclass 38, count 0 2006.224.08:05:41.19#ibcon#read 4, iclass 38, count 0 2006.224.08:05:41.19#ibcon#about to read 5, iclass 38, count 0 2006.224.08:05:41.19#ibcon#read 5, iclass 38, count 0 2006.224.08:05:41.19#ibcon#about to read 6, iclass 38, count 0 2006.224.08:05:41.19#ibcon#read 6, iclass 38, count 0 2006.224.08:05:41.19#ibcon#end of sib2, iclass 38, count 0 2006.224.08:05:41.19#ibcon#*mode == 0, iclass 38, count 0 2006.224.08:05:41.19#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.224.08:05:41.19#ibcon#[28=FRQ=03,656.99\r\n] 2006.224.08:05:41.19#ibcon#*before write, iclass 38, count 0 2006.224.08:05:41.19#ibcon#enter sib2, iclass 38, count 0 2006.224.08:05:41.19#ibcon#flushed, iclass 38, count 0 2006.224.08:05:41.19#ibcon#about to write, iclass 38, count 0 2006.224.08:05:41.19#ibcon#wrote, iclass 38, count 0 2006.224.08:05:41.19#ibcon#about to read 3, iclass 38, count 0 2006.224.08:05:41.23#ibcon#read 3, iclass 38, count 0 2006.224.08:05:41.23#ibcon#about to read 4, iclass 38, count 0 2006.224.08:05:41.23#ibcon#read 4, iclass 38, count 0 2006.224.08:05:41.23#ibcon#about to read 5, iclass 38, count 0 2006.224.08:05:41.23#ibcon#read 5, iclass 38, count 0 2006.224.08:05:41.23#ibcon#about to read 6, iclass 38, count 0 2006.224.08:05:41.23#ibcon#read 6, iclass 38, count 0 2006.224.08:05:41.23#ibcon#end of sib2, iclass 38, count 0 2006.224.08:05:41.23#ibcon#*after write, iclass 38, count 0 2006.224.08:05:41.23#ibcon#*before return 0, iclass 38, count 0 2006.224.08:05:41.23#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.224.08:05:41.23#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.224.08:05:41.23#ibcon#about to clear, iclass 38 cls_cnt 0 2006.224.08:05:41.23#ibcon#cleared, iclass 38 cls_cnt 0 2006.224.08:05:41.23$vc4f8/vb=3,4 2006.224.08:05:41.23#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.224.08:05:41.23#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.224.08:05:41.23#ibcon#ireg 11 cls_cnt 2 2006.224.08:05:41.23#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.224.08:05:41.29#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.224.08:05:41.29#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.224.08:05:41.29#ibcon#enter wrdev, iclass 40, count 2 2006.224.08:05:41.29#ibcon#first serial, iclass 40, count 2 2006.224.08:05:41.29#ibcon#enter sib2, iclass 40, count 2 2006.224.08:05:41.29#ibcon#flushed, iclass 40, count 2 2006.224.08:05:41.29#ibcon#about to write, iclass 40, count 2 2006.224.08:05:41.29#ibcon#wrote, iclass 40, count 2 2006.224.08:05:41.30#ibcon#about to read 3, iclass 40, count 2 2006.224.08:05:41.31#ibcon#read 3, iclass 40, count 2 2006.224.08:05:41.31#ibcon#about to read 4, iclass 40, count 2 2006.224.08:05:41.31#ibcon#read 4, iclass 40, count 2 2006.224.08:05:41.31#ibcon#about to read 5, iclass 40, count 2 2006.224.08:05:41.31#ibcon#read 5, iclass 40, count 2 2006.224.08:05:41.31#ibcon#about to read 6, iclass 40, count 2 2006.224.08:05:41.31#ibcon#read 6, iclass 40, count 2 2006.224.08:05:41.31#ibcon#end of sib2, iclass 40, count 2 2006.224.08:05:41.31#ibcon#*mode == 0, iclass 40, count 2 2006.224.08:05:41.31#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.224.08:05:41.31#ibcon#[27=AT03-04\r\n] 2006.224.08:05:41.31#ibcon#*before write, iclass 40, count 2 2006.224.08:05:41.31#ibcon#enter sib2, iclass 40, count 2 2006.224.08:05:41.31#ibcon#flushed, iclass 40, count 2 2006.224.08:05:41.31#ibcon#about to write, iclass 40, count 2 2006.224.08:05:41.31#ibcon#wrote, iclass 40, count 2 2006.224.08:05:41.31#ibcon#about to read 3, iclass 40, count 2 2006.224.08:05:41.34#ibcon#read 3, iclass 40, count 2 2006.224.08:05:41.34#ibcon#about to read 4, iclass 40, count 2 2006.224.08:05:41.34#ibcon#read 4, iclass 40, count 2 2006.224.08:05:41.34#ibcon#about to read 5, iclass 40, count 2 2006.224.08:05:41.34#ibcon#read 5, iclass 40, count 2 2006.224.08:05:41.34#ibcon#about to read 6, iclass 40, count 2 2006.224.08:05:41.34#ibcon#read 6, iclass 40, count 2 2006.224.08:05:41.34#ibcon#end of sib2, iclass 40, count 2 2006.224.08:05:41.34#ibcon#*after write, iclass 40, count 2 2006.224.08:05:41.34#ibcon#*before return 0, iclass 40, count 2 2006.224.08:05:41.34#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.224.08:05:41.34#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.224.08:05:41.34#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.224.08:05:41.34#ibcon#ireg 7 cls_cnt 0 2006.224.08:05:41.34#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.224.08:05:41.46#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.224.08:05:41.46#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.224.08:05:41.46#ibcon#enter wrdev, iclass 40, count 0 2006.224.08:05:41.46#ibcon#first serial, iclass 40, count 0 2006.224.08:05:41.46#ibcon#enter sib2, iclass 40, count 0 2006.224.08:05:41.46#ibcon#flushed, iclass 40, count 0 2006.224.08:05:41.46#ibcon#about to write, iclass 40, count 0 2006.224.08:05:41.46#ibcon#wrote, iclass 40, count 0 2006.224.08:05:41.46#ibcon#about to read 3, iclass 40, count 0 2006.224.08:05:41.48#ibcon#read 3, iclass 40, count 0 2006.224.08:05:41.48#ibcon#about to read 4, iclass 40, count 0 2006.224.08:05:41.48#ibcon#read 4, iclass 40, count 0 2006.224.08:05:41.48#ibcon#about to read 5, iclass 40, count 0 2006.224.08:05:41.48#ibcon#read 5, iclass 40, count 0 2006.224.08:05:41.48#ibcon#about to read 6, iclass 40, count 0 2006.224.08:05:41.48#ibcon#read 6, iclass 40, count 0 2006.224.08:05:41.48#ibcon#end of sib2, iclass 40, count 0 2006.224.08:05:41.48#ibcon#*mode == 0, iclass 40, count 0 2006.224.08:05:41.48#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.224.08:05:41.48#ibcon#[27=USB\r\n] 2006.224.08:05:41.48#ibcon#*before write, iclass 40, count 0 2006.224.08:05:41.48#ibcon#enter sib2, iclass 40, count 0 2006.224.08:05:41.48#ibcon#flushed, iclass 40, count 0 2006.224.08:05:41.48#ibcon#about to write, iclass 40, count 0 2006.224.08:05:41.48#ibcon#wrote, iclass 40, count 0 2006.224.08:05:41.48#ibcon#about to read 3, iclass 40, count 0 2006.224.08:05:41.51#ibcon#read 3, iclass 40, count 0 2006.224.08:05:41.51#ibcon#about to read 4, iclass 40, count 0 2006.224.08:05:41.51#ibcon#read 4, iclass 40, count 0 2006.224.08:05:41.51#ibcon#about to read 5, iclass 40, count 0 2006.224.08:05:41.51#ibcon#read 5, iclass 40, count 0 2006.224.08:05:41.51#ibcon#about to read 6, iclass 40, count 0 2006.224.08:05:41.51#ibcon#read 6, iclass 40, count 0 2006.224.08:05:41.51#ibcon#end of sib2, iclass 40, count 0 2006.224.08:05:41.51#ibcon#*after write, iclass 40, count 0 2006.224.08:05:41.51#ibcon#*before return 0, iclass 40, count 0 2006.224.08:05:41.51#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.224.08:05:41.51#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.224.08:05:41.51#ibcon#about to clear, iclass 40 cls_cnt 0 2006.224.08:05:41.51#ibcon#cleared, iclass 40 cls_cnt 0 2006.224.08:05:41.51$vc4f8/vblo=4,712.99 2006.224.08:05:41.51#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.224.08:05:41.51#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.224.08:05:41.51#ibcon#ireg 17 cls_cnt 0 2006.224.08:05:41.51#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.224.08:05:41.51#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.224.08:05:41.51#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.224.08:05:41.51#ibcon#enter wrdev, iclass 4, count 0 2006.224.08:05:41.51#ibcon#first serial, iclass 4, count 0 2006.224.08:05:41.51#ibcon#enter sib2, iclass 4, count 0 2006.224.08:05:41.51#ibcon#flushed, iclass 4, count 0 2006.224.08:05:41.51#ibcon#about to write, iclass 4, count 0 2006.224.08:05:41.51#ibcon#wrote, iclass 4, count 0 2006.224.08:05:41.51#ibcon#about to read 3, iclass 4, count 0 2006.224.08:05:41.53#ibcon#read 3, iclass 4, count 0 2006.224.08:05:41.53#ibcon#about to read 4, iclass 4, count 0 2006.224.08:05:41.53#ibcon#read 4, iclass 4, count 0 2006.224.08:05:41.53#ibcon#about to read 5, iclass 4, count 0 2006.224.08:05:41.53#ibcon#read 5, iclass 4, count 0 2006.224.08:05:41.53#ibcon#about to read 6, iclass 4, count 0 2006.224.08:05:41.53#ibcon#read 6, iclass 4, count 0 2006.224.08:05:41.53#ibcon#end of sib2, iclass 4, count 0 2006.224.08:05:41.53#ibcon#*mode == 0, iclass 4, count 0 2006.224.08:05:41.53#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.224.08:05:41.53#ibcon#[28=FRQ=04,712.99\r\n] 2006.224.08:05:41.53#ibcon#*before write, iclass 4, count 0 2006.224.08:05:41.53#ibcon#enter sib2, iclass 4, count 0 2006.224.08:05:41.53#ibcon#flushed, iclass 4, count 0 2006.224.08:05:41.53#ibcon#about to write, iclass 4, count 0 2006.224.08:05:41.53#ibcon#wrote, iclass 4, count 0 2006.224.08:05:41.53#ibcon#about to read 3, iclass 4, count 0 2006.224.08:05:41.57#ibcon#read 3, iclass 4, count 0 2006.224.08:05:41.57#ibcon#about to read 4, iclass 4, count 0 2006.224.08:05:41.57#ibcon#read 4, iclass 4, count 0 2006.224.08:05:41.57#ibcon#about to read 5, iclass 4, count 0 2006.224.08:05:41.57#ibcon#read 5, iclass 4, count 0 2006.224.08:05:41.57#ibcon#about to read 6, iclass 4, count 0 2006.224.08:05:41.57#ibcon#read 6, iclass 4, count 0 2006.224.08:05:41.57#ibcon#end of sib2, iclass 4, count 0 2006.224.08:05:41.57#ibcon#*after write, iclass 4, count 0 2006.224.08:05:41.57#ibcon#*before return 0, iclass 4, count 0 2006.224.08:05:41.57#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.224.08:05:41.57#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.224.08:05:41.57#ibcon#about to clear, iclass 4 cls_cnt 0 2006.224.08:05:41.57#ibcon#cleared, iclass 4 cls_cnt 0 2006.224.08:05:41.57$vc4f8/vb=4,4 2006.224.08:05:41.57#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.224.08:05:41.57#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.224.08:05:41.57#ibcon#ireg 11 cls_cnt 2 2006.224.08:05:41.57#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.224.08:05:41.63#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.224.08:05:41.63#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.224.08:05:41.63#ibcon#enter wrdev, iclass 6, count 2 2006.224.08:05:41.63#ibcon#first serial, iclass 6, count 2 2006.224.08:05:41.63#ibcon#enter sib2, iclass 6, count 2 2006.224.08:05:41.63#ibcon#flushed, iclass 6, count 2 2006.224.08:05:41.63#ibcon#about to write, iclass 6, count 2 2006.224.08:05:41.63#ibcon#wrote, iclass 6, count 2 2006.224.08:05:41.63#ibcon#about to read 3, iclass 6, count 2 2006.224.08:05:41.65#ibcon#read 3, iclass 6, count 2 2006.224.08:05:41.65#ibcon#about to read 4, iclass 6, count 2 2006.224.08:05:41.65#ibcon#read 4, iclass 6, count 2 2006.224.08:05:41.65#ibcon#about to read 5, iclass 6, count 2 2006.224.08:05:41.65#ibcon#read 5, iclass 6, count 2 2006.224.08:05:41.65#ibcon#about to read 6, iclass 6, count 2 2006.224.08:05:41.65#ibcon#read 6, iclass 6, count 2 2006.224.08:05:41.65#ibcon#end of sib2, iclass 6, count 2 2006.224.08:05:41.65#ibcon#*mode == 0, iclass 6, count 2 2006.224.08:05:41.65#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.224.08:05:41.65#ibcon#[27=AT04-04\r\n] 2006.224.08:05:41.65#ibcon#*before write, iclass 6, count 2 2006.224.08:05:41.65#ibcon#enter sib2, iclass 6, count 2 2006.224.08:05:41.65#ibcon#flushed, iclass 6, count 2 2006.224.08:05:41.65#ibcon#about to write, iclass 6, count 2 2006.224.08:05:41.65#ibcon#wrote, iclass 6, count 2 2006.224.08:05:41.65#ibcon#about to read 3, iclass 6, count 2 2006.224.08:05:41.68#ibcon#read 3, iclass 6, count 2 2006.224.08:05:41.68#ibcon#about to read 4, iclass 6, count 2 2006.224.08:05:41.68#ibcon#read 4, iclass 6, count 2 2006.224.08:05:41.68#ibcon#about to read 5, iclass 6, count 2 2006.224.08:05:41.68#ibcon#read 5, iclass 6, count 2 2006.224.08:05:41.68#ibcon#about to read 6, iclass 6, count 2 2006.224.08:05:41.68#ibcon#read 6, iclass 6, count 2 2006.224.08:05:41.68#ibcon#end of sib2, iclass 6, count 2 2006.224.08:05:41.68#ibcon#*after write, iclass 6, count 2 2006.224.08:05:41.68#ibcon#*before return 0, iclass 6, count 2 2006.224.08:05:41.68#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.224.08:05:41.68#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.224.08:05:41.68#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.224.08:05:41.68#ibcon#ireg 7 cls_cnt 0 2006.224.08:05:41.68#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.224.08:05:41.80#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.224.08:05:41.80#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.224.08:05:41.80#ibcon#enter wrdev, iclass 6, count 0 2006.224.08:05:41.80#ibcon#first serial, iclass 6, count 0 2006.224.08:05:41.80#ibcon#enter sib2, iclass 6, count 0 2006.224.08:05:41.80#ibcon#flushed, iclass 6, count 0 2006.224.08:05:41.80#ibcon#about to write, iclass 6, count 0 2006.224.08:05:41.80#ibcon#wrote, iclass 6, count 0 2006.224.08:05:41.80#ibcon#about to read 3, iclass 6, count 0 2006.224.08:05:41.82#ibcon#read 3, iclass 6, count 0 2006.224.08:05:41.82#ibcon#about to read 4, iclass 6, count 0 2006.224.08:05:41.82#ibcon#read 4, iclass 6, count 0 2006.224.08:05:41.82#ibcon#about to read 5, iclass 6, count 0 2006.224.08:05:41.82#ibcon#read 5, iclass 6, count 0 2006.224.08:05:41.82#ibcon#about to read 6, iclass 6, count 0 2006.224.08:05:41.82#ibcon#read 6, iclass 6, count 0 2006.224.08:05:41.82#ibcon#end of sib2, iclass 6, count 0 2006.224.08:05:41.82#ibcon#*mode == 0, iclass 6, count 0 2006.224.08:05:41.82#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.224.08:05:41.82#ibcon#[27=USB\r\n] 2006.224.08:05:41.82#ibcon#*before write, iclass 6, count 0 2006.224.08:05:41.82#ibcon#enter sib2, iclass 6, count 0 2006.224.08:05:41.82#ibcon#flushed, iclass 6, count 0 2006.224.08:05:41.82#ibcon#about to write, iclass 6, count 0 2006.224.08:05:41.82#ibcon#wrote, iclass 6, count 0 2006.224.08:05:41.82#ibcon#about to read 3, iclass 6, count 0 2006.224.08:05:41.85#ibcon#read 3, iclass 6, count 0 2006.224.08:05:41.85#ibcon#about to read 4, iclass 6, count 0 2006.224.08:05:41.85#ibcon#read 4, iclass 6, count 0 2006.224.08:05:41.85#ibcon#about to read 5, iclass 6, count 0 2006.224.08:05:41.85#ibcon#read 5, iclass 6, count 0 2006.224.08:05:41.85#ibcon#about to read 6, iclass 6, count 0 2006.224.08:05:41.85#ibcon#read 6, iclass 6, count 0 2006.224.08:05:41.85#ibcon#end of sib2, iclass 6, count 0 2006.224.08:05:41.85#ibcon#*after write, iclass 6, count 0 2006.224.08:05:41.85#ibcon#*before return 0, iclass 6, count 0 2006.224.08:05:41.85#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.224.08:05:41.85#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.224.08:05:41.85#ibcon#about to clear, iclass 6 cls_cnt 0 2006.224.08:05:41.85#ibcon#cleared, iclass 6 cls_cnt 0 2006.224.08:05:41.85$vc4f8/vblo=5,744.99 2006.224.08:05:41.85#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.224.08:05:41.85#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.224.08:05:41.85#ibcon#ireg 17 cls_cnt 0 2006.224.08:05:41.85#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.224.08:05:41.85#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.224.08:05:41.85#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.224.08:05:41.85#ibcon#enter wrdev, iclass 10, count 0 2006.224.08:05:41.85#ibcon#first serial, iclass 10, count 0 2006.224.08:05:41.85#ibcon#enter sib2, iclass 10, count 0 2006.224.08:05:41.85#ibcon#flushed, iclass 10, count 0 2006.224.08:05:41.85#ibcon#about to write, iclass 10, count 0 2006.224.08:05:41.85#ibcon#wrote, iclass 10, count 0 2006.224.08:05:41.85#ibcon#about to read 3, iclass 10, count 0 2006.224.08:05:41.87#ibcon#read 3, iclass 10, count 0 2006.224.08:05:41.87#ibcon#about to read 4, iclass 10, count 0 2006.224.08:05:41.87#ibcon#read 4, iclass 10, count 0 2006.224.08:05:41.87#ibcon#about to read 5, iclass 10, count 0 2006.224.08:05:41.87#ibcon#read 5, iclass 10, count 0 2006.224.08:05:41.87#ibcon#about to read 6, iclass 10, count 0 2006.224.08:05:41.87#ibcon#read 6, iclass 10, count 0 2006.224.08:05:41.87#ibcon#end of sib2, iclass 10, count 0 2006.224.08:05:41.87#ibcon#*mode == 0, iclass 10, count 0 2006.224.08:05:41.87#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.224.08:05:41.87#ibcon#[28=FRQ=05,744.99\r\n] 2006.224.08:05:41.87#ibcon#*before write, iclass 10, count 0 2006.224.08:05:41.87#ibcon#enter sib2, iclass 10, count 0 2006.224.08:05:41.87#ibcon#flushed, iclass 10, count 0 2006.224.08:05:41.87#ibcon#about to write, iclass 10, count 0 2006.224.08:05:41.87#ibcon#wrote, iclass 10, count 0 2006.224.08:05:41.87#ibcon#about to read 3, iclass 10, count 0 2006.224.08:05:41.91#ibcon#read 3, iclass 10, count 0 2006.224.08:05:41.91#ibcon#about to read 4, iclass 10, count 0 2006.224.08:05:41.91#ibcon#read 4, iclass 10, count 0 2006.224.08:05:41.91#ibcon#about to read 5, iclass 10, count 0 2006.224.08:05:41.91#ibcon#read 5, iclass 10, count 0 2006.224.08:05:41.91#ibcon#about to read 6, iclass 10, count 0 2006.224.08:05:41.91#ibcon#read 6, iclass 10, count 0 2006.224.08:05:41.91#ibcon#end of sib2, iclass 10, count 0 2006.224.08:05:41.91#ibcon#*after write, iclass 10, count 0 2006.224.08:05:41.91#ibcon#*before return 0, iclass 10, count 0 2006.224.08:05:41.91#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.224.08:05:41.91#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.224.08:05:41.91#ibcon#about to clear, iclass 10 cls_cnt 0 2006.224.08:05:41.91#ibcon#cleared, iclass 10 cls_cnt 0 2006.224.08:05:41.91$vc4f8/vb=5,4 2006.224.08:05:41.91#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.224.08:05:41.91#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.224.08:05:41.91#ibcon#ireg 11 cls_cnt 2 2006.224.08:05:41.91#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.224.08:05:41.97#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.224.08:05:41.97#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.224.08:05:41.97#ibcon#enter wrdev, iclass 12, count 2 2006.224.08:05:41.97#ibcon#first serial, iclass 12, count 2 2006.224.08:05:41.97#ibcon#enter sib2, iclass 12, count 2 2006.224.08:05:41.97#ibcon#flushed, iclass 12, count 2 2006.224.08:05:41.97#ibcon#about to write, iclass 12, count 2 2006.224.08:05:41.97#ibcon#wrote, iclass 12, count 2 2006.224.08:05:41.97#ibcon#about to read 3, iclass 12, count 2 2006.224.08:05:41.99#ibcon#read 3, iclass 12, count 2 2006.224.08:05:41.99#ibcon#about to read 4, iclass 12, count 2 2006.224.08:05:41.99#ibcon#read 4, iclass 12, count 2 2006.224.08:05:41.99#ibcon#about to read 5, iclass 12, count 2 2006.224.08:05:41.99#ibcon#read 5, iclass 12, count 2 2006.224.08:05:41.99#ibcon#about to read 6, iclass 12, count 2 2006.224.08:05:41.99#ibcon#read 6, iclass 12, count 2 2006.224.08:05:41.99#ibcon#end of sib2, iclass 12, count 2 2006.224.08:05:41.99#ibcon#*mode == 0, iclass 12, count 2 2006.224.08:05:41.99#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.224.08:05:41.99#ibcon#[27=AT05-04\r\n] 2006.224.08:05:41.99#ibcon#*before write, iclass 12, count 2 2006.224.08:05:41.99#ibcon#enter sib2, iclass 12, count 2 2006.224.08:05:41.99#ibcon#flushed, iclass 12, count 2 2006.224.08:05:41.99#ibcon#about to write, iclass 12, count 2 2006.224.08:05:41.99#ibcon#wrote, iclass 12, count 2 2006.224.08:05:41.99#ibcon#about to read 3, iclass 12, count 2 2006.224.08:05:42.02#ibcon#read 3, iclass 12, count 2 2006.224.08:05:42.02#ibcon#about to read 4, iclass 12, count 2 2006.224.08:05:42.02#ibcon#read 4, iclass 12, count 2 2006.224.08:05:42.02#ibcon#about to read 5, iclass 12, count 2 2006.224.08:05:42.02#ibcon#read 5, iclass 12, count 2 2006.224.08:05:42.02#ibcon#about to read 6, iclass 12, count 2 2006.224.08:05:42.02#ibcon#read 6, iclass 12, count 2 2006.224.08:05:42.02#ibcon#end of sib2, iclass 12, count 2 2006.224.08:05:42.02#ibcon#*after write, iclass 12, count 2 2006.224.08:05:42.02#ibcon#*before return 0, iclass 12, count 2 2006.224.08:05:42.02#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.224.08:05:42.02#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.224.08:05:42.02#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.224.08:05:42.02#ibcon#ireg 7 cls_cnt 0 2006.224.08:05:42.02#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.224.08:05:42.14#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.224.08:05:42.14#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.224.08:05:42.14#ibcon#enter wrdev, iclass 12, count 0 2006.224.08:05:42.14#ibcon#first serial, iclass 12, count 0 2006.224.08:05:42.14#ibcon#enter sib2, iclass 12, count 0 2006.224.08:05:42.14#ibcon#flushed, iclass 12, count 0 2006.224.08:05:42.14#ibcon#about to write, iclass 12, count 0 2006.224.08:05:42.14#ibcon#wrote, iclass 12, count 0 2006.224.08:05:42.14#ibcon#about to read 3, iclass 12, count 0 2006.224.08:05:42.16#ibcon#read 3, iclass 12, count 0 2006.224.08:05:42.16#ibcon#about to read 4, iclass 12, count 0 2006.224.08:05:42.16#ibcon#read 4, iclass 12, count 0 2006.224.08:05:42.16#ibcon#about to read 5, iclass 12, count 0 2006.224.08:05:42.16#ibcon#read 5, iclass 12, count 0 2006.224.08:05:42.16#ibcon#about to read 6, iclass 12, count 0 2006.224.08:05:42.16#ibcon#read 6, iclass 12, count 0 2006.224.08:05:42.16#ibcon#end of sib2, iclass 12, count 0 2006.224.08:05:42.16#ibcon#*mode == 0, iclass 12, count 0 2006.224.08:05:42.16#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.224.08:05:42.16#ibcon#[27=USB\r\n] 2006.224.08:05:42.16#ibcon#*before write, iclass 12, count 0 2006.224.08:05:42.16#ibcon#enter sib2, iclass 12, count 0 2006.224.08:05:42.16#ibcon#flushed, iclass 12, count 0 2006.224.08:05:42.16#ibcon#about to write, iclass 12, count 0 2006.224.08:05:42.16#ibcon#wrote, iclass 12, count 0 2006.224.08:05:42.16#ibcon#about to read 3, iclass 12, count 0 2006.224.08:05:42.19#ibcon#read 3, iclass 12, count 0 2006.224.08:05:42.19#ibcon#about to read 4, iclass 12, count 0 2006.224.08:05:42.19#ibcon#read 4, iclass 12, count 0 2006.224.08:05:42.19#ibcon#about to read 5, iclass 12, count 0 2006.224.08:05:42.19#ibcon#read 5, iclass 12, count 0 2006.224.08:05:42.19#ibcon#about to read 6, iclass 12, count 0 2006.224.08:05:42.19#ibcon#read 6, iclass 12, count 0 2006.224.08:05:42.19#ibcon#end of sib2, iclass 12, count 0 2006.224.08:05:42.19#ibcon#*after write, iclass 12, count 0 2006.224.08:05:42.19#ibcon#*before return 0, iclass 12, count 0 2006.224.08:05:42.19#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.224.08:05:42.19#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.224.08:05:42.19#ibcon#about to clear, iclass 12 cls_cnt 0 2006.224.08:05:42.19#ibcon#cleared, iclass 12 cls_cnt 0 2006.224.08:05:42.19$vc4f8/vblo=6,752.99 2006.224.08:05:42.19#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.224.08:05:42.19#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.224.08:05:42.19#ibcon#ireg 17 cls_cnt 0 2006.224.08:05:42.19#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.224.08:05:42.19#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.224.08:05:42.19#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.224.08:05:42.19#ibcon#enter wrdev, iclass 14, count 0 2006.224.08:05:42.19#ibcon#first serial, iclass 14, count 0 2006.224.08:05:42.19#ibcon#enter sib2, iclass 14, count 0 2006.224.08:05:42.19#ibcon#flushed, iclass 14, count 0 2006.224.08:05:42.19#ibcon#about to write, iclass 14, count 0 2006.224.08:05:42.19#ibcon#wrote, iclass 14, count 0 2006.224.08:05:42.19#ibcon#about to read 3, iclass 14, count 0 2006.224.08:05:42.21#ibcon#read 3, iclass 14, count 0 2006.224.08:05:42.21#ibcon#about to read 4, iclass 14, count 0 2006.224.08:05:42.21#ibcon#read 4, iclass 14, count 0 2006.224.08:05:42.21#ibcon#about to read 5, iclass 14, count 0 2006.224.08:05:42.21#ibcon#read 5, iclass 14, count 0 2006.224.08:05:42.21#ibcon#about to read 6, iclass 14, count 0 2006.224.08:05:42.21#ibcon#read 6, iclass 14, count 0 2006.224.08:05:42.22#ibcon#end of sib2, iclass 14, count 0 2006.224.08:05:42.22#ibcon#*mode == 0, iclass 14, count 0 2006.224.08:05:42.22#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.224.08:05:42.22#ibcon#[28=FRQ=06,752.99\r\n] 2006.224.08:05:42.22#ibcon#*before write, iclass 14, count 0 2006.224.08:05:42.22#ibcon#enter sib2, iclass 14, count 0 2006.224.08:05:42.22#ibcon#flushed, iclass 14, count 0 2006.224.08:05:42.22#ibcon#about to write, iclass 14, count 0 2006.224.08:05:42.22#ibcon#wrote, iclass 14, count 0 2006.224.08:05:42.22#ibcon#about to read 3, iclass 14, count 0 2006.224.08:05:42.26#ibcon#read 3, iclass 14, count 0 2006.224.08:05:42.26#ibcon#about to read 4, iclass 14, count 0 2006.224.08:05:42.26#ibcon#read 4, iclass 14, count 0 2006.224.08:05:42.26#ibcon#about to read 5, iclass 14, count 0 2006.224.08:05:42.26#ibcon#read 5, iclass 14, count 0 2006.224.08:05:42.26#ibcon#about to read 6, iclass 14, count 0 2006.224.08:05:42.26#ibcon#read 6, iclass 14, count 0 2006.224.08:05:42.26#ibcon#end of sib2, iclass 14, count 0 2006.224.08:05:42.26#ibcon#*after write, iclass 14, count 0 2006.224.08:05:42.26#ibcon#*before return 0, iclass 14, count 0 2006.224.08:05:42.26#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.224.08:05:42.26#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.224.08:05:42.26#ibcon#about to clear, iclass 14 cls_cnt 0 2006.224.08:05:42.26#ibcon#cleared, iclass 14 cls_cnt 0 2006.224.08:05:42.26$vc4f8/vb=6,4 2006.224.08:05:42.26#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.224.08:05:42.26#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.224.08:05:42.26#ibcon#ireg 11 cls_cnt 2 2006.224.08:05:42.26#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.224.08:05:42.31#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.224.08:05:42.31#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.224.08:05:42.31#ibcon#enter wrdev, iclass 16, count 2 2006.224.08:05:42.31#ibcon#first serial, iclass 16, count 2 2006.224.08:05:42.31#ibcon#enter sib2, iclass 16, count 2 2006.224.08:05:42.31#ibcon#flushed, iclass 16, count 2 2006.224.08:05:42.31#ibcon#about to write, iclass 16, count 2 2006.224.08:05:42.31#ibcon#wrote, iclass 16, count 2 2006.224.08:05:42.31#ibcon#about to read 3, iclass 16, count 2 2006.224.08:05:42.33#ibcon#read 3, iclass 16, count 2 2006.224.08:05:42.33#ibcon#about to read 4, iclass 16, count 2 2006.224.08:05:42.33#ibcon#read 4, iclass 16, count 2 2006.224.08:05:42.33#ibcon#about to read 5, iclass 16, count 2 2006.224.08:05:42.33#ibcon#read 5, iclass 16, count 2 2006.224.08:05:42.33#ibcon#about to read 6, iclass 16, count 2 2006.224.08:05:42.33#ibcon#read 6, iclass 16, count 2 2006.224.08:05:42.33#ibcon#end of sib2, iclass 16, count 2 2006.224.08:05:42.33#ibcon#*mode == 0, iclass 16, count 2 2006.224.08:05:42.33#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.224.08:05:42.33#ibcon#[27=AT06-04\r\n] 2006.224.08:05:42.33#ibcon#*before write, iclass 16, count 2 2006.224.08:05:42.33#ibcon#enter sib2, iclass 16, count 2 2006.224.08:05:42.33#ibcon#flushed, iclass 16, count 2 2006.224.08:05:42.33#ibcon#about to write, iclass 16, count 2 2006.224.08:05:42.33#ibcon#wrote, iclass 16, count 2 2006.224.08:05:42.33#ibcon#about to read 3, iclass 16, count 2 2006.224.08:05:42.36#ibcon#read 3, iclass 16, count 2 2006.224.08:05:42.36#ibcon#about to read 4, iclass 16, count 2 2006.224.08:05:42.36#ibcon#read 4, iclass 16, count 2 2006.224.08:05:42.36#ibcon#about to read 5, iclass 16, count 2 2006.224.08:05:42.36#ibcon#read 5, iclass 16, count 2 2006.224.08:05:42.36#ibcon#about to read 6, iclass 16, count 2 2006.224.08:05:42.36#ibcon#read 6, iclass 16, count 2 2006.224.08:05:42.36#ibcon#end of sib2, iclass 16, count 2 2006.224.08:05:42.36#ibcon#*after write, iclass 16, count 2 2006.224.08:05:42.36#ibcon#*before return 0, iclass 16, count 2 2006.224.08:05:42.36#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.224.08:05:42.36#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.224.08:05:42.36#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.224.08:05:42.36#ibcon#ireg 7 cls_cnt 0 2006.224.08:05:42.36#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.224.08:05:42.48#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.224.08:05:42.48#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.224.08:05:42.48#ibcon#enter wrdev, iclass 16, count 0 2006.224.08:05:42.48#ibcon#first serial, iclass 16, count 0 2006.224.08:05:42.48#ibcon#enter sib2, iclass 16, count 0 2006.224.08:05:42.48#ibcon#flushed, iclass 16, count 0 2006.224.08:05:42.48#ibcon#about to write, iclass 16, count 0 2006.224.08:05:42.48#ibcon#wrote, iclass 16, count 0 2006.224.08:05:42.48#ibcon#about to read 3, iclass 16, count 0 2006.224.08:05:42.50#ibcon#read 3, iclass 16, count 0 2006.224.08:05:42.50#ibcon#about to read 4, iclass 16, count 0 2006.224.08:05:42.50#ibcon#read 4, iclass 16, count 0 2006.224.08:05:42.50#ibcon#about to read 5, iclass 16, count 0 2006.224.08:05:42.50#ibcon#read 5, iclass 16, count 0 2006.224.08:05:42.50#ibcon#about to read 6, iclass 16, count 0 2006.224.08:05:42.50#ibcon#read 6, iclass 16, count 0 2006.224.08:05:42.50#ibcon#end of sib2, iclass 16, count 0 2006.224.08:05:42.50#ibcon#*mode == 0, iclass 16, count 0 2006.224.08:05:42.50#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.224.08:05:42.50#ibcon#[27=USB\r\n] 2006.224.08:05:42.50#ibcon#*before write, iclass 16, count 0 2006.224.08:05:42.50#ibcon#enter sib2, iclass 16, count 0 2006.224.08:05:42.50#ibcon#flushed, iclass 16, count 0 2006.224.08:05:42.50#ibcon#about to write, iclass 16, count 0 2006.224.08:05:42.50#ibcon#wrote, iclass 16, count 0 2006.224.08:05:42.50#ibcon#about to read 3, iclass 16, count 0 2006.224.08:05:42.53#ibcon#read 3, iclass 16, count 0 2006.224.08:05:42.53#ibcon#about to read 4, iclass 16, count 0 2006.224.08:05:42.53#ibcon#read 4, iclass 16, count 0 2006.224.08:05:42.53#ibcon#about to read 5, iclass 16, count 0 2006.224.08:05:42.53#ibcon#read 5, iclass 16, count 0 2006.224.08:05:42.53#ibcon#about to read 6, iclass 16, count 0 2006.224.08:05:42.53#ibcon#read 6, iclass 16, count 0 2006.224.08:05:42.53#ibcon#end of sib2, iclass 16, count 0 2006.224.08:05:42.53#ibcon#*after write, iclass 16, count 0 2006.224.08:05:42.53#ibcon#*before return 0, iclass 16, count 0 2006.224.08:05:42.53#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.224.08:05:42.53#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.224.08:05:42.53#ibcon#about to clear, iclass 16 cls_cnt 0 2006.224.08:05:42.53#ibcon#cleared, iclass 16 cls_cnt 0 2006.224.08:05:42.53$vc4f8/vabw=wide 2006.224.08:05:42.53#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.224.08:05:42.53#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.224.08:05:42.53#ibcon#ireg 8 cls_cnt 0 2006.224.08:05:42.53#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.224.08:05:42.53#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.224.08:05:42.53#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.224.08:05:42.53#ibcon#enter wrdev, iclass 18, count 0 2006.224.08:05:42.53#ibcon#first serial, iclass 18, count 0 2006.224.08:05:42.53#ibcon#enter sib2, iclass 18, count 0 2006.224.08:05:42.53#ibcon#flushed, iclass 18, count 0 2006.224.08:05:42.53#ibcon#about to write, iclass 18, count 0 2006.224.08:05:42.53#ibcon#wrote, iclass 18, count 0 2006.224.08:05:42.53#ibcon#about to read 3, iclass 18, count 0 2006.224.08:05:42.55#ibcon#read 3, iclass 18, count 0 2006.224.08:05:42.55#ibcon#about to read 4, iclass 18, count 0 2006.224.08:05:42.55#ibcon#read 4, iclass 18, count 0 2006.224.08:05:42.55#ibcon#about to read 5, iclass 18, count 0 2006.224.08:05:42.55#ibcon#read 5, iclass 18, count 0 2006.224.08:05:42.55#ibcon#about to read 6, iclass 18, count 0 2006.224.08:05:42.55#ibcon#read 6, iclass 18, count 0 2006.224.08:05:42.55#ibcon#end of sib2, iclass 18, count 0 2006.224.08:05:42.55#ibcon#*mode == 0, iclass 18, count 0 2006.224.08:05:42.55#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.224.08:05:42.55#ibcon#[25=BW32\r\n] 2006.224.08:05:42.55#ibcon#*before write, iclass 18, count 0 2006.224.08:05:42.55#ibcon#enter sib2, iclass 18, count 0 2006.224.08:05:42.55#ibcon#flushed, iclass 18, count 0 2006.224.08:05:42.55#ibcon#about to write, iclass 18, count 0 2006.224.08:05:42.55#ibcon#wrote, iclass 18, count 0 2006.224.08:05:42.55#ibcon#about to read 3, iclass 18, count 0 2006.224.08:05:42.58#ibcon#read 3, iclass 18, count 0 2006.224.08:05:42.58#ibcon#about to read 4, iclass 18, count 0 2006.224.08:05:42.58#ibcon#read 4, iclass 18, count 0 2006.224.08:05:42.58#ibcon#about to read 5, iclass 18, count 0 2006.224.08:05:42.58#ibcon#read 5, iclass 18, count 0 2006.224.08:05:42.58#ibcon#about to read 6, iclass 18, count 0 2006.224.08:05:42.58#ibcon#read 6, iclass 18, count 0 2006.224.08:05:42.58#ibcon#end of sib2, iclass 18, count 0 2006.224.08:05:42.58#ibcon#*after write, iclass 18, count 0 2006.224.08:05:42.58#ibcon#*before return 0, iclass 18, count 0 2006.224.08:05:42.58#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.224.08:05:42.58#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.224.08:05:42.58#ibcon#about to clear, iclass 18 cls_cnt 0 2006.224.08:05:42.58#ibcon#cleared, iclass 18 cls_cnt 0 2006.224.08:05:42.58$vc4f8/vbbw=wide 2006.224.08:05:42.58#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.224.08:05:42.58#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.224.08:05:42.58#ibcon#ireg 8 cls_cnt 0 2006.224.08:05:42.58#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.224.08:05:42.65#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.224.08:05:42.65#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.224.08:05:42.65#ibcon#enter wrdev, iclass 20, count 0 2006.224.08:05:42.65#ibcon#first serial, iclass 20, count 0 2006.224.08:05:42.65#ibcon#enter sib2, iclass 20, count 0 2006.224.08:05:42.65#ibcon#flushed, iclass 20, count 0 2006.224.08:05:42.65#ibcon#about to write, iclass 20, count 0 2006.224.08:05:42.65#ibcon#wrote, iclass 20, count 0 2006.224.08:05:42.65#ibcon#about to read 3, iclass 20, count 0 2006.224.08:05:42.67#ibcon#read 3, iclass 20, count 0 2006.224.08:05:42.67#ibcon#about to read 4, iclass 20, count 0 2006.224.08:05:42.67#ibcon#read 4, iclass 20, count 0 2006.224.08:05:42.67#ibcon#about to read 5, iclass 20, count 0 2006.224.08:05:42.67#ibcon#read 5, iclass 20, count 0 2006.224.08:05:42.67#ibcon#about to read 6, iclass 20, count 0 2006.224.08:05:42.67#ibcon#read 6, iclass 20, count 0 2006.224.08:05:42.67#ibcon#end of sib2, iclass 20, count 0 2006.224.08:05:42.67#ibcon#*mode == 0, iclass 20, count 0 2006.224.08:05:42.67#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.224.08:05:42.67#ibcon#[27=BW32\r\n] 2006.224.08:05:42.67#ibcon#*before write, iclass 20, count 0 2006.224.08:05:42.67#ibcon#enter sib2, iclass 20, count 0 2006.224.08:05:42.67#ibcon#flushed, iclass 20, count 0 2006.224.08:05:42.67#ibcon#about to write, iclass 20, count 0 2006.224.08:05:42.67#ibcon#wrote, iclass 20, count 0 2006.224.08:05:42.67#ibcon#about to read 3, iclass 20, count 0 2006.224.08:05:42.70#ibcon#read 3, iclass 20, count 0 2006.224.08:05:42.70#ibcon#about to read 4, iclass 20, count 0 2006.224.08:05:42.70#ibcon#read 4, iclass 20, count 0 2006.224.08:05:42.70#ibcon#about to read 5, iclass 20, count 0 2006.224.08:05:42.70#ibcon#read 5, iclass 20, count 0 2006.224.08:05:42.70#ibcon#about to read 6, iclass 20, count 0 2006.224.08:05:42.70#ibcon#read 6, iclass 20, count 0 2006.224.08:05:42.70#ibcon#end of sib2, iclass 20, count 0 2006.224.08:05:42.70#ibcon#*after write, iclass 20, count 0 2006.224.08:05:42.70#ibcon#*before return 0, iclass 20, count 0 2006.224.08:05:42.70#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.224.08:05:42.70#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.224.08:05:42.70#ibcon#about to clear, iclass 20 cls_cnt 0 2006.224.08:05:42.70#ibcon#cleared, iclass 20 cls_cnt 0 2006.224.08:05:42.70$4f8m12a/ifd4f 2006.224.08:05:42.70$ifd4f/lo= 2006.224.08:05:42.70$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.224.08:05:42.70$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.224.08:05:42.70$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.224.08:05:42.70$ifd4f/patch= 2006.224.08:05:42.70$ifd4f/patch=lo1,a1,a2,a3,a4 2006.224.08:05:42.70$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.224.08:05:42.70$ifd4f/patch=lo3,a5,a6,a7,a8 2006.224.08:05:42.70$4f8m12a/"form=m,16.000,1:2 2006.224.08:05:42.70$4f8m12a/"tpicd 2006.224.08:05:42.70$4f8m12a/echo=off 2006.224.08:05:42.70$4f8m12a/xlog=off 2006.224.08:05:42.70:!2006.224.08:06:10 2006.224.08:05:52.14#trakl#Source acquired 2006.224.08:05:52.14#flagr#flagr/antenna,acquired 2006.224.08:06:10.00:preob 2006.224.08:06:11.14/onsource/TRACKING 2006.224.08:06:11.14:!2006.224.08:06:20 2006.224.08:06:20.00:data_valid=on 2006.224.08:06:20.00:midob 2006.224.08:06:20.14/onsource/TRACKING 2006.224.08:06:20.14/wx/23.65,1004.7,100 2006.224.08:06:20.26/cable/+6.4336E-03 2006.224.08:06:21.35/va/01,08,usb,yes,42,45 2006.224.08:06:21.35/va/02,07,usb,yes,43,45 2006.224.08:06:21.35/va/03,06,usb,yes,46,46 2006.224.08:06:21.35/va/04,07,usb,yes,45,48 2006.224.08:06:21.35/va/05,07,usb,yes,52,54 2006.224.08:06:21.35/va/06,06,usb,yes,51,51 2006.224.08:06:21.35/va/07,06,usb,yes,52,52 2006.224.08:06:21.35/va/08,07,usb,yes,49,48 2006.224.08:06:21.58/valo/01,532.99,yes,locked 2006.224.08:06:21.58/valo/02,572.99,yes,locked 2006.224.08:06:21.58/valo/03,672.99,yes,locked 2006.224.08:06:21.58/valo/04,832.99,yes,locked 2006.224.08:06:21.58/valo/05,652.99,yes,locked 2006.224.08:06:21.58/valo/06,772.99,yes,locked 2006.224.08:06:21.58/valo/07,832.99,yes,locked 2006.224.08:06:21.58/valo/08,852.99,yes,locked 2006.224.08:06:22.67/vb/01,04,usb,yes,31,30 2006.224.08:06:22.67/vb/02,04,usb,yes,33,35 2006.224.08:06:22.67/vb/03,04,usb,yes,30,33 2006.224.08:06:22.67/vb/04,04,usb,yes,30,31 2006.224.08:06:22.67/vb/05,04,usb,yes,29,33 2006.224.08:06:22.67/vb/06,04,usb,yes,30,33 2006.224.08:06:22.67/vb/07,04,usb,yes,32,32 2006.224.08:06:22.67/vb/08,04,usb,yes,29,33 2006.224.08:06:22.91/vblo/01,632.99,yes,locked 2006.224.08:06:22.91/vblo/02,640.99,yes,locked 2006.224.08:06:22.91/vblo/03,656.99,yes,locked 2006.224.08:06:22.91/vblo/04,712.99,yes,locked 2006.224.08:06:22.91/vblo/05,744.99,yes,locked 2006.224.08:06:22.91/vblo/06,752.99,yes,locked 2006.224.08:06:22.91/vblo/07,734.99,yes,locked 2006.224.08:06:22.91/vblo/08,744.99,yes,locked 2006.224.08:06:23.06/vabw/8 2006.224.08:06:23.21/vbbw/8 2006.224.08:06:23.39/xfe/off,on,15.5 2006.224.08:06:23.78/ifatt/23,28,28,28 2006.224.08:06:24.07/fmout-gps/S +4.47E-07 2006.224.08:06:24.11:!2006.224.08:07:20 2006.224.08:07:20.00:data_valid=off 2006.224.08:07:20.00:postob 2006.224.08:07:20.06/cable/+6.4339E-03 2006.224.08:07:20.06/wx/23.66,1004.7,100 2006.224.08:07:21.08/fmout-gps/S +4.49E-07 2006.224.08:07:21.08:scan_name=224-0808,k06224,60 2006.224.08:07:21.08:source=3c418,203837.03,511912.7,2000.0,cw 2006.224.08:07:21.14#flagr#flagr/antenna,new-source 2006.224.08:07:22.14:checkk5 2006.224.08:07:22.51/chk_autoobs//k5ts1/ autoobs is running! 2006.224.08:07:22.88/chk_autoobs//k5ts2/ autoobs is running! 2006.224.08:07:23.26/chk_autoobs//k5ts3/ autoobs is running! 2006.224.08:07:23.63/chk_autoobs//k5ts4/ autoobs is running! 2006.224.08:07:23.99/chk_obsdata//k5ts1/T2240806??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.08:07:24.35/chk_obsdata//k5ts2/T2240806??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.08:07:24.72/chk_obsdata//k5ts3/T2240806??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.08:07:25.08/chk_obsdata//k5ts4/T2240806??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.08:07:25.76/k5log//k5ts1_log_newline 2006.224.08:07:26.45/k5log//k5ts2_log_newline 2006.224.08:07:27.14/k5log//k5ts3_log_newline 2006.224.08:07:27.82/k5log//k5ts4_log_newline 2006.224.08:07:27.84/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.224.08:07:27.84:4f8m12a=2 2006.224.08:07:27.84$4f8m12a/echo=on 2006.224.08:07:27.84$4f8m12a/pcalon 2006.224.08:07:27.84$pcalon/"no phase cal control is implemented here 2006.224.08:07:27.84$4f8m12a/"tpicd=stop 2006.224.08:07:27.84$4f8m12a/vc4f8 2006.224.08:07:27.84$vc4f8/valo=1,532.99 2006.224.08:07:27.85#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.224.08:07:27.85#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.224.08:07:27.85#ibcon#ireg 17 cls_cnt 0 2006.224.08:07:27.85#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.224.08:07:27.85#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.224.08:07:27.85#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.224.08:07:27.85#ibcon#enter wrdev, iclass 27, count 0 2006.224.08:07:27.85#ibcon#first serial, iclass 27, count 0 2006.224.08:07:27.85#ibcon#enter sib2, iclass 27, count 0 2006.224.08:07:27.85#ibcon#flushed, iclass 27, count 0 2006.224.08:07:27.85#ibcon#about to write, iclass 27, count 0 2006.224.08:07:27.85#ibcon#wrote, iclass 27, count 0 2006.224.08:07:27.85#ibcon#about to read 3, iclass 27, count 0 2006.224.08:07:27.89#ibcon#read 3, iclass 27, count 0 2006.224.08:07:27.89#ibcon#about to read 4, iclass 27, count 0 2006.224.08:07:27.89#ibcon#read 4, iclass 27, count 0 2006.224.08:07:27.89#ibcon#about to read 5, iclass 27, count 0 2006.224.08:07:27.89#ibcon#read 5, iclass 27, count 0 2006.224.08:07:27.89#ibcon#about to read 6, iclass 27, count 0 2006.224.08:07:27.89#ibcon#read 6, iclass 27, count 0 2006.224.08:07:27.89#ibcon#end of sib2, iclass 27, count 0 2006.224.08:07:27.89#ibcon#*mode == 0, iclass 27, count 0 2006.224.08:07:27.89#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.224.08:07:27.89#ibcon#[26=FRQ=01,532.99\r\n] 2006.224.08:07:27.89#ibcon#*before write, iclass 27, count 0 2006.224.08:07:27.89#ibcon#enter sib2, iclass 27, count 0 2006.224.08:07:27.89#ibcon#flushed, iclass 27, count 0 2006.224.08:07:27.89#ibcon#about to write, iclass 27, count 0 2006.224.08:07:27.89#ibcon#wrote, iclass 27, count 0 2006.224.08:07:27.89#ibcon#about to read 3, iclass 27, count 0 2006.224.08:07:27.94#ibcon#read 3, iclass 27, count 0 2006.224.08:07:27.94#ibcon#about to read 4, iclass 27, count 0 2006.224.08:07:27.94#ibcon#read 4, iclass 27, count 0 2006.224.08:07:27.94#ibcon#about to read 5, iclass 27, count 0 2006.224.08:07:27.94#ibcon#read 5, iclass 27, count 0 2006.224.08:07:27.94#ibcon#about to read 6, iclass 27, count 0 2006.224.08:07:27.94#ibcon#read 6, iclass 27, count 0 2006.224.08:07:27.94#ibcon#end of sib2, iclass 27, count 0 2006.224.08:07:27.94#ibcon#*after write, iclass 27, count 0 2006.224.08:07:27.94#ibcon#*before return 0, iclass 27, count 0 2006.224.08:07:27.94#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.224.08:07:27.94#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.224.08:07:27.94#ibcon#about to clear, iclass 27 cls_cnt 0 2006.224.08:07:27.94#ibcon#cleared, iclass 27 cls_cnt 0 2006.224.08:07:27.94$vc4f8/va=1,8 2006.224.08:07:27.94#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.224.08:07:27.94#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.224.08:07:27.94#ibcon#ireg 11 cls_cnt 2 2006.224.08:07:27.94#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.224.08:07:27.94#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.224.08:07:27.94#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.224.08:07:27.94#ibcon#enter wrdev, iclass 29, count 2 2006.224.08:07:27.94#ibcon#first serial, iclass 29, count 2 2006.224.08:07:27.94#ibcon#enter sib2, iclass 29, count 2 2006.224.08:07:27.94#ibcon#flushed, iclass 29, count 2 2006.224.08:07:27.94#ibcon#about to write, iclass 29, count 2 2006.224.08:07:27.94#ibcon#wrote, iclass 29, count 2 2006.224.08:07:27.94#ibcon#about to read 3, iclass 29, count 2 2006.224.08:07:27.96#ibcon#read 3, iclass 29, count 2 2006.224.08:07:27.96#ibcon#about to read 4, iclass 29, count 2 2006.224.08:07:27.96#ibcon#read 4, iclass 29, count 2 2006.224.08:07:27.96#ibcon#about to read 5, iclass 29, count 2 2006.224.08:07:27.96#ibcon#read 5, iclass 29, count 2 2006.224.08:07:27.96#ibcon#about to read 6, iclass 29, count 2 2006.224.08:07:27.96#ibcon#read 6, iclass 29, count 2 2006.224.08:07:27.96#ibcon#end of sib2, iclass 29, count 2 2006.224.08:07:27.96#ibcon#*mode == 0, iclass 29, count 2 2006.224.08:07:27.96#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.224.08:07:27.96#ibcon#[25=AT01-08\r\n] 2006.224.08:07:27.96#ibcon#*before write, iclass 29, count 2 2006.224.08:07:27.96#ibcon#enter sib2, iclass 29, count 2 2006.224.08:07:27.96#ibcon#flushed, iclass 29, count 2 2006.224.08:07:27.96#ibcon#about to write, iclass 29, count 2 2006.224.08:07:27.96#ibcon#wrote, iclass 29, count 2 2006.224.08:07:27.96#ibcon#about to read 3, iclass 29, count 2 2006.224.08:07:27.99#ibcon#read 3, iclass 29, count 2 2006.224.08:07:27.99#ibcon#about to read 4, iclass 29, count 2 2006.224.08:07:27.99#ibcon#read 4, iclass 29, count 2 2006.224.08:07:27.99#ibcon#about to read 5, iclass 29, count 2 2006.224.08:07:27.99#ibcon#read 5, iclass 29, count 2 2006.224.08:07:27.99#ibcon#about to read 6, iclass 29, count 2 2006.224.08:07:27.99#ibcon#read 6, iclass 29, count 2 2006.224.08:07:27.99#ibcon#end of sib2, iclass 29, count 2 2006.224.08:07:27.99#ibcon#*after write, iclass 29, count 2 2006.224.08:07:27.99#ibcon#*before return 0, iclass 29, count 2 2006.224.08:07:27.99#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.224.08:07:27.99#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.224.08:07:27.99#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.224.08:07:27.99#ibcon#ireg 7 cls_cnt 0 2006.224.08:07:27.99#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.224.08:07:28.11#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.224.08:07:28.11#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.224.08:07:28.11#ibcon#enter wrdev, iclass 29, count 0 2006.224.08:07:28.11#ibcon#first serial, iclass 29, count 0 2006.224.08:07:28.11#ibcon#enter sib2, iclass 29, count 0 2006.224.08:07:28.11#ibcon#flushed, iclass 29, count 0 2006.224.08:07:28.11#ibcon#about to write, iclass 29, count 0 2006.224.08:07:28.11#ibcon#wrote, iclass 29, count 0 2006.224.08:07:28.11#ibcon#about to read 3, iclass 29, count 0 2006.224.08:07:28.13#ibcon#read 3, iclass 29, count 0 2006.224.08:07:28.13#ibcon#about to read 4, iclass 29, count 0 2006.224.08:07:28.13#ibcon#read 4, iclass 29, count 0 2006.224.08:07:28.13#ibcon#about to read 5, iclass 29, count 0 2006.224.08:07:28.13#ibcon#read 5, iclass 29, count 0 2006.224.08:07:28.13#ibcon#about to read 6, iclass 29, count 0 2006.224.08:07:28.13#ibcon#read 6, iclass 29, count 0 2006.224.08:07:28.13#ibcon#end of sib2, iclass 29, count 0 2006.224.08:07:28.13#ibcon#*mode == 0, iclass 29, count 0 2006.224.08:07:28.13#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.224.08:07:28.13#ibcon#[25=USB\r\n] 2006.224.08:07:28.13#ibcon#*before write, iclass 29, count 0 2006.224.08:07:28.13#ibcon#enter sib2, iclass 29, count 0 2006.224.08:07:28.13#ibcon#flushed, iclass 29, count 0 2006.224.08:07:28.13#ibcon#about to write, iclass 29, count 0 2006.224.08:07:28.13#ibcon#wrote, iclass 29, count 0 2006.224.08:07:28.13#ibcon#about to read 3, iclass 29, count 0 2006.224.08:07:28.16#ibcon#read 3, iclass 29, count 0 2006.224.08:07:28.16#ibcon#about to read 4, iclass 29, count 0 2006.224.08:07:28.16#ibcon#read 4, iclass 29, count 0 2006.224.08:07:28.16#ibcon#about to read 5, iclass 29, count 0 2006.224.08:07:28.16#ibcon#read 5, iclass 29, count 0 2006.224.08:07:28.16#ibcon#about to read 6, iclass 29, count 0 2006.224.08:07:28.16#ibcon#read 6, iclass 29, count 0 2006.224.08:07:28.16#ibcon#end of sib2, iclass 29, count 0 2006.224.08:07:28.16#ibcon#*after write, iclass 29, count 0 2006.224.08:07:28.16#ibcon#*before return 0, iclass 29, count 0 2006.224.08:07:28.16#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.224.08:07:28.16#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.224.08:07:28.16#ibcon#about to clear, iclass 29 cls_cnt 0 2006.224.08:07:28.16#ibcon#cleared, iclass 29 cls_cnt 0 2006.224.08:07:28.16$vc4f8/valo=2,572.99 2006.224.08:07:28.16#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.224.08:07:28.16#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.224.08:07:28.16#ibcon#ireg 17 cls_cnt 0 2006.224.08:07:28.16#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.224.08:07:28.16#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.224.08:07:28.16#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.224.08:07:28.16#ibcon#enter wrdev, iclass 31, count 0 2006.224.08:07:28.16#ibcon#first serial, iclass 31, count 0 2006.224.08:07:28.16#ibcon#enter sib2, iclass 31, count 0 2006.224.08:07:28.16#ibcon#flushed, iclass 31, count 0 2006.224.08:07:28.16#ibcon#about to write, iclass 31, count 0 2006.224.08:07:28.16#ibcon#wrote, iclass 31, count 0 2006.224.08:07:28.16#ibcon#about to read 3, iclass 31, count 0 2006.224.08:07:28.18#ibcon#read 3, iclass 31, count 0 2006.224.08:07:28.18#ibcon#about to read 4, iclass 31, count 0 2006.224.08:07:28.18#ibcon#read 4, iclass 31, count 0 2006.224.08:07:28.18#ibcon#about to read 5, iclass 31, count 0 2006.224.08:07:28.18#ibcon#read 5, iclass 31, count 0 2006.224.08:07:28.18#ibcon#about to read 6, iclass 31, count 0 2006.224.08:07:28.18#ibcon#read 6, iclass 31, count 0 2006.224.08:07:28.18#ibcon#end of sib2, iclass 31, count 0 2006.224.08:07:28.18#ibcon#*mode == 0, iclass 31, count 0 2006.224.08:07:28.18#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.224.08:07:28.18#ibcon#[26=FRQ=02,572.99\r\n] 2006.224.08:07:28.18#ibcon#*before write, iclass 31, count 0 2006.224.08:07:28.18#ibcon#enter sib2, iclass 31, count 0 2006.224.08:07:28.18#ibcon#flushed, iclass 31, count 0 2006.224.08:07:28.18#ibcon#about to write, iclass 31, count 0 2006.224.08:07:28.18#ibcon#wrote, iclass 31, count 0 2006.224.08:07:28.18#ibcon#about to read 3, iclass 31, count 0 2006.224.08:07:28.23#ibcon#read 3, iclass 31, count 0 2006.224.08:07:28.23#ibcon#about to read 4, iclass 31, count 0 2006.224.08:07:28.23#ibcon#read 4, iclass 31, count 0 2006.224.08:07:28.23#ibcon#about to read 5, iclass 31, count 0 2006.224.08:07:28.23#ibcon#read 5, iclass 31, count 0 2006.224.08:07:28.23#ibcon#about to read 6, iclass 31, count 0 2006.224.08:07:28.23#ibcon#read 6, iclass 31, count 0 2006.224.08:07:28.23#ibcon#end of sib2, iclass 31, count 0 2006.224.08:07:28.23#ibcon#*after write, iclass 31, count 0 2006.224.08:07:28.23#ibcon#*before return 0, iclass 31, count 0 2006.224.08:07:28.23#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.224.08:07:28.23#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.224.08:07:28.23#ibcon#about to clear, iclass 31 cls_cnt 0 2006.224.08:07:28.23#ibcon#cleared, iclass 31 cls_cnt 0 2006.224.08:07:28.23$vc4f8/va=2,7 2006.224.08:07:28.23#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.224.08:07:28.23#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.224.08:07:28.23#ibcon#ireg 11 cls_cnt 2 2006.224.08:07:28.23#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.224.08:07:28.28#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.224.08:07:28.28#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.224.08:07:28.28#ibcon#enter wrdev, iclass 33, count 2 2006.224.08:07:28.28#ibcon#first serial, iclass 33, count 2 2006.224.08:07:28.28#ibcon#enter sib2, iclass 33, count 2 2006.224.08:07:28.28#ibcon#flushed, iclass 33, count 2 2006.224.08:07:28.28#ibcon#about to write, iclass 33, count 2 2006.224.08:07:28.28#ibcon#wrote, iclass 33, count 2 2006.224.08:07:28.28#ibcon#about to read 3, iclass 33, count 2 2006.224.08:07:28.30#ibcon#read 3, iclass 33, count 2 2006.224.08:07:28.30#ibcon#about to read 4, iclass 33, count 2 2006.224.08:07:28.30#ibcon#read 4, iclass 33, count 2 2006.224.08:07:28.30#ibcon#about to read 5, iclass 33, count 2 2006.224.08:07:28.30#ibcon#read 5, iclass 33, count 2 2006.224.08:07:28.30#ibcon#about to read 6, iclass 33, count 2 2006.224.08:07:28.30#ibcon#read 6, iclass 33, count 2 2006.224.08:07:28.30#ibcon#end of sib2, iclass 33, count 2 2006.224.08:07:28.30#ibcon#*mode == 0, iclass 33, count 2 2006.224.08:07:28.30#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.224.08:07:28.30#ibcon#[25=AT02-07\r\n] 2006.224.08:07:28.30#ibcon#*before write, iclass 33, count 2 2006.224.08:07:28.30#ibcon#enter sib2, iclass 33, count 2 2006.224.08:07:28.30#ibcon#flushed, iclass 33, count 2 2006.224.08:07:28.30#ibcon#about to write, iclass 33, count 2 2006.224.08:07:28.30#ibcon#wrote, iclass 33, count 2 2006.224.08:07:28.30#ibcon#about to read 3, iclass 33, count 2 2006.224.08:07:28.33#ibcon#read 3, iclass 33, count 2 2006.224.08:07:28.33#ibcon#about to read 4, iclass 33, count 2 2006.224.08:07:28.33#ibcon#read 4, iclass 33, count 2 2006.224.08:07:28.33#ibcon#about to read 5, iclass 33, count 2 2006.224.08:07:28.33#ibcon#read 5, iclass 33, count 2 2006.224.08:07:28.33#ibcon#about to read 6, iclass 33, count 2 2006.224.08:07:28.33#ibcon#read 6, iclass 33, count 2 2006.224.08:07:28.33#ibcon#end of sib2, iclass 33, count 2 2006.224.08:07:28.33#ibcon#*after write, iclass 33, count 2 2006.224.08:07:28.33#ibcon#*before return 0, iclass 33, count 2 2006.224.08:07:28.33#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.224.08:07:28.33#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.224.08:07:28.33#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.224.08:07:28.33#ibcon#ireg 7 cls_cnt 0 2006.224.08:07:28.33#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.224.08:07:28.45#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.224.08:07:28.45#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.224.08:07:28.45#ibcon#enter wrdev, iclass 33, count 0 2006.224.08:07:28.45#ibcon#first serial, iclass 33, count 0 2006.224.08:07:28.45#ibcon#enter sib2, iclass 33, count 0 2006.224.08:07:28.45#ibcon#flushed, iclass 33, count 0 2006.224.08:07:28.45#ibcon#about to write, iclass 33, count 0 2006.224.08:07:28.45#ibcon#wrote, iclass 33, count 0 2006.224.08:07:28.45#ibcon#about to read 3, iclass 33, count 0 2006.224.08:07:28.47#ibcon#read 3, iclass 33, count 0 2006.224.08:07:28.47#ibcon#about to read 4, iclass 33, count 0 2006.224.08:07:28.47#ibcon#read 4, iclass 33, count 0 2006.224.08:07:28.47#ibcon#about to read 5, iclass 33, count 0 2006.224.08:07:28.47#ibcon#read 5, iclass 33, count 0 2006.224.08:07:28.47#ibcon#about to read 6, iclass 33, count 0 2006.224.08:07:28.47#ibcon#read 6, iclass 33, count 0 2006.224.08:07:28.47#ibcon#end of sib2, iclass 33, count 0 2006.224.08:07:28.47#ibcon#*mode == 0, iclass 33, count 0 2006.224.08:07:28.47#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.224.08:07:28.47#ibcon#[25=USB\r\n] 2006.224.08:07:28.47#ibcon#*before write, iclass 33, count 0 2006.224.08:07:28.47#ibcon#enter sib2, iclass 33, count 0 2006.224.08:07:28.47#ibcon#flushed, iclass 33, count 0 2006.224.08:07:28.47#ibcon#about to write, iclass 33, count 0 2006.224.08:07:28.47#ibcon#wrote, iclass 33, count 0 2006.224.08:07:28.47#ibcon#about to read 3, iclass 33, count 0 2006.224.08:07:28.50#ibcon#read 3, iclass 33, count 0 2006.224.08:07:28.50#ibcon#about to read 4, iclass 33, count 0 2006.224.08:07:28.50#ibcon#read 4, iclass 33, count 0 2006.224.08:07:28.50#ibcon#about to read 5, iclass 33, count 0 2006.224.08:07:28.50#ibcon#read 5, iclass 33, count 0 2006.224.08:07:28.50#ibcon#about to read 6, iclass 33, count 0 2006.224.08:07:28.50#ibcon#read 6, iclass 33, count 0 2006.224.08:07:28.50#ibcon#end of sib2, iclass 33, count 0 2006.224.08:07:28.50#ibcon#*after write, iclass 33, count 0 2006.224.08:07:28.50#ibcon#*before return 0, iclass 33, count 0 2006.224.08:07:28.50#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.224.08:07:28.50#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.224.08:07:28.50#ibcon#about to clear, iclass 33 cls_cnt 0 2006.224.08:07:28.50#ibcon#cleared, iclass 33 cls_cnt 0 2006.224.08:07:28.50$vc4f8/valo=3,672.99 2006.224.08:07:28.50#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.224.08:07:28.50#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.224.08:07:28.50#ibcon#ireg 17 cls_cnt 0 2006.224.08:07:28.50#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.224.08:07:28.50#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.224.08:07:28.50#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.224.08:07:28.50#ibcon#enter wrdev, iclass 35, count 0 2006.224.08:07:28.50#ibcon#first serial, iclass 35, count 0 2006.224.08:07:28.50#ibcon#enter sib2, iclass 35, count 0 2006.224.08:07:28.50#ibcon#flushed, iclass 35, count 0 2006.224.08:07:28.50#ibcon#about to write, iclass 35, count 0 2006.224.08:07:28.50#ibcon#wrote, iclass 35, count 0 2006.224.08:07:28.50#ibcon#about to read 3, iclass 35, count 0 2006.224.08:07:28.52#ibcon#read 3, iclass 35, count 0 2006.224.08:07:28.52#ibcon#about to read 4, iclass 35, count 0 2006.224.08:07:28.52#ibcon#read 4, iclass 35, count 0 2006.224.08:07:28.52#ibcon#about to read 5, iclass 35, count 0 2006.224.08:07:28.52#ibcon#read 5, iclass 35, count 0 2006.224.08:07:28.52#ibcon#about to read 6, iclass 35, count 0 2006.224.08:07:28.52#ibcon#read 6, iclass 35, count 0 2006.224.08:07:28.52#ibcon#end of sib2, iclass 35, count 0 2006.224.08:07:28.52#ibcon#*mode == 0, iclass 35, count 0 2006.224.08:07:28.52#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.224.08:07:28.52#ibcon#[26=FRQ=03,672.99\r\n] 2006.224.08:07:28.52#ibcon#*before write, iclass 35, count 0 2006.224.08:07:28.52#ibcon#enter sib2, iclass 35, count 0 2006.224.08:07:28.52#ibcon#flushed, iclass 35, count 0 2006.224.08:07:28.52#ibcon#about to write, iclass 35, count 0 2006.224.08:07:28.52#ibcon#wrote, iclass 35, count 0 2006.224.08:07:28.52#ibcon#about to read 3, iclass 35, count 0 2006.224.08:07:28.57#ibcon#read 3, iclass 35, count 0 2006.224.08:07:28.57#ibcon#about to read 4, iclass 35, count 0 2006.224.08:07:28.57#ibcon#read 4, iclass 35, count 0 2006.224.08:07:28.57#ibcon#about to read 5, iclass 35, count 0 2006.224.08:07:28.57#ibcon#read 5, iclass 35, count 0 2006.224.08:07:28.57#ibcon#about to read 6, iclass 35, count 0 2006.224.08:07:28.57#ibcon#read 6, iclass 35, count 0 2006.224.08:07:28.57#ibcon#end of sib2, iclass 35, count 0 2006.224.08:07:28.57#ibcon#*after write, iclass 35, count 0 2006.224.08:07:28.57#ibcon#*before return 0, iclass 35, count 0 2006.224.08:07:28.57#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.224.08:07:28.57#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.224.08:07:28.57#ibcon#about to clear, iclass 35 cls_cnt 0 2006.224.08:07:28.57#ibcon#cleared, iclass 35 cls_cnt 0 2006.224.08:07:28.57$vc4f8/va=3,6 2006.224.08:07:28.57#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.224.08:07:28.57#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.224.08:07:28.57#ibcon#ireg 11 cls_cnt 2 2006.224.08:07:28.57#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.224.08:07:28.62#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.224.08:07:28.62#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.224.08:07:28.62#ibcon#enter wrdev, iclass 37, count 2 2006.224.08:07:28.62#ibcon#first serial, iclass 37, count 2 2006.224.08:07:28.62#ibcon#enter sib2, iclass 37, count 2 2006.224.08:07:28.62#ibcon#flushed, iclass 37, count 2 2006.224.08:07:28.62#ibcon#about to write, iclass 37, count 2 2006.224.08:07:28.62#ibcon#wrote, iclass 37, count 2 2006.224.08:07:28.62#ibcon#about to read 3, iclass 37, count 2 2006.224.08:07:28.64#ibcon#read 3, iclass 37, count 2 2006.224.08:07:28.64#ibcon#about to read 4, iclass 37, count 2 2006.224.08:07:28.64#ibcon#read 4, iclass 37, count 2 2006.224.08:07:28.64#ibcon#about to read 5, iclass 37, count 2 2006.224.08:07:28.64#ibcon#read 5, iclass 37, count 2 2006.224.08:07:28.64#ibcon#about to read 6, iclass 37, count 2 2006.224.08:07:28.64#ibcon#read 6, iclass 37, count 2 2006.224.08:07:28.64#ibcon#end of sib2, iclass 37, count 2 2006.224.08:07:28.64#ibcon#*mode == 0, iclass 37, count 2 2006.224.08:07:28.64#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.224.08:07:28.64#ibcon#[25=AT03-06\r\n] 2006.224.08:07:28.64#ibcon#*before write, iclass 37, count 2 2006.224.08:07:28.64#ibcon#enter sib2, iclass 37, count 2 2006.224.08:07:28.64#ibcon#flushed, iclass 37, count 2 2006.224.08:07:28.64#ibcon#about to write, iclass 37, count 2 2006.224.08:07:28.64#ibcon#wrote, iclass 37, count 2 2006.224.08:07:28.64#ibcon#about to read 3, iclass 37, count 2 2006.224.08:07:28.67#ibcon#read 3, iclass 37, count 2 2006.224.08:07:28.67#ibcon#about to read 4, iclass 37, count 2 2006.224.08:07:28.67#ibcon#read 4, iclass 37, count 2 2006.224.08:07:28.67#ibcon#about to read 5, iclass 37, count 2 2006.224.08:07:28.67#ibcon#read 5, iclass 37, count 2 2006.224.08:07:28.67#ibcon#about to read 6, iclass 37, count 2 2006.224.08:07:28.67#ibcon#read 6, iclass 37, count 2 2006.224.08:07:28.67#ibcon#end of sib2, iclass 37, count 2 2006.224.08:07:28.67#ibcon#*after write, iclass 37, count 2 2006.224.08:07:28.67#ibcon#*before return 0, iclass 37, count 2 2006.224.08:07:28.67#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.224.08:07:28.67#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.224.08:07:28.67#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.224.08:07:28.67#ibcon#ireg 7 cls_cnt 0 2006.224.08:07:28.67#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.224.08:07:28.79#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.224.08:07:28.79#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.224.08:07:28.79#ibcon#enter wrdev, iclass 37, count 0 2006.224.08:07:28.79#ibcon#first serial, iclass 37, count 0 2006.224.08:07:28.79#ibcon#enter sib2, iclass 37, count 0 2006.224.08:07:28.79#ibcon#flushed, iclass 37, count 0 2006.224.08:07:28.79#ibcon#about to write, iclass 37, count 0 2006.224.08:07:28.79#ibcon#wrote, iclass 37, count 0 2006.224.08:07:28.79#ibcon#about to read 3, iclass 37, count 0 2006.224.08:07:28.81#ibcon#read 3, iclass 37, count 0 2006.224.08:07:28.81#ibcon#about to read 4, iclass 37, count 0 2006.224.08:07:28.81#ibcon#read 4, iclass 37, count 0 2006.224.08:07:28.81#ibcon#about to read 5, iclass 37, count 0 2006.224.08:07:28.81#ibcon#read 5, iclass 37, count 0 2006.224.08:07:28.81#ibcon#about to read 6, iclass 37, count 0 2006.224.08:07:28.81#ibcon#read 6, iclass 37, count 0 2006.224.08:07:28.81#ibcon#end of sib2, iclass 37, count 0 2006.224.08:07:28.81#ibcon#*mode == 0, iclass 37, count 0 2006.224.08:07:28.81#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.224.08:07:28.81#ibcon#[25=USB\r\n] 2006.224.08:07:28.81#ibcon#*before write, iclass 37, count 0 2006.224.08:07:28.81#ibcon#enter sib2, iclass 37, count 0 2006.224.08:07:28.81#ibcon#flushed, iclass 37, count 0 2006.224.08:07:28.81#ibcon#about to write, iclass 37, count 0 2006.224.08:07:28.81#ibcon#wrote, iclass 37, count 0 2006.224.08:07:28.81#ibcon#about to read 3, iclass 37, count 0 2006.224.08:07:28.84#ibcon#read 3, iclass 37, count 0 2006.224.08:07:28.84#ibcon#about to read 4, iclass 37, count 0 2006.224.08:07:28.84#ibcon#read 4, iclass 37, count 0 2006.224.08:07:28.84#ibcon#about to read 5, iclass 37, count 0 2006.224.08:07:28.84#ibcon#read 5, iclass 37, count 0 2006.224.08:07:28.84#ibcon#about to read 6, iclass 37, count 0 2006.224.08:07:28.84#ibcon#read 6, iclass 37, count 0 2006.224.08:07:28.84#ibcon#end of sib2, iclass 37, count 0 2006.224.08:07:28.84#ibcon#*after write, iclass 37, count 0 2006.224.08:07:28.84#ibcon#*before return 0, iclass 37, count 0 2006.224.08:07:28.84#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.224.08:07:28.84#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.224.08:07:28.84#ibcon#about to clear, iclass 37 cls_cnt 0 2006.224.08:07:28.84#ibcon#cleared, iclass 37 cls_cnt 0 2006.224.08:07:28.84$vc4f8/valo=4,832.99 2006.224.08:07:28.84#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.224.08:07:28.84#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.224.08:07:28.84#ibcon#ireg 17 cls_cnt 0 2006.224.08:07:28.84#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.224.08:07:28.84#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.224.08:07:28.84#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.224.08:07:28.84#ibcon#enter wrdev, iclass 39, count 0 2006.224.08:07:28.84#ibcon#first serial, iclass 39, count 0 2006.224.08:07:28.84#ibcon#enter sib2, iclass 39, count 0 2006.224.08:07:28.84#ibcon#flushed, iclass 39, count 0 2006.224.08:07:28.84#ibcon#about to write, iclass 39, count 0 2006.224.08:07:28.84#ibcon#wrote, iclass 39, count 0 2006.224.08:07:28.84#ibcon#about to read 3, iclass 39, count 0 2006.224.08:07:28.86#ibcon#read 3, iclass 39, count 0 2006.224.08:07:28.86#ibcon#about to read 4, iclass 39, count 0 2006.224.08:07:28.86#ibcon#read 4, iclass 39, count 0 2006.224.08:07:28.86#ibcon#about to read 5, iclass 39, count 0 2006.224.08:07:28.86#ibcon#read 5, iclass 39, count 0 2006.224.08:07:28.86#ibcon#about to read 6, iclass 39, count 0 2006.224.08:07:28.86#ibcon#read 6, iclass 39, count 0 2006.224.08:07:28.86#ibcon#end of sib2, iclass 39, count 0 2006.224.08:07:28.86#ibcon#*mode == 0, iclass 39, count 0 2006.224.08:07:28.86#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.224.08:07:28.86#ibcon#[26=FRQ=04,832.99\r\n] 2006.224.08:07:28.86#ibcon#*before write, iclass 39, count 0 2006.224.08:07:28.86#ibcon#enter sib2, iclass 39, count 0 2006.224.08:07:28.86#ibcon#flushed, iclass 39, count 0 2006.224.08:07:28.86#ibcon#about to write, iclass 39, count 0 2006.224.08:07:28.86#ibcon#wrote, iclass 39, count 0 2006.224.08:07:28.86#ibcon#about to read 3, iclass 39, count 0 2006.224.08:07:28.90#ibcon#read 3, iclass 39, count 0 2006.224.08:07:28.90#ibcon#about to read 4, iclass 39, count 0 2006.224.08:07:28.90#ibcon#read 4, iclass 39, count 0 2006.224.08:07:28.90#ibcon#about to read 5, iclass 39, count 0 2006.224.08:07:28.90#ibcon#read 5, iclass 39, count 0 2006.224.08:07:28.90#ibcon#about to read 6, iclass 39, count 0 2006.224.08:07:28.90#ibcon#read 6, iclass 39, count 0 2006.224.08:07:28.90#ibcon#end of sib2, iclass 39, count 0 2006.224.08:07:28.90#ibcon#*after write, iclass 39, count 0 2006.224.08:07:28.90#ibcon#*before return 0, iclass 39, count 0 2006.224.08:07:28.90#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.224.08:07:28.90#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.224.08:07:28.90#ibcon#about to clear, iclass 39 cls_cnt 0 2006.224.08:07:28.90#ibcon#cleared, iclass 39 cls_cnt 0 2006.224.08:07:28.90$vc4f8/va=4,7 2006.224.08:07:28.90#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.224.08:07:28.90#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.224.08:07:28.90#ibcon#ireg 11 cls_cnt 2 2006.224.08:07:28.90#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.224.08:07:28.96#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.224.08:07:28.96#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.224.08:07:28.96#ibcon#enter wrdev, iclass 3, count 2 2006.224.08:07:28.96#ibcon#first serial, iclass 3, count 2 2006.224.08:07:28.96#ibcon#enter sib2, iclass 3, count 2 2006.224.08:07:28.96#ibcon#flushed, iclass 3, count 2 2006.224.08:07:28.96#ibcon#about to write, iclass 3, count 2 2006.224.08:07:28.96#ibcon#wrote, iclass 3, count 2 2006.224.08:07:28.96#ibcon#about to read 3, iclass 3, count 2 2006.224.08:07:28.98#ibcon#read 3, iclass 3, count 2 2006.224.08:07:28.98#ibcon#about to read 4, iclass 3, count 2 2006.224.08:07:28.98#ibcon#read 4, iclass 3, count 2 2006.224.08:07:28.98#ibcon#about to read 5, iclass 3, count 2 2006.224.08:07:28.98#ibcon#read 5, iclass 3, count 2 2006.224.08:07:28.98#ibcon#about to read 6, iclass 3, count 2 2006.224.08:07:28.98#ibcon#read 6, iclass 3, count 2 2006.224.08:07:28.98#ibcon#end of sib2, iclass 3, count 2 2006.224.08:07:28.98#ibcon#*mode == 0, iclass 3, count 2 2006.224.08:07:28.98#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.224.08:07:28.98#ibcon#[25=AT04-07\r\n] 2006.224.08:07:28.98#ibcon#*before write, iclass 3, count 2 2006.224.08:07:28.98#ibcon#enter sib2, iclass 3, count 2 2006.224.08:07:28.98#ibcon#flushed, iclass 3, count 2 2006.224.08:07:28.98#ibcon#about to write, iclass 3, count 2 2006.224.08:07:28.98#ibcon#wrote, iclass 3, count 2 2006.224.08:07:28.98#ibcon#about to read 3, iclass 3, count 2 2006.224.08:07:29.01#ibcon#read 3, iclass 3, count 2 2006.224.08:07:29.01#ibcon#about to read 4, iclass 3, count 2 2006.224.08:07:29.01#ibcon#read 4, iclass 3, count 2 2006.224.08:07:29.01#ibcon#about to read 5, iclass 3, count 2 2006.224.08:07:29.01#ibcon#read 5, iclass 3, count 2 2006.224.08:07:29.01#ibcon#about to read 6, iclass 3, count 2 2006.224.08:07:29.01#ibcon#read 6, iclass 3, count 2 2006.224.08:07:29.01#ibcon#end of sib2, iclass 3, count 2 2006.224.08:07:29.01#ibcon#*after write, iclass 3, count 2 2006.224.08:07:29.01#ibcon#*before return 0, iclass 3, count 2 2006.224.08:07:29.01#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.224.08:07:29.01#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.224.08:07:29.01#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.224.08:07:29.01#ibcon#ireg 7 cls_cnt 0 2006.224.08:07:29.01#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.224.08:07:29.13#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.224.08:07:29.13#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.224.08:07:29.13#ibcon#enter wrdev, iclass 3, count 0 2006.224.08:07:29.13#ibcon#first serial, iclass 3, count 0 2006.224.08:07:29.13#ibcon#enter sib2, iclass 3, count 0 2006.224.08:07:29.13#ibcon#flushed, iclass 3, count 0 2006.224.08:07:29.13#ibcon#about to write, iclass 3, count 0 2006.224.08:07:29.13#ibcon#wrote, iclass 3, count 0 2006.224.08:07:29.13#ibcon#about to read 3, iclass 3, count 0 2006.224.08:07:29.15#ibcon#read 3, iclass 3, count 0 2006.224.08:07:29.15#ibcon#about to read 4, iclass 3, count 0 2006.224.08:07:29.15#ibcon#read 4, iclass 3, count 0 2006.224.08:07:29.15#ibcon#about to read 5, iclass 3, count 0 2006.224.08:07:29.15#ibcon#read 5, iclass 3, count 0 2006.224.08:07:29.15#ibcon#about to read 6, iclass 3, count 0 2006.224.08:07:29.15#ibcon#read 6, iclass 3, count 0 2006.224.08:07:29.15#ibcon#end of sib2, iclass 3, count 0 2006.224.08:07:29.15#ibcon#*mode == 0, iclass 3, count 0 2006.224.08:07:29.15#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.224.08:07:29.15#ibcon#[25=USB\r\n] 2006.224.08:07:29.15#ibcon#*before write, iclass 3, count 0 2006.224.08:07:29.15#ibcon#enter sib2, iclass 3, count 0 2006.224.08:07:29.15#ibcon#flushed, iclass 3, count 0 2006.224.08:07:29.15#ibcon#about to write, iclass 3, count 0 2006.224.08:07:29.15#ibcon#wrote, iclass 3, count 0 2006.224.08:07:29.15#ibcon#about to read 3, iclass 3, count 0 2006.224.08:07:29.18#ibcon#read 3, iclass 3, count 0 2006.224.08:07:29.18#ibcon#about to read 4, iclass 3, count 0 2006.224.08:07:29.18#ibcon#read 4, iclass 3, count 0 2006.224.08:07:29.18#ibcon#about to read 5, iclass 3, count 0 2006.224.08:07:29.18#ibcon#read 5, iclass 3, count 0 2006.224.08:07:29.18#ibcon#about to read 6, iclass 3, count 0 2006.224.08:07:29.18#ibcon#read 6, iclass 3, count 0 2006.224.08:07:29.18#ibcon#end of sib2, iclass 3, count 0 2006.224.08:07:29.18#ibcon#*after write, iclass 3, count 0 2006.224.08:07:29.18#ibcon#*before return 0, iclass 3, count 0 2006.224.08:07:29.18#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.224.08:07:29.18#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.224.08:07:29.18#ibcon#about to clear, iclass 3 cls_cnt 0 2006.224.08:07:29.18#ibcon#cleared, iclass 3 cls_cnt 0 2006.224.08:07:29.18$vc4f8/valo=5,652.99 2006.224.08:07:29.18#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.224.08:07:29.18#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.224.08:07:29.18#ibcon#ireg 17 cls_cnt 0 2006.224.08:07:29.18#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.224.08:07:29.18#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.224.08:07:29.18#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.224.08:07:29.18#ibcon#enter wrdev, iclass 5, count 0 2006.224.08:07:29.18#ibcon#first serial, iclass 5, count 0 2006.224.08:07:29.18#ibcon#enter sib2, iclass 5, count 0 2006.224.08:07:29.18#ibcon#flushed, iclass 5, count 0 2006.224.08:07:29.18#ibcon#about to write, iclass 5, count 0 2006.224.08:07:29.18#ibcon#wrote, iclass 5, count 0 2006.224.08:07:29.18#ibcon#about to read 3, iclass 5, count 0 2006.224.08:07:29.20#ibcon#read 3, iclass 5, count 0 2006.224.08:07:29.20#ibcon#about to read 4, iclass 5, count 0 2006.224.08:07:29.20#ibcon#read 4, iclass 5, count 0 2006.224.08:07:29.20#ibcon#about to read 5, iclass 5, count 0 2006.224.08:07:29.20#ibcon#read 5, iclass 5, count 0 2006.224.08:07:29.20#ibcon#about to read 6, iclass 5, count 0 2006.224.08:07:29.20#ibcon#read 6, iclass 5, count 0 2006.224.08:07:29.20#ibcon#end of sib2, iclass 5, count 0 2006.224.08:07:29.20#ibcon#*mode == 0, iclass 5, count 0 2006.224.08:07:29.20#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.224.08:07:29.20#ibcon#[26=FRQ=05,652.99\r\n] 2006.224.08:07:29.20#ibcon#*before write, iclass 5, count 0 2006.224.08:07:29.20#ibcon#enter sib2, iclass 5, count 0 2006.224.08:07:29.20#ibcon#flushed, iclass 5, count 0 2006.224.08:07:29.20#ibcon#about to write, iclass 5, count 0 2006.224.08:07:29.20#ibcon#wrote, iclass 5, count 0 2006.224.08:07:29.20#ibcon#about to read 3, iclass 5, count 0 2006.224.08:07:29.24#ibcon#read 3, iclass 5, count 0 2006.224.08:07:29.24#ibcon#about to read 4, iclass 5, count 0 2006.224.08:07:29.24#ibcon#read 4, iclass 5, count 0 2006.224.08:07:29.24#ibcon#about to read 5, iclass 5, count 0 2006.224.08:07:29.24#ibcon#read 5, iclass 5, count 0 2006.224.08:07:29.24#ibcon#about to read 6, iclass 5, count 0 2006.224.08:07:29.24#ibcon#read 6, iclass 5, count 0 2006.224.08:07:29.24#ibcon#end of sib2, iclass 5, count 0 2006.224.08:07:29.24#ibcon#*after write, iclass 5, count 0 2006.224.08:07:29.24#ibcon#*before return 0, iclass 5, count 0 2006.224.08:07:29.24#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.224.08:07:29.24#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.224.08:07:29.24#ibcon#about to clear, iclass 5 cls_cnt 0 2006.224.08:07:29.24#ibcon#cleared, iclass 5 cls_cnt 0 2006.224.08:07:29.24$vc4f8/va=5,7 2006.224.08:07:29.24#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.224.08:07:29.24#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.224.08:07:29.24#ibcon#ireg 11 cls_cnt 2 2006.224.08:07:29.24#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.224.08:07:29.30#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.224.08:07:29.30#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.224.08:07:29.30#ibcon#enter wrdev, iclass 7, count 2 2006.224.08:07:29.30#ibcon#first serial, iclass 7, count 2 2006.224.08:07:29.30#ibcon#enter sib2, iclass 7, count 2 2006.224.08:07:29.30#ibcon#flushed, iclass 7, count 2 2006.224.08:07:29.30#ibcon#about to write, iclass 7, count 2 2006.224.08:07:29.30#ibcon#wrote, iclass 7, count 2 2006.224.08:07:29.30#ibcon#about to read 3, iclass 7, count 2 2006.224.08:07:29.32#ibcon#read 3, iclass 7, count 2 2006.224.08:07:29.32#ibcon#about to read 4, iclass 7, count 2 2006.224.08:07:29.32#ibcon#read 4, iclass 7, count 2 2006.224.08:07:29.32#ibcon#about to read 5, iclass 7, count 2 2006.224.08:07:29.32#ibcon#read 5, iclass 7, count 2 2006.224.08:07:29.32#ibcon#about to read 6, iclass 7, count 2 2006.224.08:07:29.32#ibcon#read 6, iclass 7, count 2 2006.224.08:07:29.32#ibcon#end of sib2, iclass 7, count 2 2006.224.08:07:29.32#ibcon#*mode == 0, iclass 7, count 2 2006.224.08:07:29.32#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.224.08:07:29.32#ibcon#[25=AT05-07\r\n] 2006.224.08:07:29.32#ibcon#*before write, iclass 7, count 2 2006.224.08:07:29.32#ibcon#enter sib2, iclass 7, count 2 2006.224.08:07:29.32#ibcon#flushed, iclass 7, count 2 2006.224.08:07:29.32#ibcon#about to write, iclass 7, count 2 2006.224.08:07:29.32#ibcon#wrote, iclass 7, count 2 2006.224.08:07:29.32#ibcon#about to read 3, iclass 7, count 2 2006.224.08:07:29.35#ibcon#read 3, iclass 7, count 2 2006.224.08:07:29.35#ibcon#about to read 4, iclass 7, count 2 2006.224.08:07:29.35#ibcon#read 4, iclass 7, count 2 2006.224.08:07:29.35#ibcon#about to read 5, iclass 7, count 2 2006.224.08:07:29.35#ibcon#read 5, iclass 7, count 2 2006.224.08:07:29.35#ibcon#about to read 6, iclass 7, count 2 2006.224.08:07:29.35#ibcon#read 6, iclass 7, count 2 2006.224.08:07:29.35#ibcon#end of sib2, iclass 7, count 2 2006.224.08:07:29.35#ibcon#*after write, iclass 7, count 2 2006.224.08:07:29.35#ibcon#*before return 0, iclass 7, count 2 2006.224.08:07:29.35#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.224.08:07:29.35#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.224.08:07:29.35#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.224.08:07:29.35#ibcon#ireg 7 cls_cnt 0 2006.224.08:07:29.35#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.224.08:07:29.47#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.224.08:07:29.47#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.224.08:07:29.47#ibcon#enter wrdev, iclass 7, count 0 2006.224.08:07:29.47#ibcon#first serial, iclass 7, count 0 2006.224.08:07:29.47#ibcon#enter sib2, iclass 7, count 0 2006.224.08:07:29.47#ibcon#flushed, iclass 7, count 0 2006.224.08:07:29.47#ibcon#about to write, iclass 7, count 0 2006.224.08:07:29.47#ibcon#wrote, iclass 7, count 0 2006.224.08:07:29.47#ibcon#about to read 3, iclass 7, count 0 2006.224.08:07:29.49#ibcon#read 3, iclass 7, count 0 2006.224.08:07:29.49#ibcon#about to read 4, iclass 7, count 0 2006.224.08:07:29.49#ibcon#read 4, iclass 7, count 0 2006.224.08:07:29.49#ibcon#about to read 5, iclass 7, count 0 2006.224.08:07:29.49#ibcon#read 5, iclass 7, count 0 2006.224.08:07:29.49#ibcon#about to read 6, iclass 7, count 0 2006.224.08:07:29.49#ibcon#read 6, iclass 7, count 0 2006.224.08:07:29.49#ibcon#end of sib2, iclass 7, count 0 2006.224.08:07:29.49#ibcon#*mode == 0, iclass 7, count 0 2006.224.08:07:29.49#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.224.08:07:29.49#ibcon#[25=USB\r\n] 2006.224.08:07:29.49#ibcon#*before write, iclass 7, count 0 2006.224.08:07:29.49#ibcon#enter sib2, iclass 7, count 0 2006.224.08:07:29.49#ibcon#flushed, iclass 7, count 0 2006.224.08:07:29.49#ibcon#about to write, iclass 7, count 0 2006.224.08:07:29.49#ibcon#wrote, iclass 7, count 0 2006.224.08:07:29.49#ibcon#about to read 3, iclass 7, count 0 2006.224.08:07:29.52#ibcon#read 3, iclass 7, count 0 2006.224.08:07:29.52#ibcon#about to read 4, iclass 7, count 0 2006.224.08:07:29.52#ibcon#read 4, iclass 7, count 0 2006.224.08:07:29.52#ibcon#about to read 5, iclass 7, count 0 2006.224.08:07:29.52#ibcon#read 5, iclass 7, count 0 2006.224.08:07:29.52#ibcon#about to read 6, iclass 7, count 0 2006.224.08:07:29.52#ibcon#read 6, iclass 7, count 0 2006.224.08:07:29.52#ibcon#end of sib2, iclass 7, count 0 2006.224.08:07:29.52#ibcon#*after write, iclass 7, count 0 2006.224.08:07:29.52#ibcon#*before return 0, iclass 7, count 0 2006.224.08:07:29.52#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.224.08:07:29.52#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.224.08:07:29.52#ibcon#about to clear, iclass 7 cls_cnt 0 2006.224.08:07:29.52#ibcon#cleared, iclass 7 cls_cnt 0 2006.224.08:07:29.52$vc4f8/valo=6,772.99 2006.224.08:07:29.52#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.224.08:07:29.52#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.224.08:07:29.52#ibcon#ireg 17 cls_cnt 0 2006.224.08:07:29.52#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.224.08:07:29.52#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.224.08:07:29.52#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.224.08:07:29.52#ibcon#enter wrdev, iclass 11, count 0 2006.224.08:07:29.52#ibcon#first serial, iclass 11, count 0 2006.224.08:07:29.52#ibcon#enter sib2, iclass 11, count 0 2006.224.08:07:29.52#ibcon#flushed, iclass 11, count 0 2006.224.08:07:29.52#ibcon#about to write, iclass 11, count 0 2006.224.08:07:29.52#ibcon#wrote, iclass 11, count 0 2006.224.08:07:29.52#ibcon#about to read 3, iclass 11, count 0 2006.224.08:07:29.54#ibcon#read 3, iclass 11, count 0 2006.224.08:07:29.54#ibcon#about to read 4, iclass 11, count 0 2006.224.08:07:29.54#ibcon#read 4, iclass 11, count 0 2006.224.08:07:29.54#ibcon#about to read 5, iclass 11, count 0 2006.224.08:07:29.54#ibcon#read 5, iclass 11, count 0 2006.224.08:07:29.54#ibcon#about to read 6, iclass 11, count 0 2006.224.08:07:29.54#ibcon#read 6, iclass 11, count 0 2006.224.08:07:29.54#ibcon#end of sib2, iclass 11, count 0 2006.224.08:07:29.54#ibcon#*mode == 0, iclass 11, count 0 2006.224.08:07:29.54#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.224.08:07:29.54#ibcon#[26=FRQ=06,772.99\r\n] 2006.224.08:07:29.54#ibcon#*before write, iclass 11, count 0 2006.224.08:07:29.54#ibcon#enter sib2, iclass 11, count 0 2006.224.08:07:29.54#ibcon#flushed, iclass 11, count 0 2006.224.08:07:29.54#ibcon#about to write, iclass 11, count 0 2006.224.08:07:29.54#ibcon#wrote, iclass 11, count 0 2006.224.08:07:29.54#ibcon#about to read 3, iclass 11, count 0 2006.224.08:07:29.58#ibcon#read 3, iclass 11, count 0 2006.224.08:07:29.58#ibcon#about to read 4, iclass 11, count 0 2006.224.08:07:29.58#ibcon#read 4, iclass 11, count 0 2006.224.08:07:29.58#ibcon#about to read 5, iclass 11, count 0 2006.224.08:07:29.58#ibcon#read 5, iclass 11, count 0 2006.224.08:07:29.58#ibcon#about to read 6, iclass 11, count 0 2006.224.08:07:29.58#ibcon#read 6, iclass 11, count 0 2006.224.08:07:29.58#ibcon#end of sib2, iclass 11, count 0 2006.224.08:07:29.58#ibcon#*after write, iclass 11, count 0 2006.224.08:07:29.58#ibcon#*before return 0, iclass 11, count 0 2006.224.08:07:29.58#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.224.08:07:29.58#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.224.08:07:29.58#ibcon#about to clear, iclass 11 cls_cnt 0 2006.224.08:07:29.58#ibcon#cleared, iclass 11 cls_cnt 0 2006.224.08:07:29.58$vc4f8/va=6,6 2006.224.08:07:29.58#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.224.08:07:29.58#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.224.08:07:29.58#ibcon#ireg 11 cls_cnt 2 2006.224.08:07:29.58#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.224.08:07:29.64#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.224.08:07:29.64#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.224.08:07:29.64#ibcon#enter wrdev, iclass 13, count 2 2006.224.08:07:29.64#ibcon#first serial, iclass 13, count 2 2006.224.08:07:29.64#ibcon#enter sib2, iclass 13, count 2 2006.224.08:07:29.64#ibcon#flushed, iclass 13, count 2 2006.224.08:07:29.64#ibcon#about to write, iclass 13, count 2 2006.224.08:07:29.64#ibcon#wrote, iclass 13, count 2 2006.224.08:07:29.64#ibcon#about to read 3, iclass 13, count 2 2006.224.08:07:29.66#ibcon#read 3, iclass 13, count 2 2006.224.08:07:29.66#ibcon#about to read 4, iclass 13, count 2 2006.224.08:07:29.66#ibcon#read 4, iclass 13, count 2 2006.224.08:07:29.66#ibcon#about to read 5, iclass 13, count 2 2006.224.08:07:29.66#ibcon#read 5, iclass 13, count 2 2006.224.08:07:29.66#ibcon#about to read 6, iclass 13, count 2 2006.224.08:07:29.66#ibcon#read 6, iclass 13, count 2 2006.224.08:07:29.66#ibcon#end of sib2, iclass 13, count 2 2006.224.08:07:29.66#ibcon#*mode == 0, iclass 13, count 2 2006.224.08:07:29.66#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.224.08:07:29.66#ibcon#[25=AT06-06\r\n] 2006.224.08:07:29.66#ibcon#*before write, iclass 13, count 2 2006.224.08:07:29.66#ibcon#enter sib2, iclass 13, count 2 2006.224.08:07:29.66#ibcon#flushed, iclass 13, count 2 2006.224.08:07:29.66#ibcon#about to write, iclass 13, count 2 2006.224.08:07:29.66#ibcon#wrote, iclass 13, count 2 2006.224.08:07:29.66#ibcon#about to read 3, iclass 13, count 2 2006.224.08:07:29.69#ibcon#read 3, iclass 13, count 2 2006.224.08:07:29.69#ibcon#about to read 4, iclass 13, count 2 2006.224.08:07:29.69#ibcon#read 4, iclass 13, count 2 2006.224.08:07:29.69#ibcon#about to read 5, iclass 13, count 2 2006.224.08:07:29.69#ibcon#read 5, iclass 13, count 2 2006.224.08:07:29.69#ibcon#about to read 6, iclass 13, count 2 2006.224.08:07:29.69#ibcon#read 6, iclass 13, count 2 2006.224.08:07:29.69#ibcon#end of sib2, iclass 13, count 2 2006.224.08:07:29.69#ibcon#*after write, iclass 13, count 2 2006.224.08:07:29.69#ibcon#*before return 0, iclass 13, count 2 2006.224.08:07:29.69#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.224.08:07:29.69#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.224.08:07:29.69#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.224.08:07:29.69#ibcon#ireg 7 cls_cnt 0 2006.224.08:07:29.69#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.224.08:07:29.81#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.224.08:07:29.81#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.224.08:07:29.81#ibcon#enter wrdev, iclass 13, count 0 2006.224.08:07:29.81#ibcon#first serial, iclass 13, count 0 2006.224.08:07:29.81#ibcon#enter sib2, iclass 13, count 0 2006.224.08:07:29.81#ibcon#flushed, iclass 13, count 0 2006.224.08:07:29.81#ibcon#about to write, iclass 13, count 0 2006.224.08:07:29.81#ibcon#wrote, iclass 13, count 0 2006.224.08:07:29.81#ibcon#about to read 3, iclass 13, count 0 2006.224.08:07:29.83#ibcon#read 3, iclass 13, count 0 2006.224.08:07:29.83#ibcon#about to read 4, iclass 13, count 0 2006.224.08:07:29.83#ibcon#read 4, iclass 13, count 0 2006.224.08:07:29.83#ibcon#about to read 5, iclass 13, count 0 2006.224.08:07:29.83#ibcon#read 5, iclass 13, count 0 2006.224.08:07:29.83#ibcon#about to read 6, iclass 13, count 0 2006.224.08:07:29.83#ibcon#read 6, iclass 13, count 0 2006.224.08:07:29.83#ibcon#end of sib2, iclass 13, count 0 2006.224.08:07:29.83#ibcon#*mode == 0, iclass 13, count 0 2006.224.08:07:29.83#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.224.08:07:29.83#ibcon#[25=USB\r\n] 2006.224.08:07:29.83#ibcon#*before write, iclass 13, count 0 2006.224.08:07:29.83#ibcon#enter sib2, iclass 13, count 0 2006.224.08:07:29.83#ibcon#flushed, iclass 13, count 0 2006.224.08:07:29.83#ibcon#about to write, iclass 13, count 0 2006.224.08:07:29.83#ibcon#wrote, iclass 13, count 0 2006.224.08:07:29.83#ibcon#about to read 3, iclass 13, count 0 2006.224.08:07:29.86#ibcon#read 3, iclass 13, count 0 2006.224.08:07:29.86#ibcon#about to read 4, iclass 13, count 0 2006.224.08:07:29.86#ibcon#read 4, iclass 13, count 0 2006.224.08:07:29.86#ibcon#about to read 5, iclass 13, count 0 2006.224.08:07:29.86#ibcon#read 5, iclass 13, count 0 2006.224.08:07:29.86#ibcon#about to read 6, iclass 13, count 0 2006.224.08:07:29.86#ibcon#read 6, iclass 13, count 0 2006.224.08:07:29.86#ibcon#end of sib2, iclass 13, count 0 2006.224.08:07:29.86#ibcon#*after write, iclass 13, count 0 2006.224.08:07:29.86#ibcon#*before return 0, iclass 13, count 0 2006.224.08:07:29.86#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.224.08:07:29.86#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.224.08:07:29.86#ibcon#about to clear, iclass 13 cls_cnt 0 2006.224.08:07:29.86#ibcon#cleared, iclass 13 cls_cnt 0 2006.224.08:07:29.86$vc4f8/valo=7,832.99 2006.224.08:07:29.86#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.224.08:07:29.86#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.224.08:07:29.86#ibcon#ireg 17 cls_cnt 0 2006.224.08:07:29.86#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.224.08:07:29.86#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.224.08:07:29.86#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.224.08:07:29.86#ibcon#enter wrdev, iclass 15, count 0 2006.224.08:07:29.86#ibcon#first serial, iclass 15, count 0 2006.224.08:07:29.86#ibcon#enter sib2, iclass 15, count 0 2006.224.08:07:29.86#ibcon#flushed, iclass 15, count 0 2006.224.08:07:29.86#ibcon#about to write, iclass 15, count 0 2006.224.08:07:29.86#ibcon#wrote, iclass 15, count 0 2006.224.08:07:29.86#ibcon#about to read 3, iclass 15, count 0 2006.224.08:07:29.88#ibcon#read 3, iclass 15, count 0 2006.224.08:07:29.88#ibcon#about to read 4, iclass 15, count 0 2006.224.08:07:29.88#ibcon#read 4, iclass 15, count 0 2006.224.08:07:29.88#ibcon#about to read 5, iclass 15, count 0 2006.224.08:07:29.88#ibcon#read 5, iclass 15, count 0 2006.224.08:07:29.88#ibcon#about to read 6, iclass 15, count 0 2006.224.08:07:29.88#ibcon#read 6, iclass 15, count 0 2006.224.08:07:29.88#ibcon#end of sib2, iclass 15, count 0 2006.224.08:07:29.88#ibcon#*mode == 0, iclass 15, count 0 2006.224.08:07:29.88#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.224.08:07:29.88#ibcon#[26=FRQ=07,832.99\r\n] 2006.224.08:07:29.88#ibcon#*before write, iclass 15, count 0 2006.224.08:07:29.88#ibcon#enter sib2, iclass 15, count 0 2006.224.08:07:29.88#ibcon#flushed, iclass 15, count 0 2006.224.08:07:29.88#ibcon#about to write, iclass 15, count 0 2006.224.08:07:29.88#ibcon#wrote, iclass 15, count 0 2006.224.08:07:29.88#ibcon#about to read 3, iclass 15, count 0 2006.224.08:07:29.92#ibcon#read 3, iclass 15, count 0 2006.224.08:07:29.92#ibcon#about to read 4, iclass 15, count 0 2006.224.08:07:29.92#ibcon#read 4, iclass 15, count 0 2006.224.08:07:29.92#ibcon#about to read 5, iclass 15, count 0 2006.224.08:07:29.92#ibcon#read 5, iclass 15, count 0 2006.224.08:07:29.92#ibcon#about to read 6, iclass 15, count 0 2006.224.08:07:29.92#ibcon#read 6, iclass 15, count 0 2006.224.08:07:29.92#ibcon#end of sib2, iclass 15, count 0 2006.224.08:07:29.92#ibcon#*after write, iclass 15, count 0 2006.224.08:07:29.92#ibcon#*before return 0, iclass 15, count 0 2006.224.08:07:29.92#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.224.08:07:29.92#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.224.08:07:29.92#ibcon#about to clear, iclass 15 cls_cnt 0 2006.224.08:07:29.92#ibcon#cleared, iclass 15 cls_cnt 0 2006.224.08:07:29.92$vc4f8/va=7,6 2006.224.08:07:29.92#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.224.08:07:29.92#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.224.08:07:29.92#ibcon#ireg 11 cls_cnt 2 2006.224.08:07:29.92#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.224.08:07:29.98#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.224.08:07:29.98#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.224.08:07:29.98#ibcon#enter wrdev, iclass 17, count 2 2006.224.08:07:29.98#ibcon#first serial, iclass 17, count 2 2006.224.08:07:29.98#ibcon#enter sib2, iclass 17, count 2 2006.224.08:07:29.98#ibcon#flushed, iclass 17, count 2 2006.224.08:07:29.98#ibcon#about to write, iclass 17, count 2 2006.224.08:07:29.98#ibcon#wrote, iclass 17, count 2 2006.224.08:07:29.98#ibcon#about to read 3, iclass 17, count 2 2006.224.08:07:30.00#ibcon#read 3, iclass 17, count 2 2006.224.08:07:30.00#ibcon#about to read 4, iclass 17, count 2 2006.224.08:07:30.00#ibcon#read 4, iclass 17, count 2 2006.224.08:07:30.00#ibcon#about to read 5, iclass 17, count 2 2006.224.08:07:30.00#ibcon#read 5, iclass 17, count 2 2006.224.08:07:30.00#ibcon#about to read 6, iclass 17, count 2 2006.224.08:07:30.00#ibcon#read 6, iclass 17, count 2 2006.224.08:07:30.00#ibcon#end of sib2, iclass 17, count 2 2006.224.08:07:30.00#ibcon#*mode == 0, iclass 17, count 2 2006.224.08:07:30.00#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.224.08:07:30.00#ibcon#[25=AT07-06\r\n] 2006.224.08:07:30.00#ibcon#*before write, iclass 17, count 2 2006.224.08:07:30.00#ibcon#enter sib2, iclass 17, count 2 2006.224.08:07:30.00#ibcon#flushed, iclass 17, count 2 2006.224.08:07:30.00#ibcon#about to write, iclass 17, count 2 2006.224.08:07:30.00#ibcon#wrote, iclass 17, count 2 2006.224.08:07:30.00#ibcon#about to read 3, iclass 17, count 2 2006.224.08:07:30.03#ibcon#read 3, iclass 17, count 2 2006.224.08:07:30.03#ibcon#about to read 4, iclass 17, count 2 2006.224.08:07:30.03#ibcon#read 4, iclass 17, count 2 2006.224.08:07:30.03#ibcon#about to read 5, iclass 17, count 2 2006.224.08:07:30.03#ibcon#read 5, iclass 17, count 2 2006.224.08:07:30.03#ibcon#about to read 6, iclass 17, count 2 2006.224.08:07:30.03#ibcon#read 6, iclass 17, count 2 2006.224.08:07:30.03#ibcon#end of sib2, iclass 17, count 2 2006.224.08:07:30.03#ibcon#*after write, iclass 17, count 2 2006.224.08:07:30.03#ibcon#*before return 0, iclass 17, count 2 2006.224.08:07:30.03#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.224.08:07:30.03#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.224.08:07:30.03#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.224.08:07:30.03#ibcon#ireg 7 cls_cnt 0 2006.224.08:07:30.03#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.224.08:07:30.15#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.224.08:07:30.15#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.224.08:07:30.15#ibcon#enter wrdev, iclass 17, count 0 2006.224.08:07:30.15#ibcon#first serial, iclass 17, count 0 2006.224.08:07:30.15#ibcon#enter sib2, iclass 17, count 0 2006.224.08:07:30.15#ibcon#flushed, iclass 17, count 0 2006.224.08:07:30.15#ibcon#about to write, iclass 17, count 0 2006.224.08:07:30.15#ibcon#wrote, iclass 17, count 0 2006.224.08:07:30.15#ibcon#about to read 3, iclass 17, count 0 2006.224.08:07:30.17#ibcon#read 3, iclass 17, count 0 2006.224.08:07:30.17#ibcon#about to read 4, iclass 17, count 0 2006.224.08:07:30.17#ibcon#read 4, iclass 17, count 0 2006.224.08:07:30.17#ibcon#about to read 5, iclass 17, count 0 2006.224.08:07:30.17#ibcon#read 5, iclass 17, count 0 2006.224.08:07:30.17#ibcon#about to read 6, iclass 17, count 0 2006.224.08:07:30.17#ibcon#read 6, iclass 17, count 0 2006.224.08:07:30.17#ibcon#end of sib2, iclass 17, count 0 2006.224.08:07:30.17#ibcon#*mode == 0, iclass 17, count 0 2006.224.08:07:30.17#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.224.08:07:30.17#ibcon#[25=USB\r\n] 2006.224.08:07:30.17#ibcon#*before write, iclass 17, count 0 2006.224.08:07:30.17#ibcon#enter sib2, iclass 17, count 0 2006.224.08:07:30.17#ibcon#flushed, iclass 17, count 0 2006.224.08:07:30.17#ibcon#about to write, iclass 17, count 0 2006.224.08:07:30.17#ibcon#wrote, iclass 17, count 0 2006.224.08:07:30.17#ibcon#about to read 3, iclass 17, count 0 2006.224.08:07:30.20#ibcon#read 3, iclass 17, count 0 2006.224.08:07:30.20#ibcon#about to read 4, iclass 17, count 0 2006.224.08:07:30.20#ibcon#read 4, iclass 17, count 0 2006.224.08:07:30.20#ibcon#about to read 5, iclass 17, count 0 2006.224.08:07:30.20#ibcon#read 5, iclass 17, count 0 2006.224.08:07:30.20#ibcon#about to read 6, iclass 17, count 0 2006.224.08:07:30.20#ibcon#read 6, iclass 17, count 0 2006.224.08:07:30.20#ibcon#end of sib2, iclass 17, count 0 2006.224.08:07:30.20#ibcon#*after write, iclass 17, count 0 2006.224.08:07:30.20#ibcon#*before return 0, iclass 17, count 0 2006.224.08:07:30.20#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.224.08:07:30.20#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.224.08:07:30.20#ibcon#about to clear, iclass 17 cls_cnt 0 2006.224.08:07:30.20#ibcon#cleared, iclass 17 cls_cnt 0 2006.224.08:07:30.20$vc4f8/valo=8,852.99 2006.224.08:07:30.20#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.224.08:07:30.20#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.224.08:07:30.20#ibcon#ireg 17 cls_cnt 0 2006.224.08:07:30.20#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.224.08:07:30.20#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.224.08:07:30.20#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.224.08:07:30.20#ibcon#enter wrdev, iclass 19, count 0 2006.224.08:07:30.20#ibcon#first serial, iclass 19, count 0 2006.224.08:07:30.20#ibcon#enter sib2, iclass 19, count 0 2006.224.08:07:30.20#ibcon#flushed, iclass 19, count 0 2006.224.08:07:30.20#ibcon#about to write, iclass 19, count 0 2006.224.08:07:30.20#ibcon#wrote, iclass 19, count 0 2006.224.08:07:30.20#ibcon#about to read 3, iclass 19, count 0 2006.224.08:07:30.22#ibcon#read 3, iclass 19, count 0 2006.224.08:07:30.22#ibcon#about to read 4, iclass 19, count 0 2006.224.08:07:30.22#ibcon#read 4, iclass 19, count 0 2006.224.08:07:30.22#ibcon#about to read 5, iclass 19, count 0 2006.224.08:07:30.22#ibcon#read 5, iclass 19, count 0 2006.224.08:07:30.22#ibcon#about to read 6, iclass 19, count 0 2006.224.08:07:30.22#ibcon#read 6, iclass 19, count 0 2006.224.08:07:30.22#ibcon#end of sib2, iclass 19, count 0 2006.224.08:07:30.22#ibcon#*mode == 0, iclass 19, count 0 2006.224.08:07:30.22#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.224.08:07:30.22#ibcon#[26=FRQ=08,852.99\r\n] 2006.224.08:07:30.22#ibcon#*before write, iclass 19, count 0 2006.224.08:07:30.22#ibcon#enter sib2, iclass 19, count 0 2006.224.08:07:30.22#ibcon#flushed, iclass 19, count 0 2006.224.08:07:30.22#ibcon#about to write, iclass 19, count 0 2006.224.08:07:30.22#ibcon#wrote, iclass 19, count 0 2006.224.08:07:30.22#ibcon#about to read 3, iclass 19, count 0 2006.224.08:07:30.26#ibcon#read 3, iclass 19, count 0 2006.224.08:07:30.26#ibcon#about to read 4, iclass 19, count 0 2006.224.08:07:30.26#ibcon#read 4, iclass 19, count 0 2006.224.08:07:30.26#ibcon#about to read 5, iclass 19, count 0 2006.224.08:07:30.26#ibcon#read 5, iclass 19, count 0 2006.224.08:07:30.26#ibcon#about to read 6, iclass 19, count 0 2006.224.08:07:30.26#ibcon#read 6, iclass 19, count 0 2006.224.08:07:30.26#ibcon#end of sib2, iclass 19, count 0 2006.224.08:07:30.26#ibcon#*after write, iclass 19, count 0 2006.224.08:07:30.26#ibcon#*before return 0, iclass 19, count 0 2006.224.08:07:30.26#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.224.08:07:30.26#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.224.08:07:30.26#ibcon#about to clear, iclass 19 cls_cnt 0 2006.224.08:07:30.26#ibcon#cleared, iclass 19 cls_cnt 0 2006.224.08:07:30.26$vc4f8/va=8,7 2006.224.08:07:30.26#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.224.08:07:30.26#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.224.08:07:30.26#ibcon#ireg 11 cls_cnt 2 2006.224.08:07:30.26#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.224.08:07:30.32#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.224.08:07:30.32#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.224.08:07:30.32#ibcon#enter wrdev, iclass 21, count 2 2006.224.08:07:30.32#ibcon#first serial, iclass 21, count 2 2006.224.08:07:30.32#ibcon#enter sib2, iclass 21, count 2 2006.224.08:07:30.32#ibcon#flushed, iclass 21, count 2 2006.224.08:07:30.32#ibcon#about to write, iclass 21, count 2 2006.224.08:07:30.32#ibcon#wrote, iclass 21, count 2 2006.224.08:07:30.32#ibcon#about to read 3, iclass 21, count 2 2006.224.08:07:30.34#ibcon#read 3, iclass 21, count 2 2006.224.08:07:30.34#ibcon#about to read 4, iclass 21, count 2 2006.224.08:07:30.34#ibcon#read 4, iclass 21, count 2 2006.224.08:07:30.34#ibcon#about to read 5, iclass 21, count 2 2006.224.08:07:30.34#ibcon#read 5, iclass 21, count 2 2006.224.08:07:30.34#ibcon#about to read 6, iclass 21, count 2 2006.224.08:07:30.34#ibcon#read 6, iclass 21, count 2 2006.224.08:07:30.34#ibcon#end of sib2, iclass 21, count 2 2006.224.08:07:30.34#ibcon#*mode == 0, iclass 21, count 2 2006.224.08:07:30.34#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.224.08:07:30.34#ibcon#[25=AT08-07\r\n] 2006.224.08:07:30.34#ibcon#*before write, iclass 21, count 2 2006.224.08:07:30.34#ibcon#enter sib2, iclass 21, count 2 2006.224.08:07:30.34#ibcon#flushed, iclass 21, count 2 2006.224.08:07:30.34#ibcon#about to write, iclass 21, count 2 2006.224.08:07:30.34#ibcon#wrote, iclass 21, count 2 2006.224.08:07:30.34#ibcon#about to read 3, iclass 21, count 2 2006.224.08:07:30.37#ibcon#read 3, iclass 21, count 2 2006.224.08:07:30.37#ibcon#about to read 4, iclass 21, count 2 2006.224.08:07:30.37#ibcon#read 4, iclass 21, count 2 2006.224.08:07:30.37#ibcon#about to read 5, iclass 21, count 2 2006.224.08:07:30.37#ibcon#read 5, iclass 21, count 2 2006.224.08:07:30.37#ibcon#about to read 6, iclass 21, count 2 2006.224.08:07:30.37#ibcon#read 6, iclass 21, count 2 2006.224.08:07:30.37#ibcon#end of sib2, iclass 21, count 2 2006.224.08:07:30.37#ibcon#*after write, iclass 21, count 2 2006.224.08:07:30.37#ibcon#*before return 0, iclass 21, count 2 2006.224.08:07:30.37#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.224.08:07:30.37#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.224.08:07:30.37#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.224.08:07:30.37#ibcon#ireg 7 cls_cnt 0 2006.224.08:07:30.37#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.224.08:07:30.49#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.224.08:07:30.49#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.224.08:07:30.49#ibcon#enter wrdev, iclass 21, count 0 2006.224.08:07:30.49#ibcon#first serial, iclass 21, count 0 2006.224.08:07:30.49#ibcon#enter sib2, iclass 21, count 0 2006.224.08:07:30.49#ibcon#flushed, iclass 21, count 0 2006.224.08:07:30.49#ibcon#about to write, iclass 21, count 0 2006.224.08:07:30.49#ibcon#wrote, iclass 21, count 0 2006.224.08:07:30.49#ibcon#about to read 3, iclass 21, count 0 2006.224.08:07:30.51#ibcon#read 3, iclass 21, count 0 2006.224.08:07:30.51#ibcon#about to read 4, iclass 21, count 0 2006.224.08:07:30.51#ibcon#read 4, iclass 21, count 0 2006.224.08:07:30.51#ibcon#about to read 5, iclass 21, count 0 2006.224.08:07:30.51#ibcon#read 5, iclass 21, count 0 2006.224.08:07:30.51#ibcon#about to read 6, iclass 21, count 0 2006.224.08:07:30.51#ibcon#read 6, iclass 21, count 0 2006.224.08:07:30.51#ibcon#end of sib2, iclass 21, count 0 2006.224.08:07:30.51#ibcon#*mode == 0, iclass 21, count 0 2006.224.08:07:30.51#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.224.08:07:30.51#ibcon#[25=USB\r\n] 2006.224.08:07:30.51#ibcon#*before write, iclass 21, count 0 2006.224.08:07:30.51#ibcon#enter sib2, iclass 21, count 0 2006.224.08:07:30.51#ibcon#flushed, iclass 21, count 0 2006.224.08:07:30.51#ibcon#about to write, iclass 21, count 0 2006.224.08:07:30.51#ibcon#wrote, iclass 21, count 0 2006.224.08:07:30.51#ibcon#about to read 3, iclass 21, count 0 2006.224.08:07:30.54#ibcon#read 3, iclass 21, count 0 2006.224.08:07:30.54#ibcon#about to read 4, iclass 21, count 0 2006.224.08:07:30.54#ibcon#read 4, iclass 21, count 0 2006.224.08:07:30.54#ibcon#about to read 5, iclass 21, count 0 2006.224.08:07:30.54#ibcon#read 5, iclass 21, count 0 2006.224.08:07:30.54#ibcon#about to read 6, iclass 21, count 0 2006.224.08:07:30.54#ibcon#read 6, iclass 21, count 0 2006.224.08:07:30.54#ibcon#end of sib2, iclass 21, count 0 2006.224.08:07:30.54#ibcon#*after write, iclass 21, count 0 2006.224.08:07:30.54#ibcon#*before return 0, iclass 21, count 0 2006.224.08:07:30.54#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.224.08:07:30.54#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.224.08:07:30.54#ibcon#about to clear, iclass 21 cls_cnt 0 2006.224.08:07:30.54#ibcon#cleared, iclass 21 cls_cnt 0 2006.224.08:07:30.54$vc4f8/vblo=1,632.99 2006.224.08:07:30.54#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.224.08:07:30.54#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.224.08:07:30.54#ibcon#ireg 17 cls_cnt 0 2006.224.08:07:30.54#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.224.08:07:30.54#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.224.08:07:30.54#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.224.08:07:30.54#ibcon#enter wrdev, iclass 23, count 0 2006.224.08:07:30.54#ibcon#first serial, iclass 23, count 0 2006.224.08:07:30.54#ibcon#enter sib2, iclass 23, count 0 2006.224.08:07:30.54#ibcon#flushed, iclass 23, count 0 2006.224.08:07:30.54#ibcon#about to write, iclass 23, count 0 2006.224.08:07:30.54#ibcon#wrote, iclass 23, count 0 2006.224.08:07:30.54#ibcon#about to read 3, iclass 23, count 0 2006.224.08:07:30.56#ibcon#read 3, iclass 23, count 0 2006.224.08:07:30.56#ibcon#about to read 4, iclass 23, count 0 2006.224.08:07:30.56#ibcon#read 4, iclass 23, count 0 2006.224.08:07:30.56#ibcon#about to read 5, iclass 23, count 0 2006.224.08:07:30.56#ibcon#read 5, iclass 23, count 0 2006.224.08:07:30.56#ibcon#about to read 6, iclass 23, count 0 2006.224.08:07:30.56#ibcon#read 6, iclass 23, count 0 2006.224.08:07:30.56#ibcon#end of sib2, iclass 23, count 0 2006.224.08:07:30.56#ibcon#*mode == 0, iclass 23, count 0 2006.224.08:07:30.56#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.224.08:07:30.56#ibcon#[28=FRQ=01,632.99\r\n] 2006.224.08:07:30.56#ibcon#*before write, iclass 23, count 0 2006.224.08:07:30.56#ibcon#enter sib2, iclass 23, count 0 2006.224.08:07:30.56#ibcon#flushed, iclass 23, count 0 2006.224.08:07:30.56#ibcon#about to write, iclass 23, count 0 2006.224.08:07:30.56#ibcon#wrote, iclass 23, count 0 2006.224.08:07:30.56#ibcon#about to read 3, iclass 23, count 0 2006.224.08:07:30.60#ibcon#read 3, iclass 23, count 0 2006.224.08:07:30.60#ibcon#about to read 4, iclass 23, count 0 2006.224.08:07:30.60#ibcon#read 4, iclass 23, count 0 2006.224.08:07:30.60#ibcon#about to read 5, iclass 23, count 0 2006.224.08:07:30.60#ibcon#read 5, iclass 23, count 0 2006.224.08:07:30.60#ibcon#about to read 6, iclass 23, count 0 2006.224.08:07:30.60#ibcon#read 6, iclass 23, count 0 2006.224.08:07:30.60#ibcon#end of sib2, iclass 23, count 0 2006.224.08:07:30.60#ibcon#*after write, iclass 23, count 0 2006.224.08:07:30.60#ibcon#*before return 0, iclass 23, count 0 2006.224.08:07:30.60#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.224.08:07:30.60#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.224.08:07:30.60#ibcon#about to clear, iclass 23 cls_cnt 0 2006.224.08:07:30.60#ibcon#cleared, iclass 23 cls_cnt 0 2006.224.08:07:30.60$vc4f8/vb=1,4 2006.224.08:07:30.60#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.224.08:07:30.60#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.224.08:07:30.60#ibcon#ireg 11 cls_cnt 2 2006.224.08:07:30.60#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.224.08:07:30.60#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.224.08:07:30.60#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.224.08:07:30.60#ibcon#enter wrdev, iclass 25, count 2 2006.224.08:07:30.60#ibcon#first serial, iclass 25, count 2 2006.224.08:07:30.60#ibcon#enter sib2, iclass 25, count 2 2006.224.08:07:30.60#ibcon#flushed, iclass 25, count 2 2006.224.08:07:30.60#ibcon#about to write, iclass 25, count 2 2006.224.08:07:30.60#ibcon#wrote, iclass 25, count 2 2006.224.08:07:30.60#ibcon#about to read 3, iclass 25, count 2 2006.224.08:07:30.62#ibcon#read 3, iclass 25, count 2 2006.224.08:07:30.62#ibcon#about to read 4, iclass 25, count 2 2006.224.08:07:30.62#ibcon#read 4, iclass 25, count 2 2006.224.08:07:30.62#ibcon#about to read 5, iclass 25, count 2 2006.224.08:07:30.62#ibcon#read 5, iclass 25, count 2 2006.224.08:07:30.62#ibcon#about to read 6, iclass 25, count 2 2006.224.08:07:30.62#ibcon#read 6, iclass 25, count 2 2006.224.08:07:30.62#ibcon#end of sib2, iclass 25, count 2 2006.224.08:07:30.62#ibcon#*mode == 0, iclass 25, count 2 2006.224.08:07:30.62#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.224.08:07:30.62#ibcon#[27=AT01-04\r\n] 2006.224.08:07:30.62#ibcon#*before write, iclass 25, count 2 2006.224.08:07:30.62#ibcon#enter sib2, iclass 25, count 2 2006.224.08:07:30.62#ibcon#flushed, iclass 25, count 2 2006.224.08:07:30.62#ibcon#about to write, iclass 25, count 2 2006.224.08:07:30.62#ibcon#wrote, iclass 25, count 2 2006.224.08:07:30.62#ibcon#about to read 3, iclass 25, count 2 2006.224.08:07:30.65#ibcon#read 3, iclass 25, count 2 2006.224.08:07:30.65#ibcon#about to read 4, iclass 25, count 2 2006.224.08:07:30.65#ibcon#read 4, iclass 25, count 2 2006.224.08:07:30.65#ibcon#about to read 5, iclass 25, count 2 2006.224.08:07:30.65#ibcon#read 5, iclass 25, count 2 2006.224.08:07:30.65#ibcon#about to read 6, iclass 25, count 2 2006.224.08:07:30.65#ibcon#read 6, iclass 25, count 2 2006.224.08:07:30.65#ibcon#end of sib2, iclass 25, count 2 2006.224.08:07:30.65#ibcon#*after write, iclass 25, count 2 2006.224.08:07:30.65#ibcon#*before return 0, iclass 25, count 2 2006.224.08:07:30.65#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.224.08:07:30.65#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.224.08:07:30.65#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.224.08:07:30.65#ibcon#ireg 7 cls_cnt 0 2006.224.08:07:30.65#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.224.08:07:30.77#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.224.08:07:30.77#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.224.08:07:30.77#ibcon#enter wrdev, iclass 25, count 0 2006.224.08:07:30.77#ibcon#first serial, iclass 25, count 0 2006.224.08:07:30.77#ibcon#enter sib2, iclass 25, count 0 2006.224.08:07:30.77#ibcon#flushed, iclass 25, count 0 2006.224.08:07:30.77#ibcon#about to write, iclass 25, count 0 2006.224.08:07:30.77#ibcon#wrote, iclass 25, count 0 2006.224.08:07:30.77#ibcon#about to read 3, iclass 25, count 0 2006.224.08:07:30.79#ibcon#read 3, iclass 25, count 0 2006.224.08:07:30.79#ibcon#about to read 4, iclass 25, count 0 2006.224.08:07:30.79#ibcon#read 4, iclass 25, count 0 2006.224.08:07:30.79#ibcon#about to read 5, iclass 25, count 0 2006.224.08:07:30.79#ibcon#read 5, iclass 25, count 0 2006.224.08:07:30.79#ibcon#about to read 6, iclass 25, count 0 2006.224.08:07:30.79#ibcon#read 6, iclass 25, count 0 2006.224.08:07:30.79#ibcon#end of sib2, iclass 25, count 0 2006.224.08:07:30.79#ibcon#*mode == 0, iclass 25, count 0 2006.224.08:07:30.79#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.224.08:07:30.79#ibcon#[27=USB\r\n] 2006.224.08:07:30.79#ibcon#*before write, iclass 25, count 0 2006.224.08:07:30.79#ibcon#enter sib2, iclass 25, count 0 2006.224.08:07:30.79#ibcon#flushed, iclass 25, count 0 2006.224.08:07:30.79#ibcon#about to write, iclass 25, count 0 2006.224.08:07:30.79#ibcon#wrote, iclass 25, count 0 2006.224.08:07:30.79#ibcon#about to read 3, iclass 25, count 0 2006.224.08:07:30.82#ibcon#read 3, iclass 25, count 0 2006.224.08:07:30.82#ibcon#about to read 4, iclass 25, count 0 2006.224.08:07:30.82#ibcon#read 4, iclass 25, count 0 2006.224.08:07:30.82#ibcon#about to read 5, iclass 25, count 0 2006.224.08:07:30.82#ibcon#read 5, iclass 25, count 0 2006.224.08:07:30.82#ibcon#about to read 6, iclass 25, count 0 2006.224.08:07:30.82#ibcon#read 6, iclass 25, count 0 2006.224.08:07:30.82#ibcon#end of sib2, iclass 25, count 0 2006.224.08:07:30.82#ibcon#*after write, iclass 25, count 0 2006.224.08:07:30.82#ibcon#*before return 0, iclass 25, count 0 2006.224.08:07:30.82#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.224.08:07:30.82#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.224.08:07:30.82#ibcon#about to clear, iclass 25 cls_cnt 0 2006.224.08:07:30.82#ibcon#cleared, iclass 25 cls_cnt 0 2006.224.08:07:30.82$vc4f8/vblo=2,640.99 2006.224.08:07:30.82#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.224.08:07:30.82#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.224.08:07:30.82#ibcon#ireg 17 cls_cnt 0 2006.224.08:07:30.82#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.224.08:07:30.82#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.224.08:07:30.82#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.224.08:07:30.82#ibcon#enter wrdev, iclass 27, count 0 2006.224.08:07:30.82#ibcon#first serial, iclass 27, count 0 2006.224.08:07:30.82#ibcon#enter sib2, iclass 27, count 0 2006.224.08:07:30.82#ibcon#flushed, iclass 27, count 0 2006.224.08:07:30.82#ibcon#about to write, iclass 27, count 0 2006.224.08:07:30.82#ibcon#wrote, iclass 27, count 0 2006.224.08:07:30.82#ibcon#about to read 3, iclass 27, count 0 2006.224.08:07:30.84#ibcon#read 3, iclass 27, count 0 2006.224.08:07:30.84#ibcon#about to read 4, iclass 27, count 0 2006.224.08:07:30.84#ibcon#read 4, iclass 27, count 0 2006.224.08:07:30.84#ibcon#about to read 5, iclass 27, count 0 2006.224.08:07:30.84#ibcon#read 5, iclass 27, count 0 2006.224.08:07:30.84#ibcon#about to read 6, iclass 27, count 0 2006.224.08:07:30.84#ibcon#read 6, iclass 27, count 0 2006.224.08:07:30.84#ibcon#end of sib2, iclass 27, count 0 2006.224.08:07:30.84#ibcon#*mode == 0, iclass 27, count 0 2006.224.08:07:30.84#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.224.08:07:30.84#ibcon#[28=FRQ=02,640.99\r\n] 2006.224.08:07:30.84#ibcon#*before write, iclass 27, count 0 2006.224.08:07:30.84#ibcon#enter sib2, iclass 27, count 0 2006.224.08:07:30.84#ibcon#flushed, iclass 27, count 0 2006.224.08:07:30.84#ibcon#about to write, iclass 27, count 0 2006.224.08:07:30.84#ibcon#wrote, iclass 27, count 0 2006.224.08:07:30.84#ibcon#about to read 3, iclass 27, count 0 2006.224.08:07:30.88#ibcon#read 3, iclass 27, count 0 2006.224.08:07:30.88#ibcon#about to read 4, iclass 27, count 0 2006.224.08:07:30.88#ibcon#read 4, iclass 27, count 0 2006.224.08:07:30.88#ibcon#about to read 5, iclass 27, count 0 2006.224.08:07:30.88#ibcon#read 5, iclass 27, count 0 2006.224.08:07:30.88#ibcon#about to read 6, iclass 27, count 0 2006.224.08:07:30.88#ibcon#read 6, iclass 27, count 0 2006.224.08:07:30.88#ibcon#end of sib2, iclass 27, count 0 2006.224.08:07:30.88#ibcon#*after write, iclass 27, count 0 2006.224.08:07:30.88#ibcon#*before return 0, iclass 27, count 0 2006.224.08:07:30.88#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.224.08:07:30.88#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.224.08:07:30.88#ibcon#about to clear, iclass 27 cls_cnt 0 2006.224.08:07:30.88#ibcon#cleared, iclass 27 cls_cnt 0 2006.224.08:07:30.88$vc4f8/vb=2,4 2006.224.08:07:30.88#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.224.08:07:30.88#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.224.08:07:30.88#ibcon#ireg 11 cls_cnt 2 2006.224.08:07:30.88#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.224.08:07:30.94#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.224.08:07:30.94#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.224.08:07:30.94#ibcon#enter wrdev, iclass 29, count 2 2006.224.08:07:30.94#ibcon#first serial, iclass 29, count 2 2006.224.08:07:30.94#ibcon#enter sib2, iclass 29, count 2 2006.224.08:07:30.94#ibcon#flushed, iclass 29, count 2 2006.224.08:07:30.94#ibcon#about to write, iclass 29, count 2 2006.224.08:07:30.94#ibcon#wrote, iclass 29, count 2 2006.224.08:07:30.94#ibcon#about to read 3, iclass 29, count 2 2006.224.08:07:30.96#ibcon#read 3, iclass 29, count 2 2006.224.08:07:30.96#ibcon#about to read 4, iclass 29, count 2 2006.224.08:07:30.96#ibcon#read 4, iclass 29, count 2 2006.224.08:07:30.96#ibcon#about to read 5, iclass 29, count 2 2006.224.08:07:30.96#ibcon#read 5, iclass 29, count 2 2006.224.08:07:30.96#ibcon#about to read 6, iclass 29, count 2 2006.224.08:07:30.96#ibcon#read 6, iclass 29, count 2 2006.224.08:07:30.96#ibcon#end of sib2, iclass 29, count 2 2006.224.08:07:30.96#ibcon#*mode == 0, iclass 29, count 2 2006.224.08:07:30.96#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.224.08:07:30.96#ibcon#[27=AT02-04\r\n] 2006.224.08:07:30.96#ibcon#*before write, iclass 29, count 2 2006.224.08:07:30.96#ibcon#enter sib2, iclass 29, count 2 2006.224.08:07:30.96#ibcon#flushed, iclass 29, count 2 2006.224.08:07:30.96#ibcon#about to write, iclass 29, count 2 2006.224.08:07:30.96#ibcon#wrote, iclass 29, count 2 2006.224.08:07:30.96#ibcon#about to read 3, iclass 29, count 2 2006.224.08:07:30.99#ibcon#read 3, iclass 29, count 2 2006.224.08:07:30.99#ibcon#about to read 4, iclass 29, count 2 2006.224.08:07:30.99#ibcon#read 4, iclass 29, count 2 2006.224.08:07:30.99#ibcon#about to read 5, iclass 29, count 2 2006.224.08:07:30.99#ibcon#read 5, iclass 29, count 2 2006.224.08:07:30.99#ibcon#about to read 6, iclass 29, count 2 2006.224.08:07:30.99#ibcon#read 6, iclass 29, count 2 2006.224.08:07:30.99#ibcon#end of sib2, iclass 29, count 2 2006.224.08:07:30.99#ibcon#*after write, iclass 29, count 2 2006.224.08:07:30.99#ibcon#*before return 0, iclass 29, count 2 2006.224.08:07:30.99#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.224.08:07:30.99#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.224.08:07:30.99#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.224.08:07:30.99#ibcon#ireg 7 cls_cnt 0 2006.224.08:07:30.99#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.224.08:07:31.11#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.224.08:07:31.11#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.224.08:07:31.11#ibcon#enter wrdev, iclass 29, count 0 2006.224.08:07:31.11#ibcon#first serial, iclass 29, count 0 2006.224.08:07:31.11#ibcon#enter sib2, iclass 29, count 0 2006.224.08:07:31.11#ibcon#flushed, iclass 29, count 0 2006.224.08:07:31.11#ibcon#about to write, iclass 29, count 0 2006.224.08:07:31.11#ibcon#wrote, iclass 29, count 0 2006.224.08:07:31.11#ibcon#about to read 3, iclass 29, count 0 2006.224.08:07:31.13#ibcon#read 3, iclass 29, count 0 2006.224.08:07:31.13#ibcon#about to read 4, iclass 29, count 0 2006.224.08:07:31.13#ibcon#read 4, iclass 29, count 0 2006.224.08:07:31.13#ibcon#about to read 5, iclass 29, count 0 2006.224.08:07:31.13#ibcon#read 5, iclass 29, count 0 2006.224.08:07:31.13#ibcon#about to read 6, iclass 29, count 0 2006.224.08:07:31.13#ibcon#read 6, iclass 29, count 0 2006.224.08:07:31.13#ibcon#end of sib2, iclass 29, count 0 2006.224.08:07:31.13#ibcon#*mode == 0, iclass 29, count 0 2006.224.08:07:31.13#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.224.08:07:31.13#ibcon#[27=USB\r\n] 2006.224.08:07:31.13#ibcon#*before write, iclass 29, count 0 2006.224.08:07:31.13#ibcon#enter sib2, iclass 29, count 0 2006.224.08:07:31.13#ibcon#flushed, iclass 29, count 0 2006.224.08:07:31.13#ibcon#about to write, iclass 29, count 0 2006.224.08:07:31.13#ibcon#wrote, iclass 29, count 0 2006.224.08:07:31.13#ibcon#about to read 3, iclass 29, count 0 2006.224.08:07:31.16#ibcon#read 3, iclass 29, count 0 2006.224.08:07:31.16#ibcon#about to read 4, iclass 29, count 0 2006.224.08:07:31.16#ibcon#read 4, iclass 29, count 0 2006.224.08:07:31.16#ibcon#about to read 5, iclass 29, count 0 2006.224.08:07:31.16#ibcon#read 5, iclass 29, count 0 2006.224.08:07:31.16#ibcon#about to read 6, iclass 29, count 0 2006.224.08:07:31.16#ibcon#read 6, iclass 29, count 0 2006.224.08:07:31.16#ibcon#end of sib2, iclass 29, count 0 2006.224.08:07:31.16#ibcon#*after write, iclass 29, count 0 2006.224.08:07:31.16#ibcon#*before return 0, iclass 29, count 0 2006.224.08:07:31.16#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.224.08:07:31.16#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.224.08:07:31.16#ibcon#about to clear, iclass 29 cls_cnt 0 2006.224.08:07:31.16#ibcon#cleared, iclass 29 cls_cnt 0 2006.224.08:07:31.16$vc4f8/vblo=3,656.99 2006.224.08:07:31.16#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.224.08:07:31.16#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.224.08:07:31.16#ibcon#ireg 17 cls_cnt 0 2006.224.08:07:31.16#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.224.08:07:31.16#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.224.08:07:31.16#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.224.08:07:31.16#ibcon#enter wrdev, iclass 31, count 0 2006.224.08:07:31.16#ibcon#first serial, iclass 31, count 0 2006.224.08:07:31.16#ibcon#enter sib2, iclass 31, count 0 2006.224.08:07:31.16#ibcon#flushed, iclass 31, count 0 2006.224.08:07:31.16#ibcon#about to write, iclass 31, count 0 2006.224.08:07:31.16#ibcon#wrote, iclass 31, count 0 2006.224.08:07:31.16#ibcon#about to read 3, iclass 31, count 0 2006.224.08:07:31.18#ibcon#read 3, iclass 31, count 0 2006.224.08:07:31.18#ibcon#about to read 4, iclass 31, count 0 2006.224.08:07:31.18#ibcon#read 4, iclass 31, count 0 2006.224.08:07:31.18#ibcon#about to read 5, iclass 31, count 0 2006.224.08:07:31.18#ibcon#read 5, iclass 31, count 0 2006.224.08:07:31.18#ibcon#about to read 6, iclass 31, count 0 2006.224.08:07:31.18#ibcon#read 6, iclass 31, count 0 2006.224.08:07:31.18#ibcon#end of sib2, iclass 31, count 0 2006.224.08:07:31.18#ibcon#*mode == 0, iclass 31, count 0 2006.224.08:07:31.18#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.224.08:07:31.18#ibcon#[28=FRQ=03,656.99\r\n] 2006.224.08:07:31.18#ibcon#*before write, iclass 31, count 0 2006.224.08:07:31.18#ibcon#enter sib2, iclass 31, count 0 2006.224.08:07:31.18#ibcon#flushed, iclass 31, count 0 2006.224.08:07:31.18#ibcon#about to write, iclass 31, count 0 2006.224.08:07:31.18#ibcon#wrote, iclass 31, count 0 2006.224.08:07:31.18#ibcon#about to read 3, iclass 31, count 0 2006.224.08:07:31.22#ibcon#read 3, iclass 31, count 0 2006.224.08:07:31.22#ibcon#about to read 4, iclass 31, count 0 2006.224.08:07:31.22#ibcon#read 4, iclass 31, count 0 2006.224.08:07:31.22#ibcon#about to read 5, iclass 31, count 0 2006.224.08:07:31.22#ibcon#read 5, iclass 31, count 0 2006.224.08:07:31.22#ibcon#about to read 6, iclass 31, count 0 2006.224.08:07:31.22#ibcon#read 6, iclass 31, count 0 2006.224.08:07:31.22#ibcon#end of sib2, iclass 31, count 0 2006.224.08:07:31.22#ibcon#*after write, iclass 31, count 0 2006.224.08:07:31.22#ibcon#*before return 0, iclass 31, count 0 2006.224.08:07:31.22#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.224.08:07:31.22#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.224.08:07:31.22#ibcon#about to clear, iclass 31 cls_cnt 0 2006.224.08:07:31.22#ibcon#cleared, iclass 31 cls_cnt 0 2006.224.08:07:31.22$vc4f8/vb=3,4 2006.224.08:07:31.22#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.224.08:07:31.22#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.224.08:07:31.22#ibcon#ireg 11 cls_cnt 2 2006.224.08:07:31.22#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.224.08:07:31.28#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.224.08:07:31.28#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.224.08:07:31.28#ibcon#enter wrdev, iclass 33, count 2 2006.224.08:07:31.28#ibcon#first serial, iclass 33, count 2 2006.224.08:07:31.28#ibcon#enter sib2, iclass 33, count 2 2006.224.08:07:31.28#ibcon#flushed, iclass 33, count 2 2006.224.08:07:31.28#ibcon#about to write, iclass 33, count 2 2006.224.08:07:31.28#ibcon#wrote, iclass 33, count 2 2006.224.08:07:31.28#ibcon#about to read 3, iclass 33, count 2 2006.224.08:07:31.30#ibcon#read 3, iclass 33, count 2 2006.224.08:07:31.30#ibcon#about to read 4, iclass 33, count 2 2006.224.08:07:31.30#ibcon#read 4, iclass 33, count 2 2006.224.08:07:31.30#ibcon#about to read 5, iclass 33, count 2 2006.224.08:07:31.30#ibcon#read 5, iclass 33, count 2 2006.224.08:07:31.30#ibcon#about to read 6, iclass 33, count 2 2006.224.08:07:31.30#ibcon#read 6, iclass 33, count 2 2006.224.08:07:31.30#ibcon#end of sib2, iclass 33, count 2 2006.224.08:07:31.30#ibcon#*mode == 0, iclass 33, count 2 2006.224.08:07:31.30#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.224.08:07:31.30#ibcon#[27=AT03-04\r\n] 2006.224.08:07:31.30#ibcon#*before write, iclass 33, count 2 2006.224.08:07:31.30#ibcon#enter sib2, iclass 33, count 2 2006.224.08:07:31.30#ibcon#flushed, iclass 33, count 2 2006.224.08:07:31.30#ibcon#about to write, iclass 33, count 2 2006.224.08:07:31.30#ibcon#wrote, iclass 33, count 2 2006.224.08:07:31.30#ibcon#about to read 3, iclass 33, count 2 2006.224.08:07:31.33#ibcon#read 3, iclass 33, count 2 2006.224.08:07:31.33#ibcon#about to read 4, iclass 33, count 2 2006.224.08:07:31.33#ibcon#read 4, iclass 33, count 2 2006.224.08:07:31.33#ibcon#about to read 5, iclass 33, count 2 2006.224.08:07:31.33#ibcon#read 5, iclass 33, count 2 2006.224.08:07:31.33#ibcon#about to read 6, iclass 33, count 2 2006.224.08:07:31.33#ibcon#read 6, iclass 33, count 2 2006.224.08:07:31.33#ibcon#end of sib2, iclass 33, count 2 2006.224.08:07:31.33#ibcon#*after write, iclass 33, count 2 2006.224.08:07:31.33#ibcon#*before return 0, iclass 33, count 2 2006.224.08:07:31.33#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.224.08:07:31.33#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.224.08:07:31.33#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.224.08:07:31.33#ibcon#ireg 7 cls_cnt 0 2006.224.08:07:31.33#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.224.08:07:31.45#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.224.08:07:31.45#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.224.08:07:31.45#ibcon#enter wrdev, iclass 33, count 0 2006.224.08:07:31.45#ibcon#first serial, iclass 33, count 0 2006.224.08:07:31.45#ibcon#enter sib2, iclass 33, count 0 2006.224.08:07:31.45#ibcon#flushed, iclass 33, count 0 2006.224.08:07:31.45#ibcon#about to write, iclass 33, count 0 2006.224.08:07:31.45#ibcon#wrote, iclass 33, count 0 2006.224.08:07:31.45#ibcon#about to read 3, iclass 33, count 0 2006.224.08:07:31.47#ibcon#read 3, iclass 33, count 0 2006.224.08:07:31.47#ibcon#about to read 4, iclass 33, count 0 2006.224.08:07:31.47#ibcon#read 4, iclass 33, count 0 2006.224.08:07:31.47#ibcon#about to read 5, iclass 33, count 0 2006.224.08:07:31.47#ibcon#read 5, iclass 33, count 0 2006.224.08:07:31.47#ibcon#about to read 6, iclass 33, count 0 2006.224.08:07:31.47#ibcon#read 6, iclass 33, count 0 2006.224.08:07:31.47#ibcon#end of sib2, iclass 33, count 0 2006.224.08:07:31.47#ibcon#*mode == 0, iclass 33, count 0 2006.224.08:07:31.47#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.224.08:07:31.47#ibcon#[27=USB\r\n] 2006.224.08:07:31.47#ibcon#*before write, iclass 33, count 0 2006.224.08:07:31.47#ibcon#enter sib2, iclass 33, count 0 2006.224.08:07:31.47#ibcon#flushed, iclass 33, count 0 2006.224.08:07:31.47#ibcon#about to write, iclass 33, count 0 2006.224.08:07:31.47#ibcon#wrote, iclass 33, count 0 2006.224.08:07:31.47#ibcon#about to read 3, iclass 33, count 0 2006.224.08:07:31.50#ibcon#read 3, iclass 33, count 0 2006.224.08:07:31.50#ibcon#about to read 4, iclass 33, count 0 2006.224.08:07:31.50#ibcon#read 4, iclass 33, count 0 2006.224.08:07:31.50#ibcon#about to read 5, iclass 33, count 0 2006.224.08:07:31.50#ibcon#read 5, iclass 33, count 0 2006.224.08:07:31.50#ibcon#about to read 6, iclass 33, count 0 2006.224.08:07:31.50#ibcon#read 6, iclass 33, count 0 2006.224.08:07:31.50#ibcon#end of sib2, iclass 33, count 0 2006.224.08:07:31.50#ibcon#*after write, iclass 33, count 0 2006.224.08:07:31.50#ibcon#*before return 0, iclass 33, count 0 2006.224.08:07:31.50#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.224.08:07:31.50#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.224.08:07:31.50#ibcon#about to clear, iclass 33 cls_cnt 0 2006.224.08:07:31.50#ibcon#cleared, iclass 33 cls_cnt 0 2006.224.08:07:31.50$vc4f8/vblo=4,712.99 2006.224.08:07:31.50#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.224.08:07:31.50#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.224.08:07:31.50#ibcon#ireg 17 cls_cnt 0 2006.224.08:07:31.50#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.224.08:07:31.50#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.224.08:07:31.50#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.224.08:07:31.50#ibcon#enter wrdev, iclass 35, count 0 2006.224.08:07:31.50#ibcon#first serial, iclass 35, count 0 2006.224.08:07:31.50#ibcon#enter sib2, iclass 35, count 0 2006.224.08:07:31.50#ibcon#flushed, iclass 35, count 0 2006.224.08:07:31.50#ibcon#about to write, iclass 35, count 0 2006.224.08:07:31.50#ibcon#wrote, iclass 35, count 0 2006.224.08:07:31.50#ibcon#about to read 3, iclass 35, count 0 2006.224.08:07:31.52#ibcon#read 3, iclass 35, count 0 2006.224.08:07:31.52#ibcon#about to read 4, iclass 35, count 0 2006.224.08:07:31.52#ibcon#read 4, iclass 35, count 0 2006.224.08:07:31.52#ibcon#about to read 5, iclass 35, count 0 2006.224.08:07:31.52#ibcon#read 5, iclass 35, count 0 2006.224.08:07:31.52#ibcon#about to read 6, iclass 35, count 0 2006.224.08:07:31.52#ibcon#read 6, iclass 35, count 0 2006.224.08:07:31.52#ibcon#end of sib2, iclass 35, count 0 2006.224.08:07:31.52#ibcon#*mode == 0, iclass 35, count 0 2006.224.08:07:31.52#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.224.08:07:31.52#ibcon#[28=FRQ=04,712.99\r\n] 2006.224.08:07:31.52#ibcon#*before write, iclass 35, count 0 2006.224.08:07:31.52#ibcon#enter sib2, iclass 35, count 0 2006.224.08:07:31.52#ibcon#flushed, iclass 35, count 0 2006.224.08:07:31.52#ibcon#about to write, iclass 35, count 0 2006.224.08:07:31.52#ibcon#wrote, iclass 35, count 0 2006.224.08:07:31.52#ibcon#about to read 3, iclass 35, count 0 2006.224.08:07:31.56#ibcon#read 3, iclass 35, count 0 2006.224.08:07:31.56#ibcon#about to read 4, iclass 35, count 0 2006.224.08:07:31.56#ibcon#read 4, iclass 35, count 0 2006.224.08:07:31.56#ibcon#about to read 5, iclass 35, count 0 2006.224.08:07:31.56#ibcon#read 5, iclass 35, count 0 2006.224.08:07:31.56#ibcon#about to read 6, iclass 35, count 0 2006.224.08:07:31.56#ibcon#read 6, iclass 35, count 0 2006.224.08:07:31.56#ibcon#end of sib2, iclass 35, count 0 2006.224.08:07:31.56#ibcon#*after write, iclass 35, count 0 2006.224.08:07:31.56#ibcon#*before return 0, iclass 35, count 0 2006.224.08:07:31.56#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.224.08:07:31.56#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.224.08:07:31.56#ibcon#about to clear, iclass 35 cls_cnt 0 2006.224.08:07:31.56#ibcon#cleared, iclass 35 cls_cnt 0 2006.224.08:07:31.56$vc4f8/vb=4,4 2006.224.08:07:31.56#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.224.08:07:31.56#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.224.08:07:31.56#ibcon#ireg 11 cls_cnt 2 2006.224.08:07:31.56#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.224.08:07:31.62#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.224.08:07:31.62#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.224.08:07:31.62#ibcon#enter wrdev, iclass 37, count 2 2006.224.08:07:31.62#ibcon#first serial, iclass 37, count 2 2006.224.08:07:31.62#ibcon#enter sib2, iclass 37, count 2 2006.224.08:07:31.62#ibcon#flushed, iclass 37, count 2 2006.224.08:07:31.62#ibcon#about to write, iclass 37, count 2 2006.224.08:07:31.62#ibcon#wrote, iclass 37, count 2 2006.224.08:07:31.62#ibcon#about to read 3, iclass 37, count 2 2006.224.08:07:31.64#ibcon#read 3, iclass 37, count 2 2006.224.08:07:31.64#ibcon#about to read 4, iclass 37, count 2 2006.224.08:07:31.64#ibcon#read 4, iclass 37, count 2 2006.224.08:07:31.64#ibcon#about to read 5, iclass 37, count 2 2006.224.08:07:31.64#ibcon#read 5, iclass 37, count 2 2006.224.08:07:31.64#ibcon#about to read 6, iclass 37, count 2 2006.224.08:07:31.64#ibcon#read 6, iclass 37, count 2 2006.224.08:07:31.64#ibcon#end of sib2, iclass 37, count 2 2006.224.08:07:31.64#ibcon#*mode == 0, iclass 37, count 2 2006.224.08:07:31.64#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.224.08:07:31.64#ibcon#[27=AT04-04\r\n] 2006.224.08:07:31.64#ibcon#*before write, iclass 37, count 2 2006.224.08:07:31.64#ibcon#enter sib2, iclass 37, count 2 2006.224.08:07:31.64#ibcon#flushed, iclass 37, count 2 2006.224.08:07:31.64#ibcon#about to write, iclass 37, count 2 2006.224.08:07:31.64#ibcon#wrote, iclass 37, count 2 2006.224.08:07:31.64#ibcon#about to read 3, iclass 37, count 2 2006.224.08:07:31.67#ibcon#read 3, iclass 37, count 2 2006.224.08:07:31.67#ibcon#about to read 4, iclass 37, count 2 2006.224.08:07:31.67#ibcon#read 4, iclass 37, count 2 2006.224.08:07:31.67#ibcon#about to read 5, iclass 37, count 2 2006.224.08:07:31.67#ibcon#read 5, iclass 37, count 2 2006.224.08:07:31.67#ibcon#about to read 6, iclass 37, count 2 2006.224.08:07:31.67#ibcon#read 6, iclass 37, count 2 2006.224.08:07:31.67#ibcon#end of sib2, iclass 37, count 2 2006.224.08:07:31.67#ibcon#*after write, iclass 37, count 2 2006.224.08:07:31.67#ibcon#*before return 0, iclass 37, count 2 2006.224.08:07:31.67#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.224.08:07:31.67#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.224.08:07:31.67#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.224.08:07:31.67#ibcon#ireg 7 cls_cnt 0 2006.224.08:07:31.67#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.224.08:07:31.79#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.224.08:07:31.79#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.224.08:07:31.79#ibcon#enter wrdev, iclass 37, count 0 2006.224.08:07:31.79#ibcon#first serial, iclass 37, count 0 2006.224.08:07:31.79#ibcon#enter sib2, iclass 37, count 0 2006.224.08:07:31.79#ibcon#flushed, iclass 37, count 0 2006.224.08:07:31.79#ibcon#about to write, iclass 37, count 0 2006.224.08:07:31.79#ibcon#wrote, iclass 37, count 0 2006.224.08:07:31.79#ibcon#about to read 3, iclass 37, count 0 2006.224.08:07:31.81#ibcon#read 3, iclass 37, count 0 2006.224.08:07:31.81#ibcon#about to read 4, iclass 37, count 0 2006.224.08:07:31.81#ibcon#read 4, iclass 37, count 0 2006.224.08:07:31.81#ibcon#about to read 5, iclass 37, count 0 2006.224.08:07:31.81#ibcon#read 5, iclass 37, count 0 2006.224.08:07:31.81#ibcon#about to read 6, iclass 37, count 0 2006.224.08:07:31.81#ibcon#read 6, iclass 37, count 0 2006.224.08:07:31.81#ibcon#end of sib2, iclass 37, count 0 2006.224.08:07:31.81#ibcon#*mode == 0, iclass 37, count 0 2006.224.08:07:31.81#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.224.08:07:31.81#ibcon#[27=USB\r\n] 2006.224.08:07:31.81#ibcon#*before write, iclass 37, count 0 2006.224.08:07:31.81#ibcon#enter sib2, iclass 37, count 0 2006.224.08:07:31.81#ibcon#flushed, iclass 37, count 0 2006.224.08:07:31.81#ibcon#about to write, iclass 37, count 0 2006.224.08:07:31.81#ibcon#wrote, iclass 37, count 0 2006.224.08:07:31.81#ibcon#about to read 3, iclass 37, count 0 2006.224.08:07:31.84#ibcon#read 3, iclass 37, count 0 2006.224.08:07:31.84#ibcon#about to read 4, iclass 37, count 0 2006.224.08:07:31.84#ibcon#read 4, iclass 37, count 0 2006.224.08:07:31.84#ibcon#about to read 5, iclass 37, count 0 2006.224.08:07:31.84#ibcon#read 5, iclass 37, count 0 2006.224.08:07:31.84#ibcon#about to read 6, iclass 37, count 0 2006.224.08:07:31.84#ibcon#read 6, iclass 37, count 0 2006.224.08:07:31.84#ibcon#end of sib2, iclass 37, count 0 2006.224.08:07:31.84#ibcon#*after write, iclass 37, count 0 2006.224.08:07:31.84#ibcon#*before return 0, iclass 37, count 0 2006.224.08:07:31.84#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.224.08:07:31.84#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.224.08:07:31.84#ibcon#about to clear, iclass 37 cls_cnt 0 2006.224.08:07:31.84#ibcon#cleared, iclass 37 cls_cnt 0 2006.224.08:07:31.84$vc4f8/vblo=5,744.99 2006.224.08:07:31.84#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.224.08:07:31.84#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.224.08:07:31.84#ibcon#ireg 17 cls_cnt 0 2006.224.08:07:31.84#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.224.08:07:31.84#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.224.08:07:31.84#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.224.08:07:31.84#ibcon#enter wrdev, iclass 39, count 0 2006.224.08:07:31.84#ibcon#first serial, iclass 39, count 0 2006.224.08:07:31.84#ibcon#enter sib2, iclass 39, count 0 2006.224.08:07:31.84#ibcon#flushed, iclass 39, count 0 2006.224.08:07:31.84#ibcon#about to write, iclass 39, count 0 2006.224.08:07:31.84#ibcon#wrote, iclass 39, count 0 2006.224.08:07:31.84#ibcon#about to read 3, iclass 39, count 0 2006.224.08:07:31.86#ibcon#read 3, iclass 39, count 0 2006.224.08:07:31.86#ibcon#about to read 4, iclass 39, count 0 2006.224.08:07:31.86#ibcon#read 4, iclass 39, count 0 2006.224.08:07:31.86#ibcon#about to read 5, iclass 39, count 0 2006.224.08:07:31.86#ibcon#read 5, iclass 39, count 0 2006.224.08:07:31.86#ibcon#about to read 6, iclass 39, count 0 2006.224.08:07:31.86#ibcon#read 6, iclass 39, count 0 2006.224.08:07:31.86#ibcon#end of sib2, iclass 39, count 0 2006.224.08:07:31.86#ibcon#*mode == 0, iclass 39, count 0 2006.224.08:07:31.86#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.224.08:07:31.86#ibcon#[28=FRQ=05,744.99\r\n] 2006.224.08:07:31.86#ibcon#*before write, iclass 39, count 0 2006.224.08:07:31.86#ibcon#enter sib2, iclass 39, count 0 2006.224.08:07:31.86#ibcon#flushed, iclass 39, count 0 2006.224.08:07:31.86#ibcon#about to write, iclass 39, count 0 2006.224.08:07:31.86#ibcon#wrote, iclass 39, count 0 2006.224.08:07:31.86#ibcon#about to read 3, iclass 39, count 0 2006.224.08:07:31.90#ibcon#read 3, iclass 39, count 0 2006.224.08:07:31.90#ibcon#about to read 4, iclass 39, count 0 2006.224.08:07:31.90#ibcon#read 4, iclass 39, count 0 2006.224.08:07:31.90#ibcon#about to read 5, iclass 39, count 0 2006.224.08:07:31.90#ibcon#read 5, iclass 39, count 0 2006.224.08:07:31.90#ibcon#about to read 6, iclass 39, count 0 2006.224.08:07:31.90#ibcon#read 6, iclass 39, count 0 2006.224.08:07:31.90#ibcon#end of sib2, iclass 39, count 0 2006.224.08:07:31.90#ibcon#*after write, iclass 39, count 0 2006.224.08:07:31.90#ibcon#*before return 0, iclass 39, count 0 2006.224.08:07:31.90#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.224.08:07:31.90#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.224.08:07:31.90#ibcon#about to clear, iclass 39 cls_cnt 0 2006.224.08:07:31.90#ibcon#cleared, iclass 39 cls_cnt 0 2006.224.08:07:31.90$vc4f8/vb=5,4 2006.224.08:07:31.90#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.224.08:07:31.90#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.224.08:07:31.90#ibcon#ireg 11 cls_cnt 2 2006.224.08:07:31.90#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.224.08:07:31.96#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.224.08:07:31.96#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.224.08:07:31.96#ibcon#enter wrdev, iclass 3, count 2 2006.224.08:07:31.96#ibcon#first serial, iclass 3, count 2 2006.224.08:07:31.96#ibcon#enter sib2, iclass 3, count 2 2006.224.08:07:31.96#ibcon#flushed, iclass 3, count 2 2006.224.08:07:31.96#ibcon#about to write, iclass 3, count 2 2006.224.08:07:31.96#ibcon#wrote, iclass 3, count 2 2006.224.08:07:31.96#ibcon#about to read 3, iclass 3, count 2 2006.224.08:07:31.98#ibcon#read 3, iclass 3, count 2 2006.224.08:07:31.98#ibcon#about to read 4, iclass 3, count 2 2006.224.08:07:31.98#ibcon#read 4, iclass 3, count 2 2006.224.08:07:31.98#ibcon#about to read 5, iclass 3, count 2 2006.224.08:07:31.98#ibcon#read 5, iclass 3, count 2 2006.224.08:07:31.98#ibcon#about to read 6, iclass 3, count 2 2006.224.08:07:31.98#ibcon#read 6, iclass 3, count 2 2006.224.08:07:31.98#ibcon#end of sib2, iclass 3, count 2 2006.224.08:07:31.98#ibcon#*mode == 0, iclass 3, count 2 2006.224.08:07:31.98#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.224.08:07:31.98#ibcon#[27=AT05-04\r\n] 2006.224.08:07:31.98#ibcon#*before write, iclass 3, count 2 2006.224.08:07:31.98#ibcon#enter sib2, iclass 3, count 2 2006.224.08:07:31.98#ibcon#flushed, iclass 3, count 2 2006.224.08:07:31.98#ibcon#about to write, iclass 3, count 2 2006.224.08:07:31.98#ibcon#wrote, iclass 3, count 2 2006.224.08:07:31.98#ibcon#about to read 3, iclass 3, count 2 2006.224.08:07:32.01#ibcon#read 3, iclass 3, count 2 2006.224.08:07:32.01#ibcon#about to read 4, iclass 3, count 2 2006.224.08:07:32.01#ibcon#read 4, iclass 3, count 2 2006.224.08:07:32.01#ibcon#about to read 5, iclass 3, count 2 2006.224.08:07:32.01#ibcon#read 5, iclass 3, count 2 2006.224.08:07:32.01#ibcon#about to read 6, iclass 3, count 2 2006.224.08:07:32.01#ibcon#read 6, iclass 3, count 2 2006.224.08:07:32.01#ibcon#end of sib2, iclass 3, count 2 2006.224.08:07:32.01#ibcon#*after write, iclass 3, count 2 2006.224.08:07:32.01#ibcon#*before return 0, iclass 3, count 2 2006.224.08:07:32.01#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.224.08:07:32.01#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.224.08:07:32.01#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.224.08:07:32.01#ibcon#ireg 7 cls_cnt 0 2006.224.08:07:32.01#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.224.08:07:32.07#abcon#<5=/10 1.6 2.8 23.661001004.8\r\n> 2006.224.08:07:32.09#abcon#{5=INTERFACE CLEAR} 2006.224.08:07:32.13#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.224.08:07:32.13#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.224.08:07:32.13#ibcon#enter wrdev, iclass 3, count 0 2006.224.08:07:32.13#ibcon#first serial, iclass 3, count 0 2006.224.08:07:32.13#ibcon#enter sib2, iclass 3, count 0 2006.224.08:07:32.13#ibcon#flushed, iclass 3, count 0 2006.224.08:07:32.13#ibcon#about to write, iclass 3, count 0 2006.224.08:07:32.13#ibcon#wrote, iclass 3, count 0 2006.224.08:07:32.13#ibcon#about to read 3, iclass 3, count 0 2006.224.08:07:32.15#ibcon#read 3, iclass 3, count 0 2006.224.08:07:32.15#ibcon#about to read 4, iclass 3, count 0 2006.224.08:07:32.15#ibcon#read 4, iclass 3, count 0 2006.224.08:07:32.15#ibcon#about to read 5, iclass 3, count 0 2006.224.08:07:32.15#ibcon#read 5, iclass 3, count 0 2006.224.08:07:32.15#ibcon#about to read 6, iclass 3, count 0 2006.224.08:07:32.15#ibcon#read 6, iclass 3, count 0 2006.224.08:07:32.15#ibcon#end of sib2, iclass 3, count 0 2006.224.08:07:32.15#ibcon#*mode == 0, iclass 3, count 0 2006.224.08:07:32.15#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.224.08:07:32.15#ibcon#[27=USB\r\n] 2006.224.08:07:32.15#ibcon#*before write, iclass 3, count 0 2006.224.08:07:32.15#ibcon#enter sib2, iclass 3, count 0 2006.224.08:07:32.15#ibcon#flushed, iclass 3, count 0 2006.224.08:07:32.15#ibcon#about to write, iclass 3, count 0 2006.224.08:07:32.15#ibcon#wrote, iclass 3, count 0 2006.224.08:07:32.15#ibcon#about to read 3, iclass 3, count 0 2006.224.08:07:32.15#abcon#[5=S1D000X0/0*\r\n] 2006.224.08:07:32.18#ibcon#read 3, iclass 3, count 0 2006.224.08:07:32.18#ibcon#about to read 4, iclass 3, count 0 2006.224.08:07:32.18#ibcon#read 4, iclass 3, count 0 2006.224.08:07:32.18#ibcon#about to read 5, iclass 3, count 0 2006.224.08:07:32.18#ibcon#read 5, iclass 3, count 0 2006.224.08:07:32.18#ibcon#about to read 6, iclass 3, count 0 2006.224.08:07:32.18#ibcon#read 6, iclass 3, count 0 2006.224.08:07:32.18#ibcon#end of sib2, iclass 3, count 0 2006.224.08:07:32.18#ibcon#*after write, iclass 3, count 0 2006.224.08:07:32.18#ibcon#*before return 0, iclass 3, count 0 2006.224.08:07:32.18#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.224.08:07:32.18#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.224.08:07:32.18#ibcon#about to clear, iclass 3 cls_cnt 0 2006.224.08:07:32.18#ibcon#cleared, iclass 3 cls_cnt 0 2006.224.08:07:32.18$vc4f8/vblo=6,752.99 2006.224.08:07:32.18#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.224.08:07:32.18#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.224.08:07:32.18#ibcon#ireg 17 cls_cnt 0 2006.224.08:07:32.18#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.224.08:07:32.18#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.224.08:07:32.18#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.224.08:07:32.18#ibcon#enter wrdev, iclass 11, count 0 2006.224.08:07:32.18#ibcon#first serial, iclass 11, count 0 2006.224.08:07:32.18#ibcon#enter sib2, iclass 11, count 0 2006.224.08:07:32.18#ibcon#flushed, iclass 11, count 0 2006.224.08:07:32.18#ibcon#about to write, iclass 11, count 0 2006.224.08:07:32.18#ibcon#wrote, iclass 11, count 0 2006.224.08:07:32.18#ibcon#about to read 3, iclass 11, count 0 2006.224.08:07:32.20#ibcon#read 3, iclass 11, count 0 2006.224.08:07:32.20#ibcon#about to read 4, iclass 11, count 0 2006.224.08:07:32.20#ibcon#read 4, iclass 11, count 0 2006.224.08:07:32.20#ibcon#about to read 5, iclass 11, count 0 2006.224.08:07:32.20#ibcon#read 5, iclass 11, count 0 2006.224.08:07:32.20#ibcon#about to read 6, iclass 11, count 0 2006.224.08:07:32.20#ibcon#read 6, iclass 11, count 0 2006.224.08:07:32.20#ibcon#end of sib2, iclass 11, count 0 2006.224.08:07:32.20#ibcon#*mode == 0, iclass 11, count 0 2006.224.08:07:32.20#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.224.08:07:32.20#ibcon#[28=FRQ=06,752.99\r\n] 2006.224.08:07:32.20#ibcon#*before write, iclass 11, count 0 2006.224.08:07:32.20#ibcon#enter sib2, iclass 11, count 0 2006.224.08:07:32.20#ibcon#flushed, iclass 11, count 0 2006.224.08:07:32.20#ibcon#about to write, iclass 11, count 0 2006.224.08:07:32.20#ibcon#wrote, iclass 11, count 0 2006.224.08:07:32.20#ibcon#about to read 3, iclass 11, count 0 2006.224.08:07:32.24#ibcon#read 3, iclass 11, count 0 2006.224.08:07:32.24#ibcon#about to read 4, iclass 11, count 0 2006.224.08:07:32.24#ibcon#read 4, iclass 11, count 0 2006.224.08:07:32.24#ibcon#about to read 5, iclass 11, count 0 2006.224.08:07:32.24#ibcon#read 5, iclass 11, count 0 2006.224.08:07:32.24#ibcon#about to read 6, iclass 11, count 0 2006.224.08:07:32.24#ibcon#read 6, iclass 11, count 0 2006.224.08:07:32.24#ibcon#end of sib2, iclass 11, count 0 2006.224.08:07:32.24#ibcon#*after write, iclass 11, count 0 2006.224.08:07:32.24#ibcon#*before return 0, iclass 11, count 0 2006.224.08:07:32.24#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.224.08:07:32.24#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.224.08:07:32.24#ibcon#about to clear, iclass 11 cls_cnt 0 2006.224.08:07:32.24#ibcon#cleared, iclass 11 cls_cnt 0 2006.224.08:07:32.24$vc4f8/vb=6,4 2006.224.08:07:32.24#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.224.08:07:32.24#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.224.08:07:32.24#ibcon#ireg 11 cls_cnt 2 2006.224.08:07:32.24#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.224.08:07:32.30#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.224.08:07:32.30#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.224.08:07:32.30#ibcon#enter wrdev, iclass 13, count 2 2006.224.08:07:32.30#ibcon#first serial, iclass 13, count 2 2006.224.08:07:32.30#ibcon#enter sib2, iclass 13, count 2 2006.224.08:07:32.30#ibcon#flushed, iclass 13, count 2 2006.224.08:07:32.30#ibcon#about to write, iclass 13, count 2 2006.224.08:07:32.30#ibcon#wrote, iclass 13, count 2 2006.224.08:07:32.30#ibcon#about to read 3, iclass 13, count 2 2006.224.08:07:32.32#ibcon#read 3, iclass 13, count 2 2006.224.08:07:32.32#ibcon#about to read 4, iclass 13, count 2 2006.224.08:07:32.32#ibcon#read 4, iclass 13, count 2 2006.224.08:07:32.32#ibcon#about to read 5, iclass 13, count 2 2006.224.08:07:32.32#ibcon#read 5, iclass 13, count 2 2006.224.08:07:32.32#ibcon#about to read 6, iclass 13, count 2 2006.224.08:07:32.32#ibcon#read 6, iclass 13, count 2 2006.224.08:07:32.32#ibcon#end of sib2, iclass 13, count 2 2006.224.08:07:32.32#ibcon#*mode == 0, iclass 13, count 2 2006.224.08:07:32.32#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.224.08:07:32.32#ibcon#[27=AT06-04\r\n] 2006.224.08:07:32.32#ibcon#*before write, iclass 13, count 2 2006.224.08:07:32.32#ibcon#enter sib2, iclass 13, count 2 2006.224.08:07:32.32#ibcon#flushed, iclass 13, count 2 2006.224.08:07:32.32#ibcon#about to write, iclass 13, count 2 2006.224.08:07:32.32#ibcon#wrote, iclass 13, count 2 2006.224.08:07:32.32#ibcon#about to read 3, iclass 13, count 2 2006.224.08:07:32.35#ibcon#read 3, iclass 13, count 2 2006.224.08:07:32.35#ibcon#about to read 4, iclass 13, count 2 2006.224.08:07:32.35#ibcon#read 4, iclass 13, count 2 2006.224.08:07:32.35#ibcon#about to read 5, iclass 13, count 2 2006.224.08:07:32.35#ibcon#read 5, iclass 13, count 2 2006.224.08:07:32.35#ibcon#about to read 6, iclass 13, count 2 2006.224.08:07:32.35#ibcon#read 6, iclass 13, count 2 2006.224.08:07:32.35#ibcon#end of sib2, iclass 13, count 2 2006.224.08:07:32.35#ibcon#*after write, iclass 13, count 2 2006.224.08:07:32.35#ibcon#*before return 0, iclass 13, count 2 2006.224.08:07:32.35#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.224.08:07:32.35#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.224.08:07:32.35#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.224.08:07:32.35#ibcon#ireg 7 cls_cnt 0 2006.224.08:07:32.35#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.224.08:07:32.47#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.224.08:07:32.47#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.224.08:07:32.47#ibcon#enter wrdev, iclass 13, count 0 2006.224.08:07:32.47#ibcon#first serial, iclass 13, count 0 2006.224.08:07:32.47#ibcon#enter sib2, iclass 13, count 0 2006.224.08:07:32.47#ibcon#flushed, iclass 13, count 0 2006.224.08:07:32.47#ibcon#about to write, iclass 13, count 0 2006.224.08:07:32.47#ibcon#wrote, iclass 13, count 0 2006.224.08:07:32.47#ibcon#about to read 3, iclass 13, count 0 2006.224.08:07:32.49#ibcon#read 3, iclass 13, count 0 2006.224.08:07:32.49#ibcon#about to read 4, iclass 13, count 0 2006.224.08:07:32.49#ibcon#read 4, iclass 13, count 0 2006.224.08:07:32.49#ibcon#about to read 5, iclass 13, count 0 2006.224.08:07:32.49#ibcon#read 5, iclass 13, count 0 2006.224.08:07:32.49#ibcon#about to read 6, iclass 13, count 0 2006.224.08:07:32.49#ibcon#read 6, iclass 13, count 0 2006.224.08:07:32.49#ibcon#end of sib2, iclass 13, count 0 2006.224.08:07:32.49#ibcon#*mode == 0, iclass 13, count 0 2006.224.08:07:32.49#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.224.08:07:32.49#ibcon#[27=USB\r\n] 2006.224.08:07:32.49#ibcon#*before write, iclass 13, count 0 2006.224.08:07:32.49#ibcon#enter sib2, iclass 13, count 0 2006.224.08:07:32.49#ibcon#flushed, iclass 13, count 0 2006.224.08:07:32.49#ibcon#about to write, iclass 13, count 0 2006.224.08:07:32.49#ibcon#wrote, iclass 13, count 0 2006.224.08:07:32.49#ibcon#about to read 3, iclass 13, count 0 2006.224.08:07:32.52#ibcon#read 3, iclass 13, count 0 2006.224.08:07:32.52#ibcon#about to read 4, iclass 13, count 0 2006.224.08:07:32.52#ibcon#read 4, iclass 13, count 0 2006.224.08:07:32.52#ibcon#about to read 5, iclass 13, count 0 2006.224.08:07:32.52#ibcon#read 5, iclass 13, count 0 2006.224.08:07:32.52#ibcon#about to read 6, iclass 13, count 0 2006.224.08:07:32.52#ibcon#read 6, iclass 13, count 0 2006.224.08:07:32.52#ibcon#end of sib2, iclass 13, count 0 2006.224.08:07:32.52#ibcon#*after write, iclass 13, count 0 2006.224.08:07:32.52#ibcon#*before return 0, iclass 13, count 0 2006.224.08:07:32.52#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.224.08:07:32.52#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.224.08:07:32.52#ibcon#about to clear, iclass 13 cls_cnt 0 2006.224.08:07:32.52#ibcon#cleared, iclass 13 cls_cnt 0 2006.224.08:07:32.52$vc4f8/vabw=wide 2006.224.08:07:32.52#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.224.08:07:32.52#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.224.08:07:32.52#ibcon#ireg 8 cls_cnt 0 2006.224.08:07:32.52#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.224.08:07:32.52#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.224.08:07:32.52#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.224.08:07:32.52#ibcon#enter wrdev, iclass 15, count 0 2006.224.08:07:32.52#ibcon#first serial, iclass 15, count 0 2006.224.08:07:32.52#ibcon#enter sib2, iclass 15, count 0 2006.224.08:07:32.52#ibcon#flushed, iclass 15, count 0 2006.224.08:07:32.52#ibcon#about to write, iclass 15, count 0 2006.224.08:07:32.52#ibcon#wrote, iclass 15, count 0 2006.224.08:07:32.52#ibcon#about to read 3, iclass 15, count 0 2006.224.08:07:32.54#ibcon#read 3, iclass 15, count 0 2006.224.08:07:32.54#ibcon#about to read 4, iclass 15, count 0 2006.224.08:07:32.54#ibcon#read 4, iclass 15, count 0 2006.224.08:07:32.54#ibcon#about to read 5, iclass 15, count 0 2006.224.08:07:32.54#ibcon#read 5, iclass 15, count 0 2006.224.08:07:32.54#ibcon#about to read 6, iclass 15, count 0 2006.224.08:07:32.54#ibcon#read 6, iclass 15, count 0 2006.224.08:07:32.54#ibcon#end of sib2, iclass 15, count 0 2006.224.08:07:32.54#ibcon#*mode == 0, iclass 15, count 0 2006.224.08:07:32.54#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.224.08:07:32.54#ibcon#[25=BW32\r\n] 2006.224.08:07:32.54#ibcon#*before write, iclass 15, count 0 2006.224.08:07:32.54#ibcon#enter sib2, iclass 15, count 0 2006.224.08:07:32.54#ibcon#flushed, iclass 15, count 0 2006.224.08:07:32.54#ibcon#about to write, iclass 15, count 0 2006.224.08:07:32.54#ibcon#wrote, iclass 15, count 0 2006.224.08:07:32.54#ibcon#about to read 3, iclass 15, count 0 2006.224.08:07:32.57#ibcon#read 3, iclass 15, count 0 2006.224.08:07:32.57#ibcon#about to read 4, iclass 15, count 0 2006.224.08:07:32.57#ibcon#read 4, iclass 15, count 0 2006.224.08:07:32.57#ibcon#about to read 5, iclass 15, count 0 2006.224.08:07:32.57#ibcon#read 5, iclass 15, count 0 2006.224.08:07:32.57#ibcon#about to read 6, iclass 15, count 0 2006.224.08:07:32.57#ibcon#read 6, iclass 15, count 0 2006.224.08:07:32.57#ibcon#end of sib2, iclass 15, count 0 2006.224.08:07:32.57#ibcon#*after write, iclass 15, count 0 2006.224.08:07:32.57#ibcon#*before return 0, iclass 15, count 0 2006.224.08:07:32.57#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.224.08:07:32.57#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.224.08:07:32.57#ibcon#about to clear, iclass 15 cls_cnt 0 2006.224.08:07:32.57#ibcon#cleared, iclass 15 cls_cnt 0 2006.224.08:07:32.57$vc4f8/vbbw=wide 2006.224.08:07:32.57#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.224.08:07:32.57#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.224.08:07:32.57#ibcon#ireg 8 cls_cnt 0 2006.224.08:07:32.57#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.224.08:07:32.64#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.224.08:07:32.64#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.224.08:07:32.64#ibcon#enter wrdev, iclass 17, count 0 2006.224.08:07:32.64#ibcon#first serial, iclass 17, count 0 2006.224.08:07:32.64#ibcon#enter sib2, iclass 17, count 0 2006.224.08:07:32.64#ibcon#flushed, iclass 17, count 0 2006.224.08:07:32.64#ibcon#about to write, iclass 17, count 0 2006.224.08:07:32.64#ibcon#wrote, iclass 17, count 0 2006.224.08:07:32.64#ibcon#about to read 3, iclass 17, count 0 2006.224.08:07:32.66#ibcon#read 3, iclass 17, count 0 2006.224.08:07:32.66#ibcon#about to read 4, iclass 17, count 0 2006.224.08:07:32.66#ibcon#read 4, iclass 17, count 0 2006.224.08:07:32.66#ibcon#about to read 5, iclass 17, count 0 2006.224.08:07:32.66#ibcon#read 5, iclass 17, count 0 2006.224.08:07:32.66#ibcon#about to read 6, iclass 17, count 0 2006.224.08:07:32.66#ibcon#read 6, iclass 17, count 0 2006.224.08:07:32.66#ibcon#end of sib2, iclass 17, count 0 2006.224.08:07:32.66#ibcon#*mode == 0, iclass 17, count 0 2006.224.08:07:32.66#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.224.08:07:32.66#ibcon#[27=BW32\r\n] 2006.224.08:07:32.66#ibcon#*before write, iclass 17, count 0 2006.224.08:07:32.66#ibcon#enter sib2, iclass 17, count 0 2006.224.08:07:32.66#ibcon#flushed, iclass 17, count 0 2006.224.08:07:32.66#ibcon#about to write, iclass 17, count 0 2006.224.08:07:32.66#ibcon#wrote, iclass 17, count 0 2006.224.08:07:32.66#ibcon#about to read 3, iclass 17, count 0 2006.224.08:07:32.69#ibcon#read 3, iclass 17, count 0 2006.224.08:07:32.69#ibcon#about to read 4, iclass 17, count 0 2006.224.08:07:32.69#ibcon#read 4, iclass 17, count 0 2006.224.08:07:32.69#ibcon#about to read 5, iclass 17, count 0 2006.224.08:07:32.69#ibcon#read 5, iclass 17, count 0 2006.224.08:07:32.69#ibcon#about to read 6, iclass 17, count 0 2006.224.08:07:32.69#ibcon#read 6, iclass 17, count 0 2006.224.08:07:32.69#ibcon#end of sib2, iclass 17, count 0 2006.224.08:07:32.69#ibcon#*after write, iclass 17, count 0 2006.224.08:07:32.69#ibcon#*before return 0, iclass 17, count 0 2006.224.08:07:32.69#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.224.08:07:32.69#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.224.08:07:32.69#ibcon#about to clear, iclass 17 cls_cnt 0 2006.224.08:07:32.69#ibcon#cleared, iclass 17 cls_cnt 0 2006.224.08:07:32.69$4f8m12a/ifd4f 2006.224.08:07:32.69$ifd4f/lo= 2006.224.08:07:32.69$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.224.08:07:32.69$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.224.08:07:32.69$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.224.08:07:32.69$ifd4f/patch= 2006.224.08:07:32.69$ifd4f/patch=lo1,a1,a2,a3,a4 2006.224.08:07:32.69$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.224.08:07:32.69$ifd4f/patch=lo3,a5,a6,a7,a8 2006.224.08:07:32.69$4f8m12a/"form=m,16.000,1:2 2006.224.08:07:32.69$4f8m12a/"tpicd 2006.224.08:07:32.69$4f8m12a/echo=off 2006.224.08:07:32.69$4f8m12a/xlog=off 2006.224.08:07:32.69:!2006.224.08:08:00 2006.224.08:07:42.14#trakl#Source acquired 2006.224.08:07:42.14#flagr#flagr/antenna,acquired 2006.224.08:08:00.00:preob 2006.224.08:08:01.14/onsource/TRACKING 2006.224.08:08:01.14:!2006.224.08:08:10 2006.224.08:08:10.00:data_valid=on 2006.224.08:08:10.00:midob 2006.224.08:08:10.14/onsource/TRACKING 2006.224.08:08:10.14/wx/23.67,1004.7,100 2006.224.08:08:10.33/cable/+6.4332E-03 2006.224.08:08:11.42/va/01,08,usb,yes,43,45 2006.224.08:08:11.42/va/02,07,usb,yes,43,45 2006.224.08:08:11.42/va/03,06,usb,yes,46,46 2006.224.08:08:11.42/va/04,07,usb,yes,45,48 2006.224.08:08:11.42/va/05,07,usb,yes,53,56 2006.224.08:08:11.42/va/06,06,usb,yes,52,52 2006.224.08:08:11.42/va/07,06,usb,yes,53,53 2006.224.08:08:11.42/va/08,07,usb,yes,50,50 2006.224.08:08:11.65/valo/01,532.99,yes,locked 2006.224.08:08:11.65/valo/02,572.99,yes,locked 2006.224.08:08:11.65/valo/03,672.99,yes,locked 2006.224.08:08:11.65/valo/04,832.99,yes,locked 2006.224.08:08:11.65/valo/05,652.99,yes,locked 2006.224.08:08:11.65/valo/06,772.99,yes,locked 2006.224.08:08:11.65/valo/07,832.99,yes,locked 2006.224.08:08:11.65/valo/08,852.99,yes,locked 2006.224.08:08:12.74/vb/01,04,usb,yes,33,31 2006.224.08:08:12.74/vb/02,04,usb,yes,35,36 2006.224.08:08:12.74/vb/03,04,usb,yes,31,35 2006.224.08:08:12.74/vb/04,04,usb,yes,32,32 2006.224.08:08:12.74/vb/05,04,usb,yes,30,34 2006.224.08:08:12.74/vb/06,04,usb,yes,31,34 2006.224.08:08:12.74/vb/07,04,usb,yes,33,33 2006.224.08:08:12.74/vb/08,04,usb,yes,31,34 2006.224.08:08:12.97/vblo/01,632.99,yes,locked 2006.224.08:08:12.97/vblo/02,640.99,yes,locked 2006.224.08:08:12.97/vblo/03,656.99,yes,locked 2006.224.08:08:12.97/vblo/04,712.99,yes,locked 2006.224.08:08:12.97/vblo/05,744.99,yes,locked 2006.224.08:08:12.97/vblo/06,752.99,yes,locked 2006.224.08:08:12.97/vblo/07,734.99,yes,locked 2006.224.08:08:12.97/vblo/08,744.99,yes,locked 2006.224.08:08:13.12/vabw/8 2006.224.08:08:13.27/vbbw/8 2006.224.08:08:13.36/xfe/off,on,15.2 2006.224.08:08:13.74/ifatt/23,28,28,28 2006.224.08:08:14.07/fmout-gps/S +4.52E-07 2006.224.08:08:14.11:!2006.224.08:09:10 2006.224.08:09:10.01:data_valid=off 2006.224.08:09:10.01:postob 2006.224.08:09:10.23/cable/+6.4339E-03 2006.224.08:09:10.23/wx/23.70,1004.7,100 2006.224.08:09:11.07/fmout-gps/S +4.55E-07 2006.224.08:09:11.07:scan_name=224-0810,k06224,60 2006.224.08:09:11.07:source=1739+522,174036.98,521143.4,2000.0,cw 2006.224.08:09:11.14#flagr#flagr/antenna,new-source 2006.224.08:09:12.14:checkk5 2006.224.08:09:12.51/chk_autoobs//k5ts1/ autoobs is running! 2006.224.08:09:12.88/chk_autoobs//k5ts2/ autoobs is running! 2006.224.08:09:13.25/chk_autoobs//k5ts3/ autoobs is running! 2006.224.08:09:13.62/chk_autoobs//k5ts4/ autoobs is running! 2006.224.08:09:13.99/chk_obsdata//k5ts1/T2240808??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.08:09:14.35/chk_obsdata//k5ts2/T2240808??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.08:09:14.72/chk_obsdata//k5ts3/T2240808??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.08:09:15.08/chk_obsdata//k5ts4/T2240808??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.08:09:15.77/k5log//k5ts1_log_newline 2006.224.08:09:16.46/k5log//k5ts2_log_newline 2006.224.08:09:17.14/k5log//k5ts3_log_newline 2006.224.08:09:17.82/k5log//k5ts4_log_newline 2006.224.08:09:17.84/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.224.08:09:17.84:4f8m12a=2 2006.224.08:09:17.84$4f8m12a/echo=on 2006.224.08:09:17.84$4f8m12a/pcalon 2006.224.08:09:17.84$pcalon/"no phase cal control is implemented here 2006.224.08:09:17.84$4f8m12a/"tpicd=stop 2006.224.08:09:17.84$4f8m12a/vc4f8 2006.224.08:09:17.84$vc4f8/valo=1,532.99 2006.224.08:09:17.85#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.224.08:09:17.85#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.224.08:09:17.85#ibcon#ireg 17 cls_cnt 0 2006.224.08:09:17.85#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.224.08:09:17.85#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.224.08:09:17.85#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.224.08:09:17.85#ibcon#enter wrdev, iclass 24, count 0 2006.224.08:09:17.85#ibcon#first serial, iclass 24, count 0 2006.224.08:09:17.85#ibcon#enter sib2, iclass 24, count 0 2006.224.08:09:17.85#ibcon#flushed, iclass 24, count 0 2006.224.08:09:17.85#ibcon#about to write, iclass 24, count 0 2006.224.08:09:17.85#ibcon#wrote, iclass 24, count 0 2006.224.08:09:17.85#ibcon#about to read 3, iclass 24, count 0 2006.224.08:09:17.89#ibcon#read 3, iclass 24, count 0 2006.224.08:09:17.89#ibcon#about to read 4, iclass 24, count 0 2006.224.08:09:17.89#ibcon#read 4, iclass 24, count 0 2006.224.08:09:17.89#ibcon#about to read 5, iclass 24, count 0 2006.224.08:09:17.89#ibcon#read 5, iclass 24, count 0 2006.224.08:09:17.89#ibcon#about to read 6, iclass 24, count 0 2006.224.08:09:17.89#ibcon#read 6, iclass 24, count 0 2006.224.08:09:17.89#ibcon#end of sib2, iclass 24, count 0 2006.224.08:09:17.89#ibcon#*mode == 0, iclass 24, count 0 2006.224.08:09:17.89#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.224.08:09:17.89#ibcon#[26=FRQ=01,532.99\r\n] 2006.224.08:09:17.89#ibcon#*before write, iclass 24, count 0 2006.224.08:09:17.89#ibcon#enter sib2, iclass 24, count 0 2006.224.08:09:17.89#ibcon#flushed, iclass 24, count 0 2006.224.08:09:17.89#ibcon#about to write, iclass 24, count 0 2006.224.08:09:17.89#ibcon#wrote, iclass 24, count 0 2006.224.08:09:17.89#ibcon#about to read 3, iclass 24, count 0 2006.224.08:09:17.94#ibcon#read 3, iclass 24, count 0 2006.224.08:09:17.94#ibcon#about to read 4, iclass 24, count 0 2006.224.08:09:17.94#ibcon#read 4, iclass 24, count 0 2006.224.08:09:17.94#ibcon#about to read 5, iclass 24, count 0 2006.224.08:09:17.94#ibcon#read 5, iclass 24, count 0 2006.224.08:09:17.94#ibcon#about to read 6, iclass 24, count 0 2006.224.08:09:17.94#ibcon#read 6, iclass 24, count 0 2006.224.08:09:17.94#ibcon#end of sib2, iclass 24, count 0 2006.224.08:09:17.94#ibcon#*after write, iclass 24, count 0 2006.224.08:09:17.94#ibcon#*before return 0, iclass 24, count 0 2006.224.08:09:17.94#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.224.08:09:17.94#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.224.08:09:17.94#ibcon#about to clear, iclass 24 cls_cnt 0 2006.224.08:09:17.94#ibcon#cleared, iclass 24 cls_cnt 0 2006.224.08:09:17.94$vc4f8/va=1,8 2006.224.08:09:17.94#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.224.08:09:17.94#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.224.08:09:17.94#ibcon#ireg 11 cls_cnt 2 2006.224.08:09:17.94#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.224.08:09:17.94#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.224.08:09:17.94#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.224.08:09:17.94#ibcon#enter wrdev, iclass 26, count 2 2006.224.08:09:17.94#ibcon#first serial, iclass 26, count 2 2006.224.08:09:17.94#ibcon#enter sib2, iclass 26, count 2 2006.224.08:09:17.94#ibcon#flushed, iclass 26, count 2 2006.224.08:09:17.94#ibcon#about to write, iclass 26, count 2 2006.224.08:09:17.94#ibcon#wrote, iclass 26, count 2 2006.224.08:09:17.94#ibcon#about to read 3, iclass 26, count 2 2006.224.08:09:17.96#ibcon#read 3, iclass 26, count 2 2006.224.08:09:17.96#ibcon#about to read 4, iclass 26, count 2 2006.224.08:09:17.96#ibcon#read 4, iclass 26, count 2 2006.224.08:09:17.96#ibcon#about to read 5, iclass 26, count 2 2006.224.08:09:17.96#ibcon#read 5, iclass 26, count 2 2006.224.08:09:17.96#ibcon#about to read 6, iclass 26, count 2 2006.224.08:09:17.96#ibcon#read 6, iclass 26, count 2 2006.224.08:09:17.96#ibcon#end of sib2, iclass 26, count 2 2006.224.08:09:17.96#ibcon#*mode == 0, iclass 26, count 2 2006.224.08:09:17.96#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.224.08:09:17.96#ibcon#[25=AT01-08\r\n] 2006.224.08:09:17.96#ibcon#*before write, iclass 26, count 2 2006.224.08:09:17.96#ibcon#enter sib2, iclass 26, count 2 2006.224.08:09:17.96#ibcon#flushed, iclass 26, count 2 2006.224.08:09:17.96#ibcon#about to write, iclass 26, count 2 2006.224.08:09:17.96#ibcon#wrote, iclass 26, count 2 2006.224.08:09:17.96#ibcon#about to read 3, iclass 26, count 2 2006.224.08:09:18.00#ibcon#read 3, iclass 26, count 2 2006.224.08:09:18.00#ibcon#about to read 4, iclass 26, count 2 2006.224.08:09:18.00#ibcon#read 4, iclass 26, count 2 2006.224.08:09:18.00#ibcon#about to read 5, iclass 26, count 2 2006.224.08:09:18.00#ibcon#read 5, iclass 26, count 2 2006.224.08:09:18.00#ibcon#about to read 6, iclass 26, count 2 2006.224.08:09:18.00#ibcon#read 6, iclass 26, count 2 2006.224.08:09:18.00#ibcon#end of sib2, iclass 26, count 2 2006.224.08:09:18.00#ibcon#*after write, iclass 26, count 2 2006.224.08:09:18.00#ibcon#*before return 0, iclass 26, count 2 2006.224.08:09:18.00#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.224.08:09:18.00#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.224.08:09:18.00#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.224.08:09:18.00#ibcon#ireg 7 cls_cnt 0 2006.224.08:09:18.00#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.224.08:09:18.12#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.224.08:09:18.12#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.224.08:09:18.12#ibcon#enter wrdev, iclass 26, count 0 2006.224.08:09:18.12#ibcon#first serial, iclass 26, count 0 2006.224.08:09:18.12#ibcon#enter sib2, iclass 26, count 0 2006.224.08:09:18.12#ibcon#flushed, iclass 26, count 0 2006.224.08:09:18.12#ibcon#about to write, iclass 26, count 0 2006.224.08:09:18.12#ibcon#wrote, iclass 26, count 0 2006.224.08:09:18.12#ibcon#about to read 3, iclass 26, count 0 2006.224.08:09:18.14#ibcon#read 3, iclass 26, count 0 2006.224.08:09:18.14#ibcon#about to read 4, iclass 26, count 0 2006.224.08:09:18.14#ibcon#read 4, iclass 26, count 0 2006.224.08:09:18.14#ibcon#about to read 5, iclass 26, count 0 2006.224.08:09:18.14#ibcon#read 5, iclass 26, count 0 2006.224.08:09:18.14#ibcon#about to read 6, iclass 26, count 0 2006.224.08:09:18.14#ibcon#read 6, iclass 26, count 0 2006.224.08:09:18.14#ibcon#end of sib2, iclass 26, count 0 2006.224.08:09:18.14#ibcon#*mode == 0, iclass 26, count 0 2006.224.08:09:18.14#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.224.08:09:18.14#ibcon#[25=USB\r\n] 2006.224.08:09:18.14#ibcon#*before write, iclass 26, count 0 2006.224.08:09:18.14#ibcon#enter sib2, iclass 26, count 0 2006.224.08:09:18.14#ibcon#flushed, iclass 26, count 0 2006.224.08:09:18.14#ibcon#about to write, iclass 26, count 0 2006.224.08:09:18.14#ibcon#wrote, iclass 26, count 0 2006.224.08:09:18.14#ibcon#about to read 3, iclass 26, count 0 2006.224.08:09:18.17#ibcon#read 3, iclass 26, count 0 2006.224.08:09:18.17#ibcon#about to read 4, iclass 26, count 0 2006.224.08:09:18.17#ibcon#read 4, iclass 26, count 0 2006.224.08:09:18.17#ibcon#about to read 5, iclass 26, count 0 2006.224.08:09:18.17#ibcon#read 5, iclass 26, count 0 2006.224.08:09:18.17#ibcon#about to read 6, iclass 26, count 0 2006.224.08:09:18.17#ibcon#read 6, iclass 26, count 0 2006.224.08:09:18.17#ibcon#end of sib2, iclass 26, count 0 2006.224.08:09:18.17#ibcon#*after write, iclass 26, count 0 2006.224.08:09:18.17#ibcon#*before return 0, iclass 26, count 0 2006.224.08:09:18.17#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.224.08:09:18.17#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.224.08:09:18.17#ibcon#about to clear, iclass 26 cls_cnt 0 2006.224.08:09:18.17#ibcon#cleared, iclass 26 cls_cnt 0 2006.224.08:09:18.17$vc4f8/valo=2,572.99 2006.224.08:09:18.17#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.224.08:09:18.17#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.224.08:09:18.17#ibcon#ireg 17 cls_cnt 0 2006.224.08:09:18.17#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.224.08:09:18.17#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.224.08:09:18.17#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.224.08:09:18.17#ibcon#enter wrdev, iclass 28, count 0 2006.224.08:09:18.17#ibcon#first serial, iclass 28, count 0 2006.224.08:09:18.17#ibcon#enter sib2, iclass 28, count 0 2006.224.08:09:18.17#ibcon#flushed, iclass 28, count 0 2006.224.08:09:18.17#ibcon#about to write, iclass 28, count 0 2006.224.08:09:18.17#ibcon#wrote, iclass 28, count 0 2006.224.08:09:18.17#ibcon#about to read 3, iclass 28, count 0 2006.224.08:09:18.19#ibcon#read 3, iclass 28, count 0 2006.224.08:09:18.19#ibcon#about to read 4, iclass 28, count 0 2006.224.08:09:18.19#ibcon#read 4, iclass 28, count 0 2006.224.08:09:18.19#ibcon#about to read 5, iclass 28, count 0 2006.224.08:09:18.19#ibcon#read 5, iclass 28, count 0 2006.224.08:09:18.19#ibcon#about to read 6, iclass 28, count 0 2006.224.08:09:18.19#ibcon#read 6, iclass 28, count 0 2006.224.08:09:18.19#ibcon#end of sib2, iclass 28, count 0 2006.224.08:09:18.19#ibcon#*mode == 0, iclass 28, count 0 2006.224.08:09:18.19#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.224.08:09:18.19#ibcon#[26=FRQ=02,572.99\r\n] 2006.224.08:09:18.19#ibcon#*before write, iclass 28, count 0 2006.224.08:09:18.19#ibcon#enter sib2, iclass 28, count 0 2006.224.08:09:18.19#ibcon#flushed, iclass 28, count 0 2006.224.08:09:18.19#ibcon#about to write, iclass 28, count 0 2006.224.08:09:18.19#ibcon#wrote, iclass 28, count 0 2006.224.08:09:18.19#ibcon#about to read 3, iclass 28, count 0 2006.224.08:09:18.24#ibcon#read 3, iclass 28, count 0 2006.224.08:09:18.24#ibcon#about to read 4, iclass 28, count 0 2006.224.08:09:18.24#ibcon#read 4, iclass 28, count 0 2006.224.08:09:18.24#ibcon#about to read 5, iclass 28, count 0 2006.224.08:09:18.24#ibcon#read 5, iclass 28, count 0 2006.224.08:09:18.24#ibcon#about to read 6, iclass 28, count 0 2006.224.08:09:18.24#ibcon#read 6, iclass 28, count 0 2006.224.08:09:18.24#ibcon#end of sib2, iclass 28, count 0 2006.224.08:09:18.24#ibcon#*after write, iclass 28, count 0 2006.224.08:09:18.24#ibcon#*before return 0, iclass 28, count 0 2006.224.08:09:18.24#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.224.08:09:18.24#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.224.08:09:18.24#ibcon#about to clear, iclass 28 cls_cnt 0 2006.224.08:09:18.24#ibcon#cleared, iclass 28 cls_cnt 0 2006.224.08:09:18.24$vc4f8/va=2,7 2006.224.08:09:18.24#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.224.08:09:18.24#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.224.08:09:18.24#ibcon#ireg 11 cls_cnt 2 2006.224.08:09:18.24#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.224.08:09:18.29#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.224.08:09:18.29#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.224.08:09:18.29#ibcon#enter wrdev, iclass 30, count 2 2006.224.08:09:18.29#ibcon#first serial, iclass 30, count 2 2006.224.08:09:18.29#ibcon#enter sib2, iclass 30, count 2 2006.224.08:09:18.29#ibcon#flushed, iclass 30, count 2 2006.224.08:09:18.29#ibcon#about to write, iclass 30, count 2 2006.224.08:09:18.29#ibcon#wrote, iclass 30, count 2 2006.224.08:09:18.29#ibcon#about to read 3, iclass 30, count 2 2006.224.08:09:18.31#ibcon#read 3, iclass 30, count 2 2006.224.08:09:18.31#ibcon#about to read 4, iclass 30, count 2 2006.224.08:09:18.31#ibcon#read 4, iclass 30, count 2 2006.224.08:09:18.31#ibcon#about to read 5, iclass 30, count 2 2006.224.08:09:18.31#ibcon#read 5, iclass 30, count 2 2006.224.08:09:18.31#ibcon#about to read 6, iclass 30, count 2 2006.224.08:09:18.31#ibcon#read 6, iclass 30, count 2 2006.224.08:09:18.31#ibcon#end of sib2, iclass 30, count 2 2006.224.08:09:18.31#ibcon#*mode == 0, iclass 30, count 2 2006.224.08:09:18.31#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.224.08:09:18.31#ibcon#[25=AT02-07\r\n] 2006.224.08:09:18.31#ibcon#*before write, iclass 30, count 2 2006.224.08:09:18.31#ibcon#enter sib2, iclass 30, count 2 2006.224.08:09:18.31#ibcon#flushed, iclass 30, count 2 2006.224.08:09:18.31#ibcon#about to write, iclass 30, count 2 2006.224.08:09:18.31#ibcon#wrote, iclass 30, count 2 2006.224.08:09:18.31#ibcon#about to read 3, iclass 30, count 2 2006.224.08:09:18.34#ibcon#read 3, iclass 30, count 2 2006.224.08:09:18.34#ibcon#about to read 4, iclass 30, count 2 2006.224.08:09:18.34#ibcon#read 4, iclass 30, count 2 2006.224.08:09:18.34#ibcon#about to read 5, iclass 30, count 2 2006.224.08:09:18.34#ibcon#read 5, iclass 30, count 2 2006.224.08:09:18.34#ibcon#about to read 6, iclass 30, count 2 2006.224.08:09:18.34#ibcon#read 6, iclass 30, count 2 2006.224.08:09:18.34#ibcon#end of sib2, iclass 30, count 2 2006.224.08:09:18.34#ibcon#*after write, iclass 30, count 2 2006.224.08:09:18.34#ibcon#*before return 0, iclass 30, count 2 2006.224.08:09:18.34#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.224.08:09:18.34#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.224.08:09:18.34#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.224.08:09:18.34#ibcon#ireg 7 cls_cnt 0 2006.224.08:09:18.34#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.224.08:09:18.46#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.224.08:09:18.46#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.224.08:09:18.46#ibcon#enter wrdev, iclass 30, count 0 2006.224.08:09:18.46#ibcon#first serial, iclass 30, count 0 2006.224.08:09:18.46#ibcon#enter sib2, iclass 30, count 0 2006.224.08:09:18.46#ibcon#flushed, iclass 30, count 0 2006.224.08:09:18.46#ibcon#about to write, iclass 30, count 0 2006.224.08:09:18.46#ibcon#wrote, iclass 30, count 0 2006.224.08:09:18.46#ibcon#about to read 3, iclass 30, count 0 2006.224.08:09:18.48#ibcon#read 3, iclass 30, count 0 2006.224.08:09:18.48#ibcon#about to read 4, iclass 30, count 0 2006.224.08:09:18.48#ibcon#read 4, iclass 30, count 0 2006.224.08:09:18.48#ibcon#about to read 5, iclass 30, count 0 2006.224.08:09:18.48#ibcon#read 5, iclass 30, count 0 2006.224.08:09:18.48#ibcon#about to read 6, iclass 30, count 0 2006.224.08:09:18.48#ibcon#read 6, iclass 30, count 0 2006.224.08:09:18.48#ibcon#end of sib2, iclass 30, count 0 2006.224.08:09:18.48#ibcon#*mode == 0, iclass 30, count 0 2006.224.08:09:18.48#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.224.08:09:18.48#ibcon#[25=USB\r\n] 2006.224.08:09:18.48#ibcon#*before write, iclass 30, count 0 2006.224.08:09:18.48#ibcon#enter sib2, iclass 30, count 0 2006.224.08:09:18.48#ibcon#flushed, iclass 30, count 0 2006.224.08:09:18.48#ibcon#about to write, iclass 30, count 0 2006.224.08:09:18.48#ibcon#wrote, iclass 30, count 0 2006.224.08:09:18.48#ibcon#about to read 3, iclass 30, count 0 2006.224.08:09:18.51#ibcon#read 3, iclass 30, count 0 2006.224.08:09:18.51#ibcon#about to read 4, iclass 30, count 0 2006.224.08:09:18.51#ibcon#read 4, iclass 30, count 0 2006.224.08:09:18.51#ibcon#about to read 5, iclass 30, count 0 2006.224.08:09:18.51#ibcon#read 5, iclass 30, count 0 2006.224.08:09:18.51#ibcon#about to read 6, iclass 30, count 0 2006.224.08:09:18.51#ibcon#read 6, iclass 30, count 0 2006.224.08:09:18.51#ibcon#end of sib2, iclass 30, count 0 2006.224.08:09:18.51#ibcon#*after write, iclass 30, count 0 2006.224.08:09:18.51#ibcon#*before return 0, iclass 30, count 0 2006.224.08:09:18.51#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.224.08:09:18.51#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.224.08:09:18.51#ibcon#about to clear, iclass 30 cls_cnt 0 2006.224.08:09:18.51#ibcon#cleared, iclass 30 cls_cnt 0 2006.224.08:09:18.51$vc4f8/valo=3,672.99 2006.224.08:09:18.51#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.224.08:09:18.51#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.224.08:09:18.51#ibcon#ireg 17 cls_cnt 0 2006.224.08:09:18.51#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.224.08:09:18.51#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.224.08:09:18.51#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.224.08:09:18.51#ibcon#enter wrdev, iclass 32, count 0 2006.224.08:09:18.51#ibcon#first serial, iclass 32, count 0 2006.224.08:09:18.51#ibcon#enter sib2, iclass 32, count 0 2006.224.08:09:18.51#ibcon#flushed, iclass 32, count 0 2006.224.08:09:18.51#ibcon#about to write, iclass 32, count 0 2006.224.08:09:18.51#ibcon#wrote, iclass 32, count 0 2006.224.08:09:18.51#ibcon#about to read 3, iclass 32, count 0 2006.224.08:09:18.53#ibcon#read 3, iclass 32, count 0 2006.224.08:09:18.53#ibcon#about to read 4, iclass 32, count 0 2006.224.08:09:18.53#ibcon#read 4, iclass 32, count 0 2006.224.08:09:18.53#ibcon#about to read 5, iclass 32, count 0 2006.224.08:09:18.53#ibcon#read 5, iclass 32, count 0 2006.224.08:09:18.53#ibcon#about to read 6, iclass 32, count 0 2006.224.08:09:18.53#ibcon#read 6, iclass 32, count 0 2006.224.08:09:18.53#ibcon#end of sib2, iclass 32, count 0 2006.224.08:09:18.53#ibcon#*mode == 0, iclass 32, count 0 2006.224.08:09:18.53#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.224.08:09:18.53#ibcon#[26=FRQ=03,672.99\r\n] 2006.224.08:09:18.53#ibcon#*before write, iclass 32, count 0 2006.224.08:09:18.53#ibcon#enter sib2, iclass 32, count 0 2006.224.08:09:18.53#ibcon#flushed, iclass 32, count 0 2006.224.08:09:18.53#ibcon#about to write, iclass 32, count 0 2006.224.08:09:18.53#ibcon#wrote, iclass 32, count 0 2006.224.08:09:18.53#ibcon#about to read 3, iclass 32, count 0 2006.224.08:09:18.58#ibcon#read 3, iclass 32, count 0 2006.224.08:09:18.58#ibcon#about to read 4, iclass 32, count 0 2006.224.08:09:18.58#ibcon#read 4, iclass 32, count 0 2006.224.08:09:18.58#ibcon#about to read 5, iclass 32, count 0 2006.224.08:09:18.58#ibcon#read 5, iclass 32, count 0 2006.224.08:09:18.58#ibcon#about to read 6, iclass 32, count 0 2006.224.08:09:18.58#ibcon#read 6, iclass 32, count 0 2006.224.08:09:18.58#ibcon#end of sib2, iclass 32, count 0 2006.224.08:09:18.58#ibcon#*after write, iclass 32, count 0 2006.224.08:09:18.58#ibcon#*before return 0, iclass 32, count 0 2006.224.08:09:18.58#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.224.08:09:18.58#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.224.08:09:18.58#ibcon#about to clear, iclass 32 cls_cnt 0 2006.224.08:09:18.58#ibcon#cleared, iclass 32 cls_cnt 0 2006.224.08:09:18.58$vc4f8/va=3,6 2006.224.08:09:18.58#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.224.08:09:18.58#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.224.08:09:18.58#ibcon#ireg 11 cls_cnt 2 2006.224.08:09:18.58#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.224.08:09:18.63#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.224.08:09:18.63#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.224.08:09:18.63#ibcon#enter wrdev, iclass 34, count 2 2006.224.08:09:18.63#ibcon#first serial, iclass 34, count 2 2006.224.08:09:18.63#ibcon#enter sib2, iclass 34, count 2 2006.224.08:09:18.63#ibcon#flushed, iclass 34, count 2 2006.224.08:09:18.63#ibcon#about to write, iclass 34, count 2 2006.224.08:09:18.63#ibcon#wrote, iclass 34, count 2 2006.224.08:09:18.63#ibcon#about to read 3, iclass 34, count 2 2006.224.08:09:18.65#ibcon#read 3, iclass 34, count 2 2006.224.08:09:18.65#ibcon#about to read 4, iclass 34, count 2 2006.224.08:09:18.65#ibcon#read 4, iclass 34, count 2 2006.224.08:09:18.65#ibcon#about to read 5, iclass 34, count 2 2006.224.08:09:18.65#ibcon#read 5, iclass 34, count 2 2006.224.08:09:18.65#ibcon#about to read 6, iclass 34, count 2 2006.224.08:09:18.65#ibcon#read 6, iclass 34, count 2 2006.224.08:09:18.65#ibcon#end of sib2, iclass 34, count 2 2006.224.08:09:18.65#ibcon#*mode == 0, iclass 34, count 2 2006.224.08:09:18.65#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.224.08:09:18.65#ibcon#[25=AT03-06\r\n] 2006.224.08:09:18.65#ibcon#*before write, iclass 34, count 2 2006.224.08:09:18.65#ibcon#enter sib2, iclass 34, count 2 2006.224.08:09:18.65#ibcon#flushed, iclass 34, count 2 2006.224.08:09:18.65#ibcon#about to write, iclass 34, count 2 2006.224.08:09:18.65#ibcon#wrote, iclass 34, count 2 2006.224.08:09:18.65#ibcon#about to read 3, iclass 34, count 2 2006.224.08:09:18.68#ibcon#read 3, iclass 34, count 2 2006.224.08:09:18.68#ibcon#about to read 4, iclass 34, count 2 2006.224.08:09:18.68#ibcon#read 4, iclass 34, count 2 2006.224.08:09:18.68#ibcon#about to read 5, iclass 34, count 2 2006.224.08:09:18.68#ibcon#read 5, iclass 34, count 2 2006.224.08:09:18.68#ibcon#about to read 6, iclass 34, count 2 2006.224.08:09:18.68#ibcon#read 6, iclass 34, count 2 2006.224.08:09:18.68#ibcon#end of sib2, iclass 34, count 2 2006.224.08:09:18.68#ibcon#*after write, iclass 34, count 2 2006.224.08:09:18.68#ibcon#*before return 0, iclass 34, count 2 2006.224.08:09:18.68#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.224.08:09:18.68#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.224.08:09:18.68#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.224.08:09:18.68#ibcon#ireg 7 cls_cnt 0 2006.224.08:09:18.68#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.224.08:09:18.80#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.224.08:09:18.80#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.224.08:09:18.80#ibcon#enter wrdev, iclass 34, count 0 2006.224.08:09:18.80#ibcon#first serial, iclass 34, count 0 2006.224.08:09:18.80#ibcon#enter sib2, iclass 34, count 0 2006.224.08:09:18.80#ibcon#flushed, iclass 34, count 0 2006.224.08:09:18.80#ibcon#about to write, iclass 34, count 0 2006.224.08:09:18.80#ibcon#wrote, iclass 34, count 0 2006.224.08:09:18.80#ibcon#about to read 3, iclass 34, count 0 2006.224.08:09:18.82#ibcon#read 3, iclass 34, count 0 2006.224.08:09:18.82#ibcon#about to read 4, iclass 34, count 0 2006.224.08:09:18.82#ibcon#read 4, iclass 34, count 0 2006.224.08:09:18.82#ibcon#about to read 5, iclass 34, count 0 2006.224.08:09:18.82#ibcon#read 5, iclass 34, count 0 2006.224.08:09:18.82#ibcon#about to read 6, iclass 34, count 0 2006.224.08:09:18.82#ibcon#read 6, iclass 34, count 0 2006.224.08:09:18.82#ibcon#end of sib2, iclass 34, count 0 2006.224.08:09:18.82#ibcon#*mode == 0, iclass 34, count 0 2006.224.08:09:18.82#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.224.08:09:18.82#ibcon#[25=USB\r\n] 2006.224.08:09:18.82#ibcon#*before write, iclass 34, count 0 2006.224.08:09:18.82#ibcon#enter sib2, iclass 34, count 0 2006.224.08:09:18.82#ibcon#flushed, iclass 34, count 0 2006.224.08:09:18.82#ibcon#about to write, iclass 34, count 0 2006.224.08:09:18.82#ibcon#wrote, iclass 34, count 0 2006.224.08:09:18.82#ibcon#about to read 3, iclass 34, count 0 2006.224.08:09:18.85#ibcon#read 3, iclass 34, count 0 2006.224.08:09:18.85#ibcon#about to read 4, iclass 34, count 0 2006.224.08:09:18.85#ibcon#read 4, iclass 34, count 0 2006.224.08:09:18.85#ibcon#about to read 5, iclass 34, count 0 2006.224.08:09:18.85#ibcon#read 5, iclass 34, count 0 2006.224.08:09:18.85#ibcon#about to read 6, iclass 34, count 0 2006.224.08:09:18.85#ibcon#read 6, iclass 34, count 0 2006.224.08:09:18.85#ibcon#end of sib2, iclass 34, count 0 2006.224.08:09:18.85#ibcon#*after write, iclass 34, count 0 2006.224.08:09:18.85#ibcon#*before return 0, iclass 34, count 0 2006.224.08:09:18.85#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.224.08:09:18.85#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.224.08:09:18.85#ibcon#about to clear, iclass 34 cls_cnt 0 2006.224.08:09:18.85#ibcon#cleared, iclass 34 cls_cnt 0 2006.224.08:09:18.85$vc4f8/valo=4,832.99 2006.224.08:09:18.85#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.224.08:09:18.85#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.224.08:09:18.85#ibcon#ireg 17 cls_cnt 0 2006.224.08:09:18.85#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.224.08:09:18.85#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.224.08:09:18.85#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.224.08:09:18.85#ibcon#enter wrdev, iclass 36, count 0 2006.224.08:09:18.85#ibcon#first serial, iclass 36, count 0 2006.224.08:09:18.85#ibcon#enter sib2, iclass 36, count 0 2006.224.08:09:18.85#ibcon#flushed, iclass 36, count 0 2006.224.08:09:18.85#ibcon#about to write, iclass 36, count 0 2006.224.08:09:18.85#ibcon#wrote, iclass 36, count 0 2006.224.08:09:18.85#ibcon#about to read 3, iclass 36, count 0 2006.224.08:09:18.87#ibcon#read 3, iclass 36, count 0 2006.224.08:09:18.87#ibcon#about to read 4, iclass 36, count 0 2006.224.08:09:18.87#ibcon#read 4, iclass 36, count 0 2006.224.08:09:18.87#ibcon#about to read 5, iclass 36, count 0 2006.224.08:09:18.87#ibcon#read 5, iclass 36, count 0 2006.224.08:09:18.87#ibcon#about to read 6, iclass 36, count 0 2006.224.08:09:18.87#ibcon#read 6, iclass 36, count 0 2006.224.08:09:18.87#ibcon#end of sib2, iclass 36, count 0 2006.224.08:09:18.87#ibcon#*mode == 0, iclass 36, count 0 2006.224.08:09:18.87#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.224.08:09:18.87#ibcon#[26=FRQ=04,832.99\r\n] 2006.224.08:09:18.87#ibcon#*before write, iclass 36, count 0 2006.224.08:09:18.87#ibcon#enter sib2, iclass 36, count 0 2006.224.08:09:18.87#ibcon#flushed, iclass 36, count 0 2006.224.08:09:18.87#ibcon#about to write, iclass 36, count 0 2006.224.08:09:18.87#ibcon#wrote, iclass 36, count 0 2006.224.08:09:18.87#ibcon#about to read 3, iclass 36, count 0 2006.224.08:09:18.91#ibcon#read 3, iclass 36, count 0 2006.224.08:09:18.91#ibcon#about to read 4, iclass 36, count 0 2006.224.08:09:18.91#ibcon#read 4, iclass 36, count 0 2006.224.08:09:18.91#ibcon#about to read 5, iclass 36, count 0 2006.224.08:09:18.91#ibcon#read 5, iclass 36, count 0 2006.224.08:09:18.91#ibcon#about to read 6, iclass 36, count 0 2006.224.08:09:18.91#ibcon#read 6, iclass 36, count 0 2006.224.08:09:18.91#ibcon#end of sib2, iclass 36, count 0 2006.224.08:09:18.91#ibcon#*after write, iclass 36, count 0 2006.224.08:09:18.91#ibcon#*before return 0, iclass 36, count 0 2006.224.08:09:18.91#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.224.08:09:18.91#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.224.08:09:18.91#ibcon#about to clear, iclass 36 cls_cnt 0 2006.224.08:09:18.91#ibcon#cleared, iclass 36 cls_cnt 0 2006.224.08:09:18.91$vc4f8/va=4,7 2006.224.08:09:18.91#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.224.08:09:18.91#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.224.08:09:18.91#ibcon#ireg 11 cls_cnt 2 2006.224.08:09:18.91#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.224.08:09:18.97#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.224.08:09:18.97#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.224.08:09:18.97#ibcon#enter wrdev, iclass 38, count 2 2006.224.08:09:18.97#ibcon#first serial, iclass 38, count 2 2006.224.08:09:18.97#ibcon#enter sib2, iclass 38, count 2 2006.224.08:09:18.97#ibcon#flushed, iclass 38, count 2 2006.224.08:09:18.97#ibcon#about to write, iclass 38, count 2 2006.224.08:09:18.97#ibcon#wrote, iclass 38, count 2 2006.224.08:09:18.97#ibcon#about to read 3, iclass 38, count 2 2006.224.08:09:18.99#ibcon#read 3, iclass 38, count 2 2006.224.08:09:18.99#ibcon#about to read 4, iclass 38, count 2 2006.224.08:09:18.99#ibcon#read 4, iclass 38, count 2 2006.224.08:09:18.99#ibcon#about to read 5, iclass 38, count 2 2006.224.08:09:18.99#ibcon#read 5, iclass 38, count 2 2006.224.08:09:18.99#ibcon#about to read 6, iclass 38, count 2 2006.224.08:09:18.99#ibcon#read 6, iclass 38, count 2 2006.224.08:09:18.99#ibcon#end of sib2, iclass 38, count 2 2006.224.08:09:18.99#ibcon#*mode == 0, iclass 38, count 2 2006.224.08:09:18.99#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.224.08:09:18.99#ibcon#[25=AT04-07\r\n] 2006.224.08:09:18.99#ibcon#*before write, iclass 38, count 2 2006.224.08:09:18.99#ibcon#enter sib2, iclass 38, count 2 2006.224.08:09:18.99#ibcon#flushed, iclass 38, count 2 2006.224.08:09:18.99#ibcon#about to write, iclass 38, count 2 2006.224.08:09:18.99#ibcon#wrote, iclass 38, count 2 2006.224.08:09:18.99#ibcon#about to read 3, iclass 38, count 2 2006.224.08:09:19.02#ibcon#read 3, iclass 38, count 2 2006.224.08:09:19.02#ibcon#about to read 4, iclass 38, count 2 2006.224.08:09:19.02#ibcon#read 4, iclass 38, count 2 2006.224.08:09:19.02#ibcon#about to read 5, iclass 38, count 2 2006.224.08:09:19.02#ibcon#read 5, iclass 38, count 2 2006.224.08:09:19.02#ibcon#about to read 6, iclass 38, count 2 2006.224.08:09:19.02#ibcon#read 6, iclass 38, count 2 2006.224.08:09:19.02#ibcon#end of sib2, iclass 38, count 2 2006.224.08:09:19.02#ibcon#*after write, iclass 38, count 2 2006.224.08:09:19.02#ibcon#*before return 0, iclass 38, count 2 2006.224.08:09:19.02#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.224.08:09:19.02#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.224.08:09:19.02#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.224.08:09:19.02#ibcon#ireg 7 cls_cnt 0 2006.224.08:09:19.02#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.224.08:09:19.14#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.224.08:09:19.14#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.224.08:09:19.14#ibcon#enter wrdev, iclass 38, count 0 2006.224.08:09:19.14#ibcon#first serial, iclass 38, count 0 2006.224.08:09:19.14#ibcon#enter sib2, iclass 38, count 0 2006.224.08:09:19.14#ibcon#flushed, iclass 38, count 0 2006.224.08:09:19.14#ibcon#about to write, iclass 38, count 0 2006.224.08:09:19.14#ibcon#wrote, iclass 38, count 0 2006.224.08:09:19.14#ibcon#about to read 3, iclass 38, count 0 2006.224.08:09:19.16#ibcon#read 3, iclass 38, count 0 2006.224.08:09:19.16#ibcon#about to read 4, iclass 38, count 0 2006.224.08:09:19.16#ibcon#read 4, iclass 38, count 0 2006.224.08:09:19.16#ibcon#about to read 5, iclass 38, count 0 2006.224.08:09:19.16#ibcon#read 5, iclass 38, count 0 2006.224.08:09:19.16#ibcon#about to read 6, iclass 38, count 0 2006.224.08:09:19.16#ibcon#read 6, iclass 38, count 0 2006.224.08:09:19.16#ibcon#end of sib2, iclass 38, count 0 2006.224.08:09:19.16#ibcon#*mode == 0, iclass 38, count 0 2006.224.08:09:19.16#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.224.08:09:19.16#ibcon#[25=USB\r\n] 2006.224.08:09:19.16#ibcon#*before write, iclass 38, count 0 2006.224.08:09:19.16#ibcon#enter sib2, iclass 38, count 0 2006.224.08:09:19.16#ibcon#flushed, iclass 38, count 0 2006.224.08:09:19.16#ibcon#about to write, iclass 38, count 0 2006.224.08:09:19.16#ibcon#wrote, iclass 38, count 0 2006.224.08:09:19.16#ibcon#about to read 3, iclass 38, count 0 2006.224.08:09:19.19#ibcon#read 3, iclass 38, count 0 2006.224.08:09:19.19#ibcon#about to read 4, iclass 38, count 0 2006.224.08:09:19.19#ibcon#read 4, iclass 38, count 0 2006.224.08:09:19.19#ibcon#about to read 5, iclass 38, count 0 2006.224.08:09:19.19#ibcon#read 5, iclass 38, count 0 2006.224.08:09:19.19#ibcon#about to read 6, iclass 38, count 0 2006.224.08:09:19.19#ibcon#read 6, iclass 38, count 0 2006.224.08:09:19.19#ibcon#end of sib2, iclass 38, count 0 2006.224.08:09:19.19#ibcon#*after write, iclass 38, count 0 2006.224.08:09:19.19#ibcon#*before return 0, iclass 38, count 0 2006.224.08:09:19.19#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.224.08:09:19.19#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.224.08:09:19.19#ibcon#about to clear, iclass 38 cls_cnt 0 2006.224.08:09:19.19#ibcon#cleared, iclass 38 cls_cnt 0 2006.224.08:09:19.19$vc4f8/valo=5,652.99 2006.224.08:09:19.19#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.224.08:09:19.19#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.224.08:09:19.19#ibcon#ireg 17 cls_cnt 0 2006.224.08:09:19.19#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.224.08:09:19.19#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.224.08:09:19.19#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.224.08:09:19.19#ibcon#enter wrdev, iclass 40, count 0 2006.224.08:09:19.19#ibcon#first serial, iclass 40, count 0 2006.224.08:09:19.19#ibcon#enter sib2, iclass 40, count 0 2006.224.08:09:19.19#ibcon#flushed, iclass 40, count 0 2006.224.08:09:19.19#ibcon#about to write, iclass 40, count 0 2006.224.08:09:19.19#ibcon#wrote, iclass 40, count 0 2006.224.08:09:19.19#ibcon#about to read 3, iclass 40, count 0 2006.224.08:09:19.21#ibcon#read 3, iclass 40, count 0 2006.224.08:09:19.21#ibcon#about to read 4, iclass 40, count 0 2006.224.08:09:19.21#ibcon#read 4, iclass 40, count 0 2006.224.08:09:19.21#ibcon#about to read 5, iclass 40, count 0 2006.224.08:09:19.21#ibcon#read 5, iclass 40, count 0 2006.224.08:09:19.21#ibcon#about to read 6, iclass 40, count 0 2006.224.08:09:19.21#ibcon#read 6, iclass 40, count 0 2006.224.08:09:19.21#ibcon#end of sib2, iclass 40, count 0 2006.224.08:09:19.21#ibcon#*mode == 0, iclass 40, count 0 2006.224.08:09:19.21#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.224.08:09:19.21#ibcon#[26=FRQ=05,652.99\r\n] 2006.224.08:09:19.21#ibcon#*before write, iclass 40, count 0 2006.224.08:09:19.21#ibcon#enter sib2, iclass 40, count 0 2006.224.08:09:19.21#ibcon#flushed, iclass 40, count 0 2006.224.08:09:19.21#ibcon#about to write, iclass 40, count 0 2006.224.08:09:19.21#ibcon#wrote, iclass 40, count 0 2006.224.08:09:19.21#ibcon#about to read 3, iclass 40, count 0 2006.224.08:09:19.25#ibcon#read 3, iclass 40, count 0 2006.224.08:09:19.25#ibcon#about to read 4, iclass 40, count 0 2006.224.08:09:19.25#ibcon#read 4, iclass 40, count 0 2006.224.08:09:19.25#ibcon#about to read 5, iclass 40, count 0 2006.224.08:09:19.25#ibcon#read 5, iclass 40, count 0 2006.224.08:09:19.25#ibcon#about to read 6, iclass 40, count 0 2006.224.08:09:19.25#ibcon#read 6, iclass 40, count 0 2006.224.08:09:19.25#ibcon#end of sib2, iclass 40, count 0 2006.224.08:09:19.25#ibcon#*after write, iclass 40, count 0 2006.224.08:09:19.25#ibcon#*before return 0, iclass 40, count 0 2006.224.08:09:19.25#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.224.08:09:19.25#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.224.08:09:19.25#ibcon#about to clear, iclass 40 cls_cnt 0 2006.224.08:09:19.25#ibcon#cleared, iclass 40 cls_cnt 0 2006.224.08:09:19.25$vc4f8/va=5,7 2006.224.08:09:19.25#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.224.08:09:19.25#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.224.08:09:19.25#ibcon#ireg 11 cls_cnt 2 2006.224.08:09:19.25#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.224.08:09:19.31#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.224.08:09:19.31#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.224.08:09:19.31#ibcon#enter wrdev, iclass 4, count 2 2006.224.08:09:19.31#ibcon#first serial, iclass 4, count 2 2006.224.08:09:19.31#ibcon#enter sib2, iclass 4, count 2 2006.224.08:09:19.31#ibcon#flushed, iclass 4, count 2 2006.224.08:09:19.31#ibcon#about to write, iclass 4, count 2 2006.224.08:09:19.31#ibcon#wrote, iclass 4, count 2 2006.224.08:09:19.31#ibcon#about to read 3, iclass 4, count 2 2006.224.08:09:19.33#ibcon#read 3, iclass 4, count 2 2006.224.08:09:19.33#ibcon#about to read 4, iclass 4, count 2 2006.224.08:09:19.33#ibcon#read 4, iclass 4, count 2 2006.224.08:09:19.33#ibcon#about to read 5, iclass 4, count 2 2006.224.08:09:19.33#ibcon#read 5, iclass 4, count 2 2006.224.08:09:19.33#ibcon#about to read 6, iclass 4, count 2 2006.224.08:09:19.33#ibcon#read 6, iclass 4, count 2 2006.224.08:09:19.33#ibcon#end of sib2, iclass 4, count 2 2006.224.08:09:19.33#ibcon#*mode == 0, iclass 4, count 2 2006.224.08:09:19.33#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.224.08:09:19.33#ibcon#[25=AT05-07\r\n] 2006.224.08:09:19.33#ibcon#*before write, iclass 4, count 2 2006.224.08:09:19.33#ibcon#enter sib2, iclass 4, count 2 2006.224.08:09:19.33#ibcon#flushed, iclass 4, count 2 2006.224.08:09:19.33#ibcon#about to write, iclass 4, count 2 2006.224.08:09:19.33#ibcon#wrote, iclass 4, count 2 2006.224.08:09:19.33#ibcon#about to read 3, iclass 4, count 2 2006.224.08:09:19.36#ibcon#read 3, iclass 4, count 2 2006.224.08:09:19.36#ibcon#about to read 4, iclass 4, count 2 2006.224.08:09:19.36#ibcon#read 4, iclass 4, count 2 2006.224.08:09:19.36#ibcon#about to read 5, iclass 4, count 2 2006.224.08:09:19.36#ibcon#read 5, iclass 4, count 2 2006.224.08:09:19.36#ibcon#about to read 6, iclass 4, count 2 2006.224.08:09:19.36#ibcon#read 6, iclass 4, count 2 2006.224.08:09:19.36#ibcon#end of sib2, iclass 4, count 2 2006.224.08:09:19.36#ibcon#*after write, iclass 4, count 2 2006.224.08:09:19.36#ibcon#*before return 0, iclass 4, count 2 2006.224.08:09:19.36#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.224.08:09:19.36#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.224.08:09:19.36#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.224.08:09:19.36#ibcon#ireg 7 cls_cnt 0 2006.224.08:09:19.36#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.224.08:09:19.48#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.224.08:09:19.48#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.224.08:09:19.48#ibcon#enter wrdev, iclass 4, count 0 2006.224.08:09:19.48#ibcon#first serial, iclass 4, count 0 2006.224.08:09:19.48#ibcon#enter sib2, iclass 4, count 0 2006.224.08:09:19.48#ibcon#flushed, iclass 4, count 0 2006.224.08:09:19.48#ibcon#about to write, iclass 4, count 0 2006.224.08:09:19.48#ibcon#wrote, iclass 4, count 0 2006.224.08:09:19.48#ibcon#about to read 3, iclass 4, count 0 2006.224.08:09:19.50#ibcon#read 3, iclass 4, count 0 2006.224.08:09:19.50#ibcon#about to read 4, iclass 4, count 0 2006.224.08:09:19.50#ibcon#read 4, iclass 4, count 0 2006.224.08:09:19.50#ibcon#about to read 5, iclass 4, count 0 2006.224.08:09:19.50#ibcon#read 5, iclass 4, count 0 2006.224.08:09:19.50#ibcon#about to read 6, iclass 4, count 0 2006.224.08:09:19.50#ibcon#read 6, iclass 4, count 0 2006.224.08:09:19.50#ibcon#end of sib2, iclass 4, count 0 2006.224.08:09:19.50#ibcon#*mode == 0, iclass 4, count 0 2006.224.08:09:19.50#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.224.08:09:19.50#ibcon#[25=USB\r\n] 2006.224.08:09:19.50#ibcon#*before write, iclass 4, count 0 2006.224.08:09:19.50#ibcon#enter sib2, iclass 4, count 0 2006.224.08:09:19.50#ibcon#flushed, iclass 4, count 0 2006.224.08:09:19.50#ibcon#about to write, iclass 4, count 0 2006.224.08:09:19.50#ibcon#wrote, iclass 4, count 0 2006.224.08:09:19.50#ibcon#about to read 3, iclass 4, count 0 2006.224.08:09:19.53#ibcon#read 3, iclass 4, count 0 2006.224.08:09:19.53#ibcon#about to read 4, iclass 4, count 0 2006.224.08:09:19.53#ibcon#read 4, iclass 4, count 0 2006.224.08:09:19.53#ibcon#about to read 5, iclass 4, count 0 2006.224.08:09:19.53#ibcon#read 5, iclass 4, count 0 2006.224.08:09:19.53#ibcon#about to read 6, iclass 4, count 0 2006.224.08:09:19.53#ibcon#read 6, iclass 4, count 0 2006.224.08:09:19.53#ibcon#end of sib2, iclass 4, count 0 2006.224.08:09:19.53#ibcon#*after write, iclass 4, count 0 2006.224.08:09:19.53#ibcon#*before return 0, iclass 4, count 0 2006.224.08:09:19.53#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.224.08:09:19.53#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.224.08:09:19.53#ibcon#about to clear, iclass 4 cls_cnt 0 2006.224.08:09:19.53#ibcon#cleared, iclass 4 cls_cnt 0 2006.224.08:09:19.53$vc4f8/valo=6,772.99 2006.224.08:09:19.53#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.224.08:09:19.53#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.224.08:09:19.53#ibcon#ireg 17 cls_cnt 0 2006.224.08:09:19.53#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.224.08:09:19.53#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.224.08:09:19.53#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.224.08:09:19.53#ibcon#enter wrdev, iclass 6, count 0 2006.224.08:09:19.53#ibcon#first serial, iclass 6, count 0 2006.224.08:09:19.53#ibcon#enter sib2, iclass 6, count 0 2006.224.08:09:19.53#ibcon#flushed, iclass 6, count 0 2006.224.08:09:19.53#ibcon#about to write, iclass 6, count 0 2006.224.08:09:19.53#ibcon#wrote, iclass 6, count 0 2006.224.08:09:19.53#ibcon#about to read 3, iclass 6, count 0 2006.224.08:09:19.55#ibcon#read 3, iclass 6, count 0 2006.224.08:09:19.55#ibcon#about to read 4, iclass 6, count 0 2006.224.08:09:19.55#ibcon#read 4, iclass 6, count 0 2006.224.08:09:19.55#ibcon#about to read 5, iclass 6, count 0 2006.224.08:09:19.55#ibcon#read 5, iclass 6, count 0 2006.224.08:09:19.55#ibcon#about to read 6, iclass 6, count 0 2006.224.08:09:19.55#ibcon#read 6, iclass 6, count 0 2006.224.08:09:19.55#ibcon#end of sib2, iclass 6, count 0 2006.224.08:09:19.55#ibcon#*mode == 0, iclass 6, count 0 2006.224.08:09:19.55#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.224.08:09:19.55#ibcon#[26=FRQ=06,772.99\r\n] 2006.224.08:09:19.55#ibcon#*before write, iclass 6, count 0 2006.224.08:09:19.55#ibcon#enter sib2, iclass 6, count 0 2006.224.08:09:19.55#ibcon#flushed, iclass 6, count 0 2006.224.08:09:19.55#ibcon#about to write, iclass 6, count 0 2006.224.08:09:19.55#ibcon#wrote, iclass 6, count 0 2006.224.08:09:19.55#ibcon#about to read 3, iclass 6, count 0 2006.224.08:09:19.60#ibcon#read 3, iclass 6, count 0 2006.224.08:09:19.60#ibcon#about to read 4, iclass 6, count 0 2006.224.08:09:19.60#ibcon#read 4, iclass 6, count 0 2006.224.08:09:19.60#ibcon#about to read 5, iclass 6, count 0 2006.224.08:09:19.60#ibcon#read 5, iclass 6, count 0 2006.224.08:09:19.60#ibcon#about to read 6, iclass 6, count 0 2006.224.08:09:19.60#ibcon#read 6, iclass 6, count 0 2006.224.08:09:19.60#ibcon#end of sib2, iclass 6, count 0 2006.224.08:09:19.60#ibcon#*after write, iclass 6, count 0 2006.224.08:09:19.60#ibcon#*before return 0, iclass 6, count 0 2006.224.08:09:19.60#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.224.08:09:19.60#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.224.08:09:19.60#ibcon#about to clear, iclass 6 cls_cnt 0 2006.224.08:09:19.60#ibcon#cleared, iclass 6 cls_cnt 0 2006.224.08:09:19.60$vc4f8/va=6,6 2006.224.08:09:19.60#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.224.08:09:19.60#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.224.08:09:19.60#ibcon#ireg 11 cls_cnt 2 2006.224.08:09:19.60#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.224.08:09:19.65#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.224.08:09:19.65#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.224.08:09:19.65#ibcon#enter wrdev, iclass 10, count 2 2006.224.08:09:19.65#ibcon#first serial, iclass 10, count 2 2006.224.08:09:19.65#ibcon#enter sib2, iclass 10, count 2 2006.224.08:09:19.65#ibcon#flushed, iclass 10, count 2 2006.224.08:09:19.65#ibcon#about to write, iclass 10, count 2 2006.224.08:09:19.65#ibcon#wrote, iclass 10, count 2 2006.224.08:09:19.65#ibcon#about to read 3, iclass 10, count 2 2006.224.08:09:19.67#ibcon#read 3, iclass 10, count 2 2006.224.08:09:19.67#ibcon#about to read 4, iclass 10, count 2 2006.224.08:09:19.67#ibcon#read 4, iclass 10, count 2 2006.224.08:09:19.67#ibcon#about to read 5, iclass 10, count 2 2006.224.08:09:19.67#ibcon#read 5, iclass 10, count 2 2006.224.08:09:19.67#ibcon#about to read 6, iclass 10, count 2 2006.224.08:09:19.67#ibcon#read 6, iclass 10, count 2 2006.224.08:09:19.67#ibcon#end of sib2, iclass 10, count 2 2006.224.08:09:19.67#ibcon#*mode == 0, iclass 10, count 2 2006.224.08:09:19.67#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.224.08:09:19.67#ibcon#[25=AT06-06\r\n] 2006.224.08:09:19.67#ibcon#*before write, iclass 10, count 2 2006.224.08:09:19.67#ibcon#enter sib2, iclass 10, count 2 2006.224.08:09:19.67#ibcon#flushed, iclass 10, count 2 2006.224.08:09:19.67#ibcon#about to write, iclass 10, count 2 2006.224.08:09:19.67#ibcon#wrote, iclass 10, count 2 2006.224.08:09:19.67#ibcon#about to read 3, iclass 10, count 2 2006.224.08:09:19.70#ibcon#read 3, iclass 10, count 2 2006.224.08:09:19.70#ibcon#about to read 4, iclass 10, count 2 2006.224.08:09:19.70#ibcon#read 4, iclass 10, count 2 2006.224.08:09:19.70#ibcon#about to read 5, iclass 10, count 2 2006.224.08:09:19.70#ibcon#read 5, iclass 10, count 2 2006.224.08:09:19.70#ibcon#about to read 6, iclass 10, count 2 2006.224.08:09:19.70#ibcon#read 6, iclass 10, count 2 2006.224.08:09:19.70#ibcon#end of sib2, iclass 10, count 2 2006.224.08:09:19.70#ibcon#*after write, iclass 10, count 2 2006.224.08:09:19.70#ibcon#*before return 0, iclass 10, count 2 2006.224.08:09:19.70#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.224.08:09:19.70#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.224.08:09:19.70#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.224.08:09:19.70#ibcon#ireg 7 cls_cnt 0 2006.224.08:09:19.70#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.224.08:09:19.82#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.224.08:09:19.82#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.224.08:09:19.82#ibcon#enter wrdev, iclass 10, count 0 2006.224.08:09:19.82#ibcon#first serial, iclass 10, count 0 2006.224.08:09:19.82#ibcon#enter sib2, iclass 10, count 0 2006.224.08:09:19.82#ibcon#flushed, iclass 10, count 0 2006.224.08:09:19.82#ibcon#about to write, iclass 10, count 0 2006.224.08:09:19.82#ibcon#wrote, iclass 10, count 0 2006.224.08:09:19.82#ibcon#about to read 3, iclass 10, count 0 2006.224.08:09:19.84#ibcon#read 3, iclass 10, count 0 2006.224.08:09:19.84#ibcon#about to read 4, iclass 10, count 0 2006.224.08:09:19.84#ibcon#read 4, iclass 10, count 0 2006.224.08:09:19.84#ibcon#about to read 5, iclass 10, count 0 2006.224.08:09:19.84#ibcon#read 5, iclass 10, count 0 2006.224.08:09:19.84#ibcon#about to read 6, iclass 10, count 0 2006.224.08:09:19.84#ibcon#read 6, iclass 10, count 0 2006.224.08:09:19.84#ibcon#end of sib2, iclass 10, count 0 2006.224.08:09:19.84#ibcon#*mode == 0, iclass 10, count 0 2006.224.08:09:19.84#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.224.08:09:19.84#ibcon#[25=USB\r\n] 2006.224.08:09:19.84#ibcon#*before write, iclass 10, count 0 2006.224.08:09:19.84#ibcon#enter sib2, iclass 10, count 0 2006.224.08:09:19.84#ibcon#flushed, iclass 10, count 0 2006.224.08:09:19.84#ibcon#about to write, iclass 10, count 0 2006.224.08:09:19.84#ibcon#wrote, iclass 10, count 0 2006.224.08:09:19.84#ibcon#about to read 3, iclass 10, count 0 2006.224.08:09:19.87#ibcon#read 3, iclass 10, count 0 2006.224.08:09:19.87#ibcon#about to read 4, iclass 10, count 0 2006.224.08:09:19.87#ibcon#read 4, iclass 10, count 0 2006.224.08:09:19.87#ibcon#about to read 5, iclass 10, count 0 2006.224.08:09:19.87#ibcon#read 5, iclass 10, count 0 2006.224.08:09:19.87#ibcon#about to read 6, iclass 10, count 0 2006.224.08:09:19.87#ibcon#read 6, iclass 10, count 0 2006.224.08:09:19.87#ibcon#end of sib2, iclass 10, count 0 2006.224.08:09:19.87#ibcon#*after write, iclass 10, count 0 2006.224.08:09:19.87#ibcon#*before return 0, iclass 10, count 0 2006.224.08:09:19.87#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.224.08:09:19.87#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.224.08:09:19.87#ibcon#about to clear, iclass 10 cls_cnt 0 2006.224.08:09:19.87#ibcon#cleared, iclass 10 cls_cnt 0 2006.224.08:09:19.87$vc4f8/valo=7,832.99 2006.224.08:09:19.87#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.224.08:09:19.87#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.224.08:09:19.87#ibcon#ireg 17 cls_cnt 0 2006.224.08:09:19.87#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.224.08:09:19.87#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.224.08:09:19.87#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.224.08:09:19.87#ibcon#enter wrdev, iclass 12, count 0 2006.224.08:09:19.87#ibcon#first serial, iclass 12, count 0 2006.224.08:09:19.87#ibcon#enter sib2, iclass 12, count 0 2006.224.08:09:19.87#ibcon#flushed, iclass 12, count 0 2006.224.08:09:19.87#ibcon#about to write, iclass 12, count 0 2006.224.08:09:19.87#ibcon#wrote, iclass 12, count 0 2006.224.08:09:19.87#ibcon#about to read 3, iclass 12, count 0 2006.224.08:09:19.89#ibcon#read 3, iclass 12, count 0 2006.224.08:09:19.89#ibcon#about to read 4, iclass 12, count 0 2006.224.08:09:19.89#ibcon#read 4, iclass 12, count 0 2006.224.08:09:19.89#ibcon#about to read 5, iclass 12, count 0 2006.224.08:09:19.89#ibcon#read 5, iclass 12, count 0 2006.224.08:09:19.89#ibcon#about to read 6, iclass 12, count 0 2006.224.08:09:19.89#ibcon#read 6, iclass 12, count 0 2006.224.08:09:19.89#ibcon#end of sib2, iclass 12, count 0 2006.224.08:09:19.89#ibcon#*mode == 0, iclass 12, count 0 2006.224.08:09:19.89#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.224.08:09:19.89#ibcon#[26=FRQ=07,832.99\r\n] 2006.224.08:09:19.89#ibcon#*before write, iclass 12, count 0 2006.224.08:09:19.89#ibcon#enter sib2, iclass 12, count 0 2006.224.08:09:19.89#ibcon#flushed, iclass 12, count 0 2006.224.08:09:19.89#ibcon#about to write, iclass 12, count 0 2006.224.08:09:19.89#ibcon#wrote, iclass 12, count 0 2006.224.08:09:19.89#ibcon#about to read 3, iclass 12, count 0 2006.224.08:09:19.93#ibcon#read 3, iclass 12, count 0 2006.224.08:09:19.93#ibcon#about to read 4, iclass 12, count 0 2006.224.08:09:19.93#ibcon#read 4, iclass 12, count 0 2006.224.08:09:19.93#ibcon#about to read 5, iclass 12, count 0 2006.224.08:09:19.93#ibcon#read 5, iclass 12, count 0 2006.224.08:09:19.93#ibcon#about to read 6, iclass 12, count 0 2006.224.08:09:19.93#ibcon#read 6, iclass 12, count 0 2006.224.08:09:19.93#ibcon#end of sib2, iclass 12, count 0 2006.224.08:09:19.93#ibcon#*after write, iclass 12, count 0 2006.224.08:09:19.93#ibcon#*before return 0, iclass 12, count 0 2006.224.08:09:19.93#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.224.08:09:19.93#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.224.08:09:19.93#ibcon#about to clear, iclass 12 cls_cnt 0 2006.224.08:09:19.93#ibcon#cleared, iclass 12 cls_cnt 0 2006.224.08:09:19.93$vc4f8/va=7,6 2006.224.08:09:19.93#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.224.08:09:19.93#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.224.08:09:19.93#ibcon#ireg 11 cls_cnt 2 2006.224.08:09:19.93#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.224.08:09:19.99#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.224.08:09:19.99#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.224.08:09:19.99#ibcon#enter wrdev, iclass 14, count 2 2006.224.08:09:19.99#ibcon#first serial, iclass 14, count 2 2006.224.08:09:19.99#ibcon#enter sib2, iclass 14, count 2 2006.224.08:09:19.99#ibcon#flushed, iclass 14, count 2 2006.224.08:09:19.99#ibcon#about to write, iclass 14, count 2 2006.224.08:09:19.99#ibcon#wrote, iclass 14, count 2 2006.224.08:09:19.99#ibcon#about to read 3, iclass 14, count 2 2006.224.08:09:20.01#ibcon#read 3, iclass 14, count 2 2006.224.08:09:20.01#ibcon#about to read 4, iclass 14, count 2 2006.224.08:09:20.01#ibcon#read 4, iclass 14, count 2 2006.224.08:09:20.01#ibcon#about to read 5, iclass 14, count 2 2006.224.08:09:20.01#ibcon#read 5, iclass 14, count 2 2006.224.08:09:20.01#ibcon#about to read 6, iclass 14, count 2 2006.224.08:09:20.01#ibcon#read 6, iclass 14, count 2 2006.224.08:09:20.01#ibcon#end of sib2, iclass 14, count 2 2006.224.08:09:20.01#ibcon#*mode == 0, iclass 14, count 2 2006.224.08:09:20.01#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.224.08:09:20.01#ibcon#[25=AT07-06\r\n] 2006.224.08:09:20.01#ibcon#*before write, iclass 14, count 2 2006.224.08:09:20.01#ibcon#enter sib2, iclass 14, count 2 2006.224.08:09:20.01#ibcon#flushed, iclass 14, count 2 2006.224.08:09:20.01#ibcon#about to write, iclass 14, count 2 2006.224.08:09:20.01#ibcon#wrote, iclass 14, count 2 2006.224.08:09:20.01#ibcon#about to read 3, iclass 14, count 2 2006.224.08:09:20.04#ibcon#read 3, iclass 14, count 2 2006.224.08:09:20.04#ibcon#about to read 4, iclass 14, count 2 2006.224.08:09:20.04#ibcon#read 4, iclass 14, count 2 2006.224.08:09:20.04#ibcon#about to read 5, iclass 14, count 2 2006.224.08:09:20.04#ibcon#read 5, iclass 14, count 2 2006.224.08:09:20.04#ibcon#about to read 6, iclass 14, count 2 2006.224.08:09:20.04#ibcon#read 6, iclass 14, count 2 2006.224.08:09:20.04#ibcon#end of sib2, iclass 14, count 2 2006.224.08:09:20.04#ibcon#*after write, iclass 14, count 2 2006.224.08:09:20.04#ibcon#*before return 0, iclass 14, count 2 2006.224.08:09:20.04#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.224.08:09:20.04#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.224.08:09:20.04#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.224.08:09:20.04#ibcon#ireg 7 cls_cnt 0 2006.224.08:09:20.04#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.224.08:09:20.16#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.224.08:09:20.16#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.224.08:09:20.16#ibcon#enter wrdev, iclass 14, count 0 2006.224.08:09:20.16#ibcon#first serial, iclass 14, count 0 2006.224.08:09:20.16#ibcon#enter sib2, iclass 14, count 0 2006.224.08:09:20.16#ibcon#flushed, iclass 14, count 0 2006.224.08:09:20.16#ibcon#about to write, iclass 14, count 0 2006.224.08:09:20.16#ibcon#wrote, iclass 14, count 0 2006.224.08:09:20.16#ibcon#about to read 3, iclass 14, count 0 2006.224.08:09:20.18#ibcon#read 3, iclass 14, count 0 2006.224.08:09:20.18#ibcon#about to read 4, iclass 14, count 0 2006.224.08:09:20.18#ibcon#read 4, iclass 14, count 0 2006.224.08:09:20.18#ibcon#about to read 5, iclass 14, count 0 2006.224.08:09:20.18#ibcon#read 5, iclass 14, count 0 2006.224.08:09:20.18#ibcon#about to read 6, iclass 14, count 0 2006.224.08:09:20.18#ibcon#read 6, iclass 14, count 0 2006.224.08:09:20.18#ibcon#end of sib2, iclass 14, count 0 2006.224.08:09:20.18#ibcon#*mode == 0, iclass 14, count 0 2006.224.08:09:20.18#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.224.08:09:20.18#ibcon#[25=USB\r\n] 2006.224.08:09:20.18#ibcon#*before write, iclass 14, count 0 2006.224.08:09:20.18#ibcon#enter sib2, iclass 14, count 0 2006.224.08:09:20.18#ibcon#flushed, iclass 14, count 0 2006.224.08:09:20.18#ibcon#about to write, iclass 14, count 0 2006.224.08:09:20.18#ibcon#wrote, iclass 14, count 0 2006.224.08:09:20.18#ibcon#about to read 3, iclass 14, count 0 2006.224.08:09:20.21#ibcon#read 3, iclass 14, count 0 2006.224.08:09:20.21#ibcon#about to read 4, iclass 14, count 0 2006.224.08:09:20.21#ibcon#read 4, iclass 14, count 0 2006.224.08:09:20.21#ibcon#about to read 5, iclass 14, count 0 2006.224.08:09:20.21#ibcon#read 5, iclass 14, count 0 2006.224.08:09:20.21#ibcon#about to read 6, iclass 14, count 0 2006.224.08:09:20.21#ibcon#read 6, iclass 14, count 0 2006.224.08:09:20.21#ibcon#end of sib2, iclass 14, count 0 2006.224.08:09:20.21#ibcon#*after write, iclass 14, count 0 2006.224.08:09:20.21#ibcon#*before return 0, iclass 14, count 0 2006.224.08:09:20.21#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.224.08:09:20.21#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.224.08:09:20.21#ibcon#about to clear, iclass 14 cls_cnt 0 2006.224.08:09:20.21#ibcon#cleared, iclass 14 cls_cnt 0 2006.224.08:09:20.21$vc4f8/valo=8,852.99 2006.224.08:09:20.21#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.224.08:09:20.21#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.224.08:09:20.21#ibcon#ireg 17 cls_cnt 0 2006.224.08:09:20.21#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.224.08:09:20.21#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.224.08:09:20.21#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.224.08:09:20.21#ibcon#enter wrdev, iclass 16, count 0 2006.224.08:09:20.21#ibcon#first serial, iclass 16, count 0 2006.224.08:09:20.21#ibcon#enter sib2, iclass 16, count 0 2006.224.08:09:20.21#ibcon#flushed, iclass 16, count 0 2006.224.08:09:20.21#ibcon#about to write, iclass 16, count 0 2006.224.08:09:20.21#ibcon#wrote, iclass 16, count 0 2006.224.08:09:20.21#ibcon#about to read 3, iclass 16, count 0 2006.224.08:09:20.23#ibcon#read 3, iclass 16, count 0 2006.224.08:09:20.23#ibcon#about to read 4, iclass 16, count 0 2006.224.08:09:20.23#ibcon#read 4, iclass 16, count 0 2006.224.08:09:20.23#ibcon#about to read 5, iclass 16, count 0 2006.224.08:09:20.23#ibcon#read 5, iclass 16, count 0 2006.224.08:09:20.23#ibcon#about to read 6, iclass 16, count 0 2006.224.08:09:20.23#ibcon#read 6, iclass 16, count 0 2006.224.08:09:20.23#ibcon#end of sib2, iclass 16, count 0 2006.224.08:09:20.23#ibcon#*mode == 0, iclass 16, count 0 2006.224.08:09:20.23#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.224.08:09:20.23#ibcon#[26=FRQ=08,852.99\r\n] 2006.224.08:09:20.23#ibcon#*before write, iclass 16, count 0 2006.224.08:09:20.23#ibcon#enter sib2, iclass 16, count 0 2006.224.08:09:20.23#ibcon#flushed, iclass 16, count 0 2006.224.08:09:20.23#ibcon#about to write, iclass 16, count 0 2006.224.08:09:20.23#ibcon#wrote, iclass 16, count 0 2006.224.08:09:20.23#ibcon#about to read 3, iclass 16, count 0 2006.224.08:09:20.27#ibcon#read 3, iclass 16, count 0 2006.224.08:09:20.27#ibcon#about to read 4, iclass 16, count 0 2006.224.08:09:20.27#ibcon#read 4, iclass 16, count 0 2006.224.08:09:20.27#ibcon#about to read 5, iclass 16, count 0 2006.224.08:09:20.27#ibcon#read 5, iclass 16, count 0 2006.224.08:09:20.27#ibcon#about to read 6, iclass 16, count 0 2006.224.08:09:20.27#ibcon#read 6, iclass 16, count 0 2006.224.08:09:20.27#ibcon#end of sib2, iclass 16, count 0 2006.224.08:09:20.27#ibcon#*after write, iclass 16, count 0 2006.224.08:09:20.27#ibcon#*before return 0, iclass 16, count 0 2006.224.08:09:20.27#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.224.08:09:20.27#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.224.08:09:20.27#ibcon#about to clear, iclass 16 cls_cnt 0 2006.224.08:09:20.27#ibcon#cleared, iclass 16 cls_cnt 0 2006.224.08:09:20.27$vc4f8/va=8,7 2006.224.08:09:20.27#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.224.08:09:20.27#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.224.08:09:20.27#ibcon#ireg 11 cls_cnt 2 2006.224.08:09:20.27#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.224.08:09:20.33#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.224.08:09:20.33#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.224.08:09:20.33#ibcon#enter wrdev, iclass 18, count 2 2006.224.08:09:20.33#ibcon#first serial, iclass 18, count 2 2006.224.08:09:20.33#ibcon#enter sib2, iclass 18, count 2 2006.224.08:09:20.33#ibcon#flushed, iclass 18, count 2 2006.224.08:09:20.33#ibcon#about to write, iclass 18, count 2 2006.224.08:09:20.33#ibcon#wrote, iclass 18, count 2 2006.224.08:09:20.33#ibcon#about to read 3, iclass 18, count 2 2006.224.08:09:20.35#ibcon#read 3, iclass 18, count 2 2006.224.08:09:20.35#ibcon#about to read 4, iclass 18, count 2 2006.224.08:09:20.35#ibcon#read 4, iclass 18, count 2 2006.224.08:09:20.35#ibcon#about to read 5, iclass 18, count 2 2006.224.08:09:20.35#ibcon#read 5, iclass 18, count 2 2006.224.08:09:20.35#ibcon#about to read 6, iclass 18, count 2 2006.224.08:09:20.35#ibcon#read 6, iclass 18, count 2 2006.224.08:09:20.35#ibcon#end of sib2, iclass 18, count 2 2006.224.08:09:20.35#ibcon#*mode == 0, iclass 18, count 2 2006.224.08:09:20.35#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.224.08:09:20.35#ibcon#[25=AT08-07\r\n] 2006.224.08:09:20.35#ibcon#*before write, iclass 18, count 2 2006.224.08:09:20.35#ibcon#enter sib2, iclass 18, count 2 2006.224.08:09:20.35#ibcon#flushed, iclass 18, count 2 2006.224.08:09:20.35#ibcon#about to write, iclass 18, count 2 2006.224.08:09:20.35#ibcon#wrote, iclass 18, count 2 2006.224.08:09:20.35#ibcon#about to read 3, iclass 18, count 2 2006.224.08:09:20.38#ibcon#read 3, iclass 18, count 2 2006.224.08:09:20.38#ibcon#about to read 4, iclass 18, count 2 2006.224.08:09:20.38#ibcon#read 4, iclass 18, count 2 2006.224.08:09:20.38#ibcon#about to read 5, iclass 18, count 2 2006.224.08:09:20.38#ibcon#read 5, iclass 18, count 2 2006.224.08:09:20.38#ibcon#about to read 6, iclass 18, count 2 2006.224.08:09:20.38#ibcon#read 6, iclass 18, count 2 2006.224.08:09:20.38#ibcon#end of sib2, iclass 18, count 2 2006.224.08:09:20.38#ibcon#*after write, iclass 18, count 2 2006.224.08:09:20.38#ibcon#*before return 0, iclass 18, count 2 2006.224.08:09:20.38#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.224.08:09:20.38#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.224.08:09:20.38#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.224.08:09:20.38#ibcon#ireg 7 cls_cnt 0 2006.224.08:09:20.38#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.224.08:09:20.50#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.224.08:09:20.50#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.224.08:09:20.50#ibcon#enter wrdev, iclass 18, count 0 2006.224.08:09:20.50#ibcon#first serial, iclass 18, count 0 2006.224.08:09:20.50#ibcon#enter sib2, iclass 18, count 0 2006.224.08:09:20.50#ibcon#flushed, iclass 18, count 0 2006.224.08:09:20.50#ibcon#about to write, iclass 18, count 0 2006.224.08:09:20.50#ibcon#wrote, iclass 18, count 0 2006.224.08:09:20.50#ibcon#about to read 3, iclass 18, count 0 2006.224.08:09:20.52#ibcon#read 3, iclass 18, count 0 2006.224.08:09:20.52#ibcon#about to read 4, iclass 18, count 0 2006.224.08:09:20.52#ibcon#read 4, iclass 18, count 0 2006.224.08:09:20.52#ibcon#about to read 5, iclass 18, count 0 2006.224.08:09:20.52#ibcon#read 5, iclass 18, count 0 2006.224.08:09:20.52#ibcon#about to read 6, iclass 18, count 0 2006.224.08:09:20.52#ibcon#read 6, iclass 18, count 0 2006.224.08:09:20.52#ibcon#end of sib2, iclass 18, count 0 2006.224.08:09:20.52#ibcon#*mode == 0, iclass 18, count 0 2006.224.08:09:20.52#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.224.08:09:20.52#ibcon#[25=USB\r\n] 2006.224.08:09:20.52#ibcon#*before write, iclass 18, count 0 2006.224.08:09:20.52#ibcon#enter sib2, iclass 18, count 0 2006.224.08:09:20.52#ibcon#flushed, iclass 18, count 0 2006.224.08:09:20.52#ibcon#about to write, iclass 18, count 0 2006.224.08:09:20.52#ibcon#wrote, iclass 18, count 0 2006.224.08:09:20.52#ibcon#about to read 3, iclass 18, count 0 2006.224.08:09:20.55#ibcon#read 3, iclass 18, count 0 2006.224.08:09:20.55#ibcon#about to read 4, iclass 18, count 0 2006.224.08:09:20.55#ibcon#read 4, iclass 18, count 0 2006.224.08:09:20.55#ibcon#about to read 5, iclass 18, count 0 2006.224.08:09:20.55#ibcon#read 5, iclass 18, count 0 2006.224.08:09:20.55#ibcon#about to read 6, iclass 18, count 0 2006.224.08:09:20.55#ibcon#read 6, iclass 18, count 0 2006.224.08:09:20.55#ibcon#end of sib2, iclass 18, count 0 2006.224.08:09:20.55#ibcon#*after write, iclass 18, count 0 2006.224.08:09:20.55#ibcon#*before return 0, iclass 18, count 0 2006.224.08:09:20.55#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.224.08:09:20.55#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.224.08:09:20.55#ibcon#about to clear, iclass 18 cls_cnt 0 2006.224.08:09:20.55#ibcon#cleared, iclass 18 cls_cnt 0 2006.224.08:09:20.55$vc4f8/vblo=1,632.99 2006.224.08:09:20.55#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.224.08:09:20.55#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.224.08:09:20.55#ibcon#ireg 17 cls_cnt 0 2006.224.08:09:20.55#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.224.08:09:20.55#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.224.08:09:20.55#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.224.08:09:20.55#ibcon#enter wrdev, iclass 20, count 0 2006.224.08:09:20.55#ibcon#first serial, iclass 20, count 0 2006.224.08:09:20.55#ibcon#enter sib2, iclass 20, count 0 2006.224.08:09:20.55#ibcon#flushed, iclass 20, count 0 2006.224.08:09:20.55#ibcon#about to write, iclass 20, count 0 2006.224.08:09:20.55#ibcon#wrote, iclass 20, count 0 2006.224.08:09:20.55#ibcon#about to read 3, iclass 20, count 0 2006.224.08:09:20.57#ibcon#read 3, iclass 20, count 0 2006.224.08:09:20.57#ibcon#about to read 4, iclass 20, count 0 2006.224.08:09:20.57#ibcon#read 4, iclass 20, count 0 2006.224.08:09:20.57#ibcon#about to read 5, iclass 20, count 0 2006.224.08:09:20.57#ibcon#read 5, iclass 20, count 0 2006.224.08:09:20.57#ibcon#about to read 6, iclass 20, count 0 2006.224.08:09:20.57#ibcon#read 6, iclass 20, count 0 2006.224.08:09:20.57#ibcon#end of sib2, iclass 20, count 0 2006.224.08:09:20.57#ibcon#*mode == 0, iclass 20, count 0 2006.224.08:09:20.57#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.224.08:09:20.57#ibcon#[28=FRQ=01,632.99\r\n] 2006.224.08:09:20.57#ibcon#*before write, iclass 20, count 0 2006.224.08:09:20.57#ibcon#enter sib2, iclass 20, count 0 2006.224.08:09:20.57#ibcon#flushed, iclass 20, count 0 2006.224.08:09:20.57#ibcon#about to write, iclass 20, count 0 2006.224.08:09:20.57#ibcon#wrote, iclass 20, count 0 2006.224.08:09:20.57#ibcon#about to read 3, iclass 20, count 0 2006.224.08:09:20.61#ibcon#read 3, iclass 20, count 0 2006.224.08:09:20.61#ibcon#about to read 4, iclass 20, count 0 2006.224.08:09:20.61#ibcon#read 4, iclass 20, count 0 2006.224.08:09:20.61#ibcon#about to read 5, iclass 20, count 0 2006.224.08:09:20.61#ibcon#read 5, iclass 20, count 0 2006.224.08:09:20.61#ibcon#about to read 6, iclass 20, count 0 2006.224.08:09:20.61#ibcon#read 6, iclass 20, count 0 2006.224.08:09:20.61#ibcon#end of sib2, iclass 20, count 0 2006.224.08:09:20.61#ibcon#*after write, iclass 20, count 0 2006.224.08:09:20.61#ibcon#*before return 0, iclass 20, count 0 2006.224.08:09:20.61#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.224.08:09:20.61#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.224.08:09:20.61#ibcon#about to clear, iclass 20 cls_cnt 0 2006.224.08:09:20.61#ibcon#cleared, iclass 20 cls_cnt 0 2006.224.08:09:20.61$vc4f8/vb=1,4 2006.224.08:09:20.61#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.224.08:09:20.61#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.224.08:09:20.61#ibcon#ireg 11 cls_cnt 2 2006.224.08:09:20.61#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.224.08:09:20.61#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.224.08:09:20.61#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.224.08:09:20.61#ibcon#enter wrdev, iclass 22, count 2 2006.224.08:09:20.61#ibcon#first serial, iclass 22, count 2 2006.224.08:09:20.61#ibcon#enter sib2, iclass 22, count 2 2006.224.08:09:20.61#ibcon#flushed, iclass 22, count 2 2006.224.08:09:20.61#ibcon#about to write, iclass 22, count 2 2006.224.08:09:20.61#ibcon#wrote, iclass 22, count 2 2006.224.08:09:20.61#ibcon#about to read 3, iclass 22, count 2 2006.224.08:09:20.63#ibcon#read 3, iclass 22, count 2 2006.224.08:09:20.63#ibcon#about to read 4, iclass 22, count 2 2006.224.08:09:20.63#ibcon#read 4, iclass 22, count 2 2006.224.08:09:20.63#ibcon#about to read 5, iclass 22, count 2 2006.224.08:09:20.63#ibcon#read 5, iclass 22, count 2 2006.224.08:09:20.63#ibcon#about to read 6, iclass 22, count 2 2006.224.08:09:20.63#ibcon#read 6, iclass 22, count 2 2006.224.08:09:20.63#ibcon#end of sib2, iclass 22, count 2 2006.224.08:09:20.63#ibcon#*mode == 0, iclass 22, count 2 2006.224.08:09:20.63#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.224.08:09:20.63#ibcon#[27=AT01-04\r\n] 2006.224.08:09:20.63#ibcon#*before write, iclass 22, count 2 2006.224.08:09:20.63#ibcon#enter sib2, iclass 22, count 2 2006.224.08:09:20.63#ibcon#flushed, iclass 22, count 2 2006.224.08:09:20.63#ibcon#about to write, iclass 22, count 2 2006.224.08:09:20.63#ibcon#wrote, iclass 22, count 2 2006.224.08:09:20.63#ibcon#about to read 3, iclass 22, count 2 2006.224.08:09:20.66#ibcon#read 3, iclass 22, count 2 2006.224.08:09:20.66#ibcon#about to read 4, iclass 22, count 2 2006.224.08:09:20.66#ibcon#read 4, iclass 22, count 2 2006.224.08:09:20.66#ibcon#about to read 5, iclass 22, count 2 2006.224.08:09:20.66#ibcon#read 5, iclass 22, count 2 2006.224.08:09:20.66#ibcon#about to read 6, iclass 22, count 2 2006.224.08:09:20.66#ibcon#read 6, iclass 22, count 2 2006.224.08:09:20.66#ibcon#end of sib2, iclass 22, count 2 2006.224.08:09:20.66#ibcon#*after write, iclass 22, count 2 2006.224.08:09:20.66#ibcon#*before return 0, iclass 22, count 2 2006.224.08:09:20.66#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.224.08:09:20.66#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.224.08:09:20.66#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.224.08:09:20.66#ibcon#ireg 7 cls_cnt 0 2006.224.08:09:20.66#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.224.08:09:20.78#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.224.08:09:20.78#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.224.08:09:20.78#ibcon#enter wrdev, iclass 22, count 0 2006.224.08:09:20.78#ibcon#first serial, iclass 22, count 0 2006.224.08:09:20.78#ibcon#enter sib2, iclass 22, count 0 2006.224.08:09:20.78#ibcon#flushed, iclass 22, count 0 2006.224.08:09:20.78#ibcon#about to write, iclass 22, count 0 2006.224.08:09:20.78#ibcon#wrote, iclass 22, count 0 2006.224.08:09:20.78#ibcon#about to read 3, iclass 22, count 0 2006.224.08:09:20.80#ibcon#read 3, iclass 22, count 0 2006.224.08:09:20.80#ibcon#about to read 4, iclass 22, count 0 2006.224.08:09:20.80#ibcon#read 4, iclass 22, count 0 2006.224.08:09:20.80#ibcon#about to read 5, iclass 22, count 0 2006.224.08:09:20.80#ibcon#read 5, iclass 22, count 0 2006.224.08:09:20.80#ibcon#about to read 6, iclass 22, count 0 2006.224.08:09:20.80#ibcon#read 6, iclass 22, count 0 2006.224.08:09:20.80#ibcon#end of sib2, iclass 22, count 0 2006.224.08:09:20.80#ibcon#*mode == 0, iclass 22, count 0 2006.224.08:09:20.80#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.224.08:09:20.80#ibcon#[27=USB\r\n] 2006.224.08:09:20.80#ibcon#*before write, iclass 22, count 0 2006.224.08:09:20.80#ibcon#enter sib2, iclass 22, count 0 2006.224.08:09:20.80#ibcon#flushed, iclass 22, count 0 2006.224.08:09:20.80#ibcon#about to write, iclass 22, count 0 2006.224.08:09:20.80#ibcon#wrote, iclass 22, count 0 2006.224.08:09:20.80#ibcon#about to read 3, iclass 22, count 0 2006.224.08:09:20.83#ibcon#read 3, iclass 22, count 0 2006.224.08:09:20.83#ibcon#about to read 4, iclass 22, count 0 2006.224.08:09:20.83#ibcon#read 4, iclass 22, count 0 2006.224.08:09:20.83#ibcon#about to read 5, iclass 22, count 0 2006.224.08:09:20.83#ibcon#read 5, iclass 22, count 0 2006.224.08:09:20.83#ibcon#about to read 6, iclass 22, count 0 2006.224.08:09:20.83#ibcon#read 6, iclass 22, count 0 2006.224.08:09:20.83#ibcon#end of sib2, iclass 22, count 0 2006.224.08:09:20.83#ibcon#*after write, iclass 22, count 0 2006.224.08:09:20.83#ibcon#*before return 0, iclass 22, count 0 2006.224.08:09:20.83#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.224.08:09:20.83#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.224.08:09:20.83#ibcon#about to clear, iclass 22 cls_cnt 0 2006.224.08:09:20.83#ibcon#cleared, iclass 22 cls_cnt 0 2006.224.08:09:20.83$vc4f8/vblo=2,640.99 2006.224.08:09:20.83#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.224.08:09:20.83#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.224.08:09:20.83#ibcon#ireg 17 cls_cnt 0 2006.224.08:09:20.83#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.224.08:09:20.83#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.224.08:09:20.83#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.224.08:09:20.83#ibcon#enter wrdev, iclass 24, count 0 2006.224.08:09:20.83#ibcon#first serial, iclass 24, count 0 2006.224.08:09:20.83#ibcon#enter sib2, iclass 24, count 0 2006.224.08:09:20.83#ibcon#flushed, iclass 24, count 0 2006.224.08:09:20.83#ibcon#about to write, iclass 24, count 0 2006.224.08:09:20.83#ibcon#wrote, iclass 24, count 0 2006.224.08:09:20.83#ibcon#about to read 3, iclass 24, count 0 2006.224.08:09:20.85#ibcon#read 3, iclass 24, count 0 2006.224.08:09:20.85#ibcon#about to read 4, iclass 24, count 0 2006.224.08:09:20.85#ibcon#read 4, iclass 24, count 0 2006.224.08:09:20.85#ibcon#about to read 5, iclass 24, count 0 2006.224.08:09:20.85#ibcon#read 5, iclass 24, count 0 2006.224.08:09:20.85#ibcon#about to read 6, iclass 24, count 0 2006.224.08:09:20.85#ibcon#read 6, iclass 24, count 0 2006.224.08:09:20.85#ibcon#end of sib2, iclass 24, count 0 2006.224.08:09:20.85#ibcon#*mode == 0, iclass 24, count 0 2006.224.08:09:20.85#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.224.08:09:20.85#ibcon#[28=FRQ=02,640.99\r\n] 2006.224.08:09:20.85#ibcon#*before write, iclass 24, count 0 2006.224.08:09:20.85#ibcon#enter sib2, iclass 24, count 0 2006.224.08:09:20.85#ibcon#flushed, iclass 24, count 0 2006.224.08:09:20.85#ibcon#about to write, iclass 24, count 0 2006.224.08:09:20.85#ibcon#wrote, iclass 24, count 0 2006.224.08:09:20.85#ibcon#about to read 3, iclass 24, count 0 2006.224.08:09:20.89#ibcon#read 3, iclass 24, count 0 2006.224.08:09:20.89#ibcon#about to read 4, iclass 24, count 0 2006.224.08:09:20.89#ibcon#read 4, iclass 24, count 0 2006.224.08:09:20.89#ibcon#about to read 5, iclass 24, count 0 2006.224.08:09:20.89#ibcon#read 5, iclass 24, count 0 2006.224.08:09:20.89#ibcon#about to read 6, iclass 24, count 0 2006.224.08:09:20.89#ibcon#read 6, iclass 24, count 0 2006.224.08:09:20.89#ibcon#end of sib2, iclass 24, count 0 2006.224.08:09:20.89#ibcon#*after write, iclass 24, count 0 2006.224.08:09:20.89#ibcon#*before return 0, iclass 24, count 0 2006.224.08:09:20.89#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.224.08:09:20.89#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.224.08:09:20.89#ibcon#about to clear, iclass 24 cls_cnt 0 2006.224.08:09:20.89#ibcon#cleared, iclass 24 cls_cnt 0 2006.224.08:09:20.89$vc4f8/vb=2,4 2006.224.08:09:20.89#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.224.08:09:20.89#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.224.08:09:20.89#ibcon#ireg 11 cls_cnt 2 2006.224.08:09:20.89#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.224.08:09:20.95#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.224.08:09:20.95#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.224.08:09:20.95#ibcon#enter wrdev, iclass 26, count 2 2006.224.08:09:20.95#ibcon#first serial, iclass 26, count 2 2006.224.08:09:20.95#ibcon#enter sib2, iclass 26, count 2 2006.224.08:09:20.95#ibcon#flushed, iclass 26, count 2 2006.224.08:09:20.95#ibcon#about to write, iclass 26, count 2 2006.224.08:09:20.95#ibcon#wrote, iclass 26, count 2 2006.224.08:09:20.95#ibcon#about to read 3, iclass 26, count 2 2006.224.08:09:20.97#ibcon#read 3, iclass 26, count 2 2006.224.08:09:20.97#ibcon#about to read 4, iclass 26, count 2 2006.224.08:09:20.97#ibcon#read 4, iclass 26, count 2 2006.224.08:09:20.97#ibcon#about to read 5, iclass 26, count 2 2006.224.08:09:20.97#ibcon#read 5, iclass 26, count 2 2006.224.08:09:20.97#ibcon#about to read 6, iclass 26, count 2 2006.224.08:09:20.97#ibcon#read 6, iclass 26, count 2 2006.224.08:09:20.97#ibcon#end of sib2, iclass 26, count 2 2006.224.08:09:20.97#ibcon#*mode == 0, iclass 26, count 2 2006.224.08:09:20.97#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.224.08:09:20.97#ibcon#[27=AT02-04\r\n] 2006.224.08:09:20.97#ibcon#*before write, iclass 26, count 2 2006.224.08:09:20.97#ibcon#enter sib2, iclass 26, count 2 2006.224.08:09:20.97#ibcon#flushed, iclass 26, count 2 2006.224.08:09:20.97#ibcon#about to write, iclass 26, count 2 2006.224.08:09:20.97#ibcon#wrote, iclass 26, count 2 2006.224.08:09:20.97#ibcon#about to read 3, iclass 26, count 2 2006.224.08:09:21.00#ibcon#read 3, iclass 26, count 2 2006.224.08:09:21.00#ibcon#about to read 4, iclass 26, count 2 2006.224.08:09:21.00#ibcon#read 4, iclass 26, count 2 2006.224.08:09:21.00#ibcon#about to read 5, iclass 26, count 2 2006.224.08:09:21.00#ibcon#read 5, iclass 26, count 2 2006.224.08:09:21.00#ibcon#about to read 6, iclass 26, count 2 2006.224.08:09:21.00#ibcon#read 6, iclass 26, count 2 2006.224.08:09:21.00#ibcon#end of sib2, iclass 26, count 2 2006.224.08:09:21.00#ibcon#*after write, iclass 26, count 2 2006.224.08:09:21.00#ibcon#*before return 0, iclass 26, count 2 2006.224.08:09:21.00#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.224.08:09:21.00#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.224.08:09:21.00#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.224.08:09:21.00#ibcon#ireg 7 cls_cnt 0 2006.224.08:09:21.00#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.224.08:09:21.12#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.224.08:09:21.12#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.224.08:09:21.12#ibcon#enter wrdev, iclass 26, count 0 2006.224.08:09:21.12#ibcon#first serial, iclass 26, count 0 2006.224.08:09:21.12#ibcon#enter sib2, iclass 26, count 0 2006.224.08:09:21.12#ibcon#flushed, iclass 26, count 0 2006.224.08:09:21.12#ibcon#about to write, iclass 26, count 0 2006.224.08:09:21.12#ibcon#wrote, iclass 26, count 0 2006.224.08:09:21.12#ibcon#about to read 3, iclass 26, count 0 2006.224.08:09:21.14#ibcon#read 3, iclass 26, count 0 2006.224.08:09:21.14#ibcon#about to read 4, iclass 26, count 0 2006.224.08:09:21.14#ibcon#read 4, iclass 26, count 0 2006.224.08:09:21.14#ibcon#about to read 5, iclass 26, count 0 2006.224.08:09:21.14#ibcon#read 5, iclass 26, count 0 2006.224.08:09:21.14#ibcon#about to read 6, iclass 26, count 0 2006.224.08:09:21.14#ibcon#read 6, iclass 26, count 0 2006.224.08:09:21.14#ibcon#end of sib2, iclass 26, count 0 2006.224.08:09:21.14#ibcon#*mode == 0, iclass 26, count 0 2006.224.08:09:21.14#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.224.08:09:21.14#ibcon#[27=USB\r\n] 2006.224.08:09:21.14#ibcon#*before write, iclass 26, count 0 2006.224.08:09:21.14#ibcon#enter sib2, iclass 26, count 0 2006.224.08:09:21.14#ibcon#flushed, iclass 26, count 0 2006.224.08:09:21.14#ibcon#about to write, iclass 26, count 0 2006.224.08:09:21.14#ibcon#wrote, iclass 26, count 0 2006.224.08:09:21.14#ibcon#about to read 3, iclass 26, count 0 2006.224.08:09:21.17#ibcon#read 3, iclass 26, count 0 2006.224.08:09:21.17#ibcon#about to read 4, iclass 26, count 0 2006.224.08:09:21.17#ibcon#read 4, iclass 26, count 0 2006.224.08:09:21.17#ibcon#about to read 5, iclass 26, count 0 2006.224.08:09:21.17#ibcon#read 5, iclass 26, count 0 2006.224.08:09:21.17#ibcon#about to read 6, iclass 26, count 0 2006.224.08:09:21.17#ibcon#read 6, iclass 26, count 0 2006.224.08:09:21.17#ibcon#end of sib2, iclass 26, count 0 2006.224.08:09:21.17#ibcon#*after write, iclass 26, count 0 2006.224.08:09:21.17#ibcon#*before return 0, iclass 26, count 0 2006.224.08:09:21.17#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.224.08:09:21.17#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.224.08:09:21.17#ibcon#about to clear, iclass 26 cls_cnt 0 2006.224.08:09:21.17#ibcon#cleared, iclass 26 cls_cnt 0 2006.224.08:09:21.17$vc4f8/vblo=3,656.99 2006.224.08:09:21.17#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.224.08:09:21.17#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.224.08:09:21.17#ibcon#ireg 17 cls_cnt 0 2006.224.08:09:21.17#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.224.08:09:21.17#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.224.08:09:21.17#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.224.08:09:21.17#ibcon#enter wrdev, iclass 28, count 0 2006.224.08:09:21.17#ibcon#first serial, iclass 28, count 0 2006.224.08:09:21.17#ibcon#enter sib2, iclass 28, count 0 2006.224.08:09:21.17#ibcon#flushed, iclass 28, count 0 2006.224.08:09:21.17#ibcon#about to write, iclass 28, count 0 2006.224.08:09:21.17#ibcon#wrote, iclass 28, count 0 2006.224.08:09:21.17#ibcon#about to read 3, iclass 28, count 0 2006.224.08:09:21.19#ibcon#read 3, iclass 28, count 0 2006.224.08:09:21.19#ibcon#about to read 4, iclass 28, count 0 2006.224.08:09:21.19#ibcon#read 4, iclass 28, count 0 2006.224.08:09:21.19#ibcon#about to read 5, iclass 28, count 0 2006.224.08:09:21.19#ibcon#read 5, iclass 28, count 0 2006.224.08:09:21.19#ibcon#about to read 6, iclass 28, count 0 2006.224.08:09:21.19#ibcon#read 6, iclass 28, count 0 2006.224.08:09:21.19#ibcon#end of sib2, iclass 28, count 0 2006.224.08:09:21.19#ibcon#*mode == 0, iclass 28, count 0 2006.224.08:09:21.19#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.224.08:09:21.19#ibcon#[28=FRQ=03,656.99\r\n] 2006.224.08:09:21.19#ibcon#*before write, iclass 28, count 0 2006.224.08:09:21.19#ibcon#enter sib2, iclass 28, count 0 2006.224.08:09:21.19#ibcon#flushed, iclass 28, count 0 2006.224.08:09:21.19#ibcon#about to write, iclass 28, count 0 2006.224.08:09:21.19#ibcon#wrote, iclass 28, count 0 2006.224.08:09:21.19#ibcon#about to read 3, iclass 28, count 0 2006.224.08:09:21.23#ibcon#read 3, iclass 28, count 0 2006.224.08:09:21.23#ibcon#about to read 4, iclass 28, count 0 2006.224.08:09:21.23#ibcon#read 4, iclass 28, count 0 2006.224.08:09:21.23#ibcon#about to read 5, iclass 28, count 0 2006.224.08:09:21.23#ibcon#read 5, iclass 28, count 0 2006.224.08:09:21.23#ibcon#about to read 6, iclass 28, count 0 2006.224.08:09:21.23#ibcon#read 6, iclass 28, count 0 2006.224.08:09:21.23#ibcon#end of sib2, iclass 28, count 0 2006.224.08:09:21.23#ibcon#*after write, iclass 28, count 0 2006.224.08:09:21.23#ibcon#*before return 0, iclass 28, count 0 2006.224.08:09:21.23#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.224.08:09:21.23#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.224.08:09:21.23#ibcon#about to clear, iclass 28 cls_cnt 0 2006.224.08:09:21.23#ibcon#cleared, iclass 28 cls_cnt 0 2006.224.08:09:21.23$vc4f8/vb=3,4 2006.224.08:09:21.23#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.224.08:09:21.23#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.224.08:09:21.23#ibcon#ireg 11 cls_cnt 2 2006.224.08:09:21.23#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.224.08:09:21.29#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.224.08:09:21.29#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.224.08:09:21.29#ibcon#enter wrdev, iclass 30, count 2 2006.224.08:09:21.29#ibcon#first serial, iclass 30, count 2 2006.224.08:09:21.29#ibcon#enter sib2, iclass 30, count 2 2006.224.08:09:21.29#ibcon#flushed, iclass 30, count 2 2006.224.08:09:21.29#ibcon#about to write, iclass 30, count 2 2006.224.08:09:21.29#ibcon#wrote, iclass 30, count 2 2006.224.08:09:21.29#ibcon#about to read 3, iclass 30, count 2 2006.224.08:09:21.31#ibcon#read 3, iclass 30, count 2 2006.224.08:09:21.31#ibcon#about to read 4, iclass 30, count 2 2006.224.08:09:21.31#ibcon#read 4, iclass 30, count 2 2006.224.08:09:21.31#ibcon#about to read 5, iclass 30, count 2 2006.224.08:09:21.31#ibcon#read 5, iclass 30, count 2 2006.224.08:09:21.31#ibcon#about to read 6, iclass 30, count 2 2006.224.08:09:21.31#ibcon#read 6, iclass 30, count 2 2006.224.08:09:21.31#ibcon#end of sib2, iclass 30, count 2 2006.224.08:09:21.31#ibcon#*mode == 0, iclass 30, count 2 2006.224.08:09:21.31#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.224.08:09:21.31#ibcon#[27=AT03-04\r\n] 2006.224.08:09:21.31#ibcon#*before write, iclass 30, count 2 2006.224.08:09:21.31#ibcon#enter sib2, iclass 30, count 2 2006.224.08:09:21.31#ibcon#flushed, iclass 30, count 2 2006.224.08:09:21.31#ibcon#about to write, iclass 30, count 2 2006.224.08:09:21.31#ibcon#wrote, iclass 30, count 2 2006.224.08:09:21.31#ibcon#about to read 3, iclass 30, count 2 2006.224.08:09:21.34#ibcon#read 3, iclass 30, count 2 2006.224.08:09:21.34#ibcon#about to read 4, iclass 30, count 2 2006.224.08:09:21.34#ibcon#read 4, iclass 30, count 2 2006.224.08:09:21.34#ibcon#about to read 5, iclass 30, count 2 2006.224.08:09:21.34#ibcon#read 5, iclass 30, count 2 2006.224.08:09:21.34#ibcon#about to read 6, iclass 30, count 2 2006.224.08:09:21.34#ibcon#read 6, iclass 30, count 2 2006.224.08:09:21.34#ibcon#end of sib2, iclass 30, count 2 2006.224.08:09:21.34#ibcon#*after write, iclass 30, count 2 2006.224.08:09:21.34#ibcon#*before return 0, iclass 30, count 2 2006.224.08:09:21.34#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.224.08:09:21.34#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.224.08:09:21.34#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.224.08:09:21.34#ibcon#ireg 7 cls_cnt 0 2006.224.08:09:21.34#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.224.08:09:21.46#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.224.08:09:21.46#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.224.08:09:21.46#ibcon#enter wrdev, iclass 30, count 0 2006.224.08:09:21.46#ibcon#first serial, iclass 30, count 0 2006.224.08:09:21.46#ibcon#enter sib2, iclass 30, count 0 2006.224.08:09:21.46#ibcon#flushed, iclass 30, count 0 2006.224.08:09:21.46#ibcon#about to write, iclass 30, count 0 2006.224.08:09:21.46#ibcon#wrote, iclass 30, count 0 2006.224.08:09:21.46#ibcon#about to read 3, iclass 30, count 0 2006.224.08:09:21.48#ibcon#read 3, iclass 30, count 0 2006.224.08:09:21.48#ibcon#about to read 4, iclass 30, count 0 2006.224.08:09:21.48#ibcon#read 4, iclass 30, count 0 2006.224.08:09:21.48#ibcon#about to read 5, iclass 30, count 0 2006.224.08:09:21.48#ibcon#read 5, iclass 30, count 0 2006.224.08:09:21.48#ibcon#about to read 6, iclass 30, count 0 2006.224.08:09:21.48#ibcon#read 6, iclass 30, count 0 2006.224.08:09:21.48#ibcon#end of sib2, iclass 30, count 0 2006.224.08:09:21.48#ibcon#*mode == 0, iclass 30, count 0 2006.224.08:09:21.48#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.224.08:09:21.48#ibcon#[27=USB\r\n] 2006.224.08:09:21.48#ibcon#*before write, iclass 30, count 0 2006.224.08:09:21.48#ibcon#enter sib2, iclass 30, count 0 2006.224.08:09:21.48#ibcon#flushed, iclass 30, count 0 2006.224.08:09:21.48#ibcon#about to write, iclass 30, count 0 2006.224.08:09:21.48#ibcon#wrote, iclass 30, count 0 2006.224.08:09:21.48#ibcon#about to read 3, iclass 30, count 0 2006.224.08:09:21.51#ibcon#read 3, iclass 30, count 0 2006.224.08:09:21.51#ibcon#about to read 4, iclass 30, count 0 2006.224.08:09:21.51#ibcon#read 4, iclass 30, count 0 2006.224.08:09:21.51#ibcon#about to read 5, iclass 30, count 0 2006.224.08:09:21.51#ibcon#read 5, iclass 30, count 0 2006.224.08:09:21.51#ibcon#about to read 6, iclass 30, count 0 2006.224.08:09:21.51#ibcon#read 6, iclass 30, count 0 2006.224.08:09:21.51#ibcon#end of sib2, iclass 30, count 0 2006.224.08:09:21.51#ibcon#*after write, iclass 30, count 0 2006.224.08:09:21.51#ibcon#*before return 0, iclass 30, count 0 2006.224.08:09:21.51#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.224.08:09:21.51#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.224.08:09:21.51#ibcon#about to clear, iclass 30 cls_cnt 0 2006.224.08:09:21.51#ibcon#cleared, iclass 30 cls_cnt 0 2006.224.08:09:21.51$vc4f8/vblo=4,712.99 2006.224.08:09:21.51#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.224.08:09:21.51#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.224.08:09:21.51#ibcon#ireg 17 cls_cnt 0 2006.224.08:09:21.51#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.224.08:09:21.51#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.224.08:09:21.51#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.224.08:09:21.51#ibcon#enter wrdev, iclass 32, count 0 2006.224.08:09:21.51#ibcon#first serial, iclass 32, count 0 2006.224.08:09:21.51#ibcon#enter sib2, iclass 32, count 0 2006.224.08:09:21.51#ibcon#flushed, iclass 32, count 0 2006.224.08:09:21.51#ibcon#about to write, iclass 32, count 0 2006.224.08:09:21.51#ibcon#wrote, iclass 32, count 0 2006.224.08:09:21.51#ibcon#about to read 3, iclass 32, count 0 2006.224.08:09:21.53#ibcon#read 3, iclass 32, count 0 2006.224.08:09:21.53#ibcon#about to read 4, iclass 32, count 0 2006.224.08:09:21.53#ibcon#read 4, iclass 32, count 0 2006.224.08:09:21.53#ibcon#about to read 5, iclass 32, count 0 2006.224.08:09:21.53#ibcon#read 5, iclass 32, count 0 2006.224.08:09:21.53#ibcon#about to read 6, iclass 32, count 0 2006.224.08:09:21.53#ibcon#read 6, iclass 32, count 0 2006.224.08:09:21.53#ibcon#end of sib2, iclass 32, count 0 2006.224.08:09:21.53#ibcon#*mode == 0, iclass 32, count 0 2006.224.08:09:21.53#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.224.08:09:21.53#ibcon#[28=FRQ=04,712.99\r\n] 2006.224.08:09:21.53#ibcon#*before write, iclass 32, count 0 2006.224.08:09:21.53#ibcon#enter sib2, iclass 32, count 0 2006.224.08:09:21.53#ibcon#flushed, iclass 32, count 0 2006.224.08:09:21.53#ibcon#about to write, iclass 32, count 0 2006.224.08:09:21.53#ibcon#wrote, iclass 32, count 0 2006.224.08:09:21.53#ibcon#about to read 3, iclass 32, count 0 2006.224.08:09:21.57#ibcon#read 3, iclass 32, count 0 2006.224.08:09:21.57#ibcon#about to read 4, iclass 32, count 0 2006.224.08:09:21.57#ibcon#read 4, iclass 32, count 0 2006.224.08:09:21.57#ibcon#about to read 5, iclass 32, count 0 2006.224.08:09:21.57#ibcon#read 5, iclass 32, count 0 2006.224.08:09:21.57#ibcon#about to read 6, iclass 32, count 0 2006.224.08:09:21.57#ibcon#read 6, iclass 32, count 0 2006.224.08:09:21.57#ibcon#end of sib2, iclass 32, count 0 2006.224.08:09:21.57#ibcon#*after write, iclass 32, count 0 2006.224.08:09:21.57#ibcon#*before return 0, iclass 32, count 0 2006.224.08:09:21.57#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.224.08:09:21.57#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.224.08:09:21.57#ibcon#about to clear, iclass 32 cls_cnt 0 2006.224.08:09:21.57#ibcon#cleared, iclass 32 cls_cnt 0 2006.224.08:09:21.57$vc4f8/vb=4,4 2006.224.08:09:21.57#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.224.08:09:21.57#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.224.08:09:21.57#ibcon#ireg 11 cls_cnt 2 2006.224.08:09:21.57#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.224.08:09:21.63#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.224.08:09:21.63#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.224.08:09:21.63#ibcon#enter wrdev, iclass 34, count 2 2006.224.08:09:21.63#ibcon#first serial, iclass 34, count 2 2006.224.08:09:21.63#ibcon#enter sib2, iclass 34, count 2 2006.224.08:09:21.63#ibcon#flushed, iclass 34, count 2 2006.224.08:09:21.63#ibcon#about to write, iclass 34, count 2 2006.224.08:09:21.63#ibcon#wrote, iclass 34, count 2 2006.224.08:09:21.63#ibcon#about to read 3, iclass 34, count 2 2006.224.08:09:21.65#ibcon#read 3, iclass 34, count 2 2006.224.08:09:21.65#ibcon#about to read 4, iclass 34, count 2 2006.224.08:09:21.65#ibcon#read 4, iclass 34, count 2 2006.224.08:09:21.65#ibcon#about to read 5, iclass 34, count 2 2006.224.08:09:21.65#ibcon#read 5, iclass 34, count 2 2006.224.08:09:21.65#ibcon#about to read 6, iclass 34, count 2 2006.224.08:09:21.65#ibcon#read 6, iclass 34, count 2 2006.224.08:09:21.65#ibcon#end of sib2, iclass 34, count 2 2006.224.08:09:21.65#ibcon#*mode == 0, iclass 34, count 2 2006.224.08:09:21.65#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.224.08:09:21.65#ibcon#[27=AT04-04\r\n] 2006.224.08:09:21.65#ibcon#*before write, iclass 34, count 2 2006.224.08:09:21.65#ibcon#enter sib2, iclass 34, count 2 2006.224.08:09:21.65#ibcon#flushed, iclass 34, count 2 2006.224.08:09:21.65#ibcon#about to write, iclass 34, count 2 2006.224.08:09:21.65#ibcon#wrote, iclass 34, count 2 2006.224.08:09:21.65#ibcon#about to read 3, iclass 34, count 2 2006.224.08:09:21.68#ibcon#read 3, iclass 34, count 2 2006.224.08:09:21.68#ibcon#about to read 4, iclass 34, count 2 2006.224.08:09:21.68#ibcon#read 4, iclass 34, count 2 2006.224.08:09:21.68#ibcon#about to read 5, iclass 34, count 2 2006.224.08:09:21.68#ibcon#read 5, iclass 34, count 2 2006.224.08:09:21.68#ibcon#about to read 6, iclass 34, count 2 2006.224.08:09:21.68#ibcon#read 6, iclass 34, count 2 2006.224.08:09:21.68#ibcon#end of sib2, iclass 34, count 2 2006.224.08:09:21.68#ibcon#*after write, iclass 34, count 2 2006.224.08:09:21.68#ibcon#*before return 0, iclass 34, count 2 2006.224.08:09:21.68#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.224.08:09:21.68#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.224.08:09:21.68#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.224.08:09:21.68#ibcon#ireg 7 cls_cnt 0 2006.224.08:09:21.68#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.224.08:09:21.80#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.224.08:09:21.80#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.224.08:09:21.80#ibcon#enter wrdev, iclass 34, count 0 2006.224.08:09:21.80#ibcon#first serial, iclass 34, count 0 2006.224.08:09:21.80#ibcon#enter sib2, iclass 34, count 0 2006.224.08:09:21.80#ibcon#flushed, iclass 34, count 0 2006.224.08:09:21.80#ibcon#about to write, iclass 34, count 0 2006.224.08:09:21.80#ibcon#wrote, iclass 34, count 0 2006.224.08:09:21.80#ibcon#about to read 3, iclass 34, count 0 2006.224.08:09:21.82#ibcon#read 3, iclass 34, count 0 2006.224.08:09:21.82#ibcon#about to read 4, iclass 34, count 0 2006.224.08:09:21.82#ibcon#read 4, iclass 34, count 0 2006.224.08:09:21.82#ibcon#about to read 5, iclass 34, count 0 2006.224.08:09:21.82#ibcon#read 5, iclass 34, count 0 2006.224.08:09:21.82#ibcon#about to read 6, iclass 34, count 0 2006.224.08:09:21.82#ibcon#read 6, iclass 34, count 0 2006.224.08:09:21.82#ibcon#end of sib2, iclass 34, count 0 2006.224.08:09:21.82#ibcon#*mode == 0, iclass 34, count 0 2006.224.08:09:21.82#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.224.08:09:21.82#ibcon#[27=USB\r\n] 2006.224.08:09:21.82#ibcon#*before write, iclass 34, count 0 2006.224.08:09:21.82#ibcon#enter sib2, iclass 34, count 0 2006.224.08:09:21.82#ibcon#flushed, iclass 34, count 0 2006.224.08:09:21.82#ibcon#about to write, iclass 34, count 0 2006.224.08:09:21.82#ibcon#wrote, iclass 34, count 0 2006.224.08:09:21.82#ibcon#about to read 3, iclass 34, count 0 2006.224.08:09:21.85#ibcon#read 3, iclass 34, count 0 2006.224.08:09:21.85#ibcon#about to read 4, iclass 34, count 0 2006.224.08:09:21.85#ibcon#read 4, iclass 34, count 0 2006.224.08:09:21.85#ibcon#about to read 5, iclass 34, count 0 2006.224.08:09:21.85#ibcon#read 5, iclass 34, count 0 2006.224.08:09:21.85#ibcon#about to read 6, iclass 34, count 0 2006.224.08:09:21.85#ibcon#read 6, iclass 34, count 0 2006.224.08:09:21.85#ibcon#end of sib2, iclass 34, count 0 2006.224.08:09:21.85#ibcon#*after write, iclass 34, count 0 2006.224.08:09:21.85#ibcon#*before return 0, iclass 34, count 0 2006.224.08:09:21.85#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.224.08:09:21.85#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.224.08:09:21.85#ibcon#about to clear, iclass 34 cls_cnt 0 2006.224.08:09:21.85#ibcon#cleared, iclass 34 cls_cnt 0 2006.224.08:09:21.85$vc4f8/vblo=5,744.99 2006.224.08:09:21.85#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.224.08:09:21.85#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.224.08:09:21.85#ibcon#ireg 17 cls_cnt 0 2006.224.08:09:21.85#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.224.08:09:21.85#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.224.08:09:21.85#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.224.08:09:21.85#ibcon#enter wrdev, iclass 36, count 0 2006.224.08:09:21.85#ibcon#first serial, iclass 36, count 0 2006.224.08:09:21.85#ibcon#enter sib2, iclass 36, count 0 2006.224.08:09:21.85#ibcon#flushed, iclass 36, count 0 2006.224.08:09:21.85#ibcon#about to write, iclass 36, count 0 2006.224.08:09:21.85#ibcon#wrote, iclass 36, count 0 2006.224.08:09:21.85#ibcon#about to read 3, iclass 36, count 0 2006.224.08:09:21.87#ibcon#read 3, iclass 36, count 0 2006.224.08:09:21.87#ibcon#about to read 4, iclass 36, count 0 2006.224.08:09:21.87#ibcon#read 4, iclass 36, count 0 2006.224.08:09:21.87#ibcon#about to read 5, iclass 36, count 0 2006.224.08:09:21.87#ibcon#read 5, iclass 36, count 0 2006.224.08:09:21.87#ibcon#about to read 6, iclass 36, count 0 2006.224.08:09:21.87#ibcon#read 6, iclass 36, count 0 2006.224.08:09:21.87#ibcon#end of sib2, iclass 36, count 0 2006.224.08:09:21.87#ibcon#*mode == 0, iclass 36, count 0 2006.224.08:09:21.87#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.224.08:09:21.87#ibcon#[28=FRQ=05,744.99\r\n] 2006.224.08:09:21.87#ibcon#*before write, iclass 36, count 0 2006.224.08:09:21.87#ibcon#enter sib2, iclass 36, count 0 2006.224.08:09:21.87#ibcon#flushed, iclass 36, count 0 2006.224.08:09:21.87#ibcon#about to write, iclass 36, count 0 2006.224.08:09:21.87#ibcon#wrote, iclass 36, count 0 2006.224.08:09:21.87#ibcon#about to read 3, iclass 36, count 0 2006.224.08:09:21.91#ibcon#read 3, iclass 36, count 0 2006.224.08:09:21.91#ibcon#about to read 4, iclass 36, count 0 2006.224.08:09:21.91#ibcon#read 4, iclass 36, count 0 2006.224.08:09:21.91#ibcon#about to read 5, iclass 36, count 0 2006.224.08:09:21.91#ibcon#read 5, iclass 36, count 0 2006.224.08:09:21.91#ibcon#about to read 6, iclass 36, count 0 2006.224.08:09:21.91#ibcon#read 6, iclass 36, count 0 2006.224.08:09:21.91#ibcon#end of sib2, iclass 36, count 0 2006.224.08:09:21.91#ibcon#*after write, iclass 36, count 0 2006.224.08:09:21.91#ibcon#*before return 0, iclass 36, count 0 2006.224.08:09:21.91#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.224.08:09:21.91#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.224.08:09:21.91#ibcon#about to clear, iclass 36 cls_cnt 0 2006.224.08:09:21.91#ibcon#cleared, iclass 36 cls_cnt 0 2006.224.08:09:21.91$vc4f8/vb=5,4 2006.224.08:09:21.91#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.224.08:09:21.91#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.224.08:09:21.91#ibcon#ireg 11 cls_cnt 2 2006.224.08:09:21.91#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.224.08:09:21.97#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.224.08:09:21.97#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.224.08:09:21.97#ibcon#enter wrdev, iclass 38, count 2 2006.224.08:09:21.97#ibcon#first serial, iclass 38, count 2 2006.224.08:09:21.97#ibcon#enter sib2, iclass 38, count 2 2006.224.08:09:21.97#ibcon#flushed, iclass 38, count 2 2006.224.08:09:21.97#ibcon#about to write, iclass 38, count 2 2006.224.08:09:21.97#ibcon#wrote, iclass 38, count 2 2006.224.08:09:21.97#ibcon#about to read 3, iclass 38, count 2 2006.224.08:09:21.99#ibcon#read 3, iclass 38, count 2 2006.224.08:09:21.99#ibcon#about to read 4, iclass 38, count 2 2006.224.08:09:21.99#ibcon#read 4, iclass 38, count 2 2006.224.08:09:21.99#ibcon#about to read 5, iclass 38, count 2 2006.224.08:09:21.99#ibcon#read 5, iclass 38, count 2 2006.224.08:09:21.99#ibcon#about to read 6, iclass 38, count 2 2006.224.08:09:21.99#ibcon#read 6, iclass 38, count 2 2006.224.08:09:21.99#ibcon#end of sib2, iclass 38, count 2 2006.224.08:09:21.99#ibcon#*mode == 0, iclass 38, count 2 2006.224.08:09:21.99#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.224.08:09:21.99#ibcon#[27=AT05-04\r\n] 2006.224.08:09:21.99#ibcon#*before write, iclass 38, count 2 2006.224.08:09:21.99#ibcon#enter sib2, iclass 38, count 2 2006.224.08:09:21.99#ibcon#flushed, iclass 38, count 2 2006.224.08:09:21.99#ibcon#about to write, iclass 38, count 2 2006.224.08:09:21.99#ibcon#wrote, iclass 38, count 2 2006.224.08:09:21.99#ibcon#about to read 3, iclass 38, count 2 2006.224.08:09:22.02#ibcon#read 3, iclass 38, count 2 2006.224.08:09:22.02#ibcon#about to read 4, iclass 38, count 2 2006.224.08:09:22.02#ibcon#read 4, iclass 38, count 2 2006.224.08:09:22.02#ibcon#about to read 5, iclass 38, count 2 2006.224.08:09:22.02#ibcon#read 5, iclass 38, count 2 2006.224.08:09:22.02#ibcon#about to read 6, iclass 38, count 2 2006.224.08:09:22.02#ibcon#read 6, iclass 38, count 2 2006.224.08:09:22.02#ibcon#end of sib2, iclass 38, count 2 2006.224.08:09:22.02#ibcon#*after write, iclass 38, count 2 2006.224.08:09:22.02#ibcon#*before return 0, iclass 38, count 2 2006.224.08:09:22.02#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.224.08:09:22.02#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.224.08:09:22.02#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.224.08:09:22.02#ibcon#ireg 7 cls_cnt 0 2006.224.08:09:22.02#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.224.08:09:22.14#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.224.08:09:22.14#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.224.08:09:22.14#ibcon#enter wrdev, iclass 38, count 0 2006.224.08:09:22.14#ibcon#first serial, iclass 38, count 0 2006.224.08:09:22.14#ibcon#enter sib2, iclass 38, count 0 2006.224.08:09:22.14#ibcon#flushed, iclass 38, count 0 2006.224.08:09:22.14#ibcon#about to write, iclass 38, count 0 2006.224.08:09:22.14#ibcon#wrote, iclass 38, count 0 2006.224.08:09:22.14#ibcon#about to read 3, iclass 38, count 0 2006.224.08:09:22.16#ibcon#read 3, iclass 38, count 0 2006.224.08:09:22.16#ibcon#about to read 4, iclass 38, count 0 2006.224.08:09:22.16#ibcon#read 4, iclass 38, count 0 2006.224.08:09:22.16#ibcon#about to read 5, iclass 38, count 0 2006.224.08:09:22.16#ibcon#read 5, iclass 38, count 0 2006.224.08:09:22.16#ibcon#about to read 6, iclass 38, count 0 2006.224.08:09:22.16#ibcon#read 6, iclass 38, count 0 2006.224.08:09:22.16#ibcon#end of sib2, iclass 38, count 0 2006.224.08:09:22.16#ibcon#*mode == 0, iclass 38, count 0 2006.224.08:09:22.16#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.224.08:09:22.16#ibcon#[27=USB\r\n] 2006.224.08:09:22.16#ibcon#*before write, iclass 38, count 0 2006.224.08:09:22.16#ibcon#enter sib2, iclass 38, count 0 2006.224.08:09:22.16#ibcon#flushed, iclass 38, count 0 2006.224.08:09:22.16#ibcon#about to write, iclass 38, count 0 2006.224.08:09:22.16#ibcon#wrote, iclass 38, count 0 2006.224.08:09:22.16#ibcon#about to read 3, iclass 38, count 0 2006.224.08:09:22.19#ibcon#read 3, iclass 38, count 0 2006.224.08:09:22.19#ibcon#about to read 4, iclass 38, count 0 2006.224.08:09:22.19#ibcon#read 4, iclass 38, count 0 2006.224.08:09:22.19#ibcon#about to read 5, iclass 38, count 0 2006.224.08:09:22.19#ibcon#read 5, iclass 38, count 0 2006.224.08:09:22.19#ibcon#about to read 6, iclass 38, count 0 2006.224.08:09:22.19#ibcon#read 6, iclass 38, count 0 2006.224.08:09:22.19#ibcon#end of sib2, iclass 38, count 0 2006.224.08:09:22.19#ibcon#*after write, iclass 38, count 0 2006.224.08:09:22.19#ibcon#*before return 0, iclass 38, count 0 2006.224.08:09:22.19#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.224.08:09:22.19#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.224.08:09:22.19#ibcon#about to clear, iclass 38 cls_cnt 0 2006.224.08:09:22.19#ibcon#cleared, iclass 38 cls_cnt 0 2006.224.08:09:22.19$vc4f8/vblo=6,752.99 2006.224.08:09:22.19#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.224.08:09:22.19#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.224.08:09:22.19#ibcon#ireg 17 cls_cnt 0 2006.224.08:09:22.19#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.224.08:09:22.19#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.224.08:09:22.19#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.224.08:09:22.19#ibcon#enter wrdev, iclass 40, count 0 2006.224.08:09:22.19#ibcon#first serial, iclass 40, count 0 2006.224.08:09:22.19#ibcon#enter sib2, iclass 40, count 0 2006.224.08:09:22.19#ibcon#flushed, iclass 40, count 0 2006.224.08:09:22.19#ibcon#about to write, iclass 40, count 0 2006.224.08:09:22.19#ibcon#wrote, iclass 40, count 0 2006.224.08:09:22.19#ibcon#about to read 3, iclass 40, count 0 2006.224.08:09:22.21#ibcon#read 3, iclass 40, count 0 2006.224.08:09:22.21#ibcon#about to read 4, iclass 40, count 0 2006.224.08:09:22.21#ibcon#read 4, iclass 40, count 0 2006.224.08:09:22.21#ibcon#about to read 5, iclass 40, count 0 2006.224.08:09:22.21#ibcon#read 5, iclass 40, count 0 2006.224.08:09:22.21#ibcon#about to read 6, iclass 40, count 0 2006.224.08:09:22.21#ibcon#read 6, iclass 40, count 0 2006.224.08:09:22.21#ibcon#end of sib2, iclass 40, count 0 2006.224.08:09:22.21#ibcon#*mode == 0, iclass 40, count 0 2006.224.08:09:22.21#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.224.08:09:22.21#ibcon#[28=FRQ=06,752.99\r\n] 2006.224.08:09:22.21#ibcon#*before write, iclass 40, count 0 2006.224.08:09:22.21#ibcon#enter sib2, iclass 40, count 0 2006.224.08:09:22.21#ibcon#flushed, iclass 40, count 0 2006.224.08:09:22.21#ibcon#about to write, iclass 40, count 0 2006.224.08:09:22.21#ibcon#wrote, iclass 40, count 0 2006.224.08:09:22.21#ibcon#about to read 3, iclass 40, count 0 2006.224.08:09:22.26#ibcon#read 3, iclass 40, count 0 2006.224.08:09:22.26#ibcon#about to read 4, iclass 40, count 0 2006.224.08:09:22.26#ibcon#read 4, iclass 40, count 0 2006.224.08:09:22.26#ibcon#about to read 5, iclass 40, count 0 2006.224.08:09:22.26#ibcon#read 5, iclass 40, count 0 2006.224.08:09:22.26#ibcon#about to read 6, iclass 40, count 0 2006.224.08:09:22.26#ibcon#read 6, iclass 40, count 0 2006.224.08:09:22.26#ibcon#end of sib2, iclass 40, count 0 2006.224.08:09:22.26#ibcon#*after write, iclass 40, count 0 2006.224.08:09:22.26#ibcon#*before return 0, iclass 40, count 0 2006.224.08:09:22.26#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.224.08:09:22.26#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.224.08:09:22.26#ibcon#about to clear, iclass 40 cls_cnt 0 2006.224.08:09:22.26#ibcon#cleared, iclass 40 cls_cnt 0 2006.224.08:09:22.26$vc4f8/vb=6,4 2006.224.08:09:22.26#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.224.08:09:22.26#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.224.08:09:22.26#ibcon#ireg 11 cls_cnt 2 2006.224.08:09:22.26#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.224.08:09:22.31#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.224.08:09:22.31#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.224.08:09:22.31#ibcon#enter wrdev, iclass 4, count 2 2006.224.08:09:22.31#ibcon#first serial, iclass 4, count 2 2006.224.08:09:22.31#ibcon#enter sib2, iclass 4, count 2 2006.224.08:09:22.31#ibcon#flushed, iclass 4, count 2 2006.224.08:09:22.31#ibcon#about to write, iclass 4, count 2 2006.224.08:09:22.31#ibcon#wrote, iclass 4, count 2 2006.224.08:09:22.31#ibcon#about to read 3, iclass 4, count 2 2006.224.08:09:22.33#ibcon#read 3, iclass 4, count 2 2006.224.08:09:22.33#ibcon#about to read 4, iclass 4, count 2 2006.224.08:09:22.33#ibcon#read 4, iclass 4, count 2 2006.224.08:09:22.33#ibcon#about to read 5, iclass 4, count 2 2006.224.08:09:22.33#ibcon#read 5, iclass 4, count 2 2006.224.08:09:22.33#ibcon#about to read 6, iclass 4, count 2 2006.224.08:09:22.33#ibcon#read 6, iclass 4, count 2 2006.224.08:09:22.33#ibcon#end of sib2, iclass 4, count 2 2006.224.08:09:22.33#ibcon#*mode == 0, iclass 4, count 2 2006.224.08:09:22.33#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.224.08:09:22.33#ibcon#[27=AT06-04\r\n] 2006.224.08:09:22.33#ibcon#*before write, iclass 4, count 2 2006.224.08:09:22.33#ibcon#enter sib2, iclass 4, count 2 2006.224.08:09:22.33#ibcon#flushed, iclass 4, count 2 2006.224.08:09:22.33#ibcon#about to write, iclass 4, count 2 2006.224.08:09:22.33#ibcon#wrote, iclass 4, count 2 2006.224.08:09:22.33#ibcon#about to read 3, iclass 4, count 2 2006.224.08:09:22.36#ibcon#read 3, iclass 4, count 2 2006.224.08:09:22.36#ibcon#about to read 4, iclass 4, count 2 2006.224.08:09:22.36#ibcon#read 4, iclass 4, count 2 2006.224.08:09:22.36#ibcon#about to read 5, iclass 4, count 2 2006.224.08:09:22.36#ibcon#read 5, iclass 4, count 2 2006.224.08:09:22.36#ibcon#about to read 6, iclass 4, count 2 2006.224.08:09:22.36#ibcon#read 6, iclass 4, count 2 2006.224.08:09:22.36#ibcon#end of sib2, iclass 4, count 2 2006.224.08:09:22.36#ibcon#*after write, iclass 4, count 2 2006.224.08:09:22.36#ibcon#*before return 0, iclass 4, count 2 2006.224.08:09:22.36#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.224.08:09:22.36#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.224.08:09:22.36#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.224.08:09:22.36#ibcon#ireg 7 cls_cnt 0 2006.224.08:09:22.36#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.224.08:09:22.48#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.224.08:09:22.48#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.224.08:09:22.48#ibcon#enter wrdev, iclass 4, count 0 2006.224.08:09:22.48#ibcon#first serial, iclass 4, count 0 2006.224.08:09:22.48#ibcon#enter sib2, iclass 4, count 0 2006.224.08:09:22.48#ibcon#flushed, iclass 4, count 0 2006.224.08:09:22.48#ibcon#about to write, iclass 4, count 0 2006.224.08:09:22.48#ibcon#wrote, iclass 4, count 0 2006.224.08:09:22.48#ibcon#about to read 3, iclass 4, count 0 2006.224.08:09:22.50#ibcon#read 3, iclass 4, count 0 2006.224.08:09:22.50#ibcon#about to read 4, iclass 4, count 0 2006.224.08:09:22.50#ibcon#read 4, iclass 4, count 0 2006.224.08:09:22.50#ibcon#about to read 5, iclass 4, count 0 2006.224.08:09:22.50#ibcon#read 5, iclass 4, count 0 2006.224.08:09:22.50#ibcon#about to read 6, iclass 4, count 0 2006.224.08:09:22.50#ibcon#read 6, iclass 4, count 0 2006.224.08:09:22.50#ibcon#end of sib2, iclass 4, count 0 2006.224.08:09:22.50#ibcon#*mode == 0, iclass 4, count 0 2006.224.08:09:22.50#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.224.08:09:22.50#ibcon#[27=USB\r\n] 2006.224.08:09:22.50#ibcon#*before write, iclass 4, count 0 2006.224.08:09:22.50#ibcon#enter sib2, iclass 4, count 0 2006.224.08:09:22.50#ibcon#flushed, iclass 4, count 0 2006.224.08:09:22.50#ibcon#about to write, iclass 4, count 0 2006.224.08:09:22.50#ibcon#wrote, iclass 4, count 0 2006.224.08:09:22.50#ibcon#about to read 3, iclass 4, count 0 2006.224.08:09:22.53#ibcon#read 3, iclass 4, count 0 2006.224.08:09:22.53#ibcon#about to read 4, iclass 4, count 0 2006.224.08:09:22.53#ibcon#read 4, iclass 4, count 0 2006.224.08:09:22.53#ibcon#about to read 5, iclass 4, count 0 2006.224.08:09:22.53#ibcon#read 5, iclass 4, count 0 2006.224.08:09:22.53#ibcon#about to read 6, iclass 4, count 0 2006.224.08:09:22.53#ibcon#read 6, iclass 4, count 0 2006.224.08:09:22.53#ibcon#end of sib2, iclass 4, count 0 2006.224.08:09:22.53#ibcon#*after write, iclass 4, count 0 2006.224.08:09:22.53#ibcon#*before return 0, iclass 4, count 0 2006.224.08:09:22.53#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.224.08:09:22.53#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.224.08:09:22.53#ibcon#about to clear, iclass 4 cls_cnt 0 2006.224.08:09:22.53#ibcon#cleared, iclass 4 cls_cnt 0 2006.224.08:09:22.53$vc4f8/vabw=wide 2006.224.08:09:22.53#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.224.08:09:22.53#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.224.08:09:22.53#ibcon#ireg 8 cls_cnt 0 2006.224.08:09:22.53#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.224.08:09:22.53#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.224.08:09:22.53#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.224.08:09:22.53#ibcon#enter wrdev, iclass 6, count 0 2006.224.08:09:22.53#ibcon#first serial, iclass 6, count 0 2006.224.08:09:22.53#ibcon#enter sib2, iclass 6, count 0 2006.224.08:09:22.53#ibcon#flushed, iclass 6, count 0 2006.224.08:09:22.53#ibcon#about to write, iclass 6, count 0 2006.224.08:09:22.53#ibcon#wrote, iclass 6, count 0 2006.224.08:09:22.53#ibcon#about to read 3, iclass 6, count 0 2006.224.08:09:22.55#ibcon#read 3, iclass 6, count 0 2006.224.08:09:22.55#ibcon#about to read 4, iclass 6, count 0 2006.224.08:09:22.55#ibcon#read 4, iclass 6, count 0 2006.224.08:09:22.55#ibcon#about to read 5, iclass 6, count 0 2006.224.08:09:22.55#ibcon#read 5, iclass 6, count 0 2006.224.08:09:22.55#ibcon#about to read 6, iclass 6, count 0 2006.224.08:09:22.55#ibcon#read 6, iclass 6, count 0 2006.224.08:09:22.55#ibcon#end of sib2, iclass 6, count 0 2006.224.08:09:22.55#ibcon#*mode == 0, iclass 6, count 0 2006.224.08:09:22.55#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.224.08:09:22.55#ibcon#[25=BW32\r\n] 2006.224.08:09:22.55#ibcon#*before write, iclass 6, count 0 2006.224.08:09:22.55#ibcon#enter sib2, iclass 6, count 0 2006.224.08:09:22.55#ibcon#flushed, iclass 6, count 0 2006.224.08:09:22.55#ibcon#about to write, iclass 6, count 0 2006.224.08:09:22.55#ibcon#wrote, iclass 6, count 0 2006.224.08:09:22.55#ibcon#about to read 3, iclass 6, count 0 2006.224.08:09:22.58#ibcon#read 3, iclass 6, count 0 2006.224.08:09:22.58#ibcon#about to read 4, iclass 6, count 0 2006.224.08:09:22.58#ibcon#read 4, iclass 6, count 0 2006.224.08:09:22.58#ibcon#about to read 5, iclass 6, count 0 2006.224.08:09:22.58#ibcon#read 5, iclass 6, count 0 2006.224.08:09:22.58#ibcon#about to read 6, iclass 6, count 0 2006.224.08:09:22.58#ibcon#read 6, iclass 6, count 0 2006.224.08:09:22.58#ibcon#end of sib2, iclass 6, count 0 2006.224.08:09:22.58#ibcon#*after write, iclass 6, count 0 2006.224.08:09:22.58#ibcon#*before return 0, iclass 6, count 0 2006.224.08:09:22.58#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.224.08:09:22.58#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.224.08:09:22.58#ibcon#about to clear, iclass 6 cls_cnt 0 2006.224.08:09:22.58#ibcon#cleared, iclass 6 cls_cnt 0 2006.224.08:09:22.58$vc4f8/vbbw=wide 2006.224.08:09:22.58#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.224.08:09:22.58#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.224.08:09:22.58#ibcon#ireg 8 cls_cnt 0 2006.224.08:09:22.58#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.224.08:09:22.65#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.224.08:09:22.65#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.224.08:09:22.65#ibcon#enter wrdev, iclass 10, count 0 2006.224.08:09:22.65#ibcon#first serial, iclass 10, count 0 2006.224.08:09:22.65#ibcon#enter sib2, iclass 10, count 0 2006.224.08:09:22.65#ibcon#flushed, iclass 10, count 0 2006.224.08:09:22.65#ibcon#about to write, iclass 10, count 0 2006.224.08:09:22.65#ibcon#wrote, iclass 10, count 0 2006.224.08:09:22.65#ibcon#about to read 3, iclass 10, count 0 2006.224.08:09:22.67#ibcon#read 3, iclass 10, count 0 2006.224.08:09:22.67#ibcon#about to read 4, iclass 10, count 0 2006.224.08:09:22.67#ibcon#read 4, iclass 10, count 0 2006.224.08:09:22.67#ibcon#about to read 5, iclass 10, count 0 2006.224.08:09:22.67#ibcon#read 5, iclass 10, count 0 2006.224.08:09:22.67#ibcon#about to read 6, iclass 10, count 0 2006.224.08:09:22.67#ibcon#read 6, iclass 10, count 0 2006.224.08:09:22.67#ibcon#end of sib2, iclass 10, count 0 2006.224.08:09:22.67#ibcon#*mode == 0, iclass 10, count 0 2006.224.08:09:22.67#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.224.08:09:22.67#ibcon#[27=BW32\r\n] 2006.224.08:09:22.67#ibcon#*before write, iclass 10, count 0 2006.224.08:09:22.67#ibcon#enter sib2, iclass 10, count 0 2006.224.08:09:22.67#ibcon#flushed, iclass 10, count 0 2006.224.08:09:22.67#ibcon#about to write, iclass 10, count 0 2006.224.08:09:22.67#ibcon#wrote, iclass 10, count 0 2006.224.08:09:22.67#ibcon#about to read 3, iclass 10, count 0 2006.224.08:09:22.70#ibcon#read 3, iclass 10, count 0 2006.224.08:09:22.70#ibcon#about to read 4, iclass 10, count 0 2006.224.08:09:22.70#ibcon#read 4, iclass 10, count 0 2006.224.08:09:22.70#ibcon#about to read 5, iclass 10, count 0 2006.224.08:09:22.70#ibcon#read 5, iclass 10, count 0 2006.224.08:09:22.70#ibcon#about to read 6, iclass 10, count 0 2006.224.08:09:22.70#ibcon#read 6, iclass 10, count 0 2006.224.08:09:22.70#ibcon#end of sib2, iclass 10, count 0 2006.224.08:09:22.70#ibcon#*after write, iclass 10, count 0 2006.224.08:09:22.70#ibcon#*before return 0, iclass 10, count 0 2006.224.08:09:22.70#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.224.08:09:22.70#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.224.08:09:22.70#ibcon#about to clear, iclass 10 cls_cnt 0 2006.224.08:09:22.70#ibcon#cleared, iclass 10 cls_cnt 0 2006.224.08:09:22.70$4f8m12a/ifd4f 2006.224.08:09:22.70$ifd4f/lo= 2006.224.08:09:22.70$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.224.08:09:22.70$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.224.08:09:22.70$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.224.08:09:22.70$ifd4f/patch= 2006.224.08:09:22.70$ifd4f/patch=lo1,a1,a2,a3,a4 2006.224.08:09:22.70$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.224.08:09:22.70$ifd4f/patch=lo3,a5,a6,a7,a8 2006.224.08:09:22.70$4f8m12a/"form=m,16.000,1:2 2006.224.08:09:22.70$4f8m12a/"tpicd 2006.224.08:09:22.70$4f8m12a/echo=off 2006.224.08:09:22.70$4f8m12a/xlog=off 2006.224.08:09:22.70:!2006.224.08:09:50 2006.224.08:09:31.14#trakl#Source acquired 2006.224.08:09:32.14#flagr#flagr/antenna,acquired 2006.224.08:09:50.00:preob 2006.224.08:09:51.14/onsource/TRACKING 2006.224.08:09:51.14:!2006.224.08:10:00 2006.224.08:10:00.00:data_valid=on 2006.224.08:10:00.00:midob 2006.224.08:10:00.14/onsource/TRACKING 2006.224.08:10:00.14/wx/23.72,1004.7,100 2006.224.08:10:00.22/cable/+6.4340E-03 2006.224.08:10:01.31/va/01,08,usb,yes,42,44 2006.224.08:10:01.31/va/02,07,usb,yes,43,45 2006.224.08:10:01.31/va/03,06,usb,yes,45,45 2006.224.08:10:01.31/va/04,07,usb,yes,44,48 2006.224.08:10:01.31/va/05,07,usb,yes,52,55 2006.224.08:10:01.31/va/06,06,usb,yes,52,51 2006.224.08:10:01.31/va/07,06,usb,yes,53,52 2006.224.08:10:01.31/va/08,07,usb,yes,50,49 2006.224.08:10:01.54/valo/01,532.99,yes,locked 2006.224.08:10:01.54/valo/02,572.99,yes,locked 2006.224.08:10:01.54/valo/03,672.99,yes,locked 2006.224.08:10:01.54/valo/04,832.99,yes,locked 2006.224.08:10:01.54/valo/05,652.99,yes,locked 2006.224.08:10:01.54/valo/06,772.99,yes,locked 2006.224.08:10:01.54/valo/07,832.99,yes,locked 2006.224.08:10:01.54/valo/08,852.99,yes,locked 2006.224.08:10:02.63/vb/01,04,usb,yes,32,30 2006.224.08:10:02.63/vb/02,04,usb,yes,33,35 2006.224.08:10:02.63/vb/03,04,usb,yes,30,34 2006.224.08:10:02.63/vb/04,04,usb,yes,31,31 2006.224.08:10:02.63/vb/05,04,usb,yes,29,33 2006.224.08:10:02.63/vb/06,04,usb,yes,30,33 2006.224.08:10:02.63/vb/07,04,usb,yes,32,32 2006.224.08:10:02.63/vb/08,04,usb,yes,30,33 2006.224.08:10:02.86/vblo/01,632.99,yes,locked 2006.224.08:10:02.86/vblo/02,640.99,yes,locked 2006.224.08:10:02.86/vblo/03,656.99,yes,locked 2006.224.08:10:02.86/vblo/04,712.99,yes,locked 2006.224.08:10:02.86/vblo/05,744.99,yes,locked 2006.224.08:10:02.86/vblo/06,752.99,yes,locked 2006.224.08:10:02.86/vblo/07,734.99,yes,locked 2006.224.08:10:02.86/vblo/08,744.99,yes,locked 2006.224.08:10:03.01/vabw/8 2006.224.08:10:03.16/vbbw/8 2006.224.08:10:03.25/xfe/off,on,15.0 2006.224.08:10:03.63/ifatt/23,28,28,28 2006.224.08:10:04.07/fmout-gps/S +4.57E-07 2006.224.08:10:04.11:!2006.224.08:11:00 2006.224.08:11:00.00:data_valid=off 2006.224.08:11:00.00:postob 2006.224.08:11:00.13/cable/+6.4320E-03 2006.224.08:11:00.13/wx/23.74,1004.8,100 2006.224.08:11:01.08/fmout-gps/S +4.57E-07 2006.224.08:11:01.08:scan_name=224-0812,k06224,60 2006.224.08:11:01.08:source=1418+546,141946.60,542314.8,2000.0,ccw 2006.224.08:11:01.13#flagr#flagr/antenna,new-source 2006.224.08:11:02.13:checkk5 2006.224.08:11:02.50/chk_autoobs//k5ts1/ autoobs is running! 2006.224.08:11:02.87/chk_autoobs//k5ts2/ autoobs is running! 2006.224.08:11:03.25/chk_autoobs//k5ts3/ autoobs is running! 2006.224.08:11:03.65/chk_autoobs//k5ts4/ autoobs is running! 2006.224.08:11:04.01/chk_obsdata//k5ts1/T2240810??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.08:11:04.38/chk_obsdata//k5ts2/T2240810??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.08:11:04.75/chk_obsdata//k5ts3/T2240810??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.08:11:05.11/chk_obsdata//k5ts4/T2240810??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.08:11:05.80/k5log//k5ts1_log_newline 2006.224.08:11:06.49/k5log//k5ts2_log_newline 2006.224.08:11:07.17/k5log//k5ts3_log_newline 2006.224.08:11:07.85/k5log//k5ts4_log_newline 2006.224.08:11:07.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.224.08:11:07.87:4f8m12a=2 2006.224.08:11:07.87$4f8m12a/echo=on 2006.224.08:11:07.87$4f8m12a/pcalon 2006.224.08:11:07.87$pcalon/"no phase cal control is implemented here 2006.224.08:11:07.87$4f8m12a/"tpicd=stop 2006.224.08:11:07.87$4f8m12a/vc4f8 2006.224.08:11:07.87$vc4f8/valo=1,532.99 2006.224.08:11:07.88#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.224.08:11:07.88#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.224.08:11:07.88#ibcon#ireg 17 cls_cnt 0 2006.224.08:11:07.88#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.224.08:11:07.88#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.224.08:11:07.88#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.224.08:11:07.88#ibcon#enter wrdev, iclass 21, count 0 2006.224.08:11:07.88#ibcon#first serial, iclass 21, count 0 2006.224.08:11:07.88#ibcon#enter sib2, iclass 21, count 0 2006.224.08:11:07.88#ibcon#flushed, iclass 21, count 0 2006.224.08:11:07.88#ibcon#about to write, iclass 21, count 0 2006.224.08:11:07.88#ibcon#wrote, iclass 21, count 0 2006.224.08:11:07.88#ibcon#about to read 3, iclass 21, count 0 2006.224.08:11:07.92#ibcon#read 3, iclass 21, count 0 2006.224.08:11:07.92#ibcon#about to read 4, iclass 21, count 0 2006.224.08:11:07.92#ibcon#read 4, iclass 21, count 0 2006.224.08:11:07.92#ibcon#about to read 5, iclass 21, count 0 2006.224.08:11:07.92#ibcon#read 5, iclass 21, count 0 2006.224.08:11:07.92#ibcon#about to read 6, iclass 21, count 0 2006.224.08:11:07.92#ibcon#read 6, iclass 21, count 0 2006.224.08:11:07.92#ibcon#end of sib2, iclass 21, count 0 2006.224.08:11:07.92#ibcon#*mode == 0, iclass 21, count 0 2006.224.08:11:07.92#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.224.08:11:07.92#ibcon#[26=FRQ=01,532.99\r\n] 2006.224.08:11:07.92#ibcon#*before write, iclass 21, count 0 2006.224.08:11:07.92#ibcon#enter sib2, iclass 21, count 0 2006.224.08:11:07.92#ibcon#flushed, iclass 21, count 0 2006.224.08:11:07.92#ibcon#about to write, iclass 21, count 0 2006.224.08:11:07.92#ibcon#wrote, iclass 21, count 0 2006.224.08:11:07.92#ibcon#about to read 3, iclass 21, count 0 2006.224.08:11:07.97#ibcon#read 3, iclass 21, count 0 2006.224.08:11:07.97#ibcon#about to read 4, iclass 21, count 0 2006.224.08:11:07.97#ibcon#read 4, iclass 21, count 0 2006.224.08:11:07.97#ibcon#about to read 5, iclass 21, count 0 2006.224.08:11:07.97#ibcon#read 5, iclass 21, count 0 2006.224.08:11:07.97#ibcon#about to read 6, iclass 21, count 0 2006.224.08:11:07.97#ibcon#read 6, iclass 21, count 0 2006.224.08:11:07.97#ibcon#end of sib2, iclass 21, count 0 2006.224.08:11:07.97#ibcon#*after write, iclass 21, count 0 2006.224.08:11:07.97#ibcon#*before return 0, iclass 21, count 0 2006.224.08:11:07.97#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.224.08:11:07.97#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.224.08:11:07.97#ibcon#about to clear, iclass 21 cls_cnt 0 2006.224.08:11:07.97#ibcon#cleared, iclass 21 cls_cnt 0 2006.224.08:11:07.97$vc4f8/va=1,8 2006.224.08:11:07.97#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.224.08:11:07.97#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.224.08:11:07.97#ibcon#ireg 11 cls_cnt 2 2006.224.08:11:07.97#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.224.08:11:07.97#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.224.08:11:07.97#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.224.08:11:07.97#ibcon#enter wrdev, iclass 23, count 2 2006.224.08:11:07.97#ibcon#first serial, iclass 23, count 2 2006.224.08:11:07.97#ibcon#enter sib2, iclass 23, count 2 2006.224.08:11:07.97#ibcon#flushed, iclass 23, count 2 2006.224.08:11:07.97#ibcon#about to write, iclass 23, count 2 2006.224.08:11:07.97#ibcon#wrote, iclass 23, count 2 2006.224.08:11:07.97#ibcon#about to read 3, iclass 23, count 2 2006.224.08:11:07.99#ibcon#read 3, iclass 23, count 2 2006.224.08:11:07.99#ibcon#about to read 4, iclass 23, count 2 2006.224.08:11:07.99#ibcon#read 4, iclass 23, count 2 2006.224.08:11:07.99#ibcon#about to read 5, iclass 23, count 2 2006.224.08:11:07.99#ibcon#read 5, iclass 23, count 2 2006.224.08:11:07.99#ibcon#about to read 6, iclass 23, count 2 2006.224.08:11:07.99#ibcon#read 6, iclass 23, count 2 2006.224.08:11:07.99#ibcon#end of sib2, iclass 23, count 2 2006.224.08:11:07.99#ibcon#*mode == 0, iclass 23, count 2 2006.224.08:11:07.99#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.224.08:11:07.99#ibcon#[25=AT01-08\r\n] 2006.224.08:11:07.99#ibcon#*before write, iclass 23, count 2 2006.224.08:11:07.99#ibcon#enter sib2, iclass 23, count 2 2006.224.08:11:07.99#ibcon#flushed, iclass 23, count 2 2006.224.08:11:07.99#ibcon#about to write, iclass 23, count 2 2006.224.08:11:07.99#ibcon#wrote, iclass 23, count 2 2006.224.08:11:07.99#ibcon#about to read 3, iclass 23, count 2 2006.224.08:11:08.03#ibcon#read 3, iclass 23, count 2 2006.224.08:11:08.03#ibcon#about to read 4, iclass 23, count 2 2006.224.08:11:08.03#ibcon#read 4, iclass 23, count 2 2006.224.08:11:08.03#ibcon#about to read 5, iclass 23, count 2 2006.224.08:11:08.03#ibcon#read 5, iclass 23, count 2 2006.224.08:11:08.03#ibcon#about to read 6, iclass 23, count 2 2006.224.08:11:08.03#ibcon#read 6, iclass 23, count 2 2006.224.08:11:08.03#ibcon#end of sib2, iclass 23, count 2 2006.224.08:11:08.03#ibcon#*after write, iclass 23, count 2 2006.224.08:11:08.03#ibcon#*before return 0, iclass 23, count 2 2006.224.08:11:08.03#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.224.08:11:08.03#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.224.08:11:08.03#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.224.08:11:08.03#ibcon#ireg 7 cls_cnt 0 2006.224.08:11:08.03#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.224.08:11:08.15#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.224.08:11:08.15#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.224.08:11:08.15#ibcon#enter wrdev, iclass 23, count 0 2006.224.08:11:08.15#ibcon#first serial, iclass 23, count 0 2006.224.08:11:08.15#ibcon#enter sib2, iclass 23, count 0 2006.224.08:11:08.15#ibcon#flushed, iclass 23, count 0 2006.224.08:11:08.15#ibcon#about to write, iclass 23, count 0 2006.224.08:11:08.15#ibcon#wrote, iclass 23, count 0 2006.224.08:11:08.15#ibcon#about to read 3, iclass 23, count 0 2006.224.08:11:08.17#ibcon#read 3, iclass 23, count 0 2006.224.08:11:08.17#ibcon#about to read 4, iclass 23, count 0 2006.224.08:11:08.17#ibcon#read 4, iclass 23, count 0 2006.224.08:11:08.17#ibcon#about to read 5, iclass 23, count 0 2006.224.08:11:08.17#ibcon#read 5, iclass 23, count 0 2006.224.08:11:08.17#ibcon#about to read 6, iclass 23, count 0 2006.224.08:11:08.17#ibcon#read 6, iclass 23, count 0 2006.224.08:11:08.17#ibcon#end of sib2, iclass 23, count 0 2006.224.08:11:08.17#ibcon#*mode == 0, iclass 23, count 0 2006.224.08:11:08.17#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.224.08:11:08.17#ibcon#[25=USB\r\n] 2006.224.08:11:08.17#ibcon#*before write, iclass 23, count 0 2006.224.08:11:08.17#ibcon#enter sib2, iclass 23, count 0 2006.224.08:11:08.17#ibcon#flushed, iclass 23, count 0 2006.224.08:11:08.17#ibcon#about to write, iclass 23, count 0 2006.224.08:11:08.17#ibcon#wrote, iclass 23, count 0 2006.224.08:11:08.17#ibcon#about to read 3, iclass 23, count 0 2006.224.08:11:08.20#ibcon#read 3, iclass 23, count 0 2006.224.08:11:08.20#ibcon#about to read 4, iclass 23, count 0 2006.224.08:11:08.20#ibcon#read 4, iclass 23, count 0 2006.224.08:11:08.20#ibcon#about to read 5, iclass 23, count 0 2006.224.08:11:08.20#ibcon#read 5, iclass 23, count 0 2006.224.08:11:08.20#ibcon#about to read 6, iclass 23, count 0 2006.224.08:11:08.20#ibcon#read 6, iclass 23, count 0 2006.224.08:11:08.20#ibcon#end of sib2, iclass 23, count 0 2006.224.08:11:08.20#ibcon#*after write, iclass 23, count 0 2006.224.08:11:08.20#ibcon#*before return 0, iclass 23, count 0 2006.224.08:11:08.20#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.224.08:11:08.20#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.224.08:11:08.20#ibcon#about to clear, iclass 23 cls_cnt 0 2006.224.08:11:08.20#ibcon#cleared, iclass 23 cls_cnt 0 2006.224.08:11:08.20$vc4f8/valo=2,572.99 2006.224.08:11:08.20#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.224.08:11:08.20#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.224.08:11:08.20#ibcon#ireg 17 cls_cnt 0 2006.224.08:11:08.20#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.224.08:11:08.20#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.224.08:11:08.20#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.224.08:11:08.20#ibcon#enter wrdev, iclass 25, count 0 2006.224.08:11:08.20#ibcon#first serial, iclass 25, count 0 2006.224.08:11:08.20#ibcon#enter sib2, iclass 25, count 0 2006.224.08:11:08.20#ibcon#flushed, iclass 25, count 0 2006.224.08:11:08.20#ibcon#about to write, iclass 25, count 0 2006.224.08:11:08.20#ibcon#wrote, iclass 25, count 0 2006.224.08:11:08.20#ibcon#about to read 3, iclass 25, count 0 2006.224.08:11:08.22#ibcon#read 3, iclass 25, count 0 2006.224.08:11:08.22#ibcon#about to read 4, iclass 25, count 0 2006.224.08:11:08.22#ibcon#read 4, iclass 25, count 0 2006.224.08:11:08.22#ibcon#about to read 5, iclass 25, count 0 2006.224.08:11:08.22#ibcon#read 5, iclass 25, count 0 2006.224.08:11:08.22#ibcon#about to read 6, iclass 25, count 0 2006.224.08:11:08.22#ibcon#read 6, iclass 25, count 0 2006.224.08:11:08.22#ibcon#end of sib2, iclass 25, count 0 2006.224.08:11:08.22#ibcon#*mode == 0, iclass 25, count 0 2006.224.08:11:08.22#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.224.08:11:08.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.224.08:11:08.22#ibcon#*before write, iclass 25, count 0 2006.224.08:11:08.22#ibcon#enter sib2, iclass 25, count 0 2006.224.08:11:08.22#ibcon#flushed, iclass 25, count 0 2006.224.08:11:08.22#ibcon#about to write, iclass 25, count 0 2006.224.08:11:08.22#ibcon#wrote, iclass 25, count 0 2006.224.08:11:08.22#ibcon#about to read 3, iclass 25, count 0 2006.224.08:11:08.26#ibcon#read 3, iclass 25, count 0 2006.224.08:11:08.26#ibcon#about to read 4, iclass 25, count 0 2006.224.08:11:08.26#ibcon#read 4, iclass 25, count 0 2006.224.08:11:08.26#ibcon#about to read 5, iclass 25, count 0 2006.224.08:11:08.26#ibcon#read 5, iclass 25, count 0 2006.224.08:11:08.26#ibcon#about to read 6, iclass 25, count 0 2006.224.08:11:08.26#ibcon#read 6, iclass 25, count 0 2006.224.08:11:08.26#ibcon#end of sib2, iclass 25, count 0 2006.224.08:11:08.26#ibcon#*after write, iclass 25, count 0 2006.224.08:11:08.26#ibcon#*before return 0, iclass 25, count 0 2006.224.08:11:08.26#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.224.08:11:08.26#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.224.08:11:08.26#ibcon#about to clear, iclass 25 cls_cnt 0 2006.224.08:11:08.26#ibcon#cleared, iclass 25 cls_cnt 0 2006.224.08:11:08.26$vc4f8/va=2,7 2006.224.08:11:08.26#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.224.08:11:08.26#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.224.08:11:08.26#ibcon#ireg 11 cls_cnt 2 2006.224.08:11:08.26#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.224.08:11:08.32#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.224.08:11:08.32#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.224.08:11:08.32#ibcon#enter wrdev, iclass 27, count 2 2006.224.08:11:08.32#ibcon#first serial, iclass 27, count 2 2006.224.08:11:08.32#ibcon#enter sib2, iclass 27, count 2 2006.224.08:11:08.32#ibcon#flushed, iclass 27, count 2 2006.224.08:11:08.32#ibcon#about to write, iclass 27, count 2 2006.224.08:11:08.32#ibcon#wrote, iclass 27, count 2 2006.224.08:11:08.32#ibcon#about to read 3, iclass 27, count 2 2006.224.08:11:08.34#ibcon#read 3, iclass 27, count 2 2006.224.08:11:08.34#ibcon#about to read 4, iclass 27, count 2 2006.224.08:11:08.34#ibcon#read 4, iclass 27, count 2 2006.224.08:11:08.34#ibcon#about to read 5, iclass 27, count 2 2006.224.08:11:08.34#ibcon#read 5, iclass 27, count 2 2006.224.08:11:08.34#ibcon#about to read 6, iclass 27, count 2 2006.224.08:11:08.34#ibcon#read 6, iclass 27, count 2 2006.224.08:11:08.34#ibcon#end of sib2, iclass 27, count 2 2006.224.08:11:08.34#ibcon#*mode == 0, iclass 27, count 2 2006.224.08:11:08.34#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.224.08:11:08.34#ibcon#[25=AT02-07\r\n] 2006.224.08:11:08.34#ibcon#*before write, iclass 27, count 2 2006.224.08:11:08.34#ibcon#enter sib2, iclass 27, count 2 2006.224.08:11:08.34#ibcon#flushed, iclass 27, count 2 2006.224.08:11:08.34#ibcon#about to write, iclass 27, count 2 2006.224.08:11:08.34#ibcon#wrote, iclass 27, count 2 2006.224.08:11:08.34#ibcon#about to read 3, iclass 27, count 2 2006.224.08:11:08.37#ibcon#read 3, iclass 27, count 2 2006.224.08:11:08.37#ibcon#about to read 4, iclass 27, count 2 2006.224.08:11:08.37#ibcon#read 4, iclass 27, count 2 2006.224.08:11:08.37#ibcon#about to read 5, iclass 27, count 2 2006.224.08:11:08.37#ibcon#read 5, iclass 27, count 2 2006.224.08:11:08.37#ibcon#about to read 6, iclass 27, count 2 2006.224.08:11:08.37#ibcon#read 6, iclass 27, count 2 2006.224.08:11:08.37#ibcon#end of sib2, iclass 27, count 2 2006.224.08:11:08.37#ibcon#*after write, iclass 27, count 2 2006.224.08:11:08.37#ibcon#*before return 0, iclass 27, count 2 2006.224.08:11:08.37#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.224.08:11:08.37#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.224.08:11:08.37#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.224.08:11:08.37#ibcon#ireg 7 cls_cnt 0 2006.224.08:11:08.37#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.224.08:11:08.49#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.224.08:11:08.49#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.224.08:11:08.49#ibcon#enter wrdev, iclass 27, count 0 2006.224.08:11:08.49#ibcon#first serial, iclass 27, count 0 2006.224.08:11:08.49#ibcon#enter sib2, iclass 27, count 0 2006.224.08:11:08.49#ibcon#flushed, iclass 27, count 0 2006.224.08:11:08.49#ibcon#about to write, iclass 27, count 0 2006.224.08:11:08.49#ibcon#wrote, iclass 27, count 0 2006.224.08:11:08.49#ibcon#about to read 3, iclass 27, count 0 2006.224.08:11:08.51#ibcon#read 3, iclass 27, count 0 2006.224.08:11:08.51#ibcon#about to read 4, iclass 27, count 0 2006.224.08:11:08.51#ibcon#read 4, iclass 27, count 0 2006.224.08:11:08.51#ibcon#about to read 5, iclass 27, count 0 2006.224.08:11:08.51#ibcon#read 5, iclass 27, count 0 2006.224.08:11:08.51#ibcon#about to read 6, iclass 27, count 0 2006.224.08:11:08.51#ibcon#read 6, iclass 27, count 0 2006.224.08:11:08.51#ibcon#end of sib2, iclass 27, count 0 2006.224.08:11:08.51#ibcon#*mode == 0, iclass 27, count 0 2006.224.08:11:08.51#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.224.08:11:08.51#ibcon#[25=USB\r\n] 2006.224.08:11:08.51#ibcon#*before write, iclass 27, count 0 2006.224.08:11:08.51#ibcon#enter sib2, iclass 27, count 0 2006.224.08:11:08.51#ibcon#flushed, iclass 27, count 0 2006.224.08:11:08.51#ibcon#about to write, iclass 27, count 0 2006.224.08:11:08.51#ibcon#wrote, iclass 27, count 0 2006.224.08:11:08.51#ibcon#about to read 3, iclass 27, count 0 2006.224.08:11:08.54#ibcon#read 3, iclass 27, count 0 2006.224.08:11:08.54#ibcon#about to read 4, iclass 27, count 0 2006.224.08:11:08.54#ibcon#read 4, iclass 27, count 0 2006.224.08:11:08.54#ibcon#about to read 5, iclass 27, count 0 2006.224.08:11:08.54#ibcon#read 5, iclass 27, count 0 2006.224.08:11:08.54#ibcon#about to read 6, iclass 27, count 0 2006.224.08:11:08.54#ibcon#read 6, iclass 27, count 0 2006.224.08:11:08.54#ibcon#end of sib2, iclass 27, count 0 2006.224.08:11:08.54#ibcon#*after write, iclass 27, count 0 2006.224.08:11:08.54#ibcon#*before return 0, iclass 27, count 0 2006.224.08:11:08.54#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.224.08:11:08.54#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.224.08:11:08.54#ibcon#about to clear, iclass 27 cls_cnt 0 2006.224.08:11:08.54#ibcon#cleared, iclass 27 cls_cnt 0 2006.224.08:11:08.54$vc4f8/valo=3,672.99 2006.224.08:11:08.54#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.224.08:11:08.54#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.224.08:11:08.54#ibcon#ireg 17 cls_cnt 0 2006.224.08:11:08.54#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.224.08:11:08.54#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.224.08:11:08.54#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.224.08:11:08.54#ibcon#enter wrdev, iclass 29, count 0 2006.224.08:11:08.54#ibcon#first serial, iclass 29, count 0 2006.224.08:11:08.54#ibcon#enter sib2, iclass 29, count 0 2006.224.08:11:08.54#ibcon#flushed, iclass 29, count 0 2006.224.08:11:08.54#ibcon#about to write, iclass 29, count 0 2006.224.08:11:08.54#ibcon#wrote, iclass 29, count 0 2006.224.08:11:08.54#ibcon#about to read 3, iclass 29, count 0 2006.224.08:11:08.56#ibcon#read 3, iclass 29, count 0 2006.224.08:11:08.56#ibcon#about to read 4, iclass 29, count 0 2006.224.08:11:08.56#ibcon#read 4, iclass 29, count 0 2006.224.08:11:08.56#ibcon#about to read 5, iclass 29, count 0 2006.224.08:11:08.56#ibcon#read 5, iclass 29, count 0 2006.224.08:11:08.56#ibcon#about to read 6, iclass 29, count 0 2006.224.08:11:08.56#ibcon#read 6, iclass 29, count 0 2006.224.08:11:08.56#ibcon#end of sib2, iclass 29, count 0 2006.224.08:11:08.56#ibcon#*mode == 0, iclass 29, count 0 2006.224.08:11:08.56#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.224.08:11:08.56#ibcon#[26=FRQ=03,672.99\r\n] 2006.224.08:11:08.56#ibcon#*before write, iclass 29, count 0 2006.224.08:11:08.56#ibcon#enter sib2, iclass 29, count 0 2006.224.08:11:08.56#ibcon#flushed, iclass 29, count 0 2006.224.08:11:08.56#ibcon#about to write, iclass 29, count 0 2006.224.08:11:08.56#ibcon#wrote, iclass 29, count 0 2006.224.08:11:08.56#ibcon#about to read 3, iclass 29, count 0 2006.224.08:11:08.60#ibcon#read 3, iclass 29, count 0 2006.224.08:11:08.60#ibcon#about to read 4, iclass 29, count 0 2006.224.08:11:08.60#ibcon#read 4, iclass 29, count 0 2006.224.08:11:08.60#ibcon#about to read 5, iclass 29, count 0 2006.224.08:11:08.60#ibcon#read 5, iclass 29, count 0 2006.224.08:11:08.60#ibcon#about to read 6, iclass 29, count 0 2006.224.08:11:08.60#ibcon#read 6, iclass 29, count 0 2006.224.08:11:08.60#ibcon#end of sib2, iclass 29, count 0 2006.224.08:11:08.60#ibcon#*after write, iclass 29, count 0 2006.224.08:11:08.60#ibcon#*before return 0, iclass 29, count 0 2006.224.08:11:08.60#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.224.08:11:08.60#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.224.08:11:08.60#ibcon#about to clear, iclass 29 cls_cnt 0 2006.224.08:11:08.60#ibcon#cleared, iclass 29 cls_cnt 0 2006.224.08:11:08.60$vc4f8/va=3,6 2006.224.08:11:08.60#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.224.08:11:08.60#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.224.08:11:08.60#ibcon#ireg 11 cls_cnt 2 2006.224.08:11:08.60#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.224.08:11:08.66#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.224.08:11:08.66#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.224.08:11:08.66#ibcon#enter wrdev, iclass 31, count 2 2006.224.08:11:08.66#ibcon#first serial, iclass 31, count 2 2006.224.08:11:08.66#ibcon#enter sib2, iclass 31, count 2 2006.224.08:11:08.66#ibcon#flushed, iclass 31, count 2 2006.224.08:11:08.66#ibcon#about to write, iclass 31, count 2 2006.224.08:11:08.66#ibcon#wrote, iclass 31, count 2 2006.224.08:11:08.66#ibcon#about to read 3, iclass 31, count 2 2006.224.08:11:08.68#ibcon#read 3, iclass 31, count 2 2006.224.08:11:08.68#ibcon#about to read 4, iclass 31, count 2 2006.224.08:11:08.68#ibcon#read 4, iclass 31, count 2 2006.224.08:11:08.68#ibcon#about to read 5, iclass 31, count 2 2006.224.08:11:08.68#ibcon#read 5, iclass 31, count 2 2006.224.08:11:08.68#ibcon#about to read 6, iclass 31, count 2 2006.224.08:11:08.68#ibcon#read 6, iclass 31, count 2 2006.224.08:11:08.68#ibcon#end of sib2, iclass 31, count 2 2006.224.08:11:08.68#ibcon#*mode == 0, iclass 31, count 2 2006.224.08:11:08.68#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.224.08:11:08.68#ibcon#[25=AT03-06\r\n] 2006.224.08:11:08.68#ibcon#*before write, iclass 31, count 2 2006.224.08:11:08.68#ibcon#enter sib2, iclass 31, count 2 2006.224.08:11:08.68#ibcon#flushed, iclass 31, count 2 2006.224.08:11:08.68#ibcon#about to write, iclass 31, count 2 2006.224.08:11:08.68#ibcon#wrote, iclass 31, count 2 2006.224.08:11:08.68#ibcon#about to read 3, iclass 31, count 2 2006.224.08:11:08.72#ibcon#read 3, iclass 31, count 2 2006.224.08:11:08.72#ibcon#about to read 4, iclass 31, count 2 2006.224.08:11:08.72#ibcon#read 4, iclass 31, count 2 2006.224.08:11:08.72#ibcon#about to read 5, iclass 31, count 2 2006.224.08:11:08.72#ibcon#read 5, iclass 31, count 2 2006.224.08:11:08.72#ibcon#about to read 6, iclass 31, count 2 2006.224.08:11:08.72#ibcon#read 6, iclass 31, count 2 2006.224.08:11:08.72#ibcon#end of sib2, iclass 31, count 2 2006.224.08:11:08.72#ibcon#*after write, iclass 31, count 2 2006.224.08:11:08.72#ibcon#*before return 0, iclass 31, count 2 2006.224.08:11:08.72#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.224.08:11:08.72#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.224.08:11:08.72#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.224.08:11:08.72#ibcon#ireg 7 cls_cnt 0 2006.224.08:11:08.72#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.224.08:11:08.84#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.224.08:11:08.84#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.224.08:11:08.84#ibcon#enter wrdev, iclass 31, count 0 2006.224.08:11:08.84#ibcon#first serial, iclass 31, count 0 2006.224.08:11:08.84#ibcon#enter sib2, iclass 31, count 0 2006.224.08:11:08.84#ibcon#flushed, iclass 31, count 0 2006.224.08:11:08.84#ibcon#about to write, iclass 31, count 0 2006.224.08:11:08.84#ibcon#wrote, iclass 31, count 0 2006.224.08:11:08.84#ibcon#about to read 3, iclass 31, count 0 2006.224.08:11:08.86#ibcon#read 3, iclass 31, count 0 2006.224.08:11:08.86#ibcon#about to read 4, iclass 31, count 0 2006.224.08:11:08.86#ibcon#read 4, iclass 31, count 0 2006.224.08:11:08.86#ibcon#about to read 5, iclass 31, count 0 2006.224.08:11:08.86#ibcon#read 5, iclass 31, count 0 2006.224.08:11:08.86#ibcon#about to read 6, iclass 31, count 0 2006.224.08:11:08.86#ibcon#read 6, iclass 31, count 0 2006.224.08:11:08.86#ibcon#end of sib2, iclass 31, count 0 2006.224.08:11:08.86#ibcon#*mode == 0, iclass 31, count 0 2006.224.08:11:08.86#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.224.08:11:08.86#ibcon#[25=USB\r\n] 2006.224.08:11:08.86#ibcon#*before write, iclass 31, count 0 2006.224.08:11:08.86#ibcon#enter sib2, iclass 31, count 0 2006.224.08:11:08.86#ibcon#flushed, iclass 31, count 0 2006.224.08:11:08.86#ibcon#about to write, iclass 31, count 0 2006.224.08:11:08.86#ibcon#wrote, iclass 31, count 0 2006.224.08:11:08.86#ibcon#about to read 3, iclass 31, count 0 2006.224.08:11:08.89#ibcon#read 3, iclass 31, count 0 2006.224.08:11:08.89#ibcon#about to read 4, iclass 31, count 0 2006.224.08:11:08.89#ibcon#read 4, iclass 31, count 0 2006.224.08:11:08.89#ibcon#about to read 5, iclass 31, count 0 2006.224.08:11:08.89#ibcon#read 5, iclass 31, count 0 2006.224.08:11:08.89#ibcon#about to read 6, iclass 31, count 0 2006.224.08:11:08.89#ibcon#read 6, iclass 31, count 0 2006.224.08:11:08.89#ibcon#end of sib2, iclass 31, count 0 2006.224.08:11:08.89#ibcon#*after write, iclass 31, count 0 2006.224.08:11:08.89#ibcon#*before return 0, iclass 31, count 0 2006.224.08:11:08.89#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.224.08:11:08.89#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.224.08:11:08.89#ibcon#about to clear, iclass 31 cls_cnt 0 2006.224.08:11:08.89#ibcon#cleared, iclass 31 cls_cnt 0 2006.224.08:11:08.89$vc4f8/valo=4,832.99 2006.224.08:11:08.89#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.224.08:11:08.89#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.224.08:11:08.89#ibcon#ireg 17 cls_cnt 0 2006.224.08:11:08.89#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.224.08:11:08.89#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.224.08:11:08.89#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.224.08:11:08.89#ibcon#enter wrdev, iclass 33, count 0 2006.224.08:11:08.89#ibcon#first serial, iclass 33, count 0 2006.224.08:11:08.89#ibcon#enter sib2, iclass 33, count 0 2006.224.08:11:08.89#ibcon#flushed, iclass 33, count 0 2006.224.08:11:08.89#ibcon#about to write, iclass 33, count 0 2006.224.08:11:08.89#ibcon#wrote, iclass 33, count 0 2006.224.08:11:08.89#ibcon#about to read 3, iclass 33, count 0 2006.224.08:11:08.91#ibcon#read 3, iclass 33, count 0 2006.224.08:11:08.91#ibcon#about to read 4, iclass 33, count 0 2006.224.08:11:08.91#ibcon#read 4, iclass 33, count 0 2006.224.08:11:08.91#ibcon#about to read 5, iclass 33, count 0 2006.224.08:11:08.91#ibcon#read 5, iclass 33, count 0 2006.224.08:11:08.91#ibcon#about to read 6, iclass 33, count 0 2006.224.08:11:08.91#ibcon#read 6, iclass 33, count 0 2006.224.08:11:08.91#ibcon#end of sib2, iclass 33, count 0 2006.224.08:11:08.91#ibcon#*mode == 0, iclass 33, count 0 2006.224.08:11:08.91#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.224.08:11:08.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.224.08:11:08.91#ibcon#*before write, iclass 33, count 0 2006.224.08:11:08.91#ibcon#enter sib2, iclass 33, count 0 2006.224.08:11:08.91#ibcon#flushed, iclass 33, count 0 2006.224.08:11:08.91#ibcon#about to write, iclass 33, count 0 2006.224.08:11:08.91#ibcon#wrote, iclass 33, count 0 2006.224.08:11:08.91#ibcon#about to read 3, iclass 33, count 0 2006.224.08:11:08.95#ibcon#read 3, iclass 33, count 0 2006.224.08:11:08.95#ibcon#about to read 4, iclass 33, count 0 2006.224.08:11:08.95#ibcon#read 4, iclass 33, count 0 2006.224.08:11:08.95#ibcon#about to read 5, iclass 33, count 0 2006.224.08:11:08.95#ibcon#read 5, iclass 33, count 0 2006.224.08:11:08.95#ibcon#about to read 6, iclass 33, count 0 2006.224.08:11:08.95#ibcon#read 6, iclass 33, count 0 2006.224.08:11:08.95#ibcon#end of sib2, iclass 33, count 0 2006.224.08:11:08.95#ibcon#*after write, iclass 33, count 0 2006.224.08:11:08.95#ibcon#*before return 0, iclass 33, count 0 2006.224.08:11:08.95#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.224.08:11:08.95#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.224.08:11:08.95#ibcon#about to clear, iclass 33 cls_cnt 0 2006.224.08:11:08.95#ibcon#cleared, iclass 33 cls_cnt 0 2006.224.08:11:08.95$vc4f8/va=4,7 2006.224.08:11:08.95#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.224.08:11:08.95#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.224.08:11:08.95#ibcon#ireg 11 cls_cnt 2 2006.224.08:11:08.95#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.224.08:11:09.01#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.224.08:11:09.01#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.224.08:11:09.01#ibcon#enter wrdev, iclass 35, count 2 2006.224.08:11:09.01#ibcon#first serial, iclass 35, count 2 2006.224.08:11:09.01#ibcon#enter sib2, iclass 35, count 2 2006.224.08:11:09.01#ibcon#flushed, iclass 35, count 2 2006.224.08:11:09.01#ibcon#about to write, iclass 35, count 2 2006.224.08:11:09.01#ibcon#wrote, iclass 35, count 2 2006.224.08:11:09.01#ibcon#about to read 3, iclass 35, count 2 2006.224.08:11:09.03#ibcon#read 3, iclass 35, count 2 2006.224.08:11:09.03#ibcon#about to read 4, iclass 35, count 2 2006.224.08:11:09.03#ibcon#read 4, iclass 35, count 2 2006.224.08:11:09.03#ibcon#about to read 5, iclass 35, count 2 2006.224.08:11:09.03#ibcon#read 5, iclass 35, count 2 2006.224.08:11:09.03#ibcon#about to read 6, iclass 35, count 2 2006.224.08:11:09.03#ibcon#read 6, iclass 35, count 2 2006.224.08:11:09.03#ibcon#end of sib2, iclass 35, count 2 2006.224.08:11:09.03#ibcon#*mode == 0, iclass 35, count 2 2006.224.08:11:09.03#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.224.08:11:09.03#ibcon#[25=AT04-07\r\n] 2006.224.08:11:09.03#ibcon#*before write, iclass 35, count 2 2006.224.08:11:09.03#ibcon#enter sib2, iclass 35, count 2 2006.224.08:11:09.03#ibcon#flushed, iclass 35, count 2 2006.224.08:11:09.03#ibcon#about to write, iclass 35, count 2 2006.224.08:11:09.03#ibcon#wrote, iclass 35, count 2 2006.224.08:11:09.03#ibcon#about to read 3, iclass 35, count 2 2006.224.08:11:09.06#ibcon#read 3, iclass 35, count 2 2006.224.08:11:09.06#ibcon#about to read 4, iclass 35, count 2 2006.224.08:11:09.06#ibcon#read 4, iclass 35, count 2 2006.224.08:11:09.06#ibcon#about to read 5, iclass 35, count 2 2006.224.08:11:09.06#ibcon#read 5, iclass 35, count 2 2006.224.08:11:09.06#ibcon#about to read 6, iclass 35, count 2 2006.224.08:11:09.06#ibcon#read 6, iclass 35, count 2 2006.224.08:11:09.06#ibcon#end of sib2, iclass 35, count 2 2006.224.08:11:09.06#ibcon#*after write, iclass 35, count 2 2006.224.08:11:09.06#ibcon#*before return 0, iclass 35, count 2 2006.224.08:11:09.06#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.224.08:11:09.06#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.224.08:11:09.06#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.224.08:11:09.06#ibcon#ireg 7 cls_cnt 0 2006.224.08:11:09.06#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.224.08:11:09.18#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.224.08:11:09.18#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.224.08:11:09.18#ibcon#enter wrdev, iclass 35, count 0 2006.224.08:11:09.18#ibcon#first serial, iclass 35, count 0 2006.224.08:11:09.18#ibcon#enter sib2, iclass 35, count 0 2006.224.08:11:09.18#ibcon#flushed, iclass 35, count 0 2006.224.08:11:09.18#ibcon#about to write, iclass 35, count 0 2006.224.08:11:09.18#ibcon#wrote, iclass 35, count 0 2006.224.08:11:09.18#ibcon#about to read 3, iclass 35, count 0 2006.224.08:11:09.20#ibcon#read 3, iclass 35, count 0 2006.224.08:11:09.20#ibcon#about to read 4, iclass 35, count 0 2006.224.08:11:09.20#ibcon#read 4, iclass 35, count 0 2006.224.08:11:09.20#ibcon#about to read 5, iclass 35, count 0 2006.224.08:11:09.20#ibcon#read 5, iclass 35, count 0 2006.224.08:11:09.20#ibcon#about to read 6, iclass 35, count 0 2006.224.08:11:09.20#ibcon#read 6, iclass 35, count 0 2006.224.08:11:09.20#ibcon#end of sib2, iclass 35, count 0 2006.224.08:11:09.20#ibcon#*mode == 0, iclass 35, count 0 2006.224.08:11:09.20#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.224.08:11:09.20#ibcon#[25=USB\r\n] 2006.224.08:11:09.20#ibcon#*before write, iclass 35, count 0 2006.224.08:11:09.20#ibcon#enter sib2, iclass 35, count 0 2006.224.08:11:09.20#ibcon#flushed, iclass 35, count 0 2006.224.08:11:09.20#ibcon#about to write, iclass 35, count 0 2006.224.08:11:09.20#ibcon#wrote, iclass 35, count 0 2006.224.08:11:09.20#ibcon#about to read 3, iclass 35, count 0 2006.224.08:11:09.23#ibcon#read 3, iclass 35, count 0 2006.224.08:11:09.23#ibcon#about to read 4, iclass 35, count 0 2006.224.08:11:09.23#ibcon#read 4, iclass 35, count 0 2006.224.08:11:09.23#ibcon#about to read 5, iclass 35, count 0 2006.224.08:11:09.23#ibcon#read 5, iclass 35, count 0 2006.224.08:11:09.23#ibcon#about to read 6, iclass 35, count 0 2006.224.08:11:09.23#ibcon#read 6, iclass 35, count 0 2006.224.08:11:09.23#ibcon#end of sib2, iclass 35, count 0 2006.224.08:11:09.23#ibcon#*after write, iclass 35, count 0 2006.224.08:11:09.23#ibcon#*before return 0, iclass 35, count 0 2006.224.08:11:09.23#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.224.08:11:09.23#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.224.08:11:09.23#ibcon#about to clear, iclass 35 cls_cnt 0 2006.224.08:11:09.23#ibcon#cleared, iclass 35 cls_cnt 0 2006.224.08:11:09.23$vc4f8/valo=5,652.99 2006.224.08:11:09.23#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.224.08:11:09.23#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.224.08:11:09.23#ibcon#ireg 17 cls_cnt 0 2006.224.08:11:09.23#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.224.08:11:09.23#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.224.08:11:09.23#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.224.08:11:09.23#ibcon#enter wrdev, iclass 37, count 0 2006.224.08:11:09.23#ibcon#first serial, iclass 37, count 0 2006.224.08:11:09.23#ibcon#enter sib2, iclass 37, count 0 2006.224.08:11:09.23#ibcon#flushed, iclass 37, count 0 2006.224.08:11:09.23#ibcon#about to write, iclass 37, count 0 2006.224.08:11:09.23#ibcon#wrote, iclass 37, count 0 2006.224.08:11:09.23#ibcon#about to read 3, iclass 37, count 0 2006.224.08:11:09.25#ibcon#read 3, iclass 37, count 0 2006.224.08:11:09.25#ibcon#about to read 4, iclass 37, count 0 2006.224.08:11:09.25#ibcon#read 4, iclass 37, count 0 2006.224.08:11:09.25#ibcon#about to read 5, iclass 37, count 0 2006.224.08:11:09.25#ibcon#read 5, iclass 37, count 0 2006.224.08:11:09.25#ibcon#about to read 6, iclass 37, count 0 2006.224.08:11:09.25#ibcon#read 6, iclass 37, count 0 2006.224.08:11:09.25#ibcon#end of sib2, iclass 37, count 0 2006.224.08:11:09.25#ibcon#*mode == 0, iclass 37, count 0 2006.224.08:11:09.25#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.224.08:11:09.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.224.08:11:09.25#ibcon#*before write, iclass 37, count 0 2006.224.08:11:09.25#ibcon#enter sib2, iclass 37, count 0 2006.224.08:11:09.25#ibcon#flushed, iclass 37, count 0 2006.224.08:11:09.25#ibcon#about to write, iclass 37, count 0 2006.224.08:11:09.25#ibcon#wrote, iclass 37, count 0 2006.224.08:11:09.25#ibcon#about to read 3, iclass 37, count 0 2006.224.08:11:09.29#ibcon#read 3, iclass 37, count 0 2006.224.08:11:09.29#ibcon#about to read 4, iclass 37, count 0 2006.224.08:11:09.29#ibcon#read 4, iclass 37, count 0 2006.224.08:11:09.29#ibcon#about to read 5, iclass 37, count 0 2006.224.08:11:09.29#ibcon#read 5, iclass 37, count 0 2006.224.08:11:09.29#ibcon#about to read 6, iclass 37, count 0 2006.224.08:11:09.29#ibcon#read 6, iclass 37, count 0 2006.224.08:11:09.29#ibcon#end of sib2, iclass 37, count 0 2006.224.08:11:09.29#ibcon#*after write, iclass 37, count 0 2006.224.08:11:09.29#ibcon#*before return 0, iclass 37, count 0 2006.224.08:11:09.29#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.224.08:11:09.29#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.224.08:11:09.29#ibcon#about to clear, iclass 37 cls_cnt 0 2006.224.08:11:09.29#ibcon#cleared, iclass 37 cls_cnt 0 2006.224.08:11:09.29$vc4f8/va=5,7 2006.224.08:11:09.29#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.224.08:11:09.29#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.224.08:11:09.29#ibcon#ireg 11 cls_cnt 2 2006.224.08:11:09.29#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.224.08:11:09.35#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.224.08:11:09.35#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.224.08:11:09.35#ibcon#enter wrdev, iclass 39, count 2 2006.224.08:11:09.35#ibcon#first serial, iclass 39, count 2 2006.224.08:11:09.35#ibcon#enter sib2, iclass 39, count 2 2006.224.08:11:09.35#ibcon#flushed, iclass 39, count 2 2006.224.08:11:09.35#ibcon#about to write, iclass 39, count 2 2006.224.08:11:09.35#ibcon#wrote, iclass 39, count 2 2006.224.08:11:09.35#ibcon#about to read 3, iclass 39, count 2 2006.224.08:11:09.37#ibcon#read 3, iclass 39, count 2 2006.224.08:11:09.37#ibcon#about to read 4, iclass 39, count 2 2006.224.08:11:09.37#ibcon#read 4, iclass 39, count 2 2006.224.08:11:09.37#ibcon#about to read 5, iclass 39, count 2 2006.224.08:11:09.37#ibcon#read 5, iclass 39, count 2 2006.224.08:11:09.37#ibcon#about to read 6, iclass 39, count 2 2006.224.08:11:09.37#ibcon#read 6, iclass 39, count 2 2006.224.08:11:09.37#ibcon#end of sib2, iclass 39, count 2 2006.224.08:11:09.37#ibcon#*mode == 0, iclass 39, count 2 2006.224.08:11:09.37#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.224.08:11:09.37#ibcon#[25=AT05-07\r\n] 2006.224.08:11:09.37#ibcon#*before write, iclass 39, count 2 2006.224.08:11:09.37#ibcon#enter sib2, iclass 39, count 2 2006.224.08:11:09.37#ibcon#flushed, iclass 39, count 2 2006.224.08:11:09.37#ibcon#about to write, iclass 39, count 2 2006.224.08:11:09.37#ibcon#wrote, iclass 39, count 2 2006.224.08:11:09.37#ibcon#about to read 3, iclass 39, count 2 2006.224.08:11:09.40#ibcon#read 3, iclass 39, count 2 2006.224.08:11:09.40#ibcon#about to read 4, iclass 39, count 2 2006.224.08:11:09.40#ibcon#read 4, iclass 39, count 2 2006.224.08:11:09.40#ibcon#about to read 5, iclass 39, count 2 2006.224.08:11:09.40#ibcon#read 5, iclass 39, count 2 2006.224.08:11:09.40#ibcon#about to read 6, iclass 39, count 2 2006.224.08:11:09.40#ibcon#read 6, iclass 39, count 2 2006.224.08:11:09.40#ibcon#end of sib2, iclass 39, count 2 2006.224.08:11:09.40#ibcon#*after write, iclass 39, count 2 2006.224.08:11:09.40#ibcon#*before return 0, iclass 39, count 2 2006.224.08:11:09.40#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.224.08:11:09.40#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.224.08:11:09.40#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.224.08:11:09.40#ibcon#ireg 7 cls_cnt 0 2006.224.08:11:09.40#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.224.08:11:09.52#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.224.08:11:09.52#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.224.08:11:09.52#ibcon#enter wrdev, iclass 39, count 0 2006.224.08:11:09.52#ibcon#first serial, iclass 39, count 0 2006.224.08:11:09.52#ibcon#enter sib2, iclass 39, count 0 2006.224.08:11:09.52#ibcon#flushed, iclass 39, count 0 2006.224.08:11:09.52#ibcon#about to write, iclass 39, count 0 2006.224.08:11:09.52#ibcon#wrote, iclass 39, count 0 2006.224.08:11:09.52#ibcon#about to read 3, iclass 39, count 0 2006.224.08:11:09.54#ibcon#read 3, iclass 39, count 0 2006.224.08:11:09.54#ibcon#about to read 4, iclass 39, count 0 2006.224.08:11:09.54#ibcon#read 4, iclass 39, count 0 2006.224.08:11:09.54#ibcon#about to read 5, iclass 39, count 0 2006.224.08:11:09.54#ibcon#read 5, iclass 39, count 0 2006.224.08:11:09.54#ibcon#about to read 6, iclass 39, count 0 2006.224.08:11:09.54#ibcon#read 6, iclass 39, count 0 2006.224.08:11:09.54#ibcon#end of sib2, iclass 39, count 0 2006.224.08:11:09.54#ibcon#*mode == 0, iclass 39, count 0 2006.224.08:11:09.54#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.224.08:11:09.54#ibcon#[25=USB\r\n] 2006.224.08:11:09.54#ibcon#*before write, iclass 39, count 0 2006.224.08:11:09.54#ibcon#enter sib2, iclass 39, count 0 2006.224.08:11:09.54#ibcon#flushed, iclass 39, count 0 2006.224.08:11:09.54#ibcon#about to write, iclass 39, count 0 2006.224.08:11:09.54#ibcon#wrote, iclass 39, count 0 2006.224.08:11:09.54#ibcon#about to read 3, iclass 39, count 0 2006.224.08:11:09.57#ibcon#read 3, iclass 39, count 0 2006.224.08:11:09.57#ibcon#about to read 4, iclass 39, count 0 2006.224.08:11:09.57#ibcon#read 4, iclass 39, count 0 2006.224.08:11:09.57#ibcon#about to read 5, iclass 39, count 0 2006.224.08:11:09.57#ibcon#read 5, iclass 39, count 0 2006.224.08:11:09.57#ibcon#about to read 6, iclass 39, count 0 2006.224.08:11:09.57#ibcon#read 6, iclass 39, count 0 2006.224.08:11:09.57#ibcon#end of sib2, iclass 39, count 0 2006.224.08:11:09.57#ibcon#*after write, iclass 39, count 0 2006.224.08:11:09.57#ibcon#*before return 0, iclass 39, count 0 2006.224.08:11:09.57#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.224.08:11:09.57#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.224.08:11:09.57#ibcon#about to clear, iclass 39 cls_cnt 0 2006.224.08:11:09.57#ibcon#cleared, iclass 39 cls_cnt 0 2006.224.08:11:09.57$vc4f8/valo=6,772.99 2006.224.08:11:09.57#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.224.08:11:09.57#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.224.08:11:09.57#ibcon#ireg 17 cls_cnt 0 2006.224.08:11:09.57#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.224.08:11:09.57#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.224.08:11:09.57#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.224.08:11:09.57#ibcon#enter wrdev, iclass 3, count 0 2006.224.08:11:09.57#ibcon#first serial, iclass 3, count 0 2006.224.08:11:09.57#ibcon#enter sib2, iclass 3, count 0 2006.224.08:11:09.57#ibcon#flushed, iclass 3, count 0 2006.224.08:11:09.57#ibcon#about to write, iclass 3, count 0 2006.224.08:11:09.57#ibcon#wrote, iclass 3, count 0 2006.224.08:11:09.57#ibcon#about to read 3, iclass 3, count 0 2006.224.08:11:09.59#ibcon#read 3, iclass 3, count 0 2006.224.08:11:09.59#ibcon#about to read 4, iclass 3, count 0 2006.224.08:11:09.59#ibcon#read 4, iclass 3, count 0 2006.224.08:11:09.59#ibcon#about to read 5, iclass 3, count 0 2006.224.08:11:09.59#ibcon#read 5, iclass 3, count 0 2006.224.08:11:09.59#ibcon#about to read 6, iclass 3, count 0 2006.224.08:11:09.59#ibcon#read 6, iclass 3, count 0 2006.224.08:11:09.59#ibcon#end of sib2, iclass 3, count 0 2006.224.08:11:09.59#ibcon#*mode == 0, iclass 3, count 0 2006.224.08:11:09.59#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.224.08:11:09.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.224.08:11:09.59#ibcon#*before write, iclass 3, count 0 2006.224.08:11:09.59#ibcon#enter sib2, iclass 3, count 0 2006.224.08:11:09.59#ibcon#flushed, iclass 3, count 0 2006.224.08:11:09.59#ibcon#about to write, iclass 3, count 0 2006.224.08:11:09.59#ibcon#wrote, iclass 3, count 0 2006.224.08:11:09.59#ibcon#about to read 3, iclass 3, count 0 2006.224.08:11:09.64#ibcon#read 3, iclass 3, count 0 2006.224.08:11:09.64#ibcon#about to read 4, iclass 3, count 0 2006.224.08:11:09.64#ibcon#read 4, iclass 3, count 0 2006.224.08:11:09.64#ibcon#about to read 5, iclass 3, count 0 2006.224.08:11:09.64#ibcon#read 5, iclass 3, count 0 2006.224.08:11:09.64#ibcon#about to read 6, iclass 3, count 0 2006.224.08:11:09.64#ibcon#read 6, iclass 3, count 0 2006.224.08:11:09.64#ibcon#end of sib2, iclass 3, count 0 2006.224.08:11:09.64#ibcon#*after write, iclass 3, count 0 2006.224.08:11:09.64#ibcon#*before return 0, iclass 3, count 0 2006.224.08:11:09.64#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.224.08:11:09.64#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.224.08:11:09.64#ibcon#about to clear, iclass 3 cls_cnt 0 2006.224.08:11:09.64#ibcon#cleared, iclass 3 cls_cnt 0 2006.224.08:11:09.64$vc4f8/va=6,6 2006.224.08:11:09.64#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.224.08:11:09.64#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.224.08:11:09.64#ibcon#ireg 11 cls_cnt 2 2006.224.08:11:09.64#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.224.08:11:09.69#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.224.08:11:09.69#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.224.08:11:09.69#ibcon#enter wrdev, iclass 5, count 2 2006.224.08:11:09.69#ibcon#first serial, iclass 5, count 2 2006.224.08:11:09.69#ibcon#enter sib2, iclass 5, count 2 2006.224.08:11:09.69#ibcon#flushed, iclass 5, count 2 2006.224.08:11:09.69#ibcon#about to write, iclass 5, count 2 2006.224.08:11:09.69#ibcon#wrote, iclass 5, count 2 2006.224.08:11:09.69#ibcon#about to read 3, iclass 5, count 2 2006.224.08:11:09.71#ibcon#read 3, iclass 5, count 2 2006.224.08:11:09.71#ibcon#about to read 4, iclass 5, count 2 2006.224.08:11:09.71#ibcon#read 4, iclass 5, count 2 2006.224.08:11:09.71#ibcon#about to read 5, iclass 5, count 2 2006.224.08:11:09.71#ibcon#read 5, iclass 5, count 2 2006.224.08:11:09.71#ibcon#about to read 6, iclass 5, count 2 2006.224.08:11:09.71#ibcon#read 6, iclass 5, count 2 2006.224.08:11:09.71#ibcon#end of sib2, iclass 5, count 2 2006.224.08:11:09.71#ibcon#*mode == 0, iclass 5, count 2 2006.224.08:11:09.71#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.224.08:11:09.71#ibcon#[25=AT06-06\r\n] 2006.224.08:11:09.71#ibcon#*before write, iclass 5, count 2 2006.224.08:11:09.71#ibcon#enter sib2, iclass 5, count 2 2006.224.08:11:09.71#ibcon#flushed, iclass 5, count 2 2006.224.08:11:09.71#ibcon#about to write, iclass 5, count 2 2006.224.08:11:09.71#ibcon#wrote, iclass 5, count 2 2006.224.08:11:09.71#ibcon#about to read 3, iclass 5, count 2 2006.224.08:11:09.74#ibcon#read 3, iclass 5, count 2 2006.224.08:11:09.74#ibcon#about to read 4, iclass 5, count 2 2006.224.08:11:09.74#ibcon#read 4, iclass 5, count 2 2006.224.08:11:09.74#ibcon#about to read 5, iclass 5, count 2 2006.224.08:11:09.74#ibcon#read 5, iclass 5, count 2 2006.224.08:11:09.74#ibcon#about to read 6, iclass 5, count 2 2006.224.08:11:09.74#ibcon#read 6, iclass 5, count 2 2006.224.08:11:09.74#ibcon#end of sib2, iclass 5, count 2 2006.224.08:11:09.74#ibcon#*after write, iclass 5, count 2 2006.224.08:11:09.74#ibcon#*before return 0, iclass 5, count 2 2006.224.08:11:09.74#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.224.08:11:09.74#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.224.08:11:09.74#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.224.08:11:09.74#ibcon#ireg 7 cls_cnt 0 2006.224.08:11:09.74#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.224.08:11:09.86#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.224.08:11:09.86#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.224.08:11:09.86#ibcon#enter wrdev, iclass 5, count 0 2006.224.08:11:09.86#ibcon#first serial, iclass 5, count 0 2006.224.08:11:09.86#ibcon#enter sib2, iclass 5, count 0 2006.224.08:11:09.86#ibcon#flushed, iclass 5, count 0 2006.224.08:11:09.86#ibcon#about to write, iclass 5, count 0 2006.224.08:11:09.86#ibcon#wrote, iclass 5, count 0 2006.224.08:11:09.86#ibcon#about to read 3, iclass 5, count 0 2006.224.08:11:09.88#ibcon#read 3, iclass 5, count 0 2006.224.08:11:09.88#ibcon#about to read 4, iclass 5, count 0 2006.224.08:11:09.88#ibcon#read 4, iclass 5, count 0 2006.224.08:11:09.88#ibcon#about to read 5, iclass 5, count 0 2006.224.08:11:09.88#ibcon#read 5, iclass 5, count 0 2006.224.08:11:09.88#ibcon#about to read 6, iclass 5, count 0 2006.224.08:11:09.88#ibcon#read 6, iclass 5, count 0 2006.224.08:11:09.88#ibcon#end of sib2, iclass 5, count 0 2006.224.08:11:09.88#ibcon#*mode == 0, iclass 5, count 0 2006.224.08:11:09.88#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.224.08:11:09.88#ibcon#[25=USB\r\n] 2006.224.08:11:09.88#ibcon#*before write, iclass 5, count 0 2006.224.08:11:09.88#ibcon#enter sib2, iclass 5, count 0 2006.224.08:11:09.88#ibcon#flushed, iclass 5, count 0 2006.224.08:11:09.88#ibcon#about to write, iclass 5, count 0 2006.224.08:11:09.88#ibcon#wrote, iclass 5, count 0 2006.224.08:11:09.88#ibcon#about to read 3, iclass 5, count 0 2006.224.08:11:09.91#ibcon#read 3, iclass 5, count 0 2006.224.08:11:09.91#ibcon#about to read 4, iclass 5, count 0 2006.224.08:11:09.91#ibcon#read 4, iclass 5, count 0 2006.224.08:11:09.91#ibcon#about to read 5, iclass 5, count 0 2006.224.08:11:09.91#ibcon#read 5, iclass 5, count 0 2006.224.08:11:09.91#ibcon#about to read 6, iclass 5, count 0 2006.224.08:11:09.91#ibcon#read 6, iclass 5, count 0 2006.224.08:11:09.91#ibcon#end of sib2, iclass 5, count 0 2006.224.08:11:09.91#ibcon#*after write, iclass 5, count 0 2006.224.08:11:09.91#ibcon#*before return 0, iclass 5, count 0 2006.224.08:11:09.91#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.224.08:11:09.91#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.224.08:11:09.91#ibcon#about to clear, iclass 5 cls_cnt 0 2006.224.08:11:09.91#ibcon#cleared, iclass 5 cls_cnt 0 2006.224.08:11:09.91$vc4f8/valo=7,832.99 2006.224.08:11:09.91#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.224.08:11:09.91#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.224.08:11:09.91#ibcon#ireg 17 cls_cnt 0 2006.224.08:11:09.91#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.224.08:11:09.91#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.224.08:11:09.91#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.224.08:11:09.91#ibcon#enter wrdev, iclass 7, count 0 2006.224.08:11:09.91#ibcon#first serial, iclass 7, count 0 2006.224.08:11:09.91#ibcon#enter sib2, iclass 7, count 0 2006.224.08:11:09.91#ibcon#flushed, iclass 7, count 0 2006.224.08:11:09.91#ibcon#about to write, iclass 7, count 0 2006.224.08:11:09.91#ibcon#wrote, iclass 7, count 0 2006.224.08:11:09.91#ibcon#about to read 3, iclass 7, count 0 2006.224.08:11:09.93#ibcon#read 3, iclass 7, count 0 2006.224.08:11:09.93#ibcon#about to read 4, iclass 7, count 0 2006.224.08:11:09.93#ibcon#read 4, iclass 7, count 0 2006.224.08:11:09.93#ibcon#about to read 5, iclass 7, count 0 2006.224.08:11:09.93#ibcon#read 5, iclass 7, count 0 2006.224.08:11:09.93#ibcon#about to read 6, iclass 7, count 0 2006.224.08:11:09.93#ibcon#read 6, iclass 7, count 0 2006.224.08:11:09.93#ibcon#end of sib2, iclass 7, count 0 2006.224.08:11:09.93#ibcon#*mode == 0, iclass 7, count 0 2006.224.08:11:09.93#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.224.08:11:09.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.224.08:11:09.93#ibcon#*before write, iclass 7, count 0 2006.224.08:11:09.93#ibcon#enter sib2, iclass 7, count 0 2006.224.08:11:09.93#ibcon#flushed, iclass 7, count 0 2006.224.08:11:09.93#ibcon#about to write, iclass 7, count 0 2006.224.08:11:09.93#ibcon#wrote, iclass 7, count 0 2006.224.08:11:09.93#ibcon#about to read 3, iclass 7, count 0 2006.224.08:11:09.97#ibcon#read 3, iclass 7, count 0 2006.224.08:11:09.97#ibcon#about to read 4, iclass 7, count 0 2006.224.08:11:09.97#ibcon#read 4, iclass 7, count 0 2006.224.08:11:09.97#ibcon#about to read 5, iclass 7, count 0 2006.224.08:11:09.97#ibcon#read 5, iclass 7, count 0 2006.224.08:11:09.97#ibcon#about to read 6, iclass 7, count 0 2006.224.08:11:09.97#ibcon#read 6, iclass 7, count 0 2006.224.08:11:09.97#ibcon#end of sib2, iclass 7, count 0 2006.224.08:11:09.97#ibcon#*after write, iclass 7, count 0 2006.224.08:11:09.97#ibcon#*before return 0, iclass 7, count 0 2006.224.08:11:09.97#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.224.08:11:09.97#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.224.08:11:09.97#ibcon#about to clear, iclass 7 cls_cnt 0 2006.224.08:11:09.97#ibcon#cleared, iclass 7 cls_cnt 0 2006.224.08:11:09.97$vc4f8/va=7,6 2006.224.08:11:09.97#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.224.08:11:09.97#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.224.08:11:09.97#ibcon#ireg 11 cls_cnt 2 2006.224.08:11:09.97#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.224.08:11:10.03#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.224.08:11:10.03#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.224.08:11:10.03#ibcon#enter wrdev, iclass 11, count 2 2006.224.08:11:10.03#ibcon#first serial, iclass 11, count 2 2006.224.08:11:10.03#ibcon#enter sib2, iclass 11, count 2 2006.224.08:11:10.03#ibcon#flushed, iclass 11, count 2 2006.224.08:11:10.03#ibcon#about to write, iclass 11, count 2 2006.224.08:11:10.03#ibcon#wrote, iclass 11, count 2 2006.224.08:11:10.03#ibcon#about to read 3, iclass 11, count 2 2006.224.08:11:10.05#ibcon#read 3, iclass 11, count 2 2006.224.08:11:10.05#ibcon#about to read 4, iclass 11, count 2 2006.224.08:11:10.05#ibcon#read 4, iclass 11, count 2 2006.224.08:11:10.05#ibcon#about to read 5, iclass 11, count 2 2006.224.08:11:10.05#ibcon#read 5, iclass 11, count 2 2006.224.08:11:10.05#ibcon#about to read 6, iclass 11, count 2 2006.224.08:11:10.05#ibcon#read 6, iclass 11, count 2 2006.224.08:11:10.05#ibcon#end of sib2, iclass 11, count 2 2006.224.08:11:10.05#ibcon#*mode == 0, iclass 11, count 2 2006.224.08:11:10.05#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.224.08:11:10.05#ibcon#[25=AT07-06\r\n] 2006.224.08:11:10.05#ibcon#*before write, iclass 11, count 2 2006.224.08:11:10.05#ibcon#enter sib2, iclass 11, count 2 2006.224.08:11:10.05#ibcon#flushed, iclass 11, count 2 2006.224.08:11:10.05#ibcon#about to write, iclass 11, count 2 2006.224.08:11:10.05#ibcon#wrote, iclass 11, count 2 2006.224.08:11:10.05#ibcon#about to read 3, iclass 11, count 2 2006.224.08:11:10.08#ibcon#read 3, iclass 11, count 2 2006.224.08:11:10.08#ibcon#about to read 4, iclass 11, count 2 2006.224.08:11:10.08#ibcon#read 4, iclass 11, count 2 2006.224.08:11:10.08#ibcon#about to read 5, iclass 11, count 2 2006.224.08:11:10.08#ibcon#read 5, iclass 11, count 2 2006.224.08:11:10.08#ibcon#about to read 6, iclass 11, count 2 2006.224.08:11:10.08#ibcon#read 6, iclass 11, count 2 2006.224.08:11:10.08#ibcon#end of sib2, iclass 11, count 2 2006.224.08:11:10.08#ibcon#*after write, iclass 11, count 2 2006.224.08:11:10.08#ibcon#*before return 0, iclass 11, count 2 2006.224.08:11:10.08#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.224.08:11:10.08#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.224.08:11:10.08#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.224.08:11:10.08#ibcon#ireg 7 cls_cnt 0 2006.224.08:11:10.08#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.224.08:11:10.20#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.224.08:11:10.20#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.224.08:11:10.20#ibcon#enter wrdev, iclass 11, count 0 2006.224.08:11:10.20#ibcon#first serial, iclass 11, count 0 2006.224.08:11:10.20#ibcon#enter sib2, iclass 11, count 0 2006.224.08:11:10.20#ibcon#flushed, iclass 11, count 0 2006.224.08:11:10.20#ibcon#about to write, iclass 11, count 0 2006.224.08:11:10.20#ibcon#wrote, iclass 11, count 0 2006.224.08:11:10.20#ibcon#about to read 3, iclass 11, count 0 2006.224.08:11:10.22#ibcon#read 3, iclass 11, count 0 2006.224.08:11:10.22#ibcon#about to read 4, iclass 11, count 0 2006.224.08:11:10.22#ibcon#read 4, iclass 11, count 0 2006.224.08:11:10.22#ibcon#about to read 5, iclass 11, count 0 2006.224.08:11:10.22#ibcon#read 5, iclass 11, count 0 2006.224.08:11:10.22#ibcon#about to read 6, iclass 11, count 0 2006.224.08:11:10.22#ibcon#read 6, iclass 11, count 0 2006.224.08:11:10.22#ibcon#end of sib2, iclass 11, count 0 2006.224.08:11:10.22#ibcon#*mode == 0, iclass 11, count 0 2006.224.08:11:10.22#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.224.08:11:10.22#ibcon#[25=USB\r\n] 2006.224.08:11:10.22#ibcon#*before write, iclass 11, count 0 2006.224.08:11:10.22#ibcon#enter sib2, iclass 11, count 0 2006.224.08:11:10.22#ibcon#flushed, iclass 11, count 0 2006.224.08:11:10.22#ibcon#about to write, iclass 11, count 0 2006.224.08:11:10.22#ibcon#wrote, iclass 11, count 0 2006.224.08:11:10.22#ibcon#about to read 3, iclass 11, count 0 2006.224.08:11:10.25#ibcon#read 3, iclass 11, count 0 2006.224.08:11:10.25#ibcon#about to read 4, iclass 11, count 0 2006.224.08:11:10.25#ibcon#read 4, iclass 11, count 0 2006.224.08:11:10.25#ibcon#about to read 5, iclass 11, count 0 2006.224.08:11:10.25#ibcon#read 5, iclass 11, count 0 2006.224.08:11:10.25#ibcon#about to read 6, iclass 11, count 0 2006.224.08:11:10.25#ibcon#read 6, iclass 11, count 0 2006.224.08:11:10.25#ibcon#end of sib2, iclass 11, count 0 2006.224.08:11:10.25#ibcon#*after write, iclass 11, count 0 2006.224.08:11:10.25#ibcon#*before return 0, iclass 11, count 0 2006.224.08:11:10.25#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.224.08:11:10.25#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.224.08:11:10.25#ibcon#about to clear, iclass 11 cls_cnt 0 2006.224.08:11:10.25#ibcon#cleared, iclass 11 cls_cnt 0 2006.224.08:11:10.25$vc4f8/valo=8,852.99 2006.224.08:11:10.25#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.224.08:11:10.25#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.224.08:11:10.25#ibcon#ireg 17 cls_cnt 0 2006.224.08:11:10.25#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.224.08:11:10.25#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.224.08:11:10.25#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.224.08:11:10.25#ibcon#enter wrdev, iclass 13, count 0 2006.224.08:11:10.25#ibcon#first serial, iclass 13, count 0 2006.224.08:11:10.25#ibcon#enter sib2, iclass 13, count 0 2006.224.08:11:10.25#ibcon#flushed, iclass 13, count 0 2006.224.08:11:10.25#ibcon#about to write, iclass 13, count 0 2006.224.08:11:10.25#ibcon#wrote, iclass 13, count 0 2006.224.08:11:10.25#ibcon#about to read 3, iclass 13, count 0 2006.224.08:11:10.27#ibcon#read 3, iclass 13, count 0 2006.224.08:11:10.27#ibcon#about to read 4, iclass 13, count 0 2006.224.08:11:10.27#ibcon#read 4, iclass 13, count 0 2006.224.08:11:10.27#ibcon#about to read 5, iclass 13, count 0 2006.224.08:11:10.27#ibcon#read 5, iclass 13, count 0 2006.224.08:11:10.27#ibcon#about to read 6, iclass 13, count 0 2006.224.08:11:10.27#ibcon#read 6, iclass 13, count 0 2006.224.08:11:10.27#ibcon#end of sib2, iclass 13, count 0 2006.224.08:11:10.27#ibcon#*mode == 0, iclass 13, count 0 2006.224.08:11:10.27#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.224.08:11:10.27#ibcon#[26=FRQ=08,852.99\r\n] 2006.224.08:11:10.27#ibcon#*before write, iclass 13, count 0 2006.224.08:11:10.27#ibcon#enter sib2, iclass 13, count 0 2006.224.08:11:10.27#ibcon#flushed, iclass 13, count 0 2006.224.08:11:10.27#ibcon#about to write, iclass 13, count 0 2006.224.08:11:10.27#ibcon#wrote, iclass 13, count 0 2006.224.08:11:10.27#ibcon#about to read 3, iclass 13, count 0 2006.224.08:11:10.31#ibcon#read 3, iclass 13, count 0 2006.224.08:11:10.31#ibcon#about to read 4, iclass 13, count 0 2006.224.08:11:10.31#ibcon#read 4, iclass 13, count 0 2006.224.08:11:10.31#ibcon#about to read 5, iclass 13, count 0 2006.224.08:11:10.31#ibcon#read 5, iclass 13, count 0 2006.224.08:11:10.31#ibcon#about to read 6, iclass 13, count 0 2006.224.08:11:10.31#ibcon#read 6, iclass 13, count 0 2006.224.08:11:10.31#ibcon#end of sib2, iclass 13, count 0 2006.224.08:11:10.31#ibcon#*after write, iclass 13, count 0 2006.224.08:11:10.31#ibcon#*before return 0, iclass 13, count 0 2006.224.08:11:10.31#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.224.08:11:10.31#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.224.08:11:10.31#ibcon#about to clear, iclass 13 cls_cnt 0 2006.224.08:11:10.31#ibcon#cleared, iclass 13 cls_cnt 0 2006.224.08:11:10.31$vc4f8/va=8,7 2006.224.08:11:10.31#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.224.08:11:10.31#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.224.08:11:10.31#ibcon#ireg 11 cls_cnt 2 2006.224.08:11:10.31#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.224.08:11:10.37#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.224.08:11:10.37#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.224.08:11:10.37#ibcon#enter wrdev, iclass 15, count 2 2006.224.08:11:10.37#ibcon#first serial, iclass 15, count 2 2006.224.08:11:10.37#ibcon#enter sib2, iclass 15, count 2 2006.224.08:11:10.37#ibcon#flushed, iclass 15, count 2 2006.224.08:11:10.37#ibcon#about to write, iclass 15, count 2 2006.224.08:11:10.37#ibcon#wrote, iclass 15, count 2 2006.224.08:11:10.37#ibcon#about to read 3, iclass 15, count 2 2006.224.08:11:10.39#ibcon#read 3, iclass 15, count 2 2006.224.08:11:10.39#ibcon#about to read 4, iclass 15, count 2 2006.224.08:11:10.39#ibcon#read 4, iclass 15, count 2 2006.224.08:11:10.39#ibcon#about to read 5, iclass 15, count 2 2006.224.08:11:10.39#ibcon#read 5, iclass 15, count 2 2006.224.08:11:10.39#ibcon#about to read 6, iclass 15, count 2 2006.224.08:11:10.39#ibcon#read 6, iclass 15, count 2 2006.224.08:11:10.39#ibcon#end of sib2, iclass 15, count 2 2006.224.08:11:10.39#ibcon#*mode == 0, iclass 15, count 2 2006.224.08:11:10.39#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.224.08:11:10.39#ibcon#[25=AT08-07\r\n] 2006.224.08:11:10.39#ibcon#*before write, iclass 15, count 2 2006.224.08:11:10.39#ibcon#enter sib2, iclass 15, count 2 2006.224.08:11:10.39#ibcon#flushed, iclass 15, count 2 2006.224.08:11:10.39#ibcon#about to write, iclass 15, count 2 2006.224.08:11:10.39#ibcon#wrote, iclass 15, count 2 2006.224.08:11:10.39#ibcon#about to read 3, iclass 15, count 2 2006.224.08:11:10.43#ibcon#read 3, iclass 15, count 2 2006.224.08:11:10.43#ibcon#about to read 4, iclass 15, count 2 2006.224.08:11:10.43#ibcon#read 4, iclass 15, count 2 2006.224.08:11:10.43#ibcon#about to read 5, iclass 15, count 2 2006.224.08:11:10.43#ibcon#read 5, iclass 15, count 2 2006.224.08:11:10.43#ibcon#about to read 6, iclass 15, count 2 2006.224.08:11:10.43#ibcon#read 6, iclass 15, count 2 2006.224.08:11:10.43#ibcon#end of sib2, iclass 15, count 2 2006.224.08:11:10.43#ibcon#*after write, iclass 15, count 2 2006.224.08:11:10.43#ibcon#*before return 0, iclass 15, count 2 2006.224.08:11:10.43#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.224.08:11:10.43#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.224.08:11:10.43#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.224.08:11:10.43#ibcon#ireg 7 cls_cnt 0 2006.224.08:11:10.43#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.224.08:11:10.55#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.224.08:11:10.55#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.224.08:11:10.55#ibcon#enter wrdev, iclass 15, count 0 2006.224.08:11:10.55#ibcon#first serial, iclass 15, count 0 2006.224.08:11:10.55#ibcon#enter sib2, iclass 15, count 0 2006.224.08:11:10.55#ibcon#flushed, iclass 15, count 0 2006.224.08:11:10.55#ibcon#about to write, iclass 15, count 0 2006.224.08:11:10.55#ibcon#wrote, iclass 15, count 0 2006.224.08:11:10.55#ibcon#about to read 3, iclass 15, count 0 2006.224.08:11:10.57#ibcon#read 3, iclass 15, count 0 2006.224.08:11:10.57#ibcon#about to read 4, iclass 15, count 0 2006.224.08:11:10.57#ibcon#read 4, iclass 15, count 0 2006.224.08:11:10.57#ibcon#about to read 5, iclass 15, count 0 2006.224.08:11:10.57#ibcon#read 5, iclass 15, count 0 2006.224.08:11:10.57#ibcon#about to read 6, iclass 15, count 0 2006.224.08:11:10.57#ibcon#read 6, iclass 15, count 0 2006.224.08:11:10.57#ibcon#end of sib2, iclass 15, count 0 2006.224.08:11:10.57#ibcon#*mode == 0, iclass 15, count 0 2006.224.08:11:10.57#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.224.08:11:10.57#ibcon#[25=USB\r\n] 2006.224.08:11:10.57#ibcon#*before write, iclass 15, count 0 2006.224.08:11:10.57#ibcon#enter sib2, iclass 15, count 0 2006.224.08:11:10.57#ibcon#flushed, iclass 15, count 0 2006.224.08:11:10.57#ibcon#about to write, iclass 15, count 0 2006.224.08:11:10.57#ibcon#wrote, iclass 15, count 0 2006.224.08:11:10.57#ibcon#about to read 3, iclass 15, count 0 2006.224.08:11:10.60#ibcon#read 3, iclass 15, count 0 2006.224.08:11:10.60#ibcon#about to read 4, iclass 15, count 0 2006.224.08:11:10.60#ibcon#read 4, iclass 15, count 0 2006.224.08:11:10.60#ibcon#about to read 5, iclass 15, count 0 2006.224.08:11:10.60#ibcon#read 5, iclass 15, count 0 2006.224.08:11:10.60#ibcon#about to read 6, iclass 15, count 0 2006.224.08:11:10.60#ibcon#read 6, iclass 15, count 0 2006.224.08:11:10.60#ibcon#end of sib2, iclass 15, count 0 2006.224.08:11:10.60#ibcon#*after write, iclass 15, count 0 2006.224.08:11:10.60#ibcon#*before return 0, iclass 15, count 0 2006.224.08:11:10.60#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.224.08:11:10.60#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.224.08:11:10.60#ibcon#about to clear, iclass 15 cls_cnt 0 2006.224.08:11:10.60#ibcon#cleared, iclass 15 cls_cnt 0 2006.224.08:11:10.60$vc4f8/vblo=1,632.99 2006.224.08:11:10.60#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.224.08:11:10.60#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.224.08:11:10.60#ibcon#ireg 17 cls_cnt 0 2006.224.08:11:10.60#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.224.08:11:10.60#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.224.08:11:10.60#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.224.08:11:10.60#ibcon#enter wrdev, iclass 17, count 0 2006.224.08:11:10.60#ibcon#first serial, iclass 17, count 0 2006.224.08:11:10.60#ibcon#enter sib2, iclass 17, count 0 2006.224.08:11:10.60#ibcon#flushed, iclass 17, count 0 2006.224.08:11:10.60#ibcon#about to write, iclass 17, count 0 2006.224.08:11:10.60#ibcon#wrote, iclass 17, count 0 2006.224.08:11:10.60#ibcon#about to read 3, iclass 17, count 0 2006.224.08:11:10.62#ibcon#read 3, iclass 17, count 0 2006.224.08:11:10.62#ibcon#about to read 4, iclass 17, count 0 2006.224.08:11:10.62#ibcon#read 4, iclass 17, count 0 2006.224.08:11:10.62#ibcon#about to read 5, iclass 17, count 0 2006.224.08:11:10.62#ibcon#read 5, iclass 17, count 0 2006.224.08:11:10.62#ibcon#about to read 6, iclass 17, count 0 2006.224.08:11:10.62#ibcon#read 6, iclass 17, count 0 2006.224.08:11:10.62#ibcon#end of sib2, iclass 17, count 0 2006.224.08:11:10.62#ibcon#*mode == 0, iclass 17, count 0 2006.224.08:11:10.62#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.224.08:11:10.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.224.08:11:10.62#ibcon#*before write, iclass 17, count 0 2006.224.08:11:10.62#ibcon#enter sib2, iclass 17, count 0 2006.224.08:11:10.62#ibcon#flushed, iclass 17, count 0 2006.224.08:11:10.62#ibcon#about to write, iclass 17, count 0 2006.224.08:11:10.62#ibcon#wrote, iclass 17, count 0 2006.224.08:11:10.62#ibcon#about to read 3, iclass 17, count 0 2006.224.08:11:10.66#ibcon#read 3, iclass 17, count 0 2006.224.08:11:10.66#ibcon#about to read 4, iclass 17, count 0 2006.224.08:11:10.66#ibcon#read 4, iclass 17, count 0 2006.224.08:11:10.66#ibcon#about to read 5, iclass 17, count 0 2006.224.08:11:10.66#ibcon#read 5, iclass 17, count 0 2006.224.08:11:10.66#ibcon#about to read 6, iclass 17, count 0 2006.224.08:11:10.66#ibcon#read 6, iclass 17, count 0 2006.224.08:11:10.66#ibcon#end of sib2, iclass 17, count 0 2006.224.08:11:10.66#ibcon#*after write, iclass 17, count 0 2006.224.08:11:10.66#ibcon#*before return 0, iclass 17, count 0 2006.224.08:11:10.66#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.224.08:11:10.66#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.224.08:11:10.66#ibcon#about to clear, iclass 17 cls_cnt 0 2006.224.08:11:10.66#ibcon#cleared, iclass 17 cls_cnt 0 2006.224.08:11:10.66$vc4f8/vb=1,4 2006.224.08:11:10.66#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.224.08:11:10.66#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.224.08:11:10.66#ibcon#ireg 11 cls_cnt 2 2006.224.08:11:10.66#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.224.08:11:10.66#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.224.08:11:10.66#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.224.08:11:10.66#ibcon#enter wrdev, iclass 19, count 2 2006.224.08:11:10.66#ibcon#first serial, iclass 19, count 2 2006.224.08:11:10.66#ibcon#enter sib2, iclass 19, count 2 2006.224.08:11:10.66#ibcon#flushed, iclass 19, count 2 2006.224.08:11:10.66#ibcon#about to write, iclass 19, count 2 2006.224.08:11:10.66#ibcon#wrote, iclass 19, count 2 2006.224.08:11:10.66#ibcon#about to read 3, iclass 19, count 2 2006.224.08:11:10.68#ibcon#read 3, iclass 19, count 2 2006.224.08:11:10.68#ibcon#about to read 4, iclass 19, count 2 2006.224.08:11:10.68#ibcon#read 4, iclass 19, count 2 2006.224.08:11:10.68#ibcon#about to read 5, iclass 19, count 2 2006.224.08:11:10.68#ibcon#read 5, iclass 19, count 2 2006.224.08:11:10.68#ibcon#about to read 6, iclass 19, count 2 2006.224.08:11:10.68#ibcon#read 6, iclass 19, count 2 2006.224.08:11:10.68#ibcon#end of sib2, iclass 19, count 2 2006.224.08:11:10.68#ibcon#*mode == 0, iclass 19, count 2 2006.224.08:11:10.68#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.224.08:11:10.68#ibcon#[27=AT01-04\r\n] 2006.224.08:11:10.68#ibcon#*before write, iclass 19, count 2 2006.224.08:11:10.68#ibcon#enter sib2, iclass 19, count 2 2006.224.08:11:10.68#ibcon#flushed, iclass 19, count 2 2006.224.08:11:10.68#ibcon#about to write, iclass 19, count 2 2006.224.08:11:10.68#ibcon#wrote, iclass 19, count 2 2006.224.08:11:10.68#ibcon#about to read 3, iclass 19, count 2 2006.224.08:11:10.71#ibcon#read 3, iclass 19, count 2 2006.224.08:11:10.71#ibcon#about to read 4, iclass 19, count 2 2006.224.08:11:10.71#ibcon#read 4, iclass 19, count 2 2006.224.08:11:10.71#ibcon#about to read 5, iclass 19, count 2 2006.224.08:11:10.71#ibcon#read 5, iclass 19, count 2 2006.224.08:11:10.71#ibcon#about to read 6, iclass 19, count 2 2006.224.08:11:10.71#ibcon#read 6, iclass 19, count 2 2006.224.08:11:10.71#ibcon#end of sib2, iclass 19, count 2 2006.224.08:11:10.71#ibcon#*after write, iclass 19, count 2 2006.224.08:11:10.71#ibcon#*before return 0, iclass 19, count 2 2006.224.08:11:10.71#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.224.08:11:10.71#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.224.08:11:10.71#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.224.08:11:10.71#ibcon#ireg 7 cls_cnt 0 2006.224.08:11:10.71#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.224.08:11:10.83#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.224.08:11:10.83#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.224.08:11:10.83#ibcon#enter wrdev, iclass 19, count 0 2006.224.08:11:10.83#ibcon#first serial, iclass 19, count 0 2006.224.08:11:10.83#ibcon#enter sib2, iclass 19, count 0 2006.224.08:11:10.83#ibcon#flushed, iclass 19, count 0 2006.224.08:11:10.83#ibcon#about to write, iclass 19, count 0 2006.224.08:11:10.83#ibcon#wrote, iclass 19, count 0 2006.224.08:11:10.83#ibcon#about to read 3, iclass 19, count 0 2006.224.08:11:10.85#ibcon#read 3, iclass 19, count 0 2006.224.08:11:10.85#ibcon#about to read 4, iclass 19, count 0 2006.224.08:11:10.85#ibcon#read 4, iclass 19, count 0 2006.224.08:11:10.85#ibcon#about to read 5, iclass 19, count 0 2006.224.08:11:10.85#ibcon#read 5, iclass 19, count 0 2006.224.08:11:10.85#ibcon#about to read 6, iclass 19, count 0 2006.224.08:11:10.85#ibcon#read 6, iclass 19, count 0 2006.224.08:11:10.85#ibcon#end of sib2, iclass 19, count 0 2006.224.08:11:10.85#ibcon#*mode == 0, iclass 19, count 0 2006.224.08:11:10.85#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.224.08:11:10.85#ibcon#[27=USB\r\n] 2006.224.08:11:10.85#ibcon#*before write, iclass 19, count 0 2006.224.08:11:10.85#ibcon#enter sib2, iclass 19, count 0 2006.224.08:11:10.85#ibcon#flushed, iclass 19, count 0 2006.224.08:11:10.85#ibcon#about to write, iclass 19, count 0 2006.224.08:11:10.85#ibcon#wrote, iclass 19, count 0 2006.224.08:11:10.85#ibcon#about to read 3, iclass 19, count 0 2006.224.08:11:10.88#ibcon#read 3, iclass 19, count 0 2006.224.08:11:10.88#ibcon#about to read 4, iclass 19, count 0 2006.224.08:11:10.88#ibcon#read 4, iclass 19, count 0 2006.224.08:11:10.88#ibcon#about to read 5, iclass 19, count 0 2006.224.08:11:10.88#ibcon#read 5, iclass 19, count 0 2006.224.08:11:10.88#ibcon#about to read 6, iclass 19, count 0 2006.224.08:11:10.88#ibcon#read 6, iclass 19, count 0 2006.224.08:11:10.88#ibcon#end of sib2, iclass 19, count 0 2006.224.08:11:10.88#ibcon#*after write, iclass 19, count 0 2006.224.08:11:10.88#ibcon#*before return 0, iclass 19, count 0 2006.224.08:11:10.88#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.224.08:11:10.88#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.224.08:11:10.88#ibcon#about to clear, iclass 19 cls_cnt 0 2006.224.08:11:10.88#ibcon#cleared, iclass 19 cls_cnt 0 2006.224.08:11:10.88$vc4f8/vblo=2,640.99 2006.224.08:11:10.88#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.224.08:11:10.88#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.224.08:11:10.88#ibcon#ireg 17 cls_cnt 0 2006.224.08:11:10.88#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.224.08:11:10.88#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.224.08:11:10.88#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.224.08:11:10.88#ibcon#enter wrdev, iclass 21, count 0 2006.224.08:11:10.88#ibcon#first serial, iclass 21, count 0 2006.224.08:11:10.88#ibcon#enter sib2, iclass 21, count 0 2006.224.08:11:10.88#ibcon#flushed, iclass 21, count 0 2006.224.08:11:10.88#ibcon#about to write, iclass 21, count 0 2006.224.08:11:10.88#ibcon#wrote, iclass 21, count 0 2006.224.08:11:10.88#ibcon#about to read 3, iclass 21, count 0 2006.224.08:11:10.90#ibcon#read 3, iclass 21, count 0 2006.224.08:11:10.90#ibcon#about to read 4, iclass 21, count 0 2006.224.08:11:10.90#ibcon#read 4, iclass 21, count 0 2006.224.08:11:10.90#ibcon#about to read 5, iclass 21, count 0 2006.224.08:11:10.90#ibcon#read 5, iclass 21, count 0 2006.224.08:11:10.90#ibcon#about to read 6, iclass 21, count 0 2006.224.08:11:10.90#ibcon#read 6, iclass 21, count 0 2006.224.08:11:10.90#ibcon#end of sib2, iclass 21, count 0 2006.224.08:11:10.90#ibcon#*mode == 0, iclass 21, count 0 2006.224.08:11:10.90#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.224.08:11:10.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.224.08:11:10.90#ibcon#*before write, iclass 21, count 0 2006.224.08:11:10.90#ibcon#enter sib2, iclass 21, count 0 2006.224.08:11:10.90#ibcon#flushed, iclass 21, count 0 2006.224.08:11:10.90#ibcon#about to write, iclass 21, count 0 2006.224.08:11:10.90#ibcon#wrote, iclass 21, count 0 2006.224.08:11:10.90#ibcon#about to read 3, iclass 21, count 0 2006.224.08:11:10.94#ibcon#read 3, iclass 21, count 0 2006.224.08:11:10.94#ibcon#about to read 4, iclass 21, count 0 2006.224.08:11:10.94#ibcon#read 4, iclass 21, count 0 2006.224.08:11:10.94#ibcon#about to read 5, iclass 21, count 0 2006.224.08:11:10.94#ibcon#read 5, iclass 21, count 0 2006.224.08:11:10.94#ibcon#about to read 6, iclass 21, count 0 2006.224.08:11:10.94#ibcon#read 6, iclass 21, count 0 2006.224.08:11:10.94#ibcon#end of sib2, iclass 21, count 0 2006.224.08:11:10.94#ibcon#*after write, iclass 21, count 0 2006.224.08:11:10.94#ibcon#*before return 0, iclass 21, count 0 2006.224.08:11:10.94#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.224.08:11:10.94#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.224.08:11:10.94#ibcon#about to clear, iclass 21 cls_cnt 0 2006.224.08:11:10.94#ibcon#cleared, iclass 21 cls_cnt 0 2006.224.08:11:10.94$vc4f8/vb=2,4 2006.224.08:11:10.94#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.224.08:11:10.94#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.224.08:11:10.94#ibcon#ireg 11 cls_cnt 2 2006.224.08:11:10.94#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.224.08:11:11.00#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.224.08:11:11.00#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.224.08:11:11.00#ibcon#enter wrdev, iclass 23, count 2 2006.224.08:11:11.00#ibcon#first serial, iclass 23, count 2 2006.224.08:11:11.00#ibcon#enter sib2, iclass 23, count 2 2006.224.08:11:11.00#ibcon#flushed, iclass 23, count 2 2006.224.08:11:11.00#ibcon#about to write, iclass 23, count 2 2006.224.08:11:11.00#ibcon#wrote, iclass 23, count 2 2006.224.08:11:11.00#ibcon#about to read 3, iclass 23, count 2 2006.224.08:11:11.02#ibcon#read 3, iclass 23, count 2 2006.224.08:11:11.02#ibcon#about to read 4, iclass 23, count 2 2006.224.08:11:11.02#ibcon#read 4, iclass 23, count 2 2006.224.08:11:11.02#ibcon#about to read 5, iclass 23, count 2 2006.224.08:11:11.02#ibcon#read 5, iclass 23, count 2 2006.224.08:11:11.02#ibcon#about to read 6, iclass 23, count 2 2006.224.08:11:11.02#ibcon#read 6, iclass 23, count 2 2006.224.08:11:11.02#ibcon#end of sib2, iclass 23, count 2 2006.224.08:11:11.02#ibcon#*mode == 0, iclass 23, count 2 2006.224.08:11:11.02#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.224.08:11:11.02#ibcon#[27=AT02-04\r\n] 2006.224.08:11:11.02#ibcon#*before write, iclass 23, count 2 2006.224.08:11:11.02#ibcon#enter sib2, iclass 23, count 2 2006.224.08:11:11.02#ibcon#flushed, iclass 23, count 2 2006.224.08:11:11.02#ibcon#about to write, iclass 23, count 2 2006.224.08:11:11.02#ibcon#wrote, iclass 23, count 2 2006.224.08:11:11.02#ibcon#about to read 3, iclass 23, count 2 2006.224.08:11:11.05#ibcon#read 3, iclass 23, count 2 2006.224.08:11:11.05#ibcon#about to read 4, iclass 23, count 2 2006.224.08:11:11.05#ibcon#read 4, iclass 23, count 2 2006.224.08:11:11.05#ibcon#about to read 5, iclass 23, count 2 2006.224.08:11:11.05#ibcon#read 5, iclass 23, count 2 2006.224.08:11:11.05#ibcon#about to read 6, iclass 23, count 2 2006.224.08:11:11.05#ibcon#read 6, iclass 23, count 2 2006.224.08:11:11.05#ibcon#end of sib2, iclass 23, count 2 2006.224.08:11:11.05#ibcon#*after write, iclass 23, count 2 2006.224.08:11:11.05#ibcon#*before return 0, iclass 23, count 2 2006.224.08:11:11.05#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.224.08:11:11.05#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.224.08:11:11.05#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.224.08:11:11.05#ibcon#ireg 7 cls_cnt 0 2006.224.08:11:11.05#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.224.08:11:11.17#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.224.08:11:11.17#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.224.08:11:11.17#ibcon#enter wrdev, iclass 23, count 0 2006.224.08:11:11.17#ibcon#first serial, iclass 23, count 0 2006.224.08:11:11.17#ibcon#enter sib2, iclass 23, count 0 2006.224.08:11:11.17#ibcon#flushed, iclass 23, count 0 2006.224.08:11:11.17#ibcon#about to write, iclass 23, count 0 2006.224.08:11:11.17#ibcon#wrote, iclass 23, count 0 2006.224.08:11:11.17#ibcon#about to read 3, iclass 23, count 0 2006.224.08:11:11.19#ibcon#read 3, iclass 23, count 0 2006.224.08:11:11.19#ibcon#about to read 4, iclass 23, count 0 2006.224.08:11:11.19#ibcon#read 4, iclass 23, count 0 2006.224.08:11:11.19#ibcon#about to read 5, iclass 23, count 0 2006.224.08:11:11.19#ibcon#read 5, iclass 23, count 0 2006.224.08:11:11.19#ibcon#about to read 6, iclass 23, count 0 2006.224.08:11:11.19#ibcon#read 6, iclass 23, count 0 2006.224.08:11:11.19#ibcon#end of sib2, iclass 23, count 0 2006.224.08:11:11.19#ibcon#*mode == 0, iclass 23, count 0 2006.224.08:11:11.19#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.224.08:11:11.19#ibcon#[27=USB\r\n] 2006.224.08:11:11.19#ibcon#*before write, iclass 23, count 0 2006.224.08:11:11.19#ibcon#enter sib2, iclass 23, count 0 2006.224.08:11:11.19#ibcon#flushed, iclass 23, count 0 2006.224.08:11:11.19#ibcon#about to write, iclass 23, count 0 2006.224.08:11:11.19#ibcon#wrote, iclass 23, count 0 2006.224.08:11:11.19#ibcon#about to read 3, iclass 23, count 0 2006.224.08:11:11.22#ibcon#read 3, iclass 23, count 0 2006.224.08:11:11.22#ibcon#about to read 4, iclass 23, count 0 2006.224.08:11:11.22#ibcon#read 4, iclass 23, count 0 2006.224.08:11:11.22#ibcon#about to read 5, iclass 23, count 0 2006.224.08:11:11.22#ibcon#read 5, iclass 23, count 0 2006.224.08:11:11.22#ibcon#about to read 6, iclass 23, count 0 2006.224.08:11:11.22#ibcon#read 6, iclass 23, count 0 2006.224.08:11:11.22#ibcon#end of sib2, iclass 23, count 0 2006.224.08:11:11.22#ibcon#*after write, iclass 23, count 0 2006.224.08:11:11.22#ibcon#*before return 0, iclass 23, count 0 2006.224.08:11:11.22#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.224.08:11:11.22#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.224.08:11:11.22#ibcon#about to clear, iclass 23 cls_cnt 0 2006.224.08:11:11.22#ibcon#cleared, iclass 23 cls_cnt 0 2006.224.08:11:11.22$vc4f8/vblo=3,656.99 2006.224.08:11:11.22#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.224.08:11:11.22#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.224.08:11:11.22#ibcon#ireg 17 cls_cnt 0 2006.224.08:11:11.22#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.224.08:11:11.22#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.224.08:11:11.22#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.224.08:11:11.22#ibcon#enter wrdev, iclass 25, count 0 2006.224.08:11:11.22#ibcon#first serial, iclass 25, count 0 2006.224.08:11:11.22#ibcon#enter sib2, iclass 25, count 0 2006.224.08:11:11.22#ibcon#flushed, iclass 25, count 0 2006.224.08:11:11.22#ibcon#about to write, iclass 25, count 0 2006.224.08:11:11.22#ibcon#wrote, iclass 25, count 0 2006.224.08:11:11.22#ibcon#about to read 3, iclass 25, count 0 2006.224.08:11:11.24#ibcon#read 3, iclass 25, count 0 2006.224.08:11:11.24#ibcon#about to read 4, iclass 25, count 0 2006.224.08:11:11.24#ibcon#read 4, iclass 25, count 0 2006.224.08:11:11.24#ibcon#about to read 5, iclass 25, count 0 2006.224.08:11:11.24#ibcon#read 5, iclass 25, count 0 2006.224.08:11:11.24#ibcon#about to read 6, iclass 25, count 0 2006.224.08:11:11.24#ibcon#read 6, iclass 25, count 0 2006.224.08:11:11.24#ibcon#end of sib2, iclass 25, count 0 2006.224.08:11:11.24#ibcon#*mode == 0, iclass 25, count 0 2006.224.08:11:11.24#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.224.08:11:11.24#ibcon#[28=FRQ=03,656.99\r\n] 2006.224.08:11:11.24#ibcon#*before write, iclass 25, count 0 2006.224.08:11:11.24#ibcon#enter sib2, iclass 25, count 0 2006.224.08:11:11.24#ibcon#flushed, iclass 25, count 0 2006.224.08:11:11.24#ibcon#about to write, iclass 25, count 0 2006.224.08:11:11.24#ibcon#wrote, iclass 25, count 0 2006.224.08:11:11.24#ibcon#about to read 3, iclass 25, count 0 2006.224.08:11:11.28#ibcon#read 3, iclass 25, count 0 2006.224.08:11:11.28#ibcon#about to read 4, iclass 25, count 0 2006.224.08:11:11.28#ibcon#read 4, iclass 25, count 0 2006.224.08:11:11.28#ibcon#about to read 5, iclass 25, count 0 2006.224.08:11:11.28#ibcon#read 5, iclass 25, count 0 2006.224.08:11:11.28#ibcon#about to read 6, iclass 25, count 0 2006.224.08:11:11.28#ibcon#read 6, iclass 25, count 0 2006.224.08:11:11.28#ibcon#end of sib2, iclass 25, count 0 2006.224.08:11:11.28#ibcon#*after write, iclass 25, count 0 2006.224.08:11:11.28#ibcon#*before return 0, iclass 25, count 0 2006.224.08:11:11.28#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.224.08:11:11.28#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.224.08:11:11.28#ibcon#about to clear, iclass 25 cls_cnt 0 2006.224.08:11:11.28#ibcon#cleared, iclass 25 cls_cnt 0 2006.224.08:11:11.28$vc4f8/vb=3,4 2006.224.08:11:11.28#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.224.08:11:11.28#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.224.08:11:11.28#ibcon#ireg 11 cls_cnt 2 2006.224.08:11:11.28#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.224.08:11:11.34#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.224.08:11:11.34#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.224.08:11:11.34#ibcon#enter wrdev, iclass 27, count 2 2006.224.08:11:11.34#ibcon#first serial, iclass 27, count 2 2006.224.08:11:11.34#ibcon#enter sib2, iclass 27, count 2 2006.224.08:11:11.34#ibcon#flushed, iclass 27, count 2 2006.224.08:11:11.34#ibcon#about to write, iclass 27, count 2 2006.224.08:11:11.34#ibcon#wrote, iclass 27, count 2 2006.224.08:11:11.34#ibcon#about to read 3, iclass 27, count 2 2006.224.08:11:11.36#ibcon#read 3, iclass 27, count 2 2006.224.08:11:11.36#ibcon#about to read 4, iclass 27, count 2 2006.224.08:11:11.36#ibcon#read 4, iclass 27, count 2 2006.224.08:11:11.36#ibcon#about to read 5, iclass 27, count 2 2006.224.08:11:11.36#ibcon#read 5, iclass 27, count 2 2006.224.08:11:11.36#ibcon#about to read 6, iclass 27, count 2 2006.224.08:11:11.36#ibcon#read 6, iclass 27, count 2 2006.224.08:11:11.36#ibcon#end of sib2, iclass 27, count 2 2006.224.08:11:11.36#ibcon#*mode == 0, iclass 27, count 2 2006.224.08:11:11.36#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.224.08:11:11.36#ibcon#[27=AT03-04\r\n] 2006.224.08:11:11.36#ibcon#*before write, iclass 27, count 2 2006.224.08:11:11.36#ibcon#enter sib2, iclass 27, count 2 2006.224.08:11:11.36#ibcon#flushed, iclass 27, count 2 2006.224.08:11:11.36#ibcon#about to write, iclass 27, count 2 2006.224.08:11:11.36#ibcon#wrote, iclass 27, count 2 2006.224.08:11:11.36#ibcon#about to read 3, iclass 27, count 2 2006.224.08:11:11.39#ibcon#read 3, iclass 27, count 2 2006.224.08:11:11.39#ibcon#about to read 4, iclass 27, count 2 2006.224.08:11:11.39#ibcon#read 4, iclass 27, count 2 2006.224.08:11:11.39#ibcon#about to read 5, iclass 27, count 2 2006.224.08:11:11.39#ibcon#read 5, iclass 27, count 2 2006.224.08:11:11.39#ibcon#about to read 6, iclass 27, count 2 2006.224.08:11:11.39#ibcon#read 6, iclass 27, count 2 2006.224.08:11:11.39#ibcon#end of sib2, iclass 27, count 2 2006.224.08:11:11.39#ibcon#*after write, iclass 27, count 2 2006.224.08:11:11.39#ibcon#*before return 0, iclass 27, count 2 2006.224.08:11:11.39#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.224.08:11:11.39#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.224.08:11:11.39#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.224.08:11:11.39#ibcon#ireg 7 cls_cnt 0 2006.224.08:11:11.39#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.224.08:11:11.51#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.224.08:11:11.51#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.224.08:11:11.51#ibcon#enter wrdev, iclass 27, count 0 2006.224.08:11:11.51#ibcon#first serial, iclass 27, count 0 2006.224.08:11:11.51#ibcon#enter sib2, iclass 27, count 0 2006.224.08:11:11.51#ibcon#flushed, iclass 27, count 0 2006.224.08:11:11.51#ibcon#about to write, iclass 27, count 0 2006.224.08:11:11.51#ibcon#wrote, iclass 27, count 0 2006.224.08:11:11.51#ibcon#about to read 3, iclass 27, count 0 2006.224.08:11:11.53#ibcon#read 3, iclass 27, count 0 2006.224.08:11:11.53#ibcon#about to read 4, iclass 27, count 0 2006.224.08:11:11.53#ibcon#read 4, iclass 27, count 0 2006.224.08:11:11.53#ibcon#about to read 5, iclass 27, count 0 2006.224.08:11:11.53#ibcon#read 5, iclass 27, count 0 2006.224.08:11:11.53#ibcon#about to read 6, iclass 27, count 0 2006.224.08:11:11.53#ibcon#read 6, iclass 27, count 0 2006.224.08:11:11.53#ibcon#end of sib2, iclass 27, count 0 2006.224.08:11:11.53#ibcon#*mode == 0, iclass 27, count 0 2006.224.08:11:11.53#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.224.08:11:11.53#ibcon#[27=USB\r\n] 2006.224.08:11:11.53#ibcon#*before write, iclass 27, count 0 2006.224.08:11:11.53#ibcon#enter sib2, iclass 27, count 0 2006.224.08:11:11.53#ibcon#flushed, iclass 27, count 0 2006.224.08:11:11.53#ibcon#about to write, iclass 27, count 0 2006.224.08:11:11.53#ibcon#wrote, iclass 27, count 0 2006.224.08:11:11.53#ibcon#about to read 3, iclass 27, count 0 2006.224.08:11:11.56#ibcon#read 3, iclass 27, count 0 2006.224.08:11:11.56#ibcon#about to read 4, iclass 27, count 0 2006.224.08:11:11.56#ibcon#read 4, iclass 27, count 0 2006.224.08:11:11.56#ibcon#about to read 5, iclass 27, count 0 2006.224.08:11:11.56#ibcon#read 5, iclass 27, count 0 2006.224.08:11:11.56#ibcon#about to read 6, iclass 27, count 0 2006.224.08:11:11.56#ibcon#read 6, iclass 27, count 0 2006.224.08:11:11.56#ibcon#end of sib2, iclass 27, count 0 2006.224.08:11:11.56#ibcon#*after write, iclass 27, count 0 2006.224.08:11:11.56#ibcon#*before return 0, iclass 27, count 0 2006.224.08:11:11.56#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.224.08:11:11.56#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.224.08:11:11.56#ibcon#about to clear, iclass 27 cls_cnt 0 2006.224.08:11:11.56#ibcon#cleared, iclass 27 cls_cnt 0 2006.224.08:11:11.56$vc4f8/vblo=4,712.99 2006.224.08:11:11.56#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.224.08:11:11.56#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.224.08:11:11.56#ibcon#ireg 17 cls_cnt 0 2006.224.08:11:11.56#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.224.08:11:11.56#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.224.08:11:11.56#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.224.08:11:11.56#ibcon#enter wrdev, iclass 29, count 0 2006.224.08:11:11.56#ibcon#first serial, iclass 29, count 0 2006.224.08:11:11.56#ibcon#enter sib2, iclass 29, count 0 2006.224.08:11:11.56#ibcon#flushed, iclass 29, count 0 2006.224.08:11:11.56#ibcon#about to write, iclass 29, count 0 2006.224.08:11:11.56#ibcon#wrote, iclass 29, count 0 2006.224.08:11:11.56#ibcon#about to read 3, iclass 29, count 0 2006.224.08:11:11.58#ibcon#read 3, iclass 29, count 0 2006.224.08:11:11.58#ibcon#about to read 4, iclass 29, count 0 2006.224.08:11:11.58#ibcon#read 4, iclass 29, count 0 2006.224.08:11:11.58#ibcon#about to read 5, iclass 29, count 0 2006.224.08:11:11.58#ibcon#read 5, iclass 29, count 0 2006.224.08:11:11.58#ibcon#about to read 6, iclass 29, count 0 2006.224.08:11:11.58#ibcon#read 6, iclass 29, count 0 2006.224.08:11:11.58#ibcon#end of sib2, iclass 29, count 0 2006.224.08:11:11.58#ibcon#*mode == 0, iclass 29, count 0 2006.224.08:11:11.58#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.224.08:11:11.58#ibcon#[28=FRQ=04,712.99\r\n] 2006.224.08:11:11.58#ibcon#*before write, iclass 29, count 0 2006.224.08:11:11.58#ibcon#enter sib2, iclass 29, count 0 2006.224.08:11:11.58#ibcon#flushed, iclass 29, count 0 2006.224.08:11:11.58#ibcon#about to write, iclass 29, count 0 2006.224.08:11:11.58#ibcon#wrote, iclass 29, count 0 2006.224.08:11:11.58#ibcon#about to read 3, iclass 29, count 0 2006.224.08:11:11.62#ibcon#read 3, iclass 29, count 0 2006.224.08:11:11.62#ibcon#about to read 4, iclass 29, count 0 2006.224.08:11:11.62#ibcon#read 4, iclass 29, count 0 2006.224.08:11:11.62#ibcon#about to read 5, iclass 29, count 0 2006.224.08:11:11.62#ibcon#read 5, iclass 29, count 0 2006.224.08:11:11.62#ibcon#about to read 6, iclass 29, count 0 2006.224.08:11:11.62#ibcon#read 6, iclass 29, count 0 2006.224.08:11:11.62#ibcon#end of sib2, iclass 29, count 0 2006.224.08:11:11.62#ibcon#*after write, iclass 29, count 0 2006.224.08:11:11.62#ibcon#*before return 0, iclass 29, count 0 2006.224.08:11:11.62#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.224.08:11:11.62#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.224.08:11:11.62#ibcon#about to clear, iclass 29 cls_cnt 0 2006.224.08:11:11.62#ibcon#cleared, iclass 29 cls_cnt 0 2006.224.08:11:11.62$vc4f8/vb=4,4 2006.224.08:11:11.62#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.224.08:11:11.62#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.224.08:11:11.62#ibcon#ireg 11 cls_cnt 2 2006.224.08:11:11.62#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.224.08:11:11.68#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.224.08:11:11.68#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.224.08:11:11.68#ibcon#enter wrdev, iclass 31, count 2 2006.224.08:11:11.68#ibcon#first serial, iclass 31, count 2 2006.224.08:11:11.68#ibcon#enter sib2, iclass 31, count 2 2006.224.08:11:11.68#ibcon#flushed, iclass 31, count 2 2006.224.08:11:11.68#ibcon#about to write, iclass 31, count 2 2006.224.08:11:11.68#ibcon#wrote, iclass 31, count 2 2006.224.08:11:11.68#ibcon#about to read 3, iclass 31, count 2 2006.224.08:11:11.70#ibcon#read 3, iclass 31, count 2 2006.224.08:11:11.70#ibcon#about to read 4, iclass 31, count 2 2006.224.08:11:11.70#ibcon#read 4, iclass 31, count 2 2006.224.08:11:11.70#ibcon#about to read 5, iclass 31, count 2 2006.224.08:11:11.70#ibcon#read 5, iclass 31, count 2 2006.224.08:11:11.70#ibcon#about to read 6, iclass 31, count 2 2006.224.08:11:11.70#ibcon#read 6, iclass 31, count 2 2006.224.08:11:11.70#ibcon#end of sib2, iclass 31, count 2 2006.224.08:11:11.70#ibcon#*mode == 0, iclass 31, count 2 2006.224.08:11:11.70#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.224.08:11:11.70#ibcon#[27=AT04-04\r\n] 2006.224.08:11:11.70#ibcon#*before write, iclass 31, count 2 2006.224.08:11:11.70#ibcon#enter sib2, iclass 31, count 2 2006.224.08:11:11.70#ibcon#flushed, iclass 31, count 2 2006.224.08:11:11.70#ibcon#about to write, iclass 31, count 2 2006.224.08:11:11.70#ibcon#wrote, iclass 31, count 2 2006.224.08:11:11.70#ibcon#about to read 3, iclass 31, count 2 2006.224.08:11:11.73#ibcon#read 3, iclass 31, count 2 2006.224.08:11:11.73#ibcon#about to read 4, iclass 31, count 2 2006.224.08:11:11.73#ibcon#read 4, iclass 31, count 2 2006.224.08:11:11.73#ibcon#about to read 5, iclass 31, count 2 2006.224.08:11:11.73#ibcon#read 5, iclass 31, count 2 2006.224.08:11:11.73#ibcon#about to read 6, iclass 31, count 2 2006.224.08:11:11.73#ibcon#read 6, iclass 31, count 2 2006.224.08:11:11.73#ibcon#end of sib2, iclass 31, count 2 2006.224.08:11:11.73#ibcon#*after write, iclass 31, count 2 2006.224.08:11:11.73#ibcon#*before return 0, iclass 31, count 2 2006.224.08:11:11.73#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.224.08:11:11.73#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.224.08:11:11.73#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.224.08:11:11.73#ibcon#ireg 7 cls_cnt 0 2006.224.08:11:11.73#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.224.08:11:11.85#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.224.08:11:11.85#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.224.08:11:11.85#ibcon#enter wrdev, iclass 31, count 0 2006.224.08:11:11.85#ibcon#first serial, iclass 31, count 0 2006.224.08:11:11.85#ibcon#enter sib2, iclass 31, count 0 2006.224.08:11:11.85#ibcon#flushed, iclass 31, count 0 2006.224.08:11:11.85#ibcon#about to write, iclass 31, count 0 2006.224.08:11:11.85#ibcon#wrote, iclass 31, count 0 2006.224.08:11:11.85#ibcon#about to read 3, iclass 31, count 0 2006.224.08:11:11.87#ibcon#read 3, iclass 31, count 0 2006.224.08:11:11.87#ibcon#about to read 4, iclass 31, count 0 2006.224.08:11:11.87#ibcon#read 4, iclass 31, count 0 2006.224.08:11:11.87#ibcon#about to read 5, iclass 31, count 0 2006.224.08:11:11.87#ibcon#read 5, iclass 31, count 0 2006.224.08:11:11.87#ibcon#about to read 6, iclass 31, count 0 2006.224.08:11:11.87#ibcon#read 6, iclass 31, count 0 2006.224.08:11:11.87#ibcon#end of sib2, iclass 31, count 0 2006.224.08:11:11.87#ibcon#*mode == 0, iclass 31, count 0 2006.224.08:11:11.87#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.224.08:11:11.87#ibcon#[27=USB\r\n] 2006.224.08:11:11.87#ibcon#*before write, iclass 31, count 0 2006.224.08:11:11.87#ibcon#enter sib2, iclass 31, count 0 2006.224.08:11:11.87#ibcon#flushed, iclass 31, count 0 2006.224.08:11:11.87#ibcon#about to write, iclass 31, count 0 2006.224.08:11:11.87#ibcon#wrote, iclass 31, count 0 2006.224.08:11:11.87#ibcon#about to read 3, iclass 31, count 0 2006.224.08:11:11.90#ibcon#read 3, iclass 31, count 0 2006.224.08:11:11.90#ibcon#about to read 4, iclass 31, count 0 2006.224.08:11:11.90#ibcon#read 4, iclass 31, count 0 2006.224.08:11:11.90#ibcon#about to read 5, iclass 31, count 0 2006.224.08:11:11.90#ibcon#read 5, iclass 31, count 0 2006.224.08:11:11.90#ibcon#about to read 6, iclass 31, count 0 2006.224.08:11:11.90#ibcon#read 6, iclass 31, count 0 2006.224.08:11:11.90#ibcon#end of sib2, iclass 31, count 0 2006.224.08:11:11.90#ibcon#*after write, iclass 31, count 0 2006.224.08:11:11.90#ibcon#*before return 0, iclass 31, count 0 2006.224.08:11:11.90#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.224.08:11:11.90#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.224.08:11:11.90#ibcon#about to clear, iclass 31 cls_cnt 0 2006.224.08:11:11.90#ibcon#cleared, iclass 31 cls_cnt 0 2006.224.08:11:11.90$vc4f8/vblo=5,744.99 2006.224.08:11:11.90#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.224.08:11:11.90#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.224.08:11:11.90#ibcon#ireg 17 cls_cnt 0 2006.224.08:11:11.90#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.224.08:11:11.90#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.224.08:11:11.90#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.224.08:11:11.90#ibcon#enter wrdev, iclass 33, count 0 2006.224.08:11:11.90#ibcon#first serial, iclass 33, count 0 2006.224.08:11:11.90#ibcon#enter sib2, iclass 33, count 0 2006.224.08:11:11.90#ibcon#flushed, iclass 33, count 0 2006.224.08:11:11.90#ibcon#about to write, iclass 33, count 0 2006.224.08:11:11.90#ibcon#wrote, iclass 33, count 0 2006.224.08:11:11.90#ibcon#about to read 3, iclass 33, count 0 2006.224.08:11:11.92#ibcon#read 3, iclass 33, count 0 2006.224.08:11:11.92#ibcon#about to read 4, iclass 33, count 0 2006.224.08:11:11.92#ibcon#read 4, iclass 33, count 0 2006.224.08:11:11.92#ibcon#about to read 5, iclass 33, count 0 2006.224.08:11:11.92#ibcon#read 5, iclass 33, count 0 2006.224.08:11:11.92#ibcon#about to read 6, iclass 33, count 0 2006.224.08:11:11.92#ibcon#read 6, iclass 33, count 0 2006.224.08:11:11.92#ibcon#end of sib2, iclass 33, count 0 2006.224.08:11:11.92#ibcon#*mode == 0, iclass 33, count 0 2006.224.08:11:11.92#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.224.08:11:11.92#ibcon#[28=FRQ=05,744.99\r\n] 2006.224.08:11:11.92#ibcon#*before write, iclass 33, count 0 2006.224.08:11:11.92#ibcon#enter sib2, iclass 33, count 0 2006.224.08:11:11.92#ibcon#flushed, iclass 33, count 0 2006.224.08:11:11.92#ibcon#about to write, iclass 33, count 0 2006.224.08:11:11.92#ibcon#wrote, iclass 33, count 0 2006.224.08:11:11.92#ibcon#about to read 3, iclass 33, count 0 2006.224.08:11:11.96#ibcon#read 3, iclass 33, count 0 2006.224.08:11:11.96#ibcon#about to read 4, iclass 33, count 0 2006.224.08:11:11.96#ibcon#read 4, iclass 33, count 0 2006.224.08:11:11.96#ibcon#about to read 5, iclass 33, count 0 2006.224.08:11:11.96#ibcon#read 5, iclass 33, count 0 2006.224.08:11:11.96#ibcon#about to read 6, iclass 33, count 0 2006.224.08:11:11.96#ibcon#read 6, iclass 33, count 0 2006.224.08:11:11.96#ibcon#end of sib2, iclass 33, count 0 2006.224.08:11:11.96#ibcon#*after write, iclass 33, count 0 2006.224.08:11:11.96#ibcon#*before return 0, iclass 33, count 0 2006.224.08:11:11.96#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.224.08:11:11.96#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.224.08:11:11.96#ibcon#about to clear, iclass 33 cls_cnt 0 2006.224.08:11:11.96#ibcon#cleared, iclass 33 cls_cnt 0 2006.224.08:11:11.96$vc4f8/vb=5,4 2006.224.08:11:11.96#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.224.08:11:11.96#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.224.08:11:11.96#ibcon#ireg 11 cls_cnt 2 2006.224.08:11:11.96#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.224.08:11:12.02#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.224.08:11:12.02#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.224.08:11:12.02#ibcon#enter wrdev, iclass 35, count 2 2006.224.08:11:12.02#ibcon#first serial, iclass 35, count 2 2006.224.08:11:12.02#ibcon#enter sib2, iclass 35, count 2 2006.224.08:11:12.02#ibcon#flushed, iclass 35, count 2 2006.224.08:11:12.02#ibcon#about to write, iclass 35, count 2 2006.224.08:11:12.02#ibcon#wrote, iclass 35, count 2 2006.224.08:11:12.02#ibcon#about to read 3, iclass 35, count 2 2006.224.08:11:12.04#ibcon#read 3, iclass 35, count 2 2006.224.08:11:12.04#ibcon#about to read 4, iclass 35, count 2 2006.224.08:11:12.04#ibcon#read 4, iclass 35, count 2 2006.224.08:11:12.04#ibcon#about to read 5, iclass 35, count 2 2006.224.08:11:12.04#ibcon#read 5, iclass 35, count 2 2006.224.08:11:12.04#ibcon#about to read 6, iclass 35, count 2 2006.224.08:11:12.04#ibcon#read 6, iclass 35, count 2 2006.224.08:11:12.04#ibcon#end of sib2, iclass 35, count 2 2006.224.08:11:12.04#ibcon#*mode == 0, iclass 35, count 2 2006.224.08:11:12.04#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.224.08:11:12.04#ibcon#[27=AT05-04\r\n] 2006.224.08:11:12.04#ibcon#*before write, iclass 35, count 2 2006.224.08:11:12.04#ibcon#enter sib2, iclass 35, count 2 2006.224.08:11:12.04#ibcon#flushed, iclass 35, count 2 2006.224.08:11:12.04#ibcon#about to write, iclass 35, count 2 2006.224.08:11:12.04#ibcon#wrote, iclass 35, count 2 2006.224.08:11:12.04#ibcon#about to read 3, iclass 35, count 2 2006.224.08:11:12.07#ibcon#read 3, iclass 35, count 2 2006.224.08:11:12.07#ibcon#about to read 4, iclass 35, count 2 2006.224.08:11:12.07#ibcon#read 4, iclass 35, count 2 2006.224.08:11:12.07#ibcon#about to read 5, iclass 35, count 2 2006.224.08:11:12.07#ibcon#read 5, iclass 35, count 2 2006.224.08:11:12.07#ibcon#about to read 6, iclass 35, count 2 2006.224.08:11:12.07#ibcon#read 6, iclass 35, count 2 2006.224.08:11:12.07#ibcon#end of sib2, iclass 35, count 2 2006.224.08:11:12.07#ibcon#*after write, iclass 35, count 2 2006.224.08:11:12.07#ibcon#*before return 0, iclass 35, count 2 2006.224.08:11:12.07#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.224.08:11:12.07#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.224.08:11:12.07#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.224.08:11:12.07#ibcon#ireg 7 cls_cnt 0 2006.224.08:11:12.07#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.224.08:11:12.19#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.224.08:11:12.19#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.224.08:11:12.19#ibcon#enter wrdev, iclass 35, count 0 2006.224.08:11:12.19#ibcon#first serial, iclass 35, count 0 2006.224.08:11:12.19#ibcon#enter sib2, iclass 35, count 0 2006.224.08:11:12.19#ibcon#flushed, iclass 35, count 0 2006.224.08:11:12.19#ibcon#about to write, iclass 35, count 0 2006.224.08:11:12.19#ibcon#wrote, iclass 35, count 0 2006.224.08:11:12.19#ibcon#about to read 3, iclass 35, count 0 2006.224.08:11:12.21#ibcon#read 3, iclass 35, count 0 2006.224.08:11:12.21#ibcon#about to read 4, iclass 35, count 0 2006.224.08:11:12.21#ibcon#read 4, iclass 35, count 0 2006.224.08:11:12.21#ibcon#about to read 5, iclass 35, count 0 2006.224.08:11:12.21#ibcon#read 5, iclass 35, count 0 2006.224.08:11:12.21#ibcon#about to read 6, iclass 35, count 0 2006.224.08:11:12.21#ibcon#read 6, iclass 35, count 0 2006.224.08:11:12.21#ibcon#end of sib2, iclass 35, count 0 2006.224.08:11:12.21#ibcon#*mode == 0, iclass 35, count 0 2006.224.08:11:12.21#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.224.08:11:12.21#ibcon#[27=USB\r\n] 2006.224.08:11:12.21#ibcon#*before write, iclass 35, count 0 2006.224.08:11:12.21#ibcon#enter sib2, iclass 35, count 0 2006.224.08:11:12.21#ibcon#flushed, iclass 35, count 0 2006.224.08:11:12.21#ibcon#about to write, iclass 35, count 0 2006.224.08:11:12.21#ibcon#wrote, iclass 35, count 0 2006.224.08:11:12.21#ibcon#about to read 3, iclass 35, count 0 2006.224.08:11:12.24#ibcon#read 3, iclass 35, count 0 2006.224.08:11:12.24#ibcon#about to read 4, iclass 35, count 0 2006.224.08:11:12.24#ibcon#read 4, iclass 35, count 0 2006.224.08:11:12.24#ibcon#about to read 5, iclass 35, count 0 2006.224.08:11:12.24#ibcon#read 5, iclass 35, count 0 2006.224.08:11:12.24#ibcon#about to read 6, iclass 35, count 0 2006.224.08:11:12.24#ibcon#read 6, iclass 35, count 0 2006.224.08:11:12.24#ibcon#end of sib2, iclass 35, count 0 2006.224.08:11:12.24#ibcon#*after write, iclass 35, count 0 2006.224.08:11:12.24#ibcon#*before return 0, iclass 35, count 0 2006.224.08:11:12.24#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.224.08:11:12.24#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.224.08:11:12.24#ibcon#about to clear, iclass 35 cls_cnt 0 2006.224.08:11:12.24#ibcon#cleared, iclass 35 cls_cnt 0 2006.224.08:11:12.24$vc4f8/vblo=6,752.99 2006.224.08:11:12.24#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.224.08:11:12.24#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.224.08:11:12.24#ibcon#ireg 17 cls_cnt 0 2006.224.08:11:12.24#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.224.08:11:12.24#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.224.08:11:12.24#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.224.08:11:12.24#ibcon#enter wrdev, iclass 37, count 0 2006.224.08:11:12.24#ibcon#first serial, iclass 37, count 0 2006.224.08:11:12.24#ibcon#enter sib2, iclass 37, count 0 2006.224.08:11:12.24#ibcon#flushed, iclass 37, count 0 2006.224.08:11:12.24#ibcon#about to write, iclass 37, count 0 2006.224.08:11:12.24#ibcon#wrote, iclass 37, count 0 2006.224.08:11:12.24#ibcon#about to read 3, iclass 37, count 0 2006.224.08:11:12.26#ibcon#read 3, iclass 37, count 0 2006.224.08:11:12.26#ibcon#about to read 4, iclass 37, count 0 2006.224.08:11:12.26#ibcon#read 4, iclass 37, count 0 2006.224.08:11:12.26#ibcon#about to read 5, iclass 37, count 0 2006.224.08:11:12.26#ibcon#read 5, iclass 37, count 0 2006.224.08:11:12.26#ibcon#about to read 6, iclass 37, count 0 2006.224.08:11:12.26#ibcon#read 6, iclass 37, count 0 2006.224.08:11:12.26#ibcon#end of sib2, iclass 37, count 0 2006.224.08:11:12.26#ibcon#*mode == 0, iclass 37, count 0 2006.224.08:11:12.26#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.224.08:11:12.26#ibcon#[28=FRQ=06,752.99\r\n] 2006.224.08:11:12.26#ibcon#*before write, iclass 37, count 0 2006.224.08:11:12.26#ibcon#enter sib2, iclass 37, count 0 2006.224.08:11:12.26#ibcon#flushed, iclass 37, count 0 2006.224.08:11:12.26#ibcon#about to write, iclass 37, count 0 2006.224.08:11:12.26#ibcon#wrote, iclass 37, count 0 2006.224.08:11:12.26#ibcon#about to read 3, iclass 37, count 0 2006.224.08:11:12.30#ibcon#read 3, iclass 37, count 0 2006.224.08:11:12.30#ibcon#about to read 4, iclass 37, count 0 2006.224.08:11:12.30#ibcon#read 4, iclass 37, count 0 2006.224.08:11:12.30#ibcon#about to read 5, iclass 37, count 0 2006.224.08:11:12.30#ibcon#read 5, iclass 37, count 0 2006.224.08:11:12.30#ibcon#about to read 6, iclass 37, count 0 2006.224.08:11:12.30#ibcon#read 6, iclass 37, count 0 2006.224.08:11:12.30#ibcon#end of sib2, iclass 37, count 0 2006.224.08:11:12.30#ibcon#*after write, iclass 37, count 0 2006.224.08:11:12.30#ibcon#*before return 0, iclass 37, count 0 2006.224.08:11:12.30#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.224.08:11:12.30#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.224.08:11:12.30#ibcon#about to clear, iclass 37 cls_cnt 0 2006.224.08:11:12.30#ibcon#cleared, iclass 37 cls_cnt 0 2006.224.08:11:12.30$vc4f8/vb=6,4 2006.224.08:11:12.30#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.224.08:11:12.30#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.224.08:11:12.30#ibcon#ireg 11 cls_cnt 2 2006.224.08:11:12.30#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.224.08:11:12.36#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.224.08:11:12.36#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.224.08:11:12.36#ibcon#enter wrdev, iclass 39, count 2 2006.224.08:11:12.36#ibcon#first serial, iclass 39, count 2 2006.224.08:11:12.36#ibcon#enter sib2, iclass 39, count 2 2006.224.08:11:12.36#ibcon#flushed, iclass 39, count 2 2006.224.08:11:12.36#ibcon#about to write, iclass 39, count 2 2006.224.08:11:12.36#ibcon#wrote, iclass 39, count 2 2006.224.08:11:12.36#ibcon#about to read 3, iclass 39, count 2 2006.224.08:11:12.38#ibcon#read 3, iclass 39, count 2 2006.224.08:11:12.38#ibcon#about to read 4, iclass 39, count 2 2006.224.08:11:12.38#ibcon#read 4, iclass 39, count 2 2006.224.08:11:12.38#ibcon#about to read 5, iclass 39, count 2 2006.224.08:11:12.38#ibcon#read 5, iclass 39, count 2 2006.224.08:11:12.38#ibcon#about to read 6, iclass 39, count 2 2006.224.08:11:12.38#ibcon#read 6, iclass 39, count 2 2006.224.08:11:12.38#ibcon#end of sib2, iclass 39, count 2 2006.224.08:11:12.38#ibcon#*mode == 0, iclass 39, count 2 2006.224.08:11:12.38#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.224.08:11:12.38#ibcon#[27=AT06-04\r\n] 2006.224.08:11:12.38#ibcon#*before write, iclass 39, count 2 2006.224.08:11:12.38#ibcon#enter sib2, iclass 39, count 2 2006.224.08:11:12.38#ibcon#flushed, iclass 39, count 2 2006.224.08:11:12.38#ibcon#about to write, iclass 39, count 2 2006.224.08:11:12.38#ibcon#wrote, iclass 39, count 2 2006.224.08:11:12.38#ibcon#about to read 3, iclass 39, count 2 2006.224.08:11:12.41#ibcon#read 3, iclass 39, count 2 2006.224.08:11:12.41#ibcon#about to read 4, iclass 39, count 2 2006.224.08:11:12.41#ibcon#read 4, iclass 39, count 2 2006.224.08:11:12.41#ibcon#about to read 5, iclass 39, count 2 2006.224.08:11:12.41#ibcon#read 5, iclass 39, count 2 2006.224.08:11:12.41#ibcon#about to read 6, iclass 39, count 2 2006.224.08:11:12.41#ibcon#read 6, iclass 39, count 2 2006.224.08:11:12.41#ibcon#end of sib2, iclass 39, count 2 2006.224.08:11:12.41#ibcon#*after write, iclass 39, count 2 2006.224.08:11:12.41#ibcon#*before return 0, iclass 39, count 2 2006.224.08:11:12.41#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.224.08:11:12.41#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.224.08:11:12.41#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.224.08:11:12.41#ibcon#ireg 7 cls_cnt 0 2006.224.08:11:12.41#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.224.08:11:12.53#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.224.08:11:12.53#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.224.08:11:12.53#ibcon#enter wrdev, iclass 39, count 0 2006.224.08:11:12.53#ibcon#first serial, iclass 39, count 0 2006.224.08:11:12.53#ibcon#enter sib2, iclass 39, count 0 2006.224.08:11:12.53#ibcon#flushed, iclass 39, count 0 2006.224.08:11:12.53#ibcon#about to write, iclass 39, count 0 2006.224.08:11:12.53#ibcon#wrote, iclass 39, count 0 2006.224.08:11:12.53#ibcon#about to read 3, iclass 39, count 0 2006.224.08:11:12.55#ibcon#read 3, iclass 39, count 0 2006.224.08:11:12.55#ibcon#about to read 4, iclass 39, count 0 2006.224.08:11:12.55#ibcon#read 4, iclass 39, count 0 2006.224.08:11:12.55#ibcon#about to read 5, iclass 39, count 0 2006.224.08:11:12.55#ibcon#read 5, iclass 39, count 0 2006.224.08:11:12.55#ibcon#about to read 6, iclass 39, count 0 2006.224.08:11:12.55#ibcon#read 6, iclass 39, count 0 2006.224.08:11:12.55#ibcon#end of sib2, iclass 39, count 0 2006.224.08:11:12.55#ibcon#*mode == 0, iclass 39, count 0 2006.224.08:11:12.55#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.224.08:11:12.55#ibcon#[27=USB\r\n] 2006.224.08:11:12.55#ibcon#*before write, iclass 39, count 0 2006.224.08:11:12.55#ibcon#enter sib2, iclass 39, count 0 2006.224.08:11:12.55#ibcon#flushed, iclass 39, count 0 2006.224.08:11:12.55#ibcon#about to write, iclass 39, count 0 2006.224.08:11:12.55#ibcon#wrote, iclass 39, count 0 2006.224.08:11:12.55#ibcon#about to read 3, iclass 39, count 0 2006.224.08:11:12.58#ibcon#read 3, iclass 39, count 0 2006.224.08:11:12.58#ibcon#about to read 4, iclass 39, count 0 2006.224.08:11:12.58#ibcon#read 4, iclass 39, count 0 2006.224.08:11:12.58#ibcon#about to read 5, iclass 39, count 0 2006.224.08:11:12.58#ibcon#read 5, iclass 39, count 0 2006.224.08:11:12.58#ibcon#about to read 6, iclass 39, count 0 2006.224.08:11:12.58#ibcon#read 6, iclass 39, count 0 2006.224.08:11:12.58#ibcon#end of sib2, iclass 39, count 0 2006.224.08:11:12.58#ibcon#*after write, iclass 39, count 0 2006.224.08:11:12.58#ibcon#*before return 0, iclass 39, count 0 2006.224.08:11:12.58#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.224.08:11:12.58#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.224.08:11:12.58#ibcon#about to clear, iclass 39 cls_cnt 0 2006.224.08:11:12.58#ibcon#cleared, iclass 39 cls_cnt 0 2006.224.08:11:12.58$vc4f8/vabw=wide 2006.224.08:11:12.58#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.224.08:11:12.58#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.224.08:11:12.58#ibcon#ireg 8 cls_cnt 0 2006.224.08:11:12.58#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.224.08:11:12.58#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.224.08:11:12.58#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.224.08:11:12.58#ibcon#enter wrdev, iclass 3, count 0 2006.224.08:11:12.58#ibcon#first serial, iclass 3, count 0 2006.224.08:11:12.58#ibcon#enter sib2, iclass 3, count 0 2006.224.08:11:12.58#ibcon#flushed, iclass 3, count 0 2006.224.08:11:12.58#ibcon#about to write, iclass 3, count 0 2006.224.08:11:12.58#ibcon#wrote, iclass 3, count 0 2006.224.08:11:12.58#ibcon#about to read 3, iclass 3, count 0 2006.224.08:11:12.60#ibcon#read 3, iclass 3, count 0 2006.224.08:11:12.60#ibcon#about to read 4, iclass 3, count 0 2006.224.08:11:12.60#ibcon#read 4, iclass 3, count 0 2006.224.08:11:12.60#ibcon#about to read 5, iclass 3, count 0 2006.224.08:11:12.60#ibcon#read 5, iclass 3, count 0 2006.224.08:11:12.60#ibcon#about to read 6, iclass 3, count 0 2006.224.08:11:12.60#ibcon#read 6, iclass 3, count 0 2006.224.08:11:12.60#ibcon#end of sib2, iclass 3, count 0 2006.224.08:11:12.60#ibcon#*mode == 0, iclass 3, count 0 2006.224.08:11:12.60#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.224.08:11:12.60#ibcon#[25=BW32\r\n] 2006.224.08:11:12.60#ibcon#*before write, iclass 3, count 0 2006.224.08:11:12.60#ibcon#enter sib2, iclass 3, count 0 2006.224.08:11:12.60#ibcon#flushed, iclass 3, count 0 2006.224.08:11:12.60#ibcon#about to write, iclass 3, count 0 2006.224.08:11:12.60#ibcon#wrote, iclass 3, count 0 2006.224.08:11:12.60#ibcon#about to read 3, iclass 3, count 0 2006.224.08:11:12.63#ibcon#read 3, iclass 3, count 0 2006.224.08:11:12.63#ibcon#about to read 4, iclass 3, count 0 2006.224.08:11:12.63#ibcon#read 4, iclass 3, count 0 2006.224.08:11:12.63#ibcon#about to read 5, iclass 3, count 0 2006.224.08:11:12.63#ibcon#read 5, iclass 3, count 0 2006.224.08:11:12.63#ibcon#about to read 6, iclass 3, count 0 2006.224.08:11:12.63#ibcon#read 6, iclass 3, count 0 2006.224.08:11:12.63#ibcon#end of sib2, iclass 3, count 0 2006.224.08:11:12.63#ibcon#*after write, iclass 3, count 0 2006.224.08:11:12.63#ibcon#*before return 0, iclass 3, count 0 2006.224.08:11:12.63#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.224.08:11:12.63#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.224.08:11:12.63#ibcon#about to clear, iclass 3 cls_cnt 0 2006.224.08:11:12.63#ibcon#cleared, iclass 3 cls_cnt 0 2006.224.08:11:12.63$vc4f8/vbbw=wide 2006.224.08:11:12.63#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.224.08:11:12.63#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.224.08:11:12.63#ibcon#ireg 8 cls_cnt 0 2006.224.08:11:12.63#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.224.08:11:12.70#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.224.08:11:12.70#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.224.08:11:12.70#ibcon#enter wrdev, iclass 5, count 0 2006.224.08:11:12.70#ibcon#first serial, iclass 5, count 0 2006.224.08:11:12.70#ibcon#enter sib2, iclass 5, count 0 2006.224.08:11:12.70#ibcon#flushed, iclass 5, count 0 2006.224.08:11:12.70#ibcon#about to write, iclass 5, count 0 2006.224.08:11:12.70#ibcon#wrote, iclass 5, count 0 2006.224.08:11:12.70#ibcon#about to read 3, iclass 5, count 0 2006.224.08:11:12.72#ibcon#read 3, iclass 5, count 0 2006.224.08:11:12.72#ibcon#about to read 4, iclass 5, count 0 2006.224.08:11:12.72#ibcon#read 4, iclass 5, count 0 2006.224.08:11:12.72#ibcon#about to read 5, iclass 5, count 0 2006.224.08:11:12.72#ibcon#read 5, iclass 5, count 0 2006.224.08:11:12.72#ibcon#about to read 6, iclass 5, count 0 2006.224.08:11:12.72#ibcon#read 6, iclass 5, count 0 2006.224.08:11:12.72#ibcon#end of sib2, iclass 5, count 0 2006.224.08:11:12.72#ibcon#*mode == 0, iclass 5, count 0 2006.224.08:11:12.72#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.224.08:11:12.72#ibcon#[27=BW32\r\n] 2006.224.08:11:12.72#ibcon#*before write, iclass 5, count 0 2006.224.08:11:12.72#ibcon#enter sib2, iclass 5, count 0 2006.224.08:11:12.72#ibcon#flushed, iclass 5, count 0 2006.224.08:11:12.72#ibcon#about to write, iclass 5, count 0 2006.224.08:11:12.72#ibcon#wrote, iclass 5, count 0 2006.224.08:11:12.72#ibcon#about to read 3, iclass 5, count 0 2006.224.08:11:12.75#ibcon#read 3, iclass 5, count 0 2006.224.08:11:12.75#ibcon#about to read 4, iclass 5, count 0 2006.224.08:11:12.75#ibcon#read 4, iclass 5, count 0 2006.224.08:11:12.75#ibcon#about to read 5, iclass 5, count 0 2006.224.08:11:12.75#ibcon#read 5, iclass 5, count 0 2006.224.08:11:12.75#ibcon#about to read 6, iclass 5, count 0 2006.224.08:11:12.75#ibcon#read 6, iclass 5, count 0 2006.224.08:11:12.75#ibcon#end of sib2, iclass 5, count 0 2006.224.08:11:12.75#ibcon#*after write, iclass 5, count 0 2006.224.08:11:12.75#ibcon#*before return 0, iclass 5, count 0 2006.224.08:11:12.75#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.224.08:11:12.75#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.224.08:11:12.75#ibcon#about to clear, iclass 5 cls_cnt 0 2006.224.08:11:12.75#ibcon#cleared, iclass 5 cls_cnt 0 2006.224.08:11:12.75$4f8m12a/ifd4f 2006.224.08:11:12.75$ifd4f/lo= 2006.224.08:11:12.75$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.224.08:11:12.75$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.224.08:11:12.75$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.224.08:11:12.75$ifd4f/patch= 2006.224.08:11:12.75$ifd4f/patch=lo1,a1,a2,a3,a4 2006.224.08:11:12.75$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.224.08:11:12.75$ifd4f/patch=lo3,a5,a6,a7,a8 2006.224.08:11:12.75$4f8m12a/"form=m,16.000,1:2 2006.224.08:11:12.75$4f8m12a/"tpicd 2006.224.08:11:12.75$4f8m12a/echo=off 2006.224.08:11:12.75$4f8m12a/xlog=off 2006.224.08:11:12.75:!2006.224.08:11:50 2006.224.08:11:31.13#trakl#Source acquired 2006.224.08:11:31.13#flagr#flagr/antenna,acquired 2006.224.08:11:50.00:preob 2006.224.08:11:50.13/onsource/TRACKING 2006.224.08:11:50.13:!2006.224.08:12:00 2006.224.08:12:00.00:data_valid=on 2006.224.08:12:00.00:midob 2006.224.08:12:01.13/onsource/TRACKING 2006.224.08:12:01.13/wx/23.75,1004.7,100 2006.224.08:12:01.34/cable/+6.4336E-03 2006.224.08:12:02.43/va/01,08,usb,yes,45,48 2006.224.08:12:02.43/va/02,07,usb,yes,46,48 2006.224.08:12:02.43/va/03,06,usb,yes,49,49 2006.224.08:12:02.43/va/04,07,usb,yes,48,51 2006.224.08:12:02.43/va/05,07,usb,yes,55,58 2006.224.08:12:02.43/va/06,06,usb,yes,54,54 2006.224.08:12:02.43/va/07,06,usb,yes,55,55 2006.224.08:12:02.43/va/08,07,usb,yes,52,51 2006.224.08:12:02.66/valo/01,532.99,yes,locked 2006.224.08:12:02.66/valo/02,572.99,yes,locked 2006.224.08:12:02.66/valo/03,672.99,yes,locked 2006.224.08:12:02.66/valo/04,832.99,yes,locked 2006.224.08:12:02.66/valo/05,652.99,yes,locked 2006.224.08:12:02.66/valo/06,772.99,yes,locked 2006.224.08:12:02.66/valo/07,832.99,yes,locked 2006.224.08:12:02.66/valo/08,852.99,yes,locked 2006.224.08:12:03.75/vb/01,04,usb,yes,32,30 2006.224.08:12:03.75/vb/02,04,usb,yes,34,35 2006.224.08:12:03.75/vb/03,04,usb,yes,30,34 2006.224.08:12:03.75/vb/04,04,usb,yes,31,31 2006.224.08:12:03.75/vb/05,04,usb,yes,29,33 2006.224.08:12:03.75/vb/06,04,usb,yes,30,33 2006.224.08:12:03.75/vb/07,04,usb,yes,33,32 2006.224.08:12:03.75/vb/08,04,usb,yes,30,33 2006.224.08:12:03.99/vblo/01,632.99,yes,locked 2006.224.08:12:03.99/vblo/02,640.99,yes,locked 2006.224.08:12:03.99/vblo/03,656.99,yes,locked 2006.224.08:12:03.99/vblo/04,712.99,yes,locked 2006.224.08:12:03.99/vblo/05,744.99,yes,locked 2006.224.08:12:03.99/vblo/06,752.99,yes,locked 2006.224.08:12:03.99/vblo/07,734.99,yes,locked 2006.224.08:12:03.99/vblo/08,744.99,yes,locked 2006.224.08:12:04.14/vabw/8 2006.224.08:12:04.29/vbbw/8 2006.224.08:12:04.38/xfe/off,on,15.0 2006.224.08:12:04.77/ifatt/23,28,28,28 2006.224.08:12:05.08/fmout-gps/S +4.56E-07 2006.224.08:12:05.12:!2006.224.08:13:00 2006.224.08:13:00.01:data_valid=off 2006.224.08:13:00.01:postob 2006.224.08:13:00.18/cable/+6.4340E-03 2006.224.08:13:00.18/wx/23.77,1004.7,100 2006.224.08:13:01.08/fmout-gps/S +4.56E-07 2006.224.08:13:01.08:scan_name=224-0814,k06224,70 2006.224.08:13:01.08:source=1116+128,111857.30,123441.7,2000.0,ccw 2006.224.08:13:01.14#flagr#flagr/antenna,new-source 2006.224.08:13:02.14:checkk5 2006.224.08:13:02.51/chk_autoobs//k5ts1/ autoobs is running! 2006.224.08:13:02.88/chk_autoobs//k5ts2/ autoobs is running! 2006.224.08:13:03.25/chk_autoobs//k5ts3/ autoobs is running! 2006.224.08:13:03.62/chk_autoobs//k5ts4/ autoobs is running! 2006.224.08:13:03.98/chk_obsdata//k5ts1/T2240812??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.08:13:04.35/chk_obsdata//k5ts2/T2240812??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.08:13:04.72/chk_obsdata//k5ts3/T2240812??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.08:13:05.08/chk_obsdata//k5ts4/T2240812??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.08:13:05.77/k5log//k5ts1_log_newline 2006.224.08:13:06.45/k5log//k5ts2_log_newline 2006.224.08:13:07.13/k5log//k5ts3_log_newline 2006.224.08:13:07.81/k5log//k5ts4_log_newline 2006.224.08:13:07.83/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.224.08:13:07.83:4f8m12a=2 2006.224.08:13:07.83$4f8m12a/echo=on 2006.224.08:13:07.83$4f8m12a/pcalon 2006.224.08:13:07.83$pcalon/"no phase cal control is implemented here 2006.224.08:13:07.83$4f8m12a/"tpicd=stop 2006.224.08:13:07.83$4f8m12a/vc4f8 2006.224.08:13:07.83$vc4f8/valo=1,532.99 2006.224.08:13:07.84#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.224.08:13:07.84#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.224.08:13:07.84#ibcon#ireg 17 cls_cnt 0 2006.224.08:13:07.84#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.224.08:13:07.84#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.224.08:13:07.84#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.224.08:13:07.84#ibcon#enter wrdev, iclass 21, count 0 2006.224.08:13:07.84#ibcon#first serial, iclass 21, count 0 2006.224.08:13:07.84#ibcon#enter sib2, iclass 21, count 0 2006.224.08:13:07.84#ibcon#flushed, iclass 21, count 0 2006.224.08:13:07.84#ibcon#about to write, iclass 21, count 0 2006.224.08:13:07.84#ibcon#wrote, iclass 21, count 0 2006.224.08:13:07.84#ibcon#about to read 3, iclass 21, count 0 2006.224.08:13:07.88#ibcon#read 3, iclass 21, count 0 2006.224.08:13:07.88#ibcon#about to read 4, iclass 21, count 0 2006.224.08:13:07.88#ibcon#read 4, iclass 21, count 0 2006.224.08:13:07.88#ibcon#about to read 5, iclass 21, count 0 2006.224.08:13:07.88#ibcon#read 5, iclass 21, count 0 2006.224.08:13:07.88#ibcon#about to read 6, iclass 21, count 0 2006.224.08:13:07.88#ibcon#read 6, iclass 21, count 0 2006.224.08:13:07.88#ibcon#end of sib2, iclass 21, count 0 2006.224.08:13:07.88#ibcon#*mode == 0, iclass 21, count 0 2006.224.08:13:07.88#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.224.08:13:07.88#ibcon#[26=FRQ=01,532.99\r\n] 2006.224.08:13:07.88#ibcon#*before write, iclass 21, count 0 2006.224.08:13:07.88#ibcon#enter sib2, iclass 21, count 0 2006.224.08:13:07.88#ibcon#flushed, iclass 21, count 0 2006.224.08:13:07.88#ibcon#about to write, iclass 21, count 0 2006.224.08:13:07.88#ibcon#wrote, iclass 21, count 0 2006.224.08:13:07.88#ibcon#about to read 3, iclass 21, count 0 2006.224.08:13:07.90#abcon#[5=S1D000X0/0*\r\n] 2006.224.08:13:07.93#ibcon#read 3, iclass 21, count 0 2006.224.08:13:07.93#ibcon#about to read 4, iclass 21, count 0 2006.224.08:13:07.93#ibcon#read 4, iclass 21, count 0 2006.224.08:13:07.93#ibcon#about to read 5, iclass 21, count 0 2006.224.08:13:07.93#ibcon#read 5, iclass 21, count 0 2006.224.08:13:07.93#ibcon#about to read 6, iclass 21, count 0 2006.224.08:13:07.93#ibcon#read 6, iclass 21, count 0 2006.224.08:13:07.93#ibcon#end of sib2, iclass 21, count 0 2006.224.08:13:07.93#ibcon#*after write, iclass 21, count 0 2006.224.08:13:07.93#ibcon#*before return 0, iclass 21, count 0 2006.224.08:13:07.93#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.224.08:13:07.93#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.224.08:13:07.93#ibcon#about to clear, iclass 21 cls_cnt 0 2006.224.08:13:07.93#ibcon#cleared, iclass 21 cls_cnt 0 2006.224.08:13:07.93$vc4f8/va=1,8 2006.224.08:13:07.93#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.224.08:13:07.93#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.224.08:13:07.93#ibcon#ireg 11 cls_cnt 2 2006.224.08:13:07.93#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.224.08:13:07.93#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.224.08:13:07.93#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.224.08:13:07.93#ibcon#enter wrdev, iclass 24, count 2 2006.224.08:13:07.93#ibcon#first serial, iclass 24, count 2 2006.224.08:13:07.93#ibcon#enter sib2, iclass 24, count 2 2006.224.08:13:07.93#ibcon#flushed, iclass 24, count 2 2006.224.08:13:07.93#ibcon#about to write, iclass 24, count 2 2006.224.08:13:07.93#ibcon#wrote, iclass 24, count 2 2006.224.08:13:07.93#ibcon#about to read 3, iclass 24, count 2 2006.224.08:13:07.95#ibcon#read 3, iclass 24, count 2 2006.224.08:13:07.95#ibcon#about to read 4, iclass 24, count 2 2006.224.08:13:07.95#ibcon#read 4, iclass 24, count 2 2006.224.08:13:07.95#ibcon#about to read 5, iclass 24, count 2 2006.224.08:13:07.95#ibcon#read 5, iclass 24, count 2 2006.224.08:13:07.95#ibcon#about to read 6, iclass 24, count 2 2006.224.08:13:07.95#ibcon#read 6, iclass 24, count 2 2006.224.08:13:07.95#ibcon#end of sib2, iclass 24, count 2 2006.224.08:13:07.95#ibcon#*mode == 0, iclass 24, count 2 2006.224.08:13:07.95#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.224.08:13:07.95#ibcon#[25=AT01-08\r\n] 2006.224.08:13:07.95#ibcon#*before write, iclass 24, count 2 2006.224.08:13:07.95#ibcon#enter sib2, iclass 24, count 2 2006.224.08:13:07.95#ibcon#flushed, iclass 24, count 2 2006.224.08:13:07.95#ibcon#about to write, iclass 24, count 2 2006.224.08:13:07.95#ibcon#wrote, iclass 24, count 2 2006.224.08:13:07.95#ibcon#about to read 3, iclass 24, count 2 2006.224.08:13:07.98#ibcon#read 3, iclass 24, count 2 2006.224.08:13:07.98#ibcon#about to read 4, iclass 24, count 2 2006.224.08:13:07.98#ibcon#read 4, iclass 24, count 2 2006.224.08:13:07.98#ibcon#about to read 5, iclass 24, count 2 2006.224.08:13:07.98#ibcon#read 5, iclass 24, count 2 2006.224.08:13:07.98#ibcon#about to read 6, iclass 24, count 2 2006.224.08:13:07.98#ibcon#read 6, iclass 24, count 2 2006.224.08:13:07.98#ibcon#end of sib2, iclass 24, count 2 2006.224.08:13:07.98#ibcon#*after write, iclass 24, count 2 2006.224.08:13:07.98#ibcon#*before return 0, iclass 24, count 2 2006.224.08:13:07.98#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.224.08:13:07.98#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.224.08:13:07.98#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.224.08:13:07.98#ibcon#ireg 7 cls_cnt 0 2006.224.08:13:07.98#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.224.08:13:08.10#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.224.08:13:08.10#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.224.08:13:08.10#ibcon#enter wrdev, iclass 24, count 0 2006.224.08:13:08.10#ibcon#first serial, iclass 24, count 0 2006.224.08:13:08.10#ibcon#enter sib2, iclass 24, count 0 2006.224.08:13:08.10#ibcon#flushed, iclass 24, count 0 2006.224.08:13:08.10#ibcon#about to write, iclass 24, count 0 2006.224.08:13:08.10#ibcon#wrote, iclass 24, count 0 2006.224.08:13:08.10#ibcon#about to read 3, iclass 24, count 0 2006.224.08:13:08.12#ibcon#read 3, iclass 24, count 0 2006.224.08:13:08.12#ibcon#about to read 4, iclass 24, count 0 2006.224.08:13:08.12#ibcon#read 4, iclass 24, count 0 2006.224.08:13:08.12#ibcon#about to read 5, iclass 24, count 0 2006.224.08:13:08.12#ibcon#read 5, iclass 24, count 0 2006.224.08:13:08.12#ibcon#about to read 6, iclass 24, count 0 2006.224.08:13:08.12#ibcon#read 6, iclass 24, count 0 2006.224.08:13:08.12#ibcon#end of sib2, iclass 24, count 0 2006.224.08:13:08.12#ibcon#*mode == 0, iclass 24, count 0 2006.224.08:13:08.12#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.224.08:13:08.12#ibcon#[25=USB\r\n] 2006.224.08:13:08.12#ibcon#*before write, iclass 24, count 0 2006.224.08:13:08.12#ibcon#enter sib2, iclass 24, count 0 2006.224.08:13:08.12#ibcon#flushed, iclass 24, count 0 2006.224.08:13:08.12#ibcon#about to write, iclass 24, count 0 2006.224.08:13:08.12#ibcon#wrote, iclass 24, count 0 2006.224.08:13:08.12#ibcon#about to read 3, iclass 24, count 0 2006.224.08:13:08.15#ibcon#read 3, iclass 24, count 0 2006.224.08:13:08.15#ibcon#about to read 4, iclass 24, count 0 2006.224.08:13:08.15#ibcon#read 4, iclass 24, count 0 2006.224.08:13:08.15#ibcon#about to read 5, iclass 24, count 0 2006.224.08:13:08.15#ibcon#read 5, iclass 24, count 0 2006.224.08:13:08.15#ibcon#about to read 6, iclass 24, count 0 2006.224.08:13:08.15#ibcon#read 6, iclass 24, count 0 2006.224.08:13:08.15#ibcon#end of sib2, iclass 24, count 0 2006.224.08:13:08.15#ibcon#*after write, iclass 24, count 0 2006.224.08:13:08.15#ibcon#*before return 0, iclass 24, count 0 2006.224.08:13:08.15#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.224.08:13:08.15#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.224.08:13:08.15#ibcon#about to clear, iclass 24 cls_cnt 0 2006.224.08:13:08.15#ibcon#cleared, iclass 24 cls_cnt 0 2006.224.08:13:08.15$vc4f8/valo=2,572.99 2006.224.08:13:08.15#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.224.08:13:08.15#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.224.08:13:08.15#ibcon#ireg 17 cls_cnt 0 2006.224.08:13:08.15#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.224.08:13:08.15#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.224.08:13:08.15#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.224.08:13:08.15#ibcon#enter wrdev, iclass 26, count 0 2006.224.08:13:08.15#ibcon#first serial, iclass 26, count 0 2006.224.08:13:08.15#ibcon#enter sib2, iclass 26, count 0 2006.224.08:13:08.15#ibcon#flushed, iclass 26, count 0 2006.224.08:13:08.15#ibcon#about to write, iclass 26, count 0 2006.224.08:13:08.15#ibcon#wrote, iclass 26, count 0 2006.224.08:13:08.15#ibcon#about to read 3, iclass 26, count 0 2006.224.08:13:08.17#ibcon#read 3, iclass 26, count 0 2006.224.08:13:08.17#ibcon#about to read 4, iclass 26, count 0 2006.224.08:13:08.17#ibcon#read 4, iclass 26, count 0 2006.224.08:13:08.17#ibcon#about to read 5, iclass 26, count 0 2006.224.08:13:08.17#ibcon#read 5, iclass 26, count 0 2006.224.08:13:08.17#ibcon#about to read 6, iclass 26, count 0 2006.224.08:13:08.17#ibcon#read 6, iclass 26, count 0 2006.224.08:13:08.17#ibcon#end of sib2, iclass 26, count 0 2006.224.08:13:08.17#ibcon#*mode == 0, iclass 26, count 0 2006.224.08:13:08.17#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.224.08:13:08.17#ibcon#[26=FRQ=02,572.99\r\n] 2006.224.08:13:08.17#ibcon#*before write, iclass 26, count 0 2006.224.08:13:08.17#ibcon#enter sib2, iclass 26, count 0 2006.224.08:13:08.17#ibcon#flushed, iclass 26, count 0 2006.224.08:13:08.17#ibcon#about to write, iclass 26, count 0 2006.224.08:13:08.17#ibcon#wrote, iclass 26, count 0 2006.224.08:13:08.17#ibcon#about to read 3, iclass 26, count 0 2006.224.08:13:08.21#ibcon#read 3, iclass 26, count 0 2006.224.08:13:08.21#ibcon#about to read 4, iclass 26, count 0 2006.224.08:13:08.21#ibcon#read 4, iclass 26, count 0 2006.224.08:13:08.21#ibcon#about to read 5, iclass 26, count 0 2006.224.08:13:08.21#ibcon#read 5, iclass 26, count 0 2006.224.08:13:08.21#ibcon#about to read 6, iclass 26, count 0 2006.224.08:13:08.21#ibcon#read 6, iclass 26, count 0 2006.224.08:13:08.21#ibcon#end of sib2, iclass 26, count 0 2006.224.08:13:08.21#ibcon#*after write, iclass 26, count 0 2006.224.08:13:08.21#ibcon#*before return 0, iclass 26, count 0 2006.224.08:13:08.21#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.224.08:13:08.21#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.224.08:13:08.21#ibcon#about to clear, iclass 26 cls_cnt 0 2006.224.08:13:08.21#ibcon#cleared, iclass 26 cls_cnt 0 2006.224.08:13:08.21$vc4f8/va=2,7 2006.224.08:13:08.21#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.224.08:13:08.21#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.224.08:13:08.21#ibcon#ireg 11 cls_cnt 2 2006.224.08:13:08.21#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.224.08:13:08.27#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.224.08:13:08.27#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.224.08:13:08.27#ibcon#enter wrdev, iclass 28, count 2 2006.224.08:13:08.27#ibcon#first serial, iclass 28, count 2 2006.224.08:13:08.27#ibcon#enter sib2, iclass 28, count 2 2006.224.08:13:08.27#ibcon#flushed, iclass 28, count 2 2006.224.08:13:08.27#ibcon#about to write, iclass 28, count 2 2006.224.08:13:08.27#ibcon#wrote, iclass 28, count 2 2006.224.08:13:08.27#ibcon#about to read 3, iclass 28, count 2 2006.224.08:13:08.29#ibcon#read 3, iclass 28, count 2 2006.224.08:13:08.29#ibcon#about to read 4, iclass 28, count 2 2006.224.08:13:08.29#ibcon#read 4, iclass 28, count 2 2006.224.08:13:08.29#ibcon#about to read 5, iclass 28, count 2 2006.224.08:13:08.29#ibcon#read 5, iclass 28, count 2 2006.224.08:13:08.29#ibcon#about to read 6, iclass 28, count 2 2006.224.08:13:08.29#ibcon#read 6, iclass 28, count 2 2006.224.08:13:08.29#ibcon#end of sib2, iclass 28, count 2 2006.224.08:13:08.29#ibcon#*mode == 0, iclass 28, count 2 2006.224.08:13:08.29#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.224.08:13:08.29#ibcon#[25=AT02-07\r\n] 2006.224.08:13:08.29#ibcon#*before write, iclass 28, count 2 2006.224.08:13:08.29#ibcon#enter sib2, iclass 28, count 2 2006.224.08:13:08.29#ibcon#flushed, iclass 28, count 2 2006.224.08:13:08.29#ibcon#about to write, iclass 28, count 2 2006.224.08:13:08.29#ibcon#wrote, iclass 28, count 2 2006.224.08:13:08.29#ibcon#about to read 3, iclass 28, count 2 2006.224.08:13:08.32#ibcon#read 3, iclass 28, count 2 2006.224.08:13:08.32#ibcon#about to read 4, iclass 28, count 2 2006.224.08:13:08.32#ibcon#read 4, iclass 28, count 2 2006.224.08:13:08.32#ibcon#about to read 5, iclass 28, count 2 2006.224.08:13:08.32#ibcon#read 5, iclass 28, count 2 2006.224.08:13:08.32#ibcon#about to read 6, iclass 28, count 2 2006.224.08:13:08.32#ibcon#read 6, iclass 28, count 2 2006.224.08:13:08.32#ibcon#end of sib2, iclass 28, count 2 2006.224.08:13:08.32#ibcon#*after write, iclass 28, count 2 2006.224.08:13:08.32#ibcon#*before return 0, iclass 28, count 2 2006.224.08:13:08.32#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.224.08:13:08.32#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.224.08:13:08.32#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.224.08:13:08.32#ibcon#ireg 7 cls_cnt 0 2006.224.08:13:08.32#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.224.08:13:08.44#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.224.08:13:08.44#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.224.08:13:08.44#ibcon#enter wrdev, iclass 28, count 0 2006.224.08:13:08.44#ibcon#first serial, iclass 28, count 0 2006.224.08:13:08.44#ibcon#enter sib2, iclass 28, count 0 2006.224.08:13:08.44#ibcon#flushed, iclass 28, count 0 2006.224.08:13:08.44#ibcon#about to write, iclass 28, count 0 2006.224.08:13:08.44#ibcon#wrote, iclass 28, count 0 2006.224.08:13:08.44#ibcon#about to read 3, iclass 28, count 0 2006.224.08:13:08.46#ibcon#read 3, iclass 28, count 0 2006.224.08:13:08.46#ibcon#about to read 4, iclass 28, count 0 2006.224.08:13:08.46#ibcon#read 4, iclass 28, count 0 2006.224.08:13:08.46#ibcon#about to read 5, iclass 28, count 0 2006.224.08:13:08.46#ibcon#read 5, iclass 28, count 0 2006.224.08:13:08.46#ibcon#about to read 6, iclass 28, count 0 2006.224.08:13:08.46#ibcon#read 6, iclass 28, count 0 2006.224.08:13:08.46#ibcon#end of sib2, iclass 28, count 0 2006.224.08:13:08.46#ibcon#*mode == 0, iclass 28, count 0 2006.224.08:13:08.46#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.224.08:13:08.46#ibcon#[25=USB\r\n] 2006.224.08:13:08.46#ibcon#*before write, iclass 28, count 0 2006.224.08:13:08.46#ibcon#enter sib2, iclass 28, count 0 2006.224.08:13:08.46#ibcon#flushed, iclass 28, count 0 2006.224.08:13:08.46#ibcon#about to write, iclass 28, count 0 2006.224.08:13:08.46#ibcon#wrote, iclass 28, count 0 2006.224.08:13:08.46#ibcon#about to read 3, iclass 28, count 0 2006.224.08:13:08.49#ibcon#read 3, iclass 28, count 0 2006.224.08:13:08.49#ibcon#about to read 4, iclass 28, count 0 2006.224.08:13:08.49#ibcon#read 4, iclass 28, count 0 2006.224.08:13:08.49#ibcon#about to read 5, iclass 28, count 0 2006.224.08:13:08.49#ibcon#read 5, iclass 28, count 0 2006.224.08:13:08.49#ibcon#about to read 6, iclass 28, count 0 2006.224.08:13:08.49#ibcon#read 6, iclass 28, count 0 2006.224.08:13:08.49#ibcon#end of sib2, iclass 28, count 0 2006.224.08:13:08.49#ibcon#*after write, iclass 28, count 0 2006.224.08:13:08.49#ibcon#*before return 0, iclass 28, count 0 2006.224.08:13:08.49#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.224.08:13:08.49#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.224.08:13:08.49#ibcon#about to clear, iclass 28 cls_cnt 0 2006.224.08:13:08.49#ibcon#cleared, iclass 28 cls_cnt 0 2006.224.08:13:08.49$vc4f8/valo=3,672.99 2006.224.08:13:08.49#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.224.08:13:08.49#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.224.08:13:08.49#ibcon#ireg 17 cls_cnt 0 2006.224.08:13:08.49#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.224.08:13:08.49#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.224.08:13:08.49#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.224.08:13:08.49#ibcon#enter wrdev, iclass 30, count 0 2006.224.08:13:08.49#ibcon#first serial, iclass 30, count 0 2006.224.08:13:08.49#ibcon#enter sib2, iclass 30, count 0 2006.224.08:13:08.49#ibcon#flushed, iclass 30, count 0 2006.224.08:13:08.49#ibcon#about to write, iclass 30, count 0 2006.224.08:13:08.49#ibcon#wrote, iclass 30, count 0 2006.224.08:13:08.49#ibcon#about to read 3, iclass 30, count 0 2006.224.08:13:08.51#ibcon#read 3, iclass 30, count 0 2006.224.08:13:08.51#ibcon#about to read 4, iclass 30, count 0 2006.224.08:13:08.51#ibcon#read 4, iclass 30, count 0 2006.224.08:13:08.51#ibcon#about to read 5, iclass 30, count 0 2006.224.08:13:08.51#ibcon#read 5, iclass 30, count 0 2006.224.08:13:08.51#ibcon#about to read 6, iclass 30, count 0 2006.224.08:13:08.51#ibcon#read 6, iclass 30, count 0 2006.224.08:13:08.51#ibcon#end of sib2, iclass 30, count 0 2006.224.08:13:08.51#ibcon#*mode == 0, iclass 30, count 0 2006.224.08:13:08.51#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.224.08:13:08.51#ibcon#[26=FRQ=03,672.99\r\n] 2006.224.08:13:08.51#ibcon#*before write, iclass 30, count 0 2006.224.08:13:08.51#ibcon#enter sib2, iclass 30, count 0 2006.224.08:13:08.51#ibcon#flushed, iclass 30, count 0 2006.224.08:13:08.51#ibcon#about to write, iclass 30, count 0 2006.224.08:13:08.51#ibcon#wrote, iclass 30, count 0 2006.224.08:13:08.51#ibcon#about to read 3, iclass 30, count 0 2006.224.08:13:08.56#ibcon#read 3, iclass 30, count 0 2006.224.08:13:08.56#ibcon#about to read 4, iclass 30, count 0 2006.224.08:13:08.56#ibcon#read 4, iclass 30, count 0 2006.224.08:13:08.56#ibcon#about to read 5, iclass 30, count 0 2006.224.08:13:08.56#ibcon#read 5, iclass 30, count 0 2006.224.08:13:08.56#ibcon#about to read 6, iclass 30, count 0 2006.224.08:13:08.56#ibcon#read 6, iclass 30, count 0 2006.224.08:13:08.56#ibcon#end of sib2, iclass 30, count 0 2006.224.08:13:08.56#ibcon#*after write, iclass 30, count 0 2006.224.08:13:08.56#ibcon#*before return 0, iclass 30, count 0 2006.224.08:13:08.56#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.224.08:13:08.56#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.224.08:13:08.56#ibcon#about to clear, iclass 30 cls_cnt 0 2006.224.08:13:08.56#ibcon#cleared, iclass 30 cls_cnt 0 2006.224.08:13:08.56$vc4f8/va=3,6 2006.224.08:13:08.56#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.224.08:13:08.56#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.224.08:13:08.56#ibcon#ireg 11 cls_cnt 2 2006.224.08:13:08.56#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.224.08:13:08.61#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.224.08:13:08.61#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.224.08:13:08.61#ibcon#enter wrdev, iclass 32, count 2 2006.224.08:13:08.61#ibcon#first serial, iclass 32, count 2 2006.224.08:13:08.61#ibcon#enter sib2, iclass 32, count 2 2006.224.08:13:08.61#ibcon#flushed, iclass 32, count 2 2006.224.08:13:08.61#ibcon#about to write, iclass 32, count 2 2006.224.08:13:08.61#ibcon#wrote, iclass 32, count 2 2006.224.08:13:08.61#ibcon#about to read 3, iclass 32, count 2 2006.224.08:13:08.63#ibcon#read 3, iclass 32, count 2 2006.224.08:13:08.63#ibcon#about to read 4, iclass 32, count 2 2006.224.08:13:08.63#ibcon#read 4, iclass 32, count 2 2006.224.08:13:08.63#ibcon#about to read 5, iclass 32, count 2 2006.224.08:13:08.63#ibcon#read 5, iclass 32, count 2 2006.224.08:13:08.63#ibcon#about to read 6, iclass 32, count 2 2006.224.08:13:08.63#ibcon#read 6, iclass 32, count 2 2006.224.08:13:08.63#ibcon#end of sib2, iclass 32, count 2 2006.224.08:13:08.63#ibcon#*mode == 0, iclass 32, count 2 2006.224.08:13:08.63#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.224.08:13:08.63#ibcon#[25=AT03-06\r\n] 2006.224.08:13:08.63#ibcon#*before write, iclass 32, count 2 2006.224.08:13:08.63#ibcon#enter sib2, iclass 32, count 2 2006.224.08:13:08.63#ibcon#flushed, iclass 32, count 2 2006.224.08:13:08.63#ibcon#about to write, iclass 32, count 2 2006.224.08:13:08.63#ibcon#wrote, iclass 32, count 2 2006.224.08:13:08.63#ibcon#about to read 3, iclass 32, count 2 2006.224.08:13:08.66#ibcon#read 3, iclass 32, count 2 2006.224.08:13:08.66#ibcon#about to read 4, iclass 32, count 2 2006.224.08:13:08.66#ibcon#read 4, iclass 32, count 2 2006.224.08:13:08.66#ibcon#about to read 5, iclass 32, count 2 2006.224.08:13:08.66#ibcon#read 5, iclass 32, count 2 2006.224.08:13:08.66#ibcon#about to read 6, iclass 32, count 2 2006.224.08:13:08.66#ibcon#read 6, iclass 32, count 2 2006.224.08:13:08.66#ibcon#end of sib2, iclass 32, count 2 2006.224.08:13:08.66#ibcon#*after write, iclass 32, count 2 2006.224.08:13:08.66#ibcon#*before return 0, iclass 32, count 2 2006.224.08:13:08.66#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.224.08:13:08.66#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.224.08:13:08.66#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.224.08:13:08.66#ibcon#ireg 7 cls_cnt 0 2006.224.08:13:08.66#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.224.08:13:08.78#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.224.08:13:08.78#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.224.08:13:08.78#ibcon#enter wrdev, iclass 32, count 0 2006.224.08:13:08.78#ibcon#first serial, iclass 32, count 0 2006.224.08:13:08.78#ibcon#enter sib2, iclass 32, count 0 2006.224.08:13:08.78#ibcon#flushed, iclass 32, count 0 2006.224.08:13:08.78#ibcon#about to write, iclass 32, count 0 2006.224.08:13:08.78#ibcon#wrote, iclass 32, count 0 2006.224.08:13:08.78#ibcon#about to read 3, iclass 32, count 0 2006.224.08:13:08.80#ibcon#read 3, iclass 32, count 0 2006.224.08:13:08.80#ibcon#about to read 4, iclass 32, count 0 2006.224.08:13:08.80#ibcon#read 4, iclass 32, count 0 2006.224.08:13:08.80#ibcon#about to read 5, iclass 32, count 0 2006.224.08:13:08.80#ibcon#read 5, iclass 32, count 0 2006.224.08:13:08.80#ibcon#about to read 6, iclass 32, count 0 2006.224.08:13:08.80#ibcon#read 6, iclass 32, count 0 2006.224.08:13:08.80#ibcon#end of sib2, iclass 32, count 0 2006.224.08:13:08.80#ibcon#*mode == 0, iclass 32, count 0 2006.224.08:13:08.80#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.224.08:13:08.80#ibcon#[25=USB\r\n] 2006.224.08:13:08.80#ibcon#*before write, iclass 32, count 0 2006.224.08:13:08.80#ibcon#enter sib2, iclass 32, count 0 2006.224.08:13:08.80#ibcon#flushed, iclass 32, count 0 2006.224.08:13:08.80#ibcon#about to write, iclass 32, count 0 2006.224.08:13:08.80#ibcon#wrote, iclass 32, count 0 2006.224.08:13:08.80#ibcon#about to read 3, iclass 32, count 0 2006.224.08:13:08.83#ibcon#read 3, iclass 32, count 0 2006.224.08:13:08.83#ibcon#about to read 4, iclass 32, count 0 2006.224.08:13:08.83#ibcon#read 4, iclass 32, count 0 2006.224.08:13:08.83#ibcon#about to read 5, iclass 32, count 0 2006.224.08:13:08.83#ibcon#read 5, iclass 32, count 0 2006.224.08:13:08.83#ibcon#about to read 6, iclass 32, count 0 2006.224.08:13:08.83#ibcon#read 6, iclass 32, count 0 2006.224.08:13:08.83#ibcon#end of sib2, iclass 32, count 0 2006.224.08:13:08.83#ibcon#*after write, iclass 32, count 0 2006.224.08:13:08.83#ibcon#*before return 0, iclass 32, count 0 2006.224.08:13:08.83#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.224.08:13:08.83#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.224.08:13:08.83#ibcon#about to clear, iclass 32 cls_cnt 0 2006.224.08:13:08.83#ibcon#cleared, iclass 32 cls_cnt 0 2006.224.08:13:08.83$vc4f8/valo=4,832.99 2006.224.08:13:08.83#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.224.08:13:08.83#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.224.08:13:08.83#ibcon#ireg 17 cls_cnt 0 2006.224.08:13:08.83#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.224.08:13:08.83#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.224.08:13:08.83#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.224.08:13:08.83#ibcon#enter wrdev, iclass 34, count 0 2006.224.08:13:08.83#ibcon#first serial, iclass 34, count 0 2006.224.08:13:08.83#ibcon#enter sib2, iclass 34, count 0 2006.224.08:13:08.83#ibcon#flushed, iclass 34, count 0 2006.224.08:13:08.83#ibcon#about to write, iclass 34, count 0 2006.224.08:13:08.83#ibcon#wrote, iclass 34, count 0 2006.224.08:13:08.83#ibcon#about to read 3, iclass 34, count 0 2006.224.08:13:08.85#ibcon#read 3, iclass 34, count 0 2006.224.08:13:08.85#ibcon#about to read 4, iclass 34, count 0 2006.224.08:13:08.85#ibcon#read 4, iclass 34, count 0 2006.224.08:13:08.85#ibcon#about to read 5, iclass 34, count 0 2006.224.08:13:08.85#ibcon#read 5, iclass 34, count 0 2006.224.08:13:08.85#ibcon#about to read 6, iclass 34, count 0 2006.224.08:13:08.85#ibcon#read 6, iclass 34, count 0 2006.224.08:13:08.85#ibcon#end of sib2, iclass 34, count 0 2006.224.08:13:08.85#ibcon#*mode == 0, iclass 34, count 0 2006.224.08:13:08.85#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.224.08:13:08.85#ibcon#[26=FRQ=04,832.99\r\n] 2006.224.08:13:08.85#ibcon#*before write, iclass 34, count 0 2006.224.08:13:08.85#ibcon#enter sib2, iclass 34, count 0 2006.224.08:13:08.85#ibcon#flushed, iclass 34, count 0 2006.224.08:13:08.85#ibcon#about to write, iclass 34, count 0 2006.224.08:13:08.85#ibcon#wrote, iclass 34, count 0 2006.224.08:13:08.85#ibcon#about to read 3, iclass 34, count 0 2006.224.08:13:08.90#ibcon#read 3, iclass 34, count 0 2006.224.08:13:08.90#ibcon#about to read 4, iclass 34, count 0 2006.224.08:13:08.90#ibcon#read 4, iclass 34, count 0 2006.224.08:13:08.90#ibcon#about to read 5, iclass 34, count 0 2006.224.08:13:08.90#ibcon#read 5, iclass 34, count 0 2006.224.08:13:08.90#ibcon#about to read 6, iclass 34, count 0 2006.224.08:13:08.90#ibcon#read 6, iclass 34, count 0 2006.224.08:13:08.90#ibcon#end of sib2, iclass 34, count 0 2006.224.08:13:08.90#ibcon#*after write, iclass 34, count 0 2006.224.08:13:08.90#ibcon#*before return 0, iclass 34, count 0 2006.224.08:13:08.90#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.224.08:13:08.90#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.224.08:13:08.90#ibcon#about to clear, iclass 34 cls_cnt 0 2006.224.08:13:08.90#ibcon#cleared, iclass 34 cls_cnt 0 2006.224.08:13:08.90$vc4f8/va=4,7 2006.224.08:13:08.90#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.224.08:13:08.90#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.224.08:13:08.90#ibcon#ireg 11 cls_cnt 2 2006.224.08:13:08.90#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.224.08:13:08.95#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.224.08:13:08.95#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.224.08:13:08.95#ibcon#enter wrdev, iclass 36, count 2 2006.224.08:13:08.95#ibcon#first serial, iclass 36, count 2 2006.224.08:13:08.95#ibcon#enter sib2, iclass 36, count 2 2006.224.08:13:08.95#ibcon#flushed, iclass 36, count 2 2006.224.08:13:08.95#ibcon#about to write, iclass 36, count 2 2006.224.08:13:08.95#ibcon#wrote, iclass 36, count 2 2006.224.08:13:08.95#ibcon#about to read 3, iclass 36, count 2 2006.224.08:13:08.97#ibcon#read 3, iclass 36, count 2 2006.224.08:13:08.97#ibcon#about to read 4, iclass 36, count 2 2006.224.08:13:08.97#ibcon#read 4, iclass 36, count 2 2006.224.08:13:08.97#ibcon#about to read 5, iclass 36, count 2 2006.224.08:13:08.97#ibcon#read 5, iclass 36, count 2 2006.224.08:13:08.97#ibcon#about to read 6, iclass 36, count 2 2006.224.08:13:08.97#ibcon#read 6, iclass 36, count 2 2006.224.08:13:08.97#ibcon#end of sib2, iclass 36, count 2 2006.224.08:13:08.97#ibcon#*mode == 0, iclass 36, count 2 2006.224.08:13:08.97#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.224.08:13:08.97#ibcon#[25=AT04-07\r\n] 2006.224.08:13:08.97#ibcon#*before write, iclass 36, count 2 2006.224.08:13:08.97#ibcon#enter sib2, iclass 36, count 2 2006.224.08:13:08.97#ibcon#flushed, iclass 36, count 2 2006.224.08:13:08.97#ibcon#about to write, iclass 36, count 2 2006.224.08:13:08.97#ibcon#wrote, iclass 36, count 2 2006.224.08:13:08.97#ibcon#about to read 3, iclass 36, count 2 2006.224.08:13:09.00#ibcon#read 3, iclass 36, count 2 2006.224.08:13:09.00#ibcon#about to read 4, iclass 36, count 2 2006.224.08:13:09.00#ibcon#read 4, iclass 36, count 2 2006.224.08:13:09.00#ibcon#about to read 5, iclass 36, count 2 2006.224.08:13:09.00#ibcon#read 5, iclass 36, count 2 2006.224.08:13:09.00#ibcon#about to read 6, iclass 36, count 2 2006.224.08:13:09.00#ibcon#read 6, iclass 36, count 2 2006.224.08:13:09.00#ibcon#end of sib2, iclass 36, count 2 2006.224.08:13:09.00#ibcon#*after write, iclass 36, count 2 2006.224.08:13:09.00#ibcon#*before return 0, iclass 36, count 2 2006.224.08:13:09.00#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.224.08:13:09.00#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.224.08:13:09.00#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.224.08:13:09.00#ibcon#ireg 7 cls_cnt 0 2006.224.08:13:09.00#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.224.08:13:09.12#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.224.08:13:09.12#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.224.08:13:09.12#ibcon#enter wrdev, iclass 36, count 0 2006.224.08:13:09.12#ibcon#first serial, iclass 36, count 0 2006.224.08:13:09.12#ibcon#enter sib2, iclass 36, count 0 2006.224.08:13:09.12#ibcon#flushed, iclass 36, count 0 2006.224.08:13:09.12#ibcon#about to write, iclass 36, count 0 2006.224.08:13:09.12#ibcon#wrote, iclass 36, count 0 2006.224.08:13:09.12#ibcon#about to read 3, iclass 36, count 0 2006.224.08:13:09.14#ibcon#read 3, iclass 36, count 0 2006.224.08:13:09.14#ibcon#about to read 4, iclass 36, count 0 2006.224.08:13:09.14#ibcon#read 4, iclass 36, count 0 2006.224.08:13:09.14#ibcon#about to read 5, iclass 36, count 0 2006.224.08:13:09.14#ibcon#read 5, iclass 36, count 0 2006.224.08:13:09.14#ibcon#about to read 6, iclass 36, count 0 2006.224.08:13:09.14#ibcon#read 6, iclass 36, count 0 2006.224.08:13:09.14#ibcon#end of sib2, iclass 36, count 0 2006.224.08:13:09.14#ibcon#*mode == 0, iclass 36, count 0 2006.224.08:13:09.14#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.224.08:13:09.14#ibcon#[25=USB\r\n] 2006.224.08:13:09.14#ibcon#*before write, iclass 36, count 0 2006.224.08:13:09.14#ibcon#enter sib2, iclass 36, count 0 2006.224.08:13:09.14#ibcon#flushed, iclass 36, count 0 2006.224.08:13:09.14#ibcon#about to write, iclass 36, count 0 2006.224.08:13:09.14#ibcon#wrote, iclass 36, count 0 2006.224.08:13:09.14#ibcon#about to read 3, iclass 36, count 0 2006.224.08:13:09.17#ibcon#read 3, iclass 36, count 0 2006.224.08:13:09.17#ibcon#about to read 4, iclass 36, count 0 2006.224.08:13:09.17#ibcon#read 4, iclass 36, count 0 2006.224.08:13:09.17#ibcon#about to read 5, iclass 36, count 0 2006.224.08:13:09.17#ibcon#read 5, iclass 36, count 0 2006.224.08:13:09.17#ibcon#about to read 6, iclass 36, count 0 2006.224.08:13:09.17#ibcon#read 6, iclass 36, count 0 2006.224.08:13:09.17#ibcon#end of sib2, iclass 36, count 0 2006.224.08:13:09.17#ibcon#*after write, iclass 36, count 0 2006.224.08:13:09.17#ibcon#*before return 0, iclass 36, count 0 2006.224.08:13:09.17#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.224.08:13:09.17#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.224.08:13:09.17#ibcon#about to clear, iclass 36 cls_cnt 0 2006.224.08:13:09.17#ibcon#cleared, iclass 36 cls_cnt 0 2006.224.08:13:09.17$vc4f8/valo=5,652.99 2006.224.08:13:09.17#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.224.08:13:09.17#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.224.08:13:09.17#ibcon#ireg 17 cls_cnt 0 2006.224.08:13:09.17#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.224.08:13:09.17#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.224.08:13:09.17#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.224.08:13:09.17#ibcon#enter wrdev, iclass 38, count 0 2006.224.08:13:09.17#ibcon#first serial, iclass 38, count 0 2006.224.08:13:09.17#ibcon#enter sib2, iclass 38, count 0 2006.224.08:13:09.17#ibcon#flushed, iclass 38, count 0 2006.224.08:13:09.17#ibcon#about to write, iclass 38, count 0 2006.224.08:13:09.17#ibcon#wrote, iclass 38, count 0 2006.224.08:13:09.17#ibcon#about to read 3, iclass 38, count 0 2006.224.08:13:09.19#ibcon#read 3, iclass 38, count 0 2006.224.08:13:09.19#ibcon#about to read 4, iclass 38, count 0 2006.224.08:13:09.19#ibcon#read 4, iclass 38, count 0 2006.224.08:13:09.19#ibcon#about to read 5, iclass 38, count 0 2006.224.08:13:09.19#ibcon#read 5, iclass 38, count 0 2006.224.08:13:09.19#ibcon#about to read 6, iclass 38, count 0 2006.224.08:13:09.19#ibcon#read 6, iclass 38, count 0 2006.224.08:13:09.19#ibcon#end of sib2, iclass 38, count 0 2006.224.08:13:09.19#ibcon#*mode == 0, iclass 38, count 0 2006.224.08:13:09.19#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.224.08:13:09.19#ibcon#[26=FRQ=05,652.99\r\n] 2006.224.08:13:09.19#ibcon#*before write, iclass 38, count 0 2006.224.08:13:09.19#ibcon#enter sib2, iclass 38, count 0 2006.224.08:13:09.19#ibcon#flushed, iclass 38, count 0 2006.224.08:13:09.19#ibcon#about to write, iclass 38, count 0 2006.224.08:13:09.19#ibcon#wrote, iclass 38, count 0 2006.224.08:13:09.19#ibcon#about to read 3, iclass 38, count 0 2006.224.08:13:09.23#ibcon#read 3, iclass 38, count 0 2006.224.08:13:09.23#ibcon#about to read 4, iclass 38, count 0 2006.224.08:13:09.23#ibcon#read 4, iclass 38, count 0 2006.224.08:13:09.23#ibcon#about to read 5, iclass 38, count 0 2006.224.08:13:09.23#ibcon#read 5, iclass 38, count 0 2006.224.08:13:09.23#ibcon#about to read 6, iclass 38, count 0 2006.224.08:13:09.23#ibcon#read 6, iclass 38, count 0 2006.224.08:13:09.23#ibcon#end of sib2, iclass 38, count 0 2006.224.08:13:09.23#ibcon#*after write, iclass 38, count 0 2006.224.08:13:09.23#ibcon#*before return 0, iclass 38, count 0 2006.224.08:13:09.23#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.224.08:13:09.23#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.224.08:13:09.23#ibcon#about to clear, iclass 38 cls_cnt 0 2006.224.08:13:09.23#ibcon#cleared, iclass 38 cls_cnt 0 2006.224.08:13:09.23$vc4f8/va=5,7 2006.224.08:13:09.23#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.224.08:13:09.23#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.224.08:13:09.23#ibcon#ireg 11 cls_cnt 2 2006.224.08:13:09.23#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.224.08:13:09.29#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.224.08:13:09.29#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.224.08:13:09.29#ibcon#enter wrdev, iclass 40, count 2 2006.224.08:13:09.29#ibcon#first serial, iclass 40, count 2 2006.224.08:13:09.29#ibcon#enter sib2, iclass 40, count 2 2006.224.08:13:09.29#ibcon#flushed, iclass 40, count 2 2006.224.08:13:09.29#ibcon#about to write, iclass 40, count 2 2006.224.08:13:09.29#ibcon#wrote, iclass 40, count 2 2006.224.08:13:09.29#ibcon#about to read 3, iclass 40, count 2 2006.224.08:13:09.31#ibcon#read 3, iclass 40, count 2 2006.224.08:13:09.31#ibcon#about to read 4, iclass 40, count 2 2006.224.08:13:09.31#ibcon#read 4, iclass 40, count 2 2006.224.08:13:09.31#ibcon#about to read 5, iclass 40, count 2 2006.224.08:13:09.31#ibcon#read 5, iclass 40, count 2 2006.224.08:13:09.31#ibcon#about to read 6, iclass 40, count 2 2006.224.08:13:09.31#ibcon#read 6, iclass 40, count 2 2006.224.08:13:09.31#ibcon#end of sib2, iclass 40, count 2 2006.224.08:13:09.31#ibcon#*mode == 0, iclass 40, count 2 2006.224.08:13:09.31#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.224.08:13:09.31#ibcon#[25=AT05-07\r\n] 2006.224.08:13:09.31#ibcon#*before write, iclass 40, count 2 2006.224.08:13:09.31#ibcon#enter sib2, iclass 40, count 2 2006.224.08:13:09.31#ibcon#flushed, iclass 40, count 2 2006.224.08:13:09.31#ibcon#about to write, iclass 40, count 2 2006.224.08:13:09.31#ibcon#wrote, iclass 40, count 2 2006.224.08:13:09.31#ibcon#about to read 3, iclass 40, count 2 2006.224.08:13:09.34#ibcon#read 3, iclass 40, count 2 2006.224.08:13:09.34#ibcon#about to read 4, iclass 40, count 2 2006.224.08:13:09.34#ibcon#read 4, iclass 40, count 2 2006.224.08:13:09.34#ibcon#about to read 5, iclass 40, count 2 2006.224.08:13:09.34#ibcon#read 5, iclass 40, count 2 2006.224.08:13:09.34#ibcon#about to read 6, iclass 40, count 2 2006.224.08:13:09.34#ibcon#read 6, iclass 40, count 2 2006.224.08:13:09.34#ibcon#end of sib2, iclass 40, count 2 2006.224.08:13:09.34#ibcon#*after write, iclass 40, count 2 2006.224.08:13:09.34#ibcon#*before return 0, iclass 40, count 2 2006.224.08:13:09.34#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.224.08:13:09.34#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.224.08:13:09.34#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.224.08:13:09.34#ibcon#ireg 7 cls_cnt 0 2006.224.08:13:09.34#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.224.08:13:09.46#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.224.08:13:09.46#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.224.08:13:09.46#ibcon#enter wrdev, iclass 40, count 0 2006.224.08:13:09.46#ibcon#first serial, iclass 40, count 0 2006.224.08:13:09.46#ibcon#enter sib2, iclass 40, count 0 2006.224.08:13:09.46#ibcon#flushed, iclass 40, count 0 2006.224.08:13:09.46#ibcon#about to write, iclass 40, count 0 2006.224.08:13:09.46#ibcon#wrote, iclass 40, count 0 2006.224.08:13:09.46#ibcon#about to read 3, iclass 40, count 0 2006.224.08:13:09.48#ibcon#read 3, iclass 40, count 0 2006.224.08:13:09.48#ibcon#about to read 4, iclass 40, count 0 2006.224.08:13:09.48#ibcon#read 4, iclass 40, count 0 2006.224.08:13:09.48#ibcon#about to read 5, iclass 40, count 0 2006.224.08:13:09.48#ibcon#read 5, iclass 40, count 0 2006.224.08:13:09.48#ibcon#about to read 6, iclass 40, count 0 2006.224.08:13:09.48#ibcon#read 6, iclass 40, count 0 2006.224.08:13:09.48#ibcon#end of sib2, iclass 40, count 0 2006.224.08:13:09.48#ibcon#*mode == 0, iclass 40, count 0 2006.224.08:13:09.48#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.224.08:13:09.48#ibcon#[25=USB\r\n] 2006.224.08:13:09.48#ibcon#*before write, iclass 40, count 0 2006.224.08:13:09.48#ibcon#enter sib2, iclass 40, count 0 2006.224.08:13:09.48#ibcon#flushed, iclass 40, count 0 2006.224.08:13:09.48#ibcon#about to write, iclass 40, count 0 2006.224.08:13:09.48#ibcon#wrote, iclass 40, count 0 2006.224.08:13:09.48#ibcon#about to read 3, iclass 40, count 0 2006.224.08:13:09.51#ibcon#read 3, iclass 40, count 0 2006.224.08:13:09.51#ibcon#about to read 4, iclass 40, count 0 2006.224.08:13:09.51#ibcon#read 4, iclass 40, count 0 2006.224.08:13:09.51#ibcon#about to read 5, iclass 40, count 0 2006.224.08:13:09.51#ibcon#read 5, iclass 40, count 0 2006.224.08:13:09.51#ibcon#about to read 6, iclass 40, count 0 2006.224.08:13:09.51#ibcon#read 6, iclass 40, count 0 2006.224.08:13:09.51#ibcon#end of sib2, iclass 40, count 0 2006.224.08:13:09.51#ibcon#*after write, iclass 40, count 0 2006.224.08:13:09.51#ibcon#*before return 0, iclass 40, count 0 2006.224.08:13:09.51#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.224.08:13:09.51#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.224.08:13:09.51#ibcon#about to clear, iclass 40 cls_cnt 0 2006.224.08:13:09.51#ibcon#cleared, iclass 40 cls_cnt 0 2006.224.08:13:09.51$vc4f8/valo=6,772.99 2006.224.08:13:09.51#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.224.08:13:09.51#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.224.08:13:09.51#ibcon#ireg 17 cls_cnt 0 2006.224.08:13:09.51#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.224.08:13:09.51#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.224.08:13:09.51#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.224.08:13:09.51#ibcon#enter wrdev, iclass 4, count 0 2006.224.08:13:09.51#ibcon#first serial, iclass 4, count 0 2006.224.08:13:09.51#ibcon#enter sib2, iclass 4, count 0 2006.224.08:13:09.51#ibcon#flushed, iclass 4, count 0 2006.224.08:13:09.51#ibcon#about to write, iclass 4, count 0 2006.224.08:13:09.51#ibcon#wrote, iclass 4, count 0 2006.224.08:13:09.51#ibcon#about to read 3, iclass 4, count 0 2006.224.08:13:09.53#ibcon#read 3, iclass 4, count 0 2006.224.08:13:09.53#ibcon#about to read 4, iclass 4, count 0 2006.224.08:13:09.53#ibcon#read 4, iclass 4, count 0 2006.224.08:13:09.53#ibcon#about to read 5, iclass 4, count 0 2006.224.08:13:09.53#ibcon#read 5, iclass 4, count 0 2006.224.08:13:09.53#ibcon#about to read 6, iclass 4, count 0 2006.224.08:13:09.53#ibcon#read 6, iclass 4, count 0 2006.224.08:13:09.53#ibcon#end of sib2, iclass 4, count 0 2006.224.08:13:09.53#ibcon#*mode == 0, iclass 4, count 0 2006.224.08:13:09.53#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.224.08:13:09.53#ibcon#[26=FRQ=06,772.99\r\n] 2006.224.08:13:09.53#ibcon#*before write, iclass 4, count 0 2006.224.08:13:09.53#ibcon#enter sib2, iclass 4, count 0 2006.224.08:13:09.53#ibcon#flushed, iclass 4, count 0 2006.224.08:13:09.53#ibcon#about to write, iclass 4, count 0 2006.224.08:13:09.53#ibcon#wrote, iclass 4, count 0 2006.224.08:13:09.53#ibcon#about to read 3, iclass 4, count 0 2006.224.08:13:09.57#ibcon#read 3, iclass 4, count 0 2006.224.08:13:09.57#ibcon#about to read 4, iclass 4, count 0 2006.224.08:13:09.57#ibcon#read 4, iclass 4, count 0 2006.224.08:13:09.57#ibcon#about to read 5, iclass 4, count 0 2006.224.08:13:09.57#ibcon#read 5, iclass 4, count 0 2006.224.08:13:09.57#ibcon#about to read 6, iclass 4, count 0 2006.224.08:13:09.57#ibcon#read 6, iclass 4, count 0 2006.224.08:13:09.57#ibcon#end of sib2, iclass 4, count 0 2006.224.08:13:09.57#ibcon#*after write, iclass 4, count 0 2006.224.08:13:09.57#ibcon#*before return 0, iclass 4, count 0 2006.224.08:13:09.57#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.224.08:13:09.57#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.224.08:13:09.57#ibcon#about to clear, iclass 4 cls_cnt 0 2006.224.08:13:09.57#ibcon#cleared, iclass 4 cls_cnt 0 2006.224.08:13:09.57$vc4f8/va=6,6 2006.224.08:13:09.57#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.224.08:13:09.57#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.224.08:13:09.57#ibcon#ireg 11 cls_cnt 2 2006.224.08:13:09.57#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.224.08:13:09.63#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.224.08:13:09.63#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.224.08:13:09.63#ibcon#enter wrdev, iclass 6, count 2 2006.224.08:13:09.63#ibcon#first serial, iclass 6, count 2 2006.224.08:13:09.63#ibcon#enter sib2, iclass 6, count 2 2006.224.08:13:09.63#ibcon#flushed, iclass 6, count 2 2006.224.08:13:09.63#ibcon#about to write, iclass 6, count 2 2006.224.08:13:09.63#ibcon#wrote, iclass 6, count 2 2006.224.08:13:09.63#ibcon#about to read 3, iclass 6, count 2 2006.224.08:13:09.65#ibcon#read 3, iclass 6, count 2 2006.224.08:13:09.65#ibcon#about to read 4, iclass 6, count 2 2006.224.08:13:09.65#ibcon#read 4, iclass 6, count 2 2006.224.08:13:09.65#ibcon#about to read 5, iclass 6, count 2 2006.224.08:13:09.65#ibcon#read 5, iclass 6, count 2 2006.224.08:13:09.65#ibcon#about to read 6, iclass 6, count 2 2006.224.08:13:09.65#ibcon#read 6, iclass 6, count 2 2006.224.08:13:09.65#ibcon#end of sib2, iclass 6, count 2 2006.224.08:13:09.65#ibcon#*mode == 0, iclass 6, count 2 2006.224.08:13:09.65#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.224.08:13:09.65#ibcon#[25=AT06-06\r\n] 2006.224.08:13:09.65#ibcon#*before write, iclass 6, count 2 2006.224.08:13:09.65#ibcon#enter sib2, iclass 6, count 2 2006.224.08:13:09.65#ibcon#flushed, iclass 6, count 2 2006.224.08:13:09.65#ibcon#about to write, iclass 6, count 2 2006.224.08:13:09.65#ibcon#wrote, iclass 6, count 2 2006.224.08:13:09.65#ibcon#about to read 3, iclass 6, count 2 2006.224.08:13:09.68#ibcon#read 3, iclass 6, count 2 2006.224.08:13:09.68#ibcon#about to read 4, iclass 6, count 2 2006.224.08:13:09.68#ibcon#read 4, iclass 6, count 2 2006.224.08:13:09.68#ibcon#about to read 5, iclass 6, count 2 2006.224.08:13:09.68#ibcon#read 5, iclass 6, count 2 2006.224.08:13:09.68#ibcon#about to read 6, iclass 6, count 2 2006.224.08:13:09.68#ibcon#read 6, iclass 6, count 2 2006.224.08:13:09.68#ibcon#end of sib2, iclass 6, count 2 2006.224.08:13:09.68#ibcon#*after write, iclass 6, count 2 2006.224.08:13:09.68#ibcon#*before return 0, iclass 6, count 2 2006.224.08:13:09.68#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.224.08:13:09.68#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.224.08:13:09.68#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.224.08:13:09.68#ibcon#ireg 7 cls_cnt 0 2006.224.08:13:09.68#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.224.08:13:09.80#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.224.08:13:09.80#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.224.08:13:09.80#ibcon#enter wrdev, iclass 6, count 0 2006.224.08:13:09.80#ibcon#first serial, iclass 6, count 0 2006.224.08:13:09.80#ibcon#enter sib2, iclass 6, count 0 2006.224.08:13:09.80#ibcon#flushed, iclass 6, count 0 2006.224.08:13:09.80#ibcon#about to write, iclass 6, count 0 2006.224.08:13:09.80#ibcon#wrote, iclass 6, count 0 2006.224.08:13:09.80#ibcon#about to read 3, iclass 6, count 0 2006.224.08:13:09.82#ibcon#read 3, iclass 6, count 0 2006.224.08:13:09.82#ibcon#about to read 4, iclass 6, count 0 2006.224.08:13:09.82#ibcon#read 4, iclass 6, count 0 2006.224.08:13:09.82#ibcon#about to read 5, iclass 6, count 0 2006.224.08:13:09.82#ibcon#read 5, iclass 6, count 0 2006.224.08:13:09.82#ibcon#about to read 6, iclass 6, count 0 2006.224.08:13:09.82#ibcon#read 6, iclass 6, count 0 2006.224.08:13:09.82#ibcon#end of sib2, iclass 6, count 0 2006.224.08:13:09.82#ibcon#*mode == 0, iclass 6, count 0 2006.224.08:13:09.82#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.224.08:13:09.82#ibcon#[25=USB\r\n] 2006.224.08:13:09.82#ibcon#*before write, iclass 6, count 0 2006.224.08:13:09.82#ibcon#enter sib2, iclass 6, count 0 2006.224.08:13:09.82#ibcon#flushed, iclass 6, count 0 2006.224.08:13:09.82#ibcon#about to write, iclass 6, count 0 2006.224.08:13:09.82#ibcon#wrote, iclass 6, count 0 2006.224.08:13:09.82#ibcon#about to read 3, iclass 6, count 0 2006.224.08:13:09.85#ibcon#read 3, iclass 6, count 0 2006.224.08:13:09.85#ibcon#about to read 4, iclass 6, count 0 2006.224.08:13:09.85#ibcon#read 4, iclass 6, count 0 2006.224.08:13:09.85#ibcon#about to read 5, iclass 6, count 0 2006.224.08:13:09.85#ibcon#read 5, iclass 6, count 0 2006.224.08:13:09.85#ibcon#about to read 6, iclass 6, count 0 2006.224.08:13:09.85#ibcon#read 6, iclass 6, count 0 2006.224.08:13:09.85#ibcon#end of sib2, iclass 6, count 0 2006.224.08:13:09.85#ibcon#*after write, iclass 6, count 0 2006.224.08:13:09.85#ibcon#*before return 0, iclass 6, count 0 2006.224.08:13:09.85#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.224.08:13:09.85#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.224.08:13:09.85#ibcon#about to clear, iclass 6 cls_cnt 0 2006.224.08:13:09.85#ibcon#cleared, iclass 6 cls_cnt 0 2006.224.08:13:09.85$vc4f8/valo=7,832.99 2006.224.08:13:09.85#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.224.08:13:09.85#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.224.08:13:09.85#ibcon#ireg 17 cls_cnt 0 2006.224.08:13:09.85#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.224.08:13:09.85#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.224.08:13:09.85#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.224.08:13:09.85#ibcon#enter wrdev, iclass 10, count 0 2006.224.08:13:09.85#ibcon#first serial, iclass 10, count 0 2006.224.08:13:09.85#ibcon#enter sib2, iclass 10, count 0 2006.224.08:13:09.85#ibcon#flushed, iclass 10, count 0 2006.224.08:13:09.85#ibcon#about to write, iclass 10, count 0 2006.224.08:13:09.85#ibcon#wrote, iclass 10, count 0 2006.224.08:13:09.85#ibcon#about to read 3, iclass 10, count 0 2006.224.08:13:09.87#ibcon#read 3, iclass 10, count 0 2006.224.08:13:09.87#ibcon#about to read 4, iclass 10, count 0 2006.224.08:13:09.87#ibcon#read 4, iclass 10, count 0 2006.224.08:13:09.87#ibcon#about to read 5, iclass 10, count 0 2006.224.08:13:09.87#ibcon#read 5, iclass 10, count 0 2006.224.08:13:09.87#ibcon#about to read 6, iclass 10, count 0 2006.224.08:13:09.87#ibcon#read 6, iclass 10, count 0 2006.224.08:13:09.87#ibcon#end of sib2, iclass 10, count 0 2006.224.08:13:09.87#ibcon#*mode == 0, iclass 10, count 0 2006.224.08:13:09.87#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.224.08:13:09.87#ibcon#[26=FRQ=07,832.99\r\n] 2006.224.08:13:09.87#ibcon#*before write, iclass 10, count 0 2006.224.08:13:09.87#ibcon#enter sib2, iclass 10, count 0 2006.224.08:13:09.87#ibcon#flushed, iclass 10, count 0 2006.224.08:13:09.87#ibcon#about to write, iclass 10, count 0 2006.224.08:13:09.87#ibcon#wrote, iclass 10, count 0 2006.224.08:13:09.87#ibcon#about to read 3, iclass 10, count 0 2006.224.08:13:09.91#ibcon#read 3, iclass 10, count 0 2006.224.08:13:09.91#ibcon#about to read 4, iclass 10, count 0 2006.224.08:13:09.91#ibcon#read 4, iclass 10, count 0 2006.224.08:13:09.91#ibcon#about to read 5, iclass 10, count 0 2006.224.08:13:09.91#ibcon#read 5, iclass 10, count 0 2006.224.08:13:09.91#ibcon#about to read 6, iclass 10, count 0 2006.224.08:13:09.91#ibcon#read 6, iclass 10, count 0 2006.224.08:13:09.91#ibcon#end of sib2, iclass 10, count 0 2006.224.08:13:09.91#ibcon#*after write, iclass 10, count 0 2006.224.08:13:09.91#ibcon#*before return 0, iclass 10, count 0 2006.224.08:13:09.91#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.224.08:13:09.91#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.224.08:13:09.91#ibcon#about to clear, iclass 10 cls_cnt 0 2006.224.08:13:09.91#ibcon#cleared, iclass 10 cls_cnt 0 2006.224.08:13:09.91$vc4f8/va=7,6 2006.224.08:13:09.91#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.224.08:13:09.91#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.224.08:13:09.91#ibcon#ireg 11 cls_cnt 2 2006.224.08:13:09.91#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.224.08:13:09.97#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.224.08:13:09.97#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.224.08:13:09.97#ibcon#enter wrdev, iclass 12, count 2 2006.224.08:13:09.97#ibcon#first serial, iclass 12, count 2 2006.224.08:13:09.97#ibcon#enter sib2, iclass 12, count 2 2006.224.08:13:09.97#ibcon#flushed, iclass 12, count 2 2006.224.08:13:09.97#ibcon#about to write, iclass 12, count 2 2006.224.08:13:09.97#ibcon#wrote, iclass 12, count 2 2006.224.08:13:09.97#ibcon#about to read 3, iclass 12, count 2 2006.224.08:13:09.99#ibcon#read 3, iclass 12, count 2 2006.224.08:13:09.99#ibcon#about to read 4, iclass 12, count 2 2006.224.08:13:09.99#ibcon#read 4, iclass 12, count 2 2006.224.08:13:09.99#ibcon#about to read 5, iclass 12, count 2 2006.224.08:13:09.99#ibcon#read 5, iclass 12, count 2 2006.224.08:13:09.99#ibcon#about to read 6, iclass 12, count 2 2006.224.08:13:09.99#ibcon#read 6, iclass 12, count 2 2006.224.08:13:09.99#ibcon#end of sib2, iclass 12, count 2 2006.224.08:13:09.99#ibcon#*mode == 0, iclass 12, count 2 2006.224.08:13:09.99#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.224.08:13:09.99#ibcon#[25=AT07-06\r\n] 2006.224.08:13:09.99#ibcon#*before write, iclass 12, count 2 2006.224.08:13:09.99#ibcon#enter sib2, iclass 12, count 2 2006.224.08:13:09.99#ibcon#flushed, iclass 12, count 2 2006.224.08:13:09.99#ibcon#about to write, iclass 12, count 2 2006.224.08:13:09.99#ibcon#wrote, iclass 12, count 2 2006.224.08:13:09.99#ibcon#about to read 3, iclass 12, count 2 2006.224.08:13:10.02#ibcon#read 3, iclass 12, count 2 2006.224.08:13:10.02#ibcon#about to read 4, iclass 12, count 2 2006.224.08:13:10.02#ibcon#read 4, iclass 12, count 2 2006.224.08:13:10.02#ibcon#about to read 5, iclass 12, count 2 2006.224.08:13:10.02#ibcon#read 5, iclass 12, count 2 2006.224.08:13:10.02#ibcon#about to read 6, iclass 12, count 2 2006.224.08:13:10.02#ibcon#read 6, iclass 12, count 2 2006.224.08:13:10.02#ibcon#end of sib2, iclass 12, count 2 2006.224.08:13:10.02#ibcon#*after write, iclass 12, count 2 2006.224.08:13:10.02#ibcon#*before return 0, iclass 12, count 2 2006.224.08:13:10.02#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.224.08:13:10.02#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.224.08:13:10.02#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.224.08:13:10.02#ibcon#ireg 7 cls_cnt 0 2006.224.08:13:10.02#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.224.08:13:10.14#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.224.08:13:10.14#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.224.08:13:10.14#ibcon#enter wrdev, iclass 12, count 0 2006.224.08:13:10.14#ibcon#first serial, iclass 12, count 0 2006.224.08:13:10.14#ibcon#enter sib2, iclass 12, count 0 2006.224.08:13:10.14#ibcon#flushed, iclass 12, count 0 2006.224.08:13:10.14#ibcon#about to write, iclass 12, count 0 2006.224.08:13:10.14#ibcon#wrote, iclass 12, count 0 2006.224.08:13:10.14#ibcon#about to read 3, iclass 12, count 0 2006.224.08:13:10.16#ibcon#read 3, iclass 12, count 0 2006.224.08:13:10.16#ibcon#about to read 4, iclass 12, count 0 2006.224.08:13:10.16#ibcon#read 4, iclass 12, count 0 2006.224.08:13:10.16#ibcon#about to read 5, iclass 12, count 0 2006.224.08:13:10.16#ibcon#read 5, iclass 12, count 0 2006.224.08:13:10.16#ibcon#about to read 6, iclass 12, count 0 2006.224.08:13:10.16#ibcon#read 6, iclass 12, count 0 2006.224.08:13:10.16#ibcon#end of sib2, iclass 12, count 0 2006.224.08:13:10.16#ibcon#*mode == 0, iclass 12, count 0 2006.224.08:13:10.16#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.224.08:13:10.16#ibcon#[25=USB\r\n] 2006.224.08:13:10.16#ibcon#*before write, iclass 12, count 0 2006.224.08:13:10.16#ibcon#enter sib2, iclass 12, count 0 2006.224.08:13:10.16#ibcon#flushed, iclass 12, count 0 2006.224.08:13:10.16#ibcon#about to write, iclass 12, count 0 2006.224.08:13:10.16#ibcon#wrote, iclass 12, count 0 2006.224.08:13:10.16#ibcon#about to read 3, iclass 12, count 0 2006.224.08:13:10.19#ibcon#read 3, iclass 12, count 0 2006.224.08:13:10.19#ibcon#about to read 4, iclass 12, count 0 2006.224.08:13:10.19#ibcon#read 4, iclass 12, count 0 2006.224.08:13:10.19#ibcon#about to read 5, iclass 12, count 0 2006.224.08:13:10.19#ibcon#read 5, iclass 12, count 0 2006.224.08:13:10.19#ibcon#about to read 6, iclass 12, count 0 2006.224.08:13:10.19#ibcon#read 6, iclass 12, count 0 2006.224.08:13:10.19#ibcon#end of sib2, iclass 12, count 0 2006.224.08:13:10.19#ibcon#*after write, iclass 12, count 0 2006.224.08:13:10.19#ibcon#*before return 0, iclass 12, count 0 2006.224.08:13:10.19#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.224.08:13:10.19#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.224.08:13:10.19#ibcon#about to clear, iclass 12 cls_cnt 0 2006.224.08:13:10.19#ibcon#cleared, iclass 12 cls_cnt 0 2006.224.08:13:10.19$vc4f8/valo=8,852.99 2006.224.08:13:10.19#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.224.08:13:10.19#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.224.08:13:10.19#ibcon#ireg 17 cls_cnt 0 2006.224.08:13:10.19#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.224.08:13:10.19#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.224.08:13:10.19#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.224.08:13:10.19#ibcon#enter wrdev, iclass 14, count 0 2006.224.08:13:10.19#ibcon#first serial, iclass 14, count 0 2006.224.08:13:10.19#ibcon#enter sib2, iclass 14, count 0 2006.224.08:13:10.19#ibcon#flushed, iclass 14, count 0 2006.224.08:13:10.19#ibcon#about to write, iclass 14, count 0 2006.224.08:13:10.19#ibcon#wrote, iclass 14, count 0 2006.224.08:13:10.19#ibcon#about to read 3, iclass 14, count 0 2006.224.08:13:10.21#ibcon#read 3, iclass 14, count 0 2006.224.08:13:10.21#ibcon#about to read 4, iclass 14, count 0 2006.224.08:13:10.21#ibcon#read 4, iclass 14, count 0 2006.224.08:13:10.21#ibcon#about to read 5, iclass 14, count 0 2006.224.08:13:10.21#ibcon#read 5, iclass 14, count 0 2006.224.08:13:10.21#ibcon#about to read 6, iclass 14, count 0 2006.224.08:13:10.21#ibcon#read 6, iclass 14, count 0 2006.224.08:13:10.21#ibcon#end of sib2, iclass 14, count 0 2006.224.08:13:10.21#ibcon#*mode == 0, iclass 14, count 0 2006.224.08:13:10.21#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.224.08:13:10.21#ibcon#[26=FRQ=08,852.99\r\n] 2006.224.08:13:10.21#ibcon#*before write, iclass 14, count 0 2006.224.08:13:10.21#ibcon#enter sib2, iclass 14, count 0 2006.224.08:13:10.21#ibcon#flushed, iclass 14, count 0 2006.224.08:13:10.21#ibcon#about to write, iclass 14, count 0 2006.224.08:13:10.21#ibcon#wrote, iclass 14, count 0 2006.224.08:13:10.21#ibcon#about to read 3, iclass 14, count 0 2006.224.08:13:10.25#ibcon#read 3, iclass 14, count 0 2006.224.08:13:10.25#ibcon#about to read 4, iclass 14, count 0 2006.224.08:13:10.25#ibcon#read 4, iclass 14, count 0 2006.224.08:13:10.25#ibcon#about to read 5, iclass 14, count 0 2006.224.08:13:10.25#ibcon#read 5, iclass 14, count 0 2006.224.08:13:10.25#ibcon#about to read 6, iclass 14, count 0 2006.224.08:13:10.25#ibcon#read 6, iclass 14, count 0 2006.224.08:13:10.25#ibcon#end of sib2, iclass 14, count 0 2006.224.08:13:10.25#ibcon#*after write, iclass 14, count 0 2006.224.08:13:10.25#ibcon#*before return 0, iclass 14, count 0 2006.224.08:13:10.25#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.224.08:13:10.25#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.224.08:13:10.25#ibcon#about to clear, iclass 14 cls_cnt 0 2006.224.08:13:10.25#ibcon#cleared, iclass 14 cls_cnt 0 2006.224.08:13:10.25$vc4f8/va=8,7 2006.224.08:13:10.25#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.224.08:13:10.25#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.224.08:13:10.25#ibcon#ireg 11 cls_cnt 2 2006.224.08:13:10.25#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.224.08:13:10.31#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.224.08:13:10.31#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.224.08:13:10.31#ibcon#enter wrdev, iclass 16, count 2 2006.224.08:13:10.31#ibcon#first serial, iclass 16, count 2 2006.224.08:13:10.31#ibcon#enter sib2, iclass 16, count 2 2006.224.08:13:10.31#ibcon#flushed, iclass 16, count 2 2006.224.08:13:10.31#ibcon#about to write, iclass 16, count 2 2006.224.08:13:10.31#ibcon#wrote, iclass 16, count 2 2006.224.08:13:10.31#ibcon#about to read 3, iclass 16, count 2 2006.224.08:13:10.33#ibcon#read 3, iclass 16, count 2 2006.224.08:13:10.33#ibcon#about to read 4, iclass 16, count 2 2006.224.08:13:10.33#ibcon#read 4, iclass 16, count 2 2006.224.08:13:10.33#ibcon#about to read 5, iclass 16, count 2 2006.224.08:13:10.33#ibcon#read 5, iclass 16, count 2 2006.224.08:13:10.33#ibcon#about to read 6, iclass 16, count 2 2006.224.08:13:10.33#ibcon#read 6, iclass 16, count 2 2006.224.08:13:10.33#ibcon#end of sib2, iclass 16, count 2 2006.224.08:13:10.33#ibcon#*mode == 0, iclass 16, count 2 2006.224.08:13:10.33#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.224.08:13:10.33#ibcon#[25=AT08-07\r\n] 2006.224.08:13:10.33#ibcon#*before write, iclass 16, count 2 2006.224.08:13:10.33#ibcon#enter sib2, iclass 16, count 2 2006.224.08:13:10.33#ibcon#flushed, iclass 16, count 2 2006.224.08:13:10.33#ibcon#about to write, iclass 16, count 2 2006.224.08:13:10.33#ibcon#wrote, iclass 16, count 2 2006.224.08:13:10.33#ibcon#about to read 3, iclass 16, count 2 2006.224.08:13:10.36#ibcon#read 3, iclass 16, count 2 2006.224.08:13:10.36#ibcon#about to read 4, iclass 16, count 2 2006.224.08:13:10.36#ibcon#read 4, iclass 16, count 2 2006.224.08:13:10.36#ibcon#about to read 5, iclass 16, count 2 2006.224.08:13:10.36#ibcon#read 5, iclass 16, count 2 2006.224.08:13:10.36#ibcon#about to read 6, iclass 16, count 2 2006.224.08:13:10.36#ibcon#read 6, iclass 16, count 2 2006.224.08:13:10.36#ibcon#end of sib2, iclass 16, count 2 2006.224.08:13:10.36#ibcon#*after write, iclass 16, count 2 2006.224.08:13:10.36#ibcon#*before return 0, iclass 16, count 2 2006.224.08:13:10.36#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.224.08:13:10.36#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.224.08:13:10.36#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.224.08:13:10.36#ibcon#ireg 7 cls_cnt 0 2006.224.08:13:10.36#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.224.08:13:10.48#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.224.08:13:10.48#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.224.08:13:10.48#ibcon#enter wrdev, iclass 16, count 0 2006.224.08:13:10.48#ibcon#first serial, iclass 16, count 0 2006.224.08:13:10.48#ibcon#enter sib2, iclass 16, count 0 2006.224.08:13:10.48#ibcon#flushed, iclass 16, count 0 2006.224.08:13:10.48#ibcon#about to write, iclass 16, count 0 2006.224.08:13:10.48#ibcon#wrote, iclass 16, count 0 2006.224.08:13:10.48#ibcon#about to read 3, iclass 16, count 0 2006.224.08:13:10.50#ibcon#read 3, iclass 16, count 0 2006.224.08:13:10.50#ibcon#about to read 4, iclass 16, count 0 2006.224.08:13:10.50#ibcon#read 4, iclass 16, count 0 2006.224.08:13:10.50#ibcon#about to read 5, iclass 16, count 0 2006.224.08:13:10.50#ibcon#read 5, iclass 16, count 0 2006.224.08:13:10.50#ibcon#about to read 6, iclass 16, count 0 2006.224.08:13:10.50#ibcon#read 6, iclass 16, count 0 2006.224.08:13:10.50#ibcon#end of sib2, iclass 16, count 0 2006.224.08:13:10.50#ibcon#*mode == 0, iclass 16, count 0 2006.224.08:13:10.50#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.224.08:13:10.50#ibcon#[25=USB\r\n] 2006.224.08:13:10.50#ibcon#*before write, iclass 16, count 0 2006.224.08:13:10.50#ibcon#enter sib2, iclass 16, count 0 2006.224.08:13:10.50#ibcon#flushed, iclass 16, count 0 2006.224.08:13:10.50#ibcon#about to write, iclass 16, count 0 2006.224.08:13:10.50#ibcon#wrote, iclass 16, count 0 2006.224.08:13:10.50#ibcon#about to read 3, iclass 16, count 0 2006.224.08:13:10.53#ibcon#read 3, iclass 16, count 0 2006.224.08:13:10.53#ibcon#about to read 4, iclass 16, count 0 2006.224.08:13:10.53#ibcon#read 4, iclass 16, count 0 2006.224.08:13:10.53#ibcon#about to read 5, iclass 16, count 0 2006.224.08:13:10.53#ibcon#read 5, iclass 16, count 0 2006.224.08:13:10.53#ibcon#about to read 6, iclass 16, count 0 2006.224.08:13:10.53#ibcon#read 6, iclass 16, count 0 2006.224.08:13:10.53#ibcon#end of sib2, iclass 16, count 0 2006.224.08:13:10.53#ibcon#*after write, iclass 16, count 0 2006.224.08:13:10.53#ibcon#*before return 0, iclass 16, count 0 2006.224.08:13:10.53#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.224.08:13:10.53#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.224.08:13:10.53#ibcon#about to clear, iclass 16 cls_cnt 0 2006.224.08:13:10.53#ibcon#cleared, iclass 16 cls_cnt 0 2006.224.08:13:10.53$vc4f8/vblo=1,632.99 2006.224.08:13:10.53#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.224.08:13:10.53#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.224.08:13:10.53#ibcon#ireg 17 cls_cnt 0 2006.224.08:13:10.53#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.224.08:13:10.53#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.224.08:13:10.53#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.224.08:13:10.53#ibcon#enter wrdev, iclass 18, count 0 2006.224.08:13:10.53#ibcon#first serial, iclass 18, count 0 2006.224.08:13:10.53#ibcon#enter sib2, iclass 18, count 0 2006.224.08:13:10.53#ibcon#flushed, iclass 18, count 0 2006.224.08:13:10.53#ibcon#about to write, iclass 18, count 0 2006.224.08:13:10.53#ibcon#wrote, iclass 18, count 0 2006.224.08:13:10.53#ibcon#about to read 3, iclass 18, count 0 2006.224.08:13:10.55#ibcon#read 3, iclass 18, count 0 2006.224.08:13:10.55#ibcon#about to read 4, iclass 18, count 0 2006.224.08:13:10.55#ibcon#read 4, iclass 18, count 0 2006.224.08:13:10.55#ibcon#about to read 5, iclass 18, count 0 2006.224.08:13:10.55#ibcon#read 5, iclass 18, count 0 2006.224.08:13:10.55#ibcon#about to read 6, iclass 18, count 0 2006.224.08:13:10.55#ibcon#read 6, iclass 18, count 0 2006.224.08:13:10.55#ibcon#end of sib2, iclass 18, count 0 2006.224.08:13:10.55#ibcon#*mode == 0, iclass 18, count 0 2006.224.08:13:10.55#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.224.08:13:10.55#ibcon#[28=FRQ=01,632.99\r\n] 2006.224.08:13:10.55#ibcon#*before write, iclass 18, count 0 2006.224.08:13:10.55#ibcon#enter sib2, iclass 18, count 0 2006.224.08:13:10.55#ibcon#flushed, iclass 18, count 0 2006.224.08:13:10.55#ibcon#about to write, iclass 18, count 0 2006.224.08:13:10.55#ibcon#wrote, iclass 18, count 0 2006.224.08:13:10.55#ibcon#about to read 3, iclass 18, count 0 2006.224.08:13:10.60#ibcon#read 3, iclass 18, count 0 2006.224.08:13:10.60#ibcon#about to read 4, iclass 18, count 0 2006.224.08:13:10.60#ibcon#read 4, iclass 18, count 0 2006.224.08:13:10.60#ibcon#about to read 5, iclass 18, count 0 2006.224.08:13:10.60#ibcon#read 5, iclass 18, count 0 2006.224.08:13:10.60#ibcon#about to read 6, iclass 18, count 0 2006.224.08:13:10.60#ibcon#read 6, iclass 18, count 0 2006.224.08:13:10.60#ibcon#end of sib2, iclass 18, count 0 2006.224.08:13:10.60#ibcon#*after write, iclass 18, count 0 2006.224.08:13:10.60#ibcon#*before return 0, iclass 18, count 0 2006.224.08:13:10.60#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.224.08:13:10.60#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.224.08:13:10.60#ibcon#about to clear, iclass 18 cls_cnt 0 2006.224.08:13:10.60#ibcon#cleared, iclass 18 cls_cnt 0 2006.224.08:13:10.60$vc4f8/vb=1,4 2006.224.08:13:10.60#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.224.08:13:10.60#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.224.08:13:10.60#ibcon#ireg 11 cls_cnt 2 2006.224.08:13:10.60#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.224.08:13:10.60#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.224.08:13:10.60#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.224.08:13:10.60#ibcon#enter wrdev, iclass 20, count 2 2006.224.08:13:10.60#ibcon#first serial, iclass 20, count 2 2006.224.08:13:10.60#ibcon#enter sib2, iclass 20, count 2 2006.224.08:13:10.60#ibcon#flushed, iclass 20, count 2 2006.224.08:13:10.60#ibcon#about to write, iclass 20, count 2 2006.224.08:13:10.60#ibcon#wrote, iclass 20, count 2 2006.224.08:13:10.60#ibcon#about to read 3, iclass 20, count 2 2006.224.08:13:10.62#ibcon#read 3, iclass 20, count 2 2006.224.08:13:10.62#ibcon#about to read 4, iclass 20, count 2 2006.224.08:13:10.62#ibcon#read 4, iclass 20, count 2 2006.224.08:13:10.62#ibcon#about to read 5, iclass 20, count 2 2006.224.08:13:10.62#ibcon#read 5, iclass 20, count 2 2006.224.08:13:10.62#ibcon#about to read 6, iclass 20, count 2 2006.224.08:13:10.62#ibcon#read 6, iclass 20, count 2 2006.224.08:13:10.62#ibcon#end of sib2, iclass 20, count 2 2006.224.08:13:10.62#ibcon#*mode == 0, iclass 20, count 2 2006.224.08:13:10.62#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.224.08:13:10.62#ibcon#[27=AT01-04\r\n] 2006.224.08:13:10.62#ibcon#*before write, iclass 20, count 2 2006.224.08:13:10.62#ibcon#enter sib2, iclass 20, count 2 2006.224.08:13:10.62#ibcon#flushed, iclass 20, count 2 2006.224.08:13:10.62#ibcon#about to write, iclass 20, count 2 2006.224.08:13:10.62#ibcon#wrote, iclass 20, count 2 2006.224.08:13:10.62#ibcon#about to read 3, iclass 20, count 2 2006.224.08:13:10.65#ibcon#read 3, iclass 20, count 2 2006.224.08:13:10.65#ibcon#about to read 4, iclass 20, count 2 2006.224.08:13:10.65#ibcon#read 4, iclass 20, count 2 2006.224.08:13:10.65#ibcon#about to read 5, iclass 20, count 2 2006.224.08:13:10.65#ibcon#read 5, iclass 20, count 2 2006.224.08:13:10.65#ibcon#about to read 6, iclass 20, count 2 2006.224.08:13:10.65#ibcon#read 6, iclass 20, count 2 2006.224.08:13:10.65#ibcon#end of sib2, iclass 20, count 2 2006.224.08:13:10.65#ibcon#*after write, iclass 20, count 2 2006.224.08:13:10.65#ibcon#*before return 0, iclass 20, count 2 2006.224.08:13:10.65#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.224.08:13:10.65#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.224.08:13:10.65#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.224.08:13:10.65#ibcon#ireg 7 cls_cnt 0 2006.224.08:13:10.65#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.224.08:13:10.77#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.224.08:13:10.77#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.224.08:13:10.77#ibcon#enter wrdev, iclass 20, count 0 2006.224.08:13:10.77#ibcon#first serial, iclass 20, count 0 2006.224.08:13:10.77#ibcon#enter sib2, iclass 20, count 0 2006.224.08:13:10.77#ibcon#flushed, iclass 20, count 0 2006.224.08:13:10.77#ibcon#about to write, iclass 20, count 0 2006.224.08:13:10.77#ibcon#wrote, iclass 20, count 0 2006.224.08:13:10.77#ibcon#about to read 3, iclass 20, count 0 2006.224.08:13:10.79#ibcon#read 3, iclass 20, count 0 2006.224.08:13:10.79#ibcon#about to read 4, iclass 20, count 0 2006.224.08:13:10.79#ibcon#read 4, iclass 20, count 0 2006.224.08:13:10.79#ibcon#about to read 5, iclass 20, count 0 2006.224.08:13:10.79#ibcon#read 5, iclass 20, count 0 2006.224.08:13:10.79#ibcon#about to read 6, iclass 20, count 0 2006.224.08:13:10.79#ibcon#read 6, iclass 20, count 0 2006.224.08:13:10.79#ibcon#end of sib2, iclass 20, count 0 2006.224.08:13:10.79#ibcon#*mode == 0, iclass 20, count 0 2006.224.08:13:10.79#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.224.08:13:10.79#ibcon#[27=USB\r\n] 2006.224.08:13:10.79#ibcon#*before write, iclass 20, count 0 2006.224.08:13:10.79#ibcon#enter sib2, iclass 20, count 0 2006.224.08:13:10.79#ibcon#flushed, iclass 20, count 0 2006.224.08:13:10.79#ibcon#about to write, iclass 20, count 0 2006.224.08:13:10.79#ibcon#wrote, iclass 20, count 0 2006.224.08:13:10.79#ibcon#about to read 3, iclass 20, count 0 2006.224.08:13:10.82#ibcon#read 3, iclass 20, count 0 2006.224.08:13:10.82#ibcon#about to read 4, iclass 20, count 0 2006.224.08:13:10.82#ibcon#read 4, iclass 20, count 0 2006.224.08:13:10.82#ibcon#about to read 5, iclass 20, count 0 2006.224.08:13:10.82#ibcon#read 5, iclass 20, count 0 2006.224.08:13:10.82#ibcon#about to read 6, iclass 20, count 0 2006.224.08:13:10.82#ibcon#read 6, iclass 20, count 0 2006.224.08:13:10.82#ibcon#end of sib2, iclass 20, count 0 2006.224.08:13:10.82#ibcon#*after write, iclass 20, count 0 2006.224.08:13:10.82#ibcon#*before return 0, iclass 20, count 0 2006.224.08:13:10.82#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.224.08:13:10.82#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.224.08:13:10.82#ibcon#about to clear, iclass 20 cls_cnt 0 2006.224.08:13:10.82#ibcon#cleared, iclass 20 cls_cnt 0 2006.224.08:13:10.82$vc4f8/vblo=2,640.99 2006.224.08:13:10.82#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.224.08:13:10.82#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.224.08:13:10.82#ibcon#ireg 17 cls_cnt 0 2006.224.08:13:10.82#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.224.08:13:10.82#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.224.08:13:10.82#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.224.08:13:10.82#ibcon#enter wrdev, iclass 22, count 0 2006.224.08:13:10.82#ibcon#first serial, iclass 22, count 0 2006.224.08:13:10.82#ibcon#enter sib2, iclass 22, count 0 2006.224.08:13:10.82#ibcon#flushed, iclass 22, count 0 2006.224.08:13:10.82#ibcon#about to write, iclass 22, count 0 2006.224.08:13:10.82#ibcon#wrote, iclass 22, count 0 2006.224.08:13:10.82#ibcon#about to read 3, iclass 22, count 0 2006.224.08:13:10.84#ibcon#read 3, iclass 22, count 0 2006.224.08:13:10.84#ibcon#about to read 4, iclass 22, count 0 2006.224.08:13:10.84#ibcon#read 4, iclass 22, count 0 2006.224.08:13:10.84#ibcon#about to read 5, iclass 22, count 0 2006.224.08:13:10.84#ibcon#read 5, iclass 22, count 0 2006.224.08:13:10.84#ibcon#about to read 6, iclass 22, count 0 2006.224.08:13:10.84#ibcon#read 6, iclass 22, count 0 2006.224.08:13:10.84#ibcon#end of sib2, iclass 22, count 0 2006.224.08:13:10.84#ibcon#*mode == 0, iclass 22, count 0 2006.224.08:13:10.84#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.224.08:13:10.84#ibcon#[28=FRQ=02,640.99\r\n] 2006.224.08:13:10.84#ibcon#*before write, iclass 22, count 0 2006.224.08:13:10.84#ibcon#enter sib2, iclass 22, count 0 2006.224.08:13:10.84#ibcon#flushed, iclass 22, count 0 2006.224.08:13:10.84#ibcon#about to write, iclass 22, count 0 2006.224.08:13:10.84#ibcon#wrote, iclass 22, count 0 2006.224.08:13:10.84#ibcon#about to read 3, iclass 22, count 0 2006.224.08:13:10.88#ibcon#read 3, iclass 22, count 0 2006.224.08:13:10.88#ibcon#about to read 4, iclass 22, count 0 2006.224.08:13:10.88#ibcon#read 4, iclass 22, count 0 2006.224.08:13:10.88#ibcon#about to read 5, iclass 22, count 0 2006.224.08:13:10.88#ibcon#read 5, iclass 22, count 0 2006.224.08:13:10.88#ibcon#about to read 6, iclass 22, count 0 2006.224.08:13:10.88#ibcon#read 6, iclass 22, count 0 2006.224.08:13:10.88#ibcon#end of sib2, iclass 22, count 0 2006.224.08:13:10.88#ibcon#*after write, iclass 22, count 0 2006.224.08:13:10.88#ibcon#*before return 0, iclass 22, count 0 2006.224.08:13:10.88#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.224.08:13:10.88#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.224.08:13:10.88#ibcon#about to clear, iclass 22 cls_cnt 0 2006.224.08:13:10.88#ibcon#cleared, iclass 22 cls_cnt 0 2006.224.08:13:10.88$vc4f8/vb=2,4 2006.224.08:13:10.88#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.224.08:13:10.88#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.224.08:13:10.88#ibcon#ireg 11 cls_cnt 2 2006.224.08:13:10.88#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.224.08:13:10.94#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.224.08:13:10.94#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.224.08:13:10.94#ibcon#enter wrdev, iclass 24, count 2 2006.224.08:13:10.94#ibcon#first serial, iclass 24, count 2 2006.224.08:13:10.94#ibcon#enter sib2, iclass 24, count 2 2006.224.08:13:10.94#ibcon#flushed, iclass 24, count 2 2006.224.08:13:10.94#ibcon#about to write, iclass 24, count 2 2006.224.08:13:10.94#ibcon#wrote, iclass 24, count 2 2006.224.08:13:10.94#ibcon#about to read 3, iclass 24, count 2 2006.224.08:13:10.96#ibcon#read 3, iclass 24, count 2 2006.224.08:13:10.96#ibcon#about to read 4, iclass 24, count 2 2006.224.08:13:10.96#ibcon#read 4, iclass 24, count 2 2006.224.08:13:10.96#ibcon#about to read 5, iclass 24, count 2 2006.224.08:13:10.96#ibcon#read 5, iclass 24, count 2 2006.224.08:13:10.96#ibcon#about to read 6, iclass 24, count 2 2006.224.08:13:10.96#ibcon#read 6, iclass 24, count 2 2006.224.08:13:10.96#ibcon#end of sib2, iclass 24, count 2 2006.224.08:13:10.96#ibcon#*mode == 0, iclass 24, count 2 2006.224.08:13:10.96#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.224.08:13:10.96#ibcon#[27=AT02-04\r\n] 2006.224.08:13:10.96#ibcon#*before write, iclass 24, count 2 2006.224.08:13:10.96#ibcon#enter sib2, iclass 24, count 2 2006.224.08:13:10.96#ibcon#flushed, iclass 24, count 2 2006.224.08:13:10.96#ibcon#about to write, iclass 24, count 2 2006.224.08:13:10.96#ibcon#wrote, iclass 24, count 2 2006.224.08:13:10.96#ibcon#about to read 3, iclass 24, count 2 2006.224.08:13:10.99#ibcon#read 3, iclass 24, count 2 2006.224.08:13:10.99#ibcon#about to read 4, iclass 24, count 2 2006.224.08:13:10.99#ibcon#read 4, iclass 24, count 2 2006.224.08:13:10.99#ibcon#about to read 5, iclass 24, count 2 2006.224.08:13:10.99#ibcon#read 5, iclass 24, count 2 2006.224.08:13:10.99#ibcon#about to read 6, iclass 24, count 2 2006.224.08:13:10.99#ibcon#read 6, iclass 24, count 2 2006.224.08:13:10.99#ibcon#end of sib2, iclass 24, count 2 2006.224.08:13:10.99#ibcon#*after write, iclass 24, count 2 2006.224.08:13:10.99#ibcon#*before return 0, iclass 24, count 2 2006.224.08:13:10.99#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.224.08:13:10.99#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.224.08:13:10.99#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.224.08:13:10.99#ibcon#ireg 7 cls_cnt 0 2006.224.08:13:10.99#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.224.08:13:11.11#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.224.08:13:11.11#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.224.08:13:11.11#ibcon#enter wrdev, iclass 24, count 0 2006.224.08:13:11.11#ibcon#first serial, iclass 24, count 0 2006.224.08:13:11.11#ibcon#enter sib2, iclass 24, count 0 2006.224.08:13:11.11#ibcon#flushed, iclass 24, count 0 2006.224.08:13:11.11#ibcon#about to write, iclass 24, count 0 2006.224.08:13:11.11#ibcon#wrote, iclass 24, count 0 2006.224.08:13:11.11#ibcon#about to read 3, iclass 24, count 0 2006.224.08:13:11.13#ibcon#read 3, iclass 24, count 0 2006.224.08:13:11.13#ibcon#about to read 4, iclass 24, count 0 2006.224.08:13:11.13#ibcon#read 4, iclass 24, count 0 2006.224.08:13:11.13#ibcon#about to read 5, iclass 24, count 0 2006.224.08:13:11.13#ibcon#read 5, iclass 24, count 0 2006.224.08:13:11.13#ibcon#about to read 6, iclass 24, count 0 2006.224.08:13:11.13#ibcon#read 6, iclass 24, count 0 2006.224.08:13:11.13#ibcon#end of sib2, iclass 24, count 0 2006.224.08:13:11.13#ibcon#*mode == 0, iclass 24, count 0 2006.224.08:13:11.13#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.224.08:13:11.13#ibcon#[27=USB\r\n] 2006.224.08:13:11.13#ibcon#*before write, iclass 24, count 0 2006.224.08:13:11.13#ibcon#enter sib2, iclass 24, count 0 2006.224.08:13:11.13#ibcon#flushed, iclass 24, count 0 2006.224.08:13:11.13#ibcon#about to write, iclass 24, count 0 2006.224.08:13:11.13#ibcon#wrote, iclass 24, count 0 2006.224.08:13:11.13#ibcon#about to read 3, iclass 24, count 0 2006.224.08:13:11.16#ibcon#read 3, iclass 24, count 0 2006.224.08:13:11.16#ibcon#about to read 4, iclass 24, count 0 2006.224.08:13:11.16#ibcon#read 4, iclass 24, count 0 2006.224.08:13:11.16#ibcon#about to read 5, iclass 24, count 0 2006.224.08:13:11.16#ibcon#read 5, iclass 24, count 0 2006.224.08:13:11.16#ibcon#about to read 6, iclass 24, count 0 2006.224.08:13:11.16#ibcon#read 6, iclass 24, count 0 2006.224.08:13:11.16#ibcon#end of sib2, iclass 24, count 0 2006.224.08:13:11.16#ibcon#*after write, iclass 24, count 0 2006.224.08:13:11.16#ibcon#*before return 0, iclass 24, count 0 2006.224.08:13:11.16#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.224.08:13:11.16#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.224.08:13:11.16#ibcon#about to clear, iclass 24 cls_cnt 0 2006.224.08:13:11.16#ibcon#cleared, iclass 24 cls_cnt 0 2006.224.08:13:11.16$vc4f8/vblo=3,656.99 2006.224.08:13:11.16#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.224.08:13:11.16#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.224.08:13:11.16#ibcon#ireg 17 cls_cnt 0 2006.224.08:13:11.16#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.224.08:13:11.16#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.224.08:13:11.16#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.224.08:13:11.16#ibcon#enter wrdev, iclass 26, count 0 2006.224.08:13:11.16#ibcon#first serial, iclass 26, count 0 2006.224.08:13:11.16#ibcon#enter sib2, iclass 26, count 0 2006.224.08:13:11.16#ibcon#flushed, iclass 26, count 0 2006.224.08:13:11.16#ibcon#about to write, iclass 26, count 0 2006.224.08:13:11.16#ibcon#wrote, iclass 26, count 0 2006.224.08:13:11.16#ibcon#about to read 3, iclass 26, count 0 2006.224.08:13:11.18#ibcon#read 3, iclass 26, count 0 2006.224.08:13:11.18#ibcon#about to read 4, iclass 26, count 0 2006.224.08:13:11.18#ibcon#read 4, iclass 26, count 0 2006.224.08:13:11.18#ibcon#about to read 5, iclass 26, count 0 2006.224.08:13:11.18#ibcon#read 5, iclass 26, count 0 2006.224.08:13:11.18#ibcon#about to read 6, iclass 26, count 0 2006.224.08:13:11.18#ibcon#read 6, iclass 26, count 0 2006.224.08:13:11.18#ibcon#end of sib2, iclass 26, count 0 2006.224.08:13:11.18#ibcon#*mode == 0, iclass 26, count 0 2006.224.08:13:11.18#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.224.08:13:11.18#ibcon#[28=FRQ=03,656.99\r\n] 2006.224.08:13:11.18#ibcon#*before write, iclass 26, count 0 2006.224.08:13:11.18#ibcon#enter sib2, iclass 26, count 0 2006.224.08:13:11.18#ibcon#flushed, iclass 26, count 0 2006.224.08:13:11.18#ibcon#about to write, iclass 26, count 0 2006.224.08:13:11.18#ibcon#wrote, iclass 26, count 0 2006.224.08:13:11.18#ibcon#about to read 3, iclass 26, count 0 2006.224.08:13:11.23#ibcon#read 3, iclass 26, count 0 2006.224.08:13:11.23#ibcon#about to read 4, iclass 26, count 0 2006.224.08:13:11.23#ibcon#read 4, iclass 26, count 0 2006.224.08:13:11.23#ibcon#about to read 5, iclass 26, count 0 2006.224.08:13:11.23#ibcon#read 5, iclass 26, count 0 2006.224.08:13:11.23#ibcon#about to read 6, iclass 26, count 0 2006.224.08:13:11.23#ibcon#read 6, iclass 26, count 0 2006.224.08:13:11.23#ibcon#end of sib2, iclass 26, count 0 2006.224.08:13:11.23#ibcon#*after write, iclass 26, count 0 2006.224.08:13:11.23#ibcon#*before return 0, iclass 26, count 0 2006.224.08:13:11.23#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.224.08:13:11.23#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.224.08:13:11.23#ibcon#about to clear, iclass 26 cls_cnt 0 2006.224.08:13:11.23#ibcon#cleared, iclass 26 cls_cnt 0 2006.224.08:13:11.23$vc4f8/vb=3,4 2006.224.08:13:11.23#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.224.08:13:11.23#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.224.08:13:11.23#ibcon#ireg 11 cls_cnt 2 2006.224.08:13:11.23#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.224.08:13:11.28#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.224.08:13:11.28#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.224.08:13:11.28#ibcon#enter wrdev, iclass 28, count 2 2006.224.08:13:11.28#ibcon#first serial, iclass 28, count 2 2006.224.08:13:11.28#ibcon#enter sib2, iclass 28, count 2 2006.224.08:13:11.28#ibcon#flushed, iclass 28, count 2 2006.224.08:13:11.28#ibcon#about to write, iclass 28, count 2 2006.224.08:13:11.28#ibcon#wrote, iclass 28, count 2 2006.224.08:13:11.28#ibcon#about to read 3, iclass 28, count 2 2006.224.08:13:11.30#ibcon#read 3, iclass 28, count 2 2006.224.08:13:11.30#ibcon#about to read 4, iclass 28, count 2 2006.224.08:13:11.30#ibcon#read 4, iclass 28, count 2 2006.224.08:13:11.30#ibcon#about to read 5, iclass 28, count 2 2006.224.08:13:11.30#ibcon#read 5, iclass 28, count 2 2006.224.08:13:11.30#ibcon#about to read 6, iclass 28, count 2 2006.224.08:13:11.30#ibcon#read 6, iclass 28, count 2 2006.224.08:13:11.30#ibcon#end of sib2, iclass 28, count 2 2006.224.08:13:11.30#ibcon#*mode == 0, iclass 28, count 2 2006.224.08:13:11.30#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.224.08:13:11.30#ibcon#[27=AT03-04\r\n] 2006.224.08:13:11.30#ibcon#*before write, iclass 28, count 2 2006.224.08:13:11.30#ibcon#enter sib2, iclass 28, count 2 2006.224.08:13:11.30#ibcon#flushed, iclass 28, count 2 2006.224.08:13:11.30#ibcon#about to write, iclass 28, count 2 2006.224.08:13:11.30#ibcon#wrote, iclass 28, count 2 2006.224.08:13:11.30#ibcon#about to read 3, iclass 28, count 2 2006.224.08:13:11.33#ibcon#read 3, iclass 28, count 2 2006.224.08:13:11.33#ibcon#about to read 4, iclass 28, count 2 2006.224.08:13:11.33#ibcon#read 4, iclass 28, count 2 2006.224.08:13:11.33#ibcon#about to read 5, iclass 28, count 2 2006.224.08:13:11.33#ibcon#read 5, iclass 28, count 2 2006.224.08:13:11.33#ibcon#about to read 6, iclass 28, count 2 2006.224.08:13:11.33#ibcon#read 6, iclass 28, count 2 2006.224.08:13:11.33#ibcon#end of sib2, iclass 28, count 2 2006.224.08:13:11.33#ibcon#*after write, iclass 28, count 2 2006.224.08:13:11.33#ibcon#*before return 0, iclass 28, count 2 2006.224.08:13:11.33#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.224.08:13:11.33#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.224.08:13:11.33#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.224.08:13:11.33#ibcon#ireg 7 cls_cnt 0 2006.224.08:13:11.33#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.224.08:13:11.45#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.224.08:13:11.45#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.224.08:13:11.45#ibcon#enter wrdev, iclass 28, count 0 2006.224.08:13:11.45#ibcon#first serial, iclass 28, count 0 2006.224.08:13:11.45#ibcon#enter sib2, iclass 28, count 0 2006.224.08:13:11.45#ibcon#flushed, iclass 28, count 0 2006.224.08:13:11.45#ibcon#about to write, iclass 28, count 0 2006.224.08:13:11.45#ibcon#wrote, iclass 28, count 0 2006.224.08:13:11.45#ibcon#about to read 3, iclass 28, count 0 2006.224.08:13:11.47#ibcon#read 3, iclass 28, count 0 2006.224.08:13:11.47#ibcon#about to read 4, iclass 28, count 0 2006.224.08:13:11.47#ibcon#read 4, iclass 28, count 0 2006.224.08:13:11.47#ibcon#about to read 5, iclass 28, count 0 2006.224.08:13:11.47#ibcon#read 5, iclass 28, count 0 2006.224.08:13:11.47#ibcon#about to read 6, iclass 28, count 0 2006.224.08:13:11.47#ibcon#read 6, iclass 28, count 0 2006.224.08:13:11.47#ibcon#end of sib2, iclass 28, count 0 2006.224.08:13:11.47#ibcon#*mode == 0, iclass 28, count 0 2006.224.08:13:11.47#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.224.08:13:11.47#ibcon#[27=USB\r\n] 2006.224.08:13:11.47#ibcon#*before write, iclass 28, count 0 2006.224.08:13:11.47#ibcon#enter sib2, iclass 28, count 0 2006.224.08:13:11.47#ibcon#flushed, iclass 28, count 0 2006.224.08:13:11.47#ibcon#about to write, iclass 28, count 0 2006.224.08:13:11.47#ibcon#wrote, iclass 28, count 0 2006.224.08:13:11.47#ibcon#about to read 3, iclass 28, count 0 2006.224.08:13:11.50#ibcon#read 3, iclass 28, count 0 2006.224.08:13:11.50#ibcon#about to read 4, iclass 28, count 0 2006.224.08:13:11.50#ibcon#read 4, iclass 28, count 0 2006.224.08:13:11.50#ibcon#about to read 5, iclass 28, count 0 2006.224.08:13:11.50#ibcon#read 5, iclass 28, count 0 2006.224.08:13:11.50#ibcon#about to read 6, iclass 28, count 0 2006.224.08:13:11.50#ibcon#read 6, iclass 28, count 0 2006.224.08:13:11.50#ibcon#end of sib2, iclass 28, count 0 2006.224.08:13:11.50#ibcon#*after write, iclass 28, count 0 2006.224.08:13:11.50#ibcon#*before return 0, iclass 28, count 0 2006.224.08:13:11.50#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.224.08:13:11.50#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.224.08:13:11.50#ibcon#about to clear, iclass 28 cls_cnt 0 2006.224.08:13:11.50#ibcon#cleared, iclass 28 cls_cnt 0 2006.224.08:13:11.50$vc4f8/vblo=4,712.99 2006.224.08:13:11.50#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.224.08:13:11.50#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.224.08:13:11.50#ibcon#ireg 17 cls_cnt 0 2006.224.08:13:11.50#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.224.08:13:11.50#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.224.08:13:11.50#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.224.08:13:11.50#ibcon#enter wrdev, iclass 30, count 0 2006.224.08:13:11.50#ibcon#first serial, iclass 30, count 0 2006.224.08:13:11.50#ibcon#enter sib2, iclass 30, count 0 2006.224.08:13:11.50#ibcon#flushed, iclass 30, count 0 2006.224.08:13:11.50#ibcon#about to write, iclass 30, count 0 2006.224.08:13:11.50#ibcon#wrote, iclass 30, count 0 2006.224.08:13:11.50#ibcon#about to read 3, iclass 30, count 0 2006.224.08:13:11.52#ibcon#read 3, iclass 30, count 0 2006.224.08:13:11.52#ibcon#about to read 4, iclass 30, count 0 2006.224.08:13:11.52#ibcon#read 4, iclass 30, count 0 2006.224.08:13:11.52#ibcon#about to read 5, iclass 30, count 0 2006.224.08:13:11.52#ibcon#read 5, iclass 30, count 0 2006.224.08:13:11.52#ibcon#about to read 6, iclass 30, count 0 2006.224.08:13:11.52#ibcon#read 6, iclass 30, count 0 2006.224.08:13:11.52#ibcon#end of sib2, iclass 30, count 0 2006.224.08:13:11.52#ibcon#*mode == 0, iclass 30, count 0 2006.224.08:13:11.52#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.224.08:13:11.52#ibcon#[28=FRQ=04,712.99\r\n] 2006.224.08:13:11.52#ibcon#*before write, iclass 30, count 0 2006.224.08:13:11.52#ibcon#enter sib2, iclass 30, count 0 2006.224.08:13:11.52#ibcon#flushed, iclass 30, count 0 2006.224.08:13:11.52#ibcon#about to write, iclass 30, count 0 2006.224.08:13:11.52#ibcon#wrote, iclass 30, count 0 2006.224.08:13:11.52#ibcon#about to read 3, iclass 30, count 0 2006.224.08:13:11.56#ibcon#read 3, iclass 30, count 0 2006.224.08:13:11.56#ibcon#about to read 4, iclass 30, count 0 2006.224.08:13:11.56#ibcon#read 4, iclass 30, count 0 2006.224.08:13:11.56#ibcon#about to read 5, iclass 30, count 0 2006.224.08:13:11.56#ibcon#read 5, iclass 30, count 0 2006.224.08:13:11.56#ibcon#about to read 6, iclass 30, count 0 2006.224.08:13:11.56#ibcon#read 6, iclass 30, count 0 2006.224.08:13:11.56#ibcon#end of sib2, iclass 30, count 0 2006.224.08:13:11.56#ibcon#*after write, iclass 30, count 0 2006.224.08:13:11.56#ibcon#*before return 0, iclass 30, count 0 2006.224.08:13:11.56#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.224.08:13:11.56#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.224.08:13:11.56#ibcon#about to clear, iclass 30 cls_cnt 0 2006.224.08:13:11.56#ibcon#cleared, iclass 30 cls_cnt 0 2006.224.08:13:11.56$vc4f8/vb=4,4 2006.224.08:13:11.56#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.224.08:13:11.56#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.224.08:13:11.56#ibcon#ireg 11 cls_cnt 2 2006.224.08:13:11.56#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.224.08:13:11.62#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.224.08:13:11.62#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.224.08:13:11.62#ibcon#enter wrdev, iclass 32, count 2 2006.224.08:13:11.62#ibcon#first serial, iclass 32, count 2 2006.224.08:13:11.62#ibcon#enter sib2, iclass 32, count 2 2006.224.08:13:11.62#ibcon#flushed, iclass 32, count 2 2006.224.08:13:11.62#ibcon#about to write, iclass 32, count 2 2006.224.08:13:11.62#ibcon#wrote, iclass 32, count 2 2006.224.08:13:11.62#ibcon#about to read 3, iclass 32, count 2 2006.224.08:13:11.64#ibcon#read 3, iclass 32, count 2 2006.224.08:13:11.64#ibcon#about to read 4, iclass 32, count 2 2006.224.08:13:11.64#ibcon#read 4, iclass 32, count 2 2006.224.08:13:11.64#ibcon#about to read 5, iclass 32, count 2 2006.224.08:13:11.64#ibcon#read 5, iclass 32, count 2 2006.224.08:13:11.64#ibcon#about to read 6, iclass 32, count 2 2006.224.08:13:11.64#ibcon#read 6, iclass 32, count 2 2006.224.08:13:11.64#ibcon#end of sib2, iclass 32, count 2 2006.224.08:13:11.64#ibcon#*mode == 0, iclass 32, count 2 2006.224.08:13:11.64#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.224.08:13:11.64#ibcon#[27=AT04-04\r\n] 2006.224.08:13:11.64#ibcon#*before write, iclass 32, count 2 2006.224.08:13:11.64#ibcon#enter sib2, iclass 32, count 2 2006.224.08:13:11.64#ibcon#flushed, iclass 32, count 2 2006.224.08:13:11.64#ibcon#about to write, iclass 32, count 2 2006.224.08:13:11.64#ibcon#wrote, iclass 32, count 2 2006.224.08:13:11.64#ibcon#about to read 3, iclass 32, count 2 2006.224.08:13:11.67#ibcon#read 3, iclass 32, count 2 2006.224.08:13:11.67#ibcon#about to read 4, iclass 32, count 2 2006.224.08:13:11.67#ibcon#read 4, iclass 32, count 2 2006.224.08:13:11.67#ibcon#about to read 5, iclass 32, count 2 2006.224.08:13:11.67#ibcon#read 5, iclass 32, count 2 2006.224.08:13:11.67#ibcon#about to read 6, iclass 32, count 2 2006.224.08:13:11.67#ibcon#read 6, iclass 32, count 2 2006.224.08:13:11.67#ibcon#end of sib2, iclass 32, count 2 2006.224.08:13:11.67#ibcon#*after write, iclass 32, count 2 2006.224.08:13:11.67#ibcon#*before return 0, iclass 32, count 2 2006.224.08:13:11.67#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.224.08:13:11.67#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.224.08:13:11.67#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.224.08:13:11.67#ibcon#ireg 7 cls_cnt 0 2006.224.08:13:11.67#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.224.08:13:11.79#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.224.08:13:11.79#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.224.08:13:11.79#ibcon#enter wrdev, iclass 32, count 0 2006.224.08:13:11.79#ibcon#first serial, iclass 32, count 0 2006.224.08:13:11.79#ibcon#enter sib2, iclass 32, count 0 2006.224.08:13:11.79#ibcon#flushed, iclass 32, count 0 2006.224.08:13:11.79#ibcon#about to write, iclass 32, count 0 2006.224.08:13:11.79#ibcon#wrote, iclass 32, count 0 2006.224.08:13:11.79#ibcon#about to read 3, iclass 32, count 0 2006.224.08:13:11.81#ibcon#read 3, iclass 32, count 0 2006.224.08:13:11.81#ibcon#about to read 4, iclass 32, count 0 2006.224.08:13:11.81#ibcon#read 4, iclass 32, count 0 2006.224.08:13:11.81#ibcon#about to read 5, iclass 32, count 0 2006.224.08:13:11.81#ibcon#read 5, iclass 32, count 0 2006.224.08:13:11.81#ibcon#about to read 6, iclass 32, count 0 2006.224.08:13:11.81#ibcon#read 6, iclass 32, count 0 2006.224.08:13:11.81#ibcon#end of sib2, iclass 32, count 0 2006.224.08:13:11.81#ibcon#*mode == 0, iclass 32, count 0 2006.224.08:13:11.81#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.224.08:13:11.81#ibcon#[27=USB\r\n] 2006.224.08:13:11.81#ibcon#*before write, iclass 32, count 0 2006.224.08:13:11.81#ibcon#enter sib2, iclass 32, count 0 2006.224.08:13:11.81#ibcon#flushed, iclass 32, count 0 2006.224.08:13:11.81#ibcon#about to write, iclass 32, count 0 2006.224.08:13:11.81#ibcon#wrote, iclass 32, count 0 2006.224.08:13:11.81#ibcon#about to read 3, iclass 32, count 0 2006.224.08:13:11.84#ibcon#read 3, iclass 32, count 0 2006.224.08:13:11.84#ibcon#about to read 4, iclass 32, count 0 2006.224.08:13:11.84#ibcon#read 4, iclass 32, count 0 2006.224.08:13:11.84#ibcon#about to read 5, iclass 32, count 0 2006.224.08:13:11.84#ibcon#read 5, iclass 32, count 0 2006.224.08:13:11.84#ibcon#about to read 6, iclass 32, count 0 2006.224.08:13:11.84#ibcon#read 6, iclass 32, count 0 2006.224.08:13:11.84#ibcon#end of sib2, iclass 32, count 0 2006.224.08:13:11.84#ibcon#*after write, iclass 32, count 0 2006.224.08:13:11.84#ibcon#*before return 0, iclass 32, count 0 2006.224.08:13:11.84#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.224.08:13:11.84#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.224.08:13:11.84#ibcon#about to clear, iclass 32 cls_cnt 0 2006.224.08:13:11.84#ibcon#cleared, iclass 32 cls_cnt 0 2006.224.08:13:11.84$vc4f8/vblo=5,744.99 2006.224.08:13:11.84#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.224.08:13:11.84#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.224.08:13:11.84#ibcon#ireg 17 cls_cnt 0 2006.224.08:13:11.84#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.224.08:13:11.84#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.224.08:13:11.84#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.224.08:13:11.84#ibcon#enter wrdev, iclass 34, count 0 2006.224.08:13:11.84#ibcon#first serial, iclass 34, count 0 2006.224.08:13:11.84#ibcon#enter sib2, iclass 34, count 0 2006.224.08:13:11.84#ibcon#flushed, iclass 34, count 0 2006.224.08:13:11.84#ibcon#about to write, iclass 34, count 0 2006.224.08:13:11.84#ibcon#wrote, iclass 34, count 0 2006.224.08:13:11.84#ibcon#about to read 3, iclass 34, count 0 2006.224.08:13:11.86#ibcon#read 3, iclass 34, count 0 2006.224.08:13:11.86#ibcon#about to read 4, iclass 34, count 0 2006.224.08:13:11.86#ibcon#read 4, iclass 34, count 0 2006.224.08:13:11.86#ibcon#about to read 5, iclass 34, count 0 2006.224.08:13:11.86#ibcon#read 5, iclass 34, count 0 2006.224.08:13:11.86#ibcon#about to read 6, iclass 34, count 0 2006.224.08:13:11.86#ibcon#read 6, iclass 34, count 0 2006.224.08:13:11.86#ibcon#end of sib2, iclass 34, count 0 2006.224.08:13:11.86#ibcon#*mode == 0, iclass 34, count 0 2006.224.08:13:11.86#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.224.08:13:11.86#ibcon#[28=FRQ=05,744.99\r\n] 2006.224.08:13:11.86#ibcon#*before write, iclass 34, count 0 2006.224.08:13:11.86#ibcon#enter sib2, iclass 34, count 0 2006.224.08:13:11.86#ibcon#flushed, iclass 34, count 0 2006.224.08:13:11.86#ibcon#about to write, iclass 34, count 0 2006.224.08:13:11.86#ibcon#wrote, iclass 34, count 0 2006.224.08:13:11.86#ibcon#about to read 3, iclass 34, count 0 2006.224.08:13:11.90#ibcon#read 3, iclass 34, count 0 2006.224.08:13:11.90#ibcon#about to read 4, iclass 34, count 0 2006.224.08:13:11.90#ibcon#read 4, iclass 34, count 0 2006.224.08:13:11.90#ibcon#about to read 5, iclass 34, count 0 2006.224.08:13:11.90#ibcon#read 5, iclass 34, count 0 2006.224.08:13:11.90#ibcon#about to read 6, iclass 34, count 0 2006.224.08:13:11.90#ibcon#read 6, iclass 34, count 0 2006.224.08:13:11.90#ibcon#end of sib2, iclass 34, count 0 2006.224.08:13:11.90#ibcon#*after write, iclass 34, count 0 2006.224.08:13:11.90#ibcon#*before return 0, iclass 34, count 0 2006.224.08:13:11.90#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.224.08:13:11.90#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.224.08:13:11.90#ibcon#about to clear, iclass 34 cls_cnt 0 2006.224.08:13:11.90#ibcon#cleared, iclass 34 cls_cnt 0 2006.224.08:13:11.90$vc4f8/vb=5,4 2006.224.08:13:11.90#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.224.08:13:11.90#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.224.08:13:11.90#ibcon#ireg 11 cls_cnt 2 2006.224.08:13:11.90#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.224.08:13:11.96#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.224.08:13:11.96#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.224.08:13:11.96#ibcon#enter wrdev, iclass 36, count 2 2006.224.08:13:11.96#ibcon#first serial, iclass 36, count 2 2006.224.08:13:11.96#ibcon#enter sib2, iclass 36, count 2 2006.224.08:13:11.96#ibcon#flushed, iclass 36, count 2 2006.224.08:13:11.96#ibcon#about to write, iclass 36, count 2 2006.224.08:13:11.96#ibcon#wrote, iclass 36, count 2 2006.224.08:13:11.96#ibcon#about to read 3, iclass 36, count 2 2006.224.08:13:11.98#ibcon#read 3, iclass 36, count 2 2006.224.08:13:11.98#ibcon#about to read 4, iclass 36, count 2 2006.224.08:13:11.98#ibcon#read 4, iclass 36, count 2 2006.224.08:13:11.98#ibcon#about to read 5, iclass 36, count 2 2006.224.08:13:11.98#ibcon#read 5, iclass 36, count 2 2006.224.08:13:11.98#ibcon#about to read 6, iclass 36, count 2 2006.224.08:13:11.98#ibcon#read 6, iclass 36, count 2 2006.224.08:13:11.98#ibcon#end of sib2, iclass 36, count 2 2006.224.08:13:11.98#ibcon#*mode == 0, iclass 36, count 2 2006.224.08:13:11.98#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.224.08:13:11.98#ibcon#[27=AT05-04\r\n] 2006.224.08:13:11.98#ibcon#*before write, iclass 36, count 2 2006.224.08:13:11.98#ibcon#enter sib2, iclass 36, count 2 2006.224.08:13:11.98#ibcon#flushed, iclass 36, count 2 2006.224.08:13:11.98#ibcon#about to write, iclass 36, count 2 2006.224.08:13:11.98#ibcon#wrote, iclass 36, count 2 2006.224.08:13:11.98#ibcon#about to read 3, iclass 36, count 2 2006.224.08:13:12.01#ibcon#read 3, iclass 36, count 2 2006.224.08:13:12.01#ibcon#about to read 4, iclass 36, count 2 2006.224.08:13:12.01#ibcon#read 4, iclass 36, count 2 2006.224.08:13:12.01#ibcon#about to read 5, iclass 36, count 2 2006.224.08:13:12.01#ibcon#read 5, iclass 36, count 2 2006.224.08:13:12.01#ibcon#about to read 6, iclass 36, count 2 2006.224.08:13:12.01#ibcon#read 6, iclass 36, count 2 2006.224.08:13:12.01#ibcon#end of sib2, iclass 36, count 2 2006.224.08:13:12.01#ibcon#*after write, iclass 36, count 2 2006.224.08:13:12.01#ibcon#*before return 0, iclass 36, count 2 2006.224.08:13:12.01#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.224.08:13:12.01#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.224.08:13:12.01#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.224.08:13:12.01#ibcon#ireg 7 cls_cnt 0 2006.224.08:13:12.01#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.224.08:13:12.13#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.224.08:13:12.13#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.224.08:13:12.13#ibcon#enter wrdev, iclass 36, count 0 2006.224.08:13:12.13#ibcon#first serial, iclass 36, count 0 2006.224.08:13:12.13#ibcon#enter sib2, iclass 36, count 0 2006.224.08:13:12.13#ibcon#flushed, iclass 36, count 0 2006.224.08:13:12.13#ibcon#about to write, iclass 36, count 0 2006.224.08:13:12.13#ibcon#wrote, iclass 36, count 0 2006.224.08:13:12.13#ibcon#about to read 3, iclass 36, count 0 2006.224.08:13:12.15#ibcon#read 3, iclass 36, count 0 2006.224.08:13:12.15#ibcon#about to read 4, iclass 36, count 0 2006.224.08:13:12.15#ibcon#read 4, iclass 36, count 0 2006.224.08:13:12.15#ibcon#about to read 5, iclass 36, count 0 2006.224.08:13:12.15#ibcon#read 5, iclass 36, count 0 2006.224.08:13:12.15#ibcon#about to read 6, iclass 36, count 0 2006.224.08:13:12.15#ibcon#read 6, iclass 36, count 0 2006.224.08:13:12.15#ibcon#end of sib2, iclass 36, count 0 2006.224.08:13:12.15#ibcon#*mode == 0, iclass 36, count 0 2006.224.08:13:12.15#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.224.08:13:12.15#ibcon#[27=USB\r\n] 2006.224.08:13:12.15#ibcon#*before write, iclass 36, count 0 2006.224.08:13:12.15#ibcon#enter sib2, iclass 36, count 0 2006.224.08:13:12.15#ibcon#flushed, iclass 36, count 0 2006.224.08:13:12.15#ibcon#about to write, iclass 36, count 0 2006.224.08:13:12.15#ibcon#wrote, iclass 36, count 0 2006.224.08:13:12.15#ibcon#about to read 3, iclass 36, count 0 2006.224.08:13:12.18#ibcon#read 3, iclass 36, count 0 2006.224.08:13:12.18#ibcon#about to read 4, iclass 36, count 0 2006.224.08:13:12.18#ibcon#read 4, iclass 36, count 0 2006.224.08:13:12.18#ibcon#about to read 5, iclass 36, count 0 2006.224.08:13:12.18#ibcon#read 5, iclass 36, count 0 2006.224.08:13:12.18#ibcon#about to read 6, iclass 36, count 0 2006.224.08:13:12.18#ibcon#read 6, iclass 36, count 0 2006.224.08:13:12.18#ibcon#end of sib2, iclass 36, count 0 2006.224.08:13:12.18#ibcon#*after write, iclass 36, count 0 2006.224.08:13:12.18#ibcon#*before return 0, iclass 36, count 0 2006.224.08:13:12.18#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.224.08:13:12.18#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.224.08:13:12.18#ibcon#about to clear, iclass 36 cls_cnt 0 2006.224.08:13:12.18#ibcon#cleared, iclass 36 cls_cnt 0 2006.224.08:13:12.18$vc4f8/vblo=6,752.99 2006.224.08:13:12.18#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.224.08:13:12.18#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.224.08:13:12.18#ibcon#ireg 17 cls_cnt 0 2006.224.08:13:12.18#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.224.08:13:12.18#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.224.08:13:12.18#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.224.08:13:12.18#ibcon#enter wrdev, iclass 38, count 0 2006.224.08:13:12.18#ibcon#first serial, iclass 38, count 0 2006.224.08:13:12.18#ibcon#enter sib2, iclass 38, count 0 2006.224.08:13:12.18#ibcon#flushed, iclass 38, count 0 2006.224.08:13:12.18#ibcon#about to write, iclass 38, count 0 2006.224.08:13:12.18#ibcon#wrote, iclass 38, count 0 2006.224.08:13:12.18#ibcon#about to read 3, iclass 38, count 0 2006.224.08:13:12.20#ibcon#read 3, iclass 38, count 0 2006.224.08:13:12.20#ibcon#about to read 4, iclass 38, count 0 2006.224.08:13:12.20#ibcon#read 4, iclass 38, count 0 2006.224.08:13:12.20#ibcon#about to read 5, iclass 38, count 0 2006.224.08:13:12.20#ibcon#read 5, iclass 38, count 0 2006.224.08:13:12.20#ibcon#about to read 6, iclass 38, count 0 2006.224.08:13:12.20#ibcon#read 6, iclass 38, count 0 2006.224.08:13:12.20#ibcon#end of sib2, iclass 38, count 0 2006.224.08:13:12.20#ibcon#*mode == 0, iclass 38, count 0 2006.224.08:13:12.20#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.224.08:13:12.20#ibcon#[28=FRQ=06,752.99\r\n] 2006.224.08:13:12.20#ibcon#*before write, iclass 38, count 0 2006.224.08:13:12.20#ibcon#enter sib2, iclass 38, count 0 2006.224.08:13:12.20#ibcon#flushed, iclass 38, count 0 2006.224.08:13:12.20#ibcon#about to write, iclass 38, count 0 2006.224.08:13:12.20#ibcon#wrote, iclass 38, count 0 2006.224.08:13:12.20#ibcon#about to read 3, iclass 38, count 0 2006.224.08:13:12.25#ibcon#read 3, iclass 38, count 0 2006.224.08:13:12.25#ibcon#about to read 4, iclass 38, count 0 2006.224.08:13:12.25#ibcon#read 4, iclass 38, count 0 2006.224.08:13:12.25#ibcon#about to read 5, iclass 38, count 0 2006.224.08:13:12.25#ibcon#read 5, iclass 38, count 0 2006.224.08:13:12.25#ibcon#about to read 6, iclass 38, count 0 2006.224.08:13:12.25#ibcon#read 6, iclass 38, count 0 2006.224.08:13:12.25#ibcon#end of sib2, iclass 38, count 0 2006.224.08:13:12.25#ibcon#*after write, iclass 38, count 0 2006.224.08:13:12.25#ibcon#*before return 0, iclass 38, count 0 2006.224.08:13:12.25#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.224.08:13:12.25#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.224.08:13:12.25#ibcon#about to clear, iclass 38 cls_cnt 0 2006.224.08:13:12.25#ibcon#cleared, iclass 38 cls_cnt 0 2006.224.08:13:12.25$vc4f8/vb=6,4 2006.224.08:13:12.25#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.224.08:13:12.25#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.224.08:13:12.25#ibcon#ireg 11 cls_cnt 2 2006.224.08:13:12.25#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.224.08:13:12.30#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.224.08:13:12.30#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.224.08:13:12.30#ibcon#enter wrdev, iclass 40, count 2 2006.224.08:13:12.30#ibcon#first serial, iclass 40, count 2 2006.224.08:13:12.30#ibcon#enter sib2, iclass 40, count 2 2006.224.08:13:12.30#ibcon#flushed, iclass 40, count 2 2006.224.08:13:12.30#ibcon#about to write, iclass 40, count 2 2006.224.08:13:12.30#ibcon#wrote, iclass 40, count 2 2006.224.08:13:12.30#ibcon#about to read 3, iclass 40, count 2 2006.224.08:13:12.32#ibcon#read 3, iclass 40, count 2 2006.224.08:13:12.32#ibcon#about to read 4, iclass 40, count 2 2006.224.08:13:12.32#ibcon#read 4, iclass 40, count 2 2006.224.08:13:12.32#ibcon#about to read 5, iclass 40, count 2 2006.224.08:13:12.32#ibcon#read 5, iclass 40, count 2 2006.224.08:13:12.32#ibcon#about to read 6, iclass 40, count 2 2006.224.08:13:12.32#ibcon#read 6, iclass 40, count 2 2006.224.08:13:12.32#ibcon#end of sib2, iclass 40, count 2 2006.224.08:13:12.32#ibcon#*mode == 0, iclass 40, count 2 2006.224.08:13:12.32#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.224.08:13:12.32#ibcon#[27=AT06-04\r\n] 2006.224.08:13:12.32#ibcon#*before write, iclass 40, count 2 2006.224.08:13:12.32#ibcon#enter sib2, iclass 40, count 2 2006.224.08:13:12.32#ibcon#flushed, iclass 40, count 2 2006.224.08:13:12.32#ibcon#about to write, iclass 40, count 2 2006.224.08:13:12.32#ibcon#wrote, iclass 40, count 2 2006.224.08:13:12.32#ibcon#about to read 3, iclass 40, count 2 2006.224.08:13:12.35#ibcon#read 3, iclass 40, count 2 2006.224.08:13:12.35#ibcon#about to read 4, iclass 40, count 2 2006.224.08:13:12.35#ibcon#read 4, iclass 40, count 2 2006.224.08:13:12.35#ibcon#about to read 5, iclass 40, count 2 2006.224.08:13:12.35#ibcon#read 5, iclass 40, count 2 2006.224.08:13:12.35#ibcon#about to read 6, iclass 40, count 2 2006.224.08:13:12.35#ibcon#read 6, iclass 40, count 2 2006.224.08:13:12.35#ibcon#end of sib2, iclass 40, count 2 2006.224.08:13:12.35#ibcon#*after write, iclass 40, count 2 2006.224.08:13:12.35#ibcon#*before return 0, iclass 40, count 2 2006.224.08:13:12.35#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.224.08:13:12.35#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.224.08:13:12.35#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.224.08:13:12.35#ibcon#ireg 7 cls_cnt 0 2006.224.08:13:12.35#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.224.08:13:12.47#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.224.08:13:12.47#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.224.08:13:12.47#ibcon#enter wrdev, iclass 40, count 0 2006.224.08:13:12.47#ibcon#first serial, iclass 40, count 0 2006.224.08:13:12.47#ibcon#enter sib2, iclass 40, count 0 2006.224.08:13:12.47#ibcon#flushed, iclass 40, count 0 2006.224.08:13:12.47#ibcon#about to write, iclass 40, count 0 2006.224.08:13:12.47#ibcon#wrote, iclass 40, count 0 2006.224.08:13:12.47#ibcon#about to read 3, iclass 40, count 0 2006.224.08:13:12.49#ibcon#read 3, iclass 40, count 0 2006.224.08:13:12.49#ibcon#about to read 4, iclass 40, count 0 2006.224.08:13:12.49#ibcon#read 4, iclass 40, count 0 2006.224.08:13:12.49#ibcon#about to read 5, iclass 40, count 0 2006.224.08:13:12.49#ibcon#read 5, iclass 40, count 0 2006.224.08:13:12.49#ibcon#about to read 6, iclass 40, count 0 2006.224.08:13:12.49#ibcon#read 6, iclass 40, count 0 2006.224.08:13:12.49#ibcon#end of sib2, iclass 40, count 0 2006.224.08:13:12.49#ibcon#*mode == 0, iclass 40, count 0 2006.224.08:13:12.49#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.224.08:13:12.49#ibcon#[27=USB\r\n] 2006.224.08:13:12.49#ibcon#*before write, iclass 40, count 0 2006.224.08:13:12.49#ibcon#enter sib2, iclass 40, count 0 2006.224.08:13:12.49#ibcon#flushed, iclass 40, count 0 2006.224.08:13:12.49#ibcon#about to write, iclass 40, count 0 2006.224.08:13:12.49#ibcon#wrote, iclass 40, count 0 2006.224.08:13:12.49#ibcon#about to read 3, iclass 40, count 0 2006.224.08:13:12.52#ibcon#read 3, iclass 40, count 0 2006.224.08:13:12.52#ibcon#about to read 4, iclass 40, count 0 2006.224.08:13:12.52#ibcon#read 4, iclass 40, count 0 2006.224.08:13:12.52#ibcon#about to read 5, iclass 40, count 0 2006.224.08:13:12.52#ibcon#read 5, iclass 40, count 0 2006.224.08:13:12.52#ibcon#about to read 6, iclass 40, count 0 2006.224.08:13:12.52#ibcon#read 6, iclass 40, count 0 2006.224.08:13:12.52#ibcon#end of sib2, iclass 40, count 0 2006.224.08:13:12.52#ibcon#*after write, iclass 40, count 0 2006.224.08:13:12.52#ibcon#*before return 0, iclass 40, count 0 2006.224.08:13:12.52#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.224.08:13:12.52#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.224.08:13:12.52#ibcon#about to clear, iclass 40 cls_cnt 0 2006.224.08:13:12.52#ibcon#cleared, iclass 40 cls_cnt 0 2006.224.08:13:12.52$vc4f8/vabw=wide 2006.224.08:13:12.52#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.224.08:13:12.52#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.224.08:13:12.52#ibcon#ireg 8 cls_cnt 0 2006.224.08:13:12.52#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.224.08:13:12.52#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.224.08:13:12.52#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.224.08:13:12.52#ibcon#enter wrdev, iclass 4, count 0 2006.224.08:13:12.52#ibcon#first serial, iclass 4, count 0 2006.224.08:13:12.52#ibcon#enter sib2, iclass 4, count 0 2006.224.08:13:12.52#ibcon#flushed, iclass 4, count 0 2006.224.08:13:12.52#ibcon#about to write, iclass 4, count 0 2006.224.08:13:12.52#ibcon#wrote, iclass 4, count 0 2006.224.08:13:12.52#ibcon#about to read 3, iclass 4, count 0 2006.224.08:13:12.54#ibcon#read 3, iclass 4, count 0 2006.224.08:13:12.54#ibcon#about to read 4, iclass 4, count 0 2006.224.08:13:12.54#ibcon#read 4, iclass 4, count 0 2006.224.08:13:12.54#ibcon#about to read 5, iclass 4, count 0 2006.224.08:13:12.54#ibcon#read 5, iclass 4, count 0 2006.224.08:13:12.54#ibcon#about to read 6, iclass 4, count 0 2006.224.08:13:12.54#ibcon#read 6, iclass 4, count 0 2006.224.08:13:12.54#ibcon#end of sib2, iclass 4, count 0 2006.224.08:13:12.54#ibcon#*mode == 0, iclass 4, count 0 2006.224.08:13:12.54#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.224.08:13:12.54#ibcon#[25=BW32\r\n] 2006.224.08:13:12.54#ibcon#*before write, iclass 4, count 0 2006.224.08:13:12.54#ibcon#enter sib2, iclass 4, count 0 2006.224.08:13:12.54#ibcon#flushed, iclass 4, count 0 2006.224.08:13:12.54#ibcon#about to write, iclass 4, count 0 2006.224.08:13:12.54#ibcon#wrote, iclass 4, count 0 2006.224.08:13:12.54#ibcon#about to read 3, iclass 4, count 0 2006.224.08:13:12.57#ibcon#read 3, iclass 4, count 0 2006.224.08:13:12.57#ibcon#about to read 4, iclass 4, count 0 2006.224.08:13:12.57#ibcon#read 4, iclass 4, count 0 2006.224.08:13:12.57#ibcon#about to read 5, iclass 4, count 0 2006.224.08:13:12.57#ibcon#read 5, iclass 4, count 0 2006.224.08:13:12.57#ibcon#about to read 6, iclass 4, count 0 2006.224.08:13:12.57#ibcon#read 6, iclass 4, count 0 2006.224.08:13:12.57#ibcon#end of sib2, iclass 4, count 0 2006.224.08:13:12.57#ibcon#*after write, iclass 4, count 0 2006.224.08:13:12.57#ibcon#*before return 0, iclass 4, count 0 2006.224.08:13:12.57#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.224.08:13:12.57#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.224.08:13:12.57#ibcon#about to clear, iclass 4 cls_cnt 0 2006.224.08:13:12.57#ibcon#cleared, iclass 4 cls_cnt 0 2006.224.08:13:12.57$vc4f8/vbbw=wide 2006.224.08:13:12.57#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.224.08:13:12.57#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.224.08:13:12.57#ibcon#ireg 8 cls_cnt 0 2006.224.08:13:12.57#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.224.08:13:12.64#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.224.08:13:12.64#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.224.08:13:12.64#ibcon#enter wrdev, iclass 6, count 0 2006.224.08:13:12.64#ibcon#first serial, iclass 6, count 0 2006.224.08:13:12.64#ibcon#enter sib2, iclass 6, count 0 2006.224.08:13:12.64#ibcon#flushed, iclass 6, count 0 2006.224.08:13:12.64#ibcon#about to write, iclass 6, count 0 2006.224.08:13:12.64#ibcon#wrote, iclass 6, count 0 2006.224.08:13:12.64#ibcon#about to read 3, iclass 6, count 0 2006.224.08:13:12.66#ibcon#read 3, iclass 6, count 0 2006.224.08:13:12.66#ibcon#about to read 4, iclass 6, count 0 2006.224.08:13:12.66#ibcon#read 4, iclass 6, count 0 2006.224.08:13:12.66#ibcon#about to read 5, iclass 6, count 0 2006.224.08:13:12.66#ibcon#read 5, iclass 6, count 0 2006.224.08:13:12.66#ibcon#about to read 6, iclass 6, count 0 2006.224.08:13:12.66#ibcon#read 6, iclass 6, count 0 2006.224.08:13:12.66#ibcon#end of sib2, iclass 6, count 0 2006.224.08:13:12.66#ibcon#*mode == 0, iclass 6, count 0 2006.224.08:13:12.66#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.224.08:13:12.66#ibcon#[27=BW32\r\n] 2006.224.08:13:12.66#ibcon#*before write, iclass 6, count 0 2006.224.08:13:12.66#ibcon#enter sib2, iclass 6, count 0 2006.224.08:13:12.66#ibcon#flushed, iclass 6, count 0 2006.224.08:13:12.66#ibcon#about to write, iclass 6, count 0 2006.224.08:13:12.66#ibcon#wrote, iclass 6, count 0 2006.224.08:13:12.66#ibcon#about to read 3, iclass 6, count 0 2006.224.08:13:12.69#ibcon#read 3, iclass 6, count 0 2006.224.08:13:12.69#ibcon#about to read 4, iclass 6, count 0 2006.224.08:13:12.69#ibcon#read 4, iclass 6, count 0 2006.224.08:13:12.69#ibcon#about to read 5, iclass 6, count 0 2006.224.08:13:12.69#ibcon#read 5, iclass 6, count 0 2006.224.08:13:12.69#ibcon#about to read 6, iclass 6, count 0 2006.224.08:13:12.69#ibcon#read 6, iclass 6, count 0 2006.224.08:13:12.69#ibcon#end of sib2, iclass 6, count 0 2006.224.08:13:12.69#ibcon#*after write, iclass 6, count 0 2006.224.08:13:12.69#ibcon#*before return 0, iclass 6, count 0 2006.224.08:13:12.69#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.224.08:13:12.69#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.224.08:13:12.69#ibcon#about to clear, iclass 6 cls_cnt 0 2006.224.08:13:12.69#ibcon#cleared, iclass 6 cls_cnt 0 2006.224.08:13:12.69$4f8m12a/ifd4f 2006.224.08:13:12.69$ifd4f/lo= 2006.224.08:13:12.69$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.224.08:13:12.69$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.224.08:13:12.69$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.224.08:13:12.69$ifd4f/patch= 2006.224.08:13:12.69$ifd4f/patch=lo1,a1,a2,a3,a4 2006.224.08:13:12.69$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.224.08:13:12.69$ifd4f/patch=lo3,a5,a6,a7,a8 2006.224.08:13:12.69$4f8m12a/"form=m,16.000,1:2 2006.224.08:13:12.69$4f8m12a/"tpicd 2006.224.08:13:12.69$4f8m12a/echo=off 2006.224.08:13:12.69$4f8m12a/xlog=off 2006.224.08:13:12.69:!2006.224.08:14:00 2006.224.08:13:38.14#trakl#Source acquired 2006.224.08:13:40.14#flagr#flagr/antenna,acquired 2006.224.08:14:00.00:preob 2006.224.08:14:00.14/onsource/TRACKING 2006.224.08:14:00.14:!2006.224.08:14:10 2006.224.08:14:10.00:data_valid=on 2006.224.08:14:10.00:midob 2006.224.08:14:10.14/onsource/TRACKING 2006.224.08:14:10.14/wx/23.79,1004.7,100 2006.224.08:14:10.27/cable/+6.4358E-03 2006.224.08:14:11.36/va/01,08,usb,yes,44,46 2006.224.08:14:11.36/va/02,07,usb,yes,45,47 2006.224.08:14:11.36/va/03,06,usb,yes,48,48 2006.224.08:14:11.36/va/04,07,usb,yes,46,50 2006.224.08:14:11.36/va/05,07,usb,yes,53,56 2006.224.08:14:11.36/va/06,06,usb,yes,53,52 2006.224.08:14:11.36/va/07,06,usb,yes,53,53 2006.224.08:14:11.36/va/08,07,usb,yes,51,50 2006.224.08:14:11.59/valo/01,532.99,yes,locked 2006.224.08:14:11.59/valo/02,572.99,yes,locked 2006.224.08:14:11.59/valo/03,672.99,yes,locked 2006.224.08:14:11.59/valo/04,832.99,yes,locked 2006.224.08:14:11.59/valo/05,652.99,yes,locked 2006.224.08:14:11.59/valo/06,772.99,yes,locked 2006.224.08:14:11.59/valo/07,832.99,yes,locked 2006.224.08:14:11.59/valo/08,852.99,yes,locked 2006.224.08:14:12.68/vb/01,04,usb,yes,32,30 2006.224.08:14:12.68/vb/02,04,usb,yes,33,35 2006.224.08:14:12.68/vb/03,04,usb,yes,30,34 2006.224.08:14:12.68/vb/04,04,usb,yes,31,31 2006.224.08:14:12.68/vb/05,04,usb,yes,29,33 2006.224.08:14:12.68/vb/06,04,usb,yes,30,33 2006.224.08:14:12.68/vb/07,04,usb,yes,33,32 2006.224.08:14:12.68/vb/08,04,usb,yes,30,33 2006.224.08:14:12.91/vblo/01,632.99,yes,locked 2006.224.08:14:12.91/vblo/02,640.99,yes,locked 2006.224.08:14:12.91/vblo/03,656.99,yes,locked 2006.224.08:14:12.91/vblo/04,712.99,yes,locked 2006.224.08:14:12.91/vblo/05,744.99,yes,locked 2006.224.08:14:12.91/vblo/06,752.99,yes,locked 2006.224.08:14:12.91/vblo/07,734.99,yes,locked 2006.224.08:14:12.91/vblo/08,744.99,yes,locked 2006.224.08:14:13.06/vabw/8 2006.224.08:14:13.21/vbbw/8 2006.224.08:14:13.30/xfe/off,on,15.0 2006.224.08:14:13.67/ifatt/23,28,28,28 2006.224.08:14:14.08/fmout-gps/S +4.56E-07 2006.224.08:14:14.12:!2006.224.08:15:20 2006.224.08:15:20.00:data_valid=off 2006.224.08:15:20.00:postob 2006.224.08:15:20.19/cable/+6.4353E-03 2006.224.08:15:20.19/wx/23.79,1004.6,100 2006.224.08:15:21.08/fmout-gps/S +4.57E-07 2006.224.08:15:21.08:scan_name=224-0816,k06224,60 2006.224.08:15:21.08:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.224.08:15:22.14#flagr#flagr/antenna,new-source 2006.224.08:15:22.14:checkk5 2006.224.08:15:22.51/chk_autoobs//k5ts1/ autoobs is running! 2006.224.08:15:22.88/chk_autoobs//k5ts2/ autoobs is running! 2006.224.08:15:23.25/chk_autoobs//k5ts3/ autoobs is running! 2006.224.08:15:23.62/chk_autoobs//k5ts4/ autoobs is running! 2006.224.08:15:23.98/chk_obsdata//k5ts1/T2240814??a.dat file size is correct (nominal:560MB, actual:552MB). 2006.224.08:15:24.34/chk_obsdata//k5ts2/T2240814??b.dat file size is correct (nominal:560MB, actual:552MB). 2006.224.08:15:24.71/chk_obsdata//k5ts3/T2240814??c.dat file size is correct (nominal:560MB, actual:552MB). 2006.224.08:15:25.07/chk_obsdata//k5ts4/T2240814??d.dat file size is correct (nominal:560MB, actual:552MB). 2006.224.08:15:25.77/k5log//k5ts1_log_newline 2006.224.08:15:26.47/k5log//k5ts2_log_newline 2006.224.08:15:27.17/k5log//k5ts3_log_newline 2006.224.08:15:27.86/k5log//k5ts4_log_newline 2006.224.08:15:27.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.224.08:15:27.88:4f8m12a=2 2006.224.08:15:27.89$4f8m12a/echo=on 2006.224.08:15:27.89$4f8m12a/pcalon 2006.224.08:15:27.89$pcalon/"no phase cal control is implemented here 2006.224.08:15:27.89$4f8m12a/"tpicd=stop 2006.224.08:15:27.89$4f8m12a/vc4f8 2006.224.08:15:27.89$vc4f8/valo=1,532.99 2006.224.08:15:27.89#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.224.08:15:27.89#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.224.08:15:27.89#ibcon#ireg 17 cls_cnt 0 2006.224.08:15:27.89#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.224.08:15:27.89#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.224.08:15:27.89#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.224.08:15:27.89#ibcon#enter wrdev, iclass 27, count 0 2006.224.08:15:27.89#ibcon#first serial, iclass 27, count 0 2006.224.08:15:27.89#ibcon#enter sib2, iclass 27, count 0 2006.224.08:15:27.89#ibcon#flushed, iclass 27, count 0 2006.224.08:15:27.89#ibcon#about to write, iclass 27, count 0 2006.224.08:15:27.89#ibcon#wrote, iclass 27, count 0 2006.224.08:15:27.89#ibcon#about to read 3, iclass 27, count 0 2006.224.08:15:27.93#ibcon#read 3, iclass 27, count 0 2006.224.08:15:27.93#ibcon#about to read 4, iclass 27, count 0 2006.224.08:15:27.93#ibcon#read 4, iclass 27, count 0 2006.224.08:15:27.93#ibcon#about to read 5, iclass 27, count 0 2006.224.08:15:27.93#ibcon#read 5, iclass 27, count 0 2006.224.08:15:27.93#ibcon#about to read 6, iclass 27, count 0 2006.224.08:15:27.93#ibcon#read 6, iclass 27, count 0 2006.224.08:15:27.93#ibcon#end of sib2, iclass 27, count 0 2006.224.08:15:27.93#ibcon#*mode == 0, iclass 27, count 0 2006.224.08:15:27.93#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.224.08:15:27.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.224.08:15:27.93#ibcon#*before write, iclass 27, count 0 2006.224.08:15:27.93#ibcon#enter sib2, iclass 27, count 0 2006.224.08:15:27.93#ibcon#flushed, iclass 27, count 0 2006.224.08:15:27.93#ibcon#about to write, iclass 27, count 0 2006.224.08:15:27.93#ibcon#wrote, iclass 27, count 0 2006.224.08:15:27.93#ibcon#about to read 3, iclass 27, count 0 2006.224.08:15:27.98#ibcon#read 3, iclass 27, count 0 2006.224.08:15:27.98#ibcon#about to read 4, iclass 27, count 0 2006.224.08:15:27.98#ibcon#read 4, iclass 27, count 0 2006.224.08:15:27.98#ibcon#about to read 5, iclass 27, count 0 2006.224.08:15:27.98#ibcon#read 5, iclass 27, count 0 2006.224.08:15:27.98#ibcon#about to read 6, iclass 27, count 0 2006.224.08:15:27.98#ibcon#read 6, iclass 27, count 0 2006.224.08:15:27.98#ibcon#end of sib2, iclass 27, count 0 2006.224.08:15:27.98#ibcon#*after write, iclass 27, count 0 2006.224.08:15:27.98#ibcon#*before return 0, iclass 27, count 0 2006.224.08:15:27.98#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.224.08:15:27.98#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.224.08:15:27.98#ibcon#about to clear, iclass 27 cls_cnt 0 2006.224.08:15:27.98#ibcon#cleared, iclass 27 cls_cnt 0 2006.224.08:15:27.98$vc4f8/va=1,8 2006.224.08:15:27.98#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.224.08:15:27.98#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.224.08:15:27.98#ibcon#ireg 11 cls_cnt 2 2006.224.08:15:27.98#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.224.08:15:27.98#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.224.08:15:27.98#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.224.08:15:27.98#ibcon#enter wrdev, iclass 29, count 2 2006.224.08:15:27.98#ibcon#first serial, iclass 29, count 2 2006.224.08:15:27.98#ibcon#enter sib2, iclass 29, count 2 2006.224.08:15:27.98#ibcon#flushed, iclass 29, count 2 2006.224.08:15:27.98#ibcon#about to write, iclass 29, count 2 2006.224.08:15:27.98#ibcon#wrote, iclass 29, count 2 2006.224.08:15:27.98#ibcon#about to read 3, iclass 29, count 2 2006.224.08:15:28.00#ibcon#read 3, iclass 29, count 2 2006.224.08:15:28.00#ibcon#about to read 4, iclass 29, count 2 2006.224.08:15:28.00#ibcon#read 4, iclass 29, count 2 2006.224.08:15:28.00#ibcon#about to read 5, iclass 29, count 2 2006.224.08:15:28.00#ibcon#read 5, iclass 29, count 2 2006.224.08:15:28.00#ibcon#about to read 6, iclass 29, count 2 2006.224.08:15:28.00#ibcon#read 6, iclass 29, count 2 2006.224.08:15:28.00#ibcon#end of sib2, iclass 29, count 2 2006.224.08:15:28.00#ibcon#*mode == 0, iclass 29, count 2 2006.224.08:15:28.00#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.224.08:15:28.00#ibcon#[25=AT01-08\r\n] 2006.224.08:15:28.00#ibcon#*before write, iclass 29, count 2 2006.224.08:15:28.00#ibcon#enter sib2, iclass 29, count 2 2006.224.08:15:28.00#ibcon#flushed, iclass 29, count 2 2006.224.08:15:28.00#ibcon#about to write, iclass 29, count 2 2006.224.08:15:28.00#ibcon#wrote, iclass 29, count 2 2006.224.08:15:28.00#ibcon#about to read 3, iclass 29, count 2 2006.224.08:15:28.03#ibcon#read 3, iclass 29, count 2 2006.224.08:15:28.03#ibcon#about to read 4, iclass 29, count 2 2006.224.08:15:28.03#ibcon#read 4, iclass 29, count 2 2006.224.08:15:28.03#ibcon#about to read 5, iclass 29, count 2 2006.224.08:15:28.03#ibcon#read 5, iclass 29, count 2 2006.224.08:15:28.03#ibcon#about to read 6, iclass 29, count 2 2006.224.08:15:28.03#ibcon#read 6, iclass 29, count 2 2006.224.08:15:28.03#ibcon#end of sib2, iclass 29, count 2 2006.224.08:15:28.03#ibcon#*after write, iclass 29, count 2 2006.224.08:15:28.03#ibcon#*before return 0, iclass 29, count 2 2006.224.08:15:28.03#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.224.08:15:28.03#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.224.08:15:28.03#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.224.08:15:28.03#ibcon#ireg 7 cls_cnt 0 2006.224.08:15:28.03#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.224.08:15:28.15#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.224.08:15:28.15#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.224.08:15:28.15#ibcon#enter wrdev, iclass 29, count 0 2006.224.08:15:28.15#ibcon#first serial, iclass 29, count 0 2006.224.08:15:28.15#ibcon#enter sib2, iclass 29, count 0 2006.224.08:15:28.15#ibcon#flushed, iclass 29, count 0 2006.224.08:15:28.15#ibcon#about to write, iclass 29, count 0 2006.224.08:15:28.15#ibcon#wrote, iclass 29, count 0 2006.224.08:15:28.15#ibcon#about to read 3, iclass 29, count 0 2006.224.08:15:28.17#ibcon#read 3, iclass 29, count 0 2006.224.08:15:28.17#ibcon#about to read 4, iclass 29, count 0 2006.224.08:15:28.17#ibcon#read 4, iclass 29, count 0 2006.224.08:15:28.17#ibcon#about to read 5, iclass 29, count 0 2006.224.08:15:28.17#ibcon#read 5, iclass 29, count 0 2006.224.08:15:28.17#ibcon#about to read 6, iclass 29, count 0 2006.224.08:15:28.17#ibcon#read 6, iclass 29, count 0 2006.224.08:15:28.17#ibcon#end of sib2, iclass 29, count 0 2006.224.08:15:28.17#ibcon#*mode == 0, iclass 29, count 0 2006.224.08:15:28.17#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.224.08:15:28.17#ibcon#[25=USB\r\n] 2006.224.08:15:28.17#ibcon#*before write, iclass 29, count 0 2006.224.08:15:28.17#ibcon#enter sib2, iclass 29, count 0 2006.224.08:15:28.17#ibcon#flushed, iclass 29, count 0 2006.224.08:15:28.17#ibcon#about to write, iclass 29, count 0 2006.224.08:15:28.17#ibcon#wrote, iclass 29, count 0 2006.224.08:15:28.17#ibcon#about to read 3, iclass 29, count 0 2006.224.08:15:28.20#ibcon#read 3, iclass 29, count 0 2006.224.08:15:28.20#ibcon#about to read 4, iclass 29, count 0 2006.224.08:15:28.20#ibcon#read 4, iclass 29, count 0 2006.224.08:15:28.20#ibcon#about to read 5, iclass 29, count 0 2006.224.08:15:28.20#ibcon#read 5, iclass 29, count 0 2006.224.08:15:28.20#ibcon#about to read 6, iclass 29, count 0 2006.224.08:15:28.20#ibcon#read 6, iclass 29, count 0 2006.224.08:15:28.20#ibcon#end of sib2, iclass 29, count 0 2006.224.08:15:28.20#ibcon#*after write, iclass 29, count 0 2006.224.08:15:28.20#ibcon#*before return 0, iclass 29, count 0 2006.224.08:15:28.20#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.224.08:15:28.20#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.224.08:15:28.20#ibcon#about to clear, iclass 29 cls_cnt 0 2006.224.08:15:28.20#ibcon#cleared, iclass 29 cls_cnt 0 2006.224.08:15:28.20$vc4f8/valo=2,572.99 2006.224.08:15:28.20#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.224.08:15:28.20#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.224.08:15:28.20#ibcon#ireg 17 cls_cnt 0 2006.224.08:15:28.20#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.224.08:15:28.20#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.224.08:15:28.20#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.224.08:15:28.20#ibcon#enter wrdev, iclass 31, count 0 2006.224.08:15:28.20#ibcon#first serial, iclass 31, count 0 2006.224.08:15:28.20#ibcon#enter sib2, iclass 31, count 0 2006.224.08:15:28.20#ibcon#flushed, iclass 31, count 0 2006.224.08:15:28.20#ibcon#about to write, iclass 31, count 0 2006.224.08:15:28.20#ibcon#wrote, iclass 31, count 0 2006.224.08:15:28.20#ibcon#about to read 3, iclass 31, count 0 2006.224.08:15:28.22#ibcon#read 3, iclass 31, count 0 2006.224.08:15:28.22#ibcon#about to read 4, iclass 31, count 0 2006.224.08:15:28.22#ibcon#read 4, iclass 31, count 0 2006.224.08:15:28.22#ibcon#about to read 5, iclass 31, count 0 2006.224.08:15:28.22#ibcon#read 5, iclass 31, count 0 2006.224.08:15:28.22#ibcon#about to read 6, iclass 31, count 0 2006.224.08:15:28.22#ibcon#read 6, iclass 31, count 0 2006.224.08:15:28.22#ibcon#end of sib2, iclass 31, count 0 2006.224.08:15:28.22#ibcon#*mode == 0, iclass 31, count 0 2006.224.08:15:28.22#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.224.08:15:28.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.224.08:15:28.22#ibcon#*before write, iclass 31, count 0 2006.224.08:15:28.22#ibcon#enter sib2, iclass 31, count 0 2006.224.08:15:28.22#ibcon#flushed, iclass 31, count 0 2006.224.08:15:28.22#ibcon#about to write, iclass 31, count 0 2006.224.08:15:28.22#ibcon#wrote, iclass 31, count 0 2006.224.08:15:28.22#ibcon#about to read 3, iclass 31, count 0 2006.224.08:15:28.26#ibcon#read 3, iclass 31, count 0 2006.224.08:15:28.26#ibcon#about to read 4, iclass 31, count 0 2006.224.08:15:28.26#ibcon#read 4, iclass 31, count 0 2006.224.08:15:28.26#ibcon#about to read 5, iclass 31, count 0 2006.224.08:15:28.26#ibcon#read 5, iclass 31, count 0 2006.224.08:15:28.26#ibcon#about to read 6, iclass 31, count 0 2006.224.08:15:28.26#ibcon#read 6, iclass 31, count 0 2006.224.08:15:28.26#ibcon#end of sib2, iclass 31, count 0 2006.224.08:15:28.26#ibcon#*after write, iclass 31, count 0 2006.224.08:15:28.26#ibcon#*before return 0, iclass 31, count 0 2006.224.08:15:28.26#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.224.08:15:28.26#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.224.08:15:28.26#ibcon#about to clear, iclass 31 cls_cnt 0 2006.224.08:15:28.26#ibcon#cleared, iclass 31 cls_cnt 0 2006.224.08:15:28.26$vc4f8/va=2,7 2006.224.08:15:28.26#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.224.08:15:28.26#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.224.08:15:28.26#ibcon#ireg 11 cls_cnt 2 2006.224.08:15:28.26#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.224.08:15:28.32#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.224.08:15:28.32#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.224.08:15:28.32#ibcon#enter wrdev, iclass 33, count 2 2006.224.08:15:28.32#ibcon#first serial, iclass 33, count 2 2006.224.08:15:28.32#ibcon#enter sib2, iclass 33, count 2 2006.224.08:15:28.32#ibcon#flushed, iclass 33, count 2 2006.224.08:15:28.32#ibcon#about to write, iclass 33, count 2 2006.224.08:15:28.32#ibcon#wrote, iclass 33, count 2 2006.224.08:15:28.32#ibcon#about to read 3, iclass 33, count 2 2006.224.08:15:28.34#ibcon#read 3, iclass 33, count 2 2006.224.08:15:28.34#ibcon#about to read 4, iclass 33, count 2 2006.224.08:15:28.34#ibcon#read 4, iclass 33, count 2 2006.224.08:15:28.34#ibcon#about to read 5, iclass 33, count 2 2006.224.08:15:28.34#ibcon#read 5, iclass 33, count 2 2006.224.08:15:28.34#ibcon#about to read 6, iclass 33, count 2 2006.224.08:15:28.34#ibcon#read 6, iclass 33, count 2 2006.224.08:15:28.34#ibcon#end of sib2, iclass 33, count 2 2006.224.08:15:28.34#ibcon#*mode == 0, iclass 33, count 2 2006.224.08:15:28.34#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.224.08:15:28.34#ibcon#[25=AT02-07\r\n] 2006.224.08:15:28.34#ibcon#*before write, iclass 33, count 2 2006.224.08:15:28.34#ibcon#enter sib2, iclass 33, count 2 2006.224.08:15:28.34#ibcon#flushed, iclass 33, count 2 2006.224.08:15:28.34#ibcon#about to write, iclass 33, count 2 2006.224.08:15:28.34#ibcon#wrote, iclass 33, count 2 2006.224.08:15:28.34#ibcon#about to read 3, iclass 33, count 2 2006.224.08:15:28.37#ibcon#read 3, iclass 33, count 2 2006.224.08:15:28.37#ibcon#about to read 4, iclass 33, count 2 2006.224.08:15:28.37#ibcon#read 4, iclass 33, count 2 2006.224.08:15:28.37#ibcon#about to read 5, iclass 33, count 2 2006.224.08:15:28.37#ibcon#read 5, iclass 33, count 2 2006.224.08:15:28.37#ibcon#about to read 6, iclass 33, count 2 2006.224.08:15:28.37#ibcon#read 6, iclass 33, count 2 2006.224.08:15:28.37#ibcon#end of sib2, iclass 33, count 2 2006.224.08:15:28.37#ibcon#*after write, iclass 33, count 2 2006.224.08:15:28.37#ibcon#*before return 0, iclass 33, count 2 2006.224.08:15:28.37#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.224.08:15:28.37#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.224.08:15:28.37#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.224.08:15:28.37#ibcon#ireg 7 cls_cnt 0 2006.224.08:15:28.37#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.224.08:15:28.49#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.224.08:15:28.49#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.224.08:15:28.49#ibcon#enter wrdev, iclass 33, count 0 2006.224.08:15:28.49#ibcon#first serial, iclass 33, count 0 2006.224.08:15:28.49#ibcon#enter sib2, iclass 33, count 0 2006.224.08:15:28.49#ibcon#flushed, iclass 33, count 0 2006.224.08:15:28.49#ibcon#about to write, iclass 33, count 0 2006.224.08:15:28.49#ibcon#wrote, iclass 33, count 0 2006.224.08:15:28.49#ibcon#about to read 3, iclass 33, count 0 2006.224.08:15:28.51#ibcon#read 3, iclass 33, count 0 2006.224.08:15:28.51#ibcon#about to read 4, iclass 33, count 0 2006.224.08:15:28.51#ibcon#read 4, iclass 33, count 0 2006.224.08:15:28.51#ibcon#about to read 5, iclass 33, count 0 2006.224.08:15:28.51#ibcon#read 5, iclass 33, count 0 2006.224.08:15:28.51#ibcon#about to read 6, iclass 33, count 0 2006.224.08:15:28.51#ibcon#read 6, iclass 33, count 0 2006.224.08:15:28.51#ibcon#end of sib2, iclass 33, count 0 2006.224.08:15:28.51#ibcon#*mode == 0, iclass 33, count 0 2006.224.08:15:28.51#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.224.08:15:28.51#ibcon#[25=USB\r\n] 2006.224.08:15:28.51#ibcon#*before write, iclass 33, count 0 2006.224.08:15:28.51#ibcon#enter sib2, iclass 33, count 0 2006.224.08:15:28.51#ibcon#flushed, iclass 33, count 0 2006.224.08:15:28.51#ibcon#about to write, iclass 33, count 0 2006.224.08:15:28.51#ibcon#wrote, iclass 33, count 0 2006.224.08:15:28.51#ibcon#about to read 3, iclass 33, count 0 2006.224.08:15:28.54#ibcon#read 3, iclass 33, count 0 2006.224.08:15:28.54#ibcon#about to read 4, iclass 33, count 0 2006.224.08:15:28.54#ibcon#read 4, iclass 33, count 0 2006.224.08:15:28.54#ibcon#about to read 5, iclass 33, count 0 2006.224.08:15:28.54#ibcon#read 5, iclass 33, count 0 2006.224.08:15:28.54#ibcon#about to read 6, iclass 33, count 0 2006.224.08:15:28.54#ibcon#read 6, iclass 33, count 0 2006.224.08:15:28.54#ibcon#end of sib2, iclass 33, count 0 2006.224.08:15:28.54#ibcon#*after write, iclass 33, count 0 2006.224.08:15:28.54#ibcon#*before return 0, iclass 33, count 0 2006.224.08:15:28.54#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.224.08:15:28.54#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.224.08:15:28.54#ibcon#about to clear, iclass 33 cls_cnt 0 2006.224.08:15:28.54#ibcon#cleared, iclass 33 cls_cnt 0 2006.224.08:15:28.54$vc4f8/valo=3,672.99 2006.224.08:15:28.54#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.224.08:15:28.54#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.224.08:15:28.54#ibcon#ireg 17 cls_cnt 0 2006.224.08:15:28.54#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.224.08:15:28.54#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.224.08:15:28.54#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.224.08:15:28.54#ibcon#enter wrdev, iclass 35, count 0 2006.224.08:15:28.54#ibcon#first serial, iclass 35, count 0 2006.224.08:15:28.54#ibcon#enter sib2, iclass 35, count 0 2006.224.08:15:28.54#ibcon#flushed, iclass 35, count 0 2006.224.08:15:28.54#ibcon#about to write, iclass 35, count 0 2006.224.08:15:28.54#ibcon#wrote, iclass 35, count 0 2006.224.08:15:28.54#ibcon#about to read 3, iclass 35, count 0 2006.224.08:15:28.56#ibcon#read 3, iclass 35, count 0 2006.224.08:15:28.56#ibcon#about to read 4, iclass 35, count 0 2006.224.08:15:28.56#ibcon#read 4, iclass 35, count 0 2006.224.08:15:28.56#ibcon#about to read 5, iclass 35, count 0 2006.224.08:15:28.56#ibcon#read 5, iclass 35, count 0 2006.224.08:15:28.56#ibcon#about to read 6, iclass 35, count 0 2006.224.08:15:28.56#ibcon#read 6, iclass 35, count 0 2006.224.08:15:28.56#ibcon#end of sib2, iclass 35, count 0 2006.224.08:15:28.56#ibcon#*mode == 0, iclass 35, count 0 2006.224.08:15:28.56#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.224.08:15:28.56#ibcon#[26=FRQ=03,672.99\r\n] 2006.224.08:15:28.56#ibcon#*before write, iclass 35, count 0 2006.224.08:15:28.56#ibcon#enter sib2, iclass 35, count 0 2006.224.08:15:28.56#ibcon#flushed, iclass 35, count 0 2006.224.08:15:28.56#ibcon#about to write, iclass 35, count 0 2006.224.08:15:28.56#ibcon#wrote, iclass 35, count 0 2006.224.08:15:28.56#ibcon#about to read 3, iclass 35, count 0 2006.224.08:15:28.60#ibcon#read 3, iclass 35, count 0 2006.224.08:15:28.60#ibcon#about to read 4, iclass 35, count 0 2006.224.08:15:28.60#ibcon#read 4, iclass 35, count 0 2006.224.08:15:28.60#ibcon#about to read 5, iclass 35, count 0 2006.224.08:15:28.60#ibcon#read 5, iclass 35, count 0 2006.224.08:15:28.60#ibcon#about to read 6, iclass 35, count 0 2006.224.08:15:28.60#ibcon#read 6, iclass 35, count 0 2006.224.08:15:28.60#ibcon#end of sib2, iclass 35, count 0 2006.224.08:15:28.60#ibcon#*after write, iclass 35, count 0 2006.224.08:15:28.60#ibcon#*before return 0, iclass 35, count 0 2006.224.08:15:28.60#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.224.08:15:28.60#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.224.08:15:28.60#ibcon#about to clear, iclass 35 cls_cnt 0 2006.224.08:15:28.60#ibcon#cleared, iclass 35 cls_cnt 0 2006.224.08:15:28.60$vc4f8/va=3,6 2006.224.08:15:28.60#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.224.08:15:28.60#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.224.08:15:28.60#ibcon#ireg 11 cls_cnt 2 2006.224.08:15:28.60#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.224.08:15:28.66#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.224.08:15:28.66#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.224.08:15:28.66#ibcon#enter wrdev, iclass 37, count 2 2006.224.08:15:28.66#ibcon#first serial, iclass 37, count 2 2006.224.08:15:28.66#ibcon#enter sib2, iclass 37, count 2 2006.224.08:15:28.66#ibcon#flushed, iclass 37, count 2 2006.224.08:15:28.66#ibcon#about to write, iclass 37, count 2 2006.224.08:15:28.66#ibcon#wrote, iclass 37, count 2 2006.224.08:15:28.66#ibcon#about to read 3, iclass 37, count 2 2006.224.08:15:28.68#ibcon#read 3, iclass 37, count 2 2006.224.08:15:28.68#ibcon#about to read 4, iclass 37, count 2 2006.224.08:15:28.68#ibcon#read 4, iclass 37, count 2 2006.224.08:15:28.68#ibcon#about to read 5, iclass 37, count 2 2006.224.08:15:28.68#ibcon#read 5, iclass 37, count 2 2006.224.08:15:28.68#ibcon#about to read 6, iclass 37, count 2 2006.224.08:15:28.68#ibcon#read 6, iclass 37, count 2 2006.224.08:15:28.68#ibcon#end of sib2, iclass 37, count 2 2006.224.08:15:28.68#ibcon#*mode == 0, iclass 37, count 2 2006.224.08:15:28.68#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.224.08:15:28.68#ibcon#[25=AT03-06\r\n] 2006.224.08:15:28.68#ibcon#*before write, iclass 37, count 2 2006.224.08:15:28.68#ibcon#enter sib2, iclass 37, count 2 2006.224.08:15:28.68#ibcon#flushed, iclass 37, count 2 2006.224.08:15:28.68#ibcon#about to write, iclass 37, count 2 2006.224.08:15:28.68#ibcon#wrote, iclass 37, count 2 2006.224.08:15:28.68#ibcon#about to read 3, iclass 37, count 2 2006.224.08:15:28.71#ibcon#read 3, iclass 37, count 2 2006.224.08:15:28.71#ibcon#about to read 4, iclass 37, count 2 2006.224.08:15:28.71#ibcon#read 4, iclass 37, count 2 2006.224.08:15:28.71#ibcon#about to read 5, iclass 37, count 2 2006.224.08:15:28.71#ibcon#read 5, iclass 37, count 2 2006.224.08:15:28.71#ibcon#about to read 6, iclass 37, count 2 2006.224.08:15:28.71#ibcon#read 6, iclass 37, count 2 2006.224.08:15:28.71#ibcon#end of sib2, iclass 37, count 2 2006.224.08:15:28.71#ibcon#*after write, iclass 37, count 2 2006.224.08:15:28.71#ibcon#*before return 0, iclass 37, count 2 2006.224.08:15:28.71#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.224.08:15:28.71#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.224.08:15:28.71#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.224.08:15:28.71#ibcon#ireg 7 cls_cnt 0 2006.224.08:15:28.71#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.224.08:15:28.83#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.224.08:15:28.83#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.224.08:15:28.83#ibcon#enter wrdev, iclass 37, count 0 2006.224.08:15:28.83#ibcon#first serial, iclass 37, count 0 2006.224.08:15:28.83#ibcon#enter sib2, iclass 37, count 0 2006.224.08:15:28.83#ibcon#flushed, iclass 37, count 0 2006.224.08:15:28.83#ibcon#about to write, iclass 37, count 0 2006.224.08:15:28.83#ibcon#wrote, iclass 37, count 0 2006.224.08:15:28.83#ibcon#about to read 3, iclass 37, count 0 2006.224.08:15:28.85#ibcon#read 3, iclass 37, count 0 2006.224.08:15:28.85#ibcon#about to read 4, iclass 37, count 0 2006.224.08:15:28.85#ibcon#read 4, iclass 37, count 0 2006.224.08:15:28.85#ibcon#about to read 5, iclass 37, count 0 2006.224.08:15:28.85#ibcon#read 5, iclass 37, count 0 2006.224.08:15:28.85#ibcon#about to read 6, iclass 37, count 0 2006.224.08:15:28.85#ibcon#read 6, iclass 37, count 0 2006.224.08:15:28.85#ibcon#end of sib2, iclass 37, count 0 2006.224.08:15:28.85#ibcon#*mode == 0, iclass 37, count 0 2006.224.08:15:28.85#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.224.08:15:28.85#ibcon#[25=USB\r\n] 2006.224.08:15:28.85#ibcon#*before write, iclass 37, count 0 2006.224.08:15:28.85#ibcon#enter sib2, iclass 37, count 0 2006.224.08:15:28.85#ibcon#flushed, iclass 37, count 0 2006.224.08:15:28.85#ibcon#about to write, iclass 37, count 0 2006.224.08:15:28.85#ibcon#wrote, iclass 37, count 0 2006.224.08:15:28.85#ibcon#about to read 3, iclass 37, count 0 2006.224.08:15:28.88#ibcon#read 3, iclass 37, count 0 2006.224.08:15:28.88#ibcon#about to read 4, iclass 37, count 0 2006.224.08:15:28.88#ibcon#read 4, iclass 37, count 0 2006.224.08:15:28.88#ibcon#about to read 5, iclass 37, count 0 2006.224.08:15:28.88#ibcon#read 5, iclass 37, count 0 2006.224.08:15:28.88#ibcon#about to read 6, iclass 37, count 0 2006.224.08:15:28.88#ibcon#read 6, iclass 37, count 0 2006.224.08:15:28.88#ibcon#end of sib2, iclass 37, count 0 2006.224.08:15:28.88#ibcon#*after write, iclass 37, count 0 2006.224.08:15:28.88#ibcon#*before return 0, iclass 37, count 0 2006.224.08:15:28.88#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.224.08:15:28.88#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.224.08:15:28.88#ibcon#about to clear, iclass 37 cls_cnt 0 2006.224.08:15:28.88#ibcon#cleared, iclass 37 cls_cnt 0 2006.224.08:15:28.88$vc4f8/valo=4,832.99 2006.224.08:15:28.88#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.224.08:15:28.88#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.224.08:15:28.88#ibcon#ireg 17 cls_cnt 0 2006.224.08:15:28.88#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.224.08:15:28.88#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.224.08:15:28.88#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.224.08:15:28.88#ibcon#enter wrdev, iclass 39, count 0 2006.224.08:15:28.88#ibcon#first serial, iclass 39, count 0 2006.224.08:15:28.88#ibcon#enter sib2, iclass 39, count 0 2006.224.08:15:28.88#ibcon#flushed, iclass 39, count 0 2006.224.08:15:28.88#ibcon#about to write, iclass 39, count 0 2006.224.08:15:28.88#ibcon#wrote, iclass 39, count 0 2006.224.08:15:28.88#ibcon#about to read 3, iclass 39, count 0 2006.224.08:15:28.90#ibcon#read 3, iclass 39, count 0 2006.224.08:15:28.90#ibcon#about to read 4, iclass 39, count 0 2006.224.08:15:28.90#ibcon#read 4, iclass 39, count 0 2006.224.08:15:28.90#ibcon#about to read 5, iclass 39, count 0 2006.224.08:15:28.90#ibcon#read 5, iclass 39, count 0 2006.224.08:15:28.90#ibcon#about to read 6, iclass 39, count 0 2006.224.08:15:28.90#ibcon#read 6, iclass 39, count 0 2006.224.08:15:28.90#ibcon#end of sib2, iclass 39, count 0 2006.224.08:15:28.90#ibcon#*mode == 0, iclass 39, count 0 2006.224.08:15:28.90#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.224.08:15:28.90#ibcon#[26=FRQ=04,832.99\r\n] 2006.224.08:15:28.90#ibcon#*before write, iclass 39, count 0 2006.224.08:15:28.90#ibcon#enter sib2, iclass 39, count 0 2006.224.08:15:28.90#ibcon#flushed, iclass 39, count 0 2006.224.08:15:28.90#ibcon#about to write, iclass 39, count 0 2006.224.08:15:28.90#ibcon#wrote, iclass 39, count 0 2006.224.08:15:28.90#ibcon#about to read 3, iclass 39, count 0 2006.224.08:15:28.94#ibcon#read 3, iclass 39, count 0 2006.224.08:15:28.94#ibcon#about to read 4, iclass 39, count 0 2006.224.08:15:28.94#ibcon#read 4, iclass 39, count 0 2006.224.08:15:28.94#ibcon#about to read 5, iclass 39, count 0 2006.224.08:15:28.94#ibcon#read 5, iclass 39, count 0 2006.224.08:15:28.94#ibcon#about to read 6, iclass 39, count 0 2006.224.08:15:28.94#ibcon#read 6, iclass 39, count 0 2006.224.08:15:28.94#ibcon#end of sib2, iclass 39, count 0 2006.224.08:15:28.94#ibcon#*after write, iclass 39, count 0 2006.224.08:15:28.94#ibcon#*before return 0, iclass 39, count 0 2006.224.08:15:28.94#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.224.08:15:28.94#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.224.08:15:28.94#ibcon#about to clear, iclass 39 cls_cnt 0 2006.224.08:15:28.94#ibcon#cleared, iclass 39 cls_cnt 0 2006.224.08:15:28.94$vc4f8/va=4,7 2006.224.08:15:28.94#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.224.08:15:28.94#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.224.08:15:28.94#ibcon#ireg 11 cls_cnt 2 2006.224.08:15:28.94#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.224.08:15:29.00#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.224.08:15:29.00#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.224.08:15:29.00#ibcon#enter wrdev, iclass 3, count 2 2006.224.08:15:29.00#ibcon#first serial, iclass 3, count 2 2006.224.08:15:29.00#ibcon#enter sib2, iclass 3, count 2 2006.224.08:15:29.00#ibcon#flushed, iclass 3, count 2 2006.224.08:15:29.00#ibcon#about to write, iclass 3, count 2 2006.224.08:15:29.00#ibcon#wrote, iclass 3, count 2 2006.224.08:15:29.00#ibcon#about to read 3, iclass 3, count 2 2006.224.08:15:29.02#ibcon#read 3, iclass 3, count 2 2006.224.08:15:29.02#ibcon#about to read 4, iclass 3, count 2 2006.224.08:15:29.02#ibcon#read 4, iclass 3, count 2 2006.224.08:15:29.02#ibcon#about to read 5, iclass 3, count 2 2006.224.08:15:29.02#ibcon#read 5, iclass 3, count 2 2006.224.08:15:29.02#ibcon#about to read 6, iclass 3, count 2 2006.224.08:15:29.02#ibcon#read 6, iclass 3, count 2 2006.224.08:15:29.02#ibcon#end of sib2, iclass 3, count 2 2006.224.08:15:29.02#ibcon#*mode == 0, iclass 3, count 2 2006.224.08:15:29.02#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.224.08:15:29.02#ibcon#[25=AT04-07\r\n] 2006.224.08:15:29.02#ibcon#*before write, iclass 3, count 2 2006.224.08:15:29.02#ibcon#enter sib2, iclass 3, count 2 2006.224.08:15:29.02#ibcon#flushed, iclass 3, count 2 2006.224.08:15:29.02#ibcon#about to write, iclass 3, count 2 2006.224.08:15:29.02#ibcon#wrote, iclass 3, count 2 2006.224.08:15:29.02#ibcon#about to read 3, iclass 3, count 2 2006.224.08:15:29.05#ibcon#read 3, iclass 3, count 2 2006.224.08:15:29.05#ibcon#about to read 4, iclass 3, count 2 2006.224.08:15:29.05#ibcon#read 4, iclass 3, count 2 2006.224.08:15:29.05#ibcon#about to read 5, iclass 3, count 2 2006.224.08:15:29.05#ibcon#read 5, iclass 3, count 2 2006.224.08:15:29.05#ibcon#about to read 6, iclass 3, count 2 2006.224.08:15:29.05#ibcon#read 6, iclass 3, count 2 2006.224.08:15:29.05#ibcon#end of sib2, iclass 3, count 2 2006.224.08:15:29.05#ibcon#*after write, iclass 3, count 2 2006.224.08:15:29.05#ibcon#*before return 0, iclass 3, count 2 2006.224.08:15:29.05#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.224.08:15:29.05#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.224.08:15:29.05#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.224.08:15:29.05#ibcon#ireg 7 cls_cnt 0 2006.224.08:15:29.05#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.224.08:15:29.17#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.224.08:15:29.17#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.224.08:15:29.17#ibcon#enter wrdev, iclass 3, count 0 2006.224.08:15:29.17#ibcon#first serial, iclass 3, count 0 2006.224.08:15:29.17#ibcon#enter sib2, iclass 3, count 0 2006.224.08:15:29.17#ibcon#flushed, iclass 3, count 0 2006.224.08:15:29.17#ibcon#about to write, iclass 3, count 0 2006.224.08:15:29.17#ibcon#wrote, iclass 3, count 0 2006.224.08:15:29.17#ibcon#about to read 3, iclass 3, count 0 2006.224.08:15:29.19#ibcon#read 3, iclass 3, count 0 2006.224.08:15:29.19#ibcon#about to read 4, iclass 3, count 0 2006.224.08:15:29.19#ibcon#read 4, iclass 3, count 0 2006.224.08:15:29.19#ibcon#about to read 5, iclass 3, count 0 2006.224.08:15:29.19#ibcon#read 5, iclass 3, count 0 2006.224.08:15:29.19#ibcon#about to read 6, iclass 3, count 0 2006.224.08:15:29.19#ibcon#read 6, iclass 3, count 0 2006.224.08:15:29.19#ibcon#end of sib2, iclass 3, count 0 2006.224.08:15:29.19#ibcon#*mode == 0, iclass 3, count 0 2006.224.08:15:29.19#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.224.08:15:29.19#ibcon#[25=USB\r\n] 2006.224.08:15:29.19#ibcon#*before write, iclass 3, count 0 2006.224.08:15:29.19#ibcon#enter sib2, iclass 3, count 0 2006.224.08:15:29.19#ibcon#flushed, iclass 3, count 0 2006.224.08:15:29.19#ibcon#about to write, iclass 3, count 0 2006.224.08:15:29.19#ibcon#wrote, iclass 3, count 0 2006.224.08:15:29.19#ibcon#about to read 3, iclass 3, count 0 2006.224.08:15:29.22#ibcon#read 3, iclass 3, count 0 2006.224.08:15:29.22#ibcon#about to read 4, iclass 3, count 0 2006.224.08:15:29.22#ibcon#read 4, iclass 3, count 0 2006.224.08:15:29.22#ibcon#about to read 5, iclass 3, count 0 2006.224.08:15:29.22#ibcon#read 5, iclass 3, count 0 2006.224.08:15:29.22#ibcon#about to read 6, iclass 3, count 0 2006.224.08:15:29.22#ibcon#read 6, iclass 3, count 0 2006.224.08:15:29.22#ibcon#end of sib2, iclass 3, count 0 2006.224.08:15:29.22#ibcon#*after write, iclass 3, count 0 2006.224.08:15:29.22#ibcon#*before return 0, iclass 3, count 0 2006.224.08:15:29.22#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.224.08:15:29.22#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.224.08:15:29.22#ibcon#about to clear, iclass 3 cls_cnt 0 2006.224.08:15:29.22#ibcon#cleared, iclass 3 cls_cnt 0 2006.224.08:15:29.22$vc4f8/valo=5,652.99 2006.224.08:15:29.22#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.224.08:15:29.22#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.224.08:15:29.22#ibcon#ireg 17 cls_cnt 0 2006.224.08:15:29.22#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.224.08:15:29.22#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.224.08:15:29.22#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.224.08:15:29.22#ibcon#enter wrdev, iclass 5, count 0 2006.224.08:15:29.22#ibcon#first serial, iclass 5, count 0 2006.224.08:15:29.22#ibcon#enter sib2, iclass 5, count 0 2006.224.08:15:29.22#ibcon#flushed, iclass 5, count 0 2006.224.08:15:29.22#ibcon#about to write, iclass 5, count 0 2006.224.08:15:29.22#ibcon#wrote, iclass 5, count 0 2006.224.08:15:29.22#ibcon#about to read 3, iclass 5, count 0 2006.224.08:15:29.24#ibcon#read 3, iclass 5, count 0 2006.224.08:15:29.24#ibcon#about to read 4, iclass 5, count 0 2006.224.08:15:29.24#ibcon#read 4, iclass 5, count 0 2006.224.08:15:29.24#ibcon#about to read 5, iclass 5, count 0 2006.224.08:15:29.24#ibcon#read 5, iclass 5, count 0 2006.224.08:15:29.24#ibcon#about to read 6, iclass 5, count 0 2006.224.08:15:29.24#ibcon#read 6, iclass 5, count 0 2006.224.08:15:29.24#ibcon#end of sib2, iclass 5, count 0 2006.224.08:15:29.24#ibcon#*mode == 0, iclass 5, count 0 2006.224.08:15:29.24#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.224.08:15:29.24#ibcon#[26=FRQ=05,652.99\r\n] 2006.224.08:15:29.24#ibcon#*before write, iclass 5, count 0 2006.224.08:15:29.24#ibcon#enter sib2, iclass 5, count 0 2006.224.08:15:29.24#ibcon#flushed, iclass 5, count 0 2006.224.08:15:29.24#ibcon#about to write, iclass 5, count 0 2006.224.08:15:29.24#ibcon#wrote, iclass 5, count 0 2006.224.08:15:29.24#ibcon#about to read 3, iclass 5, count 0 2006.224.08:15:29.28#ibcon#read 3, iclass 5, count 0 2006.224.08:15:29.28#ibcon#about to read 4, iclass 5, count 0 2006.224.08:15:29.28#ibcon#read 4, iclass 5, count 0 2006.224.08:15:29.28#ibcon#about to read 5, iclass 5, count 0 2006.224.08:15:29.28#ibcon#read 5, iclass 5, count 0 2006.224.08:15:29.28#ibcon#about to read 6, iclass 5, count 0 2006.224.08:15:29.28#ibcon#read 6, iclass 5, count 0 2006.224.08:15:29.28#ibcon#end of sib2, iclass 5, count 0 2006.224.08:15:29.28#ibcon#*after write, iclass 5, count 0 2006.224.08:15:29.28#ibcon#*before return 0, iclass 5, count 0 2006.224.08:15:29.28#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.224.08:15:29.28#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.224.08:15:29.28#ibcon#about to clear, iclass 5 cls_cnt 0 2006.224.08:15:29.28#ibcon#cleared, iclass 5 cls_cnt 0 2006.224.08:15:29.28$vc4f8/va=5,7 2006.224.08:15:29.28#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.224.08:15:29.28#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.224.08:15:29.28#ibcon#ireg 11 cls_cnt 2 2006.224.08:15:29.28#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.224.08:15:29.34#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.224.08:15:29.34#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.224.08:15:29.34#ibcon#enter wrdev, iclass 7, count 2 2006.224.08:15:29.34#ibcon#first serial, iclass 7, count 2 2006.224.08:15:29.34#ibcon#enter sib2, iclass 7, count 2 2006.224.08:15:29.34#ibcon#flushed, iclass 7, count 2 2006.224.08:15:29.34#ibcon#about to write, iclass 7, count 2 2006.224.08:15:29.34#ibcon#wrote, iclass 7, count 2 2006.224.08:15:29.34#ibcon#about to read 3, iclass 7, count 2 2006.224.08:15:29.36#ibcon#read 3, iclass 7, count 2 2006.224.08:15:29.36#ibcon#about to read 4, iclass 7, count 2 2006.224.08:15:29.36#ibcon#read 4, iclass 7, count 2 2006.224.08:15:29.36#ibcon#about to read 5, iclass 7, count 2 2006.224.08:15:29.36#ibcon#read 5, iclass 7, count 2 2006.224.08:15:29.36#ibcon#about to read 6, iclass 7, count 2 2006.224.08:15:29.36#ibcon#read 6, iclass 7, count 2 2006.224.08:15:29.36#ibcon#end of sib2, iclass 7, count 2 2006.224.08:15:29.36#ibcon#*mode == 0, iclass 7, count 2 2006.224.08:15:29.36#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.224.08:15:29.36#ibcon#[25=AT05-07\r\n] 2006.224.08:15:29.36#ibcon#*before write, iclass 7, count 2 2006.224.08:15:29.36#ibcon#enter sib2, iclass 7, count 2 2006.224.08:15:29.36#ibcon#flushed, iclass 7, count 2 2006.224.08:15:29.36#ibcon#about to write, iclass 7, count 2 2006.224.08:15:29.36#ibcon#wrote, iclass 7, count 2 2006.224.08:15:29.36#ibcon#about to read 3, iclass 7, count 2 2006.224.08:15:29.39#ibcon#read 3, iclass 7, count 2 2006.224.08:15:29.39#ibcon#about to read 4, iclass 7, count 2 2006.224.08:15:29.39#ibcon#read 4, iclass 7, count 2 2006.224.08:15:29.39#ibcon#about to read 5, iclass 7, count 2 2006.224.08:15:29.39#ibcon#read 5, iclass 7, count 2 2006.224.08:15:29.39#ibcon#about to read 6, iclass 7, count 2 2006.224.08:15:29.39#ibcon#read 6, iclass 7, count 2 2006.224.08:15:29.39#ibcon#end of sib2, iclass 7, count 2 2006.224.08:15:29.39#ibcon#*after write, iclass 7, count 2 2006.224.08:15:29.39#ibcon#*before return 0, iclass 7, count 2 2006.224.08:15:29.39#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.224.08:15:29.39#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.224.08:15:29.39#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.224.08:15:29.39#ibcon#ireg 7 cls_cnt 0 2006.224.08:15:29.39#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.224.08:15:29.51#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.224.08:15:29.51#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.224.08:15:29.51#ibcon#enter wrdev, iclass 7, count 0 2006.224.08:15:29.51#ibcon#first serial, iclass 7, count 0 2006.224.08:15:29.51#ibcon#enter sib2, iclass 7, count 0 2006.224.08:15:29.51#ibcon#flushed, iclass 7, count 0 2006.224.08:15:29.51#ibcon#about to write, iclass 7, count 0 2006.224.08:15:29.51#ibcon#wrote, iclass 7, count 0 2006.224.08:15:29.51#ibcon#about to read 3, iclass 7, count 0 2006.224.08:15:29.53#ibcon#read 3, iclass 7, count 0 2006.224.08:15:29.53#ibcon#about to read 4, iclass 7, count 0 2006.224.08:15:29.53#ibcon#read 4, iclass 7, count 0 2006.224.08:15:29.53#ibcon#about to read 5, iclass 7, count 0 2006.224.08:15:29.53#ibcon#read 5, iclass 7, count 0 2006.224.08:15:29.53#ibcon#about to read 6, iclass 7, count 0 2006.224.08:15:29.53#ibcon#read 6, iclass 7, count 0 2006.224.08:15:29.53#ibcon#end of sib2, iclass 7, count 0 2006.224.08:15:29.53#ibcon#*mode == 0, iclass 7, count 0 2006.224.08:15:29.53#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.224.08:15:29.53#ibcon#[25=USB\r\n] 2006.224.08:15:29.53#ibcon#*before write, iclass 7, count 0 2006.224.08:15:29.53#ibcon#enter sib2, iclass 7, count 0 2006.224.08:15:29.53#ibcon#flushed, iclass 7, count 0 2006.224.08:15:29.53#ibcon#about to write, iclass 7, count 0 2006.224.08:15:29.53#ibcon#wrote, iclass 7, count 0 2006.224.08:15:29.53#ibcon#about to read 3, iclass 7, count 0 2006.224.08:15:29.56#ibcon#read 3, iclass 7, count 0 2006.224.08:15:29.56#ibcon#about to read 4, iclass 7, count 0 2006.224.08:15:29.56#ibcon#read 4, iclass 7, count 0 2006.224.08:15:29.56#ibcon#about to read 5, iclass 7, count 0 2006.224.08:15:29.56#ibcon#read 5, iclass 7, count 0 2006.224.08:15:29.56#ibcon#about to read 6, iclass 7, count 0 2006.224.08:15:29.56#ibcon#read 6, iclass 7, count 0 2006.224.08:15:29.56#ibcon#end of sib2, iclass 7, count 0 2006.224.08:15:29.56#ibcon#*after write, iclass 7, count 0 2006.224.08:15:29.56#ibcon#*before return 0, iclass 7, count 0 2006.224.08:15:29.56#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.224.08:15:29.56#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.224.08:15:29.56#ibcon#about to clear, iclass 7 cls_cnt 0 2006.224.08:15:29.56#ibcon#cleared, iclass 7 cls_cnt 0 2006.224.08:15:29.56$vc4f8/valo=6,772.99 2006.224.08:15:29.56#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.224.08:15:29.56#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.224.08:15:29.56#ibcon#ireg 17 cls_cnt 0 2006.224.08:15:29.56#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.224.08:15:29.56#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.224.08:15:29.56#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.224.08:15:29.56#ibcon#enter wrdev, iclass 11, count 0 2006.224.08:15:29.56#ibcon#first serial, iclass 11, count 0 2006.224.08:15:29.56#ibcon#enter sib2, iclass 11, count 0 2006.224.08:15:29.56#ibcon#flushed, iclass 11, count 0 2006.224.08:15:29.56#ibcon#about to write, iclass 11, count 0 2006.224.08:15:29.56#ibcon#wrote, iclass 11, count 0 2006.224.08:15:29.56#ibcon#about to read 3, iclass 11, count 0 2006.224.08:15:29.58#ibcon#read 3, iclass 11, count 0 2006.224.08:15:29.58#ibcon#about to read 4, iclass 11, count 0 2006.224.08:15:29.58#ibcon#read 4, iclass 11, count 0 2006.224.08:15:29.58#ibcon#about to read 5, iclass 11, count 0 2006.224.08:15:29.58#ibcon#read 5, iclass 11, count 0 2006.224.08:15:29.58#ibcon#about to read 6, iclass 11, count 0 2006.224.08:15:29.58#ibcon#read 6, iclass 11, count 0 2006.224.08:15:29.58#ibcon#end of sib2, iclass 11, count 0 2006.224.08:15:29.58#ibcon#*mode == 0, iclass 11, count 0 2006.224.08:15:29.58#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.224.08:15:29.58#ibcon#[26=FRQ=06,772.99\r\n] 2006.224.08:15:29.58#ibcon#*before write, iclass 11, count 0 2006.224.08:15:29.58#ibcon#enter sib2, iclass 11, count 0 2006.224.08:15:29.58#ibcon#flushed, iclass 11, count 0 2006.224.08:15:29.58#ibcon#about to write, iclass 11, count 0 2006.224.08:15:29.58#ibcon#wrote, iclass 11, count 0 2006.224.08:15:29.58#ibcon#about to read 3, iclass 11, count 0 2006.224.08:15:29.62#ibcon#read 3, iclass 11, count 0 2006.224.08:15:29.62#ibcon#about to read 4, iclass 11, count 0 2006.224.08:15:29.62#ibcon#read 4, iclass 11, count 0 2006.224.08:15:29.62#ibcon#about to read 5, iclass 11, count 0 2006.224.08:15:29.62#ibcon#read 5, iclass 11, count 0 2006.224.08:15:29.62#ibcon#about to read 6, iclass 11, count 0 2006.224.08:15:29.62#ibcon#read 6, iclass 11, count 0 2006.224.08:15:29.62#ibcon#end of sib2, iclass 11, count 0 2006.224.08:15:29.62#ibcon#*after write, iclass 11, count 0 2006.224.08:15:29.62#ibcon#*before return 0, iclass 11, count 0 2006.224.08:15:29.62#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.224.08:15:29.62#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.224.08:15:29.62#ibcon#about to clear, iclass 11 cls_cnt 0 2006.224.08:15:29.62#ibcon#cleared, iclass 11 cls_cnt 0 2006.224.08:15:29.62$vc4f8/va=6,6 2006.224.08:15:29.62#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.224.08:15:29.62#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.224.08:15:29.62#ibcon#ireg 11 cls_cnt 2 2006.224.08:15:29.62#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.224.08:15:29.68#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.224.08:15:29.68#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.224.08:15:29.68#ibcon#enter wrdev, iclass 13, count 2 2006.224.08:15:29.68#ibcon#first serial, iclass 13, count 2 2006.224.08:15:29.68#ibcon#enter sib2, iclass 13, count 2 2006.224.08:15:29.68#ibcon#flushed, iclass 13, count 2 2006.224.08:15:29.68#ibcon#about to write, iclass 13, count 2 2006.224.08:15:29.68#ibcon#wrote, iclass 13, count 2 2006.224.08:15:29.68#ibcon#about to read 3, iclass 13, count 2 2006.224.08:15:29.70#ibcon#read 3, iclass 13, count 2 2006.224.08:15:29.70#ibcon#about to read 4, iclass 13, count 2 2006.224.08:15:29.70#ibcon#read 4, iclass 13, count 2 2006.224.08:15:29.70#ibcon#about to read 5, iclass 13, count 2 2006.224.08:15:29.70#ibcon#read 5, iclass 13, count 2 2006.224.08:15:29.70#ibcon#about to read 6, iclass 13, count 2 2006.224.08:15:29.70#ibcon#read 6, iclass 13, count 2 2006.224.08:15:29.70#ibcon#end of sib2, iclass 13, count 2 2006.224.08:15:29.70#ibcon#*mode == 0, iclass 13, count 2 2006.224.08:15:29.70#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.224.08:15:29.70#ibcon#[25=AT06-06\r\n] 2006.224.08:15:29.70#ibcon#*before write, iclass 13, count 2 2006.224.08:15:29.70#ibcon#enter sib2, iclass 13, count 2 2006.224.08:15:29.70#ibcon#flushed, iclass 13, count 2 2006.224.08:15:29.70#ibcon#about to write, iclass 13, count 2 2006.224.08:15:29.70#ibcon#wrote, iclass 13, count 2 2006.224.08:15:29.70#ibcon#about to read 3, iclass 13, count 2 2006.224.08:15:29.73#ibcon#read 3, iclass 13, count 2 2006.224.08:15:29.73#ibcon#about to read 4, iclass 13, count 2 2006.224.08:15:29.73#ibcon#read 4, iclass 13, count 2 2006.224.08:15:29.73#ibcon#about to read 5, iclass 13, count 2 2006.224.08:15:29.73#ibcon#read 5, iclass 13, count 2 2006.224.08:15:29.73#ibcon#about to read 6, iclass 13, count 2 2006.224.08:15:29.73#ibcon#read 6, iclass 13, count 2 2006.224.08:15:29.73#ibcon#end of sib2, iclass 13, count 2 2006.224.08:15:29.73#ibcon#*after write, iclass 13, count 2 2006.224.08:15:29.73#ibcon#*before return 0, iclass 13, count 2 2006.224.08:15:29.73#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.224.08:15:29.73#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.224.08:15:29.73#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.224.08:15:29.73#ibcon#ireg 7 cls_cnt 0 2006.224.08:15:29.73#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.224.08:15:29.85#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.224.08:15:29.85#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.224.08:15:29.85#ibcon#enter wrdev, iclass 13, count 0 2006.224.08:15:29.85#ibcon#first serial, iclass 13, count 0 2006.224.08:15:29.85#ibcon#enter sib2, iclass 13, count 0 2006.224.08:15:29.85#ibcon#flushed, iclass 13, count 0 2006.224.08:15:29.85#ibcon#about to write, iclass 13, count 0 2006.224.08:15:29.85#ibcon#wrote, iclass 13, count 0 2006.224.08:15:29.85#ibcon#about to read 3, iclass 13, count 0 2006.224.08:15:29.87#ibcon#read 3, iclass 13, count 0 2006.224.08:15:29.87#ibcon#about to read 4, iclass 13, count 0 2006.224.08:15:29.87#ibcon#read 4, iclass 13, count 0 2006.224.08:15:29.87#ibcon#about to read 5, iclass 13, count 0 2006.224.08:15:29.87#ibcon#read 5, iclass 13, count 0 2006.224.08:15:29.87#ibcon#about to read 6, iclass 13, count 0 2006.224.08:15:29.87#ibcon#read 6, iclass 13, count 0 2006.224.08:15:29.87#ibcon#end of sib2, iclass 13, count 0 2006.224.08:15:29.87#ibcon#*mode == 0, iclass 13, count 0 2006.224.08:15:29.87#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.224.08:15:29.87#ibcon#[25=USB\r\n] 2006.224.08:15:29.87#ibcon#*before write, iclass 13, count 0 2006.224.08:15:29.87#ibcon#enter sib2, iclass 13, count 0 2006.224.08:15:29.87#ibcon#flushed, iclass 13, count 0 2006.224.08:15:29.87#ibcon#about to write, iclass 13, count 0 2006.224.08:15:29.87#ibcon#wrote, iclass 13, count 0 2006.224.08:15:29.87#ibcon#about to read 3, iclass 13, count 0 2006.224.08:15:29.90#ibcon#read 3, iclass 13, count 0 2006.224.08:15:29.90#ibcon#about to read 4, iclass 13, count 0 2006.224.08:15:29.90#ibcon#read 4, iclass 13, count 0 2006.224.08:15:29.90#ibcon#about to read 5, iclass 13, count 0 2006.224.08:15:29.90#ibcon#read 5, iclass 13, count 0 2006.224.08:15:29.90#ibcon#about to read 6, iclass 13, count 0 2006.224.08:15:29.90#ibcon#read 6, iclass 13, count 0 2006.224.08:15:29.90#ibcon#end of sib2, iclass 13, count 0 2006.224.08:15:29.90#ibcon#*after write, iclass 13, count 0 2006.224.08:15:29.90#ibcon#*before return 0, iclass 13, count 0 2006.224.08:15:29.90#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.224.08:15:29.90#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.224.08:15:29.90#ibcon#about to clear, iclass 13 cls_cnt 0 2006.224.08:15:29.90#ibcon#cleared, iclass 13 cls_cnt 0 2006.224.08:15:29.90$vc4f8/valo=7,832.99 2006.224.08:15:29.90#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.224.08:15:29.90#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.224.08:15:29.90#ibcon#ireg 17 cls_cnt 0 2006.224.08:15:29.90#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.224.08:15:29.90#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.224.08:15:29.90#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.224.08:15:29.90#ibcon#enter wrdev, iclass 15, count 0 2006.224.08:15:29.90#ibcon#first serial, iclass 15, count 0 2006.224.08:15:29.90#ibcon#enter sib2, iclass 15, count 0 2006.224.08:15:29.90#ibcon#flushed, iclass 15, count 0 2006.224.08:15:29.90#ibcon#about to write, iclass 15, count 0 2006.224.08:15:29.90#ibcon#wrote, iclass 15, count 0 2006.224.08:15:29.90#ibcon#about to read 3, iclass 15, count 0 2006.224.08:15:29.92#ibcon#read 3, iclass 15, count 0 2006.224.08:15:29.92#ibcon#about to read 4, iclass 15, count 0 2006.224.08:15:29.92#ibcon#read 4, iclass 15, count 0 2006.224.08:15:29.92#ibcon#about to read 5, iclass 15, count 0 2006.224.08:15:29.92#ibcon#read 5, iclass 15, count 0 2006.224.08:15:29.92#ibcon#about to read 6, iclass 15, count 0 2006.224.08:15:29.92#ibcon#read 6, iclass 15, count 0 2006.224.08:15:29.92#ibcon#end of sib2, iclass 15, count 0 2006.224.08:15:29.92#ibcon#*mode == 0, iclass 15, count 0 2006.224.08:15:29.92#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.224.08:15:29.92#ibcon#[26=FRQ=07,832.99\r\n] 2006.224.08:15:29.92#ibcon#*before write, iclass 15, count 0 2006.224.08:15:29.92#ibcon#enter sib2, iclass 15, count 0 2006.224.08:15:29.92#ibcon#flushed, iclass 15, count 0 2006.224.08:15:29.92#ibcon#about to write, iclass 15, count 0 2006.224.08:15:29.92#ibcon#wrote, iclass 15, count 0 2006.224.08:15:29.92#ibcon#about to read 3, iclass 15, count 0 2006.224.08:15:29.96#ibcon#read 3, iclass 15, count 0 2006.224.08:15:29.96#ibcon#about to read 4, iclass 15, count 0 2006.224.08:15:29.96#ibcon#read 4, iclass 15, count 0 2006.224.08:15:29.96#ibcon#about to read 5, iclass 15, count 0 2006.224.08:15:29.96#ibcon#read 5, iclass 15, count 0 2006.224.08:15:29.96#ibcon#about to read 6, iclass 15, count 0 2006.224.08:15:29.96#ibcon#read 6, iclass 15, count 0 2006.224.08:15:29.96#ibcon#end of sib2, iclass 15, count 0 2006.224.08:15:29.96#ibcon#*after write, iclass 15, count 0 2006.224.08:15:29.96#ibcon#*before return 0, iclass 15, count 0 2006.224.08:15:29.96#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.224.08:15:29.96#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.224.08:15:29.96#ibcon#about to clear, iclass 15 cls_cnt 0 2006.224.08:15:29.96#ibcon#cleared, iclass 15 cls_cnt 0 2006.224.08:15:29.96$vc4f8/va=7,6 2006.224.08:15:29.96#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.224.08:15:29.96#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.224.08:15:29.96#ibcon#ireg 11 cls_cnt 2 2006.224.08:15:29.96#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.224.08:15:30.02#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.224.08:15:30.02#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.224.08:15:30.02#ibcon#enter wrdev, iclass 17, count 2 2006.224.08:15:30.02#ibcon#first serial, iclass 17, count 2 2006.224.08:15:30.02#ibcon#enter sib2, iclass 17, count 2 2006.224.08:15:30.02#ibcon#flushed, iclass 17, count 2 2006.224.08:15:30.02#ibcon#about to write, iclass 17, count 2 2006.224.08:15:30.02#ibcon#wrote, iclass 17, count 2 2006.224.08:15:30.02#ibcon#about to read 3, iclass 17, count 2 2006.224.08:15:30.04#ibcon#read 3, iclass 17, count 2 2006.224.08:15:30.04#ibcon#about to read 4, iclass 17, count 2 2006.224.08:15:30.04#ibcon#read 4, iclass 17, count 2 2006.224.08:15:30.04#ibcon#about to read 5, iclass 17, count 2 2006.224.08:15:30.04#ibcon#read 5, iclass 17, count 2 2006.224.08:15:30.04#ibcon#about to read 6, iclass 17, count 2 2006.224.08:15:30.04#ibcon#read 6, iclass 17, count 2 2006.224.08:15:30.04#ibcon#end of sib2, iclass 17, count 2 2006.224.08:15:30.04#ibcon#*mode == 0, iclass 17, count 2 2006.224.08:15:30.04#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.224.08:15:30.04#ibcon#[25=AT07-06\r\n] 2006.224.08:15:30.04#ibcon#*before write, iclass 17, count 2 2006.224.08:15:30.04#ibcon#enter sib2, iclass 17, count 2 2006.224.08:15:30.04#ibcon#flushed, iclass 17, count 2 2006.224.08:15:30.04#ibcon#about to write, iclass 17, count 2 2006.224.08:15:30.04#ibcon#wrote, iclass 17, count 2 2006.224.08:15:30.04#ibcon#about to read 3, iclass 17, count 2 2006.224.08:15:30.07#ibcon#read 3, iclass 17, count 2 2006.224.08:15:30.07#ibcon#about to read 4, iclass 17, count 2 2006.224.08:15:30.07#ibcon#read 4, iclass 17, count 2 2006.224.08:15:30.07#ibcon#about to read 5, iclass 17, count 2 2006.224.08:15:30.07#ibcon#read 5, iclass 17, count 2 2006.224.08:15:30.07#ibcon#about to read 6, iclass 17, count 2 2006.224.08:15:30.07#ibcon#read 6, iclass 17, count 2 2006.224.08:15:30.07#ibcon#end of sib2, iclass 17, count 2 2006.224.08:15:30.07#ibcon#*after write, iclass 17, count 2 2006.224.08:15:30.07#ibcon#*before return 0, iclass 17, count 2 2006.224.08:15:30.07#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.224.08:15:30.07#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.224.08:15:30.07#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.224.08:15:30.07#ibcon#ireg 7 cls_cnt 0 2006.224.08:15:30.07#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.224.08:15:30.19#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.224.08:15:30.19#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.224.08:15:30.19#ibcon#enter wrdev, iclass 17, count 0 2006.224.08:15:30.19#ibcon#first serial, iclass 17, count 0 2006.224.08:15:30.19#ibcon#enter sib2, iclass 17, count 0 2006.224.08:15:30.19#ibcon#flushed, iclass 17, count 0 2006.224.08:15:30.19#ibcon#about to write, iclass 17, count 0 2006.224.08:15:30.19#ibcon#wrote, iclass 17, count 0 2006.224.08:15:30.19#ibcon#about to read 3, iclass 17, count 0 2006.224.08:15:30.20#abcon#<5=/11 1.7 3.2 23.801001004.6\r\n> 2006.224.08:15:30.21#ibcon#read 3, iclass 17, count 0 2006.224.08:15:30.21#ibcon#about to read 4, iclass 17, count 0 2006.224.08:15:30.21#ibcon#read 4, iclass 17, count 0 2006.224.08:15:30.21#ibcon#about to read 5, iclass 17, count 0 2006.224.08:15:30.21#ibcon#read 5, iclass 17, count 0 2006.224.08:15:30.21#ibcon#about to read 6, iclass 17, count 0 2006.224.08:15:30.21#ibcon#read 6, iclass 17, count 0 2006.224.08:15:30.21#ibcon#end of sib2, iclass 17, count 0 2006.224.08:15:30.21#ibcon#*mode == 0, iclass 17, count 0 2006.224.08:15:30.21#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.224.08:15:30.21#ibcon#[25=USB\r\n] 2006.224.08:15:30.21#ibcon#*before write, iclass 17, count 0 2006.224.08:15:30.21#ibcon#enter sib2, iclass 17, count 0 2006.224.08:15:30.21#ibcon#flushed, iclass 17, count 0 2006.224.08:15:30.21#ibcon#about to write, iclass 17, count 0 2006.224.08:15:30.21#ibcon#wrote, iclass 17, count 0 2006.224.08:15:30.21#ibcon#about to read 3, iclass 17, count 0 2006.224.08:15:30.22#abcon#{5=INTERFACE CLEAR} 2006.224.08:15:30.24#ibcon#read 3, iclass 17, count 0 2006.224.08:15:30.24#ibcon#about to read 4, iclass 17, count 0 2006.224.08:15:30.24#ibcon#read 4, iclass 17, count 0 2006.224.08:15:30.24#ibcon#about to read 5, iclass 17, count 0 2006.224.08:15:30.24#ibcon#read 5, iclass 17, count 0 2006.224.08:15:30.24#ibcon#about to read 6, iclass 17, count 0 2006.224.08:15:30.24#ibcon#read 6, iclass 17, count 0 2006.224.08:15:30.24#ibcon#end of sib2, iclass 17, count 0 2006.224.08:15:30.24#ibcon#*after write, iclass 17, count 0 2006.224.08:15:30.24#ibcon#*before return 0, iclass 17, count 0 2006.224.08:15:30.24#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.224.08:15:30.24#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.224.08:15:30.24#ibcon#about to clear, iclass 17 cls_cnt 0 2006.224.08:15:30.24#ibcon#cleared, iclass 17 cls_cnt 0 2006.224.08:15:30.24$vc4f8/valo=8,852.99 2006.224.08:15:30.24#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.224.08:15:30.24#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.224.08:15:30.24#ibcon#ireg 17 cls_cnt 0 2006.224.08:15:30.24#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.224.08:15:30.24#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.224.08:15:30.24#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.224.08:15:30.24#ibcon#enter wrdev, iclass 22, count 0 2006.224.08:15:30.24#ibcon#first serial, iclass 22, count 0 2006.224.08:15:30.24#ibcon#enter sib2, iclass 22, count 0 2006.224.08:15:30.24#ibcon#flushed, iclass 22, count 0 2006.224.08:15:30.24#ibcon#about to write, iclass 22, count 0 2006.224.08:15:30.24#ibcon#wrote, iclass 22, count 0 2006.224.08:15:30.24#ibcon#about to read 3, iclass 22, count 0 2006.224.08:15:30.26#ibcon#read 3, iclass 22, count 0 2006.224.08:15:30.26#ibcon#about to read 4, iclass 22, count 0 2006.224.08:15:30.26#ibcon#read 4, iclass 22, count 0 2006.224.08:15:30.26#ibcon#about to read 5, iclass 22, count 0 2006.224.08:15:30.26#ibcon#read 5, iclass 22, count 0 2006.224.08:15:30.26#ibcon#about to read 6, iclass 22, count 0 2006.224.08:15:30.26#ibcon#read 6, iclass 22, count 0 2006.224.08:15:30.26#ibcon#end of sib2, iclass 22, count 0 2006.224.08:15:30.26#ibcon#*mode == 0, iclass 22, count 0 2006.224.08:15:30.26#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.224.08:15:30.26#ibcon#[26=FRQ=08,852.99\r\n] 2006.224.08:15:30.26#ibcon#*before write, iclass 22, count 0 2006.224.08:15:30.26#ibcon#enter sib2, iclass 22, count 0 2006.224.08:15:30.26#ibcon#flushed, iclass 22, count 0 2006.224.08:15:30.26#ibcon#about to write, iclass 22, count 0 2006.224.08:15:30.26#ibcon#wrote, iclass 22, count 0 2006.224.08:15:30.26#ibcon#about to read 3, iclass 22, count 0 2006.224.08:15:30.28#abcon#[5=S1D000X0/0*\r\n] 2006.224.08:15:30.30#ibcon#read 3, iclass 22, count 0 2006.224.08:15:30.30#ibcon#about to read 4, iclass 22, count 0 2006.224.08:15:30.30#ibcon#read 4, iclass 22, count 0 2006.224.08:15:30.30#ibcon#about to read 5, iclass 22, count 0 2006.224.08:15:30.30#ibcon#read 5, iclass 22, count 0 2006.224.08:15:30.30#ibcon#about to read 6, iclass 22, count 0 2006.224.08:15:30.30#ibcon#read 6, iclass 22, count 0 2006.224.08:15:30.30#ibcon#end of sib2, iclass 22, count 0 2006.224.08:15:30.30#ibcon#*after write, iclass 22, count 0 2006.224.08:15:30.30#ibcon#*before return 0, iclass 22, count 0 2006.224.08:15:30.30#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.224.08:15:30.30#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.224.08:15:30.30#ibcon#about to clear, iclass 22 cls_cnt 0 2006.224.08:15:30.30#ibcon#cleared, iclass 22 cls_cnt 0 2006.224.08:15:30.30$vc4f8/va=8,7 2006.224.08:15:30.30#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.224.08:15:30.30#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.224.08:15:30.30#ibcon#ireg 11 cls_cnt 2 2006.224.08:15:30.30#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.224.08:15:30.36#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.224.08:15:30.36#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.224.08:15:30.36#ibcon#enter wrdev, iclass 25, count 2 2006.224.08:15:30.36#ibcon#first serial, iclass 25, count 2 2006.224.08:15:30.36#ibcon#enter sib2, iclass 25, count 2 2006.224.08:15:30.36#ibcon#flushed, iclass 25, count 2 2006.224.08:15:30.36#ibcon#about to write, iclass 25, count 2 2006.224.08:15:30.36#ibcon#wrote, iclass 25, count 2 2006.224.08:15:30.36#ibcon#about to read 3, iclass 25, count 2 2006.224.08:15:30.38#ibcon#read 3, iclass 25, count 2 2006.224.08:15:30.38#ibcon#about to read 4, iclass 25, count 2 2006.224.08:15:30.38#ibcon#read 4, iclass 25, count 2 2006.224.08:15:30.38#ibcon#about to read 5, iclass 25, count 2 2006.224.08:15:30.38#ibcon#read 5, iclass 25, count 2 2006.224.08:15:30.38#ibcon#about to read 6, iclass 25, count 2 2006.224.08:15:30.38#ibcon#read 6, iclass 25, count 2 2006.224.08:15:30.38#ibcon#end of sib2, iclass 25, count 2 2006.224.08:15:30.38#ibcon#*mode == 0, iclass 25, count 2 2006.224.08:15:30.38#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.224.08:15:30.38#ibcon#[25=AT08-07\r\n] 2006.224.08:15:30.38#ibcon#*before write, iclass 25, count 2 2006.224.08:15:30.38#ibcon#enter sib2, iclass 25, count 2 2006.224.08:15:30.38#ibcon#flushed, iclass 25, count 2 2006.224.08:15:30.38#ibcon#about to write, iclass 25, count 2 2006.224.08:15:30.38#ibcon#wrote, iclass 25, count 2 2006.224.08:15:30.38#ibcon#about to read 3, iclass 25, count 2 2006.224.08:15:30.41#ibcon#read 3, iclass 25, count 2 2006.224.08:15:30.41#ibcon#about to read 4, iclass 25, count 2 2006.224.08:15:30.41#ibcon#read 4, iclass 25, count 2 2006.224.08:15:30.41#ibcon#about to read 5, iclass 25, count 2 2006.224.08:15:30.41#ibcon#read 5, iclass 25, count 2 2006.224.08:15:30.41#ibcon#about to read 6, iclass 25, count 2 2006.224.08:15:30.41#ibcon#read 6, iclass 25, count 2 2006.224.08:15:30.41#ibcon#end of sib2, iclass 25, count 2 2006.224.08:15:30.41#ibcon#*after write, iclass 25, count 2 2006.224.08:15:30.41#ibcon#*before return 0, iclass 25, count 2 2006.224.08:15:30.41#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.224.08:15:30.41#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.224.08:15:30.41#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.224.08:15:30.41#ibcon#ireg 7 cls_cnt 0 2006.224.08:15:30.41#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.224.08:15:30.53#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.224.08:15:30.53#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.224.08:15:30.53#ibcon#enter wrdev, iclass 25, count 0 2006.224.08:15:30.53#ibcon#first serial, iclass 25, count 0 2006.224.08:15:30.53#ibcon#enter sib2, iclass 25, count 0 2006.224.08:15:30.53#ibcon#flushed, iclass 25, count 0 2006.224.08:15:30.53#ibcon#about to write, iclass 25, count 0 2006.224.08:15:30.53#ibcon#wrote, iclass 25, count 0 2006.224.08:15:30.53#ibcon#about to read 3, iclass 25, count 0 2006.224.08:15:30.55#ibcon#read 3, iclass 25, count 0 2006.224.08:15:30.55#ibcon#about to read 4, iclass 25, count 0 2006.224.08:15:30.55#ibcon#read 4, iclass 25, count 0 2006.224.08:15:30.55#ibcon#about to read 5, iclass 25, count 0 2006.224.08:15:30.55#ibcon#read 5, iclass 25, count 0 2006.224.08:15:30.55#ibcon#about to read 6, iclass 25, count 0 2006.224.08:15:30.55#ibcon#read 6, iclass 25, count 0 2006.224.08:15:30.55#ibcon#end of sib2, iclass 25, count 0 2006.224.08:15:30.55#ibcon#*mode == 0, iclass 25, count 0 2006.224.08:15:30.55#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.224.08:15:30.55#ibcon#[25=USB\r\n] 2006.224.08:15:30.55#ibcon#*before write, iclass 25, count 0 2006.224.08:15:30.55#ibcon#enter sib2, iclass 25, count 0 2006.224.08:15:30.55#ibcon#flushed, iclass 25, count 0 2006.224.08:15:30.55#ibcon#about to write, iclass 25, count 0 2006.224.08:15:30.55#ibcon#wrote, iclass 25, count 0 2006.224.08:15:30.55#ibcon#about to read 3, iclass 25, count 0 2006.224.08:15:30.58#ibcon#read 3, iclass 25, count 0 2006.224.08:15:30.58#ibcon#about to read 4, iclass 25, count 0 2006.224.08:15:30.58#ibcon#read 4, iclass 25, count 0 2006.224.08:15:30.58#ibcon#about to read 5, iclass 25, count 0 2006.224.08:15:30.58#ibcon#read 5, iclass 25, count 0 2006.224.08:15:30.58#ibcon#about to read 6, iclass 25, count 0 2006.224.08:15:30.58#ibcon#read 6, iclass 25, count 0 2006.224.08:15:30.58#ibcon#end of sib2, iclass 25, count 0 2006.224.08:15:30.58#ibcon#*after write, iclass 25, count 0 2006.224.08:15:30.58#ibcon#*before return 0, iclass 25, count 0 2006.224.08:15:30.58#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.224.08:15:30.58#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.224.08:15:30.58#ibcon#about to clear, iclass 25 cls_cnt 0 2006.224.08:15:30.58#ibcon#cleared, iclass 25 cls_cnt 0 2006.224.08:15:30.58$vc4f8/vblo=1,632.99 2006.224.08:15:30.58#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.224.08:15:30.58#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.224.08:15:30.58#ibcon#ireg 17 cls_cnt 0 2006.224.08:15:30.58#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.224.08:15:30.58#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.224.08:15:30.58#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.224.08:15:30.58#ibcon#enter wrdev, iclass 27, count 0 2006.224.08:15:30.58#ibcon#first serial, iclass 27, count 0 2006.224.08:15:30.58#ibcon#enter sib2, iclass 27, count 0 2006.224.08:15:30.58#ibcon#flushed, iclass 27, count 0 2006.224.08:15:30.58#ibcon#about to write, iclass 27, count 0 2006.224.08:15:30.58#ibcon#wrote, iclass 27, count 0 2006.224.08:15:30.58#ibcon#about to read 3, iclass 27, count 0 2006.224.08:15:30.60#ibcon#read 3, iclass 27, count 0 2006.224.08:15:30.60#ibcon#about to read 4, iclass 27, count 0 2006.224.08:15:30.60#ibcon#read 4, iclass 27, count 0 2006.224.08:15:30.60#ibcon#about to read 5, iclass 27, count 0 2006.224.08:15:30.60#ibcon#read 5, iclass 27, count 0 2006.224.08:15:30.60#ibcon#about to read 6, iclass 27, count 0 2006.224.08:15:30.60#ibcon#read 6, iclass 27, count 0 2006.224.08:15:30.60#ibcon#end of sib2, iclass 27, count 0 2006.224.08:15:30.60#ibcon#*mode == 0, iclass 27, count 0 2006.224.08:15:30.60#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.224.08:15:30.60#ibcon#[28=FRQ=01,632.99\r\n] 2006.224.08:15:30.60#ibcon#*before write, iclass 27, count 0 2006.224.08:15:30.60#ibcon#enter sib2, iclass 27, count 0 2006.224.08:15:30.60#ibcon#flushed, iclass 27, count 0 2006.224.08:15:30.60#ibcon#about to write, iclass 27, count 0 2006.224.08:15:30.60#ibcon#wrote, iclass 27, count 0 2006.224.08:15:30.60#ibcon#about to read 3, iclass 27, count 0 2006.224.08:15:30.64#ibcon#read 3, iclass 27, count 0 2006.224.08:15:30.64#ibcon#about to read 4, iclass 27, count 0 2006.224.08:15:30.64#ibcon#read 4, iclass 27, count 0 2006.224.08:15:30.64#ibcon#about to read 5, iclass 27, count 0 2006.224.08:15:30.64#ibcon#read 5, iclass 27, count 0 2006.224.08:15:30.64#ibcon#about to read 6, iclass 27, count 0 2006.224.08:15:30.64#ibcon#read 6, iclass 27, count 0 2006.224.08:15:30.64#ibcon#end of sib2, iclass 27, count 0 2006.224.08:15:30.64#ibcon#*after write, iclass 27, count 0 2006.224.08:15:30.64#ibcon#*before return 0, iclass 27, count 0 2006.224.08:15:30.64#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.224.08:15:30.64#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.224.08:15:30.64#ibcon#about to clear, iclass 27 cls_cnt 0 2006.224.08:15:30.64#ibcon#cleared, iclass 27 cls_cnt 0 2006.224.08:15:30.64$vc4f8/vb=1,4 2006.224.08:15:30.64#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.224.08:15:30.64#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.224.08:15:30.64#ibcon#ireg 11 cls_cnt 2 2006.224.08:15:30.64#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.224.08:15:30.64#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.224.08:15:30.64#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.224.08:15:30.64#ibcon#enter wrdev, iclass 29, count 2 2006.224.08:15:30.64#ibcon#first serial, iclass 29, count 2 2006.224.08:15:30.64#ibcon#enter sib2, iclass 29, count 2 2006.224.08:15:30.64#ibcon#flushed, iclass 29, count 2 2006.224.08:15:30.64#ibcon#about to write, iclass 29, count 2 2006.224.08:15:30.64#ibcon#wrote, iclass 29, count 2 2006.224.08:15:30.64#ibcon#about to read 3, iclass 29, count 2 2006.224.08:15:30.66#ibcon#read 3, iclass 29, count 2 2006.224.08:15:30.66#ibcon#about to read 4, iclass 29, count 2 2006.224.08:15:30.66#ibcon#read 4, iclass 29, count 2 2006.224.08:15:30.66#ibcon#about to read 5, iclass 29, count 2 2006.224.08:15:30.66#ibcon#read 5, iclass 29, count 2 2006.224.08:15:30.66#ibcon#about to read 6, iclass 29, count 2 2006.224.08:15:30.66#ibcon#read 6, iclass 29, count 2 2006.224.08:15:30.66#ibcon#end of sib2, iclass 29, count 2 2006.224.08:15:30.66#ibcon#*mode == 0, iclass 29, count 2 2006.224.08:15:30.66#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.224.08:15:30.66#ibcon#[27=AT01-04\r\n] 2006.224.08:15:30.66#ibcon#*before write, iclass 29, count 2 2006.224.08:15:30.66#ibcon#enter sib2, iclass 29, count 2 2006.224.08:15:30.66#ibcon#flushed, iclass 29, count 2 2006.224.08:15:30.66#ibcon#about to write, iclass 29, count 2 2006.224.08:15:30.66#ibcon#wrote, iclass 29, count 2 2006.224.08:15:30.66#ibcon#about to read 3, iclass 29, count 2 2006.224.08:15:30.69#ibcon#read 3, iclass 29, count 2 2006.224.08:15:30.69#ibcon#about to read 4, iclass 29, count 2 2006.224.08:15:30.69#ibcon#read 4, iclass 29, count 2 2006.224.08:15:30.69#ibcon#about to read 5, iclass 29, count 2 2006.224.08:15:30.69#ibcon#read 5, iclass 29, count 2 2006.224.08:15:30.69#ibcon#about to read 6, iclass 29, count 2 2006.224.08:15:30.69#ibcon#read 6, iclass 29, count 2 2006.224.08:15:30.69#ibcon#end of sib2, iclass 29, count 2 2006.224.08:15:30.69#ibcon#*after write, iclass 29, count 2 2006.224.08:15:30.69#ibcon#*before return 0, iclass 29, count 2 2006.224.08:15:30.69#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.224.08:15:30.69#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.224.08:15:30.69#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.224.08:15:30.69#ibcon#ireg 7 cls_cnt 0 2006.224.08:15:30.69#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.224.08:15:30.81#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.224.08:15:30.81#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.224.08:15:30.81#ibcon#enter wrdev, iclass 29, count 0 2006.224.08:15:30.81#ibcon#first serial, iclass 29, count 0 2006.224.08:15:30.81#ibcon#enter sib2, iclass 29, count 0 2006.224.08:15:30.81#ibcon#flushed, iclass 29, count 0 2006.224.08:15:30.81#ibcon#about to write, iclass 29, count 0 2006.224.08:15:30.81#ibcon#wrote, iclass 29, count 0 2006.224.08:15:30.81#ibcon#about to read 3, iclass 29, count 0 2006.224.08:15:30.83#ibcon#read 3, iclass 29, count 0 2006.224.08:15:30.83#ibcon#about to read 4, iclass 29, count 0 2006.224.08:15:30.83#ibcon#read 4, iclass 29, count 0 2006.224.08:15:30.83#ibcon#about to read 5, iclass 29, count 0 2006.224.08:15:30.83#ibcon#read 5, iclass 29, count 0 2006.224.08:15:30.83#ibcon#about to read 6, iclass 29, count 0 2006.224.08:15:30.83#ibcon#read 6, iclass 29, count 0 2006.224.08:15:30.83#ibcon#end of sib2, iclass 29, count 0 2006.224.08:15:30.83#ibcon#*mode == 0, iclass 29, count 0 2006.224.08:15:30.83#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.224.08:15:30.83#ibcon#[27=USB\r\n] 2006.224.08:15:30.83#ibcon#*before write, iclass 29, count 0 2006.224.08:15:30.83#ibcon#enter sib2, iclass 29, count 0 2006.224.08:15:30.83#ibcon#flushed, iclass 29, count 0 2006.224.08:15:30.83#ibcon#about to write, iclass 29, count 0 2006.224.08:15:30.83#ibcon#wrote, iclass 29, count 0 2006.224.08:15:30.83#ibcon#about to read 3, iclass 29, count 0 2006.224.08:15:30.86#ibcon#read 3, iclass 29, count 0 2006.224.08:15:30.86#ibcon#about to read 4, iclass 29, count 0 2006.224.08:15:30.86#ibcon#read 4, iclass 29, count 0 2006.224.08:15:30.86#ibcon#about to read 5, iclass 29, count 0 2006.224.08:15:30.86#ibcon#read 5, iclass 29, count 0 2006.224.08:15:30.86#ibcon#about to read 6, iclass 29, count 0 2006.224.08:15:30.86#ibcon#read 6, iclass 29, count 0 2006.224.08:15:30.86#ibcon#end of sib2, iclass 29, count 0 2006.224.08:15:30.86#ibcon#*after write, iclass 29, count 0 2006.224.08:15:30.86#ibcon#*before return 0, iclass 29, count 0 2006.224.08:15:30.86#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.224.08:15:30.86#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.224.08:15:30.86#ibcon#about to clear, iclass 29 cls_cnt 0 2006.224.08:15:30.86#ibcon#cleared, iclass 29 cls_cnt 0 2006.224.08:15:30.86$vc4f8/vblo=2,640.99 2006.224.08:15:30.86#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.224.08:15:30.86#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.224.08:15:30.86#ibcon#ireg 17 cls_cnt 0 2006.224.08:15:30.86#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.224.08:15:30.86#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.224.08:15:30.86#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.224.08:15:30.86#ibcon#enter wrdev, iclass 31, count 0 2006.224.08:15:30.86#ibcon#first serial, iclass 31, count 0 2006.224.08:15:30.86#ibcon#enter sib2, iclass 31, count 0 2006.224.08:15:30.86#ibcon#flushed, iclass 31, count 0 2006.224.08:15:30.86#ibcon#about to write, iclass 31, count 0 2006.224.08:15:30.86#ibcon#wrote, iclass 31, count 0 2006.224.08:15:30.86#ibcon#about to read 3, iclass 31, count 0 2006.224.08:15:30.88#ibcon#read 3, iclass 31, count 0 2006.224.08:15:30.88#ibcon#about to read 4, iclass 31, count 0 2006.224.08:15:30.88#ibcon#read 4, iclass 31, count 0 2006.224.08:15:30.88#ibcon#about to read 5, iclass 31, count 0 2006.224.08:15:30.88#ibcon#read 5, iclass 31, count 0 2006.224.08:15:30.88#ibcon#about to read 6, iclass 31, count 0 2006.224.08:15:30.88#ibcon#read 6, iclass 31, count 0 2006.224.08:15:30.88#ibcon#end of sib2, iclass 31, count 0 2006.224.08:15:30.88#ibcon#*mode == 0, iclass 31, count 0 2006.224.08:15:30.88#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.224.08:15:30.88#ibcon#[28=FRQ=02,640.99\r\n] 2006.224.08:15:30.88#ibcon#*before write, iclass 31, count 0 2006.224.08:15:30.88#ibcon#enter sib2, iclass 31, count 0 2006.224.08:15:30.88#ibcon#flushed, iclass 31, count 0 2006.224.08:15:30.88#ibcon#about to write, iclass 31, count 0 2006.224.08:15:30.88#ibcon#wrote, iclass 31, count 0 2006.224.08:15:30.88#ibcon#about to read 3, iclass 31, count 0 2006.224.08:15:30.92#ibcon#read 3, iclass 31, count 0 2006.224.08:15:30.92#ibcon#about to read 4, iclass 31, count 0 2006.224.08:15:30.92#ibcon#read 4, iclass 31, count 0 2006.224.08:15:30.92#ibcon#about to read 5, iclass 31, count 0 2006.224.08:15:30.92#ibcon#read 5, iclass 31, count 0 2006.224.08:15:30.92#ibcon#about to read 6, iclass 31, count 0 2006.224.08:15:30.92#ibcon#read 6, iclass 31, count 0 2006.224.08:15:30.92#ibcon#end of sib2, iclass 31, count 0 2006.224.08:15:30.92#ibcon#*after write, iclass 31, count 0 2006.224.08:15:30.92#ibcon#*before return 0, iclass 31, count 0 2006.224.08:15:30.92#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.224.08:15:30.92#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.224.08:15:30.92#ibcon#about to clear, iclass 31 cls_cnt 0 2006.224.08:15:30.92#ibcon#cleared, iclass 31 cls_cnt 0 2006.224.08:15:30.92$vc4f8/vb=2,4 2006.224.08:15:30.92#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.224.08:15:30.92#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.224.08:15:30.92#ibcon#ireg 11 cls_cnt 2 2006.224.08:15:30.92#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.224.08:15:30.98#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.224.08:15:30.98#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.224.08:15:30.98#ibcon#enter wrdev, iclass 33, count 2 2006.224.08:15:30.98#ibcon#first serial, iclass 33, count 2 2006.224.08:15:30.98#ibcon#enter sib2, iclass 33, count 2 2006.224.08:15:30.98#ibcon#flushed, iclass 33, count 2 2006.224.08:15:30.98#ibcon#about to write, iclass 33, count 2 2006.224.08:15:30.98#ibcon#wrote, iclass 33, count 2 2006.224.08:15:30.98#ibcon#about to read 3, iclass 33, count 2 2006.224.08:15:31.00#ibcon#read 3, iclass 33, count 2 2006.224.08:15:31.00#ibcon#about to read 4, iclass 33, count 2 2006.224.08:15:31.00#ibcon#read 4, iclass 33, count 2 2006.224.08:15:31.00#ibcon#about to read 5, iclass 33, count 2 2006.224.08:15:31.00#ibcon#read 5, iclass 33, count 2 2006.224.08:15:31.00#ibcon#about to read 6, iclass 33, count 2 2006.224.08:15:31.00#ibcon#read 6, iclass 33, count 2 2006.224.08:15:31.00#ibcon#end of sib2, iclass 33, count 2 2006.224.08:15:31.00#ibcon#*mode == 0, iclass 33, count 2 2006.224.08:15:31.00#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.224.08:15:31.00#ibcon#[27=AT02-04\r\n] 2006.224.08:15:31.00#ibcon#*before write, iclass 33, count 2 2006.224.08:15:31.00#ibcon#enter sib2, iclass 33, count 2 2006.224.08:15:31.00#ibcon#flushed, iclass 33, count 2 2006.224.08:15:31.00#ibcon#about to write, iclass 33, count 2 2006.224.08:15:31.00#ibcon#wrote, iclass 33, count 2 2006.224.08:15:31.00#ibcon#about to read 3, iclass 33, count 2 2006.224.08:15:31.03#ibcon#read 3, iclass 33, count 2 2006.224.08:15:31.03#ibcon#about to read 4, iclass 33, count 2 2006.224.08:15:31.03#ibcon#read 4, iclass 33, count 2 2006.224.08:15:31.03#ibcon#about to read 5, iclass 33, count 2 2006.224.08:15:31.03#ibcon#read 5, iclass 33, count 2 2006.224.08:15:31.03#ibcon#about to read 6, iclass 33, count 2 2006.224.08:15:31.03#ibcon#read 6, iclass 33, count 2 2006.224.08:15:31.03#ibcon#end of sib2, iclass 33, count 2 2006.224.08:15:31.03#ibcon#*after write, iclass 33, count 2 2006.224.08:15:31.03#ibcon#*before return 0, iclass 33, count 2 2006.224.08:15:31.03#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.224.08:15:31.03#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.224.08:15:31.03#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.224.08:15:31.03#ibcon#ireg 7 cls_cnt 0 2006.224.08:15:31.03#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.224.08:15:31.15#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.224.08:15:31.15#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.224.08:15:31.15#ibcon#enter wrdev, iclass 33, count 0 2006.224.08:15:31.15#ibcon#first serial, iclass 33, count 0 2006.224.08:15:31.15#ibcon#enter sib2, iclass 33, count 0 2006.224.08:15:31.15#ibcon#flushed, iclass 33, count 0 2006.224.08:15:31.15#ibcon#about to write, iclass 33, count 0 2006.224.08:15:31.15#ibcon#wrote, iclass 33, count 0 2006.224.08:15:31.15#ibcon#about to read 3, iclass 33, count 0 2006.224.08:15:31.17#ibcon#read 3, iclass 33, count 0 2006.224.08:15:31.17#ibcon#about to read 4, iclass 33, count 0 2006.224.08:15:31.17#ibcon#read 4, iclass 33, count 0 2006.224.08:15:31.17#ibcon#about to read 5, iclass 33, count 0 2006.224.08:15:31.17#ibcon#read 5, iclass 33, count 0 2006.224.08:15:31.17#ibcon#about to read 6, iclass 33, count 0 2006.224.08:15:31.17#ibcon#read 6, iclass 33, count 0 2006.224.08:15:31.17#ibcon#end of sib2, iclass 33, count 0 2006.224.08:15:31.17#ibcon#*mode == 0, iclass 33, count 0 2006.224.08:15:31.17#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.224.08:15:31.17#ibcon#[27=USB\r\n] 2006.224.08:15:31.17#ibcon#*before write, iclass 33, count 0 2006.224.08:15:31.17#ibcon#enter sib2, iclass 33, count 0 2006.224.08:15:31.17#ibcon#flushed, iclass 33, count 0 2006.224.08:15:31.17#ibcon#about to write, iclass 33, count 0 2006.224.08:15:31.17#ibcon#wrote, iclass 33, count 0 2006.224.08:15:31.17#ibcon#about to read 3, iclass 33, count 0 2006.224.08:15:31.20#ibcon#read 3, iclass 33, count 0 2006.224.08:15:31.20#ibcon#about to read 4, iclass 33, count 0 2006.224.08:15:31.20#ibcon#read 4, iclass 33, count 0 2006.224.08:15:31.20#ibcon#about to read 5, iclass 33, count 0 2006.224.08:15:31.20#ibcon#read 5, iclass 33, count 0 2006.224.08:15:31.20#ibcon#about to read 6, iclass 33, count 0 2006.224.08:15:31.20#ibcon#read 6, iclass 33, count 0 2006.224.08:15:31.20#ibcon#end of sib2, iclass 33, count 0 2006.224.08:15:31.20#ibcon#*after write, iclass 33, count 0 2006.224.08:15:31.20#ibcon#*before return 0, iclass 33, count 0 2006.224.08:15:31.20#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.224.08:15:31.20#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.224.08:15:31.20#ibcon#about to clear, iclass 33 cls_cnt 0 2006.224.08:15:31.20#ibcon#cleared, iclass 33 cls_cnt 0 2006.224.08:15:31.20$vc4f8/vblo=3,656.99 2006.224.08:15:31.20#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.224.08:15:31.20#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.224.08:15:31.20#ibcon#ireg 17 cls_cnt 0 2006.224.08:15:31.20#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.224.08:15:31.20#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.224.08:15:31.20#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.224.08:15:31.20#ibcon#enter wrdev, iclass 35, count 0 2006.224.08:15:31.20#ibcon#first serial, iclass 35, count 0 2006.224.08:15:31.20#ibcon#enter sib2, iclass 35, count 0 2006.224.08:15:31.20#ibcon#flushed, iclass 35, count 0 2006.224.08:15:31.20#ibcon#about to write, iclass 35, count 0 2006.224.08:15:31.20#ibcon#wrote, iclass 35, count 0 2006.224.08:15:31.20#ibcon#about to read 3, iclass 35, count 0 2006.224.08:15:31.22#ibcon#read 3, iclass 35, count 0 2006.224.08:15:31.22#ibcon#about to read 4, iclass 35, count 0 2006.224.08:15:31.22#ibcon#read 4, iclass 35, count 0 2006.224.08:15:31.22#ibcon#about to read 5, iclass 35, count 0 2006.224.08:15:31.22#ibcon#read 5, iclass 35, count 0 2006.224.08:15:31.22#ibcon#about to read 6, iclass 35, count 0 2006.224.08:15:31.22#ibcon#read 6, iclass 35, count 0 2006.224.08:15:31.22#ibcon#end of sib2, iclass 35, count 0 2006.224.08:15:31.22#ibcon#*mode == 0, iclass 35, count 0 2006.224.08:15:31.22#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.224.08:15:31.22#ibcon#[28=FRQ=03,656.99\r\n] 2006.224.08:15:31.22#ibcon#*before write, iclass 35, count 0 2006.224.08:15:31.22#ibcon#enter sib2, iclass 35, count 0 2006.224.08:15:31.22#ibcon#flushed, iclass 35, count 0 2006.224.08:15:31.22#ibcon#about to write, iclass 35, count 0 2006.224.08:15:31.22#ibcon#wrote, iclass 35, count 0 2006.224.08:15:31.22#ibcon#about to read 3, iclass 35, count 0 2006.224.08:15:31.26#ibcon#read 3, iclass 35, count 0 2006.224.08:15:31.26#ibcon#about to read 4, iclass 35, count 0 2006.224.08:15:31.26#ibcon#read 4, iclass 35, count 0 2006.224.08:15:31.26#ibcon#about to read 5, iclass 35, count 0 2006.224.08:15:31.26#ibcon#read 5, iclass 35, count 0 2006.224.08:15:31.26#ibcon#about to read 6, iclass 35, count 0 2006.224.08:15:31.26#ibcon#read 6, iclass 35, count 0 2006.224.08:15:31.26#ibcon#end of sib2, iclass 35, count 0 2006.224.08:15:31.26#ibcon#*after write, iclass 35, count 0 2006.224.08:15:31.26#ibcon#*before return 0, iclass 35, count 0 2006.224.08:15:31.26#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.224.08:15:31.26#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.224.08:15:31.26#ibcon#about to clear, iclass 35 cls_cnt 0 2006.224.08:15:31.26#ibcon#cleared, iclass 35 cls_cnt 0 2006.224.08:15:31.26$vc4f8/vb=3,4 2006.224.08:15:31.26#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.224.08:15:31.26#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.224.08:15:31.26#ibcon#ireg 11 cls_cnt 2 2006.224.08:15:31.26#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.224.08:15:31.32#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.224.08:15:31.32#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.224.08:15:31.32#ibcon#enter wrdev, iclass 37, count 2 2006.224.08:15:31.32#ibcon#first serial, iclass 37, count 2 2006.224.08:15:31.32#ibcon#enter sib2, iclass 37, count 2 2006.224.08:15:31.32#ibcon#flushed, iclass 37, count 2 2006.224.08:15:31.32#ibcon#about to write, iclass 37, count 2 2006.224.08:15:31.32#ibcon#wrote, iclass 37, count 2 2006.224.08:15:31.32#ibcon#about to read 3, iclass 37, count 2 2006.224.08:15:31.34#ibcon#read 3, iclass 37, count 2 2006.224.08:15:31.34#ibcon#about to read 4, iclass 37, count 2 2006.224.08:15:31.34#ibcon#read 4, iclass 37, count 2 2006.224.08:15:31.34#ibcon#about to read 5, iclass 37, count 2 2006.224.08:15:31.34#ibcon#read 5, iclass 37, count 2 2006.224.08:15:31.34#ibcon#about to read 6, iclass 37, count 2 2006.224.08:15:31.34#ibcon#read 6, iclass 37, count 2 2006.224.08:15:31.34#ibcon#end of sib2, iclass 37, count 2 2006.224.08:15:31.34#ibcon#*mode == 0, iclass 37, count 2 2006.224.08:15:31.34#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.224.08:15:31.34#ibcon#[27=AT03-04\r\n] 2006.224.08:15:31.34#ibcon#*before write, iclass 37, count 2 2006.224.08:15:31.34#ibcon#enter sib2, iclass 37, count 2 2006.224.08:15:31.34#ibcon#flushed, iclass 37, count 2 2006.224.08:15:31.34#ibcon#about to write, iclass 37, count 2 2006.224.08:15:31.34#ibcon#wrote, iclass 37, count 2 2006.224.08:15:31.34#ibcon#about to read 3, iclass 37, count 2 2006.224.08:15:31.37#ibcon#read 3, iclass 37, count 2 2006.224.08:15:31.37#ibcon#about to read 4, iclass 37, count 2 2006.224.08:15:31.37#ibcon#read 4, iclass 37, count 2 2006.224.08:15:31.37#ibcon#about to read 5, iclass 37, count 2 2006.224.08:15:31.37#ibcon#read 5, iclass 37, count 2 2006.224.08:15:31.37#ibcon#about to read 6, iclass 37, count 2 2006.224.08:15:31.37#ibcon#read 6, iclass 37, count 2 2006.224.08:15:31.37#ibcon#end of sib2, iclass 37, count 2 2006.224.08:15:31.37#ibcon#*after write, iclass 37, count 2 2006.224.08:15:31.37#ibcon#*before return 0, iclass 37, count 2 2006.224.08:15:31.37#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.224.08:15:31.37#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.224.08:15:31.37#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.224.08:15:31.37#ibcon#ireg 7 cls_cnt 0 2006.224.08:15:31.37#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.224.08:15:31.49#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.224.08:15:31.49#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.224.08:15:31.49#ibcon#enter wrdev, iclass 37, count 0 2006.224.08:15:31.49#ibcon#first serial, iclass 37, count 0 2006.224.08:15:31.49#ibcon#enter sib2, iclass 37, count 0 2006.224.08:15:31.49#ibcon#flushed, iclass 37, count 0 2006.224.08:15:31.49#ibcon#about to write, iclass 37, count 0 2006.224.08:15:31.49#ibcon#wrote, iclass 37, count 0 2006.224.08:15:31.49#ibcon#about to read 3, iclass 37, count 0 2006.224.08:15:31.51#ibcon#read 3, iclass 37, count 0 2006.224.08:15:31.51#ibcon#about to read 4, iclass 37, count 0 2006.224.08:15:31.51#ibcon#read 4, iclass 37, count 0 2006.224.08:15:31.51#ibcon#about to read 5, iclass 37, count 0 2006.224.08:15:31.51#ibcon#read 5, iclass 37, count 0 2006.224.08:15:31.51#ibcon#about to read 6, iclass 37, count 0 2006.224.08:15:31.51#ibcon#read 6, iclass 37, count 0 2006.224.08:15:31.51#ibcon#end of sib2, iclass 37, count 0 2006.224.08:15:31.51#ibcon#*mode == 0, iclass 37, count 0 2006.224.08:15:31.51#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.224.08:15:31.51#ibcon#[27=USB\r\n] 2006.224.08:15:31.51#ibcon#*before write, iclass 37, count 0 2006.224.08:15:31.51#ibcon#enter sib2, iclass 37, count 0 2006.224.08:15:31.51#ibcon#flushed, iclass 37, count 0 2006.224.08:15:31.51#ibcon#about to write, iclass 37, count 0 2006.224.08:15:31.51#ibcon#wrote, iclass 37, count 0 2006.224.08:15:31.51#ibcon#about to read 3, iclass 37, count 0 2006.224.08:15:31.54#ibcon#read 3, iclass 37, count 0 2006.224.08:15:31.54#ibcon#about to read 4, iclass 37, count 0 2006.224.08:15:31.54#ibcon#read 4, iclass 37, count 0 2006.224.08:15:31.54#ibcon#about to read 5, iclass 37, count 0 2006.224.08:15:31.54#ibcon#read 5, iclass 37, count 0 2006.224.08:15:31.54#ibcon#about to read 6, iclass 37, count 0 2006.224.08:15:31.54#ibcon#read 6, iclass 37, count 0 2006.224.08:15:31.54#ibcon#end of sib2, iclass 37, count 0 2006.224.08:15:31.54#ibcon#*after write, iclass 37, count 0 2006.224.08:15:31.54#ibcon#*before return 0, iclass 37, count 0 2006.224.08:15:31.54#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.224.08:15:31.54#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.224.08:15:31.54#ibcon#about to clear, iclass 37 cls_cnt 0 2006.224.08:15:31.54#ibcon#cleared, iclass 37 cls_cnt 0 2006.224.08:15:31.54$vc4f8/vblo=4,712.99 2006.224.08:15:31.54#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.224.08:15:31.54#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.224.08:15:31.54#ibcon#ireg 17 cls_cnt 0 2006.224.08:15:31.54#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.224.08:15:31.54#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.224.08:15:31.54#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.224.08:15:31.54#ibcon#enter wrdev, iclass 39, count 0 2006.224.08:15:31.54#ibcon#first serial, iclass 39, count 0 2006.224.08:15:31.54#ibcon#enter sib2, iclass 39, count 0 2006.224.08:15:31.54#ibcon#flushed, iclass 39, count 0 2006.224.08:15:31.54#ibcon#about to write, iclass 39, count 0 2006.224.08:15:31.54#ibcon#wrote, iclass 39, count 0 2006.224.08:15:31.54#ibcon#about to read 3, iclass 39, count 0 2006.224.08:15:31.56#ibcon#read 3, iclass 39, count 0 2006.224.08:15:31.56#ibcon#about to read 4, iclass 39, count 0 2006.224.08:15:31.56#ibcon#read 4, iclass 39, count 0 2006.224.08:15:31.56#ibcon#about to read 5, iclass 39, count 0 2006.224.08:15:31.56#ibcon#read 5, iclass 39, count 0 2006.224.08:15:31.56#ibcon#about to read 6, iclass 39, count 0 2006.224.08:15:31.56#ibcon#read 6, iclass 39, count 0 2006.224.08:15:31.56#ibcon#end of sib2, iclass 39, count 0 2006.224.08:15:31.56#ibcon#*mode == 0, iclass 39, count 0 2006.224.08:15:31.56#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.224.08:15:31.56#ibcon#[28=FRQ=04,712.99\r\n] 2006.224.08:15:31.56#ibcon#*before write, iclass 39, count 0 2006.224.08:15:31.56#ibcon#enter sib2, iclass 39, count 0 2006.224.08:15:31.56#ibcon#flushed, iclass 39, count 0 2006.224.08:15:31.56#ibcon#about to write, iclass 39, count 0 2006.224.08:15:31.56#ibcon#wrote, iclass 39, count 0 2006.224.08:15:31.56#ibcon#about to read 3, iclass 39, count 0 2006.224.08:15:31.60#ibcon#read 3, iclass 39, count 0 2006.224.08:15:31.60#ibcon#about to read 4, iclass 39, count 0 2006.224.08:15:31.60#ibcon#read 4, iclass 39, count 0 2006.224.08:15:31.60#ibcon#about to read 5, iclass 39, count 0 2006.224.08:15:31.60#ibcon#read 5, iclass 39, count 0 2006.224.08:15:31.60#ibcon#about to read 6, iclass 39, count 0 2006.224.08:15:31.60#ibcon#read 6, iclass 39, count 0 2006.224.08:15:31.60#ibcon#end of sib2, iclass 39, count 0 2006.224.08:15:31.60#ibcon#*after write, iclass 39, count 0 2006.224.08:15:31.60#ibcon#*before return 0, iclass 39, count 0 2006.224.08:15:31.60#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.224.08:15:31.60#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.224.08:15:31.60#ibcon#about to clear, iclass 39 cls_cnt 0 2006.224.08:15:31.60#ibcon#cleared, iclass 39 cls_cnt 0 2006.224.08:15:31.60$vc4f8/vb=4,4 2006.224.08:15:31.60#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.224.08:15:31.60#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.224.08:15:31.60#ibcon#ireg 11 cls_cnt 2 2006.224.08:15:31.60#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.224.08:15:31.66#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.224.08:15:31.66#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.224.08:15:31.66#ibcon#enter wrdev, iclass 3, count 2 2006.224.08:15:31.66#ibcon#first serial, iclass 3, count 2 2006.224.08:15:31.66#ibcon#enter sib2, iclass 3, count 2 2006.224.08:15:31.66#ibcon#flushed, iclass 3, count 2 2006.224.08:15:31.66#ibcon#about to write, iclass 3, count 2 2006.224.08:15:31.66#ibcon#wrote, iclass 3, count 2 2006.224.08:15:31.66#ibcon#about to read 3, iclass 3, count 2 2006.224.08:15:31.68#ibcon#read 3, iclass 3, count 2 2006.224.08:15:31.68#ibcon#about to read 4, iclass 3, count 2 2006.224.08:15:31.68#ibcon#read 4, iclass 3, count 2 2006.224.08:15:31.68#ibcon#about to read 5, iclass 3, count 2 2006.224.08:15:31.68#ibcon#read 5, iclass 3, count 2 2006.224.08:15:31.68#ibcon#about to read 6, iclass 3, count 2 2006.224.08:15:31.68#ibcon#read 6, iclass 3, count 2 2006.224.08:15:31.68#ibcon#end of sib2, iclass 3, count 2 2006.224.08:15:31.68#ibcon#*mode == 0, iclass 3, count 2 2006.224.08:15:31.68#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.224.08:15:31.68#ibcon#[27=AT04-04\r\n] 2006.224.08:15:31.68#ibcon#*before write, iclass 3, count 2 2006.224.08:15:31.68#ibcon#enter sib2, iclass 3, count 2 2006.224.08:15:31.68#ibcon#flushed, iclass 3, count 2 2006.224.08:15:31.68#ibcon#about to write, iclass 3, count 2 2006.224.08:15:31.68#ibcon#wrote, iclass 3, count 2 2006.224.08:15:31.68#ibcon#about to read 3, iclass 3, count 2 2006.224.08:15:31.71#ibcon#read 3, iclass 3, count 2 2006.224.08:15:31.71#ibcon#about to read 4, iclass 3, count 2 2006.224.08:15:31.71#ibcon#read 4, iclass 3, count 2 2006.224.08:15:31.71#ibcon#about to read 5, iclass 3, count 2 2006.224.08:15:31.71#ibcon#read 5, iclass 3, count 2 2006.224.08:15:31.71#ibcon#about to read 6, iclass 3, count 2 2006.224.08:15:31.71#ibcon#read 6, iclass 3, count 2 2006.224.08:15:31.71#ibcon#end of sib2, iclass 3, count 2 2006.224.08:15:31.71#ibcon#*after write, iclass 3, count 2 2006.224.08:15:31.71#ibcon#*before return 0, iclass 3, count 2 2006.224.08:15:31.71#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.224.08:15:31.71#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.224.08:15:31.71#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.224.08:15:31.71#ibcon#ireg 7 cls_cnt 0 2006.224.08:15:31.71#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.224.08:15:31.83#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.224.08:15:31.83#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.224.08:15:31.83#ibcon#enter wrdev, iclass 3, count 0 2006.224.08:15:31.83#ibcon#first serial, iclass 3, count 0 2006.224.08:15:31.83#ibcon#enter sib2, iclass 3, count 0 2006.224.08:15:31.83#ibcon#flushed, iclass 3, count 0 2006.224.08:15:31.83#ibcon#about to write, iclass 3, count 0 2006.224.08:15:31.83#ibcon#wrote, iclass 3, count 0 2006.224.08:15:31.83#ibcon#about to read 3, iclass 3, count 0 2006.224.08:15:31.85#ibcon#read 3, iclass 3, count 0 2006.224.08:15:31.85#ibcon#about to read 4, iclass 3, count 0 2006.224.08:15:31.85#ibcon#read 4, iclass 3, count 0 2006.224.08:15:31.85#ibcon#about to read 5, iclass 3, count 0 2006.224.08:15:31.85#ibcon#read 5, iclass 3, count 0 2006.224.08:15:31.85#ibcon#about to read 6, iclass 3, count 0 2006.224.08:15:31.85#ibcon#read 6, iclass 3, count 0 2006.224.08:15:31.85#ibcon#end of sib2, iclass 3, count 0 2006.224.08:15:31.85#ibcon#*mode == 0, iclass 3, count 0 2006.224.08:15:31.85#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.224.08:15:31.85#ibcon#[27=USB\r\n] 2006.224.08:15:31.85#ibcon#*before write, iclass 3, count 0 2006.224.08:15:31.85#ibcon#enter sib2, iclass 3, count 0 2006.224.08:15:31.85#ibcon#flushed, iclass 3, count 0 2006.224.08:15:31.85#ibcon#about to write, iclass 3, count 0 2006.224.08:15:31.85#ibcon#wrote, iclass 3, count 0 2006.224.08:15:31.85#ibcon#about to read 3, iclass 3, count 0 2006.224.08:15:31.88#ibcon#read 3, iclass 3, count 0 2006.224.08:15:31.88#ibcon#about to read 4, iclass 3, count 0 2006.224.08:15:31.88#ibcon#read 4, iclass 3, count 0 2006.224.08:15:31.88#ibcon#about to read 5, iclass 3, count 0 2006.224.08:15:31.88#ibcon#read 5, iclass 3, count 0 2006.224.08:15:31.88#ibcon#about to read 6, iclass 3, count 0 2006.224.08:15:31.88#ibcon#read 6, iclass 3, count 0 2006.224.08:15:31.88#ibcon#end of sib2, iclass 3, count 0 2006.224.08:15:31.88#ibcon#*after write, iclass 3, count 0 2006.224.08:15:31.88#ibcon#*before return 0, iclass 3, count 0 2006.224.08:15:31.88#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.224.08:15:31.88#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.224.08:15:31.88#ibcon#about to clear, iclass 3 cls_cnt 0 2006.224.08:15:31.88#ibcon#cleared, iclass 3 cls_cnt 0 2006.224.08:15:31.88$vc4f8/vblo=5,744.99 2006.224.08:15:31.88#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.224.08:15:31.88#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.224.08:15:31.88#ibcon#ireg 17 cls_cnt 0 2006.224.08:15:31.88#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.224.08:15:31.88#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.224.08:15:31.88#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.224.08:15:31.88#ibcon#enter wrdev, iclass 5, count 0 2006.224.08:15:31.88#ibcon#first serial, iclass 5, count 0 2006.224.08:15:31.88#ibcon#enter sib2, iclass 5, count 0 2006.224.08:15:31.88#ibcon#flushed, iclass 5, count 0 2006.224.08:15:31.88#ibcon#about to write, iclass 5, count 0 2006.224.08:15:31.88#ibcon#wrote, iclass 5, count 0 2006.224.08:15:31.88#ibcon#about to read 3, iclass 5, count 0 2006.224.08:15:31.90#ibcon#read 3, iclass 5, count 0 2006.224.08:15:31.90#ibcon#about to read 4, iclass 5, count 0 2006.224.08:15:31.90#ibcon#read 4, iclass 5, count 0 2006.224.08:15:31.90#ibcon#about to read 5, iclass 5, count 0 2006.224.08:15:31.90#ibcon#read 5, iclass 5, count 0 2006.224.08:15:31.90#ibcon#about to read 6, iclass 5, count 0 2006.224.08:15:31.90#ibcon#read 6, iclass 5, count 0 2006.224.08:15:31.90#ibcon#end of sib2, iclass 5, count 0 2006.224.08:15:31.90#ibcon#*mode == 0, iclass 5, count 0 2006.224.08:15:31.90#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.224.08:15:31.90#ibcon#[28=FRQ=05,744.99\r\n] 2006.224.08:15:31.90#ibcon#*before write, iclass 5, count 0 2006.224.08:15:31.90#ibcon#enter sib2, iclass 5, count 0 2006.224.08:15:31.90#ibcon#flushed, iclass 5, count 0 2006.224.08:15:31.90#ibcon#about to write, iclass 5, count 0 2006.224.08:15:31.90#ibcon#wrote, iclass 5, count 0 2006.224.08:15:31.90#ibcon#about to read 3, iclass 5, count 0 2006.224.08:15:31.94#ibcon#read 3, iclass 5, count 0 2006.224.08:15:31.94#ibcon#about to read 4, iclass 5, count 0 2006.224.08:15:31.94#ibcon#read 4, iclass 5, count 0 2006.224.08:15:31.94#ibcon#about to read 5, iclass 5, count 0 2006.224.08:15:31.94#ibcon#read 5, iclass 5, count 0 2006.224.08:15:31.94#ibcon#about to read 6, iclass 5, count 0 2006.224.08:15:31.94#ibcon#read 6, iclass 5, count 0 2006.224.08:15:31.94#ibcon#end of sib2, iclass 5, count 0 2006.224.08:15:31.94#ibcon#*after write, iclass 5, count 0 2006.224.08:15:31.94#ibcon#*before return 0, iclass 5, count 0 2006.224.08:15:31.94#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.224.08:15:31.94#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.224.08:15:31.94#ibcon#about to clear, iclass 5 cls_cnt 0 2006.224.08:15:31.94#ibcon#cleared, iclass 5 cls_cnt 0 2006.224.08:15:31.94$vc4f8/vb=5,4 2006.224.08:15:31.94#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.224.08:15:31.94#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.224.08:15:31.94#ibcon#ireg 11 cls_cnt 2 2006.224.08:15:31.94#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.224.08:15:32.00#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.224.08:15:32.00#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.224.08:15:32.00#ibcon#enter wrdev, iclass 7, count 2 2006.224.08:15:32.00#ibcon#first serial, iclass 7, count 2 2006.224.08:15:32.00#ibcon#enter sib2, iclass 7, count 2 2006.224.08:15:32.00#ibcon#flushed, iclass 7, count 2 2006.224.08:15:32.00#ibcon#about to write, iclass 7, count 2 2006.224.08:15:32.00#ibcon#wrote, iclass 7, count 2 2006.224.08:15:32.00#ibcon#about to read 3, iclass 7, count 2 2006.224.08:15:32.02#ibcon#read 3, iclass 7, count 2 2006.224.08:15:32.02#ibcon#about to read 4, iclass 7, count 2 2006.224.08:15:32.02#ibcon#read 4, iclass 7, count 2 2006.224.08:15:32.02#ibcon#about to read 5, iclass 7, count 2 2006.224.08:15:32.02#ibcon#read 5, iclass 7, count 2 2006.224.08:15:32.02#ibcon#about to read 6, iclass 7, count 2 2006.224.08:15:32.02#ibcon#read 6, iclass 7, count 2 2006.224.08:15:32.02#ibcon#end of sib2, iclass 7, count 2 2006.224.08:15:32.02#ibcon#*mode == 0, iclass 7, count 2 2006.224.08:15:32.02#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.224.08:15:32.02#ibcon#[27=AT05-04\r\n] 2006.224.08:15:32.02#ibcon#*before write, iclass 7, count 2 2006.224.08:15:32.02#ibcon#enter sib2, iclass 7, count 2 2006.224.08:15:32.02#ibcon#flushed, iclass 7, count 2 2006.224.08:15:32.02#ibcon#about to write, iclass 7, count 2 2006.224.08:15:32.02#ibcon#wrote, iclass 7, count 2 2006.224.08:15:32.02#ibcon#about to read 3, iclass 7, count 2 2006.224.08:15:32.05#ibcon#read 3, iclass 7, count 2 2006.224.08:15:32.05#ibcon#about to read 4, iclass 7, count 2 2006.224.08:15:32.05#ibcon#read 4, iclass 7, count 2 2006.224.08:15:32.05#ibcon#about to read 5, iclass 7, count 2 2006.224.08:15:32.05#ibcon#read 5, iclass 7, count 2 2006.224.08:15:32.05#ibcon#about to read 6, iclass 7, count 2 2006.224.08:15:32.05#ibcon#read 6, iclass 7, count 2 2006.224.08:15:32.05#ibcon#end of sib2, iclass 7, count 2 2006.224.08:15:32.05#ibcon#*after write, iclass 7, count 2 2006.224.08:15:32.05#ibcon#*before return 0, iclass 7, count 2 2006.224.08:15:32.05#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.224.08:15:32.05#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.224.08:15:32.05#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.224.08:15:32.05#ibcon#ireg 7 cls_cnt 0 2006.224.08:15:32.05#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.224.08:15:32.17#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.224.08:15:32.17#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.224.08:15:32.17#ibcon#enter wrdev, iclass 7, count 0 2006.224.08:15:32.17#ibcon#first serial, iclass 7, count 0 2006.224.08:15:32.17#ibcon#enter sib2, iclass 7, count 0 2006.224.08:15:32.17#ibcon#flushed, iclass 7, count 0 2006.224.08:15:32.17#ibcon#about to write, iclass 7, count 0 2006.224.08:15:32.17#ibcon#wrote, iclass 7, count 0 2006.224.08:15:32.17#ibcon#about to read 3, iclass 7, count 0 2006.224.08:15:32.19#ibcon#read 3, iclass 7, count 0 2006.224.08:15:32.19#ibcon#about to read 4, iclass 7, count 0 2006.224.08:15:32.19#ibcon#read 4, iclass 7, count 0 2006.224.08:15:32.19#ibcon#about to read 5, iclass 7, count 0 2006.224.08:15:32.19#ibcon#read 5, iclass 7, count 0 2006.224.08:15:32.19#ibcon#about to read 6, iclass 7, count 0 2006.224.08:15:32.19#ibcon#read 6, iclass 7, count 0 2006.224.08:15:32.19#ibcon#end of sib2, iclass 7, count 0 2006.224.08:15:32.19#ibcon#*mode == 0, iclass 7, count 0 2006.224.08:15:32.19#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.224.08:15:32.19#ibcon#[27=USB\r\n] 2006.224.08:15:32.19#ibcon#*before write, iclass 7, count 0 2006.224.08:15:32.19#ibcon#enter sib2, iclass 7, count 0 2006.224.08:15:32.19#ibcon#flushed, iclass 7, count 0 2006.224.08:15:32.19#ibcon#about to write, iclass 7, count 0 2006.224.08:15:32.19#ibcon#wrote, iclass 7, count 0 2006.224.08:15:32.19#ibcon#about to read 3, iclass 7, count 0 2006.224.08:15:32.22#ibcon#read 3, iclass 7, count 0 2006.224.08:15:32.22#ibcon#about to read 4, iclass 7, count 0 2006.224.08:15:32.22#ibcon#read 4, iclass 7, count 0 2006.224.08:15:32.22#ibcon#about to read 5, iclass 7, count 0 2006.224.08:15:32.22#ibcon#read 5, iclass 7, count 0 2006.224.08:15:32.22#ibcon#about to read 6, iclass 7, count 0 2006.224.08:15:32.22#ibcon#read 6, iclass 7, count 0 2006.224.08:15:32.22#ibcon#end of sib2, iclass 7, count 0 2006.224.08:15:32.22#ibcon#*after write, iclass 7, count 0 2006.224.08:15:32.22#ibcon#*before return 0, iclass 7, count 0 2006.224.08:15:32.22#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.224.08:15:32.22#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.224.08:15:32.22#ibcon#about to clear, iclass 7 cls_cnt 0 2006.224.08:15:32.22#ibcon#cleared, iclass 7 cls_cnt 0 2006.224.08:15:32.22$vc4f8/vblo=6,752.99 2006.224.08:15:32.22#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.224.08:15:32.22#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.224.08:15:32.22#ibcon#ireg 17 cls_cnt 0 2006.224.08:15:32.22#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.224.08:15:32.22#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.224.08:15:32.22#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.224.08:15:32.22#ibcon#enter wrdev, iclass 11, count 0 2006.224.08:15:32.22#ibcon#first serial, iclass 11, count 0 2006.224.08:15:32.22#ibcon#enter sib2, iclass 11, count 0 2006.224.08:15:32.22#ibcon#flushed, iclass 11, count 0 2006.224.08:15:32.22#ibcon#about to write, iclass 11, count 0 2006.224.08:15:32.22#ibcon#wrote, iclass 11, count 0 2006.224.08:15:32.22#ibcon#about to read 3, iclass 11, count 0 2006.224.08:15:32.24#ibcon#read 3, iclass 11, count 0 2006.224.08:15:32.24#ibcon#about to read 4, iclass 11, count 0 2006.224.08:15:32.24#ibcon#read 4, iclass 11, count 0 2006.224.08:15:32.24#ibcon#about to read 5, iclass 11, count 0 2006.224.08:15:32.24#ibcon#read 5, iclass 11, count 0 2006.224.08:15:32.24#ibcon#about to read 6, iclass 11, count 0 2006.224.08:15:32.24#ibcon#read 6, iclass 11, count 0 2006.224.08:15:32.24#ibcon#end of sib2, iclass 11, count 0 2006.224.08:15:32.24#ibcon#*mode == 0, iclass 11, count 0 2006.224.08:15:32.24#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.224.08:15:32.24#ibcon#[28=FRQ=06,752.99\r\n] 2006.224.08:15:32.24#ibcon#*before write, iclass 11, count 0 2006.224.08:15:32.24#ibcon#enter sib2, iclass 11, count 0 2006.224.08:15:32.24#ibcon#flushed, iclass 11, count 0 2006.224.08:15:32.24#ibcon#about to write, iclass 11, count 0 2006.224.08:15:32.24#ibcon#wrote, iclass 11, count 0 2006.224.08:15:32.24#ibcon#about to read 3, iclass 11, count 0 2006.224.08:15:32.28#ibcon#read 3, iclass 11, count 0 2006.224.08:15:32.28#ibcon#about to read 4, iclass 11, count 0 2006.224.08:15:32.28#ibcon#read 4, iclass 11, count 0 2006.224.08:15:32.28#ibcon#about to read 5, iclass 11, count 0 2006.224.08:15:32.28#ibcon#read 5, iclass 11, count 0 2006.224.08:15:32.28#ibcon#about to read 6, iclass 11, count 0 2006.224.08:15:32.28#ibcon#read 6, iclass 11, count 0 2006.224.08:15:32.28#ibcon#end of sib2, iclass 11, count 0 2006.224.08:15:32.28#ibcon#*after write, iclass 11, count 0 2006.224.08:15:32.28#ibcon#*before return 0, iclass 11, count 0 2006.224.08:15:32.28#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.224.08:15:32.28#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.224.08:15:32.28#ibcon#about to clear, iclass 11 cls_cnt 0 2006.224.08:15:32.28#ibcon#cleared, iclass 11 cls_cnt 0 2006.224.08:15:32.28$vc4f8/vb=6,4 2006.224.08:15:32.28#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.224.08:15:32.28#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.224.08:15:32.28#ibcon#ireg 11 cls_cnt 2 2006.224.08:15:32.28#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.224.08:15:32.34#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.224.08:15:32.34#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.224.08:15:32.34#ibcon#enter wrdev, iclass 13, count 2 2006.224.08:15:32.34#ibcon#first serial, iclass 13, count 2 2006.224.08:15:32.34#ibcon#enter sib2, iclass 13, count 2 2006.224.08:15:32.34#ibcon#flushed, iclass 13, count 2 2006.224.08:15:32.34#ibcon#about to write, iclass 13, count 2 2006.224.08:15:32.34#ibcon#wrote, iclass 13, count 2 2006.224.08:15:32.34#ibcon#about to read 3, iclass 13, count 2 2006.224.08:15:32.36#ibcon#read 3, iclass 13, count 2 2006.224.08:15:32.36#ibcon#about to read 4, iclass 13, count 2 2006.224.08:15:32.36#ibcon#read 4, iclass 13, count 2 2006.224.08:15:32.36#ibcon#about to read 5, iclass 13, count 2 2006.224.08:15:32.36#ibcon#read 5, iclass 13, count 2 2006.224.08:15:32.36#ibcon#about to read 6, iclass 13, count 2 2006.224.08:15:32.36#ibcon#read 6, iclass 13, count 2 2006.224.08:15:32.36#ibcon#end of sib2, iclass 13, count 2 2006.224.08:15:32.36#ibcon#*mode == 0, iclass 13, count 2 2006.224.08:15:32.36#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.224.08:15:32.36#ibcon#[27=AT06-04\r\n] 2006.224.08:15:32.36#ibcon#*before write, iclass 13, count 2 2006.224.08:15:32.36#ibcon#enter sib2, iclass 13, count 2 2006.224.08:15:32.36#ibcon#flushed, iclass 13, count 2 2006.224.08:15:32.36#ibcon#about to write, iclass 13, count 2 2006.224.08:15:32.36#ibcon#wrote, iclass 13, count 2 2006.224.08:15:32.36#ibcon#about to read 3, iclass 13, count 2 2006.224.08:15:32.39#ibcon#read 3, iclass 13, count 2 2006.224.08:15:32.39#ibcon#about to read 4, iclass 13, count 2 2006.224.08:15:32.39#ibcon#read 4, iclass 13, count 2 2006.224.08:15:32.39#ibcon#about to read 5, iclass 13, count 2 2006.224.08:15:32.39#ibcon#read 5, iclass 13, count 2 2006.224.08:15:32.39#ibcon#about to read 6, iclass 13, count 2 2006.224.08:15:32.39#ibcon#read 6, iclass 13, count 2 2006.224.08:15:32.39#ibcon#end of sib2, iclass 13, count 2 2006.224.08:15:32.39#ibcon#*after write, iclass 13, count 2 2006.224.08:15:32.39#ibcon#*before return 0, iclass 13, count 2 2006.224.08:15:32.39#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.224.08:15:32.39#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.224.08:15:32.39#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.224.08:15:32.39#ibcon#ireg 7 cls_cnt 0 2006.224.08:15:32.39#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.224.08:15:32.51#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.224.08:15:32.51#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.224.08:15:32.51#ibcon#enter wrdev, iclass 13, count 0 2006.224.08:15:32.51#ibcon#first serial, iclass 13, count 0 2006.224.08:15:32.51#ibcon#enter sib2, iclass 13, count 0 2006.224.08:15:32.51#ibcon#flushed, iclass 13, count 0 2006.224.08:15:32.51#ibcon#about to write, iclass 13, count 0 2006.224.08:15:32.51#ibcon#wrote, iclass 13, count 0 2006.224.08:15:32.51#ibcon#about to read 3, iclass 13, count 0 2006.224.08:15:32.53#ibcon#read 3, iclass 13, count 0 2006.224.08:15:32.53#ibcon#about to read 4, iclass 13, count 0 2006.224.08:15:32.53#ibcon#read 4, iclass 13, count 0 2006.224.08:15:32.53#ibcon#about to read 5, iclass 13, count 0 2006.224.08:15:32.53#ibcon#read 5, iclass 13, count 0 2006.224.08:15:32.53#ibcon#about to read 6, iclass 13, count 0 2006.224.08:15:32.53#ibcon#read 6, iclass 13, count 0 2006.224.08:15:32.53#ibcon#end of sib2, iclass 13, count 0 2006.224.08:15:32.53#ibcon#*mode == 0, iclass 13, count 0 2006.224.08:15:32.53#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.224.08:15:32.53#ibcon#[27=USB\r\n] 2006.224.08:15:32.53#ibcon#*before write, iclass 13, count 0 2006.224.08:15:32.53#ibcon#enter sib2, iclass 13, count 0 2006.224.08:15:32.53#ibcon#flushed, iclass 13, count 0 2006.224.08:15:32.53#ibcon#about to write, iclass 13, count 0 2006.224.08:15:32.53#ibcon#wrote, iclass 13, count 0 2006.224.08:15:32.53#ibcon#about to read 3, iclass 13, count 0 2006.224.08:15:32.56#ibcon#read 3, iclass 13, count 0 2006.224.08:15:32.56#ibcon#about to read 4, iclass 13, count 0 2006.224.08:15:32.56#ibcon#read 4, iclass 13, count 0 2006.224.08:15:32.56#ibcon#about to read 5, iclass 13, count 0 2006.224.08:15:32.56#ibcon#read 5, iclass 13, count 0 2006.224.08:15:32.56#ibcon#about to read 6, iclass 13, count 0 2006.224.08:15:32.56#ibcon#read 6, iclass 13, count 0 2006.224.08:15:32.56#ibcon#end of sib2, iclass 13, count 0 2006.224.08:15:32.56#ibcon#*after write, iclass 13, count 0 2006.224.08:15:32.56#ibcon#*before return 0, iclass 13, count 0 2006.224.08:15:32.56#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.224.08:15:32.56#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.224.08:15:32.56#ibcon#about to clear, iclass 13 cls_cnt 0 2006.224.08:15:32.56#ibcon#cleared, iclass 13 cls_cnt 0 2006.224.08:15:32.56$vc4f8/vabw=wide 2006.224.08:15:32.56#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.224.08:15:32.56#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.224.08:15:32.56#ibcon#ireg 8 cls_cnt 0 2006.224.08:15:32.56#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.224.08:15:32.56#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.224.08:15:32.56#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.224.08:15:32.56#ibcon#enter wrdev, iclass 15, count 0 2006.224.08:15:32.56#ibcon#first serial, iclass 15, count 0 2006.224.08:15:32.56#ibcon#enter sib2, iclass 15, count 0 2006.224.08:15:32.56#ibcon#flushed, iclass 15, count 0 2006.224.08:15:32.56#ibcon#about to write, iclass 15, count 0 2006.224.08:15:32.56#ibcon#wrote, iclass 15, count 0 2006.224.08:15:32.56#ibcon#about to read 3, iclass 15, count 0 2006.224.08:15:32.58#ibcon#read 3, iclass 15, count 0 2006.224.08:15:32.58#ibcon#about to read 4, iclass 15, count 0 2006.224.08:15:32.58#ibcon#read 4, iclass 15, count 0 2006.224.08:15:32.58#ibcon#about to read 5, iclass 15, count 0 2006.224.08:15:32.58#ibcon#read 5, iclass 15, count 0 2006.224.08:15:32.58#ibcon#about to read 6, iclass 15, count 0 2006.224.08:15:32.58#ibcon#read 6, iclass 15, count 0 2006.224.08:15:32.58#ibcon#end of sib2, iclass 15, count 0 2006.224.08:15:32.58#ibcon#*mode == 0, iclass 15, count 0 2006.224.08:15:32.58#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.224.08:15:32.58#ibcon#[25=BW32\r\n] 2006.224.08:15:32.58#ibcon#*before write, iclass 15, count 0 2006.224.08:15:32.58#ibcon#enter sib2, iclass 15, count 0 2006.224.08:15:32.58#ibcon#flushed, iclass 15, count 0 2006.224.08:15:32.58#ibcon#about to write, iclass 15, count 0 2006.224.08:15:32.58#ibcon#wrote, iclass 15, count 0 2006.224.08:15:32.58#ibcon#about to read 3, iclass 15, count 0 2006.224.08:15:32.61#ibcon#read 3, iclass 15, count 0 2006.224.08:15:32.61#ibcon#about to read 4, iclass 15, count 0 2006.224.08:15:32.61#ibcon#read 4, iclass 15, count 0 2006.224.08:15:32.61#ibcon#about to read 5, iclass 15, count 0 2006.224.08:15:32.61#ibcon#read 5, iclass 15, count 0 2006.224.08:15:32.61#ibcon#about to read 6, iclass 15, count 0 2006.224.08:15:32.61#ibcon#read 6, iclass 15, count 0 2006.224.08:15:32.61#ibcon#end of sib2, iclass 15, count 0 2006.224.08:15:32.61#ibcon#*after write, iclass 15, count 0 2006.224.08:15:32.61#ibcon#*before return 0, iclass 15, count 0 2006.224.08:15:32.61#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.224.08:15:32.61#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.224.08:15:32.61#ibcon#about to clear, iclass 15 cls_cnt 0 2006.224.08:15:32.61#ibcon#cleared, iclass 15 cls_cnt 0 2006.224.08:15:32.61$vc4f8/vbbw=wide 2006.224.08:15:32.61#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.224.08:15:32.61#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.224.08:15:32.61#ibcon#ireg 8 cls_cnt 0 2006.224.08:15:32.61#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.224.08:15:32.68#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.224.08:15:32.68#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.224.08:15:32.68#ibcon#enter wrdev, iclass 17, count 0 2006.224.08:15:32.68#ibcon#first serial, iclass 17, count 0 2006.224.08:15:32.68#ibcon#enter sib2, iclass 17, count 0 2006.224.08:15:32.68#ibcon#flushed, iclass 17, count 0 2006.224.08:15:32.68#ibcon#about to write, iclass 17, count 0 2006.224.08:15:32.68#ibcon#wrote, iclass 17, count 0 2006.224.08:15:32.68#ibcon#about to read 3, iclass 17, count 0 2006.224.08:15:32.70#ibcon#read 3, iclass 17, count 0 2006.224.08:15:32.70#ibcon#about to read 4, iclass 17, count 0 2006.224.08:15:32.70#ibcon#read 4, iclass 17, count 0 2006.224.08:15:32.70#ibcon#about to read 5, iclass 17, count 0 2006.224.08:15:32.70#ibcon#read 5, iclass 17, count 0 2006.224.08:15:32.70#ibcon#about to read 6, iclass 17, count 0 2006.224.08:15:32.70#ibcon#read 6, iclass 17, count 0 2006.224.08:15:32.70#ibcon#end of sib2, iclass 17, count 0 2006.224.08:15:32.70#ibcon#*mode == 0, iclass 17, count 0 2006.224.08:15:32.70#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.224.08:15:32.70#ibcon#[27=BW32\r\n] 2006.224.08:15:32.70#ibcon#*before write, iclass 17, count 0 2006.224.08:15:32.70#ibcon#enter sib2, iclass 17, count 0 2006.224.08:15:32.70#ibcon#flushed, iclass 17, count 0 2006.224.08:15:32.70#ibcon#about to write, iclass 17, count 0 2006.224.08:15:32.70#ibcon#wrote, iclass 17, count 0 2006.224.08:15:32.70#ibcon#about to read 3, iclass 17, count 0 2006.224.08:15:32.73#ibcon#read 3, iclass 17, count 0 2006.224.08:15:32.73#ibcon#about to read 4, iclass 17, count 0 2006.224.08:15:32.73#ibcon#read 4, iclass 17, count 0 2006.224.08:15:32.73#ibcon#about to read 5, iclass 17, count 0 2006.224.08:15:32.73#ibcon#read 5, iclass 17, count 0 2006.224.08:15:32.73#ibcon#about to read 6, iclass 17, count 0 2006.224.08:15:32.73#ibcon#read 6, iclass 17, count 0 2006.224.08:15:32.73#ibcon#end of sib2, iclass 17, count 0 2006.224.08:15:32.73#ibcon#*after write, iclass 17, count 0 2006.224.08:15:32.73#ibcon#*before return 0, iclass 17, count 0 2006.224.08:15:32.73#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.224.08:15:32.73#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.224.08:15:32.73#ibcon#about to clear, iclass 17 cls_cnt 0 2006.224.08:15:32.73#ibcon#cleared, iclass 17 cls_cnt 0 2006.224.08:15:32.73$4f8m12a/ifd4f 2006.224.08:15:32.73$ifd4f/lo= 2006.224.08:15:32.73$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.224.08:15:32.73$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.224.08:15:32.73$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.224.08:15:32.73$ifd4f/patch= 2006.224.08:15:32.73$ifd4f/patch=lo1,a1,a2,a3,a4 2006.224.08:15:32.73$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.224.08:15:32.73$ifd4f/patch=lo3,a5,a6,a7,a8 2006.224.08:15:32.73$4f8m12a/"form=m,16.000,1:2 2006.224.08:15:32.73$4f8m12a/"tpicd 2006.224.08:15:32.73$4f8m12a/echo=off 2006.224.08:15:32.73$4f8m12a/xlog=off 2006.224.08:15:32.73:!2006.224.08:16:00 2006.224.08:15:41.14#trakl#Source acquired 2006.224.08:15:41.14#flagr#flagr/antenna,acquired 2006.224.08:16:00.00:preob 2006.224.08:16:00.14/onsource/TRACKING 2006.224.08:16:00.14:!2006.224.08:16:10 2006.224.08:16:10.00:data_valid=on 2006.224.08:16:10.00:midob 2006.224.08:16:11.14/onsource/TRACKING 2006.224.08:16:11.14/wx/23.80,1004.6,100 2006.224.08:16:11.30/cable/+6.4349E-03 2006.224.08:16:12.39/va/01,08,usb,yes,42,44 2006.224.08:16:12.39/va/02,07,usb,yes,42,44 2006.224.08:16:12.39/va/03,06,usb,yes,45,45 2006.224.08:16:12.39/va/04,07,usb,yes,44,48 2006.224.08:16:12.39/va/05,07,usb,yes,51,54 2006.224.08:16:12.39/va/06,06,usb,yes,51,50 2006.224.08:16:12.39/va/07,06,usb,yes,52,51 2006.224.08:16:12.39/va/08,07,usb,yes,49,48 2006.224.08:16:12.62/valo/01,532.99,yes,locked 2006.224.08:16:12.62/valo/02,572.99,yes,locked 2006.224.08:16:12.62/valo/03,672.99,yes,locked 2006.224.08:16:12.62/valo/04,832.99,yes,locked 2006.224.08:16:12.62/valo/05,652.99,yes,locked 2006.224.08:16:12.62/valo/06,772.99,yes,locked 2006.224.08:16:12.62/valo/07,832.99,yes,locked 2006.224.08:16:12.62/valo/08,852.99,yes,locked 2006.224.08:16:13.71/vb/01,04,usb,yes,32,30 2006.224.08:16:13.71/vb/02,04,usb,yes,33,35 2006.224.08:16:13.71/vb/03,04,usb,yes,30,34 2006.224.08:16:13.71/vb/04,04,usb,yes,31,31 2006.224.08:16:13.71/vb/05,04,usb,yes,29,33 2006.224.08:16:13.71/vb/06,04,usb,yes,30,33 2006.224.08:16:13.71/vb/07,04,usb,yes,32,32 2006.224.08:16:13.71/vb/08,04,usb,yes,30,33 2006.224.08:16:13.95/vblo/01,632.99,yes,locked 2006.224.08:16:13.95/vblo/02,640.99,yes,locked 2006.224.08:16:13.95/vblo/03,656.99,yes,locked 2006.224.08:16:13.95/vblo/04,712.99,yes,locked 2006.224.08:16:13.95/vblo/05,744.99,yes,locked 2006.224.08:16:13.95/vblo/06,752.99,yes,locked 2006.224.08:16:13.95/vblo/07,734.99,yes,locked 2006.224.08:16:13.95/vblo/08,744.99,yes,locked 2006.224.08:16:14.10/vabw/8 2006.224.08:16:14.25/vbbw/8 2006.224.08:16:14.39/xfe/off,on,15.2 2006.224.08:16:14.78/ifatt/23,28,28,28 2006.224.08:16:15.08/fmout-gps/S +4.57E-07 2006.224.08:16:15.12:!2006.224.08:17:10 2006.224.08:17:10.02:data_valid=off 2006.224.08:17:10.02:postob 2006.224.08:17:10.15/cable/+6.4354E-03 2006.224.08:17:10.15/wx/23.80,1004.6,100 2006.224.08:17:11.08/fmout-gps/S +4.54E-07 2006.224.08:17:11.08:scan_name=224-0818,k06224,60 2006.224.08:17:11.08:source=1417+385,141946.61,382148.5,2000.0,ccw 2006.224.08:17:11.15#flagr#flagr/antenna,new-source 2006.224.08:17:12.15:checkk5 2006.224.08:17:12.51/chk_autoobs//k5ts1/ autoobs is running! 2006.224.08:17:12.88/chk_autoobs//k5ts2/ autoobs is running! 2006.224.08:17:13.25/chk_autoobs//k5ts3/ autoobs is running! 2006.224.08:17:13.62/chk_autoobs//k5ts4/ autoobs is running! 2006.224.08:17:13.99/chk_obsdata//k5ts1/T2240816??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.224.08:17:14.36/chk_obsdata//k5ts2/T2240816??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.224.08:17:14.73/chk_obsdata//k5ts3/T2240816??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.224.08:17:15.09/chk_obsdata//k5ts4/T2240816??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.224.08:17:15.78/k5log//k5ts1_log_newline 2006.224.08:17:16.48/k5log//k5ts2_log_newline 2006.224.08:17:17.18/k5log//k5ts3_log_newline 2006.224.08:17:17.87/k5log//k5ts4_log_newline 2006.224.08:17:17.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.224.08:17:17.90:4f8m12a=2 2006.224.08:17:17.90$4f8m12a/echo=on 2006.224.08:17:17.90$4f8m12a/pcalon 2006.224.08:17:17.90$pcalon/"no phase cal control is implemented here 2006.224.08:17:17.90$4f8m12a/"tpicd=stop 2006.224.08:17:17.90$4f8m12a/vc4f8 2006.224.08:17:17.90$vc4f8/valo=1,532.99 2006.224.08:17:17.90#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.224.08:17:17.90#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.224.08:17:17.90#ibcon#ireg 17 cls_cnt 0 2006.224.08:17:17.90#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.224.08:17:17.90#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.224.08:17:17.90#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.224.08:17:17.90#ibcon#enter wrdev, iclass 24, count 0 2006.224.08:17:17.90#ibcon#first serial, iclass 24, count 0 2006.224.08:17:17.90#ibcon#enter sib2, iclass 24, count 0 2006.224.08:17:17.90#ibcon#flushed, iclass 24, count 0 2006.224.08:17:17.90#ibcon#about to write, iclass 24, count 0 2006.224.08:17:17.90#ibcon#wrote, iclass 24, count 0 2006.224.08:17:17.90#ibcon#about to read 3, iclass 24, count 0 2006.224.08:17:17.91#ibcon#read 3, iclass 24, count 0 2006.224.08:17:17.91#ibcon#about to read 4, iclass 24, count 0 2006.224.08:17:17.91#ibcon#read 4, iclass 24, count 0 2006.224.08:17:17.91#ibcon#about to read 5, iclass 24, count 0 2006.224.08:17:17.91#ibcon#read 5, iclass 24, count 0 2006.224.08:17:17.91#ibcon#about to read 6, iclass 24, count 0 2006.224.08:17:17.91#ibcon#read 6, iclass 24, count 0 2006.224.08:17:17.91#ibcon#end of sib2, iclass 24, count 0 2006.224.08:17:17.91#ibcon#*mode == 0, iclass 24, count 0 2006.224.08:17:17.91#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.224.08:17:17.92#ibcon#[26=FRQ=01,532.99\r\n] 2006.224.08:17:17.92#ibcon#*before write, iclass 24, count 0 2006.224.08:17:17.92#ibcon#enter sib2, iclass 24, count 0 2006.224.08:17:17.92#ibcon#flushed, iclass 24, count 0 2006.224.08:17:17.92#ibcon#about to write, iclass 24, count 0 2006.224.08:17:17.92#ibcon#wrote, iclass 24, count 0 2006.224.08:17:17.92#ibcon#about to read 3, iclass 24, count 0 2006.224.08:17:17.96#ibcon#read 3, iclass 24, count 0 2006.224.08:17:17.96#ibcon#about to read 4, iclass 24, count 0 2006.224.08:17:17.96#ibcon#read 4, iclass 24, count 0 2006.224.08:17:17.96#ibcon#about to read 5, iclass 24, count 0 2006.224.08:17:17.97#ibcon#read 5, iclass 24, count 0 2006.224.08:17:17.97#ibcon#about to read 6, iclass 24, count 0 2006.224.08:17:17.97#ibcon#read 6, iclass 24, count 0 2006.224.08:17:17.97#ibcon#end of sib2, iclass 24, count 0 2006.224.08:17:17.97#ibcon#*after write, iclass 24, count 0 2006.224.08:17:17.97#ibcon#*before return 0, iclass 24, count 0 2006.224.08:17:17.97#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.224.08:17:17.97#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.224.08:17:17.97#ibcon#about to clear, iclass 24 cls_cnt 0 2006.224.08:17:17.97#ibcon#cleared, iclass 24 cls_cnt 0 2006.224.08:17:17.97$vc4f8/va=1,8 2006.224.08:17:17.97#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.224.08:17:17.97#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.224.08:17:17.97#ibcon#ireg 11 cls_cnt 2 2006.224.08:17:17.97#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.224.08:17:17.97#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.224.08:17:17.97#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.224.08:17:17.97#ibcon#enter wrdev, iclass 26, count 2 2006.224.08:17:17.97#ibcon#first serial, iclass 26, count 2 2006.224.08:17:17.97#ibcon#enter sib2, iclass 26, count 2 2006.224.08:17:17.97#ibcon#flushed, iclass 26, count 2 2006.224.08:17:17.97#ibcon#about to write, iclass 26, count 2 2006.224.08:17:17.97#ibcon#wrote, iclass 26, count 2 2006.224.08:17:17.97#ibcon#about to read 3, iclass 26, count 2 2006.224.08:17:17.98#ibcon#read 3, iclass 26, count 2 2006.224.08:17:17.98#ibcon#about to read 4, iclass 26, count 2 2006.224.08:17:17.98#ibcon#read 4, iclass 26, count 2 2006.224.08:17:17.98#ibcon#about to read 5, iclass 26, count 2 2006.224.08:17:17.98#ibcon#read 5, iclass 26, count 2 2006.224.08:17:17.98#ibcon#about to read 6, iclass 26, count 2 2006.224.08:17:17.98#ibcon#read 6, iclass 26, count 2 2006.224.08:17:17.98#ibcon#end of sib2, iclass 26, count 2 2006.224.08:17:17.98#ibcon#*mode == 0, iclass 26, count 2 2006.224.08:17:17.98#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.224.08:17:17.99#ibcon#[25=AT01-08\r\n] 2006.224.08:17:17.99#ibcon#*before write, iclass 26, count 2 2006.224.08:17:17.99#ibcon#enter sib2, iclass 26, count 2 2006.224.08:17:17.99#ibcon#flushed, iclass 26, count 2 2006.224.08:17:17.99#ibcon#about to write, iclass 26, count 2 2006.224.08:17:17.99#ibcon#wrote, iclass 26, count 2 2006.224.08:17:17.99#ibcon#about to read 3, iclass 26, count 2 2006.224.08:17:18.01#ibcon#read 3, iclass 26, count 2 2006.224.08:17:18.01#ibcon#about to read 4, iclass 26, count 2 2006.224.08:17:18.01#ibcon#read 4, iclass 26, count 2 2006.224.08:17:18.01#ibcon#about to read 5, iclass 26, count 2 2006.224.08:17:18.01#ibcon#read 5, iclass 26, count 2 2006.224.08:17:18.01#ibcon#about to read 6, iclass 26, count 2 2006.224.08:17:18.01#ibcon#read 6, iclass 26, count 2 2006.224.08:17:18.01#ibcon#end of sib2, iclass 26, count 2 2006.224.08:17:18.01#ibcon#*after write, iclass 26, count 2 2006.224.08:17:18.02#ibcon#*before return 0, iclass 26, count 2 2006.224.08:17:18.02#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.224.08:17:18.02#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.224.08:17:18.02#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.224.08:17:18.02#ibcon#ireg 7 cls_cnt 0 2006.224.08:17:18.02#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.224.08:17:18.14#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.224.08:17:18.14#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.224.08:17:18.14#ibcon#enter wrdev, iclass 26, count 0 2006.224.08:17:18.14#ibcon#first serial, iclass 26, count 0 2006.224.08:17:18.14#ibcon#enter sib2, iclass 26, count 0 2006.224.08:17:18.14#ibcon#flushed, iclass 26, count 0 2006.224.08:17:18.14#ibcon#about to write, iclass 26, count 0 2006.224.08:17:18.14#ibcon#wrote, iclass 26, count 0 2006.224.08:17:18.14#ibcon#about to read 3, iclass 26, count 0 2006.224.08:17:18.15#ibcon#read 3, iclass 26, count 0 2006.224.08:17:18.15#ibcon#about to read 4, iclass 26, count 0 2006.224.08:17:18.15#ibcon#read 4, iclass 26, count 0 2006.224.08:17:18.15#ibcon#about to read 5, iclass 26, count 0 2006.224.08:17:18.15#ibcon#read 5, iclass 26, count 0 2006.224.08:17:18.15#ibcon#about to read 6, iclass 26, count 0 2006.224.08:17:18.15#ibcon#read 6, iclass 26, count 0 2006.224.08:17:18.15#ibcon#end of sib2, iclass 26, count 0 2006.224.08:17:18.15#ibcon#*mode == 0, iclass 26, count 0 2006.224.08:17:18.16#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.224.08:17:18.16#ibcon#[25=USB\r\n] 2006.224.08:17:18.16#ibcon#*before write, iclass 26, count 0 2006.224.08:17:18.16#ibcon#enter sib2, iclass 26, count 0 2006.224.08:17:18.16#ibcon#flushed, iclass 26, count 0 2006.224.08:17:18.16#ibcon#about to write, iclass 26, count 0 2006.224.08:17:18.16#ibcon#wrote, iclass 26, count 0 2006.224.08:17:18.16#ibcon#about to read 3, iclass 26, count 0 2006.224.08:17:18.18#ibcon#read 3, iclass 26, count 0 2006.224.08:17:18.18#ibcon#about to read 4, iclass 26, count 0 2006.224.08:17:18.18#ibcon#read 4, iclass 26, count 0 2006.224.08:17:18.18#ibcon#about to read 5, iclass 26, count 0 2006.224.08:17:18.18#ibcon#read 5, iclass 26, count 0 2006.224.08:17:18.18#ibcon#about to read 6, iclass 26, count 0 2006.224.08:17:18.18#ibcon#read 6, iclass 26, count 0 2006.224.08:17:18.18#ibcon#end of sib2, iclass 26, count 0 2006.224.08:17:18.18#ibcon#*after write, iclass 26, count 0 2006.224.08:17:18.18#ibcon#*before return 0, iclass 26, count 0 2006.224.08:17:18.19#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.224.08:17:18.19#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.224.08:17:18.19#ibcon#about to clear, iclass 26 cls_cnt 0 2006.224.08:17:18.19#ibcon#cleared, iclass 26 cls_cnt 0 2006.224.08:17:18.19$vc4f8/valo=2,572.99 2006.224.08:17:18.19#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.224.08:17:18.19#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.224.08:17:18.19#ibcon#ireg 17 cls_cnt 0 2006.224.08:17:18.19#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.224.08:17:18.19#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.224.08:17:18.19#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.224.08:17:18.19#ibcon#enter wrdev, iclass 28, count 0 2006.224.08:17:18.19#ibcon#first serial, iclass 28, count 0 2006.224.08:17:18.19#ibcon#enter sib2, iclass 28, count 0 2006.224.08:17:18.19#ibcon#flushed, iclass 28, count 0 2006.224.08:17:18.19#ibcon#about to write, iclass 28, count 0 2006.224.08:17:18.19#ibcon#wrote, iclass 28, count 0 2006.224.08:17:18.19#ibcon#about to read 3, iclass 28, count 0 2006.224.08:17:18.21#ibcon#read 3, iclass 28, count 0 2006.224.08:17:18.21#ibcon#about to read 4, iclass 28, count 0 2006.224.08:17:18.21#ibcon#read 4, iclass 28, count 0 2006.224.08:17:18.21#ibcon#about to read 5, iclass 28, count 0 2006.224.08:17:18.21#ibcon#read 5, iclass 28, count 0 2006.224.08:17:18.21#ibcon#about to read 6, iclass 28, count 0 2006.224.08:17:18.21#ibcon#read 6, iclass 28, count 0 2006.224.08:17:18.21#ibcon#end of sib2, iclass 28, count 0 2006.224.08:17:18.21#ibcon#*mode == 0, iclass 28, count 0 2006.224.08:17:18.21#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.224.08:17:18.21#ibcon#[26=FRQ=02,572.99\r\n] 2006.224.08:17:18.21#ibcon#*before write, iclass 28, count 0 2006.224.08:17:18.21#ibcon#enter sib2, iclass 28, count 0 2006.224.08:17:18.21#ibcon#flushed, iclass 28, count 0 2006.224.08:17:18.21#ibcon#about to write, iclass 28, count 0 2006.224.08:17:18.21#ibcon#wrote, iclass 28, count 0 2006.224.08:17:18.21#ibcon#about to read 3, iclass 28, count 0 2006.224.08:17:18.25#ibcon#read 3, iclass 28, count 0 2006.224.08:17:18.25#ibcon#about to read 4, iclass 28, count 0 2006.224.08:17:18.25#ibcon#read 4, iclass 28, count 0 2006.224.08:17:18.25#ibcon#about to read 5, iclass 28, count 0 2006.224.08:17:18.25#ibcon#read 5, iclass 28, count 0 2006.224.08:17:18.25#ibcon#about to read 6, iclass 28, count 0 2006.224.08:17:18.25#ibcon#read 6, iclass 28, count 0 2006.224.08:17:18.26#ibcon#end of sib2, iclass 28, count 0 2006.224.08:17:18.26#ibcon#*after write, iclass 28, count 0 2006.224.08:17:18.26#ibcon#*before return 0, iclass 28, count 0 2006.224.08:17:18.26#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.224.08:17:18.26#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.224.08:17:18.26#ibcon#about to clear, iclass 28 cls_cnt 0 2006.224.08:17:18.26#ibcon#cleared, iclass 28 cls_cnt 0 2006.224.08:17:18.26$vc4f8/va=2,7 2006.224.08:17:18.26#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.224.08:17:18.26#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.224.08:17:18.26#ibcon#ireg 11 cls_cnt 2 2006.224.08:17:18.26#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.224.08:17:18.31#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.224.08:17:18.31#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.224.08:17:18.31#ibcon#enter wrdev, iclass 30, count 2 2006.224.08:17:18.31#ibcon#first serial, iclass 30, count 2 2006.224.08:17:18.31#ibcon#enter sib2, iclass 30, count 2 2006.224.08:17:18.31#ibcon#flushed, iclass 30, count 2 2006.224.08:17:18.31#ibcon#about to write, iclass 30, count 2 2006.224.08:17:18.31#ibcon#wrote, iclass 30, count 2 2006.224.08:17:18.31#ibcon#about to read 3, iclass 30, count 2 2006.224.08:17:18.32#ibcon#read 3, iclass 30, count 2 2006.224.08:17:18.32#ibcon#about to read 4, iclass 30, count 2 2006.224.08:17:18.32#ibcon#read 4, iclass 30, count 2 2006.224.08:17:18.32#ibcon#about to read 5, iclass 30, count 2 2006.224.08:17:18.32#ibcon#read 5, iclass 30, count 2 2006.224.08:17:18.32#ibcon#about to read 6, iclass 30, count 2 2006.224.08:17:18.32#ibcon#read 6, iclass 30, count 2 2006.224.08:17:18.32#ibcon#end of sib2, iclass 30, count 2 2006.224.08:17:18.33#ibcon#*mode == 0, iclass 30, count 2 2006.224.08:17:18.33#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.224.08:17:18.33#ibcon#[25=AT02-07\r\n] 2006.224.08:17:18.33#ibcon#*before write, iclass 30, count 2 2006.224.08:17:18.33#ibcon#enter sib2, iclass 30, count 2 2006.224.08:17:18.33#ibcon#flushed, iclass 30, count 2 2006.224.08:17:18.33#ibcon#about to write, iclass 30, count 2 2006.224.08:17:18.33#ibcon#wrote, iclass 30, count 2 2006.224.08:17:18.33#ibcon#about to read 3, iclass 30, count 2 2006.224.08:17:18.35#ibcon#read 3, iclass 30, count 2 2006.224.08:17:18.35#ibcon#about to read 4, iclass 30, count 2 2006.224.08:17:18.35#ibcon#read 4, iclass 30, count 2 2006.224.08:17:18.35#ibcon#about to read 5, iclass 30, count 2 2006.224.08:17:18.35#ibcon#read 5, iclass 30, count 2 2006.224.08:17:18.35#ibcon#about to read 6, iclass 30, count 2 2006.224.08:17:18.35#ibcon#read 6, iclass 30, count 2 2006.224.08:17:18.35#ibcon#end of sib2, iclass 30, count 2 2006.224.08:17:18.36#ibcon#*after write, iclass 30, count 2 2006.224.08:17:18.36#ibcon#*before return 0, iclass 30, count 2 2006.224.08:17:18.36#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.224.08:17:18.36#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.224.08:17:18.36#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.224.08:17:18.36#ibcon#ireg 7 cls_cnt 0 2006.224.08:17:18.36#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.224.08:17:18.47#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.224.08:17:18.47#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.224.08:17:18.47#ibcon#enter wrdev, iclass 30, count 0 2006.224.08:17:18.47#ibcon#first serial, iclass 30, count 0 2006.224.08:17:18.47#ibcon#enter sib2, iclass 30, count 0 2006.224.08:17:18.47#ibcon#flushed, iclass 30, count 0 2006.224.08:17:18.47#ibcon#about to write, iclass 30, count 0 2006.224.08:17:18.47#ibcon#wrote, iclass 30, count 0 2006.224.08:17:18.47#ibcon#about to read 3, iclass 30, count 0 2006.224.08:17:18.49#ibcon#read 3, iclass 30, count 0 2006.224.08:17:18.49#ibcon#about to read 4, iclass 30, count 0 2006.224.08:17:18.49#ibcon#read 4, iclass 30, count 0 2006.224.08:17:18.49#ibcon#about to read 5, iclass 30, count 0 2006.224.08:17:18.49#ibcon#read 5, iclass 30, count 0 2006.224.08:17:18.49#ibcon#about to read 6, iclass 30, count 0 2006.224.08:17:18.49#ibcon#read 6, iclass 30, count 0 2006.224.08:17:18.49#ibcon#end of sib2, iclass 30, count 0 2006.224.08:17:18.49#ibcon#*mode == 0, iclass 30, count 0 2006.224.08:17:18.49#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.224.08:17:18.50#ibcon#[25=USB\r\n] 2006.224.08:17:18.50#ibcon#*before write, iclass 30, count 0 2006.224.08:17:18.50#ibcon#enter sib2, iclass 30, count 0 2006.224.08:17:18.50#ibcon#flushed, iclass 30, count 0 2006.224.08:17:18.50#ibcon#about to write, iclass 30, count 0 2006.224.08:17:18.50#ibcon#wrote, iclass 30, count 0 2006.224.08:17:18.50#ibcon#about to read 3, iclass 30, count 0 2006.224.08:17:18.52#ibcon#read 3, iclass 30, count 0 2006.224.08:17:18.52#ibcon#about to read 4, iclass 30, count 0 2006.224.08:17:18.52#ibcon#read 4, iclass 30, count 0 2006.224.08:17:18.52#ibcon#about to read 5, iclass 30, count 0 2006.224.08:17:18.52#ibcon#read 5, iclass 30, count 0 2006.224.08:17:18.52#ibcon#about to read 6, iclass 30, count 0 2006.224.08:17:18.52#ibcon#read 6, iclass 30, count 0 2006.224.08:17:18.52#ibcon#end of sib2, iclass 30, count 0 2006.224.08:17:18.52#ibcon#*after write, iclass 30, count 0 2006.224.08:17:18.52#ibcon#*before return 0, iclass 30, count 0 2006.224.08:17:18.53#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.224.08:17:18.53#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.224.08:17:18.53#ibcon#about to clear, iclass 30 cls_cnt 0 2006.224.08:17:18.53#ibcon#cleared, iclass 30 cls_cnt 0 2006.224.08:17:18.53$vc4f8/valo=3,672.99 2006.224.08:17:18.53#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.224.08:17:18.53#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.224.08:17:18.53#ibcon#ireg 17 cls_cnt 0 2006.224.08:17:18.53#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.224.08:17:18.53#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.224.08:17:18.53#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.224.08:17:18.53#ibcon#enter wrdev, iclass 32, count 0 2006.224.08:17:18.53#ibcon#first serial, iclass 32, count 0 2006.224.08:17:18.53#ibcon#enter sib2, iclass 32, count 0 2006.224.08:17:18.53#ibcon#flushed, iclass 32, count 0 2006.224.08:17:18.53#ibcon#about to write, iclass 32, count 0 2006.224.08:17:18.53#ibcon#wrote, iclass 32, count 0 2006.224.08:17:18.53#ibcon#about to read 3, iclass 32, count 0 2006.224.08:17:18.55#ibcon#read 3, iclass 32, count 0 2006.224.08:17:18.55#ibcon#about to read 4, iclass 32, count 0 2006.224.08:17:18.55#ibcon#read 4, iclass 32, count 0 2006.224.08:17:18.55#ibcon#about to read 5, iclass 32, count 0 2006.224.08:17:18.55#ibcon#read 5, iclass 32, count 0 2006.224.08:17:18.55#ibcon#about to read 6, iclass 32, count 0 2006.224.08:17:18.55#ibcon#read 6, iclass 32, count 0 2006.224.08:17:18.55#ibcon#end of sib2, iclass 32, count 0 2006.224.08:17:18.55#ibcon#*mode == 0, iclass 32, count 0 2006.224.08:17:18.55#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.224.08:17:18.55#ibcon#[26=FRQ=03,672.99\r\n] 2006.224.08:17:18.55#ibcon#*before write, iclass 32, count 0 2006.224.08:17:18.55#ibcon#enter sib2, iclass 32, count 0 2006.224.08:17:18.55#ibcon#flushed, iclass 32, count 0 2006.224.08:17:18.55#ibcon#about to write, iclass 32, count 0 2006.224.08:17:18.55#ibcon#wrote, iclass 32, count 0 2006.224.08:17:18.55#ibcon#about to read 3, iclass 32, count 0 2006.224.08:17:18.59#ibcon#read 3, iclass 32, count 0 2006.224.08:17:18.59#ibcon#about to read 4, iclass 32, count 0 2006.224.08:17:18.59#ibcon#read 4, iclass 32, count 0 2006.224.08:17:18.59#ibcon#about to read 5, iclass 32, count 0 2006.224.08:17:18.59#ibcon#read 5, iclass 32, count 0 2006.224.08:17:18.59#ibcon#about to read 6, iclass 32, count 0 2006.224.08:17:18.59#ibcon#read 6, iclass 32, count 0 2006.224.08:17:18.60#ibcon#end of sib2, iclass 32, count 0 2006.224.08:17:18.60#ibcon#*after write, iclass 32, count 0 2006.224.08:17:18.60#ibcon#*before return 0, iclass 32, count 0 2006.224.08:17:18.60#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.224.08:17:18.60#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.224.08:17:18.60#ibcon#about to clear, iclass 32 cls_cnt 0 2006.224.08:17:18.60#ibcon#cleared, iclass 32 cls_cnt 0 2006.224.08:17:18.60$vc4f8/va=3,6 2006.224.08:17:18.60#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.224.08:17:18.60#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.224.08:17:18.60#ibcon#ireg 11 cls_cnt 2 2006.224.08:17:18.60#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.224.08:17:18.65#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.224.08:17:18.65#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.224.08:17:18.65#ibcon#enter wrdev, iclass 34, count 2 2006.224.08:17:18.65#ibcon#first serial, iclass 34, count 2 2006.224.08:17:18.65#ibcon#enter sib2, iclass 34, count 2 2006.224.08:17:18.65#ibcon#flushed, iclass 34, count 2 2006.224.08:17:18.65#ibcon#about to write, iclass 34, count 2 2006.224.08:17:18.65#ibcon#wrote, iclass 34, count 2 2006.224.08:17:18.65#ibcon#about to read 3, iclass 34, count 2 2006.224.08:17:18.66#ibcon#read 3, iclass 34, count 2 2006.224.08:17:18.66#ibcon#about to read 4, iclass 34, count 2 2006.224.08:17:18.66#ibcon#read 4, iclass 34, count 2 2006.224.08:17:18.66#ibcon#about to read 5, iclass 34, count 2 2006.224.08:17:18.66#ibcon#read 5, iclass 34, count 2 2006.224.08:17:18.66#ibcon#about to read 6, iclass 34, count 2 2006.224.08:17:18.66#ibcon#read 6, iclass 34, count 2 2006.224.08:17:18.66#ibcon#end of sib2, iclass 34, count 2 2006.224.08:17:18.67#ibcon#*mode == 0, iclass 34, count 2 2006.224.08:17:18.67#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.224.08:17:18.67#ibcon#[25=AT03-06\r\n] 2006.224.08:17:18.67#ibcon#*before write, iclass 34, count 2 2006.224.08:17:18.67#ibcon#enter sib2, iclass 34, count 2 2006.224.08:17:18.67#ibcon#flushed, iclass 34, count 2 2006.224.08:17:18.67#ibcon#about to write, iclass 34, count 2 2006.224.08:17:18.67#ibcon#wrote, iclass 34, count 2 2006.224.08:17:18.67#ibcon#about to read 3, iclass 34, count 2 2006.224.08:17:18.69#ibcon#read 3, iclass 34, count 2 2006.224.08:17:18.69#ibcon#about to read 4, iclass 34, count 2 2006.224.08:17:18.69#ibcon#read 4, iclass 34, count 2 2006.224.08:17:18.69#ibcon#about to read 5, iclass 34, count 2 2006.224.08:17:18.69#ibcon#read 5, iclass 34, count 2 2006.224.08:17:18.69#ibcon#about to read 6, iclass 34, count 2 2006.224.08:17:18.69#ibcon#read 6, iclass 34, count 2 2006.224.08:17:18.69#ibcon#end of sib2, iclass 34, count 2 2006.224.08:17:18.70#ibcon#*after write, iclass 34, count 2 2006.224.08:17:18.70#ibcon#*before return 0, iclass 34, count 2 2006.224.08:17:18.70#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.224.08:17:18.70#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.224.08:17:18.70#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.224.08:17:18.70#ibcon#ireg 7 cls_cnt 0 2006.224.08:17:18.70#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.224.08:17:18.81#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.224.08:17:18.81#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.224.08:17:18.81#ibcon#enter wrdev, iclass 34, count 0 2006.224.08:17:18.81#ibcon#first serial, iclass 34, count 0 2006.224.08:17:18.81#ibcon#enter sib2, iclass 34, count 0 2006.224.08:17:18.81#ibcon#flushed, iclass 34, count 0 2006.224.08:17:18.81#ibcon#about to write, iclass 34, count 0 2006.224.08:17:18.81#ibcon#wrote, iclass 34, count 0 2006.224.08:17:18.81#ibcon#about to read 3, iclass 34, count 0 2006.224.08:17:18.83#ibcon#read 3, iclass 34, count 0 2006.224.08:17:18.83#ibcon#about to read 4, iclass 34, count 0 2006.224.08:17:18.83#ibcon#read 4, iclass 34, count 0 2006.224.08:17:18.83#ibcon#about to read 5, iclass 34, count 0 2006.224.08:17:18.83#ibcon#read 5, iclass 34, count 0 2006.224.08:17:18.83#ibcon#about to read 6, iclass 34, count 0 2006.224.08:17:18.83#ibcon#read 6, iclass 34, count 0 2006.224.08:17:18.83#ibcon#end of sib2, iclass 34, count 0 2006.224.08:17:18.83#ibcon#*mode == 0, iclass 34, count 0 2006.224.08:17:18.83#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.224.08:17:18.84#ibcon#[25=USB\r\n] 2006.224.08:17:18.84#ibcon#*before write, iclass 34, count 0 2006.224.08:17:18.84#ibcon#enter sib2, iclass 34, count 0 2006.224.08:17:18.84#ibcon#flushed, iclass 34, count 0 2006.224.08:17:18.84#ibcon#about to write, iclass 34, count 0 2006.224.08:17:18.84#ibcon#wrote, iclass 34, count 0 2006.224.08:17:18.84#ibcon#about to read 3, iclass 34, count 0 2006.224.08:17:18.86#ibcon#read 3, iclass 34, count 0 2006.224.08:17:18.86#ibcon#about to read 4, iclass 34, count 0 2006.224.08:17:18.86#ibcon#read 4, iclass 34, count 0 2006.224.08:17:18.86#ibcon#about to read 5, iclass 34, count 0 2006.224.08:17:18.86#ibcon#read 5, iclass 34, count 0 2006.224.08:17:18.86#ibcon#about to read 6, iclass 34, count 0 2006.224.08:17:18.86#ibcon#read 6, iclass 34, count 0 2006.224.08:17:18.86#ibcon#end of sib2, iclass 34, count 0 2006.224.08:17:18.86#ibcon#*after write, iclass 34, count 0 2006.224.08:17:18.86#ibcon#*before return 0, iclass 34, count 0 2006.224.08:17:18.87#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.224.08:17:18.87#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.224.08:17:18.87#ibcon#about to clear, iclass 34 cls_cnt 0 2006.224.08:17:18.87#ibcon#cleared, iclass 34 cls_cnt 0 2006.224.08:17:18.87$vc4f8/valo=4,832.99 2006.224.08:17:18.87#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.224.08:17:18.87#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.224.08:17:18.87#ibcon#ireg 17 cls_cnt 0 2006.224.08:17:18.87#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.224.08:17:18.87#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.224.08:17:18.87#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.224.08:17:18.87#ibcon#enter wrdev, iclass 36, count 0 2006.224.08:17:18.87#ibcon#first serial, iclass 36, count 0 2006.224.08:17:18.87#ibcon#enter sib2, iclass 36, count 0 2006.224.08:17:18.87#ibcon#flushed, iclass 36, count 0 2006.224.08:17:18.87#ibcon#about to write, iclass 36, count 0 2006.224.08:17:18.87#ibcon#wrote, iclass 36, count 0 2006.224.08:17:18.87#ibcon#about to read 3, iclass 36, count 0 2006.224.08:17:18.89#ibcon#read 3, iclass 36, count 0 2006.224.08:17:18.89#ibcon#about to read 4, iclass 36, count 0 2006.224.08:17:18.89#ibcon#read 4, iclass 36, count 0 2006.224.08:17:18.89#ibcon#about to read 5, iclass 36, count 0 2006.224.08:17:18.89#ibcon#read 5, iclass 36, count 0 2006.224.08:17:18.89#ibcon#about to read 6, iclass 36, count 0 2006.224.08:17:18.89#ibcon#read 6, iclass 36, count 0 2006.224.08:17:18.89#ibcon#end of sib2, iclass 36, count 0 2006.224.08:17:18.89#ibcon#*mode == 0, iclass 36, count 0 2006.224.08:17:18.89#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.224.08:17:18.89#ibcon#[26=FRQ=04,832.99\r\n] 2006.224.08:17:18.89#ibcon#*before write, iclass 36, count 0 2006.224.08:17:18.89#ibcon#enter sib2, iclass 36, count 0 2006.224.08:17:18.89#ibcon#flushed, iclass 36, count 0 2006.224.08:17:18.89#ibcon#about to write, iclass 36, count 0 2006.224.08:17:18.89#ibcon#wrote, iclass 36, count 0 2006.224.08:17:18.89#ibcon#about to read 3, iclass 36, count 0 2006.224.08:17:18.93#ibcon#read 3, iclass 36, count 0 2006.224.08:17:18.93#ibcon#about to read 4, iclass 36, count 0 2006.224.08:17:18.93#ibcon#read 4, iclass 36, count 0 2006.224.08:17:18.93#ibcon#about to read 5, iclass 36, count 0 2006.224.08:17:18.93#ibcon#read 5, iclass 36, count 0 2006.224.08:17:18.93#ibcon#about to read 6, iclass 36, count 0 2006.224.08:17:18.93#ibcon#read 6, iclass 36, count 0 2006.224.08:17:18.94#ibcon#end of sib2, iclass 36, count 0 2006.224.08:17:18.94#ibcon#*after write, iclass 36, count 0 2006.224.08:17:18.94#ibcon#*before return 0, iclass 36, count 0 2006.224.08:17:18.94#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.224.08:17:18.94#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.224.08:17:18.94#ibcon#about to clear, iclass 36 cls_cnt 0 2006.224.08:17:18.94#ibcon#cleared, iclass 36 cls_cnt 0 2006.224.08:17:18.94$vc4f8/va=4,7 2006.224.08:17:18.94#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.224.08:17:18.94#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.224.08:17:18.94#ibcon#ireg 11 cls_cnt 2 2006.224.08:17:18.94#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.224.08:17:18.98#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.224.08:17:18.98#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.224.08:17:18.98#ibcon#enter wrdev, iclass 38, count 2 2006.224.08:17:18.98#ibcon#first serial, iclass 38, count 2 2006.224.08:17:18.98#ibcon#enter sib2, iclass 38, count 2 2006.224.08:17:18.98#ibcon#flushed, iclass 38, count 2 2006.224.08:17:18.98#ibcon#about to write, iclass 38, count 2 2006.224.08:17:18.98#ibcon#wrote, iclass 38, count 2 2006.224.08:17:18.98#ibcon#about to read 3, iclass 38, count 2 2006.224.08:17:19.00#ibcon#read 3, iclass 38, count 2 2006.224.08:17:19.00#ibcon#about to read 4, iclass 38, count 2 2006.224.08:17:19.00#ibcon#read 4, iclass 38, count 2 2006.224.08:17:19.00#ibcon#about to read 5, iclass 38, count 2 2006.224.08:17:19.00#ibcon#read 5, iclass 38, count 2 2006.224.08:17:19.00#ibcon#about to read 6, iclass 38, count 2 2006.224.08:17:19.00#ibcon#read 6, iclass 38, count 2 2006.224.08:17:19.00#ibcon#end of sib2, iclass 38, count 2 2006.224.08:17:19.00#ibcon#*mode == 0, iclass 38, count 2 2006.224.08:17:19.00#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.224.08:17:19.01#ibcon#[25=AT04-07\r\n] 2006.224.08:17:19.01#ibcon#*before write, iclass 38, count 2 2006.224.08:17:19.01#ibcon#enter sib2, iclass 38, count 2 2006.224.08:17:19.01#ibcon#flushed, iclass 38, count 2 2006.224.08:17:19.01#ibcon#about to write, iclass 38, count 2 2006.224.08:17:19.01#ibcon#wrote, iclass 38, count 2 2006.224.08:17:19.01#ibcon#about to read 3, iclass 38, count 2 2006.224.08:17:19.03#ibcon#read 3, iclass 38, count 2 2006.224.08:17:19.03#ibcon#about to read 4, iclass 38, count 2 2006.224.08:17:19.03#ibcon#read 4, iclass 38, count 2 2006.224.08:17:19.03#ibcon#about to read 5, iclass 38, count 2 2006.224.08:17:19.03#ibcon#read 5, iclass 38, count 2 2006.224.08:17:19.03#ibcon#about to read 6, iclass 38, count 2 2006.224.08:17:19.03#ibcon#read 6, iclass 38, count 2 2006.224.08:17:19.03#ibcon#end of sib2, iclass 38, count 2 2006.224.08:17:19.04#ibcon#*after write, iclass 38, count 2 2006.224.08:17:19.04#ibcon#*before return 0, iclass 38, count 2 2006.224.08:17:19.04#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.224.08:17:19.04#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.224.08:17:19.04#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.224.08:17:19.04#ibcon#ireg 7 cls_cnt 0 2006.224.08:17:19.04#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.224.08:17:19.15#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.224.08:17:19.15#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.224.08:17:19.15#ibcon#enter wrdev, iclass 38, count 0 2006.224.08:17:19.15#ibcon#first serial, iclass 38, count 0 2006.224.08:17:19.15#ibcon#enter sib2, iclass 38, count 0 2006.224.08:17:19.15#ibcon#flushed, iclass 38, count 0 2006.224.08:17:19.15#ibcon#about to write, iclass 38, count 0 2006.224.08:17:19.15#ibcon#wrote, iclass 38, count 0 2006.224.08:17:19.15#ibcon#about to read 3, iclass 38, count 0 2006.224.08:17:19.17#ibcon#read 3, iclass 38, count 0 2006.224.08:17:19.17#ibcon#about to read 4, iclass 38, count 0 2006.224.08:17:19.17#ibcon#read 4, iclass 38, count 0 2006.224.08:17:19.17#ibcon#about to read 5, iclass 38, count 0 2006.224.08:17:19.17#ibcon#read 5, iclass 38, count 0 2006.224.08:17:19.17#ibcon#about to read 6, iclass 38, count 0 2006.224.08:17:19.17#ibcon#read 6, iclass 38, count 0 2006.224.08:17:19.17#ibcon#end of sib2, iclass 38, count 0 2006.224.08:17:19.17#ibcon#*mode == 0, iclass 38, count 0 2006.224.08:17:19.17#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.224.08:17:19.18#ibcon#[25=USB\r\n] 2006.224.08:17:19.18#ibcon#*before write, iclass 38, count 0 2006.224.08:17:19.18#ibcon#enter sib2, iclass 38, count 0 2006.224.08:17:19.18#ibcon#flushed, iclass 38, count 0 2006.224.08:17:19.18#ibcon#about to write, iclass 38, count 0 2006.224.08:17:19.18#ibcon#wrote, iclass 38, count 0 2006.224.08:17:19.18#ibcon#about to read 3, iclass 38, count 0 2006.224.08:17:19.20#ibcon#read 3, iclass 38, count 0 2006.224.08:17:19.20#ibcon#about to read 4, iclass 38, count 0 2006.224.08:17:19.20#ibcon#read 4, iclass 38, count 0 2006.224.08:17:19.20#ibcon#about to read 5, iclass 38, count 0 2006.224.08:17:19.20#ibcon#read 5, iclass 38, count 0 2006.224.08:17:19.20#ibcon#about to read 6, iclass 38, count 0 2006.224.08:17:19.20#ibcon#read 6, iclass 38, count 0 2006.224.08:17:19.20#ibcon#end of sib2, iclass 38, count 0 2006.224.08:17:19.20#ibcon#*after write, iclass 38, count 0 2006.224.08:17:19.20#ibcon#*before return 0, iclass 38, count 0 2006.224.08:17:19.21#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.224.08:17:19.21#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.224.08:17:19.21#ibcon#about to clear, iclass 38 cls_cnt 0 2006.224.08:17:19.21#ibcon#cleared, iclass 38 cls_cnt 0 2006.224.08:17:19.21$vc4f8/valo=5,652.99 2006.224.08:17:19.21#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.224.08:17:19.21#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.224.08:17:19.21#ibcon#ireg 17 cls_cnt 0 2006.224.08:17:19.21#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.224.08:17:19.21#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.224.08:17:19.21#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.224.08:17:19.21#ibcon#enter wrdev, iclass 40, count 0 2006.224.08:17:19.21#ibcon#first serial, iclass 40, count 0 2006.224.08:17:19.21#ibcon#enter sib2, iclass 40, count 0 2006.224.08:17:19.21#ibcon#flushed, iclass 40, count 0 2006.224.08:17:19.21#ibcon#about to write, iclass 40, count 0 2006.224.08:17:19.21#ibcon#wrote, iclass 40, count 0 2006.224.08:17:19.21#ibcon#about to read 3, iclass 40, count 0 2006.224.08:17:19.22#ibcon#read 3, iclass 40, count 0 2006.224.08:17:19.22#ibcon#about to read 4, iclass 40, count 0 2006.224.08:17:19.22#ibcon#read 4, iclass 40, count 0 2006.224.08:17:19.22#ibcon#about to read 5, iclass 40, count 0 2006.224.08:17:19.22#ibcon#read 5, iclass 40, count 0 2006.224.08:17:19.22#ibcon#about to read 6, iclass 40, count 0 2006.224.08:17:19.22#ibcon#read 6, iclass 40, count 0 2006.224.08:17:19.22#ibcon#end of sib2, iclass 40, count 0 2006.224.08:17:19.22#ibcon#*mode == 0, iclass 40, count 0 2006.224.08:17:19.23#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.224.08:17:19.23#ibcon#[26=FRQ=05,652.99\r\n] 2006.224.08:17:19.23#ibcon#*before write, iclass 40, count 0 2006.224.08:17:19.23#ibcon#enter sib2, iclass 40, count 0 2006.224.08:17:19.23#ibcon#flushed, iclass 40, count 0 2006.224.08:17:19.23#ibcon#about to write, iclass 40, count 0 2006.224.08:17:19.23#ibcon#wrote, iclass 40, count 0 2006.224.08:17:19.23#ibcon#about to read 3, iclass 40, count 0 2006.224.08:17:19.26#ibcon#read 3, iclass 40, count 0 2006.224.08:17:19.26#ibcon#about to read 4, iclass 40, count 0 2006.224.08:17:19.26#ibcon#read 4, iclass 40, count 0 2006.224.08:17:19.26#ibcon#about to read 5, iclass 40, count 0 2006.224.08:17:19.26#ibcon#read 5, iclass 40, count 0 2006.224.08:17:19.26#ibcon#about to read 6, iclass 40, count 0 2006.224.08:17:19.26#ibcon#read 6, iclass 40, count 0 2006.224.08:17:19.26#ibcon#end of sib2, iclass 40, count 0 2006.224.08:17:19.26#ibcon#*after write, iclass 40, count 0 2006.224.08:17:19.26#ibcon#*before return 0, iclass 40, count 0 2006.224.08:17:19.27#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.224.08:17:19.27#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.224.08:17:19.27#ibcon#about to clear, iclass 40 cls_cnt 0 2006.224.08:17:19.27#ibcon#cleared, iclass 40 cls_cnt 0 2006.224.08:17:19.27$vc4f8/va=5,7 2006.224.08:17:19.27#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.224.08:17:19.27#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.224.08:17:19.27#ibcon#ireg 11 cls_cnt 2 2006.224.08:17:19.27#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.224.08:17:19.32#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.224.08:17:19.32#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.224.08:17:19.32#ibcon#enter wrdev, iclass 4, count 2 2006.224.08:17:19.32#ibcon#first serial, iclass 4, count 2 2006.224.08:17:19.32#ibcon#enter sib2, iclass 4, count 2 2006.224.08:17:19.32#ibcon#flushed, iclass 4, count 2 2006.224.08:17:19.32#ibcon#about to write, iclass 4, count 2 2006.224.08:17:19.32#ibcon#wrote, iclass 4, count 2 2006.224.08:17:19.32#ibcon#about to read 3, iclass 4, count 2 2006.224.08:17:19.34#ibcon#read 3, iclass 4, count 2 2006.224.08:17:19.34#ibcon#about to read 4, iclass 4, count 2 2006.224.08:17:19.34#ibcon#read 4, iclass 4, count 2 2006.224.08:17:19.34#ibcon#about to read 5, iclass 4, count 2 2006.224.08:17:19.34#ibcon#read 5, iclass 4, count 2 2006.224.08:17:19.34#ibcon#about to read 6, iclass 4, count 2 2006.224.08:17:19.34#ibcon#read 6, iclass 4, count 2 2006.224.08:17:19.34#ibcon#end of sib2, iclass 4, count 2 2006.224.08:17:19.34#ibcon#*mode == 0, iclass 4, count 2 2006.224.08:17:19.34#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.224.08:17:19.35#ibcon#[25=AT05-07\r\n] 2006.224.08:17:19.35#ibcon#*before write, iclass 4, count 2 2006.224.08:17:19.35#ibcon#enter sib2, iclass 4, count 2 2006.224.08:17:19.35#ibcon#flushed, iclass 4, count 2 2006.224.08:17:19.35#ibcon#about to write, iclass 4, count 2 2006.224.08:17:19.35#ibcon#wrote, iclass 4, count 2 2006.224.08:17:19.35#ibcon#about to read 3, iclass 4, count 2 2006.224.08:17:19.37#ibcon#read 3, iclass 4, count 2 2006.224.08:17:19.37#ibcon#about to read 4, iclass 4, count 2 2006.224.08:17:19.37#ibcon#read 4, iclass 4, count 2 2006.224.08:17:19.37#ibcon#about to read 5, iclass 4, count 2 2006.224.08:17:19.37#ibcon#read 5, iclass 4, count 2 2006.224.08:17:19.37#ibcon#about to read 6, iclass 4, count 2 2006.224.08:17:19.37#ibcon#read 6, iclass 4, count 2 2006.224.08:17:19.37#ibcon#end of sib2, iclass 4, count 2 2006.224.08:17:19.37#ibcon#*after write, iclass 4, count 2 2006.224.08:17:19.37#ibcon#*before return 0, iclass 4, count 2 2006.224.08:17:19.38#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.224.08:17:19.38#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.224.08:17:19.38#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.224.08:17:19.38#ibcon#ireg 7 cls_cnt 0 2006.224.08:17:19.38#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.224.08:17:19.49#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.224.08:17:19.49#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.224.08:17:19.49#ibcon#enter wrdev, iclass 4, count 0 2006.224.08:17:19.49#ibcon#first serial, iclass 4, count 0 2006.224.08:17:19.49#ibcon#enter sib2, iclass 4, count 0 2006.224.08:17:19.49#ibcon#flushed, iclass 4, count 0 2006.224.08:17:19.49#ibcon#about to write, iclass 4, count 0 2006.224.08:17:19.49#ibcon#wrote, iclass 4, count 0 2006.224.08:17:19.49#ibcon#about to read 3, iclass 4, count 0 2006.224.08:17:19.51#ibcon#read 3, iclass 4, count 0 2006.224.08:17:19.51#ibcon#about to read 4, iclass 4, count 0 2006.224.08:17:19.51#ibcon#read 4, iclass 4, count 0 2006.224.08:17:19.51#ibcon#about to read 5, iclass 4, count 0 2006.224.08:17:19.51#ibcon#read 5, iclass 4, count 0 2006.224.08:17:19.51#ibcon#about to read 6, iclass 4, count 0 2006.224.08:17:19.51#ibcon#read 6, iclass 4, count 0 2006.224.08:17:19.51#ibcon#end of sib2, iclass 4, count 0 2006.224.08:17:19.51#ibcon#*mode == 0, iclass 4, count 0 2006.224.08:17:19.51#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.224.08:17:19.52#ibcon#[25=USB\r\n] 2006.224.08:17:19.52#ibcon#*before write, iclass 4, count 0 2006.224.08:17:19.52#ibcon#enter sib2, iclass 4, count 0 2006.224.08:17:19.52#ibcon#flushed, iclass 4, count 0 2006.224.08:17:19.52#ibcon#about to write, iclass 4, count 0 2006.224.08:17:19.52#ibcon#wrote, iclass 4, count 0 2006.224.08:17:19.52#ibcon#about to read 3, iclass 4, count 0 2006.224.08:17:19.54#ibcon#read 3, iclass 4, count 0 2006.224.08:17:19.54#ibcon#about to read 4, iclass 4, count 0 2006.224.08:17:19.54#ibcon#read 4, iclass 4, count 0 2006.224.08:17:19.54#ibcon#about to read 5, iclass 4, count 0 2006.224.08:17:19.54#ibcon#read 5, iclass 4, count 0 2006.224.08:17:19.54#ibcon#about to read 6, iclass 4, count 0 2006.224.08:17:19.54#ibcon#read 6, iclass 4, count 0 2006.224.08:17:19.54#ibcon#end of sib2, iclass 4, count 0 2006.224.08:17:19.54#ibcon#*after write, iclass 4, count 0 2006.224.08:17:19.54#ibcon#*before return 0, iclass 4, count 0 2006.224.08:17:19.55#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.224.08:17:19.55#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.224.08:17:19.55#ibcon#about to clear, iclass 4 cls_cnt 0 2006.224.08:17:19.55#ibcon#cleared, iclass 4 cls_cnt 0 2006.224.08:17:19.55$vc4f8/valo=6,772.99 2006.224.08:17:19.55#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.224.08:17:19.55#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.224.08:17:19.55#ibcon#ireg 17 cls_cnt 0 2006.224.08:17:19.55#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.224.08:17:19.55#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.224.08:17:19.55#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.224.08:17:19.55#ibcon#enter wrdev, iclass 6, count 0 2006.224.08:17:19.55#ibcon#first serial, iclass 6, count 0 2006.224.08:17:19.55#ibcon#enter sib2, iclass 6, count 0 2006.224.08:17:19.55#ibcon#flushed, iclass 6, count 0 2006.224.08:17:19.55#ibcon#about to write, iclass 6, count 0 2006.224.08:17:19.55#ibcon#wrote, iclass 6, count 0 2006.224.08:17:19.55#ibcon#about to read 3, iclass 6, count 0 2006.224.08:17:19.56#ibcon#read 3, iclass 6, count 0 2006.224.08:17:19.56#ibcon#about to read 4, iclass 6, count 0 2006.224.08:17:19.56#ibcon#read 4, iclass 6, count 0 2006.224.08:17:19.56#ibcon#about to read 5, iclass 6, count 0 2006.224.08:17:19.56#ibcon#read 5, iclass 6, count 0 2006.224.08:17:19.56#ibcon#about to read 6, iclass 6, count 0 2006.224.08:17:19.56#ibcon#read 6, iclass 6, count 0 2006.224.08:17:19.56#ibcon#end of sib2, iclass 6, count 0 2006.224.08:17:19.56#ibcon#*mode == 0, iclass 6, count 0 2006.224.08:17:19.56#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.224.08:17:19.57#ibcon#[26=FRQ=06,772.99\r\n] 2006.224.08:17:19.57#ibcon#*before write, iclass 6, count 0 2006.224.08:17:19.57#ibcon#enter sib2, iclass 6, count 0 2006.224.08:17:19.57#ibcon#flushed, iclass 6, count 0 2006.224.08:17:19.57#ibcon#about to write, iclass 6, count 0 2006.224.08:17:19.57#ibcon#wrote, iclass 6, count 0 2006.224.08:17:19.57#ibcon#about to read 3, iclass 6, count 0 2006.224.08:17:19.60#ibcon#read 3, iclass 6, count 0 2006.224.08:17:19.60#ibcon#about to read 4, iclass 6, count 0 2006.224.08:17:19.60#ibcon#read 4, iclass 6, count 0 2006.224.08:17:19.60#ibcon#about to read 5, iclass 6, count 0 2006.224.08:17:19.60#ibcon#read 5, iclass 6, count 0 2006.224.08:17:19.60#ibcon#about to read 6, iclass 6, count 0 2006.224.08:17:19.60#ibcon#read 6, iclass 6, count 0 2006.224.08:17:19.60#ibcon#end of sib2, iclass 6, count 0 2006.224.08:17:19.60#ibcon#*after write, iclass 6, count 0 2006.224.08:17:19.60#ibcon#*before return 0, iclass 6, count 0 2006.224.08:17:19.61#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.224.08:17:19.61#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.224.08:17:19.61#ibcon#about to clear, iclass 6 cls_cnt 0 2006.224.08:17:19.61#ibcon#cleared, iclass 6 cls_cnt 0 2006.224.08:17:19.61$vc4f8/va=6,6 2006.224.08:17:19.61#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.224.08:17:19.61#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.224.08:17:19.61#ibcon#ireg 11 cls_cnt 2 2006.224.08:17:19.61#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.224.08:17:19.67#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.224.08:17:19.67#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.224.08:17:19.67#ibcon#enter wrdev, iclass 10, count 2 2006.224.08:17:19.67#ibcon#first serial, iclass 10, count 2 2006.224.08:17:19.67#ibcon#enter sib2, iclass 10, count 2 2006.224.08:17:19.67#ibcon#flushed, iclass 10, count 2 2006.224.08:17:19.67#ibcon#about to write, iclass 10, count 2 2006.224.08:17:19.67#ibcon#wrote, iclass 10, count 2 2006.224.08:17:19.67#ibcon#about to read 3, iclass 10, count 2 2006.224.08:17:19.68#ibcon#read 3, iclass 10, count 2 2006.224.08:17:19.68#ibcon#about to read 4, iclass 10, count 2 2006.224.08:17:19.68#ibcon#read 4, iclass 10, count 2 2006.224.08:17:19.68#ibcon#about to read 5, iclass 10, count 2 2006.224.08:17:19.68#ibcon#read 5, iclass 10, count 2 2006.224.08:17:19.68#ibcon#about to read 6, iclass 10, count 2 2006.224.08:17:19.68#ibcon#read 6, iclass 10, count 2 2006.224.08:17:19.68#ibcon#end of sib2, iclass 10, count 2 2006.224.08:17:19.68#ibcon#*mode == 0, iclass 10, count 2 2006.224.08:17:19.68#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.224.08:17:19.69#ibcon#[25=AT06-06\r\n] 2006.224.08:17:19.69#ibcon#*before write, iclass 10, count 2 2006.224.08:17:19.69#ibcon#enter sib2, iclass 10, count 2 2006.224.08:17:19.69#ibcon#flushed, iclass 10, count 2 2006.224.08:17:19.69#ibcon#about to write, iclass 10, count 2 2006.224.08:17:19.69#ibcon#wrote, iclass 10, count 2 2006.224.08:17:19.69#ibcon#about to read 3, iclass 10, count 2 2006.224.08:17:19.71#ibcon#read 3, iclass 10, count 2 2006.224.08:17:19.71#ibcon#about to read 4, iclass 10, count 2 2006.224.08:17:19.71#ibcon#read 4, iclass 10, count 2 2006.224.08:17:19.71#ibcon#about to read 5, iclass 10, count 2 2006.224.08:17:19.71#ibcon#read 5, iclass 10, count 2 2006.224.08:17:19.71#ibcon#about to read 6, iclass 10, count 2 2006.224.08:17:19.71#ibcon#read 6, iclass 10, count 2 2006.224.08:17:19.71#ibcon#end of sib2, iclass 10, count 2 2006.224.08:17:19.72#ibcon#*after write, iclass 10, count 2 2006.224.08:17:19.72#ibcon#*before return 0, iclass 10, count 2 2006.224.08:17:19.72#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.224.08:17:19.72#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.224.08:17:19.72#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.224.08:17:19.72#ibcon#ireg 7 cls_cnt 0 2006.224.08:17:19.72#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.224.08:17:19.83#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.224.08:17:19.83#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.224.08:17:19.83#ibcon#enter wrdev, iclass 10, count 0 2006.224.08:17:19.83#ibcon#first serial, iclass 10, count 0 2006.224.08:17:19.83#ibcon#enter sib2, iclass 10, count 0 2006.224.08:17:19.83#ibcon#flushed, iclass 10, count 0 2006.224.08:17:19.83#ibcon#about to write, iclass 10, count 0 2006.224.08:17:19.83#ibcon#wrote, iclass 10, count 0 2006.224.08:17:19.83#ibcon#about to read 3, iclass 10, count 0 2006.224.08:17:19.85#ibcon#read 3, iclass 10, count 0 2006.224.08:17:19.85#ibcon#about to read 4, iclass 10, count 0 2006.224.08:17:19.85#ibcon#read 4, iclass 10, count 0 2006.224.08:17:19.85#ibcon#about to read 5, iclass 10, count 0 2006.224.08:17:19.85#ibcon#read 5, iclass 10, count 0 2006.224.08:17:19.85#ibcon#about to read 6, iclass 10, count 0 2006.224.08:17:19.85#ibcon#read 6, iclass 10, count 0 2006.224.08:17:19.85#ibcon#end of sib2, iclass 10, count 0 2006.224.08:17:19.85#ibcon#*mode == 0, iclass 10, count 0 2006.224.08:17:19.85#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.224.08:17:19.86#ibcon#[25=USB\r\n] 2006.224.08:17:19.86#ibcon#*before write, iclass 10, count 0 2006.224.08:17:19.86#ibcon#enter sib2, iclass 10, count 0 2006.224.08:17:19.86#ibcon#flushed, iclass 10, count 0 2006.224.08:17:19.86#ibcon#about to write, iclass 10, count 0 2006.224.08:17:19.86#ibcon#wrote, iclass 10, count 0 2006.224.08:17:19.86#ibcon#about to read 3, iclass 10, count 0 2006.224.08:17:19.88#ibcon#read 3, iclass 10, count 0 2006.224.08:17:19.88#ibcon#about to read 4, iclass 10, count 0 2006.224.08:17:19.88#ibcon#read 4, iclass 10, count 0 2006.224.08:17:19.88#ibcon#about to read 5, iclass 10, count 0 2006.224.08:17:19.88#ibcon#read 5, iclass 10, count 0 2006.224.08:17:19.88#ibcon#about to read 6, iclass 10, count 0 2006.224.08:17:19.88#ibcon#read 6, iclass 10, count 0 2006.224.08:17:19.88#ibcon#end of sib2, iclass 10, count 0 2006.224.08:17:19.88#ibcon#*after write, iclass 10, count 0 2006.224.08:17:19.88#ibcon#*before return 0, iclass 10, count 0 2006.224.08:17:19.89#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.224.08:17:19.89#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.224.08:17:19.89#ibcon#about to clear, iclass 10 cls_cnt 0 2006.224.08:17:19.89#ibcon#cleared, iclass 10 cls_cnt 0 2006.224.08:17:19.89$vc4f8/valo=7,832.99 2006.224.08:17:19.89#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.224.08:17:19.89#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.224.08:17:19.89#ibcon#ireg 17 cls_cnt 0 2006.224.08:17:19.89#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.224.08:17:19.89#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.224.08:17:19.89#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.224.08:17:19.89#ibcon#enter wrdev, iclass 12, count 0 2006.224.08:17:19.89#ibcon#first serial, iclass 12, count 0 2006.224.08:17:19.89#ibcon#enter sib2, iclass 12, count 0 2006.224.08:17:19.89#ibcon#flushed, iclass 12, count 0 2006.224.08:17:19.89#ibcon#about to write, iclass 12, count 0 2006.224.08:17:19.89#ibcon#wrote, iclass 12, count 0 2006.224.08:17:19.89#ibcon#about to read 3, iclass 12, count 0 2006.224.08:17:19.90#ibcon#read 3, iclass 12, count 0 2006.224.08:17:19.90#ibcon#about to read 4, iclass 12, count 0 2006.224.08:17:19.90#ibcon#read 4, iclass 12, count 0 2006.224.08:17:19.90#ibcon#about to read 5, iclass 12, count 0 2006.224.08:17:19.90#ibcon#read 5, iclass 12, count 0 2006.224.08:17:19.90#ibcon#about to read 6, iclass 12, count 0 2006.224.08:17:19.90#ibcon#read 6, iclass 12, count 0 2006.224.08:17:19.90#ibcon#end of sib2, iclass 12, count 0 2006.224.08:17:19.90#ibcon#*mode == 0, iclass 12, count 0 2006.224.08:17:19.90#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.224.08:17:19.90#ibcon#[26=FRQ=07,832.99\r\n] 2006.224.08:17:19.91#ibcon#*before write, iclass 12, count 0 2006.224.08:17:19.91#ibcon#enter sib2, iclass 12, count 0 2006.224.08:17:19.91#ibcon#flushed, iclass 12, count 0 2006.224.08:17:19.91#ibcon#about to write, iclass 12, count 0 2006.224.08:17:19.91#ibcon#wrote, iclass 12, count 0 2006.224.08:17:19.91#ibcon#about to read 3, iclass 12, count 0 2006.224.08:17:19.94#ibcon#read 3, iclass 12, count 0 2006.224.08:17:19.94#ibcon#about to read 4, iclass 12, count 0 2006.224.08:17:19.94#ibcon#read 4, iclass 12, count 0 2006.224.08:17:19.94#ibcon#about to read 5, iclass 12, count 0 2006.224.08:17:19.94#ibcon#read 5, iclass 12, count 0 2006.224.08:17:19.94#ibcon#about to read 6, iclass 12, count 0 2006.224.08:17:19.94#ibcon#read 6, iclass 12, count 0 2006.224.08:17:19.94#ibcon#end of sib2, iclass 12, count 0 2006.224.08:17:19.94#ibcon#*after write, iclass 12, count 0 2006.224.08:17:19.94#ibcon#*before return 0, iclass 12, count 0 2006.224.08:17:19.95#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.224.08:17:19.95#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.224.08:17:19.95#ibcon#about to clear, iclass 12 cls_cnt 0 2006.224.08:17:19.95#ibcon#cleared, iclass 12 cls_cnt 0 2006.224.08:17:19.95$vc4f8/va=7,6 2006.224.08:17:19.95#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.224.08:17:19.95#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.224.08:17:19.95#ibcon#ireg 11 cls_cnt 2 2006.224.08:17:19.95#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.224.08:17:20.01#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.224.08:17:20.01#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.224.08:17:20.01#ibcon#enter wrdev, iclass 14, count 2 2006.224.08:17:20.01#ibcon#first serial, iclass 14, count 2 2006.224.08:17:20.01#ibcon#enter sib2, iclass 14, count 2 2006.224.08:17:20.01#ibcon#flushed, iclass 14, count 2 2006.224.08:17:20.01#ibcon#about to write, iclass 14, count 2 2006.224.08:17:20.01#ibcon#wrote, iclass 14, count 2 2006.224.08:17:20.01#ibcon#about to read 3, iclass 14, count 2 2006.224.08:17:20.02#ibcon#read 3, iclass 14, count 2 2006.224.08:17:20.02#ibcon#about to read 4, iclass 14, count 2 2006.224.08:17:20.02#ibcon#read 4, iclass 14, count 2 2006.224.08:17:20.02#ibcon#about to read 5, iclass 14, count 2 2006.224.08:17:20.02#ibcon#read 5, iclass 14, count 2 2006.224.08:17:20.02#ibcon#about to read 6, iclass 14, count 2 2006.224.08:17:20.02#ibcon#read 6, iclass 14, count 2 2006.224.08:17:20.02#ibcon#end of sib2, iclass 14, count 2 2006.224.08:17:20.02#ibcon#*mode == 0, iclass 14, count 2 2006.224.08:17:20.02#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.224.08:17:20.02#ibcon#[25=AT07-06\r\n] 2006.224.08:17:20.02#ibcon#*before write, iclass 14, count 2 2006.224.08:17:20.03#ibcon#enter sib2, iclass 14, count 2 2006.224.08:17:20.03#ibcon#flushed, iclass 14, count 2 2006.224.08:17:20.03#ibcon#about to write, iclass 14, count 2 2006.224.08:17:20.03#ibcon#wrote, iclass 14, count 2 2006.224.08:17:20.03#ibcon#about to read 3, iclass 14, count 2 2006.224.08:17:20.05#ibcon#read 3, iclass 14, count 2 2006.224.08:17:20.05#ibcon#about to read 4, iclass 14, count 2 2006.224.08:17:20.05#ibcon#read 4, iclass 14, count 2 2006.224.08:17:20.05#ibcon#about to read 5, iclass 14, count 2 2006.224.08:17:20.05#ibcon#read 5, iclass 14, count 2 2006.224.08:17:20.05#ibcon#about to read 6, iclass 14, count 2 2006.224.08:17:20.05#ibcon#read 6, iclass 14, count 2 2006.224.08:17:20.05#ibcon#end of sib2, iclass 14, count 2 2006.224.08:17:20.06#ibcon#*after write, iclass 14, count 2 2006.224.08:17:20.06#ibcon#*before return 0, iclass 14, count 2 2006.224.08:17:20.06#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.224.08:17:20.06#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.224.08:17:20.06#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.224.08:17:20.06#ibcon#ireg 7 cls_cnt 0 2006.224.08:17:20.06#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.224.08:17:20.17#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.224.08:17:20.17#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.224.08:17:20.17#ibcon#enter wrdev, iclass 14, count 0 2006.224.08:17:20.17#ibcon#first serial, iclass 14, count 0 2006.224.08:17:20.17#ibcon#enter sib2, iclass 14, count 0 2006.224.08:17:20.17#ibcon#flushed, iclass 14, count 0 2006.224.08:17:20.17#ibcon#about to write, iclass 14, count 0 2006.224.08:17:20.17#ibcon#wrote, iclass 14, count 0 2006.224.08:17:20.17#ibcon#about to read 3, iclass 14, count 0 2006.224.08:17:20.19#ibcon#read 3, iclass 14, count 0 2006.224.08:17:20.19#ibcon#about to read 4, iclass 14, count 0 2006.224.08:17:20.19#ibcon#read 4, iclass 14, count 0 2006.224.08:17:20.19#ibcon#about to read 5, iclass 14, count 0 2006.224.08:17:20.19#ibcon#read 5, iclass 14, count 0 2006.224.08:17:20.19#ibcon#about to read 6, iclass 14, count 0 2006.224.08:17:20.19#ibcon#read 6, iclass 14, count 0 2006.224.08:17:20.19#ibcon#end of sib2, iclass 14, count 0 2006.224.08:17:20.19#ibcon#*mode == 0, iclass 14, count 0 2006.224.08:17:20.19#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.224.08:17:20.19#ibcon#[25=USB\r\n] 2006.224.08:17:20.20#ibcon#*before write, iclass 14, count 0 2006.224.08:17:20.20#ibcon#enter sib2, iclass 14, count 0 2006.224.08:17:20.20#ibcon#flushed, iclass 14, count 0 2006.224.08:17:20.20#ibcon#about to write, iclass 14, count 0 2006.224.08:17:20.20#ibcon#wrote, iclass 14, count 0 2006.224.08:17:20.20#ibcon#about to read 3, iclass 14, count 0 2006.224.08:17:20.22#ibcon#read 3, iclass 14, count 0 2006.224.08:17:20.22#ibcon#about to read 4, iclass 14, count 0 2006.224.08:17:20.22#ibcon#read 4, iclass 14, count 0 2006.224.08:17:20.22#ibcon#about to read 5, iclass 14, count 0 2006.224.08:17:20.22#ibcon#read 5, iclass 14, count 0 2006.224.08:17:20.22#ibcon#about to read 6, iclass 14, count 0 2006.224.08:17:20.22#ibcon#read 6, iclass 14, count 0 2006.224.08:17:20.22#ibcon#end of sib2, iclass 14, count 0 2006.224.08:17:20.22#ibcon#*after write, iclass 14, count 0 2006.224.08:17:20.22#ibcon#*before return 0, iclass 14, count 0 2006.224.08:17:20.23#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.224.08:17:20.23#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.224.08:17:20.23#ibcon#about to clear, iclass 14 cls_cnt 0 2006.224.08:17:20.23#ibcon#cleared, iclass 14 cls_cnt 0 2006.224.08:17:20.23$vc4f8/valo=8,852.99 2006.224.08:17:20.23#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.224.08:17:20.23#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.224.08:17:20.23#ibcon#ireg 17 cls_cnt 0 2006.224.08:17:20.23#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.224.08:17:20.23#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.224.08:17:20.23#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.224.08:17:20.23#ibcon#enter wrdev, iclass 16, count 0 2006.224.08:17:20.23#ibcon#first serial, iclass 16, count 0 2006.224.08:17:20.23#ibcon#enter sib2, iclass 16, count 0 2006.224.08:17:20.23#ibcon#flushed, iclass 16, count 0 2006.224.08:17:20.23#ibcon#about to write, iclass 16, count 0 2006.224.08:17:20.23#ibcon#wrote, iclass 16, count 0 2006.224.08:17:20.23#ibcon#about to read 3, iclass 16, count 0 2006.224.08:17:20.24#ibcon#read 3, iclass 16, count 0 2006.224.08:17:20.24#ibcon#about to read 4, iclass 16, count 0 2006.224.08:17:20.24#ibcon#read 4, iclass 16, count 0 2006.224.08:17:20.24#ibcon#about to read 5, iclass 16, count 0 2006.224.08:17:20.24#ibcon#read 5, iclass 16, count 0 2006.224.08:17:20.24#ibcon#about to read 6, iclass 16, count 0 2006.224.08:17:20.24#ibcon#read 6, iclass 16, count 0 2006.224.08:17:20.24#ibcon#end of sib2, iclass 16, count 0 2006.224.08:17:20.25#ibcon#*mode == 0, iclass 16, count 0 2006.224.08:17:20.25#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.224.08:17:20.25#ibcon#[26=FRQ=08,852.99\r\n] 2006.224.08:17:20.25#ibcon#*before write, iclass 16, count 0 2006.224.08:17:20.25#ibcon#enter sib2, iclass 16, count 0 2006.224.08:17:20.25#ibcon#flushed, iclass 16, count 0 2006.224.08:17:20.25#ibcon#about to write, iclass 16, count 0 2006.224.08:17:20.25#ibcon#wrote, iclass 16, count 0 2006.224.08:17:20.25#ibcon#about to read 3, iclass 16, count 0 2006.224.08:17:20.28#ibcon#read 3, iclass 16, count 0 2006.224.08:17:20.28#ibcon#about to read 4, iclass 16, count 0 2006.224.08:17:20.28#ibcon#read 4, iclass 16, count 0 2006.224.08:17:20.28#ibcon#about to read 5, iclass 16, count 0 2006.224.08:17:20.28#ibcon#read 5, iclass 16, count 0 2006.224.08:17:20.28#ibcon#about to read 6, iclass 16, count 0 2006.224.08:17:20.28#ibcon#read 6, iclass 16, count 0 2006.224.08:17:20.28#ibcon#end of sib2, iclass 16, count 0 2006.224.08:17:20.28#ibcon#*after write, iclass 16, count 0 2006.224.08:17:20.28#ibcon#*before return 0, iclass 16, count 0 2006.224.08:17:20.28#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.224.08:17:20.29#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.224.08:17:20.29#ibcon#about to clear, iclass 16 cls_cnt 0 2006.224.08:17:20.29#ibcon#cleared, iclass 16 cls_cnt 0 2006.224.08:17:20.29$vc4f8/va=8,7 2006.224.08:17:20.29#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.224.08:17:20.29#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.224.08:17:20.29#ibcon#ireg 11 cls_cnt 2 2006.224.08:17:20.29#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.224.08:17:20.34#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.224.08:17:20.34#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.224.08:17:20.34#ibcon#enter wrdev, iclass 18, count 2 2006.224.08:17:20.34#ibcon#first serial, iclass 18, count 2 2006.224.08:17:20.34#ibcon#enter sib2, iclass 18, count 2 2006.224.08:17:20.34#ibcon#flushed, iclass 18, count 2 2006.224.08:17:20.34#ibcon#about to write, iclass 18, count 2 2006.224.08:17:20.34#ibcon#wrote, iclass 18, count 2 2006.224.08:17:20.35#ibcon#about to read 3, iclass 18, count 2 2006.224.08:17:20.36#ibcon#read 3, iclass 18, count 2 2006.224.08:17:20.36#ibcon#about to read 4, iclass 18, count 2 2006.224.08:17:20.36#ibcon#read 4, iclass 18, count 2 2006.224.08:17:20.36#ibcon#about to read 5, iclass 18, count 2 2006.224.08:17:20.36#ibcon#read 5, iclass 18, count 2 2006.224.08:17:20.36#ibcon#about to read 6, iclass 18, count 2 2006.224.08:17:20.36#ibcon#read 6, iclass 18, count 2 2006.224.08:17:20.36#ibcon#end of sib2, iclass 18, count 2 2006.224.08:17:20.36#ibcon#*mode == 0, iclass 18, count 2 2006.224.08:17:20.36#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.224.08:17:20.36#ibcon#[25=AT08-07\r\n] 2006.224.08:17:20.37#ibcon#*before write, iclass 18, count 2 2006.224.08:17:20.37#ibcon#enter sib2, iclass 18, count 2 2006.224.08:17:20.37#ibcon#flushed, iclass 18, count 2 2006.224.08:17:20.37#ibcon#about to write, iclass 18, count 2 2006.224.08:17:20.37#ibcon#wrote, iclass 18, count 2 2006.224.08:17:20.37#ibcon#about to read 3, iclass 18, count 2 2006.224.08:17:20.39#ibcon#read 3, iclass 18, count 2 2006.224.08:17:20.39#ibcon#about to read 4, iclass 18, count 2 2006.224.08:17:20.39#ibcon#read 4, iclass 18, count 2 2006.224.08:17:20.39#ibcon#about to read 5, iclass 18, count 2 2006.224.08:17:20.39#ibcon#read 5, iclass 18, count 2 2006.224.08:17:20.39#ibcon#about to read 6, iclass 18, count 2 2006.224.08:17:20.40#ibcon#read 6, iclass 18, count 2 2006.224.08:17:20.40#ibcon#end of sib2, iclass 18, count 2 2006.224.08:17:20.40#ibcon#*after write, iclass 18, count 2 2006.224.08:17:20.40#ibcon#*before return 0, iclass 18, count 2 2006.224.08:17:20.40#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.224.08:17:20.40#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.224.08:17:20.40#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.224.08:17:20.40#ibcon#ireg 7 cls_cnt 0 2006.224.08:17:20.40#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.224.08:17:20.51#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.224.08:17:20.51#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.224.08:17:20.51#ibcon#enter wrdev, iclass 18, count 0 2006.224.08:17:20.51#ibcon#first serial, iclass 18, count 0 2006.224.08:17:20.51#ibcon#enter sib2, iclass 18, count 0 2006.224.08:17:20.51#ibcon#flushed, iclass 18, count 0 2006.224.08:17:20.51#ibcon#about to write, iclass 18, count 0 2006.224.08:17:20.51#ibcon#wrote, iclass 18, count 0 2006.224.08:17:20.51#ibcon#about to read 3, iclass 18, count 0 2006.224.08:17:20.53#ibcon#read 3, iclass 18, count 0 2006.224.08:17:20.53#ibcon#about to read 4, iclass 18, count 0 2006.224.08:17:20.53#ibcon#read 4, iclass 18, count 0 2006.224.08:17:20.53#ibcon#about to read 5, iclass 18, count 0 2006.224.08:17:20.53#ibcon#read 5, iclass 18, count 0 2006.224.08:17:20.53#ibcon#about to read 6, iclass 18, count 0 2006.224.08:17:20.53#ibcon#read 6, iclass 18, count 0 2006.224.08:17:20.53#ibcon#end of sib2, iclass 18, count 0 2006.224.08:17:20.53#ibcon#*mode == 0, iclass 18, count 0 2006.224.08:17:20.53#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.224.08:17:20.53#ibcon#[25=USB\r\n] 2006.224.08:17:20.54#ibcon#*before write, iclass 18, count 0 2006.224.08:17:20.54#ibcon#enter sib2, iclass 18, count 0 2006.224.08:17:20.54#ibcon#flushed, iclass 18, count 0 2006.224.08:17:20.54#ibcon#about to write, iclass 18, count 0 2006.224.08:17:20.54#ibcon#wrote, iclass 18, count 0 2006.224.08:17:20.54#ibcon#about to read 3, iclass 18, count 0 2006.224.08:17:20.56#ibcon#read 3, iclass 18, count 0 2006.224.08:17:20.56#ibcon#about to read 4, iclass 18, count 0 2006.224.08:17:20.56#ibcon#read 4, iclass 18, count 0 2006.224.08:17:20.56#ibcon#about to read 5, iclass 18, count 0 2006.224.08:17:20.56#ibcon#read 5, iclass 18, count 0 2006.224.08:17:20.56#ibcon#about to read 6, iclass 18, count 0 2006.224.08:17:20.56#ibcon#read 6, iclass 18, count 0 2006.224.08:17:20.56#ibcon#end of sib2, iclass 18, count 0 2006.224.08:17:20.56#ibcon#*after write, iclass 18, count 0 2006.224.08:17:20.56#ibcon#*before return 0, iclass 18, count 0 2006.224.08:17:20.57#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.224.08:17:20.57#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.224.08:17:20.57#ibcon#about to clear, iclass 18 cls_cnt 0 2006.224.08:17:20.57#ibcon#cleared, iclass 18 cls_cnt 0 2006.224.08:17:20.57$vc4f8/vblo=1,632.99 2006.224.08:17:20.57#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.224.08:17:20.57#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.224.08:17:20.57#ibcon#ireg 17 cls_cnt 0 2006.224.08:17:20.57#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.224.08:17:20.57#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.224.08:17:20.57#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.224.08:17:20.57#ibcon#enter wrdev, iclass 20, count 0 2006.224.08:17:20.57#ibcon#first serial, iclass 20, count 0 2006.224.08:17:20.57#ibcon#enter sib2, iclass 20, count 0 2006.224.08:17:20.57#ibcon#flushed, iclass 20, count 0 2006.224.08:17:20.57#ibcon#about to write, iclass 20, count 0 2006.224.08:17:20.57#ibcon#wrote, iclass 20, count 0 2006.224.08:17:20.57#ibcon#about to read 3, iclass 20, count 0 2006.224.08:17:20.59#ibcon#read 3, iclass 20, count 0 2006.224.08:17:20.59#ibcon#about to read 4, iclass 20, count 0 2006.224.08:17:20.59#ibcon#read 4, iclass 20, count 0 2006.224.08:17:20.59#ibcon#about to read 5, iclass 20, count 0 2006.224.08:17:20.59#ibcon#read 5, iclass 20, count 0 2006.224.08:17:20.59#ibcon#about to read 6, iclass 20, count 0 2006.224.08:17:20.59#ibcon#read 6, iclass 20, count 0 2006.224.08:17:20.59#ibcon#end of sib2, iclass 20, count 0 2006.224.08:17:20.59#ibcon#*mode == 0, iclass 20, count 0 2006.224.08:17:20.59#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.224.08:17:20.59#ibcon#[28=FRQ=01,632.99\r\n] 2006.224.08:17:20.59#ibcon#*before write, iclass 20, count 0 2006.224.08:17:20.59#ibcon#enter sib2, iclass 20, count 0 2006.224.08:17:20.59#ibcon#flushed, iclass 20, count 0 2006.224.08:17:20.59#ibcon#about to write, iclass 20, count 0 2006.224.08:17:20.59#ibcon#wrote, iclass 20, count 0 2006.224.08:17:20.59#ibcon#about to read 3, iclass 20, count 0 2006.224.08:17:20.63#ibcon#read 3, iclass 20, count 0 2006.224.08:17:20.63#ibcon#about to read 4, iclass 20, count 0 2006.224.08:17:20.63#ibcon#read 4, iclass 20, count 0 2006.224.08:17:20.63#ibcon#about to read 5, iclass 20, count 0 2006.224.08:17:20.63#ibcon#read 5, iclass 20, count 0 2006.224.08:17:20.63#ibcon#about to read 6, iclass 20, count 0 2006.224.08:17:20.63#ibcon#read 6, iclass 20, count 0 2006.224.08:17:20.63#ibcon#end of sib2, iclass 20, count 0 2006.224.08:17:20.64#ibcon#*after write, iclass 20, count 0 2006.224.08:17:20.64#ibcon#*before return 0, iclass 20, count 0 2006.224.08:17:20.64#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.224.08:17:20.64#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.224.08:17:20.64#ibcon#about to clear, iclass 20 cls_cnt 0 2006.224.08:17:20.64#ibcon#cleared, iclass 20 cls_cnt 0 2006.224.08:17:20.64$vc4f8/vb=1,4 2006.224.08:17:20.64#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.224.08:17:20.64#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.224.08:17:20.64#ibcon#ireg 11 cls_cnt 2 2006.224.08:17:20.64#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.224.08:17:20.64#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.224.08:17:20.64#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.224.08:17:20.64#ibcon#enter wrdev, iclass 22, count 2 2006.224.08:17:20.64#ibcon#first serial, iclass 22, count 2 2006.224.08:17:20.64#ibcon#enter sib2, iclass 22, count 2 2006.224.08:17:20.64#ibcon#flushed, iclass 22, count 2 2006.224.08:17:20.64#ibcon#about to write, iclass 22, count 2 2006.224.08:17:20.64#ibcon#wrote, iclass 22, count 2 2006.224.08:17:20.64#ibcon#about to read 3, iclass 22, count 2 2006.224.08:17:20.65#ibcon#read 3, iclass 22, count 2 2006.224.08:17:20.65#ibcon#about to read 4, iclass 22, count 2 2006.224.08:17:20.65#ibcon#read 4, iclass 22, count 2 2006.224.08:17:20.65#ibcon#about to read 5, iclass 22, count 2 2006.224.08:17:20.65#ibcon#read 5, iclass 22, count 2 2006.224.08:17:20.65#ibcon#about to read 6, iclass 22, count 2 2006.224.08:17:20.65#ibcon#read 6, iclass 22, count 2 2006.224.08:17:20.65#ibcon#end of sib2, iclass 22, count 2 2006.224.08:17:20.65#ibcon#*mode == 0, iclass 22, count 2 2006.224.08:17:20.65#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.224.08:17:20.66#ibcon#[27=AT01-04\r\n] 2006.224.08:17:20.66#ibcon#*before write, iclass 22, count 2 2006.224.08:17:20.66#ibcon#enter sib2, iclass 22, count 2 2006.224.08:17:20.66#ibcon#flushed, iclass 22, count 2 2006.224.08:17:20.66#ibcon#about to write, iclass 22, count 2 2006.224.08:17:20.66#ibcon#wrote, iclass 22, count 2 2006.224.08:17:20.66#ibcon#about to read 3, iclass 22, count 2 2006.224.08:17:20.68#ibcon#read 3, iclass 22, count 2 2006.224.08:17:20.68#ibcon#about to read 4, iclass 22, count 2 2006.224.08:17:20.68#ibcon#read 4, iclass 22, count 2 2006.224.08:17:20.68#ibcon#about to read 5, iclass 22, count 2 2006.224.08:17:20.68#ibcon#read 5, iclass 22, count 2 2006.224.08:17:20.68#ibcon#about to read 6, iclass 22, count 2 2006.224.08:17:20.68#ibcon#read 6, iclass 22, count 2 2006.224.08:17:20.68#ibcon#end of sib2, iclass 22, count 2 2006.224.08:17:20.68#ibcon#*after write, iclass 22, count 2 2006.224.08:17:20.68#ibcon#*before return 0, iclass 22, count 2 2006.224.08:17:20.68#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.224.08:17:20.69#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.224.08:17:20.69#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.224.08:17:20.69#ibcon#ireg 7 cls_cnt 0 2006.224.08:17:20.69#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.224.08:17:20.80#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.224.08:17:20.80#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.224.08:17:20.80#ibcon#enter wrdev, iclass 22, count 0 2006.224.08:17:20.80#ibcon#first serial, iclass 22, count 0 2006.224.08:17:20.80#ibcon#enter sib2, iclass 22, count 0 2006.224.08:17:20.80#ibcon#flushed, iclass 22, count 0 2006.224.08:17:20.80#ibcon#about to write, iclass 22, count 0 2006.224.08:17:20.80#ibcon#wrote, iclass 22, count 0 2006.224.08:17:20.80#ibcon#about to read 3, iclass 22, count 0 2006.224.08:17:20.82#ibcon#read 3, iclass 22, count 0 2006.224.08:17:20.82#ibcon#about to read 4, iclass 22, count 0 2006.224.08:17:20.82#ibcon#read 4, iclass 22, count 0 2006.224.08:17:20.82#ibcon#about to read 5, iclass 22, count 0 2006.224.08:17:20.82#ibcon#read 5, iclass 22, count 0 2006.224.08:17:20.82#ibcon#about to read 6, iclass 22, count 0 2006.224.08:17:20.82#ibcon#read 6, iclass 22, count 0 2006.224.08:17:20.82#ibcon#end of sib2, iclass 22, count 0 2006.224.08:17:20.82#ibcon#*mode == 0, iclass 22, count 0 2006.224.08:17:20.82#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.224.08:17:20.82#ibcon#[27=USB\r\n] 2006.224.08:17:20.83#ibcon#*before write, iclass 22, count 0 2006.224.08:17:20.83#ibcon#enter sib2, iclass 22, count 0 2006.224.08:17:20.83#ibcon#flushed, iclass 22, count 0 2006.224.08:17:20.83#ibcon#about to write, iclass 22, count 0 2006.224.08:17:20.83#ibcon#wrote, iclass 22, count 0 2006.224.08:17:20.83#ibcon#about to read 3, iclass 22, count 0 2006.224.08:17:20.85#ibcon#read 3, iclass 22, count 0 2006.224.08:17:20.85#ibcon#about to read 4, iclass 22, count 0 2006.224.08:17:20.85#ibcon#read 4, iclass 22, count 0 2006.224.08:17:20.85#ibcon#about to read 5, iclass 22, count 0 2006.224.08:17:20.85#ibcon#read 5, iclass 22, count 0 2006.224.08:17:20.85#ibcon#about to read 6, iclass 22, count 0 2006.224.08:17:20.85#ibcon#read 6, iclass 22, count 0 2006.224.08:17:20.85#ibcon#end of sib2, iclass 22, count 0 2006.224.08:17:20.85#ibcon#*after write, iclass 22, count 0 2006.224.08:17:20.85#ibcon#*before return 0, iclass 22, count 0 2006.224.08:17:20.86#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.224.08:17:20.86#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.224.08:17:20.86#ibcon#about to clear, iclass 22 cls_cnt 0 2006.224.08:17:20.86#ibcon#cleared, iclass 22 cls_cnt 0 2006.224.08:17:20.86$vc4f8/vblo=2,640.99 2006.224.08:17:20.86#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.224.08:17:20.86#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.224.08:17:20.86#ibcon#ireg 17 cls_cnt 0 2006.224.08:17:20.86#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.224.08:17:20.86#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.224.08:17:20.86#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.224.08:17:20.86#ibcon#enter wrdev, iclass 24, count 0 2006.224.08:17:20.86#ibcon#first serial, iclass 24, count 0 2006.224.08:17:20.86#ibcon#enter sib2, iclass 24, count 0 2006.224.08:17:20.86#ibcon#flushed, iclass 24, count 0 2006.224.08:17:20.86#ibcon#about to write, iclass 24, count 0 2006.224.08:17:20.86#ibcon#wrote, iclass 24, count 0 2006.224.08:17:20.86#ibcon#about to read 3, iclass 24, count 0 2006.224.08:17:20.87#ibcon#read 3, iclass 24, count 0 2006.224.08:17:20.87#ibcon#about to read 4, iclass 24, count 0 2006.224.08:17:20.87#ibcon#read 4, iclass 24, count 0 2006.224.08:17:20.87#ibcon#about to read 5, iclass 24, count 0 2006.224.08:17:20.87#ibcon#read 5, iclass 24, count 0 2006.224.08:17:20.87#ibcon#about to read 6, iclass 24, count 0 2006.224.08:17:20.87#ibcon#read 6, iclass 24, count 0 2006.224.08:17:20.87#ibcon#end of sib2, iclass 24, count 0 2006.224.08:17:20.87#ibcon#*mode == 0, iclass 24, count 0 2006.224.08:17:20.87#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.224.08:17:20.87#ibcon#[28=FRQ=02,640.99\r\n] 2006.224.08:17:20.88#ibcon#*before write, iclass 24, count 0 2006.224.08:17:20.88#ibcon#enter sib2, iclass 24, count 0 2006.224.08:17:20.88#ibcon#flushed, iclass 24, count 0 2006.224.08:17:20.88#ibcon#about to write, iclass 24, count 0 2006.224.08:17:20.88#ibcon#wrote, iclass 24, count 0 2006.224.08:17:20.88#ibcon#about to read 3, iclass 24, count 0 2006.224.08:17:20.91#ibcon#read 3, iclass 24, count 0 2006.224.08:17:20.91#ibcon#about to read 4, iclass 24, count 0 2006.224.08:17:20.91#ibcon#read 4, iclass 24, count 0 2006.224.08:17:20.91#ibcon#about to read 5, iclass 24, count 0 2006.224.08:17:20.91#ibcon#read 5, iclass 24, count 0 2006.224.08:17:20.91#ibcon#about to read 6, iclass 24, count 0 2006.224.08:17:20.91#ibcon#read 6, iclass 24, count 0 2006.224.08:17:20.91#ibcon#end of sib2, iclass 24, count 0 2006.224.08:17:20.91#ibcon#*after write, iclass 24, count 0 2006.224.08:17:20.91#ibcon#*before return 0, iclass 24, count 0 2006.224.08:17:20.92#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.224.08:17:20.92#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.224.08:17:20.92#ibcon#about to clear, iclass 24 cls_cnt 0 2006.224.08:17:20.92#ibcon#cleared, iclass 24 cls_cnt 0 2006.224.08:17:20.92$vc4f8/vb=2,4 2006.224.08:17:20.92#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.224.08:17:20.92#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.224.08:17:20.92#ibcon#ireg 11 cls_cnt 2 2006.224.08:17:20.92#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.224.08:17:20.97#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.224.08:17:20.97#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.224.08:17:20.97#ibcon#enter wrdev, iclass 26, count 2 2006.224.08:17:20.97#ibcon#first serial, iclass 26, count 2 2006.224.08:17:20.97#ibcon#enter sib2, iclass 26, count 2 2006.224.08:17:20.97#ibcon#flushed, iclass 26, count 2 2006.224.08:17:20.97#ibcon#about to write, iclass 26, count 2 2006.224.08:17:20.97#ibcon#wrote, iclass 26, count 2 2006.224.08:17:20.97#ibcon#about to read 3, iclass 26, count 2 2006.224.08:17:20.99#ibcon#read 3, iclass 26, count 2 2006.224.08:17:20.99#ibcon#about to read 4, iclass 26, count 2 2006.224.08:17:20.99#ibcon#read 4, iclass 26, count 2 2006.224.08:17:20.99#ibcon#about to read 5, iclass 26, count 2 2006.224.08:17:20.99#ibcon#read 5, iclass 26, count 2 2006.224.08:17:20.99#ibcon#about to read 6, iclass 26, count 2 2006.224.08:17:20.99#ibcon#read 6, iclass 26, count 2 2006.224.08:17:20.99#ibcon#end of sib2, iclass 26, count 2 2006.224.08:17:20.99#ibcon#*mode == 0, iclass 26, count 2 2006.224.08:17:20.99#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.224.08:17:21.00#ibcon#[27=AT02-04\r\n] 2006.224.08:17:21.00#ibcon#*before write, iclass 26, count 2 2006.224.08:17:21.00#ibcon#enter sib2, iclass 26, count 2 2006.224.08:17:21.00#ibcon#flushed, iclass 26, count 2 2006.224.08:17:21.00#ibcon#about to write, iclass 26, count 2 2006.224.08:17:21.00#ibcon#wrote, iclass 26, count 2 2006.224.08:17:21.00#ibcon#about to read 3, iclass 26, count 2 2006.224.08:17:21.02#ibcon#read 3, iclass 26, count 2 2006.224.08:17:21.02#ibcon#about to read 4, iclass 26, count 2 2006.224.08:17:21.02#ibcon#read 4, iclass 26, count 2 2006.224.08:17:21.02#ibcon#about to read 5, iclass 26, count 2 2006.224.08:17:21.02#ibcon#read 5, iclass 26, count 2 2006.224.08:17:21.02#ibcon#about to read 6, iclass 26, count 2 2006.224.08:17:21.02#ibcon#read 6, iclass 26, count 2 2006.224.08:17:21.02#ibcon#end of sib2, iclass 26, count 2 2006.224.08:17:21.02#ibcon#*after write, iclass 26, count 2 2006.224.08:17:21.03#ibcon#*before return 0, iclass 26, count 2 2006.224.08:17:21.03#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.224.08:17:21.03#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.224.08:17:21.03#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.224.08:17:21.03#ibcon#ireg 7 cls_cnt 0 2006.224.08:17:21.03#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.224.08:17:21.15#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.224.08:17:21.15#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.224.08:17:21.15#ibcon#enter wrdev, iclass 26, count 0 2006.224.08:17:21.15#ibcon#first serial, iclass 26, count 0 2006.224.08:17:21.15#ibcon#enter sib2, iclass 26, count 0 2006.224.08:17:21.15#ibcon#flushed, iclass 26, count 0 2006.224.08:17:21.15#ibcon#about to write, iclass 26, count 0 2006.224.08:17:21.15#ibcon#wrote, iclass 26, count 0 2006.224.08:17:21.15#ibcon#about to read 3, iclass 26, count 0 2006.224.08:17:21.16#ibcon#read 3, iclass 26, count 0 2006.224.08:17:21.16#ibcon#about to read 4, iclass 26, count 0 2006.224.08:17:21.16#ibcon#read 4, iclass 26, count 0 2006.224.08:17:21.16#ibcon#about to read 5, iclass 26, count 0 2006.224.08:17:21.16#ibcon#read 5, iclass 26, count 0 2006.224.08:17:21.16#ibcon#about to read 6, iclass 26, count 0 2006.224.08:17:21.16#ibcon#read 6, iclass 26, count 0 2006.224.08:17:21.16#ibcon#end of sib2, iclass 26, count 0 2006.224.08:17:21.16#ibcon#*mode == 0, iclass 26, count 0 2006.224.08:17:21.16#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.224.08:17:21.16#ibcon#[27=USB\r\n] 2006.224.08:17:21.17#ibcon#*before write, iclass 26, count 0 2006.224.08:17:21.17#ibcon#enter sib2, iclass 26, count 0 2006.224.08:17:21.17#ibcon#flushed, iclass 26, count 0 2006.224.08:17:21.17#ibcon#about to write, iclass 26, count 0 2006.224.08:17:21.17#ibcon#wrote, iclass 26, count 0 2006.224.08:17:21.17#ibcon#about to read 3, iclass 26, count 0 2006.224.08:17:21.19#ibcon#read 3, iclass 26, count 0 2006.224.08:17:21.19#ibcon#about to read 4, iclass 26, count 0 2006.224.08:17:21.19#ibcon#read 4, iclass 26, count 0 2006.224.08:17:21.19#ibcon#about to read 5, iclass 26, count 0 2006.224.08:17:21.19#ibcon#read 5, iclass 26, count 0 2006.224.08:17:21.19#ibcon#about to read 6, iclass 26, count 0 2006.224.08:17:21.19#ibcon#read 6, iclass 26, count 0 2006.224.08:17:21.19#ibcon#end of sib2, iclass 26, count 0 2006.224.08:17:21.19#ibcon#*after write, iclass 26, count 0 2006.224.08:17:21.19#ibcon#*before return 0, iclass 26, count 0 2006.224.08:17:21.20#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.224.08:17:21.20#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.224.08:17:21.20#ibcon#about to clear, iclass 26 cls_cnt 0 2006.224.08:17:21.20#ibcon#cleared, iclass 26 cls_cnt 0 2006.224.08:17:21.20$vc4f8/vblo=3,656.99 2006.224.08:17:21.20#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.224.08:17:21.20#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.224.08:17:21.20#ibcon#ireg 17 cls_cnt 0 2006.224.08:17:21.20#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.224.08:17:21.20#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.224.08:17:21.20#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.224.08:17:21.20#ibcon#enter wrdev, iclass 28, count 0 2006.224.08:17:21.20#ibcon#first serial, iclass 28, count 0 2006.224.08:17:21.20#ibcon#enter sib2, iclass 28, count 0 2006.224.08:17:21.20#ibcon#flushed, iclass 28, count 0 2006.224.08:17:21.20#ibcon#about to write, iclass 28, count 0 2006.224.08:17:21.20#ibcon#wrote, iclass 28, count 0 2006.224.08:17:21.20#ibcon#about to read 3, iclass 28, count 0 2006.224.08:17:21.21#ibcon#read 3, iclass 28, count 0 2006.224.08:17:21.21#ibcon#about to read 4, iclass 28, count 0 2006.224.08:17:21.21#ibcon#read 4, iclass 28, count 0 2006.224.08:17:21.21#ibcon#about to read 5, iclass 28, count 0 2006.224.08:17:21.21#ibcon#read 5, iclass 28, count 0 2006.224.08:17:21.21#ibcon#about to read 6, iclass 28, count 0 2006.224.08:17:21.21#ibcon#read 6, iclass 28, count 0 2006.224.08:17:21.21#ibcon#end of sib2, iclass 28, count 0 2006.224.08:17:21.21#ibcon#*mode == 0, iclass 28, count 0 2006.224.08:17:21.21#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.224.08:17:21.21#ibcon#[28=FRQ=03,656.99\r\n] 2006.224.08:17:21.22#ibcon#*before write, iclass 28, count 0 2006.224.08:17:21.22#ibcon#enter sib2, iclass 28, count 0 2006.224.08:17:21.22#ibcon#flushed, iclass 28, count 0 2006.224.08:17:21.22#ibcon#about to write, iclass 28, count 0 2006.224.08:17:21.22#ibcon#wrote, iclass 28, count 0 2006.224.08:17:21.22#ibcon#about to read 3, iclass 28, count 0 2006.224.08:17:21.25#ibcon#read 3, iclass 28, count 0 2006.224.08:17:21.25#ibcon#about to read 4, iclass 28, count 0 2006.224.08:17:21.25#ibcon#read 4, iclass 28, count 0 2006.224.08:17:21.25#ibcon#about to read 5, iclass 28, count 0 2006.224.08:17:21.25#ibcon#read 5, iclass 28, count 0 2006.224.08:17:21.25#ibcon#about to read 6, iclass 28, count 0 2006.224.08:17:21.25#ibcon#read 6, iclass 28, count 0 2006.224.08:17:21.25#ibcon#end of sib2, iclass 28, count 0 2006.224.08:17:21.25#ibcon#*after write, iclass 28, count 0 2006.224.08:17:21.25#ibcon#*before return 0, iclass 28, count 0 2006.224.08:17:21.26#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.224.08:17:21.26#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.224.08:17:21.26#ibcon#about to clear, iclass 28 cls_cnt 0 2006.224.08:17:21.26#ibcon#cleared, iclass 28 cls_cnt 0 2006.224.08:17:21.26$vc4f8/vb=3,4 2006.224.08:17:21.26#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.224.08:17:21.26#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.224.08:17:21.26#ibcon#ireg 11 cls_cnt 2 2006.224.08:17:21.26#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.224.08:17:21.31#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.224.08:17:21.31#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.224.08:17:21.31#ibcon#enter wrdev, iclass 30, count 2 2006.224.08:17:21.31#ibcon#first serial, iclass 30, count 2 2006.224.08:17:21.31#ibcon#enter sib2, iclass 30, count 2 2006.224.08:17:21.31#ibcon#flushed, iclass 30, count 2 2006.224.08:17:21.31#ibcon#about to write, iclass 30, count 2 2006.224.08:17:21.31#ibcon#wrote, iclass 30, count 2 2006.224.08:17:21.31#ibcon#about to read 3, iclass 30, count 2 2006.224.08:17:21.33#ibcon#read 3, iclass 30, count 2 2006.224.08:17:21.33#ibcon#about to read 4, iclass 30, count 2 2006.224.08:17:21.33#ibcon#read 4, iclass 30, count 2 2006.224.08:17:21.33#ibcon#about to read 5, iclass 30, count 2 2006.224.08:17:21.33#ibcon#read 5, iclass 30, count 2 2006.224.08:17:21.33#ibcon#about to read 6, iclass 30, count 2 2006.224.08:17:21.33#ibcon#read 6, iclass 30, count 2 2006.224.08:17:21.33#ibcon#end of sib2, iclass 30, count 2 2006.224.08:17:21.33#ibcon#*mode == 0, iclass 30, count 2 2006.224.08:17:21.33#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.224.08:17:21.33#ibcon#[27=AT03-04\r\n] 2006.224.08:17:21.33#ibcon#*before write, iclass 30, count 2 2006.224.08:17:21.34#ibcon#enter sib2, iclass 30, count 2 2006.224.08:17:21.34#ibcon#flushed, iclass 30, count 2 2006.224.08:17:21.34#ibcon#about to write, iclass 30, count 2 2006.224.08:17:21.34#ibcon#wrote, iclass 30, count 2 2006.224.08:17:21.34#ibcon#about to read 3, iclass 30, count 2 2006.224.08:17:21.36#ibcon#read 3, iclass 30, count 2 2006.224.08:17:21.36#ibcon#about to read 4, iclass 30, count 2 2006.224.08:17:21.36#ibcon#read 4, iclass 30, count 2 2006.224.08:17:21.36#ibcon#about to read 5, iclass 30, count 2 2006.224.08:17:21.36#ibcon#read 5, iclass 30, count 2 2006.224.08:17:21.36#ibcon#about to read 6, iclass 30, count 2 2006.224.08:17:21.36#ibcon#read 6, iclass 30, count 2 2006.224.08:17:21.36#ibcon#end of sib2, iclass 30, count 2 2006.224.08:17:21.36#ibcon#*after write, iclass 30, count 2 2006.224.08:17:21.37#ibcon#*before return 0, iclass 30, count 2 2006.224.08:17:21.37#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.224.08:17:21.37#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.224.08:17:21.37#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.224.08:17:21.37#ibcon#ireg 7 cls_cnt 0 2006.224.08:17:21.37#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.224.08:17:21.48#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.224.08:17:21.48#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.224.08:17:21.48#ibcon#enter wrdev, iclass 30, count 0 2006.224.08:17:21.48#ibcon#first serial, iclass 30, count 0 2006.224.08:17:21.48#ibcon#enter sib2, iclass 30, count 0 2006.224.08:17:21.48#ibcon#flushed, iclass 30, count 0 2006.224.08:17:21.48#ibcon#about to write, iclass 30, count 0 2006.224.08:17:21.48#ibcon#wrote, iclass 30, count 0 2006.224.08:17:21.48#ibcon#about to read 3, iclass 30, count 0 2006.224.08:17:21.50#ibcon#read 3, iclass 30, count 0 2006.224.08:17:21.50#ibcon#about to read 4, iclass 30, count 0 2006.224.08:17:21.50#ibcon#read 4, iclass 30, count 0 2006.224.08:17:21.50#ibcon#about to read 5, iclass 30, count 0 2006.224.08:17:21.50#ibcon#read 5, iclass 30, count 0 2006.224.08:17:21.50#ibcon#about to read 6, iclass 30, count 0 2006.224.08:17:21.50#ibcon#read 6, iclass 30, count 0 2006.224.08:17:21.50#ibcon#end of sib2, iclass 30, count 0 2006.224.08:17:21.50#ibcon#*mode == 0, iclass 30, count 0 2006.224.08:17:21.50#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.224.08:17:21.50#ibcon#[27=USB\r\n] 2006.224.08:17:21.51#ibcon#*before write, iclass 30, count 0 2006.224.08:17:21.51#ibcon#enter sib2, iclass 30, count 0 2006.224.08:17:21.51#ibcon#flushed, iclass 30, count 0 2006.224.08:17:21.51#ibcon#about to write, iclass 30, count 0 2006.224.08:17:21.51#ibcon#wrote, iclass 30, count 0 2006.224.08:17:21.51#ibcon#about to read 3, iclass 30, count 0 2006.224.08:17:21.53#ibcon#read 3, iclass 30, count 0 2006.224.08:17:21.53#ibcon#about to read 4, iclass 30, count 0 2006.224.08:17:21.53#ibcon#read 4, iclass 30, count 0 2006.224.08:17:21.53#ibcon#about to read 5, iclass 30, count 0 2006.224.08:17:21.53#ibcon#read 5, iclass 30, count 0 2006.224.08:17:21.53#ibcon#about to read 6, iclass 30, count 0 2006.224.08:17:21.53#ibcon#read 6, iclass 30, count 0 2006.224.08:17:21.53#ibcon#end of sib2, iclass 30, count 0 2006.224.08:17:21.53#ibcon#*after write, iclass 30, count 0 2006.224.08:17:21.53#ibcon#*before return 0, iclass 30, count 0 2006.224.08:17:21.54#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.224.08:17:21.54#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.224.08:17:21.54#ibcon#about to clear, iclass 30 cls_cnt 0 2006.224.08:17:21.54#ibcon#cleared, iclass 30 cls_cnt 0 2006.224.08:17:21.54$vc4f8/vblo=4,712.99 2006.224.08:17:21.54#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.224.08:17:21.54#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.224.08:17:21.54#ibcon#ireg 17 cls_cnt 0 2006.224.08:17:21.54#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.224.08:17:21.54#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.224.08:17:21.54#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.224.08:17:21.54#ibcon#enter wrdev, iclass 32, count 0 2006.224.08:17:21.54#ibcon#first serial, iclass 32, count 0 2006.224.08:17:21.54#ibcon#enter sib2, iclass 32, count 0 2006.224.08:17:21.54#ibcon#flushed, iclass 32, count 0 2006.224.08:17:21.54#ibcon#about to write, iclass 32, count 0 2006.224.08:17:21.54#ibcon#wrote, iclass 32, count 0 2006.224.08:17:21.54#ibcon#about to read 3, iclass 32, count 0 2006.224.08:17:21.55#ibcon#read 3, iclass 32, count 0 2006.224.08:17:21.55#ibcon#about to read 4, iclass 32, count 0 2006.224.08:17:21.55#ibcon#read 4, iclass 32, count 0 2006.224.08:17:21.55#ibcon#about to read 5, iclass 32, count 0 2006.224.08:17:21.55#ibcon#read 5, iclass 32, count 0 2006.224.08:17:21.55#ibcon#about to read 6, iclass 32, count 0 2006.224.08:17:21.55#ibcon#read 6, iclass 32, count 0 2006.224.08:17:21.55#ibcon#end of sib2, iclass 32, count 0 2006.224.08:17:21.55#ibcon#*mode == 0, iclass 32, count 0 2006.224.08:17:21.55#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.224.08:17:21.55#ibcon#[28=FRQ=04,712.99\r\n] 2006.224.08:17:21.56#ibcon#*before write, iclass 32, count 0 2006.224.08:17:21.56#ibcon#enter sib2, iclass 32, count 0 2006.224.08:17:21.56#ibcon#flushed, iclass 32, count 0 2006.224.08:17:21.56#ibcon#about to write, iclass 32, count 0 2006.224.08:17:21.56#ibcon#wrote, iclass 32, count 0 2006.224.08:17:21.56#ibcon#about to read 3, iclass 32, count 0 2006.224.08:17:21.59#ibcon#read 3, iclass 32, count 0 2006.224.08:17:21.59#ibcon#about to read 4, iclass 32, count 0 2006.224.08:17:21.59#ibcon#read 4, iclass 32, count 0 2006.224.08:17:21.59#ibcon#about to read 5, iclass 32, count 0 2006.224.08:17:21.59#ibcon#read 5, iclass 32, count 0 2006.224.08:17:21.59#ibcon#about to read 6, iclass 32, count 0 2006.224.08:17:21.59#ibcon#read 6, iclass 32, count 0 2006.224.08:17:21.59#ibcon#end of sib2, iclass 32, count 0 2006.224.08:17:21.59#ibcon#*after write, iclass 32, count 0 2006.224.08:17:21.59#ibcon#*before return 0, iclass 32, count 0 2006.224.08:17:21.60#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.224.08:17:21.60#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.224.08:17:21.60#ibcon#about to clear, iclass 32 cls_cnt 0 2006.224.08:17:21.60#ibcon#cleared, iclass 32 cls_cnt 0 2006.224.08:17:21.60$vc4f8/vb=4,4 2006.224.08:17:21.60#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.224.08:17:21.60#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.224.08:17:21.60#ibcon#ireg 11 cls_cnt 2 2006.224.08:17:21.60#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.224.08:17:21.65#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.224.08:17:21.65#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.224.08:17:21.65#ibcon#enter wrdev, iclass 34, count 2 2006.224.08:17:21.65#ibcon#first serial, iclass 34, count 2 2006.224.08:17:21.65#ibcon#enter sib2, iclass 34, count 2 2006.224.08:17:21.65#ibcon#flushed, iclass 34, count 2 2006.224.08:17:21.65#ibcon#about to write, iclass 34, count 2 2006.224.08:17:21.65#ibcon#wrote, iclass 34, count 2 2006.224.08:17:21.65#ibcon#about to read 3, iclass 34, count 2 2006.224.08:17:21.67#ibcon#read 3, iclass 34, count 2 2006.224.08:17:21.67#ibcon#about to read 4, iclass 34, count 2 2006.224.08:17:21.67#ibcon#read 4, iclass 34, count 2 2006.224.08:17:21.67#ibcon#about to read 5, iclass 34, count 2 2006.224.08:17:21.67#ibcon#read 5, iclass 34, count 2 2006.224.08:17:21.67#ibcon#about to read 6, iclass 34, count 2 2006.224.08:17:21.67#ibcon#read 6, iclass 34, count 2 2006.224.08:17:21.67#ibcon#end of sib2, iclass 34, count 2 2006.224.08:17:21.67#ibcon#*mode == 0, iclass 34, count 2 2006.224.08:17:21.67#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.224.08:17:21.67#ibcon#[27=AT04-04\r\n] 2006.224.08:17:21.68#ibcon#*before write, iclass 34, count 2 2006.224.08:17:21.68#ibcon#enter sib2, iclass 34, count 2 2006.224.08:17:21.68#ibcon#flushed, iclass 34, count 2 2006.224.08:17:21.68#ibcon#about to write, iclass 34, count 2 2006.224.08:17:21.68#ibcon#wrote, iclass 34, count 2 2006.224.08:17:21.68#ibcon#about to read 3, iclass 34, count 2 2006.224.08:17:21.70#ibcon#read 3, iclass 34, count 2 2006.224.08:17:21.70#ibcon#about to read 4, iclass 34, count 2 2006.224.08:17:21.70#ibcon#read 4, iclass 34, count 2 2006.224.08:17:21.70#ibcon#about to read 5, iclass 34, count 2 2006.224.08:17:21.70#ibcon#read 5, iclass 34, count 2 2006.224.08:17:21.70#ibcon#about to read 6, iclass 34, count 2 2006.224.08:17:21.70#ibcon#read 6, iclass 34, count 2 2006.224.08:17:21.70#ibcon#end of sib2, iclass 34, count 2 2006.224.08:17:21.70#ibcon#*after write, iclass 34, count 2 2006.224.08:17:21.71#ibcon#*before return 0, iclass 34, count 2 2006.224.08:17:21.71#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.224.08:17:21.71#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.224.08:17:21.71#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.224.08:17:21.71#ibcon#ireg 7 cls_cnt 0 2006.224.08:17:21.71#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.224.08:17:21.82#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.224.08:17:21.82#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.224.08:17:21.82#ibcon#enter wrdev, iclass 34, count 0 2006.224.08:17:21.82#ibcon#first serial, iclass 34, count 0 2006.224.08:17:21.82#ibcon#enter sib2, iclass 34, count 0 2006.224.08:17:21.82#ibcon#flushed, iclass 34, count 0 2006.224.08:17:21.82#ibcon#about to write, iclass 34, count 0 2006.224.08:17:21.82#ibcon#wrote, iclass 34, count 0 2006.224.08:17:21.82#ibcon#about to read 3, iclass 34, count 0 2006.224.08:17:21.84#ibcon#read 3, iclass 34, count 0 2006.224.08:17:21.84#ibcon#about to read 4, iclass 34, count 0 2006.224.08:17:21.84#ibcon#read 4, iclass 34, count 0 2006.224.08:17:21.84#ibcon#about to read 5, iclass 34, count 0 2006.224.08:17:21.84#ibcon#read 5, iclass 34, count 0 2006.224.08:17:21.84#ibcon#about to read 6, iclass 34, count 0 2006.224.08:17:21.84#ibcon#read 6, iclass 34, count 0 2006.224.08:17:21.84#ibcon#end of sib2, iclass 34, count 0 2006.224.08:17:21.84#ibcon#*mode == 0, iclass 34, count 0 2006.224.08:17:21.84#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.224.08:17:21.84#ibcon#[27=USB\r\n] 2006.224.08:17:21.85#ibcon#*before write, iclass 34, count 0 2006.224.08:17:21.85#ibcon#enter sib2, iclass 34, count 0 2006.224.08:17:21.85#ibcon#flushed, iclass 34, count 0 2006.224.08:17:21.85#ibcon#about to write, iclass 34, count 0 2006.224.08:17:21.85#ibcon#wrote, iclass 34, count 0 2006.224.08:17:21.85#ibcon#about to read 3, iclass 34, count 0 2006.224.08:17:21.87#ibcon#read 3, iclass 34, count 0 2006.224.08:17:21.87#ibcon#about to read 4, iclass 34, count 0 2006.224.08:17:21.87#ibcon#read 4, iclass 34, count 0 2006.224.08:17:21.87#ibcon#about to read 5, iclass 34, count 0 2006.224.08:17:21.87#ibcon#read 5, iclass 34, count 0 2006.224.08:17:21.87#ibcon#about to read 6, iclass 34, count 0 2006.224.08:17:21.87#ibcon#read 6, iclass 34, count 0 2006.224.08:17:21.87#ibcon#end of sib2, iclass 34, count 0 2006.224.08:17:21.87#ibcon#*after write, iclass 34, count 0 2006.224.08:17:21.87#ibcon#*before return 0, iclass 34, count 0 2006.224.08:17:21.88#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.224.08:17:21.88#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.224.08:17:21.88#ibcon#about to clear, iclass 34 cls_cnt 0 2006.224.08:17:21.88#ibcon#cleared, iclass 34 cls_cnt 0 2006.224.08:17:21.88$vc4f8/vblo=5,744.99 2006.224.08:17:21.88#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.224.08:17:21.88#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.224.08:17:21.88#ibcon#ireg 17 cls_cnt 0 2006.224.08:17:21.88#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.224.08:17:21.88#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.224.08:17:21.88#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.224.08:17:21.88#ibcon#enter wrdev, iclass 36, count 0 2006.224.08:17:21.88#ibcon#first serial, iclass 36, count 0 2006.224.08:17:21.88#ibcon#enter sib2, iclass 36, count 0 2006.224.08:17:21.88#ibcon#flushed, iclass 36, count 0 2006.224.08:17:21.88#ibcon#about to write, iclass 36, count 0 2006.224.08:17:21.88#ibcon#wrote, iclass 36, count 0 2006.224.08:17:21.88#ibcon#about to read 3, iclass 36, count 0 2006.224.08:17:21.89#ibcon#read 3, iclass 36, count 0 2006.224.08:17:21.89#ibcon#about to read 4, iclass 36, count 0 2006.224.08:17:21.89#ibcon#read 4, iclass 36, count 0 2006.224.08:17:21.89#ibcon#about to read 5, iclass 36, count 0 2006.224.08:17:21.89#ibcon#read 5, iclass 36, count 0 2006.224.08:17:21.89#ibcon#about to read 6, iclass 36, count 0 2006.224.08:17:21.89#ibcon#read 6, iclass 36, count 0 2006.224.08:17:21.89#ibcon#end of sib2, iclass 36, count 0 2006.224.08:17:21.89#ibcon#*mode == 0, iclass 36, count 0 2006.224.08:17:21.89#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.224.08:17:21.89#ibcon#[28=FRQ=05,744.99\r\n] 2006.224.08:17:21.90#ibcon#*before write, iclass 36, count 0 2006.224.08:17:21.90#ibcon#enter sib2, iclass 36, count 0 2006.224.08:17:21.90#ibcon#flushed, iclass 36, count 0 2006.224.08:17:21.90#ibcon#about to write, iclass 36, count 0 2006.224.08:17:21.90#ibcon#wrote, iclass 36, count 0 2006.224.08:17:21.90#ibcon#about to read 3, iclass 36, count 0 2006.224.08:17:21.93#ibcon#read 3, iclass 36, count 0 2006.224.08:17:21.93#ibcon#about to read 4, iclass 36, count 0 2006.224.08:17:21.93#ibcon#read 4, iclass 36, count 0 2006.224.08:17:21.93#ibcon#about to read 5, iclass 36, count 0 2006.224.08:17:21.93#ibcon#read 5, iclass 36, count 0 2006.224.08:17:21.93#ibcon#about to read 6, iclass 36, count 0 2006.224.08:17:21.93#ibcon#read 6, iclass 36, count 0 2006.224.08:17:21.93#ibcon#end of sib2, iclass 36, count 0 2006.224.08:17:21.93#ibcon#*after write, iclass 36, count 0 2006.224.08:17:21.93#ibcon#*before return 0, iclass 36, count 0 2006.224.08:17:21.94#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.224.08:17:21.94#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.224.08:17:21.94#ibcon#about to clear, iclass 36 cls_cnt 0 2006.224.08:17:21.94#ibcon#cleared, iclass 36 cls_cnt 0 2006.224.08:17:21.94$vc4f8/vb=5,4 2006.224.08:17:21.94#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.224.08:17:21.94#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.224.08:17:21.94#ibcon#ireg 11 cls_cnt 2 2006.224.08:17:21.94#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.224.08:17:21.99#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.224.08:17:21.99#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.224.08:17:21.99#ibcon#enter wrdev, iclass 38, count 2 2006.224.08:17:21.99#ibcon#first serial, iclass 38, count 2 2006.224.08:17:21.99#ibcon#enter sib2, iclass 38, count 2 2006.224.08:17:21.99#ibcon#flushed, iclass 38, count 2 2006.224.08:17:21.99#ibcon#about to write, iclass 38, count 2 2006.224.08:17:21.99#ibcon#wrote, iclass 38, count 2 2006.224.08:17:21.99#ibcon#about to read 3, iclass 38, count 2 2006.224.08:17:22.01#ibcon#read 3, iclass 38, count 2 2006.224.08:17:22.01#ibcon#about to read 4, iclass 38, count 2 2006.224.08:17:22.01#ibcon#read 4, iclass 38, count 2 2006.224.08:17:22.01#ibcon#about to read 5, iclass 38, count 2 2006.224.08:17:22.01#ibcon#read 5, iclass 38, count 2 2006.224.08:17:22.01#ibcon#about to read 6, iclass 38, count 2 2006.224.08:17:22.01#ibcon#read 6, iclass 38, count 2 2006.224.08:17:22.01#ibcon#end of sib2, iclass 38, count 2 2006.224.08:17:22.01#ibcon#*mode == 0, iclass 38, count 2 2006.224.08:17:22.01#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.224.08:17:22.01#ibcon#[27=AT05-04\r\n] 2006.224.08:17:22.02#ibcon#*before write, iclass 38, count 2 2006.224.08:17:22.02#ibcon#enter sib2, iclass 38, count 2 2006.224.08:17:22.02#ibcon#flushed, iclass 38, count 2 2006.224.08:17:22.02#ibcon#about to write, iclass 38, count 2 2006.224.08:17:22.02#ibcon#wrote, iclass 38, count 2 2006.224.08:17:22.02#ibcon#about to read 3, iclass 38, count 2 2006.224.08:17:22.04#ibcon#read 3, iclass 38, count 2 2006.224.08:17:22.04#ibcon#about to read 4, iclass 38, count 2 2006.224.08:17:22.04#ibcon#read 4, iclass 38, count 2 2006.224.08:17:22.04#ibcon#about to read 5, iclass 38, count 2 2006.224.08:17:22.04#ibcon#read 5, iclass 38, count 2 2006.224.08:17:22.04#ibcon#about to read 6, iclass 38, count 2 2006.224.08:17:22.04#ibcon#read 6, iclass 38, count 2 2006.224.08:17:22.04#ibcon#end of sib2, iclass 38, count 2 2006.224.08:17:22.04#ibcon#*after write, iclass 38, count 2 2006.224.08:17:22.05#ibcon#*before return 0, iclass 38, count 2 2006.224.08:17:22.05#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.224.08:17:22.05#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.224.08:17:22.05#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.224.08:17:22.05#ibcon#ireg 7 cls_cnt 0 2006.224.08:17:22.05#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.224.08:17:22.06#abcon#<5=/11 1.4 3.2 23.811001004.6\r\n> 2006.224.08:17:22.08#abcon#{5=INTERFACE CLEAR} 2006.224.08:17:22.14#abcon#[5=S1D000X0/0*\r\n] 2006.224.08:17:22.16#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.224.08:17:22.16#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.224.08:17:22.17#ibcon#enter wrdev, iclass 38, count 0 2006.224.08:17:22.17#ibcon#first serial, iclass 38, count 0 2006.224.08:17:22.17#ibcon#enter sib2, iclass 38, count 0 2006.224.08:17:22.17#ibcon#flushed, iclass 38, count 0 2006.224.08:17:22.17#ibcon#about to write, iclass 38, count 0 2006.224.08:17:22.17#ibcon#wrote, iclass 38, count 0 2006.224.08:17:22.17#ibcon#about to read 3, iclass 38, count 0 2006.224.08:17:22.18#ibcon#read 3, iclass 38, count 0 2006.224.08:17:22.18#ibcon#about to read 4, iclass 38, count 0 2006.224.08:17:22.18#ibcon#read 4, iclass 38, count 0 2006.224.08:17:22.18#ibcon#about to read 5, iclass 38, count 0 2006.224.08:17:22.18#ibcon#read 5, iclass 38, count 0 2006.224.08:17:22.18#ibcon#about to read 6, iclass 38, count 0 2006.224.08:17:22.18#ibcon#read 6, iclass 38, count 0 2006.224.08:17:22.18#ibcon#end of sib2, iclass 38, count 0 2006.224.08:17:22.18#ibcon#*mode == 0, iclass 38, count 0 2006.224.08:17:22.18#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.224.08:17:22.18#ibcon#[27=USB\r\n] 2006.224.08:17:22.18#ibcon#*before write, iclass 38, count 0 2006.224.08:17:22.19#ibcon#enter sib2, iclass 38, count 0 2006.224.08:17:22.19#ibcon#flushed, iclass 38, count 0 2006.224.08:17:22.19#ibcon#about to write, iclass 38, count 0 2006.224.08:17:22.19#ibcon#wrote, iclass 38, count 0 2006.224.08:17:22.19#ibcon#about to read 3, iclass 38, count 0 2006.224.08:17:22.21#ibcon#read 3, iclass 38, count 0 2006.224.08:17:22.21#ibcon#about to read 4, iclass 38, count 0 2006.224.08:17:22.21#ibcon#read 4, iclass 38, count 0 2006.224.08:17:22.21#ibcon#about to read 5, iclass 38, count 0 2006.224.08:17:22.21#ibcon#read 5, iclass 38, count 0 2006.224.08:17:22.21#ibcon#about to read 6, iclass 38, count 0 2006.224.08:17:22.21#ibcon#read 6, iclass 38, count 0 2006.224.08:17:22.21#ibcon#end of sib2, iclass 38, count 0 2006.224.08:17:22.21#ibcon#*after write, iclass 38, count 0 2006.224.08:17:22.22#ibcon#*before return 0, iclass 38, count 0 2006.224.08:17:22.22#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.224.08:17:22.22#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.224.08:17:22.22#ibcon#about to clear, iclass 38 cls_cnt 0 2006.224.08:17:22.22#ibcon#cleared, iclass 38 cls_cnt 0 2006.224.08:17:22.22$vc4f8/vblo=6,752.99 2006.224.08:17:22.22#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.224.08:17:22.22#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.224.08:17:22.22#ibcon#ireg 17 cls_cnt 0 2006.224.08:17:22.22#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.224.08:17:22.22#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.224.08:17:22.22#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.224.08:17:22.22#ibcon#enter wrdev, iclass 6, count 0 2006.224.08:17:22.22#ibcon#first serial, iclass 6, count 0 2006.224.08:17:22.22#ibcon#enter sib2, iclass 6, count 0 2006.224.08:17:22.22#ibcon#flushed, iclass 6, count 0 2006.224.08:17:22.22#ibcon#about to write, iclass 6, count 0 2006.224.08:17:22.22#ibcon#wrote, iclass 6, count 0 2006.224.08:17:22.22#ibcon#about to read 3, iclass 6, count 0 2006.224.08:17:22.23#ibcon#read 3, iclass 6, count 0 2006.224.08:17:22.23#ibcon#about to read 4, iclass 6, count 0 2006.224.08:17:22.23#ibcon#read 4, iclass 6, count 0 2006.224.08:17:22.23#ibcon#about to read 5, iclass 6, count 0 2006.224.08:17:22.23#ibcon#read 5, iclass 6, count 0 2006.224.08:17:22.23#ibcon#about to read 6, iclass 6, count 0 2006.224.08:17:22.23#ibcon#read 6, iclass 6, count 0 2006.224.08:17:22.23#ibcon#end of sib2, iclass 6, count 0 2006.224.08:17:22.23#ibcon#*mode == 0, iclass 6, count 0 2006.224.08:17:22.23#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.224.08:17:22.24#ibcon#[28=FRQ=06,752.99\r\n] 2006.224.08:17:22.24#ibcon#*before write, iclass 6, count 0 2006.224.08:17:22.24#ibcon#enter sib2, iclass 6, count 0 2006.224.08:17:22.24#ibcon#flushed, iclass 6, count 0 2006.224.08:17:22.24#ibcon#about to write, iclass 6, count 0 2006.224.08:17:22.24#ibcon#wrote, iclass 6, count 0 2006.224.08:17:22.24#ibcon#about to read 3, iclass 6, count 0 2006.224.08:17:22.27#ibcon#read 3, iclass 6, count 0 2006.224.08:17:22.27#ibcon#about to read 4, iclass 6, count 0 2006.224.08:17:22.27#ibcon#read 4, iclass 6, count 0 2006.224.08:17:22.27#ibcon#about to read 5, iclass 6, count 0 2006.224.08:17:22.27#ibcon#read 5, iclass 6, count 0 2006.224.08:17:22.27#ibcon#about to read 6, iclass 6, count 0 2006.224.08:17:22.27#ibcon#read 6, iclass 6, count 0 2006.224.08:17:22.27#ibcon#end of sib2, iclass 6, count 0 2006.224.08:17:22.28#ibcon#*after write, iclass 6, count 0 2006.224.08:17:22.28#ibcon#*before return 0, iclass 6, count 0 2006.224.08:17:22.28#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.224.08:17:22.28#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.224.08:17:22.28#ibcon#about to clear, iclass 6 cls_cnt 0 2006.224.08:17:22.28#ibcon#cleared, iclass 6 cls_cnt 0 2006.224.08:17:22.28$vc4f8/vb=6,4 2006.224.08:17:22.28#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.224.08:17:22.28#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.224.08:17:22.28#ibcon#ireg 11 cls_cnt 2 2006.224.08:17:22.28#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.224.08:17:22.33#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.224.08:17:22.33#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.224.08:17:22.33#ibcon#enter wrdev, iclass 10, count 2 2006.224.08:17:22.33#ibcon#first serial, iclass 10, count 2 2006.224.08:17:22.33#ibcon#enter sib2, iclass 10, count 2 2006.224.08:17:22.33#ibcon#flushed, iclass 10, count 2 2006.224.08:17:22.33#ibcon#about to write, iclass 10, count 2 2006.224.08:17:22.33#ibcon#wrote, iclass 10, count 2 2006.224.08:17:22.33#ibcon#about to read 3, iclass 10, count 2 2006.224.08:17:22.36#ibcon#read 3, iclass 10, count 2 2006.224.08:17:22.36#ibcon#about to read 4, iclass 10, count 2 2006.224.08:17:22.36#ibcon#read 4, iclass 10, count 2 2006.224.08:17:22.36#ibcon#about to read 5, iclass 10, count 2 2006.224.08:17:22.36#ibcon#read 5, iclass 10, count 2 2006.224.08:17:22.36#ibcon#about to read 6, iclass 10, count 2 2006.224.08:17:22.36#ibcon#read 6, iclass 10, count 2 2006.224.08:17:22.36#ibcon#end of sib2, iclass 10, count 2 2006.224.08:17:22.36#ibcon#*mode == 0, iclass 10, count 2 2006.224.08:17:22.36#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.224.08:17:22.36#ibcon#[27=AT06-04\r\n] 2006.224.08:17:22.36#ibcon#*before write, iclass 10, count 2 2006.224.08:17:22.36#ibcon#enter sib2, iclass 10, count 2 2006.224.08:17:22.36#ibcon#flushed, iclass 10, count 2 2006.224.08:17:22.36#ibcon#about to write, iclass 10, count 2 2006.224.08:17:22.36#ibcon#wrote, iclass 10, count 2 2006.224.08:17:22.36#ibcon#about to read 3, iclass 10, count 2 2006.224.08:17:22.38#ibcon#read 3, iclass 10, count 2 2006.224.08:17:22.38#ibcon#about to read 4, iclass 10, count 2 2006.224.08:17:22.38#ibcon#read 4, iclass 10, count 2 2006.224.08:17:22.38#ibcon#about to read 5, iclass 10, count 2 2006.224.08:17:22.38#ibcon#read 5, iclass 10, count 2 2006.224.08:17:22.38#ibcon#about to read 6, iclass 10, count 2 2006.224.08:17:22.38#ibcon#read 6, iclass 10, count 2 2006.224.08:17:22.38#ibcon#end of sib2, iclass 10, count 2 2006.224.08:17:22.38#ibcon#*after write, iclass 10, count 2 2006.224.08:17:22.38#ibcon#*before return 0, iclass 10, count 2 2006.224.08:17:22.39#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.224.08:17:22.39#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.224.08:17:22.39#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.224.08:17:22.39#ibcon#ireg 7 cls_cnt 0 2006.224.08:17:22.39#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.224.08:17:22.50#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.224.08:17:22.50#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.224.08:17:22.50#ibcon#enter wrdev, iclass 10, count 0 2006.224.08:17:22.50#ibcon#first serial, iclass 10, count 0 2006.224.08:17:22.50#ibcon#enter sib2, iclass 10, count 0 2006.224.08:17:22.50#ibcon#flushed, iclass 10, count 0 2006.224.08:17:22.50#ibcon#about to write, iclass 10, count 0 2006.224.08:17:22.50#ibcon#wrote, iclass 10, count 0 2006.224.08:17:22.50#ibcon#about to read 3, iclass 10, count 0 2006.224.08:17:22.52#ibcon#read 3, iclass 10, count 0 2006.224.08:17:22.52#ibcon#about to read 4, iclass 10, count 0 2006.224.08:17:22.52#ibcon#read 4, iclass 10, count 0 2006.224.08:17:22.52#ibcon#about to read 5, iclass 10, count 0 2006.224.08:17:22.52#ibcon#read 5, iclass 10, count 0 2006.224.08:17:22.52#ibcon#about to read 6, iclass 10, count 0 2006.224.08:17:22.52#ibcon#read 6, iclass 10, count 0 2006.224.08:17:22.52#ibcon#end of sib2, iclass 10, count 0 2006.224.08:17:22.52#ibcon#*mode == 0, iclass 10, count 0 2006.224.08:17:22.52#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.224.08:17:22.52#ibcon#[27=USB\r\n] 2006.224.08:17:22.53#ibcon#*before write, iclass 10, count 0 2006.224.08:17:22.53#ibcon#enter sib2, iclass 10, count 0 2006.224.08:17:22.53#ibcon#flushed, iclass 10, count 0 2006.224.08:17:22.53#ibcon#about to write, iclass 10, count 0 2006.224.08:17:22.53#ibcon#wrote, iclass 10, count 0 2006.224.08:17:22.53#ibcon#about to read 3, iclass 10, count 0 2006.224.08:17:22.55#ibcon#read 3, iclass 10, count 0 2006.224.08:17:22.55#ibcon#about to read 4, iclass 10, count 0 2006.224.08:17:22.55#ibcon#read 4, iclass 10, count 0 2006.224.08:17:22.55#ibcon#about to read 5, iclass 10, count 0 2006.224.08:17:22.55#ibcon#read 5, iclass 10, count 0 2006.224.08:17:22.55#ibcon#about to read 6, iclass 10, count 0 2006.224.08:17:22.55#ibcon#read 6, iclass 10, count 0 2006.224.08:17:22.55#ibcon#end of sib2, iclass 10, count 0 2006.224.08:17:22.55#ibcon#*after write, iclass 10, count 0 2006.224.08:17:22.55#ibcon#*before return 0, iclass 10, count 0 2006.224.08:17:22.55#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.224.08:17:22.56#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.224.08:17:22.56#ibcon#about to clear, iclass 10 cls_cnt 0 2006.224.08:17:22.56#ibcon#cleared, iclass 10 cls_cnt 0 2006.224.08:17:22.56$vc4f8/vabw=wide 2006.224.08:17:22.56#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.224.08:17:22.56#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.224.08:17:22.56#ibcon#ireg 8 cls_cnt 0 2006.224.08:17:22.56#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.224.08:17:22.56#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.224.08:17:22.56#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.224.08:17:22.56#ibcon#enter wrdev, iclass 12, count 0 2006.224.08:17:22.56#ibcon#first serial, iclass 12, count 0 2006.224.08:17:22.56#ibcon#enter sib2, iclass 12, count 0 2006.224.08:17:22.56#ibcon#flushed, iclass 12, count 0 2006.224.08:17:22.56#ibcon#about to write, iclass 12, count 0 2006.224.08:17:22.56#ibcon#wrote, iclass 12, count 0 2006.224.08:17:22.56#ibcon#about to read 3, iclass 12, count 0 2006.224.08:17:22.57#ibcon#read 3, iclass 12, count 0 2006.224.08:17:22.57#ibcon#about to read 4, iclass 12, count 0 2006.224.08:17:22.57#ibcon#read 4, iclass 12, count 0 2006.224.08:17:22.57#ibcon#about to read 5, iclass 12, count 0 2006.224.08:17:22.57#ibcon#read 5, iclass 12, count 0 2006.224.08:17:22.57#ibcon#about to read 6, iclass 12, count 0 2006.224.08:17:22.57#ibcon#read 6, iclass 12, count 0 2006.224.08:17:22.57#ibcon#end of sib2, iclass 12, count 0 2006.224.08:17:22.57#ibcon#*mode == 0, iclass 12, count 0 2006.224.08:17:22.57#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.224.08:17:22.57#ibcon#[25=BW32\r\n] 2006.224.08:17:22.58#ibcon#*before write, iclass 12, count 0 2006.224.08:17:22.58#ibcon#enter sib2, iclass 12, count 0 2006.224.08:17:22.58#ibcon#flushed, iclass 12, count 0 2006.224.08:17:22.58#ibcon#about to write, iclass 12, count 0 2006.224.08:17:22.58#ibcon#wrote, iclass 12, count 0 2006.224.08:17:22.58#ibcon#about to read 3, iclass 12, count 0 2006.224.08:17:22.60#ibcon#read 3, iclass 12, count 0 2006.224.08:17:22.60#ibcon#about to read 4, iclass 12, count 0 2006.224.08:17:22.60#ibcon#read 4, iclass 12, count 0 2006.224.08:17:22.60#ibcon#about to read 5, iclass 12, count 0 2006.224.08:17:22.60#ibcon#read 5, iclass 12, count 0 2006.224.08:17:22.60#ibcon#about to read 6, iclass 12, count 0 2006.224.08:17:22.60#ibcon#read 6, iclass 12, count 0 2006.224.08:17:22.60#ibcon#end of sib2, iclass 12, count 0 2006.224.08:17:22.60#ibcon#*after write, iclass 12, count 0 2006.224.08:17:22.60#ibcon#*before return 0, iclass 12, count 0 2006.224.08:17:22.60#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.224.08:17:22.61#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.224.08:17:22.61#ibcon#about to clear, iclass 12 cls_cnt 0 2006.224.08:17:22.61#ibcon#cleared, iclass 12 cls_cnt 0 2006.224.08:17:22.61$vc4f8/vbbw=wide 2006.224.08:17:22.61#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.224.08:17:22.61#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.224.08:17:22.61#ibcon#ireg 8 cls_cnt 0 2006.224.08:17:22.61#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.224.08:17:22.67#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.224.08:17:22.67#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.224.08:17:22.67#ibcon#enter wrdev, iclass 14, count 0 2006.224.08:17:22.67#ibcon#first serial, iclass 14, count 0 2006.224.08:17:22.67#ibcon#enter sib2, iclass 14, count 0 2006.224.08:17:22.67#ibcon#flushed, iclass 14, count 0 2006.224.08:17:22.67#ibcon#about to write, iclass 14, count 0 2006.224.08:17:22.67#ibcon#wrote, iclass 14, count 0 2006.224.08:17:22.67#ibcon#about to read 3, iclass 14, count 0 2006.224.08:17:22.69#ibcon#read 3, iclass 14, count 0 2006.224.08:17:22.69#ibcon#about to read 4, iclass 14, count 0 2006.224.08:17:22.69#ibcon#read 4, iclass 14, count 0 2006.224.08:17:22.69#ibcon#about to read 5, iclass 14, count 0 2006.224.08:17:22.69#ibcon#read 5, iclass 14, count 0 2006.224.08:17:22.69#ibcon#about to read 6, iclass 14, count 0 2006.224.08:17:22.69#ibcon#read 6, iclass 14, count 0 2006.224.08:17:22.69#ibcon#end of sib2, iclass 14, count 0 2006.224.08:17:22.69#ibcon#*mode == 0, iclass 14, count 0 2006.224.08:17:22.69#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.224.08:17:22.70#ibcon#[27=BW32\r\n] 2006.224.08:17:22.70#ibcon#*before write, iclass 14, count 0 2006.224.08:17:22.70#ibcon#enter sib2, iclass 14, count 0 2006.224.08:17:22.70#ibcon#flushed, iclass 14, count 0 2006.224.08:17:22.70#ibcon#about to write, iclass 14, count 0 2006.224.08:17:22.70#ibcon#wrote, iclass 14, count 0 2006.224.08:17:22.70#ibcon#about to read 3, iclass 14, count 0 2006.224.08:17:22.72#ibcon#read 3, iclass 14, count 0 2006.224.08:17:22.72#ibcon#about to read 4, iclass 14, count 0 2006.224.08:17:22.72#ibcon#read 4, iclass 14, count 0 2006.224.08:17:22.72#ibcon#about to read 5, iclass 14, count 0 2006.224.08:17:22.72#ibcon#read 5, iclass 14, count 0 2006.224.08:17:22.72#ibcon#about to read 6, iclass 14, count 0 2006.224.08:17:22.72#ibcon#read 6, iclass 14, count 0 2006.224.08:17:22.72#ibcon#end of sib2, iclass 14, count 0 2006.224.08:17:22.72#ibcon#*after write, iclass 14, count 0 2006.224.08:17:22.73#ibcon#*before return 0, iclass 14, count 0 2006.224.08:17:22.73#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.224.08:17:22.73#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.224.08:17:22.73#ibcon#about to clear, iclass 14 cls_cnt 0 2006.224.08:17:22.73#ibcon#cleared, iclass 14 cls_cnt 0 2006.224.08:17:22.73$4f8m12a/ifd4f 2006.224.08:17:22.73$ifd4f/lo= 2006.224.08:17:22.73$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.224.08:17:22.73$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.224.08:17:22.73$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.224.08:17:22.73$ifd4f/patch= 2006.224.08:17:22.73$ifd4f/patch=lo1,a1,a2,a3,a4 2006.224.08:17:22.73$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.224.08:17:22.73$ifd4f/patch=lo3,a5,a6,a7,a8 2006.224.08:17:22.73$4f8m12a/"form=m,16.000,1:2 2006.224.08:17:22.73$4f8m12a/"tpicd 2006.224.08:17:22.73$4f8m12a/echo=off 2006.224.08:17:22.73$4f8m12a/xlog=off 2006.224.08:17:22.73:!2006.224.08:17:50 2006.224.08:17:34.14#trakl#Source acquired 2006.224.08:17:35.15#flagr#flagr/antenna,acquired 2006.224.08:17:50.02:preob 2006.224.08:17:51.15/onsource/TRACKING 2006.224.08:17:51.15:!2006.224.08:18:00 2006.224.08:18:00.02:data_valid=on 2006.224.08:18:00.02:midob 2006.224.08:18:01.15/onsource/TRACKING 2006.224.08:18:01.15/wx/23.81,1004.6,100 2006.224.08:18:01.30/cable/+6.4348E-03 2006.224.08:18:02.39/va/01,08,usb,yes,43,45 2006.224.08:18:02.39/va/02,07,usb,yes,43,45 2006.224.08:18:02.39/va/03,06,usb,yes,46,46 2006.224.08:18:02.39/va/04,07,usb,yes,45,48 2006.224.08:18:02.39/va/05,07,usb,yes,52,55 2006.224.08:18:02.39/va/06,06,usb,yes,52,51 2006.224.08:18:02.39/va/07,06,usb,yes,52,52 2006.224.08:18:02.39/va/08,07,usb,yes,50,49 2006.224.08:18:02.62/valo/01,532.99,yes,locked 2006.224.08:18:02.62/valo/02,572.99,yes,locked 2006.224.08:18:02.62/valo/03,672.99,yes,locked 2006.224.08:18:02.62/valo/04,832.99,yes,locked 2006.224.08:18:02.62/valo/05,652.99,yes,locked 2006.224.08:18:02.62/valo/06,772.99,yes,locked 2006.224.08:18:02.62/valo/07,832.99,yes,locked 2006.224.08:18:02.62/valo/08,852.99,yes,locked 2006.224.08:18:03.71/vb/01,04,usb,yes,32,30 2006.224.08:18:03.71/vb/02,04,usb,yes,33,35 2006.224.08:18:03.71/vb/03,04,usb,yes,30,34 2006.224.08:18:03.71/vb/04,04,usb,yes,31,31 2006.224.08:18:03.71/vb/05,04,usb,yes,29,33 2006.224.08:18:03.71/vb/06,04,usb,yes,30,33 2006.224.08:18:03.71/vb/07,04,usb,yes,32,32 2006.224.08:18:03.71/vb/08,04,usb,yes,30,33 2006.224.08:18:03.94/vblo/01,632.99,yes,locked 2006.224.08:18:03.94/vblo/02,640.99,yes,locked 2006.224.08:18:03.94/vblo/03,656.99,yes,locked 2006.224.08:18:03.94/vblo/04,712.99,yes,locked 2006.224.08:18:03.94/vblo/05,744.99,yes,locked 2006.224.08:18:03.94/vblo/06,752.99,yes,locked 2006.224.08:18:03.94/vblo/07,734.99,yes,locked 2006.224.08:18:03.94/vblo/08,744.99,yes,locked 2006.224.08:18:04.09/vabw/8 2006.224.08:18:04.24/vbbw/8 2006.224.08:18:04.33/xfe/off,on,15.2 2006.224.08:18:04.70/ifatt/23,28,28,28 2006.224.08:18:05.07/fmout-gps/S +4.54E-07 2006.224.08:18:05.12:!2006.224.08:19:00 2006.224.08:19:00.02:data_valid=off 2006.224.08:19:00.02:postob 2006.224.08:19:00.21/cable/+6.4354E-03 2006.224.08:19:00.22/wx/23.81,1004.6,100 2006.224.08:19:01.07/fmout-gps/S +4.51E-07 2006.224.08:19:01.08:scan_name=224-0820,k06224,60 2006.224.08:19:01.08:source=3c418,203837.03,511912.7,2000.0,cw 2006.224.08:19:02.14#flagr#flagr/antenna,new-source 2006.224.08:19:02.14:checkk5 2006.224.08:19:02.51/chk_autoobs//k5ts1/ autoobs is running! 2006.224.08:19:02.88/chk_autoobs//k5ts2/ autoobs is running! 2006.224.08:19:03.25/chk_autoobs//k5ts3/ autoobs is running! 2006.224.08:19:03.63/chk_autoobs//k5ts4/ autoobs is running! 2006.224.08:19:04.00/chk_obsdata//k5ts1/T2240818??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.08:19:04.37/chk_obsdata//k5ts2/T2240818??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.08:19:04.74/chk_obsdata//k5ts3/T2240818??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.08:19:05.10/chk_obsdata//k5ts4/T2240818??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.08:19:05.80/k5log//k5ts1_log_newline 2006.224.08:19:06.48/k5log//k5ts2_log_newline 2006.224.08:19:07.17/k5log//k5ts3_log_newline 2006.224.08:19:07.85/k5log//k5ts4_log_newline 2006.224.08:19:07.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.224.08:19:07.87:4f8m12a=3 2006.224.08:19:07.87$4f8m12a/echo=on 2006.224.08:19:07.87$4f8m12a/pcalon 2006.224.08:19:07.87$pcalon/"no phase cal control is implemented here 2006.224.08:19:07.87$4f8m12a/"tpicd=stop 2006.224.08:19:07.87$4f8m12a/vc4f8 2006.224.08:19:07.87$vc4f8/valo=1,532.99 2006.224.08:19:07.88#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.224.08:19:07.88#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.224.08:19:07.88#ibcon#ireg 17 cls_cnt 0 2006.224.08:19:07.88#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.224.08:19:07.88#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.224.08:19:07.88#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.224.08:19:07.88#ibcon#enter wrdev, iclass 21, count 0 2006.224.08:19:07.88#ibcon#first serial, iclass 21, count 0 2006.224.08:19:07.88#ibcon#enter sib2, iclass 21, count 0 2006.224.08:19:07.88#ibcon#flushed, iclass 21, count 0 2006.224.08:19:07.88#ibcon#about to write, iclass 21, count 0 2006.224.08:19:07.88#ibcon#wrote, iclass 21, count 0 2006.224.08:19:07.88#ibcon#about to read 3, iclass 21, count 0 2006.224.08:19:07.92#ibcon#read 3, iclass 21, count 0 2006.224.08:19:07.92#ibcon#about to read 4, iclass 21, count 0 2006.224.08:19:07.92#ibcon#read 4, iclass 21, count 0 2006.224.08:19:07.92#ibcon#about to read 5, iclass 21, count 0 2006.224.08:19:07.92#ibcon#read 5, iclass 21, count 0 2006.224.08:19:07.92#ibcon#about to read 6, iclass 21, count 0 2006.224.08:19:07.92#ibcon#read 6, iclass 21, count 0 2006.224.08:19:07.92#ibcon#end of sib2, iclass 21, count 0 2006.224.08:19:07.92#ibcon#*mode == 0, iclass 21, count 0 2006.224.08:19:07.92#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.224.08:19:07.92#ibcon#[26=FRQ=01,532.99\r\n] 2006.224.08:19:07.92#ibcon#*before write, iclass 21, count 0 2006.224.08:19:07.92#ibcon#enter sib2, iclass 21, count 0 2006.224.08:19:07.92#ibcon#flushed, iclass 21, count 0 2006.224.08:19:07.92#ibcon#about to write, iclass 21, count 0 2006.224.08:19:07.92#ibcon#wrote, iclass 21, count 0 2006.224.08:19:07.92#ibcon#about to read 3, iclass 21, count 0 2006.224.08:19:07.96#ibcon#read 3, iclass 21, count 0 2006.224.08:19:07.96#ibcon#about to read 4, iclass 21, count 0 2006.224.08:19:07.96#ibcon#read 4, iclass 21, count 0 2006.224.08:19:07.96#ibcon#about to read 5, iclass 21, count 0 2006.224.08:19:07.96#ibcon#read 5, iclass 21, count 0 2006.224.08:19:07.96#ibcon#about to read 6, iclass 21, count 0 2006.224.08:19:07.96#ibcon#read 6, iclass 21, count 0 2006.224.08:19:07.96#ibcon#end of sib2, iclass 21, count 0 2006.224.08:19:07.96#ibcon#*after write, iclass 21, count 0 2006.224.08:19:07.96#ibcon#*before return 0, iclass 21, count 0 2006.224.08:19:07.96#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.224.08:19:07.96#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.224.08:19:07.96#ibcon#about to clear, iclass 21 cls_cnt 0 2006.224.08:19:07.96#ibcon#cleared, iclass 21 cls_cnt 0 2006.224.08:19:07.97$vc4f8/va=1,8 2006.224.08:19:07.97#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.224.08:19:07.97#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.224.08:19:07.97#ibcon#ireg 11 cls_cnt 2 2006.224.08:19:07.97#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.224.08:19:07.97#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.224.08:19:07.97#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.224.08:19:07.97#ibcon#enter wrdev, iclass 23, count 2 2006.224.08:19:07.97#ibcon#first serial, iclass 23, count 2 2006.224.08:19:07.97#ibcon#enter sib2, iclass 23, count 2 2006.224.08:19:07.97#ibcon#flushed, iclass 23, count 2 2006.224.08:19:07.97#ibcon#about to write, iclass 23, count 2 2006.224.08:19:07.97#ibcon#wrote, iclass 23, count 2 2006.224.08:19:07.97#ibcon#about to read 3, iclass 23, count 2 2006.224.08:19:07.98#ibcon#read 3, iclass 23, count 2 2006.224.08:19:07.98#ibcon#about to read 4, iclass 23, count 2 2006.224.08:19:07.98#ibcon#read 4, iclass 23, count 2 2006.224.08:19:07.98#ibcon#about to read 5, iclass 23, count 2 2006.224.08:19:07.98#ibcon#read 5, iclass 23, count 2 2006.224.08:19:07.98#ibcon#about to read 6, iclass 23, count 2 2006.224.08:19:07.98#ibcon#read 6, iclass 23, count 2 2006.224.08:19:07.98#ibcon#end of sib2, iclass 23, count 2 2006.224.08:19:07.98#ibcon#*mode == 0, iclass 23, count 2 2006.224.08:19:07.98#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.224.08:19:07.98#ibcon#[25=AT01-08\r\n] 2006.224.08:19:07.98#ibcon#*before write, iclass 23, count 2 2006.224.08:19:07.98#ibcon#enter sib2, iclass 23, count 2 2006.224.08:19:07.98#ibcon#flushed, iclass 23, count 2 2006.224.08:19:07.98#ibcon#about to write, iclass 23, count 2 2006.224.08:19:07.98#ibcon#wrote, iclass 23, count 2 2006.224.08:19:07.98#ibcon#about to read 3, iclass 23, count 2 2006.224.08:19:08.02#ibcon#read 3, iclass 23, count 2 2006.224.08:19:08.02#ibcon#about to read 4, iclass 23, count 2 2006.224.08:19:08.02#ibcon#read 4, iclass 23, count 2 2006.224.08:19:08.02#ibcon#about to read 5, iclass 23, count 2 2006.224.08:19:08.02#ibcon#read 5, iclass 23, count 2 2006.224.08:19:08.02#ibcon#about to read 6, iclass 23, count 2 2006.224.08:19:08.02#ibcon#read 6, iclass 23, count 2 2006.224.08:19:08.02#ibcon#end of sib2, iclass 23, count 2 2006.224.08:19:08.02#ibcon#*after write, iclass 23, count 2 2006.224.08:19:08.02#ibcon#*before return 0, iclass 23, count 2 2006.224.08:19:08.02#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.224.08:19:08.02#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.224.08:19:08.02#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.224.08:19:08.02#ibcon#ireg 7 cls_cnt 0 2006.224.08:19:08.02#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.224.08:19:08.13#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.224.08:19:08.13#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.224.08:19:08.13#ibcon#enter wrdev, iclass 23, count 0 2006.224.08:19:08.13#ibcon#first serial, iclass 23, count 0 2006.224.08:19:08.13#ibcon#enter sib2, iclass 23, count 0 2006.224.08:19:08.13#ibcon#flushed, iclass 23, count 0 2006.224.08:19:08.13#ibcon#about to write, iclass 23, count 0 2006.224.08:19:08.13#ibcon#wrote, iclass 23, count 0 2006.224.08:19:08.13#ibcon#about to read 3, iclass 23, count 0 2006.224.08:19:08.15#ibcon#read 3, iclass 23, count 0 2006.224.08:19:08.15#ibcon#about to read 4, iclass 23, count 0 2006.224.08:19:08.15#ibcon#read 4, iclass 23, count 0 2006.224.08:19:08.15#ibcon#about to read 5, iclass 23, count 0 2006.224.08:19:08.15#ibcon#read 5, iclass 23, count 0 2006.224.08:19:08.15#ibcon#about to read 6, iclass 23, count 0 2006.224.08:19:08.15#ibcon#read 6, iclass 23, count 0 2006.224.08:19:08.15#ibcon#end of sib2, iclass 23, count 0 2006.224.08:19:08.15#ibcon#*mode == 0, iclass 23, count 0 2006.224.08:19:08.15#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.224.08:19:08.15#ibcon#[25=USB\r\n] 2006.224.08:19:08.15#ibcon#*before write, iclass 23, count 0 2006.224.08:19:08.15#ibcon#enter sib2, iclass 23, count 0 2006.224.08:19:08.15#ibcon#flushed, iclass 23, count 0 2006.224.08:19:08.15#ibcon#about to write, iclass 23, count 0 2006.224.08:19:08.15#ibcon#wrote, iclass 23, count 0 2006.224.08:19:08.15#ibcon#about to read 3, iclass 23, count 0 2006.224.08:19:08.18#ibcon#read 3, iclass 23, count 0 2006.224.08:19:08.18#ibcon#about to read 4, iclass 23, count 0 2006.224.08:19:08.18#ibcon#read 4, iclass 23, count 0 2006.224.08:19:08.18#ibcon#about to read 5, iclass 23, count 0 2006.224.08:19:08.18#ibcon#read 5, iclass 23, count 0 2006.224.08:19:08.18#ibcon#about to read 6, iclass 23, count 0 2006.224.08:19:08.18#ibcon#read 6, iclass 23, count 0 2006.224.08:19:08.18#ibcon#end of sib2, iclass 23, count 0 2006.224.08:19:08.18#ibcon#*after write, iclass 23, count 0 2006.224.08:19:08.18#ibcon#*before return 0, iclass 23, count 0 2006.224.08:19:08.18#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.224.08:19:08.18#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.224.08:19:08.18#ibcon#about to clear, iclass 23 cls_cnt 0 2006.224.08:19:08.18#ibcon#cleared, iclass 23 cls_cnt 0 2006.224.08:19:08.19$vc4f8/valo=2,572.99 2006.224.08:19:08.19#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.224.08:19:08.19#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.224.08:19:08.19#ibcon#ireg 17 cls_cnt 0 2006.224.08:19:08.19#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.224.08:19:08.19#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.224.08:19:08.19#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.224.08:19:08.19#ibcon#enter wrdev, iclass 25, count 0 2006.224.08:19:08.19#ibcon#first serial, iclass 25, count 0 2006.224.08:19:08.19#ibcon#enter sib2, iclass 25, count 0 2006.224.08:19:08.19#ibcon#flushed, iclass 25, count 0 2006.224.08:19:08.19#ibcon#about to write, iclass 25, count 0 2006.224.08:19:08.19#ibcon#wrote, iclass 25, count 0 2006.224.08:19:08.19#ibcon#about to read 3, iclass 25, count 0 2006.224.08:19:08.20#ibcon#read 3, iclass 25, count 0 2006.224.08:19:08.20#ibcon#about to read 4, iclass 25, count 0 2006.224.08:19:08.20#ibcon#read 4, iclass 25, count 0 2006.224.08:19:08.20#ibcon#about to read 5, iclass 25, count 0 2006.224.08:19:08.20#ibcon#read 5, iclass 25, count 0 2006.224.08:19:08.20#ibcon#about to read 6, iclass 25, count 0 2006.224.08:19:08.20#ibcon#read 6, iclass 25, count 0 2006.224.08:19:08.20#ibcon#end of sib2, iclass 25, count 0 2006.224.08:19:08.20#ibcon#*mode == 0, iclass 25, count 0 2006.224.08:19:08.20#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.224.08:19:08.20#ibcon#[26=FRQ=02,572.99\r\n] 2006.224.08:19:08.20#ibcon#*before write, iclass 25, count 0 2006.224.08:19:08.20#ibcon#enter sib2, iclass 25, count 0 2006.224.08:19:08.20#ibcon#flushed, iclass 25, count 0 2006.224.08:19:08.20#ibcon#about to write, iclass 25, count 0 2006.224.08:19:08.20#ibcon#wrote, iclass 25, count 0 2006.224.08:19:08.20#ibcon#about to read 3, iclass 25, count 0 2006.224.08:19:08.24#ibcon#read 3, iclass 25, count 0 2006.224.08:19:08.24#ibcon#about to read 4, iclass 25, count 0 2006.224.08:19:08.24#ibcon#read 4, iclass 25, count 0 2006.224.08:19:08.24#ibcon#about to read 5, iclass 25, count 0 2006.224.08:19:08.24#ibcon#read 5, iclass 25, count 0 2006.224.08:19:08.24#ibcon#about to read 6, iclass 25, count 0 2006.224.08:19:08.24#ibcon#read 6, iclass 25, count 0 2006.224.08:19:08.24#ibcon#end of sib2, iclass 25, count 0 2006.224.08:19:08.24#ibcon#*after write, iclass 25, count 0 2006.224.08:19:08.24#ibcon#*before return 0, iclass 25, count 0 2006.224.08:19:08.24#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.224.08:19:08.24#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.224.08:19:08.24#ibcon#about to clear, iclass 25 cls_cnt 0 2006.224.08:19:08.24#ibcon#cleared, iclass 25 cls_cnt 0 2006.224.08:19:08.25$vc4f8/va=2,7 2006.224.08:19:08.25#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.224.08:19:08.25#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.224.08:19:08.25#ibcon#ireg 11 cls_cnt 2 2006.224.08:19:08.25#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.224.08:19:08.30#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.224.08:19:08.30#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.224.08:19:08.30#ibcon#enter wrdev, iclass 27, count 2 2006.224.08:19:08.30#ibcon#first serial, iclass 27, count 2 2006.224.08:19:08.30#ibcon#enter sib2, iclass 27, count 2 2006.224.08:19:08.30#ibcon#flushed, iclass 27, count 2 2006.224.08:19:08.30#ibcon#about to write, iclass 27, count 2 2006.224.08:19:08.30#ibcon#wrote, iclass 27, count 2 2006.224.08:19:08.30#ibcon#about to read 3, iclass 27, count 2 2006.224.08:19:08.31#ibcon#read 3, iclass 27, count 2 2006.224.08:19:08.31#ibcon#about to read 4, iclass 27, count 2 2006.224.08:19:08.31#ibcon#read 4, iclass 27, count 2 2006.224.08:19:08.31#ibcon#about to read 5, iclass 27, count 2 2006.224.08:19:08.31#ibcon#read 5, iclass 27, count 2 2006.224.08:19:08.31#ibcon#about to read 6, iclass 27, count 2 2006.224.08:19:08.31#ibcon#read 6, iclass 27, count 2 2006.224.08:19:08.31#ibcon#end of sib2, iclass 27, count 2 2006.224.08:19:08.31#ibcon#*mode == 0, iclass 27, count 2 2006.224.08:19:08.31#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.224.08:19:08.31#ibcon#[25=AT02-07\r\n] 2006.224.08:19:08.31#ibcon#*before write, iclass 27, count 2 2006.224.08:19:08.31#ibcon#enter sib2, iclass 27, count 2 2006.224.08:19:08.31#ibcon#flushed, iclass 27, count 2 2006.224.08:19:08.31#ibcon#about to write, iclass 27, count 2 2006.224.08:19:08.31#ibcon#wrote, iclass 27, count 2 2006.224.08:19:08.31#ibcon#about to read 3, iclass 27, count 2 2006.224.08:19:08.34#ibcon#read 3, iclass 27, count 2 2006.224.08:19:08.34#ibcon#about to read 4, iclass 27, count 2 2006.224.08:19:08.34#ibcon#read 4, iclass 27, count 2 2006.224.08:19:08.34#ibcon#about to read 5, iclass 27, count 2 2006.224.08:19:08.34#ibcon#read 5, iclass 27, count 2 2006.224.08:19:08.34#ibcon#about to read 6, iclass 27, count 2 2006.224.08:19:08.34#ibcon#read 6, iclass 27, count 2 2006.224.08:19:08.34#ibcon#end of sib2, iclass 27, count 2 2006.224.08:19:08.34#ibcon#*after write, iclass 27, count 2 2006.224.08:19:08.34#ibcon#*before return 0, iclass 27, count 2 2006.224.08:19:08.34#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.224.08:19:08.34#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.224.08:19:08.34#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.224.08:19:08.34#ibcon#ireg 7 cls_cnt 0 2006.224.08:19:08.34#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.224.08:19:08.46#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.224.08:19:08.46#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.224.08:19:08.46#ibcon#enter wrdev, iclass 27, count 0 2006.224.08:19:08.46#ibcon#first serial, iclass 27, count 0 2006.224.08:19:08.46#ibcon#enter sib2, iclass 27, count 0 2006.224.08:19:08.46#ibcon#flushed, iclass 27, count 0 2006.224.08:19:08.46#ibcon#about to write, iclass 27, count 0 2006.224.08:19:08.46#ibcon#wrote, iclass 27, count 0 2006.224.08:19:08.46#ibcon#about to read 3, iclass 27, count 0 2006.224.08:19:08.48#ibcon#read 3, iclass 27, count 0 2006.224.08:19:08.48#ibcon#about to read 4, iclass 27, count 0 2006.224.08:19:08.48#ibcon#read 4, iclass 27, count 0 2006.224.08:19:08.48#ibcon#about to read 5, iclass 27, count 0 2006.224.08:19:08.48#ibcon#read 5, iclass 27, count 0 2006.224.08:19:08.48#ibcon#about to read 6, iclass 27, count 0 2006.224.08:19:08.48#ibcon#read 6, iclass 27, count 0 2006.224.08:19:08.48#ibcon#end of sib2, iclass 27, count 0 2006.224.08:19:08.48#ibcon#*mode == 0, iclass 27, count 0 2006.224.08:19:08.48#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.224.08:19:08.48#ibcon#[25=USB\r\n] 2006.224.08:19:08.48#ibcon#*before write, iclass 27, count 0 2006.224.08:19:08.48#ibcon#enter sib2, iclass 27, count 0 2006.224.08:19:08.48#ibcon#flushed, iclass 27, count 0 2006.224.08:19:08.48#ibcon#about to write, iclass 27, count 0 2006.224.08:19:08.48#ibcon#wrote, iclass 27, count 0 2006.224.08:19:08.48#ibcon#about to read 3, iclass 27, count 0 2006.224.08:19:08.51#ibcon#read 3, iclass 27, count 0 2006.224.08:19:08.51#ibcon#about to read 4, iclass 27, count 0 2006.224.08:19:08.51#ibcon#read 4, iclass 27, count 0 2006.224.08:19:08.51#ibcon#about to read 5, iclass 27, count 0 2006.224.08:19:08.51#ibcon#read 5, iclass 27, count 0 2006.224.08:19:08.51#ibcon#about to read 6, iclass 27, count 0 2006.224.08:19:08.51#ibcon#read 6, iclass 27, count 0 2006.224.08:19:08.51#ibcon#end of sib2, iclass 27, count 0 2006.224.08:19:08.51#ibcon#*after write, iclass 27, count 0 2006.224.08:19:08.51#ibcon#*before return 0, iclass 27, count 0 2006.224.08:19:08.51#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.224.08:19:08.51#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.224.08:19:08.51#ibcon#about to clear, iclass 27 cls_cnt 0 2006.224.08:19:08.51#ibcon#cleared, iclass 27 cls_cnt 0 2006.224.08:19:08.52$vc4f8/valo=3,672.99 2006.224.08:19:08.52#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.224.08:19:08.52#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.224.08:19:08.52#ibcon#ireg 17 cls_cnt 0 2006.224.08:19:08.52#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.224.08:19:08.52#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.224.08:19:08.52#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.224.08:19:08.52#ibcon#enter wrdev, iclass 29, count 0 2006.224.08:19:08.52#ibcon#first serial, iclass 29, count 0 2006.224.08:19:08.52#ibcon#enter sib2, iclass 29, count 0 2006.224.08:19:08.52#ibcon#flushed, iclass 29, count 0 2006.224.08:19:08.52#ibcon#about to write, iclass 29, count 0 2006.224.08:19:08.52#ibcon#wrote, iclass 29, count 0 2006.224.08:19:08.52#ibcon#about to read 3, iclass 29, count 0 2006.224.08:19:08.53#ibcon#read 3, iclass 29, count 0 2006.224.08:19:08.53#ibcon#about to read 4, iclass 29, count 0 2006.224.08:19:08.53#ibcon#read 4, iclass 29, count 0 2006.224.08:19:08.53#ibcon#about to read 5, iclass 29, count 0 2006.224.08:19:08.53#ibcon#read 5, iclass 29, count 0 2006.224.08:19:08.53#ibcon#about to read 6, iclass 29, count 0 2006.224.08:19:08.53#ibcon#read 6, iclass 29, count 0 2006.224.08:19:08.53#ibcon#end of sib2, iclass 29, count 0 2006.224.08:19:08.53#ibcon#*mode == 0, iclass 29, count 0 2006.224.08:19:08.53#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.224.08:19:08.53#ibcon#[26=FRQ=03,672.99\r\n] 2006.224.08:19:08.53#ibcon#*before write, iclass 29, count 0 2006.224.08:19:08.53#ibcon#enter sib2, iclass 29, count 0 2006.224.08:19:08.53#ibcon#flushed, iclass 29, count 0 2006.224.08:19:08.53#ibcon#about to write, iclass 29, count 0 2006.224.08:19:08.53#ibcon#wrote, iclass 29, count 0 2006.224.08:19:08.53#ibcon#about to read 3, iclass 29, count 0 2006.224.08:19:08.57#ibcon#read 3, iclass 29, count 0 2006.224.08:19:08.57#ibcon#about to read 4, iclass 29, count 0 2006.224.08:19:08.57#ibcon#read 4, iclass 29, count 0 2006.224.08:19:08.57#ibcon#about to read 5, iclass 29, count 0 2006.224.08:19:08.57#ibcon#read 5, iclass 29, count 0 2006.224.08:19:08.57#ibcon#about to read 6, iclass 29, count 0 2006.224.08:19:08.57#ibcon#read 6, iclass 29, count 0 2006.224.08:19:08.57#ibcon#end of sib2, iclass 29, count 0 2006.224.08:19:08.57#ibcon#*after write, iclass 29, count 0 2006.224.08:19:08.57#ibcon#*before return 0, iclass 29, count 0 2006.224.08:19:08.57#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.224.08:19:08.57#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.224.08:19:08.57#ibcon#about to clear, iclass 29 cls_cnt 0 2006.224.08:19:08.57#ibcon#cleared, iclass 29 cls_cnt 0 2006.224.08:19:08.58$vc4f8/va=3,6 2006.224.08:19:08.58#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.224.08:19:08.58#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.224.08:19:08.58#ibcon#ireg 11 cls_cnt 2 2006.224.08:19:08.58#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.224.08:19:08.63#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.224.08:19:08.63#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.224.08:19:08.63#ibcon#enter wrdev, iclass 31, count 2 2006.224.08:19:08.63#ibcon#first serial, iclass 31, count 2 2006.224.08:19:08.63#ibcon#enter sib2, iclass 31, count 2 2006.224.08:19:08.63#ibcon#flushed, iclass 31, count 2 2006.224.08:19:08.63#ibcon#about to write, iclass 31, count 2 2006.224.08:19:08.63#ibcon#wrote, iclass 31, count 2 2006.224.08:19:08.63#ibcon#about to read 3, iclass 31, count 2 2006.224.08:19:08.64#ibcon#read 3, iclass 31, count 2 2006.224.08:19:08.64#ibcon#about to read 4, iclass 31, count 2 2006.224.08:19:08.64#ibcon#read 4, iclass 31, count 2 2006.224.08:19:08.64#ibcon#about to read 5, iclass 31, count 2 2006.224.08:19:08.64#ibcon#read 5, iclass 31, count 2 2006.224.08:19:08.64#ibcon#about to read 6, iclass 31, count 2 2006.224.08:19:08.64#ibcon#read 6, iclass 31, count 2 2006.224.08:19:08.64#ibcon#end of sib2, iclass 31, count 2 2006.224.08:19:08.64#ibcon#*mode == 0, iclass 31, count 2 2006.224.08:19:08.64#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.224.08:19:08.64#ibcon#[25=AT03-06\r\n] 2006.224.08:19:08.64#ibcon#*before write, iclass 31, count 2 2006.224.08:19:08.64#ibcon#enter sib2, iclass 31, count 2 2006.224.08:19:08.64#ibcon#flushed, iclass 31, count 2 2006.224.08:19:08.64#ibcon#about to write, iclass 31, count 2 2006.224.08:19:08.64#ibcon#wrote, iclass 31, count 2 2006.224.08:19:08.64#ibcon#about to read 3, iclass 31, count 2 2006.224.08:19:08.67#ibcon#read 3, iclass 31, count 2 2006.224.08:19:08.67#ibcon#about to read 4, iclass 31, count 2 2006.224.08:19:08.67#ibcon#read 4, iclass 31, count 2 2006.224.08:19:08.67#ibcon#about to read 5, iclass 31, count 2 2006.224.08:19:08.67#ibcon#read 5, iclass 31, count 2 2006.224.08:19:08.67#ibcon#about to read 6, iclass 31, count 2 2006.224.08:19:08.67#ibcon#read 6, iclass 31, count 2 2006.224.08:19:08.67#ibcon#end of sib2, iclass 31, count 2 2006.224.08:19:08.67#ibcon#*after write, iclass 31, count 2 2006.224.08:19:08.67#ibcon#*before return 0, iclass 31, count 2 2006.224.08:19:08.67#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.224.08:19:08.67#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.224.08:19:08.67#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.224.08:19:08.67#ibcon#ireg 7 cls_cnt 0 2006.224.08:19:08.67#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.224.08:19:08.79#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.224.08:19:08.79#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.224.08:19:08.79#ibcon#enter wrdev, iclass 31, count 0 2006.224.08:19:08.79#ibcon#first serial, iclass 31, count 0 2006.224.08:19:08.79#ibcon#enter sib2, iclass 31, count 0 2006.224.08:19:08.79#ibcon#flushed, iclass 31, count 0 2006.224.08:19:08.79#ibcon#about to write, iclass 31, count 0 2006.224.08:19:08.79#ibcon#wrote, iclass 31, count 0 2006.224.08:19:08.79#ibcon#about to read 3, iclass 31, count 0 2006.224.08:19:08.81#ibcon#read 3, iclass 31, count 0 2006.224.08:19:08.81#ibcon#about to read 4, iclass 31, count 0 2006.224.08:19:08.81#ibcon#read 4, iclass 31, count 0 2006.224.08:19:08.81#ibcon#about to read 5, iclass 31, count 0 2006.224.08:19:08.81#ibcon#read 5, iclass 31, count 0 2006.224.08:19:08.81#ibcon#about to read 6, iclass 31, count 0 2006.224.08:19:08.81#ibcon#read 6, iclass 31, count 0 2006.224.08:19:08.81#ibcon#end of sib2, iclass 31, count 0 2006.224.08:19:08.81#ibcon#*mode == 0, iclass 31, count 0 2006.224.08:19:08.81#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.224.08:19:08.81#ibcon#[25=USB\r\n] 2006.224.08:19:08.81#ibcon#*before write, iclass 31, count 0 2006.224.08:19:08.81#ibcon#enter sib2, iclass 31, count 0 2006.224.08:19:08.81#ibcon#flushed, iclass 31, count 0 2006.224.08:19:08.81#ibcon#about to write, iclass 31, count 0 2006.224.08:19:08.81#ibcon#wrote, iclass 31, count 0 2006.224.08:19:08.81#ibcon#about to read 3, iclass 31, count 0 2006.224.08:19:08.84#ibcon#read 3, iclass 31, count 0 2006.224.08:19:08.84#ibcon#about to read 4, iclass 31, count 0 2006.224.08:19:08.84#ibcon#read 4, iclass 31, count 0 2006.224.08:19:08.84#ibcon#about to read 5, iclass 31, count 0 2006.224.08:19:08.84#ibcon#read 5, iclass 31, count 0 2006.224.08:19:08.84#ibcon#about to read 6, iclass 31, count 0 2006.224.08:19:08.84#ibcon#read 6, iclass 31, count 0 2006.224.08:19:08.84#ibcon#end of sib2, iclass 31, count 0 2006.224.08:19:08.84#ibcon#*after write, iclass 31, count 0 2006.224.08:19:08.84#ibcon#*before return 0, iclass 31, count 0 2006.224.08:19:08.84#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.224.08:19:08.84#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.224.08:19:08.84#ibcon#about to clear, iclass 31 cls_cnt 0 2006.224.08:19:08.84#ibcon#cleared, iclass 31 cls_cnt 0 2006.224.08:19:08.85$vc4f8/valo=4,832.99 2006.224.08:19:08.85#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.224.08:19:08.85#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.224.08:19:08.85#ibcon#ireg 17 cls_cnt 0 2006.224.08:19:08.85#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.224.08:19:08.85#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.224.08:19:08.85#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.224.08:19:08.85#ibcon#enter wrdev, iclass 33, count 0 2006.224.08:19:08.85#ibcon#first serial, iclass 33, count 0 2006.224.08:19:08.85#ibcon#enter sib2, iclass 33, count 0 2006.224.08:19:08.85#ibcon#flushed, iclass 33, count 0 2006.224.08:19:08.85#ibcon#about to write, iclass 33, count 0 2006.224.08:19:08.85#ibcon#wrote, iclass 33, count 0 2006.224.08:19:08.85#ibcon#about to read 3, iclass 33, count 0 2006.224.08:19:08.86#ibcon#read 3, iclass 33, count 0 2006.224.08:19:08.86#ibcon#about to read 4, iclass 33, count 0 2006.224.08:19:08.86#ibcon#read 4, iclass 33, count 0 2006.224.08:19:08.86#ibcon#about to read 5, iclass 33, count 0 2006.224.08:19:08.86#ibcon#read 5, iclass 33, count 0 2006.224.08:19:08.86#ibcon#about to read 6, iclass 33, count 0 2006.224.08:19:08.86#ibcon#read 6, iclass 33, count 0 2006.224.08:19:08.86#ibcon#end of sib2, iclass 33, count 0 2006.224.08:19:08.86#ibcon#*mode == 0, iclass 33, count 0 2006.224.08:19:08.86#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.224.08:19:08.86#ibcon#[26=FRQ=04,832.99\r\n] 2006.224.08:19:08.86#ibcon#*before write, iclass 33, count 0 2006.224.08:19:08.86#ibcon#enter sib2, iclass 33, count 0 2006.224.08:19:08.86#ibcon#flushed, iclass 33, count 0 2006.224.08:19:08.86#ibcon#about to write, iclass 33, count 0 2006.224.08:19:08.86#ibcon#wrote, iclass 33, count 0 2006.224.08:19:08.86#ibcon#about to read 3, iclass 33, count 0 2006.224.08:19:08.90#ibcon#read 3, iclass 33, count 0 2006.224.08:19:08.90#ibcon#about to read 4, iclass 33, count 0 2006.224.08:19:08.90#ibcon#read 4, iclass 33, count 0 2006.224.08:19:08.90#ibcon#about to read 5, iclass 33, count 0 2006.224.08:19:08.90#ibcon#read 5, iclass 33, count 0 2006.224.08:19:08.90#ibcon#about to read 6, iclass 33, count 0 2006.224.08:19:08.90#ibcon#read 6, iclass 33, count 0 2006.224.08:19:08.90#ibcon#end of sib2, iclass 33, count 0 2006.224.08:19:08.90#ibcon#*after write, iclass 33, count 0 2006.224.08:19:08.90#ibcon#*before return 0, iclass 33, count 0 2006.224.08:19:08.90#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.224.08:19:08.90#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.224.08:19:08.90#ibcon#about to clear, iclass 33 cls_cnt 0 2006.224.08:19:08.90#ibcon#cleared, iclass 33 cls_cnt 0 2006.224.08:19:08.91$vc4f8/va=4,7 2006.224.08:19:08.91#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.224.08:19:08.91#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.224.08:19:08.91#ibcon#ireg 11 cls_cnt 2 2006.224.08:19:08.91#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.224.08:19:08.96#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.224.08:19:08.96#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.224.08:19:08.96#ibcon#enter wrdev, iclass 35, count 2 2006.224.08:19:08.96#ibcon#first serial, iclass 35, count 2 2006.224.08:19:08.96#ibcon#enter sib2, iclass 35, count 2 2006.224.08:19:08.96#ibcon#flushed, iclass 35, count 2 2006.224.08:19:08.96#ibcon#about to write, iclass 35, count 2 2006.224.08:19:08.96#ibcon#wrote, iclass 35, count 2 2006.224.08:19:08.96#ibcon#about to read 3, iclass 35, count 2 2006.224.08:19:08.97#ibcon#read 3, iclass 35, count 2 2006.224.08:19:08.97#ibcon#about to read 4, iclass 35, count 2 2006.224.08:19:08.97#ibcon#read 4, iclass 35, count 2 2006.224.08:19:08.97#ibcon#about to read 5, iclass 35, count 2 2006.224.08:19:08.97#ibcon#read 5, iclass 35, count 2 2006.224.08:19:08.97#ibcon#about to read 6, iclass 35, count 2 2006.224.08:19:08.97#ibcon#read 6, iclass 35, count 2 2006.224.08:19:08.97#ibcon#end of sib2, iclass 35, count 2 2006.224.08:19:08.97#ibcon#*mode == 0, iclass 35, count 2 2006.224.08:19:08.97#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.224.08:19:08.97#ibcon#[25=AT04-07\r\n] 2006.224.08:19:08.97#ibcon#*before write, iclass 35, count 2 2006.224.08:19:08.97#ibcon#enter sib2, iclass 35, count 2 2006.224.08:19:08.97#ibcon#flushed, iclass 35, count 2 2006.224.08:19:08.97#ibcon#about to write, iclass 35, count 2 2006.224.08:19:08.97#ibcon#wrote, iclass 35, count 2 2006.224.08:19:08.97#ibcon#about to read 3, iclass 35, count 2 2006.224.08:19:09.00#ibcon#read 3, iclass 35, count 2 2006.224.08:19:09.00#ibcon#about to read 4, iclass 35, count 2 2006.224.08:19:09.00#ibcon#read 4, iclass 35, count 2 2006.224.08:19:09.00#ibcon#about to read 5, iclass 35, count 2 2006.224.08:19:09.00#ibcon#read 5, iclass 35, count 2 2006.224.08:19:09.00#ibcon#about to read 6, iclass 35, count 2 2006.224.08:19:09.00#ibcon#read 6, iclass 35, count 2 2006.224.08:19:09.00#ibcon#end of sib2, iclass 35, count 2 2006.224.08:19:09.00#ibcon#*after write, iclass 35, count 2 2006.224.08:19:09.00#ibcon#*before return 0, iclass 35, count 2 2006.224.08:19:09.00#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.224.08:19:09.00#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.224.08:19:09.00#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.224.08:19:09.00#ibcon#ireg 7 cls_cnt 0 2006.224.08:19:09.00#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.224.08:19:09.12#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.224.08:19:09.12#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.224.08:19:09.12#ibcon#enter wrdev, iclass 35, count 0 2006.224.08:19:09.12#ibcon#first serial, iclass 35, count 0 2006.224.08:19:09.12#ibcon#enter sib2, iclass 35, count 0 2006.224.08:19:09.12#ibcon#flushed, iclass 35, count 0 2006.224.08:19:09.12#ibcon#about to write, iclass 35, count 0 2006.224.08:19:09.12#ibcon#wrote, iclass 35, count 0 2006.224.08:19:09.12#ibcon#about to read 3, iclass 35, count 0 2006.224.08:19:09.14#ibcon#read 3, iclass 35, count 0 2006.224.08:19:09.14#ibcon#about to read 4, iclass 35, count 0 2006.224.08:19:09.14#ibcon#read 4, iclass 35, count 0 2006.224.08:19:09.14#ibcon#about to read 5, iclass 35, count 0 2006.224.08:19:09.14#ibcon#read 5, iclass 35, count 0 2006.224.08:19:09.14#ibcon#about to read 6, iclass 35, count 0 2006.224.08:19:09.14#ibcon#read 6, iclass 35, count 0 2006.224.08:19:09.14#ibcon#end of sib2, iclass 35, count 0 2006.224.08:19:09.14#ibcon#*mode == 0, iclass 35, count 0 2006.224.08:19:09.14#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.224.08:19:09.14#ibcon#[25=USB\r\n] 2006.224.08:19:09.14#ibcon#*before write, iclass 35, count 0 2006.224.08:19:09.14#ibcon#enter sib2, iclass 35, count 0 2006.224.08:19:09.14#ibcon#flushed, iclass 35, count 0 2006.224.08:19:09.14#ibcon#about to write, iclass 35, count 0 2006.224.08:19:09.14#ibcon#wrote, iclass 35, count 0 2006.224.08:19:09.14#ibcon#about to read 3, iclass 35, count 0 2006.224.08:19:09.17#ibcon#read 3, iclass 35, count 0 2006.224.08:19:09.17#ibcon#about to read 4, iclass 35, count 0 2006.224.08:19:09.17#ibcon#read 4, iclass 35, count 0 2006.224.08:19:09.17#ibcon#about to read 5, iclass 35, count 0 2006.224.08:19:09.17#ibcon#read 5, iclass 35, count 0 2006.224.08:19:09.17#ibcon#about to read 6, iclass 35, count 0 2006.224.08:19:09.17#ibcon#read 6, iclass 35, count 0 2006.224.08:19:09.17#ibcon#end of sib2, iclass 35, count 0 2006.224.08:19:09.17#ibcon#*after write, iclass 35, count 0 2006.224.08:19:09.17#ibcon#*before return 0, iclass 35, count 0 2006.224.08:19:09.17#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.224.08:19:09.17#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.224.08:19:09.17#ibcon#about to clear, iclass 35 cls_cnt 0 2006.224.08:19:09.17#ibcon#cleared, iclass 35 cls_cnt 0 2006.224.08:19:09.18$vc4f8/valo=5,652.99 2006.224.08:19:09.18#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.224.08:19:09.18#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.224.08:19:09.18#ibcon#ireg 17 cls_cnt 0 2006.224.08:19:09.18#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.224.08:19:09.18#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.224.08:19:09.18#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.224.08:19:09.18#ibcon#enter wrdev, iclass 37, count 0 2006.224.08:19:09.18#ibcon#first serial, iclass 37, count 0 2006.224.08:19:09.18#ibcon#enter sib2, iclass 37, count 0 2006.224.08:19:09.18#ibcon#flushed, iclass 37, count 0 2006.224.08:19:09.18#ibcon#about to write, iclass 37, count 0 2006.224.08:19:09.18#ibcon#wrote, iclass 37, count 0 2006.224.08:19:09.18#ibcon#about to read 3, iclass 37, count 0 2006.224.08:19:09.19#ibcon#read 3, iclass 37, count 0 2006.224.08:19:09.19#ibcon#about to read 4, iclass 37, count 0 2006.224.08:19:09.19#ibcon#read 4, iclass 37, count 0 2006.224.08:19:09.19#ibcon#about to read 5, iclass 37, count 0 2006.224.08:19:09.19#ibcon#read 5, iclass 37, count 0 2006.224.08:19:09.19#ibcon#about to read 6, iclass 37, count 0 2006.224.08:19:09.19#ibcon#read 6, iclass 37, count 0 2006.224.08:19:09.19#ibcon#end of sib2, iclass 37, count 0 2006.224.08:19:09.19#ibcon#*mode == 0, iclass 37, count 0 2006.224.08:19:09.19#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.224.08:19:09.19#ibcon#[26=FRQ=05,652.99\r\n] 2006.224.08:19:09.19#ibcon#*before write, iclass 37, count 0 2006.224.08:19:09.19#ibcon#enter sib2, iclass 37, count 0 2006.224.08:19:09.19#ibcon#flushed, iclass 37, count 0 2006.224.08:19:09.19#ibcon#about to write, iclass 37, count 0 2006.224.08:19:09.19#ibcon#wrote, iclass 37, count 0 2006.224.08:19:09.19#ibcon#about to read 3, iclass 37, count 0 2006.224.08:19:09.23#ibcon#read 3, iclass 37, count 0 2006.224.08:19:09.23#ibcon#about to read 4, iclass 37, count 0 2006.224.08:19:09.23#ibcon#read 4, iclass 37, count 0 2006.224.08:19:09.23#ibcon#about to read 5, iclass 37, count 0 2006.224.08:19:09.23#ibcon#read 5, iclass 37, count 0 2006.224.08:19:09.23#ibcon#about to read 6, iclass 37, count 0 2006.224.08:19:09.23#ibcon#read 6, iclass 37, count 0 2006.224.08:19:09.23#ibcon#end of sib2, iclass 37, count 0 2006.224.08:19:09.23#ibcon#*after write, iclass 37, count 0 2006.224.08:19:09.23#ibcon#*before return 0, iclass 37, count 0 2006.224.08:19:09.23#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.224.08:19:09.23#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.224.08:19:09.23#ibcon#about to clear, iclass 37 cls_cnt 0 2006.224.08:19:09.23#ibcon#cleared, iclass 37 cls_cnt 0 2006.224.08:19:09.24$vc4f8/va=5,7 2006.224.08:19:09.24#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.224.08:19:09.24#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.224.08:19:09.24#ibcon#ireg 11 cls_cnt 2 2006.224.08:19:09.24#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.224.08:19:09.28#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.224.08:19:09.28#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.224.08:19:09.28#ibcon#enter wrdev, iclass 39, count 2 2006.224.08:19:09.28#ibcon#first serial, iclass 39, count 2 2006.224.08:19:09.28#ibcon#enter sib2, iclass 39, count 2 2006.224.08:19:09.28#ibcon#flushed, iclass 39, count 2 2006.224.08:19:09.28#ibcon#about to write, iclass 39, count 2 2006.224.08:19:09.28#ibcon#wrote, iclass 39, count 2 2006.224.08:19:09.28#ibcon#about to read 3, iclass 39, count 2 2006.224.08:19:09.30#ibcon#read 3, iclass 39, count 2 2006.224.08:19:09.30#ibcon#about to read 4, iclass 39, count 2 2006.224.08:19:09.30#ibcon#read 4, iclass 39, count 2 2006.224.08:19:09.30#ibcon#about to read 5, iclass 39, count 2 2006.224.08:19:09.30#ibcon#read 5, iclass 39, count 2 2006.224.08:19:09.30#ibcon#about to read 6, iclass 39, count 2 2006.224.08:19:09.30#ibcon#read 6, iclass 39, count 2 2006.224.08:19:09.30#ibcon#end of sib2, iclass 39, count 2 2006.224.08:19:09.30#ibcon#*mode == 0, iclass 39, count 2 2006.224.08:19:09.30#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.224.08:19:09.30#ibcon#[25=AT05-07\r\n] 2006.224.08:19:09.30#ibcon#*before write, iclass 39, count 2 2006.224.08:19:09.30#ibcon#enter sib2, iclass 39, count 2 2006.224.08:19:09.30#ibcon#flushed, iclass 39, count 2 2006.224.08:19:09.30#ibcon#about to write, iclass 39, count 2 2006.224.08:19:09.30#ibcon#wrote, iclass 39, count 2 2006.224.08:19:09.30#ibcon#about to read 3, iclass 39, count 2 2006.224.08:19:09.33#ibcon#read 3, iclass 39, count 2 2006.224.08:19:09.33#ibcon#about to read 4, iclass 39, count 2 2006.224.08:19:09.33#ibcon#read 4, iclass 39, count 2 2006.224.08:19:09.33#ibcon#about to read 5, iclass 39, count 2 2006.224.08:19:09.33#ibcon#read 5, iclass 39, count 2 2006.224.08:19:09.33#ibcon#about to read 6, iclass 39, count 2 2006.224.08:19:09.33#ibcon#read 6, iclass 39, count 2 2006.224.08:19:09.33#ibcon#end of sib2, iclass 39, count 2 2006.224.08:19:09.33#ibcon#*after write, iclass 39, count 2 2006.224.08:19:09.33#ibcon#*before return 0, iclass 39, count 2 2006.224.08:19:09.33#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.224.08:19:09.33#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.224.08:19:09.33#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.224.08:19:09.33#ibcon#ireg 7 cls_cnt 0 2006.224.08:19:09.33#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.224.08:19:09.45#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.224.08:19:09.45#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.224.08:19:09.45#ibcon#enter wrdev, iclass 39, count 0 2006.224.08:19:09.45#ibcon#first serial, iclass 39, count 0 2006.224.08:19:09.45#ibcon#enter sib2, iclass 39, count 0 2006.224.08:19:09.45#ibcon#flushed, iclass 39, count 0 2006.224.08:19:09.45#ibcon#about to write, iclass 39, count 0 2006.224.08:19:09.45#ibcon#wrote, iclass 39, count 0 2006.224.08:19:09.45#ibcon#about to read 3, iclass 39, count 0 2006.224.08:19:09.47#ibcon#read 3, iclass 39, count 0 2006.224.08:19:09.47#ibcon#about to read 4, iclass 39, count 0 2006.224.08:19:09.47#ibcon#read 4, iclass 39, count 0 2006.224.08:19:09.47#ibcon#about to read 5, iclass 39, count 0 2006.224.08:19:09.47#ibcon#read 5, iclass 39, count 0 2006.224.08:19:09.47#ibcon#about to read 6, iclass 39, count 0 2006.224.08:19:09.47#ibcon#read 6, iclass 39, count 0 2006.224.08:19:09.47#ibcon#end of sib2, iclass 39, count 0 2006.224.08:19:09.47#ibcon#*mode == 0, iclass 39, count 0 2006.224.08:19:09.47#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.224.08:19:09.47#ibcon#[25=USB\r\n] 2006.224.08:19:09.47#ibcon#*before write, iclass 39, count 0 2006.224.08:19:09.47#ibcon#enter sib2, iclass 39, count 0 2006.224.08:19:09.47#ibcon#flushed, iclass 39, count 0 2006.224.08:19:09.47#ibcon#about to write, iclass 39, count 0 2006.224.08:19:09.47#ibcon#wrote, iclass 39, count 0 2006.224.08:19:09.47#ibcon#about to read 3, iclass 39, count 0 2006.224.08:19:09.50#ibcon#read 3, iclass 39, count 0 2006.224.08:19:09.50#ibcon#about to read 4, iclass 39, count 0 2006.224.08:19:09.50#ibcon#read 4, iclass 39, count 0 2006.224.08:19:09.50#ibcon#about to read 5, iclass 39, count 0 2006.224.08:19:09.50#ibcon#read 5, iclass 39, count 0 2006.224.08:19:09.50#ibcon#about to read 6, iclass 39, count 0 2006.224.08:19:09.50#ibcon#read 6, iclass 39, count 0 2006.224.08:19:09.50#ibcon#end of sib2, iclass 39, count 0 2006.224.08:19:09.50#ibcon#*after write, iclass 39, count 0 2006.224.08:19:09.50#ibcon#*before return 0, iclass 39, count 0 2006.224.08:19:09.50#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.224.08:19:09.50#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.224.08:19:09.50#ibcon#about to clear, iclass 39 cls_cnt 0 2006.224.08:19:09.50#ibcon#cleared, iclass 39 cls_cnt 0 2006.224.08:19:09.51$vc4f8/valo=6,772.99 2006.224.08:19:09.51#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.224.08:19:09.51#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.224.08:19:09.51#ibcon#ireg 17 cls_cnt 0 2006.224.08:19:09.51#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.224.08:19:09.51#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.224.08:19:09.51#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.224.08:19:09.51#ibcon#enter wrdev, iclass 3, count 0 2006.224.08:19:09.51#ibcon#first serial, iclass 3, count 0 2006.224.08:19:09.51#ibcon#enter sib2, iclass 3, count 0 2006.224.08:19:09.51#ibcon#flushed, iclass 3, count 0 2006.224.08:19:09.51#ibcon#about to write, iclass 3, count 0 2006.224.08:19:09.51#ibcon#wrote, iclass 3, count 0 2006.224.08:19:09.51#ibcon#about to read 3, iclass 3, count 0 2006.224.08:19:09.52#ibcon#read 3, iclass 3, count 0 2006.224.08:19:09.52#ibcon#about to read 4, iclass 3, count 0 2006.224.08:19:09.52#ibcon#read 4, iclass 3, count 0 2006.224.08:19:09.52#ibcon#about to read 5, iclass 3, count 0 2006.224.08:19:09.52#ibcon#read 5, iclass 3, count 0 2006.224.08:19:09.52#ibcon#about to read 6, iclass 3, count 0 2006.224.08:19:09.52#ibcon#read 6, iclass 3, count 0 2006.224.08:19:09.52#ibcon#end of sib2, iclass 3, count 0 2006.224.08:19:09.52#ibcon#*mode == 0, iclass 3, count 0 2006.224.08:19:09.52#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.224.08:19:09.52#ibcon#[26=FRQ=06,772.99\r\n] 2006.224.08:19:09.52#ibcon#*before write, iclass 3, count 0 2006.224.08:19:09.52#ibcon#enter sib2, iclass 3, count 0 2006.224.08:19:09.52#ibcon#flushed, iclass 3, count 0 2006.224.08:19:09.52#ibcon#about to write, iclass 3, count 0 2006.224.08:19:09.52#ibcon#wrote, iclass 3, count 0 2006.224.08:19:09.52#ibcon#about to read 3, iclass 3, count 0 2006.224.08:19:09.56#ibcon#read 3, iclass 3, count 0 2006.224.08:19:09.56#ibcon#about to read 4, iclass 3, count 0 2006.224.08:19:09.56#ibcon#read 4, iclass 3, count 0 2006.224.08:19:09.56#ibcon#about to read 5, iclass 3, count 0 2006.224.08:19:09.56#ibcon#read 5, iclass 3, count 0 2006.224.08:19:09.56#ibcon#about to read 6, iclass 3, count 0 2006.224.08:19:09.56#ibcon#read 6, iclass 3, count 0 2006.224.08:19:09.56#ibcon#end of sib2, iclass 3, count 0 2006.224.08:19:09.56#ibcon#*after write, iclass 3, count 0 2006.224.08:19:09.56#ibcon#*before return 0, iclass 3, count 0 2006.224.08:19:09.56#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.224.08:19:09.56#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.224.08:19:09.56#ibcon#about to clear, iclass 3 cls_cnt 0 2006.224.08:19:09.56#ibcon#cleared, iclass 3 cls_cnt 0 2006.224.08:19:09.57$vc4f8/va=6,6 2006.224.08:19:09.57#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.224.08:19:09.57#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.224.08:19:09.57#ibcon#ireg 11 cls_cnt 2 2006.224.08:19:09.57#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.224.08:19:09.62#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.224.08:19:09.62#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.224.08:19:09.62#ibcon#enter wrdev, iclass 5, count 2 2006.224.08:19:09.62#ibcon#first serial, iclass 5, count 2 2006.224.08:19:09.62#ibcon#enter sib2, iclass 5, count 2 2006.224.08:19:09.62#ibcon#flushed, iclass 5, count 2 2006.224.08:19:09.62#ibcon#about to write, iclass 5, count 2 2006.224.08:19:09.62#ibcon#wrote, iclass 5, count 2 2006.224.08:19:09.62#ibcon#about to read 3, iclass 5, count 2 2006.224.08:19:09.63#ibcon#read 3, iclass 5, count 2 2006.224.08:19:09.63#ibcon#about to read 4, iclass 5, count 2 2006.224.08:19:09.63#ibcon#read 4, iclass 5, count 2 2006.224.08:19:09.63#ibcon#about to read 5, iclass 5, count 2 2006.224.08:19:09.63#ibcon#read 5, iclass 5, count 2 2006.224.08:19:09.63#ibcon#about to read 6, iclass 5, count 2 2006.224.08:19:09.63#ibcon#read 6, iclass 5, count 2 2006.224.08:19:09.63#ibcon#end of sib2, iclass 5, count 2 2006.224.08:19:09.63#ibcon#*mode == 0, iclass 5, count 2 2006.224.08:19:09.63#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.224.08:19:09.63#ibcon#[25=AT06-06\r\n] 2006.224.08:19:09.63#ibcon#*before write, iclass 5, count 2 2006.224.08:19:09.63#ibcon#enter sib2, iclass 5, count 2 2006.224.08:19:09.63#ibcon#flushed, iclass 5, count 2 2006.224.08:19:09.63#ibcon#about to write, iclass 5, count 2 2006.224.08:19:09.63#ibcon#wrote, iclass 5, count 2 2006.224.08:19:09.63#ibcon#about to read 3, iclass 5, count 2 2006.224.08:19:09.66#ibcon#read 3, iclass 5, count 2 2006.224.08:19:09.66#ibcon#about to read 4, iclass 5, count 2 2006.224.08:19:09.66#ibcon#read 4, iclass 5, count 2 2006.224.08:19:09.66#ibcon#about to read 5, iclass 5, count 2 2006.224.08:19:09.66#ibcon#read 5, iclass 5, count 2 2006.224.08:19:09.66#ibcon#about to read 6, iclass 5, count 2 2006.224.08:19:09.66#ibcon#read 6, iclass 5, count 2 2006.224.08:19:09.66#ibcon#end of sib2, iclass 5, count 2 2006.224.08:19:09.66#ibcon#*after write, iclass 5, count 2 2006.224.08:19:09.66#ibcon#*before return 0, iclass 5, count 2 2006.224.08:19:09.66#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.224.08:19:09.66#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.224.08:19:09.66#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.224.08:19:09.66#ibcon#ireg 7 cls_cnt 0 2006.224.08:19:09.66#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.224.08:19:09.78#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.224.08:19:09.78#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.224.08:19:09.78#ibcon#enter wrdev, iclass 5, count 0 2006.224.08:19:09.78#ibcon#first serial, iclass 5, count 0 2006.224.08:19:09.78#ibcon#enter sib2, iclass 5, count 0 2006.224.08:19:09.78#ibcon#flushed, iclass 5, count 0 2006.224.08:19:09.78#ibcon#about to write, iclass 5, count 0 2006.224.08:19:09.78#ibcon#wrote, iclass 5, count 0 2006.224.08:19:09.78#ibcon#about to read 3, iclass 5, count 0 2006.224.08:19:09.80#ibcon#read 3, iclass 5, count 0 2006.224.08:19:09.80#ibcon#about to read 4, iclass 5, count 0 2006.224.08:19:09.80#ibcon#read 4, iclass 5, count 0 2006.224.08:19:09.80#ibcon#about to read 5, iclass 5, count 0 2006.224.08:19:09.80#ibcon#read 5, iclass 5, count 0 2006.224.08:19:09.80#ibcon#about to read 6, iclass 5, count 0 2006.224.08:19:09.80#ibcon#read 6, iclass 5, count 0 2006.224.08:19:09.80#ibcon#end of sib2, iclass 5, count 0 2006.224.08:19:09.80#ibcon#*mode == 0, iclass 5, count 0 2006.224.08:19:09.80#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.224.08:19:09.80#ibcon#[25=USB\r\n] 2006.224.08:19:09.80#ibcon#*before write, iclass 5, count 0 2006.224.08:19:09.80#ibcon#enter sib2, iclass 5, count 0 2006.224.08:19:09.80#ibcon#flushed, iclass 5, count 0 2006.224.08:19:09.80#ibcon#about to write, iclass 5, count 0 2006.224.08:19:09.80#ibcon#wrote, iclass 5, count 0 2006.224.08:19:09.80#ibcon#about to read 3, iclass 5, count 0 2006.224.08:19:09.83#ibcon#read 3, iclass 5, count 0 2006.224.08:19:09.83#ibcon#about to read 4, iclass 5, count 0 2006.224.08:19:09.83#ibcon#read 4, iclass 5, count 0 2006.224.08:19:09.83#ibcon#about to read 5, iclass 5, count 0 2006.224.08:19:09.83#ibcon#read 5, iclass 5, count 0 2006.224.08:19:09.83#ibcon#about to read 6, iclass 5, count 0 2006.224.08:19:09.83#ibcon#read 6, iclass 5, count 0 2006.224.08:19:09.83#ibcon#end of sib2, iclass 5, count 0 2006.224.08:19:09.83#ibcon#*after write, iclass 5, count 0 2006.224.08:19:09.83#ibcon#*before return 0, iclass 5, count 0 2006.224.08:19:09.83#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.224.08:19:09.83#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.224.08:19:09.83#ibcon#about to clear, iclass 5 cls_cnt 0 2006.224.08:19:09.83#ibcon#cleared, iclass 5 cls_cnt 0 2006.224.08:19:09.83$vc4f8/valo=7,832.99 2006.224.08:19:09.84#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.224.08:19:09.84#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.224.08:19:09.84#ibcon#ireg 17 cls_cnt 0 2006.224.08:19:09.84#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.224.08:19:09.84#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.224.08:19:09.84#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.224.08:19:09.84#ibcon#enter wrdev, iclass 7, count 0 2006.224.08:19:09.84#ibcon#first serial, iclass 7, count 0 2006.224.08:19:09.84#ibcon#enter sib2, iclass 7, count 0 2006.224.08:19:09.84#ibcon#flushed, iclass 7, count 0 2006.224.08:19:09.84#ibcon#about to write, iclass 7, count 0 2006.224.08:19:09.84#ibcon#wrote, iclass 7, count 0 2006.224.08:19:09.84#ibcon#about to read 3, iclass 7, count 0 2006.224.08:19:09.85#ibcon#read 3, iclass 7, count 0 2006.224.08:19:09.85#ibcon#about to read 4, iclass 7, count 0 2006.224.08:19:09.85#ibcon#read 4, iclass 7, count 0 2006.224.08:19:09.85#ibcon#about to read 5, iclass 7, count 0 2006.224.08:19:09.85#ibcon#read 5, iclass 7, count 0 2006.224.08:19:09.85#ibcon#about to read 6, iclass 7, count 0 2006.224.08:19:09.85#ibcon#read 6, iclass 7, count 0 2006.224.08:19:09.85#ibcon#end of sib2, iclass 7, count 0 2006.224.08:19:09.85#ibcon#*mode == 0, iclass 7, count 0 2006.224.08:19:09.85#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.224.08:19:09.85#ibcon#[26=FRQ=07,832.99\r\n] 2006.224.08:19:09.85#ibcon#*before write, iclass 7, count 0 2006.224.08:19:09.85#ibcon#enter sib2, iclass 7, count 0 2006.224.08:19:09.85#ibcon#flushed, iclass 7, count 0 2006.224.08:19:09.85#ibcon#about to write, iclass 7, count 0 2006.224.08:19:09.85#ibcon#wrote, iclass 7, count 0 2006.224.08:19:09.85#ibcon#about to read 3, iclass 7, count 0 2006.224.08:19:09.89#ibcon#read 3, iclass 7, count 0 2006.224.08:19:09.89#ibcon#about to read 4, iclass 7, count 0 2006.224.08:19:09.89#ibcon#read 4, iclass 7, count 0 2006.224.08:19:09.89#ibcon#about to read 5, iclass 7, count 0 2006.224.08:19:09.89#ibcon#read 5, iclass 7, count 0 2006.224.08:19:09.89#ibcon#about to read 6, iclass 7, count 0 2006.224.08:19:09.89#ibcon#read 6, iclass 7, count 0 2006.224.08:19:09.89#ibcon#end of sib2, iclass 7, count 0 2006.224.08:19:09.89#ibcon#*after write, iclass 7, count 0 2006.224.08:19:09.89#ibcon#*before return 0, iclass 7, count 0 2006.224.08:19:09.89#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.224.08:19:09.89#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.224.08:19:09.89#ibcon#about to clear, iclass 7 cls_cnt 0 2006.224.08:19:09.89#ibcon#cleared, iclass 7 cls_cnt 0 2006.224.08:19:09.89$vc4f8/va=7,6 2006.224.08:19:09.89#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.224.08:19:09.89#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.224.08:19:09.90#ibcon#ireg 11 cls_cnt 2 2006.224.08:19:09.90#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.224.08:19:09.94#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.224.08:19:09.94#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.224.08:19:09.94#ibcon#enter wrdev, iclass 11, count 2 2006.224.08:19:09.94#ibcon#first serial, iclass 11, count 2 2006.224.08:19:09.94#ibcon#enter sib2, iclass 11, count 2 2006.224.08:19:09.94#ibcon#flushed, iclass 11, count 2 2006.224.08:19:09.94#ibcon#about to write, iclass 11, count 2 2006.224.08:19:09.94#ibcon#wrote, iclass 11, count 2 2006.224.08:19:09.94#ibcon#about to read 3, iclass 11, count 2 2006.224.08:19:09.96#ibcon#read 3, iclass 11, count 2 2006.224.08:19:09.96#ibcon#about to read 4, iclass 11, count 2 2006.224.08:19:09.96#ibcon#read 4, iclass 11, count 2 2006.224.08:19:09.96#ibcon#about to read 5, iclass 11, count 2 2006.224.08:19:09.96#ibcon#read 5, iclass 11, count 2 2006.224.08:19:09.96#ibcon#about to read 6, iclass 11, count 2 2006.224.08:19:09.96#ibcon#read 6, iclass 11, count 2 2006.224.08:19:09.96#ibcon#end of sib2, iclass 11, count 2 2006.224.08:19:09.96#ibcon#*mode == 0, iclass 11, count 2 2006.224.08:19:09.96#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.224.08:19:09.96#ibcon#[25=AT07-06\r\n] 2006.224.08:19:09.96#ibcon#*before write, iclass 11, count 2 2006.224.08:19:09.96#ibcon#enter sib2, iclass 11, count 2 2006.224.08:19:09.96#ibcon#flushed, iclass 11, count 2 2006.224.08:19:09.96#ibcon#about to write, iclass 11, count 2 2006.224.08:19:09.96#ibcon#wrote, iclass 11, count 2 2006.224.08:19:09.96#ibcon#about to read 3, iclass 11, count 2 2006.224.08:19:09.99#ibcon#read 3, iclass 11, count 2 2006.224.08:19:09.99#ibcon#about to read 4, iclass 11, count 2 2006.224.08:19:09.99#ibcon#read 4, iclass 11, count 2 2006.224.08:19:09.99#ibcon#about to read 5, iclass 11, count 2 2006.224.08:19:09.99#ibcon#read 5, iclass 11, count 2 2006.224.08:19:09.99#ibcon#about to read 6, iclass 11, count 2 2006.224.08:19:09.99#ibcon#read 6, iclass 11, count 2 2006.224.08:19:09.99#ibcon#end of sib2, iclass 11, count 2 2006.224.08:19:09.99#ibcon#*after write, iclass 11, count 2 2006.224.08:19:09.99#ibcon#*before return 0, iclass 11, count 2 2006.224.08:19:09.99#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.224.08:19:09.99#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.224.08:19:09.99#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.224.08:19:09.99#ibcon#ireg 7 cls_cnt 0 2006.224.08:19:09.99#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.224.08:19:10.11#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.224.08:19:10.11#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.224.08:19:10.11#ibcon#enter wrdev, iclass 11, count 0 2006.224.08:19:10.11#ibcon#first serial, iclass 11, count 0 2006.224.08:19:10.11#ibcon#enter sib2, iclass 11, count 0 2006.224.08:19:10.11#ibcon#flushed, iclass 11, count 0 2006.224.08:19:10.11#ibcon#about to write, iclass 11, count 0 2006.224.08:19:10.11#ibcon#wrote, iclass 11, count 0 2006.224.08:19:10.11#ibcon#about to read 3, iclass 11, count 0 2006.224.08:19:10.13#ibcon#read 3, iclass 11, count 0 2006.224.08:19:10.13#ibcon#about to read 4, iclass 11, count 0 2006.224.08:19:10.13#ibcon#read 4, iclass 11, count 0 2006.224.08:19:10.13#ibcon#about to read 5, iclass 11, count 0 2006.224.08:19:10.13#ibcon#read 5, iclass 11, count 0 2006.224.08:19:10.13#ibcon#about to read 6, iclass 11, count 0 2006.224.08:19:10.13#ibcon#read 6, iclass 11, count 0 2006.224.08:19:10.13#ibcon#end of sib2, iclass 11, count 0 2006.224.08:19:10.13#ibcon#*mode == 0, iclass 11, count 0 2006.224.08:19:10.13#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.224.08:19:10.13#ibcon#[25=USB\r\n] 2006.224.08:19:10.13#ibcon#*before write, iclass 11, count 0 2006.224.08:19:10.13#ibcon#enter sib2, iclass 11, count 0 2006.224.08:19:10.13#ibcon#flushed, iclass 11, count 0 2006.224.08:19:10.13#ibcon#about to write, iclass 11, count 0 2006.224.08:19:10.13#ibcon#wrote, iclass 11, count 0 2006.224.08:19:10.13#ibcon#about to read 3, iclass 11, count 0 2006.224.08:19:10.16#ibcon#read 3, iclass 11, count 0 2006.224.08:19:10.16#ibcon#about to read 4, iclass 11, count 0 2006.224.08:19:10.16#ibcon#read 4, iclass 11, count 0 2006.224.08:19:10.16#ibcon#about to read 5, iclass 11, count 0 2006.224.08:19:10.16#ibcon#read 5, iclass 11, count 0 2006.224.08:19:10.16#ibcon#about to read 6, iclass 11, count 0 2006.224.08:19:10.16#ibcon#read 6, iclass 11, count 0 2006.224.08:19:10.16#ibcon#end of sib2, iclass 11, count 0 2006.224.08:19:10.16#ibcon#*after write, iclass 11, count 0 2006.224.08:19:10.16#ibcon#*before return 0, iclass 11, count 0 2006.224.08:19:10.16#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.224.08:19:10.16#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.224.08:19:10.16#ibcon#about to clear, iclass 11 cls_cnt 0 2006.224.08:19:10.16#ibcon#cleared, iclass 11 cls_cnt 0 2006.224.08:19:10.16$vc4f8/valo=8,852.99 2006.224.08:19:10.16#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.224.08:19:10.16#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.224.08:19:10.16#ibcon#ireg 17 cls_cnt 0 2006.224.08:19:10.16#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.224.08:19:10.17#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.224.08:19:10.17#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.224.08:19:10.17#ibcon#enter wrdev, iclass 13, count 0 2006.224.08:19:10.17#ibcon#first serial, iclass 13, count 0 2006.224.08:19:10.17#ibcon#enter sib2, iclass 13, count 0 2006.224.08:19:10.17#ibcon#flushed, iclass 13, count 0 2006.224.08:19:10.17#ibcon#about to write, iclass 13, count 0 2006.224.08:19:10.17#ibcon#wrote, iclass 13, count 0 2006.224.08:19:10.17#ibcon#about to read 3, iclass 13, count 0 2006.224.08:19:10.18#ibcon#read 3, iclass 13, count 0 2006.224.08:19:10.18#ibcon#about to read 4, iclass 13, count 0 2006.224.08:19:10.18#ibcon#read 4, iclass 13, count 0 2006.224.08:19:10.18#ibcon#about to read 5, iclass 13, count 0 2006.224.08:19:10.18#ibcon#read 5, iclass 13, count 0 2006.224.08:19:10.18#ibcon#about to read 6, iclass 13, count 0 2006.224.08:19:10.18#ibcon#read 6, iclass 13, count 0 2006.224.08:19:10.18#ibcon#end of sib2, iclass 13, count 0 2006.224.08:19:10.18#ibcon#*mode == 0, iclass 13, count 0 2006.224.08:19:10.18#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.224.08:19:10.18#ibcon#[26=FRQ=08,852.99\r\n] 2006.224.08:19:10.18#ibcon#*before write, iclass 13, count 0 2006.224.08:19:10.18#ibcon#enter sib2, iclass 13, count 0 2006.224.08:19:10.18#ibcon#flushed, iclass 13, count 0 2006.224.08:19:10.18#ibcon#about to write, iclass 13, count 0 2006.224.08:19:10.18#ibcon#wrote, iclass 13, count 0 2006.224.08:19:10.18#ibcon#about to read 3, iclass 13, count 0 2006.224.08:19:10.22#ibcon#read 3, iclass 13, count 0 2006.224.08:19:10.22#ibcon#about to read 4, iclass 13, count 0 2006.224.08:19:10.22#ibcon#read 4, iclass 13, count 0 2006.224.08:19:10.22#ibcon#about to read 5, iclass 13, count 0 2006.224.08:19:10.22#ibcon#read 5, iclass 13, count 0 2006.224.08:19:10.22#ibcon#about to read 6, iclass 13, count 0 2006.224.08:19:10.22#ibcon#read 6, iclass 13, count 0 2006.224.08:19:10.22#ibcon#end of sib2, iclass 13, count 0 2006.224.08:19:10.22#ibcon#*after write, iclass 13, count 0 2006.224.08:19:10.22#ibcon#*before return 0, iclass 13, count 0 2006.224.08:19:10.22#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.224.08:19:10.22#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.224.08:19:10.22#ibcon#about to clear, iclass 13 cls_cnt 0 2006.224.08:19:10.22#ibcon#cleared, iclass 13 cls_cnt 0 2006.224.08:19:10.22$vc4f8/va=8,7 2006.224.08:19:10.22#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.224.08:19:10.22#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.224.08:19:10.23#ibcon#ireg 11 cls_cnt 2 2006.224.08:19:10.23#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.224.08:19:10.27#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.224.08:19:10.27#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.224.08:19:10.27#ibcon#enter wrdev, iclass 15, count 2 2006.224.08:19:10.27#ibcon#first serial, iclass 15, count 2 2006.224.08:19:10.27#ibcon#enter sib2, iclass 15, count 2 2006.224.08:19:10.27#ibcon#flushed, iclass 15, count 2 2006.224.08:19:10.27#ibcon#about to write, iclass 15, count 2 2006.224.08:19:10.27#ibcon#wrote, iclass 15, count 2 2006.224.08:19:10.27#ibcon#about to read 3, iclass 15, count 2 2006.224.08:19:10.29#ibcon#read 3, iclass 15, count 2 2006.224.08:19:10.29#ibcon#about to read 4, iclass 15, count 2 2006.224.08:19:10.29#ibcon#read 4, iclass 15, count 2 2006.224.08:19:10.29#ibcon#about to read 5, iclass 15, count 2 2006.224.08:19:10.29#ibcon#read 5, iclass 15, count 2 2006.224.08:19:10.29#ibcon#about to read 6, iclass 15, count 2 2006.224.08:19:10.29#ibcon#read 6, iclass 15, count 2 2006.224.08:19:10.29#ibcon#end of sib2, iclass 15, count 2 2006.224.08:19:10.29#ibcon#*mode == 0, iclass 15, count 2 2006.224.08:19:10.29#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.224.08:19:10.29#ibcon#[25=AT08-07\r\n] 2006.224.08:19:10.29#ibcon#*before write, iclass 15, count 2 2006.224.08:19:10.29#ibcon#enter sib2, iclass 15, count 2 2006.224.08:19:10.29#ibcon#flushed, iclass 15, count 2 2006.224.08:19:10.29#ibcon#about to write, iclass 15, count 2 2006.224.08:19:10.29#ibcon#wrote, iclass 15, count 2 2006.224.08:19:10.29#ibcon#about to read 3, iclass 15, count 2 2006.224.08:19:10.32#ibcon#read 3, iclass 15, count 2 2006.224.08:19:10.32#ibcon#about to read 4, iclass 15, count 2 2006.224.08:19:10.32#ibcon#read 4, iclass 15, count 2 2006.224.08:19:10.32#ibcon#about to read 5, iclass 15, count 2 2006.224.08:19:10.32#ibcon#read 5, iclass 15, count 2 2006.224.08:19:10.32#ibcon#about to read 6, iclass 15, count 2 2006.224.08:19:10.32#ibcon#read 6, iclass 15, count 2 2006.224.08:19:10.32#ibcon#end of sib2, iclass 15, count 2 2006.224.08:19:10.32#ibcon#*after write, iclass 15, count 2 2006.224.08:19:10.32#ibcon#*before return 0, iclass 15, count 2 2006.224.08:19:10.32#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.224.08:19:10.32#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.224.08:19:10.32#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.224.08:19:10.32#ibcon#ireg 7 cls_cnt 0 2006.224.08:19:10.32#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.224.08:19:10.44#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.224.08:19:10.44#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.224.08:19:10.44#ibcon#enter wrdev, iclass 15, count 0 2006.224.08:19:10.44#ibcon#first serial, iclass 15, count 0 2006.224.08:19:10.44#ibcon#enter sib2, iclass 15, count 0 2006.224.08:19:10.44#ibcon#flushed, iclass 15, count 0 2006.224.08:19:10.44#ibcon#about to write, iclass 15, count 0 2006.224.08:19:10.44#ibcon#wrote, iclass 15, count 0 2006.224.08:19:10.44#ibcon#about to read 3, iclass 15, count 0 2006.224.08:19:10.46#ibcon#read 3, iclass 15, count 0 2006.224.08:19:10.46#ibcon#about to read 4, iclass 15, count 0 2006.224.08:19:10.46#ibcon#read 4, iclass 15, count 0 2006.224.08:19:10.46#ibcon#about to read 5, iclass 15, count 0 2006.224.08:19:10.46#ibcon#read 5, iclass 15, count 0 2006.224.08:19:10.46#ibcon#about to read 6, iclass 15, count 0 2006.224.08:19:10.46#ibcon#read 6, iclass 15, count 0 2006.224.08:19:10.46#ibcon#end of sib2, iclass 15, count 0 2006.224.08:19:10.46#ibcon#*mode == 0, iclass 15, count 0 2006.224.08:19:10.46#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.224.08:19:10.46#ibcon#[25=USB\r\n] 2006.224.08:19:10.46#ibcon#*before write, iclass 15, count 0 2006.224.08:19:10.46#ibcon#enter sib2, iclass 15, count 0 2006.224.08:19:10.46#ibcon#flushed, iclass 15, count 0 2006.224.08:19:10.46#ibcon#about to write, iclass 15, count 0 2006.224.08:19:10.46#ibcon#wrote, iclass 15, count 0 2006.224.08:19:10.46#ibcon#about to read 3, iclass 15, count 0 2006.224.08:19:10.49#ibcon#read 3, iclass 15, count 0 2006.224.08:19:10.49#ibcon#about to read 4, iclass 15, count 0 2006.224.08:19:10.49#ibcon#read 4, iclass 15, count 0 2006.224.08:19:10.49#ibcon#about to read 5, iclass 15, count 0 2006.224.08:19:10.49#ibcon#read 5, iclass 15, count 0 2006.224.08:19:10.49#ibcon#about to read 6, iclass 15, count 0 2006.224.08:19:10.49#ibcon#read 6, iclass 15, count 0 2006.224.08:19:10.49#ibcon#end of sib2, iclass 15, count 0 2006.224.08:19:10.49#ibcon#*after write, iclass 15, count 0 2006.224.08:19:10.49#ibcon#*before return 0, iclass 15, count 0 2006.224.08:19:10.49#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.224.08:19:10.49#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.224.08:19:10.49#ibcon#about to clear, iclass 15 cls_cnt 0 2006.224.08:19:10.49#ibcon#cleared, iclass 15 cls_cnt 0 2006.224.08:19:10.49$vc4f8/vblo=1,632.99 2006.224.08:19:10.49#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.224.08:19:10.49#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.224.08:19:10.49#ibcon#ireg 17 cls_cnt 0 2006.224.08:19:10.49#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.224.08:19:10.49#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.224.08:19:10.50#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.224.08:19:10.50#ibcon#enter wrdev, iclass 17, count 0 2006.224.08:19:10.50#ibcon#first serial, iclass 17, count 0 2006.224.08:19:10.50#ibcon#enter sib2, iclass 17, count 0 2006.224.08:19:10.50#ibcon#flushed, iclass 17, count 0 2006.224.08:19:10.50#ibcon#about to write, iclass 17, count 0 2006.224.08:19:10.50#ibcon#wrote, iclass 17, count 0 2006.224.08:19:10.50#ibcon#about to read 3, iclass 17, count 0 2006.224.08:19:10.51#ibcon#read 3, iclass 17, count 0 2006.224.08:19:10.51#ibcon#about to read 4, iclass 17, count 0 2006.224.08:19:10.51#ibcon#read 4, iclass 17, count 0 2006.224.08:19:10.51#ibcon#about to read 5, iclass 17, count 0 2006.224.08:19:10.51#ibcon#read 5, iclass 17, count 0 2006.224.08:19:10.51#ibcon#about to read 6, iclass 17, count 0 2006.224.08:19:10.51#ibcon#read 6, iclass 17, count 0 2006.224.08:19:10.51#ibcon#end of sib2, iclass 17, count 0 2006.224.08:19:10.51#ibcon#*mode == 0, iclass 17, count 0 2006.224.08:19:10.51#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.224.08:19:10.51#ibcon#[28=FRQ=01,632.99\r\n] 2006.224.08:19:10.51#ibcon#*before write, iclass 17, count 0 2006.224.08:19:10.51#ibcon#enter sib2, iclass 17, count 0 2006.224.08:19:10.51#ibcon#flushed, iclass 17, count 0 2006.224.08:19:10.51#ibcon#about to write, iclass 17, count 0 2006.224.08:19:10.51#ibcon#wrote, iclass 17, count 0 2006.224.08:19:10.51#ibcon#about to read 3, iclass 17, count 0 2006.224.08:19:10.55#ibcon#read 3, iclass 17, count 0 2006.224.08:19:10.55#ibcon#about to read 4, iclass 17, count 0 2006.224.08:19:10.55#ibcon#read 4, iclass 17, count 0 2006.224.08:19:10.55#ibcon#about to read 5, iclass 17, count 0 2006.224.08:19:10.55#ibcon#read 5, iclass 17, count 0 2006.224.08:19:10.55#ibcon#about to read 6, iclass 17, count 0 2006.224.08:19:10.55#ibcon#read 6, iclass 17, count 0 2006.224.08:19:10.55#ibcon#end of sib2, iclass 17, count 0 2006.224.08:19:10.55#ibcon#*after write, iclass 17, count 0 2006.224.08:19:10.55#ibcon#*before return 0, iclass 17, count 0 2006.224.08:19:10.55#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.224.08:19:10.55#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.224.08:19:10.55#ibcon#about to clear, iclass 17 cls_cnt 0 2006.224.08:19:10.55#ibcon#cleared, iclass 17 cls_cnt 0 2006.224.08:19:10.55$vc4f8/vb=1,4 2006.224.08:19:10.55#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.224.08:19:10.55#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.224.08:19:10.56#ibcon#ireg 11 cls_cnt 2 2006.224.08:19:10.56#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.224.08:19:10.56#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.224.08:19:10.56#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.224.08:19:10.56#ibcon#enter wrdev, iclass 19, count 2 2006.224.08:19:10.56#ibcon#first serial, iclass 19, count 2 2006.224.08:19:10.56#ibcon#enter sib2, iclass 19, count 2 2006.224.08:19:10.56#ibcon#flushed, iclass 19, count 2 2006.224.08:19:10.56#ibcon#about to write, iclass 19, count 2 2006.224.08:19:10.56#ibcon#wrote, iclass 19, count 2 2006.224.08:19:10.56#ibcon#about to read 3, iclass 19, count 2 2006.224.08:19:10.57#ibcon#read 3, iclass 19, count 2 2006.224.08:19:10.57#ibcon#about to read 4, iclass 19, count 2 2006.224.08:19:10.57#ibcon#read 4, iclass 19, count 2 2006.224.08:19:10.57#ibcon#about to read 5, iclass 19, count 2 2006.224.08:19:10.57#ibcon#read 5, iclass 19, count 2 2006.224.08:19:10.57#ibcon#about to read 6, iclass 19, count 2 2006.224.08:19:10.57#ibcon#read 6, iclass 19, count 2 2006.224.08:19:10.57#ibcon#end of sib2, iclass 19, count 2 2006.224.08:19:10.57#ibcon#*mode == 0, iclass 19, count 2 2006.224.08:19:10.57#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.224.08:19:10.57#ibcon#[27=AT01-04\r\n] 2006.224.08:19:10.57#ibcon#*before write, iclass 19, count 2 2006.224.08:19:10.57#ibcon#enter sib2, iclass 19, count 2 2006.224.08:19:10.57#ibcon#flushed, iclass 19, count 2 2006.224.08:19:10.57#ibcon#about to write, iclass 19, count 2 2006.224.08:19:10.57#ibcon#wrote, iclass 19, count 2 2006.224.08:19:10.57#ibcon#about to read 3, iclass 19, count 2 2006.224.08:19:10.60#ibcon#read 3, iclass 19, count 2 2006.224.08:19:10.60#ibcon#about to read 4, iclass 19, count 2 2006.224.08:19:10.60#ibcon#read 4, iclass 19, count 2 2006.224.08:19:10.60#ibcon#about to read 5, iclass 19, count 2 2006.224.08:19:10.60#ibcon#read 5, iclass 19, count 2 2006.224.08:19:10.60#ibcon#about to read 6, iclass 19, count 2 2006.224.08:19:10.60#ibcon#read 6, iclass 19, count 2 2006.224.08:19:10.60#ibcon#end of sib2, iclass 19, count 2 2006.224.08:19:10.60#ibcon#*after write, iclass 19, count 2 2006.224.08:19:10.60#ibcon#*before return 0, iclass 19, count 2 2006.224.08:19:10.60#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.224.08:19:10.60#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.224.08:19:10.60#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.224.08:19:10.60#ibcon#ireg 7 cls_cnt 0 2006.224.08:19:10.60#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.224.08:19:10.72#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.224.08:19:10.72#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.224.08:19:10.72#ibcon#enter wrdev, iclass 19, count 0 2006.224.08:19:10.72#ibcon#first serial, iclass 19, count 0 2006.224.08:19:10.72#ibcon#enter sib2, iclass 19, count 0 2006.224.08:19:10.72#ibcon#flushed, iclass 19, count 0 2006.224.08:19:10.72#ibcon#about to write, iclass 19, count 0 2006.224.08:19:10.72#ibcon#wrote, iclass 19, count 0 2006.224.08:19:10.72#ibcon#about to read 3, iclass 19, count 0 2006.224.08:19:10.74#ibcon#read 3, iclass 19, count 0 2006.224.08:19:10.74#ibcon#about to read 4, iclass 19, count 0 2006.224.08:19:10.74#ibcon#read 4, iclass 19, count 0 2006.224.08:19:10.74#ibcon#about to read 5, iclass 19, count 0 2006.224.08:19:10.74#ibcon#read 5, iclass 19, count 0 2006.224.08:19:10.74#ibcon#about to read 6, iclass 19, count 0 2006.224.08:19:10.74#ibcon#read 6, iclass 19, count 0 2006.224.08:19:10.74#ibcon#end of sib2, iclass 19, count 0 2006.224.08:19:10.74#ibcon#*mode == 0, iclass 19, count 0 2006.224.08:19:10.74#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.224.08:19:10.74#ibcon#[27=USB\r\n] 2006.224.08:19:10.74#ibcon#*before write, iclass 19, count 0 2006.224.08:19:10.74#ibcon#enter sib2, iclass 19, count 0 2006.224.08:19:10.74#ibcon#flushed, iclass 19, count 0 2006.224.08:19:10.74#ibcon#about to write, iclass 19, count 0 2006.224.08:19:10.74#ibcon#wrote, iclass 19, count 0 2006.224.08:19:10.74#ibcon#about to read 3, iclass 19, count 0 2006.224.08:19:10.77#ibcon#read 3, iclass 19, count 0 2006.224.08:19:10.77#ibcon#about to read 4, iclass 19, count 0 2006.224.08:19:10.77#ibcon#read 4, iclass 19, count 0 2006.224.08:19:10.77#ibcon#about to read 5, iclass 19, count 0 2006.224.08:19:10.77#ibcon#read 5, iclass 19, count 0 2006.224.08:19:10.77#ibcon#about to read 6, iclass 19, count 0 2006.224.08:19:10.77#ibcon#read 6, iclass 19, count 0 2006.224.08:19:10.77#ibcon#end of sib2, iclass 19, count 0 2006.224.08:19:10.77#ibcon#*after write, iclass 19, count 0 2006.224.08:19:10.77#ibcon#*before return 0, iclass 19, count 0 2006.224.08:19:10.77#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.224.08:19:10.77#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.224.08:19:10.77#ibcon#about to clear, iclass 19 cls_cnt 0 2006.224.08:19:10.77#ibcon#cleared, iclass 19 cls_cnt 0 2006.224.08:19:10.77$vc4f8/vblo=2,640.99 2006.224.08:19:10.77#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.224.08:19:10.77#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.224.08:19:10.77#ibcon#ireg 17 cls_cnt 0 2006.224.08:19:10.78#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.224.08:19:10.78#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.224.08:19:10.78#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.224.08:19:10.78#ibcon#enter wrdev, iclass 21, count 0 2006.224.08:19:10.78#ibcon#first serial, iclass 21, count 0 2006.224.08:19:10.78#ibcon#enter sib2, iclass 21, count 0 2006.224.08:19:10.78#ibcon#flushed, iclass 21, count 0 2006.224.08:19:10.78#ibcon#about to write, iclass 21, count 0 2006.224.08:19:10.78#ibcon#wrote, iclass 21, count 0 2006.224.08:19:10.78#ibcon#about to read 3, iclass 21, count 0 2006.224.08:19:10.79#ibcon#read 3, iclass 21, count 0 2006.224.08:19:10.79#ibcon#about to read 4, iclass 21, count 0 2006.224.08:19:10.79#ibcon#read 4, iclass 21, count 0 2006.224.08:19:10.79#ibcon#about to read 5, iclass 21, count 0 2006.224.08:19:10.79#ibcon#read 5, iclass 21, count 0 2006.224.08:19:10.79#ibcon#about to read 6, iclass 21, count 0 2006.224.08:19:10.79#ibcon#read 6, iclass 21, count 0 2006.224.08:19:10.79#ibcon#end of sib2, iclass 21, count 0 2006.224.08:19:10.79#ibcon#*mode == 0, iclass 21, count 0 2006.224.08:19:10.79#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.224.08:19:10.79#ibcon#[28=FRQ=02,640.99\r\n] 2006.224.08:19:10.79#ibcon#*before write, iclass 21, count 0 2006.224.08:19:10.79#ibcon#enter sib2, iclass 21, count 0 2006.224.08:19:10.79#ibcon#flushed, iclass 21, count 0 2006.224.08:19:10.79#ibcon#about to write, iclass 21, count 0 2006.224.08:19:10.79#ibcon#wrote, iclass 21, count 0 2006.224.08:19:10.79#ibcon#about to read 3, iclass 21, count 0 2006.224.08:19:10.83#ibcon#read 3, iclass 21, count 0 2006.224.08:19:10.83#ibcon#about to read 4, iclass 21, count 0 2006.224.08:19:10.83#ibcon#read 4, iclass 21, count 0 2006.224.08:19:10.83#ibcon#about to read 5, iclass 21, count 0 2006.224.08:19:10.83#ibcon#read 5, iclass 21, count 0 2006.224.08:19:10.83#ibcon#about to read 6, iclass 21, count 0 2006.224.08:19:10.83#ibcon#read 6, iclass 21, count 0 2006.224.08:19:10.83#ibcon#end of sib2, iclass 21, count 0 2006.224.08:19:10.83#ibcon#*after write, iclass 21, count 0 2006.224.08:19:10.83#ibcon#*before return 0, iclass 21, count 0 2006.224.08:19:10.83#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.224.08:19:10.83#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.224.08:19:10.83#ibcon#about to clear, iclass 21 cls_cnt 0 2006.224.08:19:10.83#ibcon#cleared, iclass 21 cls_cnt 0 2006.224.08:19:10.83$vc4f8/vb=2,4 2006.224.08:19:10.83#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.224.08:19:10.83#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.224.08:19:10.84#ibcon#ireg 11 cls_cnt 2 2006.224.08:19:10.84#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.224.08:19:10.88#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.224.08:19:10.88#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.224.08:19:10.88#ibcon#enter wrdev, iclass 23, count 2 2006.224.08:19:10.88#ibcon#first serial, iclass 23, count 2 2006.224.08:19:10.88#ibcon#enter sib2, iclass 23, count 2 2006.224.08:19:10.88#ibcon#flushed, iclass 23, count 2 2006.224.08:19:10.88#ibcon#about to write, iclass 23, count 2 2006.224.08:19:10.88#ibcon#wrote, iclass 23, count 2 2006.224.08:19:10.88#ibcon#about to read 3, iclass 23, count 2 2006.224.08:19:10.90#ibcon#read 3, iclass 23, count 2 2006.224.08:19:10.90#ibcon#about to read 4, iclass 23, count 2 2006.224.08:19:10.90#ibcon#read 4, iclass 23, count 2 2006.224.08:19:10.90#ibcon#about to read 5, iclass 23, count 2 2006.224.08:19:10.90#ibcon#read 5, iclass 23, count 2 2006.224.08:19:10.90#ibcon#about to read 6, iclass 23, count 2 2006.224.08:19:10.90#ibcon#read 6, iclass 23, count 2 2006.224.08:19:10.90#ibcon#end of sib2, iclass 23, count 2 2006.224.08:19:10.90#ibcon#*mode == 0, iclass 23, count 2 2006.224.08:19:10.90#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.224.08:19:10.90#ibcon#[27=AT02-04\r\n] 2006.224.08:19:10.90#ibcon#*before write, iclass 23, count 2 2006.224.08:19:10.90#ibcon#enter sib2, iclass 23, count 2 2006.224.08:19:10.90#ibcon#flushed, iclass 23, count 2 2006.224.08:19:10.90#ibcon#about to write, iclass 23, count 2 2006.224.08:19:10.90#ibcon#wrote, iclass 23, count 2 2006.224.08:19:10.90#ibcon#about to read 3, iclass 23, count 2 2006.224.08:19:10.93#ibcon#read 3, iclass 23, count 2 2006.224.08:19:10.93#ibcon#about to read 4, iclass 23, count 2 2006.224.08:19:10.93#ibcon#read 4, iclass 23, count 2 2006.224.08:19:10.93#ibcon#about to read 5, iclass 23, count 2 2006.224.08:19:10.93#ibcon#read 5, iclass 23, count 2 2006.224.08:19:10.93#ibcon#about to read 6, iclass 23, count 2 2006.224.08:19:10.93#ibcon#read 6, iclass 23, count 2 2006.224.08:19:10.93#ibcon#end of sib2, iclass 23, count 2 2006.224.08:19:10.93#ibcon#*after write, iclass 23, count 2 2006.224.08:19:10.93#ibcon#*before return 0, iclass 23, count 2 2006.224.08:19:10.93#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.224.08:19:10.93#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.224.08:19:10.93#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.224.08:19:10.93#ibcon#ireg 7 cls_cnt 0 2006.224.08:19:10.93#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.224.08:19:11.05#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.224.08:19:11.05#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.224.08:19:11.05#ibcon#enter wrdev, iclass 23, count 0 2006.224.08:19:11.05#ibcon#first serial, iclass 23, count 0 2006.224.08:19:11.05#ibcon#enter sib2, iclass 23, count 0 2006.224.08:19:11.05#ibcon#flushed, iclass 23, count 0 2006.224.08:19:11.05#ibcon#about to write, iclass 23, count 0 2006.224.08:19:11.05#ibcon#wrote, iclass 23, count 0 2006.224.08:19:11.05#ibcon#about to read 3, iclass 23, count 0 2006.224.08:19:11.07#ibcon#read 3, iclass 23, count 0 2006.224.08:19:11.07#ibcon#about to read 4, iclass 23, count 0 2006.224.08:19:11.07#ibcon#read 4, iclass 23, count 0 2006.224.08:19:11.07#ibcon#about to read 5, iclass 23, count 0 2006.224.08:19:11.07#ibcon#read 5, iclass 23, count 0 2006.224.08:19:11.07#ibcon#about to read 6, iclass 23, count 0 2006.224.08:19:11.07#ibcon#read 6, iclass 23, count 0 2006.224.08:19:11.07#ibcon#end of sib2, iclass 23, count 0 2006.224.08:19:11.07#ibcon#*mode == 0, iclass 23, count 0 2006.224.08:19:11.07#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.224.08:19:11.07#ibcon#[27=USB\r\n] 2006.224.08:19:11.07#ibcon#*before write, iclass 23, count 0 2006.224.08:19:11.07#ibcon#enter sib2, iclass 23, count 0 2006.224.08:19:11.07#ibcon#flushed, iclass 23, count 0 2006.224.08:19:11.07#ibcon#about to write, iclass 23, count 0 2006.224.08:19:11.07#ibcon#wrote, iclass 23, count 0 2006.224.08:19:11.07#ibcon#about to read 3, iclass 23, count 0 2006.224.08:19:11.10#ibcon#read 3, iclass 23, count 0 2006.224.08:19:11.10#ibcon#about to read 4, iclass 23, count 0 2006.224.08:19:11.10#ibcon#read 4, iclass 23, count 0 2006.224.08:19:11.10#ibcon#about to read 5, iclass 23, count 0 2006.224.08:19:11.10#ibcon#read 5, iclass 23, count 0 2006.224.08:19:11.10#ibcon#about to read 6, iclass 23, count 0 2006.224.08:19:11.10#ibcon#read 6, iclass 23, count 0 2006.224.08:19:11.10#ibcon#end of sib2, iclass 23, count 0 2006.224.08:19:11.10#ibcon#*after write, iclass 23, count 0 2006.224.08:19:11.10#ibcon#*before return 0, iclass 23, count 0 2006.224.08:19:11.10#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.224.08:19:11.10#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.224.08:19:11.10#ibcon#about to clear, iclass 23 cls_cnt 0 2006.224.08:19:11.10#ibcon#cleared, iclass 23 cls_cnt 0 2006.224.08:19:11.10$vc4f8/vblo=3,656.99 2006.224.08:19:11.11#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.224.08:19:11.11#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.224.08:19:11.11#ibcon#ireg 17 cls_cnt 0 2006.224.08:19:11.11#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.224.08:19:11.11#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.224.08:19:11.11#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.224.08:19:11.11#ibcon#enter wrdev, iclass 25, count 0 2006.224.08:19:11.11#ibcon#first serial, iclass 25, count 0 2006.224.08:19:11.11#ibcon#enter sib2, iclass 25, count 0 2006.224.08:19:11.11#ibcon#flushed, iclass 25, count 0 2006.224.08:19:11.11#ibcon#about to write, iclass 25, count 0 2006.224.08:19:11.11#ibcon#wrote, iclass 25, count 0 2006.224.08:19:11.11#ibcon#about to read 3, iclass 25, count 0 2006.224.08:19:11.12#ibcon#read 3, iclass 25, count 0 2006.224.08:19:11.12#ibcon#about to read 4, iclass 25, count 0 2006.224.08:19:11.12#ibcon#read 4, iclass 25, count 0 2006.224.08:19:11.12#ibcon#about to read 5, iclass 25, count 0 2006.224.08:19:11.12#ibcon#read 5, iclass 25, count 0 2006.224.08:19:11.12#ibcon#about to read 6, iclass 25, count 0 2006.224.08:19:11.12#ibcon#read 6, iclass 25, count 0 2006.224.08:19:11.12#ibcon#end of sib2, iclass 25, count 0 2006.224.08:19:11.12#ibcon#*mode == 0, iclass 25, count 0 2006.224.08:19:11.12#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.224.08:19:11.12#ibcon#[28=FRQ=03,656.99\r\n] 2006.224.08:19:11.12#ibcon#*before write, iclass 25, count 0 2006.224.08:19:11.12#ibcon#enter sib2, iclass 25, count 0 2006.224.08:19:11.12#ibcon#flushed, iclass 25, count 0 2006.224.08:19:11.12#ibcon#about to write, iclass 25, count 0 2006.224.08:19:11.12#ibcon#wrote, iclass 25, count 0 2006.224.08:19:11.12#ibcon#about to read 3, iclass 25, count 0 2006.224.08:19:11.16#ibcon#read 3, iclass 25, count 0 2006.224.08:19:11.16#ibcon#about to read 4, iclass 25, count 0 2006.224.08:19:11.16#ibcon#read 4, iclass 25, count 0 2006.224.08:19:11.16#ibcon#about to read 5, iclass 25, count 0 2006.224.08:19:11.16#ibcon#read 5, iclass 25, count 0 2006.224.08:19:11.16#ibcon#about to read 6, iclass 25, count 0 2006.224.08:19:11.16#ibcon#read 6, iclass 25, count 0 2006.224.08:19:11.16#ibcon#end of sib2, iclass 25, count 0 2006.224.08:19:11.16#ibcon#*after write, iclass 25, count 0 2006.224.08:19:11.16#ibcon#*before return 0, iclass 25, count 0 2006.224.08:19:11.16#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.224.08:19:11.16#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.224.08:19:11.16#ibcon#about to clear, iclass 25 cls_cnt 0 2006.224.08:19:11.16#ibcon#cleared, iclass 25 cls_cnt 0 2006.224.08:19:11.16$vc4f8/vb=3,4 2006.224.08:19:11.16#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.224.08:19:11.16#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.224.08:19:11.16#ibcon#ireg 11 cls_cnt 2 2006.224.08:19:11.17#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.224.08:19:11.22#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.224.08:19:11.22#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.224.08:19:11.22#ibcon#enter wrdev, iclass 27, count 2 2006.224.08:19:11.22#ibcon#first serial, iclass 27, count 2 2006.224.08:19:11.22#ibcon#enter sib2, iclass 27, count 2 2006.224.08:19:11.22#ibcon#flushed, iclass 27, count 2 2006.224.08:19:11.22#ibcon#about to write, iclass 27, count 2 2006.224.08:19:11.22#ibcon#wrote, iclass 27, count 2 2006.224.08:19:11.22#ibcon#about to read 3, iclass 27, count 2 2006.224.08:19:11.24#ibcon#read 3, iclass 27, count 2 2006.224.08:19:11.24#ibcon#about to read 4, iclass 27, count 2 2006.224.08:19:11.24#ibcon#read 4, iclass 27, count 2 2006.224.08:19:11.24#ibcon#about to read 5, iclass 27, count 2 2006.224.08:19:11.24#ibcon#read 5, iclass 27, count 2 2006.224.08:19:11.24#ibcon#about to read 6, iclass 27, count 2 2006.224.08:19:11.24#ibcon#read 6, iclass 27, count 2 2006.224.08:19:11.24#ibcon#end of sib2, iclass 27, count 2 2006.224.08:19:11.24#ibcon#*mode == 0, iclass 27, count 2 2006.224.08:19:11.24#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.224.08:19:11.24#ibcon#[27=AT03-04\r\n] 2006.224.08:19:11.24#ibcon#*before write, iclass 27, count 2 2006.224.08:19:11.24#ibcon#enter sib2, iclass 27, count 2 2006.224.08:19:11.24#ibcon#flushed, iclass 27, count 2 2006.224.08:19:11.24#ibcon#about to write, iclass 27, count 2 2006.224.08:19:11.24#ibcon#wrote, iclass 27, count 2 2006.224.08:19:11.24#ibcon#about to read 3, iclass 27, count 2 2006.224.08:19:11.28#ibcon#read 3, iclass 27, count 2 2006.224.08:19:11.28#ibcon#about to read 4, iclass 27, count 2 2006.224.08:19:11.28#ibcon#read 4, iclass 27, count 2 2006.224.08:19:11.28#ibcon#about to read 5, iclass 27, count 2 2006.224.08:19:11.28#ibcon#read 5, iclass 27, count 2 2006.224.08:19:11.28#ibcon#about to read 6, iclass 27, count 2 2006.224.08:19:11.28#ibcon#read 6, iclass 27, count 2 2006.224.08:19:11.28#ibcon#end of sib2, iclass 27, count 2 2006.224.08:19:11.28#ibcon#*after write, iclass 27, count 2 2006.224.08:19:11.28#ibcon#*before return 0, iclass 27, count 2 2006.224.08:19:11.28#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.224.08:19:11.28#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.224.08:19:11.28#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.224.08:19:11.28#ibcon#ireg 7 cls_cnt 0 2006.224.08:19:11.28#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.224.08:19:11.39#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.224.08:19:11.39#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.224.08:19:11.39#ibcon#enter wrdev, iclass 27, count 0 2006.224.08:19:11.39#ibcon#first serial, iclass 27, count 0 2006.224.08:19:11.39#ibcon#enter sib2, iclass 27, count 0 2006.224.08:19:11.39#ibcon#flushed, iclass 27, count 0 2006.224.08:19:11.39#ibcon#about to write, iclass 27, count 0 2006.224.08:19:11.39#ibcon#wrote, iclass 27, count 0 2006.224.08:19:11.39#ibcon#about to read 3, iclass 27, count 0 2006.224.08:19:11.41#ibcon#read 3, iclass 27, count 0 2006.224.08:19:11.41#ibcon#about to read 4, iclass 27, count 0 2006.224.08:19:11.41#ibcon#read 4, iclass 27, count 0 2006.224.08:19:11.41#ibcon#about to read 5, iclass 27, count 0 2006.224.08:19:11.41#ibcon#read 5, iclass 27, count 0 2006.224.08:19:11.41#ibcon#about to read 6, iclass 27, count 0 2006.224.08:19:11.41#ibcon#read 6, iclass 27, count 0 2006.224.08:19:11.41#ibcon#end of sib2, iclass 27, count 0 2006.224.08:19:11.41#ibcon#*mode == 0, iclass 27, count 0 2006.224.08:19:11.41#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.224.08:19:11.41#ibcon#[27=USB\r\n] 2006.224.08:19:11.41#ibcon#*before write, iclass 27, count 0 2006.224.08:19:11.41#ibcon#enter sib2, iclass 27, count 0 2006.224.08:19:11.41#ibcon#flushed, iclass 27, count 0 2006.224.08:19:11.41#ibcon#about to write, iclass 27, count 0 2006.224.08:19:11.41#ibcon#wrote, iclass 27, count 0 2006.224.08:19:11.41#ibcon#about to read 3, iclass 27, count 0 2006.224.08:19:11.44#ibcon#read 3, iclass 27, count 0 2006.224.08:19:11.44#ibcon#about to read 4, iclass 27, count 0 2006.224.08:19:11.44#ibcon#read 4, iclass 27, count 0 2006.224.08:19:11.44#ibcon#about to read 5, iclass 27, count 0 2006.224.08:19:11.44#ibcon#read 5, iclass 27, count 0 2006.224.08:19:11.44#ibcon#about to read 6, iclass 27, count 0 2006.224.08:19:11.44#ibcon#read 6, iclass 27, count 0 2006.224.08:19:11.44#ibcon#end of sib2, iclass 27, count 0 2006.224.08:19:11.44#ibcon#*after write, iclass 27, count 0 2006.224.08:19:11.44#ibcon#*before return 0, iclass 27, count 0 2006.224.08:19:11.44#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.224.08:19:11.44#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.224.08:19:11.44#ibcon#about to clear, iclass 27 cls_cnt 0 2006.224.08:19:11.44#ibcon#cleared, iclass 27 cls_cnt 0 2006.224.08:19:11.44$vc4f8/vblo=4,712.99 2006.224.08:19:11.44#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.224.08:19:11.44#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.224.08:19:11.44#ibcon#ireg 17 cls_cnt 0 2006.224.08:19:11.45#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.224.08:19:11.45#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.224.08:19:11.45#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.224.08:19:11.45#ibcon#enter wrdev, iclass 29, count 0 2006.224.08:19:11.45#ibcon#first serial, iclass 29, count 0 2006.224.08:19:11.45#ibcon#enter sib2, iclass 29, count 0 2006.224.08:19:11.45#ibcon#flushed, iclass 29, count 0 2006.224.08:19:11.45#ibcon#about to write, iclass 29, count 0 2006.224.08:19:11.45#ibcon#wrote, iclass 29, count 0 2006.224.08:19:11.45#ibcon#about to read 3, iclass 29, count 0 2006.224.08:19:11.46#ibcon#read 3, iclass 29, count 0 2006.224.08:19:11.46#ibcon#about to read 4, iclass 29, count 0 2006.224.08:19:11.46#ibcon#read 4, iclass 29, count 0 2006.224.08:19:11.46#ibcon#about to read 5, iclass 29, count 0 2006.224.08:19:11.46#ibcon#read 5, iclass 29, count 0 2006.224.08:19:11.46#ibcon#about to read 6, iclass 29, count 0 2006.224.08:19:11.46#ibcon#read 6, iclass 29, count 0 2006.224.08:19:11.46#ibcon#end of sib2, iclass 29, count 0 2006.224.08:19:11.46#ibcon#*mode == 0, iclass 29, count 0 2006.224.08:19:11.46#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.224.08:19:11.46#ibcon#[28=FRQ=04,712.99\r\n] 2006.224.08:19:11.46#ibcon#*before write, iclass 29, count 0 2006.224.08:19:11.46#ibcon#enter sib2, iclass 29, count 0 2006.224.08:19:11.46#ibcon#flushed, iclass 29, count 0 2006.224.08:19:11.46#ibcon#about to write, iclass 29, count 0 2006.224.08:19:11.46#ibcon#wrote, iclass 29, count 0 2006.224.08:19:11.46#ibcon#about to read 3, iclass 29, count 0 2006.224.08:19:11.50#ibcon#read 3, iclass 29, count 0 2006.224.08:19:11.50#ibcon#about to read 4, iclass 29, count 0 2006.224.08:19:11.50#ibcon#read 4, iclass 29, count 0 2006.224.08:19:11.50#ibcon#about to read 5, iclass 29, count 0 2006.224.08:19:11.50#ibcon#read 5, iclass 29, count 0 2006.224.08:19:11.50#ibcon#about to read 6, iclass 29, count 0 2006.224.08:19:11.50#ibcon#read 6, iclass 29, count 0 2006.224.08:19:11.50#ibcon#end of sib2, iclass 29, count 0 2006.224.08:19:11.50#ibcon#*after write, iclass 29, count 0 2006.224.08:19:11.50#ibcon#*before return 0, iclass 29, count 0 2006.224.08:19:11.50#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.224.08:19:11.50#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.224.08:19:11.50#ibcon#about to clear, iclass 29 cls_cnt 0 2006.224.08:19:11.50#ibcon#cleared, iclass 29 cls_cnt 0 2006.224.08:19:11.50$vc4f8/vb=4,4 2006.224.08:19:11.50#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.224.08:19:11.50#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.224.08:19:11.51#ibcon#ireg 11 cls_cnt 2 2006.224.08:19:11.51#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.224.08:19:11.55#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.224.08:19:11.55#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.224.08:19:11.55#ibcon#enter wrdev, iclass 31, count 2 2006.224.08:19:11.55#ibcon#first serial, iclass 31, count 2 2006.224.08:19:11.55#ibcon#enter sib2, iclass 31, count 2 2006.224.08:19:11.55#ibcon#flushed, iclass 31, count 2 2006.224.08:19:11.55#ibcon#about to write, iclass 31, count 2 2006.224.08:19:11.55#ibcon#wrote, iclass 31, count 2 2006.224.08:19:11.55#ibcon#about to read 3, iclass 31, count 2 2006.224.08:19:11.57#ibcon#read 3, iclass 31, count 2 2006.224.08:19:11.57#ibcon#about to read 4, iclass 31, count 2 2006.224.08:19:11.57#ibcon#read 4, iclass 31, count 2 2006.224.08:19:11.57#ibcon#about to read 5, iclass 31, count 2 2006.224.08:19:11.57#ibcon#read 5, iclass 31, count 2 2006.224.08:19:11.57#ibcon#about to read 6, iclass 31, count 2 2006.224.08:19:11.57#ibcon#read 6, iclass 31, count 2 2006.224.08:19:11.57#ibcon#end of sib2, iclass 31, count 2 2006.224.08:19:11.57#ibcon#*mode == 0, iclass 31, count 2 2006.224.08:19:11.57#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.224.08:19:11.57#ibcon#[27=AT04-04\r\n] 2006.224.08:19:11.57#ibcon#*before write, iclass 31, count 2 2006.224.08:19:11.57#ibcon#enter sib2, iclass 31, count 2 2006.224.08:19:11.57#ibcon#flushed, iclass 31, count 2 2006.224.08:19:11.57#ibcon#about to write, iclass 31, count 2 2006.224.08:19:11.57#ibcon#wrote, iclass 31, count 2 2006.224.08:19:11.57#ibcon#about to read 3, iclass 31, count 2 2006.224.08:19:11.60#ibcon#read 3, iclass 31, count 2 2006.224.08:19:11.60#ibcon#about to read 4, iclass 31, count 2 2006.224.08:19:11.60#ibcon#read 4, iclass 31, count 2 2006.224.08:19:11.60#ibcon#about to read 5, iclass 31, count 2 2006.224.08:19:11.60#ibcon#read 5, iclass 31, count 2 2006.224.08:19:11.60#ibcon#about to read 6, iclass 31, count 2 2006.224.08:19:11.60#ibcon#read 6, iclass 31, count 2 2006.224.08:19:11.60#ibcon#end of sib2, iclass 31, count 2 2006.224.08:19:11.60#ibcon#*after write, iclass 31, count 2 2006.224.08:19:11.60#ibcon#*before return 0, iclass 31, count 2 2006.224.08:19:11.60#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.224.08:19:11.60#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.224.08:19:11.60#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.224.08:19:11.60#ibcon#ireg 7 cls_cnt 0 2006.224.08:19:11.60#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.224.08:19:11.72#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.224.08:19:11.72#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.224.08:19:11.72#ibcon#enter wrdev, iclass 31, count 0 2006.224.08:19:11.72#ibcon#first serial, iclass 31, count 0 2006.224.08:19:11.72#ibcon#enter sib2, iclass 31, count 0 2006.224.08:19:11.72#ibcon#flushed, iclass 31, count 0 2006.224.08:19:11.72#ibcon#about to write, iclass 31, count 0 2006.224.08:19:11.72#ibcon#wrote, iclass 31, count 0 2006.224.08:19:11.72#ibcon#about to read 3, iclass 31, count 0 2006.224.08:19:11.74#ibcon#read 3, iclass 31, count 0 2006.224.08:19:11.74#ibcon#about to read 4, iclass 31, count 0 2006.224.08:19:11.74#ibcon#read 4, iclass 31, count 0 2006.224.08:19:11.74#ibcon#about to read 5, iclass 31, count 0 2006.224.08:19:11.74#ibcon#read 5, iclass 31, count 0 2006.224.08:19:11.74#ibcon#about to read 6, iclass 31, count 0 2006.224.08:19:11.74#ibcon#read 6, iclass 31, count 0 2006.224.08:19:11.74#ibcon#end of sib2, iclass 31, count 0 2006.224.08:19:11.74#ibcon#*mode == 0, iclass 31, count 0 2006.224.08:19:11.74#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.224.08:19:11.74#ibcon#[27=USB\r\n] 2006.224.08:19:11.74#ibcon#*before write, iclass 31, count 0 2006.224.08:19:11.74#ibcon#enter sib2, iclass 31, count 0 2006.224.08:19:11.74#ibcon#flushed, iclass 31, count 0 2006.224.08:19:11.74#ibcon#about to write, iclass 31, count 0 2006.224.08:19:11.74#ibcon#wrote, iclass 31, count 0 2006.224.08:19:11.74#ibcon#about to read 3, iclass 31, count 0 2006.224.08:19:11.77#ibcon#read 3, iclass 31, count 0 2006.224.08:19:11.77#ibcon#about to read 4, iclass 31, count 0 2006.224.08:19:11.77#ibcon#read 4, iclass 31, count 0 2006.224.08:19:11.77#ibcon#about to read 5, iclass 31, count 0 2006.224.08:19:11.77#ibcon#read 5, iclass 31, count 0 2006.224.08:19:11.77#ibcon#about to read 6, iclass 31, count 0 2006.224.08:19:11.77#ibcon#read 6, iclass 31, count 0 2006.224.08:19:11.77#ibcon#end of sib2, iclass 31, count 0 2006.224.08:19:11.77#ibcon#*after write, iclass 31, count 0 2006.224.08:19:11.77#ibcon#*before return 0, iclass 31, count 0 2006.224.08:19:11.77#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.224.08:19:11.77#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.224.08:19:11.77#ibcon#about to clear, iclass 31 cls_cnt 0 2006.224.08:19:11.77#ibcon#cleared, iclass 31 cls_cnt 0 2006.224.08:19:11.77$vc4f8/vblo=5,744.99 2006.224.08:19:11.77#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.224.08:19:11.77#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.224.08:19:11.77#ibcon#ireg 17 cls_cnt 0 2006.224.08:19:11.77#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.224.08:19:11.77#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.224.08:19:11.78#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.224.08:19:11.78#ibcon#enter wrdev, iclass 33, count 0 2006.224.08:19:11.78#ibcon#first serial, iclass 33, count 0 2006.224.08:19:11.78#ibcon#enter sib2, iclass 33, count 0 2006.224.08:19:11.78#ibcon#flushed, iclass 33, count 0 2006.224.08:19:11.78#ibcon#about to write, iclass 33, count 0 2006.224.08:19:11.78#ibcon#wrote, iclass 33, count 0 2006.224.08:19:11.78#ibcon#about to read 3, iclass 33, count 0 2006.224.08:19:11.79#ibcon#read 3, iclass 33, count 0 2006.224.08:19:11.79#ibcon#about to read 4, iclass 33, count 0 2006.224.08:19:11.79#ibcon#read 4, iclass 33, count 0 2006.224.08:19:11.79#ibcon#about to read 5, iclass 33, count 0 2006.224.08:19:11.79#ibcon#read 5, iclass 33, count 0 2006.224.08:19:11.79#ibcon#about to read 6, iclass 33, count 0 2006.224.08:19:11.79#ibcon#read 6, iclass 33, count 0 2006.224.08:19:11.79#ibcon#end of sib2, iclass 33, count 0 2006.224.08:19:11.79#ibcon#*mode == 0, iclass 33, count 0 2006.224.08:19:11.79#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.224.08:19:11.79#ibcon#[28=FRQ=05,744.99\r\n] 2006.224.08:19:11.79#ibcon#*before write, iclass 33, count 0 2006.224.08:19:11.79#ibcon#enter sib2, iclass 33, count 0 2006.224.08:19:11.79#ibcon#flushed, iclass 33, count 0 2006.224.08:19:11.79#ibcon#about to write, iclass 33, count 0 2006.224.08:19:11.79#ibcon#wrote, iclass 33, count 0 2006.224.08:19:11.79#ibcon#about to read 3, iclass 33, count 0 2006.224.08:19:11.83#ibcon#read 3, iclass 33, count 0 2006.224.08:19:11.83#ibcon#about to read 4, iclass 33, count 0 2006.224.08:19:11.83#ibcon#read 4, iclass 33, count 0 2006.224.08:19:11.83#ibcon#about to read 5, iclass 33, count 0 2006.224.08:19:11.83#ibcon#read 5, iclass 33, count 0 2006.224.08:19:11.83#ibcon#about to read 6, iclass 33, count 0 2006.224.08:19:11.83#ibcon#read 6, iclass 33, count 0 2006.224.08:19:11.83#ibcon#end of sib2, iclass 33, count 0 2006.224.08:19:11.83#ibcon#*after write, iclass 33, count 0 2006.224.08:19:11.83#ibcon#*before return 0, iclass 33, count 0 2006.224.08:19:11.83#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.224.08:19:11.83#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.224.08:19:11.83#ibcon#about to clear, iclass 33 cls_cnt 0 2006.224.08:19:11.83#ibcon#cleared, iclass 33 cls_cnt 0 2006.224.08:19:11.83$vc4f8/vb=5,4 2006.224.08:19:11.83#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.224.08:19:11.83#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.224.08:19:11.84#ibcon#ireg 11 cls_cnt 2 2006.224.08:19:11.84#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.224.08:19:11.88#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.224.08:19:11.88#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.224.08:19:11.88#ibcon#enter wrdev, iclass 35, count 2 2006.224.08:19:11.88#ibcon#first serial, iclass 35, count 2 2006.224.08:19:11.88#ibcon#enter sib2, iclass 35, count 2 2006.224.08:19:11.88#ibcon#flushed, iclass 35, count 2 2006.224.08:19:11.88#ibcon#about to write, iclass 35, count 2 2006.224.08:19:11.88#ibcon#wrote, iclass 35, count 2 2006.224.08:19:11.88#ibcon#about to read 3, iclass 35, count 2 2006.224.08:19:11.90#ibcon#read 3, iclass 35, count 2 2006.224.08:19:11.90#ibcon#about to read 4, iclass 35, count 2 2006.224.08:19:11.90#ibcon#read 4, iclass 35, count 2 2006.224.08:19:11.90#ibcon#about to read 5, iclass 35, count 2 2006.224.08:19:11.90#ibcon#read 5, iclass 35, count 2 2006.224.08:19:11.90#ibcon#about to read 6, iclass 35, count 2 2006.224.08:19:11.90#ibcon#read 6, iclass 35, count 2 2006.224.08:19:11.90#ibcon#end of sib2, iclass 35, count 2 2006.224.08:19:11.90#ibcon#*mode == 0, iclass 35, count 2 2006.224.08:19:11.90#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.224.08:19:11.90#ibcon#[27=AT05-04\r\n] 2006.224.08:19:11.90#ibcon#*before write, iclass 35, count 2 2006.224.08:19:11.90#ibcon#enter sib2, iclass 35, count 2 2006.224.08:19:11.90#ibcon#flushed, iclass 35, count 2 2006.224.08:19:11.90#ibcon#about to write, iclass 35, count 2 2006.224.08:19:11.90#ibcon#wrote, iclass 35, count 2 2006.224.08:19:11.90#ibcon#about to read 3, iclass 35, count 2 2006.224.08:19:11.93#ibcon#read 3, iclass 35, count 2 2006.224.08:19:11.93#ibcon#about to read 4, iclass 35, count 2 2006.224.08:19:11.93#ibcon#read 4, iclass 35, count 2 2006.224.08:19:11.93#ibcon#about to read 5, iclass 35, count 2 2006.224.08:19:11.93#ibcon#read 5, iclass 35, count 2 2006.224.08:19:11.93#ibcon#about to read 6, iclass 35, count 2 2006.224.08:19:11.93#ibcon#read 6, iclass 35, count 2 2006.224.08:19:11.93#ibcon#end of sib2, iclass 35, count 2 2006.224.08:19:11.93#ibcon#*after write, iclass 35, count 2 2006.224.08:19:11.93#ibcon#*before return 0, iclass 35, count 2 2006.224.08:19:11.93#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.224.08:19:11.93#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.224.08:19:11.93#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.224.08:19:11.93#ibcon#ireg 7 cls_cnt 0 2006.224.08:19:11.93#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.224.08:19:12.05#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.224.08:19:12.05#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.224.08:19:12.05#ibcon#enter wrdev, iclass 35, count 0 2006.224.08:19:12.05#ibcon#first serial, iclass 35, count 0 2006.224.08:19:12.05#ibcon#enter sib2, iclass 35, count 0 2006.224.08:19:12.05#ibcon#flushed, iclass 35, count 0 2006.224.08:19:12.05#ibcon#about to write, iclass 35, count 0 2006.224.08:19:12.05#ibcon#wrote, iclass 35, count 0 2006.224.08:19:12.05#ibcon#about to read 3, iclass 35, count 0 2006.224.08:19:12.07#ibcon#read 3, iclass 35, count 0 2006.224.08:19:12.07#ibcon#about to read 4, iclass 35, count 0 2006.224.08:19:12.07#ibcon#read 4, iclass 35, count 0 2006.224.08:19:12.07#ibcon#about to read 5, iclass 35, count 0 2006.224.08:19:12.07#ibcon#read 5, iclass 35, count 0 2006.224.08:19:12.07#ibcon#about to read 6, iclass 35, count 0 2006.224.08:19:12.07#ibcon#read 6, iclass 35, count 0 2006.224.08:19:12.07#ibcon#end of sib2, iclass 35, count 0 2006.224.08:19:12.07#ibcon#*mode == 0, iclass 35, count 0 2006.224.08:19:12.07#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.224.08:19:12.07#ibcon#[27=USB\r\n] 2006.224.08:19:12.07#ibcon#*before write, iclass 35, count 0 2006.224.08:19:12.07#ibcon#enter sib2, iclass 35, count 0 2006.224.08:19:12.07#ibcon#flushed, iclass 35, count 0 2006.224.08:19:12.07#ibcon#about to write, iclass 35, count 0 2006.224.08:19:12.07#ibcon#wrote, iclass 35, count 0 2006.224.08:19:12.07#ibcon#about to read 3, iclass 35, count 0 2006.224.08:19:12.10#ibcon#read 3, iclass 35, count 0 2006.224.08:19:12.10#ibcon#about to read 4, iclass 35, count 0 2006.224.08:19:12.10#ibcon#read 4, iclass 35, count 0 2006.224.08:19:12.10#ibcon#about to read 5, iclass 35, count 0 2006.224.08:19:12.10#ibcon#read 5, iclass 35, count 0 2006.224.08:19:12.10#ibcon#about to read 6, iclass 35, count 0 2006.224.08:19:12.10#ibcon#read 6, iclass 35, count 0 2006.224.08:19:12.10#ibcon#end of sib2, iclass 35, count 0 2006.224.08:19:12.10#ibcon#*after write, iclass 35, count 0 2006.224.08:19:12.10#ibcon#*before return 0, iclass 35, count 0 2006.224.08:19:12.10#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.224.08:19:12.10#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.224.08:19:12.10#ibcon#about to clear, iclass 35 cls_cnt 0 2006.224.08:19:12.10#ibcon#cleared, iclass 35 cls_cnt 0 2006.224.08:19:12.10$vc4f8/vblo=6,752.99 2006.224.08:19:12.11#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.224.08:19:12.11#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.224.08:19:12.11#ibcon#ireg 17 cls_cnt 0 2006.224.08:19:12.11#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.224.08:19:12.11#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.224.08:19:12.11#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.224.08:19:12.11#ibcon#enter wrdev, iclass 37, count 0 2006.224.08:19:12.11#ibcon#first serial, iclass 37, count 0 2006.224.08:19:12.11#ibcon#enter sib2, iclass 37, count 0 2006.224.08:19:12.11#ibcon#flushed, iclass 37, count 0 2006.224.08:19:12.11#ibcon#about to write, iclass 37, count 0 2006.224.08:19:12.11#ibcon#wrote, iclass 37, count 0 2006.224.08:19:12.11#ibcon#about to read 3, iclass 37, count 0 2006.224.08:19:12.12#ibcon#read 3, iclass 37, count 0 2006.224.08:19:12.12#ibcon#about to read 4, iclass 37, count 0 2006.224.08:19:12.12#ibcon#read 4, iclass 37, count 0 2006.224.08:19:12.12#ibcon#about to read 5, iclass 37, count 0 2006.224.08:19:12.12#ibcon#read 5, iclass 37, count 0 2006.224.08:19:12.12#ibcon#about to read 6, iclass 37, count 0 2006.224.08:19:12.12#ibcon#read 6, iclass 37, count 0 2006.224.08:19:12.12#ibcon#end of sib2, iclass 37, count 0 2006.224.08:19:12.12#ibcon#*mode == 0, iclass 37, count 0 2006.224.08:19:12.12#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.224.08:19:12.12#ibcon#[28=FRQ=06,752.99\r\n] 2006.224.08:19:12.12#ibcon#*before write, iclass 37, count 0 2006.224.08:19:12.12#ibcon#enter sib2, iclass 37, count 0 2006.224.08:19:12.12#ibcon#flushed, iclass 37, count 0 2006.224.08:19:12.12#ibcon#about to write, iclass 37, count 0 2006.224.08:19:12.12#ibcon#wrote, iclass 37, count 0 2006.224.08:19:12.12#ibcon#about to read 3, iclass 37, count 0 2006.224.08:19:12.17#ibcon#read 3, iclass 37, count 0 2006.224.08:19:12.17#ibcon#about to read 4, iclass 37, count 0 2006.224.08:19:12.17#ibcon#read 4, iclass 37, count 0 2006.224.08:19:12.17#ibcon#about to read 5, iclass 37, count 0 2006.224.08:19:12.17#ibcon#read 5, iclass 37, count 0 2006.224.08:19:12.17#ibcon#about to read 6, iclass 37, count 0 2006.224.08:19:12.17#ibcon#read 6, iclass 37, count 0 2006.224.08:19:12.17#ibcon#end of sib2, iclass 37, count 0 2006.224.08:19:12.17#ibcon#*after write, iclass 37, count 0 2006.224.08:19:12.17#ibcon#*before return 0, iclass 37, count 0 2006.224.08:19:12.17#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.224.08:19:12.17#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.224.08:19:12.17#ibcon#about to clear, iclass 37 cls_cnt 0 2006.224.08:19:12.17#ibcon#cleared, iclass 37 cls_cnt 0 2006.224.08:19:12.17$vc4f8/vb=6,4 2006.224.08:19:12.17#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.224.08:19:12.17#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.224.08:19:12.17#ibcon#ireg 11 cls_cnt 2 2006.224.08:19:12.17#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.224.08:19:12.21#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.224.08:19:12.21#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.224.08:19:12.21#ibcon#enter wrdev, iclass 39, count 2 2006.224.08:19:12.21#ibcon#first serial, iclass 39, count 2 2006.224.08:19:12.21#ibcon#enter sib2, iclass 39, count 2 2006.224.08:19:12.21#ibcon#flushed, iclass 39, count 2 2006.224.08:19:12.21#ibcon#about to write, iclass 39, count 2 2006.224.08:19:12.21#ibcon#wrote, iclass 39, count 2 2006.224.08:19:12.21#ibcon#about to read 3, iclass 39, count 2 2006.224.08:19:12.23#ibcon#read 3, iclass 39, count 2 2006.224.08:19:12.23#ibcon#about to read 4, iclass 39, count 2 2006.224.08:19:12.23#ibcon#read 4, iclass 39, count 2 2006.224.08:19:12.23#ibcon#about to read 5, iclass 39, count 2 2006.224.08:19:12.23#ibcon#read 5, iclass 39, count 2 2006.224.08:19:12.23#ibcon#about to read 6, iclass 39, count 2 2006.224.08:19:12.23#ibcon#read 6, iclass 39, count 2 2006.224.08:19:12.23#ibcon#end of sib2, iclass 39, count 2 2006.224.08:19:12.23#ibcon#*mode == 0, iclass 39, count 2 2006.224.08:19:12.23#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.224.08:19:12.23#ibcon#[27=AT06-04\r\n] 2006.224.08:19:12.23#ibcon#*before write, iclass 39, count 2 2006.224.08:19:12.23#ibcon#enter sib2, iclass 39, count 2 2006.224.08:19:12.23#ibcon#flushed, iclass 39, count 2 2006.224.08:19:12.23#ibcon#about to write, iclass 39, count 2 2006.224.08:19:12.23#ibcon#wrote, iclass 39, count 2 2006.224.08:19:12.23#ibcon#about to read 3, iclass 39, count 2 2006.224.08:19:12.26#ibcon#read 3, iclass 39, count 2 2006.224.08:19:12.26#ibcon#about to read 4, iclass 39, count 2 2006.224.08:19:12.26#ibcon#read 4, iclass 39, count 2 2006.224.08:19:12.26#ibcon#about to read 5, iclass 39, count 2 2006.224.08:19:12.26#ibcon#read 5, iclass 39, count 2 2006.224.08:19:12.26#ibcon#about to read 6, iclass 39, count 2 2006.224.08:19:12.26#ibcon#read 6, iclass 39, count 2 2006.224.08:19:12.26#ibcon#end of sib2, iclass 39, count 2 2006.224.08:19:12.26#ibcon#*after write, iclass 39, count 2 2006.224.08:19:12.26#ibcon#*before return 0, iclass 39, count 2 2006.224.08:19:12.26#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.224.08:19:12.26#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.224.08:19:12.26#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.224.08:19:12.26#ibcon#ireg 7 cls_cnt 0 2006.224.08:19:12.26#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.224.08:19:12.38#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.224.08:19:12.38#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.224.08:19:12.38#ibcon#enter wrdev, iclass 39, count 0 2006.224.08:19:12.38#ibcon#first serial, iclass 39, count 0 2006.224.08:19:12.38#ibcon#enter sib2, iclass 39, count 0 2006.224.08:19:12.38#ibcon#flushed, iclass 39, count 0 2006.224.08:19:12.38#ibcon#about to write, iclass 39, count 0 2006.224.08:19:12.38#ibcon#wrote, iclass 39, count 0 2006.224.08:19:12.38#ibcon#about to read 3, iclass 39, count 0 2006.224.08:19:12.40#ibcon#read 3, iclass 39, count 0 2006.224.08:19:12.40#ibcon#about to read 4, iclass 39, count 0 2006.224.08:19:12.40#ibcon#read 4, iclass 39, count 0 2006.224.08:19:12.40#ibcon#about to read 5, iclass 39, count 0 2006.224.08:19:12.40#ibcon#read 5, iclass 39, count 0 2006.224.08:19:12.40#ibcon#about to read 6, iclass 39, count 0 2006.224.08:19:12.40#ibcon#read 6, iclass 39, count 0 2006.224.08:19:12.40#ibcon#end of sib2, iclass 39, count 0 2006.224.08:19:12.40#ibcon#*mode == 0, iclass 39, count 0 2006.224.08:19:12.40#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.224.08:19:12.40#ibcon#[27=USB\r\n] 2006.224.08:19:12.40#ibcon#*before write, iclass 39, count 0 2006.224.08:19:12.40#ibcon#enter sib2, iclass 39, count 0 2006.224.08:19:12.40#ibcon#flushed, iclass 39, count 0 2006.224.08:19:12.40#ibcon#about to write, iclass 39, count 0 2006.224.08:19:12.40#ibcon#wrote, iclass 39, count 0 2006.224.08:19:12.40#ibcon#about to read 3, iclass 39, count 0 2006.224.08:19:12.43#ibcon#read 3, iclass 39, count 0 2006.224.08:19:12.43#ibcon#about to read 4, iclass 39, count 0 2006.224.08:19:12.43#ibcon#read 4, iclass 39, count 0 2006.224.08:19:12.43#ibcon#about to read 5, iclass 39, count 0 2006.224.08:19:12.43#ibcon#read 5, iclass 39, count 0 2006.224.08:19:12.43#ibcon#about to read 6, iclass 39, count 0 2006.224.08:19:12.43#ibcon#read 6, iclass 39, count 0 2006.224.08:19:12.43#ibcon#end of sib2, iclass 39, count 0 2006.224.08:19:12.43#ibcon#*after write, iclass 39, count 0 2006.224.08:19:12.43#ibcon#*before return 0, iclass 39, count 0 2006.224.08:19:12.43#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.224.08:19:12.43#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.224.08:19:12.43#ibcon#about to clear, iclass 39 cls_cnt 0 2006.224.08:19:12.43#ibcon#cleared, iclass 39 cls_cnt 0 2006.224.08:19:12.43$vc4f8/vabw=wide 2006.224.08:19:12.43#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.224.08:19:12.43#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.224.08:19:12.43#ibcon#ireg 8 cls_cnt 0 2006.224.08:19:12.43#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.224.08:19:12.43#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.224.08:19:12.43#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.224.08:19:12.44#ibcon#enter wrdev, iclass 3, count 0 2006.224.08:19:12.44#ibcon#first serial, iclass 3, count 0 2006.224.08:19:12.44#ibcon#enter sib2, iclass 3, count 0 2006.224.08:19:12.44#ibcon#flushed, iclass 3, count 0 2006.224.08:19:12.44#ibcon#about to write, iclass 3, count 0 2006.224.08:19:12.44#ibcon#wrote, iclass 3, count 0 2006.224.08:19:12.44#ibcon#about to read 3, iclass 3, count 0 2006.224.08:19:12.45#ibcon#read 3, iclass 3, count 0 2006.224.08:19:12.45#ibcon#about to read 4, iclass 3, count 0 2006.224.08:19:12.45#ibcon#read 4, iclass 3, count 0 2006.224.08:19:12.45#ibcon#about to read 5, iclass 3, count 0 2006.224.08:19:12.45#ibcon#read 5, iclass 3, count 0 2006.224.08:19:12.45#ibcon#about to read 6, iclass 3, count 0 2006.224.08:19:12.45#ibcon#read 6, iclass 3, count 0 2006.224.08:19:12.45#ibcon#end of sib2, iclass 3, count 0 2006.224.08:19:12.45#ibcon#*mode == 0, iclass 3, count 0 2006.224.08:19:12.45#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.224.08:19:12.45#ibcon#[25=BW32\r\n] 2006.224.08:19:12.45#ibcon#*before write, iclass 3, count 0 2006.224.08:19:12.45#ibcon#enter sib2, iclass 3, count 0 2006.224.08:19:12.45#ibcon#flushed, iclass 3, count 0 2006.224.08:19:12.45#ibcon#about to write, iclass 3, count 0 2006.224.08:19:12.45#ibcon#wrote, iclass 3, count 0 2006.224.08:19:12.45#ibcon#about to read 3, iclass 3, count 0 2006.224.08:19:12.48#ibcon#read 3, iclass 3, count 0 2006.224.08:19:12.48#ibcon#about to read 4, iclass 3, count 0 2006.224.08:19:12.48#ibcon#read 4, iclass 3, count 0 2006.224.08:19:12.48#ibcon#about to read 5, iclass 3, count 0 2006.224.08:19:12.48#ibcon#read 5, iclass 3, count 0 2006.224.08:19:12.48#ibcon#about to read 6, iclass 3, count 0 2006.224.08:19:12.48#ibcon#read 6, iclass 3, count 0 2006.224.08:19:12.48#ibcon#end of sib2, iclass 3, count 0 2006.224.08:19:12.48#ibcon#*after write, iclass 3, count 0 2006.224.08:19:12.48#ibcon#*before return 0, iclass 3, count 0 2006.224.08:19:12.48#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.224.08:19:12.48#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.224.08:19:12.48#ibcon#about to clear, iclass 3 cls_cnt 0 2006.224.08:19:12.48#ibcon#cleared, iclass 3 cls_cnt 0 2006.224.08:19:12.48$vc4f8/vbbw=wide 2006.224.08:19:12.48#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.224.08:19:12.48#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.224.08:19:12.48#ibcon#ireg 8 cls_cnt 0 2006.224.08:19:12.49#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.224.08:19:12.54#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.224.08:19:12.54#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.224.08:19:12.54#ibcon#enter wrdev, iclass 5, count 0 2006.224.08:19:12.54#ibcon#first serial, iclass 5, count 0 2006.224.08:19:12.54#ibcon#enter sib2, iclass 5, count 0 2006.224.08:19:12.54#ibcon#flushed, iclass 5, count 0 2006.224.08:19:12.54#ibcon#about to write, iclass 5, count 0 2006.224.08:19:12.54#ibcon#wrote, iclass 5, count 0 2006.224.08:19:12.54#ibcon#about to read 3, iclass 5, count 0 2006.224.08:19:12.56#ibcon#read 3, iclass 5, count 0 2006.224.08:19:12.56#ibcon#about to read 4, iclass 5, count 0 2006.224.08:19:12.56#ibcon#read 4, iclass 5, count 0 2006.224.08:19:12.56#ibcon#about to read 5, iclass 5, count 0 2006.224.08:19:12.56#ibcon#read 5, iclass 5, count 0 2006.224.08:19:12.56#ibcon#about to read 6, iclass 5, count 0 2006.224.08:19:12.56#ibcon#read 6, iclass 5, count 0 2006.224.08:19:12.56#ibcon#end of sib2, iclass 5, count 0 2006.224.08:19:12.56#ibcon#*mode == 0, iclass 5, count 0 2006.224.08:19:12.56#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.224.08:19:12.56#ibcon#[27=BW32\r\n] 2006.224.08:19:12.56#ibcon#*before write, iclass 5, count 0 2006.224.08:19:12.56#ibcon#enter sib2, iclass 5, count 0 2006.224.08:19:12.56#ibcon#flushed, iclass 5, count 0 2006.224.08:19:12.56#ibcon#about to write, iclass 5, count 0 2006.224.08:19:12.56#ibcon#wrote, iclass 5, count 0 2006.224.08:19:12.56#ibcon#about to read 3, iclass 5, count 0 2006.224.08:19:12.59#ibcon#read 3, iclass 5, count 0 2006.224.08:19:12.59#ibcon#about to read 4, iclass 5, count 0 2006.224.08:19:12.59#ibcon#read 4, iclass 5, count 0 2006.224.08:19:12.59#ibcon#about to read 5, iclass 5, count 0 2006.224.08:19:12.59#ibcon#read 5, iclass 5, count 0 2006.224.08:19:12.59#ibcon#about to read 6, iclass 5, count 0 2006.224.08:19:12.59#ibcon#read 6, iclass 5, count 0 2006.224.08:19:12.59#ibcon#end of sib2, iclass 5, count 0 2006.224.08:19:12.59#ibcon#*after write, iclass 5, count 0 2006.224.08:19:12.59#ibcon#*before return 0, iclass 5, count 0 2006.224.08:19:12.59#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.224.08:19:12.59#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.224.08:19:12.59#ibcon#about to clear, iclass 5 cls_cnt 0 2006.224.08:19:12.59#ibcon#cleared, iclass 5 cls_cnt 0 2006.224.08:19:12.59$4f8m12a/ifd4f 2006.224.08:19:12.60$ifd4f/lo= 2006.224.08:19:12.60$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.224.08:19:12.60$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.224.08:19:12.60$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.224.08:19:12.60$ifd4f/patch= 2006.224.08:19:12.60$ifd4f/patch=lo1,a1,a2,a3,a4 2006.224.08:19:12.60$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.224.08:19:12.60$ifd4f/patch=lo3,a5,a6,a7,a8 2006.224.08:19:12.60$4f8m12a/"form=m,16.000,1:2 2006.224.08:19:12.60$4f8m12a/"tpicd 2006.224.08:19:12.60$4f8m12a/echo=off 2006.224.08:19:12.60$4f8m12a/xlog=off 2006.224.08:19:12.60:!2006.224.08:20:40 2006.224.08:19:48.13#trakl#Source acquired 2006.224.08:19:49.13#flagr#flagr/antenna,acquired 2006.224.08:20:40.01:preob 2006.224.08:20:41.13/onsource/TRACKING 2006.224.08:20:41.13:!2006.224.08:20:50 2006.224.08:20:50.00:data_valid=on 2006.224.08:20:50.00:midob 2006.224.08:20:50.14/onsource/TRACKING 2006.224.08:20:50.15/wx/23.82,1004.7,100 2006.224.08:20:50.33/cable/+6.4338E-03 2006.224.08:20:51.42/va/01,08,usb,yes,42,44 2006.224.08:20:51.42/va/02,07,usb,yes,43,44 2006.224.08:20:51.42/va/03,06,usb,yes,45,45 2006.224.08:20:51.42/va/04,07,usb,yes,44,48 2006.224.08:20:51.42/va/05,07,usb,yes,52,55 2006.224.08:20:51.42/va/06,06,usb,yes,51,51 2006.224.08:20:51.42/va/07,06,usb,yes,52,52 2006.224.08:20:51.42/va/08,07,usb,yes,50,49 2006.224.08:20:51.65/valo/01,532.99,yes,locked 2006.224.08:20:51.65/valo/02,572.99,yes,locked 2006.224.08:20:51.65/valo/03,672.99,yes,locked 2006.224.08:20:51.65/valo/04,832.99,yes,locked 2006.224.08:20:51.65/valo/05,652.99,yes,locked 2006.224.08:20:51.65/valo/06,772.99,yes,locked 2006.224.08:20:51.65/valo/07,832.99,yes,locked 2006.224.08:20:51.65/valo/08,852.99,yes,locked 2006.224.08:20:52.74/vb/01,04,usb,yes,32,31 2006.224.08:20:52.74/vb/02,04,usb,yes,34,35 2006.224.08:20:52.74/vb/03,04,usb,yes,30,34 2006.224.08:20:52.74/vb/04,04,usb,yes,31,31 2006.224.08:20:52.74/vb/05,04,usb,yes,30,34 2006.224.08:20:52.74/vb/06,04,usb,yes,31,34 2006.224.08:20:52.74/vb/07,04,usb,yes,33,33 2006.224.08:20:52.74/vb/08,04,usb,yes,30,34 2006.224.08:20:52.97/vblo/01,632.99,yes,locked 2006.224.08:20:52.97/vblo/02,640.99,yes,locked 2006.224.08:20:52.97/vblo/03,656.99,yes,locked 2006.224.08:20:52.97/vblo/04,712.99,yes,locked 2006.224.08:20:52.97/vblo/05,744.99,yes,locked 2006.224.08:20:52.97/vblo/06,752.99,yes,locked 2006.224.08:20:52.97/vblo/07,734.99,yes,locked 2006.224.08:20:52.97/vblo/08,744.99,yes,locked 2006.224.08:20:53.12/vabw/8 2006.224.08:20:53.27/vbbw/8 2006.224.08:20:53.48/xfe/off,on,16.0 2006.224.08:20:53.87/ifatt/23,28,28,28 2006.224.08:20:54.07/fmout-gps/S +4.51E-07 2006.224.08:20:54.12:!2006.224.08:21:50 2006.224.08:21:50.01:data_valid=off 2006.224.08:21:50.01:postob 2006.224.08:21:50.14/cable/+6.4328E-03 2006.224.08:21:50.15/wx/23.82,1004.7,100 2006.224.08:21:51.08/fmout-gps/S +4.51E-07 2006.224.08:21:51.08:scan_name=224-0824,k06224,60 2006.224.08:21:51.08:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.224.08:21:51.14#flagr#flagr/antenna,new-source 2006.224.08:21:52.14:checkk5 2006.224.08:21:52.51/chk_autoobs//k5ts1/ autoobs is running! 2006.224.08:21:52.88/chk_autoobs//k5ts2/ autoobs is running! 2006.224.08:21:53.26/chk_autoobs//k5ts3/ autoobs is running! 2006.224.08:21:53.63/chk_autoobs//k5ts4/ autoobs is running! 2006.224.08:21:53.99/chk_obsdata//k5ts1/T2240820??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.08:21:54.36/chk_obsdata//k5ts2/T2240820??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.08:21:54.72/chk_obsdata//k5ts3/T2240820??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.08:21:55.08/chk_obsdata//k5ts4/T2240820??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.08:21:55.77/k5log//k5ts1_log_newline 2006.224.08:21:56.45/k5log//k5ts2_log_newline 2006.224.08:21:57.14/k5log//k5ts3_log_newline 2006.224.08:21:57.82/k5log//k5ts4_log_newline 2006.224.08:21:57.84/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.224.08:21:57.84:4f8m12a=3 2006.224.08:21:57.85$4f8m12a/echo=on 2006.224.08:21:57.85$4f8m12a/pcalon 2006.224.08:21:57.85$pcalon/"no phase cal control is implemented here 2006.224.08:21:57.85$4f8m12a/"tpicd=stop 2006.224.08:21:57.85$4f8m12a/vc4f8 2006.224.08:21:57.85$vc4f8/valo=1,532.99 2006.224.08:21:57.85#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.224.08:21:57.85#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.224.08:21:57.85#ibcon#ireg 17 cls_cnt 0 2006.224.08:21:57.85#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.224.08:21:57.85#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.224.08:21:57.85#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.224.08:21:57.85#ibcon#enter wrdev, iclass 33, count 0 2006.224.08:21:57.85#ibcon#first serial, iclass 33, count 0 2006.224.08:21:57.85#ibcon#enter sib2, iclass 33, count 0 2006.224.08:21:57.85#ibcon#flushed, iclass 33, count 0 2006.224.08:21:57.85#ibcon#about to write, iclass 33, count 0 2006.224.08:21:57.85#ibcon#wrote, iclass 33, count 0 2006.224.08:21:57.85#ibcon#about to read 3, iclass 33, count 0 2006.224.08:21:57.89#ibcon#read 3, iclass 33, count 0 2006.224.08:21:57.89#ibcon#about to read 4, iclass 33, count 0 2006.224.08:21:57.89#ibcon#read 4, iclass 33, count 0 2006.224.08:21:57.89#ibcon#about to read 5, iclass 33, count 0 2006.224.08:21:57.89#ibcon#read 5, iclass 33, count 0 2006.224.08:21:57.89#ibcon#about to read 6, iclass 33, count 0 2006.224.08:21:57.89#ibcon#read 6, iclass 33, count 0 2006.224.08:21:57.89#ibcon#end of sib2, iclass 33, count 0 2006.224.08:21:57.89#ibcon#*mode == 0, iclass 33, count 0 2006.224.08:21:57.89#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.224.08:21:57.89#ibcon#[26=FRQ=01,532.99\r\n] 2006.224.08:21:57.89#ibcon#*before write, iclass 33, count 0 2006.224.08:21:57.89#ibcon#enter sib2, iclass 33, count 0 2006.224.08:21:57.89#ibcon#flushed, iclass 33, count 0 2006.224.08:21:57.89#ibcon#about to write, iclass 33, count 0 2006.224.08:21:57.89#ibcon#wrote, iclass 33, count 0 2006.224.08:21:57.89#ibcon#about to read 3, iclass 33, count 0 2006.224.08:21:57.93#ibcon#read 3, iclass 33, count 0 2006.224.08:21:57.93#ibcon#about to read 4, iclass 33, count 0 2006.224.08:21:57.93#ibcon#read 4, iclass 33, count 0 2006.224.08:21:57.93#ibcon#about to read 5, iclass 33, count 0 2006.224.08:21:57.93#ibcon#read 5, iclass 33, count 0 2006.224.08:21:57.93#ibcon#about to read 6, iclass 33, count 0 2006.224.08:21:57.93#ibcon#read 6, iclass 33, count 0 2006.224.08:21:57.93#ibcon#end of sib2, iclass 33, count 0 2006.224.08:21:57.93#ibcon#*after write, iclass 33, count 0 2006.224.08:21:57.93#ibcon#*before return 0, iclass 33, count 0 2006.224.08:21:57.93#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.224.08:21:57.93#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.224.08:21:57.93#ibcon#about to clear, iclass 33 cls_cnt 0 2006.224.08:21:57.93#ibcon#cleared, iclass 33 cls_cnt 0 2006.224.08:21:57.93$vc4f8/va=1,8 2006.224.08:21:57.93#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.224.08:21:57.93#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.224.08:21:57.93#ibcon#ireg 11 cls_cnt 2 2006.224.08:21:57.93#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.224.08:21:57.93#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.224.08:21:57.93#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.224.08:21:57.93#ibcon#enter wrdev, iclass 35, count 2 2006.224.08:21:57.93#ibcon#first serial, iclass 35, count 2 2006.224.08:21:57.93#ibcon#enter sib2, iclass 35, count 2 2006.224.08:21:57.93#ibcon#flushed, iclass 35, count 2 2006.224.08:21:57.93#ibcon#about to write, iclass 35, count 2 2006.224.08:21:57.93#ibcon#wrote, iclass 35, count 2 2006.224.08:21:57.93#ibcon#about to read 3, iclass 35, count 2 2006.224.08:21:57.95#ibcon#read 3, iclass 35, count 2 2006.224.08:21:57.95#ibcon#about to read 4, iclass 35, count 2 2006.224.08:21:57.95#ibcon#read 4, iclass 35, count 2 2006.224.08:21:57.95#ibcon#about to read 5, iclass 35, count 2 2006.224.08:21:57.95#ibcon#read 5, iclass 35, count 2 2006.224.08:21:57.95#ibcon#about to read 6, iclass 35, count 2 2006.224.08:21:57.95#ibcon#read 6, iclass 35, count 2 2006.224.08:21:57.95#ibcon#end of sib2, iclass 35, count 2 2006.224.08:21:57.95#ibcon#*mode == 0, iclass 35, count 2 2006.224.08:21:57.95#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.224.08:21:57.95#ibcon#[25=AT01-08\r\n] 2006.224.08:21:57.95#ibcon#*before write, iclass 35, count 2 2006.224.08:21:57.95#ibcon#enter sib2, iclass 35, count 2 2006.224.08:21:57.95#ibcon#flushed, iclass 35, count 2 2006.224.08:21:57.95#ibcon#about to write, iclass 35, count 2 2006.224.08:21:57.95#ibcon#wrote, iclass 35, count 2 2006.224.08:21:57.95#ibcon#about to read 3, iclass 35, count 2 2006.224.08:21:57.99#ibcon#read 3, iclass 35, count 2 2006.224.08:21:57.99#ibcon#about to read 4, iclass 35, count 2 2006.224.08:21:57.99#ibcon#read 4, iclass 35, count 2 2006.224.08:21:57.99#ibcon#about to read 5, iclass 35, count 2 2006.224.08:21:57.99#ibcon#read 5, iclass 35, count 2 2006.224.08:21:57.99#ibcon#about to read 6, iclass 35, count 2 2006.224.08:21:57.99#ibcon#read 6, iclass 35, count 2 2006.224.08:21:57.99#ibcon#end of sib2, iclass 35, count 2 2006.224.08:21:57.99#ibcon#*after write, iclass 35, count 2 2006.224.08:21:57.99#ibcon#*before return 0, iclass 35, count 2 2006.224.08:21:57.99#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.224.08:21:57.99#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.224.08:21:57.99#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.224.08:21:57.99#ibcon#ireg 7 cls_cnt 0 2006.224.08:21:57.99#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.224.08:21:58.11#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.224.08:21:58.11#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.224.08:21:58.11#ibcon#enter wrdev, iclass 35, count 0 2006.224.08:21:58.11#ibcon#first serial, iclass 35, count 0 2006.224.08:21:58.11#ibcon#enter sib2, iclass 35, count 0 2006.224.08:21:58.11#ibcon#flushed, iclass 35, count 0 2006.224.08:21:58.11#ibcon#about to write, iclass 35, count 0 2006.224.08:21:58.11#ibcon#wrote, iclass 35, count 0 2006.224.08:21:58.11#ibcon#about to read 3, iclass 35, count 0 2006.224.08:21:58.12#ibcon#read 3, iclass 35, count 0 2006.224.08:21:58.12#ibcon#about to read 4, iclass 35, count 0 2006.224.08:21:58.12#ibcon#read 4, iclass 35, count 0 2006.224.08:21:58.12#ibcon#about to read 5, iclass 35, count 0 2006.224.08:21:58.12#ibcon#read 5, iclass 35, count 0 2006.224.08:21:58.12#ibcon#about to read 6, iclass 35, count 0 2006.224.08:21:58.12#ibcon#read 6, iclass 35, count 0 2006.224.08:21:58.12#ibcon#end of sib2, iclass 35, count 0 2006.224.08:21:58.12#ibcon#*mode == 0, iclass 35, count 0 2006.224.08:21:58.12#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.224.08:21:58.12#ibcon#[25=USB\r\n] 2006.224.08:21:58.12#ibcon#*before write, iclass 35, count 0 2006.224.08:21:58.12#ibcon#enter sib2, iclass 35, count 0 2006.224.08:21:58.12#ibcon#flushed, iclass 35, count 0 2006.224.08:21:58.12#ibcon#about to write, iclass 35, count 0 2006.224.08:21:58.12#ibcon#wrote, iclass 35, count 0 2006.224.08:21:58.12#ibcon#about to read 3, iclass 35, count 0 2006.224.08:21:58.15#ibcon#read 3, iclass 35, count 0 2006.224.08:21:58.15#ibcon#about to read 4, iclass 35, count 0 2006.224.08:21:58.15#ibcon#read 4, iclass 35, count 0 2006.224.08:21:58.15#ibcon#about to read 5, iclass 35, count 0 2006.224.08:21:58.15#ibcon#read 5, iclass 35, count 0 2006.224.08:21:58.15#ibcon#about to read 6, iclass 35, count 0 2006.224.08:21:58.15#ibcon#read 6, iclass 35, count 0 2006.224.08:21:58.15#ibcon#end of sib2, iclass 35, count 0 2006.224.08:21:58.15#ibcon#*after write, iclass 35, count 0 2006.224.08:21:58.15#ibcon#*before return 0, iclass 35, count 0 2006.224.08:21:58.15#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.224.08:21:58.15#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.224.08:21:58.15#ibcon#about to clear, iclass 35 cls_cnt 0 2006.224.08:21:58.15#ibcon#cleared, iclass 35 cls_cnt 0 2006.224.08:21:58.15$vc4f8/valo=2,572.99 2006.224.08:21:58.15#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.224.08:21:58.15#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.224.08:21:58.15#ibcon#ireg 17 cls_cnt 0 2006.224.08:21:58.15#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.224.08:21:58.15#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.224.08:21:58.15#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.224.08:21:58.15#ibcon#enter wrdev, iclass 37, count 0 2006.224.08:21:58.15#ibcon#first serial, iclass 37, count 0 2006.224.08:21:58.15#ibcon#enter sib2, iclass 37, count 0 2006.224.08:21:58.15#ibcon#flushed, iclass 37, count 0 2006.224.08:21:58.15#ibcon#about to write, iclass 37, count 0 2006.224.08:21:58.15#ibcon#wrote, iclass 37, count 0 2006.224.08:21:58.15#ibcon#about to read 3, iclass 37, count 0 2006.224.08:21:58.18#ibcon#read 3, iclass 37, count 0 2006.224.08:21:58.18#ibcon#about to read 4, iclass 37, count 0 2006.224.08:21:58.18#ibcon#read 4, iclass 37, count 0 2006.224.08:21:58.18#ibcon#about to read 5, iclass 37, count 0 2006.224.08:21:58.18#ibcon#read 5, iclass 37, count 0 2006.224.08:21:58.18#ibcon#about to read 6, iclass 37, count 0 2006.224.08:21:58.18#ibcon#read 6, iclass 37, count 0 2006.224.08:21:58.18#ibcon#end of sib2, iclass 37, count 0 2006.224.08:21:58.18#ibcon#*mode == 0, iclass 37, count 0 2006.224.08:21:58.18#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.224.08:21:58.18#ibcon#[26=FRQ=02,572.99\r\n] 2006.224.08:21:58.18#ibcon#*before write, iclass 37, count 0 2006.224.08:21:58.18#ibcon#enter sib2, iclass 37, count 0 2006.224.08:21:58.18#ibcon#flushed, iclass 37, count 0 2006.224.08:21:58.18#ibcon#about to write, iclass 37, count 0 2006.224.08:21:58.18#ibcon#wrote, iclass 37, count 0 2006.224.08:21:58.18#ibcon#about to read 3, iclass 37, count 0 2006.224.08:21:58.22#ibcon#read 3, iclass 37, count 0 2006.224.08:21:58.22#ibcon#about to read 4, iclass 37, count 0 2006.224.08:21:58.22#ibcon#read 4, iclass 37, count 0 2006.224.08:21:58.22#ibcon#about to read 5, iclass 37, count 0 2006.224.08:21:58.22#ibcon#read 5, iclass 37, count 0 2006.224.08:21:58.22#ibcon#about to read 6, iclass 37, count 0 2006.224.08:21:58.22#ibcon#read 6, iclass 37, count 0 2006.224.08:21:58.22#ibcon#end of sib2, iclass 37, count 0 2006.224.08:21:58.22#ibcon#*after write, iclass 37, count 0 2006.224.08:21:58.22#ibcon#*before return 0, iclass 37, count 0 2006.224.08:21:58.22#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.224.08:21:58.22#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.224.08:21:58.22#ibcon#about to clear, iclass 37 cls_cnt 0 2006.224.08:21:58.22#ibcon#cleared, iclass 37 cls_cnt 0 2006.224.08:21:58.22$vc4f8/va=2,7 2006.224.08:21:58.22#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.224.08:21:58.22#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.224.08:21:58.22#ibcon#ireg 11 cls_cnt 2 2006.224.08:21:58.22#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.224.08:21:58.28#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.224.08:21:58.28#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.224.08:21:58.28#ibcon#enter wrdev, iclass 39, count 2 2006.224.08:21:58.28#ibcon#first serial, iclass 39, count 2 2006.224.08:21:58.28#ibcon#enter sib2, iclass 39, count 2 2006.224.08:21:58.28#ibcon#flushed, iclass 39, count 2 2006.224.08:21:58.28#ibcon#about to write, iclass 39, count 2 2006.224.08:21:58.28#ibcon#wrote, iclass 39, count 2 2006.224.08:21:58.28#ibcon#about to read 3, iclass 39, count 2 2006.224.08:21:58.29#ibcon#read 3, iclass 39, count 2 2006.224.08:21:58.29#ibcon#about to read 4, iclass 39, count 2 2006.224.08:21:58.29#ibcon#read 4, iclass 39, count 2 2006.224.08:21:58.29#ibcon#about to read 5, iclass 39, count 2 2006.224.08:21:58.29#ibcon#read 5, iclass 39, count 2 2006.224.08:21:58.29#ibcon#about to read 6, iclass 39, count 2 2006.224.08:21:58.29#ibcon#read 6, iclass 39, count 2 2006.224.08:21:58.29#ibcon#end of sib2, iclass 39, count 2 2006.224.08:21:58.29#ibcon#*mode == 0, iclass 39, count 2 2006.224.08:21:58.29#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.224.08:21:58.29#ibcon#[25=AT02-07\r\n] 2006.224.08:21:58.29#ibcon#*before write, iclass 39, count 2 2006.224.08:21:58.29#ibcon#enter sib2, iclass 39, count 2 2006.224.08:21:58.29#ibcon#flushed, iclass 39, count 2 2006.224.08:21:58.29#ibcon#about to write, iclass 39, count 2 2006.224.08:21:58.29#ibcon#wrote, iclass 39, count 2 2006.224.08:21:58.29#ibcon#about to read 3, iclass 39, count 2 2006.224.08:21:58.32#ibcon#read 3, iclass 39, count 2 2006.224.08:21:58.32#ibcon#about to read 4, iclass 39, count 2 2006.224.08:21:58.32#ibcon#read 4, iclass 39, count 2 2006.224.08:21:58.32#ibcon#about to read 5, iclass 39, count 2 2006.224.08:21:58.32#ibcon#read 5, iclass 39, count 2 2006.224.08:21:58.32#ibcon#about to read 6, iclass 39, count 2 2006.224.08:21:58.32#ibcon#read 6, iclass 39, count 2 2006.224.08:21:58.32#ibcon#end of sib2, iclass 39, count 2 2006.224.08:21:58.32#ibcon#*after write, iclass 39, count 2 2006.224.08:21:58.32#ibcon#*before return 0, iclass 39, count 2 2006.224.08:21:58.32#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.224.08:21:58.32#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.224.08:21:58.32#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.224.08:21:58.32#ibcon#ireg 7 cls_cnt 0 2006.224.08:21:58.32#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.224.08:21:58.44#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.224.08:21:58.44#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.224.08:21:58.44#ibcon#enter wrdev, iclass 39, count 0 2006.224.08:21:58.44#ibcon#first serial, iclass 39, count 0 2006.224.08:21:58.44#ibcon#enter sib2, iclass 39, count 0 2006.224.08:21:58.44#ibcon#flushed, iclass 39, count 0 2006.224.08:21:58.44#ibcon#about to write, iclass 39, count 0 2006.224.08:21:58.44#ibcon#wrote, iclass 39, count 0 2006.224.08:21:58.44#ibcon#about to read 3, iclass 39, count 0 2006.224.08:21:58.46#ibcon#read 3, iclass 39, count 0 2006.224.08:21:58.46#ibcon#about to read 4, iclass 39, count 0 2006.224.08:21:58.46#ibcon#read 4, iclass 39, count 0 2006.224.08:21:58.46#ibcon#about to read 5, iclass 39, count 0 2006.224.08:21:58.46#ibcon#read 5, iclass 39, count 0 2006.224.08:21:58.46#ibcon#about to read 6, iclass 39, count 0 2006.224.08:21:58.46#ibcon#read 6, iclass 39, count 0 2006.224.08:21:58.46#ibcon#end of sib2, iclass 39, count 0 2006.224.08:21:58.46#ibcon#*mode == 0, iclass 39, count 0 2006.224.08:21:58.46#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.224.08:21:58.46#ibcon#[25=USB\r\n] 2006.224.08:21:58.46#ibcon#*before write, iclass 39, count 0 2006.224.08:21:58.46#ibcon#enter sib2, iclass 39, count 0 2006.224.08:21:58.46#ibcon#flushed, iclass 39, count 0 2006.224.08:21:58.46#ibcon#about to write, iclass 39, count 0 2006.224.08:21:58.46#ibcon#wrote, iclass 39, count 0 2006.224.08:21:58.46#ibcon#about to read 3, iclass 39, count 0 2006.224.08:21:58.49#ibcon#read 3, iclass 39, count 0 2006.224.08:21:58.49#ibcon#about to read 4, iclass 39, count 0 2006.224.08:21:58.49#ibcon#read 4, iclass 39, count 0 2006.224.08:21:58.49#ibcon#about to read 5, iclass 39, count 0 2006.224.08:21:58.49#ibcon#read 5, iclass 39, count 0 2006.224.08:21:58.49#ibcon#about to read 6, iclass 39, count 0 2006.224.08:21:58.49#ibcon#read 6, iclass 39, count 0 2006.224.08:21:58.49#ibcon#end of sib2, iclass 39, count 0 2006.224.08:21:58.49#ibcon#*after write, iclass 39, count 0 2006.224.08:21:58.49#ibcon#*before return 0, iclass 39, count 0 2006.224.08:21:58.49#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.224.08:21:58.49#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.224.08:21:58.49#ibcon#about to clear, iclass 39 cls_cnt 0 2006.224.08:21:58.49#ibcon#cleared, iclass 39 cls_cnt 0 2006.224.08:21:58.49$vc4f8/valo=3,672.99 2006.224.08:21:58.49#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.224.08:21:58.49#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.224.08:21:58.49#ibcon#ireg 17 cls_cnt 0 2006.224.08:21:58.49#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.224.08:21:58.49#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.224.08:21:58.49#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.224.08:21:58.49#ibcon#enter wrdev, iclass 3, count 0 2006.224.08:21:58.49#ibcon#first serial, iclass 3, count 0 2006.224.08:21:58.49#ibcon#enter sib2, iclass 3, count 0 2006.224.08:21:58.49#ibcon#flushed, iclass 3, count 0 2006.224.08:21:58.49#ibcon#about to write, iclass 3, count 0 2006.224.08:21:58.49#ibcon#wrote, iclass 3, count 0 2006.224.08:21:58.49#ibcon#about to read 3, iclass 3, count 0 2006.224.08:21:58.52#ibcon#read 3, iclass 3, count 0 2006.224.08:21:58.52#ibcon#about to read 4, iclass 3, count 0 2006.224.08:21:58.52#ibcon#read 4, iclass 3, count 0 2006.224.08:21:58.52#ibcon#about to read 5, iclass 3, count 0 2006.224.08:21:58.52#ibcon#read 5, iclass 3, count 0 2006.224.08:21:58.52#ibcon#about to read 6, iclass 3, count 0 2006.224.08:21:58.52#ibcon#read 6, iclass 3, count 0 2006.224.08:21:58.52#ibcon#end of sib2, iclass 3, count 0 2006.224.08:21:58.52#ibcon#*mode == 0, iclass 3, count 0 2006.224.08:21:58.52#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.224.08:21:58.52#ibcon#[26=FRQ=03,672.99\r\n] 2006.224.08:21:58.52#ibcon#*before write, iclass 3, count 0 2006.224.08:21:58.52#ibcon#enter sib2, iclass 3, count 0 2006.224.08:21:58.52#ibcon#flushed, iclass 3, count 0 2006.224.08:21:58.52#ibcon#about to write, iclass 3, count 0 2006.224.08:21:58.52#ibcon#wrote, iclass 3, count 0 2006.224.08:21:58.52#ibcon#about to read 3, iclass 3, count 0 2006.224.08:21:58.56#ibcon#read 3, iclass 3, count 0 2006.224.08:21:58.56#ibcon#about to read 4, iclass 3, count 0 2006.224.08:21:58.56#ibcon#read 4, iclass 3, count 0 2006.224.08:21:58.56#ibcon#about to read 5, iclass 3, count 0 2006.224.08:21:58.56#ibcon#read 5, iclass 3, count 0 2006.224.08:21:58.56#ibcon#about to read 6, iclass 3, count 0 2006.224.08:21:58.56#ibcon#read 6, iclass 3, count 0 2006.224.08:21:58.56#ibcon#end of sib2, iclass 3, count 0 2006.224.08:21:58.56#ibcon#*after write, iclass 3, count 0 2006.224.08:21:58.56#ibcon#*before return 0, iclass 3, count 0 2006.224.08:21:58.56#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.224.08:21:58.56#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.224.08:21:58.56#ibcon#about to clear, iclass 3 cls_cnt 0 2006.224.08:21:58.56#ibcon#cleared, iclass 3 cls_cnt 0 2006.224.08:21:58.56$vc4f8/va=3,6 2006.224.08:21:58.56#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.224.08:21:58.56#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.224.08:21:58.56#ibcon#ireg 11 cls_cnt 2 2006.224.08:21:58.56#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.224.08:21:58.62#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.224.08:21:58.62#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.224.08:21:58.62#ibcon#enter wrdev, iclass 5, count 2 2006.224.08:21:58.62#ibcon#first serial, iclass 5, count 2 2006.224.08:21:58.62#ibcon#enter sib2, iclass 5, count 2 2006.224.08:21:58.62#ibcon#flushed, iclass 5, count 2 2006.224.08:21:58.62#ibcon#about to write, iclass 5, count 2 2006.224.08:21:58.62#ibcon#wrote, iclass 5, count 2 2006.224.08:21:58.62#ibcon#about to read 3, iclass 5, count 2 2006.224.08:21:58.63#ibcon#read 3, iclass 5, count 2 2006.224.08:21:58.63#ibcon#about to read 4, iclass 5, count 2 2006.224.08:21:58.63#ibcon#read 4, iclass 5, count 2 2006.224.08:21:58.63#ibcon#about to read 5, iclass 5, count 2 2006.224.08:21:58.63#ibcon#read 5, iclass 5, count 2 2006.224.08:21:58.63#ibcon#about to read 6, iclass 5, count 2 2006.224.08:21:58.63#ibcon#read 6, iclass 5, count 2 2006.224.08:21:58.63#ibcon#end of sib2, iclass 5, count 2 2006.224.08:21:58.63#ibcon#*mode == 0, iclass 5, count 2 2006.224.08:21:58.63#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.224.08:21:58.63#ibcon#[25=AT03-06\r\n] 2006.224.08:21:58.63#ibcon#*before write, iclass 5, count 2 2006.224.08:21:58.63#ibcon#enter sib2, iclass 5, count 2 2006.224.08:21:58.63#ibcon#flushed, iclass 5, count 2 2006.224.08:21:58.63#ibcon#about to write, iclass 5, count 2 2006.224.08:21:58.63#ibcon#wrote, iclass 5, count 2 2006.224.08:21:58.63#ibcon#about to read 3, iclass 5, count 2 2006.224.08:21:58.66#ibcon#read 3, iclass 5, count 2 2006.224.08:21:58.66#ibcon#about to read 4, iclass 5, count 2 2006.224.08:21:58.66#ibcon#read 4, iclass 5, count 2 2006.224.08:21:58.66#ibcon#about to read 5, iclass 5, count 2 2006.224.08:21:58.66#ibcon#read 5, iclass 5, count 2 2006.224.08:21:58.66#ibcon#about to read 6, iclass 5, count 2 2006.224.08:21:58.66#ibcon#read 6, iclass 5, count 2 2006.224.08:21:58.66#ibcon#end of sib2, iclass 5, count 2 2006.224.08:21:58.66#ibcon#*after write, iclass 5, count 2 2006.224.08:21:58.66#ibcon#*before return 0, iclass 5, count 2 2006.224.08:21:58.66#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.224.08:21:58.66#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.224.08:21:58.66#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.224.08:21:58.66#ibcon#ireg 7 cls_cnt 0 2006.224.08:21:58.66#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.224.08:21:58.78#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.224.08:21:58.78#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.224.08:21:58.78#ibcon#enter wrdev, iclass 5, count 0 2006.224.08:21:58.78#ibcon#first serial, iclass 5, count 0 2006.224.08:21:58.78#ibcon#enter sib2, iclass 5, count 0 2006.224.08:21:58.78#ibcon#flushed, iclass 5, count 0 2006.224.08:21:58.78#ibcon#about to write, iclass 5, count 0 2006.224.08:21:58.78#ibcon#wrote, iclass 5, count 0 2006.224.08:21:58.78#ibcon#about to read 3, iclass 5, count 0 2006.224.08:21:58.80#ibcon#read 3, iclass 5, count 0 2006.224.08:21:58.80#ibcon#about to read 4, iclass 5, count 0 2006.224.08:21:58.80#ibcon#read 4, iclass 5, count 0 2006.224.08:21:58.80#ibcon#about to read 5, iclass 5, count 0 2006.224.08:21:58.80#ibcon#read 5, iclass 5, count 0 2006.224.08:21:58.80#ibcon#about to read 6, iclass 5, count 0 2006.224.08:21:58.80#ibcon#read 6, iclass 5, count 0 2006.224.08:21:58.80#ibcon#end of sib2, iclass 5, count 0 2006.224.08:21:58.80#ibcon#*mode == 0, iclass 5, count 0 2006.224.08:21:58.80#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.224.08:21:58.80#ibcon#[25=USB\r\n] 2006.224.08:21:58.80#ibcon#*before write, iclass 5, count 0 2006.224.08:21:58.80#ibcon#enter sib2, iclass 5, count 0 2006.224.08:21:58.80#ibcon#flushed, iclass 5, count 0 2006.224.08:21:58.80#ibcon#about to write, iclass 5, count 0 2006.224.08:21:58.80#ibcon#wrote, iclass 5, count 0 2006.224.08:21:58.80#ibcon#about to read 3, iclass 5, count 0 2006.224.08:21:58.83#ibcon#read 3, iclass 5, count 0 2006.224.08:21:58.83#ibcon#about to read 4, iclass 5, count 0 2006.224.08:21:58.83#ibcon#read 4, iclass 5, count 0 2006.224.08:21:58.83#ibcon#about to read 5, iclass 5, count 0 2006.224.08:21:58.83#ibcon#read 5, iclass 5, count 0 2006.224.08:21:58.83#ibcon#about to read 6, iclass 5, count 0 2006.224.08:21:58.83#ibcon#read 6, iclass 5, count 0 2006.224.08:21:58.83#ibcon#end of sib2, iclass 5, count 0 2006.224.08:21:58.83#ibcon#*after write, iclass 5, count 0 2006.224.08:21:58.83#ibcon#*before return 0, iclass 5, count 0 2006.224.08:21:58.83#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.224.08:21:58.83#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.224.08:21:58.83#ibcon#about to clear, iclass 5 cls_cnt 0 2006.224.08:21:58.83#ibcon#cleared, iclass 5 cls_cnt 0 2006.224.08:21:58.83$vc4f8/valo=4,832.99 2006.224.08:21:58.83#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.224.08:21:58.83#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.224.08:21:58.83#ibcon#ireg 17 cls_cnt 0 2006.224.08:21:58.83#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.224.08:21:58.83#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.224.08:21:58.83#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.224.08:21:58.83#ibcon#enter wrdev, iclass 7, count 0 2006.224.08:21:58.83#ibcon#first serial, iclass 7, count 0 2006.224.08:21:58.83#ibcon#enter sib2, iclass 7, count 0 2006.224.08:21:58.83#ibcon#flushed, iclass 7, count 0 2006.224.08:21:58.83#ibcon#about to write, iclass 7, count 0 2006.224.08:21:58.83#ibcon#wrote, iclass 7, count 0 2006.224.08:21:58.83#ibcon#about to read 3, iclass 7, count 0 2006.224.08:21:58.86#ibcon#read 3, iclass 7, count 0 2006.224.08:21:58.86#ibcon#about to read 4, iclass 7, count 0 2006.224.08:21:58.86#ibcon#read 4, iclass 7, count 0 2006.224.08:21:58.86#ibcon#about to read 5, iclass 7, count 0 2006.224.08:21:58.86#ibcon#read 5, iclass 7, count 0 2006.224.08:21:58.86#ibcon#about to read 6, iclass 7, count 0 2006.224.08:21:58.86#ibcon#read 6, iclass 7, count 0 2006.224.08:21:58.86#ibcon#end of sib2, iclass 7, count 0 2006.224.08:21:58.86#ibcon#*mode == 0, iclass 7, count 0 2006.224.08:21:58.86#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.224.08:21:58.86#ibcon#[26=FRQ=04,832.99\r\n] 2006.224.08:21:58.86#ibcon#*before write, iclass 7, count 0 2006.224.08:21:58.86#ibcon#enter sib2, iclass 7, count 0 2006.224.08:21:58.86#ibcon#flushed, iclass 7, count 0 2006.224.08:21:58.86#ibcon#about to write, iclass 7, count 0 2006.224.08:21:58.86#ibcon#wrote, iclass 7, count 0 2006.224.08:21:58.86#ibcon#about to read 3, iclass 7, count 0 2006.224.08:21:58.90#ibcon#read 3, iclass 7, count 0 2006.224.08:21:58.90#ibcon#about to read 4, iclass 7, count 0 2006.224.08:21:58.90#ibcon#read 4, iclass 7, count 0 2006.224.08:21:58.90#ibcon#about to read 5, iclass 7, count 0 2006.224.08:21:58.90#ibcon#read 5, iclass 7, count 0 2006.224.08:21:58.90#ibcon#about to read 6, iclass 7, count 0 2006.224.08:21:58.90#ibcon#read 6, iclass 7, count 0 2006.224.08:21:58.90#ibcon#end of sib2, iclass 7, count 0 2006.224.08:21:58.90#ibcon#*after write, iclass 7, count 0 2006.224.08:21:58.90#ibcon#*before return 0, iclass 7, count 0 2006.224.08:21:58.90#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.224.08:21:58.90#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.224.08:21:58.90#ibcon#about to clear, iclass 7 cls_cnt 0 2006.224.08:21:58.90#ibcon#cleared, iclass 7 cls_cnt 0 2006.224.08:21:58.90$vc4f8/va=4,7 2006.224.08:21:58.90#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.224.08:21:58.90#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.224.08:21:58.90#ibcon#ireg 11 cls_cnt 2 2006.224.08:21:58.90#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.224.08:21:58.95#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.224.08:21:58.95#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.224.08:21:58.95#ibcon#enter wrdev, iclass 11, count 2 2006.224.08:21:58.95#ibcon#first serial, iclass 11, count 2 2006.224.08:21:58.95#ibcon#enter sib2, iclass 11, count 2 2006.224.08:21:58.95#ibcon#flushed, iclass 11, count 2 2006.224.08:21:58.95#ibcon#about to write, iclass 11, count 2 2006.224.08:21:58.95#ibcon#wrote, iclass 11, count 2 2006.224.08:21:58.95#ibcon#about to read 3, iclass 11, count 2 2006.224.08:21:58.97#ibcon#read 3, iclass 11, count 2 2006.224.08:21:58.97#ibcon#about to read 4, iclass 11, count 2 2006.224.08:21:58.97#ibcon#read 4, iclass 11, count 2 2006.224.08:21:58.97#ibcon#about to read 5, iclass 11, count 2 2006.224.08:21:58.97#ibcon#read 5, iclass 11, count 2 2006.224.08:21:58.97#ibcon#about to read 6, iclass 11, count 2 2006.224.08:21:58.97#ibcon#read 6, iclass 11, count 2 2006.224.08:21:58.97#ibcon#end of sib2, iclass 11, count 2 2006.224.08:21:58.97#ibcon#*mode == 0, iclass 11, count 2 2006.224.08:21:58.97#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.224.08:21:58.97#ibcon#[25=AT04-07\r\n] 2006.224.08:21:58.97#ibcon#*before write, iclass 11, count 2 2006.224.08:21:58.97#ibcon#enter sib2, iclass 11, count 2 2006.224.08:21:58.97#ibcon#flushed, iclass 11, count 2 2006.224.08:21:58.97#ibcon#about to write, iclass 11, count 2 2006.224.08:21:58.97#ibcon#wrote, iclass 11, count 2 2006.224.08:21:58.97#ibcon#about to read 3, iclass 11, count 2 2006.224.08:21:59.00#ibcon#read 3, iclass 11, count 2 2006.224.08:21:59.00#ibcon#about to read 4, iclass 11, count 2 2006.224.08:21:59.00#ibcon#read 4, iclass 11, count 2 2006.224.08:21:59.00#ibcon#about to read 5, iclass 11, count 2 2006.224.08:21:59.00#ibcon#read 5, iclass 11, count 2 2006.224.08:21:59.00#ibcon#about to read 6, iclass 11, count 2 2006.224.08:21:59.00#ibcon#read 6, iclass 11, count 2 2006.224.08:21:59.00#ibcon#end of sib2, iclass 11, count 2 2006.224.08:21:59.00#ibcon#*after write, iclass 11, count 2 2006.224.08:21:59.00#ibcon#*before return 0, iclass 11, count 2 2006.224.08:21:59.00#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.224.08:21:59.00#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.224.08:21:59.00#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.224.08:21:59.00#ibcon#ireg 7 cls_cnt 0 2006.224.08:21:59.00#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.224.08:21:59.12#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.224.08:21:59.12#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.224.08:21:59.12#ibcon#enter wrdev, iclass 11, count 0 2006.224.08:21:59.12#ibcon#first serial, iclass 11, count 0 2006.224.08:21:59.12#ibcon#enter sib2, iclass 11, count 0 2006.224.08:21:59.12#ibcon#flushed, iclass 11, count 0 2006.224.08:21:59.12#ibcon#about to write, iclass 11, count 0 2006.224.08:21:59.12#ibcon#wrote, iclass 11, count 0 2006.224.08:21:59.12#ibcon#about to read 3, iclass 11, count 0 2006.224.08:21:59.14#ibcon#read 3, iclass 11, count 0 2006.224.08:21:59.14#ibcon#about to read 4, iclass 11, count 0 2006.224.08:21:59.14#ibcon#read 4, iclass 11, count 0 2006.224.08:21:59.14#ibcon#about to read 5, iclass 11, count 0 2006.224.08:21:59.14#ibcon#read 5, iclass 11, count 0 2006.224.08:21:59.14#ibcon#about to read 6, iclass 11, count 0 2006.224.08:21:59.14#ibcon#read 6, iclass 11, count 0 2006.224.08:21:59.14#ibcon#end of sib2, iclass 11, count 0 2006.224.08:21:59.14#ibcon#*mode == 0, iclass 11, count 0 2006.224.08:21:59.14#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.224.08:21:59.14#ibcon#[25=USB\r\n] 2006.224.08:21:59.14#ibcon#*before write, iclass 11, count 0 2006.224.08:21:59.14#ibcon#enter sib2, iclass 11, count 0 2006.224.08:21:59.14#ibcon#flushed, iclass 11, count 0 2006.224.08:21:59.14#ibcon#about to write, iclass 11, count 0 2006.224.08:21:59.14#ibcon#wrote, iclass 11, count 0 2006.224.08:21:59.14#ibcon#about to read 3, iclass 11, count 0 2006.224.08:21:59.17#ibcon#read 3, iclass 11, count 0 2006.224.08:21:59.17#ibcon#about to read 4, iclass 11, count 0 2006.224.08:21:59.17#ibcon#read 4, iclass 11, count 0 2006.224.08:21:59.17#ibcon#about to read 5, iclass 11, count 0 2006.224.08:21:59.17#ibcon#read 5, iclass 11, count 0 2006.224.08:21:59.17#ibcon#about to read 6, iclass 11, count 0 2006.224.08:21:59.17#ibcon#read 6, iclass 11, count 0 2006.224.08:21:59.17#ibcon#end of sib2, iclass 11, count 0 2006.224.08:21:59.17#ibcon#*after write, iclass 11, count 0 2006.224.08:21:59.17#ibcon#*before return 0, iclass 11, count 0 2006.224.08:21:59.17#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.224.08:21:59.17#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.224.08:21:59.17#ibcon#about to clear, iclass 11 cls_cnt 0 2006.224.08:21:59.17#ibcon#cleared, iclass 11 cls_cnt 0 2006.224.08:21:59.17$vc4f8/valo=5,652.99 2006.224.08:21:59.17#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.224.08:21:59.17#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.224.08:21:59.17#ibcon#ireg 17 cls_cnt 0 2006.224.08:21:59.17#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.224.08:21:59.17#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.224.08:21:59.17#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.224.08:21:59.17#ibcon#enter wrdev, iclass 13, count 0 2006.224.08:21:59.17#ibcon#first serial, iclass 13, count 0 2006.224.08:21:59.17#ibcon#enter sib2, iclass 13, count 0 2006.224.08:21:59.17#ibcon#flushed, iclass 13, count 0 2006.224.08:21:59.17#ibcon#about to write, iclass 13, count 0 2006.224.08:21:59.17#ibcon#wrote, iclass 13, count 0 2006.224.08:21:59.17#ibcon#about to read 3, iclass 13, count 0 2006.224.08:21:59.19#ibcon#read 3, iclass 13, count 0 2006.224.08:21:59.19#ibcon#about to read 4, iclass 13, count 0 2006.224.08:21:59.19#ibcon#read 4, iclass 13, count 0 2006.224.08:21:59.19#ibcon#about to read 5, iclass 13, count 0 2006.224.08:21:59.19#ibcon#read 5, iclass 13, count 0 2006.224.08:21:59.19#ibcon#about to read 6, iclass 13, count 0 2006.224.08:21:59.19#ibcon#read 6, iclass 13, count 0 2006.224.08:21:59.19#ibcon#end of sib2, iclass 13, count 0 2006.224.08:21:59.19#ibcon#*mode == 0, iclass 13, count 0 2006.224.08:21:59.19#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.224.08:21:59.19#ibcon#[26=FRQ=05,652.99\r\n] 2006.224.08:21:59.19#ibcon#*before write, iclass 13, count 0 2006.224.08:21:59.19#ibcon#enter sib2, iclass 13, count 0 2006.224.08:21:59.19#ibcon#flushed, iclass 13, count 0 2006.224.08:21:59.19#ibcon#about to write, iclass 13, count 0 2006.224.08:21:59.19#ibcon#wrote, iclass 13, count 0 2006.224.08:21:59.19#ibcon#about to read 3, iclass 13, count 0 2006.224.08:21:59.23#ibcon#read 3, iclass 13, count 0 2006.224.08:21:59.23#ibcon#about to read 4, iclass 13, count 0 2006.224.08:21:59.23#ibcon#read 4, iclass 13, count 0 2006.224.08:21:59.23#ibcon#about to read 5, iclass 13, count 0 2006.224.08:21:59.23#ibcon#read 5, iclass 13, count 0 2006.224.08:21:59.23#ibcon#about to read 6, iclass 13, count 0 2006.224.08:21:59.23#ibcon#read 6, iclass 13, count 0 2006.224.08:21:59.23#ibcon#end of sib2, iclass 13, count 0 2006.224.08:21:59.23#ibcon#*after write, iclass 13, count 0 2006.224.08:21:59.23#ibcon#*before return 0, iclass 13, count 0 2006.224.08:21:59.23#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.224.08:21:59.23#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.224.08:21:59.23#ibcon#about to clear, iclass 13 cls_cnt 0 2006.224.08:21:59.23#ibcon#cleared, iclass 13 cls_cnt 0 2006.224.08:21:59.23$vc4f8/va=5,7 2006.224.08:21:59.23#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.224.08:21:59.23#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.224.08:21:59.23#ibcon#ireg 11 cls_cnt 2 2006.224.08:21:59.23#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.224.08:21:59.29#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.224.08:21:59.29#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.224.08:21:59.29#ibcon#enter wrdev, iclass 15, count 2 2006.224.08:21:59.29#ibcon#first serial, iclass 15, count 2 2006.224.08:21:59.29#ibcon#enter sib2, iclass 15, count 2 2006.224.08:21:59.29#ibcon#flushed, iclass 15, count 2 2006.224.08:21:59.29#ibcon#about to write, iclass 15, count 2 2006.224.08:21:59.29#ibcon#wrote, iclass 15, count 2 2006.224.08:21:59.29#ibcon#about to read 3, iclass 15, count 2 2006.224.08:21:59.31#ibcon#read 3, iclass 15, count 2 2006.224.08:21:59.31#ibcon#about to read 4, iclass 15, count 2 2006.224.08:21:59.31#ibcon#read 4, iclass 15, count 2 2006.224.08:21:59.31#ibcon#about to read 5, iclass 15, count 2 2006.224.08:21:59.31#ibcon#read 5, iclass 15, count 2 2006.224.08:21:59.31#ibcon#about to read 6, iclass 15, count 2 2006.224.08:21:59.31#ibcon#read 6, iclass 15, count 2 2006.224.08:21:59.31#ibcon#end of sib2, iclass 15, count 2 2006.224.08:21:59.31#ibcon#*mode == 0, iclass 15, count 2 2006.224.08:21:59.31#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.224.08:21:59.31#ibcon#[25=AT05-07\r\n] 2006.224.08:21:59.31#ibcon#*before write, iclass 15, count 2 2006.224.08:21:59.31#ibcon#enter sib2, iclass 15, count 2 2006.224.08:21:59.31#ibcon#flushed, iclass 15, count 2 2006.224.08:21:59.31#ibcon#about to write, iclass 15, count 2 2006.224.08:21:59.31#ibcon#wrote, iclass 15, count 2 2006.224.08:21:59.31#ibcon#about to read 3, iclass 15, count 2 2006.224.08:21:59.34#ibcon#read 3, iclass 15, count 2 2006.224.08:21:59.34#ibcon#about to read 4, iclass 15, count 2 2006.224.08:21:59.34#ibcon#read 4, iclass 15, count 2 2006.224.08:21:59.34#ibcon#about to read 5, iclass 15, count 2 2006.224.08:21:59.34#ibcon#read 5, iclass 15, count 2 2006.224.08:21:59.34#ibcon#about to read 6, iclass 15, count 2 2006.224.08:21:59.34#ibcon#read 6, iclass 15, count 2 2006.224.08:21:59.34#ibcon#end of sib2, iclass 15, count 2 2006.224.08:21:59.34#ibcon#*after write, iclass 15, count 2 2006.224.08:21:59.34#ibcon#*before return 0, iclass 15, count 2 2006.224.08:21:59.34#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.224.08:21:59.34#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.224.08:21:59.34#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.224.08:21:59.34#ibcon#ireg 7 cls_cnt 0 2006.224.08:21:59.34#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.224.08:21:59.46#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.224.08:21:59.46#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.224.08:21:59.46#ibcon#enter wrdev, iclass 15, count 0 2006.224.08:21:59.46#ibcon#first serial, iclass 15, count 0 2006.224.08:21:59.46#ibcon#enter sib2, iclass 15, count 0 2006.224.08:21:59.46#ibcon#flushed, iclass 15, count 0 2006.224.08:21:59.46#ibcon#about to write, iclass 15, count 0 2006.224.08:21:59.46#ibcon#wrote, iclass 15, count 0 2006.224.08:21:59.46#ibcon#about to read 3, iclass 15, count 0 2006.224.08:21:59.48#ibcon#read 3, iclass 15, count 0 2006.224.08:21:59.48#ibcon#about to read 4, iclass 15, count 0 2006.224.08:21:59.48#ibcon#read 4, iclass 15, count 0 2006.224.08:21:59.48#ibcon#about to read 5, iclass 15, count 0 2006.224.08:21:59.48#ibcon#read 5, iclass 15, count 0 2006.224.08:21:59.48#ibcon#about to read 6, iclass 15, count 0 2006.224.08:21:59.48#ibcon#read 6, iclass 15, count 0 2006.224.08:21:59.48#ibcon#end of sib2, iclass 15, count 0 2006.224.08:21:59.48#ibcon#*mode == 0, iclass 15, count 0 2006.224.08:21:59.48#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.224.08:21:59.48#ibcon#[25=USB\r\n] 2006.224.08:21:59.48#ibcon#*before write, iclass 15, count 0 2006.224.08:21:59.48#ibcon#enter sib2, iclass 15, count 0 2006.224.08:21:59.48#ibcon#flushed, iclass 15, count 0 2006.224.08:21:59.48#ibcon#about to write, iclass 15, count 0 2006.224.08:21:59.48#ibcon#wrote, iclass 15, count 0 2006.224.08:21:59.48#ibcon#about to read 3, iclass 15, count 0 2006.224.08:21:59.48#abcon#<5=/11 1.0 2.6 23.811001004.7\r\n> 2006.224.08:21:59.50#abcon#{5=INTERFACE CLEAR} 2006.224.08:21:59.51#ibcon#read 3, iclass 15, count 0 2006.224.08:21:59.51#ibcon#about to read 4, iclass 15, count 0 2006.224.08:21:59.51#ibcon#read 4, iclass 15, count 0 2006.224.08:21:59.51#ibcon#about to read 5, iclass 15, count 0 2006.224.08:21:59.51#ibcon#read 5, iclass 15, count 0 2006.224.08:21:59.51#ibcon#about to read 6, iclass 15, count 0 2006.224.08:21:59.51#ibcon#read 6, iclass 15, count 0 2006.224.08:21:59.51#ibcon#end of sib2, iclass 15, count 0 2006.224.08:21:59.51#ibcon#*after write, iclass 15, count 0 2006.224.08:21:59.51#ibcon#*before return 0, iclass 15, count 0 2006.224.08:21:59.51#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.224.08:21:59.51#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.224.08:21:59.51#ibcon#about to clear, iclass 15 cls_cnt 0 2006.224.08:21:59.51#ibcon#cleared, iclass 15 cls_cnt 0 2006.224.08:21:59.51$vc4f8/valo=6,772.99 2006.224.08:21:59.51#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.224.08:21:59.51#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.224.08:21:59.51#ibcon#ireg 17 cls_cnt 0 2006.224.08:21:59.51#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.224.08:21:59.51#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.224.08:21:59.51#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.224.08:21:59.51#ibcon#enter wrdev, iclass 20, count 0 2006.224.08:21:59.51#ibcon#first serial, iclass 20, count 0 2006.224.08:21:59.51#ibcon#enter sib2, iclass 20, count 0 2006.224.08:21:59.51#ibcon#flushed, iclass 20, count 0 2006.224.08:21:59.51#ibcon#about to write, iclass 20, count 0 2006.224.08:21:59.51#ibcon#wrote, iclass 20, count 0 2006.224.08:21:59.51#ibcon#about to read 3, iclass 20, count 0 2006.224.08:21:59.53#ibcon#read 3, iclass 20, count 0 2006.224.08:21:59.53#ibcon#about to read 4, iclass 20, count 0 2006.224.08:21:59.53#ibcon#read 4, iclass 20, count 0 2006.224.08:21:59.53#ibcon#about to read 5, iclass 20, count 0 2006.224.08:21:59.53#ibcon#read 5, iclass 20, count 0 2006.224.08:21:59.53#ibcon#about to read 6, iclass 20, count 0 2006.224.08:21:59.53#ibcon#read 6, iclass 20, count 0 2006.224.08:21:59.53#ibcon#end of sib2, iclass 20, count 0 2006.224.08:21:59.53#ibcon#*mode == 0, iclass 20, count 0 2006.224.08:21:59.53#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.224.08:21:59.53#ibcon#[26=FRQ=06,772.99\r\n] 2006.224.08:21:59.53#ibcon#*before write, iclass 20, count 0 2006.224.08:21:59.53#ibcon#enter sib2, iclass 20, count 0 2006.224.08:21:59.53#ibcon#flushed, iclass 20, count 0 2006.224.08:21:59.53#ibcon#about to write, iclass 20, count 0 2006.224.08:21:59.53#ibcon#wrote, iclass 20, count 0 2006.224.08:21:59.53#ibcon#about to read 3, iclass 20, count 0 2006.224.08:21:59.56#abcon#[5=S1D000X0/0*\r\n] 2006.224.08:21:59.57#ibcon#read 3, iclass 20, count 0 2006.224.08:21:59.57#ibcon#about to read 4, iclass 20, count 0 2006.224.08:21:59.57#ibcon#read 4, iclass 20, count 0 2006.224.08:21:59.57#ibcon#about to read 5, iclass 20, count 0 2006.224.08:21:59.57#ibcon#read 5, iclass 20, count 0 2006.224.08:21:59.57#ibcon#about to read 6, iclass 20, count 0 2006.224.08:21:59.57#ibcon#read 6, iclass 20, count 0 2006.224.08:21:59.57#ibcon#end of sib2, iclass 20, count 0 2006.224.08:21:59.57#ibcon#*after write, iclass 20, count 0 2006.224.08:21:59.57#ibcon#*before return 0, iclass 20, count 0 2006.224.08:21:59.57#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.224.08:21:59.57#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.224.08:21:59.57#ibcon#about to clear, iclass 20 cls_cnt 0 2006.224.08:21:59.57#ibcon#cleared, iclass 20 cls_cnt 0 2006.224.08:21:59.57$vc4f8/va=6,6 2006.224.08:21:59.57#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.224.08:21:59.57#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.224.08:21:59.57#ibcon#ireg 11 cls_cnt 2 2006.224.08:21:59.57#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.224.08:21:59.64#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.224.08:21:59.64#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.224.08:21:59.64#ibcon#enter wrdev, iclass 23, count 2 2006.224.08:21:59.64#ibcon#first serial, iclass 23, count 2 2006.224.08:21:59.64#ibcon#enter sib2, iclass 23, count 2 2006.224.08:21:59.64#ibcon#flushed, iclass 23, count 2 2006.224.08:21:59.64#ibcon#about to write, iclass 23, count 2 2006.224.08:21:59.64#ibcon#wrote, iclass 23, count 2 2006.224.08:21:59.64#ibcon#about to read 3, iclass 23, count 2 2006.224.08:21:59.65#ibcon#read 3, iclass 23, count 2 2006.224.08:21:59.65#ibcon#about to read 4, iclass 23, count 2 2006.224.08:21:59.65#ibcon#read 4, iclass 23, count 2 2006.224.08:21:59.65#ibcon#about to read 5, iclass 23, count 2 2006.224.08:21:59.66#ibcon#read 5, iclass 23, count 2 2006.224.08:21:59.66#ibcon#about to read 6, iclass 23, count 2 2006.224.08:21:59.66#ibcon#read 6, iclass 23, count 2 2006.224.08:21:59.66#ibcon#end of sib2, iclass 23, count 2 2006.224.08:21:59.66#ibcon#*mode == 0, iclass 23, count 2 2006.224.08:21:59.66#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.224.08:21:59.66#ibcon#[25=AT06-06\r\n] 2006.224.08:21:59.66#ibcon#*before write, iclass 23, count 2 2006.224.08:21:59.66#ibcon#enter sib2, iclass 23, count 2 2006.224.08:21:59.66#ibcon#flushed, iclass 23, count 2 2006.224.08:21:59.66#ibcon#about to write, iclass 23, count 2 2006.224.08:21:59.66#ibcon#wrote, iclass 23, count 2 2006.224.08:21:59.66#ibcon#about to read 3, iclass 23, count 2 2006.224.08:21:59.68#ibcon#read 3, iclass 23, count 2 2006.224.08:21:59.68#ibcon#about to read 4, iclass 23, count 2 2006.224.08:21:59.68#ibcon#read 4, iclass 23, count 2 2006.224.08:21:59.68#ibcon#about to read 5, iclass 23, count 2 2006.224.08:21:59.68#ibcon#read 5, iclass 23, count 2 2006.224.08:21:59.68#ibcon#about to read 6, iclass 23, count 2 2006.224.08:21:59.68#ibcon#read 6, iclass 23, count 2 2006.224.08:21:59.68#ibcon#end of sib2, iclass 23, count 2 2006.224.08:21:59.68#ibcon#*after write, iclass 23, count 2 2006.224.08:21:59.68#ibcon#*before return 0, iclass 23, count 2 2006.224.08:21:59.68#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.224.08:21:59.68#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.224.08:21:59.68#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.224.08:21:59.68#ibcon#ireg 7 cls_cnt 0 2006.224.08:21:59.68#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.224.08:21:59.80#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.224.08:21:59.80#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.224.08:21:59.80#ibcon#enter wrdev, iclass 23, count 0 2006.224.08:21:59.80#ibcon#first serial, iclass 23, count 0 2006.224.08:21:59.80#ibcon#enter sib2, iclass 23, count 0 2006.224.08:21:59.80#ibcon#flushed, iclass 23, count 0 2006.224.08:21:59.80#ibcon#about to write, iclass 23, count 0 2006.224.08:21:59.80#ibcon#wrote, iclass 23, count 0 2006.224.08:21:59.80#ibcon#about to read 3, iclass 23, count 0 2006.224.08:21:59.82#ibcon#read 3, iclass 23, count 0 2006.224.08:21:59.82#ibcon#about to read 4, iclass 23, count 0 2006.224.08:21:59.82#ibcon#read 4, iclass 23, count 0 2006.224.08:21:59.82#ibcon#about to read 5, iclass 23, count 0 2006.224.08:21:59.82#ibcon#read 5, iclass 23, count 0 2006.224.08:21:59.82#ibcon#about to read 6, iclass 23, count 0 2006.224.08:21:59.82#ibcon#read 6, iclass 23, count 0 2006.224.08:21:59.82#ibcon#end of sib2, iclass 23, count 0 2006.224.08:21:59.82#ibcon#*mode == 0, iclass 23, count 0 2006.224.08:21:59.82#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.224.08:21:59.82#ibcon#[25=USB\r\n] 2006.224.08:21:59.82#ibcon#*before write, iclass 23, count 0 2006.224.08:21:59.82#ibcon#enter sib2, iclass 23, count 0 2006.224.08:21:59.82#ibcon#flushed, iclass 23, count 0 2006.224.08:21:59.82#ibcon#about to write, iclass 23, count 0 2006.224.08:21:59.82#ibcon#wrote, iclass 23, count 0 2006.224.08:21:59.82#ibcon#about to read 3, iclass 23, count 0 2006.224.08:21:59.85#ibcon#read 3, iclass 23, count 0 2006.224.08:21:59.85#ibcon#about to read 4, iclass 23, count 0 2006.224.08:21:59.85#ibcon#read 4, iclass 23, count 0 2006.224.08:21:59.85#ibcon#about to read 5, iclass 23, count 0 2006.224.08:21:59.85#ibcon#read 5, iclass 23, count 0 2006.224.08:21:59.85#ibcon#about to read 6, iclass 23, count 0 2006.224.08:21:59.85#ibcon#read 6, iclass 23, count 0 2006.224.08:21:59.85#ibcon#end of sib2, iclass 23, count 0 2006.224.08:21:59.85#ibcon#*after write, iclass 23, count 0 2006.224.08:21:59.85#ibcon#*before return 0, iclass 23, count 0 2006.224.08:21:59.85#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.224.08:21:59.85#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.224.08:21:59.85#ibcon#about to clear, iclass 23 cls_cnt 0 2006.224.08:21:59.85#ibcon#cleared, iclass 23 cls_cnt 0 2006.224.08:21:59.85$vc4f8/valo=7,832.99 2006.224.08:21:59.85#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.224.08:21:59.85#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.224.08:21:59.85#ibcon#ireg 17 cls_cnt 0 2006.224.08:21:59.85#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.224.08:21:59.85#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.224.08:21:59.85#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.224.08:21:59.85#ibcon#enter wrdev, iclass 25, count 0 2006.224.08:21:59.85#ibcon#first serial, iclass 25, count 0 2006.224.08:21:59.85#ibcon#enter sib2, iclass 25, count 0 2006.224.08:21:59.85#ibcon#flushed, iclass 25, count 0 2006.224.08:21:59.85#ibcon#about to write, iclass 25, count 0 2006.224.08:21:59.85#ibcon#wrote, iclass 25, count 0 2006.224.08:21:59.85#ibcon#about to read 3, iclass 25, count 0 2006.224.08:21:59.87#ibcon#read 3, iclass 25, count 0 2006.224.08:21:59.87#ibcon#about to read 4, iclass 25, count 0 2006.224.08:21:59.87#ibcon#read 4, iclass 25, count 0 2006.224.08:21:59.87#ibcon#about to read 5, iclass 25, count 0 2006.224.08:21:59.87#ibcon#read 5, iclass 25, count 0 2006.224.08:21:59.87#ibcon#about to read 6, iclass 25, count 0 2006.224.08:21:59.87#ibcon#read 6, iclass 25, count 0 2006.224.08:21:59.87#ibcon#end of sib2, iclass 25, count 0 2006.224.08:21:59.87#ibcon#*mode == 0, iclass 25, count 0 2006.224.08:21:59.87#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.224.08:21:59.87#ibcon#[26=FRQ=07,832.99\r\n] 2006.224.08:21:59.87#ibcon#*before write, iclass 25, count 0 2006.224.08:21:59.87#ibcon#enter sib2, iclass 25, count 0 2006.224.08:21:59.87#ibcon#flushed, iclass 25, count 0 2006.224.08:21:59.87#ibcon#about to write, iclass 25, count 0 2006.224.08:21:59.87#ibcon#wrote, iclass 25, count 0 2006.224.08:21:59.87#ibcon#about to read 3, iclass 25, count 0 2006.224.08:21:59.91#ibcon#read 3, iclass 25, count 0 2006.224.08:21:59.91#ibcon#about to read 4, iclass 25, count 0 2006.224.08:21:59.91#ibcon#read 4, iclass 25, count 0 2006.224.08:21:59.91#ibcon#about to read 5, iclass 25, count 0 2006.224.08:21:59.91#ibcon#read 5, iclass 25, count 0 2006.224.08:21:59.91#ibcon#about to read 6, iclass 25, count 0 2006.224.08:21:59.91#ibcon#read 6, iclass 25, count 0 2006.224.08:21:59.91#ibcon#end of sib2, iclass 25, count 0 2006.224.08:21:59.91#ibcon#*after write, iclass 25, count 0 2006.224.08:21:59.91#ibcon#*before return 0, iclass 25, count 0 2006.224.08:21:59.91#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.224.08:21:59.91#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.224.08:21:59.91#ibcon#about to clear, iclass 25 cls_cnt 0 2006.224.08:21:59.91#ibcon#cleared, iclass 25 cls_cnt 0 2006.224.08:21:59.91$vc4f8/va=7,6 2006.224.08:21:59.91#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.224.08:21:59.91#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.224.08:21:59.91#ibcon#ireg 11 cls_cnt 2 2006.224.08:21:59.91#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.224.08:21:59.97#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.224.08:21:59.97#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.224.08:21:59.97#ibcon#enter wrdev, iclass 27, count 2 2006.224.08:21:59.97#ibcon#first serial, iclass 27, count 2 2006.224.08:21:59.97#ibcon#enter sib2, iclass 27, count 2 2006.224.08:21:59.97#ibcon#flushed, iclass 27, count 2 2006.224.08:21:59.97#ibcon#about to write, iclass 27, count 2 2006.224.08:21:59.97#ibcon#wrote, iclass 27, count 2 2006.224.08:21:59.97#ibcon#about to read 3, iclass 27, count 2 2006.224.08:21:59.99#ibcon#read 3, iclass 27, count 2 2006.224.08:21:59.99#ibcon#about to read 4, iclass 27, count 2 2006.224.08:21:59.99#ibcon#read 4, iclass 27, count 2 2006.224.08:21:59.99#ibcon#about to read 5, iclass 27, count 2 2006.224.08:21:59.99#ibcon#read 5, iclass 27, count 2 2006.224.08:21:59.99#ibcon#about to read 6, iclass 27, count 2 2006.224.08:21:59.99#ibcon#read 6, iclass 27, count 2 2006.224.08:21:59.99#ibcon#end of sib2, iclass 27, count 2 2006.224.08:21:59.99#ibcon#*mode == 0, iclass 27, count 2 2006.224.08:21:59.99#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.224.08:21:59.99#ibcon#[25=AT07-06\r\n] 2006.224.08:21:59.99#ibcon#*before write, iclass 27, count 2 2006.224.08:21:59.99#ibcon#enter sib2, iclass 27, count 2 2006.224.08:21:59.99#ibcon#flushed, iclass 27, count 2 2006.224.08:21:59.99#ibcon#about to write, iclass 27, count 2 2006.224.08:21:59.99#ibcon#wrote, iclass 27, count 2 2006.224.08:21:59.99#ibcon#about to read 3, iclass 27, count 2 2006.224.08:22:00.02#ibcon#read 3, iclass 27, count 2 2006.224.08:22:00.02#ibcon#about to read 4, iclass 27, count 2 2006.224.08:22:00.02#ibcon#read 4, iclass 27, count 2 2006.224.08:22:00.02#ibcon#about to read 5, iclass 27, count 2 2006.224.08:22:00.02#ibcon#read 5, iclass 27, count 2 2006.224.08:22:00.02#ibcon#about to read 6, iclass 27, count 2 2006.224.08:22:00.02#ibcon#read 6, iclass 27, count 2 2006.224.08:22:00.02#ibcon#end of sib2, iclass 27, count 2 2006.224.08:22:00.02#ibcon#*after write, iclass 27, count 2 2006.224.08:22:00.02#ibcon#*before return 0, iclass 27, count 2 2006.224.08:22:00.02#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.224.08:22:00.02#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.224.08:22:00.02#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.224.08:22:00.02#ibcon#ireg 7 cls_cnt 0 2006.224.08:22:00.02#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.224.08:22:00.14#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.224.08:22:00.14#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.224.08:22:00.14#ibcon#enter wrdev, iclass 27, count 0 2006.224.08:22:00.14#ibcon#first serial, iclass 27, count 0 2006.224.08:22:00.14#ibcon#enter sib2, iclass 27, count 0 2006.224.08:22:00.14#ibcon#flushed, iclass 27, count 0 2006.224.08:22:00.14#ibcon#about to write, iclass 27, count 0 2006.224.08:22:00.14#ibcon#wrote, iclass 27, count 0 2006.224.08:22:00.14#ibcon#about to read 3, iclass 27, count 0 2006.224.08:22:00.16#ibcon#read 3, iclass 27, count 0 2006.224.08:22:00.16#ibcon#about to read 4, iclass 27, count 0 2006.224.08:22:00.16#ibcon#read 4, iclass 27, count 0 2006.224.08:22:00.16#ibcon#about to read 5, iclass 27, count 0 2006.224.08:22:00.16#ibcon#read 5, iclass 27, count 0 2006.224.08:22:00.16#ibcon#about to read 6, iclass 27, count 0 2006.224.08:22:00.16#ibcon#read 6, iclass 27, count 0 2006.224.08:22:00.16#ibcon#end of sib2, iclass 27, count 0 2006.224.08:22:00.16#ibcon#*mode == 0, iclass 27, count 0 2006.224.08:22:00.16#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.224.08:22:00.16#ibcon#[25=USB\r\n] 2006.224.08:22:00.16#ibcon#*before write, iclass 27, count 0 2006.224.08:22:00.16#ibcon#enter sib2, iclass 27, count 0 2006.224.08:22:00.16#ibcon#flushed, iclass 27, count 0 2006.224.08:22:00.16#ibcon#about to write, iclass 27, count 0 2006.224.08:22:00.16#ibcon#wrote, iclass 27, count 0 2006.224.08:22:00.16#ibcon#about to read 3, iclass 27, count 0 2006.224.08:22:00.19#ibcon#read 3, iclass 27, count 0 2006.224.08:22:00.19#ibcon#about to read 4, iclass 27, count 0 2006.224.08:22:00.19#ibcon#read 4, iclass 27, count 0 2006.224.08:22:00.19#ibcon#about to read 5, iclass 27, count 0 2006.224.08:22:00.19#ibcon#read 5, iclass 27, count 0 2006.224.08:22:00.19#ibcon#about to read 6, iclass 27, count 0 2006.224.08:22:00.19#ibcon#read 6, iclass 27, count 0 2006.224.08:22:00.19#ibcon#end of sib2, iclass 27, count 0 2006.224.08:22:00.19#ibcon#*after write, iclass 27, count 0 2006.224.08:22:00.19#ibcon#*before return 0, iclass 27, count 0 2006.224.08:22:00.19#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.224.08:22:00.19#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.224.08:22:00.19#ibcon#about to clear, iclass 27 cls_cnt 0 2006.224.08:22:00.19#ibcon#cleared, iclass 27 cls_cnt 0 2006.224.08:22:00.19$vc4f8/valo=8,852.99 2006.224.08:22:00.19#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.224.08:22:00.19#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.224.08:22:00.19#ibcon#ireg 17 cls_cnt 0 2006.224.08:22:00.19#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.224.08:22:00.19#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.224.08:22:00.19#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.224.08:22:00.19#ibcon#enter wrdev, iclass 29, count 0 2006.224.08:22:00.19#ibcon#first serial, iclass 29, count 0 2006.224.08:22:00.19#ibcon#enter sib2, iclass 29, count 0 2006.224.08:22:00.19#ibcon#flushed, iclass 29, count 0 2006.224.08:22:00.19#ibcon#about to write, iclass 29, count 0 2006.224.08:22:00.19#ibcon#wrote, iclass 29, count 0 2006.224.08:22:00.19#ibcon#about to read 3, iclass 29, count 0 2006.224.08:22:00.21#ibcon#read 3, iclass 29, count 0 2006.224.08:22:00.21#ibcon#about to read 4, iclass 29, count 0 2006.224.08:22:00.21#ibcon#read 4, iclass 29, count 0 2006.224.08:22:00.21#ibcon#about to read 5, iclass 29, count 0 2006.224.08:22:00.21#ibcon#read 5, iclass 29, count 0 2006.224.08:22:00.21#ibcon#about to read 6, iclass 29, count 0 2006.224.08:22:00.21#ibcon#read 6, iclass 29, count 0 2006.224.08:22:00.21#ibcon#end of sib2, iclass 29, count 0 2006.224.08:22:00.21#ibcon#*mode == 0, iclass 29, count 0 2006.224.08:22:00.21#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.224.08:22:00.21#ibcon#[26=FRQ=08,852.99\r\n] 2006.224.08:22:00.21#ibcon#*before write, iclass 29, count 0 2006.224.08:22:00.21#ibcon#enter sib2, iclass 29, count 0 2006.224.08:22:00.21#ibcon#flushed, iclass 29, count 0 2006.224.08:22:00.21#ibcon#about to write, iclass 29, count 0 2006.224.08:22:00.21#ibcon#wrote, iclass 29, count 0 2006.224.08:22:00.21#ibcon#about to read 3, iclass 29, count 0 2006.224.08:22:00.25#ibcon#read 3, iclass 29, count 0 2006.224.08:22:00.25#ibcon#about to read 4, iclass 29, count 0 2006.224.08:22:00.25#ibcon#read 4, iclass 29, count 0 2006.224.08:22:00.25#ibcon#about to read 5, iclass 29, count 0 2006.224.08:22:00.25#ibcon#read 5, iclass 29, count 0 2006.224.08:22:00.25#ibcon#about to read 6, iclass 29, count 0 2006.224.08:22:00.25#ibcon#read 6, iclass 29, count 0 2006.224.08:22:00.25#ibcon#end of sib2, iclass 29, count 0 2006.224.08:22:00.25#ibcon#*after write, iclass 29, count 0 2006.224.08:22:00.25#ibcon#*before return 0, iclass 29, count 0 2006.224.08:22:00.25#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.224.08:22:00.25#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.224.08:22:00.25#ibcon#about to clear, iclass 29 cls_cnt 0 2006.224.08:22:00.25#ibcon#cleared, iclass 29 cls_cnt 0 2006.224.08:22:00.25$vc4f8/va=8,7 2006.224.08:22:00.25#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.224.08:22:00.25#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.224.08:22:00.25#ibcon#ireg 11 cls_cnt 2 2006.224.08:22:00.25#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.224.08:22:00.31#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.224.08:22:00.31#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.224.08:22:00.31#ibcon#enter wrdev, iclass 31, count 2 2006.224.08:22:00.31#ibcon#first serial, iclass 31, count 2 2006.224.08:22:00.31#ibcon#enter sib2, iclass 31, count 2 2006.224.08:22:00.31#ibcon#flushed, iclass 31, count 2 2006.224.08:22:00.31#ibcon#about to write, iclass 31, count 2 2006.224.08:22:00.31#ibcon#wrote, iclass 31, count 2 2006.224.08:22:00.31#ibcon#about to read 3, iclass 31, count 2 2006.224.08:22:00.33#ibcon#read 3, iclass 31, count 2 2006.224.08:22:00.33#ibcon#about to read 4, iclass 31, count 2 2006.224.08:22:00.33#ibcon#read 4, iclass 31, count 2 2006.224.08:22:00.33#ibcon#about to read 5, iclass 31, count 2 2006.224.08:22:00.33#ibcon#read 5, iclass 31, count 2 2006.224.08:22:00.33#ibcon#about to read 6, iclass 31, count 2 2006.224.08:22:00.33#ibcon#read 6, iclass 31, count 2 2006.224.08:22:00.33#ibcon#end of sib2, iclass 31, count 2 2006.224.08:22:00.33#ibcon#*mode == 0, iclass 31, count 2 2006.224.08:22:00.33#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.224.08:22:00.33#ibcon#[25=AT08-07\r\n] 2006.224.08:22:00.33#ibcon#*before write, iclass 31, count 2 2006.224.08:22:00.33#ibcon#enter sib2, iclass 31, count 2 2006.224.08:22:00.33#ibcon#flushed, iclass 31, count 2 2006.224.08:22:00.33#ibcon#about to write, iclass 31, count 2 2006.224.08:22:00.33#ibcon#wrote, iclass 31, count 2 2006.224.08:22:00.33#ibcon#about to read 3, iclass 31, count 2 2006.224.08:22:00.36#ibcon#read 3, iclass 31, count 2 2006.224.08:22:00.36#ibcon#about to read 4, iclass 31, count 2 2006.224.08:22:00.36#ibcon#read 4, iclass 31, count 2 2006.224.08:22:00.36#ibcon#about to read 5, iclass 31, count 2 2006.224.08:22:00.36#ibcon#read 5, iclass 31, count 2 2006.224.08:22:00.36#ibcon#about to read 6, iclass 31, count 2 2006.224.08:22:00.36#ibcon#read 6, iclass 31, count 2 2006.224.08:22:00.36#ibcon#end of sib2, iclass 31, count 2 2006.224.08:22:00.36#ibcon#*after write, iclass 31, count 2 2006.224.08:22:00.36#ibcon#*before return 0, iclass 31, count 2 2006.224.08:22:00.36#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.224.08:22:00.36#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.224.08:22:00.36#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.224.08:22:00.36#ibcon#ireg 7 cls_cnt 0 2006.224.08:22:00.36#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.224.08:22:00.48#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.224.08:22:00.48#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.224.08:22:00.48#ibcon#enter wrdev, iclass 31, count 0 2006.224.08:22:00.48#ibcon#first serial, iclass 31, count 0 2006.224.08:22:00.48#ibcon#enter sib2, iclass 31, count 0 2006.224.08:22:00.48#ibcon#flushed, iclass 31, count 0 2006.224.08:22:00.48#ibcon#about to write, iclass 31, count 0 2006.224.08:22:00.48#ibcon#wrote, iclass 31, count 0 2006.224.08:22:00.48#ibcon#about to read 3, iclass 31, count 0 2006.224.08:22:00.50#ibcon#read 3, iclass 31, count 0 2006.224.08:22:00.50#ibcon#about to read 4, iclass 31, count 0 2006.224.08:22:00.50#ibcon#read 4, iclass 31, count 0 2006.224.08:22:00.50#ibcon#about to read 5, iclass 31, count 0 2006.224.08:22:00.50#ibcon#read 5, iclass 31, count 0 2006.224.08:22:00.50#ibcon#about to read 6, iclass 31, count 0 2006.224.08:22:00.50#ibcon#read 6, iclass 31, count 0 2006.224.08:22:00.50#ibcon#end of sib2, iclass 31, count 0 2006.224.08:22:00.50#ibcon#*mode == 0, iclass 31, count 0 2006.224.08:22:00.50#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.224.08:22:00.50#ibcon#[25=USB\r\n] 2006.224.08:22:00.50#ibcon#*before write, iclass 31, count 0 2006.224.08:22:00.50#ibcon#enter sib2, iclass 31, count 0 2006.224.08:22:00.50#ibcon#flushed, iclass 31, count 0 2006.224.08:22:00.50#ibcon#about to write, iclass 31, count 0 2006.224.08:22:00.50#ibcon#wrote, iclass 31, count 0 2006.224.08:22:00.50#ibcon#about to read 3, iclass 31, count 0 2006.224.08:22:00.53#ibcon#read 3, iclass 31, count 0 2006.224.08:22:00.53#ibcon#about to read 4, iclass 31, count 0 2006.224.08:22:00.53#ibcon#read 4, iclass 31, count 0 2006.224.08:22:00.53#ibcon#about to read 5, iclass 31, count 0 2006.224.08:22:00.53#ibcon#read 5, iclass 31, count 0 2006.224.08:22:00.53#ibcon#about to read 6, iclass 31, count 0 2006.224.08:22:00.53#ibcon#read 6, iclass 31, count 0 2006.224.08:22:00.53#ibcon#end of sib2, iclass 31, count 0 2006.224.08:22:00.53#ibcon#*after write, iclass 31, count 0 2006.224.08:22:00.53#ibcon#*before return 0, iclass 31, count 0 2006.224.08:22:00.53#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.224.08:22:00.53#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.224.08:22:00.53#ibcon#about to clear, iclass 31 cls_cnt 0 2006.224.08:22:00.53#ibcon#cleared, iclass 31 cls_cnt 0 2006.224.08:22:00.53$vc4f8/vblo=1,632.99 2006.224.08:22:00.53#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.224.08:22:00.53#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.224.08:22:00.53#ibcon#ireg 17 cls_cnt 0 2006.224.08:22:00.53#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.224.08:22:00.53#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.224.08:22:00.53#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.224.08:22:00.53#ibcon#enter wrdev, iclass 33, count 0 2006.224.08:22:00.53#ibcon#first serial, iclass 33, count 0 2006.224.08:22:00.53#ibcon#enter sib2, iclass 33, count 0 2006.224.08:22:00.53#ibcon#flushed, iclass 33, count 0 2006.224.08:22:00.53#ibcon#about to write, iclass 33, count 0 2006.224.08:22:00.53#ibcon#wrote, iclass 33, count 0 2006.224.08:22:00.53#ibcon#about to read 3, iclass 33, count 0 2006.224.08:22:00.55#ibcon#read 3, iclass 33, count 0 2006.224.08:22:00.55#ibcon#about to read 4, iclass 33, count 0 2006.224.08:22:00.55#ibcon#read 4, iclass 33, count 0 2006.224.08:22:00.55#ibcon#about to read 5, iclass 33, count 0 2006.224.08:22:00.55#ibcon#read 5, iclass 33, count 0 2006.224.08:22:00.55#ibcon#about to read 6, iclass 33, count 0 2006.224.08:22:00.55#ibcon#read 6, iclass 33, count 0 2006.224.08:22:00.55#ibcon#end of sib2, iclass 33, count 0 2006.224.08:22:00.55#ibcon#*mode == 0, iclass 33, count 0 2006.224.08:22:00.55#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.224.08:22:00.55#ibcon#[28=FRQ=01,632.99\r\n] 2006.224.08:22:00.55#ibcon#*before write, iclass 33, count 0 2006.224.08:22:00.55#ibcon#enter sib2, iclass 33, count 0 2006.224.08:22:00.55#ibcon#flushed, iclass 33, count 0 2006.224.08:22:00.55#ibcon#about to write, iclass 33, count 0 2006.224.08:22:00.55#ibcon#wrote, iclass 33, count 0 2006.224.08:22:00.55#ibcon#about to read 3, iclass 33, count 0 2006.224.08:22:00.59#ibcon#read 3, iclass 33, count 0 2006.224.08:22:00.59#ibcon#about to read 4, iclass 33, count 0 2006.224.08:22:00.59#ibcon#read 4, iclass 33, count 0 2006.224.08:22:00.59#ibcon#about to read 5, iclass 33, count 0 2006.224.08:22:00.59#ibcon#read 5, iclass 33, count 0 2006.224.08:22:00.59#ibcon#about to read 6, iclass 33, count 0 2006.224.08:22:00.59#ibcon#read 6, iclass 33, count 0 2006.224.08:22:00.59#ibcon#end of sib2, iclass 33, count 0 2006.224.08:22:00.59#ibcon#*after write, iclass 33, count 0 2006.224.08:22:00.59#ibcon#*before return 0, iclass 33, count 0 2006.224.08:22:00.59#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.224.08:22:00.59#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.224.08:22:00.59#ibcon#about to clear, iclass 33 cls_cnt 0 2006.224.08:22:00.59#ibcon#cleared, iclass 33 cls_cnt 0 2006.224.08:22:00.59$vc4f8/vb=1,4 2006.224.08:22:00.59#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.224.08:22:00.59#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.224.08:22:00.59#ibcon#ireg 11 cls_cnt 2 2006.224.08:22:00.59#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.224.08:22:00.59#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.224.08:22:00.59#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.224.08:22:00.59#ibcon#enter wrdev, iclass 35, count 2 2006.224.08:22:00.59#ibcon#first serial, iclass 35, count 2 2006.224.08:22:00.59#ibcon#enter sib2, iclass 35, count 2 2006.224.08:22:00.59#ibcon#flushed, iclass 35, count 2 2006.224.08:22:00.59#ibcon#about to write, iclass 35, count 2 2006.224.08:22:00.59#ibcon#wrote, iclass 35, count 2 2006.224.08:22:00.59#ibcon#about to read 3, iclass 35, count 2 2006.224.08:22:00.61#ibcon#read 3, iclass 35, count 2 2006.224.08:22:00.61#ibcon#about to read 4, iclass 35, count 2 2006.224.08:22:00.61#ibcon#read 4, iclass 35, count 2 2006.224.08:22:00.61#ibcon#about to read 5, iclass 35, count 2 2006.224.08:22:00.61#ibcon#read 5, iclass 35, count 2 2006.224.08:22:00.61#ibcon#about to read 6, iclass 35, count 2 2006.224.08:22:00.61#ibcon#read 6, iclass 35, count 2 2006.224.08:22:00.61#ibcon#end of sib2, iclass 35, count 2 2006.224.08:22:00.61#ibcon#*mode == 0, iclass 35, count 2 2006.224.08:22:00.61#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.224.08:22:00.61#ibcon#[27=AT01-04\r\n] 2006.224.08:22:00.61#ibcon#*before write, iclass 35, count 2 2006.224.08:22:00.61#ibcon#enter sib2, iclass 35, count 2 2006.224.08:22:00.61#ibcon#flushed, iclass 35, count 2 2006.224.08:22:00.61#ibcon#about to write, iclass 35, count 2 2006.224.08:22:00.61#ibcon#wrote, iclass 35, count 2 2006.224.08:22:00.61#ibcon#about to read 3, iclass 35, count 2 2006.224.08:22:00.65#ibcon#read 3, iclass 35, count 2 2006.224.08:22:00.65#ibcon#about to read 4, iclass 35, count 2 2006.224.08:22:00.65#ibcon#read 4, iclass 35, count 2 2006.224.08:22:00.65#ibcon#about to read 5, iclass 35, count 2 2006.224.08:22:00.65#ibcon#read 5, iclass 35, count 2 2006.224.08:22:00.65#ibcon#about to read 6, iclass 35, count 2 2006.224.08:22:00.65#ibcon#read 6, iclass 35, count 2 2006.224.08:22:00.65#ibcon#end of sib2, iclass 35, count 2 2006.224.08:22:00.65#ibcon#*after write, iclass 35, count 2 2006.224.08:22:00.65#ibcon#*before return 0, iclass 35, count 2 2006.224.08:22:00.65#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.224.08:22:00.65#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.224.08:22:00.65#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.224.08:22:00.65#ibcon#ireg 7 cls_cnt 0 2006.224.08:22:00.65#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.224.08:22:00.76#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.224.08:22:00.76#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.224.08:22:00.76#ibcon#enter wrdev, iclass 35, count 0 2006.224.08:22:00.76#ibcon#first serial, iclass 35, count 0 2006.224.08:22:00.76#ibcon#enter sib2, iclass 35, count 0 2006.224.08:22:00.76#ibcon#flushed, iclass 35, count 0 2006.224.08:22:00.76#ibcon#about to write, iclass 35, count 0 2006.224.08:22:00.76#ibcon#wrote, iclass 35, count 0 2006.224.08:22:00.76#ibcon#about to read 3, iclass 35, count 0 2006.224.08:22:00.78#ibcon#read 3, iclass 35, count 0 2006.224.08:22:00.78#ibcon#about to read 4, iclass 35, count 0 2006.224.08:22:00.78#ibcon#read 4, iclass 35, count 0 2006.224.08:22:00.78#ibcon#about to read 5, iclass 35, count 0 2006.224.08:22:00.78#ibcon#read 5, iclass 35, count 0 2006.224.08:22:00.78#ibcon#about to read 6, iclass 35, count 0 2006.224.08:22:00.78#ibcon#read 6, iclass 35, count 0 2006.224.08:22:00.78#ibcon#end of sib2, iclass 35, count 0 2006.224.08:22:00.78#ibcon#*mode == 0, iclass 35, count 0 2006.224.08:22:00.78#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.224.08:22:00.78#ibcon#[27=USB\r\n] 2006.224.08:22:00.78#ibcon#*before write, iclass 35, count 0 2006.224.08:22:00.78#ibcon#enter sib2, iclass 35, count 0 2006.224.08:22:00.78#ibcon#flushed, iclass 35, count 0 2006.224.08:22:00.78#ibcon#about to write, iclass 35, count 0 2006.224.08:22:00.78#ibcon#wrote, iclass 35, count 0 2006.224.08:22:00.78#ibcon#about to read 3, iclass 35, count 0 2006.224.08:22:00.81#ibcon#read 3, iclass 35, count 0 2006.224.08:22:00.81#ibcon#about to read 4, iclass 35, count 0 2006.224.08:22:00.81#ibcon#read 4, iclass 35, count 0 2006.224.08:22:00.81#ibcon#about to read 5, iclass 35, count 0 2006.224.08:22:00.81#ibcon#read 5, iclass 35, count 0 2006.224.08:22:00.81#ibcon#about to read 6, iclass 35, count 0 2006.224.08:22:00.81#ibcon#read 6, iclass 35, count 0 2006.224.08:22:00.81#ibcon#end of sib2, iclass 35, count 0 2006.224.08:22:00.81#ibcon#*after write, iclass 35, count 0 2006.224.08:22:00.81#ibcon#*before return 0, iclass 35, count 0 2006.224.08:22:00.81#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.224.08:22:00.81#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.224.08:22:00.81#ibcon#about to clear, iclass 35 cls_cnt 0 2006.224.08:22:00.81#ibcon#cleared, iclass 35 cls_cnt 0 2006.224.08:22:00.81$vc4f8/vblo=2,640.99 2006.224.08:22:00.81#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.224.08:22:00.81#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.224.08:22:00.81#ibcon#ireg 17 cls_cnt 0 2006.224.08:22:00.81#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.224.08:22:00.81#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.224.08:22:00.81#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.224.08:22:00.81#ibcon#enter wrdev, iclass 37, count 0 2006.224.08:22:00.81#ibcon#first serial, iclass 37, count 0 2006.224.08:22:00.81#ibcon#enter sib2, iclass 37, count 0 2006.224.08:22:00.81#ibcon#flushed, iclass 37, count 0 2006.224.08:22:00.81#ibcon#about to write, iclass 37, count 0 2006.224.08:22:00.81#ibcon#wrote, iclass 37, count 0 2006.224.08:22:00.81#ibcon#about to read 3, iclass 37, count 0 2006.224.08:22:00.83#ibcon#read 3, iclass 37, count 0 2006.224.08:22:00.83#ibcon#about to read 4, iclass 37, count 0 2006.224.08:22:00.83#ibcon#read 4, iclass 37, count 0 2006.224.08:22:00.83#ibcon#about to read 5, iclass 37, count 0 2006.224.08:22:00.83#ibcon#read 5, iclass 37, count 0 2006.224.08:22:00.83#ibcon#about to read 6, iclass 37, count 0 2006.224.08:22:00.83#ibcon#read 6, iclass 37, count 0 2006.224.08:22:00.83#ibcon#end of sib2, iclass 37, count 0 2006.224.08:22:00.83#ibcon#*mode == 0, iclass 37, count 0 2006.224.08:22:00.83#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.224.08:22:00.83#ibcon#[28=FRQ=02,640.99\r\n] 2006.224.08:22:00.83#ibcon#*before write, iclass 37, count 0 2006.224.08:22:00.83#ibcon#enter sib2, iclass 37, count 0 2006.224.08:22:00.83#ibcon#flushed, iclass 37, count 0 2006.224.08:22:00.83#ibcon#about to write, iclass 37, count 0 2006.224.08:22:00.83#ibcon#wrote, iclass 37, count 0 2006.224.08:22:00.83#ibcon#about to read 3, iclass 37, count 0 2006.224.08:22:00.87#ibcon#read 3, iclass 37, count 0 2006.224.08:22:00.87#ibcon#about to read 4, iclass 37, count 0 2006.224.08:22:00.87#ibcon#read 4, iclass 37, count 0 2006.224.08:22:00.87#ibcon#about to read 5, iclass 37, count 0 2006.224.08:22:00.87#ibcon#read 5, iclass 37, count 0 2006.224.08:22:00.87#ibcon#about to read 6, iclass 37, count 0 2006.224.08:22:00.87#ibcon#read 6, iclass 37, count 0 2006.224.08:22:00.87#ibcon#end of sib2, iclass 37, count 0 2006.224.08:22:00.87#ibcon#*after write, iclass 37, count 0 2006.224.08:22:00.87#ibcon#*before return 0, iclass 37, count 0 2006.224.08:22:00.87#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.224.08:22:00.87#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.224.08:22:00.87#ibcon#about to clear, iclass 37 cls_cnt 0 2006.224.08:22:00.87#ibcon#cleared, iclass 37 cls_cnt 0 2006.224.08:22:00.87$vc4f8/vb=2,4 2006.224.08:22:00.87#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.224.08:22:00.87#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.224.08:22:00.87#ibcon#ireg 11 cls_cnt 2 2006.224.08:22:00.87#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.224.08:22:00.93#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.224.08:22:00.93#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.224.08:22:00.93#ibcon#enter wrdev, iclass 39, count 2 2006.224.08:22:00.93#ibcon#first serial, iclass 39, count 2 2006.224.08:22:00.93#ibcon#enter sib2, iclass 39, count 2 2006.224.08:22:00.93#ibcon#flushed, iclass 39, count 2 2006.224.08:22:00.93#ibcon#about to write, iclass 39, count 2 2006.224.08:22:00.93#ibcon#wrote, iclass 39, count 2 2006.224.08:22:00.93#ibcon#about to read 3, iclass 39, count 2 2006.224.08:22:00.95#ibcon#read 3, iclass 39, count 2 2006.224.08:22:00.95#ibcon#about to read 4, iclass 39, count 2 2006.224.08:22:00.95#ibcon#read 4, iclass 39, count 2 2006.224.08:22:00.95#ibcon#about to read 5, iclass 39, count 2 2006.224.08:22:00.95#ibcon#read 5, iclass 39, count 2 2006.224.08:22:00.95#ibcon#about to read 6, iclass 39, count 2 2006.224.08:22:00.95#ibcon#read 6, iclass 39, count 2 2006.224.08:22:00.95#ibcon#end of sib2, iclass 39, count 2 2006.224.08:22:00.95#ibcon#*mode == 0, iclass 39, count 2 2006.224.08:22:00.95#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.224.08:22:00.95#ibcon#[27=AT02-04\r\n] 2006.224.08:22:00.95#ibcon#*before write, iclass 39, count 2 2006.224.08:22:00.95#ibcon#enter sib2, iclass 39, count 2 2006.224.08:22:00.95#ibcon#flushed, iclass 39, count 2 2006.224.08:22:00.95#ibcon#about to write, iclass 39, count 2 2006.224.08:22:00.95#ibcon#wrote, iclass 39, count 2 2006.224.08:22:00.95#ibcon#about to read 3, iclass 39, count 2 2006.224.08:22:00.98#ibcon#read 3, iclass 39, count 2 2006.224.08:22:00.98#ibcon#about to read 4, iclass 39, count 2 2006.224.08:22:00.98#ibcon#read 4, iclass 39, count 2 2006.224.08:22:00.98#ibcon#about to read 5, iclass 39, count 2 2006.224.08:22:00.98#ibcon#read 5, iclass 39, count 2 2006.224.08:22:00.98#ibcon#about to read 6, iclass 39, count 2 2006.224.08:22:00.98#ibcon#read 6, iclass 39, count 2 2006.224.08:22:00.98#ibcon#end of sib2, iclass 39, count 2 2006.224.08:22:00.98#ibcon#*after write, iclass 39, count 2 2006.224.08:22:00.98#ibcon#*before return 0, iclass 39, count 2 2006.224.08:22:00.98#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.224.08:22:00.98#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.224.08:22:00.98#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.224.08:22:00.98#ibcon#ireg 7 cls_cnt 0 2006.224.08:22:00.98#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.224.08:22:01.10#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.224.08:22:01.10#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.224.08:22:01.10#ibcon#enter wrdev, iclass 39, count 0 2006.224.08:22:01.10#ibcon#first serial, iclass 39, count 0 2006.224.08:22:01.10#ibcon#enter sib2, iclass 39, count 0 2006.224.08:22:01.10#ibcon#flushed, iclass 39, count 0 2006.224.08:22:01.10#ibcon#about to write, iclass 39, count 0 2006.224.08:22:01.10#ibcon#wrote, iclass 39, count 0 2006.224.08:22:01.10#ibcon#about to read 3, iclass 39, count 0 2006.224.08:22:01.12#ibcon#read 3, iclass 39, count 0 2006.224.08:22:01.12#ibcon#about to read 4, iclass 39, count 0 2006.224.08:22:01.12#ibcon#read 4, iclass 39, count 0 2006.224.08:22:01.12#ibcon#about to read 5, iclass 39, count 0 2006.224.08:22:01.12#ibcon#read 5, iclass 39, count 0 2006.224.08:22:01.12#ibcon#about to read 6, iclass 39, count 0 2006.224.08:22:01.12#ibcon#read 6, iclass 39, count 0 2006.224.08:22:01.12#ibcon#end of sib2, iclass 39, count 0 2006.224.08:22:01.12#ibcon#*mode == 0, iclass 39, count 0 2006.224.08:22:01.12#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.224.08:22:01.12#ibcon#[27=USB\r\n] 2006.224.08:22:01.12#ibcon#*before write, iclass 39, count 0 2006.224.08:22:01.12#ibcon#enter sib2, iclass 39, count 0 2006.224.08:22:01.12#ibcon#flushed, iclass 39, count 0 2006.224.08:22:01.12#ibcon#about to write, iclass 39, count 0 2006.224.08:22:01.12#ibcon#wrote, iclass 39, count 0 2006.224.08:22:01.12#ibcon#about to read 3, iclass 39, count 0 2006.224.08:22:01.15#ibcon#read 3, iclass 39, count 0 2006.224.08:22:01.15#ibcon#about to read 4, iclass 39, count 0 2006.224.08:22:01.15#ibcon#read 4, iclass 39, count 0 2006.224.08:22:01.15#ibcon#about to read 5, iclass 39, count 0 2006.224.08:22:01.15#ibcon#read 5, iclass 39, count 0 2006.224.08:22:01.15#ibcon#about to read 6, iclass 39, count 0 2006.224.08:22:01.15#ibcon#read 6, iclass 39, count 0 2006.224.08:22:01.15#ibcon#end of sib2, iclass 39, count 0 2006.224.08:22:01.15#ibcon#*after write, iclass 39, count 0 2006.224.08:22:01.15#ibcon#*before return 0, iclass 39, count 0 2006.224.08:22:01.15#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.224.08:22:01.15#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.224.08:22:01.15#ibcon#about to clear, iclass 39 cls_cnt 0 2006.224.08:22:01.15#ibcon#cleared, iclass 39 cls_cnt 0 2006.224.08:22:01.15$vc4f8/vblo=3,656.99 2006.224.08:22:01.15#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.224.08:22:01.15#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.224.08:22:01.15#ibcon#ireg 17 cls_cnt 0 2006.224.08:22:01.15#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.224.08:22:01.15#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.224.08:22:01.15#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.224.08:22:01.15#ibcon#enter wrdev, iclass 3, count 0 2006.224.08:22:01.15#ibcon#first serial, iclass 3, count 0 2006.224.08:22:01.15#ibcon#enter sib2, iclass 3, count 0 2006.224.08:22:01.15#ibcon#flushed, iclass 3, count 0 2006.224.08:22:01.15#ibcon#about to write, iclass 3, count 0 2006.224.08:22:01.15#ibcon#wrote, iclass 3, count 0 2006.224.08:22:01.15#ibcon#about to read 3, iclass 3, count 0 2006.224.08:22:01.17#ibcon#read 3, iclass 3, count 0 2006.224.08:22:01.17#ibcon#about to read 4, iclass 3, count 0 2006.224.08:22:01.17#ibcon#read 4, iclass 3, count 0 2006.224.08:22:01.17#ibcon#about to read 5, iclass 3, count 0 2006.224.08:22:01.17#ibcon#read 5, iclass 3, count 0 2006.224.08:22:01.17#ibcon#about to read 6, iclass 3, count 0 2006.224.08:22:01.17#ibcon#read 6, iclass 3, count 0 2006.224.08:22:01.17#ibcon#end of sib2, iclass 3, count 0 2006.224.08:22:01.17#ibcon#*mode == 0, iclass 3, count 0 2006.224.08:22:01.17#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.224.08:22:01.17#ibcon#[28=FRQ=03,656.99\r\n] 2006.224.08:22:01.17#ibcon#*before write, iclass 3, count 0 2006.224.08:22:01.17#ibcon#enter sib2, iclass 3, count 0 2006.224.08:22:01.17#ibcon#flushed, iclass 3, count 0 2006.224.08:22:01.17#ibcon#about to write, iclass 3, count 0 2006.224.08:22:01.17#ibcon#wrote, iclass 3, count 0 2006.224.08:22:01.17#ibcon#about to read 3, iclass 3, count 0 2006.224.08:22:01.21#ibcon#read 3, iclass 3, count 0 2006.224.08:22:01.21#ibcon#about to read 4, iclass 3, count 0 2006.224.08:22:01.21#ibcon#read 4, iclass 3, count 0 2006.224.08:22:01.21#ibcon#about to read 5, iclass 3, count 0 2006.224.08:22:01.21#ibcon#read 5, iclass 3, count 0 2006.224.08:22:01.21#ibcon#about to read 6, iclass 3, count 0 2006.224.08:22:01.21#ibcon#read 6, iclass 3, count 0 2006.224.08:22:01.21#ibcon#end of sib2, iclass 3, count 0 2006.224.08:22:01.21#ibcon#*after write, iclass 3, count 0 2006.224.08:22:01.21#ibcon#*before return 0, iclass 3, count 0 2006.224.08:22:01.21#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.224.08:22:01.21#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.224.08:22:01.21#ibcon#about to clear, iclass 3 cls_cnt 0 2006.224.08:22:01.21#ibcon#cleared, iclass 3 cls_cnt 0 2006.224.08:22:01.21$vc4f8/vb=3,4 2006.224.08:22:01.21#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.224.08:22:01.21#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.224.08:22:01.21#ibcon#ireg 11 cls_cnt 2 2006.224.08:22:01.21#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.224.08:22:01.27#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.224.08:22:01.27#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.224.08:22:01.27#ibcon#enter wrdev, iclass 5, count 2 2006.224.08:22:01.27#ibcon#first serial, iclass 5, count 2 2006.224.08:22:01.27#ibcon#enter sib2, iclass 5, count 2 2006.224.08:22:01.27#ibcon#flushed, iclass 5, count 2 2006.224.08:22:01.27#ibcon#about to write, iclass 5, count 2 2006.224.08:22:01.27#ibcon#wrote, iclass 5, count 2 2006.224.08:22:01.27#ibcon#about to read 3, iclass 5, count 2 2006.224.08:22:01.29#ibcon#read 3, iclass 5, count 2 2006.224.08:22:01.29#ibcon#about to read 4, iclass 5, count 2 2006.224.08:22:01.29#ibcon#read 4, iclass 5, count 2 2006.224.08:22:01.29#ibcon#about to read 5, iclass 5, count 2 2006.224.08:22:01.29#ibcon#read 5, iclass 5, count 2 2006.224.08:22:01.29#ibcon#about to read 6, iclass 5, count 2 2006.224.08:22:01.29#ibcon#read 6, iclass 5, count 2 2006.224.08:22:01.29#ibcon#end of sib2, iclass 5, count 2 2006.224.08:22:01.29#ibcon#*mode == 0, iclass 5, count 2 2006.224.08:22:01.29#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.224.08:22:01.29#ibcon#[27=AT03-04\r\n] 2006.224.08:22:01.29#ibcon#*before write, iclass 5, count 2 2006.224.08:22:01.29#ibcon#enter sib2, iclass 5, count 2 2006.224.08:22:01.29#ibcon#flushed, iclass 5, count 2 2006.224.08:22:01.29#ibcon#about to write, iclass 5, count 2 2006.224.08:22:01.29#ibcon#wrote, iclass 5, count 2 2006.224.08:22:01.29#ibcon#about to read 3, iclass 5, count 2 2006.224.08:22:01.32#ibcon#read 3, iclass 5, count 2 2006.224.08:22:01.32#ibcon#about to read 4, iclass 5, count 2 2006.224.08:22:01.32#ibcon#read 4, iclass 5, count 2 2006.224.08:22:01.32#ibcon#about to read 5, iclass 5, count 2 2006.224.08:22:01.32#ibcon#read 5, iclass 5, count 2 2006.224.08:22:01.32#ibcon#about to read 6, iclass 5, count 2 2006.224.08:22:01.32#ibcon#read 6, iclass 5, count 2 2006.224.08:22:01.32#ibcon#end of sib2, iclass 5, count 2 2006.224.08:22:01.32#ibcon#*after write, iclass 5, count 2 2006.224.08:22:01.32#ibcon#*before return 0, iclass 5, count 2 2006.224.08:22:01.32#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.224.08:22:01.32#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.224.08:22:01.32#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.224.08:22:01.32#ibcon#ireg 7 cls_cnt 0 2006.224.08:22:01.32#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.224.08:22:01.44#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.224.08:22:01.44#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.224.08:22:01.44#ibcon#enter wrdev, iclass 5, count 0 2006.224.08:22:01.44#ibcon#first serial, iclass 5, count 0 2006.224.08:22:01.44#ibcon#enter sib2, iclass 5, count 0 2006.224.08:22:01.44#ibcon#flushed, iclass 5, count 0 2006.224.08:22:01.44#ibcon#about to write, iclass 5, count 0 2006.224.08:22:01.44#ibcon#wrote, iclass 5, count 0 2006.224.08:22:01.44#ibcon#about to read 3, iclass 5, count 0 2006.224.08:22:01.46#ibcon#read 3, iclass 5, count 0 2006.224.08:22:01.46#ibcon#about to read 4, iclass 5, count 0 2006.224.08:22:01.46#ibcon#read 4, iclass 5, count 0 2006.224.08:22:01.46#ibcon#about to read 5, iclass 5, count 0 2006.224.08:22:01.46#ibcon#read 5, iclass 5, count 0 2006.224.08:22:01.46#ibcon#about to read 6, iclass 5, count 0 2006.224.08:22:01.46#ibcon#read 6, iclass 5, count 0 2006.224.08:22:01.46#ibcon#end of sib2, iclass 5, count 0 2006.224.08:22:01.46#ibcon#*mode == 0, iclass 5, count 0 2006.224.08:22:01.46#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.224.08:22:01.46#ibcon#[27=USB\r\n] 2006.224.08:22:01.46#ibcon#*before write, iclass 5, count 0 2006.224.08:22:01.46#ibcon#enter sib2, iclass 5, count 0 2006.224.08:22:01.46#ibcon#flushed, iclass 5, count 0 2006.224.08:22:01.46#ibcon#about to write, iclass 5, count 0 2006.224.08:22:01.46#ibcon#wrote, iclass 5, count 0 2006.224.08:22:01.46#ibcon#about to read 3, iclass 5, count 0 2006.224.08:22:01.49#ibcon#read 3, iclass 5, count 0 2006.224.08:22:01.49#ibcon#about to read 4, iclass 5, count 0 2006.224.08:22:01.49#ibcon#read 4, iclass 5, count 0 2006.224.08:22:01.49#ibcon#about to read 5, iclass 5, count 0 2006.224.08:22:01.49#ibcon#read 5, iclass 5, count 0 2006.224.08:22:01.49#ibcon#about to read 6, iclass 5, count 0 2006.224.08:22:01.49#ibcon#read 6, iclass 5, count 0 2006.224.08:22:01.49#ibcon#end of sib2, iclass 5, count 0 2006.224.08:22:01.49#ibcon#*after write, iclass 5, count 0 2006.224.08:22:01.49#ibcon#*before return 0, iclass 5, count 0 2006.224.08:22:01.49#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.224.08:22:01.49#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.224.08:22:01.49#ibcon#about to clear, iclass 5 cls_cnt 0 2006.224.08:22:01.49#ibcon#cleared, iclass 5 cls_cnt 0 2006.224.08:22:01.49$vc4f8/vblo=4,712.99 2006.224.08:22:01.49#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.224.08:22:01.49#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.224.08:22:01.49#ibcon#ireg 17 cls_cnt 0 2006.224.08:22:01.49#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.224.08:22:01.49#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.224.08:22:01.49#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.224.08:22:01.49#ibcon#enter wrdev, iclass 7, count 0 2006.224.08:22:01.49#ibcon#first serial, iclass 7, count 0 2006.224.08:22:01.49#ibcon#enter sib2, iclass 7, count 0 2006.224.08:22:01.49#ibcon#flushed, iclass 7, count 0 2006.224.08:22:01.49#ibcon#about to write, iclass 7, count 0 2006.224.08:22:01.49#ibcon#wrote, iclass 7, count 0 2006.224.08:22:01.49#ibcon#about to read 3, iclass 7, count 0 2006.224.08:22:01.51#ibcon#read 3, iclass 7, count 0 2006.224.08:22:01.51#ibcon#about to read 4, iclass 7, count 0 2006.224.08:22:01.51#ibcon#read 4, iclass 7, count 0 2006.224.08:22:01.51#ibcon#about to read 5, iclass 7, count 0 2006.224.08:22:01.51#ibcon#read 5, iclass 7, count 0 2006.224.08:22:01.51#ibcon#about to read 6, iclass 7, count 0 2006.224.08:22:01.51#ibcon#read 6, iclass 7, count 0 2006.224.08:22:01.51#ibcon#end of sib2, iclass 7, count 0 2006.224.08:22:01.51#ibcon#*mode == 0, iclass 7, count 0 2006.224.08:22:01.51#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.224.08:22:01.51#ibcon#[28=FRQ=04,712.99\r\n] 2006.224.08:22:01.51#ibcon#*before write, iclass 7, count 0 2006.224.08:22:01.51#ibcon#enter sib2, iclass 7, count 0 2006.224.08:22:01.51#ibcon#flushed, iclass 7, count 0 2006.224.08:22:01.51#ibcon#about to write, iclass 7, count 0 2006.224.08:22:01.51#ibcon#wrote, iclass 7, count 0 2006.224.08:22:01.51#ibcon#about to read 3, iclass 7, count 0 2006.224.08:22:01.55#ibcon#read 3, iclass 7, count 0 2006.224.08:22:01.55#ibcon#about to read 4, iclass 7, count 0 2006.224.08:22:01.55#ibcon#read 4, iclass 7, count 0 2006.224.08:22:01.55#ibcon#about to read 5, iclass 7, count 0 2006.224.08:22:01.55#ibcon#read 5, iclass 7, count 0 2006.224.08:22:01.55#ibcon#about to read 6, iclass 7, count 0 2006.224.08:22:01.55#ibcon#read 6, iclass 7, count 0 2006.224.08:22:01.55#ibcon#end of sib2, iclass 7, count 0 2006.224.08:22:01.55#ibcon#*after write, iclass 7, count 0 2006.224.08:22:01.55#ibcon#*before return 0, iclass 7, count 0 2006.224.08:22:01.55#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.224.08:22:01.55#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.224.08:22:01.55#ibcon#about to clear, iclass 7 cls_cnt 0 2006.224.08:22:01.55#ibcon#cleared, iclass 7 cls_cnt 0 2006.224.08:22:01.55$vc4f8/vb=4,4 2006.224.08:22:01.55#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.224.08:22:01.55#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.224.08:22:01.55#ibcon#ireg 11 cls_cnt 2 2006.224.08:22:01.55#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.224.08:22:01.62#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.224.08:22:01.62#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.224.08:22:01.62#ibcon#enter wrdev, iclass 11, count 2 2006.224.08:22:01.62#ibcon#first serial, iclass 11, count 2 2006.224.08:22:01.62#ibcon#enter sib2, iclass 11, count 2 2006.224.08:22:01.62#ibcon#flushed, iclass 11, count 2 2006.224.08:22:01.62#ibcon#about to write, iclass 11, count 2 2006.224.08:22:01.62#ibcon#wrote, iclass 11, count 2 2006.224.08:22:01.62#ibcon#about to read 3, iclass 11, count 2 2006.224.08:22:01.63#ibcon#read 3, iclass 11, count 2 2006.224.08:22:01.63#ibcon#about to read 4, iclass 11, count 2 2006.224.08:22:01.63#ibcon#read 4, iclass 11, count 2 2006.224.08:22:01.63#ibcon#about to read 5, iclass 11, count 2 2006.224.08:22:01.63#ibcon#read 5, iclass 11, count 2 2006.224.08:22:01.63#ibcon#about to read 6, iclass 11, count 2 2006.224.08:22:01.63#ibcon#read 6, iclass 11, count 2 2006.224.08:22:01.63#ibcon#end of sib2, iclass 11, count 2 2006.224.08:22:01.63#ibcon#*mode == 0, iclass 11, count 2 2006.224.08:22:01.63#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.224.08:22:01.63#ibcon#[27=AT04-04\r\n] 2006.224.08:22:01.63#ibcon#*before write, iclass 11, count 2 2006.224.08:22:01.63#ibcon#enter sib2, iclass 11, count 2 2006.224.08:22:01.63#ibcon#flushed, iclass 11, count 2 2006.224.08:22:01.63#ibcon#about to write, iclass 11, count 2 2006.224.08:22:01.63#ibcon#wrote, iclass 11, count 2 2006.224.08:22:01.63#ibcon#about to read 3, iclass 11, count 2 2006.224.08:22:01.66#ibcon#read 3, iclass 11, count 2 2006.224.08:22:01.66#ibcon#about to read 4, iclass 11, count 2 2006.224.08:22:01.66#ibcon#read 4, iclass 11, count 2 2006.224.08:22:01.66#ibcon#about to read 5, iclass 11, count 2 2006.224.08:22:01.66#ibcon#read 5, iclass 11, count 2 2006.224.08:22:01.66#ibcon#about to read 6, iclass 11, count 2 2006.224.08:22:01.66#ibcon#read 6, iclass 11, count 2 2006.224.08:22:01.66#ibcon#end of sib2, iclass 11, count 2 2006.224.08:22:01.66#ibcon#*after write, iclass 11, count 2 2006.224.08:22:01.66#ibcon#*before return 0, iclass 11, count 2 2006.224.08:22:01.66#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.224.08:22:01.66#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.224.08:22:01.66#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.224.08:22:01.66#ibcon#ireg 7 cls_cnt 0 2006.224.08:22:01.66#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.224.08:22:01.78#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.224.08:22:01.78#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.224.08:22:01.78#ibcon#enter wrdev, iclass 11, count 0 2006.224.08:22:01.78#ibcon#first serial, iclass 11, count 0 2006.224.08:22:01.78#ibcon#enter sib2, iclass 11, count 0 2006.224.08:22:01.78#ibcon#flushed, iclass 11, count 0 2006.224.08:22:01.78#ibcon#about to write, iclass 11, count 0 2006.224.08:22:01.78#ibcon#wrote, iclass 11, count 0 2006.224.08:22:01.78#ibcon#about to read 3, iclass 11, count 0 2006.224.08:22:01.80#ibcon#read 3, iclass 11, count 0 2006.224.08:22:01.80#ibcon#about to read 4, iclass 11, count 0 2006.224.08:22:01.80#ibcon#read 4, iclass 11, count 0 2006.224.08:22:01.80#ibcon#about to read 5, iclass 11, count 0 2006.224.08:22:01.80#ibcon#read 5, iclass 11, count 0 2006.224.08:22:01.80#ibcon#about to read 6, iclass 11, count 0 2006.224.08:22:01.80#ibcon#read 6, iclass 11, count 0 2006.224.08:22:01.80#ibcon#end of sib2, iclass 11, count 0 2006.224.08:22:01.80#ibcon#*mode == 0, iclass 11, count 0 2006.224.08:22:01.80#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.224.08:22:01.80#ibcon#[27=USB\r\n] 2006.224.08:22:01.80#ibcon#*before write, iclass 11, count 0 2006.224.08:22:01.80#ibcon#enter sib2, iclass 11, count 0 2006.224.08:22:01.80#ibcon#flushed, iclass 11, count 0 2006.224.08:22:01.80#ibcon#about to write, iclass 11, count 0 2006.224.08:22:01.80#ibcon#wrote, iclass 11, count 0 2006.224.08:22:01.80#ibcon#about to read 3, iclass 11, count 0 2006.224.08:22:01.83#ibcon#read 3, iclass 11, count 0 2006.224.08:22:01.83#ibcon#about to read 4, iclass 11, count 0 2006.224.08:22:01.83#ibcon#read 4, iclass 11, count 0 2006.224.08:22:01.83#ibcon#about to read 5, iclass 11, count 0 2006.224.08:22:01.83#ibcon#read 5, iclass 11, count 0 2006.224.08:22:01.83#ibcon#about to read 6, iclass 11, count 0 2006.224.08:22:01.83#ibcon#read 6, iclass 11, count 0 2006.224.08:22:01.83#ibcon#end of sib2, iclass 11, count 0 2006.224.08:22:01.83#ibcon#*after write, iclass 11, count 0 2006.224.08:22:01.83#ibcon#*before return 0, iclass 11, count 0 2006.224.08:22:01.83#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.224.08:22:01.83#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.224.08:22:01.83#ibcon#about to clear, iclass 11 cls_cnt 0 2006.224.08:22:01.83#ibcon#cleared, iclass 11 cls_cnt 0 2006.224.08:22:01.83$vc4f8/vblo=5,744.99 2006.224.08:22:01.83#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.224.08:22:01.83#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.224.08:22:01.83#ibcon#ireg 17 cls_cnt 0 2006.224.08:22:01.83#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.224.08:22:01.83#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.224.08:22:01.83#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.224.08:22:01.83#ibcon#enter wrdev, iclass 13, count 0 2006.224.08:22:01.83#ibcon#first serial, iclass 13, count 0 2006.224.08:22:01.83#ibcon#enter sib2, iclass 13, count 0 2006.224.08:22:01.83#ibcon#flushed, iclass 13, count 0 2006.224.08:22:01.83#ibcon#about to write, iclass 13, count 0 2006.224.08:22:01.83#ibcon#wrote, iclass 13, count 0 2006.224.08:22:01.83#ibcon#about to read 3, iclass 13, count 0 2006.224.08:22:01.85#ibcon#read 3, iclass 13, count 0 2006.224.08:22:01.85#ibcon#about to read 4, iclass 13, count 0 2006.224.08:22:01.85#ibcon#read 4, iclass 13, count 0 2006.224.08:22:01.85#ibcon#about to read 5, iclass 13, count 0 2006.224.08:22:01.85#ibcon#read 5, iclass 13, count 0 2006.224.08:22:01.85#ibcon#about to read 6, iclass 13, count 0 2006.224.08:22:01.85#ibcon#read 6, iclass 13, count 0 2006.224.08:22:01.85#ibcon#end of sib2, iclass 13, count 0 2006.224.08:22:01.85#ibcon#*mode == 0, iclass 13, count 0 2006.224.08:22:01.85#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.224.08:22:01.85#ibcon#[28=FRQ=05,744.99\r\n] 2006.224.08:22:01.85#ibcon#*before write, iclass 13, count 0 2006.224.08:22:01.85#ibcon#enter sib2, iclass 13, count 0 2006.224.08:22:01.85#ibcon#flushed, iclass 13, count 0 2006.224.08:22:01.85#ibcon#about to write, iclass 13, count 0 2006.224.08:22:01.85#ibcon#wrote, iclass 13, count 0 2006.224.08:22:01.85#ibcon#about to read 3, iclass 13, count 0 2006.224.08:22:01.89#ibcon#read 3, iclass 13, count 0 2006.224.08:22:01.89#ibcon#about to read 4, iclass 13, count 0 2006.224.08:22:01.89#ibcon#read 4, iclass 13, count 0 2006.224.08:22:01.89#ibcon#about to read 5, iclass 13, count 0 2006.224.08:22:01.89#ibcon#read 5, iclass 13, count 0 2006.224.08:22:01.89#ibcon#about to read 6, iclass 13, count 0 2006.224.08:22:01.89#ibcon#read 6, iclass 13, count 0 2006.224.08:22:01.89#ibcon#end of sib2, iclass 13, count 0 2006.224.08:22:01.89#ibcon#*after write, iclass 13, count 0 2006.224.08:22:01.89#ibcon#*before return 0, iclass 13, count 0 2006.224.08:22:01.89#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.224.08:22:01.89#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.224.08:22:01.89#ibcon#about to clear, iclass 13 cls_cnt 0 2006.224.08:22:01.89#ibcon#cleared, iclass 13 cls_cnt 0 2006.224.08:22:01.89$vc4f8/vb=5,4 2006.224.08:22:01.89#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.224.08:22:01.89#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.224.08:22:01.89#ibcon#ireg 11 cls_cnt 2 2006.224.08:22:01.89#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.224.08:22:01.95#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.224.08:22:01.95#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.224.08:22:01.95#ibcon#enter wrdev, iclass 15, count 2 2006.224.08:22:01.95#ibcon#first serial, iclass 15, count 2 2006.224.08:22:01.95#ibcon#enter sib2, iclass 15, count 2 2006.224.08:22:01.95#ibcon#flushed, iclass 15, count 2 2006.224.08:22:01.95#ibcon#about to write, iclass 15, count 2 2006.224.08:22:01.95#ibcon#wrote, iclass 15, count 2 2006.224.08:22:01.95#ibcon#about to read 3, iclass 15, count 2 2006.224.08:22:01.97#ibcon#read 3, iclass 15, count 2 2006.224.08:22:01.97#ibcon#about to read 4, iclass 15, count 2 2006.224.08:22:01.97#ibcon#read 4, iclass 15, count 2 2006.224.08:22:01.97#ibcon#about to read 5, iclass 15, count 2 2006.224.08:22:01.97#ibcon#read 5, iclass 15, count 2 2006.224.08:22:01.97#ibcon#about to read 6, iclass 15, count 2 2006.224.08:22:01.97#ibcon#read 6, iclass 15, count 2 2006.224.08:22:01.97#ibcon#end of sib2, iclass 15, count 2 2006.224.08:22:01.97#ibcon#*mode == 0, iclass 15, count 2 2006.224.08:22:01.97#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.224.08:22:01.97#ibcon#[27=AT05-04\r\n] 2006.224.08:22:01.97#ibcon#*before write, iclass 15, count 2 2006.224.08:22:01.97#ibcon#enter sib2, iclass 15, count 2 2006.224.08:22:01.97#ibcon#flushed, iclass 15, count 2 2006.224.08:22:01.97#ibcon#about to write, iclass 15, count 2 2006.224.08:22:01.97#ibcon#wrote, iclass 15, count 2 2006.224.08:22:01.97#ibcon#about to read 3, iclass 15, count 2 2006.224.08:22:02.00#ibcon#read 3, iclass 15, count 2 2006.224.08:22:02.00#ibcon#about to read 4, iclass 15, count 2 2006.224.08:22:02.00#ibcon#read 4, iclass 15, count 2 2006.224.08:22:02.00#ibcon#about to read 5, iclass 15, count 2 2006.224.08:22:02.00#ibcon#read 5, iclass 15, count 2 2006.224.08:22:02.00#ibcon#about to read 6, iclass 15, count 2 2006.224.08:22:02.00#ibcon#read 6, iclass 15, count 2 2006.224.08:22:02.00#ibcon#end of sib2, iclass 15, count 2 2006.224.08:22:02.00#ibcon#*after write, iclass 15, count 2 2006.224.08:22:02.00#ibcon#*before return 0, iclass 15, count 2 2006.224.08:22:02.00#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.224.08:22:02.00#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.224.08:22:02.00#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.224.08:22:02.00#ibcon#ireg 7 cls_cnt 0 2006.224.08:22:02.00#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.224.08:22:02.12#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.224.08:22:02.12#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.224.08:22:02.12#ibcon#enter wrdev, iclass 15, count 0 2006.224.08:22:02.12#ibcon#first serial, iclass 15, count 0 2006.224.08:22:02.12#ibcon#enter sib2, iclass 15, count 0 2006.224.08:22:02.12#ibcon#flushed, iclass 15, count 0 2006.224.08:22:02.12#ibcon#about to write, iclass 15, count 0 2006.224.08:22:02.12#ibcon#wrote, iclass 15, count 0 2006.224.08:22:02.12#ibcon#about to read 3, iclass 15, count 0 2006.224.08:22:02.14#ibcon#read 3, iclass 15, count 0 2006.224.08:22:02.14#ibcon#about to read 4, iclass 15, count 0 2006.224.08:22:02.14#ibcon#read 4, iclass 15, count 0 2006.224.08:22:02.14#ibcon#about to read 5, iclass 15, count 0 2006.224.08:22:02.14#ibcon#read 5, iclass 15, count 0 2006.224.08:22:02.14#ibcon#about to read 6, iclass 15, count 0 2006.224.08:22:02.14#ibcon#read 6, iclass 15, count 0 2006.224.08:22:02.14#ibcon#end of sib2, iclass 15, count 0 2006.224.08:22:02.14#ibcon#*mode == 0, iclass 15, count 0 2006.224.08:22:02.14#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.224.08:22:02.14#ibcon#[27=USB\r\n] 2006.224.08:22:02.14#ibcon#*before write, iclass 15, count 0 2006.224.08:22:02.14#ibcon#enter sib2, iclass 15, count 0 2006.224.08:22:02.14#ibcon#flushed, iclass 15, count 0 2006.224.08:22:02.14#ibcon#about to write, iclass 15, count 0 2006.224.08:22:02.14#ibcon#wrote, iclass 15, count 0 2006.224.08:22:02.14#ibcon#about to read 3, iclass 15, count 0 2006.224.08:22:02.17#ibcon#read 3, iclass 15, count 0 2006.224.08:22:02.17#ibcon#about to read 4, iclass 15, count 0 2006.224.08:22:02.17#ibcon#read 4, iclass 15, count 0 2006.224.08:22:02.17#ibcon#about to read 5, iclass 15, count 0 2006.224.08:22:02.17#ibcon#read 5, iclass 15, count 0 2006.224.08:22:02.17#ibcon#about to read 6, iclass 15, count 0 2006.224.08:22:02.17#ibcon#read 6, iclass 15, count 0 2006.224.08:22:02.17#ibcon#end of sib2, iclass 15, count 0 2006.224.08:22:02.17#ibcon#*after write, iclass 15, count 0 2006.224.08:22:02.17#ibcon#*before return 0, iclass 15, count 0 2006.224.08:22:02.17#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.224.08:22:02.17#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.224.08:22:02.17#ibcon#about to clear, iclass 15 cls_cnt 0 2006.224.08:22:02.17#ibcon#cleared, iclass 15 cls_cnt 0 2006.224.08:22:02.17$vc4f8/vblo=6,752.99 2006.224.08:22:02.17#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.224.08:22:02.17#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.224.08:22:02.17#ibcon#ireg 17 cls_cnt 0 2006.224.08:22:02.17#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.224.08:22:02.17#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.224.08:22:02.17#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.224.08:22:02.17#ibcon#enter wrdev, iclass 17, count 0 2006.224.08:22:02.17#ibcon#first serial, iclass 17, count 0 2006.224.08:22:02.17#ibcon#enter sib2, iclass 17, count 0 2006.224.08:22:02.17#ibcon#flushed, iclass 17, count 0 2006.224.08:22:02.17#ibcon#about to write, iclass 17, count 0 2006.224.08:22:02.17#ibcon#wrote, iclass 17, count 0 2006.224.08:22:02.17#ibcon#about to read 3, iclass 17, count 0 2006.224.08:22:02.19#ibcon#read 3, iclass 17, count 0 2006.224.08:22:02.19#ibcon#about to read 4, iclass 17, count 0 2006.224.08:22:02.19#ibcon#read 4, iclass 17, count 0 2006.224.08:22:02.19#ibcon#about to read 5, iclass 17, count 0 2006.224.08:22:02.19#ibcon#read 5, iclass 17, count 0 2006.224.08:22:02.19#ibcon#about to read 6, iclass 17, count 0 2006.224.08:22:02.19#ibcon#read 6, iclass 17, count 0 2006.224.08:22:02.19#ibcon#end of sib2, iclass 17, count 0 2006.224.08:22:02.19#ibcon#*mode == 0, iclass 17, count 0 2006.224.08:22:02.19#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.224.08:22:02.19#ibcon#[28=FRQ=06,752.99\r\n] 2006.224.08:22:02.19#ibcon#*before write, iclass 17, count 0 2006.224.08:22:02.19#ibcon#enter sib2, iclass 17, count 0 2006.224.08:22:02.19#ibcon#flushed, iclass 17, count 0 2006.224.08:22:02.19#ibcon#about to write, iclass 17, count 0 2006.224.08:22:02.19#ibcon#wrote, iclass 17, count 0 2006.224.08:22:02.19#ibcon#about to read 3, iclass 17, count 0 2006.224.08:22:02.23#ibcon#read 3, iclass 17, count 0 2006.224.08:22:02.23#ibcon#about to read 4, iclass 17, count 0 2006.224.08:22:02.23#ibcon#read 4, iclass 17, count 0 2006.224.08:22:02.23#ibcon#about to read 5, iclass 17, count 0 2006.224.08:22:02.23#ibcon#read 5, iclass 17, count 0 2006.224.08:22:02.23#ibcon#about to read 6, iclass 17, count 0 2006.224.08:22:02.23#ibcon#read 6, iclass 17, count 0 2006.224.08:22:02.23#ibcon#end of sib2, iclass 17, count 0 2006.224.08:22:02.23#ibcon#*after write, iclass 17, count 0 2006.224.08:22:02.23#ibcon#*before return 0, iclass 17, count 0 2006.224.08:22:02.23#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.224.08:22:02.23#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.224.08:22:02.23#ibcon#about to clear, iclass 17 cls_cnt 0 2006.224.08:22:02.23#ibcon#cleared, iclass 17 cls_cnt 0 2006.224.08:22:02.23$vc4f8/vb=6,4 2006.224.08:22:02.23#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.224.08:22:02.23#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.224.08:22:02.23#ibcon#ireg 11 cls_cnt 2 2006.224.08:22:02.23#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.224.08:22:02.29#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.224.08:22:02.29#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.224.08:22:02.29#ibcon#enter wrdev, iclass 19, count 2 2006.224.08:22:02.29#ibcon#first serial, iclass 19, count 2 2006.224.08:22:02.29#ibcon#enter sib2, iclass 19, count 2 2006.224.08:22:02.29#ibcon#flushed, iclass 19, count 2 2006.224.08:22:02.29#ibcon#about to write, iclass 19, count 2 2006.224.08:22:02.29#ibcon#wrote, iclass 19, count 2 2006.224.08:22:02.29#ibcon#about to read 3, iclass 19, count 2 2006.224.08:22:02.31#ibcon#read 3, iclass 19, count 2 2006.224.08:22:02.31#ibcon#about to read 4, iclass 19, count 2 2006.224.08:22:02.31#ibcon#read 4, iclass 19, count 2 2006.224.08:22:02.31#ibcon#about to read 5, iclass 19, count 2 2006.224.08:22:02.31#ibcon#read 5, iclass 19, count 2 2006.224.08:22:02.31#ibcon#about to read 6, iclass 19, count 2 2006.224.08:22:02.31#ibcon#read 6, iclass 19, count 2 2006.224.08:22:02.31#ibcon#end of sib2, iclass 19, count 2 2006.224.08:22:02.31#ibcon#*mode == 0, iclass 19, count 2 2006.224.08:22:02.31#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.224.08:22:02.31#ibcon#[27=AT06-04\r\n] 2006.224.08:22:02.31#ibcon#*before write, iclass 19, count 2 2006.224.08:22:02.31#ibcon#enter sib2, iclass 19, count 2 2006.224.08:22:02.31#ibcon#flushed, iclass 19, count 2 2006.224.08:22:02.31#ibcon#about to write, iclass 19, count 2 2006.224.08:22:02.31#ibcon#wrote, iclass 19, count 2 2006.224.08:22:02.31#ibcon#about to read 3, iclass 19, count 2 2006.224.08:22:02.34#ibcon#read 3, iclass 19, count 2 2006.224.08:22:02.34#ibcon#about to read 4, iclass 19, count 2 2006.224.08:22:02.34#ibcon#read 4, iclass 19, count 2 2006.224.08:22:02.34#ibcon#about to read 5, iclass 19, count 2 2006.224.08:22:02.34#ibcon#read 5, iclass 19, count 2 2006.224.08:22:02.34#ibcon#about to read 6, iclass 19, count 2 2006.224.08:22:02.34#ibcon#read 6, iclass 19, count 2 2006.224.08:22:02.34#ibcon#end of sib2, iclass 19, count 2 2006.224.08:22:02.34#ibcon#*after write, iclass 19, count 2 2006.224.08:22:02.34#ibcon#*before return 0, iclass 19, count 2 2006.224.08:22:02.34#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.224.08:22:02.34#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.224.08:22:02.34#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.224.08:22:02.34#ibcon#ireg 7 cls_cnt 0 2006.224.08:22:02.34#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.224.08:22:02.46#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.224.08:22:02.46#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.224.08:22:02.46#ibcon#enter wrdev, iclass 19, count 0 2006.224.08:22:02.46#ibcon#first serial, iclass 19, count 0 2006.224.08:22:02.46#ibcon#enter sib2, iclass 19, count 0 2006.224.08:22:02.46#ibcon#flushed, iclass 19, count 0 2006.224.08:22:02.46#ibcon#about to write, iclass 19, count 0 2006.224.08:22:02.46#ibcon#wrote, iclass 19, count 0 2006.224.08:22:02.46#ibcon#about to read 3, iclass 19, count 0 2006.224.08:22:02.48#ibcon#read 3, iclass 19, count 0 2006.224.08:22:02.48#ibcon#about to read 4, iclass 19, count 0 2006.224.08:22:02.48#ibcon#read 4, iclass 19, count 0 2006.224.08:22:02.48#ibcon#about to read 5, iclass 19, count 0 2006.224.08:22:02.48#ibcon#read 5, iclass 19, count 0 2006.224.08:22:02.48#ibcon#about to read 6, iclass 19, count 0 2006.224.08:22:02.48#ibcon#read 6, iclass 19, count 0 2006.224.08:22:02.48#ibcon#end of sib2, iclass 19, count 0 2006.224.08:22:02.48#ibcon#*mode == 0, iclass 19, count 0 2006.224.08:22:02.48#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.224.08:22:02.48#ibcon#[27=USB\r\n] 2006.224.08:22:02.48#ibcon#*before write, iclass 19, count 0 2006.224.08:22:02.48#ibcon#enter sib2, iclass 19, count 0 2006.224.08:22:02.48#ibcon#flushed, iclass 19, count 0 2006.224.08:22:02.48#ibcon#about to write, iclass 19, count 0 2006.224.08:22:02.48#ibcon#wrote, iclass 19, count 0 2006.224.08:22:02.48#ibcon#about to read 3, iclass 19, count 0 2006.224.08:22:02.51#ibcon#read 3, iclass 19, count 0 2006.224.08:22:02.51#ibcon#about to read 4, iclass 19, count 0 2006.224.08:22:02.51#ibcon#read 4, iclass 19, count 0 2006.224.08:22:02.51#ibcon#about to read 5, iclass 19, count 0 2006.224.08:22:02.51#ibcon#read 5, iclass 19, count 0 2006.224.08:22:02.51#ibcon#about to read 6, iclass 19, count 0 2006.224.08:22:02.51#ibcon#read 6, iclass 19, count 0 2006.224.08:22:02.51#ibcon#end of sib2, iclass 19, count 0 2006.224.08:22:02.51#ibcon#*after write, iclass 19, count 0 2006.224.08:22:02.51#ibcon#*before return 0, iclass 19, count 0 2006.224.08:22:02.51#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.224.08:22:02.51#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.224.08:22:02.51#ibcon#about to clear, iclass 19 cls_cnt 0 2006.224.08:22:02.51#ibcon#cleared, iclass 19 cls_cnt 0 2006.224.08:22:02.51$vc4f8/vabw=wide 2006.224.08:22:02.51#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.224.08:22:02.51#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.224.08:22:02.51#ibcon#ireg 8 cls_cnt 0 2006.224.08:22:02.51#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.224.08:22:02.51#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.224.08:22:02.51#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.224.08:22:02.51#ibcon#enter wrdev, iclass 21, count 0 2006.224.08:22:02.51#ibcon#first serial, iclass 21, count 0 2006.224.08:22:02.51#ibcon#enter sib2, iclass 21, count 0 2006.224.08:22:02.51#ibcon#flushed, iclass 21, count 0 2006.224.08:22:02.51#ibcon#about to write, iclass 21, count 0 2006.224.08:22:02.51#ibcon#wrote, iclass 21, count 0 2006.224.08:22:02.51#ibcon#about to read 3, iclass 21, count 0 2006.224.08:22:02.54#ibcon#read 3, iclass 21, count 0 2006.224.08:22:02.54#ibcon#about to read 4, iclass 21, count 0 2006.224.08:22:02.54#ibcon#read 4, iclass 21, count 0 2006.224.08:22:02.54#ibcon#about to read 5, iclass 21, count 0 2006.224.08:22:02.54#ibcon#read 5, iclass 21, count 0 2006.224.08:22:02.54#ibcon#about to read 6, iclass 21, count 0 2006.224.08:22:02.54#ibcon#read 6, iclass 21, count 0 2006.224.08:22:02.54#ibcon#end of sib2, iclass 21, count 0 2006.224.08:22:02.54#ibcon#*mode == 0, iclass 21, count 0 2006.224.08:22:02.54#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.224.08:22:02.54#ibcon#[25=BW32\r\n] 2006.224.08:22:02.54#ibcon#*before write, iclass 21, count 0 2006.224.08:22:02.54#ibcon#enter sib2, iclass 21, count 0 2006.224.08:22:02.54#ibcon#flushed, iclass 21, count 0 2006.224.08:22:02.54#ibcon#about to write, iclass 21, count 0 2006.224.08:22:02.54#ibcon#wrote, iclass 21, count 0 2006.224.08:22:02.54#ibcon#about to read 3, iclass 21, count 0 2006.224.08:22:02.57#ibcon#read 3, iclass 21, count 0 2006.224.08:22:02.57#ibcon#about to read 4, iclass 21, count 0 2006.224.08:22:02.57#ibcon#read 4, iclass 21, count 0 2006.224.08:22:02.57#ibcon#about to read 5, iclass 21, count 0 2006.224.08:22:02.57#ibcon#read 5, iclass 21, count 0 2006.224.08:22:02.57#ibcon#about to read 6, iclass 21, count 0 2006.224.08:22:02.57#ibcon#read 6, iclass 21, count 0 2006.224.08:22:02.57#ibcon#end of sib2, iclass 21, count 0 2006.224.08:22:02.57#ibcon#*after write, iclass 21, count 0 2006.224.08:22:02.57#ibcon#*before return 0, iclass 21, count 0 2006.224.08:22:02.57#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.224.08:22:02.57#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.224.08:22:02.57#ibcon#about to clear, iclass 21 cls_cnt 0 2006.224.08:22:02.57#ibcon#cleared, iclass 21 cls_cnt 0 2006.224.08:22:02.57$vc4f8/vbbw=wide 2006.224.08:22:02.57#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.224.08:22:02.57#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.224.08:22:02.57#ibcon#ireg 8 cls_cnt 0 2006.224.08:22:02.57#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.224.08:22:02.64#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.224.08:22:02.64#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.224.08:22:02.64#ibcon#enter wrdev, iclass 23, count 0 2006.224.08:22:02.64#ibcon#first serial, iclass 23, count 0 2006.224.08:22:02.64#ibcon#enter sib2, iclass 23, count 0 2006.224.08:22:02.64#ibcon#flushed, iclass 23, count 0 2006.224.08:22:02.64#ibcon#about to write, iclass 23, count 0 2006.224.08:22:02.64#ibcon#wrote, iclass 23, count 0 2006.224.08:22:02.64#ibcon#about to read 3, iclass 23, count 0 2006.224.08:22:02.65#ibcon#read 3, iclass 23, count 0 2006.224.08:22:02.65#ibcon#about to read 4, iclass 23, count 0 2006.224.08:22:02.65#ibcon#read 4, iclass 23, count 0 2006.224.08:22:02.65#ibcon#about to read 5, iclass 23, count 0 2006.224.08:22:02.65#ibcon#read 5, iclass 23, count 0 2006.224.08:22:02.65#ibcon#about to read 6, iclass 23, count 0 2006.224.08:22:02.65#ibcon#read 6, iclass 23, count 0 2006.224.08:22:02.65#ibcon#end of sib2, iclass 23, count 0 2006.224.08:22:02.65#ibcon#*mode == 0, iclass 23, count 0 2006.224.08:22:02.65#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.224.08:22:02.65#ibcon#[27=BW32\r\n] 2006.224.08:22:02.65#ibcon#*before write, iclass 23, count 0 2006.224.08:22:02.65#ibcon#enter sib2, iclass 23, count 0 2006.224.08:22:02.65#ibcon#flushed, iclass 23, count 0 2006.224.08:22:02.65#ibcon#about to write, iclass 23, count 0 2006.224.08:22:02.65#ibcon#wrote, iclass 23, count 0 2006.224.08:22:02.65#ibcon#about to read 3, iclass 23, count 0 2006.224.08:22:02.68#ibcon#read 3, iclass 23, count 0 2006.224.08:22:02.68#ibcon#about to read 4, iclass 23, count 0 2006.224.08:22:02.68#ibcon#read 4, iclass 23, count 0 2006.224.08:22:02.68#ibcon#about to read 5, iclass 23, count 0 2006.224.08:22:02.68#ibcon#read 5, iclass 23, count 0 2006.224.08:22:02.68#ibcon#about to read 6, iclass 23, count 0 2006.224.08:22:02.68#ibcon#read 6, iclass 23, count 0 2006.224.08:22:02.68#ibcon#end of sib2, iclass 23, count 0 2006.224.08:22:02.68#ibcon#*after write, iclass 23, count 0 2006.224.08:22:02.68#ibcon#*before return 0, iclass 23, count 0 2006.224.08:22:02.68#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.224.08:22:02.68#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.224.08:22:02.68#ibcon#about to clear, iclass 23 cls_cnt 0 2006.224.08:22:02.68#ibcon#cleared, iclass 23 cls_cnt 0 2006.224.08:22:02.68$4f8m12a/ifd4f 2006.224.08:22:02.68$ifd4f/lo= 2006.224.08:22:02.68$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.224.08:22:02.68$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.224.08:22:02.68$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.224.08:22:02.68$ifd4f/patch= 2006.224.08:22:02.69$ifd4f/patch=lo1,a1,a2,a3,a4 2006.224.08:22:02.69$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.224.08:22:02.69$ifd4f/patch=lo3,a5,a6,a7,a8 2006.224.08:22:02.69$4f8m12a/"form=m,16.000,1:2 2006.224.08:22:02.69$4f8m12a/"tpicd 2006.224.08:22:02.69$4f8m12a/echo=off 2006.224.08:22:02.69$4f8m12a/xlog=off 2006.224.08:22:02.69:!2006.224.08:24:10 2006.224.08:22:34.14#trakl#Source acquired 2006.224.08:22:36.14#flagr#flagr/antenna,acquired 2006.224.08:24:10.01:preob 2006.224.08:24:11.14/onsource/TRACKING 2006.224.08:24:11.14:!2006.224.08:24:20 2006.224.08:24:20.00:data_valid=on 2006.224.08:24:20.00:midob 2006.224.08:24:20.14/onsource/TRACKING 2006.224.08:24:20.14/wx/23.75,1004.8,100 2006.224.08:24:20.26/cable/+6.4362E-03 2006.224.08:24:21.35/va/01,08,usb,yes,41,43 2006.224.08:24:21.35/va/02,07,usb,yes,41,43 2006.224.08:24:21.35/va/03,06,usb,yes,44,44 2006.224.08:24:21.35/va/04,07,usb,yes,43,46 2006.224.08:24:21.35/va/05,07,usb,yes,50,52 2006.224.08:24:21.35/va/06,06,usb,yes,49,49 2006.224.08:24:21.35/va/07,06,usb,yes,50,50 2006.224.08:24:21.35/va/08,07,usb,yes,47,47 2006.224.08:24:21.58/valo/01,532.99,yes,locked 2006.224.08:24:21.58/valo/02,572.99,yes,locked 2006.224.08:24:21.58/valo/03,672.99,yes,locked 2006.224.08:24:21.58/valo/04,832.99,yes,locked 2006.224.08:24:21.58/valo/05,652.99,yes,locked 2006.224.08:24:21.58/valo/06,772.99,yes,locked 2006.224.08:24:21.58/valo/07,832.99,yes,locked 2006.224.08:24:21.58/valo/08,852.99,yes,locked 2006.224.08:24:22.67/vb/01,04,usb,yes,32,31 2006.224.08:24:22.67/vb/02,04,usb,yes,34,36 2006.224.08:24:22.67/vb/03,04,usb,yes,30,34 2006.224.08:24:22.67/vb/04,04,usb,yes,31,32 2006.224.08:24:22.67/vb/05,04,usb,yes,30,34 2006.224.08:24:22.67/vb/06,04,usb,yes,31,34 2006.224.08:24:22.67/vb/07,04,usb,yes,33,33 2006.224.08:24:22.67/vb/08,04,usb,yes,30,34 2006.224.08:24:22.91/vblo/01,632.99,yes,locked 2006.224.08:24:22.91/vblo/02,640.99,yes,locked 2006.224.08:24:22.91/vblo/03,656.99,yes,locked 2006.224.08:24:22.91/vblo/04,712.99,yes,locked 2006.224.08:24:22.91/vblo/05,744.99,yes,locked 2006.224.08:24:22.91/vblo/06,752.99,yes,locked 2006.224.08:24:22.91/vblo/07,734.99,yes,locked 2006.224.08:24:22.91/vblo/08,744.99,yes,locked 2006.224.08:24:23.06/vabw/8 2006.224.08:24:23.21/vbbw/8 2006.224.08:24:23.30/xfe/off,on,16.0 2006.224.08:24:23.68/ifatt/23,28,28,28 2006.224.08:24:24.08/fmout-gps/S +4.49E-07 2006.224.08:24:24.12:!2006.224.08:25:20 2006.224.08:25:20.00:data_valid=off 2006.224.08:25:20.00:postob 2006.224.08:25:20.22/cable/+6.4335E-03 2006.224.08:25:20.22/wx/23.73,1004.7,100 2006.224.08:25:21.07/fmout-gps/S +4.49E-07 2006.224.08:25:21.08:scan_name=224-0826,k06224,60 2006.224.08:25:21.08:source=0955+476,095819.67,472507.8,2000.0,ccw 2006.224.08:25:22.13#flagr#flagr/antenna,new-source 2006.224.08:25:22.13:checkk5 2006.224.08:25:22.51/chk_autoobs//k5ts1/ autoobs is running! 2006.224.08:25:22.87/chk_autoobs//k5ts2/ autoobs is running! 2006.224.08:25:23.25/chk_autoobs//k5ts3/ autoobs is running! 2006.224.08:25:23.62/chk_autoobs//k5ts4/ autoobs is running! 2006.224.08:25:23.99/chk_obsdata//k5ts1/T2240824??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.224.08:25:24.36/chk_obsdata//k5ts2/T2240824??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.224.08:25:24.72/chk_obsdata//k5ts3/T2240824??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.224.08:25:25.09/chk_obsdata//k5ts4/T2240824??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.224.08:25:25.77/k5log//k5ts1_log_newline 2006.224.08:25:26.46/k5log//k5ts2_log_newline 2006.224.08:25:27.14/k5log//k5ts3_log_newline 2006.224.08:25:27.82/k5log//k5ts4_log_newline 2006.224.08:25:27.85/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.224.08:25:27.85:4f8m12a=3 2006.224.08:25:27.85$4f8m12a/echo=on 2006.224.08:25:27.85$4f8m12a/pcalon 2006.224.08:25:27.85$pcalon/"no phase cal control is implemented here 2006.224.08:25:27.85$4f8m12a/"tpicd=stop 2006.224.08:25:27.85$4f8m12a/vc4f8 2006.224.08:25:27.85$vc4f8/valo=1,532.99 2006.224.08:25:27.85#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.224.08:25:27.85#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.224.08:25:27.85#ibcon#ireg 17 cls_cnt 0 2006.224.08:25:27.85#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.224.08:25:27.85#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.224.08:25:27.85#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.224.08:25:27.85#ibcon#enter wrdev, iclass 34, count 0 2006.224.08:25:27.85#ibcon#first serial, iclass 34, count 0 2006.224.08:25:27.85#ibcon#enter sib2, iclass 34, count 0 2006.224.08:25:27.85#ibcon#flushed, iclass 34, count 0 2006.224.08:25:27.85#ibcon#about to write, iclass 34, count 0 2006.224.08:25:27.85#ibcon#wrote, iclass 34, count 0 2006.224.08:25:27.85#ibcon#about to read 3, iclass 34, count 0 2006.224.08:25:27.86#ibcon#read 3, iclass 34, count 0 2006.224.08:25:27.86#ibcon#about to read 4, iclass 34, count 0 2006.224.08:25:27.86#ibcon#read 4, iclass 34, count 0 2006.224.08:25:27.86#ibcon#about to read 5, iclass 34, count 0 2006.224.08:25:27.86#ibcon#read 5, iclass 34, count 0 2006.224.08:25:27.86#ibcon#about to read 6, iclass 34, count 0 2006.224.08:25:27.86#ibcon#read 6, iclass 34, count 0 2006.224.08:25:27.86#ibcon#end of sib2, iclass 34, count 0 2006.224.08:25:27.86#ibcon#*mode == 0, iclass 34, count 0 2006.224.08:25:27.86#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.224.08:25:27.86#ibcon#[26=FRQ=01,532.99\r\n] 2006.224.08:25:27.86#ibcon#*before write, iclass 34, count 0 2006.224.08:25:27.86#ibcon#enter sib2, iclass 34, count 0 2006.224.08:25:27.86#ibcon#flushed, iclass 34, count 0 2006.224.08:25:27.86#ibcon#about to write, iclass 34, count 0 2006.224.08:25:27.86#ibcon#wrote, iclass 34, count 0 2006.224.08:25:27.86#ibcon#about to read 3, iclass 34, count 0 2006.224.08:25:27.91#ibcon#read 3, iclass 34, count 0 2006.224.08:25:27.91#ibcon#about to read 4, iclass 34, count 0 2006.224.08:25:27.91#ibcon#read 4, iclass 34, count 0 2006.224.08:25:27.91#ibcon#about to read 5, iclass 34, count 0 2006.224.08:25:27.91#ibcon#read 5, iclass 34, count 0 2006.224.08:25:27.91#ibcon#about to read 6, iclass 34, count 0 2006.224.08:25:27.91#ibcon#read 6, iclass 34, count 0 2006.224.08:25:27.91#ibcon#end of sib2, iclass 34, count 0 2006.224.08:25:27.91#ibcon#*after write, iclass 34, count 0 2006.224.08:25:27.91#ibcon#*before return 0, iclass 34, count 0 2006.224.08:25:27.91#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.224.08:25:27.91#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.224.08:25:27.91#ibcon#about to clear, iclass 34 cls_cnt 0 2006.224.08:25:27.91#ibcon#cleared, iclass 34 cls_cnt 0 2006.224.08:25:27.91$vc4f8/va=1,8 2006.224.08:25:27.91#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.224.08:25:27.91#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.224.08:25:27.91#ibcon#ireg 11 cls_cnt 2 2006.224.08:25:27.91#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.224.08:25:27.91#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.224.08:25:27.91#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.224.08:25:27.91#ibcon#enter wrdev, iclass 36, count 2 2006.224.08:25:27.91#ibcon#first serial, iclass 36, count 2 2006.224.08:25:27.91#ibcon#enter sib2, iclass 36, count 2 2006.224.08:25:27.91#ibcon#flushed, iclass 36, count 2 2006.224.08:25:27.91#ibcon#about to write, iclass 36, count 2 2006.224.08:25:27.91#ibcon#wrote, iclass 36, count 2 2006.224.08:25:27.91#ibcon#about to read 3, iclass 36, count 2 2006.224.08:25:27.93#ibcon#read 3, iclass 36, count 2 2006.224.08:25:27.93#ibcon#about to read 4, iclass 36, count 2 2006.224.08:25:27.93#ibcon#read 4, iclass 36, count 2 2006.224.08:25:27.93#ibcon#about to read 5, iclass 36, count 2 2006.224.08:25:27.93#ibcon#read 5, iclass 36, count 2 2006.224.08:25:27.93#ibcon#about to read 6, iclass 36, count 2 2006.224.08:25:27.93#ibcon#read 6, iclass 36, count 2 2006.224.08:25:27.93#ibcon#end of sib2, iclass 36, count 2 2006.224.08:25:27.93#ibcon#*mode == 0, iclass 36, count 2 2006.224.08:25:27.93#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.224.08:25:27.93#ibcon#[25=AT01-08\r\n] 2006.224.08:25:27.93#ibcon#*before write, iclass 36, count 2 2006.224.08:25:27.93#ibcon#enter sib2, iclass 36, count 2 2006.224.08:25:27.93#ibcon#flushed, iclass 36, count 2 2006.224.08:25:27.93#ibcon#about to write, iclass 36, count 2 2006.224.08:25:27.93#ibcon#wrote, iclass 36, count 2 2006.224.08:25:27.93#ibcon#about to read 3, iclass 36, count 2 2006.224.08:25:27.97#ibcon#read 3, iclass 36, count 2 2006.224.08:25:27.97#ibcon#about to read 4, iclass 36, count 2 2006.224.08:25:27.97#ibcon#read 4, iclass 36, count 2 2006.224.08:25:27.97#ibcon#about to read 5, iclass 36, count 2 2006.224.08:25:27.97#ibcon#read 5, iclass 36, count 2 2006.224.08:25:27.97#ibcon#about to read 6, iclass 36, count 2 2006.224.08:25:27.97#ibcon#read 6, iclass 36, count 2 2006.224.08:25:27.97#ibcon#end of sib2, iclass 36, count 2 2006.224.08:25:27.97#ibcon#*after write, iclass 36, count 2 2006.224.08:25:27.97#ibcon#*before return 0, iclass 36, count 2 2006.224.08:25:27.97#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.224.08:25:27.97#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.224.08:25:27.97#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.224.08:25:27.97#ibcon#ireg 7 cls_cnt 0 2006.224.08:25:27.97#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.224.08:25:28.08#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.224.08:25:28.08#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.224.08:25:28.08#ibcon#enter wrdev, iclass 36, count 0 2006.224.08:25:28.08#ibcon#first serial, iclass 36, count 0 2006.224.08:25:28.08#ibcon#enter sib2, iclass 36, count 0 2006.224.08:25:28.08#ibcon#flushed, iclass 36, count 0 2006.224.08:25:28.08#ibcon#about to write, iclass 36, count 0 2006.224.08:25:28.08#ibcon#wrote, iclass 36, count 0 2006.224.08:25:28.08#ibcon#about to read 3, iclass 36, count 0 2006.224.08:25:28.10#ibcon#read 3, iclass 36, count 0 2006.224.08:25:28.10#ibcon#about to read 4, iclass 36, count 0 2006.224.08:25:28.10#ibcon#read 4, iclass 36, count 0 2006.224.08:25:28.10#ibcon#about to read 5, iclass 36, count 0 2006.224.08:25:28.10#ibcon#read 5, iclass 36, count 0 2006.224.08:25:28.10#ibcon#about to read 6, iclass 36, count 0 2006.224.08:25:28.10#ibcon#read 6, iclass 36, count 0 2006.224.08:25:28.10#ibcon#end of sib2, iclass 36, count 0 2006.224.08:25:28.10#ibcon#*mode == 0, iclass 36, count 0 2006.224.08:25:28.10#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.224.08:25:28.10#ibcon#[25=USB\r\n] 2006.224.08:25:28.10#ibcon#*before write, iclass 36, count 0 2006.224.08:25:28.10#ibcon#enter sib2, iclass 36, count 0 2006.224.08:25:28.10#ibcon#flushed, iclass 36, count 0 2006.224.08:25:28.10#ibcon#about to write, iclass 36, count 0 2006.224.08:25:28.10#ibcon#wrote, iclass 36, count 0 2006.224.08:25:28.10#ibcon#about to read 3, iclass 36, count 0 2006.224.08:25:28.13#ibcon#read 3, iclass 36, count 0 2006.224.08:25:28.13#ibcon#about to read 4, iclass 36, count 0 2006.224.08:25:28.13#ibcon#read 4, iclass 36, count 0 2006.224.08:25:28.13#ibcon#about to read 5, iclass 36, count 0 2006.224.08:25:28.13#ibcon#read 5, iclass 36, count 0 2006.224.08:25:28.13#ibcon#about to read 6, iclass 36, count 0 2006.224.08:25:28.13#ibcon#read 6, iclass 36, count 0 2006.224.08:25:28.13#ibcon#end of sib2, iclass 36, count 0 2006.224.08:25:28.13#ibcon#*after write, iclass 36, count 0 2006.224.08:25:28.13#ibcon#*before return 0, iclass 36, count 0 2006.224.08:25:28.13#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.224.08:25:28.13#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.224.08:25:28.13#ibcon#about to clear, iclass 36 cls_cnt 0 2006.224.08:25:28.13#ibcon#cleared, iclass 36 cls_cnt 0 2006.224.08:25:28.13$vc4f8/valo=2,572.99 2006.224.08:25:28.13#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.224.08:25:28.13#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.224.08:25:28.13#ibcon#ireg 17 cls_cnt 0 2006.224.08:25:28.13#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.224.08:25:28.13#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.224.08:25:28.13#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.224.08:25:28.13#ibcon#enter wrdev, iclass 38, count 0 2006.224.08:25:28.13#ibcon#first serial, iclass 38, count 0 2006.224.08:25:28.13#ibcon#enter sib2, iclass 38, count 0 2006.224.08:25:28.13#ibcon#flushed, iclass 38, count 0 2006.224.08:25:28.13#ibcon#about to write, iclass 38, count 0 2006.224.08:25:28.13#ibcon#wrote, iclass 38, count 0 2006.224.08:25:28.13#ibcon#about to read 3, iclass 38, count 0 2006.224.08:25:28.16#ibcon#read 3, iclass 38, count 0 2006.224.08:25:28.16#ibcon#about to read 4, iclass 38, count 0 2006.224.08:25:28.16#ibcon#read 4, iclass 38, count 0 2006.224.08:25:28.16#ibcon#about to read 5, iclass 38, count 0 2006.224.08:25:28.16#ibcon#read 5, iclass 38, count 0 2006.224.08:25:28.16#ibcon#about to read 6, iclass 38, count 0 2006.224.08:25:28.16#ibcon#read 6, iclass 38, count 0 2006.224.08:25:28.16#ibcon#end of sib2, iclass 38, count 0 2006.224.08:25:28.16#ibcon#*mode == 0, iclass 38, count 0 2006.224.08:25:28.16#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.224.08:25:28.16#ibcon#[26=FRQ=02,572.99\r\n] 2006.224.08:25:28.16#ibcon#*before write, iclass 38, count 0 2006.224.08:25:28.16#ibcon#enter sib2, iclass 38, count 0 2006.224.08:25:28.16#ibcon#flushed, iclass 38, count 0 2006.224.08:25:28.16#ibcon#about to write, iclass 38, count 0 2006.224.08:25:28.16#ibcon#wrote, iclass 38, count 0 2006.224.08:25:28.16#ibcon#about to read 3, iclass 38, count 0 2006.224.08:25:28.20#ibcon#read 3, iclass 38, count 0 2006.224.08:25:28.20#ibcon#about to read 4, iclass 38, count 0 2006.224.08:25:28.20#ibcon#read 4, iclass 38, count 0 2006.224.08:25:28.20#ibcon#about to read 5, iclass 38, count 0 2006.224.08:25:28.20#ibcon#read 5, iclass 38, count 0 2006.224.08:25:28.20#ibcon#about to read 6, iclass 38, count 0 2006.224.08:25:28.20#ibcon#read 6, iclass 38, count 0 2006.224.08:25:28.20#ibcon#end of sib2, iclass 38, count 0 2006.224.08:25:28.20#ibcon#*after write, iclass 38, count 0 2006.224.08:25:28.20#ibcon#*before return 0, iclass 38, count 0 2006.224.08:25:28.20#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.224.08:25:28.20#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.224.08:25:28.20#ibcon#about to clear, iclass 38 cls_cnt 0 2006.224.08:25:28.20#ibcon#cleared, iclass 38 cls_cnt 0 2006.224.08:25:28.20$vc4f8/va=2,7 2006.224.08:25:28.20#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.224.08:25:28.20#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.224.08:25:28.20#ibcon#ireg 11 cls_cnt 2 2006.224.08:25:28.20#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.224.08:25:28.25#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.224.08:25:28.25#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.224.08:25:28.25#ibcon#enter wrdev, iclass 40, count 2 2006.224.08:25:28.25#ibcon#first serial, iclass 40, count 2 2006.224.08:25:28.25#ibcon#enter sib2, iclass 40, count 2 2006.224.08:25:28.25#ibcon#flushed, iclass 40, count 2 2006.224.08:25:28.25#ibcon#about to write, iclass 40, count 2 2006.224.08:25:28.25#ibcon#wrote, iclass 40, count 2 2006.224.08:25:28.25#ibcon#about to read 3, iclass 40, count 2 2006.224.08:25:28.27#ibcon#read 3, iclass 40, count 2 2006.224.08:25:28.27#ibcon#about to read 4, iclass 40, count 2 2006.224.08:25:28.27#ibcon#read 4, iclass 40, count 2 2006.224.08:25:28.27#ibcon#about to read 5, iclass 40, count 2 2006.224.08:25:28.27#ibcon#read 5, iclass 40, count 2 2006.224.08:25:28.27#ibcon#about to read 6, iclass 40, count 2 2006.224.08:25:28.27#ibcon#read 6, iclass 40, count 2 2006.224.08:25:28.27#ibcon#end of sib2, iclass 40, count 2 2006.224.08:25:28.27#ibcon#*mode == 0, iclass 40, count 2 2006.224.08:25:28.27#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.224.08:25:28.27#ibcon#[25=AT02-07\r\n] 2006.224.08:25:28.27#ibcon#*before write, iclass 40, count 2 2006.224.08:25:28.27#ibcon#enter sib2, iclass 40, count 2 2006.224.08:25:28.27#ibcon#flushed, iclass 40, count 2 2006.224.08:25:28.27#ibcon#about to write, iclass 40, count 2 2006.224.08:25:28.27#ibcon#wrote, iclass 40, count 2 2006.224.08:25:28.27#ibcon#about to read 3, iclass 40, count 2 2006.224.08:25:28.30#ibcon#read 3, iclass 40, count 2 2006.224.08:25:28.30#ibcon#about to read 4, iclass 40, count 2 2006.224.08:25:28.30#ibcon#read 4, iclass 40, count 2 2006.224.08:25:28.30#ibcon#about to read 5, iclass 40, count 2 2006.224.08:25:28.30#ibcon#read 5, iclass 40, count 2 2006.224.08:25:28.30#ibcon#about to read 6, iclass 40, count 2 2006.224.08:25:28.30#ibcon#read 6, iclass 40, count 2 2006.224.08:25:28.30#ibcon#end of sib2, iclass 40, count 2 2006.224.08:25:28.30#ibcon#*after write, iclass 40, count 2 2006.224.08:25:28.30#ibcon#*before return 0, iclass 40, count 2 2006.224.08:25:28.30#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.224.08:25:28.30#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.224.08:25:28.30#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.224.08:25:28.30#ibcon#ireg 7 cls_cnt 0 2006.224.08:25:28.30#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.224.08:25:28.42#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.224.08:25:28.42#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.224.08:25:28.42#ibcon#enter wrdev, iclass 40, count 0 2006.224.08:25:28.42#ibcon#first serial, iclass 40, count 0 2006.224.08:25:28.42#ibcon#enter sib2, iclass 40, count 0 2006.224.08:25:28.42#ibcon#flushed, iclass 40, count 0 2006.224.08:25:28.42#ibcon#about to write, iclass 40, count 0 2006.224.08:25:28.42#ibcon#wrote, iclass 40, count 0 2006.224.08:25:28.42#ibcon#about to read 3, iclass 40, count 0 2006.224.08:25:28.44#ibcon#read 3, iclass 40, count 0 2006.224.08:25:28.44#ibcon#about to read 4, iclass 40, count 0 2006.224.08:25:28.44#ibcon#read 4, iclass 40, count 0 2006.224.08:25:28.44#ibcon#about to read 5, iclass 40, count 0 2006.224.08:25:28.44#ibcon#read 5, iclass 40, count 0 2006.224.08:25:28.44#ibcon#about to read 6, iclass 40, count 0 2006.224.08:25:28.44#ibcon#read 6, iclass 40, count 0 2006.224.08:25:28.44#ibcon#end of sib2, iclass 40, count 0 2006.224.08:25:28.44#ibcon#*mode == 0, iclass 40, count 0 2006.224.08:25:28.44#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.224.08:25:28.44#ibcon#[25=USB\r\n] 2006.224.08:25:28.44#ibcon#*before write, iclass 40, count 0 2006.224.08:25:28.44#ibcon#enter sib2, iclass 40, count 0 2006.224.08:25:28.44#ibcon#flushed, iclass 40, count 0 2006.224.08:25:28.44#ibcon#about to write, iclass 40, count 0 2006.224.08:25:28.44#ibcon#wrote, iclass 40, count 0 2006.224.08:25:28.44#ibcon#about to read 3, iclass 40, count 0 2006.224.08:25:28.47#ibcon#read 3, iclass 40, count 0 2006.224.08:25:28.47#ibcon#about to read 4, iclass 40, count 0 2006.224.08:25:28.47#ibcon#read 4, iclass 40, count 0 2006.224.08:25:28.47#ibcon#about to read 5, iclass 40, count 0 2006.224.08:25:28.47#ibcon#read 5, iclass 40, count 0 2006.224.08:25:28.47#ibcon#about to read 6, iclass 40, count 0 2006.224.08:25:28.47#ibcon#read 6, iclass 40, count 0 2006.224.08:25:28.47#ibcon#end of sib2, iclass 40, count 0 2006.224.08:25:28.47#ibcon#*after write, iclass 40, count 0 2006.224.08:25:28.47#ibcon#*before return 0, iclass 40, count 0 2006.224.08:25:28.47#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.224.08:25:28.47#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.224.08:25:28.47#ibcon#about to clear, iclass 40 cls_cnt 0 2006.224.08:25:28.47#ibcon#cleared, iclass 40 cls_cnt 0 2006.224.08:25:28.47$vc4f8/valo=3,672.99 2006.224.08:25:28.47#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.224.08:25:28.47#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.224.08:25:28.47#ibcon#ireg 17 cls_cnt 0 2006.224.08:25:28.47#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.224.08:25:28.47#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.224.08:25:28.47#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.224.08:25:28.47#ibcon#enter wrdev, iclass 4, count 0 2006.224.08:25:28.47#ibcon#first serial, iclass 4, count 0 2006.224.08:25:28.47#ibcon#enter sib2, iclass 4, count 0 2006.224.08:25:28.47#ibcon#flushed, iclass 4, count 0 2006.224.08:25:28.47#ibcon#about to write, iclass 4, count 0 2006.224.08:25:28.47#ibcon#wrote, iclass 4, count 0 2006.224.08:25:28.47#ibcon#about to read 3, iclass 4, count 0 2006.224.08:25:28.50#ibcon#read 3, iclass 4, count 0 2006.224.08:25:28.50#ibcon#about to read 4, iclass 4, count 0 2006.224.08:25:28.50#ibcon#read 4, iclass 4, count 0 2006.224.08:25:28.50#ibcon#about to read 5, iclass 4, count 0 2006.224.08:25:28.50#ibcon#read 5, iclass 4, count 0 2006.224.08:25:28.50#ibcon#about to read 6, iclass 4, count 0 2006.224.08:25:28.50#ibcon#read 6, iclass 4, count 0 2006.224.08:25:28.50#ibcon#end of sib2, iclass 4, count 0 2006.224.08:25:28.50#ibcon#*mode == 0, iclass 4, count 0 2006.224.08:25:28.50#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.224.08:25:28.50#ibcon#[26=FRQ=03,672.99\r\n] 2006.224.08:25:28.50#ibcon#*before write, iclass 4, count 0 2006.224.08:25:28.50#ibcon#enter sib2, iclass 4, count 0 2006.224.08:25:28.50#ibcon#flushed, iclass 4, count 0 2006.224.08:25:28.50#ibcon#about to write, iclass 4, count 0 2006.224.08:25:28.50#ibcon#wrote, iclass 4, count 0 2006.224.08:25:28.50#ibcon#about to read 3, iclass 4, count 0 2006.224.08:25:28.54#ibcon#read 3, iclass 4, count 0 2006.224.08:25:28.54#ibcon#about to read 4, iclass 4, count 0 2006.224.08:25:28.54#ibcon#read 4, iclass 4, count 0 2006.224.08:25:28.54#ibcon#about to read 5, iclass 4, count 0 2006.224.08:25:28.54#ibcon#read 5, iclass 4, count 0 2006.224.08:25:28.54#ibcon#about to read 6, iclass 4, count 0 2006.224.08:25:28.54#ibcon#read 6, iclass 4, count 0 2006.224.08:25:28.54#ibcon#end of sib2, iclass 4, count 0 2006.224.08:25:28.54#ibcon#*after write, iclass 4, count 0 2006.224.08:25:28.54#ibcon#*before return 0, iclass 4, count 0 2006.224.08:25:28.54#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.224.08:25:28.54#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.224.08:25:28.54#ibcon#about to clear, iclass 4 cls_cnt 0 2006.224.08:25:28.54#ibcon#cleared, iclass 4 cls_cnt 0 2006.224.08:25:28.54$vc4f8/va=3,6 2006.224.08:25:28.54#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.224.08:25:28.54#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.224.08:25:28.54#ibcon#ireg 11 cls_cnt 2 2006.224.08:25:28.54#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.224.08:25:28.59#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.224.08:25:28.59#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.224.08:25:28.59#ibcon#enter wrdev, iclass 6, count 2 2006.224.08:25:28.59#ibcon#first serial, iclass 6, count 2 2006.224.08:25:28.59#ibcon#enter sib2, iclass 6, count 2 2006.224.08:25:28.59#ibcon#flushed, iclass 6, count 2 2006.224.08:25:28.59#ibcon#about to write, iclass 6, count 2 2006.224.08:25:28.59#ibcon#wrote, iclass 6, count 2 2006.224.08:25:28.59#ibcon#about to read 3, iclass 6, count 2 2006.224.08:25:28.61#ibcon#read 3, iclass 6, count 2 2006.224.08:25:28.61#ibcon#about to read 4, iclass 6, count 2 2006.224.08:25:28.61#ibcon#read 4, iclass 6, count 2 2006.224.08:25:28.61#ibcon#about to read 5, iclass 6, count 2 2006.224.08:25:28.61#ibcon#read 5, iclass 6, count 2 2006.224.08:25:28.61#ibcon#about to read 6, iclass 6, count 2 2006.224.08:25:28.61#ibcon#read 6, iclass 6, count 2 2006.224.08:25:28.61#ibcon#end of sib2, iclass 6, count 2 2006.224.08:25:28.61#ibcon#*mode == 0, iclass 6, count 2 2006.224.08:25:28.61#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.224.08:25:28.61#ibcon#[25=AT03-06\r\n] 2006.224.08:25:28.61#ibcon#*before write, iclass 6, count 2 2006.224.08:25:28.61#ibcon#enter sib2, iclass 6, count 2 2006.224.08:25:28.61#ibcon#flushed, iclass 6, count 2 2006.224.08:25:28.61#ibcon#about to write, iclass 6, count 2 2006.224.08:25:28.61#ibcon#wrote, iclass 6, count 2 2006.224.08:25:28.61#ibcon#about to read 3, iclass 6, count 2 2006.224.08:25:28.64#ibcon#read 3, iclass 6, count 2 2006.224.08:25:28.64#ibcon#about to read 4, iclass 6, count 2 2006.224.08:25:28.64#ibcon#read 4, iclass 6, count 2 2006.224.08:25:28.64#ibcon#about to read 5, iclass 6, count 2 2006.224.08:25:28.64#ibcon#read 5, iclass 6, count 2 2006.224.08:25:28.64#ibcon#about to read 6, iclass 6, count 2 2006.224.08:25:28.64#ibcon#read 6, iclass 6, count 2 2006.224.08:25:28.64#ibcon#end of sib2, iclass 6, count 2 2006.224.08:25:28.64#ibcon#*after write, iclass 6, count 2 2006.224.08:25:28.64#ibcon#*before return 0, iclass 6, count 2 2006.224.08:25:28.64#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.224.08:25:28.64#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.224.08:25:28.64#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.224.08:25:28.64#ibcon#ireg 7 cls_cnt 0 2006.224.08:25:28.64#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.224.08:25:28.76#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.224.08:25:28.76#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.224.08:25:28.76#ibcon#enter wrdev, iclass 6, count 0 2006.224.08:25:28.76#ibcon#first serial, iclass 6, count 0 2006.224.08:25:28.76#ibcon#enter sib2, iclass 6, count 0 2006.224.08:25:28.76#ibcon#flushed, iclass 6, count 0 2006.224.08:25:28.76#ibcon#about to write, iclass 6, count 0 2006.224.08:25:28.76#ibcon#wrote, iclass 6, count 0 2006.224.08:25:28.76#ibcon#about to read 3, iclass 6, count 0 2006.224.08:25:28.78#ibcon#read 3, iclass 6, count 0 2006.224.08:25:28.78#ibcon#about to read 4, iclass 6, count 0 2006.224.08:25:28.78#ibcon#read 4, iclass 6, count 0 2006.224.08:25:28.78#ibcon#about to read 5, iclass 6, count 0 2006.224.08:25:28.78#ibcon#read 5, iclass 6, count 0 2006.224.08:25:28.78#ibcon#about to read 6, iclass 6, count 0 2006.224.08:25:28.78#ibcon#read 6, iclass 6, count 0 2006.224.08:25:28.78#ibcon#end of sib2, iclass 6, count 0 2006.224.08:25:28.78#ibcon#*mode == 0, iclass 6, count 0 2006.224.08:25:28.78#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.224.08:25:28.78#ibcon#[25=USB\r\n] 2006.224.08:25:28.78#ibcon#*before write, iclass 6, count 0 2006.224.08:25:28.78#ibcon#enter sib2, iclass 6, count 0 2006.224.08:25:28.78#ibcon#flushed, iclass 6, count 0 2006.224.08:25:28.78#ibcon#about to write, iclass 6, count 0 2006.224.08:25:28.78#ibcon#wrote, iclass 6, count 0 2006.224.08:25:28.78#ibcon#about to read 3, iclass 6, count 0 2006.224.08:25:28.81#ibcon#read 3, iclass 6, count 0 2006.224.08:25:28.81#ibcon#about to read 4, iclass 6, count 0 2006.224.08:25:28.81#ibcon#read 4, iclass 6, count 0 2006.224.08:25:28.81#ibcon#about to read 5, iclass 6, count 0 2006.224.08:25:28.81#ibcon#read 5, iclass 6, count 0 2006.224.08:25:28.81#ibcon#about to read 6, iclass 6, count 0 2006.224.08:25:28.81#ibcon#read 6, iclass 6, count 0 2006.224.08:25:28.81#ibcon#end of sib2, iclass 6, count 0 2006.224.08:25:28.81#ibcon#*after write, iclass 6, count 0 2006.224.08:25:28.81#ibcon#*before return 0, iclass 6, count 0 2006.224.08:25:28.81#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.224.08:25:28.81#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.224.08:25:28.81#ibcon#about to clear, iclass 6 cls_cnt 0 2006.224.08:25:28.81#ibcon#cleared, iclass 6 cls_cnt 0 2006.224.08:25:28.81$vc4f8/valo=4,832.99 2006.224.08:25:28.81#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.224.08:25:28.81#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.224.08:25:28.81#ibcon#ireg 17 cls_cnt 0 2006.224.08:25:28.81#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.224.08:25:28.81#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.224.08:25:28.81#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.224.08:25:28.81#ibcon#enter wrdev, iclass 10, count 0 2006.224.08:25:28.81#ibcon#first serial, iclass 10, count 0 2006.224.08:25:28.81#ibcon#enter sib2, iclass 10, count 0 2006.224.08:25:28.81#ibcon#flushed, iclass 10, count 0 2006.224.08:25:28.81#ibcon#about to write, iclass 10, count 0 2006.224.08:25:28.81#ibcon#wrote, iclass 10, count 0 2006.224.08:25:28.81#ibcon#about to read 3, iclass 10, count 0 2006.224.08:25:28.84#ibcon#read 3, iclass 10, count 0 2006.224.08:25:28.84#ibcon#about to read 4, iclass 10, count 0 2006.224.08:25:28.84#ibcon#read 4, iclass 10, count 0 2006.224.08:25:28.84#ibcon#about to read 5, iclass 10, count 0 2006.224.08:25:28.84#ibcon#read 5, iclass 10, count 0 2006.224.08:25:28.84#ibcon#about to read 6, iclass 10, count 0 2006.224.08:25:28.84#ibcon#read 6, iclass 10, count 0 2006.224.08:25:28.84#ibcon#end of sib2, iclass 10, count 0 2006.224.08:25:28.84#ibcon#*mode == 0, iclass 10, count 0 2006.224.08:25:28.84#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.224.08:25:28.84#ibcon#[26=FRQ=04,832.99\r\n] 2006.224.08:25:28.84#ibcon#*before write, iclass 10, count 0 2006.224.08:25:28.84#ibcon#enter sib2, iclass 10, count 0 2006.224.08:25:28.84#ibcon#flushed, iclass 10, count 0 2006.224.08:25:28.84#ibcon#about to write, iclass 10, count 0 2006.224.08:25:28.84#ibcon#wrote, iclass 10, count 0 2006.224.08:25:28.84#ibcon#about to read 3, iclass 10, count 0 2006.224.08:25:28.88#ibcon#read 3, iclass 10, count 0 2006.224.08:25:28.88#ibcon#about to read 4, iclass 10, count 0 2006.224.08:25:28.88#ibcon#read 4, iclass 10, count 0 2006.224.08:25:28.88#ibcon#about to read 5, iclass 10, count 0 2006.224.08:25:28.88#ibcon#read 5, iclass 10, count 0 2006.224.08:25:28.88#ibcon#about to read 6, iclass 10, count 0 2006.224.08:25:28.88#ibcon#read 6, iclass 10, count 0 2006.224.08:25:28.88#ibcon#end of sib2, iclass 10, count 0 2006.224.08:25:28.88#ibcon#*after write, iclass 10, count 0 2006.224.08:25:28.88#ibcon#*before return 0, iclass 10, count 0 2006.224.08:25:28.88#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.224.08:25:28.88#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.224.08:25:28.88#ibcon#about to clear, iclass 10 cls_cnt 0 2006.224.08:25:28.88#ibcon#cleared, iclass 10 cls_cnt 0 2006.224.08:25:28.88$vc4f8/va=4,7 2006.224.08:25:28.88#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.224.08:25:28.88#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.224.08:25:28.88#ibcon#ireg 11 cls_cnt 2 2006.224.08:25:28.88#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.224.08:25:28.93#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.224.08:25:28.93#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.224.08:25:28.93#ibcon#enter wrdev, iclass 12, count 2 2006.224.08:25:28.93#ibcon#first serial, iclass 12, count 2 2006.224.08:25:28.93#ibcon#enter sib2, iclass 12, count 2 2006.224.08:25:28.93#ibcon#flushed, iclass 12, count 2 2006.224.08:25:28.93#ibcon#about to write, iclass 12, count 2 2006.224.08:25:28.93#ibcon#wrote, iclass 12, count 2 2006.224.08:25:28.93#ibcon#about to read 3, iclass 12, count 2 2006.224.08:25:28.95#ibcon#read 3, iclass 12, count 2 2006.224.08:25:28.95#ibcon#about to read 4, iclass 12, count 2 2006.224.08:25:28.95#ibcon#read 4, iclass 12, count 2 2006.224.08:25:28.95#ibcon#about to read 5, iclass 12, count 2 2006.224.08:25:28.95#ibcon#read 5, iclass 12, count 2 2006.224.08:25:28.95#ibcon#about to read 6, iclass 12, count 2 2006.224.08:25:28.95#ibcon#read 6, iclass 12, count 2 2006.224.08:25:28.95#ibcon#end of sib2, iclass 12, count 2 2006.224.08:25:28.95#ibcon#*mode == 0, iclass 12, count 2 2006.224.08:25:28.95#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.224.08:25:28.95#ibcon#[25=AT04-07\r\n] 2006.224.08:25:28.95#ibcon#*before write, iclass 12, count 2 2006.224.08:25:28.95#ibcon#enter sib2, iclass 12, count 2 2006.224.08:25:28.95#ibcon#flushed, iclass 12, count 2 2006.224.08:25:28.95#ibcon#about to write, iclass 12, count 2 2006.224.08:25:28.95#ibcon#wrote, iclass 12, count 2 2006.224.08:25:28.95#ibcon#about to read 3, iclass 12, count 2 2006.224.08:25:28.98#ibcon#read 3, iclass 12, count 2 2006.224.08:25:28.98#ibcon#about to read 4, iclass 12, count 2 2006.224.08:25:28.98#ibcon#read 4, iclass 12, count 2 2006.224.08:25:28.98#ibcon#about to read 5, iclass 12, count 2 2006.224.08:25:28.98#ibcon#read 5, iclass 12, count 2 2006.224.08:25:28.98#ibcon#about to read 6, iclass 12, count 2 2006.224.08:25:28.98#ibcon#read 6, iclass 12, count 2 2006.224.08:25:28.98#ibcon#end of sib2, iclass 12, count 2 2006.224.08:25:28.98#ibcon#*after write, iclass 12, count 2 2006.224.08:25:28.98#ibcon#*before return 0, iclass 12, count 2 2006.224.08:25:28.98#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.224.08:25:28.98#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.224.08:25:28.98#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.224.08:25:28.98#ibcon#ireg 7 cls_cnt 0 2006.224.08:25:28.98#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.224.08:25:29.10#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.224.08:25:29.10#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.224.08:25:29.10#ibcon#enter wrdev, iclass 12, count 0 2006.224.08:25:29.10#ibcon#first serial, iclass 12, count 0 2006.224.08:25:29.10#ibcon#enter sib2, iclass 12, count 0 2006.224.08:25:29.10#ibcon#flushed, iclass 12, count 0 2006.224.08:25:29.10#ibcon#about to write, iclass 12, count 0 2006.224.08:25:29.10#ibcon#wrote, iclass 12, count 0 2006.224.08:25:29.10#ibcon#about to read 3, iclass 12, count 0 2006.224.08:25:29.12#ibcon#read 3, iclass 12, count 0 2006.224.08:25:29.12#ibcon#about to read 4, iclass 12, count 0 2006.224.08:25:29.12#ibcon#read 4, iclass 12, count 0 2006.224.08:25:29.12#ibcon#about to read 5, iclass 12, count 0 2006.224.08:25:29.12#ibcon#read 5, iclass 12, count 0 2006.224.08:25:29.12#ibcon#about to read 6, iclass 12, count 0 2006.224.08:25:29.12#ibcon#read 6, iclass 12, count 0 2006.224.08:25:29.12#ibcon#end of sib2, iclass 12, count 0 2006.224.08:25:29.12#ibcon#*mode == 0, iclass 12, count 0 2006.224.08:25:29.12#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.224.08:25:29.12#ibcon#[25=USB\r\n] 2006.224.08:25:29.12#ibcon#*before write, iclass 12, count 0 2006.224.08:25:29.12#ibcon#enter sib2, iclass 12, count 0 2006.224.08:25:29.12#ibcon#flushed, iclass 12, count 0 2006.224.08:25:29.12#ibcon#about to write, iclass 12, count 0 2006.224.08:25:29.12#ibcon#wrote, iclass 12, count 0 2006.224.08:25:29.12#ibcon#about to read 3, iclass 12, count 0 2006.224.08:25:29.15#ibcon#read 3, iclass 12, count 0 2006.224.08:25:29.15#ibcon#about to read 4, iclass 12, count 0 2006.224.08:25:29.15#ibcon#read 4, iclass 12, count 0 2006.224.08:25:29.15#ibcon#about to read 5, iclass 12, count 0 2006.224.08:25:29.15#ibcon#read 5, iclass 12, count 0 2006.224.08:25:29.15#ibcon#about to read 6, iclass 12, count 0 2006.224.08:25:29.15#ibcon#read 6, iclass 12, count 0 2006.224.08:25:29.15#ibcon#end of sib2, iclass 12, count 0 2006.224.08:25:29.15#ibcon#*after write, iclass 12, count 0 2006.224.08:25:29.15#ibcon#*before return 0, iclass 12, count 0 2006.224.08:25:29.15#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.224.08:25:29.15#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.224.08:25:29.15#ibcon#about to clear, iclass 12 cls_cnt 0 2006.224.08:25:29.15#ibcon#cleared, iclass 12 cls_cnt 0 2006.224.08:25:29.15$vc4f8/valo=5,652.99 2006.224.08:25:29.15#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.224.08:25:29.15#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.224.08:25:29.15#ibcon#ireg 17 cls_cnt 0 2006.224.08:25:29.15#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.224.08:25:29.15#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.224.08:25:29.15#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.224.08:25:29.15#ibcon#enter wrdev, iclass 14, count 0 2006.224.08:25:29.15#ibcon#first serial, iclass 14, count 0 2006.224.08:25:29.15#ibcon#enter sib2, iclass 14, count 0 2006.224.08:25:29.15#ibcon#flushed, iclass 14, count 0 2006.224.08:25:29.15#ibcon#about to write, iclass 14, count 0 2006.224.08:25:29.15#ibcon#wrote, iclass 14, count 0 2006.224.08:25:29.15#ibcon#about to read 3, iclass 14, count 0 2006.224.08:25:29.17#ibcon#read 3, iclass 14, count 0 2006.224.08:25:29.17#ibcon#about to read 4, iclass 14, count 0 2006.224.08:25:29.17#ibcon#read 4, iclass 14, count 0 2006.224.08:25:29.17#ibcon#about to read 5, iclass 14, count 0 2006.224.08:25:29.17#ibcon#read 5, iclass 14, count 0 2006.224.08:25:29.17#ibcon#about to read 6, iclass 14, count 0 2006.224.08:25:29.17#ibcon#read 6, iclass 14, count 0 2006.224.08:25:29.17#ibcon#end of sib2, iclass 14, count 0 2006.224.08:25:29.17#ibcon#*mode == 0, iclass 14, count 0 2006.224.08:25:29.17#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.224.08:25:29.17#ibcon#[26=FRQ=05,652.99\r\n] 2006.224.08:25:29.17#ibcon#*before write, iclass 14, count 0 2006.224.08:25:29.17#ibcon#enter sib2, iclass 14, count 0 2006.224.08:25:29.17#ibcon#flushed, iclass 14, count 0 2006.224.08:25:29.17#ibcon#about to write, iclass 14, count 0 2006.224.08:25:29.17#ibcon#wrote, iclass 14, count 0 2006.224.08:25:29.17#ibcon#about to read 3, iclass 14, count 0 2006.224.08:25:29.21#ibcon#read 3, iclass 14, count 0 2006.224.08:25:29.21#ibcon#about to read 4, iclass 14, count 0 2006.224.08:25:29.21#ibcon#read 4, iclass 14, count 0 2006.224.08:25:29.21#ibcon#about to read 5, iclass 14, count 0 2006.224.08:25:29.21#ibcon#read 5, iclass 14, count 0 2006.224.08:25:29.21#ibcon#about to read 6, iclass 14, count 0 2006.224.08:25:29.21#ibcon#read 6, iclass 14, count 0 2006.224.08:25:29.21#ibcon#end of sib2, iclass 14, count 0 2006.224.08:25:29.21#ibcon#*after write, iclass 14, count 0 2006.224.08:25:29.21#ibcon#*before return 0, iclass 14, count 0 2006.224.08:25:29.21#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.224.08:25:29.21#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.224.08:25:29.21#ibcon#about to clear, iclass 14 cls_cnt 0 2006.224.08:25:29.21#ibcon#cleared, iclass 14 cls_cnt 0 2006.224.08:25:29.21$vc4f8/va=5,7 2006.224.08:25:29.21#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.224.08:25:29.21#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.224.08:25:29.21#ibcon#ireg 11 cls_cnt 2 2006.224.08:25:29.21#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.224.08:25:29.27#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.224.08:25:29.27#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.224.08:25:29.27#ibcon#enter wrdev, iclass 16, count 2 2006.224.08:25:29.27#ibcon#first serial, iclass 16, count 2 2006.224.08:25:29.27#ibcon#enter sib2, iclass 16, count 2 2006.224.08:25:29.27#ibcon#flushed, iclass 16, count 2 2006.224.08:25:29.27#ibcon#about to write, iclass 16, count 2 2006.224.08:25:29.27#ibcon#wrote, iclass 16, count 2 2006.224.08:25:29.27#ibcon#about to read 3, iclass 16, count 2 2006.224.08:25:29.29#ibcon#read 3, iclass 16, count 2 2006.224.08:25:29.29#ibcon#about to read 4, iclass 16, count 2 2006.224.08:25:29.29#ibcon#read 4, iclass 16, count 2 2006.224.08:25:29.29#ibcon#about to read 5, iclass 16, count 2 2006.224.08:25:29.29#ibcon#read 5, iclass 16, count 2 2006.224.08:25:29.29#ibcon#about to read 6, iclass 16, count 2 2006.224.08:25:29.29#ibcon#read 6, iclass 16, count 2 2006.224.08:25:29.29#ibcon#end of sib2, iclass 16, count 2 2006.224.08:25:29.29#ibcon#*mode == 0, iclass 16, count 2 2006.224.08:25:29.29#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.224.08:25:29.29#ibcon#[25=AT05-07\r\n] 2006.224.08:25:29.29#ibcon#*before write, iclass 16, count 2 2006.224.08:25:29.29#ibcon#enter sib2, iclass 16, count 2 2006.224.08:25:29.29#ibcon#flushed, iclass 16, count 2 2006.224.08:25:29.29#ibcon#about to write, iclass 16, count 2 2006.224.08:25:29.29#ibcon#wrote, iclass 16, count 2 2006.224.08:25:29.29#ibcon#about to read 3, iclass 16, count 2 2006.224.08:25:29.32#ibcon#read 3, iclass 16, count 2 2006.224.08:25:29.32#ibcon#about to read 4, iclass 16, count 2 2006.224.08:25:29.32#ibcon#read 4, iclass 16, count 2 2006.224.08:25:29.32#ibcon#about to read 5, iclass 16, count 2 2006.224.08:25:29.32#ibcon#read 5, iclass 16, count 2 2006.224.08:25:29.32#ibcon#about to read 6, iclass 16, count 2 2006.224.08:25:29.32#ibcon#read 6, iclass 16, count 2 2006.224.08:25:29.32#ibcon#end of sib2, iclass 16, count 2 2006.224.08:25:29.32#ibcon#*after write, iclass 16, count 2 2006.224.08:25:29.32#ibcon#*before return 0, iclass 16, count 2 2006.224.08:25:29.32#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.224.08:25:29.32#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.224.08:25:29.32#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.224.08:25:29.32#ibcon#ireg 7 cls_cnt 0 2006.224.08:25:29.32#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.224.08:25:29.44#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.224.08:25:29.44#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.224.08:25:29.44#ibcon#enter wrdev, iclass 16, count 0 2006.224.08:25:29.44#ibcon#first serial, iclass 16, count 0 2006.224.08:25:29.44#ibcon#enter sib2, iclass 16, count 0 2006.224.08:25:29.44#ibcon#flushed, iclass 16, count 0 2006.224.08:25:29.44#ibcon#about to write, iclass 16, count 0 2006.224.08:25:29.44#ibcon#wrote, iclass 16, count 0 2006.224.08:25:29.44#ibcon#about to read 3, iclass 16, count 0 2006.224.08:25:29.46#ibcon#read 3, iclass 16, count 0 2006.224.08:25:29.46#ibcon#about to read 4, iclass 16, count 0 2006.224.08:25:29.46#ibcon#read 4, iclass 16, count 0 2006.224.08:25:29.46#ibcon#about to read 5, iclass 16, count 0 2006.224.08:25:29.46#ibcon#read 5, iclass 16, count 0 2006.224.08:25:29.46#ibcon#about to read 6, iclass 16, count 0 2006.224.08:25:29.46#ibcon#read 6, iclass 16, count 0 2006.224.08:25:29.46#ibcon#end of sib2, iclass 16, count 0 2006.224.08:25:29.46#ibcon#*mode == 0, iclass 16, count 0 2006.224.08:25:29.46#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.224.08:25:29.46#ibcon#[25=USB\r\n] 2006.224.08:25:29.46#ibcon#*before write, iclass 16, count 0 2006.224.08:25:29.46#ibcon#enter sib2, iclass 16, count 0 2006.224.08:25:29.46#ibcon#flushed, iclass 16, count 0 2006.224.08:25:29.46#ibcon#about to write, iclass 16, count 0 2006.224.08:25:29.46#ibcon#wrote, iclass 16, count 0 2006.224.08:25:29.46#ibcon#about to read 3, iclass 16, count 0 2006.224.08:25:29.49#ibcon#read 3, iclass 16, count 0 2006.224.08:25:29.49#ibcon#about to read 4, iclass 16, count 0 2006.224.08:25:29.49#ibcon#read 4, iclass 16, count 0 2006.224.08:25:29.49#ibcon#about to read 5, iclass 16, count 0 2006.224.08:25:29.49#ibcon#read 5, iclass 16, count 0 2006.224.08:25:29.49#ibcon#about to read 6, iclass 16, count 0 2006.224.08:25:29.49#ibcon#read 6, iclass 16, count 0 2006.224.08:25:29.49#ibcon#end of sib2, iclass 16, count 0 2006.224.08:25:29.49#ibcon#*after write, iclass 16, count 0 2006.224.08:25:29.49#ibcon#*before return 0, iclass 16, count 0 2006.224.08:25:29.49#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.224.08:25:29.49#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.224.08:25:29.49#ibcon#about to clear, iclass 16 cls_cnt 0 2006.224.08:25:29.49#ibcon#cleared, iclass 16 cls_cnt 0 2006.224.08:25:29.49$vc4f8/valo=6,772.99 2006.224.08:25:29.49#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.224.08:25:29.49#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.224.08:25:29.49#ibcon#ireg 17 cls_cnt 0 2006.224.08:25:29.49#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.224.08:25:29.49#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.224.08:25:29.49#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.224.08:25:29.49#ibcon#enter wrdev, iclass 18, count 0 2006.224.08:25:29.49#ibcon#first serial, iclass 18, count 0 2006.224.08:25:29.49#ibcon#enter sib2, iclass 18, count 0 2006.224.08:25:29.49#ibcon#flushed, iclass 18, count 0 2006.224.08:25:29.49#ibcon#about to write, iclass 18, count 0 2006.224.08:25:29.49#ibcon#wrote, iclass 18, count 0 2006.224.08:25:29.49#ibcon#about to read 3, iclass 18, count 0 2006.224.08:25:29.52#ibcon#read 3, iclass 18, count 0 2006.224.08:25:29.52#ibcon#about to read 4, iclass 18, count 0 2006.224.08:25:29.52#ibcon#read 4, iclass 18, count 0 2006.224.08:25:29.52#ibcon#about to read 5, iclass 18, count 0 2006.224.08:25:29.52#ibcon#read 5, iclass 18, count 0 2006.224.08:25:29.52#ibcon#about to read 6, iclass 18, count 0 2006.224.08:25:29.52#ibcon#read 6, iclass 18, count 0 2006.224.08:25:29.52#ibcon#end of sib2, iclass 18, count 0 2006.224.08:25:29.52#ibcon#*mode == 0, iclass 18, count 0 2006.224.08:25:29.52#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.224.08:25:29.52#ibcon#[26=FRQ=06,772.99\r\n] 2006.224.08:25:29.52#ibcon#*before write, iclass 18, count 0 2006.224.08:25:29.52#ibcon#enter sib2, iclass 18, count 0 2006.224.08:25:29.52#ibcon#flushed, iclass 18, count 0 2006.224.08:25:29.52#ibcon#about to write, iclass 18, count 0 2006.224.08:25:29.52#ibcon#wrote, iclass 18, count 0 2006.224.08:25:29.52#ibcon#about to read 3, iclass 18, count 0 2006.224.08:25:29.56#ibcon#read 3, iclass 18, count 0 2006.224.08:25:29.56#ibcon#about to read 4, iclass 18, count 0 2006.224.08:25:29.56#ibcon#read 4, iclass 18, count 0 2006.224.08:25:29.56#ibcon#about to read 5, iclass 18, count 0 2006.224.08:25:29.56#ibcon#read 5, iclass 18, count 0 2006.224.08:25:29.56#ibcon#about to read 6, iclass 18, count 0 2006.224.08:25:29.56#ibcon#read 6, iclass 18, count 0 2006.224.08:25:29.56#ibcon#end of sib2, iclass 18, count 0 2006.224.08:25:29.56#ibcon#*after write, iclass 18, count 0 2006.224.08:25:29.56#ibcon#*before return 0, iclass 18, count 0 2006.224.08:25:29.56#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.224.08:25:29.56#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.224.08:25:29.56#ibcon#about to clear, iclass 18 cls_cnt 0 2006.224.08:25:29.56#ibcon#cleared, iclass 18 cls_cnt 0 2006.224.08:25:29.56$vc4f8/va=6,6 2006.224.08:25:29.56#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.224.08:25:29.56#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.224.08:25:29.56#ibcon#ireg 11 cls_cnt 2 2006.224.08:25:29.56#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.224.08:25:29.61#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.224.08:25:29.61#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.224.08:25:29.61#ibcon#enter wrdev, iclass 20, count 2 2006.224.08:25:29.61#ibcon#first serial, iclass 20, count 2 2006.224.08:25:29.61#ibcon#enter sib2, iclass 20, count 2 2006.224.08:25:29.61#ibcon#flushed, iclass 20, count 2 2006.224.08:25:29.61#ibcon#about to write, iclass 20, count 2 2006.224.08:25:29.61#ibcon#wrote, iclass 20, count 2 2006.224.08:25:29.61#ibcon#about to read 3, iclass 20, count 2 2006.224.08:25:29.63#ibcon#read 3, iclass 20, count 2 2006.224.08:25:29.63#ibcon#about to read 4, iclass 20, count 2 2006.224.08:25:29.63#ibcon#read 4, iclass 20, count 2 2006.224.08:25:29.63#ibcon#about to read 5, iclass 20, count 2 2006.224.08:25:29.63#ibcon#read 5, iclass 20, count 2 2006.224.08:25:29.63#ibcon#about to read 6, iclass 20, count 2 2006.224.08:25:29.63#ibcon#read 6, iclass 20, count 2 2006.224.08:25:29.63#ibcon#end of sib2, iclass 20, count 2 2006.224.08:25:29.63#ibcon#*mode == 0, iclass 20, count 2 2006.224.08:25:29.63#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.224.08:25:29.63#ibcon#[25=AT06-06\r\n] 2006.224.08:25:29.63#ibcon#*before write, iclass 20, count 2 2006.224.08:25:29.63#ibcon#enter sib2, iclass 20, count 2 2006.224.08:25:29.63#ibcon#flushed, iclass 20, count 2 2006.224.08:25:29.63#ibcon#about to write, iclass 20, count 2 2006.224.08:25:29.63#ibcon#wrote, iclass 20, count 2 2006.224.08:25:29.63#ibcon#about to read 3, iclass 20, count 2 2006.224.08:25:29.66#ibcon#read 3, iclass 20, count 2 2006.224.08:25:29.66#ibcon#about to read 4, iclass 20, count 2 2006.224.08:25:29.66#ibcon#read 4, iclass 20, count 2 2006.224.08:25:29.66#ibcon#about to read 5, iclass 20, count 2 2006.224.08:25:29.66#ibcon#read 5, iclass 20, count 2 2006.224.08:25:29.66#ibcon#about to read 6, iclass 20, count 2 2006.224.08:25:29.66#ibcon#read 6, iclass 20, count 2 2006.224.08:25:29.66#ibcon#end of sib2, iclass 20, count 2 2006.224.08:25:29.66#ibcon#*after write, iclass 20, count 2 2006.224.08:25:29.66#ibcon#*before return 0, iclass 20, count 2 2006.224.08:25:29.66#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.224.08:25:29.66#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.224.08:25:29.66#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.224.08:25:29.66#ibcon#ireg 7 cls_cnt 0 2006.224.08:25:29.66#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.224.08:25:29.78#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.224.08:25:29.78#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.224.08:25:29.78#ibcon#enter wrdev, iclass 20, count 0 2006.224.08:25:29.78#ibcon#first serial, iclass 20, count 0 2006.224.08:25:29.78#ibcon#enter sib2, iclass 20, count 0 2006.224.08:25:29.78#ibcon#flushed, iclass 20, count 0 2006.224.08:25:29.78#ibcon#about to write, iclass 20, count 0 2006.224.08:25:29.78#ibcon#wrote, iclass 20, count 0 2006.224.08:25:29.78#ibcon#about to read 3, iclass 20, count 0 2006.224.08:25:29.80#ibcon#read 3, iclass 20, count 0 2006.224.08:25:29.80#ibcon#about to read 4, iclass 20, count 0 2006.224.08:25:29.80#ibcon#read 4, iclass 20, count 0 2006.224.08:25:29.80#ibcon#about to read 5, iclass 20, count 0 2006.224.08:25:29.80#ibcon#read 5, iclass 20, count 0 2006.224.08:25:29.80#ibcon#about to read 6, iclass 20, count 0 2006.224.08:25:29.80#ibcon#read 6, iclass 20, count 0 2006.224.08:25:29.80#ibcon#end of sib2, iclass 20, count 0 2006.224.08:25:29.80#ibcon#*mode == 0, iclass 20, count 0 2006.224.08:25:29.80#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.224.08:25:29.80#ibcon#[25=USB\r\n] 2006.224.08:25:29.80#ibcon#*before write, iclass 20, count 0 2006.224.08:25:29.80#ibcon#enter sib2, iclass 20, count 0 2006.224.08:25:29.80#ibcon#flushed, iclass 20, count 0 2006.224.08:25:29.80#ibcon#about to write, iclass 20, count 0 2006.224.08:25:29.80#ibcon#wrote, iclass 20, count 0 2006.224.08:25:29.80#ibcon#about to read 3, iclass 20, count 0 2006.224.08:25:29.83#ibcon#read 3, iclass 20, count 0 2006.224.08:25:29.83#ibcon#about to read 4, iclass 20, count 0 2006.224.08:25:29.83#ibcon#read 4, iclass 20, count 0 2006.224.08:25:29.83#ibcon#about to read 5, iclass 20, count 0 2006.224.08:25:29.83#ibcon#read 5, iclass 20, count 0 2006.224.08:25:29.83#ibcon#about to read 6, iclass 20, count 0 2006.224.08:25:29.83#ibcon#read 6, iclass 20, count 0 2006.224.08:25:29.83#ibcon#end of sib2, iclass 20, count 0 2006.224.08:25:29.83#ibcon#*after write, iclass 20, count 0 2006.224.08:25:29.83#ibcon#*before return 0, iclass 20, count 0 2006.224.08:25:29.83#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.224.08:25:29.83#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.224.08:25:29.83#ibcon#about to clear, iclass 20 cls_cnt 0 2006.224.08:25:29.83#ibcon#cleared, iclass 20 cls_cnt 0 2006.224.08:25:29.83$vc4f8/valo=7,832.99 2006.224.08:25:29.83#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.224.08:25:29.83#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.224.08:25:29.83#ibcon#ireg 17 cls_cnt 0 2006.224.08:25:29.83#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.224.08:25:29.83#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.224.08:25:29.83#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.224.08:25:29.83#ibcon#enter wrdev, iclass 22, count 0 2006.224.08:25:29.83#ibcon#first serial, iclass 22, count 0 2006.224.08:25:29.83#ibcon#enter sib2, iclass 22, count 0 2006.224.08:25:29.83#ibcon#flushed, iclass 22, count 0 2006.224.08:25:29.83#ibcon#about to write, iclass 22, count 0 2006.224.08:25:29.83#ibcon#wrote, iclass 22, count 0 2006.224.08:25:29.83#ibcon#about to read 3, iclass 22, count 0 2006.224.08:25:29.85#ibcon#read 3, iclass 22, count 0 2006.224.08:25:29.85#ibcon#about to read 4, iclass 22, count 0 2006.224.08:25:29.85#ibcon#read 4, iclass 22, count 0 2006.224.08:25:29.85#ibcon#about to read 5, iclass 22, count 0 2006.224.08:25:29.85#ibcon#read 5, iclass 22, count 0 2006.224.08:25:29.85#ibcon#about to read 6, iclass 22, count 0 2006.224.08:25:29.85#ibcon#read 6, iclass 22, count 0 2006.224.08:25:29.85#ibcon#end of sib2, iclass 22, count 0 2006.224.08:25:29.85#ibcon#*mode == 0, iclass 22, count 0 2006.224.08:25:29.85#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.224.08:25:29.85#ibcon#[26=FRQ=07,832.99\r\n] 2006.224.08:25:29.85#ibcon#*before write, iclass 22, count 0 2006.224.08:25:29.85#ibcon#enter sib2, iclass 22, count 0 2006.224.08:25:29.85#ibcon#flushed, iclass 22, count 0 2006.224.08:25:29.85#ibcon#about to write, iclass 22, count 0 2006.224.08:25:29.85#ibcon#wrote, iclass 22, count 0 2006.224.08:25:29.85#ibcon#about to read 3, iclass 22, count 0 2006.224.08:25:29.89#ibcon#read 3, iclass 22, count 0 2006.224.08:25:29.89#ibcon#about to read 4, iclass 22, count 0 2006.224.08:25:29.89#ibcon#read 4, iclass 22, count 0 2006.224.08:25:29.89#ibcon#about to read 5, iclass 22, count 0 2006.224.08:25:29.89#ibcon#read 5, iclass 22, count 0 2006.224.08:25:29.89#ibcon#about to read 6, iclass 22, count 0 2006.224.08:25:29.89#ibcon#read 6, iclass 22, count 0 2006.224.08:25:29.89#ibcon#end of sib2, iclass 22, count 0 2006.224.08:25:29.89#ibcon#*after write, iclass 22, count 0 2006.224.08:25:29.89#ibcon#*before return 0, iclass 22, count 0 2006.224.08:25:29.89#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.224.08:25:29.89#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.224.08:25:29.89#ibcon#about to clear, iclass 22 cls_cnt 0 2006.224.08:25:29.89#ibcon#cleared, iclass 22 cls_cnt 0 2006.224.08:25:29.89$vc4f8/va=7,6 2006.224.08:25:29.89#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.224.08:25:29.89#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.224.08:25:29.89#ibcon#ireg 11 cls_cnt 2 2006.224.08:25:29.89#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.224.08:25:29.95#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.224.08:25:29.95#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.224.08:25:29.95#ibcon#enter wrdev, iclass 24, count 2 2006.224.08:25:29.95#ibcon#first serial, iclass 24, count 2 2006.224.08:25:29.95#ibcon#enter sib2, iclass 24, count 2 2006.224.08:25:29.95#ibcon#flushed, iclass 24, count 2 2006.224.08:25:29.95#ibcon#about to write, iclass 24, count 2 2006.224.08:25:29.95#ibcon#wrote, iclass 24, count 2 2006.224.08:25:29.95#ibcon#about to read 3, iclass 24, count 2 2006.224.08:25:29.97#ibcon#read 3, iclass 24, count 2 2006.224.08:25:29.97#ibcon#about to read 4, iclass 24, count 2 2006.224.08:25:29.97#ibcon#read 4, iclass 24, count 2 2006.224.08:25:29.97#ibcon#about to read 5, iclass 24, count 2 2006.224.08:25:29.97#ibcon#read 5, iclass 24, count 2 2006.224.08:25:29.97#ibcon#about to read 6, iclass 24, count 2 2006.224.08:25:29.97#ibcon#read 6, iclass 24, count 2 2006.224.08:25:29.97#ibcon#end of sib2, iclass 24, count 2 2006.224.08:25:29.97#ibcon#*mode == 0, iclass 24, count 2 2006.224.08:25:29.97#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.224.08:25:29.97#ibcon#[25=AT07-06\r\n] 2006.224.08:25:29.97#ibcon#*before write, iclass 24, count 2 2006.224.08:25:29.97#ibcon#enter sib2, iclass 24, count 2 2006.224.08:25:29.97#ibcon#flushed, iclass 24, count 2 2006.224.08:25:29.97#ibcon#about to write, iclass 24, count 2 2006.224.08:25:29.97#ibcon#wrote, iclass 24, count 2 2006.224.08:25:29.97#ibcon#about to read 3, iclass 24, count 2 2006.224.08:25:30.00#ibcon#read 3, iclass 24, count 2 2006.224.08:25:30.00#ibcon#about to read 4, iclass 24, count 2 2006.224.08:25:30.00#ibcon#read 4, iclass 24, count 2 2006.224.08:25:30.00#ibcon#about to read 5, iclass 24, count 2 2006.224.08:25:30.00#ibcon#read 5, iclass 24, count 2 2006.224.08:25:30.00#ibcon#about to read 6, iclass 24, count 2 2006.224.08:25:30.00#ibcon#read 6, iclass 24, count 2 2006.224.08:25:30.00#ibcon#end of sib2, iclass 24, count 2 2006.224.08:25:30.00#ibcon#*after write, iclass 24, count 2 2006.224.08:25:30.00#ibcon#*before return 0, iclass 24, count 2 2006.224.08:25:30.00#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.224.08:25:30.00#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.224.08:25:30.00#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.224.08:25:30.00#ibcon#ireg 7 cls_cnt 0 2006.224.08:25:30.00#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.224.08:25:30.12#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.224.08:25:30.12#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.224.08:25:30.12#ibcon#enter wrdev, iclass 24, count 0 2006.224.08:25:30.12#ibcon#first serial, iclass 24, count 0 2006.224.08:25:30.12#ibcon#enter sib2, iclass 24, count 0 2006.224.08:25:30.12#ibcon#flushed, iclass 24, count 0 2006.224.08:25:30.12#ibcon#about to write, iclass 24, count 0 2006.224.08:25:30.12#ibcon#wrote, iclass 24, count 0 2006.224.08:25:30.12#ibcon#about to read 3, iclass 24, count 0 2006.224.08:25:30.14#ibcon#read 3, iclass 24, count 0 2006.224.08:25:30.14#ibcon#about to read 4, iclass 24, count 0 2006.224.08:25:30.14#ibcon#read 4, iclass 24, count 0 2006.224.08:25:30.14#ibcon#about to read 5, iclass 24, count 0 2006.224.08:25:30.14#ibcon#read 5, iclass 24, count 0 2006.224.08:25:30.14#ibcon#about to read 6, iclass 24, count 0 2006.224.08:25:30.14#ibcon#read 6, iclass 24, count 0 2006.224.08:25:30.14#ibcon#end of sib2, iclass 24, count 0 2006.224.08:25:30.14#ibcon#*mode == 0, iclass 24, count 0 2006.224.08:25:30.14#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.224.08:25:30.14#ibcon#[25=USB\r\n] 2006.224.08:25:30.14#ibcon#*before write, iclass 24, count 0 2006.224.08:25:30.14#ibcon#enter sib2, iclass 24, count 0 2006.224.08:25:30.14#ibcon#flushed, iclass 24, count 0 2006.224.08:25:30.14#ibcon#about to write, iclass 24, count 0 2006.224.08:25:30.14#ibcon#wrote, iclass 24, count 0 2006.224.08:25:30.14#ibcon#about to read 3, iclass 24, count 0 2006.224.08:25:30.17#ibcon#read 3, iclass 24, count 0 2006.224.08:25:30.17#ibcon#about to read 4, iclass 24, count 0 2006.224.08:25:30.17#ibcon#read 4, iclass 24, count 0 2006.224.08:25:30.17#ibcon#about to read 5, iclass 24, count 0 2006.224.08:25:30.17#ibcon#read 5, iclass 24, count 0 2006.224.08:25:30.17#ibcon#about to read 6, iclass 24, count 0 2006.224.08:25:30.17#ibcon#read 6, iclass 24, count 0 2006.224.08:25:30.17#ibcon#end of sib2, iclass 24, count 0 2006.224.08:25:30.17#ibcon#*after write, iclass 24, count 0 2006.224.08:25:30.17#ibcon#*before return 0, iclass 24, count 0 2006.224.08:25:30.17#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.224.08:25:30.17#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.224.08:25:30.17#ibcon#about to clear, iclass 24 cls_cnt 0 2006.224.08:25:30.17#ibcon#cleared, iclass 24 cls_cnt 0 2006.224.08:25:30.17$vc4f8/valo=8,852.99 2006.224.08:25:30.17#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.224.08:25:30.17#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.224.08:25:30.17#ibcon#ireg 17 cls_cnt 0 2006.224.08:25:30.17#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.224.08:25:30.17#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.224.08:25:30.17#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.224.08:25:30.17#ibcon#enter wrdev, iclass 26, count 0 2006.224.08:25:30.17#ibcon#first serial, iclass 26, count 0 2006.224.08:25:30.17#ibcon#enter sib2, iclass 26, count 0 2006.224.08:25:30.17#ibcon#flushed, iclass 26, count 0 2006.224.08:25:30.17#ibcon#about to write, iclass 26, count 0 2006.224.08:25:30.17#ibcon#wrote, iclass 26, count 0 2006.224.08:25:30.17#ibcon#about to read 3, iclass 26, count 0 2006.224.08:25:30.19#ibcon#read 3, iclass 26, count 0 2006.224.08:25:30.19#ibcon#about to read 4, iclass 26, count 0 2006.224.08:25:30.19#ibcon#read 4, iclass 26, count 0 2006.224.08:25:30.19#ibcon#about to read 5, iclass 26, count 0 2006.224.08:25:30.19#ibcon#read 5, iclass 26, count 0 2006.224.08:25:30.19#ibcon#about to read 6, iclass 26, count 0 2006.224.08:25:30.19#ibcon#read 6, iclass 26, count 0 2006.224.08:25:30.19#ibcon#end of sib2, iclass 26, count 0 2006.224.08:25:30.19#ibcon#*mode == 0, iclass 26, count 0 2006.224.08:25:30.19#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.224.08:25:30.19#ibcon#[26=FRQ=08,852.99\r\n] 2006.224.08:25:30.19#ibcon#*before write, iclass 26, count 0 2006.224.08:25:30.19#ibcon#enter sib2, iclass 26, count 0 2006.224.08:25:30.19#ibcon#flushed, iclass 26, count 0 2006.224.08:25:30.19#ibcon#about to write, iclass 26, count 0 2006.224.08:25:30.19#ibcon#wrote, iclass 26, count 0 2006.224.08:25:30.19#ibcon#about to read 3, iclass 26, count 0 2006.224.08:25:30.23#ibcon#read 3, iclass 26, count 0 2006.224.08:25:30.23#ibcon#about to read 4, iclass 26, count 0 2006.224.08:25:30.23#ibcon#read 4, iclass 26, count 0 2006.224.08:25:30.23#ibcon#about to read 5, iclass 26, count 0 2006.224.08:25:30.23#ibcon#read 5, iclass 26, count 0 2006.224.08:25:30.23#ibcon#about to read 6, iclass 26, count 0 2006.224.08:25:30.23#ibcon#read 6, iclass 26, count 0 2006.224.08:25:30.23#ibcon#end of sib2, iclass 26, count 0 2006.224.08:25:30.23#ibcon#*after write, iclass 26, count 0 2006.224.08:25:30.23#ibcon#*before return 0, iclass 26, count 0 2006.224.08:25:30.23#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.224.08:25:30.23#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.224.08:25:30.23#ibcon#about to clear, iclass 26 cls_cnt 0 2006.224.08:25:30.23#ibcon#cleared, iclass 26 cls_cnt 0 2006.224.08:25:30.23$vc4f8/va=8,7 2006.224.08:25:30.23#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.224.08:25:30.23#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.224.08:25:30.23#ibcon#ireg 11 cls_cnt 2 2006.224.08:25:30.23#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.224.08:25:30.29#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.224.08:25:30.29#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.224.08:25:30.29#ibcon#enter wrdev, iclass 28, count 2 2006.224.08:25:30.29#ibcon#first serial, iclass 28, count 2 2006.224.08:25:30.29#ibcon#enter sib2, iclass 28, count 2 2006.224.08:25:30.29#ibcon#flushed, iclass 28, count 2 2006.224.08:25:30.29#ibcon#about to write, iclass 28, count 2 2006.224.08:25:30.29#ibcon#wrote, iclass 28, count 2 2006.224.08:25:30.29#ibcon#about to read 3, iclass 28, count 2 2006.224.08:25:30.31#ibcon#read 3, iclass 28, count 2 2006.224.08:25:30.31#ibcon#about to read 4, iclass 28, count 2 2006.224.08:25:30.31#ibcon#read 4, iclass 28, count 2 2006.224.08:25:30.31#ibcon#about to read 5, iclass 28, count 2 2006.224.08:25:30.31#ibcon#read 5, iclass 28, count 2 2006.224.08:25:30.31#ibcon#about to read 6, iclass 28, count 2 2006.224.08:25:30.31#ibcon#read 6, iclass 28, count 2 2006.224.08:25:30.31#ibcon#end of sib2, iclass 28, count 2 2006.224.08:25:30.31#ibcon#*mode == 0, iclass 28, count 2 2006.224.08:25:30.31#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.224.08:25:30.31#ibcon#[25=AT08-07\r\n] 2006.224.08:25:30.31#ibcon#*before write, iclass 28, count 2 2006.224.08:25:30.31#ibcon#enter sib2, iclass 28, count 2 2006.224.08:25:30.31#ibcon#flushed, iclass 28, count 2 2006.224.08:25:30.31#ibcon#about to write, iclass 28, count 2 2006.224.08:25:30.31#ibcon#wrote, iclass 28, count 2 2006.224.08:25:30.31#ibcon#about to read 3, iclass 28, count 2 2006.224.08:25:30.34#ibcon#read 3, iclass 28, count 2 2006.224.08:25:30.34#ibcon#about to read 4, iclass 28, count 2 2006.224.08:25:30.34#ibcon#read 4, iclass 28, count 2 2006.224.08:25:30.34#ibcon#about to read 5, iclass 28, count 2 2006.224.08:25:30.34#ibcon#read 5, iclass 28, count 2 2006.224.08:25:30.34#ibcon#about to read 6, iclass 28, count 2 2006.224.08:25:30.34#ibcon#read 6, iclass 28, count 2 2006.224.08:25:30.34#ibcon#end of sib2, iclass 28, count 2 2006.224.08:25:30.34#ibcon#*after write, iclass 28, count 2 2006.224.08:25:30.34#ibcon#*before return 0, iclass 28, count 2 2006.224.08:25:30.34#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.224.08:25:30.34#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.224.08:25:30.34#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.224.08:25:30.34#ibcon#ireg 7 cls_cnt 0 2006.224.08:25:30.34#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.224.08:25:30.46#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.224.08:25:30.46#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.224.08:25:30.46#ibcon#enter wrdev, iclass 28, count 0 2006.224.08:25:30.46#ibcon#first serial, iclass 28, count 0 2006.224.08:25:30.46#ibcon#enter sib2, iclass 28, count 0 2006.224.08:25:30.46#ibcon#flushed, iclass 28, count 0 2006.224.08:25:30.46#ibcon#about to write, iclass 28, count 0 2006.224.08:25:30.46#ibcon#wrote, iclass 28, count 0 2006.224.08:25:30.46#ibcon#about to read 3, iclass 28, count 0 2006.224.08:25:30.48#ibcon#read 3, iclass 28, count 0 2006.224.08:25:30.48#ibcon#about to read 4, iclass 28, count 0 2006.224.08:25:30.48#ibcon#read 4, iclass 28, count 0 2006.224.08:25:30.48#ibcon#about to read 5, iclass 28, count 0 2006.224.08:25:30.48#ibcon#read 5, iclass 28, count 0 2006.224.08:25:30.48#ibcon#about to read 6, iclass 28, count 0 2006.224.08:25:30.48#ibcon#read 6, iclass 28, count 0 2006.224.08:25:30.48#ibcon#end of sib2, iclass 28, count 0 2006.224.08:25:30.48#ibcon#*mode == 0, iclass 28, count 0 2006.224.08:25:30.48#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.224.08:25:30.48#ibcon#[25=USB\r\n] 2006.224.08:25:30.48#ibcon#*before write, iclass 28, count 0 2006.224.08:25:30.48#ibcon#enter sib2, iclass 28, count 0 2006.224.08:25:30.48#ibcon#flushed, iclass 28, count 0 2006.224.08:25:30.48#ibcon#about to write, iclass 28, count 0 2006.224.08:25:30.48#ibcon#wrote, iclass 28, count 0 2006.224.08:25:30.48#ibcon#about to read 3, iclass 28, count 0 2006.224.08:25:30.51#ibcon#read 3, iclass 28, count 0 2006.224.08:25:30.51#ibcon#about to read 4, iclass 28, count 0 2006.224.08:25:30.51#ibcon#read 4, iclass 28, count 0 2006.224.08:25:30.51#ibcon#about to read 5, iclass 28, count 0 2006.224.08:25:30.51#ibcon#read 5, iclass 28, count 0 2006.224.08:25:30.51#ibcon#about to read 6, iclass 28, count 0 2006.224.08:25:30.51#ibcon#read 6, iclass 28, count 0 2006.224.08:25:30.51#ibcon#end of sib2, iclass 28, count 0 2006.224.08:25:30.51#ibcon#*after write, iclass 28, count 0 2006.224.08:25:30.51#ibcon#*before return 0, iclass 28, count 0 2006.224.08:25:30.51#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.224.08:25:30.51#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.224.08:25:30.51#ibcon#about to clear, iclass 28 cls_cnt 0 2006.224.08:25:30.51#ibcon#cleared, iclass 28 cls_cnt 0 2006.224.08:25:30.51$vc4f8/vblo=1,632.99 2006.224.08:25:30.51#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.224.08:25:30.51#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.224.08:25:30.51#ibcon#ireg 17 cls_cnt 0 2006.224.08:25:30.51#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.224.08:25:30.51#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.224.08:25:30.51#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.224.08:25:30.51#ibcon#enter wrdev, iclass 30, count 0 2006.224.08:25:30.51#ibcon#first serial, iclass 30, count 0 2006.224.08:25:30.51#ibcon#enter sib2, iclass 30, count 0 2006.224.08:25:30.51#ibcon#flushed, iclass 30, count 0 2006.224.08:25:30.51#ibcon#about to write, iclass 30, count 0 2006.224.08:25:30.51#ibcon#wrote, iclass 30, count 0 2006.224.08:25:30.51#ibcon#about to read 3, iclass 30, count 0 2006.224.08:25:30.54#ibcon#read 3, iclass 30, count 0 2006.224.08:25:30.54#ibcon#about to read 4, iclass 30, count 0 2006.224.08:25:30.54#ibcon#read 4, iclass 30, count 0 2006.224.08:25:30.54#ibcon#about to read 5, iclass 30, count 0 2006.224.08:25:30.54#ibcon#read 5, iclass 30, count 0 2006.224.08:25:30.54#ibcon#about to read 6, iclass 30, count 0 2006.224.08:25:30.54#ibcon#read 6, iclass 30, count 0 2006.224.08:25:30.54#ibcon#end of sib2, iclass 30, count 0 2006.224.08:25:30.54#ibcon#*mode == 0, iclass 30, count 0 2006.224.08:25:30.54#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.224.08:25:30.54#ibcon#[28=FRQ=01,632.99\r\n] 2006.224.08:25:30.54#ibcon#*before write, iclass 30, count 0 2006.224.08:25:30.54#ibcon#enter sib2, iclass 30, count 0 2006.224.08:25:30.54#ibcon#flushed, iclass 30, count 0 2006.224.08:25:30.54#ibcon#about to write, iclass 30, count 0 2006.224.08:25:30.54#ibcon#wrote, iclass 30, count 0 2006.224.08:25:30.54#ibcon#about to read 3, iclass 30, count 0 2006.224.08:25:30.58#ibcon#read 3, iclass 30, count 0 2006.224.08:25:30.58#ibcon#about to read 4, iclass 30, count 0 2006.224.08:25:30.58#ibcon#read 4, iclass 30, count 0 2006.224.08:25:30.58#ibcon#about to read 5, iclass 30, count 0 2006.224.08:25:30.58#ibcon#read 5, iclass 30, count 0 2006.224.08:25:30.58#ibcon#about to read 6, iclass 30, count 0 2006.224.08:25:30.58#ibcon#read 6, iclass 30, count 0 2006.224.08:25:30.58#ibcon#end of sib2, iclass 30, count 0 2006.224.08:25:30.58#ibcon#*after write, iclass 30, count 0 2006.224.08:25:30.58#ibcon#*before return 0, iclass 30, count 0 2006.224.08:25:30.58#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.224.08:25:30.58#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.224.08:25:30.58#ibcon#about to clear, iclass 30 cls_cnt 0 2006.224.08:25:30.58#ibcon#cleared, iclass 30 cls_cnt 0 2006.224.08:25:30.58$vc4f8/vb=1,4 2006.224.08:25:30.58#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.224.08:25:30.58#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.224.08:25:30.58#ibcon#ireg 11 cls_cnt 2 2006.224.08:25:30.58#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.224.08:25:30.58#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.224.08:25:30.58#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.224.08:25:30.58#ibcon#enter wrdev, iclass 32, count 2 2006.224.08:25:30.58#ibcon#first serial, iclass 32, count 2 2006.224.08:25:30.58#ibcon#enter sib2, iclass 32, count 2 2006.224.08:25:30.58#ibcon#flushed, iclass 32, count 2 2006.224.08:25:30.58#ibcon#about to write, iclass 32, count 2 2006.224.08:25:30.58#ibcon#wrote, iclass 32, count 2 2006.224.08:25:30.58#ibcon#about to read 3, iclass 32, count 2 2006.224.08:25:30.60#ibcon#read 3, iclass 32, count 2 2006.224.08:25:30.60#ibcon#about to read 4, iclass 32, count 2 2006.224.08:25:30.60#ibcon#read 4, iclass 32, count 2 2006.224.08:25:30.60#ibcon#about to read 5, iclass 32, count 2 2006.224.08:25:30.60#ibcon#read 5, iclass 32, count 2 2006.224.08:25:30.60#ibcon#about to read 6, iclass 32, count 2 2006.224.08:25:30.60#ibcon#read 6, iclass 32, count 2 2006.224.08:25:30.60#ibcon#end of sib2, iclass 32, count 2 2006.224.08:25:30.60#ibcon#*mode == 0, iclass 32, count 2 2006.224.08:25:30.60#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.224.08:25:30.60#ibcon#[27=AT01-04\r\n] 2006.224.08:25:30.60#ibcon#*before write, iclass 32, count 2 2006.224.08:25:30.60#ibcon#enter sib2, iclass 32, count 2 2006.224.08:25:30.60#ibcon#flushed, iclass 32, count 2 2006.224.08:25:30.60#ibcon#about to write, iclass 32, count 2 2006.224.08:25:30.60#ibcon#wrote, iclass 32, count 2 2006.224.08:25:30.60#ibcon#about to read 3, iclass 32, count 2 2006.224.08:25:30.63#ibcon#read 3, iclass 32, count 2 2006.224.08:25:30.63#ibcon#about to read 4, iclass 32, count 2 2006.224.08:25:30.63#ibcon#read 4, iclass 32, count 2 2006.224.08:25:30.63#ibcon#about to read 5, iclass 32, count 2 2006.224.08:25:30.63#ibcon#read 5, iclass 32, count 2 2006.224.08:25:30.63#ibcon#about to read 6, iclass 32, count 2 2006.224.08:25:30.63#ibcon#read 6, iclass 32, count 2 2006.224.08:25:30.63#ibcon#end of sib2, iclass 32, count 2 2006.224.08:25:30.63#ibcon#*after write, iclass 32, count 2 2006.224.08:25:30.63#ibcon#*before return 0, iclass 32, count 2 2006.224.08:25:30.63#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.224.08:25:30.63#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.224.08:25:30.63#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.224.08:25:30.63#ibcon#ireg 7 cls_cnt 0 2006.224.08:25:30.63#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.224.08:25:30.75#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.224.08:25:30.75#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.224.08:25:30.75#ibcon#enter wrdev, iclass 32, count 0 2006.224.08:25:30.75#ibcon#first serial, iclass 32, count 0 2006.224.08:25:30.75#ibcon#enter sib2, iclass 32, count 0 2006.224.08:25:30.75#ibcon#flushed, iclass 32, count 0 2006.224.08:25:30.75#ibcon#about to write, iclass 32, count 0 2006.224.08:25:30.75#ibcon#wrote, iclass 32, count 0 2006.224.08:25:30.75#ibcon#about to read 3, iclass 32, count 0 2006.224.08:25:30.77#ibcon#read 3, iclass 32, count 0 2006.224.08:25:30.77#ibcon#about to read 4, iclass 32, count 0 2006.224.08:25:30.77#ibcon#read 4, iclass 32, count 0 2006.224.08:25:30.77#ibcon#about to read 5, iclass 32, count 0 2006.224.08:25:30.77#ibcon#read 5, iclass 32, count 0 2006.224.08:25:30.77#ibcon#about to read 6, iclass 32, count 0 2006.224.08:25:30.77#ibcon#read 6, iclass 32, count 0 2006.224.08:25:30.77#ibcon#end of sib2, iclass 32, count 0 2006.224.08:25:30.77#ibcon#*mode == 0, iclass 32, count 0 2006.224.08:25:30.77#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.224.08:25:30.77#ibcon#[27=USB\r\n] 2006.224.08:25:30.77#ibcon#*before write, iclass 32, count 0 2006.224.08:25:30.77#ibcon#enter sib2, iclass 32, count 0 2006.224.08:25:30.77#ibcon#flushed, iclass 32, count 0 2006.224.08:25:30.77#ibcon#about to write, iclass 32, count 0 2006.224.08:25:30.77#ibcon#wrote, iclass 32, count 0 2006.224.08:25:30.77#ibcon#about to read 3, iclass 32, count 0 2006.224.08:25:30.80#ibcon#read 3, iclass 32, count 0 2006.224.08:25:30.80#ibcon#about to read 4, iclass 32, count 0 2006.224.08:25:30.80#ibcon#read 4, iclass 32, count 0 2006.224.08:25:30.80#ibcon#about to read 5, iclass 32, count 0 2006.224.08:25:30.80#ibcon#read 5, iclass 32, count 0 2006.224.08:25:30.80#ibcon#about to read 6, iclass 32, count 0 2006.224.08:25:30.80#ibcon#read 6, iclass 32, count 0 2006.224.08:25:30.80#ibcon#end of sib2, iclass 32, count 0 2006.224.08:25:30.80#ibcon#*after write, iclass 32, count 0 2006.224.08:25:30.80#ibcon#*before return 0, iclass 32, count 0 2006.224.08:25:30.80#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.224.08:25:30.80#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.224.08:25:30.80#ibcon#about to clear, iclass 32 cls_cnt 0 2006.224.08:25:30.80#ibcon#cleared, iclass 32 cls_cnt 0 2006.224.08:25:30.80$vc4f8/vblo=2,640.99 2006.224.08:25:30.80#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.224.08:25:30.80#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.224.08:25:30.80#ibcon#ireg 17 cls_cnt 0 2006.224.08:25:30.80#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.224.08:25:30.80#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.224.08:25:30.80#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.224.08:25:30.80#ibcon#enter wrdev, iclass 34, count 0 2006.224.08:25:30.80#ibcon#first serial, iclass 34, count 0 2006.224.08:25:30.80#ibcon#enter sib2, iclass 34, count 0 2006.224.08:25:30.80#ibcon#flushed, iclass 34, count 0 2006.224.08:25:30.80#ibcon#about to write, iclass 34, count 0 2006.224.08:25:30.80#ibcon#wrote, iclass 34, count 0 2006.224.08:25:30.80#ibcon#about to read 3, iclass 34, count 0 2006.224.08:25:30.82#ibcon#read 3, iclass 34, count 0 2006.224.08:25:30.82#ibcon#about to read 4, iclass 34, count 0 2006.224.08:25:30.82#ibcon#read 4, iclass 34, count 0 2006.224.08:25:30.82#ibcon#about to read 5, iclass 34, count 0 2006.224.08:25:30.82#ibcon#read 5, iclass 34, count 0 2006.224.08:25:30.82#ibcon#about to read 6, iclass 34, count 0 2006.224.08:25:30.82#ibcon#read 6, iclass 34, count 0 2006.224.08:25:30.82#ibcon#end of sib2, iclass 34, count 0 2006.224.08:25:30.82#ibcon#*mode == 0, iclass 34, count 0 2006.224.08:25:30.82#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.224.08:25:30.82#ibcon#[28=FRQ=02,640.99\r\n] 2006.224.08:25:30.82#ibcon#*before write, iclass 34, count 0 2006.224.08:25:30.82#ibcon#enter sib2, iclass 34, count 0 2006.224.08:25:30.82#ibcon#flushed, iclass 34, count 0 2006.224.08:25:30.82#ibcon#about to write, iclass 34, count 0 2006.224.08:25:30.82#ibcon#wrote, iclass 34, count 0 2006.224.08:25:30.82#ibcon#about to read 3, iclass 34, count 0 2006.224.08:25:30.86#ibcon#read 3, iclass 34, count 0 2006.224.08:25:30.86#ibcon#about to read 4, iclass 34, count 0 2006.224.08:25:30.86#ibcon#read 4, iclass 34, count 0 2006.224.08:25:30.86#ibcon#about to read 5, iclass 34, count 0 2006.224.08:25:30.86#ibcon#read 5, iclass 34, count 0 2006.224.08:25:30.86#ibcon#about to read 6, iclass 34, count 0 2006.224.08:25:30.86#ibcon#read 6, iclass 34, count 0 2006.224.08:25:30.86#ibcon#end of sib2, iclass 34, count 0 2006.224.08:25:30.86#ibcon#*after write, iclass 34, count 0 2006.224.08:25:30.86#ibcon#*before return 0, iclass 34, count 0 2006.224.08:25:30.86#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.224.08:25:30.86#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.224.08:25:30.86#ibcon#about to clear, iclass 34 cls_cnt 0 2006.224.08:25:30.86#ibcon#cleared, iclass 34 cls_cnt 0 2006.224.08:25:30.86$vc4f8/vb=2,4 2006.224.08:25:30.86#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.224.08:25:30.86#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.224.08:25:30.86#ibcon#ireg 11 cls_cnt 2 2006.224.08:25:30.86#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.224.08:25:30.92#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.224.08:25:30.92#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.224.08:25:30.92#ibcon#enter wrdev, iclass 36, count 2 2006.224.08:25:30.92#ibcon#first serial, iclass 36, count 2 2006.224.08:25:30.92#ibcon#enter sib2, iclass 36, count 2 2006.224.08:25:30.92#ibcon#flushed, iclass 36, count 2 2006.224.08:25:30.92#ibcon#about to write, iclass 36, count 2 2006.224.08:25:30.92#ibcon#wrote, iclass 36, count 2 2006.224.08:25:30.92#ibcon#about to read 3, iclass 36, count 2 2006.224.08:25:30.94#ibcon#read 3, iclass 36, count 2 2006.224.08:25:30.94#ibcon#about to read 4, iclass 36, count 2 2006.224.08:25:30.94#ibcon#read 4, iclass 36, count 2 2006.224.08:25:30.94#ibcon#about to read 5, iclass 36, count 2 2006.224.08:25:30.94#ibcon#read 5, iclass 36, count 2 2006.224.08:25:30.94#ibcon#about to read 6, iclass 36, count 2 2006.224.08:25:30.94#ibcon#read 6, iclass 36, count 2 2006.224.08:25:30.94#ibcon#end of sib2, iclass 36, count 2 2006.224.08:25:30.94#ibcon#*mode == 0, iclass 36, count 2 2006.224.08:25:30.94#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.224.08:25:30.94#ibcon#[27=AT02-04\r\n] 2006.224.08:25:30.94#ibcon#*before write, iclass 36, count 2 2006.224.08:25:30.94#ibcon#enter sib2, iclass 36, count 2 2006.224.08:25:30.94#ibcon#flushed, iclass 36, count 2 2006.224.08:25:30.94#ibcon#about to write, iclass 36, count 2 2006.224.08:25:30.94#ibcon#wrote, iclass 36, count 2 2006.224.08:25:30.94#ibcon#about to read 3, iclass 36, count 2 2006.224.08:25:30.97#ibcon#read 3, iclass 36, count 2 2006.224.08:25:30.97#ibcon#about to read 4, iclass 36, count 2 2006.224.08:25:30.97#ibcon#read 4, iclass 36, count 2 2006.224.08:25:30.97#ibcon#about to read 5, iclass 36, count 2 2006.224.08:25:30.97#ibcon#read 5, iclass 36, count 2 2006.224.08:25:30.97#ibcon#about to read 6, iclass 36, count 2 2006.224.08:25:30.97#ibcon#read 6, iclass 36, count 2 2006.224.08:25:30.97#ibcon#end of sib2, iclass 36, count 2 2006.224.08:25:30.97#ibcon#*after write, iclass 36, count 2 2006.224.08:25:30.97#ibcon#*before return 0, iclass 36, count 2 2006.224.08:25:30.97#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.224.08:25:30.97#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.224.08:25:30.97#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.224.08:25:30.97#ibcon#ireg 7 cls_cnt 0 2006.224.08:25:30.97#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.224.08:25:31.09#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.224.08:25:31.09#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.224.08:25:31.09#ibcon#enter wrdev, iclass 36, count 0 2006.224.08:25:31.09#ibcon#first serial, iclass 36, count 0 2006.224.08:25:31.09#ibcon#enter sib2, iclass 36, count 0 2006.224.08:25:31.09#ibcon#flushed, iclass 36, count 0 2006.224.08:25:31.09#ibcon#about to write, iclass 36, count 0 2006.224.08:25:31.09#ibcon#wrote, iclass 36, count 0 2006.224.08:25:31.09#ibcon#about to read 3, iclass 36, count 0 2006.224.08:25:31.11#ibcon#read 3, iclass 36, count 0 2006.224.08:25:31.11#ibcon#about to read 4, iclass 36, count 0 2006.224.08:25:31.11#ibcon#read 4, iclass 36, count 0 2006.224.08:25:31.11#ibcon#about to read 5, iclass 36, count 0 2006.224.08:25:31.11#ibcon#read 5, iclass 36, count 0 2006.224.08:25:31.11#ibcon#about to read 6, iclass 36, count 0 2006.224.08:25:31.11#ibcon#read 6, iclass 36, count 0 2006.224.08:25:31.11#ibcon#end of sib2, iclass 36, count 0 2006.224.08:25:31.11#ibcon#*mode == 0, iclass 36, count 0 2006.224.08:25:31.11#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.224.08:25:31.11#ibcon#[27=USB\r\n] 2006.224.08:25:31.11#ibcon#*before write, iclass 36, count 0 2006.224.08:25:31.11#ibcon#enter sib2, iclass 36, count 0 2006.224.08:25:31.11#ibcon#flushed, iclass 36, count 0 2006.224.08:25:31.11#ibcon#about to write, iclass 36, count 0 2006.224.08:25:31.11#ibcon#wrote, iclass 36, count 0 2006.224.08:25:31.11#ibcon#about to read 3, iclass 36, count 0 2006.224.08:25:31.14#ibcon#read 3, iclass 36, count 0 2006.224.08:25:31.14#ibcon#about to read 4, iclass 36, count 0 2006.224.08:25:31.14#ibcon#read 4, iclass 36, count 0 2006.224.08:25:31.14#ibcon#about to read 5, iclass 36, count 0 2006.224.08:25:31.14#ibcon#read 5, iclass 36, count 0 2006.224.08:25:31.14#ibcon#about to read 6, iclass 36, count 0 2006.224.08:25:31.14#ibcon#read 6, iclass 36, count 0 2006.224.08:25:31.14#ibcon#end of sib2, iclass 36, count 0 2006.224.08:25:31.14#ibcon#*after write, iclass 36, count 0 2006.224.08:25:31.14#ibcon#*before return 0, iclass 36, count 0 2006.224.08:25:31.14#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.224.08:25:31.14#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.224.08:25:31.14#ibcon#about to clear, iclass 36 cls_cnt 0 2006.224.08:25:31.14#ibcon#cleared, iclass 36 cls_cnt 0 2006.224.08:25:31.14$vc4f8/vblo=3,656.99 2006.224.08:25:31.14#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.224.08:25:31.14#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.224.08:25:31.14#ibcon#ireg 17 cls_cnt 0 2006.224.08:25:31.14#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.224.08:25:31.14#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.224.08:25:31.14#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.224.08:25:31.14#ibcon#enter wrdev, iclass 38, count 0 2006.224.08:25:31.14#ibcon#first serial, iclass 38, count 0 2006.224.08:25:31.14#ibcon#enter sib2, iclass 38, count 0 2006.224.08:25:31.14#ibcon#flushed, iclass 38, count 0 2006.224.08:25:31.14#ibcon#about to write, iclass 38, count 0 2006.224.08:25:31.14#ibcon#wrote, iclass 38, count 0 2006.224.08:25:31.14#ibcon#about to read 3, iclass 38, count 0 2006.224.08:25:31.16#ibcon#read 3, iclass 38, count 0 2006.224.08:25:31.16#ibcon#about to read 4, iclass 38, count 0 2006.224.08:25:31.16#ibcon#read 4, iclass 38, count 0 2006.224.08:25:31.16#ibcon#about to read 5, iclass 38, count 0 2006.224.08:25:31.16#ibcon#read 5, iclass 38, count 0 2006.224.08:25:31.16#ibcon#about to read 6, iclass 38, count 0 2006.224.08:25:31.16#ibcon#read 6, iclass 38, count 0 2006.224.08:25:31.16#ibcon#end of sib2, iclass 38, count 0 2006.224.08:25:31.16#ibcon#*mode == 0, iclass 38, count 0 2006.224.08:25:31.16#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.224.08:25:31.16#ibcon#[28=FRQ=03,656.99\r\n] 2006.224.08:25:31.16#ibcon#*before write, iclass 38, count 0 2006.224.08:25:31.16#ibcon#enter sib2, iclass 38, count 0 2006.224.08:25:31.16#ibcon#flushed, iclass 38, count 0 2006.224.08:25:31.16#ibcon#about to write, iclass 38, count 0 2006.224.08:25:31.16#ibcon#wrote, iclass 38, count 0 2006.224.08:25:31.16#ibcon#about to read 3, iclass 38, count 0 2006.224.08:25:31.20#ibcon#read 3, iclass 38, count 0 2006.224.08:25:31.20#ibcon#about to read 4, iclass 38, count 0 2006.224.08:25:31.20#ibcon#read 4, iclass 38, count 0 2006.224.08:25:31.20#ibcon#about to read 5, iclass 38, count 0 2006.224.08:25:31.20#ibcon#read 5, iclass 38, count 0 2006.224.08:25:31.20#ibcon#about to read 6, iclass 38, count 0 2006.224.08:25:31.20#ibcon#read 6, iclass 38, count 0 2006.224.08:25:31.20#ibcon#end of sib2, iclass 38, count 0 2006.224.08:25:31.20#ibcon#*after write, iclass 38, count 0 2006.224.08:25:31.20#ibcon#*before return 0, iclass 38, count 0 2006.224.08:25:31.20#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.224.08:25:31.20#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.224.08:25:31.20#ibcon#about to clear, iclass 38 cls_cnt 0 2006.224.08:25:31.20#ibcon#cleared, iclass 38 cls_cnt 0 2006.224.08:25:31.20$vc4f8/vb=3,4 2006.224.08:25:31.20#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.224.08:25:31.20#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.224.08:25:31.20#ibcon#ireg 11 cls_cnt 2 2006.224.08:25:31.20#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.224.08:25:31.26#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.224.08:25:31.26#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.224.08:25:31.26#ibcon#enter wrdev, iclass 40, count 2 2006.224.08:25:31.26#ibcon#first serial, iclass 40, count 2 2006.224.08:25:31.26#ibcon#enter sib2, iclass 40, count 2 2006.224.08:25:31.26#ibcon#flushed, iclass 40, count 2 2006.224.08:25:31.26#ibcon#about to write, iclass 40, count 2 2006.224.08:25:31.26#ibcon#wrote, iclass 40, count 2 2006.224.08:25:31.26#ibcon#about to read 3, iclass 40, count 2 2006.224.08:25:31.28#ibcon#read 3, iclass 40, count 2 2006.224.08:25:31.28#ibcon#about to read 4, iclass 40, count 2 2006.224.08:25:31.28#ibcon#read 4, iclass 40, count 2 2006.224.08:25:31.28#ibcon#about to read 5, iclass 40, count 2 2006.224.08:25:31.28#ibcon#read 5, iclass 40, count 2 2006.224.08:25:31.28#ibcon#about to read 6, iclass 40, count 2 2006.224.08:25:31.28#ibcon#read 6, iclass 40, count 2 2006.224.08:25:31.28#ibcon#end of sib2, iclass 40, count 2 2006.224.08:25:31.28#ibcon#*mode == 0, iclass 40, count 2 2006.224.08:25:31.28#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.224.08:25:31.28#ibcon#[27=AT03-04\r\n] 2006.224.08:25:31.28#ibcon#*before write, iclass 40, count 2 2006.224.08:25:31.28#ibcon#enter sib2, iclass 40, count 2 2006.224.08:25:31.28#ibcon#flushed, iclass 40, count 2 2006.224.08:25:31.28#ibcon#about to write, iclass 40, count 2 2006.224.08:25:31.28#ibcon#wrote, iclass 40, count 2 2006.224.08:25:31.28#ibcon#about to read 3, iclass 40, count 2 2006.224.08:25:31.31#ibcon#read 3, iclass 40, count 2 2006.224.08:25:31.31#ibcon#about to read 4, iclass 40, count 2 2006.224.08:25:31.31#ibcon#read 4, iclass 40, count 2 2006.224.08:25:31.31#ibcon#about to read 5, iclass 40, count 2 2006.224.08:25:31.31#ibcon#read 5, iclass 40, count 2 2006.224.08:25:31.31#ibcon#about to read 6, iclass 40, count 2 2006.224.08:25:31.31#ibcon#read 6, iclass 40, count 2 2006.224.08:25:31.31#ibcon#end of sib2, iclass 40, count 2 2006.224.08:25:31.31#ibcon#*after write, iclass 40, count 2 2006.224.08:25:31.31#ibcon#*before return 0, iclass 40, count 2 2006.224.08:25:31.31#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.224.08:25:31.31#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.224.08:25:31.31#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.224.08:25:31.31#ibcon#ireg 7 cls_cnt 0 2006.224.08:25:31.31#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.224.08:25:31.43#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.224.08:25:31.43#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.224.08:25:31.43#ibcon#enter wrdev, iclass 40, count 0 2006.224.08:25:31.43#ibcon#first serial, iclass 40, count 0 2006.224.08:25:31.43#ibcon#enter sib2, iclass 40, count 0 2006.224.08:25:31.43#ibcon#flushed, iclass 40, count 0 2006.224.08:25:31.43#ibcon#about to write, iclass 40, count 0 2006.224.08:25:31.43#ibcon#wrote, iclass 40, count 0 2006.224.08:25:31.43#ibcon#about to read 3, iclass 40, count 0 2006.224.08:25:31.45#ibcon#read 3, iclass 40, count 0 2006.224.08:25:31.45#ibcon#about to read 4, iclass 40, count 0 2006.224.08:25:31.45#ibcon#read 4, iclass 40, count 0 2006.224.08:25:31.45#ibcon#about to read 5, iclass 40, count 0 2006.224.08:25:31.45#ibcon#read 5, iclass 40, count 0 2006.224.08:25:31.45#ibcon#about to read 6, iclass 40, count 0 2006.224.08:25:31.45#ibcon#read 6, iclass 40, count 0 2006.224.08:25:31.45#ibcon#end of sib2, iclass 40, count 0 2006.224.08:25:31.45#ibcon#*mode == 0, iclass 40, count 0 2006.224.08:25:31.45#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.224.08:25:31.45#ibcon#[27=USB\r\n] 2006.224.08:25:31.45#ibcon#*before write, iclass 40, count 0 2006.224.08:25:31.45#ibcon#enter sib2, iclass 40, count 0 2006.224.08:25:31.45#ibcon#flushed, iclass 40, count 0 2006.224.08:25:31.45#ibcon#about to write, iclass 40, count 0 2006.224.08:25:31.45#ibcon#wrote, iclass 40, count 0 2006.224.08:25:31.45#ibcon#about to read 3, iclass 40, count 0 2006.224.08:25:31.48#ibcon#read 3, iclass 40, count 0 2006.224.08:25:31.48#ibcon#about to read 4, iclass 40, count 0 2006.224.08:25:31.48#ibcon#read 4, iclass 40, count 0 2006.224.08:25:31.48#ibcon#about to read 5, iclass 40, count 0 2006.224.08:25:31.48#ibcon#read 5, iclass 40, count 0 2006.224.08:25:31.48#ibcon#about to read 6, iclass 40, count 0 2006.224.08:25:31.48#ibcon#read 6, iclass 40, count 0 2006.224.08:25:31.48#ibcon#end of sib2, iclass 40, count 0 2006.224.08:25:31.48#ibcon#*after write, iclass 40, count 0 2006.224.08:25:31.48#ibcon#*before return 0, iclass 40, count 0 2006.224.08:25:31.48#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.224.08:25:31.48#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.224.08:25:31.48#ibcon#about to clear, iclass 40 cls_cnt 0 2006.224.08:25:31.48#ibcon#cleared, iclass 40 cls_cnt 0 2006.224.08:25:31.48$vc4f8/vblo=4,712.99 2006.224.08:25:31.48#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.224.08:25:31.48#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.224.08:25:31.48#ibcon#ireg 17 cls_cnt 0 2006.224.08:25:31.48#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.224.08:25:31.48#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.224.08:25:31.48#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.224.08:25:31.48#ibcon#enter wrdev, iclass 4, count 0 2006.224.08:25:31.48#ibcon#first serial, iclass 4, count 0 2006.224.08:25:31.48#ibcon#enter sib2, iclass 4, count 0 2006.224.08:25:31.48#ibcon#flushed, iclass 4, count 0 2006.224.08:25:31.48#ibcon#about to write, iclass 4, count 0 2006.224.08:25:31.48#ibcon#wrote, iclass 4, count 0 2006.224.08:25:31.48#ibcon#about to read 3, iclass 4, count 0 2006.224.08:25:31.50#ibcon#read 3, iclass 4, count 0 2006.224.08:25:31.50#ibcon#about to read 4, iclass 4, count 0 2006.224.08:25:31.50#ibcon#read 4, iclass 4, count 0 2006.224.08:25:31.50#ibcon#about to read 5, iclass 4, count 0 2006.224.08:25:31.50#ibcon#read 5, iclass 4, count 0 2006.224.08:25:31.50#ibcon#about to read 6, iclass 4, count 0 2006.224.08:25:31.50#ibcon#read 6, iclass 4, count 0 2006.224.08:25:31.50#ibcon#end of sib2, iclass 4, count 0 2006.224.08:25:31.50#ibcon#*mode == 0, iclass 4, count 0 2006.224.08:25:31.50#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.224.08:25:31.50#ibcon#[28=FRQ=04,712.99\r\n] 2006.224.08:25:31.50#ibcon#*before write, iclass 4, count 0 2006.224.08:25:31.50#ibcon#enter sib2, iclass 4, count 0 2006.224.08:25:31.50#ibcon#flushed, iclass 4, count 0 2006.224.08:25:31.50#ibcon#about to write, iclass 4, count 0 2006.224.08:25:31.50#ibcon#wrote, iclass 4, count 0 2006.224.08:25:31.50#ibcon#about to read 3, iclass 4, count 0 2006.224.08:25:31.54#ibcon#read 3, iclass 4, count 0 2006.224.08:25:31.54#ibcon#about to read 4, iclass 4, count 0 2006.224.08:25:31.54#ibcon#read 4, iclass 4, count 0 2006.224.08:25:31.54#ibcon#about to read 5, iclass 4, count 0 2006.224.08:25:31.54#ibcon#read 5, iclass 4, count 0 2006.224.08:25:31.54#ibcon#about to read 6, iclass 4, count 0 2006.224.08:25:31.54#ibcon#read 6, iclass 4, count 0 2006.224.08:25:31.54#ibcon#end of sib2, iclass 4, count 0 2006.224.08:25:31.54#ibcon#*after write, iclass 4, count 0 2006.224.08:25:31.54#ibcon#*before return 0, iclass 4, count 0 2006.224.08:25:31.54#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.224.08:25:31.54#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.224.08:25:31.54#ibcon#about to clear, iclass 4 cls_cnt 0 2006.224.08:25:31.54#ibcon#cleared, iclass 4 cls_cnt 0 2006.224.08:25:31.54$vc4f8/vb=4,4 2006.224.08:25:31.54#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.224.08:25:31.54#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.224.08:25:31.54#ibcon#ireg 11 cls_cnt 2 2006.224.08:25:31.54#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.224.08:25:31.60#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.224.08:25:31.60#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.224.08:25:31.60#ibcon#enter wrdev, iclass 6, count 2 2006.224.08:25:31.60#ibcon#first serial, iclass 6, count 2 2006.224.08:25:31.60#ibcon#enter sib2, iclass 6, count 2 2006.224.08:25:31.60#ibcon#flushed, iclass 6, count 2 2006.224.08:25:31.60#ibcon#about to write, iclass 6, count 2 2006.224.08:25:31.60#ibcon#wrote, iclass 6, count 2 2006.224.08:25:31.60#ibcon#about to read 3, iclass 6, count 2 2006.224.08:25:31.62#ibcon#read 3, iclass 6, count 2 2006.224.08:25:31.62#ibcon#about to read 4, iclass 6, count 2 2006.224.08:25:31.62#ibcon#read 4, iclass 6, count 2 2006.224.08:25:31.62#ibcon#about to read 5, iclass 6, count 2 2006.224.08:25:31.62#ibcon#read 5, iclass 6, count 2 2006.224.08:25:31.62#ibcon#about to read 6, iclass 6, count 2 2006.224.08:25:31.62#ibcon#read 6, iclass 6, count 2 2006.224.08:25:31.62#ibcon#end of sib2, iclass 6, count 2 2006.224.08:25:31.62#ibcon#*mode == 0, iclass 6, count 2 2006.224.08:25:31.62#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.224.08:25:31.62#ibcon#[27=AT04-04\r\n] 2006.224.08:25:31.62#ibcon#*before write, iclass 6, count 2 2006.224.08:25:31.62#ibcon#enter sib2, iclass 6, count 2 2006.224.08:25:31.62#ibcon#flushed, iclass 6, count 2 2006.224.08:25:31.62#ibcon#about to write, iclass 6, count 2 2006.224.08:25:31.62#ibcon#wrote, iclass 6, count 2 2006.224.08:25:31.62#ibcon#about to read 3, iclass 6, count 2 2006.224.08:25:31.65#ibcon#read 3, iclass 6, count 2 2006.224.08:25:31.65#ibcon#about to read 4, iclass 6, count 2 2006.224.08:25:31.65#ibcon#read 4, iclass 6, count 2 2006.224.08:25:31.65#ibcon#about to read 5, iclass 6, count 2 2006.224.08:25:31.65#ibcon#read 5, iclass 6, count 2 2006.224.08:25:31.65#ibcon#about to read 6, iclass 6, count 2 2006.224.08:25:31.65#ibcon#read 6, iclass 6, count 2 2006.224.08:25:31.65#ibcon#end of sib2, iclass 6, count 2 2006.224.08:25:31.65#ibcon#*after write, iclass 6, count 2 2006.224.08:25:31.65#ibcon#*before return 0, iclass 6, count 2 2006.224.08:25:31.65#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.224.08:25:31.65#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.224.08:25:31.65#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.224.08:25:31.65#ibcon#ireg 7 cls_cnt 0 2006.224.08:25:31.65#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.224.08:25:31.77#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.224.08:25:31.77#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.224.08:25:31.77#ibcon#enter wrdev, iclass 6, count 0 2006.224.08:25:31.77#ibcon#first serial, iclass 6, count 0 2006.224.08:25:31.77#ibcon#enter sib2, iclass 6, count 0 2006.224.08:25:31.77#ibcon#flushed, iclass 6, count 0 2006.224.08:25:31.77#ibcon#about to write, iclass 6, count 0 2006.224.08:25:31.77#ibcon#wrote, iclass 6, count 0 2006.224.08:25:31.77#ibcon#about to read 3, iclass 6, count 0 2006.224.08:25:31.79#ibcon#read 3, iclass 6, count 0 2006.224.08:25:31.79#ibcon#about to read 4, iclass 6, count 0 2006.224.08:25:31.79#ibcon#read 4, iclass 6, count 0 2006.224.08:25:31.79#ibcon#about to read 5, iclass 6, count 0 2006.224.08:25:31.79#ibcon#read 5, iclass 6, count 0 2006.224.08:25:31.79#ibcon#about to read 6, iclass 6, count 0 2006.224.08:25:31.79#ibcon#read 6, iclass 6, count 0 2006.224.08:25:31.79#ibcon#end of sib2, iclass 6, count 0 2006.224.08:25:31.79#ibcon#*mode == 0, iclass 6, count 0 2006.224.08:25:31.79#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.224.08:25:31.79#ibcon#[27=USB\r\n] 2006.224.08:25:31.79#ibcon#*before write, iclass 6, count 0 2006.224.08:25:31.79#ibcon#enter sib2, iclass 6, count 0 2006.224.08:25:31.79#ibcon#flushed, iclass 6, count 0 2006.224.08:25:31.79#ibcon#about to write, iclass 6, count 0 2006.224.08:25:31.79#ibcon#wrote, iclass 6, count 0 2006.224.08:25:31.79#ibcon#about to read 3, iclass 6, count 0 2006.224.08:25:31.82#ibcon#read 3, iclass 6, count 0 2006.224.08:25:31.82#ibcon#about to read 4, iclass 6, count 0 2006.224.08:25:31.82#ibcon#read 4, iclass 6, count 0 2006.224.08:25:31.82#ibcon#about to read 5, iclass 6, count 0 2006.224.08:25:31.82#ibcon#read 5, iclass 6, count 0 2006.224.08:25:31.82#ibcon#about to read 6, iclass 6, count 0 2006.224.08:25:31.82#ibcon#read 6, iclass 6, count 0 2006.224.08:25:31.82#ibcon#end of sib2, iclass 6, count 0 2006.224.08:25:31.82#ibcon#*after write, iclass 6, count 0 2006.224.08:25:31.82#ibcon#*before return 0, iclass 6, count 0 2006.224.08:25:31.82#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.224.08:25:31.82#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.224.08:25:31.82#ibcon#about to clear, iclass 6 cls_cnt 0 2006.224.08:25:31.82#ibcon#cleared, iclass 6 cls_cnt 0 2006.224.08:25:31.82$vc4f8/vblo=5,744.99 2006.224.08:25:31.82#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.224.08:25:31.82#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.224.08:25:31.82#ibcon#ireg 17 cls_cnt 0 2006.224.08:25:31.82#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.224.08:25:31.82#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.224.08:25:31.82#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.224.08:25:31.82#ibcon#enter wrdev, iclass 10, count 0 2006.224.08:25:31.82#ibcon#first serial, iclass 10, count 0 2006.224.08:25:31.82#ibcon#enter sib2, iclass 10, count 0 2006.224.08:25:31.82#ibcon#flushed, iclass 10, count 0 2006.224.08:25:31.82#ibcon#about to write, iclass 10, count 0 2006.224.08:25:31.82#ibcon#wrote, iclass 10, count 0 2006.224.08:25:31.82#ibcon#about to read 3, iclass 10, count 0 2006.224.08:25:31.84#ibcon#read 3, iclass 10, count 0 2006.224.08:25:31.84#ibcon#about to read 4, iclass 10, count 0 2006.224.08:25:31.84#ibcon#read 4, iclass 10, count 0 2006.224.08:25:31.84#ibcon#about to read 5, iclass 10, count 0 2006.224.08:25:31.84#ibcon#read 5, iclass 10, count 0 2006.224.08:25:31.84#ibcon#about to read 6, iclass 10, count 0 2006.224.08:25:31.84#ibcon#read 6, iclass 10, count 0 2006.224.08:25:31.84#ibcon#end of sib2, iclass 10, count 0 2006.224.08:25:31.84#ibcon#*mode == 0, iclass 10, count 0 2006.224.08:25:31.84#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.224.08:25:31.84#ibcon#[28=FRQ=05,744.99\r\n] 2006.224.08:25:31.84#ibcon#*before write, iclass 10, count 0 2006.224.08:25:31.84#ibcon#enter sib2, iclass 10, count 0 2006.224.08:25:31.84#ibcon#flushed, iclass 10, count 0 2006.224.08:25:31.84#ibcon#about to write, iclass 10, count 0 2006.224.08:25:31.84#ibcon#wrote, iclass 10, count 0 2006.224.08:25:31.84#ibcon#about to read 3, iclass 10, count 0 2006.224.08:25:31.88#ibcon#read 3, iclass 10, count 0 2006.224.08:25:31.88#ibcon#about to read 4, iclass 10, count 0 2006.224.08:25:31.88#ibcon#read 4, iclass 10, count 0 2006.224.08:25:31.88#ibcon#about to read 5, iclass 10, count 0 2006.224.08:25:31.88#ibcon#read 5, iclass 10, count 0 2006.224.08:25:31.88#ibcon#about to read 6, iclass 10, count 0 2006.224.08:25:31.88#ibcon#read 6, iclass 10, count 0 2006.224.08:25:31.88#ibcon#end of sib2, iclass 10, count 0 2006.224.08:25:31.88#ibcon#*after write, iclass 10, count 0 2006.224.08:25:31.88#ibcon#*before return 0, iclass 10, count 0 2006.224.08:25:31.88#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.224.08:25:31.88#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.224.08:25:31.88#ibcon#about to clear, iclass 10 cls_cnt 0 2006.224.08:25:31.88#ibcon#cleared, iclass 10 cls_cnt 0 2006.224.08:25:31.88$vc4f8/vb=5,4 2006.224.08:25:31.88#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.224.08:25:31.88#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.224.08:25:31.88#ibcon#ireg 11 cls_cnt 2 2006.224.08:25:31.88#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.224.08:25:31.94#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.224.08:25:31.94#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.224.08:25:31.94#ibcon#enter wrdev, iclass 12, count 2 2006.224.08:25:31.94#ibcon#first serial, iclass 12, count 2 2006.224.08:25:31.94#ibcon#enter sib2, iclass 12, count 2 2006.224.08:25:31.94#ibcon#flushed, iclass 12, count 2 2006.224.08:25:31.94#ibcon#about to write, iclass 12, count 2 2006.224.08:25:31.94#ibcon#wrote, iclass 12, count 2 2006.224.08:25:31.94#ibcon#about to read 3, iclass 12, count 2 2006.224.08:25:31.96#ibcon#read 3, iclass 12, count 2 2006.224.08:25:31.96#ibcon#about to read 4, iclass 12, count 2 2006.224.08:25:31.96#ibcon#read 4, iclass 12, count 2 2006.224.08:25:31.96#ibcon#about to read 5, iclass 12, count 2 2006.224.08:25:31.96#ibcon#read 5, iclass 12, count 2 2006.224.08:25:31.96#ibcon#about to read 6, iclass 12, count 2 2006.224.08:25:31.96#ibcon#read 6, iclass 12, count 2 2006.224.08:25:31.96#ibcon#end of sib2, iclass 12, count 2 2006.224.08:25:31.96#ibcon#*mode == 0, iclass 12, count 2 2006.224.08:25:31.96#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.224.08:25:31.96#ibcon#[27=AT05-04\r\n] 2006.224.08:25:31.96#ibcon#*before write, iclass 12, count 2 2006.224.08:25:31.96#ibcon#enter sib2, iclass 12, count 2 2006.224.08:25:31.96#ibcon#flushed, iclass 12, count 2 2006.224.08:25:31.96#ibcon#about to write, iclass 12, count 2 2006.224.08:25:31.96#ibcon#wrote, iclass 12, count 2 2006.224.08:25:31.96#ibcon#about to read 3, iclass 12, count 2 2006.224.08:25:31.99#ibcon#read 3, iclass 12, count 2 2006.224.08:25:31.99#ibcon#about to read 4, iclass 12, count 2 2006.224.08:25:31.99#ibcon#read 4, iclass 12, count 2 2006.224.08:25:31.99#ibcon#about to read 5, iclass 12, count 2 2006.224.08:25:31.99#ibcon#read 5, iclass 12, count 2 2006.224.08:25:31.99#ibcon#about to read 6, iclass 12, count 2 2006.224.08:25:31.99#ibcon#read 6, iclass 12, count 2 2006.224.08:25:31.99#ibcon#end of sib2, iclass 12, count 2 2006.224.08:25:31.99#ibcon#*after write, iclass 12, count 2 2006.224.08:25:31.99#ibcon#*before return 0, iclass 12, count 2 2006.224.08:25:31.99#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.224.08:25:31.99#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.224.08:25:31.99#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.224.08:25:31.99#ibcon#ireg 7 cls_cnt 0 2006.224.08:25:31.99#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.224.08:25:32.11#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.224.08:25:32.11#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.224.08:25:32.11#ibcon#enter wrdev, iclass 12, count 0 2006.224.08:25:32.11#ibcon#first serial, iclass 12, count 0 2006.224.08:25:32.11#ibcon#enter sib2, iclass 12, count 0 2006.224.08:25:32.11#ibcon#flushed, iclass 12, count 0 2006.224.08:25:32.11#ibcon#about to write, iclass 12, count 0 2006.224.08:25:32.11#ibcon#wrote, iclass 12, count 0 2006.224.08:25:32.11#ibcon#about to read 3, iclass 12, count 0 2006.224.08:25:32.13#ibcon#read 3, iclass 12, count 0 2006.224.08:25:32.13#ibcon#about to read 4, iclass 12, count 0 2006.224.08:25:32.13#ibcon#read 4, iclass 12, count 0 2006.224.08:25:32.13#ibcon#about to read 5, iclass 12, count 0 2006.224.08:25:32.13#ibcon#read 5, iclass 12, count 0 2006.224.08:25:32.13#ibcon#about to read 6, iclass 12, count 0 2006.224.08:25:32.13#ibcon#read 6, iclass 12, count 0 2006.224.08:25:32.13#ibcon#end of sib2, iclass 12, count 0 2006.224.08:25:32.13#ibcon#*mode == 0, iclass 12, count 0 2006.224.08:25:32.13#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.224.08:25:32.13#ibcon#[27=USB\r\n] 2006.224.08:25:32.13#ibcon#*before write, iclass 12, count 0 2006.224.08:25:32.13#ibcon#enter sib2, iclass 12, count 0 2006.224.08:25:32.13#ibcon#flushed, iclass 12, count 0 2006.224.08:25:32.13#ibcon#about to write, iclass 12, count 0 2006.224.08:25:32.13#ibcon#wrote, iclass 12, count 0 2006.224.08:25:32.13#ibcon#about to read 3, iclass 12, count 0 2006.224.08:25:32.16#ibcon#read 3, iclass 12, count 0 2006.224.08:25:32.16#ibcon#about to read 4, iclass 12, count 0 2006.224.08:25:32.16#ibcon#read 4, iclass 12, count 0 2006.224.08:25:32.16#ibcon#about to read 5, iclass 12, count 0 2006.224.08:25:32.16#ibcon#read 5, iclass 12, count 0 2006.224.08:25:32.16#ibcon#about to read 6, iclass 12, count 0 2006.224.08:25:32.16#ibcon#read 6, iclass 12, count 0 2006.224.08:25:32.16#ibcon#end of sib2, iclass 12, count 0 2006.224.08:25:32.16#ibcon#*after write, iclass 12, count 0 2006.224.08:25:32.16#ibcon#*before return 0, iclass 12, count 0 2006.224.08:25:32.16#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.224.08:25:32.16#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.224.08:25:32.16#ibcon#about to clear, iclass 12 cls_cnt 0 2006.224.08:25:32.16#ibcon#cleared, iclass 12 cls_cnt 0 2006.224.08:25:32.16$vc4f8/vblo=6,752.99 2006.224.08:25:32.16#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.224.08:25:32.16#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.224.08:25:32.16#ibcon#ireg 17 cls_cnt 0 2006.224.08:25:32.16#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.224.08:25:32.16#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.224.08:25:32.16#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.224.08:25:32.16#ibcon#enter wrdev, iclass 14, count 0 2006.224.08:25:32.16#ibcon#first serial, iclass 14, count 0 2006.224.08:25:32.16#ibcon#enter sib2, iclass 14, count 0 2006.224.08:25:32.16#ibcon#flushed, iclass 14, count 0 2006.224.08:25:32.16#ibcon#about to write, iclass 14, count 0 2006.224.08:25:32.16#ibcon#wrote, iclass 14, count 0 2006.224.08:25:32.16#ibcon#about to read 3, iclass 14, count 0 2006.224.08:25:32.19#ibcon#read 3, iclass 14, count 0 2006.224.08:25:32.19#ibcon#about to read 4, iclass 14, count 0 2006.224.08:25:32.19#ibcon#read 4, iclass 14, count 0 2006.224.08:25:32.19#ibcon#about to read 5, iclass 14, count 0 2006.224.08:25:32.19#ibcon#read 5, iclass 14, count 0 2006.224.08:25:32.19#ibcon#about to read 6, iclass 14, count 0 2006.224.08:25:32.19#ibcon#read 6, iclass 14, count 0 2006.224.08:25:32.19#ibcon#end of sib2, iclass 14, count 0 2006.224.08:25:32.19#ibcon#*mode == 0, iclass 14, count 0 2006.224.08:25:32.19#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.224.08:25:32.19#ibcon#[28=FRQ=06,752.99\r\n] 2006.224.08:25:32.19#ibcon#*before write, iclass 14, count 0 2006.224.08:25:32.19#ibcon#enter sib2, iclass 14, count 0 2006.224.08:25:32.19#ibcon#flushed, iclass 14, count 0 2006.224.08:25:32.19#ibcon#about to write, iclass 14, count 0 2006.224.08:25:32.19#ibcon#wrote, iclass 14, count 0 2006.224.08:25:32.19#ibcon#about to read 3, iclass 14, count 0 2006.224.08:25:32.23#ibcon#read 3, iclass 14, count 0 2006.224.08:25:32.23#ibcon#about to read 4, iclass 14, count 0 2006.224.08:25:32.23#ibcon#read 4, iclass 14, count 0 2006.224.08:25:32.23#ibcon#about to read 5, iclass 14, count 0 2006.224.08:25:32.23#ibcon#read 5, iclass 14, count 0 2006.224.08:25:32.23#ibcon#about to read 6, iclass 14, count 0 2006.224.08:25:32.23#ibcon#read 6, iclass 14, count 0 2006.224.08:25:32.23#ibcon#end of sib2, iclass 14, count 0 2006.224.08:25:32.23#ibcon#*after write, iclass 14, count 0 2006.224.08:25:32.23#ibcon#*before return 0, iclass 14, count 0 2006.224.08:25:32.23#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.224.08:25:32.23#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.224.08:25:32.23#ibcon#about to clear, iclass 14 cls_cnt 0 2006.224.08:25:32.23#ibcon#cleared, iclass 14 cls_cnt 0 2006.224.08:25:32.23$vc4f8/vb=6,4 2006.224.08:25:32.23#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.224.08:25:32.23#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.224.08:25:32.23#ibcon#ireg 11 cls_cnt 2 2006.224.08:25:32.23#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.224.08:25:32.28#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.224.08:25:32.28#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.224.08:25:32.28#ibcon#enter wrdev, iclass 16, count 2 2006.224.08:25:32.28#ibcon#first serial, iclass 16, count 2 2006.224.08:25:32.28#ibcon#enter sib2, iclass 16, count 2 2006.224.08:25:32.28#ibcon#flushed, iclass 16, count 2 2006.224.08:25:32.28#ibcon#about to write, iclass 16, count 2 2006.224.08:25:32.28#ibcon#wrote, iclass 16, count 2 2006.224.08:25:32.28#ibcon#about to read 3, iclass 16, count 2 2006.224.08:25:32.30#ibcon#read 3, iclass 16, count 2 2006.224.08:25:32.30#ibcon#about to read 4, iclass 16, count 2 2006.224.08:25:32.30#ibcon#read 4, iclass 16, count 2 2006.224.08:25:32.30#ibcon#about to read 5, iclass 16, count 2 2006.224.08:25:32.30#ibcon#read 5, iclass 16, count 2 2006.224.08:25:32.30#ibcon#about to read 6, iclass 16, count 2 2006.224.08:25:32.30#ibcon#read 6, iclass 16, count 2 2006.224.08:25:32.30#ibcon#end of sib2, iclass 16, count 2 2006.224.08:25:32.30#ibcon#*mode == 0, iclass 16, count 2 2006.224.08:25:32.30#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.224.08:25:32.30#ibcon#[27=AT06-04\r\n] 2006.224.08:25:32.30#ibcon#*before write, iclass 16, count 2 2006.224.08:25:32.30#ibcon#enter sib2, iclass 16, count 2 2006.224.08:25:32.30#ibcon#flushed, iclass 16, count 2 2006.224.08:25:32.30#ibcon#about to write, iclass 16, count 2 2006.224.08:25:32.30#ibcon#wrote, iclass 16, count 2 2006.224.08:25:32.30#ibcon#about to read 3, iclass 16, count 2 2006.224.08:25:32.33#ibcon#read 3, iclass 16, count 2 2006.224.08:25:32.33#ibcon#about to read 4, iclass 16, count 2 2006.224.08:25:32.33#ibcon#read 4, iclass 16, count 2 2006.224.08:25:32.33#ibcon#about to read 5, iclass 16, count 2 2006.224.08:25:32.33#ibcon#read 5, iclass 16, count 2 2006.224.08:25:32.33#ibcon#about to read 6, iclass 16, count 2 2006.224.08:25:32.33#ibcon#read 6, iclass 16, count 2 2006.224.08:25:32.33#ibcon#end of sib2, iclass 16, count 2 2006.224.08:25:32.33#ibcon#*after write, iclass 16, count 2 2006.224.08:25:32.33#ibcon#*before return 0, iclass 16, count 2 2006.224.08:25:32.33#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.224.08:25:32.33#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.224.08:25:32.33#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.224.08:25:32.33#ibcon#ireg 7 cls_cnt 0 2006.224.08:25:32.33#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.224.08:25:32.45#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.224.08:25:32.45#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.224.08:25:32.45#ibcon#enter wrdev, iclass 16, count 0 2006.224.08:25:32.45#ibcon#first serial, iclass 16, count 0 2006.224.08:25:32.45#ibcon#enter sib2, iclass 16, count 0 2006.224.08:25:32.45#ibcon#flushed, iclass 16, count 0 2006.224.08:25:32.45#ibcon#about to write, iclass 16, count 0 2006.224.08:25:32.45#ibcon#wrote, iclass 16, count 0 2006.224.08:25:32.45#ibcon#about to read 3, iclass 16, count 0 2006.224.08:25:32.47#ibcon#read 3, iclass 16, count 0 2006.224.08:25:32.47#ibcon#about to read 4, iclass 16, count 0 2006.224.08:25:32.47#ibcon#read 4, iclass 16, count 0 2006.224.08:25:32.47#ibcon#about to read 5, iclass 16, count 0 2006.224.08:25:32.47#ibcon#read 5, iclass 16, count 0 2006.224.08:25:32.47#ibcon#about to read 6, iclass 16, count 0 2006.224.08:25:32.47#ibcon#read 6, iclass 16, count 0 2006.224.08:25:32.47#ibcon#end of sib2, iclass 16, count 0 2006.224.08:25:32.47#ibcon#*mode == 0, iclass 16, count 0 2006.224.08:25:32.47#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.224.08:25:32.47#ibcon#[27=USB\r\n] 2006.224.08:25:32.47#ibcon#*before write, iclass 16, count 0 2006.224.08:25:32.47#ibcon#enter sib2, iclass 16, count 0 2006.224.08:25:32.47#ibcon#flushed, iclass 16, count 0 2006.224.08:25:32.47#ibcon#about to write, iclass 16, count 0 2006.224.08:25:32.47#ibcon#wrote, iclass 16, count 0 2006.224.08:25:32.47#ibcon#about to read 3, iclass 16, count 0 2006.224.08:25:32.50#ibcon#read 3, iclass 16, count 0 2006.224.08:25:32.50#ibcon#about to read 4, iclass 16, count 0 2006.224.08:25:32.50#ibcon#read 4, iclass 16, count 0 2006.224.08:25:32.50#ibcon#about to read 5, iclass 16, count 0 2006.224.08:25:32.50#ibcon#read 5, iclass 16, count 0 2006.224.08:25:32.50#ibcon#about to read 6, iclass 16, count 0 2006.224.08:25:32.50#ibcon#read 6, iclass 16, count 0 2006.224.08:25:32.50#ibcon#end of sib2, iclass 16, count 0 2006.224.08:25:32.50#ibcon#*after write, iclass 16, count 0 2006.224.08:25:32.50#ibcon#*before return 0, iclass 16, count 0 2006.224.08:25:32.50#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.224.08:25:32.50#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.224.08:25:32.50#ibcon#about to clear, iclass 16 cls_cnt 0 2006.224.08:25:32.50#ibcon#cleared, iclass 16 cls_cnt 0 2006.224.08:25:32.50$vc4f8/vabw=wide 2006.224.08:25:32.50#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.224.08:25:32.50#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.224.08:25:32.50#ibcon#ireg 8 cls_cnt 0 2006.224.08:25:32.50#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.224.08:25:32.50#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.224.08:25:32.50#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.224.08:25:32.50#ibcon#enter wrdev, iclass 18, count 0 2006.224.08:25:32.50#ibcon#first serial, iclass 18, count 0 2006.224.08:25:32.50#ibcon#enter sib2, iclass 18, count 0 2006.224.08:25:32.50#ibcon#flushed, iclass 18, count 0 2006.224.08:25:32.50#ibcon#about to write, iclass 18, count 0 2006.224.08:25:32.50#ibcon#wrote, iclass 18, count 0 2006.224.08:25:32.50#ibcon#about to read 3, iclass 18, count 0 2006.224.08:25:32.52#ibcon#read 3, iclass 18, count 0 2006.224.08:25:32.52#ibcon#about to read 4, iclass 18, count 0 2006.224.08:25:32.52#ibcon#read 4, iclass 18, count 0 2006.224.08:25:32.52#ibcon#about to read 5, iclass 18, count 0 2006.224.08:25:32.52#ibcon#read 5, iclass 18, count 0 2006.224.08:25:32.52#ibcon#about to read 6, iclass 18, count 0 2006.224.08:25:32.52#ibcon#read 6, iclass 18, count 0 2006.224.08:25:32.52#ibcon#end of sib2, iclass 18, count 0 2006.224.08:25:32.52#ibcon#*mode == 0, iclass 18, count 0 2006.224.08:25:32.52#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.224.08:25:32.52#ibcon#[25=BW32\r\n] 2006.224.08:25:32.52#ibcon#*before write, iclass 18, count 0 2006.224.08:25:32.52#ibcon#enter sib2, iclass 18, count 0 2006.224.08:25:32.52#ibcon#flushed, iclass 18, count 0 2006.224.08:25:32.52#ibcon#about to write, iclass 18, count 0 2006.224.08:25:32.52#ibcon#wrote, iclass 18, count 0 2006.224.08:25:32.52#ibcon#about to read 3, iclass 18, count 0 2006.224.08:25:32.55#ibcon#read 3, iclass 18, count 0 2006.224.08:25:32.55#ibcon#about to read 4, iclass 18, count 0 2006.224.08:25:32.55#ibcon#read 4, iclass 18, count 0 2006.224.08:25:32.55#ibcon#about to read 5, iclass 18, count 0 2006.224.08:25:32.55#ibcon#read 5, iclass 18, count 0 2006.224.08:25:32.55#ibcon#about to read 6, iclass 18, count 0 2006.224.08:25:32.55#ibcon#read 6, iclass 18, count 0 2006.224.08:25:32.55#ibcon#end of sib2, iclass 18, count 0 2006.224.08:25:32.55#ibcon#*after write, iclass 18, count 0 2006.224.08:25:32.55#ibcon#*before return 0, iclass 18, count 0 2006.224.08:25:32.55#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.224.08:25:32.55#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.224.08:25:32.55#ibcon#about to clear, iclass 18 cls_cnt 0 2006.224.08:25:32.55#ibcon#cleared, iclass 18 cls_cnt 0 2006.224.08:25:32.55$vc4f8/vbbw=wide 2006.224.08:25:32.55#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.224.08:25:32.55#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.224.08:25:32.55#ibcon#ireg 8 cls_cnt 0 2006.224.08:25:32.55#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.224.08:25:32.62#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.224.08:25:32.62#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.224.08:25:32.62#ibcon#enter wrdev, iclass 20, count 0 2006.224.08:25:32.62#ibcon#first serial, iclass 20, count 0 2006.224.08:25:32.62#ibcon#enter sib2, iclass 20, count 0 2006.224.08:25:32.62#ibcon#flushed, iclass 20, count 0 2006.224.08:25:32.62#ibcon#about to write, iclass 20, count 0 2006.224.08:25:32.62#ibcon#wrote, iclass 20, count 0 2006.224.08:25:32.62#ibcon#about to read 3, iclass 20, count 0 2006.224.08:25:32.64#ibcon#read 3, iclass 20, count 0 2006.224.08:25:32.64#ibcon#about to read 4, iclass 20, count 0 2006.224.08:25:32.64#ibcon#read 4, iclass 20, count 0 2006.224.08:25:32.64#ibcon#about to read 5, iclass 20, count 0 2006.224.08:25:32.64#ibcon#read 5, iclass 20, count 0 2006.224.08:25:32.64#ibcon#about to read 6, iclass 20, count 0 2006.224.08:25:32.64#ibcon#read 6, iclass 20, count 0 2006.224.08:25:32.64#ibcon#end of sib2, iclass 20, count 0 2006.224.08:25:32.64#ibcon#*mode == 0, iclass 20, count 0 2006.224.08:25:32.64#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.224.08:25:32.64#ibcon#[27=BW32\r\n] 2006.224.08:25:32.64#ibcon#*before write, iclass 20, count 0 2006.224.08:25:32.64#ibcon#enter sib2, iclass 20, count 0 2006.224.08:25:32.64#ibcon#flushed, iclass 20, count 0 2006.224.08:25:32.64#ibcon#about to write, iclass 20, count 0 2006.224.08:25:32.64#ibcon#wrote, iclass 20, count 0 2006.224.08:25:32.64#ibcon#about to read 3, iclass 20, count 0 2006.224.08:25:32.67#ibcon#read 3, iclass 20, count 0 2006.224.08:25:32.67#ibcon#about to read 4, iclass 20, count 0 2006.224.08:25:32.67#ibcon#read 4, iclass 20, count 0 2006.224.08:25:32.67#ibcon#about to read 5, iclass 20, count 0 2006.224.08:25:32.67#ibcon#read 5, iclass 20, count 0 2006.224.08:25:32.67#ibcon#about to read 6, iclass 20, count 0 2006.224.08:25:32.67#ibcon#read 6, iclass 20, count 0 2006.224.08:25:32.67#ibcon#end of sib2, iclass 20, count 0 2006.224.08:25:32.67#ibcon#*after write, iclass 20, count 0 2006.224.08:25:32.67#ibcon#*before return 0, iclass 20, count 0 2006.224.08:25:32.67#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.224.08:25:32.67#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.224.08:25:32.67#ibcon#about to clear, iclass 20 cls_cnt 0 2006.224.08:25:32.67#ibcon#cleared, iclass 20 cls_cnt 0 2006.224.08:25:32.67$4f8m12a/ifd4f 2006.224.08:25:32.67$ifd4f/lo= 2006.224.08:25:32.67$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.224.08:25:32.67$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.224.08:25:32.67$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.224.08:25:32.67$ifd4f/patch= 2006.224.08:25:32.67$ifd4f/patch=lo1,a1,a2,a3,a4 2006.224.08:25:32.67$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.224.08:25:32.67$ifd4f/patch=lo3,a5,a6,a7,a8 2006.224.08:25:32.67$4f8m12a/"form=m,16.000,1:2 2006.224.08:25:32.67$4f8m12a/"tpicd 2006.224.08:25:32.67$4f8m12a/echo=off 2006.224.08:25:32.68$4f8m12a/xlog=off 2006.224.08:25:32.68:!2006.224.08:26:00 2006.224.08:25:35.14#trakl#Source acquired 2006.224.08:25:35.14#flagr#flagr/antenna,acquired 2006.224.08:26:00.01:preob 2006.224.08:26:01.14/onsource/TRACKING 2006.224.08:26:01.14:!2006.224.08:26:10 2006.224.08:26:10.00:data_valid=on 2006.224.08:26:10.00:midob 2006.224.08:26:10.14/onsource/TRACKING 2006.224.08:26:10.14/wx/23.70,1004.7,100 2006.224.08:26:10.25/cable/+6.4365E-03 2006.224.08:26:11.34/va/01,08,usb,yes,39,41 2006.224.08:26:11.34/va/02,07,usb,yes,39,41 2006.224.08:26:11.34/va/03,06,usb,yes,42,42 2006.224.08:26:11.34/va/04,07,usb,yes,41,44 2006.224.08:26:11.34/va/05,07,usb,yes,48,50 2006.224.08:26:11.34/va/06,06,usb,yes,47,47 2006.224.08:26:11.34/va/07,06,usb,yes,48,48 2006.224.08:26:11.34/va/08,07,usb,yes,45,45 2006.224.08:26:11.57/valo/01,532.99,yes,locked 2006.224.08:26:11.57/valo/02,572.99,yes,locked 2006.224.08:26:11.57/valo/03,672.99,yes,locked 2006.224.08:26:11.57/valo/04,832.99,yes,locked 2006.224.08:26:11.57/valo/05,652.99,yes,locked 2006.224.08:26:11.57/valo/06,772.99,yes,locked 2006.224.08:26:11.57/valo/07,832.99,yes,locked 2006.224.08:26:11.57/valo/08,852.99,yes,locked 2006.224.08:26:12.66/vb/01,04,usb,yes,31,30 2006.224.08:26:12.66/vb/02,04,usb,yes,33,35 2006.224.08:26:12.66/vb/03,04,usb,yes,30,34 2006.224.08:26:12.66/vb/04,04,usb,yes,30,31 2006.224.08:26:12.66/vb/05,04,usb,yes,29,33 2006.224.08:26:12.66/vb/06,04,usb,yes,30,33 2006.224.08:26:12.66/vb/07,04,usb,yes,32,32 2006.224.08:26:12.66/vb/08,04,usb,yes,29,33 2006.224.08:26:12.89/vblo/01,632.99,yes,locked 2006.224.08:26:12.89/vblo/02,640.99,yes,locked 2006.224.08:26:12.89/vblo/03,656.99,yes,locked 2006.224.08:26:12.89/vblo/04,712.99,yes,locked 2006.224.08:26:12.89/vblo/05,744.99,yes,locked 2006.224.08:26:12.89/vblo/06,752.99,yes,locked 2006.224.08:26:12.89/vblo/07,734.99,yes,locked 2006.224.08:26:12.89/vblo/08,744.99,yes,locked 2006.224.08:26:13.04/vabw/8 2006.224.08:26:13.19/vbbw/8 2006.224.08:26:13.40/xfe/off,on,15.5 2006.224.08:26:13.79/ifatt/23,28,28,28 2006.224.08:26:14.07/fmout-gps/S +4.48E-07 2006.224.08:26:14.11:!2006.224.08:27:10 2006.224.08:27:10.00:data_valid=off 2006.224.08:27:10.00:postob 2006.224.08:27:10.13/cable/+6.4348E-03 2006.224.08:27:10.13/wx/23.69,1004.7,100 2006.224.08:27:11.08/fmout-gps/S +4.48E-07 2006.224.08:27:11.08:checkk5last 2006.224.08:27:11.08&checkk5last/chk_obsdata=1 2006.224.08:27:11.08&checkk5last/chk_obsdata=2 2006.224.08:27:11.08&checkk5last/chk_obsdata=3 2006.224.08:27:11.08&checkk5last/chk_obsdata=4 2006.224.08:27:11.08&checkk5last/k5log=1 2006.224.08:27:11.08&checkk5last/k5log=2 2006.224.08:27:11.08&checkk5last/k5log=3 2006.224.08:27:11.08&checkk5last/k5log=4 2006.224.08:27:11.08&checkk5last/obsinfo 2006.224.08:27:11.46/chk_obsdata//k5ts1/T2240826??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.08:27:11.83/chk_obsdata//k5ts2/T2240826??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.08:27:12.20/chk_obsdata//k5ts3/T2240826??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.08:27:12.56/chk_obsdata//k5ts4/T2240826??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.224.08:27:13.25/k5log//k5ts1_log_newline 2006.224.08:27:13.94/k5log//k5ts2_log_newline 2006.224.08:27:14.62/k5log//k5ts3_log_newline 2006.224.08:27:15.30/k5log//k5ts4_log_newline 2006.224.08:27:15.33/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.224.08:27:15.33:"sched_end 2006.224.08:27:15.33:source=idle 2006.224.08:27:16.13:stow 2006.224.08:27:16.13&stow/source=idle 2006.224.08:27:16.13&stow/"this is stow command. 2006.224.08:27:16.13&stow/antenna=m3 2006.224.08:27:16.13#flagr#flagr/antenna,new-source 2006.224.08:27:19.01:!+10m 2006.224.08:37:19.02:standby 2006.224.08:37:19.02&standby/"this is standby command. 2006.224.08:37:19.02&standby/antenna=m0 2006.224.08:37:20.01:checkk5hdd 2006.224.08:37:20.01&checkk5hdd/chk_hdd=1 2006.224.08:37:20.01&checkk5hdd/chk_hdd=2 2006.224.08:37:20.01&checkk5hdd/chk_hdd=3 2006.224.08:37:20.01&checkk5hdd/chk_hdd=4 2006.224.08:37:22.84/chk_hdd//k5ts1/GSI00275:T224073000a.dat~T224082610a.dat[12953387008Byte] 2006.224.08:37:25.64/chk_hdd//k5ts2/GSI00163:T224073000b.dat~T224082610b.dat[12953387008Byte] 2006.224.08:37:28.45/chk_hdd//k5ts3/GSI00278:T224073000c.dat~T224082610c.dat[12953387008Byte] 2006.224.08:37:31.25/chk_hdd//k5ts4/GSI00141:T224073000d.dat~T224082610d.dat[12953387008Byte] 2006.224.08:37:31.25:sy=cp /usr2/log/k06224ts.log /usr2/log_backup/ 2006.224.08:37:31.34:log=k06225ts