2006.217.19:07:07.10:Log Opened: Mark IV Field System Version 9.7.7 2006.217.19:07:07.11:location,TSUKUB32,-140.09,36.10,61.0 2006.217.19:07:07.11:horizon1,0.,5.,360. 2006.217.19:07:07.11:antenna,32.0,180.0,180.0,10.0,710.0,5.0,88.0,azel 2006.217.19:07:07.12:equip,k42c/mk4,vlbab,vlbab,mk4,500.10,3,a/d,101,60,20,none,41,1,in,8bit,cdp,3 2006.217.19:07:07.12:drivev11,330,270,no 2006.217.19:07:07.12:drivev12,mvme117,0,11.400,2548.000,152.780,-6.655,0.014,152,10.000,54500 2006.217.19:07:07.12:drivev13,15.000,268,10.000,10.000,10.000 2006.217.19:07:07.12:drivev21,330,270,no 2006.217.19:07:07.12:drivev22,mvme117,0,11.500,2821.000,127.500,-8.640,0.015,152,14.000,54500 2006.217.19:07:07.12:drivev23,15.000,268,10.000,10.000,10.000 2006.217.19:07:07.12:head10,all,all,all,odd,adaptive,no,5.0000,1 2006.217.19:07:07.12:head11,131.5,16.4,-291.0,131.5,16.4,0.8,168.30,168.30 2006.217.19:07:07.12:head12,122.8,13.9,-150.8,122.8,14.7,2.5,167.61,167.61 2006.217.19:07:07.12:head20,all,all,all,odd,adaptive,no,5.0000,1 2006.217.19:07:07.12:head21,145.3,16.1,-209.3,137.2,16.1,58.9,165.28,165.28 2006.217.19:07:07.12:head22,157.5,17.4,-203.7,149.2,16.6,56.5,169.73,169.73 2006.217.19:07:07.12:time,-0.364,101.533,rate 2006.217.19:07:07.12:flagr,200 2006.217.19:07:07.12:proc=k06218ts 2006.217.19:07:07.12:" k06218 2006 tsukub32 t ts 2006.217.19:07:07.12:" t tsukub32 azel .0000 180.0 14 10.0 710.0 180.0 14 5.0 88.0 32.0 ts 108 2006.217.19:07:07.12:" ts tsukub32 -3957408.75120 3310229.34660 3737494.83600 73452301 2006.217.19:07:07.12:" 108 tsukub32 14 17400 2006.217.19:07:07.12:" drudg version 050216 compiled under fs 9.7.07 2006.217.19:07:07.12:" rack=k4-2/m4 recorder 1=k5 recorder 2=none 2006.217.19:07:07.12:!2006.218.06:29:50 2006.218.06:29:50.00:sy=/usr2/oper/k5/bin/freeze_chk.pl & 2006.218.06:29:50.02:!2006.218.07:19:50 2006.218.07:19:50.00:unstow 2006.218.07:19:50.00&unstow/antenna=e 2006.218.07:19:50.00&unstow/!+10s 2006.218.07:19:50.00&unstow/antenna=m2 2006.218.07:20:02.01:scan_name=218-0730,k06218,60 2006.218.07:20:02.01:source=3c418,203837.03,511912.7,2000.0,ccw 2006.218.07:20:03.13#antcn#PM 1 00019 2005 228 00 22 31 00 2006.218.07:20:03.13#antcn#PM 2 90.0000 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 2006.218.07:20:03.13#antcn#PM 2 -0.0279715 0.0000000 -0.0282214 -0.0241630 -0.0014011 2006.218.07:20:03.13#antcn#PM 3 -0.0059899 0.0042895 -0.0643783 0.0000000 0.0000000 2006.218.07:20:03.13#antcn#PM 4 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.218.07:20:03.13#antcn#PM 5 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.218.07:20:04.13:ready_k5 2006.218.07:20:04.13&ready_k5/obsinfo=st 2006.218.07:20:04.13&ready_k5/autoobs=1 2006.218.07:20:04.13&ready_k5/autoobs=2 2006.218.07:20:04.13&ready_k5/autoobs=3 2006.218.07:20:04.13&ready_k5/autoobs=4 2006.218.07:20:04.13&ready_k5/obsinfo 2006.218.07:20:04.13#flagr#flagr/antenna,new-source 2006.218.07:20:04.13/obsinfo=st/error_log.tmp was not found (or not removed). 2006.218.07:20:07.34/autoobs//k5ts1/ autoobs started! 2006.218.07:20:10.46/autoobs//k5ts2/ autoobs started! 2006.218.07:20:13.59/autoobs//k5ts3/ autoobs started! 2006.218.07:20:17.25/autoobs//k5ts4/ autoobs started! 2006.218.07:20:17.28/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.218.07:20:17.28:4f8m12a=1 2006.218.07:20:17.28&4f8m12a/xlog=on 2006.218.07:20:17.28&4f8m12a/echo=on 2006.218.07:20:17.28&4f8m12a/pcalon 2006.218.07:20:17.28&4f8m12a/"tpicd=stop 2006.218.07:20:17.28&4f8m12a/vc4f8 2006.218.07:20:17.28&4f8m12a/ifd4f 2006.218.07:20:17.28&4f8m12a/"form=m,16.000,1:2 2006.218.07:20:17.28&4f8m12a/"tpicd 2006.218.07:20:17.28&4f8m12a/echo=off 2006.218.07:20:17.28&4f8m12a/xlog=off 2006.218.07:20:17.28$4f8m12a/echo=on 2006.218.07:20:17.28$4f8m12a/pcalon 2006.218.07:20:17.28&pcalon/"no phase cal control is implemented here 2006.218.07:20:17.28$pcalon/"no phase cal control is implemented here 2006.218.07:20:17.28$4f8m12a/"tpicd=stop 2006.218.07:20:17.28$4f8m12a/vc4f8 2006.218.07:20:17.28&vc4f8/valo=1,532.99 2006.218.07:20:17.28&vc4f8/va=1,5 2006.218.07:20:17.28&vc4f8/valo=2,572.99 2006.218.07:20:17.28&vc4f8/va=2,4 2006.218.07:20:17.28&vc4f8/valo=3,672.99 2006.218.07:20:17.28&vc4f8/va=3,4 2006.218.07:20:17.28&vc4f8/valo=4,832.99 2006.218.07:20:17.28&vc4f8/va=4,4 2006.218.07:20:17.28&vc4f8/valo=5,652.99 2006.218.07:20:17.28&vc4f8/va=5,7 2006.218.07:20:17.28&vc4f8/valo=6,772.99 2006.218.07:20:17.28&vc4f8/va=6,6 2006.218.07:20:17.28&vc4f8/valo=7,832.99 2006.218.07:20:17.28&vc4f8/va=7,6 2006.218.07:20:17.28&vc4f8/valo=8,852.99 2006.218.07:20:17.28&vc4f8/va=8,7 2006.218.07:20:17.28&vc4f8/vblo=1,632.99 2006.218.07:20:17.28&vc4f8/vb=1,4 2006.218.07:20:17.28&vc4f8/vblo=2,640.99 2006.218.07:20:17.28&vc4f8/vb=2,4 2006.218.07:20:17.28&vc4f8/vblo=3,656.99 2006.218.07:20:17.28&vc4f8/vb=3,4 2006.218.07:20:17.28&vc4f8/vblo=4,712.99 2006.218.07:20:17.28&vc4f8/vb=4,4 2006.218.07:20:17.28&vc4f8/vblo=5,744.99 2006.218.07:20:17.28&vc4f8/vb=5,4 2006.218.07:20:17.28&vc4f8/vblo=6,752.99 2006.218.07:20:17.28&vc4f8/vb=6,4 2006.218.07:20:17.28&vc4f8/vabw=wide 2006.218.07:20:17.28&vc4f8/vbbw=wide 2006.218.07:20:17.28$vc4f8/valo=1,532.99 2006.218.07:20:17.29#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.218.07:20:17.29#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.218.07:20:17.29#ibcon#ireg 17 cls_cnt 0 2006.218.07:20:17.29#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.218.07:20:17.29#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.218.07:20:17.29#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.218.07:20:17.29#ibcon#enter wrdev, iclass 35, count 0 2006.218.07:20:17.29#ibcon#first serial, iclass 35, count 0 2006.218.07:20:17.29#ibcon#enter sib2, iclass 35, count 0 2006.218.07:20:17.29#ibcon#flushed, iclass 35, count 0 2006.218.07:20:17.29#ibcon#about to write, iclass 35, count 0 2006.218.07:20:17.29#ibcon#wrote, iclass 35, count 0 2006.218.07:20:17.29#ibcon#about to read 3, iclass 35, count 0 2006.218.07:20:17.32#ibcon#read 3, iclass 35, count 0 2006.218.07:20:17.32#ibcon#about to read 4, iclass 35, count 0 2006.218.07:20:17.32#ibcon#read 4, iclass 35, count 0 2006.218.07:20:17.32#ibcon#about to read 5, iclass 35, count 0 2006.218.07:20:17.32#ibcon#read 5, iclass 35, count 0 2006.218.07:20:17.32#ibcon#about to read 6, iclass 35, count 0 2006.218.07:20:17.32#ibcon#read 6, iclass 35, count 0 2006.218.07:20:17.32#ibcon#end of sib2, iclass 35, count 0 2006.218.07:20:17.32#ibcon#*mode == 0, iclass 35, count 0 2006.218.07:20:17.32#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.218.07:20:17.32#ibcon#[26=FRQ=01,532.99\r\n] 2006.218.07:20:17.32#ibcon#*before write, iclass 35, count 0 2006.218.07:20:17.32#ibcon#enter sib2, iclass 35, count 0 2006.218.07:20:17.32#ibcon#flushed, iclass 35, count 0 2006.218.07:20:17.32#ibcon#about to write, iclass 35, count 0 2006.218.07:20:17.32#ibcon#wrote, iclass 35, count 0 2006.218.07:20:17.32#ibcon#about to read 3, iclass 35, count 0 2006.218.07:20:17.36#ibcon#read 3, iclass 35, count 0 2006.218.07:20:17.36#ibcon#about to read 4, iclass 35, count 0 2006.218.07:20:17.36#ibcon#read 4, iclass 35, count 0 2006.218.07:20:17.36#ibcon#about to read 5, iclass 35, count 0 2006.218.07:20:17.36#ibcon#read 5, iclass 35, count 0 2006.218.07:20:17.36#ibcon#about to read 6, iclass 35, count 0 2006.218.07:20:17.36#ibcon#read 6, iclass 35, count 0 2006.218.07:20:17.36#ibcon#end of sib2, iclass 35, count 0 2006.218.07:20:17.36#ibcon#*after write, iclass 35, count 0 2006.218.07:20:17.36#ibcon#*before return 0, iclass 35, count 0 2006.218.07:20:17.36#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.218.07:20:17.36#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.218.07:20:17.36#ibcon#about to clear, iclass 35 cls_cnt 0 2006.218.07:20:17.36#ibcon#cleared, iclass 35 cls_cnt 0 2006.218.07:20:17.36$vc4f8/va=1,5 2006.218.07:20:17.36#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.218.07:20:17.36#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.218.07:20:17.36#ibcon#ireg 11 cls_cnt 2 2006.218.07:20:17.36#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.218.07:20:17.36#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.218.07:20:17.36#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.218.07:20:17.36#ibcon#enter wrdev, iclass 37, count 2 2006.218.07:20:17.36#ibcon#first serial, iclass 37, count 2 2006.218.07:20:17.36#ibcon#enter sib2, iclass 37, count 2 2006.218.07:20:17.36#ibcon#flushed, iclass 37, count 2 2006.218.07:20:17.36#ibcon#about to write, iclass 37, count 2 2006.218.07:20:17.36#ibcon#wrote, iclass 37, count 2 2006.218.07:20:17.36#ibcon#about to read 3, iclass 37, count 2 2006.218.07:20:17.38#ibcon#read 3, iclass 37, count 2 2006.218.07:20:17.38#ibcon#about to read 4, iclass 37, count 2 2006.218.07:20:17.38#ibcon#read 4, iclass 37, count 2 2006.218.07:20:17.38#ibcon#about to read 5, iclass 37, count 2 2006.218.07:20:17.38#ibcon#read 5, iclass 37, count 2 2006.218.07:20:17.38#ibcon#about to read 6, iclass 37, count 2 2006.218.07:20:17.38#ibcon#read 6, iclass 37, count 2 2006.218.07:20:17.38#ibcon#end of sib2, iclass 37, count 2 2006.218.07:20:17.38#ibcon#*mode == 0, iclass 37, count 2 2006.218.07:20:17.38#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.218.07:20:17.38#ibcon#[25=AT01-05\r\n] 2006.218.07:20:17.38#ibcon#*before write, iclass 37, count 2 2006.218.07:20:17.38#ibcon#enter sib2, iclass 37, count 2 2006.218.07:20:17.38#ibcon#flushed, iclass 37, count 2 2006.218.07:20:17.38#ibcon#about to write, iclass 37, count 2 2006.218.07:20:17.38#ibcon#wrote, iclass 37, count 2 2006.218.07:20:17.38#ibcon#about to read 3, iclass 37, count 2 2006.218.07:20:17.42#ibcon#read 3, iclass 37, count 2 2006.218.07:20:17.42#ibcon#about to read 4, iclass 37, count 2 2006.218.07:20:17.42#ibcon#read 4, iclass 37, count 2 2006.218.07:20:17.42#ibcon#about to read 5, iclass 37, count 2 2006.218.07:20:17.42#ibcon#read 5, iclass 37, count 2 2006.218.07:20:17.42#ibcon#about to read 6, iclass 37, count 2 2006.218.07:20:17.42#ibcon#read 6, iclass 37, count 2 2006.218.07:20:17.42#ibcon#end of sib2, iclass 37, count 2 2006.218.07:20:17.42#ibcon#*after write, iclass 37, count 2 2006.218.07:20:17.42#ibcon#*before return 0, iclass 37, count 2 2006.218.07:20:17.42#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.218.07:20:17.42#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.218.07:20:17.42#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.218.07:20:17.42#ibcon#ireg 7 cls_cnt 0 2006.218.07:20:17.42#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.218.07:20:17.53#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.218.07:20:17.53#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.218.07:20:17.53#ibcon#enter wrdev, iclass 37, count 0 2006.218.07:20:17.53#ibcon#first serial, iclass 37, count 0 2006.218.07:20:17.53#ibcon#enter sib2, iclass 37, count 0 2006.218.07:20:17.53#ibcon#flushed, iclass 37, count 0 2006.218.07:20:17.53#ibcon#about to write, iclass 37, count 0 2006.218.07:20:17.53#ibcon#wrote, iclass 37, count 0 2006.218.07:20:17.53#ibcon#about to read 3, iclass 37, count 0 2006.218.07:20:17.55#ibcon#read 3, iclass 37, count 0 2006.218.07:20:17.55#ibcon#about to read 4, iclass 37, count 0 2006.218.07:20:17.55#ibcon#read 4, iclass 37, count 0 2006.218.07:20:17.55#ibcon#about to read 5, iclass 37, count 0 2006.218.07:20:17.55#ibcon#read 5, iclass 37, count 0 2006.218.07:20:17.55#ibcon#about to read 6, iclass 37, count 0 2006.218.07:20:17.55#ibcon#read 6, iclass 37, count 0 2006.218.07:20:17.55#ibcon#end of sib2, iclass 37, count 0 2006.218.07:20:17.55#ibcon#*mode == 0, iclass 37, count 0 2006.218.07:20:17.55#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.218.07:20:17.55#ibcon#[25=USB\r\n] 2006.218.07:20:17.55#ibcon#*before write, iclass 37, count 0 2006.218.07:20:17.55#ibcon#enter sib2, iclass 37, count 0 2006.218.07:20:17.55#ibcon#flushed, iclass 37, count 0 2006.218.07:20:17.55#ibcon#about to write, iclass 37, count 0 2006.218.07:20:17.55#ibcon#wrote, iclass 37, count 0 2006.218.07:20:17.55#ibcon#about to read 3, iclass 37, count 0 2006.218.07:20:17.58#ibcon#read 3, iclass 37, count 0 2006.218.07:20:17.58#ibcon#about to read 4, iclass 37, count 0 2006.218.07:20:17.58#ibcon#read 4, iclass 37, count 0 2006.218.07:20:17.58#ibcon#about to read 5, iclass 37, count 0 2006.218.07:20:17.58#ibcon#read 5, iclass 37, count 0 2006.218.07:20:17.58#ibcon#about to read 6, iclass 37, count 0 2006.218.07:20:17.58#ibcon#read 6, iclass 37, count 0 2006.218.07:20:17.58#ibcon#end of sib2, iclass 37, count 0 2006.218.07:20:17.58#ibcon#*after write, iclass 37, count 0 2006.218.07:20:17.58#ibcon#*before return 0, iclass 37, count 0 2006.218.07:20:17.58#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.218.07:20:17.58#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.218.07:20:17.58#ibcon#about to clear, iclass 37 cls_cnt 0 2006.218.07:20:17.58#ibcon#cleared, iclass 37 cls_cnt 0 2006.218.07:20:17.58$vc4f8/valo=2,572.99 2006.218.07:20:17.58#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.218.07:20:17.58#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.218.07:20:17.58#ibcon#ireg 17 cls_cnt 0 2006.218.07:20:17.58#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.218.07:20:17.58#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.218.07:20:17.58#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.218.07:20:17.58#ibcon#enter wrdev, iclass 39, count 0 2006.218.07:20:17.58#ibcon#first serial, iclass 39, count 0 2006.218.07:20:17.58#ibcon#enter sib2, iclass 39, count 0 2006.218.07:20:17.58#ibcon#flushed, iclass 39, count 0 2006.218.07:20:17.58#ibcon#about to write, iclass 39, count 0 2006.218.07:20:17.58#ibcon#wrote, iclass 39, count 0 2006.218.07:20:17.58#ibcon#about to read 3, iclass 39, count 0 2006.218.07:20:17.61#ibcon#read 3, iclass 39, count 0 2006.218.07:20:17.61#ibcon#about to read 4, iclass 39, count 0 2006.218.07:20:17.61#ibcon#read 4, iclass 39, count 0 2006.218.07:20:17.61#ibcon#about to read 5, iclass 39, count 0 2006.218.07:20:17.61#ibcon#read 5, iclass 39, count 0 2006.218.07:20:17.61#ibcon#about to read 6, iclass 39, count 0 2006.218.07:20:17.61#ibcon#read 6, iclass 39, count 0 2006.218.07:20:17.61#ibcon#end of sib2, iclass 39, count 0 2006.218.07:20:17.61#ibcon#*mode == 0, iclass 39, count 0 2006.218.07:20:17.61#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.218.07:20:17.61#ibcon#[26=FRQ=02,572.99\r\n] 2006.218.07:20:17.61#ibcon#*before write, iclass 39, count 0 2006.218.07:20:17.61#ibcon#enter sib2, iclass 39, count 0 2006.218.07:20:17.61#ibcon#flushed, iclass 39, count 0 2006.218.07:20:17.61#ibcon#about to write, iclass 39, count 0 2006.218.07:20:17.61#ibcon#wrote, iclass 39, count 0 2006.218.07:20:17.61#ibcon#about to read 3, iclass 39, count 0 2006.218.07:20:17.65#ibcon#read 3, iclass 39, count 0 2006.218.07:20:17.65#ibcon#about to read 4, iclass 39, count 0 2006.218.07:20:17.65#ibcon#read 4, iclass 39, count 0 2006.218.07:20:17.65#ibcon#about to read 5, iclass 39, count 0 2006.218.07:20:17.65#ibcon#read 5, iclass 39, count 0 2006.218.07:20:17.65#ibcon#about to read 6, iclass 39, count 0 2006.218.07:20:17.65#ibcon#read 6, iclass 39, count 0 2006.218.07:20:17.65#ibcon#end of sib2, iclass 39, count 0 2006.218.07:20:17.65#ibcon#*after write, iclass 39, count 0 2006.218.07:20:17.65#ibcon#*before return 0, iclass 39, count 0 2006.218.07:20:17.65#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.218.07:20:17.65#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.218.07:20:17.65#ibcon#about to clear, iclass 39 cls_cnt 0 2006.218.07:20:17.65#ibcon#cleared, iclass 39 cls_cnt 0 2006.218.07:20:17.65$vc4f8/va=2,4 2006.218.07:20:17.65#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.218.07:20:17.65#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.218.07:20:17.65#ibcon#ireg 11 cls_cnt 2 2006.218.07:20:17.65#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.218.07:20:17.70#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.218.07:20:17.70#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.218.07:20:17.70#ibcon#enter wrdev, iclass 3, count 2 2006.218.07:20:17.70#ibcon#first serial, iclass 3, count 2 2006.218.07:20:17.70#ibcon#enter sib2, iclass 3, count 2 2006.218.07:20:17.70#ibcon#flushed, iclass 3, count 2 2006.218.07:20:17.70#ibcon#about to write, iclass 3, count 2 2006.218.07:20:17.70#ibcon#wrote, iclass 3, count 2 2006.218.07:20:17.70#ibcon#about to read 3, iclass 3, count 2 2006.218.07:20:17.72#ibcon#read 3, iclass 3, count 2 2006.218.07:20:17.72#ibcon#about to read 4, iclass 3, count 2 2006.218.07:20:17.72#ibcon#read 4, iclass 3, count 2 2006.218.07:20:17.72#ibcon#about to read 5, iclass 3, count 2 2006.218.07:20:17.72#ibcon#read 5, iclass 3, count 2 2006.218.07:20:17.72#ibcon#about to read 6, iclass 3, count 2 2006.218.07:20:17.72#ibcon#read 6, iclass 3, count 2 2006.218.07:20:17.72#ibcon#end of sib2, iclass 3, count 2 2006.218.07:20:17.72#ibcon#*mode == 0, iclass 3, count 2 2006.218.07:20:17.72#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.218.07:20:17.72#ibcon#[25=AT02-04\r\n] 2006.218.07:20:17.72#ibcon#*before write, iclass 3, count 2 2006.218.07:20:17.72#ibcon#enter sib2, iclass 3, count 2 2006.218.07:20:17.72#ibcon#flushed, iclass 3, count 2 2006.218.07:20:17.72#ibcon#about to write, iclass 3, count 2 2006.218.07:20:17.72#ibcon#wrote, iclass 3, count 2 2006.218.07:20:17.72#ibcon#about to read 3, iclass 3, count 2 2006.218.07:20:17.75#ibcon#read 3, iclass 3, count 2 2006.218.07:20:17.75#ibcon#about to read 4, iclass 3, count 2 2006.218.07:20:17.75#ibcon#read 4, iclass 3, count 2 2006.218.07:20:17.75#ibcon#about to read 5, iclass 3, count 2 2006.218.07:20:17.75#ibcon#read 5, iclass 3, count 2 2006.218.07:20:17.75#ibcon#about to read 6, iclass 3, count 2 2006.218.07:20:17.75#ibcon#read 6, iclass 3, count 2 2006.218.07:20:17.75#ibcon#end of sib2, iclass 3, count 2 2006.218.07:20:17.75#ibcon#*after write, iclass 3, count 2 2006.218.07:20:17.75#ibcon#*before return 0, iclass 3, count 2 2006.218.07:20:17.75#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.218.07:20:17.75#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.218.07:20:17.75#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.218.07:20:17.75#ibcon#ireg 7 cls_cnt 0 2006.218.07:20:17.75#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.218.07:20:17.87#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.218.07:20:17.87#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.218.07:20:17.87#ibcon#enter wrdev, iclass 3, count 0 2006.218.07:20:17.87#ibcon#first serial, iclass 3, count 0 2006.218.07:20:17.87#ibcon#enter sib2, iclass 3, count 0 2006.218.07:20:17.87#ibcon#flushed, iclass 3, count 0 2006.218.07:20:17.87#ibcon#about to write, iclass 3, count 0 2006.218.07:20:17.87#ibcon#wrote, iclass 3, count 0 2006.218.07:20:17.87#ibcon#about to read 3, iclass 3, count 0 2006.218.07:20:17.89#ibcon#read 3, iclass 3, count 0 2006.218.07:20:17.89#ibcon#about to read 4, iclass 3, count 0 2006.218.07:20:17.89#ibcon#read 4, iclass 3, count 0 2006.218.07:20:17.89#ibcon#about to read 5, iclass 3, count 0 2006.218.07:20:17.89#ibcon#read 5, iclass 3, count 0 2006.218.07:20:17.89#ibcon#about to read 6, iclass 3, count 0 2006.218.07:20:17.89#ibcon#read 6, iclass 3, count 0 2006.218.07:20:17.89#ibcon#end of sib2, iclass 3, count 0 2006.218.07:20:17.89#ibcon#*mode == 0, iclass 3, count 0 2006.218.07:20:17.89#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.218.07:20:17.89#ibcon#[25=USB\r\n] 2006.218.07:20:17.89#ibcon#*before write, iclass 3, count 0 2006.218.07:20:17.89#ibcon#enter sib2, iclass 3, count 0 2006.218.07:20:17.89#ibcon#flushed, iclass 3, count 0 2006.218.07:20:17.89#ibcon#about to write, iclass 3, count 0 2006.218.07:20:17.89#ibcon#wrote, iclass 3, count 0 2006.218.07:20:17.89#ibcon#about to read 3, iclass 3, count 0 2006.218.07:20:17.92#ibcon#read 3, iclass 3, count 0 2006.218.07:20:17.92#ibcon#about to read 4, iclass 3, count 0 2006.218.07:20:17.92#ibcon#read 4, iclass 3, count 0 2006.218.07:20:17.92#ibcon#about to read 5, iclass 3, count 0 2006.218.07:20:17.92#ibcon#read 5, iclass 3, count 0 2006.218.07:20:17.92#ibcon#about to read 6, iclass 3, count 0 2006.218.07:20:17.92#ibcon#read 6, iclass 3, count 0 2006.218.07:20:17.92#ibcon#end of sib2, iclass 3, count 0 2006.218.07:20:17.92#ibcon#*after write, iclass 3, count 0 2006.218.07:20:17.92#ibcon#*before return 0, iclass 3, count 0 2006.218.07:20:17.92#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.218.07:20:17.92#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.218.07:20:17.92#ibcon#about to clear, iclass 3 cls_cnt 0 2006.218.07:20:17.92#ibcon#cleared, iclass 3 cls_cnt 0 2006.218.07:20:17.92$vc4f8/valo=3,672.99 2006.218.07:20:17.92#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.218.07:20:17.92#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.218.07:20:17.92#ibcon#ireg 17 cls_cnt 0 2006.218.07:20:17.92#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.218.07:20:17.92#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.218.07:20:17.92#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.218.07:20:17.92#ibcon#enter wrdev, iclass 5, count 0 2006.218.07:20:17.92#ibcon#first serial, iclass 5, count 0 2006.218.07:20:17.92#ibcon#enter sib2, iclass 5, count 0 2006.218.07:20:17.92#ibcon#flushed, iclass 5, count 0 2006.218.07:20:17.92#ibcon#about to write, iclass 5, count 0 2006.218.07:20:17.92#ibcon#wrote, iclass 5, count 0 2006.218.07:20:17.92#ibcon#about to read 3, iclass 5, count 0 2006.218.07:20:17.95#ibcon#read 3, iclass 5, count 0 2006.218.07:20:17.95#ibcon#about to read 4, iclass 5, count 0 2006.218.07:20:17.95#ibcon#read 4, iclass 5, count 0 2006.218.07:20:17.95#ibcon#about to read 5, iclass 5, count 0 2006.218.07:20:17.95#ibcon#read 5, iclass 5, count 0 2006.218.07:20:17.95#ibcon#about to read 6, iclass 5, count 0 2006.218.07:20:17.95#ibcon#read 6, iclass 5, count 0 2006.218.07:20:17.95#ibcon#end of sib2, iclass 5, count 0 2006.218.07:20:17.95#ibcon#*mode == 0, iclass 5, count 0 2006.218.07:20:17.95#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.218.07:20:17.95#ibcon#[26=FRQ=03,672.99\r\n] 2006.218.07:20:17.95#ibcon#*before write, iclass 5, count 0 2006.218.07:20:17.95#ibcon#enter sib2, iclass 5, count 0 2006.218.07:20:17.95#ibcon#flushed, iclass 5, count 0 2006.218.07:20:17.95#ibcon#about to write, iclass 5, count 0 2006.218.07:20:17.95#ibcon#wrote, iclass 5, count 0 2006.218.07:20:17.95#ibcon#about to read 3, iclass 5, count 0 2006.218.07:20:17.99#ibcon#read 3, iclass 5, count 0 2006.218.07:20:17.99#ibcon#about to read 4, iclass 5, count 0 2006.218.07:20:17.99#ibcon#read 4, iclass 5, count 0 2006.218.07:20:17.99#ibcon#about to read 5, iclass 5, count 0 2006.218.07:20:17.99#ibcon#read 5, iclass 5, count 0 2006.218.07:20:17.99#ibcon#about to read 6, iclass 5, count 0 2006.218.07:20:17.99#ibcon#read 6, iclass 5, count 0 2006.218.07:20:17.99#ibcon#end of sib2, iclass 5, count 0 2006.218.07:20:17.99#ibcon#*after write, iclass 5, count 0 2006.218.07:20:17.99#ibcon#*before return 0, iclass 5, count 0 2006.218.07:20:17.99#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.218.07:20:17.99#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.218.07:20:17.99#ibcon#about to clear, iclass 5 cls_cnt 0 2006.218.07:20:17.99#ibcon#cleared, iclass 5 cls_cnt 0 2006.218.07:20:17.99$vc4f8/va=3,4 2006.218.07:20:17.99#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.218.07:20:17.99#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.218.07:20:17.99#ibcon#ireg 11 cls_cnt 2 2006.218.07:20:17.99#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.218.07:20:18.04#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.218.07:20:18.04#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.218.07:20:18.04#ibcon#enter wrdev, iclass 7, count 2 2006.218.07:20:18.04#ibcon#first serial, iclass 7, count 2 2006.218.07:20:18.04#ibcon#enter sib2, iclass 7, count 2 2006.218.07:20:18.04#ibcon#flushed, iclass 7, count 2 2006.218.07:20:18.04#ibcon#about to write, iclass 7, count 2 2006.218.07:20:18.04#ibcon#wrote, iclass 7, count 2 2006.218.07:20:18.04#ibcon#about to read 3, iclass 7, count 2 2006.218.07:20:18.06#ibcon#read 3, iclass 7, count 2 2006.218.07:20:18.06#ibcon#about to read 4, iclass 7, count 2 2006.218.07:20:18.06#ibcon#read 4, iclass 7, count 2 2006.218.07:20:18.06#ibcon#about to read 5, iclass 7, count 2 2006.218.07:20:18.06#ibcon#read 5, iclass 7, count 2 2006.218.07:20:18.06#ibcon#about to read 6, iclass 7, count 2 2006.218.07:20:18.06#ibcon#read 6, iclass 7, count 2 2006.218.07:20:18.06#ibcon#end of sib2, iclass 7, count 2 2006.218.07:20:18.06#ibcon#*mode == 0, iclass 7, count 2 2006.218.07:20:18.06#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.218.07:20:18.06#ibcon#[25=AT03-04\r\n] 2006.218.07:20:18.06#ibcon#*before write, iclass 7, count 2 2006.218.07:20:18.06#ibcon#enter sib2, iclass 7, count 2 2006.218.07:20:18.06#ibcon#flushed, iclass 7, count 2 2006.218.07:20:18.06#ibcon#about to write, iclass 7, count 2 2006.218.07:20:18.06#ibcon#wrote, iclass 7, count 2 2006.218.07:20:18.06#ibcon#about to read 3, iclass 7, count 2 2006.218.07:20:18.09#ibcon#read 3, iclass 7, count 2 2006.218.07:20:18.09#ibcon#about to read 4, iclass 7, count 2 2006.218.07:20:18.09#ibcon#read 4, iclass 7, count 2 2006.218.07:20:18.09#ibcon#about to read 5, iclass 7, count 2 2006.218.07:20:18.09#ibcon#read 5, iclass 7, count 2 2006.218.07:20:18.09#ibcon#about to read 6, iclass 7, count 2 2006.218.07:20:18.09#ibcon#read 6, iclass 7, count 2 2006.218.07:20:18.09#ibcon#end of sib2, iclass 7, count 2 2006.218.07:20:18.09#ibcon#*after write, iclass 7, count 2 2006.218.07:20:18.09#ibcon#*before return 0, iclass 7, count 2 2006.218.07:20:18.09#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.218.07:20:18.09#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.218.07:20:18.09#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.218.07:20:18.09#ibcon#ireg 7 cls_cnt 0 2006.218.07:20:18.09#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.218.07:20:18.21#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.218.07:20:18.21#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.218.07:20:18.21#ibcon#enter wrdev, iclass 7, count 0 2006.218.07:20:18.21#ibcon#first serial, iclass 7, count 0 2006.218.07:20:18.21#ibcon#enter sib2, iclass 7, count 0 2006.218.07:20:18.21#ibcon#flushed, iclass 7, count 0 2006.218.07:20:18.21#ibcon#about to write, iclass 7, count 0 2006.218.07:20:18.21#ibcon#wrote, iclass 7, count 0 2006.218.07:20:18.21#ibcon#about to read 3, iclass 7, count 0 2006.218.07:20:18.25#ibcon#read 3, iclass 7, count 0 2006.218.07:20:18.25#ibcon#about to read 4, iclass 7, count 0 2006.218.07:20:18.25#ibcon#read 4, iclass 7, count 0 2006.218.07:20:18.25#ibcon#about to read 5, iclass 7, count 0 2006.218.07:20:18.25#ibcon#read 5, iclass 7, count 0 2006.218.07:20:18.25#ibcon#about to read 6, iclass 7, count 0 2006.218.07:20:18.25#ibcon#read 6, iclass 7, count 0 2006.218.07:20:18.25#ibcon#end of sib2, iclass 7, count 0 2006.218.07:20:18.25#ibcon#*mode == 0, iclass 7, count 0 2006.218.07:20:18.25#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.218.07:20:18.25#ibcon#[25=USB\r\n] 2006.218.07:20:18.25#ibcon#*before write, iclass 7, count 0 2006.218.07:20:18.25#ibcon#enter sib2, iclass 7, count 0 2006.218.07:20:18.25#ibcon#flushed, iclass 7, count 0 2006.218.07:20:18.25#ibcon#about to write, iclass 7, count 0 2006.218.07:20:18.25#ibcon#wrote, iclass 7, count 0 2006.218.07:20:18.25#ibcon#about to read 3, iclass 7, count 0 2006.218.07:20:18.27#ibcon#read 3, iclass 7, count 0 2006.218.07:20:18.27#ibcon#about to read 4, iclass 7, count 0 2006.218.07:20:18.27#ibcon#read 4, iclass 7, count 0 2006.218.07:20:18.27#ibcon#about to read 5, iclass 7, count 0 2006.218.07:20:18.27#ibcon#read 5, iclass 7, count 0 2006.218.07:20:18.27#ibcon#about to read 6, iclass 7, count 0 2006.218.07:20:18.27#ibcon#read 6, iclass 7, count 0 2006.218.07:20:18.27#ibcon#end of sib2, iclass 7, count 0 2006.218.07:20:18.27#ibcon#*after write, iclass 7, count 0 2006.218.07:20:18.27#ibcon#*before return 0, iclass 7, count 0 2006.218.07:20:18.27#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.218.07:20:18.27#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.218.07:20:18.27#ibcon#about to clear, iclass 7 cls_cnt 0 2006.218.07:20:18.27#ibcon#cleared, iclass 7 cls_cnt 0 2006.218.07:20:18.27$vc4f8/valo=4,832.99 2006.218.07:20:18.27#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.218.07:20:18.27#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.218.07:20:18.27#ibcon#ireg 17 cls_cnt 0 2006.218.07:20:18.27#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.218.07:20:18.27#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.218.07:20:18.27#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.218.07:20:18.27#ibcon#enter wrdev, iclass 11, count 0 2006.218.07:20:18.27#ibcon#first serial, iclass 11, count 0 2006.218.07:20:18.27#ibcon#enter sib2, iclass 11, count 0 2006.218.07:20:18.27#ibcon#flushed, iclass 11, count 0 2006.218.07:20:18.27#ibcon#about to write, iclass 11, count 0 2006.218.07:20:18.27#ibcon#wrote, iclass 11, count 0 2006.218.07:20:18.27#ibcon#about to read 3, iclass 11, count 0 2006.218.07:20:18.29#ibcon#read 3, iclass 11, count 0 2006.218.07:20:18.29#ibcon#about to read 4, iclass 11, count 0 2006.218.07:20:18.29#ibcon#read 4, iclass 11, count 0 2006.218.07:20:18.29#ibcon#about to read 5, iclass 11, count 0 2006.218.07:20:18.29#ibcon#read 5, iclass 11, count 0 2006.218.07:20:18.29#ibcon#about to read 6, iclass 11, count 0 2006.218.07:20:18.29#ibcon#read 6, iclass 11, count 0 2006.218.07:20:18.29#ibcon#end of sib2, iclass 11, count 0 2006.218.07:20:18.29#ibcon#*mode == 0, iclass 11, count 0 2006.218.07:20:18.29#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.218.07:20:18.29#ibcon#[26=FRQ=04,832.99\r\n] 2006.218.07:20:18.29#ibcon#*before write, iclass 11, count 0 2006.218.07:20:18.29#ibcon#enter sib2, iclass 11, count 0 2006.218.07:20:18.29#ibcon#flushed, iclass 11, count 0 2006.218.07:20:18.29#ibcon#about to write, iclass 11, count 0 2006.218.07:20:18.29#ibcon#wrote, iclass 11, count 0 2006.218.07:20:18.29#ibcon#about to read 3, iclass 11, count 0 2006.218.07:20:18.33#ibcon#read 3, iclass 11, count 0 2006.218.07:20:18.33#ibcon#about to read 4, iclass 11, count 0 2006.218.07:20:18.33#ibcon#read 4, iclass 11, count 0 2006.218.07:20:18.33#ibcon#about to read 5, iclass 11, count 0 2006.218.07:20:18.33#ibcon#read 5, iclass 11, count 0 2006.218.07:20:18.33#ibcon#about to read 6, iclass 11, count 0 2006.218.07:20:18.33#ibcon#read 6, iclass 11, count 0 2006.218.07:20:18.33#ibcon#end of sib2, iclass 11, count 0 2006.218.07:20:18.33#ibcon#*after write, iclass 11, count 0 2006.218.07:20:18.33#ibcon#*before return 0, iclass 11, count 0 2006.218.07:20:18.33#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.218.07:20:18.33#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.218.07:20:18.33#ibcon#about to clear, iclass 11 cls_cnt 0 2006.218.07:20:18.33#ibcon#cleared, iclass 11 cls_cnt 0 2006.218.07:20:18.33$vc4f8/va=4,4 2006.218.07:20:18.33#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.218.07:20:18.33#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.218.07:20:18.33#ibcon#ireg 11 cls_cnt 2 2006.218.07:20:18.33#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.218.07:20:18.39#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.218.07:20:18.39#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.218.07:20:18.39#ibcon#enter wrdev, iclass 13, count 2 2006.218.07:20:18.39#ibcon#first serial, iclass 13, count 2 2006.218.07:20:18.39#ibcon#enter sib2, iclass 13, count 2 2006.218.07:20:18.39#ibcon#flushed, iclass 13, count 2 2006.218.07:20:18.39#ibcon#about to write, iclass 13, count 2 2006.218.07:20:18.39#ibcon#wrote, iclass 13, count 2 2006.218.07:20:18.39#ibcon#about to read 3, iclass 13, count 2 2006.218.07:20:18.41#ibcon#read 3, iclass 13, count 2 2006.218.07:20:18.41#ibcon#about to read 4, iclass 13, count 2 2006.218.07:20:18.41#ibcon#read 4, iclass 13, count 2 2006.218.07:20:18.41#ibcon#about to read 5, iclass 13, count 2 2006.218.07:20:18.41#ibcon#read 5, iclass 13, count 2 2006.218.07:20:18.41#ibcon#about to read 6, iclass 13, count 2 2006.218.07:20:18.41#ibcon#read 6, iclass 13, count 2 2006.218.07:20:18.41#ibcon#end of sib2, iclass 13, count 2 2006.218.07:20:18.41#ibcon#*mode == 0, iclass 13, count 2 2006.218.07:20:18.41#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.218.07:20:18.41#ibcon#[25=AT04-04\r\n] 2006.218.07:20:18.41#ibcon#*before write, iclass 13, count 2 2006.218.07:20:18.41#ibcon#enter sib2, iclass 13, count 2 2006.218.07:20:18.41#ibcon#flushed, iclass 13, count 2 2006.218.07:20:18.41#ibcon#about to write, iclass 13, count 2 2006.218.07:20:18.41#ibcon#wrote, iclass 13, count 2 2006.218.07:20:18.41#ibcon#about to read 3, iclass 13, count 2 2006.218.07:20:18.44#ibcon#read 3, iclass 13, count 2 2006.218.07:20:18.44#ibcon#about to read 4, iclass 13, count 2 2006.218.07:20:18.44#ibcon#read 4, iclass 13, count 2 2006.218.07:20:18.44#ibcon#about to read 5, iclass 13, count 2 2006.218.07:20:18.44#ibcon#read 5, iclass 13, count 2 2006.218.07:20:18.44#ibcon#about to read 6, iclass 13, count 2 2006.218.07:20:18.44#ibcon#read 6, iclass 13, count 2 2006.218.07:20:18.44#ibcon#end of sib2, iclass 13, count 2 2006.218.07:20:18.44#ibcon#*after write, iclass 13, count 2 2006.218.07:20:18.44#ibcon#*before return 0, iclass 13, count 2 2006.218.07:20:18.44#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.218.07:20:18.44#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.218.07:20:18.44#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.218.07:20:18.44#ibcon#ireg 7 cls_cnt 0 2006.218.07:20:18.44#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.218.07:20:18.56#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.218.07:20:18.56#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.218.07:20:18.56#ibcon#enter wrdev, iclass 13, count 0 2006.218.07:20:18.56#ibcon#first serial, iclass 13, count 0 2006.218.07:20:18.56#ibcon#enter sib2, iclass 13, count 0 2006.218.07:20:18.56#ibcon#flushed, iclass 13, count 0 2006.218.07:20:18.56#ibcon#about to write, iclass 13, count 0 2006.218.07:20:18.56#ibcon#wrote, iclass 13, count 0 2006.218.07:20:18.56#ibcon#about to read 3, iclass 13, count 0 2006.218.07:20:18.58#ibcon#read 3, iclass 13, count 0 2006.218.07:20:18.58#ibcon#about to read 4, iclass 13, count 0 2006.218.07:20:18.58#ibcon#read 4, iclass 13, count 0 2006.218.07:20:18.58#ibcon#about to read 5, iclass 13, count 0 2006.218.07:20:18.58#ibcon#read 5, iclass 13, count 0 2006.218.07:20:18.58#ibcon#about to read 6, iclass 13, count 0 2006.218.07:20:18.58#ibcon#read 6, iclass 13, count 0 2006.218.07:20:18.58#ibcon#end of sib2, iclass 13, count 0 2006.218.07:20:18.58#ibcon#*mode == 0, iclass 13, count 0 2006.218.07:20:18.58#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.218.07:20:18.58#ibcon#[25=USB\r\n] 2006.218.07:20:18.58#ibcon#*before write, iclass 13, count 0 2006.218.07:20:18.58#ibcon#enter sib2, iclass 13, count 0 2006.218.07:20:18.58#ibcon#flushed, iclass 13, count 0 2006.218.07:20:18.58#ibcon#about to write, iclass 13, count 0 2006.218.07:20:18.58#ibcon#wrote, iclass 13, count 0 2006.218.07:20:18.58#ibcon#about to read 3, iclass 13, count 0 2006.218.07:20:18.61#ibcon#read 3, iclass 13, count 0 2006.218.07:20:18.61#ibcon#about to read 4, iclass 13, count 0 2006.218.07:20:18.61#ibcon#read 4, iclass 13, count 0 2006.218.07:20:18.61#ibcon#about to read 5, iclass 13, count 0 2006.218.07:20:18.61#ibcon#read 5, iclass 13, count 0 2006.218.07:20:18.61#ibcon#about to read 6, iclass 13, count 0 2006.218.07:20:18.61#ibcon#read 6, iclass 13, count 0 2006.218.07:20:18.61#ibcon#end of sib2, iclass 13, count 0 2006.218.07:20:18.61#ibcon#*after write, iclass 13, count 0 2006.218.07:20:18.61#ibcon#*before return 0, iclass 13, count 0 2006.218.07:20:18.61#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.218.07:20:18.61#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.218.07:20:18.61#ibcon#about to clear, iclass 13 cls_cnt 0 2006.218.07:20:18.61#ibcon#cleared, iclass 13 cls_cnt 0 2006.218.07:20:18.61$vc4f8/valo=5,652.99 2006.218.07:20:18.61#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.218.07:20:18.61#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.218.07:20:18.61#ibcon#ireg 17 cls_cnt 0 2006.218.07:20:18.61#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.218.07:20:18.61#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.218.07:20:18.61#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.218.07:20:18.61#ibcon#enter wrdev, iclass 15, count 0 2006.218.07:20:18.61#ibcon#first serial, iclass 15, count 0 2006.218.07:20:18.61#ibcon#enter sib2, iclass 15, count 0 2006.218.07:20:18.61#ibcon#flushed, iclass 15, count 0 2006.218.07:20:18.61#ibcon#about to write, iclass 15, count 0 2006.218.07:20:18.61#ibcon#wrote, iclass 15, count 0 2006.218.07:20:18.61#ibcon#about to read 3, iclass 15, count 0 2006.218.07:20:18.63#ibcon#read 3, iclass 15, count 0 2006.218.07:20:18.63#ibcon#about to read 4, iclass 15, count 0 2006.218.07:20:18.63#ibcon#read 4, iclass 15, count 0 2006.218.07:20:18.63#ibcon#about to read 5, iclass 15, count 0 2006.218.07:20:18.63#ibcon#read 5, iclass 15, count 0 2006.218.07:20:18.63#ibcon#about to read 6, iclass 15, count 0 2006.218.07:20:18.63#ibcon#read 6, iclass 15, count 0 2006.218.07:20:18.63#ibcon#end of sib2, iclass 15, count 0 2006.218.07:20:18.63#ibcon#*mode == 0, iclass 15, count 0 2006.218.07:20:18.63#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.218.07:20:18.63#ibcon#[26=FRQ=05,652.99\r\n] 2006.218.07:20:18.63#ibcon#*before write, iclass 15, count 0 2006.218.07:20:18.63#ibcon#enter sib2, iclass 15, count 0 2006.218.07:20:18.63#ibcon#flushed, iclass 15, count 0 2006.218.07:20:18.63#ibcon#about to write, iclass 15, count 0 2006.218.07:20:18.63#ibcon#wrote, iclass 15, count 0 2006.218.07:20:18.63#ibcon#about to read 3, iclass 15, count 0 2006.218.07:20:18.67#ibcon#read 3, iclass 15, count 0 2006.218.07:20:18.67#ibcon#about to read 4, iclass 15, count 0 2006.218.07:20:18.67#ibcon#read 4, iclass 15, count 0 2006.218.07:20:18.67#ibcon#about to read 5, iclass 15, count 0 2006.218.07:20:18.67#ibcon#read 5, iclass 15, count 0 2006.218.07:20:18.67#ibcon#about to read 6, iclass 15, count 0 2006.218.07:20:18.67#ibcon#read 6, iclass 15, count 0 2006.218.07:20:18.67#ibcon#end of sib2, iclass 15, count 0 2006.218.07:20:18.67#ibcon#*after write, iclass 15, count 0 2006.218.07:20:18.67#ibcon#*before return 0, iclass 15, count 0 2006.218.07:20:18.67#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.218.07:20:18.67#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.218.07:20:18.67#ibcon#about to clear, iclass 15 cls_cnt 0 2006.218.07:20:18.67#ibcon#cleared, iclass 15 cls_cnt 0 2006.218.07:20:18.67$vc4f8/va=5,7 2006.218.07:20:18.67#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.218.07:20:18.67#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.218.07:20:18.67#ibcon#ireg 11 cls_cnt 2 2006.218.07:20:18.67#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.218.07:20:18.73#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.218.07:20:18.73#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.218.07:20:18.73#ibcon#enter wrdev, iclass 17, count 2 2006.218.07:20:18.73#ibcon#first serial, iclass 17, count 2 2006.218.07:20:18.73#ibcon#enter sib2, iclass 17, count 2 2006.218.07:20:18.73#ibcon#flushed, iclass 17, count 2 2006.218.07:20:18.73#ibcon#about to write, iclass 17, count 2 2006.218.07:20:18.73#ibcon#wrote, iclass 17, count 2 2006.218.07:20:18.73#ibcon#about to read 3, iclass 17, count 2 2006.218.07:20:18.75#ibcon#read 3, iclass 17, count 2 2006.218.07:20:18.75#ibcon#about to read 4, iclass 17, count 2 2006.218.07:20:18.75#ibcon#read 4, iclass 17, count 2 2006.218.07:20:18.75#ibcon#about to read 5, iclass 17, count 2 2006.218.07:20:18.75#ibcon#read 5, iclass 17, count 2 2006.218.07:20:18.75#ibcon#about to read 6, iclass 17, count 2 2006.218.07:20:18.75#ibcon#read 6, iclass 17, count 2 2006.218.07:20:18.75#ibcon#end of sib2, iclass 17, count 2 2006.218.07:20:18.75#ibcon#*mode == 0, iclass 17, count 2 2006.218.07:20:18.75#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.218.07:20:18.75#ibcon#[25=AT05-07\r\n] 2006.218.07:20:18.75#ibcon#*before write, iclass 17, count 2 2006.218.07:20:18.75#ibcon#enter sib2, iclass 17, count 2 2006.218.07:20:18.75#ibcon#flushed, iclass 17, count 2 2006.218.07:20:18.75#ibcon#about to write, iclass 17, count 2 2006.218.07:20:18.75#ibcon#wrote, iclass 17, count 2 2006.218.07:20:18.75#ibcon#about to read 3, iclass 17, count 2 2006.218.07:20:18.78#ibcon#read 3, iclass 17, count 2 2006.218.07:20:18.78#ibcon#about to read 4, iclass 17, count 2 2006.218.07:20:18.78#ibcon#read 4, iclass 17, count 2 2006.218.07:20:18.78#ibcon#about to read 5, iclass 17, count 2 2006.218.07:20:18.78#ibcon#read 5, iclass 17, count 2 2006.218.07:20:18.78#ibcon#about to read 6, iclass 17, count 2 2006.218.07:20:18.78#ibcon#read 6, iclass 17, count 2 2006.218.07:20:18.78#ibcon#end of sib2, iclass 17, count 2 2006.218.07:20:18.78#ibcon#*after write, iclass 17, count 2 2006.218.07:20:18.78#ibcon#*before return 0, iclass 17, count 2 2006.218.07:20:18.78#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.218.07:20:18.78#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.218.07:20:18.78#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.218.07:20:18.78#ibcon#ireg 7 cls_cnt 0 2006.218.07:20:18.78#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.218.07:20:18.90#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.218.07:20:18.90#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.218.07:20:18.90#ibcon#enter wrdev, iclass 17, count 0 2006.218.07:20:18.90#ibcon#first serial, iclass 17, count 0 2006.218.07:20:18.90#ibcon#enter sib2, iclass 17, count 0 2006.218.07:20:18.90#ibcon#flushed, iclass 17, count 0 2006.218.07:20:18.90#ibcon#about to write, iclass 17, count 0 2006.218.07:20:18.90#ibcon#wrote, iclass 17, count 0 2006.218.07:20:18.90#ibcon#about to read 3, iclass 17, count 0 2006.218.07:20:18.92#ibcon#read 3, iclass 17, count 0 2006.218.07:20:18.92#ibcon#about to read 4, iclass 17, count 0 2006.218.07:20:18.92#ibcon#read 4, iclass 17, count 0 2006.218.07:20:18.92#ibcon#about to read 5, iclass 17, count 0 2006.218.07:20:18.92#ibcon#read 5, iclass 17, count 0 2006.218.07:20:18.92#ibcon#about to read 6, iclass 17, count 0 2006.218.07:20:18.92#ibcon#read 6, iclass 17, count 0 2006.218.07:20:18.92#ibcon#end of sib2, iclass 17, count 0 2006.218.07:20:18.92#ibcon#*mode == 0, iclass 17, count 0 2006.218.07:20:18.92#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.218.07:20:18.92#ibcon#[25=USB\r\n] 2006.218.07:20:18.92#ibcon#*before write, iclass 17, count 0 2006.218.07:20:18.92#ibcon#enter sib2, iclass 17, count 0 2006.218.07:20:18.92#ibcon#flushed, iclass 17, count 0 2006.218.07:20:18.92#ibcon#about to write, iclass 17, count 0 2006.218.07:20:18.92#ibcon#wrote, iclass 17, count 0 2006.218.07:20:18.92#ibcon#about to read 3, iclass 17, count 0 2006.218.07:20:18.95#ibcon#read 3, iclass 17, count 0 2006.218.07:20:18.95#ibcon#about to read 4, iclass 17, count 0 2006.218.07:20:18.95#ibcon#read 4, iclass 17, count 0 2006.218.07:20:18.95#ibcon#about to read 5, iclass 17, count 0 2006.218.07:20:18.95#ibcon#read 5, iclass 17, count 0 2006.218.07:20:18.95#ibcon#about to read 6, iclass 17, count 0 2006.218.07:20:18.95#ibcon#read 6, iclass 17, count 0 2006.218.07:20:18.95#ibcon#end of sib2, iclass 17, count 0 2006.218.07:20:18.95#ibcon#*after write, iclass 17, count 0 2006.218.07:20:18.95#ibcon#*before return 0, iclass 17, count 0 2006.218.07:20:18.95#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.218.07:20:18.95#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.218.07:20:18.95#ibcon#about to clear, iclass 17 cls_cnt 0 2006.218.07:20:18.95#ibcon#cleared, iclass 17 cls_cnt 0 2006.218.07:20:18.95$vc4f8/valo=6,772.99 2006.218.07:20:18.95#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.218.07:20:18.95#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.218.07:20:18.95#ibcon#ireg 17 cls_cnt 0 2006.218.07:20:18.95#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.218.07:20:18.95#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.218.07:20:18.95#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.218.07:20:18.95#ibcon#enter wrdev, iclass 19, count 0 2006.218.07:20:18.95#ibcon#first serial, iclass 19, count 0 2006.218.07:20:18.95#ibcon#enter sib2, iclass 19, count 0 2006.218.07:20:18.95#ibcon#flushed, iclass 19, count 0 2006.218.07:20:18.95#ibcon#about to write, iclass 19, count 0 2006.218.07:20:18.95#ibcon#wrote, iclass 19, count 0 2006.218.07:20:18.95#ibcon#about to read 3, iclass 19, count 0 2006.218.07:20:18.98#ibcon#read 3, iclass 19, count 0 2006.218.07:20:18.98#ibcon#about to read 4, iclass 19, count 0 2006.218.07:20:18.98#ibcon#read 4, iclass 19, count 0 2006.218.07:20:18.98#ibcon#about to read 5, iclass 19, count 0 2006.218.07:20:18.98#ibcon#read 5, iclass 19, count 0 2006.218.07:20:18.98#ibcon#about to read 6, iclass 19, count 0 2006.218.07:20:18.98#ibcon#read 6, iclass 19, count 0 2006.218.07:20:18.98#ibcon#end of sib2, iclass 19, count 0 2006.218.07:20:18.98#ibcon#*mode == 0, iclass 19, count 0 2006.218.07:20:18.98#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.218.07:20:18.98#ibcon#[26=FRQ=06,772.99\r\n] 2006.218.07:20:18.98#ibcon#*before write, iclass 19, count 0 2006.218.07:20:18.98#ibcon#enter sib2, iclass 19, count 0 2006.218.07:20:18.98#ibcon#flushed, iclass 19, count 0 2006.218.07:20:18.98#ibcon#about to write, iclass 19, count 0 2006.218.07:20:18.98#ibcon#wrote, iclass 19, count 0 2006.218.07:20:18.98#ibcon#about to read 3, iclass 19, count 0 2006.218.07:20:19.02#ibcon#read 3, iclass 19, count 0 2006.218.07:20:19.02#ibcon#about to read 4, iclass 19, count 0 2006.218.07:20:19.02#ibcon#read 4, iclass 19, count 0 2006.218.07:20:19.02#ibcon#about to read 5, iclass 19, count 0 2006.218.07:20:19.02#ibcon#read 5, iclass 19, count 0 2006.218.07:20:19.02#ibcon#about to read 6, iclass 19, count 0 2006.218.07:20:19.02#ibcon#read 6, iclass 19, count 0 2006.218.07:20:19.02#ibcon#end of sib2, iclass 19, count 0 2006.218.07:20:19.02#ibcon#*after write, iclass 19, count 0 2006.218.07:20:19.02#ibcon#*before return 0, iclass 19, count 0 2006.218.07:20:19.02#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.218.07:20:19.02#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.218.07:20:19.02#ibcon#about to clear, iclass 19 cls_cnt 0 2006.218.07:20:19.02#ibcon#cleared, iclass 19 cls_cnt 0 2006.218.07:20:19.02$vc4f8/va=6,6 2006.218.07:20:19.02#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.218.07:20:19.02#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.218.07:20:19.02#ibcon#ireg 11 cls_cnt 2 2006.218.07:20:19.02#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.218.07:20:19.07#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.218.07:20:19.07#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.218.07:20:19.07#ibcon#enter wrdev, iclass 21, count 2 2006.218.07:20:19.07#ibcon#first serial, iclass 21, count 2 2006.218.07:20:19.07#ibcon#enter sib2, iclass 21, count 2 2006.218.07:20:19.07#ibcon#flushed, iclass 21, count 2 2006.218.07:20:19.07#ibcon#about to write, iclass 21, count 2 2006.218.07:20:19.07#ibcon#wrote, iclass 21, count 2 2006.218.07:20:19.07#ibcon#about to read 3, iclass 21, count 2 2006.218.07:20:19.09#ibcon#read 3, iclass 21, count 2 2006.218.07:20:19.09#ibcon#about to read 4, iclass 21, count 2 2006.218.07:20:19.09#ibcon#read 4, iclass 21, count 2 2006.218.07:20:19.09#ibcon#about to read 5, iclass 21, count 2 2006.218.07:20:19.09#ibcon#read 5, iclass 21, count 2 2006.218.07:20:19.09#ibcon#about to read 6, iclass 21, count 2 2006.218.07:20:19.09#ibcon#read 6, iclass 21, count 2 2006.218.07:20:19.09#ibcon#end of sib2, iclass 21, count 2 2006.218.07:20:19.09#ibcon#*mode == 0, iclass 21, count 2 2006.218.07:20:19.09#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.218.07:20:19.09#ibcon#[25=AT06-06\r\n] 2006.218.07:20:19.09#ibcon#*before write, iclass 21, count 2 2006.218.07:20:19.09#ibcon#enter sib2, iclass 21, count 2 2006.218.07:20:19.09#ibcon#flushed, iclass 21, count 2 2006.218.07:20:19.09#ibcon#about to write, iclass 21, count 2 2006.218.07:20:19.09#ibcon#wrote, iclass 21, count 2 2006.218.07:20:19.09#ibcon#about to read 3, iclass 21, count 2 2006.218.07:20:19.12#ibcon#read 3, iclass 21, count 2 2006.218.07:20:19.12#ibcon#about to read 4, iclass 21, count 2 2006.218.07:20:19.12#ibcon#read 4, iclass 21, count 2 2006.218.07:20:19.12#ibcon#about to read 5, iclass 21, count 2 2006.218.07:20:19.12#ibcon#read 5, iclass 21, count 2 2006.218.07:20:19.12#ibcon#about to read 6, iclass 21, count 2 2006.218.07:20:19.12#ibcon#read 6, iclass 21, count 2 2006.218.07:20:19.12#ibcon#end of sib2, iclass 21, count 2 2006.218.07:20:19.12#ibcon#*after write, iclass 21, count 2 2006.218.07:20:19.12#ibcon#*before return 0, iclass 21, count 2 2006.218.07:20:19.12#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.218.07:20:19.12#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.218.07:20:19.12#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.218.07:20:19.12#ibcon#ireg 7 cls_cnt 0 2006.218.07:20:19.12#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.218.07:20:19.24#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.218.07:20:19.24#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.218.07:20:19.24#ibcon#enter wrdev, iclass 21, count 0 2006.218.07:20:19.24#ibcon#first serial, iclass 21, count 0 2006.218.07:20:19.24#ibcon#enter sib2, iclass 21, count 0 2006.218.07:20:19.24#ibcon#flushed, iclass 21, count 0 2006.218.07:20:19.24#ibcon#about to write, iclass 21, count 0 2006.218.07:20:19.24#ibcon#wrote, iclass 21, count 0 2006.218.07:20:19.24#ibcon#about to read 3, iclass 21, count 0 2006.218.07:20:19.26#ibcon#read 3, iclass 21, count 0 2006.218.07:20:19.26#ibcon#about to read 4, iclass 21, count 0 2006.218.07:20:19.26#ibcon#read 4, iclass 21, count 0 2006.218.07:20:19.26#ibcon#about to read 5, iclass 21, count 0 2006.218.07:20:19.26#ibcon#read 5, iclass 21, count 0 2006.218.07:20:19.26#ibcon#about to read 6, iclass 21, count 0 2006.218.07:20:19.26#ibcon#read 6, iclass 21, count 0 2006.218.07:20:19.26#ibcon#end of sib2, iclass 21, count 0 2006.218.07:20:19.26#ibcon#*mode == 0, iclass 21, count 0 2006.218.07:20:19.26#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.218.07:20:19.26#ibcon#[25=USB\r\n] 2006.218.07:20:19.26#ibcon#*before write, iclass 21, count 0 2006.218.07:20:19.26#ibcon#enter sib2, iclass 21, count 0 2006.218.07:20:19.26#ibcon#flushed, iclass 21, count 0 2006.218.07:20:19.26#ibcon#about to write, iclass 21, count 0 2006.218.07:20:19.26#ibcon#wrote, iclass 21, count 0 2006.218.07:20:19.26#ibcon#about to read 3, iclass 21, count 0 2006.218.07:20:19.29#ibcon#read 3, iclass 21, count 0 2006.218.07:20:19.29#ibcon#about to read 4, iclass 21, count 0 2006.218.07:20:19.29#ibcon#read 4, iclass 21, count 0 2006.218.07:20:19.29#ibcon#about to read 5, iclass 21, count 0 2006.218.07:20:19.29#ibcon#read 5, iclass 21, count 0 2006.218.07:20:19.29#ibcon#about to read 6, iclass 21, count 0 2006.218.07:20:19.29#ibcon#read 6, iclass 21, count 0 2006.218.07:20:19.29#ibcon#end of sib2, iclass 21, count 0 2006.218.07:20:19.29#ibcon#*after write, iclass 21, count 0 2006.218.07:20:19.29#ibcon#*before return 0, iclass 21, count 0 2006.218.07:20:19.29#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.218.07:20:19.29#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.218.07:20:19.29#ibcon#about to clear, iclass 21 cls_cnt 0 2006.218.07:20:19.29#ibcon#cleared, iclass 21 cls_cnt 0 2006.218.07:20:19.29$vc4f8/valo=7,832.99 2006.218.07:20:19.29#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.218.07:20:19.29#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.218.07:20:19.29#ibcon#ireg 17 cls_cnt 0 2006.218.07:20:19.29#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.218.07:20:19.29#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.218.07:20:19.29#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.218.07:20:19.29#ibcon#enter wrdev, iclass 23, count 0 2006.218.07:20:19.29#ibcon#first serial, iclass 23, count 0 2006.218.07:20:19.29#ibcon#enter sib2, iclass 23, count 0 2006.218.07:20:19.29#ibcon#flushed, iclass 23, count 0 2006.218.07:20:19.29#ibcon#about to write, iclass 23, count 0 2006.218.07:20:19.29#ibcon#wrote, iclass 23, count 0 2006.218.07:20:19.29#ibcon#about to read 3, iclass 23, count 0 2006.218.07:20:19.31#ibcon#read 3, iclass 23, count 0 2006.218.07:20:19.31#ibcon#about to read 4, iclass 23, count 0 2006.218.07:20:19.31#ibcon#read 4, iclass 23, count 0 2006.218.07:20:19.31#ibcon#about to read 5, iclass 23, count 0 2006.218.07:20:19.31#ibcon#read 5, iclass 23, count 0 2006.218.07:20:19.31#ibcon#about to read 6, iclass 23, count 0 2006.218.07:20:19.31#ibcon#read 6, iclass 23, count 0 2006.218.07:20:19.31#ibcon#end of sib2, iclass 23, count 0 2006.218.07:20:19.31#ibcon#*mode == 0, iclass 23, count 0 2006.218.07:20:19.31#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.218.07:20:19.31#ibcon#[26=FRQ=07,832.99\r\n] 2006.218.07:20:19.31#ibcon#*before write, iclass 23, count 0 2006.218.07:20:19.31#ibcon#enter sib2, iclass 23, count 0 2006.218.07:20:19.31#ibcon#flushed, iclass 23, count 0 2006.218.07:20:19.31#ibcon#about to write, iclass 23, count 0 2006.218.07:20:19.31#ibcon#wrote, iclass 23, count 0 2006.218.07:20:19.31#ibcon#about to read 3, iclass 23, count 0 2006.218.07:20:19.35#ibcon#read 3, iclass 23, count 0 2006.218.07:20:19.35#ibcon#about to read 4, iclass 23, count 0 2006.218.07:20:19.35#ibcon#read 4, iclass 23, count 0 2006.218.07:20:19.35#ibcon#about to read 5, iclass 23, count 0 2006.218.07:20:19.35#ibcon#read 5, iclass 23, count 0 2006.218.07:20:19.35#ibcon#about to read 6, iclass 23, count 0 2006.218.07:20:19.35#ibcon#read 6, iclass 23, count 0 2006.218.07:20:19.35#ibcon#end of sib2, iclass 23, count 0 2006.218.07:20:19.35#ibcon#*after write, iclass 23, count 0 2006.218.07:20:19.35#ibcon#*before return 0, iclass 23, count 0 2006.218.07:20:19.35#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.218.07:20:19.35#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.218.07:20:19.35#ibcon#about to clear, iclass 23 cls_cnt 0 2006.218.07:20:19.35#ibcon#cleared, iclass 23 cls_cnt 0 2006.218.07:20:19.35$vc4f8/va=7,6 2006.218.07:20:19.35#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.218.07:20:19.35#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.218.07:20:19.35#ibcon#ireg 11 cls_cnt 2 2006.218.07:20:19.35#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.218.07:20:19.41#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.218.07:20:19.41#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.218.07:20:19.41#ibcon#enter wrdev, iclass 25, count 2 2006.218.07:20:19.41#ibcon#first serial, iclass 25, count 2 2006.218.07:20:19.41#ibcon#enter sib2, iclass 25, count 2 2006.218.07:20:19.41#ibcon#flushed, iclass 25, count 2 2006.218.07:20:19.41#ibcon#about to write, iclass 25, count 2 2006.218.07:20:19.41#ibcon#wrote, iclass 25, count 2 2006.218.07:20:19.41#ibcon#about to read 3, iclass 25, count 2 2006.218.07:20:19.43#ibcon#read 3, iclass 25, count 2 2006.218.07:20:19.43#ibcon#about to read 4, iclass 25, count 2 2006.218.07:20:19.43#ibcon#read 4, iclass 25, count 2 2006.218.07:20:19.43#ibcon#about to read 5, iclass 25, count 2 2006.218.07:20:19.43#ibcon#read 5, iclass 25, count 2 2006.218.07:20:19.43#ibcon#about to read 6, iclass 25, count 2 2006.218.07:20:19.43#ibcon#read 6, iclass 25, count 2 2006.218.07:20:19.43#ibcon#end of sib2, iclass 25, count 2 2006.218.07:20:19.43#ibcon#*mode == 0, iclass 25, count 2 2006.218.07:20:19.43#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.218.07:20:19.43#ibcon#[25=AT07-06\r\n] 2006.218.07:20:19.43#ibcon#*before write, iclass 25, count 2 2006.218.07:20:19.43#ibcon#enter sib2, iclass 25, count 2 2006.218.07:20:19.43#ibcon#flushed, iclass 25, count 2 2006.218.07:20:19.43#ibcon#about to write, iclass 25, count 2 2006.218.07:20:19.43#ibcon#wrote, iclass 25, count 2 2006.218.07:20:19.43#ibcon#about to read 3, iclass 25, count 2 2006.218.07:20:19.46#ibcon#read 3, iclass 25, count 2 2006.218.07:20:19.46#ibcon#about to read 4, iclass 25, count 2 2006.218.07:20:19.46#ibcon#read 4, iclass 25, count 2 2006.218.07:20:19.46#ibcon#about to read 5, iclass 25, count 2 2006.218.07:20:19.46#ibcon#read 5, iclass 25, count 2 2006.218.07:20:19.46#ibcon#about to read 6, iclass 25, count 2 2006.218.07:20:19.46#ibcon#read 6, iclass 25, count 2 2006.218.07:20:19.46#ibcon#end of sib2, iclass 25, count 2 2006.218.07:20:19.46#ibcon#*after write, iclass 25, count 2 2006.218.07:20:19.46#ibcon#*before return 0, iclass 25, count 2 2006.218.07:20:19.46#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.218.07:20:19.46#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.218.07:20:19.46#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.218.07:20:19.46#ibcon#ireg 7 cls_cnt 0 2006.218.07:20:19.46#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.218.07:20:19.58#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.218.07:20:19.58#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.218.07:20:19.58#ibcon#enter wrdev, iclass 25, count 0 2006.218.07:20:19.58#ibcon#first serial, iclass 25, count 0 2006.218.07:20:19.58#ibcon#enter sib2, iclass 25, count 0 2006.218.07:20:19.58#ibcon#flushed, iclass 25, count 0 2006.218.07:20:19.58#ibcon#about to write, iclass 25, count 0 2006.218.07:20:19.58#ibcon#wrote, iclass 25, count 0 2006.218.07:20:19.58#ibcon#about to read 3, iclass 25, count 0 2006.218.07:20:19.60#ibcon#read 3, iclass 25, count 0 2006.218.07:20:19.60#ibcon#about to read 4, iclass 25, count 0 2006.218.07:20:19.60#ibcon#read 4, iclass 25, count 0 2006.218.07:20:19.60#ibcon#about to read 5, iclass 25, count 0 2006.218.07:20:19.60#ibcon#read 5, iclass 25, count 0 2006.218.07:20:19.60#ibcon#about to read 6, iclass 25, count 0 2006.218.07:20:19.60#ibcon#read 6, iclass 25, count 0 2006.218.07:20:19.60#ibcon#end of sib2, iclass 25, count 0 2006.218.07:20:19.60#ibcon#*mode == 0, iclass 25, count 0 2006.218.07:20:19.60#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.218.07:20:19.60#ibcon#[25=USB\r\n] 2006.218.07:20:19.60#ibcon#*before write, iclass 25, count 0 2006.218.07:20:19.60#ibcon#enter sib2, iclass 25, count 0 2006.218.07:20:19.60#ibcon#flushed, iclass 25, count 0 2006.218.07:20:19.60#ibcon#about to write, iclass 25, count 0 2006.218.07:20:19.60#ibcon#wrote, iclass 25, count 0 2006.218.07:20:19.60#ibcon#about to read 3, iclass 25, count 0 2006.218.07:20:19.63#ibcon#read 3, iclass 25, count 0 2006.218.07:20:19.63#ibcon#about to read 4, iclass 25, count 0 2006.218.07:20:19.63#ibcon#read 4, iclass 25, count 0 2006.218.07:20:19.63#ibcon#about to read 5, iclass 25, count 0 2006.218.07:20:19.63#ibcon#read 5, iclass 25, count 0 2006.218.07:20:19.63#ibcon#about to read 6, iclass 25, count 0 2006.218.07:20:19.63#ibcon#read 6, iclass 25, count 0 2006.218.07:20:19.63#ibcon#end of sib2, iclass 25, count 0 2006.218.07:20:19.63#ibcon#*after write, iclass 25, count 0 2006.218.07:20:19.63#ibcon#*before return 0, iclass 25, count 0 2006.218.07:20:19.63#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.218.07:20:19.63#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.218.07:20:19.63#ibcon#about to clear, iclass 25 cls_cnt 0 2006.218.07:20:19.63#ibcon#cleared, iclass 25 cls_cnt 0 2006.218.07:20:19.63$vc4f8/valo=8,852.99 2006.218.07:20:19.63#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.218.07:20:19.63#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.218.07:20:19.63#ibcon#ireg 17 cls_cnt 0 2006.218.07:20:19.63#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.218.07:20:19.63#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.218.07:20:19.63#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.218.07:20:19.63#ibcon#enter wrdev, iclass 27, count 0 2006.218.07:20:19.63#ibcon#first serial, iclass 27, count 0 2006.218.07:20:19.63#ibcon#enter sib2, iclass 27, count 0 2006.218.07:20:19.63#ibcon#flushed, iclass 27, count 0 2006.218.07:20:19.63#ibcon#about to write, iclass 27, count 0 2006.218.07:20:19.63#ibcon#wrote, iclass 27, count 0 2006.218.07:20:19.63#ibcon#about to read 3, iclass 27, count 0 2006.218.07:20:19.66#ibcon#read 3, iclass 27, count 0 2006.218.07:20:19.66#ibcon#about to read 4, iclass 27, count 0 2006.218.07:20:19.66#ibcon#read 4, iclass 27, count 0 2006.218.07:20:19.66#ibcon#about to read 5, iclass 27, count 0 2006.218.07:20:19.66#ibcon#read 5, iclass 27, count 0 2006.218.07:20:19.66#ibcon#about to read 6, iclass 27, count 0 2006.218.07:20:19.66#ibcon#read 6, iclass 27, count 0 2006.218.07:20:19.66#ibcon#end of sib2, iclass 27, count 0 2006.218.07:20:19.66#ibcon#*mode == 0, iclass 27, count 0 2006.218.07:20:19.66#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.218.07:20:19.66#ibcon#[26=FRQ=08,852.99\r\n] 2006.218.07:20:19.66#ibcon#*before write, iclass 27, count 0 2006.218.07:20:19.66#ibcon#enter sib2, iclass 27, count 0 2006.218.07:20:19.66#ibcon#flushed, iclass 27, count 0 2006.218.07:20:19.66#ibcon#about to write, iclass 27, count 0 2006.218.07:20:19.66#ibcon#wrote, iclass 27, count 0 2006.218.07:20:19.66#ibcon#about to read 3, iclass 27, count 0 2006.218.07:20:19.70#ibcon#read 3, iclass 27, count 0 2006.218.07:20:19.70#ibcon#about to read 4, iclass 27, count 0 2006.218.07:20:19.70#ibcon#read 4, iclass 27, count 0 2006.218.07:20:19.70#ibcon#about to read 5, iclass 27, count 0 2006.218.07:20:19.70#ibcon#read 5, iclass 27, count 0 2006.218.07:20:19.70#ibcon#about to read 6, iclass 27, count 0 2006.218.07:20:19.70#ibcon#read 6, iclass 27, count 0 2006.218.07:20:19.70#ibcon#end of sib2, iclass 27, count 0 2006.218.07:20:19.70#ibcon#*after write, iclass 27, count 0 2006.218.07:20:19.70#ibcon#*before return 0, iclass 27, count 0 2006.218.07:20:19.70#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.218.07:20:19.70#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.218.07:20:19.70#ibcon#about to clear, iclass 27 cls_cnt 0 2006.218.07:20:19.70#ibcon#cleared, iclass 27 cls_cnt 0 2006.218.07:20:19.70$vc4f8/va=8,7 2006.218.07:20:19.70#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.218.07:20:19.70#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.218.07:20:19.70#ibcon#ireg 11 cls_cnt 2 2006.218.07:20:19.70#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.218.07:20:19.75#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.218.07:20:19.75#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.218.07:20:19.75#ibcon#enter wrdev, iclass 29, count 2 2006.218.07:20:19.75#ibcon#first serial, iclass 29, count 2 2006.218.07:20:19.75#ibcon#enter sib2, iclass 29, count 2 2006.218.07:20:19.75#ibcon#flushed, iclass 29, count 2 2006.218.07:20:19.75#ibcon#about to write, iclass 29, count 2 2006.218.07:20:19.75#ibcon#wrote, iclass 29, count 2 2006.218.07:20:19.75#ibcon#about to read 3, iclass 29, count 2 2006.218.07:20:19.77#ibcon#read 3, iclass 29, count 2 2006.218.07:20:19.77#ibcon#about to read 4, iclass 29, count 2 2006.218.07:20:19.77#ibcon#read 4, iclass 29, count 2 2006.218.07:20:19.77#ibcon#about to read 5, iclass 29, count 2 2006.218.07:20:19.77#ibcon#read 5, iclass 29, count 2 2006.218.07:20:19.77#ibcon#about to read 6, iclass 29, count 2 2006.218.07:20:19.77#ibcon#read 6, iclass 29, count 2 2006.218.07:20:19.77#ibcon#end of sib2, iclass 29, count 2 2006.218.07:20:19.77#ibcon#*mode == 0, iclass 29, count 2 2006.218.07:20:19.77#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.218.07:20:19.77#ibcon#[25=AT08-07\r\n] 2006.218.07:20:19.77#ibcon#*before write, iclass 29, count 2 2006.218.07:20:19.77#ibcon#enter sib2, iclass 29, count 2 2006.218.07:20:19.77#ibcon#flushed, iclass 29, count 2 2006.218.07:20:19.77#ibcon#about to write, iclass 29, count 2 2006.218.07:20:19.77#ibcon#wrote, iclass 29, count 2 2006.218.07:20:19.77#ibcon#about to read 3, iclass 29, count 2 2006.218.07:20:19.80#ibcon#read 3, iclass 29, count 2 2006.218.07:20:19.80#ibcon#about to read 4, iclass 29, count 2 2006.218.07:20:19.80#ibcon#read 4, iclass 29, count 2 2006.218.07:20:19.80#ibcon#about to read 5, iclass 29, count 2 2006.218.07:20:19.80#ibcon#read 5, iclass 29, count 2 2006.218.07:20:19.80#ibcon#about to read 6, iclass 29, count 2 2006.218.07:20:19.80#ibcon#read 6, iclass 29, count 2 2006.218.07:20:19.80#ibcon#end of sib2, iclass 29, count 2 2006.218.07:20:19.80#ibcon#*after write, iclass 29, count 2 2006.218.07:20:19.80#ibcon#*before return 0, iclass 29, count 2 2006.218.07:20:19.80#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.218.07:20:19.80#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.218.07:20:19.80#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.218.07:20:19.80#ibcon#ireg 7 cls_cnt 0 2006.218.07:20:19.80#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.218.07:20:19.92#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.218.07:20:19.92#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.218.07:20:19.92#ibcon#enter wrdev, iclass 29, count 0 2006.218.07:20:19.92#ibcon#first serial, iclass 29, count 0 2006.218.07:20:19.92#ibcon#enter sib2, iclass 29, count 0 2006.218.07:20:19.92#ibcon#flushed, iclass 29, count 0 2006.218.07:20:19.92#ibcon#about to write, iclass 29, count 0 2006.218.07:20:19.92#ibcon#wrote, iclass 29, count 0 2006.218.07:20:19.92#ibcon#about to read 3, iclass 29, count 0 2006.218.07:20:19.94#ibcon#read 3, iclass 29, count 0 2006.218.07:20:19.94#ibcon#about to read 4, iclass 29, count 0 2006.218.07:20:19.94#ibcon#read 4, iclass 29, count 0 2006.218.07:20:19.94#ibcon#about to read 5, iclass 29, count 0 2006.218.07:20:19.94#ibcon#read 5, iclass 29, count 0 2006.218.07:20:19.94#ibcon#about to read 6, iclass 29, count 0 2006.218.07:20:19.94#ibcon#read 6, iclass 29, count 0 2006.218.07:20:19.94#ibcon#end of sib2, iclass 29, count 0 2006.218.07:20:19.94#ibcon#*mode == 0, iclass 29, count 0 2006.218.07:20:19.94#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.218.07:20:19.94#ibcon#[25=USB\r\n] 2006.218.07:20:19.94#ibcon#*before write, iclass 29, count 0 2006.218.07:20:19.94#ibcon#enter sib2, iclass 29, count 0 2006.218.07:20:19.94#ibcon#flushed, iclass 29, count 0 2006.218.07:20:19.94#ibcon#about to write, iclass 29, count 0 2006.218.07:20:19.94#ibcon#wrote, iclass 29, count 0 2006.218.07:20:19.94#ibcon#about to read 3, iclass 29, count 0 2006.218.07:20:19.97#ibcon#read 3, iclass 29, count 0 2006.218.07:20:19.97#ibcon#about to read 4, iclass 29, count 0 2006.218.07:20:19.97#ibcon#read 4, iclass 29, count 0 2006.218.07:20:19.97#ibcon#about to read 5, iclass 29, count 0 2006.218.07:20:19.97#ibcon#read 5, iclass 29, count 0 2006.218.07:20:19.97#ibcon#about to read 6, iclass 29, count 0 2006.218.07:20:19.97#ibcon#read 6, iclass 29, count 0 2006.218.07:20:19.97#ibcon#end of sib2, iclass 29, count 0 2006.218.07:20:19.97#ibcon#*after write, iclass 29, count 0 2006.218.07:20:19.97#ibcon#*before return 0, iclass 29, count 0 2006.218.07:20:19.97#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.218.07:20:19.97#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.218.07:20:19.97#ibcon#about to clear, iclass 29 cls_cnt 0 2006.218.07:20:19.97#ibcon#cleared, iclass 29 cls_cnt 0 2006.218.07:20:19.97$vc4f8/vblo=1,632.99 2006.218.07:20:19.97#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.218.07:20:19.97#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.218.07:20:19.97#ibcon#ireg 17 cls_cnt 0 2006.218.07:20:19.97#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.218.07:20:19.97#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.218.07:20:19.97#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.218.07:20:19.97#ibcon#enter wrdev, iclass 31, count 0 2006.218.07:20:19.97#ibcon#first serial, iclass 31, count 0 2006.218.07:20:19.97#ibcon#enter sib2, iclass 31, count 0 2006.218.07:20:19.97#ibcon#flushed, iclass 31, count 0 2006.218.07:20:19.97#ibcon#about to write, iclass 31, count 0 2006.218.07:20:19.97#ibcon#wrote, iclass 31, count 0 2006.218.07:20:19.97#ibcon#about to read 3, iclass 31, count 0 2006.218.07:20:19.99#ibcon#read 3, iclass 31, count 0 2006.218.07:20:19.99#ibcon#about to read 4, iclass 31, count 0 2006.218.07:20:19.99#ibcon#read 4, iclass 31, count 0 2006.218.07:20:19.99#ibcon#about to read 5, iclass 31, count 0 2006.218.07:20:19.99#ibcon#read 5, iclass 31, count 0 2006.218.07:20:19.99#ibcon#about to read 6, iclass 31, count 0 2006.218.07:20:19.99#ibcon#read 6, iclass 31, count 0 2006.218.07:20:19.99#ibcon#end of sib2, iclass 31, count 0 2006.218.07:20:19.99#ibcon#*mode == 0, iclass 31, count 0 2006.218.07:20:19.99#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.218.07:20:19.99#ibcon#[28=FRQ=01,632.99\r\n] 2006.218.07:20:19.99#ibcon#*before write, iclass 31, count 0 2006.218.07:20:19.99#ibcon#enter sib2, iclass 31, count 0 2006.218.07:20:19.99#ibcon#flushed, iclass 31, count 0 2006.218.07:20:19.99#ibcon#about to write, iclass 31, count 0 2006.218.07:20:19.99#ibcon#wrote, iclass 31, count 0 2006.218.07:20:19.99#ibcon#about to read 3, iclass 31, count 0 2006.218.07:20:20.03#ibcon#read 3, iclass 31, count 0 2006.218.07:20:20.03#ibcon#about to read 4, iclass 31, count 0 2006.218.07:20:20.03#ibcon#read 4, iclass 31, count 0 2006.218.07:20:20.03#ibcon#about to read 5, iclass 31, count 0 2006.218.07:20:20.03#ibcon#read 5, iclass 31, count 0 2006.218.07:20:20.03#ibcon#about to read 6, iclass 31, count 0 2006.218.07:20:20.03#ibcon#read 6, iclass 31, count 0 2006.218.07:20:20.03#ibcon#end of sib2, iclass 31, count 0 2006.218.07:20:20.03#ibcon#*after write, iclass 31, count 0 2006.218.07:20:20.03#ibcon#*before return 0, iclass 31, count 0 2006.218.07:20:20.03#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.218.07:20:20.03#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.218.07:20:20.03#ibcon#about to clear, iclass 31 cls_cnt 0 2006.218.07:20:20.03#ibcon#cleared, iclass 31 cls_cnt 0 2006.218.07:20:20.03$vc4f8/vb=1,4 2006.218.07:20:20.03#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.218.07:20:20.03#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.218.07:20:20.03#ibcon#ireg 11 cls_cnt 2 2006.218.07:20:20.03#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.218.07:20:20.03#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.218.07:20:20.03#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.218.07:20:20.03#ibcon#enter wrdev, iclass 34, count 2 2006.218.07:20:20.03#ibcon#first serial, iclass 34, count 2 2006.218.07:20:20.03#ibcon#enter sib2, iclass 34, count 2 2006.218.07:20:20.03#ibcon#flushed, iclass 34, count 2 2006.218.07:20:20.03#ibcon#about to write, iclass 34, count 2 2006.218.07:20:20.03#ibcon#wrote, iclass 34, count 2 2006.218.07:20:20.03#ibcon#about to read 3, iclass 34, count 2 2006.218.07:20:20.05#ibcon#read 3, iclass 34, count 2 2006.218.07:20:20.05#ibcon#about to read 4, iclass 34, count 2 2006.218.07:20:20.05#ibcon#read 4, iclass 34, count 2 2006.218.07:20:20.05#ibcon#about to read 5, iclass 34, count 2 2006.218.07:20:20.05#ibcon#read 5, iclass 34, count 2 2006.218.07:20:20.05#ibcon#about to read 6, iclass 34, count 2 2006.218.07:20:20.05#ibcon#read 6, iclass 34, count 2 2006.218.07:20:20.05#ibcon#end of sib2, iclass 34, count 2 2006.218.07:20:20.05#ibcon#*mode == 0, iclass 34, count 2 2006.218.07:20:20.05#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.218.07:20:20.05#ibcon#[27=AT01-04\r\n] 2006.218.07:20:20.05#ibcon#*before write, iclass 34, count 2 2006.218.07:20:20.05#ibcon#enter sib2, iclass 34, count 2 2006.218.07:20:20.05#ibcon#flushed, iclass 34, count 2 2006.218.07:20:20.05#ibcon#about to write, iclass 34, count 2 2006.218.07:20:20.05#ibcon#wrote, iclass 34, count 2 2006.218.07:20:20.05#ibcon#about to read 3, iclass 34, count 2 2006.218.07:20:20.07#abcon#<5=/06 4.6 7.5 32.11 731007.3\r\n> 2006.218.07:20:20.08#ibcon#read 3, iclass 34, count 2 2006.218.07:20:20.08#ibcon#about to read 4, iclass 34, count 2 2006.218.07:20:20.08#ibcon#read 4, iclass 34, count 2 2006.218.07:20:20.08#ibcon#about to read 5, iclass 34, count 2 2006.218.07:20:20.08#ibcon#read 5, iclass 34, count 2 2006.218.07:20:20.08#ibcon#about to read 6, iclass 34, count 2 2006.218.07:20:20.08#ibcon#read 6, iclass 34, count 2 2006.218.07:20:20.08#ibcon#end of sib2, iclass 34, count 2 2006.218.07:20:20.08#ibcon#*after write, iclass 34, count 2 2006.218.07:20:20.08#ibcon#*before return 0, iclass 34, count 2 2006.218.07:20:20.08#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.218.07:20:20.08#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.218.07:20:20.08#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.218.07:20:20.08#ibcon#ireg 7 cls_cnt 0 2006.218.07:20:20.08#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.218.07:20:20.09#abcon#{5=INTERFACE CLEAR} 2006.218.07:20:20.15#abcon#[5=S1D000X0/0*\r\n] 2006.218.07:20:20.20#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.218.07:20:20.20#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.218.07:20:20.20#ibcon#enter wrdev, iclass 34, count 0 2006.218.07:20:20.20#ibcon#first serial, iclass 34, count 0 2006.218.07:20:20.20#ibcon#enter sib2, iclass 34, count 0 2006.218.07:20:20.20#ibcon#flushed, iclass 34, count 0 2006.218.07:20:20.20#ibcon#about to write, iclass 34, count 0 2006.218.07:20:20.20#ibcon#wrote, iclass 34, count 0 2006.218.07:20:20.20#ibcon#about to read 3, iclass 34, count 0 2006.218.07:20:20.22#ibcon#read 3, iclass 34, count 0 2006.218.07:20:20.22#ibcon#about to read 4, iclass 34, count 0 2006.218.07:20:20.22#ibcon#read 4, iclass 34, count 0 2006.218.07:20:20.22#ibcon#about to read 5, iclass 34, count 0 2006.218.07:20:20.22#ibcon#read 5, iclass 34, count 0 2006.218.07:20:20.22#ibcon#about to read 6, iclass 34, count 0 2006.218.07:20:20.22#ibcon#read 6, iclass 34, count 0 2006.218.07:20:20.22#ibcon#end of sib2, iclass 34, count 0 2006.218.07:20:20.22#ibcon#*mode == 0, iclass 34, count 0 2006.218.07:20:20.22#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.218.07:20:20.22#ibcon#[27=USB\r\n] 2006.218.07:20:20.22#ibcon#*before write, iclass 34, count 0 2006.218.07:20:20.22#ibcon#enter sib2, iclass 34, count 0 2006.218.07:20:20.22#ibcon#flushed, iclass 34, count 0 2006.218.07:20:20.22#ibcon#about to write, iclass 34, count 0 2006.218.07:20:20.22#ibcon#wrote, iclass 34, count 0 2006.218.07:20:20.22#ibcon#about to read 3, iclass 34, count 0 2006.218.07:20:20.25#ibcon#read 3, iclass 34, count 0 2006.218.07:20:20.25#ibcon#about to read 4, iclass 34, count 0 2006.218.07:20:20.25#ibcon#read 4, iclass 34, count 0 2006.218.07:20:20.25#ibcon#about to read 5, iclass 34, count 0 2006.218.07:20:20.25#ibcon#read 5, iclass 34, count 0 2006.218.07:20:20.25#ibcon#about to read 6, iclass 34, count 0 2006.218.07:20:20.25#ibcon#read 6, iclass 34, count 0 2006.218.07:20:20.25#ibcon#end of sib2, iclass 34, count 0 2006.218.07:20:20.25#ibcon#*after write, iclass 34, count 0 2006.218.07:20:20.25#ibcon#*before return 0, iclass 34, count 0 2006.218.07:20:20.25#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.218.07:20:20.25#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.218.07:20:20.25#ibcon#about to clear, iclass 34 cls_cnt 0 2006.218.07:20:20.25#ibcon#cleared, iclass 34 cls_cnt 0 2006.218.07:20:20.25$vc4f8/vblo=2,640.99 2006.218.07:20:20.25#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.218.07:20:20.25#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.218.07:20:20.25#ibcon#ireg 17 cls_cnt 0 2006.218.07:20:20.25#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.218.07:20:20.25#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.218.07:20:20.25#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.218.07:20:20.25#ibcon#enter wrdev, iclass 39, count 0 2006.218.07:20:20.25#ibcon#first serial, iclass 39, count 0 2006.218.07:20:20.25#ibcon#enter sib2, iclass 39, count 0 2006.218.07:20:20.25#ibcon#flushed, iclass 39, count 0 2006.218.07:20:20.25#ibcon#about to write, iclass 39, count 0 2006.218.07:20:20.25#ibcon#wrote, iclass 39, count 0 2006.218.07:20:20.25#ibcon#about to read 3, iclass 39, count 0 2006.218.07:20:20.27#ibcon#read 3, iclass 39, count 0 2006.218.07:20:20.27#ibcon#about to read 4, iclass 39, count 0 2006.218.07:20:20.27#ibcon#read 4, iclass 39, count 0 2006.218.07:20:20.27#ibcon#about to read 5, iclass 39, count 0 2006.218.07:20:20.27#ibcon#read 5, iclass 39, count 0 2006.218.07:20:20.27#ibcon#about to read 6, iclass 39, count 0 2006.218.07:20:20.27#ibcon#read 6, iclass 39, count 0 2006.218.07:20:20.27#ibcon#end of sib2, iclass 39, count 0 2006.218.07:20:20.27#ibcon#*mode == 0, iclass 39, count 0 2006.218.07:20:20.27#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.218.07:20:20.27#ibcon#[28=FRQ=02,640.99\r\n] 2006.218.07:20:20.27#ibcon#*before write, iclass 39, count 0 2006.218.07:20:20.27#ibcon#enter sib2, iclass 39, count 0 2006.218.07:20:20.27#ibcon#flushed, iclass 39, count 0 2006.218.07:20:20.27#ibcon#about to write, iclass 39, count 0 2006.218.07:20:20.27#ibcon#wrote, iclass 39, count 0 2006.218.07:20:20.27#ibcon#about to read 3, iclass 39, count 0 2006.218.07:20:20.31#ibcon#read 3, iclass 39, count 0 2006.218.07:20:20.31#ibcon#about to read 4, iclass 39, count 0 2006.218.07:20:20.31#ibcon#read 4, iclass 39, count 0 2006.218.07:20:20.31#ibcon#about to read 5, iclass 39, count 0 2006.218.07:20:20.31#ibcon#read 5, iclass 39, count 0 2006.218.07:20:20.31#ibcon#about to read 6, iclass 39, count 0 2006.218.07:20:20.31#ibcon#read 6, iclass 39, count 0 2006.218.07:20:20.31#ibcon#end of sib2, iclass 39, count 0 2006.218.07:20:20.31#ibcon#*after write, iclass 39, count 0 2006.218.07:20:20.31#ibcon#*before return 0, iclass 39, count 0 2006.218.07:20:20.31#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.218.07:20:20.31#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.218.07:20:20.31#ibcon#about to clear, iclass 39 cls_cnt 0 2006.218.07:20:20.31#ibcon#cleared, iclass 39 cls_cnt 0 2006.218.07:20:20.31$vc4f8/vb=2,4 2006.218.07:20:20.31#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.218.07:20:20.31#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.218.07:20:20.31#ibcon#ireg 11 cls_cnt 2 2006.218.07:20:20.31#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.218.07:20:20.37#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.218.07:20:20.37#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.218.07:20:20.37#ibcon#enter wrdev, iclass 3, count 2 2006.218.07:20:20.37#ibcon#first serial, iclass 3, count 2 2006.218.07:20:20.37#ibcon#enter sib2, iclass 3, count 2 2006.218.07:20:20.37#ibcon#flushed, iclass 3, count 2 2006.218.07:20:20.37#ibcon#about to write, iclass 3, count 2 2006.218.07:20:20.37#ibcon#wrote, iclass 3, count 2 2006.218.07:20:20.37#ibcon#about to read 3, iclass 3, count 2 2006.218.07:20:20.39#ibcon#read 3, iclass 3, count 2 2006.218.07:20:20.39#ibcon#about to read 4, iclass 3, count 2 2006.218.07:20:20.39#ibcon#read 4, iclass 3, count 2 2006.218.07:20:20.39#ibcon#about to read 5, iclass 3, count 2 2006.218.07:20:20.39#ibcon#read 5, iclass 3, count 2 2006.218.07:20:20.39#ibcon#about to read 6, iclass 3, count 2 2006.218.07:20:20.39#ibcon#read 6, iclass 3, count 2 2006.218.07:20:20.39#ibcon#end of sib2, iclass 3, count 2 2006.218.07:20:20.39#ibcon#*mode == 0, iclass 3, count 2 2006.218.07:20:20.39#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.218.07:20:20.39#ibcon#[27=AT02-04\r\n] 2006.218.07:20:20.39#ibcon#*before write, iclass 3, count 2 2006.218.07:20:20.39#ibcon#enter sib2, iclass 3, count 2 2006.218.07:20:20.39#ibcon#flushed, iclass 3, count 2 2006.218.07:20:20.39#ibcon#about to write, iclass 3, count 2 2006.218.07:20:20.39#ibcon#wrote, iclass 3, count 2 2006.218.07:20:20.39#ibcon#about to read 3, iclass 3, count 2 2006.218.07:20:20.42#ibcon#read 3, iclass 3, count 2 2006.218.07:20:20.42#ibcon#about to read 4, iclass 3, count 2 2006.218.07:20:20.42#ibcon#read 4, iclass 3, count 2 2006.218.07:20:20.42#ibcon#about to read 5, iclass 3, count 2 2006.218.07:20:20.42#ibcon#read 5, iclass 3, count 2 2006.218.07:20:20.42#ibcon#about to read 6, iclass 3, count 2 2006.218.07:20:20.42#ibcon#read 6, iclass 3, count 2 2006.218.07:20:20.42#ibcon#end of sib2, iclass 3, count 2 2006.218.07:20:20.42#ibcon#*after write, iclass 3, count 2 2006.218.07:20:20.42#ibcon#*before return 0, iclass 3, count 2 2006.218.07:20:20.42#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.218.07:20:20.42#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.218.07:20:20.42#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.218.07:20:20.42#ibcon#ireg 7 cls_cnt 0 2006.218.07:20:20.42#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.218.07:20:20.54#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.218.07:20:20.54#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.218.07:20:20.54#ibcon#enter wrdev, iclass 3, count 0 2006.218.07:20:20.54#ibcon#first serial, iclass 3, count 0 2006.218.07:20:20.54#ibcon#enter sib2, iclass 3, count 0 2006.218.07:20:20.54#ibcon#flushed, iclass 3, count 0 2006.218.07:20:20.54#ibcon#about to write, iclass 3, count 0 2006.218.07:20:20.54#ibcon#wrote, iclass 3, count 0 2006.218.07:20:20.54#ibcon#about to read 3, iclass 3, count 0 2006.218.07:20:20.56#ibcon#read 3, iclass 3, count 0 2006.218.07:20:20.56#ibcon#about to read 4, iclass 3, count 0 2006.218.07:20:20.56#ibcon#read 4, iclass 3, count 0 2006.218.07:20:20.56#ibcon#about to read 5, iclass 3, count 0 2006.218.07:20:20.56#ibcon#read 5, iclass 3, count 0 2006.218.07:20:20.56#ibcon#about to read 6, iclass 3, count 0 2006.218.07:20:20.56#ibcon#read 6, iclass 3, count 0 2006.218.07:20:20.56#ibcon#end of sib2, iclass 3, count 0 2006.218.07:20:20.56#ibcon#*mode == 0, iclass 3, count 0 2006.218.07:20:20.56#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.218.07:20:20.56#ibcon#[27=USB\r\n] 2006.218.07:20:20.56#ibcon#*before write, iclass 3, count 0 2006.218.07:20:20.56#ibcon#enter sib2, iclass 3, count 0 2006.218.07:20:20.56#ibcon#flushed, iclass 3, count 0 2006.218.07:20:20.56#ibcon#about to write, iclass 3, count 0 2006.218.07:20:20.56#ibcon#wrote, iclass 3, count 0 2006.218.07:20:20.56#ibcon#about to read 3, iclass 3, count 0 2006.218.07:20:20.59#ibcon#read 3, iclass 3, count 0 2006.218.07:20:20.59#ibcon#about to read 4, iclass 3, count 0 2006.218.07:20:20.59#ibcon#read 4, iclass 3, count 0 2006.218.07:20:20.59#ibcon#about to read 5, iclass 3, count 0 2006.218.07:20:20.59#ibcon#read 5, iclass 3, count 0 2006.218.07:20:20.59#ibcon#about to read 6, iclass 3, count 0 2006.218.07:20:20.59#ibcon#read 6, iclass 3, count 0 2006.218.07:20:20.59#ibcon#end of sib2, iclass 3, count 0 2006.218.07:20:20.59#ibcon#*after write, iclass 3, count 0 2006.218.07:20:20.59#ibcon#*before return 0, iclass 3, count 0 2006.218.07:20:20.59#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.218.07:20:20.59#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.218.07:20:20.59#ibcon#about to clear, iclass 3 cls_cnt 0 2006.218.07:20:20.59#ibcon#cleared, iclass 3 cls_cnt 0 2006.218.07:20:20.59$vc4f8/vblo=3,656.99 2006.218.07:20:20.59#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.218.07:20:20.59#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.218.07:20:20.59#ibcon#ireg 17 cls_cnt 0 2006.218.07:20:20.59#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.218.07:20:20.59#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.218.07:20:20.59#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.218.07:20:20.59#ibcon#enter wrdev, iclass 5, count 0 2006.218.07:20:20.59#ibcon#first serial, iclass 5, count 0 2006.218.07:20:20.59#ibcon#enter sib2, iclass 5, count 0 2006.218.07:20:20.59#ibcon#flushed, iclass 5, count 0 2006.218.07:20:20.59#ibcon#about to write, iclass 5, count 0 2006.218.07:20:20.59#ibcon#wrote, iclass 5, count 0 2006.218.07:20:20.59#ibcon#about to read 3, iclass 5, count 0 2006.218.07:20:20.62#ibcon#read 3, iclass 5, count 0 2006.218.07:20:20.62#ibcon#about to read 4, iclass 5, count 0 2006.218.07:20:20.62#ibcon#read 4, iclass 5, count 0 2006.218.07:20:20.62#ibcon#about to read 5, iclass 5, count 0 2006.218.07:20:20.62#ibcon#read 5, iclass 5, count 0 2006.218.07:20:20.62#ibcon#about to read 6, iclass 5, count 0 2006.218.07:20:20.62#ibcon#read 6, iclass 5, count 0 2006.218.07:20:20.62#ibcon#end of sib2, iclass 5, count 0 2006.218.07:20:20.62#ibcon#*mode == 0, iclass 5, count 0 2006.218.07:20:20.62#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.218.07:20:20.62#ibcon#[28=FRQ=03,656.99\r\n] 2006.218.07:20:20.62#ibcon#*before write, iclass 5, count 0 2006.218.07:20:20.62#ibcon#enter sib2, iclass 5, count 0 2006.218.07:20:20.62#ibcon#flushed, iclass 5, count 0 2006.218.07:20:20.62#ibcon#about to write, iclass 5, count 0 2006.218.07:20:20.62#ibcon#wrote, iclass 5, count 0 2006.218.07:20:20.62#ibcon#about to read 3, iclass 5, count 0 2006.218.07:20:20.66#ibcon#read 3, iclass 5, count 0 2006.218.07:20:20.66#ibcon#about to read 4, iclass 5, count 0 2006.218.07:20:20.66#ibcon#read 4, iclass 5, count 0 2006.218.07:20:20.66#ibcon#about to read 5, iclass 5, count 0 2006.218.07:20:20.66#ibcon#read 5, iclass 5, count 0 2006.218.07:20:20.66#ibcon#about to read 6, iclass 5, count 0 2006.218.07:20:20.66#ibcon#read 6, iclass 5, count 0 2006.218.07:20:20.66#ibcon#end of sib2, iclass 5, count 0 2006.218.07:20:20.66#ibcon#*after write, iclass 5, count 0 2006.218.07:20:20.66#ibcon#*before return 0, iclass 5, count 0 2006.218.07:20:20.66#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.218.07:20:20.66#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.218.07:20:20.66#ibcon#about to clear, iclass 5 cls_cnt 0 2006.218.07:20:20.66#ibcon#cleared, iclass 5 cls_cnt 0 2006.218.07:20:20.66$vc4f8/vb=3,4 2006.218.07:20:20.66#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.218.07:20:20.66#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.218.07:20:20.66#ibcon#ireg 11 cls_cnt 2 2006.218.07:20:20.66#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.218.07:20:20.71#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.218.07:20:20.71#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.218.07:20:20.71#ibcon#enter wrdev, iclass 7, count 2 2006.218.07:20:20.71#ibcon#first serial, iclass 7, count 2 2006.218.07:20:20.71#ibcon#enter sib2, iclass 7, count 2 2006.218.07:20:20.71#ibcon#flushed, iclass 7, count 2 2006.218.07:20:20.71#ibcon#about to write, iclass 7, count 2 2006.218.07:20:20.71#ibcon#wrote, iclass 7, count 2 2006.218.07:20:20.71#ibcon#about to read 3, iclass 7, count 2 2006.218.07:20:20.73#ibcon#read 3, iclass 7, count 2 2006.218.07:20:20.73#ibcon#about to read 4, iclass 7, count 2 2006.218.07:20:20.73#ibcon#read 4, iclass 7, count 2 2006.218.07:20:20.73#ibcon#about to read 5, iclass 7, count 2 2006.218.07:20:20.73#ibcon#read 5, iclass 7, count 2 2006.218.07:20:20.73#ibcon#about to read 6, iclass 7, count 2 2006.218.07:20:20.73#ibcon#read 6, iclass 7, count 2 2006.218.07:20:20.73#ibcon#end of sib2, iclass 7, count 2 2006.218.07:20:20.73#ibcon#*mode == 0, iclass 7, count 2 2006.218.07:20:20.73#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.218.07:20:20.73#ibcon#[27=AT03-04\r\n] 2006.218.07:20:20.73#ibcon#*before write, iclass 7, count 2 2006.218.07:20:20.73#ibcon#enter sib2, iclass 7, count 2 2006.218.07:20:20.73#ibcon#flushed, iclass 7, count 2 2006.218.07:20:20.73#ibcon#about to write, iclass 7, count 2 2006.218.07:20:20.73#ibcon#wrote, iclass 7, count 2 2006.218.07:20:20.73#ibcon#about to read 3, iclass 7, count 2 2006.218.07:20:20.76#ibcon#read 3, iclass 7, count 2 2006.218.07:20:20.76#ibcon#about to read 4, iclass 7, count 2 2006.218.07:20:20.76#ibcon#read 4, iclass 7, count 2 2006.218.07:20:20.76#ibcon#about to read 5, iclass 7, count 2 2006.218.07:20:20.76#ibcon#read 5, iclass 7, count 2 2006.218.07:20:20.76#ibcon#about to read 6, iclass 7, count 2 2006.218.07:20:20.76#ibcon#read 6, iclass 7, count 2 2006.218.07:20:20.76#ibcon#end of sib2, iclass 7, count 2 2006.218.07:20:20.76#ibcon#*after write, iclass 7, count 2 2006.218.07:20:20.76#ibcon#*before return 0, iclass 7, count 2 2006.218.07:20:20.76#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.218.07:20:20.76#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.218.07:20:20.76#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.218.07:20:20.76#ibcon#ireg 7 cls_cnt 0 2006.218.07:20:20.76#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.218.07:20:20.88#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.218.07:20:20.88#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.218.07:20:20.88#ibcon#enter wrdev, iclass 7, count 0 2006.218.07:20:20.88#ibcon#first serial, iclass 7, count 0 2006.218.07:20:20.88#ibcon#enter sib2, iclass 7, count 0 2006.218.07:20:20.88#ibcon#flushed, iclass 7, count 0 2006.218.07:20:20.88#ibcon#about to write, iclass 7, count 0 2006.218.07:20:20.88#ibcon#wrote, iclass 7, count 0 2006.218.07:20:20.88#ibcon#about to read 3, iclass 7, count 0 2006.218.07:20:20.90#ibcon#read 3, iclass 7, count 0 2006.218.07:20:20.90#ibcon#about to read 4, iclass 7, count 0 2006.218.07:20:20.90#ibcon#read 4, iclass 7, count 0 2006.218.07:20:20.90#ibcon#about to read 5, iclass 7, count 0 2006.218.07:20:20.90#ibcon#read 5, iclass 7, count 0 2006.218.07:20:20.90#ibcon#about to read 6, iclass 7, count 0 2006.218.07:20:20.90#ibcon#read 6, iclass 7, count 0 2006.218.07:20:20.90#ibcon#end of sib2, iclass 7, count 0 2006.218.07:20:20.90#ibcon#*mode == 0, iclass 7, count 0 2006.218.07:20:20.90#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.218.07:20:20.90#ibcon#[27=USB\r\n] 2006.218.07:20:20.90#ibcon#*before write, iclass 7, count 0 2006.218.07:20:20.90#ibcon#enter sib2, iclass 7, count 0 2006.218.07:20:20.90#ibcon#flushed, iclass 7, count 0 2006.218.07:20:20.90#ibcon#about to write, iclass 7, count 0 2006.218.07:20:20.90#ibcon#wrote, iclass 7, count 0 2006.218.07:20:20.90#ibcon#about to read 3, iclass 7, count 0 2006.218.07:20:20.93#ibcon#read 3, iclass 7, count 0 2006.218.07:20:20.93#ibcon#about to read 4, iclass 7, count 0 2006.218.07:20:20.93#ibcon#read 4, iclass 7, count 0 2006.218.07:20:20.93#ibcon#about to read 5, iclass 7, count 0 2006.218.07:20:20.93#ibcon#read 5, iclass 7, count 0 2006.218.07:20:20.93#ibcon#about to read 6, iclass 7, count 0 2006.218.07:20:20.93#ibcon#read 6, iclass 7, count 0 2006.218.07:20:20.93#ibcon#end of sib2, iclass 7, count 0 2006.218.07:20:20.93#ibcon#*after write, iclass 7, count 0 2006.218.07:20:20.93#ibcon#*before return 0, iclass 7, count 0 2006.218.07:20:20.93#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.218.07:20:20.93#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.218.07:20:20.93#ibcon#about to clear, iclass 7 cls_cnt 0 2006.218.07:20:20.93#ibcon#cleared, iclass 7 cls_cnt 0 2006.218.07:20:20.93$vc4f8/vblo=4,712.99 2006.218.07:20:20.93#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.218.07:20:20.93#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.218.07:20:20.93#ibcon#ireg 17 cls_cnt 0 2006.218.07:20:20.93#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.218.07:20:20.93#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.218.07:20:20.93#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.218.07:20:20.93#ibcon#enter wrdev, iclass 11, count 0 2006.218.07:20:20.93#ibcon#first serial, iclass 11, count 0 2006.218.07:20:20.93#ibcon#enter sib2, iclass 11, count 0 2006.218.07:20:20.93#ibcon#flushed, iclass 11, count 0 2006.218.07:20:20.93#ibcon#about to write, iclass 11, count 0 2006.218.07:20:20.93#ibcon#wrote, iclass 11, count 0 2006.218.07:20:20.93#ibcon#about to read 3, iclass 11, count 0 2006.218.07:20:20.95#ibcon#read 3, iclass 11, count 0 2006.218.07:20:20.95#ibcon#about to read 4, iclass 11, count 0 2006.218.07:20:20.95#ibcon#read 4, iclass 11, count 0 2006.218.07:20:20.95#ibcon#about to read 5, iclass 11, count 0 2006.218.07:20:20.95#ibcon#read 5, iclass 11, count 0 2006.218.07:20:20.95#ibcon#about to read 6, iclass 11, count 0 2006.218.07:20:20.95#ibcon#read 6, iclass 11, count 0 2006.218.07:20:20.95#ibcon#end of sib2, iclass 11, count 0 2006.218.07:20:20.95#ibcon#*mode == 0, iclass 11, count 0 2006.218.07:20:20.95#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.218.07:20:20.95#ibcon#[28=FRQ=04,712.99\r\n] 2006.218.07:20:20.95#ibcon#*before write, iclass 11, count 0 2006.218.07:20:20.95#ibcon#enter sib2, iclass 11, count 0 2006.218.07:20:20.95#ibcon#flushed, iclass 11, count 0 2006.218.07:20:20.95#ibcon#about to write, iclass 11, count 0 2006.218.07:20:20.95#ibcon#wrote, iclass 11, count 0 2006.218.07:20:20.95#ibcon#about to read 3, iclass 11, count 0 2006.218.07:20:20.99#ibcon#read 3, iclass 11, count 0 2006.218.07:20:20.99#ibcon#about to read 4, iclass 11, count 0 2006.218.07:20:20.99#ibcon#read 4, iclass 11, count 0 2006.218.07:20:20.99#ibcon#about to read 5, iclass 11, count 0 2006.218.07:20:20.99#ibcon#read 5, iclass 11, count 0 2006.218.07:20:20.99#ibcon#about to read 6, iclass 11, count 0 2006.218.07:20:20.99#ibcon#read 6, iclass 11, count 0 2006.218.07:20:20.99#ibcon#end of sib2, iclass 11, count 0 2006.218.07:20:20.99#ibcon#*after write, iclass 11, count 0 2006.218.07:20:20.99#ibcon#*before return 0, iclass 11, count 0 2006.218.07:20:20.99#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.218.07:20:20.99#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.218.07:20:20.99#ibcon#about to clear, iclass 11 cls_cnt 0 2006.218.07:20:20.99#ibcon#cleared, iclass 11 cls_cnt 0 2006.218.07:20:20.99$vc4f8/vb=4,4 2006.218.07:20:20.99#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.218.07:20:20.99#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.218.07:20:20.99#ibcon#ireg 11 cls_cnt 2 2006.218.07:20:20.99#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.218.07:20:21.05#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.218.07:20:21.05#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.218.07:20:21.05#ibcon#enter wrdev, iclass 13, count 2 2006.218.07:20:21.05#ibcon#first serial, iclass 13, count 2 2006.218.07:20:21.05#ibcon#enter sib2, iclass 13, count 2 2006.218.07:20:21.05#ibcon#flushed, iclass 13, count 2 2006.218.07:20:21.05#ibcon#about to write, iclass 13, count 2 2006.218.07:20:21.05#ibcon#wrote, iclass 13, count 2 2006.218.07:20:21.05#ibcon#about to read 3, iclass 13, count 2 2006.218.07:20:21.07#ibcon#read 3, iclass 13, count 2 2006.218.07:20:21.07#ibcon#about to read 4, iclass 13, count 2 2006.218.07:20:21.07#ibcon#read 4, iclass 13, count 2 2006.218.07:20:21.07#ibcon#about to read 5, iclass 13, count 2 2006.218.07:20:21.07#ibcon#read 5, iclass 13, count 2 2006.218.07:20:21.07#ibcon#about to read 6, iclass 13, count 2 2006.218.07:20:21.07#ibcon#read 6, iclass 13, count 2 2006.218.07:20:21.07#ibcon#end of sib2, iclass 13, count 2 2006.218.07:20:21.07#ibcon#*mode == 0, iclass 13, count 2 2006.218.07:20:21.07#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.218.07:20:21.07#ibcon#[27=AT04-04\r\n] 2006.218.07:20:21.07#ibcon#*before write, iclass 13, count 2 2006.218.07:20:21.07#ibcon#enter sib2, iclass 13, count 2 2006.218.07:20:21.07#ibcon#flushed, iclass 13, count 2 2006.218.07:20:21.07#ibcon#about to write, iclass 13, count 2 2006.218.07:20:21.07#ibcon#wrote, iclass 13, count 2 2006.218.07:20:21.07#ibcon#about to read 3, iclass 13, count 2 2006.218.07:20:21.10#ibcon#read 3, iclass 13, count 2 2006.218.07:20:21.10#ibcon#about to read 4, iclass 13, count 2 2006.218.07:20:21.10#ibcon#read 4, iclass 13, count 2 2006.218.07:20:21.10#ibcon#about to read 5, iclass 13, count 2 2006.218.07:20:21.10#ibcon#read 5, iclass 13, count 2 2006.218.07:20:21.10#ibcon#about to read 6, iclass 13, count 2 2006.218.07:20:21.10#ibcon#read 6, iclass 13, count 2 2006.218.07:20:21.10#ibcon#end of sib2, iclass 13, count 2 2006.218.07:20:21.10#ibcon#*after write, iclass 13, count 2 2006.218.07:20:21.10#ibcon#*before return 0, iclass 13, count 2 2006.218.07:20:21.10#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.218.07:20:21.10#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.218.07:20:21.10#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.218.07:20:21.10#ibcon#ireg 7 cls_cnt 0 2006.218.07:20:21.10#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.218.07:20:21.22#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.218.07:20:21.22#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.218.07:20:21.22#ibcon#enter wrdev, iclass 13, count 0 2006.218.07:20:21.22#ibcon#first serial, iclass 13, count 0 2006.218.07:20:21.22#ibcon#enter sib2, iclass 13, count 0 2006.218.07:20:21.22#ibcon#flushed, iclass 13, count 0 2006.218.07:20:21.22#ibcon#about to write, iclass 13, count 0 2006.218.07:20:21.22#ibcon#wrote, iclass 13, count 0 2006.218.07:20:21.22#ibcon#about to read 3, iclass 13, count 0 2006.218.07:20:21.24#ibcon#read 3, iclass 13, count 0 2006.218.07:20:21.24#ibcon#about to read 4, iclass 13, count 0 2006.218.07:20:21.24#ibcon#read 4, iclass 13, count 0 2006.218.07:20:21.24#ibcon#about to read 5, iclass 13, count 0 2006.218.07:20:21.24#ibcon#read 5, iclass 13, count 0 2006.218.07:20:21.24#ibcon#about to read 6, iclass 13, count 0 2006.218.07:20:21.24#ibcon#read 6, iclass 13, count 0 2006.218.07:20:21.24#ibcon#end of sib2, iclass 13, count 0 2006.218.07:20:21.24#ibcon#*mode == 0, iclass 13, count 0 2006.218.07:20:21.24#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.218.07:20:21.24#ibcon#[27=USB\r\n] 2006.218.07:20:21.24#ibcon#*before write, iclass 13, count 0 2006.218.07:20:21.24#ibcon#enter sib2, iclass 13, count 0 2006.218.07:20:21.24#ibcon#flushed, iclass 13, count 0 2006.218.07:20:21.24#ibcon#about to write, iclass 13, count 0 2006.218.07:20:21.24#ibcon#wrote, iclass 13, count 0 2006.218.07:20:21.24#ibcon#about to read 3, iclass 13, count 0 2006.218.07:20:21.27#ibcon#read 3, iclass 13, count 0 2006.218.07:20:21.27#ibcon#about to read 4, iclass 13, count 0 2006.218.07:20:21.27#ibcon#read 4, iclass 13, count 0 2006.218.07:20:21.27#ibcon#about to read 5, iclass 13, count 0 2006.218.07:20:21.27#ibcon#read 5, iclass 13, count 0 2006.218.07:20:21.27#ibcon#about to read 6, iclass 13, count 0 2006.218.07:20:21.27#ibcon#read 6, iclass 13, count 0 2006.218.07:20:21.27#ibcon#end of sib2, iclass 13, count 0 2006.218.07:20:21.27#ibcon#*after write, iclass 13, count 0 2006.218.07:20:21.27#ibcon#*before return 0, iclass 13, count 0 2006.218.07:20:21.27#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.218.07:20:21.27#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.218.07:20:21.27#ibcon#about to clear, iclass 13 cls_cnt 0 2006.218.07:20:21.27#ibcon#cleared, iclass 13 cls_cnt 0 2006.218.07:20:21.27$vc4f8/vblo=5,744.99 2006.218.07:20:21.27#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.218.07:20:21.27#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.218.07:20:21.27#ibcon#ireg 17 cls_cnt 0 2006.218.07:20:21.27#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.218.07:20:21.27#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.218.07:20:21.27#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.218.07:20:21.27#ibcon#enter wrdev, iclass 15, count 0 2006.218.07:20:21.27#ibcon#first serial, iclass 15, count 0 2006.218.07:20:21.27#ibcon#enter sib2, iclass 15, count 0 2006.218.07:20:21.27#ibcon#flushed, iclass 15, count 0 2006.218.07:20:21.27#ibcon#about to write, iclass 15, count 0 2006.218.07:20:21.27#ibcon#wrote, iclass 15, count 0 2006.218.07:20:21.27#ibcon#about to read 3, iclass 15, count 0 2006.218.07:20:21.30#ibcon#read 3, iclass 15, count 0 2006.218.07:20:21.30#ibcon#about to read 4, iclass 15, count 0 2006.218.07:20:21.30#ibcon#read 4, iclass 15, count 0 2006.218.07:20:21.30#ibcon#about to read 5, iclass 15, count 0 2006.218.07:20:21.30#ibcon#read 5, iclass 15, count 0 2006.218.07:20:21.30#ibcon#about to read 6, iclass 15, count 0 2006.218.07:20:21.30#ibcon#read 6, iclass 15, count 0 2006.218.07:20:21.30#ibcon#end of sib2, iclass 15, count 0 2006.218.07:20:21.30#ibcon#*mode == 0, iclass 15, count 0 2006.218.07:20:21.30#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.218.07:20:21.30#ibcon#[28=FRQ=05,744.99\r\n] 2006.218.07:20:21.30#ibcon#*before write, iclass 15, count 0 2006.218.07:20:21.30#ibcon#enter sib2, iclass 15, count 0 2006.218.07:20:21.30#ibcon#flushed, iclass 15, count 0 2006.218.07:20:21.30#ibcon#about to write, iclass 15, count 0 2006.218.07:20:21.30#ibcon#wrote, iclass 15, count 0 2006.218.07:20:21.30#ibcon#about to read 3, iclass 15, count 0 2006.218.07:20:21.34#ibcon#read 3, iclass 15, count 0 2006.218.07:20:21.34#ibcon#about to read 4, iclass 15, count 0 2006.218.07:20:21.34#ibcon#read 4, iclass 15, count 0 2006.218.07:20:21.34#ibcon#about to read 5, iclass 15, count 0 2006.218.07:20:21.34#ibcon#read 5, iclass 15, count 0 2006.218.07:20:21.34#ibcon#about to read 6, iclass 15, count 0 2006.218.07:20:21.34#ibcon#read 6, iclass 15, count 0 2006.218.07:20:21.34#ibcon#end of sib2, iclass 15, count 0 2006.218.07:20:21.34#ibcon#*after write, iclass 15, count 0 2006.218.07:20:21.34#ibcon#*before return 0, iclass 15, count 0 2006.218.07:20:21.34#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.218.07:20:21.34#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.218.07:20:21.34#ibcon#about to clear, iclass 15 cls_cnt 0 2006.218.07:20:21.34#ibcon#cleared, iclass 15 cls_cnt 0 2006.218.07:20:21.34$vc4f8/vb=5,4 2006.218.07:20:21.34#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.218.07:20:21.34#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.218.07:20:21.34#ibcon#ireg 11 cls_cnt 2 2006.218.07:20:21.34#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.218.07:20:21.39#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.218.07:20:21.39#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.218.07:20:21.39#ibcon#enter wrdev, iclass 17, count 2 2006.218.07:20:21.39#ibcon#first serial, iclass 17, count 2 2006.218.07:20:21.39#ibcon#enter sib2, iclass 17, count 2 2006.218.07:20:21.39#ibcon#flushed, iclass 17, count 2 2006.218.07:20:21.39#ibcon#about to write, iclass 17, count 2 2006.218.07:20:21.39#ibcon#wrote, iclass 17, count 2 2006.218.07:20:21.39#ibcon#about to read 3, iclass 17, count 2 2006.218.07:20:21.41#ibcon#read 3, iclass 17, count 2 2006.218.07:20:21.41#ibcon#about to read 4, iclass 17, count 2 2006.218.07:20:21.41#ibcon#read 4, iclass 17, count 2 2006.218.07:20:21.41#ibcon#about to read 5, iclass 17, count 2 2006.218.07:20:21.41#ibcon#read 5, iclass 17, count 2 2006.218.07:20:21.41#ibcon#about to read 6, iclass 17, count 2 2006.218.07:20:21.41#ibcon#read 6, iclass 17, count 2 2006.218.07:20:21.41#ibcon#end of sib2, iclass 17, count 2 2006.218.07:20:21.41#ibcon#*mode == 0, iclass 17, count 2 2006.218.07:20:21.41#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.218.07:20:21.41#ibcon#[27=AT05-04\r\n] 2006.218.07:20:21.41#ibcon#*before write, iclass 17, count 2 2006.218.07:20:21.41#ibcon#enter sib2, iclass 17, count 2 2006.218.07:20:21.41#ibcon#flushed, iclass 17, count 2 2006.218.07:20:21.41#ibcon#about to write, iclass 17, count 2 2006.218.07:20:21.41#ibcon#wrote, iclass 17, count 2 2006.218.07:20:21.41#ibcon#about to read 3, iclass 17, count 2 2006.218.07:20:21.44#ibcon#read 3, iclass 17, count 2 2006.218.07:20:21.44#ibcon#about to read 4, iclass 17, count 2 2006.218.07:20:21.44#ibcon#read 4, iclass 17, count 2 2006.218.07:20:21.44#ibcon#about to read 5, iclass 17, count 2 2006.218.07:20:21.44#ibcon#read 5, iclass 17, count 2 2006.218.07:20:21.44#ibcon#about to read 6, iclass 17, count 2 2006.218.07:20:21.44#ibcon#read 6, iclass 17, count 2 2006.218.07:20:21.44#ibcon#end of sib2, iclass 17, count 2 2006.218.07:20:21.44#ibcon#*after write, iclass 17, count 2 2006.218.07:20:21.44#ibcon#*before return 0, iclass 17, count 2 2006.218.07:20:21.44#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.218.07:20:21.44#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.218.07:20:21.44#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.218.07:20:21.44#ibcon#ireg 7 cls_cnt 0 2006.218.07:20:21.44#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.218.07:20:21.56#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.218.07:20:21.56#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.218.07:20:21.56#ibcon#enter wrdev, iclass 17, count 0 2006.218.07:20:21.56#ibcon#first serial, iclass 17, count 0 2006.218.07:20:21.56#ibcon#enter sib2, iclass 17, count 0 2006.218.07:20:21.56#ibcon#flushed, iclass 17, count 0 2006.218.07:20:21.56#ibcon#about to write, iclass 17, count 0 2006.218.07:20:21.56#ibcon#wrote, iclass 17, count 0 2006.218.07:20:21.56#ibcon#about to read 3, iclass 17, count 0 2006.218.07:20:21.58#ibcon#read 3, iclass 17, count 0 2006.218.07:20:21.58#ibcon#about to read 4, iclass 17, count 0 2006.218.07:20:21.58#ibcon#read 4, iclass 17, count 0 2006.218.07:20:21.58#ibcon#about to read 5, iclass 17, count 0 2006.218.07:20:21.58#ibcon#read 5, iclass 17, count 0 2006.218.07:20:21.58#ibcon#about to read 6, iclass 17, count 0 2006.218.07:20:21.58#ibcon#read 6, iclass 17, count 0 2006.218.07:20:21.58#ibcon#end of sib2, iclass 17, count 0 2006.218.07:20:21.58#ibcon#*mode == 0, iclass 17, count 0 2006.218.07:20:21.58#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.218.07:20:21.58#ibcon#[27=USB\r\n] 2006.218.07:20:21.58#ibcon#*before write, iclass 17, count 0 2006.218.07:20:21.58#ibcon#enter sib2, iclass 17, count 0 2006.218.07:20:21.58#ibcon#flushed, iclass 17, count 0 2006.218.07:20:21.58#ibcon#about to write, iclass 17, count 0 2006.218.07:20:21.58#ibcon#wrote, iclass 17, count 0 2006.218.07:20:21.58#ibcon#about to read 3, iclass 17, count 0 2006.218.07:20:21.61#ibcon#read 3, iclass 17, count 0 2006.218.07:20:21.61#ibcon#about to read 4, iclass 17, count 0 2006.218.07:20:21.61#ibcon#read 4, iclass 17, count 0 2006.218.07:20:21.61#ibcon#about to read 5, iclass 17, count 0 2006.218.07:20:21.61#ibcon#read 5, iclass 17, count 0 2006.218.07:20:21.61#ibcon#about to read 6, iclass 17, count 0 2006.218.07:20:21.61#ibcon#read 6, iclass 17, count 0 2006.218.07:20:21.61#ibcon#end of sib2, iclass 17, count 0 2006.218.07:20:21.61#ibcon#*after write, iclass 17, count 0 2006.218.07:20:21.61#ibcon#*before return 0, iclass 17, count 0 2006.218.07:20:21.61#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.218.07:20:21.61#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.218.07:20:21.61#ibcon#about to clear, iclass 17 cls_cnt 0 2006.218.07:20:21.61#ibcon#cleared, iclass 17 cls_cnt 0 2006.218.07:20:21.61$vc4f8/vblo=6,752.99 2006.218.07:20:21.61#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.218.07:20:21.61#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.218.07:20:21.61#ibcon#ireg 17 cls_cnt 0 2006.218.07:20:21.61#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.218.07:20:21.61#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.218.07:20:21.61#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.218.07:20:21.61#ibcon#enter wrdev, iclass 19, count 0 2006.218.07:20:21.61#ibcon#first serial, iclass 19, count 0 2006.218.07:20:21.61#ibcon#enter sib2, iclass 19, count 0 2006.218.07:20:21.61#ibcon#flushed, iclass 19, count 0 2006.218.07:20:21.61#ibcon#about to write, iclass 19, count 0 2006.218.07:20:21.61#ibcon#wrote, iclass 19, count 0 2006.218.07:20:21.61#ibcon#about to read 3, iclass 19, count 0 2006.218.07:20:21.63#ibcon#read 3, iclass 19, count 0 2006.218.07:20:21.63#ibcon#about to read 4, iclass 19, count 0 2006.218.07:20:21.63#ibcon#read 4, iclass 19, count 0 2006.218.07:20:21.63#ibcon#about to read 5, iclass 19, count 0 2006.218.07:20:21.63#ibcon#read 5, iclass 19, count 0 2006.218.07:20:21.63#ibcon#about to read 6, iclass 19, count 0 2006.218.07:20:21.63#ibcon#read 6, iclass 19, count 0 2006.218.07:20:21.63#ibcon#end of sib2, iclass 19, count 0 2006.218.07:20:21.63#ibcon#*mode == 0, iclass 19, count 0 2006.218.07:20:21.63#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.218.07:20:21.63#ibcon#[28=FRQ=06,752.99\r\n] 2006.218.07:20:21.63#ibcon#*before write, iclass 19, count 0 2006.218.07:20:21.63#ibcon#enter sib2, iclass 19, count 0 2006.218.07:20:21.63#ibcon#flushed, iclass 19, count 0 2006.218.07:20:21.63#ibcon#about to write, iclass 19, count 0 2006.218.07:20:21.63#ibcon#wrote, iclass 19, count 0 2006.218.07:20:21.63#ibcon#about to read 3, iclass 19, count 0 2006.218.07:20:21.67#ibcon#read 3, iclass 19, count 0 2006.218.07:20:21.67#ibcon#about to read 4, iclass 19, count 0 2006.218.07:20:21.67#ibcon#read 4, iclass 19, count 0 2006.218.07:20:21.67#ibcon#about to read 5, iclass 19, count 0 2006.218.07:20:21.67#ibcon#read 5, iclass 19, count 0 2006.218.07:20:21.67#ibcon#about to read 6, iclass 19, count 0 2006.218.07:20:21.67#ibcon#read 6, iclass 19, count 0 2006.218.07:20:21.67#ibcon#end of sib2, iclass 19, count 0 2006.218.07:20:21.67#ibcon#*after write, iclass 19, count 0 2006.218.07:20:21.67#ibcon#*before return 0, iclass 19, count 0 2006.218.07:20:21.67#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.218.07:20:21.67#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.218.07:20:21.67#ibcon#about to clear, iclass 19 cls_cnt 0 2006.218.07:20:21.67#ibcon#cleared, iclass 19 cls_cnt 0 2006.218.07:20:21.67$vc4f8/vb=6,4 2006.218.07:20:21.67#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.218.07:20:21.67#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.218.07:20:21.67#ibcon#ireg 11 cls_cnt 2 2006.218.07:20:21.67#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.218.07:20:21.73#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.218.07:20:21.73#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.218.07:20:21.73#ibcon#enter wrdev, iclass 21, count 2 2006.218.07:20:21.73#ibcon#first serial, iclass 21, count 2 2006.218.07:20:21.73#ibcon#enter sib2, iclass 21, count 2 2006.218.07:20:21.73#ibcon#flushed, iclass 21, count 2 2006.218.07:20:21.73#ibcon#about to write, iclass 21, count 2 2006.218.07:20:21.73#ibcon#wrote, iclass 21, count 2 2006.218.07:20:21.73#ibcon#about to read 3, iclass 21, count 2 2006.218.07:20:21.75#ibcon#read 3, iclass 21, count 2 2006.218.07:20:21.75#ibcon#about to read 4, iclass 21, count 2 2006.218.07:20:21.75#ibcon#read 4, iclass 21, count 2 2006.218.07:20:21.75#ibcon#about to read 5, iclass 21, count 2 2006.218.07:20:21.75#ibcon#read 5, iclass 21, count 2 2006.218.07:20:21.75#ibcon#about to read 6, iclass 21, count 2 2006.218.07:20:21.75#ibcon#read 6, iclass 21, count 2 2006.218.07:20:21.75#ibcon#end of sib2, iclass 21, count 2 2006.218.07:20:21.75#ibcon#*mode == 0, iclass 21, count 2 2006.218.07:20:21.75#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.218.07:20:21.75#ibcon#[27=AT06-04\r\n] 2006.218.07:20:21.75#ibcon#*before write, iclass 21, count 2 2006.218.07:20:21.75#ibcon#enter sib2, iclass 21, count 2 2006.218.07:20:21.75#ibcon#flushed, iclass 21, count 2 2006.218.07:20:21.75#ibcon#about to write, iclass 21, count 2 2006.218.07:20:21.75#ibcon#wrote, iclass 21, count 2 2006.218.07:20:21.75#ibcon#about to read 3, iclass 21, count 2 2006.218.07:20:21.78#ibcon#read 3, iclass 21, count 2 2006.218.07:20:21.78#ibcon#about to read 4, iclass 21, count 2 2006.218.07:20:21.78#ibcon#read 4, iclass 21, count 2 2006.218.07:20:21.78#ibcon#about to read 5, iclass 21, count 2 2006.218.07:20:21.78#ibcon#read 5, iclass 21, count 2 2006.218.07:20:21.78#ibcon#about to read 6, iclass 21, count 2 2006.218.07:20:21.78#ibcon#read 6, iclass 21, count 2 2006.218.07:20:21.78#ibcon#end of sib2, iclass 21, count 2 2006.218.07:20:21.78#ibcon#*after write, iclass 21, count 2 2006.218.07:20:21.78#ibcon#*before return 0, iclass 21, count 2 2006.218.07:20:21.78#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.218.07:20:21.78#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.218.07:20:21.78#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.218.07:20:21.78#ibcon#ireg 7 cls_cnt 0 2006.218.07:20:21.78#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.218.07:20:21.90#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.218.07:20:21.90#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.218.07:20:21.90#ibcon#enter wrdev, iclass 21, count 0 2006.218.07:20:21.90#ibcon#first serial, iclass 21, count 0 2006.218.07:20:21.90#ibcon#enter sib2, iclass 21, count 0 2006.218.07:20:21.90#ibcon#flushed, iclass 21, count 0 2006.218.07:20:21.90#ibcon#about to write, iclass 21, count 0 2006.218.07:20:21.90#ibcon#wrote, iclass 21, count 0 2006.218.07:20:21.90#ibcon#about to read 3, iclass 21, count 0 2006.218.07:20:21.92#ibcon#read 3, iclass 21, count 0 2006.218.07:20:21.92#ibcon#about to read 4, iclass 21, count 0 2006.218.07:20:21.92#ibcon#read 4, iclass 21, count 0 2006.218.07:20:21.92#ibcon#about to read 5, iclass 21, count 0 2006.218.07:20:21.92#ibcon#read 5, iclass 21, count 0 2006.218.07:20:21.92#ibcon#about to read 6, iclass 21, count 0 2006.218.07:20:21.92#ibcon#read 6, iclass 21, count 0 2006.218.07:20:21.92#ibcon#end of sib2, iclass 21, count 0 2006.218.07:20:21.92#ibcon#*mode == 0, iclass 21, count 0 2006.218.07:20:21.92#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.218.07:20:21.92#ibcon#[27=USB\r\n] 2006.218.07:20:21.92#ibcon#*before write, iclass 21, count 0 2006.218.07:20:21.92#ibcon#enter sib2, iclass 21, count 0 2006.218.07:20:21.92#ibcon#flushed, iclass 21, count 0 2006.218.07:20:21.92#ibcon#about to write, iclass 21, count 0 2006.218.07:20:21.92#ibcon#wrote, iclass 21, count 0 2006.218.07:20:21.92#ibcon#about to read 3, iclass 21, count 0 2006.218.07:20:21.95#ibcon#read 3, iclass 21, count 0 2006.218.07:20:21.95#ibcon#about to read 4, iclass 21, count 0 2006.218.07:20:21.95#ibcon#read 4, iclass 21, count 0 2006.218.07:20:21.95#ibcon#about to read 5, iclass 21, count 0 2006.218.07:20:21.95#ibcon#read 5, iclass 21, count 0 2006.218.07:20:21.95#ibcon#about to read 6, iclass 21, count 0 2006.218.07:20:21.95#ibcon#read 6, iclass 21, count 0 2006.218.07:20:21.95#ibcon#end of sib2, iclass 21, count 0 2006.218.07:20:21.95#ibcon#*after write, iclass 21, count 0 2006.218.07:20:21.95#ibcon#*before return 0, iclass 21, count 0 2006.218.07:20:21.95#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.218.07:20:21.95#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.218.07:20:21.95#ibcon#about to clear, iclass 21 cls_cnt 0 2006.218.07:20:21.95#ibcon#cleared, iclass 21 cls_cnt 0 2006.218.07:20:21.95$vc4f8/vabw=wide 2006.218.07:20:21.95#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.218.07:20:21.95#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.218.07:20:21.95#ibcon#ireg 8 cls_cnt 0 2006.218.07:20:21.95#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.218.07:20:21.95#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.218.07:20:21.95#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.218.07:20:21.95#ibcon#enter wrdev, iclass 23, count 0 2006.218.07:20:21.95#ibcon#first serial, iclass 23, count 0 2006.218.07:20:21.95#ibcon#enter sib2, iclass 23, count 0 2006.218.07:20:21.95#ibcon#flushed, iclass 23, count 0 2006.218.07:20:21.95#ibcon#about to write, iclass 23, count 0 2006.218.07:20:21.95#ibcon#wrote, iclass 23, count 0 2006.218.07:20:21.95#ibcon#about to read 3, iclass 23, count 0 2006.218.07:20:21.97#ibcon#read 3, iclass 23, count 0 2006.218.07:20:21.97#ibcon#about to read 4, iclass 23, count 0 2006.218.07:20:21.97#ibcon#read 4, iclass 23, count 0 2006.218.07:20:21.97#ibcon#about to read 5, iclass 23, count 0 2006.218.07:20:21.97#ibcon#read 5, iclass 23, count 0 2006.218.07:20:21.97#ibcon#about to read 6, iclass 23, count 0 2006.218.07:20:21.97#ibcon#read 6, iclass 23, count 0 2006.218.07:20:21.97#ibcon#end of sib2, iclass 23, count 0 2006.218.07:20:21.97#ibcon#*mode == 0, iclass 23, count 0 2006.218.07:20:21.97#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.218.07:20:21.97#ibcon#[25=BW32\r\n] 2006.218.07:20:21.97#ibcon#*before write, iclass 23, count 0 2006.218.07:20:21.97#ibcon#enter sib2, iclass 23, count 0 2006.218.07:20:21.97#ibcon#flushed, iclass 23, count 0 2006.218.07:20:21.97#ibcon#about to write, iclass 23, count 0 2006.218.07:20:21.97#ibcon#wrote, iclass 23, count 0 2006.218.07:20:21.97#ibcon#about to read 3, iclass 23, count 0 2006.218.07:20:22.00#ibcon#read 3, iclass 23, count 0 2006.218.07:20:22.00#ibcon#about to read 4, iclass 23, count 0 2006.218.07:20:22.00#ibcon#read 4, iclass 23, count 0 2006.218.07:20:22.00#ibcon#about to read 5, iclass 23, count 0 2006.218.07:20:22.00#ibcon#read 5, iclass 23, count 0 2006.218.07:20:22.00#ibcon#about to read 6, iclass 23, count 0 2006.218.07:20:22.00#ibcon#read 6, iclass 23, count 0 2006.218.07:20:22.00#ibcon#end of sib2, iclass 23, count 0 2006.218.07:20:22.00#ibcon#*after write, iclass 23, count 0 2006.218.07:20:22.00#ibcon#*before return 0, iclass 23, count 0 2006.218.07:20:22.00#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.218.07:20:22.00#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.218.07:20:22.00#ibcon#about to clear, iclass 23 cls_cnt 0 2006.218.07:20:22.00#ibcon#cleared, iclass 23 cls_cnt 0 2006.218.07:20:22.00$vc4f8/vbbw=wide 2006.218.07:20:22.00#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.218.07:20:22.00#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.218.07:20:22.00#ibcon#ireg 8 cls_cnt 0 2006.218.07:20:22.00#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.218.07:20:22.07#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.218.07:20:22.07#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.218.07:20:22.07#ibcon#enter wrdev, iclass 25, count 0 2006.218.07:20:22.07#ibcon#first serial, iclass 25, count 0 2006.218.07:20:22.07#ibcon#enter sib2, iclass 25, count 0 2006.218.07:20:22.07#ibcon#flushed, iclass 25, count 0 2006.218.07:20:22.07#ibcon#about to write, iclass 25, count 0 2006.218.07:20:22.07#ibcon#wrote, iclass 25, count 0 2006.218.07:20:22.07#ibcon#about to read 3, iclass 25, count 0 2006.218.07:20:22.09#ibcon#read 3, iclass 25, count 0 2006.218.07:20:22.09#ibcon#about to read 4, iclass 25, count 0 2006.218.07:20:22.09#ibcon#read 4, iclass 25, count 0 2006.218.07:20:22.09#ibcon#about to read 5, iclass 25, count 0 2006.218.07:20:22.09#ibcon#read 5, iclass 25, count 0 2006.218.07:20:22.09#ibcon#about to read 6, iclass 25, count 0 2006.218.07:20:22.09#ibcon#read 6, iclass 25, count 0 2006.218.07:20:22.09#ibcon#end of sib2, iclass 25, count 0 2006.218.07:20:22.09#ibcon#*mode == 0, iclass 25, count 0 2006.218.07:20:22.09#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.218.07:20:22.09#ibcon#[27=BW32\r\n] 2006.218.07:20:22.09#ibcon#*before write, iclass 25, count 0 2006.218.07:20:22.09#ibcon#enter sib2, iclass 25, count 0 2006.218.07:20:22.09#ibcon#flushed, iclass 25, count 0 2006.218.07:20:22.09#ibcon#about to write, iclass 25, count 0 2006.218.07:20:22.09#ibcon#wrote, iclass 25, count 0 2006.218.07:20:22.09#ibcon#about to read 3, iclass 25, count 0 2006.218.07:20:22.12#ibcon#read 3, iclass 25, count 0 2006.218.07:20:22.12#ibcon#about to read 4, iclass 25, count 0 2006.218.07:20:22.12#ibcon#read 4, iclass 25, count 0 2006.218.07:20:22.12#ibcon#about to read 5, iclass 25, count 0 2006.218.07:20:22.12#ibcon#read 5, iclass 25, count 0 2006.218.07:20:22.12#ibcon#about to read 6, iclass 25, count 0 2006.218.07:20:22.12#ibcon#read 6, iclass 25, count 0 2006.218.07:20:22.12#ibcon#end of sib2, iclass 25, count 0 2006.218.07:20:22.12#ibcon#*after write, iclass 25, count 0 2006.218.07:20:22.12#ibcon#*before return 0, iclass 25, count 0 2006.218.07:20:22.12#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.218.07:20:22.12#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.218.07:20:22.12#ibcon#about to clear, iclass 25 cls_cnt 0 2006.218.07:20:22.12#ibcon#cleared, iclass 25 cls_cnt 0 2006.218.07:20:22.12$4f8m12a/ifd4f 2006.218.07:20:22.12&ifd4f/lo= 2006.218.07:20:22.12&ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.218.07:20:22.12&ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.218.07:20:22.12&ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.218.07:20:22.12&ifd4f/patch= 2006.218.07:20:22.12&ifd4f/patch=lo1,a1,a2,a3,a4 2006.218.07:20:22.12&ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.218.07:20:22.12&ifd4f/patch=lo3,a5,a6,a7,a8 2006.218.07:20:22.12$ifd4f/lo= 2006.218.07:20:22.12$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.218.07:20:22.12$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.218.07:20:22.12$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.218.07:20:22.12$ifd4f/patch= 2006.218.07:20:22.12$ifd4f/patch=lo1,a1,a2,a3,a4 2006.218.07:20:22.12$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.218.07:20:22.12$ifd4f/patch=lo3,a5,a6,a7,a8 2006.218.07:20:22.13$4f8m12a/"form=m,16.000,1:2 2006.218.07:20:22.13$4f8m12a/"tpicd 2006.218.07:20:22.13$4f8m12a/echo=off 2006.218.07:20:22.13$4f8m12a/xlog=off 2006.218.07:20:22.13:!2006.218.07:29:50 2006.218.07:20:41.13#trakl#Source acquired 2006.218.07:20:41.13#flagr#flagr/antenna,acquired 2006.218.07:29:50.00:preob 2006.218.07:29:50.00&preob/onsource 2006.218.07:29:51.13/onsource/TRACKING 2006.218.07:29:51.13:!2006.218.07:30:00 2006.218.07:30:00.00:data_valid=on 2006.218.07:30:00.00:midob 2006.218.07:30:00.00&midob/onsource 2006.218.07:30:00.00&midob/wx 2006.218.07:30:00.00&midob/cable 2006.218.07:30:00.00&midob/va 2006.218.07:30:00.00&midob/valo 2006.218.07:30:00.00&midob/vb 2006.218.07:30:00.00&midob/vblo 2006.218.07:30:00.00&midob/vabw 2006.218.07:30:00.00&midob/vbbw 2006.218.07:30:00.00&midob/"form 2006.218.07:30:00.00&midob/xfe 2006.218.07:30:00.00&midob/ifatt 2006.218.07:30:00.00&midob/clockoff 2006.218.07:30:00.00&midob/sy=logmail 2006.218.07:30:00.00&midob/"sy=run setcl adapt & 2006.218.07:30:00.14/onsource/TRACKING 2006.218.07:30:00.14/wx/31.81,1007.4,71 2006.218.07:30:00.30/cable/+6.3825E-03 2006.218.07:30:01.39/va/01,05,usb,yes,34,36 2006.218.07:30:01.39/va/02,04,usb,yes,32,33 2006.218.07:30:01.39/va/03,04,usb,yes,30,30 2006.218.07:30:01.39/va/04,04,usb,yes,33,36 2006.218.07:30:01.39/va/05,07,usb,yes,35,38 2006.218.07:30:01.39/va/06,06,usb,yes,35,34 2006.218.07:30:01.39/va/07,06,usb,yes,35,35 2006.218.07:30:01.39/va/08,07,usb,yes,33,33 2006.218.07:30:01.62/valo/01,532.99,yes,locked 2006.218.07:30:01.62/valo/02,572.99,yes,locked 2006.218.07:30:01.62/valo/03,672.99,yes,locked 2006.218.07:30:01.62/valo/04,832.99,yes,locked 2006.218.07:30:01.62/valo/05,652.99,yes,locked 2006.218.07:30:01.62/valo/06,772.99,yes,locked 2006.218.07:30:01.62/valo/07,832.99,yes,locked 2006.218.07:30:01.62/valo/08,852.99,yes,locked 2006.218.07:30:02.71/vb/01,04,usb,yes,32,30 2006.218.07:30:02.71/vb/02,04,usb,yes,34,35 2006.218.07:30:02.71/vb/03,04,usb,yes,30,34 2006.218.07:30:02.71/vb/04,04,usb,yes,31,31 2006.218.07:30:02.71/vb/05,04,usb,yes,29,33 2006.218.07:30:02.71/vb/06,04,usb,yes,30,33 2006.218.07:30:02.71/vb/07,04,usb,yes,33,32 2006.218.07:30:02.71/vb/08,04,usb,yes,30,34 2006.218.07:30:02.94/vblo/01,632.99,yes,locked 2006.218.07:30:02.94/vblo/02,640.99,yes,locked 2006.218.07:30:02.94/vblo/03,656.99,yes,locked 2006.218.07:30:02.94/vblo/04,712.99,yes,locked 2006.218.07:30:02.94/vblo/05,744.99,yes,locked 2006.218.07:30:02.94/vblo/06,752.99,yes,locked 2006.218.07:30:02.94/vblo/07,734.99,yes,locked 2006.218.07:30:02.94/vblo/08,744.99,yes,locked 2006.218.07:30:03.09/vabw/8 2006.218.07:30:03.24/vbbw/8 2006.218.07:30:03.38/xfe/off,on,15.7 2006.218.07:30:03.76/ifatt/23,28,28,28 2006.218.07:30:03.76&clockoff/"gps-fmout=1p 2006.218.07:30:03.76&clockoff/fmout-gps=1p 2006.218.07:30:04.07/fmout-gps/S +4.69E-07 2006.218.07:30:04.16:!2006.218.07:31:00 2006.218.07:31:00.01:data_valid=off 2006.218.07:31:00.01:postob 2006.218.07:31:00.02&postob/cable 2006.218.07:31:00.02&postob/wx 2006.218.07:31:00.02&postob/clockoff 2006.218.07:31:00.21/cable/+6.3833E-03 2006.218.07:31:00.21/wx/31.77,1007.4,72 2006.218.07:31:00.29/fmout-gps/S +4.71E-07 2006.218.07:31:00.30:scan_name=218-0733,k06218,60 2006.218.07:31:00.30:source=0823+033,082550.34,030924.5,2000.0,ccw 2006.218.07:31:01.14#flagr#flagr/antenna,new-source 2006.218.07:31:01.14:checkk5 2006.218.07:31:01.15&checkk5/chk_autoobs=1 2006.218.07:31:01.15&checkk5/chk_autoobs=2 2006.218.07:31:01.15&checkk5/chk_autoobs=3 2006.218.07:31:01.15&checkk5/chk_autoobs=4 2006.218.07:31:01.15&checkk5/chk_obsdata=1 2006.218.07:31:01.15&checkk5/chk_obsdata=2 2006.218.07:31:01.15&checkk5/chk_obsdata=3 2006.218.07:31:01.15&checkk5/chk_obsdata=4 2006.218.07:31:01.15&checkk5/k5log=1 2006.218.07:31:01.15&checkk5/k5log=2 2006.218.07:31:01.15&checkk5/k5log=3 2006.218.07:31:01.15&checkk5/k5log=4 2006.218.07:31:01.15&checkk5/obsinfo 2006.218.07:31:01.55/chk_autoobs//k5ts1/ autoobs is running! 2006.218.07:31:01.93/chk_autoobs//k5ts2/ autoobs is running! 2006.218.07:31:02.30/chk_autoobs//k5ts3/ autoobs is running! 2006.218.07:31:02.69/chk_autoobs//k5ts4/ autoobs is running! 2006.218.07:31:03.07/chk_obsdata//k5ts1/T2180730??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:31:03.44/chk_obsdata//k5ts2/T2180730??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:31:03.81/chk_obsdata//k5ts3/T2180730??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:31:04.19/chk_obsdata//k5ts4/T2180730??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:31:04.90/k5log//k5ts1_log_newline 2006.218.07:31:05.58/k5log//k5ts2_log_newline 2006.218.07:31:06.28/k5log//k5ts3_log_newline 2006.218.07:31:06.97/k5log//k5ts4_log_newline 2006.218.07:31:06.99/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.218.07:31:06.99:4f8m12a=1 2006.218.07:31:06.99$4f8m12a/echo=on 2006.218.07:31:06.99$4f8m12a/pcalon 2006.218.07:31:06.99$pcalon/"no phase cal control is implemented here 2006.218.07:31:06.99$4f8m12a/"tpicd=stop 2006.218.07:31:06.99$4f8m12a/vc4f8 2006.218.07:31:06.99$vc4f8/valo=1,532.99 2006.218.07:31:06.99#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.218.07:31:06.99#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.218.07:31:06.99#ibcon#ireg 17 cls_cnt 0 2006.218.07:31:06.99#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.218.07:31:06.99#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.218.07:31:06.99#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.218.07:31:06.99#ibcon#enter wrdev, iclass 28, count 0 2006.218.07:31:06.99#ibcon#first serial, iclass 28, count 0 2006.218.07:31:06.99#ibcon#enter sib2, iclass 28, count 0 2006.218.07:31:06.99#ibcon#flushed, iclass 28, count 0 2006.218.07:31:06.99#ibcon#about to write, iclass 28, count 0 2006.218.07:31:06.99#ibcon#wrote, iclass 28, count 0 2006.218.07:31:06.99#ibcon#about to read 3, iclass 28, count 0 2006.218.07:31:07.01#ibcon#read 3, iclass 28, count 0 2006.218.07:31:07.01#ibcon#about to read 4, iclass 28, count 0 2006.218.07:31:07.01#ibcon#read 4, iclass 28, count 0 2006.218.07:31:07.01#ibcon#about to read 5, iclass 28, count 0 2006.218.07:31:07.01#ibcon#read 5, iclass 28, count 0 2006.218.07:31:07.01#ibcon#about to read 6, iclass 28, count 0 2006.218.07:31:07.01#ibcon#read 6, iclass 28, count 0 2006.218.07:31:07.01#ibcon#end of sib2, iclass 28, count 0 2006.218.07:31:07.01#ibcon#*mode == 0, iclass 28, count 0 2006.218.07:31:07.01#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.218.07:31:07.01#ibcon#[26=FRQ=01,532.99\r\n] 2006.218.07:31:07.01#ibcon#*before write, iclass 28, count 0 2006.218.07:31:07.01#ibcon#enter sib2, iclass 28, count 0 2006.218.07:31:07.01#ibcon#flushed, iclass 28, count 0 2006.218.07:31:07.01#ibcon#about to write, iclass 28, count 0 2006.218.07:31:07.01#ibcon#wrote, iclass 28, count 0 2006.218.07:31:07.01#ibcon#about to read 3, iclass 28, count 0 2006.218.07:31:07.06#ibcon#read 3, iclass 28, count 0 2006.218.07:31:07.06#ibcon#about to read 4, iclass 28, count 0 2006.218.07:31:07.06#ibcon#read 4, iclass 28, count 0 2006.218.07:31:07.06#ibcon#about to read 5, iclass 28, count 0 2006.218.07:31:07.06#ibcon#read 5, iclass 28, count 0 2006.218.07:31:07.06#ibcon#about to read 6, iclass 28, count 0 2006.218.07:31:07.06#ibcon#read 6, iclass 28, count 0 2006.218.07:31:07.06#ibcon#end of sib2, iclass 28, count 0 2006.218.07:31:07.06#ibcon#*after write, iclass 28, count 0 2006.218.07:31:07.06#ibcon#*before return 0, iclass 28, count 0 2006.218.07:31:07.06#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.218.07:31:07.06#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.218.07:31:07.06#ibcon#about to clear, iclass 28 cls_cnt 0 2006.218.07:31:07.06#ibcon#cleared, iclass 28 cls_cnt 0 2006.218.07:31:07.06$vc4f8/va=1,5 2006.218.07:31:07.06#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.218.07:31:07.06#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.218.07:31:07.06#ibcon#ireg 11 cls_cnt 2 2006.218.07:31:07.06#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.218.07:31:07.06#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.218.07:31:07.06#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.218.07:31:07.06#ibcon#enter wrdev, iclass 30, count 2 2006.218.07:31:07.06#ibcon#first serial, iclass 30, count 2 2006.218.07:31:07.06#ibcon#enter sib2, iclass 30, count 2 2006.218.07:31:07.06#ibcon#flushed, iclass 30, count 2 2006.218.07:31:07.06#ibcon#about to write, iclass 30, count 2 2006.218.07:31:07.06#ibcon#wrote, iclass 30, count 2 2006.218.07:31:07.06#ibcon#about to read 3, iclass 30, count 2 2006.218.07:31:07.08#ibcon#read 3, iclass 30, count 2 2006.218.07:31:07.08#ibcon#about to read 4, iclass 30, count 2 2006.218.07:31:07.08#ibcon#read 4, iclass 30, count 2 2006.218.07:31:07.08#ibcon#about to read 5, iclass 30, count 2 2006.218.07:31:07.08#ibcon#read 5, iclass 30, count 2 2006.218.07:31:07.08#ibcon#about to read 6, iclass 30, count 2 2006.218.07:31:07.08#ibcon#read 6, iclass 30, count 2 2006.218.07:31:07.08#ibcon#end of sib2, iclass 30, count 2 2006.218.07:31:07.08#ibcon#*mode == 0, iclass 30, count 2 2006.218.07:31:07.08#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.218.07:31:07.08#ibcon#[25=AT01-05\r\n] 2006.218.07:31:07.08#ibcon#*before write, iclass 30, count 2 2006.218.07:31:07.08#ibcon#enter sib2, iclass 30, count 2 2006.218.07:31:07.08#ibcon#flushed, iclass 30, count 2 2006.218.07:31:07.08#ibcon#about to write, iclass 30, count 2 2006.218.07:31:07.08#ibcon#wrote, iclass 30, count 2 2006.218.07:31:07.08#ibcon#about to read 3, iclass 30, count 2 2006.218.07:31:07.11#ibcon#read 3, iclass 30, count 2 2006.218.07:31:07.11#ibcon#about to read 4, iclass 30, count 2 2006.218.07:31:07.11#ibcon#read 4, iclass 30, count 2 2006.218.07:31:07.11#ibcon#about to read 5, iclass 30, count 2 2006.218.07:31:07.11#ibcon#read 5, iclass 30, count 2 2006.218.07:31:07.11#ibcon#about to read 6, iclass 30, count 2 2006.218.07:31:07.11#ibcon#read 6, iclass 30, count 2 2006.218.07:31:07.11#ibcon#end of sib2, iclass 30, count 2 2006.218.07:31:07.11#ibcon#*after write, iclass 30, count 2 2006.218.07:31:07.11#ibcon#*before return 0, iclass 30, count 2 2006.218.07:31:07.11#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.218.07:31:07.11#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.218.07:31:07.11#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.218.07:31:07.11#ibcon#ireg 7 cls_cnt 0 2006.218.07:31:07.11#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.218.07:31:07.23#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.218.07:31:07.23#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.218.07:31:07.23#ibcon#enter wrdev, iclass 30, count 0 2006.218.07:31:07.23#ibcon#first serial, iclass 30, count 0 2006.218.07:31:07.23#ibcon#enter sib2, iclass 30, count 0 2006.218.07:31:07.23#ibcon#flushed, iclass 30, count 0 2006.218.07:31:07.23#ibcon#about to write, iclass 30, count 0 2006.218.07:31:07.23#ibcon#wrote, iclass 30, count 0 2006.218.07:31:07.23#ibcon#about to read 3, iclass 30, count 0 2006.218.07:31:07.25#ibcon#read 3, iclass 30, count 0 2006.218.07:31:07.25#ibcon#about to read 4, iclass 30, count 0 2006.218.07:31:07.25#ibcon#read 4, iclass 30, count 0 2006.218.07:31:07.25#ibcon#about to read 5, iclass 30, count 0 2006.218.07:31:07.25#ibcon#read 5, iclass 30, count 0 2006.218.07:31:07.25#ibcon#about to read 6, iclass 30, count 0 2006.218.07:31:07.25#ibcon#read 6, iclass 30, count 0 2006.218.07:31:07.25#ibcon#end of sib2, iclass 30, count 0 2006.218.07:31:07.25#ibcon#*mode == 0, iclass 30, count 0 2006.218.07:31:07.25#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.218.07:31:07.25#ibcon#[25=USB\r\n] 2006.218.07:31:07.25#ibcon#*before write, iclass 30, count 0 2006.218.07:31:07.25#ibcon#enter sib2, iclass 30, count 0 2006.218.07:31:07.25#ibcon#flushed, iclass 30, count 0 2006.218.07:31:07.25#ibcon#about to write, iclass 30, count 0 2006.218.07:31:07.25#ibcon#wrote, iclass 30, count 0 2006.218.07:31:07.25#ibcon#about to read 3, iclass 30, count 0 2006.218.07:31:07.28#ibcon#read 3, iclass 30, count 0 2006.218.07:31:07.28#ibcon#about to read 4, iclass 30, count 0 2006.218.07:31:07.28#ibcon#read 4, iclass 30, count 0 2006.218.07:31:07.28#ibcon#about to read 5, iclass 30, count 0 2006.218.07:31:07.28#ibcon#read 5, iclass 30, count 0 2006.218.07:31:07.28#ibcon#about to read 6, iclass 30, count 0 2006.218.07:31:07.28#ibcon#read 6, iclass 30, count 0 2006.218.07:31:07.28#ibcon#end of sib2, iclass 30, count 0 2006.218.07:31:07.28#ibcon#*after write, iclass 30, count 0 2006.218.07:31:07.28#ibcon#*before return 0, iclass 30, count 0 2006.218.07:31:07.28#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.218.07:31:07.28#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.218.07:31:07.28#ibcon#about to clear, iclass 30 cls_cnt 0 2006.218.07:31:07.28#ibcon#cleared, iclass 30 cls_cnt 0 2006.218.07:31:07.28$vc4f8/valo=2,572.99 2006.218.07:31:07.28#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.218.07:31:07.28#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.218.07:31:07.28#ibcon#ireg 17 cls_cnt 0 2006.218.07:31:07.28#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.218.07:31:07.28#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.218.07:31:07.28#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.218.07:31:07.28#ibcon#enter wrdev, iclass 32, count 0 2006.218.07:31:07.28#ibcon#first serial, iclass 32, count 0 2006.218.07:31:07.28#ibcon#enter sib2, iclass 32, count 0 2006.218.07:31:07.28#ibcon#flushed, iclass 32, count 0 2006.218.07:31:07.28#ibcon#about to write, iclass 32, count 0 2006.218.07:31:07.28#ibcon#wrote, iclass 32, count 0 2006.218.07:31:07.28#ibcon#about to read 3, iclass 32, count 0 2006.218.07:31:07.31#ibcon#read 3, iclass 32, count 0 2006.218.07:31:07.31#ibcon#about to read 4, iclass 32, count 0 2006.218.07:31:07.31#ibcon#read 4, iclass 32, count 0 2006.218.07:31:07.31#ibcon#about to read 5, iclass 32, count 0 2006.218.07:31:07.31#ibcon#read 5, iclass 32, count 0 2006.218.07:31:07.31#ibcon#about to read 6, iclass 32, count 0 2006.218.07:31:07.31#ibcon#read 6, iclass 32, count 0 2006.218.07:31:07.31#ibcon#end of sib2, iclass 32, count 0 2006.218.07:31:07.31#ibcon#*mode == 0, iclass 32, count 0 2006.218.07:31:07.31#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.218.07:31:07.31#ibcon#[26=FRQ=02,572.99\r\n] 2006.218.07:31:07.31#ibcon#*before write, iclass 32, count 0 2006.218.07:31:07.31#ibcon#enter sib2, iclass 32, count 0 2006.218.07:31:07.31#ibcon#flushed, iclass 32, count 0 2006.218.07:31:07.31#ibcon#about to write, iclass 32, count 0 2006.218.07:31:07.31#ibcon#wrote, iclass 32, count 0 2006.218.07:31:07.31#ibcon#about to read 3, iclass 32, count 0 2006.218.07:31:07.35#ibcon#read 3, iclass 32, count 0 2006.218.07:31:07.35#ibcon#about to read 4, iclass 32, count 0 2006.218.07:31:07.35#ibcon#read 4, iclass 32, count 0 2006.218.07:31:07.35#ibcon#about to read 5, iclass 32, count 0 2006.218.07:31:07.35#ibcon#read 5, iclass 32, count 0 2006.218.07:31:07.35#ibcon#about to read 6, iclass 32, count 0 2006.218.07:31:07.35#ibcon#read 6, iclass 32, count 0 2006.218.07:31:07.35#ibcon#end of sib2, iclass 32, count 0 2006.218.07:31:07.35#ibcon#*after write, iclass 32, count 0 2006.218.07:31:07.35#ibcon#*before return 0, iclass 32, count 0 2006.218.07:31:07.35#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.218.07:31:07.35#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.218.07:31:07.35#ibcon#about to clear, iclass 32 cls_cnt 0 2006.218.07:31:07.35#ibcon#cleared, iclass 32 cls_cnt 0 2006.218.07:31:07.35$vc4f8/va=2,4 2006.218.07:31:07.35#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.218.07:31:07.35#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.218.07:31:07.35#ibcon#ireg 11 cls_cnt 2 2006.218.07:31:07.35#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.218.07:31:07.40#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.218.07:31:07.40#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.218.07:31:07.40#ibcon#enter wrdev, iclass 34, count 2 2006.218.07:31:07.40#ibcon#first serial, iclass 34, count 2 2006.218.07:31:07.40#ibcon#enter sib2, iclass 34, count 2 2006.218.07:31:07.40#ibcon#flushed, iclass 34, count 2 2006.218.07:31:07.40#ibcon#about to write, iclass 34, count 2 2006.218.07:31:07.40#ibcon#wrote, iclass 34, count 2 2006.218.07:31:07.40#ibcon#about to read 3, iclass 34, count 2 2006.218.07:31:07.42#ibcon#read 3, iclass 34, count 2 2006.218.07:31:07.42#ibcon#about to read 4, iclass 34, count 2 2006.218.07:31:07.42#ibcon#read 4, iclass 34, count 2 2006.218.07:31:07.42#ibcon#about to read 5, iclass 34, count 2 2006.218.07:31:07.42#ibcon#read 5, iclass 34, count 2 2006.218.07:31:07.42#ibcon#about to read 6, iclass 34, count 2 2006.218.07:31:07.42#ibcon#read 6, iclass 34, count 2 2006.218.07:31:07.42#ibcon#end of sib2, iclass 34, count 2 2006.218.07:31:07.42#ibcon#*mode == 0, iclass 34, count 2 2006.218.07:31:07.42#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.218.07:31:07.42#ibcon#[25=AT02-04\r\n] 2006.218.07:31:07.42#ibcon#*before write, iclass 34, count 2 2006.218.07:31:07.42#ibcon#enter sib2, iclass 34, count 2 2006.218.07:31:07.42#ibcon#flushed, iclass 34, count 2 2006.218.07:31:07.42#ibcon#about to write, iclass 34, count 2 2006.218.07:31:07.42#ibcon#wrote, iclass 34, count 2 2006.218.07:31:07.42#ibcon#about to read 3, iclass 34, count 2 2006.218.07:31:07.45#ibcon#read 3, iclass 34, count 2 2006.218.07:31:07.45#ibcon#about to read 4, iclass 34, count 2 2006.218.07:31:07.45#ibcon#read 4, iclass 34, count 2 2006.218.07:31:07.45#ibcon#about to read 5, iclass 34, count 2 2006.218.07:31:07.45#ibcon#read 5, iclass 34, count 2 2006.218.07:31:07.45#ibcon#about to read 6, iclass 34, count 2 2006.218.07:31:07.45#ibcon#read 6, iclass 34, count 2 2006.218.07:31:07.45#ibcon#end of sib2, iclass 34, count 2 2006.218.07:31:07.45#ibcon#*after write, iclass 34, count 2 2006.218.07:31:07.45#ibcon#*before return 0, iclass 34, count 2 2006.218.07:31:07.45#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.218.07:31:07.45#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.218.07:31:07.45#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.218.07:31:07.45#ibcon#ireg 7 cls_cnt 0 2006.218.07:31:07.45#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.218.07:31:07.57#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.218.07:31:07.57#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.218.07:31:07.57#ibcon#enter wrdev, iclass 34, count 0 2006.218.07:31:07.57#ibcon#first serial, iclass 34, count 0 2006.218.07:31:07.57#ibcon#enter sib2, iclass 34, count 0 2006.218.07:31:07.57#ibcon#flushed, iclass 34, count 0 2006.218.07:31:07.57#ibcon#about to write, iclass 34, count 0 2006.218.07:31:07.57#ibcon#wrote, iclass 34, count 0 2006.218.07:31:07.57#ibcon#about to read 3, iclass 34, count 0 2006.218.07:31:07.59#ibcon#read 3, iclass 34, count 0 2006.218.07:31:07.59#ibcon#about to read 4, iclass 34, count 0 2006.218.07:31:07.59#ibcon#read 4, iclass 34, count 0 2006.218.07:31:07.59#ibcon#about to read 5, iclass 34, count 0 2006.218.07:31:07.59#ibcon#read 5, iclass 34, count 0 2006.218.07:31:07.59#ibcon#about to read 6, iclass 34, count 0 2006.218.07:31:07.59#ibcon#read 6, iclass 34, count 0 2006.218.07:31:07.59#ibcon#end of sib2, iclass 34, count 0 2006.218.07:31:07.59#ibcon#*mode == 0, iclass 34, count 0 2006.218.07:31:07.59#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.218.07:31:07.59#ibcon#[25=USB\r\n] 2006.218.07:31:07.59#ibcon#*before write, iclass 34, count 0 2006.218.07:31:07.59#ibcon#enter sib2, iclass 34, count 0 2006.218.07:31:07.59#ibcon#flushed, iclass 34, count 0 2006.218.07:31:07.59#ibcon#about to write, iclass 34, count 0 2006.218.07:31:07.59#ibcon#wrote, iclass 34, count 0 2006.218.07:31:07.59#ibcon#about to read 3, iclass 34, count 0 2006.218.07:31:07.62#ibcon#read 3, iclass 34, count 0 2006.218.07:31:07.62#ibcon#about to read 4, iclass 34, count 0 2006.218.07:31:07.62#ibcon#read 4, iclass 34, count 0 2006.218.07:31:07.62#ibcon#about to read 5, iclass 34, count 0 2006.218.07:31:07.62#ibcon#read 5, iclass 34, count 0 2006.218.07:31:07.62#ibcon#about to read 6, iclass 34, count 0 2006.218.07:31:07.62#ibcon#read 6, iclass 34, count 0 2006.218.07:31:07.62#ibcon#end of sib2, iclass 34, count 0 2006.218.07:31:07.62#ibcon#*after write, iclass 34, count 0 2006.218.07:31:07.62#ibcon#*before return 0, iclass 34, count 0 2006.218.07:31:07.62#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.218.07:31:07.62#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.218.07:31:07.62#ibcon#about to clear, iclass 34 cls_cnt 0 2006.218.07:31:07.62#ibcon#cleared, iclass 34 cls_cnt 0 2006.218.07:31:07.62$vc4f8/valo=3,672.99 2006.218.07:31:07.62#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.218.07:31:07.62#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.218.07:31:07.62#ibcon#ireg 17 cls_cnt 0 2006.218.07:31:07.62#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.218.07:31:07.62#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.218.07:31:07.62#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.218.07:31:07.62#ibcon#enter wrdev, iclass 36, count 0 2006.218.07:31:07.62#ibcon#first serial, iclass 36, count 0 2006.218.07:31:07.62#ibcon#enter sib2, iclass 36, count 0 2006.218.07:31:07.62#ibcon#flushed, iclass 36, count 0 2006.218.07:31:07.62#ibcon#about to write, iclass 36, count 0 2006.218.07:31:07.62#ibcon#wrote, iclass 36, count 0 2006.218.07:31:07.62#ibcon#about to read 3, iclass 36, count 0 2006.218.07:31:07.65#ibcon#read 3, iclass 36, count 0 2006.218.07:31:07.65#ibcon#about to read 4, iclass 36, count 0 2006.218.07:31:07.65#ibcon#read 4, iclass 36, count 0 2006.218.07:31:07.65#ibcon#about to read 5, iclass 36, count 0 2006.218.07:31:07.65#ibcon#read 5, iclass 36, count 0 2006.218.07:31:07.65#ibcon#about to read 6, iclass 36, count 0 2006.218.07:31:07.65#ibcon#read 6, iclass 36, count 0 2006.218.07:31:07.65#ibcon#end of sib2, iclass 36, count 0 2006.218.07:31:07.65#ibcon#*mode == 0, iclass 36, count 0 2006.218.07:31:07.65#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.218.07:31:07.65#ibcon#[26=FRQ=03,672.99\r\n] 2006.218.07:31:07.65#ibcon#*before write, iclass 36, count 0 2006.218.07:31:07.65#ibcon#enter sib2, iclass 36, count 0 2006.218.07:31:07.65#ibcon#flushed, iclass 36, count 0 2006.218.07:31:07.65#ibcon#about to write, iclass 36, count 0 2006.218.07:31:07.65#ibcon#wrote, iclass 36, count 0 2006.218.07:31:07.65#ibcon#about to read 3, iclass 36, count 0 2006.218.07:31:07.69#ibcon#read 3, iclass 36, count 0 2006.218.07:31:07.69#ibcon#about to read 4, iclass 36, count 0 2006.218.07:31:07.69#ibcon#read 4, iclass 36, count 0 2006.218.07:31:07.69#ibcon#about to read 5, iclass 36, count 0 2006.218.07:31:07.69#ibcon#read 5, iclass 36, count 0 2006.218.07:31:07.69#ibcon#about to read 6, iclass 36, count 0 2006.218.07:31:07.69#ibcon#read 6, iclass 36, count 0 2006.218.07:31:07.69#ibcon#end of sib2, iclass 36, count 0 2006.218.07:31:07.69#ibcon#*after write, iclass 36, count 0 2006.218.07:31:07.69#ibcon#*before return 0, iclass 36, count 0 2006.218.07:31:07.69#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.218.07:31:07.69#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.218.07:31:07.69#ibcon#about to clear, iclass 36 cls_cnt 0 2006.218.07:31:07.69#ibcon#cleared, iclass 36 cls_cnt 0 2006.218.07:31:07.69$vc4f8/va=3,4 2006.218.07:31:07.69#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.218.07:31:07.69#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.218.07:31:07.69#ibcon#ireg 11 cls_cnt 2 2006.218.07:31:07.69#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.218.07:31:07.74#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.218.07:31:07.74#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.218.07:31:07.74#ibcon#enter wrdev, iclass 38, count 2 2006.218.07:31:07.74#ibcon#first serial, iclass 38, count 2 2006.218.07:31:07.74#ibcon#enter sib2, iclass 38, count 2 2006.218.07:31:07.74#ibcon#flushed, iclass 38, count 2 2006.218.07:31:07.74#ibcon#about to write, iclass 38, count 2 2006.218.07:31:07.74#ibcon#wrote, iclass 38, count 2 2006.218.07:31:07.74#ibcon#about to read 3, iclass 38, count 2 2006.218.07:31:07.76#ibcon#read 3, iclass 38, count 2 2006.218.07:31:07.76#ibcon#about to read 4, iclass 38, count 2 2006.218.07:31:07.76#ibcon#read 4, iclass 38, count 2 2006.218.07:31:07.76#ibcon#about to read 5, iclass 38, count 2 2006.218.07:31:07.76#ibcon#read 5, iclass 38, count 2 2006.218.07:31:07.76#ibcon#about to read 6, iclass 38, count 2 2006.218.07:31:07.76#ibcon#read 6, iclass 38, count 2 2006.218.07:31:07.76#ibcon#end of sib2, iclass 38, count 2 2006.218.07:31:07.76#ibcon#*mode == 0, iclass 38, count 2 2006.218.07:31:07.76#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.218.07:31:07.76#ibcon#[25=AT03-04\r\n] 2006.218.07:31:07.76#ibcon#*before write, iclass 38, count 2 2006.218.07:31:07.76#ibcon#enter sib2, iclass 38, count 2 2006.218.07:31:07.76#ibcon#flushed, iclass 38, count 2 2006.218.07:31:07.76#ibcon#about to write, iclass 38, count 2 2006.218.07:31:07.76#ibcon#wrote, iclass 38, count 2 2006.218.07:31:07.76#ibcon#about to read 3, iclass 38, count 2 2006.218.07:31:07.79#ibcon#read 3, iclass 38, count 2 2006.218.07:31:07.79#ibcon#about to read 4, iclass 38, count 2 2006.218.07:31:07.79#ibcon#read 4, iclass 38, count 2 2006.218.07:31:07.79#ibcon#about to read 5, iclass 38, count 2 2006.218.07:31:07.79#ibcon#read 5, iclass 38, count 2 2006.218.07:31:07.79#ibcon#about to read 6, iclass 38, count 2 2006.218.07:31:07.79#ibcon#read 6, iclass 38, count 2 2006.218.07:31:07.79#ibcon#end of sib2, iclass 38, count 2 2006.218.07:31:07.79#ibcon#*after write, iclass 38, count 2 2006.218.07:31:07.79#ibcon#*before return 0, iclass 38, count 2 2006.218.07:31:07.79#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.218.07:31:07.79#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.218.07:31:07.79#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.218.07:31:07.79#ibcon#ireg 7 cls_cnt 0 2006.218.07:31:07.79#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.218.07:31:07.91#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.218.07:31:07.91#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.218.07:31:07.91#ibcon#enter wrdev, iclass 38, count 0 2006.218.07:31:07.91#ibcon#first serial, iclass 38, count 0 2006.218.07:31:07.91#ibcon#enter sib2, iclass 38, count 0 2006.218.07:31:07.91#ibcon#flushed, iclass 38, count 0 2006.218.07:31:07.91#ibcon#about to write, iclass 38, count 0 2006.218.07:31:07.91#ibcon#wrote, iclass 38, count 0 2006.218.07:31:07.91#ibcon#about to read 3, iclass 38, count 0 2006.218.07:31:07.93#ibcon#read 3, iclass 38, count 0 2006.218.07:31:07.93#ibcon#about to read 4, iclass 38, count 0 2006.218.07:31:07.93#ibcon#read 4, iclass 38, count 0 2006.218.07:31:07.93#ibcon#about to read 5, iclass 38, count 0 2006.218.07:31:07.93#ibcon#read 5, iclass 38, count 0 2006.218.07:31:07.93#ibcon#about to read 6, iclass 38, count 0 2006.218.07:31:07.93#ibcon#read 6, iclass 38, count 0 2006.218.07:31:07.93#ibcon#end of sib2, iclass 38, count 0 2006.218.07:31:07.93#ibcon#*mode == 0, iclass 38, count 0 2006.218.07:31:07.93#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.218.07:31:07.93#ibcon#[25=USB\r\n] 2006.218.07:31:07.93#ibcon#*before write, iclass 38, count 0 2006.218.07:31:07.93#ibcon#enter sib2, iclass 38, count 0 2006.218.07:31:07.93#ibcon#flushed, iclass 38, count 0 2006.218.07:31:07.93#ibcon#about to write, iclass 38, count 0 2006.218.07:31:07.93#ibcon#wrote, iclass 38, count 0 2006.218.07:31:07.93#ibcon#about to read 3, iclass 38, count 0 2006.218.07:31:07.96#ibcon#read 3, iclass 38, count 0 2006.218.07:31:07.96#ibcon#about to read 4, iclass 38, count 0 2006.218.07:31:07.96#ibcon#read 4, iclass 38, count 0 2006.218.07:31:07.96#ibcon#about to read 5, iclass 38, count 0 2006.218.07:31:07.96#ibcon#read 5, iclass 38, count 0 2006.218.07:31:07.96#ibcon#about to read 6, iclass 38, count 0 2006.218.07:31:07.96#ibcon#read 6, iclass 38, count 0 2006.218.07:31:07.96#ibcon#end of sib2, iclass 38, count 0 2006.218.07:31:07.96#ibcon#*after write, iclass 38, count 0 2006.218.07:31:07.96#ibcon#*before return 0, iclass 38, count 0 2006.218.07:31:07.96#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.218.07:31:07.96#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.218.07:31:07.96#ibcon#about to clear, iclass 38 cls_cnt 0 2006.218.07:31:07.96#ibcon#cleared, iclass 38 cls_cnt 0 2006.218.07:31:07.96$vc4f8/valo=4,832.99 2006.218.07:31:07.96#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.218.07:31:07.96#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.218.07:31:07.96#ibcon#ireg 17 cls_cnt 0 2006.218.07:31:07.96#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.218.07:31:07.96#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.218.07:31:07.96#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.218.07:31:07.96#ibcon#enter wrdev, iclass 40, count 0 2006.218.07:31:07.96#ibcon#first serial, iclass 40, count 0 2006.218.07:31:07.96#ibcon#enter sib2, iclass 40, count 0 2006.218.07:31:07.96#ibcon#flushed, iclass 40, count 0 2006.218.07:31:07.96#ibcon#about to write, iclass 40, count 0 2006.218.07:31:07.96#ibcon#wrote, iclass 40, count 0 2006.218.07:31:07.96#ibcon#about to read 3, iclass 40, count 0 2006.218.07:31:07.99#ibcon#read 3, iclass 40, count 0 2006.218.07:31:07.99#ibcon#about to read 4, iclass 40, count 0 2006.218.07:31:07.99#ibcon#read 4, iclass 40, count 0 2006.218.07:31:07.99#ibcon#about to read 5, iclass 40, count 0 2006.218.07:31:07.99#ibcon#read 5, iclass 40, count 0 2006.218.07:31:07.99#ibcon#about to read 6, iclass 40, count 0 2006.218.07:31:07.99#ibcon#read 6, iclass 40, count 0 2006.218.07:31:07.99#ibcon#end of sib2, iclass 40, count 0 2006.218.07:31:07.99#ibcon#*mode == 0, iclass 40, count 0 2006.218.07:31:07.99#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.218.07:31:07.99#ibcon#[26=FRQ=04,832.99\r\n] 2006.218.07:31:07.99#ibcon#*before write, iclass 40, count 0 2006.218.07:31:07.99#ibcon#enter sib2, iclass 40, count 0 2006.218.07:31:07.99#ibcon#flushed, iclass 40, count 0 2006.218.07:31:07.99#ibcon#about to write, iclass 40, count 0 2006.218.07:31:07.99#ibcon#wrote, iclass 40, count 0 2006.218.07:31:07.99#ibcon#about to read 3, iclass 40, count 0 2006.218.07:31:08.03#ibcon#read 3, iclass 40, count 0 2006.218.07:31:08.03#ibcon#about to read 4, iclass 40, count 0 2006.218.07:31:08.03#ibcon#read 4, iclass 40, count 0 2006.218.07:31:08.03#ibcon#about to read 5, iclass 40, count 0 2006.218.07:31:08.03#ibcon#read 5, iclass 40, count 0 2006.218.07:31:08.03#ibcon#about to read 6, iclass 40, count 0 2006.218.07:31:08.03#ibcon#read 6, iclass 40, count 0 2006.218.07:31:08.03#ibcon#end of sib2, iclass 40, count 0 2006.218.07:31:08.03#ibcon#*after write, iclass 40, count 0 2006.218.07:31:08.03#ibcon#*before return 0, iclass 40, count 0 2006.218.07:31:08.03#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.218.07:31:08.03#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.218.07:31:08.03#ibcon#about to clear, iclass 40 cls_cnt 0 2006.218.07:31:08.03#ibcon#cleared, iclass 40 cls_cnt 0 2006.218.07:31:08.03$vc4f8/va=4,4 2006.218.07:31:08.03#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.218.07:31:08.03#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.218.07:31:08.03#ibcon#ireg 11 cls_cnt 2 2006.218.07:31:08.03#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.218.07:31:08.08#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.218.07:31:08.08#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.218.07:31:08.08#ibcon#enter wrdev, iclass 4, count 2 2006.218.07:31:08.08#ibcon#first serial, iclass 4, count 2 2006.218.07:31:08.08#ibcon#enter sib2, iclass 4, count 2 2006.218.07:31:08.08#ibcon#flushed, iclass 4, count 2 2006.218.07:31:08.08#ibcon#about to write, iclass 4, count 2 2006.218.07:31:08.08#ibcon#wrote, iclass 4, count 2 2006.218.07:31:08.08#ibcon#about to read 3, iclass 4, count 2 2006.218.07:31:08.10#ibcon#read 3, iclass 4, count 2 2006.218.07:31:08.10#ibcon#about to read 4, iclass 4, count 2 2006.218.07:31:08.10#ibcon#read 4, iclass 4, count 2 2006.218.07:31:08.10#ibcon#about to read 5, iclass 4, count 2 2006.218.07:31:08.10#ibcon#read 5, iclass 4, count 2 2006.218.07:31:08.10#ibcon#about to read 6, iclass 4, count 2 2006.218.07:31:08.10#ibcon#read 6, iclass 4, count 2 2006.218.07:31:08.10#ibcon#end of sib2, iclass 4, count 2 2006.218.07:31:08.10#ibcon#*mode == 0, iclass 4, count 2 2006.218.07:31:08.10#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.218.07:31:08.10#ibcon#[25=AT04-04\r\n] 2006.218.07:31:08.10#ibcon#*before write, iclass 4, count 2 2006.218.07:31:08.10#ibcon#enter sib2, iclass 4, count 2 2006.218.07:31:08.10#ibcon#flushed, iclass 4, count 2 2006.218.07:31:08.10#ibcon#about to write, iclass 4, count 2 2006.218.07:31:08.10#ibcon#wrote, iclass 4, count 2 2006.218.07:31:08.10#ibcon#about to read 3, iclass 4, count 2 2006.218.07:31:08.13#ibcon#read 3, iclass 4, count 2 2006.218.07:31:08.13#ibcon#about to read 4, iclass 4, count 2 2006.218.07:31:08.13#ibcon#read 4, iclass 4, count 2 2006.218.07:31:08.13#ibcon#about to read 5, iclass 4, count 2 2006.218.07:31:08.13#ibcon#read 5, iclass 4, count 2 2006.218.07:31:08.13#ibcon#about to read 6, iclass 4, count 2 2006.218.07:31:08.13#ibcon#read 6, iclass 4, count 2 2006.218.07:31:08.13#ibcon#end of sib2, iclass 4, count 2 2006.218.07:31:08.13#ibcon#*after write, iclass 4, count 2 2006.218.07:31:08.13#ibcon#*before return 0, iclass 4, count 2 2006.218.07:31:08.13#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.218.07:31:08.13#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.218.07:31:08.13#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.218.07:31:08.13#ibcon#ireg 7 cls_cnt 0 2006.218.07:31:08.13#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.218.07:31:08.25#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.218.07:31:08.25#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.218.07:31:08.25#ibcon#enter wrdev, iclass 4, count 0 2006.218.07:31:08.25#ibcon#first serial, iclass 4, count 0 2006.218.07:31:08.25#ibcon#enter sib2, iclass 4, count 0 2006.218.07:31:08.25#ibcon#flushed, iclass 4, count 0 2006.218.07:31:08.25#ibcon#about to write, iclass 4, count 0 2006.218.07:31:08.25#ibcon#wrote, iclass 4, count 0 2006.218.07:31:08.25#ibcon#about to read 3, iclass 4, count 0 2006.218.07:31:08.27#ibcon#read 3, iclass 4, count 0 2006.218.07:31:08.27#ibcon#about to read 4, iclass 4, count 0 2006.218.07:31:08.27#ibcon#read 4, iclass 4, count 0 2006.218.07:31:08.27#ibcon#about to read 5, iclass 4, count 0 2006.218.07:31:08.27#ibcon#read 5, iclass 4, count 0 2006.218.07:31:08.27#ibcon#about to read 6, iclass 4, count 0 2006.218.07:31:08.27#ibcon#read 6, iclass 4, count 0 2006.218.07:31:08.27#ibcon#end of sib2, iclass 4, count 0 2006.218.07:31:08.27#ibcon#*mode == 0, iclass 4, count 0 2006.218.07:31:08.27#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.218.07:31:08.27#ibcon#[25=USB\r\n] 2006.218.07:31:08.27#ibcon#*before write, iclass 4, count 0 2006.218.07:31:08.27#ibcon#enter sib2, iclass 4, count 0 2006.218.07:31:08.27#ibcon#flushed, iclass 4, count 0 2006.218.07:31:08.27#ibcon#about to write, iclass 4, count 0 2006.218.07:31:08.27#ibcon#wrote, iclass 4, count 0 2006.218.07:31:08.27#ibcon#about to read 3, iclass 4, count 0 2006.218.07:31:08.30#ibcon#read 3, iclass 4, count 0 2006.218.07:31:08.30#ibcon#about to read 4, iclass 4, count 0 2006.218.07:31:08.30#ibcon#read 4, iclass 4, count 0 2006.218.07:31:08.30#ibcon#about to read 5, iclass 4, count 0 2006.218.07:31:08.30#ibcon#read 5, iclass 4, count 0 2006.218.07:31:08.30#ibcon#about to read 6, iclass 4, count 0 2006.218.07:31:08.30#ibcon#read 6, iclass 4, count 0 2006.218.07:31:08.30#ibcon#end of sib2, iclass 4, count 0 2006.218.07:31:08.30#ibcon#*after write, iclass 4, count 0 2006.218.07:31:08.30#ibcon#*before return 0, iclass 4, count 0 2006.218.07:31:08.30#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.218.07:31:08.30#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.218.07:31:08.30#ibcon#about to clear, iclass 4 cls_cnt 0 2006.218.07:31:08.30#ibcon#cleared, iclass 4 cls_cnt 0 2006.218.07:31:08.30$vc4f8/valo=5,652.99 2006.218.07:31:08.30#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.218.07:31:08.30#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.218.07:31:08.30#ibcon#ireg 17 cls_cnt 0 2006.218.07:31:08.30#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.218.07:31:08.30#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.218.07:31:08.30#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.218.07:31:08.30#ibcon#enter wrdev, iclass 6, count 0 2006.218.07:31:08.30#ibcon#first serial, iclass 6, count 0 2006.218.07:31:08.30#ibcon#enter sib2, iclass 6, count 0 2006.218.07:31:08.30#ibcon#flushed, iclass 6, count 0 2006.218.07:31:08.30#ibcon#about to write, iclass 6, count 0 2006.218.07:31:08.30#ibcon#wrote, iclass 6, count 0 2006.218.07:31:08.30#ibcon#about to read 3, iclass 6, count 0 2006.218.07:31:08.32#ibcon#read 3, iclass 6, count 0 2006.218.07:31:08.32#ibcon#about to read 4, iclass 6, count 0 2006.218.07:31:08.32#ibcon#read 4, iclass 6, count 0 2006.218.07:31:08.32#ibcon#about to read 5, iclass 6, count 0 2006.218.07:31:08.32#ibcon#read 5, iclass 6, count 0 2006.218.07:31:08.32#ibcon#about to read 6, iclass 6, count 0 2006.218.07:31:08.32#ibcon#read 6, iclass 6, count 0 2006.218.07:31:08.32#ibcon#end of sib2, iclass 6, count 0 2006.218.07:31:08.32#ibcon#*mode == 0, iclass 6, count 0 2006.218.07:31:08.32#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.218.07:31:08.32#ibcon#[26=FRQ=05,652.99\r\n] 2006.218.07:31:08.32#ibcon#*before write, iclass 6, count 0 2006.218.07:31:08.32#ibcon#enter sib2, iclass 6, count 0 2006.218.07:31:08.32#ibcon#flushed, iclass 6, count 0 2006.218.07:31:08.32#ibcon#about to write, iclass 6, count 0 2006.218.07:31:08.32#ibcon#wrote, iclass 6, count 0 2006.218.07:31:08.32#ibcon#about to read 3, iclass 6, count 0 2006.218.07:31:08.36#ibcon#read 3, iclass 6, count 0 2006.218.07:31:08.36#ibcon#about to read 4, iclass 6, count 0 2006.218.07:31:08.36#ibcon#read 4, iclass 6, count 0 2006.218.07:31:08.36#ibcon#about to read 5, iclass 6, count 0 2006.218.07:31:08.36#ibcon#read 5, iclass 6, count 0 2006.218.07:31:08.36#ibcon#about to read 6, iclass 6, count 0 2006.218.07:31:08.36#ibcon#read 6, iclass 6, count 0 2006.218.07:31:08.36#ibcon#end of sib2, iclass 6, count 0 2006.218.07:31:08.36#ibcon#*after write, iclass 6, count 0 2006.218.07:31:08.36#ibcon#*before return 0, iclass 6, count 0 2006.218.07:31:08.36#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.218.07:31:08.36#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.218.07:31:08.36#ibcon#about to clear, iclass 6 cls_cnt 0 2006.218.07:31:08.36#ibcon#cleared, iclass 6 cls_cnt 0 2006.218.07:31:08.36$vc4f8/va=5,7 2006.218.07:31:08.36#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.218.07:31:08.36#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.218.07:31:08.36#ibcon#ireg 11 cls_cnt 2 2006.218.07:31:08.36#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.218.07:31:08.42#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.218.07:31:08.42#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.218.07:31:08.42#ibcon#enter wrdev, iclass 10, count 2 2006.218.07:31:08.42#ibcon#first serial, iclass 10, count 2 2006.218.07:31:08.42#ibcon#enter sib2, iclass 10, count 2 2006.218.07:31:08.42#ibcon#flushed, iclass 10, count 2 2006.218.07:31:08.42#ibcon#about to write, iclass 10, count 2 2006.218.07:31:08.42#ibcon#wrote, iclass 10, count 2 2006.218.07:31:08.42#ibcon#about to read 3, iclass 10, count 2 2006.218.07:31:08.44#ibcon#read 3, iclass 10, count 2 2006.218.07:31:08.44#ibcon#about to read 4, iclass 10, count 2 2006.218.07:31:08.44#ibcon#read 4, iclass 10, count 2 2006.218.07:31:08.44#ibcon#about to read 5, iclass 10, count 2 2006.218.07:31:08.44#ibcon#read 5, iclass 10, count 2 2006.218.07:31:08.44#ibcon#about to read 6, iclass 10, count 2 2006.218.07:31:08.44#ibcon#read 6, iclass 10, count 2 2006.218.07:31:08.44#ibcon#end of sib2, iclass 10, count 2 2006.218.07:31:08.44#ibcon#*mode == 0, iclass 10, count 2 2006.218.07:31:08.44#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.218.07:31:08.44#ibcon#[25=AT05-07\r\n] 2006.218.07:31:08.44#ibcon#*before write, iclass 10, count 2 2006.218.07:31:08.44#ibcon#enter sib2, iclass 10, count 2 2006.218.07:31:08.44#ibcon#flushed, iclass 10, count 2 2006.218.07:31:08.44#ibcon#about to write, iclass 10, count 2 2006.218.07:31:08.44#ibcon#wrote, iclass 10, count 2 2006.218.07:31:08.44#ibcon#about to read 3, iclass 10, count 2 2006.218.07:31:08.47#ibcon#read 3, iclass 10, count 2 2006.218.07:31:08.47#ibcon#about to read 4, iclass 10, count 2 2006.218.07:31:08.47#ibcon#read 4, iclass 10, count 2 2006.218.07:31:08.47#ibcon#about to read 5, iclass 10, count 2 2006.218.07:31:08.47#ibcon#read 5, iclass 10, count 2 2006.218.07:31:08.47#ibcon#about to read 6, iclass 10, count 2 2006.218.07:31:08.47#ibcon#read 6, iclass 10, count 2 2006.218.07:31:08.47#ibcon#end of sib2, iclass 10, count 2 2006.218.07:31:08.47#ibcon#*after write, iclass 10, count 2 2006.218.07:31:08.47#ibcon#*before return 0, iclass 10, count 2 2006.218.07:31:08.47#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.218.07:31:08.47#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.218.07:31:08.47#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.218.07:31:08.47#ibcon#ireg 7 cls_cnt 0 2006.218.07:31:08.47#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.218.07:31:08.59#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.218.07:31:08.59#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.218.07:31:08.59#ibcon#enter wrdev, iclass 10, count 0 2006.218.07:31:08.59#ibcon#first serial, iclass 10, count 0 2006.218.07:31:08.59#ibcon#enter sib2, iclass 10, count 0 2006.218.07:31:08.59#ibcon#flushed, iclass 10, count 0 2006.218.07:31:08.59#ibcon#about to write, iclass 10, count 0 2006.218.07:31:08.59#ibcon#wrote, iclass 10, count 0 2006.218.07:31:08.59#ibcon#about to read 3, iclass 10, count 0 2006.218.07:31:08.61#ibcon#read 3, iclass 10, count 0 2006.218.07:31:08.61#ibcon#about to read 4, iclass 10, count 0 2006.218.07:31:08.61#ibcon#read 4, iclass 10, count 0 2006.218.07:31:08.61#ibcon#about to read 5, iclass 10, count 0 2006.218.07:31:08.61#ibcon#read 5, iclass 10, count 0 2006.218.07:31:08.61#ibcon#about to read 6, iclass 10, count 0 2006.218.07:31:08.61#ibcon#read 6, iclass 10, count 0 2006.218.07:31:08.61#ibcon#end of sib2, iclass 10, count 0 2006.218.07:31:08.61#ibcon#*mode == 0, iclass 10, count 0 2006.218.07:31:08.61#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.218.07:31:08.61#ibcon#[25=USB\r\n] 2006.218.07:31:08.61#ibcon#*before write, iclass 10, count 0 2006.218.07:31:08.61#ibcon#enter sib2, iclass 10, count 0 2006.218.07:31:08.61#ibcon#flushed, iclass 10, count 0 2006.218.07:31:08.61#ibcon#about to write, iclass 10, count 0 2006.218.07:31:08.61#ibcon#wrote, iclass 10, count 0 2006.218.07:31:08.61#ibcon#about to read 3, iclass 10, count 0 2006.218.07:31:08.64#ibcon#read 3, iclass 10, count 0 2006.218.07:31:08.64#ibcon#about to read 4, iclass 10, count 0 2006.218.07:31:08.64#ibcon#read 4, iclass 10, count 0 2006.218.07:31:08.64#ibcon#about to read 5, iclass 10, count 0 2006.218.07:31:08.64#ibcon#read 5, iclass 10, count 0 2006.218.07:31:08.64#ibcon#about to read 6, iclass 10, count 0 2006.218.07:31:08.64#ibcon#read 6, iclass 10, count 0 2006.218.07:31:08.64#ibcon#end of sib2, iclass 10, count 0 2006.218.07:31:08.64#ibcon#*after write, iclass 10, count 0 2006.218.07:31:08.64#ibcon#*before return 0, iclass 10, count 0 2006.218.07:31:08.64#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.218.07:31:08.64#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.218.07:31:08.64#ibcon#about to clear, iclass 10 cls_cnt 0 2006.218.07:31:08.64#ibcon#cleared, iclass 10 cls_cnt 0 2006.218.07:31:08.64$vc4f8/valo=6,772.99 2006.218.07:31:08.64#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.218.07:31:08.64#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.218.07:31:08.64#ibcon#ireg 17 cls_cnt 0 2006.218.07:31:08.64#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.218.07:31:08.64#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.218.07:31:08.64#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.218.07:31:08.64#ibcon#enter wrdev, iclass 12, count 0 2006.218.07:31:08.64#ibcon#first serial, iclass 12, count 0 2006.218.07:31:08.64#ibcon#enter sib2, iclass 12, count 0 2006.218.07:31:08.64#ibcon#flushed, iclass 12, count 0 2006.218.07:31:08.64#ibcon#about to write, iclass 12, count 0 2006.218.07:31:08.64#ibcon#wrote, iclass 12, count 0 2006.218.07:31:08.64#ibcon#about to read 3, iclass 12, count 0 2006.218.07:31:08.66#ibcon#read 3, iclass 12, count 0 2006.218.07:31:08.66#ibcon#about to read 4, iclass 12, count 0 2006.218.07:31:08.66#ibcon#read 4, iclass 12, count 0 2006.218.07:31:08.66#ibcon#about to read 5, iclass 12, count 0 2006.218.07:31:08.66#ibcon#read 5, iclass 12, count 0 2006.218.07:31:08.66#ibcon#about to read 6, iclass 12, count 0 2006.218.07:31:08.66#ibcon#read 6, iclass 12, count 0 2006.218.07:31:08.66#ibcon#end of sib2, iclass 12, count 0 2006.218.07:31:08.66#ibcon#*mode == 0, iclass 12, count 0 2006.218.07:31:08.66#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.218.07:31:08.66#ibcon#[26=FRQ=06,772.99\r\n] 2006.218.07:31:08.66#ibcon#*before write, iclass 12, count 0 2006.218.07:31:08.66#ibcon#enter sib2, iclass 12, count 0 2006.218.07:31:08.66#ibcon#flushed, iclass 12, count 0 2006.218.07:31:08.66#ibcon#about to write, iclass 12, count 0 2006.218.07:31:08.66#ibcon#wrote, iclass 12, count 0 2006.218.07:31:08.66#ibcon#about to read 3, iclass 12, count 0 2006.218.07:31:08.70#ibcon#read 3, iclass 12, count 0 2006.218.07:31:08.70#ibcon#about to read 4, iclass 12, count 0 2006.218.07:31:08.70#ibcon#read 4, iclass 12, count 0 2006.218.07:31:08.70#ibcon#about to read 5, iclass 12, count 0 2006.218.07:31:08.70#ibcon#read 5, iclass 12, count 0 2006.218.07:31:08.70#ibcon#about to read 6, iclass 12, count 0 2006.218.07:31:08.70#ibcon#read 6, iclass 12, count 0 2006.218.07:31:08.70#ibcon#end of sib2, iclass 12, count 0 2006.218.07:31:08.70#ibcon#*after write, iclass 12, count 0 2006.218.07:31:08.70#ibcon#*before return 0, iclass 12, count 0 2006.218.07:31:08.70#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.218.07:31:08.70#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.218.07:31:08.70#ibcon#about to clear, iclass 12 cls_cnt 0 2006.218.07:31:08.70#ibcon#cleared, iclass 12 cls_cnt 0 2006.218.07:31:08.70$vc4f8/va=6,6 2006.218.07:31:08.70#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.218.07:31:08.70#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.218.07:31:08.70#ibcon#ireg 11 cls_cnt 2 2006.218.07:31:08.70#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.218.07:31:08.76#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.218.07:31:08.76#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.218.07:31:08.76#ibcon#enter wrdev, iclass 14, count 2 2006.218.07:31:08.76#ibcon#first serial, iclass 14, count 2 2006.218.07:31:08.76#ibcon#enter sib2, iclass 14, count 2 2006.218.07:31:08.76#ibcon#flushed, iclass 14, count 2 2006.218.07:31:08.76#ibcon#about to write, iclass 14, count 2 2006.218.07:31:08.76#ibcon#wrote, iclass 14, count 2 2006.218.07:31:08.76#ibcon#about to read 3, iclass 14, count 2 2006.218.07:31:08.78#ibcon#read 3, iclass 14, count 2 2006.218.07:31:08.78#ibcon#about to read 4, iclass 14, count 2 2006.218.07:31:08.78#ibcon#read 4, iclass 14, count 2 2006.218.07:31:08.78#ibcon#about to read 5, iclass 14, count 2 2006.218.07:31:08.78#ibcon#read 5, iclass 14, count 2 2006.218.07:31:08.78#ibcon#about to read 6, iclass 14, count 2 2006.218.07:31:08.78#ibcon#read 6, iclass 14, count 2 2006.218.07:31:08.78#ibcon#end of sib2, iclass 14, count 2 2006.218.07:31:08.78#ibcon#*mode == 0, iclass 14, count 2 2006.218.07:31:08.78#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.218.07:31:08.78#ibcon#[25=AT06-06\r\n] 2006.218.07:31:08.78#ibcon#*before write, iclass 14, count 2 2006.218.07:31:08.78#ibcon#enter sib2, iclass 14, count 2 2006.218.07:31:08.78#ibcon#flushed, iclass 14, count 2 2006.218.07:31:08.78#ibcon#about to write, iclass 14, count 2 2006.218.07:31:08.78#ibcon#wrote, iclass 14, count 2 2006.218.07:31:08.78#ibcon#about to read 3, iclass 14, count 2 2006.218.07:31:08.81#ibcon#read 3, iclass 14, count 2 2006.218.07:31:08.81#ibcon#about to read 4, iclass 14, count 2 2006.218.07:31:08.81#ibcon#read 4, iclass 14, count 2 2006.218.07:31:08.81#ibcon#about to read 5, iclass 14, count 2 2006.218.07:31:08.81#ibcon#read 5, iclass 14, count 2 2006.218.07:31:08.81#ibcon#about to read 6, iclass 14, count 2 2006.218.07:31:08.81#ibcon#read 6, iclass 14, count 2 2006.218.07:31:08.81#ibcon#end of sib2, iclass 14, count 2 2006.218.07:31:08.81#ibcon#*after write, iclass 14, count 2 2006.218.07:31:08.81#ibcon#*before return 0, iclass 14, count 2 2006.218.07:31:08.81#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.218.07:31:08.81#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.218.07:31:08.81#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.218.07:31:08.81#ibcon#ireg 7 cls_cnt 0 2006.218.07:31:08.81#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.218.07:31:08.93#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.218.07:31:08.93#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.218.07:31:08.93#ibcon#enter wrdev, iclass 14, count 0 2006.218.07:31:08.93#ibcon#first serial, iclass 14, count 0 2006.218.07:31:08.93#ibcon#enter sib2, iclass 14, count 0 2006.218.07:31:08.93#ibcon#flushed, iclass 14, count 0 2006.218.07:31:08.93#ibcon#about to write, iclass 14, count 0 2006.218.07:31:08.93#ibcon#wrote, iclass 14, count 0 2006.218.07:31:08.93#ibcon#about to read 3, iclass 14, count 0 2006.218.07:31:08.95#ibcon#read 3, iclass 14, count 0 2006.218.07:31:08.95#ibcon#about to read 4, iclass 14, count 0 2006.218.07:31:08.95#ibcon#read 4, iclass 14, count 0 2006.218.07:31:08.95#ibcon#about to read 5, iclass 14, count 0 2006.218.07:31:08.95#ibcon#read 5, iclass 14, count 0 2006.218.07:31:08.95#ibcon#about to read 6, iclass 14, count 0 2006.218.07:31:08.95#ibcon#read 6, iclass 14, count 0 2006.218.07:31:08.95#ibcon#end of sib2, iclass 14, count 0 2006.218.07:31:08.95#ibcon#*mode == 0, iclass 14, count 0 2006.218.07:31:08.95#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.218.07:31:08.95#ibcon#[25=USB\r\n] 2006.218.07:31:08.95#ibcon#*before write, iclass 14, count 0 2006.218.07:31:08.95#ibcon#enter sib2, iclass 14, count 0 2006.218.07:31:08.95#ibcon#flushed, iclass 14, count 0 2006.218.07:31:08.95#ibcon#about to write, iclass 14, count 0 2006.218.07:31:08.95#ibcon#wrote, iclass 14, count 0 2006.218.07:31:08.95#ibcon#about to read 3, iclass 14, count 0 2006.218.07:31:08.98#ibcon#read 3, iclass 14, count 0 2006.218.07:31:08.98#ibcon#about to read 4, iclass 14, count 0 2006.218.07:31:08.98#ibcon#read 4, iclass 14, count 0 2006.218.07:31:08.98#ibcon#about to read 5, iclass 14, count 0 2006.218.07:31:08.98#ibcon#read 5, iclass 14, count 0 2006.218.07:31:08.98#ibcon#about to read 6, iclass 14, count 0 2006.218.07:31:08.98#ibcon#read 6, iclass 14, count 0 2006.218.07:31:08.98#ibcon#end of sib2, iclass 14, count 0 2006.218.07:31:08.98#ibcon#*after write, iclass 14, count 0 2006.218.07:31:08.98#ibcon#*before return 0, iclass 14, count 0 2006.218.07:31:08.98#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.218.07:31:08.98#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.218.07:31:08.98#ibcon#about to clear, iclass 14 cls_cnt 0 2006.218.07:31:08.98#ibcon#cleared, iclass 14 cls_cnt 0 2006.218.07:31:08.98$vc4f8/valo=7,832.99 2006.218.07:31:08.98#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.218.07:31:08.98#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.218.07:31:08.98#ibcon#ireg 17 cls_cnt 0 2006.218.07:31:08.98#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.218.07:31:08.98#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.218.07:31:08.98#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.218.07:31:08.98#ibcon#enter wrdev, iclass 16, count 0 2006.218.07:31:08.98#ibcon#first serial, iclass 16, count 0 2006.218.07:31:08.98#ibcon#enter sib2, iclass 16, count 0 2006.218.07:31:08.98#ibcon#flushed, iclass 16, count 0 2006.218.07:31:08.98#ibcon#about to write, iclass 16, count 0 2006.218.07:31:08.98#ibcon#wrote, iclass 16, count 0 2006.218.07:31:08.98#ibcon#about to read 3, iclass 16, count 0 2006.218.07:31:09.00#ibcon#read 3, iclass 16, count 0 2006.218.07:31:09.00#ibcon#about to read 4, iclass 16, count 0 2006.218.07:31:09.00#ibcon#read 4, iclass 16, count 0 2006.218.07:31:09.00#ibcon#about to read 5, iclass 16, count 0 2006.218.07:31:09.00#ibcon#read 5, iclass 16, count 0 2006.218.07:31:09.00#ibcon#about to read 6, iclass 16, count 0 2006.218.07:31:09.00#ibcon#read 6, iclass 16, count 0 2006.218.07:31:09.00#ibcon#end of sib2, iclass 16, count 0 2006.218.07:31:09.00#ibcon#*mode == 0, iclass 16, count 0 2006.218.07:31:09.00#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.218.07:31:09.00#ibcon#[26=FRQ=07,832.99\r\n] 2006.218.07:31:09.00#ibcon#*before write, iclass 16, count 0 2006.218.07:31:09.00#ibcon#enter sib2, iclass 16, count 0 2006.218.07:31:09.00#ibcon#flushed, iclass 16, count 0 2006.218.07:31:09.00#ibcon#about to write, iclass 16, count 0 2006.218.07:31:09.00#ibcon#wrote, iclass 16, count 0 2006.218.07:31:09.00#ibcon#about to read 3, iclass 16, count 0 2006.218.07:31:09.04#ibcon#read 3, iclass 16, count 0 2006.218.07:31:09.04#ibcon#about to read 4, iclass 16, count 0 2006.218.07:31:09.04#ibcon#read 4, iclass 16, count 0 2006.218.07:31:09.04#ibcon#about to read 5, iclass 16, count 0 2006.218.07:31:09.04#ibcon#read 5, iclass 16, count 0 2006.218.07:31:09.04#ibcon#about to read 6, iclass 16, count 0 2006.218.07:31:09.04#ibcon#read 6, iclass 16, count 0 2006.218.07:31:09.04#ibcon#end of sib2, iclass 16, count 0 2006.218.07:31:09.04#ibcon#*after write, iclass 16, count 0 2006.218.07:31:09.04#ibcon#*before return 0, iclass 16, count 0 2006.218.07:31:09.04#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.218.07:31:09.04#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.218.07:31:09.04#ibcon#about to clear, iclass 16 cls_cnt 0 2006.218.07:31:09.04#ibcon#cleared, iclass 16 cls_cnt 0 2006.218.07:31:09.04$vc4f8/va=7,6 2006.218.07:31:09.04#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.218.07:31:09.04#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.218.07:31:09.04#ibcon#ireg 11 cls_cnt 2 2006.218.07:31:09.04#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.218.07:31:09.10#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.218.07:31:09.10#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.218.07:31:09.10#ibcon#enter wrdev, iclass 18, count 2 2006.218.07:31:09.10#ibcon#first serial, iclass 18, count 2 2006.218.07:31:09.10#ibcon#enter sib2, iclass 18, count 2 2006.218.07:31:09.10#ibcon#flushed, iclass 18, count 2 2006.218.07:31:09.10#ibcon#about to write, iclass 18, count 2 2006.218.07:31:09.10#ibcon#wrote, iclass 18, count 2 2006.218.07:31:09.10#ibcon#about to read 3, iclass 18, count 2 2006.218.07:31:09.12#ibcon#read 3, iclass 18, count 2 2006.218.07:31:09.12#ibcon#about to read 4, iclass 18, count 2 2006.218.07:31:09.12#ibcon#read 4, iclass 18, count 2 2006.218.07:31:09.12#ibcon#about to read 5, iclass 18, count 2 2006.218.07:31:09.12#ibcon#read 5, iclass 18, count 2 2006.218.07:31:09.12#ibcon#about to read 6, iclass 18, count 2 2006.218.07:31:09.12#ibcon#read 6, iclass 18, count 2 2006.218.07:31:09.12#ibcon#end of sib2, iclass 18, count 2 2006.218.07:31:09.12#ibcon#*mode == 0, iclass 18, count 2 2006.218.07:31:09.12#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.218.07:31:09.12#ibcon#[25=AT07-06\r\n] 2006.218.07:31:09.12#ibcon#*before write, iclass 18, count 2 2006.218.07:31:09.12#ibcon#enter sib2, iclass 18, count 2 2006.218.07:31:09.12#ibcon#flushed, iclass 18, count 2 2006.218.07:31:09.12#ibcon#about to write, iclass 18, count 2 2006.218.07:31:09.12#ibcon#wrote, iclass 18, count 2 2006.218.07:31:09.12#ibcon#about to read 3, iclass 18, count 2 2006.218.07:31:09.15#ibcon#read 3, iclass 18, count 2 2006.218.07:31:09.15#ibcon#about to read 4, iclass 18, count 2 2006.218.07:31:09.15#ibcon#read 4, iclass 18, count 2 2006.218.07:31:09.15#ibcon#about to read 5, iclass 18, count 2 2006.218.07:31:09.15#ibcon#read 5, iclass 18, count 2 2006.218.07:31:09.15#ibcon#about to read 6, iclass 18, count 2 2006.218.07:31:09.15#ibcon#read 6, iclass 18, count 2 2006.218.07:31:09.15#ibcon#end of sib2, iclass 18, count 2 2006.218.07:31:09.15#ibcon#*after write, iclass 18, count 2 2006.218.07:31:09.15#ibcon#*before return 0, iclass 18, count 2 2006.218.07:31:09.15#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.218.07:31:09.15#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.218.07:31:09.15#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.218.07:31:09.15#ibcon#ireg 7 cls_cnt 0 2006.218.07:31:09.15#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.218.07:31:09.27#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.218.07:31:09.27#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.218.07:31:09.27#ibcon#enter wrdev, iclass 18, count 0 2006.218.07:31:09.27#ibcon#first serial, iclass 18, count 0 2006.218.07:31:09.27#ibcon#enter sib2, iclass 18, count 0 2006.218.07:31:09.27#ibcon#flushed, iclass 18, count 0 2006.218.07:31:09.27#ibcon#about to write, iclass 18, count 0 2006.218.07:31:09.27#ibcon#wrote, iclass 18, count 0 2006.218.07:31:09.27#ibcon#about to read 3, iclass 18, count 0 2006.218.07:31:09.29#ibcon#read 3, iclass 18, count 0 2006.218.07:31:09.29#ibcon#about to read 4, iclass 18, count 0 2006.218.07:31:09.29#ibcon#read 4, iclass 18, count 0 2006.218.07:31:09.29#ibcon#about to read 5, iclass 18, count 0 2006.218.07:31:09.29#ibcon#read 5, iclass 18, count 0 2006.218.07:31:09.29#ibcon#about to read 6, iclass 18, count 0 2006.218.07:31:09.29#ibcon#read 6, iclass 18, count 0 2006.218.07:31:09.29#ibcon#end of sib2, iclass 18, count 0 2006.218.07:31:09.29#ibcon#*mode == 0, iclass 18, count 0 2006.218.07:31:09.29#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.218.07:31:09.29#ibcon#[25=USB\r\n] 2006.218.07:31:09.29#ibcon#*before write, iclass 18, count 0 2006.218.07:31:09.29#ibcon#enter sib2, iclass 18, count 0 2006.218.07:31:09.29#ibcon#flushed, iclass 18, count 0 2006.218.07:31:09.29#ibcon#about to write, iclass 18, count 0 2006.218.07:31:09.29#ibcon#wrote, iclass 18, count 0 2006.218.07:31:09.29#ibcon#about to read 3, iclass 18, count 0 2006.218.07:31:09.32#ibcon#read 3, iclass 18, count 0 2006.218.07:31:09.32#ibcon#about to read 4, iclass 18, count 0 2006.218.07:31:09.32#ibcon#read 4, iclass 18, count 0 2006.218.07:31:09.32#ibcon#about to read 5, iclass 18, count 0 2006.218.07:31:09.32#ibcon#read 5, iclass 18, count 0 2006.218.07:31:09.32#ibcon#about to read 6, iclass 18, count 0 2006.218.07:31:09.32#ibcon#read 6, iclass 18, count 0 2006.218.07:31:09.32#ibcon#end of sib2, iclass 18, count 0 2006.218.07:31:09.32#ibcon#*after write, iclass 18, count 0 2006.218.07:31:09.32#ibcon#*before return 0, iclass 18, count 0 2006.218.07:31:09.32#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.218.07:31:09.32#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.218.07:31:09.32#ibcon#about to clear, iclass 18 cls_cnt 0 2006.218.07:31:09.32#ibcon#cleared, iclass 18 cls_cnt 0 2006.218.07:31:09.32$vc4f8/valo=8,852.99 2006.218.07:31:09.32#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.218.07:31:09.32#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.218.07:31:09.32#ibcon#ireg 17 cls_cnt 0 2006.218.07:31:09.32#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.218.07:31:09.32#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.218.07:31:09.32#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.218.07:31:09.32#ibcon#enter wrdev, iclass 20, count 0 2006.218.07:31:09.32#ibcon#first serial, iclass 20, count 0 2006.218.07:31:09.32#ibcon#enter sib2, iclass 20, count 0 2006.218.07:31:09.32#ibcon#flushed, iclass 20, count 0 2006.218.07:31:09.32#ibcon#about to write, iclass 20, count 0 2006.218.07:31:09.32#ibcon#wrote, iclass 20, count 0 2006.218.07:31:09.32#ibcon#about to read 3, iclass 20, count 0 2006.218.07:31:09.34#ibcon#read 3, iclass 20, count 0 2006.218.07:31:09.34#ibcon#about to read 4, iclass 20, count 0 2006.218.07:31:09.34#ibcon#read 4, iclass 20, count 0 2006.218.07:31:09.34#ibcon#about to read 5, iclass 20, count 0 2006.218.07:31:09.34#ibcon#read 5, iclass 20, count 0 2006.218.07:31:09.34#ibcon#about to read 6, iclass 20, count 0 2006.218.07:31:09.34#ibcon#read 6, iclass 20, count 0 2006.218.07:31:09.34#ibcon#end of sib2, iclass 20, count 0 2006.218.07:31:09.34#ibcon#*mode == 0, iclass 20, count 0 2006.218.07:31:09.34#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.218.07:31:09.34#ibcon#[26=FRQ=08,852.99\r\n] 2006.218.07:31:09.34#ibcon#*before write, iclass 20, count 0 2006.218.07:31:09.34#ibcon#enter sib2, iclass 20, count 0 2006.218.07:31:09.34#ibcon#flushed, iclass 20, count 0 2006.218.07:31:09.34#ibcon#about to write, iclass 20, count 0 2006.218.07:31:09.34#ibcon#wrote, iclass 20, count 0 2006.218.07:31:09.34#ibcon#about to read 3, iclass 20, count 0 2006.218.07:31:09.38#ibcon#read 3, iclass 20, count 0 2006.218.07:31:09.38#ibcon#about to read 4, iclass 20, count 0 2006.218.07:31:09.38#ibcon#read 4, iclass 20, count 0 2006.218.07:31:09.38#ibcon#about to read 5, iclass 20, count 0 2006.218.07:31:09.38#ibcon#read 5, iclass 20, count 0 2006.218.07:31:09.38#ibcon#about to read 6, iclass 20, count 0 2006.218.07:31:09.38#ibcon#read 6, iclass 20, count 0 2006.218.07:31:09.38#ibcon#end of sib2, iclass 20, count 0 2006.218.07:31:09.38#ibcon#*after write, iclass 20, count 0 2006.218.07:31:09.38#ibcon#*before return 0, iclass 20, count 0 2006.218.07:31:09.38#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.218.07:31:09.38#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.218.07:31:09.38#ibcon#about to clear, iclass 20 cls_cnt 0 2006.218.07:31:09.38#ibcon#cleared, iclass 20 cls_cnt 0 2006.218.07:31:09.38$vc4f8/va=8,7 2006.218.07:31:09.38#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.218.07:31:09.38#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.218.07:31:09.38#ibcon#ireg 11 cls_cnt 2 2006.218.07:31:09.38#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.218.07:31:09.44#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.218.07:31:09.44#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.218.07:31:09.44#ibcon#enter wrdev, iclass 22, count 2 2006.218.07:31:09.44#ibcon#first serial, iclass 22, count 2 2006.218.07:31:09.44#ibcon#enter sib2, iclass 22, count 2 2006.218.07:31:09.44#ibcon#flushed, iclass 22, count 2 2006.218.07:31:09.44#ibcon#about to write, iclass 22, count 2 2006.218.07:31:09.44#ibcon#wrote, iclass 22, count 2 2006.218.07:31:09.44#ibcon#about to read 3, iclass 22, count 2 2006.218.07:31:09.46#ibcon#read 3, iclass 22, count 2 2006.218.07:31:09.46#ibcon#about to read 4, iclass 22, count 2 2006.218.07:31:09.46#ibcon#read 4, iclass 22, count 2 2006.218.07:31:09.46#ibcon#about to read 5, iclass 22, count 2 2006.218.07:31:09.46#ibcon#read 5, iclass 22, count 2 2006.218.07:31:09.46#ibcon#about to read 6, iclass 22, count 2 2006.218.07:31:09.46#ibcon#read 6, iclass 22, count 2 2006.218.07:31:09.46#ibcon#end of sib2, iclass 22, count 2 2006.218.07:31:09.46#ibcon#*mode == 0, iclass 22, count 2 2006.218.07:31:09.46#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.218.07:31:09.46#ibcon#[25=AT08-07\r\n] 2006.218.07:31:09.46#ibcon#*before write, iclass 22, count 2 2006.218.07:31:09.46#ibcon#enter sib2, iclass 22, count 2 2006.218.07:31:09.46#ibcon#flushed, iclass 22, count 2 2006.218.07:31:09.46#ibcon#about to write, iclass 22, count 2 2006.218.07:31:09.46#ibcon#wrote, iclass 22, count 2 2006.218.07:31:09.46#ibcon#about to read 3, iclass 22, count 2 2006.218.07:31:09.49#ibcon#read 3, iclass 22, count 2 2006.218.07:31:09.49#ibcon#about to read 4, iclass 22, count 2 2006.218.07:31:09.49#ibcon#read 4, iclass 22, count 2 2006.218.07:31:09.49#ibcon#about to read 5, iclass 22, count 2 2006.218.07:31:09.49#ibcon#read 5, iclass 22, count 2 2006.218.07:31:09.49#ibcon#about to read 6, iclass 22, count 2 2006.218.07:31:09.49#ibcon#read 6, iclass 22, count 2 2006.218.07:31:09.49#ibcon#end of sib2, iclass 22, count 2 2006.218.07:31:09.49#ibcon#*after write, iclass 22, count 2 2006.218.07:31:09.49#ibcon#*before return 0, iclass 22, count 2 2006.218.07:31:09.49#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.218.07:31:09.49#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.218.07:31:09.49#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.218.07:31:09.49#ibcon#ireg 7 cls_cnt 0 2006.218.07:31:09.49#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.218.07:31:09.61#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.218.07:31:09.61#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.218.07:31:09.61#ibcon#enter wrdev, iclass 22, count 0 2006.218.07:31:09.61#ibcon#first serial, iclass 22, count 0 2006.218.07:31:09.61#ibcon#enter sib2, iclass 22, count 0 2006.218.07:31:09.61#ibcon#flushed, iclass 22, count 0 2006.218.07:31:09.61#ibcon#about to write, iclass 22, count 0 2006.218.07:31:09.61#ibcon#wrote, iclass 22, count 0 2006.218.07:31:09.61#ibcon#about to read 3, iclass 22, count 0 2006.218.07:31:09.63#ibcon#read 3, iclass 22, count 0 2006.218.07:31:09.63#ibcon#about to read 4, iclass 22, count 0 2006.218.07:31:09.63#ibcon#read 4, iclass 22, count 0 2006.218.07:31:09.63#ibcon#about to read 5, iclass 22, count 0 2006.218.07:31:09.63#ibcon#read 5, iclass 22, count 0 2006.218.07:31:09.63#ibcon#about to read 6, iclass 22, count 0 2006.218.07:31:09.63#ibcon#read 6, iclass 22, count 0 2006.218.07:31:09.63#ibcon#end of sib2, iclass 22, count 0 2006.218.07:31:09.63#ibcon#*mode == 0, iclass 22, count 0 2006.218.07:31:09.63#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.218.07:31:09.63#ibcon#[25=USB\r\n] 2006.218.07:31:09.63#ibcon#*before write, iclass 22, count 0 2006.218.07:31:09.63#ibcon#enter sib2, iclass 22, count 0 2006.218.07:31:09.63#ibcon#flushed, iclass 22, count 0 2006.218.07:31:09.63#ibcon#about to write, iclass 22, count 0 2006.218.07:31:09.63#ibcon#wrote, iclass 22, count 0 2006.218.07:31:09.63#ibcon#about to read 3, iclass 22, count 0 2006.218.07:31:09.66#ibcon#read 3, iclass 22, count 0 2006.218.07:31:09.66#ibcon#about to read 4, iclass 22, count 0 2006.218.07:31:09.66#ibcon#read 4, iclass 22, count 0 2006.218.07:31:09.66#ibcon#about to read 5, iclass 22, count 0 2006.218.07:31:09.66#ibcon#read 5, iclass 22, count 0 2006.218.07:31:09.66#ibcon#about to read 6, iclass 22, count 0 2006.218.07:31:09.66#ibcon#read 6, iclass 22, count 0 2006.218.07:31:09.66#ibcon#end of sib2, iclass 22, count 0 2006.218.07:31:09.66#ibcon#*after write, iclass 22, count 0 2006.218.07:31:09.66#ibcon#*before return 0, iclass 22, count 0 2006.218.07:31:09.66#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.218.07:31:09.66#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.218.07:31:09.66#ibcon#about to clear, iclass 22 cls_cnt 0 2006.218.07:31:09.66#ibcon#cleared, iclass 22 cls_cnt 0 2006.218.07:31:09.66$vc4f8/vblo=1,632.99 2006.218.07:31:09.66#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.218.07:31:09.66#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.218.07:31:09.66#ibcon#ireg 17 cls_cnt 0 2006.218.07:31:09.66#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.218.07:31:09.66#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.218.07:31:09.66#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.218.07:31:09.66#ibcon#enter wrdev, iclass 24, count 0 2006.218.07:31:09.66#ibcon#first serial, iclass 24, count 0 2006.218.07:31:09.66#ibcon#enter sib2, iclass 24, count 0 2006.218.07:31:09.66#ibcon#flushed, iclass 24, count 0 2006.218.07:31:09.66#ibcon#about to write, iclass 24, count 0 2006.218.07:31:09.66#ibcon#wrote, iclass 24, count 0 2006.218.07:31:09.66#ibcon#about to read 3, iclass 24, count 0 2006.218.07:31:09.69#ibcon#read 3, iclass 24, count 0 2006.218.07:31:09.69#ibcon#about to read 4, iclass 24, count 0 2006.218.07:31:09.69#ibcon#read 4, iclass 24, count 0 2006.218.07:31:09.69#ibcon#about to read 5, iclass 24, count 0 2006.218.07:31:09.69#ibcon#read 5, iclass 24, count 0 2006.218.07:31:09.69#ibcon#about to read 6, iclass 24, count 0 2006.218.07:31:09.69#ibcon#read 6, iclass 24, count 0 2006.218.07:31:09.69#ibcon#end of sib2, iclass 24, count 0 2006.218.07:31:09.69#ibcon#*mode == 0, iclass 24, count 0 2006.218.07:31:09.69#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.218.07:31:09.69#ibcon#[28=FRQ=01,632.99\r\n] 2006.218.07:31:09.69#ibcon#*before write, iclass 24, count 0 2006.218.07:31:09.69#ibcon#enter sib2, iclass 24, count 0 2006.218.07:31:09.69#ibcon#flushed, iclass 24, count 0 2006.218.07:31:09.69#ibcon#about to write, iclass 24, count 0 2006.218.07:31:09.69#ibcon#wrote, iclass 24, count 0 2006.218.07:31:09.69#ibcon#about to read 3, iclass 24, count 0 2006.218.07:31:09.73#ibcon#read 3, iclass 24, count 0 2006.218.07:31:09.73#ibcon#about to read 4, iclass 24, count 0 2006.218.07:31:09.73#ibcon#read 4, iclass 24, count 0 2006.218.07:31:09.73#ibcon#about to read 5, iclass 24, count 0 2006.218.07:31:09.73#ibcon#read 5, iclass 24, count 0 2006.218.07:31:09.73#ibcon#about to read 6, iclass 24, count 0 2006.218.07:31:09.73#ibcon#read 6, iclass 24, count 0 2006.218.07:31:09.73#ibcon#end of sib2, iclass 24, count 0 2006.218.07:31:09.73#ibcon#*after write, iclass 24, count 0 2006.218.07:31:09.73#ibcon#*before return 0, iclass 24, count 0 2006.218.07:31:09.73#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.218.07:31:09.73#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.218.07:31:09.73#ibcon#about to clear, iclass 24 cls_cnt 0 2006.218.07:31:09.73#ibcon#cleared, iclass 24 cls_cnt 0 2006.218.07:31:09.73$vc4f8/vb=1,4 2006.218.07:31:09.73#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.218.07:31:09.73#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.218.07:31:09.73#ibcon#ireg 11 cls_cnt 2 2006.218.07:31:09.73#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.218.07:31:09.73#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.218.07:31:09.73#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.218.07:31:09.73#ibcon#enter wrdev, iclass 26, count 2 2006.218.07:31:09.73#ibcon#first serial, iclass 26, count 2 2006.218.07:31:09.73#ibcon#enter sib2, iclass 26, count 2 2006.218.07:31:09.73#ibcon#flushed, iclass 26, count 2 2006.218.07:31:09.73#ibcon#about to write, iclass 26, count 2 2006.218.07:31:09.73#ibcon#wrote, iclass 26, count 2 2006.218.07:31:09.73#ibcon#about to read 3, iclass 26, count 2 2006.218.07:31:09.75#ibcon#read 3, iclass 26, count 2 2006.218.07:31:09.75#ibcon#about to read 4, iclass 26, count 2 2006.218.07:31:09.75#ibcon#read 4, iclass 26, count 2 2006.218.07:31:09.75#ibcon#about to read 5, iclass 26, count 2 2006.218.07:31:09.75#ibcon#read 5, iclass 26, count 2 2006.218.07:31:09.75#ibcon#about to read 6, iclass 26, count 2 2006.218.07:31:09.75#ibcon#read 6, iclass 26, count 2 2006.218.07:31:09.75#ibcon#end of sib2, iclass 26, count 2 2006.218.07:31:09.75#ibcon#*mode == 0, iclass 26, count 2 2006.218.07:31:09.75#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.218.07:31:09.75#ibcon#[27=AT01-04\r\n] 2006.218.07:31:09.75#ibcon#*before write, iclass 26, count 2 2006.218.07:31:09.75#ibcon#enter sib2, iclass 26, count 2 2006.218.07:31:09.75#ibcon#flushed, iclass 26, count 2 2006.218.07:31:09.75#ibcon#about to write, iclass 26, count 2 2006.218.07:31:09.75#ibcon#wrote, iclass 26, count 2 2006.218.07:31:09.75#ibcon#about to read 3, iclass 26, count 2 2006.218.07:31:09.78#ibcon#read 3, iclass 26, count 2 2006.218.07:31:09.78#ibcon#about to read 4, iclass 26, count 2 2006.218.07:31:09.78#ibcon#read 4, iclass 26, count 2 2006.218.07:31:09.78#ibcon#about to read 5, iclass 26, count 2 2006.218.07:31:09.78#ibcon#read 5, iclass 26, count 2 2006.218.07:31:09.78#ibcon#about to read 6, iclass 26, count 2 2006.218.07:31:09.78#ibcon#read 6, iclass 26, count 2 2006.218.07:31:09.78#ibcon#end of sib2, iclass 26, count 2 2006.218.07:31:09.78#ibcon#*after write, iclass 26, count 2 2006.218.07:31:09.78#ibcon#*before return 0, iclass 26, count 2 2006.218.07:31:09.78#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.218.07:31:09.78#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.218.07:31:09.78#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.218.07:31:09.78#ibcon#ireg 7 cls_cnt 0 2006.218.07:31:09.78#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.218.07:31:09.90#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.218.07:31:09.90#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.218.07:31:09.90#ibcon#enter wrdev, iclass 26, count 0 2006.218.07:31:09.90#ibcon#first serial, iclass 26, count 0 2006.218.07:31:09.90#ibcon#enter sib2, iclass 26, count 0 2006.218.07:31:09.90#ibcon#flushed, iclass 26, count 0 2006.218.07:31:09.90#ibcon#about to write, iclass 26, count 0 2006.218.07:31:09.90#ibcon#wrote, iclass 26, count 0 2006.218.07:31:09.90#ibcon#about to read 3, iclass 26, count 0 2006.218.07:31:09.92#ibcon#read 3, iclass 26, count 0 2006.218.07:31:09.92#ibcon#about to read 4, iclass 26, count 0 2006.218.07:31:09.92#ibcon#read 4, iclass 26, count 0 2006.218.07:31:09.92#ibcon#about to read 5, iclass 26, count 0 2006.218.07:31:09.92#ibcon#read 5, iclass 26, count 0 2006.218.07:31:09.92#ibcon#about to read 6, iclass 26, count 0 2006.218.07:31:09.92#ibcon#read 6, iclass 26, count 0 2006.218.07:31:09.92#ibcon#end of sib2, iclass 26, count 0 2006.218.07:31:09.92#ibcon#*mode == 0, iclass 26, count 0 2006.218.07:31:09.92#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.218.07:31:09.92#ibcon#[27=USB\r\n] 2006.218.07:31:09.92#ibcon#*before write, iclass 26, count 0 2006.218.07:31:09.92#ibcon#enter sib2, iclass 26, count 0 2006.218.07:31:09.92#ibcon#flushed, iclass 26, count 0 2006.218.07:31:09.92#ibcon#about to write, iclass 26, count 0 2006.218.07:31:09.92#ibcon#wrote, iclass 26, count 0 2006.218.07:31:09.92#ibcon#about to read 3, iclass 26, count 0 2006.218.07:31:09.95#ibcon#read 3, iclass 26, count 0 2006.218.07:31:09.95#ibcon#about to read 4, iclass 26, count 0 2006.218.07:31:09.95#ibcon#read 4, iclass 26, count 0 2006.218.07:31:09.95#ibcon#about to read 5, iclass 26, count 0 2006.218.07:31:09.95#ibcon#read 5, iclass 26, count 0 2006.218.07:31:09.95#ibcon#about to read 6, iclass 26, count 0 2006.218.07:31:09.95#ibcon#read 6, iclass 26, count 0 2006.218.07:31:09.95#ibcon#end of sib2, iclass 26, count 0 2006.218.07:31:09.95#ibcon#*after write, iclass 26, count 0 2006.218.07:31:09.95#ibcon#*before return 0, iclass 26, count 0 2006.218.07:31:09.95#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.218.07:31:09.95#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.218.07:31:09.95#ibcon#about to clear, iclass 26 cls_cnt 0 2006.218.07:31:09.95#ibcon#cleared, iclass 26 cls_cnt 0 2006.218.07:31:09.95$vc4f8/vblo=2,640.99 2006.218.07:31:09.95#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.218.07:31:09.95#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.218.07:31:09.95#ibcon#ireg 17 cls_cnt 0 2006.218.07:31:09.95#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.218.07:31:09.95#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.218.07:31:09.95#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.218.07:31:09.95#ibcon#enter wrdev, iclass 28, count 0 2006.218.07:31:09.95#ibcon#first serial, iclass 28, count 0 2006.218.07:31:09.95#ibcon#enter sib2, iclass 28, count 0 2006.218.07:31:09.95#ibcon#flushed, iclass 28, count 0 2006.218.07:31:09.95#ibcon#about to write, iclass 28, count 0 2006.218.07:31:09.95#ibcon#wrote, iclass 28, count 0 2006.218.07:31:09.95#ibcon#about to read 3, iclass 28, count 0 2006.218.07:31:09.97#ibcon#read 3, iclass 28, count 0 2006.218.07:31:09.97#ibcon#about to read 4, iclass 28, count 0 2006.218.07:31:09.97#ibcon#read 4, iclass 28, count 0 2006.218.07:31:09.97#ibcon#about to read 5, iclass 28, count 0 2006.218.07:31:09.97#ibcon#read 5, iclass 28, count 0 2006.218.07:31:09.97#ibcon#about to read 6, iclass 28, count 0 2006.218.07:31:09.97#ibcon#read 6, iclass 28, count 0 2006.218.07:31:09.97#ibcon#end of sib2, iclass 28, count 0 2006.218.07:31:09.97#ibcon#*mode == 0, iclass 28, count 0 2006.218.07:31:09.97#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.218.07:31:09.97#ibcon#[28=FRQ=02,640.99\r\n] 2006.218.07:31:09.97#ibcon#*before write, iclass 28, count 0 2006.218.07:31:09.97#ibcon#enter sib2, iclass 28, count 0 2006.218.07:31:09.97#ibcon#flushed, iclass 28, count 0 2006.218.07:31:09.97#ibcon#about to write, iclass 28, count 0 2006.218.07:31:09.97#ibcon#wrote, iclass 28, count 0 2006.218.07:31:09.97#ibcon#about to read 3, iclass 28, count 0 2006.218.07:31:10.01#ibcon#read 3, iclass 28, count 0 2006.218.07:31:10.01#ibcon#about to read 4, iclass 28, count 0 2006.218.07:31:10.01#ibcon#read 4, iclass 28, count 0 2006.218.07:31:10.01#ibcon#about to read 5, iclass 28, count 0 2006.218.07:31:10.01#ibcon#read 5, iclass 28, count 0 2006.218.07:31:10.01#ibcon#about to read 6, iclass 28, count 0 2006.218.07:31:10.01#ibcon#read 6, iclass 28, count 0 2006.218.07:31:10.01#ibcon#end of sib2, iclass 28, count 0 2006.218.07:31:10.01#ibcon#*after write, iclass 28, count 0 2006.218.07:31:10.01#ibcon#*before return 0, iclass 28, count 0 2006.218.07:31:10.01#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.218.07:31:10.01#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.218.07:31:10.01#ibcon#about to clear, iclass 28 cls_cnt 0 2006.218.07:31:10.01#ibcon#cleared, iclass 28 cls_cnt 0 2006.218.07:31:10.01$vc4f8/vb=2,4 2006.218.07:31:10.01#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.218.07:31:10.01#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.218.07:31:10.01#ibcon#ireg 11 cls_cnt 2 2006.218.07:31:10.01#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.218.07:31:10.07#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.218.07:31:10.07#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.218.07:31:10.07#ibcon#enter wrdev, iclass 30, count 2 2006.218.07:31:10.07#ibcon#first serial, iclass 30, count 2 2006.218.07:31:10.07#ibcon#enter sib2, iclass 30, count 2 2006.218.07:31:10.07#ibcon#flushed, iclass 30, count 2 2006.218.07:31:10.07#ibcon#about to write, iclass 30, count 2 2006.218.07:31:10.07#ibcon#wrote, iclass 30, count 2 2006.218.07:31:10.07#ibcon#about to read 3, iclass 30, count 2 2006.218.07:31:10.09#ibcon#read 3, iclass 30, count 2 2006.218.07:31:10.09#ibcon#about to read 4, iclass 30, count 2 2006.218.07:31:10.09#ibcon#read 4, iclass 30, count 2 2006.218.07:31:10.09#ibcon#about to read 5, iclass 30, count 2 2006.218.07:31:10.09#ibcon#read 5, iclass 30, count 2 2006.218.07:31:10.09#ibcon#about to read 6, iclass 30, count 2 2006.218.07:31:10.09#ibcon#read 6, iclass 30, count 2 2006.218.07:31:10.09#ibcon#end of sib2, iclass 30, count 2 2006.218.07:31:10.09#ibcon#*mode == 0, iclass 30, count 2 2006.218.07:31:10.09#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.218.07:31:10.09#ibcon#[27=AT02-04\r\n] 2006.218.07:31:10.09#ibcon#*before write, iclass 30, count 2 2006.218.07:31:10.09#ibcon#enter sib2, iclass 30, count 2 2006.218.07:31:10.09#ibcon#flushed, iclass 30, count 2 2006.218.07:31:10.09#ibcon#about to write, iclass 30, count 2 2006.218.07:31:10.09#ibcon#wrote, iclass 30, count 2 2006.218.07:31:10.09#ibcon#about to read 3, iclass 30, count 2 2006.218.07:31:10.12#ibcon#read 3, iclass 30, count 2 2006.218.07:31:10.12#ibcon#about to read 4, iclass 30, count 2 2006.218.07:31:10.12#ibcon#read 4, iclass 30, count 2 2006.218.07:31:10.12#ibcon#about to read 5, iclass 30, count 2 2006.218.07:31:10.12#ibcon#read 5, iclass 30, count 2 2006.218.07:31:10.12#ibcon#about to read 6, iclass 30, count 2 2006.218.07:31:10.12#ibcon#read 6, iclass 30, count 2 2006.218.07:31:10.12#ibcon#end of sib2, iclass 30, count 2 2006.218.07:31:10.12#ibcon#*after write, iclass 30, count 2 2006.218.07:31:10.12#ibcon#*before return 0, iclass 30, count 2 2006.218.07:31:10.12#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.218.07:31:10.12#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.218.07:31:10.12#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.218.07:31:10.12#ibcon#ireg 7 cls_cnt 0 2006.218.07:31:10.12#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.218.07:31:10.24#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.218.07:31:10.24#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.218.07:31:10.24#ibcon#enter wrdev, iclass 30, count 0 2006.218.07:31:10.24#ibcon#first serial, iclass 30, count 0 2006.218.07:31:10.24#ibcon#enter sib2, iclass 30, count 0 2006.218.07:31:10.24#ibcon#flushed, iclass 30, count 0 2006.218.07:31:10.24#ibcon#about to write, iclass 30, count 0 2006.218.07:31:10.24#ibcon#wrote, iclass 30, count 0 2006.218.07:31:10.24#ibcon#about to read 3, iclass 30, count 0 2006.218.07:31:10.26#ibcon#read 3, iclass 30, count 0 2006.218.07:31:10.26#ibcon#about to read 4, iclass 30, count 0 2006.218.07:31:10.26#ibcon#read 4, iclass 30, count 0 2006.218.07:31:10.26#ibcon#about to read 5, iclass 30, count 0 2006.218.07:31:10.26#ibcon#read 5, iclass 30, count 0 2006.218.07:31:10.26#ibcon#about to read 6, iclass 30, count 0 2006.218.07:31:10.26#ibcon#read 6, iclass 30, count 0 2006.218.07:31:10.26#ibcon#end of sib2, iclass 30, count 0 2006.218.07:31:10.26#ibcon#*mode == 0, iclass 30, count 0 2006.218.07:31:10.26#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.218.07:31:10.26#ibcon#[27=USB\r\n] 2006.218.07:31:10.26#ibcon#*before write, iclass 30, count 0 2006.218.07:31:10.26#ibcon#enter sib2, iclass 30, count 0 2006.218.07:31:10.26#ibcon#flushed, iclass 30, count 0 2006.218.07:31:10.26#ibcon#about to write, iclass 30, count 0 2006.218.07:31:10.26#ibcon#wrote, iclass 30, count 0 2006.218.07:31:10.26#ibcon#about to read 3, iclass 30, count 0 2006.218.07:31:10.29#ibcon#read 3, iclass 30, count 0 2006.218.07:31:10.29#ibcon#about to read 4, iclass 30, count 0 2006.218.07:31:10.29#ibcon#read 4, iclass 30, count 0 2006.218.07:31:10.29#ibcon#about to read 5, iclass 30, count 0 2006.218.07:31:10.29#ibcon#read 5, iclass 30, count 0 2006.218.07:31:10.29#ibcon#about to read 6, iclass 30, count 0 2006.218.07:31:10.29#ibcon#read 6, iclass 30, count 0 2006.218.07:31:10.29#ibcon#end of sib2, iclass 30, count 0 2006.218.07:31:10.29#ibcon#*after write, iclass 30, count 0 2006.218.07:31:10.29#ibcon#*before return 0, iclass 30, count 0 2006.218.07:31:10.29#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.218.07:31:10.29#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.218.07:31:10.29#ibcon#about to clear, iclass 30 cls_cnt 0 2006.218.07:31:10.29#ibcon#cleared, iclass 30 cls_cnt 0 2006.218.07:31:10.29$vc4f8/vblo=3,656.99 2006.218.07:31:10.29#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.218.07:31:10.29#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.218.07:31:10.29#ibcon#ireg 17 cls_cnt 0 2006.218.07:31:10.29#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.218.07:31:10.29#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.218.07:31:10.29#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.218.07:31:10.29#ibcon#enter wrdev, iclass 32, count 0 2006.218.07:31:10.29#ibcon#first serial, iclass 32, count 0 2006.218.07:31:10.29#ibcon#enter sib2, iclass 32, count 0 2006.218.07:31:10.29#ibcon#flushed, iclass 32, count 0 2006.218.07:31:10.29#ibcon#about to write, iclass 32, count 0 2006.218.07:31:10.29#ibcon#wrote, iclass 32, count 0 2006.218.07:31:10.29#ibcon#about to read 3, iclass 32, count 0 2006.218.07:31:10.31#ibcon#read 3, iclass 32, count 0 2006.218.07:31:10.31#ibcon#about to read 4, iclass 32, count 0 2006.218.07:31:10.31#ibcon#read 4, iclass 32, count 0 2006.218.07:31:10.31#ibcon#about to read 5, iclass 32, count 0 2006.218.07:31:10.31#ibcon#read 5, iclass 32, count 0 2006.218.07:31:10.31#ibcon#about to read 6, iclass 32, count 0 2006.218.07:31:10.31#ibcon#read 6, iclass 32, count 0 2006.218.07:31:10.31#ibcon#end of sib2, iclass 32, count 0 2006.218.07:31:10.31#ibcon#*mode == 0, iclass 32, count 0 2006.218.07:31:10.31#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.218.07:31:10.31#ibcon#[28=FRQ=03,656.99\r\n] 2006.218.07:31:10.31#ibcon#*before write, iclass 32, count 0 2006.218.07:31:10.31#ibcon#enter sib2, iclass 32, count 0 2006.218.07:31:10.31#ibcon#flushed, iclass 32, count 0 2006.218.07:31:10.31#ibcon#about to write, iclass 32, count 0 2006.218.07:31:10.31#ibcon#wrote, iclass 32, count 0 2006.218.07:31:10.31#ibcon#about to read 3, iclass 32, count 0 2006.218.07:31:10.35#ibcon#read 3, iclass 32, count 0 2006.218.07:31:10.35#ibcon#about to read 4, iclass 32, count 0 2006.218.07:31:10.35#ibcon#read 4, iclass 32, count 0 2006.218.07:31:10.35#ibcon#about to read 5, iclass 32, count 0 2006.218.07:31:10.35#ibcon#read 5, iclass 32, count 0 2006.218.07:31:10.35#ibcon#about to read 6, iclass 32, count 0 2006.218.07:31:10.35#ibcon#read 6, iclass 32, count 0 2006.218.07:31:10.35#ibcon#end of sib2, iclass 32, count 0 2006.218.07:31:10.35#ibcon#*after write, iclass 32, count 0 2006.218.07:31:10.35#ibcon#*before return 0, iclass 32, count 0 2006.218.07:31:10.35#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.218.07:31:10.35#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.218.07:31:10.35#ibcon#about to clear, iclass 32 cls_cnt 0 2006.218.07:31:10.35#ibcon#cleared, iclass 32 cls_cnt 0 2006.218.07:31:10.35$vc4f8/vb=3,4 2006.218.07:31:10.35#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.218.07:31:10.35#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.218.07:31:10.35#ibcon#ireg 11 cls_cnt 2 2006.218.07:31:10.35#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.218.07:31:10.41#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.218.07:31:10.41#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.218.07:31:10.41#ibcon#enter wrdev, iclass 34, count 2 2006.218.07:31:10.41#ibcon#first serial, iclass 34, count 2 2006.218.07:31:10.41#ibcon#enter sib2, iclass 34, count 2 2006.218.07:31:10.41#ibcon#flushed, iclass 34, count 2 2006.218.07:31:10.41#ibcon#about to write, iclass 34, count 2 2006.218.07:31:10.41#ibcon#wrote, iclass 34, count 2 2006.218.07:31:10.41#ibcon#about to read 3, iclass 34, count 2 2006.218.07:31:10.43#ibcon#read 3, iclass 34, count 2 2006.218.07:31:10.43#ibcon#about to read 4, iclass 34, count 2 2006.218.07:31:10.43#ibcon#read 4, iclass 34, count 2 2006.218.07:31:10.43#ibcon#about to read 5, iclass 34, count 2 2006.218.07:31:10.43#ibcon#read 5, iclass 34, count 2 2006.218.07:31:10.43#ibcon#about to read 6, iclass 34, count 2 2006.218.07:31:10.43#ibcon#read 6, iclass 34, count 2 2006.218.07:31:10.43#ibcon#end of sib2, iclass 34, count 2 2006.218.07:31:10.43#ibcon#*mode == 0, iclass 34, count 2 2006.218.07:31:10.43#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.218.07:31:10.43#ibcon#[27=AT03-04\r\n] 2006.218.07:31:10.43#ibcon#*before write, iclass 34, count 2 2006.218.07:31:10.43#ibcon#enter sib2, iclass 34, count 2 2006.218.07:31:10.43#ibcon#flushed, iclass 34, count 2 2006.218.07:31:10.43#ibcon#about to write, iclass 34, count 2 2006.218.07:31:10.43#ibcon#wrote, iclass 34, count 2 2006.218.07:31:10.43#ibcon#about to read 3, iclass 34, count 2 2006.218.07:31:10.46#ibcon#read 3, iclass 34, count 2 2006.218.07:31:10.46#ibcon#about to read 4, iclass 34, count 2 2006.218.07:31:10.46#ibcon#read 4, iclass 34, count 2 2006.218.07:31:10.46#ibcon#about to read 5, iclass 34, count 2 2006.218.07:31:10.46#ibcon#read 5, iclass 34, count 2 2006.218.07:31:10.46#ibcon#about to read 6, iclass 34, count 2 2006.218.07:31:10.46#ibcon#read 6, iclass 34, count 2 2006.218.07:31:10.46#ibcon#end of sib2, iclass 34, count 2 2006.218.07:31:10.46#ibcon#*after write, iclass 34, count 2 2006.218.07:31:10.46#ibcon#*before return 0, iclass 34, count 2 2006.218.07:31:10.46#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.218.07:31:10.46#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.218.07:31:10.46#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.218.07:31:10.46#ibcon#ireg 7 cls_cnt 0 2006.218.07:31:10.46#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.218.07:31:10.58#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.218.07:31:10.58#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.218.07:31:10.58#ibcon#enter wrdev, iclass 34, count 0 2006.218.07:31:10.58#ibcon#first serial, iclass 34, count 0 2006.218.07:31:10.58#ibcon#enter sib2, iclass 34, count 0 2006.218.07:31:10.58#ibcon#flushed, iclass 34, count 0 2006.218.07:31:10.58#ibcon#about to write, iclass 34, count 0 2006.218.07:31:10.58#ibcon#wrote, iclass 34, count 0 2006.218.07:31:10.58#ibcon#about to read 3, iclass 34, count 0 2006.218.07:31:10.60#ibcon#read 3, iclass 34, count 0 2006.218.07:31:10.60#ibcon#about to read 4, iclass 34, count 0 2006.218.07:31:10.60#ibcon#read 4, iclass 34, count 0 2006.218.07:31:10.60#ibcon#about to read 5, iclass 34, count 0 2006.218.07:31:10.60#ibcon#read 5, iclass 34, count 0 2006.218.07:31:10.60#ibcon#about to read 6, iclass 34, count 0 2006.218.07:31:10.60#ibcon#read 6, iclass 34, count 0 2006.218.07:31:10.60#ibcon#end of sib2, iclass 34, count 0 2006.218.07:31:10.60#ibcon#*mode == 0, iclass 34, count 0 2006.218.07:31:10.60#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.218.07:31:10.60#ibcon#[27=USB\r\n] 2006.218.07:31:10.60#ibcon#*before write, iclass 34, count 0 2006.218.07:31:10.60#ibcon#enter sib2, iclass 34, count 0 2006.218.07:31:10.60#ibcon#flushed, iclass 34, count 0 2006.218.07:31:10.60#ibcon#about to write, iclass 34, count 0 2006.218.07:31:10.60#ibcon#wrote, iclass 34, count 0 2006.218.07:31:10.60#ibcon#about to read 3, iclass 34, count 0 2006.218.07:31:10.63#ibcon#read 3, iclass 34, count 0 2006.218.07:31:10.63#ibcon#about to read 4, iclass 34, count 0 2006.218.07:31:10.63#ibcon#read 4, iclass 34, count 0 2006.218.07:31:10.63#ibcon#about to read 5, iclass 34, count 0 2006.218.07:31:10.63#ibcon#read 5, iclass 34, count 0 2006.218.07:31:10.63#ibcon#about to read 6, iclass 34, count 0 2006.218.07:31:10.63#ibcon#read 6, iclass 34, count 0 2006.218.07:31:10.63#ibcon#end of sib2, iclass 34, count 0 2006.218.07:31:10.63#ibcon#*after write, iclass 34, count 0 2006.218.07:31:10.63#ibcon#*before return 0, iclass 34, count 0 2006.218.07:31:10.63#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.218.07:31:10.63#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.218.07:31:10.63#ibcon#about to clear, iclass 34 cls_cnt 0 2006.218.07:31:10.63#ibcon#cleared, iclass 34 cls_cnt 0 2006.218.07:31:10.63$vc4f8/vblo=4,712.99 2006.218.07:31:10.63#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.218.07:31:10.63#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.218.07:31:10.63#ibcon#ireg 17 cls_cnt 0 2006.218.07:31:10.63#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.218.07:31:10.63#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.218.07:31:10.63#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.218.07:31:10.63#ibcon#enter wrdev, iclass 36, count 0 2006.218.07:31:10.63#ibcon#first serial, iclass 36, count 0 2006.218.07:31:10.63#ibcon#enter sib2, iclass 36, count 0 2006.218.07:31:10.63#ibcon#flushed, iclass 36, count 0 2006.218.07:31:10.63#ibcon#about to write, iclass 36, count 0 2006.218.07:31:10.63#ibcon#wrote, iclass 36, count 0 2006.218.07:31:10.63#ibcon#about to read 3, iclass 36, count 0 2006.218.07:31:10.66#ibcon#read 3, iclass 36, count 0 2006.218.07:31:10.66#ibcon#about to read 4, iclass 36, count 0 2006.218.07:31:10.66#ibcon#read 4, iclass 36, count 0 2006.218.07:31:10.66#ibcon#about to read 5, iclass 36, count 0 2006.218.07:31:10.66#ibcon#read 5, iclass 36, count 0 2006.218.07:31:10.66#ibcon#about to read 6, iclass 36, count 0 2006.218.07:31:10.66#ibcon#read 6, iclass 36, count 0 2006.218.07:31:10.66#ibcon#end of sib2, iclass 36, count 0 2006.218.07:31:10.66#ibcon#*mode == 0, iclass 36, count 0 2006.218.07:31:10.66#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.218.07:31:10.66#ibcon#[28=FRQ=04,712.99\r\n] 2006.218.07:31:10.66#ibcon#*before write, iclass 36, count 0 2006.218.07:31:10.66#ibcon#enter sib2, iclass 36, count 0 2006.218.07:31:10.66#ibcon#flushed, iclass 36, count 0 2006.218.07:31:10.66#ibcon#about to write, iclass 36, count 0 2006.218.07:31:10.66#ibcon#wrote, iclass 36, count 0 2006.218.07:31:10.66#ibcon#about to read 3, iclass 36, count 0 2006.218.07:31:10.70#ibcon#read 3, iclass 36, count 0 2006.218.07:31:10.70#ibcon#about to read 4, iclass 36, count 0 2006.218.07:31:10.70#ibcon#read 4, iclass 36, count 0 2006.218.07:31:10.70#ibcon#about to read 5, iclass 36, count 0 2006.218.07:31:10.70#ibcon#read 5, iclass 36, count 0 2006.218.07:31:10.70#ibcon#about to read 6, iclass 36, count 0 2006.218.07:31:10.70#ibcon#read 6, iclass 36, count 0 2006.218.07:31:10.70#ibcon#end of sib2, iclass 36, count 0 2006.218.07:31:10.70#ibcon#*after write, iclass 36, count 0 2006.218.07:31:10.70#ibcon#*before return 0, iclass 36, count 0 2006.218.07:31:10.70#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.218.07:31:10.70#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.218.07:31:10.70#ibcon#about to clear, iclass 36 cls_cnt 0 2006.218.07:31:10.70#ibcon#cleared, iclass 36 cls_cnt 0 2006.218.07:31:10.70$vc4f8/vb=4,4 2006.218.07:31:10.70#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.218.07:31:10.70#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.218.07:31:10.70#ibcon#ireg 11 cls_cnt 2 2006.218.07:31:10.70#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.218.07:31:10.75#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.218.07:31:10.75#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.218.07:31:10.75#ibcon#enter wrdev, iclass 38, count 2 2006.218.07:31:10.75#ibcon#first serial, iclass 38, count 2 2006.218.07:31:10.75#ibcon#enter sib2, iclass 38, count 2 2006.218.07:31:10.75#ibcon#flushed, iclass 38, count 2 2006.218.07:31:10.75#ibcon#about to write, iclass 38, count 2 2006.218.07:31:10.75#ibcon#wrote, iclass 38, count 2 2006.218.07:31:10.75#ibcon#about to read 3, iclass 38, count 2 2006.218.07:31:10.77#ibcon#read 3, iclass 38, count 2 2006.218.07:31:10.77#ibcon#about to read 4, iclass 38, count 2 2006.218.07:31:10.77#ibcon#read 4, iclass 38, count 2 2006.218.07:31:10.77#ibcon#about to read 5, iclass 38, count 2 2006.218.07:31:10.77#ibcon#read 5, iclass 38, count 2 2006.218.07:31:10.77#ibcon#about to read 6, iclass 38, count 2 2006.218.07:31:10.77#ibcon#read 6, iclass 38, count 2 2006.218.07:31:10.77#ibcon#end of sib2, iclass 38, count 2 2006.218.07:31:10.77#ibcon#*mode == 0, iclass 38, count 2 2006.218.07:31:10.77#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.218.07:31:10.77#ibcon#[27=AT04-04\r\n] 2006.218.07:31:10.77#ibcon#*before write, iclass 38, count 2 2006.218.07:31:10.77#ibcon#enter sib2, iclass 38, count 2 2006.218.07:31:10.77#ibcon#flushed, iclass 38, count 2 2006.218.07:31:10.77#ibcon#about to write, iclass 38, count 2 2006.218.07:31:10.77#ibcon#wrote, iclass 38, count 2 2006.218.07:31:10.77#ibcon#about to read 3, iclass 38, count 2 2006.218.07:31:10.80#ibcon#read 3, iclass 38, count 2 2006.218.07:31:10.80#ibcon#about to read 4, iclass 38, count 2 2006.218.07:31:10.80#ibcon#read 4, iclass 38, count 2 2006.218.07:31:10.80#ibcon#about to read 5, iclass 38, count 2 2006.218.07:31:10.80#ibcon#read 5, iclass 38, count 2 2006.218.07:31:10.80#ibcon#about to read 6, iclass 38, count 2 2006.218.07:31:10.80#ibcon#read 6, iclass 38, count 2 2006.218.07:31:10.80#ibcon#end of sib2, iclass 38, count 2 2006.218.07:31:10.80#ibcon#*after write, iclass 38, count 2 2006.218.07:31:10.80#ibcon#*before return 0, iclass 38, count 2 2006.218.07:31:10.80#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.218.07:31:10.80#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.218.07:31:10.80#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.218.07:31:10.80#ibcon#ireg 7 cls_cnt 0 2006.218.07:31:10.80#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.218.07:31:10.92#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.218.07:31:10.92#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.218.07:31:10.92#ibcon#enter wrdev, iclass 38, count 0 2006.218.07:31:10.92#ibcon#first serial, iclass 38, count 0 2006.218.07:31:10.92#ibcon#enter sib2, iclass 38, count 0 2006.218.07:31:10.92#ibcon#flushed, iclass 38, count 0 2006.218.07:31:10.92#ibcon#about to write, iclass 38, count 0 2006.218.07:31:10.92#ibcon#wrote, iclass 38, count 0 2006.218.07:31:10.92#ibcon#about to read 3, iclass 38, count 0 2006.218.07:31:10.94#ibcon#read 3, iclass 38, count 0 2006.218.07:31:10.94#ibcon#about to read 4, iclass 38, count 0 2006.218.07:31:10.94#ibcon#read 4, iclass 38, count 0 2006.218.07:31:10.94#ibcon#about to read 5, iclass 38, count 0 2006.218.07:31:10.94#ibcon#read 5, iclass 38, count 0 2006.218.07:31:10.94#ibcon#about to read 6, iclass 38, count 0 2006.218.07:31:10.94#ibcon#read 6, iclass 38, count 0 2006.218.07:31:10.94#ibcon#end of sib2, iclass 38, count 0 2006.218.07:31:10.94#ibcon#*mode == 0, iclass 38, count 0 2006.218.07:31:10.94#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.218.07:31:10.94#ibcon#[27=USB\r\n] 2006.218.07:31:10.94#ibcon#*before write, iclass 38, count 0 2006.218.07:31:10.94#ibcon#enter sib2, iclass 38, count 0 2006.218.07:31:10.94#ibcon#flushed, iclass 38, count 0 2006.218.07:31:10.94#ibcon#about to write, iclass 38, count 0 2006.218.07:31:10.94#ibcon#wrote, iclass 38, count 0 2006.218.07:31:10.94#ibcon#about to read 3, iclass 38, count 0 2006.218.07:31:10.97#ibcon#read 3, iclass 38, count 0 2006.218.07:31:10.97#ibcon#about to read 4, iclass 38, count 0 2006.218.07:31:10.97#ibcon#read 4, iclass 38, count 0 2006.218.07:31:10.97#ibcon#about to read 5, iclass 38, count 0 2006.218.07:31:10.97#ibcon#read 5, iclass 38, count 0 2006.218.07:31:10.97#ibcon#about to read 6, iclass 38, count 0 2006.218.07:31:10.97#ibcon#read 6, iclass 38, count 0 2006.218.07:31:10.97#ibcon#end of sib2, iclass 38, count 0 2006.218.07:31:10.97#ibcon#*after write, iclass 38, count 0 2006.218.07:31:10.97#ibcon#*before return 0, iclass 38, count 0 2006.218.07:31:10.97#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.218.07:31:10.97#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.218.07:31:10.97#ibcon#about to clear, iclass 38 cls_cnt 0 2006.218.07:31:10.97#ibcon#cleared, iclass 38 cls_cnt 0 2006.218.07:31:10.97$vc4f8/vblo=5,744.99 2006.218.07:31:10.97#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.218.07:31:10.97#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.218.07:31:10.97#ibcon#ireg 17 cls_cnt 0 2006.218.07:31:10.97#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.218.07:31:10.97#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.218.07:31:10.97#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.218.07:31:10.97#ibcon#enter wrdev, iclass 40, count 0 2006.218.07:31:10.97#ibcon#first serial, iclass 40, count 0 2006.218.07:31:10.97#ibcon#enter sib2, iclass 40, count 0 2006.218.07:31:10.97#ibcon#flushed, iclass 40, count 0 2006.218.07:31:10.97#ibcon#about to write, iclass 40, count 0 2006.218.07:31:10.97#ibcon#wrote, iclass 40, count 0 2006.218.07:31:10.97#ibcon#about to read 3, iclass 40, count 0 2006.218.07:31:10.99#ibcon#read 3, iclass 40, count 0 2006.218.07:31:10.99#ibcon#about to read 4, iclass 40, count 0 2006.218.07:31:10.99#ibcon#read 4, iclass 40, count 0 2006.218.07:31:10.99#ibcon#about to read 5, iclass 40, count 0 2006.218.07:31:10.99#ibcon#read 5, iclass 40, count 0 2006.218.07:31:10.99#ibcon#about to read 6, iclass 40, count 0 2006.218.07:31:10.99#ibcon#read 6, iclass 40, count 0 2006.218.07:31:10.99#ibcon#end of sib2, iclass 40, count 0 2006.218.07:31:10.99#ibcon#*mode == 0, iclass 40, count 0 2006.218.07:31:10.99#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.218.07:31:10.99#ibcon#[28=FRQ=05,744.99\r\n] 2006.218.07:31:10.99#ibcon#*before write, iclass 40, count 0 2006.218.07:31:10.99#ibcon#enter sib2, iclass 40, count 0 2006.218.07:31:10.99#ibcon#flushed, iclass 40, count 0 2006.218.07:31:10.99#ibcon#about to write, iclass 40, count 0 2006.218.07:31:10.99#ibcon#wrote, iclass 40, count 0 2006.218.07:31:10.99#ibcon#about to read 3, iclass 40, count 0 2006.218.07:31:11.03#ibcon#read 3, iclass 40, count 0 2006.218.07:31:11.03#ibcon#about to read 4, iclass 40, count 0 2006.218.07:31:11.03#ibcon#read 4, iclass 40, count 0 2006.218.07:31:11.03#ibcon#about to read 5, iclass 40, count 0 2006.218.07:31:11.03#ibcon#read 5, iclass 40, count 0 2006.218.07:31:11.03#ibcon#about to read 6, iclass 40, count 0 2006.218.07:31:11.03#ibcon#read 6, iclass 40, count 0 2006.218.07:31:11.03#ibcon#end of sib2, iclass 40, count 0 2006.218.07:31:11.03#ibcon#*after write, iclass 40, count 0 2006.218.07:31:11.03#ibcon#*before return 0, iclass 40, count 0 2006.218.07:31:11.03#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.218.07:31:11.03#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.218.07:31:11.03#ibcon#about to clear, iclass 40 cls_cnt 0 2006.218.07:31:11.03#ibcon#cleared, iclass 40 cls_cnt 0 2006.218.07:31:11.03$vc4f8/vb=5,4 2006.218.07:31:11.03#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.218.07:31:11.03#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.218.07:31:11.03#ibcon#ireg 11 cls_cnt 2 2006.218.07:31:11.03#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.218.07:31:11.04#abcon#<5=/07 4.0 7.4 31.76 721007.4\r\n> 2006.218.07:31:11.06#abcon#{5=INTERFACE CLEAR} 2006.218.07:31:11.09#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.218.07:31:11.09#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.218.07:31:11.09#ibcon#enter wrdev, iclass 5, count 2 2006.218.07:31:11.09#ibcon#first serial, iclass 5, count 2 2006.218.07:31:11.09#ibcon#enter sib2, iclass 5, count 2 2006.218.07:31:11.09#ibcon#flushed, iclass 5, count 2 2006.218.07:31:11.09#ibcon#about to write, iclass 5, count 2 2006.218.07:31:11.09#ibcon#wrote, iclass 5, count 2 2006.218.07:31:11.09#ibcon#about to read 3, iclass 5, count 2 2006.218.07:31:11.11#ibcon#read 3, iclass 5, count 2 2006.218.07:31:11.11#ibcon#about to read 4, iclass 5, count 2 2006.218.07:31:11.11#ibcon#read 4, iclass 5, count 2 2006.218.07:31:11.11#ibcon#about to read 5, iclass 5, count 2 2006.218.07:31:11.11#ibcon#read 5, iclass 5, count 2 2006.218.07:31:11.11#ibcon#about to read 6, iclass 5, count 2 2006.218.07:31:11.11#ibcon#read 6, iclass 5, count 2 2006.218.07:31:11.11#ibcon#end of sib2, iclass 5, count 2 2006.218.07:31:11.11#ibcon#*mode == 0, iclass 5, count 2 2006.218.07:31:11.11#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.218.07:31:11.11#ibcon#[27=AT05-04\r\n] 2006.218.07:31:11.11#ibcon#*before write, iclass 5, count 2 2006.218.07:31:11.11#ibcon#enter sib2, iclass 5, count 2 2006.218.07:31:11.11#ibcon#flushed, iclass 5, count 2 2006.218.07:31:11.11#ibcon#about to write, iclass 5, count 2 2006.218.07:31:11.11#ibcon#wrote, iclass 5, count 2 2006.218.07:31:11.11#ibcon#about to read 3, iclass 5, count 2 2006.218.07:31:11.12#abcon#[5=S1D000X0/0*\r\n] 2006.218.07:31:11.14#ibcon#read 3, iclass 5, count 2 2006.218.07:31:11.14#ibcon#about to read 4, iclass 5, count 2 2006.218.07:31:11.14#ibcon#read 4, iclass 5, count 2 2006.218.07:31:11.14#ibcon#about to read 5, iclass 5, count 2 2006.218.07:31:11.14#ibcon#read 5, iclass 5, count 2 2006.218.07:31:11.14#ibcon#about to read 6, iclass 5, count 2 2006.218.07:31:11.14#ibcon#read 6, iclass 5, count 2 2006.218.07:31:11.14#ibcon#end of sib2, iclass 5, count 2 2006.218.07:31:11.14#ibcon#*after write, iclass 5, count 2 2006.218.07:31:11.14#ibcon#*before return 0, iclass 5, count 2 2006.218.07:31:11.14#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.218.07:31:11.14#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.218.07:31:11.14#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.218.07:31:11.14#ibcon#ireg 7 cls_cnt 0 2006.218.07:31:11.14#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.218.07:31:11.26#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.218.07:31:11.26#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.218.07:31:11.26#ibcon#enter wrdev, iclass 5, count 0 2006.218.07:31:11.26#ibcon#first serial, iclass 5, count 0 2006.218.07:31:11.26#ibcon#enter sib2, iclass 5, count 0 2006.218.07:31:11.26#ibcon#flushed, iclass 5, count 0 2006.218.07:31:11.26#ibcon#about to write, iclass 5, count 0 2006.218.07:31:11.26#ibcon#wrote, iclass 5, count 0 2006.218.07:31:11.26#ibcon#about to read 3, iclass 5, count 0 2006.218.07:31:11.28#ibcon#read 3, iclass 5, count 0 2006.218.07:31:11.28#ibcon#about to read 4, iclass 5, count 0 2006.218.07:31:11.28#ibcon#read 4, iclass 5, count 0 2006.218.07:31:11.28#ibcon#about to read 5, iclass 5, count 0 2006.218.07:31:11.28#ibcon#read 5, iclass 5, count 0 2006.218.07:31:11.28#ibcon#about to read 6, iclass 5, count 0 2006.218.07:31:11.28#ibcon#read 6, iclass 5, count 0 2006.218.07:31:11.28#ibcon#end of sib2, iclass 5, count 0 2006.218.07:31:11.28#ibcon#*mode == 0, iclass 5, count 0 2006.218.07:31:11.28#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.218.07:31:11.28#ibcon#[27=USB\r\n] 2006.218.07:31:11.28#ibcon#*before write, iclass 5, count 0 2006.218.07:31:11.28#ibcon#enter sib2, iclass 5, count 0 2006.218.07:31:11.28#ibcon#flushed, iclass 5, count 0 2006.218.07:31:11.28#ibcon#about to write, iclass 5, count 0 2006.218.07:31:11.28#ibcon#wrote, iclass 5, count 0 2006.218.07:31:11.28#ibcon#about to read 3, iclass 5, count 0 2006.218.07:31:11.31#ibcon#read 3, iclass 5, count 0 2006.218.07:31:11.31#ibcon#about to read 4, iclass 5, count 0 2006.218.07:31:11.31#ibcon#read 4, iclass 5, count 0 2006.218.07:31:11.31#ibcon#about to read 5, iclass 5, count 0 2006.218.07:31:11.31#ibcon#read 5, iclass 5, count 0 2006.218.07:31:11.31#ibcon#about to read 6, iclass 5, count 0 2006.218.07:31:11.31#ibcon#read 6, iclass 5, count 0 2006.218.07:31:11.31#ibcon#end of sib2, iclass 5, count 0 2006.218.07:31:11.31#ibcon#*after write, iclass 5, count 0 2006.218.07:31:11.31#ibcon#*before return 0, iclass 5, count 0 2006.218.07:31:11.31#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.218.07:31:11.31#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.218.07:31:11.31#ibcon#about to clear, iclass 5 cls_cnt 0 2006.218.07:31:11.31#ibcon#cleared, iclass 5 cls_cnt 0 2006.218.07:31:11.31$vc4f8/vblo=6,752.99 2006.218.07:31:11.31#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.218.07:31:11.31#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.218.07:31:11.31#ibcon#ireg 17 cls_cnt 0 2006.218.07:31:11.31#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.218.07:31:11.31#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.218.07:31:11.31#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.218.07:31:11.31#ibcon#enter wrdev, iclass 12, count 0 2006.218.07:31:11.31#ibcon#first serial, iclass 12, count 0 2006.218.07:31:11.31#ibcon#enter sib2, iclass 12, count 0 2006.218.07:31:11.31#ibcon#flushed, iclass 12, count 0 2006.218.07:31:11.31#ibcon#about to write, iclass 12, count 0 2006.218.07:31:11.31#ibcon#wrote, iclass 12, count 0 2006.218.07:31:11.31#ibcon#about to read 3, iclass 12, count 0 2006.218.07:31:11.33#ibcon#read 3, iclass 12, count 0 2006.218.07:31:11.33#ibcon#about to read 4, iclass 12, count 0 2006.218.07:31:11.33#ibcon#read 4, iclass 12, count 0 2006.218.07:31:11.33#ibcon#about to read 5, iclass 12, count 0 2006.218.07:31:11.33#ibcon#read 5, iclass 12, count 0 2006.218.07:31:11.33#ibcon#about to read 6, iclass 12, count 0 2006.218.07:31:11.33#ibcon#read 6, iclass 12, count 0 2006.218.07:31:11.33#ibcon#end of sib2, iclass 12, count 0 2006.218.07:31:11.33#ibcon#*mode == 0, iclass 12, count 0 2006.218.07:31:11.33#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.218.07:31:11.33#ibcon#[28=FRQ=06,752.99\r\n] 2006.218.07:31:11.33#ibcon#*before write, iclass 12, count 0 2006.218.07:31:11.33#ibcon#enter sib2, iclass 12, count 0 2006.218.07:31:11.33#ibcon#flushed, iclass 12, count 0 2006.218.07:31:11.33#ibcon#about to write, iclass 12, count 0 2006.218.07:31:11.33#ibcon#wrote, iclass 12, count 0 2006.218.07:31:11.33#ibcon#about to read 3, iclass 12, count 0 2006.218.07:31:11.37#ibcon#read 3, iclass 12, count 0 2006.218.07:31:11.37#ibcon#about to read 4, iclass 12, count 0 2006.218.07:31:11.37#ibcon#read 4, iclass 12, count 0 2006.218.07:31:11.37#ibcon#about to read 5, iclass 12, count 0 2006.218.07:31:11.37#ibcon#read 5, iclass 12, count 0 2006.218.07:31:11.37#ibcon#about to read 6, iclass 12, count 0 2006.218.07:31:11.37#ibcon#read 6, iclass 12, count 0 2006.218.07:31:11.37#ibcon#end of sib2, iclass 12, count 0 2006.218.07:31:11.37#ibcon#*after write, iclass 12, count 0 2006.218.07:31:11.37#ibcon#*before return 0, iclass 12, count 0 2006.218.07:31:11.37#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.218.07:31:11.37#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.218.07:31:11.37#ibcon#about to clear, iclass 12 cls_cnt 0 2006.218.07:31:11.37#ibcon#cleared, iclass 12 cls_cnt 0 2006.218.07:31:11.37$vc4f8/vb=6,4 2006.218.07:31:11.37#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.218.07:31:11.37#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.218.07:31:11.37#ibcon#ireg 11 cls_cnt 2 2006.218.07:31:11.37#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.218.07:31:11.43#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.218.07:31:11.43#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.218.07:31:11.43#ibcon#enter wrdev, iclass 14, count 2 2006.218.07:31:11.43#ibcon#first serial, iclass 14, count 2 2006.218.07:31:11.43#ibcon#enter sib2, iclass 14, count 2 2006.218.07:31:11.43#ibcon#flushed, iclass 14, count 2 2006.218.07:31:11.43#ibcon#about to write, iclass 14, count 2 2006.218.07:31:11.43#ibcon#wrote, iclass 14, count 2 2006.218.07:31:11.43#ibcon#about to read 3, iclass 14, count 2 2006.218.07:31:11.45#ibcon#read 3, iclass 14, count 2 2006.218.07:31:11.45#ibcon#about to read 4, iclass 14, count 2 2006.218.07:31:11.45#ibcon#read 4, iclass 14, count 2 2006.218.07:31:11.45#ibcon#about to read 5, iclass 14, count 2 2006.218.07:31:11.45#ibcon#read 5, iclass 14, count 2 2006.218.07:31:11.45#ibcon#about to read 6, iclass 14, count 2 2006.218.07:31:11.45#ibcon#read 6, iclass 14, count 2 2006.218.07:31:11.45#ibcon#end of sib2, iclass 14, count 2 2006.218.07:31:11.45#ibcon#*mode == 0, iclass 14, count 2 2006.218.07:31:11.45#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.218.07:31:11.45#ibcon#[27=AT06-04\r\n] 2006.218.07:31:11.45#ibcon#*before write, iclass 14, count 2 2006.218.07:31:11.45#ibcon#enter sib2, iclass 14, count 2 2006.218.07:31:11.45#ibcon#flushed, iclass 14, count 2 2006.218.07:31:11.45#ibcon#about to write, iclass 14, count 2 2006.218.07:31:11.45#ibcon#wrote, iclass 14, count 2 2006.218.07:31:11.45#ibcon#about to read 3, iclass 14, count 2 2006.218.07:31:11.48#ibcon#read 3, iclass 14, count 2 2006.218.07:31:11.48#ibcon#about to read 4, iclass 14, count 2 2006.218.07:31:11.48#ibcon#read 4, iclass 14, count 2 2006.218.07:31:11.48#ibcon#about to read 5, iclass 14, count 2 2006.218.07:31:11.48#ibcon#read 5, iclass 14, count 2 2006.218.07:31:11.48#ibcon#about to read 6, iclass 14, count 2 2006.218.07:31:11.48#ibcon#read 6, iclass 14, count 2 2006.218.07:31:11.48#ibcon#end of sib2, iclass 14, count 2 2006.218.07:31:11.48#ibcon#*after write, iclass 14, count 2 2006.218.07:31:11.48#ibcon#*before return 0, iclass 14, count 2 2006.218.07:31:11.48#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.218.07:31:11.48#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.218.07:31:11.48#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.218.07:31:11.48#ibcon#ireg 7 cls_cnt 0 2006.218.07:31:11.48#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.218.07:31:11.60#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.218.07:31:11.60#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.218.07:31:11.60#ibcon#enter wrdev, iclass 14, count 0 2006.218.07:31:11.60#ibcon#first serial, iclass 14, count 0 2006.218.07:31:11.60#ibcon#enter sib2, iclass 14, count 0 2006.218.07:31:11.60#ibcon#flushed, iclass 14, count 0 2006.218.07:31:11.60#ibcon#about to write, iclass 14, count 0 2006.218.07:31:11.60#ibcon#wrote, iclass 14, count 0 2006.218.07:31:11.60#ibcon#about to read 3, iclass 14, count 0 2006.218.07:31:11.62#ibcon#read 3, iclass 14, count 0 2006.218.07:31:11.62#ibcon#about to read 4, iclass 14, count 0 2006.218.07:31:11.62#ibcon#read 4, iclass 14, count 0 2006.218.07:31:11.62#ibcon#about to read 5, iclass 14, count 0 2006.218.07:31:11.62#ibcon#read 5, iclass 14, count 0 2006.218.07:31:11.62#ibcon#about to read 6, iclass 14, count 0 2006.218.07:31:11.62#ibcon#read 6, iclass 14, count 0 2006.218.07:31:11.62#ibcon#end of sib2, iclass 14, count 0 2006.218.07:31:11.62#ibcon#*mode == 0, iclass 14, count 0 2006.218.07:31:11.62#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.218.07:31:11.62#ibcon#[27=USB\r\n] 2006.218.07:31:11.62#ibcon#*before write, iclass 14, count 0 2006.218.07:31:11.62#ibcon#enter sib2, iclass 14, count 0 2006.218.07:31:11.62#ibcon#flushed, iclass 14, count 0 2006.218.07:31:11.62#ibcon#about to write, iclass 14, count 0 2006.218.07:31:11.62#ibcon#wrote, iclass 14, count 0 2006.218.07:31:11.62#ibcon#about to read 3, iclass 14, count 0 2006.218.07:31:11.65#ibcon#read 3, iclass 14, count 0 2006.218.07:31:11.65#ibcon#about to read 4, iclass 14, count 0 2006.218.07:31:11.65#ibcon#read 4, iclass 14, count 0 2006.218.07:31:11.65#ibcon#about to read 5, iclass 14, count 0 2006.218.07:31:11.65#ibcon#read 5, iclass 14, count 0 2006.218.07:31:11.65#ibcon#about to read 6, iclass 14, count 0 2006.218.07:31:11.65#ibcon#read 6, iclass 14, count 0 2006.218.07:31:11.65#ibcon#end of sib2, iclass 14, count 0 2006.218.07:31:11.65#ibcon#*after write, iclass 14, count 0 2006.218.07:31:11.65#ibcon#*before return 0, iclass 14, count 0 2006.218.07:31:11.65#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.218.07:31:11.65#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.218.07:31:11.65#ibcon#about to clear, iclass 14 cls_cnt 0 2006.218.07:31:11.65#ibcon#cleared, iclass 14 cls_cnt 0 2006.218.07:31:11.65$vc4f8/vabw=wide 2006.218.07:31:11.65#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.218.07:31:11.65#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.218.07:31:11.65#ibcon#ireg 8 cls_cnt 0 2006.218.07:31:11.65#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.218.07:31:11.65#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.218.07:31:11.65#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.218.07:31:11.65#ibcon#enter wrdev, iclass 16, count 0 2006.218.07:31:11.65#ibcon#first serial, iclass 16, count 0 2006.218.07:31:11.65#ibcon#enter sib2, iclass 16, count 0 2006.218.07:31:11.65#ibcon#flushed, iclass 16, count 0 2006.218.07:31:11.65#ibcon#about to write, iclass 16, count 0 2006.218.07:31:11.65#ibcon#wrote, iclass 16, count 0 2006.218.07:31:11.65#ibcon#about to read 3, iclass 16, count 0 2006.218.07:31:11.67#ibcon#read 3, iclass 16, count 0 2006.218.07:31:11.67#ibcon#about to read 4, iclass 16, count 0 2006.218.07:31:11.67#ibcon#read 4, iclass 16, count 0 2006.218.07:31:11.67#ibcon#about to read 5, iclass 16, count 0 2006.218.07:31:11.67#ibcon#read 5, iclass 16, count 0 2006.218.07:31:11.67#ibcon#about to read 6, iclass 16, count 0 2006.218.07:31:11.67#ibcon#read 6, iclass 16, count 0 2006.218.07:31:11.67#ibcon#end of sib2, iclass 16, count 0 2006.218.07:31:11.67#ibcon#*mode == 0, iclass 16, count 0 2006.218.07:31:11.67#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.218.07:31:11.67#ibcon#[25=BW32\r\n] 2006.218.07:31:11.67#ibcon#*before write, iclass 16, count 0 2006.218.07:31:11.67#ibcon#enter sib2, iclass 16, count 0 2006.218.07:31:11.67#ibcon#flushed, iclass 16, count 0 2006.218.07:31:11.67#ibcon#about to write, iclass 16, count 0 2006.218.07:31:11.67#ibcon#wrote, iclass 16, count 0 2006.218.07:31:11.67#ibcon#about to read 3, iclass 16, count 0 2006.218.07:31:11.70#ibcon#read 3, iclass 16, count 0 2006.218.07:31:11.70#ibcon#about to read 4, iclass 16, count 0 2006.218.07:31:11.70#ibcon#read 4, iclass 16, count 0 2006.218.07:31:11.70#ibcon#about to read 5, iclass 16, count 0 2006.218.07:31:11.70#ibcon#read 5, iclass 16, count 0 2006.218.07:31:11.70#ibcon#about to read 6, iclass 16, count 0 2006.218.07:31:11.70#ibcon#read 6, iclass 16, count 0 2006.218.07:31:11.70#ibcon#end of sib2, iclass 16, count 0 2006.218.07:31:11.70#ibcon#*after write, iclass 16, count 0 2006.218.07:31:11.70#ibcon#*before return 0, iclass 16, count 0 2006.218.07:31:11.70#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.218.07:31:11.70#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.218.07:31:11.70#ibcon#about to clear, iclass 16 cls_cnt 0 2006.218.07:31:11.70#ibcon#cleared, iclass 16 cls_cnt 0 2006.218.07:31:11.70$vc4f8/vbbw=wide 2006.218.07:31:11.70#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.218.07:31:11.70#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.218.07:31:11.70#ibcon#ireg 8 cls_cnt 0 2006.218.07:31:11.70#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.218.07:31:11.77#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.218.07:31:11.77#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.218.07:31:11.77#ibcon#enter wrdev, iclass 18, count 0 2006.218.07:31:11.77#ibcon#first serial, iclass 18, count 0 2006.218.07:31:11.77#ibcon#enter sib2, iclass 18, count 0 2006.218.07:31:11.77#ibcon#flushed, iclass 18, count 0 2006.218.07:31:11.77#ibcon#about to write, iclass 18, count 0 2006.218.07:31:11.77#ibcon#wrote, iclass 18, count 0 2006.218.07:31:11.77#ibcon#about to read 3, iclass 18, count 0 2006.218.07:31:11.79#ibcon#read 3, iclass 18, count 0 2006.218.07:31:11.79#ibcon#about to read 4, iclass 18, count 0 2006.218.07:31:11.79#ibcon#read 4, iclass 18, count 0 2006.218.07:31:11.79#ibcon#about to read 5, iclass 18, count 0 2006.218.07:31:11.79#ibcon#read 5, iclass 18, count 0 2006.218.07:31:11.79#ibcon#about to read 6, iclass 18, count 0 2006.218.07:31:11.79#ibcon#read 6, iclass 18, count 0 2006.218.07:31:11.79#ibcon#end of sib2, iclass 18, count 0 2006.218.07:31:11.79#ibcon#*mode == 0, iclass 18, count 0 2006.218.07:31:11.79#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.218.07:31:11.79#ibcon#[27=BW32\r\n] 2006.218.07:31:11.79#ibcon#*before write, iclass 18, count 0 2006.218.07:31:11.79#ibcon#enter sib2, iclass 18, count 0 2006.218.07:31:11.79#ibcon#flushed, iclass 18, count 0 2006.218.07:31:11.79#ibcon#about to write, iclass 18, count 0 2006.218.07:31:11.79#ibcon#wrote, iclass 18, count 0 2006.218.07:31:11.79#ibcon#about to read 3, iclass 18, count 0 2006.218.07:31:11.82#ibcon#read 3, iclass 18, count 0 2006.218.07:31:11.82#ibcon#about to read 4, iclass 18, count 0 2006.218.07:31:11.82#ibcon#read 4, iclass 18, count 0 2006.218.07:31:11.82#ibcon#about to read 5, iclass 18, count 0 2006.218.07:31:11.82#ibcon#read 5, iclass 18, count 0 2006.218.07:31:11.82#ibcon#about to read 6, iclass 18, count 0 2006.218.07:31:11.82#ibcon#read 6, iclass 18, count 0 2006.218.07:31:11.82#ibcon#end of sib2, iclass 18, count 0 2006.218.07:31:11.82#ibcon#*after write, iclass 18, count 0 2006.218.07:31:11.82#ibcon#*before return 0, iclass 18, count 0 2006.218.07:31:11.82#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.218.07:31:11.82#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.218.07:31:11.82#ibcon#about to clear, iclass 18 cls_cnt 0 2006.218.07:31:11.82#ibcon#cleared, iclass 18 cls_cnt 0 2006.218.07:31:11.82$4f8m12a/ifd4f 2006.218.07:31:11.82$ifd4f/lo= 2006.218.07:31:11.82$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.218.07:31:11.82$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.218.07:31:11.82$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.218.07:31:11.82$ifd4f/patch= 2006.218.07:31:11.82$ifd4f/patch=lo1,a1,a2,a3,a4 2006.218.07:31:11.82$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.218.07:31:11.82$ifd4f/patch=lo3,a5,a6,a7,a8 2006.218.07:31:11.82$4f8m12a/"form=m,16.000,1:2 2006.218.07:31:11.82$4f8m12a/"tpicd 2006.218.07:31:11.82$4f8m12a/echo=off 2006.218.07:31:11.82$4f8m12a/xlog=off 2006.218.07:31:11.82:!2006.218.07:33:20 2006.218.07:31:53.14#trakl#Source acquired 2006.218.07:31:54.14#flagr#flagr/antenna,acquired 2006.218.07:33:20.00:preob 2006.218.07:33:20.14/onsource/TRACKING 2006.218.07:33:20.14:!2006.218.07:33:30 2006.218.07:33:30.00:data_valid=on 2006.218.07:33:30.00:midob 2006.218.07:33:30.14/onsource/TRACKING 2006.218.07:33:30.14/wx/31.67,1007.4,70 2006.218.07:33:30.26/cable/+6.3840E-03 2006.218.07:33:31.35/va/01,05,usb,yes,39,41 2006.218.07:33:31.35/va/02,04,usb,yes,36,38 2006.218.07:33:31.35/va/03,04,usb,yes,34,35 2006.218.07:33:31.35/va/04,04,usb,yes,38,41 2006.218.07:33:31.35/va/05,07,usb,yes,40,42 2006.218.07:33:31.35/va/06,06,usb,yes,39,39 2006.218.07:33:31.35/va/07,06,usb,yes,40,40 2006.218.07:33:31.35/va/08,07,usb,yes,38,37 2006.218.07:33:31.58/valo/01,532.99,yes,locked 2006.218.07:33:31.58/valo/02,572.99,yes,locked 2006.218.07:33:31.58/valo/03,672.99,yes,locked 2006.218.07:33:31.58/valo/04,832.99,yes,locked 2006.218.07:33:31.58/valo/05,652.99,yes,locked 2006.218.07:33:31.58/valo/06,772.99,yes,locked 2006.218.07:33:31.58/valo/07,832.99,yes,locked 2006.218.07:33:31.58/valo/08,852.99,yes,locked 2006.218.07:33:32.67/vb/01,04,usb,yes,33,31 2006.218.07:33:32.67/vb/02,04,usb,yes,35,36 2006.218.07:33:32.67/vb/03,04,usb,yes,31,35 2006.218.07:33:32.67/vb/04,04,usb,yes,32,32 2006.218.07:33:32.67/vb/05,04,usb,yes,30,34 2006.218.07:33:32.67/vb/06,04,usb,yes,31,34 2006.218.07:33:32.67/vb/07,04,usb,yes,34,33 2006.218.07:33:32.67/vb/08,04,usb,yes,31,34 2006.218.07:33:32.91/vblo/01,632.99,yes,locked 2006.218.07:33:32.91/vblo/02,640.99,yes,locked 2006.218.07:33:32.91/vblo/03,656.99,yes,locked 2006.218.07:33:32.91/vblo/04,712.99,yes,locked 2006.218.07:33:32.91/vblo/05,744.99,yes,locked 2006.218.07:33:32.91/vblo/06,752.99,yes,locked 2006.218.07:33:32.91/vblo/07,734.99,yes,locked 2006.218.07:33:32.91/vblo/08,744.99,yes,locked 2006.218.07:33:33.06/vabw/8 2006.218.07:33:33.21/vbbw/8 2006.218.07:33:33.30/xfe/off,on,15.0 2006.218.07:33:33.68/ifatt/23,28,28,28 2006.218.07:33:34.07/fmout-gps/S +4.73E-07 2006.218.07:33:34.11:!2006.218.07:34:30 2006.218.07:34:30.00:data_valid=off 2006.218.07:34:30.00:postob 2006.218.07:34:30.14/cable/+6.3847E-03 2006.218.07:34:30.14/wx/31.63,1007.4,71 2006.218.07:34:31.07/fmout-gps/S +4.74E-07 2006.218.07:34:31.07:scan_name=218-0735,k06218,60 2006.218.07:34:31.08:source=0955+476,095819.67,472507.8,2000.0,ccw 2006.218.07:34:31.14#flagr#flagr/antenna,new-source 2006.218.07:34:32.14:checkk5 2006.218.07:34:32.51/chk_autoobs//k5ts1/ autoobs is running! 2006.218.07:34:32.89/chk_autoobs//k5ts2/ autoobs is running! 2006.218.07:34:33.27/chk_autoobs//k5ts3/ autoobs is running! 2006.218.07:34:33.64/chk_autoobs//k5ts4/ autoobs is running! 2006.218.07:34:34.02/chk_obsdata//k5ts1/T2180733??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:34:34.38/chk_obsdata//k5ts2/T2180733??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:34:34.75/chk_obsdata//k5ts3/T2180733??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:34:35.12/chk_obsdata//k5ts4/T2180733??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:34:35.80/k5log//k5ts1_log_newline 2006.218.07:34:36.50/k5log//k5ts2_log_newline 2006.218.07:34:37.19/k5log//k5ts3_log_newline 2006.218.07:34:37.88/k5log//k5ts4_log_newline 2006.218.07:34:37.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.218.07:34:37.90:4f8m12a=1 2006.218.07:34:37.90$4f8m12a/echo=on 2006.218.07:34:37.90$4f8m12a/pcalon 2006.218.07:34:37.90$pcalon/"no phase cal control is implemented here 2006.218.07:34:37.90$4f8m12a/"tpicd=stop 2006.218.07:34:37.90$4f8m12a/vc4f8 2006.218.07:34:37.90$vc4f8/valo=1,532.99 2006.218.07:34:37.90#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.218.07:34:37.90#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.218.07:34:37.90#ibcon#ireg 17 cls_cnt 0 2006.218.07:34:37.90#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.218.07:34:37.90#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.218.07:34:37.90#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.218.07:34:37.90#ibcon#enter wrdev, iclass 29, count 0 2006.218.07:34:37.90#ibcon#first serial, iclass 29, count 0 2006.218.07:34:37.90#ibcon#enter sib2, iclass 29, count 0 2006.218.07:34:37.90#ibcon#flushed, iclass 29, count 0 2006.218.07:34:37.90#ibcon#about to write, iclass 29, count 0 2006.218.07:34:37.90#ibcon#wrote, iclass 29, count 0 2006.218.07:34:37.90#ibcon#about to read 3, iclass 29, count 0 2006.218.07:34:37.92#ibcon#read 3, iclass 29, count 0 2006.218.07:34:37.92#ibcon#about to read 4, iclass 29, count 0 2006.218.07:34:37.92#ibcon#read 4, iclass 29, count 0 2006.218.07:34:37.92#ibcon#about to read 5, iclass 29, count 0 2006.218.07:34:37.92#ibcon#read 5, iclass 29, count 0 2006.218.07:34:37.92#ibcon#about to read 6, iclass 29, count 0 2006.218.07:34:37.92#ibcon#read 6, iclass 29, count 0 2006.218.07:34:37.92#ibcon#end of sib2, iclass 29, count 0 2006.218.07:34:37.92#ibcon#*mode == 0, iclass 29, count 0 2006.218.07:34:37.92#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.218.07:34:37.92#ibcon#[26=FRQ=01,532.99\r\n] 2006.218.07:34:37.92#ibcon#*before write, iclass 29, count 0 2006.218.07:34:37.92#ibcon#enter sib2, iclass 29, count 0 2006.218.07:34:37.92#ibcon#flushed, iclass 29, count 0 2006.218.07:34:37.92#ibcon#about to write, iclass 29, count 0 2006.218.07:34:37.92#ibcon#wrote, iclass 29, count 0 2006.218.07:34:37.92#ibcon#about to read 3, iclass 29, count 0 2006.218.07:34:37.97#ibcon#read 3, iclass 29, count 0 2006.218.07:34:37.97#ibcon#about to read 4, iclass 29, count 0 2006.218.07:34:37.97#ibcon#read 4, iclass 29, count 0 2006.218.07:34:37.97#ibcon#about to read 5, iclass 29, count 0 2006.218.07:34:37.97#ibcon#read 5, iclass 29, count 0 2006.218.07:34:37.97#ibcon#about to read 6, iclass 29, count 0 2006.218.07:34:37.97#ibcon#read 6, iclass 29, count 0 2006.218.07:34:37.97#ibcon#end of sib2, iclass 29, count 0 2006.218.07:34:37.97#ibcon#*after write, iclass 29, count 0 2006.218.07:34:37.97#ibcon#*before return 0, iclass 29, count 0 2006.218.07:34:37.97#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.218.07:34:37.97#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.218.07:34:37.97#ibcon#about to clear, iclass 29 cls_cnt 0 2006.218.07:34:37.97#ibcon#cleared, iclass 29 cls_cnt 0 2006.218.07:34:37.97$vc4f8/va=1,5 2006.218.07:34:37.97#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.218.07:34:37.97#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.218.07:34:37.97#ibcon#ireg 11 cls_cnt 2 2006.218.07:34:37.97#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.218.07:34:37.97#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.218.07:34:37.97#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.218.07:34:37.97#ibcon#enter wrdev, iclass 31, count 2 2006.218.07:34:37.97#ibcon#first serial, iclass 31, count 2 2006.218.07:34:37.97#ibcon#enter sib2, iclass 31, count 2 2006.218.07:34:37.97#ibcon#flushed, iclass 31, count 2 2006.218.07:34:37.97#ibcon#about to write, iclass 31, count 2 2006.218.07:34:37.97#ibcon#wrote, iclass 31, count 2 2006.218.07:34:37.97#ibcon#about to read 3, iclass 31, count 2 2006.218.07:34:37.99#ibcon#read 3, iclass 31, count 2 2006.218.07:34:37.99#ibcon#about to read 4, iclass 31, count 2 2006.218.07:34:37.99#ibcon#read 4, iclass 31, count 2 2006.218.07:34:37.99#ibcon#about to read 5, iclass 31, count 2 2006.218.07:34:37.99#ibcon#read 5, iclass 31, count 2 2006.218.07:34:37.99#ibcon#about to read 6, iclass 31, count 2 2006.218.07:34:37.99#ibcon#read 6, iclass 31, count 2 2006.218.07:34:37.99#ibcon#end of sib2, iclass 31, count 2 2006.218.07:34:37.99#ibcon#*mode == 0, iclass 31, count 2 2006.218.07:34:37.99#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.218.07:34:37.99#ibcon#[25=AT01-05\r\n] 2006.218.07:34:37.99#ibcon#*before write, iclass 31, count 2 2006.218.07:34:37.99#ibcon#enter sib2, iclass 31, count 2 2006.218.07:34:37.99#ibcon#flushed, iclass 31, count 2 2006.218.07:34:37.99#ibcon#about to write, iclass 31, count 2 2006.218.07:34:37.99#ibcon#wrote, iclass 31, count 2 2006.218.07:34:37.99#ibcon#about to read 3, iclass 31, count 2 2006.218.07:34:38.02#ibcon#read 3, iclass 31, count 2 2006.218.07:34:38.02#ibcon#about to read 4, iclass 31, count 2 2006.218.07:34:38.02#ibcon#read 4, iclass 31, count 2 2006.218.07:34:38.02#ibcon#about to read 5, iclass 31, count 2 2006.218.07:34:38.02#ibcon#read 5, iclass 31, count 2 2006.218.07:34:38.02#ibcon#about to read 6, iclass 31, count 2 2006.218.07:34:38.02#ibcon#read 6, iclass 31, count 2 2006.218.07:34:38.02#ibcon#end of sib2, iclass 31, count 2 2006.218.07:34:38.02#ibcon#*after write, iclass 31, count 2 2006.218.07:34:38.02#ibcon#*before return 0, iclass 31, count 2 2006.218.07:34:38.02#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.218.07:34:38.02#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.218.07:34:38.02#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.218.07:34:38.02#ibcon#ireg 7 cls_cnt 0 2006.218.07:34:38.02#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.218.07:34:38.14#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.218.07:34:38.14#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.218.07:34:38.14#ibcon#enter wrdev, iclass 31, count 0 2006.218.07:34:38.14#ibcon#first serial, iclass 31, count 0 2006.218.07:34:38.14#ibcon#enter sib2, iclass 31, count 0 2006.218.07:34:38.14#ibcon#flushed, iclass 31, count 0 2006.218.07:34:38.14#ibcon#about to write, iclass 31, count 0 2006.218.07:34:38.14#ibcon#wrote, iclass 31, count 0 2006.218.07:34:38.14#ibcon#about to read 3, iclass 31, count 0 2006.218.07:34:38.16#ibcon#read 3, iclass 31, count 0 2006.218.07:34:38.16#ibcon#about to read 4, iclass 31, count 0 2006.218.07:34:38.16#ibcon#read 4, iclass 31, count 0 2006.218.07:34:38.16#ibcon#about to read 5, iclass 31, count 0 2006.218.07:34:38.16#ibcon#read 5, iclass 31, count 0 2006.218.07:34:38.16#ibcon#about to read 6, iclass 31, count 0 2006.218.07:34:38.16#ibcon#read 6, iclass 31, count 0 2006.218.07:34:38.16#ibcon#end of sib2, iclass 31, count 0 2006.218.07:34:38.16#ibcon#*mode == 0, iclass 31, count 0 2006.218.07:34:38.16#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.218.07:34:38.16#ibcon#[25=USB\r\n] 2006.218.07:34:38.16#ibcon#*before write, iclass 31, count 0 2006.218.07:34:38.16#ibcon#enter sib2, iclass 31, count 0 2006.218.07:34:38.16#ibcon#flushed, iclass 31, count 0 2006.218.07:34:38.16#ibcon#about to write, iclass 31, count 0 2006.218.07:34:38.16#ibcon#wrote, iclass 31, count 0 2006.218.07:34:38.16#ibcon#about to read 3, iclass 31, count 0 2006.218.07:34:38.19#ibcon#read 3, iclass 31, count 0 2006.218.07:34:38.19#ibcon#about to read 4, iclass 31, count 0 2006.218.07:34:38.19#ibcon#read 4, iclass 31, count 0 2006.218.07:34:38.19#ibcon#about to read 5, iclass 31, count 0 2006.218.07:34:38.19#ibcon#read 5, iclass 31, count 0 2006.218.07:34:38.19#ibcon#about to read 6, iclass 31, count 0 2006.218.07:34:38.19#ibcon#read 6, iclass 31, count 0 2006.218.07:34:38.19#ibcon#end of sib2, iclass 31, count 0 2006.218.07:34:38.19#ibcon#*after write, iclass 31, count 0 2006.218.07:34:38.19#ibcon#*before return 0, iclass 31, count 0 2006.218.07:34:38.19#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.218.07:34:38.19#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.218.07:34:38.19#ibcon#about to clear, iclass 31 cls_cnt 0 2006.218.07:34:38.19#ibcon#cleared, iclass 31 cls_cnt 0 2006.218.07:34:38.19$vc4f8/valo=2,572.99 2006.218.07:34:38.19#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.218.07:34:38.19#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.218.07:34:38.19#ibcon#ireg 17 cls_cnt 0 2006.218.07:34:38.19#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.218.07:34:38.19#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.218.07:34:38.19#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.218.07:34:38.19#ibcon#enter wrdev, iclass 33, count 0 2006.218.07:34:38.19#ibcon#first serial, iclass 33, count 0 2006.218.07:34:38.19#ibcon#enter sib2, iclass 33, count 0 2006.218.07:34:38.19#ibcon#flushed, iclass 33, count 0 2006.218.07:34:38.19#ibcon#about to write, iclass 33, count 0 2006.218.07:34:38.19#ibcon#wrote, iclass 33, count 0 2006.218.07:34:38.19#ibcon#about to read 3, iclass 33, count 0 2006.218.07:34:38.21#ibcon#read 3, iclass 33, count 0 2006.218.07:34:38.21#ibcon#about to read 4, iclass 33, count 0 2006.218.07:34:38.21#ibcon#read 4, iclass 33, count 0 2006.218.07:34:38.21#ibcon#about to read 5, iclass 33, count 0 2006.218.07:34:38.21#ibcon#read 5, iclass 33, count 0 2006.218.07:34:38.21#ibcon#about to read 6, iclass 33, count 0 2006.218.07:34:38.21#ibcon#read 6, iclass 33, count 0 2006.218.07:34:38.21#ibcon#end of sib2, iclass 33, count 0 2006.218.07:34:38.21#ibcon#*mode == 0, iclass 33, count 0 2006.218.07:34:38.21#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.218.07:34:38.21#ibcon#[26=FRQ=02,572.99\r\n] 2006.218.07:34:38.21#ibcon#*before write, iclass 33, count 0 2006.218.07:34:38.21#ibcon#enter sib2, iclass 33, count 0 2006.218.07:34:38.21#ibcon#flushed, iclass 33, count 0 2006.218.07:34:38.21#ibcon#about to write, iclass 33, count 0 2006.218.07:34:38.21#ibcon#wrote, iclass 33, count 0 2006.218.07:34:38.21#ibcon#about to read 3, iclass 33, count 0 2006.218.07:34:38.26#ibcon#read 3, iclass 33, count 0 2006.218.07:34:38.26#ibcon#about to read 4, iclass 33, count 0 2006.218.07:34:38.26#ibcon#read 4, iclass 33, count 0 2006.218.07:34:38.26#ibcon#about to read 5, iclass 33, count 0 2006.218.07:34:38.26#ibcon#read 5, iclass 33, count 0 2006.218.07:34:38.26#ibcon#about to read 6, iclass 33, count 0 2006.218.07:34:38.26#ibcon#read 6, iclass 33, count 0 2006.218.07:34:38.26#ibcon#end of sib2, iclass 33, count 0 2006.218.07:34:38.26#ibcon#*after write, iclass 33, count 0 2006.218.07:34:38.26#ibcon#*before return 0, iclass 33, count 0 2006.218.07:34:38.26#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.218.07:34:38.26#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.218.07:34:38.26#ibcon#about to clear, iclass 33 cls_cnt 0 2006.218.07:34:38.26#ibcon#cleared, iclass 33 cls_cnt 0 2006.218.07:34:38.26$vc4f8/va=2,4 2006.218.07:34:38.26#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.218.07:34:38.26#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.218.07:34:38.26#ibcon#ireg 11 cls_cnt 2 2006.218.07:34:38.26#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.218.07:34:38.31#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.218.07:34:38.31#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.218.07:34:38.31#ibcon#enter wrdev, iclass 35, count 2 2006.218.07:34:38.31#ibcon#first serial, iclass 35, count 2 2006.218.07:34:38.31#ibcon#enter sib2, iclass 35, count 2 2006.218.07:34:38.31#ibcon#flushed, iclass 35, count 2 2006.218.07:34:38.31#ibcon#about to write, iclass 35, count 2 2006.218.07:34:38.31#ibcon#wrote, iclass 35, count 2 2006.218.07:34:38.31#ibcon#about to read 3, iclass 35, count 2 2006.218.07:34:38.33#ibcon#read 3, iclass 35, count 2 2006.218.07:34:38.33#ibcon#about to read 4, iclass 35, count 2 2006.218.07:34:38.33#ibcon#read 4, iclass 35, count 2 2006.218.07:34:38.33#ibcon#about to read 5, iclass 35, count 2 2006.218.07:34:38.33#ibcon#read 5, iclass 35, count 2 2006.218.07:34:38.33#ibcon#about to read 6, iclass 35, count 2 2006.218.07:34:38.33#ibcon#read 6, iclass 35, count 2 2006.218.07:34:38.33#ibcon#end of sib2, iclass 35, count 2 2006.218.07:34:38.33#ibcon#*mode == 0, iclass 35, count 2 2006.218.07:34:38.33#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.218.07:34:38.33#ibcon#[25=AT02-04\r\n] 2006.218.07:34:38.33#ibcon#*before write, iclass 35, count 2 2006.218.07:34:38.33#ibcon#enter sib2, iclass 35, count 2 2006.218.07:34:38.33#ibcon#flushed, iclass 35, count 2 2006.218.07:34:38.33#ibcon#about to write, iclass 35, count 2 2006.218.07:34:38.33#ibcon#wrote, iclass 35, count 2 2006.218.07:34:38.33#ibcon#about to read 3, iclass 35, count 2 2006.218.07:34:38.36#ibcon#read 3, iclass 35, count 2 2006.218.07:34:38.36#ibcon#about to read 4, iclass 35, count 2 2006.218.07:34:38.36#ibcon#read 4, iclass 35, count 2 2006.218.07:34:38.36#ibcon#about to read 5, iclass 35, count 2 2006.218.07:34:38.36#ibcon#read 5, iclass 35, count 2 2006.218.07:34:38.36#ibcon#about to read 6, iclass 35, count 2 2006.218.07:34:38.36#ibcon#read 6, iclass 35, count 2 2006.218.07:34:38.36#ibcon#end of sib2, iclass 35, count 2 2006.218.07:34:38.36#ibcon#*after write, iclass 35, count 2 2006.218.07:34:38.36#ibcon#*before return 0, iclass 35, count 2 2006.218.07:34:38.36#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.218.07:34:38.36#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.218.07:34:38.36#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.218.07:34:38.36#ibcon#ireg 7 cls_cnt 0 2006.218.07:34:38.36#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.218.07:34:38.48#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.218.07:34:38.48#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.218.07:34:38.48#ibcon#enter wrdev, iclass 35, count 0 2006.218.07:34:38.48#ibcon#first serial, iclass 35, count 0 2006.218.07:34:38.48#ibcon#enter sib2, iclass 35, count 0 2006.218.07:34:38.48#ibcon#flushed, iclass 35, count 0 2006.218.07:34:38.48#ibcon#about to write, iclass 35, count 0 2006.218.07:34:38.48#ibcon#wrote, iclass 35, count 0 2006.218.07:34:38.48#ibcon#about to read 3, iclass 35, count 0 2006.218.07:34:38.50#ibcon#read 3, iclass 35, count 0 2006.218.07:34:38.50#ibcon#about to read 4, iclass 35, count 0 2006.218.07:34:38.50#ibcon#read 4, iclass 35, count 0 2006.218.07:34:38.50#ibcon#about to read 5, iclass 35, count 0 2006.218.07:34:38.50#ibcon#read 5, iclass 35, count 0 2006.218.07:34:38.50#ibcon#about to read 6, iclass 35, count 0 2006.218.07:34:38.50#ibcon#read 6, iclass 35, count 0 2006.218.07:34:38.50#ibcon#end of sib2, iclass 35, count 0 2006.218.07:34:38.50#ibcon#*mode == 0, iclass 35, count 0 2006.218.07:34:38.50#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.218.07:34:38.50#ibcon#[25=USB\r\n] 2006.218.07:34:38.50#ibcon#*before write, iclass 35, count 0 2006.218.07:34:38.50#ibcon#enter sib2, iclass 35, count 0 2006.218.07:34:38.50#ibcon#flushed, iclass 35, count 0 2006.218.07:34:38.50#ibcon#about to write, iclass 35, count 0 2006.218.07:34:38.50#ibcon#wrote, iclass 35, count 0 2006.218.07:34:38.50#ibcon#about to read 3, iclass 35, count 0 2006.218.07:34:38.53#ibcon#read 3, iclass 35, count 0 2006.218.07:34:38.53#ibcon#about to read 4, iclass 35, count 0 2006.218.07:34:38.53#ibcon#read 4, iclass 35, count 0 2006.218.07:34:38.53#ibcon#about to read 5, iclass 35, count 0 2006.218.07:34:38.53#ibcon#read 5, iclass 35, count 0 2006.218.07:34:38.53#ibcon#about to read 6, iclass 35, count 0 2006.218.07:34:38.53#ibcon#read 6, iclass 35, count 0 2006.218.07:34:38.53#ibcon#end of sib2, iclass 35, count 0 2006.218.07:34:38.53#ibcon#*after write, iclass 35, count 0 2006.218.07:34:38.53#ibcon#*before return 0, iclass 35, count 0 2006.218.07:34:38.53#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.218.07:34:38.53#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.218.07:34:38.53#ibcon#about to clear, iclass 35 cls_cnt 0 2006.218.07:34:38.53#ibcon#cleared, iclass 35 cls_cnt 0 2006.218.07:34:38.53$vc4f8/valo=3,672.99 2006.218.07:34:38.53#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.218.07:34:38.53#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.218.07:34:38.53#ibcon#ireg 17 cls_cnt 0 2006.218.07:34:38.53#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.218.07:34:38.53#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.218.07:34:38.53#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.218.07:34:38.53#ibcon#enter wrdev, iclass 37, count 0 2006.218.07:34:38.53#ibcon#first serial, iclass 37, count 0 2006.218.07:34:38.53#ibcon#enter sib2, iclass 37, count 0 2006.218.07:34:38.53#ibcon#flushed, iclass 37, count 0 2006.218.07:34:38.53#ibcon#about to write, iclass 37, count 0 2006.218.07:34:38.53#ibcon#wrote, iclass 37, count 0 2006.218.07:34:38.53#ibcon#about to read 3, iclass 37, count 0 2006.218.07:34:38.56#ibcon#read 3, iclass 37, count 0 2006.218.07:34:38.56#ibcon#about to read 4, iclass 37, count 0 2006.218.07:34:38.56#ibcon#read 4, iclass 37, count 0 2006.218.07:34:38.56#ibcon#about to read 5, iclass 37, count 0 2006.218.07:34:38.56#ibcon#read 5, iclass 37, count 0 2006.218.07:34:38.56#ibcon#about to read 6, iclass 37, count 0 2006.218.07:34:38.56#ibcon#read 6, iclass 37, count 0 2006.218.07:34:38.56#ibcon#end of sib2, iclass 37, count 0 2006.218.07:34:38.56#ibcon#*mode == 0, iclass 37, count 0 2006.218.07:34:38.56#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.218.07:34:38.56#ibcon#[26=FRQ=03,672.99\r\n] 2006.218.07:34:38.56#ibcon#*before write, iclass 37, count 0 2006.218.07:34:38.56#ibcon#enter sib2, iclass 37, count 0 2006.218.07:34:38.56#ibcon#flushed, iclass 37, count 0 2006.218.07:34:38.56#ibcon#about to write, iclass 37, count 0 2006.218.07:34:38.56#ibcon#wrote, iclass 37, count 0 2006.218.07:34:38.56#ibcon#about to read 3, iclass 37, count 0 2006.218.07:34:38.60#ibcon#read 3, iclass 37, count 0 2006.218.07:34:38.60#ibcon#about to read 4, iclass 37, count 0 2006.218.07:34:38.60#ibcon#read 4, iclass 37, count 0 2006.218.07:34:38.60#ibcon#about to read 5, iclass 37, count 0 2006.218.07:34:38.60#ibcon#read 5, iclass 37, count 0 2006.218.07:34:38.60#ibcon#about to read 6, iclass 37, count 0 2006.218.07:34:38.60#ibcon#read 6, iclass 37, count 0 2006.218.07:34:38.60#ibcon#end of sib2, iclass 37, count 0 2006.218.07:34:38.60#ibcon#*after write, iclass 37, count 0 2006.218.07:34:38.60#ibcon#*before return 0, iclass 37, count 0 2006.218.07:34:38.60#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.218.07:34:38.60#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.218.07:34:38.60#ibcon#about to clear, iclass 37 cls_cnt 0 2006.218.07:34:38.60#ibcon#cleared, iclass 37 cls_cnt 0 2006.218.07:34:38.60$vc4f8/va=3,4 2006.218.07:34:38.60#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.218.07:34:38.60#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.218.07:34:38.60#ibcon#ireg 11 cls_cnt 2 2006.218.07:34:38.60#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.218.07:34:38.65#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.218.07:34:38.65#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.218.07:34:38.65#ibcon#enter wrdev, iclass 39, count 2 2006.218.07:34:38.65#ibcon#first serial, iclass 39, count 2 2006.218.07:34:38.65#ibcon#enter sib2, iclass 39, count 2 2006.218.07:34:38.65#ibcon#flushed, iclass 39, count 2 2006.218.07:34:38.65#ibcon#about to write, iclass 39, count 2 2006.218.07:34:38.65#ibcon#wrote, iclass 39, count 2 2006.218.07:34:38.65#ibcon#about to read 3, iclass 39, count 2 2006.218.07:34:38.67#ibcon#read 3, iclass 39, count 2 2006.218.07:34:38.67#ibcon#about to read 4, iclass 39, count 2 2006.218.07:34:38.67#ibcon#read 4, iclass 39, count 2 2006.218.07:34:38.67#ibcon#about to read 5, iclass 39, count 2 2006.218.07:34:38.67#ibcon#read 5, iclass 39, count 2 2006.218.07:34:38.67#ibcon#about to read 6, iclass 39, count 2 2006.218.07:34:38.67#ibcon#read 6, iclass 39, count 2 2006.218.07:34:38.67#ibcon#end of sib2, iclass 39, count 2 2006.218.07:34:38.67#ibcon#*mode == 0, iclass 39, count 2 2006.218.07:34:38.67#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.218.07:34:38.67#ibcon#[25=AT03-04\r\n] 2006.218.07:34:38.67#ibcon#*before write, iclass 39, count 2 2006.218.07:34:38.67#ibcon#enter sib2, iclass 39, count 2 2006.218.07:34:38.67#ibcon#flushed, iclass 39, count 2 2006.218.07:34:38.67#ibcon#about to write, iclass 39, count 2 2006.218.07:34:38.67#ibcon#wrote, iclass 39, count 2 2006.218.07:34:38.67#ibcon#about to read 3, iclass 39, count 2 2006.218.07:34:38.70#ibcon#read 3, iclass 39, count 2 2006.218.07:34:38.70#ibcon#about to read 4, iclass 39, count 2 2006.218.07:34:38.70#ibcon#read 4, iclass 39, count 2 2006.218.07:34:38.70#ibcon#about to read 5, iclass 39, count 2 2006.218.07:34:38.70#ibcon#read 5, iclass 39, count 2 2006.218.07:34:38.70#ibcon#about to read 6, iclass 39, count 2 2006.218.07:34:38.70#ibcon#read 6, iclass 39, count 2 2006.218.07:34:38.70#ibcon#end of sib2, iclass 39, count 2 2006.218.07:34:38.70#ibcon#*after write, iclass 39, count 2 2006.218.07:34:38.70#ibcon#*before return 0, iclass 39, count 2 2006.218.07:34:38.70#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.218.07:34:38.70#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.218.07:34:38.70#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.218.07:34:38.70#ibcon#ireg 7 cls_cnt 0 2006.218.07:34:38.70#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.218.07:34:38.82#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.218.07:34:38.82#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.218.07:34:38.82#ibcon#enter wrdev, iclass 39, count 0 2006.218.07:34:38.82#ibcon#first serial, iclass 39, count 0 2006.218.07:34:38.82#ibcon#enter sib2, iclass 39, count 0 2006.218.07:34:38.82#ibcon#flushed, iclass 39, count 0 2006.218.07:34:38.82#ibcon#about to write, iclass 39, count 0 2006.218.07:34:38.82#ibcon#wrote, iclass 39, count 0 2006.218.07:34:38.82#ibcon#about to read 3, iclass 39, count 0 2006.218.07:34:38.84#ibcon#read 3, iclass 39, count 0 2006.218.07:34:38.84#ibcon#about to read 4, iclass 39, count 0 2006.218.07:34:38.84#ibcon#read 4, iclass 39, count 0 2006.218.07:34:38.84#ibcon#about to read 5, iclass 39, count 0 2006.218.07:34:38.84#ibcon#read 5, iclass 39, count 0 2006.218.07:34:38.84#ibcon#about to read 6, iclass 39, count 0 2006.218.07:34:38.84#ibcon#read 6, iclass 39, count 0 2006.218.07:34:38.84#ibcon#end of sib2, iclass 39, count 0 2006.218.07:34:38.84#ibcon#*mode == 0, iclass 39, count 0 2006.218.07:34:38.84#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.218.07:34:38.84#ibcon#[25=USB\r\n] 2006.218.07:34:38.84#ibcon#*before write, iclass 39, count 0 2006.218.07:34:38.84#ibcon#enter sib2, iclass 39, count 0 2006.218.07:34:38.84#ibcon#flushed, iclass 39, count 0 2006.218.07:34:38.84#ibcon#about to write, iclass 39, count 0 2006.218.07:34:38.84#ibcon#wrote, iclass 39, count 0 2006.218.07:34:38.84#ibcon#about to read 3, iclass 39, count 0 2006.218.07:34:38.87#ibcon#read 3, iclass 39, count 0 2006.218.07:34:38.87#ibcon#about to read 4, iclass 39, count 0 2006.218.07:34:38.87#ibcon#read 4, iclass 39, count 0 2006.218.07:34:38.87#ibcon#about to read 5, iclass 39, count 0 2006.218.07:34:38.87#ibcon#read 5, iclass 39, count 0 2006.218.07:34:38.87#ibcon#about to read 6, iclass 39, count 0 2006.218.07:34:38.87#ibcon#read 6, iclass 39, count 0 2006.218.07:34:38.87#ibcon#end of sib2, iclass 39, count 0 2006.218.07:34:38.87#ibcon#*after write, iclass 39, count 0 2006.218.07:34:38.87#ibcon#*before return 0, iclass 39, count 0 2006.218.07:34:38.87#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.218.07:34:38.87#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.218.07:34:38.87#ibcon#about to clear, iclass 39 cls_cnt 0 2006.218.07:34:38.87#ibcon#cleared, iclass 39 cls_cnt 0 2006.218.07:34:38.87$vc4f8/valo=4,832.99 2006.218.07:34:38.87#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.218.07:34:38.87#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.218.07:34:38.87#ibcon#ireg 17 cls_cnt 0 2006.218.07:34:38.87#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.218.07:34:38.87#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.218.07:34:38.87#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.218.07:34:38.87#ibcon#enter wrdev, iclass 3, count 0 2006.218.07:34:38.87#ibcon#first serial, iclass 3, count 0 2006.218.07:34:38.87#ibcon#enter sib2, iclass 3, count 0 2006.218.07:34:38.87#ibcon#flushed, iclass 3, count 0 2006.218.07:34:38.87#ibcon#about to write, iclass 3, count 0 2006.218.07:34:38.87#ibcon#wrote, iclass 3, count 0 2006.218.07:34:38.87#ibcon#about to read 3, iclass 3, count 0 2006.218.07:34:38.90#ibcon#read 3, iclass 3, count 0 2006.218.07:34:38.90#ibcon#about to read 4, iclass 3, count 0 2006.218.07:34:38.90#ibcon#read 4, iclass 3, count 0 2006.218.07:34:38.90#ibcon#about to read 5, iclass 3, count 0 2006.218.07:34:38.90#ibcon#read 5, iclass 3, count 0 2006.218.07:34:38.90#ibcon#about to read 6, iclass 3, count 0 2006.218.07:34:38.90#ibcon#read 6, iclass 3, count 0 2006.218.07:34:38.90#ibcon#end of sib2, iclass 3, count 0 2006.218.07:34:38.90#ibcon#*mode == 0, iclass 3, count 0 2006.218.07:34:38.90#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.218.07:34:38.90#ibcon#[26=FRQ=04,832.99\r\n] 2006.218.07:34:38.90#ibcon#*before write, iclass 3, count 0 2006.218.07:34:38.90#ibcon#enter sib2, iclass 3, count 0 2006.218.07:34:38.90#ibcon#flushed, iclass 3, count 0 2006.218.07:34:38.90#ibcon#about to write, iclass 3, count 0 2006.218.07:34:38.90#ibcon#wrote, iclass 3, count 0 2006.218.07:34:38.90#ibcon#about to read 3, iclass 3, count 0 2006.218.07:34:38.94#ibcon#read 3, iclass 3, count 0 2006.218.07:34:38.94#ibcon#about to read 4, iclass 3, count 0 2006.218.07:34:38.94#ibcon#read 4, iclass 3, count 0 2006.218.07:34:38.94#ibcon#about to read 5, iclass 3, count 0 2006.218.07:34:38.94#ibcon#read 5, iclass 3, count 0 2006.218.07:34:38.94#ibcon#about to read 6, iclass 3, count 0 2006.218.07:34:38.94#ibcon#read 6, iclass 3, count 0 2006.218.07:34:38.94#ibcon#end of sib2, iclass 3, count 0 2006.218.07:34:38.94#ibcon#*after write, iclass 3, count 0 2006.218.07:34:38.94#ibcon#*before return 0, iclass 3, count 0 2006.218.07:34:38.94#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.218.07:34:38.94#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.218.07:34:38.94#ibcon#about to clear, iclass 3 cls_cnt 0 2006.218.07:34:38.94#ibcon#cleared, iclass 3 cls_cnt 0 2006.218.07:34:38.94$vc4f8/va=4,4 2006.218.07:34:38.94#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.218.07:34:38.94#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.218.07:34:38.94#ibcon#ireg 11 cls_cnt 2 2006.218.07:34:38.94#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.218.07:34:38.99#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.218.07:34:38.99#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.218.07:34:38.99#ibcon#enter wrdev, iclass 5, count 2 2006.218.07:34:38.99#ibcon#first serial, iclass 5, count 2 2006.218.07:34:38.99#ibcon#enter sib2, iclass 5, count 2 2006.218.07:34:38.99#ibcon#flushed, iclass 5, count 2 2006.218.07:34:38.99#ibcon#about to write, iclass 5, count 2 2006.218.07:34:38.99#ibcon#wrote, iclass 5, count 2 2006.218.07:34:38.99#ibcon#about to read 3, iclass 5, count 2 2006.218.07:34:39.01#ibcon#read 3, iclass 5, count 2 2006.218.07:34:39.01#ibcon#about to read 4, iclass 5, count 2 2006.218.07:34:39.01#ibcon#read 4, iclass 5, count 2 2006.218.07:34:39.01#ibcon#about to read 5, iclass 5, count 2 2006.218.07:34:39.01#ibcon#read 5, iclass 5, count 2 2006.218.07:34:39.01#ibcon#about to read 6, iclass 5, count 2 2006.218.07:34:39.01#ibcon#read 6, iclass 5, count 2 2006.218.07:34:39.01#ibcon#end of sib2, iclass 5, count 2 2006.218.07:34:39.01#ibcon#*mode == 0, iclass 5, count 2 2006.218.07:34:39.01#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.218.07:34:39.01#ibcon#[25=AT04-04\r\n] 2006.218.07:34:39.01#ibcon#*before write, iclass 5, count 2 2006.218.07:34:39.01#ibcon#enter sib2, iclass 5, count 2 2006.218.07:34:39.01#ibcon#flushed, iclass 5, count 2 2006.218.07:34:39.01#ibcon#about to write, iclass 5, count 2 2006.218.07:34:39.01#ibcon#wrote, iclass 5, count 2 2006.218.07:34:39.01#ibcon#about to read 3, iclass 5, count 2 2006.218.07:34:39.04#ibcon#read 3, iclass 5, count 2 2006.218.07:34:39.04#ibcon#about to read 4, iclass 5, count 2 2006.218.07:34:39.04#ibcon#read 4, iclass 5, count 2 2006.218.07:34:39.04#ibcon#about to read 5, iclass 5, count 2 2006.218.07:34:39.04#ibcon#read 5, iclass 5, count 2 2006.218.07:34:39.04#ibcon#about to read 6, iclass 5, count 2 2006.218.07:34:39.04#ibcon#read 6, iclass 5, count 2 2006.218.07:34:39.04#ibcon#end of sib2, iclass 5, count 2 2006.218.07:34:39.04#ibcon#*after write, iclass 5, count 2 2006.218.07:34:39.04#ibcon#*before return 0, iclass 5, count 2 2006.218.07:34:39.04#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.218.07:34:39.04#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.218.07:34:39.04#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.218.07:34:39.04#ibcon#ireg 7 cls_cnt 0 2006.218.07:34:39.04#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.218.07:34:39.16#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.218.07:34:39.16#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.218.07:34:39.16#ibcon#enter wrdev, iclass 5, count 0 2006.218.07:34:39.16#ibcon#first serial, iclass 5, count 0 2006.218.07:34:39.16#ibcon#enter sib2, iclass 5, count 0 2006.218.07:34:39.16#ibcon#flushed, iclass 5, count 0 2006.218.07:34:39.16#ibcon#about to write, iclass 5, count 0 2006.218.07:34:39.16#ibcon#wrote, iclass 5, count 0 2006.218.07:34:39.16#ibcon#about to read 3, iclass 5, count 0 2006.218.07:34:39.18#ibcon#read 3, iclass 5, count 0 2006.218.07:34:39.18#ibcon#about to read 4, iclass 5, count 0 2006.218.07:34:39.18#ibcon#read 4, iclass 5, count 0 2006.218.07:34:39.18#ibcon#about to read 5, iclass 5, count 0 2006.218.07:34:39.18#ibcon#read 5, iclass 5, count 0 2006.218.07:34:39.18#ibcon#about to read 6, iclass 5, count 0 2006.218.07:34:39.18#ibcon#read 6, iclass 5, count 0 2006.218.07:34:39.18#ibcon#end of sib2, iclass 5, count 0 2006.218.07:34:39.18#ibcon#*mode == 0, iclass 5, count 0 2006.218.07:34:39.18#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.218.07:34:39.18#ibcon#[25=USB\r\n] 2006.218.07:34:39.18#ibcon#*before write, iclass 5, count 0 2006.218.07:34:39.18#ibcon#enter sib2, iclass 5, count 0 2006.218.07:34:39.18#ibcon#flushed, iclass 5, count 0 2006.218.07:34:39.18#ibcon#about to write, iclass 5, count 0 2006.218.07:34:39.18#ibcon#wrote, iclass 5, count 0 2006.218.07:34:39.18#ibcon#about to read 3, iclass 5, count 0 2006.218.07:34:39.21#ibcon#read 3, iclass 5, count 0 2006.218.07:34:39.21#ibcon#about to read 4, iclass 5, count 0 2006.218.07:34:39.21#ibcon#read 4, iclass 5, count 0 2006.218.07:34:39.21#ibcon#about to read 5, iclass 5, count 0 2006.218.07:34:39.21#ibcon#read 5, iclass 5, count 0 2006.218.07:34:39.21#ibcon#about to read 6, iclass 5, count 0 2006.218.07:34:39.21#ibcon#read 6, iclass 5, count 0 2006.218.07:34:39.21#ibcon#end of sib2, iclass 5, count 0 2006.218.07:34:39.21#ibcon#*after write, iclass 5, count 0 2006.218.07:34:39.21#ibcon#*before return 0, iclass 5, count 0 2006.218.07:34:39.21#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.218.07:34:39.21#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.218.07:34:39.21#ibcon#about to clear, iclass 5 cls_cnt 0 2006.218.07:34:39.21#ibcon#cleared, iclass 5 cls_cnt 0 2006.218.07:34:39.21$vc4f8/valo=5,652.99 2006.218.07:34:39.21#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.218.07:34:39.21#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.218.07:34:39.21#ibcon#ireg 17 cls_cnt 0 2006.218.07:34:39.21#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.218.07:34:39.21#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.218.07:34:39.21#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.218.07:34:39.21#ibcon#enter wrdev, iclass 7, count 0 2006.218.07:34:39.21#ibcon#first serial, iclass 7, count 0 2006.218.07:34:39.21#ibcon#enter sib2, iclass 7, count 0 2006.218.07:34:39.21#ibcon#flushed, iclass 7, count 0 2006.218.07:34:39.21#ibcon#about to write, iclass 7, count 0 2006.218.07:34:39.21#ibcon#wrote, iclass 7, count 0 2006.218.07:34:39.21#ibcon#about to read 3, iclass 7, count 0 2006.218.07:34:39.23#ibcon#read 3, iclass 7, count 0 2006.218.07:34:39.23#ibcon#about to read 4, iclass 7, count 0 2006.218.07:34:39.23#ibcon#read 4, iclass 7, count 0 2006.218.07:34:39.23#ibcon#about to read 5, iclass 7, count 0 2006.218.07:34:39.23#ibcon#read 5, iclass 7, count 0 2006.218.07:34:39.23#ibcon#about to read 6, iclass 7, count 0 2006.218.07:34:39.23#ibcon#read 6, iclass 7, count 0 2006.218.07:34:39.23#ibcon#end of sib2, iclass 7, count 0 2006.218.07:34:39.23#ibcon#*mode == 0, iclass 7, count 0 2006.218.07:34:39.23#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.218.07:34:39.23#ibcon#[26=FRQ=05,652.99\r\n] 2006.218.07:34:39.23#ibcon#*before write, iclass 7, count 0 2006.218.07:34:39.23#ibcon#enter sib2, iclass 7, count 0 2006.218.07:34:39.23#ibcon#flushed, iclass 7, count 0 2006.218.07:34:39.23#ibcon#about to write, iclass 7, count 0 2006.218.07:34:39.23#ibcon#wrote, iclass 7, count 0 2006.218.07:34:39.23#ibcon#about to read 3, iclass 7, count 0 2006.218.07:34:39.27#ibcon#read 3, iclass 7, count 0 2006.218.07:34:39.27#ibcon#about to read 4, iclass 7, count 0 2006.218.07:34:39.27#ibcon#read 4, iclass 7, count 0 2006.218.07:34:39.27#ibcon#about to read 5, iclass 7, count 0 2006.218.07:34:39.27#ibcon#read 5, iclass 7, count 0 2006.218.07:34:39.27#ibcon#about to read 6, iclass 7, count 0 2006.218.07:34:39.27#ibcon#read 6, iclass 7, count 0 2006.218.07:34:39.27#ibcon#end of sib2, iclass 7, count 0 2006.218.07:34:39.27#ibcon#*after write, iclass 7, count 0 2006.218.07:34:39.27#ibcon#*before return 0, iclass 7, count 0 2006.218.07:34:39.27#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.218.07:34:39.27#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.218.07:34:39.27#ibcon#about to clear, iclass 7 cls_cnt 0 2006.218.07:34:39.27#ibcon#cleared, iclass 7 cls_cnt 0 2006.218.07:34:39.27$vc4f8/va=5,7 2006.218.07:34:39.27#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.218.07:34:39.27#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.218.07:34:39.27#ibcon#ireg 11 cls_cnt 2 2006.218.07:34:39.27#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.218.07:34:39.33#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.218.07:34:39.33#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.218.07:34:39.33#ibcon#enter wrdev, iclass 11, count 2 2006.218.07:34:39.33#ibcon#first serial, iclass 11, count 2 2006.218.07:34:39.33#ibcon#enter sib2, iclass 11, count 2 2006.218.07:34:39.33#ibcon#flushed, iclass 11, count 2 2006.218.07:34:39.33#ibcon#about to write, iclass 11, count 2 2006.218.07:34:39.33#ibcon#wrote, iclass 11, count 2 2006.218.07:34:39.33#ibcon#about to read 3, iclass 11, count 2 2006.218.07:34:39.35#ibcon#read 3, iclass 11, count 2 2006.218.07:34:39.35#ibcon#about to read 4, iclass 11, count 2 2006.218.07:34:39.35#ibcon#read 4, iclass 11, count 2 2006.218.07:34:39.35#ibcon#about to read 5, iclass 11, count 2 2006.218.07:34:39.35#ibcon#read 5, iclass 11, count 2 2006.218.07:34:39.35#ibcon#about to read 6, iclass 11, count 2 2006.218.07:34:39.35#ibcon#read 6, iclass 11, count 2 2006.218.07:34:39.35#ibcon#end of sib2, iclass 11, count 2 2006.218.07:34:39.35#ibcon#*mode == 0, iclass 11, count 2 2006.218.07:34:39.35#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.218.07:34:39.35#ibcon#[25=AT05-07\r\n] 2006.218.07:34:39.35#ibcon#*before write, iclass 11, count 2 2006.218.07:34:39.35#ibcon#enter sib2, iclass 11, count 2 2006.218.07:34:39.35#ibcon#flushed, iclass 11, count 2 2006.218.07:34:39.35#ibcon#about to write, iclass 11, count 2 2006.218.07:34:39.35#ibcon#wrote, iclass 11, count 2 2006.218.07:34:39.35#ibcon#about to read 3, iclass 11, count 2 2006.218.07:34:39.38#ibcon#read 3, iclass 11, count 2 2006.218.07:34:39.38#ibcon#about to read 4, iclass 11, count 2 2006.218.07:34:39.38#ibcon#read 4, iclass 11, count 2 2006.218.07:34:39.38#ibcon#about to read 5, iclass 11, count 2 2006.218.07:34:39.38#ibcon#read 5, iclass 11, count 2 2006.218.07:34:39.38#ibcon#about to read 6, iclass 11, count 2 2006.218.07:34:39.38#ibcon#read 6, iclass 11, count 2 2006.218.07:34:39.38#ibcon#end of sib2, iclass 11, count 2 2006.218.07:34:39.38#ibcon#*after write, iclass 11, count 2 2006.218.07:34:39.38#ibcon#*before return 0, iclass 11, count 2 2006.218.07:34:39.38#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.218.07:34:39.38#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.218.07:34:39.38#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.218.07:34:39.38#ibcon#ireg 7 cls_cnt 0 2006.218.07:34:39.38#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.218.07:34:39.50#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.218.07:34:39.50#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.218.07:34:39.50#ibcon#enter wrdev, iclass 11, count 0 2006.218.07:34:39.50#ibcon#first serial, iclass 11, count 0 2006.218.07:34:39.50#ibcon#enter sib2, iclass 11, count 0 2006.218.07:34:39.50#ibcon#flushed, iclass 11, count 0 2006.218.07:34:39.50#ibcon#about to write, iclass 11, count 0 2006.218.07:34:39.50#ibcon#wrote, iclass 11, count 0 2006.218.07:34:39.50#ibcon#about to read 3, iclass 11, count 0 2006.218.07:34:39.52#ibcon#read 3, iclass 11, count 0 2006.218.07:34:39.52#ibcon#about to read 4, iclass 11, count 0 2006.218.07:34:39.52#ibcon#read 4, iclass 11, count 0 2006.218.07:34:39.52#ibcon#about to read 5, iclass 11, count 0 2006.218.07:34:39.52#ibcon#read 5, iclass 11, count 0 2006.218.07:34:39.52#ibcon#about to read 6, iclass 11, count 0 2006.218.07:34:39.52#ibcon#read 6, iclass 11, count 0 2006.218.07:34:39.52#ibcon#end of sib2, iclass 11, count 0 2006.218.07:34:39.52#ibcon#*mode == 0, iclass 11, count 0 2006.218.07:34:39.52#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.218.07:34:39.52#ibcon#[25=USB\r\n] 2006.218.07:34:39.52#ibcon#*before write, iclass 11, count 0 2006.218.07:34:39.52#ibcon#enter sib2, iclass 11, count 0 2006.218.07:34:39.52#ibcon#flushed, iclass 11, count 0 2006.218.07:34:39.52#ibcon#about to write, iclass 11, count 0 2006.218.07:34:39.52#ibcon#wrote, iclass 11, count 0 2006.218.07:34:39.52#ibcon#about to read 3, iclass 11, count 0 2006.218.07:34:39.55#ibcon#read 3, iclass 11, count 0 2006.218.07:34:39.55#ibcon#about to read 4, iclass 11, count 0 2006.218.07:34:39.55#ibcon#read 4, iclass 11, count 0 2006.218.07:34:39.55#ibcon#about to read 5, iclass 11, count 0 2006.218.07:34:39.55#ibcon#read 5, iclass 11, count 0 2006.218.07:34:39.55#ibcon#about to read 6, iclass 11, count 0 2006.218.07:34:39.55#ibcon#read 6, iclass 11, count 0 2006.218.07:34:39.55#ibcon#end of sib2, iclass 11, count 0 2006.218.07:34:39.55#ibcon#*after write, iclass 11, count 0 2006.218.07:34:39.55#ibcon#*before return 0, iclass 11, count 0 2006.218.07:34:39.55#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.218.07:34:39.55#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.218.07:34:39.55#ibcon#about to clear, iclass 11 cls_cnt 0 2006.218.07:34:39.55#ibcon#cleared, iclass 11 cls_cnt 0 2006.218.07:34:39.55$vc4f8/valo=6,772.99 2006.218.07:34:39.55#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.218.07:34:39.55#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.218.07:34:39.55#ibcon#ireg 17 cls_cnt 0 2006.218.07:34:39.55#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.218.07:34:39.55#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.218.07:34:39.55#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.218.07:34:39.55#ibcon#enter wrdev, iclass 13, count 0 2006.218.07:34:39.55#ibcon#first serial, iclass 13, count 0 2006.218.07:34:39.55#ibcon#enter sib2, iclass 13, count 0 2006.218.07:34:39.55#ibcon#flushed, iclass 13, count 0 2006.218.07:34:39.55#ibcon#about to write, iclass 13, count 0 2006.218.07:34:39.55#ibcon#wrote, iclass 13, count 0 2006.218.07:34:39.55#ibcon#about to read 3, iclass 13, count 0 2006.218.07:34:39.58#ibcon#read 3, iclass 13, count 0 2006.218.07:34:39.58#ibcon#about to read 4, iclass 13, count 0 2006.218.07:34:39.58#ibcon#read 4, iclass 13, count 0 2006.218.07:34:39.58#ibcon#about to read 5, iclass 13, count 0 2006.218.07:34:39.58#ibcon#read 5, iclass 13, count 0 2006.218.07:34:39.58#ibcon#about to read 6, iclass 13, count 0 2006.218.07:34:39.58#ibcon#read 6, iclass 13, count 0 2006.218.07:34:39.58#ibcon#end of sib2, iclass 13, count 0 2006.218.07:34:39.58#ibcon#*mode == 0, iclass 13, count 0 2006.218.07:34:39.58#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.218.07:34:39.58#ibcon#[26=FRQ=06,772.99\r\n] 2006.218.07:34:39.58#ibcon#*before write, iclass 13, count 0 2006.218.07:34:39.58#ibcon#enter sib2, iclass 13, count 0 2006.218.07:34:39.58#ibcon#flushed, iclass 13, count 0 2006.218.07:34:39.58#ibcon#about to write, iclass 13, count 0 2006.218.07:34:39.58#ibcon#wrote, iclass 13, count 0 2006.218.07:34:39.58#ibcon#about to read 3, iclass 13, count 0 2006.218.07:34:39.62#ibcon#read 3, iclass 13, count 0 2006.218.07:34:39.62#ibcon#about to read 4, iclass 13, count 0 2006.218.07:34:39.62#ibcon#read 4, iclass 13, count 0 2006.218.07:34:39.62#ibcon#about to read 5, iclass 13, count 0 2006.218.07:34:39.62#ibcon#read 5, iclass 13, count 0 2006.218.07:34:39.62#ibcon#about to read 6, iclass 13, count 0 2006.218.07:34:39.62#ibcon#read 6, iclass 13, count 0 2006.218.07:34:39.62#ibcon#end of sib2, iclass 13, count 0 2006.218.07:34:39.62#ibcon#*after write, iclass 13, count 0 2006.218.07:34:39.62#ibcon#*before return 0, iclass 13, count 0 2006.218.07:34:39.62#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.218.07:34:39.62#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.218.07:34:39.62#ibcon#about to clear, iclass 13 cls_cnt 0 2006.218.07:34:39.62#ibcon#cleared, iclass 13 cls_cnt 0 2006.218.07:34:39.62$vc4f8/va=6,6 2006.218.07:34:39.62#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.218.07:34:39.62#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.218.07:34:39.62#ibcon#ireg 11 cls_cnt 2 2006.218.07:34:39.62#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.218.07:34:39.67#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.218.07:34:39.67#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.218.07:34:39.67#ibcon#enter wrdev, iclass 15, count 2 2006.218.07:34:39.67#ibcon#first serial, iclass 15, count 2 2006.218.07:34:39.67#ibcon#enter sib2, iclass 15, count 2 2006.218.07:34:39.67#ibcon#flushed, iclass 15, count 2 2006.218.07:34:39.67#ibcon#about to write, iclass 15, count 2 2006.218.07:34:39.67#ibcon#wrote, iclass 15, count 2 2006.218.07:34:39.67#ibcon#about to read 3, iclass 15, count 2 2006.218.07:34:39.69#ibcon#read 3, iclass 15, count 2 2006.218.07:34:39.69#ibcon#about to read 4, iclass 15, count 2 2006.218.07:34:39.69#ibcon#read 4, iclass 15, count 2 2006.218.07:34:39.69#ibcon#about to read 5, iclass 15, count 2 2006.218.07:34:39.69#ibcon#read 5, iclass 15, count 2 2006.218.07:34:39.69#ibcon#about to read 6, iclass 15, count 2 2006.218.07:34:39.69#ibcon#read 6, iclass 15, count 2 2006.218.07:34:39.69#ibcon#end of sib2, iclass 15, count 2 2006.218.07:34:39.69#ibcon#*mode == 0, iclass 15, count 2 2006.218.07:34:39.69#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.218.07:34:39.69#ibcon#[25=AT06-06\r\n] 2006.218.07:34:39.69#ibcon#*before write, iclass 15, count 2 2006.218.07:34:39.69#ibcon#enter sib2, iclass 15, count 2 2006.218.07:34:39.69#ibcon#flushed, iclass 15, count 2 2006.218.07:34:39.69#ibcon#about to write, iclass 15, count 2 2006.218.07:34:39.69#ibcon#wrote, iclass 15, count 2 2006.218.07:34:39.69#ibcon#about to read 3, iclass 15, count 2 2006.218.07:34:39.72#ibcon#read 3, iclass 15, count 2 2006.218.07:34:39.72#ibcon#about to read 4, iclass 15, count 2 2006.218.07:34:39.72#ibcon#read 4, iclass 15, count 2 2006.218.07:34:39.72#ibcon#about to read 5, iclass 15, count 2 2006.218.07:34:39.72#ibcon#read 5, iclass 15, count 2 2006.218.07:34:39.72#ibcon#about to read 6, iclass 15, count 2 2006.218.07:34:39.72#ibcon#read 6, iclass 15, count 2 2006.218.07:34:39.72#ibcon#end of sib2, iclass 15, count 2 2006.218.07:34:39.72#ibcon#*after write, iclass 15, count 2 2006.218.07:34:39.72#ibcon#*before return 0, iclass 15, count 2 2006.218.07:34:39.72#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.218.07:34:39.72#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.218.07:34:39.72#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.218.07:34:39.72#ibcon#ireg 7 cls_cnt 0 2006.218.07:34:39.72#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.218.07:34:39.84#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.218.07:34:39.84#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.218.07:34:39.84#ibcon#enter wrdev, iclass 15, count 0 2006.218.07:34:39.84#ibcon#first serial, iclass 15, count 0 2006.218.07:34:39.84#ibcon#enter sib2, iclass 15, count 0 2006.218.07:34:39.84#ibcon#flushed, iclass 15, count 0 2006.218.07:34:39.84#ibcon#about to write, iclass 15, count 0 2006.218.07:34:39.84#ibcon#wrote, iclass 15, count 0 2006.218.07:34:39.84#ibcon#about to read 3, iclass 15, count 0 2006.218.07:34:39.86#ibcon#read 3, iclass 15, count 0 2006.218.07:34:39.86#ibcon#about to read 4, iclass 15, count 0 2006.218.07:34:39.86#ibcon#read 4, iclass 15, count 0 2006.218.07:34:39.86#ibcon#about to read 5, iclass 15, count 0 2006.218.07:34:39.86#ibcon#read 5, iclass 15, count 0 2006.218.07:34:39.86#ibcon#about to read 6, iclass 15, count 0 2006.218.07:34:39.86#ibcon#read 6, iclass 15, count 0 2006.218.07:34:39.86#ibcon#end of sib2, iclass 15, count 0 2006.218.07:34:39.86#ibcon#*mode == 0, iclass 15, count 0 2006.218.07:34:39.86#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.218.07:34:39.86#ibcon#[25=USB\r\n] 2006.218.07:34:39.86#ibcon#*before write, iclass 15, count 0 2006.218.07:34:39.86#ibcon#enter sib2, iclass 15, count 0 2006.218.07:34:39.86#ibcon#flushed, iclass 15, count 0 2006.218.07:34:39.86#ibcon#about to write, iclass 15, count 0 2006.218.07:34:39.86#ibcon#wrote, iclass 15, count 0 2006.218.07:34:39.86#ibcon#about to read 3, iclass 15, count 0 2006.218.07:34:39.89#ibcon#read 3, iclass 15, count 0 2006.218.07:34:39.89#ibcon#about to read 4, iclass 15, count 0 2006.218.07:34:39.89#ibcon#read 4, iclass 15, count 0 2006.218.07:34:39.89#ibcon#about to read 5, iclass 15, count 0 2006.218.07:34:39.89#ibcon#read 5, iclass 15, count 0 2006.218.07:34:39.89#ibcon#about to read 6, iclass 15, count 0 2006.218.07:34:39.89#ibcon#read 6, iclass 15, count 0 2006.218.07:34:39.89#ibcon#end of sib2, iclass 15, count 0 2006.218.07:34:39.89#ibcon#*after write, iclass 15, count 0 2006.218.07:34:39.89#ibcon#*before return 0, iclass 15, count 0 2006.218.07:34:39.89#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.218.07:34:39.89#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.218.07:34:39.89#ibcon#about to clear, iclass 15 cls_cnt 0 2006.218.07:34:39.89#ibcon#cleared, iclass 15 cls_cnt 0 2006.218.07:34:39.89$vc4f8/valo=7,832.99 2006.218.07:34:39.89#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.218.07:34:39.89#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.218.07:34:39.89#ibcon#ireg 17 cls_cnt 0 2006.218.07:34:39.89#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.218.07:34:39.89#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.218.07:34:39.89#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.218.07:34:39.89#ibcon#enter wrdev, iclass 17, count 0 2006.218.07:34:39.89#ibcon#first serial, iclass 17, count 0 2006.218.07:34:39.89#ibcon#enter sib2, iclass 17, count 0 2006.218.07:34:39.89#ibcon#flushed, iclass 17, count 0 2006.218.07:34:39.89#ibcon#about to write, iclass 17, count 0 2006.218.07:34:39.89#ibcon#wrote, iclass 17, count 0 2006.218.07:34:39.89#ibcon#about to read 3, iclass 17, count 0 2006.218.07:34:39.91#ibcon#read 3, iclass 17, count 0 2006.218.07:34:39.91#ibcon#about to read 4, iclass 17, count 0 2006.218.07:34:39.91#ibcon#read 4, iclass 17, count 0 2006.218.07:34:39.91#ibcon#about to read 5, iclass 17, count 0 2006.218.07:34:39.91#ibcon#read 5, iclass 17, count 0 2006.218.07:34:39.91#ibcon#about to read 6, iclass 17, count 0 2006.218.07:34:39.91#ibcon#read 6, iclass 17, count 0 2006.218.07:34:39.91#ibcon#end of sib2, iclass 17, count 0 2006.218.07:34:39.91#ibcon#*mode == 0, iclass 17, count 0 2006.218.07:34:39.91#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.218.07:34:39.91#ibcon#[26=FRQ=07,832.99\r\n] 2006.218.07:34:39.91#ibcon#*before write, iclass 17, count 0 2006.218.07:34:39.91#ibcon#enter sib2, iclass 17, count 0 2006.218.07:34:39.91#ibcon#flushed, iclass 17, count 0 2006.218.07:34:39.91#ibcon#about to write, iclass 17, count 0 2006.218.07:34:39.91#ibcon#wrote, iclass 17, count 0 2006.218.07:34:39.91#ibcon#about to read 3, iclass 17, count 0 2006.218.07:34:39.95#ibcon#read 3, iclass 17, count 0 2006.218.07:34:39.95#ibcon#about to read 4, iclass 17, count 0 2006.218.07:34:39.95#ibcon#read 4, iclass 17, count 0 2006.218.07:34:39.95#ibcon#about to read 5, iclass 17, count 0 2006.218.07:34:39.95#ibcon#read 5, iclass 17, count 0 2006.218.07:34:39.95#ibcon#about to read 6, iclass 17, count 0 2006.218.07:34:39.95#ibcon#read 6, iclass 17, count 0 2006.218.07:34:39.95#ibcon#end of sib2, iclass 17, count 0 2006.218.07:34:39.95#ibcon#*after write, iclass 17, count 0 2006.218.07:34:39.95#ibcon#*before return 0, iclass 17, count 0 2006.218.07:34:39.95#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.218.07:34:39.95#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.218.07:34:39.95#ibcon#about to clear, iclass 17 cls_cnt 0 2006.218.07:34:39.95#ibcon#cleared, iclass 17 cls_cnt 0 2006.218.07:34:39.95$vc4f8/va=7,6 2006.218.07:34:39.95#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.218.07:34:39.95#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.218.07:34:39.95#ibcon#ireg 11 cls_cnt 2 2006.218.07:34:39.95#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.218.07:34:40.01#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.218.07:34:40.01#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.218.07:34:40.01#ibcon#enter wrdev, iclass 19, count 2 2006.218.07:34:40.01#ibcon#first serial, iclass 19, count 2 2006.218.07:34:40.01#ibcon#enter sib2, iclass 19, count 2 2006.218.07:34:40.01#ibcon#flushed, iclass 19, count 2 2006.218.07:34:40.01#ibcon#about to write, iclass 19, count 2 2006.218.07:34:40.01#ibcon#wrote, iclass 19, count 2 2006.218.07:34:40.01#ibcon#about to read 3, iclass 19, count 2 2006.218.07:34:40.03#ibcon#read 3, iclass 19, count 2 2006.218.07:34:40.03#ibcon#about to read 4, iclass 19, count 2 2006.218.07:34:40.03#ibcon#read 4, iclass 19, count 2 2006.218.07:34:40.03#ibcon#about to read 5, iclass 19, count 2 2006.218.07:34:40.03#ibcon#read 5, iclass 19, count 2 2006.218.07:34:40.03#ibcon#about to read 6, iclass 19, count 2 2006.218.07:34:40.03#ibcon#read 6, iclass 19, count 2 2006.218.07:34:40.03#ibcon#end of sib2, iclass 19, count 2 2006.218.07:34:40.03#ibcon#*mode == 0, iclass 19, count 2 2006.218.07:34:40.03#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.218.07:34:40.03#ibcon#[25=AT07-06\r\n] 2006.218.07:34:40.03#ibcon#*before write, iclass 19, count 2 2006.218.07:34:40.03#ibcon#enter sib2, iclass 19, count 2 2006.218.07:34:40.03#ibcon#flushed, iclass 19, count 2 2006.218.07:34:40.03#ibcon#about to write, iclass 19, count 2 2006.218.07:34:40.03#ibcon#wrote, iclass 19, count 2 2006.218.07:34:40.03#ibcon#about to read 3, iclass 19, count 2 2006.218.07:34:40.06#ibcon#read 3, iclass 19, count 2 2006.218.07:34:40.06#ibcon#about to read 4, iclass 19, count 2 2006.218.07:34:40.06#ibcon#read 4, iclass 19, count 2 2006.218.07:34:40.06#ibcon#about to read 5, iclass 19, count 2 2006.218.07:34:40.06#ibcon#read 5, iclass 19, count 2 2006.218.07:34:40.06#ibcon#about to read 6, iclass 19, count 2 2006.218.07:34:40.06#ibcon#read 6, iclass 19, count 2 2006.218.07:34:40.06#ibcon#end of sib2, iclass 19, count 2 2006.218.07:34:40.06#ibcon#*after write, iclass 19, count 2 2006.218.07:34:40.06#ibcon#*before return 0, iclass 19, count 2 2006.218.07:34:40.06#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.218.07:34:40.06#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.218.07:34:40.06#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.218.07:34:40.06#ibcon#ireg 7 cls_cnt 0 2006.218.07:34:40.06#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.218.07:34:40.18#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.218.07:34:40.18#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.218.07:34:40.18#ibcon#enter wrdev, iclass 19, count 0 2006.218.07:34:40.18#ibcon#first serial, iclass 19, count 0 2006.218.07:34:40.18#ibcon#enter sib2, iclass 19, count 0 2006.218.07:34:40.18#ibcon#flushed, iclass 19, count 0 2006.218.07:34:40.18#ibcon#about to write, iclass 19, count 0 2006.218.07:34:40.18#ibcon#wrote, iclass 19, count 0 2006.218.07:34:40.18#ibcon#about to read 3, iclass 19, count 0 2006.218.07:34:40.20#ibcon#read 3, iclass 19, count 0 2006.218.07:34:40.20#ibcon#about to read 4, iclass 19, count 0 2006.218.07:34:40.20#ibcon#read 4, iclass 19, count 0 2006.218.07:34:40.20#ibcon#about to read 5, iclass 19, count 0 2006.218.07:34:40.20#ibcon#read 5, iclass 19, count 0 2006.218.07:34:40.20#ibcon#about to read 6, iclass 19, count 0 2006.218.07:34:40.20#ibcon#read 6, iclass 19, count 0 2006.218.07:34:40.20#ibcon#end of sib2, iclass 19, count 0 2006.218.07:34:40.20#ibcon#*mode == 0, iclass 19, count 0 2006.218.07:34:40.20#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.218.07:34:40.20#ibcon#[25=USB\r\n] 2006.218.07:34:40.20#ibcon#*before write, iclass 19, count 0 2006.218.07:34:40.20#ibcon#enter sib2, iclass 19, count 0 2006.218.07:34:40.20#ibcon#flushed, iclass 19, count 0 2006.218.07:34:40.20#ibcon#about to write, iclass 19, count 0 2006.218.07:34:40.20#ibcon#wrote, iclass 19, count 0 2006.218.07:34:40.20#ibcon#about to read 3, iclass 19, count 0 2006.218.07:34:40.23#ibcon#read 3, iclass 19, count 0 2006.218.07:34:40.23#ibcon#about to read 4, iclass 19, count 0 2006.218.07:34:40.23#ibcon#read 4, iclass 19, count 0 2006.218.07:34:40.23#ibcon#about to read 5, iclass 19, count 0 2006.218.07:34:40.23#ibcon#read 5, iclass 19, count 0 2006.218.07:34:40.23#ibcon#about to read 6, iclass 19, count 0 2006.218.07:34:40.23#ibcon#read 6, iclass 19, count 0 2006.218.07:34:40.23#ibcon#end of sib2, iclass 19, count 0 2006.218.07:34:40.23#ibcon#*after write, iclass 19, count 0 2006.218.07:34:40.23#ibcon#*before return 0, iclass 19, count 0 2006.218.07:34:40.23#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.218.07:34:40.23#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.218.07:34:40.23#ibcon#about to clear, iclass 19 cls_cnt 0 2006.218.07:34:40.23#ibcon#cleared, iclass 19 cls_cnt 0 2006.218.07:34:40.23$vc4f8/valo=8,852.99 2006.218.07:34:40.23#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.218.07:34:40.23#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.218.07:34:40.23#ibcon#ireg 17 cls_cnt 0 2006.218.07:34:40.23#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.218.07:34:40.23#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.218.07:34:40.23#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.218.07:34:40.23#ibcon#enter wrdev, iclass 21, count 0 2006.218.07:34:40.23#ibcon#first serial, iclass 21, count 0 2006.218.07:34:40.23#ibcon#enter sib2, iclass 21, count 0 2006.218.07:34:40.23#ibcon#flushed, iclass 21, count 0 2006.218.07:34:40.23#ibcon#about to write, iclass 21, count 0 2006.218.07:34:40.23#ibcon#wrote, iclass 21, count 0 2006.218.07:34:40.23#ibcon#about to read 3, iclass 21, count 0 2006.218.07:34:40.25#ibcon#read 3, iclass 21, count 0 2006.218.07:34:40.25#ibcon#about to read 4, iclass 21, count 0 2006.218.07:34:40.25#ibcon#read 4, iclass 21, count 0 2006.218.07:34:40.25#ibcon#about to read 5, iclass 21, count 0 2006.218.07:34:40.25#ibcon#read 5, iclass 21, count 0 2006.218.07:34:40.25#ibcon#about to read 6, iclass 21, count 0 2006.218.07:34:40.25#ibcon#read 6, iclass 21, count 0 2006.218.07:34:40.25#ibcon#end of sib2, iclass 21, count 0 2006.218.07:34:40.25#ibcon#*mode == 0, iclass 21, count 0 2006.218.07:34:40.25#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.218.07:34:40.25#ibcon#[26=FRQ=08,852.99\r\n] 2006.218.07:34:40.25#ibcon#*before write, iclass 21, count 0 2006.218.07:34:40.25#ibcon#enter sib2, iclass 21, count 0 2006.218.07:34:40.25#ibcon#flushed, iclass 21, count 0 2006.218.07:34:40.25#ibcon#about to write, iclass 21, count 0 2006.218.07:34:40.25#ibcon#wrote, iclass 21, count 0 2006.218.07:34:40.25#ibcon#about to read 3, iclass 21, count 0 2006.218.07:34:40.29#ibcon#read 3, iclass 21, count 0 2006.218.07:34:40.29#ibcon#about to read 4, iclass 21, count 0 2006.218.07:34:40.29#ibcon#read 4, iclass 21, count 0 2006.218.07:34:40.29#ibcon#about to read 5, iclass 21, count 0 2006.218.07:34:40.29#ibcon#read 5, iclass 21, count 0 2006.218.07:34:40.29#ibcon#about to read 6, iclass 21, count 0 2006.218.07:34:40.29#ibcon#read 6, iclass 21, count 0 2006.218.07:34:40.29#ibcon#end of sib2, iclass 21, count 0 2006.218.07:34:40.29#ibcon#*after write, iclass 21, count 0 2006.218.07:34:40.29#ibcon#*before return 0, iclass 21, count 0 2006.218.07:34:40.29#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.218.07:34:40.29#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.218.07:34:40.29#ibcon#about to clear, iclass 21 cls_cnt 0 2006.218.07:34:40.29#ibcon#cleared, iclass 21 cls_cnt 0 2006.218.07:34:40.29$vc4f8/va=8,7 2006.218.07:34:40.29#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.218.07:34:40.29#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.218.07:34:40.29#ibcon#ireg 11 cls_cnt 2 2006.218.07:34:40.29#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.218.07:34:40.35#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.218.07:34:40.35#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.218.07:34:40.35#ibcon#enter wrdev, iclass 23, count 2 2006.218.07:34:40.35#ibcon#first serial, iclass 23, count 2 2006.218.07:34:40.35#ibcon#enter sib2, iclass 23, count 2 2006.218.07:34:40.35#ibcon#flushed, iclass 23, count 2 2006.218.07:34:40.35#ibcon#about to write, iclass 23, count 2 2006.218.07:34:40.35#ibcon#wrote, iclass 23, count 2 2006.218.07:34:40.35#ibcon#about to read 3, iclass 23, count 2 2006.218.07:34:40.37#ibcon#read 3, iclass 23, count 2 2006.218.07:34:40.37#ibcon#about to read 4, iclass 23, count 2 2006.218.07:34:40.37#ibcon#read 4, iclass 23, count 2 2006.218.07:34:40.37#ibcon#about to read 5, iclass 23, count 2 2006.218.07:34:40.37#ibcon#read 5, iclass 23, count 2 2006.218.07:34:40.37#ibcon#about to read 6, iclass 23, count 2 2006.218.07:34:40.37#ibcon#read 6, iclass 23, count 2 2006.218.07:34:40.37#ibcon#end of sib2, iclass 23, count 2 2006.218.07:34:40.37#ibcon#*mode == 0, iclass 23, count 2 2006.218.07:34:40.37#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.218.07:34:40.37#ibcon#[25=AT08-07\r\n] 2006.218.07:34:40.37#ibcon#*before write, iclass 23, count 2 2006.218.07:34:40.37#ibcon#enter sib2, iclass 23, count 2 2006.218.07:34:40.37#ibcon#flushed, iclass 23, count 2 2006.218.07:34:40.37#ibcon#about to write, iclass 23, count 2 2006.218.07:34:40.37#ibcon#wrote, iclass 23, count 2 2006.218.07:34:40.37#ibcon#about to read 3, iclass 23, count 2 2006.218.07:34:40.41#ibcon#read 3, iclass 23, count 2 2006.218.07:34:40.41#ibcon#about to read 4, iclass 23, count 2 2006.218.07:34:40.41#ibcon#read 4, iclass 23, count 2 2006.218.07:34:40.41#ibcon#about to read 5, iclass 23, count 2 2006.218.07:34:40.41#ibcon#read 5, iclass 23, count 2 2006.218.07:34:40.41#ibcon#about to read 6, iclass 23, count 2 2006.218.07:34:40.41#ibcon#read 6, iclass 23, count 2 2006.218.07:34:40.41#ibcon#end of sib2, iclass 23, count 2 2006.218.07:34:40.41#ibcon#*after write, iclass 23, count 2 2006.218.07:34:40.41#ibcon#*before return 0, iclass 23, count 2 2006.218.07:34:40.41#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.218.07:34:40.41#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.218.07:34:40.41#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.218.07:34:40.41#ibcon#ireg 7 cls_cnt 0 2006.218.07:34:40.41#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.218.07:34:40.53#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.218.07:34:40.53#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.218.07:34:40.53#ibcon#enter wrdev, iclass 23, count 0 2006.218.07:34:40.53#ibcon#first serial, iclass 23, count 0 2006.218.07:34:40.53#ibcon#enter sib2, iclass 23, count 0 2006.218.07:34:40.53#ibcon#flushed, iclass 23, count 0 2006.218.07:34:40.53#ibcon#about to write, iclass 23, count 0 2006.218.07:34:40.53#ibcon#wrote, iclass 23, count 0 2006.218.07:34:40.53#ibcon#about to read 3, iclass 23, count 0 2006.218.07:34:40.55#ibcon#read 3, iclass 23, count 0 2006.218.07:34:40.55#ibcon#about to read 4, iclass 23, count 0 2006.218.07:34:40.55#ibcon#read 4, iclass 23, count 0 2006.218.07:34:40.55#ibcon#about to read 5, iclass 23, count 0 2006.218.07:34:40.55#ibcon#read 5, iclass 23, count 0 2006.218.07:34:40.55#ibcon#about to read 6, iclass 23, count 0 2006.218.07:34:40.55#ibcon#read 6, iclass 23, count 0 2006.218.07:34:40.55#ibcon#end of sib2, iclass 23, count 0 2006.218.07:34:40.55#ibcon#*mode == 0, iclass 23, count 0 2006.218.07:34:40.55#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.218.07:34:40.55#ibcon#[25=USB\r\n] 2006.218.07:34:40.55#ibcon#*before write, iclass 23, count 0 2006.218.07:34:40.55#ibcon#enter sib2, iclass 23, count 0 2006.218.07:34:40.55#ibcon#flushed, iclass 23, count 0 2006.218.07:34:40.55#ibcon#about to write, iclass 23, count 0 2006.218.07:34:40.55#ibcon#wrote, iclass 23, count 0 2006.218.07:34:40.55#ibcon#about to read 3, iclass 23, count 0 2006.218.07:34:40.58#ibcon#read 3, iclass 23, count 0 2006.218.07:34:40.58#ibcon#about to read 4, iclass 23, count 0 2006.218.07:34:40.58#ibcon#read 4, iclass 23, count 0 2006.218.07:34:40.58#ibcon#about to read 5, iclass 23, count 0 2006.218.07:34:40.58#ibcon#read 5, iclass 23, count 0 2006.218.07:34:40.58#ibcon#about to read 6, iclass 23, count 0 2006.218.07:34:40.58#ibcon#read 6, iclass 23, count 0 2006.218.07:34:40.58#ibcon#end of sib2, iclass 23, count 0 2006.218.07:34:40.58#ibcon#*after write, iclass 23, count 0 2006.218.07:34:40.58#ibcon#*before return 0, iclass 23, count 0 2006.218.07:34:40.58#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.218.07:34:40.58#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.218.07:34:40.58#ibcon#about to clear, iclass 23 cls_cnt 0 2006.218.07:34:40.58#ibcon#cleared, iclass 23 cls_cnt 0 2006.218.07:34:40.58$vc4f8/vblo=1,632.99 2006.218.07:34:40.58#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.218.07:34:40.58#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.218.07:34:40.58#ibcon#ireg 17 cls_cnt 0 2006.218.07:34:40.58#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.218.07:34:40.58#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.218.07:34:40.58#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.218.07:34:40.58#ibcon#enter wrdev, iclass 25, count 0 2006.218.07:34:40.58#ibcon#first serial, iclass 25, count 0 2006.218.07:34:40.58#ibcon#enter sib2, iclass 25, count 0 2006.218.07:34:40.58#ibcon#flushed, iclass 25, count 0 2006.218.07:34:40.58#ibcon#about to write, iclass 25, count 0 2006.218.07:34:40.58#ibcon#wrote, iclass 25, count 0 2006.218.07:34:40.58#ibcon#about to read 3, iclass 25, count 0 2006.218.07:34:40.60#ibcon#read 3, iclass 25, count 0 2006.218.07:34:40.60#ibcon#about to read 4, iclass 25, count 0 2006.218.07:34:40.60#ibcon#read 4, iclass 25, count 0 2006.218.07:34:40.60#ibcon#about to read 5, iclass 25, count 0 2006.218.07:34:40.60#ibcon#read 5, iclass 25, count 0 2006.218.07:34:40.60#ibcon#about to read 6, iclass 25, count 0 2006.218.07:34:40.60#ibcon#read 6, iclass 25, count 0 2006.218.07:34:40.60#ibcon#end of sib2, iclass 25, count 0 2006.218.07:34:40.60#ibcon#*mode == 0, iclass 25, count 0 2006.218.07:34:40.60#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.218.07:34:40.60#ibcon#[28=FRQ=01,632.99\r\n] 2006.218.07:34:40.60#ibcon#*before write, iclass 25, count 0 2006.218.07:34:40.60#ibcon#enter sib2, iclass 25, count 0 2006.218.07:34:40.60#ibcon#flushed, iclass 25, count 0 2006.218.07:34:40.60#ibcon#about to write, iclass 25, count 0 2006.218.07:34:40.60#ibcon#wrote, iclass 25, count 0 2006.218.07:34:40.60#ibcon#about to read 3, iclass 25, count 0 2006.218.07:34:40.64#ibcon#read 3, iclass 25, count 0 2006.218.07:34:40.64#ibcon#about to read 4, iclass 25, count 0 2006.218.07:34:40.64#ibcon#read 4, iclass 25, count 0 2006.218.07:34:40.64#ibcon#about to read 5, iclass 25, count 0 2006.218.07:34:40.64#ibcon#read 5, iclass 25, count 0 2006.218.07:34:40.64#ibcon#about to read 6, iclass 25, count 0 2006.218.07:34:40.64#ibcon#read 6, iclass 25, count 0 2006.218.07:34:40.64#ibcon#end of sib2, iclass 25, count 0 2006.218.07:34:40.64#ibcon#*after write, iclass 25, count 0 2006.218.07:34:40.64#ibcon#*before return 0, iclass 25, count 0 2006.218.07:34:40.64#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.218.07:34:40.64#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.218.07:34:40.64#ibcon#about to clear, iclass 25 cls_cnt 0 2006.218.07:34:40.64#ibcon#cleared, iclass 25 cls_cnt 0 2006.218.07:34:40.64$vc4f8/vb=1,4 2006.218.07:34:40.64#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.218.07:34:40.64#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.218.07:34:40.64#ibcon#ireg 11 cls_cnt 2 2006.218.07:34:40.64#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.218.07:34:40.64#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.218.07:34:40.64#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.218.07:34:40.64#ibcon#enter wrdev, iclass 27, count 2 2006.218.07:34:40.64#ibcon#first serial, iclass 27, count 2 2006.218.07:34:40.64#ibcon#enter sib2, iclass 27, count 2 2006.218.07:34:40.64#ibcon#flushed, iclass 27, count 2 2006.218.07:34:40.64#ibcon#about to write, iclass 27, count 2 2006.218.07:34:40.64#ibcon#wrote, iclass 27, count 2 2006.218.07:34:40.64#ibcon#about to read 3, iclass 27, count 2 2006.218.07:34:40.66#ibcon#read 3, iclass 27, count 2 2006.218.07:34:40.66#ibcon#about to read 4, iclass 27, count 2 2006.218.07:34:40.66#ibcon#read 4, iclass 27, count 2 2006.218.07:34:40.66#ibcon#about to read 5, iclass 27, count 2 2006.218.07:34:40.66#ibcon#read 5, iclass 27, count 2 2006.218.07:34:40.66#ibcon#about to read 6, iclass 27, count 2 2006.218.07:34:40.66#ibcon#read 6, iclass 27, count 2 2006.218.07:34:40.66#ibcon#end of sib2, iclass 27, count 2 2006.218.07:34:40.66#ibcon#*mode == 0, iclass 27, count 2 2006.218.07:34:40.66#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.218.07:34:40.66#ibcon#[27=AT01-04\r\n] 2006.218.07:34:40.66#ibcon#*before write, iclass 27, count 2 2006.218.07:34:40.66#ibcon#enter sib2, iclass 27, count 2 2006.218.07:34:40.66#ibcon#flushed, iclass 27, count 2 2006.218.07:34:40.66#ibcon#about to write, iclass 27, count 2 2006.218.07:34:40.66#ibcon#wrote, iclass 27, count 2 2006.218.07:34:40.66#ibcon#about to read 3, iclass 27, count 2 2006.218.07:34:40.69#ibcon#read 3, iclass 27, count 2 2006.218.07:34:40.69#ibcon#about to read 4, iclass 27, count 2 2006.218.07:34:40.69#ibcon#read 4, iclass 27, count 2 2006.218.07:34:40.69#ibcon#about to read 5, iclass 27, count 2 2006.218.07:34:40.69#ibcon#read 5, iclass 27, count 2 2006.218.07:34:40.69#ibcon#about to read 6, iclass 27, count 2 2006.218.07:34:40.69#ibcon#read 6, iclass 27, count 2 2006.218.07:34:40.69#ibcon#end of sib2, iclass 27, count 2 2006.218.07:34:40.69#ibcon#*after write, iclass 27, count 2 2006.218.07:34:40.69#ibcon#*before return 0, iclass 27, count 2 2006.218.07:34:40.69#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.218.07:34:40.69#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.218.07:34:40.69#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.218.07:34:40.69#ibcon#ireg 7 cls_cnt 0 2006.218.07:34:40.69#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.218.07:34:40.81#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.218.07:34:40.81#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.218.07:34:40.81#ibcon#enter wrdev, iclass 27, count 0 2006.218.07:34:40.81#ibcon#first serial, iclass 27, count 0 2006.218.07:34:40.81#ibcon#enter sib2, iclass 27, count 0 2006.218.07:34:40.81#ibcon#flushed, iclass 27, count 0 2006.218.07:34:40.81#ibcon#about to write, iclass 27, count 0 2006.218.07:34:40.81#ibcon#wrote, iclass 27, count 0 2006.218.07:34:40.81#ibcon#about to read 3, iclass 27, count 0 2006.218.07:34:40.83#ibcon#read 3, iclass 27, count 0 2006.218.07:34:40.83#ibcon#about to read 4, iclass 27, count 0 2006.218.07:34:40.83#ibcon#read 4, iclass 27, count 0 2006.218.07:34:40.83#ibcon#about to read 5, iclass 27, count 0 2006.218.07:34:40.83#ibcon#read 5, iclass 27, count 0 2006.218.07:34:40.83#ibcon#about to read 6, iclass 27, count 0 2006.218.07:34:40.83#ibcon#read 6, iclass 27, count 0 2006.218.07:34:40.83#ibcon#end of sib2, iclass 27, count 0 2006.218.07:34:40.83#ibcon#*mode == 0, iclass 27, count 0 2006.218.07:34:40.83#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.218.07:34:40.83#ibcon#[27=USB\r\n] 2006.218.07:34:40.83#ibcon#*before write, iclass 27, count 0 2006.218.07:34:40.83#ibcon#enter sib2, iclass 27, count 0 2006.218.07:34:40.83#ibcon#flushed, iclass 27, count 0 2006.218.07:34:40.83#ibcon#about to write, iclass 27, count 0 2006.218.07:34:40.83#ibcon#wrote, iclass 27, count 0 2006.218.07:34:40.83#ibcon#about to read 3, iclass 27, count 0 2006.218.07:34:40.86#ibcon#read 3, iclass 27, count 0 2006.218.07:34:40.86#ibcon#about to read 4, iclass 27, count 0 2006.218.07:34:40.86#ibcon#read 4, iclass 27, count 0 2006.218.07:34:40.86#ibcon#about to read 5, iclass 27, count 0 2006.218.07:34:40.86#ibcon#read 5, iclass 27, count 0 2006.218.07:34:40.86#ibcon#about to read 6, iclass 27, count 0 2006.218.07:34:40.86#ibcon#read 6, iclass 27, count 0 2006.218.07:34:40.86#ibcon#end of sib2, iclass 27, count 0 2006.218.07:34:40.86#ibcon#*after write, iclass 27, count 0 2006.218.07:34:40.86#ibcon#*before return 0, iclass 27, count 0 2006.218.07:34:40.86#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.218.07:34:40.86#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.218.07:34:40.86#ibcon#about to clear, iclass 27 cls_cnt 0 2006.218.07:34:40.86#ibcon#cleared, iclass 27 cls_cnt 0 2006.218.07:34:40.86$vc4f8/vblo=2,640.99 2006.218.07:34:40.86#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.218.07:34:40.86#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.218.07:34:40.86#ibcon#ireg 17 cls_cnt 0 2006.218.07:34:40.86#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.218.07:34:40.86#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.218.07:34:40.86#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.218.07:34:40.86#ibcon#enter wrdev, iclass 29, count 0 2006.218.07:34:40.86#ibcon#first serial, iclass 29, count 0 2006.218.07:34:40.86#ibcon#enter sib2, iclass 29, count 0 2006.218.07:34:40.86#ibcon#flushed, iclass 29, count 0 2006.218.07:34:40.86#ibcon#about to write, iclass 29, count 0 2006.218.07:34:40.86#ibcon#wrote, iclass 29, count 0 2006.218.07:34:40.86#ibcon#about to read 3, iclass 29, count 0 2006.218.07:34:40.88#ibcon#read 3, iclass 29, count 0 2006.218.07:34:40.88#ibcon#about to read 4, iclass 29, count 0 2006.218.07:34:40.88#ibcon#read 4, iclass 29, count 0 2006.218.07:34:40.88#ibcon#about to read 5, iclass 29, count 0 2006.218.07:34:40.88#ibcon#read 5, iclass 29, count 0 2006.218.07:34:40.88#ibcon#about to read 6, iclass 29, count 0 2006.218.07:34:40.88#ibcon#read 6, iclass 29, count 0 2006.218.07:34:40.88#ibcon#end of sib2, iclass 29, count 0 2006.218.07:34:40.88#ibcon#*mode == 0, iclass 29, count 0 2006.218.07:34:40.88#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.218.07:34:40.88#ibcon#[28=FRQ=02,640.99\r\n] 2006.218.07:34:40.88#ibcon#*before write, iclass 29, count 0 2006.218.07:34:40.88#ibcon#enter sib2, iclass 29, count 0 2006.218.07:34:40.88#ibcon#flushed, iclass 29, count 0 2006.218.07:34:40.88#ibcon#about to write, iclass 29, count 0 2006.218.07:34:40.88#ibcon#wrote, iclass 29, count 0 2006.218.07:34:40.88#ibcon#about to read 3, iclass 29, count 0 2006.218.07:34:40.92#ibcon#read 3, iclass 29, count 0 2006.218.07:34:40.92#ibcon#about to read 4, iclass 29, count 0 2006.218.07:34:40.92#ibcon#read 4, iclass 29, count 0 2006.218.07:34:40.92#ibcon#about to read 5, iclass 29, count 0 2006.218.07:34:40.92#ibcon#read 5, iclass 29, count 0 2006.218.07:34:40.92#ibcon#about to read 6, iclass 29, count 0 2006.218.07:34:40.92#ibcon#read 6, iclass 29, count 0 2006.218.07:34:40.92#ibcon#end of sib2, iclass 29, count 0 2006.218.07:34:40.92#ibcon#*after write, iclass 29, count 0 2006.218.07:34:40.92#ibcon#*before return 0, iclass 29, count 0 2006.218.07:34:40.92#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.218.07:34:40.92#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.218.07:34:40.92#ibcon#about to clear, iclass 29 cls_cnt 0 2006.218.07:34:40.92#ibcon#cleared, iclass 29 cls_cnt 0 2006.218.07:34:40.92$vc4f8/vb=2,4 2006.218.07:34:40.92#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.218.07:34:40.92#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.218.07:34:40.92#ibcon#ireg 11 cls_cnt 2 2006.218.07:34:40.92#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.218.07:34:40.98#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.218.07:34:40.98#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.218.07:34:40.98#ibcon#enter wrdev, iclass 31, count 2 2006.218.07:34:40.98#ibcon#first serial, iclass 31, count 2 2006.218.07:34:40.98#ibcon#enter sib2, iclass 31, count 2 2006.218.07:34:40.98#ibcon#flushed, iclass 31, count 2 2006.218.07:34:40.98#ibcon#about to write, iclass 31, count 2 2006.218.07:34:40.98#ibcon#wrote, iclass 31, count 2 2006.218.07:34:40.98#ibcon#about to read 3, iclass 31, count 2 2006.218.07:34:41.00#ibcon#read 3, iclass 31, count 2 2006.218.07:34:41.00#ibcon#about to read 4, iclass 31, count 2 2006.218.07:34:41.00#ibcon#read 4, iclass 31, count 2 2006.218.07:34:41.00#ibcon#about to read 5, iclass 31, count 2 2006.218.07:34:41.00#ibcon#read 5, iclass 31, count 2 2006.218.07:34:41.00#ibcon#about to read 6, iclass 31, count 2 2006.218.07:34:41.00#ibcon#read 6, iclass 31, count 2 2006.218.07:34:41.00#ibcon#end of sib2, iclass 31, count 2 2006.218.07:34:41.00#ibcon#*mode == 0, iclass 31, count 2 2006.218.07:34:41.00#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.218.07:34:41.00#ibcon#[27=AT02-04\r\n] 2006.218.07:34:41.00#ibcon#*before write, iclass 31, count 2 2006.218.07:34:41.00#ibcon#enter sib2, iclass 31, count 2 2006.218.07:34:41.00#ibcon#flushed, iclass 31, count 2 2006.218.07:34:41.00#ibcon#about to write, iclass 31, count 2 2006.218.07:34:41.00#ibcon#wrote, iclass 31, count 2 2006.218.07:34:41.00#ibcon#about to read 3, iclass 31, count 2 2006.218.07:34:41.03#ibcon#read 3, iclass 31, count 2 2006.218.07:34:41.03#ibcon#about to read 4, iclass 31, count 2 2006.218.07:34:41.03#ibcon#read 4, iclass 31, count 2 2006.218.07:34:41.03#ibcon#about to read 5, iclass 31, count 2 2006.218.07:34:41.03#ibcon#read 5, iclass 31, count 2 2006.218.07:34:41.03#ibcon#about to read 6, iclass 31, count 2 2006.218.07:34:41.03#ibcon#read 6, iclass 31, count 2 2006.218.07:34:41.03#ibcon#end of sib2, iclass 31, count 2 2006.218.07:34:41.03#ibcon#*after write, iclass 31, count 2 2006.218.07:34:41.03#ibcon#*before return 0, iclass 31, count 2 2006.218.07:34:41.03#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.218.07:34:41.03#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.218.07:34:41.03#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.218.07:34:41.03#ibcon#ireg 7 cls_cnt 0 2006.218.07:34:41.03#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.218.07:34:41.15#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.218.07:34:41.15#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.218.07:34:41.15#ibcon#enter wrdev, iclass 31, count 0 2006.218.07:34:41.15#ibcon#first serial, iclass 31, count 0 2006.218.07:34:41.15#ibcon#enter sib2, iclass 31, count 0 2006.218.07:34:41.15#ibcon#flushed, iclass 31, count 0 2006.218.07:34:41.15#ibcon#about to write, iclass 31, count 0 2006.218.07:34:41.15#ibcon#wrote, iclass 31, count 0 2006.218.07:34:41.15#ibcon#about to read 3, iclass 31, count 0 2006.218.07:34:41.17#ibcon#read 3, iclass 31, count 0 2006.218.07:34:41.17#ibcon#about to read 4, iclass 31, count 0 2006.218.07:34:41.17#ibcon#read 4, iclass 31, count 0 2006.218.07:34:41.17#ibcon#about to read 5, iclass 31, count 0 2006.218.07:34:41.17#ibcon#read 5, iclass 31, count 0 2006.218.07:34:41.17#ibcon#about to read 6, iclass 31, count 0 2006.218.07:34:41.17#ibcon#read 6, iclass 31, count 0 2006.218.07:34:41.17#ibcon#end of sib2, iclass 31, count 0 2006.218.07:34:41.17#ibcon#*mode == 0, iclass 31, count 0 2006.218.07:34:41.17#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.218.07:34:41.17#ibcon#[27=USB\r\n] 2006.218.07:34:41.17#ibcon#*before write, iclass 31, count 0 2006.218.07:34:41.17#ibcon#enter sib2, iclass 31, count 0 2006.218.07:34:41.17#ibcon#flushed, iclass 31, count 0 2006.218.07:34:41.17#ibcon#about to write, iclass 31, count 0 2006.218.07:34:41.17#ibcon#wrote, iclass 31, count 0 2006.218.07:34:41.17#ibcon#about to read 3, iclass 31, count 0 2006.218.07:34:41.20#ibcon#read 3, iclass 31, count 0 2006.218.07:34:41.20#ibcon#about to read 4, iclass 31, count 0 2006.218.07:34:41.20#ibcon#read 4, iclass 31, count 0 2006.218.07:34:41.20#ibcon#about to read 5, iclass 31, count 0 2006.218.07:34:41.20#ibcon#read 5, iclass 31, count 0 2006.218.07:34:41.20#ibcon#about to read 6, iclass 31, count 0 2006.218.07:34:41.20#ibcon#read 6, iclass 31, count 0 2006.218.07:34:41.20#ibcon#end of sib2, iclass 31, count 0 2006.218.07:34:41.20#ibcon#*after write, iclass 31, count 0 2006.218.07:34:41.20#ibcon#*before return 0, iclass 31, count 0 2006.218.07:34:41.20#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.218.07:34:41.20#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.218.07:34:41.20#ibcon#about to clear, iclass 31 cls_cnt 0 2006.218.07:34:41.20#ibcon#cleared, iclass 31 cls_cnt 0 2006.218.07:34:41.20$vc4f8/vblo=3,656.99 2006.218.07:34:41.20#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.218.07:34:41.20#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.218.07:34:41.20#ibcon#ireg 17 cls_cnt 0 2006.218.07:34:41.20#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.218.07:34:41.20#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.218.07:34:41.20#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.218.07:34:41.20#ibcon#enter wrdev, iclass 33, count 0 2006.218.07:34:41.20#ibcon#first serial, iclass 33, count 0 2006.218.07:34:41.20#ibcon#enter sib2, iclass 33, count 0 2006.218.07:34:41.20#ibcon#flushed, iclass 33, count 0 2006.218.07:34:41.20#ibcon#about to write, iclass 33, count 0 2006.218.07:34:41.20#ibcon#wrote, iclass 33, count 0 2006.218.07:34:41.20#ibcon#about to read 3, iclass 33, count 0 2006.218.07:34:41.22#ibcon#read 3, iclass 33, count 0 2006.218.07:34:41.22#ibcon#about to read 4, iclass 33, count 0 2006.218.07:34:41.22#ibcon#read 4, iclass 33, count 0 2006.218.07:34:41.22#ibcon#about to read 5, iclass 33, count 0 2006.218.07:34:41.22#ibcon#read 5, iclass 33, count 0 2006.218.07:34:41.22#ibcon#about to read 6, iclass 33, count 0 2006.218.07:34:41.22#ibcon#read 6, iclass 33, count 0 2006.218.07:34:41.22#ibcon#end of sib2, iclass 33, count 0 2006.218.07:34:41.22#ibcon#*mode == 0, iclass 33, count 0 2006.218.07:34:41.22#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.218.07:34:41.22#ibcon#[28=FRQ=03,656.99\r\n] 2006.218.07:34:41.22#ibcon#*before write, iclass 33, count 0 2006.218.07:34:41.22#ibcon#enter sib2, iclass 33, count 0 2006.218.07:34:41.22#ibcon#flushed, iclass 33, count 0 2006.218.07:34:41.22#ibcon#about to write, iclass 33, count 0 2006.218.07:34:41.22#ibcon#wrote, iclass 33, count 0 2006.218.07:34:41.22#ibcon#about to read 3, iclass 33, count 0 2006.218.07:34:41.26#ibcon#read 3, iclass 33, count 0 2006.218.07:34:41.26#ibcon#about to read 4, iclass 33, count 0 2006.218.07:34:41.26#ibcon#read 4, iclass 33, count 0 2006.218.07:34:41.26#ibcon#about to read 5, iclass 33, count 0 2006.218.07:34:41.26#ibcon#read 5, iclass 33, count 0 2006.218.07:34:41.26#ibcon#about to read 6, iclass 33, count 0 2006.218.07:34:41.26#ibcon#read 6, iclass 33, count 0 2006.218.07:34:41.26#ibcon#end of sib2, iclass 33, count 0 2006.218.07:34:41.26#ibcon#*after write, iclass 33, count 0 2006.218.07:34:41.26#ibcon#*before return 0, iclass 33, count 0 2006.218.07:34:41.26#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.218.07:34:41.26#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.218.07:34:41.26#ibcon#about to clear, iclass 33 cls_cnt 0 2006.218.07:34:41.26#ibcon#cleared, iclass 33 cls_cnt 0 2006.218.07:34:41.26$vc4f8/vb=3,4 2006.218.07:34:41.26#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.218.07:34:41.26#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.218.07:34:41.26#ibcon#ireg 11 cls_cnt 2 2006.218.07:34:41.26#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.218.07:34:41.32#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.218.07:34:41.32#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.218.07:34:41.32#ibcon#enter wrdev, iclass 35, count 2 2006.218.07:34:41.32#ibcon#first serial, iclass 35, count 2 2006.218.07:34:41.32#ibcon#enter sib2, iclass 35, count 2 2006.218.07:34:41.32#ibcon#flushed, iclass 35, count 2 2006.218.07:34:41.32#ibcon#about to write, iclass 35, count 2 2006.218.07:34:41.32#ibcon#wrote, iclass 35, count 2 2006.218.07:34:41.32#ibcon#about to read 3, iclass 35, count 2 2006.218.07:34:41.34#ibcon#read 3, iclass 35, count 2 2006.218.07:34:41.34#ibcon#about to read 4, iclass 35, count 2 2006.218.07:34:41.34#ibcon#read 4, iclass 35, count 2 2006.218.07:34:41.34#ibcon#about to read 5, iclass 35, count 2 2006.218.07:34:41.34#ibcon#read 5, iclass 35, count 2 2006.218.07:34:41.34#ibcon#about to read 6, iclass 35, count 2 2006.218.07:34:41.34#ibcon#read 6, iclass 35, count 2 2006.218.07:34:41.34#ibcon#end of sib2, iclass 35, count 2 2006.218.07:34:41.34#ibcon#*mode == 0, iclass 35, count 2 2006.218.07:34:41.34#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.218.07:34:41.34#ibcon#[27=AT03-04\r\n] 2006.218.07:34:41.34#ibcon#*before write, iclass 35, count 2 2006.218.07:34:41.34#ibcon#enter sib2, iclass 35, count 2 2006.218.07:34:41.34#ibcon#flushed, iclass 35, count 2 2006.218.07:34:41.34#ibcon#about to write, iclass 35, count 2 2006.218.07:34:41.34#ibcon#wrote, iclass 35, count 2 2006.218.07:34:41.34#ibcon#about to read 3, iclass 35, count 2 2006.218.07:34:41.37#ibcon#read 3, iclass 35, count 2 2006.218.07:34:41.37#ibcon#about to read 4, iclass 35, count 2 2006.218.07:34:41.37#ibcon#read 4, iclass 35, count 2 2006.218.07:34:41.37#ibcon#about to read 5, iclass 35, count 2 2006.218.07:34:41.37#ibcon#read 5, iclass 35, count 2 2006.218.07:34:41.37#ibcon#about to read 6, iclass 35, count 2 2006.218.07:34:41.37#ibcon#read 6, iclass 35, count 2 2006.218.07:34:41.37#ibcon#end of sib2, iclass 35, count 2 2006.218.07:34:41.37#ibcon#*after write, iclass 35, count 2 2006.218.07:34:41.37#ibcon#*before return 0, iclass 35, count 2 2006.218.07:34:41.37#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.218.07:34:41.37#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.218.07:34:41.37#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.218.07:34:41.37#ibcon#ireg 7 cls_cnt 0 2006.218.07:34:41.37#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.218.07:34:41.49#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.218.07:34:41.49#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.218.07:34:41.49#ibcon#enter wrdev, iclass 35, count 0 2006.218.07:34:41.49#ibcon#first serial, iclass 35, count 0 2006.218.07:34:41.49#ibcon#enter sib2, iclass 35, count 0 2006.218.07:34:41.49#ibcon#flushed, iclass 35, count 0 2006.218.07:34:41.49#ibcon#about to write, iclass 35, count 0 2006.218.07:34:41.49#ibcon#wrote, iclass 35, count 0 2006.218.07:34:41.49#ibcon#about to read 3, iclass 35, count 0 2006.218.07:34:41.51#ibcon#read 3, iclass 35, count 0 2006.218.07:34:41.51#ibcon#about to read 4, iclass 35, count 0 2006.218.07:34:41.51#ibcon#read 4, iclass 35, count 0 2006.218.07:34:41.51#ibcon#about to read 5, iclass 35, count 0 2006.218.07:34:41.51#ibcon#read 5, iclass 35, count 0 2006.218.07:34:41.51#ibcon#about to read 6, iclass 35, count 0 2006.218.07:34:41.51#ibcon#read 6, iclass 35, count 0 2006.218.07:34:41.51#ibcon#end of sib2, iclass 35, count 0 2006.218.07:34:41.51#ibcon#*mode == 0, iclass 35, count 0 2006.218.07:34:41.51#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.218.07:34:41.51#ibcon#[27=USB\r\n] 2006.218.07:34:41.51#ibcon#*before write, iclass 35, count 0 2006.218.07:34:41.51#ibcon#enter sib2, iclass 35, count 0 2006.218.07:34:41.51#ibcon#flushed, iclass 35, count 0 2006.218.07:34:41.51#ibcon#about to write, iclass 35, count 0 2006.218.07:34:41.51#ibcon#wrote, iclass 35, count 0 2006.218.07:34:41.51#ibcon#about to read 3, iclass 35, count 0 2006.218.07:34:41.54#ibcon#read 3, iclass 35, count 0 2006.218.07:34:41.54#ibcon#about to read 4, iclass 35, count 0 2006.218.07:34:41.54#ibcon#read 4, iclass 35, count 0 2006.218.07:34:41.54#ibcon#about to read 5, iclass 35, count 0 2006.218.07:34:41.54#ibcon#read 5, iclass 35, count 0 2006.218.07:34:41.54#ibcon#about to read 6, iclass 35, count 0 2006.218.07:34:41.54#ibcon#read 6, iclass 35, count 0 2006.218.07:34:41.54#ibcon#end of sib2, iclass 35, count 0 2006.218.07:34:41.54#ibcon#*after write, iclass 35, count 0 2006.218.07:34:41.54#ibcon#*before return 0, iclass 35, count 0 2006.218.07:34:41.54#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.218.07:34:41.54#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.218.07:34:41.54#ibcon#about to clear, iclass 35 cls_cnt 0 2006.218.07:34:41.54#ibcon#cleared, iclass 35 cls_cnt 0 2006.218.07:34:41.54$vc4f8/vblo=4,712.99 2006.218.07:34:41.54#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.218.07:34:41.54#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.218.07:34:41.54#ibcon#ireg 17 cls_cnt 0 2006.218.07:34:41.54#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.218.07:34:41.54#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.218.07:34:41.54#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.218.07:34:41.54#ibcon#enter wrdev, iclass 37, count 0 2006.218.07:34:41.54#ibcon#first serial, iclass 37, count 0 2006.218.07:34:41.54#ibcon#enter sib2, iclass 37, count 0 2006.218.07:34:41.54#ibcon#flushed, iclass 37, count 0 2006.218.07:34:41.54#ibcon#about to write, iclass 37, count 0 2006.218.07:34:41.54#ibcon#wrote, iclass 37, count 0 2006.218.07:34:41.54#ibcon#about to read 3, iclass 37, count 0 2006.218.07:34:41.56#ibcon#read 3, iclass 37, count 0 2006.218.07:34:41.56#ibcon#about to read 4, iclass 37, count 0 2006.218.07:34:41.56#ibcon#read 4, iclass 37, count 0 2006.218.07:34:41.56#ibcon#about to read 5, iclass 37, count 0 2006.218.07:34:41.56#ibcon#read 5, iclass 37, count 0 2006.218.07:34:41.56#ibcon#about to read 6, iclass 37, count 0 2006.218.07:34:41.56#ibcon#read 6, iclass 37, count 0 2006.218.07:34:41.56#ibcon#end of sib2, iclass 37, count 0 2006.218.07:34:41.56#ibcon#*mode == 0, iclass 37, count 0 2006.218.07:34:41.56#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.218.07:34:41.56#ibcon#[28=FRQ=04,712.99\r\n] 2006.218.07:34:41.56#ibcon#*before write, iclass 37, count 0 2006.218.07:34:41.56#ibcon#enter sib2, iclass 37, count 0 2006.218.07:34:41.56#ibcon#flushed, iclass 37, count 0 2006.218.07:34:41.56#ibcon#about to write, iclass 37, count 0 2006.218.07:34:41.56#ibcon#wrote, iclass 37, count 0 2006.218.07:34:41.56#ibcon#about to read 3, iclass 37, count 0 2006.218.07:34:41.60#ibcon#read 3, iclass 37, count 0 2006.218.07:34:41.60#ibcon#about to read 4, iclass 37, count 0 2006.218.07:34:41.60#ibcon#read 4, iclass 37, count 0 2006.218.07:34:41.60#ibcon#about to read 5, iclass 37, count 0 2006.218.07:34:41.60#ibcon#read 5, iclass 37, count 0 2006.218.07:34:41.60#ibcon#about to read 6, iclass 37, count 0 2006.218.07:34:41.60#ibcon#read 6, iclass 37, count 0 2006.218.07:34:41.60#ibcon#end of sib2, iclass 37, count 0 2006.218.07:34:41.60#ibcon#*after write, iclass 37, count 0 2006.218.07:34:41.60#ibcon#*before return 0, iclass 37, count 0 2006.218.07:34:41.60#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.218.07:34:41.60#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.218.07:34:41.60#ibcon#about to clear, iclass 37 cls_cnt 0 2006.218.07:34:41.60#ibcon#cleared, iclass 37 cls_cnt 0 2006.218.07:34:41.60$vc4f8/vb=4,4 2006.218.07:34:41.60#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.218.07:34:41.60#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.218.07:34:41.60#ibcon#ireg 11 cls_cnt 2 2006.218.07:34:41.60#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.218.07:34:41.66#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.218.07:34:41.66#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.218.07:34:41.66#ibcon#enter wrdev, iclass 39, count 2 2006.218.07:34:41.66#ibcon#first serial, iclass 39, count 2 2006.218.07:34:41.66#ibcon#enter sib2, iclass 39, count 2 2006.218.07:34:41.66#ibcon#flushed, iclass 39, count 2 2006.218.07:34:41.66#ibcon#about to write, iclass 39, count 2 2006.218.07:34:41.66#ibcon#wrote, iclass 39, count 2 2006.218.07:34:41.66#ibcon#about to read 3, iclass 39, count 2 2006.218.07:34:41.68#ibcon#read 3, iclass 39, count 2 2006.218.07:34:41.68#ibcon#about to read 4, iclass 39, count 2 2006.218.07:34:41.68#ibcon#read 4, iclass 39, count 2 2006.218.07:34:41.68#ibcon#about to read 5, iclass 39, count 2 2006.218.07:34:41.68#ibcon#read 5, iclass 39, count 2 2006.218.07:34:41.68#ibcon#about to read 6, iclass 39, count 2 2006.218.07:34:41.68#ibcon#read 6, iclass 39, count 2 2006.218.07:34:41.68#ibcon#end of sib2, iclass 39, count 2 2006.218.07:34:41.68#ibcon#*mode == 0, iclass 39, count 2 2006.218.07:34:41.68#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.218.07:34:41.68#ibcon#[27=AT04-04\r\n] 2006.218.07:34:41.68#ibcon#*before write, iclass 39, count 2 2006.218.07:34:41.68#ibcon#enter sib2, iclass 39, count 2 2006.218.07:34:41.68#ibcon#flushed, iclass 39, count 2 2006.218.07:34:41.68#ibcon#about to write, iclass 39, count 2 2006.218.07:34:41.68#ibcon#wrote, iclass 39, count 2 2006.218.07:34:41.68#ibcon#about to read 3, iclass 39, count 2 2006.218.07:34:41.71#ibcon#read 3, iclass 39, count 2 2006.218.07:34:41.71#ibcon#about to read 4, iclass 39, count 2 2006.218.07:34:41.71#ibcon#read 4, iclass 39, count 2 2006.218.07:34:41.71#ibcon#about to read 5, iclass 39, count 2 2006.218.07:34:41.71#ibcon#read 5, iclass 39, count 2 2006.218.07:34:41.71#ibcon#about to read 6, iclass 39, count 2 2006.218.07:34:41.71#ibcon#read 6, iclass 39, count 2 2006.218.07:34:41.71#ibcon#end of sib2, iclass 39, count 2 2006.218.07:34:41.71#ibcon#*after write, iclass 39, count 2 2006.218.07:34:41.71#ibcon#*before return 0, iclass 39, count 2 2006.218.07:34:41.71#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.218.07:34:41.71#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.218.07:34:41.71#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.218.07:34:41.71#ibcon#ireg 7 cls_cnt 0 2006.218.07:34:41.71#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.218.07:34:41.83#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.218.07:34:41.83#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.218.07:34:41.83#ibcon#enter wrdev, iclass 39, count 0 2006.218.07:34:41.83#ibcon#first serial, iclass 39, count 0 2006.218.07:34:41.83#ibcon#enter sib2, iclass 39, count 0 2006.218.07:34:41.83#ibcon#flushed, iclass 39, count 0 2006.218.07:34:41.83#ibcon#about to write, iclass 39, count 0 2006.218.07:34:41.83#ibcon#wrote, iclass 39, count 0 2006.218.07:34:41.83#ibcon#about to read 3, iclass 39, count 0 2006.218.07:34:41.85#ibcon#read 3, iclass 39, count 0 2006.218.07:34:41.85#ibcon#about to read 4, iclass 39, count 0 2006.218.07:34:41.85#ibcon#read 4, iclass 39, count 0 2006.218.07:34:41.85#ibcon#about to read 5, iclass 39, count 0 2006.218.07:34:41.85#ibcon#read 5, iclass 39, count 0 2006.218.07:34:41.85#ibcon#about to read 6, iclass 39, count 0 2006.218.07:34:41.85#ibcon#read 6, iclass 39, count 0 2006.218.07:34:41.85#ibcon#end of sib2, iclass 39, count 0 2006.218.07:34:41.85#ibcon#*mode == 0, iclass 39, count 0 2006.218.07:34:41.85#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.218.07:34:41.85#ibcon#[27=USB\r\n] 2006.218.07:34:41.85#ibcon#*before write, iclass 39, count 0 2006.218.07:34:41.85#ibcon#enter sib2, iclass 39, count 0 2006.218.07:34:41.85#ibcon#flushed, iclass 39, count 0 2006.218.07:34:41.85#ibcon#about to write, iclass 39, count 0 2006.218.07:34:41.85#ibcon#wrote, iclass 39, count 0 2006.218.07:34:41.85#ibcon#about to read 3, iclass 39, count 0 2006.218.07:34:41.88#ibcon#read 3, iclass 39, count 0 2006.218.07:34:41.88#ibcon#about to read 4, iclass 39, count 0 2006.218.07:34:41.88#ibcon#read 4, iclass 39, count 0 2006.218.07:34:41.88#ibcon#about to read 5, iclass 39, count 0 2006.218.07:34:41.88#ibcon#read 5, iclass 39, count 0 2006.218.07:34:41.88#ibcon#about to read 6, iclass 39, count 0 2006.218.07:34:41.88#ibcon#read 6, iclass 39, count 0 2006.218.07:34:41.88#ibcon#end of sib2, iclass 39, count 0 2006.218.07:34:41.88#ibcon#*after write, iclass 39, count 0 2006.218.07:34:41.88#ibcon#*before return 0, iclass 39, count 0 2006.218.07:34:41.88#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.218.07:34:41.88#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.218.07:34:41.88#ibcon#about to clear, iclass 39 cls_cnt 0 2006.218.07:34:41.88#ibcon#cleared, iclass 39 cls_cnt 0 2006.218.07:34:41.88$vc4f8/vblo=5,744.99 2006.218.07:34:41.88#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.218.07:34:41.88#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.218.07:34:41.88#ibcon#ireg 17 cls_cnt 0 2006.218.07:34:41.88#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.218.07:34:41.88#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.218.07:34:41.88#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.218.07:34:41.88#ibcon#enter wrdev, iclass 3, count 0 2006.218.07:34:41.88#ibcon#first serial, iclass 3, count 0 2006.218.07:34:41.88#ibcon#enter sib2, iclass 3, count 0 2006.218.07:34:41.88#ibcon#flushed, iclass 3, count 0 2006.218.07:34:41.88#ibcon#about to write, iclass 3, count 0 2006.218.07:34:41.88#ibcon#wrote, iclass 3, count 0 2006.218.07:34:41.88#ibcon#about to read 3, iclass 3, count 0 2006.218.07:34:41.90#ibcon#read 3, iclass 3, count 0 2006.218.07:34:41.90#ibcon#about to read 4, iclass 3, count 0 2006.218.07:34:41.90#ibcon#read 4, iclass 3, count 0 2006.218.07:34:41.90#ibcon#about to read 5, iclass 3, count 0 2006.218.07:34:41.90#ibcon#read 5, iclass 3, count 0 2006.218.07:34:41.90#ibcon#about to read 6, iclass 3, count 0 2006.218.07:34:41.90#ibcon#read 6, iclass 3, count 0 2006.218.07:34:41.90#ibcon#end of sib2, iclass 3, count 0 2006.218.07:34:41.90#ibcon#*mode == 0, iclass 3, count 0 2006.218.07:34:41.90#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.218.07:34:41.90#ibcon#[28=FRQ=05,744.99\r\n] 2006.218.07:34:41.90#ibcon#*before write, iclass 3, count 0 2006.218.07:34:41.90#ibcon#enter sib2, iclass 3, count 0 2006.218.07:34:41.90#ibcon#flushed, iclass 3, count 0 2006.218.07:34:41.90#ibcon#about to write, iclass 3, count 0 2006.218.07:34:41.90#ibcon#wrote, iclass 3, count 0 2006.218.07:34:41.90#ibcon#about to read 3, iclass 3, count 0 2006.218.07:34:41.94#ibcon#read 3, iclass 3, count 0 2006.218.07:34:41.94#ibcon#about to read 4, iclass 3, count 0 2006.218.07:34:41.94#ibcon#read 4, iclass 3, count 0 2006.218.07:34:41.94#ibcon#about to read 5, iclass 3, count 0 2006.218.07:34:41.94#ibcon#read 5, iclass 3, count 0 2006.218.07:34:41.94#ibcon#about to read 6, iclass 3, count 0 2006.218.07:34:41.94#ibcon#read 6, iclass 3, count 0 2006.218.07:34:41.94#ibcon#end of sib2, iclass 3, count 0 2006.218.07:34:41.94#ibcon#*after write, iclass 3, count 0 2006.218.07:34:41.94#ibcon#*before return 0, iclass 3, count 0 2006.218.07:34:41.94#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.218.07:34:41.94#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.218.07:34:41.94#ibcon#about to clear, iclass 3 cls_cnt 0 2006.218.07:34:41.94#ibcon#cleared, iclass 3 cls_cnt 0 2006.218.07:34:41.94$vc4f8/vb=5,4 2006.218.07:34:41.94#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.218.07:34:41.94#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.218.07:34:41.94#ibcon#ireg 11 cls_cnt 2 2006.218.07:34:41.94#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.218.07:34:42.00#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.218.07:34:42.00#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.218.07:34:42.00#ibcon#enter wrdev, iclass 5, count 2 2006.218.07:34:42.00#ibcon#first serial, iclass 5, count 2 2006.218.07:34:42.00#ibcon#enter sib2, iclass 5, count 2 2006.218.07:34:42.00#ibcon#flushed, iclass 5, count 2 2006.218.07:34:42.00#ibcon#about to write, iclass 5, count 2 2006.218.07:34:42.00#ibcon#wrote, iclass 5, count 2 2006.218.07:34:42.00#ibcon#about to read 3, iclass 5, count 2 2006.218.07:34:42.02#ibcon#read 3, iclass 5, count 2 2006.218.07:34:42.02#ibcon#about to read 4, iclass 5, count 2 2006.218.07:34:42.02#ibcon#read 4, iclass 5, count 2 2006.218.07:34:42.02#ibcon#about to read 5, iclass 5, count 2 2006.218.07:34:42.02#ibcon#read 5, iclass 5, count 2 2006.218.07:34:42.02#ibcon#about to read 6, iclass 5, count 2 2006.218.07:34:42.02#ibcon#read 6, iclass 5, count 2 2006.218.07:34:42.02#ibcon#end of sib2, iclass 5, count 2 2006.218.07:34:42.02#ibcon#*mode == 0, iclass 5, count 2 2006.218.07:34:42.02#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.218.07:34:42.02#ibcon#[27=AT05-04\r\n] 2006.218.07:34:42.02#ibcon#*before write, iclass 5, count 2 2006.218.07:34:42.02#ibcon#enter sib2, iclass 5, count 2 2006.218.07:34:42.02#ibcon#flushed, iclass 5, count 2 2006.218.07:34:42.02#ibcon#about to write, iclass 5, count 2 2006.218.07:34:42.02#ibcon#wrote, iclass 5, count 2 2006.218.07:34:42.02#ibcon#about to read 3, iclass 5, count 2 2006.218.07:34:42.05#ibcon#read 3, iclass 5, count 2 2006.218.07:34:42.05#ibcon#about to read 4, iclass 5, count 2 2006.218.07:34:42.05#ibcon#read 4, iclass 5, count 2 2006.218.07:34:42.05#ibcon#about to read 5, iclass 5, count 2 2006.218.07:34:42.05#ibcon#read 5, iclass 5, count 2 2006.218.07:34:42.05#ibcon#about to read 6, iclass 5, count 2 2006.218.07:34:42.05#ibcon#read 6, iclass 5, count 2 2006.218.07:34:42.05#ibcon#end of sib2, iclass 5, count 2 2006.218.07:34:42.05#ibcon#*after write, iclass 5, count 2 2006.218.07:34:42.05#ibcon#*before return 0, iclass 5, count 2 2006.218.07:34:42.05#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.218.07:34:42.05#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.218.07:34:42.05#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.218.07:34:42.05#ibcon#ireg 7 cls_cnt 0 2006.218.07:34:42.05#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.218.07:34:42.17#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.218.07:34:42.17#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.218.07:34:42.17#ibcon#enter wrdev, iclass 5, count 0 2006.218.07:34:42.17#ibcon#first serial, iclass 5, count 0 2006.218.07:34:42.17#ibcon#enter sib2, iclass 5, count 0 2006.218.07:34:42.17#ibcon#flushed, iclass 5, count 0 2006.218.07:34:42.17#ibcon#about to write, iclass 5, count 0 2006.218.07:34:42.17#ibcon#wrote, iclass 5, count 0 2006.218.07:34:42.17#ibcon#about to read 3, iclass 5, count 0 2006.218.07:34:42.20#ibcon#read 3, iclass 5, count 0 2006.218.07:34:42.20#ibcon#about to read 4, iclass 5, count 0 2006.218.07:34:42.20#ibcon#read 4, iclass 5, count 0 2006.218.07:34:42.20#ibcon#about to read 5, iclass 5, count 0 2006.218.07:34:42.20#ibcon#read 5, iclass 5, count 0 2006.218.07:34:42.20#ibcon#about to read 6, iclass 5, count 0 2006.218.07:34:42.20#ibcon#read 6, iclass 5, count 0 2006.218.07:34:42.20#ibcon#end of sib2, iclass 5, count 0 2006.218.07:34:42.20#ibcon#*mode == 0, iclass 5, count 0 2006.218.07:34:42.20#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.218.07:34:42.20#ibcon#[27=USB\r\n] 2006.218.07:34:42.20#ibcon#*before write, iclass 5, count 0 2006.218.07:34:42.20#ibcon#enter sib2, iclass 5, count 0 2006.218.07:34:42.20#ibcon#flushed, iclass 5, count 0 2006.218.07:34:42.20#ibcon#about to write, iclass 5, count 0 2006.218.07:34:42.20#ibcon#wrote, iclass 5, count 0 2006.218.07:34:42.20#ibcon#about to read 3, iclass 5, count 0 2006.218.07:34:42.23#ibcon#read 3, iclass 5, count 0 2006.218.07:34:42.23#ibcon#about to read 4, iclass 5, count 0 2006.218.07:34:42.23#ibcon#read 4, iclass 5, count 0 2006.218.07:34:42.23#ibcon#about to read 5, iclass 5, count 0 2006.218.07:34:42.23#ibcon#read 5, iclass 5, count 0 2006.218.07:34:42.23#ibcon#about to read 6, iclass 5, count 0 2006.218.07:34:42.23#ibcon#read 6, iclass 5, count 0 2006.218.07:34:42.23#ibcon#end of sib2, iclass 5, count 0 2006.218.07:34:42.23#ibcon#*after write, iclass 5, count 0 2006.218.07:34:42.23#ibcon#*before return 0, iclass 5, count 0 2006.218.07:34:42.23#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.218.07:34:42.23#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.218.07:34:42.23#ibcon#about to clear, iclass 5 cls_cnt 0 2006.218.07:34:42.23#ibcon#cleared, iclass 5 cls_cnt 0 2006.218.07:34:42.23$vc4f8/vblo=6,752.99 2006.218.07:34:42.23#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.218.07:34:42.23#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.218.07:34:42.23#ibcon#ireg 17 cls_cnt 0 2006.218.07:34:42.23#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.218.07:34:42.23#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.218.07:34:42.23#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.218.07:34:42.23#ibcon#enter wrdev, iclass 7, count 0 2006.218.07:34:42.23#ibcon#first serial, iclass 7, count 0 2006.218.07:34:42.23#ibcon#enter sib2, iclass 7, count 0 2006.218.07:34:42.23#ibcon#flushed, iclass 7, count 0 2006.218.07:34:42.23#ibcon#about to write, iclass 7, count 0 2006.218.07:34:42.23#ibcon#wrote, iclass 7, count 0 2006.218.07:34:42.23#ibcon#about to read 3, iclass 7, count 0 2006.218.07:34:42.25#ibcon#read 3, iclass 7, count 0 2006.218.07:34:42.25#ibcon#about to read 4, iclass 7, count 0 2006.218.07:34:42.25#ibcon#read 4, iclass 7, count 0 2006.218.07:34:42.25#ibcon#about to read 5, iclass 7, count 0 2006.218.07:34:42.25#ibcon#read 5, iclass 7, count 0 2006.218.07:34:42.25#ibcon#about to read 6, iclass 7, count 0 2006.218.07:34:42.25#ibcon#read 6, iclass 7, count 0 2006.218.07:34:42.25#ibcon#end of sib2, iclass 7, count 0 2006.218.07:34:42.25#ibcon#*mode == 0, iclass 7, count 0 2006.218.07:34:42.25#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.218.07:34:42.25#ibcon#[28=FRQ=06,752.99\r\n] 2006.218.07:34:42.25#ibcon#*before write, iclass 7, count 0 2006.218.07:34:42.25#ibcon#enter sib2, iclass 7, count 0 2006.218.07:34:42.25#ibcon#flushed, iclass 7, count 0 2006.218.07:34:42.25#ibcon#about to write, iclass 7, count 0 2006.218.07:34:42.25#ibcon#wrote, iclass 7, count 0 2006.218.07:34:42.25#ibcon#about to read 3, iclass 7, count 0 2006.218.07:34:42.29#ibcon#read 3, iclass 7, count 0 2006.218.07:34:42.29#ibcon#about to read 4, iclass 7, count 0 2006.218.07:34:42.29#ibcon#read 4, iclass 7, count 0 2006.218.07:34:42.29#ibcon#about to read 5, iclass 7, count 0 2006.218.07:34:42.29#ibcon#read 5, iclass 7, count 0 2006.218.07:34:42.29#ibcon#about to read 6, iclass 7, count 0 2006.218.07:34:42.29#ibcon#read 6, iclass 7, count 0 2006.218.07:34:42.29#ibcon#end of sib2, iclass 7, count 0 2006.218.07:34:42.29#ibcon#*after write, iclass 7, count 0 2006.218.07:34:42.29#ibcon#*before return 0, iclass 7, count 0 2006.218.07:34:42.29#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.218.07:34:42.29#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.218.07:34:42.29#ibcon#about to clear, iclass 7 cls_cnt 0 2006.218.07:34:42.29#ibcon#cleared, iclass 7 cls_cnt 0 2006.218.07:34:42.29$vc4f8/vb=6,4 2006.218.07:34:42.29#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.218.07:34:42.29#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.218.07:34:42.29#ibcon#ireg 11 cls_cnt 2 2006.218.07:34:42.29#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.218.07:34:42.35#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.218.07:34:42.35#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.218.07:34:42.35#ibcon#enter wrdev, iclass 11, count 2 2006.218.07:34:42.35#ibcon#first serial, iclass 11, count 2 2006.218.07:34:42.35#ibcon#enter sib2, iclass 11, count 2 2006.218.07:34:42.35#ibcon#flushed, iclass 11, count 2 2006.218.07:34:42.35#ibcon#about to write, iclass 11, count 2 2006.218.07:34:42.35#ibcon#wrote, iclass 11, count 2 2006.218.07:34:42.35#ibcon#about to read 3, iclass 11, count 2 2006.218.07:34:42.37#ibcon#read 3, iclass 11, count 2 2006.218.07:34:42.37#ibcon#about to read 4, iclass 11, count 2 2006.218.07:34:42.37#ibcon#read 4, iclass 11, count 2 2006.218.07:34:42.37#ibcon#about to read 5, iclass 11, count 2 2006.218.07:34:42.37#ibcon#read 5, iclass 11, count 2 2006.218.07:34:42.37#ibcon#about to read 6, iclass 11, count 2 2006.218.07:34:42.37#ibcon#read 6, iclass 11, count 2 2006.218.07:34:42.37#ibcon#end of sib2, iclass 11, count 2 2006.218.07:34:42.37#ibcon#*mode == 0, iclass 11, count 2 2006.218.07:34:42.37#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.218.07:34:42.37#ibcon#[27=AT06-04\r\n] 2006.218.07:34:42.37#ibcon#*before write, iclass 11, count 2 2006.218.07:34:42.37#ibcon#enter sib2, iclass 11, count 2 2006.218.07:34:42.37#ibcon#flushed, iclass 11, count 2 2006.218.07:34:42.37#ibcon#about to write, iclass 11, count 2 2006.218.07:34:42.37#ibcon#wrote, iclass 11, count 2 2006.218.07:34:42.37#ibcon#about to read 3, iclass 11, count 2 2006.218.07:34:42.40#ibcon#read 3, iclass 11, count 2 2006.218.07:34:42.40#ibcon#about to read 4, iclass 11, count 2 2006.218.07:34:42.40#ibcon#read 4, iclass 11, count 2 2006.218.07:34:42.40#ibcon#about to read 5, iclass 11, count 2 2006.218.07:34:42.40#ibcon#read 5, iclass 11, count 2 2006.218.07:34:42.40#ibcon#about to read 6, iclass 11, count 2 2006.218.07:34:42.40#ibcon#read 6, iclass 11, count 2 2006.218.07:34:42.40#ibcon#end of sib2, iclass 11, count 2 2006.218.07:34:42.40#ibcon#*after write, iclass 11, count 2 2006.218.07:34:42.40#ibcon#*before return 0, iclass 11, count 2 2006.218.07:34:42.40#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.218.07:34:42.40#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.218.07:34:42.40#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.218.07:34:42.40#ibcon#ireg 7 cls_cnt 0 2006.218.07:34:42.40#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.218.07:34:42.52#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.218.07:34:42.52#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.218.07:34:42.52#ibcon#enter wrdev, iclass 11, count 0 2006.218.07:34:42.52#ibcon#first serial, iclass 11, count 0 2006.218.07:34:42.52#ibcon#enter sib2, iclass 11, count 0 2006.218.07:34:42.52#ibcon#flushed, iclass 11, count 0 2006.218.07:34:42.52#ibcon#about to write, iclass 11, count 0 2006.218.07:34:42.52#ibcon#wrote, iclass 11, count 0 2006.218.07:34:42.52#ibcon#about to read 3, iclass 11, count 0 2006.218.07:34:42.54#ibcon#read 3, iclass 11, count 0 2006.218.07:34:42.54#ibcon#about to read 4, iclass 11, count 0 2006.218.07:34:42.54#ibcon#read 4, iclass 11, count 0 2006.218.07:34:42.54#ibcon#about to read 5, iclass 11, count 0 2006.218.07:34:42.54#ibcon#read 5, iclass 11, count 0 2006.218.07:34:42.54#ibcon#about to read 6, iclass 11, count 0 2006.218.07:34:42.54#ibcon#read 6, iclass 11, count 0 2006.218.07:34:42.54#ibcon#end of sib2, iclass 11, count 0 2006.218.07:34:42.54#ibcon#*mode == 0, iclass 11, count 0 2006.218.07:34:42.54#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.218.07:34:42.54#ibcon#[27=USB\r\n] 2006.218.07:34:42.54#ibcon#*before write, iclass 11, count 0 2006.218.07:34:42.54#ibcon#enter sib2, iclass 11, count 0 2006.218.07:34:42.54#ibcon#flushed, iclass 11, count 0 2006.218.07:34:42.54#ibcon#about to write, iclass 11, count 0 2006.218.07:34:42.54#ibcon#wrote, iclass 11, count 0 2006.218.07:34:42.54#ibcon#about to read 3, iclass 11, count 0 2006.218.07:34:42.57#ibcon#read 3, iclass 11, count 0 2006.218.07:34:42.57#ibcon#about to read 4, iclass 11, count 0 2006.218.07:34:42.57#ibcon#read 4, iclass 11, count 0 2006.218.07:34:42.57#ibcon#about to read 5, iclass 11, count 0 2006.218.07:34:42.57#ibcon#read 5, iclass 11, count 0 2006.218.07:34:42.57#ibcon#about to read 6, iclass 11, count 0 2006.218.07:34:42.57#ibcon#read 6, iclass 11, count 0 2006.218.07:34:42.57#ibcon#end of sib2, iclass 11, count 0 2006.218.07:34:42.57#ibcon#*after write, iclass 11, count 0 2006.218.07:34:42.57#ibcon#*before return 0, iclass 11, count 0 2006.218.07:34:42.57#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.218.07:34:42.57#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.218.07:34:42.57#ibcon#about to clear, iclass 11 cls_cnt 0 2006.218.07:34:42.57#ibcon#cleared, iclass 11 cls_cnt 0 2006.218.07:34:42.57$vc4f8/vabw=wide 2006.218.07:34:42.57#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.218.07:34:42.57#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.218.07:34:42.57#ibcon#ireg 8 cls_cnt 0 2006.218.07:34:42.57#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.218.07:34:42.57#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.218.07:34:42.57#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.218.07:34:42.57#ibcon#enter wrdev, iclass 13, count 0 2006.218.07:34:42.57#ibcon#first serial, iclass 13, count 0 2006.218.07:34:42.57#ibcon#enter sib2, iclass 13, count 0 2006.218.07:34:42.57#ibcon#flushed, iclass 13, count 0 2006.218.07:34:42.57#ibcon#about to write, iclass 13, count 0 2006.218.07:34:42.57#ibcon#wrote, iclass 13, count 0 2006.218.07:34:42.57#ibcon#about to read 3, iclass 13, count 0 2006.218.07:34:42.59#ibcon#read 3, iclass 13, count 0 2006.218.07:34:42.59#ibcon#about to read 4, iclass 13, count 0 2006.218.07:34:42.59#ibcon#read 4, iclass 13, count 0 2006.218.07:34:42.59#ibcon#about to read 5, iclass 13, count 0 2006.218.07:34:42.59#ibcon#read 5, iclass 13, count 0 2006.218.07:34:42.59#ibcon#about to read 6, iclass 13, count 0 2006.218.07:34:42.59#ibcon#read 6, iclass 13, count 0 2006.218.07:34:42.59#ibcon#end of sib2, iclass 13, count 0 2006.218.07:34:42.59#ibcon#*mode == 0, iclass 13, count 0 2006.218.07:34:42.59#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.218.07:34:42.59#ibcon#[25=BW32\r\n] 2006.218.07:34:42.59#ibcon#*before write, iclass 13, count 0 2006.218.07:34:42.59#ibcon#enter sib2, iclass 13, count 0 2006.218.07:34:42.59#ibcon#flushed, iclass 13, count 0 2006.218.07:34:42.59#ibcon#about to write, iclass 13, count 0 2006.218.07:34:42.59#ibcon#wrote, iclass 13, count 0 2006.218.07:34:42.59#ibcon#about to read 3, iclass 13, count 0 2006.218.07:34:42.62#ibcon#read 3, iclass 13, count 0 2006.218.07:34:42.62#ibcon#about to read 4, iclass 13, count 0 2006.218.07:34:42.62#ibcon#read 4, iclass 13, count 0 2006.218.07:34:42.62#ibcon#about to read 5, iclass 13, count 0 2006.218.07:34:42.62#ibcon#read 5, iclass 13, count 0 2006.218.07:34:42.62#ibcon#about to read 6, iclass 13, count 0 2006.218.07:34:42.62#ibcon#read 6, iclass 13, count 0 2006.218.07:34:42.62#ibcon#end of sib2, iclass 13, count 0 2006.218.07:34:42.62#ibcon#*after write, iclass 13, count 0 2006.218.07:34:42.62#ibcon#*before return 0, iclass 13, count 0 2006.218.07:34:42.62#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.218.07:34:42.62#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.218.07:34:42.62#ibcon#about to clear, iclass 13 cls_cnt 0 2006.218.07:34:42.62#ibcon#cleared, iclass 13 cls_cnt 0 2006.218.07:34:42.62$vc4f8/vbbw=wide 2006.218.07:34:42.62#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.218.07:34:42.62#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.218.07:34:42.62#ibcon#ireg 8 cls_cnt 0 2006.218.07:34:42.62#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.218.07:34:42.69#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.218.07:34:42.69#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.218.07:34:42.69#ibcon#enter wrdev, iclass 15, count 0 2006.218.07:34:42.69#ibcon#first serial, iclass 15, count 0 2006.218.07:34:42.69#ibcon#enter sib2, iclass 15, count 0 2006.218.07:34:42.69#ibcon#flushed, iclass 15, count 0 2006.218.07:34:42.69#ibcon#about to write, iclass 15, count 0 2006.218.07:34:42.69#ibcon#wrote, iclass 15, count 0 2006.218.07:34:42.69#ibcon#about to read 3, iclass 15, count 0 2006.218.07:34:42.71#ibcon#read 3, iclass 15, count 0 2006.218.07:34:42.71#ibcon#about to read 4, iclass 15, count 0 2006.218.07:34:42.71#ibcon#read 4, iclass 15, count 0 2006.218.07:34:42.71#ibcon#about to read 5, iclass 15, count 0 2006.218.07:34:42.71#ibcon#read 5, iclass 15, count 0 2006.218.07:34:42.71#ibcon#about to read 6, iclass 15, count 0 2006.218.07:34:42.71#ibcon#read 6, iclass 15, count 0 2006.218.07:34:42.71#ibcon#end of sib2, iclass 15, count 0 2006.218.07:34:42.71#ibcon#*mode == 0, iclass 15, count 0 2006.218.07:34:42.71#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.218.07:34:42.71#ibcon#[27=BW32\r\n] 2006.218.07:34:42.71#ibcon#*before write, iclass 15, count 0 2006.218.07:34:42.71#ibcon#enter sib2, iclass 15, count 0 2006.218.07:34:42.71#ibcon#flushed, iclass 15, count 0 2006.218.07:34:42.71#ibcon#about to write, iclass 15, count 0 2006.218.07:34:42.71#ibcon#wrote, iclass 15, count 0 2006.218.07:34:42.71#ibcon#about to read 3, iclass 15, count 0 2006.218.07:34:42.74#ibcon#read 3, iclass 15, count 0 2006.218.07:34:42.74#ibcon#about to read 4, iclass 15, count 0 2006.218.07:34:42.74#ibcon#read 4, iclass 15, count 0 2006.218.07:34:42.74#ibcon#about to read 5, iclass 15, count 0 2006.218.07:34:42.74#ibcon#read 5, iclass 15, count 0 2006.218.07:34:42.74#ibcon#about to read 6, iclass 15, count 0 2006.218.07:34:42.74#ibcon#read 6, iclass 15, count 0 2006.218.07:34:42.74#ibcon#end of sib2, iclass 15, count 0 2006.218.07:34:42.74#ibcon#*after write, iclass 15, count 0 2006.218.07:34:42.74#ibcon#*before return 0, iclass 15, count 0 2006.218.07:34:42.74#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.218.07:34:42.74#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.218.07:34:42.74#ibcon#about to clear, iclass 15 cls_cnt 0 2006.218.07:34:42.74#ibcon#cleared, iclass 15 cls_cnt 0 2006.218.07:34:42.74$4f8m12a/ifd4f 2006.218.07:34:42.74$ifd4f/lo= 2006.218.07:34:42.74$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.218.07:34:42.74$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.218.07:34:42.74$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.218.07:34:42.74$ifd4f/patch= 2006.218.07:34:42.74$ifd4f/patch=lo1,a1,a2,a3,a4 2006.218.07:34:42.74$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.218.07:34:42.74$ifd4f/patch=lo3,a5,a6,a7,a8 2006.218.07:34:42.74$4f8m12a/"form=m,16.000,1:2 2006.218.07:34:42.74$4f8m12a/"tpicd 2006.218.07:34:42.74$4f8m12a/echo=off 2006.218.07:34:42.74$4f8m12a/xlog=off 2006.218.07:34:42.74:!2006.218.07:35:10 2006.218.07:34:56.14#trakl#Source acquired 2006.218.07:34:58.14#flagr#flagr/antenna,acquired 2006.218.07:35:10.00:preob 2006.218.07:35:11.14/onsource/TRACKING 2006.218.07:35:11.14:!2006.218.07:35:20 2006.218.07:35:20.00:data_valid=on 2006.218.07:35:20.00:midob 2006.218.07:35:20.14/onsource/TRACKING 2006.218.07:35:20.14/wx/31.59,1007.4,70 2006.218.07:35:20.23/cable/+6.3841E-03 2006.218.07:35:21.32/va/01,05,usb,yes,32,33 2006.218.07:35:21.32/va/02,04,usb,yes,30,31 2006.218.07:35:21.32/va/03,04,usb,yes,28,28 2006.218.07:35:21.32/va/04,04,usb,yes,31,33 2006.218.07:35:21.32/va/05,07,usb,yes,33,35 2006.218.07:35:21.32/va/06,06,usb,yes,32,32 2006.218.07:35:21.32/va/07,06,usb,yes,33,32 2006.218.07:35:21.32/va/08,07,usb,yes,31,30 2006.218.07:35:21.55/valo/01,532.99,yes,locked 2006.218.07:35:21.55/valo/02,572.99,yes,locked 2006.218.07:35:21.55/valo/03,672.99,yes,locked 2006.218.07:35:21.55/valo/04,832.99,yes,locked 2006.218.07:35:21.55/valo/05,652.99,yes,locked 2006.218.07:35:21.55/valo/06,772.99,yes,locked 2006.218.07:35:21.55/valo/07,832.99,yes,locked 2006.218.07:35:21.55/valo/08,852.99,yes,locked 2006.218.07:35:22.64/vb/01,04,usb,yes,30,29 2006.218.07:35:22.64/vb/02,04,usb,yes,32,33 2006.218.07:35:22.64/vb/03,04,usb,yes,28,32 2006.218.07:35:22.64/vb/04,04,usb,yes,29,29 2006.218.07:35:22.64/vb/05,04,usb,yes,28,32 2006.218.07:35:22.64/vb/06,04,usb,yes,29,31 2006.218.07:35:22.64/vb/07,04,usb,yes,31,31 2006.218.07:35:22.64/vb/08,04,usb,yes,28,32 2006.218.07:35:22.87/vblo/01,632.99,yes,locked 2006.218.07:35:22.87/vblo/02,640.99,yes,locked 2006.218.07:35:22.87/vblo/03,656.99,yes,locked 2006.218.07:35:22.87/vblo/04,712.99,yes,locked 2006.218.07:35:22.87/vblo/05,744.99,yes,locked 2006.218.07:35:22.87/vblo/06,752.99,yes,locked 2006.218.07:35:22.87/vblo/07,734.99,yes,locked 2006.218.07:35:22.87/vblo/08,744.99,yes,locked 2006.218.07:35:23.02/vabw/8 2006.218.07:35:23.17/vbbw/8 2006.218.07:35:23.29/xfe/off,on,15.2 2006.218.07:35:23.67/ifatt/23,28,28,28 2006.218.07:35:24.07/fmout-gps/S +4.75E-07 2006.218.07:35:24.14:!2006.218.07:36:20 2006.218.07:36:20.01:data_valid=off 2006.218.07:36:20.01:postob 2006.218.07:36:20.22/cable/+6.3842E-03 2006.218.07:36:20.22/wx/31.54,1007.4,69 2006.218.07:36:21.08/fmout-gps/S +4.75E-07 2006.218.07:36:21.08:scan_name=218-0737,k06218,60 2006.218.07:36:21.09:source=0602+673,060752.67,672055.4,2000.0,ccw 2006.218.07:36:21.13#flagr#flagr/antenna,new-source 2006.218.07:36:22.13:checkk5 2006.218.07:36:22.51/chk_autoobs//k5ts1/ autoobs is running! 2006.218.07:36:22.88/chk_autoobs//k5ts2/ autoobs is running! 2006.218.07:36:23.26/chk_autoobs//k5ts3/ autoobs is running! 2006.218.07:36:23.64/chk_autoobs//k5ts4/ autoobs is running! 2006.218.07:36:24.00/chk_obsdata//k5ts1/T2180735??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:36:24.37/chk_obsdata//k5ts2/T2180735??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:36:24.74/chk_obsdata//k5ts3/T2180735??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:36:25.10/chk_obsdata//k5ts4/T2180735??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:36:25.79/k5log//k5ts1_log_newline 2006.218.07:36:26.48/k5log//k5ts2_log_newline 2006.218.07:36:27.18/k5log//k5ts3_log_newline 2006.218.07:36:27.86/k5log//k5ts4_log_newline 2006.218.07:36:27.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.218.07:36:27.88:4f8m12a=1 2006.218.07:36:27.88$4f8m12a/echo=on 2006.218.07:36:27.88$4f8m12a/pcalon 2006.218.07:36:27.88$pcalon/"no phase cal control is implemented here 2006.218.07:36:27.88$4f8m12a/"tpicd=stop 2006.218.07:36:27.88$4f8m12a/vc4f8 2006.218.07:36:27.88$vc4f8/valo=1,532.99 2006.218.07:36:27.88#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.218.07:36:27.88#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.218.07:36:27.88#ibcon#ireg 17 cls_cnt 0 2006.218.07:36:27.88#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.218.07:36:27.88#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.218.07:36:27.88#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.218.07:36:27.88#ibcon#enter wrdev, iclass 26, count 0 2006.218.07:36:27.88#ibcon#first serial, iclass 26, count 0 2006.218.07:36:27.88#ibcon#enter sib2, iclass 26, count 0 2006.218.07:36:27.88#ibcon#flushed, iclass 26, count 0 2006.218.07:36:27.88#ibcon#about to write, iclass 26, count 0 2006.218.07:36:27.88#ibcon#wrote, iclass 26, count 0 2006.218.07:36:27.88#ibcon#about to read 3, iclass 26, count 0 2006.218.07:36:27.90#ibcon#read 3, iclass 26, count 0 2006.218.07:36:27.90#ibcon#about to read 4, iclass 26, count 0 2006.218.07:36:27.90#ibcon#read 4, iclass 26, count 0 2006.218.07:36:27.90#ibcon#about to read 5, iclass 26, count 0 2006.218.07:36:27.90#ibcon#read 5, iclass 26, count 0 2006.218.07:36:27.90#ibcon#about to read 6, iclass 26, count 0 2006.218.07:36:27.90#ibcon#read 6, iclass 26, count 0 2006.218.07:36:27.90#ibcon#end of sib2, iclass 26, count 0 2006.218.07:36:27.90#ibcon#*mode == 0, iclass 26, count 0 2006.218.07:36:27.90#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.218.07:36:27.90#ibcon#[26=FRQ=01,532.99\r\n] 2006.218.07:36:27.90#ibcon#*before write, iclass 26, count 0 2006.218.07:36:27.90#ibcon#enter sib2, iclass 26, count 0 2006.218.07:36:27.90#ibcon#flushed, iclass 26, count 0 2006.218.07:36:27.90#ibcon#about to write, iclass 26, count 0 2006.218.07:36:27.90#ibcon#wrote, iclass 26, count 0 2006.218.07:36:27.90#ibcon#about to read 3, iclass 26, count 0 2006.218.07:36:27.95#ibcon#read 3, iclass 26, count 0 2006.218.07:36:27.95#ibcon#about to read 4, iclass 26, count 0 2006.218.07:36:27.95#ibcon#read 4, iclass 26, count 0 2006.218.07:36:27.95#ibcon#about to read 5, iclass 26, count 0 2006.218.07:36:27.95#ibcon#read 5, iclass 26, count 0 2006.218.07:36:27.95#ibcon#about to read 6, iclass 26, count 0 2006.218.07:36:27.95#ibcon#read 6, iclass 26, count 0 2006.218.07:36:27.95#ibcon#end of sib2, iclass 26, count 0 2006.218.07:36:27.95#ibcon#*after write, iclass 26, count 0 2006.218.07:36:27.95#ibcon#*before return 0, iclass 26, count 0 2006.218.07:36:27.95#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.218.07:36:27.95#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.218.07:36:27.95#ibcon#about to clear, iclass 26 cls_cnt 0 2006.218.07:36:27.95#ibcon#cleared, iclass 26 cls_cnt 0 2006.218.07:36:27.95$vc4f8/va=1,5 2006.218.07:36:27.95#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.218.07:36:27.95#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.218.07:36:27.95#ibcon#ireg 11 cls_cnt 2 2006.218.07:36:27.95#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.218.07:36:27.95#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.218.07:36:27.95#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.218.07:36:27.95#ibcon#enter wrdev, iclass 28, count 2 2006.218.07:36:27.95#ibcon#first serial, iclass 28, count 2 2006.218.07:36:27.95#ibcon#enter sib2, iclass 28, count 2 2006.218.07:36:27.95#ibcon#flushed, iclass 28, count 2 2006.218.07:36:27.95#ibcon#about to write, iclass 28, count 2 2006.218.07:36:27.95#ibcon#wrote, iclass 28, count 2 2006.218.07:36:27.95#ibcon#about to read 3, iclass 28, count 2 2006.218.07:36:27.97#ibcon#read 3, iclass 28, count 2 2006.218.07:36:27.97#ibcon#about to read 4, iclass 28, count 2 2006.218.07:36:27.97#ibcon#read 4, iclass 28, count 2 2006.218.07:36:27.97#ibcon#about to read 5, iclass 28, count 2 2006.218.07:36:27.97#ibcon#read 5, iclass 28, count 2 2006.218.07:36:27.97#ibcon#about to read 6, iclass 28, count 2 2006.218.07:36:27.97#ibcon#read 6, iclass 28, count 2 2006.218.07:36:27.97#ibcon#end of sib2, iclass 28, count 2 2006.218.07:36:27.97#ibcon#*mode == 0, iclass 28, count 2 2006.218.07:36:27.97#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.218.07:36:27.97#ibcon#[25=AT01-05\r\n] 2006.218.07:36:27.97#ibcon#*before write, iclass 28, count 2 2006.218.07:36:27.97#ibcon#enter sib2, iclass 28, count 2 2006.218.07:36:27.97#ibcon#flushed, iclass 28, count 2 2006.218.07:36:27.97#ibcon#about to write, iclass 28, count 2 2006.218.07:36:27.97#ibcon#wrote, iclass 28, count 2 2006.218.07:36:27.97#ibcon#about to read 3, iclass 28, count 2 2006.218.07:36:28.00#ibcon#read 3, iclass 28, count 2 2006.218.07:36:28.00#ibcon#about to read 4, iclass 28, count 2 2006.218.07:36:28.00#ibcon#read 4, iclass 28, count 2 2006.218.07:36:28.00#ibcon#about to read 5, iclass 28, count 2 2006.218.07:36:28.00#ibcon#read 5, iclass 28, count 2 2006.218.07:36:28.00#ibcon#about to read 6, iclass 28, count 2 2006.218.07:36:28.00#ibcon#read 6, iclass 28, count 2 2006.218.07:36:28.00#ibcon#end of sib2, iclass 28, count 2 2006.218.07:36:28.00#ibcon#*after write, iclass 28, count 2 2006.218.07:36:28.00#ibcon#*before return 0, iclass 28, count 2 2006.218.07:36:28.00#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.218.07:36:28.00#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.218.07:36:28.00#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.218.07:36:28.00#ibcon#ireg 7 cls_cnt 0 2006.218.07:36:28.00#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.218.07:36:28.12#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.218.07:36:28.12#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.218.07:36:28.12#ibcon#enter wrdev, iclass 28, count 0 2006.218.07:36:28.12#ibcon#first serial, iclass 28, count 0 2006.218.07:36:28.12#ibcon#enter sib2, iclass 28, count 0 2006.218.07:36:28.12#ibcon#flushed, iclass 28, count 0 2006.218.07:36:28.12#ibcon#about to write, iclass 28, count 0 2006.218.07:36:28.12#ibcon#wrote, iclass 28, count 0 2006.218.07:36:28.12#ibcon#about to read 3, iclass 28, count 0 2006.218.07:36:28.14#ibcon#read 3, iclass 28, count 0 2006.218.07:36:28.14#ibcon#about to read 4, iclass 28, count 0 2006.218.07:36:28.14#ibcon#read 4, iclass 28, count 0 2006.218.07:36:28.14#ibcon#about to read 5, iclass 28, count 0 2006.218.07:36:28.14#ibcon#read 5, iclass 28, count 0 2006.218.07:36:28.14#ibcon#about to read 6, iclass 28, count 0 2006.218.07:36:28.14#ibcon#read 6, iclass 28, count 0 2006.218.07:36:28.14#ibcon#end of sib2, iclass 28, count 0 2006.218.07:36:28.14#ibcon#*mode == 0, iclass 28, count 0 2006.218.07:36:28.14#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.218.07:36:28.14#ibcon#[25=USB\r\n] 2006.218.07:36:28.14#ibcon#*before write, iclass 28, count 0 2006.218.07:36:28.14#ibcon#enter sib2, iclass 28, count 0 2006.218.07:36:28.14#ibcon#flushed, iclass 28, count 0 2006.218.07:36:28.14#ibcon#about to write, iclass 28, count 0 2006.218.07:36:28.14#ibcon#wrote, iclass 28, count 0 2006.218.07:36:28.14#ibcon#about to read 3, iclass 28, count 0 2006.218.07:36:28.17#ibcon#read 3, iclass 28, count 0 2006.218.07:36:28.17#ibcon#about to read 4, iclass 28, count 0 2006.218.07:36:28.17#ibcon#read 4, iclass 28, count 0 2006.218.07:36:28.17#ibcon#about to read 5, iclass 28, count 0 2006.218.07:36:28.17#ibcon#read 5, iclass 28, count 0 2006.218.07:36:28.17#ibcon#about to read 6, iclass 28, count 0 2006.218.07:36:28.17#ibcon#read 6, iclass 28, count 0 2006.218.07:36:28.17#ibcon#end of sib2, iclass 28, count 0 2006.218.07:36:28.17#ibcon#*after write, iclass 28, count 0 2006.218.07:36:28.17#ibcon#*before return 0, iclass 28, count 0 2006.218.07:36:28.17#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.218.07:36:28.17#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.218.07:36:28.17#ibcon#about to clear, iclass 28 cls_cnt 0 2006.218.07:36:28.17#ibcon#cleared, iclass 28 cls_cnt 0 2006.218.07:36:28.17$vc4f8/valo=2,572.99 2006.218.07:36:28.17#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.218.07:36:28.17#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.218.07:36:28.17#ibcon#ireg 17 cls_cnt 0 2006.218.07:36:28.17#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.218.07:36:28.17#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.218.07:36:28.17#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.218.07:36:28.17#ibcon#enter wrdev, iclass 30, count 0 2006.218.07:36:28.17#ibcon#first serial, iclass 30, count 0 2006.218.07:36:28.17#ibcon#enter sib2, iclass 30, count 0 2006.218.07:36:28.17#ibcon#flushed, iclass 30, count 0 2006.218.07:36:28.17#ibcon#about to write, iclass 30, count 0 2006.218.07:36:28.17#ibcon#wrote, iclass 30, count 0 2006.218.07:36:28.17#ibcon#about to read 3, iclass 30, count 0 2006.218.07:36:28.19#ibcon#read 3, iclass 30, count 0 2006.218.07:36:28.19#ibcon#about to read 4, iclass 30, count 0 2006.218.07:36:28.19#ibcon#read 4, iclass 30, count 0 2006.218.07:36:28.19#ibcon#about to read 5, iclass 30, count 0 2006.218.07:36:28.19#ibcon#read 5, iclass 30, count 0 2006.218.07:36:28.19#ibcon#about to read 6, iclass 30, count 0 2006.218.07:36:28.19#ibcon#read 6, iclass 30, count 0 2006.218.07:36:28.19#ibcon#end of sib2, iclass 30, count 0 2006.218.07:36:28.19#ibcon#*mode == 0, iclass 30, count 0 2006.218.07:36:28.19#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.218.07:36:28.19#ibcon#[26=FRQ=02,572.99\r\n] 2006.218.07:36:28.19#ibcon#*before write, iclass 30, count 0 2006.218.07:36:28.19#ibcon#enter sib2, iclass 30, count 0 2006.218.07:36:28.19#ibcon#flushed, iclass 30, count 0 2006.218.07:36:28.19#ibcon#about to write, iclass 30, count 0 2006.218.07:36:28.19#ibcon#wrote, iclass 30, count 0 2006.218.07:36:28.19#ibcon#about to read 3, iclass 30, count 0 2006.218.07:36:28.24#ibcon#read 3, iclass 30, count 0 2006.218.07:36:28.24#ibcon#about to read 4, iclass 30, count 0 2006.218.07:36:28.24#ibcon#read 4, iclass 30, count 0 2006.218.07:36:28.24#ibcon#about to read 5, iclass 30, count 0 2006.218.07:36:28.24#ibcon#read 5, iclass 30, count 0 2006.218.07:36:28.24#ibcon#about to read 6, iclass 30, count 0 2006.218.07:36:28.24#ibcon#read 6, iclass 30, count 0 2006.218.07:36:28.24#ibcon#end of sib2, iclass 30, count 0 2006.218.07:36:28.24#ibcon#*after write, iclass 30, count 0 2006.218.07:36:28.24#ibcon#*before return 0, iclass 30, count 0 2006.218.07:36:28.24#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.218.07:36:28.24#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.218.07:36:28.24#ibcon#about to clear, iclass 30 cls_cnt 0 2006.218.07:36:28.24#ibcon#cleared, iclass 30 cls_cnt 0 2006.218.07:36:28.24$vc4f8/va=2,4 2006.218.07:36:28.24#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.218.07:36:28.24#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.218.07:36:28.24#ibcon#ireg 11 cls_cnt 2 2006.218.07:36:28.24#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.218.07:36:28.29#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.218.07:36:28.29#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.218.07:36:28.29#ibcon#enter wrdev, iclass 32, count 2 2006.218.07:36:28.29#ibcon#first serial, iclass 32, count 2 2006.218.07:36:28.29#ibcon#enter sib2, iclass 32, count 2 2006.218.07:36:28.29#ibcon#flushed, iclass 32, count 2 2006.218.07:36:28.29#ibcon#about to write, iclass 32, count 2 2006.218.07:36:28.29#ibcon#wrote, iclass 32, count 2 2006.218.07:36:28.29#ibcon#about to read 3, iclass 32, count 2 2006.218.07:36:28.31#ibcon#read 3, iclass 32, count 2 2006.218.07:36:28.31#ibcon#about to read 4, iclass 32, count 2 2006.218.07:36:28.31#ibcon#read 4, iclass 32, count 2 2006.218.07:36:28.31#ibcon#about to read 5, iclass 32, count 2 2006.218.07:36:28.31#ibcon#read 5, iclass 32, count 2 2006.218.07:36:28.31#ibcon#about to read 6, iclass 32, count 2 2006.218.07:36:28.31#ibcon#read 6, iclass 32, count 2 2006.218.07:36:28.31#ibcon#end of sib2, iclass 32, count 2 2006.218.07:36:28.31#ibcon#*mode == 0, iclass 32, count 2 2006.218.07:36:28.31#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.218.07:36:28.31#ibcon#[25=AT02-04\r\n] 2006.218.07:36:28.31#ibcon#*before write, iclass 32, count 2 2006.218.07:36:28.31#ibcon#enter sib2, iclass 32, count 2 2006.218.07:36:28.31#ibcon#flushed, iclass 32, count 2 2006.218.07:36:28.31#ibcon#about to write, iclass 32, count 2 2006.218.07:36:28.31#ibcon#wrote, iclass 32, count 2 2006.218.07:36:28.31#ibcon#about to read 3, iclass 32, count 2 2006.218.07:36:28.34#ibcon#read 3, iclass 32, count 2 2006.218.07:36:28.34#ibcon#about to read 4, iclass 32, count 2 2006.218.07:36:28.34#ibcon#read 4, iclass 32, count 2 2006.218.07:36:28.34#ibcon#about to read 5, iclass 32, count 2 2006.218.07:36:28.34#ibcon#read 5, iclass 32, count 2 2006.218.07:36:28.34#ibcon#about to read 6, iclass 32, count 2 2006.218.07:36:28.34#ibcon#read 6, iclass 32, count 2 2006.218.07:36:28.34#ibcon#end of sib2, iclass 32, count 2 2006.218.07:36:28.34#ibcon#*after write, iclass 32, count 2 2006.218.07:36:28.34#ibcon#*before return 0, iclass 32, count 2 2006.218.07:36:28.34#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.218.07:36:28.34#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.218.07:36:28.34#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.218.07:36:28.34#ibcon#ireg 7 cls_cnt 0 2006.218.07:36:28.34#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.218.07:36:28.46#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.218.07:36:28.46#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.218.07:36:28.46#ibcon#enter wrdev, iclass 32, count 0 2006.218.07:36:28.46#ibcon#first serial, iclass 32, count 0 2006.218.07:36:28.46#ibcon#enter sib2, iclass 32, count 0 2006.218.07:36:28.46#ibcon#flushed, iclass 32, count 0 2006.218.07:36:28.46#ibcon#about to write, iclass 32, count 0 2006.218.07:36:28.46#ibcon#wrote, iclass 32, count 0 2006.218.07:36:28.46#ibcon#about to read 3, iclass 32, count 0 2006.218.07:36:28.48#ibcon#read 3, iclass 32, count 0 2006.218.07:36:28.48#ibcon#about to read 4, iclass 32, count 0 2006.218.07:36:28.48#ibcon#read 4, iclass 32, count 0 2006.218.07:36:28.48#ibcon#about to read 5, iclass 32, count 0 2006.218.07:36:28.48#ibcon#read 5, iclass 32, count 0 2006.218.07:36:28.48#ibcon#about to read 6, iclass 32, count 0 2006.218.07:36:28.48#ibcon#read 6, iclass 32, count 0 2006.218.07:36:28.48#ibcon#end of sib2, iclass 32, count 0 2006.218.07:36:28.48#ibcon#*mode == 0, iclass 32, count 0 2006.218.07:36:28.48#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.218.07:36:28.48#ibcon#[25=USB\r\n] 2006.218.07:36:28.48#ibcon#*before write, iclass 32, count 0 2006.218.07:36:28.48#ibcon#enter sib2, iclass 32, count 0 2006.218.07:36:28.48#ibcon#flushed, iclass 32, count 0 2006.218.07:36:28.48#ibcon#about to write, iclass 32, count 0 2006.218.07:36:28.48#ibcon#wrote, iclass 32, count 0 2006.218.07:36:28.48#ibcon#about to read 3, iclass 32, count 0 2006.218.07:36:28.51#ibcon#read 3, iclass 32, count 0 2006.218.07:36:28.51#ibcon#about to read 4, iclass 32, count 0 2006.218.07:36:28.51#ibcon#read 4, iclass 32, count 0 2006.218.07:36:28.51#ibcon#about to read 5, iclass 32, count 0 2006.218.07:36:28.51#ibcon#read 5, iclass 32, count 0 2006.218.07:36:28.51#ibcon#about to read 6, iclass 32, count 0 2006.218.07:36:28.51#ibcon#read 6, iclass 32, count 0 2006.218.07:36:28.51#ibcon#end of sib2, iclass 32, count 0 2006.218.07:36:28.51#ibcon#*after write, iclass 32, count 0 2006.218.07:36:28.51#ibcon#*before return 0, iclass 32, count 0 2006.218.07:36:28.51#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.218.07:36:28.51#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.218.07:36:28.51#ibcon#about to clear, iclass 32 cls_cnt 0 2006.218.07:36:28.51#ibcon#cleared, iclass 32 cls_cnt 0 2006.218.07:36:28.51$vc4f8/valo=3,672.99 2006.218.07:36:28.51#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.218.07:36:28.51#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.218.07:36:28.51#ibcon#ireg 17 cls_cnt 0 2006.218.07:36:28.51#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.218.07:36:28.51#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.218.07:36:28.51#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.218.07:36:28.51#ibcon#enter wrdev, iclass 34, count 0 2006.218.07:36:28.51#ibcon#first serial, iclass 34, count 0 2006.218.07:36:28.51#ibcon#enter sib2, iclass 34, count 0 2006.218.07:36:28.51#ibcon#flushed, iclass 34, count 0 2006.218.07:36:28.51#ibcon#about to write, iclass 34, count 0 2006.218.07:36:28.51#ibcon#wrote, iclass 34, count 0 2006.218.07:36:28.51#ibcon#about to read 3, iclass 34, count 0 2006.218.07:36:28.53#ibcon#read 3, iclass 34, count 0 2006.218.07:36:28.53#ibcon#about to read 4, iclass 34, count 0 2006.218.07:36:28.53#ibcon#read 4, iclass 34, count 0 2006.218.07:36:28.53#ibcon#about to read 5, iclass 34, count 0 2006.218.07:36:28.53#ibcon#read 5, iclass 34, count 0 2006.218.07:36:28.53#ibcon#about to read 6, iclass 34, count 0 2006.218.07:36:28.53#ibcon#read 6, iclass 34, count 0 2006.218.07:36:28.53#ibcon#end of sib2, iclass 34, count 0 2006.218.07:36:28.53#ibcon#*mode == 0, iclass 34, count 0 2006.218.07:36:28.53#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.218.07:36:28.53#ibcon#[26=FRQ=03,672.99\r\n] 2006.218.07:36:28.53#ibcon#*before write, iclass 34, count 0 2006.218.07:36:28.53#ibcon#enter sib2, iclass 34, count 0 2006.218.07:36:28.53#ibcon#flushed, iclass 34, count 0 2006.218.07:36:28.53#ibcon#about to write, iclass 34, count 0 2006.218.07:36:28.53#ibcon#wrote, iclass 34, count 0 2006.218.07:36:28.53#ibcon#about to read 3, iclass 34, count 0 2006.218.07:36:28.57#ibcon#read 3, iclass 34, count 0 2006.218.07:36:28.57#ibcon#about to read 4, iclass 34, count 0 2006.218.07:36:28.57#ibcon#read 4, iclass 34, count 0 2006.218.07:36:28.57#ibcon#about to read 5, iclass 34, count 0 2006.218.07:36:28.57#ibcon#read 5, iclass 34, count 0 2006.218.07:36:28.57#ibcon#about to read 6, iclass 34, count 0 2006.218.07:36:28.57#ibcon#read 6, iclass 34, count 0 2006.218.07:36:28.57#ibcon#end of sib2, iclass 34, count 0 2006.218.07:36:28.57#ibcon#*after write, iclass 34, count 0 2006.218.07:36:28.57#ibcon#*before return 0, iclass 34, count 0 2006.218.07:36:28.57#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.218.07:36:28.57#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.218.07:36:28.57#ibcon#about to clear, iclass 34 cls_cnt 0 2006.218.07:36:28.57#ibcon#cleared, iclass 34 cls_cnt 0 2006.218.07:36:28.57$vc4f8/va=3,4 2006.218.07:36:28.57#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.218.07:36:28.57#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.218.07:36:28.57#ibcon#ireg 11 cls_cnt 2 2006.218.07:36:28.57#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.218.07:36:28.63#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.218.07:36:28.63#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.218.07:36:28.63#ibcon#enter wrdev, iclass 36, count 2 2006.218.07:36:28.63#ibcon#first serial, iclass 36, count 2 2006.218.07:36:28.64#ibcon#enter sib2, iclass 36, count 2 2006.218.07:36:28.64#ibcon#flushed, iclass 36, count 2 2006.218.07:36:28.64#ibcon#about to write, iclass 36, count 2 2006.218.07:36:28.64#ibcon#wrote, iclass 36, count 2 2006.218.07:36:28.64#ibcon#about to read 3, iclass 36, count 2 2006.218.07:36:28.65#ibcon#read 3, iclass 36, count 2 2006.218.07:36:28.65#ibcon#about to read 4, iclass 36, count 2 2006.218.07:36:28.65#ibcon#read 4, iclass 36, count 2 2006.218.07:36:28.65#ibcon#about to read 5, iclass 36, count 2 2006.218.07:36:28.65#ibcon#read 5, iclass 36, count 2 2006.218.07:36:28.65#ibcon#about to read 6, iclass 36, count 2 2006.218.07:36:28.65#ibcon#read 6, iclass 36, count 2 2006.218.07:36:28.65#ibcon#end of sib2, iclass 36, count 2 2006.218.07:36:28.65#ibcon#*mode == 0, iclass 36, count 2 2006.218.07:36:28.65#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.218.07:36:28.65#ibcon#[25=AT03-04\r\n] 2006.218.07:36:28.65#ibcon#*before write, iclass 36, count 2 2006.218.07:36:28.65#ibcon#enter sib2, iclass 36, count 2 2006.218.07:36:28.65#ibcon#flushed, iclass 36, count 2 2006.218.07:36:28.65#ibcon#about to write, iclass 36, count 2 2006.218.07:36:28.65#ibcon#wrote, iclass 36, count 2 2006.218.07:36:28.65#ibcon#about to read 3, iclass 36, count 2 2006.218.07:36:28.68#ibcon#read 3, iclass 36, count 2 2006.218.07:36:28.68#ibcon#about to read 4, iclass 36, count 2 2006.218.07:36:28.68#ibcon#read 4, iclass 36, count 2 2006.218.07:36:28.68#ibcon#about to read 5, iclass 36, count 2 2006.218.07:36:28.68#ibcon#read 5, iclass 36, count 2 2006.218.07:36:28.68#ibcon#about to read 6, iclass 36, count 2 2006.218.07:36:28.68#ibcon#read 6, iclass 36, count 2 2006.218.07:36:28.68#ibcon#end of sib2, iclass 36, count 2 2006.218.07:36:28.68#ibcon#*after write, iclass 36, count 2 2006.218.07:36:28.68#ibcon#*before return 0, iclass 36, count 2 2006.218.07:36:28.68#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.218.07:36:28.68#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.218.07:36:28.68#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.218.07:36:28.68#ibcon#ireg 7 cls_cnt 0 2006.218.07:36:28.68#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.218.07:36:28.80#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.218.07:36:28.80#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.218.07:36:28.80#ibcon#enter wrdev, iclass 36, count 0 2006.218.07:36:28.80#ibcon#first serial, iclass 36, count 0 2006.218.07:36:28.80#ibcon#enter sib2, iclass 36, count 0 2006.218.07:36:28.80#ibcon#flushed, iclass 36, count 0 2006.218.07:36:28.80#ibcon#about to write, iclass 36, count 0 2006.218.07:36:28.80#ibcon#wrote, iclass 36, count 0 2006.218.07:36:28.80#ibcon#about to read 3, iclass 36, count 0 2006.218.07:36:28.82#ibcon#read 3, iclass 36, count 0 2006.218.07:36:28.82#ibcon#about to read 4, iclass 36, count 0 2006.218.07:36:28.82#ibcon#read 4, iclass 36, count 0 2006.218.07:36:28.82#ibcon#about to read 5, iclass 36, count 0 2006.218.07:36:28.82#ibcon#read 5, iclass 36, count 0 2006.218.07:36:28.82#ibcon#about to read 6, iclass 36, count 0 2006.218.07:36:28.82#ibcon#read 6, iclass 36, count 0 2006.218.07:36:28.82#ibcon#end of sib2, iclass 36, count 0 2006.218.07:36:28.82#ibcon#*mode == 0, iclass 36, count 0 2006.218.07:36:28.82#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.218.07:36:28.82#ibcon#[25=USB\r\n] 2006.218.07:36:28.82#ibcon#*before write, iclass 36, count 0 2006.218.07:36:28.82#ibcon#enter sib2, iclass 36, count 0 2006.218.07:36:28.82#ibcon#flushed, iclass 36, count 0 2006.218.07:36:28.82#ibcon#about to write, iclass 36, count 0 2006.218.07:36:28.82#ibcon#wrote, iclass 36, count 0 2006.218.07:36:28.82#ibcon#about to read 3, iclass 36, count 0 2006.218.07:36:28.85#ibcon#read 3, iclass 36, count 0 2006.218.07:36:28.85#ibcon#about to read 4, iclass 36, count 0 2006.218.07:36:28.85#ibcon#read 4, iclass 36, count 0 2006.218.07:36:28.85#ibcon#about to read 5, iclass 36, count 0 2006.218.07:36:28.85#ibcon#read 5, iclass 36, count 0 2006.218.07:36:28.85#ibcon#about to read 6, iclass 36, count 0 2006.218.07:36:28.85#ibcon#read 6, iclass 36, count 0 2006.218.07:36:28.85#ibcon#end of sib2, iclass 36, count 0 2006.218.07:36:28.85#ibcon#*after write, iclass 36, count 0 2006.218.07:36:28.85#ibcon#*before return 0, iclass 36, count 0 2006.218.07:36:28.85#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.218.07:36:28.85#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.218.07:36:28.85#ibcon#about to clear, iclass 36 cls_cnt 0 2006.218.07:36:28.85#ibcon#cleared, iclass 36 cls_cnt 0 2006.218.07:36:28.85$vc4f8/valo=4,832.99 2006.218.07:36:28.85#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.218.07:36:28.85#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.218.07:36:28.85#ibcon#ireg 17 cls_cnt 0 2006.218.07:36:28.85#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.218.07:36:28.85#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.218.07:36:28.85#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.218.07:36:28.85#ibcon#enter wrdev, iclass 38, count 0 2006.218.07:36:28.85#ibcon#first serial, iclass 38, count 0 2006.218.07:36:28.85#ibcon#enter sib2, iclass 38, count 0 2006.218.07:36:28.85#ibcon#flushed, iclass 38, count 0 2006.218.07:36:28.85#ibcon#about to write, iclass 38, count 0 2006.218.07:36:28.85#ibcon#wrote, iclass 38, count 0 2006.218.07:36:28.85#ibcon#about to read 3, iclass 38, count 0 2006.218.07:36:28.87#ibcon#read 3, iclass 38, count 0 2006.218.07:36:28.87#ibcon#about to read 4, iclass 38, count 0 2006.218.07:36:28.87#ibcon#read 4, iclass 38, count 0 2006.218.07:36:28.87#ibcon#about to read 5, iclass 38, count 0 2006.218.07:36:28.87#ibcon#read 5, iclass 38, count 0 2006.218.07:36:28.87#ibcon#about to read 6, iclass 38, count 0 2006.218.07:36:28.87#ibcon#read 6, iclass 38, count 0 2006.218.07:36:28.87#ibcon#end of sib2, iclass 38, count 0 2006.218.07:36:28.87#ibcon#*mode == 0, iclass 38, count 0 2006.218.07:36:28.87#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.218.07:36:28.87#ibcon#[26=FRQ=04,832.99\r\n] 2006.218.07:36:28.87#ibcon#*before write, iclass 38, count 0 2006.218.07:36:28.87#ibcon#enter sib2, iclass 38, count 0 2006.218.07:36:28.87#ibcon#flushed, iclass 38, count 0 2006.218.07:36:28.87#ibcon#about to write, iclass 38, count 0 2006.218.07:36:28.87#ibcon#wrote, iclass 38, count 0 2006.218.07:36:28.87#ibcon#about to read 3, iclass 38, count 0 2006.218.07:36:28.91#ibcon#read 3, iclass 38, count 0 2006.218.07:36:28.91#ibcon#about to read 4, iclass 38, count 0 2006.218.07:36:28.91#ibcon#read 4, iclass 38, count 0 2006.218.07:36:28.91#ibcon#about to read 5, iclass 38, count 0 2006.218.07:36:28.91#ibcon#read 5, iclass 38, count 0 2006.218.07:36:28.91#ibcon#about to read 6, iclass 38, count 0 2006.218.07:36:28.91#ibcon#read 6, iclass 38, count 0 2006.218.07:36:28.91#ibcon#end of sib2, iclass 38, count 0 2006.218.07:36:28.91#ibcon#*after write, iclass 38, count 0 2006.218.07:36:28.91#ibcon#*before return 0, iclass 38, count 0 2006.218.07:36:28.91#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.218.07:36:28.91#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.218.07:36:28.91#ibcon#about to clear, iclass 38 cls_cnt 0 2006.218.07:36:28.91#ibcon#cleared, iclass 38 cls_cnt 0 2006.218.07:36:28.91$vc4f8/va=4,4 2006.218.07:36:28.91#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.218.07:36:28.91#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.218.07:36:28.91#ibcon#ireg 11 cls_cnt 2 2006.218.07:36:28.91#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.218.07:36:28.98#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.218.07:36:28.98#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.218.07:36:28.98#ibcon#enter wrdev, iclass 40, count 2 2006.218.07:36:28.98#ibcon#first serial, iclass 40, count 2 2006.218.07:36:28.98#ibcon#enter sib2, iclass 40, count 2 2006.218.07:36:28.98#ibcon#flushed, iclass 40, count 2 2006.218.07:36:28.98#ibcon#about to write, iclass 40, count 2 2006.218.07:36:28.98#ibcon#wrote, iclass 40, count 2 2006.218.07:36:28.98#ibcon#about to read 3, iclass 40, count 2 2006.218.07:36:28.99#ibcon#read 3, iclass 40, count 2 2006.218.07:36:28.99#ibcon#about to read 4, iclass 40, count 2 2006.218.07:36:28.99#ibcon#read 4, iclass 40, count 2 2006.218.07:36:28.99#ibcon#about to read 5, iclass 40, count 2 2006.218.07:36:28.99#ibcon#read 5, iclass 40, count 2 2006.218.07:36:28.99#ibcon#about to read 6, iclass 40, count 2 2006.218.07:36:28.99#ibcon#read 6, iclass 40, count 2 2006.218.07:36:28.99#ibcon#end of sib2, iclass 40, count 2 2006.218.07:36:28.99#ibcon#*mode == 0, iclass 40, count 2 2006.218.07:36:28.99#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.218.07:36:28.99#ibcon#[25=AT04-04\r\n] 2006.218.07:36:28.99#ibcon#*before write, iclass 40, count 2 2006.218.07:36:28.99#ibcon#enter sib2, iclass 40, count 2 2006.218.07:36:28.99#ibcon#flushed, iclass 40, count 2 2006.218.07:36:28.99#ibcon#about to write, iclass 40, count 2 2006.218.07:36:28.99#ibcon#wrote, iclass 40, count 2 2006.218.07:36:28.99#ibcon#about to read 3, iclass 40, count 2 2006.218.07:36:29.02#ibcon#read 3, iclass 40, count 2 2006.218.07:36:29.02#ibcon#about to read 4, iclass 40, count 2 2006.218.07:36:29.02#ibcon#read 4, iclass 40, count 2 2006.218.07:36:29.02#ibcon#about to read 5, iclass 40, count 2 2006.218.07:36:29.02#ibcon#read 5, iclass 40, count 2 2006.218.07:36:29.02#ibcon#about to read 6, iclass 40, count 2 2006.218.07:36:29.02#ibcon#read 6, iclass 40, count 2 2006.218.07:36:29.02#ibcon#end of sib2, iclass 40, count 2 2006.218.07:36:29.02#ibcon#*after write, iclass 40, count 2 2006.218.07:36:29.02#ibcon#*before return 0, iclass 40, count 2 2006.218.07:36:29.02#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.218.07:36:29.02#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.218.07:36:29.02#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.218.07:36:29.02#ibcon#ireg 7 cls_cnt 0 2006.218.07:36:29.02#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.218.07:36:29.14#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.218.07:36:29.14#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.218.07:36:29.14#ibcon#enter wrdev, iclass 40, count 0 2006.218.07:36:29.14#ibcon#first serial, iclass 40, count 0 2006.218.07:36:29.14#ibcon#enter sib2, iclass 40, count 0 2006.218.07:36:29.14#ibcon#flushed, iclass 40, count 0 2006.218.07:36:29.14#ibcon#about to write, iclass 40, count 0 2006.218.07:36:29.14#ibcon#wrote, iclass 40, count 0 2006.218.07:36:29.14#ibcon#about to read 3, iclass 40, count 0 2006.218.07:36:29.16#ibcon#read 3, iclass 40, count 0 2006.218.07:36:29.16#ibcon#about to read 4, iclass 40, count 0 2006.218.07:36:29.16#ibcon#read 4, iclass 40, count 0 2006.218.07:36:29.16#ibcon#about to read 5, iclass 40, count 0 2006.218.07:36:29.16#ibcon#read 5, iclass 40, count 0 2006.218.07:36:29.16#ibcon#about to read 6, iclass 40, count 0 2006.218.07:36:29.16#ibcon#read 6, iclass 40, count 0 2006.218.07:36:29.16#ibcon#end of sib2, iclass 40, count 0 2006.218.07:36:29.16#ibcon#*mode == 0, iclass 40, count 0 2006.218.07:36:29.16#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.218.07:36:29.16#ibcon#[25=USB\r\n] 2006.218.07:36:29.16#ibcon#*before write, iclass 40, count 0 2006.218.07:36:29.16#ibcon#enter sib2, iclass 40, count 0 2006.218.07:36:29.16#ibcon#flushed, iclass 40, count 0 2006.218.07:36:29.16#ibcon#about to write, iclass 40, count 0 2006.218.07:36:29.16#ibcon#wrote, iclass 40, count 0 2006.218.07:36:29.16#ibcon#about to read 3, iclass 40, count 0 2006.218.07:36:29.19#ibcon#read 3, iclass 40, count 0 2006.218.07:36:29.19#ibcon#about to read 4, iclass 40, count 0 2006.218.07:36:29.19#ibcon#read 4, iclass 40, count 0 2006.218.07:36:29.19#ibcon#about to read 5, iclass 40, count 0 2006.218.07:36:29.19#ibcon#read 5, iclass 40, count 0 2006.218.07:36:29.19#ibcon#about to read 6, iclass 40, count 0 2006.218.07:36:29.19#ibcon#read 6, iclass 40, count 0 2006.218.07:36:29.19#ibcon#end of sib2, iclass 40, count 0 2006.218.07:36:29.19#ibcon#*after write, iclass 40, count 0 2006.218.07:36:29.19#ibcon#*before return 0, iclass 40, count 0 2006.218.07:36:29.19#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.218.07:36:29.19#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.218.07:36:29.19#ibcon#about to clear, iclass 40 cls_cnt 0 2006.218.07:36:29.19#ibcon#cleared, iclass 40 cls_cnt 0 2006.218.07:36:29.19$vc4f8/valo=5,652.99 2006.218.07:36:29.19#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.218.07:36:29.19#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.218.07:36:29.19#ibcon#ireg 17 cls_cnt 0 2006.218.07:36:29.19#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.218.07:36:29.19#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.218.07:36:29.19#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.218.07:36:29.19#ibcon#enter wrdev, iclass 4, count 0 2006.218.07:36:29.19#ibcon#first serial, iclass 4, count 0 2006.218.07:36:29.19#ibcon#enter sib2, iclass 4, count 0 2006.218.07:36:29.19#ibcon#flushed, iclass 4, count 0 2006.218.07:36:29.19#ibcon#about to write, iclass 4, count 0 2006.218.07:36:29.19#ibcon#wrote, iclass 4, count 0 2006.218.07:36:29.19#ibcon#about to read 3, iclass 4, count 0 2006.218.07:36:29.21#ibcon#read 3, iclass 4, count 0 2006.218.07:36:29.21#ibcon#about to read 4, iclass 4, count 0 2006.218.07:36:29.21#ibcon#read 4, iclass 4, count 0 2006.218.07:36:29.21#ibcon#about to read 5, iclass 4, count 0 2006.218.07:36:29.21#ibcon#read 5, iclass 4, count 0 2006.218.07:36:29.21#ibcon#about to read 6, iclass 4, count 0 2006.218.07:36:29.21#ibcon#read 6, iclass 4, count 0 2006.218.07:36:29.21#ibcon#end of sib2, iclass 4, count 0 2006.218.07:36:29.21#ibcon#*mode == 0, iclass 4, count 0 2006.218.07:36:29.21#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.218.07:36:29.21#ibcon#[26=FRQ=05,652.99\r\n] 2006.218.07:36:29.21#ibcon#*before write, iclass 4, count 0 2006.218.07:36:29.21#ibcon#enter sib2, iclass 4, count 0 2006.218.07:36:29.21#ibcon#flushed, iclass 4, count 0 2006.218.07:36:29.21#ibcon#about to write, iclass 4, count 0 2006.218.07:36:29.21#ibcon#wrote, iclass 4, count 0 2006.218.07:36:29.21#ibcon#about to read 3, iclass 4, count 0 2006.218.07:36:29.25#ibcon#read 3, iclass 4, count 0 2006.218.07:36:29.25#ibcon#about to read 4, iclass 4, count 0 2006.218.07:36:29.25#ibcon#read 4, iclass 4, count 0 2006.218.07:36:29.25#ibcon#about to read 5, iclass 4, count 0 2006.218.07:36:29.25#ibcon#read 5, iclass 4, count 0 2006.218.07:36:29.25#ibcon#about to read 6, iclass 4, count 0 2006.218.07:36:29.25#ibcon#read 6, iclass 4, count 0 2006.218.07:36:29.25#ibcon#end of sib2, iclass 4, count 0 2006.218.07:36:29.25#ibcon#*after write, iclass 4, count 0 2006.218.07:36:29.25#ibcon#*before return 0, iclass 4, count 0 2006.218.07:36:29.25#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.218.07:36:29.25#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.218.07:36:29.25#ibcon#about to clear, iclass 4 cls_cnt 0 2006.218.07:36:29.25#ibcon#cleared, iclass 4 cls_cnt 0 2006.218.07:36:29.25$vc4f8/va=5,7 2006.218.07:36:29.25#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.218.07:36:29.25#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.218.07:36:29.25#ibcon#ireg 11 cls_cnt 2 2006.218.07:36:29.25#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.218.07:36:29.31#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.218.07:36:29.31#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.218.07:36:29.31#ibcon#enter wrdev, iclass 6, count 2 2006.218.07:36:29.31#ibcon#first serial, iclass 6, count 2 2006.218.07:36:29.31#ibcon#enter sib2, iclass 6, count 2 2006.218.07:36:29.31#ibcon#flushed, iclass 6, count 2 2006.218.07:36:29.31#ibcon#about to write, iclass 6, count 2 2006.218.07:36:29.31#ibcon#wrote, iclass 6, count 2 2006.218.07:36:29.31#ibcon#about to read 3, iclass 6, count 2 2006.218.07:36:29.33#ibcon#read 3, iclass 6, count 2 2006.218.07:36:29.33#ibcon#about to read 4, iclass 6, count 2 2006.218.07:36:29.33#ibcon#read 4, iclass 6, count 2 2006.218.07:36:29.33#ibcon#about to read 5, iclass 6, count 2 2006.218.07:36:29.33#ibcon#read 5, iclass 6, count 2 2006.218.07:36:29.33#ibcon#about to read 6, iclass 6, count 2 2006.218.07:36:29.33#ibcon#read 6, iclass 6, count 2 2006.218.07:36:29.33#ibcon#end of sib2, iclass 6, count 2 2006.218.07:36:29.33#ibcon#*mode == 0, iclass 6, count 2 2006.218.07:36:29.33#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.218.07:36:29.33#ibcon#[25=AT05-07\r\n] 2006.218.07:36:29.33#ibcon#*before write, iclass 6, count 2 2006.218.07:36:29.33#ibcon#enter sib2, iclass 6, count 2 2006.218.07:36:29.33#ibcon#flushed, iclass 6, count 2 2006.218.07:36:29.33#ibcon#about to write, iclass 6, count 2 2006.218.07:36:29.33#ibcon#wrote, iclass 6, count 2 2006.218.07:36:29.33#ibcon#about to read 3, iclass 6, count 2 2006.218.07:36:29.36#ibcon#read 3, iclass 6, count 2 2006.218.07:36:29.36#ibcon#about to read 4, iclass 6, count 2 2006.218.07:36:29.36#ibcon#read 4, iclass 6, count 2 2006.218.07:36:29.36#ibcon#about to read 5, iclass 6, count 2 2006.218.07:36:29.36#ibcon#read 5, iclass 6, count 2 2006.218.07:36:29.36#ibcon#about to read 6, iclass 6, count 2 2006.218.07:36:29.36#ibcon#read 6, iclass 6, count 2 2006.218.07:36:29.36#ibcon#end of sib2, iclass 6, count 2 2006.218.07:36:29.36#ibcon#*after write, iclass 6, count 2 2006.218.07:36:29.36#ibcon#*before return 0, iclass 6, count 2 2006.218.07:36:29.36#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.218.07:36:29.36#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.218.07:36:29.36#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.218.07:36:29.36#ibcon#ireg 7 cls_cnt 0 2006.218.07:36:29.36#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.218.07:36:29.48#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.218.07:36:29.48#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.218.07:36:29.48#ibcon#enter wrdev, iclass 6, count 0 2006.218.07:36:29.48#ibcon#first serial, iclass 6, count 0 2006.218.07:36:29.48#ibcon#enter sib2, iclass 6, count 0 2006.218.07:36:29.48#ibcon#flushed, iclass 6, count 0 2006.218.07:36:29.48#ibcon#about to write, iclass 6, count 0 2006.218.07:36:29.48#ibcon#wrote, iclass 6, count 0 2006.218.07:36:29.48#ibcon#about to read 3, iclass 6, count 0 2006.218.07:36:29.50#ibcon#read 3, iclass 6, count 0 2006.218.07:36:29.50#ibcon#about to read 4, iclass 6, count 0 2006.218.07:36:29.50#ibcon#read 4, iclass 6, count 0 2006.218.07:36:29.50#ibcon#about to read 5, iclass 6, count 0 2006.218.07:36:29.50#ibcon#read 5, iclass 6, count 0 2006.218.07:36:29.50#ibcon#about to read 6, iclass 6, count 0 2006.218.07:36:29.50#ibcon#read 6, iclass 6, count 0 2006.218.07:36:29.50#ibcon#end of sib2, iclass 6, count 0 2006.218.07:36:29.50#ibcon#*mode == 0, iclass 6, count 0 2006.218.07:36:29.50#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.218.07:36:29.50#ibcon#[25=USB\r\n] 2006.218.07:36:29.50#ibcon#*before write, iclass 6, count 0 2006.218.07:36:29.50#ibcon#enter sib2, iclass 6, count 0 2006.218.07:36:29.50#ibcon#flushed, iclass 6, count 0 2006.218.07:36:29.50#ibcon#about to write, iclass 6, count 0 2006.218.07:36:29.50#ibcon#wrote, iclass 6, count 0 2006.218.07:36:29.50#ibcon#about to read 3, iclass 6, count 0 2006.218.07:36:29.53#ibcon#read 3, iclass 6, count 0 2006.218.07:36:29.53#ibcon#about to read 4, iclass 6, count 0 2006.218.07:36:29.53#ibcon#read 4, iclass 6, count 0 2006.218.07:36:29.53#ibcon#about to read 5, iclass 6, count 0 2006.218.07:36:29.53#ibcon#read 5, iclass 6, count 0 2006.218.07:36:29.53#ibcon#about to read 6, iclass 6, count 0 2006.218.07:36:29.53#ibcon#read 6, iclass 6, count 0 2006.218.07:36:29.53#ibcon#end of sib2, iclass 6, count 0 2006.218.07:36:29.53#ibcon#*after write, iclass 6, count 0 2006.218.07:36:29.53#ibcon#*before return 0, iclass 6, count 0 2006.218.07:36:29.53#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.218.07:36:29.53#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.218.07:36:29.53#ibcon#about to clear, iclass 6 cls_cnt 0 2006.218.07:36:29.53#ibcon#cleared, iclass 6 cls_cnt 0 2006.218.07:36:29.53$vc4f8/valo=6,772.99 2006.218.07:36:29.53#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.218.07:36:29.53#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.218.07:36:29.53#ibcon#ireg 17 cls_cnt 0 2006.218.07:36:29.53#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.218.07:36:29.53#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.218.07:36:29.53#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.218.07:36:29.53#ibcon#enter wrdev, iclass 10, count 0 2006.218.07:36:29.53#ibcon#first serial, iclass 10, count 0 2006.218.07:36:29.53#ibcon#enter sib2, iclass 10, count 0 2006.218.07:36:29.53#ibcon#flushed, iclass 10, count 0 2006.218.07:36:29.53#ibcon#about to write, iclass 10, count 0 2006.218.07:36:29.53#ibcon#wrote, iclass 10, count 0 2006.218.07:36:29.53#ibcon#about to read 3, iclass 10, count 0 2006.218.07:36:29.55#ibcon#read 3, iclass 10, count 0 2006.218.07:36:29.55#ibcon#about to read 4, iclass 10, count 0 2006.218.07:36:29.55#ibcon#read 4, iclass 10, count 0 2006.218.07:36:29.55#ibcon#about to read 5, iclass 10, count 0 2006.218.07:36:29.55#ibcon#read 5, iclass 10, count 0 2006.218.07:36:29.55#ibcon#about to read 6, iclass 10, count 0 2006.218.07:36:29.55#ibcon#read 6, iclass 10, count 0 2006.218.07:36:29.55#ibcon#end of sib2, iclass 10, count 0 2006.218.07:36:29.55#ibcon#*mode == 0, iclass 10, count 0 2006.218.07:36:29.55#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.218.07:36:29.55#ibcon#[26=FRQ=06,772.99\r\n] 2006.218.07:36:29.55#ibcon#*before write, iclass 10, count 0 2006.218.07:36:29.55#ibcon#enter sib2, iclass 10, count 0 2006.218.07:36:29.55#ibcon#flushed, iclass 10, count 0 2006.218.07:36:29.55#ibcon#about to write, iclass 10, count 0 2006.218.07:36:29.55#ibcon#wrote, iclass 10, count 0 2006.218.07:36:29.55#ibcon#about to read 3, iclass 10, count 0 2006.218.07:36:29.59#ibcon#read 3, iclass 10, count 0 2006.218.07:36:29.59#ibcon#about to read 4, iclass 10, count 0 2006.218.07:36:29.59#ibcon#read 4, iclass 10, count 0 2006.218.07:36:29.59#ibcon#about to read 5, iclass 10, count 0 2006.218.07:36:29.59#ibcon#read 5, iclass 10, count 0 2006.218.07:36:29.59#ibcon#about to read 6, iclass 10, count 0 2006.218.07:36:29.59#ibcon#read 6, iclass 10, count 0 2006.218.07:36:29.59#ibcon#end of sib2, iclass 10, count 0 2006.218.07:36:29.59#ibcon#*after write, iclass 10, count 0 2006.218.07:36:29.59#ibcon#*before return 0, iclass 10, count 0 2006.218.07:36:29.59#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.218.07:36:29.59#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.218.07:36:29.59#ibcon#about to clear, iclass 10 cls_cnt 0 2006.218.07:36:29.59#ibcon#cleared, iclass 10 cls_cnt 0 2006.218.07:36:29.59$vc4f8/va=6,6 2006.218.07:36:29.59#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.218.07:36:29.59#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.218.07:36:29.59#ibcon#ireg 11 cls_cnt 2 2006.218.07:36:29.59#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.218.07:36:29.65#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.218.07:36:29.65#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.218.07:36:29.65#ibcon#enter wrdev, iclass 12, count 2 2006.218.07:36:29.65#ibcon#first serial, iclass 12, count 2 2006.218.07:36:29.65#ibcon#enter sib2, iclass 12, count 2 2006.218.07:36:29.65#ibcon#flushed, iclass 12, count 2 2006.218.07:36:29.65#ibcon#about to write, iclass 12, count 2 2006.218.07:36:29.65#ibcon#wrote, iclass 12, count 2 2006.218.07:36:29.65#ibcon#about to read 3, iclass 12, count 2 2006.218.07:36:29.68#ibcon#read 3, iclass 12, count 2 2006.218.07:36:29.68#ibcon#about to read 4, iclass 12, count 2 2006.218.07:36:29.68#ibcon#read 4, iclass 12, count 2 2006.218.07:36:29.68#ibcon#about to read 5, iclass 12, count 2 2006.218.07:36:29.68#ibcon#read 5, iclass 12, count 2 2006.218.07:36:29.68#ibcon#about to read 6, iclass 12, count 2 2006.218.07:36:29.68#ibcon#read 6, iclass 12, count 2 2006.218.07:36:29.68#ibcon#end of sib2, iclass 12, count 2 2006.218.07:36:29.68#ibcon#*mode == 0, iclass 12, count 2 2006.218.07:36:29.68#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.218.07:36:29.68#ibcon#[25=AT06-06\r\n] 2006.218.07:36:29.68#ibcon#*before write, iclass 12, count 2 2006.218.07:36:29.68#ibcon#enter sib2, iclass 12, count 2 2006.218.07:36:29.68#ibcon#flushed, iclass 12, count 2 2006.218.07:36:29.68#ibcon#about to write, iclass 12, count 2 2006.218.07:36:29.68#ibcon#wrote, iclass 12, count 2 2006.218.07:36:29.68#ibcon#about to read 3, iclass 12, count 2 2006.218.07:36:29.71#ibcon#read 3, iclass 12, count 2 2006.218.07:36:29.71#ibcon#about to read 4, iclass 12, count 2 2006.218.07:36:29.71#ibcon#read 4, iclass 12, count 2 2006.218.07:36:29.71#ibcon#about to read 5, iclass 12, count 2 2006.218.07:36:29.71#ibcon#read 5, iclass 12, count 2 2006.218.07:36:29.71#ibcon#about to read 6, iclass 12, count 2 2006.218.07:36:29.71#ibcon#read 6, iclass 12, count 2 2006.218.07:36:29.71#ibcon#end of sib2, iclass 12, count 2 2006.218.07:36:29.71#ibcon#*after write, iclass 12, count 2 2006.218.07:36:29.71#ibcon#*before return 0, iclass 12, count 2 2006.218.07:36:29.71#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.218.07:36:29.71#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.218.07:36:29.71#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.218.07:36:29.71#ibcon#ireg 7 cls_cnt 0 2006.218.07:36:29.71#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.218.07:36:29.83#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.218.07:36:29.83#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.218.07:36:29.83#ibcon#enter wrdev, iclass 12, count 0 2006.218.07:36:29.83#ibcon#first serial, iclass 12, count 0 2006.218.07:36:29.83#ibcon#enter sib2, iclass 12, count 0 2006.218.07:36:29.83#ibcon#flushed, iclass 12, count 0 2006.218.07:36:29.83#ibcon#about to write, iclass 12, count 0 2006.218.07:36:29.83#ibcon#wrote, iclass 12, count 0 2006.218.07:36:29.83#ibcon#about to read 3, iclass 12, count 0 2006.218.07:36:29.85#ibcon#read 3, iclass 12, count 0 2006.218.07:36:29.85#ibcon#about to read 4, iclass 12, count 0 2006.218.07:36:29.85#ibcon#read 4, iclass 12, count 0 2006.218.07:36:29.85#ibcon#about to read 5, iclass 12, count 0 2006.218.07:36:29.85#ibcon#read 5, iclass 12, count 0 2006.218.07:36:29.85#ibcon#about to read 6, iclass 12, count 0 2006.218.07:36:29.85#ibcon#read 6, iclass 12, count 0 2006.218.07:36:29.85#ibcon#end of sib2, iclass 12, count 0 2006.218.07:36:29.85#ibcon#*mode == 0, iclass 12, count 0 2006.218.07:36:29.85#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.218.07:36:29.85#ibcon#[25=USB\r\n] 2006.218.07:36:29.85#ibcon#*before write, iclass 12, count 0 2006.218.07:36:29.85#ibcon#enter sib2, iclass 12, count 0 2006.218.07:36:29.85#ibcon#flushed, iclass 12, count 0 2006.218.07:36:29.85#ibcon#about to write, iclass 12, count 0 2006.218.07:36:29.85#ibcon#wrote, iclass 12, count 0 2006.218.07:36:29.85#ibcon#about to read 3, iclass 12, count 0 2006.218.07:36:29.88#ibcon#read 3, iclass 12, count 0 2006.218.07:36:29.88#ibcon#about to read 4, iclass 12, count 0 2006.218.07:36:29.88#ibcon#read 4, iclass 12, count 0 2006.218.07:36:29.88#ibcon#about to read 5, iclass 12, count 0 2006.218.07:36:29.88#ibcon#read 5, iclass 12, count 0 2006.218.07:36:29.88#ibcon#about to read 6, iclass 12, count 0 2006.218.07:36:29.88#ibcon#read 6, iclass 12, count 0 2006.218.07:36:29.88#ibcon#end of sib2, iclass 12, count 0 2006.218.07:36:29.88#ibcon#*after write, iclass 12, count 0 2006.218.07:36:29.88#ibcon#*before return 0, iclass 12, count 0 2006.218.07:36:29.88#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.218.07:36:29.88#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.218.07:36:29.88#ibcon#about to clear, iclass 12 cls_cnt 0 2006.218.07:36:29.88#ibcon#cleared, iclass 12 cls_cnt 0 2006.218.07:36:29.88$vc4f8/valo=7,832.99 2006.218.07:36:29.88#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.218.07:36:29.88#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.218.07:36:29.88#ibcon#ireg 17 cls_cnt 0 2006.218.07:36:29.88#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.218.07:36:29.88#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.218.07:36:29.88#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.218.07:36:29.88#ibcon#enter wrdev, iclass 14, count 0 2006.218.07:36:29.88#ibcon#first serial, iclass 14, count 0 2006.218.07:36:29.88#ibcon#enter sib2, iclass 14, count 0 2006.218.07:36:29.88#ibcon#flushed, iclass 14, count 0 2006.218.07:36:29.88#ibcon#about to write, iclass 14, count 0 2006.218.07:36:29.88#ibcon#wrote, iclass 14, count 0 2006.218.07:36:29.88#ibcon#about to read 3, iclass 14, count 0 2006.218.07:36:29.90#ibcon#read 3, iclass 14, count 0 2006.218.07:36:29.90#ibcon#about to read 4, iclass 14, count 0 2006.218.07:36:29.90#ibcon#read 4, iclass 14, count 0 2006.218.07:36:29.90#ibcon#about to read 5, iclass 14, count 0 2006.218.07:36:29.90#ibcon#read 5, iclass 14, count 0 2006.218.07:36:29.90#ibcon#about to read 6, iclass 14, count 0 2006.218.07:36:29.90#ibcon#read 6, iclass 14, count 0 2006.218.07:36:29.90#ibcon#end of sib2, iclass 14, count 0 2006.218.07:36:29.90#ibcon#*mode == 0, iclass 14, count 0 2006.218.07:36:29.90#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.218.07:36:29.90#ibcon#[26=FRQ=07,832.99\r\n] 2006.218.07:36:29.90#ibcon#*before write, iclass 14, count 0 2006.218.07:36:29.90#ibcon#enter sib2, iclass 14, count 0 2006.218.07:36:29.90#ibcon#flushed, iclass 14, count 0 2006.218.07:36:29.90#ibcon#about to write, iclass 14, count 0 2006.218.07:36:29.90#ibcon#wrote, iclass 14, count 0 2006.218.07:36:29.90#ibcon#about to read 3, iclass 14, count 0 2006.218.07:36:29.94#ibcon#read 3, iclass 14, count 0 2006.218.07:36:29.94#ibcon#about to read 4, iclass 14, count 0 2006.218.07:36:29.94#ibcon#read 4, iclass 14, count 0 2006.218.07:36:29.94#ibcon#about to read 5, iclass 14, count 0 2006.218.07:36:29.94#ibcon#read 5, iclass 14, count 0 2006.218.07:36:29.94#ibcon#about to read 6, iclass 14, count 0 2006.218.07:36:29.94#ibcon#read 6, iclass 14, count 0 2006.218.07:36:29.94#ibcon#end of sib2, iclass 14, count 0 2006.218.07:36:29.94#ibcon#*after write, iclass 14, count 0 2006.218.07:36:29.94#ibcon#*before return 0, iclass 14, count 0 2006.218.07:36:29.94#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.218.07:36:29.94#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.218.07:36:29.94#ibcon#about to clear, iclass 14 cls_cnt 0 2006.218.07:36:29.94#ibcon#cleared, iclass 14 cls_cnt 0 2006.218.07:36:29.94$vc4f8/va=7,6 2006.218.07:36:29.94#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.218.07:36:29.94#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.218.07:36:29.94#ibcon#ireg 11 cls_cnt 2 2006.218.07:36:29.94#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.218.07:36:30.00#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.218.07:36:30.00#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.218.07:36:30.00#ibcon#enter wrdev, iclass 16, count 2 2006.218.07:36:30.00#ibcon#first serial, iclass 16, count 2 2006.218.07:36:30.00#ibcon#enter sib2, iclass 16, count 2 2006.218.07:36:30.00#ibcon#flushed, iclass 16, count 2 2006.218.07:36:30.00#ibcon#about to write, iclass 16, count 2 2006.218.07:36:30.00#ibcon#wrote, iclass 16, count 2 2006.218.07:36:30.00#ibcon#about to read 3, iclass 16, count 2 2006.218.07:36:30.02#ibcon#read 3, iclass 16, count 2 2006.218.07:36:30.02#ibcon#about to read 4, iclass 16, count 2 2006.218.07:36:30.02#ibcon#read 4, iclass 16, count 2 2006.218.07:36:30.02#ibcon#about to read 5, iclass 16, count 2 2006.218.07:36:30.02#ibcon#read 5, iclass 16, count 2 2006.218.07:36:30.02#ibcon#about to read 6, iclass 16, count 2 2006.218.07:36:30.02#ibcon#read 6, iclass 16, count 2 2006.218.07:36:30.02#ibcon#end of sib2, iclass 16, count 2 2006.218.07:36:30.02#ibcon#*mode == 0, iclass 16, count 2 2006.218.07:36:30.02#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.218.07:36:30.02#ibcon#[25=AT07-06\r\n] 2006.218.07:36:30.02#ibcon#*before write, iclass 16, count 2 2006.218.07:36:30.02#ibcon#enter sib2, iclass 16, count 2 2006.218.07:36:30.02#ibcon#flushed, iclass 16, count 2 2006.218.07:36:30.02#ibcon#about to write, iclass 16, count 2 2006.218.07:36:30.02#ibcon#wrote, iclass 16, count 2 2006.218.07:36:30.02#ibcon#about to read 3, iclass 16, count 2 2006.218.07:36:30.05#ibcon#read 3, iclass 16, count 2 2006.218.07:36:30.05#ibcon#about to read 4, iclass 16, count 2 2006.218.07:36:30.05#ibcon#read 4, iclass 16, count 2 2006.218.07:36:30.05#ibcon#about to read 5, iclass 16, count 2 2006.218.07:36:30.05#ibcon#read 5, iclass 16, count 2 2006.218.07:36:30.05#ibcon#about to read 6, iclass 16, count 2 2006.218.07:36:30.05#ibcon#read 6, iclass 16, count 2 2006.218.07:36:30.05#ibcon#end of sib2, iclass 16, count 2 2006.218.07:36:30.05#ibcon#*after write, iclass 16, count 2 2006.218.07:36:30.05#ibcon#*before return 0, iclass 16, count 2 2006.218.07:36:30.05#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.218.07:36:30.05#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.218.07:36:30.05#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.218.07:36:30.05#ibcon#ireg 7 cls_cnt 0 2006.218.07:36:30.05#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.218.07:36:30.17#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.218.07:36:30.17#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.218.07:36:30.17#ibcon#enter wrdev, iclass 16, count 0 2006.218.07:36:30.17#ibcon#first serial, iclass 16, count 0 2006.218.07:36:30.17#ibcon#enter sib2, iclass 16, count 0 2006.218.07:36:30.17#ibcon#flushed, iclass 16, count 0 2006.218.07:36:30.17#ibcon#about to write, iclass 16, count 0 2006.218.07:36:30.17#ibcon#wrote, iclass 16, count 0 2006.218.07:36:30.17#ibcon#about to read 3, iclass 16, count 0 2006.218.07:36:30.19#ibcon#read 3, iclass 16, count 0 2006.218.07:36:30.19#ibcon#about to read 4, iclass 16, count 0 2006.218.07:36:30.19#ibcon#read 4, iclass 16, count 0 2006.218.07:36:30.19#ibcon#about to read 5, iclass 16, count 0 2006.218.07:36:30.19#ibcon#read 5, iclass 16, count 0 2006.218.07:36:30.19#ibcon#about to read 6, iclass 16, count 0 2006.218.07:36:30.19#ibcon#read 6, iclass 16, count 0 2006.218.07:36:30.19#ibcon#end of sib2, iclass 16, count 0 2006.218.07:36:30.19#ibcon#*mode == 0, iclass 16, count 0 2006.218.07:36:30.19#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.218.07:36:30.19#ibcon#[25=USB\r\n] 2006.218.07:36:30.19#ibcon#*before write, iclass 16, count 0 2006.218.07:36:30.19#ibcon#enter sib2, iclass 16, count 0 2006.218.07:36:30.19#ibcon#flushed, iclass 16, count 0 2006.218.07:36:30.19#ibcon#about to write, iclass 16, count 0 2006.218.07:36:30.19#ibcon#wrote, iclass 16, count 0 2006.218.07:36:30.19#ibcon#about to read 3, iclass 16, count 0 2006.218.07:36:30.22#ibcon#read 3, iclass 16, count 0 2006.218.07:36:30.22#ibcon#about to read 4, iclass 16, count 0 2006.218.07:36:30.22#ibcon#read 4, iclass 16, count 0 2006.218.07:36:30.22#ibcon#about to read 5, iclass 16, count 0 2006.218.07:36:30.22#ibcon#read 5, iclass 16, count 0 2006.218.07:36:30.22#ibcon#about to read 6, iclass 16, count 0 2006.218.07:36:30.22#ibcon#read 6, iclass 16, count 0 2006.218.07:36:30.22#ibcon#end of sib2, iclass 16, count 0 2006.218.07:36:30.22#ibcon#*after write, iclass 16, count 0 2006.218.07:36:30.22#ibcon#*before return 0, iclass 16, count 0 2006.218.07:36:30.22#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.218.07:36:30.22#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.218.07:36:30.22#ibcon#about to clear, iclass 16 cls_cnt 0 2006.218.07:36:30.22#ibcon#cleared, iclass 16 cls_cnt 0 2006.218.07:36:30.22$vc4f8/valo=8,852.99 2006.218.07:36:30.22#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.218.07:36:30.22#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.218.07:36:30.22#ibcon#ireg 17 cls_cnt 0 2006.218.07:36:30.22#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.218.07:36:30.22#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.218.07:36:30.22#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.218.07:36:30.22#ibcon#enter wrdev, iclass 18, count 0 2006.218.07:36:30.22#ibcon#first serial, iclass 18, count 0 2006.218.07:36:30.22#ibcon#enter sib2, iclass 18, count 0 2006.218.07:36:30.22#ibcon#flushed, iclass 18, count 0 2006.218.07:36:30.22#ibcon#about to write, iclass 18, count 0 2006.218.07:36:30.22#ibcon#wrote, iclass 18, count 0 2006.218.07:36:30.22#ibcon#about to read 3, iclass 18, count 0 2006.218.07:36:30.24#ibcon#read 3, iclass 18, count 0 2006.218.07:36:30.24#ibcon#about to read 4, iclass 18, count 0 2006.218.07:36:30.24#ibcon#read 4, iclass 18, count 0 2006.218.07:36:30.24#ibcon#about to read 5, iclass 18, count 0 2006.218.07:36:30.24#ibcon#read 5, iclass 18, count 0 2006.218.07:36:30.24#ibcon#about to read 6, iclass 18, count 0 2006.218.07:36:30.24#ibcon#read 6, iclass 18, count 0 2006.218.07:36:30.24#ibcon#end of sib2, iclass 18, count 0 2006.218.07:36:30.24#ibcon#*mode == 0, iclass 18, count 0 2006.218.07:36:30.24#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.218.07:36:30.24#ibcon#[26=FRQ=08,852.99\r\n] 2006.218.07:36:30.24#ibcon#*before write, iclass 18, count 0 2006.218.07:36:30.24#ibcon#enter sib2, iclass 18, count 0 2006.218.07:36:30.24#ibcon#flushed, iclass 18, count 0 2006.218.07:36:30.24#ibcon#about to write, iclass 18, count 0 2006.218.07:36:30.24#ibcon#wrote, iclass 18, count 0 2006.218.07:36:30.24#ibcon#about to read 3, iclass 18, count 0 2006.218.07:36:30.28#ibcon#read 3, iclass 18, count 0 2006.218.07:36:30.28#ibcon#about to read 4, iclass 18, count 0 2006.218.07:36:30.28#ibcon#read 4, iclass 18, count 0 2006.218.07:36:30.28#ibcon#about to read 5, iclass 18, count 0 2006.218.07:36:30.28#ibcon#read 5, iclass 18, count 0 2006.218.07:36:30.28#ibcon#about to read 6, iclass 18, count 0 2006.218.07:36:30.28#ibcon#read 6, iclass 18, count 0 2006.218.07:36:30.28#ibcon#end of sib2, iclass 18, count 0 2006.218.07:36:30.28#ibcon#*after write, iclass 18, count 0 2006.218.07:36:30.28#ibcon#*before return 0, iclass 18, count 0 2006.218.07:36:30.28#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.218.07:36:30.28#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.218.07:36:30.28#ibcon#about to clear, iclass 18 cls_cnt 0 2006.218.07:36:30.28#ibcon#cleared, iclass 18 cls_cnt 0 2006.218.07:36:30.28$vc4f8/va=8,7 2006.218.07:36:30.28#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.218.07:36:30.28#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.218.07:36:30.28#ibcon#ireg 11 cls_cnt 2 2006.218.07:36:30.28#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.218.07:36:30.34#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.218.07:36:30.34#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.218.07:36:30.34#ibcon#enter wrdev, iclass 20, count 2 2006.218.07:36:30.34#ibcon#first serial, iclass 20, count 2 2006.218.07:36:30.34#ibcon#enter sib2, iclass 20, count 2 2006.218.07:36:30.34#ibcon#flushed, iclass 20, count 2 2006.218.07:36:30.34#ibcon#about to write, iclass 20, count 2 2006.218.07:36:30.34#ibcon#wrote, iclass 20, count 2 2006.218.07:36:30.34#ibcon#about to read 3, iclass 20, count 2 2006.218.07:36:30.36#ibcon#read 3, iclass 20, count 2 2006.218.07:36:30.36#ibcon#about to read 4, iclass 20, count 2 2006.218.07:36:30.36#ibcon#read 4, iclass 20, count 2 2006.218.07:36:30.36#ibcon#about to read 5, iclass 20, count 2 2006.218.07:36:30.36#ibcon#read 5, iclass 20, count 2 2006.218.07:36:30.36#ibcon#about to read 6, iclass 20, count 2 2006.218.07:36:30.36#ibcon#read 6, iclass 20, count 2 2006.218.07:36:30.36#ibcon#end of sib2, iclass 20, count 2 2006.218.07:36:30.36#ibcon#*mode == 0, iclass 20, count 2 2006.218.07:36:30.36#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.218.07:36:30.36#ibcon#[25=AT08-07\r\n] 2006.218.07:36:30.36#ibcon#*before write, iclass 20, count 2 2006.218.07:36:30.36#ibcon#enter sib2, iclass 20, count 2 2006.218.07:36:30.36#ibcon#flushed, iclass 20, count 2 2006.218.07:36:30.36#ibcon#about to write, iclass 20, count 2 2006.218.07:36:30.36#ibcon#wrote, iclass 20, count 2 2006.218.07:36:30.36#ibcon#about to read 3, iclass 20, count 2 2006.218.07:36:30.39#ibcon#read 3, iclass 20, count 2 2006.218.07:36:30.39#ibcon#about to read 4, iclass 20, count 2 2006.218.07:36:30.39#ibcon#read 4, iclass 20, count 2 2006.218.07:36:30.39#ibcon#about to read 5, iclass 20, count 2 2006.218.07:36:30.39#ibcon#read 5, iclass 20, count 2 2006.218.07:36:30.39#ibcon#about to read 6, iclass 20, count 2 2006.218.07:36:30.39#ibcon#read 6, iclass 20, count 2 2006.218.07:36:30.39#ibcon#end of sib2, iclass 20, count 2 2006.218.07:36:30.39#ibcon#*after write, iclass 20, count 2 2006.218.07:36:30.39#ibcon#*before return 0, iclass 20, count 2 2006.218.07:36:30.39#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.218.07:36:30.39#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.218.07:36:30.39#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.218.07:36:30.39#ibcon#ireg 7 cls_cnt 0 2006.218.07:36:30.39#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.218.07:36:30.51#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.218.07:36:30.51#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.218.07:36:30.51#ibcon#enter wrdev, iclass 20, count 0 2006.218.07:36:30.51#ibcon#first serial, iclass 20, count 0 2006.218.07:36:30.51#ibcon#enter sib2, iclass 20, count 0 2006.218.07:36:30.51#ibcon#flushed, iclass 20, count 0 2006.218.07:36:30.51#ibcon#about to write, iclass 20, count 0 2006.218.07:36:30.51#ibcon#wrote, iclass 20, count 0 2006.218.07:36:30.51#ibcon#about to read 3, iclass 20, count 0 2006.218.07:36:30.53#ibcon#read 3, iclass 20, count 0 2006.218.07:36:30.53#ibcon#about to read 4, iclass 20, count 0 2006.218.07:36:30.53#ibcon#read 4, iclass 20, count 0 2006.218.07:36:30.53#ibcon#about to read 5, iclass 20, count 0 2006.218.07:36:30.53#ibcon#read 5, iclass 20, count 0 2006.218.07:36:30.53#ibcon#about to read 6, iclass 20, count 0 2006.218.07:36:30.53#ibcon#read 6, iclass 20, count 0 2006.218.07:36:30.53#ibcon#end of sib2, iclass 20, count 0 2006.218.07:36:30.53#ibcon#*mode == 0, iclass 20, count 0 2006.218.07:36:30.53#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.218.07:36:30.53#ibcon#[25=USB\r\n] 2006.218.07:36:30.53#ibcon#*before write, iclass 20, count 0 2006.218.07:36:30.53#ibcon#enter sib2, iclass 20, count 0 2006.218.07:36:30.53#ibcon#flushed, iclass 20, count 0 2006.218.07:36:30.53#ibcon#about to write, iclass 20, count 0 2006.218.07:36:30.53#ibcon#wrote, iclass 20, count 0 2006.218.07:36:30.53#ibcon#about to read 3, iclass 20, count 0 2006.218.07:36:30.56#ibcon#read 3, iclass 20, count 0 2006.218.07:36:30.56#ibcon#about to read 4, iclass 20, count 0 2006.218.07:36:30.56#ibcon#read 4, iclass 20, count 0 2006.218.07:36:30.56#ibcon#about to read 5, iclass 20, count 0 2006.218.07:36:30.56#ibcon#read 5, iclass 20, count 0 2006.218.07:36:30.56#ibcon#about to read 6, iclass 20, count 0 2006.218.07:36:30.56#ibcon#read 6, iclass 20, count 0 2006.218.07:36:30.56#ibcon#end of sib2, iclass 20, count 0 2006.218.07:36:30.56#ibcon#*after write, iclass 20, count 0 2006.218.07:36:30.56#ibcon#*before return 0, iclass 20, count 0 2006.218.07:36:30.56#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.218.07:36:30.56#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.218.07:36:30.56#ibcon#about to clear, iclass 20 cls_cnt 0 2006.218.07:36:30.56#ibcon#cleared, iclass 20 cls_cnt 0 2006.218.07:36:30.56$vc4f8/vblo=1,632.99 2006.218.07:36:30.56#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.218.07:36:30.56#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.218.07:36:30.56#ibcon#ireg 17 cls_cnt 0 2006.218.07:36:30.56#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.218.07:36:30.56#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.218.07:36:30.56#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.218.07:36:30.56#ibcon#enter wrdev, iclass 22, count 0 2006.218.07:36:30.56#ibcon#first serial, iclass 22, count 0 2006.218.07:36:30.56#ibcon#enter sib2, iclass 22, count 0 2006.218.07:36:30.56#ibcon#flushed, iclass 22, count 0 2006.218.07:36:30.56#ibcon#about to write, iclass 22, count 0 2006.218.07:36:30.56#ibcon#wrote, iclass 22, count 0 2006.218.07:36:30.56#ibcon#about to read 3, iclass 22, count 0 2006.218.07:36:30.58#ibcon#read 3, iclass 22, count 0 2006.218.07:36:30.58#ibcon#about to read 4, iclass 22, count 0 2006.218.07:36:30.58#ibcon#read 4, iclass 22, count 0 2006.218.07:36:30.58#ibcon#about to read 5, iclass 22, count 0 2006.218.07:36:30.58#ibcon#read 5, iclass 22, count 0 2006.218.07:36:30.58#ibcon#about to read 6, iclass 22, count 0 2006.218.07:36:30.58#ibcon#read 6, iclass 22, count 0 2006.218.07:36:30.58#ibcon#end of sib2, iclass 22, count 0 2006.218.07:36:30.58#ibcon#*mode == 0, iclass 22, count 0 2006.218.07:36:30.58#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.218.07:36:30.58#ibcon#[28=FRQ=01,632.99\r\n] 2006.218.07:36:30.58#ibcon#*before write, iclass 22, count 0 2006.218.07:36:30.58#ibcon#enter sib2, iclass 22, count 0 2006.218.07:36:30.58#ibcon#flushed, iclass 22, count 0 2006.218.07:36:30.58#ibcon#about to write, iclass 22, count 0 2006.218.07:36:30.58#ibcon#wrote, iclass 22, count 0 2006.218.07:36:30.58#ibcon#about to read 3, iclass 22, count 0 2006.218.07:36:30.62#ibcon#read 3, iclass 22, count 0 2006.218.07:36:30.62#ibcon#about to read 4, iclass 22, count 0 2006.218.07:36:30.62#ibcon#read 4, iclass 22, count 0 2006.218.07:36:30.62#ibcon#about to read 5, iclass 22, count 0 2006.218.07:36:30.62#ibcon#read 5, iclass 22, count 0 2006.218.07:36:30.62#ibcon#about to read 6, iclass 22, count 0 2006.218.07:36:30.62#ibcon#read 6, iclass 22, count 0 2006.218.07:36:30.62#ibcon#end of sib2, iclass 22, count 0 2006.218.07:36:30.62#ibcon#*after write, iclass 22, count 0 2006.218.07:36:30.62#ibcon#*before return 0, iclass 22, count 0 2006.218.07:36:30.62#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.218.07:36:30.62#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.218.07:36:30.62#ibcon#about to clear, iclass 22 cls_cnt 0 2006.218.07:36:30.62#ibcon#cleared, iclass 22 cls_cnt 0 2006.218.07:36:30.62$vc4f8/vb=1,4 2006.218.07:36:30.62#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.218.07:36:30.62#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.218.07:36:30.62#ibcon#ireg 11 cls_cnt 2 2006.218.07:36:30.62#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.218.07:36:30.62#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.218.07:36:30.62#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.218.07:36:30.62#ibcon#enter wrdev, iclass 24, count 2 2006.218.07:36:30.62#ibcon#first serial, iclass 24, count 2 2006.218.07:36:30.62#ibcon#enter sib2, iclass 24, count 2 2006.218.07:36:30.62#ibcon#flushed, iclass 24, count 2 2006.218.07:36:30.62#ibcon#about to write, iclass 24, count 2 2006.218.07:36:30.62#ibcon#wrote, iclass 24, count 2 2006.218.07:36:30.62#ibcon#about to read 3, iclass 24, count 2 2006.218.07:36:30.64#ibcon#read 3, iclass 24, count 2 2006.218.07:36:30.64#ibcon#about to read 4, iclass 24, count 2 2006.218.07:36:30.64#ibcon#read 4, iclass 24, count 2 2006.218.07:36:30.64#ibcon#about to read 5, iclass 24, count 2 2006.218.07:36:30.64#ibcon#read 5, iclass 24, count 2 2006.218.07:36:30.64#ibcon#about to read 6, iclass 24, count 2 2006.218.07:36:30.64#ibcon#read 6, iclass 24, count 2 2006.218.07:36:30.64#ibcon#end of sib2, iclass 24, count 2 2006.218.07:36:30.64#ibcon#*mode == 0, iclass 24, count 2 2006.218.07:36:30.64#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.218.07:36:30.64#ibcon#[27=AT01-04\r\n] 2006.218.07:36:30.64#ibcon#*before write, iclass 24, count 2 2006.218.07:36:30.64#ibcon#enter sib2, iclass 24, count 2 2006.218.07:36:30.64#ibcon#flushed, iclass 24, count 2 2006.218.07:36:30.64#ibcon#about to write, iclass 24, count 2 2006.218.07:36:30.64#ibcon#wrote, iclass 24, count 2 2006.218.07:36:30.64#ibcon#about to read 3, iclass 24, count 2 2006.218.07:36:30.67#ibcon#read 3, iclass 24, count 2 2006.218.07:36:30.67#ibcon#about to read 4, iclass 24, count 2 2006.218.07:36:30.67#ibcon#read 4, iclass 24, count 2 2006.218.07:36:30.67#ibcon#about to read 5, iclass 24, count 2 2006.218.07:36:30.67#ibcon#read 5, iclass 24, count 2 2006.218.07:36:30.67#ibcon#about to read 6, iclass 24, count 2 2006.218.07:36:30.67#ibcon#read 6, iclass 24, count 2 2006.218.07:36:30.67#ibcon#end of sib2, iclass 24, count 2 2006.218.07:36:30.67#ibcon#*after write, iclass 24, count 2 2006.218.07:36:30.67#ibcon#*before return 0, iclass 24, count 2 2006.218.07:36:30.67#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.218.07:36:30.67#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.218.07:36:30.67#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.218.07:36:30.67#ibcon#ireg 7 cls_cnt 0 2006.218.07:36:30.67#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.218.07:36:30.79#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.218.07:36:30.79#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.218.07:36:30.79#ibcon#enter wrdev, iclass 24, count 0 2006.218.07:36:30.79#ibcon#first serial, iclass 24, count 0 2006.218.07:36:30.79#ibcon#enter sib2, iclass 24, count 0 2006.218.07:36:30.79#ibcon#flushed, iclass 24, count 0 2006.218.07:36:30.79#ibcon#about to write, iclass 24, count 0 2006.218.07:36:30.79#ibcon#wrote, iclass 24, count 0 2006.218.07:36:30.79#ibcon#about to read 3, iclass 24, count 0 2006.218.07:36:30.81#ibcon#read 3, iclass 24, count 0 2006.218.07:36:30.81#ibcon#about to read 4, iclass 24, count 0 2006.218.07:36:30.81#ibcon#read 4, iclass 24, count 0 2006.218.07:36:30.81#ibcon#about to read 5, iclass 24, count 0 2006.218.07:36:30.81#ibcon#read 5, iclass 24, count 0 2006.218.07:36:30.81#ibcon#about to read 6, iclass 24, count 0 2006.218.07:36:30.81#ibcon#read 6, iclass 24, count 0 2006.218.07:36:30.81#ibcon#end of sib2, iclass 24, count 0 2006.218.07:36:30.81#ibcon#*mode == 0, iclass 24, count 0 2006.218.07:36:30.81#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.218.07:36:30.81#ibcon#[27=USB\r\n] 2006.218.07:36:30.81#ibcon#*before write, iclass 24, count 0 2006.218.07:36:30.81#ibcon#enter sib2, iclass 24, count 0 2006.218.07:36:30.81#ibcon#flushed, iclass 24, count 0 2006.218.07:36:30.81#ibcon#about to write, iclass 24, count 0 2006.218.07:36:30.81#ibcon#wrote, iclass 24, count 0 2006.218.07:36:30.81#ibcon#about to read 3, iclass 24, count 0 2006.218.07:36:30.84#ibcon#read 3, iclass 24, count 0 2006.218.07:36:30.84#ibcon#about to read 4, iclass 24, count 0 2006.218.07:36:30.84#ibcon#read 4, iclass 24, count 0 2006.218.07:36:30.84#ibcon#about to read 5, iclass 24, count 0 2006.218.07:36:30.84#ibcon#read 5, iclass 24, count 0 2006.218.07:36:30.84#ibcon#about to read 6, iclass 24, count 0 2006.218.07:36:30.84#ibcon#read 6, iclass 24, count 0 2006.218.07:36:30.84#ibcon#end of sib2, iclass 24, count 0 2006.218.07:36:30.84#ibcon#*after write, iclass 24, count 0 2006.218.07:36:30.84#ibcon#*before return 0, iclass 24, count 0 2006.218.07:36:30.84#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.218.07:36:30.84#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.218.07:36:30.84#ibcon#about to clear, iclass 24 cls_cnt 0 2006.218.07:36:30.84#ibcon#cleared, iclass 24 cls_cnt 0 2006.218.07:36:30.84$vc4f8/vblo=2,640.99 2006.218.07:36:30.84#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.218.07:36:30.84#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.218.07:36:30.84#ibcon#ireg 17 cls_cnt 0 2006.218.07:36:30.84#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.218.07:36:30.84#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.218.07:36:30.84#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.218.07:36:30.84#ibcon#enter wrdev, iclass 26, count 0 2006.218.07:36:30.84#ibcon#first serial, iclass 26, count 0 2006.218.07:36:30.84#ibcon#enter sib2, iclass 26, count 0 2006.218.07:36:30.84#ibcon#flushed, iclass 26, count 0 2006.218.07:36:30.84#ibcon#about to write, iclass 26, count 0 2006.218.07:36:30.84#ibcon#wrote, iclass 26, count 0 2006.218.07:36:30.84#ibcon#about to read 3, iclass 26, count 0 2006.218.07:36:30.86#ibcon#read 3, iclass 26, count 0 2006.218.07:36:30.86#ibcon#about to read 4, iclass 26, count 0 2006.218.07:36:30.86#ibcon#read 4, iclass 26, count 0 2006.218.07:36:30.86#ibcon#about to read 5, iclass 26, count 0 2006.218.07:36:30.86#ibcon#read 5, iclass 26, count 0 2006.218.07:36:30.86#ibcon#about to read 6, iclass 26, count 0 2006.218.07:36:30.86#ibcon#read 6, iclass 26, count 0 2006.218.07:36:30.86#ibcon#end of sib2, iclass 26, count 0 2006.218.07:36:30.86#ibcon#*mode == 0, iclass 26, count 0 2006.218.07:36:30.86#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.218.07:36:30.86#ibcon#[28=FRQ=02,640.99\r\n] 2006.218.07:36:30.86#ibcon#*before write, iclass 26, count 0 2006.218.07:36:30.86#ibcon#enter sib2, iclass 26, count 0 2006.218.07:36:30.86#ibcon#flushed, iclass 26, count 0 2006.218.07:36:30.86#ibcon#about to write, iclass 26, count 0 2006.218.07:36:30.86#ibcon#wrote, iclass 26, count 0 2006.218.07:36:30.86#ibcon#about to read 3, iclass 26, count 0 2006.218.07:36:30.90#ibcon#read 3, iclass 26, count 0 2006.218.07:36:30.90#ibcon#about to read 4, iclass 26, count 0 2006.218.07:36:30.90#ibcon#read 4, iclass 26, count 0 2006.218.07:36:30.90#ibcon#about to read 5, iclass 26, count 0 2006.218.07:36:30.90#ibcon#read 5, iclass 26, count 0 2006.218.07:36:30.90#ibcon#about to read 6, iclass 26, count 0 2006.218.07:36:30.90#ibcon#read 6, iclass 26, count 0 2006.218.07:36:30.90#ibcon#end of sib2, iclass 26, count 0 2006.218.07:36:30.90#ibcon#*after write, iclass 26, count 0 2006.218.07:36:30.90#ibcon#*before return 0, iclass 26, count 0 2006.218.07:36:30.90#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.218.07:36:30.90#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.218.07:36:30.90#ibcon#about to clear, iclass 26 cls_cnt 0 2006.218.07:36:30.90#ibcon#cleared, iclass 26 cls_cnt 0 2006.218.07:36:30.90$vc4f8/vb=2,4 2006.218.07:36:30.90#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.218.07:36:30.90#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.218.07:36:30.90#ibcon#ireg 11 cls_cnt 2 2006.218.07:36:30.90#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.218.07:36:30.96#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.218.07:36:30.96#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.218.07:36:30.96#ibcon#enter wrdev, iclass 28, count 2 2006.218.07:36:30.96#ibcon#first serial, iclass 28, count 2 2006.218.07:36:30.96#ibcon#enter sib2, iclass 28, count 2 2006.218.07:36:30.96#ibcon#flushed, iclass 28, count 2 2006.218.07:36:30.96#ibcon#about to write, iclass 28, count 2 2006.218.07:36:30.96#ibcon#wrote, iclass 28, count 2 2006.218.07:36:30.96#ibcon#about to read 3, iclass 28, count 2 2006.218.07:36:30.98#ibcon#read 3, iclass 28, count 2 2006.218.07:36:30.98#ibcon#about to read 4, iclass 28, count 2 2006.218.07:36:30.98#ibcon#read 4, iclass 28, count 2 2006.218.07:36:30.98#ibcon#about to read 5, iclass 28, count 2 2006.218.07:36:30.98#ibcon#read 5, iclass 28, count 2 2006.218.07:36:30.98#ibcon#about to read 6, iclass 28, count 2 2006.218.07:36:30.98#ibcon#read 6, iclass 28, count 2 2006.218.07:36:30.98#ibcon#end of sib2, iclass 28, count 2 2006.218.07:36:30.98#ibcon#*mode == 0, iclass 28, count 2 2006.218.07:36:30.98#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.218.07:36:30.98#ibcon#[27=AT02-04\r\n] 2006.218.07:36:30.98#ibcon#*before write, iclass 28, count 2 2006.218.07:36:30.98#ibcon#enter sib2, iclass 28, count 2 2006.218.07:36:30.98#ibcon#flushed, iclass 28, count 2 2006.218.07:36:30.98#ibcon#about to write, iclass 28, count 2 2006.218.07:36:30.98#ibcon#wrote, iclass 28, count 2 2006.218.07:36:30.98#ibcon#about to read 3, iclass 28, count 2 2006.218.07:36:31.01#ibcon#read 3, iclass 28, count 2 2006.218.07:36:31.01#ibcon#about to read 4, iclass 28, count 2 2006.218.07:36:31.01#ibcon#read 4, iclass 28, count 2 2006.218.07:36:31.01#ibcon#about to read 5, iclass 28, count 2 2006.218.07:36:31.01#ibcon#read 5, iclass 28, count 2 2006.218.07:36:31.01#ibcon#about to read 6, iclass 28, count 2 2006.218.07:36:31.01#ibcon#read 6, iclass 28, count 2 2006.218.07:36:31.01#ibcon#end of sib2, iclass 28, count 2 2006.218.07:36:31.01#ibcon#*after write, iclass 28, count 2 2006.218.07:36:31.01#ibcon#*before return 0, iclass 28, count 2 2006.218.07:36:31.01#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.218.07:36:31.01#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.218.07:36:31.01#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.218.07:36:31.01#ibcon#ireg 7 cls_cnt 0 2006.218.07:36:31.01#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.218.07:36:31.13#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.218.07:36:31.13#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.218.07:36:31.13#ibcon#enter wrdev, iclass 28, count 0 2006.218.07:36:31.13#ibcon#first serial, iclass 28, count 0 2006.218.07:36:31.13#ibcon#enter sib2, iclass 28, count 0 2006.218.07:36:31.13#ibcon#flushed, iclass 28, count 0 2006.218.07:36:31.13#ibcon#about to write, iclass 28, count 0 2006.218.07:36:31.13#ibcon#wrote, iclass 28, count 0 2006.218.07:36:31.13#ibcon#about to read 3, iclass 28, count 0 2006.218.07:36:31.15#ibcon#read 3, iclass 28, count 0 2006.218.07:36:31.15#ibcon#about to read 4, iclass 28, count 0 2006.218.07:36:31.15#ibcon#read 4, iclass 28, count 0 2006.218.07:36:31.15#ibcon#about to read 5, iclass 28, count 0 2006.218.07:36:31.15#ibcon#read 5, iclass 28, count 0 2006.218.07:36:31.15#ibcon#about to read 6, iclass 28, count 0 2006.218.07:36:31.15#ibcon#read 6, iclass 28, count 0 2006.218.07:36:31.15#ibcon#end of sib2, iclass 28, count 0 2006.218.07:36:31.15#ibcon#*mode == 0, iclass 28, count 0 2006.218.07:36:31.15#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.218.07:36:31.15#ibcon#[27=USB\r\n] 2006.218.07:36:31.15#ibcon#*before write, iclass 28, count 0 2006.218.07:36:31.15#ibcon#enter sib2, iclass 28, count 0 2006.218.07:36:31.15#ibcon#flushed, iclass 28, count 0 2006.218.07:36:31.15#ibcon#about to write, iclass 28, count 0 2006.218.07:36:31.15#ibcon#wrote, iclass 28, count 0 2006.218.07:36:31.15#ibcon#about to read 3, iclass 28, count 0 2006.218.07:36:31.18#ibcon#read 3, iclass 28, count 0 2006.218.07:36:31.18#ibcon#about to read 4, iclass 28, count 0 2006.218.07:36:31.18#ibcon#read 4, iclass 28, count 0 2006.218.07:36:31.18#ibcon#about to read 5, iclass 28, count 0 2006.218.07:36:31.18#ibcon#read 5, iclass 28, count 0 2006.218.07:36:31.18#ibcon#about to read 6, iclass 28, count 0 2006.218.07:36:31.18#ibcon#read 6, iclass 28, count 0 2006.218.07:36:31.18#ibcon#end of sib2, iclass 28, count 0 2006.218.07:36:31.18#ibcon#*after write, iclass 28, count 0 2006.218.07:36:31.18#ibcon#*before return 0, iclass 28, count 0 2006.218.07:36:31.18#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.218.07:36:31.18#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.218.07:36:31.18#ibcon#about to clear, iclass 28 cls_cnt 0 2006.218.07:36:31.18#ibcon#cleared, iclass 28 cls_cnt 0 2006.218.07:36:31.18$vc4f8/vblo=3,656.99 2006.218.07:36:31.18#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.218.07:36:31.18#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.218.07:36:31.18#ibcon#ireg 17 cls_cnt 0 2006.218.07:36:31.18#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.218.07:36:31.18#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.218.07:36:31.18#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.218.07:36:31.18#ibcon#enter wrdev, iclass 30, count 0 2006.218.07:36:31.18#ibcon#first serial, iclass 30, count 0 2006.218.07:36:31.18#ibcon#enter sib2, iclass 30, count 0 2006.218.07:36:31.18#ibcon#flushed, iclass 30, count 0 2006.218.07:36:31.18#ibcon#about to write, iclass 30, count 0 2006.218.07:36:31.18#ibcon#wrote, iclass 30, count 0 2006.218.07:36:31.18#ibcon#about to read 3, iclass 30, count 0 2006.218.07:36:31.20#ibcon#read 3, iclass 30, count 0 2006.218.07:36:31.20#ibcon#about to read 4, iclass 30, count 0 2006.218.07:36:31.20#ibcon#read 4, iclass 30, count 0 2006.218.07:36:31.20#ibcon#about to read 5, iclass 30, count 0 2006.218.07:36:31.20#ibcon#read 5, iclass 30, count 0 2006.218.07:36:31.20#ibcon#about to read 6, iclass 30, count 0 2006.218.07:36:31.20#ibcon#read 6, iclass 30, count 0 2006.218.07:36:31.20#ibcon#end of sib2, iclass 30, count 0 2006.218.07:36:31.20#ibcon#*mode == 0, iclass 30, count 0 2006.218.07:36:31.20#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.218.07:36:31.20#ibcon#[28=FRQ=03,656.99\r\n] 2006.218.07:36:31.20#ibcon#*before write, iclass 30, count 0 2006.218.07:36:31.20#ibcon#enter sib2, iclass 30, count 0 2006.218.07:36:31.20#ibcon#flushed, iclass 30, count 0 2006.218.07:36:31.20#ibcon#about to write, iclass 30, count 0 2006.218.07:36:31.20#ibcon#wrote, iclass 30, count 0 2006.218.07:36:31.20#ibcon#about to read 3, iclass 30, count 0 2006.218.07:36:31.24#ibcon#read 3, iclass 30, count 0 2006.218.07:36:31.24#ibcon#about to read 4, iclass 30, count 0 2006.218.07:36:31.24#ibcon#read 4, iclass 30, count 0 2006.218.07:36:31.24#ibcon#about to read 5, iclass 30, count 0 2006.218.07:36:31.24#ibcon#read 5, iclass 30, count 0 2006.218.07:36:31.24#ibcon#about to read 6, iclass 30, count 0 2006.218.07:36:31.24#ibcon#read 6, iclass 30, count 0 2006.218.07:36:31.24#ibcon#end of sib2, iclass 30, count 0 2006.218.07:36:31.24#ibcon#*after write, iclass 30, count 0 2006.218.07:36:31.24#ibcon#*before return 0, iclass 30, count 0 2006.218.07:36:31.24#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.218.07:36:31.24#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.218.07:36:31.24#ibcon#about to clear, iclass 30 cls_cnt 0 2006.218.07:36:31.24#ibcon#cleared, iclass 30 cls_cnt 0 2006.218.07:36:31.24$vc4f8/vb=3,4 2006.218.07:36:31.24#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.218.07:36:31.24#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.218.07:36:31.24#ibcon#ireg 11 cls_cnt 2 2006.218.07:36:31.24#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.218.07:36:31.30#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.218.07:36:31.30#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.218.07:36:31.30#ibcon#enter wrdev, iclass 32, count 2 2006.218.07:36:31.30#ibcon#first serial, iclass 32, count 2 2006.218.07:36:31.30#ibcon#enter sib2, iclass 32, count 2 2006.218.07:36:31.30#ibcon#flushed, iclass 32, count 2 2006.218.07:36:31.30#ibcon#about to write, iclass 32, count 2 2006.218.07:36:31.30#ibcon#wrote, iclass 32, count 2 2006.218.07:36:31.30#ibcon#about to read 3, iclass 32, count 2 2006.218.07:36:31.32#ibcon#read 3, iclass 32, count 2 2006.218.07:36:31.32#ibcon#about to read 4, iclass 32, count 2 2006.218.07:36:31.32#ibcon#read 4, iclass 32, count 2 2006.218.07:36:31.32#ibcon#about to read 5, iclass 32, count 2 2006.218.07:36:31.32#ibcon#read 5, iclass 32, count 2 2006.218.07:36:31.32#ibcon#about to read 6, iclass 32, count 2 2006.218.07:36:31.32#ibcon#read 6, iclass 32, count 2 2006.218.07:36:31.32#ibcon#end of sib2, iclass 32, count 2 2006.218.07:36:31.32#ibcon#*mode == 0, iclass 32, count 2 2006.218.07:36:31.32#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.218.07:36:31.32#ibcon#[27=AT03-04\r\n] 2006.218.07:36:31.32#ibcon#*before write, iclass 32, count 2 2006.218.07:36:31.32#ibcon#enter sib2, iclass 32, count 2 2006.218.07:36:31.32#ibcon#flushed, iclass 32, count 2 2006.218.07:36:31.32#ibcon#about to write, iclass 32, count 2 2006.218.07:36:31.32#ibcon#wrote, iclass 32, count 2 2006.218.07:36:31.32#ibcon#about to read 3, iclass 32, count 2 2006.218.07:36:31.35#ibcon#read 3, iclass 32, count 2 2006.218.07:36:31.35#ibcon#about to read 4, iclass 32, count 2 2006.218.07:36:31.35#ibcon#read 4, iclass 32, count 2 2006.218.07:36:31.35#ibcon#about to read 5, iclass 32, count 2 2006.218.07:36:31.35#ibcon#read 5, iclass 32, count 2 2006.218.07:36:31.35#ibcon#about to read 6, iclass 32, count 2 2006.218.07:36:31.35#ibcon#read 6, iclass 32, count 2 2006.218.07:36:31.35#ibcon#end of sib2, iclass 32, count 2 2006.218.07:36:31.35#ibcon#*after write, iclass 32, count 2 2006.218.07:36:31.35#ibcon#*before return 0, iclass 32, count 2 2006.218.07:36:31.35#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.218.07:36:31.35#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.218.07:36:31.35#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.218.07:36:31.35#ibcon#ireg 7 cls_cnt 0 2006.218.07:36:31.35#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.218.07:36:31.47#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.218.07:36:31.47#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.218.07:36:31.47#ibcon#enter wrdev, iclass 32, count 0 2006.218.07:36:31.47#ibcon#first serial, iclass 32, count 0 2006.218.07:36:31.47#ibcon#enter sib2, iclass 32, count 0 2006.218.07:36:31.47#ibcon#flushed, iclass 32, count 0 2006.218.07:36:31.47#ibcon#about to write, iclass 32, count 0 2006.218.07:36:31.47#ibcon#wrote, iclass 32, count 0 2006.218.07:36:31.47#ibcon#about to read 3, iclass 32, count 0 2006.218.07:36:31.49#ibcon#read 3, iclass 32, count 0 2006.218.07:36:31.49#ibcon#about to read 4, iclass 32, count 0 2006.218.07:36:31.49#ibcon#read 4, iclass 32, count 0 2006.218.07:36:31.49#ibcon#about to read 5, iclass 32, count 0 2006.218.07:36:31.49#ibcon#read 5, iclass 32, count 0 2006.218.07:36:31.49#ibcon#about to read 6, iclass 32, count 0 2006.218.07:36:31.49#ibcon#read 6, iclass 32, count 0 2006.218.07:36:31.49#ibcon#end of sib2, iclass 32, count 0 2006.218.07:36:31.49#ibcon#*mode == 0, iclass 32, count 0 2006.218.07:36:31.49#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.218.07:36:31.49#ibcon#[27=USB\r\n] 2006.218.07:36:31.49#ibcon#*before write, iclass 32, count 0 2006.218.07:36:31.49#ibcon#enter sib2, iclass 32, count 0 2006.218.07:36:31.49#ibcon#flushed, iclass 32, count 0 2006.218.07:36:31.49#ibcon#about to write, iclass 32, count 0 2006.218.07:36:31.49#ibcon#wrote, iclass 32, count 0 2006.218.07:36:31.49#ibcon#about to read 3, iclass 32, count 0 2006.218.07:36:31.52#ibcon#read 3, iclass 32, count 0 2006.218.07:36:31.52#ibcon#about to read 4, iclass 32, count 0 2006.218.07:36:31.52#ibcon#read 4, iclass 32, count 0 2006.218.07:36:31.52#ibcon#about to read 5, iclass 32, count 0 2006.218.07:36:31.52#ibcon#read 5, iclass 32, count 0 2006.218.07:36:31.52#ibcon#about to read 6, iclass 32, count 0 2006.218.07:36:31.52#ibcon#read 6, iclass 32, count 0 2006.218.07:36:31.52#ibcon#end of sib2, iclass 32, count 0 2006.218.07:36:31.52#ibcon#*after write, iclass 32, count 0 2006.218.07:36:31.52#ibcon#*before return 0, iclass 32, count 0 2006.218.07:36:31.52#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.218.07:36:31.52#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.218.07:36:31.52#ibcon#about to clear, iclass 32 cls_cnt 0 2006.218.07:36:31.52#ibcon#cleared, iclass 32 cls_cnt 0 2006.218.07:36:31.52$vc4f8/vblo=4,712.99 2006.218.07:36:31.52#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.218.07:36:31.52#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.218.07:36:31.52#ibcon#ireg 17 cls_cnt 0 2006.218.07:36:31.52#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.218.07:36:31.52#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.218.07:36:31.52#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.218.07:36:31.52#ibcon#enter wrdev, iclass 34, count 0 2006.218.07:36:31.52#ibcon#first serial, iclass 34, count 0 2006.218.07:36:31.52#ibcon#enter sib2, iclass 34, count 0 2006.218.07:36:31.52#ibcon#flushed, iclass 34, count 0 2006.218.07:36:31.52#ibcon#about to write, iclass 34, count 0 2006.218.07:36:31.52#ibcon#wrote, iclass 34, count 0 2006.218.07:36:31.52#ibcon#about to read 3, iclass 34, count 0 2006.218.07:36:31.54#ibcon#read 3, iclass 34, count 0 2006.218.07:36:31.54#ibcon#about to read 4, iclass 34, count 0 2006.218.07:36:31.54#ibcon#read 4, iclass 34, count 0 2006.218.07:36:31.54#ibcon#about to read 5, iclass 34, count 0 2006.218.07:36:31.54#ibcon#read 5, iclass 34, count 0 2006.218.07:36:31.54#ibcon#about to read 6, iclass 34, count 0 2006.218.07:36:31.54#ibcon#read 6, iclass 34, count 0 2006.218.07:36:31.54#ibcon#end of sib2, iclass 34, count 0 2006.218.07:36:31.54#ibcon#*mode == 0, iclass 34, count 0 2006.218.07:36:31.54#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.218.07:36:31.54#ibcon#[28=FRQ=04,712.99\r\n] 2006.218.07:36:31.54#ibcon#*before write, iclass 34, count 0 2006.218.07:36:31.54#ibcon#enter sib2, iclass 34, count 0 2006.218.07:36:31.54#ibcon#flushed, iclass 34, count 0 2006.218.07:36:31.54#ibcon#about to write, iclass 34, count 0 2006.218.07:36:31.54#ibcon#wrote, iclass 34, count 0 2006.218.07:36:31.54#ibcon#about to read 3, iclass 34, count 0 2006.218.07:36:31.58#ibcon#read 3, iclass 34, count 0 2006.218.07:36:31.58#ibcon#about to read 4, iclass 34, count 0 2006.218.07:36:31.58#ibcon#read 4, iclass 34, count 0 2006.218.07:36:31.58#ibcon#about to read 5, iclass 34, count 0 2006.218.07:36:31.58#ibcon#read 5, iclass 34, count 0 2006.218.07:36:31.58#ibcon#about to read 6, iclass 34, count 0 2006.218.07:36:31.58#ibcon#read 6, iclass 34, count 0 2006.218.07:36:31.58#ibcon#end of sib2, iclass 34, count 0 2006.218.07:36:31.58#ibcon#*after write, iclass 34, count 0 2006.218.07:36:31.58#ibcon#*before return 0, iclass 34, count 0 2006.218.07:36:31.58#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.218.07:36:31.58#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.218.07:36:31.58#ibcon#about to clear, iclass 34 cls_cnt 0 2006.218.07:36:31.58#ibcon#cleared, iclass 34 cls_cnt 0 2006.218.07:36:31.58$vc4f8/vb=4,4 2006.218.07:36:31.58#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.218.07:36:31.58#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.218.07:36:31.58#ibcon#ireg 11 cls_cnt 2 2006.218.07:36:31.58#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.218.07:36:31.64#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.218.07:36:31.64#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.218.07:36:31.64#ibcon#enter wrdev, iclass 36, count 2 2006.218.07:36:31.64#ibcon#first serial, iclass 36, count 2 2006.218.07:36:31.64#ibcon#enter sib2, iclass 36, count 2 2006.218.07:36:31.64#ibcon#flushed, iclass 36, count 2 2006.218.07:36:31.64#ibcon#about to write, iclass 36, count 2 2006.218.07:36:31.64#ibcon#wrote, iclass 36, count 2 2006.218.07:36:31.64#ibcon#about to read 3, iclass 36, count 2 2006.218.07:36:31.66#ibcon#read 3, iclass 36, count 2 2006.218.07:36:31.66#ibcon#about to read 4, iclass 36, count 2 2006.218.07:36:31.66#ibcon#read 4, iclass 36, count 2 2006.218.07:36:31.66#ibcon#about to read 5, iclass 36, count 2 2006.218.07:36:31.66#ibcon#read 5, iclass 36, count 2 2006.218.07:36:31.66#ibcon#about to read 6, iclass 36, count 2 2006.218.07:36:31.66#ibcon#read 6, iclass 36, count 2 2006.218.07:36:31.66#ibcon#end of sib2, iclass 36, count 2 2006.218.07:36:31.66#ibcon#*mode == 0, iclass 36, count 2 2006.218.07:36:31.66#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.218.07:36:31.66#ibcon#[27=AT04-04\r\n] 2006.218.07:36:31.66#ibcon#*before write, iclass 36, count 2 2006.218.07:36:31.66#ibcon#enter sib2, iclass 36, count 2 2006.218.07:36:31.66#ibcon#flushed, iclass 36, count 2 2006.218.07:36:31.66#ibcon#about to write, iclass 36, count 2 2006.218.07:36:31.66#ibcon#wrote, iclass 36, count 2 2006.218.07:36:31.66#ibcon#about to read 3, iclass 36, count 2 2006.218.07:36:31.69#ibcon#read 3, iclass 36, count 2 2006.218.07:36:31.69#ibcon#about to read 4, iclass 36, count 2 2006.218.07:36:31.69#ibcon#read 4, iclass 36, count 2 2006.218.07:36:31.69#ibcon#about to read 5, iclass 36, count 2 2006.218.07:36:31.69#ibcon#read 5, iclass 36, count 2 2006.218.07:36:31.69#ibcon#about to read 6, iclass 36, count 2 2006.218.07:36:31.69#ibcon#read 6, iclass 36, count 2 2006.218.07:36:31.69#ibcon#end of sib2, iclass 36, count 2 2006.218.07:36:31.69#ibcon#*after write, iclass 36, count 2 2006.218.07:36:31.69#ibcon#*before return 0, iclass 36, count 2 2006.218.07:36:31.69#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.218.07:36:31.69#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.218.07:36:31.69#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.218.07:36:31.69#ibcon#ireg 7 cls_cnt 0 2006.218.07:36:31.69#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.218.07:36:31.81#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.218.07:36:31.81#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.218.07:36:31.81#ibcon#enter wrdev, iclass 36, count 0 2006.218.07:36:31.81#ibcon#first serial, iclass 36, count 0 2006.218.07:36:31.81#ibcon#enter sib2, iclass 36, count 0 2006.218.07:36:31.81#ibcon#flushed, iclass 36, count 0 2006.218.07:36:31.81#ibcon#about to write, iclass 36, count 0 2006.218.07:36:31.81#ibcon#wrote, iclass 36, count 0 2006.218.07:36:31.81#ibcon#about to read 3, iclass 36, count 0 2006.218.07:36:31.83#ibcon#read 3, iclass 36, count 0 2006.218.07:36:31.83#ibcon#about to read 4, iclass 36, count 0 2006.218.07:36:31.83#ibcon#read 4, iclass 36, count 0 2006.218.07:36:31.83#ibcon#about to read 5, iclass 36, count 0 2006.218.07:36:31.83#ibcon#read 5, iclass 36, count 0 2006.218.07:36:31.83#ibcon#about to read 6, iclass 36, count 0 2006.218.07:36:31.83#ibcon#read 6, iclass 36, count 0 2006.218.07:36:31.83#ibcon#end of sib2, iclass 36, count 0 2006.218.07:36:31.83#ibcon#*mode == 0, iclass 36, count 0 2006.218.07:36:31.83#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.218.07:36:31.83#ibcon#[27=USB\r\n] 2006.218.07:36:31.83#ibcon#*before write, iclass 36, count 0 2006.218.07:36:31.83#ibcon#enter sib2, iclass 36, count 0 2006.218.07:36:31.83#ibcon#flushed, iclass 36, count 0 2006.218.07:36:31.83#ibcon#about to write, iclass 36, count 0 2006.218.07:36:31.83#ibcon#wrote, iclass 36, count 0 2006.218.07:36:31.83#ibcon#about to read 3, iclass 36, count 0 2006.218.07:36:31.86#ibcon#read 3, iclass 36, count 0 2006.218.07:36:31.86#ibcon#about to read 4, iclass 36, count 0 2006.218.07:36:31.86#ibcon#read 4, iclass 36, count 0 2006.218.07:36:31.86#ibcon#about to read 5, iclass 36, count 0 2006.218.07:36:31.86#ibcon#read 5, iclass 36, count 0 2006.218.07:36:31.86#ibcon#about to read 6, iclass 36, count 0 2006.218.07:36:31.86#ibcon#read 6, iclass 36, count 0 2006.218.07:36:31.86#ibcon#end of sib2, iclass 36, count 0 2006.218.07:36:31.86#ibcon#*after write, iclass 36, count 0 2006.218.07:36:31.86#ibcon#*before return 0, iclass 36, count 0 2006.218.07:36:31.86#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.218.07:36:31.86#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.218.07:36:31.86#ibcon#about to clear, iclass 36 cls_cnt 0 2006.218.07:36:31.86#ibcon#cleared, iclass 36 cls_cnt 0 2006.218.07:36:31.86$vc4f8/vblo=5,744.99 2006.218.07:36:31.86#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.218.07:36:31.86#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.218.07:36:31.86#ibcon#ireg 17 cls_cnt 0 2006.218.07:36:31.86#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.218.07:36:31.86#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.218.07:36:31.86#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.218.07:36:31.86#ibcon#enter wrdev, iclass 38, count 0 2006.218.07:36:31.86#ibcon#first serial, iclass 38, count 0 2006.218.07:36:31.86#ibcon#enter sib2, iclass 38, count 0 2006.218.07:36:31.86#ibcon#flushed, iclass 38, count 0 2006.218.07:36:31.86#ibcon#about to write, iclass 38, count 0 2006.218.07:36:31.86#ibcon#wrote, iclass 38, count 0 2006.218.07:36:31.86#ibcon#about to read 3, iclass 38, count 0 2006.218.07:36:31.88#ibcon#read 3, iclass 38, count 0 2006.218.07:36:31.88#ibcon#about to read 4, iclass 38, count 0 2006.218.07:36:31.88#ibcon#read 4, iclass 38, count 0 2006.218.07:36:31.88#ibcon#about to read 5, iclass 38, count 0 2006.218.07:36:31.88#ibcon#read 5, iclass 38, count 0 2006.218.07:36:31.88#ibcon#about to read 6, iclass 38, count 0 2006.218.07:36:31.88#ibcon#read 6, iclass 38, count 0 2006.218.07:36:31.88#ibcon#end of sib2, iclass 38, count 0 2006.218.07:36:31.88#ibcon#*mode == 0, iclass 38, count 0 2006.218.07:36:31.88#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.218.07:36:31.88#ibcon#[28=FRQ=05,744.99\r\n] 2006.218.07:36:31.88#ibcon#*before write, iclass 38, count 0 2006.218.07:36:31.88#ibcon#enter sib2, iclass 38, count 0 2006.218.07:36:31.88#ibcon#flushed, iclass 38, count 0 2006.218.07:36:31.88#ibcon#about to write, iclass 38, count 0 2006.218.07:36:31.88#ibcon#wrote, iclass 38, count 0 2006.218.07:36:31.88#ibcon#about to read 3, iclass 38, count 0 2006.218.07:36:31.92#ibcon#read 3, iclass 38, count 0 2006.218.07:36:31.92#ibcon#about to read 4, iclass 38, count 0 2006.218.07:36:31.92#ibcon#read 4, iclass 38, count 0 2006.218.07:36:31.92#ibcon#about to read 5, iclass 38, count 0 2006.218.07:36:31.92#ibcon#read 5, iclass 38, count 0 2006.218.07:36:31.92#ibcon#about to read 6, iclass 38, count 0 2006.218.07:36:31.92#ibcon#read 6, iclass 38, count 0 2006.218.07:36:31.92#ibcon#end of sib2, iclass 38, count 0 2006.218.07:36:31.92#ibcon#*after write, iclass 38, count 0 2006.218.07:36:31.92#ibcon#*before return 0, iclass 38, count 0 2006.218.07:36:31.92#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.218.07:36:31.92#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.218.07:36:31.92#ibcon#about to clear, iclass 38 cls_cnt 0 2006.218.07:36:31.92#ibcon#cleared, iclass 38 cls_cnt 0 2006.218.07:36:31.92$vc4f8/vb=5,4 2006.218.07:36:31.92#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.218.07:36:31.92#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.218.07:36:31.92#ibcon#ireg 11 cls_cnt 2 2006.218.07:36:31.92#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.218.07:36:31.98#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.218.07:36:31.98#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.218.07:36:31.98#ibcon#enter wrdev, iclass 40, count 2 2006.218.07:36:31.98#ibcon#first serial, iclass 40, count 2 2006.218.07:36:31.98#ibcon#enter sib2, iclass 40, count 2 2006.218.07:36:31.98#ibcon#flushed, iclass 40, count 2 2006.218.07:36:31.98#ibcon#about to write, iclass 40, count 2 2006.218.07:36:31.98#ibcon#wrote, iclass 40, count 2 2006.218.07:36:31.98#ibcon#about to read 3, iclass 40, count 2 2006.218.07:36:32.00#ibcon#read 3, iclass 40, count 2 2006.218.07:36:32.00#ibcon#about to read 4, iclass 40, count 2 2006.218.07:36:32.00#ibcon#read 4, iclass 40, count 2 2006.218.07:36:32.00#ibcon#about to read 5, iclass 40, count 2 2006.218.07:36:32.00#ibcon#read 5, iclass 40, count 2 2006.218.07:36:32.00#ibcon#about to read 6, iclass 40, count 2 2006.218.07:36:32.00#ibcon#read 6, iclass 40, count 2 2006.218.07:36:32.00#ibcon#end of sib2, iclass 40, count 2 2006.218.07:36:32.00#ibcon#*mode == 0, iclass 40, count 2 2006.218.07:36:32.00#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.218.07:36:32.00#ibcon#[27=AT05-04\r\n] 2006.218.07:36:32.00#ibcon#*before write, iclass 40, count 2 2006.218.07:36:32.00#ibcon#enter sib2, iclass 40, count 2 2006.218.07:36:32.00#ibcon#flushed, iclass 40, count 2 2006.218.07:36:32.00#ibcon#about to write, iclass 40, count 2 2006.218.07:36:32.00#ibcon#wrote, iclass 40, count 2 2006.218.07:36:32.00#ibcon#about to read 3, iclass 40, count 2 2006.218.07:36:32.03#ibcon#read 3, iclass 40, count 2 2006.218.07:36:32.03#ibcon#about to read 4, iclass 40, count 2 2006.218.07:36:32.03#ibcon#read 4, iclass 40, count 2 2006.218.07:36:32.03#ibcon#about to read 5, iclass 40, count 2 2006.218.07:36:32.03#ibcon#read 5, iclass 40, count 2 2006.218.07:36:32.03#ibcon#about to read 6, iclass 40, count 2 2006.218.07:36:32.03#ibcon#read 6, iclass 40, count 2 2006.218.07:36:32.03#ibcon#end of sib2, iclass 40, count 2 2006.218.07:36:32.03#ibcon#*after write, iclass 40, count 2 2006.218.07:36:32.03#ibcon#*before return 0, iclass 40, count 2 2006.218.07:36:32.03#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.218.07:36:32.03#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.218.07:36:32.03#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.218.07:36:32.03#ibcon#ireg 7 cls_cnt 0 2006.218.07:36:32.03#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.218.07:36:32.15#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.218.07:36:32.15#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.218.07:36:32.15#ibcon#enter wrdev, iclass 40, count 0 2006.218.07:36:32.15#ibcon#first serial, iclass 40, count 0 2006.218.07:36:32.15#ibcon#enter sib2, iclass 40, count 0 2006.218.07:36:32.15#ibcon#flushed, iclass 40, count 0 2006.218.07:36:32.15#ibcon#about to write, iclass 40, count 0 2006.218.07:36:32.15#ibcon#wrote, iclass 40, count 0 2006.218.07:36:32.15#ibcon#about to read 3, iclass 40, count 0 2006.218.07:36:32.17#ibcon#read 3, iclass 40, count 0 2006.218.07:36:32.17#ibcon#about to read 4, iclass 40, count 0 2006.218.07:36:32.17#ibcon#read 4, iclass 40, count 0 2006.218.07:36:32.17#ibcon#about to read 5, iclass 40, count 0 2006.218.07:36:32.17#ibcon#read 5, iclass 40, count 0 2006.218.07:36:32.17#ibcon#about to read 6, iclass 40, count 0 2006.218.07:36:32.17#ibcon#read 6, iclass 40, count 0 2006.218.07:36:32.17#ibcon#end of sib2, iclass 40, count 0 2006.218.07:36:32.17#ibcon#*mode == 0, iclass 40, count 0 2006.218.07:36:32.17#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.218.07:36:32.17#ibcon#[27=USB\r\n] 2006.218.07:36:32.17#ibcon#*before write, iclass 40, count 0 2006.218.07:36:32.17#ibcon#enter sib2, iclass 40, count 0 2006.218.07:36:32.17#ibcon#flushed, iclass 40, count 0 2006.218.07:36:32.17#ibcon#about to write, iclass 40, count 0 2006.218.07:36:32.17#ibcon#wrote, iclass 40, count 0 2006.218.07:36:32.17#ibcon#about to read 3, iclass 40, count 0 2006.218.07:36:32.20#ibcon#read 3, iclass 40, count 0 2006.218.07:36:32.20#ibcon#about to read 4, iclass 40, count 0 2006.218.07:36:32.20#ibcon#read 4, iclass 40, count 0 2006.218.07:36:32.20#ibcon#about to read 5, iclass 40, count 0 2006.218.07:36:32.20#ibcon#read 5, iclass 40, count 0 2006.218.07:36:32.20#ibcon#about to read 6, iclass 40, count 0 2006.218.07:36:32.20#ibcon#read 6, iclass 40, count 0 2006.218.07:36:32.20#ibcon#end of sib2, iclass 40, count 0 2006.218.07:36:32.20#ibcon#*after write, iclass 40, count 0 2006.218.07:36:32.20#ibcon#*before return 0, iclass 40, count 0 2006.218.07:36:32.20#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.218.07:36:32.20#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.218.07:36:32.20#ibcon#about to clear, iclass 40 cls_cnt 0 2006.218.07:36:32.20#ibcon#cleared, iclass 40 cls_cnt 0 2006.218.07:36:32.20$vc4f8/vblo=6,752.99 2006.218.07:36:32.20#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.218.07:36:32.20#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.218.07:36:32.20#ibcon#ireg 17 cls_cnt 0 2006.218.07:36:32.20#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.218.07:36:32.20#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.218.07:36:32.20#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.218.07:36:32.20#ibcon#enter wrdev, iclass 4, count 0 2006.218.07:36:32.20#ibcon#first serial, iclass 4, count 0 2006.218.07:36:32.20#ibcon#enter sib2, iclass 4, count 0 2006.218.07:36:32.20#ibcon#flushed, iclass 4, count 0 2006.218.07:36:32.20#ibcon#about to write, iclass 4, count 0 2006.218.07:36:32.20#ibcon#wrote, iclass 4, count 0 2006.218.07:36:32.20#ibcon#about to read 3, iclass 4, count 0 2006.218.07:36:32.22#ibcon#read 3, iclass 4, count 0 2006.218.07:36:32.22#ibcon#about to read 4, iclass 4, count 0 2006.218.07:36:32.22#ibcon#read 4, iclass 4, count 0 2006.218.07:36:32.22#ibcon#about to read 5, iclass 4, count 0 2006.218.07:36:32.22#ibcon#read 5, iclass 4, count 0 2006.218.07:36:32.22#ibcon#about to read 6, iclass 4, count 0 2006.218.07:36:32.22#ibcon#read 6, iclass 4, count 0 2006.218.07:36:32.22#ibcon#end of sib2, iclass 4, count 0 2006.218.07:36:32.22#ibcon#*mode == 0, iclass 4, count 0 2006.218.07:36:32.22#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.218.07:36:32.22#ibcon#[28=FRQ=06,752.99\r\n] 2006.218.07:36:32.22#ibcon#*before write, iclass 4, count 0 2006.218.07:36:32.22#ibcon#enter sib2, iclass 4, count 0 2006.218.07:36:32.22#ibcon#flushed, iclass 4, count 0 2006.218.07:36:32.22#ibcon#about to write, iclass 4, count 0 2006.218.07:36:32.22#ibcon#wrote, iclass 4, count 0 2006.218.07:36:32.22#ibcon#about to read 3, iclass 4, count 0 2006.218.07:36:32.26#ibcon#read 3, iclass 4, count 0 2006.218.07:36:32.26#ibcon#about to read 4, iclass 4, count 0 2006.218.07:36:32.26#ibcon#read 4, iclass 4, count 0 2006.218.07:36:32.26#ibcon#about to read 5, iclass 4, count 0 2006.218.07:36:32.26#ibcon#read 5, iclass 4, count 0 2006.218.07:36:32.26#ibcon#about to read 6, iclass 4, count 0 2006.218.07:36:32.26#ibcon#read 6, iclass 4, count 0 2006.218.07:36:32.26#ibcon#end of sib2, iclass 4, count 0 2006.218.07:36:32.26#ibcon#*after write, iclass 4, count 0 2006.218.07:36:32.26#ibcon#*before return 0, iclass 4, count 0 2006.218.07:36:32.26#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.218.07:36:32.26#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.218.07:36:32.26#ibcon#about to clear, iclass 4 cls_cnt 0 2006.218.07:36:32.26#ibcon#cleared, iclass 4 cls_cnt 0 2006.218.07:36:32.26$vc4f8/vb=6,4 2006.218.07:36:32.26#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.218.07:36:32.26#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.218.07:36:32.26#ibcon#ireg 11 cls_cnt 2 2006.218.07:36:32.26#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.218.07:36:32.32#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.218.07:36:32.32#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.218.07:36:32.32#ibcon#enter wrdev, iclass 6, count 2 2006.218.07:36:32.32#ibcon#first serial, iclass 6, count 2 2006.218.07:36:32.32#ibcon#enter sib2, iclass 6, count 2 2006.218.07:36:32.32#ibcon#flushed, iclass 6, count 2 2006.218.07:36:32.33#ibcon#about to write, iclass 6, count 2 2006.218.07:36:32.33#ibcon#wrote, iclass 6, count 2 2006.218.07:36:32.33#ibcon#about to read 3, iclass 6, count 2 2006.218.07:36:32.34#ibcon#read 3, iclass 6, count 2 2006.218.07:36:32.34#ibcon#about to read 4, iclass 6, count 2 2006.218.07:36:32.34#ibcon#read 4, iclass 6, count 2 2006.218.07:36:32.34#ibcon#about to read 5, iclass 6, count 2 2006.218.07:36:32.34#ibcon#read 5, iclass 6, count 2 2006.218.07:36:32.34#ibcon#about to read 6, iclass 6, count 2 2006.218.07:36:32.34#ibcon#read 6, iclass 6, count 2 2006.218.07:36:32.34#ibcon#end of sib2, iclass 6, count 2 2006.218.07:36:32.34#ibcon#*mode == 0, iclass 6, count 2 2006.218.07:36:32.34#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.218.07:36:32.34#ibcon#[27=AT06-04\r\n] 2006.218.07:36:32.34#ibcon#*before write, iclass 6, count 2 2006.218.07:36:32.34#ibcon#enter sib2, iclass 6, count 2 2006.218.07:36:32.34#ibcon#flushed, iclass 6, count 2 2006.218.07:36:32.34#ibcon#about to write, iclass 6, count 2 2006.218.07:36:32.34#ibcon#wrote, iclass 6, count 2 2006.218.07:36:32.34#ibcon#about to read 3, iclass 6, count 2 2006.218.07:36:32.37#ibcon#read 3, iclass 6, count 2 2006.218.07:36:32.37#ibcon#about to read 4, iclass 6, count 2 2006.218.07:36:32.37#ibcon#read 4, iclass 6, count 2 2006.218.07:36:32.37#ibcon#about to read 5, iclass 6, count 2 2006.218.07:36:32.37#ibcon#read 5, iclass 6, count 2 2006.218.07:36:32.37#ibcon#about to read 6, iclass 6, count 2 2006.218.07:36:32.37#ibcon#read 6, iclass 6, count 2 2006.218.07:36:32.37#ibcon#end of sib2, iclass 6, count 2 2006.218.07:36:32.37#ibcon#*after write, iclass 6, count 2 2006.218.07:36:32.37#ibcon#*before return 0, iclass 6, count 2 2006.218.07:36:32.37#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.218.07:36:32.37#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.218.07:36:32.37#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.218.07:36:32.37#ibcon#ireg 7 cls_cnt 0 2006.218.07:36:32.37#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.218.07:36:32.49#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.218.07:36:32.49#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.218.07:36:32.49#ibcon#enter wrdev, iclass 6, count 0 2006.218.07:36:32.49#ibcon#first serial, iclass 6, count 0 2006.218.07:36:32.49#ibcon#enter sib2, iclass 6, count 0 2006.218.07:36:32.49#ibcon#flushed, iclass 6, count 0 2006.218.07:36:32.49#ibcon#about to write, iclass 6, count 0 2006.218.07:36:32.49#ibcon#wrote, iclass 6, count 0 2006.218.07:36:32.49#ibcon#about to read 3, iclass 6, count 0 2006.218.07:36:32.51#ibcon#read 3, iclass 6, count 0 2006.218.07:36:32.51#ibcon#about to read 4, iclass 6, count 0 2006.218.07:36:32.51#ibcon#read 4, iclass 6, count 0 2006.218.07:36:32.51#ibcon#about to read 5, iclass 6, count 0 2006.218.07:36:32.51#ibcon#read 5, iclass 6, count 0 2006.218.07:36:32.51#ibcon#about to read 6, iclass 6, count 0 2006.218.07:36:32.51#ibcon#read 6, iclass 6, count 0 2006.218.07:36:32.51#ibcon#end of sib2, iclass 6, count 0 2006.218.07:36:32.51#ibcon#*mode == 0, iclass 6, count 0 2006.218.07:36:32.51#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.218.07:36:32.51#ibcon#[27=USB\r\n] 2006.218.07:36:32.51#ibcon#*before write, iclass 6, count 0 2006.218.07:36:32.51#ibcon#enter sib2, iclass 6, count 0 2006.218.07:36:32.51#ibcon#flushed, iclass 6, count 0 2006.218.07:36:32.51#ibcon#about to write, iclass 6, count 0 2006.218.07:36:32.51#ibcon#wrote, iclass 6, count 0 2006.218.07:36:32.51#ibcon#about to read 3, iclass 6, count 0 2006.218.07:36:32.54#ibcon#read 3, iclass 6, count 0 2006.218.07:36:32.54#ibcon#about to read 4, iclass 6, count 0 2006.218.07:36:32.54#ibcon#read 4, iclass 6, count 0 2006.218.07:36:32.54#ibcon#about to read 5, iclass 6, count 0 2006.218.07:36:32.54#ibcon#read 5, iclass 6, count 0 2006.218.07:36:32.54#ibcon#about to read 6, iclass 6, count 0 2006.218.07:36:32.54#ibcon#read 6, iclass 6, count 0 2006.218.07:36:32.54#ibcon#end of sib2, iclass 6, count 0 2006.218.07:36:32.54#ibcon#*after write, iclass 6, count 0 2006.218.07:36:32.54#ibcon#*before return 0, iclass 6, count 0 2006.218.07:36:32.54#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.218.07:36:32.54#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.218.07:36:32.54#ibcon#about to clear, iclass 6 cls_cnt 0 2006.218.07:36:32.54#ibcon#cleared, iclass 6 cls_cnt 0 2006.218.07:36:32.54$vc4f8/vabw=wide 2006.218.07:36:32.54#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.218.07:36:32.54#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.218.07:36:32.54#ibcon#ireg 8 cls_cnt 0 2006.218.07:36:32.54#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.218.07:36:32.54#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.218.07:36:32.54#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.218.07:36:32.54#ibcon#enter wrdev, iclass 10, count 0 2006.218.07:36:32.54#ibcon#first serial, iclass 10, count 0 2006.218.07:36:32.54#ibcon#enter sib2, iclass 10, count 0 2006.218.07:36:32.54#ibcon#flushed, iclass 10, count 0 2006.218.07:36:32.54#ibcon#about to write, iclass 10, count 0 2006.218.07:36:32.54#ibcon#wrote, iclass 10, count 0 2006.218.07:36:32.54#ibcon#about to read 3, iclass 10, count 0 2006.218.07:36:32.56#ibcon#read 3, iclass 10, count 0 2006.218.07:36:32.56#ibcon#about to read 4, iclass 10, count 0 2006.218.07:36:32.56#ibcon#read 4, iclass 10, count 0 2006.218.07:36:32.56#ibcon#about to read 5, iclass 10, count 0 2006.218.07:36:32.56#ibcon#read 5, iclass 10, count 0 2006.218.07:36:32.56#ibcon#about to read 6, iclass 10, count 0 2006.218.07:36:32.56#ibcon#read 6, iclass 10, count 0 2006.218.07:36:32.56#ibcon#end of sib2, iclass 10, count 0 2006.218.07:36:32.56#ibcon#*mode == 0, iclass 10, count 0 2006.218.07:36:32.56#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.218.07:36:32.56#ibcon#[25=BW32\r\n] 2006.218.07:36:32.56#ibcon#*before write, iclass 10, count 0 2006.218.07:36:32.56#ibcon#enter sib2, iclass 10, count 0 2006.218.07:36:32.56#ibcon#flushed, iclass 10, count 0 2006.218.07:36:32.56#ibcon#about to write, iclass 10, count 0 2006.218.07:36:32.56#ibcon#wrote, iclass 10, count 0 2006.218.07:36:32.56#ibcon#about to read 3, iclass 10, count 0 2006.218.07:36:32.59#ibcon#read 3, iclass 10, count 0 2006.218.07:36:32.59#ibcon#about to read 4, iclass 10, count 0 2006.218.07:36:32.59#ibcon#read 4, iclass 10, count 0 2006.218.07:36:32.59#ibcon#about to read 5, iclass 10, count 0 2006.218.07:36:32.59#ibcon#read 5, iclass 10, count 0 2006.218.07:36:32.59#ibcon#about to read 6, iclass 10, count 0 2006.218.07:36:32.59#ibcon#read 6, iclass 10, count 0 2006.218.07:36:32.59#ibcon#end of sib2, iclass 10, count 0 2006.218.07:36:32.59#ibcon#*after write, iclass 10, count 0 2006.218.07:36:32.59#ibcon#*before return 0, iclass 10, count 0 2006.218.07:36:32.59#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.218.07:36:32.59#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.218.07:36:32.59#ibcon#about to clear, iclass 10 cls_cnt 0 2006.218.07:36:32.59#ibcon#cleared, iclass 10 cls_cnt 0 2006.218.07:36:32.59$vc4f8/vbbw=wide 2006.218.07:36:32.59#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.218.07:36:32.59#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.218.07:36:32.59#ibcon#ireg 8 cls_cnt 0 2006.218.07:36:32.59#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.218.07:36:32.66#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.218.07:36:32.66#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.218.07:36:32.66#ibcon#enter wrdev, iclass 12, count 0 2006.218.07:36:32.66#ibcon#first serial, iclass 12, count 0 2006.218.07:36:32.66#ibcon#enter sib2, iclass 12, count 0 2006.218.07:36:32.66#ibcon#flushed, iclass 12, count 0 2006.218.07:36:32.66#ibcon#about to write, iclass 12, count 0 2006.218.07:36:32.66#ibcon#wrote, iclass 12, count 0 2006.218.07:36:32.66#ibcon#about to read 3, iclass 12, count 0 2006.218.07:36:32.68#ibcon#read 3, iclass 12, count 0 2006.218.07:36:32.68#ibcon#about to read 4, iclass 12, count 0 2006.218.07:36:32.68#ibcon#read 4, iclass 12, count 0 2006.218.07:36:32.68#ibcon#about to read 5, iclass 12, count 0 2006.218.07:36:32.68#ibcon#read 5, iclass 12, count 0 2006.218.07:36:32.68#ibcon#about to read 6, iclass 12, count 0 2006.218.07:36:32.68#ibcon#read 6, iclass 12, count 0 2006.218.07:36:32.68#ibcon#end of sib2, iclass 12, count 0 2006.218.07:36:32.68#ibcon#*mode == 0, iclass 12, count 0 2006.218.07:36:32.68#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.218.07:36:32.68#ibcon#[27=BW32\r\n] 2006.218.07:36:32.68#ibcon#*before write, iclass 12, count 0 2006.218.07:36:32.68#ibcon#enter sib2, iclass 12, count 0 2006.218.07:36:32.68#ibcon#flushed, iclass 12, count 0 2006.218.07:36:32.68#ibcon#about to write, iclass 12, count 0 2006.218.07:36:32.68#ibcon#wrote, iclass 12, count 0 2006.218.07:36:32.68#ibcon#about to read 3, iclass 12, count 0 2006.218.07:36:32.71#ibcon#read 3, iclass 12, count 0 2006.218.07:36:32.71#ibcon#about to read 4, iclass 12, count 0 2006.218.07:36:32.71#ibcon#read 4, iclass 12, count 0 2006.218.07:36:32.71#ibcon#about to read 5, iclass 12, count 0 2006.218.07:36:32.71#ibcon#read 5, iclass 12, count 0 2006.218.07:36:32.71#ibcon#about to read 6, iclass 12, count 0 2006.218.07:36:32.71#ibcon#read 6, iclass 12, count 0 2006.218.07:36:32.71#ibcon#end of sib2, iclass 12, count 0 2006.218.07:36:32.71#ibcon#*after write, iclass 12, count 0 2006.218.07:36:32.71#ibcon#*before return 0, iclass 12, count 0 2006.218.07:36:32.71#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.218.07:36:32.71#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.218.07:36:32.71#ibcon#about to clear, iclass 12 cls_cnt 0 2006.218.07:36:32.71#ibcon#cleared, iclass 12 cls_cnt 0 2006.218.07:36:32.71$4f8m12a/ifd4f 2006.218.07:36:32.71$ifd4f/lo= 2006.218.07:36:32.71$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.218.07:36:32.71$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.218.07:36:32.71$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.218.07:36:32.71$ifd4f/patch= 2006.218.07:36:32.71$ifd4f/patch=lo1,a1,a2,a3,a4 2006.218.07:36:32.71$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.218.07:36:32.71$ifd4f/patch=lo3,a5,a6,a7,a8 2006.218.07:36:32.71$4f8m12a/"form=m,16.000,1:2 2006.218.07:36:32.71$4f8m12a/"tpicd 2006.218.07:36:32.71$4f8m12a/echo=off 2006.218.07:36:32.71$4f8m12a/xlog=off 2006.218.07:36:32.71:!2006.218.07:37:00 2006.218.07:36:42.13#trakl#Source acquired 2006.218.07:36:42.13#flagr#flagr/antenna,acquired 2006.218.07:37:00.00:preob 2006.218.07:37:01.13/onsource/TRACKING 2006.218.07:37:01.13:!2006.218.07:37:10 2006.218.07:37:10.00:data_valid=on 2006.218.07:37:10.00:midob 2006.218.07:37:10.13/onsource/TRACKING 2006.218.07:37:10.13/wx/31.51,1007.4,70 2006.218.07:37:10.34/cable/+6.3846E-03 2006.218.07:37:11.43/va/01,05,usb,yes,33,35 2006.218.07:37:11.43/va/02,04,usb,yes,31,33 2006.218.07:37:11.43/va/03,04,usb,yes,29,30 2006.218.07:37:11.43/va/04,04,usb,yes,33,35 2006.218.07:37:11.43/va/05,07,usb,yes,35,37 2006.218.07:37:11.43/va/06,06,usb,yes,34,33 2006.218.07:37:11.43/va/07,06,usb,yes,34,34 2006.218.07:37:11.43/va/08,07,usb,yes,32,32 2006.218.07:37:11.66/valo/01,532.99,yes,locked 2006.218.07:37:11.66/valo/02,572.99,yes,locked 2006.218.07:37:11.66/valo/03,672.99,yes,locked 2006.218.07:37:11.66/valo/04,832.99,yes,locked 2006.218.07:37:11.66/valo/05,652.99,yes,locked 2006.218.07:37:11.66/valo/06,772.99,yes,locked 2006.218.07:37:11.66/valo/07,832.99,yes,locked 2006.218.07:37:11.66/valo/08,852.99,yes,locked 2006.218.07:37:12.75/vb/01,04,usb,yes,31,30 2006.218.07:37:12.75/vb/02,04,usb,yes,33,34 2006.218.07:37:12.75/vb/03,04,usb,yes,29,33 2006.218.07:37:12.75/vb/04,04,usb,yes,30,30 2006.218.07:37:12.75/vb/05,04,usb,yes,29,33 2006.218.07:37:12.75/vb/06,04,usb,yes,30,32 2006.218.07:37:12.75/vb/07,04,usb,yes,32,32 2006.218.07:37:12.75/vb/08,04,usb,yes,29,33 2006.218.07:37:12.98/vblo/01,632.99,yes,locked 2006.218.07:37:12.98/vblo/02,640.99,yes,locked 2006.218.07:37:12.98/vblo/03,656.99,yes,locked 2006.218.07:37:12.98/vblo/04,712.99,yes,locked 2006.218.07:37:12.98/vblo/05,744.99,yes,locked 2006.218.07:37:12.98/vblo/06,752.99,yes,locked 2006.218.07:37:12.98/vblo/07,734.99,yes,locked 2006.218.07:37:12.98/vblo/08,744.99,yes,locked 2006.218.07:37:13.13/vabw/8 2006.218.07:37:13.28/vbbw/8 2006.218.07:37:13.37/xfe/off,on,15.2 2006.218.07:37:13.76/ifatt/23,28,28,28 2006.218.07:37:14.08/fmout-gps/S +4.74E-07 2006.218.07:37:14.12:!2006.218.07:38:10 2006.218.07:38:10.00:data_valid=off 2006.218.07:38:10.00:postob 2006.218.07:38:10.08/cable/+6.3838E-03 2006.218.07:38:10.08/wx/31.47,1007.4,71 2006.218.07:38:11.08/fmout-gps/S +4.76E-07 2006.218.07:38:11.08:scan_name=218-0739,k06218,60 2006.218.07:38:11.08:source=1357+769,135755.37,764321.1,2000.0,neutral 2006.218.07:38:11.13#flagr#flagr/antenna,new-source 2006.218.07:38:12.13:checkk5 2006.218.07:38:12.51/chk_autoobs//k5ts1/ autoobs is running! 2006.218.07:38:12.88/chk_autoobs//k5ts2/ autoobs is running! 2006.218.07:38:13.26/chk_autoobs//k5ts3/ autoobs is running! 2006.218.07:38:13.64/chk_autoobs//k5ts4/ autoobs is running! 2006.218.07:38:14.00/chk_obsdata//k5ts1/T2180737??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:38:14.43/chk_obsdata//k5ts2/T2180737??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:38:14.80/chk_obsdata//k5ts3/T2180737??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:38:15.17/chk_obsdata//k5ts4/T2180737??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:38:15.86/k5log//k5ts1_log_newline 2006.218.07:38:16.56/k5log//k5ts2_log_newline 2006.218.07:38:17.26/k5log//k5ts3_log_newline 2006.218.07:38:17.95/k5log//k5ts4_log_newline 2006.218.07:38:17.97/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.218.07:38:17.97:4f8m12a=1 2006.218.07:38:17.97$4f8m12a/echo=on 2006.218.07:38:17.97$4f8m12a/pcalon 2006.218.07:38:17.97$pcalon/"no phase cal control is implemented here 2006.218.07:38:17.97$4f8m12a/"tpicd=stop 2006.218.07:38:17.97$4f8m12a/vc4f8 2006.218.07:38:17.97$vc4f8/valo=1,532.99 2006.218.07:38:17.97#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.218.07:38:17.97#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.218.07:38:17.97#ibcon#ireg 17 cls_cnt 0 2006.218.07:38:17.97#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.218.07:38:17.97#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.218.07:38:17.97#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.218.07:38:17.97#ibcon#enter wrdev, iclass 19, count 0 2006.218.07:38:17.97#ibcon#first serial, iclass 19, count 0 2006.218.07:38:17.97#ibcon#enter sib2, iclass 19, count 0 2006.218.07:38:17.97#ibcon#flushed, iclass 19, count 0 2006.218.07:38:17.97#ibcon#about to write, iclass 19, count 0 2006.218.07:38:17.97#ibcon#wrote, iclass 19, count 0 2006.218.07:38:17.97#ibcon#about to read 3, iclass 19, count 0 2006.218.07:38:17.99#ibcon#read 3, iclass 19, count 0 2006.218.07:38:17.99#ibcon#about to read 4, iclass 19, count 0 2006.218.07:38:17.99#ibcon#read 4, iclass 19, count 0 2006.218.07:38:17.99#ibcon#about to read 5, iclass 19, count 0 2006.218.07:38:17.99#ibcon#read 5, iclass 19, count 0 2006.218.07:38:17.99#ibcon#about to read 6, iclass 19, count 0 2006.218.07:38:17.99#ibcon#read 6, iclass 19, count 0 2006.218.07:38:17.99#ibcon#end of sib2, iclass 19, count 0 2006.218.07:38:17.99#ibcon#*mode == 0, iclass 19, count 0 2006.218.07:38:17.99#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.218.07:38:17.99#ibcon#[26=FRQ=01,532.99\r\n] 2006.218.07:38:17.99#ibcon#*before write, iclass 19, count 0 2006.218.07:38:17.99#ibcon#enter sib2, iclass 19, count 0 2006.218.07:38:17.99#ibcon#flushed, iclass 19, count 0 2006.218.07:38:17.99#ibcon#about to write, iclass 19, count 0 2006.218.07:38:17.99#ibcon#wrote, iclass 19, count 0 2006.218.07:38:17.99#ibcon#about to read 3, iclass 19, count 0 2006.218.07:38:18.04#ibcon#read 3, iclass 19, count 0 2006.218.07:38:18.04#ibcon#about to read 4, iclass 19, count 0 2006.218.07:38:18.04#ibcon#read 4, iclass 19, count 0 2006.218.07:38:18.04#ibcon#about to read 5, iclass 19, count 0 2006.218.07:38:18.04#ibcon#read 5, iclass 19, count 0 2006.218.07:38:18.04#ibcon#about to read 6, iclass 19, count 0 2006.218.07:38:18.04#ibcon#read 6, iclass 19, count 0 2006.218.07:38:18.04#ibcon#end of sib2, iclass 19, count 0 2006.218.07:38:18.04#ibcon#*after write, iclass 19, count 0 2006.218.07:38:18.04#ibcon#*before return 0, iclass 19, count 0 2006.218.07:38:18.04#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.218.07:38:18.04#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.218.07:38:18.04#ibcon#about to clear, iclass 19 cls_cnt 0 2006.218.07:38:18.04#ibcon#cleared, iclass 19 cls_cnt 0 2006.218.07:38:18.04$vc4f8/va=1,5 2006.218.07:38:18.04#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.218.07:38:18.04#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.218.07:38:18.04#ibcon#ireg 11 cls_cnt 2 2006.218.07:38:18.04#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.218.07:38:18.04#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.218.07:38:18.04#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.218.07:38:18.04#ibcon#enter wrdev, iclass 21, count 2 2006.218.07:38:18.04#ibcon#first serial, iclass 21, count 2 2006.218.07:38:18.04#ibcon#enter sib2, iclass 21, count 2 2006.218.07:38:18.04#ibcon#flushed, iclass 21, count 2 2006.218.07:38:18.04#ibcon#about to write, iclass 21, count 2 2006.218.07:38:18.04#ibcon#wrote, iclass 21, count 2 2006.218.07:38:18.04#ibcon#about to read 3, iclass 21, count 2 2006.218.07:38:18.06#ibcon#read 3, iclass 21, count 2 2006.218.07:38:18.06#ibcon#about to read 4, iclass 21, count 2 2006.218.07:38:18.06#ibcon#read 4, iclass 21, count 2 2006.218.07:38:18.06#ibcon#about to read 5, iclass 21, count 2 2006.218.07:38:18.06#ibcon#read 5, iclass 21, count 2 2006.218.07:38:18.06#ibcon#about to read 6, iclass 21, count 2 2006.218.07:38:18.06#ibcon#read 6, iclass 21, count 2 2006.218.07:38:18.06#ibcon#end of sib2, iclass 21, count 2 2006.218.07:38:18.06#ibcon#*mode == 0, iclass 21, count 2 2006.218.07:38:18.06#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.218.07:38:18.06#ibcon#[25=AT01-05\r\n] 2006.218.07:38:18.06#ibcon#*before write, iclass 21, count 2 2006.218.07:38:18.06#ibcon#enter sib2, iclass 21, count 2 2006.218.07:38:18.06#ibcon#flushed, iclass 21, count 2 2006.218.07:38:18.06#ibcon#about to write, iclass 21, count 2 2006.218.07:38:18.06#ibcon#wrote, iclass 21, count 2 2006.218.07:38:18.06#ibcon#about to read 3, iclass 21, count 2 2006.218.07:38:18.09#ibcon#read 3, iclass 21, count 2 2006.218.07:38:18.09#ibcon#about to read 4, iclass 21, count 2 2006.218.07:38:18.09#ibcon#read 4, iclass 21, count 2 2006.218.07:38:18.09#ibcon#about to read 5, iclass 21, count 2 2006.218.07:38:18.09#ibcon#read 5, iclass 21, count 2 2006.218.07:38:18.09#ibcon#about to read 6, iclass 21, count 2 2006.218.07:38:18.09#ibcon#read 6, iclass 21, count 2 2006.218.07:38:18.09#ibcon#end of sib2, iclass 21, count 2 2006.218.07:38:18.09#ibcon#*after write, iclass 21, count 2 2006.218.07:38:18.09#ibcon#*before return 0, iclass 21, count 2 2006.218.07:38:18.09#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.218.07:38:18.09#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.218.07:38:18.09#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.218.07:38:18.09#ibcon#ireg 7 cls_cnt 0 2006.218.07:38:18.09#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.218.07:38:18.21#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.218.07:38:18.21#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.218.07:38:18.21#ibcon#enter wrdev, iclass 21, count 0 2006.218.07:38:18.21#ibcon#first serial, iclass 21, count 0 2006.218.07:38:18.21#ibcon#enter sib2, iclass 21, count 0 2006.218.07:38:18.21#ibcon#flushed, iclass 21, count 0 2006.218.07:38:18.21#ibcon#about to write, iclass 21, count 0 2006.218.07:38:18.21#ibcon#wrote, iclass 21, count 0 2006.218.07:38:18.21#ibcon#about to read 3, iclass 21, count 0 2006.218.07:38:18.23#ibcon#read 3, iclass 21, count 0 2006.218.07:38:18.23#ibcon#about to read 4, iclass 21, count 0 2006.218.07:38:18.23#ibcon#read 4, iclass 21, count 0 2006.218.07:38:18.23#ibcon#about to read 5, iclass 21, count 0 2006.218.07:38:18.23#ibcon#read 5, iclass 21, count 0 2006.218.07:38:18.23#ibcon#about to read 6, iclass 21, count 0 2006.218.07:38:18.23#ibcon#read 6, iclass 21, count 0 2006.218.07:38:18.23#ibcon#end of sib2, iclass 21, count 0 2006.218.07:38:18.23#ibcon#*mode == 0, iclass 21, count 0 2006.218.07:38:18.23#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.218.07:38:18.23#ibcon#[25=USB\r\n] 2006.218.07:38:18.23#ibcon#*before write, iclass 21, count 0 2006.218.07:38:18.23#ibcon#enter sib2, iclass 21, count 0 2006.218.07:38:18.23#ibcon#flushed, iclass 21, count 0 2006.218.07:38:18.23#ibcon#about to write, iclass 21, count 0 2006.218.07:38:18.23#ibcon#wrote, iclass 21, count 0 2006.218.07:38:18.23#ibcon#about to read 3, iclass 21, count 0 2006.218.07:38:18.26#ibcon#read 3, iclass 21, count 0 2006.218.07:38:18.26#ibcon#about to read 4, iclass 21, count 0 2006.218.07:38:18.26#ibcon#read 4, iclass 21, count 0 2006.218.07:38:18.26#ibcon#about to read 5, iclass 21, count 0 2006.218.07:38:18.26#ibcon#read 5, iclass 21, count 0 2006.218.07:38:18.26#ibcon#about to read 6, iclass 21, count 0 2006.218.07:38:18.26#ibcon#read 6, iclass 21, count 0 2006.218.07:38:18.26#ibcon#end of sib2, iclass 21, count 0 2006.218.07:38:18.26#ibcon#*after write, iclass 21, count 0 2006.218.07:38:18.26#ibcon#*before return 0, iclass 21, count 0 2006.218.07:38:18.26#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.218.07:38:18.26#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.218.07:38:18.26#ibcon#about to clear, iclass 21 cls_cnt 0 2006.218.07:38:18.26#ibcon#cleared, iclass 21 cls_cnt 0 2006.218.07:38:18.26$vc4f8/valo=2,572.99 2006.218.07:38:18.26#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.218.07:38:18.26#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.218.07:38:18.26#ibcon#ireg 17 cls_cnt 0 2006.218.07:38:18.26#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.218.07:38:18.26#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.218.07:38:18.26#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.218.07:38:18.26#ibcon#enter wrdev, iclass 23, count 0 2006.218.07:38:18.26#ibcon#first serial, iclass 23, count 0 2006.218.07:38:18.26#ibcon#enter sib2, iclass 23, count 0 2006.218.07:38:18.26#ibcon#flushed, iclass 23, count 0 2006.218.07:38:18.26#ibcon#about to write, iclass 23, count 0 2006.218.07:38:18.26#ibcon#wrote, iclass 23, count 0 2006.218.07:38:18.26#ibcon#about to read 3, iclass 23, count 0 2006.218.07:38:18.28#ibcon#read 3, iclass 23, count 0 2006.218.07:38:18.28#ibcon#about to read 4, iclass 23, count 0 2006.218.07:38:18.28#ibcon#read 4, iclass 23, count 0 2006.218.07:38:18.28#ibcon#about to read 5, iclass 23, count 0 2006.218.07:38:18.28#ibcon#read 5, iclass 23, count 0 2006.218.07:38:18.28#ibcon#about to read 6, iclass 23, count 0 2006.218.07:38:18.28#ibcon#read 6, iclass 23, count 0 2006.218.07:38:18.28#ibcon#end of sib2, iclass 23, count 0 2006.218.07:38:18.28#ibcon#*mode == 0, iclass 23, count 0 2006.218.07:38:18.28#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.218.07:38:18.28#ibcon#[26=FRQ=02,572.99\r\n] 2006.218.07:38:18.28#ibcon#*before write, iclass 23, count 0 2006.218.07:38:18.28#ibcon#enter sib2, iclass 23, count 0 2006.218.07:38:18.28#ibcon#flushed, iclass 23, count 0 2006.218.07:38:18.28#ibcon#about to write, iclass 23, count 0 2006.218.07:38:18.28#ibcon#wrote, iclass 23, count 0 2006.218.07:38:18.28#ibcon#about to read 3, iclass 23, count 0 2006.218.07:38:18.33#ibcon#read 3, iclass 23, count 0 2006.218.07:38:18.33#ibcon#about to read 4, iclass 23, count 0 2006.218.07:38:18.33#ibcon#read 4, iclass 23, count 0 2006.218.07:38:18.33#ibcon#about to read 5, iclass 23, count 0 2006.218.07:38:18.33#ibcon#read 5, iclass 23, count 0 2006.218.07:38:18.33#ibcon#about to read 6, iclass 23, count 0 2006.218.07:38:18.33#ibcon#read 6, iclass 23, count 0 2006.218.07:38:18.33#ibcon#end of sib2, iclass 23, count 0 2006.218.07:38:18.33#ibcon#*after write, iclass 23, count 0 2006.218.07:38:18.33#ibcon#*before return 0, iclass 23, count 0 2006.218.07:38:18.33#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.218.07:38:18.33#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.218.07:38:18.33#ibcon#about to clear, iclass 23 cls_cnt 0 2006.218.07:38:18.33#ibcon#cleared, iclass 23 cls_cnt 0 2006.218.07:38:18.33$vc4f8/va=2,4 2006.218.07:38:18.33#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.218.07:38:18.33#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.218.07:38:18.33#ibcon#ireg 11 cls_cnt 2 2006.218.07:38:18.33#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.218.07:38:18.38#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.218.07:38:18.38#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.218.07:38:18.38#ibcon#enter wrdev, iclass 25, count 2 2006.218.07:38:18.38#ibcon#first serial, iclass 25, count 2 2006.218.07:38:18.38#ibcon#enter sib2, iclass 25, count 2 2006.218.07:38:18.38#ibcon#flushed, iclass 25, count 2 2006.218.07:38:18.38#ibcon#about to write, iclass 25, count 2 2006.218.07:38:18.38#ibcon#wrote, iclass 25, count 2 2006.218.07:38:18.38#ibcon#about to read 3, iclass 25, count 2 2006.218.07:38:18.40#ibcon#read 3, iclass 25, count 2 2006.218.07:38:18.40#ibcon#about to read 4, iclass 25, count 2 2006.218.07:38:18.40#ibcon#read 4, iclass 25, count 2 2006.218.07:38:18.40#ibcon#about to read 5, iclass 25, count 2 2006.218.07:38:18.40#ibcon#read 5, iclass 25, count 2 2006.218.07:38:18.40#ibcon#about to read 6, iclass 25, count 2 2006.218.07:38:18.40#ibcon#read 6, iclass 25, count 2 2006.218.07:38:18.40#ibcon#end of sib2, iclass 25, count 2 2006.218.07:38:18.40#ibcon#*mode == 0, iclass 25, count 2 2006.218.07:38:18.40#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.218.07:38:18.40#ibcon#[25=AT02-04\r\n] 2006.218.07:38:18.40#ibcon#*before write, iclass 25, count 2 2006.218.07:38:18.40#ibcon#enter sib2, iclass 25, count 2 2006.218.07:38:18.40#ibcon#flushed, iclass 25, count 2 2006.218.07:38:18.40#ibcon#about to write, iclass 25, count 2 2006.218.07:38:18.40#ibcon#wrote, iclass 25, count 2 2006.218.07:38:18.40#ibcon#about to read 3, iclass 25, count 2 2006.218.07:38:18.43#ibcon#read 3, iclass 25, count 2 2006.218.07:38:18.43#ibcon#about to read 4, iclass 25, count 2 2006.218.07:38:18.43#ibcon#read 4, iclass 25, count 2 2006.218.07:38:18.43#ibcon#about to read 5, iclass 25, count 2 2006.218.07:38:18.43#ibcon#read 5, iclass 25, count 2 2006.218.07:38:18.43#ibcon#about to read 6, iclass 25, count 2 2006.218.07:38:18.43#ibcon#read 6, iclass 25, count 2 2006.218.07:38:18.43#ibcon#end of sib2, iclass 25, count 2 2006.218.07:38:18.43#ibcon#*after write, iclass 25, count 2 2006.218.07:38:18.43#ibcon#*before return 0, iclass 25, count 2 2006.218.07:38:18.43#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.218.07:38:18.43#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.218.07:38:18.43#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.218.07:38:18.43#ibcon#ireg 7 cls_cnt 0 2006.218.07:38:18.43#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.218.07:38:18.55#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.218.07:38:18.55#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.218.07:38:18.55#ibcon#enter wrdev, iclass 25, count 0 2006.218.07:38:18.55#ibcon#first serial, iclass 25, count 0 2006.218.07:38:18.55#ibcon#enter sib2, iclass 25, count 0 2006.218.07:38:18.55#ibcon#flushed, iclass 25, count 0 2006.218.07:38:18.55#ibcon#about to write, iclass 25, count 0 2006.218.07:38:18.55#ibcon#wrote, iclass 25, count 0 2006.218.07:38:18.55#ibcon#about to read 3, iclass 25, count 0 2006.218.07:38:18.57#ibcon#read 3, iclass 25, count 0 2006.218.07:38:18.57#ibcon#about to read 4, iclass 25, count 0 2006.218.07:38:18.57#ibcon#read 4, iclass 25, count 0 2006.218.07:38:18.57#ibcon#about to read 5, iclass 25, count 0 2006.218.07:38:18.57#ibcon#read 5, iclass 25, count 0 2006.218.07:38:18.57#ibcon#about to read 6, iclass 25, count 0 2006.218.07:38:18.57#ibcon#read 6, iclass 25, count 0 2006.218.07:38:18.57#ibcon#end of sib2, iclass 25, count 0 2006.218.07:38:18.57#ibcon#*mode == 0, iclass 25, count 0 2006.218.07:38:18.57#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.218.07:38:18.57#ibcon#[25=USB\r\n] 2006.218.07:38:18.57#ibcon#*before write, iclass 25, count 0 2006.218.07:38:18.57#ibcon#enter sib2, iclass 25, count 0 2006.218.07:38:18.57#ibcon#flushed, iclass 25, count 0 2006.218.07:38:18.57#ibcon#about to write, iclass 25, count 0 2006.218.07:38:18.57#ibcon#wrote, iclass 25, count 0 2006.218.07:38:18.57#ibcon#about to read 3, iclass 25, count 0 2006.218.07:38:18.60#ibcon#read 3, iclass 25, count 0 2006.218.07:38:18.60#ibcon#about to read 4, iclass 25, count 0 2006.218.07:38:18.60#ibcon#read 4, iclass 25, count 0 2006.218.07:38:18.60#ibcon#about to read 5, iclass 25, count 0 2006.218.07:38:18.60#ibcon#read 5, iclass 25, count 0 2006.218.07:38:18.60#ibcon#about to read 6, iclass 25, count 0 2006.218.07:38:18.60#ibcon#read 6, iclass 25, count 0 2006.218.07:38:18.60#ibcon#end of sib2, iclass 25, count 0 2006.218.07:38:18.60#ibcon#*after write, iclass 25, count 0 2006.218.07:38:18.60#ibcon#*before return 0, iclass 25, count 0 2006.218.07:38:18.60#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.218.07:38:18.60#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.218.07:38:18.60#ibcon#about to clear, iclass 25 cls_cnt 0 2006.218.07:38:18.60#ibcon#cleared, iclass 25 cls_cnt 0 2006.218.07:38:18.60$vc4f8/valo=3,672.99 2006.218.07:38:18.60#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.218.07:38:18.60#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.218.07:38:18.60#ibcon#ireg 17 cls_cnt 0 2006.218.07:38:18.60#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.218.07:38:18.60#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.218.07:38:18.60#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.218.07:38:18.60#ibcon#enter wrdev, iclass 27, count 0 2006.218.07:38:18.60#ibcon#first serial, iclass 27, count 0 2006.218.07:38:18.60#ibcon#enter sib2, iclass 27, count 0 2006.218.07:38:18.60#ibcon#flushed, iclass 27, count 0 2006.218.07:38:18.60#ibcon#about to write, iclass 27, count 0 2006.218.07:38:18.60#ibcon#wrote, iclass 27, count 0 2006.218.07:38:18.60#ibcon#about to read 3, iclass 27, count 0 2006.218.07:38:18.62#ibcon#read 3, iclass 27, count 0 2006.218.07:38:18.62#ibcon#about to read 4, iclass 27, count 0 2006.218.07:38:18.62#ibcon#read 4, iclass 27, count 0 2006.218.07:38:18.62#ibcon#about to read 5, iclass 27, count 0 2006.218.07:38:18.62#ibcon#read 5, iclass 27, count 0 2006.218.07:38:18.62#ibcon#about to read 6, iclass 27, count 0 2006.218.07:38:18.62#ibcon#read 6, iclass 27, count 0 2006.218.07:38:18.62#ibcon#end of sib2, iclass 27, count 0 2006.218.07:38:18.62#ibcon#*mode == 0, iclass 27, count 0 2006.218.07:38:18.62#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.218.07:38:18.62#ibcon#[26=FRQ=03,672.99\r\n] 2006.218.07:38:18.62#ibcon#*before write, iclass 27, count 0 2006.218.07:38:18.62#ibcon#enter sib2, iclass 27, count 0 2006.218.07:38:18.62#ibcon#flushed, iclass 27, count 0 2006.218.07:38:18.63#ibcon#about to write, iclass 27, count 0 2006.218.07:38:18.63#ibcon#wrote, iclass 27, count 0 2006.218.07:38:18.63#ibcon#about to read 3, iclass 27, count 0 2006.218.07:38:18.66#abcon#<5=/06 4.3 7.4 31.46 711007.4\r\n> 2006.218.07:38:18.67#ibcon#read 3, iclass 27, count 0 2006.218.07:38:18.67#ibcon#about to read 4, iclass 27, count 0 2006.218.07:38:18.67#ibcon#read 4, iclass 27, count 0 2006.218.07:38:18.67#ibcon#about to read 5, iclass 27, count 0 2006.218.07:38:18.67#ibcon#read 5, iclass 27, count 0 2006.218.07:38:18.67#ibcon#about to read 6, iclass 27, count 0 2006.218.07:38:18.67#ibcon#read 6, iclass 27, count 0 2006.218.07:38:18.67#ibcon#end of sib2, iclass 27, count 0 2006.218.07:38:18.67#ibcon#*after write, iclass 27, count 0 2006.218.07:38:18.67#ibcon#*before return 0, iclass 27, count 0 2006.218.07:38:18.67#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.218.07:38:18.67#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.218.07:38:18.67#ibcon#about to clear, iclass 27 cls_cnt 0 2006.218.07:38:18.67#ibcon#cleared, iclass 27 cls_cnt 0 2006.218.07:38:18.67$vc4f8/va=3,4 2006.218.07:38:18.67#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.218.07:38:18.67#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.218.07:38:18.67#ibcon#ireg 11 cls_cnt 2 2006.218.07:38:18.67#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.218.07:38:18.68#abcon#{5=INTERFACE CLEAR} 2006.218.07:38:18.72#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.218.07:38:18.72#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.218.07:38:18.72#ibcon#enter wrdev, iclass 32, count 2 2006.218.07:38:18.72#ibcon#first serial, iclass 32, count 2 2006.218.07:38:18.72#ibcon#enter sib2, iclass 32, count 2 2006.218.07:38:18.72#ibcon#flushed, iclass 32, count 2 2006.218.07:38:18.72#ibcon#about to write, iclass 32, count 2 2006.218.07:38:18.72#ibcon#wrote, iclass 32, count 2 2006.218.07:38:18.72#ibcon#about to read 3, iclass 32, count 2 2006.218.07:38:18.74#ibcon#read 3, iclass 32, count 2 2006.218.07:38:18.74#ibcon#about to read 4, iclass 32, count 2 2006.218.07:38:18.74#ibcon#read 4, iclass 32, count 2 2006.218.07:38:18.74#ibcon#about to read 5, iclass 32, count 2 2006.218.07:38:18.74#ibcon#read 5, iclass 32, count 2 2006.218.07:38:18.74#ibcon#about to read 6, iclass 32, count 2 2006.218.07:38:18.74#ibcon#read 6, iclass 32, count 2 2006.218.07:38:18.74#ibcon#end of sib2, iclass 32, count 2 2006.218.07:38:18.74#ibcon#*mode == 0, iclass 32, count 2 2006.218.07:38:18.74#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.218.07:38:18.74#ibcon#[25=AT03-04\r\n] 2006.218.07:38:18.74#ibcon#*before write, iclass 32, count 2 2006.218.07:38:18.74#ibcon#enter sib2, iclass 32, count 2 2006.218.07:38:18.74#ibcon#flushed, iclass 32, count 2 2006.218.07:38:18.74#ibcon#about to write, iclass 32, count 2 2006.218.07:38:18.74#ibcon#wrote, iclass 32, count 2 2006.218.07:38:18.74#ibcon#about to read 3, iclass 32, count 2 2006.218.07:38:18.74#abcon#[5=S1D000X0/0*\r\n] 2006.218.07:38:18.77#ibcon#read 3, iclass 32, count 2 2006.218.07:38:18.77#ibcon#about to read 4, iclass 32, count 2 2006.218.07:38:18.77#ibcon#read 4, iclass 32, count 2 2006.218.07:38:18.77#ibcon#about to read 5, iclass 32, count 2 2006.218.07:38:18.77#ibcon#read 5, iclass 32, count 2 2006.218.07:38:18.77#ibcon#about to read 6, iclass 32, count 2 2006.218.07:38:18.77#ibcon#read 6, iclass 32, count 2 2006.218.07:38:18.77#ibcon#end of sib2, iclass 32, count 2 2006.218.07:38:18.77#ibcon#*after write, iclass 32, count 2 2006.218.07:38:18.77#ibcon#*before return 0, iclass 32, count 2 2006.218.07:38:18.77#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.218.07:38:18.77#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.218.07:38:18.77#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.218.07:38:18.77#ibcon#ireg 7 cls_cnt 0 2006.218.07:38:18.77#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.218.07:38:18.89#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.218.07:38:18.89#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.218.07:38:18.89#ibcon#enter wrdev, iclass 32, count 0 2006.218.07:38:18.89#ibcon#first serial, iclass 32, count 0 2006.218.07:38:18.89#ibcon#enter sib2, iclass 32, count 0 2006.218.07:38:18.89#ibcon#flushed, iclass 32, count 0 2006.218.07:38:18.89#ibcon#about to write, iclass 32, count 0 2006.218.07:38:18.89#ibcon#wrote, iclass 32, count 0 2006.218.07:38:18.89#ibcon#about to read 3, iclass 32, count 0 2006.218.07:38:18.91#ibcon#read 3, iclass 32, count 0 2006.218.07:38:18.91#ibcon#about to read 4, iclass 32, count 0 2006.218.07:38:18.91#ibcon#read 4, iclass 32, count 0 2006.218.07:38:18.91#ibcon#about to read 5, iclass 32, count 0 2006.218.07:38:18.91#ibcon#read 5, iclass 32, count 0 2006.218.07:38:18.91#ibcon#about to read 6, iclass 32, count 0 2006.218.07:38:18.91#ibcon#read 6, iclass 32, count 0 2006.218.07:38:18.91#ibcon#end of sib2, iclass 32, count 0 2006.218.07:38:18.91#ibcon#*mode == 0, iclass 32, count 0 2006.218.07:38:18.91#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.218.07:38:18.91#ibcon#[25=USB\r\n] 2006.218.07:38:18.91#ibcon#*before write, iclass 32, count 0 2006.218.07:38:18.91#ibcon#enter sib2, iclass 32, count 0 2006.218.07:38:18.91#ibcon#flushed, iclass 32, count 0 2006.218.07:38:18.91#ibcon#about to write, iclass 32, count 0 2006.218.07:38:18.91#ibcon#wrote, iclass 32, count 0 2006.218.07:38:18.91#ibcon#about to read 3, iclass 32, count 0 2006.218.07:38:18.94#ibcon#read 3, iclass 32, count 0 2006.218.07:38:18.94#ibcon#about to read 4, iclass 32, count 0 2006.218.07:38:18.94#ibcon#read 4, iclass 32, count 0 2006.218.07:38:18.94#ibcon#about to read 5, iclass 32, count 0 2006.218.07:38:18.94#ibcon#read 5, iclass 32, count 0 2006.218.07:38:18.94#ibcon#about to read 6, iclass 32, count 0 2006.218.07:38:18.94#ibcon#read 6, iclass 32, count 0 2006.218.07:38:18.94#ibcon#end of sib2, iclass 32, count 0 2006.218.07:38:18.94#ibcon#*after write, iclass 32, count 0 2006.218.07:38:18.94#ibcon#*before return 0, iclass 32, count 0 2006.218.07:38:18.94#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.218.07:38:18.94#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.218.07:38:18.94#ibcon#about to clear, iclass 32 cls_cnt 0 2006.218.07:38:18.94#ibcon#cleared, iclass 32 cls_cnt 0 2006.218.07:38:18.94$vc4f8/valo=4,832.99 2006.218.07:38:18.94#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.218.07:38:18.94#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.218.07:38:18.94#ibcon#ireg 17 cls_cnt 0 2006.218.07:38:18.94#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.218.07:38:18.94#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.218.07:38:18.94#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.218.07:38:18.94#ibcon#enter wrdev, iclass 35, count 0 2006.218.07:38:18.94#ibcon#first serial, iclass 35, count 0 2006.218.07:38:18.94#ibcon#enter sib2, iclass 35, count 0 2006.218.07:38:18.94#ibcon#flushed, iclass 35, count 0 2006.218.07:38:18.94#ibcon#about to write, iclass 35, count 0 2006.218.07:38:18.94#ibcon#wrote, iclass 35, count 0 2006.218.07:38:18.94#ibcon#about to read 3, iclass 35, count 0 2006.218.07:38:18.96#ibcon#read 3, iclass 35, count 0 2006.218.07:38:18.96#ibcon#about to read 4, iclass 35, count 0 2006.218.07:38:18.96#ibcon#read 4, iclass 35, count 0 2006.218.07:38:18.96#ibcon#about to read 5, iclass 35, count 0 2006.218.07:38:18.96#ibcon#read 5, iclass 35, count 0 2006.218.07:38:18.96#ibcon#about to read 6, iclass 35, count 0 2006.218.07:38:18.96#ibcon#read 6, iclass 35, count 0 2006.218.07:38:18.96#ibcon#end of sib2, iclass 35, count 0 2006.218.07:38:18.96#ibcon#*mode == 0, iclass 35, count 0 2006.218.07:38:18.96#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.218.07:38:18.96#ibcon#[26=FRQ=04,832.99\r\n] 2006.218.07:38:18.96#ibcon#*before write, iclass 35, count 0 2006.218.07:38:18.96#ibcon#enter sib2, iclass 35, count 0 2006.218.07:38:18.96#ibcon#flushed, iclass 35, count 0 2006.218.07:38:18.96#ibcon#about to write, iclass 35, count 0 2006.218.07:38:18.96#ibcon#wrote, iclass 35, count 0 2006.218.07:38:18.96#ibcon#about to read 3, iclass 35, count 0 2006.218.07:38:19.01#ibcon#read 3, iclass 35, count 0 2006.218.07:38:19.01#ibcon#about to read 4, iclass 35, count 0 2006.218.07:38:19.01#ibcon#read 4, iclass 35, count 0 2006.218.07:38:19.01#ibcon#about to read 5, iclass 35, count 0 2006.218.07:38:19.01#ibcon#read 5, iclass 35, count 0 2006.218.07:38:19.01#ibcon#about to read 6, iclass 35, count 0 2006.218.07:38:19.01#ibcon#read 6, iclass 35, count 0 2006.218.07:38:19.01#ibcon#end of sib2, iclass 35, count 0 2006.218.07:38:19.01#ibcon#*after write, iclass 35, count 0 2006.218.07:38:19.01#ibcon#*before return 0, iclass 35, count 0 2006.218.07:38:19.01#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.218.07:38:19.01#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.218.07:38:19.01#ibcon#about to clear, iclass 35 cls_cnt 0 2006.218.07:38:19.01#ibcon#cleared, iclass 35 cls_cnt 0 2006.218.07:38:19.01$vc4f8/va=4,4 2006.218.07:38:19.01#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.218.07:38:19.01#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.218.07:38:19.01#ibcon#ireg 11 cls_cnt 2 2006.218.07:38:19.01#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.218.07:38:19.06#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.218.07:38:19.06#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.218.07:38:19.06#ibcon#enter wrdev, iclass 37, count 2 2006.218.07:38:19.06#ibcon#first serial, iclass 37, count 2 2006.218.07:38:19.06#ibcon#enter sib2, iclass 37, count 2 2006.218.07:38:19.06#ibcon#flushed, iclass 37, count 2 2006.218.07:38:19.06#ibcon#about to write, iclass 37, count 2 2006.218.07:38:19.06#ibcon#wrote, iclass 37, count 2 2006.218.07:38:19.06#ibcon#about to read 3, iclass 37, count 2 2006.218.07:38:19.08#ibcon#read 3, iclass 37, count 2 2006.218.07:38:19.08#ibcon#about to read 4, iclass 37, count 2 2006.218.07:38:19.08#ibcon#read 4, iclass 37, count 2 2006.218.07:38:19.08#ibcon#about to read 5, iclass 37, count 2 2006.218.07:38:19.08#ibcon#read 5, iclass 37, count 2 2006.218.07:38:19.08#ibcon#about to read 6, iclass 37, count 2 2006.218.07:38:19.08#ibcon#read 6, iclass 37, count 2 2006.218.07:38:19.08#ibcon#end of sib2, iclass 37, count 2 2006.218.07:38:19.08#ibcon#*mode == 0, iclass 37, count 2 2006.218.07:38:19.08#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.218.07:38:19.08#ibcon#[25=AT04-04\r\n] 2006.218.07:38:19.08#ibcon#*before write, iclass 37, count 2 2006.218.07:38:19.08#ibcon#enter sib2, iclass 37, count 2 2006.218.07:38:19.08#ibcon#flushed, iclass 37, count 2 2006.218.07:38:19.08#ibcon#about to write, iclass 37, count 2 2006.218.07:38:19.08#ibcon#wrote, iclass 37, count 2 2006.218.07:38:19.08#ibcon#about to read 3, iclass 37, count 2 2006.218.07:38:19.11#ibcon#read 3, iclass 37, count 2 2006.218.07:38:19.11#ibcon#about to read 4, iclass 37, count 2 2006.218.07:38:19.11#ibcon#read 4, iclass 37, count 2 2006.218.07:38:19.11#ibcon#about to read 5, iclass 37, count 2 2006.218.07:38:19.11#ibcon#read 5, iclass 37, count 2 2006.218.07:38:19.11#ibcon#about to read 6, iclass 37, count 2 2006.218.07:38:19.11#ibcon#read 6, iclass 37, count 2 2006.218.07:38:19.11#ibcon#end of sib2, iclass 37, count 2 2006.218.07:38:19.11#ibcon#*after write, iclass 37, count 2 2006.218.07:38:19.11#ibcon#*before return 0, iclass 37, count 2 2006.218.07:38:19.11#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.218.07:38:19.11#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.218.07:38:19.11#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.218.07:38:19.11#ibcon#ireg 7 cls_cnt 0 2006.218.07:38:19.11#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.218.07:38:19.23#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.218.07:38:19.23#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.218.07:38:19.23#ibcon#enter wrdev, iclass 37, count 0 2006.218.07:38:19.23#ibcon#first serial, iclass 37, count 0 2006.218.07:38:19.23#ibcon#enter sib2, iclass 37, count 0 2006.218.07:38:19.23#ibcon#flushed, iclass 37, count 0 2006.218.07:38:19.23#ibcon#about to write, iclass 37, count 0 2006.218.07:38:19.23#ibcon#wrote, iclass 37, count 0 2006.218.07:38:19.23#ibcon#about to read 3, iclass 37, count 0 2006.218.07:38:19.25#ibcon#read 3, iclass 37, count 0 2006.218.07:38:19.25#ibcon#about to read 4, iclass 37, count 0 2006.218.07:38:19.25#ibcon#read 4, iclass 37, count 0 2006.218.07:38:19.25#ibcon#about to read 5, iclass 37, count 0 2006.218.07:38:19.25#ibcon#read 5, iclass 37, count 0 2006.218.07:38:19.25#ibcon#about to read 6, iclass 37, count 0 2006.218.07:38:19.25#ibcon#read 6, iclass 37, count 0 2006.218.07:38:19.25#ibcon#end of sib2, iclass 37, count 0 2006.218.07:38:19.25#ibcon#*mode == 0, iclass 37, count 0 2006.218.07:38:19.25#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.218.07:38:19.25#ibcon#[25=USB\r\n] 2006.218.07:38:19.25#ibcon#*before write, iclass 37, count 0 2006.218.07:38:19.25#ibcon#enter sib2, iclass 37, count 0 2006.218.07:38:19.25#ibcon#flushed, iclass 37, count 0 2006.218.07:38:19.25#ibcon#about to write, iclass 37, count 0 2006.218.07:38:19.25#ibcon#wrote, iclass 37, count 0 2006.218.07:38:19.25#ibcon#about to read 3, iclass 37, count 0 2006.218.07:38:19.28#ibcon#read 3, iclass 37, count 0 2006.218.07:38:19.28#ibcon#about to read 4, iclass 37, count 0 2006.218.07:38:19.28#ibcon#read 4, iclass 37, count 0 2006.218.07:38:19.28#ibcon#about to read 5, iclass 37, count 0 2006.218.07:38:19.28#ibcon#read 5, iclass 37, count 0 2006.218.07:38:19.28#ibcon#about to read 6, iclass 37, count 0 2006.218.07:38:19.28#ibcon#read 6, iclass 37, count 0 2006.218.07:38:19.28#ibcon#end of sib2, iclass 37, count 0 2006.218.07:38:19.28#ibcon#*after write, iclass 37, count 0 2006.218.07:38:19.28#ibcon#*before return 0, iclass 37, count 0 2006.218.07:38:19.28#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.218.07:38:19.28#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.218.07:38:19.28#ibcon#about to clear, iclass 37 cls_cnt 0 2006.218.07:38:19.28#ibcon#cleared, iclass 37 cls_cnt 0 2006.218.07:38:19.28$vc4f8/valo=5,652.99 2006.218.07:38:19.28#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.218.07:38:19.28#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.218.07:38:19.28#ibcon#ireg 17 cls_cnt 0 2006.218.07:38:19.28#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.218.07:38:19.28#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.218.07:38:19.28#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.218.07:38:19.28#ibcon#enter wrdev, iclass 39, count 0 2006.218.07:38:19.28#ibcon#first serial, iclass 39, count 0 2006.218.07:38:19.28#ibcon#enter sib2, iclass 39, count 0 2006.218.07:38:19.28#ibcon#flushed, iclass 39, count 0 2006.218.07:38:19.28#ibcon#about to write, iclass 39, count 0 2006.218.07:38:19.28#ibcon#wrote, iclass 39, count 0 2006.218.07:38:19.28#ibcon#about to read 3, iclass 39, count 0 2006.218.07:38:19.30#ibcon#read 3, iclass 39, count 0 2006.218.07:38:19.30#ibcon#about to read 4, iclass 39, count 0 2006.218.07:38:19.30#ibcon#read 4, iclass 39, count 0 2006.218.07:38:19.30#ibcon#about to read 5, iclass 39, count 0 2006.218.07:38:19.30#ibcon#read 5, iclass 39, count 0 2006.218.07:38:19.30#ibcon#about to read 6, iclass 39, count 0 2006.218.07:38:19.30#ibcon#read 6, iclass 39, count 0 2006.218.07:38:19.30#ibcon#end of sib2, iclass 39, count 0 2006.218.07:38:19.30#ibcon#*mode == 0, iclass 39, count 0 2006.218.07:38:19.30#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.218.07:38:19.30#ibcon#[26=FRQ=05,652.99\r\n] 2006.218.07:38:19.30#ibcon#*before write, iclass 39, count 0 2006.218.07:38:19.30#ibcon#enter sib2, iclass 39, count 0 2006.218.07:38:19.30#ibcon#flushed, iclass 39, count 0 2006.218.07:38:19.30#ibcon#about to write, iclass 39, count 0 2006.218.07:38:19.30#ibcon#wrote, iclass 39, count 0 2006.218.07:38:19.30#ibcon#about to read 3, iclass 39, count 0 2006.218.07:38:19.34#ibcon#read 3, iclass 39, count 0 2006.218.07:38:19.34#ibcon#about to read 4, iclass 39, count 0 2006.218.07:38:19.34#ibcon#read 4, iclass 39, count 0 2006.218.07:38:19.34#ibcon#about to read 5, iclass 39, count 0 2006.218.07:38:19.34#ibcon#read 5, iclass 39, count 0 2006.218.07:38:19.34#ibcon#about to read 6, iclass 39, count 0 2006.218.07:38:19.34#ibcon#read 6, iclass 39, count 0 2006.218.07:38:19.34#ibcon#end of sib2, iclass 39, count 0 2006.218.07:38:19.34#ibcon#*after write, iclass 39, count 0 2006.218.07:38:19.34#ibcon#*before return 0, iclass 39, count 0 2006.218.07:38:19.34#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.218.07:38:19.34#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.218.07:38:19.34#ibcon#about to clear, iclass 39 cls_cnt 0 2006.218.07:38:19.34#ibcon#cleared, iclass 39 cls_cnt 0 2006.218.07:38:19.34$vc4f8/va=5,7 2006.218.07:38:19.34#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.218.07:38:19.34#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.218.07:38:19.34#ibcon#ireg 11 cls_cnt 2 2006.218.07:38:19.34#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.218.07:38:19.40#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.218.07:38:19.40#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.218.07:38:19.40#ibcon#enter wrdev, iclass 3, count 2 2006.218.07:38:19.40#ibcon#first serial, iclass 3, count 2 2006.218.07:38:19.40#ibcon#enter sib2, iclass 3, count 2 2006.218.07:38:19.40#ibcon#flushed, iclass 3, count 2 2006.218.07:38:19.40#ibcon#about to write, iclass 3, count 2 2006.218.07:38:19.40#ibcon#wrote, iclass 3, count 2 2006.218.07:38:19.40#ibcon#about to read 3, iclass 3, count 2 2006.218.07:38:19.42#ibcon#read 3, iclass 3, count 2 2006.218.07:38:19.42#ibcon#about to read 4, iclass 3, count 2 2006.218.07:38:19.42#ibcon#read 4, iclass 3, count 2 2006.218.07:38:19.42#ibcon#about to read 5, iclass 3, count 2 2006.218.07:38:19.42#ibcon#read 5, iclass 3, count 2 2006.218.07:38:19.42#ibcon#about to read 6, iclass 3, count 2 2006.218.07:38:19.42#ibcon#read 6, iclass 3, count 2 2006.218.07:38:19.42#ibcon#end of sib2, iclass 3, count 2 2006.218.07:38:19.42#ibcon#*mode == 0, iclass 3, count 2 2006.218.07:38:19.42#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.218.07:38:19.42#ibcon#[25=AT05-07\r\n] 2006.218.07:38:19.42#ibcon#*before write, iclass 3, count 2 2006.218.07:38:19.42#ibcon#enter sib2, iclass 3, count 2 2006.218.07:38:19.42#ibcon#flushed, iclass 3, count 2 2006.218.07:38:19.42#ibcon#about to write, iclass 3, count 2 2006.218.07:38:19.42#ibcon#wrote, iclass 3, count 2 2006.218.07:38:19.42#ibcon#about to read 3, iclass 3, count 2 2006.218.07:38:19.45#ibcon#read 3, iclass 3, count 2 2006.218.07:38:19.45#ibcon#about to read 4, iclass 3, count 2 2006.218.07:38:19.45#ibcon#read 4, iclass 3, count 2 2006.218.07:38:19.45#ibcon#about to read 5, iclass 3, count 2 2006.218.07:38:19.45#ibcon#read 5, iclass 3, count 2 2006.218.07:38:19.45#ibcon#about to read 6, iclass 3, count 2 2006.218.07:38:19.45#ibcon#read 6, iclass 3, count 2 2006.218.07:38:19.45#ibcon#end of sib2, iclass 3, count 2 2006.218.07:38:19.45#ibcon#*after write, iclass 3, count 2 2006.218.07:38:19.45#ibcon#*before return 0, iclass 3, count 2 2006.218.07:38:19.45#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.218.07:38:19.45#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.218.07:38:19.45#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.218.07:38:19.45#ibcon#ireg 7 cls_cnt 0 2006.218.07:38:19.45#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.218.07:38:19.57#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.218.07:38:19.57#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.218.07:38:19.57#ibcon#enter wrdev, iclass 3, count 0 2006.218.07:38:19.57#ibcon#first serial, iclass 3, count 0 2006.218.07:38:19.57#ibcon#enter sib2, iclass 3, count 0 2006.218.07:38:19.57#ibcon#flushed, iclass 3, count 0 2006.218.07:38:19.57#ibcon#about to write, iclass 3, count 0 2006.218.07:38:19.57#ibcon#wrote, iclass 3, count 0 2006.218.07:38:19.57#ibcon#about to read 3, iclass 3, count 0 2006.218.07:38:19.59#ibcon#read 3, iclass 3, count 0 2006.218.07:38:19.59#ibcon#about to read 4, iclass 3, count 0 2006.218.07:38:19.59#ibcon#read 4, iclass 3, count 0 2006.218.07:38:19.59#ibcon#about to read 5, iclass 3, count 0 2006.218.07:38:19.59#ibcon#read 5, iclass 3, count 0 2006.218.07:38:19.59#ibcon#about to read 6, iclass 3, count 0 2006.218.07:38:19.59#ibcon#read 6, iclass 3, count 0 2006.218.07:38:19.59#ibcon#end of sib2, iclass 3, count 0 2006.218.07:38:19.59#ibcon#*mode == 0, iclass 3, count 0 2006.218.07:38:19.59#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.218.07:38:19.59#ibcon#[25=USB\r\n] 2006.218.07:38:19.59#ibcon#*before write, iclass 3, count 0 2006.218.07:38:19.59#ibcon#enter sib2, iclass 3, count 0 2006.218.07:38:19.59#ibcon#flushed, iclass 3, count 0 2006.218.07:38:19.59#ibcon#about to write, iclass 3, count 0 2006.218.07:38:19.59#ibcon#wrote, iclass 3, count 0 2006.218.07:38:19.59#ibcon#about to read 3, iclass 3, count 0 2006.218.07:38:19.62#ibcon#read 3, iclass 3, count 0 2006.218.07:38:19.62#ibcon#about to read 4, iclass 3, count 0 2006.218.07:38:19.62#ibcon#read 4, iclass 3, count 0 2006.218.07:38:19.62#ibcon#about to read 5, iclass 3, count 0 2006.218.07:38:19.62#ibcon#read 5, iclass 3, count 0 2006.218.07:38:19.62#ibcon#about to read 6, iclass 3, count 0 2006.218.07:38:19.62#ibcon#read 6, iclass 3, count 0 2006.218.07:38:19.62#ibcon#end of sib2, iclass 3, count 0 2006.218.07:38:19.62#ibcon#*after write, iclass 3, count 0 2006.218.07:38:19.62#ibcon#*before return 0, iclass 3, count 0 2006.218.07:38:19.62#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.218.07:38:19.62#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.218.07:38:19.62#ibcon#about to clear, iclass 3 cls_cnt 0 2006.218.07:38:19.62#ibcon#cleared, iclass 3 cls_cnt 0 2006.218.07:38:19.62$vc4f8/valo=6,772.99 2006.218.07:38:19.62#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.218.07:38:19.62#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.218.07:38:19.62#ibcon#ireg 17 cls_cnt 0 2006.218.07:38:19.62#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.218.07:38:19.62#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.218.07:38:19.62#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.218.07:38:19.62#ibcon#enter wrdev, iclass 5, count 0 2006.218.07:38:19.62#ibcon#first serial, iclass 5, count 0 2006.218.07:38:19.62#ibcon#enter sib2, iclass 5, count 0 2006.218.07:38:19.62#ibcon#flushed, iclass 5, count 0 2006.218.07:38:19.62#ibcon#about to write, iclass 5, count 0 2006.218.07:38:19.62#ibcon#wrote, iclass 5, count 0 2006.218.07:38:19.62#ibcon#about to read 3, iclass 5, count 0 2006.218.07:38:19.64#ibcon#read 3, iclass 5, count 0 2006.218.07:38:19.64#ibcon#about to read 4, iclass 5, count 0 2006.218.07:38:19.64#ibcon#read 4, iclass 5, count 0 2006.218.07:38:19.64#ibcon#about to read 5, iclass 5, count 0 2006.218.07:38:19.64#ibcon#read 5, iclass 5, count 0 2006.218.07:38:19.64#ibcon#about to read 6, iclass 5, count 0 2006.218.07:38:19.64#ibcon#read 6, iclass 5, count 0 2006.218.07:38:19.64#ibcon#end of sib2, iclass 5, count 0 2006.218.07:38:19.64#ibcon#*mode == 0, iclass 5, count 0 2006.218.07:38:19.64#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.218.07:38:19.64#ibcon#[26=FRQ=06,772.99\r\n] 2006.218.07:38:19.64#ibcon#*before write, iclass 5, count 0 2006.218.07:38:19.64#ibcon#enter sib2, iclass 5, count 0 2006.218.07:38:19.64#ibcon#flushed, iclass 5, count 0 2006.218.07:38:19.64#ibcon#about to write, iclass 5, count 0 2006.218.07:38:19.64#ibcon#wrote, iclass 5, count 0 2006.218.07:38:19.64#ibcon#about to read 3, iclass 5, count 0 2006.218.07:38:19.69#ibcon#read 3, iclass 5, count 0 2006.218.07:38:19.69#ibcon#about to read 4, iclass 5, count 0 2006.218.07:38:19.69#ibcon#read 4, iclass 5, count 0 2006.218.07:38:19.69#ibcon#about to read 5, iclass 5, count 0 2006.218.07:38:19.69#ibcon#read 5, iclass 5, count 0 2006.218.07:38:19.69#ibcon#about to read 6, iclass 5, count 0 2006.218.07:38:19.69#ibcon#read 6, iclass 5, count 0 2006.218.07:38:19.69#ibcon#end of sib2, iclass 5, count 0 2006.218.07:38:19.69#ibcon#*after write, iclass 5, count 0 2006.218.07:38:19.69#ibcon#*before return 0, iclass 5, count 0 2006.218.07:38:19.69#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.218.07:38:19.69#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.218.07:38:19.69#ibcon#about to clear, iclass 5 cls_cnt 0 2006.218.07:38:19.69#ibcon#cleared, iclass 5 cls_cnt 0 2006.218.07:38:19.69$vc4f8/va=6,6 2006.218.07:38:19.69#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.218.07:38:19.69#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.218.07:38:19.69#ibcon#ireg 11 cls_cnt 2 2006.218.07:38:19.69#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.218.07:38:19.74#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.218.07:38:19.74#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.218.07:38:19.74#ibcon#enter wrdev, iclass 7, count 2 2006.218.07:38:19.74#ibcon#first serial, iclass 7, count 2 2006.218.07:38:19.74#ibcon#enter sib2, iclass 7, count 2 2006.218.07:38:19.74#ibcon#flushed, iclass 7, count 2 2006.218.07:38:19.74#ibcon#about to write, iclass 7, count 2 2006.218.07:38:19.74#ibcon#wrote, iclass 7, count 2 2006.218.07:38:19.74#ibcon#about to read 3, iclass 7, count 2 2006.218.07:38:19.76#ibcon#read 3, iclass 7, count 2 2006.218.07:38:19.76#ibcon#about to read 4, iclass 7, count 2 2006.218.07:38:19.76#ibcon#read 4, iclass 7, count 2 2006.218.07:38:19.76#ibcon#about to read 5, iclass 7, count 2 2006.218.07:38:19.76#ibcon#read 5, iclass 7, count 2 2006.218.07:38:19.76#ibcon#about to read 6, iclass 7, count 2 2006.218.07:38:19.76#ibcon#read 6, iclass 7, count 2 2006.218.07:38:19.76#ibcon#end of sib2, iclass 7, count 2 2006.218.07:38:19.76#ibcon#*mode == 0, iclass 7, count 2 2006.218.07:38:19.76#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.218.07:38:19.76#ibcon#[25=AT06-06\r\n] 2006.218.07:38:19.76#ibcon#*before write, iclass 7, count 2 2006.218.07:38:19.76#ibcon#enter sib2, iclass 7, count 2 2006.218.07:38:19.76#ibcon#flushed, iclass 7, count 2 2006.218.07:38:19.76#ibcon#about to write, iclass 7, count 2 2006.218.07:38:19.76#ibcon#wrote, iclass 7, count 2 2006.218.07:38:19.76#ibcon#about to read 3, iclass 7, count 2 2006.218.07:38:19.79#ibcon#read 3, iclass 7, count 2 2006.218.07:38:19.79#ibcon#about to read 4, iclass 7, count 2 2006.218.07:38:19.79#ibcon#read 4, iclass 7, count 2 2006.218.07:38:19.79#ibcon#about to read 5, iclass 7, count 2 2006.218.07:38:19.79#ibcon#read 5, iclass 7, count 2 2006.218.07:38:19.79#ibcon#about to read 6, iclass 7, count 2 2006.218.07:38:19.79#ibcon#read 6, iclass 7, count 2 2006.218.07:38:19.79#ibcon#end of sib2, iclass 7, count 2 2006.218.07:38:19.79#ibcon#*after write, iclass 7, count 2 2006.218.07:38:19.79#ibcon#*before return 0, iclass 7, count 2 2006.218.07:38:19.79#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.218.07:38:19.79#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.218.07:38:19.79#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.218.07:38:19.79#ibcon#ireg 7 cls_cnt 0 2006.218.07:38:19.79#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.218.07:38:19.91#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.218.07:38:19.91#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.218.07:38:19.91#ibcon#enter wrdev, iclass 7, count 0 2006.218.07:38:19.91#ibcon#first serial, iclass 7, count 0 2006.218.07:38:19.91#ibcon#enter sib2, iclass 7, count 0 2006.218.07:38:19.91#ibcon#flushed, iclass 7, count 0 2006.218.07:38:19.91#ibcon#about to write, iclass 7, count 0 2006.218.07:38:19.91#ibcon#wrote, iclass 7, count 0 2006.218.07:38:19.91#ibcon#about to read 3, iclass 7, count 0 2006.218.07:38:19.93#ibcon#read 3, iclass 7, count 0 2006.218.07:38:19.93#ibcon#about to read 4, iclass 7, count 0 2006.218.07:38:19.93#ibcon#read 4, iclass 7, count 0 2006.218.07:38:19.93#ibcon#about to read 5, iclass 7, count 0 2006.218.07:38:19.93#ibcon#read 5, iclass 7, count 0 2006.218.07:38:19.93#ibcon#about to read 6, iclass 7, count 0 2006.218.07:38:19.93#ibcon#read 6, iclass 7, count 0 2006.218.07:38:19.93#ibcon#end of sib2, iclass 7, count 0 2006.218.07:38:19.93#ibcon#*mode == 0, iclass 7, count 0 2006.218.07:38:19.93#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.218.07:38:19.93#ibcon#[25=USB\r\n] 2006.218.07:38:19.93#ibcon#*before write, iclass 7, count 0 2006.218.07:38:19.93#ibcon#enter sib2, iclass 7, count 0 2006.218.07:38:19.93#ibcon#flushed, iclass 7, count 0 2006.218.07:38:19.93#ibcon#about to write, iclass 7, count 0 2006.218.07:38:19.93#ibcon#wrote, iclass 7, count 0 2006.218.07:38:19.93#ibcon#about to read 3, iclass 7, count 0 2006.218.07:38:19.96#ibcon#read 3, iclass 7, count 0 2006.218.07:38:19.96#ibcon#about to read 4, iclass 7, count 0 2006.218.07:38:19.96#ibcon#read 4, iclass 7, count 0 2006.218.07:38:19.96#ibcon#about to read 5, iclass 7, count 0 2006.218.07:38:19.96#ibcon#read 5, iclass 7, count 0 2006.218.07:38:19.96#ibcon#about to read 6, iclass 7, count 0 2006.218.07:38:19.96#ibcon#read 6, iclass 7, count 0 2006.218.07:38:19.96#ibcon#end of sib2, iclass 7, count 0 2006.218.07:38:19.96#ibcon#*after write, iclass 7, count 0 2006.218.07:38:19.96#ibcon#*before return 0, iclass 7, count 0 2006.218.07:38:19.96#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.218.07:38:19.96#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.218.07:38:19.96#ibcon#about to clear, iclass 7 cls_cnt 0 2006.218.07:38:19.96#ibcon#cleared, iclass 7 cls_cnt 0 2006.218.07:38:19.96$vc4f8/valo=7,832.99 2006.218.07:38:19.96#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.218.07:38:19.96#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.218.07:38:19.96#ibcon#ireg 17 cls_cnt 0 2006.218.07:38:19.96#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.218.07:38:19.96#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.218.07:38:19.96#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.218.07:38:19.96#ibcon#enter wrdev, iclass 11, count 0 2006.218.07:38:19.96#ibcon#first serial, iclass 11, count 0 2006.218.07:38:19.96#ibcon#enter sib2, iclass 11, count 0 2006.218.07:38:19.96#ibcon#flushed, iclass 11, count 0 2006.218.07:38:19.96#ibcon#about to write, iclass 11, count 0 2006.218.07:38:19.96#ibcon#wrote, iclass 11, count 0 2006.218.07:38:19.96#ibcon#about to read 3, iclass 11, count 0 2006.218.07:38:19.98#ibcon#read 3, iclass 11, count 0 2006.218.07:38:19.98#ibcon#about to read 4, iclass 11, count 0 2006.218.07:38:19.98#ibcon#read 4, iclass 11, count 0 2006.218.07:38:19.98#ibcon#about to read 5, iclass 11, count 0 2006.218.07:38:19.98#ibcon#read 5, iclass 11, count 0 2006.218.07:38:19.98#ibcon#about to read 6, iclass 11, count 0 2006.218.07:38:19.98#ibcon#read 6, iclass 11, count 0 2006.218.07:38:19.98#ibcon#end of sib2, iclass 11, count 0 2006.218.07:38:19.98#ibcon#*mode == 0, iclass 11, count 0 2006.218.07:38:19.98#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.218.07:38:19.98#ibcon#[26=FRQ=07,832.99\r\n] 2006.218.07:38:19.98#ibcon#*before write, iclass 11, count 0 2006.218.07:38:19.98#ibcon#enter sib2, iclass 11, count 0 2006.218.07:38:19.98#ibcon#flushed, iclass 11, count 0 2006.218.07:38:19.98#ibcon#about to write, iclass 11, count 0 2006.218.07:38:19.98#ibcon#wrote, iclass 11, count 0 2006.218.07:38:19.98#ibcon#about to read 3, iclass 11, count 0 2006.218.07:38:20.02#ibcon#read 3, iclass 11, count 0 2006.218.07:38:20.02#ibcon#about to read 4, iclass 11, count 0 2006.218.07:38:20.02#ibcon#read 4, iclass 11, count 0 2006.218.07:38:20.02#ibcon#about to read 5, iclass 11, count 0 2006.218.07:38:20.02#ibcon#read 5, iclass 11, count 0 2006.218.07:38:20.02#ibcon#about to read 6, iclass 11, count 0 2006.218.07:38:20.02#ibcon#read 6, iclass 11, count 0 2006.218.07:38:20.02#ibcon#end of sib2, iclass 11, count 0 2006.218.07:38:20.02#ibcon#*after write, iclass 11, count 0 2006.218.07:38:20.02#ibcon#*before return 0, iclass 11, count 0 2006.218.07:38:20.02#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.218.07:38:20.02#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.218.07:38:20.02#ibcon#about to clear, iclass 11 cls_cnt 0 2006.218.07:38:20.02#ibcon#cleared, iclass 11 cls_cnt 0 2006.218.07:38:20.02$vc4f8/va=7,6 2006.218.07:38:20.02#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.218.07:38:20.02#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.218.07:38:20.02#ibcon#ireg 11 cls_cnt 2 2006.218.07:38:20.02#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.218.07:38:20.08#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.218.07:38:20.08#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.218.07:38:20.08#ibcon#enter wrdev, iclass 13, count 2 2006.218.07:38:20.08#ibcon#first serial, iclass 13, count 2 2006.218.07:38:20.08#ibcon#enter sib2, iclass 13, count 2 2006.218.07:38:20.08#ibcon#flushed, iclass 13, count 2 2006.218.07:38:20.08#ibcon#about to write, iclass 13, count 2 2006.218.07:38:20.08#ibcon#wrote, iclass 13, count 2 2006.218.07:38:20.08#ibcon#about to read 3, iclass 13, count 2 2006.218.07:38:20.10#ibcon#read 3, iclass 13, count 2 2006.218.07:38:20.10#ibcon#about to read 4, iclass 13, count 2 2006.218.07:38:20.10#ibcon#read 4, iclass 13, count 2 2006.218.07:38:20.10#ibcon#about to read 5, iclass 13, count 2 2006.218.07:38:20.10#ibcon#read 5, iclass 13, count 2 2006.218.07:38:20.10#ibcon#about to read 6, iclass 13, count 2 2006.218.07:38:20.10#ibcon#read 6, iclass 13, count 2 2006.218.07:38:20.10#ibcon#end of sib2, iclass 13, count 2 2006.218.07:38:20.10#ibcon#*mode == 0, iclass 13, count 2 2006.218.07:38:20.10#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.218.07:38:20.10#ibcon#[25=AT07-06\r\n] 2006.218.07:38:20.10#ibcon#*before write, iclass 13, count 2 2006.218.07:38:20.10#ibcon#enter sib2, iclass 13, count 2 2006.218.07:38:20.10#ibcon#flushed, iclass 13, count 2 2006.218.07:38:20.10#ibcon#about to write, iclass 13, count 2 2006.218.07:38:20.10#ibcon#wrote, iclass 13, count 2 2006.218.07:38:20.10#ibcon#about to read 3, iclass 13, count 2 2006.218.07:38:20.13#ibcon#read 3, iclass 13, count 2 2006.218.07:38:20.13#ibcon#about to read 4, iclass 13, count 2 2006.218.07:38:20.13#ibcon#read 4, iclass 13, count 2 2006.218.07:38:20.13#ibcon#about to read 5, iclass 13, count 2 2006.218.07:38:20.13#ibcon#read 5, iclass 13, count 2 2006.218.07:38:20.13#ibcon#about to read 6, iclass 13, count 2 2006.218.07:38:20.13#ibcon#read 6, iclass 13, count 2 2006.218.07:38:20.13#ibcon#end of sib2, iclass 13, count 2 2006.218.07:38:20.13#ibcon#*after write, iclass 13, count 2 2006.218.07:38:20.13#ibcon#*before return 0, iclass 13, count 2 2006.218.07:38:20.13#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.218.07:38:20.13#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.218.07:38:20.13#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.218.07:38:20.13#ibcon#ireg 7 cls_cnt 0 2006.218.07:38:20.13#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.218.07:38:20.25#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.218.07:38:20.25#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.218.07:38:20.25#ibcon#enter wrdev, iclass 13, count 0 2006.218.07:38:20.25#ibcon#first serial, iclass 13, count 0 2006.218.07:38:20.25#ibcon#enter sib2, iclass 13, count 0 2006.218.07:38:20.25#ibcon#flushed, iclass 13, count 0 2006.218.07:38:20.25#ibcon#about to write, iclass 13, count 0 2006.218.07:38:20.25#ibcon#wrote, iclass 13, count 0 2006.218.07:38:20.25#ibcon#about to read 3, iclass 13, count 0 2006.218.07:38:20.27#ibcon#read 3, iclass 13, count 0 2006.218.07:38:20.27#ibcon#about to read 4, iclass 13, count 0 2006.218.07:38:20.27#ibcon#read 4, iclass 13, count 0 2006.218.07:38:20.27#ibcon#about to read 5, iclass 13, count 0 2006.218.07:38:20.27#ibcon#read 5, iclass 13, count 0 2006.218.07:38:20.27#ibcon#about to read 6, iclass 13, count 0 2006.218.07:38:20.27#ibcon#read 6, iclass 13, count 0 2006.218.07:38:20.27#ibcon#end of sib2, iclass 13, count 0 2006.218.07:38:20.27#ibcon#*mode == 0, iclass 13, count 0 2006.218.07:38:20.27#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.218.07:38:20.27#ibcon#[25=USB\r\n] 2006.218.07:38:20.27#ibcon#*before write, iclass 13, count 0 2006.218.07:38:20.27#ibcon#enter sib2, iclass 13, count 0 2006.218.07:38:20.27#ibcon#flushed, iclass 13, count 0 2006.218.07:38:20.27#ibcon#about to write, iclass 13, count 0 2006.218.07:38:20.27#ibcon#wrote, iclass 13, count 0 2006.218.07:38:20.27#ibcon#about to read 3, iclass 13, count 0 2006.218.07:38:20.30#ibcon#read 3, iclass 13, count 0 2006.218.07:38:20.30#ibcon#about to read 4, iclass 13, count 0 2006.218.07:38:20.30#ibcon#read 4, iclass 13, count 0 2006.218.07:38:20.30#ibcon#about to read 5, iclass 13, count 0 2006.218.07:38:20.30#ibcon#read 5, iclass 13, count 0 2006.218.07:38:20.30#ibcon#about to read 6, iclass 13, count 0 2006.218.07:38:20.30#ibcon#read 6, iclass 13, count 0 2006.218.07:38:20.30#ibcon#end of sib2, iclass 13, count 0 2006.218.07:38:20.30#ibcon#*after write, iclass 13, count 0 2006.218.07:38:20.30#ibcon#*before return 0, iclass 13, count 0 2006.218.07:38:20.30#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.218.07:38:20.30#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.218.07:38:20.30#ibcon#about to clear, iclass 13 cls_cnt 0 2006.218.07:38:20.30#ibcon#cleared, iclass 13 cls_cnt 0 2006.218.07:38:20.30$vc4f8/valo=8,852.99 2006.218.07:38:20.30#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.218.07:38:20.30#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.218.07:38:20.30#ibcon#ireg 17 cls_cnt 0 2006.218.07:38:20.30#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.218.07:38:20.30#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.218.07:38:20.30#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.218.07:38:20.30#ibcon#enter wrdev, iclass 15, count 0 2006.218.07:38:20.30#ibcon#first serial, iclass 15, count 0 2006.218.07:38:20.30#ibcon#enter sib2, iclass 15, count 0 2006.218.07:38:20.30#ibcon#flushed, iclass 15, count 0 2006.218.07:38:20.30#ibcon#about to write, iclass 15, count 0 2006.218.07:38:20.30#ibcon#wrote, iclass 15, count 0 2006.218.07:38:20.30#ibcon#about to read 3, iclass 15, count 0 2006.218.07:38:20.32#ibcon#read 3, iclass 15, count 0 2006.218.07:38:20.32#ibcon#about to read 4, iclass 15, count 0 2006.218.07:38:20.32#ibcon#read 4, iclass 15, count 0 2006.218.07:38:20.32#ibcon#about to read 5, iclass 15, count 0 2006.218.07:38:20.32#ibcon#read 5, iclass 15, count 0 2006.218.07:38:20.32#ibcon#about to read 6, iclass 15, count 0 2006.218.07:38:20.32#ibcon#read 6, iclass 15, count 0 2006.218.07:38:20.32#ibcon#end of sib2, iclass 15, count 0 2006.218.07:38:20.32#ibcon#*mode == 0, iclass 15, count 0 2006.218.07:38:20.32#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.218.07:38:20.32#ibcon#[26=FRQ=08,852.99\r\n] 2006.218.07:38:20.32#ibcon#*before write, iclass 15, count 0 2006.218.07:38:20.32#ibcon#enter sib2, iclass 15, count 0 2006.218.07:38:20.32#ibcon#flushed, iclass 15, count 0 2006.218.07:38:20.32#ibcon#about to write, iclass 15, count 0 2006.218.07:38:20.32#ibcon#wrote, iclass 15, count 0 2006.218.07:38:20.32#ibcon#about to read 3, iclass 15, count 0 2006.218.07:38:20.36#ibcon#read 3, iclass 15, count 0 2006.218.07:38:20.36#ibcon#about to read 4, iclass 15, count 0 2006.218.07:38:20.36#ibcon#read 4, iclass 15, count 0 2006.218.07:38:20.36#ibcon#about to read 5, iclass 15, count 0 2006.218.07:38:20.36#ibcon#read 5, iclass 15, count 0 2006.218.07:38:20.36#ibcon#about to read 6, iclass 15, count 0 2006.218.07:38:20.36#ibcon#read 6, iclass 15, count 0 2006.218.07:38:20.36#ibcon#end of sib2, iclass 15, count 0 2006.218.07:38:20.36#ibcon#*after write, iclass 15, count 0 2006.218.07:38:20.36#ibcon#*before return 0, iclass 15, count 0 2006.218.07:38:20.36#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.218.07:38:20.36#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.218.07:38:20.36#ibcon#about to clear, iclass 15 cls_cnt 0 2006.218.07:38:20.36#ibcon#cleared, iclass 15 cls_cnt 0 2006.218.07:38:20.36$vc4f8/va=8,7 2006.218.07:38:20.36#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.218.07:38:20.36#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.218.07:38:20.36#ibcon#ireg 11 cls_cnt 2 2006.218.07:38:20.36#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.218.07:38:20.42#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.218.07:38:20.42#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.218.07:38:20.42#ibcon#enter wrdev, iclass 17, count 2 2006.218.07:38:20.42#ibcon#first serial, iclass 17, count 2 2006.218.07:38:20.42#ibcon#enter sib2, iclass 17, count 2 2006.218.07:38:20.42#ibcon#flushed, iclass 17, count 2 2006.218.07:38:20.42#ibcon#about to write, iclass 17, count 2 2006.218.07:38:20.42#ibcon#wrote, iclass 17, count 2 2006.218.07:38:20.42#ibcon#about to read 3, iclass 17, count 2 2006.218.07:38:20.44#ibcon#read 3, iclass 17, count 2 2006.218.07:38:20.44#ibcon#about to read 4, iclass 17, count 2 2006.218.07:38:20.44#ibcon#read 4, iclass 17, count 2 2006.218.07:38:20.44#ibcon#about to read 5, iclass 17, count 2 2006.218.07:38:20.44#ibcon#read 5, iclass 17, count 2 2006.218.07:38:20.44#ibcon#about to read 6, iclass 17, count 2 2006.218.07:38:20.44#ibcon#read 6, iclass 17, count 2 2006.218.07:38:20.44#ibcon#end of sib2, iclass 17, count 2 2006.218.07:38:20.44#ibcon#*mode == 0, iclass 17, count 2 2006.218.07:38:20.44#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.218.07:38:20.44#ibcon#[25=AT08-07\r\n] 2006.218.07:38:20.44#ibcon#*before write, iclass 17, count 2 2006.218.07:38:20.44#ibcon#enter sib2, iclass 17, count 2 2006.218.07:38:20.44#ibcon#flushed, iclass 17, count 2 2006.218.07:38:20.44#ibcon#about to write, iclass 17, count 2 2006.218.07:38:20.44#ibcon#wrote, iclass 17, count 2 2006.218.07:38:20.44#ibcon#about to read 3, iclass 17, count 2 2006.218.07:38:20.47#ibcon#read 3, iclass 17, count 2 2006.218.07:38:20.47#ibcon#about to read 4, iclass 17, count 2 2006.218.07:38:20.47#ibcon#read 4, iclass 17, count 2 2006.218.07:38:20.47#ibcon#about to read 5, iclass 17, count 2 2006.218.07:38:20.47#ibcon#read 5, iclass 17, count 2 2006.218.07:38:20.47#ibcon#about to read 6, iclass 17, count 2 2006.218.07:38:20.47#ibcon#read 6, iclass 17, count 2 2006.218.07:38:20.47#ibcon#end of sib2, iclass 17, count 2 2006.218.07:38:20.47#ibcon#*after write, iclass 17, count 2 2006.218.07:38:20.47#ibcon#*before return 0, iclass 17, count 2 2006.218.07:38:20.47#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.218.07:38:20.47#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.218.07:38:20.47#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.218.07:38:20.47#ibcon#ireg 7 cls_cnt 0 2006.218.07:38:20.47#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.218.07:38:20.59#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.218.07:38:20.59#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.218.07:38:20.59#ibcon#enter wrdev, iclass 17, count 0 2006.218.07:38:20.59#ibcon#first serial, iclass 17, count 0 2006.218.07:38:20.59#ibcon#enter sib2, iclass 17, count 0 2006.218.07:38:20.59#ibcon#flushed, iclass 17, count 0 2006.218.07:38:20.59#ibcon#about to write, iclass 17, count 0 2006.218.07:38:20.59#ibcon#wrote, iclass 17, count 0 2006.218.07:38:20.59#ibcon#about to read 3, iclass 17, count 0 2006.218.07:38:20.61#ibcon#read 3, iclass 17, count 0 2006.218.07:38:20.61#ibcon#about to read 4, iclass 17, count 0 2006.218.07:38:20.61#ibcon#read 4, iclass 17, count 0 2006.218.07:38:20.61#ibcon#about to read 5, iclass 17, count 0 2006.218.07:38:20.61#ibcon#read 5, iclass 17, count 0 2006.218.07:38:20.61#ibcon#about to read 6, iclass 17, count 0 2006.218.07:38:20.61#ibcon#read 6, iclass 17, count 0 2006.218.07:38:20.61#ibcon#end of sib2, iclass 17, count 0 2006.218.07:38:20.61#ibcon#*mode == 0, iclass 17, count 0 2006.218.07:38:20.61#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.218.07:38:20.61#ibcon#[25=USB\r\n] 2006.218.07:38:20.61#ibcon#*before write, iclass 17, count 0 2006.218.07:38:20.61#ibcon#enter sib2, iclass 17, count 0 2006.218.07:38:20.61#ibcon#flushed, iclass 17, count 0 2006.218.07:38:20.61#ibcon#about to write, iclass 17, count 0 2006.218.07:38:20.61#ibcon#wrote, iclass 17, count 0 2006.218.07:38:20.61#ibcon#about to read 3, iclass 17, count 0 2006.218.07:38:20.64#ibcon#read 3, iclass 17, count 0 2006.218.07:38:20.64#ibcon#about to read 4, iclass 17, count 0 2006.218.07:38:20.64#ibcon#read 4, iclass 17, count 0 2006.218.07:38:20.64#ibcon#about to read 5, iclass 17, count 0 2006.218.07:38:20.64#ibcon#read 5, iclass 17, count 0 2006.218.07:38:20.64#ibcon#about to read 6, iclass 17, count 0 2006.218.07:38:20.64#ibcon#read 6, iclass 17, count 0 2006.218.07:38:20.64#ibcon#end of sib2, iclass 17, count 0 2006.218.07:38:20.64#ibcon#*after write, iclass 17, count 0 2006.218.07:38:20.64#ibcon#*before return 0, iclass 17, count 0 2006.218.07:38:20.64#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.218.07:38:20.64#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.218.07:38:20.64#ibcon#about to clear, iclass 17 cls_cnt 0 2006.218.07:38:20.64#ibcon#cleared, iclass 17 cls_cnt 0 2006.218.07:38:20.64$vc4f8/vblo=1,632.99 2006.218.07:38:20.64#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.218.07:38:20.64#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.218.07:38:20.64#ibcon#ireg 17 cls_cnt 0 2006.218.07:38:20.64#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.218.07:38:20.64#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.218.07:38:20.64#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.218.07:38:20.64#ibcon#enter wrdev, iclass 19, count 0 2006.218.07:38:20.64#ibcon#first serial, iclass 19, count 0 2006.218.07:38:20.64#ibcon#enter sib2, iclass 19, count 0 2006.218.07:38:20.64#ibcon#flushed, iclass 19, count 0 2006.218.07:38:20.64#ibcon#about to write, iclass 19, count 0 2006.218.07:38:20.64#ibcon#wrote, iclass 19, count 0 2006.218.07:38:20.64#ibcon#about to read 3, iclass 19, count 0 2006.218.07:38:20.66#ibcon#read 3, iclass 19, count 0 2006.218.07:38:20.66#ibcon#about to read 4, iclass 19, count 0 2006.218.07:38:20.66#ibcon#read 4, iclass 19, count 0 2006.218.07:38:20.66#ibcon#about to read 5, iclass 19, count 0 2006.218.07:38:20.66#ibcon#read 5, iclass 19, count 0 2006.218.07:38:20.66#ibcon#about to read 6, iclass 19, count 0 2006.218.07:38:20.66#ibcon#read 6, iclass 19, count 0 2006.218.07:38:20.66#ibcon#end of sib2, iclass 19, count 0 2006.218.07:38:20.66#ibcon#*mode == 0, iclass 19, count 0 2006.218.07:38:20.66#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.218.07:38:20.66#ibcon#[28=FRQ=01,632.99\r\n] 2006.218.07:38:20.66#ibcon#*before write, iclass 19, count 0 2006.218.07:38:20.66#ibcon#enter sib2, iclass 19, count 0 2006.218.07:38:20.66#ibcon#flushed, iclass 19, count 0 2006.218.07:38:20.66#ibcon#about to write, iclass 19, count 0 2006.218.07:38:20.66#ibcon#wrote, iclass 19, count 0 2006.218.07:38:20.66#ibcon#about to read 3, iclass 19, count 0 2006.218.07:38:20.70#ibcon#read 3, iclass 19, count 0 2006.218.07:38:20.70#ibcon#about to read 4, iclass 19, count 0 2006.218.07:38:20.70#ibcon#read 4, iclass 19, count 0 2006.218.07:38:20.70#ibcon#about to read 5, iclass 19, count 0 2006.218.07:38:20.70#ibcon#read 5, iclass 19, count 0 2006.218.07:38:20.70#ibcon#about to read 6, iclass 19, count 0 2006.218.07:38:20.70#ibcon#read 6, iclass 19, count 0 2006.218.07:38:20.70#ibcon#end of sib2, iclass 19, count 0 2006.218.07:38:20.70#ibcon#*after write, iclass 19, count 0 2006.218.07:38:20.70#ibcon#*before return 0, iclass 19, count 0 2006.218.07:38:20.70#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.218.07:38:20.70#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.218.07:38:20.70#ibcon#about to clear, iclass 19 cls_cnt 0 2006.218.07:38:20.70#ibcon#cleared, iclass 19 cls_cnt 0 2006.218.07:38:20.70$vc4f8/vb=1,4 2006.218.07:38:20.70#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.218.07:38:20.70#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.218.07:38:20.70#ibcon#ireg 11 cls_cnt 2 2006.218.07:38:20.70#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.218.07:38:20.70#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.218.07:38:20.70#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.218.07:38:20.70#ibcon#enter wrdev, iclass 21, count 2 2006.218.07:38:20.70#ibcon#first serial, iclass 21, count 2 2006.218.07:38:20.70#ibcon#enter sib2, iclass 21, count 2 2006.218.07:38:20.70#ibcon#flushed, iclass 21, count 2 2006.218.07:38:20.70#ibcon#about to write, iclass 21, count 2 2006.218.07:38:20.70#ibcon#wrote, iclass 21, count 2 2006.218.07:38:20.70#ibcon#about to read 3, iclass 21, count 2 2006.218.07:38:20.72#ibcon#read 3, iclass 21, count 2 2006.218.07:38:20.72#ibcon#about to read 4, iclass 21, count 2 2006.218.07:38:20.72#ibcon#read 4, iclass 21, count 2 2006.218.07:38:20.72#ibcon#about to read 5, iclass 21, count 2 2006.218.07:38:20.72#ibcon#read 5, iclass 21, count 2 2006.218.07:38:20.72#ibcon#about to read 6, iclass 21, count 2 2006.218.07:38:20.72#ibcon#read 6, iclass 21, count 2 2006.218.07:38:20.72#ibcon#end of sib2, iclass 21, count 2 2006.218.07:38:20.72#ibcon#*mode == 0, iclass 21, count 2 2006.218.07:38:20.72#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.218.07:38:20.72#ibcon#[27=AT01-04\r\n] 2006.218.07:38:20.72#ibcon#*before write, iclass 21, count 2 2006.218.07:38:20.72#ibcon#enter sib2, iclass 21, count 2 2006.218.07:38:20.72#ibcon#flushed, iclass 21, count 2 2006.218.07:38:20.72#ibcon#about to write, iclass 21, count 2 2006.218.07:38:20.72#ibcon#wrote, iclass 21, count 2 2006.218.07:38:20.72#ibcon#about to read 3, iclass 21, count 2 2006.218.07:38:20.75#ibcon#read 3, iclass 21, count 2 2006.218.07:38:20.75#ibcon#about to read 4, iclass 21, count 2 2006.218.07:38:20.75#ibcon#read 4, iclass 21, count 2 2006.218.07:38:20.75#ibcon#about to read 5, iclass 21, count 2 2006.218.07:38:20.75#ibcon#read 5, iclass 21, count 2 2006.218.07:38:20.75#ibcon#about to read 6, iclass 21, count 2 2006.218.07:38:20.75#ibcon#read 6, iclass 21, count 2 2006.218.07:38:20.75#ibcon#end of sib2, iclass 21, count 2 2006.218.07:38:20.75#ibcon#*after write, iclass 21, count 2 2006.218.07:38:20.75#ibcon#*before return 0, iclass 21, count 2 2006.218.07:38:20.75#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.218.07:38:20.75#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.218.07:38:20.75#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.218.07:38:20.75#ibcon#ireg 7 cls_cnt 0 2006.218.07:38:20.75#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.218.07:38:20.87#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.218.07:38:20.87#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.218.07:38:20.87#ibcon#enter wrdev, iclass 21, count 0 2006.218.07:38:20.87#ibcon#first serial, iclass 21, count 0 2006.218.07:38:20.87#ibcon#enter sib2, iclass 21, count 0 2006.218.07:38:20.87#ibcon#flushed, iclass 21, count 0 2006.218.07:38:20.87#ibcon#about to write, iclass 21, count 0 2006.218.07:38:20.87#ibcon#wrote, iclass 21, count 0 2006.218.07:38:20.87#ibcon#about to read 3, iclass 21, count 0 2006.218.07:38:20.89#ibcon#read 3, iclass 21, count 0 2006.218.07:38:20.89#ibcon#about to read 4, iclass 21, count 0 2006.218.07:38:20.89#ibcon#read 4, iclass 21, count 0 2006.218.07:38:20.89#ibcon#about to read 5, iclass 21, count 0 2006.218.07:38:20.89#ibcon#read 5, iclass 21, count 0 2006.218.07:38:20.89#ibcon#about to read 6, iclass 21, count 0 2006.218.07:38:20.89#ibcon#read 6, iclass 21, count 0 2006.218.07:38:20.89#ibcon#end of sib2, iclass 21, count 0 2006.218.07:38:20.89#ibcon#*mode == 0, iclass 21, count 0 2006.218.07:38:20.89#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.218.07:38:20.89#ibcon#[27=USB\r\n] 2006.218.07:38:20.89#ibcon#*before write, iclass 21, count 0 2006.218.07:38:20.89#ibcon#enter sib2, iclass 21, count 0 2006.218.07:38:20.89#ibcon#flushed, iclass 21, count 0 2006.218.07:38:20.89#ibcon#about to write, iclass 21, count 0 2006.218.07:38:20.89#ibcon#wrote, iclass 21, count 0 2006.218.07:38:20.89#ibcon#about to read 3, iclass 21, count 0 2006.218.07:38:20.92#ibcon#read 3, iclass 21, count 0 2006.218.07:38:20.92#ibcon#about to read 4, iclass 21, count 0 2006.218.07:38:20.92#ibcon#read 4, iclass 21, count 0 2006.218.07:38:20.92#ibcon#about to read 5, iclass 21, count 0 2006.218.07:38:20.92#ibcon#read 5, iclass 21, count 0 2006.218.07:38:20.92#ibcon#about to read 6, iclass 21, count 0 2006.218.07:38:20.92#ibcon#read 6, iclass 21, count 0 2006.218.07:38:20.92#ibcon#end of sib2, iclass 21, count 0 2006.218.07:38:20.92#ibcon#*after write, iclass 21, count 0 2006.218.07:38:20.92#ibcon#*before return 0, iclass 21, count 0 2006.218.07:38:20.92#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.218.07:38:20.92#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.218.07:38:20.92#ibcon#about to clear, iclass 21 cls_cnt 0 2006.218.07:38:20.92#ibcon#cleared, iclass 21 cls_cnt 0 2006.218.07:38:20.92$vc4f8/vblo=2,640.99 2006.218.07:38:20.92#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.218.07:38:20.92#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.218.07:38:20.92#ibcon#ireg 17 cls_cnt 0 2006.218.07:38:20.92#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.218.07:38:20.92#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.218.07:38:20.92#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.218.07:38:20.92#ibcon#enter wrdev, iclass 23, count 0 2006.218.07:38:20.92#ibcon#first serial, iclass 23, count 0 2006.218.07:38:20.92#ibcon#enter sib2, iclass 23, count 0 2006.218.07:38:20.92#ibcon#flushed, iclass 23, count 0 2006.218.07:38:20.92#ibcon#about to write, iclass 23, count 0 2006.218.07:38:20.92#ibcon#wrote, iclass 23, count 0 2006.218.07:38:20.92#ibcon#about to read 3, iclass 23, count 0 2006.218.07:38:20.94#ibcon#read 3, iclass 23, count 0 2006.218.07:38:20.94#ibcon#about to read 4, iclass 23, count 0 2006.218.07:38:20.94#ibcon#read 4, iclass 23, count 0 2006.218.07:38:20.94#ibcon#about to read 5, iclass 23, count 0 2006.218.07:38:20.94#ibcon#read 5, iclass 23, count 0 2006.218.07:38:20.94#ibcon#about to read 6, iclass 23, count 0 2006.218.07:38:20.94#ibcon#read 6, iclass 23, count 0 2006.218.07:38:20.94#ibcon#end of sib2, iclass 23, count 0 2006.218.07:38:20.94#ibcon#*mode == 0, iclass 23, count 0 2006.218.07:38:20.94#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.218.07:38:20.94#ibcon#[28=FRQ=02,640.99\r\n] 2006.218.07:38:20.94#ibcon#*before write, iclass 23, count 0 2006.218.07:38:20.94#ibcon#enter sib2, iclass 23, count 0 2006.218.07:38:20.94#ibcon#flushed, iclass 23, count 0 2006.218.07:38:20.94#ibcon#about to write, iclass 23, count 0 2006.218.07:38:20.94#ibcon#wrote, iclass 23, count 0 2006.218.07:38:20.94#ibcon#about to read 3, iclass 23, count 0 2006.218.07:38:20.98#ibcon#read 3, iclass 23, count 0 2006.218.07:38:20.98#ibcon#about to read 4, iclass 23, count 0 2006.218.07:38:20.98#ibcon#read 4, iclass 23, count 0 2006.218.07:38:20.98#ibcon#about to read 5, iclass 23, count 0 2006.218.07:38:20.98#ibcon#read 5, iclass 23, count 0 2006.218.07:38:20.98#ibcon#about to read 6, iclass 23, count 0 2006.218.07:38:20.98#ibcon#read 6, iclass 23, count 0 2006.218.07:38:20.98#ibcon#end of sib2, iclass 23, count 0 2006.218.07:38:20.98#ibcon#*after write, iclass 23, count 0 2006.218.07:38:20.98#ibcon#*before return 0, iclass 23, count 0 2006.218.07:38:20.98#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.218.07:38:20.98#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.218.07:38:20.98#ibcon#about to clear, iclass 23 cls_cnt 0 2006.218.07:38:20.98#ibcon#cleared, iclass 23 cls_cnt 0 2006.218.07:38:20.98$vc4f8/vb=2,4 2006.218.07:38:20.98#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.218.07:38:20.98#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.218.07:38:20.98#ibcon#ireg 11 cls_cnt 2 2006.218.07:38:20.98#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.218.07:38:21.04#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.218.07:38:21.04#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.218.07:38:21.04#ibcon#enter wrdev, iclass 25, count 2 2006.218.07:38:21.04#ibcon#first serial, iclass 25, count 2 2006.218.07:38:21.04#ibcon#enter sib2, iclass 25, count 2 2006.218.07:38:21.04#ibcon#flushed, iclass 25, count 2 2006.218.07:38:21.04#ibcon#about to write, iclass 25, count 2 2006.218.07:38:21.04#ibcon#wrote, iclass 25, count 2 2006.218.07:38:21.04#ibcon#about to read 3, iclass 25, count 2 2006.218.07:38:21.06#ibcon#read 3, iclass 25, count 2 2006.218.07:38:21.06#ibcon#about to read 4, iclass 25, count 2 2006.218.07:38:21.06#ibcon#read 4, iclass 25, count 2 2006.218.07:38:21.06#ibcon#about to read 5, iclass 25, count 2 2006.218.07:38:21.06#ibcon#read 5, iclass 25, count 2 2006.218.07:38:21.06#ibcon#about to read 6, iclass 25, count 2 2006.218.07:38:21.06#ibcon#read 6, iclass 25, count 2 2006.218.07:38:21.06#ibcon#end of sib2, iclass 25, count 2 2006.218.07:38:21.06#ibcon#*mode == 0, iclass 25, count 2 2006.218.07:38:21.06#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.218.07:38:21.06#ibcon#[27=AT02-04\r\n] 2006.218.07:38:21.06#ibcon#*before write, iclass 25, count 2 2006.218.07:38:21.06#ibcon#enter sib2, iclass 25, count 2 2006.218.07:38:21.06#ibcon#flushed, iclass 25, count 2 2006.218.07:38:21.06#ibcon#about to write, iclass 25, count 2 2006.218.07:38:21.06#ibcon#wrote, iclass 25, count 2 2006.218.07:38:21.06#ibcon#about to read 3, iclass 25, count 2 2006.218.07:38:21.09#ibcon#read 3, iclass 25, count 2 2006.218.07:38:21.09#ibcon#about to read 4, iclass 25, count 2 2006.218.07:38:21.09#ibcon#read 4, iclass 25, count 2 2006.218.07:38:21.09#ibcon#about to read 5, iclass 25, count 2 2006.218.07:38:21.09#ibcon#read 5, iclass 25, count 2 2006.218.07:38:21.09#ibcon#about to read 6, iclass 25, count 2 2006.218.07:38:21.09#ibcon#read 6, iclass 25, count 2 2006.218.07:38:21.09#ibcon#end of sib2, iclass 25, count 2 2006.218.07:38:21.09#ibcon#*after write, iclass 25, count 2 2006.218.07:38:21.09#ibcon#*before return 0, iclass 25, count 2 2006.218.07:38:21.09#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.218.07:38:21.09#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.218.07:38:21.09#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.218.07:38:21.09#ibcon#ireg 7 cls_cnt 0 2006.218.07:38:21.09#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.218.07:38:21.21#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.218.07:38:21.21#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.218.07:38:21.21#ibcon#enter wrdev, iclass 25, count 0 2006.218.07:38:21.21#ibcon#first serial, iclass 25, count 0 2006.218.07:38:21.21#ibcon#enter sib2, iclass 25, count 0 2006.218.07:38:21.21#ibcon#flushed, iclass 25, count 0 2006.218.07:38:21.21#ibcon#about to write, iclass 25, count 0 2006.218.07:38:21.21#ibcon#wrote, iclass 25, count 0 2006.218.07:38:21.21#ibcon#about to read 3, iclass 25, count 0 2006.218.07:38:21.24#ibcon#read 3, iclass 25, count 0 2006.218.07:38:21.24#ibcon#about to read 4, iclass 25, count 0 2006.218.07:38:21.24#ibcon#read 4, iclass 25, count 0 2006.218.07:38:21.24#ibcon#about to read 5, iclass 25, count 0 2006.218.07:38:21.24#ibcon#read 5, iclass 25, count 0 2006.218.07:38:21.24#ibcon#about to read 6, iclass 25, count 0 2006.218.07:38:21.24#ibcon#read 6, iclass 25, count 0 2006.218.07:38:21.24#ibcon#end of sib2, iclass 25, count 0 2006.218.07:38:21.24#ibcon#*mode == 0, iclass 25, count 0 2006.218.07:38:21.24#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.218.07:38:21.24#ibcon#[27=USB\r\n] 2006.218.07:38:21.24#ibcon#*before write, iclass 25, count 0 2006.218.07:38:21.24#ibcon#enter sib2, iclass 25, count 0 2006.218.07:38:21.24#ibcon#flushed, iclass 25, count 0 2006.218.07:38:21.24#ibcon#about to write, iclass 25, count 0 2006.218.07:38:21.24#ibcon#wrote, iclass 25, count 0 2006.218.07:38:21.24#ibcon#about to read 3, iclass 25, count 0 2006.218.07:38:21.27#ibcon#read 3, iclass 25, count 0 2006.218.07:38:21.27#ibcon#about to read 4, iclass 25, count 0 2006.218.07:38:21.27#ibcon#read 4, iclass 25, count 0 2006.218.07:38:21.27#ibcon#about to read 5, iclass 25, count 0 2006.218.07:38:21.27#ibcon#read 5, iclass 25, count 0 2006.218.07:38:21.27#ibcon#about to read 6, iclass 25, count 0 2006.218.07:38:21.27#ibcon#read 6, iclass 25, count 0 2006.218.07:38:21.27#ibcon#end of sib2, iclass 25, count 0 2006.218.07:38:21.27#ibcon#*after write, iclass 25, count 0 2006.218.07:38:21.27#ibcon#*before return 0, iclass 25, count 0 2006.218.07:38:21.27#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.218.07:38:21.27#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.218.07:38:21.27#ibcon#about to clear, iclass 25 cls_cnt 0 2006.218.07:38:21.27#ibcon#cleared, iclass 25 cls_cnt 0 2006.218.07:38:21.27$vc4f8/vblo=3,656.99 2006.218.07:38:21.27#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.218.07:38:21.27#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.218.07:38:21.27#ibcon#ireg 17 cls_cnt 0 2006.218.07:38:21.27#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.218.07:38:21.27#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.218.07:38:21.27#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.218.07:38:21.27#ibcon#enter wrdev, iclass 27, count 0 2006.218.07:38:21.27#ibcon#first serial, iclass 27, count 0 2006.218.07:38:21.27#ibcon#enter sib2, iclass 27, count 0 2006.218.07:38:21.27#ibcon#flushed, iclass 27, count 0 2006.218.07:38:21.27#ibcon#about to write, iclass 27, count 0 2006.218.07:38:21.27#ibcon#wrote, iclass 27, count 0 2006.218.07:38:21.27#ibcon#about to read 3, iclass 27, count 0 2006.218.07:38:21.29#ibcon#read 3, iclass 27, count 0 2006.218.07:38:21.29#ibcon#about to read 4, iclass 27, count 0 2006.218.07:38:21.29#ibcon#read 4, iclass 27, count 0 2006.218.07:38:21.29#ibcon#about to read 5, iclass 27, count 0 2006.218.07:38:21.29#ibcon#read 5, iclass 27, count 0 2006.218.07:38:21.29#ibcon#about to read 6, iclass 27, count 0 2006.218.07:38:21.29#ibcon#read 6, iclass 27, count 0 2006.218.07:38:21.29#ibcon#end of sib2, iclass 27, count 0 2006.218.07:38:21.29#ibcon#*mode == 0, iclass 27, count 0 2006.218.07:38:21.29#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.218.07:38:21.29#ibcon#[28=FRQ=03,656.99\r\n] 2006.218.07:38:21.29#ibcon#*before write, iclass 27, count 0 2006.218.07:38:21.29#ibcon#enter sib2, iclass 27, count 0 2006.218.07:38:21.29#ibcon#flushed, iclass 27, count 0 2006.218.07:38:21.29#ibcon#about to write, iclass 27, count 0 2006.218.07:38:21.29#ibcon#wrote, iclass 27, count 0 2006.218.07:38:21.29#ibcon#about to read 3, iclass 27, count 0 2006.218.07:38:21.33#ibcon#read 3, iclass 27, count 0 2006.218.07:38:21.33#ibcon#about to read 4, iclass 27, count 0 2006.218.07:38:21.33#ibcon#read 4, iclass 27, count 0 2006.218.07:38:21.33#ibcon#about to read 5, iclass 27, count 0 2006.218.07:38:21.33#ibcon#read 5, iclass 27, count 0 2006.218.07:38:21.33#ibcon#about to read 6, iclass 27, count 0 2006.218.07:38:21.33#ibcon#read 6, iclass 27, count 0 2006.218.07:38:21.33#ibcon#end of sib2, iclass 27, count 0 2006.218.07:38:21.33#ibcon#*after write, iclass 27, count 0 2006.218.07:38:21.33#ibcon#*before return 0, iclass 27, count 0 2006.218.07:38:21.33#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.218.07:38:21.33#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.218.07:38:21.33#ibcon#about to clear, iclass 27 cls_cnt 0 2006.218.07:38:21.33#ibcon#cleared, iclass 27 cls_cnt 0 2006.218.07:38:21.33$vc4f8/vb=3,4 2006.218.07:38:21.33#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.218.07:38:21.33#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.218.07:38:21.33#ibcon#ireg 11 cls_cnt 2 2006.218.07:38:21.33#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.218.07:38:21.39#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.218.07:38:21.39#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.218.07:38:21.39#ibcon#enter wrdev, iclass 29, count 2 2006.218.07:38:21.39#ibcon#first serial, iclass 29, count 2 2006.218.07:38:21.39#ibcon#enter sib2, iclass 29, count 2 2006.218.07:38:21.39#ibcon#flushed, iclass 29, count 2 2006.218.07:38:21.39#ibcon#about to write, iclass 29, count 2 2006.218.07:38:21.39#ibcon#wrote, iclass 29, count 2 2006.218.07:38:21.39#ibcon#about to read 3, iclass 29, count 2 2006.218.07:38:21.41#ibcon#read 3, iclass 29, count 2 2006.218.07:38:21.41#ibcon#about to read 4, iclass 29, count 2 2006.218.07:38:21.41#ibcon#read 4, iclass 29, count 2 2006.218.07:38:21.41#ibcon#about to read 5, iclass 29, count 2 2006.218.07:38:21.41#ibcon#read 5, iclass 29, count 2 2006.218.07:38:21.41#ibcon#about to read 6, iclass 29, count 2 2006.218.07:38:21.41#ibcon#read 6, iclass 29, count 2 2006.218.07:38:21.41#ibcon#end of sib2, iclass 29, count 2 2006.218.07:38:21.41#ibcon#*mode == 0, iclass 29, count 2 2006.218.07:38:21.41#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.218.07:38:21.41#ibcon#[27=AT03-04\r\n] 2006.218.07:38:21.41#ibcon#*before write, iclass 29, count 2 2006.218.07:38:21.41#ibcon#enter sib2, iclass 29, count 2 2006.218.07:38:21.41#ibcon#flushed, iclass 29, count 2 2006.218.07:38:21.41#ibcon#about to write, iclass 29, count 2 2006.218.07:38:21.41#ibcon#wrote, iclass 29, count 2 2006.218.07:38:21.41#ibcon#about to read 3, iclass 29, count 2 2006.218.07:38:21.44#ibcon#read 3, iclass 29, count 2 2006.218.07:38:21.44#ibcon#about to read 4, iclass 29, count 2 2006.218.07:38:21.44#ibcon#read 4, iclass 29, count 2 2006.218.07:38:21.44#ibcon#about to read 5, iclass 29, count 2 2006.218.07:38:21.44#ibcon#read 5, iclass 29, count 2 2006.218.07:38:21.44#ibcon#about to read 6, iclass 29, count 2 2006.218.07:38:21.44#ibcon#read 6, iclass 29, count 2 2006.218.07:38:21.44#ibcon#end of sib2, iclass 29, count 2 2006.218.07:38:21.44#ibcon#*after write, iclass 29, count 2 2006.218.07:38:21.44#ibcon#*before return 0, iclass 29, count 2 2006.218.07:38:21.44#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.218.07:38:21.44#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.218.07:38:21.44#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.218.07:38:21.44#ibcon#ireg 7 cls_cnt 0 2006.218.07:38:21.44#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.218.07:38:21.56#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.218.07:38:21.56#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.218.07:38:21.56#ibcon#enter wrdev, iclass 29, count 0 2006.218.07:38:21.56#ibcon#first serial, iclass 29, count 0 2006.218.07:38:21.56#ibcon#enter sib2, iclass 29, count 0 2006.218.07:38:21.56#ibcon#flushed, iclass 29, count 0 2006.218.07:38:21.56#ibcon#about to write, iclass 29, count 0 2006.218.07:38:21.56#ibcon#wrote, iclass 29, count 0 2006.218.07:38:21.56#ibcon#about to read 3, iclass 29, count 0 2006.218.07:38:21.58#ibcon#read 3, iclass 29, count 0 2006.218.07:38:21.58#ibcon#about to read 4, iclass 29, count 0 2006.218.07:38:21.58#ibcon#read 4, iclass 29, count 0 2006.218.07:38:21.58#ibcon#about to read 5, iclass 29, count 0 2006.218.07:38:21.58#ibcon#read 5, iclass 29, count 0 2006.218.07:38:21.58#ibcon#about to read 6, iclass 29, count 0 2006.218.07:38:21.58#ibcon#read 6, iclass 29, count 0 2006.218.07:38:21.58#ibcon#end of sib2, iclass 29, count 0 2006.218.07:38:21.58#ibcon#*mode == 0, iclass 29, count 0 2006.218.07:38:21.58#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.218.07:38:21.58#ibcon#[27=USB\r\n] 2006.218.07:38:21.58#ibcon#*before write, iclass 29, count 0 2006.218.07:38:21.58#ibcon#enter sib2, iclass 29, count 0 2006.218.07:38:21.58#ibcon#flushed, iclass 29, count 0 2006.218.07:38:21.58#ibcon#about to write, iclass 29, count 0 2006.218.07:38:21.58#ibcon#wrote, iclass 29, count 0 2006.218.07:38:21.58#ibcon#about to read 3, iclass 29, count 0 2006.218.07:38:21.61#ibcon#read 3, iclass 29, count 0 2006.218.07:38:21.61#ibcon#about to read 4, iclass 29, count 0 2006.218.07:38:21.61#ibcon#read 4, iclass 29, count 0 2006.218.07:38:21.61#ibcon#about to read 5, iclass 29, count 0 2006.218.07:38:21.61#ibcon#read 5, iclass 29, count 0 2006.218.07:38:21.61#ibcon#about to read 6, iclass 29, count 0 2006.218.07:38:21.61#ibcon#read 6, iclass 29, count 0 2006.218.07:38:21.61#ibcon#end of sib2, iclass 29, count 0 2006.218.07:38:21.61#ibcon#*after write, iclass 29, count 0 2006.218.07:38:21.61#ibcon#*before return 0, iclass 29, count 0 2006.218.07:38:21.61#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.218.07:38:21.61#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.218.07:38:21.61#ibcon#about to clear, iclass 29 cls_cnt 0 2006.218.07:38:21.61#ibcon#cleared, iclass 29 cls_cnt 0 2006.218.07:38:21.61$vc4f8/vblo=4,712.99 2006.218.07:38:21.61#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.218.07:38:21.61#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.218.07:38:21.61#ibcon#ireg 17 cls_cnt 0 2006.218.07:38:21.61#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.218.07:38:21.61#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.218.07:38:21.61#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.218.07:38:21.61#ibcon#enter wrdev, iclass 31, count 0 2006.218.07:38:21.61#ibcon#first serial, iclass 31, count 0 2006.218.07:38:21.61#ibcon#enter sib2, iclass 31, count 0 2006.218.07:38:21.61#ibcon#flushed, iclass 31, count 0 2006.218.07:38:21.61#ibcon#about to write, iclass 31, count 0 2006.218.07:38:21.61#ibcon#wrote, iclass 31, count 0 2006.218.07:38:21.61#ibcon#about to read 3, iclass 31, count 0 2006.218.07:38:21.63#ibcon#read 3, iclass 31, count 0 2006.218.07:38:21.63#ibcon#about to read 4, iclass 31, count 0 2006.218.07:38:21.63#ibcon#read 4, iclass 31, count 0 2006.218.07:38:21.63#ibcon#about to read 5, iclass 31, count 0 2006.218.07:38:21.63#ibcon#read 5, iclass 31, count 0 2006.218.07:38:21.63#ibcon#about to read 6, iclass 31, count 0 2006.218.07:38:21.63#ibcon#read 6, iclass 31, count 0 2006.218.07:38:21.63#ibcon#end of sib2, iclass 31, count 0 2006.218.07:38:21.63#ibcon#*mode == 0, iclass 31, count 0 2006.218.07:38:21.63#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.218.07:38:21.63#ibcon#[28=FRQ=04,712.99\r\n] 2006.218.07:38:21.63#ibcon#*before write, iclass 31, count 0 2006.218.07:38:21.63#ibcon#enter sib2, iclass 31, count 0 2006.218.07:38:21.63#ibcon#flushed, iclass 31, count 0 2006.218.07:38:21.63#ibcon#about to write, iclass 31, count 0 2006.218.07:38:21.63#ibcon#wrote, iclass 31, count 0 2006.218.07:38:21.63#ibcon#about to read 3, iclass 31, count 0 2006.218.07:38:21.67#ibcon#read 3, iclass 31, count 0 2006.218.07:38:21.67#ibcon#about to read 4, iclass 31, count 0 2006.218.07:38:21.67#ibcon#read 4, iclass 31, count 0 2006.218.07:38:21.67#ibcon#about to read 5, iclass 31, count 0 2006.218.07:38:21.67#ibcon#read 5, iclass 31, count 0 2006.218.07:38:21.67#ibcon#about to read 6, iclass 31, count 0 2006.218.07:38:21.67#ibcon#read 6, iclass 31, count 0 2006.218.07:38:21.67#ibcon#end of sib2, iclass 31, count 0 2006.218.07:38:21.67#ibcon#*after write, iclass 31, count 0 2006.218.07:38:21.67#ibcon#*before return 0, iclass 31, count 0 2006.218.07:38:21.67#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.218.07:38:21.67#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.218.07:38:21.67#ibcon#about to clear, iclass 31 cls_cnt 0 2006.218.07:38:21.67#ibcon#cleared, iclass 31 cls_cnt 0 2006.218.07:38:21.67$vc4f8/vb=4,4 2006.218.07:38:21.67#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.218.07:38:21.67#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.218.07:38:21.67#ibcon#ireg 11 cls_cnt 2 2006.218.07:38:21.67#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.218.07:38:21.73#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.218.07:38:21.73#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.218.07:38:21.73#ibcon#enter wrdev, iclass 33, count 2 2006.218.07:38:21.73#ibcon#first serial, iclass 33, count 2 2006.218.07:38:21.73#ibcon#enter sib2, iclass 33, count 2 2006.218.07:38:21.73#ibcon#flushed, iclass 33, count 2 2006.218.07:38:21.73#ibcon#about to write, iclass 33, count 2 2006.218.07:38:21.73#ibcon#wrote, iclass 33, count 2 2006.218.07:38:21.73#ibcon#about to read 3, iclass 33, count 2 2006.218.07:38:21.75#ibcon#read 3, iclass 33, count 2 2006.218.07:38:21.75#ibcon#about to read 4, iclass 33, count 2 2006.218.07:38:21.75#ibcon#read 4, iclass 33, count 2 2006.218.07:38:21.75#ibcon#about to read 5, iclass 33, count 2 2006.218.07:38:21.75#ibcon#read 5, iclass 33, count 2 2006.218.07:38:21.75#ibcon#about to read 6, iclass 33, count 2 2006.218.07:38:21.75#ibcon#read 6, iclass 33, count 2 2006.218.07:38:21.75#ibcon#end of sib2, iclass 33, count 2 2006.218.07:38:21.75#ibcon#*mode == 0, iclass 33, count 2 2006.218.07:38:21.75#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.218.07:38:21.75#ibcon#[27=AT04-04\r\n] 2006.218.07:38:21.75#ibcon#*before write, iclass 33, count 2 2006.218.07:38:21.75#ibcon#enter sib2, iclass 33, count 2 2006.218.07:38:21.75#ibcon#flushed, iclass 33, count 2 2006.218.07:38:21.75#ibcon#about to write, iclass 33, count 2 2006.218.07:38:21.75#ibcon#wrote, iclass 33, count 2 2006.218.07:38:21.75#ibcon#about to read 3, iclass 33, count 2 2006.218.07:38:21.78#ibcon#read 3, iclass 33, count 2 2006.218.07:38:21.78#ibcon#about to read 4, iclass 33, count 2 2006.218.07:38:21.78#ibcon#read 4, iclass 33, count 2 2006.218.07:38:21.78#ibcon#about to read 5, iclass 33, count 2 2006.218.07:38:21.78#ibcon#read 5, iclass 33, count 2 2006.218.07:38:21.78#ibcon#about to read 6, iclass 33, count 2 2006.218.07:38:21.78#ibcon#read 6, iclass 33, count 2 2006.218.07:38:21.78#ibcon#end of sib2, iclass 33, count 2 2006.218.07:38:21.78#ibcon#*after write, iclass 33, count 2 2006.218.07:38:21.78#ibcon#*before return 0, iclass 33, count 2 2006.218.07:38:21.78#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.218.07:38:21.78#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.218.07:38:21.78#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.218.07:38:21.78#ibcon#ireg 7 cls_cnt 0 2006.218.07:38:21.78#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.218.07:38:21.90#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.218.07:38:21.90#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.218.07:38:21.90#ibcon#enter wrdev, iclass 33, count 0 2006.218.07:38:21.90#ibcon#first serial, iclass 33, count 0 2006.218.07:38:21.90#ibcon#enter sib2, iclass 33, count 0 2006.218.07:38:21.90#ibcon#flushed, iclass 33, count 0 2006.218.07:38:21.90#ibcon#about to write, iclass 33, count 0 2006.218.07:38:21.90#ibcon#wrote, iclass 33, count 0 2006.218.07:38:21.90#ibcon#about to read 3, iclass 33, count 0 2006.218.07:38:21.92#ibcon#read 3, iclass 33, count 0 2006.218.07:38:21.92#ibcon#about to read 4, iclass 33, count 0 2006.218.07:38:21.92#ibcon#read 4, iclass 33, count 0 2006.218.07:38:21.92#ibcon#about to read 5, iclass 33, count 0 2006.218.07:38:21.92#ibcon#read 5, iclass 33, count 0 2006.218.07:38:21.92#ibcon#about to read 6, iclass 33, count 0 2006.218.07:38:21.92#ibcon#read 6, iclass 33, count 0 2006.218.07:38:21.92#ibcon#end of sib2, iclass 33, count 0 2006.218.07:38:21.92#ibcon#*mode == 0, iclass 33, count 0 2006.218.07:38:21.92#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.218.07:38:21.92#ibcon#[27=USB\r\n] 2006.218.07:38:21.92#ibcon#*before write, iclass 33, count 0 2006.218.07:38:21.92#ibcon#enter sib2, iclass 33, count 0 2006.218.07:38:21.92#ibcon#flushed, iclass 33, count 0 2006.218.07:38:21.92#ibcon#about to write, iclass 33, count 0 2006.218.07:38:21.92#ibcon#wrote, iclass 33, count 0 2006.218.07:38:21.92#ibcon#about to read 3, iclass 33, count 0 2006.218.07:38:21.95#ibcon#read 3, iclass 33, count 0 2006.218.07:38:21.95#ibcon#about to read 4, iclass 33, count 0 2006.218.07:38:21.95#ibcon#read 4, iclass 33, count 0 2006.218.07:38:21.95#ibcon#about to read 5, iclass 33, count 0 2006.218.07:38:21.95#ibcon#read 5, iclass 33, count 0 2006.218.07:38:21.95#ibcon#about to read 6, iclass 33, count 0 2006.218.07:38:21.95#ibcon#read 6, iclass 33, count 0 2006.218.07:38:21.95#ibcon#end of sib2, iclass 33, count 0 2006.218.07:38:21.95#ibcon#*after write, iclass 33, count 0 2006.218.07:38:21.95#ibcon#*before return 0, iclass 33, count 0 2006.218.07:38:21.95#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.218.07:38:21.95#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.218.07:38:21.95#ibcon#about to clear, iclass 33 cls_cnt 0 2006.218.07:38:21.95#ibcon#cleared, iclass 33 cls_cnt 0 2006.218.07:38:21.95$vc4f8/vblo=5,744.99 2006.218.07:38:21.95#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.218.07:38:21.95#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.218.07:38:21.95#ibcon#ireg 17 cls_cnt 0 2006.218.07:38:21.95#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.218.07:38:21.95#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.218.07:38:21.95#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.218.07:38:21.95#ibcon#enter wrdev, iclass 35, count 0 2006.218.07:38:21.95#ibcon#first serial, iclass 35, count 0 2006.218.07:38:21.95#ibcon#enter sib2, iclass 35, count 0 2006.218.07:38:21.95#ibcon#flushed, iclass 35, count 0 2006.218.07:38:21.95#ibcon#about to write, iclass 35, count 0 2006.218.07:38:21.95#ibcon#wrote, iclass 35, count 0 2006.218.07:38:21.95#ibcon#about to read 3, iclass 35, count 0 2006.218.07:38:21.97#ibcon#read 3, iclass 35, count 0 2006.218.07:38:21.97#ibcon#about to read 4, iclass 35, count 0 2006.218.07:38:21.97#ibcon#read 4, iclass 35, count 0 2006.218.07:38:21.97#ibcon#about to read 5, iclass 35, count 0 2006.218.07:38:21.97#ibcon#read 5, iclass 35, count 0 2006.218.07:38:21.97#ibcon#about to read 6, iclass 35, count 0 2006.218.07:38:21.97#ibcon#read 6, iclass 35, count 0 2006.218.07:38:21.97#ibcon#end of sib2, iclass 35, count 0 2006.218.07:38:21.97#ibcon#*mode == 0, iclass 35, count 0 2006.218.07:38:21.97#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.218.07:38:21.97#ibcon#[28=FRQ=05,744.99\r\n] 2006.218.07:38:21.97#ibcon#*before write, iclass 35, count 0 2006.218.07:38:21.97#ibcon#enter sib2, iclass 35, count 0 2006.218.07:38:21.97#ibcon#flushed, iclass 35, count 0 2006.218.07:38:21.97#ibcon#about to write, iclass 35, count 0 2006.218.07:38:21.97#ibcon#wrote, iclass 35, count 0 2006.218.07:38:21.97#ibcon#about to read 3, iclass 35, count 0 2006.218.07:38:22.01#ibcon#read 3, iclass 35, count 0 2006.218.07:38:22.01#ibcon#about to read 4, iclass 35, count 0 2006.218.07:38:22.01#ibcon#read 4, iclass 35, count 0 2006.218.07:38:22.01#ibcon#about to read 5, iclass 35, count 0 2006.218.07:38:22.01#ibcon#read 5, iclass 35, count 0 2006.218.07:38:22.01#ibcon#about to read 6, iclass 35, count 0 2006.218.07:38:22.01#ibcon#read 6, iclass 35, count 0 2006.218.07:38:22.01#ibcon#end of sib2, iclass 35, count 0 2006.218.07:38:22.01#ibcon#*after write, iclass 35, count 0 2006.218.07:38:22.01#ibcon#*before return 0, iclass 35, count 0 2006.218.07:38:22.01#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.218.07:38:22.01#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.218.07:38:22.01#ibcon#about to clear, iclass 35 cls_cnt 0 2006.218.07:38:22.01#ibcon#cleared, iclass 35 cls_cnt 0 2006.218.07:38:22.01$vc4f8/vb=5,4 2006.218.07:38:22.01#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.218.07:38:22.01#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.218.07:38:22.01#ibcon#ireg 11 cls_cnt 2 2006.218.07:38:22.01#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.218.07:38:22.07#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.218.07:38:22.07#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.218.07:38:22.07#ibcon#enter wrdev, iclass 37, count 2 2006.218.07:38:22.07#ibcon#first serial, iclass 37, count 2 2006.218.07:38:22.07#ibcon#enter sib2, iclass 37, count 2 2006.218.07:38:22.07#ibcon#flushed, iclass 37, count 2 2006.218.07:38:22.07#ibcon#about to write, iclass 37, count 2 2006.218.07:38:22.07#ibcon#wrote, iclass 37, count 2 2006.218.07:38:22.07#ibcon#about to read 3, iclass 37, count 2 2006.218.07:38:22.09#ibcon#read 3, iclass 37, count 2 2006.218.07:38:22.09#ibcon#about to read 4, iclass 37, count 2 2006.218.07:38:22.09#ibcon#read 4, iclass 37, count 2 2006.218.07:38:22.09#ibcon#about to read 5, iclass 37, count 2 2006.218.07:38:22.09#ibcon#read 5, iclass 37, count 2 2006.218.07:38:22.09#ibcon#about to read 6, iclass 37, count 2 2006.218.07:38:22.09#ibcon#read 6, iclass 37, count 2 2006.218.07:38:22.09#ibcon#end of sib2, iclass 37, count 2 2006.218.07:38:22.09#ibcon#*mode == 0, iclass 37, count 2 2006.218.07:38:22.09#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.218.07:38:22.09#ibcon#[27=AT05-04\r\n] 2006.218.07:38:22.09#ibcon#*before write, iclass 37, count 2 2006.218.07:38:22.09#ibcon#enter sib2, iclass 37, count 2 2006.218.07:38:22.09#ibcon#flushed, iclass 37, count 2 2006.218.07:38:22.09#ibcon#about to write, iclass 37, count 2 2006.218.07:38:22.09#ibcon#wrote, iclass 37, count 2 2006.218.07:38:22.09#ibcon#about to read 3, iclass 37, count 2 2006.218.07:38:22.12#ibcon#read 3, iclass 37, count 2 2006.218.07:38:22.12#ibcon#about to read 4, iclass 37, count 2 2006.218.07:38:22.12#ibcon#read 4, iclass 37, count 2 2006.218.07:38:22.12#ibcon#about to read 5, iclass 37, count 2 2006.218.07:38:22.12#ibcon#read 5, iclass 37, count 2 2006.218.07:38:22.12#ibcon#about to read 6, iclass 37, count 2 2006.218.07:38:22.12#ibcon#read 6, iclass 37, count 2 2006.218.07:38:22.12#ibcon#end of sib2, iclass 37, count 2 2006.218.07:38:22.12#ibcon#*after write, iclass 37, count 2 2006.218.07:38:22.12#ibcon#*before return 0, iclass 37, count 2 2006.218.07:38:22.12#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.218.07:38:22.12#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.218.07:38:22.12#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.218.07:38:22.12#ibcon#ireg 7 cls_cnt 0 2006.218.07:38:22.12#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.218.07:38:22.24#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.218.07:38:22.24#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.218.07:38:22.24#ibcon#enter wrdev, iclass 37, count 0 2006.218.07:38:22.24#ibcon#first serial, iclass 37, count 0 2006.218.07:38:22.24#ibcon#enter sib2, iclass 37, count 0 2006.218.07:38:22.24#ibcon#flushed, iclass 37, count 0 2006.218.07:38:22.24#ibcon#about to write, iclass 37, count 0 2006.218.07:38:22.24#ibcon#wrote, iclass 37, count 0 2006.218.07:38:22.24#ibcon#about to read 3, iclass 37, count 0 2006.218.07:38:22.26#ibcon#read 3, iclass 37, count 0 2006.218.07:38:22.26#ibcon#about to read 4, iclass 37, count 0 2006.218.07:38:22.26#ibcon#read 4, iclass 37, count 0 2006.218.07:38:22.26#ibcon#about to read 5, iclass 37, count 0 2006.218.07:38:22.26#ibcon#read 5, iclass 37, count 0 2006.218.07:38:22.26#ibcon#about to read 6, iclass 37, count 0 2006.218.07:38:22.26#ibcon#read 6, iclass 37, count 0 2006.218.07:38:22.26#ibcon#end of sib2, iclass 37, count 0 2006.218.07:38:22.26#ibcon#*mode == 0, iclass 37, count 0 2006.218.07:38:22.26#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.218.07:38:22.26#ibcon#[27=USB\r\n] 2006.218.07:38:22.26#ibcon#*before write, iclass 37, count 0 2006.218.07:38:22.26#ibcon#enter sib2, iclass 37, count 0 2006.218.07:38:22.26#ibcon#flushed, iclass 37, count 0 2006.218.07:38:22.26#ibcon#about to write, iclass 37, count 0 2006.218.07:38:22.26#ibcon#wrote, iclass 37, count 0 2006.218.07:38:22.26#ibcon#about to read 3, iclass 37, count 0 2006.218.07:38:22.29#ibcon#read 3, iclass 37, count 0 2006.218.07:38:22.29#ibcon#about to read 4, iclass 37, count 0 2006.218.07:38:22.29#ibcon#read 4, iclass 37, count 0 2006.218.07:38:22.29#ibcon#about to read 5, iclass 37, count 0 2006.218.07:38:22.29#ibcon#read 5, iclass 37, count 0 2006.218.07:38:22.29#ibcon#about to read 6, iclass 37, count 0 2006.218.07:38:22.29#ibcon#read 6, iclass 37, count 0 2006.218.07:38:22.29#ibcon#end of sib2, iclass 37, count 0 2006.218.07:38:22.29#ibcon#*after write, iclass 37, count 0 2006.218.07:38:22.29#ibcon#*before return 0, iclass 37, count 0 2006.218.07:38:22.29#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.218.07:38:22.29#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.218.07:38:22.29#ibcon#about to clear, iclass 37 cls_cnt 0 2006.218.07:38:22.29#ibcon#cleared, iclass 37 cls_cnt 0 2006.218.07:38:22.29$vc4f8/vblo=6,752.99 2006.218.07:38:22.29#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.218.07:38:22.29#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.218.07:38:22.29#ibcon#ireg 17 cls_cnt 0 2006.218.07:38:22.29#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.218.07:38:22.29#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.218.07:38:22.29#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.218.07:38:22.29#ibcon#enter wrdev, iclass 39, count 0 2006.218.07:38:22.29#ibcon#first serial, iclass 39, count 0 2006.218.07:38:22.29#ibcon#enter sib2, iclass 39, count 0 2006.218.07:38:22.29#ibcon#flushed, iclass 39, count 0 2006.218.07:38:22.29#ibcon#about to write, iclass 39, count 0 2006.218.07:38:22.29#ibcon#wrote, iclass 39, count 0 2006.218.07:38:22.29#ibcon#about to read 3, iclass 39, count 0 2006.218.07:38:22.31#ibcon#read 3, iclass 39, count 0 2006.218.07:38:22.31#ibcon#about to read 4, iclass 39, count 0 2006.218.07:38:22.31#ibcon#read 4, iclass 39, count 0 2006.218.07:38:22.31#ibcon#about to read 5, iclass 39, count 0 2006.218.07:38:22.31#ibcon#read 5, iclass 39, count 0 2006.218.07:38:22.31#ibcon#about to read 6, iclass 39, count 0 2006.218.07:38:22.31#ibcon#read 6, iclass 39, count 0 2006.218.07:38:22.31#ibcon#end of sib2, iclass 39, count 0 2006.218.07:38:22.31#ibcon#*mode == 0, iclass 39, count 0 2006.218.07:38:22.31#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.218.07:38:22.31#ibcon#[28=FRQ=06,752.99\r\n] 2006.218.07:38:22.31#ibcon#*before write, iclass 39, count 0 2006.218.07:38:22.31#ibcon#enter sib2, iclass 39, count 0 2006.218.07:38:22.31#ibcon#flushed, iclass 39, count 0 2006.218.07:38:22.31#ibcon#about to write, iclass 39, count 0 2006.218.07:38:22.31#ibcon#wrote, iclass 39, count 0 2006.218.07:38:22.31#ibcon#about to read 3, iclass 39, count 0 2006.218.07:38:22.35#ibcon#read 3, iclass 39, count 0 2006.218.07:38:22.35#ibcon#about to read 4, iclass 39, count 0 2006.218.07:38:22.35#ibcon#read 4, iclass 39, count 0 2006.218.07:38:22.35#ibcon#about to read 5, iclass 39, count 0 2006.218.07:38:22.35#ibcon#read 5, iclass 39, count 0 2006.218.07:38:22.35#ibcon#about to read 6, iclass 39, count 0 2006.218.07:38:22.35#ibcon#read 6, iclass 39, count 0 2006.218.07:38:22.35#ibcon#end of sib2, iclass 39, count 0 2006.218.07:38:22.35#ibcon#*after write, iclass 39, count 0 2006.218.07:38:22.35#ibcon#*before return 0, iclass 39, count 0 2006.218.07:38:22.35#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.218.07:38:22.35#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.218.07:38:22.35#ibcon#about to clear, iclass 39 cls_cnt 0 2006.218.07:38:22.35#ibcon#cleared, iclass 39 cls_cnt 0 2006.218.07:38:22.35$vc4f8/vb=6,4 2006.218.07:38:22.35#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.218.07:38:22.35#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.218.07:38:22.35#ibcon#ireg 11 cls_cnt 2 2006.218.07:38:22.35#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.218.07:38:22.41#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.218.07:38:22.41#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.218.07:38:22.41#ibcon#enter wrdev, iclass 3, count 2 2006.218.07:38:22.41#ibcon#first serial, iclass 3, count 2 2006.218.07:38:22.41#ibcon#enter sib2, iclass 3, count 2 2006.218.07:38:22.41#ibcon#flushed, iclass 3, count 2 2006.218.07:38:22.41#ibcon#about to write, iclass 3, count 2 2006.218.07:38:22.41#ibcon#wrote, iclass 3, count 2 2006.218.07:38:22.41#ibcon#about to read 3, iclass 3, count 2 2006.218.07:38:22.43#ibcon#read 3, iclass 3, count 2 2006.218.07:38:22.43#ibcon#about to read 4, iclass 3, count 2 2006.218.07:38:22.43#ibcon#read 4, iclass 3, count 2 2006.218.07:38:22.43#ibcon#about to read 5, iclass 3, count 2 2006.218.07:38:22.43#ibcon#read 5, iclass 3, count 2 2006.218.07:38:22.43#ibcon#about to read 6, iclass 3, count 2 2006.218.07:38:22.43#ibcon#read 6, iclass 3, count 2 2006.218.07:38:22.43#ibcon#end of sib2, iclass 3, count 2 2006.218.07:38:22.43#ibcon#*mode == 0, iclass 3, count 2 2006.218.07:38:22.43#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.218.07:38:22.43#ibcon#[27=AT06-04\r\n] 2006.218.07:38:22.43#ibcon#*before write, iclass 3, count 2 2006.218.07:38:22.43#ibcon#enter sib2, iclass 3, count 2 2006.218.07:38:22.43#ibcon#flushed, iclass 3, count 2 2006.218.07:38:22.43#ibcon#about to write, iclass 3, count 2 2006.218.07:38:22.43#ibcon#wrote, iclass 3, count 2 2006.218.07:38:22.43#ibcon#about to read 3, iclass 3, count 2 2006.218.07:38:22.46#ibcon#read 3, iclass 3, count 2 2006.218.07:38:22.46#ibcon#about to read 4, iclass 3, count 2 2006.218.07:38:22.46#ibcon#read 4, iclass 3, count 2 2006.218.07:38:22.46#ibcon#about to read 5, iclass 3, count 2 2006.218.07:38:22.46#ibcon#read 5, iclass 3, count 2 2006.218.07:38:22.46#ibcon#about to read 6, iclass 3, count 2 2006.218.07:38:22.46#ibcon#read 6, iclass 3, count 2 2006.218.07:38:22.46#ibcon#end of sib2, iclass 3, count 2 2006.218.07:38:22.46#ibcon#*after write, iclass 3, count 2 2006.218.07:38:22.46#ibcon#*before return 0, iclass 3, count 2 2006.218.07:38:22.46#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.218.07:38:22.46#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.218.07:38:22.46#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.218.07:38:22.46#ibcon#ireg 7 cls_cnt 0 2006.218.07:38:22.46#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.218.07:38:22.58#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.218.07:38:22.58#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.218.07:38:22.58#ibcon#enter wrdev, iclass 3, count 0 2006.218.07:38:22.58#ibcon#first serial, iclass 3, count 0 2006.218.07:38:22.58#ibcon#enter sib2, iclass 3, count 0 2006.218.07:38:22.58#ibcon#flushed, iclass 3, count 0 2006.218.07:38:22.58#ibcon#about to write, iclass 3, count 0 2006.218.07:38:22.58#ibcon#wrote, iclass 3, count 0 2006.218.07:38:22.58#ibcon#about to read 3, iclass 3, count 0 2006.218.07:38:22.60#ibcon#read 3, iclass 3, count 0 2006.218.07:38:22.60#ibcon#about to read 4, iclass 3, count 0 2006.218.07:38:22.60#ibcon#read 4, iclass 3, count 0 2006.218.07:38:22.60#ibcon#about to read 5, iclass 3, count 0 2006.218.07:38:22.60#ibcon#read 5, iclass 3, count 0 2006.218.07:38:22.60#ibcon#about to read 6, iclass 3, count 0 2006.218.07:38:22.60#ibcon#read 6, iclass 3, count 0 2006.218.07:38:22.60#ibcon#end of sib2, iclass 3, count 0 2006.218.07:38:22.60#ibcon#*mode == 0, iclass 3, count 0 2006.218.07:38:22.60#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.218.07:38:22.60#ibcon#[27=USB\r\n] 2006.218.07:38:22.60#ibcon#*before write, iclass 3, count 0 2006.218.07:38:22.60#ibcon#enter sib2, iclass 3, count 0 2006.218.07:38:22.60#ibcon#flushed, iclass 3, count 0 2006.218.07:38:22.60#ibcon#about to write, iclass 3, count 0 2006.218.07:38:22.60#ibcon#wrote, iclass 3, count 0 2006.218.07:38:22.60#ibcon#about to read 3, iclass 3, count 0 2006.218.07:38:22.63#ibcon#read 3, iclass 3, count 0 2006.218.07:38:22.63#ibcon#about to read 4, iclass 3, count 0 2006.218.07:38:22.63#ibcon#read 4, iclass 3, count 0 2006.218.07:38:22.63#ibcon#about to read 5, iclass 3, count 0 2006.218.07:38:22.63#ibcon#read 5, iclass 3, count 0 2006.218.07:38:22.63#ibcon#about to read 6, iclass 3, count 0 2006.218.07:38:22.63#ibcon#read 6, iclass 3, count 0 2006.218.07:38:22.63#ibcon#end of sib2, iclass 3, count 0 2006.218.07:38:22.63#ibcon#*after write, iclass 3, count 0 2006.218.07:38:22.63#ibcon#*before return 0, iclass 3, count 0 2006.218.07:38:22.63#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.218.07:38:22.63#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.218.07:38:22.63#ibcon#about to clear, iclass 3 cls_cnt 0 2006.218.07:38:22.63#ibcon#cleared, iclass 3 cls_cnt 0 2006.218.07:38:22.63$vc4f8/vabw=wide 2006.218.07:38:22.63#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.218.07:38:22.63#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.218.07:38:22.63#ibcon#ireg 8 cls_cnt 0 2006.218.07:38:22.63#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.218.07:38:22.63#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.218.07:38:22.63#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.218.07:38:22.63#ibcon#enter wrdev, iclass 5, count 0 2006.218.07:38:22.63#ibcon#first serial, iclass 5, count 0 2006.218.07:38:22.63#ibcon#enter sib2, iclass 5, count 0 2006.218.07:38:22.63#ibcon#flushed, iclass 5, count 0 2006.218.07:38:22.63#ibcon#about to write, iclass 5, count 0 2006.218.07:38:22.63#ibcon#wrote, iclass 5, count 0 2006.218.07:38:22.63#ibcon#about to read 3, iclass 5, count 0 2006.218.07:38:22.65#ibcon#read 3, iclass 5, count 0 2006.218.07:38:22.65#ibcon#about to read 4, iclass 5, count 0 2006.218.07:38:22.65#ibcon#read 4, iclass 5, count 0 2006.218.07:38:22.65#ibcon#about to read 5, iclass 5, count 0 2006.218.07:38:22.65#ibcon#read 5, iclass 5, count 0 2006.218.07:38:22.65#ibcon#about to read 6, iclass 5, count 0 2006.218.07:38:22.65#ibcon#read 6, iclass 5, count 0 2006.218.07:38:22.65#ibcon#end of sib2, iclass 5, count 0 2006.218.07:38:22.65#ibcon#*mode == 0, iclass 5, count 0 2006.218.07:38:22.65#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.218.07:38:22.65#ibcon#[25=BW32\r\n] 2006.218.07:38:22.65#ibcon#*before write, iclass 5, count 0 2006.218.07:38:22.65#ibcon#enter sib2, iclass 5, count 0 2006.218.07:38:22.65#ibcon#flushed, iclass 5, count 0 2006.218.07:38:22.65#ibcon#about to write, iclass 5, count 0 2006.218.07:38:22.65#ibcon#wrote, iclass 5, count 0 2006.218.07:38:22.65#ibcon#about to read 3, iclass 5, count 0 2006.218.07:38:22.68#ibcon#read 3, iclass 5, count 0 2006.218.07:38:22.68#ibcon#about to read 4, iclass 5, count 0 2006.218.07:38:22.68#ibcon#read 4, iclass 5, count 0 2006.218.07:38:22.68#ibcon#about to read 5, iclass 5, count 0 2006.218.07:38:22.68#ibcon#read 5, iclass 5, count 0 2006.218.07:38:22.68#ibcon#about to read 6, iclass 5, count 0 2006.218.07:38:22.68#ibcon#read 6, iclass 5, count 0 2006.218.07:38:22.68#ibcon#end of sib2, iclass 5, count 0 2006.218.07:38:22.68#ibcon#*after write, iclass 5, count 0 2006.218.07:38:22.68#ibcon#*before return 0, iclass 5, count 0 2006.218.07:38:22.68#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.218.07:38:22.68#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.218.07:38:22.68#ibcon#about to clear, iclass 5 cls_cnt 0 2006.218.07:38:22.68#ibcon#cleared, iclass 5 cls_cnt 0 2006.218.07:38:22.68$vc4f8/vbbw=wide 2006.218.07:38:22.68#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.218.07:38:22.68#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.218.07:38:22.68#ibcon#ireg 8 cls_cnt 0 2006.218.07:38:22.68#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.218.07:38:22.75#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.218.07:38:22.75#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.218.07:38:22.75#ibcon#enter wrdev, iclass 7, count 0 2006.218.07:38:22.75#ibcon#first serial, iclass 7, count 0 2006.218.07:38:22.75#ibcon#enter sib2, iclass 7, count 0 2006.218.07:38:22.75#ibcon#flushed, iclass 7, count 0 2006.218.07:38:22.75#ibcon#about to write, iclass 7, count 0 2006.218.07:38:22.75#ibcon#wrote, iclass 7, count 0 2006.218.07:38:22.75#ibcon#about to read 3, iclass 7, count 0 2006.218.07:38:22.77#ibcon#read 3, iclass 7, count 0 2006.218.07:38:22.77#ibcon#about to read 4, iclass 7, count 0 2006.218.07:38:22.77#ibcon#read 4, iclass 7, count 0 2006.218.07:38:22.77#ibcon#about to read 5, iclass 7, count 0 2006.218.07:38:22.77#ibcon#read 5, iclass 7, count 0 2006.218.07:38:22.77#ibcon#about to read 6, iclass 7, count 0 2006.218.07:38:22.77#ibcon#read 6, iclass 7, count 0 2006.218.07:38:22.77#ibcon#end of sib2, iclass 7, count 0 2006.218.07:38:22.77#ibcon#*mode == 0, iclass 7, count 0 2006.218.07:38:22.77#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.218.07:38:22.77#ibcon#[27=BW32\r\n] 2006.218.07:38:22.77#ibcon#*before write, iclass 7, count 0 2006.218.07:38:22.77#ibcon#enter sib2, iclass 7, count 0 2006.218.07:38:22.77#ibcon#flushed, iclass 7, count 0 2006.218.07:38:22.77#ibcon#about to write, iclass 7, count 0 2006.218.07:38:22.77#ibcon#wrote, iclass 7, count 0 2006.218.07:38:22.77#ibcon#about to read 3, iclass 7, count 0 2006.218.07:38:22.80#ibcon#read 3, iclass 7, count 0 2006.218.07:38:22.80#ibcon#about to read 4, iclass 7, count 0 2006.218.07:38:22.80#ibcon#read 4, iclass 7, count 0 2006.218.07:38:22.80#ibcon#about to read 5, iclass 7, count 0 2006.218.07:38:22.80#ibcon#read 5, iclass 7, count 0 2006.218.07:38:22.80#ibcon#about to read 6, iclass 7, count 0 2006.218.07:38:22.80#ibcon#read 6, iclass 7, count 0 2006.218.07:38:22.80#ibcon#end of sib2, iclass 7, count 0 2006.218.07:38:22.80#ibcon#*after write, iclass 7, count 0 2006.218.07:38:22.80#ibcon#*before return 0, iclass 7, count 0 2006.218.07:38:22.80#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.218.07:38:22.80#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.218.07:38:22.80#ibcon#about to clear, iclass 7 cls_cnt 0 2006.218.07:38:22.80#ibcon#cleared, iclass 7 cls_cnt 0 2006.218.07:38:22.80$4f8m12a/ifd4f 2006.218.07:38:22.80$ifd4f/lo= 2006.218.07:38:22.80$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.218.07:38:22.80$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.218.07:38:22.80$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.218.07:38:22.80$ifd4f/patch= 2006.218.07:38:22.80$ifd4f/patch=lo1,a1,a2,a3,a4 2006.218.07:38:22.80$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.218.07:38:22.80$ifd4f/patch=lo3,a5,a6,a7,a8 2006.218.07:38:22.80$4f8m12a/"form=m,16.000,1:2 2006.218.07:38:22.80$4f8m12a/"tpicd 2006.218.07:38:22.80$4f8m12a/echo=off 2006.218.07:38:22.80$4f8m12a/xlog=off 2006.218.07:38:22.80:!2006.218.07:38:50 2006.218.07:38:31.14#trakl#Source acquired 2006.218.07:38:32.14#flagr#flagr/antenna,acquired 2006.218.07:38:50.00:preob 2006.218.07:38:51.14/onsource/TRACKING 2006.218.07:38:51.14:!2006.218.07:39:00 2006.218.07:39:00.00:data_valid=on 2006.218.07:39:00.00:midob 2006.218.07:39:00.14/onsource/TRACKING 2006.218.07:39:00.14/wx/31.45,1007.4,72 2006.218.07:39:00.22/cable/+6.3841E-03 2006.218.07:39:01.31/va/01,05,usb,yes,31,33 2006.218.07:39:01.31/va/02,04,usb,yes,29,31 2006.218.07:39:01.31/va/03,04,usb,yes,28,28 2006.218.07:39:01.31/va/04,04,usb,yes,31,33 2006.218.07:39:01.31/va/05,07,usb,yes,32,34 2006.218.07:39:01.31/va/06,06,usb,yes,32,31 2006.218.07:39:01.31/va/07,06,usb,yes,32,32 2006.218.07:39:01.31/va/08,07,usb,yes,30,30 2006.218.07:39:01.54/valo/01,532.99,yes,locked 2006.218.07:39:01.54/valo/02,572.99,yes,locked 2006.218.07:39:01.54/valo/03,672.99,yes,locked 2006.218.07:39:01.54/valo/04,832.99,yes,locked 2006.218.07:39:01.54/valo/05,652.99,yes,locked 2006.218.07:39:01.54/valo/06,772.99,yes,locked 2006.218.07:39:01.54/valo/07,832.99,yes,locked 2006.218.07:39:01.54/valo/08,852.99,yes,locked 2006.218.07:39:02.63/vb/01,04,usb,yes,30,29 2006.218.07:39:02.63/vb/02,04,usb,yes,32,33 2006.218.07:39:02.63/vb/03,04,usb,yes,28,32 2006.218.07:39:02.63/vb/04,04,usb,yes,29,29 2006.218.07:39:02.63/vb/05,04,usb,yes,28,32 2006.218.07:39:02.63/vb/06,04,usb,yes,28,31 2006.218.07:39:02.63/vb/07,04,usb,yes,31,31 2006.218.07:39:02.63/vb/08,04,usb,yes,28,32 2006.218.07:39:02.87/vblo/01,632.99,yes,locked 2006.218.07:39:02.87/vblo/02,640.99,yes,locked 2006.218.07:39:02.87/vblo/03,656.99,yes,locked 2006.218.07:39:02.87/vblo/04,712.99,yes,locked 2006.218.07:39:02.87/vblo/05,744.99,yes,locked 2006.218.07:39:02.87/vblo/06,752.99,yes,locked 2006.218.07:39:02.87/vblo/07,734.99,yes,locked 2006.218.07:39:02.87/vblo/08,744.99,yes,locked 2006.218.07:39:03.02/vabw/8 2006.218.07:39:03.17/vbbw/8 2006.218.07:39:03.26/xfe/off,on,15.2 2006.218.07:39:03.64/ifatt/23,28,28,28 2006.218.07:39:04.08/fmout-gps/S +4.74E-07 2006.218.07:39:04.12:!2006.218.07:40:00 2006.218.07:40:00.00:data_valid=off 2006.218.07:40:00.00:postob 2006.218.07:40:00.18/cable/+6.3837E-03 2006.218.07:40:00.18/wx/31.42,1007.4,73 2006.218.07:40:01.08/fmout-gps/S +4.74E-07 2006.218.07:40:01.08:scan_name=218-0740,k06218,60 2006.218.07:40:01.08:source=1418+546,141946.60,542314.8,2000.0,neutral 2006.218.07:40:01.14#flagr#flagr/antenna,new-source 2006.218.07:40:02.14:checkk5 2006.218.07:40:02.51/chk_autoobs//k5ts1/ autoobs is running! 2006.218.07:40:02.88/chk_autoobs//k5ts2/ autoobs is running! 2006.218.07:40:03.26/chk_autoobs//k5ts3/ autoobs is running! 2006.218.07:40:03.63/chk_autoobs//k5ts4/ autoobs is running! 2006.218.07:40:04.00/chk_obsdata//k5ts1/T2180739??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:40:04.38/chk_obsdata//k5ts2/T2180739??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:40:04.74/chk_obsdata//k5ts3/T2180739??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:40:05.11/chk_obsdata//k5ts4/T2180739??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:40:05.80/k5log//k5ts1_log_newline 2006.218.07:40:06.48/k5log//k5ts2_log_newline 2006.218.07:40:07.17/k5log//k5ts3_log_newline 2006.218.07:40:07.86/k5log//k5ts4_log_newline 2006.218.07:40:07.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.218.07:40:07.88:4f8m12a=1 2006.218.07:40:07.88$4f8m12a/echo=on 2006.218.07:40:07.88$4f8m12a/pcalon 2006.218.07:40:07.88$pcalon/"no phase cal control is implemented here 2006.218.07:40:07.88$4f8m12a/"tpicd=stop 2006.218.07:40:07.88$4f8m12a/vc4f8 2006.218.07:40:07.88$vc4f8/valo=1,532.99 2006.218.07:40:07.89#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.218.07:40:07.89#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.218.07:40:07.89#ibcon#ireg 17 cls_cnt 0 2006.218.07:40:07.89#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.218.07:40:07.89#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.218.07:40:07.89#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.218.07:40:07.89#ibcon#enter wrdev, iclass 16, count 0 2006.218.07:40:07.89#ibcon#first serial, iclass 16, count 0 2006.218.07:40:07.89#ibcon#enter sib2, iclass 16, count 0 2006.218.07:40:07.89#ibcon#flushed, iclass 16, count 0 2006.218.07:40:07.89#ibcon#about to write, iclass 16, count 0 2006.218.07:40:07.89#ibcon#wrote, iclass 16, count 0 2006.218.07:40:07.89#ibcon#about to read 3, iclass 16, count 0 2006.218.07:40:07.93#ibcon#read 3, iclass 16, count 0 2006.218.07:40:07.93#ibcon#about to read 4, iclass 16, count 0 2006.218.07:40:07.93#ibcon#read 4, iclass 16, count 0 2006.218.07:40:07.93#ibcon#about to read 5, iclass 16, count 0 2006.218.07:40:07.93#ibcon#read 5, iclass 16, count 0 2006.218.07:40:07.93#ibcon#about to read 6, iclass 16, count 0 2006.218.07:40:07.93#ibcon#read 6, iclass 16, count 0 2006.218.07:40:07.93#ibcon#end of sib2, iclass 16, count 0 2006.218.07:40:07.93#ibcon#*mode == 0, iclass 16, count 0 2006.218.07:40:07.93#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.218.07:40:07.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.218.07:40:07.93#ibcon#*before write, iclass 16, count 0 2006.218.07:40:07.93#ibcon#enter sib2, iclass 16, count 0 2006.218.07:40:07.93#ibcon#flushed, iclass 16, count 0 2006.218.07:40:07.93#ibcon#about to write, iclass 16, count 0 2006.218.07:40:07.93#ibcon#wrote, iclass 16, count 0 2006.218.07:40:07.93#ibcon#about to read 3, iclass 16, count 0 2006.218.07:40:07.98#ibcon#read 3, iclass 16, count 0 2006.218.07:40:07.98#ibcon#about to read 4, iclass 16, count 0 2006.218.07:40:07.98#ibcon#read 4, iclass 16, count 0 2006.218.07:40:07.98#ibcon#about to read 5, iclass 16, count 0 2006.218.07:40:07.98#ibcon#read 5, iclass 16, count 0 2006.218.07:40:07.98#ibcon#about to read 6, iclass 16, count 0 2006.218.07:40:07.98#ibcon#read 6, iclass 16, count 0 2006.218.07:40:07.98#ibcon#end of sib2, iclass 16, count 0 2006.218.07:40:07.98#ibcon#*after write, iclass 16, count 0 2006.218.07:40:07.98#ibcon#*before return 0, iclass 16, count 0 2006.218.07:40:07.98#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.218.07:40:07.98#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.218.07:40:07.98#ibcon#about to clear, iclass 16 cls_cnt 0 2006.218.07:40:07.98#ibcon#cleared, iclass 16 cls_cnt 0 2006.218.07:40:07.98$vc4f8/va=1,5 2006.218.07:40:07.98#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.218.07:40:07.98#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.218.07:40:07.98#ibcon#ireg 11 cls_cnt 2 2006.218.07:40:07.98#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.218.07:40:07.98#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.218.07:40:07.98#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.218.07:40:07.98#ibcon#enter wrdev, iclass 18, count 2 2006.218.07:40:07.98#ibcon#first serial, iclass 18, count 2 2006.218.07:40:07.98#ibcon#enter sib2, iclass 18, count 2 2006.218.07:40:07.98#ibcon#flushed, iclass 18, count 2 2006.218.07:40:07.98#ibcon#about to write, iclass 18, count 2 2006.218.07:40:07.98#ibcon#wrote, iclass 18, count 2 2006.218.07:40:07.98#ibcon#about to read 3, iclass 18, count 2 2006.218.07:40:08.00#ibcon#read 3, iclass 18, count 2 2006.218.07:40:08.00#ibcon#about to read 4, iclass 18, count 2 2006.218.07:40:08.00#ibcon#read 4, iclass 18, count 2 2006.218.07:40:08.00#ibcon#about to read 5, iclass 18, count 2 2006.218.07:40:08.00#ibcon#read 5, iclass 18, count 2 2006.218.07:40:08.00#ibcon#about to read 6, iclass 18, count 2 2006.218.07:40:08.00#ibcon#read 6, iclass 18, count 2 2006.218.07:40:08.00#ibcon#end of sib2, iclass 18, count 2 2006.218.07:40:08.00#ibcon#*mode == 0, iclass 18, count 2 2006.218.07:40:08.00#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.218.07:40:08.00#ibcon#[25=AT01-05\r\n] 2006.218.07:40:08.00#ibcon#*before write, iclass 18, count 2 2006.218.07:40:08.00#ibcon#enter sib2, iclass 18, count 2 2006.218.07:40:08.00#ibcon#flushed, iclass 18, count 2 2006.218.07:40:08.00#ibcon#about to write, iclass 18, count 2 2006.218.07:40:08.00#ibcon#wrote, iclass 18, count 2 2006.218.07:40:08.00#ibcon#about to read 3, iclass 18, count 2 2006.218.07:40:08.04#ibcon#read 3, iclass 18, count 2 2006.218.07:40:08.04#ibcon#about to read 4, iclass 18, count 2 2006.218.07:40:08.04#ibcon#read 4, iclass 18, count 2 2006.218.07:40:08.04#ibcon#about to read 5, iclass 18, count 2 2006.218.07:40:08.04#ibcon#read 5, iclass 18, count 2 2006.218.07:40:08.04#ibcon#about to read 6, iclass 18, count 2 2006.218.07:40:08.04#ibcon#read 6, iclass 18, count 2 2006.218.07:40:08.04#ibcon#end of sib2, iclass 18, count 2 2006.218.07:40:08.04#ibcon#*after write, iclass 18, count 2 2006.218.07:40:08.04#ibcon#*before return 0, iclass 18, count 2 2006.218.07:40:08.04#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.218.07:40:08.04#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.218.07:40:08.04#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.218.07:40:08.04#ibcon#ireg 7 cls_cnt 0 2006.218.07:40:08.04#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.218.07:40:08.16#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.218.07:40:08.16#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.218.07:40:08.16#ibcon#enter wrdev, iclass 18, count 0 2006.218.07:40:08.16#ibcon#first serial, iclass 18, count 0 2006.218.07:40:08.16#ibcon#enter sib2, iclass 18, count 0 2006.218.07:40:08.16#ibcon#flushed, iclass 18, count 0 2006.218.07:40:08.16#ibcon#about to write, iclass 18, count 0 2006.218.07:40:08.16#ibcon#wrote, iclass 18, count 0 2006.218.07:40:08.16#ibcon#about to read 3, iclass 18, count 0 2006.218.07:40:08.18#ibcon#read 3, iclass 18, count 0 2006.218.07:40:08.18#ibcon#about to read 4, iclass 18, count 0 2006.218.07:40:08.18#ibcon#read 4, iclass 18, count 0 2006.218.07:40:08.18#ibcon#about to read 5, iclass 18, count 0 2006.218.07:40:08.18#ibcon#read 5, iclass 18, count 0 2006.218.07:40:08.18#ibcon#about to read 6, iclass 18, count 0 2006.218.07:40:08.18#ibcon#read 6, iclass 18, count 0 2006.218.07:40:08.18#ibcon#end of sib2, iclass 18, count 0 2006.218.07:40:08.18#ibcon#*mode == 0, iclass 18, count 0 2006.218.07:40:08.18#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.218.07:40:08.18#ibcon#[25=USB\r\n] 2006.218.07:40:08.18#ibcon#*before write, iclass 18, count 0 2006.218.07:40:08.18#ibcon#enter sib2, iclass 18, count 0 2006.218.07:40:08.18#ibcon#flushed, iclass 18, count 0 2006.218.07:40:08.18#ibcon#about to write, iclass 18, count 0 2006.218.07:40:08.18#ibcon#wrote, iclass 18, count 0 2006.218.07:40:08.18#ibcon#about to read 3, iclass 18, count 0 2006.218.07:40:08.21#ibcon#read 3, iclass 18, count 0 2006.218.07:40:08.21#ibcon#about to read 4, iclass 18, count 0 2006.218.07:40:08.21#ibcon#read 4, iclass 18, count 0 2006.218.07:40:08.21#ibcon#about to read 5, iclass 18, count 0 2006.218.07:40:08.21#ibcon#read 5, iclass 18, count 0 2006.218.07:40:08.21#ibcon#about to read 6, iclass 18, count 0 2006.218.07:40:08.21#ibcon#read 6, iclass 18, count 0 2006.218.07:40:08.21#ibcon#end of sib2, iclass 18, count 0 2006.218.07:40:08.21#ibcon#*after write, iclass 18, count 0 2006.218.07:40:08.21#ibcon#*before return 0, iclass 18, count 0 2006.218.07:40:08.21#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.218.07:40:08.21#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.218.07:40:08.21#ibcon#about to clear, iclass 18 cls_cnt 0 2006.218.07:40:08.21#ibcon#cleared, iclass 18 cls_cnt 0 2006.218.07:40:08.21$vc4f8/valo=2,572.99 2006.218.07:40:08.21#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.218.07:40:08.21#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.218.07:40:08.21#ibcon#ireg 17 cls_cnt 0 2006.218.07:40:08.21#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.218.07:40:08.21#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.218.07:40:08.21#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.218.07:40:08.21#ibcon#enter wrdev, iclass 20, count 0 2006.218.07:40:08.21#ibcon#first serial, iclass 20, count 0 2006.218.07:40:08.21#ibcon#enter sib2, iclass 20, count 0 2006.218.07:40:08.21#ibcon#flushed, iclass 20, count 0 2006.218.07:40:08.21#ibcon#about to write, iclass 20, count 0 2006.218.07:40:08.21#ibcon#wrote, iclass 20, count 0 2006.218.07:40:08.21#ibcon#about to read 3, iclass 20, count 0 2006.218.07:40:08.23#ibcon#read 3, iclass 20, count 0 2006.218.07:40:08.23#ibcon#about to read 4, iclass 20, count 0 2006.218.07:40:08.23#ibcon#read 4, iclass 20, count 0 2006.218.07:40:08.23#ibcon#about to read 5, iclass 20, count 0 2006.218.07:40:08.23#ibcon#read 5, iclass 20, count 0 2006.218.07:40:08.23#ibcon#about to read 6, iclass 20, count 0 2006.218.07:40:08.23#ibcon#read 6, iclass 20, count 0 2006.218.07:40:08.23#ibcon#end of sib2, iclass 20, count 0 2006.218.07:40:08.23#ibcon#*mode == 0, iclass 20, count 0 2006.218.07:40:08.23#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.218.07:40:08.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.218.07:40:08.23#ibcon#*before write, iclass 20, count 0 2006.218.07:40:08.23#ibcon#enter sib2, iclass 20, count 0 2006.218.07:40:08.23#ibcon#flushed, iclass 20, count 0 2006.218.07:40:08.23#ibcon#about to write, iclass 20, count 0 2006.218.07:40:08.23#ibcon#wrote, iclass 20, count 0 2006.218.07:40:08.23#ibcon#about to read 3, iclass 20, count 0 2006.218.07:40:08.27#ibcon#read 3, iclass 20, count 0 2006.218.07:40:08.27#ibcon#about to read 4, iclass 20, count 0 2006.218.07:40:08.27#ibcon#read 4, iclass 20, count 0 2006.218.07:40:08.27#ibcon#about to read 5, iclass 20, count 0 2006.218.07:40:08.27#ibcon#read 5, iclass 20, count 0 2006.218.07:40:08.27#ibcon#about to read 6, iclass 20, count 0 2006.218.07:40:08.27#ibcon#read 6, iclass 20, count 0 2006.218.07:40:08.27#ibcon#end of sib2, iclass 20, count 0 2006.218.07:40:08.27#ibcon#*after write, iclass 20, count 0 2006.218.07:40:08.27#ibcon#*before return 0, iclass 20, count 0 2006.218.07:40:08.27#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.218.07:40:08.27#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.218.07:40:08.27#ibcon#about to clear, iclass 20 cls_cnt 0 2006.218.07:40:08.27#ibcon#cleared, iclass 20 cls_cnt 0 2006.218.07:40:08.27$vc4f8/va=2,4 2006.218.07:40:08.27#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.218.07:40:08.27#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.218.07:40:08.27#ibcon#ireg 11 cls_cnt 2 2006.218.07:40:08.27#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.218.07:40:08.33#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.218.07:40:08.33#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.218.07:40:08.33#ibcon#enter wrdev, iclass 22, count 2 2006.218.07:40:08.33#ibcon#first serial, iclass 22, count 2 2006.218.07:40:08.33#ibcon#enter sib2, iclass 22, count 2 2006.218.07:40:08.33#ibcon#flushed, iclass 22, count 2 2006.218.07:40:08.33#ibcon#about to write, iclass 22, count 2 2006.218.07:40:08.33#ibcon#wrote, iclass 22, count 2 2006.218.07:40:08.33#ibcon#about to read 3, iclass 22, count 2 2006.218.07:40:08.35#ibcon#read 3, iclass 22, count 2 2006.218.07:40:08.35#ibcon#about to read 4, iclass 22, count 2 2006.218.07:40:08.35#ibcon#read 4, iclass 22, count 2 2006.218.07:40:08.35#ibcon#about to read 5, iclass 22, count 2 2006.218.07:40:08.35#ibcon#read 5, iclass 22, count 2 2006.218.07:40:08.35#ibcon#about to read 6, iclass 22, count 2 2006.218.07:40:08.35#ibcon#read 6, iclass 22, count 2 2006.218.07:40:08.35#ibcon#end of sib2, iclass 22, count 2 2006.218.07:40:08.35#ibcon#*mode == 0, iclass 22, count 2 2006.218.07:40:08.35#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.218.07:40:08.35#ibcon#[25=AT02-04\r\n] 2006.218.07:40:08.35#ibcon#*before write, iclass 22, count 2 2006.218.07:40:08.35#ibcon#enter sib2, iclass 22, count 2 2006.218.07:40:08.35#ibcon#flushed, iclass 22, count 2 2006.218.07:40:08.35#ibcon#about to write, iclass 22, count 2 2006.218.07:40:08.35#ibcon#wrote, iclass 22, count 2 2006.218.07:40:08.35#ibcon#about to read 3, iclass 22, count 2 2006.218.07:40:08.38#ibcon#read 3, iclass 22, count 2 2006.218.07:40:08.38#ibcon#about to read 4, iclass 22, count 2 2006.218.07:40:08.38#ibcon#read 4, iclass 22, count 2 2006.218.07:40:08.38#ibcon#about to read 5, iclass 22, count 2 2006.218.07:40:08.38#ibcon#read 5, iclass 22, count 2 2006.218.07:40:08.38#ibcon#about to read 6, iclass 22, count 2 2006.218.07:40:08.38#ibcon#read 6, iclass 22, count 2 2006.218.07:40:08.38#ibcon#end of sib2, iclass 22, count 2 2006.218.07:40:08.38#ibcon#*after write, iclass 22, count 2 2006.218.07:40:08.38#ibcon#*before return 0, iclass 22, count 2 2006.218.07:40:08.38#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.218.07:40:08.38#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.218.07:40:08.38#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.218.07:40:08.38#ibcon#ireg 7 cls_cnt 0 2006.218.07:40:08.38#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.218.07:40:08.50#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.218.07:40:08.50#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.218.07:40:08.50#ibcon#enter wrdev, iclass 22, count 0 2006.218.07:40:08.50#ibcon#first serial, iclass 22, count 0 2006.218.07:40:08.50#ibcon#enter sib2, iclass 22, count 0 2006.218.07:40:08.50#ibcon#flushed, iclass 22, count 0 2006.218.07:40:08.50#ibcon#about to write, iclass 22, count 0 2006.218.07:40:08.50#ibcon#wrote, iclass 22, count 0 2006.218.07:40:08.50#ibcon#about to read 3, iclass 22, count 0 2006.218.07:40:08.52#ibcon#read 3, iclass 22, count 0 2006.218.07:40:08.52#ibcon#about to read 4, iclass 22, count 0 2006.218.07:40:08.52#ibcon#read 4, iclass 22, count 0 2006.218.07:40:08.52#ibcon#about to read 5, iclass 22, count 0 2006.218.07:40:08.52#ibcon#read 5, iclass 22, count 0 2006.218.07:40:08.52#ibcon#about to read 6, iclass 22, count 0 2006.218.07:40:08.52#ibcon#read 6, iclass 22, count 0 2006.218.07:40:08.52#ibcon#end of sib2, iclass 22, count 0 2006.218.07:40:08.52#ibcon#*mode == 0, iclass 22, count 0 2006.218.07:40:08.52#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.218.07:40:08.52#ibcon#[25=USB\r\n] 2006.218.07:40:08.52#ibcon#*before write, iclass 22, count 0 2006.218.07:40:08.52#ibcon#enter sib2, iclass 22, count 0 2006.218.07:40:08.52#ibcon#flushed, iclass 22, count 0 2006.218.07:40:08.52#ibcon#about to write, iclass 22, count 0 2006.218.07:40:08.52#ibcon#wrote, iclass 22, count 0 2006.218.07:40:08.52#ibcon#about to read 3, iclass 22, count 0 2006.218.07:40:08.55#ibcon#read 3, iclass 22, count 0 2006.218.07:40:08.55#ibcon#about to read 4, iclass 22, count 0 2006.218.07:40:08.55#ibcon#read 4, iclass 22, count 0 2006.218.07:40:08.55#ibcon#about to read 5, iclass 22, count 0 2006.218.07:40:08.55#ibcon#read 5, iclass 22, count 0 2006.218.07:40:08.55#ibcon#about to read 6, iclass 22, count 0 2006.218.07:40:08.55#ibcon#read 6, iclass 22, count 0 2006.218.07:40:08.55#ibcon#end of sib2, iclass 22, count 0 2006.218.07:40:08.55#ibcon#*after write, iclass 22, count 0 2006.218.07:40:08.55#ibcon#*before return 0, iclass 22, count 0 2006.218.07:40:08.55#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.218.07:40:08.55#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.218.07:40:08.55#ibcon#about to clear, iclass 22 cls_cnt 0 2006.218.07:40:08.55#ibcon#cleared, iclass 22 cls_cnt 0 2006.218.07:40:08.55$vc4f8/valo=3,672.99 2006.218.07:40:08.55#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.218.07:40:08.55#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.218.07:40:08.55#ibcon#ireg 17 cls_cnt 0 2006.218.07:40:08.55#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.218.07:40:08.55#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.218.07:40:08.55#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.218.07:40:08.55#ibcon#enter wrdev, iclass 24, count 0 2006.218.07:40:08.55#ibcon#first serial, iclass 24, count 0 2006.218.07:40:08.55#ibcon#enter sib2, iclass 24, count 0 2006.218.07:40:08.55#ibcon#flushed, iclass 24, count 0 2006.218.07:40:08.55#ibcon#about to write, iclass 24, count 0 2006.218.07:40:08.55#ibcon#wrote, iclass 24, count 0 2006.218.07:40:08.55#ibcon#about to read 3, iclass 24, count 0 2006.218.07:40:08.57#ibcon#read 3, iclass 24, count 0 2006.218.07:40:08.57#ibcon#about to read 4, iclass 24, count 0 2006.218.07:40:08.57#ibcon#read 4, iclass 24, count 0 2006.218.07:40:08.57#ibcon#about to read 5, iclass 24, count 0 2006.218.07:40:08.57#ibcon#read 5, iclass 24, count 0 2006.218.07:40:08.57#ibcon#about to read 6, iclass 24, count 0 2006.218.07:40:08.57#ibcon#read 6, iclass 24, count 0 2006.218.07:40:08.57#ibcon#end of sib2, iclass 24, count 0 2006.218.07:40:08.57#ibcon#*mode == 0, iclass 24, count 0 2006.218.07:40:08.57#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.218.07:40:08.57#ibcon#[26=FRQ=03,672.99\r\n] 2006.218.07:40:08.57#ibcon#*before write, iclass 24, count 0 2006.218.07:40:08.57#ibcon#enter sib2, iclass 24, count 0 2006.218.07:40:08.57#ibcon#flushed, iclass 24, count 0 2006.218.07:40:08.57#ibcon#about to write, iclass 24, count 0 2006.218.07:40:08.57#ibcon#wrote, iclass 24, count 0 2006.218.07:40:08.57#ibcon#about to read 3, iclass 24, count 0 2006.218.07:40:08.62#ibcon#read 3, iclass 24, count 0 2006.218.07:40:08.62#ibcon#about to read 4, iclass 24, count 0 2006.218.07:40:08.62#ibcon#read 4, iclass 24, count 0 2006.218.07:40:08.62#ibcon#about to read 5, iclass 24, count 0 2006.218.07:40:08.62#ibcon#read 5, iclass 24, count 0 2006.218.07:40:08.62#ibcon#about to read 6, iclass 24, count 0 2006.218.07:40:08.62#ibcon#read 6, iclass 24, count 0 2006.218.07:40:08.62#ibcon#end of sib2, iclass 24, count 0 2006.218.07:40:08.62#ibcon#*after write, iclass 24, count 0 2006.218.07:40:08.62#ibcon#*before return 0, iclass 24, count 0 2006.218.07:40:08.62#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.218.07:40:08.62#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.218.07:40:08.62#ibcon#about to clear, iclass 24 cls_cnt 0 2006.218.07:40:08.62#ibcon#cleared, iclass 24 cls_cnt 0 2006.218.07:40:08.62$vc4f8/va=3,4 2006.218.07:40:08.62#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.218.07:40:08.62#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.218.07:40:08.62#ibcon#ireg 11 cls_cnt 2 2006.218.07:40:08.62#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.218.07:40:08.67#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.218.07:40:08.67#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.218.07:40:08.67#ibcon#enter wrdev, iclass 26, count 2 2006.218.07:40:08.67#ibcon#first serial, iclass 26, count 2 2006.218.07:40:08.67#ibcon#enter sib2, iclass 26, count 2 2006.218.07:40:08.67#ibcon#flushed, iclass 26, count 2 2006.218.07:40:08.67#ibcon#about to write, iclass 26, count 2 2006.218.07:40:08.67#ibcon#wrote, iclass 26, count 2 2006.218.07:40:08.67#ibcon#about to read 3, iclass 26, count 2 2006.218.07:40:08.69#ibcon#read 3, iclass 26, count 2 2006.218.07:40:08.69#ibcon#about to read 4, iclass 26, count 2 2006.218.07:40:08.69#ibcon#read 4, iclass 26, count 2 2006.218.07:40:08.69#ibcon#about to read 5, iclass 26, count 2 2006.218.07:40:08.69#ibcon#read 5, iclass 26, count 2 2006.218.07:40:08.69#ibcon#about to read 6, iclass 26, count 2 2006.218.07:40:08.69#ibcon#read 6, iclass 26, count 2 2006.218.07:40:08.69#ibcon#end of sib2, iclass 26, count 2 2006.218.07:40:08.69#ibcon#*mode == 0, iclass 26, count 2 2006.218.07:40:08.69#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.218.07:40:08.69#ibcon#[25=AT03-04\r\n] 2006.218.07:40:08.69#ibcon#*before write, iclass 26, count 2 2006.218.07:40:08.69#ibcon#enter sib2, iclass 26, count 2 2006.218.07:40:08.69#ibcon#flushed, iclass 26, count 2 2006.218.07:40:08.69#ibcon#about to write, iclass 26, count 2 2006.218.07:40:08.69#ibcon#wrote, iclass 26, count 2 2006.218.07:40:08.69#ibcon#about to read 3, iclass 26, count 2 2006.218.07:40:08.72#ibcon#read 3, iclass 26, count 2 2006.218.07:40:08.72#ibcon#about to read 4, iclass 26, count 2 2006.218.07:40:08.72#ibcon#read 4, iclass 26, count 2 2006.218.07:40:08.72#ibcon#about to read 5, iclass 26, count 2 2006.218.07:40:08.72#ibcon#read 5, iclass 26, count 2 2006.218.07:40:08.72#ibcon#about to read 6, iclass 26, count 2 2006.218.07:40:08.72#ibcon#read 6, iclass 26, count 2 2006.218.07:40:08.72#ibcon#end of sib2, iclass 26, count 2 2006.218.07:40:08.72#ibcon#*after write, iclass 26, count 2 2006.218.07:40:08.72#ibcon#*before return 0, iclass 26, count 2 2006.218.07:40:08.72#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.218.07:40:08.72#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.218.07:40:08.72#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.218.07:40:08.72#ibcon#ireg 7 cls_cnt 0 2006.218.07:40:08.72#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.218.07:40:08.84#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.218.07:40:08.84#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.218.07:40:08.84#ibcon#enter wrdev, iclass 26, count 0 2006.218.07:40:08.84#ibcon#first serial, iclass 26, count 0 2006.218.07:40:08.84#ibcon#enter sib2, iclass 26, count 0 2006.218.07:40:08.84#ibcon#flushed, iclass 26, count 0 2006.218.07:40:08.84#ibcon#about to write, iclass 26, count 0 2006.218.07:40:08.84#ibcon#wrote, iclass 26, count 0 2006.218.07:40:08.84#ibcon#about to read 3, iclass 26, count 0 2006.218.07:40:08.86#ibcon#read 3, iclass 26, count 0 2006.218.07:40:08.86#ibcon#about to read 4, iclass 26, count 0 2006.218.07:40:08.86#ibcon#read 4, iclass 26, count 0 2006.218.07:40:08.86#ibcon#about to read 5, iclass 26, count 0 2006.218.07:40:08.86#ibcon#read 5, iclass 26, count 0 2006.218.07:40:08.86#ibcon#about to read 6, iclass 26, count 0 2006.218.07:40:08.86#ibcon#read 6, iclass 26, count 0 2006.218.07:40:08.86#ibcon#end of sib2, iclass 26, count 0 2006.218.07:40:08.86#ibcon#*mode == 0, iclass 26, count 0 2006.218.07:40:08.86#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.218.07:40:08.86#ibcon#[25=USB\r\n] 2006.218.07:40:08.86#ibcon#*before write, iclass 26, count 0 2006.218.07:40:08.86#ibcon#enter sib2, iclass 26, count 0 2006.218.07:40:08.86#ibcon#flushed, iclass 26, count 0 2006.218.07:40:08.86#ibcon#about to write, iclass 26, count 0 2006.218.07:40:08.86#ibcon#wrote, iclass 26, count 0 2006.218.07:40:08.86#ibcon#about to read 3, iclass 26, count 0 2006.218.07:40:08.89#ibcon#read 3, iclass 26, count 0 2006.218.07:40:08.89#ibcon#about to read 4, iclass 26, count 0 2006.218.07:40:08.89#ibcon#read 4, iclass 26, count 0 2006.218.07:40:08.89#ibcon#about to read 5, iclass 26, count 0 2006.218.07:40:08.89#ibcon#read 5, iclass 26, count 0 2006.218.07:40:08.89#ibcon#about to read 6, iclass 26, count 0 2006.218.07:40:08.89#ibcon#read 6, iclass 26, count 0 2006.218.07:40:08.89#ibcon#end of sib2, iclass 26, count 0 2006.218.07:40:08.89#ibcon#*after write, iclass 26, count 0 2006.218.07:40:08.89#ibcon#*before return 0, iclass 26, count 0 2006.218.07:40:08.89#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.218.07:40:08.89#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.218.07:40:08.89#ibcon#about to clear, iclass 26 cls_cnt 0 2006.218.07:40:08.89#ibcon#cleared, iclass 26 cls_cnt 0 2006.218.07:40:08.89$vc4f8/valo=4,832.99 2006.218.07:40:08.89#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.218.07:40:08.89#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.218.07:40:08.89#ibcon#ireg 17 cls_cnt 0 2006.218.07:40:08.89#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.218.07:40:08.89#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.218.07:40:08.89#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.218.07:40:08.89#ibcon#enter wrdev, iclass 28, count 0 2006.218.07:40:08.89#ibcon#first serial, iclass 28, count 0 2006.218.07:40:08.89#ibcon#enter sib2, iclass 28, count 0 2006.218.07:40:08.89#ibcon#flushed, iclass 28, count 0 2006.218.07:40:08.89#ibcon#about to write, iclass 28, count 0 2006.218.07:40:08.89#ibcon#wrote, iclass 28, count 0 2006.218.07:40:08.89#ibcon#about to read 3, iclass 28, count 0 2006.218.07:40:08.91#ibcon#read 3, iclass 28, count 0 2006.218.07:40:08.91#ibcon#about to read 4, iclass 28, count 0 2006.218.07:40:08.91#ibcon#read 4, iclass 28, count 0 2006.218.07:40:08.91#ibcon#about to read 5, iclass 28, count 0 2006.218.07:40:08.91#ibcon#read 5, iclass 28, count 0 2006.218.07:40:08.91#ibcon#about to read 6, iclass 28, count 0 2006.218.07:40:08.91#ibcon#read 6, iclass 28, count 0 2006.218.07:40:08.91#ibcon#end of sib2, iclass 28, count 0 2006.218.07:40:08.91#ibcon#*mode == 0, iclass 28, count 0 2006.218.07:40:08.91#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.218.07:40:08.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.218.07:40:08.91#ibcon#*before write, iclass 28, count 0 2006.218.07:40:08.91#ibcon#enter sib2, iclass 28, count 0 2006.218.07:40:08.91#ibcon#flushed, iclass 28, count 0 2006.218.07:40:08.91#ibcon#about to write, iclass 28, count 0 2006.218.07:40:08.91#ibcon#wrote, iclass 28, count 0 2006.218.07:40:08.91#ibcon#about to read 3, iclass 28, count 0 2006.218.07:40:08.95#ibcon#read 3, iclass 28, count 0 2006.218.07:40:08.95#ibcon#about to read 4, iclass 28, count 0 2006.218.07:40:08.95#ibcon#read 4, iclass 28, count 0 2006.218.07:40:08.95#ibcon#about to read 5, iclass 28, count 0 2006.218.07:40:08.95#ibcon#read 5, iclass 28, count 0 2006.218.07:40:08.95#ibcon#about to read 6, iclass 28, count 0 2006.218.07:40:08.95#ibcon#read 6, iclass 28, count 0 2006.218.07:40:08.95#ibcon#end of sib2, iclass 28, count 0 2006.218.07:40:08.95#ibcon#*after write, iclass 28, count 0 2006.218.07:40:08.95#ibcon#*before return 0, iclass 28, count 0 2006.218.07:40:08.95#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.218.07:40:08.95#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.218.07:40:08.95#ibcon#about to clear, iclass 28 cls_cnt 0 2006.218.07:40:08.95#ibcon#cleared, iclass 28 cls_cnt 0 2006.218.07:40:08.95$vc4f8/va=4,4 2006.218.07:40:08.95#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.218.07:40:08.95#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.218.07:40:08.95#ibcon#ireg 11 cls_cnt 2 2006.218.07:40:08.95#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.218.07:40:09.01#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.218.07:40:09.01#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.218.07:40:09.01#ibcon#enter wrdev, iclass 30, count 2 2006.218.07:40:09.01#ibcon#first serial, iclass 30, count 2 2006.218.07:40:09.01#ibcon#enter sib2, iclass 30, count 2 2006.218.07:40:09.01#ibcon#flushed, iclass 30, count 2 2006.218.07:40:09.01#ibcon#about to write, iclass 30, count 2 2006.218.07:40:09.01#ibcon#wrote, iclass 30, count 2 2006.218.07:40:09.01#ibcon#about to read 3, iclass 30, count 2 2006.218.07:40:09.03#ibcon#read 3, iclass 30, count 2 2006.218.07:40:09.03#ibcon#about to read 4, iclass 30, count 2 2006.218.07:40:09.03#ibcon#read 4, iclass 30, count 2 2006.218.07:40:09.03#ibcon#about to read 5, iclass 30, count 2 2006.218.07:40:09.03#ibcon#read 5, iclass 30, count 2 2006.218.07:40:09.03#ibcon#about to read 6, iclass 30, count 2 2006.218.07:40:09.03#ibcon#read 6, iclass 30, count 2 2006.218.07:40:09.03#ibcon#end of sib2, iclass 30, count 2 2006.218.07:40:09.03#ibcon#*mode == 0, iclass 30, count 2 2006.218.07:40:09.03#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.218.07:40:09.03#ibcon#[25=AT04-04\r\n] 2006.218.07:40:09.03#ibcon#*before write, iclass 30, count 2 2006.218.07:40:09.03#ibcon#enter sib2, iclass 30, count 2 2006.218.07:40:09.03#ibcon#flushed, iclass 30, count 2 2006.218.07:40:09.03#ibcon#about to write, iclass 30, count 2 2006.218.07:40:09.03#ibcon#wrote, iclass 30, count 2 2006.218.07:40:09.03#ibcon#about to read 3, iclass 30, count 2 2006.218.07:40:09.06#ibcon#read 3, iclass 30, count 2 2006.218.07:40:09.06#ibcon#about to read 4, iclass 30, count 2 2006.218.07:40:09.06#ibcon#read 4, iclass 30, count 2 2006.218.07:40:09.06#ibcon#about to read 5, iclass 30, count 2 2006.218.07:40:09.06#ibcon#read 5, iclass 30, count 2 2006.218.07:40:09.06#ibcon#about to read 6, iclass 30, count 2 2006.218.07:40:09.06#ibcon#read 6, iclass 30, count 2 2006.218.07:40:09.06#ibcon#end of sib2, iclass 30, count 2 2006.218.07:40:09.06#ibcon#*after write, iclass 30, count 2 2006.218.07:40:09.06#ibcon#*before return 0, iclass 30, count 2 2006.218.07:40:09.06#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.218.07:40:09.06#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.218.07:40:09.06#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.218.07:40:09.06#ibcon#ireg 7 cls_cnt 0 2006.218.07:40:09.06#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.218.07:40:09.18#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.218.07:40:09.18#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.218.07:40:09.18#ibcon#enter wrdev, iclass 30, count 0 2006.218.07:40:09.18#ibcon#first serial, iclass 30, count 0 2006.218.07:40:09.18#ibcon#enter sib2, iclass 30, count 0 2006.218.07:40:09.18#ibcon#flushed, iclass 30, count 0 2006.218.07:40:09.18#ibcon#about to write, iclass 30, count 0 2006.218.07:40:09.18#ibcon#wrote, iclass 30, count 0 2006.218.07:40:09.18#ibcon#about to read 3, iclass 30, count 0 2006.218.07:40:09.20#ibcon#read 3, iclass 30, count 0 2006.218.07:40:09.20#ibcon#about to read 4, iclass 30, count 0 2006.218.07:40:09.20#ibcon#read 4, iclass 30, count 0 2006.218.07:40:09.20#ibcon#about to read 5, iclass 30, count 0 2006.218.07:40:09.20#ibcon#read 5, iclass 30, count 0 2006.218.07:40:09.20#ibcon#about to read 6, iclass 30, count 0 2006.218.07:40:09.20#ibcon#read 6, iclass 30, count 0 2006.218.07:40:09.20#ibcon#end of sib2, iclass 30, count 0 2006.218.07:40:09.20#ibcon#*mode == 0, iclass 30, count 0 2006.218.07:40:09.20#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.218.07:40:09.20#ibcon#[25=USB\r\n] 2006.218.07:40:09.20#ibcon#*before write, iclass 30, count 0 2006.218.07:40:09.20#ibcon#enter sib2, iclass 30, count 0 2006.218.07:40:09.20#ibcon#flushed, iclass 30, count 0 2006.218.07:40:09.20#ibcon#about to write, iclass 30, count 0 2006.218.07:40:09.20#ibcon#wrote, iclass 30, count 0 2006.218.07:40:09.20#ibcon#about to read 3, iclass 30, count 0 2006.218.07:40:09.23#ibcon#read 3, iclass 30, count 0 2006.218.07:40:09.23#ibcon#about to read 4, iclass 30, count 0 2006.218.07:40:09.23#ibcon#read 4, iclass 30, count 0 2006.218.07:40:09.23#ibcon#about to read 5, iclass 30, count 0 2006.218.07:40:09.23#ibcon#read 5, iclass 30, count 0 2006.218.07:40:09.23#ibcon#about to read 6, iclass 30, count 0 2006.218.07:40:09.23#ibcon#read 6, iclass 30, count 0 2006.218.07:40:09.23#ibcon#end of sib2, iclass 30, count 0 2006.218.07:40:09.23#ibcon#*after write, iclass 30, count 0 2006.218.07:40:09.23#ibcon#*before return 0, iclass 30, count 0 2006.218.07:40:09.23#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.218.07:40:09.23#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.218.07:40:09.23#ibcon#about to clear, iclass 30 cls_cnt 0 2006.218.07:40:09.23#ibcon#cleared, iclass 30 cls_cnt 0 2006.218.07:40:09.23$vc4f8/valo=5,652.99 2006.218.07:40:09.23#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.218.07:40:09.23#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.218.07:40:09.23#ibcon#ireg 17 cls_cnt 0 2006.218.07:40:09.23#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.218.07:40:09.23#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.218.07:40:09.23#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.218.07:40:09.23#ibcon#enter wrdev, iclass 32, count 0 2006.218.07:40:09.23#ibcon#first serial, iclass 32, count 0 2006.218.07:40:09.23#ibcon#enter sib2, iclass 32, count 0 2006.218.07:40:09.23#ibcon#flushed, iclass 32, count 0 2006.218.07:40:09.23#ibcon#about to write, iclass 32, count 0 2006.218.07:40:09.23#ibcon#wrote, iclass 32, count 0 2006.218.07:40:09.23#ibcon#about to read 3, iclass 32, count 0 2006.218.07:40:09.25#ibcon#read 3, iclass 32, count 0 2006.218.07:40:09.25#ibcon#about to read 4, iclass 32, count 0 2006.218.07:40:09.25#ibcon#read 4, iclass 32, count 0 2006.218.07:40:09.25#ibcon#about to read 5, iclass 32, count 0 2006.218.07:40:09.25#ibcon#read 5, iclass 32, count 0 2006.218.07:40:09.25#ibcon#about to read 6, iclass 32, count 0 2006.218.07:40:09.25#ibcon#read 6, iclass 32, count 0 2006.218.07:40:09.25#ibcon#end of sib2, iclass 32, count 0 2006.218.07:40:09.25#ibcon#*mode == 0, iclass 32, count 0 2006.218.07:40:09.25#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.218.07:40:09.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.218.07:40:09.25#ibcon#*before write, iclass 32, count 0 2006.218.07:40:09.25#ibcon#enter sib2, iclass 32, count 0 2006.218.07:40:09.25#ibcon#flushed, iclass 32, count 0 2006.218.07:40:09.25#ibcon#about to write, iclass 32, count 0 2006.218.07:40:09.25#ibcon#wrote, iclass 32, count 0 2006.218.07:40:09.25#ibcon#about to read 3, iclass 32, count 0 2006.218.07:40:09.29#ibcon#read 3, iclass 32, count 0 2006.218.07:40:09.29#ibcon#about to read 4, iclass 32, count 0 2006.218.07:40:09.29#ibcon#read 4, iclass 32, count 0 2006.218.07:40:09.29#ibcon#about to read 5, iclass 32, count 0 2006.218.07:40:09.29#ibcon#read 5, iclass 32, count 0 2006.218.07:40:09.29#ibcon#about to read 6, iclass 32, count 0 2006.218.07:40:09.29#ibcon#read 6, iclass 32, count 0 2006.218.07:40:09.29#ibcon#end of sib2, iclass 32, count 0 2006.218.07:40:09.29#ibcon#*after write, iclass 32, count 0 2006.218.07:40:09.29#ibcon#*before return 0, iclass 32, count 0 2006.218.07:40:09.29#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.218.07:40:09.29#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.218.07:40:09.29#ibcon#about to clear, iclass 32 cls_cnt 0 2006.218.07:40:09.29#ibcon#cleared, iclass 32 cls_cnt 0 2006.218.07:40:09.29$vc4f8/va=5,7 2006.218.07:40:09.29#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.218.07:40:09.29#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.218.07:40:09.29#ibcon#ireg 11 cls_cnt 2 2006.218.07:40:09.29#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.218.07:40:09.35#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.218.07:40:09.35#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.218.07:40:09.35#ibcon#enter wrdev, iclass 34, count 2 2006.218.07:40:09.35#ibcon#first serial, iclass 34, count 2 2006.218.07:40:09.35#ibcon#enter sib2, iclass 34, count 2 2006.218.07:40:09.35#ibcon#flushed, iclass 34, count 2 2006.218.07:40:09.35#ibcon#about to write, iclass 34, count 2 2006.218.07:40:09.35#ibcon#wrote, iclass 34, count 2 2006.218.07:40:09.35#ibcon#about to read 3, iclass 34, count 2 2006.218.07:40:09.37#ibcon#read 3, iclass 34, count 2 2006.218.07:40:09.37#ibcon#about to read 4, iclass 34, count 2 2006.218.07:40:09.37#ibcon#read 4, iclass 34, count 2 2006.218.07:40:09.37#ibcon#about to read 5, iclass 34, count 2 2006.218.07:40:09.37#ibcon#read 5, iclass 34, count 2 2006.218.07:40:09.37#ibcon#about to read 6, iclass 34, count 2 2006.218.07:40:09.37#ibcon#read 6, iclass 34, count 2 2006.218.07:40:09.37#ibcon#end of sib2, iclass 34, count 2 2006.218.07:40:09.37#ibcon#*mode == 0, iclass 34, count 2 2006.218.07:40:09.37#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.218.07:40:09.37#ibcon#[25=AT05-07\r\n] 2006.218.07:40:09.37#ibcon#*before write, iclass 34, count 2 2006.218.07:40:09.37#ibcon#enter sib2, iclass 34, count 2 2006.218.07:40:09.37#ibcon#flushed, iclass 34, count 2 2006.218.07:40:09.37#ibcon#about to write, iclass 34, count 2 2006.218.07:40:09.37#ibcon#wrote, iclass 34, count 2 2006.218.07:40:09.37#ibcon#about to read 3, iclass 34, count 2 2006.218.07:40:09.40#ibcon#read 3, iclass 34, count 2 2006.218.07:40:09.40#ibcon#about to read 4, iclass 34, count 2 2006.218.07:40:09.40#ibcon#read 4, iclass 34, count 2 2006.218.07:40:09.40#ibcon#about to read 5, iclass 34, count 2 2006.218.07:40:09.40#ibcon#read 5, iclass 34, count 2 2006.218.07:40:09.40#ibcon#about to read 6, iclass 34, count 2 2006.218.07:40:09.40#ibcon#read 6, iclass 34, count 2 2006.218.07:40:09.40#ibcon#end of sib2, iclass 34, count 2 2006.218.07:40:09.40#ibcon#*after write, iclass 34, count 2 2006.218.07:40:09.40#ibcon#*before return 0, iclass 34, count 2 2006.218.07:40:09.40#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.218.07:40:09.40#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.218.07:40:09.40#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.218.07:40:09.40#ibcon#ireg 7 cls_cnt 0 2006.218.07:40:09.40#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.218.07:40:09.54#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.218.07:40:09.54#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.218.07:40:09.54#ibcon#enter wrdev, iclass 34, count 0 2006.218.07:40:09.54#ibcon#first serial, iclass 34, count 0 2006.218.07:40:09.54#ibcon#enter sib2, iclass 34, count 0 2006.218.07:40:09.54#ibcon#flushed, iclass 34, count 0 2006.218.07:40:09.54#ibcon#about to write, iclass 34, count 0 2006.218.07:40:09.54#ibcon#wrote, iclass 34, count 0 2006.218.07:40:09.54#ibcon#about to read 3, iclass 34, count 0 2006.218.07:40:09.56#ibcon#read 3, iclass 34, count 0 2006.218.07:40:09.56#ibcon#about to read 4, iclass 34, count 0 2006.218.07:40:09.56#ibcon#read 4, iclass 34, count 0 2006.218.07:40:09.56#ibcon#about to read 5, iclass 34, count 0 2006.218.07:40:09.56#ibcon#read 5, iclass 34, count 0 2006.218.07:40:09.56#ibcon#about to read 6, iclass 34, count 0 2006.218.07:40:09.56#ibcon#read 6, iclass 34, count 0 2006.218.07:40:09.56#ibcon#end of sib2, iclass 34, count 0 2006.218.07:40:09.56#ibcon#*mode == 0, iclass 34, count 0 2006.218.07:40:09.56#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.218.07:40:09.56#ibcon#[25=USB\r\n] 2006.218.07:40:09.56#ibcon#*before write, iclass 34, count 0 2006.218.07:40:09.56#ibcon#enter sib2, iclass 34, count 0 2006.218.07:40:09.56#ibcon#flushed, iclass 34, count 0 2006.218.07:40:09.56#ibcon#about to write, iclass 34, count 0 2006.218.07:40:09.56#ibcon#wrote, iclass 34, count 0 2006.218.07:40:09.56#ibcon#about to read 3, iclass 34, count 0 2006.218.07:40:09.59#ibcon#read 3, iclass 34, count 0 2006.218.07:40:09.59#ibcon#about to read 4, iclass 34, count 0 2006.218.07:40:09.59#ibcon#read 4, iclass 34, count 0 2006.218.07:40:09.59#ibcon#about to read 5, iclass 34, count 0 2006.218.07:40:09.59#ibcon#read 5, iclass 34, count 0 2006.218.07:40:09.59#ibcon#about to read 6, iclass 34, count 0 2006.218.07:40:09.59#ibcon#read 6, iclass 34, count 0 2006.218.07:40:09.59#ibcon#end of sib2, iclass 34, count 0 2006.218.07:40:09.59#ibcon#*after write, iclass 34, count 0 2006.218.07:40:09.59#ibcon#*before return 0, iclass 34, count 0 2006.218.07:40:09.59#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.218.07:40:09.59#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.218.07:40:09.59#ibcon#about to clear, iclass 34 cls_cnt 0 2006.218.07:40:09.59#ibcon#cleared, iclass 34 cls_cnt 0 2006.218.07:40:09.59$vc4f8/valo=6,772.99 2006.218.07:40:09.59#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.218.07:40:09.59#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.218.07:40:09.59#ibcon#ireg 17 cls_cnt 0 2006.218.07:40:09.59#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.218.07:40:09.59#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.218.07:40:09.59#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.218.07:40:09.59#ibcon#enter wrdev, iclass 36, count 0 2006.218.07:40:09.59#ibcon#first serial, iclass 36, count 0 2006.218.07:40:09.59#ibcon#enter sib2, iclass 36, count 0 2006.218.07:40:09.59#ibcon#flushed, iclass 36, count 0 2006.218.07:40:09.59#ibcon#about to write, iclass 36, count 0 2006.218.07:40:09.59#ibcon#wrote, iclass 36, count 0 2006.218.07:40:09.59#ibcon#about to read 3, iclass 36, count 0 2006.218.07:40:09.61#ibcon#read 3, iclass 36, count 0 2006.218.07:40:09.61#ibcon#about to read 4, iclass 36, count 0 2006.218.07:40:09.61#ibcon#read 4, iclass 36, count 0 2006.218.07:40:09.61#ibcon#about to read 5, iclass 36, count 0 2006.218.07:40:09.61#ibcon#read 5, iclass 36, count 0 2006.218.07:40:09.61#ibcon#about to read 6, iclass 36, count 0 2006.218.07:40:09.61#ibcon#read 6, iclass 36, count 0 2006.218.07:40:09.61#ibcon#end of sib2, iclass 36, count 0 2006.218.07:40:09.61#ibcon#*mode == 0, iclass 36, count 0 2006.218.07:40:09.61#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.218.07:40:09.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.218.07:40:09.61#ibcon#*before write, iclass 36, count 0 2006.218.07:40:09.61#ibcon#enter sib2, iclass 36, count 0 2006.218.07:40:09.61#ibcon#flushed, iclass 36, count 0 2006.218.07:40:09.61#ibcon#about to write, iclass 36, count 0 2006.218.07:40:09.61#ibcon#wrote, iclass 36, count 0 2006.218.07:40:09.61#ibcon#about to read 3, iclass 36, count 0 2006.218.07:40:09.66#ibcon#read 3, iclass 36, count 0 2006.218.07:40:09.66#ibcon#about to read 4, iclass 36, count 0 2006.218.07:40:09.66#ibcon#read 4, iclass 36, count 0 2006.218.07:40:09.66#ibcon#about to read 5, iclass 36, count 0 2006.218.07:40:09.66#ibcon#read 5, iclass 36, count 0 2006.218.07:40:09.66#ibcon#about to read 6, iclass 36, count 0 2006.218.07:40:09.66#ibcon#read 6, iclass 36, count 0 2006.218.07:40:09.66#ibcon#end of sib2, iclass 36, count 0 2006.218.07:40:09.66#ibcon#*after write, iclass 36, count 0 2006.218.07:40:09.66#ibcon#*before return 0, iclass 36, count 0 2006.218.07:40:09.66#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.218.07:40:09.66#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.218.07:40:09.66#ibcon#about to clear, iclass 36 cls_cnt 0 2006.218.07:40:09.66#ibcon#cleared, iclass 36 cls_cnt 0 2006.218.07:40:09.66$vc4f8/va=6,6 2006.218.07:40:09.66#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.218.07:40:09.66#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.218.07:40:09.66#ibcon#ireg 11 cls_cnt 2 2006.218.07:40:09.66#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.218.07:40:09.71#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.218.07:40:09.71#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.218.07:40:09.71#ibcon#enter wrdev, iclass 38, count 2 2006.218.07:40:09.71#ibcon#first serial, iclass 38, count 2 2006.218.07:40:09.71#ibcon#enter sib2, iclass 38, count 2 2006.218.07:40:09.71#ibcon#flushed, iclass 38, count 2 2006.218.07:40:09.71#ibcon#about to write, iclass 38, count 2 2006.218.07:40:09.71#ibcon#wrote, iclass 38, count 2 2006.218.07:40:09.71#ibcon#about to read 3, iclass 38, count 2 2006.218.07:40:09.73#ibcon#read 3, iclass 38, count 2 2006.218.07:40:09.73#ibcon#about to read 4, iclass 38, count 2 2006.218.07:40:09.73#ibcon#read 4, iclass 38, count 2 2006.218.07:40:09.73#ibcon#about to read 5, iclass 38, count 2 2006.218.07:40:09.73#ibcon#read 5, iclass 38, count 2 2006.218.07:40:09.73#ibcon#about to read 6, iclass 38, count 2 2006.218.07:40:09.73#ibcon#read 6, iclass 38, count 2 2006.218.07:40:09.73#ibcon#end of sib2, iclass 38, count 2 2006.218.07:40:09.73#ibcon#*mode == 0, iclass 38, count 2 2006.218.07:40:09.73#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.218.07:40:09.73#ibcon#[25=AT06-06\r\n] 2006.218.07:40:09.73#ibcon#*before write, iclass 38, count 2 2006.218.07:40:09.73#ibcon#enter sib2, iclass 38, count 2 2006.218.07:40:09.73#ibcon#flushed, iclass 38, count 2 2006.218.07:40:09.73#ibcon#about to write, iclass 38, count 2 2006.218.07:40:09.73#ibcon#wrote, iclass 38, count 2 2006.218.07:40:09.73#ibcon#about to read 3, iclass 38, count 2 2006.218.07:40:09.76#ibcon#read 3, iclass 38, count 2 2006.218.07:40:09.76#ibcon#about to read 4, iclass 38, count 2 2006.218.07:40:09.76#ibcon#read 4, iclass 38, count 2 2006.218.07:40:09.76#ibcon#about to read 5, iclass 38, count 2 2006.218.07:40:09.76#ibcon#read 5, iclass 38, count 2 2006.218.07:40:09.76#ibcon#about to read 6, iclass 38, count 2 2006.218.07:40:09.76#ibcon#read 6, iclass 38, count 2 2006.218.07:40:09.76#ibcon#end of sib2, iclass 38, count 2 2006.218.07:40:09.76#ibcon#*after write, iclass 38, count 2 2006.218.07:40:09.76#ibcon#*before return 0, iclass 38, count 2 2006.218.07:40:09.76#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.218.07:40:09.76#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.218.07:40:09.76#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.218.07:40:09.76#ibcon#ireg 7 cls_cnt 0 2006.218.07:40:09.76#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.218.07:40:09.88#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.218.07:40:09.88#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.218.07:40:09.88#ibcon#enter wrdev, iclass 38, count 0 2006.218.07:40:09.88#ibcon#first serial, iclass 38, count 0 2006.218.07:40:09.88#ibcon#enter sib2, iclass 38, count 0 2006.218.07:40:09.88#ibcon#flushed, iclass 38, count 0 2006.218.07:40:09.88#ibcon#about to write, iclass 38, count 0 2006.218.07:40:09.88#ibcon#wrote, iclass 38, count 0 2006.218.07:40:09.88#ibcon#about to read 3, iclass 38, count 0 2006.218.07:40:09.90#ibcon#read 3, iclass 38, count 0 2006.218.07:40:09.90#ibcon#about to read 4, iclass 38, count 0 2006.218.07:40:09.90#ibcon#read 4, iclass 38, count 0 2006.218.07:40:09.90#ibcon#about to read 5, iclass 38, count 0 2006.218.07:40:09.90#ibcon#read 5, iclass 38, count 0 2006.218.07:40:09.90#ibcon#about to read 6, iclass 38, count 0 2006.218.07:40:09.90#ibcon#read 6, iclass 38, count 0 2006.218.07:40:09.90#ibcon#end of sib2, iclass 38, count 0 2006.218.07:40:09.90#ibcon#*mode == 0, iclass 38, count 0 2006.218.07:40:09.90#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.218.07:40:09.90#ibcon#[25=USB\r\n] 2006.218.07:40:09.90#ibcon#*before write, iclass 38, count 0 2006.218.07:40:09.90#ibcon#enter sib2, iclass 38, count 0 2006.218.07:40:09.90#ibcon#flushed, iclass 38, count 0 2006.218.07:40:09.90#ibcon#about to write, iclass 38, count 0 2006.218.07:40:09.90#ibcon#wrote, iclass 38, count 0 2006.218.07:40:09.90#ibcon#about to read 3, iclass 38, count 0 2006.218.07:40:09.93#ibcon#read 3, iclass 38, count 0 2006.218.07:40:09.93#ibcon#about to read 4, iclass 38, count 0 2006.218.07:40:09.93#ibcon#read 4, iclass 38, count 0 2006.218.07:40:09.93#ibcon#about to read 5, iclass 38, count 0 2006.218.07:40:09.93#ibcon#read 5, iclass 38, count 0 2006.218.07:40:09.93#ibcon#about to read 6, iclass 38, count 0 2006.218.07:40:09.93#ibcon#read 6, iclass 38, count 0 2006.218.07:40:09.93#ibcon#end of sib2, iclass 38, count 0 2006.218.07:40:09.93#ibcon#*after write, iclass 38, count 0 2006.218.07:40:09.93#ibcon#*before return 0, iclass 38, count 0 2006.218.07:40:09.93#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.218.07:40:09.93#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.218.07:40:09.93#ibcon#about to clear, iclass 38 cls_cnt 0 2006.218.07:40:09.93#ibcon#cleared, iclass 38 cls_cnt 0 2006.218.07:40:09.93$vc4f8/valo=7,832.99 2006.218.07:40:09.93#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.218.07:40:09.93#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.218.07:40:09.93#ibcon#ireg 17 cls_cnt 0 2006.218.07:40:09.93#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.218.07:40:09.93#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.218.07:40:09.93#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.218.07:40:09.93#ibcon#enter wrdev, iclass 40, count 0 2006.218.07:40:09.93#ibcon#first serial, iclass 40, count 0 2006.218.07:40:09.93#ibcon#enter sib2, iclass 40, count 0 2006.218.07:40:09.93#ibcon#flushed, iclass 40, count 0 2006.218.07:40:09.93#ibcon#about to write, iclass 40, count 0 2006.218.07:40:09.93#ibcon#wrote, iclass 40, count 0 2006.218.07:40:09.93#ibcon#about to read 3, iclass 40, count 0 2006.218.07:40:09.95#ibcon#read 3, iclass 40, count 0 2006.218.07:40:09.95#ibcon#about to read 4, iclass 40, count 0 2006.218.07:40:09.95#ibcon#read 4, iclass 40, count 0 2006.218.07:40:09.95#ibcon#about to read 5, iclass 40, count 0 2006.218.07:40:09.95#ibcon#read 5, iclass 40, count 0 2006.218.07:40:09.95#ibcon#about to read 6, iclass 40, count 0 2006.218.07:40:09.95#ibcon#read 6, iclass 40, count 0 2006.218.07:40:09.95#ibcon#end of sib2, iclass 40, count 0 2006.218.07:40:09.95#ibcon#*mode == 0, iclass 40, count 0 2006.218.07:40:09.95#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.218.07:40:09.95#ibcon#[26=FRQ=07,832.99\r\n] 2006.218.07:40:09.95#ibcon#*before write, iclass 40, count 0 2006.218.07:40:09.95#ibcon#enter sib2, iclass 40, count 0 2006.218.07:40:09.95#ibcon#flushed, iclass 40, count 0 2006.218.07:40:09.95#ibcon#about to write, iclass 40, count 0 2006.218.07:40:09.95#ibcon#wrote, iclass 40, count 0 2006.218.07:40:09.95#ibcon#about to read 3, iclass 40, count 0 2006.218.07:40:09.99#ibcon#read 3, iclass 40, count 0 2006.218.07:40:09.99#ibcon#about to read 4, iclass 40, count 0 2006.218.07:40:09.99#ibcon#read 4, iclass 40, count 0 2006.218.07:40:09.99#ibcon#about to read 5, iclass 40, count 0 2006.218.07:40:09.99#ibcon#read 5, iclass 40, count 0 2006.218.07:40:09.99#ibcon#about to read 6, iclass 40, count 0 2006.218.07:40:09.99#ibcon#read 6, iclass 40, count 0 2006.218.07:40:09.99#ibcon#end of sib2, iclass 40, count 0 2006.218.07:40:09.99#ibcon#*after write, iclass 40, count 0 2006.218.07:40:09.99#ibcon#*before return 0, iclass 40, count 0 2006.218.07:40:09.99#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.218.07:40:09.99#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.218.07:40:09.99#ibcon#about to clear, iclass 40 cls_cnt 0 2006.218.07:40:09.99#ibcon#cleared, iclass 40 cls_cnt 0 2006.218.07:40:09.99$vc4f8/va=7,6 2006.218.07:40:09.99#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.218.07:40:09.99#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.218.07:40:09.99#ibcon#ireg 11 cls_cnt 2 2006.218.07:40:09.99#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.218.07:40:10.05#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.218.07:40:10.05#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.218.07:40:10.05#ibcon#enter wrdev, iclass 4, count 2 2006.218.07:40:10.05#ibcon#first serial, iclass 4, count 2 2006.218.07:40:10.05#ibcon#enter sib2, iclass 4, count 2 2006.218.07:40:10.05#ibcon#flushed, iclass 4, count 2 2006.218.07:40:10.05#ibcon#about to write, iclass 4, count 2 2006.218.07:40:10.05#ibcon#wrote, iclass 4, count 2 2006.218.07:40:10.05#ibcon#about to read 3, iclass 4, count 2 2006.218.07:40:10.07#ibcon#read 3, iclass 4, count 2 2006.218.07:40:10.07#ibcon#about to read 4, iclass 4, count 2 2006.218.07:40:10.07#ibcon#read 4, iclass 4, count 2 2006.218.07:40:10.07#ibcon#about to read 5, iclass 4, count 2 2006.218.07:40:10.07#ibcon#read 5, iclass 4, count 2 2006.218.07:40:10.07#ibcon#about to read 6, iclass 4, count 2 2006.218.07:40:10.07#ibcon#read 6, iclass 4, count 2 2006.218.07:40:10.07#ibcon#end of sib2, iclass 4, count 2 2006.218.07:40:10.07#ibcon#*mode == 0, iclass 4, count 2 2006.218.07:40:10.07#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.218.07:40:10.07#ibcon#[25=AT07-06\r\n] 2006.218.07:40:10.07#ibcon#*before write, iclass 4, count 2 2006.218.07:40:10.07#ibcon#enter sib2, iclass 4, count 2 2006.218.07:40:10.07#ibcon#flushed, iclass 4, count 2 2006.218.07:40:10.07#ibcon#about to write, iclass 4, count 2 2006.218.07:40:10.07#ibcon#wrote, iclass 4, count 2 2006.218.07:40:10.07#ibcon#about to read 3, iclass 4, count 2 2006.218.07:40:10.10#ibcon#read 3, iclass 4, count 2 2006.218.07:40:10.10#ibcon#about to read 4, iclass 4, count 2 2006.218.07:40:10.10#ibcon#read 4, iclass 4, count 2 2006.218.07:40:10.10#ibcon#about to read 5, iclass 4, count 2 2006.218.07:40:10.10#ibcon#read 5, iclass 4, count 2 2006.218.07:40:10.10#ibcon#about to read 6, iclass 4, count 2 2006.218.07:40:10.10#ibcon#read 6, iclass 4, count 2 2006.218.07:40:10.10#ibcon#end of sib2, iclass 4, count 2 2006.218.07:40:10.10#ibcon#*after write, iclass 4, count 2 2006.218.07:40:10.10#ibcon#*before return 0, iclass 4, count 2 2006.218.07:40:10.10#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.218.07:40:10.10#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.218.07:40:10.10#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.218.07:40:10.10#ibcon#ireg 7 cls_cnt 0 2006.218.07:40:10.10#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.218.07:40:10.22#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.218.07:40:10.22#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.218.07:40:10.22#ibcon#enter wrdev, iclass 4, count 0 2006.218.07:40:10.22#ibcon#first serial, iclass 4, count 0 2006.218.07:40:10.22#ibcon#enter sib2, iclass 4, count 0 2006.218.07:40:10.22#ibcon#flushed, iclass 4, count 0 2006.218.07:40:10.22#ibcon#about to write, iclass 4, count 0 2006.218.07:40:10.22#ibcon#wrote, iclass 4, count 0 2006.218.07:40:10.22#ibcon#about to read 3, iclass 4, count 0 2006.218.07:40:10.24#ibcon#read 3, iclass 4, count 0 2006.218.07:40:10.24#ibcon#about to read 4, iclass 4, count 0 2006.218.07:40:10.24#ibcon#read 4, iclass 4, count 0 2006.218.07:40:10.24#ibcon#about to read 5, iclass 4, count 0 2006.218.07:40:10.24#ibcon#read 5, iclass 4, count 0 2006.218.07:40:10.24#ibcon#about to read 6, iclass 4, count 0 2006.218.07:40:10.24#ibcon#read 6, iclass 4, count 0 2006.218.07:40:10.24#ibcon#end of sib2, iclass 4, count 0 2006.218.07:40:10.24#ibcon#*mode == 0, iclass 4, count 0 2006.218.07:40:10.24#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.218.07:40:10.24#ibcon#[25=USB\r\n] 2006.218.07:40:10.24#ibcon#*before write, iclass 4, count 0 2006.218.07:40:10.24#ibcon#enter sib2, iclass 4, count 0 2006.218.07:40:10.24#ibcon#flushed, iclass 4, count 0 2006.218.07:40:10.24#ibcon#about to write, iclass 4, count 0 2006.218.07:40:10.24#ibcon#wrote, iclass 4, count 0 2006.218.07:40:10.24#ibcon#about to read 3, iclass 4, count 0 2006.218.07:40:10.27#ibcon#read 3, iclass 4, count 0 2006.218.07:40:10.27#ibcon#about to read 4, iclass 4, count 0 2006.218.07:40:10.27#ibcon#read 4, iclass 4, count 0 2006.218.07:40:10.27#ibcon#about to read 5, iclass 4, count 0 2006.218.07:40:10.27#ibcon#read 5, iclass 4, count 0 2006.218.07:40:10.27#ibcon#about to read 6, iclass 4, count 0 2006.218.07:40:10.27#ibcon#read 6, iclass 4, count 0 2006.218.07:40:10.27#ibcon#end of sib2, iclass 4, count 0 2006.218.07:40:10.27#ibcon#*after write, iclass 4, count 0 2006.218.07:40:10.27#ibcon#*before return 0, iclass 4, count 0 2006.218.07:40:10.27#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.218.07:40:10.27#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.218.07:40:10.27#ibcon#about to clear, iclass 4 cls_cnt 0 2006.218.07:40:10.27#ibcon#cleared, iclass 4 cls_cnt 0 2006.218.07:40:10.27$vc4f8/valo=8,852.99 2006.218.07:40:10.27#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.218.07:40:10.27#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.218.07:40:10.27#ibcon#ireg 17 cls_cnt 0 2006.218.07:40:10.27#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.218.07:40:10.27#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.218.07:40:10.27#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.218.07:40:10.27#ibcon#enter wrdev, iclass 6, count 0 2006.218.07:40:10.27#ibcon#first serial, iclass 6, count 0 2006.218.07:40:10.27#ibcon#enter sib2, iclass 6, count 0 2006.218.07:40:10.27#ibcon#flushed, iclass 6, count 0 2006.218.07:40:10.27#ibcon#about to write, iclass 6, count 0 2006.218.07:40:10.27#ibcon#wrote, iclass 6, count 0 2006.218.07:40:10.27#ibcon#about to read 3, iclass 6, count 0 2006.218.07:40:10.29#ibcon#read 3, iclass 6, count 0 2006.218.07:40:10.29#ibcon#about to read 4, iclass 6, count 0 2006.218.07:40:10.29#ibcon#read 4, iclass 6, count 0 2006.218.07:40:10.29#ibcon#about to read 5, iclass 6, count 0 2006.218.07:40:10.29#ibcon#read 5, iclass 6, count 0 2006.218.07:40:10.29#ibcon#about to read 6, iclass 6, count 0 2006.218.07:40:10.29#ibcon#read 6, iclass 6, count 0 2006.218.07:40:10.29#ibcon#end of sib2, iclass 6, count 0 2006.218.07:40:10.29#ibcon#*mode == 0, iclass 6, count 0 2006.218.07:40:10.29#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.218.07:40:10.29#ibcon#[26=FRQ=08,852.99\r\n] 2006.218.07:40:10.29#ibcon#*before write, iclass 6, count 0 2006.218.07:40:10.29#ibcon#enter sib2, iclass 6, count 0 2006.218.07:40:10.29#ibcon#flushed, iclass 6, count 0 2006.218.07:40:10.29#ibcon#about to write, iclass 6, count 0 2006.218.07:40:10.29#ibcon#wrote, iclass 6, count 0 2006.218.07:40:10.29#ibcon#about to read 3, iclass 6, count 0 2006.218.07:40:10.33#ibcon#read 3, iclass 6, count 0 2006.218.07:40:10.33#ibcon#about to read 4, iclass 6, count 0 2006.218.07:40:10.33#ibcon#read 4, iclass 6, count 0 2006.218.07:40:10.33#ibcon#about to read 5, iclass 6, count 0 2006.218.07:40:10.33#ibcon#read 5, iclass 6, count 0 2006.218.07:40:10.33#ibcon#about to read 6, iclass 6, count 0 2006.218.07:40:10.33#ibcon#read 6, iclass 6, count 0 2006.218.07:40:10.33#ibcon#end of sib2, iclass 6, count 0 2006.218.07:40:10.33#ibcon#*after write, iclass 6, count 0 2006.218.07:40:10.33#ibcon#*before return 0, iclass 6, count 0 2006.218.07:40:10.33#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.218.07:40:10.33#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.218.07:40:10.33#ibcon#about to clear, iclass 6 cls_cnt 0 2006.218.07:40:10.33#ibcon#cleared, iclass 6 cls_cnt 0 2006.218.07:40:10.33$vc4f8/va=8,7 2006.218.07:40:10.33#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.218.07:40:10.33#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.218.07:40:10.33#ibcon#ireg 11 cls_cnt 2 2006.218.07:40:10.33#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.218.07:40:10.39#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.218.07:40:10.39#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.218.07:40:10.39#ibcon#enter wrdev, iclass 10, count 2 2006.218.07:40:10.39#ibcon#first serial, iclass 10, count 2 2006.218.07:40:10.39#ibcon#enter sib2, iclass 10, count 2 2006.218.07:40:10.39#ibcon#flushed, iclass 10, count 2 2006.218.07:40:10.39#ibcon#about to write, iclass 10, count 2 2006.218.07:40:10.39#ibcon#wrote, iclass 10, count 2 2006.218.07:40:10.39#ibcon#about to read 3, iclass 10, count 2 2006.218.07:40:10.41#ibcon#read 3, iclass 10, count 2 2006.218.07:40:10.41#ibcon#about to read 4, iclass 10, count 2 2006.218.07:40:10.41#ibcon#read 4, iclass 10, count 2 2006.218.07:40:10.41#ibcon#about to read 5, iclass 10, count 2 2006.218.07:40:10.41#ibcon#read 5, iclass 10, count 2 2006.218.07:40:10.41#ibcon#about to read 6, iclass 10, count 2 2006.218.07:40:10.41#ibcon#read 6, iclass 10, count 2 2006.218.07:40:10.41#ibcon#end of sib2, iclass 10, count 2 2006.218.07:40:10.41#ibcon#*mode == 0, iclass 10, count 2 2006.218.07:40:10.41#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.218.07:40:10.41#ibcon#[25=AT08-07\r\n] 2006.218.07:40:10.41#ibcon#*before write, iclass 10, count 2 2006.218.07:40:10.41#ibcon#enter sib2, iclass 10, count 2 2006.218.07:40:10.41#ibcon#flushed, iclass 10, count 2 2006.218.07:40:10.41#ibcon#about to write, iclass 10, count 2 2006.218.07:40:10.41#ibcon#wrote, iclass 10, count 2 2006.218.07:40:10.41#ibcon#about to read 3, iclass 10, count 2 2006.218.07:40:10.45#ibcon#read 3, iclass 10, count 2 2006.218.07:40:10.45#ibcon#about to read 4, iclass 10, count 2 2006.218.07:40:10.45#ibcon#read 4, iclass 10, count 2 2006.218.07:40:10.45#ibcon#about to read 5, iclass 10, count 2 2006.218.07:40:10.45#ibcon#read 5, iclass 10, count 2 2006.218.07:40:10.45#ibcon#about to read 6, iclass 10, count 2 2006.218.07:40:10.45#ibcon#read 6, iclass 10, count 2 2006.218.07:40:10.45#ibcon#end of sib2, iclass 10, count 2 2006.218.07:40:10.45#ibcon#*after write, iclass 10, count 2 2006.218.07:40:10.45#ibcon#*before return 0, iclass 10, count 2 2006.218.07:40:10.45#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.218.07:40:10.45#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.218.07:40:10.45#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.218.07:40:10.45#ibcon#ireg 7 cls_cnt 0 2006.218.07:40:10.45#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.218.07:40:10.53#abcon#<5=/06 4.3 7.4 31.41 721007.4\r\n> 2006.218.07:40:10.55#abcon#{5=INTERFACE CLEAR} 2006.218.07:40:10.57#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.218.07:40:10.57#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.218.07:40:10.57#ibcon#enter wrdev, iclass 10, count 0 2006.218.07:40:10.57#ibcon#first serial, iclass 10, count 0 2006.218.07:40:10.57#ibcon#enter sib2, iclass 10, count 0 2006.218.07:40:10.57#ibcon#flushed, iclass 10, count 0 2006.218.07:40:10.57#ibcon#about to write, iclass 10, count 0 2006.218.07:40:10.57#ibcon#wrote, iclass 10, count 0 2006.218.07:40:10.57#ibcon#about to read 3, iclass 10, count 0 2006.218.07:40:10.59#ibcon#read 3, iclass 10, count 0 2006.218.07:40:10.59#ibcon#about to read 4, iclass 10, count 0 2006.218.07:40:10.59#ibcon#read 4, iclass 10, count 0 2006.218.07:40:10.59#ibcon#about to read 5, iclass 10, count 0 2006.218.07:40:10.59#ibcon#read 5, iclass 10, count 0 2006.218.07:40:10.59#ibcon#about to read 6, iclass 10, count 0 2006.218.07:40:10.59#ibcon#read 6, iclass 10, count 0 2006.218.07:40:10.59#ibcon#end of sib2, iclass 10, count 0 2006.218.07:40:10.59#ibcon#*mode == 0, iclass 10, count 0 2006.218.07:40:10.59#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.218.07:40:10.59#ibcon#[25=USB\r\n] 2006.218.07:40:10.59#ibcon#*before write, iclass 10, count 0 2006.218.07:40:10.59#ibcon#enter sib2, iclass 10, count 0 2006.218.07:40:10.59#ibcon#flushed, iclass 10, count 0 2006.218.07:40:10.59#ibcon#about to write, iclass 10, count 0 2006.218.07:40:10.59#ibcon#wrote, iclass 10, count 0 2006.218.07:40:10.59#ibcon#about to read 3, iclass 10, count 0 2006.218.07:40:10.61#abcon#[5=S1D000X0/0*\r\n] 2006.218.07:40:10.62#ibcon#read 3, iclass 10, count 0 2006.218.07:40:10.62#ibcon#about to read 4, iclass 10, count 0 2006.218.07:40:10.62#ibcon#read 4, iclass 10, count 0 2006.218.07:40:10.62#ibcon#about to read 5, iclass 10, count 0 2006.218.07:40:10.62#ibcon#read 5, iclass 10, count 0 2006.218.07:40:10.62#ibcon#about to read 6, iclass 10, count 0 2006.218.07:40:10.62#ibcon#read 6, iclass 10, count 0 2006.218.07:40:10.62#ibcon#end of sib2, iclass 10, count 0 2006.218.07:40:10.62#ibcon#*after write, iclass 10, count 0 2006.218.07:40:10.62#ibcon#*before return 0, iclass 10, count 0 2006.218.07:40:10.62#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.218.07:40:10.62#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.218.07:40:10.62#ibcon#about to clear, iclass 10 cls_cnt 0 2006.218.07:40:10.62#ibcon#cleared, iclass 10 cls_cnt 0 2006.218.07:40:10.62$vc4f8/vblo=1,632.99 2006.218.07:40:10.62#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.218.07:40:10.62#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.218.07:40:10.62#ibcon#ireg 17 cls_cnt 0 2006.218.07:40:10.62#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.218.07:40:10.62#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.218.07:40:10.62#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.218.07:40:10.62#ibcon#enter wrdev, iclass 16, count 0 2006.218.07:40:10.62#ibcon#first serial, iclass 16, count 0 2006.218.07:40:10.62#ibcon#enter sib2, iclass 16, count 0 2006.218.07:40:10.62#ibcon#flushed, iclass 16, count 0 2006.218.07:40:10.62#ibcon#about to write, iclass 16, count 0 2006.218.07:40:10.62#ibcon#wrote, iclass 16, count 0 2006.218.07:40:10.62#ibcon#about to read 3, iclass 16, count 0 2006.218.07:40:10.64#ibcon#read 3, iclass 16, count 0 2006.218.07:40:10.64#ibcon#about to read 4, iclass 16, count 0 2006.218.07:40:10.64#ibcon#read 4, iclass 16, count 0 2006.218.07:40:10.64#ibcon#about to read 5, iclass 16, count 0 2006.218.07:40:10.64#ibcon#read 5, iclass 16, count 0 2006.218.07:40:10.64#ibcon#about to read 6, iclass 16, count 0 2006.218.07:40:10.64#ibcon#read 6, iclass 16, count 0 2006.218.07:40:10.64#ibcon#end of sib2, iclass 16, count 0 2006.218.07:40:10.64#ibcon#*mode == 0, iclass 16, count 0 2006.218.07:40:10.64#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.218.07:40:10.64#ibcon#[28=FRQ=01,632.99\r\n] 2006.218.07:40:10.64#ibcon#*before write, iclass 16, count 0 2006.218.07:40:10.64#ibcon#enter sib2, iclass 16, count 0 2006.218.07:40:10.64#ibcon#flushed, iclass 16, count 0 2006.218.07:40:10.64#ibcon#about to write, iclass 16, count 0 2006.218.07:40:10.64#ibcon#wrote, iclass 16, count 0 2006.218.07:40:10.64#ibcon#about to read 3, iclass 16, count 0 2006.218.07:40:10.68#ibcon#read 3, iclass 16, count 0 2006.218.07:40:10.68#ibcon#about to read 4, iclass 16, count 0 2006.218.07:40:10.68#ibcon#read 4, iclass 16, count 0 2006.218.07:40:10.68#ibcon#about to read 5, iclass 16, count 0 2006.218.07:40:10.68#ibcon#read 5, iclass 16, count 0 2006.218.07:40:10.68#ibcon#about to read 6, iclass 16, count 0 2006.218.07:40:10.68#ibcon#read 6, iclass 16, count 0 2006.218.07:40:10.68#ibcon#end of sib2, iclass 16, count 0 2006.218.07:40:10.68#ibcon#*after write, iclass 16, count 0 2006.218.07:40:10.68#ibcon#*before return 0, iclass 16, count 0 2006.218.07:40:10.68#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.218.07:40:10.68#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.218.07:40:10.68#ibcon#about to clear, iclass 16 cls_cnt 0 2006.218.07:40:10.68#ibcon#cleared, iclass 16 cls_cnt 0 2006.218.07:40:10.68$vc4f8/vb=1,4 2006.218.07:40:10.68#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.218.07:40:10.68#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.218.07:40:10.68#ibcon#ireg 11 cls_cnt 2 2006.218.07:40:10.68#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.218.07:40:10.68#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.218.07:40:10.68#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.218.07:40:10.68#ibcon#enter wrdev, iclass 18, count 2 2006.218.07:40:10.68#ibcon#first serial, iclass 18, count 2 2006.218.07:40:10.68#ibcon#enter sib2, iclass 18, count 2 2006.218.07:40:10.68#ibcon#flushed, iclass 18, count 2 2006.218.07:40:10.68#ibcon#about to write, iclass 18, count 2 2006.218.07:40:10.68#ibcon#wrote, iclass 18, count 2 2006.218.07:40:10.68#ibcon#about to read 3, iclass 18, count 2 2006.218.07:40:10.70#ibcon#read 3, iclass 18, count 2 2006.218.07:40:10.70#ibcon#about to read 4, iclass 18, count 2 2006.218.07:40:10.70#ibcon#read 4, iclass 18, count 2 2006.218.07:40:10.70#ibcon#about to read 5, iclass 18, count 2 2006.218.07:40:10.70#ibcon#read 5, iclass 18, count 2 2006.218.07:40:10.70#ibcon#about to read 6, iclass 18, count 2 2006.218.07:40:10.70#ibcon#read 6, iclass 18, count 2 2006.218.07:40:10.70#ibcon#end of sib2, iclass 18, count 2 2006.218.07:40:10.70#ibcon#*mode == 0, iclass 18, count 2 2006.218.07:40:10.70#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.218.07:40:10.70#ibcon#[27=AT01-04\r\n] 2006.218.07:40:10.70#ibcon#*before write, iclass 18, count 2 2006.218.07:40:10.70#ibcon#enter sib2, iclass 18, count 2 2006.218.07:40:10.70#ibcon#flushed, iclass 18, count 2 2006.218.07:40:10.70#ibcon#about to write, iclass 18, count 2 2006.218.07:40:10.70#ibcon#wrote, iclass 18, count 2 2006.218.07:40:10.70#ibcon#about to read 3, iclass 18, count 2 2006.218.07:40:10.73#ibcon#read 3, iclass 18, count 2 2006.218.07:40:10.73#ibcon#about to read 4, iclass 18, count 2 2006.218.07:40:10.73#ibcon#read 4, iclass 18, count 2 2006.218.07:40:10.73#ibcon#about to read 5, iclass 18, count 2 2006.218.07:40:10.73#ibcon#read 5, iclass 18, count 2 2006.218.07:40:10.73#ibcon#about to read 6, iclass 18, count 2 2006.218.07:40:10.73#ibcon#read 6, iclass 18, count 2 2006.218.07:40:10.73#ibcon#end of sib2, iclass 18, count 2 2006.218.07:40:10.73#ibcon#*after write, iclass 18, count 2 2006.218.07:40:10.73#ibcon#*before return 0, iclass 18, count 2 2006.218.07:40:10.73#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.218.07:40:10.73#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.218.07:40:10.73#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.218.07:40:10.73#ibcon#ireg 7 cls_cnt 0 2006.218.07:40:10.73#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.218.07:40:10.85#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.218.07:40:10.85#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.218.07:40:10.85#ibcon#enter wrdev, iclass 18, count 0 2006.218.07:40:10.85#ibcon#first serial, iclass 18, count 0 2006.218.07:40:10.85#ibcon#enter sib2, iclass 18, count 0 2006.218.07:40:10.85#ibcon#flushed, iclass 18, count 0 2006.218.07:40:10.85#ibcon#about to write, iclass 18, count 0 2006.218.07:40:10.85#ibcon#wrote, iclass 18, count 0 2006.218.07:40:10.85#ibcon#about to read 3, iclass 18, count 0 2006.218.07:40:10.87#ibcon#read 3, iclass 18, count 0 2006.218.07:40:10.87#ibcon#about to read 4, iclass 18, count 0 2006.218.07:40:10.87#ibcon#read 4, iclass 18, count 0 2006.218.07:40:10.87#ibcon#about to read 5, iclass 18, count 0 2006.218.07:40:10.87#ibcon#read 5, iclass 18, count 0 2006.218.07:40:10.87#ibcon#about to read 6, iclass 18, count 0 2006.218.07:40:10.87#ibcon#read 6, iclass 18, count 0 2006.218.07:40:10.87#ibcon#end of sib2, iclass 18, count 0 2006.218.07:40:10.87#ibcon#*mode == 0, iclass 18, count 0 2006.218.07:40:10.87#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.218.07:40:10.87#ibcon#[27=USB\r\n] 2006.218.07:40:10.87#ibcon#*before write, iclass 18, count 0 2006.218.07:40:10.87#ibcon#enter sib2, iclass 18, count 0 2006.218.07:40:10.87#ibcon#flushed, iclass 18, count 0 2006.218.07:40:10.87#ibcon#about to write, iclass 18, count 0 2006.218.07:40:10.87#ibcon#wrote, iclass 18, count 0 2006.218.07:40:10.87#ibcon#about to read 3, iclass 18, count 0 2006.218.07:40:10.90#ibcon#read 3, iclass 18, count 0 2006.218.07:40:10.90#ibcon#about to read 4, iclass 18, count 0 2006.218.07:40:10.90#ibcon#read 4, iclass 18, count 0 2006.218.07:40:10.90#ibcon#about to read 5, iclass 18, count 0 2006.218.07:40:10.90#ibcon#read 5, iclass 18, count 0 2006.218.07:40:10.90#ibcon#about to read 6, iclass 18, count 0 2006.218.07:40:10.90#ibcon#read 6, iclass 18, count 0 2006.218.07:40:10.90#ibcon#end of sib2, iclass 18, count 0 2006.218.07:40:10.90#ibcon#*after write, iclass 18, count 0 2006.218.07:40:10.90#ibcon#*before return 0, iclass 18, count 0 2006.218.07:40:10.90#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.218.07:40:10.90#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.218.07:40:10.90#ibcon#about to clear, iclass 18 cls_cnt 0 2006.218.07:40:10.90#ibcon#cleared, iclass 18 cls_cnt 0 2006.218.07:40:10.90$vc4f8/vblo=2,640.99 2006.218.07:40:10.90#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.218.07:40:10.90#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.218.07:40:10.90#ibcon#ireg 17 cls_cnt 0 2006.218.07:40:10.90#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.218.07:40:10.90#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.218.07:40:10.90#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.218.07:40:10.90#ibcon#enter wrdev, iclass 20, count 0 2006.218.07:40:10.90#ibcon#first serial, iclass 20, count 0 2006.218.07:40:10.90#ibcon#enter sib2, iclass 20, count 0 2006.218.07:40:10.90#ibcon#flushed, iclass 20, count 0 2006.218.07:40:10.90#ibcon#about to write, iclass 20, count 0 2006.218.07:40:10.90#ibcon#wrote, iclass 20, count 0 2006.218.07:40:10.90#ibcon#about to read 3, iclass 20, count 0 2006.218.07:40:10.92#ibcon#read 3, iclass 20, count 0 2006.218.07:40:10.92#ibcon#about to read 4, iclass 20, count 0 2006.218.07:40:10.92#ibcon#read 4, iclass 20, count 0 2006.218.07:40:10.92#ibcon#about to read 5, iclass 20, count 0 2006.218.07:40:10.92#ibcon#read 5, iclass 20, count 0 2006.218.07:40:10.92#ibcon#about to read 6, iclass 20, count 0 2006.218.07:40:10.92#ibcon#read 6, iclass 20, count 0 2006.218.07:40:10.92#ibcon#end of sib2, iclass 20, count 0 2006.218.07:40:10.92#ibcon#*mode == 0, iclass 20, count 0 2006.218.07:40:10.92#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.218.07:40:10.92#ibcon#[28=FRQ=02,640.99\r\n] 2006.218.07:40:10.92#ibcon#*before write, iclass 20, count 0 2006.218.07:40:10.92#ibcon#enter sib2, iclass 20, count 0 2006.218.07:40:10.92#ibcon#flushed, iclass 20, count 0 2006.218.07:40:10.92#ibcon#about to write, iclass 20, count 0 2006.218.07:40:10.92#ibcon#wrote, iclass 20, count 0 2006.218.07:40:10.92#ibcon#about to read 3, iclass 20, count 0 2006.218.07:40:10.96#ibcon#read 3, iclass 20, count 0 2006.218.07:40:10.96#ibcon#about to read 4, iclass 20, count 0 2006.218.07:40:10.96#ibcon#read 4, iclass 20, count 0 2006.218.07:40:10.96#ibcon#about to read 5, iclass 20, count 0 2006.218.07:40:10.96#ibcon#read 5, iclass 20, count 0 2006.218.07:40:10.96#ibcon#about to read 6, iclass 20, count 0 2006.218.07:40:10.96#ibcon#read 6, iclass 20, count 0 2006.218.07:40:10.96#ibcon#end of sib2, iclass 20, count 0 2006.218.07:40:10.96#ibcon#*after write, iclass 20, count 0 2006.218.07:40:10.96#ibcon#*before return 0, iclass 20, count 0 2006.218.07:40:10.96#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.218.07:40:10.96#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.218.07:40:10.96#ibcon#about to clear, iclass 20 cls_cnt 0 2006.218.07:40:10.96#ibcon#cleared, iclass 20 cls_cnt 0 2006.218.07:40:10.96$vc4f8/vb=2,4 2006.218.07:40:10.96#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.218.07:40:10.96#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.218.07:40:10.96#ibcon#ireg 11 cls_cnt 2 2006.218.07:40:10.96#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.218.07:40:11.02#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.218.07:40:11.02#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.218.07:40:11.02#ibcon#enter wrdev, iclass 22, count 2 2006.218.07:40:11.02#ibcon#first serial, iclass 22, count 2 2006.218.07:40:11.02#ibcon#enter sib2, iclass 22, count 2 2006.218.07:40:11.02#ibcon#flushed, iclass 22, count 2 2006.218.07:40:11.02#ibcon#about to write, iclass 22, count 2 2006.218.07:40:11.02#ibcon#wrote, iclass 22, count 2 2006.218.07:40:11.02#ibcon#about to read 3, iclass 22, count 2 2006.218.07:40:11.04#ibcon#read 3, iclass 22, count 2 2006.218.07:40:11.04#ibcon#about to read 4, iclass 22, count 2 2006.218.07:40:11.04#ibcon#read 4, iclass 22, count 2 2006.218.07:40:11.04#ibcon#about to read 5, iclass 22, count 2 2006.218.07:40:11.04#ibcon#read 5, iclass 22, count 2 2006.218.07:40:11.04#ibcon#about to read 6, iclass 22, count 2 2006.218.07:40:11.04#ibcon#read 6, iclass 22, count 2 2006.218.07:40:11.04#ibcon#end of sib2, iclass 22, count 2 2006.218.07:40:11.04#ibcon#*mode == 0, iclass 22, count 2 2006.218.07:40:11.04#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.218.07:40:11.04#ibcon#[27=AT02-04\r\n] 2006.218.07:40:11.04#ibcon#*before write, iclass 22, count 2 2006.218.07:40:11.04#ibcon#enter sib2, iclass 22, count 2 2006.218.07:40:11.04#ibcon#flushed, iclass 22, count 2 2006.218.07:40:11.04#ibcon#about to write, iclass 22, count 2 2006.218.07:40:11.04#ibcon#wrote, iclass 22, count 2 2006.218.07:40:11.04#ibcon#about to read 3, iclass 22, count 2 2006.218.07:40:11.07#ibcon#read 3, iclass 22, count 2 2006.218.07:40:11.07#ibcon#about to read 4, iclass 22, count 2 2006.218.07:40:11.07#ibcon#read 4, iclass 22, count 2 2006.218.07:40:11.07#ibcon#about to read 5, iclass 22, count 2 2006.218.07:40:11.07#ibcon#read 5, iclass 22, count 2 2006.218.07:40:11.07#ibcon#about to read 6, iclass 22, count 2 2006.218.07:40:11.07#ibcon#read 6, iclass 22, count 2 2006.218.07:40:11.07#ibcon#end of sib2, iclass 22, count 2 2006.218.07:40:11.07#ibcon#*after write, iclass 22, count 2 2006.218.07:40:11.07#ibcon#*before return 0, iclass 22, count 2 2006.218.07:40:11.07#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.218.07:40:11.07#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.218.07:40:11.07#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.218.07:40:11.07#ibcon#ireg 7 cls_cnt 0 2006.218.07:40:11.07#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.218.07:40:11.19#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.218.07:40:11.19#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.218.07:40:11.19#ibcon#enter wrdev, iclass 22, count 0 2006.218.07:40:11.19#ibcon#first serial, iclass 22, count 0 2006.218.07:40:11.19#ibcon#enter sib2, iclass 22, count 0 2006.218.07:40:11.19#ibcon#flushed, iclass 22, count 0 2006.218.07:40:11.19#ibcon#about to write, iclass 22, count 0 2006.218.07:40:11.19#ibcon#wrote, iclass 22, count 0 2006.218.07:40:11.19#ibcon#about to read 3, iclass 22, count 0 2006.218.07:40:11.21#ibcon#read 3, iclass 22, count 0 2006.218.07:40:11.21#ibcon#about to read 4, iclass 22, count 0 2006.218.07:40:11.21#ibcon#read 4, iclass 22, count 0 2006.218.07:40:11.21#ibcon#about to read 5, iclass 22, count 0 2006.218.07:40:11.21#ibcon#read 5, iclass 22, count 0 2006.218.07:40:11.21#ibcon#about to read 6, iclass 22, count 0 2006.218.07:40:11.21#ibcon#read 6, iclass 22, count 0 2006.218.07:40:11.21#ibcon#end of sib2, iclass 22, count 0 2006.218.07:40:11.21#ibcon#*mode == 0, iclass 22, count 0 2006.218.07:40:11.21#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.218.07:40:11.21#ibcon#[27=USB\r\n] 2006.218.07:40:11.21#ibcon#*before write, iclass 22, count 0 2006.218.07:40:11.21#ibcon#enter sib2, iclass 22, count 0 2006.218.07:40:11.21#ibcon#flushed, iclass 22, count 0 2006.218.07:40:11.21#ibcon#about to write, iclass 22, count 0 2006.218.07:40:11.21#ibcon#wrote, iclass 22, count 0 2006.218.07:40:11.21#ibcon#about to read 3, iclass 22, count 0 2006.218.07:40:11.24#ibcon#read 3, iclass 22, count 0 2006.218.07:40:11.24#ibcon#about to read 4, iclass 22, count 0 2006.218.07:40:11.24#ibcon#read 4, iclass 22, count 0 2006.218.07:40:11.24#ibcon#about to read 5, iclass 22, count 0 2006.218.07:40:11.24#ibcon#read 5, iclass 22, count 0 2006.218.07:40:11.24#ibcon#about to read 6, iclass 22, count 0 2006.218.07:40:11.24#ibcon#read 6, iclass 22, count 0 2006.218.07:40:11.24#ibcon#end of sib2, iclass 22, count 0 2006.218.07:40:11.24#ibcon#*after write, iclass 22, count 0 2006.218.07:40:11.24#ibcon#*before return 0, iclass 22, count 0 2006.218.07:40:11.24#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.218.07:40:11.24#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.218.07:40:11.24#ibcon#about to clear, iclass 22 cls_cnt 0 2006.218.07:40:11.24#ibcon#cleared, iclass 22 cls_cnt 0 2006.218.07:40:11.24$vc4f8/vblo=3,656.99 2006.218.07:40:11.24#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.218.07:40:11.24#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.218.07:40:11.24#ibcon#ireg 17 cls_cnt 0 2006.218.07:40:11.24#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.218.07:40:11.24#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.218.07:40:11.24#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.218.07:40:11.24#ibcon#enter wrdev, iclass 24, count 0 2006.218.07:40:11.24#ibcon#first serial, iclass 24, count 0 2006.218.07:40:11.24#ibcon#enter sib2, iclass 24, count 0 2006.218.07:40:11.24#ibcon#flushed, iclass 24, count 0 2006.218.07:40:11.24#ibcon#about to write, iclass 24, count 0 2006.218.07:40:11.24#ibcon#wrote, iclass 24, count 0 2006.218.07:40:11.24#ibcon#about to read 3, iclass 24, count 0 2006.218.07:40:11.26#ibcon#read 3, iclass 24, count 0 2006.218.07:40:11.26#ibcon#about to read 4, iclass 24, count 0 2006.218.07:40:11.26#ibcon#read 4, iclass 24, count 0 2006.218.07:40:11.26#ibcon#about to read 5, iclass 24, count 0 2006.218.07:40:11.26#ibcon#read 5, iclass 24, count 0 2006.218.07:40:11.26#ibcon#about to read 6, iclass 24, count 0 2006.218.07:40:11.26#ibcon#read 6, iclass 24, count 0 2006.218.07:40:11.26#ibcon#end of sib2, iclass 24, count 0 2006.218.07:40:11.26#ibcon#*mode == 0, iclass 24, count 0 2006.218.07:40:11.26#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.218.07:40:11.26#ibcon#[28=FRQ=03,656.99\r\n] 2006.218.07:40:11.26#ibcon#*before write, iclass 24, count 0 2006.218.07:40:11.26#ibcon#enter sib2, iclass 24, count 0 2006.218.07:40:11.26#ibcon#flushed, iclass 24, count 0 2006.218.07:40:11.26#ibcon#about to write, iclass 24, count 0 2006.218.07:40:11.26#ibcon#wrote, iclass 24, count 0 2006.218.07:40:11.26#ibcon#about to read 3, iclass 24, count 0 2006.218.07:40:11.30#ibcon#read 3, iclass 24, count 0 2006.218.07:40:11.30#ibcon#about to read 4, iclass 24, count 0 2006.218.07:40:11.30#ibcon#read 4, iclass 24, count 0 2006.218.07:40:11.30#ibcon#about to read 5, iclass 24, count 0 2006.218.07:40:11.30#ibcon#read 5, iclass 24, count 0 2006.218.07:40:11.30#ibcon#about to read 6, iclass 24, count 0 2006.218.07:40:11.30#ibcon#read 6, iclass 24, count 0 2006.218.07:40:11.30#ibcon#end of sib2, iclass 24, count 0 2006.218.07:40:11.30#ibcon#*after write, iclass 24, count 0 2006.218.07:40:11.30#ibcon#*before return 0, iclass 24, count 0 2006.218.07:40:11.30#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.218.07:40:11.30#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.218.07:40:11.30#ibcon#about to clear, iclass 24 cls_cnt 0 2006.218.07:40:11.30#ibcon#cleared, iclass 24 cls_cnt 0 2006.218.07:40:11.30$vc4f8/vb=3,4 2006.218.07:40:11.30#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.218.07:40:11.30#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.218.07:40:11.30#ibcon#ireg 11 cls_cnt 2 2006.218.07:40:11.30#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.218.07:40:11.36#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.218.07:40:11.36#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.218.07:40:11.36#ibcon#enter wrdev, iclass 26, count 2 2006.218.07:40:11.36#ibcon#first serial, iclass 26, count 2 2006.218.07:40:11.36#ibcon#enter sib2, iclass 26, count 2 2006.218.07:40:11.36#ibcon#flushed, iclass 26, count 2 2006.218.07:40:11.36#ibcon#about to write, iclass 26, count 2 2006.218.07:40:11.36#ibcon#wrote, iclass 26, count 2 2006.218.07:40:11.36#ibcon#about to read 3, iclass 26, count 2 2006.218.07:40:11.38#ibcon#read 3, iclass 26, count 2 2006.218.07:40:11.38#ibcon#about to read 4, iclass 26, count 2 2006.218.07:40:11.38#ibcon#read 4, iclass 26, count 2 2006.218.07:40:11.38#ibcon#about to read 5, iclass 26, count 2 2006.218.07:40:11.38#ibcon#read 5, iclass 26, count 2 2006.218.07:40:11.38#ibcon#about to read 6, iclass 26, count 2 2006.218.07:40:11.38#ibcon#read 6, iclass 26, count 2 2006.218.07:40:11.38#ibcon#end of sib2, iclass 26, count 2 2006.218.07:40:11.38#ibcon#*mode == 0, iclass 26, count 2 2006.218.07:40:11.38#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.218.07:40:11.38#ibcon#[27=AT03-04\r\n] 2006.218.07:40:11.38#ibcon#*before write, iclass 26, count 2 2006.218.07:40:11.38#ibcon#enter sib2, iclass 26, count 2 2006.218.07:40:11.38#ibcon#flushed, iclass 26, count 2 2006.218.07:40:11.38#ibcon#about to write, iclass 26, count 2 2006.218.07:40:11.38#ibcon#wrote, iclass 26, count 2 2006.218.07:40:11.38#ibcon#about to read 3, iclass 26, count 2 2006.218.07:40:11.41#ibcon#read 3, iclass 26, count 2 2006.218.07:40:11.41#ibcon#about to read 4, iclass 26, count 2 2006.218.07:40:11.41#ibcon#read 4, iclass 26, count 2 2006.218.07:40:11.41#ibcon#about to read 5, iclass 26, count 2 2006.218.07:40:11.41#ibcon#read 5, iclass 26, count 2 2006.218.07:40:11.41#ibcon#about to read 6, iclass 26, count 2 2006.218.07:40:11.41#ibcon#read 6, iclass 26, count 2 2006.218.07:40:11.41#ibcon#end of sib2, iclass 26, count 2 2006.218.07:40:11.41#ibcon#*after write, iclass 26, count 2 2006.218.07:40:11.41#ibcon#*before return 0, iclass 26, count 2 2006.218.07:40:11.41#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.218.07:40:11.41#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.218.07:40:11.41#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.218.07:40:11.41#ibcon#ireg 7 cls_cnt 0 2006.218.07:40:11.41#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.218.07:40:11.53#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.218.07:40:11.53#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.218.07:40:11.53#ibcon#enter wrdev, iclass 26, count 0 2006.218.07:40:11.53#ibcon#first serial, iclass 26, count 0 2006.218.07:40:11.53#ibcon#enter sib2, iclass 26, count 0 2006.218.07:40:11.53#ibcon#flushed, iclass 26, count 0 2006.218.07:40:11.53#ibcon#about to write, iclass 26, count 0 2006.218.07:40:11.53#ibcon#wrote, iclass 26, count 0 2006.218.07:40:11.53#ibcon#about to read 3, iclass 26, count 0 2006.218.07:40:11.55#ibcon#read 3, iclass 26, count 0 2006.218.07:40:11.55#ibcon#about to read 4, iclass 26, count 0 2006.218.07:40:11.55#ibcon#read 4, iclass 26, count 0 2006.218.07:40:11.55#ibcon#about to read 5, iclass 26, count 0 2006.218.07:40:11.55#ibcon#read 5, iclass 26, count 0 2006.218.07:40:11.55#ibcon#about to read 6, iclass 26, count 0 2006.218.07:40:11.55#ibcon#read 6, iclass 26, count 0 2006.218.07:40:11.55#ibcon#end of sib2, iclass 26, count 0 2006.218.07:40:11.55#ibcon#*mode == 0, iclass 26, count 0 2006.218.07:40:11.55#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.218.07:40:11.55#ibcon#[27=USB\r\n] 2006.218.07:40:11.55#ibcon#*before write, iclass 26, count 0 2006.218.07:40:11.55#ibcon#enter sib2, iclass 26, count 0 2006.218.07:40:11.55#ibcon#flushed, iclass 26, count 0 2006.218.07:40:11.55#ibcon#about to write, iclass 26, count 0 2006.218.07:40:11.55#ibcon#wrote, iclass 26, count 0 2006.218.07:40:11.55#ibcon#about to read 3, iclass 26, count 0 2006.218.07:40:11.58#ibcon#read 3, iclass 26, count 0 2006.218.07:40:11.58#ibcon#about to read 4, iclass 26, count 0 2006.218.07:40:11.58#ibcon#read 4, iclass 26, count 0 2006.218.07:40:11.58#ibcon#about to read 5, iclass 26, count 0 2006.218.07:40:11.58#ibcon#read 5, iclass 26, count 0 2006.218.07:40:11.58#ibcon#about to read 6, iclass 26, count 0 2006.218.07:40:11.58#ibcon#read 6, iclass 26, count 0 2006.218.07:40:11.58#ibcon#end of sib2, iclass 26, count 0 2006.218.07:40:11.58#ibcon#*after write, iclass 26, count 0 2006.218.07:40:11.58#ibcon#*before return 0, iclass 26, count 0 2006.218.07:40:11.58#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.218.07:40:11.58#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.218.07:40:11.58#ibcon#about to clear, iclass 26 cls_cnt 0 2006.218.07:40:11.58#ibcon#cleared, iclass 26 cls_cnt 0 2006.218.07:40:11.58$vc4f8/vblo=4,712.99 2006.218.07:40:11.58#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.218.07:40:11.58#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.218.07:40:11.58#ibcon#ireg 17 cls_cnt 0 2006.218.07:40:11.58#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.218.07:40:11.58#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.218.07:40:11.58#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.218.07:40:11.58#ibcon#enter wrdev, iclass 28, count 0 2006.218.07:40:11.58#ibcon#first serial, iclass 28, count 0 2006.218.07:40:11.58#ibcon#enter sib2, iclass 28, count 0 2006.218.07:40:11.58#ibcon#flushed, iclass 28, count 0 2006.218.07:40:11.58#ibcon#about to write, iclass 28, count 0 2006.218.07:40:11.58#ibcon#wrote, iclass 28, count 0 2006.218.07:40:11.58#ibcon#about to read 3, iclass 28, count 0 2006.218.07:40:11.60#ibcon#read 3, iclass 28, count 0 2006.218.07:40:11.60#ibcon#about to read 4, iclass 28, count 0 2006.218.07:40:11.60#ibcon#read 4, iclass 28, count 0 2006.218.07:40:11.60#ibcon#about to read 5, iclass 28, count 0 2006.218.07:40:11.60#ibcon#read 5, iclass 28, count 0 2006.218.07:40:11.60#ibcon#about to read 6, iclass 28, count 0 2006.218.07:40:11.60#ibcon#read 6, iclass 28, count 0 2006.218.07:40:11.60#ibcon#end of sib2, iclass 28, count 0 2006.218.07:40:11.60#ibcon#*mode == 0, iclass 28, count 0 2006.218.07:40:11.60#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.218.07:40:11.60#ibcon#[28=FRQ=04,712.99\r\n] 2006.218.07:40:11.60#ibcon#*before write, iclass 28, count 0 2006.218.07:40:11.60#ibcon#enter sib2, iclass 28, count 0 2006.218.07:40:11.60#ibcon#flushed, iclass 28, count 0 2006.218.07:40:11.60#ibcon#about to write, iclass 28, count 0 2006.218.07:40:11.60#ibcon#wrote, iclass 28, count 0 2006.218.07:40:11.60#ibcon#about to read 3, iclass 28, count 0 2006.218.07:40:11.64#ibcon#read 3, iclass 28, count 0 2006.218.07:40:11.64#ibcon#about to read 4, iclass 28, count 0 2006.218.07:40:11.64#ibcon#read 4, iclass 28, count 0 2006.218.07:40:11.64#ibcon#about to read 5, iclass 28, count 0 2006.218.07:40:11.64#ibcon#read 5, iclass 28, count 0 2006.218.07:40:11.64#ibcon#about to read 6, iclass 28, count 0 2006.218.07:40:11.64#ibcon#read 6, iclass 28, count 0 2006.218.07:40:11.64#ibcon#end of sib2, iclass 28, count 0 2006.218.07:40:11.64#ibcon#*after write, iclass 28, count 0 2006.218.07:40:11.64#ibcon#*before return 0, iclass 28, count 0 2006.218.07:40:11.64#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.218.07:40:11.64#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.218.07:40:11.64#ibcon#about to clear, iclass 28 cls_cnt 0 2006.218.07:40:11.64#ibcon#cleared, iclass 28 cls_cnt 0 2006.218.07:40:11.64$vc4f8/vb=4,4 2006.218.07:40:11.64#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.218.07:40:11.64#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.218.07:40:11.64#ibcon#ireg 11 cls_cnt 2 2006.218.07:40:11.64#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.218.07:40:11.70#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.218.07:40:11.70#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.218.07:40:11.70#ibcon#enter wrdev, iclass 30, count 2 2006.218.07:40:11.70#ibcon#first serial, iclass 30, count 2 2006.218.07:40:11.70#ibcon#enter sib2, iclass 30, count 2 2006.218.07:40:11.70#ibcon#flushed, iclass 30, count 2 2006.218.07:40:11.70#ibcon#about to write, iclass 30, count 2 2006.218.07:40:11.70#ibcon#wrote, iclass 30, count 2 2006.218.07:40:11.70#ibcon#about to read 3, iclass 30, count 2 2006.218.07:40:11.72#ibcon#read 3, iclass 30, count 2 2006.218.07:40:11.72#ibcon#about to read 4, iclass 30, count 2 2006.218.07:40:11.72#ibcon#read 4, iclass 30, count 2 2006.218.07:40:11.72#ibcon#about to read 5, iclass 30, count 2 2006.218.07:40:11.72#ibcon#read 5, iclass 30, count 2 2006.218.07:40:11.72#ibcon#about to read 6, iclass 30, count 2 2006.218.07:40:11.72#ibcon#read 6, iclass 30, count 2 2006.218.07:40:11.72#ibcon#end of sib2, iclass 30, count 2 2006.218.07:40:11.72#ibcon#*mode == 0, iclass 30, count 2 2006.218.07:40:11.72#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.218.07:40:11.72#ibcon#[27=AT04-04\r\n] 2006.218.07:40:11.72#ibcon#*before write, iclass 30, count 2 2006.218.07:40:11.72#ibcon#enter sib2, iclass 30, count 2 2006.218.07:40:11.72#ibcon#flushed, iclass 30, count 2 2006.218.07:40:11.72#ibcon#about to write, iclass 30, count 2 2006.218.07:40:11.72#ibcon#wrote, iclass 30, count 2 2006.218.07:40:11.72#ibcon#about to read 3, iclass 30, count 2 2006.218.07:40:11.75#ibcon#read 3, iclass 30, count 2 2006.218.07:40:11.75#ibcon#about to read 4, iclass 30, count 2 2006.218.07:40:11.75#ibcon#read 4, iclass 30, count 2 2006.218.07:40:11.75#ibcon#about to read 5, iclass 30, count 2 2006.218.07:40:11.75#ibcon#read 5, iclass 30, count 2 2006.218.07:40:11.75#ibcon#about to read 6, iclass 30, count 2 2006.218.07:40:11.75#ibcon#read 6, iclass 30, count 2 2006.218.07:40:11.75#ibcon#end of sib2, iclass 30, count 2 2006.218.07:40:11.75#ibcon#*after write, iclass 30, count 2 2006.218.07:40:11.75#ibcon#*before return 0, iclass 30, count 2 2006.218.07:40:11.75#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.218.07:40:11.75#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.218.07:40:11.75#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.218.07:40:11.75#ibcon#ireg 7 cls_cnt 0 2006.218.07:40:11.75#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.218.07:40:11.87#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.218.07:40:11.87#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.218.07:40:11.87#ibcon#enter wrdev, iclass 30, count 0 2006.218.07:40:11.87#ibcon#first serial, iclass 30, count 0 2006.218.07:40:11.87#ibcon#enter sib2, iclass 30, count 0 2006.218.07:40:11.87#ibcon#flushed, iclass 30, count 0 2006.218.07:40:11.87#ibcon#about to write, iclass 30, count 0 2006.218.07:40:11.87#ibcon#wrote, iclass 30, count 0 2006.218.07:40:11.87#ibcon#about to read 3, iclass 30, count 0 2006.218.07:40:11.89#ibcon#read 3, iclass 30, count 0 2006.218.07:40:11.89#ibcon#about to read 4, iclass 30, count 0 2006.218.07:40:11.89#ibcon#read 4, iclass 30, count 0 2006.218.07:40:11.89#ibcon#about to read 5, iclass 30, count 0 2006.218.07:40:11.89#ibcon#read 5, iclass 30, count 0 2006.218.07:40:11.89#ibcon#about to read 6, iclass 30, count 0 2006.218.07:40:11.89#ibcon#read 6, iclass 30, count 0 2006.218.07:40:11.89#ibcon#end of sib2, iclass 30, count 0 2006.218.07:40:11.89#ibcon#*mode == 0, iclass 30, count 0 2006.218.07:40:11.89#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.218.07:40:11.89#ibcon#[27=USB\r\n] 2006.218.07:40:11.89#ibcon#*before write, iclass 30, count 0 2006.218.07:40:11.89#ibcon#enter sib2, iclass 30, count 0 2006.218.07:40:11.89#ibcon#flushed, iclass 30, count 0 2006.218.07:40:11.89#ibcon#about to write, iclass 30, count 0 2006.218.07:40:11.89#ibcon#wrote, iclass 30, count 0 2006.218.07:40:11.89#ibcon#about to read 3, iclass 30, count 0 2006.218.07:40:11.92#ibcon#read 3, iclass 30, count 0 2006.218.07:40:11.92#ibcon#about to read 4, iclass 30, count 0 2006.218.07:40:11.92#ibcon#read 4, iclass 30, count 0 2006.218.07:40:11.92#ibcon#about to read 5, iclass 30, count 0 2006.218.07:40:11.92#ibcon#read 5, iclass 30, count 0 2006.218.07:40:11.92#ibcon#about to read 6, iclass 30, count 0 2006.218.07:40:11.92#ibcon#read 6, iclass 30, count 0 2006.218.07:40:11.92#ibcon#end of sib2, iclass 30, count 0 2006.218.07:40:11.92#ibcon#*after write, iclass 30, count 0 2006.218.07:40:11.92#ibcon#*before return 0, iclass 30, count 0 2006.218.07:40:11.92#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.218.07:40:11.92#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.218.07:40:11.92#ibcon#about to clear, iclass 30 cls_cnt 0 2006.218.07:40:11.92#ibcon#cleared, iclass 30 cls_cnt 0 2006.218.07:40:11.92$vc4f8/vblo=5,744.99 2006.218.07:40:11.92#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.218.07:40:11.92#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.218.07:40:11.92#ibcon#ireg 17 cls_cnt 0 2006.218.07:40:11.92#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.218.07:40:11.92#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.218.07:40:11.92#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.218.07:40:11.92#ibcon#enter wrdev, iclass 32, count 0 2006.218.07:40:11.92#ibcon#first serial, iclass 32, count 0 2006.218.07:40:11.92#ibcon#enter sib2, iclass 32, count 0 2006.218.07:40:11.92#ibcon#flushed, iclass 32, count 0 2006.218.07:40:11.92#ibcon#about to write, iclass 32, count 0 2006.218.07:40:11.92#ibcon#wrote, iclass 32, count 0 2006.218.07:40:11.92#ibcon#about to read 3, iclass 32, count 0 2006.218.07:40:11.94#ibcon#read 3, iclass 32, count 0 2006.218.07:40:11.94#ibcon#about to read 4, iclass 32, count 0 2006.218.07:40:11.94#ibcon#read 4, iclass 32, count 0 2006.218.07:40:11.94#ibcon#about to read 5, iclass 32, count 0 2006.218.07:40:11.94#ibcon#read 5, iclass 32, count 0 2006.218.07:40:11.94#ibcon#about to read 6, iclass 32, count 0 2006.218.07:40:11.94#ibcon#read 6, iclass 32, count 0 2006.218.07:40:11.94#ibcon#end of sib2, iclass 32, count 0 2006.218.07:40:11.94#ibcon#*mode == 0, iclass 32, count 0 2006.218.07:40:11.94#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.218.07:40:11.94#ibcon#[28=FRQ=05,744.99\r\n] 2006.218.07:40:11.94#ibcon#*before write, iclass 32, count 0 2006.218.07:40:11.94#ibcon#enter sib2, iclass 32, count 0 2006.218.07:40:11.94#ibcon#flushed, iclass 32, count 0 2006.218.07:40:11.94#ibcon#about to write, iclass 32, count 0 2006.218.07:40:11.94#ibcon#wrote, iclass 32, count 0 2006.218.07:40:11.94#ibcon#about to read 3, iclass 32, count 0 2006.218.07:40:11.98#ibcon#read 3, iclass 32, count 0 2006.218.07:40:11.98#ibcon#about to read 4, iclass 32, count 0 2006.218.07:40:11.98#ibcon#read 4, iclass 32, count 0 2006.218.07:40:11.98#ibcon#about to read 5, iclass 32, count 0 2006.218.07:40:11.98#ibcon#read 5, iclass 32, count 0 2006.218.07:40:11.98#ibcon#about to read 6, iclass 32, count 0 2006.218.07:40:11.98#ibcon#read 6, iclass 32, count 0 2006.218.07:40:11.98#ibcon#end of sib2, iclass 32, count 0 2006.218.07:40:11.98#ibcon#*after write, iclass 32, count 0 2006.218.07:40:11.98#ibcon#*before return 0, iclass 32, count 0 2006.218.07:40:11.98#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.218.07:40:11.98#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.218.07:40:11.98#ibcon#about to clear, iclass 32 cls_cnt 0 2006.218.07:40:11.98#ibcon#cleared, iclass 32 cls_cnt 0 2006.218.07:40:11.98$vc4f8/vb=5,4 2006.218.07:40:11.98#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.218.07:40:11.98#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.218.07:40:11.98#ibcon#ireg 11 cls_cnt 2 2006.218.07:40:11.98#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.218.07:40:12.04#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.218.07:40:12.04#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.218.07:40:12.04#ibcon#enter wrdev, iclass 34, count 2 2006.218.07:40:12.04#ibcon#first serial, iclass 34, count 2 2006.218.07:40:12.04#ibcon#enter sib2, iclass 34, count 2 2006.218.07:40:12.04#ibcon#flushed, iclass 34, count 2 2006.218.07:40:12.04#ibcon#about to write, iclass 34, count 2 2006.218.07:40:12.04#ibcon#wrote, iclass 34, count 2 2006.218.07:40:12.04#ibcon#about to read 3, iclass 34, count 2 2006.218.07:40:12.06#ibcon#read 3, iclass 34, count 2 2006.218.07:40:12.06#ibcon#about to read 4, iclass 34, count 2 2006.218.07:40:12.06#ibcon#read 4, iclass 34, count 2 2006.218.07:40:12.06#ibcon#about to read 5, iclass 34, count 2 2006.218.07:40:12.06#ibcon#read 5, iclass 34, count 2 2006.218.07:40:12.06#ibcon#about to read 6, iclass 34, count 2 2006.218.07:40:12.06#ibcon#read 6, iclass 34, count 2 2006.218.07:40:12.06#ibcon#end of sib2, iclass 34, count 2 2006.218.07:40:12.06#ibcon#*mode == 0, iclass 34, count 2 2006.218.07:40:12.07#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.218.07:40:12.07#ibcon#[27=AT05-04\r\n] 2006.218.07:40:12.07#ibcon#*before write, iclass 34, count 2 2006.218.07:40:12.07#ibcon#enter sib2, iclass 34, count 2 2006.218.07:40:12.07#ibcon#flushed, iclass 34, count 2 2006.218.07:40:12.07#ibcon#about to write, iclass 34, count 2 2006.218.07:40:12.07#ibcon#wrote, iclass 34, count 2 2006.218.07:40:12.07#ibcon#about to read 3, iclass 34, count 2 2006.218.07:40:12.10#ibcon#read 3, iclass 34, count 2 2006.218.07:40:12.10#ibcon#about to read 4, iclass 34, count 2 2006.218.07:40:12.10#ibcon#read 4, iclass 34, count 2 2006.218.07:40:12.10#ibcon#about to read 5, iclass 34, count 2 2006.218.07:40:12.10#ibcon#read 5, iclass 34, count 2 2006.218.07:40:12.10#ibcon#about to read 6, iclass 34, count 2 2006.218.07:40:12.10#ibcon#read 6, iclass 34, count 2 2006.218.07:40:12.10#ibcon#end of sib2, iclass 34, count 2 2006.218.07:40:12.10#ibcon#*after write, iclass 34, count 2 2006.218.07:40:12.10#ibcon#*before return 0, iclass 34, count 2 2006.218.07:40:12.10#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.218.07:40:12.10#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.218.07:40:12.10#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.218.07:40:12.10#ibcon#ireg 7 cls_cnt 0 2006.218.07:40:12.10#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.218.07:40:12.22#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.218.07:40:12.22#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.218.07:40:12.22#ibcon#enter wrdev, iclass 34, count 0 2006.218.07:40:12.22#ibcon#first serial, iclass 34, count 0 2006.218.07:40:12.22#ibcon#enter sib2, iclass 34, count 0 2006.218.07:40:12.22#ibcon#flushed, iclass 34, count 0 2006.218.07:40:12.22#ibcon#about to write, iclass 34, count 0 2006.218.07:40:12.22#ibcon#wrote, iclass 34, count 0 2006.218.07:40:12.22#ibcon#about to read 3, iclass 34, count 0 2006.218.07:40:12.24#ibcon#read 3, iclass 34, count 0 2006.218.07:40:12.24#ibcon#about to read 4, iclass 34, count 0 2006.218.07:40:12.24#ibcon#read 4, iclass 34, count 0 2006.218.07:40:12.24#ibcon#about to read 5, iclass 34, count 0 2006.218.07:40:12.24#ibcon#read 5, iclass 34, count 0 2006.218.07:40:12.24#ibcon#about to read 6, iclass 34, count 0 2006.218.07:40:12.24#ibcon#read 6, iclass 34, count 0 2006.218.07:40:12.24#ibcon#end of sib2, iclass 34, count 0 2006.218.07:40:12.24#ibcon#*mode == 0, iclass 34, count 0 2006.218.07:40:12.24#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.218.07:40:12.24#ibcon#[27=USB\r\n] 2006.218.07:40:12.24#ibcon#*before write, iclass 34, count 0 2006.218.07:40:12.24#ibcon#enter sib2, iclass 34, count 0 2006.218.07:40:12.24#ibcon#flushed, iclass 34, count 0 2006.218.07:40:12.24#ibcon#about to write, iclass 34, count 0 2006.218.07:40:12.24#ibcon#wrote, iclass 34, count 0 2006.218.07:40:12.24#ibcon#about to read 3, iclass 34, count 0 2006.218.07:40:12.27#ibcon#read 3, iclass 34, count 0 2006.218.07:40:12.27#ibcon#about to read 4, iclass 34, count 0 2006.218.07:40:12.27#ibcon#read 4, iclass 34, count 0 2006.218.07:40:12.27#ibcon#about to read 5, iclass 34, count 0 2006.218.07:40:12.27#ibcon#read 5, iclass 34, count 0 2006.218.07:40:12.27#ibcon#about to read 6, iclass 34, count 0 2006.218.07:40:12.27#ibcon#read 6, iclass 34, count 0 2006.218.07:40:12.27#ibcon#end of sib2, iclass 34, count 0 2006.218.07:40:12.27#ibcon#*after write, iclass 34, count 0 2006.218.07:40:12.27#ibcon#*before return 0, iclass 34, count 0 2006.218.07:40:12.27#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.218.07:40:12.27#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.218.07:40:12.27#ibcon#about to clear, iclass 34 cls_cnt 0 2006.218.07:40:12.27#ibcon#cleared, iclass 34 cls_cnt 0 2006.218.07:40:12.27$vc4f8/vblo=6,752.99 2006.218.07:40:12.27#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.218.07:40:12.27#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.218.07:40:12.27#ibcon#ireg 17 cls_cnt 0 2006.218.07:40:12.27#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.218.07:40:12.27#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.218.07:40:12.27#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.218.07:40:12.27#ibcon#enter wrdev, iclass 36, count 0 2006.218.07:40:12.27#ibcon#first serial, iclass 36, count 0 2006.218.07:40:12.27#ibcon#enter sib2, iclass 36, count 0 2006.218.07:40:12.27#ibcon#flushed, iclass 36, count 0 2006.218.07:40:12.27#ibcon#about to write, iclass 36, count 0 2006.218.07:40:12.27#ibcon#wrote, iclass 36, count 0 2006.218.07:40:12.27#ibcon#about to read 3, iclass 36, count 0 2006.218.07:40:12.29#ibcon#read 3, iclass 36, count 0 2006.218.07:40:12.29#ibcon#about to read 4, iclass 36, count 0 2006.218.07:40:12.29#ibcon#read 4, iclass 36, count 0 2006.218.07:40:12.29#ibcon#about to read 5, iclass 36, count 0 2006.218.07:40:12.29#ibcon#read 5, iclass 36, count 0 2006.218.07:40:12.29#ibcon#about to read 6, iclass 36, count 0 2006.218.07:40:12.29#ibcon#read 6, iclass 36, count 0 2006.218.07:40:12.29#ibcon#end of sib2, iclass 36, count 0 2006.218.07:40:12.29#ibcon#*mode == 0, iclass 36, count 0 2006.218.07:40:12.29#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.218.07:40:12.29#ibcon#[28=FRQ=06,752.99\r\n] 2006.218.07:40:12.29#ibcon#*before write, iclass 36, count 0 2006.218.07:40:12.29#ibcon#enter sib2, iclass 36, count 0 2006.218.07:40:12.29#ibcon#flushed, iclass 36, count 0 2006.218.07:40:12.29#ibcon#about to write, iclass 36, count 0 2006.218.07:40:12.29#ibcon#wrote, iclass 36, count 0 2006.218.07:40:12.29#ibcon#about to read 3, iclass 36, count 0 2006.218.07:40:12.33#ibcon#read 3, iclass 36, count 0 2006.218.07:40:12.33#ibcon#about to read 4, iclass 36, count 0 2006.218.07:40:12.33#ibcon#read 4, iclass 36, count 0 2006.218.07:40:12.33#ibcon#about to read 5, iclass 36, count 0 2006.218.07:40:12.33#ibcon#read 5, iclass 36, count 0 2006.218.07:40:12.33#ibcon#about to read 6, iclass 36, count 0 2006.218.07:40:12.33#ibcon#read 6, iclass 36, count 0 2006.218.07:40:12.33#ibcon#end of sib2, iclass 36, count 0 2006.218.07:40:12.33#ibcon#*after write, iclass 36, count 0 2006.218.07:40:12.33#ibcon#*before return 0, iclass 36, count 0 2006.218.07:40:12.33#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.218.07:40:12.33#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.218.07:40:12.33#ibcon#about to clear, iclass 36 cls_cnt 0 2006.218.07:40:12.33#ibcon#cleared, iclass 36 cls_cnt 0 2006.218.07:40:12.33$vc4f8/vb=6,4 2006.218.07:40:12.33#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.218.07:40:12.33#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.218.07:40:12.33#ibcon#ireg 11 cls_cnt 2 2006.218.07:40:12.33#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.218.07:40:12.39#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.218.07:40:12.39#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.218.07:40:12.39#ibcon#enter wrdev, iclass 38, count 2 2006.218.07:40:12.39#ibcon#first serial, iclass 38, count 2 2006.218.07:40:12.39#ibcon#enter sib2, iclass 38, count 2 2006.218.07:40:12.39#ibcon#flushed, iclass 38, count 2 2006.218.07:40:12.39#ibcon#about to write, iclass 38, count 2 2006.218.07:40:12.39#ibcon#wrote, iclass 38, count 2 2006.218.07:40:12.39#ibcon#about to read 3, iclass 38, count 2 2006.218.07:40:12.41#ibcon#read 3, iclass 38, count 2 2006.218.07:40:12.41#ibcon#about to read 4, iclass 38, count 2 2006.218.07:40:12.41#ibcon#read 4, iclass 38, count 2 2006.218.07:40:12.41#ibcon#about to read 5, iclass 38, count 2 2006.218.07:40:12.41#ibcon#read 5, iclass 38, count 2 2006.218.07:40:12.41#ibcon#about to read 6, iclass 38, count 2 2006.218.07:40:12.41#ibcon#read 6, iclass 38, count 2 2006.218.07:40:12.41#ibcon#end of sib2, iclass 38, count 2 2006.218.07:40:12.41#ibcon#*mode == 0, iclass 38, count 2 2006.218.07:40:12.41#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.218.07:40:12.41#ibcon#[27=AT06-04\r\n] 2006.218.07:40:12.41#ibcon#*before write, iclass 38, count 2 2006.218.07:40:12.41#ibcon#enter sib2, iclass 38, count 2 2006.218.07:40:12.41#ibcon#flushed, iclass 38, count 2 2006.218.07:40:12.41#ibcon#about to write, iclass 38, count 2 2006.218.07:40:12.41#ibcon#wrote, iclass 38, count 2 2006.218.07:40:12.41#ibcon#about to read 3, iclass 38, count 2 2006.218.07:40:12.44#ibcon#read 3, iclass 38, count 2 2006.218.07:40:12.44#ibcon#about to read 4, iclass 38, count 2 2006.218.07:40:12.44#ibcon#read 4, iclass 38, count 2 2006.218.07:40:12.44#ibcon#about to read 5, iclass 38, count 2 2006.218.07:40:12.44#ibcon#read 5, iclass 38, count 2 2006.218.07:40:12.44#ibcon#about to read 6, iclass 38, count 2 2006.218.07:40:12.44#ibcon#read 6, iclass 38, count 2 2006.218.07:40:12.44#ibcon#end of sib2, iclass 38, count 2 2006.218.07:40:12.44#ibcon#*after write, iclass 38, count 2 2006.218.07:40:12.44#ibcon#*before return 0, iclass 38, count 2 2006.218.07:40:12.44#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.218.07:40:12.44#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.218.07:40:12.44#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.218.07:40:12.44#ibcon#ireg 7 cls_cnt 0 2006.218.07:40:12.44#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.218.07:40:12.56#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.218.07:40:12.56#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.218.07:40:12.56#ibcon#enter wrdev, iclass 38, count 0 2006.218.07:40:12.56#ibcon#first serial, iclass 38, count 0 2006.218.07:40:12.56#ibcon#enter sib2, iclass 38, count 0 2006.218.07:40:12.56#ibcon#flushed, iclass 38, count 0 2006.218.07:40:12.56#ibcon#about to write, iclass 38, count 0 2006.218.07:40:12.56#ibcon#wrote, iclass 38, count 0 2006.218.07:40:12.56#ibcon#about to read 3, iclass 38, count 0 2006.218.07:40:12.58#ibcon#read 3, iclass 38, count 0 2006.218.07:40:12.58#ibcon#about to read 4, iclass 38, count 0 2006.218.07:40:12.58#ibcon#read 4, iclass 38, count 0 2006.218.07:40:12.58#ibcon#about to read 5, iclass 38, count 0 2006.218.07:40:12.58#ibcon#read 5, iclass 38, count 0 2006.218.07:40:12.58#ibcon#about to read 6, iclass 38, count 0 2006.218.07:40:12.58#ibcon#read 6, iclass 38, count 0 2006.218.07:40:12.58#ibcon#end of sib2, iclass 38, count 0 2006.218.07:40:12.58#ibcon#*mode == 0, iclass 38, count 0 2006.218.07:40:12.58#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.218.07:40:12.58#ibcon#[27=USB\r\n] 2006.218.07:40:12.58#ibcon#*before write, iclass 38, count 0 2006.218.07:40:12.58#ibcon#enter sib2, iclass 38, count 0 2006.218.07:40:12.58#ibcon#flushed, iclass 38, count 0 2006.218.07:40:12.58#ibcon#about to write, iclass 38, count 0 2006.218.07:40:12.58#ibcon#wrote, iclass 38, count 0 2006.218.07:40:12.58#ibcon#about to read 3, iclass 38, count 0 2006.218.07:40:12.61#ibcon#read 3, iclass 38, count 0 2006.218.07:40:12.61#ibcon#about to read 4, iclass 38, count 0 2006.218.07:40:12.61#ibcon#read 4, iclass 38, count 0 2006.218.07:40:12.61#ibcon#about to read 5, iclass 38, count 0 2006.218.07:40:12.61#ibcon#read 5, iclass 38, count 0 2006.218.07:40:12.61#ibcon#about to read 6, iclass 38, count 0 2006.218.07:40:12.61#ibcon#read 6, iclass 38, count 0 2006.218.07:40:12.61#ibcon#end of sib2, iclass 38, count 0 2006.218.07:40:12.61#ibcon#*after write, iclass 38, count 0 2006.218.07:40:12.61#ibcon#*before return 0, iclass 38, count 0 2006.218.07:40:12.61#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.218.07:40:12.61#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.218.07:40:12.61#ibcon#about to clear, iclass 38 cls_cnt 0 2006.218.07:40:12.61#ibcon#cleared, iclass 38 cls_cnt 0 2006.218.07:40:12.61$vc4f8/vabw=wide 2006.218.07:40:12.61#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.218.07:40:12.61#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.218.07:40:12.61#ibcon#ireg 8 cls_cnt 0 2006.218.07:40:12.61#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.218.07:40:12.61#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.218.07:40:12.61#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.218.07:40:12.61#ibcon#enter wrdev, iclass 40, count 0 2006.218.07:40:12.61#ibcon#first serial, iclass 40, count 0 2006.218.07:40:12.61#ibcon#enter sib2, iclass 40, count 0 2006.218.07:40:12.61#ibcon#flushed, iclass 40, count 0 2006.218.07:40:12.61#ibcon#about to write, iclass 40, count 0 2006.218.07:40:12.61#ibcon#wrote, iclass 40, count 0 2006.218.07:40:12.61#ibcon#about to read 3, iclass 40, count 0 2006.218.07:40:12.63#ibcon#read 3, iclass 40, count 0 2006.218.07:40:12.63#ibcon#about to read 4, iclass 40, count 0 2006.218.07:40:12.63#ibcon#read 4, iclass 40, count 0 2006.218.07:40:12.63#ibcon#about to read 5, iclass 40, count 0 2006.218.07:40:12.63#ibcon#read 5, iclass 40, count 0 2006.218.07:40:12.63#ibcon#about to read 6, iclass 40, count 0 2006.218.07:40:12.63#ibcon#read 6, iclass 40, count 0 2006.218.07:40:12.63#ibcon#end of sib2, iclass 40, count 0 2006.218.07:40:12.63#ibcon#*mode == 0, iclass 40, count 0 2006.218.07:40:12.63#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.218.07:40:12.63#ibcon#[25=BW32\r\n] 2006.218.07:40:12.63#ibcon#*before write, iclass 40, count 0 2006.218.07:40:12.63#ibcon#enter sib2, iclass 40, count 0 2006.218.07:40:12.63#ibcon#flushed, iclass 40, count 0 2006.218.07:40:12.63#ibcon#about to write, iclass 40, count 0 2006.218.07:40:12.63#ibcon#wrote, iclass 40, count 0 2006.218.07:40:12.63#ibcon#about to read 3, iclass 40, count 0 2006.218.07:40:12.66#ibcon#read 3, iclass 40, count 0 2006.218.07:40:12.66#ibcon#about to read 4, iclass 40, count 0 2006.218.07:40:12.66#ibcon#read 4, iclass 40, count 0 2006.218.07:40:12.66#ibcon#about to read 5, iclass 40, count 0 2006.218.07:40:12.66#ibcon#read 5, iclass 40, count 0 2006.218.07:40:12.66#ibcon#about to read 6, iclass 40, count 0 2006.218.07:40:12.66#ibcon#read 6, iclass 40, count 0 2006.218.07:40:12.66#ibcon#end of sib2, iclass 40, count 0 2006.218.07:40:12.66#ibcon#*after write, iclass 40, count 0 2006.218.07:40:12.66#ibcon#*before return 0, iclass 40, count 0 2006.218.07:40:12.66#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.218.07:40:12.66#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.218.07:40:12.66#ibcon#about to clear, iclass 40 cls_cnt 0 2006.218.07:40:12.66#ibcon#cleared, iclass 40 cls_cnt 0 2006.218.07:40:12.66$vc4f8/vbbw=wide 2006.218.07:40:12.66#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.218.07:40:12.66#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.218.07:40:12.66#ibcon#ireg 8 cls_cnt 0 2006.218.07:40:12.66#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.218.07:40:12.73#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.218.07:40:12.73#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.218.07:40:12.73#ibcon#enter wrdev, iclass 4, count 0 2006.218.07:40:12.73#ibcon#first serial, iclass 4, count 0 2006.218.07:40:12.73#ibcon#enter sib2, iclass 4, count 0 2006.218.07:40:12.73#ibcon#flushed, iclass 4, count 0 2006.218.07:40:12.73#ibcon#about to write, iclass 4, count 0 2006.218.07:40:12.73#ibcon#wrote, iclass 4, count 0 2006.218.07:40:12.73#ibcon#about to read 3, iclass 4, count 0 2006.218.07:40:12.75#ibcon#read 3, iclass 4, count 0 2006.218.07:40:12.75#ibcon#about to read 4, iclass 4, count 0 2006.218.07:40:12.75#ibcon#read 4, iclass 4, count 0 2006.218.07:40:12.75#ibcon#about to read 5, iclass 4, count 0 2006.218.07:40:12.75#ibcon#read 5, iclass 4, count 0 2006.218.07:40:12.75#ibcon#about to read 6, iclass 4, count 0 2006.218.07:40:12.75#ibcon#read 6, iclass 4, count 0 2006.218.07:40:12.75#ibcon#end of sib2, iclass 4, count 0 2006.218.07:40:12.75#ibcon#*mode == 0, iclass 4, count 0 2006.218.07:40:12.75#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.218.07:40:12.75#ibcon#[27=BW32\r\n] 2006.218.07:40:12.75#ibcon#*before write, iclass 4, count 0 2006.218.07:40:12.75#ibcon#enter sib2, iclass 4, count 0 2006.218.07:40:12.75#ibcon#flushed, iclass 4, count 0 2006.218.07:40:12.75#ibcon#about to write, iclass 4, count 0 2006.218.07:40:12.75#ibcon#wrote, iclass 4, count 0 2006.218.07:40:12.75#ibcon#about to read 3, iclass 4, count 0 2006.218.07:40:12.78#ibcon#read 3, iclass 4, count 0 2006.218.07:40:12.78#ibcon#about to read 4, iclass 4, count 0 2006.218.07:40:12.78#ibcon#read 4, iclass 4, count 0 2006.218.07:40:12.78#ibcon#about to read 5, iclass 4, count 0 2006.218.07:40:12.78#ibcon#read 5, iclass 4, count 0 2006.218.07:40:12.78#ibcon#about to read 6, iclass 4, count 0 2006.218.07:40:12.78#ibcon#read 6, iclass 4, count 0 2006.218.07:40:12.78#ibcon#end of sib2, iclass 4, count 0 2006.218.07:40:12.78#ibcon#*after write, iclass 4, count 0 2006.218.07:40:12.78#ibcon#*before return 0, iclass 4, count 0 2006.218.07:40:12.78#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.218.07:40:12.78#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.218.07:40:12.78#ibcon#about to clear, iclass 4 cls_cnt 0 2006.218.07:40:12.78#ibcon#cleared, iclass 4 cls_cnt 0 2006.218.07:40:12.78$4f8m12a/ifd4f 2006.218.07:40:12.78$ifd4f/lo= 2006.218.07:40:12.78$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.218.07:40:12.78$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.218.07:40:12.78$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.218.07:40:12.78$ifd4f/patch= 2006.218.07:40:12.78$ifd4f/patch=lo1,a1,a2,a3,a4 2006.218.07:40:12.78$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.218.07:40:12.78$ifd4f/patch=lo3,a5,a6,a7,a8 2006.218.07:40:12.78$4f8m12a/"form=m,16.000,1:2 2006.218.07:40:12.78$4f8m12a/"tpicd 2006.218.07:40:12.78$4f8m12a/echo=off 2006.218.07:40:12.78$4f8m12a/xlog=off 2006.218.07:40:12.78:!2006.218.07:40:40 2006.218.07:40:20.14#trakl#Source acquired 2006.218.07:40:22.14#flagr#flagr/antenna,acquired 2006.218.07:40:40.00:preob 2006.218.07:40:41.14/onsource/TRACKING 2006.218.07:40:41.14:!2006.218.07:40:50 2006.218.07:40:50.00:data_valid=on 2006.218.07:40:50.00:midob 2006.218.07:40:50.14/onsource/TRACKING 2006.218.07:40:50.14/wx/31.40,1007.4,71 2006.218.07:40:50.29/cable/+6.3842E-03 2006.218.07:40:51.38/va/01,05,usb,yes,31,33 2006.218.07:40:51.38/va/02,04,usb,yes,29,30 2006.218.07:40:51.38/va/03,04,usb,yes,27,28 2006.218.07:40:51.38/va/04,04,usb,yes,31,33 2006.218.07:40:51.38/va/05,07,usb,yes,32,34 2006.218.07:40:51.38/va/06,06,usb,yes,31,31 2006.218.07:40:51.38/va/07,06,usb,yes,32,32 2006.218.07:40:51.38/va/08,07,usb,yes,30,30 2006.218.07:40:51.61/valo/01,532.99,yes,locked 2006.218.07:40:51.61/valo/02,572.99,yes,locked 2006.218.07:40:51.61/valo/03,672.99,yes,locked 2006.218.07:40:51.61/valo/04,832.99,yes,locked 2006.218.07:40:51.61/valo/05,652.99,yes,locked 2006.218.07:40:51.61/valo/06,772.99,yes,locked 2006.218.07:40:51.61/valo/07,832.99,yes,locked 2006.218.07:40:51.61/valo/08,852.99,yes,locked 2006.218.07:40:52.70/vb/01,04,usb,yes,30,29 2006.218.07:40:52.70/vb/02,04,usb,yes,32,33 2006.218.07:40:52.70/vb/03,04,usb,yes,28,32 2006.218.07:40:52.70/vb/04,04,usb,yes,29,29 2006.218.07:40:52.70/vb/05,04,usb,yes,27,31 2006.218.07:40:52.70/vb/06,04,usb,yes,28,31 2006.218.07:40:52.70/vb/07,04,usb,yes,31,30 2006.218.07:40:52.70/vb/08,04,usb,yes,28,31 2006.218.07:40:52.93/vblo/01,632.99,yes,locked 2006.218.07:40:52.93/vblo/02,640.99,yes,locked 2006.218.07:40:52.93/vblo/03,656.99,yes,locked 2006.218.07:40:52.93/vblo/04,712.99,yes,locked 2006.218.07:40:52.93/vblo/05,744.99,yes,locked 2006.218.07:40:52.93/vblo/06,752.99,yes,locked 2006.218.07:40:52.93/vblo/07,734.99,yes,locked 2006.218.07:40:52.93/vblo/08,744.99,yes,locked 2006.218.07:40:53.08/vabw/8 2006.218.07:40:53.23/vbbw/8 2006.218.07:40:53.32/xfe/off,on,15.0 2006.218.07:40:53.70/ifatt/23,28,28,28 2006.218.07:40:54.07/fmout-gps/S +4.73E-07 2006.218.07:40:54.14:!2006.218.07:41:50 2006.218.07:41:50.01:data_valid=off 2006.218.07:41:50.01:postob 2006.218.07:41:50.10/cable/+6.3835E-03 2006.218.07:41:50.10/wx/31.38,1007.4,71 2006.218.07:41:51.07/fmout-gps/S +4.72E-07 2006.218.07:41:51.07:scan_name=218-0742,k06218,60 2006.218.07:41:51.07:source=1739+522,174036.98,521143.4,2000.0,cw 2006.218.07:41:51.14#flagr#flagr/antenna,new-source 2006.218.07:41:52.14:checkk5 2006.218.07:41:52.52/chk_autoobs//k5ts1/ autoobs is running! 2006.218.07:41:52.91/chk_autoobs//k5ts2/ autoobs is running! 2006.218.07:41:53.28/chk_autoobs//k5ts3/ autoobs is running! 2006.218.07:41:53.66/chk_autoobs//k5ts4/ autoobs is running! 2006.218.07:41:54.02/chk_obsdata//k5ts1/T2180740??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:41:54.39/chk_obsdata//k5ts2/T2180740??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:41:54.76/chk_obsdata//k5ts3/T2180740??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:41:55.13/chk_obsdata//k5ts4/T2180740??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:41:55.82/k5log//k5ts1_log_newline 2006.218.07:41:56.51/k5log//k5ts2_log_newline 2006.218.07:41:57.20/k5log//k5ts3_log_newline 2006.218.07:41:57.90/k5log//k5ts4_log_newline 2006.218.07:41:57.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.218.07:41:57.92:4f8m12a=1 2006.218.07:41:57.92$4f8m12a/echo=on 2006.218.07:41:57.92$4f8m12a/pcalon 2006.218.07:41:57.92$pcalon/"no phase cal control is implemented here 2006.218.07:41:57.92$4f8m12a/"tpicd=stop 2006.218.07:41:57.92$4f8m12a/vc4f8 2006.218.07:41:57.92$vc4f8/valo=1,532.99 2006.218.07:41:57.93#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.218.07:41:57.93#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.218.07:41:57.93#ibcon#ireg 17 cls_cnt 0 2006.218.07:41:57.93#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.218.07:41:57.93#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.218.07:41:57.93#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.218.07:41:57.93#ibcon#enter wrdev, iclass 13, count 0 2006.218.07:41:57.93#ibcon#first serial, iclass 13, count 0 2006.218.07:41:57.93#ibcon#enter sib2, iclass 13, count 0 2006.218.07:41:57.93#ibcon#flushed, iclass 13, count 0 2006.218.07:41:57.93#ibcon#about to write, iclass 13, count 0 2006.218.07:41:57.93#ibcon#wrote, iclass 13, count 0 2006.218.07:41:57.93#ibcon#about to read 3, iclass 13, count 0 2006.218.07:41:57.97#ibcon#read 3, iclass 13, count 0 2006.218.07:41:57.97#ibcon#about to read 4, iclass 13, count 0 2006.218.07:41:57.97#ibcon#read 4, iclass 13, count 0 2006.218.07:41:57.97#ibcon#about to read 5, iclass 13, count 0 2006.218.07:41:57.97#ibcon#read 5, iclass 13, count 0 2006.218.07:41:57.97#ibcon#about to read 6, iclass 13, count 0 2006.218.07:41:57.97#ibcon#read 6, iclass 13, count 0 2006.218.07:41:57.97#ibcon#end of sib2, iclass 13, count 0 2006.218.07:41:57.97#ibcon#*mode == 0, iclass 13, count 0 2006.218.07:41:57.97#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.218.07:41:57.97#ibcon#[26=FRQ=01,532.99\r\n] 2006.218.07:41:57.97#ibcon#*before write, iclass 13, count 0 2006.218.07:41:57.97#ibcon#enter sib2, iclass 13, count 0 2006.218.07:41:57.97#ibcon#flushed, iclass 13, count 0 2006.218.07:41:57.97#ibcon#about to write, iclass 13, count 0 2006.218.07:41:57.97#ibcon#wrote, iclass 13, count 0 2006.218.07:41:57.97#ibcon#about to read 3, iclass 13, count 0 2006.218.07:41:58.02#ibcon#read 3, iclass 13, count 0 2006.218.07:41:58.02#ibcon#about to read 4, iclass 13, count 0 2006.218.07:41:58.02#ibcon#read 4, iclass 13, count 0 2006.218.07:41:58.02#ibcon#about to read 5, iclass 13, count 0 2006.218.07:41:58.02#ibcon#read 5, iclass 13, count 0 2006.218.07:41:58.02#ibcon#about to read 6, iclass 13, count 0 2006.218.07:41:58.02#ibcon#read 6, iclass 13, count 0 2006.218.07:41:58.02#ibcon#end of sib2, iclass 13, count 0 2006.218.07:41:58.02#ibcon#*after write, iclass 13, count 0 2006.218.07:41:58.02#ibcon#*before return 0, iclass 13, count 0 2006.218.07:41:58.02#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.218.07:41:58.02#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.218.07:41:58.02#ibcon#about to clear, iclass 13 cls_cnt 0 2006.218.07:41:58.02#ibcon#cleared, iclass 13 cls_cnt 0 2006.218.07:41:58.02$vc4f8/va=1,5 2006.218.07:41:58.02#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.218.07:41:58.02#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.218.07:41:58.02#ibcon#ireg 11 cls_cnt 2 2006.218.07:41:58.02#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.218.07:41:58.02#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.218.07:41:58.02#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.218.07:41:58.02#ibcon#enter wrdev, iclass 15, count 2 2006.218.07:41:58.02#ibcon#first serial, iclass 15, count 2 2006.218.07:41:58.02#ibcon#enter sib2, iclass 15, count 2 2006.218.07:41:58.02#ibcon#flushed, iclass 15, count 2 2006.218.07:41:58.02#ibcon#about to write, iclass 15, count 2 2006.218.07:41:58.02#ibcon#wrote, iclass 15, count 2 2006.218.07:41:58.02#ibcon#about to read 3, iclass 15, count 2 2006.218.07:41:58.04#ibcon#read 3, iclass 15, count 2 2006.218.07:41:58.04#ibcon#about to read 4, iclass 15, count 2 2006.218.07:41:58.04#ibcon#read 4, iclass 15, count 2 2006.218.07:41:58.04#ibcon#about to read 5, iclass 15, count 2 2006.218.07:41:58.04#ibcon#read 5, iclass 15, count 2 2006.218.07:41:58.04#ibcon#about to read 6, iclass 15, count 2 2006.218.07:41:58.04#ibcon#read 6, iclass 15, count 2 2006.218.07:41:58.04#ibcon#end of sib2, iclass 15, count 2 2006.218.07:41:58.04#ibcon#*mode == 0, iclass 15, count 2 2006.218.07:41:58.04#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.218.07:41:58.04#ibcon#[25=AT01-05\r\n] 2006.218.07:41:58.04#ibcon#*before write, iclass 15, count 2 2006.218.07:41:58.04#ibcon#enter sib2, iclass 15, count 2 2006.218.07:41:58.04#ibcon#flushed, iclass 15, count 2 2006.218.07:41:58.04#ibcon#about to write, iclass 15, count 2 2006.218.07:41:58.04#ibcon#wrote, iclass 15, count 2 2006.218.07:41:58.04#ibcon#about to read 3, iclass 15, count 2 2006.218.07:41:58.07#ibcon#read 3, iclass 15, count 2 2006.218.07:41:58.07#ibcon#about to read 4, iclass 15, count 2 2006.218.07:41:58.07#ibcon#read 4, iclass 15, count 2 2006.218.07:41:58.07#ibcon#about to read 5, iclass 15, count 2 2006.218.07:41:58.07#ibcon#read 5, iclass 15, count 2 2006.218.07:41:58.07#ibcon#about to read 6, iclass 15, count 2 2006.218.07:41:58.07#ibcon#read 6, iclass 15, count 2 2006.218.07:41:58.07#ibcon#end of sib2, iclass 15, count 2 2006.218.07:41:58.07#ibcon#*after write, iclass 15, count 2 2006.218.07:41:58.07#ibcon#*before return 0, iclass 15, count 2 2006.218.07:41:58.07#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.218.07:41:58.07#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.218.07:41:58.07#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.218.07:41:58.07#ibcon#ireg 7 cls_cnt 0 2006.218.07:41:58.07#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.218.07:41:58.19#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.218.07:41:58.19#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.218.07:41:58.19#ibcon#enter wrdev, iclass 15, count 0 2006.218.07:41:58.19#ibcon#first serial, iclass 15, count 0 2006.218.07:41:58.19#ibcon#enter sib2, iclass 15, count 0 2006.218.07:41:58.19#ibcon#flushed, iclass 15, count 0 2006.218.07:41:58.19#ibcon#about to write, iclass 15, count 0 2006.218.07:41:58.19#ibcon#wrote, iclass 15, count 0 2006.218.07:41:58.19#ibcon#about to read 3, iclass 15, count 0 2006.218.07:41:58.21#ibcon#read 3, iclass 15, count 0 2006.218.07:41:58.21#ibcon#about to read 4, iclass 15, count 0 2006.218.07:41:58.21#ibcon#read 4, iclass 15, count 0 2006.218.07:41:58.21#ibcon#about to read 5, iclass 15, count 0 2006.218.07:41:58.21#ibcon#read 5, iclass 15, count 0 2006.218.07:41:58.21#ibcon#about to read 6, iclass 15, count 0 2006.218.07:41:58.21#ibcon#read 6, iclass 15, count 0 2006.218.07:41:58.21#ibcon#end of sib2, iclass 15, count 0 2006.218.07:41:58.21#ibcon#*mode == 0, iclass 15, count 0 2006.218.07:41:58.21#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.218.07:41:58.21#ibcon#[25=USB\r\n] 2006.218.07:41:58.21#ibcon#*before write, iclass 15, count 0 2006.218.07:41:58.21#ibcon#enter sib2, iclass 15, count 0 2006.218.07:41:58.21#ibcon#flushed, iclass 15, count 0 2006.218.07:41:58.21#ibcon#about to write, iclass 15, count 0 2006.218.07:41:58.21#ibcon#wrote, iclass 15, count 0 2006.218.07:41:58.21#ibcon#about to read 3, iclass 15, count 0 2006.218.07:41:58.24#ibcon#read 3, iclass 15, count 0 2006.218.07:41:58.24#ibcon#about to read 4, iclass 15, count 0 2006.218.07:41:58.24#ibcon#read 4, iclass 15, count 0 2006.218.07:41:58.24#ibcon#about to read 5, iclass 15, count 0 2006.218.07:41:58.24#ibcon#read 5, iclass 15, count 0 2006.218.07:41:58.24#ibcon#about to read 6, iclass 15, count 0 2006.218.07:41:58.24#ibcon#read 6, iclass 15, count 0 2006.218.07:41:58.24#ibcon#end of sib2, iclass 15, count 0 2006.218.07:41:58.24#ibcon#*after write, iclass 15, count 0 2006.218.07:41:58.24#ibcon#*before return 0, iclass 15, count 0 2006.218.07:41:58.24#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.218.07:41:58.24#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.218.07:41:58.24#ibcon#about to clear, iclass 15 cls_cnt 0 2006.218.07:41:58.24#ibcon#cleared, iclass 15 cls_cnt 0 2006.218.07:41:58.24$vc4f8/valo=2,572.99 2006.218.07:41:58.24#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.218.07:41:58.24#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.218.07:41:58.24#ibcon#ireg 17 cls_cnt 0 2006.218.07:41:58.24#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.218.07:41:58.24#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.218.07:41:58.24#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.218.07:41:58.24#ibcon#enter wrdev, iclass 17, count 0 2006.218.07:41:58.24#ibcon#first serial, iclass 17, count 0 2006.218.07:41:58.24#ibcon#enter sib2, iclass 17, count 0 2006.218.07:41:58.24#ibcon#flushed, iclass 17, count 0 2006.218.07:41:58.24#ibcon#about to write, iclass 17, count 0 2006.218.07:41:58.24#ibcon#wrote, iclass 17, count 0 2006.218.07:41:58.24#ibcon#about to read 3, iclass 17, count 0 2006.218.07:41:58.26#ibcon#read 3, iclass 17, count 0 2006.218.07:41:58.26#ibcon#about to read 4, iclass 17, count 0 2006.218.07:41:58.26#ibcon#read 4, iclass 17, count 0 2006.218.07:41:58.26#ibcon#about to read 5, iclass 17, count 0 2006.218.07:41:58.26#ibcon#read 5, iclass 17, count 0 2006.218.07:41:58.26#ibcon#about to read 6, iclass 17, count 0 2006.218.07:41:58.26#ibcon#read 6, iclass 17, count 0 2006.218.07:41:58.26#ibcon#end of sib2, iclass 17, count 0 2006.218.07:41:58.26#ibcon#*mode == 0, iclass 17, count 0 2006.218.07:41:58.26#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.218.07:41:58.26#ibcon#[26=FRQ=02,572.99\r\n] 2006.218.07:41:58.26#ibcon#*before write, iclass 17, count 0 2006.218.07:41:58.26#ibcon#enter sib2, iclass 17, count 0 2006.218.07:41:58.26#ibcon#flushed, iclass 17, count 0 2006.218.07:41:58.26#ibcon#about to write, iclass 17, count 0 2006.218.07:41:58.26#ibcon#wrote, iclass 17, count 0 2006.218.07:41:58.26#ibcon#about to read 3, iclass 17, count 0 2006.218.07:41:58.30#ibcon#read 3, iclass 17, count 0 2006.218.07:41:58.30#ibcon#about to read 4, iclass 17, count 0 2006.218.07:41:58.30#ibcon#read 4, iclass 17, count 0 2006.218.07:41:58.30#ibcon#about to read 5, iclass 17, count 0 2006.218.07:41:58.30#ibcon#read 5, iclass 17, count 0 2006.218.07:41:58.30#ibcon#about to read 6, iclass 17, count 0 2006.218.07:41:58.30#ibcon#read 6, iclass 17, count 0 2006.218.07:41:58.30#ibcon#end of sib2, iclass 17, count 0 2006.218.07:41:58.30#ibcon#*after write, iclass 17, count 0 2006.218.07:41:58.30#ibcon#*before return 0, iclass 17, count 0 2006.218.07:41:58.30#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.218.07:41:58.30#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.218.07:41:58.30#ibcon#about to clear, iclass 17 cls_cnt 0 2006.218.07:41:58.30#ibcon#cleared, iclass 17 cls_cnt 0 2006.218.07:41:58.30$vc4f8/va=2,4 2006.218.07:41:58.30#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.218.07:41:58.30#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.218.07:41:58.30#ibcon#ireg 11 cls_cnt 2 2006.218.07:41:58.30#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.218.07:41:58.36#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.218.07:41:58.36#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.218.07:41:58.36#ibcon#enter wrdev, iclass 19, count 2 2006.218.07:41:58.36#ibcon#first serial, iclass 19, count 2 2006.218.07:41:58.36#ibcon#enter sib2, iclass 19, count 2 2006.218.07:41:58.36#ibcon#flushed, iclass 19, count 2 2006.218.07:41:58.36#ibcon#about to write, iclass 19, count 2 2006.218.07:41:58.36#ibcon#wrote, iclass 19, count 2 2006.218.07:41:58.36#ibcon#about to read 3, iclass 19, count 2 2006.218.07:41:58.38#ibcon#read 3, iclass 19, count 2 2006.218.07:41:58.38#ibcon#about to read 4, iclass 19, count 2 2006.218.07:41:58.38#ibcon#read 4, iclass 19, count 2 2006.218.07:41:58.38#ibcon#about to read 5, iclass 19, count 2 2006.218.07:41:58.38#ibcon#read 5, iclass 19, count 2 2006.218.07:41:58.38#ibcon#about to read 6, iclass 19, count 2 2006.218.07:41:58.38#ibcon#read 6, iclass 19, count 2 2006.218.07:41:58.38#ibcon#end of sib2, iclass 19, count 2 2006.218.07:41:58.38#ibcon#*mode == 0, iclass 19, count 2 2006.218.07:41:58.38#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.218.07:41:58.38#ibcon#[25=AT02-04\r\n] 2006.218.07:41:58.38#ibcon#*before write, iclass 19, count 2 2006.218.07:41:58.38#ibcon#enter sib2, iclass 19, count 2 2006.218.07:41:58.38#ibcon#flushed, iclass 19, count 2 2006.218.07:41:58.38#ibcon#about to write, iclass 19, count 2 2006.218.07:41:58.38#ibcon#wrote, iclass 19, count 2 2006.218.07:41:58.38#ibcon#about to read 3, iclass 19, count 2 2006.218.07:41:58.41#ibcon#read 3, iclass 19, count 2 2006.218.07:41:58.41#ibcon#about to read 4, iclass 19, count 2 2006.218.07:41:58.41#ibcon#read 4, iclass 19, count 2 2006.218.07:41:58.41#ibcon#about to read 5, iclass 19, count 2 2006.218.07:41:58.41#ibcon#read 5, iclass 19, count 2 2006.218.07:41:58.41#ibcon#about to read 6, iclass 19, count 2 2006.218.07:41:58.41#ibcon#read 6, iclass 19, count 2 2006.218.07:41:58.41#ibcon#end of sib2, iclass 19, count 2 2006.218.07:41:58.41#ibcon#*after write, iclass 19, count 2 2006.218.07:41:58.41#ibcon#*before return 0, iclass 19, count 2 2006.218.07:41:58.41#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.218.07:41:58.41#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.218.07:41:58.41#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.218.07:41:58.41#ibcon#ireg 7 cls_cnt 0 2006.218.07:41:58.41#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.218.07:41:58.53#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.218.07:41:58.53#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.218.07:41:58.53#ibcon#enter wrdev, iclass 19, count 0 2006.218.07:41:58.53#ibcon#first serial, iclass 19, count 0 2006.218.07:41:58.53#ibcon#enter sib2, iclass 19, count 0 2006.218.07:41:58.53#ibcon#flushed, iclass 19, count 0 2006.218.07:41:58.53#ibcon#about to write, iclass 19, count 0 2006.218.07:41:58.53#ibcon#wrote, iclass 19, count 0 2006.218.07:41:58.53#ibcon#about to read 3, iclass 19, count 0 2006.218.07:41:58.55#ibcon#read 3, iclass 19, count 0 2006.218.07:41:58.55#ibcon#about to read 4, iclass 19, count 0 2006.218.07:41:58.55#ibcon#read 4, iclass 19, count 0 2006.218.07:41:58.55#ibcon#about to read 5, iclass 19, count 0 2006.218.07:41:58.55#ibcon#read 5, iclass 19, count 0 2006.218.07:41:58.55#ibcon#about to read 6, iclass 19, count 0 2006.218.07:41:58.55#ibcon#read 6, iclass 19, count 0 2006.218.07:41:58.55#ibcon#end of sib2, iclass 19, count 0 2006.218.07:41:58.55#ibcon#*mode == 0, iclass 19, count 0 2006.218.07:41:58.55#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.218.07:41:58.55#ibcon#[25=USB\r\n] 2006.218.07:41:58.55#ibcon#*before write, iclass 19, count 0 2006.218.07:41:58.55#ibcon#enter sib2, iclass 19, count 0 2006.218.07:41:58.55#ibcon#flushed, iclass 19, count 0 2006.218.07:41:58.55#ibcon#about to write, iclass 19, count 0 2006.218.07:41:58.55#ibcon#wrote, iclass 19, count 0 2006.218.07:41:58.55#ibcon#about to read 3, iclass 19, count 0 2006.218.07:41:58.58#ibcon#read 3, iclass 19, count 0 2006.218.07:41:58.58#ibcon#about to read 4, iclass 19, count 0 2006.218.07:41:58.58#ibcon#read 4, iclass 19, count 0 2006.218.07:41:58.58#ibcon#about to read 5, iclass 19, count 0 2006.218.07:41:58.58#ibcon#read 5, iclass 19, count 0 2006.218.07:41:58.58#ibcon#about to read 6, iclass 19, count 0 2006.218.07:41:58.58#ibcon#read 6, iclass 19, count 0 2006.218.07:41:58.58#ibcon#end of sib2, iclass 19, count 0 2006.218.07:41:58.58#ibcon#*after write, iclass 19, count 0 2006.218.07:41:58.58#ibcon#*before return 0, iclass 19, count 0 2006.218.07:41:58.58#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.218.07:41:58.58#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.218.07:41:58.58#ibcon#about to clear, iclass 19 cls_cnt 0 2006.218.07:41:58.58#ibcon#cleared, iclass 19 cls_cnt 0 2006.218.07:41:58.58$vc4f8/valo=3,672.99 2006.218.07:41:58.58#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.218.07:41:58.58#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.218.07:41:58.58#ibcon#ireg 17 cls_cnt 0 2006.218.07:41:58.58#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.218.07:41:58.58#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.218.07:41:58.58#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.218.07:41:58.58#ibcon#enter wrdev, iclass 21, count 0 2006.218.07:41:58.58#ibcon#first serial, iclass 21, count 0 2006.218.07:41:58.58#ibcon#enter sib2, iclass 21, count 0 2006.218.07:41:58.58#ibcon#flushed, iclass 21, count 0 2006.218.07:41:58.58#ibcon#about to write, iclass 21, count 0 2006.218.07:41:58.58#ibcon#wrote, iclass 21, count 0 2006.218.07:41:58.58#ibcon#about to read 3, iclass 21, count 0 2006.218.07:41:58.60#ibcon#read 3, iclass 21, count 0 2006.218.07:41:58.60#ibcon#about to read 4, iclass 21, count 0 2006.218.07:41:58.60#ibcon#read 4, iclass 21, count 0 2006.218.07:41:58.60#ibcon#about to read 5, iclass 21, count 0 2006.218.07:41:58.60#ibcon#read 5, iclass 21, count 0 2006.218.07:41:58.60#ibcon#about to read 6, iclass 21, count 0 2006.218.07:41:58.60#ibcon#read 6, iclass 21, count 0 2006.218.07:41:58.60#ibcon#end of sib2, iclass 21, count 0 2006.218.07:41:58.60#ibcon#*mode == 0, iclass 21, count 0 2006.218.07:41:58.60#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.218.07:41:58.60#ibcon#[26=FRQ=03,672.99\r\n] 2006.218.07:41:58.60#ibcon#*before write, iclass 21, count 0 2006.218.07:41:58.60#ibcon#enter sib2, iclass 21, count 0 2006.218.07:41:58.60#ibcon#flushed, iclass 21, count 0 2006.218.07:41:58.60#ibcon#about to write, iclass 21, count 0 2006.218.07:41:58.60#ibcon#wrote, iclass 21, count 0 2006.218.07:41:58.60#ibcon#about to read 3, iclass 21, count 0 2006.218.07:41:58.65#ibcon#read 3, iclass 21, count 0 2006.218.07:41:58.65#ibcon#about to read 4, iclass 21, count 0 2006.218.07:41:58.65#ibcon#read 4, iclass 21, count 0 2006.218.07:41:58.65#ibcon#about to read 5, iclass 21, count 0 2006.218.07:41:58.65#ibcon#read 5, iclass 21, count 0 2006.218.07:41:58.65#ibcon#about to read 6, iclass 21, count 0 2006.218.07:41:58.65#ibcon#read 6, iclass 21, count 0 2006.218.07:41:58.65#ibcon#end of sib2, iclass 21, count 0 2006.218.07:41:58.65#ibcon#*after write, iclass 21, count 0 2006.218.07:41:58.65#ibcon#*before return 0, iclass 21, count 0 2006.218.07:41:58.65#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.218.07:41:58.65#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.218.07:41:58.65#ibcon#about to clear, iclass 21 cls_cnt 0 2006.218.07:41:58.65#ibcon#cleared, iclass 21 cls_cnt 0 2006.218.07:41:58.65$vc4f8/va=3,4 2006.218.07:41:58.65#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.218.07:41:58.65#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.218.07:41:58.65#ibcon#ireg 11 cls_cnt 2 2006.218.07:41:58.65#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.218.07:41:58.70#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.218.07:41:58.70#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.218.07:41:58.70#ibcon#enter wrdev, iclass 23, count 2 2006.218.07:41:58.70#ibcon#first serial, iclass 23, count 2 2006.218.07:41:58.70#ibcon#enter sib2, iclass 23, count 2 2006.218.07:41:58.70#ibcon#flushed, iclass 23, count 2 2006.218.07:41:58.70#ibcon#about to write, iclass 23, count 2 2006.218.07:41:58.70#ibcon#wrote, iclass 23, count 2 2006.218.07:41:58.70#ibcon#about to read 3, iclass 23, count 2 2006.218.07:41:58.72#ibcon#read 3, iclass 23, count 2 2006.218.07:41:58.72#ibcon#about to read 4, iclass 23, count 2 2006.218.07:41:58.72#ibcon#read 4, iclass 23, count 2 2006.218.07:41:58.72#ibcon#about to read 5, iclass 23, count 2 2006.218.07:41:58.72#ibcon#read 5, iclass 23, count 2 2006.218.07:41:58.72#ibcon#about to read 6, iclass 23, count 2 2006.218.07:41:58.72#ibcon#read 6, iclass 23, count 2 2006.218.07:41:58.72#ibcon#end of sib2, iclass 23, count 2 2006.218.07:41:58.72#ibcon#*mode == 0, iclass 23, count 2 2006.218.07:41:58.72#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.218.07:41:58.72#ibcon#[25=AT03-04\r\n] 2006.218.07:41:58.72#ibcon#*before write, iclass 23, count 2 2006.218.07:41:58.72#ibcon#enter sib2, iclass 23, count 2 2006.218.07:41:58.72#ibcon#flushed, iclass 23, count 2 2006.218.07:41:58.72#ibcon#about to write, iclass 23, count 2 2006.218.07:41:58.72#ibcon#wrote, iclass 23, count 2 2006.218.07:41:58.72#ibcon#about to read 3, iclass 23, count 2 2006.218.07:41:58.75#ibcon#read 3, iclass 23, count 2 2006.218.07:41:58.75#ibcon#about to read 4, iclass 23, count 2 2006.218.07:41:58.75#ibcon#read 4, iclass 23, count 2 2006.218.07:41:58.75#ibcon#about to read 5, iclass 23, count 2 2006.218.07:41:58.75#ibcon#read 5, iclass 23, count 2 2006.218.07:41:58.75#ibcon#about to read 6, iclass 23, count 2 2006.218.07:41:58.75#ibcon#read 6, iclass 23, count 2 2006.218.07:41:58.75#ibcon#end of sib2, iclass 23, count 2 2006.218.07:41:58.75#ibcon#*after write, iclass 23, count 2 2006.218.07:41:58.75#ibcon#*before return 0, iclass 23, count 2 2006.218.07:41:58.75#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.218.07:41:58.75#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.218.07:41:58.75#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.218.07:41:58.75#ibcon#ireg 7 cls_cnt 0 2006.218.07:41:58.75#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.218.07:41:58.87#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.218.07:41:58.87#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.218.07:41:58.87#ibcon#enter wrdev, iclass 23, count 0 2006.218.07:41:58.87#ibcon#first serial, iclass 23, count 0 2006.218.07:41:58.87#ibcon#enter sib2, iclass 23, count 0 2006.218.07:41:58.87#ibcon#flushed, iclass 23, count 0 2006.218.07:41:58.87#ibcon#about to write, iclass 23, count 0 2006.218.07:41:58.87#ibcon#wrote, iclass 23, count 0 2006.218.07:41:58.87#ibcon#about to read 3, iclass 23, count 0 2006.218.07:41:58.89#ibcon#read 3, iclass 23, count 0 2006.218.07:41:58.89#ibcon#about to read 4, iclass 23, count 0 2006.218.07:41:58.89#ibcon#read 4, iclass 23, count 0 2006.218.07:41:58.89#ibcon#about to read 5, iclass 23, count 0 2006.218.07:41:58.89#ibcon#read 5, iclass 23, count 0 2006.218.07:41:58.89#ibcon#about to read 6, iclass 23, count 0 2006.218.07:41:58.89#ibcon#read 6, iclass 23, count 0 2006.218.07:41:58.89#ibcon#end of sib2, iclass 23, count 0 2006.218.07:41:58.89#ibcon#*mode == 0, iclass 23, count 0 2006.218.07:41:58.89#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.218.07:41:58.89#ibcon#[25=USB\r\n] 2006.218.07:41:58.89#ibcon#*before write, iclass 23, count 0 2006.218.07:41:58.89#ibcon#enter sib2, iclass 23, count 0 2006.218.07:41:58.89#ibcon#flushed, iclass 23, count 0 2006.218.07:41:58.89#ibcon#about to write, iclass 23, count 0 2006.218.07:41:58.89#ibcon#wrote, iclass 23, count 0 2006.218.07:41:58.89#ibcon#about to read 3, iclass 23, count 0 2006.218.07:41:58.92#ibcon#read 3, iclass 23, count 0 2006.218.07:41:58.92#ibcon#about to read 4, iclass 23, count 0 2006.218.07:41:58.92#ibcon#read 4, iclass 23, count 0 2006.218.07:41:58.92#ibcon#about to read 5, iclass 23, count 0 2006.218.07:41:58.92#ibcon#read 5, iclass 23, count 0 2006.218.07:41:58.92#ibcon#about to read 6, iclass 23, count 0 2006.218.07:41:58.92#ibcon#read 6, iclass 23, count 0 2006.218.07:41:58.92#ibcon#end of sib2, iclass 23, count 0 2006.218.07:41:58.92#ibcon#*after write, iclass 23, count 0 2006.218.07:41:58.92#ibcon#*before return 0, iclass 23, count 0 2006.218.07:41:58.92#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.218.07:41:58.92#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.218.07:41:58.92#ibcon#about to clear, iclass 23 cls_cnt 0 2006.218.07:41:58.92#ibcon#cleared, iclass 23 cls_cnt 0 2006.218.07:41:58.92$vc4f8/valo=4,832.99 2006.218.07:41:58.92#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.218.07:41:58.92#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.218.07:41:58.92#ibcon#ireg 17 cls_cnt 0 2006.218.07:41:58.92#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.218.07:41:58.92#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.218.07:41:58.92#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.218.07:41:58.92#ibcon#enter wrdev, iclass 25, count 0 2006.218.07:41:58.92#ibcon#first serial, iclass 25, count 0 2006.218.07:41:58.92#ibcon#enter sib2, iclass 25, count 0 2006.218.07:41:58.92#ibcon#flushed, iclass 25, count 0 2006.218.07:41:58.92#ibcon#about to write, iclass 25, count 0 2006.218.07:41:58.92#ibcon#wrote, iclass 25, count 0 2006.218.07:41:58.92#ibcon#about to read 3, iclass 25, count 0 2006.218.07:41:58.94#ibcon#read 3, iclass 25, count 0 2006.218.07:41:58.94#ibcon#about to read 4, iclass 25, count 0 2006.218.07:41:58.94#ibcon#read 4, iclass 25, count 0 2006.218.07:41:58.94#ibcon#about to read 5, iclass 25, count 0 2006.218.07:41:58.94#ibcon#read 5, iclass 25, count 0 2006.218.07:41:58.94#ibcon#about to read 6, iclass 25, count 0 2006.218.07:41:58.94#ibcon#read 6, iclass 25, count 0 2006.218.07:41:58.94#ibcon#end of sib2, iclass 25, count 0 2006.218.07:41:58.94#ibcon#*mode == 0, iclass 25, count 0 2006.218.07:41:58.94#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.218.07:41:58.94#ibcon#[26=FRQ=04,832.99\r\n] 2006.218.07:41:58.94#ibcon#*before write, iclass 25, count 0 2006.218.07:41:58.94#ibcon#enter sib2, iclass 25, count 0 2006.218.07:41:58.94#ibcon#flushed, iclass 25, count 0 2006.218.07:41:58.94#ibcon#about to write, iclass 25, count 0 2006.218.07:41:58.94#ibcon#wrote, iclass 25, count 0 2006.218.07:41:58.94#ibcon#about to read 3, iclass 25, count 0 2006.218.07:41:58.98#ibcon#read 3, iclass 25, count 0 2006.218.07:41:58.98#ibcon#about to read 4, iclass 25, count 0 2006.218.07:41:58.98#ibcon#read 4, iclass 25, count 0 2006.218.07:41:58.98#ibcon#about to read 5, iclass 25, count 0 2006.218.07:41:58.98#ibcon#read 5, iclass 25, count 0 2006.218.07:41:58.98#ibcon#about to read 6, iclass 25, count 0 2006.218.07:41:58.98#ibcon#read 6, iclass 25, count 0 2006.218.07:41:58.98#ibcon#end of sib2, iclass 25, count 0 2006.218.07:41:58.98#ibcon#*after write, iclass 25, count 0 2006.218.07:41:58.98#ibcon#*before return 0, iclass 25, count 0 2006.218.07:41:58.98#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.218.07:41:58.98#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.218.07:41:58.98#ibcon#about to clear, iclass 25 cls_cnt 0 2006.218.07:41:58.98#ibcon#cleared, iclass 25 cls_cnt 0 2006.218.07:41:58.98$vc4f8/va=4,4 2006.218.07:41:58.98#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.218.07:41:58.98#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.218.07:41:58.98#ibcon#ireg 11 cls_cnt 2 2006.218.07:41:58.98#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.218.07:41:59.04#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.218.07:41:59.04#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.218.07:41:59.04#ibcon#enter wrdev, iclass 27, count 2 2006.218.07:41:59.04#ibcon#first serial, iclass 27, count 2 2006.218.07:41:59.04#ibcon#enter sib2, iclass 27, count 2 2006.218.07:41:59.04#ibcon#flushed, iclass 27, count 2 2006.218.07:41:59.04#ibcon#about to write, iclass 27, count 2 2006.218.07:41:59.04#ibcon#wrote, iclass 27, count 2 2006.218.07:41:59.04#ibcon#about to read 3, iclass 27, count 2 2006.218.07:41:59.06#ibcon#read 3, iclass 27, count 2 2006.218.07:41:59.06#ibcon#about to read 4, iclass 27, count 2 2006.218.07:41:59.06#ibcon#read 4, iclass 27, count 2 2006.218.07:41:59.06#ibcon#about to read 5, iclass 27, count 2 2006.218.07:41:59.06#ibcon#read 5, iclass 27, count 2 2006.218.07:41:59.06#ibcon#about to read 6, iclass 27, count 2 2006.218.07:41:59.06#ibcon#read 6, iclass 27, count 2 2006.218.07:41:59.06#ibcon#end of sib2, iclass 27, count 2 2006.218.07:41:59.06#ibcon#*mode == 0, iclass 27, count 2 2006.218.07:41:59.06#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.218.07:41:59.06#ibcon#[25=AT04-04\r\n] 2006.218.07:41:59.06#ibcon#*before write, iclass 27, count 2 2006.218.07:41:59.06#ibcon#enter sib2, iclass 27, count 2 2006.218.07:41:59.06#ibcon#flushed, iclass 27, count 2 2006.218.07:41:59.06#ibcon#about to write, iclass 27, count 2 2006.218.07:41:59.06#ibcon#wrote, iclass 27, count 2 2006.218.07:41:59.06#ibcon#about to read 3, iclass 27, count 2 2006.218.07:41:59.09#ibcon#read 3, iclass 27, count 2 2006.218.07:41:59.09#ibcon#about to read 4, iclass 27, count 2 2006.218.07:41:59.09#ibcon#read 4, iclass 27, count 2 2006.218.07:41:59.09#ibcon#about to read 5, iclass 27, count 2 2006.218.07:41:59.09#ibcon#read 5, iclass 27, count 2 2006.218.07:41:59.09#ibcon#about to read 6, iclass 27, count 2 2006.218.07:41:59.09#ibcon#read 6, iclass 27, count 2 2006.218.07:41:59.09#ibcon#end of sib2, iclass 27, count 2 2006.218.07:41:59.09#ibcon#*after write, iclass 27, count 2 2006.218.07:41:59.09#ibcon#*before return 0, iclass 27, count 2 2006.218.07:41:59.09#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.218.07:41:59.09#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.218.07:41:59.09#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.218.07:41:59.09#ibcon#ireg 7 cls_cnt 0 2006.218.07:41:59.09#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.218.07:41:59.21#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.218.07:41:59.21#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.218.07:41:59.21#ibcon#enter wrdev, iclass 27, count 0 2006.218.07:41:59.21#ibcon#first serial, iclass 27, count 0 2006.218.07:41:59.21#ibcon#enter sib2, iclass 27, count 0 2006.218.07:41:59.21#ibcon#flushed, iclass 27, count 0 2006.218.07:41:59.21#ibcon#about to write, iclass 27, count 0 2006.218.07:41:59.21#ibcon#wrote, iclass 27, count 0 2006.218.07:41:59.21#ibcon#about to read 3, iclass 27, count 0 2006.218.07:41:59.23#ibcon#read 3, iclass 27, count 0 2006.218.07:41:59.23#ibcon#about to read 4, iclass 27, count 0 2006.218.07:41:59.23#ibcon#read 4, iclass 27, count 0 2006.218.07:41:59.23#ibcon#about to read 5, iclass 27, count 0 2006.218.07:41:59.23#ibcon#read 5, iclass 27, count 0 2006.218.07:41:59.23#ibcon#about to read 6, iclass 27, count 0 2006.218.07:41:59.23#ibcon#read 6, iclass 27, count 0 2006.218.07:41:59.23#ibcon#end of sib2, iclass 27, count 0 2006.218.07:41:59.23#ibcon#*mode == 0, iclass 27, count 0 2006.218.07:41:59.23#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.218.07:41:59.23#ibcon#[25=USB\r\n] 2006.218.07:41:59.23#ibcon#*before write, iclass 27, count 0 2006.218.07:41:59.23#ibcon#enter sib2, iclass 27, count 0 2006.218.07:41:59.23#ibcon#flushed, iclass 27, count 0 2006.218.07:41:59.23#ibcon#about to write, iclass 27, count 0 2006.218.07:41:59.23#ibcon#wrote, iclass 27, count 0 2006.218.07:41:59.23#ibcon#about to read 3, iclass 27, count 0 2006.218.07:41:59.26#ibcon#read 3, iclass 27, count 0 2006.218.07:41:59.26#ibcon#about to read 4, iclass 27, count 0 2006.218.07:41:59.26#ibcon#read 4, iclass 27, count 0 2006.218.07:41:59.26#ibcon#about to read 5, iclass 27, count 0 2006.218.07:41:59.26#ibcon#read 5, iclass 27, count 0 2006.218.07:41:59.26#ibcon#about to read 6, iclass 27, count 0 2006.218.07:41:59.26#ibcon#read 6, iclass 27, count 0 2006.218.07:41:59.26#ibcon#end of sib2, iclass 27, count 0 2006.218.07:41:59.26#ibcon#*after write, iclass 27, count 0 2006.218.07:41:59.26#ibcon#*before return 0, iclass 27, count 0 2006.218.07:41:59.26#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.218.07:41:59.26#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.218.07:41:59.26#ibcon#about to clear, iclass 27 cls_cnt 0 2006.218.07:41:59.26#ibcon#cleared, iclass 27 cls_cnt 0 2006.218.07:41:59.26$vc4f8/valo=5,652.99 2006.218.07:41:59.26#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.218.07:41:59.26#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.218.07:41:59.26#ibcon#ireg 17 cls_cnt 0 2006.218.07:41:59.26#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.218.07:41:59.26#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.218.07:41:59.26#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.218.07:41:59.26#ibcon#enter wrdev, iclass 29, count 0 2006.218.07:41:59.26#ibcon#first serial, iclass 29, count 0 2006.218.07:41:59.26#ibcon#enter sib2, iclass 29, count 0 2006.218.07:41:59.26#ibcon#flushed, iclass 29, count 0 2006.218.07:41:59.26#ibcon#about to write, iclass 29, count 0 2006.218.07:41:59.26#ibcon#wrote, iclass 29, count 0 2006.218.07:41:59.26#ibcon#about to read 3, iclass 29, count 0 2006.218.07:41:59.28#ibcon#read 3, iclass 29, count 0 2006.218.07:41:59.28#ibcon#about to read 4, iclass 29, count 0 2006.218.07:41:59.28#ibcon#read 4, iclass 29, count 0 2006.218.07:41:59.28#ibcon#about to read 5, iclass 29, count 0 2006.218.07:41:59.28#ibcon#read 5, iclass 29, count 0 2006.218.07:41:59.28#ibcon#about to read 6, iclass 29, count 0 2006.218.07:41:59.28#ibcon#read 6, iclass 29, count 0 2006.218.07:41:59.28#ibcon#end of sib2, iclass 29, count 0 2006.218.07:41:59.28#ibcon#*mode == 0, iclass 29, count 0 2006.218.07:41:59.28#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.218.07:41:59.28#ibcon#[26=FRQ=05,652.99\r\n] 2006.218.07:41:59.28#ibcon#*before write, iclass 29, count 0 2006.218.07:41:59.28#ibcon#enter sib2, iclass 29, count 0 2006.218.07:41:59.28#ibcon#flushed, iclass 29, count 0 2006.218.07:41:59.28#ibcon#about to write, iclass 29, count 0 2006.218.07:41:59.28#ibcon#wrote, iclass 29, count 0 2006.218.07:41:59.28#ibcon#about to read 3, iclass 29, count 0 2006.218.07:41:59.32#ibcon#read 3, iclass 29, count 0 2006.218.07:41:59.32#ibcon#about to read 4, iclass 29, count 0 2006.218.07:41:59.32#ibcon#read 4, iclass 29, count 0 2006.218.07:41:59.32#ibcon#about to read 5, iclass 29, count 0 2006.218.07:41:59.32#ibcon#read 5, iclass 29, count 0 2006.218.07:41:59.32#ibcon#about to read 6, iclass 29, count 0 2006.218.07:41:59.32#ibcon#read 6, iclass 29, count 0 2006.218.07:41:59.32#ibcon#end of sib2, iclass 29, count 0 2006.218.07:41:59.32#ibcon#*after write, iclass 29, count 0 2006.218.07:41:59.32#ibcon#*before return 0, iclass 29, count 0 2006.218.07:41:59.32#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.218.07:41:59.32#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.218.07:41:59.32#ibcon#about to clear, iclass 29 cls_cnt 0 2006.218.07:41:59.32#ibcon#cleared, iclass 29 cls_cnt 0 2006.218.07:41:59.32$vc4f8/va=5,7 2006.218.07:41:59.32#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.218.07:41:59.32#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.218.07:41:59.32#ibcon#ireg 11 cls_cnt 2 2006.218.07:41:59.32#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.218.07:41:59.38#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.218.07:41:59.38#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.218.07:41:59.38#ibcon#enter wrdev, iclass 31, count 2 2006.218.07:41:59.38#ibcon#first serial, iclass 31, count 2 2006.218.07:41:59.38#ibcon#enter sib2, iclass 31, count 2 2006.218.07:41:59.38#ibcon#flushed, iclass 31, count 2 2006.218.07:41:59.38#ibcon#about to write, iclass 31, count 2 2006.218.07:41:59.38#ibcon#wrote, iclass 31, count 2 2006.218.07:41:59.38#ibcon#about to read 3, iclass 31, count 2 2006.218.07:41:59.40#ibcon#read 3, iclass 31, count 2 2006.218.07:41:59.40#ibcon#about to read 4, iclass 31, count 2 2006.218.07:41:59.40#ibcon#read 4, iclass 31, count 2 2006.218.07:41:59.40#ibcon#about to read 5, iclass 31, count 2 2006.218.07:41:59.40#ibcon#read 5, iclass 31, count 2 2006.218.07:41:59.40#ibcon#about to read 6, iclass 31, count 2 2006.218.07:41:59.40#ibcon#read 6, iclass 31, count 2 2006.218.07:41:59.40#ibcon#end of sib2, iclass 31, count 2 2006.218.07:41:59.40#ibcon#*mode == 0, iclass 31, count 2 2006.218.07:41:59.40#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.218.07:41:59.40#ibcon#[25=AT05-07\r\n] 2006.218.07:41:59.40#ibcon#*before write, iclass 31, count 2 2006.218.07:41:59.40#ibcon#enter sib2, iclass 31, count 2 2006.218.07:41:59.40#ibcon#flushed, iclass 31, count 2 2006.218.07:41:59.40#ibcon#about to write, iclass 31, count 2 2006.218.07:41:59.40#ibcon#wrote, iclass 31, count 2 2006.218.07:41:59.40#ibcon#about to read 3, iclass 31, count 2 2006.218.07:41:59.44#ibcon#read 3, iclass 31, count 2 2006.218.07:41:59.44#ibcon#about to read 4, iclass 31, count 2 2006.218.07:41:59.44#ibcon#read 4, iclass 31, count 2 2006.218.07:41:59.44#ibcon#about to read 5, iclass 31, count 2 2006.218.07:41:59.44#ibcon#read 5, iclass 31, count 2 2006.218.07:41:59.44#ibcon#about to read 6, iclass 31, count 2 2006.218.07:41:59.44#ibcon#read 6, iclass 31, count 2 2006.218.07:41:59.44#ibcon#end of sib2, iclass 31, count 2 2006.218.07:41:59.44#ibcon#*after write, iclass 31, count 2 2006.218.07:41:59.44#ibcon#*before return 0, iclass 31, count 2 2006.218.07:41:59.44#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.218.07:41:59.44#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.218.07:41:59.44#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.218.07:41:59.44#ibcon#ireg 7 cls_cnt 0 2006.218.07:41:59.44#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.218.07:41:59.56#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.218.07:41:59.56#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.218.07:41:59.56#ibcon#enter wrdev, iclass 31, count 0 2006.218.07:41:59.56#ibcon#first serial, iclass 31, count 0 2006.218.07:41:59.56#ibcon#enter sib2, iclass 31, count 0 2006.218.07:41:59.56#ibcon#flushed, iclass 31, count 0 2006.218.07:41:59.56#ibcon#about to write, iclass 31, count 0 2006.218.07:41:59.56#ibcon#wrote, iclass 31, count 0 2006.218.07:41:59.56#ibcon#about to read 3, iclass 31, count 0 2006.218.07:41:59.58#ibcon#read 3, iclass 31, count 0 2006.218.07:41:59.58#ibcon#about to read 4, iclass 31, count 0 2006.218.07:41:59.58#ibcon#read 4, iclass 31, count 0 2006.218.07:41:59.58#ibcon#about to read 5, iclass 31, count 0 2006.218.07:41:59.58#ibcon#read 5, iclass 31, count 0 2006.218.07:41:59.58#ibcon#about to read 6, iclass 31, count 0 2006.218.07:41:59.58#ibcon#read 6, iclass 31, count 0 2006.218.07:41:59.58#ibcon#end of sib2, iclass 31, count 0 2006.218.07:41:59.58#ibcon#*mode == 0, iclass 31, count 0 2006.218.07:41:59.58#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.218.07:41:59.58#ibcon#[25=USB\r\n] 2006.218.07:41:59.58#ibcon#*before write, iclass 31, count 0 2006.218.07:41:59.58#ibcon#enter sib2, iclass 31, count 0 2006.218.07:41:59.58#ibcon#flushed, iclass 31, count 0 2006.218.07:41:59.58#ibcon#about to write, iclass 31, count 0 2006.218.07:41:59.58#ibcon#wrote, iclass 31, count 0 2006.218.07:41:59.58#ibcon#about to read 3, iclass 31, count 0 2006.218.07:41:59.61#ibcon#read 3, iclass 31, count 0 2006.218.07:41:59.61#ibcon#about to read 4, iclass 31, count 0 2006.218.07:41:59.61#ibcon#read 4, iclass 31, count 0 2006.218.07:41:59.61#ibcon#about to read 5, iclass 31, count 0 2006.218.07:41:59.61#ibcon#read 5, iclass 31, count 0 2006.218.07:41:59.61#ibcon#about to read 6, iclass 31, count 0 2006.218.07:41:59.61#ibcon#read 6, iclass 31, count 0 2006.218.07:41:59.61#ibcon#end of sib2, iclass 31, count 0 2006.218.07:41:59.61#ibcon#*after write, iclass 31, count 0 2006.218.07:41:59.61#ibcon#*before return 0, iclass 31, count 0 2006.218.07:41:59.61#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.218.07:41:59.61#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.218.07:41:59.61#ibcon#about to clear, iclass 31 cls_cnt 0 2006.218.07:41:59.61#ibcon#cleared, iclass 31 cls_cnt 0 2006.218.07:41:59.61$vc4f8/valo=6,772.99 2006.218.07:41:59.61#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.218.07:41:59.61#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.218.07:41:59.61#ibcon#ireg 17 cls_cnt 0 2006.218.07:41:59.61#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.218.07:41:59.61#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.218.07:41:59.61#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.218.07:41:59.61#ibcon#enter wrdev, iclass 33, count 0 2006.218.07:41:59.61#ibcon#first serial, iclass 33, count 0 2006.218.07:41:59.61#ibcon#enter sib2, iclass 33, count 0 2006.218.07:41:59.61#ibcon#flushed, iclass 33, count 0 2006.218.07:41:59.61#ibcon#about to write, iclass 33, count 0 2006.218.07:41:59.61#ibcon#wrote, iclass 33, count 0 2006.218.07:41:59.61#ibcon#about to read 3, iclass 33, count 0 2006.218.07:41:59.63#ibcon#read 3, iclass 33, count 0 2006.218.07:41:59.63#ibcon#about to read 4, iclass 33, count 0 2006.218.07:41:59.63#ibcon#read 4, iclass 33, count 0 2006.218.07:41:59.63#ibcon#about to read 5, iclass 33, count 0 2006.218.07:41:59.63#ibcon#read 5, iclass 33, count 0 2006.218.07:41:59.63#ibcon#about to read 6, iclass 33, count 0 2006.218.07:41:59.63#ibcon#read 6, iclass 33, count 0 2006.218.07:41:59.63#ibcon#end of sib2, iclass 33, count 0 2006.218.07:41:59.63#ibcon#*mode == 0, iclass 33, count 0 2006.218.07:41:59.63#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.218.07:41:59.63#ibcon#[26=FRQ=06,772.99\r\n] 2006.218.07:41:59.63#ibcon#*before write, iclass 33, count 0 2006.218.07:41:59.63#ibcon#enter sib2, iclass 33, count 0 2006.218.07:41:59.63#ibcon#flushed, iclass 33, count 0 2006.218.07:41:59.63#ibcon#about to write, iclass 33, count 0 2006.218.07:41:59.63#ibcon#wrote, iclass 33, count 0 2006.218.07:41:59.63#ibcon#about to read 3, iclass 33, count 0 2006.218.07:41:59.67#ibcon#read 3, iclass 33, count 0 2006.218.07:41:59.67#ibcon#about to read 4, iclass 33, count 0 2006.218.07:41:59.67#ibcon#read 4, iclass 33, count 0 2006.218.07:41:59.67#ibcon#about to read 5, iclass 33, count 0 2006.218.07:41:59.67#ibcon#read 5, iclass 33, count 0 2006.218.07:41:59.67#ibcon#about to read 6, iclass 33, count 0 2006.218.07:41:59.67#ibcon#read 6, iclass 33, count 0 2006.218.07:41:59.67#ibcon#end of sib2, iclass 33, count 0 2006.218.07:41:59.67#ibcon#*after write, iclass 33, count 0 2006.218.07:41:59.67#ibcon#*before return 0, iclass 33, count 0 2006.218.07:41:59.67#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.218.07:41:59.67#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.218.07:41:59.67#ibcon#about to clear, iclass 33 cls_cnt 0 2006.218.07:41:59.67#ibcon#cleared, iclass 33 cls_cnt 0 2006.218.07:41:59.67$vc4f8/va=6,6 2006.218.07:41:59.67#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.218.07:41:59.67#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.218.07:41:59.67#ibcon#ireg 11 cls_cnt 2 2006.218.07:41:59.67#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.218.07:41:59.73#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.218.07:41:59.73#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.218.07:41:59.73#ibcon#enter wrdev, iclass 35, count 2 2006.218.07:41:59.73#ibcon#first serial, iclass 35, count 2 2006.218.07:41:59.73#ibcon#enter sib2, iclass 35, count 2 2006.218.07:41:59.73#ibcon#flushed, iclass 35, count 2 2006.218.07:41:59.73#ibcon#about to write, iclass 35, count 2 2006.218.07:41:59.73#ibcon#wrote, iclass 35, count 2 2006.218.07:41:59.73#ibcon#about to read 3, iclass 35, count 2 2006.218.07:41:59.75#ibcon#read 3, iclass 35, count 2 2006.218.07:41:59.75#ibcon#about to read 4, iclass 35, count 2 2006.218.07:41:59.75#ibcon#read 4, iclass 35, count 2 2006.218.07:41:59.75#ibcon#about to read 5, iclass 35, count 2 2006.218.07:41:59.75#ibcon#read 5, iclass 35, count 2 2006.218.07:41:59.75#ibcon#about to read 6, iclass 35, count 2 2006.218.07:41:59.75#ibcon#read 6, iclass 35, count 2 2006.218.07:41:59.75#ibcon#end of sib2, iclass 35, count 2 2006.218.07:41:59.75#ibcon#*mode == 0, iclass 35, count 2 2006.218.07:41:59.75#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.218.07:41:59.75#ibcon#[25=AT06-06\r\n] 2006.218.07:41:59.75#ibcon#*before write, iclass 35, count 2 2006.218.07:41:59.75#ibcon#enter sib2, iclass 35, count 2 2006.218.07:41:59.75#ibcon#flushed, iclass 35, count 2 2006.218.07:41:59.75#ibcon#about to write, iclass 35, count 2 2006.218.07:41:59.75#ibcon#wrote, iclass 35, count 2 2006.218.07:41:59.75#ibcon#about to read 3, iclass 35, count 2 2006.218.07:41:59.78#ibcon#read 3, iclass 35, count 2 2006.218.07:41:59.78#ibcon#about to read 4, iclass 35, count 2 2006.218.07:41:59.78#ibcon#read 4, iclass 35, count 2 2006.218.07:41:59.78#ibcon#about to read 5, iclass 35, count 2 2006.218.07:41:59.78#ibcon#read 5, iclass 35, count 2 2006.218.07:41:59.78#ibcon#about to read 6, iclass 35, count 2 2006.218.07:41:59.78#ibcon#read 6, iclass 35, count 2 2006.218.07:41:59.78#ibcon#end of sib2, iclass 35, count 2 2006.218.07:41:59.78#ibcon#*after write, iclass 35, count 2 2006.218.07:41:59.78#ibcon#*before return 0, iclass 35, count 2 2006.218.07:41:59.78#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.218.07:41:59.78#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.218.07:41:59.78#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.218.07:41:59.78#ibcon#ireg 7 cls_cnt 0 2006.218.07:41:59.78#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.218.07:41:59.90#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.218.07:41:59.90#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.218.07:41:59.90#ibcon#enter wrdev, iclass 35, count 0 2006.218.07:41:59.90#ibcon#first serial, iclass 35, count 0 2006.218.07:41:59.90#ibcon#enter sib2, iclass 35, count 0 2006.218.07:41:59.90#ibcon#flushed, iclass 35, count 0 2006.218.07:41:59.90#ibcon#about to write, iclass 35, count 0 2006.218.07:41:59.90#ibcon#wrote, iclass 35, count 0 2006.218.07:41:59.90#ibcon#about to read 3, iclass 35, count 0 2006.218.07:41:59.92#ibcon#read 3, iclass 35, count 0 2006.218.07:41:59.92#ibcon#about to read 4, iclass 35, count 0 2006.218.07:41:59.92#ibcon#read 4, iclass 35, count 0 2006.218.07:41:59.92#ibcon#about to read 5, iclass 35, count 0 2006.218.07:41:59.92#ibcon#read 5, iclass 35, count 0 2006.218.07:41:59.92#ibcon#about to read 6, iclass 35, count 0 2006.218.07:41:59.92#ibcon#read 6, iclass 35, count 0 2006.218.07:41:59.92#ibcon#end of sib2, iclass 35, count 0 2006.218.07:41:59.92#ibcon#*mode == 0, iclass 35, count 0 2006.218.07:41:59.92#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.218.07:41:59.92#ibcon#[25=USB\r\n] 2006.218.07:41:59.92#ibcon#*before write, iclass 35, count 0 2006.218.07:41:59.92#ibcon#enter sib2, iclass 35, count 0 2006.218.07:41:59.92#ibcon#flushed, iclass 35, count 0 2006.218.07:41:59.92#ibcon#about to write, iclass 35, count 0 2006.218.07:41:59.92#ibcon#wrote, iclass 35, count 0 2006.218.07:41:59.92#ibcon#about to read 3, iclass 35, count 0 2006.218.07:41:59.95#ibcon#read 3, iclass 35, count 0 2006.218.07:41:59.95#ibcon#about to read 4, iclass 35, count 0 2006.218.07:41:59.95#ibcon#read 4, iclass 35, count 0 2006.218.07:41:59.95#ibcon#about to read 5, iclass 35, count 0 2006.218.07:41:59.95#ibcon#read 5, iclass 35, count 0 2006.218.07:41:59.95#ibcon#about to read 6, iclass 35, count 0 2006.218.07:41:59.95#ibcon#read 6, iclass 35, count 0 2006.218.07:41:59.95#ibcon#end of sib2, iclass 35, count 0 2006.218.07:41:59.95#ibcon#*after write, iclass 35, count 0 2006.218.07:41:59.95#ibcon#*before return 0, iclass 35, count 0 2006.218.07:41:59.95#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.218.07:41:59.95#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.218.07:41:59.95#ibcon#about to clear, iclass 35 cls_cnt 0 2006.218.07:41:59.95#ibcon#cleared, iclass 35 cls_cnt 0 2006.218.07:41:59.95$vc4f8/valo=7,832.99 2006.218.07:41:59.95#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.218.07:41:59.95#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.218.07:41:59.95#ibcon#ireg 17 cls_cnt 0 2006.218.07:41:59.95#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.218.07:41:59.95#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.218.07:41:59.95#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.218.07:41:59.95#ibcon#enter wrdev, iclass 37, count 0 2006.218.07:41:59.95#ibcon#first serial, iclass 37, count 0 2006.218.07:41:59.95#ibcon#enter sib2, iclass 37, count 0 2006.218.07:41:59.95#ibcon#flushed, iclass 37, count 0 2006.218.07:41:59.95#ibcon#about to write, iclass 37, count 0 2006.218.07:41:59.95#ibcon#wrote, iclass 37, count 0 2006.218.07:41:59.95#ibcon#about to read 3, iclass 37, count 0 2006.218.07:41:59.97#ibcon#read 3, iclass 37, count 0 2006.218.07:41:59.97#ibcon#about to read 4, iclass 37, count 0 2006.218.07:41:59.97#ibcon#read 4, iclass 37, count 0 2006.218.07:41:59.97#ibcon#about to read 5, iclass 37, count 0 2006.218.07:41:59.97#ibcon#read 5, iclass 37, count 0 2006.218.07:41:59.97#ibcon#about to read 6, iclass 37, count 0 2006.218.07:41:59.97#ibcon#read 6, iclass 37, count 0 2006.218.07:41:59.97#ibcon#end of sib2, iclass 37, count 0 2006.218.07:41:59.97#ibcon#*mode == 0, iclass 37, count 0 2006.218.07:41:59.97#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.218.07:41:59.97#ibcon#[26=FRQ=07,832.99\r\n] 2006.218.07:41:59.97#ibcon#*before write, iclass 37, count 0 2006.218.07:41:59.97#ibcon#enter sib2, iclass 37, count 0 2006.218.07:41:59.97#ibcon#flushed, iclass 37, count 0 2006.218.07:41:59.97#ibcon#about to write, iclass 37, count 0 2006.218.07:41:59.97#ibcon#wrote, iclass 37, count 0 2006.218.07:41:59.97#ibcon#about to read 3, iclass 37, count 0 2006.218.07:42:00.01#ibcon#read 3, iclass 37, count 0 2006.218.07:42:00.01#ibcon#about to read 4, iclass 37, count 0 2006.218.07:42:00.01#ibcon#read 4, iclass 37, count 0 2006.218.07:42:00.01#ibcon#about to read 5, iclass 37, count 0 2006.218.07:42:00.01#ibcon#read 5, iclass 37, count 0 2006.218.07:42:00.01#ibcon#about to read 6, iclass 37, count 0 2006.218.07:42:00.01#ibcon#read 6, iclass 37, count 0 2006.218.07:42:00.01#ibcon#end of sib2, iclass 37, count 0 2006.218.07:42:00.01#ibcon#*after write, iclass 37, count 0 2006.218.07:42:00.01#ibcon#*before return 0, iclass 37, count 0 2006.218.07:42:00.01#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.218.07:42:00.01#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.218.07:42:00.01#ibcon#about to clear, iclass 37 cls_cnt 0 2006.218.07:42:00.01#ibcon#cleared, iclass 37 cls_cnt 0 2006.218.07:42:00.01$vc4f8/va=7,6 2006.218.07:42:00.01#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.218.07:42:00.01#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.218.07:42:00.01#ibcon#ireg 11 cls_cnt 2 2006.218.07:42:00.01#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.218.07:42:00.07#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.218.07:42:00.07#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.218.07:42:00.07#ibcon#enter wrdev, iclass 39, count 2 2006.218.07:42:00.07#ibcon#first serial, iclass 39, count 2 2006.218.07:42:00.07#ibcon#enter sib2, iclass 39, count 2 2006.218.07:42:00.07#ibcon#flushed, iclass 39, count 2 2006.218.07:42:00.07#ibcon#about to write, iclass 39, count 2 2006.218.07:42:00.07#ibcon#wrote, iclass 39, count 2 2006.218.07:42:00.07#ibcon#about to read 3, iclass 39, count 2 2006.218.07:42:00.09#ibcon#read 3, iclass 39, count 2 2006.218.07:42:00.09#ibcon#about to read 4, iclass 39, count 2 2006.218.07:42:00.09#ibcon#read 4, iclass 39, count 2 2006.218.07:42:00.09#ibcon#about to read 5, iclass 39, count 2 2006.218.07:42:00.09#ibcon#read 5, iclass 39, count 2 2006.218.07:42:00.09#ibcon#about to read 6, iclass 39, count 2 2006.218.07:42:00.09#ibcon#read 6, iclass 39, count 2 2006.218.07:42:00.09#ibcon#end of sib2, iclass 39, count 2 2006.218.07:42:00.09#ibcon#*mode == 0, iclass 39, count 2 2006.218.07:42:00.09#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.218.07:42:00.09#ibcon#[25=AT07-06\r\n] 2006.218.07:42:00.09#ibcon#*before write, iclass 39, count 2 2006.218.07:42:00.09#ibcon#enter sib2, iclass 39, count 2 2006.218.07:42:00.09#ibcon#flushed, iclass 39, count 2 2006.218.07:42:00.09#ibcon#about to write, iclass 39, count 2 2006.218.07:42:00.09#ibcon#wrote, iclass 39, count 2 2006.218.07:42:00.09#ibcon#about to read 3, iclass 39, count 2 2006.218.07:42:00.12#ibcon#read 3, iclass 39, count 2 2006.218.07:42:00.12#ibcon#about to read 4, iclass 39, count 2 2006.218.07:42:00.12#ibcon#read 4, iclass 39, count 2 2006.218.07:42:00.12#ibcon#about to read 5, iclass 39, count 2 2006.218.07:42:00.12#ibcon#read 5, iclass 39, count 2 2006.218.07:42:00.12#ibcon#about to read 6, iclass 39, count 2 2006.218.07:42:00.12#ibcon#read 6, iclass 39, count 2 2006.218.07:42:00.12#ibcon#end of sib2, iclass 39, count 2 2006.218.07:42:00.12#ibcon#*after write, iclass 39, count 2 2006.218.07:42:00.12#ibcon#*before return 0, iclass 39, count 2 2006.218.07:42:00.12#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.218.07:42:00.12#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.218.07:42:00.12#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.218.07:42:00.12#ibcon#ireg 7 cls_cnt 0 2006.218.07:42:00.12#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.218.07:42:00.24#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.218.07:42:00.24#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.218.07:42:00.24#ibcon#enter wrdev, iclass 39, count 0 2006.218.07:42:00.24#ibcon#first serial, iclass 39, count 0 2006.218.07:42:00.24#ibcon#enter sib2, iclass 39, count 0 2006.218.07:42:00.24#ibcon#flushed, iclass 39, count 0 2006.218.07:42:00.24#ibcon#about to write, iclass 39, count 0 2006.218.07:42:00.24#ibcon#wrote, iclass 39, count 0 2006.218.07:42:00.24#ibcon#about to read 3, iclass 39, count 0 2006.218.07:42:00.26#ibcon#read 3, iclass 39, count 0 2006.218.07:42:00.26#ibcon#about to read 4, iclass 39, count 0 2006.218.07:42:00.26#ibcon#read 4, iclass 39, count 0 2006.218.07:42:00.26#ibcon#about to read 5, iclass 39, count 0 2006.218.07:42:00.26#ibcon#read 5, iclass 39, count 0 2006.218.07:42:00.26#ibcon#about to read 6, iclass 39, count 0 2006.218.07:42:00.26#ibcon#read 6, iclass 39, count 0 2006.218.07:42:00.26#ibcon#end of sib2, iclass 39, count 0 2006.218.07:42:00.26#ibcon#*mode == 0, iclass 39, count 0 2006.218.07:42:00.26#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.218.07:42:00.26#ibcon#[25=USB\r\n] 2006.218.07:42:00.26#ibcon#*before write, iclass 39, count 0 2006.218.07:42:00.26#ibcon#enter sib2, iclass 39, count 0 2006.218.07:42:00.26#ibcon#flushed, iclass 39, count 0 2006.218.07:42:00.26#ibcon#about to write, iclass 39, count 0 2006.218.07:42:00.26#ibcon#wrote, iclass 39, count 0 2006.218.07:42:00.26#ibcon#about to read 3, iclass 39, count 0 2006.218.07:42:00.29#ibcon#read 3, iclass 39, count 0 2006.218.07:42:00.29#ibcon#about to read 4, iclass 39, count 0 2006.218.07:42:00.29#ibcon#read 4, iclass 39, count 0 2006.218.07:42:00.29#ibcon#about to read 5, iclass 39, count 0 2006.218.07:42:00.29#ibcon#read 5, iclass 39, count 0 2006.218.07:42:00.29#ibcon#about to read 6, iclass 39, count 0 2006.218.07:42:00.29#ibcon#read 6, iclass 39, count 0 2006.218.07:42:00.29#ibcon#end of sib2, iclass 39, count 0 2006.218.07:42:00.29#ibcon#*after write, iclass 39, count 0 2006.218.07:42:00.29#ibcon#*before return 0, iclass 39, count 0 2006.218.07:42:00.29#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.218.07:42:00.29#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.218.07:42:00.29#ibcon#about to clear, iclass 39 cls_cnt 0 2006.218.07:42:00.29#ibcon#cleared, iclass 39 cls_cnt 0 2006.218.07:42:00.29$vc4f8/valo=8,852.99 2006.218.07:42:00.29#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.218.07:42:00.29#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.218.07:42:00.29#ibcon#ireg 17 cls_cnt 0 2006.218.07:42:00.29#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.218.07:42:00.29#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.218.07:42:00.29#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.218.07:42:00.29#ibcon#enter wrdev, iclass 3, count 0 2006.218.07:42:00.29#ibcon#first serial, iclass 3, count 0 2006.218.07:42:00.29#ibcon#enter sib2, iclass 3, count 0 2006.218.07:42:00.29#ibcon#flushed, iclass 3, count 0 2006.218.07:42:00.29#ibcon#about to write, iclass 3, count 0 2006.218.07:42:00.29#ibcon#wrote, iclass 3, count 0 2006.218.07:42:00.29#ibcon#about to read 3, iclass 3, count 0 2006.218.07:42:00.31#ibcon#read 3, iclass 3, count 0 2006.218.07:42:00.31#ibcon#about to read 4, iclass 3, count 0 2006.218.07:42:00.31#ibcon#read 4, iclass 3, count 0 2006.218.07:42:00.31#ibcon#about to read 5, iclass 3, count 0 2006.218.07:42:00.31#ibcon#read 5, iclass 3, count 0 2006.218.07:42:00.31#ibcon#about to read 6, iclass 3, count 0 2006.218.07:42:00.31#ibcon#read 6, iclass 3, count 0 2006.218.07:42:00.31#ibcon#end of sib2, iclass 3, count 0 2006.218.07:42:00.31#ibcon#*mode == 0, iclass 3, count 0 2006.218.07:42:00.31#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.218.07:42:00.31#ibcon#[26=FRQ=08,852.99\r\n] 2006.218.07:42:00.31#ibcon#*before write, iclass 3, count 0 2006.218.07:42:00.31#ibcon#enter sib2, iclass 3, count 0 2006.218.07:42:00.31#ibcon#flushed, iclass 3, count 0 2006.218.07:42:00.31#ibcon#about to write, iclass 3, count 0 2006.218.07:42:00.31#ibcon#wrote, iclass 3, count 0 2006.218.07:42:00.31#ibcon#about to read 3, iclass 3, count 0 2006.218.07:42:00.36#ibcon#read 3, iclass 3, count 0 2006.218.07:42:00.36#ibcon#about to read 4, iclass 3, count 0 2006.218.07:42:00.36#ibcon#read 4, iclass 3, count 0 2006.218.07:42:00.36#ibcon#about to read 5, iclass 3, count 0 2006.218.07:42:00.36#ibcon#read 5, iclass 3, count 0 2006.218.07:42:00.36#ibcon#about to read 6, iclass 3, count 0 2006.218.07:42:00.36#ibcon#read 6, iclass 3, count 0 2006.218.07:42:00.36#ibcon#end of sib2, iclass 3, count 0 2006.218.07:42:00.36#ibcon#*after write, iclass 3, count 0 2006.218.07:42:00.36#ibcon#*before return 0, iclass 3, count 0 2006.218.07:42:00.36#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.218.07:42:00.36#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.218.07:42:00.36#ibcon#about to clear, iclass 3 cls_cnt 0 2006.218.07:42:00.36#ibcon#cleared, iclass 3 cls_cnt 0 2006.218.07:42:00.36$vc4f8/va=8,7 2006.218.07:42:00.36#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.218.07:42:00.36#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.218.07:42:00.36#ibcon#ireg 11 cls_cnt 2 2006.218.07:42:00.36#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.218.07:42:00.41#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.218.07:42:00.41#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.218.07:42:00.41#ibcon#enter wrdev, iclass 5, count 2 2006.218.07:42:00.41#ibcon#first serial, iclass 5, count 2 2006.218.07:42:00.41#ibcon#enter sib2, iclass 5, count 2 2006.218.07:42:00.41#ibcon#flushed, iclass 5, count 2 2006.218.07:42:00.41#ibcon#about to write, iclass 5, count 2 2006.218.07:42:00.41#ibcon#wrote, iclass 5, count 2 2006.218.07:42:00.41#ibcon#about to read 3, iclass 5, count 2 2006.218.07:42:00.43#ibcon#read 3, iclass 5, count 2 2006.218.07:42:00.43#ibcon#about to read 4, iclass 5, count 2 2006.218.07:42:00.43#ibcon#read 4, iclass 5, count 2 2006.218.07:42:00.43#ibcon#about to read 5, iclass 5, count 2 2006.218.07:42:00.43#ibcon#read 5, iclass 5, count 2 2006.218.07:42:00.43#ibcon#about to read 6, iclass 5, count 2 2006.218.07:42:00.43#ibcon#read 6, iclass 5, count 2 2006.218.07:42:00.43#ibcon#end of sib2, iclass 5, count 2 2006.218.07:42:00.43#ibcon#*mode == 0, iclass 5, count 2 2006.218.07:42:00.43#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.218.07:42:00.43#ibcon#[25=AT08-07\r\n] 2006.218.07:42:00.43#ibcon#*before write, iclass 5, count 2 2006.218.07:42:00.43#ibcon#enter sib2, iclass 5, count 2 2006.218.07:42:00.43#ibcon#flushed, iclass 5, count 2 2006.218.07:42:00.43#ibcon#about to write, iclass 5, count 2 2006.218.07:42:00.43#ibcon#wrote, iclass 5, count 2 2006.218.07:42:00.43#ibcon#about to read 3, iclass 5, count 2 2006.218.07:42:00.46#ibcon#read 3, iclass 5, count 2 2006.218.07:42:00.46#ibcon#about to read 4, iclass 5, count 2 2006.218.07:42:00.46#ibcon#read 4, iclass 5, count 2 2006.218.07:42:00.46#ibcon#about to read 5, iclass 5, count 2 2006.218.07:42:00.46#ibcon#read 5, iclass 5, count 2 2006.218.07:42:00.46#ibcon#about to read 6, iclass 5, count 2 2006.218.07:42:00.46#ibcon#read 6, iclass 5, count 2 2006.218.07:42:00.46#ibcon#end of sib2, iclass 5, count 2 2006.218.07:42:00.46#ibcon#*after write, iclass 5, count 2 2006.218.07:42:00.46#ibcon#*before return 0, iclass 5, count 2 2006.218.07:42:00.46#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.218.07:42:00.46#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.218.07:42:00.46#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.218.07:42:00.46#ibcon#ireg 7 cls_cnt 0 2006.218.07:42:00.46#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.218.07:42:00.58#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.218.07:42:00.58#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.218.07:42:00.58#ibcon#enter wrdev, iclass 5, count 0 2006.218.07:42:00.58#ibcon#first serial, iclass 5, count 0 2006.218.07:42:00.58#ibcon#enter sib2, iclass 5, count 0 2006.218.07:42:00.58#ibcon#flushed, iclass 5, count 0 2006.218.07:42:00.58#ibcon#about to write, iclass 5, count 0 2006.218.07:42:00.58#ibcon#wrote, iclass 5, count 0 2006.218.07:42:00.58#ibcon#about to read 3, iclass 5, count 0 2006.218.07:42:00.60#ibcon#read 3, iclass 5, count 0 2006.218.07:42:00.60#ibcon#about to read 4, iclass 5, count 0 2006.218.07:42:00.60#ibcon#read 4, iclass 5, count 0 2006.218.07:42:00.60#ibcon#about to read 5, iclass 5, count 0 2006.218.07:42:00.60#ibcon#read 5, iclass 5, count 0 2006.218.07:42:00.60#ibcon#about to read 6, iclass 5, count 0 2006.218.07:42:00.60#ibcon#read 6, iclass 5, count 0 2006.218.07:42:00.60#ibcon#end of sib2, iclass 5, count 0 2006.218.07:42:00.60#ibcon#*mode == 0, iclass 5, count 0 2006.218.07:42:00.60#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.218.07:42:00.60#ibcon#[25=USB\r\n] 2006.218.07:42:00.60#ibcon#*before write, iclass 5, count 0 2006.218.07:42:00.60#ibcon#enter sib2, iclass 5, count 0 2006.218.07:42:00.60#ibcon#flushed, iclass 5, count 0 2006.218.07:42:00.60#ibcon#about to write, iclass 5, count 0 2006.218.07:42:00.60#ibcon#wrote, iclass 5, count 0 2006.218.07:42:00.60#ibcon#about to read 3, iclass 5, count 0 2006.218.07:42:00.63#ibcon#read 3, iclass 5, count 0 2006.218.07:42:00.63#ibcon#about to read 4, iclass 5, count 0 2006.218.07:42:00.63#ibcon#read 4, iclass 5, count 0 2006.218.07:42:00.63#ibcon#about to read 5, iclass 5, count 0 2006.218.07:42:00.63#ibcon#read 5, iclass 5, count 0 2006.218.07:42:00.63#ibcon#about to read 6, iclass 5, count 0 2006.218.07:42:00.63#ibcon#read 6, iclass 5, count 0 2006.218.07:42:00.63#ibcon#end of sib2, iclass 5, count 0 2006.218.07:42:00.63#ibcon#*after write, iclass 5, count 0 2006.218.07:42:00.63#ibcon#*before return 0, iclass 5, count 0 2006.218.07:42:00.63#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.218.07:42:00.63#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.218.07:42:00.63#ibcon#about to clear, iclass 5 cls_cnt 0 2006.218.07:42:00.63#ibcon#cleared, iclass 5 cls_cnt 0 2006.218.07:42:00.63$vc4f8/vblo=1,632.99 2006.218.07:42:00.63#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.218.07:42:00.63#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.218.07:42:00.63#ibcon#ireg 17 cls_cnt 0 2006.218.07:42:00.63#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.218.07:42:00.63#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.218.07:42:00.63#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.218.07:42:00.63#ibcon#enter wrdev, iclass 7, count 0 2006.218.07:42:00.63#ibcon#first serial, iclass 7, count 0 2006.218.07:42:00.63#ibcon#enter sib2, iclass 7, count 0 2006.218.07:42:00.63#ibcon#flushed, iclass 7, count 0 2006.218.07:42:00.63#ibcon#about to write, iclass 7, count 0 2006.218.07:42:00.63#ibcon#wrote, iclass 7, count 0 2006.218.07:42:00.63#ibcon#about to read 3, iclass 7, count 0 2006.218.07:42:00.65#ibcon#read 3, iclass 7, count 0 2006.218.07:42:00.65#ibcon#about to read 4, iclass 7, count 0 2006.218.07:42:00.65#ibcon#read 4, iclass 7, count 0 2006.218.07:42:00.65#ibcon#about to read 5, iclass 7, count 0 2006.218.07:42:00.65#ibcon#read 5, iclass 7, count 0 2006.218.07:42:00.65#ibcon#about to read 6, iclass 7, count 0 2006.218.07:42:00.65#ibcon#read 6, iclass 7, count 0 2006.218.07:42:00.65#ibcon#end of sib2, iclass 7, count 0 2006.218.07:42:00.65#ibcon#*mode == 0, iclass 7, count 0 2006.218.07:42:00.65#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.218.07:42:00.65#ibcon#[28=FRQ=01,632.99\r\n] 2006.218.07:42:00.65#ibcon#*before write, iclass 7, count 0 2006.218.07:42:00.65#ibcon#enter sib2, iclass 7, count 0 2006.218.07:42:00.65#ibcon#flushed, iclass 7, count 0 2006.218.07:42:00.65#ibcon#about to write, iclass 7, count 0 2006.218.07:42:00.65#ibcon#wrote, iclass 7, count 0 2006.218.07:42:00.65#ibcon#about to read 3, iclass 7, count 0 2006.218.07:42:00.69#ibcon#read 3, iclass 7, count 0 2006.218.07:42:00.69#ibcon#about to read 4, iclass 7, count 0 2006.218.07:42:00.69#ibcon#read 4, iclass 7, count 0 2006.218.07:42:00.69#ibcon#about to read 5, iclass 7, count 0 2006.218.07:42:00.69#ibcon#read 5, iclass 7, count 0 2006.218.07:42:00.69#ibcon#about to read 6, iclass 7, count 0 2006.218.07:42:00.69#ibcon#read 6, iclass 7, count 0 2006.218.07:42:00.69#ibcon#end of sib2, iclass 7, count 0 2006.218.07:42:00.69#ibcon#*after write, iclass 7, count 0 2006.218.07:42:00.69#ibcon#*before return 0, iclass 7, count 0 2006.218.07:42:00.69#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.218.07:42:00.69#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.218.07:42:00.69#ibcon#about to clear, iclass 7 cls_cnt 0 2006.218.07:42:00.69#ibcon#cleared, iclass 7 cls_cnt 0 2006.218.07:42:00.69$vc4f8/vb=1,4 2006.218.07:42:00.69#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.218.07:42:00.69#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.218.07:42:00.69#ibcon#ireg 11 cls_cnt 2 2006.218.07:42:00.69#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.218.07:42:00.69#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.218.07:42:00.69#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.218.07:42:00.69#ibcon#enter wrdev, iclass 11, count 2 2006.218.07:42:00.69#ibcon#first serial, iclass 11, count 2 2006.218.07:42:00.69#ibcon#enter sib2, iclass 11, count 2 2006.218.07:42:00.69#ibcon#flushed, iclass 11, count 2 2006.218.07:42:00.69#ibcon#about to write, iclass 11, count 2 2006.218.07:42:00.69#ibcon#wrote, iclass 11, count 2 2006.218.07:42:00.69#ibcon#about to read 3, iclass 11, count 2 2006.218.07:42:00.71#ibcon#read 3, iclass 11, count 2 2006.218.07:42:00.71#ibcon#about to read 4, iclass 11, count 2 2006.218.07:42:00.71#ibcon#read 4, iclass 11, count 2 2006.218.07:42:00.71#ibcon#about to read 5, iclass 11, count 2 2006.218.07:42:00.71#ibcon#read 5, iclass 11, count 2 2006.218.07:42:00.71#ibcon#about to read 6, iclass 11, count 2 2006.218.07:42:00.71#ibcon#read 6, iclass 11, count 2 2006.218.07:42:00.71#ibcon#end of sib2, iclass 11, count 2 2006.218.07:42:00.71#ibcon#*mode == 0, iclass 11, count 2 2006.218.07:42:00.71#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.218.07:42:00.71#ibcon#[27=AT01-04\r\n] 2006.218.07:42:00.71#ibcon#*before write, iclass 11, count 2 2006.218.07:42:00.71#ibcon#enter sib2, iclass 11, count 2 2006.218.07:42:00.71#ibcon#flushed, iclass 11, count 2 2006.218.07:42:00.71#ibcon#about to write, iclass 11, count 2 2006.218.07:42:00.71#ibcon#wrote, iclass 11, count 2 2006.218.07:42:00.71#ibcon#about to read 3, iclass 11, count 2 2006.218.07:42:00.74#ibcon#read 3, iclass 11, count 2 2006.218.07:42:00.74#ibcon#about to read 4, iclass 11, count 2 2006.218.07:42:00.74#ibcon#read 4, iclass 11, count 2 2006.218.07:42:00.74#ibcon#about to read 5, iclass 11, count 2 2006.218.07:42:00.74#ibcon#read 5, iclass 11, count 2 2006.218.07:42:00.74#ibcon#about to read 6, iclass 11, count 2 2006.218.07:42:00.74#ibcon#read 6, iclass 11, count 2 2006.218.07:42:00.74#ibcon#end of sib2, iclass 11, count 2 2006.218.07:42:00.74#ibcon#*after write, iclass 11, count 2 2006.218.07:42:00.74#ibcon#*before return 0, iclass 11, count 2 2006.218.07:42:00.74#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.218.07:42:00.74#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.218.07:42:00.74#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.218.07:42:00.74#ibcon#ireg 7 cls_cnt 0 2006.218.07:42:00.74#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.218.07:42:00.86#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.218.07:42:00.86#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.218.07:42:00.86#ibcon#enter wrdev, iclass 11, count 0 2006.218.07:42:00.86#ibcon#first serial, iclass 11, count 0 2006.218.07:42:00.86#ibcon#enter sib2, iclass 11, count 0 2006.218.07:42:00.86#ibcon#flushed, iclass 11, count 0 2006.218.07:42:00.86#ibcon#about to write, iclass 11, count 0 2006.218.07:42:00.86#ibcon#wrote, iclass 11, count 0 2006.218.07:42:00.86#ibcon#about to read 3, iclass 11, count 0 2006.218.07:42:00.88#ibcon#read 3, iclass 11, count 0 2006.218.07:42:00.88#ibcon#about to read 4, iclass 11, count 0 2006.218.07:42:00.88#ibcon#read 4, iclass 11, count 0 2006.218.07:42:00.88#ibcon#about to read 5, iclass 11, count 0 2006.218.07:42:00.88#ibcon#read 5, iclass 11, count 0 2006.218.07:42:00.88#ibcon#about to read 6, iclass 11, count 0 2006.218.07:42:00.88#ibcon#read 6, iclass 11, count 0 2006.218.07:42:00.88#ibcon#end of sib2, iclass 11, count 0 2006.218.07:42:00.88#ibcon#*mode == 0, iclass 11, count 0 2006.218.07:42:00.88#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.218.07:42:00.88#ibcon#[27=USB\r\n] 2006.218.07:42:00.88#ibcon#*before write, iclass 11, count 0 2006.218.07:42:00.88#ibcon#enter sib2, iclass 11, count 0 2006.218.07:42:00.88#ibcon#flushed, iclass 11, count 0 2006.218.07:42:00.88#ibcon#about to write, iclass 11, count 0 2006.218.07:42:00.88#ibcon#wrote, iclass 11, count 0 2006.218.07:42:00.88#ibcon#about to read 3, iclass 11, count 0 2006.218.07:42:00.91#ibcon#read 3, iclass 11, count 0 2006.218.07:42:00.91#ibcon#about to read 4, iclass 11, count 0 2006.218.07:42:00.91#ibcon#read 4, iclass 11, count 0 2006.218.07:42:00.91#ibcon#about to read 5, iclass 11, count 0 2006.218.07:42:00.91#ibcon#read 5, iclass 11, count 0 2006.218.07:42:00.91#ibcon#about to read 6, iclass 11, count 0 2006.218.07:42:00.91#ibcon#read 6, iclass 11, count 0 2006.218.07:42:00.91#ibcon#end of sib2, iclass 11, count 0 2006.218.07:42:00.91#ibcon#*after write, iclass 11, count 0 2006.218.07:42:00.91#ibcon#*before return 0, iclass 11, count 0 2006.218.07:42:00.91#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.218.07:42:00.91#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.218.07:42:00.91#ibcon#about to clear, iclass 11 cls_cnt 0 2006.218.07:42:00.91#ibcon#cleared, iclass 11 cls_cnt 0 2006.218.07:42:00.91$vc4f8/vblo=2,640.99 2006.218.07:42:00.91#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.218.07:42:00.91#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.218.07:42:00.91#ibcon#ireg 17 cls_cnt 0 2006.218.07:42:00.91#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.218.07:42:00.91#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.218.07:42:00.91#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.218.07:42:00.91#ibcon#enter wrdev, iclass 13, count 0 2006.218.07:42:00.91#ibcon#first serial, iclass 13, count 0 2006.218.07:42:00.91#ibcon#enter sib2, iclass 13, count 0 2006.218.07:42:00.91#ibcon#flushed, iclass 13, count 0 2006.218.07:42:00.91#ibcon#about to write, iclass 13, count 0 2006.218.07:42:00.91#ibcon#wrote, iclass 13, count 0 2006.218.07:42:00.91#ibcon#about to read 3, iclass 13, count 0 2006.218.07:42:00.93#ibcon#read 3, iclass 13, count 0 2006.218.07:42:00.93#ibcon#about to read 4, iclass 13, count 0 2006.218.07:42:00.93#ibcon#read 4, iclass 13, count 0 2006.218.07:42:00.93#ibcon#about to read 5, iclass 13, count 0 2006.218.07:42:00.93#ibcon#read 5, iclass 13, count 0 2006.218.07:42:00.93#ibcon#about to read 6, iclass 13, count 0 2006.218.07:42:00.93#ibcon#read 6, iclass 13, count 0 2006.218.07:42:00.93#ibcon#end of sib2, iclass 13, count 0 2006.218.07:42:00.93#ibcon#*mode == 0, iclass 13, count 0 2006.218.07:42:00.93#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.218.07:42:00.93#ibcon#[28=FRQ=02,640.99\r\n] 2006.218.07:42:00.93#ibcon#*before write, iclass 13, count 0 2006.218.07:42:00.93#ibcon#enter sib2, iclass 13, count 0 2006.218.07:42:00.93#ibcon#flushed, iclass 13, count 0 2006.218.07:42:00.93#ibcon#about to write, iclass 13, count 0 2006.218.07:42:00.93#ibcon#wrote, iclass 13, count 0 2006.218.07:42:00.93#ibcon#about to read 3, iclass 13, count 0 2006.218.07:42:00.97#ibcon#read 3, iclass 13, count 0 2006.218.07:42:00.97#ibcon#about to read 4, iclass 13, count 0 2006.218.07:42:00.97#ibcon#read 4, iclass 13, count 0 2006.218.07:42:00.97#ibcon#about to read 5, iclass 13, count 0 2006.218.07:42:00.97#ibcon#read 5, iclass 13, count 0 2006.218.07:42:00.97#ibcon#about to read 6, iclass 13, count 0 2006.218.07:42:00.97#ibcon#read 6, iclass 13, count 0 2006.218.07:42:00.97#ibcon#end of sib2, iclass 13, count 0 2006.218.07:42:00.97#ibcon#*after write, iclass 13, count 0 2006.218.07:42:00.97#ibcon#*before return 0, iclass 13, count 0 2006.218.07:42:00.97#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.218.07:42:00.97#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.218.07:42:00.97#ibcon#about to clear, iclass 13 cls_cnt 0 2006.218.07:42:00.97#ibcon#cleared, iclass 13 cls_cnt 0 2006.218.07:42:00.97$vc4f8/vb=2,4 2006.218.07:42:00.97#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.218.07:42:00.97#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.218.07:42:00.97#ibcon#ireg 11 cls_cnt 2 2006.218.07:42:00.97#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.218.07:42:01.03#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.218.07:42:01.03#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.218.07:42:01.03#ibcon#enter wrdev, iclass 15, count 2 2006.218.07:42:01.03#ibcon#first serial, iclass 15, count 2 2006.218.07:42:01.03#ibcon#enter sib2, iclass 15, count 2 2006.218.07:42:01.03#ibcon#flushed, iclass 15, count 2 2006.218.07:42:01.03#ibcon#about to write, iclass 15, count 2 2006.218.07:42:01.03#ibcon#wrote, iclass 15, count 2 2006.218.07:42:01.03#ibcon#about to read 3, iclass 15, count 2 2006.218.07:42:01.05#ibcon#read 3, iclass 15, count 2 2006.218.07:42:01.05#ibcon#about to read 4, iclass 15, count 2 2006.218.07:42:01.05#ibcon#read 4, iclass 15, count 2 2006.218.07:42:01.05#ibcon#about to read 5, iclass 15, count 2 2006.218.07:42:01.05#ibcon#read 5, iclass 15, count 2 2006.218.07:42:01.05#ibcon#about to read 6, iclass 15, count 2 2006.218.07:42:01.05#ibcon#read 6, iclass 15, count 2 2006.218.07:42:01.05#ibcon#end of sib2, iclass 15, count 2 2006.218.07:42:01.05#ibcon#*mode == 0, iclass 15, count 2 2006.218.07:42:01.05#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.218.07:42:01.05#ibcon#[27=AT02-04\r\n] 2006.218.07:42:01.05#ibcon#*before write, iclass 15, count 2 2006.218.07:42:01.05#ibcon#enter sib2, iclass 15, count 2 2006.218.07:42:01.05#ibcon#flushed, iclass 15, count 2 2006.218.07:42:01.05#ibcon#about to write, iclass 15, count 2 2006.218.07:42:01.05#ibcon#wrote, iclass 15, count 2 2006.218.07:42:01.05#ibcon#about to read 3, iclass 15, count 2 2006.218.07:42:01.08#ibcon#read 3, iclass 15, count 2 2006.218.07:42:01.08#ibcon#about to read 4, iclass 15, count 2 2006.218.07:42:01.08#ibcon#read 4, iclass 15, count 2 2006.218.07:42:01.08#ibcon#about to read 5, iclass 15, count 2 2006.218.07:42:01.08#ibcon#read 5, iclass 15, count 2 2006.218.07:42:01.08#ibcon#about to read 6, iclass 15, count 2 2006.218.07:42:01.08#ibcon#read 6, iclass 15, count 2 2006.218.07:42:01.08#ibcon#end of sib2, iclass 15, count 2 2006.218.07:42:01.08#ibcon#*after write, iclass 15, count 2 2006.218.07:42:01.08#ibcon#*before return 0, iclass 15, count 2 2006.218.07:42:01.08#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.218.07:42:01.08#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.218.07:42:01.08#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.218.07:42:01.08#ibcon#ireg 7 cls_cnt 0 2006.218.07:42:01.08#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.218.07:42:01.20#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.218.07:42:01.20#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.218.07:42:01.20#ibcon#enter wrdev, iclass 15, count 0 2006.218.07:42:01.20#ibcon#first serial, iclass 15, count 0 2006.218.07:42:01.20#ibcon#enter sib2, iclass 15, count 0 2006.218.07:42:01.20#ibcon#flushed, iclass 15, count 0 2006.218.07:42:01.20#ibcon#about to write, iclass 15, count 0 2006.218.07:42:01.20#ibcon#wrote, iclass 15, count 0 2006.218.07:42:01.20#ibcon#about to read 3, iclass 15, count 0 2006.218.07:42:01.22#ibcon#read 3, iclass 15, count 0 2006.218.07:42:01.22#ibcon#about to read 4, iclass 15, count 0 2006.218.07:42:01.22#ibcon#read 4, iclass 15, count 0 2006.218.07:42:01.22#ibcon#about to read 5, iclass 15, count 0 2006.218.07:42:01.22#ibcon#read 5, iclass 15, count 0 2006.218.07:42:01.22#ibcon#about to read 6, iclass 15, count 0 2006.218.07:42:01.22#ibcon#read 6, iclass 15, count 0 2006.218.07:42:01.22#ibcon#end of sib2, iclass 15, count 0 2006.218.07:42:01.22#ibcon#*mode == 0, iclass 15, count 0 2006.218.07:42:01.22#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.218.07:42:01.22#ibcon#[27=USB\r\n] 2006.218.07:42:01.22#ibcon#*before write, iclass 15, count 0 2006.218.07:42:01.22#ibcon#enter sib2, iclass 15, count 0 2006.218.07:42:01.22#ibcon#flushed, iclass 15, count 0 2006.218.07:42:01.22#ibcon#about to write, iclass 15, count 0 2006.218.07:42:01.22#ibcon#wrote, iclass 15, count 0 2006.218.07:42:01.22#ibcon#about to read 3, iclass 15, count 0 2006.218.07:42:01.25#ibcon#read 3, iclass 15, count 0 2006.218.07:42:01.25#ibcon#about to read 4, iclass 15, count 0 2006.218.07:42:01.25#ibcon#read 4, iclass 15, count 0 2006.218.07:42:01.25#ibcon#about to read 5, iclass 15, count 0 2006.218.07:42:01.25#ibcon#read 5, iclass 15, count 0 2006.218.07:42:01.25#ibcon#about to read 6, iclass 15, count 0 2006.218.07:42:01.25#ibcon#read 6, iclass 15, count 0 2006.218.07:42:01.25#ibcon#end of sib2, iclass 15, count 0 2006.218.07:42:01.25#ibcon#*after write, iclass 15, count 0 2006.218.07:42:01.25#ibcon#*before return 0, iclass 15, count 0 2006.218.07:42:01.25#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.218.07:42:01.25#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.218.07:42:01.25#ibcon#about to clear, iclass 15 cls_cnt 0 2006.218.07:42:01.25#ibcon#cleared, iclass 15 cls_cnt 0 2006.218.07:42:01.25$vc4f8/vblo=3,656.99 2006.218.07:42:01.25#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.218.07:42:01.25#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.218.07:42:01.25#ibcon#ireg 17 cls_cnt 0 2006.218.07:42:01.25#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.218.07:42:01.25#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.218.07:42:01.25#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.218.07:42:01.25#ibcon#enter wrdev, iclass 17, count 0 2006.218.07:42:01.25#ibcon#first serial, iclass 17, count 0 2006.218.07:42:01.25#ibcon#enter sib2, iclass 17, count 0 2006.218.07:42:01.25#ibcon#flushed, iclass 17, count 0 2006.218.07:42:01.25#ibcon#about to write, iclass 17, count 0 2006.218.07:42:01.25#ibcon#wrote, iclass 17, count 0 2006.218.07:42:01.25#ibcon#about to read 3, iclass 17, count 0 2006.218.07:42:01.27#ibcon#read 3, iclass 17, count 0 2006.218.07:42:01.27#ibcon#about to read 4, iclass 17, count 0 2006.218.07:42:01.27#ibcon#read 4, iclass 17, count 0 2006.218.07:42:01.27#ibcon#about to read 5, iclass 17, count 0 2006.218.07:42:01.27#ibcon#read 5, iclass 17, count 0 2006.218.07:42:01.27#ibcon#about to read 6, iclass 17, count 0 2006.218.07:42:01.27#ibcon#read 6, iclass 17, count 0 2006.218.07:42:01.27#ibcon#end of sib2, iclass 17, count 0 2006.218.07:42:01.27#ibcon#*mode == 0, iclass 17, count 0 2006.218.07:42:01.27#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.218.07:42:01.27#ibcon#[28=FRQ=03,656.99\r\n] 2006.218.07:42:01.27#ibcon#*before write, iclass 17, count 0 2006.218.07:42:01.27#ibcon#enter sib2, iclass 17, count 0 2006.218.07:42:01.27#ibcon#flushed, iclass 17, count 0 2006.218.07:42:01.27#ibcon#about to write, iclass 17, count 0 2006.218.07:42:01.27#ibcon#wrote, iclass 17, count 0 2006.218.07:42:01.27#ibcon#about to read 3, iclass 17, count 0 2006.218.07:42:01.31#ibcon#read 3, iclass 17, count 0 2006.218.07:42:01.31#ibcon#about to read 4, iclass 17, count 0 2006.218.07:42:01.31#ibcon#read 4, iclass 17, count 0 2006.218.07:42:01.31#ibcon#about to read 5, iclass 17, count 0 2006.218.07:42:01.31#ibcon#read 5, iclass 17, count 0 2006.218.07:42:01.31#ibcon#about to read 6, iclass 17, count 0 2006.218.07:42:01.31#ibcon#read 6, iclass 17, count 0 2006.218.07:42:01.31#ibcon#end of sib2, iclass 17, count 0 2006.218.07:42:01.31#ibcon#*after write, iclass 17, count 0 2006.218.07:42:01.31#ibcon#*before return 0, iclass 17, count 0 2006.218.07:42:01.31#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.218.07:42:01.31#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.218.07:42:01.31#ibcon#about to clear, iclass 17 cls_cnt 0 2006.218.07:42:01.31#ibcon#cleared, iclass 17 cls_cnt 0 2006.218.07:42:01.31$vc4f8/vb=3,4 2006.218.07:42:01.31#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.218.07:42:01.31#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.218.07:42:01.31#ibcon#ireg 11 cls_cnt 2 2006.218.07:42:01.31#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.218.07:42:01.37#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.218.07:42:01.37#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.218.07:42:01.37#ibcon#enter wrdev, iclass 19, count 2 2006.218.07:42:01.37#ibcon#first serial, iclass 19, count 2 2006.218.07:42:01.37#ibcon#enter sib2, iclass 19, count 2 2006.218.07:42:01.37#ibcon#flushed, iclass 19, count 2 2006.218.07:42:01.37#ibcon#about to write, iclass 19, count 2 2006.218.07:42:01.37#ibcon#wrote, iclass 19, count 2 2006.218.07:42:01.37#ibcon#about to read 3, iclass 19, count 2 2006.218.07:42:01.39#ibcon#read 3, iclass 19, count 2 2006.218.07:42:01.39#ibcon#about to read 4, iclass 19, count 2 2006.218.07:42:01.39#ibcon#read 4, iclass 19, count 2 2006.218.07:42:01.39#ibcon#about to read 5, iclass 19, count 2 2006.218.07:42:01.39#ibcon#read 5, iclass 19, count 2 2006.218.07:42:01.39#ibcon#about to read 6, iclass 19, count 2 2006.218.07:42:01.39#ibcon#read 6, iclass 19, count 2 2006.218.07:42:01.39#ibcon#end of sib2, iclass 19, count 2 2006.218.07:42:01.39#ibcon#*mode == 0, iclass 19, count 2 2006.218.07:42:01.39#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.218.07:42:01.39#ibcon#[27=AT03-04\r\n] 2006.218.07:42:01.39#ibcon#*before write, iclass 19, count 2 2006.218.07:42:01.39#ibcon#enter sib2, iclass 19, count 2 2006.218.07:42:01.39#ibcon#flushed, iclass 19, count 2 2006.218.07:42:01.39#ibcon#about to write, iclass 19, count 2 2006.218.07:42:01.39#ibcon#wrote, iclass 19, count 2 2006.218.07:42:01.39#ibcon#about to read 3, iclass 19, count 2 2006.218.07:42:01.42#ibcon#read 3, iclass 19, count 2 2006.218.07:42:01.42#ibcon#about to read 4, iclass 19, count 2 2006.218.07:42:01.42#ibcon#read 4, iclass 19, count 2 2006.218.07:42:01.42#ibcon#about to read 5, iclass 19, count 2 2006.218.07:42:01.42#ibcon#read 5, iclass 19, count 2 2006.218.07:42:01.42#ibcon#about to read 6, iclass 19, count 2 2006.218.07:42:01.42#ibcon#read 6, iclass 19, count 2 2006.218.07:42:01.42#ibcon#end of sib2, iclass 19, count 2 2006.218.07:42:01.42#ibcon#*after write, iclass 19, count 2 2006.218.07:42:01.42#ibcon#*before return 0, iclass 19, count 2 2006.218.07:42:01.42#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.218.07:42:01.42#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.218.07:42:01.42#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.218.07:42:01.42#ibcon#ireg 7 cls_cnt 0 2006.218.07:42:01.42#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.218.07:42:01.54#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.218.07:42:01.54#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.218.07:42:01.54#ibcon#enter wrdev, iclass 19, count 0 2006.218.07:42:01.54#ibcon#first serial, iclass 19, count 0 2006.218.07:42:01.54#ibcon#enter sib2, iclass 19, count 0 2006.218.07:42:01.54#ibcon#flushed, iclass 19, count 0 2006.218.07:42:01.54#ibcon#about to write, iclass 19, count 0 2006.218.07:42:01.54#ibcon#wrote, iclass 19, count 0 2006.218.07:42:01.54#ibcon#about to read 3, iclass 19, count 0 2006.218.07:42:01.56#ibcon#read 3, iclass 19, count 0 2006.218.07:42:01.56#ibcon#about to read 4, iclass 19, count 0 2006.218.07:42:01.56#ibcon#read 4, iclass 19, count 0 2006.218.07:42:01.56#ibcon#about to read 5, iclass 19, count 0 2006.218.07:42:01.56#ibcon#read 5, iclass 19, count 0 2006.218.07:42:01.56#ibcon#about to read 6, iclass 19, count 0 2006.218.07:42:01.56#ibcon#read 6, iclass 19, count 0 2006.218.07:42:01.56#ibcon#end of sib2, iclass 19, count 0 2006.218.07:42:01.56#ibcon#*mode == 0, iclass 19, count 0 2006.218.07:42:01.56#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.218.07:42:01.56#ibcon#[27=USB\r\n] 2006.218.07:42:01.56#ibcon#*before write, iclass 19, count 0 2006.218.07:42:01.56#ibcon#enter sib2, iclass 19, count 0 2006.218.07:42:01.56#ibcon#flushed, iclass 19, count 0 2006.218.07:42:01.56#ibcon#about to write, iclass 19, count 0 2006.218.07:42:01.56#ibcon#wrote, iclass 19, count 0 2006.218.07:42:01.56#ibcon#about to read 3, iclass 19, count 0 2006.218.07:42:01.59#ibcon#read 3, iclass 19, count 0 2006.218.07:42:01.59#ibcon#about to read 4, iclass 19, count 0 2006.218.07:42:01.59#ibcon#read 4, iclass 19, count 0 2006.218.07:42:01.59#ibcon#about to read 5, iclass 19, count 0 2006.218.07:42:01.59#ibcon#read 5, iclass 19, count 0 2006.218.07:42:01.59#ibcon#about to read 6, iclass 19, count 0 2006.218.07:42:01.59#ibcon#read 6, iclass 19, count 0 2006.218.07:42:01.59#ibcon#end of sib2, iclass 19, count 0 2006.218.07:42:01.59#ibcon#*after write, iclass 19, count 0 2006.218.07:42:01.59#ibcon#*before return 0, iclass 19, count 0 2006.218.07:42:01.59#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.218.07:42:01.59#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.218.07:42:01.59#ibcon#about to clear, iclass 19 cls_cnt 0 2006.218.07:42:01.59#ibcon#cleared, iclass 19 cls_cnt 0 2006.218.07:42:01.59$vc4f8/vblo=4,712.99 2006.218.07:42:01.59#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.218.07:42:01.59#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.218.07:42:01.59#ibcon#ireg 17 cls_cnt 0 2006.218.07:42:01.59#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.218.07:42:01.59#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.218.07:42:01.59#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.218.07:42:01.59#ibcon#enter wrdev, iclass 21, count 0 2006.218.07:42:01.59#ibcon#first serial, iclass 21, count 0 2006.218.07:42:01.59#ibcon#enter sib2, iclass 21, count 0 2006.218.07:42:01.59#ibcon#flushed, iclass 21, count 0 2006.218.07:42:01.59#ibcon#about to write, iclass 21, count 0 2006.218.07:42:01.59#ibcon#wrote, iclass 21, count 0 2006.218.07:42:01.59#ibcon#about to read 3, iclass 21, count 0 2006.218.07:42:01.61#ibcon#read 3, iclass 21, count 0 2006.218.07:42:01.61#ibcon#about to read 4, iclass 21, count 0 2006.218.07:42:01.61#ibcon#read 4, iclass 21, count 0 2006.218.07:42:01.61#ibcon#about to read 5, iclass 21, count 0 2006.218.07:42:01.61#ibcon#read 5, iclass 21, count 0 2006.218.07:42:01.61#ibcon#about to read 6, iclass 21, count 0 2006.218.07:42:01.61#ibcon#read 6, iclass 21, count 0 2006.218.07:42:01.61#ibcon#end of sib2, iclass 21, count 0 2006.218.07:42:01.61#ibcon#*mode == 0, iclass 21, count 0 2006.218.07:42:01.61#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.218.07:42:01.61#ibcon#[28=FRQ=04,712.99\r\n] 2006.218.07:42:01.61#ibcon#*before write, iclass 21, count 0 2006.218.07:42:01.61#ibcon#enter sib2, iclass 21, count 0 2006.218.07:42:01.61#ibcon#flushed, iclass 21, count 0 2006.218.07:42:01.61#ibcon#about to write, iclass 21, count 0 2006.218.07:42:01.61#ibcon#wrote, iclass 21, count 0 2006.218.07:42:01.61#ibcon#about to read 3, iclass 21, count 0 2006.218.07:42:01.65#ibcon#read 3, iclass 21, count 0 2006.218.07:42:01.65#ibcon#about to read 4, iclass 21, count 0 2006.218.07:42:01.65#ibcon#read 4, iclass 21, count 0 2006.218.07:42:01.65#ibcon#about to read 5, iclass 21, count 0 2006.218.07:42:01.65#ibcon#read 5, iclass 21, count 0 2006.218.07:42:01.65#ibcon#about to read 6, iclass 21, count 0 2006.218.07:42:01.65#ibcon#read 6, iclass 21, count 0 2006.218.07:42:01.65#ibcon#end of sib2, iclass 21, count 0 2006.218.07:42:01.65#ibcon#*after write, iclass 21, count 0 2006.218.07:42:01.65#ibcon#*before return 0, iclass 21, count 0 2006.218.07:42:01.65#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.218.07:42:01.65#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.218.07:42:01.65#ibcon#about to clear, iclass 21 cls_cnt 0 2006.218.07:42:01.65#ibcon#cleared, iclass 21 cls_cnt 0 2006.218.07:42:01.65$vc4f8/vb=4,4 2006.218.07:42:01.65#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.218.07:42:01.65#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.218.07:42:01.65#ibcon#ireg 11 cls_cnt 2 2006.218.07:42:01.65#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.218.07:42:01.71#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.218.07:42:01.71#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.218.07:42:01.71#ibcon#enter wrdev, iclass 23, count 2 2006.218.07:42:01.71#ibcon#first serial, iclass 23, count 2 2006.218.07:42:01.71#ibcon#enter sib2, iclass 23, count 2 2006.218.07:42:01.71#ibcon#flushed, iclass 23, count 2 2006.218.07:42:01.71#ibcon#about to write, iclass 23, count 2 2006.218.07:42:01.71#ibcon#wrote, iclass 23, count 2 2006.218.07:42:01.71#ibcon#about to read 3, iclass 23, count 2 2006.218.07:42:01.73#ibcon#read 3, iclass 23, count 2 2006.218.07:42:01.73#ibcon#about to read 4, iclass 23, count 2 2006.218.07:42:01.73#ibcon#read 4, iclass 23, count 2 2006.218.07:42:01.73#ibcon#about to read 5, iclass 23, count 2 2006.218.07:42:01.73#ibcon#read 5, iclass 23, count 2 2006.218.07:42:01.73#ibcon#about to read 6, iclass 23, count 2 2006.218.07:42:01.73#ibcon#read 6, iclass 23, count 2 2006.218.07:42:01.73#ibcon#end of sib2, iclass 23, count 2 2006.218.07:42:01.73#ibcon#*mode == 0, iclass 23, count 2 2006.218.07:42:01.73#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.218.07:42:01.73#ibcon#[27=AT04-04\r\n] 2006.218.07:42:01.73#ibcon#*before write, iclass 23, count 2 2006.218.07:42:01.73#ibcon#enter sib2, iclass 23, count 2 2006.218.07:42:01.73#ibcon#flushed, iclass 23, count 2 2006.218.07:42:01.73#ibcon#about to write, iclass 23, count 2 2006.218.07:42:01.73#ibcon#wrote, iclass 23, count 2 2006.218.07:42:01.73#ibcon#about to read 3, iclass 23, count 2 2006.218.07:42:01.76#ibcon#read 3, iclass 23, count 2 2006.218.07:42:01.76#ibcon#about to read 4, iclass 23, count 2 2006.218.07:42:01.76#ibcon#read 4, iclass 23, count 2 2006.218.07:42:01.76#ibcon#about to read 5, iclass 23, count 2 2006.218.07:42:01.76#ibcon#read 5, iclass 23, count 2 2006.218.07:42:01.76#ibcon#about to read 6, iclass 23, count 2 2006.218.07:42:01.76#ibcon#read 6, iclass 23, count 2 2006.218.07:42:01.76#ibcon#end of sib2, iclass 23, count 2 2006.218.07:42:01.76#ibcon#*after write, iclass 23, count 2 2006.218.07:42:01.76#ibcon#*before return 0, iclass 23, count 2 2006.218.07:42:01.76#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.218.07:42:01.76#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.218.07:42:01.76#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.218.07:42:01.76#ibcon#ireg 7 cls_cnt 0 2006.218.07:42:01.76#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.218.07:42:01.88#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.218.07:42:01.88#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.218.07:42:01.88#ibcon#enter wrdev, iclass 23, count 0 2006.218.07:42:01.88#ibcon#first serial, iclass 23, count 0 2006.218.07:42:01.88#ibcon#enter sib2, iclass 23, count 0 2006.218.07:42:01.88#ibcon#flushed, iclass 23, count 0 2006.218.07:42:01.88#ibcon#about to write, iclass 23, count 0 2006.218.07:42:01.88#ibcon#wrote, iclass 23, count 0 2006.218.07:42:01.88#ibcon#about to read 3, iclass 23, count 0 2006.218.07:42:01.90#ibcon#read 3, iclass 23, count 0 2006.218.07:42:01.90#ibcon#about to read 4, iclass 23, count 0 2006.218.07:42:01.90#ibcon#read 4, iclass 23, count 0 2006.218.07:42:01.90#ibcon#about to read 5, iclass 23, count 0 2006.218.07:42:01.90#ibcon#read 5, iclass 23, count 0 2006.218.07:42:01.90#ibcon#about to read 6, iclass 23, count 0 2006.218.07:42:01.90#ibcon#read 6, iclass 23, count 0 2006.218.07:42:01.90#ibcon#end of sib2, iclass 23, count 0 2006.218.07:42:01.90#ibcon#*mode == 0, iclass 23, count 0 2006.218.07:42:01.90#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.218.07:42:01.90#ibcon#[27=USB\r\n] 2006.218.07:42:01.90#ibcon#*before write, iclass 23, count 0 2006.218.07:42:01.90#ibcon#enter sib2, iclass 23, count 0 2006.218.07:42:01.90#ibcon#flushed, iclass 23, count 0 2006.218.07:42:01.90#ibcon#about to write, iclass 23, count 0 2006.218.07:42:01.90#ibcon#wrote, iclass 23, count 0 2006.218.07:42:01.90#ibcon#about to read 3, iclass 23, count 0 2006.218.07:42:01.93#ibcon#read 3, iclass 23, count 0 2006.218.07:42:01.93#ibcon#about to read 4, iclass 23, count 0 2006.218.07:42:01.93#ibcon#read 4, iclass 23, count 0 2006.218.07:42:01.93#ibcon#about to read 5, iclass 23, count 0 2006.218.07:42:01.93#ibcon#read 5, iclass 23, count 0 2006.218.07:42:01.93#ibcon#about to read 6, iclass 23, count 0 2006.218.07:42:01.93#ibcon#read 6, iclass 23, count 0 2006.218.07:42:01.93#ibcon#end of sib2, iclass 23, count 0 2006.218.07:42:01.93#ibcon#*after write, iclass 23, count 0 2006.218.07:42:01.93#ibcon#*before return 0, iclass 23, count 0 2006.218.07:42:01.93#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.218.07:42:01.93#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.218.07:42:01.93#ibcon#about to clear, iclass 23 cls_cnt 0 2006.218.07:42:01.93#ibcon#cleared, iclass 23 cls_cnt 0 2006.218.07:42:01.93$vc4f8/vblo=5,744.99 2006.218.07:42:01.93#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.218.07:42:01.93#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.218.07:42:01.93#ibcon#ireg 17 cls_cnt 0 2006.218.07:42:01.93#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.218.07:42:01.93#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.218.07:42:01.93#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.218.07:42:01.93#ibcon#enter wrdev, iclass 25, count 0 2006.218.07:42:01.93#ibcon#first serial, iclass 25, count 0 2006.218.07:42:01.93#ibcon#enter sib2, iclass 25, count 0 2006.218.07:42:01.93#ibcon#flushed, iclass 25, count 0 2006.218.07:42:01.93#ibcon#about to write, iclass 25, count 0 2006.218.07:42:01.93#ibcon#wrote, iclass 25, count 0 2006.218.07:42:01.93#ibcon#about to read 3, iclass 25, count 0 2006.218.07:42:01.95#ibcon#read 3, iclass 25, count 0 2006.218.07:42:01.95#ibcon#about to read 4, iclass 25, count 0 2006.218.07:42:01.95#ibcon#read 4, iclass 25, count 0 2006.218.07:42:01.95#ibcon#about to read 5, iclass 25, count 0 2006.218.07:42:01.95#ibcon#read 5, iclass 25, count 0 2006.218.07:42:01.95#ibcon#about to read 6, iclass 25, count 0 2006.218.07:42:01.95#ibcon#read 6, iclass 25, count 0 2006.218.07:42:01.95#ibcon#end of sib2, iclass 25, count 0 2006.218.07:42:01.95#ibcon#*mode == 0, iclass 25, count 0 2006.218.07:42:01.95#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.218.07:42:01.95#ibcon#[28=FRQ=05,744.99\r\n] 2006.218.07:42:01.95#ibcon#*before write, iclass 25, count 0 2006.218.07:42:01.95#ibcon#enter sib2, iclass 25, count 0 2006.218.07:42:01.95#ibcon#flushed, iclass 25, count 0 2006.218.07:42:01.95#ibcon#about to write, iclass 25, count 0 2006.218.07:42:01.95#ibcon#wrote, iclass 25, count 0 2006.218.07:42:01.95#ibcon#about to read 3, iclass 25, count 0 2006.218.07:42:02.00#ibcon#read 3, iclass 25, count 0 2006.218.07:42:02.00#ibcon#about to read 4, iclass 25, count 0 2006.218.07:42:02.00#ibcon#read 4, iclass 25, count 0 2006.218.07:42:02.00#ibcon#about to read 5, iclass 25, count 0 2006.218.07:42:02.00#ibcon#read 5, iclass 25, count 0 2006.218.07:42:02.00#ibcon#about to read 6, iclass 25, count 0 2006.218.07:42:02.00#ibcon#read 6, iclass 25, count 0 2006.218.07:42:02.00#ibcon#end of sib2, iclass 25, count 0 2006.218.07:42:02.00#ibcon#*after write, iclass 25, count 0 2006.218.07:42:02.00#ibcon#*before return 0, iclass 25, count 0 2006.218.07:42:02.00#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.218.07:42:02.00#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.218.07:42:02.00#ibcon#about to clear, iclass 25 cls_cnt 0 2006.218.07:42:02.00#ibcon#cleared, iclass 25 cls_cnt 0 2006.218.07:42:02.00$vc4f8/vb=5,4 2006.218.07:42:02.00#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.218.07:42:02.00#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.218.07:42:02.00#ibcon#ireg 11 cls_cnt 2 2006.218.07:42:02.00#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.218.07:42:02.05#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.218.07:42:02.05#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.218.07:42:02.05#ibcon#enter wrdev, iclass 27, count 2 2006.218.07:42:02.05#ibcon#first serial, iclass 27, count 2 2006.218.07:42:02.05#ibcon#enter sib2, iclass 27, count 2 2006.218.07:42:02.05#ibcon#flushed, iclass 27, count 2 2006.218.07:42:02.05#ibcon#about to write, iclass 27, count 2 2006.218.07:42:02.05#ibcon#wrote, iclass 27, count 2 2006.218.07:42:02.05#ibcon#about to read 3, iclass 27, count 2 2006.218.07:42:02.07#ibcon#read 3, iclass 27, count 2 2006.218.07:42:02.07#ibcon#about to read 4, iclass 27, count 2 2006.218.07:42:02.07#ibcon#read 4, iclass 27, count 2 2006.218.07:42:02.07#ibcon#about to read 5, iclass 27, count 2 2006.218.07:42:02.07#ibcon#read 5, iclass 27, count 2 2006.218.07:42:02.07#ibcon#about to read 6, iclass 27, count 2 2006.218.07:42:02.07#ibcon#read 6, iclass 27, count 2 2006.218.07:42:02.07#ibcon#end of sib2, iclass 27, count 2 2006.218.07:42:02.07#ibcon#*mode == 0, iclass 27, count 2 2006.218.07:42:02.07#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.218.07:42:02.07#ibcon#[27=AT05-04\r\n] 2006.218.07:42:02.07#ibcon#*before write, iclass 27, count 2 2006.218.07:42:02.07#ibcon#enter sib2, iclass 27, count 2 2006.218.07:42:02.07#ibcon#flushed, iclass 27, count 2 2006.218.07:42:02.07#ibcon#about to write, iclass 27, count 2 2006.218.07:42:02.07#ibcon#wrote, iclass 27, count 2 2006.218.07:42:02.07#ibcon#about to read 3, iclass 27, count 2 2006.218.07:42:02.10#ibcon#read 3, iclass 27, count 2 2006.218.07:42:02.10#ibcon#about to read 4, iclass 27, count 2 2006.218.07:42:02.10#ibcon#read 4, iclass 27, count 2 2006.218.07:42:02.10#ibcon#about to read 5, iclass 27, count 2 2006.218.07:42:02.10#ibcon#read 5, iclass 27, count 2 2006.218.07:42:02.10#ibcon#about to read 6, iclass 27, count 2 2006.218.07:42:02.10#ibcon#read 6, iclass 27, count 2 2006.218.07:42:02.10#ibcon#end of sib2, iclass 27, count 2 2006.218.07:42:02.10#ibcon#*after write, iclass 27, count 2 2006.218.07:42:02.10#ibcon#*before return 0, iclass 27, count 2 2006.218.07:42:02.10#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.218.07:42:02.10#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.218.07:42:02.10#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.218.07:42:02.10#ibcon#ireg 7 cls_cnt 0 2006.218.07:42:02.10#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.218.07:42:02.22#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.218.07:42:02.22#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.218.07:42:02.22#ibcon#enter wrdev, iclass 27, count 0 2006.218.07:42:02.22#ibcon#first serial, iclass 27, count 0 2006.218.07:42:02.22#ibcon#enter sib2, iclass 27, count 0 2006.218.07:42:02.22#ibcon#flushed, iclass 27, count 0 2006.218.07:42:02.22#ibcon#about to write, iclass 27, count 0 2006.218.07:42:02.22#ibcon#wrote, iclass 27, count 0 2006.218.07:42:02.22#ibcon#about to read 3, iclass 27, count 0 2006.218.07:42:02.24#ibcon#read 3, iclass 27, count 0 2006.218.07:42:02.24#ibcon#about to read 4, iclass 27, count 0 2006.218.07:42:02.24#ibcon#read 4, iclass 27, count 0 2006.218.07:42:02.24#ibcon#about to read 5, iclass 27, count 0 2006.218.07:42:02.24#ibcon#read 5, iclass 27, count 0 2006.218.07:42:02.24#ibcon#about to read 6, iclass 27, count 0 2006.218.07:42:02.24#ibcon#read 6, iclass 27, count 0 2006.218.07:42:02.24#ibcon#end of sib2, iclass 27, count 0 2006.218.07:42:02.24#ibcon#*mode == 0, iclass 27, count 0 2006.218.07:42:02.24#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.218.07:42:02.24#ibcon#[27=USB\r\n] 2006.218.07:42:02.24#ibcon#*before write, iclass 27, count 0 2006.218.07:42:02.24#ibcon#enter sib2, iclass 27, count 0 2006.218.07:42:02.24#ibcon#flushed, iclass 27, count 0 2006.218.07:42:02.24#ibcon#about to write, iclass 27, count 0 2006.218.07:42:02.24#ibcon#wrote, iclass 27, count 0 2006.218.07:42:02.24#ibcon#about to read 3, iclass 27, count 0 2006.218.07:42:02.27#ibcon#read 3, iclass 27, count 0 2006.218.07:42:02.27#ibcon#about to read 4, iclass 27, count 0 2006.218.07:42:02.27#ibcon#read 4, iclass 27, count 0 2006.218.07:42:02.27#ibcon#about to read 5, iclass 27, count 0 2006.218.07:42:02.27#ibcon#read 5, iclass 27, count 0 2006.218.07:42:02.27#ibcon#about to read 6, iclass 27, count 0 2006.218.07:42:02.27#ibcon#read 6, iclass 27, count 0 2006.218.07:42:02.27#ibcon#end of sib2, iclass 27, count 0 2006.218.07:42:02.27#ibcon#*after write, iclass 27, count 0 2006.218.07:42:02.27#ibcon#*before return 0, iclass 27, count 0 2006.218.07:42:02.27#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.218.07:42:02.27#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.218.07:42:02.27#ibcon#about to clear, iclass 27 cls_cnt 0 2006.218.07:42:02.27#ibcon#cleared, iclass 27 cls_cnt 0 2006.218.07:42:02.27$vc4f8/vblo=6,752.99 2006.218.07:42:02.27#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.218.07:42:02.27#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.218.07:42:02.27#ibcon#ireg 17 cls_cnt 0 2006.218.07:42:02.27#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.218.07:42:02.27#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.218.07:42:02.27#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.218.07:42:02.27#ibcon#enter wrdev, iclass 29, count 0 2006.218.07:42:02.27#ibcon#first serial, iclass 29, count 0 2006.218.07:42:02.27#ibcon#enter sib2, iclass 29, count 0 2006.218.07:42:02.27#ibcon#flushed, iclass 29, count 0 2006.218.07:42:02.27#ibcon#about to write, iclass 29, count 0 2006.218.07:42:02.27#ibcon#wrote, iclass 29, count 0 2006.218.07:42:02.27#ibcon#about to read 3, iclass 29, count 0 2006.218.07:42:02.29#ibcon#read 3, iclass 29, count 0 2006.218.07:42:02.29#ibcon#about to read 4, iclass 29, count 0 2006.218.07:42:02.29#ibcon#read 4, iclass 29, count 0 2006.218.07:42:02.29#ibcon#about to read 5, iclass 29, count 0 2006.218.07:42:02.29#ibcon#read 5, iclass 29, count 0 2006.218.07:42:02.29#ibcon#about to read 6, iclass 29, count 0 2006.218.07:42:02.29#ibcon#read 6, iclass 29, count 0 2006.218.07:42:02.29#ibcon#end of sib2, iclass 29, count 0 2006.218.07:42:02.29#ibcon#*mode == 0, iclass 29, count 0 2006.218.07:42:02.29#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.218.07:42:02.29#ibcon#[28=FRQ=06,752.99\r\n] 2006.218.07:42:02.29#ibcon#*before write, iclass 29, count 0 2006.218.07:42:02.29#ibcon#enter sib2, iclass 29, count 0 2006.218.07:42:02.29#ibcon#flushed, iclass 29, count 0 2006.218.07:42:02.29#ibcon#about to write, iclass 29, count 0 2006.218.07:42:02.29#ibcon#wrote, iclass 29, count 0 2006.218.07:42:02.29#ibcon#about to read 3, iclass 29, count 0 2006.218.07:42:02.33#ibcon#read 3, iclass 29, count 0 2006.218.07:42:02.33#ibcon#about to read 4, iclass 29, count 0 2006.218.07:42:02.33#ibcon#read 4, iclass 29, count 0 2006.218.07:42:02.33#ibcon#about to read 5, iclass 29, count 0 2006.218.07:42:02.33#ibcon#read 5, iclass 29, count 0 2006.218.07:42:02.33#ibcon#about to read 6, iclass 29, count 0 2006.218.07:42:02.33#ibcon#read 6, iclass 29, count 0 2006.218.07:42:02.33#ibcon#end of sib2, iclass 29, count 0 2006.218.07:42:02.33#ibcon#*after write, iclass 29, count 0 2006.218.07:42:02.33#ibcon#*before return 0, iclass 29, count 0 2006.218.07:42:02.33#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.218.07:42:02.33#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.218.07:42:02.33#ibcon#about to clear, iclass 29 cls_cnt 0 2006.218.07:42:02.33#ibcon#cleared, iclass 29 cls_cnt 0 2006.218.07:42:02.33$vc4f8/vb=6,4 2006.218.07:42:02.33#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.218.07:42:02.33#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.218.07:42:02.33#ibcon#ireg 11 cls_cnt 2 2006.218.07:42:02.33#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.218.07:42:02.39#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.218.07:42:02.39#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.218.07:42:02.39#ibcon#enter wrdev, iclass 31, count 2 2006.218.07:42:02.39#ibcon#first serial, iclass 31, count 2 2006.218.07:42:02.39#ibcon#enter sib2, iclass 31, count 2 2006.218.07:42:02.39#ibcon#flushed, iclass 31, count 2 2006.218.07:42:02.39#ibcon#about to write, iclass 31, count 2 2006.218.07:42:02.39#ibcon#wrote, iclass 31, count 2 2006.218.07:42:02.39#ibcon#about to read 3, iclass 31, count 2 2006.218.07:42:02.40#abcon#<5=/06 4.5 7.4 31.37 721007.4\r\n> 2006.218.07:42:02.41#ibcon#read 3, iclass 31, count 2 2006.218.07:42:02.41#ibcon#about to read 4, iclass 31, count 2 2006.218.07:42:02.41#ibcon#read 4, iclass 31, count 2 2006.218.07:42:02.41#ibcon#about to read 5, iclass 31, count 2 2006.218.07:42:02.41#ibcon#read 5, iclass 31, count 2 2006.218.07:42:02.41#ibcon#about to read 6, iclass 31, count 2 2006.218.07:42:02.41#ibcon#read 6, iclass 31, count 2 2006.218.07:42:02.41#ibcon#end of sib2, iclass 31, count 2 2006.218.07:42:02.41#ibcon#*mode == 0, iclass 31, count 2 2006.218.07:42:02.41#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.218.07:42:02.41#ibcon#[27=AT06-04\r\n] 2006.218.07:42:02.41#ibcon#*before write, iclass 31, count 2 2006.218.07:42:02.41#ibcon#enter sib2, iclass 31, count 2 2006.218.07:42:02.41#ibcon#flushed, iclass 31, count 2 2006.218.07:42:02.41#ibcon#about to write, iclass 31, count 2 2006.218.07:42:02.41#ibcon#wrote, iclass 31, count 2 2006.218.07:42:02.41#ibcon#about to read 3, iclass 31, count 2 2006.218.07:42:02.42#abcon#{5=INTERFACE CLEAR} 2006.218.07:42:02.44#ibcon#read 3, iclass 31, count 2 2006.218.07:42:02.44#ibcon#about to read 4, iclass 31, count 2 2006.218.07:42:02.44#ibcon#read 4, iclass 31, count 2 2006.218.07:42:02.44#ibcon#about to read 5, iclass 31, count 2 2006.218.07:42:02.44#ibcon#read 5, iclass 31, count 2 2006.218.07:42:02.44#ibcon#about to read 6, iclass 31, count 2 2006.218.07:42:02.44#ibcon#read 6, iclass 31, count 2 2006.218.07:42:02.44#ibcon#end of sib2, iclass 31, count 2 2006.218.07:42:02.44#ibcon#*after write, iclass 31, count 2 2006.218.07:42:02.44#ibcon#*before return 0, iclass 31, count 2 2006.218.07:42:02.44#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.218.07:42:02.44#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.218.07:42:02.44#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.218.07:42:02.44#ibcon#ireg 7 cls_cnt 0 2006.218.07:42:02.44#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.218.07:42:02.48#abcon#[5=S1D000X0/0*\r\n] 2006.218.07:42:02.56#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.218.07:42:02.56#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.218.07:42:02.56#ibcon#enter wrdev, iclass 31, count 0 2006.218.07:42:02.56#ibcon#first serial, iclass 31, count 0 2006.218.07:42:02.56#ibcon#enter sib2, iclass 31, count 0 2006.218.07:42:02.56#ibcon#flushed, iclass 31, count 0 2006.218.07:42:02.56#ibcon#about to write, iclass 31, count 0 2006.218.07:42:02.56#ibcon#wrote, iclass 31, count 0 2006.218.07:42:02.56#ibcon#about to read 3, iclass 31, count 0 2006.218.07:42:02.58#ibcon#read 3, iclass 31, count 0 2006.218.07:42:02.58#ibcon#about to read 4, iclass 31, count 0 2006.218.07:42:02.58#ibcon#read 4, iclass 31, count 0 2006.218.07:42:02.58#ibcon#about to read 5, iclass 31, count 0 2006.218.07:42:02.58#ibcon#read 5, iclass 31, count 0 2006.218.07:42:02.58#ibcon#about to read 6, iclass 31, count 0 2006.218.07:42:02.58#ibcon#read 6, iclass 31, count 0 2006.218.07:42:02.58#ibcon#end of sib2, iclass 31, count 0 2006.218.07:42:02.58#ibcon#*mode == 0, iclass 31, count 0 2006.218.07:42:02.58#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.218.07:42:02.58#ibcon#[27=USB\r\n] 2006.218.07:42:02.58#ibcon#*before write, iclass 31, count 0 2006.218.07:42:02.58#ibcon#enter sib2, iclass 31, count 0 2006.218.07:42:02.58#ibcon#flushed, iclass 31, count 0 2006.218.07:42:02.58#ibcon#about to write, iclass 31, count 0 2006.218.07:42:02.58#ibcon#wrote, iclass 31, count 0 2006.218.07:42:02.58#ibcon#about to read 3, iclass 31, count 0 2006.218.07:42:02.61#ibcon#read 3, iclass 31, count 0 2006.218.07:42:02.61#ibcon#about to read 4, iclass 31, count 0 2006.218.07:42:02.61#ibcon#read 4, iclass 31, count 0 2006.218.07:42:02.61#ibcon#about to read 5, iclass 31, count 0 2006.218.07:42:02.61#ibcon#read 5, iclass 31, count 0 2006.218.07:42:02.61#ibcon#about to read 6, iclass 31, count 0 2006.218.07:42:02.61#ibcon#read 6, iclass 31, count 0 2006.218.07:42:02.61#ibcon#end of sib2, iclass 31, count 0 2006.218.07:42:02.61#ibcon#*after write, iclass 31, count 0 2006.218.07:42:02.61#ibcon#*before return 0, iclass 31, count 0 2006.218.07:42:02.61#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.218.07:42:02.61#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.218.07:42:02.61#ibcon#about to clear, iclass 31 cls_cnt 0 2006.218.07:42:02.61#ibcon#cleared, iclass 31 cls_cnt 0 2006.218.07:42:02.61$vc4f8/vabw=wide 2006.218.07:42:02.61#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.218.07:42:02.61#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.218.07:42:02.61#ibcon#ireg 8 cls_cnt 0 2006.218.07:42:02.61#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.218.07:42:02.61#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.218.07:42:02.61#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.218.07:42:02.61#ibcon#enter wrdev, iclass 37, count 0 2006.218.07:42:02.61#ibcon#first serial, iclass 37, count 0 2006.218.07:42:02.61#ibcon#enter sib2, iclass 37, count 0 2006.218.07:42:02.61#ibcon#flushed, iclass 37, count 0 2006.218.07:42:02.61#ibcon#about to write, iclass 37, count 0 2006.218.07:42:02.61#ibcon#wrote, iclass 37, count 0 2006.218.07:42:02.61#ibcon#about to read 3, iclass 37, count 0 2006.218.07:42:02.63#ibcon#read 3, iclass 37, count 0 2006.218.07:42:02.63#ibcon#about to read 4, iclass 37, count 0 2006.218.07:42:02.63#ibcon#read 4, iclass 37, count 0 2006.218.07:42:02.63#ibcon#about to read 5, iclass 37, count 0 2006.218.07:42:02.63#ibcon#read 5, iclass 37, count 0 2006.218.07:42:02.63#ibcon#about to read 6, iclass 37, count 0 2006.218.07:42:02.63#ibcon#read 6, iclass 37, count 0 2006.218.07:42:02.63#ibcon#end of sib2, iclass 37, count 0 2006.218.07:42:02.63#ibcon#*mode == 0, iclass 37, count 0 2006.218.07:42:02.63#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.218.07:42:02.63#ibcon#[25=BW32\r\n] 2006.218.07:42:02.63#ibcon#*before write, iclass 37, count 0 2006.218.07:42:02.63#ibcon#enter sib2, iclass 37, count 0 2006.218.07:42:02.63#ibcon#flushed, iclass 37, count 0 2006.218.07:42:02.63#ibcon#about to write, iclass 37, count 0 2006.218.07:42:02.63#ibcon#wrote, iclass 37, count 0 2006.218.07:42:02.63#ibcon#about to read 3, iclass 37, count 0 2006.218.07:42:02.66#ibcon#read 3, iclass 37, count 0 2006.218.07:42:02.66#ibcon#about to read 4, iclass 37, count 0 2006.218.07:42:02.66#ibcon#read 4, iclass 37, count 0 2006.218.07:42:02.66#ibcon#about to read 5, iclass 37, count 0 2006.218.07:42:02.66#ibcon#read 5, iclass 37, count 0 2006.218.07:42:02.66#ibcon#about to read 6, iclass 37, count 0 2006.218.07:42:02.66#ibcon#read 6, iclass 37, count 0 2006.218.07:42:02.66#ibcon#end of sib2, iclass 37, count 0 2006.218.07:42:02.66#ibcon#*after write, iclass 37, count 0 2006.218.07:42:02.66#ibcon#*before return 0, iclass 37, count 0 2006.218.07:42:02.66#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.218.07:42:02.66#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.218.07:42:02.66#ibcon#about to clear, iclass 37 cls_cnt 0 2006.218.07:42:02.66#ibcon#cleared, iclass 37 cls_cnt 0 2006.218.07:42:02.66$vc4f8/vbbw=wide 2006.218.07:42:02.66#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.218.07:42:02.66#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.218.07:42:02.66#ibcon#ireg 8 cls_cnt 0 2006.218.07:42:02.66#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.218.07:42:02.73#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.218.07:42:02.73#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.218.07:42:02.73#ibcon#enter wrdev, iclass 39, count 0 2006.218.07:42:02.73#ibcon#first serial, iclass 39, count 0 2006.218.07:42:02.73#ibcon#enter sib2, iclass 39, count 0 2006.218.07:42:02.73#ibcon#flushed, iclass 39, count 0 2006.218.07:42:02.73#ibcon#about to write, iclass 39, count 0 2006.218.07:42:02.73#ibcon#wrote, iclass 39, count 0 2006.218.07:42:02.73#ibcon#about to read 3, iclass 39, count 0 2006.218.07:42:02.75#ibcon#read 3, iclass 39, count 0 2006.218.07:42:02.75#ibcon#about to read 4, iclass 39, count 0 2006.218.07:42:02.75#ibcon#read 4, iclass 39, count 0 2006.218.07:42:02.75#ibcon#about to read 5, iclass 39, count 0 2006.218.07:42:02.75#ibcon#read 5, iclass 39, count 0 2006.218.07:42:02.75#ibcon#about to read 6, iclass 39, count 0 2006.218.07:42:02.75#ibcon#read 6, iclass 39, count 0 2006.218.07:42:02.75#ibcon#end of sib2, iclass 39, count 0 2006.218.07:42:02.75#ibcon#*mode == 0, iclass 39, count 0 2006.218.07:42:02.75#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.218.07:42:02.75#ibcon#[27=BW32\r\n] 2006.218.07:42:02.75#ibcon#*before write, iclass 39, count 0 2006.218.07:42:02.75#ibcon#enter sib2, iclass 39, count 0 2006.218.07:42:02.75#ibcon#flushed, iclass 39, count 0 2006.218.07:42:02.75#ibcon#about to write, iclass 39, count 0 2006.218.07:42:02.75#ibcon#wrote, iclass 39, count 0 2006.218.07:42:02.75#ibcon#about to read 3, iclass 39, count 0 2006.218.07:42:02.78#ibcon#read 3, iclass 39, count 0 2006.218.07:42:02.78#ibcon#about to read 4, iclass 39, count 0 2006.218.07:42:02.78#ibcon#read 4, iclass 39, count 0 2006.218.07:42:02.78#ibcon#about to read 5, iclass 39, count 0 2006.218.07:42:02.78#ibcon#read 5, iclass 39, count 0 2006.218.07:42:02.78#ibcon#about to read 6, iclass 39, count 0 2006.218.07:42:02.78#ibcon#read 6, iclass 39, count 0 2006.218.07:42:02.78#ibcon#end of sib2, iclass 39, count 0 2006.218.07:42:02.78#ibcon#*after write, iclass 39, count 0 2006.218.07:42:02.78#ibcon#*before return 0, iclass 39, count 0 2006.218.07:42:02.78#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.218.07:42:02.78#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.218.07:42:02.78#ibcon#about to clear, iclass 39 cls_cnt 0 2006.218.07:42:02.78#ibcon#cleared, iclass 39 cls_cnt 0 2006.218.07:42:02.78$4f8m12a/ifd4f 2006.218.07:42:02.78$ifd4f/lo= 2006.218.07:42:02.78$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.218.07:42:02.78$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.218.07:42:02.78$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.218.07:42:02.78$ifd4f/patch= 2006.218.07:42:02.78$ifd4f/patch=lo1,a1,a2,a3,a4 2006.218.07:42:02.78$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.218.07:42:02.78$ifd4f/patch=lo3,a5,a6,a7,a8 2006.218.07:42:02.78$4f8m12a/"form=m,16.000,1:2 2006.218.07:42:02.78$4f8m12a/"tpicd 2006.218.07:42:02.78$4f8m12a/echo=off 2006.218.07:42:02.78$4f8m12a/xlog=off 2006.218.07:42:02.78:!2006.218.07:42:30 2006.218.07:42:14.14#trakl#Source acquired 2006.218.07:42:15.14#flagr#flagr/antenna,acquired 2006.218.07:42:30.00:preob 2006.218.07:42:31.14/onsource/TRACKING 2006.218.07:42:31.14:!2006.218.07:42:40 2006.218.07:42:40.00:data_valid=on 2006.218.07:42:40.00:midob 2006.218.07:42:40.14/onsource/TRACKING 2006.218.07:42:40.14/wx/31.36,1007.4,72 2006.218.07:42:40.31/cable/+6.3825E-03 2006.218.07:42:41.40/va/01,05,usb,yes,32,33 2006.218.07:42:41.40/va/02,04,usb,yes,29,31 2006.218.07:42:41.40/va/03,04,usb,yes,28,28 2006.218.07:42:41.40/va/04,04,usb,yes,31,33 2006.218.07:42:41.40/va/05,07,usb,yes,33,35 2006.218.07:42:41.40/va/06,06,usb,yes,32,32 2006.218.07:42:41.40/va/07,06,usb,yes,33,32 2006.218.07:42:41.40/va/08,07,usb,yes,31,31 2006.218.07:42:41.63/valo/01,532.99,yes,locked 2006.218.07:42:41.63/valo/02,572.99,yes,locked 2006.218.07:42:41.63/valo/03,672.99,yes,locked 2006.218.07:42:41.63/valo/04,832.99,yes,locked 2006.218.07:42:41.63/valo/05,652.99,yes,locked 2006.218.07:42:41.63/valo/06,772.99,yes,locked 2006.218.07:42:41.63/valo/07,832.99,yes,locked 2006.218.07:42:41.63/valo/08,852.99,yes,locked 2006.218.07:42:42.72/vb/01,04,usb,yes,30,29 2006.218.07:42:42.72/vb/02,04,usb,yes,33,34 2006.218.07:42:42.72/vb/03,04,usb,yes,29,34 2006.218.07:42:42.72/vb/04,04,usb,yes,29,29 2006.218.07:42:42.72/vb/05,04,usb,yes,28,32 2006.218.07:42:42.72/vb/06,04,usb,yes,29,32 2006.218.07:42:42.72/vb/07,04,usb,yes,31,31 2006.218.07:42:42.72/vb/08,04,usb,yes,28,32 2006.218.07:42:42.96/vblo/01,632.99,yes,locked 2006.218.07:42:42.96/vblo/02,640.99,yes,locked 2006.218.07:42:42.96/vblo/03,656.99,yes,locked 2006.218.07:42:42.96/vblo/04,712.99,yes,locked 2006.218.07:42:42.96/vblo/05,744.99,yes,locked 2006.218.07:42:42.96/vblo/06,752.99,yes,locked 2006.218.07:42:42.96/vblo/07,734.99,yes,locked 2006.218.07:42:42.96/vblo/08,744.99,yes,locked 2006.218.07:42:43.11/vabw/8 2006.218.07:42:43.26/vbbw/8 2006.218.07:42:43.35/xfe/off,on,14.7 2006.218.07:42:43.74/ifatt/23,28,28,28 2006.218.07:42:44.08/fmout-gps/S +4.69E-07 2006.218.07:42:44.12:!2006.218.07:43:40 2006.218.07:43:40.00:data_valid=off 2006.218.07:43:40.00:postob 2006.218.07:43:40.14/cable/+6.3825E-03 2006.218.07:43:40.14/wx/31.33,1007.4,72 2006.218.07:43:41.07/fmout-gps/S +4.70E-07 2006.218.07:43:41.07:scan_name=218-0744,k06218,60 2006.218.07:43:41.07:source=3c371,180650.68,694928.1,2000.0,cw 2006.218.07:43:41.14#flagr#flagr/antenna,new-source 2006.218.07:43:42.14:checkk5 2006.218.07:43:42.51/chk_autoobs//k5ts1/ autoobs is running! 2006.218.07:43:42.88/chk_autoobs//k5ts2/ autoobs is running! 2006.218.07:43:43.26/chk_autoobs//k5ts3/ autoobs is running! 2006.218.07:43:43.64/chk_autoobs//k5ts4/ autoobs is running! 2006.218.07:43:44.00/chk_obsdata//k5ts1/T2180742??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:43:44.37/chk_obsdata//k5ts2/T2180742??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:43:44.73/chk_obsdata//k5ts3/T2180742??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:43:45.10/chk_obsdata//k5ts4/T2180742??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:43:45.81/k5log//k5ts1_log_newline 2006.218.07:43:46.49/k5log//k5ts2_log_newline 2006.218.07:43:47.18/k5log//k5ts3_log_newline 2006.218.07:43:47.88/k5log//k5ts4_log_newline 2006.218.07:43:47.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.218.07:43:47.90:4f8m12a=1 2006.218.07:43:47.90$4f8m12a/echo=on 2006.218.07:43:47.90$4f8m12a/pcalon 2006.218.07:43:47.90$pcalon/"no phase cal control is implemented here 2006.218.07:43:47.90$4f8m12a/"tpicd=stop 2006.218.07:43:47.90$4f8m12a/vc4f8 2006.218.07:43:47.90$vc4f8/valo=1,532.99 2006.218.07:43:47.91#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.218.07:43:47.91#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.218.07:43:47.91#ibcon#ireg 17 cls_cnt 0 2006.218.07:43:47.91#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.218.07:43:47.91#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.218.07:43:47.91#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.218.07:43:47.91#ibcon#enter wrdev, iclass 10, count 0 2006.218.07:43:47.91#ibcon#first serial, iclass 10, count 0 2006.218.07:43:47.91#ibcon#enter sib2, iclass 10, count 0 2006.218.07:43:47.91#ibcon#flushed, iclass 10, count 0 2006.218.07:43:47.91#ibcon#about to write, iclass 10, count 0 2006.218.07:43:47.91#ibcon#wrote, iclass 10, count 0 2006.218.07:43:47.91#ibcon#about to read 3, iclass 10, count 0 2006.218.07:43:47.94#ibcon#read 3, iclass 10, count 0 2006.218.07:43:47.94#ibcon#about to read 4, iclass 10, count 0 2006.218.07:43:47.94#ibcon#read 4, iclass 10, count 0 2006.218.07:43:47.94#ibcon#about to read 5, iclass 10, count 0 2006.218.07:43:47.94#ibcon#read 5, iclass 10, count 0 2006.218.07:43:47.94#ibcon#about to read 6, iclass 10, count 0 2006.218.07:43:47.94#ibcon#read 6, iclass 10, count 0 2006.218.07:43:47.94#ibcon#end of sib2, iclass 10, count 0 2006.218.07:43:47.94#ibcon#*mode == 0, iclass 10, count 0 2006.218.07:43:47.94#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.218.07:43:47.94#ibcon#[26=FRQ=01,532.99\r\n] 2006.218.07:43:47.94#ibcon#*before write, iclass 10, count 0 2006.218.07:43:47.94#ibcon#enter sib2, iclass 10, count 0 2006.218.07:43:47.94#ibcon#flushed, iclass 10, count 0 2006.218.07:43:47.94#ibcon#about to write, iclass 10, count 0 2006.218.07:43:47.94#ibcon#wrote, iclass 10, count 0 2006.218.07:43:47.94#ibcon#about to read 3, iclass 10, count 0 2006.218.07:43:47.99#ibcon#read 3, iclass 10, count 0 2006.218.07:43:47.99#ibcon#about to read 4, iclass 10, count 0 2006.218.07:43:47.99#ibcon#read 4, iclass 10, count 0 2006.218.07:43:47.99#ibcon#about to read 5, iclass 10, count 0 2006.218.07:43:47.99#ibcon#read 5, iclass 10, count 0 2006.218.07:43:47.99#ibcon#about to read 6, iclass 10, count 0 2006.218.07:43:47.99#ibcon#read 6, iclass 10, count 0 2006.218.07:43:47.99#ibcon#end of sib2, iclass 10, count 0 2006.218.07:43:47.99#ibcon#*after write, iclass 10, count 0 2006.218.07:43:47.99#ibcon#*before return 0, iclass 10, count 0 2006.218.07:43:47.99#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.218.07:43:47.99#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.218.07:43:47.99#ibcon#about to clear, iclass 10 cls_cnt 0 2006.218.07:43:47.99#ibcon#cleared, iclass 10 cls_cnt 0 2006.218.07:43:47.99$vc4f8/va=1,5 2006.218.07:43:47.99#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.218.07:43:47.99#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.218.07:43:47.99#ibcon#ireg 11 cls_cnt 2 2006.218.07:43:47.99#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.218.07:43:47.99#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.218.07:43:47.99#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.218.07:43:47.99#ibcon#enter wrdev, iclass 12, count 2 2006.218.07:43:47.99#ibcon#first serial, iclass 12, count 2 2006.218.07:43:47.99#ibcon#enter sib2, iclass 12, count 2 2006.218.07:43:47.99#ibcon#flushed, iclass 12, count 2 2006.218.07:43:47.99#ibcon#about to write, iclass 12, count 2 2006.218.07:43:47.99#ibcon#wrote, iclass 12, count 2 2006.218.07:43:47.99#ibcon#about to read 3, iclass 12, count 2 2006.218.07:43:48.01#ibcon#read 3, iclass 12, count 2 2006.218.07:43:48.01#ibcon#about to read 4, iclass 12, count 2 2006.218.07:43:48.01#ibcon#read 4, iclass 12, count 2 2006.218.07:43:48.01#ibcon#about to read 5, iclass 12, count 2 2006.218.07:43:48.01#ibcon#read 5, iclass 12, count 2 2006.218.07:43:48.01#ibcon#about to read 6, iclass 12, count 2 2006.218.07:43:48.01#ibcon#read 6, iclass 12, count 2 2006.218.07:43:48.01#ibcon#end of sib2, iclass 12, count 2 2006.218.07:43:48.01#ibcon#*mode == 0, iclass 12, count 2 2006.218.07:43:48.01#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.218.07:43:48.01#ibcon#[25=AT01-05\r\n] 2006.218.07:43:48.01#ibcon#*before write, iclass 12, count 2 2006.218.07:43:48.01#ibcon#enter sib2, iclass 12, count 2 2006.218.07:43:48.01#ibcon#flushed, iclass 12, count 2 2006.218.07:43:48.01#ibcon#about to write, iclass 12, count 2 2006.218.07:43:48.01#ibcon#wrote, iclass 12, count 2 2006.218.07:43:48.01#ibcon#about to read 3, iclass 12, count 2 2006.218.07:43:48.04#ibcon#read 3, iclass 12, count 2 2006.218.07:43:48.04#ibcon#about to read 4, iclass 12, count 2 2006.218.07:43:48.04#ibcon#read 4, iclass 12, count 2 2006.218.07:43:48.04#ibcon#about to read 5, iclass 12, count 2 2006.218.07:43:48.04#ibcon#read 5, iclass 12, count 2 2006.218.07:43:48.04#ibcon#about to read 6, iclass 12, count 2 2006.218.07:43:48.04#ibcon#read 6, iclass 12, count 2 2006.218.07:43:48.04#ibcon#end of sib2, iclass 12, count 2 2006.218.07:43:48.04#ibcon#*after write, iclass 12, count 2 2006.218.07:43:48.04#ibcon#*before return 0, iclass 12, count 2 2006.218.07:43:48.04#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.218.07:43:48.04#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.218.07:43:48.04#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.218.07:43:48.04#ibcon#ireg 7 cls_cnt 0 2006.218.07:43:48.04#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.218.07:43:48.16#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.218.07:43:48.16#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.218.07:43:48.16#ibcon#enter wrdev, iclass 12, count 0 2006.218.07:43:48.16#ibcon#first serial, iclass 12, count 0 2006.218.07:43:48.16#ibcon#enter sib2, iclass 12, count 0 2006.218.07:43:48.16#ibcon#flushed, iclass 12, count 0 2006.218.07:43:48.16#ibcon#about to write, iclass 12, count 0 2006.218.07:43:48.16#ibcon#wrote, iclass 12, count 0 2006.218.07:43:48.16#ibcon#about to read 3, iclass 12, count 0 2006.218.07:43:48.18#ibcon#read 3, iclass 12, count 0 2006.218.07:43:48.18#ibcon#about to read 4, iclass 12, count 0 2006.218.07:43:48.18#ibcon#read 4, iclass 12, count 0 2006.218.07:43:48.18#ibcon#about to read 5, iclass 12, count 0 2006.218.07:43:48.18#ibcon#read 5, iclass 12, count 0 2006.218.07:43:48.18#ibcon#about to read 6, iclass 12, count 0 2006.218.07:43:48.18#ibcon#read 6, iclass 12, count 0 2006.218.07:43:48.18#ibcon#end of sib2, iclass 12, count 0 2006.218.07:43:48.18#ibcon#*mode == 0, iclass 12, count 0 2006.218.07:43:48.18#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.218.07:43:48.18#ibcon#[25=USB\r\n] 2006.218.07:43:48.18#ibcon#*before write, iclass 12, count 0 2006.218.07:43:48.18#ibcon#enter sib2, iclass 12, count 0 2006.218.07:43:48.18#ibcon#flushed, iclass 12, count 0 2006.218.07:43:48.18#ibcon#about to write, iclass 12, count 0 2006.218.07:43:48.18#ibcon#wrote, iclass 12, count 0 2006.218.07:43:48.18#ibcon#about to read 3, iclass 12, count 0 2006.218.07:43:48.21#ibcon#read 3, iclass 12, count 0 2006.218.07:43:48.21#ibcon#about to read 4, iclass 12, count 0 2006.218.07:43:48.21#ibcon#read 4, iclass 12, count 0 2006.218.07:43:48.21#ibcon#about to read 5, iclass 12, count 0 2006.218.07:43:48.21#ibcon#read 5, iclass 12, count 0 2006.218.07:43:48.21#ibcon#about to read 6, iclass 12, count 0 2006.218.07:43:48.21#ibcon#read 6, iclass 12, count 0 2006.218.07:43:48.21#ibcon#end of sib2, iclass 12, count 0 2006.218.07:43:48.21#ibcon#*after write, iclass 12, count 0 2006.218.07:43:48.21#ibcon#*before return 0, iclass 12, count 0 2006.218.07:43:48.21#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.218.07:43:48.21#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.218.07:43:48.21#ibcon#about to clear, iclass 12 cls_cnt 0 2006.218.07:43:48.21#ibcon#cleared, iclass 12 cls_cnt 0 2006.218.07:43:48.21$vc4f8/valo=2,572.99 2006.218.07:43:48.21#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.218.07:43:48.21#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.218.07:43:48.21#ibcon#ireg 17 cls_cnt 0 2006.218.07:43:48.21#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.218.07:43:48.21#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.218.07:43:48.21#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.218.07:43:48.21#ibcon#enter wrdev, iclass 14, count 0 2006.218.07:43:48.21#ibcon#first serial, iclass 14, count 0 2006.218.07:43:48.21#ibcon#enter sib2, iclass 14, count 0 2006.218.07:43:48.21#ibcon#flushed, iclass 14, count 0 2006.218.07:43:48.21#ibcon#about to write, iclass 14, count 0 2006.218.07:43:48.21#ibcon#wrote, iclass 14, count 0 2006.218.07:43:48.21#ibcon#about to read 3, iclass 14, count 0 2006.218.07:43:48.23#ibcon#read 3, iclass 14, count 0 2006.218.07:43:48.23#ibcon#about to read 4, iclass 14, count 0 2006.218.07:43:48.23#ibcon#read 4, iclass 14, count 0 2006.218.07:43:48.23#ibcon#about to read 5, iclass 14, count 0 2006.218.07:43:48.23#ibcon#read 5, iclass 14, count 0 2006.218.07:43:48.23#ibcon#about to read 6, iclass 14, count 0 2006.218.07:43:48.23#ibcon#read 6, iclass 14, count 0 2006.218.07:43:48.23#ibcon#end of sib2, iclass 14, count 0 2006.218.07:43:48.23#ibcon#*mode == 0, iclass 14, count 0 2006.218.07:43:48.23#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.218.07:43:48.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.218.07:43:48.23#ibcon#*before write, iclass 14, count 0 2006.218.07:43:48.23#ibcon#enter sib2, iclass 14, count 0 2006.218.07:43:48.23#ibcon#flushed, iclass 14, count 0 2006.218.07:43:48.23#ibcon#about to write, iclass 14, count 0 2006.218.07:43:48.23#ibcon#wrote, iclass 14, count 0 2006.218.07:43:48.23#ibcon#about to read 3, iclass 14, count 0 2006.218.07:43:48.27#ibcon#read 3, iclass 14, count 0 2006.218.07:43:48.27#ibcon#about to read 4, iclass 14, count 0 2006.218.07:43:48.27#ibcon#read 4, iclass 14, count 0 2006.218.07:43:48.27#ibcon#about to read 5, iclass 14, count 0 2006.218.07:43:48.27#ibcon#read 5, iclass 14, count 0 2006.218.07:43:48.27#ibcon#about to read 6, iclass 14, count 0 2006.218.07:43:48.27#ibcon#read 6, iclass 14, count 0 2006.218.07:43:48.27#ibcon#end of sib2, iclass 14, count 0 2006.218.07:43:48.27#ibcon#*after write, iclass 14, count 0 2006.218.07:43:48.27#ibcon#*before return 0, iclass 14, count 0 2006.218.07:43:48.27#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.218.07:43:48.27#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.218.07:43:48.27#ibcon#about to clear, iclass 14 cls_cnt 0 2006.218.07:43:48.27#ibcon#cleared, iclass 14 cls_cnt 0 2006.218.07:43:48.27$vc4f8/va=2,4 2006.218.07:43:48.27#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.218.07:43:48.27#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.218.07:43:48.27#ibcon#ireg 11 cls_cnt 2 2006.218.07:43:48.27#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.218.07:43:48.33#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.218.07:43:48.33#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.218.07:43:48.33#ibcon#enter wrdev, iclass 16, count 2 2006.218.07:43:48.33#ibcon#first serial, iclass 16, count 2 2006.218.07:43:48.33#ibcon#enter sib2, iclass 16, count 2 2006.218.07:43:48.33#ibcon#flushed, iclass 16, count 2 2006.218.07:43:48.33#ibcon#about to write, iclass 16, count 2 2006.218.07:43:48.33#ibcon#wrote, iclass 16, count 2 2006.218.07:43:48.33#ibcon#about to read 3, iclass 16, count 2 2006.218.07:43:48.35#ibcon#read 3, iclass 16, count 2 2006.218.07:43:48.35#ibcon#about to read 4, iclass 16, count 2 2006.218.07:43:48.35#ibcon#read 4, iclass 16, count 2 2006.218.07:43:48.35#ibcon#about to read 5, iclass 16, count 2 2006.218.07:43:48.35#ibcon#read 5, iclass 16, count 2 2006.218.07:43:48.35#ibcon#about to read 6, iclass 16, count 2 2006.218.07:43:48.35#ibcon#read 6, iclass 16, count 2 2006.218.07:43:48.35#ibcon#end of sib2, iclass 16, count 2 2006.218.07:43:48.35#ibcon#*mode == 0, iclass 16, count 2 2006.218.07:43:48.35#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.218.07:43:48.35#ibcon#[25=AT02-04\r\n] 2006.218.07:43:48.35#ibcon#*before write, iclass 16, count 2 2006.218.07:43:48.35#ibcon#enter sib2, iclass 16, count 2 2006.218.07:43:48.35#ibcon#flushed, iclass 16, count 2 2006.218.07:43:48.35#ibcon#about to write, iclass 16, count 2 2006.218.07:43:48.35#ibcon#wrote, iclass 16, count 2 2006.218.07:43:48.35#ibcon#about to read 3, iclass 16, count 2 2006.218.07:43:48.38#ibcon#read 3, iclass 16, count 2 2006.218.07:43:48.38#ibcon#about to read 4, iclass 16, count 2 2006.218.07:43:48.38#ibcon#read 4, iclass 16, count 2 2006.218.07:43:48.38#ibcon#about to read 5, iclass 16, count 2 2006.218.07:43:48.38#ibcon#read 5, iclass 16, count 2 2006.218.07:43:48.38#ibcon#about to read 6, iclass 16, count 2 2006.218.07:43:48.38#ibcon#read 6, iclass 16, count 2 2006.218.07:43:48.38#ibcon#end of sib2, iclass 16, count 2 2006.218.07:43:48.38#ibcon#*after write, iclass 16, count 2 2006.218.07:43:48.38#ibcon#*before return 0, iclass 16, count 2 2006.218.07:43:48.38#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.218.07:43:48.38#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.218.07:43:48.38#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.218.07:43:48.38#ibcon#ireg 7 cls_cnt 0 2006.218.07:43:48.38#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.218.07:43:48.50#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.218.07:43:48.50#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.218.07:43:48.50#ibcon#enter wrdev, iclass 16, count 0 2006.218.07:43:48.50#ibcon#first serial, iclass 16, count 0 2006.218.07:43:48.50#ibcon#enter sib2, iclass 16, count 0 2006.218.07:43:48.50#ibcon#flushed, iclass 16, count 0 2006.218.07:43:48.50#ibcon#about to write, iclass 16, count 0 2006.218.07:43:48.50#ibcon#wrote, iclass 16, count 0 2006.218.07:43:48.50#ibcon#about to read 3, iclass 16, count 0 2006.218.07:43:48.52#ibcon#read 3, iclass 16, count 0 2006.218.07:43:48.52#ibcon#about to read 4, iclass 16, count 0 2006.218.07:43:48.52#ibcon#read 4, iclass 16, count 0 2006.218.07:43:48.52#ibcon#about to read 5, iclass 16, count 0 2006.218.07:43:48.52#ibcon#read 5, iclass 16, count 0 2006.218.07:43:48.52#ibcon#about to read 6, iclass 16, count 0 2006.218.07:43:48.52#ibcon#read 6, iclass 16, count 0 2006.218.07:43:48.52#ibcon#end of sib2, iclass 16, count 0 2006.218.07:43:48.52#ibcon#*mode == 0, iclass 16, count 0 2006.218.07:43:48.52#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.218.07:43:48.52#ibcon#[25=USB\r\n] 2006.218.07:43:48.52#ibcon#*before write, iclass 16, count 0 2006.218.07:43:48.52#ibcon#enter sib2, iclass 16, count 0 2006.218.07:43:48.52#ibcon#flushed, iclass 16, count 0 2006.218.07:43:48.52#ibcon#about to write, iclass 16, count 0 2006.218.07:43:48.52#ibcon#wrote, iclass 16, count 0 2006.218.07:43:48.52#ibcon#about to read 3, iclass 16, count 0 2006.218.07:43:48.55#ibcon#read 3, iclass 16, count 0 2006.218.07:43:48.55#ibcon#about to read 4, iclass 16, count 0 2006.218.07:43:48.55#ibcon#read 4, iclass 16, count 0 2006.218.07:43:48.55#ibcon#about to read 5, iclass 16, count 0 2006.218.07:43:48.55#ibcon#read 5, iclass 16, count 0 2006.218.07:43:48.55#ibcon#about to read 6, iclass 16, count 0 2006.218.07:43:48.55#ibcon#read 6, iclass 16, count 0 2006.218.07:43:48.55#ibcon#end of sib2, iclass 16, count 0 2006.218.07:43:48.55#ibcon#*after write, iclass 16, count 0 2006.218.07:43:48.55#ibcon#*before return 0, iclass 16, count 0 2006.218.07:43:48.55#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.218.07:43:48.55#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.218.07:43:48.55#ibcon#about to clear, iclass 16 cls_cnt 0 2006.218.07:43:48.55#ibcon#cleared, iclass 16 cls_cnt 0 2006.218.07:43:48.55$vc4f8/valo=3,672.99 2006.218.07:43:48.55#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.218.07:43:48.55#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.218.07:43:48.55#ibcon#ireg 17 cls_cnt 0 2006.218.07:43:48.55#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.218.07:43:48.55#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.218.07:43:48.55#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.218.07:43:48.55#ibcon#enter wrdev, iclass 18, count 0 2006.218.07:43:48.55#ibcon#first serial, iclass 18, count 0 2006.218.07:43:48.55#ibcon#enter sib2, iclass 18, count 0 2006.218.07:43:48.55#ibcon#flushed, iclass 18, count 0 2006.218.07:43:48.55#ibcon#about to write, iclass 18, count 0 2006.218.07:43:48.55#ibcon#wrote, iclass 18, count 0 2006.218.07:43:48.55#ibcon#about to read 3, iclass 18, count 0 2006.218.07:43:48.57#ibcon#read 3, iclass 18, count 0 2006.218.07:43:48.57#ibcon#about to read 4, iclass 18, count 0 2006.218.07:43:48.57#ibcon#read 4, iclass 18, count 0 2006.218.07:43:48.57#ibcon#about to read 5, iclass 18, count 0 2006.218.07:43:48.57#ibcon#read 5, iclass 18, count 0 2006.218.07:43:48.57#ibcon#about to read 6, iclass 18, count 0 2006.218.07:43:48.57#ibcon#read 6, iclass 18, count 0 2006.218.07:43:48.57#ibcon#end of sib2, iclass 18, count 0 2006.218.07:43:48.57#ibcon#*mode == 0, iclass 18, count 0 2006.218.07:43:48.57#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.218.07:43:48.57#ibcon#[26=FRQ=03,672.99\r\n] 2006.218.07:43:48.57#ibcon#*before write, iclass 18, count 0 2006.218.07:43:48.57#ibcon#enter sib2, iclass 18, count 0 2006.218.07:43:48.57#ibcon#flushed, iclass 18, count 0 2006.218.07:43:48.57#ibcon#about to write, iclass 18, count 0 2006.218.07:43:48.57#ibcon#wrote, iclass 18, count 0 2006.218.07:43:48.57#ibcon#about to read 3, iclass 18, count 0 2006.218.07:43:48.61#ibcon#read 3, iclass 18, count 0 2006.218.07:43:48.61#ibcon#about to read 4, iclass 18, count 0 2006.218.07:43:48.61#ibcon#read 4, iclass 18, count 0 2006.218.07:43:48.61#ibcon#about to read 5, iclass 18, count 0 2006.218.07:43:48.61#ibcon#read 5, iclass 18, count 0 2006.218.07:43:48.61#ibcon#about to read 6, iclass 18, count 0 2006.218.07:43:48.61#ibcon#read 6, iclass 18, count 0 2006.218.07:43:48.61#ibcon#end of sib2, iclass 18, count 0 2006.218.07:43:48.61#ibcon#*after write, iclass 18, count 0 2006.218.07:43:48.61#ibcon#*before return 0, iclass 18, count 0 2006.218.07:43:48.61#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.218.07:43:48.61#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.218.07:43:48.61#ibcon#about to clear, iclass 18 cls_cnt 0 2006.218.07:43:48.61#ibcon#cleared, iclass 18 cls_cnt 0 2006.218.07:43:48.61$vc4f8/va=3,4 2006.218.07:43:48.61#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.218.07:43:48.61#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.218.07:43:48.61#ibcon#ireg 11 cls_cnt 2 2006.218.07:43:48.61#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.218.07:43:48.67#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.218.07:43:48.67#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.218.07:43:48.67#ibcon#enter wrdev, iclass 20, count 2 2006.218.07:43:48.67#ibcon#first serial, iclass 20, count 2 2006.218.07:43:48.67#ibcon#enter sib2, iclass 20, count 2 2006.218.07:43:48.67#ibcon#flushed, iclass 20, count 2 2006.218.07:43:48.67#ibcon#about to write, iclass 20, count 2 2006.218.07:43:48.67#ibcon#wrote, iclass 20, count 2 2006.218.07:43:48.67#ibcon#about to read 3, iclass 20, count 2 2006.218.07:43:48.69#ibcon#read 3, iclass 20, count 2 2006.218.07:43:48.69#ibcon#about to read 4, iclass 20, count 2 2006.218.07:43:48.69#ibcon#read 4, iclass 20, count 2 2006.218.07:43:48.69#ibcon#about to read 5, iclass 20, count 2 2006.218.07:43:48.69#ibcon#read 5, iclass 20, count 2 2006.218.07:43:48.69#ibcon#about to read 6, iclass 20, count 2 2006.218.07:43:48.69#ibcon#read 6, iclass 20, count 2 2006.218.07:43:48.69#ibcon#end of sib2, iclass 20, count 2 2006.218.07:43:48.69#ibcon#*mode == 0, iclass 20, count 2 2006.218.07:43:48.69#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.218.07:43:48.69#ibcon#[25=AT03-04\r\n] 2006.218.07:43:48.69#ibcon#*before write, iclass 20, count 2 2006.218.07:43:48.69#ibcon#enter sib2, iclass 20, count 2 2006.218.07:43:48.69#ibcon#flushed, iclass 20, count 2 2006.218.07:43:48.69#ibcon#about to write, iclass 20, count 2 2006.218.07:43:48.69#ibcon#wrote, iclass 20, count 2 2006.218.07:43:48.69#ibcon#about to read 3, iclass 20, count 2 2006.218.07:43:48.73#ibcon#read 3, iclass 20, count 2 2006.218.07:43:48.73#ibcon#about to read 4, iclass 20, count 2 2006.218.07:43:48.73#ibcon#read 4, iclass 20, count 2 2006.218.07:43:48.73#ibcon#about to read 5, iclass 20, count 2 2006.218.07:43:48.73#ibcon#read 5, iclass 20, count 2 2006.218.07:43:48.73#ibcon#about to read 6, iclass 20, count 2 2006.218.07:43:48.73#ibcon#read 6, iclass 20, count 2 2006.218.07:43:48.73#ibcon#end of sib2, iclass 20, count 2 2006.218.07:43:48.73#ibcon#*after write, iclass 20, count 2 2006.218.07:43:48.73#ibcon#*before return 0, iclass 20, count 2 2006.218.07:43:48.73#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.218.07:43:48.73#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.218.07:43:48.73#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.218.07:43:48.73#ibcon#ireg 7 cls_cnt 0 2006.218.07:43:48.73#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.218.07:43:48.85#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.218.07:43:48.85#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.218.07:43:48.85#ibcon#enter wrdev, iclass 20, count 0 2006.218.07:43:48.85#ibcon#first serial, iclass 20, count 0 2006.218.07:43:48.85#ibcon#enter sib2, iclass 20, count 0 2006.218.07:43:48.85#ibcon#flushed, iclass 20, count 0 2006.218.07:43:48.85#ibcon#about to write, iclass 20, count 0 2006.218.07:43:48.85#ibcon#wrote, iclass 20, count 0 2006.218.07:43:48.85#ibcon#about to read 3, iclass 20, count 0 2006.218.07:43:48.87#ibcon#read 3, iclass 20, count 0 2006.218.07:43:48.87#ibcon#about to read 4, iclass 20, count 0 2006.218.07:43:48.87#ibcon#read 4, iclass 20, count 0 2006.218.07:43:48.87#ibcon#about to read 5, iclass 20, count 0 2006.218.07:43:48.87#ibcon#read 5, iclass 20, count 0 2006.218.07:43:48.87#ibcon#about to read 6, iclass 20, count 0 2006.218.07:43:48.87#ibcon#read 6, iclass 20, count 0 2006.218.07:43:48.87#ibcon#end of sib2, iclass 20, count 0 2006.218.07:43:48.87#ibcon#*mode == 0, iclass 20, count 0 2006.218.07:43:48.87#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.218.07:43:48.87#ibcon#[25=USB\r\n] 2006.218.07:43:48.87#ibcon#*before write, iclass 20, count 0 2006.218.07:43:48.87#ibcon#enter sib2, iclass 20, count 0 2006.218.07:43:48.87#ibcon#flushed, iclass 20, count 0 2006.218.07:43:48.87#ibcon#about to write, iclass 20, count 0 2006.218.07:43:48.87#ibcon#wrote, iclass 20, count 0 2006.218.07:43:48.87#ibcon#about to read 3, iclass 20, count 0 2006.218.07:43:48.90#ibcon#read 3, iclass 20, count 0 2006.218.07:43:48.90#ibcon#about to read 4, iclass 20, count 0 2006.218.07:43:48.90#ibcon#read 4, iclass 20, count 0 2006.218.07:43:48.90#ibcon#about to read 5, iclass 20, count 0 2006.218.07:43:48.90#ibcon#read 5, iclass 20, count 0 2006.218.07:43:48.90#ibcon#about to read 6, iclass 20, count 0 2006.218.07:43:48.90#ibcon#read 6, iclass 20, count 0 2006.218.07:43:48.90#ibcon#end of sib2, iclass 20, count 0 2006.218.07:43:48.90#ibcon#*after write, iclass 20, count 0 2006.218.07:43:48.90#ibcon#*before return 0, iclass 20, count 0 2006.218.07:43:48.90#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.218.07:43:48.90#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.218.07:43:48.90#ibcon#about to clear, iclass 20 cls_cnt 0 2006.218.07:43:48.90#ibcon#cleared, iclass 20 cls_cnt 0 2006.218.07:43:48.90$vc4f8/valo=4,832.99 2006.218.07:43:48.90#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.218.07:43:48.90#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.218.07:43:48.90#ibcon#ireg 17 cls_cnt 0 2006.218.07:43:48.90#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.218.07:43:48.90#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.218.07:43:48.90#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.218.07:43:48.90#ibcon#enter wrdev, iclass 22, count 0 2006.218.07:43:48.90#ibcon#first serial, iclass 22, count 0 2006.218.07:43:48.90#ibcon#enter sib2, iclass 22, count 0 2006.218.07:43:48.90#ibcon#flushed, iclass 22, count 0 2006.218.07:43:48.90#ibcon#about to write, iclass 22, count 0 2006.218.07:43:48.90#ibcon#wrote, iclass 22, count 0 2006.218.07:43:48.90#ibcon#about to read 3, iclass 22, count 0 2006.218.07:43:48.92#ibcon#read 3, iclass 22, count 0 2006.218.07:43:48.92#ibcon#about to read 4, iclass 22, count 0 2006.218.07:43:48.92#ibcon#read 4, iclass 22, count 0 2006.218.07:43:48.92#ibcon#about to read 5, iclass 22, count 0 2006.218.07:43:48.92#ibcon#read 5, iclass 22, count 0 2006.218.07:43:48.92#ibcon#about to read 6, iclass 22, count 0 2006.218.07:43:48.92#ibcon#read 6, iclass 22, count 0 2006.218.07:43:48.92#ibcon#end of sib2, iclass 22, count 0 2006.218.07:43:48.92#ibcon#*mode == 0, iclass 22, count 0 2006.218.07:43:48.92#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.218.07:43:48.92#ibcon#[26=FRQ=04,832.99\r\n] 2006.218.07:43:48.92#ibcon#*before write, iclass 22, count 0 2006.218.07:43:48.92#ibcon#enter sib2, iclass 22, count 0 2006.218.07:43:48.92#ibcon#flushed, iclass 22, count 0 2006.218.07:43:48.92#ibcon#about to write, iclass 22, count 0 2006.218.07:43:48.92#ibcon#wrote, iclass 22, count 0 2006.218.07:43:48.92#ibcon#about to read 3, iclass 22, count 0 2006.218.07:43:48.96#ibcon#read 3, iclass 22, count 0 2006.218.07:43:48.96#ibcon#about to read 4, iclass 22, count 0 2006.218.07:43:48.96#ibcon#read 4, iclass 22, count 0 2006.218.07:43:48.96#ibcon#about to read 5, iclass 22, count 0 2006.218.07:43:48.96#ibcon#read 5, iclass 22, count 0 2006.218.07:43:48.96#ibcon#about to read 6, iclass 22, count 0 2006.218.07:43:48.96#ibcon#read 6, iclass 22, count 0 2006.218.07:43:48.96#ibcon#end of sib2, iclass 22, count 0 2006.218.07:43:48.96#ibcon#*after write, iclass 22, count 0 2006.218.07:43:48.96#ibcon#*before return 0, iclass 22, count 0 2006.218.07:43:48.96#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.218.07:43:48.96#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.218.07:43:48.96#ibcon#about to clear, iclass 22 cls_cnt 0 2006.218.07:43:48.96#ibcon#cleared, iclass 22 cls_cnt 0 2006.218.07:43:48.96$vc4f8/va=4,4 2006.218.07:43:48.96#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.218.07:43:48.96#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.218.07:43:48.96#ibcon#ireg 11 cls_cnt 2 2006.218.07:43:48.96#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.218.07:43:49.02#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.218.07:43:49.02#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.218.07:43:49.02#ibcon#enter wrdev, iclass 24, count 2 2006.218.07:43:49.02#ibcon#first serial, iclass 24, count 2 2006.218.07:43:49.02#ibcon#enter sib2, iclass 24, count 2 2006.218.07:43:49.02#ibcon#flushed, iclass 24, count 2 2006.218.07:43:49.02#ibcon#about to write, iclass 24, count 2 2006.218.07:43:49.02#ibcon#wrote, iclass 24, count 2 2006.218.07:43:49.02#ibcon#about to read 3, iclass 24, count 2 2006.218.07:43:49.04#ibcon#read 3, iclass 24, count 2 2006.218.07:43:49.04#ibcon#about to read 4, iclass 24, count 2 2006.218.07:43:49.04#ibcon#read 4, iclass 24, count 2 2006.218.07:43:49.04#ibcon#about to read 5, iclass 24, count 2 2006.218.07:43:49.04#ibcon#read 5, iclass 24, count 2 2006.218.07:43:49.04#ibcon#about to read 6, iclass 24, count 2 2006.218.07:43:49.04#ibcon#read 6, iclass 24, count 2 2006.218.07:43:49.04#ibcon#end of sib2, iclass 24, count 2 2006.218.07:43:49.04#ibcon#*mode == 0, iclass 24, count 2 2006.218.07:43:49.04#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.218.07:43:49.04#ibcon#[25=AT04-04\r\n] 2006.218.07:43:49.04#ibcon#*before write, iclass 24, count 2 2006.218.07:43:49.04#ibcon#enter sib2, iclass 24, count 2 2006.218.07:43:49.04#ibcon#flushed, iclass 24, count 2 2006.218.07:43:49.04#ibcon#about to write, iclass 24, count 2 2006.218.07:43:49.04#ibcon#wrote, iclass 24, count 2 2006.218.07:43:49.04#ibcon#about to read 3, iclass 24, count 2 2006.218.07:43:49.07#ibcon#read 3, iclass 24, count 2 2006.218.07:43:49.07#ibcon#about to read 4, iclass 24, count 2 2006.218.07:43:49.07#ibcon#read 4, iclass 24, count 2 2006.218.07:43:49.07#ibcon#about to read 5, iclass 24, count 2 2006.218.07:43:49.07#ibcon#read 5, iclass 24, count 2 2006.218.07:43:49.07#ibcon#about to read 6, iclass 24, count 2 2006.218.07:43:49.07#ibcon#read 6, iclass 24, count 2 2006.218.07:43:49.07#ibcon#end of sib2, iclass 24, count 2 2006.218.07:43:49.07#ibcon#*after write, iclass 24, count 2 2006.218.07:43:49.07#ibcon#*before return 0, iclass 24, count 2 2006.218.07:43:49.07#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.218.07:43:49.07#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.218.07:43:49.07#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.218.07:43:49.07#ibcon#ireg 7 cls_cnt 0 2006.218.07:43:49.07#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.218.07:43:49.19#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.218.07:43:49.19#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.218.07:43:49.19#ibcon#enter wrdev, iclass 24, count 0 2006.218.07:43:49.19#ibcon#first serial, iclass 24, count 0 2006.218.07:43:49.19#ibcon#enter sib2, iclass 24, count 0 2006.218.07:43:49.19#ibcon#flushed, iclass 24, count 0 2006.218.07:43:49.19#ibcon#about to write, iclass 24, count 0 2006.218.07:43:49.19#ibcon#wrote, iclass 24, count 0 2006.218.07:43:49.19#ibcon#about to read 3, iclass 24, count 0 2006.218.07:43:49.21#ibcon#read 3, iclass 24, count 0 2006.218.07:43:49.21#ibcon#about to read 4, iclass 24, count 0 2006.218.07:43:49.21#ibcon#read 4, iclass 24, count 0 2006.218.07:43:49.21#ibcon#about to read 5, iclass 24, count 0 2006.218.07:43:49.21#ibcon#read 5, iclass 24, count 0 2006.218.07:43:49.21#ibcon#about to read 6, iclass 24, count 0 2006.218.07:43:49.21#ibcon#read 6, iclass 24, count 0 2006.218.07:43:49.21#ibcon#end of sib2, iclass 24, count 0 2006.218.07:43:49.21#ibcon#*mode == 0, iclass 24, count 0 2006.218.07:43:49.21#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.218.07:43:49.21#ibcon#[25=USB\r\n] 2006.218.07:43:49.21#ibcon#*before write, iclass 24, count 0 2006.218.07:43:49.21#ibcon#enter sib2, iclass 24, count 0 2006.218.07:43:49.21#ibcon#flushed, iclass 24, count 0 2006.218.07:43:49.21#ibcon#about to write, iclass 24, count 0 2006.218.07:43:49.21#ibcon#wrote, iclass 24, count 0 2006.218.07:43:49.21#ibcon#about to read 3, iclass 24, count 0 2006.218.07:43:49.24#ibcon#read 3, iclass 24, count 0 2006.218.07:43:49.24#ibcon#about to read 4, iclass 24, count 0 2006.218.07:43:49.24#ibcon#read 4, iclass 24, count 0 2006.218.07:43:49.24#ibcon#about to read 5, iclass 24, count 0 2006.218.07:43:49.24#ibcon#read 5, iclass 24, count 0 2006.218.07:43:49.24#ibcon#about to read 6, iclass 24, count 0 2006.218.07:43:49.24#ibcon#read 6, iclass 24, count 0 2006.218.07:43:49.24#ibcon#end of sib2, iclass 24, count 0 2006.218.07:43:49.24#ibcon#*after write, iclass 24, count 0 2006.218.07:43:49.24#ibcon#*before return 0, iclass 24, count 0 2006.218.07:43:49.24#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.218.07:43:49.24#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.218.07:43:49.24#ibcon#about to clear, iclass 24 cls_cnt 0 2006.218.07:43:49.24#ibcon#cleared, iclass 24 cls_cnt 0 2006.218.07:43:49.24$vc4f8/valo=5,652.99 2006.218.07:43:49.24#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.218.07:43:49.24#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.218.07:43:49.24#ibcon#ireg 17 cls_cnt 0 2006.218.07:43:49.24#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.218.07:43:49.24#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.218.07:43:49.24#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.218.07:43:49.24#ibcon#enter wrdev, iclass 26, count 0 2006.218.07:43:49.24#ibcon#first serial, iclass 26, count 0 2006.218.07:43:49.24#ibcon#enter sib2, iclass 26, count 0 2006.218.07:43:49.24#ibcon#flushed, iclass 26, count 0 2006.218.07:43:49.24#ibcon#about to write, iclass 26, count 0 2006.218.07:43:49.24#ibcon#wrote, iclass 26, count 0 2006.218.07:43:49.24#ibcon#about to read 3, iclass 26, count 0 2006.218.07:43:49.26#ibcon#read 3, iclass 26, count 0 2006.218.07:43:49.26#ibcon#about to read 4, iclass 26, count 0 2006.218.07:43:49.26#ibcon#read 4, iclass 26, count 0 2006.218.07:43:49.26#ibcon#about to read 5, iclass 26, count 0 2006.218.07:43:49.26#ibcon#read 5, iclass 26, count 0 2006.218.07:43:49.26#ibcon#about to read 6, iclass 26, count 0 2006.218.07:43:49.26#ibcon#read 6, iclass 26, count 0 2006.218.07:43:49.26#ibcon#end of sib2, iclass 26, count 0 2006.218.07:43:49.26#ibcon#*mode == 0, iclass 26, count 0 2006.218.07:43:49.26#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.218.07:43:49.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.218.07:43:49.26#ibcon#*before write, iclass 26, count 0 2006.218.07:43:49.26#ibcon#enter sib2, iclass 26, count 0 2006.218.07:43:49.26#ibcon#flushed, iclass 26, count 0 2006.218.07:43:49.26#ibcon#about to write, iclass 26, count 0 2006.218.07:43:49.26#ibcon#wrote, iclass 26, count 0 2006.218.07:43:49.26#ibcon#about to read 3, iclass 26, count 0 2006.218.07:43:49.30#ibcon#read 3, iclass 26, count 0 2006.218.07:43:49.30#ibcon#about to read 4, iclass 26, count 0 2006.218.07:43:49.30#ibcon#read 4, iclass 26, count 0 2006.218.07:43:49.30#ibcon#about to read 5, iclass 26, count 0 2006.218.07:43:49.30#ibcon#read 5, iclass 26, count 0 2006.218.07:43:49.30#ibcon#about to read 6, iclass 26, count 0 2006.218.07:43:49.30#ibcon#read 6, iclass 26, count 0 2006.218.07:43:49.30#ibcon#end of sib2, iclass 26, count 0 2006.218.07:43:49.30#ibcon#*after write, iclass 26, count 0 2006.218.07:43:49.30#ibcon#*before return 0, iclass 26, count 0 2006.218.07:43:49.30#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.218.07:43:49.30#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.218.07:43:49.30#ibcon#about to clear, iclass 26 cls_cnt 0 2006.218.07:43:49.30#ibcon#cleared, iclass 26 cls_cnt 0 2006.218.07:43:49.30$vc4f8/va=5,7 2006.218.07:43:49.30#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.218.07:43:49.30#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.218.07:43:49.30#ibcon#ireg 11 cls_cnt 2 2006.218.07:43:49.30#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.218.07:43:49.36#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.218.07:43:49.36#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.218.07:43:49.36#ibcon#enter wrdev, iclass 28, count 2 2006.218.07:43:49.36#ibcon#first serial, iclass 28, count 2 2006.218.07:43:49.36#ibcon#enter sib2, iclass 28, count 2 2006.218.07:43:49.36#ibcon#flushed, iclass 28, count 2 2006.218.07:43:49.36#ibcon#about to write, iclass 28, count 2 2006.218.07:43:49.36#ibcon#wrote, iclass 28, count 2 2006.218.07:43:49.36#ibcon#about to read 3, iclass 28, count 2 2006.218.07:43:49.38#ibcon#read 3, iclass 28, count 2 2006.218.07:43:49.38#ibcon#about to read 4, iclass 28, count 2 2006.218.07:43:49.38#ibcon#read 4, iclass 28, count 2 2006.218.07:43:49.38#ibcon#about to read 5, iclass 28, count 2 2006.218.07:43:49.38#ibcon#read 5, iclass 28, count 2 2006.218.07:43:49.38#ibcon#about to read 6, iclass 28, count 2 2006.218.07:43:49.38#ibcon#read 6, iclass 28, count 2 2006.218.07:43:49.38#ibcon#end of sib2, iclass 28, count 2 2006.218.07:43:49.38#ibcon#*mode == 0, iclass 28, count 2 2006.218.07:43:49.38#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.218.07:43:49.38#ibcon#[25=AT05-07\r\n] 2006.218.07:43:49.38#ibcon#*before write, iclass 28, count 2 2006.218.07:43:49.38#ibcon#enter sib2, iclass 28, count 2 2006.218.07:43:49.38#ibcon#flushed, iclass 28, count 2 2006.218.07:43:49.38#ibcon#about to write, iclass 28, count 2 2006.218.07:43:49.38#ibcon#wrote, iclass 28, count 2 2006.218.07:43:49.38#ibcon#about to read 3, iclass 28, count 2 2006.218.07:43:49.41#ibcon#read 3, iclass 28, count 2 2006.218.07:43:49.41#ibcon#about to read 4, iclass 28, count 2 2006.218.07:43:49.41#ibcon#read 4, iclass 28, count 2 2006.218.07:43:49.41#ibcon#about to read 5, iclass 28, count 2 2006.218.07:43:49.41#ibcon#read 5, iclass 28, count 2 2006.218.07:43:49.41#ibcon#about to read 6, iclass 28, count 2 2006.218.07:43:49.41#ibcon#read 6, iclass 28, count 2 2006.218.07:43:49.41#ibcon#end of sib2, iclass 28, count 2 2006.218.07:43:49.41#ibcon#*after write, iclass 28, count 2 2006.218.07:43:49.41#ibcon#*before return 0, iclass 28, count 2 2006.218.07:43:49.41#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.218.07:43:49.41#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.218.07:43:49.41#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.218.07:43:49.41#ibcon#ireg 7 cls_cnt 0 2006.218.07:43:49.41#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.218.07:43:49.53#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.218.07:43:49.53#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.218.07:43:49.53#ibcon#enter wrdev, iclass 28, count 0 2006.218.07:43:49.53#ibcon#first serial, iclass 28, count 0 2006.218.07:43:49.53#ibcon#enter sib2, iclass 28, count 0 2006.218.07:43:49.53#ibcon#flushed, iclass 28, count 0 2006.218.07:43:49.53#ibcon#about to write, iclass 28, count 0 2006.218.07:43:49.53#ibcon#wrote, iclass 28, count 0 2006.218.07:43:49.53#ibcon#about to read 3, iclass 28, count 0 2006.218.07:43:49.55#ibcon#read 3, iclass 28, count 0 2006.218.07:43:49.55#ibcon#about to read 4, iclass 28, count 0 2006.218.07:43:49.55#ibcon#read 4, iclass 28, count 0 2006.218.07:43:49.55#ibcon#about to read 5, iclass 28, count 0 2006.218.07:43:49.55#ibcon#read 5, iclass 28, count 0 2006.218.07:43:49.55#ibcon#about to read 6, iclass 28, count 0 2006.218.07:43:49.55#ibcon#read 6, iclass 28, count 0 2006.218.07:43:49.55#ibcon#end of sib2, iclass 28, count 0 2006.218.07:43:49.55#ibcon#*mode == 0, iclass 28, count 0 2006.218.07:43:49.55#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.218.07:43:49.55#ibcon#[25=USB\r\n] 2006.218.07:43:49.55#ibcon#*before write, iclass 28, count 0 2006.218.07:43:49.55#ibcon#enter sib2, iclass 28, count 0 2006.218.07:43:49.55#ibcon#flushed, iclass 28, count 0 2006.218.07:43:49.55#ibcon#about to write, iclass 28, count 0 2006.218.07:43:49.55#ibcon#wrote, iclass 28, count 0 2006.218.07:43:49.55#ibcon#about to read 3, iclass 28, count 0 2006.218.07:43:49.58#ibcon#read 3, iclass 28, count 0 2006.218.07:43:49.58#ibcon#about to read 4, iclass 28, count 0 2006.218.07:43:49.58#ibcon#read 4, iclass 28, count 0 2006.218.07:43:49.58#ibcon#about to read 5, iclass 28, count 0 2006.218.07:43:49.58#ibcon#read 5, iclass 28, count 0 2006.218.07:43:49.58#ibcon#about to read 6, iclass 28, count 0 2006.218.07:43:49.58#ibcon#read 6, iclass 28, count 0 2006.218.07:43:49.58#ibcon#end of sib2, iclass 28, count 0 2006.218.07:43:49.58#ibcon#*after write, iclass 28, count 0 2006.218.07:43:49.58#ibcon#*before return 0, iclass 28, count 0 2006.218.07:43:49.58#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.218.07:43:49.58#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.218.07:43:49.58#ibcon#about to clear, iclass 28 cls_cnt 0 2006.218.07:43:49.58#ibcon#cleared, iclass 28 cls_cnt 0 2006.218.07:43:49.58$vc4f8/valo=6,772.99 2006.218.07:43:49.58#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.218.07:43:49.58#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.218.07:43:49.58#ibcon#ireg 17 cls_cnt 0 2006.218.07:43:49.58#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.218.07:43:49.58#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.218.07:43:49.58#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.218.07:43:49.58#ibcon#enter wrdev, iclass 30, count 0 2006.218.07:43:49.58#ibcon#first serial, iclass 30, count 0 2006.218.07:43:49.58#ibcon#enter sib2, iclass 30, count 0 2006.218.07:43:49.58#ibcon#flushed, iclass 30, count 0 2006.218.07:43:49.58#ibcon#about to write, iclass 30, count 0 2006.218.07:43:49.58#ibcon#wrote, iclass 30, count 0 2006.218.07:43:49.58#ibcon#about to read 3, iclass 30, count 0 2006.218.07:43:49.60#ibcon#read 3, iclass 30, count 0 2006.218.07:43:49.60#ibcon#about to read 4, iclass 30, count 0 2006.218.07:43:49.60#ibcon#read 4, iclass 30, count 0 2006.218.07:43:49.60#ibcon#about to read 5, iclass 30, count 0 2006.218.07:43:49.60#ibcon#read 5, iclass 30, count 0 2006.218.07:43:49.60#ibcon#about to read 6, iclass 30, count 0 2006.218.07:43:49.60#ibcon#read 6, iclass 30, count 0 2006.218.07:43:49.60#ibcon#end of sib2, iclass 30, count 0 2006.218.07:43:49.60#ibcon#*mode == 0, iclass 30, count 0 2006.218.07:43:49.60#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.218.07:43:49.60#ibcon#[26=FRQ=06,772.99\r\n] 2006.218.07:43:49.60#ibcon#*before write, iclass 30, count 0 2006.218.07:43:49.60#ibcon#enter sib2, iclass 30, count 0 2006.218.07:43:49.60#ibcon#flushed, iclass 30, count 0 2006.218.07:43:49.60#ibcon#about to write, iclass 30, count 0 2006.218.07:43:49.60#ibcon#wrote, iclass 30, count 0 2006.218.07:43:49.60#ibcon#about to read 3, iclass 30, count 0 2006.218.07:43:49.64#ibcon#read 3, iclass 30, count 0 2006.218.07:43:49.64#ibcon#about to read 4, iclass 30, count 0 2006.218.07:43:49.64#ibcon#read 4, iclass 30, count 0 2006.218.07:43:49.64#ibcon#about to read 5, iclass 30, count 0 2006.218.07:43:49.64#ibcon#read 5, iclass 30, count 0 2006.218.07:43:49.64#ibcon#about to read 6, iclass 30, count 0 2006.218.07:43:49.64#ibcon#read 6, iclass 30, count 0 2006.218.07:43:49.64#ibcon#end of sib2, iclass 30, count 0 2006.218.07:43:49.64#ibcon#*after write, iclass 30, count 0 2006.218.07:43:49.64#ibcon#*before return 0, iclass 30, count 0 2006.218.07:43:49.64#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.218.07:43:49.64#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.218.07:43:49.64#ibcon#about to clear, iclass 30 cls_cnt 0 2006.218.07:43:49.64#ibcon#cleared, iclass 30 cls_cnt 0 2006.218.07:43:49.64$vc4f8/va=6,6 2006.218.07:43:49.64#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.218.07:43:49.64#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.218.07:43:49.64#ibcon#ireg 11 cls_cnt 2 2006.218.07:43:49.64#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.218.07:43:49.70#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.218.07:43:49.70#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.218.07:43:49.70#ibcon#enter wrdev, iclass 32, count 2 2006.218.07:43:49.70#ibcon#first serial, iclass 32, count 2 2006.218.07:43:49.70#ibcon#enter sib2, iclass 32, count 2 2006.218.07:43:49.70#ibcon#flushed, iclass 32, count 2 2006.218.07:43:49.70#ibcon#about to write, iclass 32, count 2 2006.218.07:43:49.70#ibcon#wrote, iclass 32, count 2 2006.218.07:43:49.70#ibcon#about to read 3, iclass 32, count 2 2006.218.07:43:49.72#ibcon#read 3, iclass 32, count 2 2006.218.07:43:49.72#ibcon#about to read 4, iclass 32, count 2 2006.218.07:43:49.72#ibcon#read 4, iclass 32, count 2 2006.218.07:43:49.72#ibcon#about to read 5, iclass 32, count 2 2006.218.07:43:49.72#ibcon#read 5, iclass 32, count 2 2006.218.07:43:49.72#ibcon#about to read 6, iclass 32, count 2 2006.218.07:43:49.72#ibcon#read 6, iclass 32, count 2 2006.218.07:43:49.72#ibcon#end of sib2, iclass 32, count 2 2006.218.07:43:49.72#ibcon#*mode == 0, iclass 32, count 2 2006.218.07:43:49.72#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.218.07:43:49.72#ibcon#[25=AT06-06\r\n] 2006.218.07:43:49.72#ibcon#*before write, iclass 32, count 2 2006.218.07:43:49.72#ibcon#enter sib2, iclass 32, count 2 2006.218.07:43:49.72#ibcon#flushed, iclass 32, count 2 2006.218.07:43:49.72#ibcon#about to write, iclass 32, count 2 2006.218.07:43:49.72#ibcon#wrote, iclass 32, count 2 2006.218.07:43:49.72#ibcon#about to read 3, iclass 32, count 2 2006.218.07:43:49.75#ibcon#read 3, iclass 32, count 2 2006.218.07:43:49.75#ibcon#about to read 4, iclass 32, count 2 2006.218.07:43:49.75#ibcon#read 4, iclass 32, count 2 2006.218.07:43:49.75#ibcon#about to read 5, iclass 32, count 2 2006.218.07:43:49.75#ibcon#read 5, iclass 32, count 2 2006.218.07:43:49.75#ibcon#about to read 6, iclass 32, count 2 2006.218.07:43:49.75#ibcon#read 6, iclass 32, count 2 2006.218.07:43:49.75#ibcon#end of sib2, iclass 32, count 2 2006.218.07:43:49.75#ibcon#*after write, iclass 32, count 2 2006.218.07:43:49.75#ibcon#*before return 0, iclass 32, count 2 2006.218.07:43:49.75#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.218.07:43:49.75#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.218.07:43:49.75#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.218.07:43:49.75#ibcon#ireg 7 cls_cnt 0 2006.218.07:43:49.75#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.218.07:43:49.87#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.218.07:43:49.87#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.218.07:43:49.87#ibcon#enter wrdev, iclass 32, count 0 2006.218.07:43:49.87#ibcon#first serial, iclass 32, count 0 2006.218.07:43:49.87#ibcon#enter sib2, iclass 32, count 0 2006.218.07:43:49.87#ibcon#flushed, iclass 32, count 0 2006.218.07:43:49.87#ibcon#about to write, iclass 32, count 0 2006.218.07:43:49.87#ibcon#wrote, iclass 32, count 0 2006.218.07:43:49.87#ibcon#about to read 3, iclass 32, count 0 2006.218.07:43:49.89#ibcon#read 3, iclass 32, count 0 2006.218.07:43:49.89#ibcon#about to read 4, iclass 32, count 0 2006.218.07:43:49.89#ibcon#read 4, iclass 32, count 0 2006.218.07:43:49.89#ibcon#about to read 5, iclass 32, count 0 2006.218.07:43:49.89#ibcon#read 5, iclass 32, count 0 2006.218.07:43:49.89#ibcon#about to read 6, iclass 32, count 0 2006.218.07:43:49.89#ibcon#read 6, iclass 32, count 0 2006.218.07:43:49.89#ibcon#end of sib2, iclass 32, count 0 2006.218.07:43:49.89#ibcon#*mode == 0, iclass 32, count 0 2006.218.07:43:49.89#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.218.07:43:49.89#ibcon#[25=USB\r\n] 2006.218.07:43:49.89#ibcon#*before write, iclass 32, count 0 2006.218.07:43:49.89#ibcon#enter sib2, iclass 32, count 0 2006.218.07:43:49.89#ibcon#flushed, iclass 32, count 0 2006.218.07:43:49.89#ibcon#about to write, iclass 32, count 0 2006.218.07:43:49.89#ibcon#wrote, iclass 32, count 0 2006.218.07:43:49.89#ibcon#about to read 3, iclass 32, count 0 2006.218.07:43:49.92#ibcon#read 3, iclass 32, count 0 2006.218.07:43:49.92#ibcon#about to read 4, iclass 32, count 0 2006.218.07:43:49.92#ibcon#read 4, iclass 32, count 0 2006.218.07:43:49.92#ibcon#about to read 5, iclass 32, count 0 2006.218.07:43:49.92#ibcon#read 5, iclass 32, count 0 2006.218.07:43:49.92#ibcon#about to read 6, iclass 32, count 0 2006.218.07:43:49.92#ibcon#read 6, iclass 32, count 0 2006.218.07:43:49.92#ibcon#end of sib2, iclass 32, count 0 2006.218.07:43:49.92#ibcon#*after write, iclass 32, count 0 2006.218.07:43:49.92#ibcon#*before return 0, iclass 32, count 0 2006.218.07:43:49.92#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.218.07:43:49.92#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.218.07:43:49.92#ibcon#about to clear, iclass 32 cls_cnt 0 2006.218.07:43:49.92#ibcon#cleared, iclass 32 cls_cnt 0 2006.218.07:43:49.92$vc4f8/valo=7,832.99 2006.218.07:43:49.92#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.218.07:43:49.92#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.218.07:43:49.92#ibcon#ireg 17 cls_cnt 0 2006.218.07:43:49.92#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.218.07:43:49.92#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.218.07:43:49.92#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.218.07:43:49.92#ibcon#enter wrdev, iclass 34, count 0 2006.218.07:43:49.92#ibcon#first serial, iclass 34, count 0 2006.218.07:43:49.92#ibcon#enter sib2, iclass 34, count 0 2006.218.07:43:49.92#ibcon#flushed, iclass 34, count 0 2006.218.07:43:49.92#ibcon#about to write, iclass 34, count 0 2006.218.07:43:49.92#ibcon#wrote, iclass 34, count 0 2006.218.07:43:49.92#ibcon#about to read 3, iclass 34, count 0 2006.218.07:43:49.94#ibcon#read 3, iclass 34, count 0 2006.218.07:43:49.94#ibcon#about to read 4, iclass 34, count 0 2006.218.07:43:49.94#ibcon#read 4, iclass 34, count 0 2006.218.07:43:49.94#ibcon#about to read 5, iclass 34, count 0 2006.218.07:43:49.94#ibcon#read 5, iclass 34, count 0 2006.218.07:43:49.94#ibcon#about to read 6, iclass 34, count 0 2006.218.07:43:49.94#ibcon#read 6, iclass 34, count 0 2006.218.07:43:49.94#ibcon#end of sib2, iclass 34, count 0 2006.218.07:43:49.94#ibcon#*mode == 0, iclass 34, count 0 2006.218.07:43:49.94#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.218.07:43:49.94#ibcon#[26=FRQ=07,832.99\r\n] 2006.218.07:43:49.94#ibcon#*before write, iclass 34, count 0 2006.218.07:43:49.94#ibcon#enter sib2, iclass 34, count 0 2006.218.07:43:49.94#ibcon#flushed, iclass 34, count 0 2006.218.07:43:49.94#ibcon#about to write, iclass 34, count 0 2006.218.07:43:49.94#ibcon#wrote, iclass 34, count 0 2006.218.07:43:49.94#ibcon#about to read 3, iclass 34, count 0 2006.218.07:43:49.98#ibcon#read 3, iclass 34, count 0 2006.218.07:43:49.98#ibcon#about to read 4, iclass 34, count 0 2006.218.07:43:49.98#ibcon#read 4, iclass 34, count 0 2006.218.07:43:49.98#ibcon#about to read 5, iclass 34, count 0 2006.218.07:43:49.98#ibcon#read 5, iclass 34, count 0 2006.218.07:43:49.98#ibcon#about to read 6, iclass 34, count 0 2006.218.07:43:49.98#ibcon#read 6, iclass 34, count 0 2006.218.07:43:49.98#ibcon#end of sib2, iclass 34, count 0 2006.218.07:43:49.98#ibcon#*after write, iclass 34, count 0 2006.218.07:43:49.98#ibcon#*before return 0, iclass 34, count 0 2006.218.07:43:49.98#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.218.07:43:49.98#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.218.07:43:49.98#ibcon#about to clear, iclass 34 cls_cnt 0 2006.218.07:43:49.98#ibcon#cleared, iclass 34 cls_cnt 0 2006.218.07:43:49.98$vc4f8/va=7,6 2006.218.07:43:49.98#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.218.07:43:49.98#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.218.07:43:49.98#ibcon#ireg 11 cls_cnt 2 2006.218.07:43:49.98#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.218.07:43:50.04#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.218.07:43:50.04#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.218.07:43:50.04#ibcon#enter wrdev, iclass 36, count 2 2006.218.07:43:50.04#ibcon#first serial, iclass 36, count 2 2006.218.07:43:50.04#ibcon#enter sib2, iclass 36, count 2 2006.218.07:43:50.04#ibcon#flushed, iclass 36, count 2 2006.218.07:43:50.04#ibcon#about to write, iclass 36, count 2 2006.218.07:43:50.04#ibcon#wrote, iclass 36, count 2 2006.218.07:43:50.04#ibcon#about to read 3, iclass 36, count 2 2006.218.07:43:50.06#ibcon#read 3, iclass 36, count 2 2006.218.07:43:50.06#ibcon#about to read 4, iclass 36, count 2 2006.218.07:43:50.06#ibcon#read 4, iclass 36, count 2 2006.218.07:43:50.06#ibcon#about to read 5, iclass 36, count 2 2006.218.07:43:50.06#ibcon#read 5, iclass 36, count 2 2006.218.07:43:50.06#ibcon#about to read 6, iclass 36, count 2 2006.218.07:43:50.06#ibcon#read 6, iclass 36, count 2 2006.218.07:43:50.06#ibcon#end of sib2, iclass 36, count 2 2006.218.07:43:50.06#ibcon#*mode == 0, iclass 36, count 2 2006.218.07:43:50.06#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.218.07:43:50.06#ibcon#[25=AT07-06\r\n] 2006.218.07:43:50.06#ibcon#*before write, iclass 36, count 2 2006.218.07:43:50.06#ibcon#enter sib2, iclass 36, count 2 2006.218.07:43:50.06#ibcon#flushed, iclass 36, count 2 2006.218.07:43:50.06#ibcon#about to write, iclass 36, count 2 2006.218.07:43:50.06#ibcon#wrote, iclass 36, count 2 2006.218.07:43:50.06#ibcon#about to read 3, iclass 36, count 2 2006.218.07:43:50.09#ibcon#read 3, iclass 36, count 2 2006.218.07:43:50.09#ibcon#about to read 4, iclass 36, count 2 2006.218.07:43:50.09#ibcon#read 4, iclass 36, count 2 2006.218.07:43:50.09#ibcon#about to read 5, iclass 36, count 2 2006.218.07:43:50.09#ibcon#read 5, iclass 36, count 2 2006.218.07:43:50.09#ibcon#about to read 6, iclass 36, count 2 2006.218.07:43:50.09#ibcon#read 6, iclass 36, count 2 2006.218.07:43:50.09#ibcon#end of sib2, iclass 36, count 2 2006.218.07:43:50.09#ibcon#*after write, iclass 36, count 2 2006.218.07:43:50.09#ibcon#*before return 0, iclass 36, count 2 2006.218.07:43:50.09#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.218.07:43:50.09#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.218.07:43:50.09#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.218.07:43:50.09#ibcon#ireg 7 cls_cnt 0 2006.218.07:43:50.09#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.218.07:43:50.21#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.218.07:43:50.21#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.218.07:43:50.21#ibcon#enter wrdev, iclass 36, count 0 2006.218.07:43:50.21#ibcon#first serial, iclass 36, count 0 2006.218.07:43:50.21#ibcon#enter sib2, iclass 36, count 0 2006.218.07:43:50.21#ibcon#flushed, iclass 36, count 0 2006.218.07:43:50.21#ibcon#about to write, iclass 36, count 0 2006.218.07:43:50.21#ibcon#wrote, iclass 36, count 0 2006.218.07:43:50.21#ibcon#about to read 3, iclass 36, count 0 2006.218.07:43:50.23#ibcon#read 3, iclass 36, count 0 2006.218.07:43:50.23#ibcon#about to read 4, iclass 36, count 0 2006.218.07:43:50.23#ibcon#read 4, iclass 36, count 0 2006.218.07:43:50.23#ibcon#about to read 5, iclass 36, count 0 2006.218.07:43:50.23#ibcon#read 5, iclass 36, count 0 2006.218.07:43:50.23#ibcon#about to read 6, iclass 36, count 0 2006.218.07:43:50.23#ibcon#read 6, iclass 36, count 0 2006.218.07:43:50.23#ibcon#end of sib2, iclass 36, count 0 2006.218.07:43:50.23#ibcon#*mode == 0, iclass 36, count 0 2006.218.07:43:50.23#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.218.07:43:50.23#ibcon#[25=USB\r\n] 2006.218.07:43:50.23#ibcon#*before write, iclass 36, count 0 2006.218.07:43:50.23#ibcon#enter sib2, iclass 36, count 0 2006.218.07:43:50.23#ibcon#flushed, iclass 36, count 0 2006.218.07:43:50.23#ibcon#about to write, iclass 36, count 0 2006.218.07:43:50.23#ibcon#wrote, iclass 36, count 0 2006.218.07:43:50.23#ibcon#about to read 3, iclass 36, count 0 2006.218.07:43:50.26#ibcon#read 3, iclass 36, count 0 2006.218.07:43:50.26#ibcon#about to read 4, iclass 36, count 0 2006.218.07:43:50.26#ibcon#read 4, iclass 36, count 0 2006.218.07:43:50.26#ibcon#about to read 5, iclass 36, count 0 2006.218.07:43:50.26#ibcon#read 5, iclass 36, count 0 2006.218.07:43:50.26#ibcon#about to read 6, iclass 36, count 0 2006.218.07:43:50.26#ibcon#read 6, iclass 36, count 0 2006.218.07:43:50.26#ibcon#end of sib2, iclass 36, count 0 2006.218.07:43:50.26#ibcon#*after write, iclass 36, count 0 2006.218.07:43:50.26#ibcon#*before return 0, iclass 36, count 0 2006.218.07:43:50.26#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.218.07:43:50.26#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.218.07:43:50.26#ibcon#about to clear, iclass 36 cls_cnt 0 2006.218.07:43:50.26#ibcon#cleared, iclass 36 cls_cnt 0 2006.218.07:43:50.26$vc4f8/valo=8,852.99 2006.218.07:43:50.26#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.218.07:43:50.26#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.218.07:43:50.26#ibcon#ireg 17 cls_cnt 0 2006.218.07:43:50.26#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.218.07:43:50.26#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.218.07:43:50.26#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.218.07:43:50.26#ibcon#enter wrdev, iclass 38, count 0 2006.218.07:43:50.26#ibcon#first serial, iclass 38, count 0 2006.218.07:43:50.26#ibcon#enter sib2, iclass 38, count 0 2006.218.07:43:50.26#ibcon#flushed, iclass 38, count 0 2006.218.07:43:50.26#ibcon#about to write, iclass 38, count 0 2006.218.07:43:50.26#ibcon#wrote, iclass 38, count 0 2006.218.07:43:50.26#ibcon#about to read 3, iclass 38, count 0 2006.218.07:43:50.28#ibcon#read 3, iclass 38, count 0 2006.218.07:43:50.28#ibcon#about to read 4, iclass 38, count 0 2006.218.07:43:50.28#ibcon#read 4, iclass 38, count 0 2006.218.07:43:50.28#ibcon#about to read 5, iclass 38, count 0 2006.218.07:43:50.28#ibcon#read 5, iclass 38, count 0 2006.218.07:43:50.28#ibcon#about to read 6, iclass 38, count 0 2006.218.07:43:50.28#ibcon#read 6, iclass 38, count 0 2006.218.07:43:50.28#ibcon#end of sib2, iclass 38, count 0 2006.218.07:43:50.28#ibcon#*mode == 0, iclass 38, count 0 2006.218.07:43:50.28#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.218.07:43:50.28#ibcon#[26=FRQ=08,852.99\r\n] 2006.218.07:43:50.28#ibcon#*before write, iclass 38, count 0 2006.218.07:43:50.28#ibcon#enter sib2, iclass 38, count 0 2006.218.07:43:50.28#ibcon#flushed, iclass 38, count 0 2006.218.07:43:50.28#ibcon#about to write, iclass 38, count 0 2006.218.07:43:50.28#ibcon#wrote, iclass 38, count 0 2006.218.07:43:50.28#ibcon#about to read 3, iclass 38, count 0 2006.218.07:43:50.32#ibcon#read 3, iclass 38, count 0 2006.218.07:43:50.32#ibcon#about to read 4, iclass 38, count 0 2006.218.07:43:50.32#ibcon#read 4, iclass 38, count 0 2006.218.07:43:50.32#ibcon#about to read 5, iclass 38, count 0 2006.218.07:43:50.32#ibcon#read 5, iclass 38, count 0 2006.218.07:43:50.32#ibcon#about to read 6, iclass 38, count 0 2006.218.07:43:50.32#ibcon#read 6, iclass 38, count 0 2006.218.07:43:50.32#ibcon#end of sib2, iclass 38, count 0 2006.218.07:43:50.32#ibcon#*after write, iclass 38, count 0 2006.218.07:43:50.32#ibcon#*before return 0, iclass 38, count 0 2006.218.07:43:50.32#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.218.07:43:50.32#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.218.07:43:50.32#ibcon#about to clear, iclass 38 cls_cnt 0 2006.218.07:43:50.32#ibcon#cleared, iclass 38 cls_cnt 0 2006.218.07:43:50.32$vc4f8/va=8,7 2006.218.07:43:50.32#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.218.07:43:50.32#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.218.07:43:50.32#ibcon#ireg 11 cls_cnt 2 2006.218.07:43:50.32#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.218.07:43:50.38#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.218.07:43:50.38#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.218.07:43:50.38#ibcon#enter wrdev, iclass 40, count 2 2006.218.07:43:50.38#ibcon#first serial, iclass 40, count 2 2006.218.07:43:50.38#ibcon#enter sib2, iclass 40, count 2 2006.218.07:43:50.38#ibcon#flushed, iclass 40, count 2 2006.218.07:43:50.38#ibcon#about to write, iclass 40, count 2 2006.218.07:43:50.38#ibcon#wrote, iclass 40, count 2 2006.218.07:43:50.38#ibcon#about to read 3, iclass 40, count 2 2006.218.07:43:50.40#ibcon#read 3, iclass 40, count 2 2006.218.07:43:50.40#ibcon#about to read 4, iclass 40, count 2 2006.218.07:43:50.40#ibcon#read 4, iclass 40, count 2 2006.218.07:43:50.40#ibcon#about to read 5, iclass 40, count 2 2006.218.07:43:50.40#ibcon#read 5, iclass 40, count 2 2006.218.07:43:50.40#ibcon#about to read 6, iclass 40, count 2 2006.218.07:43:50.40#ibcon#read 6, iclass 40, count 2 2006.218.07:43:50.40#ibcon#end of sib2, iclass 40, count 2 2006.218.07:43:50.40#ibcon#*mode == 0, iclass 40, count 2 2006.218.07:43:50.40#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.218.07:43:50.40#ibcon#[25=AT08-07\r\n] 2006.218.07:43:50.40#ibcon#*before write, iclass 40, count 2 2006.218.07:43:50.40#ibcon#enter sib2, iclass 40, count 2 2006.218.07:43:50.40#ibcon#flushed, iclass 40, count 2 2006.218.07:43:50.40#ibcon#about to write, iclass 40, count 2 2006.218.07:43:50.40#ibcon#wrote, iclass 40, count 2 2006.218.07:43:50.40#ibcon#about to read 3, iclass 40, count 2 2006.218.07:43:50.43#ibcon#read 3, iclass 40, count 2 2006.218.07:43:50.43#ibcon#about to read 4, iclass 40, count 2 2006.218.07:43:50.43#ibcon#read 4, iclass 40, count 2 2006.218.07:43:50.43#ibcon#about to read 5, iclass 40, count 2 2006.218.07:43:50.43#ibcon#read 5, iclass 40, count 2 2006.218.07:43:50.43#ibcon#about to read 6, iclass 40, count 2 2006.218.07:43:50.43#ibcon#read 6, iclass 40, count 2 2006.218.07:43:50.43#ibcon#end of sib2, iclass 40, count 2 2006.218.07:43:50.43#ibcon#*after write, iclass 40, count 2 2006.218.07:43:50.43#ibcon#*before return 0, iclass 40, count 2 2006.218.07:43:50.43#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.218.07:43:50.43#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.218.07:43:50.43#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.218.07:43:50.43#ibcon#ireg 7 cls_cnt 0 2006.218.07:43:50.43#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.218.07:43:50.55#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.218.07:43:50.55#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.218.07:43:50.55#ibcon#enter wrdev, iclass 40, count 0 2006.218.07:43:50.55#ibcon#first serial, iclass 40, count 0 2006.218.07:43:50.55#ibcon#enter sib2, iclass 40, count 0 2006.218.07:43:50.55#ibcon#flushed, iclass 40, count 0 2006.218.07:43:50.55#ibcon#about to write, iclass 40, count 0 2006.218.07:43:50.55#ibcon#wrote, iclass 40, count 0 2006.218.07:43:50.55#ibcon#about to read 3, iclass 40, count 0 2006.218.07:43:50.57#ibcon#read 3, iclass 40, count 0 2006.218.07:43:50.57#ibcon#about to read 4, iclass 40, count 0 2006.218.07:43:50.57#ibcon#read 4, iclass 40, count 0 2006.218.07:43:50.57#ibcon#about to read 5, iclass 40, count 0 2006.218.07:43:50.57#ibcon#read 5, iclass 40, count 0 2006.218.07:43:50.57#ibcon#about to read 6, iclass 40, count 0 2006.218.07:43:50.57#ibcon#read 6, iclass 40, count 0 2006.218.07:43:50.57#ibcon#end of sib2, iclass 40, count 0 2006.218.07:43:50.57#ibcon#*mode == 0, iclass 40, count 0 2006.218.07:43:50.57#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.218.07:43:50.57#ibcon#[25=USB\r\n] 2006.218.07:43:50.57#ibcon#*before write, iclass 40, count 0 2006.218.07:43:50.57#ibcon#enter sib2, iclass 40, count 0 2006.218.07:43:50.57#ibcon#flushed, iclass 40, count 0 2006.218.07:43:50.57#ibcon#about to write, iclass 40, count 0 2006.218.07:43:50.57#ibcon#wrote, iclass 40, count 0 2006.218.07:43:50.57#ibcon#about to read 3, iclass 40, count 0 2006.218.07:43:50.60#ibcon#read 3, iclass 40, count 0 2006.218.07:43:50.60#ibcon#about to read 4, iclass 40, count 0 2006.218.07:43:50.60#ibcon#read 4, iclass 40, count 0 2006.218.07:43:50.60#ibcon#about to read 5, iclass 40, count 0 2006.218.07:43:50.60#ibcon#read 5, iclass 40, count 0 2006.218.07:43:50.60#ibcon#about to read 6, iclass 40, count 0 2006.218.07:43:50.60#ibcon#read 6, iclass 40, count 0 2006.218.07:43:50.60#ibcon#end of sib2, iclass 40, count 0 2006.218.07:43:50.60#ibcon#*after write, iclass 40, count 0 2006.218.07:43:50.60#ibcon#*before return 0, iclass 40, count 0 2006.218.07:43:50.60#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.218.07:43:50.60#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.218.07:43:50.60#ibcon#about to clear, iclass 40 cls_cnt 0 2006.218.07:43:50.60#ibcon#cleared, iclass 40 cls_cnt 0 2006.218.07:43:50.60$vc4f8/vblo=1,632.99 2006.218.07:43:50.60#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.218.07:43:50.60#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.218.07:43:50.60#ibcon#ireg 17 cls_cnt 0 2006.218.07:43:50.60#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.218.07:43:50.60#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.218.07:43:50.60#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.218.07:43:50.60#ibcon#enter wrdev, iclass 4, count 0 2006.218.07:43:50.60#ibcon#first serial, iclass 4, count 0 2006.218.07:43:50.60#ibcon#enter sib2, iclass 4, count 0 2006.218.07:43:50.60#ibcon#flushed, iclass 4, count 0 2006.218.07:43:50.60#ibcon#about to write, iclass 4, count 0 2006.218.07:43:50.60#ibcon#wrote, iclass 4, count 0 2006.218.07:43:50.60#ibcon#about to read 3, iclass 4, count 0 2006.218.07:43:50.62#ibcon#read 3, iclass 4, count 0 2006.218.07:43:50.62#ibcon#about to read 4, iclass 4, count 0 2006.218.07:43:50.62#ibcon#read 4, iclass 4, count 0 2006.218.07:43:50.62#ibcon#about to read 5, iclass 4, count 0 2006.218.07:43:50.62#ibcon#read 5, iclass 4, count 0 2006.218.07:43:50.62#ibcon#about to read 6, iclass 4, count 0 2006.218.07:43:50.62#ibcon#read 6, iclass 4, count 0 2006.218.07:43:50.62#ibcon#end of sib2, iclass 4, count 0 2006.218.07:43:50.62#ibcon#*mode == 0, iclass 4, count 0 2006.218.07:43:50.62#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.218.07:43:50.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.218.07:43:50.62#ibcon#*before write, iclass 4, count 0 2006.218.07:43:50.62#ibcon#enter sib2, iclass 4, count 0 2006.218.07:43:50.62#ibcon#flushed, iclass 4, count 0 2006.218.07:43:50.62#ibcon#about to write, iclass 4, count 0 2006.218.07:43:50.62#ibcon#wrote, iclass 4, count 0 2006.218.07:43:50.62#ibcon#about to read 3, iclass 4, count 0 2006.218.07:43:50.66#ibcon#read 3, iclass 4, count 0 2006.218.07:43:50.66#ibcon#about to read 4, iclass 4, count 0 2006.218.07:43:50.66#ibcon#read 4, iclass 4, count 0 2006.218.07:43:50.66#ibcon#about to read 5, iclass 4, count 0 2006.218.07:43:50.66#ibcon#read 5, iclass 4, count 0 2006.218.07:43:50.66#ibcon#about to read 6, iclass 4, count 0 2006.218.07:43:50.66#ibcon#read 6, iclass 4, count 0 2006.218.07:43:50.66#ibcon#end of sib2, iclass 4, count 0 2006.218.07:43:50.66#ibcon#*after write, iclass 4, count 0 2006.218.07:43:50.66#ibcon#*before return 0, iclass 4, count 0 2006.218.07:43:50.66#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.218.07:43:50.66#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.218.07:43:50.66#ibcon#about to clear, iclass 4 cls_cnt 0 2006.218.07:43:50.66#ibcon#cleared, iclass 4 cls_cnt 0 2006.218.07:43:50.66$vc4f8/vb=1,4 2006.218.07:43:50.66#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.218.07:43:50.66#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.218.07:43:50.66#ibcon#ireg 11 cls_cnt 2 2006.218.07:43:50.66#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.218.07:43:50.66#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.218.07:43:50.66#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.218.07:43:50.66#ibcon#enter wrdev, iclass 6, count 2 2006.218.07:43:50.66#ibcon#first serial, iclass 6, count 2 2006.218.07:43:50.66#ibcon#enter sib2, iclass 6, count 2 2006.218.07:43:50.66#ibcon#flushed, iclass 6, count 2 2006.218.07:43:50.66#ibcon#about to write, iclass 6, count 2 2006.218.07:43:50.66#ibcon#wrote, iclass 6, count 2 2006.218.07:43:50.66#ibcon#about to read 3, iclass 6, count 2 2006.218.07:43:50.68#ibcon#read 3, iclass 6, count 2 2006.218.07:43:50.68#ibcon#about to read 4, iclass 6, count 2 2006.218.07:43:50.68#ibcon#read 4, iclass 6, count 2 2006.218.07:43:50.68#ibcon#about to read 5, iclass 6, count 2 2006.218.07:43:50.68#ibcon#read 5, iclass 6, count 2 2006.218.07:43:50.68#ibcon#about to read 6, iclass 6, count 2 2006.218.07:43:50.68#ibcon#read 6, iclass 6, count 2 2006.218.07:43:50.68#ibcon#end of sib2, iclass 6, count 2 2006.218.07:43:50.68#ibcon#*mode == 0, iclass 6, count 2 2006.218.07:43:50.68#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.218.07:43:50.68#ibcon#[27=AT01-04\r\n] 2006.218.07:43:50.68#ibcon#*before write, iclass 6, count 2 2006.218.07:43:50.68#ibcon#enter sib2, iclass 6, count 2 2006.218.07:43:50.68#ibcon#flushed, iclass 6, count 2 2006.218.07:43:50.68#ibcon#about to write, iclass 6, count 2 2006.218.07:43:50.68#ibcon#wrote, iclass 6, count 2 2006.218.07:43:50.68#ibcon#about to read 3, iclass 6, count 2 2006.218.07:43:50.71#ibcon#read 3, iclass 6, count 2 2006.218.07:43:50.71#ibcon#about to read 4, iclass 6, count 2 2006.218.07:43:50.71#ibcon#read 4, iclass 6, count 2 2006.218.07:43:50.71#ibcon#about to read 5, iclass 6, count 2 2006.218.07:43:50.71#ibcon#read 5, iclass 6, count 2 2006.218.07:43:50.71#ibcon#about to read 6, iclass 6, count 2 2006.218.07:43:50.71#ibcon#read 6, iclass 6, count 2 2006.218.07:43:50.71#ibcon#end of sib2, iclass 6, count 2 2006.218.07:43:50.71#ibcon#*after write, iclass 6, count 2 2006.218.07:43:50.71#ibcon#*before return 0, iclass 6, count 2 2006.218.07:43:50.71#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.218.07:43:50.71#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.218.07:43:50.71#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.218.07:43:50.71#ibcon#ireg 7 cls_cnt 0 2006.218.07:43:50.71#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.218.07:43:50.83#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.218.07:43:50.83#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.218.07:43:50.83#ibcon#enter wrdev, iclass 6, count 0 2006.218.07:43:50.83#ibcon#first serial, iclass 6, count 0 2006.218.07:43:50.83#ibcon#enter sib2, iclass 6, count 0 2006.218.07:43:50.83#ibcon#flushed, iclass 6, count 0 2006.218.07:43:50.83#ibcon#about to write, iclass 6, count 0 2006.218.07:43:50.83#ibcon#wrote, iclass 6, count 0 2006.218.07:43:50.83#ibcon#about to read 3, iclass 6, count 0 2006.218.07:43:50.85#ibcon#read 3, iclass 6, count 0 2006.218.07:43:50.85#ibcon#about to read 4, iclass 6, count 0 2006.218.07:43:50.85#ibcon#read 4, iclass 6, count 0 2006.218.07:43:50.85#ibcon#about to read 5, iclass 6, count 0 2006.218.07:43:50.85#ibcon#read 5, iclass 6, count 0 2006.218.07:43:50.85#ibcon#about to read 6, iclass 6, count 0 2006.218.07:43:50.85#ibcon#read 6, iclass 6, count 0 2006.218.07:43:50.85#ibcon#end of sib2, iclass 6, count 0 2006.218.07:43:50.85#ibcon#*mode == 0, iclass 6, count 0 2006.218.07:43:50.85#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.218.07:43:50.85#ibcon#[27=USB\r\n] 2006.218.07:43:50.85#ibcon#*before write, iclass 6, count 0 2006.218.07:43:50.85#ibcon#enter sib2, iclass 6, count 0 2006.218.07:43:50.85#ibcon#flushed, iclass 6, count 0 2006.218.07:43:50.85#ibcon#about to write, iclass 6, count 0 2006.218.07:43:50.85#ibcon#wrote, iclass 6, count 0 2006.218.07:43:50.85#ibcon#about to read 3, iclass 6, count 0 2006.218.07:43:50.88#ibcon#read 3, iclass 6, count 0 2006.218.07:43:50.88#ibcon#about to read 4, iclass 6, count 0 2006.218.07:43:50.88#ibcon#read 4, iclass 6, count 0 2006.218.07:43:50.88#ibcon#about to read 5, iclass 6, count 0 2006.218.07:43:50.88#ibcon#read 5, iclass 6, count 0 2006.218.07:43:50.88#ibcon#about to read 6, iclass 6, count 0 2006.218.07:43:50.88#ibcon#read 6, iclass 6, count 0 2006.218.07:43:50.88#ibcon#end of sib2, iclass 6, count 0 2006.218.07:43:50.88#ibcon#*after write, iclass 6, count 0 2006.218.07:43:50.88#ibcon#*before return 0, iclass 6, count 0 2006.218.07:43:50.88#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.218.07:43:50.88#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.218.07:43:50.88#ibcon#about to clear, iclass 6 cls_cnt 0 2006.218.07:43:50.88#ibcon#cleared, iclass 6 cls_cnt 0 2006.218.07:43:50.88$vc4f8/vblo=2,640.99 2006.218.07:43:50.88#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.218.07:43:50.88#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.218.07:43:50.88#ibcon#ireg 17 cls_cnt 0 2006.218.07:43:50.88#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.218.07:43:50.88#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.218.07:43:50.88#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.218.07:43:50.88#ibcon#enter wrdev, iclass 10, count 0 2006.218.07:43:50.88#ibcon#first serial, iclass 10, count 0 2006.218.07:43:50.88#ibcon#enter sib2, iclass 10, count 0 2006.218.07:43:50.88#ibcon#flushed, iclass 10, count 0 2006.218.07:43:50.88#ibcon#about to write, iclass 10, count 0 2006.218.07:43:50.88#ibcon#wrote, iclass 10, count 0 2006.218.07:43:50.88#ibcon#about to read 3, iclass 10, count 0 2006.218.07:43:50.90#ibcon#read 3, iclass 10, count 0 2006.218.07:43:50.90#ibcon#about to read 4, iclass 10, count 0 2006.218.07:43:50.90#ibcon#read 4, iclass 10, count 0 2006.218.07:43:50.90#ibcon#about to read 5, iclass 10, count 0 2006.218.07:43:50.90#ibcon#read 5, iclass 10, count 0 2006.218.07:43:50.90#ibcon#about to read 6, iclass 10, count 0 2006.218.07:43:50.90#ibcon#read 6, iclass 10, count 0 2006.218.07:43:50.90#ibcon#end of sib2, iclass 10, count 0 2006.218.07:43:50.90#ibcon#*mode == 0, iclass 10, count 0 2006.218.07:43:50.90#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.218.07:43:50.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.218.07:43:50.90#ibcon#*before write, iclass 10, count 0 2006.218.07:43:50.90#ibcon#enter sib2, iclass 10, count 0 2006.218.07:43:50.90#ibcon#flushed, iclass 10, count 0 2006.218.07:43:50.90#ibcon#about to write, iclass 10, count 0 2006.218.07:43:50.90#ibcon#wrote, iclass 10, count 0 2006.218.07:43:50.90#ibcon#about to read 3, iclass 10, count 0 2006.218.07:43:50.94#ibcon#read 3, iclass 10, count 0 2006.218.07:43:50.94#ibcon#about to read 4, iclass 10, count 0 2006.218.07:43:50.94#ibcon#read 4, iclass 10, count 0 2006.218.07:43:50.94#ibcon#about to read 5, iclass 10, count 0 2006.218.07:43:50.94#ibcon#read 5, iclass 10, count 0 2006.218.07:43:50.94#ibcon#about to read 6, iclass 10, count 0 2006.218.07:43:50.94#ibcon#read 6, iclass 10, count 0 2006.218.07:43:50.94#ibcon#end of sib2, iclass 10, count 0 2006.218.07:43:50.94#ibcon#*after write, iclass 10, count 0 2006.218.07:43:50.94#ibcon#*before return 0, iclass 10, count 0 2006.218.07:43:50.94#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.218.07:43:50.94#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.218.07:43:50.94#ibcon#about to clear, iclass 10 cls_cnt 0 2006.218.07:43:50.94#ibcon#cleared, iclass 10 cls_cnt 0 2006.218.07:43:50.94$vc4f8/vb=2,4 2006.218.07:43:50.94#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.218.07:43:50.94#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.218.07:43:50.94#ibcon#ireg 11 cls_cnt 2 2006.218.07:43:50.94#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.218.07:43:51.00#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.218.07:43:51.00#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.218.07:43:51.00#ibcon#enter wrdev, iclass 12, count 2 2006.218.07:43:51.00#ibcon#first serial, iclass 12, count 2 2006.218.07:43:51.00#ibcon#enter sib2, iclass 12, count 2 2006.218.07:43:51.00#ibcon#flushed, iclass 12, count 2 2006.218.07:43:51.00#ibcon#about to write, iclass 12, count 2 2006.218.07:43:51.00#ibcon#wrote, iclass 12, count 2 2006.218.07:43:51.00#ibcon#about to read 3, iclass 12, count 2 2006.218.07:43:51.02#ibcon#read 3, iclass 12, count 2 2006.218.07:43:51.02#ibcon#about to read 4, iclass 12, count 2 2006.218.07:43:51.02#ibcon#read 4, iclass 12, count 2 2006.218.07:43:51.02#ibcon#about to read 5, iclass 12, count 2 2006.218.07:43:51.02#ibcon#read 5, iclass 12, count 2 2006.218.07:43:51.02#ibcon#about to read 6, iclass 12, count 2 2006.218.07:43:51.02#ibcon#read 6, iclass 12, count 2 2006.218.07:43:51.02#ibcon#end of sib2, iclass 12, count 2 2006.218.07:43:51.02#ibcon#*mode == 0, iclass 12, count 2 2006.218.07:43:51.02#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.218.07:43:51.02#ibcon#[27=AT02-04\r\n] 2006.218.07:43:51.02#ibcon#*before write, iclass 12, count 2 2006.218.07:43:51.02#ibcon#enter sib2, iclass 12, count 2 2006.218.07:43:51.02#ibcon#flushed, iclass 12, count 2 2006.218.07:43:51.02#ibcon#about to write, iclass 12, count 2 2006.218.07:43:51.02#ibcon#wrote, iclass 12, count 2 2006.218.07:43:51.02#ibcon#about to read 3, iclass 12, count 2 2006.218.07:43:51.05#ibcon#read 3, iclass 12, count 2 2006.218.07:43:51.05#ibcon#about to read 4, iclass 12, count 2 2006.218.07:43:51.05#ibcon#read 4, iclass 12, count 2 2006.218.07:43:51.05#ibcon#about to read 5, iclass 12, count 2 2006.218.07:43:51.05#ibcon#read 5, iclass 12, count 2 2006.218.07:43:51.05#ibcon#about to read 6, iclass 12, count 2 2006.218.07:43:51.05#ibcon#read 6, iclass 12, count 2 2006.218.07:43:51.05#ibcon#end of sib2, iclass 12, count 2 2006.218.07:43:51.05#ibcon#*after write, iclass 12, count 2 2006.218.07:43:51.05#ibcon#*before return 0, iclass 12, count 2 2006.218.07:43:51.05#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.218.07:43:51.05#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.218.07:43:51.05#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.218.07:43:51.05#ibcon#ireg 7 cls_cnt 0 2006.218.07:43:51.05#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.218.07:43:51.17#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.218.07:43:51.17#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.218.07:43:51.17#ibcon#enter wrdev, iclass 12, count 0 2006.218.07:43:51.17#ibcon#first serial, iclass 12, count 0 2006.218.07:43:51.17#ibcon#enter sib2, iclass 12, count 0 2006.218.07:43:51.17#ibcon#flushed, iclass 12, count 0 2006.218.07:43:51.17#ibcon#about to write, iclass 12, count 0 2006.218.07:43:51.17#ibcon#wrote, iclass 12, count 0 2006.218.07:43:51.17#ibcon#about to read 3, iclass 12, count 0 2006.218.07:43:51.19#ibcon#read 3, iclass 12, count 0 2006.218.07:43:51.19#ibcon#about to read 4, iclass 12, count 0 2006.218.07:43:51.19#ibcon#read 4, iclass 12, count 0 2006.218.07:43:51.19#ibcon#about to read 5, iclass 12, count 0 2006.218.07:43:51.19#ibcon#read 5, iclass 12, count 0 2006.218.07:43:51.19#ibcon#about to read 6, iclass 12, count 0 2006.218.07:43:51.19#ibcon#read 6, iclass 12, count 0 2006.218.07:43:51.19#ibcon#end of sib2, iclass 12, count 0 2006.218.07:43:51.19#ibcon#*mode == 0, iclass 12, count 0 2006.218.07:43:51.19#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.218.07:43:51.19#ibcon#[27=USB\r\n] 2006.218.07:43:51.19#ibcon#*before write, iclass 12, count 0 2006.218.07:43:51.19#ibcon#enter sib2, iclass 12, count 0 2006.218.07:43:51.19#ibcon#flushed, iclass 12, count 0 2006.218.07:43:51.19#ibcon#about to write, iclass 12, count 0 2006.218.07:43:51.19#ibcon#wrote, iclass 12, count 0 2006.218.07:43:51.19#ibcon#about to read 3, iclass 12, count 0 2006.218.07:43:51.22#ibcon#read 3, iclass 12, count 0 2006.218.07:43:51.22#ibcon#about to read 4, iclass 12, count 0 2006.218.07:43:51.22#ibcon#read 4, iclass 12, count 0 2006.218.07:43:51.22#ibcon#about to read 5, iclass 12, count 0 2006.218.07:43:51.22#ibcon#read 5, iclass 12, count 0 2006.218.07:43:51.22#ibcon#about to read 6, iclass 12, count 0 2006.218.07:43:51.22#ibcon#read 6, iclass 12, count 0 2006.218.07:43:51.22#ibcon#end of sib2, iclass 12, count 0 2006.218.07:43:51.22#ibcon#*after write, iclass 12, count 0 2006.218.07:43:51.22#ibcon#*before return 0, iclass 12, count 0 2006.218.07:43:51.22#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.218.07:43:51.22#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.218.07:43:51.22#ibcon#about to clear, iclass 12 cls_cnt 0 2006.218.07:43:51.22#ibcon#cleared, iclass 12 cls_cnt 0 2006.218.07:43:51.22$vc4f8/vblo=3,656.99 2006.218.07:43:51.22#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.218.07:43:51.22#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.218.07:43:51.22#ibcon#ireg 17 cls_cnt 0 2006.218.07:43:51.22#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.218.07:43:51.22#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.218.07:43:51.22#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.218.07:43:51.22#ibcon#enter wrdev, iclass 14, count 0 2006.218.07:43:51.22#ibcon#first serial, iclass 14, count 0 2006.218.07:43:51.22#ibcon#enter sib2, iclass 14, count 0 2006.218.07:43:51.22#ibcon#flushed, iclass 14, count 0 2006.218.07:43:51.22#ibcon#about to write, iclass 14, count 0 2006.218.07:43:51.22#ibcon#wrote, iclass 14, count 0 2006.218.07:43:51.22#ibcon#about to read 3, iclass 14, count 0 2006.218.07:43:51.24#ibcon#read 3, iclass 14, count 0 2006.218.07:43:51.24#ibcon#about to read 4, iclass 14, count 0 2006.218.07:43:51.24#ibcon#read 4, iclass 14, count 0 2006.218.07:43:51.24#ibcon#about to read 5, iclass 14, count 0 2006.218.07:43:51.24#ibcon#read 5, iclass 14, count 0 2006.218.07:43:51.24#ibcon#about to read 6, iclass 14, count 0 2006.218.07:43:51.24#ibcon#read 6, iclass 14, count 0 2006.218.07:43:51.24#ibcon#end of sib2, iclass 14, count 0 2006.218.07:43:51.24#ibcon#*mode == 0, iclass 14, count 0 2006.218.07:43:51.24#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.218.07:43:51.24#ibcon#[28=FRQ=03,656.99\r\n] 2006.218.07:43:51.24#ibcon#*before write, iclass 14, count 0 2006.218.07:43:51.24#ibcon#enter sib2, iclass 14, count 0 2006.218.07:43:51.24#ibcon#flushed, iclass 14, count 0 2006.218.07:43:51.24#ibcon#about to write, iclass 14, count 0 2006.218.07:43:51.24#ibcon#wrote, iclass 14, count 0 2006.218.07:43:51.24#ibcon#about to read 3, iclass 14, count 0 2006.218.07:43:51.28#ibcon#read 3, iclass 14, count 0 2006.218.07:43:51.28#ibcon#about to read 4, iclass 14, count 0 2006.218.07:43:51.28#ibcon#read 4, iclass 14, count 0 2006.218.07:43:51.28#ibcon#about to read 5, iclass 14, count 0 2006.218.07:43:51.28#ibcon#read 5, iclass 14, count 0 2006.218.07:43:51.28#ibcon#about to read 6, iclass 14, count 0 2006.218.07:43:51.28#ibcon#read 6, iclass 14, count 0 2006.218.07:43:51.28#ibcon#end of sib2, iclass 14, count 0 2006.218.07:43:51.28#ibcon#*after write, iclass 14, count 0 2006.218.07:43:51.28#ibcon#*before return 0, iclass 14, count 0 2006.218.07:43:51.28#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.218.07:43:51.28#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.218.07:43:51.28#ibcon#about to clear, iclass 14 cls_cnt 0 2006.218.07:43:51.28#ibcon#cleared, iclass 14 cls_cnt 0 2006.218.07:43:51.28$vc4f8/vb=3,4 2006.218.07:43:51.28#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.218.07:43:51.28#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.218.07:43:51.28#ibcon#ireg 11 cls_cnt 2 2006.218.07:43:51.28#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.218.07:43:51.34#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.218.07:43:51.34#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.218.07:43:51.34#ibcon#enter wrdev, iclass 16, count 2 2006.218.07:43:51.34#ibcon#first serial, iclass 16, count 2 2006.218.07:43:51.34#ibcon#enter sib2, iclass 16, count 2 2006.218.07:43:51.34#ibcon#flushed, iclass 16, count 2 2006.218.07:43:51.34#ibcon#about to write, iclass 16, count 2 2006.218.07:43:51.34#ibcon#wrote, iclass 16, count 2 2006.218.07:43:51.34#ibcon#about to read 3, iclass 16, count 2 2006.218.07:43:51.36#ibcon#read 3, iclass 16, count 2 2006.218.07:43:51.36#ibcon#about to read 4, iclass 16, count 2 2006.218.07:43:51.36#ibcon#read 4, iclass 16, count 2 2006.218.07:43:51.36#ibcon#about to read 5, iclass 16, count 2 2006.218.07:43:51.36#ibcon#read 5, iclass 16, count 2 2006.218.07:43:51.36#ibcon#about to read 6, iclass 16, count 2 2006.218.07:43:51.36#ibcon#read 6, iclass 16, count 2 2006.218.07:43:51.36#ibcon#end of sib2, iclass 16, count 2 2006.218.07:43:51.36#ibcon#*mode == 0, iclass 16, count 2 2006.218.07:43:51.36#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.218.07:43:51.36#ibcon#[27=AT03-04\r\n] 2006.218.07:43:51.36#ibcon#*before write, iclass 16, count 2 2006.218.07:43:51.36#ibcon#enter sib2, iclass 16, count 2 2006.218.07:43:51.36#ibcon#flushed, iclass 16, count 2 2006.218.07:43:51.36#ibcon#about to write, iclass 16, count 2 2006.218.07:43:51.36#ibcon#wrote, iclass 16, count 2 2006.218.07:43:51.36#ibcon#about to read 3, iclass 16, count 2 2006.218.07:43:51.39#ibcon#read 3, iclass 16, count 2 2006.218.07:43:51.39#ibcon#about to read 4, iclass 16, count 2 2006.218.07:43:51.39#ibcon#read 4, iclass 16, count 2 2006.218.07:43:51.39#ibcon#about to read 5, iclass 16, count 2 2006.218.07:43:51.39#ibcon#read 5, iclass 16, count 2 2006.218.07:43:51.39#ibcon#about to read 6, iclass 16, count 2 2006.218.07:43:51.39#ibcon#read 6, iclass 16, count 2 2006.218.07:43:51.39#ibcon#end of sib2, iclass 16, count 2 2006.218.07:43:51.39#ibcon#*after write, iclass 16, count 2 2006.218.07:43:51.39#ibcon#*before return 0, iclass 16, count 2 2006.218.07:43:51.39#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.218.07:43:51.39#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.218.07:43:51.39#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.218.07:43:51.39#ibcon#ireg 7 cls_cnt 0 2006.218.07:43:51.39#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.218.07:43:51.51#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.218.07:43:51.51#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.218.07:43:51.51#ibcon#enter wrdev, iclass 16, count 0 2006.218.07:43:51.51#ibcon#first serial, iclass 16, count 0 2006.218.07:43:51.51#ibcon#enter sib2, iclass 16, count 0 2006.218.07:43:51.51#ibcon#flushed, iclass 16, count 0 2006.218.07:43:51.51#ibcon#about to write, iclass 16, count 0 2006.218.07:43:51.51#ibcon#wrote, iclass 16, count 0 2006.218.07:43:51.51#ibcon#about to read 3, iclass 16, count 0 2006.218.07:43:51.53#ibcon#read 3, iclass 16, count 0 2006.218.07:43:51.53#ibcon#about to read 4, iclass 16, count 0 2006.218.07:43:51.53#ibcon#read 4, iclass 16, count 0 2006.218.07:43:51.53#ibcon#about to read 5, iclass 16, count 0 2006.218.07:43:51.53#ibcon#read 5, iclass 16, count 0 2006.218.07:43:51.53#ibcon#about to read 6, iclass 16, count 0 2006.218.07:43:51.53#ibcon#read 6, iclass 16, count 0 2006.218.07:43:51.53#ibcon#end of sib2, iclass 16, count 0 2006.218.07:43:51.53#ibcon#*mode == 0, iclass 16, count 0 2006.218.07:43:51.53#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.218.07:43:51.53#ibcon#[27=USB\r\n] 2006.218.07:43:51.53#ibcon#*before write, iclass 16, count 0 2006.218.07:43:51.53#ibcon#enter sib2, iclass 16, count 0 2006.218.07:43:51.53#ibcon#flushed, iclass 16, count 0 2006.218.07:43:51.53#ibcon#about to write, iclass 16, count 0 2006.218.07:43:51.53#ibcon#wrote, iclass 16, count 0 2006.218.07:43:51.53#ibcon#about to read 3, iclass 16, count 0 2006.218.07:43:51.56#ibcon#read 3, iclass 16, count 0 2006.218.07:43:51.56#ibcon#about to read 4, iclass 16, count 0 2006.218.07:43:51.56#ibcon#read 4, iclass 16, count 0 2006.218.07:43:51.56#ibcon#about to read 5, iclass 16, count 0 2006.218.07:43:51.56#ibcon#read 5, iclass 16, count 0 2006.218.07:43:51.56#ibcon#about to read 6, iclass 16, count 0 2006.218.07:43:51.56#ibcon#read 6, iclass 16, count 0 2006.218.07:43:51.56#ibcon#end of sib2, iclass 16, count 0 2006.218.07:43:51.56#ibcon#*after write, iclass 16, count 0 2006.218.07:43:51.56#ibcon#*before return 0, iclass 16, count 0 2006.218.07:43:51.56#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.218.07:43:51.56#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.218.07:43:51.56#ibcon#about to clear, iclass 16 cls_cnt 0 2006.218.07:43:51.56#ibcon#cleared, iclass 16 cls_cnt 0 2006.218.07:43:51.56$vc4f8/vblo=4,712.99 2006.218.07:43:51.56#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.218.07:43:51.56#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.218.07:43:51.56#ibcon#ireg 17 cls_cnt 0 2006.218.07:43:51.56#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.218.07:43:51.56#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.218.07:43:51.56#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.218.07:43:51.56#ibcon#enter wrdev, iclass 18, count 0 2006.218.07:43:51.56#ibcon#first serial, iclass 18, count 0 2006.218.07:43:51.56#ibcon#enter sib2, iclass 18, count 0 2006.218.07:43:51.56#ibcon#flushed, iclass 18, count 0 2006.218.07:43:51.56#ibcon#about to write, iclass 18, count 0 2006.218.07:43:51.56#ibcon#wrote, iclass 18, count 0 2006.218.07:43:51.56#ibcon#about to read 3, iclass 18, count 0 2006.218.07:43:51.58#ibcon#read 3, iclass 18, count 0 2006.218.07:43:51.58#ibcon#about to read 4, iclass 18, count 0 2006.218.07:43:51.58#ibcon#read 4, iclass 18, count 0 2006.218.07:43:51.58#ibcon#about to read 5, iclass 18, count 0 2006.218.07:43:51.58#ibcon#read 5, iclass 18, count 0 2006.218.07:43:51.58#ibcon#about to read 6, iclass 18, count 0 2006.218.07:43:51.58#ibcon#read 6, iclass 18, count 0 2006.218.07:43:51.58#ibcon#end of sib2, iclass 18, count 0 2006.218.07:43:51.58#ibcon#*mode == 0, iclass 18, count 0 2006.218.07:43:51.58#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.218.07:43:51.58#ibcon#[28=FRQ=04,712.99\r\n] 2006.218.07:43:51.58#ibcon#*before write, iclass 18, count 0 2006.218.07:43:51.58#ibcon#enter sib2, iclass 18, count 0 2006.218.07:43:51.58#ibcon#flushed, iclass 18, count 0 2006.218.07:43:51.58#ibcon#about to write, iclass 18, count 0 2006.218.07:43:51.58#ibcon#wrote, iclass 18, count 0 2006.218.07:43:51.58#ibcon#about to read 3, iclass 18, count 0 2006.218.07:43:51.62#ibcon#read 3, iclass 18, count 0 2006.218.07:43:51.62#ibcon#about to read 4, iclass 18, count 0 2006.218.07:43:51.62#ibcon#read 4, iclass 18, count 0 2006.218.07:43:51.62#ibcon#about to read 5, iclass 18, count 0 2006.218.07:43:51.62#ibcon#read 5, iclass 18, count 0 2006.218.07:43:51.62#ibcon#about to read 6, iclass 18, count 0 2006.218.07:43:51.62#ibcon#read 6, iclass 18, count 0 2006.218.07:43:51.62#ibcon#end of sib2, iclass 18, count 0 2006.218.07:43:51.62#ibcon#*after write, iclass 18, count 0 2006.218.07:43:51.62#ibcon#*before return 0, iclass 18, count 0 2006.218.07:43:51.62#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.218.07:43:51.62#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.218.07:43:51.62#ibcon#about to clear, iclass 18 cls_cnt 0 2006.218.07:43:51.62#ibcon#cleared, iclass 18 cls_cnt 0 2006.218.07:43:51.62$vc4f8/vb=4,4 2006.218.07:43:51.62#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.218.07:43:51.62#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.218.07:43:51.62#ibcon#ireg 11 cls_cnt 2 2006.218.07:43:51.62#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.218.07:43:51.68#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.218.07:43:51.68#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.218.07:43:51.68#ibcon#enter wrdev, iclass 20, count 2 2006.218.07:43:51.68#ibcon#first serial, iclass 20, count 2 2006.218.07:43:51.68#ibcon#enter sib2, iclass 20, count 2 2006.218.07:43:51.68#ibcon#flushed, iclass 20, count 2 2006.218.07:43:51.68#ibcon#about to write, iclass 20, count 2 2006.218.07:43:51.68#ibcon#wrote, iclass 20, count 2 2006.218.07:43:51.68#ibcon#about to read 3, iclass 20, count 2 2006.218.07:43:51.70#ibcon#read 3, iclass 20, count 2 2006.218.07:43:51.70#ibcon#about to read 4, iclass 20, count 2 2006.218.07:43:51.70#ibcon#read 4, iclass 20, count 2 2006.218.07:43:51.70#ibcon#about to read 5, iclass 20, count 2 2006.218.07:43:51.70#ibcon#read 5, iclass 20, count 2 2006.218.07:43:51.70#ibcon#about to read 6, iclass 20, count 2 2006.218.07:43:51.70#ibcon#read 6, iclass 20, count 2 2006.218.07:43:51.70#ibcon#end of sib2, iclass 20, count 2 2006.218.07:43:51.70#ibcon#*mode == 0, iclass 20, count 2 2006.218.07:43:51.70#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.218.07:43:51.70#ibcon#[27=AT04-04\r\n] 2006.218.07:43:51.70#ibcon#*before write, iclass 20, count 2 2006.218.07:43:51.70#ibcon#enter sib2, iclass 20, count 2 2006.218.07:43:51.70#ibcon#flushed, iclass 20, count 2 2006.218.07:43:51.70#ibcon#about to write, iclass 20, count 2 2006.218.07:43:51.70#ibcon#wrote, iclass 20, count 2 2006.218.07:43:51.70#ibcon#about to read 3, iclass 20, count 2 2006.218.07:43:51.73#ibcon#read 3, iclass 20, count 2 2006.218.07:43:51.73#ibcon#about to read 4, iclass 20, count 2 2006.218.07:43:51.73#ibcon#read 4, iclass 20, count 2 2006.218.07:43:51.73#ibcon#about to read 5, iclass 20, count 2 2006.218.07:43:51.73#ibcon#read 5, iclass 20, count 2 2006.218.07:43:51.73#ibcon#about to read 6, iclass 20, count 2 2006.218.07:43:51.73#ibcon#read 6, iclass 20, count 2 2006.218.07:43:51.73#ibcon#end of sib2, iclass 20, count 2 2006.218.07:43:51.73#ibcon#*after write, iclass 20, count 2 2006.218.07:43:51.73#ibcon#*before return 0, iclass 20, count 2 2006.218.07:43:51.73#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.218.07:43:51.73#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.218.07:43:51.73#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.218.07:43:51.73#ibcon#ireg 7 cls_cnt 0 2006.218.07:43:51.73#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.218.07:43:51.85#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.218.07:43:51.85#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.218.07:43:51.85#ibcon#enter wrdev, iclass 20, count 0 2006.218.07:43:51.85#ibcon#first serial, iclass 20, count 0 2006.218.07:43:51.85#ibcon#enter sib2, iclass 20, count 0 2006.218.07:43:51.85#ibcon#flushed, iclass 20, count 0 2006.218.07:43:51.85#ibcon#about to write, iclass 20, count 0 2006.218.07:43:51.85#ibcon#wrote, iclass 20, count 0 2006.218.07:43:51.85#ibcon#about to read 3, iclass 20, count 0 2006.218.07:43:51.87#ibcon#read 3, iclass 20, count 0 2006.218.07:43:51.87#ibcon#about to read 4, iclass 20, count 0 2006.218.07:43:51.87#ibcon#read 4, iclass 20, count 0 2006.218.07:43:51.87#ibcon#about to read 5, iclass 20, count 0 2006.218.07:43:51.87#ibcon#read 5, iclass 20, count 0 2006.218.07:43:51.87#ibcon#about to read 6, iclass 20, count 0 2006.218.07:43:51.87#ibcon#read 6, iclass 20, count 0 2006.218.07:43:51.87#ibcon#end of sib2, iclass 20, count 0 2006.218.07:43:51.87#ibcon#*mode == 0, iclass 20, count 0 2006.218.07:43:51.87#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.218.07:43:51.87#ibcon#[27=USB\r\n] 2006.218.07:43:51.87#ibcon#*before write, iclass 20, count 0 2006.218.07:43:51.87#ibcon#enter sib2, iclass 20, count 0 2006.218.07:43:51.87#ibcon#flushed, iclass 20, count 0 2006.218.07:43:51.87#ibcon#about to write, iclass 20, count 0 2006.218.07:43:51.87#ibcon#wrote, iclass 20, count 0 2006.218.07:43:51.87#ibcon#about to read 3, iclass 20, count 0 2006.218.07:43:51.90#ibcon#read 3, iclass 20, count 0 2006.218.07:43:51.90#ibcon#about to read 4, iclass 20, count 0 2006.218.07:43:51.90#ibcon#read 4, iclass 20, count 0 2006.218.07:43:51.90#ibcon#about to read 5, iclass 20, count 0 2006.218.07:43:51.90#ibcon#read 5, iclass 20, count 0 2006.218.07:43:51.90#ibcon#about to read 6, iclass 20, count 0 2006.218.07:43:51.90#ibcon#read 6, iclass 20, count 0 2006.218.07:43:51.90#ibcon#end of sib2, iclass 20, count 0 2006.218.07:43:51.90#ibcon#*after write, iclass 20, count 0 2006.218.07:43:51.90#ibcon#*before return 0, iclass 20, count 0 2006.218.07:43:51.90#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.218.07:43:51.90#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.218.07:43:51.90#ibcon#about to clear, iclass 20 cls_cnt 0 2006.218.07:43:51.90#ibcon#cleared, iclass 20 cls_cnt 0 2006.218.07:43:51.90$vc4f8/vblo=5,744.99 2006.218.07:43:51.90#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.218.07:43:51.90#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.218.07:43:51.90#ibcon#ireg 17 cls_cnt 0 2006.218.07:43:51.90#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.218.07:43:51.90#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.218.07:43:51.90#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.218.07:43:51.90#ibcon#enter wrdev, iclass 22, count 0 2006.218.07:43:51.90#ibcon#first serial, iclass 22, count 0 2006.218.07:43:51.90#ibcon#enter sib2, iclass 22, count 0 2006.218.07:43:51.90#ibcon#flushed, iclass 22, count 0 2006.218.07:43:51.90#ibcon#about to write, iclass 22, count 0 2006.218.07:43:51.90#ibcon#wrote, iclass 22, count 0 2006.218.07:43:51.90#ibcon#about to read 3, iclass 22, count 0 2006.218.07:43:51.92#ibcon#read 3, iclass 22, count 0 2006.218.07:43:51.92#ibcon#about to read 4, iclass 22, count 0 2006.218.07:43:51.92#ibcon#read 4, iclass 22, count 0 2006.218.07:43:51.92#ibcon#about to read 5, iclass 22, count 0 2006.218.07:43:51.92#ibcon#read 5, iclass 22, count 0 2006.218.07:43:51.92#ibcon#about to read 6, iclass 22, count 0 2006.218.07:43:51.92#ibcon#read 6, iclass 22, count 0 2006.218.07:43:51.92#ibcon#end of sib2, iclass 22, count 0 2006.218.07:43:51.92#ibcon#*mode == 0, iclass 22, count 0 2006.218.07:43:51.92#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.218.07:43:51.92#ibcon#[28=FRQ=05,744.99\r\n] 2006.218.07:43:51.92#ibcon#*before write, iclass 22, count 0 2006.218.07:43:51.92#ibcon#enter sib2, iclass 22, count 0 2006.218.07:43:51.92#ibcon#flushed, iclass 22, count 0 2006.218.07:43:51.92#ibcon#about to write, iclass 22, count 0 2006.218.07:43:51.92#ibcon#wrote, iclass 22, count 0 2006.218.07:43:51.92#ibcon#about to read 3, iclass 22, count 0 2006.218.07:43:51.96#ibcon#read 3, iclass 22, count 0 2006.218.07:43:51.96#ibcon#about to read 4, iclass 22, count 0 2006.218.07:43:51.96#ibcon#read 4, iclass 22, count 0 2006.218.07:43:51.96#ibcon#about to read 5, iclass 22, count 0 2006.218.07:43:51.96#ibcon#read 5, iclass 22, count 0 2006.218.07:43:51.96#ibcon#about to read 6, iclass 22, count 0 2006.218.07:43:51.96#ibcon#read 6, iclass 22, count 0 2006.218.07:43:51.96#ibcon#end of sib2, iclass 22, count 0 2006.218.07:43:51.96#ibcon#*after write, iclass 22, count 0 2006.218.07:43:51.96#ibcon#*before return 0, iclass 22, count 0 2006.218.07:43:51.96#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.218.07:43:51.96#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.218.07:43:51.96#ibcon#about to clear, iclass 22 cls_cnt 0 2006.218.07:43:51.96#ibcon#cleared, iclass 22 cls_cnt 0 2006.218.07:43:51.96$vc4f8/vb=5,4 2006.218.07:43:51.96#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.218.07:43:51.96#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.218.07:43:51.96#ibcon#ireg 11 cls_cnt 2 2006.218.07:43:51.96#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.218.07:43:52.02#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.218.07:43:52.02#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.218.07:43:52.02#ibcon#enter wrdev, iclass 24, count 2 2006.218.07:43:52.02#ibcon#first serial, iclass 24, count 2 2006.218.07:43:52.02#ibcon#enter sib2, iclass 24, count 2 2006.218.07:43:52.02#ibcon#flushed, iclass 24, count 2 2006.218.07:43:52.02#ibcon#about to write, iclass 24, count 2 2006.218.07:43:52.02#ibcon#wrote, iclass 24, count 2 2006.218.07:43:52.02#ibcon#about to read 3, iclass 24, count 2 2006.218.07:43:52.04#ibcon#read 3, iclass 24, count 2 2006.218.07:43:52.04#ibcon#about to read 4, iclass 24, count 2 2006.218.07:43:52.04#ibcon#read 4, iclass 24, count 2 2006.218.07:43:52.04#ibcon#about to read 5, iclass 24, count 2 2006.218.07:43:52.04#ibcon#read 5, iclass 24, count 2 2006.218.07:43:52.04#ibcon#about to read 6, iclass 24, count 2 2006.218.07:43:52.04#ibcon#read 6, iclass 24, count 2 2006.218.07:43:52.04#ibcon#end of sib2, iclass 24, count 2 2006.218.07:43:52.04#ibcon#*mode == 0, iclass 24, count 2 2006.218.07:43:52.04#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.218.07:43:52.04#ibcon#[27=AT05-04\r\n] 2006.218.07:43:52.04#ibcon#*before write, iclass 24, count 2 2006.218.07:43:52.04#ibcon#enter sib2, iclass 24, count 2 2006.218.07:43:52.04#ibcon#flushed, iclass 24, count 2 2006.218.07:43:52.04#ibcon#about to write, iclass 24, count 2 2006.218.07:43:52.04#ibcon#wrote, iclass 24, count 2 2006.218.07:43:52.04#ibcon#about to read 3, iclass 24, count 2 2006.218.07:43:52.07#ibcon#read 3, iclass 24, count 2 2006.218.07:43:52.07#ibcon#about to read 4, iclass 24, count 2 2006.218.07:43:52.07#ibcon#read 4, iclass 24, count 2 2006.218.07:43:52.07#ibcon#about to read 5, iclass 24, count 2 2006.218.07:43:52.07#ibcon#read 5, iclass 24, count 2 2006.218.07:43:52.07#ibcon#about to read 6, iclass 24, count 2 2006.218.07:43:52.07#ibcon#read 6, iclass 24, count 2 2006.218.07:43:52.07#ibcon#end of sib2, iclass 24, count 2 2006.218.07:43:52.07#ibcon#*after write, iclass 24, count 2 2006.218.07:43:52.07#ibcon#*before return 0, iclass 24, count 2 2006.218.07:43:52.07#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.218.07:43:52.07#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.218.07:43:52.07#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.218.07:43:52.07#ibcon#ireg 7 cls_cnt 0 2006.218.07:43:52.07#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.218.07:43:52.19#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.218.07:43:52.19#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.218.07:43:52.19#ibcon#enter wrdev, iclass 24, count 0 2006.218.07:43:52.19#ibcon#first serial, iclass 24, count 0 2006.218.07:43:52.19#ibcon#enter sib2, iclass 24, count 0 2006.218.07:43:52.19#ibcon#flushed, iclass 24, count 0 2006.218.07:43:52.19#ibcon#about to write, iclass 24, count 0 2006.218.07:43:52.19#ibcon#wrote, iclass 24, count 0 2006.218.07:43:52.19#ibcon#about to read 3, iclass 24, count 0 2006.218.07:43:52.21#ibcon#read 3, iclass 24, count 0 2006.218.07:43:52.21#ibcon#about to read 4, iclass 24, count 0 2006.218.07:43:52.21#ibcon#read 4, iclass 24, count 0 2006.218.07:43:52.21#ibcon#about to read 5, iclass 24, count 0 2006.218.07:43:52.21#ibcon#read 5, iclass 24, count 0 2006.218.07:43:52.21#ibcon#about to read 6, iclass 24, count 0 2006.218.07:43:52.21#ibcon#read 6, iclass 24, count 0 2006.218.07:43:52.21#ibcon#end of sib2, iclass 24, count 0 2006.218.07:43:52.21#ibcon#*mode == 0, iclass 24, count 0 2006.218.07:43:52.21#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.218.07:43:52.21#ibcon#[27=USB\r\n] 2006.218.07:43:52.21#ibcon#*before write, iclass 24, count 0 2006.218.07:43:52.21#ibcon#enter sib2, iclass 24, count 0 2006.218.07:43:52.21#ibcon#flushed, iclass 24, count 0 2006.218.07:43:52.21#ibcon#about to write, iclass 24, count 0 2006.218.07:43:52.21#ibcon#wrote, iclass 24, count 0 2006.218.07:43:52.21#ibcon#about to read 3, iclass 24, count 0 2006.218.07:43:52.24#ibcon#read 3, iclass 24, count 0 2006.218.07:43:52.24#ibcon#about to read 4, iclass 24, count 0 2006.218.07:43:52.24#ibcon#read 4, iclass 24, count 0 2006.218.07:43:52.24#ibcon#about to read 5, iclass 24, count 0 2006.218.07:43:52.24#ibcon#read 5, iclass 24, count 0 2006.218.07:43:52.24#ibcon#about to read 6, iclass 24, count 0 2006.218.07:43:52.24#ibcon#read 6, iclass 24, count 0 2006.218.07:43:52.24#ibcon#end of sib2, iclass 24, count 0 2006.218.07:43:52.24#ibcon#*after write, iclass 24, count 0 2006.218.07:43:52.24#ibcon#*before return 0, iclass 24, count 0 2006.218.07:43:52.24#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.218.07:43:52.24#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.218.07:43:52.24#ibcon#about to clear, iclass 24 cls_cnt 0 2006.218.07:43:52.24#ibcon#cleared, iclass 24 cls_cnt 0 2006.218.07:43:52.24$vc4f8/vblo=6,752.99 2006.218.07:43:52.24#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.218.07:43:52.24#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.218.07:43:52.24#ibcon#ireg 17 cls_cnt 0 2006.218.07:43:52.24#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.218.07:43:52.24#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.218.07:43:52.24#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.218.07:43:52.24#ibcon#enter wrdev, iclass 26, count 0 2006.218.07:43:52.24#ibcon#first serial, iclass 26, count 0 2006.218.07:43:52.24#ibcon#enter sib2, iclass 26, count 0 2006.218.07:43:52.24#ibcon#flushed, iclass 26, count 0 2006.218.07:43:52.24#ibcon#about to write, iclass 26, count 0 2006.218.07:43:52.24#ibcon#wrote, iclass 26, count 0 2006.218.07:43:52.24#ibcon#about to read 3, iclass 26, count 0 2006.218.07:43:52.26#ibcon#read 3, iclass 26, count 0 2006.218.07:43:52.26#ibcon#about to read 4, iclass 26, count 0 2006.218.07:43:52.26#ibcon#read 4, iclass 26, count 0 2006.218.07:43:52.26#ibcon#about to read 5, iclass 26, count 0 2006.218.07:43:52.26#ibcon#read 5, iclass 26, count 0 2006.218.07:43:52.26#ibcon#about to read 6, iclass 26, count 0 2006.218.07:43:52.26#ibcon#read 6, iclass 26, count 0 2006.218.07:43:52.26#ibcon#end of sib2, iclass 26, count 0 2006.218.07:43:52.26#ibcon#*mode == 0, iclass 26, count 0 2006.218.07:43:52.26#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.218.07:43:52.26#ibcon#[28=FRQ=06,752.99\r\n] 2006.218.07:43:52.26#ibcon#*before write, iclass 26, count 0 2006.218.07:43:52.26#ibcon#enter sib2, iclass 26, count 0 2006.218.07:43:52.26#ibcon#flushed, iclass 26, count 0 2006.218.07:43:52.26#ibcon#about to write, iclass 26, count 0 2006.218.07:43:52.26#ibcon#wrote, iclass 26, count 0 2006.218.07:43:52.26#ibcon#about to read 3, iclass 26, count 0 2006.218.07:43:52.30#ibcon#read 3, iclass 26, count 0 2006.218.07:43:52.30#ibcon#about to read 4, iclass 26, count 0 2006.218.07:43:52.30#ibcon#read 4, iclass 26, count 0 2006.218.07:43:52.30#ibcon#about to read 5, iclass 26, count 0 2006.218.07:43:52.30#ibcon#read 5, iclass 26, count 0 2006.218.07:43:52.30#ibcon#about to read 6, iclass 26, count 0 2006.218.07:43:52.30#ibcon#read 6, iclass 26, count 0 2006.218.07:43:52.30#ibcon#end of sib2, iclass 26, count 0 2006.218.07:43:52.30#ibcon#*after write, iclass 26, count 0 2006.218.07:43:52.30#ibcon#*before return 0, iclass 26, count 0 2006.218.07:43:52.30#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.218.07:43:52.30#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.218.07:43:52.30#ibcon#about to clear, iclass 26 cls_cnt 0 2006.218.07:43:52.30#ibcon#cleared, iclass 26 cls_cnt 0 2006.218.07:43:52.30$vc4f8/vb=6,4 2006.218.07:43:52.30#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.218.07:43:52.30#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.218.07:43:52.30#ibcon#ireg 11 cls_cnt 2 2006.218.07:43:52.30#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.218.07:43:52.36#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.218.07:43:52.36#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.218.07:43:52.36#ibcon#enter wrdev, iclass 28, count 2 2006.218.07:43:52.36#ibcon#first serial, iclass 28, count 2 2006.218.07:43:52.36#ibcon#enter sib2, iclass 28, count 2 2006.218.07:43:52.36#ibcon#flushed, iclass 28, count 2 2006.218.07:43:52.36#ibcon#about to write, iclass 28, count 2 2006.218.07:43:52.36#ibcon#wrote, iclass 28, count 2 2006.218.07:43:52.36#ibcon#about to read 3, iclass 28, count 2 2006.218.07:43:52.38#ibcon#read 3, iclass 28, count 2 2006.218.07:43:52.38#ibcon#about to read 4, iclass 28, count 2 2006.218.07:43:52.38#ibcon#read 4, iclass 28, count 2 2006.218.07:43:52.38#ibcon#about to read 5, iclass 28, count 2 2006.218.07:43:52.38#ibcon#read 5, iclass 28, count 2 2006.218.07:43:52.38#ibcon#about to read 6, iclass 28, count 2 2006.218.07:43:52.38#ibcon#read 6, iclass 28, count 2 2006.218.07:43:52.38#ibcon#end of sib2, iclass 28, count 2 2006.218.07:43:52.38#ibcon#*mode == 0, iclass 28, count 2 2006.218.07:43:52.38#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.218.07:43:52.38#ibcon#[27=AT06-04\r\n] 2006.218.07:43:52.38#ibcon#*before write, iclass 28, count 2 2006.218.07:43:52.38#ibcon#enter sib2, iclass 28, count 2 2006.218.07:43:52.38#ibcon#flushed, iclass 28, count 2 2006.218.07:43:52.38#ibcon#about to write, iclass 28, count 2 2006.218.07:43:52.38#ibcon#wrote, iclass 28, count 2 2006.218.07:43:52.38#ibcon#about to read 3, iclass 28, count 2 2006.218.07:43:52.41#ibcon#read 3, iclass 28, count 2 2006.218.07:43:52.41#ibcon#about to read 4, iclass 28, count 2 2006.218.07:43:52.41#ibcon#read 4, iclass 28, count 2 2006.218.07:43:52.41#ibcon#about to read 5, iclass 28, count 2 2006.218.07:43:52.41#ibcon#read 5, iclass 28, count 2 2006.218.07:43:52.41#ibcon#about to read 6, iclass 28, count 2 2006.218.07:43:52.41#ibcon#read 6, iclass 28, count 2 2006.218.07:43:52.41#ibcon#end of sib2, iclass 28, count 2 2006.218.07:43:52.41#ibcon#*after write, iclass 28, count 2 2006.218.07:43:52.41#ibcon#*before return 0, iclass 28, count 2 2006.218.07:43:52.41#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.218.07:43:52.41#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.218.07:43:52.41#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.218.07:43:52.41#ibcon#ireg 7 cls_cnt 0 2006.218.07:43:52.41#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.218.07:43:52.53#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.218.07:43:52.53#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.218.07:43:52.53#ibcon#enter wrdev, iclass 28, count 0 2006.218.07:43:52.53#ibcon#first serial, iclass 28, count 0 2006.218.07:43:52.53#ibcon#enter sib2, iclass 28, count 0 2006.218.07:43:52.53#ibcon#flushed, iclass 28, count 0 2006.218.07:43:52.53#ibcon#about to write, iclass 28, count 0 2006.218.07:43:52.53#ibcon#wrote, iclass 28, count 0 2006.218.07:43:52.53#ibcon#about to read 3, iclass 28, count 0 2006.218.07:43:52.55#ibcon#read 3, iclass 28, count 0 2006.218.07:43:52.55#ibcon#about to read 4, iclass 28, count 0 2006.218.07:43:52.55#ibcon#read 4, iclass 28, count 0 2006.218.07:43:52.55#ibcon#about to read 5, iclass 28, count 0 2006.218.07:43:52.55#ibcon#read 5, iclass 28, count 0 2006.218.07:43:52.55#ibcon#about to read 6, iclass 28, count 0 2006.218.07:43:52.55#ibcon#read 6, iclass 28, count 0 2006.218.07:43:52.55#ibcon#end of sib2, iclass 28, count 0 2006.218.07:43:52.55#ibcon#*mode == 0, iclass 28, count 0 2006.218.07:43:52.55#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.218.07:43:52.55#ibcon#[27=USB\r\n] 2006.218.07:43:52.55#ibcon#*before write, iclass 28, count 0 2006.218.07:43:52.55#ibcon#enter sib2, iclass 28, count 0 2006.218.07:43:52.55#ibcon#flushed, iclass 28, count 0 2006.218.07:43:52.55#ibcon#about to write, iclass 28, count 0 2006.218.07:43:52.55#ibcon#wrote, iclass 28, count 0 2006.218.07:43:52.55#ibcon#about to read 3, iclass 28, count 0 2006.218.07:43:52.58#ibcon#read 3, iclass 28, count 0 2006.218.07:43:52.58#ibcon#about to read 4, iclass 28, count 0 2006.218.07:43:52.58#ibcon#read 4, iclass 28, count 0 2006.218.07:43:52.58#ibcon#about to read 5, iclass 28, count 0 2006.218.07:43:52.58#ibcon#read 5, iclass 28, count 0 2006.218.07:43:52.58#ibcon#about to read 6, iclass 28, count 0 2006.218.07:43:52.58#ibcon#read 6, iclass 28, count 0 2006.218.07:43:52.58#ibcon#end of sib2, iclass 28, count 0 2006.218.07:43:52.58#ibcon#*after write, iclass 28, count 0 2006.218.07:43:52.58#ibcon#*before return 0, iclass 28, count 0 2006.218.07:43:52.58#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.218.07:43:52.58#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.218.07:43:52.58#ibcon#about to clear, iclass 28 cls_cnt 0 2006.218.07:43:52.58#ibcon#cleared, iclass 28 cls_cnt 0 2006.218.07:43:52.58$vc4f8/vabw=wide 2006.218.07:43:52.58#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.218.07:43:52.58#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.218.07:43:52.58#ibcon#ireg 8 cls_cnt 0 2006.218.07:43:52.58#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.218.07:43:52.58#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.218.07:43:52.58#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.218.07:43:52.58#ibcon#enter wrdev, iclass 30, count 0 2006.218.07:43:52.58#ibcon#first serial, iclass 30, count 0 2006.218.07:43:52.58#ibcon#enter sib2, iclass 30, count 0 2006.218.07:43:52.58#ibcon#flushed, iclass 30, count 0 2006.218.07:43:52.58#ibcon#about to write, iclass 30, count 0 2006.218.07:43:52.58#ibcon#wrote, iclass 30, count 0 2006.218.07:43:52.58#ibcon#about to read 3, iclass 30, count 0 2006.218.07:43:52.60#ibcon#read 3, iclass 30, count 0 2006.218.07:43:52.60#ibcon#about to read 4, iclass 30, count 0 2006.218.07:43:52.60#ibcon#read 4, iclass 30, count 0 2006.218.07:43:52.60#ibcon#about to read 5, iclass 30, count 0 2006.218.07:43:52.60#ibcon#read 5, iclass 30, count 0 2006.218.07:43:52.60#ibcon#about to read 6, iclass 30, count 0 2006.218.07:43:52.60#ibcon#read 6, iclass 30, count 0 2006.218.07:43:52.60#ibcon#end of sib2, iclass 30, count 0 2006.218.07:43:52.60#ibcon#*mode == 0, iclass 30, count 0 2006.218.07:43:52.60#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.218.07:43:52.60#ibcon#[25=BW32\r\n] 2006.218.07:43:52.60#ibcon#*before write, iclass 30, count 0 2006.218.07:43:52.60#ibcon#enter sib2, iclass 30, count 0 2006.218.07:43:52.60#ibcon#flushed, iclass 30, count 0 2006.218.07:43:52.60#ibcon#about to write, iclass 30, count 0 2006.218.07:43:52.60#ibcon#wrote, iclass 30, count 0 2006.218.07:43:52.60#ibcon#about to read 3, iclass 30, count 0 2006.218.07:43:52.63#ibcon#read 3, iclass 30, count 0 2006.218.07:43:52.63#ibcon#about to read 4, iclass 30, count 0 2006.218.07:43:52.63#ibcon#read 4, iclass 30, count 0 2006.218.07:43:52.63#ibcon#about to read 5, iclass 30, count 0 2006.218.07:43:52.63#ibcon#read 5, iclass 30, count 0 2006.218.07:43:52.63#ibcon#about to read 6, iclass 30, count 0 2006.218.07:43:52.63#ibcon#read 6, iclass 30, count 0 2006.218.07:43:52.63#ibcon#end of sib2, iclass 30, count 0 2006.218.07:43:52.63#ibcon#*after write, iclass 30, count 0 2006.218.07:43:52.63#ibcon#*before return 0, iclass 30, count 0 2006.218.07:43:52.63#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.218.07:43:52.63#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.218.07:43:52.63#ibcon#about to clear, iclass 30 cls_cnt 0 2006.218.07:43:52.63#ibcon#cleared, iclass 30 cls_cnt 0 2006.218.07:43:52.63$vc4f8/vbbw=wide 2006.218.07:43:52.63#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.218.07:43:52.63#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.218.07:43:52.63#ibcon#ireg 8 cls_cnt 0 2006.218.07:43:52.63#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.218.07:43:52.70#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.218.07:43:52.70#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.218.07:43:52.70#ibcon#enter wrdev, iclass 32, count 0 2006.218.07:43:52.70#ibcon#first serial, iclass 32, count 0 2006.218.07:43:52.70#ibcon#enter sib2, iclass 32, count 0 2006.218.07:43:52.70#ibcon#flushed, iclass 32, count 0 2006.218.07:43:52.70#ibcon#about to write, iclass 32, count 0 2006.218.07:43:52.70#ibcon#wrote, iclass 32, count 0 2006.218.07:43:52.70#ibcon#about to read 3, iclass 32, count 0 2006.218.07:43:52.72#ibcon#read 3, iclass 32, count 0 2006.218.07:43:52.72#ibcon#about to read 4, iclass 32, count 0 2006.218.07:43:52.72#ibcon#read 4, iclass 32, count 0 2006.218.07:43:52.72#ibcon#about to read 5, iclass 32, count 0 2006.218.07:43:52.72#ibcon#read 5, iclass 32, count 0 2006.218.07:43:52.72#ibcon#about to read 6, iclass 32, count 0 2006.218.07:43:52.72#ibcon#read 6, iclass 32, count 0 2006.218.07:43:52.72#ibcon#end of sib2, iclass 32, count 0 2006.218.07:43:52.72#ibcon#*mode == 0, iclass 32, count 0 2006.218.07:43:52.72#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.218.07:43:52.72#ibcon#[27=BW32\r\n] 2006.218.07:43:52.72#ibcon#*before write, iclass 32, count 0 2006.218.07:43:52.72#ibcon#enter sib2, iclass 32, count 0 2006.218.07:43:52.72#ibcon#flushed, iclass 32, count 0 2006.218.07:43:52.72#ibcon#about to write, iclass 32, count 0 2006.218.07:43:52.72#ibcon#wrote, iclass 32, count 0 2006.218.07:43:52.72#ibcon#about to read 3, iclass 32, count 0 2006.218.07:43:52.75#ibcon#read 3, iclass 32, count 0 2006.218.07:43:52.75#ibcon#about to read 4, iclass 32, count 0 2006.218.07:43:52.75#ibcon#read 4, iclass 32, count 0 2006.218.07:43:52.75#ibcon#about to read 5, iclass 32, count 0 2006.218.07:43:52.75#ibcon#read 5, iclass 32, count 0 2006.218.07:43:52.75#ibcon#about to read 6, iclass 32, count 0 2006.218.07:43:52.75#ibcon#read 6, iclass 32, count 0 2006.218.07:43:52.75#ibcon#end of sib2, iclass 32, count 0 2006.218.07:43:52.75#ibcon#*after write, iclass 32, count 0 2006.218.07:43:52.75#ibcon#*before return 0, iclass 32, count 0 2006.218.07:43:52.75#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.218.07:43:52.75#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.218.07:43:52.75#ibcon#about to clear, iclass 32 cls_cnt 0 2006.218.07:43:52.75#ibcon#cleared, iclass 32 cls_cnt 0 2006.218.07:43:52.75$4f8m12a/ifd4f 2006.218.07:43:52.75$ifd4f/lo= 2006.218.07:43:52.75$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.218.07:43:52.75$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.218.07:43:52.75$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.218.07:43:52.75$ifd4f/patch= 2006.218.07:43:52.75$ifd4f/patch=lo1,a1,a2,a3,a4 2006.218.07:43:52.75$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.218.07:43:52.75$ifd4f/patch=lo3,a5,a6,a7,a8 2006.218.07:43:52.75$4f8m12a/"form=m,16.000,1:2 2006.218.07:43:52.75$4f8m12a/"tpicd 2006.218.07:43:52.75$4f8m12a/echo=off 2006.218.07:43:52.75$4f8m12a/xlog=off 2006.218.07:43:52.75:!2006.218.07:44:20 2006.218.07:43:59.14#trakl#Source acquired 2006.218.07:43:59.14#flagr#flagr/antenna,acquired 2006.218.07:44:20.00:preob 2006.218.07:44:21.14/onsource/TRACKING 2006.218.07:44:21.14:!2006.218.07:44:30 2006.218.07:44:30.00:data_valid=on 2006.218.07:44:30.00:midob 2006.218.07:44:30.14/onsource/TRACKING 2006.218.07:44:30.14/wx/31.31,1007.4,73 2006.218.07:44:30.25/cable/+6.3831E-03 2006.218.07:44:31.34/va/01,05,usb,yes,32,33 2006.218.07:44:31.34/va/02,04,usb,yes,30,31 2006.218.07:44:31.34/va/03,04,usb,yes,28,28 2006.218.07:44:31.34/va/04,04,usb,yes,31,33 2006.218.07:44:31.34/va/05,07,usb,yes,33,35 2006.218.07:44:31.34/va/06,06,usb,yes,32,32 2006.218.07:44:31.34/va/07,06,usb,yes,33,32 2006.218.07:44:31.34/va/08,07,usb,yes,31,31 2006.218.07:44:31.57/valo/01,532.99,yes,locked 2006.218.07:44:31.57/valo/02,572.99,yes,locked 2006.218.07:44:31.57/valo/03,672.99,yes,locked 2006.218.07:44:31.57/valo/04,832.99,yes,locked 2006.218.07:44:31.57/valo/05,652.99,yes,locked 2006.218.07:44:31.57/valo/06,772.99,yes,locked 2006.218.07:44:31.57/valo/07,832.99,yes,locked 2006.218.07:44:31.57/valo/08,852.99,yes,locked 2006.218.07:44:32.66/vb/01,04,usb,yes,31,29 2006.218.07:44:32.66/vb/02,04,usb,yes,33,34 2006.218.07:44:32.66/vb/03,04,usb,yes,29,33 2006.218.07:44:32.66/vb/04,04,usb,yes,29,30 2006.218.07:44:32.66/vb/05,04,usb,yes,28,32 2006.218.07:44:32.66/vb/06,04,usb,yes,29,32 2006.218.07:44:32.66/vb/07,04,usb,yes,31,31 2006.218.07:44:32.66/vb/08,04,usb,yes,28,32 2006.218.07:44:32.90/vblo/01,632.99,yes,locked 2006.218.07:44:32.90/vblo/02,640.99,yes,locked 2006.218.07:44:32.90/vblo/03,656.99,yes,locked 2006.218.07:44:32.90/vblo/04,712.99,yes,locked 2006.218.07:44:32.90/vblo/05,744.99,yes,locked 2006.218.07:44:32.90/vblo/06,752.99,yes,locked 2006.218.07:44:32.90/vblo/07,734.99,yes,locked 2006.218.07:44:32.90/vblo/08,744.99,yes,locked 2006.218.07:44:33.05/vabw/8 2006.218.07:44:33.20/vbbw/8 2006.218.07:44:33.29/xfe/off,on,15.0 2006.218.07:44:33.66/ifatt/23,28,28,28 2006.218.07:44:34.08/fmout-gps/S +4.70E-07 2006.218.07:44:34.14:!2006.218.07:45:30 2006.218.07:45:30.00:data_valid=off 2006.218.07:45:30.00:postob 2006.218.07:45:30.08/cable/+6.3825E-03 2006.218.07:45:30.08/wx/31.29,1007.4,73 2006.218.07:45:31.07/fmout-gps/S +4.71E-07 2006.218.07:45:31.07:scan_name=218-0746,k06218,100 2006.218.07:45:31.07:source=1004+141,100741.50,135629.6,2000.0,ccw 2006.218.07:45:31.13#flagr#flagr/antenna,new-source 2006.218.07:45:32.13:checkk5 2006.218.07:45:32.50/chk_autoobs//k5ts1/ autoobs is running! 2006.218.07:45:32.87/chk_autoobs//k5ts2/ autoobs is running! 2006.218.07:45:33.25/chk_autoobs//k5ts3/ autoobs is running! 2006.218.07:45:33.63/chk_autoobs//k5ts4/ autoobs is running! 2006.218.07:45:34.00/chk_obsdata//k5ts1/T2180744??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:45:34.37/chk_obsdata//k5ts2/T2180744??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:45:34.73/chk_obsdata//k5ts3/T2180744??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:45:35.10/chk_obsdata//k5ts4/T2180744??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:45:35.79/k5log//k5ts1_log_newline 2006.218.07:45:36.48/k5log//k5ts2_log_newline 2006.218.07:45:37.18/k5log//k5ts3_log_newline 2006.218.07:45:37.87/k5log//k5ts4_log_newline 2006.218.07:45:37.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.218.07:45:37.89:4f8m12a=1 2006.218.07:45:37.89$4f8m12a/echo=on 2006.218.07:45:37.89$4f8m12a/pcalon 2006.218.07:45:37.89$pcalon/"no phase cal control is implemented here 2006.218.07:45:37.89$4f8m12a/"tpicd=stop 2006.218.07:45:37.89$4f8m12a/vc4f8 2006.218.07:45:37.89$vc4f8/valo=1,532.99 2006.218.07:45:37.90#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.218.07:45:37.90#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.218.07:45:37.90#ibcon#ireg 17 cls_cnt 0 2006.218.07:45:37.90#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.218.07:45:37.90#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.218.07:45:37.90#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.218.07:45:37.90#ibcon#enter wrdev, iclass 5, count 0 2006.218.07:45:37.90#ibcon#first serial, iclass 5, count 0 2006.218.07:45:37.90#ibcon#enter sib2, iclass 5, count 0 2006.218.07:45:37.90#ibcon#flushed, iclass 5, count 0 2006.218.07:45:37.90#ibcon#about to write, iclass 5, count 0 2006.218.07:45:37.90#ibcon#wrote, iclass 5, count 0 2006.218.07:45:37.90#ibcon#about to read 3, iclass 5, count 0 2006.218.07:45:37.94#ibcon#read 3, iclass 5, count 0 2006.218.07:45:37.94#ibcon#about to read 4, iclass 5, count 0 2006.218.07:45:37.94#ibcon#read 4, iclass 5, count 0 2006.218.07:45:37.94#ibcon#about to read 5, iclass 5, count 0 2006.218.07:45:37.94#ibcon#read 5, iclass 5, count 0 2006.218.07:45:37.94#ibcon#about to read 6, iclass 5, count 0 2006.218.07:45:37.94#ibcon#read 6, iclass 5, count 0 2006.218.07:45:37.94#ibcon#end of sib2, iclass 5, count 0 2006.218.07:45:37.94#ibcon#*mode == 0, iclass 5, count 0 2006.218.07:45:37.94#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.218.07:45:37.94#ibcon#[26=FRQ=01,532.99\r\n] 2006.218.07:45:37.94#ibcon#*before write, iclass 5, count 0 2006.218.07:45:37.94#ibcon#enter sib2, iclass 5, count 0 2006.218.07:45:37.94#ibcon#flushed, iclass 5, count 0 2006.218.07:45:37.94#ibcon#about to write, iclass 5, count 0 2006.218.07:45:37.94#ibcon#wrote, iclass 5, count 0 2006.218.07:45:37.94#ibcon#about to read 3, iclass 5, count 0 2006.218.07:45:37.99#ibcon#read 3, iclass 5, count 0 2006.218.07:45:37.99#ibcon#about to read 4, iclass 5, count 0 2006.218.07:45:37.99#ibcon#read 4, iclass 5, count 0 2006.218.07:45:37.99#ibcon#about to read 5, iclass 5, count 0 2006.218.07:45:37.99#ibcon#read 5, iclass 5, count 0 2006.218.07:45:37.99#ibcon#about to read 6, iclass 5, count 0 2006.218.07:45:37.99#ibcon#read 6, iclass 5, count 0 2006.218.07:45:37.99#ibcon#end of sib2, iclass 5, count 0 2006.218.07:45:37.99#ibcon#*after write, iclass 5, count 0 2006.218.07:45:37.99#ibcon#*before return 0, iclass 5, count 0 2006.218.07:45:37.99#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.218.07:45:37.99#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.218.07:45:37.99#ibcon#about to clear, iclass 5 cls_cnt 0 2006.218.07:45:37.99#ibcon#cleared, iclass 5 cls_cnt 0 2006.218.07:45:37.99$vc4f8/va=1,5 2006.218.07:45:37.99#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.218.07:45:37.99#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.218.07:45:37.99#ibcon#ireg 11 cls_cnt 2 2006.218.07:45:37.99#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.218.07:45:37.99#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.218.07:45:37.99#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.218.07:45:37.99#ibcon#enter wrdev, iclass 7, count 2 2006.218.07:45:37.99#ibcon#first serial, iclass 7, count 2 2006.218.07:45:37.99#ibcon#enter sib2, iclass 7, count 2 2006.218.07:45:37.99#ibcon#flushed, iclass 7, count 2 2006.218.07:45:37.99#ibcon#about to write, iclass 7, count 2 2006.218.07:45:37.99#ibcon#wrote, iclass 7, count 2 2006.218.07:45:37.99#ibcon#about to read 3, iclass 7, count 2 2006.218.07:45:38.01#ibcon#read 3, iclass 7, count 2 2006.218.07:45:38.01#ibcon#about to read 4, iclass 7, count 2 2006.218.07:45:38.01#ibcon#read 4, iclass 7, count 2 2006.218.07:45:38.01#ibcon#about to read 5, iclass 7, count 2 2006.218.07:45:38.01#ibcon#read 5, iclass 7, count 2 2006.218.07:45:38.01#ibcon#about to read 6, iclass 7, count 2 2006.218.07:45:38.01#ibcon#read 6, iclass 7, count 2 2006.218.07:45:38.01#ibcon#end of sib2, iclass 7, count 2 2006.218.07:45:38.01#ibcon#*mode == 0, iclass 7, count 2 2006.218.07:45:38.01#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.218.07:45:38.01#ibcon#[25=AT01-05\r\n] 2006.218.07:45:38.01#ibcon#*before write, iclass 7, count 2 2006.218.07:45:38.01#ibcon#enter sib2, iclass 7, count 2 2006.218.07:45:38.01#ibcon#flushed, iclass 7, count 2 2006.218.07:45:38.01#ibcon#about to write, iclass 7, count 2 2006.218.07:45:38.01#ibcon#wrote, iclass 7, count 2 2006.218.07:45:38.01#ibcon#about to read 3, iclass 7, count 2 2006.218.07:45:38.04#ibcon#read 3, iclass 7, count 2 2006.218.07:45:38.04#ibcon#about to read 4, iclass 7, count 2 2006.218.07:45:38.04#ibcon#read 4, iclass 7, count 2 2006.218.07:45:38.04#ibcon#about to read 5, iclass 7, count 2 2006.218.07:45:38.04#ibcon#read 5, iclass 7, count 2 2006.218.07:45:38.04#ibcon#about to read 6, iclass 7, count 2 2006.218.07:45:38.04#ibcon#read 6, iclass 7, count 2 2006.218.07:45:38.04#ibcon#end of sib2, iclass 7, count 2 2006.218.07:45:38.04#ibcon#*after write, iclass 7, count 2 2006.218.07:45:38.04#ibcon#*before return 0, iclass 7, count 2 2006.218.07:45:38.04#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.218.07:45:38.04#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.218.07:45:38.04#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.218.07:45:38.04#ibcon#ireg 7 cls_cnt 0 2006.218.07:45:38.04#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.218.07:45:38.16#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.218.07:45:38.16#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.218.07:45:38.16#ibcon#enter wrdev, iclass 7, count 0 2006.218.07:45:38.16#ibcon#first serial, iclass 7, count 0 2006.218.07:45:38.16#ibcon#enter sib2, iclass 7, count 0 2006.218.07:45:38.16#ibcon#flushed, iclass 7, count 0 2006.218.07:45:38.16#ibcon#about to write, iclass 7, count 0 2006.218.07:45:38.16#ibcon#wrote, iclass 7, count 0 2006.218.07:45:38.16#ibcon#about to read 3, iclass 7, count 0 2006.218.07:45:38.18#ibcon#read 3, iclass 7, count 0 2006.218.07:45:38.18#ibcon#about to read 4, iclass 7, count 0 2006.218.07:45:38.18#ibcon#read 4, iclass 7, count 0 2006.218.07:45:38.18#ibcon#about to read 5, iclass 7, count 0 2006.218.07:45:38.18#ibcon#read 5, iclass 7, count 0 2006.218.07:45:38.18#ibcon#about to read 6, iclass 7, count 0 2006.218.07:45:38.18#ibcon#read 6, iclass 7, count 0 2006.218.07:45:38.18#ibcon#end of sib2, iclass 7, count 0 2006.218.07:45:38.18#ibcon#*mode == 0, iclass 7, count 0 2006.218.07:45:38.18#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.218.07:45:38.18#ibcon#[25=USB\r\n] 2006.218.07:45:38.18#ibcon#*before write, iclass 7, count 0 2006.218.07:45:38.18#ibcon#enter sib2, iclass 7, count 0 2006.218.07:45:38.18#ibcon#flushed, iclass 7, count 0 2006.218.07:45:38.18#ibcon#about to write, iclass 7, count 0 2006.218.07:45:38.18#ibcon#wrote, iclass 7, count 0 2006.218.07:45:38.18#ibcon#about to read 3, iclass 7, count 0 2006.218.07:45:38.21#ibcon#read 3, iclass 7, count 0 2006.218.07:45:38.21#ibcon#about to read 4, iclass 7, count 0 2006.218.07:45:38.21#ibcon#read 4, iclass 7, count 0 2006.218.07:45:38.21#ibcon#about to read 5, iclass 7, count 0 2006.218.07:45:38.21#ibcon#read 5, iclass 7, count 0 2006.218.07:45:38.21#ibcon#about to read 6, iclass 7, count 0 2006.218.07:45:38.21#ibcon#read 6, iclass 7, count 0 2006.218.07:45:38.21#ibcon#end of sib2, iclass 7, count 0 2006.218.07:45:38.21#ibcon#*after write, iclass 7, count 0 2006.218.07:45:38.21#ibcon#*before return 0, iclass 7, count 0 2006.218.07:45:38.21#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.218.07:45:38.21#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.218.07:45:38.21#ibcon#about to clear, iclass 7 cls_cnt 0 2006.218.07:45:38.21#ibcon#cleared, iclass 7 cls_cnt 0 2006.218.07:45:38.21$vc4f8/valo=2,572.99 2006.218.07:45:38.21#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.218.07:45:38.21#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.218.07:45:38.21#ibcon#ireg 17 cls_cnt 0 2006.218.07:45:38.21#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.218.07:45:38.21#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.218.07:45:38.21#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.218.07:45:38.21#ibcon#enter wrdev, iclass 11, count 0 2006.218.07:45:38.21#ibcon#first serial, iclass 11, count 0 2006.218.07:45:38.21#ibcon#enter sib2, iclass 11, count 0 2006.218.07:45:38.21#ibcon#flushed, iclass 11, count 0 2006.218.07:45:38.21#ibcon#about to write, iclass 11, count 0 2006.218.07:45:38.21#ibcon#wrote, iclass 11, count 0 2006.218.07:45:38.21#ibcon#about to read 3, iclass 11, count 0 2006.218.07:45:38.23#ibcon#read 3, iclass 11, count 0 2006.218.07:45:38.23#ibcon#about to read 4, iclass 11, count 0 2006.218.07:45:38.23#ibcon#read 4, iclass 11, count 0 2006.218.07:45:38.23#ibcon#about to read 5, iclass 11, count 0 2006.218.07:45:38.23#ibcon#read 5, iclass 11, count 0 2006.218.07:45:38.23#ibcon#about to read 6, iclass 11, count 0 2006.218.07:45:38.23#ibcon#read 6, iclass 11, count 0 2006.218.07:45:38.23#ibcon#end of sib2, iclass 11, count 0 2006.218.07:45:38.23#ibcon#*mode == 0, iclass 11, count 0 2006.218.07:45:38.23#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.218.07:45:38.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.218.07:45:38.23#ibcon#*before write, iclass 11, count 0 2006.218.07:45:38.23#ibcon#enter sib2, iclass 11, count 0 2006.218.07:45:38.23#ibcon#flushed, iclass 11, count 0 2006.218.07:45:38.23#ibcon#about to write, iclass 11, count 0 2006.218.07:45:38.23#ibcon#wrote, iclass 11, count 0 2006.218.07:45:38.23#ibcon#about to read 3, iclass 11, count 0 2006.218.07:45:38.27#ibcon#read 3, iclass 11, count 0 2006.218.07:45:38.27#ibcon#about to read 4, iclass 11, count 0 2006.218.07:45:38.27#ibcon#read 4, iclass 11, count 0 2006.218.07:45:38.27#ibcon#about to read 5, iclass 11, count 0 2006.218.07:45:38.27#ibcon#read 5, iclass 11, count 0 2006.218.07:45:38.27#ibcon#about to read 6, iclass 11, count 0 2006.218.07:45:38.27#ibcon#read 6, iclass 11, count 0 2006.218.07:45:38.27#ibcon#end of sib2, iclass 11, count 0 2006.218.07:45:38.27#ibcon#*after write, iclass 11, count 0 2006.218.07:45:38.27#ibcon#*before return 0, iclass 11, count 0 2006.218.07:45:38.27#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.218.07:45:38.27#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.218.07:45:38.27#ibcon#about to clear, iclass 11 cls_cnt 0 2006.218.07:45:38.27#ibcon#cleared, iclass 11 cls_cnt 0 2006.218.07:45:38.27$vc4f8/va=2,4 2006.218.07:45:38.27#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.218.07:45:38.27#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.218.07:45:38.27#ibcon#ireg 11 cls_cnt 2 2006.218.07:45:38.27#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.218.07:45:38.33#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.218.07:45:38.33#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.218.07:45:38.33#ibcon#enter wrdev, iclass 13, count 2 2006.218.07:45:38.33#ibcon#first serial, iclass 13, count 2 2006.218.07:45:38.33#ibcon#enter sib2, iclass 13, count 2 2006.218.07:45:38.33#ibcon#flushed, iclass 13, count 2 2006.218.07:45:38.33#ibcon#about to write, iclass 13, count 2 2006.218.07:45:38.33#ibcon#wrote, iclass 13, count 2 2006.218.07:45:38.33#ibcon#about to read 3, iclass 13, count 2 2006.218.07:45:38.35#ibcon#read 3, iclass 13, count 2 2006.218.07:45:38.35#ibcon#about to read 4, iclass 13, count 2 2006.218.07:45:38.35#ibcon#read 4, iclass 13, count 2 2006.218.07:45:38.35#ibcon#about to read 5, iclass 13, count 2 2006.218.07:45:38.35#ibcon#read 5, iclass 13, count 2 2006.218.07:45:38.35#ibcon#about to read 6, iclass 13, count 2 2006.218.07:45:38.35#ibcon#read 6, iclass 13, count 2 2006.218.07:45:38.35#ibcon#end of sib2, iclass 13, count 2 2006.218.07:45:38.35#ibcon#*mode == 0, iclass 13, count 2 2006.218.07:45:38.35#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.218.07:45:38.35#ibcon#[25=AT02-04\r\n] 2006.218.07:45:38.35#ibcon#*before write, iclass 13, count 2 2006.218.07:45:38.35#ibcon#enter sib2, iclass 13, count 2 2006.218.07:45:38.35#ibcon#flushed, iclass 13, count 2 2006.218.07:45:38.35#ibcon#about to write, iclass 13, count 2 2006.218.07:45:38.35#ibcon#wrote, iclass 13, count 2 2006.218.07:45:38.35#ibcon#about to read 3, iclass 13, count 2 2006.218.07:45:38.38#ibcon#read 3, iclass 13, count 2 2006.218.07:45:38.38#ibcon#about to read 4, iclass 13, count 2 2006.218.07:45:38.38#ibcon#read 4, iclass 13, count 2 2006.218.07:45:38.38#ibcon#about to read 5, iclass 13, count 2 2006.218.07:45:38.38#ibcon#read 5, iclass 13, count 2 2006.218.07:45:38.38#ibcon#about to read 6, iclass 13, count 2 2006.218.07:45:38.38#ibcon#read 6, iclass 13, count 2 2006.218.07:45:38.38#ibcon#end of sib2, iclass 13, count 2 2006.218.07:45:38.38#ibcon#*after write, iclass 13, count 2 2006.218.07:45:38.38#ibcon#*before return 0, iclass 13, count 2 2006.218.07:45:38.38#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.218.07:45:38.38#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.218.07:45:38.38#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.218.07:45:38.38#ibcon#ireg 7 cls_cnt 0 2006.218.07:45:38.38#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.218.07:45:38.50#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.218.07:45:38.50#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.218.07:45:38.50#ibcon#enter wrdev, iclass 13, count 0 2006.218.07:45:38.50#ibcon#first serial, iclass 13, count 0 2006.218.07:45:38.50#ibcon#enter sib2, iclass 13, count 0 2006.218.07:45:38.50#ibcon#flushed, iclass 13, count 0 2006.218.07:45:38.50#ibcon#about to write, iclass 13, count 0 2006.218.07:45:38.50#ibcon#wrote, iclass 13, count 0 2006.218.07:45:38.50#ibcon#about to read 3, iclass 13, count 0 2006.218.07:45:38.52#ibcon#read 3, iclass 13, count 0 2006.218.07:45:38.52#ibcon#about to read 4, iclass 13, count 0 2006.218.07:45:38.52#ibcon#read 4, iclass 13, count 0 2006.218.07:45:38.52#ibcon#about to read 5, iclass 13, count 0 2006.218.07:45:38.52#ibcon#read 5, iclass 13, count 0 2006.218.07:45:38.52#ibcon#about to read 6, iclass 13, count 0 2006.218.07:45:38.52#ibcon#read 6, iclass 13, count 0 2006.218.07:45:38.52#ibcon#end of sib2, iclass 13, count 0 2006.218.07:45:38.52#ibcon#*mode == 0, iclass 13, count 0 2006.218.07:45:38.52#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.218.07:45:38.52#ibcon#[25=USB\r\n] 2006.218.07:45:38.52#ibcon#*before write, iclass 13, count 0 2006.218.07:45:38.52#ibcon#enter sib2, iclass 13, count 0 2006.218.07:45:38.52#ibcon#flushed, iclass 13, count 0 2006.218.07:45:38.52#ibcon#about to write, iclass 13, count 0 2006.218.07:45:38.52#ibcon#wrote, iclass 13, count 0 2006.218.07:45:38.52#ibcon#about to read 3, iclass 13, count 0 2006.218.07:45:38.55#ibcon#read 3, iclass 13, count 0 2006.218.07:45:38.55#ibcon#about to read 4, iclass 13, count 0 2006.218.07:45:38.55#ibcon#read 4, iclass 13, count 0 2006.218.07:45:38.55#ibcon#about to read 5, iclass 13, count 0 2006.218.07:45:38.55#ibcon#read 5, iclass 13, count 0 2006.218.07:45:38.55#ibcon#about to read 6, iclass 13, count 0 2006.218.07:45:38.55#ibcon#read 6, iclass 13, count 0 2006.218.07:45:38.55#ibcon#end of sib2, iclass 13, count 0 2006.218.07:45:38.55#ibcon#*after write, iclass 13, count 0 2006.218.07:45:38.55#ibcon#*before return 0, iclass 13, count 0 2006.218.07:45:38.55#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.218.07:45:38.55#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.218.07:45:38.55#ibcon#about to clear, iclass 13 cls_cnt 0 2006.218.07:45:38.55#ibcon#cleared, iclass 13 cls_cnt 0 2006.218.07:45:38.55$vc4f8/valo=3,672.99 2006.218.07:45:38.55#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.218.07:45:38.55#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.218.07:45:38.55#ibcon#ireg 17 cls_cnt 0 2006.218.07:45:38.55#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.218.07:45:38.55#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.218.07:45:38.55#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.218.07:45:38.55#ibcon#enter wrdev, iclass 15, count 0 2006.218.07:45:38.55#ibcon#first serial, iclass 15, count 0 2006.218.07:45:38.55#ibcon#enter sib2, iclass 15, count 0 2006.218.07:45:38.55#ibcon#flushed, iclass 15, count 0 2006.218.07:45:38.55#ibcon#about to write, iclass 15, count 0 2006.218.07:45:38.55#ibcon#wrote, iclass 15, count 0 2006.218.07:45:38.55#ibcon#about to read 3, iclass 15, count 0 2006.218.07:45:38.57#ibcon#read 3, iclass 15, count 0 2006.218.07:45:38.57#ibcon#about to read 4, iclass 15, count 0 2006.218.07:45:38.57#ibcon#read 4, iclass 15, count 0 2006.218.07:45:38.57#ibcon#about to read 5, iclass 15, count 0 2006.218.07:45:38.57#ibcon#read 5, iclass 15, count 0 2006.218.07:45:38.57#ibcon#about to read 6, iclass 15, count 0 2006.218.07:45:38.57#ibcon#read 6, iclass 15, count 0 2006.218.07:45:38.57#ibcon#end of sib2, iclass 15, count 0 2006.218.07:45:38.57#ibcon#*mode == 0, iclass 15, count 0 2006.218.07:45:38.57#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.218.07:45:38.57#ibcon#[26=FRQ=03,672.99\r\n] 2006.218.07:45:38.57#ibcon#*before write, iclass 15, count 0 2006.218.07:45:38.57#ibcon#enter sib2, iclass 15, count 0 2006.218.07:45:38.57#ibcon#flushed, iclass 15, count 0 2006.218.07:45:38.57#ibcon#about to write, iclass 15, count 0 2006.218.07:45:38.57#ibcon#wrote, iclass 15, count 0 2006.218.07:45:38.57#ibcon#about to read 3, iclass 15, count 0 2006.218.07:45:38.62#ibcon#read 3, iclass 15, count 0 2006.218.07:45:38.62#ibcon#about to read 4, iclass 15, count 0 2006.218.07:45:38.62#ibcon#read 4, iclass 15, count 0 2006.218.07:45:38.62#ibcon#about to read 5, iclass 15, count 0 2006.218.07:45:38.62#ibcon#read 5, iclass 15, count 0 2006.218.07:45:38.62#ibcon#about to read 6, iclass 15, count 0 2006.218.07:45:38.62#ibcon#read 6, iclass 15, count 0 2006.218.07:45:38.62#ibcon#end of sib2, iclass 15, count 0 2006.218.07:45:38.62#ibcon#*after write, iclass 15, count 0 2006.218.07:45:38.62#ibcon#*before return 0, iclass 15, count 0 2006.218.07:45:38.62#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.218.07:45:38.62#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.218.07:45:38.62#ibcon#about to clear, iclass 15 cls_cnt 0 2006.218.07:45:38.62#ibcon#cleared, iclass 15 cls_cnt 0 2006.218.07:45:38.62$vc4f8/va=3,4 2006.218.07:45:38.62#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.218.07:45:38.62#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.218.07:45:38.62#ibcon#ireg 11 cls_cnt 2 2006.218.07:45:38.62#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.218.07:45:38.67#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.218.07:45:38.67#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.218.07:45:38.67#ibcon#enter wrdev, iclass 17, count 2 2006.218.07:45:38.67#ibcon#first serial, iclass 17, count 2 2006.218.07:45:38.67#ibcon#enter sib2, iclass 17, count 2 2006.218.07:45:38.67#ibcon#flushed, iclass 17, count 2 2006.218.07:45:38.67#ibcon#about to write, iclass 17, count 2 2006.218.07:45:38.67#ibcon#wrote, iclass 17, count 2 2006.218.07:45:38.67#ibcon#about to read 3, iclass 17, count 2 2006.218.07:45:38.69#ibcon#read 3, iclass 17, count 2 2006.218.07:45:38.69#ibcon#about to read 4, iclass 17, count 2 2006.218.07:45:38.69#ibcon#read 4, iclass 17, count 2 2006.218.07:45:38.69#ibcon#about to read 5, iclass 17, count 2 2006.218.07:45:38.69#ibcon#read 5, iclass 17, count 2 2006.218.07:45:38.69#ibcon#about to read 6, iclass 17, count 2 2006.218.07:45:38.69#ibcon#read 6, iclass 17, count 2 2006.218.07:45:38.69#ibcon#end of sib2, iclass 17, count 2 2006.218.07:45:38.69#ibcon#*mode == 0, iclass 17, count 2 2006.218.07:45:38.69#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.218.07:45:38.69#ibcon#[25=AT03-04\r\n] 2006.218.07:45:38.69#ibcon#*before write, iclass 17, count 2 2006.218.07:45:38.69#ibcon#enter sib2, iclass 17, count 2 2006.218.07:45:38.69#ibcon#flushed, iclass 17, count 2 2006.218.07:45:38.69#ibcon#about to write, iclass 17, count 2 2006.218.07:45:38.69#ibcon#wrote, iclass 17, count 2 2006.218.07:45:38.69#ibcon#about to read 3, iclass 17, count 2 2006.218.07:45:38.72#ibcon#read 3, iclass 17, count 2 2006.218.07:45:38.72#ibcon#about to read 4, iclass 17, count 2 2006.218.07:45:38.72#ibcon#read 4, iclass 17, count 2 2006.218.07:45:38.72#ibcon#about to read 5, iclass 17, count 2 2006.218.07:45:38.72#ibcon#read 5, iclass 17, count 2 2006.218.07:45:38.72#ibcon#about to read 6, iclass 17, count 2 2006.218.07:45:38.72#ibcon#read 6, iclass 17, count 2 2006.218.07:45:38.72#ibcon#end of sib2, iclass 17, count 2 2006.218.07:45:38.72#ibcon#*after write, iclass 17, count 2 2006.218.07:45:38.72#ibcon#*before return 0, iclass 17, count 2 2006.218.07:45:38.72#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.218.07:45:38.72#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.218.07:45:38.72#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.218.07:45:38.72#ibcon#ireg 7 cls_cnt 0 2006.218.07:45:38.72#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.218.07:45:38.84#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.218.07:45:38.84#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.218.07:45:38.84#ibcon#enter wrdev, iclass 17, count 0 2006.218.07:45:38.84#ibcon#first serial, iclass 17, count 0 2006.218.07:45:38.84#ibcon#enter sib2, iclass 17, count 0 2006.218.07:45:38.84#ibcon#flushed, iclass 17, count 0 2006.218.07:45:38.84#ibcon#about to write, iclass 17, count 0 2006.218.07:45:38.84#ibcon#wrote, iclass 17, count 0 2006.218.07:45:38.84#ibcon#about to read 3, iclass 17, count 0 2006.218.07:45:38.86#ibcon#read 3, iclass 17, count 0 2006.218.07:45:38.86#ibcon#about to read 4, iclass 17, count 0 2006.218.07:45:38.86#ibcon#read 4, iclass 17, count 0 2006.218.07:45:38.86#ibcon#about to read 5, iclass 17, count 0 2006.218.07:45:38.86#ibcon#read 5, iclass 17, count 0 2006.218.07:45:38.86#ibcon#about to read 6, iclass 17, count 0 2006.218.07:45:38.86#ibcon#read 6, iclass 17, count 0 2006.218.07:45:38.86#ibcon#end of sib2, iclass 17, count 0 2006.218.07:45:38.86#ibcon#*mode == 0, iclass 17, count 0 2006.218.07:45:38.86#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.218.07:45:38.86#ibcon#[25=USB\r\n] 2006.218.07:45:38.86#ibcon#*before write, iclass 17, count 0 2006.218.07:45:38.86#ibcon#enter sib2, iclass 17, count 0 2006.218.07:45:38.86#ibcon#flushed, iclass 17, count 0 2006.218.07:45:38.86#ibcon#about to write, iclass 17, count 0 2006.218.07:45:38.86#ibcon#wrote, iclass 17, count 0 2006.218.07:45:38.86#ibcon#about to read 3, iclass 17, count 0 2006.218.07:45:38.89#ibcon#read 3, iclass 17, count 0 2006.218.07:45:38.89#ibcon#about to read 4, iclass 17, count 0 2006.218.07:45:38.89#ibcon#read 4, iclass 17, count 0 2006.218.07:45:38.89#ibcon#about to read 5, iclass 17, count 0 2006.218.07:45:38.89#ibcon#read 5, iclass 17, count 0 2006.218.07:45:38.89#ibcon#about to read 6, iclass 17, count 0 2006.218.07:45:38.89#ibcon#read 6, iclass 17, count 0 2006.218.07:45:38.89#ibcon#end of sib2, iclass 17, count 0 2006.218.07:45:38.89#ibcon#*after write, iclass 17, count 0 2006.218.07:45:38.89#ibcon#*before return 0, iclass 17, count 0 2006.218.07:45:38.89#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.218.07:45:38.89#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.218.07:45:38.89#ibcon#about to clear, iclass 17 cls_cnt 0 2006.218.07:45:38.89#ibcon#cleared, iclass 17 cls_cnt 0 2006.218.07:45:38.89$vc4f8/valo=4,832.99 2006.218.07:45:38.89#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.218.07:45:38.89#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.218.07:45:38.89#ibcon#ireg 17 cls_cnt 0 2006.218.07:45:38.89#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.218.07:45:38.89#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.218.07:45:38.89#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.218.07:45:38.89#ibcon#enter wrdev, iclass 19, count 0 2006.218.07:45:38.89#ibcon#first serial, iclass 19, count 0 2006.218.07:45:38.89#ibcon#enter sib2, iclass 19, count 0 2006.218.07:45:38.89#ibcon#flushed, iclass 19, count 0 2006.218.07:45:38.89#ibcon#about to write, iclass 19, count 0 2006.218.07:45:38.89#ibcon#wrote, iclass 19, count 0 2006.218.07:45:38.89#ibcon#about to read 3, iclass 19, count 0 2006.218.07:45:38.91#ibcon#read 3, iclass 19, count 0 2006.218.07:45:38.91#ibcon#about to read 4, iclass 19, count 0 2006.218.07:45:38.91#ibcon#read 4, iclass 19, count 0 2006.218.07:45:38.91#ibcon#about to read 5, iclass 19, count 0 2006.218.07:45:38.91#ibcon#read 5, iclass 19, count 0 2006.218.07:45:38.91#ibcon#about to read 6, iclass 19, count 0 2006.218.07:45:38.91#ibcon#read 6, iclass 19, count 0 2006.218.07:45:38.91#ibcon#end of sib2, iclass 19, count 0 2006.218.07:45:38.91#ibcon#*mode == 0, iclass 19, count 0 2006.218.07:45:38.91#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.218.07:45:38.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.218.07:45:38.91#ibcon#*before write, iclass 19, count 0 2006.218.07:45:38.91#ibcon#enter sib2, iclass 19, count 0 2006.218.07:45:38.91#ibcon#flushed, iclass 19, count 0 2006.218.07:45:38.91#ibcon#about to write, iclass 19, count 0 2006.218.07:45:38.91#ibcon#wrote, iclass 19, count 0 2006.218.07:45:38.91#ibcon#about to read 3, iclass 19, count 0 2006.218.07:45:38.95#ibcon#read 3, iclass 19, count 0 2006.218.07:45:38.95#ibcon#about to read 4, iclass 19, count 0 2006.218.07:45:38.95#ibcon#read 4, iclass 19, count 0 2006.218.07:45:38.95#ibcon#about to read 5, iclass 19, count 0 2006.218.07:45:38.95#ibcon#read 5, iclass 19, count 0 2006.218.07:45:38.95#ibcon#about to read 6, iclass 19, count 0 2006.218.07:45:38.95#ibcon#read 6, iclass 19, count 0 2006.218.07:45:38.95#ibcon#end of sib2, iclass 19, count 0 2006.218.07:45:38.95#ibcon#*after write, iclass 19, count 0 2006.218.07:45:38.95#ibcon#*before return 0, iclass 19, count 0 2006.218.07:45:38.95#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.218.07:45:38.95#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.218.07:45:38.95#ibcon#about to clear, iclass 19 cls_cnt 0 2006.218.07:45:38.95#ibcon#cleared, iclass 19 cls_cnt 0 2006.218.07:45:38.95$vc4f8/va=4,4 2006.218.07:45:38.95#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.218.07:45:38.95#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.218.07:45:38.95#ibcon#ireg 11 cls_cnt 2 2006.218.07:45:38.95#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.218.07:45:39.01#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.218.07:45:39.01#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.218.07:45:39.01#ibcon#enter wrdev, iclass 21, count 2 2006.218.07:45:39.01#ibcon#first serial, iclass 21, count 2 2006.218.07:45:39.01#ibcon#enter sib2, iclass 21, count 2 2006.218.07:45:39.01#ibcon#flushed, iclass 21, count 2 2006.218.07:45:39.01#ibcon#about to write, iclass 21, count 2 2006.218.07:45:39.01#ibcon#wrote, iclass 21, count 2 2006.218.07:45:39.01#ibcon#about to read 3, iclass 21, count 2 2006.218.07:45:39.03#ibcon#read 3, iclass 21, count 2 2006.218.07:45:39.03#ibcon#about to read 4, iclass 21, count 2 2006.218.07:45:39.03#ibcon#read 4, iclass 21, count 2 2006.218.07:45:39.03#ibcon#about to read 5, iclass 21, count 2 2006.218.07:45:39.03#ibcon#read 5, iclass 21, count 2 2006.218.07:45:39.03#ibcon#about to read 6, iclass 21, count 2 2006.218.07:45:39.03#ibcon#read 6, iclass 21, count 2 2006.218.07:45:39.03#ibcon#end of sib2, iclass 21, count 2 2006.218.07:45:39.03#ibcon#*mode == 0, iclass 21, count 2 2006.218.07:45:39.03#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.218.07:45:39.03#ibcon#[25=AT04-04\r\n] 2006.218.07:45:39.03#ibcon#*before write, iclass 21, count 2 2006.218.07:45:39.03#ibcon#enter sib2, iclass 21, count 2 2006.218.07:45:39.03#ibcon#flushed, iclass 21, count 2 2006.218.07:45:39.03#ibcon#about to write, iclass 21, count 2 2006.218.07:45:39.03#ibcon#wrote, iclass 21, count 2 2006.218.07:45:39.03#ibcon#about to read 3, iclass 21, count 2 2006.218.07:45:39.06#ibcon#read 3, iclass 21, count 2 2006.218.07:45:39.06#ibcon#about to read 4, iclass 21, count 2 2006.218.07:45:39.06#ibcon#read 4, iclass 21, count 2 2006.218.07:45:39.06#ibcon#about to read 5, iclass 21, count 2 2006.218.07:45:39.06#ibcon#read 5, iclass 21, count 2 2006.218.07:45:39.06#ibcon#about to read 6, iclass 21, count 2 2006.218.07:45:39.06#ibcon#read 6, iclass 21, count 2 2006.218.07:45:39.06#ibcon#end of sib2, iclass 21, count 2 2006.218.07:45:39.06#ibcon#*after write, iclass 21, count 2 2006.218.07:45:39.06#ibcon#*before return 0, iclass 21, count 2 2006.218.07:45:39.06#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.218.07:45:39.06#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.218.07:45:39.06#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.218.07:45:39.06#ibcon#ireg 7 cls_cnt 0 2006.218.07:45:39.06#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.218.07:45:39.18#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.218.07:45:39.18#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.218.07:45:39.18#ibcon#enter wrdev, iclass 21, count 0 2006.218.07:45:39.18#ibcon#first serial, iclass 21, count 0 2006.218.07:45:39.18#ibcon#enter sib2, iclass 21, count 0 2006.218.07:45:39.18#ibcon#flushed, iclass 21, count 0 2006.218.07:45:39.18#ibcon#about to write, iclass 21, count 0 2006.218.07:45:39.18#ibcon#wrote, iclass 21, count 0 2006.218.07:45:39.18#ibcon#about to read 3, iclass 21, count 0 2006.218.07:45:39.20#ibcon#read 3, iclass 21, count 0 2006.218.07:45:39.20#ibcon#about to read 4, iclass 21, count 0 2006.218.07:45:39.20#ibcon#read 4, iclass 21, count 0 2006.218.07:45:39.20#ibcon#about to read 5, iclass 21, count 0 2006.218.07:45:39.20#ibcon#read 5, iclass 21, count 0 2006.218.07:45:39.20#ibcon#about to read 6, iclass 21, count 0 2006.218.07:45:39.20#ibcon#read 6, iclass 21, count 0 2006.218.07:45:39.20#ibcon#end of sib2, iclass 21, count 0 2006.218.07:45:39.20#ibcon#*mode == 0, iclass 21, count 0 2006.218.07:45:39.20#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.218.07:45:39.20#ibcon#[25=USB\r\n] 2006.218.07:45:39.20#ibcon#*before write, iclass 21, count 0 2006.218.07:45:39.20#ibcon#enter sib2, iclass 21, count 0 2006.218.07:45:39.20#ibcon#flushed, iclass 21, count 0 2006.218.07:45:39.20#ibcon#about to write, iclass 21, count 0 2006.218.07:45:39.20#ibcon#wrote, iclass 21, count 0 2006.218.07:45:39.20#ibcon#about to read 3, iclass 21, count 0 2006.218.07:45:39.23#ibcon#read 3, iclass 21, count 0 2006.218.07:45:39.23#ibcon#about to read 4, iclass 21, count 0 2006.218.07:45:39.23#ibcon#read 4, iclass 21, count 0 2006.218.07:45:39.23#ibcon#about to read 5, iclass 21, count 0 2006.218.07:45:39.23#ibcon#read 5, iclass 21, count 0 2006.218.07:45:39.23#ibcon#about to read 6, iclass 21, count 0 2006.218.07:45:39.23#ibcon#read 6, iclass 21, count 0 2006.218.07:45:39.23#ibcon#end of sib2, iclass 21, count 0 2006.218.07:45:39.23#ibcon#*after write, iclass 21, count 0 2006.218.07:45:39.23#ibcon#*before return 0, iclass 21, count 0 2006.218.07:45:39.23#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.218.07:45:39.23#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.218.07:45:39.23#ibcon#about to clear, iclass 21 cls_cnt 0 2006.218.07:45:39.23#ibcon#cleared, iclass 21 cls_cnt 0 2006.218.07:45:39.23$vc4f8/valo=5,652.99 2006.218.07:45:39.23#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.218.07:45:39.23#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.218.07:45:39.23#ibcon#ireg 17 cls_cnt 0 2006.218.07:45:39.23#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.218.07:45:39.23#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.218.07:45:39.23#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.218.07:45:39.23#ibcon#enter wrdev, iclass 23, count 0 2006.218.07:45:39.23#ibcon#first serial, iclass 23, count 0 2006.218.07:45:39.23#ibcon#enter sib2, iclass 23, count 0 2006.218.07:45:39.23#ibcon#flushed, iclass 23, count 0 2006.218.07:45:39.23#ibcon#about to write, iclass 23, count 0 2006.218.07:45:39.23#ibcon#wrote, iclass 23, count 0 2006.218.07:45:39.23#ibcon#about to read 3, iclass 23, count 0 2006.218.07:45:39.25#ibcon#read 3, iclass 23, count 0 2006.218.07:45:39.25#ibcon#about to read 4, iclass 23, count 0 2006.218.07:45:39.25#ibcon#read 4, iclass 23, count 0 2006.218.07:45:39.25#ibcon#about to read 5, iclass 23, count 0 2006.218.07:45:39.25#ibcon#read 5, iclass 23, count 0 2006.218.07:45:39.25#ibcon#about to read 6, iclass 23, count 0 2006.218.07:45:39.25#ibcon#read 6, iclass 23, count 0 2006.218.07:45:39.25#ibcon#end of sib2, iclass 23, count 0 2006.218.07:45:39.25#ibcon#*mode == 0, iclass 23, count 0 2006.218.07:45:39.25#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.218.07:45:39.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.218.07:45:39.25#ibcon#*before write, iclass 23, count 0 2006.218.07:45:39.25#ibcon#enter sib2, iclass 23, count 0 2006.218.07:45:39.25#ibcon#flushed, iclass 23, count 0 2006.218.07:45:39.25#ibcon#about to write, iclass 23, count 0 2006.218.07:45:39.25#ibcon#wrote, iclass 23, count 0 2006.218.07:45:39.25#ibcon#about to read 3, iclass 23, count 0 2006.218.07:45:39.29#ibcon#read 3, iclass 23, count 0 2006.218.07:45:39.29#ibcon#about to read 4, iclass 23, count 0 2006.218.07:45:39.29#ibcon#read 4, iclass 23, count 0 2006.218.07:45:39.29#ibcon#about to read 5, iclass 23, count 0 2006.218.07:45:39.29#ibcon#read 5, iclass 23, count 0 2006.218.07:45:39.29#ibcon#about to read 6, iclass 23, count 0 2006.218.07:45:39.29#ibcon#read 6, iclass 23, count 0 2006.218.07:45:39.29#ibcon#end of sib2, iclass 23, count 0 2006.218.07:45:39.29#ibcon#*after write, iclass 23, count 0 2006.218.07:45:39.29#ibcon#*before return 0, iclass 23, count 0 2006.218.07:45:39.29#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.218.07:45:39.29#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.218.07:45:39.29#ibcon#about to clear, iclass 23 cls_cnt 0 2006.218.07:45:39.29#ibcon#cleared, iclass 23 cls_cnt 0 2006.218.07:45:39.29$vc4f8/va=5,7 2006.218.07:45:39.29#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.218.07:45:39.29#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.218.07:45:39.29#ibcon#ireg 11 cls_cnt 2 2006.218.07:45:39.29#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.218.07:45:39.35#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.218.07:45:39.35#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.218.07:45:39.35#ibcon#enter wrdev, iclass 25, count 2 2006.218.07:45:39.35#ibcon#first serial, iclass 25, count 2 2006.218.07:45:39.35#ibcon#enter sib2, iclass 25, count 2 2006.218.07:45:39.35#ibcon#flushed, iclass 25, count 2 2006.218.07:45:39.35#ibcon#about to write, iclass 25, count 2 2006.218.07:45:39.35#ibcon#wrote, iclass 25, count 2 2006.218.07:45:39.35#ibcon#about to read 3, iclass 25, count 2 2006.218.07:45:39.37#ibcon#read 3, iclass 25, count 2 2006.218.07:45:39.37#ibcon#about to read 4, iclass 25, count 2 2006.218.07:45:39.37#ibcon#read 4, iclass 25, count 2 2006.218.07:45:39.37#ibcon#about to read 5, iclass 25, count 2 2006.218.07:45:39.37#ibcon#read 5, iclass 25, count 2 2006.218.07:45:39.37#ibcon#about to read 6, iclass 25, count 2 2006.218.07:45:39.37#ibcon#read 6, iclass 25, count 2 2006.218.07:45:39.37#ibcon#end of sib2, iclass 25, count 2 2006.218.07:45:39.37#ibcon#*mode == 0, iclass 25, count 2 2006.218.07:45:39.37#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.218.07:45:39.37#ibcon#[25=AT05-07\r\n] 2006.218.07:45:39.37#ibcon#*before write, iclass 25, count 2 2006.218.07:45:39.37#ibcon#enter sib2, iclass 25, count 2 2006.218.07:45:39.37#ibcon#flushed, iclass 25, count 2 2006.218.07:45:39.37#ibcon#about to write, iclass 25, count 2 2006.218.07:45:39.37#ibcon#wrote, iclass 25, count 2 2006.218.07:45:39.37#ibcon#about to read 3, iclass 25, count 2 2006.218.07:45:39.40#ibcon#read 3, iclass 25, count 2 2006.218.07:45:39.40#ibcon#about to read 4, iclass 25, count 2 2006.218.07:45:39.40#ibcon#read 4, iclass 25, count 2 2006.218.07:45:39.40#ibcon#about to read 5, iclass 25, count 2 2006.218.07:45:39.40#ibcon#read 5, iclass 25, count 2 2006.218.07:45:39.40#ibcon#about to read 6, iclass 25, count 2 2006.218.07:45:39.40#ibcon#read 6, iclass 25, count 2 2006.218.07:45:39.40#ibcon#end of sib2, iclass 25, count 2 2006.218.07:45:39.40#ibcon#*after write, iclass 25, count 2 2006.218.07:45:39.40#ibcon#*before return 0, iclass 25, count 2 2006.218.07:45:39.40#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.218.07:45:39.40#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.218.07:45:39.40#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.218.07:45:39.40#ibcon#ireg 7 cls_cnt 0 2006.218.07:45:39.40#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.218.07:45:39.52#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.218.07:45:39.52#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.218.07:45:39.52#ibcon#enter wrdev, iclass 25, count 0 2006.218.07:45:39.52#ibcon#first serial, iclass 25, count 0 2006.218.07:45:39.52#ibcon#enter sib2, iclass 25, count 0 2006.218.07:45:39.52#ibcon#flushed, iclass 25, count 0 2006.218.07:45:39.52#ibcon#about to write, iclass 25, count 0 2006.218.07:45:39.52#ibcon#wrote, iclass 25, count 0 2006.218.07:45:39.52#ibcon#about to read 3, iclass 25, count 0 2006.218.07:45:39.54#ibcon#read 3, iclass 25, count 0 2006.218.07:45:39.54#ibcon#about to read 4, iclass 25, count 0 2006.218.07:45:39.54#ibcon#read 4, iclass 25, count 0 2006.218.07:45:39.54#ibcon#about to read 5, iclass 25, count 0 2006.218.07:45:39.54#ibcon#read 5, iclass 25, count 0 2006.218.07:45:39.54#ibcon#about to read 6, iclass 25, count 0 2006.218.07:45:39.54#ibcon#read 6, iclass 25, count 0 2006.218.07:45:39.54#ibcon#end of sib2, iclass 25, count 0 2006.218.07:45:39.54#ibcon#*mode == 0, iclass 25, count 0 2006.218.07:45:39.54#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.218.07:45:39.54#ibcon#[25=USB\r\n] 2006.218.07:45:39.54#ibcon#*before write, iclass 25, count 0 2006.218.07:45:39.54#ibcon#enter sib2, iclass 25, count 0 2006.218.07:45:39.54#ibcon#flushed, iclass 25, count 0 2006.218.07:45:39.54#ibcon#about to write, iclass 25, count 0 2006.218.07:45:39.54#ibcon#wrote, iclass 25, count 0 2006.218.07:45:39.54#ibcon#about to read 3, iclass 25, count 0 2006.218.07:45:39.57#ibcon#read 3, iclass 25, count 0 2006.218.07:45:39.57#ibcon#about to read 4, iclass 25, count 0 2006.218.07:45:39.57#ibcon#read 4, iclass 25, count 0 2006.218.07:45:39.57#ibcon#about to read 5, iclass 25, count 0 2006.218.07:45:39.57#ibcon#read 5, iclass 25, count 0 2006.218.07:45:39.57#ibcon#about to read 6, iclass 25, count 0 2006.218.07:45:39.57#ibcon#read 6, iclass 25, count 0 2006.218.07:45:39.57#ibcon#end of sib2, iclass 25, count 0 2006.218.07:45:39.57#ibcon#*after write, iclass 25, count 0 2006.218.07:45:39.57#ibcon#*before return 0, iclass 25, count 0 2006.218.07:45:39.57#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.218.07:45:39.57#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.218.07:45:39.57#ibcon#about to clear, iclass 25 cls_cnt 0 2006.218.07:45:39.57#ibcon#cleared, iclass 25 cls_cnt 0 2006.218.07:45:39.57$vc4f8/valo=6,772.99 2006.218.07:45:39.57#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.218.07:45:39.57#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.218.07:45:39.57#ibcon#ireg 17 cls_cnt 0 2006.218.07:45:39.57#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.218.07:45:39.57#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.218.07:45:39.57#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.218.07:45:39.57#ibcon#enter wrdev, iclass 27, count 0 2006.218.07:45:39.57#ibcon#first serial, iclass 27, count 0 2006.218.07:45:39.57#ibcon#enter sib2, iclass 27, count 0 2006.218.07:45:39.57#ibcon#flushed, iclass 27, count 0 2006.218.07:45:39.57#ibcon#about to write, iclass 27, count 0 2006.218.07:45:39.57#ibcon#wrote, iclass 27, count 0 2006.218.07:45:39.57#ibcon#about to read 3, iclass 27, count 0 2006.218.07:45:39.59#ibcon#read 3, iclass 27, count 0 2006.218.07:45:39.59#ibcon#about to read 4, iclass 27, count 0 2006.218.07:45:39.59#ibcon#read 4, iclass 27, count 0 2006.218.07:45:39.59#ibcon#about to read 5, iclass 27, count 0 2006.218.07:45:39.59#ibcon#read 5, iclass 27, count 0 2006.218.07:45:39.59#ibcon#about to read 6, iclass 27, count 0 2006.218.07:45:39.59#ibcon#read 6, iclass 27, count 0 2006.218.07:45:39.59#ibcon#end of sib2, iclass 27, count 0 2006.218.07:45:39.59#ibcon#*mode == 0, iclass 27, count 0 2006.218.07:45:39.59#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.218.07:45:39.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.218.07:45:39.59#ibcon#*before write, iclass 27, count 0 2006.218.07:45:39.59#ibcon#enter sib2, iclass 27, count 0 2006.218.07:45:39.59#ibcon#flushed, iclass 27, count 0 2006.218.07:45:39.59#ibcon#about to write, iclass 27, count 0 2006.218.07:45:39.59#ibcon#wrote, iclass 27, count 0 2006.218.07:45:39.59#ibcon#about to read 3, iclass 27, count 0 2006.218.07:45:39.63#ibcon#read 3, iclass 27, count 0 2006.218.07:45:39.63#ibcon#about to read 4, iclass 27, count 0 2006.218.07:45:39.63#ibcon#read 4, iclass 27, count 0 2006.218.07:45:39.63#ibcon#about to read 5, iclass 27, count 0 2006.218.07:45:39.63#ibcon#read 5, iclass 27, count 0 2006.218.07:45:39.63#ibcon#about to read 6, iclass 27, count 0 2006.218.07:45:39.63#ibcon#read 6, iclass 27, count 0 2006.218.07:45:39.63#ibcon#end of sib2, iclass 27, count 0 2006.218.07:45:39.63#ibcon#*after write, iclass 27, count 0 2006.218.07:45:39.63#ibcon#*before return 0, iclass 27, count 0 2006.218.07:45:39.63#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.218.07:45:39.63#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.218.07:45:39.63#ibcon#about to clear, iclass 27 cls_cnt 0 2006.218.07:45:39.63#ibcon#cleared, iclass 27 cls_cnt 0 2006.218.07:45:39.63$vc4f8/va=6,6 2006.218.07:45:39.63#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.218.07:45:39.63#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.218.07:45:39.63#ibcon#ireg 11 cls_cnt 2 2006.218.07:45:39.63#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.218.07:45:39.69#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.218.07:45:39.69#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.218.07:45:39.69#ibcon#enter wrdev, iclass 29, count 2 2006.218.07:45:39.69#ibcon#first serial, iclass 29, count 2 2006.218.07:45:39.69#ibcon#enter sib2, iclass 29, count 2 2006.218.07:45:39.69#ibcon#flushed, iclass 29, count 2 2006.218.07:45:39.69#ibcon#about to write, iclass 29, count 2 2006.218.07:45:39.69#ibcon#wrote, iclass 29, count 2 2006.218.07:45:39.69#ibcon#about to read 3, iclass 29, count 2 2006.218.07:45:39.71#ibcon#read 3, iclass 29, count 2 2006.218.07:45:39.71#ibcon#about to read 4, iclass 29, count 2 2006.218.07:45:39.71#ibcon#read 4, iclass 29, count 2 2006.218.07:45:39.71#ibcon#about to read 5, iclass 29, count 2 2006.218.07:45:39.71#ibcon#read 5, iclass 29, count 2 2006.218.07:45:39.71#ibcon#about to read 6, iclass 29, count 2 2006.218.07:45:39.71#ibcon#read 6, iclass 29, count 2 2006.218.07:45:39.71#ibcon#end of sib2, iclass 29, count 2 2006.218.07:45:39.71#ibcon#*mode == 0, iclass 29, count 2 2006.218.07:45:39.71#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.218.07:45:39.71#ibcon#[25=AT06-06\r\n] 2006.218.07:45:39.71#ibcon#*before write, iclass 29, count 2 2006.218.07:45:39.71#ibcon#enter sib2, iclass 29, count 2 2006.218.07:45:39.71#ibcon#flushed, iclass 29, count 2 2006.218.07:45:39.71#ibcon#about to write, iclass 29, count 2 2006.218.07:45:39.71#ibcon#wrote, iclass 29, count 2 2006.218.07:45:39.71#ibcon#about to read 3, iclass 29, count 2 2006.218.07:45:39.74#ibcon#read 3, iclass 29, count 2 2006.218.07:45:39.74#ibcon#about to read 4, iclass 29, count 2 2006.218.07:45:39.74#ibcon#read 4, iclass 29, count 2 2006.218.07:45:39.74#ibcon#about to read 5, iclass 29, count 2 2006.218.07:45:39.74#ibcon#read 5, iclass 29, count 2 2006.218.07:45:39.74#ibcon#about to read 6, iclass 29, count 2 2006.218.07:45:39.74#ibcon#read 6, iclass 29, count 2 2006.218.07:45:39.74#ibcon#end of sib2, iclass 29, count 2 2006.218.07:45:39.74#ibcon#*after write, iclass 29, count 2 2006.218.07:45:39.74#ibcon#*before return 0, iclass 29, count 2 2006.218.07:45:39.74#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.218.07:45:39.74#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.218.07:45:39.74#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.218.07:45:39.74#ibcon#ireg 7 cls_cnt 0 2006.218.07:45:39.74#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.218.07:45:39.86#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.218.07:45:39.86#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.218.07:45:39.86#ibcon#enter wrdev, iclass 29, count 0 2006.218.07:45:39.86#ibcon#first serial, iclass 29, count 0 2006.218.07:45:39.86#ibcon#enter sib2, iclass 29, count 0 2006.218.07:45:39.86#ibcon#flushed, iclass 29, count 0 2006.218.07:45:39.86#ibcon#about to write, iclass 29, count 0 2006.218.07:45:39.86#ibcon#wrote, iclass 29, count 0 2006.218.07:45:39.86#ibcon#about to read 3, iclass 29, count 0 2006.218.07:45:39.88#ibcon#read 3, iclass 29, count 0 2006.218.07:45:39.88#ibcon#about to read 4, iclass 29, count 0 2006.218.07:45:39.88#ibcon#read 4, iclass 29, count 0 2006.218.07:45:39.88#ibcon#about to read 5, iclass 29, count 0 2006.218.07:45:39.88#ibcon#read 5, iclass 29, count 0 2006.218.07:45:39.88#ibcon#about to read 6, iclass 29, count 0 2006.218.07:45:39.88#ibcon#read 6, iclass 29, count 0 2006.218.07:45:39.88#ibcon#end of sib2, iclass 29, count 0 2006.218.07:45:39.88#ibcon#*mode == 0, iclass 29, count 0 2006.218.07:45:39.88#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.218.07:45:39.88#ibcon#[25=USB\r\n] 2006.218.07:45:39.88#ibcon#*before write, iclass 29, count 0 2006.218.07:45:39.88#ibcon#enter sib2, iclass 29, count 0 2006.218.07:45:39.88#ibcon#flushed, iclass 29, count 0 2006.218.07:45:39.88#ibcon#about to write, iclass 29, count 0 2006.218.07:45:39.88#ibcon#wrote, iclass 29, count 0 2006.218.07:45:39.88#ibcon#about to read 3, iclass 29, count 0 2006.218.07:45:39.91#ibcon#read 3, iclass 29, count 0 2006.218.07:45:39.91#ibcon#about to read 4, iclass 29, count 0 2006.218.07:45:39.91#ibcon#read 4, iclass 29, count 0 2006.218.07:45:39.91#ibcon#about to read 5, iclass 29, count 0 2006.218.07:45:39.91#ibcon#read 5, iclass 29, count 0 2006.218.07:45:39.91#ibcon#about to read 6, iclass 29, count 0 2006.218.07:45:39.91#ibcon#read 6, iclass 29, count 0 2006.218.07:45:39.91#ibcon#end of sib2, iclass 29, count 0 2006.218.07:45:39.91#ibcon#*after write, iclass 29, count 0 2006.218.07:45:39.91#ibcon#*before return 0, iclass 29, count 0 2006.218.07:45:39.91#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.218.07:45:39.91#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.218.07:45:39.91#ibcon#about to clear, iclass 29 cls_cnt 0 2006.218.07:45:39.91#ibcon#cleared, iclass 29 cls_cnt 0 2006.218.07:45:39.91$vc4f8/valo=7,832.99 2006.218.07:45:39.91#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.218.07:45:39.91#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.218.07:45:39.91#ibcon#ireg 17 cls_cnt 0 2006.218.07:45:39.91#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.218.07:45:39.91#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.218.07:45:39.91#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.218.07:45:39.91#ibcon#enter wrdev, iclass 31, count 0 2006.218.07:45:39.91#ibcon#first serial, iclass 31, count 0 2006.218.07:45:39.91#ibcon#enter sib2, iclass 31, count 0 2006.218.07:45:39.91#ibcon#flushed, iclass 31, count 0 2006.218.07:45:39.91#ibcon#about to write, iclass 31, count 0 2006.218.07:45:39.91#ibcon#wrote, iclass 31, count 0 2006.218.07:45:39.91#ibcon#about to read 3, iclass 31, count 0 2006.218.07:45:39.93#ibcon#read 3, iclass 31, count 0 2006.218.07:45:39.93#ibcon#about to read 4, iclass 31, count 0 2006.218.07:45:39.93#ibcon#read 4, iclass 31, count 0 2006.218.07:45:39.93#ibcon#about to read 5, iclass 31, count 0 2006.218.07:45:39.93#ibcon#read 5, iclass 31, count 0 2006.218.07:45:39.93#ibcon#about to read 6, iclass 31, count 0 2006.218.07:45:39.93#ibcon#read 6, iclass 31, count 0 2006.218.07:45:39.93#ibcon#end of sib2, iclass 31, count 0 2006.218.07:45:39.93#ibcon#*mode == 0, iclass 31, count 0 2006.218.07:45:39.93#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.218.07:45:39.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.218.07:45:39.93#ibcon#*before write, iclass 31, count 0 2006.218.07:45:39.93#ibcon#enter sib2, iclass 31, count 0 2006.218.07:45:39.93#ibcon#flushed, iclass 31, count 0 2006.218.07:45:39.93#ibcon#about to write, iclass 31, count 0 2006.218.07:45:39.93#ibcon#wrote, iclass 31, count 0 2006.218.07:45:39.93#ibcon#about to read 3, iclass 31, count 0 2006.218.07:45:39.97#ibcon#read 3, iclass 31, count 0 2006.218.07:45:39.97#ibcon#about to read 4, iclass 31, count 0 2006.218.07:45:39.97#ibcon#read 4, iclass 31, count 0 2006.218.07:45:39.97#ibcon#about to read 5, iclass 31, count 0 2006.218.07:45:39.97#ibcon#read 5, iclass 31, count 0 2006.218.07:45:39.97#ibcon#about to read 6, iclass 31, count 0 2006.218.07:45:39.97#ibcon#read 6, iclass 31, count 0 2006.218.07:45:39.97#ibcon#end of sib2, iclass 31, count 0 2006.218.07:45:39.97#ibcon#*after write, iclass 31, count 0 2006.218.07:45:39.97#ibcon#*before return 0, iclass 31, count 0 2006.218.07:45:39.97#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.218.07:45:39.97#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.218.07:45:39.97#ibcon#about to clear, iclass 31 cls_cnt 0 2006.218.07:45:39.97#ibcon#cleared, iclass 31 cls_cnt 0 2006.218.07:45:39.97$vc4f8/va=7,6 2006.218.07:45:39.97#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.218.07:45:39.97#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.218.07:45:39.97#ibcon#ireg 11 cls_cnt 2 2006.218.07:45:39.97#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.218.07:45:40.03#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.218.07:45:40.03#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.218.07:45:40.03#ibcon#enter wrdev, iclass 33, count 2 2006.218.07:45:40.03#ibcon#first serial, iclass 33, count 2 2006.218.07:45:40.03#ibcon#enter sib2, iclass 33, count 2 2006.218.07:45:40.03#ibcon#flushed, iclass 33, count 2 2006.218.07:45:40.03#ibcon#about to write, iclass 33, count 2 2006.218.07:45:40.03#ibcon#wrote, iclass 33, count 2 2006.218.07:45:40.03#ibcon#about to read 3, iclass 33, count 2 2006.218.07:45:40.05#ibcon#read 3, iclass 33, count 2 2006.218.07:45:40.05#ibcon#about to read 4, iclass 33, count 2 2006.218.07:45:40.05#ibcon#read 4, iclass 33, count 2 2006.218.07:45:40.05#ibcon#about to read 5, iclass 33, count 2 2006.218.07:45:40.05#ibcon#read 5, iclass 33, count 2 2006.218.07:45:40.05#ibcon#about to read 6, iclass 33, count 2 2006.218.07:45:40.05#ibcon#read 6, iclass 33, count 2 2006.218.07:45:40.05#ibcon#end of sib2, iclass 33, count 2 2006.218.07:45:40.05#ibcon#*mode == 0, iclass 33, count 2 2006.218.07:45:40.05#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.218.07:45:40.05#ibcon#[25=AT07-06\r\n] 2006.218.07:45:40.05#ibcon#*before write, iclass 33, count 2 2006.218.07:45:40.05#ibcon#enter sib2, iclass 33, count 2 2006.218.07:45:40.05#ibcon#flushed, iclass 33, count 2 2006.218.07:45:40.05#ibcon#about to write, iclass 33, count 2 2006.218.07:45:40.05#ibcon#wrote, iclass 33, count 2 2006.218.07:45:40.05#ibcon#about to read 3, iclass 33, count 2 2006.218.07:45:40.08#ibcon#read 3, iclass 33, count 2 2006.218.07:45:40.08#ibcon#about to read 4, iclass 33, count 2 2006.218.07:45:40.08#ibcon#read 4, iclass 33, count 2 2006.218.07:45:40.08#ibcon#about to read 5, iclass 33, count 2 2006.218.07:45:40.08#ibcon#read 5, iclass 33, count 2 2006.218.07:45:40.08#ibcon#about to read 6, iclass 33, count 2 2006.218.07:45:40.08#ibcon#read 6, iclass 33, count 2 2006.218.07:45:40.08#ibcon#end of sib2, iclass 33, count 2 2006.218.07:45:40.08#ibcon#*after write, iclass 33, count 2 2006.218.07:45:40.08#ibcon#*before return 0, iclass 33, count 2 2006.218.07:45:40.08#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.218.07:45:40.08#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.218.07:45:40.08#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.218.07:45:40.08#ibcon#ireg 7 cls_cnt 0 2006.218.07:45:40.08#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.218.07:45:40.20#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.218.07:45:40.20#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.218.07:45:40.20#ibcon#enter wrdev, iclass 33, count 0 2006.218.07:45:40.20#ibcon#first serial, iclass 33, count 0 2006.218.07:45:40.20#ibcon#enter sib2, iclass 33, count 0 2006.218.07:45:40.20#ibcon#flushed, iclass 33, count 0 2006.218.07:45:40.20#ibcon#about to write, iclass 33, count 0 2006.218.07:45:40.20#ibcon#wrote, iclass 33, count 0 2006.218.07:45:40.20#ibcon#about to read 3, iclass 33, count 0 2006.218.07:45:40.22#ibcon#read 3, iclass 33, count 0 2006.218.07:45:40.22#ibcon#about to read 4, iclass 33, count 0 2006.218.07:45:40.22#ibcon#read 4, iclass 33, count 0 2006.218.07:45:40.22#ibcon#about to read 5, iclass 33, count 0 2006.218.07:45:40.22#ibcon#read 5, iclass 33, count 0 2006.218.07:45:40.22#ibcon#about to read 6, iclass 33, count 0 2006.218.07:45:40.22#ibcon#read 6, iclass 33, count 0 2006.218.07:45:40.22#ibcon#end of sib2, iclass 33, count 0 2006.218.07:45:40.22#ibcon#*mode == 0, iclass 33, count 0 2006.218.07:45:40.22#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.218.07:45:40.22#ibcon#[25=USB\r\n] 2006.218.07:45:40.22#ibcon#*before write, iclass 33, count 0 2006.218.07:45:40.22#ibcon#enter sib2, iclass 33, count 0 2006.218.07:45:40.22#ibcon#flushed, iclass 33, count 0 2006.218.07:45:40.22#ibcon#about to write, iclass 33, count 0 2006.218.07:45:40.22#ibcon#wrote, iclass 33, count 0 2006.218.07:45:40.22#ibcon#about to read 3, iclass 33, count 0 2006.218.07:45:40.25#ibcon#read 3, iclass 33, count 0 2006.218.07:45:40.25#ibcon#about to read 4, iclass 33, count 0 2006.218.07:45:40.25#ibcon#read 4, iclass 33, count 0 2006.218.07:45:40.25#ibcon#about to read 5, iclass 33, count 0 2006.218.07:45:40.25#ibcon#read 5, iclass 33, count 0 2006.218.07:45:40.25#ibcon#about to read 6, iclass 33, count 0 2006.218.07:45:40.25#ibcon#read 6, iclass 33, count 0 2006.218.07:45:40.25#ibcon#end of sib2, iclass 33, count 0 2006.218.07:45:40.25#ibcon#*after write, iclass 33, count 0 2006.218.07:45:40.25#ibcon#*before return 0, iclass 33, count 0 2006.218.07:45:40.25#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.218.07:45:40.25#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.218.07:45:40.25#ibcon#about to clear, iclass 33 cls_cnt 0 2006.218.07:45:40.25#ibcon#cleared, iclass 33 cls_cnt 0 2006.218.07:45:40.25$vc4f8/valo=8,852.99 2006.218.07:45:40.25#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.218.07:45:40.25#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.218.07:45:40.25#ibcon#ireg 17 cls_cnt 0 2006.218.07:45:40.25#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.218.07:45:40.25#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.218.07:45:40.25#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.218.07:45:40.25#ibcon#enter wrdev, iclass 35, count 0 2006.218.07:45:40.25#ibcon#first serial, iclass 35, count 0 2006.218.07:45:40.25#ibcon#enter sib2, iclass 35, count 0 2006.218.07:45:40.25#ibcon#flushed, iclass 35, count 0 2006.218.07:45:40.25#ibcon#about to write, iclass 35, count 0 2006.218.07:45:40.25#ibcon#wrote, iclass 35, count 0 2006.218.07:45:40.25#ibcon#about to read 3, iclass 35, count 0 2006.218.07:45:40.27#ibcon#read 3, iclass 35, count 0 2006.218.07:45:40.27#ibcon#about to read 4, iclass 35, count 0 2006.218.07:45:40.27#ibcon#read 4, iclass 35, count 0 2006.218.07:45:40.27#ibcon#about to read 5, iclass 35, count 0 2006.218.07:45:40.27#ibcon#read 5, iclass 35, count 0 2006.218.07:45:40.27#ibcon#about to read 6, iclass 35, count 0 2006.218.07:45:40.27#ibcon#read 6, iclass 35, count 0 2006.218.07:45:40.27#ibcon#end of sib2, iclass 35, count 0 2006.218.07:45:40.27#ibcon#*mode == 0, iclass 35, count 0 2006.218.07:45:40.27#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.218.07:45:40.27#ibcon#[26=FRQ=08,852.99\r\n] 2006.218.07:45:40.27#ibcon#*before write, iclass 35, count 0 2006.218.07:45:40.27#ibcon#enter sib2, iclass 35, count 0 2006.218.07:45:40.27#ibcon#flushed, iclass 35, count 0 2006.218.07:45:40.27#ibcon#about to write, iclass 35, count 0 2006.218.07:45:40.27#ibcon#wrote, iclass 35, count 0 2006.218.07:45:40.27#ibcon#about to read 3, iclass 35, count 0 2006.218.07:45:40.31#ibcon#read 3, iclass 35, count 0 2006.218.07:45:40.31#ibcon#about to read 4, iclass 35, count 0 2006.218.07:45:40.31#ibcon#read 4, iclass 35, count 0 2006.218.07:45:40.31#ibcon#about to read 5, iclass 35, count 0 2006.218.07:45:40.31#ibcon#read 5, iclass 35, count 0 2006.218.07:45:40.31#ibcon#about to read 6, iclass 35, count 0 2006.218.07:45:40.31#ibcon#read 6, iclass 35, count 0 2006.218.07:45:40.31#ibcon#end of sib2, iclass 35, count 0 2006.218.07:45:40.31#ibcon#*after write, iclass 35, count 0 2006.218.07:45:40.31#ibcon#*before return 0, iclass 35, count 0 2006.218.07:45:40.31#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.218.07:45:40.31#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.218.07:45:40.31#ibcon#about to clear, iclass 35 cls_cnt 0 2006.218.07:45:40.31#ibcon#cleared, iclass 35 cls_cnt 0 2006.218.07:45:40.31$vc4f8/va=8,7 2006.218.07:45:40.31#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.218.07:45:40.31#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.218.07:45:40.31#ibcon#ireg 11 cls_cnt 2 2006.218.07:45:40.31#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.218.07:45:40.37#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.218.07:45:40.37#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.218.07:45:40.37#ibcon#enter wrdev, iclass 37, count 2 2006.218.07:45:40.37#ibcon#first serial, iclass 37, count 2 2006.218.07:45:40.37#ibcon#enter sib2, iclass 37, count 2 2006.218.07:45:40.37#ibcon#flushed, iclass 37, count 2 2006.218.07:45:40.37#ibcon#about to write, iclass 37, count 2 2006.218.07:45:40.37#ibcon#wrote, iclass 37, count 2 2006.218.07:45:40.37#ibcon#about to read 3, iclass 37, count 2 2006.218.07:45:40.39#ibcon#read 3, iclass 37, count 2 2006.218.07:45:40.39#ibcon#about to read 4, iclass 37, count 2 2006.218.07:45:40.39#ibcon#read 4, iclass 37, count 2 2006.218.07:45:40.39#ibcon#about to read 5, iclass 37, count 2 2006.218.07:45:40.39#ibcon#read 5, iclass 37, count 2 2006.218.07:45:40.39#ibcon#about to read 6, iclass 37, count 2 2006.218.07:45:40.39#ibcon#read 6, iclass 37, count 2 2006.218.07:45:40.39#ibcon#end of sib2, iclass 37, count 2 2006.218.07:45:40.39#ibcon#*mode == 0, iclass 37, count 2 2006.218.07:45:40.39#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.218.07:45:40.39#ibcon#[25=AT08-07\r\n] 2006.218.07:45:40.39#ibcon#*before write, iclass 37, count 2 2006.218.07:45:40.39#ibcon#enter sib2, iclass 37, count 2 2006.218.07:45:40.39#ibcon#flushed, iclass 37, count 2 2006.218.07:45:40.39#ibcon#about to write, iclass 37, count 2 2006.218.07:45:40.39#ibcon#wrote, iclass 37, count 2 2006.218.07:45:40.39#ibcon#about to read 3, iclass 37, count 2 2006.218.07:45:40.43#ibcon#read 3, iclass 37, count 2 2006.218.07:45:40.43#ibcon#about to read 4, iclass 37, count 2 2006.218.07:45:40.43#ibcon#read 4, iclass 37, count 2 2006.218.07:45:40.43#ibcon#about to read 5, iclass 37, count 2 2006.218.07:45:40.43#ibcon#read 5, iclass 37, count 2 2006.218.07:45:40.43#ibcon#about to read 6, iclass 37, count 2 2006.218.07:45:40.43#ibcon#read 6, iclass 37, count 2 2006.218.07:45:40.43#ibcon#end of sib2, iclass 37, count 2 2006.218.07:45:40.43#ibcon#*after write, iclass 37, count 2 2006.218.07:45:40.43#ibcon#*before return 0, iclass 37, count 2 2006.218.07:45:40.43#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.218.07:45:40.43#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.218.07:45:40.43#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.218.07:45:40.43#ibcon#ireg 7 cls_cnt 0 2006.218.07:45:40.43#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.218.07:45:40.55#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.218.07:45:40.55#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.218.07:45:40.55#ibcon#enter wrdev, iclass 37, count 0 2006.218.07:45:40.55#ibcon#first serial, iclass 37, count 0 2006.218.07:45:40.55#ibcon#enter sib2, iclass 37, count 0 2006.218.07:45:40.55#ibcon#flushed, iclass 37, count 0 2006.218.07:45:40.55#ibcon#about to write, iclass 37, count 0 2006.218.07:45:40.55#ibcon#wrote, iclass 37, count 0 2006.218.07:45:40.55#ibcon#about to read 3, iclass 37, count 0 2006.218.07:45:40.57#ibcon#read 3, iclass 37, count 0 2006.218.07:45:40.57#ibcon#about to read 4, iclass 37, count 0 2006.218.07:45:40.57#ibcon#read 4, iclass 37, count 0 2006.218.07:45:40.57#ibcon#about to read 5, iclass 37, count 0 2006.218.07:45:40.57#ibcon#read 5, iclass 37, count 0 2006.218.07:45:40.57#ibcon#about to read 6, iclass 37, count 0 2006.218.07:45:40.57#ibcon#read 6, iclass 37, count 0 2006.218.07:45:40.57#ibcon#end of sib2, iclass 37, count 0 2006.218.07:45:40.57#ibcon#*mode == 0, iclass 37, count 0 2006.218.07:45:40.57#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.218.07:45:40.57#ibcon#[25=USB\r\n] 2006.218.07:45:40.57#ibcon#*before write, iclass 37, count 0 2006.218.07:45:40.57#ibcon#enter sib2, iclass 37, count 0 2006.218.07:45:40.57#ibcon#flushed, iclass 37, count 0 2006.218.07:45:40.57#ibcon#about to write, iclass 37, count 0 2006.218.07:45:40.57#ibcon#wrote, iclass 37, count 0 2006.218.07:45:40.57#ibcon#about to read 3, iclass 37, count 0 2006.218.07:45:40.60#ibcon#read 3, iclass 37, count 0 2006.218.07:45:40.60#ibcon#about to read 4, iclass 37, count 0 2006.218.07:45:40.60#ibcon#read 4, iclass 37, count 0 2006.218.07:45:40.60#ibcon#about to read 5, iclass 37, count 0 2006.218.07:45:40.60#ibcon#read 5, iclass 37, count 0 2006.218.07:45:40.60#ibcon#about to read 6, iclass 37, count 0 2006.218.07:45:40.60#ibcon#read 6, iclass 37, count 0 2006.218.07:45:40.60#ibcon#end of sib2, iclass 37, count 0 2006.218.07:45:40.60#ibcon#*after write, iclass 37, count 0 2006.218.07:45:40.60#ibcon#*before return 0, iclass 37, count 0 2006.218.07:45:40.60#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.218.07:45:40.60#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.218.07:45:40.60#ibcon#about to clear, iclass 37 cls_cnt 0 2006.218.07:45:40.60#ibcon#cleared, iclass 37 cls_cnt 0 2006.218.07:45:40.60$vc4f8/vblo=1,632.99 2006.218.07:45:40.60#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.218.07:45:40.60#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.218.07:45:40.60#ibcon#ireg 17 cls_cnt 0 2006.218.07:45:40.60#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.218.07:45:40.60#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.218.07:45:40.60#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.218.07:45:40.60#ibcon#enter wrdev, iclass 39, count 0 2006.218.07:45:40.60#ibcon#first serial, iclass 39, count 0 2006.218.07:45:40.60#ibcon#enter sib2, iclass 39, count 0 2006.218.07:45:40.60#ibcon#flushed, iclass 39, count 0 2006.218.07:45:40.60#ibcon#about to write, iclass 39, count 0 2006.218.07:45:40.60#ibcon#wrote, iclass 39, count 0 2006.218.07:45:40.60#ibcon#about to read 3, iclass 39, count 0 2006.218.07:45:40.62#ibcon#read 3, iclass 39, count 0 2006.218.07:45:40.62#ibcon#about to read 4, iclass 39, count 0 2006.218.07:45:40.62#ibcon#read 4, iclass 39, count 0 2006.218.07:45:40.62#ibcon#about to read 5, iclass 39, count 0 2006.218.07:45:40.62#ibcon#read 5, iclass 39, count 0 2006.218.07:45:40.62#ibcon#about to read 6, iclass 39, count 0 2006.218.07:45:40.62#ibcon#read 6, iclass 39, count 0 2006.218.07:45:40.62#ibcon#end of sib2, iclass 39, count 0 2006.218.07:45:40.62#ibcon#*mode == 0, iclass 39, count 0 2006.218.07:45:40.62#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.218.07:45:40.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.218.07:45:40.62#ibcon#*before write, iclass 39, count 0 2006.218.07:45:40.62#ibcon#enter sib2, iclass 39, count 0 2006.218.07:45:40.62#ibcon#flushed, iclass 39, count 0 2006.218.07:45:40.62#ibcon#about to write, iclass 39, count 0 2006.218.07:45:40.62#ibcon#wrote, iclass 39, count 0 2006.218.07:45:40.62#ibcon#about to read 3, iclass 39, count 0 2006.218.07:45:40.66#ibcon#read 3, iclass 39, count 0 2006.218.07:45:40.66#ibcon#about to read 4, iclass 39, count 0 2006.218.07:45:40.66#ibcon#read 4, iclass 39, count 0 2006.218.07:45:40.66#ibcon#about to read 5, iclass 39, count 0 2006.218.07:45:40.66#ibcon#read 5, iclass 39, count 0 2006.218.07:45:40.66#ibcon#about to read 6, iclass 39, count 0 2006.218.07:45:40.66#ibcon#read 6, iclass 39, count 0 2006.218.07:45:40.66#ibcon#end of sib2, iclass 39, count 0 2006.218.07:45:40.66#ibcon#*after write, iclass 39, count 0 2006.218.07:45:40.66#ibcon#*before return 0, iclass 39, count 0 2006.218.07:45:40.66#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.218.07:45:40.66#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.218.07:45:40.66#ibcon#about to clear, iclass 39 cls_cnt 0 2006.218.07:45:40.66#ibcon#cleared, iclass 39 cls_cnt 0 2006.218.07:45:40.66$vc4f8/vb=1,4 2006.218.07:45:40.66#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.218.07:45:40.66#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.218.07:45:40.66#ibcon#ireg 11 cls_cnt 2 2006.218.07:45:40.66#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.218.07:45:40.66#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.218.07:45:40.66#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.218.07:45:40.66#ibcon#enter wrdev, iclass 3, count 2 2006.218.07:45:40.66#ibcon#first serial, iclass 3, count 2 2006.218.07:45:40.66#ibcon#enter sib2, iclass 3, count 2 2006.218.07:45:40.66#ibcon#flushed, iclass 3, count 2 2006.218.07:45:40.66#ibcon#about to write, iclass 3, count 2 2006.218.07:45:40.66#ibcon#wrote, iclass 3, count 2 2006.218.07:45:40.66#ibcon#about to read 3, iclass 3, count 2 2006.218.07:45:40.68#ibcon#read 3, iclass 3, count 2 2006.218.07:45:40.68#ibcon#about to read 4, iclass 3, count 2 2006.218.07:45:40.68#ibcon#read 4, iclass 3, count 2 2006.218.07:45:40.68#ibcon#about to read 5, iclass 3, count 2 2006.218.07:45:40.68#ibcon#read 5, iclass 3, count 2 2006.218.07:45:40.68#ibcon#about to read 6, iclass 3, count 2 2006.218.07:45:40.68#ibcon#read 6, iclass 3, count 2 2006.218.07:45:40.68#ibcon#end of sib2, iclass 3, count 2 2006.218.07:45:40.68#ibcon#*mode == 0, iclass 3, count 2 2006.218.07:45:40.68#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.218.07:45:40.68#ibcon#[27=AT01-04\r\n] 2006.218.07:45:40.68#ibcon#*before write, iclass 3, count 2 2006.218.07:45:40.68#ibcon#enter sib2, iclass 3, count 2 2006.218.07:45:40.68#ibcon#flushed, iclass 3, count 2 2006.218.07:45:40.68#ibcon#about to write, iclass 3, count 2 2006.218.07:45:40.68#ibcon#wrote, iclass 3, count 2 2006.218.07:45:40.68#ibcon#about to read 3, iclass 3, count 2 2006.218.07:45:40.71#ibcon#read 3, iclass 3, count 2 2006.218.07:45:40.71#ibcon#about to read 4, iclass 3, count 2 2006.218.07:45:40.71#ibcon#read 4, iclass 3, count 2 2006.218.07:45:40.71#ibcon#about to read 5, iclass 3, count 2 2006.218.07:45:40.71#ibcon#read 5, iclass 3, count 2 2006.218.07:45:40.71#ibcon#about to read 6, iclass 3, count 2 2006.218.07:45:40.71#ibcon#read 6, iclass 3, count 2 2006.218.07:45:40.71#ibcon#end of sib2, iclass 3, count 2 2006.218.07:45:40.71#ibcon#*after write, iclass 3, count 2 2006.218.07:45:40.71#ibcon#*before return 0, iclass 3, count 2 2006.218.07:45:40.71#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.218.07:45:40.71#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.218.07:45:40.71#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.218.07:45:40.71#ibcon#ireg 7 cls_cnt 0 2006.218.07:45:40.71#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.218.07:45:40.83#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.218.07:45:40.83#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.218.07:45:40.83#ibcon#enter wrdev, iclass 3, count 0 2006.218.07:45:40.83#ibcon#first serial, iclass 3, count 0 2006.218.07:45:40.83#ibcon#enter sib2, iclass 3, count 0 2006.218.07:45:40.83#ibcon#flushed, iclass 3, count 0 2006.218.07:45:40.83#ibcon#about to write, iclass 3, count 0 2006.218.07:45:40.83#ibcon#wrote, iclass 3, count 0 2006.218.07:45:40.83#ibcon#about to read 3, iclass 3, count 0 2006.218.07:45:40.85#ibcon#read 3, iclass 3, count 0 2006.218.07:45:40.85#ibcon#about to read 4, iclass 3, count 0 2006.218.07:45:40.85#ibcon#read 4, iclass 3, count 0 2006.218.07:45:40.85#ibcon#about to read 5, iclass 3, count 0 2006.218.07:45:40.85#ibcon#read 5, iclass 3, count 0 2006.218.07:45:40.85#ibcon#about to read 6, iclass 3, count 0 2006.218.07:45:40.85#ibcon#read 6, iclass 3, count 0 2006.218.07:45:40.85#ibcon#end of sib2, iclass 3, count 0 2006.218.07:45:40.85#ibcon#*mode == 0, iclass 3, count 0 2006.218.07:45:40.85#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.218.07:45:40.85#ibcon#[27=USB\r\n] 2006.218.07:45:40.85#ibcon#*before write, iclass 3, count 0 2006.218.07:45:40.85#ibcon#enter sib2, iclass 3, count 0 2006.218.07:45:40.85#ibcon#flushed, iclass 3, count 0 2006.218.07:45:40.85#ibcon#about to write, iclass 3, count 0 2006.218.07:45:40.85#ibcon#wrote, iclass 3, count 0 2006.218.07:45:40.85#ibcon#about to read 3, iclass 3, count 0 2006.218.07:45:40.88#ibcon#read 3, iclass 3, count 0 2006.218.07:45:40.88#ibcon#about to read 4, iclass 3, count 0 2006.218.07:45:40.88#ibcon#read 4, iclass 3, count 0 2006.218.07:45:40.88#ibcon#about to read 5, iclass 3, count 0 2006.218.07:45:40.88#ibcon#read 5, iclass 3, count 0 2006.218.07:45:40.88#ibcon#about to read 6, iclass 3, count 0 2006.218.07:45:40.88#ibcon#read 6, iclass 3, count 0 2006.218.07:45:40.88#ibcon#end of sib2, iclass 3, count 0 2006.218.07:45:40.88#ibcon#*after write, iclass 3, count 0 2006.218.07:45:40.88#ibcon#*before return 0, iclass 3, count 0 2006.218.07:45:40.88#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.218.07:45:40.88#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.218.07:45:40.88#ibcon#about to clear, iclass 3 cls_cnt 0 2006.218.07:45:40.88#ibcon#cleared, iclass 3 cls_cnt 0 2006.218.07:45:40.88$vc4f8/vblo=2,640.99 2006.218.07:45:40.88#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.218.07:45:40.88#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.218.07:45:40.88#ibcon#ireg 17 cls_cnt 0 2006.218.07:45:40.88#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.218.07:45:40.88#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.218.07:45:40.88#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.218.07:45:40.88#ibcon#enter wrdev, iclass 5, count 0 2006.218.07:45:40.88#ibcon#first serial, iclass 5, count 0 2006.218.07:45:40.88#ibcon#enter sib2, iclass 5, count 0 2006.218.07:45:40.88#ibcon#flushed, iclass 5, count 0 2006.218.07:45:40.88#ibcon#about to write, iclass 5, count 0 2006.218.07:45:40.88#ibcon#wrote, iclass 5, count 0 2006.218.07:45:40.88#ibcon#about to read 3, iclass 5, count 0 2006.218.07:45:40.90#ibcon#read 3, iclass 5, count 0 2006.218.07:45:40.90#ibcon#about to read 4, iclass 5, count 0 2006.218.07:45:40.90#ibcon#read 4, iclass 5, count 0 2006.218.07:45:40.90#ibcon#about to read 5, iclass 5, count 0 2006.218.07:45:40.90#ibcon#read 5, iclass 5, count 0 2006.218.07:45:40.90#ibcon#about to read 6, iclass 5, count 0 2006.218.07:45:40.90#ibcon#read 6, iclass 5, count 0 2006.218.07:45:40.90#ibcon#end of sib2, iclass 5, count 0 2006.218.07:45:40.90#ibcon#*mode == 0, iclass 5, count 0 2006.218.07:45:40.90#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.218.07:45:40.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.218.07:45:40.90#ibcon#*before write, iclass 5, count 0 2006.218.07:45:40.90#ibcon#enter sib2, iclass 5, count 0 2006.218.07:45:40.90#ibcon#flushed, iclass 5, count 0 2006.218.07:45:40.90#ibcon#about to write, iclass 5, count 0 2006.218.07:45:40.90#ibcon#wrote, iclass 5, count 0 2006.218.07:45:40.90#ibcon#about to read 3, iclass 5, count 0 2006.218.07:45:40.94#ibcon#read 3, iclass 5, count 0 2006.218.07:45:40.94#ibcon#about to read 4, iclass 5, count 0 2006.218.07:45:40.94#ibcon#read 4, iclass 5, count 0 2006.218.07:45:40.94#ibcon#about to read 5, iclass 5, count 0 2006.218.07:45:40.94#ibcon#read 5, iclass 5, count 0 2006.218.07:45:40.94#ibcon#about to read 6, iclass 5, count 0 2006.218.07:45:40.94#ibcon#read 6, iclass 5, count 0 2006.218.07:45:40.94#ibcon#end of sib2, iclass 5, count 0 2006.218.07:45:40.94#ibcon#*after write, iclass 5, count 0 2006.218.07:45:40.94#ibcon#*before return 0, iclass 5, count 0 2006.218.07:45:40.94#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.218.07:45:40.94#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.218.07:45:40.94#ibcon#about to clear, iclass 5 cls_cnt 0 2006.218.07:45:40.94#ibcon#cleared, iclass 5 cls_cnt 0 2006.218.07:45:40.94$vc4f8/vb=2,4 2006.218.07:45:40.94#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.218.07:45:40.94#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.218.07:45:40.94#ibcon#ireg 11 cls_cnt 2 2006.218.07:45:40.94#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.218.07:45:41.00#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.218.07:45:41.00#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.218.07:45:41.00#ibcon#enter wrdev, iclass 7, count 2 2006.218.07:45:41.00#ibcon#first serial, iclass 7, count 2 2006.218.07:45:41.00#ibcon#enter sib2, iclass 7, count 2 2006.218.07:45:41.00#ibcon#flushed, iclass 7, count 2 2006.218.07:45:41.00#ibcon#about to write, iclass 7, count 2 2006.218.07:45:41.00#ibcon#wrote, iclass 7, count 2 2006.218.07:45:41.00#ibcon#about to read 3, iclass 7, count 2 2006.218.07:45:41.02#ibcon#read 3, iclass 7, count 2 2006.218.07:45:41.02#ibcon#about to read 4, iclass 7, count 2 2006.218.07:45:41.02#ibcon#read 4, iclass 7, count 2 2006.218.07:45:41.02#ibcon#about to read 5, iclass 7, count 2 2006.218.07:45:41.02#ibcon#read 5, iclass 7, count 2 2006.218.07:45:41.02#ibcon#about to read 6, iclass 7, count 2 2006.218.07:45:41.02#ibcon#read 6, iclass 7, count 2 2006.218.07:45:41.02#ibcon#end of sib2, iclass 7, count 2 2006.218.07:45:41.02#ibcon#*mode == 0, iclass 7, count 2 2006.218.07:45:41.02#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.218.07:45:41.02#ibcon#[27=AT02-04\r\n] 2006.218.07:45:41.02#ibcon#*before write, iclass 7, count 2 2006.218.07:45:41.02#ibcon#enter sib2, iclass 7, count 2 2006.218.07:45:41.02#ibcon#flushed, iclass 7, count 2 2006.218.07:45:41.02#ibcon#about to write, iclass 7, count 2 2006.218.07:45:41.02#ibcon#wrote, iclass 7, count 2 2006.218.07:45:41.02#ibcon#about to read 3, iclass 7, count 2 2006.218.07:45:41.05#ibcon#read 3, iclass 7, count 2 2006.218.07:45:41.05#ibcon#about to read 4, iclass 7, count 2 2006.218.07:45:41.05#ibcon#read 4, iclass 7, count 2 2006.218.07:45:41.05#ibcon#about to read 5, iclass 7, count 2 2006.218.07:45:41.05#ibcon#read 5, iclass 7, count 2 2006.218.07:45:41.05#ibcon#about to read 6, iclass 7, count 2 2006.218.07:45:41.05#ibcon#read 6, iclass 7, count 2 2006.218.07:45:41.05#ibcon#end of sib2, iclass 7, count 2 2006.218.07:45:41.05#ibcon#*after write, iclass 7, count 2 2006.218.07:45:41.05#ibcon#*before return 0, iclass 7, count 2 2006.218.07:45:41.05#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.218.07:45:41.05#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.218.07:45:41.05#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.218.07:45:41.05#ibcon#ireg 7 cls_cnt 0 2006.218.07:45:41.05#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.218.07:45:41.17#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.218.07:45:41.17#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.218.07:45:41.17#ibcon#enter wrdev, iclass 7, count 0 2006.218.07:45:41.17#ibcon#first serial, iclass 7, count 0 2006.218.07:45:41.17#ibcon#enter sib2, iclass 7, count 0 2006.218.07:45:41.17#ibcon#flushed, iclass 7, count 0 2006.218.07:45:41.17#ibcon#about to write, iclass 7, count 0 2006.218.07:45:41.17#ibcon#wrote, iclass 7, count 0 2006.218.07:45:41.17#ibcon#about to read 3, iclass 7, count 0 2006.218.07:45:41.20#ibcon#read 3, iclass 7, count 0 2006.218.07:45:41.20#ibcon#about to read 4, iclass 7, count 0 2006.218.07:45:41.20#ibcon#read 4, iclass 7, count 0 2006.218.07:45:41.20#ibcon#about to read 5, iclass 7, count 0 2006.218.07:45:41.20#ibcon#read 5, iclass 7, count 0 2006.218.07:45:41.20#ibcon#about to read 6, iclass 7, count 0 2006.218.07:45:41.20#ibcon#read 6, iclass 7, count 0 2006.218.07:45:41.20#ibcon#end of sib2, iclass 7, count 0 2006.218.07:45:41.20#ibcon#*mode == 0, iclass 7, count 0 2006.218.07:45:41.20#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.218.07:45:41.20#ibcon#[27=USB\r\n] 2006.218.07:45:41.20#ibcon#*before write, iclass 7, count 0 2006.218.07:45:41.20#ibcon#enter sib2, iclass 7, count 0 2006.218.07:45:41.20#ibcon#flushed, iclass 7, count 0 2006.218.07:45:41.20#ibcon#about to write, iclass 7, count 0 2006.218.07:45:41.20#ibcon#wrote, iclass 7, count 0 2006.218.07:45:41.20#ibcon#about to read 3, iclass 7, count 0 2006.218.07:45:41.23#ibcon#read 3, iclass 7, count 0 2006.218.07:45:41.23#ibcon#about to read 4, iclass 7, count 0 2006.218.07:45:41.23#ibcon#read 4, iclass 7, count 0 2006.218.07:45:41.23#ibcon#about to read 5, iclass 7, count 0 2006.218.07:45:41.23#ibcon#read 5, iclass 7, count 0 2006.218.07:45:41.23#ibcon#about to read 6, iclass 7, count 0 2006.218.07:45:41.23#ibcon#read 6, iclass 7, count 0 2006.218.07:45:41.23#ibcon#end of sib2, iclass 7, count 0 2006.218.07:45:41.23#ibcon#*after write, iclass 7, count 0 2006.218.07:45:41.23#ibcon#*before return 0, iclass 7, count 0 2006.218.07:45:41.23#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.218.07:45:41.23#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.218.07:45:41.23#ibcon#about to clear, iclass 7 cls_cnt 0 2006.218.07:45:41.23#ibcon#cleared, iclass 7 cls_cnt 0 2006.218.07:45:41.23$vc4f8/vblo=3,656.99 2006.218.07:45:41.23#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.218.07:45:41.23#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.218.07:45:41.23#ibcon#ireg 17 cls_cnt 0 2006.218.07:45:41.23#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.218.07:45:41.23#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.218.07:45:41.23#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.218.07:45:41.23#ibcon#enter wrdev, iclass 11, count 0 2006.218.07:45:41.23#ibcon#first serial, iclass 11, count 0 2006.218.07:45:41.23#ibcon#enter sib2, iclass 11, count 0 2006.218.07:45:41.23#ibcon#flushed, iclass 11, count 0 2006.218.07:45:41.23#ibcon#about to write, iclass 11, count 0 2006.218.07:45:41.23#ibcon#wrote, iclass 11, count 0 2006.218.07:45:41.23#ibcon#about to read 3, iclass 11, count 0 2006.218.07:45:41.25#ibcon#read 3, iclass 11, count 0 2006.218.07:45:41.25#ibcon#about to read 4, iclass 11, count 0 2006.218.07:45:41.25#ibcon#read 4, iclass 11, count 0 2006.218.07:45:41.25#ibcon#about to read 5, iclass 11, count 0 2006.218.07:45:41.25#ibcon#read 5, iclass 11, count 0 2006.218.07:45:41.25#ibcon#about to read 6, iclass 11, count 0 2006.218.07:45:41.25#ibcon#read 6, iclass 11, count 0 2006.218.07:45:41.25#ibcon#end of sib2, iclass 11, count 0 2006.218.07:45:41.25#ibcon#*mode == 0, iclass 11, count 0 2006.218.07:45:41.25#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.218.07:45:41.25#ibcon#[28=FRQ=03,656.99\r\n] 2006.218.07:45:41.25#ibcon#*before write, iclass 11, count 0 2006.218.07:45:41.25#ibcon#enter sib2, iclass 11, count 0 2006.218.07:45:41.25#ibcon#flushed, iclass 11, count 0 2006.218.07:45:41.25#ibcon#about to write, iclass 11, count 0 2006.218.07:45:41.25#ibcon#wrote, iclass 11, count 0 2006.218.07:45:41.25#ibcon#about to read 3, iclass 11, count 0 2006.218.07:45:41.29#ibcon#read 3, iclass 11, count 0 2006.218.07:45:41.29#ibcon#about to read 4, iclass 11, count 0 2006.218.07:45:41.29#ibcon#read 4, iclass 11, count 0 2006.218.07:45:41.29#ibcon#about to read 5, iclass 11, count 0 2006.218.07:45:41.29#ibcon#read 5, iclass 11, count 0 2006.218.07:45:41.29#ibcon#about to read 6, iclass 11, count 0 2006.218.07:45:41.29#ibcon#read 6, iclass 11, count 0 2006.218.07:45:41.29#ibcon#end of sib2, iclass 11, count 0 2006.218.07:45:41.29#ibcon#*after write, iclass 11, count 0 2006.218.07:45:41.29#ibcon#*before return 0, iclass 11, count 0 2006.218.07:45:41.29#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.218.07:45:41.29#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.218.07:45:41.29#ibcon#about to clear, iclass 11 cls_cnt 0 2006.218.07:45:41.29#ibcon#cleared, iclass 11 cls_cnt 0 2006.218.07:45:41.29$vc4f8/vb=3,4 2006.218.07:45:41.29#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.218.07:45:41.29#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.218.07:45:41.29#ibcon#ireg 11 cls_cnt 2 2006.218.07:45:41.29#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.218.07:45:41.35#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.218.07:45:41.35#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.218.07:45:41.35#ibcon#enter wrdev, iclass 13, count 2 2006.218.07:45:41.35#ibcon#first serial, iclass 13, count 2 2006.218.07:45:41.35#ibcon#enter sib2, iclass 13, count 2 2006.218.07:45:41.35#ibcon#flushed, iclass 13, count 2 2006.218.07:45:41.35#ibcon#about to write, iclass 13, count 2 2006.218.07:45:41.35#ibcon#wrote, iclass 13, count 2 2006.218.07:45:41.35#ibcon#about to read 3, iclass 13, count 2 2006.218.07:45:41.37#ibcon#read 3, iclass 13, count 2 2006.218.07:45:41.37#ibcon#about to read 4, iclass 13, count 2 2006.218.07:45:41.37#ibcon#read 4, iclass 13, count 2 2006.218.07:45:41.37#ibcon#about to read 5, iclass 13, count 2 2006.218.07:45:41.37#ibcon#read 5, iclass 13, count 2 2006.218.07:45:41.37#ibcon#about to read 6, iclass 13, count 2 2006.218.07:45:41.37#ibcon#read 6, iclass 13, count 2 2006.218.07:45:41.37#ibcon#end of sib2, iclass 13, count 2 2006.218.07:45:41.37#ibcon#*mode == 0, iclass 13, count 2 2006.218.07:45:41.37#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.218.07:45:41.37#ibcon#[27=AT03-04\r\n] 2006.218.07:45:41.37#ibcon#*before write, iclass 13, count 2 2006.218.07:45:41.37#ibcon#enter sib2, iclass 13, count 2 2006.218.07:45:41.37#ibcon#flushed, iclass 13, count 2 2006.218.07:45:41.37#ibcon#about to write, iclass 13, count 2 2006.218.07:45:41.37#ibcon#wrote, iclass 13, count 2 2006.218.07:45:41.37#ibcon#about to read 3, iclass 13, count 2 2006.218.07:45:41.40#ibcon#read 3, iclass 13, count 2 2006.218.07:45:41.40#ibcon#about to read 4, iclass 13, count 2 2006.218.07:45:41.40#ibcon#read 4, iclass 13, count 2 2006.218.07:45:41.40#ibcon#about to read 5, iclass 13, count 2 2006.218.07:45:41.40#ibcon#read 5, iclass 13, count 2 2006.218.07:45:41.40#ibcon#about to read 6, iclass 13, count 2 2006.218.07:45:41.40#ibcon#read 6, iclass 13, count 2 2006.218.07:45:41.40#ibcon#end of sib2, iclass 13, count 2 2006.218.07:45:41.40#ibcon#*after write, iclass 13, count 2 2006.218.07:45:41.40#ibcon#*before return 0, iclass 13, count 2 2006.218.07:45:41.40#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.218.07:45:41.40#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.218.07:45:41.40#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.218.07:45:41.40#ibcon#ireg 7 cls_cnt 0 2006.218.07:45:41.40#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.218.07:45:41.52#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.218.07:45:41.52#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.218.07:45:41.52#ibcon#enter wrdev, iclass 13, count 0 2006.218.07:45:41.52#ibcon#first serial, iclass 13, count 0 2006.218.07:45:41.52#ibcon#enter sib2, iclass 13, count 0 2006.218.07:45:41.52#ibcon#flushed, iclass 13, count 0 2006.218.07:45:41.52#ibcon#about to write, iclass 13, count 0 2006.218.07:45:41.52#ibcon#wrote, iclass 13, count 0 2006.218.07:45:41.52#ibcon#about to read 3, iclass 13, count 0 2006.218.07:45:41.54#ibcon#read 3, iclass 13, count 0 2006.218.07:45:41.54#ibcon#about to read 4, iclass 13, count 0 2006.218.07:45:41.54#ibcon#read 4, iclass 13, count 0 2006.218.07:45:41.54#ibcon#about to read 5, iclass 13, count 0 2006.218.07:45:41.54#ibcon#read 5, iclass 13, count 0 2006.218.07:45:41.54#ibcon#about to read 6, iclass 13, count 0 2006.218.07:45:41.54#ibcon#read 6, iclass 13, count 0 2006.218.07:45:41.54#ibcon#end of sib2, iclass 13, count 0 2006.218.07:45:41.54#ibcon#*mode == 0, iclass 13, count 0 2006.218.07:45:41.54#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.218.07:45:41.54#ibcon#[27=USB\r\n] 2006.218.07:45:41.54#ibcon#*before write, iclass 13, count 0 2006.218.07:45:41.54#ibcon#enter sib2, iclass 13, count 0 2006.218.07:45:41.54#ibcon#flushed, iclass 13, count 0 2006.218.07:45:41.54#ibcon#about to write, iclass 13, count 0 2006.218.07:45:41.54#ibcon#wrote, iclass 13, count 0 2006.218.07:45:41.54#ibcon#about to read 3, iclass 13, count 0 2006.218.07:45:41.57#ibcon#read 3, iclass 13, count 0 2006.218.07:45:41.57#ibcon#about to read 4, iclass 13, count 0 2006.218.07:45:41.57#ibcon#read 4, iclass 13, count 0 2006.218.07:45:41.57#ibcon#about to read 5, iclass 13, count 0 2006.218.07:45:41.57#ibcon#read 5, iclass 13, count 0 2006.218.07:45:41.57#ibcon#about to read 6, iclass 13, count 0 2006.218.07:45:41.57#ibcon#read 6, iclass 13, count 0 2006.218.07:45:41.57#ibcon#end of sib2, iclass 13, count 0 2006.218.07:45:41.57#ibcon#*after write, iclass 13, count 0 2006.218.07:45:41.57#ibcon#*before return 0, iclass 13, count 0 2006.218.07:45:41.57#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.218.07:45:41.57#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.218.07:45:41.57#ibcon#about to clear, iclass 13 cls_cnt 0 2006.218.07:45:41.57#ibcon#cleared, iclass 13 cls_cnt 0 2006.218.07:45:41.57$vc4f8/vblo=4,712.99 2006.218.07:45:41.57#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.218.07:45:41.57#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.218.07:45:41.57#ibcon#ireg 17 cls_cnt 0 2006.218.07:45:41.57#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.218.07:45:41.57#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.218.07:45:41.57#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.218.07:45:41.57#ibcon#enter wrdev, iclass 15, count 0 2006.218.07:45:41.57#ibcon#first serial, iclass 15, count 0 2006.218.07:45:41.57#ibcon#enter sib2, iclass 15, count 0 2006.218.07:45:41.57#ibcon#flushed, iclass 15, count 0 2006.218.07:45:41.57#ibcon#about to write, iclass 15, count 0 2006.218.07:45:41.57#ibcon#wrote, iclass 15, count 0 2006.218.07:45:41.57#ibcon#about to read 3, iclass 15, count 0 2006.218.07:45:41.59#ibcon#read 3, iclass 15, count 0 2006.218.07:45:41.59#ibcon#about to read 4, iclass 15, count 0 2006.218.07:45:41.59#ibcon#read 4, iclass 15, count 0 2006.218.07:45:41.59#ibcon#about to read 5, iclass 15, count 0 2006.218.07:45:41.59#ibcon#read 5, iclass 15, count 0 2006.218.07:45:41.59#ibcon#about to read 6, iclass 15, count 0 2006.218.07:45:41.59#ibcon#read 6, iclass 15, count 0 2006.218.07:45:41.59#ibcon#end of sib2, iclass 15, count 0 2006.218.07:45:41.59#ibcon#*mode == 0, iclass 15, count 0 2006.218.07:45:41.59#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.218.07:45:41.59#ibcon#[28=FRQ=04,712.99\r\n] 2006.218.07:45:41.59#ibcon#*before write, iclass 15, count 0 2006.218.07:45:41.59#ibcon#enter sib2, iclass 15, count 0 2006.218.07:45:41.59#ibcon#flushed, iclass 15, count 0 2006.218.07:45:41.59#ibcon#about to write, iclass 15, count 0 2006.218.07:45:41.59#ibcon#wrote, iclass 15, count 0 2006.218.07:45:41.59#ibcon#about to read 3, iclass 15, count 0 2006.218.07:45:41.63#ibcon#read 3, iclass 15, count 0 2006.218.07:45:41.63#ibcon#about to read 4, iclass 15, count 0 2006.218.07:45:41.63#ibcon#read 4, iclass 15, count 0 2006.218.07:45:41.63#ibcon#about to read 5, iclass 15, count 0 2006.218.07:45:41.63#ibcon#read 5, iclass 15, count 0 2006.218.07:45:41.63#ibcon#about to read 6, iclass 15, count 0 2006.218.07:45:41.63#ibcon#read 6, iclass 15, count 0 2006.218.07:45:41.63#ibcon#end of sib2, iclass 15, count 0 2006.218.07:45:41.63#ibcon#*after write, iclass 15, count 0 2006.218.07:45:41.63#ibcon#*before return 0, iclass 15, count 0 2006.218.07:45:41.63#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.218.07:45:41.63#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.218.07:45:41.63#ibcon#about to clear, iclass 15 cls_cnt 0 2006.218.07:45:41.63#ibcon#cleared, iclass 15 cls_cnt 0 2006.218.07:45:41.63$vc4f8/vb=4,4 2006.218.07:45:41.63#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.218.07:45:41.63#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.218.07:45:41.63#ibcon#ireg 11 cls_cnt 2 2006.218.07:45:41.63#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.218.07:45:41.69#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.218.07:45:41.69#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.218.07:45:41.69#ibcon#enter wrdev, iclass 17, count 2 2006.218.07:45:41.69#ibcon#first serial, iclass 17, count 2 2006.218.07:45:41.69#ibcon#enter sib2, iclass 17, count 2 2006.218.07:45:41.69#ibcon#flushed, iclass 17, count 2 2006.218.07:45:41.69#ibcon#about to write, iclass 17, count 2 2006.218.07:45:41.69#ibcon#wrote, iclass 17, count 2 2006.218.07:45:41.69#ibcon#about to read 3, iclass 17, count 2 2006.218.07:45:41.71#ibcon#read 3, iclass 17, count 2 2006.218.07:45:41.71#ibcon#about to read 4, iclass 17, count 2 2006.218.07:45:41.71#ibcon#read 4, iclass 17, count 2 2006.218.07:45:41.71#ibcon#about to read 5, iclass 17, count 2 2006.218.07:45:41.71#ibcon#read 5, iclass 17, count 2 2006.218.07:45:41.71#ibcon#about to read 6, iclass 17, count 2 2006.218.07:45:41.71#ibcon#read 6, iclass 17, count 2 2006.218.07:45:41.71#ibcon#end of sib2, iclass 17, count 2 2006.218.07:45:41.71#ibcon#*mode == 0, iclass 17, count 2 2006.218.07:45:41.71#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.218.07:45:41.71#ibcon#[27=AT04-04\r\n] 2006.218.07:45:41.71#ibcon#*before write, iclass 17, count 2 2006.218.07:45:41.71#ibcon#enter sib2, iclass 17, count 2 2006.218.07:45:41.71#ibcon#flushed, iclass 17, count 2 2006.218.07:45:41.71#ibcon#about to write, iclass 17, count 2 2006.218.07:45:41.71#ibcon#wrote, iclass 17, count 2 2006.218.07:45:41.71#ibcon#about to read 3, iclass 17, count 2 2006.218.07:45:41.74#ibcon#read 3, iclass 17, count 2 2006.218.07:45:41.74#ibcon#about to read 4, iclass 17, count 2 2006.218.07:45:41.74#ibcon#read 4, iclass 17, count 2 2006.218.07:45:41.74#ibcon#about to read 5, iclass 17, count 2 2006.218.07:45:41.74#ibcon#read 5, iclass 17, count 2 2006.218.07:45:41.74#ibcon#about to read 6, iclass 17, count 2 2006.218.07:45:41.74#ibcon#read 6, iclass 17, count 2 2006.218.07:45:41.74#ibcon#end of sib2, iclass 17, count 2 2006.218.07:45:41.74#ibcon#*after write, iclass 17, count 2 2006.218.07:45:41.74#ibcon#*before return 0, iclass 17, count 2 2006.218.07:45:41.74#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.218.07:45:41.74#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.218.07:45:41.74#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.218.07:45:41.74#ibcon#ireg 7 cls_cnt 0 2006.218.07:45:41.74#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.218.07:45:41.86#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.218.07:45:41.86#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.218.07:45:41.86#ibcon#enter wrdev, iclass 17, count 0 2006.218.07:45:41.86#ibcon#first serial, iclass 17, count 0 2006.218.07:45:41.86#ibcon#enter sib2, iclass 17, count 0 2006.218.07:45:41.86#ibcon#flushed, iclass 17, count 0 2006.218.07:45:41.86#ibcon#about to write, iclass 17, count 0 2006.218.07:45:41.86#ibcon#wrote, iclass 17, count 0 2006.218.07:45:41.86#ibcon#about to read 3, iclass 17, count 0 2006.218.07:45:41.88#ibcon#read 3, iclass 17, count 0 2006.218.07:45:41.88#ibcon#about to read 4, iclass 17, count 0 2006.218.07:45:41.88#ibcon#read 4, iclass 17, count 0 2006.218.07:45:41.88#ibcon#about to read 5, iclass 17, count 0 2006.218.07:45:41.88#ibcon#read 5, iclass 17, count 0 2006.218.07:45:41.88#ibcon#about to read 6, iclass 17, count 0 2006.218.07:45:41.88#ibcon#read 6, iclass 17, count 0 2006.218.07:45:41.88#ibcon#end of sib2, iclass 17, count 0 2006.218.07:45:41.88#ibcon#*mode == 0, iclass 17, count 0 2006.218.07:45:41.88#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.218.07:45:41.88#ibcon#[27=USB\r\n] 2006.218.07:45:41.88#ibcon#*before write, iclass 17, count 0 2006.218.07:45:41.88#ibcon#enter sib2, iclass 17, count 0 2006.218.07:45:41.88#ibcon#flushed, iclass 17, count 0 2006.218.07:45:41.88#ibcon#about to write, iclass 17, count 0 2006.218.07:45:41.88#ibcon#wrote, iclass 17, count 0 2006.218.07:45:41.88#ibcon#about to read 3, iclass 17, count 0 2006.218.07:45:41.91#ibcon#read 3, iclass 17, count 0 2006.218.07:45:41.91#ibcon#about to read 4, iclass 17, count 0 2006.218.07:45:41.91#ibcon#read 4, iclass 17, count 0 2006.218.07:45:41.91#ibcon#about to read 5, iclass 17, count 0 2006.218.07:45:41.91#ibcon#read 5, iclass 17, count 0 2006.218.07:45:41.91#ibcon#about to read 6, iclass 17, count 0 2006.218.07:45:41.91#ibcon#read 6, iclass 17, count 0 2006.218.07:45:41.91#ibcon#end of sib2, iclass 17, count 0 2006.218.07:45:41.91#ibcon#*after write, iclass 17, count 0 2006.218.07:45:41.91#ibcon#*before return 0, iclass 17, count 0 2006.218.07:45:41.91#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.218.07:45:41.91#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.218.07:45:41.91#ibcon#about to clear, iclass 17 cls_cnt 0 2006.218.07:45:41.91#ibcon#cleared, iclass 17 cls_cnt 0 2006.218.07:45:41.91$vc4f8/vblo=5,744.99 2006.218.07:45:41.91#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.218.07:45:41.91#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.218.07:45:41.91#ibcon#ireg 17 cls_cnt 0 2006.218.07:45:41.91#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.218.07:45:41.91#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.218.07:45:41.91#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.218.07:45:41.91#ibcon#enter wrdev, iclass 19, count 0 2006.218.07:45:41.91#ibcon#first serial, iclass 19, count 0 2006.218.07:45:41.91#ibcon#enter sib2, iclass 19, count 0 2006.218.07:45:41.91#ibcon#flushed, iclass 19, count 0 2006.218.07:45:41.91#ibcon#about to write, iclass 19, count 0 2006.218.07:45:41.91#ibcon#wrote, iclass 19, count 0 2006.218.07:45:41.91#ibcon#about to read 3, iclass 19, count 0 2006.218.07:45:41.93#ibcon#read 3, iclass 19, count 0 2006.218.07:45:41.93#ibcon#about to read 4, iclass 19, count 0 2006.218.07:45:41.93#ibcon#read 4, iclass 19, count 0 2006.218.07:45:41.93#ibcon#about to read 5, iclass 19, count 0 2006.218.07:45:41.93#ibcon#read 5, iclass 19, count 0 2006.218.07:45:41.93#ibcon#about to read 6, iclass 19, count 0 2006.218.07:45:41.93#ibcon#read 6, iclass 19, count 0 2006.218.07:45:41.93#ibcon#end of sib2, iclass 19, count 0 2006.218.07:45:41.93#ibcon#*mode == 0, iclass 19, count 0 2006.218.07:45:41.93#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.218.07:45:41.93#ibcon#[28=FRQ=05,744.99\r\n] 2006.218.07:45:41.93#ibcon#*before write, iclass 19, count 0 2006.218.07:45:41.93#ibcon#enter sib2, iclass 19, count 0 2006.218.07:45:41.93#ibcon#flushed, iclass 19, count 0 2006.218.07:45:41.93#ibcon#about to write, iclass 19, count 0 2006.218.07:45:41.93#ibcon#wrote, iclass 19, count 0 2006.218.07:45:41.93#ibcon#about to read 3, iclass 19, count 0 2006.218.07:45:41.97#ibcon#read 3, iclass 19, count 0 2006.218.07:45:41.97#ibcon#about to read 4, iclass 19, count 0 2006.218.07:45:41.97#ibcon#read 4, iclass 19, count 0 2006.218.07:45:41.97#ibcon#about to read 5, iclass 19, count 0 2006.218.07:45:41.97#ibcon#read 5, iclass 19, count 0 2006.218.07:45:41.97#ibcon#about to read 6, iclass 19, count 0 2006.218.07:45:41.97#ibcon#read 6, iclass 19, count 0 2006.218.07:45:41.97#ibcon#end of sib2, iclass 19, count 0 2006.218.07:45:41.97#ibcon#*after write, iclass 19, count 0 2006.218.07:45:41.97#ibcon#*before return 0, iclass 19, count 0 2006.218.07:45:41.97#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.218.07:45:41.97#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.218.07:45:41.97#ibcon#about to clear, iclass 19 cls_cnt 0 2006.218.07:45:41.97#ibcon#cleared, iclass 19 cls_cnt 0 2006.218.07:45:41.97$vc4f8/vb=5,4 2006.218.07:45:41.97#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.218.07:45:41.97#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.218.07:45:41.97#ibcon#ireg 11 cls_cnt 2 2006.218.07:45:41.97#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.218.07:45:42.03#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.218.07:45:42.03#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.218.07:45:42.03#ibcon#enter wrdev, iclass 21, count 2 2006.218.07:45:42.03#ibcon#first serial, iclass 21, count 2 2006.218.07:45:42.03#ibcon#enter sib2, iclass 21, count 2 2006.218.07:45:42.03#ibcon#flushed, iclass 21, count 2 2006.218.07:45:42.03#ibcon#about to write, iclass 21, count 2 2006.218.07:45:42.03#ibcon#wrote, iclass 21, count 2 2006.218.07:45:42.03#ibcon#about to read 3, iclass 21, count 2 2006.218.07:45:42.05#ibcon#read 3, iclass 21, count 2 2006.218.07:45:42.05#ibcon#about to read 4, iclass 21, count 2 2006.218.07:45:42.05#ibcon#read 4, iclass 21, count 2 2006.218.07:45:42.05#ibcon#about to read 5, iclass 21, count 2 2006.218.07:45:42.05#ibcon#read 5, iclass 21, count 2 2006.218.07:45:42.05#ibcon#about to read 6, iclass 21, count 2 2006.218.07:45:42.05#ibcon#read 6, iclass 21, count 2 2006.218.07:45:42.05#ibcon#end of sib2, iclass 21, count 2 2006.218.07:45:42.05#ibcon#*mode == 0, iclass 21, count 2 2006.218.07:45:42.05#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.218.07:45:42.05#ibcon#[27=AT05-04\r\n] 2006.218.07:45:42.05#ibcon#*before write, iclass 21, count 2 2006.218.07:45:42.05#ibcon#enter sib2, iclass 21, count 2 2006.218.07:45:42.05#ibcon#flushed, iclass 21, count 2 2006.218.07:45:42.05#ibcon#about to write, iclass 21, count 2 2006.218.07:45:42.05#ibcon#wrote, iclass 21, count 2 2006.218.07:45:42.05#ibcon#about to read 3, iclass 21, count 2 2006.218.07:45:42.08#ibcon#read 3, iclass 21, count 2 2006.218.07:45:42.08#ibcon#about to read 4, iclass 21, count 2 2006.218.07:45:42.08#ibcon#read 4, iclass 21, count 2 2006.218.07:45:42.08#ibcon#about to read 5, iclass 21, count 2 2006.218.07:45:42.08#ibcon#read 5, iclass 21, count 2 2006.218.07:45:42.08#ibcon#about to read 6, iclass 21, count 2 2006.218.07:45:42.08#ibcon#read 6, iclass 21, count 2 2006.218.07:45:42.08#ibcon#end of sib2, iclass 21, count 2 2006.218.07:45:42.08#ibcon#*after write, iclass 21, count 2 2006.218.07:45:42.08#ibcon#*before return 0, iclass 21, count 2 2006.218.07:45:42.08#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.218.07:45:42.08#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.218.07:45:42.08#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.218.07:45:42.08#ibcon#ireg 7 cls_cnt 0 2006.218.07:45:42.08#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.218.07:45:42.20#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.218.07:45:42.20#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.218.07:45:42.20#ibcon#enter wrdev, iclass 21, count 0 2006.218.07:45:42.20#ibcon#first serial, iclass 21, count 0 2006.218.07:45:42.20#ibcon#enter sib2, iclass 21, count 0 2006.218.07:45:42.20#ibcon#flushed, iclass 21, count 0 2006.218.07:45:42.20#ibcon#about to write, iclass 21, count 0 2006.218.07:45:42.20#ibcon#wrote, iclass 21, count 0 2006.218.07:45:42.20#ibcon#about to read 3, iclass 21, count 0 2006.218.07:45:42.22#ibcon#read 3, iclass 21, count 0 2006.218.07:45:42.22#ibcon#about to read 4, iclass 21, count 0 2006.218.07:45:42.22#ibcon#read 4, iclass 21, count 0 2006.218.07:45:42.22#ibcon#about to read 5, iclass 21, count 0 2006.218.07:45:42.22#ibcon#read 5, iclass 21, count 0 2006.218.07:45:42.22#ibcon#about to read 6, iclass 21, count 0 2006.218.07:45:42.22#ibcon#read 6, iclass 21, count 0 2006.218.07:45:42.22#ibcon#end of sib2, iclass 21, count 0 2006.218.07:45:42.22#ibcon#*mode == 0, iclass 21, count 0 2006.218.07:45:42.22#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.218.07:45:42.22#ibcon#[27=USB\r\n] 2006.218.07:45:42.22#ibcon#*before write, iclass 21, count 0 2006.218.07:45:42.22#ibcon#enter sib2, iclass 21, count 0 2006.218.07:45:42.22#ibcon#flushed, iclass 21, count 0 2006.218.07:45:42.22#ibcon#about to write, iclass 21, count 0 2006.218.07:45:42.22#ibcon#wrote, iclass 21, count 0 2006.218.07:45:42.22#ibcon#about to read 3, iclass 21, count 0 2006.218.07:45:42.25#ibcon#read 3, iclass 21, count 0 2006.218.07:45:42.25#ibcon#about to read 4, iclass 21, count 0 2006.218.07:45:42.25#ibcon#read 4, iclass 21, count 0 2006.218.07:45:42.25#ibcon#about to read 5, iclass 21, count 0 2006.218.07:45:42.25#ibcon#read 5, iclass 21, count 0 2006.218.07:45:42.25#ibcon#about to read 6, iclass 21, count 0 2006.218.07:45:42.25#ibcon#read 6, iclass 21, count 0 2006.218.07:45:42.25#ibcon#end of sib2, iclass 21, count 0 2006.218.07:45:42.25#ibcon#*after write, iclass 21, count 0 2006.218.07:45:42.25#ibcon#*before return 0, iclass 21, count 0 2006.218.07:45:42.25#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.218.07:45:42.25#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.218.07:45:42.25#ibcon#about to clear, iclass 21 cls_cnt 0 2006.218.07:45:42.25#ibcon#cleared, iclass 21 cls_cnt 0 2006.218.07:45:42.25$vc4f8/vblo=6,752.99 2006.218.07:45:42.25#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.218.07:45:42.25#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.218.07:45:42.25#ibcon#ireg 17 cls_cnt 0 2006.218.07:45:42.25#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.218.07:45:42.25#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.218.07:45:42.25#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.218.07:45:42.25#ibcon#enter wrdev, iclass 23, count 0 2006.218.07:45:42.25#ibcon#first serial, iclass 23, count 0 2006.218.07:45:42.25#ibcon#enter sib2, iclass 23, count 0 2006.218.07:45:42.25#ibcon#flushed, iclass 23, count 0 2006.218.07:45:42.25#ibcon#about to write, iclass 23, count 0 2006.218.07:45:42.25#ibcon#wrote, iclass 23, count 0 2006.218.07:45:42.25#ibcon#about to read 3, iclass 23, count 0 2006.218.07:45:42.27#ibcon#read 3, iclass 23, count 0 2006.218.07:45:42.27#ibcon#about to read 4, iclass 23, count 0 2006.218.07:45:42.27#ibcon#read 4, iclass 23, count 0 2006.218.07:45:42.27#ibcon#about to read 5, iclass 23, count 0 2006.218.07:45:42.27#ibcon#read 5, iclass 23, count 0 2006.218.07:45:42.27#ibcon#about to read 6, iclass 23, count 0 2006.218.07:45:42.27#ibcon#read 6, iclass 23, count 0 2006.218.07:45:42.27#ibcon#end of sib2, iclass 23, count 0 2006.218.07:45:42.27#ibcon#*mode == 0, iclass 23, count 0 2006.218.07:45:42.27#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.218.07:45:42.27#ibcon#[28=FRQ=06,752.99\r\n] 2006.218.07:45:42.27#ibcon#*before write, iclass 23, count 0 2006.218.07:45:42.27#ibcon#enter sib2, iclass 23, count 0 2006.218.07:45:42.27#ibcon#flushed, iclass 23, count 0 2006.218.07:45:42.27#ibcon#about to write, iclass 23, count 0 2006.218.07:45:42.27#ibcon#wrote, iclass 23, count 0 2006.218.07:45:42.27#ibcon#about to read 3, iclass 23, count 0 2006.218.07:45:42.31#ibcon#read 3, iclass 23, count 0 2006.218.07:45:42.31#ibcon#about to read 4, iclass 23, count 0 2006.218.07:45:42.31#ibcon#read 4, iclass 23, count 0 2006.218.07:45:42.31#ibcon#about to read 5, iclass 23, count 0 2006.218.07:45:42.31#ibcon#read 5, iclass 23, count 0 2006.218.07:45:42.31#ibcon#about to read 6, iclass 23, count 0 2006.218.07:45:42.31#ibcon#read 6, iclass 23, count 0 2006.218.07:45:42.31#ibcon#end of sib2, iclass 23, count 0 2006.218.07:45:42.31#ibcon#*after write, iclass 23, count 0 2006.218.07:45:42.31#ibcon#*before return 0, iclass 23, count 0 2006.218.07:45:42.31#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.218.07:45:42.31#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.218.07:45:42.31#ibcon#about to clear, iclass 23 cls_cnt 0 2006.218.07:45:42.31#ibcon#cleared, iclass 23 cls_cnt 0 2006.218.07:45:42.31$vc4f8/vb=6,4 2006.218.07:45:42.31#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.218.07:45:42.31#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.218.07:45:42.31#ibcon#ireg 11 cls_cnt 2 2006.218.07:45:42.31#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.218.07:45:42.37#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.218.07:45:42.37#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.218.07:45:42.37#ibcon#enter wrdev, iclass 25, count 2 2006.218.07:45:42.37#ibcon#first serial, iclass 25, count 2 2006.218.07:45:42.37#ibcon#enter sib2, iclass 25, count 2 2006.218.07:45:42.37#ibcon#flushed, iclass 25, count 2 2006.218.07:45:42.37#ibcon#about to write, iclass 25, count 2 2006.218.07:45:42.37#ibcon#wrote, iclass 25, count 2 2006.218.07:45:42.37#ibcon#about to read 3, iclass 25, count 2 2006.218.07:45:42.39#ibcon#read 3, iclass 25, count 2 2006.218.07:45:42.39#ibcon#about to read 4, iclass 25, count 2 2006.218.07:45:42.39#ibcon#read 4, iclass 25, count 2 2006.218.07:45:42.39#ibcon#about to read 5, iclass 25, count 2 2006.218.07:45:42.39#ibcon#read 5, iclass 25, count 2 2006.218.07:45:42.39#ibcon#about to read 6, iclass 25, count 2 2006.218.07:45:42.39#ibcon#read 6, iclass 25, count 2 2006.218.07:45:42.39#ibcon#end of sib2, iclass 25, count 2 2006.218.07:45:42.39#ibcon#*mode == 0, iclass 25, count 2 2006.218.07:45:42.39#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.218.07:45:42.39#ibcon#[27=AT06-04\r\n] 2006.218.07:45:42.39#ibcon#*before write, iclass 25, count 2 2006.218.07:45:42.39#ibcon#enter sib2, iclass 25, count 2 2006.218.07:45:42.39#ibcon#flushed, iclass 25, count 2 2006.218.07:45:42.39#ibcon#about to write, iclass 25, count 2 2006.218.07:45:42.39#ibcon#wrote, iclass 25, count 2 2006.218.07:45:42.39#ibcon#about to read 3, iclass 25, count 2 2006.218.07:45:42.42#ibcon#read 3, iclass 25, count 2 2006.218.07:45:42.42#ibcon#about to read 4, iclass 25, count 2 2006.218.07:45:42.42#ibcon#read 4, iclass 25, count 2 2006.218.07:45:42.42#ibcon#about to read 5, iclass 25, count 2 2006.218.07:45:42.42#ibcon#read 5, iclass 25, count 2 2006.218.07:45:42.42#ibcon#about to read 6, iclass 25, count 2 2006.218.07:45:42.42#ibcon#read 6, iclass 25, count 2 2006.218.07:45:42.42#ibcon#end of sib2, iclass 25, count 2 2006.218.07:45:42.42#ibcon#*after write, iclass 25, count 2 2006.218.07:45:42.42#ibcon#*before return 0, iclass 25, count 2 2006.218.07:45:42.42#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.218.07:45:42.42#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.218.07:45:42.42#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.218.07:45:42.42#ibcon#ireg 7 cls_cnt 0 2006.218.07:45:42.42#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.218.07:45:42.54#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.218.07:45:42.54#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.218.07:45:42.54#ibcon#enter wrdev, iclass 25, count 0 2006.218.07:45:42.54#ibcon#first serial, iclass 25, count 0 2006.218.07:45:42.54#ibcon#enter sib2, iclass 25, count 0 2006.218.07:45:42.54#ibcon#flushed, iclass 25, count 0 2006.218.07:45:42.54#ibcon#about to write, iclass 25, count 0 2006.218.07:45:42.54#ibcon#wrote, iclass 25, count 0 2006.218.07:45:42.54#ibcon#about to read 3, iclass 25, count 0 2006.218.07:45:42.56#ibcon#read 3, iclass 25, count 0 2006.218.07:45:42.56#ibcon#about to read 4, iclass 25, count 0 2006.218.07:45:42.56#ibcon#read 4, iclass 25, count 0 2006.218.07:45:42.56#ibcon#about to read 5, iclass 25, count 0 2006.218.07:45:42.56#ibcon#read 5, iclass 25, count 0 2006.218.07:45:42.56#ibcon#about to read 6, iclass 25, count 0 2006.218.07:45:42.56#ibcon#read 6, iclass 25, count 0 2006.218.07:45:42.56#ibcon#end of sib2, iclass 25, count 0 2006.218.07:45:42.56#ibcon#*mode == 0, iclass 25, count 0 2006.218.07:45:42.56#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.218.07:45:42.56#ibcon#[27=USB\r\n] 2006.218.07:45:42.56#ibcon#*before write, iclass 25, count 0 2006.218.07:45:42.56#ibcon#enter sib2, iclass 25, count 0 2006.218.07:45:42.56#ibcon#flushed, iclass 25, count 0 2006.218.07:45:42.56#ibcon#about to write, iclass 25, count 0 2006.218.07:45:42.56#ibcon#wrote, iclass 25, count 0 2006.218.07:45:42.56#ibcon#about to read 3, iclass 25, count 0 2006.218.07:45:42.59#ibcon#read 3, iclass 25, count 0 2006.218.07:45:42.59#ibcon#about to read 4, iclass 25, count 0 2006.218.07:45:42.59#ibcon#read 4, iclass 25, count 0 2006.218.07:45:42.59#ibcon#about to read 5, iclass 25, count 0 2006.218.07:45:42.59#ibcon#read 5, iclass 25, count 0 2006.218.07:45:42.59#ibcon#about to read 6, iclass 25, count 0 2006.218.07:45:42.59#ibcon#read 6, iclass 25, count 0 2006.218.07:45:42.59#ibcon#end of sib2, iclass 25, count 0 2006.218.07:45:42.59#ibcon#*after write, iclass 25, count 0 2006.218.07:45:42.59#ibcon#*before return 0, iclass 25, count 0 2006.218.07:45:42.59#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.218.07:45:42.59#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.218.07:45:42.59#ibcon#about to clear, iclass 25 cls_cnt 0 2006.218.07:45:42.59#ibcon#cleared, iclass 25 cls_cnt 0 2006.218.07:45:42.59$vc4f8/vabw=wide 2006.218.07:45:42.59#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.218.07:45:42.59#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.218.07:45:42.59#ibcon#ireg 8 cls_cnt 0 2006.218.07:45:42.59#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.218.07:45:42.59#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.218.07:45:42.59#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.218.07:45:42.59#ibcon#enter wrdev, iclass 27, count 0 2006.218.07:45:42.59#ibcon#first serial, iclass 27, count 0 2006.218.07:45:42.59#ibcon#enter sib2, iclass 27, count 0 2006.218.07:45:42.59#ibcon#flushed, iclass 27, count 0 2006.218.07:45:42.59#ibcon#about to write, iclass 27, count 0 2006.218.07:45:42.59#ibcon#wrote, iclass 27, count 0 2006.218.07:45:42.59#ibcon#about to read 3, iclass 27, count 0 2006.218.07:45:42.61#ibcon#read 3, iclass 27, count 0 2006.218.07:45:42.61#ibcon#about to read 4, iclass 27, count 0 2006.218.07:45:42.61#ibcon#read 4, iclass 27, count 0 2006.218.07:45:42.61#ibcon#about to read 5, iclass 27, count 0 2006.218.07:45:42.61#ibcon#read 5, iclass 27, count 0 2006.218.07:45:42.61#ibcon#about to read 6, iclass 27, count 0 2006.218.07:45:42.61#ibcon#read 6, iclass 27, count 0 2006.218.07:45:42.61#ibcon#end of sib2, iclass 27, count 0 2006.218.07:45:42.61#ibcon#*mode == 0, iclass 27, count 0 2006.218.07:45:42.61#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.218.07:45:42.61#ibcon#[25=BW32\r\n] 2006.218.07:45:42.61#ibcon#*before write, iclass 27, count 0 2006.218.07:45:42.61#ibcon#enter sib2, iclass 27, count 0 2006.218.07:45:42.61#ibcon#flushed, iclass 27, count 0 2006.218.07:45:42.61#ibcon#about to write, iclass 27, count 0 2006.218.07:45:42.61#ibcon#wrote, iclass 27, count 0 2006.218.07:45:42.61#ibcon#about to read 3, iclass 27, count 0 2006.218.07:45:42.64#ibcon#read 3, iclass 27, count 0 2006.218.07:45:42.64#ibcon#about to read 4, iclass 27, count 0 2006.218.07:45:42.64#ibcon#read 4, iclass 27, count 0 2006.218.07:45:42.64#ibcon#about to read 5, iclass 27, count 0 2006.218.07:45:42.64#ibcon#read 5, iclass 27, count 0 2006.218.07:45:42.64#ibcon#about to read 6, iclass 27, count 0 2006.218.07:45:42.64#ibcon#read 6, iclass 27, count 0 2006.218.07:45:42.64#ibcon#end of sib2, iclass 27, count 0 2006.218.07:45:42.64#ibcon#*after write, iclass 27, count 0 2006.218.07:45:42.64#ibcon#*before return 0, iclass 27, count 0 2006.218.07:45:42.64#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.218.07:45:42.64#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.218.07:45:42.64#ibcon#about to clear, iclass 27 cls_cnt 0 2006.218.07:45:42.64#ibcon#cleared, iclass 27 cls_cnt 0 2006.218.07:45:42.64$vc4f8/vbbw=wide 2006.218.07:45:42.64#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.218.07:45:42.64#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.218.07:45:42.64#ibcon#ireg 8 cls_cnt 0 2006.218.07:45:42.64#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.218.07:45:42.71#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.218.07:45:42.71#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.218.07:45:42.71#ibcon#enter wrdev, iclass 29, count 0 2006.218.07:45:42.71#ibcon#first serial, iclass 29, count 0 2006.218.07:45:42.71#ibcon#enter sib2, iclass 29, count 0 2006.218.07:45:42.71#ibcon#flushed, iclass 29, count 0 2006.218.07:45:42.71#ibcon#about to write, iclass 29, count 0 2006.218.07:45:42.71#ibcon#wrote, iclass 29, count 0 2006.218.07:45:42.71#ibcon#about to read 3, iclass 29, count 0 2006.218.07:45:42.73#ibcon#read 3, iclass 29, count 0 2006.218.07:45:42.73#ibcon#about to read 4, iclass 29, count 0 2006.218.07:45:42.73#ibcon#read 4, iclass 29, count 0 2006.218.07:45:42.73#ibcon#about to read 5, iclass 29, count 0 2006.218.07:45:42.73#ibcon#read 5, iclass 29, count 0 2006.218.07:45:42.73#ibcon#about to read 6, iclass 29, count 0 2006.218.07:45:42.73#ibcon#read 6, iclass 29, count 0 2006.218.07:45:42.73#ibcon#end of sib2, iclass 29, count 0 2006.218.07:45:42.73#ibcon#*mode == 0, iclass 29, count 0 2006.218.07:45:42.73#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.218.07:45:42.73#ibcon#[27=BW32\r\n] 2006.218.07:45:42.73#ibcon#*before write, iclass 29, count 0 2006.218.07:45:42.73#ibcon#enter sib2, iclass 29, count 0 2006.218.07:45:42.73#ibcon#flushed, iclass 29, count 0 2006.218.07:45:42.73#ibcon#about to write, iclass 29, count 0 2006.218.07:45:42.73#ibcon#wrote, iclass 29, count 0 2006.218.07:45:42.73#ibcon#about to read 3, iclass 29, count 0 2006.218.07:45:42.76#ibcon#read 3, iclass 29, count 0 2006.218.07:45:42.76#ibcon#about to read 4, iclass 29, count 0 2006.218.07:45:42.76#ibcon#read 4, iclass 29, count 0 2006.218.07:45:42.76#ibcon#about to read 5, iclass 29, count 0 2006.218.07:45:42.76#ibcon#read 5, iclass 29, count 0 2006.218.07:45:42.76#ibcon#about to read 6, iclass 29, count 0 2006.218.07:45:42.76#ibcon#read 6, iclass 29, count 0 2006.218.07:45:42.76#ibcon#end of sib2, iclass 29, count 0 2006.218.07:45:42.76#ibcon#*after write, iclass 29, count 0 2006.218.07:45:42.76#ibcon#*before return 0, iclass 29, count 0 2006.218.07:45:42.76#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.218.07:45:42.76#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.218.07:45:42.76#ibcon#about to clear, iclass 29 cls_cnt 0 2006.218.07:45:42.76#ibcon#cleared, iclass 29 cls_cnt 0 2006.218.07:45:42.76$4f8m12a/ifd4f 2006.218.07:45:42.76$ifd4f/lo= 2006.218.07:45:42.76$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.218.07:45:42.76$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.218.07:45:42.76$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.218.07:45:42.76$ifd4f/patch= 2006.218.07:45:42.76$ifd4f/patch=lo1,a1,a2,a3,a4 2006.218.07:45:42.76$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.218.07:45:42.76$ifd4f/patch=lo3,a5,a6,a7,a8 2006.218.07:45:42.76$4f8m12a/"form=m,16.000,1:2 2006.218.07:45:42.76$4f8m12a/"tpicd 2006.218.07:45:42.76$4f8m12a/echo=off 2006.218.07:45:42.76$4f8m12a/xlog=off 2006.218.07:45:42.76:!2006.218.07:46:40 2006.218.07:46:19.13#trakl#Source acquired 2006.218.07:46:19.13#flagr#flagr/antenna,acquired 2006.218.07:46:40.00:preob 2006.218.07:46:41.13/onsource/TRACKING 2006.218.07:46:41.13:!2006.218.07:46:50 2006.218.07:46:50.00:data_valid=on 2006.218.07:46:50.00:midob 2006.218.07:46:50.14/onsource/TRACKING 2006.218.07:46:50.14/wx/31.25,1007.4,73 2006.218.07:46:50.26/cable/+6.3850E-03 2006.218.07:46:51.35/va/01,05,usb,yes,32,34 2006.218.07:46:51.35/va/02,04,usb,yes,30,32 2006.218.07:46:51.35/va/03,04,usb,yes,28,29 2006.218.07:46:51.35/va/04,04,usb,yes,32,34 2006.218.07:46:51.35/va/05,07,usb,yes,33,35 2006.218.07:46:51.35/va/06,06,usb,yes,32,32 2006.218.07:46:51.35/va/07,06,usb,yes,33,33 2006.218.07:46:51.35/va/08,07,usb,yes,31,31 2006.218.07:46:51.58/valo/01,532.99,yes,locked 2006.218.07:46:51.58/valo/02,572.99,yes,locked 2006.218.07:46:51.58/valo/03,672.99,yes,locked 2006.218.07:46:51.58/valo/04,832.99,yes,locked 2006.218.07:46:51.58/valo/05,652.99,yes,locked 2006.218.07:46:51.58/valo/06,772.99,yes,locked 2006.218.07:46:51.58/valo/07,832.99,yes,locked 2006.218.07:46:51.58/valo/08,852.99,yes,locked 2006.218.07:46:52.67/vb/01,04,usb,yes,31,29 2006.218.07:46:52.67/vb/02,04,usb,yes,32,34 2006.218.07:46:52.67/vb/03,04,usb,yes,29,33 2006.218.07:46:52.67/vb/04,04,usb,yes,30,30 2006.218.07:46:52.67/vb/05,04,usb,yes,28,32 2006.218.07:46:52.67/vb/06,04,usb,yes,29,32 2006.218.07:46:52.67/vb/07,04,usb,yes,31,31 2006.218.07:46:52.67/vb/08,04,usb,yes,29,32 2006.218.07:46:52.91/vblo/01,632.99,yes,locked 2006.218.07:46:52.91/vblo/02,640.99,yes,locked 2006.218.07:46:52.91/vblo/03,656.99,yes,locked 2006.218.07:46:52.91/vblo/04,712.99,yes,locked 2006.218.07:46:52.91/vblo/05,744.99,yes,locked 2006.218.07:46:52.91/vblo/06,752.99,yes,locked 2006.218.07:46:52.91/vblo/07,734.99,yes,locked 2006.218.07:46:52.91/vblo/08,744.99,yes,locked 2006.218.07:46:53.06/vabw/8 2006.218.07:46:53.21/vbbw/8 2006.218.07:46:53.35/xfe/off,on,15.2 2006.218.07:46:53.75/ifatt/23,28,28,28 2006.218.07:46:54.07/fmout-gps/S +4.72E-07 2006.218.07:46:54.11:!2006.218.07:48:30 2006.218.07:48:30.02:data_valid=off 2006.218.07:48:30.02:postob 2006.218.07:48:30.10/cable/+6.3855E-03 2006.218.07:48:30.10/wx/31.22,1007.4,73 2006.218.07:48:30.17/fmout-gps/S +4.70E-07 2006.218.07:48:30.17:scan_name=218-0749,k06218,60 2006.218.07:48:30.18:source=0743+259,074625.87,254902.1,2000.0,ccw 2006.218.07:48:32.14#flagr#flagr/antenna,new-source 2006.218.07:48:32.14:checkk5 2006.218.07:48:32.51/chk_autoobs//k5ts1/ autoobs is running! 2006.218.07:48:32.89/chk_autoobs//k5ts2/ autoobs is running! 2006.218.07:48:33.26/chk_autoobs//k5ts3/ autoobs is running! 2006.218.07:48:33.64/chk_autoobs//k5ts4/ autoobs is running! 2006.218.07:48:34.01/chk_obsdata//k5ts1/T2180746??a.dat file size is correct (nominal:800MB, actual:792MB). 2006.218.07:48:34.39/chk_obsdata//k5ts2/T2180746??b.dat file size is correct (nominal:800MB, actual:792MB). 2006.218.07:48:34.76/chk_obsdata//k5ts3/T2180746??c.dat file size is correct (nominal:800MB, actual:792MB). 2006.218.07:48:35.12/chk_obsdata//k5ts4/T2180746??d.dat file size is correct (nominal:800MB, actual:792MB). 2006.218.07:48:35.81/k5log//k5ts1_log_newline 2006.218.07:48:36.51/k5log//k5ts2_log_newline 2006.218.07:48:37.20/k5log//k5ts3_log_newline 2006.218.07:48:37.91/k5log//k5ts4_log_newline 2006.218.07:48:37.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.218.07:48:37.93:4f8m12a=1 2006.218.07:48:37.93$4f8m12a/echo=on 2006.218.07:48:37.93$4f8m12a/pcalon 2006.218.07:48:37.93$pcalon/"no phase cal control is implemented here 2006.218.07:48:37.93$4f8m12a/"tpicd=stop 2006.218.07:48:37.93$4f8m12a/vc4f8 2006.218.07:48:37.93$vc4f8/valo=1,532.99 2006.218.07:48:37.94#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.218.07:48:37.94#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.218.07:48:37.94#ibcon#ireg 17 cls_cnt 0 2006.218.07:48:37.94#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.218.07:48:37.94#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.218.07:48:37.94#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.218.07:48:37.94#ibcon#enter wrdev, iclass 28, count 0 2006.218.07:48:37.94#ibcon#first serial, iclass 28, count 0 2006.218.07:48:37.94#ibcon#enter sib2, iclass 28, count 0 2006.218.07:48:37.94#ibcon#flushed, iclass 28, count 0 2006.218.07:48:37.94#ibcon#about to write, iclass 28, count 0 2006.218.07:48:37.94#ibcon#wrote, iclass 28, count 0 2006.218.07:48:37.94#ibcon#about to read 3, iclass 28, count 0 2006.218.07:48:37.97#ibcon#read 3, iclass 28, count 0 2006.218.07:48:37.97#ibcon#about to read 4, iclass 28, count 0 2006.218.07:48:37.97#ibcon#read 4, iclass 28, count 0 2006.218.07:48:37.97#ibcon#about to read 5, iclass 28, count 0 2006.218.07:48:37.97#ibcon#read 5, iclass 28, count 0 2006.218.07:48:37.97#ibcon#about to read 6, iclass 28, count 0 2006.218.07:48:37.97#ibcon#read 6, iclass 28, count 0 2006.218.07:48:37.97#ibcon#end of sib2, iclass 28, count 0 2006.218.07:48:37.97#ibcon#*mode == 0, iclass 28, count 0 2006.218.07:48:37.97#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.218.07:48:37.97#ibcon#[26=FRQ=01,532.99\r\n] 2006.218.07:48:37.97#ibcon#*before write, iclass 28, count 0 2006.218.07:48:37.97#ibcon#enter sib2, iclass 28, count 0 2006.218.07:48:37.97#ibcon#flushed, iclass 28, count 0 2006.218.07:48:37.97#ibcon#about to write, iclass 28, count 0 2006.218.07:48:37.97#ibcon#wrote, iclass 28, count 0 2006.218.07:48:37.97#ibcon#about to read 3, iclass 28, count 0 2006.218.07:48:38.02#ibcon#read 3, iclass 28, count 0 2006.218.07:48:38.02#ibcon#about to read 4, iclass 28, count 0 2006.218.07:48:38.02#ibcon#read 4, iclass 28, count 0 2006.218.07:48:38.02#ibcon#about to read 5, iclass 28, count 0 2006.218.07:48:38.02#ibcon#read 5, iclass 28, count 0 2006.218.07:48:38.02#ibcon#about to read 6, iclass 28, count 0 2006.218.07:48:38.02#ibcon#read 6, iclass 28, count 0 2006.218.07:48:38.03#ibcon#end of sib2, iclass 28, count 0 2006.218.07:48:38.03#ibcon#*after write, iclass 28, count 0 2006.218.07:48:38.03#ibcon#*before return 0, iclass 28, count 0 2006.218.07:48:38.03#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.218.07:48:38.03#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.218.07:48:38.03#ibcon#about to clear, iclass 28 cls_cnt 0 2006.218.07:48:38.03#ibcon#cleared, iclass 28 cls_cnt 0 2006.218.07:48:38.03$vc4f8/va=1,5 2006.218.07:48:38.03#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.218.07:48:38.03#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.218.07:48:38.03#ibcon#ireg 11 cls_cnt 2 2006.218.07:48:38.03#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.218.07:48:38.03#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.218.07:48:38.03#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.218.07:48:38.03#ibcon#enter wrdev, iclass 30, count 2 2006.218.07:48:38.03#ibcon#first serial, iclass 30, count 2 2006.218.07:48:38.03#ibcon#enter sib2, iclass 30, count 2 2006.218.07:48:38.03#ibcon#flushed, iclass 30, count 2 2006.218.07:48:38.03#ibcon#about to write, iclass 30, count 2 2006.218.07:48:38.03#ibcon#wrote, iclass 30, count 2 2006.218.07:48:38.03#ibcon#about to read 3, iclass 30, count 2 2006.218.07:48:38.05#ibcon#read 3, iclass 30, count 2 2006.218.07:48:38.05#ibcon#about to read 4, iclass 30, count 2 2006.218.07:48:38.05#ibcon#read 4, iclass 30, count 2 2006.218.07:48:38.05#ibcon#about to read 5, iclass 30, count 2 2006.218.07:48:38.05#ibcon#read 5, iclass 30, count 2 2006.218.07:48:38.05#ibcon#about to read 6, iclass 30, count 2 2006.218.07:48:38.05#ibcon#read 6, iclass 30, count 2 2006.218.07:48:38.05#ibcon#end of sib2, iclass 30, count 2 2006.218.07:48:38.05#ibcon#*mode == 0, iclass 30, count 2 2006.218.07:48:38.05#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.218.07:48:38.05#ibcon#[25=AT01-05\r\n] 2006.218.07:48:38.05#ibcon#*before write, iclass 30, count 2 2006.218.07:48:38.05#ibcon#enter sib2, iclass 30, count 2 2006.218.07:48:38.05#ibcon#flushed, iclass 30, count 2 2006.218.07:48:38.05#ibcon#about to write, iclass 30, count 2 2006.218.07:48:38.05#ibcon#wrote, iclass 30, count 2 2006.218.07:48:38.05#ibcon#about to read 3, iclass 30, count 2 2006.218.07:48:38.08#ibcon#read 3, iclass 30, count 2 2006.218.07:48:38.08#ibcon#about to read 4, iclass 30, count 2 2006.218.07:48:38.09#ibcon#read 4, iclass 30, count 2 2006.218.07:48:38.09#ibcon#about to read 5, iclass 30, count 2 2006.218.07:48:38.09#ibcon#read 5, iclass 30, count 2 2006.218.07:48:38.09#ibcon#about to read 6, iclass 30, count 2 2006.218.07:48:38.09#ibcon#read 6, iclass 30, count 2 2006.218.07:48:38.09#ibcon#end of sib2, iclass 30, count 2 2006.218.07:48:38.09#ibcon#*after write, iclass 30, count 2 2006.218.07:48:38.09#ibcon#*before return 0, iclass 30, count 2 2006.218.07:48:38.09#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.218.07:48:38.09#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.218.07:48:38.09#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.218.07:48:38.09#ibcon#ireg 7 cls_cnt 0 2006.218.07:48:38.09#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.218.07:48:38.20#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.218.07:48:38.20#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.218.07:48:38.20#ibcon#enter wrdev, iclass 30, count 0 2006.218.07:48:38.20#ibcon#first serial, iclass 30, count 0 2006.218.07:48:38.20#ibcon#enter sib2, iclass 30, count 0 2006.218.07:48:38.20#ibcon#flushed, iclass 30, count 0 2006.218.07:48:38.21#ibcon#about to write, iclass 30, count 0 2006.218.07:48:38.21#ibcon#wrote, iclass 30, count 0 2006.218.07:48:38.21#ibcon#about to read 3, iclass 30, count 0 2006.218.07:48:38.24#ibcon#read 3, iclass 30, count 0 2006.218.07:48:38.24#ibcon#about to read 4, iclass 30, count 0 2006.218.07:48:38.24#ibcon#read 4, iclass 30, count 0 2006.218.07:48:38.24#ibcon#about to read 5, iclass 30, count 0 2006.218.07:48:38.24#ibcon#read 5, iclass 30, count 0 2006.218.07:48:38.24#ibcon#about to read 6, iclass 30, count 0 2006.218.07:48:38.24#ibcon#read 6, iclass 30, count 0 2006.218.07:48:38.24#ibcon#end of sib2, iclass 30, count 0 2006.218.07:48:38.24#ibcon#*mode == 0, iclass 30, count 0 2006.218.07:48:38.24#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.218.07:48:38.24#ibcon#[25=USB\r\n] 2006.218.07:48:38.24#ibcon#*before write, iclass 30, count 0 2006.218.07:48:38.24#ibcon#enter sib2, iclass 30, count 0 2006.218.07:48:38.24#ibcon#flushed, iclass 30, count 0 2006.218.07:48:38.24#ibcon#about to write, iclass 30, count 0 2006.218.07:48:38.24#ibcon#wrote, iclass 30, count 0 2006.218.07:48:38.24#ibcon#about to read 3, iclass 30, count 0 2006.218.07:48:38.26#ibcon#read 3, iclass 30, count 0 2006.218.07:48:38.26#ibcon#about to read 4, iclass 30, count 0 2006.218.07:48:38.26#ibcon#read 4, iclass 30, count 0 2006.218.07:48:38.26#ibcon#about to read 5, iclass 30, count 0 2006.218.07:48:38.27#ibcon#read 5, iclass 30, count 0 2006.218.07:48:38.27#ibcon#about to read 6, iclass 30, count 0 2006.218.07:48:38.27#ibcon#read 6, iclass 30, count 0 2006.218.07:48:38.27#ibcon#end of sib2, iclass 30, count 0 2006.218.07:48:38.27#ibcon#*after write, iclass 30, count 0 2006.218.07:48:38.27#ibcon#*before return 0, iclass 30, count 0 2006.218.07:48:38.27#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.218.07:48:38.27#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.218.07:48:38.27#ibcon#about to clear, iclass 30 cls_cnt 0 2006.218.07:48:38.27#ibcon#cleared, iclass 30 cls_cnt 0 2006.218.07:48:38.27$vc4f8/valo=2,572.99 2006.218.07:48:38.27#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.218.07:48:38.27#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.218.07:48:38.27#ibcon#ireg 17 cls_cnt 0 2006.218.07:48:38.27#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.218.07:48:38.27#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.218.07:48:38.27#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.218.07:48:38.27#ibcon#enter wrdev, iclass 32, count 0 2006.218.07:48:38.27#ibcon#first serial, iclass 32, count 0 2006.218.07:48:38.27#ibcon#enter sib2, iclass 32, count 0 2006.218.07:48:38.27#ibcon#flushed, iclass 32, count 0 2006.218.07:48:38.27#ibcon#about to write, iclass 32, count 0 2006.218.07:48:38.27#ibcon#wrote, iclass 32, count 0 2006.218.07:48:38.27#ibcon#about to read 3, iclass 32, count 0 2006.218.07:48:38.28#ibcon#read 3, iclass 32, count 0 2006.218.07:48:38.28#ibcon#about to read 4, iclass 32, count 0 2006.218.07:48:38.28#ibcon#read 4, iclass 32, count 0 2006.218.07:48:38.28#ibcon#about to read 5, iclass 32, count 0 2006.218.07:48:38.29#ibcon#read 5, iclass 32, count 0 2006.218.07:48:38.29#ibcon#about to read 6, iclass 32, count 0 2006.218.07:48:38.29#ibcon#read 6, iclass 32, count 0 2006.218.07:48:38.29#ibcon#end of sib2, iclass 32, count 0 2006.218.07:48:38.29#ibcon#*mode == 0, iclass 32, count 0 2006.218.07:48:38.29#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.218.07:48:38.29#ibcon#[26=FRQ=02,572.99\r\n] 2006.218.07:48:38.29#ibcon#*before write, iclass 32, count 0 2006.218.07:48:38.29#ibcon#enter sib2, iclass 32, count 0 2006.218.07:48:38.29#ibcon#flushed, iclass 32, count 0 2006.218.07:48:38.29#ibcon#about to write, iclass 32, count 0 2006.218.07:48:38.29#ibcon#wrote, iclass 32, count 0 2006.218.07:48:38.29#ibcon#about to read 3, iclass 32, count 0 2006.218.07:48:38.33#ibcon#read 3, iclass 32, count 0 2006.218.07:48:38.33#ibcon#about to read 4, iclass 32, count 0 2006.218.07:48:38.33#ibcon#read 4, iclass 32, count 0 2006.218.07:48:38.33#ibcon#about to read 5, iclass 32, count 0 2006.218.07:48:38.33#ibcon#read 5, iclass 32, count 0 2006.218.07:48:38.33#ibcon#about to read 6, iclass 32, count 0 2006.218.07:48:38.33#ibcon#read 6, iclass 32, count 0 2006.218.07:48:38.33#ibcon#end of sib2, iclass 32, count 0 2006.218.07:48:38.33#ibcon#*after write, iclass 32, count 0 2006.218.07:48:38.33#ibcon#*before return 0, iclass 32, count 0 2006.218.07:48:38.33#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.218.07:48:38.33#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.218.07:48:38.33#ibcon#about to clear, iclass 32 cls_cnt 0 2006.218.07:48:38.33#ibcon#cleared, iclass 32 cls_cnt 0 2006.218.07:48:38.33$vc4f8/va=2,4 2006.218.07:48:38.33#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.218.07:48:38.33#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.218.07:48:38.33#ibcon#ireg 11 cls_cnt 2 2006.218.07:48:38.33#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.218.07:48:38.38#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.218.07:48:38.38#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.218.07:48:38.38#ibcon#enter wrdev, iclass 34, count 2 2006.218.07:48:38.38#ibcon#first serial, iclass 34, count 2 2006.218.07:48:38.38#ibcon#enter sib2, iclass 34, count 2 2006.218.07:48:38.38#ibcon#flushed, iclass 34, count 2 2006.218.07:48:38.39#ibcon#about to write, iclass 34, count 2 2006.218.07:48:38.39#ibcon#wrote, iclass 34, count 2 2006.218.07:48:38.39#ibcon#about to read 3, iclass 34, count 2 2006.218.07:48:38.41#ibcon#read 3, iclass 34, count 2 2006.218.07:48:38.41#ibcon#about to read 4, iclass 34, count 2 2006.218.07:48:38.41#ibcon#read 4, iclass 34, count 2 2006.218.07:48:38.41#ibcon#about to read 5, iclass 34, count 2 2006.218.07:48:38.41#ibcon#read 5, iclass 34, count 2 2006.218.07:48:38.41#ibcon#about to read 6, iclass 34, count 2 2006.218.07:48:38.41#ibcon#read 6, iclass 34, count 2 2006.218.07:48:38.41#ibcon#end of sib2, iclass 34, count 2 2006.218.07:48:38.41#ibcon#*mode == 0, iclass 34, count 2 2006.218.07:48:38.41#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.218.07:48:38.41#ibcon#[25=AT02-04\r\n] 2006.218.07:48:38.41#ibcon#*before write, iclass 34, count 2 2006.218.07:48:38.41#ibcon#enter sib2, iclass 34, count 2 2006.218.07:48:38.41#ibcon#flushed, iclass 34, count 2 2006.218.07:48:38.41#ibcon#about to write, iclass 34, count 2 2006.218.07:48:38.41#ibcon#wrote, iclass 34, count 2 2006.218.07:48:38.41#ibcon#about to read 3, iclass 34, count 2 2006.218.07:48:38.44#ibcon#read 3, iclass 34, count 2 2006.218.07:48:38.44#ibcon#about to read 4, iclass 34, count 2 2006.218.07:48:38.44#ibcon#read 4, iclass 34, count 2 2006.218.07:48:38.44#ibcon#about to read 5, iclass 34, count 2 2006.218.07:48:38.44#ibcon#read 5, iclass 34, count 2 2006.218.07:48:38.44#ibcon#about to read 6, iclass 34, count 2 2006.218.07:48:38.44#ibcon#read 6, iclass 34, count 2 2006.218.07:48:38.44#ibcon#end of sib2, iclass 34, count 2 2006.218.07:48:38.44#ibcon#*after write, iclass 34, count 2 2006.218.07:48:38.44#ibcon#*before return 0, iclass 34, count 2 2006.218.07:48:38.44#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.218.07:48:38.44#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.218.07:48:38.44#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.218.07:48:38.44#ibcon#ireg 7 cls_cnt 0 2006.218.07:48:38.44#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.218.07:48:38.55#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.218.07:48:38.55#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.218.07:48:38.55#ibcon#enter wrdev, iclass 34, count 0 2006.218.07:48:38.55#ibcon#first serial, iclass 34, count 0 2006.218.07:48:38.55#ibcon#enter sib2, iclass 34, count 0 2006.218.07:48:38.55#ibcon#flushed, iclass 34, count 0 2006.218.07:48:38.55#ibcon#about to write, iclass 34, count 0 2006.218.07:48:38.56#ibcon#wrote, iclass 34, count 0 2006.218.07:48:38.56#ibcon#about to read 3, iclass 34, count 0 2006.218.07:48:38.57#ibcon#read 3, iclass 34, count 0 2006.218.07:48:38.57#ibcon#about to read 4, iclass 34, count 0 2006.218.07:48:38.57#ibcon#read 4, iclass 34, count 0 2006.218.07:48:38.57#ibcon#about to read 5, iclass 34, count 0 2006.218.07:48:38.57#ibcon#read 5, iclass 34, count 0 2006.218.07:48:38.58#ibcon#about to read 6, iclass 34, count 0 2006.218.07:48:38.58#ibcon#read 6, iclass 34, count 0 2006.218.07:48:38.58#ibcon#end of sib2, iclass 34, count 0 2006.218.07:48:38.58#ibcon#*mode == 0, iclass 34, count 0 2006.218.07:48:38.58#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.218.07:48:38.58#ibcon#[25=USB\r\n] 2006.218.07:48:38.58#ibcon#*before write, iclass 34, count 0 2006.218.07:48:38.58#ibcon#enter sib2, iclass 34, count 0 2006.218.07:48:38.58#ibcon#flushed, iclass 34, count 0 2006.218.07:48:38.58#ibcon#about to write, iclass 34, count 0 2006.218.07:48:38.58#ibcon#wrote, iclass 34, count 0 2006.218.07:48:38.58#ibcon#about to read 3, iclass 34, count 0 2006.218.07:48:38.60#ibcon#read 3, iclass 34, count 0 2006.218.07:48:38.60#ibcon#about to read 4, iclass 34, count 0 2006.218.07:48:38.60#ibcon#read 4, iclass 34, count 0 2006.218.07:48:38.61#ibcon#about to read 5, iclass 34, count 0 2006.218.07:48:38.61#ibcon#read 5, iclass 34, count 0 2006.218.07:48:38.61#ibcon#about to read 6, iclass 34, count 0 2006.218.07:48:38.61#ibcon#read 6, iclass 34, count 0 2006.218.07:48:38.61#ibcon#end of sib2, iclass 34, count 0 2006.218.07:48:38.61#ibcon#*after write, iclass 34, count 0 2006.218.07:48:38.61#ibcon#*before return 0, iclass 34, count 0 2006.218.07:48:38.61#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.218.07:48:38.61#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.218.07:48:38.61#ibcon#about to clear, iclass 34 cls_cnt 0 2006.218.07:48:38.61#ibcon#cleared, iclass 34 cls_cnt 0 2006.218.07:48:38.61$vc4f8/valo=3,672.99 2006.218.07:48:38.61#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.218.07:48:38.61#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.218.07:48:38.61#ibcon#ireg 17 cls_cnt 0 2006.218.07:48:38.61#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.218.07:48:38.61#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.218.07:48:38.61#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.218.07:48:38.61#ibcon#enter wrdev, iclass 36, count 0 2006.218.07:48:38.61#ibcon#first serial, iclass 36, count 0 2006.218.07:48:38.61#ibcon#enter sib2, iclass 36, count 0 2006.218.07:48:38.61#ibcon#flushed, iclass 36, count 0 2006.218.07:48:38.61#ibcon#about to write, iclass 36, count 0 2006.218.07:48:38.61#ibcon#wrote, iclass 36, count 0 2006.218.07:48:38.61#ibcon#about to read 3, iclass 36, count 0 2006.218.07:48:38.63#ibcon#read 3, iclass 36, count 0 2006.218.07:48:38.63#ibcon#about to read 4, iclass 36, count 0 2006.218.07:48:38.63#ibcon#read 4, iclass 36, count 0 2006.218.07:48:38.63#ibcon#about to read 5, iclass 36, count 0 2006.218.07:48:38.63#ibcon#read 5, iclass 36, count 0 2006.218.07:48:38.63#ibcon#about to read 6, iclass 36, count 0 2006.218.07:48:38.63#ibcon#read 6, iclass 36, count 0 2006.218.07:48:38.63#ibcon#end of sib2, iclass 36, count 0 2006.218.07:48:38.63#ibcon#*mode == 0, iclass 36, count 0 2006.218.07:48:38.63#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.218.07:48:38.63#ibcon#[26=FRQ=03,672.99\r\n] 2006.218.07:48:38.63#ibcon#*before write, iclass 36, count 0 2006.218.07:48:38.63#ibcon#enter sib2, iclass 36, count 0 2006.218.07:48:38.63#ibcon#flushed, iclass 36, count 0 2006.218.07:48:38.63#ibcon#about to write, iclass 36, count 0 2006.218.07:48:38.63#ibcon#wrote, iclass 36, count 0 2006.218.07:48:38.63#ibcon#about to read 3, iclass 36, count 0 2006.218.07:48:38.67#ibcon#read 3, iclass 36, count 0 2006.218.07:48:38.67#ibcon#about to read 4, iclass 36, count 0 2006.218.07:48:38.68#ibcon#read 4, iclass 36, count 0 2006.218.07:48:38.68#ibcon#about to read 5, iclass 36, count 0 2006.218.07:48:38.68#ibcon#read 5, iclass 36, count 0 2006.218.07:48:38.68#ibcon#about to read 6, iclass 36, count 0 2006.218.07:48:38.68#ibcon#read 6, iclass 36, count 0 2006.218.07:48:38.68#ibcon#end of sib2, iclass 36, count 0 2006.218.07:48:38.68#ibcon#*after write, iclass 36, count 0 2006.218.07:48:38.68#ibcon#*before return 0, iclass 36, count 0 2006.218.07:48:38.68#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.218.07:48:38.68#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.218.07:48:38.68#ibcon#about to clear, iclass 36 cls_cnt 0 2006.218.07:48:38.68#ibcon#cleared, iclass 36 cls_cnt 0 2006.218.07:48:38.68$vc4f8/va=3,4 2006.218.07:48:38.68#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.218.07:48:38.68#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.218.07:48:38.68#ibcon#ireg 11 cls_cnt 2 2006.218.07:48:38.68#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.218.07:48:38.73#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.218.07:48:38.73#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.218.07:48:38.73#ibcon#enter wrdev, iclass 38, count 2 2006.218.07:48:38.73#ibcon#first serial, iclass 38, count 2 2006.218.07:48:38.73#ibcon#enter sib2, iclass 38, count 2 2006.218.07:48:38.73#ibcon#flushed, iclass 38, count 2 2006.218.07:48:38.73#ibcon#about to write, iclass 38, count 2 2006.218.07:48:38.73#ibcon#wrote, iclass 38, count 2 2006.218.07:48:38.73#ibcon#about to read 3, iclass 38, count 2 2006.218.07:48:38.74#ibcon#read 3, iclass 38, count 2 2006.218.07:48:38.74#ibcon#about to read 4, iclass 38, count 2 2006.218.07:48:38.74#ibcon#read 4, iclass 38, count 2 2006.218.07:48:38.74#ibcon#about to read 5, iclass 38, count 2 2006.218.07:48:38.74#ibcon#read 5, iclass 38, count 2 2006.218.07:48:38.75#ibcon#about to read 6, iclass 38, count 2 2006.218.07:48:38.75#ibcon#read 6, iclass 38, count 2 2006.218.07:48:38.75#ibcon#end of sib2, iclass 38, count 2 2006.218.07:48:38.75#ibcon#*mode == 0, iclass 38, count 2 2006.218.07:48:38.75#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.218.07:48:38.75#ibcon#[25=AT03-04\r\n] 2006.218.07:48:38.75#ibcon#*before write, iclass 38, count 2 2006.218.07:48:38.75#ibcon#enter sib2, iclass 38, count 2 2006.218.07:48:38.75#ibcon#flushed, iclass 38, count 2 2006.218.07:48:38.75#ibcon#about to write, iclass 38, count 2 2006.218.07:48:38.75#ibcon#wrote, iclass 38, count 2 2006.218.07:48:38.75#ibcon#about to read 3, iclass 38, count 2 2006.218.07:48:38.77#ibcon#read 3, iclass 38, count 2 2006.218.07:48:38.77#ibcon#about to read 4, iclass 38, count 2 2006.218.07:48:38.78#ibcon#read 4, iclass 38, count 2 2006.218.07:48:38.78#ibcon#about to read 5, iclass 38, count 2 2006.218.07:48:38.78#ibcon#read 5, iclass 38, count 2 2006.218.07:48:38.78#ibcon#about to read 6, iclass 38, count 2 2006.218.07:48:38.78#ibcon#read 6, iclass 38, count 2 2006.218.07:48:38.78#ibcon#end of sib2, iclass 38, count 2 2006.218.07:48:38.78#ibcon#*after write, iclass 38, count 2 2006.218.07:48:38.78#ibcon#*before return 0, iclass 38, count 2 2006.218.07:48:38.78#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.218.07:48:38.78#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.218.07:48:38.78#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.218.07:48:38.78#ibcon#ireg 7 cls_cnt 0 2006.218.07:48:38.78#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.218.07:48:38.89#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.218.07:48:38.89#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.218.07:48:38.89#ibcon#enter wrdev, iclass 38, count 0 2006.218.07:48:38.89#ibcon#first serial, iclass 38, count 0 2006.218.07:48:38.89#ibcon#enter sib2, iclass 38, count 0 2006.218.07:48:38.89#ibcon#flushed, iclass 38, count 0 2006.218.07:48:38.89#ibcon#about to write, iclass 38, count 0 2006.218.07:48:38.90#ibcon#wrote, iclass 38, count 0 2006.218.07:48:38.90#ibcon#about to read 3, iclass 38, count 0 2006.218.07:48:38.91#ibcon#read 3, iclass 38, count 0 2006.218.07:48:38.91#ibcon#about to read 4, iclass 38, count 0 2006.218.07:48:38.91#ibcon#read 4, iclass 38, count 0 2006.218.07:48:38.91#ibcon#about to read 5, iclass 38, count 0 2006.218.07:48:38.91#ibcon#read 5, iclass 38, count 0 2006.218.07:48:38.92#ibcon#about to read 6, iclass 38, count 0 2006.218.07:48:38.92#ibcon#read 6, iclass 38, count 0 2006.218.07:48:38.92#ibcon#end of sib2, iclass 38, count 0 2006.218.07:48:38.92#ibcon#*mode == 0, iclass 38, count 0 2006.218.07:48:38.92#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.218.07:48:38.92#ibcon#[25=USB\r\n] 2006.218.07:48:38.92#ibcon#*before write, iclass 38, count 0 2006.218.07:48:38.92#ibcon#enter sib2, iclass 38, count 0 2006.218.07:48:38.92#ibcon#flushed, iclass 38, count 0 2006.218.07:48:38.92#ibcon#about to write, iclass 38, count 0 2006.218.07:48:38.92#ibcon#wrote, iclass 38, count 0 2006.218.07:48:38.92#ibcon#about to read 3, iclass 38, count 0 2006.218.07:48:38.94#ibcon#read 3, iclass 38, count 0 2006.218.07:48:38.94#ibcon#about to read 4, iclass 38, count 0 2006.218.07:48:38.94#ibcon#read 4, iclass 38, count 0 2006.218.07:48:38.94#ibcon#about to read 5, iclass 38, count 0 2006.218.07:48:38.94#ibcon#read 5, iclass 38, count 0 2006.218.07:48:38.95#ibcon#about to read 6, iclass 38, count 0 2006.218.07:48:38.95#ibcon#read 6, iclass 38, count 0 2006.218.07:48:38.95#ibcon#end of sib2, iclass 38, count 0 2006.218.07:48:38.95#ibcon#*after write, iclass 38, count 0 2006.218.07:48:38.95#ibcon#*before return 0, iclass 38, count 0 2006.218.07:48:38.95#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.218.07:48:38.95#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.218.07:48:38.95#ibcon#about to clear, iclass 38 cls_cnt 0 2006.218.07:48:38.95#ibcon#cleared, iclass 38 cls_cnt 0 2006.218.07:48:38.95$vc4f8/valo=4,832.99 2006.218.07:48:38.95#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.218.07:48:38.95#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.218.07:48:38.95#ibcon#ireg 17 cls_cnt 0 2006.218.07:48:38.95#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.218.07:48:38.95#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.218.07:48:38.95#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.218.07:48:38.95#ibcon#enter wrdev, iclass 40, count 0 2006.218.07:48:38.95#ibcon#first serial, iclass 40, count 0 2006.218.07:48:38.95#ibcon#enter sib2, iclass 40, count 0 2006.218.07:48:38.95#ibcon#flushed, iclass 40, count 0 2006.218.07:48:38.95#ibcon#about to write, iclass 40, count 0 2006.218.07:48:38.95#ibcon#wrote, iclass 40, count 0 2006.218.07:48:38.95#ibcon#about to read 3, iclass 40, count 0 2006.218.07:48:38.96#ibcon#read 3, iclass 40, count 0 2006.218.07:48:38.96#ibcon#about to read 4, iclass 40, count 0 2006.218.07:48:38.96#ibcon#read 4, iclass 40, count 0 2006.218.07:48:38.96#ibcon#about to read 5, iclass 40, count 0 2006.218.07:48:38.96#ibcon#read 5, iclass 40, count 0 2006.218.07:48:38.97#ibcon#about to read 6, iclass 40, count 0 2006.218.07:48:38.97#ibcon#read 6, iclass 40, count 0 2006.218.07:48:38.97#ibcon#end of sib2, iclass 40, count 0 2006.218.07:48:38.97#ibcon#*mode == 0, iclass 40, count 0 2006.218.07:48:38.97#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.218.07:48:38.97#ibcon#[26=FRQ=04,832.99\r\n] 2006.218.07:48:38.97#ibcon#*before write, iclass 40, count 0 2006.218.07:48:38.97#ibcon#enter sib2, iclass 40, count 0 2006.218.07:48:38.97#ibcon#flushed, iclass 40, count 0 2006.218.07:48:38.97#ibcon#about to write, iclass 40, count 0 2006.218.07:48:38.97#ibcon#wrote, iclass 40, count 0 2006.218.07:48:38.97#ibcon#about to read 3, iclass 40, count 0 2006.218.07:48:39.01#ibcon#read 3, iclass 40, count 0 2006.218.07:48:39.01#ibcon#about to read 4, iclass 40, count 0 2006.218.07:48:39.01#ibcon#read 4, iclass 40, count 0 2006.218.07:48:39.01#ibcon#about to read 5, iclass 40, count 0 2006.218.07:48:39.01#ibcon#read 5, iclass 40, count 0 2006.218.07:48:39.01#ibcon#about to read 6, iclass 40, count 0 2006.218.07:48:39.01#ibcon#read 6, iclass 40, count 0 2006.218.07:48:39.01#ibcon#end of sib2, iclass 40, count 0 2006.218.07:48:39.01#ibcon#*after write, iclass 40, count 0 2006.218.07:48:39.01#ibcon#*before return 0, iclass 40, count 0 2006.218.07:48:39.01#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.218.07:48:39.01#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.218.07:48:39.01#ibcon#about to clear, iclass 40 cls_cnt 0 2006.218.07:48:39.01#ibcon#cleared, iclass 40 cls_cnt 0 2006.218.07:48:39.01$vc4f8/va=4,4 2006.218.07:48:39.01#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.218.07:48:39.01#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.218.07:48:39.01#ibcon#ireg 11 cls_cnt 2 2006.218.07:48:39.01#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.218.07:48:39.06#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.218.07:48:39.06#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.218.07:48:39.06#ibcon#enter wrdev, iclass 4, count 2 2006.218.07:48:39.06#ibcon#first serial, iclass 4, count 2 2006.218.07:48:39.06#ibcon#enter sib2, iclass 4, count 2 2006.218.07:48:39.06#ibcon#flushed, iclass 4, count 2 2006.218.07:48:39.07#ibcon#about to write, iclass 4, count 2 2006.218.07:48:39.07#ibcon#wrote, iclass 4, count 2 2006.218.07:48:39.07#ibcon#about to read 3, iclass 4, count 2 2006.218.07:48:39.08#ibcon#read 3, iclass 4, count 2 2006.218.07:48:39.08#ibcon#about to read 4, iclass 4, count 2 2006.218.07:48:39.08#ibcon#read 4, iclass 4, count 2 2006.218.07:48:39.09#ibcon#about to read 5, iclass 4, count 2 2006.218.07:48:39.09#ibcon#read 5, iclass 4, count 2 2006.218.07:48:39.09#ibcon#about to read 6, iclass 4, count 2 2006.218.07:48:39.09#ibcon#read 6, iclass 4, count 2 2006.218.07:48:39.09#ibcon#end of sib2, iclass 4, count 2 2006.218.07:48:39.09#ibcon#*mode == 0, iclass 4, count 2 2006.218.07:48:39.09#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.218.07:48:39.09#ibcon#[25=AT04-04\r\n] 2006.218.07:48:39.09#ibcon#*before write, iclass 4, count 2 2006.218.07:48:39.09#ibcon#enter sib2, iclass 4, count 2 2006.218.07:48:39.09#ibcon#flushed, iclass 4, count 2 2006.218.07:48:39.09#ibcon#about to write, iclass 4, count 2 2006.218.07:48:39.09#ibcon#wrote, iclass 4, count 2 2006.218.07:48:39.09#ibcon#about to read 3, iclass 4, count 2 2006.218.07:48:39.11#ibcon#read 3, iclass 4, count 2 2006.218.07:48:39.11#ibcon#about to read 4, iclass 4, count 2 2006.218.07:48:39.11#ibcon#read 4, iclass 4, count 2 2006.218.07:48:39.11#ibcon#about to read 5, iclass 4, count 2 2006.218.07:48:39.11#ibcon#read 5, iclass 4, count 2 2006.218.07:48:39.12#ibcon#about to read 6, iclass 4, count 2 2006.218.07:48:39.12#ibcon#read 6, iclass 4, count 2 2006.218.07:48:39.12#ibcon#end of sib2, iclass 4, count 2 2006.218.07:48:39.12#ibcon#*after write, iclass 4, count 2 2006.218.07:48:39.12#ibcon#*before return 0, iclass 4, count 2 2006.218.07:48:39.12#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.218.07:48:39.12#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.218.07:48:39.12#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.218.07:48:39.12#ibcon#ireg 7 cls_cnt 0 2006.218.07:48:39.12#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.218.07:48:39.23#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.218.07:48:39.23#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.218.07:48:39.23#ibcon#enter wrdev, iclass 4, count 0 2006.218.07:48:39.23#ibcon#first serial, iclass 4, count 0 2006.218.07:48:39.23#ibcon#enter sib2, iclass 4, count 0 2006.218.07:48:39.23#ibcon#flushed, iclass 4, count 0 2006.218.07:48:39.23#ibcon#about to write, iclass 4, count 0 2006.218.07:48:39.24#ibcon#wrote, iclass 4, count 0 2006.218.07:48:39.24#ibcon#about to read 3, iclass 4, count 0 2006.218.07:48:39.25#ibcon#read 3, iclass 4, count 0 2006.218.07:48:39.25#ibcon#about to read 4, iclass 4, count 0 2006.218.07:48:39.25#ibcon#read 4, iclass 4, count 0 2006.218.07:48:39.25#ibcon#about to read 5, iclass 4, count 0 2006.218.07:48:39.25#ibcon#read 5, iclass 4, count 0 2006.218.07:48:39.26#ibcon#about to read 6, iclass 4, count 0 2006.218.07:48:39.26#ibcon#read 6, iclass 4, count 0 2006.218.07:48:39.26#ibcon#end of sib2, iclass 4, count 0 2006.218.07:48:39.26#ibcon#*mode == 0, iclass 4, count 0 2006.218.07:48:39.26#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.218.07:48:39.26#ibcon#[25=USB\r\n] 2006.218.07:48:39.26#ibcon#*before write, iclass 4, count 0 2006.218.07:48:39.26#ibcon#enter sib2, iclass 4, count 0 2006.218.07:48:39.26#ibcon#flushed, iclass 4, count 0 2006.218.07:48:39.26#ibcon#about to write, iclass 4, count 0 2006.218.07:48:39.26#ibcon#wrote, iclass 4, count 0 2006.218.07:48:39.26#ibcon#about to read 3, iclass 4, count 0 2006.218.07:48:39.28#ibcon#read 3, iclass 4, count 0 2006.218.07:48:39.28#ibcon#about to read 4, iclass 4, count 0 2006.218.07:48:39.28#ibcon#read 4, iclass 4, count 0 2006.218.07:48:39.28#ibcon#about to read 5, iclass 4, count 0 2006.218.07:48:39.28#ibcon#read 5, iclass 4, count 0 2006.218.07:48:39.29#ibcon#about to read 6, iclass 4, count 0 2006.218.07:48:39.29#ibcon#read 6, iclass 4, count 0 2006.218.07:48:39.29#ibcon#end of sib2, iclass 4, count 0 2006.218.07:48:39.29#ibcon#*after write, iclass 4, count 0 2006.218.07:48:39.29#ibcon#*before return 0, iclass 4, count 0 2006.218.07:48:39.29#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.218.07:48:39.29#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.218.07:48:39.29#ibcon#about to clear, iclass 4 cls_cnt 0 2006.218.07:48:39.29#ibcon#cleared, iclass 4 cls_cnt 0 2006.218.07:48:39.29$vc4f8/valo=5,652.99 2006.218.07:48:39.29#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.218.07:48:39.29#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.218.07:48:39.29#ibcon#ireg 17 cls_cnt 0 2006.218.07:48:39.29#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.218.07:48:39.29#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.218.07:48:39.29#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.218.07:48:39.29#ibcon#enter wrdev, iclass 6, count 0 2006.218.07:48:39.29#ibcon#first serial, iclass 6, count 0 2006.218.07:48:39.29#ibcon#enter sib2, iclass 6, count 0 2006.218.07:48:39.29#ibcon#flushed, iclass 6, count 0 2006.218.07:48:39.29#ibcon#about to write, iclass 6, count 0 2006.218.07:48:39.29#ibcon#wrote, iclass 6, count 0 2006.218.07:48:39.29#ibcon#about to read 3, iclass 6, count 0 2006.218.07:48:39.30#ibcon#read 3, iclass 6, count 0 2006.218.07:48:39.30#ibcon#about to read 4, iclass 6, count 0 2006.218.07:48:39.30#ibcon#read 4, iclass 6, count 0 2006.218.07:48:39.30#ibcon#about to read 5, iclass 6, count 0 2006.218.07:48:39.30#ibcon#read 5, iclass 6, count 0 2006.218.07:48:39.31#ibcon#about to read 6, iclass 6, count 0 2006.218.07:48:39.31#ibcon#read 6, iclass 6, count 0 2006.218.07:48:39.31#ibcon#end of sib2, iclass 6, count 0 2006.218.07:48:39.31#ibcon#*mode == 0, iclass 6, count 0 2006.218.07:48:39.31#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.218.07:48:39.31#ibcon#[26=FRQ=05,652.99\r\n] 2006.218.07:48:39.31#ibcon#*before write, iclass 6, count 0 2006.218.07:48:39.31#ibcon#enter sib2, iclass 6, count 0 2006.218.07:48:39.31#ibcon#flushed, iclass 6, count 0 2006.218.07:48:39.31#ibcon#about to write, iclass 6, count 0 2006.218.07:48:39.31#ibcon#wrote, iclass 6, count 0 2006.218.07:48:39.31#ibcon#about to read 3, iclass 6, count 0 2006.218.07:48:39.34#ibcon#read 3, iclass 6, count 0 2006.218.07:48:39.34#ibcon#about to read 4, iclass 6, count 0 2006.218.07:48:39.34#ibcon#read 4, iclass 6, count 0 2006.218.07:48:39.34#ibcon#about to read 5, iclass 6, count 0 2006.218.07:48:39.35#ibcon#read 5, iclass 6, count 0 2006.218.07:48:39.35#ibcon#about to read 6, iclass 6, count 0 2006.218.07:48:39.35#ibcon#read 6, iclass 6, count 0 2006.218.07:48:39.35#ibcon#end of sib2, iclass 6, count 0 2006.218.07:48:39.35#ibcon#*after write, iclass 6, count 0 2006.218.07:48:39.35#ibcon#*before return 0, iclass 6, count 0 2006.218.07:48:39.35#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.218.07:48:39.35#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.218.07:48:39.35#ibcon#about to clear, iclass 6 cls_cnt 0 2006.218.07:48:39.35#ibcon#cleared, iclass 6 cls_cnt 0 2006.218.07:48:39.35$vc4f8/va=5,7 2006.218.07:48:39.35#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.218.07:48:39.35#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.218.07:48:39.35#ibcon#ireg 11 cls_cnt 2 2006.218.07:48:39.35#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.218.07:48:39.40#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.218.07:48:39.40#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.218.07:48:39.40#ibcon#enter wrdev, iclass 10, count 2 2006.218.07:48:39.40#ibcon#first serial, iclass 10, count 2 2006.218.07:48:39.40#ibcon#enter sib2, iclass 10, count 2 2006.218.07:48:39.40#ibcon#flushed, iclass 10, count 2 2006.218.07:48:39.40#ibcon#about to write, iclass 10, count 2 2006.218.07:48:39.41#ibcon#wrote, iclass 10, count 2 2006.218.07:48:39.41#ibcon#about to read 3, iclass 10, count 2 2006.218.07:48:39.42#abcon#<5=/06 4.0 6.9 31.22 731007.4\r\n> 2006.218.07:48:39.43#ibcon#read 3, iclass 10, count 2 2006.218.07:48:39.43#ibcon#about to read 4, iclass 10, count 2 2006.218.07:48:39.43#ibcon#read 4, iclass 10, count 2 2006.218.07:48:39.43#ibcon#about to read 5, iclass 10, count 2 2006.218.07:48:39.43#ibcon#read 5, iclass 10, count 2 2006.218.07:48:39.43#ibcon#about to read 6, iclass 10, count 2 2006.218.07:48:39.43#ibcon#read 6, iclass 10, count 2 2006.218.07:48:39.43#ibcon#end of sib2, iclass 10, count 2 2006.218.07:48:39.43#ibcon#*mode == 0, iclass 10, count 2 2006.218.07:48:39.43#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.218.07:48:39.43#ibcon#[25=AT05-07\r\n] 2006.218.07:48:39.43#ibcon#*before write, iclass 10, count 2 2006.218.07:48:39.43#ibcon#enter sib2, iclass 10, count 2 2006.218.07:48:39.43#ibcon#flushed, iclass 10, count 2 2006.218.07:48:39.43#ibcon#about to write, iclass 10, count 2 2006.218.07:48:39.43#ibcon#wrote, iclass 10, count 2 2006.218.07:48:39.43#ibcon#about to read 3, iclass 10, count 2 2006.218.07:48:39.44#abcon#{5=INTERFACE CLEAR} 2006.218.07:48:39.45#ibcon#read 3, iclass 10, count 2 2006.218.07:48:39.45#ibcon#about to read 4, iclass 10, count 2 2006.218.07:48:39.45#ibcon#read 4, iclass 10, count 2 2006.218.07:48:39.45#ibcon#about to read 5, iclass 10, count 2 2006.218.07:48:39.45#ibcon#read 5, iclass 10, count 2 2006.218.07:48:39.46#ibcon#about to read 6, iclass 10, count 2 2006.218.07:48:39.46#ibcon#read 6, iclass 10, count 2 2006.218.07:48:39.46#ibcon#end of sib2, iclass 10, count 2 2006.218.07:48:39.46#ibcon#*after write, iclass 10, count 2 2006.218.07:48:39.46#ibcon#*before return 0, iclass 10, count 2 2006.218.07:48:39.46#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.218.07:48:39.46#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.218.07:48:39.46#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.218.07:48:39.46#ibcon#ireg 7 cls_cnt 0 2006.218.07:48:39.46#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.218.07:48:39.51#abcon#[5=S1D000X0/0*\r\n] 2006.218.07:48:39.57#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.218.07:48:39.57#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.218.07:48:39.57#ibcon#enter wrdev, iclass 10, count 0 2006.218.07:48:39.57#ibcon#first serial, iclass 10, count 0 2006.218.07:48:39.57#ibcon#enter sib2, iclass 10, count 0 2006.218.07:48:39.58#ibcon#flushed, iclass 10, count 0 2006.218.07:48:39.58#ibcon#about to write, iclass 10, count 0 2006.218.07:48:39.58#ibcon#wrote, iclass 10, count 0 2006.218.07:48:39.58#ibcon#about to read 3, iclass 10, count 0 2006.218.07:48:39.61#ibcon#read 3, iclass 10, count 0 2006.218.07:48:39.61#ibcon#about to read 4, iclass 10, count 0 2006.218.07:48:39.61#ibcon#read 4, iclass 10, count 0 2006.218.07:48:39.61#ibcon#about to read 5, iclass 10, count 0 2006.218.07:48:39.61#ibcon#read 5, iclass 10, count 0 2006.218.07:48:39.61#ibcon#about to read 6, iclass 10, count 0 2006.218.07:48:39.61#ibcon#read 6, iclass 10, count 0 2006.218.07:48:39.61#ibcon#end of sib2, iclass 10, count 0 2006.218.07:48:39.61#ibcon#*mode == 0, iclass 10, count 0 2006.218.07:48:39.61#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.218.07:48:39.61#ibcon#[25=USB\r\n] 2006.218.07:48:39.61#ibcon#*before write, iclass 10, count 0 2006.218.07:48:39.61#ibcon#enter sib2, iclass 10, count 0 2006.218.07:48:39.61#ibcon#flushed, iclass 10, count 0 2006.218.07:48:39.61#ibcon#about to write, iclass 10, count 0 2006.218.07:48:39.61#ibcon#wrote, iclass 10, count 0 2006.218.07:48:39.61#ibcon#about to read 3, iclass 10, count 0 2006.218.07:48:39.63#ibcon#read 3, iclass 10, count 0 2006.218.07:48:39.63#ibcon#about to read 4, iclass 10, count 0 2006.218.07:48:39.63#ibcon#read 4, iclass 10, count 0 2006.218.07:48:39.63#ibcon#about to read 5, iclass 10, count 0 2006.218.07:48:39.63#ibcon#read 5, iclass 10, count 0 2006.218.07:48:39.64#ibcon#about to read 6, iclass 10, count 0 2006.218.07:48:39.64#ibcon#read 6, iclass 10, count 0 2006.218.07:48:39.64#ibcon#end of sib2, iclass 10, count 0 2006.218.07:48:39.64#ibcon#*after write, iclass 10, count 0 2006.218.07:48:39.64#ibcon#*before return 0, iclass 10, count 0 2006.218.07:48:39.64#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.218.07:48:39.64#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.218.07:48:39.64#ibcon#about to clear, iclass 10 cls_cnt 0 2006.218.07:48:39.64#ibcon#cleared, iclass 10 cls_cnt 0 2006.218.07:48:39.64$vc4f8/valo=6,772.99 2006.218.07:48:39.64#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.218.07:48:39.64#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.218.07:48:39.64#ibcon#ireg 17 cls_cnt 0 2006.218.07:48:39.64#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.218.07:48:39.64#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.218.07:48:39.64#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.218.07:48:39.64#ibcon#enter wrdev, iclass 16, count 0 2006.218.07:48:39.64#ibcon#first serial, iclass 16, count 0 2006.218.07:48:39.64#ibcon#enter sib2, iclass 16, count 0 2006.218.07:48:39.64#ibcon#flushed, iclass 16, count 0 2006.218.07:48:39.64#ibcon#about to write, iclass 16, count 0 2006.218.07:48:39.64#ibcon#wrote, iclass 16, count 0 2006.218.07:48:39.64#ibcon#about to read 3, iclass 16, count 0 2006.218.07:48:39.65#ibcon#read 3, iclass 16, count 0 2006.218.07:48:39.65#ibcon#about to read 4, iclass 16, count 0 2006.218.07:48:39.65#ibcon#read 4, iclass 16, count 0 2006.218.07:48:39.65#ibcon#about to read 5, iclass 16, count 0 2006.218.07:48:39.65#ibcon#read 5, iclass 16, count 0 2006.218.07:48:39.66#ibcon#about to read 6, iclass 16, count 0 2006.218.07:48:39.66#ibcon#read 6, iclass 16, count 0 2006.218.07:48:39.66#ibcon#end of sib2, iclass 16, count 0 2006.218.07:48:39.66#ibcon#*mode == 0, iclass 16, count 0 2006.218.07:48:39.66#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.218.07:48:39.66#ibcon#[26=FRQ=06,772.99\r\n] 2006.218.07:48:39.66#ibcon#*before write, iclass 16, count 0 2006.218.07:48:39.66#ibcon#enter sib2, iclass 16, count 0 2006.218.07:48:39.66#ibcon#flushed, iclass 16, count 0 2006.218.07:48:39.66#ibcon#about to write, iclass 16, count 0 2006.218.07:48:39.66#ibcon#wrote, iclass 16, count 0 2006.218.07:48:39.66#ibcon#about to read 3, iclass 16, count 0 2006.218.07:48:39.69#ibcon#read 3, iclass 16, count 0 2006.218.07:48:39.69#ibcon#about to read 4, iclass 16, count 0 2006.218.07:48:39.69#ibcon#read 4, iclass 16, count 0 2006.218.07:48:39.69#ibcon#about to read 5, iclass 16, count 0 2006.218.07:48:39.69#ibcon#read 5, iclass 16, count 0 2006.218.07:48:39.69#ibcon#about to read 6, iclass 16, count 0 2006.218.07:48:39.70#ibcon#read 6, iclass 16, count 0 2006.218.07:48:39.70#ibcon#end of sib2, iclass 16, count 0 2006.218.07:48:39.70#ibcon#*after write, iclass 16, count 0 2006.218.07:48:39.70#ibcon#*before return 0, iclass 16, count 0 2006.218.07:48:39.70#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.218.07:48:39.70#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.218.07:48:39.70#ibcon#about to clear, iclass 16 cls_cnt 0 2006.218.07:48:39.70#ibcon#cleared, iclass 16 cls_cnt 0 2006.218.07:48:39.70$vc4f8/va=6,6 2006.218.07:48:39.70#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.218.07:48:39.70#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.218.07:48:39.70#ibcon#ireg 11 cls_cnt 2 2006.218.07:48:39.70#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.218.07:48:39.75#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.218.07:48:39.75#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.218.07:48:39.75#ibcon#enter wrdev, iclass 18, count 2 2006.218.07:48:39.75#ibcon#first serial, iclass 18, count 2 2006.218.07:48:39.75#ibcon#enter sib2, iclass 18, count 2 2006.218.07:48:39.75#ibcon#flushed, iclass 18, count 2 2006.218.07:48:39.76#ibcon#about to write, iclass 18, count 2 2006.218.07:48:39.76#ibcon#wrote, iclass 18, count 2 2006.218.07:48:39.76#ibcon#about to read 3, iclass 18, count 2 2006.218.07:48:39.77#ibcon#read 3, iclass 18, count 2 2006.218.07:48:39.77#ibcon#about to read 4, iclass 18, count 2 2006.218.07:48:39.77#ibcon#read 4, iclass 18, count 2 2006.218.07:48:39.77#ibcon#about to read 5, iclass 18, count 2 2006.218.07:48:39.77#ibcon#read 5, iclass 18, count 2 2006.218.07:48:39.78#ibcon#about to read 6, iclass 18, count 2 2006.218.07:48:39.78#ibcon#read 6, iclass 18, count 2 2006.218.07:48:39.78#ibcon#end of sib2, iclass 18, count 2 2006.218.07:48:39.78#ibcon#*mode == 0, iclass 18, count 2 2006.218.07:48:39.78#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.218.07:48:39.78#ibcon#[25=AT06-06\r\n] 2006.218.07:48:39.78#ibcon#*before write, iclass 18, count 2 2006.218.07:48:39.78#ibcon#enter sib2, iclass 18, count 2 2006.218.07:48:39.78#ibcon#flushed, iclass 18, count 2 2006.218.07:48:39.78#ibcon#about to write, iclass 18, count 2 2006.218.07:48:39.78#ibcon#wrote, iclass 18, count 2 2006.218.07:48:39.78#ibcon#about to read 3, iclass 18, count 2 2006.218.07:48:39.80#ibcon#read 3, iclass 18, count 2 2006.218.07:48:39.80#ibcon#about to read 4, iclass 18, count 2 2006.218.07:48:39.80#ibcon#read 4, iclass 18, count 2 2006.218.07:48:39.80#ibcon#about to read 5, iclass 18, count 2 2006.218.07:48:39.80#ibcon#read 5, iclass 18, count 2 2006.218.07:48:39.81#ibcon#about to read 6, iclass 18, count 2 2006.218.07:48:39.81#ibcon#read 6, iclass 18, count 2 2006.218.07:48:39.81#ibcon#end of sib2, iclass 18, count 2 2006.218.07:48:39.81#ibcon#*after write, iclass 18, count 2 2006.218.07:48:39.81#ibcon#*before return 0, iclass 18, count 2 2006.218.07:48:39.81#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.218.07:48:39.81#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.218.07:48:39.81#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.218.07:48:39.81#ibcon#ireg 7 cls_cnt 0 2006.218.07:48:39.81#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.218.07:48:39.92#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.218.07:48:39.92#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.218.07:48:39.92#ibcon#enter wrdev, iclass 18, count 0 2006.218.07:48:39.92#ibcon#first serial, iclass 18, count 0 2006.218.07:48:39.92#ibcon#enter sib2, iclass 18, count 0 2006.218.07:48:39.92#ibcon#flushed, iclass 18, count 0 2006.218.07:48:39.92#ibcon#about to write, iclass 18, count 0 2006.218.07:48:39.93#ibcon#wrote, iclass 18, count 0 2006.218.07:48:39.93#ibcon#about to read 3, iclass 18, count 0 2006.218.07:48:39.94#ibcon#read 3, iclass 18, count 0 2006.218.07:48:39.94#ibcon#about to read 4, iclass 18, count 0 2006.218.07:48:39.94#ibcon#read 4, iclass 18, count 0 2006.218.07:48:39.94#ibcon#about to read 5, iclass 18, count 0 2006.218.07:48:39.94#ibcon#read 5, iclass 18, count 0 2006.218.07:48:39.95#ibcon#about to read 6, iclass 18, count 0 2006.218.07:48:39.95#ibcon#read 6, iclass 18, count 0 2006.218.07:48:39.95#ibcon#end of sib2, iclass 18, count 0 2006.218.07:48:39.95#ibcon#*mode == 0, iclass 18, count 0 2006.218.07:48:39.95#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.218.07:48:39.95#ibcon#[25=USB\r\n] 2006.218.07:48:39.95#ibcon#*before write, iclass 18, count 0 2006.218.07:48:39.95#ibcon#enter sib2, iclass 18, count 0 2006.218.07:48:39.95#ibcon#flushed, iclass 18, count 0 2006.218.07:48:39.95#ibcon#about to write, iclass 18, count 0 2006.218.07:48:39.95#ibcon#wrote, iclass 18, count 0 2006.218.07:48:39.95#ibcon#about to read 3, iclass 18, count 0 2006.218.07:48:39.97#ibcon#read 3, iclass 18, count 0 2006.218.07:48:39.97#ibcon#about to read 4, iclass 18, count 0 2006.218.07:48:39.97#ibcon#read 4, iclass 18, count 0 2006.218.07:48:39.97#ibcon#about to read 5, iclass 18, count 0 2006.218.07:48:39.97#ibcon#read 5, iclass 18, count 0 2006.218.07:48:39.98#ibcon#about to read 6, iclass 18, count 0 2006.218.07:48:39.98#ibcon#read 6, iclass 18, count 0 2006.218.07:48:39.98#ibcon#end of sib2, iclass 18, count 0 2006.218.07:48:39.98#ibcon#*after write, iclass 18, count 0 2006.218.07:48:39.98#ibcon#*before return 0, iclass 18, count 0 2006.218.07:48:39.98#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.218.07:48:39.98#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.218.07:48:39.98#ibcon#about to clear, iclass 18 cls_cnt 0 2006.218.07:48:39.98#ibcon#cleared, iclass 18 cls_cnt 0 2006.218.07:48:39.98$vc4f8/valo=7,832.99 2006.218.07:48:39.98#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.218.07:48:39.98#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.218.07:48:39.98#ibcon#ireg 17 cls_cnt 0 2006.218.07:48:39.98#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.218.07:48:39.98#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.218.07:48:39.98#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.218.07:48:39.98#ibcon#enter wrdev, iclass 20, count 0 2006.218.07:48:39.98#ibcon#first serial, iclass 20, count 0 2006.218.07:48:39.98#ibcon#enter sib2, iclass 20, count 0 2006.218.07:48:39.98#ibcon#flushed, iclass 20, count 0 2006.218.07:48:39.98#ibcon#about to write, iclass 20, count 0 2006.218.07:48:39.98#ibcon#wrote, iclass 20, count 0 2006.218.07:48:39.98#ibcon#about to read 3, iclass 20, count 0 2006.218.07:48:39.99#ibcon#read 3, iclass 20, count 0 2006.218.07:48:39.99#ibcon#about to read 4, iclass 20, count 0 2006.218.07:48:39.99#ibcon#read 4, iclass 20, count 0 2006.218.07:48:39.99#ibcon#about to read 5, iclass 20, count 0 2006.218.07:48:39.99#ibcon#read 5, iclass 20, count 0 2006.218.07:48:40.00#ibcon#about to read 6, iclass 20, count 0 2006.218.07:48:40.00#ibcon#read 6, iclass 20, count 0 2006.218.07:48:40.00#ibcon#end of sib2, iclass 20, count 0 2006.218.07:48:40.00#ibcon#*mode == 0, iclass 20, count 0 2006.218.07:48:40.00#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.218.07:48:40.00#ibcon#[26=FRQ=07,832.99\r\n] 2006.218.07:48:40.00#ibcon#*before write, iclass 20, count 0 2006.218.07:48:40.00#ibcon#enter sib2, iclass 20, count 0 2006.218.07:48:40.00#ibcon#flushed, iclass 20, count 0 2006.218.07:48:40.00#ibcon#about to write, iclass 20, count 0 2006.218.07:48:40.00#ibcon#wrote, iclass 20, count 0 2006.218.07:48:40.00#ibcon#about to read 3, iclass 20, count 0 2006.218.07:48:40.03#ibcon#read 3, iclass 20, count 0 2006.218.07:48:40.03#ibcon#about to read 4, iclass 20, count 0 2006.218.07:48:40.03#ibcon#read 4, iclass 20, count 0 2006.218.07:48:40.03#ibcon#about to read 5, iclass 20, count 0 2006.218.07:48:40.03#ibcon#read 5, iclass 20, count 0 2006.218.07:48:40.04#ibcon#about to read 6, iclass 20, count 0 2006.218.07:48:40.04#ibcon#read 6, iclass 20, count 0 2006.218.07:48:40.04#ibcon#end of sib2, iclass 20, count 0 2006.218.07:48:40.04#ibcon#*after write, iclass 20, count 0 2006.218.07:48:40.04#ibcon#*before return 0, iclass 20, count 0 2006.218.07:48:40.04#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.218.07:48:40.04#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.218.07:48:40.04#ibcon#about to clear, iclass 20 cls_cnt 0 2006.218.07:48:40.04#ibcon#cleared, iclass 20 cls_cnt 0 2006.218.07:48:40.04$vc4f8/va=7,6 2006.218.07:48:40.04#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.218.07:48:40.04#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.218.07:48:40.04#ibcon#ireg 11 cls_cnt 2 2006.218.07:48:40.04#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.218.07:48:40.09#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.218.07:48:40.09#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.218.07:48:40.09#ibcon#enter wrdev, iclass 22, count 2 2006.218.07:48:40.09#ibcon#first serial, iclass 22, count 2 2006.218.07:48:40.09#ibcon#enter sib2, iclass 22, count 2 2006.218.07:48:40.09#ibcon#flushed, iclass 22, count 2 2006.218.07:48:40.09#ibcon#about to write, iclass 22, count 2 2006.218.07:48:40.10#ibcon#wrote, iclass 22, count 2 2006.218.07:48:40.10#ibcon#about to read 3, iclass 22, count 2 2006.218.07:48:40.11#ibcon#read 3, iclass 22, count 2 2006.218.07:48:40.11#ibcon#about to read 4, iclass 22, count 2 2006.218.07:48:40.11#ibcon#read 4, iclass 22, count 2 2006.218.07:48:40.11#ibcon#about to read 5, iclass 22, count 2 2006.218.07:48:40.11#ibcon#read 5, iclass 22, count 2 2006.218.07:48:40.11#ibcon#about to read 6, iclass 22, count 2 2006.218.07:48:40.12#ibcon#read 6, iclass 22, count 2 2006.218.07:48:40.12#ibcon#end of sib2, iclass 22, count 2 2006.218.07:48:40.12#ibcon#*mode == 0, iclass 22, count 2 2006.218.07:48:40.12#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.218.07:48:40.12#ibcon#[25=AT07-06\r\n] 2006.218.07:48:40.12#ibcon#*before write, iclass 22, count 2 2006.218.07:48:40.12#ibcon#enter sib2, iclass 22, count 2 2006.218.07:48:40.12#ibcon#flushed, iclass 22, count 2 2006.218.07:48:40.12#ibcon#about to write, iclass 22, count 2 2006.218.07:48:40.12#ibcon#wrote, iclass 22, count 2 2006.218.07:48:40.12#ibcon#about to read 3, iclass 22, count 2 2006.218.07:48:40.14#ibcon#read 3, iclass 22, count 2 2006.218.07:48:40.14#ibcon#about to read 4, iclass 22, count 2 2006.218.07:48:40.14#ibcon#read 4, iclass 22, count 2 2006.218.07:48:40.14#ibcon#about to read 5, iclass 22, count 2 2006.218.07:48:40.14#ibcon#read 5, iclass 22, count 2 2006.218.07:48:40.15#ibcon#about to read 6, iclass 22, count 2 2006.218.07:48:40.15#ibcon#read 6, iclass 22, count 2 2006.218.07:48:40.15#ibcon#end of sib2, iclass 22, count 2 2006.218.07:48:40.15#ibcon#*after write, iclass 22, count 2 2006.218.07:48:40.15#ibcon#*before return 0, iclass 22, count 2 2006.218.07:48:40.15#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.218.07:48:40.15#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.218.07:48:40.15#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.218.07:48:40.15#ibcon#ireg 7 cls_cnt 0 2006.218.07:48:40.15#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.218.07:48:40.26#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.218.07:48:40.26#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.218.07:48:40.26#ibcon#enter wrdev, iclass 22, count 0 2006.218.07:48:40.26#ibcon#first serial, iclass 22, count 0 2006.218.07:48:40.26#ibcon#enter sib2, iclass 22, count 0 2006.218.07:48:40.26#ibcon#flushed, iclass 22, count 0 2006.218.07:48:40.26#ibcon#about to write, iclass 22, count 0 2006.218.07:48:40.27#ibcon#wrote, iclass 22, count 0 2006.218.07:48:40.27#ibcon#about to read 3, iclass 22, count 0 2006.218.07:48:40.28#ibcon#read 3, iclass 22, count 0 2006.218.07:48:40.28#ibcon#about to read 4, iclass 22, count 0 2006.218.07:48:40.28#ibcon#read 4, iclass 22, count 0 2006.218.07:48:40.28#ibcon#about to read 5, iclass 22, count 0 2006.218.07:48:40.28#ibcon#read 5, iclass 22, count 0 2006.218.07:48:40.29#ibcon#about to read 6, iclass 22, count 0 2006.218.07:48:40.29#ibcon#read 6, iclass 22, count 0 2006.218.07:48:40.29#ibcon#end of sib2, iclass 22, count 0 2006.218.07:48:40.29#ibcon#*mode == 0, iclass 22, count 0 2006.218.07:48:40.29#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.218.07:48:40.29#ibcon#[25=USB\r\n] 2006.218.07:48:40.29#ibcon#*before write, iclass 22, count 0 2006.218.07:48:40.29#ibcon#enter sib2, iclass 22, count 0 2006.218.07:48:40.29#ibcon#flushed, iclass 22, count 0 2006.218.07:48:40.29#ibcon#about to write, iclass 22, count 0 2006.218.07:48:40.29#ibcon#wrote, iclass 22, count 0 2006.218.07:48:40.29#ibcon#about to read 3, iclass 22, count 0 2006.218.07:48:40.31#ibcon#read 3, iclass 22, count 0 2006.218.07:48:40.31#ibcon#about to read 4, iclass 22, count 0 2006.218.07:48:40.31#ibcon#read 4, iclass 22, count 0 2006.218.07:48:40.31#ibcon#about to read 5, iclass 22, count 0 2006.218.07:48:40.31#ibcon#read 5, iclass 22, count 0 2006.218.07:48:40.32#ibcon#about to read 6, iclass 22, count 0 2006.218.07:48:40.32#ibcon#read 6, iclass 22, count 0 2006.218.07:48:40.32#ibcon#end of sib2, iclass 22, count 0 2006.218.07:48:40.32#ibcon#*after write, iclass 22, count 0 2006.218.07:48:40.32#ibcon#*before return 0, iclass 22, count 0 2006.218.07:48:40.32#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.218.07:48:40.32#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.218.07:48:40.32#ibcon#about to clear, iclass 22 cls_cnt 0 2006.218.07:48:40.32#ibcon#cleared, iclass 22 cls_cnt 0 2006.218.07:48:40.32$vc4f8/valo=8,852.99 2006.218.07:48:40.32#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.218.07:48:40.32#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.218.07:48:40.32#ibcon#ireg 17 cls_cnt 0 2006.218.07:48:40.32#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.218.07:48:40.32#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.218.07:48:40.32#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.218.07:48:40.32#ibcon#enter wrdev, iclass 24, count 0 2006.218.07:48:40.32#ibcon#first serial, iclass 24, count 0 2006.218.07:48:40.32#ibcon#enter sib2, iclass 24, count 0 2006.218.07:48:40.32#ibcon#flushed, iclass 24, count 0 2006.218.07:48:40.32#ibcon#about to write, iclass 24, count 0 2006.218.07:48:40.32#ibcon#wrote, iclass 24, count 0 2006.218.07:48:40.32#ibcon#about to read 3, iclass 24, count 0 2006.218.07:48:40.33#ibcon#read 3, iclass 24, count 0 2006.218.07:48:40.33#ibcon#about to read 4, iclass 24, count 0 2006.218.07:48:40.33#ibcon#read 4, iclass 24, count 0 2006.218.07:48:40.33#ibcon#about to read 5, iclass 24, count 0 2006.218.07:48:40.33#ibcon#read 5, iclass 24, count 0 2006.218.07:48:40.34#ibcon#about to read 6, iclass 24, count 0 2006.218.07:48:40.34#ibcon#read 6, iclass 24, count 0 2006.218.07:48:40.34#ibcon#end of sib2, iclass 24, count 0 2006.218.07:48:40.34#ibcon#*mode == 0, iclass 24, count 0 2006.218.07:48:40.34#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.218.07:48:40.34#ibcon#[26=FRQ=08,852.99\r\n] 2006.218.07:48:40.34#ibcon#*before write, iclass 24, count 0 2006.218.07:48:40.34#ibcon#enter sib2, iclass 24, count 0 2006.218.07:48:40.34#ibcon#flushed, iclass 24, count 0 2006.218.07:48:40.34#ibcon#about to write, iclass 24, count 0 2006.218.07:48:40.34#ibcon#wrote, iclass 24, count 0 2006.218.07:48:40.34#ibcon#about to read 3, iclass 24, count 0 2006.218.07:48:40.37#ibcon#read 3, iclass 24, count 0 2006.218.07:48:40.37#ibcon#about to read 4, iclass 24, count 0 2006.218.07:48:40.37#ibcon#read 4, iclass 24, count 0 2006.218.07:48:40.37#ibcon#about to read 5, iclass 24, count 0 2006.218.07:48:40.37#ibcon#read 5, iclass 24, count 0 2006.218.07:48:40.38#ibcon#about to read 6, iclass 24, count 0 2006.218.07:48:40.38#ibcon#read 6, iclass 24, count 0 2006.218.07:48:40.38#ibcon#end of sib2, iclass 24, count 0 2006.218.07:48:40.38#ibcon#*after write, iclass 24, count 0 2006.218.07:48:40.38#ibcon#*before return 0, iclass 24, count 0 2006.218.07:48:40.38#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.218.07:48:40.38#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.218.07:48:40.38#ibcon#about to clear, iclass 24 cls_cnt 0 2006.218.07:48:40.38#ibcon#cleared, iclass 24 cls_cnt 0 2006.218.07:48:40.38$vc4f8/va=8,7 2006.218.07:48:40.38#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.218.07:48:40.38#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.218.07:48:40.38#ibcon#ireg 11 cls_cnt 2 2006.218.07:48:40.38#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.218.07:48:40.44#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.218.07:48:40.44#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.218.07:48:40.44#ibcon#enter wrdev, iclass 26, count 2 2006.218.07:48:40.44#ibcon#first serial, iclass 26, count 2 2006.218.07:48:40.44#ibcon#enter sib2, iclass 26, count 2 2006.218.07:48:40.44#ibcon#flushed, iclass 26, count 2 2006.218.07:48:40.44#ibcon#about to write, iclass 26, count 2 2006.218.07:48:40.44#ibcon#wrote, iclass 26, count 2 2006.218.07:48:40.44#ibcon#about to read 3, iclass 26, count 2 2006.218.07:48:40.45#ibcon#read 3, iclass 26, count 2 2006.218.07:48:40.45#ibcon#about to read 4, iclass 26, count 2 2006.218.07:48:40.46#ibcon#read 4, iclass 26, count 2 2006.218.07:48:40.46#ibcon#about to read 5, iclass 26, count 2 2006.218.07:48:40.46#ibcon#read 5, iclass 26, count 2 2006.218.07:48:40.46#ibcon#about to read 6, iclass 26, count 2 2006.218.07:48:40.46#ibcon#read 6, iclass 26, count 2 2006.218.07:48:40.46#ibcon#end of sib2, iclass 26, count 2 2006.218.07:48:40.46#ibcon#*mode == 0, iclass 26, count 2 2006.218.07:48:40.46#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.218.07:48:40.46#ibcon#[25=AT08-07\r\n] 2006.218.07:48:40.46#ibcon#*before write, iclass 26, count 2 2006.218.07:48:40.46#ibcon#enter sib2, iclass 26, count 2 2006.218.07:48:40.46#ibcon#flushed, iclass 26, count 2 2006.218.07:48:40.46#ibcon#about to write, iclass 26, count 2 2006.218.07:48:40.46#ibcon#wrote, iclass 26, count 2 2006.218.07:48:40.46#ibcon#about to read 3, iclass 26, count 2 2006.218.07:48:40.48#ibcon#read 3, iclass 26, count 2 2006.218.07:48:40.48#ibcon#about to read 4, iclass 26, count 2 2006.218.07:48:40.48#ibcon#read 4, iclass 26, count 2 2006.218.07:48:40.49#ibcon#about to read 5, iclass 26, count 2 2006.218.07:48:40.49#ibcon#read 5, iclass 26, count 2 2006.218.07:48:40.49#ibcon#about to read 6, iclass 26, count 2 2006.218.07:48:40.49#ibcon#read 6, iclass 26, count 2 2006.218.07:48:40.49#ibcon#end of sib2, iclass 26, count 2 2006.218.07:48:40.49#ibcon#*after write, iclass 26, count 2 2006.218.07:48:40.49#ibcon#*before return 0, iclass 26, count 2 2006.218.07:48:40.49#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.218.07:48:40.49#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.218.07:48:40.49#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.218.07:48:40.49#ibcon#ireg 7 cls_cnt 0 2006.218.07:48:40.49#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.218.07:48:40.60#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.218.07:48:40.60#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.218.07:48:40.60#ibcon#enter wrdev, iclass 26, count 0 2006.218.07:48:40.60#ibcon#first serial, iclass 26, count 0 2006.218.07:48:40.60#ibcon#enter sib2, iclass 26, count 0 2006.218.07:48:40.60#ibcon#flushed, iclass 26, count 0 2006.218.07:48:40.61#ibcon#about to write, iclass 26, count 0 2006.218.07:48:40.61#ibcon#wrote, iclass 26, count 0 2006.218.07:48:40.61#ibcon#about to read 3, iclass 26, count 0 2006.218.07:48:40.62#ibcon#read 3, iclass 26, count 0 2006.218.07:48:40.62#ibcon#about to read 4, iclass 26, count 0 2006.218.07:48:40.62#ibcon#read 4, iclass 26, count 0 2006.218.07:48:40.62#ibcon#about to read 5, iclass 26, count 0 2006.218.07:48:40.62#ibcon#read 5, iclass 26, count 0 2006.218.07:48:40.62#ibcon#about to read 6, iclass 26, count 0 2006.218.07:48:40.63#ibcon#read 6, iclass 26, count 0 2006.218.07:48:40.63#ibcon#end of sib2, iclass 26, count 0 2006.218.07:48:40.63#ibcon#*mode == 0, iclass 26, count 0 2006.218.07:48:40.63#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.218.07:48:40.63#ibcon#[25=USB\r\n] 2006.218.07:48:40.63#ibcon#*before write, iclass 26, count 0 2006.218.07:48:40.63#ibcon#enter sib2, iclass 26, count 0 2006.218.07:48:40.63#ibcon#flushed, iclass 26, count 0 2006.218.07:48:40.63#ibcon#about to write, iclass 26, count 0 2006.218.07:48:40.63#ibcon#wrote, iclass 26, count 0 2006.218.07:48:40.63#ibcon#about to read 3, iclass 26, count 0 2006.218.07:48:40.65#ibcon#read 3, iclass 26, count 0 2006.218.07:48:40.65#ibcon#about to read 4, iclass 26, count 0 2006.218.07:48:40.65#ibcon#read 4, iclass 26, count 0 2006.218.07:48:40.65#ibcon#about to read 5, iclass 26, count 0 2006.218.07:48:40.65#ibcon#read 5, iclass 26, count 0 2006.218.07:48:40.65#ibcon#about to read 6, iclass 26, count 0 2006.218.07:48:40.66#ibcon#read 6, iclass 26, count 0 2006.218.07:48:40.66#ibcon#end of sib2, iclass 26, count 0 2006.218.07:48:40.66#ibcon#*after write, iclass 26, count 0 2006.218.07:48:40.66#ibcon#*before return 0, iclass 26, count 0 2006.218.07:48:40.66#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.218.07:48:40.66#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.218.07:48:40.66#ibcon#about to clear, iclass 26 cls_cnt 0 2006.218.07:48:40.66#ibcon#cleared, iclass 26 cls_cnt 0 2006.218.07:48:40.66$vc4f8/vblo=1,632.99 2006.218.07:48:40.66#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.218.07:48:40.66#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.218.07:48:40.66#ibcon#ireg 17 cls_cnt 0 2006.218.07:48:40.66#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.218.07:48:40.66#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.218.07:48:40.66#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.218.07:48:40.66#ibcon#enter wrdev, iclass 28, count 0 2006.218.07:48:40.66#ibcon#first serial, iclass 28, count 0 2006.218.07:48:40.66#ibcon#enter sib2, iclass 28, count 0 2006.218.07:48:40.66#ibcon#flushed, iclass 28, count 0 2006.218.07:48:40.66#ibcon#about to write, iclass 28, count 0 2006.218.07:48:40.66#ibcon#wrote, iclass 28, count 0 2006.218.07:48:40.66#ibcon#about to read 3, iclass 28, count 0 2006.218.07:48:40.67#ibcon#read 3, iclass 28, count 0 2006.218.07:48:40.67#ibcon#about to read 4, iclass 28, count 0 2006.218.07:48:40.67#ibcon#read 4, iclass 28, count 0 2006.218.07:48:40.67#ibcon#about to read 5, iclass 28, count 0 2006.218.07:48:40.67#ibcon#read 5, iclass 28, count 0 2006.218.07:48:40.68#ibcon#about to read 6, iclass 28, count 0 2006.218.07:48:40.68#ibcon#read 6, iclass 28, count 0 2006.218.07:48:40.68#ibcon#end of sib2, iclass 28, count 0 2006.218.07:48:40.68#ibcon#*mode == 0, iclass 28, count 0 2006.218.07:48:40.68#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.218.07:48:40.68#ibcon#[28=FRQ=01,632.99\r\n] 2006.218.07:48:40.68#ibcon#*before write, iclass 28, count 0 2006.218.07:48:40.68#ibcon#enter sib2, iclass 28, count 0 2006.218.07:48:40.68#ibcon#flushed, iclass 28, count 0 2006.218.07:48:40.68#ibcon#about to write, iclass 28, count 0 2006.218.07:48:40.68#ibcon#wrote, iclass 28, count 0 2006.218.07:48:40.68#ibcon#about to read 3, iclass 28, count 0 2006.218.07:48:40.71#ibcon#read 3, iclass 28, count 0 2006.218.07:48:40.71#ibcon#about to read 4, iclass 28, count 0 2006.218.07:48:40.71#ibcon#read 4, iclass 28, count 0 2006.218.07:48:40.71#ibcon#about to read 5, iclass 28, count 0 2006.218.07:48:40.72#ibcon#read 5, iclass 28, count 0 2006.218.07:48:40.72#ibcon#about to read 6, iclass 28, count 0 2006.218.07:48:40.72#ibcon#read 6, iclass 28, count 0 2006.218.07:48:40.72#ibcon#end of sib2, iclass 28, count 0 2006.218.07:48:40.72#ibcon#*after write, iclass 28, count 0 2006.218.07:48:40.72#ibcon#*before return 0, iclass 28, count 0 2006.218.07:48:40.72#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.218.07:48:40.72#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.218.07:48:40.72#ibcon#about to clear, iclass 28 cls_cnt 0 2006.218.07:48:40.72#ibcon#cleared, iclass 28 cls_cnt 0 2006.218.07:48:40.72$vc4f8/vb=1,4 2006.218.07:48:40.72#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.218.07:48:40.72#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.218.07:48:40.72#ibcon#ireg 11 cls_cnt 2 2006.218.07:48:40.72#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.218.07:48:40.72#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.218.07:48:40.72#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.218.07:48:40.72#ibcon#enter wrdev, iclass 30, count 2 2006.218.07:48:40.72#ibcon#first serial, iclass 30, count 2 2006.218.07:48:40.72#ibcon#enter sib2, iclass 30, count 2 2006.218.07:48:40.72#ibcon#flushed, iclass 30, count 2 2006.218.07:48:40.72#ibcon#about to write, iclass 30, count 2 2006.218.07:48:40.72#ibcon#wrote, iclass 30, count 2 2006.218.07:48:40.72#ibcon#about to read 3, iclass 30, count 2 2006.218.07:48:40.73#ibcon#read 3, iclass 30, count 2 2006.218.07:48:40.73#ibcon#about to read 4, iclass 30, count 2 2006.218.07:48:40.73#ibcon#read 4, iclass 30, count 2 2006.218.07:48:40.73#ibcon#about to read 5, iclass 30, count 2 2006.218.07:48:40.73#ibcon#read 5, iclass 30, count 2 2006.218.07:48:40.74#ibcon#about to read 6, iclass 30, count 2 2006.218.07:48:40.74#ibcon#read 6, iclass 30, count 2 2006.218.07:48:40.74#ibcon#end of sib2, iclass 30, count 2 2006.218.07:48:40.74#ibcon#*mode == 0, iclass 30, count 2 2006.218.07:48:40.74#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.218.07:48:40.74#ibcon#[27=AT01-04\r\n] 2006.218.07:48:40.74#ibcon#*before write, iclass 30, count 2 2006.218.07:48:40.74#ibcon#enter sib2, iclass 30, count 2 2006.218.07:48:40.74#ibcon#flushed, iclass 30, count 2 2006.218.07:48:40.74#ibcon#about to write, iclass 30, count 2 2006.218.07:48:40.74#ibcon#wrote, iclass 30, count 2 2006.218.07:48:40.74#ibcon#about to read 3, iclass 30, count 2 2006.218.07:48:40.76#ibcon#read 3, iclass 30, count 2 2006.218.07:48:40.76#ibcon#about to read 4, iclass 30, count 2 2006.218.07:48:40.76#ibcon#read 4, iclass 30, count 2 2006.218.07:48:40.76#ibcon#about to read 5, iclass 30, count 2 2006.218.07:48:40.76#ibcon#read 5, iclass 30, count 2 2006.218.07:48:40.77#ibcon#about to read 6, iclass 30, count 2 2006.218.07:48:40.77#ibcon#read 6, iclass 30, count 2 2006.218.07:48:40.77#ibcon#end of sib2, iclass 30, count 2 2006.218.07:48:40.77#ibcon#*after write, iclass 30, count 2 2006.218.07:48:40.77#ibcon#*before return 0, iclass 30, count 2 2006.218.07:48:40.77#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.218.07:48:40.77#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.218.07:48:40.77#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.218.07:48:40.77#ibcon#ireg 7 cls_cnt 0 2006.218.07:48:40.77#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.218.07:48:40.88#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.218.07:48:40.88#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.218.07:48:40.88#ibcon#enter wrdev, iclass 30, count 0 2006.218.07:48:40.88#ibcon#first serial, iclass 30, count 0 2006.218.07:48:40.88#ibcon#enter sib2, iclass 30, count 0 2006.218.07:48:40.88#ibcon#flushed, iclass 30, count 0 2006.218.07:48:40.88#ibcon#about to write, iclass 30, count 0 2006.218.07:48:40.89#ibcon#wrote, iclass 30, count 0 2006.218.07:48:40.89#ibcon#about to read 3, iclass 30, count 0 2006.218.07:48:40.90#ibcon#read 3, iclass 30, count 0 2006.218.07:48:40.90#ibcon#about to read 4, iclass 30, count 0 2006.218.07:48:40.90#ibcon#read 4, iclass 30, count 0 2006.218.07:48:40.90#ibcon#about to read 5, iclass 30, count 0 2006.218.07:48:40.90#ibcon#read 5, iclass 30, count 0 2006.218.07:48:40.90#ibcon#about to read 6, iclass 30, count 0 2006.218.07:48:40.91#ibcon#read 6, iclass 30, count 0 2006.218.07:48:40.91#ibcon#end of sib2, iclass 30, count 0 2006.218.07:48:40.91#ibcon#*mode == 0, iclass 30, count 0 2006.218.07:48:40.91#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.218.07:48:40.91#ibcon#[27=USB\r\n] 2006.218.07:48:40.91#ibcon#*before write, iclass 30, count 0 2006.218.07:48:40.91#ibcon#enter sib2, iclass 30, count 0 2006.218.07:48:40.91#ibcon#flushed, iclass 30, count 0 2006.218.07:48:40.91#ibcon#about to write, iclass 30, count 0 2006.218.07:48:40.91#ibcon#wrote, iclass 30, count 0 2006.218.07:48:40.91#ibcon#about to read 3, iclass 30, count 0 2006.218.07:48:40.93#ibcon#read 3, iclass 30, count 0 2006.218.07:48:40.93#ibcon#about to read 4, iclass 30, count 0 2006.218.07:48:40.93#ibcon#read 4, iclass 30, count 0 2006.218.07:48:40.93#ibcon#about to read 5, iclass 30, count 0 2006.218.07:48:40.93#ibcon#read 5, iclass 30, count 0 2006.218.07:48:40.93#ibcon#about to read 6, iclass 30, count 0 2006.218.07:48:40.94#ibcon#read 6, iclass 30, count 0 2006.218.07:48:40.94#ibcon#end of sib2, iclass 30, count 0 2006.218.07:48:40.94#ibcon#*after write, iclass 30, count 0 2006.218.07:48:40.94#ibcon#*before return 0, iclass 30, count 0 2006.218.07:48:40.94#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.218.07:48:40.94#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.218.07:48:40.94#ibcon#about to clear, iclass 30 cls_cnt 0 2006.218.07:48:40.94#ibcon#cleared, iclass 30 cls_cnt 0 2006.218.07:48:40.94$vc4f8/vblo=2,640.99 2006.218.07:48:40.94#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.218.07:48:40.94#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.218.07:48:40.94#ibcon#ireg 17 cls_cnt 0 2006.218.07:48:40.94#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.218.07:48:40.94#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.218.07:48:40.94#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.218.07:48:40.94#ibcon#enter wrdev, iclass 32, count 0 2006.218.07:48:40.94#ibcon#first serial, iclass 32, count 0 2006.218.07:48:40.94#ibcon#enter sib2, iclass 32, count 0 2006.218.07:48:40.94#ibcon#flushed, iclass 32, count 0 2006.218.07:48:40.94#ibcon#about to write, iclass 32, count 0 2006.218.07:48:40.94#ibcon#wrote, iclass 32, count 0 2006.218.07:48:40.94#ibcon#about to read 3, iclass 32, count 0 2006.218.07:48:40.95#ibcon#read 3, iclass 32, count 0 2006.218.07:48:40.95#ibcon#about to read 4, iclass 32, count 0 2006.218.07:48:40.95#ibcon#read 4, iclass 32, count 0 2006.218.07:48:40.95#ibcon#about to read 5, iclass 32, count 0 2006.218.07:48:40.95#ibcon#read 5, iclass 32, count 0 2006.218.07:48:40.95#ibcon#about to read 6, iclass 32, count 0 2006.218.07:48:40.96#ibcon#read 6, iclass 32, count 0 2006.218.07:48:40.96#ibcon#end of sib2, iclass 32, count 0 2006.218.07:48:40.96#ibcon#*mode == 0, iclass 32, count 0 2006.218.07:48:40.96#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.218.07:48:40.96#ibcon#[28=FRQ=02,640.99\r\n] 2006.218.07:48:40.96#ibcon#*before write, iclass 32, count 0 2006.218.07:48:40.96#ibcon#enter sib2, iclass 32, count 0 2006.218.07:48:40.96#ibcon#flushed, iclass 32, count 0 2006.218.07:48:40.96#ibcon#about to write, iclass 32, count 0 2006.218.07:48:40.96#ibcon#wrote, iclass 32, count 0 2006.218.07:48:40.96#ibcon#about to read 3, iclass 32, count 0 2006.218.07:48:40.99#ibcon#read 3, iclass 32, count 0 2006.218.07:48:40.99#ibcon#about to read 4, iclass 32, count 0 2006.218.07:48:40.99#ibcon#read 4, iclass 32, count 0 2006.218.07:48:40.99#ibcon#about to read 5, iclass 32, count 0 2006.218.07:48:40.99#ibcon#read 5, iclass 32, count 0 2006.218.07:48:41.00#ibcon#about to read 6, iclass 32, count 0 2006.218.07:48:41.00#ibcon#read 6, iclass 32, count 0 2006.218.07:48:41.00#ibcon#end of sib2, iclass 32, count 0 2006.218.07:48:41.00#ibcon#*after write, iclass 32, count 0 2006.218.07:48:41.00#ibcon#*before return 0, iclass 32, count 0 2006.218.07:48:41.00#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.218.07:48:41.00#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.218.07:48:41.00#ibcon#about to clear, iclass 32 cls_cnt 0 2006.218.07:48:41.00#ibcon#cleared, iclass 32 cls_cnt 0 2006.218.07:48:41.00$vc4f8/vb=2,4 2006.218.07:48:41.00#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.218.07:48:41.00#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.218.07:48:41.00#ibcon#ireg 11 cls_cnt 2 2006.218.07:48:41.00#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.218.07:48:41.05#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.218.07:48:41.05#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.218.07:48:41.05#ibcon#enter wrdev, iclass 34, count 2 2006.218.07:48:41.05#ibcon#first serial, iclass 34, count 2 2006.218.07:48:41.05#ibcon#enter sib2, iclass 34, count 2 2006.218.07:48:41.05#ibcon#flushed, iclass 34, count 2 2006.218.07:48:41.05#ibcon#about to write, iclass 34, count 2 2006.218.07:48:41.06#ibcon#wrote, iclass 34, count 2 2006.218.07:48:41.06#ibcon#about to read 3, iclass 34, count 2 2006.218.07:48:41.07#ibcon#read 3, iclass 34, count 2 2006.218.07:48:41.07#ibcon#about to read 4, iclass 34, count 2 2006.218.07:48:41.07#ibcon#read 4, iclass 34, count 2 2006.218.07:48:41.07#ibcon#about to read 5, iclass 34, count 2 2006.218.07:48:41.07#ibcon#read 5, iclass 34, count 2 2006.218.07:48:41.08#ibcon#about to read 6, iclass 34, count 2 2006.218.07:48:41.08#ibcon#read 6, iclass 34, count 2 2006.218.07:48:41.08#ibcon#end of sib2, iclass 34, count 2 2006.218.07:48:41.08#ibcon#*mode == 0, iclass 34, count 2 2006.218.07:48:41.08#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.218.07:48:41.08#ibcon#[27=AT02-04\r\n] 2006.218.07:48:41.08#ibcon#*before write, iclass 34, count 2 2006.218.07:48:41.08#ibcon#enter sib2, iclass 34, count 2 2006.218.07:48:41.08#ibcon#flushed, iclass 34, count 2 2006.218.07:48:41.08#ibcon#about to write, iclass 34, count 2 2006.218.07:48:41.08#ibcon#wrote, iclass 34, count 2 2006.218.07:48:41.08#ibcon#about to read 3, iclass 34, count 2 2006.218.07:48:41.10#ibcon#read 3, iclass 34, count 2 2006.218.07:48:41.10#ibcon#about to read 4, iclass 34, count 2 2006.218.07:48:41.10#ibcon#read 4, iclass 34, count 2 2006.218.07:48:41.10#ibcon#about to read 5, iclass 34, count 2 2006.218.07:48:41.10#ibcon#read 5, iclass 34, count 2 2006.218.07:48:41.11#ibcon#about to read 6, iclass 34, count 2 2006.218.07:48:41.11#ibcon#read 6, iclass 34, count 2 2006.218.07:48:41.11#ibcon#end of sib2, iclass 34, count 2 2006.218.07:48:41.11#ibcon#*after write, iclass 34, count 2 2006.218.07:48:41.11#ibcon#*before return 0, iclass 34, count 2 2006.218.07:48:41.11#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.218.07:48:41.11#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.218.07:48:41.11#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.218.07:48:41.11#ibcon#ireg 7 cls_cnt 0 2006.218.07:48:41.11#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.218.07:48:41.22#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.218.07:48:41.22#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.218.07:48:41.22#ibcon#enter wrdev, iclass 34, count 0 2006.218.07:48:41.22#ibcon#first serial, iclass 34, count 0 2006.218.07:48:41.22#ibcon#enter sib2, iclass 34, count 0 2006.218.07:48:41.22#ibcon#flushed, iclass 34, count 0 2006.218.07:48:41.22#ibcon#about to write, iclass 34, count 0 2006.218.07:48:41.23#ibcon#wrote, iclass 34, count 0 2006.218.07:48:41.23#ibcon#about to read 3, iclass 34, count 0 2006.218.07:48:41.24#ibcon#read 3, iclass 34, count 0 2006.218.07:48:41.24#ibcon#about to read 4, iclass 34, count 0 2006.218.07:48:41.24#ibcon#read 4, iclass 34, count 0 2006.218.07:48:41.24#ibcon#about to read 5, iclass 34, count 0 2006.218.07:48:41.24#ibcon#read 5, iclass 34, count 0 2006.218.07:48:41.24#ibcon#about to read 6, iclass 34, count 0 2006.218.07:48:41.25#ibcon#read 6, iclass 34, count 0 2006.218.07:48:41.25#ibcon#end of sib2, iclass 34, count 0 2006.218.07:48:41.25#ibcon#*mode == 0, iclass 34, count 0 2006.218.07:48:41.25#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.218.07:48:41.25#ibcon#[27=USB\r\n] 2006.218.07:48:41.25#ibcon#*before write, iclass 34, count 0 2006.218.07:48:41.25#ibcon#enter sib2, iclass 34, count 0 2006.218.07:48:41.25#ibcon#flushed, iclass 34, count 0 2006.218.07:48:41.25#ibcon#about to write, iclass 34, count 0 2006.218.07:48:41.25#ibcon#wrote, iclass 34, count 0 2006.218.07:48:41.25#ibcon#about to read 3, iclass 34, count 0 2006.218.07:48:41.27#ibcon#read 3, iclass 34, count 0 2006.218.07:48:41.27#ibcon#about to read 4, iclass 34, count 0 2006.218.07:48:41.27#ibcon#read 4, iclass 34, count 0 2006.218.07:48:41.27#ibcon#about to read 5, iclass 34, count 0 2006.218.07:48:41.27#ibcon#read 5, iclass 34, count 0 2006.218.07:48:41.27#ibcon#about to read 6, iclass 34, count 0 2006.218.07:48:41.28#ibcon#read 6, iclass 34, count 0 2006.218.07:48:41.28#ibcon#end of sib2, iclass 34, count 0 2006.218.07:48:41.28#ibcon#*after write, iclass 34, count 0 2006.218.07:48:41.28#ibcon#*before return 0, iclass 34, count 0 2006.218.07:48:41.28#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.218.07:48:41.28#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.218.07:48:41.28#ibcon#about to clear, iclass 34 cls_cnt 0 2006.218.07:48:41.28#ibcon#cleared, iclass 34 cls_cnt 0 2006.218.07:48:41.28$vc4f8/vblo=3,656.99 2006.218.07:48:41.28#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.218.07:48:41.28#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.218.07:48:41.28#ibcon#ireg 17 cls_cnt 0 2006.218.07:48:41.28#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.218.07:48:41.28#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.218.07:48:41.28#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.218.07:48:41.28#ibcon#enter wrdev, iclass 36, count 0 2006.218.07:48:41.28#ibcon#first serial, iclass 36, count 0 2006.218.07:48:41.28#ibcon#enter sib2, iclass 36, count 0 2006.218.07:48:41.28#ibcon#flushed, iclass 36, count 0 2006.218.07:48:41.28#ibcon#about to write, iclass 36, count 0 2006.218.07:48:41.28#ibcon#wrote, iclass 36, count 0 2006.218.07:48:41.28#ibcon#about to read 3, iclass 36, count 0 2006.218.07:48:41.30#ibcon#read 3, iclass 36, count 0 2006.218.07:48:41.30#ibcon#about to read 4, iclass 36, count 0 2006.218.07:48:41.30#ibcon#read 4, iclass 36, count 0 2006.218.07:48:41.30#ibcon#about to read 5, iclass 36, count 0 2006.218.07:48:41.30#ibcon#read 5, iclass 36, count 0 2006.218.07:48:41.30#ibcon#about to read 6, iclass 36, count 0 2006.218.07:48:41.30#ibcon#read 6, iclass 36, count 0 2006.218.07:48:41.30#ibcon#end of sib2, iclass 36, count 0 2006.218.07:48:41.30#ibcon#*mode == 0, iclass 36, count 0 2006.218.07:48:41.30#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.218.07:48:41.30#ibcon#[28=FRQ=03,656.99\r\n] 2006.218.07:48:41.30#ibcon#*before write, iclass 36, count 0 2006.218.07:48:41.30#ibcon#enter sib2, iclass 36, count 0 2006.218.07:48:41.30#ibcon#flushed, iclass 36, count 0 2006.218.07:48:41.30#ibcon#about to write, iclass 36, count 0 2006.218.07:48:41.30#ibcon#wrote, iclass 36, count 0 2006.218.07:48:41.30#ibcon#about to read 3, iclass 36, count 0 2006.218.07:48:41.34#ibcon#read 3, iclass 36, count 0 2006.218.07:48:41.34#ibcon#about to read 4, iclass 36, count 0 2006.218.07:48:41.34#ibcon#read 4, iclass 36, count 0 2006.218.07:48:41.35#ibcon#about to read 5, iclass 36, count 0 2006.218.07:48:41.35#ibcon#read 5, iclass 36, count 0 2006.218.07:48:41.35#ibcon#about to read 6, iclass 36, count 0 2006.218.07:48:41.35#ibcon#read 6, iclass 36, count 0 2006.218.07:48:41.35#ibcon#end of sib2, iclass 36, count 0 2006.218.07:48:41.35#ibcon#*after write, iclass 36, count 0 2006.218.07:48:41.35#ibcon#*before return 0, iclass 36, count 0 2006.218.07:48:41.35#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.218.07:48:41.35#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.218.07:48:41.35#ibcon#about to clear, iclass 36 cls_cnt 0 2006.218.07:48:41.35#ibcon#cleared, iclass 36 cls_cnt 0 2006.218.07:48:41.35$vc4f8/vb=3,4 2006.218.07:48:41.35#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.218.07:48:41.35#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.218.07:48:41.35#ibcon#ireg 11 cls_cnt 2 2006.218.07:48:41.35#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.218.07:48:41.40#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.218.07:48:41.40#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.218.07:48:41.40#ibcon#enter wrdev, iclass 38, count 2 2006.218.07:48:41.40#ibcon#first serial, iclass 38, count 2 2006.218.07:48:41.40#ibcon#enter sib2, iclass 38, count 2 2006.218.07:48:41.40#ibcon#flushed, iclass 38, count 2 2006.218.07:48:41.40#ibcon#about to write, iclass 38, count 2 2006.218.07:48:41.40#ibcon#wrote, iclass 38, count 2 2006.218.07:48:41.40#ibcon#about to read 3, iclass 38, count 2 2006.218.07:48:41.41#ibcon#read 3, iclass 38, count 2 2006.218.07:48:41.41#ibcon#about to read 4, iclass 38, count 2 2006.218.07:48:41.41#ibcon#read 4, iclass 38, count 2 2006.218.07:48:41.41#ibcon#about to read 5, iclass 38, count 2 2006.218.07:48:41.41#ibcon#read 5, iclass 38, count 2 2006.218.07:48:41.41#ibcon#about to read 6, iclass 38, count 2 2006.218.07:48:41.42#ibcon#read 6, iclass 38, count 2 2006.218.07:48:41.42#ibcon#end of sib2, iclass 38, count 2 2006.218.07:48:41.42#ibcon#*mode == 0, iclass 38, count 2 2006.218.07:48:41.42#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.218.07:48:41.42#ibcon#[27=AT03-04\r\n] 2006.218.07:48:41.42#ibcon#*before write, iclass 38, count 2 2006.218.07:48:41.42#ibcon#enter sib2, iclass 38, count 2 2006.218.07:48:41.42#ibcon#flushed, iclass 38, count 2 2006.218.07:48:41.42#ibcon#about to write, iclass 38, count 2 2006.218.07:48:41.42#ibcon#wrote, iclass 38, count 2 2006.218.07:48:41.42#ibcon#about to read 3, iclass 38, count 2 2006.218.07:48:41.44#ibcon#read 3, iclass 38, count 2 2006.218.07:48:41.44#ibcon#about to read 4, iclass 38, count 2 2006.218.07:48:41.44#ibcon#read 4, iclass 38, count 2 2006.218.07:48:41.45#ibcon#about to read 5, iclass 38, count 2 2006.218.07:48:41.45#ibcon#read 5, iclass 38, count 2 2006.218.07:48:41.45#ibcon#about to read 6, iclass 38, count 2 2006.218.07:48:41.45#ibcon#read 6, iclass 38, count 2 2006.218.07:48:41.45#ibcon#end of sib2, iclass 38, count 2 2006.218.07:48:41.45#ibcon#*after write, iclass 38, count 2 2006.218.07:48:41.45#ibcon#*before return 0, iclass 38, count 2 2006.218.07:48:41.45#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.218.07:48:41.45#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.218.07:48:41.45#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.218.07:48:41.45#ibcon#ireg 7 cls_cnt 0 2006.218.07:48:41.45#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.218.07:48:41.56#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.218.07:48:41.56#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.218.07:48:41.56#ibcon#enter wrdev, iclass 38, count 0 2006.218.07:48:41.56#ibcon#first serial, iclass 38, count 0 2006.218.07:48:41.56#ibcon#enter sib2, iclass 38, count 0 2006.218.07:48:41.56#ibcon#flushed, iclass 38, count 0 2006.218.07:48:41.56#ibcon#about to write, iclass 38, count 0 2006.218.07:48:41.57#ibcon#wrote, iclass 38, count 0 2006.218.07:48:41.57#ibcon#about to read 3, iclass 38, count 0 2006.218.07:48:41.58#ibcon#read 3, iclass 38, count 0 2006.218.07:48:41.58#ibcon#about to read 4, iclass 38, count 0 2006.218.07:48:41.58#ibcon#read 4, iclass 38, count 0 2006.218.07:48:41.58#ibcon#about to read 5, iclass 38, count 0 2006.218.07:48:41.58#ibcon#read 5, iclass 38, count 0 2006.218.07:48:41.58#ibcon#about to read 6, iclass 38, count 0 2006.218.07:48:41.59#ibcon#read 6, iclass 38, count 0 2006.218.07:48:41.59#ibcon#end of sib2, iclass 38, count 0 2006.218.07:48:41.59#ibcon#*mode == 0, iclass 38, count 0 2006.218.07:48:41.59#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.218.07:48:41.59#ibcon#[27=USB\r\n] 2006.218.07:48:41.59#ibcon#*before write, iclass 38, count 0 2006.218.07:48:41.59#ibcon#enter sib2, iclass 38, count 0 2006.218.07:48:41.59#ibcon#flushed, iclass 38, count 0 2006.218.07:48:41.59#ibcon#about to write, iclass 38, count 0 2006.218.07:48:41.59#ibcon#wrote, iclass 38, count 0 2006.218.07:48:41.59#ibcon#about to read 3, iclass 38, count 0 2006.218.07:48:41.61#ibcon#read 3, iclass 38, count 0 2006.218.07:48:41.61#ibcon#about to read 4, iclass 38, count 0 2006.218.07:48:41.61#ibcon#read 4, iclass 38, count 0 2006.218.07:48:41.61#ibcon#about to read 5, iclass 38, count 0 2006.218.07:48:41.61#ibcon#read 5, iclass 38, count 0 2006.218.07:48:41.61#ibcon#about to read 6, iclass 38, count 0 2006.218.07:48:41.62#ibcon#read 6, iclass 38, count 0 2006.218.07:48:41.62#ibcon#end of sib2, iclass 38, count 0 2006.218.07:48:41.62#ibcon#*after write, iclass 38, count 0 2006.218.07:48:41.62#ibcon#*before return 0, iclass 38, count 0 2006.218.07:48:41.62#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.218.07:48:41.62#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.218.07:48:41.62#ibcon#about to clear, iclass 38 cls_cnt 0 2006.218.07:48:41.62#ibcon#cleared, iclass 38 cls_cnt 0 2006.218.07:48:41.62$vc4f8/vblo=4,712.99 2006.218.07:48:41.62#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.218.07:48:41.62#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.218.07:48:41.62#ibcon#ireg 17 cls_cnt 0 2006.218.07:48:41.62#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.218.07:48:41.62#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.218.07:48:41.62#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.218.07:48:41.62#ibcon#enter wrdev, iclass 40, count 0 2006.218.07:48:41.62#ibcon#first serial, iclass 40, count 0 2006.218.07:48:41.62#ibcon#enter sib2, iclass 40, count 0 2006.218.07:48:41.62#ibcon#flushed, iclass 40, count 0 2006.218.07:48:41.62#ibcon#about to write, iclass 40, count 0 2006.218.07:48:41.62#ibcon#wrote, iclass 40, count 0 2006.218.07:48:41.62#ibcon#about to read 3, iclass 40, count 0 2006.218.07:48:41.63#ibcon#read 3, iclass 40, count 0 2006.218.07:48:41.63#ibcon#about to read 4, iclass 40, count 0 2006.218.07:48:41.63#ibcon#read 4, iclass 40, count 0 2006.218.07:48:41.63#ibcon#about to read 5, iclass 40, count 0 2006.218.07:48:41.63#ibcon#read 5, iclass 40, count 0 2006.218.07:48:41.64#ibcon#about to read 6, iclass 40, count 0 2006.218.07:48:41.64#ibcon#read 6, iclass 40, count 0 2006.218.07:48:41.64#ibcon#end of sib2, iclass 40, count 0 2006.218.07:48:41.64#ibcon#*mode == 0, iclass 40, count 0 2006.218.07:48:41.64#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.218.07:48:41.64#ibcon#[28=FRQ=04,712.99\r\n] 2006.218.07:48:41.64#ibcon#*before write, iclass 40, count 0 2006.218.07:48:41.64#ibcon#enter sib2, iclass 40, count 0 2006.218.07:48:41.64#ibcon#flushed, iclass 40, count 0 2006.218.07:48:41.64#ibcon#about to write, iclass 40, count 0 2006.218.07:48:41.64#ibcon#wrote, iclass 40, count 0 2006.218.07:48:41.64#ibcon#about to read 3, iclass 40, count 0 2006.218.07:48:41.67#ibcon#read 3, iclass 40, count 0 2006.218.07:48:41.67#ibcon#about to read 4, iclass 40, count 0 2006.218.07:48:41.67#ibcon#read 4, iclass 40, count 0 2006.218.07:48:41.68#ibcon#about to read 5, iclass 40, count 0 2006.218.07:48:41.68#ibcon#read 5, iclass 40, count 0 2006.218.07:48:41.68#ibcon#about to read 6, iclass 40, count 0 2006.218.07:48:41.68#ibcon#read 6, iclass 40, count 0 2006.218.07:48:41.68#ibcon#end of sib2, iclass 40, count 0 2006.218.07:48:41.68#ibcon#*after write, iclass 40, count 0 2006.218.07:48:41.68#ibcon#*before return 0, iclass 40, count 0 2006.218.07:48:41.68#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.218.07:48:41.68#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.218.07:48:41.68#ibcon#about to clear, iclass 40 cls_cnt 0 2006.218.07:48:41.68#ibcon#cleared, iclass 40 cls_cnt 0 2006.218.07:48:41.68$vc4f8/vb=4,4 2006.218.07:48:41.68#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.218.07:48:41.68#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.218.07:48:41.68#ibcon#ireg 11 cls_cnt 2 2006.218.07:48:41.68#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.218.07:48:41.73#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.218.07:48:41.73#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.218.07:48:41.73#ibcon#enter wrdev, iclass 4, count 2 2006.218.07:48:41.73#ibcon#first serial, iclass 4, count 2 2006.218.07:48:41.73#ibcon#enter sib2, iclass 4, count 2 2006.218.07:48:41.73#ibcon#flushed, iclass 4, count 2 2006.218.07:48:41.73#ibcon#about to write, iclass 4, count 2 2006.218.07:48:41.74#ibcon#wrote, iclass 4, count 2 2006.218.07:48:41.74#ibcon#about to read 3, iclass 4, count 2 2006.218.07:48:41.75#ibcon#read 3, iclass 4, count 2 2006.218.07:48:41.75#ibcon#about to read 4, iclass 4, count 2 2006.218.07:48:41.75#ibcon#read 4, iclass 4, count 2 2006.218.07:48:41.75#ibcon#about to read 5, iclass 4, count 2 2006.218.07:48:41.75#ibcon#read 5, iclass 4, count 2 2006.218.07:48:41.75#ibcon#about to read 6, iclass 4, count 2 2006.218.07:48:41.76#ibcon#read 6, iclass 4, count 2 2006.218.07:48:41.76#ibcon#end of sib2, iclass 4, count 2 2006.218.07:48:41.76#ibcon#*mode == 0, iclass 4, count 2 2006.218.07:48:41.76#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.218.07:48:41.76#ibcon#[27=AT04-04\r\n] 2006.218.07:48:41.76#ibcon#*before write, iclass 4, count 2 2006.218.07:48:41.76#ibcon#enter sib2, iclass 4, count 2 2006.218.07:48:41.76#ibcon#flushed, iclass 4, count 2 2006.218.07:48:41.76#ibcon#about to write, iclass 4, count 2 2006.218.07:48:41.76#ibcon#wrote, iclass 4, count 2 2006.218.07:48:41.76#ibcon#about to read 3, iclass 4, count 2 2006.218.07:48:41.78#ibcon#read 3, iclass 4, count 2 2006.218.07:48:41.78#ibcon#about to read 4, iclass 4, count 2 2006.218.07:48:41.78#ibcon#read 4, iclass 4, count 2 2006.218.07:48:41.78#ibcon#about to read 5, iclass 4, count 2 2006.218.07:48:41.78#ibcon#read 5, iclass 4, count 2 2006.218.07:48:41.78#ibcon#about to read 6, iclass 4, count 2 2006.218.07:48:41.79#ibcon#read 6, iclass 4, count 2 2006.218.07:48:41.79#ibcon#end of sib2, iclass 4, count 2 2006.218.07:48:41.79#ibcon#*after write, iclass 4, count 2 2006.218.07:48:41.79#ibcon#*before return 0, iclass 4, count 2 2006.218.07:48:41.79#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.218.07:48:41.79#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.218.07:48:41.79#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.218.07:48:41.79#ibcon#ireg 7 cls_cnt 0 2006.218.07:48:41.79#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.218.07:48:41.90#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.218.07:48:41.90#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.218.07:48:41.90#ibcon#enter wrdev, iclass 4, count 0 2006.218.07:48:41.90#ibcon#first serial, iclass 4, count 0 2006.218.07:48:41.90#ibcon#enter sib2, iclass 4, count 0 2006.218.07:48:41.90#ibcon#flushed, iclass 4, count 0 2006.218.07:48:41.90#ibcon#about to write, iclass 4, count 0 2006.218.07:48:41.91#ibcon#wrote, iclass 4, count 0 2006.218.07:48:41.91#ibcon#about to read 3, iclass 4, count 0 2006.218.07:48:41.92#ibcon#read 3, iclass 4, count 0 2006.218.07:48:41.92#ibcon#about to read 4, iclass 4, count 0 2006.218.07:48:41.92#ibcon#read 4, iclass 4, count 0 2006.218.07:48:41.92#ibcon#about to read 5, iclass 4, count 0 2006.218.07:48:41.92#ibcon#read 5, iclass 4, count 0 2006.218.07:48:41.92#ibcon#about to read 6, iclass 4, count 0 2006.218.07:48:41.93#ibcon#read 6, iclass 4, count 0 2006.218.07:48:41.93#ibcon#end of sib2, iclass 4, count 0 2006.218.07:48:41.93#ibcon#*mode == 0, iclass 4, count 0 2006.218.07:48:41.93#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.218.07:48:41.93#ibcon#[27=USB\r\n] 2006.218.07:48:41.93#ibcon#*before write, iclass 4, count 0 2006.218.07:48:41.93#ibcon#enter sib2, iclass 4, count 0 2006.218.07:48:41.93#ibcon#flushed, iclass 4, count 0 2006.218.07:48:41.93#ibcon#about to write, iclass 4, count 0 2006.218.07:48:41.93#ibcon#wrote, iclass 4, count 0 2006.218.07:48:41.93#ibcon#about to read 3, iclass 4, count 0 2006.218.07:48:41.95#ibcon#read 3, iclass 4, count 0 2006.218.07:48:41.95#ibcon#about to read 4, iclass 4, count 0 2006.218.07:48:41.95#ibcon#read 4, iclass 4, count 0 2006.218.07:48:41.95#ibcon#about to read 5, iclass 4, count 0 2006.218.07:48:41.95#ibcon#read 5, iclass 4, count 0 2006.218.07:48:41.95#ibcon#about to read 6, iclass 4, count 0 2006.218.07:48:41.96#ibcon#read 6, iclass 4, count 0 2006.218.07:48:41.96#ibcon#end of sib2, iclass 4, count 0 2006.218.07:48:41.96#ibcon#*after write, iclass 4, count 0 2006.218.07:48:41.96#ibcon#*before return 0, iclass 4, count 0 2006.218.07:48:41.96#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.218.07:48:41.96#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.218.07:48:41.96#ibcon#about to clear, iclass 4 cls_cnt 0 2006.218.07:48:41.96#ibcon#cleared, iclass 4 cls_cnt 0 2006.218.07:48:41.96$vc4f8/vblo=5,744.99 2006.218.07:48:41.96#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.218.07:48:41.96#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.218.07:48:41.96#ibcon#ireg 17 cls_cnt 0 2006.218.07:48:41.96#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.218.07:48:41.96#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.218.07:48:41.96#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.218.07:48:41.96#ibcon#enter wrdev, iclass 6, count 0 2006.218.07:48:41.96#ibcon#first serial, iclass 6, count 0 2006.218.07:48:41.96#ibcon#enter sib2, iclass 6, count 0 2006.218.07:48:41.96#ibcon#flushed, iclass 6, count 0 2006.218.07:48:41.96#ibcon#about to write, iclass 6, count 0 2006.218.07:48:41.96#ibcon#wrote, iclass 6, count 0 2006.218.07:48:41.96#ibcon#about to read 3, iclass 6, count 0 2006.218.07:48:41.97#ibcon#read 3, iclass 6, count 0 2006.218.07:48:41.97#ibcon#about to read 4, iclass 6, count 0 2006.218.07:48:41.97#ibcon#read 4, iclass 6, count 0 2006.218.07:48:41.97#ibcon#about to read 5, iclass 6, count 0 2006.218.07:48:41.97#ibcon#read 5, iclass 6, count 0 2006.218.07:48:41.97#ibcon#about to read 6, iclass 6, count 0 2006.218.07:48:41.98#ibcon#read 6, iclass 6, count 0 2006.218.07:48:41.98#ibcon#end of sib2, iclass 6, count 0 2006.218.07:48:41.98#ibcon#*mode == 0, iclass 6, count 0 2006.218.07:48:41.98#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.218.07:48:41.98#ibcon#[28=FRQ=05,744.99\r\n] 2006.218.07:48:41.98#ibcon#*before write, iclass 6, count 0 2006.218.07:48:41.98#ibcon#enter sib2, iclass 6, count 0 2006.218.07:48:41.98#ibcon#flushed, iclass 6, count 0 2006.218.07:48:41.98#ibcon#about to write, iclass 6, count 0 2006.218.07:48:41.98#ibcon#wrote, iclass 6, count 0 2006.218.07:48:41.98#ibcon#about to read 3, iclass 6, count 0 2006.218.07:48:42.01#ibcon#read 3, iclass 6, count 0 2006.218.07:48:42.01#ibcon#about to read 4, iclass 6, count 0 2006.218.07:48:42.01#ibcon#read 4, iclass 6, count 0 2006.218.07:48:42.01#ibcon#about to read 5, iclass 6, count 0 2006.218.07:48:42.01#ibcon#read 5, iclass 6, count 0 2006.218.07:48:42.02#ibcon#about to read 6, iclass 6, count 0 2006.218.07:48:42.02#ibcon#read 6, iclass 6, count 0 2006.218.07:48:42.02#ibcon#end of sib2, iclass 6, count 0 2006.218.07:48:42.02#ibcon#*after write, iclass 6, count 0 2006.218.07:48:42.02#ibcon#*before return 0, iclass 6, count 0 2006.218.07:48:42.02#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.218.07:48:42.02#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.218.07:48:42.02#ibcon#about to clear, iclass 6 cls_cnt 0 2006.218.07:48:42.02#ibcon#cleared, iclass 6 cls_cnt 0 2006.218.07:48:42.02$vc4f8/vb=5,4 2006.218.07:48:42.02#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.218.07:48:42.02#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.218.07:48:42.02#ibcon#ireg 11 cls_cnt 2 2006.218.07:48:42.02#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.218.07:48:42.08#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.218.07:48:42.08#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.218.07:48:42.08#ibcon#enter wrdev, iclass 10, count 2 2006.218.07:48:42.08#ibcon#first serial, iclass 10, count 2 2006.218.07:48:42.08#ibcon#enter sib2, iclass 10, count 2 2006.218.07:48:42.08#ibcon#flushed, iclass 10, count 2 2006.218.07:48:42.08#ibcon#about to write, iclass 10, count 2 2006.218.07:48:42.08#ibcon#wrote, iclass 10, count 2 2006.218.07:48:42.08#ibcon#about to read 3, iclass 10, count 2 2006.218.07:48:42.09#ibcon#read 3, iclass 10, count 2 2006.218.07:48:42.09#ibcon#about to read 4, iclass 10, count 2 2006.218.07:48:42.10#ibcon#read 4, iclass 10, count 2 2006.218.07:48:42.10#ibcon#about to read 5, iclass 10, count 2 2006.218.07:48:42.10#ibcon#read 5, iclass 10, count 2 2006.218.07:48:42.10#ibcon#about to read 6, iclass 10, count 2 2006.218.07:48:42.10#ibcon#read 6, iclass 10, count 2 2006.218.07:48:42.10#ibcon#end of sib2, iclass 10, count 2 2006.218.07:48:42.10#ibcon#*mode == 0, iclass 10, count 2 2006.218.07:48:42.10#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.218.07:48:42.10#ibcon#[27=AT05-04\r\n] 2006.218.07:48:42.10#ibcon#*before write, iclass 10, count 2 2006.218.07:48:42.10#ibcon#enter sib2, iclass 10, count 2 2006.218.07:48:42.10#ibcon#flushed, iclass 10, count 2 2006.218.07:48:42.10#ibcon#about to write, iclass 10, count 2 2006.218.07:48:42.10#ibcon#wrote, iclass 10, count 2 2006.218.07:48:42.10#ibcon#about to read 3, iclass 10, count 2 2006.218.07:48:42.12#ibcon#read 3, iclass 10, count 2 2006.218.07:48:42.12#ibcon#about to read 4, iclass 10, count 2 2006.218.07:48:42.12#ibcon#read 4, iclass 10, count 2 2006.218.07:48:42.13#ibcon#about to read 5, iclass 10, count 2 2006.218.07:48:42.13#ibcon#read 5, iclass 10, count 2 2006.218.07:48:42.13#ibcon#about to read 6, iclass 10, count 2 2006.218.07:48:42.13#ibcon#read 6, iclass 10, count 2 2006.218.07:48:42.13#ibcon#end of sib2, iclass 10, count 2 2006.218.07:48:42.13#ibcon#*after write, iclass 10, count 2 2006.218.07:48:42.13#ibcon#*before return 0, iclass 10, count 2 2006.218.07:48:42.13#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.218.07:48:42.13#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.218.07:48:42.13#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.218.07:48:42.13#ibcon#ireg 7 cls_cnt 0 2006.218.07:48:42.13#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.218.07:48:42.24#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.218.07:48:42.24#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.218.07:48:42.24#ibcon#enter wrdev, iclass 10, count 0 2006.218.07:48:42.24#ibcon#first serial, iclass 10, count 0 2006.218.07:48:42.24#ibcon#enter sib2, iclass 10, count 0 2006.218.07:48:42.24#ibcon#flushed, iclass 10, count 0 2006.218.07:48:42.24#ibcon#about to write, iclass 10, count 0 2006.218.07:48:42.25#ibcon#wrote, iclass 10, count 0 2006.218.07:48:42.25#ibcon#about to read 3, iclass 10, count 0 2006.218.07:48:42.26#ibcon#read 3, iclass 10, count 0 2006.218.07:48:42.26#ibcon#about to read 4, iclass 10, count 0 2006.218.07:48:42.26#ibcon#read 4, iclass 10, count 0 2006.218.07:48:42.26#ibcon#about to read 5, iclass 10, count 0 2006.218.07:48:42.26#ibcon#read 5, iclass 10, count 0 2006.218.07:48:42.26#ibcon#about to read 6, iclass 10, count 0 2006.218.07:48:42.27#ibcon#read 6, iclass 10, count 0 2006.218.07:48:42.27#ibcon#end of sib2, iclass 10, count 0 2006.218.07:48:42.27#ibcon#*mode == 0, iclass 10, count 0 2006.218.07:48:42.27#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.218.07:48:42.27#ibcon#[27=USB\r\n] 2006.218.07:48:42.27#ibcon#*before write, iclass 10, count 0 2006.218.07:48:42.27#ibcon#enter sib2, iclass 10, count 0 2006.218.07:48:42.27#ibcon#flushed, iclass 10, count 0 2006.218.07:48:42.27#ibcon#about to write, iclass 10, count 0 2006.218.07:48:42.27#ibcon#wrote, iclass 10, count 0 2006.218.07:48:42.27#ibcon#about to read 3, iclass 10, count 0 2006.218.07:48:42.29#ibcon#read 3, iclass 10, count 0 2006.218.07:48:42.29#ibcon#about to read 4, iclass 10, count 0 2006.218.07:48:42.29#ibcon#read 4, iclass 10, count 0 2006.218.07:48:42.29#ibcon#about to read 5, iclass 10, count 0 2006.218.07:48:42.29#ibcon#read 5, iclass 10, count 0 2006.218.07:48:42.29#ibcon#about to read 6, iclass 10, count 0 2006.218.07:48:42.30#ibcon#read 6, iclass 10, count 0 2006.218.07:48:42.30#ibcon#end of sib2, iclass 10, count 0 2006.218.07:48:42.30#ibcon#*after write, iclass 10, count 0 2006.218.07:48:42.30#ibcon#*before return 0, iclass 10, count 0 2006.218.07:48:42.30#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.218.07:48:42.30#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.218.07:48:42.30#ibcon#about to clear, iclass 10 cls_cnt 0 2006.218.07:48:42.30#ibcon#cleared, iclass 10 cls_cnt 0 2006.218.07:48:42.30$vc4f8/vblo=6,752.99 2006.218.07:48:42.30#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.218.07:48:42.30#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.218.07:48:42.30#ibcon#ireg 17 cls_cnt 0 2006.218.07:48:42.30#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.218.07:48:42.30#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.218.07:48:42.30#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.218.07:48:42.30#ibcon#enter wrdev, iclass 12, count 0 2006.218.07:48:42.30#ibcon#first serial, iclass 12, count 0 2006.218.07:48:42.30#ibcon#enter sib2, iclass 12, count 0 2006.218.07:48:42.30#ibcon#flushed, iclass 12, count 0 2006.218.07:48:42.30#ibcon#about to write, iclass 12, count 0 2006.218.07:48:42.30#ibcon#wrote, iclass 12, count 0 2006.218.07:48:42.30#ibcon#about to read 3, iclass 12, count 0 2006.218.07:48:42.31#ibcon#read 3, iclass 12, count 0 2006.218.07:48:42.31#ibcon#about to read 4, iclass 12, count 0 2006.218.07:48:42.31#ibcon#read 4, iclass 12, count 0 2006.218.07:48:42.31#ibcon#about to read 5, iclass 12, count 0 2006.218.07:48:42.31#ibcon#read 5, iclass 12, count 0 2006.218.07:48:42.31#ibcon#about to read 6, iclass 12, count 0 2006.218.07:48:42.32#ibcon#read 6, iclass 12, count 0 2006.218.07:48:42.32#ibcon#end of sib2, iclass 12, count 0 2006.218.07:48:42.32#ibcon#*mode == 0, iclass 12, count 0 2006.218.07:48:42.32#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.218.07:48:42.32#ibcon#[28=FRQ=06,752.99\r\n] 2006.218.07:48:42.32#ibcon#*before write, iclass 12, count 0 2006.218.07:48:42.32#ibcon#enter sib2, iclass 12, count 0 2006.218.07:48:42.32#ibcon#flushed, iclass 12, count 0 2006.218.07:48:42.32#ibcon#about to write, iclass 12, count 0 2006.218.07:48:42.32#ibcon#wrote, iclass 12, count 0 2006.218.07:48:42.32#ibcon#about to read 3, iclass 12, count 0 2006.218.07:48:42.35#ibcon#read 3, iclass 12, count 0 2006.218.07:48:42.35#ibcon#about to read 4, iclass 12, count 0 2006.218.07:48:42.35#ibcon#read 4, iclass 12, count 0 2006.218.07:48:42.35#ibcon#about to read 5, iclass 12, count 0 2006.218.07:48:42.35#ibcon#read 5, iclass 12, count 0 2006.218.07:48:42.35#ibcon#about to read 6, iclass 12, count 0 2006.218.07:48:42.36#ibcon#read 6, iclass 12, count 0 2006.218.07:48:42.36#ibcon#end of sib2, iclass 12, count 0 2006.218.07:48:42.36#ibcon#*after write, iclass 12, count 0 2006.218.07:48:42.36#ibcon#*before return 0, iclass 12, count 0 2006.218.07:48:42.36#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.218.07:48:42.36#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.218.07:48:42.36#ibcon#about to clear, iclass 12 cls_cnt 0 2006.218.07:48:42.36#ibcon#cleared, iclass 12 cls_cnt 0 2006.218.07:48:42.36$vc4f8/vb=6,4 2006.218.07:48:42.36#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.218.07:48:42.36#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.218.07:48:42.36#ibcon#ireg 11 cls_cnt 2 2006.218.07:48:42.36#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.218.07:48:42.41#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.218.07:48:42.41#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.218.07:48:42.41#ibcon#enter wrdev, iclass 14, count 2 2006.218.07:48:42.41#ibcon#first serial, iclass 14, count 2 2006.218.07:48:42.41#ibcon#enter sib2, iclass 14, count 2 2006.218.07:48:42.41#ibcon#flushed, iclass 14, count 2 2006.218.07:48:42.41#ibcon#about to write, iclass 14, count 2 2006.218.07:48:42.42#ibcon#wrote, iclass 14, count 2 2006.218.07:48:42.42#ibcon#about to read 3, iclass 14, count 2 2006.218.07:48:42.43#ibcon#read 3, iclass 14, count 2 2006.218.07:48:42.43#ibcon#about to read 4, iclass 14, count 2 2006.218.07:48:42.43#ibcon#read 4, iclass 14, count 2 2006.218.07:48:42.43#ibcon#about to read 5, iclass 14, count 2 2006.218.07:48:42.43#ibcon#read 5, iclass 14, count 2 2006.218.07:48:42.43#ibcon#about to read 6, iclass 14, count 2 2006.218.07:48:42.44#ibcon#read 6, iclass 14, count 2 2006.218.07:48:42.44#ibcon#end of sib2, iclass 14, count 2 2006.218.07:48:42.44#ibcon#*mode == 0, iclass 14, count 2 2006.218.07:48:42.44#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.218.07:48:42.44#ibcon#[27=AT06-04\r\n] 2006.218.07:48:42.44#ibcon#*before write, iclass 14, count 2 2006.218.07:48:42.44#ibcon#enter sib2, iclass 14, count 2 2006.218.07:48:42.44#ibcon#flushed, iclass 14, count 2 2006.218.07:48:42.44#ibcon#about to write, iclass 14, count 2 2006.218.07:48:42.44#ibcon#wrote, iclass 14, count 2 2006.218.07:48:42.44#ibcon#about to read 3, iclass 14, count 2 2006.218.07:48:42.46#ibcon#read 3, iclass 14, count 2 2006.218.07:48:42.46#ibcon#about to read 4, iclass 14, count 2 2006.218.07:48:42.46#ibcon#read 4, iclass 14, count 2 2006.218.07:48:42.46#ibcon#about to read 5, iclass 14, count 2 2006.218.07:48:42.46#ibcon#read 5, iclass 14, count 2 2006.218.07:48:42.46#ibcon#about to read 6, iclass 14, count 2 2006.218.07:48:42.47#ibcon#read 6, iclass 14, count 2 2006.218.07:48:42.47#ibcon#end of sib2, iclass 14, count 2 2006.218.07:48:42.47#ibcon#*after write, iclass 14, count 2 2006.218.07:48:42.47#ibcon#*before return 0, iclass 14, count 2 2006.218.07:48:42.47#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.218.07:48:42.47#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.218.07:48:42.47#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.218.07:48:42.47#ibcon#ireg 7 cls_cnt 0 2006.218.07:48:42.47#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.218.07:48:42.58#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.218.07:48:42.58#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.218.07:48:42.58#ibcon#enter wrdev, iclass 14, count 0 2006.218.07:48:42.58#ibcon#first serial, iclass 14, count 0 2006.218.07:48:42.58#ibcon#enter sib2, iclass 14, count 0 2006.218.07:48:42.58#ibcon#flushed, iclass 14, count 0 2006.218.07:48:42.58#ibcon#about to write, iclass 14, count 0 2006.218.07:48:42.59#ibcon#wrote, iclass 14, count 0 2006.218.07:48:42.59#ibcon#about to read 3, iclass 14, count 0 2006.218.07:48:42.60#ibcon#read 3, iclass 14, count 0 2006.218.07:48:42.60#ibcon#about to read 4, iclass 14, count 0 2006.218.07:48:42.60#ibcon#read 4, iclass 14, count 0 2006.218.07:48:42.60#ibcon#about to read 5, iclass 14, count 0 2006.218.07:48:42.60#ibcon#read 5, iclass 14, count 0 2006.218.07:48:42.60#ibcon#about to read 6, iclass 14, count 0 2006.218.07:48:42.61#ibcon#read 6, iclass 14, count 0 2006.218.07:48:42.61#ibcon#end of sib2, iclass 14, count 0 2006.218.07:48:42.61#ibcon#*mode == 0, iclass 14, count 0 2006.218.07:48:42.61#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.218.07:48:42.61#ibcon#[27=USB\r\n] 2006.218.07:48:42.61#ibcon#*before write, iclass 14, count 0 2006.218.07:48:42.61#ibcon#enter sib2, iclass 14, count 0 2006.218.07:48:42.61#ibcon#flushed, iclass 14, count 0 2006.218.07:48:42.61#ibcon#about to write, iclass 14, count 0 2006.218.07:48:42.61#ibcon#wrote, iclass 14, count 0 2006.218.07:48:42.61#ibcon#about to read 3, iclass 14, count 0 2006.218.07:48:42.63#ibcon#read 3, iclass 14, count 0 2006.218.07:48:42.63#ibcon#about to read 4, iclass 14, count 0 2006.218.07:48:42.63#ibcon#read 4, iclass 14, count 0 2006.218.07:48:42.63#ibcon#about to read 5, iclass 14, count 0 2006.218.07:48:42.63#ibcon#read 5, iclass 14, count 0 2006.218.07:48:42.63#ibcon#about to read 6, iclass 14, count 0 2006.218.07:48:42.64#ibcon#read 6, iclass 14, count 0 2006.218.07:48:42.64#ibcon#end of sib2, iclass 14, count 0 2006.218.07:48:42.64#ibcon#*after write, iclass 14, count 0 2006.218.07:48:42.64#ibcon#*before return 0, iclass 14, count 0 2006.218.07:48:42.64#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.218.07:48:42.64#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.218.07:48:42.64#ibcon#about to clear, iclass 14 cls_cnt 0 2006.218.07:48:42.64#ibcon#cleared, iclass 14 cls_cnt 0 2006.218.07:48:42.64$vc4f8/vabw=wide 2006.218.07:48:42.64#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.218.07:48:42.64#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.218.07:48:42.64#ibcon#ireg 8 cls_cnt 0 2006.218.07:48:42.64#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.218.07:48:42.64#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.218.07:48:42.64#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.218.07:48:42.64#ibcon#enter wrdev, iclass 16, count 0 2006.218.07:48:42.64#ibcon#first serial, iclass 16, count 0 2006.218.07:48:42.64#ibcon#enter sib2, iclass 16, count 0 2006.218.07:48:42.64#ibcon#flushed, iclass 16, count 0 2006.218.07:48:42.64#ibcon#about to write, iclass 16, count 0 2006.218.07:48:42.64#ibcon#wrote, iclass 16, count 0 2006.218.07:48:42.64#ibcon#about to read 3, iclass 16, count 0 2006.218.07:48:42.65#ibcon#read 3, iclass 16, count 0 2006.218.07:48:42.65#ibcon#about to read 4, iclass 16, count 0 2006.218.07:48:42.65#ibcon#read 4, iclass 16, count 0 2006.218.07:48:42.65#ibcon#about to read 5, iclass 16, count 0 2006.218.07:48:42.65#ibcon#read 5, iclass 16, count 0 2006.218.07:48:42.65#ibcon#about to read 6, iclass 16, count 0 2006.218.07:48:42.66#ibcon#read 6, iclass 16, count 0 2006.218.07:48:42.66#ibcon#end of sib2, iclass 16, count 0 2006.218.07:48:42.66#ibcon#*mode == 0, iclass 16, count 0 2006.218.07:48:42.66#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.218.07:48:42.66#ibcon#[25=BW32\r\n] 2006.218.07:48:42.66#ibcon#*before write, iclass 16, count 0 2006.218.07:48:42.66#ibcon#enter sib2, iclass 16, count 0 2006.218.07:48:42.66#ibcon#flushed, iclass 16, count 0 2006.218.07:48:42.66#ibcon#about to write, iclass 16, count 0 2006.218.07:48:42.66#ibcon#wrote, iclass 16, count 0 2006.218.07:48:42.66#ibcon#about to read 3, iclass 16, count 0 2006.218.07:48:42.68#ibcon#read 3, iclass 16, count 0 2006.218.07:48:42.68#ibcon#about to read 4, iclass 16, count 0 2006.218.07:48:42.68#ibcon#read 4, iclass 16, count 0 2006.218.07:48:42.68#ibcon#about to read 5, iclass 16, count 0 2006.218.07:48:42.69#ibcon#read 5, iclass 16, count 0 2006.218.07:48:42.69#ibcon#about to read 6, iclass 16, count 0 2006.218.07:48:42.69#ibcon#read 6, iclass 16, count 0 2006.218.07:48:42.69#ibcon#end of sib2, iclass 16, count 0 2006.218.07:48:42.69#ibcon#*after write, iclass 16, count 0 2006.218.07:48:42.69#ibcon#*before return 0, iclass 16, count 0 2006.218.07:48:42.69#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.218.07:48:42.69#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.218.07:48:42.69#ibcon#about to clear, iclass 16 cls_cnt 0 2006.218.07:48:42.69#ibcon#cleared, iclass 16 cls_cnt 0 2006.218.07:48:42.69$vc4f8/vbbw=wide 2006.218.07:48:42.69#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.218.07:48:42.69#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.218.07:48:42.69#ibcon#ireg 8 cls_cnt 0 2006.218.07:48:42.69#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.218.07:48:42.75#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.218.07:48:42.75#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.218.07:48:42.75#ibcon#enter wrdev, iclass 18, count 0 2006.218.07:48:42.75#ibcon#first serial, iclass 18, count 0 2006.218.07:48:42.75#ibcon#enter sib2, iclass 18, count 0 2006.218.07:48:42.75#ibcon#flushed, iclass 18, count 0 2006.218.07:48:42.75#ibcon#about to write, iclass 18, count 0 2006.218.07:48:42.76#ibcon#wrote, iclass 18, count 0 2006.218.07:48:42.76#ibcon#about to read 3, iclass 18, count 0 2006.218.07:48:42.77#ibcon#read 3, iclass 18, count 0 2006.218.07:48:42.77#ibcon#about to read 4, iclass 18, count 0 2006.218.07:48:42.77#ibcon#read 4, iclass 18, count 0 2006.218.07:48:42.77#ibcon#about to read 5, iclass 18, count 0 2006.218.07:48:42.77#ibcon#read 5, iclass 18, count 0 2006.218.07:48:42.77#ibcon#about to read 6, iclass 18, count 0 2006.218.07:48:42.78#ibcon#read 6, iclass 18, count 0 2006.218.07:48:42.78#ibcon#end of sib2, iclass 18, count 0 2006.218.07:48:42.78#ibcon#*mode == 0, iclass 18, count 0 2006.218.07:48:42.78#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.218.07:48:42.78#ibcon#[27=BW32\r\n] 2006.218.07:48:42.78#ibcon#*before write, iclass 18, count 0 2006.218.07:48:42.78#ibcon#enter sib2, iclass 18, count 0 2006.218.07:48:42.78#ibcon#flushed, iclass 18, count 0 2006.218.07:48:42.78#ibcon#about to write, iclass 18, count 0 2006.218.07:48:42.78#ibcon#wrote, iclass 18, count 0 2006.218.07:48:42.78#ibcon#about to read 3, iclass 18, count 0 2006.218.07:48:42.80#ibcon#read 3, iclass 18, count 0 2006.218.07:48:42.80#ibcon#about to read 4, iclass 18, count 0 2006.218.07:48:42.80#ibcon#read 4, iclass 18, count 0 2006.218.07:48:42.80#ibcon#about to read 5, iclass 18, count 0 2006.218.07:48:42.80#ibcon#read 5, iclass 18, count 0 2006.218.07:48:42.80#ibcon#about to read 6, iclass 18, count 0 2006.218.07:48:42.81#ibcon#read 6, iclass 18, count 0 2006.218.07:48:42.81#ibcon#end of sib2, iclass 18, count 0 2006.218.07:48:42.81#ibcon#*after write, iclass 18, count 0 2006.218.07:48:42.81#ibcon#*before return 0, iclass 18, count 0 2006.218.07:48:42.81#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.218.07:48:42.81#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.218.07:48:42.81#ibcon#about to clear, iclass 18 cls_cnt 0 2006.218.07:48:42.81#ibcon#cleared, iclass 18 cls_cnt 0 2006.218.07:48:42.81$4f8m12a/ifd4f 2006.218.07:48:42.81$ifd4f/lo= 2006.218.07:48:42.81$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.218.07:48:42.81$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.218.07:48:42.81$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.218.07:48:42.81$ifd4f/patch= 2006.218.07:48:42.81$ifd4f/patch=lo1,a1,a2,a3,a4 2006.218.07:48:42.81$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.218.07:48:42.81$ifd4f/patch=lo3,a5,a6,a7,a8 2006.218.07:48:42.81$4f8m12a/"form=m,16.000,1:2 2006.218.07:48:42.81$4f8m12a/"tpicd 2006.218.07:48:42.81$4f8m12a/echo=off 2006.218.07:48:42.81$4f8m12a/xlog=off 2006.218.07:48:42.81:!2006.218.07:49:10 2006.218.07:48:51.14#trakl#Source acquired 2006.218.07:48:51.15#flagr#flagr/antenna,acquired 2006.218.07:49:10.02:preob 2006.218.07:49:11.15/onsource/TRACKING 2006.218.07:49:11.15:!2006.218.07:49:20 2006.218.07:49:20.02:data_valid=on 2006.218.07:49:20.02:midob 2006.218.07:49:21.15/onsource/TRACKING 2006.218.07:49:21.15/wx/31.20,1007.4,72 2006.218.07:49:21.21/cable/+6.3863E-03 2006.218.07:49:22.30/va/01,05,usb,yes,38,40 2006.218.07:49:22.30/va/02,04,usb,yes,35,37 2006.218.07:49:22.30/va/03,04,usb,yes,33,34 2006.218.07:49:22.30/va/04,04,usb,yes,37,40 2006.218.07:49:22.30/va/05,07,usb,yes,40,42 2006.218.07:49:22.30/va/06,06,usb,yes,39,39 2006.218.07:49:22.30/va/07,06,usb,yes,39,39 2006.218.07:49:22.30/va/08,07,usb,yes,37,37 2006.218.07:49:22.53/valo/01,532.99,yes,locked 2006.218.07:49:22.53/valo/02,572.99,yes,locked 2006.218.07:49:22.53/valo/03,672.99,yes,locked 2006.218.07:49:22.53/valo/04,832.99,yes,locked 2006.218.07:49:22.53/valo/05,652.99,yes,locked 2006.218.07:49:22.53/valo/06,772.99,yes,locked 2006.218.07:49:22.53/valo/07,832.99,yes,locked 2006.218.07:49:22.53/valo/08,852.99,yes,locked 2006.218.07:49:23.62/vb/01,04,usb,yes,34,32 2006.218.07:49:23.62/vb/02,04,usb,yes,36,37 2006.218.07:49:23.62/vb/03,04,usb,yes,32,36 2006.218.07:49:23.62/vb/04,04,usb,yes,33,33 2006.218.07:49:23.62/vb/05,04,usb,yes,31,35 2006.218.07:49:23.62/vb/06,04,usb,yes,32,35 2006.218.07:49:23.62/vb/07,04,usb,yes,34,34 2006.218.07:49:23.62/vb/08,04,usb,yes,32,35 2006.218.07:49:23.86/vblo/01,632.99,yes,locked 2006.218.07:49:23.86/vblo/02,640.99,yes,locked 2006.218.07:49:23.86/vblo/03,656.99,yes,locked 2006.218.07:49:23.86/vblo/04,712.99,yes,locked 2006.218.07:49:23.86/vblo/05,744.99,yes,locked 2006.218.07:49:23.86/vblo/06,752.99,yes,locked 2006.218.07:49:23.86/vblo/07,734.99,yes,locked 2006.218.07:49:23.86/vblo/08,744.99,yes,locked 2006.218.07:49:24.01/vabw/8 2006.218.07:49:24.16/vbbw/8 2006.218.07:49:24.25/xfe/off,on,16.0 2006.218.07:49:24.64/ifatt/23,28,28,28 2006.218.07:49:25.07/fmout-gps/S +4.71E-07 2006.218.07:49:25.15:!2006.218.07:50:20 2006.218.07:50:20.02:data_valid=off 2006.218.07:50:20.02:postob 2006.218.07:50:20.25/cable/+6.3842E-03 2006.218.07:50:20.26/wx/31.19,1007.4,73 2006.218.07:50:21.07/fmout-gps/S +4.69E-07 2006.218.07:50:21.07:scan_name=218-0751,k06218,60 2006.218.07:50:21.07:source=0804+499,080839.67,495036.5,2000.0,ccw 2006.218.07:50:22.15#flagr#flagr/antenna,new-source 2006.218.07:50:22.15:checkk5 2006.218.07:50:22.52/chk_autoobs//k5ts1/ autoobs is running! 2006.218.07:50:22.89/chk_autoobs//k5ts2/ autoobs is running! 2006.218.07:50:23.27/chk_autoobs//k5ts3/ autoobs is running! 2006.218.07:50:23.64/chk_autoobs//k5ts4/ autoobs is running! 2006.218.07:50:24.00/chk_obsdata//k5ts1/T2180749??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:50:24.37/chk_obsdata//k5ts2/T2180749??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:50:24.74/chk_obsdata//k5ts3/T2180749??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:50:25.10/chk_obsdata//k5ts4/T2180749??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:50:25.80/k5log//k5ts1_log_newline 2006.218.07:50:26.49/k5log//k5ts2_log_newline 2006.218.07:50:27.18/k5log//k5ts3_log_newline 2006.218.07:50:27.86/k5log//k5ts4_log_newline 2006.218.07:50:27.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.218.07:50:27.88:4f8m12a=1 2006.218.07:50:27.88$4f8m12a/echo=on 2006.218.07:50:27.88$4f8m12a/pcalon 2006.218.07:50:27.88$pcalon/"no phase cal control is implemented here 2006.218.07:50:27.88$4f8m12a/"tpicd=stop 2006.218.07:50:27.88$4f8m12a/vc4f8 2006.218.07:50:27.88$vc4f8/valo=1,532.99 2006.218.07:50:27.89#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.218.07:50:27.89#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.218.07:50:27.89#ibcon#ireg 17 cls_cnt 0 2006.218.07:50:27.89#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.218.07:50:27.89#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.218.07:50:27.89#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.218.07:50:27.89#ibcon#enter wrdev, iclass 25, count 0 2006.218.07:50:27.89#ibcon#first serial, iclass 25, count 0 2006.218.07:50:27.89#ibcon#enter sib2, iclass 25, count 0 2006.218.07:50:27.89#ibcon#flushed, iclass 25, count 0 2006.218.07:50:27.89#ibcon#about to write, iclass 25, count 0 2006.218.07:50:27.89#ibcon#wrote, iclass 25, count 0 2006.218.07:50:27.89#ibcon#about to read 3, iclass 25, count 0 2006.218.07:50:27.92#ibcon#read 3, iclass 25, count 0 2006.218.07:50:27.92#ibcon#about to read 4, iclass 25, count 0 2006.218.07:50:27.92#ibcon#read 4, iclass 25, count 0 2006.218.07:50:27.92#ibcon#about to read 5, iclass 25, count 0 2006.218.07:50:27.92#ibcon#read 5, iclass 25, count 0 2006.218.07:50:27.92#ibcon#about to read 6, iclass 25, count 0 2006.218.07:50:27.92#ibcon#read 6, iclass 25, count 0 2006.218.07:50:27.92#ibcon#end of sib2, iclass 25, count 0 2006.218.07:50:27.92#ibcon#*mode == 0, iclass 25, count 0 2006.218.07:50:27.92#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.218.07:50:27.92#ibcon#[26=FRQ=01,532.99\r\n] 2006.218.07:50:27.92#ibcon#*before write, iclass 25, count 0 2006.218.07:50:27.92#ibcon#enter sib2, iclass 25, count 0 2006.218.07:50:27.92#ibcon#flushed, iclass 25, count 0 2006.218.07:50:27.92#ibcon#about to write, iclass 25, count 0 2006.218.07:50:27.93#ibcon#wrote, iclass 25, count 0 2006.218.07:50:27.93#ibcon#about to read 3, iclass 25, count 0 2006.218.07:50:27.97#ibcon#read 3, iclass 25, count 0 2006.218.07:50:27.97#ibcon#about to read 4, iclass 25, count 0 2006.218.07:50:27.97#ibcon#read 4, iclass 25, count 0 2006.218.07:50:27.97#ibcon#about to read 5, iclass 25, count 0 2006.218.07:50:27.97#ibcon#read 5, iclass 25, count 0 2006.218.07:50:27.97#ibcon#about to read 6, iclass 25, count 0 2006.218.07:50:27.97#ibcon#read 6, iclass 25, count 0 2006.218.07:50:27.97#ibcon#end of sib2, iclass 25, count 0 2006.218.07:50:27.97#ibcon#*after write, iclass 25, count 0 2006.218.07:50:27.97#ibcon#*before return 0, iclass 25, count 0 2006.218.07:50:27.97#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.218.07:50:27.97#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.218.07:50:27.97#ibcon#about to clear, iclass 25 cls_cnt 0 2006.218.07:50:27.97#ibcon#cleared, iclass 25 cls_cnt 0 2006.218.07:50:27.97$vc4f8/va=1,5 2006.218.07:50:27.98#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.218.07:50:27.98#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.218.07:50:27.98#ibcon#ireg 11 cls_cnt 2 2006.218.07:50:27.98#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.218.07:50:27.98#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.218.07:50:27.98#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.218.07:50:27.98#ibcon#enter wrdev, iclass 27, count 2 2006.218.07:50:27.98#ibcon#first serial, iclass 27, count 2 2006.218.07:50:27.98#ibcon#enter sib2, iclass 27, count 2 2006.218.07:50:27.98#ibcon#flushed, iclass 27, count 2 2006.218.07:50:27.98#ibcon#about to write, iclass 27, count 2 2006.218.07:50:27.98#ibcon#wrote, iclass 27, count 2 2006.218.07:50:27.98#ibcon#about to read 3, iclass 27, count 2 2006.218.07:50:28.00#ibcon#read 3, iclass 27, count 2 2006.218.07:50:28.00#ibcon#about to read 4, iclass 27, count 2 2006.218.07:50:28.00#ibcon#read 4, iclass 27, count 2 2006.218.07:50:28.00#ibcon#about to read 5, iclass 27, count 2 2006.218.07:50:28.00#ibcon#read 5, iclass 27, count 2 2006.218.07:50:28.00#ibcon#about to read 6, iclass 27, count 2 2006.218.07:50:28.00#ibcon#read 6, iclass 27, count 2 2006.218.07:50:28.00#ibcon#end of sib2, iclass 27, count 2 2006.218.07:50:28.00#ibcon#*mode == 0, iclass 27, count 2 2006.218.07:50:28.00#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.218.07:50:28.00#ibcon#[25=AT01-05\r\n] 2006.218.07:50:28.00#ibcon#*before write, iclass 27, count 2 2006.218.07:50:28.00#ibcon#enter sib2, iclass 27, count 2 2006.218.07:50:28.00#ibcon#flushed, iclass 27, count 2 2006.218.07:50:28.00#ibcon#about to write, iclass 27, count 2 2006.218.07:50:28.00#ibcon#wrote, iclass 27, count 2 2006.218.07:50:28.00#ibcon#about to read 3, iclass 27, count 2 2006.218.07:50:28.03#ibcon#read 3, iclass 27, count 2 2006.218.07:50:28.03#ibcon#about to read 4, iclass 27, count 2 2006.218.07:50:28.03#ibcon#read 4, iclass 27, count 2 2006.218.07:50:28.03#ibcon#about to read 5, iclass 27, count 2 2006.218.07:50:28.03#ibcon#read 5, iclass 27, count 2 2006.218.07:50:28.03#ibcon#about to read 6, iclass 27, count 2 2006.218.07:50:28.03#ibcon#read 6, iclass 27, count 2 2006.218.07:50:28.03#ibcon#end of sib2, iclass 27, count 2 2006.218.07:50:28.03#ibcon#*after write, iclass 27, count 2 2006.218.07:50:28.03#ibcon#*before return 0, iclass 27, count 2 2006.218.07:50:28.03#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.218.07:50:28.03#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.218.07:50:28.03#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.218.07:50:28.03#ibcon#ireg 7 cls_cnt 0 2006.218.07:50:28.03#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.218.07:50:28.15#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.218.07:50:28.15#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.218.07:50:28.15#ibcon#enter wrdev, iclass 27, count 0 2006.218.07:50:28.15#ibcon#first serial, iclass 27, count 0 2006.218.07:50:28.15#ibcon#enter sib2, iclass 27, count 0 2006.218.07:50:28.15#ibcon#flushed, iclass 27, count 0 2006.218.07:50:28.15#ibcon#about to write, iclass 27, count 0 2006.218.07:50:28.15#ibcon#wrote, iclass 27, count 0 2006.218.07:50:28.15#ibcon#about to read 3, iclass 27, count 0 2006.218.07:50:28.17#ibcon#read 3, iclass 27, count 0 2006.218.07:50:28.17#ibcon#about to read 4, iclass 27, count 0 2006.218.07:50:28.17#ibcon#read 4, iclass 27, count 0 2006.218.07:50:28.17#ibcon#about to read 5, iclass 27, count 0 2006.218.07:50:28.17#ibcon#read 5, iclass 27, count 0 2006.218.07:50:28.17#ibcon#about to read 6, iclass 27, count 0 2006.218.07:50:28.17#ibcon#read 6, iclass 27, count 0 2006.218.07:50:28.17#ibcon#end of sib2, iclass 27, count 0 2006.218.07:50:28.17#ibcon#*mode == 0, iclass 27, count 0 2006.218.07:50:28.17#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.218.07:50:28.17#ibcon#[25=USB\r\n] 2006.218.07:50:28.17#ibcon#*before write, iclass 27, count 0 2006.218.07:50:28.17#ibcon#enter sib2, iclass 27, count 0 2006.218.07:50:28.17#ibcon#flushed, iclass 27, count 0 2006.218.07:50:28.17#ibcon#about to write, iclass 27, count 0 2006.218.07:50:28.17#ibcon#wrote, iclass 27, count 0 2006.218.07:50:28.17#ibcon#about to read 3, iclass 27, count 0 2006.218.07:50:28.20#ibcon#read 3, iclass 27, count 0 2006.218.07:50:28.21#ibcon#about to read 4, iclass 27, count 0 2006.218.07:50:28.21#ibcon#read 4, iclass 27, count 0 2006.218.07:50:28.21#ibcon#about to read 5, iclass 27, count 0 2006.218.07:50:28.21#ibcon#read 5, iclass 27, count 0 2006.218.07:50:28.21#ibcon#about to read 6, iclass 27, count 0 2006.218.07:50:28.21#ibcon#read 6, iclass 27, count 0 2006.218.07:50:28.21#ibcon#end of sib2, iclass 27, count 0 2006.218.07:50:28.21#ibcon#*after write, iclass 27, count 0 2006.218.07:50:28.21#ibcon#*before return 0, iclass 27, count 0 2006.218.07:50:28.21#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.218.07:50:28.21#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.218.07:50:28.21#ibcon#about to clear, iclass 27 cls_cnt 0 2006.218.07:50:28.21#ibcon#cleared, iclass 27 cls_cnt 0 2006.218.07:50:28.21$vc4f8/valo=2,572.99 2006.218.07:50:28.21#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.218.07:50:28.21#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.218.07:50:28.21#ibcon#ireg 17 cls_cnt 0 2006.218.07:50:28.21#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.218.07:50:28.21#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.218.07:50:28.21#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.218.07:50:28.21#ibcon#enter wrdev, iclass 29, count 0 2006.218.07:50:28.21#ibcon#first serial, iclass 29, count 0 2006.218.07:50:28.21#ibcon#enter sib2, iclass 29, count 0 2006.218.07:50:28.21#ibcon#flushed, iclass 29, count 0 2006.218.07:50:28.21#ibcon#about to write, iclass 29, count 0 2006.218.07:50:28.21#ibcon#wrote, iclass 29, count 0 2006.218.07:50:28.21#ibcon#about to read 3, iclass 29, count 0 2006.218.07:50:28.22#ibcon#read 3, iclass 29, count 0 2006.218.07:50:28.22#ibcon#about to read 4, iclass 29, count 0 2006.218.07:50:28.22#ibcon#read 4, iclass 29, count 0 2006.218.07:50:28.22#ibcon#about to read 5, iclass 29, count 0 2006.218.07:50:28.22#ibcon#read 5, iclass 29, count 0 2006.218.07:50:28.22#ibcon#about to read 6, iclass 29, count 0 2006.218.07:50:28.22#ibcon#read 6, iclass 29, count 0 2006.218.07:50:28.22#ibcon#end of sib2, iclass 29, count 0 2006.218.07:50:28.22#ibcon#*mode == 0, iclass 29, count 0 2006.218.07:50:28.22#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.218.07:50:28.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.218.07:50:28.22#ibcon#*before write, iclass 29, count 0 2006.218.07:50:28.22#ibcon#enter sib2, iclass 29, count 0 2006.218.07:50:28.22#ibcon#flushed, iclass 29, count 0 2006.218.07:50:28.22#ibcon#about to write, iclass 29, count 0 2006.218.07:50:28.22#ibcon#wrote, iclass 29, count 0 2006.218.07:50:28.22#ibcon#about to read 3, iclass 29, count 0 2006.218.07:50:28.26#ibcon#read 3, iclass 29, count 0 2006.218.07:50:28.26#ibcon#about to read 4, iclass 29, count 0 2006.218.07:50:28.26#ibcon#read 4, iclass 29, count 0 2006.218.07:50:28.26#ibcon#about to read 5, iclass 29, count 0 2006.218.07:50:28.26#ibcon#read 5, iclass 29, count 0 2006.218.07:50:28.26#ibcon#about to read 6, iclass 29, count 0 2006.218.07:50:28.26#ibcon#read 6, iclass 29, count 0 2006.218.07:50:28.26#ibcon#end of sib2, iclass 29, count 0 2006.218.07:50:28.26#ibcon#*after write, iclass 29, count 0 2006.218.07:50:28.26#ibcon#*before return 0, iclass 29, count 0 2006.218.07:50:28.26#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.218.07:50:28.26#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.218.07:50:28.26#ibcon#about to clear, iclass 29 cls_cnt 0 2006.218.07:50:28.26#ibcon#cleared, iclass 29 cls_cnt 0 2006.218.07:50:28.26$vc4f8/va=2,4 2006.218.07:50:28.27#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.218.07:50:28.27#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.218.07:50:28.27#ibcon#ireg 11 cls_cnt 2 2006.218.07:50:28.27#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.218.07:50:28.32#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.218.07:50:28.32#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.218.07:50:28.32#ibcon#enter wrdev, iclass 31, count 2 2006.218.07:50:28.32#ibcon#first serial, iclass 31, count 2 2006.218.07:50:28.32#ibcon#enter sib2, iclass 31, count 2 2006.218.07:50:28.32#ibcon#flushed, iclass 31, count 2 2006.218.07:50:28.32#ibcon#about to write, iclass 31, count 2 2006.218.07:50:28.32#ibcon#wrote, iclass 31, count 2 2006.218.07:50:28.32#ibcon#about to read 3, iclass 31, count 2 2006.218.07:50:28.34#ibcon#read 3, iclass 31, count 2 2006.218.07:50:28.34#ibcon#about to read 4, iclass 31, count 2 2006.218.07:50:28.34#ibcon#read 4, iclass 31, count 2 2006.218.07:50:28.34#ibcon#about to read 5, iclass 31, count 2 2006.218.07:50:28.34#ibcon#read 5, iclass 31, count 2 2006.218.07:50:28.34#ibcon#about to read 6, iclass 31, count 2 2006.218.07:50:28.34#ibcon#read 6, iclass 31, count 2 2006.218.07:50:28.34#ibcon#end of sib2, iclass 31, count 2 2006.218.07:50:28.34#ibcon#*mode == 0, iclass 31, count 2 2006.218.07:50:28.34#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.218.07:50:28.34#ibcon#[25=AT02-04\r\n] 2006.218.07:50:28.34#ibcon#*before write, iclass 31, count 2 2006.218.07:50:28.34#ibcon#enter sib2, iclass 31, count 2 2006.218.07:50:28.34#ibcon#flushed, iclass 31, count 2 2006.218.07:50:28.34#ibcon#about to write, iclass 31, count 2 2006.218.07:50:28.34#ibcon#wrote, iclass 31, count 2 2006.218.07:50:28.34#ibcon#about to read 3, iclass 31, count 2 2006.218.07:50:28.37#ibcon#read 3, iclass 31, count 2 2006.218.07:50:28.37#ibcon#about to read 4, iclass 31, count 2 2006.218.07:50:28.37#ibcon#read 4, iclass 31, count 2 2006.218.07:50:28.37#ibcon#about to read 5, iclass 31, count 2 2006.218.07:50:28.37#ibcon#read 5, iclass 31, count 2 2006.218.07:50:28.37#ibcon#about to read 6, iclass 31, count 2 2006.218.07:50:28.37#ibcon#read 6, iclass 31, count 2 2006.218.07:50:28.37#ibcon#end of sib2, iclass 31, count 2 2006.218.07:50:28.37#ibcon#*after write, iclass 31, count 2 2006.218.07:50:28.37#ibcon#*before return 0, iclass 31, count 2 2006.218.07:50:28.37#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.218.07:50:28.37#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.218.07:50:28.37#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.218.07:50:28.37#ibcon#ireg 7 cls_cnt 0 2006.218.07:50:28.37#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.218.07:50:28.49#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.218.07:50:28.50#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.218.07:50:28.50#ibcon#enter wrdev, iclass 31, count 0 2006.218.07:50:28.50#ibcon#first serial, iclass 31, count 0 2006.218.07:50:28.50#ibcon#enter sib2, iclass 31, count 0 2006.218.07:50:28.50#ibcon#flushed, iclass 31, count 0 2006.218.07:50:28.50#ibcon#about to write, iclass 31, count 0 2006.218.07:50:28.50#ibcon#wrote, iclass 31, count 0 2006.218.07:50:28.50#ibcon#about to read 3, iclass 31, count 0 2006.218.07:50:28.52#ibcon#read 3, iclass 31, count 0 2006.218.07:50:28.52#ibcon#about to read 4, iclass 31, count 0 2006.218.07:50:28.52#ibcon#read 4, iclass 31, count 0 2006.218.07:50:28.52#ibcon#about to read 5, iclass 31, count 0 2006.218.07:50:28.52#ibcon#read 5, iclass 31, count 0 2006.218.07:50:28.52#ibcon#about to read 6, iclass 31, count 0 2006.218.07:50:28.52#ibcon#read 6, iclass 31, count 0 2006.218.07:50:28.52#ibcon#end of sib2, iclass 31, count 0 2006.218.07:50:28.52#ibcon#*mode == 0, iclass 31, count 0 2006.218.07:50:28.52#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.218.07:50:28.52#ibcon#[25=USB\r\n] 2006.218.07:50:28.52#ibcon#*before write, iclass 31, count 0 2006.218.07:50:28.52#ibcon#enter sib2, iclass 31, count 0 2006.218.07:50:28.52#ibcon#flushed, iclass 31, count 0 2006.218.07:50:28.52#ibcon#about to write, iclass 31, count 0 2006.218.07:50:28.52#ibcon#wrote, iclass 31, count 0 2006.218.07:50:28.52#ibcon#about to read 3, iclass 31, count 0 2006.218.07:50:28.54#ibcon#read 3, iclass 31, count 0 2006.218.07:50:28.54#ibcon#about to read 4, iclass 31, count 0 2006.218.07:50:28.54#ibcon#read 4, iclass 31, count 0 2006.218.07:50:28.54#ibcon#about to read 5, iclass 31, count 0 2006.218.07:50:28.54#ibcon#read 5, iclass 31, count 0 2006.218.07:50:28.54#ibcon#about to read 6, iclass 31, count 0 2006.218.07:50:28.54#ibcon#read 6, iclass 31, count 0 2006.218.07:50:28.54#ibcon#end of sib2, iclass 31, count 0 2006.218.07:50:28.54#ibcon#*after write, iclass 31, count 0 2006.218.07:50:28.54#ibcon#*before return 0, iclass 31, count 0 2006.218.07:50:28.54#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.218.07:50:28.54#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.218.07:50:28.54#ibcon#about to clear, iclass 31 cls_cnt 0 2006.218.07:50:28.54#ibcon#cleared, iclass 31 cls_cnt 0 2006.218.07:50:28.54$vc4f8/valo=3,672.99 2006.218.07:50:28.55#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.218.07:50:28.55#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.218.07:50:28.55#ibcon#ireg 17 cls_cnt 0 2006.218.07:50:28.55#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.218.07:50:28.55#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.218.07:50:28.55#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.218.07:50:28.55#ibcon#enter wrdev, iclass 33, count 0 2006.218.07:50:28.55#ibcon#first serial, iclass 33, count 0 2006.218.07:50:28.55#ibcon#enter sib2, iclass 33, count 0 2006.218.07:50:28.55#ibcon#flushed, iclass 33, count 0 2006.218.07:50:28.55#ibcon#about to write, iclass 33, count 0 2006.218.07:50:28.55#ibcon#wrote, iclass 33, count 0 2006.218.07:50:28.55#ibcon#about to read 3, iclass 33, count 0 2006.218.07:50:28.56#ibcon#read 3, iclass 33, count 0 2006.218.07:50:28.56#ibcon#about to read 4, iclass 33, count 0 2006.218.07:50:28.56#ibcon#read 4, iclass 33, count 0 2006.218.07:50:28.56#ibcon#about to read 5, iclass 33, count 0 2006.218.07:50:28.56#ibcon#read 5, iclass 33, count 0 2006.218.07:50:28.56#ibcon#about to read 6, iclass 33, count 0 2006.218.07:50:28.56#ibcon#read 6, iclass 33, count 0 2006.218.07:50:28.56#ibcon#end of sib2, iclass 33, count 0 2006.218.07:50:28.56#ibcon#*mode == 0, iclass 33, count 0 2006.218.07:50:28.56#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.218.07:50:28.56#ibcon#[26=FRQ=03,672.99\r\n] 2006.218.07:50:28.56#ibcon#*before write, iclass 33, count 0 2006.218.07:50:28.56#ibcon#enter sib2, iclass 33, count 0 2006.218.07:50:28.56#ibcon#flushed, iclass 33, count 0 2006.218.07:50:28.56#ibcon#about to write, iclass 33, count 0 2006.218.07:50:28.56#ibcon#wrote, iclass 33, count 0 2006.218.07:50:28.56#ibcon#about to read 3, iclass 33, count 0 2006.218.07:50:28.61#ibcon#read 3, iclass 33, count 0 2006.218.07:50:28.61#ibcon#about to read 4, iclass 33, count 0 2006.218.07:50:28.61#ibcon#read 4, iclass 33, count 0 2006.218.07:50:28.61#ibcon#about to read 5, iclass 33, count 0 2006.218.07:50:28.61#ibcon#read 5, iclass 33, count 0 2006.218.07:50:28.61#ibcon#about to read 6, iclass 33, count 0 2006.218.07:50:28.61#ibcon#read 6, iclass 33, count 0 2006.218.07:50:28.61#ibcon#end of sib2, iclass 33, count 0 2006.218.07:50:28.61#ibcon#*after write, iclass 33, count 0 2006.218.07:50:28.61#ibcon#*before return 0, iclass 33, count 0 2006.218.07:50:28.61#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.218.07:50:28.61#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.218.07:50:28.61#ibcon#about to clear, iclass 33 cls_cnt 0 2006.218.07:50:28.61#ibcon#cleared, iclass 33 cls_cnt 0 2006.218.07:50:28.61$vc4f8/va=3,4 2006.218.07:50:28.61#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.218.07:50:28.61#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.218.07:50:28.61#ibcon#ireg 11 cls_cnt 2 2006.218.07:50:28.61#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.218.07:50:28.65#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.218.07:50:28.65#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.218.07:50:28.65#ibcon#enter wrdev, iclass 35, count 2 2006.218.07:50:28.65#ibcon#first serial, iclass 35, count 2 2006.218.07:50:28.65#ibcon#enter sib2, iclass 35, count 2 2006.218.07:50:28.65#ibcon#flushed, iclass 35, count 2 2006.218.07:50:28.65#ibcon#about to write, iclass 35, count 2 2006.218.07:50:28.65#ibcon#wrote, iclass 35, count 2 2006.218.07:50:28.65#ibcon#about to read 3, iclass 35, count 2 2006.218.07:50:28.68#ibcon#read 3, iclass 35, count 2 2006.218.07:50:28.68#ibcon#about to read 4, iclass 35, count 2 2006.218.07:50:28.68#ibcon#read 4, iclass 35, count 2 2006.218.07:50:28.68#ibcon#about to read 5, iclass 35, count 2 2006.218.07:50:28.68#ibcon#read 5, iclass 35, count 2 2006.218.07:50:28.68#ibcon#about to read 6, iclass 35, count 2 2006.218.07:50:28.68#ibcon#read 6, iclass 35, count 2 2006.218.07:50:28.68#ibcon#end of sib2, iclass 35, count 2 2006.218.07:50:28.68#ibcon#*mode == 0, iclass 35, count 2 2006.218.07:50:28.68#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.218.07:50:28.68#ibcon#[25=AT03-04\r\n] 2006.218.07:50:28.68#ibcon#*before write, iclass 35, count 2 2006.218.07:50:28.68#ibcon#enter sib2, iclass 35, count 2 2006.218.07:50:28.68#ibcon#flushed, iclass 35, count 2 2006.218.07:50:28.68#ibcon#about to write, iclass 35, count 2 2006.218.07:50:28.68#ibcon#wrote, iclass 35, count 2 2006.218.07:50:28.68#ibcon#about to read 3, iclass 35, count 2 2006.218.07:50:28.71#ibcon#read 3, iclass 35, count 2 2006.218.07:50:28.71#ibcon#about to read 4, iclass 35, count 2 2006.218.07:50:28.71#ibcon#read 4, iclass 35, count 2 2006.218.07:50:28.71#ibcon#about to read 5, iclass 35, count 2 2006.218.07:50:28.71#ibcon#read 5, iclass 35, count 2 2006.218.07:50:28.71#ibcon#about to read 6, iclass 35, count 2 2006.218.07:50:28.71#ibcon#read 6, iclass 35, count 2 2006.218.07:50:28.71#ibcon#end of sib2, iclass 35, count 2 2006.218.07:50:28.71#ibcon#*after write, iclass 35, count 2 2006.218.07:50:28.71#ibcon#*before return 0, iclass 35, count 2 2006.218.07:50:28.71#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.218.07:50:28.71#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.218.07:50:28.71#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.218.07:50:28.71#ibcon#ireg 7 cls_cnt 0 2006.218.07:50:28.71#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.218.07:50:28.83#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.218.07:50:28.83#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.218.07:50:28.83#ibcon#enter wrdev, iclass 35, count 0 2006.218.07:50:28.83#ibcon#first serial, iclass 35, count 0 2006.218.07:50:28.83#ibcon#enter sib2, iclass 35, count 0 2006.218.07:50:28.83#ibcon#flushed, iclass 35, count 0 2006.218.07:50:28.83#ibcon#about to write, iclass 35, count 0 2006.218.07:50:28.83#ibcon#wrote, iclass 35, count 0 2006.218.07:50:28.83#ibcon#about to read 3, iclass 35, count 0 2006.218.07:50:28.85#ibcon#read 3, iclass 35, count 0 2006.218.07:50:28.85#ibcon#about to read 4, iclass 35, count 0 2006.218.07:50:28.85#ibcon#read 4, iclass 35, count 0 2006.218.07:50:28.85#ibcon#about to read 5, iclass 35, count 0 2006.218.07:50:28.85#ibcon#read 5, iclass 35, count 0 2006.218.07:50:28.85#ibcon#about to read 6, iclass 35, count 0 2006.218.07:50:28.85#ibcon#read 6, iclass 35, count 0 2006.218.07:50:28.85#ibcon#end of sib2, iclass 35, count 0 2006.218.07:50:28.85#ibcon#*mode == 0, iclass 35, count 0 2006.218.07:50:28.85#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.218.07:50:28.85#ibcon#[25=USB\r\n] 2006.218.07:50:28.85#ibcon#*before write, iclass 35, count 0 2006.218.07:50:28.85#ibcon#enter sib2, iclass 35, count 0 2006.218.07:50:28.85#ibcon#flushed, iclass 35, count 0 2006.218.07:50:28.85#ibcon#about to write, iclass 35, count 0 2006.218.07:50:28.85#ibcon#wrote, iclass 35, count 0 2006.218.07:50:28.85#ibcon#about to read 3, iclass 35, count 0 2006.218.07:50:28.88#ibcon#read 3, iclass 35, count 0 2006.218.07:50:28.88#ibcon#about to read 4, iclass 35, count 0 2006.218.07:50:28.88#ibcon#read 4, iclass 35, count 0 2006.218.07:50:28.88#ibcon#about to read 5, iclass 35, count 0 2006.218.07:50:28.88#ibcon#read 5, iclass 35, count 0 2006.218.07:50:28.88#ibcon#about to read 6, iclass 35, count 0 2006.218.07:50:28.88#ibcon#read 6, iclass 35, count 0 2006.218.07:50:28.88#ibcon#end of sib2, iclass 35, count 0 2006.218.07:50:28.88#ibcon#*after write, iclass 35, count 0 2006.218.07:50:28.88#ibcon#*before return 0, iclass 35, count 0 2006.218.07:50:28.88#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.218.07:50:28.88#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.218.07:50:28.88#ibcon#about to clear, iclass 35 cls_cnt 0 2006.218.07:50:28.88#ibcon#cleared, iclass 35 cls_cnt 0 2006.218.07:50:28.88$vc4f8/valo=4,832.99 2006.218.07:50:28.89#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.218.07:50:28.89#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.218.07:50:28.89#ibcon#ireg 17 cls_cnt 0 2006.218.07:50:28.89#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.218.07:50:28.89#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.218.07:50:28.89#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.218.07:50:28.89#ibcon#enter wrdev, iclass 37, count 0 2006.218.07:50:28.89#ibcon#first serial, iclass 37, count 0 2006.218.07:50:28.89#ibcon#enter sib2, iclass 37, count 0 2006.218.07:50:28.89#ibcon#flushed, iclass 37, count 0 2006.218.07:50:28.89#ibcon#about to write, iclass 37, count 0 2006.218.07:50:28.89#ibcon#wrote, iclass 37, count 0 2006.218.07:50:28.89#ibcon#about to read 3, iclass 37, count 0 2006.218.07:50:28.90#ibcon#read 3, iclass 37, count 0 2006.218.07:50:28.90#ibcon#about to read 4, iclass 37, count 0 2006.218.07:50:28.90#ibcon#read 4, iclass 37, count 0 2006.218.07:50:28.90#ibcon#about to read 5, iclass 37, count 0 2006.218.07:50:28.90#ibcon#read 5, iclass 37, count 0 2006.218.07:50:28.90#ibcon#about to read 6, iclass 37, count 0 2006.218.07:50:28.90#ibcon#read 6, iclass 37, count 0 2006.218.07:50:28.90#ibcon#end of sib2, iclass 37, count 0 2006.218.07:50:28.90#ibcon#*mode == 0, iclass 37, count 0 2006.218.07:50:28.90#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.218.07:50:28.90#ibcon#[26=FRQ=04,832.99\r\n] 2006.218.07:50:28.90#ibcon#*before write, iclass 37, count 0 2006.218.07:50:28.90#ibcon#enter sib2, iclass 37, count 0 2006.218.07:50:28.90#ibcon#flushed, iclass 37, count 0 2006.218.07:50:28.90#ibcon#about to write, iclass 37, count 0 2006.218.07:50:28.90#ibcon#wrote, iclass 37, count 0 2006.218.07:50:28.90#ibcon#about to read 3, iclass 37, count 0 2006.218.07:50:28.94#ibcon#read 3, iclass 37, count 0 2006.218.07:50:28.94#ibcon#about to read 4, iclass 37, count 0 2006.218.07:50:28.94#ibcon#read 4, iclass 37, count 0 2006.218.07:50:28.94#ibcon#about to read 5, iclass 37, count 0 2006.218.07:50:28.94#ibcon#read 5, iclass 37, count 0 2006.218.07:50:28.94#ibcon#about to read 6, iclass 37, count 0 2006.218.07:50:28.94#ibcon#read 6, iclass 37, count 0 2006.218.07:50:28.94#ibcon#end of sib2, iclass 37, count 0 2006.218.07:50:28.94#ibcon#*after write, iclass 37, count 0 2006.218.07:50:28.94#ibcon#*before return 0, iclass 37, count 0 2006.218.07:50:28.94#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.218.07:50:28.94#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.218.07:50:28.94#ibcon#about to clear, iclass 37 cls_cnt 0 2006.218.07:50:28.94#ibcon#cleared, iclass 37 cls_cnt 0 2006.218.07:50:28.94$vc4f8/va=4,4 2006.218.07:50:28.95#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.218.07:50:28.95#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.218.07:50:28.95#ibcon#ireg 11 cls_cnt 2 2006.218.07:50:28.95#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.218.07:50:28.99#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.218.07:50:28.99#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.218.07:50:28.99#ibcon#enter wrdev, iclass 39, count 2 2006.218.07:50:28.99#ibcon#first serial, iclass 39, count 2 2006.218.07:50:28.99#ibcon#enter sib2, iclass 39, count 2 2006.218.07:50:28.99#ibcon#flushed, iclass 39, count 2 2006.218.07:50:28.99#ibcon#about to write, iclass 39, count 2 2006.218.07:50:28.99#ibcon#wrote, iclass 39, count 2 2006.218.07:50:28.99#ibcon#about to read 3, iclass 39, count 2 2006.218.07:50:29.01#ibcon#read 3, iclass 39, count 2 2006.218.07:50:29.01#ibcon#about to read 4, iclass 39, count 2 2006.218.07:50:29.01#ibcon#read 4, iclass 39, count 2 2006.218.07:50:29.01#ibcon#about to read 5, iclass 39, count 2 2006.218.07:50:29.01#ibcon#read 5, iclass 39, count 2 2006.218.07:50:29.01#ibcon#about to read 6, iclass 39, count 2 2006.218.07:50:29.01#ibcon#read 6, iclass 39, count 2 2006.218.07:50:29.01#ibcon#end of sib2, iclass 39, count 2 2006.218.07:50:29.01#ibcon#*mode == 0, iclass 39, count 2 2006.218.07:50:29.01#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.218.07:50:29.01#ibcon#[25=AT04-04\r\n] 2006.218.07:50:29.01#ibcon#*before write, iclass 39, count 2 2006.218.07:50:29.01#ibcon#enter sib2, iclass 39, count 2 2006.218.07:50:29.01#ibcon#flushed, iclass 39, count 2 2006.218.07:50:29.01#ibcon#about to write, iclass 39, count 2 2006.218.07:50:29.01#ibcon#wrote, iclass 39, count 2 2006.218.07:50:29.01#ibcon#about to read 3, iclass 39, count 2 2006.218.07:50:29.04#ibcon#read 3, iclass 39, count 2 2006.218.07:50:29.04#ibcon#about to read 4, iclass 39, count 2 2006.218.07:50:29.04#ibcon#read 4, iclass 39, count 2 2006.218.07:50:29.04#ibcon#about to read 5, iclass 39, count 2 2006.218.07:50:29.04#ibcon#read 5, iclass 39, count 2 2006.218.07:50:29.04#ibcon#about to read 6, iclass 39, count 2 2006.218.07:50:29.04#ibcon#read 6, iclass 39, count 2 2006.218.07:50:29.04#ibcon#end of sib2, iclass 39, count 2 2006.218.07:50:29.04#ibcon#*after write, iclass 39, count 2 2006.218.07:50:29.04#ibcon#*before return 0, iclass 39, count 2 2006.218.07:50:29.04#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.218.07:50:29.04#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.218.07:50:29.04#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.218.07:50:29.04#ibcon#ireg 7 cls_cnt 0 2006.218.07:50:29.04#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.218.07:50:29.16#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.218.07:50:29.16#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.218.07:50:29.16#ibcon#enter wrdev, iclass 39, count 0 2006.218.07:50:29.16#ibcon#first serial, iclass 39, count 0 2006.218.07:50:29.16#ibcon#enter sib2, iclass 39, count 0 2006.218.07:50:29.16#ibcon#flushed, iclass 39, count 0 2006.218.07:50:29.16#ibcon#about to write, iclass 39, count 0 2006.218.07:50:29.16#ibcon#wrote, iclass 39, count 0 2006.218.07:50:29.16#ibcon#about to read 3, iclass 39, count 0 2006.218.07:50:29.18#ibcon#read 3, iclass 39, count 0 2006.218.07:50:29.18#ibcon#about to read 4, iclass 39, count 0 2006.218.07:50:29.18#ibcon#read 4, iclass 39, count 0 2006.218.07:50:29.18#ibcon#about to read 5, iclass 39, count 0 2006.218.07:50:29.18#ibcon#read 5, iclass 39, count 0 2006.218.07:50:29.18#ibcon#about to read 6, iclass 39, count 0 2006.218.07:50:29.18#ibcon#read 6, iclass 39, count 0 2006.218.07:50:29.18#ibcon#end of sib2, iclass 39, count 0 2006.218.07:50:29.18#ibcon#*mode == 0, iclass 39, count 0 2006.218.07:50:29.18#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.218.07:50:29.18#ibcon#[25=USB\r\n] 2006.218.07:50:29.18#ibcon#*before write, iclass 39, count 0 2006.218.07:50:29.18#ibcon#enter sib2, iclass 39, count 0 2006.218.07:50:29.18#ibcon#flushed, iclass 39, count 0 2006.218.07:50:29.18#ibcon#about to write, iclass 39, count 0 2006.218.07:50:29.18#ibcon#wrote, iclass 39, count 0 2006.218.07:50:29.18#ibcon#about to read 3, iclass 39, count 0 2006.218.07:50:29.21#ibcon#read 3, iclass 39, count 0 2006.218.07:50:29.21#ibcon#about to read 4, iclass 39, count 0 2006.218.07:50:29.21#ibcon#read 4, iclass 39, count 0 2006.218.07:50:29.21#ibcon#about to read 5, iclass 39, count 0 2006.218.07:50:29.21#ibcon#read 5, iclass 39, count 0 2006.218.07:50:29.21#ibcon#about to read 6, iclass 39, count 0 2006.218.07:50:29.21#ibcon#read 6, iclass 39, count 0 2006.218.07:50:29.21#ibcon#end of sib2, iclass 39, count 0 2006.218.07:50:29.21#ibcon#*after write, iclass 39, count 0 2006.218.07:50:29.21#ibcon#*before return 0, iclass 39, count 0 2006.218.07:50:29.21#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.218.07:50:29.21#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.218.07:50:29.21#ibcon#about to clear, iclass 39 cls_cnt 0 2006.218.07:50:29.21#ibcon#cleared, iclass 39 cls_cnt 0 2006.218.07:50:29.21$vc4f8/valo=5,652.99 2006.218.07:50:29.22#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.218.07:50:29.22#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.218.07:50:29.22#ibcon#ireg 17 cls_cnt 0 2006.218.07:50:29.22#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.218.07:50:29.22#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.218.07:50:29.22#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.218.07:50:29.22#ibcon#enter wrdev, iclass 3, count 0 2006.218.07:50:29.22#ibcon#first serial, iclass 3, count 0 2006.218.07:50:29.22#ibcon#enter sib2, iclass 3, count 0 2006.218.07:50:29.22#ibcon#flushed, iclass 3, count 0 2006.218.07:50:29.22#ibcon#about to write, iclass 3, count 0 2006.218.07:50:29.22#ibcon#wrote, iclass 3, count 0 2006.218.07:50:29.22#ibcon#about to read 3, iclass 3, count 0 2006.218.07:50:29.23#ibcon#read 3, iclass 3, count 0 2006.218.07:50:29.23#ibcon#about to read 4, iclass 3, count 0 2006.218.07:50:29.23#ibcon#read 4, iclass 3, count 0 2006.218.07:50:29.23#ibcon#about to read 5, iclass 3, count 0 2006.218.07:50:29.23#ibcon#read 5, iclass 3, count 0 2006.218.07:50:29.23#ibcon#about to read 6, iclass 3, count 0 2006.218.07:50:29.23#ibcon#read 6, iclass 3, count 0 2006.218.07:50:29.23#ibcon#end of sib2, iclass 3, count 0 2006.218.07:50:29.23#ibcon#*mode == 0, iclass 3, count 0 2006.218.07:50:29.23#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.218.07:50:29.23#ibcon#[26=FRQ=05,652.99\r\n] 2006.218.07:50:29.23#ibcon#*before write, iclass 3, count 0 2006.218.07:50:29.23#ibcon#enter sib2, iclass 3, count 0 2006.218.07:50:29.23#ibcon#flushed, iclass 3, count 0 2006.218.07:50:29.23#ibcon#about to write, iclass 3, count 0 2006.218.07:50:29.23#ibcon#wrote, iclass 3, count 0 2006.218.07:50:29.23#ibcon#about to read 3, iclass 3, count 0 2006.218.07:50:29.27#ibcon#read 3, iclass 3, count 0 2006.218.07:50:29.27#ibcon#about to read 4, iclass 3, count 0 2006.218.07:50:29.27#ibcon#read 4, iclass 3, count 0 2006.218.07:50:29.27#ibcon#about to read 5, iclass 3, count 0 2006.218.07:50:29.27#ibcon#read 5, iclass 3, count 0 2006.218.07:50:29.27#ibcon#about to read 6, iclass 3, count 0 2006.218.07:50:29.27#ibcon#read 6, iclass 3, count 0 2006.218.07:50:29.27#ibcon#end of sib2, iclass 3, count 0 2006.218.07:50:29.27#ibcon#*after write, iclass 3, count 0 2006.218.07:50:29.27#ibcon#*before return 0, iclass 3, count 0 2006.218.07:50:29.27#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.218.07:50:29.27#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.218.07:50:29.27#ibcon#about to clear, iclass 3 cls_cnt 0 2006.218.07:50:29.27#ibcon#cleared, iclass 3 cls_cnt 0 2006.218.07:50:29.27$vc4f8/va=5,7 2006.218.07:50:29.28#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.218.07:50:29.28#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.218.07:50:29.28#ibcon#ireg 11 cls_cnt 2 2006.218.07:50:29.28#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.218.07:50:29.32#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.218.07:50:29.32#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.218.07:50:29.32#ibcon#enter wrdev, iclass 5, count 2 2006.218.07:50:29.32#ibcon#first serial, iclass 5, count 2 2006.218.07:50:29.32#ibcon#enter sib2, iclass 5, count 2 2006.218.07:50:29.32#ibcon#flushed, iclass 5, count 2 2006.218.07:50:29.32#ibcon#about to write, iclass 5, count 2 2006.218.07:50:29.32#ibcon#wrote, iclass 5, count 2 2006.218.07:50:29.32#ibcon#about to read 3, iclass 5, count 2 2006.218.07:50:29.34#ibcon#read 3, iclass 5, count 2 2006.218.07:50:29.34#ibcon#about to read 4, iclass 5, count 2 2006.218.07:50:29.34#ibcon#read 4, iclass 5, count 2 2006.218.07:50:29.34#ibcon#about to read 5, iclass 5, count 2 2006.218.07:50:29.34#ibcon#read 5, iclass 5, count 2 2006.218.07:50:29.34#ibcon#about to read 6, iclass 5, count 2 2006.218.07:50:29.34#ibcon#read 6, iclass 5, count 2 2006.218.07:50:29.34#ibcon#end of sib2, iclass 5, count 2 2006.218.07:50:29.34#ibcon#*mode == 0, iclass 5, count 2 2006.218.07:50:29.34#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.218.07:50:29.34#ibcon#[25=AT05-07\r\n] 2006.218.07:50:29.34#ibcon#*before write, iclass 5, count 2 2006.218.07:50:29.34#ibcon#enter sib2, iclass 5, count 2 2006.218.07:50:29.34#ibcon#flushed, iclass 5, count 2 2006.218.07:50:29.34#ibcon#about to write, iclass 5, count 2 2006.218.07:50:29.34#ibcon#wrote, iclass 5, count 2 2006.218.07:50:29.34#ibcon#about to read 3, iclass 5, count 2 2006.218.07:50:29.37#ibcon#read 3, iclass 5, count 2 2006.218.07:50:29.37#ibcon#about to read 4, iclass 5, count 2 2006.218.07:50:29.37#ibcon#read 4, iclass 5, count 2 2006.218.07:50:29.37#ibcon#about to read 5, iclass 5, count 2 2006.218.07:50:29.37#ibcon#read 5, iclass 5, count 2 2006.218.07:50:29.37#ibcon#about to read 6, iclass 5, count 2 2006.218.07:50:29.37#ibcon#read 6, iclass 5, count 2 2006.218.07:50:29.37#ibcon#end of sib2, iclass 5, count 2 2006.218.07:50:29.37#ibcon#*after write, iclass 5, count 2 2006.218.07:50:29.37#ibcon#*before return 0, iclass 5, count 2 2006.218.07:50:29.37#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.218.07:50:29.37#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.218.07:50:29.37#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.218.07:50:29.37#ibcon#ireg 7 cls_cnt 0 2006.218.07:50:29.37#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.218.07:50:29.49#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.218.07:50:29.49#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.218.07:50:29.49#ibcon#enter wrdev, iclass 5, count 0 2006.218.07:50:29.49#ibcon#first serial, iclass 5, count 0 2006.218.07:50:29.49#ibcon#enter sib2, iclass 5, count 0 2006.218.07:50:29.49#ibcon#flushed, iclass 5, count 0 2006.218.07:50:29.49#ibcon#about to write, iclass 5, count 0 2006.218.07:50:29.49#ibcon#wrote, iclass 5, count 0 2006.218.07:50:29.49#ibcon#about to read 3, iclass 5, count 0 2006.218.07:50:29.51#ibcon#read 3, iclass 5, count 0 2006.218.07:50:29.51#ibcon#about to read 4, iclass 5, count 0 2006.218.07:50:29.51#ibcon#read 4, iclass 5, count 0 2006.218.07:50:29.51#ibcon#about to read 5, iclass 5, count 0 2006.218.07:50:29.51#ibcon#read 5, iclass 5, count 0 2006.218.07:50:29.51#ibcon#about to read 6, iclass 5, count 0 2006.218.07:50:29.51#ibcon#read 6, iclass 5, count 0 2006.218.07:50:29.51#ibcon#end of sib2, iclass 5, count 0 2006.218.07:50:29.51#ibcon#*mode == 0, iclass 5, count 0 2006.218.07:50:29.51#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.218.07:50:29.51#ibcon#[25=USB\r\n] 2006.218.07:50:29.51#ibcon#*before write, iclass 5, count 0 2006.218.07:50:29.51#ibcon#enter sib2, iclass 5, count 0 2006.218.07:50:29.51#ibcon#flushed, iclass 5, count 0 2006.218.07:50:29.51#ibcon#about to write, iclass 5, count 0 2006.218.07:50:29.51#ibcon#wrote, iclass 5, count 0 2006.218.07:50:29.51#ibcon#about to read 3, iclass 5, count 0 2006.218.07:50:29.54#ibcon#read 3, iclass 5, count 0 2006.218.07:50:29.54#ibcon#about to read 4, iclass 5, count 0 2006.218.07:50:29.54#ibcon#read 4, iclass 5, count 0 2006.218.07:50:29.54#ibcon#about to read 5, iclass 5, count 0 2006.218.07:50:29.54#ibcon#read 5, iclass 5, count 0 2006.218.07:50:29.54#ibcon#about to read 6, iclass 5, count 0 2006.218.07:50:29.54#ibcon#read 6, iclass 5, count 0 2006.218.07:50:29.54#ibcon#end of sib2, iclass 5, count 0 2006.218.07:50:29.54#ibcon#*after write, iclass 5, count 0 2006.218.07:50:29.54#ibcon#*before return 0, iclass 5, count 0 2006.218.07:50:29.54#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.218.07:50:29.54#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.218.07:50:29.54#ibcon#about to clear, iclass 5 cls_cnt 0 2006.218.07:50:29.54#ibcon#cleared, iclass 5 cls_cnt 0 2006.218.07:50:29.54$vc4f8/valo=6,772.99 2006.218.07:50:29.55#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.218.07:50:29.55#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.218.07:50:29.55#ibcon#ireg 17 cls_cnt 0 2006.218.07:50:29.55#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.218.07:50:29.55#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.218.07:50:29.55#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.218.07:50:29.55#ibcon#enter wrdev, iclass 7, count 0 2006.218.07:50:29.55#ibcon#first serial, iclass 7, count 0 2006.218.07:50:29.55#ibcon#enter sib2, iclass 7, count 0 2006.218.07:50:29.55#ibcon#flushed, iclass 7, count 0 2006.218.07:50:29.55#ibcon#about to write, iclass 7, count 0 2006.218.07:50:29.55#ibcon#wrote, iclass 7, count 0 2006.218.07:50:29.55#ibcon#about to read 3, iclass 7, count 0 2006.218.07:50:29.56#ibcon#read 3, iclass 7, count 0 2006.218.07:50:29.56#ibcon#about to read 4, iclass 7, count 0 2006.218.07:50:29.56#ibcon#read 4, iclass 7, count 0 2006.218.07:50:29.56#ibcon#about to read 5, iclass 7, count 0 2006.218.07:50:29.56#ibcon#read 5, iclass 7, count 0 2006.218.07:50:29.56#ibcon#about to read 6, iclass 7, count 0 2006.218.07:50:29.56#ibcon#read 6, iclass 7, count 0 2006.218.07:50:29.56#ibcon#end of sib2, iclass 7, count 0 2006.218.07:50:29.56#ibcon#*mode == 0, iclass 7, count 0 2006.218.07:50:29.56#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.218.07:50:29.56#ibcon#[26=FRQ=06,772.99\r\n] 2006.218.07:50:29.56#ibcon#*before write, iclass 7, count 0 2006.218.07:50:29.56#ibcon#enter sib2, iclass 7, count 0 2006.218.07:50:29.56#ibcon#flushed, iclass 7, count 0 2006.218.07:50:29.56#ibcon#about to write, iclass 7, count 0 2006.218.07:50:29.56#ibcon#wrote, iclass 7, count 0 2006.218.07:50:29.56#ibcon#about to read 3, iclass 7, count 0 2006.218.07:50:29.61#ibcon#read 3, iclass 7, count 0 2006.218.07:50:29.61#ibcon#about to read 4, iclass 7, count 0 2006.218.07:50:29.61#ibcon#read 4, iclass 7, count 0 2006.218.07:50:29.61#ibcon#about to read 5, iclass 7, count 0 2006.218.07:50:29.61#ibcon#read 5, iclass 7, count 0 2006.218.07:50:29.61#ibcon#about to read 6, iclass 7, count 0 2006.218.07:50:29.61#ibcon#read 6, iclass 7, count 0 2006.218.07:50:29.61#ibcon#end of sib2, iclass 7, count 0 2006.218.07:50:29.61#ibcon#*after write, iclass 7, count 0 2006.218.07:50:29.61#ibcon#*before return 0, iclass 7, count 0 2006.218.07:50:29.61#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.218.07:50:29.61#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.218.07:50:29.61#ibcon#about to clear, iclass 7 cls_cnt 0 2006.218.07:50:29.61#ibcon#cleared, iclass 7 cls_cnt 0 2006.218.07:50:29.61$vc4f8/va=6,6 2006.218.07:50:29.61#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.218.07:50:29.61#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.218.07:50:29.61#ibcon#ireg 11 cls_cnt 2 2006.218.07:50:29.61#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.218.07:50:29.65#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.218.07:50:29.65#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.218.07:50:29.65#ibcon#enter wrdev, iclass 11, count 2 2006.218.07:50:29.65#ibcon#first serial, iclass 11, count 2 2006.218.07:50:29.65#ibcon#enter sib2, iclass 11, count 2 2006.218.07:50:29.65#ibcon#flushed, iclass 11, count 2 2006.218.07:50:29.65#ibcon#about to write, iclass 11, count 2 2006.218.07:50:29.65#ibcon#wrote, iclass 11, count 2 2006.218.07:50:29.65#ibcon#about to read 3, iclass 11, count 2 2006.218.07:50:29.67#ibcon#read 3, iclass 11, count 2 2006.218.07:50:29.67#ibcon#about to read 4, iclass 11, count 2 2006.218.07:50:29.67#ibcon#read 4, iclass 11, count 2 2006.218.07:50:29.67#ibcon#about to read 5, iclass 11, count 2 2006.218.07:50:29.67#ibcon#read 5, iclass 11, count 2 2006.218.07:50:29.67#ibcon#about to read 6, iclass 11, count 2 2006.218.07:50:29.67#ibcon#read 6, iclass 11, count 2 2006.218.07:50:29.67#ibcon#end of sib2, iclass 11, count 2 2006.218.07:50:29.67#ibcon#*mode == 0, iclass 11, count 2 2006.218.07:50:29.67#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.218.07:50:29.67#ibcon#[25=AT06-06\r\n] 2006.218.07:50:29.67#ibcon#*before write, iclass 11, count 2 2006.218.07:50:29.67#ibcon#enter sib2, iclass 11, count 2 2006.218.07:50:29.67#ibcon#flushed, iclass 11, count 2 2006.218.07:50:29.67#ibcon#about to write, iclass 11, count 2 2006.218.07:50:29.67#ibcon#wrote, iclass 11, count 2 2006.218.07:50:29.67#ibcon#about to read 3, iclass 11, count 2 2006.218.07:50:29.70#ibcon#read 3, iclass 11, count 2 2006.218.07:50:29.70#ibcon#about to read 4, iclass 11, count 2 2006.218.07:50:29.70#ibcon#read 4, iclass 11, count 2 2006.218.07:50:29.70#ibcon#about to read 5, iclass 11, count 2 2006.218.07:50:29.70#ibcon#read 5, iclass 11, count 2 2006.218.07:50:29.70#ibcon#about to read 6, iclass 11, count 2 2006.218.07:50:29.70#ibcon#read 6, iclass 11, count 2 2006.218.07:50:29.70#ibcon#end of sib2, iclass 11, count 2 2006.218.07:50:29.70#ibcon#*after write, iclass 11, count 2 2006.218.07:50:29.70#ibcon#*before return 0, iclass 11, count 2 2006.218.07:50:29.70#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.218.07:50:29.70#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.218.07:50:29.70#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.218.07:50:29.70#ibcon#ireg 7 cls_cnt 0 2006.218.07:50:29.70#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.218.07:50:29.82#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.218.07:50:29.82#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.218.07:50:29.82#ibcon#enter wrdev, iclass 11, count 0 2006.218.07:50:29.82#ibcon#first serial, iclass 11, count 0 2006.218.07:50:29.82#ibcon#enter sib2, iclass 11, count 0 2006.218.07:50:29.82#ibcon#flushed, iclass 11, count 0 2006.218.07:50:29.82#ibcon#about to write, iclass 11, count 0 2006.218.07:50:29.82#ibcon#wrote, iclass 11, count 0 2006.218.07:50:29.82#ibcon#about to read 3, iclass 11, count 0 2006.218.07:50:29.84#ibcon#read 3, iclass 11, count 0 2006.218.07:50:29.84#ibcon#about to read 4, iclass 11, count 0 2006.218.07:50:29.84#ibcon#read 4, iclass 11, count 0 2006.218.07:50:29.84#ibcon#about to read 5, iclass 11, count 0 2006.218.07:50:29.84#ibcon#read 5, iclass 11, count 0 2006.218.07:50:29.84#ibcon#about to read 6, iclass 11, count 0 2006.218.07:50:29.84#ibcon#read 6, iclass 11, count 0 2006.218.07:50:29.84#ibcon#end of sib2, iclass 11, count 0 2006.218.07:50:29.84#ibcon#*mode == 0, iclass 11, count 0 2006.218.07:50:29.84#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.218.07:50:29.84#ibcon#[25=USB\r\n] 2006.218.07:50:29.84#ibcon#*before write, iclass 11, count 0 2006.218.07:50:29.84#ibcon#enter sib2, iclass 11, count 0 2006.218.07:50:29.84#ibcon#flushed, iclass 11, count 0 2006.218.07:50:29.84#ibcon#about to write, iclass 11, count 0 2006.218.07:50:29.84#ibcon#wrote, iclass 11, count 0 2006.218.07:50:29.84#ibcon#about to read 3, iclass 11, count 0 2006.218.07:50:29.87#ibcon#read 3, iclass 11, count 0 2006.218.07:50:29.87#ibcon#about to read 4, iclass 11, count 0 2006.218.07:50:29.87#ibcon#read 4, iclass 11, count 0 2006.218.07:50:29.87#ibcon#about to read 5, iclass 11, count 0 2006.218.07:50:29.87#ibcon#read 5, iclass 11, count 0 2006.218.07:50:29.87#ibcon#about to read 6, iclass 11, count 0 2006.218.07:50:29.87#ibcon#read 6, iclass 11, count 0 2006.218.07:50:29.87#ibcon#end of sib2, iclass 11, count 0 2006.218.07:50:29.87#ibcon#*after write, iclass 11, count 0 2006.218.07:50:29.87#ibcon#*before return 0, iclass 11, count 0 2006.218.07:50:29.87#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.218.07:50:29.87#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.218.07:50:29.87#ibcon#about to clear, iclass 11 cls_cnt 0 2006.218.07:50:29.87#ibcon#cleared, iclass 11 cls_cnt 0 2006.218.07:50:29.87$vc4f8/valo=7,832.99 2006.218.07:50:29.88#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.218.07:50:29.88#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.218.07:50:29.88#ibcon#ireg 17 cls_cnt 0 2006.218.07:50:29.88#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.218.07:50:29.88#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.218.07:50:29.88#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.218.07:50:29.88#ibcon#enter wrdev, iclass 13, count 0 2006.218.07:50:29.88#ibcon#first serial, iclass 13, count 0 2006.218.07:50:29.88#ibcon#enter sib2, iclass 13, count 0 2006.218.07:50:29.88#ibcon#flushed, iclass 13, count 0 2006.218.07:50:29.88#ibcon#about to write, iclass 13, count 0 2006.218.07:50:29.88#ibcon#wrote, iclass 13, count 0 2006.218.07:50:29.88#ibcon#about to read 3, iclass 13, count 0 2006.218.07:50:29.89#ibcon#read 3, iclass 13, count 0 2006.218.07:50:29.89#ibcon#about to read 4, iclass 13, count 0 2006.218.07:50:29.89#ibcon#read 4, iclass 13, count 0 2006.218.07:50:29.89#ibcon#about to read 5, iclass 13, count 0 2006.218.07:50:29.89#ibcon#read 5, iclass 13, count 0 2006.218.07:50:29.89#ibcon#about to read 6, iclass 13, count 0 2006.218.07:50:29.89#ibcon#read 6, iclass 13, count 0 2006.218.07:50:29.89#ibcon#end of sib2, iclass 13, count 0 2006.218.07:50:29.89#ibcon#*mode == 0, iclass 13, count 0 2006.218.07:50:29.89#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.218.07:50:29.89#ibcon#[26=FRQ=07,832.99\r\n] 2006.218.07:50:29.89#ibcon#*before write, iclass 13, count 0 2006.218.07:50:29.89#ibcon#enter sib2, iclass 13, count 0 2006.218.07:50:29.89#ibcon#flushed, iclass 13, count 0 2006.218.07:50:29.89#ibcon#about to write, iclass 13, count 0 2006.218.07:50:29.89#ibcon#wrote, iclass 13, count 0 2006.218.07:50:29.89#ibcon#about to read 3, iclass 13, count 0 2006.218.07:50:29.93#ibcon#read 3, iclass 13, count 0 2006.218.07:50:29.93#ibcon#about to read 4, iclass 13, count 0 2006.218.07:50:29.93#ibcon#read 4, iclass 13, count 0 2006.218.07:50:29.93#ibcon#about to read 5, iclass 13, count 0 2006.218.07:50:29.93#ibcon#read 5, iclass 13, count 0 2006.218.07:50:29.93#ibcon#about to read 6, iclass 13, count 0 2006.218.07:50:29.93#ibcon#read 6, iclass 13, count 0 2006.218.07:50:29.93#ibcon#end of sib2, iclass 13, count 0 2006.218.07:50:29.93#ibcon#*after write, iclass 13, count 0 2006.218.07:50:29.93#ibcon#*before return 0, iclass 13, count 0 2006.218.07:50:29.93#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.218.07:50:29.93#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.218.07:50:29.93#ibcon#about to clear, iclass 13 cls_cnt 0 2006.218.07:50:29.93#ibcon#cleared, iclass 13 cls_cnt 0 2006.218.07:50:29.93$vc4f8/va=7,6 2006.218.07:50:29.94#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.218.07:50:29.94#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.218.07:50:29.94#ibcon#ireg 11 cls_cnt 2 2006.218.07:50:29.94#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.218.07:50:29.98#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.218.07:50:29.98#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.218.07:50:29.98#ibcon#enter wrdev, iclass 15, count 2 2006.218.07:50:29.98#ibcon#first serial, iclass 15, count 2 2006.218.07:50:29.98#ibcon#enter sib2, iclass 15, count 2 2006.218.07:50:29.98#ibcon#flushed, iclass 15, count 2 2006.218.07:50:29.98#ibcon#about to write, iclass 15, count 2 2006.218.07:50:29.98#ibcon#wrote, iclass 15, count 2 2006.218.07:50:29.98#ibcon#about to read 3, iclass 15, count 2 2006.218.07:50:30.00#ibcon#read 3, iclass 15, count 2 2006.218.07:50:30.00#ibcon#about to read 4, iclass 15, count 2 2006.218.07:50:30.00#ibcon#read 4, iclass 15, count 2 2006.218.07:50:30.00#ibcon#about to read 5, iclass 15, count 2 2006.218.07:50:30.00#ibcon#read 5, iclass 15, count 2 2006.218.07:50:30.00#ibcon#about to read 6, iclass 15, count 2 2006.218.07:50:30.00#ibcon#read 6, iclass 15, count 2 2006.218.07:50:30.00#ibcon#end of sib2, iclass 15, count 2 2006.218.07:50:30.00#ibcon#*mode == 0, iclass 15, count 2 2006.218.07:50:30.00#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.218.07:50:30.00#ibcon#[25=AT07-06\r\n] 2006.218.07:50:30.00#ibcon#*before write, iclass 15, count 2 2006.218.07:50:30.00#ibcon#enter sib2, iclass 15, count 2 2006.218.07:50:30.00#ibcon#flushed, iclass 15, count 2 2006.218.07:50:30.00#ibcon#about to write, iclass 15, count 2 2006.218.07:50:30.00#ibcon#wrote, iclass 15, count 2 2006.218.07:50:30.00#ibcon#about to read 3, iclass 15, count 2 2006.218.07:50:30.03#ibcon#read 3, iclass 15, count 2 2006.218.07:50:30.03#ibcon#about to read 4, iclass 15, count 2 2006.218.07:50:30.03#ibcon#read 4, iclass 15, count 2 2006.218.07:50:30.03#ibcon#about to read 5, iclass 15, count 2 2006.218.07:50:30.03#ibcon#read 5, iclass 15, count 2 2006.218.07:50:30.03#ibcon#about to read 6, iclass 15, count 2 2006.218.07:50:30.03#ibcon#read 6, iclass 15, count 2 2006.218.07:50:30.03#ibcon#end of sib2, iclass 15, count 2 2006.218.07:50:30.03#ibcon#*after write, iclass 15, count 2 2006.218.07:50:30.03#ibcon#*before return 0, iclass 15, count 2 2006.218.07:50:30.03#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.218.07:50:30.03#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.218.07:50:30.03#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.218.07:50:30.03#ibcon#ireg 7 cls_cnt 0 2006.218.07:50:30.03#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.218.07:50:30.15#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.218.07:50:30.15#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.218.07:50:30.15#ibcon#enter wrdev, iclass 15, count 0 2006.218.07:50:30.15#ibcon#first serial, iclass 15, count 0 2006.218.07:50:30.15#ibcon#enter sib2, iclass 15, count 0 2006.218.07:50:30.15#ibcon#flushed, iclass 15, count 0 2006.218.07:50:30.15#ibcon#about to write, iclass 15, count 0 2006.218.07:50:30.15#ibcon#wrote, iclass 15, count 0 2006.218.07:50:30.15#ibcon#about to read 3, iclass 15, count 0 2006.218.07:50:30.17#ibcon#read 3, iclass 15, count 0 2006.218.07:50:30.17#ibcon#about to read 4, iclass 15, count 0 2006.218.07:50:30.17#ibcon#read 4, iclass 15, count 0 2006.218.07:50:30.17#ibcon#about to read 5, iclass 15, count 0 2006.218.07:50:30.17#ibcon#read 5, iclass 15, count 0 2006.218.07:50:30.17#ibcon#about to read 6, iclass 15, count 0 2006.218.07:50:30.17#ibcon#read 6, iclass 15, count 0 2006.218.07:50:30.17#ibcon#end of sib2, iclass 15, count 0 2006.218.07:50:30.17#ibcon#*mode == 0, iclass 15, count 0 2006.218.07:50:30.17#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.218.07:50:30.17#ibcon#[25=USB\r\n] 2006.218.07:50:30.17#ibcon#*before write, iclass 15, count 0 2006.218.07:50:30.17#ibcon#enter sib2, iclass 15, count 0 2006.218.07:50:30.17#ibcon#flushed, iclass 15, count 0 2006.218.07:50:30.17#ibcon#about to write, iclass 15, count 0 2006.218.07:50:30.17#ibcon#wrote, iclass 15, count 0 2006.218.07:50:30.17#ibcon#about to read 3, iclass 15, count 0 2006.218.07:50:30.20#ibcon#read 3, iclass 15, count 0 2006.218.07:50:30.20#ibcon#about to read 4, iclass 15, count 0 2006.218.07:50:30.20#ibcon#read 4, iclass 15, count 0 2006.218.07:50:30.20#ibcon#about to read 5, iclass 15, count 0 2006.218.07:50:30.20#ibcon#read 5, iclass 15, count 0 2006.218.07:50:30.20#ibcon#about to read 6, iclass 15, count 0 2006.218.07:50:30.20#ibcon#read 6, iclass 15, count 0 2006.218.07:50:30.20#ibcon#end of sib2, iclass 15, count 0 2006.218.07:50:30.20#ibcon#*after write, iclass 15, count 0 2006.218.07:50:30.20#ibcon#*before return 0, iclass 15, count 0 2006.218.07:50:30.20#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.218.07:50:30.20#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.218.07:50:30.20#ibcon#about to clear, iclass 15 cls_cnt 0 2006.218.07:50:30.20#ibcon#cleared, iclass 15 cls_cnt 0 2006.218.07:50:30.20$vc4f8/valo=8,852.99 2006.218.07:50:30.21#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.218.07:50:30.21#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.218.07:50:30.21#ibcon#ireg 17 cls_cnt 0 2006.218.07:50:30.21#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.218.07:50:30.21#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.218.07:50:30.21#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.218.07:50:30.21#ibcon#enter wrdev, iclass 17, count 0 2006.218.07:50:30.21#ibcon#first serial, iclass 17, count 0 2006.218.07:50:30.21#ibcon#enter sib2, iclass 17, count 0 2006.218.07:50:30.21#ibcon#flushed, iclass 17, count 0 2006.218.07:50:30.21#ibcon#about to write, iclass 17, count 0 2006.218.07:50:30.21#ibcon#wrote, iclass 17, count 0 2006.218.07:50:30.21#ibcon#about to read 3, iclass 17, count 0 2006.218.07:50:30.22#ibcon#read 3, iclass 17, count 0 2006.218.07:50:30.22#ibcon#about to read 4, iclass 17, count 0 2006.218.07:50:30.22#ibcon#read 4, iclass 17, count 0 2006.218.07:50:30.22#ibcon#about to read 5, iclass 17, count 0 2006.218.07:50:30.22#ibcon#read 5, iclass 17, count 0 2006.218.07:50:30.22#ibcon#about to read 6, iclass 17, count 0 2006.218.07:50:30.22#ibcon#read 6, iclass 17, count 0 2006.218.07:50:30.22#ibcon#end of sib2, iclass 17, count 0 2006.218.07:50:30.22#ibcon#*mode == 0, iclass 17, count 0 2006.218.07:50:30.22#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.218.07:50:30.22#ibcon#[26=FRQ=08,852.99\r\n] 2006.218.07:50:30.22#ibcon#*before write, iclass 17, count 0 2006.218.07:50:30.22#ibcon#enter sib2, iclass 17, count 0 2006.218.07:50:30.22#ibcon#flushed, iclass 17, count 0 2006.218.07:50:30.22#ibcon#about to write, iclass 17, count 0 2006.218.07:50:30.22#ibcon#wrote, iclass 17, count 0 2006.218.07:50:30.22#ibcon#about to read 3, iclass 17, count 0 2006.218.07:50:30.26#ibcon#read 3, iclass 17, count 0 2006.218.07:50:30.26#ibcon#about to read 4, iclass 17, count 0 2006.218.07:50:30.26#ibcon#read 4, iclass 17, count 0 2006.218.07:50:30.26#ibcon#about to read 5, iclass 17, count 0 2006.218.07:50:30.26#ibcon#read 5, iclass 17, count 0 2006.218.07:50:30.26#ibcon#about to read 6, iclass 17, count 0 2006.218.07:50:30.26#ibcon#read 6, iclass 17, count 0 2006.218.07:50:30.26#ibcon#end of sib2, iclass 17, count 0 2006.218.07:50:30.26#ibcon#*after write, iclass 17, count 0 2006.218.07:50:30.26#ibcon#*before return 0, iclass 17, count 0 2006.218.07:50:30.26#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.218.07:50:30.26#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.218.07:50:30.26#ibcon#about to clear, iclass 17 cls_cnt 0 2006.218.07:50:30.26#ibcon#cleared, iclass 17 cls_cnt 0 2006.218.07:50:30.26$vc4f8/va=8,7 2006.218.07:50:30.27#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.218.07:50:30.27#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.218.07:50:30.27#ibcon#ireg 11 cls_cnt 2 2006.218.07:50:30.27#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.218.07:50:30.31#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.218.07:50:30.31#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.218.07:50:30.31#ibcon#enter wrdev, iclass 19, count 2 2006.218.07:50:30.31#ibcon#first serial, iclass 19, count 2 2006.218.07:50:30.31#ibcon#enter sib2, iclass 19, count 2 2006.218.07:50:30.31#ibcon#flushed, iclass 19, count 2 2006.218.07:50:30.31#ibcon#about to write, iclass 19, count 2 2006.218.07:50:30.31#ibcon#wrote, iclass 19, count 2 2006.218.07:50:30.31#ibcon#about to read 3, iclass 19, count 2 2006.218.07:50:30.33#ibcon#read 3, iclass 19, count 2 2006.218.07:50:30.33#ibcon#about to read 4, iclass 19, count 2 2006.218.07:50:30.33#ibcon#read 4, iclass 19, count 2 2006.218.07:50:30.33#ibcon#about to read 5, iclass 19, count 2 2006.218.07:50:30.33#ibcon#read 5, iclass 19, count 2 2006.218.07:50:30.33#ibcon#about to read 6, iclass 19, count 2 2006.218.07:50:30.33#ibcon#read 6, iclass 19, count 2 2006.218.07:50:30.33#ibcon#end of sib2, iclass 19, count 2 2006.218.07:50:30.33#ibcon#*mode == 0, iclass 19, count 2 2006.218.07:50:30.33#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.218.07:50:30.33#ibcon#[25=AT08-07\r\n] 2006.218.07:50:30.33#ibcon#*before write, iclass 19, count 2 2006.218.07:50:30.33#ibcon#enter sib2, iclass 19, count 2 2006.218.07:50:30.33#ibcon#flushed, iclass 19, count 2 2006.218.07:50:30.33#ibcon#about to write, iclass 19, count 2 2006.218.07:50:30.33#ibcon#wrote, iclass 19, count 2 2006.218.07:50:30.33#ibcon#about to read 3, iclass 19, count 2 2006.218.07:50:30.36#ibcon#read 3, iclass 19, count 2 2006.218.07:50:30.36#ibcon#about to read 4, iclass 19, count 2 2006.218.07:50:30.36#ibcon#read 4, iclass 19, count 2 2006.218.07:50:30.36#ibcon#about to read 5, iclass 19, count 2 2006.218.07:50:30.36#ibcon#read 5, iclass 19, count 2 2006.218.07:50:30.36#ibcon#about to read 6, iclass 19, count 2 2006.218.07:50:30.36#ibcon#read 6, iclass 19, count 2 2006.218.07:50:30.36#ibcon#end of sib2, iclass 19, count 2 2006.218.07:50:30.36#ibcon#*after write, iclass 19, count 2 2006.218.07:50:30.36#ibcon#*before return 0, iclass 19, count 2 2006.218.07:50:30.36#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.218.07:50:30.36#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.218.07:50:30.36#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.218.07:50:30.36#ibcon#ireg 7 cls_cnt 0 2006.218.07:50:30.36#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.218.07:50:30.48#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.218.07:50:30.48#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.218.07:50:30.48#ibcon#enter wrdev, iclass 19, count 0 2006.218.07:50:30.48#ibcon#first serial, iclass 19, count 0 2006.218.07:50:30.48#ibcon#enter sib2, iclass 19, count 0 2006.218.07:50:30.48#ibcon#flushed, iclass 19, count 0 2006.218.07:50:30.48#ibcon#about to write, iclass 19, count 0 2006.218.07:50:30.48#ibcon#wrote, iclass 19, count 0 2006.218.07:50:30.48#ibcon#about to read 3, iclass 19, count 0 2006.218.07:50:30.50#ibcon#read 3, iclass 19, count 0 2006.218.07:50:30.50#ibcon#about to read 4, iclass 19, count 0 2006.218.07:50:30.50#ibcon#read 4, iclass 19, count 0 2006.218.07:50:30.50#ibcon#about to read 5, iclass 19, count 0 2006.218.07:50:30.50#ibcon#read 5, iclass 19, count 0 2006.218.07:50:30.50#ibcon#about to read 6, iclass 19, count 0 2006.218.07:50:30.50#ibcon#read 6, iclass 19, count 0 2006.218.07:50:30.50#ibcon#end of sib2, iclass 19, count 0 2006.218.07:50:30.50#ibcon#*mode == 0, iclass 19, count 0 2006.218.07:50:30.50#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.218.07:50:30.50#ibcon#[25=USB\r\n] 2006.218.07:50:30.50#ibcon#*before write, iclass 19, count 0 2006.218.07:50:30.50#ibcon#enter sib2, iclass 19, count 0 2006.218.07:50:30.50#ibcon#flushed, iclass 19, count 0 2006.218.07:50:30.50#ibcon#about to write, iclass 19, count 0 2006.218.07:50:30.50#ibcon#wrote, iclass 19, count 0 2006.218.07:50:30.50#ibcon#about to read 3, iclass 19, count 0 2006.218.07:50:30.53#ibcon#read 3, iclass 19, count 0 2006.218.07:50:30.53#ibcon#about to read 4, iclass 19, count 0 2006.218.07:50:30.53#ibcon#read 4, iclass 19, count 0 2006.218.07:50:30.53#ibcon#about to read 5, iclass 19, count 0 2006.218.07:50:30.53#ibcon#read 5, iclass 19, count 0 2006.218.07:50:30.53#ibcon#about to read 6, iclass 19, count 0 2006.218.07:50:30.53#ibcon#read 6, iclass 19, count 0 2006.218.07:50:30.53#ibcon#end of sib2, iclass 19, count 0 2006.218.07:50:30.53#ibcon#*after write, iclass 19, count 0 2006.218.07:50:30.53#ibcon#*before return 0, iclass 19, count 0 2006.218.07:50:30.53#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.218.07:50:30.53#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.218.07:50:30.53#ibcon#about to clear, iclass 19 cls_cnt 0 2006.218.07:50:30.53#ibcon#cleared, iclass 19 cls_cnt 0 2006.218.07:50:30.53$vc4f8/vblo=1,632.99 2006.218.07:50:30.54#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.218.07:50:30.54#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.218.07:50:30.54#ibcon#ireg 17 cls_cnt 0 2006.218.07:50:30.54#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.218.07:50:30.54#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.218.07:50:30.54#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.218.07:50:30.54#ibcon#enter wrdev, iclass 21, count 0 2006.218.07:50:30.54#ibcon#first serial, iclass 21, count 0 2006.218.07:50:30.54#ibcon#enter sib2, iclass 21, count 0 2006.218.07:50:30.54#ibcon#flushed, iclass 21, count 0 2006.218.07:50:30.54#ibcon#about to write, iclass 21, count 0 2006.218.07:50:30.54#ibcon#wrote, iclass 21, count 0 2006.218.07:50:30.54#ibcon#about to read 3, iclass 21, count 0 2006.218.07:50:30.56#ibcon#read 3, iclass 21, count 0 2006.218.07:50:30.56#ibcon#about to read 4, iclass 21, count 0 2006.218.07:50:30.56#ibcon#read 4, iclass 21, count 0 2006.218.07:50:30.56#ibcon#about to read 5, iclass 21, count 0 2006.218.07:50:30.56#ibcon#read 5, iclass 21, count 0 2006.218.07:50:30.56#ibcon#about to read 6, iclass 21, count 0 2006.218.07:50:30.56#ibcon#read 6, iclass 21, count 0 2006.218.07:50:30.56#ibcon#end of sib2, iclass 21, count 0 2006.218.07:50:30.56#ibcon#*mode == 0, iclass 21, count 0 2006.218.07:50:30.56#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.218.07:50:30.56#ibcon#[28=FRQ=01,632.99\r\n] 2006.218.07:50:30.56#ibcon#*before write, iclass 21, count 0 2006.218.07:50:30.56#ibcon#enter sib2, iclass 21, count 0 2006.218.07:50:30.56#ibcon#flushed, iclass 21, count 0 2006.218.07:50:30.56#ibcon#about to write, iclass 21, count 0 2006.218.07:50:30.56#ibcon#wrote, iclass 21, count 0 2006.218.07:50:30.56#ibcon#about to read 3, iclass 21, count 0 2006.218.07:50:30.59#ibcon#read 3, iclass 21, count 0 2006.218.07:50:30.59#ibcon#about to read 4, iclass 21, count 0 2006.218.07:50:30.59#ibcon#read 4, iclass 21, count 0 2006.218.07:50:30.59#ibcon#about to read 5, iclass 21, count 0 2006.218.07:50:30.59#ibcon#read 5, iclass 21, count 0 2006.218.07:50:30.59#ibcon#about to read 6, iclass 21, count 0 2006.218.07:50:30.59#ibcon#read 6, iclass 21, count 0 2006.218.07:50:30.59#ibcon#end of sib2, iclass 21, count 0 2006.218.07:50:30.59#ibcon#*after write, iclass 21, count 0 2006.218.07:50:30.59#ibcon#*before return 0, iclass 21, count 0 2006.218.07:50:30.59#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.218.07:50:30.59#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.218.07:50:30.59#ibcon#about to clear, iclass 21 cls_cnt 0 2006.218.07:50:30.59#ibcon#cleared, iclass 21 cls_cnt 0 2006.218.07:50:30.59$vc4f8/vb=1,4 2006.218.07:50:30.60#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.218.07:50:30.60#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.218.07:50:30.60#ibcon#ireg 11 cls_cnt 2 2006.218.07:50:30.60#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.218.07:50:30.60#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.218.07:50:30.60#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.218.07:50:30.60#ibcon#enter wrdev, iclass 23, count 2 2006.218.07:50:30.60#ibcon#first serial, iclass 23, count 2 2006.218.07:50:30.60#ibcon#enter sib2, iclass 23, count 2 2006.218.07:50:30.60#ibcon#flushed, iclass 23, count 2 2006.218.07:50:30.60#ibcon#about to write, iclass 23, count 2 2006.218.07:50:30.60#ibcon#wrote, iclass 23, count 2 2006.218.07:50:30.60#ibcon#about to read 3, iclass 23, count 2 2006.218.07:50:30.61#ibcon#read 3, iclass 23, count 2 2006.218.07:50:30.61#ibcon#about to read 4, iclass 23, count 2 2006.218.07:50:30.61#ibcon#read 4, iclass 23, count 2 2006.218.07:50:30.61#ibcon#about to read 5, iclass 23, count 2 2006.218.07:50:30.61#ibcon#read 5, iclass 23, count 2 2006.218.07:50:30.61#ibcon#about to read 6, iclass 23, count 2 2006.218.07:50:30.61#ibcon#read 6, iclass 23, count 2 2006.218.07:50:30.61#ibcon#end of sib2, iclass 23, count 2 2006.218.07:50:30.61#ibcon#*mode == 0, iclass 23, count 2 2006.218.07:50:30.61#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.218.07:50:30.61#ibcon#[27=AT01-04\r\n] 2006.218.07:50:30.61#ibcon#*before write, iclass 23, count 2 2006.218.07:50:30.61#ibcon#enter sib2, iclass 23, count 2 2006.218.07:50:30.61#ibcon#flushed, iclass 23, count 2 2006.218.07:50:30.61#ibcon#about to write, iclass 23, count 2 2006.218.07:50:30.61#ibcon#wrote, iclass 23, count 2 2006.218.07:50:30.61#ibcon#about to read 3, iclass 23, count 2 2006.218.07:50:30.64#ibcon#read 3, iclass 23, count 2 2006.218.07:50:30.64#ibcon#about to read 4, iclass 23, count 2 2006.218.07:50:30.64#ibcon#read 4, iclass 23, count 2 2006.218.07:50:30.64#ibcon#about to read 5, iclass 23, count 2 2006.218.07:50:30.64#ibcon#read 5, iclass 23, count 2 2006.218.07:50:30.64#ibcon#about to read 6, iclass 23, count 2 2006.218.07:50:30.64#ibcon#read 6, iclass 23, count 2 2006.218.07:50:30.64#ibcon#end of sib2, iclass 23, count 2 2006.218.07:50:30.64#ibcon#*after write, iclass 23, count 2 2006.218.07:50:30.64#ibcon#*before return 0, iclass 23, count 2 2006.218.07:50:30.64#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.218.07:50:30.64#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.218.07:50:30.64#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.218.07:50:30.64#ibcon#ireg 7 cls_cnt 0 2006.218.07:50:30.64#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.218.07:50:30.76#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.218.07:50:30.76#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.218.07:50:30.76#ibcon#enter wrdev, iclass 23, count 0 2006.218.07:50:30.76#ibcon#first serial, iclass 23, count 0 2006.218.07:50:30.76#ibcon#enter sib2, iclass 23, count 0 2006.218.07:50:30.76#ibcon#flushed, iclass 23, count 0 2006.218.07:50:30.76#ibcon#about to write, iclass 23, count 0 2006.218.07:50:30.76#ibcon#wrote, iclass 23, count 0 2006.218.07:50:30.76#ibcon#about to read 3, iclass 23, count 0 2006.218.07:50:30.78#ibcon#read 3, iclass 23, count 0 2006.218.07:50:30.78#ibcon#about to read 4, iclass 23, count 0 2006.218.07:50:30.78#ibcon#read 4, iclass 23, count 0 2006.218.07:50:30.78#ibcon#about to read 5, iclass 23, count 0 2006.218.07:50:30.78#ibcon#read 5, iclass 23, count 0 2006.218.07:50:30.78#ibcon#about to read 6, iclass 23, count 0 2006.218.07:50:30.78#ibcon#read 6, iclass 23, count 0 2006.218.07:50:30.78#ibcon#end of sib2, iclass 23, count 0 2006.218.07:50:30.78#ibcon#*mode == 0, iclass 23, count 0 2006.218.07:50:30.78#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.218.07:50:30.78#ibcon#[27=USB\r\n] 2006.218.07:50:30.78#ibcon#*before write, iclass 23, count 0 2006.218.07:50:30.78#ibcon#enter sib2, iclass 23, count 0 2006.218.07:50:30.78#ibcon#flushed, iclass 23, count 0 2006.218.07:50:30.78#ibcon#about to write, iclass 23, count 0 2006.218.07:50:30.78#ibcon#wrote, iclass 23, count 0 2006.218.07:50:30.78#ibcon#about to read 3, iclass 23, count 0 2006.218.07:50:30.81#ibcon#read 3, iclass 23, count 0 2006.218.07:50:30.81#ibcon#about to read 4, iclass 23, count 0 2006.218.07:50:30.81#ibcon#read 4, iclass 23, count 0 2006.218.07:50:30.81#ibcon#about to read 5, iclass 23, count 0 2006.218.07:50:30.81#ibcon#read 5, iclass 23, count 0 2006.218.07:50:30.81#ibcon#about to read 6, iclass 23, count 0 2006.218.07:50:30.81#ibcon#read 6, iclass 23, count 0 2006.218.07:50:30.81#ibcon#end of sib2, iclass 23, count 0 2006.218.07:50:30.81#ibcon#*after write, iclass 23, count 0 2006.218.07:50:30.81#ibcon#*before return 0, iclass 23, count 0 2006.218.07:50:30.81#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.218.07:50:30.81#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.218.07:50:30.81#ibcon#about to clear, iclass 23 cls_cnt 0 2006.218.07:50:30.81#ibcon#cleared, iclass 23 cls_cnt 0 2006.218.07:50:30.81$vc4f8/vblo=2,640.99 2006.218.07:50:30.82#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.218.07:50:30.82#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.218.07:50:30.82#ibcon#ireg 17 cls_cnt 0 2006.218.07:50:30.82#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.218.07:50:30.82#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.218.07:50:30.82#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.218.07:50:30.82#ibcon#enter wrdev, iclass 25, count 0 2006.218.07:50:30.82#ibcon#first serial, iclass 25, count 0 2006.218.07:50:30.82#ibcon#enter sib2, iclass 25, count 0 2006.218.07:50:30.82#ibcon#flushed, iclass 25, count 0 2006.218.07:50:30.82#ibcon#about to write, iclass 25, count 0 2006.218.07:50:30.82#ibcon#wrote, iclass 25, count 0 2006.218.07:50:30.82#ibcon#about to read 3, iclass 25, count 0 2006.218.07:50:30.83#ibcon#read 3, iclass 25, count 0 2006.218.07:50:30.83#ibcon#about to read 4, iclass 25, count 0 2006.218.07:50:30.83#ibcon#read 4, iclass 25, count 0 2006.218.07:50:30.83#ibcon#about to read 5, iclass 25, count 0 2006.218.07:50:30.83#ibcon#read 5, iclass 25, count 0 2006.218.07:50:30.83#ibcon#about to read 6, iclass 25, count 0 2006.218.07:50:30.83#ibcon#read 6, iclass 25, count 0 2006.218.07:50:30.83#ibcon#end of sib2, iclass 25, count 0 2006.218.07:50:30.83#ibcon#*mode == 0, iclass 25, count 0 2006.218.07:50:30.83#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.218.07:50:30.83#ibcon#[28=FRQ=02,640.99\r\n] 2006.218.07:50:30.83#ibcon#*before write, iclass 25, count 0 2006.218.07:50:30.83#ibcon#enter sib2, iclass 25, count 0 2006.218.07:50:30.83#ibcon#flushed, iclass 25, count 0 2006.218.07:50:30.83#ibcon#about to write, iclass 25, count 0 2006.218.07:50:30.83#ibcon#wrote, iclass 25, count 0 2006.218.07:50:30.83#ibcon#about to read 3, iclass 25, count 0 2006.218.07:50:30.87#ibcon#read 3, iclass 25, count 0 2006.218.07:50:30.87#ibcon#about to read 4, iclass 25, count 0 2006.218.07:50:30.87#ibcon#read 4, iclass 25, count 0 2006.218.07:50:30.87#ibcon#about to read 5, iclass 25, count 0 2006.218.07:50:30.87#ibcon#read 5, iclass 25, count 0 2006.218.07:50:30.87#ibcon#about to read 6, iclass 25, count 0 2006.218.07:50:30.87#ibcon#read 6, iclass 25, count 0 2006.218.07:50:30.87#ibcon#end of sib2, iclass 25, count 0 2006.218.07:50:30.87#ibcon#*after write, iclass 25, count 0 2006.218.07:50:30.87#ibcon#*before return 0, iclass 25, count 0 2006.218.07:50:30.87#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.218.07:50:30.87#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.218.07:50:30.87#ibcon#about to clear, iclass 25 cls_cnt 0 2006.218.07:50:30.87#ibcon#cleared, iclass 25 cls_cnt 0 2006.218.07:50:30.87$vc4f8/vb=2,4 2006.218.07:50:30.88#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.218.07:50:30.88#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.218.07:50:30.88#ibcon#ireg 11 cls_cnt 2 2006.218.07:50:30.88#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.218.07:50:30.92#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.218.07:50:30.92#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.218.07:50:30.92#ibcon#enter wrdev, iclass 27, count 2 2006.218.07:50:30.92#ibcon#first serial, iclass 27, count 2 2006.218.07:50:30.92#ibcon#enter sib2, iclass 27, count 2 2006.218.07:50:30.92#ibcon#flushed, iclass 27, count 2 2006.218.07:50:30.92#ibcon#about to write, iclass 27, count 2 2006.218.07:50:30.92#ibcon#wrote, iclass 27, count 2 2006.218.07:50:30.92#ibcon#about to read 3, iclass 27, count 2 2006.218.07:50:30.94#ibcon#read 3, iclass 27, count 2 2006.218.07:50:30.94#ibcon#about to read 4, iclass 27, count 2 2006.218.07:50:30.94#ibcon#read 4, iclass 27, count 2 2006.218.07:50:30.94#ibcon#about to read 5, iclass 27, count 2 2006.218.07:50:30.94#ibcon#read 5, iclass 27, count 2 2006.218.07:50:30.94#ibcon#about to read 6, iclass 27, count 2 2006.218.07:50:30.94#ibcon#read 6, iclass 27, count 2 2006.218.07:50:30.94#ibcon#end of sib2, iclass 27, count 2 2006.218.07:50:30.94#ibcon#*mode == 0, iclass 27, count 2 2006.218.07:50:30.94#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.218.07:50:30.94#ibcon#[27=AT02-04\r\n] 2006.218.07:50:30.94#ibcon#*before write, iclass 27, count 2 2006.218.07:50:30.94#ibcon#enter sib2, iclass 27, count 2 2006.218.07:50:30.94#ibcon#flushed, iclass 27, count 2 2006.218.07:50:30.94#ibcon#about to write, iclass 27, count 2 2006.218.07:50:30.94#ibcon#wrote, iclass 27, count 2 2006.218.07:50:30.94#ibcon#about to read 3, iclass 27, count 2 2006.218.07:50:30.97#ibcon#read 3, iclass 27, count 2 2006.218.07:50:30.97#ibcon#about to read 4, iclass 27, count 2 2006.218.07:50:30.97#ibcon#read 4, iclass 27, count 2 2006.218.07:50:30.97#ibcon#about to read 5, iclass 27, count 2 2006.218.07:50:30.97#ibcon#read 5, iclass 27, count 2 2006.218.07:50:30.97#ibcon#about to read 6, iclass 27, count 2 2006.218.07:50:30.97#ibcon#read 6, iclass 27, count 2 2006.218.07:50:30.97#ibcon#end of sib2, iclass 27, count 2 2006.218.07:50:30.97#ibcon#*after write, iclass 27, count 2 2006.218.07:50:30.97#ibcon#*before return 0, iclass 27, count 2 2006.218.07:50:30.97#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.218.07:50:30.97#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.218.07:50:30.97#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.218.07:50:30.97#ibcon#ireg 7 cls_cnt 0 2006.218.07:50:30.97#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.218.07:50:31.09#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.218.07:50:31.09#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.218.07:50:31.09#ibcon#enter wrdev, iclass 27, count 0 2006.218.07:50:31.09#ibcon#first serial, iclass 27, count 0 2006.218.07:50:31.09#ibcon#enter sib2, iclass 27, count 0 2006.218.07:50:31.09#ibcon#flushed, iclass 27, count 0 2006.218.07:50:31.09#ibcon#about to write, iclass 27, count 0 2006.218.07:50:31.09#ibcon#wrote, iclass 27, count 0 2006.218.07:50:31.09#ibcon#about to read 3, iclass 27, count 0 2006.218.07:50:31.11#ibcon#read 3, iclass 27, count 0 2006.218.07:50:31.11#ibcon#about to read 4, iclass 27, count 0 2006.218.07:50:31.11#ibcon#read 4, iclass 27, count 0 2006.218.07:50:31.11#ibcon#about to read 5, iclass 27, count 0 2006.218.07:50:31.11#ibcon#read 5, iclass 27, count 0 2006.218.07:50:31.11#ibcon#about to read 6, iclass 27, count 0 2006.218.07:50:31.11#ibcon#read 6, iclass 27, count 0 2006.218.07:50:31.11#ibcon#end of sib2, iclass 27, count 0 2006.218.07:50:31.11#ibcon#*mode == 0, iclass 27, count 0 2006.218.07:50:31.11#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.218.07:50:31.11#ibcon#[27=USB\r\n] 2006.218.07:50:31.11#ibcon#*before write, iclass 27, count 0 2006.218.07:50:31.11#ibcon#enter sib2, iclass 27, count 0 2006.218.07:50:31.11#ibcon#flushed, iclass 27, count 0 2006.218.07:50:31.11#ibcon#about to write, iclass 27, count 0 2006.218.07:50:31.11#ibcon#wrote, iclass 27, count 0 2006.218.07:50:31.11#ibcon#about to read 3, iclass 27, count 0 2006.218.07:50:31.15#ibcon#read 3, iclass 27, count 0 2006.218.07:50:31.15#ibcon#about to read 4, iclass 27, count 0 2006.218.07:50:31.15#ibcon#read 4, iclass 27, count 0 2006.218.07:50:31.15#ibcon#about to read 5, iclass 27, count 0 2006.218.07:50:31.15#ibcon#read 5, iclass 27, count 0 2006.218.07:50:31.15#ibcon#about to read 6, iclass 27, count 0 2006.218.07:50:31.15#ibcon#read 6, iclass 27, count 0 2006.218.07:50:31.15#ibcon#end of sib2, iclass 27, count 0 2006.218.07:50:31.15#ibcon#*after write, iclass 27, count 0 2006.218.07:50:31.15#ibcon#*before return 0, iclass 27, count 0 2006.218.07:50:31.15#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.218.07:50:31.15#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.218.07:50:31.15#ibcon#about to clear, iclass 27 cls_cnt 0 2006.218.07:50:31.15#ibcon#cleared, iclass 27 cls_cnt 0 2006.218.07:50:31.15$vc4f8/vblo=3,656.99 2006.218.07:50:31.15#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.218.07:50:31.15#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.218.07:50:31.15#ibcon#ireg 17 cls_cnt 0 2006.218.07:50:31.15#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.218.07:50:31.15#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.218.07:50:31.15#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.218.07:50:31.15#ibcon#enter wrdev, iclass 29, count 0 2006.218.07:50:31.15#ibcon#first serial, iclass 29, count 0 2006.218.07:50:31.15#ibcon#enter sib2, iclass 29, count 0 2006.218.07:50:31.15#ibcon#flushed, iclass 29, count 0 2006.218.07:50:31.15#ibcon#about to write, iclass 29, count 0 2006.218.07:50:31.15#ibcon#wrote, iclass 29, count 0 2006.218.07:50:31.15#ibcon#about to read 3, iclass 29, count 0 2006.218.07:50:31.16#ibcon#read 3, iclass 29, count 0 2006.218.07:50:31.16#ibcon#about to read 4, iclass 29, count 0 2006.218.07:50:31.16#ibcon#read 4, iclass 29, count 0 2006.218.07:50:31.16#ibcon#about to read 5, iclass 29, count 0 2006.218.07:50:31.16#ibcon#read 5, iclass 29, count 0 2006.218.07:50:31.16#ibcon#about to read 6, iclass 29, count 0 2006.218.07:50:31.16#ibcon#read 6, iclass 29, count 0 2006.218.07:50:31.16#ibcon#end of sib2, iclass 29, count 0 2006.218.07:50:31.16#ibcon#*mode == 0, iclass 29, count 0 2006.218.07:50:31.16#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.218.07:50:31.16#ibcon#[28=FRQ=03,656.99\r\n] 2006.218.07:50:31.16#ibcon#*before write, iclass 29, count 0 2006.218.07:50:31.16#ibcon#enter sib2, iclass 29, count 0 2006.218.07:50:31.16#ibcon#flushed, iclass 29, count 0 2006.218.07:50:31.16#ibcon#about to write, iclass 29, count 0 2006.218.07:50:31.16#ibcon#wrote, iclass 29, count 0 2006.218.07:50:31.16#ibcon#about to read 3, iclass 29, count 0 2006.218.07:50:31.20#ibcon#read 3, iclass 29, count 0 2006.218.07:50:31.20#ibcon#about to read 4, iclass 29, count 0 2006.218.07:50:31.20#ibcon#read 4, iclass 29, count 0 2006.218.07:50:31.20#ibcon#about to read 5, iclass 29, count 0 2006.218.07:50:31.20#ibcon#read 5, iclass 29, count 0 2006.218.07:50:31.20#ibcon#about to read 6, iclass 29, count 0 2006.218.07:50:31.20#ibcon#read 6, iclass 29, count 0 2006.218.07:50:31.20#ibcon#end of sib2, iclass 29, count 0 2006.218.07:50:31.20#ibcon#*after write, iclass 29, count 0 2006.218.07:50:31.20#ibcon#*before return 0, iclass 29, count 0 2006.218.07:50:31.20#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.218.07:50:31.20#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.218.07:50:31.20#ibcon#about to clear, iclass 29 cls_cnt 0 2006.218.07:50:31.20#ibcon#cleared, iclass 29 cls_cnt 0 2006.218.07:50:31.20$vc4f8/vb=3,4 2006.218.07:50:31.21#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.218.07:50:31.21#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.218.07:50:31.21#ibcon#ireg 11 cls_cnt 2 2006.218.07:50:31.21#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.218.07:50:31.26#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.218.07:50:31.26#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.218.07:50:31.26#ibcon#enter wrdev, iclass 31, count 2 2006.218.07:50:31.26#ibcon#first serial, iclass 31, count 2 2006.218.07:50:31.26#ibcon#enter sib2, iclass 31, count 2 2006.218.07:50:31.26#ibcon#flushed, iclass 31, count 2 2006.218.07:50:31.26#ibcon#about to write, iclass 31, count 2 2006.218.07:50:31.26#ibcon#wrote, iclass 31, count 2 2006.218.07:50:31.26#ibcon#about to read 3, iclass 31, count 2 2006.218.07:50:31.28#ibcon#read 3, iclass 31, count 2 2006.218.07:50:31.28#ibcon#about to read 4, iclass 31, count 2 2006.218.07:50:31.28#ibcon#read 4, iclass 31, count 2 2006.218.07:50:31.28#ibcon#about to read 5, iclass 31, count 2 2006.218.07:50:31.28#ibcon#read 5, iclass 31, count 2 2006.218.07:50:31.28#ibcon#about to read 6, iclass 31, count 2 2006.218.07:50:31.28#ibcon#read 6, iclass 31, count 2 2006.218.07:50:31.28#ibcon#end of sib2, iclass 31, count 2 2006.218.07:50:31.28#ibcon#*mode == 0, iclass 31, count 2 2006.218.07:50:31.28#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.218.07:50:31.28#ibcon#[27=AT03-04\r\n] 2006.218.07:50:31.28#ibcon#*before write, iclass 31, count 2 2006.218.07:50:31.28#ibcon#enter sib2, iclass 31, count 2 2006.218.07:50:31.28#ibcon#flushed, iclass 31, count 2 2006.218.07:50:31.28#ibcon#about to write, iclass 31, count 2 2006.218.07:50:31.28#ibcon#wrote, iclass 31, count 2 2006.218.07:50:31.28#ibcon#about to read 3, iclass 31, count 2 2006.218.07:50:31.29#abcon#<5=/06 3.9 6.9 31.18 741007.4\r\n> 2006.218.07:50:31.31#abcon#{5=INTERFACE CLEAR} 2006.218.07:50:31.31#ibcon#read 3, iclass 31, count 2 2006.218.07:50:31.31#ibcon#about to read 4, iclass 31, count 2 2006.218.07:50:31.31#ibcon#read 4, iclass 31, count 2 2006.218.07:50:31.31#ibcon#about to read 5, iclass 31, count 2 2006.218.07:50:31.31#ibcon#read 5, iclass 31, count 2 2006.218.07:50:31.31#ibcon#about to read 6, iclass 31, count 2 2006.218.07:50:31.31#ibcon#read 6, iclass 31, count 2 2006.218.07:50:31.31#ibcon#end of sib2, iclass 31, count 2 2006.218.07:50:31.31#ibcon#*after write, iclass 31, count 2 2006.218.07:50:31.31#ibcon#*before return 0, iclass 31, count 2 2006.218.07:50:31.31#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.218.07:50:31.31#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.218.07:50:31.31#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.218.07:50:31.31#ibcon#ireg 7 cls_cnt 0 2006.218.07:50:31.32#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.218.07:50:31.37#abcon#[5=S1D000X0/0*\r\n] 2006.218.07:50:31.42#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.218.07:50:31.42#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.218.07:50:31.42#ibcon#enter wrdev, iclass 31, count 0 2006.218.07:50:31.42#ibcon#first serial, iclass 31, count 0 2006.218.07:50:31.42#ibcon#enter sib2, iclass 31, count 0 2006.218.07:50:31.42#ibcon#flushed, iclass 31, count 0 2006.218.07:50:31.42#ibcon#about to write, iclass 31, count 0 2006.218.07:50:31.42#ibcon#wrote, iclass 31, count 0 2006.218.07:50:31.42#ibcon#about to read 3, iclass 31, count 0 2006.218.07:50:31.44#ibcon#read 3, iclass 31, count 0 2006.218.07:50:31.44#ibcon#about to read 4, iclass 31, count 0 2006.218.07:50:31.44#ibcon#read 4, iclass 31, count 0 2006.218.07:50:31.44#ibcon#about to read 5, iclass 31, count 0 2006.218.07:50:31.44#ibcon#read 5, iclass 31, count 0 2006.218.07:50:31.44#ibcon#about to read 6, iclass 31, count 0 2006.218.07:50:31.44#ibcon#read 6, iclass 31, count 0 2006.218.07:50:31.44#ibcon#end of sib2, iclass 31, count 0 2006.218.07:50:31.44#ibcon#*mode == 0, iclass 31, count 0 2006.218.07:50:31.44#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.218.07:50:31.44#ibcon#[27=USB\r\n] 2006.218.07:50:31.44#ibcon#*before write, iclass 31, count 0 2006.218.07:50:31.44#ibcon#enter sib2, iclass 31, count 0 2006.218.07:50:31.44#ibcon#flushed, iclass 31, count 0 2006.218.07:50:31.44#ibcon#about to write, iclass 31, count 0 2006.218.07:50:31.44#ibcon#wrote, iclass 31, count 0 2006.218.07:50:31.44#ibcon#about to read 3, iclass 31, count 0 2006.218.07:50:31.47#ibcon#read 3, iclass 31, count 0 2006.218.07:50:31.47#ibcon#about to read 4, iclass 31, count 0 2006.218.07:50:31.47#ibcon#read 4, iclass 31, count 0 2006.218.07:50:31.47#ibcon#about to read 5, iclass 31, count 0 2006.218.07:50:31.47#ibcon#read 5, iclass 31, count 0 2006.218.07:50:31.47#ibcon#about to read 6, iclass 31, count 0 2006.218.07:50:31.47#ibcon#read 6, iclass 31, count 0 2006.218.07:50:31.47#ibcon#end of sib2, iclass 31, count 0 2006.218.07:50:31.47#ibcon#*after write, iclass 31, count 0 2006.218.07:50:31.47#ibcon#*before return 0, iclass 31, count 0 2006.218.07:50:31.47#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.218.07:50:31.47#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.218.07:50:31.47#ibcon#about to clear, iclass 31 cls_cnt 0 2006.218.07:50:31.47#ibcon#cleared, iclass 31 cls_cnt 0 2006.218.07:50:31.47$vc4f8/vblo=4,712.99 2006.218.07:50:31.48#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.218.07:50:31.48#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.218.07:50:31.48#ibcon#ireg 17 cls_cnt 0 2006.218.07:50:31.48#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.218.07:50:31.48#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.218.07:50:31.48#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.218.07:50:31.48#ibcon#enter wrdev, iclass 37, count 0 2006.218.07:50:31.48#ibcon#first serial, iclass 37, count 0 2006.218.07:50:31.48#ibcon#enter sib2, iclass 37, count 0 2006.218.07:50:31.48#ibcon#flushed, iclass 37, count 0 2006.218.07:50:31.48#ibcon#about to write, iclass 37, count 0 2006.218.07:50:31.48#ibcon#wrote, iclass 37, count 0 2006.218.07:50:31.48#ibcon#about to read 3, iclass 37, count 0 2006.218.07:50:31.49#ibcon#read 3, iclass 37, count 0 2006.218.07:50:31.49#ibcon#about to read 4, iclass 37, count 0 2006.218.07:50:31.49#ibcon#read 4, iclass 37, count 0 2006.218.07:50:31.49#ibcon#about to read 5, iclass 37, count 0 2006.218.07:50:31.49#ibcon#read 5, iclass 37, count 0 2006.218.07:50:31.49#ibcon#about to read 6, iclass 37, count 0 2006.218.07:50:31.49#ibcon#read 6, iclass 37, count 0 2006.218.07:50:31.49#ibcon#end of sib2, iclass 37, count 0 2006.218.07:50:31.49#ibcon#*mode == 0, iclass 37, count 0 2006.218.07:50:31.49#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.218.07:50:31.49#ibcon#[28=FRQ=04,712.99\r\n] 2006.218.07:50:31.49#ibcon#*before write, iclass 37, count 0 2006.218.07:50:31.49#ibcon#enter sib2, iclass 37, count 0 2006.218.07:50:31.49#ibcon#flushed, iclass 37, count 0 2006.218.07:50:31.49#ibcon#about to write, iclass 37, count 0 2006.218.07:50:31.49#ibcon#wrote, iclass 37, count 0 2006.218.07:50:31.49#ibcon#about to read 3, iclass 37, count 0 2006.218.07:50:31.54#ibcon#read 3, iclass 37, count 0 2006.218.07:50:31.54#ibcon#about to read 4, iclass 37, count 0 2006.218.07:50:31.54#ibcon#read 4, iclass 37, count 0 2006.218.07:50:31.54#ibcon#about to read 5, iclass 37, count 0 2006.218.07:50:31.54#ibcon#read 5, iclass 37, count 0 2006.218.07:50:31.54#ibcon#about to read 6, iclass 37, count 0 2006.218.07:50:31.54#ibcon#read 6, iclass 37, count 0 2006.218.07:50:31.54#ibcon#end of sib2, iclass 37, count 0 2006.218.07:50:31.54#ibcon#*after write, iclass 37, count 0 2006.218.07:50:31.54#ibcon#*before return 0, iclass 37, count 0 2006.218.07:50:31.54#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.218.07:50:31.54#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.218.07:50:31.54#ibcon#about to clear, iclass 37 cls_cnt 0 2006.218.07:50:31.54#ibcon#cleared, iclass 37 cls_cnt 0 2006.218.07:50:31.54$vc4f8/vb=4,4 2006.218.07:50:31.54#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.218.07:50:31.54#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.218.07:50:31.54#ibcon#ireg 11 cls_cnt 2 2006.218.07:50:31.54#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.218.07:50:31.58#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.218.07:50:31.58#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.218.07:50:31.58#ibcon#enter wrdev, iclass 39, count 2 2006.218.07:50:31.58#ibcon#first serial, iclass 39, count 2 2006.218.07:50:31.58#ibcon#enter sib2, iclass 39, count 2 2006.218.07:50:31.58#ibcon#flushed, iclass 39, count 2 2006.218.07:50:31.58#ibcon#about to write, iclass 39, count 2 2006.218.07:50:31.58#ibcon#wrote, iclass 39, count 2 2006.218.07:50:31.58#ibcon#about to read 3, iclass 39, count 2 2006.218.07:50:31.60#ibcon#read 3, iclass 39, count 2 2006.218.07:50:31.60#ibcon#about to read 4, iclass 39, count 2 2006.218.07:50:31.60#ibcon#read 4, iclass 39, count 2 2006.218.07:50:31.60#ibcon#about to read 5, iclass 39, count 2 2006.218.07:50:31.60#ibcon#read 5, iclass 39, count 2 2006.218.07:50:31.60#ibcon#about to read 6, iclass 39, count 2 2006.218.07:50:31.60#ibcon#read 6, iclass 39, count 2 2006.218.07:50:31.60#ibcon#end of sib2, iclass 39, count 2 2006.218.07:50:31.60#ibcon#*mode == 0, iclass 39, count 2 2006.218.07:50:31.60#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.218.07:50:31.60#ibcon#[27=AT04-04\r\n] 2006.218.07:50:31.60#ibcon#*before write, iclass 39, count 2 2006.218.07:50:31.60#ibcon#enter sib2, iclass 39, count 2 2006.218.07:50:31.60#ibcon#flushed, iclass 39, count 2 2006.218.07:50:31.60#ibcon#about to write, iclass 39, count 2 2006.218.07:50:31.60#ibcon#wrote, iclass 39, count 2 2006.218.07:50:31.60#ibcon#about to read 3, iclass 39, count 2 2006.218.07:50:31.63#ibcon#read 3, iclass 39, count 2 2006.218.07:50:31.63#ibcon#about to read 4, iclass 39, count 2 2006.218.07:50:31.63#ibcon#read 4, iclass 39, count 2 2006.218.07:50:31.63#ibcon#about to read 5, iclass 39, count 2 2006.218.07:50:31.63#ibcon#read 5, iclass 39, count 2 2006.218.07:50:31.63#ibcon#about to read 6, iclass 39, count 2 2006.218.07:50:31.63#ibcon#read 6, iclass 39, count 2 2006.218.07:50:31.63#ibcon#end of sib2, iclass 39, count 2 2006.218.07:50:31.63#ibcon#*after write, iclass 39, count 2 2006.218.07:50:31.63#ibcon#*before return 0, iclass 39, count 2 2006.218.07:50:31.63#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.218.07:50:31.63#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.218.07:50:31.63#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.218.07:50:31.63#ibcon#ireg 7 cls_cnt 0 2006.218.07:50:31.63#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.218.07:50:31.75#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.218.07:50:31.75#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.218.07:50:31.75#ibcon#enter wrdev, iclass 39, count 0 2006.218.07:50:31.75#ibcon#first serial, iclass 39, count 0 2006.218.07:50:31.75#ibcon#enter sib2, iclass 39, count 0 2006.218.07:50:31.75#ibcon#flushed, iclass 39, count 0 2006.218.07:50:31.75#ibcon#about to write, iclass 39, count 0 2006.218.07:50:31.75#ibcon#wrote, iclass 39, count 0 2006.218.07:50:31.75#ibcon#about to read 3, iclass 39, count 0 2006.218.07:50:31.77#ibcon#read 3, iclass 39, count 0 2006.218.07:50:31.77#ibcon#about to read 4, iclass 39, count 0 2006.218.07:50:31.77#ibcon#read 4, iclass 39, count 0 2006.218.07:50:31.77#ibcon#about to read 5, iclass 39, count 0 2006.218.07:50:31.77#ibcon#read 5, iclass 39, count 0 2006.218.07:50:31.77#ibcon#about to read 6, iclass 39, count 0 2006.218.07:50:31.77#ibcon#read 6, iclass 39, count 0 2006.218.07:50:31.77#ibcon#end of sib2, iclass 39, count 0 2006.218.07:50:31.77#ibcon#*mode == 0, iclass 39, count 0 2006.218.07:50:31.77#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.218.07:50:31.77#ibcon#[27=USB\r\n] 2006.218.07:50:31.77#ibcon#*before write, iclass 39, count 0 2006.218.07:50:31.77#ibcon#enter sib2, iclass 39, count 0 2006.218.07:50:31.77#ibcon#flushed, iclass 39, count 0 2006.218.07:50:31.77#ibcon#about to write, iclass 39, count 0 2006.218.07:50:31.77#ibcon#wrote, iclass 39, count 0 2006.218.07:50:31.77#ibcon#about to read 3, iclass 39, count 0 2006.218.07:50:31.80#ibcon#read 3, iclass 39, count 0 2006.218.07:50:31.80#ibcon#about to read 4, iclass 39, count 0 2006.218.07:50:31.80#ibcon#read 4, iclass 39, count 0 2006.218.07:50:31.80#ibcon#about to read 5, iclass 39, count 0 2006.218.07:50:31.80#ibcon#read 5, iclass 39, count 0 2006.218.07:50:31.80#ibcon#about to read 6, iclass 39, count 0 2006.218.07:50:31.80#ibcon#read 6, iclass 39, count 0 2006.218.07:50:31.80#ibcon#end of sib2, iclass 39, count 0 2006.218.07:50:31.80#ibcon#*after write, iclass 39, count 0 2006.218.07:50:31.80#ibcon#*before return 0, iclass 39, count 0 2006.218.07:50:31.80#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.218.07:50:31.80#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.218.07:50:31.80#ibcon#about to clear, iclass 39 cls_cnt 0 2006.218.07:50:31.80#ibcon#cleared, iclass 39 cls_cnt 0 2006.218.07:50:31.80$vc4f8/vblo=5,744.99 2006.218.07:50:31.81#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.218.07:50:31.81#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.218.07:50:31.81#ibcon#ireg 17 cls_cnt 0 2006.218.07:50:31.81#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.218.07:50:31.81#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.218.07:50:31.81#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.218.07:50:31.81#ibcon#enter wrdev, iclass 3, count 0 2006.218.07:50:31.81#ibcon#first serial, iclass 3, count 0 2006.218.07:50:31.81#ibcon#enter sib2, iclass 3, count 0 2006.218.07:50:31.81#ibcon#flushed, iclass 3, count 0 2006.218.07:50:31.81#ibcon#about to write, iclass 3, count 0 2006.218.07:50:31.81#ibcon#wrote, iclass 3, count 0 2006.218.07:50:31.81#ibcon#about to read 3, iclass 3, count 0 2006.218.07:50:31.82#ibcon#read 3, iclass 3, count 0 2006.218.07:50:31.82#ibcon#about to read 4, iclass 3, count 0 2006.218.07:50:31.82#ibcon#read 4, iclass 3, count 0 2006.218.07:50:31.82#ibcon#about to read 5, iclass 3, count 0 2006.218.07:50:31.82#ibcon#read 5, iclass 3, count 0 2006.218.07:50:31.82#ibcon#about to read 6, iclass 3, count 0 2006.218.07:50:31.82#ibcon#read 6, iclass 3, count 0 2006.218.07:50:31.82#ibcon#end of sib2, iclass 3, count 0 2006.218.07:50:31.82#ibcon#*mode == 0, iclass 3, count 0 2006.218.07:50:31.82#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.218.07:50:31.82#ibcon#[28=FRQ=05,744.99\r\n] 2006.218.07:50:31.82#ibcon#*before write, iclass 3, count 0 2006.218.07:50:31.82#ibcon#enter sib2, iclass 3, count 0 2006.218.07:50:31.82#ibcon#flushed, iclass 3, count 0 2006.218.07:50:31.82#ibcon#about to write, iclass 3, count 0 2006.218.07:50:31.82#ibcon#wrote, iclass 3, count 0 2006.218.07:50:31.82#ibcon#about to read 3, iclass 3, count 0 2006.218.07:50:31.86#ibcon#read 3, iclass 3, count 0 2006.218.07:50:31.86#ibcon#about to read 4, iclass 3, count 0 2006.218.07:50:31.86#ibcon#read 4, iclass 3, count 0 2006.218.07:50:31.86#ibcon#about to read 5, iclass 3, count 0 2006.218.07:50:31.86#ibcon#read 5, iclass 3, count 0 2006.218.07:50:31.86#ibcon#about to read 6, iclass 3, count 0 2006.218.07:50:31.86#ibcon#read 6, iclass 3, count 0 2006.218.07:50:31.86#ibcon#end of sib2, iclass 3, count 0 2006.218.07:50:31.86#ibcon#*after write, iclass 3, count 0 2006.218.07:50:31.86#ibcon#*before return 0, iclass 3, count 0 2006.218.07:50:31.86#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.218.07:50:31.86#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.218.07:50:31.86#ibcon#about to clear, iclass 3 cls_cnt 0 2006.218.07:50:31.86#ibcon#cleared, iclass 3 cls_cnt 0 2006.218.07:50:31.86$vc4f8/vb=5,4 2006.218.07:50:31.87#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.218.07:50:31.87#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.218.07:50:31.87#ibcon#ireg 11 cls_cnt 2 2006.218.07:50:31.87#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.218.07:50:31.91#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.218.07:50:31.91#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.218.07:50:31.91#ibcon#enter wrdev, iclass 5, count 2 2006.218.07:50:31.91#ibcon#first serial, iclass 5, count 2 2006.218.07:50:31.91#ibcon#enter sib2, iclass 5, count 2 2006.218.07:50:31.91#ibcon#flushed, iclass 5, count 2 2006.218.07:50:31.91#ibcon#about to write, iclass 5, count 2 2006.218.07:50:31.91#ibcon#wrote, iclass 5, count 2 2006.218.07:50:31.91#ibcon#about to read 3, iclass 5, count 2 2006.218.07:50:31.93#ibcon#read 3, iclass 5, count 2 2006.218.07:50:31.93#ibcon#about to read 4, iclass 5, count 2 2006.218.07:50:31.93#ibcon#read 4, iclass 5, count 2 2006.218.07:50:31.93#ibcon#about to read 5, iclass 5, count 2 2006.218.07:50:31.93#ibcon#read 5, iclass 5, count 2 2006.218.07:50:31.93#ibcon#about to read 6, iclass 5, count 2 2006.218.07:50:31.93#ibcon#read 6, iclass 5, count 2 2006.218.07:50:31.93#ibcon#end of sib2, iclass 5, count 2 2006.218.07:50:31.93#ibcon#*mode == 0, iclass 5, count 2 2006.218.07:50:31.93#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.218.07:50:31.93#ibcon#[27=AT05-04\r\n] 2006.218.07:50:31.93#ibcon#*before write, iclass 5, count 2 2006.218.07:50:31.93#ibcon#enter sib2, iclass 5, count 2 2006.218.07:50:31.93#ibcon#flushed, iclass 5, count 2 2006.218.07:50:31.93#ibcon#about to write, iclass 5, count 2 2006.218.07:50:31.93#ibcon#wrote, iclass 5, count 2 2006.218.07:50:31.93#ibcon#about to read 3, iclass 5, count 2 2006.218.07:50:31.96#ibcon#read 3, iclass 5, count 2 2006.218.07:50:31.96#ibcon#about to read 4, iclass 5, count 2 2006.218.07:50:31.96#ibcon#read 4, iclass 5, count 2 2006.218.07:50:31.96#ibcon#about to read 5, iclass 5, count 2 2006.218.07:50:31.96#ibcon#read 5, iclass 5, count 2 2006.218.07:50:31.96#ibcon#about to read 6, iclass 5, count 2 2006.218.07:50:31.96#ibcon#read 6, iclass 5, count 2 2006.218.07:50:31.96#ibcon#end of sib2, iclass 5, count 2 2006.218.07:50:31.96#ibcon#*after write, iclass 5, count 2 2006.218.07:50:31.96#ibcon#*before return 0, iclass 5, count 2 2006.218.07:50:31.96#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.218.07:50:31.96#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.218.07:50:31.96#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.218.07:50:31.96#ibcon#ireg 7 cls_cnt 0 2006.218.07:50:31.96#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.218.07:50:32.08#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.218.07:50:32.08#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.218.07:50:32.08#ibcon#enter wrdev, iclass 5, count 0 2006.218.07:50:32.08#ibcon#first serial, iclass 5, count 0 2006.218.07:50:32.08#ibcon#enter sib2, iclass 5, count 0 2006.218.07:50:32.08#ibcon#flushed, iclass 5, count 0 2006.218.07:50:32.08#ibcon#about to write, iclass 5, count 0 2006.218.07:50:32.08#ibcon#wrote, iclass 5, count 0 2006.218.07:50:32.08#ibcon#about to read 3, iclass 5, count 0 2006.218.07:50:32.10#ibcon#read 3, iclass 5, count 0 2006.218.07:50:32.10#ibcon#about to read 4, iclass 5, count 0 2006.218.07:50:32.10#ibcon#read 4, iclass 5, count 0 2006.218.07:50:32.10#ibcon#about to read 5, iclass 5, count 0 2006.218.07:50:32.10#ibcon#read 5, iclass 5, count 0 2006.218.07:50:32.10#ibcon#about to read 6, iclass 5, count 0 2006.218.07:50:32.10#ibcon#read 6, iclass 5, count 0 2006.218.07:50:32.10#ibcon#end of sib2, iclass 5, count 0 2006.218.07:50:32.10#ibcon#*mode == 0, iclass 5, count 0 2006.218.07:50:32.10#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.218.07:50:32.10#ibcon#[27=USB\r\n] 2006.218.07:50:32.10#ibcon#*before write, iclass 5, count 0 2006.218.07:50:32.10#ibcon#enter sib2, iclass 5, count 0 2006.218.07:50:32.10#ibcon#flushed, iclass 5, count 0 2006.218.07:50:32.10#ibcon#about to write, iclass 5, count 0 2006.218.07:50:32.10#ibcon#wrote, iclass 5, count 0 2006.218.07:50:32.10#ibcon#about to read 3, iclass 5, count 0 2006.218.07:50:32.13#ibcon#read 3, iclass 5, count 0 2006.218.07:50:32.13#ibcon#about to read 4, iclass 5, count 0 2006.218.07:50:32.13#ibcon#read 4, iclass 5, count 0 2006.218.07:50:32.13#ibcon#about to read 5, iclass 5, count 0 2006.218.07:50:32.13#ibcon#read 5, iclass 5, count 0 2006.218.07:50:32.13#ibcon#about to read 6, iclass 5, count 0 2006.218.07:50:32.13#ibcon#read 6, iclass 5, count 0 2006.218.07:50:32.13#ibcon#end of sib2, iclass 5, count 0 2006.218.07:50:32.13#ibcon#*after write, iclass 5, count 0 2006.218.07:50:32.13#ibcon#*before return 0, iclass 5, count 0 2006.218.07:50:32.13#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.218.07:50:32.13#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.218.07:50:32.13#ibcon#about to clear, iclass 5 cls_cnt 0 2006.218.07:50:32.13#ibcon#cleared, iclass 5 cls_cnt 0 2006.218.07:50:32.13$vc4f8/vblo=6,752.99 2006.218.07:50:32.14#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.218.07:50:32.14#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.218.07:50:32.14#ibcon#ireg 17 cls_cnt 0 2006.218.07:50:32.14#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.218.07:50:32.14#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.218.07:50:32.14#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.218.07:50:32.14#ibcon#enter wrdev, iclass 7, count 0 2006.218.07:50:32.14#ibcon#first serial, iclass 7, count 0 2006.218.07:50:32.14#ibcon#enter sib2, iclass 7, count 0 2006.218.07:50:32.14#ibcon#flushed, iclass 7, count 0 2006.218.07:50:32.14#ibcon#about to write, iclass 7, count 0 2006.218.07:50:32.14#ibcon#wrote, iclass 7, count 0 2006.218.07:50:32.14#ibcon#about to read 3, iclass 7, count 0 2006.218.07:50:32.15#ibcon#read 3, iclass 7, count 0 2006.218.07:50:32.15#ibcon#about to read 4, iclass 7, count 0 2006.218.07:50:32.15#ibcon#read 4, iclass 7, count 0 2006.218.07:50:32.15#ibcon#about to read 5, iclass 7, count 0 2006.218.07:50:32.15#ibcon#read 5, iclass 7, count 0 2006.218.07:50:32.15#ibcon#about to read 6, iclass 7, count 0 2006.218.07:50:32.15#ibcon#read 6, iclass 7, count 0 2006.218.07:50:32.15#ibcon#end of sib2, iclass 7, count 0 2006.218.07:50:32.15#ibcon#*mode == 0, iclass 7, count 0 2006.218.07:50:32.15#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.218.07:50:32.15#ibcon#[28=FRQ=06,752.99\r\n] 2006.218.07:50:32.15#ibcon#*before write, iclass 7, count 0 2006.218.07:50:32.15#ibcon#enter sib2, iclass 7, count 0 2006.218.07:50:32.15#ibcon#flushed, iclass 7, count 0 2006.218.07:50:32.15#ibcon#about to write, iclass 7, count 0 2006.218.07:50:32.15#ibcon#wrote, iclass 7, count 0 2006.218.07:50:32.15#ibcon#about to read 3, iclass 7, count 0 2006.218.07:50:32.19#ibcon#read 3, iclass 7, count 0 2006.218.07:50:32.19#ibcon#about to read 4, iclass 7, count 0 2006.218.07:50:32.19#ibcon#read 4, iclass 7, count 0 2006.218.07:50:32.19#ibcon#about to read 5, iclass 7, count 0 2006.218.07:50:32.19#ibcon#read 5, iclass 7, count 0 2006.218.07:50:32.19#ibcon#about to read 6, iclass 7, count 0 2006.218.07:50:32.19#ibcon#read 6, iclass 7, count 0 2006.218.07:50:32.19#ibcon#end of sib2, iclass 7, count 0 2006.218.07:50:32.19#ibcon#*after write, iclass 7, count 0 2006.218.07:50:32.19#ibcon#*before return 0, iclass 7, count 0 2006.218.07:50:32.19#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.218.07:50:32.19#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.218.07:50:32.19#ibcon#about to clear, iclass 7 cls_cnt 0 2006.218.07:50:32.19#ibcon#cleared, iclass 7 cls_cnt 0 2006.218.07:50:32.19$vc4f8/vb=6,4 2006.218.07:50:32.20#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.218.07:50:32.20#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.218.07:50:32.20#ibcon#ireg 11 cls_cnt 2 2006.218.07:50:32.20#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.218.07:50:32.24#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.218.07:50:32.24#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.218.07:50:32.24#ibcon#enter wrdev, iclass 11, count 2 2006.218.07:50:32.24#ibcon#first serial, iclass 11, count 2 2006.218.07:50:32.24#ibcon#enter sib2, iclass 11, count 2 2006.218.07:50:32.24#ibcon#flushed, iclass 11, count 2 2006.218.07:50:32.24#ibcon#about to write, iclass 11, count 2 2006.218.07:50:32.24#ibcon#wrote, iclass 11, count 2 2006.218.07:50:32.24#ibcon#about to read 3, iclass 11, count 2 2006.218.07:50:32.26#ibcon#read 3, iclass 11, count 2 2006.218.07:50:32.26#ibcon#about to read 4, iclass 11, count 2 2006.218.07:50:32.26#ibcon#read 4, iclass 11, count 2 2006.218.07:50:32.26#ibcon#about to read 5, iclass 11, count 2 2006.218.07:50:32.26#ibcon#read 5, iclass 11, count 2 2006.218.07:50:32.26#ibcon#about to read 6, iclass 11, count 2 2006.218.07:50:32.26#ibcon#read 6, iclass 11, count 2 2006.218.07:50:32.26#ibcon#end of sib2, iclass 11, count 2 2006.218.07:50:32.26#ibcon#*mode == 0, iclass 11, count 2 2006.218.07:50:32.26#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.218.07:50:32.26#ibcon#[27=AT06-04\r\n] 2006.218.07:50:32.26#ibcon#*before write, iclass 11, count 2 2006.218.07:50:32.26#ibcon#enter sib2, iclass 11, count 2 2006.218.07:50:32.26#ibcon#flushed, iclass 11, count 2 2006.218.07:50:32.26#ibcon#about to write, iclass 11, count 2 2006.218.07:50:32.26#ibcon#wrote, iclass 11, count 2 2006.218.07:50:32.26#ibcon#about to read 3, iclass 11, count 2 2006.218.07:50:32.29#ibcon#read 3, iclass 11, count 2 2006.218.07:50:32.29#ibcon#about to read 4, iclass 11, count 2 2006.218.07:50:32.29#ibcon#read 4, iclass 11, count 2 2006.218.07:50:32.29#ibcon#about to read 5, iclass 11, count 2 2006.218.07:50:32.29#ibcon#read 5, iclass 11, count 2 2006.218.07:50:32.29#ibcon#about to read 6, iclass 11, count 2 2006.218.07:50:32.29#ibcon#read 6, iclass 11, count 2 2006.218.07:50:32.29#ibcon#end of sib2, iclass 11, count 2 2006.218.07:50:32.29#ibcon#*after write, iclass 11, count 2 2006.218.07:50:32.29#ibcon#*before return 0, iclass 11, count 2 2006.218.07:50:32.29#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.218.07:50:32.29#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.218.07:50:32.29#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.218.07:50:32.29#ibcon#ireg 7 cls_cnt 0 2006.218.07:50:32.29#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.218.07:50:32.41#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.218.07:50:32.41#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.218.07:50:32.41#ibcon#enter wrdev, iclass 11, count 0 2006.218.07:50:32.41#ibcon#first serial, iclass 11, count 0 2006.218.07:50:32.41#ibcon#enter sib2, iclass 11, count 0 2006.218.07:50:32.41#ibcon#flushed, iclass 11, count 0 2006.218.07:50:32.41#ibcon#about to write, iclass 11, count 0 2006.218.07:50:32.41#ibcon#wrote, iclass 11, count 0 2006.218.07:50:32.41#ibcon#about to read 3, iclass 11, count 0 2006.218.07:50:32.43#ibcon#read 3, iclass 11, count 0 2006.218.07:50:32.43#ibcon#about to read 4, iclass 11, count 0 2006.218.07:50:32.43#ibcon#read 4, iclass 11, count 0 2006.218.07:50:32.43#ibcon#about to read 5, iclass 11, count 0 2006.218.07:50:32.43#ibcon#read 5, iclass 11, count 0 2006.218.07:50:32.43#ibcon#about to read 6, iclass 11, count 0 2006.218.07:50:32.43#ibcon#read 6, iclass 11, count 0 2006.218.07:50:32.43#ibcon#end of sib2, iclass 11, count 0 2006.218.07:50:32.43#ibcon#*mode == 0, iclass 11, count 0 2006.218.07:50:32.43#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.218.07:50:32.43#ibcon#[27=USB\r\n] 2006.218.07:50:32.43#ibcon#*before write, iclass 11, count 0 2006.218.07:50:32.43#ibcon#enter sib2, iclass 11, count 0 2006.218.07:50:32.43#ibcon#flushed, iclass 11, count 0 2006.218.07:50:32.43#ibcon#about to write, iclass 11, count 0 2006.218.07:50:32.43#ibcon#wrote, iclass 11, count 0 2006.218.07:50:32.43#ibcon#about to read 3, iclass 11, count 0 2006.218.07:50:32.46#ibcon#read 3, iclass 11, count 0 2006.218.07:50:32.46#ibcon#about to read 4, iclass 11, count 0 2006.218.07:50:32.46#ibcon#read 4, iclass 11, count 0 2006.218.07:50:32.46#ibcon#about to read 5, iclass 11, count 0 2006.218.07:50:32.46#ibcon#read 5, iclass 11, count 0 2006.218.07:50:32.46#ibcon#about to read 6, iclass 11, count 0 2006.218.07:50:32.46#ibcon#read 6, iclass 11, count 0 2006.218.07:50:32.46#ibcon#end of sib2, iclass 11, count 0 2006.218.07:50:32.46#ibcon#*after write, iclass 11, count 0 2006.218.07:50:32.46#ibcon#*before return 0, iclass 11, count 0 2006.218.07:50:32.46#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.218.07:50:32.46#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.218.07:50:32.46#ibcon#about to clear, iclass 11 cls_cnt 0 2006.218.07:50:32.46#ibcon#cleared, iclass 11 cls_cnt 0 2006.218.07:50:32.46$vc4f8/vabw=wide 2006.218.07:50:32.47#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.218.07:50:32.47#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.218.07:50:32.47#ibcon#ireg 8 cls_cnt 0 2006.218.07:50:32.47#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.218.07:50:32.47#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.218.07:50:32.47#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.218.07:50:32.47#ibcon#enter wrdev, iclass 13, count 0 2006.218.07:50:32.47#ibcon#first serial, iclass 13, count 0 2006.218.07:50:32.47#ibcon#enter sib2, iclass 13, count 0 2006.218.07:50:32.47#ibcon#flushed, iclass 13, count 0 2006.218.07:50:32.47#ibcon#about to write, iclass 13, count 0 2006.218.07:50:32.47#ibcon#wrote, iclass 13, count 0 2006.218.07:50:32.47#ibcon#about to read 3, iclass 13, count 0 2006.218.07:50:32.48#ibcon#read 3, iclass 13, count 0 2006.218.07:50:32.48#ibcon#about to read 4, iclass 13, count 0 2006.218.07:50:32.48#ibcon#read 4, iclass 13, count 0 2006.218.07:50:32.48#ibcon#about to read 5, iclass 13, count 0 2006.218.07:50:32.48#ibcon#read 5, iclass 13, count 0 2006.218.07:50:32.48#ibcon#about to read 6, iclass 13, count 0 2006.218.07:50:32.48#ibcon#read 6, iclass 13, count 0 2006.218.07:50:32.48#ibcon#end of sib2, iclass 13, count 0 2006.218.07:50:32.48#ibcon#*mode == 0, iclass 13, count 0 2006.218.07:50:32.48#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.218.07:50:32.48#ibcon#[25=BW32\r\n] 2006.218.07:50:32.48#ibcon#*before write, iclass 13, count 0 2006.218.07:50:32.48#ibcon#enter sib2, iclass 13, count 0 2006.218.07:50:32.48#ibcon#flushed, iclass 13, count 0 2006.218.07:50:32.48#ibcon#about to write, iclass 13, count 0 2006.218.07:50:32.48#ibcon#wrote, iclass 13, count 0 2006.218.07:50:32.48#ibcon#about to read 3, iclass 13, count 0 2006.218.07:50:32.51#ibcon#read 3, iclass 13, count 0 2006.218.07:50:32.51#ibcon#about to read 4, iclass 13, count 0 2006.218.07:50:32.51#ibcon#read 4, iclass 13, count 0 2006.218.07:50:32.51#ibcon#about to read 5, iclass 13, count 0 2006.218.07:50:32.51#ibcon#read 5, iclass 13, count 0 2006.218.07:50:32.51#ibcon#about to read 6, iclass 13, count 0 2006.218.07:50:32.51#ibcon#read 6, iclass 13, count 0 2006.218.07:50:32.51#ibcon#end of sib2, iclass 13, count 0 2006.218.07:50:32.51#ibcon#*after write, iclass 13, count 0 2006.218.07:50:32.51#ibcon#*before return 0, iclass 13, count 0 2006.218.07:50:32.51#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.218.07:50:32.51#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.218.07:50:32.51#ibcon#about to clear, iclass 13 cls_cnt 0 2006.218.07:50:32.51#ibcon#cleared, iclass 13 cls_cnt 0 2006.218.07:50:32.51$vc4f8/vbbw=wide 2006.218.07:50:32.52#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.218.07:50:32.52#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.218.07:50:32.52#ibcon#ireg 8 cls_cnt 0 2006.218.07:50:32.52#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.218.07:50:32.57#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.218.07:50:32.57#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.218.07:50:32.57#ibcon#enter wrdev, iclass 15, count 0 2006.218.07:50:32.57#ibcon#first serial, iclass 15, count 0 2006.218.07:50:32.57#ibcon#enter sib2, iclass 15, count 0 2006.218.07:50:32.57#ibcon#flushed, iclass 15, count 0 2006.218.07:50:32.57#ibcon#about to write, iclass 15, count 0 2006.218.07:50:32.57#ibcon#wrote, iclass 15, count 0 2006.218.07:50:32.57#ibcon#about to read 3, iclass 15, count 0 2006.218.07:50:32.59#ibcon#read 3, iclass 15, count 0 2006.218.07:50:32.59#ibcon#about to read 4, iclass 15, count 0 2006.218.07:50:32.59#ibcon#read 4, iclass 15, count 0 2006.218.07:50:32.59#ibcon#about to read 5, iclass 15, count 0 2006.218.07:50:32.59#ibcon#read 5, iclass 15, count 0 2006.218.07:50:32.59#ibcon#about to read 6, iclass 15, count 0 2006.218.07:50:32.59#ibcon#read 6, iclass 15, count 0 2006.218.07:50:32.59#ibcon#end of sib2, iclass 15, count 0 2006.218.07:50:32.59#ibcon#*mode == 0, iclass 15, count 0 2006.218.07:50:32.59#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.218.07:50:32.59#ibcon#[27=BW32\r\n] 2006.218.07:50:32.59#ibcon#*before write, iclass 15, count 0 2006.218.07:50:32.59#ibcon#enter sib2, iclass 15, count 0 2006.218.07:50:32.59#ibcon#flushed, iclass 15, count 0 2006.218.07:50:32.59#ibcon#about to write, iclass 15, count 0 2006.218.07:50:32.59#ibcon#wrote, iclass 15, count 0 2006.218.07:50:32.59#ibcon#about to read 3, iclass 15, count 0 2006.218.07:50:32.62#ibcon#read 3, iclass 15, count 0 2006.218.07:50:32.62#ibcon#about to read 4, iclass 15, count 0 2006.218.07:50:32.62#ibcon#read 4, iclass 15, count 0 2006.218.07:50:32.62#ibcon#about to read 5, iclass 15, count 0 2006.218.07:50:32.62#ibcon#read 5, iclass 15, count 0 2006.218.07:50:32.62#ibcon#about to read 6, iclass 15, count 0 2006.218.07:50:32.62#ibcon#read 6, iclass 15, count 0 2006.218.07:50:32.62#ibcon#end of sib2, iclass 15, count 0 2006.218.07:50:32.62#ibcon#*after write, iclass 15, count 0 2006.218.07:50:32.62#ibcon#*before return 0, iclass 15, count 0 2006.218.07:50:32.62#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.218.07:50:32.62#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.218.07:50:32.62#ibcon#about to clear, iclass 15 cls_cnt 0 2006.218.07:50:32.62#ibcon#cleared, iclass 15 cls_cnt 0 2006.218.07:50:32.63$4f8m12a/ifd4f 2006.218.07:50:32.63$ifd4f/lo= 2006.218.07:50:32.63$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.218.07:50:32.63$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.218.07:50:32.63$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.218.07:50:32.63$ifd4f/patch= 2006.218.07:50:32.63$ifd4f/patch=lo1,a1,a2,a3,a4 2006.218.07:50:32.63$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.218.07:50:32.63$ifd4f/patch=lo3,a5,a6,a7,a8 2006.218.07:50:32.63$4f8m12a/"form=m,16.000,1:2 2006.218.07:50:32.63$4f8m12a/"tpicd 2006.218.07:50:32.63$4f8m12a/echo=off 2006.218.07:50:32.63$4f8m12a/xlog=off 2006.218.07:50:32.63:!2006.218.07:51:00 2006.218.07:50:39.14#trakl#Source acquired 2006.218.07:50:39.15#flagr#flagr/antenna,acquired 2006.218.07:51:00.01:preob 2006.218.07:51:01.14/onsource/TRACKING 2006.218.07:51:01.15:!2006.218.07:51:10 2006.218.07:51:10.01:data_valid=on 2006.218.07:51:10.02:midob 2006.218.07:51:11.14/onsource/TRACKING 2006.218.07:51:11.15/wx/31.18,1007.4,73 2006.218.07:51:11.30/cable/+6.3848E-03 2006.218.07:51:12.39/va/01,05,usb,yes,33,35 2006.218.07:51:12.39/va/02,04,usb,yes,31,32 2006.218.07:51:12.39/va/03,04,usb,yes,29,29 2006.218.07:51:12.39/va/04,04,usb,yes,32,35 2006.218.07:51:12.39/va/05,07,usb,yes,35,37 2006.218.07:51:12.39/va/06,06,usb,yes,34,34 2006.218.07:51:12.39/va/07,06,usb,yes,34,34 2006.218.07:51:12.39/va/08,07,usb,yes,33,32 2006.218.07:51:12.62/valo/01,532.99,yes,locked 2006.218.07:51:12.62/valo/02,572.99,yes,locked 2006.218.07:51:12.62/valo/03,672.99,yes,locked 2006.218.07:51:12.62/valo/04,832.99,yes,locked 2006.218.07:51:12.62/valo/05,652.99,yes,locked 2006.218.07:51:12.62/valo/06,772.99,yes,locked 2006.218.07:51:12.62/valo/07,832.99,yes,locked 2006.218.07:51:12.62/valo/08,852.99,yes,locked 2006.218.07:51:13.71/vb/01,04,usb,yes,31,30 2006.218.07:51:13.71/vb/02,04,usb,yes,33,34 2006.218.07:51:13.71/vb/03,04,usb,yes,29,33 2006.218.07:51:13.71/vb/04,04,usb,yes,30,30 2006.218.07:51:13.71/vb/05,04,usb,yes,28,32 2006.218.07:51:13.71/vb/06,04,usb,yes,29,32 2006.218.07:51:13.71/vb/07,04,usb,yes,32,31 2006.218.07:51:13.71/vb/08,04,usb,yes,29,32 2006.218.07:51:13.94/vblo/01,632.99,yes,locked 2006.218.07:51:13.94/vblo/02,640.99,yes,locked 2006.218.07:51:13.94/vblo/03,656.99,yes,locked 2006.218.07:51:13.94/vblo/04,712.99,yes,locked 2006.218.07:51:13.94/vblo/05,744.99,yes,locked 2006.218.07:51:13.94/vblo/06,752.99,yes,locked 2006.218.07:51:13.94/vblo/07,734.99,yes,locked 2006.218.07:51:13.94/vblo/08,744.99,yes,locked 2006.218.07:51:14.09/vabw/8 2006.218.07:51:14.24/vbbw/8 2006.218.07:51:14.36/xfe/off,on,15.2 2006.218.07:51:14.74/ifatt/23,28,28,28 2006.218.07:51:15.07/fmout-gps/S +4.69E-07 2006.218.07:51:15.12:!2006.218.07:52:10 2006.218.07:52:10.01:data_valid=off 2006.218.07:52:10.02:postob 2006.218.07:52:10.13/cable/+6.3839E-03 2006.218.07:52:10.14/wx/31.16,1007.4,73 2006.218.07:52:10.19/fmout-gps/S +4.69E-07 2006.218.07:52:10.20:scan_name=218-0753,k06218,60 2006.218.07:52:10.20:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.218.07:52:11.14#flagr#flagr/antenna,new-source 2006.218.07:52:11.15:checkk5 2006.218.07:52:11.53/chk_autoobs//k5ts1/ autoobs is running! 2006.218.07:52:11.91/chk_autoobs//k5ts2/ autoobs is running! 2006.218.07:52:12.28/chk_autoobs//k5ts3/ autoobs is running! 2006.218.07:52:12.66/chk_autoobs//k5ts4/ autoobs is running! 2006.218.07:52:13.02/chk_obsdata//k5ts1/T2180751??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:52:13.39/chk_obsdata//k5ts2/T2180751??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:52:13.76/chk_obsdata//k5ts3/T2180751??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:52:14.13/chk_obsdata//k5ts4/T2180751??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:52:14.82/k5log//k5ts1_log_newline 2006.218.07:52:15.52/k5log//k5ts2_log_newline 2006.218.07:52:16.22/k5log//k5ts3_log_newline 2006.218.07:52:16.90/k5log//k5ts4_log_newline 2006.218.07:52:16.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.218.07:52:16.92:4f8m12a=1 2006.218.07:52:16.92$4f8m12a/echo=on 2006.218.07:52:16.92$4f8m12a/pcalon 2006.218.07:52:16.93$pcalon/"no phase cal control is implemented here 2006.218.07:52:16.93$4f8m12a/"tpicd=stop 2006.218.07:52:16.93$4f8m12a/vc4f8 2006.218.07:52:16.93$vc4f8/valo=1,532.99 2006.218.07:52:16.93#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.218.07:52:16.93#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.218.07:52:16.93#ibcon#ireg 17 cls_cnt 0 2006.218.07:52:16.93#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.218.07:52:16.93#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.218.07:52:16.93#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.218.07:52:16.93#ibcon#enter wrdev, iclass 22, count 0 2006.218.07:52:16.93#ibcon#first serial, iclass 22, count 0 2006.218.07:52:16.93#ibcon#enter sib2, iclass 22, count 0 2006.218.07:52:16.93#ibcon#flushed, iclass 22, count 0 2006.218.07:52:16.93#ibcon#about to write, iclass 22, count 0 2006.218.07:52:16.93#ibcon#wrote, iclass 22, count 0 2006.218.07:52:16.93#ibcon#about to read 3, iclass 22, count 0 2006.218.07:52:16.97#ibcon#read 3, iclass 22, count 0 2006.218.07:52:16.97#ibcon#about to read 4, iclass 22, count 0 2006.218.07:52:16.97#ibcon#read 4, iclass 22, count 0 2006.218.07:52:16.97#ibcon#about to read 5, iclass 22, count 0 2006.218.07:52:16.97#ibcon#read 5, iclass 22, count 0 2006.218.07:52:16.97#ibcon#about to read 6, iclass 22, count 0 2006.218.07:52:16.97#ibcon#read 6, iclass 22, count 0 2006.218.07:52:16.97#ibcon#end of sib2, iclass 22, count 0 2006.218.07:52:16.97#ibcon#*mode == 0, iclass 22, count 0 2006.218.07:52:16.97#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.218.07:52:16.97#ibcon#[26=FRQ=01,532.99\r\n] 2006.218.07:52:16.97#ibcon#*before write, iclass 22, count 0 2006.218.07:52:16.97#ibcon#enter sib2, iclass 22, count 0 2006.218.07:52:16.97#ibcon#flushed, iclass 22, count 0 2006.218.07:52:16.97#ibcon#about to write, iclass 22, count 0 2006.218.07:52:16.97#ibcon#wrote, iclass 22, count 0 2006.218.07:52:16.97#ibcon#about to read 3, iclass 22, count 0 2006.218.07:52:17.01#ibcon#read 3, iclass 22, count 0 2006.218.07:52:17.01#ibcon#about to read 4, iclass 22, count 0 2006.218.07:52:17.01#ibcon#read 4, iclass 22, count 0 2006.218.07:52:17.01#ibcon#about to read 5, iclass 22, count 0 2006.218.07:52:17.01#ibcon#read 5, iclass 22, count 0 2006.218.07:52:17.01#ibcon#about to read 6, iclass 22, count 0 2006.218.07:52:17.01#ibcon#read 6, iclass 22, count 0 2006.218.07:52:17.01#ibcon#end of sib2, iclass 22, count 0 2006.218.07:52:17.01#ibcon#*after write, iclass 22, count 0 2006.218.07:52:17.01#ibcon#*before return 0, iclass 22, count 0 2006.218.07:52:17.01#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.218.07:52:17.01#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.218.07:52:17.01#ibcon#about to clear, iclass 22 cls_cnt 0 2006.218.07:52:17.01#ibcon#cleared, iclass 22 cls_cnt 0 2006.218.07:52:17.01$vc4f8/va=1,5 2006.218.07:52:17.01#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.218.07:52:17.01#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.218.07:52:17.01#ibcon#ireg 11 cls_cnt 2 2006.218.07:52:17.01#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.218.07:52:17.01#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.218.07:52:17.01#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.218.07:52:17.01#ibcon#enter wrdev, iclass 24, count 2 2006.218.07:52:17.01#ibcon#first serial, iclass 24, count 2 2006.218.07:52:17.01#ibcon#enter sib2, iclass 24, count 2 2006.218.07:52:17.01#ibcon#flushed, iclass 24, count 2 2006.218.07:52:17.01#ibcon#about to write, iclass 24, count 2 2006.218.07:52:17.01#ibcon#wrote, iclass 24, count 2 2006.218.07:52:17.01#ibcon#about to read 3, iclass 24, count 2 2006.218.07:52:17.03#ibcon#read 3, iclass 24, count 2 2006.218.07:52:17.03#ibcon#about to read 4, iclass 24, count 2 2006.218.07:52:17.03#ibcon#read 4, iclass 24, count 2 2006.218.07:52:17.03#ibcon#about to read 5, iclass 24, count 2 2006.218.07:52:17.03#ibcon#read 5, iclass 24, count 2 2006.218.07:52:17.03#ibcon#about to read 6, iclass 24, count 2 2006.218.07:52:17.03#ibcon#read 6, iclass 24, count 2 2006.218.07:52:17.03#ibcon#end of sib2, iclass 24, count 2 2006.218.07:52:17.03#ibcon#*mode == 0, iclass 24, count 2 2006.218.07:52:17.03#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.218.07:52:17.03#ibcon#[25=AT01-05\r\n] 2006.218.07:52:17.03#ibcon#*before write, iclass 24, count 2 2006.218.07:52:17.03#ibcon#enter sib2, iclass 24, count 2 2006.218.07:52:17.03#ibcon#flushed, iclass 24, count 2 2006.218.07:52:17.03#ibcon#about to write, iclass 24, count 2 2006.218.07:52:17.03#ibcon#wrote, iclass 24, count 2 2006.218.07:52:17.03#ibcon#about to read 3, iclass 24, count 2 2006.218.07:52:17.07#ibcon#read 3, iclass 24, count 2 2006.218.07:52:17.07#ibcon#about to read 4, iclass 24, count 2 2006.218.07:52:17.07#ibcon#read 4, iclass 24, count 2 2006.218.07:52:17.07#ibcon#about to read 5, iclass 24, count 2 2006.218.07:52:17.07#ibcon#read 5, iclass 24, count 2 2006.218.07:52:17.07#ibcon#about to read 6, iclass 24, count 2 2006.218.07:52:17.07#ibcon#read 6, iclass 24, count 2 2006.218.07:52:17.07#ibcon#end of sib2, iclass 24, count 2 2006.218.07:52:17.07#ibcon#*after write, iclass 24, count 2 2006.218.07:52:17.07#ibcon#*before return 0, iclass 24, count 2 2006.218.07:52:17.07#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.218.07:52:17.07#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.218.07:52:17.07#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.218.07:52:17.07#ibcon#ireg 7 cls_cnt 0 2006.218.07:52:17.07#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.218.07:52:17.18#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.218.07:52:17.18#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.218.07:52:17.18#ibcon#enter wrdev, iclass 24, count 0 2006.218.07:52:17.18#ibcon#first serial, iclass 24, count 0 2006.218.07:52:17.18#ibcon#enter sib2, iclass 24, count 0 2006.218.07:52:17.18#ibcon#flushed, iclass 24, count 0 2006.218.07:52:17.18#ibcon#about to write, iclass 24, count 0 2006.218.07:52:17.18#ibcon#wrote, iclass 24, count 0 2006.218.07:52:17.18#ibcon#about to read 3, iclass 24, count 0 2006.218.07:52:17.20#ibcon#read 3, iclass 24, count 0 2006.218.07:52:17.20#ibcon#about to read 4, iclass 24, count 0 2006.218.07:52:17.20#ibcon#read 4, iclass 24, count 0 2006.218.07:52:17.20#ibcon#about to read 5, iclass 24, count 0 2006.218.07:52:17.20#ibcon#read 5, iclass 24, count 0 2006.218.07:52:17.20#ibcon#about to read 6, iclass 24, count 0 2006.218.07:52:17.20#ibcon#read 6, iclass 24, count 0 2006.218.07:52:17.20#ibcon#end of sib2, iclass 24, count 0 2006.218.07:52:17.20#ibcon#*mode == 0, iclass 24, count 0 2006.218.07:52:17.20#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.218.07:52:17.20#ibcon#[25=USB\r\n] 2006.218.07:52:17.20#ibcon#*before write, iclass 24, count 0 2006.218.07:52:17.20#ibcon#enter sib2, iclass 24, count 0 2006.218.07:52:17.20#ibcon#flushed, iclass 24, count 0 2006.218.07:52:17.20#ibcon#about to write, iclass 24, count 0 2006.218.07:52:17.20#ibcon#wrote, iclass 24, count 0 2006.218.07:52:17.20#ibcon#about to read 3, iclass 24, count 0 2006.218.07:52:17.23#ibcon#read 3, iclass 24, count 0 2006.218.07:52:17.23#ibcon#about to read 4, iclass 24, count 0 2006.218.07:52:17.23#ibcon#read 4, iclass 24, count 0 2006.218.07:52:17.23#ibcon#about to read 5, iclass 24, count 0 2006.218.07:52:17.23#ibcon#read 5, iclass 24, count 0 2006.218.07:52:17.23#ibcon#about to read 6, iclass 24, count 0 2006.218.07:52:17.23#ibcon#read 6, iclass 24, count 0 2006.218.07:52:17.23#ibcon#end of sib2, iclass 24, count 0 2006.218.07:52:17.23#ibcon#*after write, iclass 24, count 0 2006.218.07:52:17.23#ibcon#*before return 0, iclass 24, count 0 2006.218.07:52:17.23#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.218.07:52:17.23#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.218.07:52:17.23#ibcon#about to clear, iclass 24 cls_cnt 0 2006.218.07:52:17.23#ibcon#cleared, iclass 24 cls_cnt 0 2006.218.07:52:17.24$vc4f8/valo=2,572.99 2006.218.07:52:17.24#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.218.07:52:17.24#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.218.07:52:17.24#ibcon#ireg 17 cls_cnt 0 2006.218.07:52:17.24#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.218.07:52:17.24#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.218.07:52:17.24#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.218.07:52:17.24#ibcon#enter wrdev, iclass 26, count 0 2006.218.07:52:17.24#ibcon#first serial, iclass 26, count 0 2006.218.07:52:17.24#ibcon#enter sib2, iclass 26, count 0 2006.218.07:52:17.24#ibcon#flushed, iclass 26, count 0 2006.218.07:52:17.24#ibcon#about to write, iclass 26, count 0 2006.218.07:52:17.24#ibcon#wrote, iclass 26, count 0 2006.218.07:52:17.24#ibcon#about to read 3, iclass 26, count 0 2006.218.07:52:17.25#ibcon#read 3, iclass 26, count 0 2006.218.07:52:17.25#ibcon#about to read 4, iclass 26, count 0 2006.218.07:52:17.25#ibcon#read 4, iclass 26, count 0 2006.218.07:52:17.25#ibcon#about to read 5, iclass 26, count 0 2006.218.07:52:17.25#ibcon#read 5, iclass 26, count 0 2006.218.07:52:17.25#ibcon#about to read 6, iclass 26, count 0 2006.218.07:52:17.25#ibcon#read 6, iclass 26, count 0 2006.218.07:52:17.25#ibcon#end of sib2, iclass 26, count 0 2006.218.07:52:17.25#ibcon#*mode == 0, iclass 26, count 0 2006.218.07:52:17.25#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.218.07:52:17.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.218.07:52:17.25#ibcon#*before write, iclass 26, count 0 2006.218.07:52:17.25#ibcon#enter sib2, iclass 26, count 0 2006.218.07:52:17.25#ibcon#flushed, iclass 26, count 0 2006.218.07:52:17.25#ibcon#about to write, iclass 26, count 0 2006.218.07:52:17.25#ibcon#wrote, iclass 26, count 0 2006.218.07:52:17.25#ibcon#about to read 3, iclass 26, count 0 2006.218.07:52:17.29#ibcon#read 3, iclass 26, count 0 2006.218.07:52:17.29#ibcon#about to read 4, iclass 26, count 0 2006.218.07:52:17.29#ibcon#read 4, iclass 26, count 0 2006.218.07:52:17.29#ibcon#about to read 5, iclass 26, count 0 2006.218.07:52:17.29#ibcon#read 5, iclass 26, count 0 2006.218.07:52:17.29#ibcon#about to read 6, iclass 26, count 0 2006.218.07:52:17.29#ibcon#read 6, iclass 26, count 0 2006.218.07:52:17.29#ibcon#end of sib2, iclass 26, count 0 2006.218.07:52:17.29#ibcon#*after write, iclass 26, count 0 2006.218.07:52:17.29#ibcon#*before return 0, iclass 26, count 0 2006.218.07:52:17.29#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.218.07:52:17.29#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.218.07:52:17.29#ibcon#about to clear, iclass 26 cls_cnt 0 2006.218.07:52:17.29#ibcon#cleared, iclass 26 cls_cnt 0 2006.218.07:52:17.29$vc4f8/va=2,4 2006.218.07:52:17.29#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.218.07:52:17.29#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.218.07:52:17.29#ibcon#ireg 11 cls_cnt 2 2006.218.07:52:17.29#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.218.07:52:17.35#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.218.07:52:17.35#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.218.07:52:17.35#ibcon#enter wrdev, iclass 28, count 2 2006.218.07:52:17.35#ibcon#first serial, iclass 28, count 2 2006.218.07:52:17.35#ibcon#enter sib2, iclass 28, count 2 2006.218.07:52:17.35#ibcon#flushed, iclass 28, count 2 2006.218.07:52:17.35#ibcon#about to write, iclass 28, count 2 2006.218.07:52:17.35#ibcon#wrote, iclass 28, count 2 2006.218.07:52:17.35#ibcon#about to read 3, iclass 28, count 2 2006.218.07:52:17.37#ibcon#read 3, iclass 28, count 2 2006.218.07:52:17.37#ibcon#about to read 4, iclass 28, count 2 2006.218.07:52:17.37#ibcon#read 4, iclass 28, count 2 2006.218.07:52:17.37#ibcon#about to read 5, iclass 28, count 2 2006.218.07:52:17.37#ibcon#read 5, iclass 28, count 2 2006.218.07:52:17.37#ibcon#about to read 6, iclass 28, count 2 2006.218.07:52:17.37#ibcon#read 6, iclass 28, count 2 2006.218.07:52:17.37#ibcon#end of sib2, iclass 28, count 2 2006.218.07:52:17.37#ibcon#*mode == 0, iclass 28, count 2 2006.218.07:52:17.37#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.218.07:52:17.37#ibcon#[25=AT02-04\r\n] 2006.218.07:52:17.37#ibcon#*before write, iclass 28, count 2 2006.218.07:52:17.37#ibcon#enter sib2, iclass 28, count 2 2006.218.07:52:17.37#ibcon#flushed, iclass 28, count 2 2006.218.07:52:17.37#ibcon#about to write, iclass 28, count 2 2006.218.07:52:17.37#ibcon#wrote, iclass 28, count 2 2006.218.07:52:17.37#ibcon#about to read 3, iclass 28, count 2 2006.218.07:52:17.40#ibcon#read 3, iclass 28, count 2 2006.218.07:52:17.40#ibcon#about to read 4, iclass 28, count 2 2006.218.07:52:17.40#ibcon#read 4, iclass 28, count 2 2006.218.07:52:17.40#ibcon#about to read 5, iclass 28, count 2 2006.218.07:52:17.40#ibcon#read 5, iclass 28, count 2 2006.218.07:52:17.40#ibcon#about to read 6, iclass 28, count 2 2006.218.07:52:17.40#ibcon#read 6, iclass 28, count 2 2006.218.07:52:17.40#ibcon#end of sib2, iclass 28, count 2 2006.218.07:52:17.40#ibcon#*after write, iclass 28, count 2 2006.218.07:52:17.40#ibcon#*before return 0, iclass 28, count 2 2006.218.07:52:17.40#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.218.07:52:17.40#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.218.07:52:17.40#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.218.07:52:17.40#ibcon#ireg 7 cls_cnt 0 2006.218.07:52:17.40#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.218.07:52:17.52#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.218.07:52:17.52#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.218.07:52:17.52#ibcon#enter wrdev, iclass 28, count 0 2006.218.07:52:17.52#ibcon#first serial, iclass 28, count 0 2006.218.07:52:17.52#ibcon#enter sib2, iclass 28, count 0 2006.218.07:52:17.52#ibcon#flushed, iclass 28, count 0 2006.218.07:52:17.52#ibcon#about to write, iclass 28, count 0 2006.218.07:52:17.52#ibcon#wrote, iclass 28, count 0 2006.218.07:52:17.52#ibcon#about to read 3, iclass 28, count 0 2006.218.07:52:17.55#ibcon#read 3, iclass 28, count 0 2006.218.07:52:17.55#ibcon#about to read 4, iclass 28, count 0 2006.218.07:52:17.55#ibcon#read 4, iclass 28, count 0 2006.218.07:52:17.55#ibcon#about to read 5, iclass 28, count 0 2006.218.07:52:17.55#ibcon#read 5, iclass 28, count 0 2006.218.07:52:17.55#ibcon#about to read 6, iclass 28, count 0 2006.218.07:52:17.55#ibcon#read 6, iclass 28, count 0 2006.218.07:52:17.55#ibcon#end of sib2, iclass 28, count 0 2006.218.07:52:17.55#ibcon#*mode == 0, iclass 28, count 0 2006.218.07:52:17.55#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.218.07:52:17.55#ibcon#[25=USB\r\n] 2006.218.07:52:17.55#ibcon#*before write, iclass 28, count 0 2006.218.07:52:17.55#ibcon#enter sib2, iclass 28, count 0 2006.218.07:52:17.55#ibcon#flushed, iclass 28, count 0 2006.218.07:52:17.55#ibcon#about to write, iclass 28, count 0 2006.218.07:52:17.55#ibcon#wrote, iclass 28, count 0 2006.218.07:52:17.55#ibcon#about to read 3, iclass 28, count 0 2006.218.07:52:17.57#ibcon#read 3, iclass 28, count 0 2006.218.07:52:17.57#ibcon#about to read 4, iclass 28, count 0 2006.218.07:52:17.57#ibcon#read 4, iclass 28, count 0 2006.218.07:52:17.57#ibcon#about to read 5, iclass 28, count 0 2006.218.07:52:17.57#ibcon#read 5, iclass 28, count 0 2006.218.07:52:17.57#ibcon#about to read 6, iclass 28, count 0 2006.218.07:52:17.57#ibcon#read 6, iclass 28, count 0 2006.218.07:52:17.57#ibcon#end of sib2, iclass 28, count 0 2006.218.07:52:17.57#ibcon#*after write, iclass 28, count 0 2006.218.07:52:17.57#ibcon#*before return 0, iclass 28, count 0 2006.218.07:52:17.57#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.218.07:52:17.57#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.218.07:52:17.57#ibcon#about to clear, iclass 28 cls_cnt 0 2006.218.07:52:17.57#ibcon#cleared, iclass 28 cls_cnt 0 2006.218.07:52:17.57$vc4f8/valo=3,672.99 2006.218.07:52:17.57#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.218.07:52:17.57#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.218.07:52:17.57#ibcon#ireg 17 cls_cnt 0 2006.218.07:52:17.57#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.218.07:52:17.57#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.218.07:52:17.57#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.218.07:52:17.57#ibcon#enter wrdev, iclass 30, count 0 2006.218.07:52:17.57#ibcon#first serial, iclass 30, count 0 2006.218.07:52:17.57#ibcon#enter sib2, iclass 30, count 0 2006.218.07:52:17.57#ibcon#flushed, iclass 30, count 0 2006.218.07:52:17.57#ibcon#about to write, iclass 30, count 0 2006.218.07:52:17.57#ibcon#wrote, iclass 30, count 0 2006.218.07:52:17.57#ibcon#about to read 3, iclass 30, count 0 2006.218.07:52:17.59#ibcon#read 3, iclass 30, count 0 2006.218.07:52:17.60#ibcon#about to read 4, iclass 30, count 0 2006.218.07:52:17.60#ibcon#read 4, iclass 30, count 0 2006.218.07:52:17.60#ibcon#about to read 5, iclass 30, count 0 2006.218.07:52:17.60#ibcon#read 5, iclass 30, count 0 2006.218.07:52:17.60#ibcon#about to read 6, iclass 30, count 0 2006.218.07:52:17.60#ibcon#read 6, iclass 30, count 0 2006.218.07:52:17.60#ibcon#end of sib2, iclass 30, count 0 2006.218.07:52:17.60#ibcon#*mode == 0, iclass 30, count 0 2006.218.07:52:17.60#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.218.07:52:17.60#ibcon#[26=FRQ=03,672.99\r\n] 2006.218.07:52:17.60#ibcon#*before write, iclass 30, count 0 2006.218.07:52:17.60#ibcon#enter sib2, iclass 30, count 0 2006.218.07:52:17.60#ibcon#flushed, iclass 30, count 0 2006.218.07:52:17.60#ibcon#about to write, iclass 30, count 0 2006.218.07:52:17.60#ibcon#wrote, iclass 30, count 0 2006.218.07:52:17.60#ibcon#about to read 3, iclass 30, count 0 2006.218.07:52:17.64#ibcon#read 3, iclass 30, count 0 2006.218.07:52:17.64#ibcon#about to read 4, iclass 30, count 0 2006.218.07:52:17.64#ibcon#read 4, iclass 30, count 0 2006.218.07:52:17.64#ibcon#about to read 5, iclass 30, count 0 2006.218.07:52:17.64#ibcon#read 5, iclass 30, count 0 2006.218.07:52:17.64#ibcon#about to read 6, iclass 30, count 0 2006.218.07:52:17.64#ibcon#read 6, iclass 30, count 0 2006.218.07:52:17.64#ibcon#end of sib2, iclass 30, count 0 2006.218.07:52:17.64#ibcon#*after write, iclass 30, count 0 2006.218.07:52:17.64#ibcon#*before return 0, iclass 30, count 0 2006.218.07:52:17.64#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.218.07:52:17.64#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.218.07:52:17.64#ibcon#about to clear, iclass 30 cls_cnt 0 2006.218.07:52:17.64#ibcon#cleared, iclass 30 cls_cnt 0 2006.218.07:52:17.64$vc4f8/va=3,4 2006.218.07:52:17.64#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.218.07:52:17.64#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.218.07:52:17.64#ibcon#ireg 11 cls_cnt 2 2006.218.07:52:17.64#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.218.07:52:17.68#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.218.07:52:17.68#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.218.07:52:17.68#ibcon#enter wrdev, iclass 32, count 2 2006.218.07:52:17.68#ibcon#first serial, iclass 32, count 2 2006.218.07:52:17.68#ibcon#enter sib2, iclass 32, count 2 2006.218.07:52:17.68#ibcon#flushed, iclass 32, count 2 2006.218.07:52:17.68#ibcon#about to write, iclass 32, count 2 2006.218.07:52:17.68#ibcon#wrote, iclass 32, count 2 2006.218.07:52:17.68#ibcon#about to read 3, iclass 32, count 2 2006.218.07:52:17.70#ibcon#read 3, iclass 32, count 2 2006.218.07:52:17.70#ibcon#about to read 4, iclass 32, count 2 2006.218.07:52:17.70#ibcon#read 4, iclass 32, count 2 2006.218.07:52:17.70#ibcon#about to read 5, iclass 32, count 2 2006.218.07:52:17.70#ibcon#read 5, iclass 32, count 2 2006.218.07:52:17.70#ibcon#about to read 6, iclass 32, count 2 2006.218.07:52:17.70#ibcon#read 6, iclass 32, count 2 2006.218.07:52:17.70#ibcon#end of sib2, iclass 32, count 2 2006.218.07:52:17.70#ibcon#*mode == 0, iclass 32, count 2 2006.218.07:52:17.70#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.218.07:52:17.70#ibcon#[25=AT03-04\r\n] 2006.218.07:52:17.70#ibcon#*before write, iclass 32, count 2 2006.218.07:52:17.70#ibcon#enter sib2, iclass 32, count 2 2006.218.07:52:17.70#ibcon#flushed, iclass 32, count 2 2006.218.07:52:17.70#ibcon#about to write, iclass 32, count 2 2006.218.07:52:17.70#ibcon#wrote, iclass 32, count 2 2006.218.07:52:17.70#ibcon#about to read 3, iclass 32, count 2 2006.218.07:52:17.73#ibcon#read 3, iclass 32, count 2 2006.218.07:52:17.73#ibcon#about to read 4, iclass 32, count 2 2006.218.07:52:17.73#ibcon#read 4, iclass 32, count 2 2006.218.07:52:17.73#ibcon#about to read 5, iclass 32, count 2 2006.218.07:52:17.73#ibcon#read 5, iclass 32, count 2 2006.218.07:52:17.73#ibcon#about to read 6, iclass 32, count 2 2006.218.07:52:17.73#ibcon#read 6, iclass 32, count 2 2006.218.07:52:17.73#ibcon#end of sib2, iclass 32, count 2 2006.218.07:52:17.73#ibcon#*after write, iclass 32, count 2 2006.218.07:52:17.73#ibcon#*before return 0, iclass 32, count 2 2006.218.07:52:17.73#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.218.07:52:17.73#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.218.07:52:17.73#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.218.07:52:17.73#ibcon#ireg 7 cls_cnt 0 2006.218.07:52:17.73#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.218.07:52:17.85#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.218.07:52:17.85#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.218.07:52:17.85#ibcon#enter wrdev, iclass 32, count 0 2006.218.07:52:17.85#ibcon#first serial, iclass 32, count 0 2006.218.07:52:17.85#ibcon#enter sib2, iclass 32, count 0 2006.218.07:52:17.85#ibcon#flushed, iclass 32, count 0 2006.218.07:52:17.85#ibcon#about to write, iclass 32, count 0 2006.218.07:52:17.85#ibcon#wrote, iclass 32, count 0 2006.218.07:52:17.85#ibcon#about to read 3, iclass 32, count 0 2006.218.07:52:17.87#ibcon#read 3, iclass 32, count 0 2006.218.07:52:17.87#ibcon#about to read 4, iclass 32, count 0 2006.218.07:52:17.87#ibcon#read 4, iclass 32, count 0 2006.218.07:52:17.87#ibcon#about to read 5, iclass 32, count 0 2006.218.07:52:17.87#ibcon#read 5, iclass 32, count 0 2006.218.07:52:17.87#ibcon#about to read 6, iclass 32, count 0 2006.218.07:52:17.87#ibcon#read 6, iclass 32, count 0 2006.218.07:52:17.87#ibcon#end of sib2, iclass 32, count 0 2006.218.07:52:17.87#ibcon#*mode == 0, iclass 32, count 0 2006.218.07:52:17.87#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.218.07:52:17.87#ibcon#[25=USB\r\n] 2006.218.07:52:17.87#ibcon#*before write, iclass 32, count 0 2006.218.07:52:17.87#ibcon#enter sib2, iclass 32, count 0 2006.218.07:52:17.87#ibcon#flushed, iclass 32, count 0 2006.218.07:52:17.87#ibcon#about to write, iclass 32, count 0 2006.218.07:52:17.87#ibcon#wrote, iclass 32, count 0 2006.218.07:52:17.87#ibcon#about to read 3, iclass 32, count 0 2006.218.07:52:17.90#ibcon#read 3, iclass 32, count 0 2006.218.07:52:17.90#ibcon#about to read 4, iclass 32, count 0 2006.218.07:52:17.90#ibcon#read 4, iclass 32, count 0 2006.218.07:52:17.90#ibcon#about to read 5, iclass 32, count 0 2006.218.07:52:17.90#ibcon#read 5, iclass 32, count 0 2006.218.07:52:17.90#ibcon#about to read 6, iclass 32, count 0 2006.218.07:52:17.90#ibcon#read 6, iclass 32, count 0 2006.218.07:52:17.90#ibcon#end of sib2, iclass 32, count 0 2006.218.07:52:17.90#ibcon#*after write, iclass 32, count 0 2006.218.07:52:17.90#ibcon#*before return 0, iclass 32, count 0 2006.218.07:52:17.90#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.218.07:52:17.90#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.218.07:52:17.90#ibcon#about to clear, iclass 32 cls_cnt 0 2006.218.07:52:17.90#ibcon#cleared, iclass 32 cls_cnt 0 2006.218.07:52:17.90$vc4f8/valo=4,832.99 2006.218.07:52:17.90#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.218.07:52:17.90#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.218.07:52:17.90#ibcon#ireg 17 cls_cnt 0 2006.218.07:52:17.90#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.218.07:52:17.90#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.218.07:52:17.90#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.218.07:52:17.90#ibcon#enter wrdev, iclass 34, count 0 2006.218.07:52:17.90#ibcon#first serial, iclass 34, count 0 2006.218.07:52:17.90#ibcon#enter sib2, iclass 34, count 0 2006.218.07:52:17.90#ibcon#flushed, iclass 34, count 0 2006.218.07:52:17.90#ibcon#about to write, iclass 34, count 0 2006.218.07:52:17.90#ibcon#wrote, iclass 34, count 0 2006.218.07:52:17.90#ibcon#about to read 3, iclass 34, count 0 2006.218.07:52:17.92#ibcon#read 3, iclass 34, count 0 2006.218.07:52:17.92#ibcon#about to read 4, iclass 34, count 0 2006.218.07:52:17.92#ibcon#read 4, iclass 34, count 0 2006.218.07:52:17.92#ibcon#about to read 5, iclass 34, count 0 2006.218.07:52:17.92#ibcon#read 5, iclass 34, count 0 2006.218.07:52:17.92#ibcon#about to read 6, iclass 34, count 0 2006.218.07:52:17.92#ibcon#read 6, iclass 34, count 0 2006.218.07:52:17.92#ibcon#end of sib2, iclass 34, count 0 2006.218.07:52:17.92#ibcon#*mode == 0, iclass 34, count 0 2006.218.07:52:17.92#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.218.07:52:17.92#ibcon#[26=FRQ=04,832.99\r\n] 2006.218.07:52:17.92#ibcon#*before write, iclass 34, count 0 2006.218.07:52:17.92#ibcon#enter sib2, iclass 34, count 0 2006.218.07:52:17.92#ibcon#flushed, iclass 34, count 0 2006.218.07:52:17.92#ibcon#about to write, iclass 34, count 0 2006.218.07:52:17.92#ibcon#wrote, iclass 34, count 0 2006.218.07:52:17.92#ibcon#about to read 3, iclass 34, count 0 2006.218.07:52:17.96#ibcon#read 3, iclass 34, count 0 2006.218.07:52:17.96#ibcon#about to read 4, iclass 34, count 0 2006.218.07:52:17.96#ibcon#read 4, iclass 34, count 0 2006.218.07:52:17.96#ibcon#about to read 5, iclass 34, count 0 2006.218.07:52:17.96#ibcon#read 5, iclass 34, count 0 2006.218.07:52:17.96#ibcon#about to read 6, iclass 34, count 0 2006.218.07:52:17.96#ibcon#read 6, iclass 34, count 0 2006.218.07:52:17.96#ibcon#end of sib2, iclass 34, count 0 2006.218.07:52:17.96#ibcon#*after write, iclass 34, count 0 2006.218.07:52:17.96#ibcon#*before return 0, iclass 34, count 0 2006.218.07:52:17.96#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.218.07:52:17.96#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.218.07:52:17.96#ibcon#about to clear, iclass 34 cls_cnt 0 2006.218.07:52:17.96#ibcon#cleared, iclass 34 cls_cnt 0 2006.218.07:52:17.96$vc4f8/va=4,4 2006.218.07:52:17.96#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.218.07:52:17.96#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.218.07:52:17.96#ibcon#ireg 11 cls_cnt 2 2006.218.07:52:17.96#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.218.07:52:18.02#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.218.07:52:18.02#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.218.07:52:18.02#ibcon#enter wrdev, iclass 36, count 2 2006.218.07:52:18.02#ibcon#first serial, iclass 36, count 2 2006.218.07:52:18.02#ibcon#enter sib2, iclass 36, count 2 2006.218.07:52:18.02#ibcon#flushed, iclass 36, count 2 2006.218.07:52:18.02#ibcon#about to write, iclass 36, count 2 2006.218.07:52:18.02#ibcon#wrote, iclass 36, count 2 2006.218.07:52:18.02#ibcon#about to read 3, iclass 36, count 2 2006.218.07:52:18.04#ibcon#read 3, iclass 36, count 2 2006.218.07:52:18.04#ibcon#about to read 4, iclass 36, count 2 2006.218.07:52:18.04#ibcon#read 4, iclass 36, count 2 2006.218.07:52:18.04#ibcon#about to read 5, iclass 36, count 2 2006.218.07:52:18.04#ibcon#read 5, iclass 36, count 2 2006.218.07:52:18.04#ibcon#about to read 6, iclass 36, count 2 2006.218.07:52:18.04#ibcon#read 6, iclass 36, count 2 2006.218.07:52:18.04#ibcon#end of sib2, iclass 36, count 2 2006.218.07:52:18.04#ibcon#*mode == 0, iclass 36, count 2 2006.218.07:52:18.04#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.218.07:52:18.04#ibcon#[25=AT04-04\r\n] 2006.218.07:52:18.04#ibcon#*before write, iclass 36, count 2 2006.218.07:52:18.04#ibcon#enter sib2, iclass 36, count 2 2006.218.07:52:18.04#ibcon#flushed, iclass 36, count 2 2006.218.07:52:18.04#ibcon#about to write, iclass 36, count 2 2006.218.07:52:18.04#ibcon#wrote, iclass 36, count 2 2006.218.07:52:18.04#ibcon#about to read 3, iclass 36, count 2 2006.218.07:52:18.07#ibcon#read 3, iclass 36, count 2 2006.218.07:52:18.07#ibcon#about to read 4, iclass 36, count 2 2006.218.07:52:18.07#ibcon#read 4, iclass 36, count 2 2006.218.07:52:18.07#ibcon#about to read 5, iclass 36, count 2 2006.218.07:52:18.07#ibcon#read 5, iclass 36, count 2 2006.218.07:52:18.07#ibcon#about to read 6, iclass 36, count 2 2006.218.07:52:18.07#ibcon#read 6, iclass 36, count 2 2006.218.07:52:18.07#ibcon#end of sib2, iclass 36, count 2 2006.218.07:52:18.07#ibcon#*after write, iclass 36, count 2 2006.218.07:52:18.07#ibcon#*before return 0, iclass 36, count 2 2006.218.07:52:18.07#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.218.07:52:18.07#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.218.07:52:18.07#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.218.07:52:18.07#ibcon#ireg 7 cls_cnt 0 2006.218.07:52:18.07#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.218.07:52:18.19#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.218.07:52:18.19#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.218.07:52:18.19#ibcon#enter wrdev, iclass 36, count 0 2006.218.07:52:18.19#ibcon#first serial, iclass 36, count 0 2006.218.07:52:18.19#ibcon#enter sib2, iclass 36, count 0 2006.218.07:52:18.19#ibcon#flushed, iclass 36, count 0 2006.218.07:52:18.19#ibcon#about to write, iclass 36, count 0 2006.218.07:52:18.19#ibcon#wrote, iclass 36, count 0 2006.218.07:52:18.19#ibcon#about to read 3, iclass 36, count 0 2006.218.07:52:18.21#ibcon#read 3, iclass 36, count 0 2006.218.07:52:18.21#ibcon#about to read 4, iclass 36, count 0 2006.218.07:52:18.21#ibcon#read 4, iclass 36, count 0 2006.218.07:52:18.21#ibcon#about to read 5, iclass 36, count 0 2006.218.07:52:18.21#ibcon#read 5, iclass 36, count 0 2006.218.07:52:18.21#ibcon#about to read 6, iclass 36, count 0 2006.218.07:52:18.21#ibcon#read 6, iclass 36, count 0 2006.218.07:52:18.21#ibcon#end of sib2, iclass 36, count 0 2006.218.07:52:18.21#ibcon#*mode == 0, iclass 36, count 0 2006.218.07:52:18.21#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.218.07:52:18.21#ibcon#[25=USB\r\n] 2006.218.07:52:18.21#ibcon#*before write, iclass 36, count 0 2006.218.07:52:18.21#ibcon#enter sib2, iclass 36, count 0 2006.218.07:52:18.21#ibcon#flushed, iclass 36, count 0 2006.218.07:52:18.21#ibcon#about to write, iclass 36, count 0 2006.218.07:52:18.21#ibcon#wrote, iclass 36, count 0 2006.218.07:52:18.21#ibcon#about to read 3, iclass 36, count 0 2006.218.07:52:18.24#ibcon#read 3, iclass 36, count 0 2006.218.07:52:18.24#ibcon#about to read 4, iclass 36, count 0 2006.218.07:52:18.24#ibcon#read 4, iclass 36, count 0 2006.218.07:52:18.24#ibcon#about to read 5, iclass 36, count 0 2006.218.07:52:18.24#ibcon#read 5, iclass 36, count 0 2006.218.07:52:18.24#ibcon#about to read 6, iclass 36, count 0 2006.218.07:52:18.24#ibcon#read 6, iclass 36, count 0 2006.218.07:52:18.24#ibcon#end of sib2, iclass 36, count 0 2006.218.07:52:18.24#ibcon#*after write, iclass 36, count 0 2006.218.07:52:18.24#ibcon#*before return 0, iclass 36, count 0 2006.218.07:52:18.24#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.218.07:52:18.24#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.218.07:52:18.24#ibcon#about to clear, iclass 36 cls_cnt 0 2006.218.07:52:18.24#ibcon#cleared, iclass 36 cls_cnt 0 2006.218.07:52:18.24$vc4f8/valo=5,652.99 2006.218.07:52:18.24#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.218.07:52:18.24#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.218.07:52:18.24#ibcon#ireg 17 cls_cnt 0 2006.218.07:52:18.24#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.218.07:52:18.24#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.218.07:52:18.24#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.218.07:52:18.24#ibcon#enter wrdev, iclass 38, count 0 2006.218.07:52:18.24#ibcon#first serial, iclass 38, count 0 2006.218.07:52:18.24#ibcon#enter sib2, iclass 38, count 0 2006.218.07:52:18.24#ibcon#flushed, iclass 38, count 0 2006.218.07:52:18.24#ibcon#about to write, iclass 38, count 0 2006.218.07:52:18.24#ibcon#wrote, iclass 38, count 0 2006.218.07:52:18.24#ibcon#about to read 3, iclass 38, count 0 2006.218.07:52:18.26#ibcon#read 3, iclass 38, count 0 2006.218.07:52:18.26#ibcon#about to read 4, iclass 38, count 0 2006.218.07:52:18.26#ibcon#read 4, iclass 38, count 0 2006.218.07:52:18.26#ibcon#about to read 5, iclass 38, count 0 2006.218.07:52:18.26#ibcon#read 5, iclass 38, count 0 2006.218.07:52:18.26#ibcon#about to read 6, iclass 38, count 0 2006.218.07:52:18.26#ibcon#read 6, iclass 38, count 0 2006.218.07:52:18.26#ibcon#end of sib2, iclass 38, count 0 2006.218.07:52:18.26#ibcon#*mode == 0, iclass 38, count 0 2006.218.07:52:18.26#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.218.07:52:18.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.218.07:52:18.26#ibcon#*before write, iclass 38, count 0 2006.218.07:52:18.26#ibcon#enter sib2, iclass 38, count 0 2006.218.07:52:18.26#ibcon#flushed, iclass 38, count 0 2006.218.07:52:18.26#ibcon#about to write, iclass 38, count 0 2006.218.07:52:18.26#ibcon#wrote, iclass 38, count 0 2006.218.07:52:18.26#ibcon#about to read 3, iclass 38, count 0 2006.218.07:52:18.30#ibcon#read 3, iclass 38, count 0 2006.218.07:52:18.30#ibcon#about to read 4, iclass 38, count 0 2006.218.07:52:18.30#ibcon#read 4, iclass 38, count 0 2006.218.07:52:18.30#ibcon#about to read 5, iclass 38, count 0 2006.218.07:52:18.30#ibcon#read 5, iclass 38, count 0 2006.218.07:52:18.30#ibcon#about to read 6, iclass 38, count 0 2006.218.07:52:18.30#ibcon#read 6, iclass 38, count 0 2006.218.07:52:18.30#ibcon#end of sib2, iclass 38, count 0 2006.218.07:52:18.30#ibcon#*after write, iclass 38, count 0 2006.218.07:52:18.30#ibcon#*before return 0, iclass 38, count 0 2006.218.07:52:18.30#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.218.07:52:18.30#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.218.07:52:18.30#ibcon#about to clear, iclass 38 cls_cnt 0 2006.218.07:52:18.30#ibcon#cleared, iclass 38 cls_cnt 0 2006.218.07:52:18.30$vc4f8/va=5,7 2006.218.07:52:18.30#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.218.07:52:18.30#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.218.07:52:18.30#ibcon#ireg 11 cls_cnt 2 2006.218.07:52:18.30#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.218.07:52:18.36#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.218.07:52:18.36#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.218.07:52:18.36#ibcon#enter wrdev, iclass 40, count 2 2006.218.07:52:18.36#ibcon#first serial, iclass 40, count 2 2006.218.07:52:18.36#ibcon#enter sib2, iclass 40, count 2 2006.218.07:52:18.36#ibcon#flushed, iclass 40, count 2 2006.218.07:52:18.36#ibcon#about to write, iclass 40, count 2 2006.218.07:52:18.36#ibcon#wrote, iclass 40, count 2 2006.218.07:52:18.36#ibcon#about to read 3, iclass 40, count 2 2006.218.07:52:18.38#ibcon#read 3, iclass 40, count 2 2006.218.07:52:18.38#ibcon#about to read 4, iclass 40, count 2 2006.218.07:52:18.38#ibcon#read 4, iclass 40, count 2 2006.218.07:52:18.38#ibcon#about to read 5, iclass 40, count 2 2006.218.07:52:18.38#ibcon#read 5, iclass 40, count 2 2006.218.07:52:18.38#ibcon#about to read 6, iclass 40, count 2 2006.218.07:52:18.38#ibcon#read 6, iclass 40, count 2 2006.218.07:52:18.38#ibcon#end of sib2, iclass 40, count 2 2006.218.07:52:18.38#ibcon#*mode == 0, iclass 40, count 2 2006.218.07:52:18.38#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.218.07:52:18.38#ibcon#[25=AT05-07\r\n] 2006.218.07:52:18.38#ibcon#*before write, iclass 40, count 2 2006.218.07:52:18.38#ibcon#enter sib2, iclass 40, count 2 2006.218.07:52:18.38#ibcon#flushed, iclass 40, count 2 2006.218.07:52:18.38#ibcon#about to write, iclass 40, count 2 2006.218.07:52:18.38#ibcon#wrote, iclass 40, count 2 2006.218.07:52:18.38#ibcon#about to read 3, iclass 40, count 2 2006.218.07:52:18.41#ibcon#read 3, iclass 40, count 2 2006.218.07:52:18.41#ibcon#about to read 4, iclass 40, count 2 2006.218.07:52:18.41#ibcon#read 4, iclass 40, count 2 2006.218.07:52:18.41#ibcon#about to read 5, iclass 40, count 2 2006.218.07:52:18.41#ibcon#read 5, iclass 40, count 2 2006.218.07:52:18.41#ibcon#about to read 6, iclass 40, count 2 2006.218.07:52:18.41#ibcon#read 6, iclass 40, count 2 2006.218.07:52:18.41#ibcon#end of sib2, iclass 40, count 2 2006.218.07:52:18.41#ibcon#*after write, iclass 40, count 2 2006.218.07:52:18.41#ibcon#*before return 0, iclass 40, count 2 2006.218.07:52:18.41#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.218.07:52:18.41#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.218.07:52:18.41#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.218.07:52:18.41#ibcon#ireg 7 cls_cnt 0 2006.218.07:52:18.41#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.218.07:52:18.53#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.218.07:52:18.53#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.218.07:52:18.53#ibcon#enter wrdev, iclass 40, count 0 2006.218.07:52:18.53#ibcon#first serial, iclass 40, count 0 2006.218.07:52:18.53#ibcon#enter sib2, iclass 40, count 0 2006.218.07:52:18.53#ibcon#flushed, iclass 40, count 0 2006.218.07:52:18.53#ibcon#about to write, iclass 40, count 0 2006.218.07:52:18.53#ibcon#wrote, iclass 40, count 0 2006.218.07:52:18.53#ibcon#about to read 3, iclass 40, count 0 2006.218.07:52:18.55#ibcon#read 3, iclass 40, count 0 2006.218.07:52:18.55#ibcon#about to read 4, iclass 40, count 0 2006.218.07:52:18.55#ibcon#read 4, iclass 40, count 0 2006.218.07:52:18.55#ibcon#about to read 5, iclass 40, count 0 2006.218.07:52:18.55#ibcon#read 5, iclass 40, count 0 2006.218.07:52:18.55#ibcon#about to read 6, iclass 40, count 0 2006.218.07:52:18.55#ibcon#read 6, iclass 40, count 0 2006.218.07:52:18.55#ibcon#end of sib2, iclass 40, count 0 2006.218.07:52:18.55#ibcon#*mode == 0, iclass 40, count 0 2006.218.07:52:18.55#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.218.07:52:18.55#ibcon#[25=USB\r\n] 2006.218.07:52:18.55#ibcon#*before write, iclass 40, count 0 2006.218.07:52:18.55#ibcon#enter sib2, iclass 40, count 0 2006.218.07:52:18.55#ibcon#flushed, iclass 40, count 0 2006.218.07:52:18.55#ibcon#about to write, iclass 40, count 0 2006.218.07:52:18.55#ibcon#wrote, iclass 40, count 0 2006.218.07:52:18.55#ibcon#about to read 3, iclass 40, count 0 2006.218.07:52:18.58#ibcon#read 3, iclass 40, count 0 2006.218.07:52:18.58#ibcon#about to read 4, iclass 40, count 0 2006.218.07:52:18.58#ibcon#read 4, iclass 40, count 0 2006.218.07:52:18.58#ibcon#about to read 5, iclass 40, count 0 2006.218.07:52:18.58#ibcon#read 5, iclass 40, count 0 2006.218.07:52:18.58#ibcon#about to read 6, iclass 40, count 0 2006.218.07:52:18.58#ibcon#read 6, iclass 40, count 0 2006.218.07:52:18.58#ibcon#end of sib2, iclass 40, count 0 2006.218.07:52:18.58#ibcon#*after write, iclass 40, count 0 2006.218.07:52:18.58#ibcon#*before return 0, iclass 40, count 0 2006.218.07:52:18.58#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.218.07:52:18.58#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.218.07:52:18.58#ibcon#about to clear, iclass 40 cls_cnt 0 2006.218.07:52:18.58#ibcon#cleared, iclass 40 cls_cnt 0 2006.218.07:52:18.58$vc4f8/valo=6,772.99 2006.218.07:52:18.58#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.218.07:52:18.58#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.218.07:52:18.58#ibcon#ireg 17 cls_cnt 0 2006.218.07:52:18.58#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.218.07:52:18.58#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.218.07:52:18.58#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.218.07:52:18.58#ibcon#enter wrdev, iclass 4, count 0 2006.218.07:52:18.58#ibcon#first serial, iclass 4, count 0 2006.218.07:52:18.58#ibcon#enter sib2, iclass 4, count 0 2006.218.07:52:18.58#ibcon#flushed, iclass 4, count 0 2006.218.07:52:18.58#ibcon#about to write, iclass 4, count 0 2006.218.07:52:18.58#ibcon#wrote, iclass 4, count 0 2006.218.07:52:18.58#ibcon#about to read 3, iclass 4, count 0 2006.218.07:52:18.61#ibcon#read 3, iclass 4, count 0 2006.218.07:52:18.61#ibcon#about to read 4, iclass 4, count 0 2006.218.07:52:18.61#ibcon#read 4, iclass 4, count 0 2006.218.07:52:18.61#ibcon#about to read 5, iclass 4, count 0 2006.218.07:52:18.61#ibcon#read 5, iclass 4, count 0 2006.218.07:52:18.61#ibcon#about to read 6, iclass 4, count 0 2006.218.07:52:18.61#ibcon#read 6, iclass 4, count 0 2006.218.07:52:18.61#ibcon#end of sib2, iclass 4, count 0 2006.218.07:52:18.61#ibcon#*mode == 0, iclass 4, count 0 2006.218.07:52:18.61#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.218.07:52:18.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.218.07:52:18.61#ibcon#*before write, iclass 4, count 0 2006.218.07:52:18.61#ibcon#enter sib2, iclass 4, count 0 2006.218.07:52:18.61#ibcon#flushed, iclass 4, count 0 2006.218.07:52:18.61#ibcon#about to write, iclass 4, count 0 2006.218.07:52:18.61#ibcon#wrote, iclass 4, count 0 2006.218.07:52:18.61#ibcon#about to read 3, iclass 4, count 0 2006.218.07:52:18.65#ibcon#read 3, iclass 4, count 0 2006.218.07:52:18.65#ibcon#about to read 4, iclass 4, count 0 2006.218.07:52:18.65#ibcon#read 4, iclass 4, count 0 2006.218.07:52:18.65#ibcon#about to read 5, iclass 4, count 0 2006.218.07:52:18.65#ibcon#read 5, iclass 4, count 0 2006.218.07:52:18.65#ibcon#about to read 6, iclass 4, count 0 2006.218.07:52:18.65#ibcon#read 6, iclass 4, count 0 2006.218.07:52:18.65#ibcon#end of sib2, iclass 4, count 0 2006.218.07:52:18.65#ibcon#*after write, iclass 4, count 0 2006.218.07:52:18.65#ibcon#*before return 0, iclass 4, count 0 2006.218.07:52:18.65#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.218.07:52:18.65#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.218.07:52:18.65#ibcon#about to clear, iclass 4 cls_cnt 0 2006.218.07:52:18.65#ibcon#cleared, iclass 4 cls_cnt 0 2006.218.07:52:18.65$vc4f8/va=6,6 2006.218.07:52:18.65#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.218.07:52:18.65#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.218.07:52:18.65#ibcon#ireg 11 cls_cnt 2 2006.218.07:52:18.65#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.218.07:52:18.70#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.218.07:52:18.70#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.218.07:52:18.70#ibcon#enter wrdev, iclass 6, count 2 2006.218.07:52:18.70#ibcon#first serial, iclass 6, count 2 2006.218.07:52:18.70#ibcon#enter sib2, iclass 6, count 2 2006.218.07:52:18.70#ibcon#flushed, iclass 6, count 2 2006.218.07:52:18.70#ibcon#about to write, iclass 6, count 2 2006.218.07:52:18.70#ibcon#wrote, iclass 6, count 2 2006.218.07:52:18.70#ibcon#about to read 3, iclass 6, count 2 2006.218.07:52:18.72#ibcon#read 3, iclass 6, count 2 2006.218.07:52:18.72#ibcon#about to read 4, iclass 6, count 2 2006.218.07:52:18.72#ibcon#read 4, iclass 6, count 2 2006.218.07:52:18.72#ibcon#about to read 5, iclass 6, count 2 2006.218.07:52:18.72#ibcon#read 5, iclass 6, count 2 2006.218.07:52:18.72#ibcon#about to read 6, iclass 6, count 2 2006.218.07:52:18.72#ibcon#read 6, iclass 6, count 2 2006.218.07:52:18.72#ibcon#end of sib2, iclass 6, count 2 2006.218.07:52:18.72#ibcon#*mode == 0, iclass 6, count 2 2006.218.07:52:18.72#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.218.07:52:18.72#ibcon#[25=AT06-06\r\n] 2006.218.07:52:18.72#ibcon#*before write, iclass 6, count 2 2006.218.07:52:18.72#ibcon#enter sib2, iclass 6, count 2 2006.218.07:52:18.72#ibcon#flushed, iclass 6, count 2 2006.218.07:52:18.72#ibcon#about to write, iclass 6, count 2 2006.218.07:52:18.72#ibcon#wrote, iclass 6, count 2 2006.218.07:52:18.72#ibcon#about to read 3, iclass 6, count 2 2006.218.07:52:18.75#ibcon#read 3, iclass 6, count 2 2006.218.07:52:18.75#ibcon#about to read 4, iclass 6, count 2 2006.218.07:52:18.75#ibcon#read 4, iclass 6, count 2 2006.218.07:52:18.75#ibcon#about to read 5, iclass 6, count 2 2006.218.07:52:18.75#ibcon#read 5, iclass 6, count 2 2006.218.07:52:18.75#ibcon#about to read 6, iclass 6, count 2 2006.218.07:52:18.75#ibcon#read 6, iclass 6, count 2 2006.218.07:52:18.75#ibcon#end of sib2, iclass 6, count 2 2006.218.07:52:18.75#ibcon#*after write, iclass 6, count 2 2006.218.07:52:18.75#ibcon#*before return 0, iclass 6, count 2 2006.218.07:52:18.75#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.218.07:52:18.75#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.218.07:52:18.75#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.218.07:52:18.75#ibcon#ireg 7 cls_cnt 0 2006.218.07:52:18.75#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.218.07:52:18.87#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.218.07:52:18.87#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.218.07:52:18.87#ibcon#enter wrdev, iclass 6, count 0 2006.218.07:52:18.87#ibcon#first serial, iclass 6, count 0 2006.218.07:52:18.87#ibcon#enter sib2, iclass 6, count 0 2006.218.07:52:18.87#ibcon#flushed, iclass 6, count 0 2006.218.07:52:18.87#ibcon#about to write, iclass 6, count 0 2006.218.07:52:18.87#ibcon#wrote, iclass 6, count 0 2006.218.07:52:18.87#ibcon#about to read 3, iclass 6, count 0 2006.218.07:52:18.89#ibcon#read 3, iclass 6, count 0 2006.218.07:52:18.89#ibcon#about to read 4, iclass 6, count 0 2006.218.07:52:18.89#ibcon#read 4, iclass 6, count 0 2006.218.07:52:18.89#ibcon#about to read 5, iclass 6, count 0 2006.218.07:52:18.89#ibcon#read 5, iclass 6, count 0 2006.218.07:52:18.89#ibcon#about to read 6, iclass 6, count 0 2006.218.07:52:18.89#ibcon#read 6, iclass 6, count 0 2006.218.07:52:18.89#ibcon#end of sib2, iclass 6, count 0 2006.218.07:52:18.89#ibcon#*mode == 0, iclass 6, count 0 2006.218.07:52:18.89#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.218.07:52:18.89#ibcon#[25=USB\r\n] 2006.218.07:52:18.89#ibcon#*before write, iclass 6, count 0 2006.218.07:52:18.89#ibcon#enter sib2, iclass 6, count 0 2006.218.07:52:18.89#ibcon#flushed, iclass 6, count 0 2006.218.07:52:18.89#ibcon#about to write, iclass 6, count 0 2006.218.07:52:18.89#ibcon#wrote, iclass 6, count 0 2006.218.07:52:18.89#ibcon#about to read 3, iclass 6, count 0 2006.218.07:52:18.92#ibcon#read 3, iclass 6, count 0 2006.218.07:52:18.92#ibcon#about to read 4, iclass 6, count 0 2006.218.07:52:18.92#ibcon#read 4, iclass 6, count 0 2006.218.07:52:18.92#ibcon#about to read 5, iclass 6, count 0 2006.218.07:52:18.92#ibcon#read 5, iclass 6, count 0 2006.218.07:52:18.92#ibcon#about to read 6, iclass 6, count 0 2006.218.07:52:18.92#ibcon#read 6, iclass 6, count 0 2006.218.07:52:18.92#ibcon#end of sib2, iclass 6, count 0 2006.218.07:52:18.92#ibcon#*after write, iclass 6, count 0 2006.218.07:52:18.92#ibcon#*before return 0, iclass 6, count 0 2006.218.07:52:18.92#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.218.07:52:18.92#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.218.07:52:18.92#ibcon#about to clear, iclass 6 cls_cnt 0 2006.218.07:52:18.92#ibcon#cleared, iclass 6 cls_cnt 0 2006.218.07:52:18.92$vc4f8/valo=7,832.99 2006.218.07:52:18.92#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.218.07:52:18.92#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.218.07:52:18.92#ibcon#ireg 17 cls_cnt 0 2006.218.07:52:18.92#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.218.07:52:18.92#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.218.07:52:18.92#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.218.07:52:18.92#ibcon#enter wrdev, iclass 10, count 0 2006.218.07:52:18.92#ibcon#first serial, iclass 10, count 0 2006.218.07:52:18.92#ibcon#enter sib2, iclass 10, count 0 2006.218.07:52:18.92#ibcon#flushed, iclass 10, count 0 2006.218.07:52:18.92#ibcon#about to write, iclass 10, count 0 2006.218.07:52:18.92#ibcon#wrote, iclass 10, count 0 2006.218.07:52:18.92#ibcon#about to read 3, iclass 10, count 0 2006.218.07:52:18.94#ibcon#read 3, iclass 10, count 0 2006.218.07:52:18.94#ibcon#about to read 4, iclass 10, count 0 2006.218.07:52:18.94#ibcon#read 4, iclass 10, count 0 2006.218.07:52:18.94#ibcon#about to read 5, iclass 10, count 0 2006.218.07:52:18.94#ibcon#read 5, iclass 10, count 0 2006.218.07:52:18.94#ibcon#about to read 6, iclass 10, count 0 2006.218.07:52:18.94#ibcon#read 6, iclass 10, count 0 2006.218.07:52:18.94#ibcon#end of sib2, iclass 10, count 0 2006.218.07:52:18.94#ibcon#*mode == 0, iclass 10, count 0 2006.218.07:52:18.94#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.218.07:52:18.94#ibcon#[26=FRQ=07,832.99\r\n] 2006.218.07:52:18.94#ibcon#*before write, iclass 10, count 0 2006.218.07:52:18.94#ibcon#enter sib2, iclass 10, count 0 2006.218.07:52:18.94#ibcon#flushed, iclass 10, count 0 2006.218.07:52:18.94#ibcon#about to write, iclass 10, count 0 2006.218.07:52:18.94#ibcon#wrote, iclass 10, count 0 2006.218.07:52:18.94#ibcon#about to read 3, iclass 10, count 0 2006.218.07:52:18.98#ibcon#read 3, iclass 10, count 0 2006.218.07:52:18.98#ibcon#about to read 4, iclass 10, count 0 2006.218.07:52:18.98#ibcon#read 4, iclass 10, count 0 2006.218.07:52:18.98#ibcon#about to read 5, iclass 10, count 0 2006.218.07:52:18.98#ibcon#read 5, iclass 10, count 0 2006.218.07:52:18.98#ibcon#about to read 6, iclass 10, count 0 2006.218.07:52:18.98#ibcon#read 6, iclass 10, count 0 2006.218.07:52:18.98#ibcon#end of sib2, iclass 10, count 0 2006.218.07:52:18.98#ibcon#*after write, iclass 10, count 0 2006.218.07:52:18.98#ibcon#*before return 0, iclass 10, count 0 2006.218.07:52:18.98#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.218.07:52:18.98#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.218.07:52:18.98#ibcon#about to clear, iclass 10 cls_cnt 0 2006.218.07:52:18.98#ibcon#cleared, iclass 10 cls_cnt 0 2006.218.07:52:18.98$vc4f8/va=7,6 2006.218.07:52:18.98#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.218.07:52:18.98#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.218.07:52:18.98#ibcon#ireg 11 cls_cnt 2 2006.218.07:52:18.98#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.218.07:52:19.04#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.218.07:52:19.04#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.218.07:52:19.04#ibcon#enter wrdev, iclass 12, count 2 2006.218.07:52:19.04#ibcon#first serial, iclass 12, count 2 2006.218.07:52:19.04#ibcon#enter sib2, iclass 12, count 2 2006.218.07:52:19.04#ibcon#flushed, iclass 12, count 2 2006.218.07:52:19.04#ibcon#about to write, iclass 12, count 2 2006.218.07:52:19.04#ibcon#wrote, iclass 12, count 2 2006.218.07:52:19.04#ibcon#about to read 3, iclass 12, count 2 2006.218.07:52:19.06#ibcon#read 3, iclass 12, count 2 2006.218.07:52:19.06#ibcon#about to read 4, iclass 12, count 2 2006.218.07:52:19.06#ibcon#read 4, iclass 12, count 2 2006.218.07:52:19.06#ibcon#about to read 5, iclass 12, count 2 2006.218.07:52:19.06#ibcon#read 5, iclass 12, count 2 2006.218.07:52:19.06#ibcon#about to read 6, iclass 12, count 2 2006.218.07:52:19.06#ibcon#read 6, iclass 12, count 2 2006.218.07:52:19.06#ibcon#end of sib2, iclass 12, count 2 2006.218.07:52:19.06#ibcon#*mode == 0, iclass 12, count 2 2006.218.07:52:19.06#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.218.07:52:19.06#ibcon#[25=AT07-06\r\n] 2006.218.07:52:19.06#ibcon#*before write, iclass 12, count 2 2006.218.07:52:19.06#ibcon#enter sib2, iclass 12, count 2 2006.218.07:52:19.06#ibcon#flushed, iclass 12, count 2 2006.218.07:52:19.06#ibcon#about to write, iclass 12, count 2 2006.218.07:52:19.06#ibcon#wrote, iclass 12, count 2 2006.218.07:52:19.06#ibcon#about to read 3, iclass 12, count 2 2006.218.07:52:19.09#ibcon#read 3, iclass 12, count 2 2006.218.07:52:19.09#ibcon#about to read 4, iclass 12, count 2 2006.218.07:52:19.09#ibcon#read 4, iclass 12, count 2 2006.218.07:52:19.09#ibcon#about to read 5, iclass 12, count 2 2006.218.07:52:19.09#ibcon#read 5, iclass 12, count 2 2006.218.07:52:19.09#ibcon#about to read 6, iclass 12, count 2 2006.218.07:52:19.09#ibcon#read 6, iclass 12, count 2 2006.218.07:52:19.09#ibcon#end of sib2, iclass 12, count 2 2006.218.07:52:19.09#ibcon#*after write, iclass 12, count 2 2006.218.07:52:19.09#ibcon#*before return 0, iclass 12, count 2 2006.218.07:52:19.09#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.218.07:52:19.09#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.218.07:52:19.09#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.218.07:52:19.09#ibcon#ireg 7 cls_cnt 0 2006.218.07:52:19.09#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.218.07:52:19.21#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.218.07:52:19.21#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.218.07:52:19.21#ibcon#enter wrdev, iclass 12, count 0 2006.218.07:52:19.21#ibcon#first serial, iclass 12, count 0 2006.218.07:52:19.21#ibcon#enter sib2, iclass 12, count 0 2006.218.07:52:19.21#ibcon#flushed, iclass 12, count 0 2006.218.07:52:19.21#ibcon#about to write, iclass 12, count 0 2006.218.07:52:19.21#ibcon#wrote, iclass 12, count 0 2006.218.07:52:19.21#ibcon#about to read 3, iclass 12, count 0 2006.218.07:52:19.23#ibcon#read 3, iclass 12, count 0 2006.218.07:52:19.23#ibcon#about to read 4, iclass 12, count 0 2006.218.07:52:19.23#ibcon#read 4, iclass 12, count 0 2006.218.07:52:19.23#ibcon#about to read 5, iclass 12, count 0 2006.218.07:52:19.23#ibcon#read 5, iclass 12, count 0 2006.218.07:52:19.23#ibcon#about to read 6, iclass 12, count 0 2006.218.07:52:19.23#ibcon#read 6, iclass 12, count 0 2006.218.07:52:19.23#ibcon#end of sib2, iclass 12, count 0 2006.218.07:52:19.23#ibcon#*mode == 0, iclass 12, count 0 2006.218.07:52:19.23#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.218.07:52:19.23#ibcon#[25=USB\r\n] 2006.218.07:52:19.23#ibcon#*before write, iclass 12, count 0 2006.218.07:52:19.23#ibcon#enter sib2, iclass 12, count 0 2006.218.07:52:19.23#ibcon#flushed, iclass 12, count 0 2006.218.07:52:19.23#ibcon#about to write, iclass 12, count 0 2006.218.07:52:19.23#ibcon#wrote, iclass 12, count 0 2006.218.07:52:19.23#ibcon#about to read 3, iclass 12, count 0 2006.218.07:52:19.26#ibcon#read 3, iclass 12, count 0 2006.218.07:52:19.26#ibcon#about to read 4, iclass 12, count 0 2006.218.07:52:19.26#ibcon#read 4, iclass 12, count 0 2006.218.07:52:19.26#ibcon#about to read 5, iclass 12, count 0 2006.218.07:52:19.26#ibcon#read 5, iclass 12, count 0 2006.218.07:52:19.26#ibcon#about to read 6, iclass 12, count 0 2006.218.07:52:19.26#ibcon#read 6, iclass 12, count 0 2006.218.07:52:19.26#ibcon#end of sib2, iclass 12, count 0 2006.218.07:52:19.26#ibcon#*after write, iclass 12, count 0 2006.218.07:52:19.26#ibcon#*before return 0, iclass 12, count 0 2006.218.07:52:19.26#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.218.07:52:19.26#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.218.07:52:19.26#ibcon#about to clear, iclass 12 cls_cnt 0 2006.218.07:52:19.26#ibcon#cleared, iclass 12 cls_cnt 0 2006.218.07:52:19.26$vc4f8/valo=8,852.99 2006.218.07:52:19.26#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.218.07:52:19.26#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.218.07:52:19.26#ibcon#ireg 17 cls_cnt 0 2006.218.07:52:19.26#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.218.07:52:19.26#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.218.07:52:19.26#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.218.07:52:19.26#ibcon#enter wrdev, iclass 14, count 0 2006.218.07:52:19.26#ibcon#first serial, iclass 14, count 0 2006.218.07:52:19.26#ibcon#enter sib2, iclass 14, count 0 2006.218.07:52:19.26#ibcon#flushed, iclass 14, count 0 2006.218.07:52:19.26#ibcon#about to write, iclass 14, count 0 2006.218.07:52:19.26#ibcon#wrote, iclass 14, count 0 2006.218.07:52:19.26#ibcon#about to read 3, iclass 14, count 0 2006.218.07:52:19.28#ibcon#read 3, iclass 14, count 0 2006.218.07:52:19.28#ibcon#about to read 4, iclass 14, count 0 2006.218.07:52:19.28#ibcon#read 4, iclass 14, count 0 2006.218.07:52:19.28#ibcon#about to read 5, iclass 14, count 0 2006.218.07:52:19.28#ibcon#read 5, iclass 14, count 0 2006.218.07:52:19.28#ibcon#about to read 6, iclass 14, count 0 2006.218.07:52:19.28#ibcon#read 6, iclass 14, count 0 2006.218.07:52:19.28#ibcon#end of sib2, iclass 14, count 0 2006.218.07:52:19.28#ibcon#*mode == 0, iclass 14, count 0 2006.218.07:52:19.28#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.218.07:52:19.28#ibcon#[26=FRQ=08,852.99\r\n] 2006.218.07:52:19.28#ibcon#*before write, iclass 14, count 0 2006.218.07:52:19.28#ibcon#enter sib2, iclass 14, count 0 2006.218.07:52:19.28#ibcon#flushed, iclass 14, count 0 2006.218.07:52:19.28#ibcon#about to write, iclass 14, count 0 2006.218.07:52:19.28#ibcon#wrote, iclass 14, count 0 2006.218.07:52:19.28#ibcon#about to read 3, iclass 14, count 0 2006.218.07:52:19.32#ibcon#read 3, iclass 14, count 0 2006.218.07:52:19.32#ibcon#about to read 4, iclass 14, count 0 2006.218.07:52:19.32#ibcon#read 4, iclass 14, count 0 2006.218.07:52:19.32#ibcon#about to read 5, iclass 14, count 0 2006.218.07:52:19.32#ibcon#read 5, iclass 14, count 0 2006.218.07:52:19.32#ibcon#about to read 6, iclass 14, count 0 2006.218.07:52:19.32#ibcon#read 6, iclass 14, count 0 2006.218.07:52:19.32#ibcon#end of sib2, iclass 14, count 0 2006.218.07:52:19.32#ibcon#*after write, iclass 14, count 0 2006.218.07:52:19.32#ibcon#*before return 0, iclass 14, count 0 2006.218.07:52:19.32#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.218.07:52:19.32#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.218.07:52:19.32#ibcon#about to clear, iclass 14 cls_cnt 0 2006.218.07:52:19.32#ibcon#cleared, iclass 14 cls_cnt 0 2006.218.07:52:19.32$vc4f8/va=8,7 2006.218.07:52:19.32#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.218.07:52:19.32#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.218.07:52:19.32#ibcon#ireg 11 cls_cnt 2 2006.218.07:52:19.32#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.218.07:52:19.38#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.218.07:52:19.38#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.218.07:52:19.38#ibcon#enter wrdev, iclass 16, count 2 2006.218.07:52:19.38#ibcon#first serial, iclass 16, count 2 2006.218.07:52:19.38#ibcon#enter sib2, iclass 16, count 2 2006.218.07:52:19.38#ibcon#flushed, iclass 16, count 2 2006.218.07:52:19.38#ibcon#about to write, iclass 16, count 2 2006.218.07:52:19.38#ibcon#wrote, iclass 16, count 2 2006.218.07:52:19.38#ibcon#about to read 3, iclass 16, count 2 2006.218.07:52:19.40#ibcon#read 3, iclass 16, count 2 2006.218.07:52:19.40#ibcon#about to read 4, iclass 16, count 2 2006.218.07:52:19.40#ibcon#read 4, iclass 16, count 2 2006.218.07:52:19.40#ibcon#about to read 5, iclass 16, count 2 2006.218.07:52:19.40#ibcon#read 5, iclass 16, count 2 2006.218.07:52:19.40#ibcon#about to read 6, iclass 16, count 2 2006.218.07:52:19.40#ibcon#read 6, iclass 16, count 2 2006.218.07:52:19.40#ibcon#end of sib2, iclass 16, count 2 2006.218.07:52:19.40#ibcon#*mode == 0, iclass 16, count 2 2006.218.07:52:19.40#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.218.07:52:19.40#ibcon#[25=AT08-07\r\n] 2006.218.07:52:19.40#ibcon#*before write, iclass 16, count 2 2006.218.07:52:19.40#ibcon#enter sib2, iclass 16, count 2 2006.218.07:52:19.40#ibcon#flushed, iclass 16, count 2 2006.218.07:52:19.40#ibcon#about to write, iclass 16, count 2 2006.218.07:52:19.40#ibcon#wrote, iclass 16, count 2 2006.218.07:52:19.40#ibcon#about to read 3, iclass 16, count 2 2006.218.07:52:19.43#ibcon#read 3, iclass 16, count 2 2006.218.07:52:19.43#ibcon#about to read 4, iclass 16, count 2 2006.218.07:52:19.43#ibcon#read 4, iclass 16, count 2 2006.218.07:52:19.43#ibcon#about to read 5, iclass 16, count 2 2006.218.07:52:19.43#ibcon#read 5, iclass 16, count 2 2006.218.07:52:19.43#ibcon#about to read 6, iclass 16, count 2 2006.218.07:52:19.43#ibcon#read 6, iclass 16, count 2 2006.218.07:52:19.43#ibcon#end of sib2, iclass 16, count 2 2006.218.07:52:19.43#ibcon#*after write, iclass 16, count 2 2006.218.07:52:19.43#ibcon#*before return 0, iclass 16, count 2 2006.218.07:52:19.43#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.218.07:52:19.43#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.218.07:52:19.43#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.218.07:52:19.43#ibcon#ireg 7 cls_cnt 0 2006.218.07:52:19.43#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.218.07:52:19.55#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.218.07:52:19.55#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.218.07:52:19.55#ibcon#enter wrdev, iclass 16, count 0 2006.218.07:52:19.55#ibcon#first serial, iclass 16, count 0 2006.218.07:52:19.55#ibcon#enter sib2, iclass 16, count 0 2006.218.07:52:19.55#ibcon#flushed, iclass 16, count 0 2006.218.07:52:19.55#ibcon#about to write, iclass 16, count 0 2006.218.07:52:19.55#ibcon#wrote, iclass 16, count 0 2006.218.07:52:19.55#ibcon#about to read 3, iclass 16, count 0 2006.218.07:52:19.57#ibcon#read 3, iclass 16, count 0 2006.218.07:52:19.57#ibcon#about to read 4, iclass 16, count 0 2006.218.07:52:19.57#ibcon#read 4, iclass 16, count 0 2006.218.07:52:19.57#ibcon#about to read 5, iclass 16, count 0 2006.218.07:52:19.57#ibcon#read 5, iclass 16, count 0 2006.218.07:52:19.57#ibcon#about to read 6, iclass 16, count 0 2006.218.07:52:19.57#ibcon#read 6, iclass 16, count 0 2006.218.07:52:19.57#ibcon#end of sib2, iclass 16, count 0 2006.218.07:52:19.57#ibcon#*mode == 0, iclass 16, count 0 2006.218.07:52:19.57#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.218.07:52:19.57#ibcon#[25=USB\r\n] 2006.218.07:52:19.57#ibcon#*before write, iclass 16, count 0 2006.218.07:52:19.57#ibcon#enter sib2, iclass 16, count 0 2006.218.07:52:19.57#ibcon#flushed, iclass 16, count 0 2006.218.07:52:19.57#ibcon#about to write, iclass 16, count 0 2006.218.07:52:19.57#ibcon#wrote, iclass 16, count 0 2006.218.07:52:19.57#ibcon#about to read 3, iclass 16, count 0 2006.218.07:52:19.60#ibcon#read 3, iclass 16, count 0 2006.218.07:52:19.60#ibcon#about to read 4, iclass 16, count 0 2006.218.07:52:19.60#ibcon#read 4, iclass 16, count 0 2006.218.07:52:19.60#ibcon#about to read 5, iclass 16, count 0 2006.218.07:52:19.60#ibcon#read 5, iclass 16, count 0 2006.218.07:52:19.60#ibcon#about to read 6, iclass 16, count 0 2006.218.07:52:19.60#ibcon#read 6, iclass 16, count 0 2006.218.07:52:19.60#ibcon#end of sib2, iclass 16, count 0 2006.218.07:52:19.60#ibcon#*after write, iclass 16, count 0 2006.218.07:52:19.60#ibcon#*before return 0, iclass 16, count 0 2006.218.07:52:19.60#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.218.07:52:19.60#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.218.07:52:19.60#ibcon#about to clear, iclass 16 cls_cnt 0 2006.218.07:52:19.60#ibcon#cleared, iclass 16 cls_cnt 0 2006.218.07:52:19.60$vc4f8/vblo=1,632.99 2006.218.07:52:19.60#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.218.07:52:19.60#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.218.07:52:19.60#ibcon#ireg 17 cls_cnt 0 2006.218.07:52:19.60#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.218.07:52:19.60#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.218.07:52:19.60#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.218.07:52:19.60#ibcon#enter wrdev, iclass 18, count 0 2006.218.07:52:19.60#ibcon#first serial, iclass 18, count 0 2006.218.07:52:19.60#ibcon#enter sib2, iclass 18, count 0 2006.218.07:52:19.60#ibcon#flushed, iclass 18, count 0 2006.218.07:52:19.60#ibcon#about to write, iclass 18, count 0 2006.218.07:52:19.60#ibcon#wrote, iclass 18, count 0 2006.218.07:52:19.60#ibcon#about to read 3, iclass 18, count 0 2006.218.07:52:19.62#ibcon#read 3, iclass 18, count 0 2006.218.07:52:19.62#ibcon#about to read 4, iclass 18, count 0 2006.218.07:52:19.62#ibcon#read 4, iclass 18, count 0 2006.218.07:52:19.62#ibcon#about to read 5, iclass 18, count 0 2006.218.07:52:19.62#ibcon#read 5, iclass 18, count 0 2006.218.07:52:19.62#ibcon#about to read 6, iclass 18, count 0 2006.218.07:52:19.62#ibcon#read 6, iclass 18, count 0 2006.218.07:52:19.62#ibcon#end of sib2, iclass 18, count 0 2006.218.07:52:19.62#ibcon#*mode == 0, iclass 18, count 0 2006.218.07:52:19.62#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.218.07:52:19.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.218.07:52:19.62#ibcon#*before write, iclass 18, count 0 2006.218.07:52:19.62#ibcon#enter sib2, iclass 18, count 0 2006.218.07:52:19.62#ibcon#flushed, iclass 18, count 0 2006.218.07:52:19.62#ibcon#about to write, iclass 18, count 0 2006.218.07:52:19.62#ibcon#wrote, iclass 18, count 0 2006.218.07:52:19.62#ibcon#about to read 3, iclass 18, count 0 2006.218.07:52:19.66#ibcon#read 3, iclass 18, count 0 2006.218.07:52:19.66#ibcon#about to read 4, iclass 18, count 0 2006.218.07:52:19.66#ibcon#read 4, iclass 18, count 0 2006.218.07:52:19.66#ibcon#about to read 5, iclass 18, count 0 2006.218.07:52:19.66#ibcon#read 5, iclass 18, count 0 2006.218.07:52:19.66#ibcon#about to read 6, iclass 18, count 0 2006.218.07:52:19.66#ibcon#read 6, iclass 18, count 0 2006.218.07:52:19.66#ibcon#end of sib2, iclass 18, count 0 2006.218.07:52:19.66#ibcon#*after write, iclass 18, count 0 2006.218.07:52:19.66#ibcon#*before return 0, iclass 18, count 0 2006.218.07:52:19.66#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.218.07:52:19.66#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.218.07:52:19.66#ibcon#about to clear, iclass 18 cls_cnt 0 2006.218.07:52:19.66#ibcon#cleared, iclass 18 cls_cnt 0 2006.218.07:52:19.66$vc4f8/vb=1,4 2006.218.07:52:19.66#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.218.07:52:19.66#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.218.07:52:19.66#ibcon#ireg 11 cls_cnt 2 2006.218.07:52:19.66#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.218.07:52:19.66#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.218.07:52:19.66#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.218.07:52:19.66#ibcon#enter wrdev, iclass 20, count 2 2006.218.07:52:19.66#ibcon#first serial, iclass 20, count 2 2006.218.07:52:19.66#ibcon#enter sib2, iclass 20, count 2 2006.218.07:52:19.66#ibcon#flushed, iclass 20, count 2 2006.218.07:52:19.66#ibcon#about to write, iclass 20, count 2 2006.218.07:52:19.66#ibcon#wrote, iclass 20, count 2 2006.218.07:52:19.66#ibcon#about to read 3, iclass 20, count 2 2006.218.07:52:19.68#ibcon#read 3, iclass 20, count 2 2006.218.07:52:19.68#ibcon#about to read 4, iclass 20, count 2 2006.218.07:52:19.68#ibcon#read 4, iclass 20, count 2 2006.218.07:52:19.68#ibcon#about to read 5, iclass 20, count 2 2006.218.07:52:19.68#ibcon#read 5, iclass 20, count 2 2006.218.07:52:19.68#ibcon#about to read 6, iclass 20, count 2 2006.218.07:52:19.68#ibcon#read 6, iclass 20, count 2 2006.218.07:52:19.68#ibcon#end of sib2, iclass 20, count 2 2006.218.07:52:19.68#ibcon#*mode == 0, iclass 20, count 2 2006.218.07:52:19.68#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.218.07:52:19.68#ibcon#[27=AT01-04\r\n] 2006.218.07:52:19.68#ibcon#*before write, iclass 20, count 2 2006.218.07:52:19.68#ibcon#enter sib2, iclass 20, count 2 2006.218.07:52:19.68#ibcon#flushed, iclass 20, count 2 2006.218.07:52:19.68#ibcon#about to write, iclass 20, count 2 2006.218.07:52:19.68#ibcon#wrote, iclass 20, count 2 2006.218.07:52:19.68#ibcon#about to read 3, iclass 20, count 2 2006.218.07:52:19.71#ibcon#read 3, iclass 20, count 2 2006.218.07:52:19.71#ibcon#about to read 4, iclass 20, count 2 2006.218.07:52:19.71#ibcon#read 4, iclass 20, count 2 2006.218.07:52:19.71#ibcon#about to read 5, iclass 20, count 2 2006.218.07:52:19.71#ibcon#read 5, iclass 20, count 2 2006.218.07:52:19.71#ibcon#about to read 6, iclass 20, count 2 2006.218.07:52:19.71#ibcon#read 6, iclass 20, count 2 2006.218.07:52:19.71#ibcon#end of sib2, iclass 20, count 2 2006.218.07:52:19.71#ibcon#*after write, iclass 20, count 2 2006.218.07:52:19.71#ibcon#*before return 0, iclass 20, count 2 2006.218.07:52:19.71#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.218.07:52:19.71#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.218.07:52:19.71#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.218.07:52:19.71#ibcon#ireg 7 cls_cnt 0 2006.218.07:52:19.71#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.218.07:52:19.83#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.218.07:52:19.83#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.218.07:52:19.83#ibcon#enter wrdev, iclass 20, count 0 2006.218.07:52:19.83#ibcon#first serial, iclass 20, count 0 2006.218.07:52:19.83#ibcon#enter sib2, iclass 20, count 0 2006.218.07:52:19.83#ibcon#flushed, iclass 20, count 0 2006.218.07:52:19.83#ibcon#about to write, iclass 20, count 0 2006.218.07:52:19.83#ibcon#wrote, iclass 20, count 0 2006.218.07:52:19.83#ibcon#about to read 3, iclass 20, count 0 2006.218.07:52:19.85#ibcon#read 3, iclass 20, count 0 2006.218.07:52:19.85#ibcon#about to read 4, iclass 20, count 0 2006.218.07:52:19.85#ibcon#read 4, iclass 20, count 0 2006.218.07:52:19.85#ibcon#about to read 5, iclass 20, count 0 2006.218.07:52:19.85#ibcon#read 5, iclass 20, count 0 2006.218.07:52:19.85#ibcon#about to read 6, iclass 20, count 0 2006.218.07:52:19.85#ibcon#read 6, iclass 20, count 0 2006.218.07:52:19.85#ibcon#end of sib2, iclass 20, count 0 2006.218.07:52:19.85#ibcon#*mode == 0, iclass 20, count 0 2006.218.07:52:19.85#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.218.07:52:19.85#ibcon#[27=USB\r\n] 2006.218.07:52:19.85#ibcon#*before write, iclass 20, count 0 2006.218.07:52:19.85#ibcon#enter sib2, iclass 20, count 0 2006.218.07:52:19.85#ibcon#flushed, iclass 20, count 0 2006.218.07:52:19.85#ibcon#about to write, iclass 20, count 0 2006.218.07:52:19.85#ibcon#wrote, iclass 20, count 0 2006.218.07:52:19.85#ibcon#about to read 3, iclass 20, count 0 2006.218.07:52:19.88#ibcon#read 3, iclass 20, count 0 2006.218.07:52:19.88#ibcon#about to read 4, iclass 20, count 0 2006.218.07:52:19.88#ibcon#read 4, iclass 20, count 0 2006.218.07:52:19.88#ibcon#about to read 5, iclass 20, count 0 2006.218.07:52:19.88#ibcon#read 5, iclass 20, count 0 2006.218.07:52:19.88#ibcon#about to read 6, iclass 20, count 0 2006.218.07:52:19.88#ibcon#read 6, iclass 20, count 0 2006.218.07:52:19.88#ibcon#end of sib2, iclass 20, count 0 2006.218.07:52:19.88#ibcon#*after write, iclass 20, count 0 2006.218.07:52:19.88#ibcon#*before return 0, iclass 20, count 0 2006.218.07:52:19.88#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.218.07:52:19.88#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.218.07:52:19.88#ibcon#about to clear, iclass 20 cls_cnt 0 2006.218.07:52:19.88#ibcon#cleared, iclass 20 cls_cnt 0 2006.218.07:52:19.88$vc4f8/vblo=2,640.99 2006.218.07:52:19.88#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.218.07:52:19.88#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.218.07:52:19.88#ibcon#ireg 17 cls_cnt 0 2006.218.07:52:19.88#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.218.07:52:19.88#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.218.07:52:19.88#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.218.07:52:19.88#ibcon#enter wrdev, iclass 22, count 0 2006.218.07:52:19.88#ibcon#first serial, iclass 22, count 0 2006.218.07:52:19.88#ibcon#enter sib2, iclass 22, count 0 2006.218.07:52:19.88#ibcon#flushed, iclass 22, count 0 2006.218.07:52:19.88#ibcon#about to write, iclass 22, count 0 2006.218.07:52:19.88#ibcon#wrote, iclass 22, count 0 2006.218.07:52:19.88#ibcon#about to read 3, iclass 22, count 0 2006.218.07:52:19.90#ibcon#read 3, iclass 22, count 0 2006.218.07:52:19.90#ibcon#about to read 4, iclass 22, count 0 2006.218.07:52:19.90#ibcon#read 4, iclass 22, count 0 2006.218.07:52:19.90#ibcon#about to read 5, iclass 22, count 0 2006.218.07:52:19.90#ibcon#read 5, iclass 22, count 0 2006.218.07:52:19.90#ibcon#about to read 6, iclass 22, count 0 2006.218.07:52:19.90#ibcon#read 6, iclass 22, count 0 2006.218.07:52:19.90#ibcon#end of sib2, iclass 22, count 0 2006.218.07:52:19.90#ibcon#*mode == 0, iclass 22, count 0 2006.218.07:52:19.90#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.218.07:52:19.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.218.07:52:19.90#ibcon#*before write, iclass 22, count 0 2006.218.07:52:19.90#ibcon#enter sib2, iclass 22, count 0 2006.218.07:52:19.90#ibcon#flushed, iclass 22, count 0 2006.218.07:52:19.90#ibcon#about to write, iclass 22, count 0 2006.218.07:52:19.90#ibcon#wrote, iclass 22, count 0 2006.218.07:52:19.90#ibcon#about to read 3, iclass 22, count 0 2006.218.07:52:19.94#ibcon#read 3, iclass 22, count 0 2006.218.07:52:19.94#ibcon#about to read 4, iclass 22, count 0 2006.218.07:52:19.94#ibcon#read 4, iclass 22, count 0 2006.218.07:52:19.94#ibcon#about to read 5, iclass 22, count 0 2006.218.07:52:19.94#ibcon#read 5, iclass 22, count 0 2006.218.07:52:19.94#ibcon#about to read 6, iclass 22, count 0 2006.218.07:52:19.94#ibcon#read 6, iclass 22, count 0 2006.218.07:52:19.94#ibcon#end of sib2, iclass 22, count 0 2006.218.07:52:19.94#ibcon#*after write, iclass 22, count 0 2006.218.07:52:19.94#ibcon#*before return 0, iclass 22, count 0 2006.218.07:52:19.94#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.218.07:52:19.94#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.218.07:52:19.94#ibcon#about to clear, iclass 22 cls_cnt 0 2006.218.07:52:19.94#ibcon#cleared, iclass 22 cls_cnt 0 2006.218.07:52:19.94$vc4f8/vb=2,4 2006.218.07:52:19.94#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.218.07:52:19.94#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.218.07:52:19.94#ibcon#ireg 11 cls_cnt 2 2006.218.07:52:19.94#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.218.07:52:20.00#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.218.07:52:20.00#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.218.07:52:20.00#ibcon#enter wrdev, iclass 24, count 2 2006.218.07:52:20.00#ibcon#first serial, iclass 24, count 2 2006.218.07:52:20.00#ibcon#enter sib2, iclass 24, count 2 2006.218.07:52:20.00#ibcon#flushed, iclass 24, count 2 2006.218.07:52:20.00#ibcon#about to write, iclass 24, count 2 2006.218.07:52:20.00#ibcon#wrote, iclass 24, count 2 2006.218.07:52:20.00#ibcon#about to read 3, iclass 24, count 2 2006.218.07:52:20.02#ibcon#read 3, iclass 24, count 2 2006.218.07:52:20.02#ibcon#about to read 4, iclass 24, count 2 2006.218.07:52:20.02#ibcon#read 4, iclass 24, count 2 2006.218.07:52:20.02#ibcon#about to read 5, iclass 24, count 2 2006.218.07:52:20.02#ibcon#read 5, iclass 24, count 2 2006.218.07:52:20.02#ibcon#about to read 6, iclass 24, count 2 2006.218.07:52:20.02#ibcon#read 6, iclass 24, count 2 2006.218.07:52:20.02#ibcon#end of sib2, iclass 24, count 2 2006.218.07:52:20.02#ibcon#*mode == 0, iclass 24, count 2 2006.218.07:52:20.02#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.218.07:52:20.02#ibcon#[27=AT02-04\r\n] 2006.218.07:52:20.02#ibcon#*before write, iclass 24, count 2 2006.218.07:52:20.02#ibcon#enter sib2, iclass 24, count 2 2006.218.07:52:20.02#ibcon#flushed, iclass 24, count 2 2006.218.07:52:20.02#ibcon#about to write, iclass 24, count 2 2006.218.07:52:20.02#ibcon#wrote, iclass 24, count 2 2006.218.07:52:20.02#ibcon#about to read 3, iclass 24, count 2 2006.218.07:52:20.05#ibcon#read 3, iclass 24, count 2 2006.218.07:52:20.05#ibcon#about to read 4, iclass 24, count 2 2006.218.07:52:20.05#ibcon#read 4, iclass 24, count 2 2006.218.07:52:20.05#ibcon#about to read 5, iclass 24, count 2 2006.218.07:52:20.05#ibcon#read 5, iclass 24, count 2 2006.218.07:52:20.05#ibcon#about to read 6, iclass 24, count 2 2006.218.07:52:20.05#ibcon#read 6, iclass 24, count 2 2006.218.07:52:20.05#ibcon#end of sib2, iclass 24, count 2 2006.218.07:52:20.05#ibcon#*after write, iclass 24, count 2 2006.218.07:52:20.05#ibcon#*before return 0, iclass 24, count 2 2006.218.07:52:20.05#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.218.07:52:20.05#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.218.07:52:20.05#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.218.07:52:20.05#ibcon#ireg 7 cls_cnt 0 2006.218.07:52:20.05#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.218.07:52:20.17#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.218.07:52:20.17#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.218.07:52:20.17#ibcon#enter wrdev, iclass 24, count 0 2006.218.07:52:20.17#ibcon#first serial, iclass 24, count 0 2006.218.07:52:20.17#ibcon#enter sib2, iclass 24, count 0 2006.218.07:52:20.17#ibcon#flushed, iclass 24, count 0 2006.218.07:52:20.17#ibcon#about to write, iclass 24, count 0 2006.218.07:52:20.17#ibcon#wrote, iclass 24, count 0 2006.218.07:52:20.17#ibcon#about to read 3, iclass 24, count 0 2006.218.07:52:20.19#ibcon#read 3, iclass 24, count 0 2006.218.07:52:20.19#ibcon#about to read 4, iclass 24, count 0 2006.218.07:52:20.19#ibcon#read 4, iclass 24, count 0 2006.218.07:52:20.19#ibcon#about to read 5, iclass 24, count 0 2006.218.07:52:20.19#ibcon#read 5, iclass 24, count 0 2006.218.07:52:20.19#ibcon#about to read 6, iclass 24, count 0 2006.218.07:52:20.19#ibcon#read 6, iclass 24, count 0 2006.218.07:52:20.19#ibcon#end of sib2, iclass 24, count 0 2006.218.07:52:20.19#ibcon#*mode == 0, iclass 24, count 0 2006.218.07:52:20.19#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.218.07:52:20.19#ibcon#[27=USB\r\n] 2006.218.07:52:20.19#ibcon#*before write, iclass 24, count 0 2006.218.07:52:20.19#ibcon#enter sib2, iclass 24, count 0 2006.218.07:52:20.19#ibcon#flushed, iclass 24, count 0 2006.218.07:52:20.19#ibcon#about to write, iclass 24, count 0 2006.218.07:52:20.19#ibcon#wrote, iclass 24, count 0 2006.218.07:52:20.19#ibcon#about to read 3, iclass 24, count 0 2006.218.07:52:20.22#ibcon#read 3, iclass 24, count 0 2006.218.07:52:20.22#ibcon#about to read 4, iclass 24, count 0 2006.218.07:52:20.22#ibcon#read 4, iclass 24, count 0 2006.218.07:52:20.22#ibcon#about to read 5, iclass 24, count 0 2006.218.07:52:20.22#ibcon#read 5, iclass 24, count 0 2006.218.07:52:20.22#ibcon#about to read 6, iclass 24, count 0 2006.218.07:52:20.22#ibcon#read 6, iclass 24, count 0 2006.218.07:52:20.22#ibcon#end of sib2, iclass 24, count 0 2006.218.07:52:20.22#ibcon#*after write, iclass 24, count 0 2006.218.07:52:20.22#ibcon#*before return 0, iclass 24, count 0 2006.218.07:52:20.22#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.218.07:52:20.22#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.218.07:52:20.22#ibcon#about to clear, iclass 24 cls_cnt 0 2006.218.07:52:20.22#ibcon#cleared, iclass 24 cls_cnt 0 2006.218.07:52:20.22$vc4f8/vblo=3,656.99 2006.218.07:52:20.22#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.218.07:52:20.22#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.218.07:52:20.22#ibcon#ireg 17 cls_cnt 0 2006.218.07:52:20.22#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.218.07:52:20.22#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.218.07:52:20.22#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.218.07:52:20.22#ibcon#enter wrdev, iclass 26, count 0 2006.218.07:52:20.22#ibcon#first serial, iclass 26, count 0 2006.218.07:52:20.22#ibcon#enter sib2, iclass 26, count 0 2006.218.07:52:20.22#ibcon#flushed, iclass 26, count 0 2006.218.07:52:20.22#ibcon#about to write, iclass 26, count 0 2006.218.07:52:20.22#ibcon#wrote, iclass 26, count 0 2006.218.07:52:20.22#ibcon#about to read 3, iclass 26, count 0 2006.218.07:52:20.24#ibcon#read 3, iclass 26, count 0 2006.218.07:52:20.24#ibcon#about to read 4, iclass 26, count 0 2006.218.07:52:20.24#ibcon#read 4, iclass 26, count 0 2006.218.07:52:20.24#ibcon#about to read 5, iclass 26, count 0 2006.218.07:52:20.24#ibcon#read 5, iclass 26, count 0 2006.218.07:52:20.24#ibcon#about to read 6, iclass 26, count 0 2006.218.07:52:20.24#ibcon#read 6, iclass 26, count 0 2006.218.07:52:20.24#ibcon#end of sib2, iclass 26, count 0 2006.218.07:52:20.24#ibcon#*mode == 0, iclass 26, count 0 2006.218.07:52:20.24#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.218.07:52:20.24#ibcon#[28=FRQ=03,656.99\r\n] 2006.218.07:52:20.24#ibcon#*before write, iclass 26, count 0 2006.218.07:52:20.24#ibcon#enter sib2, iclass 26, count 0 2006.218.07:52:20.24#ibcon#flushed, iclass 26, count 0 2006.218.07:52:20.24#ibcon#about to write, iclass 26, count 0 2006.218.07:52:20.24#ibcon#wrote, iclass 26, count 0 2006.218.07:52:20.24#ibcon#about to read 3, iclass 26, count 0 2006.218.07:52:20.28#ibcon#read 3, iclass 26, count 0 2006.218.07:52:20.28#ibcon#about to read 4, iclass 26, count 0 2006.218.07:52:20.28#ibcon#read 4, iclass 26, count 0 2006.218.07:52:20.28#ibcon#about to read 5, iclass 26, count 0 2006.218.07:52:20.28#ibcon#read 5, iclass 26, count 0 2006.218.07:52:20.28#ibcon#about to read 6, iclass 26, count 0 2006.218.07:52:20.28#ibcon#read 6, iclass 26, count 0 2006.218.07:52:20.28#ibcon#end of sib2, iclass 26, count 0 2006.218.07:52:20.28#ibcon#*after write, iclass 26, count 0 2006.218.07:52:20.28#ibcon#*before return 0, iclass 26, count 0 2006.218.07:52:20.28#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.218.07:52:20.28#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.218.07:52:20.28#ibcon#about to clear, iclass 26 cls_cnt 0 2006.218.07:52:20.28#ibcon#cleared, iclass 26 cls_cnt 0 2006.218.07:52:20.28$vc4f8/vb=3,4 2006.218.07:52:20.28#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.218.07:52:20.28#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.218.07:52:20.28#ibcon#ireg 11 cls_cnt 2 2006.218.07:52:20.28#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.218.07:52:20.34#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.218.07:52:20.34#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.218.07:52:20.34#ibcon#enter wrdev, iclass 28, count 2 2006.218.07:52:20.34#ibcon#first serial, iclass 28, count 2 2006.218.07:52:20.34#ibcon#enter sib2, iclass 28, count 2 2006.218.07:52:20.34#ibcon#flushed, iclass 28, count 2 2006.218.07:52:20.34#ibcon#about to write, iclass 28, count 2 2006.218.07:52:20.34#ibcon#wrote, iclass 28, count 2 2006.218.07:52:20.34#ibcon#about to read 3, iclass 28, count 2 2006.218.07:52:20.36#ibcon#read 3, iclass 28, count 2 2006.218.07:52:20.36#ibcon#about to read 4, iclass 28, count 2 2006.218.07:52:20.36#ibcon#read 4, iclass 28, count 2 2006.218.07:52:20.36#ibcon#about to read 5, iclass 28, count 2 2006.218.07:52:20.36#ibcon#read 5, iclass 28, count 2 2006.218.07:52:20.36#ibcon#about to read 6, iclass 28, count 2 2006.218.07:52:20.36#ibcon#read 6, iclass 28, count 2 2006.218.07:52:20.36#ibcon#end of sib2, iclass 28, count 2 2006.218.07:52:20.36#ibcon#*mode == 0, iclass 28, count 2 2006.218.07:52:20.36#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.218.07:52:20.36#ibcon#[27=AT03-04\r\n] 2006.218.07:52:20.36#ibcon#*before write, iclass 28, count 2 2006.218.07:52:20.36#ibcon#enter sib2, iclass 28, count 2 2006.218.07:52:20.36#ibcon#flushed, iclass 28, count 2 2006.218.07:52:20.36#ibcon#about to write, iclass 28, count 2 2006.218.07:52:20.36#ibcon#wrote, iclass 28, count 2 2006.218.07:52:20.36#ibcon#about to read 3, iclass 28, count 2 2006.218.07:52:20.39#ibcon#read 3, iclass 28, count 2 2006.218.07:52:20.39#ibcon#about to read 4, iclass 28, count 2 2006.218.07:52:20.39#ibcon#read 4, iclass 28, count 2 2006.218.07:52:20.39#ibcon#about to read 5, iclass 28, count 2 2006.218.07:52:20.39#ibcon#read 5, iclass 28, count 2 2006.218.07:52:20.39#ibcon#about to read 6, iclass 28, count 2 2006.218.07:52:20.39#ibcon#read 6, iclass 28, count 2 2006.218.07:52:20.39#ibcon#end of sib2, iclass 28, count 2 2006.218.07:52:20.39#ibcon#*after write, iclass 28, count 2 2006.218.07:52:20.39#ibcon#*before return 0, iclass 28, count 2 2006.218.07:52:20.39#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.218.07:52:20.39#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.218.07:52:20.39#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.218.07:52:20.39#ibcon#ireg 7 cls_cnt 0 2006.218.07:52:20.39#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.218.07:52:20.51#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.218.07:52:20.51#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.218.07:52:20.51#ibcon#enter wrdev, iclass 28, count 0 2006.218.07:52:20.51#ibcon#first serial, iclass 28, count 0 2006.218.07:52:20.51#ibcon#enter sib2, iclass 28, count 0 2006.218.07:52:20.51#ibcon#flushed, iclass 28, count 0 2006.218.07:52:20.51#ibcon#about to write, iclass 28, count 0 2006.218.07:52:20.51#ibcon#wrote, iclass 28, count 0 2006.218.07:52:20.51#ibcon#about to read 3, iclass 28, count 0 2006.218.07:52:20.53#ibcon#read 3, iclass 28, count 0 2006.218.07:52:20.53#ibcon#about to read 4, iclass 28, count 0 2006.218.07:52:20.53#ibcon#read 4, iclass 28, count 0 2006.218.07:52:20.53#ibcon#about to read 5, iclass 28, count 0 2006.218.07:52:20.53#ibcon#read 5, iclass 28, count 0 2006.218.07:52:20.53#ibcon#about to read 6, iclass 28, count 0 2006.218.07:52:20.53#ibcon#read 6, iclass 28, count 0 2006.218.07:52:20.53#ibcon#end of sib2, iclass 28, count 0 2006.218.07:52:20.53#ibcon#*mode == 0, iclass 28, count 0 2006.218.07:52:20.53#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.218.07:52:20.53#ibcon#[27=USB\r\n] 2006.218.07:52:20.53#ibcon#*before write, iclass 28, count 0 2006.218.07:52:20.53#ibcon#enter sib2, iclass 28, count 0 2006.218.07:52:20.53#ibcon#flushed, iclass 28, count 0 2006.218.07:52:20.53#ibcon#about to write, iclass 28, count 0 2006.218.07:52:20.53#ibcon#wrote, iclass 28, count 0 2006.218.07:52:20.53#ibcon#about to read 3, iclass 28, count 0 2006.218.07:52:20.56#ibcon#read 3, iclass 28, count 0 2006.218.07:52:20.56#ibcon#about to read 4, iclass 28, count 0 2006.218.07:52:20.56#ibcon#read 4, iclass 28, count 0 2006.218.07:52:20.56#ibcon#about to read 5, iclass 28, count 0 2006.218.07:52:20.56#ibcon#read 5, iclass 28, count 0 2006.218.07:52:20.56#ibcon#about to read 6, iclass 28, count 0 2006.218.07:52:20.56#ibcon#read 6, iclass 28, count 0 2006.218.07:52:20.56#ibcon#end of sib2, iclass 28, count 0 2006.218.07:52:20.56#ibcon#*after write, iclass 28, count 0 2006.218.07:52:20.56#ibcon#*before return 0, iclass 28, count 0 2006.218.07:52:20.56#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.218.07:52:20.56#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.218.07:52:20.56#ibcon#about to clear, iclass 28 cls_cnt 0 2006.218.07:52:20.56#ibcon#cleared, iclass 28 cls_cnt 0 2006.218.07:52:20.56$vc4f8/vblo=4,712.99 2006.218.07:52:20.56#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.218.07:52:20.56#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.218.07:52:20.56#ibcon#ireg 17 cls_cnt 0 2006.218.07:52:20.56#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.218.07:52:20.56#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.218.07:52:20.56#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.218.07:52:20.56#ibcon#enter wrdev, iclass 30, count 0 2006.218.07:52:20.56#ibcon#first serial, iclass 30, count 0 2006.218.07:52:20.56#ibcon#enter sib2, iclass 30, count 0 2006.218.07:52:20.56#ibcon#flushed, iclass 30, count 0 2006.218.07:52:20.56#ibcon#about to write, iclass 30, count 0 2006.218.07:52:20.56#ibcon#wrote, iclass 30, count 0 2006.218.07:52:20.56#ibcon#about to read 3, iclass 30, count 0 2006.218.07:52:20.58#ibcon#read 3, iclass 30, count 0 2006.218.07:52:20.58#ibcon#about to read 4, iclass 30, count 0 2006.218.07:52:20.58#ibcon#read 4, iclass 30, count 0 2006.218.07:52:20.58#ibcon#about to read 5, iclass 30, count 0 2006.218.07:52:20.58#ibcon#read 5, iclass 30, count 0 2006.218.07:52:20.58#ibcon#about to read 6, iclass 30, count 0 2006.218.07:52:20.58#ibcon#read 6, iclass 30, count 0 2006.218.07:52:20.58#ibcon#end of sib2, iclass 30, count 0 2006.218.07:52:20.58#ibcon#*mode == 0, iclass 30, count 0 2006.218.07:52:20.58#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.218.07:52:20.58#ibcon#[28=FRQ=04,712.99\r\n] 2006.218.07:52:20.58#ibcon#*before write, iclass 30, count 0 2006.218.07:52:20.58#ibcon#enter sib2, iclass 30, count 0 2006.218.07:52:20.58#ibcon#flushed, iclass 30, count 0 2006.218.07:52:20.58#ibcon#about to write, iclass 30, count 0 2006.218.07:52:20.58#ibcon#wrote, iclass 30, count 0 2006.218.07:52:20.58#ibcon#about to read 3, iclass 30, count 0 2006.218.07:52:20.62#ibcon#read 3, iclass 30, count 0 2006.218.07:52:20.62#ibcon#about to read 4, iclass 30, count 0 2006.218.07:52:20.62#ibcon#read 4, iclass 30, count 0 2006.218.07:52:20.62#ibcon#about to read 5, iclass 30, count 0 2006.218.07:52:20.62#ibcon#read 5, iclass 30, count 0 2006.218.07:52:20.62#ibcon#about to read 6, iclass 30, count 0 2006.218.07:52:20.62#ibcon#read 6, iclass 30, count 0 2006.218.07:52:20.62#ibcon#end of sib2, iclass 30, count 0 2006.218.07:52:20.62#ibcon#*after write, iclass 30, count 0 2006.218.07:52:20.62#ibcon#*before return 0, iclass 30, count 0 2006.218.07:52:20.62#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.218.07:52:20.62#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.218.07:52:20.62#ibcon#about to clear, iclass 30 cls_cnt 0 2006.218.07:52:20.62#ibcon#cleared, iclass 30 cls_cnt 0 2006.218.07:52:20.62$vc4f8/vb=4,4 2006.218.07:52:20.62#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.218.07:52:20.62#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.218.07:52:20.62#ibcon#ireg 11 cls_cnt 2 2006.218.07:52:20.62#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.218.07:52:20.68#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.218.07:52:20.68#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.218.07:52:20.68#ibcon#enter wrdev, iclass 32, count 2 2006.218.07:52:20.68#ibcon#first serial, iclass 32, count 2 2006.218.07:52:20.68#ibcon#enter sib2, iclass 32, count 2 2006.218.07:52:20.68#ibcon#flushed, iclass 32, count 2 2006.218.07:52:20.68#ibcon#about to write, iclass 32, count 2 2006.218.07:52:20.68#ibcon#wrote, iclass 32, count 2 2006.218.07:52:20.68#ibcon#about to read 3, iclass 32, count 2 2006.218.07:52:20.70#ibcon#read 3, iclass 32, count 2 2006.218.07:52:20.70#ibcon#about to read 4, iclass 32, count 2 2006.218.07:52:20.70#ibcon#read 4, iclass 32, count 2 2006.218.07:52:20.70#ibcon#about to read 5, iclass 32, count 2 2006.218.07:52:20.70#ibcon#read 5, iclass 32, count 2 2006.218.07:52:20.70#ibcon#about to read 6, iclass 32, count 2 2006.218.07:52:20.70#ibcon#read 6, iclass 32, count 2 2006.218.07:52:20.70#ibcon#end of sib2, iclass 32, count 2 2006.218.07:52:20.70#ibcon#*mode == 0, iclass 32, count 2 2006.218.07:52:20.70#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.218.07:52:20.70#ibcon#[27=AT04-04\r\n] 2006.218.07:52:20.70#ibcon#*before write, iclass 32, count 2 2006.218.07:52:20.70#ibcon#enter sib2, iclass 32, count 2 2006.218.07:52:20.70#ibcon#flushed, iclass 32, count 2 2006.218.07:52:20.70#ibcon#about to write, iclass 32, count 2 2006.218.07:52:20.70#ibcon#wrote, iclass 32, count 2 2006.218.07:52:20.70#ibcon#about to read 3, iclass 32, count 2 2006.218.07:52:20.73#ibcon#read 3, iclass 32, count 2 2006.218.07:52:20.73#ibcon#about to read 4, iclass 32, count 2 2006.218.07:52:20.73#ibcon#read 4, iclass 32, count 2 2006.218.07:52:20.73#ibcon#about to read 5, iclass 32, count 2 2006.218.07:52:20.73#ibcon#read 5, iclass 32, count 2 2006.218.07:52:20.73#ibcon#about to read 6, iclass 32, count 2 2006.218.07:52:20.73#ibcon#read 6, iclass 32, count 2 2006.218.07:52:20.73#ibcon#end of sib2, iclass 32, count 2 2006.218.07:52:20.73#ibcon#*after write, iclass 32, count 2 2006.218.07:52:20.73#ibcon#*before return 0, iclass 32, count 2 2006.218.07:52:20.73#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.218.07:52:20.73#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.218.07:52:20.73#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.218.07:52:20.73#ibcon#ireg 7 cls_cnt 0 2006.218.07:52:20.73#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.218.07:52:20.85#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.218.07:52:20.85#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.218.07:52:20.85#ibcon#enter wrdev, iclass 32, count 0 2006.218.07:52:20.85#ibcon#first serial, iclass 32, count 0 2006.218.07:52:20.85#ibcon#enter sib2, iclass 32, count 0 2006.218.07:52:20.85#ibcon#flushed, iclass 32, count 0 2006.218.07:52:20.85#ibcon#about to write, iclass 32, count 0 2006.218.07:52:20.85#ibcon#wrote, iclass 32, count 0 2006.218.07:52:20.85#ibcon#about to read 3, iclass 32, count 0 2006.218.07:52:20.87#ibcon#read 3, iclass 32, count 0 2006.218.07:52:20.87#ibcon#about to read 4, iclass 32, count 0 2006.218.07:52:20.87#ibcon#read 4, iclass 32, count 0 2006.218.07:52:20.87#ibcon#about to read 5, iclass 32, count 0 2006.218.07:52:20.87#ibcon#read 5, iclass 32, count 0 2006.218.07:52:20.87#ibcon#about to read 6, iclass 32, count 0 2006.218.07:52:20.87#ibcon#read 6, iclass 32, count 0 2006.218.07:52:20.87#ibcon#end of sib2, iclass 32, count 0 2006.218.07:52:20.87#ibcon#*mode == 0, iclass 32, count 0 2006.218.07:52:20.87#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.218.07:52:20.87#ibcon#[27=USB\r\n] 2006.218.07:52:20.87#ibcon#*before write, iclass 32, count 0 2006.218.07:52:20.87#ibcon#enter sib2, iclass 32, count 0 2006.218.07:52:20.87#ibcon#flushed, iclass 32, count 0 2006.218.07:52:20.87#ibcon#about to write, iclass 32, count 0 2006.218.07:52:20.87#ibcon#wrote, iclass 32, count 0 2006.218.07:52:20.87#ibcon#about to read 3, iclass 32, count 0 2006.218.07:52:20.90#ibcon#read 3, iclass 32, count 0 2006.218.07:52:20.90#ibcon#about to read 4, iclass 32, count 0 2006.218.07:52:20.90#ibcon#read 4, iclass 32, count 0 2006.218.07:52:20.90#ibcon#about to read 5, iclass 32, count 0 2006.218.07:52:20.90#ibcon#read 5, iclass 32, count 0 2006.218.07:52:20.90#ibcon#about to read 6, iclass 32, count 0 2006.218.07:52:20.90#ibcon#read 6, iclass 32, count 0 2006.218.07:52:20.90#ibcon#end of sib2, iclass 32, count 0 2006.218.07:52:20.90#ibcon#*after write, iclass 32, count 0 2006.218.07:52:20.90#ibcon#*before return 0, iclass 32, count 0 2006.218.07:52:20.90#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.218.07:52:20.90#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.218.07:52:20.90#ibcon#about to clear, iclass 32 cls_cnt 0 2006.218.07:52:20.90#ibcon#cleared, iclass 32 cls_cnt 0 2006.218.07:52:20.90$vc4f8/vblo=5,744.99 2006.218.07:52:20.90#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.218.07:52:20.90#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.218.07:52:20.90#ibcon#ireg 17 cls_cnt 0 2006.218.07:52:20.90#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.218.07:52:20.90#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.218.07:52:20.90#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.218.07:52:20.90#ibcon#enter wrdev, iclass 34, count 0 2006.218.07:52:20.90#ibcon#first serial, iclass 34, count 0 2006.218.07:52:20.90#ibcon#enter sib2, iclass 34, count 0 2006.218.07:52:20.90#ibcon#flushed, iclass 34, count 0 2006.218.07:52:20.90#ibcon#about to write, iclass 34, count 0 2006.218.07:52:20.90#ibcon#wrote, iclass 34, count 0 2006.218.07:52:20.90#ibcon#about to read 3, iclass 34, count 0 2006.218.07:52:20.92#ibcon#read 3, iclass 34, count 0 2006.218.07:52:20.92#ibcon#about to read 4, iclass 34, count 0 2006.218.07:52:20.92#ibcon#read 4, iclass 34, count 0 2006.218.07:52:20.92#ibcon#about to read 5, iclass 34, count 0 2006.218.07:52:20.92#ibcon#read 5, iclass 34, count 0 2006.218.07:52:20.92#ibcon#about to read 6, iclass 34, count 0 2006.218.07:52:20.92#ibcon#read 6, iclass 34, count 0 2006.218.07:52:20.92#ibcon#end of sib2, iclass 34, count 0 2006.218.07:52:20.92#ibcon#*mode == 0, iclass 34, count 0 2006.218.07:52:20.92#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.218.07:52:20.92#ibcon#[28=FRQ=05,744.99\r\n] 2006.218.07:52:20.92#ibcon#*before write, iclass 34, count 0 2006.218.07:52:20.92#ibcon#enter sib2, iclass 34, count 0 2006.218.07:52:20.92#ibcon#flushed, iclass 34, count 0 2006.218.07:52:20.92#ibcon#about to write, iclass 34, count 0 2006.218.07:52:20.92#ibcon#wrote, iclass 34, count 0 2006.218.07:52:20.92#ibcon#about to read 3, iclass 34, count 0 2006.218.07:52:20.96#ibcon#read 3, iclass 34, count 0 2006.218.07:52:20.96#ibcon#about to read 4, iclass 34, count 0 2006.218.07:52:20.96#ibcon#read 4, iclass 34, count 0 2006.218.07:52:20.96#ibcon#about to read 5, iclass 34, count 0 2006.218.07:52:20.96#ibcon#read 5, iclass 34, count 0 2006.218.07:52:20.96#ibcon#about to read 6, iclass 34, count 0 2006.218.07:52:20.96#ibcon#read 6, iclass 34, count 0 2006.218.07:52:20.96#ibcon#end of sib2, iclass 34, count 0 2006.218.07:52:20.96#ibcon#*after write, iclass 34, count 0 2006.218.07:52:20.96#ibcon#*before return 0, iclass 34, count 0 2006.218.07:52:20.96#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.218.07:52:20.96#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.218.07:52:20.96#ibcon#about to clear, iclass 34 cls_cnt 0 2006.218.07:52:20.96#ibcon#cleared, iclass 34 cls_cnt 0 2006.218.07:52:20.96$vc4f8/vb=5,4 2006.218.07:52:20.96#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.218.07:52:20.96#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.218.07:52:20.96#ibcon#ireg 11 cls_cnt 2 2006.218.07:52:20.96#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.218.07:52:21.03#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.218.07:52:21.03#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.218.07:52:21.03#ibcon#enter wrdev, iclass 36, count 2 2006.218.07:52:21.03#ibcon#first serial, iclass 36, count 2 2006.218.07:52:21.03#ibcon#enter sib2, iclass 36, count 2 2006.218.07:52:21.03#ibcon#flushed, iclass 36, count 2 2006.218.07:52:21.03#ibcon#about to write, iclass 36, count 2 2006.218.07:52:21.03#ibcon#wrote, iclass 36, count 2 2006.218.07:52:21.03#ibcon#about to read 3, iclass 36, count 2 2006.218.07:52:21.04#ibcon#read 3, iclass 36, count 2 2006.218.07:52:21.04#ibcon#about to read 4, iclass 36, count 2 2006.218.07:52:21.04#ibcon#read 4, iclass 36, count 2 2006.218.07:52:21.04#ibcon#about to read 5, iclass 36, count 2 2006.218.07:52:21.04#ibcon#read 5, iclass 36, count 2 2006.218.07:52:21.04#ibcon#about to read 6, iclass 36, count 2 2006.218.07:52:21.04#ibcon#read 6, iclass 36, count 2 2006.218.07:52:21.04#ibcon#end of sib2, iclass 36, count 2 2006.218.07:52:21.04#ibcon#*mode == 0, iclass 36, count 2 2006.218.07:52:21.04#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.218.07:52:21.04#ibcon#[27=AT05-04\r\n] 2006.218.07:52:21.04#ibcon#*before write, iclass 36, count 2 2006.218.07:52:21.04#ibcon#enter sib2, iclass 36, count 2 2006.218.07:52:21.04#ibcon#flushed, iclass 36, count 2 2006.218.07:52:21.04#ibcon#about to write, iclass 36, count 2 2006.218.07:52:21.04#ibcon#wrote, iclass 36, count 2 2006.218.07:52:21.04#ibcon#about to read 3, iclass 36, count 2 2006.218.07:52:21.07#ibcon#read 3, iclass 36, count 2 2006.218.07:52:21.07#ibcon#about to read 4, iclass 36, count 2 2006.218.07:52:21.07#ibcon#read 4, iclass 36, count 2 2006.218.07:52:21.07#ibcon#about to read 5, iclass 36, count 2 2006.218.07:52:21.07#ibcon#read 5, iclass 36, count 2 2006.218.07:52:21.07#ibcon#about to read 6, iclass 36, count 2 2006.218.07:52:21.07#ibcon#read 6, iclass 36, count 2 2006.218.07:52:21.07#ibcon#end of sib2, iclass 36, count 2 2006.218.07:52:21.07#ibcon#*after write, iclass 36, count 2 2006.218.07:52:21.07#ibcon#*before return 0, iclass 36, count 2 2006.218.07:52:21.07#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.218.07:52:21.07#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.218.07:52:21.07#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.218.07:52:21.07#ibcon#ireg 7 cls_cnt 0 2006.218.07:52:21.07#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.218.07:52:21.19#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.218.07:52:21.19#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.218.07:52:21.19#ibcon#enter wrdev, iclass 36, count 0 2006.218.07:52:21.19#ibcon#first serial, iclass 36, count 0 2006.218.07:52:21.19#ibcon#enter sib2, iclass 36, count 0 2006.218.07:52:21.19#ibcon#flushed, iclass 36, count 0 2006.218.07:52:21.19#ibcon#about to write, iclass 36, count 0 2006.218.07:52:21.19#ibcon#wrote, iclass 36, count 0 2006.218.07:52:21.19#ibcon#about to read 3, iclass 36, count 0 2006.218.07:52:21.21#ibcon#read 3, iclass 36, count 0 2006.218.07:52:21.21#ibcon#about to read 4, iclass 36, count 0 2006.218.07:52:21.21#ibcon#read 4, iclass 36, count 0 2006.218.07:52:21.21#ibcon#about to read 5, iclass 36, count 0 2006.218.07:52:21.21#ibcon#read 5, iclass 36, count 0 2006.218.07:52:21.21#ibcon#about to read 6, iclass 36, count 0 2006.218.07:52:21.21#ibcon#read 6, iclass 36, count 0 2006.218.07:52:21.21#ibcon#end of sib2, iclass 36, count 0 2006.218.07:52:21.21#ibcon#*mode == 0, iclass 36, count 0 2006.218.07:52:21.21#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.218.07:52:21.21#ibcon#[27=USB\r\n] 2006.218.07:52:21.21#ibcon#*before write, iclass 36, count 0 2006.218.07:52:21.21#ibcon#enter sib2, iclass 36, count 0 2006.218.07:52:21.21#ibcon#flushed, iclass 36, count 0 2006.218.07:52:21.21#ibcon#about to write, iclass 36, count 0 2006.218.07:52:21.21#ibcon#wrote, iclass 36, count 0 2006.218.07:52:21.21#ibcon#about to read 3, iclass 36, count 0 2006.218.07:52:21.24#ibcon#read 3, iclass 36, count 0 2006.218.07:52:21.24#ibcon#about to read 4, iclass 36, count 0 2006.218.07:52:21.24#ibcon#read 4, iclass 36, count 0 2006.218.07:52:21.24#ibcon#about to read 5, iclass 36, count 0 2006.218.07:52:21.24#ibcon#read 5, iclass 36, count 0 2006.218.07:52:21.24#ibcon#about to read 6, iclass 36, count 0 2006.218.07:52:21.24#ibcon#read 6, iclass 36, count 0 2006.218.07:52:21.24#ibcon#end of sib2, iclass 36, count 0 2006.218.07:52:21.24#ibcon#*after write, iclass 36, count 0 2006.218.07:52:21.24#ibcon#*before return 0, iclass 36, count 0 2006.218.07:52:21.24#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.218.07:52:21.24#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.218.07:52:21.24#ibcon#about to clear, iclass 36 cls_cnt 0 2006.218.07:52:21.24#ibcon#cleared, iclass 36 cls_cnt 0 2006.218.07:52:21.24$vc4f8/vblo=6,752.99 2006.218.07:52:21.24#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.218.07:52:21.24#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.218.07:52:21.24#ibcon#ireg 17 cls_cnt 0 2006.218.07:52:21.24#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.218.07:52:21.24#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.218.07:52:21.24#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.218.07:52:21.24#ibcon#enter wrdev, iclass 38, count 0 2006.218.07:52:21.24#ibcon#first serial, iclass 38, count 0 2006.218.07:52:21.24#ibcon#enter sib2, iclass 38, count 0 2006.218.07:52:21.24#ibcon#flushed, iclass 38, count 0 2006.218.07:52:21.24#ibcon#about to write, iclass 38, count 0 2006.218.07:52:21.24#ibcon#wrote, iclass 38, count 0 2006.218.07:52:21.24#ibcon#about to read 3, iclass 38, count 0 2006.218.07:52:21.26#ibcon#read 3, iclass 38, count 0 2006.218.07:52:21.26#ibcon#about to read 4, iclass 38, count 0 2006.218.07:52:21.26#ibcon#read 4, iclass 38, count 0 2006.218.07:52:21.26#ibcon#about to read 5, iclass 38, count 0 2006.218.07:52:21.26#ibcon#read 5, iclass 38, count 0 2006.218.07:52:21.26#ibcon#about to read 6, iclass 38, count 0 2006.218.07:52:21.26#ibcon#read 6, iclass 38, count 0 2006.218.07:52:21.26#ibcon#end of sib2, iclass 38, count 0 2006.218.07:52:21.26#ibcon#*mode == 0, iclass 38, count 0 2006.218.07:52:21.26#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.218.07:52:21.26#ibcon#[28=FRQ=06,752.99\r\n] 2006.218.07:52:21.26#ibcon#*before write, iclass 38, count 0 2006.218.07:52:21.26#ibcon#enter sib2, iclass 38, count 0 2006.218.07:52:21.26#ibcon#flushed, iclass 38, count 0 2006.218.07:52:21.26#ibcon#about to write, iclass 38, count 0 2006.218.07:52:21.26#ibcon#wrote, iclass 38, count 0 2006.218.07:52:21.26#ibcon#about to read 3, iclass 38, count 0 2006.218.07:52:21.30#ibcon#read 3, iclass 38, count 0 2006.218.07:52:21.30#ibcon#about to read 4, iclass 38, count 0 2006.218.07:52:21.30#ibcon#read 4, iclass 38, count 0 2006.218.07:52:21.30#ibcon#about to read 5, iclass 38, count 0 2006.218.07:52:21.30#ibcon#read 5, iclass 38, count 0 2006.218.07:52:21.30#ibcon#about to read 6, iclass 38, count 0 2006.218.07:52:21.30#ibcon#read 6, iclass 38, count 0 2006.218.07:52:21.30#ibcon#end of sib2, iclass 38, count 0 2006.218.07:52:21.30#ibcon#*after write, iclass 38, count 0 2006.218.07:52:21.30#ibcon#*before return 0, iclass 38, count 0 2006.218.07:52:21.30#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.218.07:52:21.30#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.218.07:52:21.30#ibcon#about to clear, iclass 38 cls_cnt 0 2006.218.07:52:21.30#ibcon#cleared, iclass 38 cls_cnt 0 2006.218.07:52:21.30$vc4f8/vb=6,4 2006.218.07:52:21.30#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.218.07:52:21.30#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.218.07:52:21.30#ibcon#ireg 11 cls_cnt 2 2006.218.07:52:21.30#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.218.07:52:21.36#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.218.07:52:21.36#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.218.07:52:21.36#ibcon#enter wrdev, iclass 40, count 2 2006.218.07:52:21.36#ibcon#first serial, iclass 40, count 2 2006.218.07:52:21.36#ibcon#enter sib2, iclass 40, count 2 2006.218.07:52:21.36#ibcon#flushed, iclass 40, count 2 2006.218.07:52:21.36#ibcon#about to write, iclass 40, count 2 2006.218.07:52:21.36#ibcon#wrote, iclass 40, count 2 2006.218.07:52:21.36#ibcon#about to read 3, iclass 40, count 2 2006.218.07:52:21.38#ibcon#read 3, iclass 40, count 2 2006.218.07:52:21.38#ibcon#about to read 4, iclass 40, count 2 2006.218.07:52:21.38#ibcon#read 4, iclass 40, count 2 2006.218.07:52:21.38#ibcon#about to read 5, iclass 40, count 2 2006.218.07:52:21.38#ibcon#read 5, iclass 40, count 2 2006.218.07:52:21.38#ibcon#about to read 6, iclass 40, count 2 2006.218.07:52:21.38#ibcon#read 6, iclass 40, count 2 2006.218.07:52:21.38#ibcon#end of sib2, iclass 40, count 2 2006.218.07:52:21.38#ibcon#*mode == 0, iclass 40, count 2 2006.218.07:52:21.38#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.218.07:52:21.38#ibcon#[27=AT06-04\r\n] 2006.218.07:52:21.38#ibcon#*before write, iclass 40, count 2 2006.218.07:52:21.38#ibcon#enter sib2, iclass 40, count 2 2006.218.07:52:21.38#ibcon#flushed, iclass 40, count 2 2006.218.07:52:21.38#ibcon#about to write, iclass 40, count 2 2006.218.07:52:21.38#ibcon#wrote, iclass 40, count 2 2006.218.07:52:21.38#ibcon#about to read 3, iclass 40, count 2 2006.218.07:52:21.41#ibcon#read 3, iclass 40, count 2 2006.218.07:52:21.41#ibcon#about to read 4, iclass 40, count 2 2006.218.07:52:21.41#ibcon#read 4, iclass 40, count 2 2006.218.07:52:21.41#ibcon#about to read 5, iclass 40, count 2 2006.218.07:52:21.41#ibcon#read 5, iclass 40, count 2 2006.218.07:52:21.41#ibcon#about to read 6, iclass 40, count 2 2006.218.07:52:21.41#ibcon#read 6, iclass 40, count 2 2006.218.07:52:21.41#ibcon#end of sib2, iclass 40, count 2 2006.218.07:52:21.41#ibcon#*after write, iclass 40, count 2 2006.218.07:52:21.41#ibcon#*before return 0, iclass 40, count 2 2006.218.07:52:21.41#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.218.07:52:21.41#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.218.07:52:21.41#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.218.07:52:21.41#ibcon#ireg 7 cls_cnt 0 2006.218.07:52:21.41#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.218.07:52:21.53#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.218.07:52:21.53#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.218.07:52:21.53#ibcon#enter wrdev, iclass 40, count 0 2006.218.07:52:21.53#ibcon#first serial, iclass 40, count 0 2006.218.07:52:21.53#ibcon#enter sib2, iclass 40, count 0 2006.218.07:52:21.53#ibcon#flushed, iclass 40, count 0 2006.218.07:52:21.53#ibcon#about to write, iclass 40, count 0 2006.218.07:52:21.53#ibcon#wrote, iclass 40, count 0 2006.218.07:52:21.53#ibcon#about to read 3, iclass 40, count 0 2006.218.07:52:21.55#ibcon#read 3, iclass 40, count 0 2006.218.07:52:21.55#ibcon#about to read 4, iclass 40, count 0 2006.218.07:52:21.55#ibcon#read 4, iclass 40, count 0 2006.218.07:52:21.55#ibcon#about to read 5, iclass 40, count 0 2006.218.07:52:21.55#ibcon#read 5, iclass 40, count 0 2006.218.07:52:21.55#ibcon#about to read 6, iclass 40, count 0 2006.218.07:52:21.55#ibcon#read 6, iclass 40, count 0 2006.218.07:52:21.55#ibcon#end of sib2, iclass 40, count 0 2006.218.07:52:21.55#ibcon#*mode == 0, iclass 40, count 0 2006.218.07:52:21.55#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.218.07:52:21.55#ibcon#[27=USB\r\n] 2006.218.07:52:21.55#ibcon#*before write, iclass 40, count 0 2006.218.07:52:21.55#ibcon#enter sib2, iclass 40, count 0 2006.218.07:52:21.55#ibcon#flushed, iclass 40, count 0 2006.218.07:52:21.55#ibcon#about to write, iclass 40, count 0 2006.218.07:52:21.55#ibcon#wrote, iclass 40, count 0 2006.218.07:52:21.55#ibcon#about to read 3, iclass 40, count 0 2006.218.07:52:21.58#ibcon#read 3, iclass 40, count 0 2006.218.07:52:21.58#ibcon#about to read 4, iclass 40, count 0 2006.218.07:52:21.58#ibcon#read 4, iclass 40, count 0 2006.218.07:52:21.58#ibcon#about to read 5, iclass 40, count 0 2006.218.07:52:21.58#ibcon#read 5, iclass 40, count 0 2006.218.07:52:21.58#ibcon#about to read 6, iclass 40, count 0 2006.218.07:52:21.58#ibcon#read 6, iclass 40, count 0 2006.218.07:52:21.58#ibcon#end of sib2, iclass 40, count 0 2006.218.07:52:21.58#ibcon#*after write, iclass 40, count 0 2006.218.07:52:21.58#ibcon#*before return 0, iclass 40, count 0 2006.218.07:52:21.58#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.218.07:52:21.58#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.218.07:52:21.58#ibcon#about to clear, iclass 40 cls_cnt 0 2006.218.07:52:21.58#ibcon#cleared, iclass 40 cls_cnt 0 2006.218.07:52:21.58$vc4f8/vabw=wide 2006.218.07:52:21.58#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.218.07:52:21.58#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.218.07:52:21.58#ibcon#ireg 8 cls_cnt 0 2006.218.07:52:21.58#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.218.07:52:21.58#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.218.07:52:21.58#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.218.07:52:21.58#ibcon#enter wrdev, iclass 4, count 0 2006.218.07:52:21.58#ibcon#first serial, iclass 4, count 0 2006.218.07:52:21.58#ibcon#enter sib2, iclass 4, count 0 2006.218.07:52:21.58#ibcon#flushed, iclass 4, count 0 2006.218.07:52:21.58#ibcon#about to write, iclass 4, count 0 2006.218.07:52:21.58#ibcon#wrote, iclass 4, count 0 2006.218.07:52:21.58#ibcon#about to read 3, iclass 4, count 0 2006.218.07:52:21.60#ibcon#read 3, iclass 4, count 0 2006.218.07:52:21.60#ibcon#about to read 4, iclass 4, count 0 2006.218.07:52:21.60#ibcon#read 4, iclass 4, count 0 2006.218.07:52:21.60#ibcon#about to read 5, iclass 4, count 0 2006.218.07:52:21.60#ibcon#read 5, iclass 4, count 0 2006.218.07:52:21.60#ibcon#about to read 6, iclass 4, count 0 2006.218.07:52:21.60#ibcon#read 6, iclass 4, count 0 2006.218.07:52:21.60#ibcon#end of sib2, iclass 4, count 0 2006.218.07:52:21.60#ibcon#*mode == 0, iclass 4, count 0 2006.218.07:52:21.60#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.218.07:52:21.60#ibcon#[25=BW32\r\n] 2006.218.07:52:21.60#ibcon#*before write, iclass 4, count 0 2006.218.07:52:21.60#ibcon#enter sib2, iclass 4, count 0 2006.218.07:52:21.60#ibcon#flushed, iclass 4, count 0 2006.218.07:52:21.60#ibcon#about to write, iclass 4, count 0 2006.218.07:52:21.60#ibcon#wrote, iclass 4, count 0 2006.218.07:52:21.60#ibcon#about to read 3, iclass 4, count 0 2006.218.07:52:21.63#ibcon#read 3, iclass 4, count 0 2006.218.07:52:21.63#ibcon#about to read 4, iclass 4, count 0 2006.218.07:52:21.63#ibcon#read 4, iclass 4, count 0 2006.218.07:52:21.63#ibcon#about to read 5, iclass 4, count 0 2006.218.07:52:21.63#ibcon#read 5, iclass 4, count 0 2006.218.07:52:21.63#ibcon#about to read 6, iclass 4, count 0 2006.218.07:52:21.63#ibcon#read 6, iclass 4, count 0 2006.218.07:52:21.63#ibcon#end of sib2, iclass 4, count 0 2006.218.07:52:21.63#ibcon#*after write, iclass 4, count 0 2006.218.07:52:21.63#ibcon#*before return 0, iclass 4, count 0 2006.218.07:52:21.63#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.218.07:52:21.63#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.218.07:52:21.63#ibcon#about to clear, iclass 4 cls_cnt 0 2006.218.07:52:21.63#ibcon#cleared, iclass 4 cls_cnt 0 2006.218.07:52:21.63$vc4f8/vbbw=wide 2006.218.07:52:21.63#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.218.07:52:21.63#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.218.07:52:21.63#ibcon#ireg 8 cls_cnt 0 2006.218.07:52:21.63#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.218.07:52:21.70#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.218.07:52:21.70#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.218.07:52:21.70#ibcon#enter wrdev, iclass 6, count 0 2006.218.07:52:21.70#ibcon#first serial, iclass 6, count 0 2006.218.07:52:21.70#ibcon#enter sib2, iclass 6, count 0 2006.218.07:52:21.70#ibcon#flushed, iclass 6, count 0 2006.218.07:52:21.70#ibcon#about to write, iclass 6, count 0 2006.218.07:52:21.70#ibcon#wrote, iclass 6, count 0 2006.218.07:52:21.70#ibcon#about to read 3, iclass 6, count 0 2006.218.07:52:21.72#ibcon#read 3, iclass 6, count 0 2006.218.07:52:21.72#ibcon#about to read 4, iclass 6, count 0 2006.218.07:52:21.72#ibcon#read 4, iclass 6, count 0 2006.218.07:52:21.72#ibcon#about to read 5, iclass 6, count 0 2006.218.07:52:21.72#ibcon#read 5, iclass 6, count 0 2006.218.07:52:21.72#ibcon#about to read 6, iclass 6, count 0 2006.218.07:52:21.72#ibcon#read 6, iclass 6, count 0 2006.218.07:52:21.72#ibcon#end of sib2, iclass 6, count 0 2006.218.07:52:21.72#ibcon#*mode == 0, iclass 6, count 0 2006.218.07:52:21.72#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.218.07:52:21.72#ibcon#[27=BW32\r\n] 2006.218.07:52:21.72#ibcon#*before write, iclass 6, count 0 2006.218.07:52:21.72#ibcon#enter sib2, iclass 6, count 0 2006.218.07:52:21.72#ibcon#flushed, iclass 6, count 0 2006.218.07:52:21.72#ibcon#about to write, iclass 6, count 0 2006.218.07:52:21.72#ibcon#wrote, iclass 6, count 0 2006.218.07:52:21.72#ibcon#about to read 3, iclass 6, count 0 2006.218.07:52:21.75#ibcon#read 3, iclass 6, count 0 2006.218.07:52:21.75#ibcon#about to read 4, iclass 6, count 0 2006.218.07:52:21.75#ibcon#read 4, iclass 6, count 0 2006.218.07:52:21.75#ibcon#about to read 5, iclass 6, count 0 2006.218.07:52:21.75#ibcon#read 5, iclass 6, count 0 2006.218.07:52:21.75#ibcon#about to read 6, iclass 6, count 0 2006.218.07:52:21.75#ibcon#read 6, iclass 6, count 0 2006.218.07:52:21.75#ibcon#end of sib2, iclass 6, count 0 2006.218.07:52:21.75#ibcon#*after write, iclass 6, count 0 2006.218.07:52:21.75#ibcon#*before return 0, iclass 6, count 0 2006.218.07:52:21.75#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.218.07:52:21.75#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.218.07:52:21.75#ibcon#about to clear, iclass 6 cls_cnt 0 2006.218.07:52:21.75#ibcon#cleared, iclass 6 cls_cnt 0 2006.218.07:52:21.75$4f8m12a/ifd4f 2006.218.07:52:21.75$ifd4f/lo= 2006.218.07:52:21.75$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.218.07:52:21.75$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.218.07:52:21.76$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.218.07:52:21.76$ifd4f/patch= 2006.218.07:52:21.76$ifd4f/patch=lo1,a1,a2,a3,a4 2006.218.07:52:21.76$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.218.07:52:21.76$ifd4f/patch=lo3,a5,a6,a7,a8 2006.218.07:52:21.76$4f8m12a/"form=m,16.000,1:2 2006.218.07:52:21.76$4f8m12a/"tpicd 2006.218.07:52:21.76$4f8m12a/echo=off 2006.218.07:52:21.76$4f8m12a/xlog=off 2006.218.07:52:21.76:!2006.218.07:52:50 2006.218.07:52:32.14#trakl#Source acquired 2006.218.07:52:33.14#flagr#flagr/antenna,acquired 2006.218.07:52:50.01:preob 2006.218.07:52:51.14/onsource/TRACKING 2006.218.07:52:51.14:!2006.218.07:53:00 2006.218.07:53:00.00:data_valid=on 2006.218.07:53:00.00:midob 2006.218.07:53:00.14/onsource/TRACKING 2006.218.07:53:00.14/wx/31.14,1007.4,73 2006.218.07:53:00.26/cable/+6.3858E-03 2006.218.07:53:01.35/va/01,05,usb,yes,31,33 2006.218.07:53:01.35/va/02,04,usb,yes,29,31 2006.218.07:53:01.35/va/03,04,usb,yes,27,28 2006.218.07:53:01.35/va/04,04,usb,yes,31,33 2006.218.07:53:01.35/va/05,07,usb,yes,33,35 2006.218.07:53:01.35/va/06,06,usb,yes,32,32 2006.218.07:53:01.35/va/07,06,usb,yes,32,32 2006.218.07:53:01.35/va/08,07,usb,yes,31,30 2006.218.07:53:01.58/valo/01,532.99,yes,locked 2006.218.07:53:01.58/valo/02,572.99,yes,locked 2006.218.07:53:01.58/valo/03,672.99,yes,locked 2006.218.07:53:01.58/valo/04,832.99,yes,locked 2006.218.07:53:01.58/valo/05,652.99,yes,locked 2006.218.07:53:01.58/valo/06,772.99,yes,locked 2006.218.07:53:01.58/valo/07,832.99,yes,locked 2006.218.07:53:01.58/valo/08,852.99,yes,locked 2006.218.07:53:02.67/vb/01,04,usb,yes,30,29 2006.218.07:53:02.67/vb/02,04,usb,yes,32,33 2006.218.07:53:02.67/vb/03,04,usb,yes,28,32 2006.218.07:53:02.67/vb/04,04,usb,yes,29,29 2006.218.07:53:02.67/vb/05,04,usb,yes,27,31 2006.218.07:53:02.67/vb/06,04,usb,yes,28,31 2006.218.07:53:02.67/vb/07,04,usb,yes,31,30 2006.218.07:53:02.67/vb/08,04,usb,yes,28,31 2006.218.07:53:02.90/vblo/01,632.99,yes,locked 2006.218.07:53:02.90/vblo/02,640.99,yes,locked 2006.218.07:53:02.90/vblo/03,656.99,yes,locked 2006.218.07:53:02.90/vblo/04,712.99,yes,locked 2006.218.07:53:02.90/vblo/05,744.99,yes,locked 2006.218.07:53:02.90/vblo/06,752.99,yes,locked 2006.218.07:53:02.90/vblo/07,734.99,yes,locked 2006.218.07:53:02.90/vblo/08,744.99,yes,locked 2006.218.07:53:03.05/vabw/8 2006.218.07:53:03.21/vbbw/8 2006.218.07:53:03.30/xfe/off,on,15.0 2006.218.07:53:03.70/ifatt/23,28,28,28 2006.218.07:53:04.07/fmout-gps/S +4.69E-07 2006.218.07:53:04.15:!2006.218.07:54:00 2006.218.07:54:00.01:data_valid=off 2006.218.07:54:00.02:postob 2006.218.07:54:00.10/cable/+6.3860E-03 2006.218.07:54:00.11/wx/31.12,1007.4,73 2006.218.07:54:01.07/fmout-gps/S +4.69E-07 2006.218.07:54:01.08:scan_name=218-0755,k06218,60 2006.218.07:54:01.08:source=3c418,203837.03,511912.7,2000.0,cw 2006.218.07:54:02.13#flagr#flagr/antenna,new-source 2006.218.07:54:02.14:checkk5 2006.218.07:54:02.51/chk_autoobs//k5ts1/ autoobs is running! 2006.218.07:54:02.88/chk_autoobs//k5ts2/ autoobs is running! 2006.218.07:54:03.26/chk_autoobs//k5ts3/ autoobs is running! 2006.218.07:54:03.63/chk_autoobs//k5ts4/ autoobs is running! 2006.218.07:54:03.99/chk_obsdata//k5ts1/T2180753??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:54:04.37/chk_obsdata//k5ts2/T2180753??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:54:04.74/chk_obsdata//k5ts3/T2180753??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:54:05.10/chk_obsdata//k5ts4/T2180753??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:54:05.80/k5log//k5ts1_log_newline 2006.218.07:54:06.54/k5log//k5ts2_log_newline 2006.218.07:54:07.23/k5log//k5ts3_log_newline 2006.218.07:54:07.93/k5log//k5ts4_log_newline 2006.218.07:54:07.95/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.218.07:54:07.95:4f8m12a=2 2006.218.07:54:07.95$4f8m12a/echo=on 2006.218.07:54:07.95$4f8m12a/pcalon 2006.218.07:54:07.95$pcalon/"no phase cal control is implemented here 2006.218.07:54:07.95$4f8m12a/"tpicd=stop 2006.218.07:54:07.95$4f8m12a/vc4f8 2006.218.07:54:07.95$vc4f8/valo=1,532.99 2006.218.07:54:07.96#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.218.07:54:07.96#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.218.07:54:07.96#ibcon#ireg 17 cls_cnt 0 2006.218.07:54:07.96#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.218.07:54:07.96#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.218.07:54:07.96#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.218.07:54:07.96#ibcon#enter wrdev, iclass 19, count 0 2006.218.07:54:07.96#ibcon#first serial, iclass 19, count 0 2006.218.07:54:07.96#ibcon#enter sib2, iclass 19, count 0 2006.218.07:54:07.96#ibcon#flushed, iclass 19, count 0 2006.218.07:54:07.96#ibcon#about to write, iclass 19, count 0 2006.218.07:54:07.96#ibcon#wrote, iclass 19, count 0 2006.218.07:54:07.96#ibcon#about to read 3, iclass 19, count 0 2006.218.07:54:08.00#ibcon#read 3, iclass 19, count 0 2006.218.07:54:08.00#ibcon#about to read 4, iclass 19, count 0 2006.218.07:54:08.00#ibcon#read 4, iclass 19, count 0 2006.218.07:54:08.00#ibcon#about to read 5, iclass 19, count 0 2006.218.07:54:08.00#ibcon#read 5, iclass 19, count 0 2006.218.07:54:08.00#ibcon#about to read 6, iclass 19, count 0 2006.218.07:54:08.00#ibcon#read 6, iclass 19, count 0 2006.218.07:54:08.00#ibcon#end of sib2, iclass 19, count 0 2006.218.07:54:08.00#ibcon#*mode == 0, iclass 19, count 0 2006.218.07:54:08.00#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.218.07:54:08.00#ibcon#[26=FRQ=01,532.99\r\n] 2006.218.07:54:08.00#ibcon#*before write, iclass 19, count 0 2006.218.07:54:08.00#ibcon#enter sib2, iclass 19, count 0 2006.218.07:54:08.00#ibcon#flushed, iclass 19, count 0 2006.218.07:54:08.00#ibcon#about to write, iclass 19, count 0 2006.218.07:54:08.00#ibcon#wrote, iclass 19, count 0 2006.218.07:54:08.00#ibcon#about to read 3, iclass 19, count 0 2006.218.07:54:08.04#ibcon#read 3, iclass 19, count 0 2006.218.07:54:08.04#ibcon#about to read 4, iclass 19, count 0 2006.218.07:54:08.04#ibcon#read 4, iclass 19, count 0 2006.218.07:54:08.04#ibcon#about to read 5, iclass 19, count 0 2006.218.07:54:08.04#ibcon#read 5, iclass 19, count 0 2006.218.07:54:08.04#ibcon#about to read 6, iclass 19, count 0 2006.218.07:54:08.04#ibcon#read 6, iclass 19, count 0 2006.218.07:54:08.04#ibcon#end of sib2, iclass 19, count 0 2006.218.07:54:08.04#ibcon#*after write, iclass 19, count 0 2006.218.07:54:08.04#ibcon#*before return 0, iclass 19, count 0 2006.218.07:54:08.04#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.218.07:54:08.04#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.218.07:54:08.04#ibcon#about to clear, iclass 19 cls_cnt 0 2006.218.07:54:08.04#ibcon#cleared, iclass 19 cls_cnt 0 2006.218.07:54:08.04$vc4f8/va=1,5 2006.218.07:54:08.04#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.218.07:54:08.04#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.218.07:54:08.04#ibcon#ireg 11 cls_cnt 2 2006.218.07:54:08.04#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.218.07:54:08.04#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.218.07:54:08.04#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.218.07:54:08.04#ibcon#enter wrdev, iclass 21, count 2 2006.218.07:54:08.04#ibcon#first serial, iclass 21, count 2 2006.218.07:54:08.04#ibcon#enter sib2, iclass 21, count 2 2006.218.07:54:08.04#ibcon#flushed, iclass 21, count 2 2006.218.07:54:08.04#ibcon#about to write, iclass 21, count 2 2006.218.07:54:08.04#ibcon#wrote, iclass 21, count 2 2006.218.07:54:08.04#ibcon#about to read 3, iclass 21, count 2 2006.218.07:54:08.06#ibcon#read 3, iclass 21, count 2 2006.218.07:54:08.06#ibcon#about to read 4, iclass 21, count 2 2006.218.07:54:08.06#ibcon#read 4, iclass 21, count 2 2006.218.07:54:08.06#ibcon#about to read 5, iclass 21, count 2 2006.218.07:54:08.06#ibcon#read 5, iclass 21, count 2 2006.218.07:54:08.06#ibcon#about to read 6, iclass 21, count 2 2006.218.07:54:08.06#ibcon#read 6, iclass 21, count 2 2006.218.07:54:08.06#ibcon#end of sib2, iclass 21, count 2 2006.218.07:54:08.06#ibcon#*mode == 0, iclass 21, count 2 2006.218.07:54:08.06#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.218.07:54:08.06#ibcon#[25=AT01-05\r\n] 2006.218.07:54:08.06#ibcon#*before write, iclass 21, count 2 2006.218.07:54:08.06#ibcon#enter sib2, iclass 21, count 2 2006.218.07:54:08.06#ibcon#flushed, iclass 21, count 2 2006.218.07:54:08.06#ibcon#about to write, iclass 21, count 2 2006.218.07:54:08.06#ibcon#wrote, iclass 21, count 2 2006.218.07:54:08.06#ibcon#about to read 3, iclass 21, count 2 2006.218.07:54:08.09#ibcon#read 3, iclass 21, count 2 2006.218.07:54:08.09#ibcon#about to read 4, iclass 21, count 2 2006.218.07:54:08.09#ibcon#read 4, iclass 21, count 2 2006.218.07:54:08.09#ibcon#about to read 5, iclass 21, count 2 2006.218.07:54:08.09#ibcon#read 5, iclass 21, count 2 2006.218.07:54:08.09#ibcon#about to read 6, iclass 21, count 2 2006.218.07:54:08.09#ibcon#read 6, iclass 21, count 2 2006.218.07:54:08.09#ibcon#end of sib2, iclass 21, count 2 2006.218.07:54:08.09#ibcon#*after write, iclass 21, count 2 2006.218.07:54:08.09#ibcon#*before return 0, iclass 21, count 2 2006.218.07:54:08.09#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.218.07:54:08.09#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.218.07:54:08.09#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.218.07:54:08.09#ibcon#ireg 7 cls_cnt 0 2006.218.07:54:08.09#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.218.07:54:08.21#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.218.07:54:08.21#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.218.07:54:08.21#ibcon#enter wrdev, iclass 21, count 0 2006.218.07:54:08.21#ibcon#first serial, iclass 21, count 0 2006.218.07:54:08.21#ibcon#enter sib2, iclass 21, count 0 2006.218.07:54:08.21#ibcon#flushed, iclass 21, count 0 2006.218.07:54:08.21#ibcon#about to write, iclass 21, count 0 2006.218.07:54:08.21#ibcon#wrote, iclass 21, count 0 2006.218.07:54:08.21#ibcon#about to read 3, iclass 21, count 0 2006.218.07:54:08.23#ibcon#read 3, iclass 21, count 0 2006.218.07:54:08.23#ibcon#about to read 4, iclass 21, count 0 2006.218.07:54:08.23#ibcon#read 4, iclass 21, count 0 2006.218.07:54:08.23#ibcon#about to read 5, iclass 21, count 0 2006.218.07:54:08.23#ibcon#read 5, iclass 21, count 0 2006.218.07:54:08.23#ibcon#about to read 6, iclass 21, count 0 2006.218.07:54:08.23#ibcon#read 6, iclass 21, count 0 2006.218.07:54:08.23#ibcon#end of sib2, iclass 21, count 0 2006.218.07:54:08.23#ibcon#*mode == 0, iclass 21, count 0 2006.218.07:54:08.23#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.218.07:54:08.23#ibcon#[25=USB\r\n] 2006.218.07:54:08.23#ibcon#*before write, iclass 21, count 0 2006.218.07:54:08.23#ibcon#enter sib2, iclass 21, count 0 2006.218.07:54:08.23#ibcon#flushed, iclass 21, count 0 2006.218.07:54:08.23#ibcon#about to write, iclass 21, count 0 2006.218.07:54:08.23#ibcon#wrote, iclass 21, count 0 2006.218.07:54:08.23#ibcon#about to read 3, iclass 21, count 0 2006.218.07:54:08.26#ibcon#read 3, iclass 21, count 0 2006.218.07:54:08.26#ibcon#about to read 4, iclass 21, count 0 2006.218.07:54:08.26#ibcon#read 4, iclass 21, count 0 2006.218.07:54:08.26#ibcon#about to read 5, iclass 21, count 0 2006.218.07:54:08.26#ibcon#read 5, iclass 21, count 0 2006.218.07:54:08.26#ibcon#about to read 6, iclass 21, count 0 2006.218.07:54:08.26#ibcon#read 6, iclass 21, count 0 2006.218.07:54:08.26#ibcon#end of sib2, iclass 21, count 0 2006.218.07:54:08.26#ibcon#*after write, iclass 21, count 0 2006.218.07:54:08.26#ibcon#*before return 0, iclass 21, count 0 2006.218.07:54:08.26#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.218.07:54:08.26#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.218.07:54:08.26#ibcon#about to clear, iclass 21 cls_cnt 0 2006.218.07:54:08.26#ibcon#cleared, iclass 21 cls_cnt 0 2006.218.07:54:08.26$vc4f8/valo=2,572.99 2006.218.07:54:08.26#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.218.07:54:08.26#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.218.07:54:08.26#ibcon#ireg 17 cls_cnt 0 2006.218.07:54:08.26#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.218.07:54:08.26#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.218.07:54:08.26#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.218.07:54:08.26#ibcon#enter wrdev, iclass 23, count 0 2006.218.07:54:08.26#ibcon#first serial, iclass 23, count 0 2006.218.07:54:08.26#ibcon#enter sib2, iclass 23, count 0 2006.218.07:54:08.26#ibcon#flushed, iclass 23, count 0 2006.218.07:54:08.26#ibcon#about to write, iclass 23, count 0 2006.218.07:54:08.26#ibcon#wrote, iclass 23, count 0 2006.218.07:54:08.26#ibcon#about to read 3, iclass 23, count 0 2006.218.07:54:08.29#ibcon#read 3, iclass 23, count 0 2006.218.07:54:08.29#ibcon#about to read 4, iclass 23, count 0 2006.218.07:54:08.29#ibcon#read 4, iclass 23, count 0 2006.218.07:54:08.29#ibcon#about to read 5, iclass 23, count 0 2006.218.07:54:08.29#ibcon#read 5, iclass 23, count 0 2006.218.07:54:08.29#ibcon#about to read 6, iclass 23, count 0 2006.218.07:54:08.29#ibcon#read 6, iclass 23, count 0 2006.218.07:54:08.29#ibcon#end of sib2, iclass 23, count 0 2006.218.07:54:08.29#ibcon#*mode == 0, iclass 23, count 0 2006.218.07:54:08.29#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.218.07:54:08.29#ibcon#[26=FRQ=02,572.99\r\n] 2006.218.07:54:08.29#ibcon#*before write, iclass 23, count 0 2006.218.07:54:08.29#ibcon#enter sib2, iclass 23, count 0 2006.218.07:54:08.29#ibcon#flushed, iclass 23, count 0 2006.218.07:54:08.29#ibcon#about to write, iclass 23, count 0 2006.218.07:54:08.29#ibcon#wrote, iclass 23, count 0 2006.218.07:54:08.29#ibcon#about to read 3, iclass 23, count 0 2006.218.07:54:08.33#ibcon#read 3, iclass 23, count 0 2006.218.07:54:08.33#ibcon#about to read 4, iclass 23, count 0 2006.218.07:54:08.33#ibcon#read 4, iclass 23, count 0 2006.218.07:54:08.33#ibcon#about to read 5, iclass 23, count 0 2006.218.07:54:08.33#ibcon#read 5, iclass 23, count 0 2006.218.07:54:08.33#ibcon#about to read 6, iclass 23, count 0 2006.218.07:54:08.33#ibcon#read 6, iclass 23, count 0 2006.218.07:54:08.33#ibcon#end of sib2, iclass 23, count 0 2006.218.07:54:08.33#ibcon#*after write, iclass 23, count 0 2006.218.07:54:08.33#ibcon#*before return 0, iclass 23, count 0 2006.218.07:54:08.33#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.218.07:54:08.33#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.218.07:54:08.33#ibcon#about to clear, iclass 23 cls_cnt 0 2006.218.07:54:08.33#ibcon#cleared, iclass 23 cls_cnt 0 2006.218.07:54:08.33$vc4f8/va=2,4 2006.218.07:54:08.33#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.218.07:54:08.33#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.218.07:54:08.33#ibcon#ireg 11 cls_cnt 2 2006.218.07:54:08.33#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.218.07:54:08.39#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.218.07:54:08.39#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.218.07:54:08.39#ibcon#enter wrdev, iclass 25, count 2 2006.218.07:54:08.39#ibcon#first serial, iclass 25, count 2 2006.218.07:54:08.39#ibcon#enter sib2, iclass 25, count 2 2006.218.07:54:08.39#ibcon#flushed, iclass 25, count 2 2006.218.07:54:08.39#ibcon#about to write, iclass 25, count 2 2006.218.07:54:08.39#ibcon#wrote, iclass 25, count 2 2006.218.07:54:08.39#ibcon#about to read 3, iclass 25, count 2 2006.218.07:54:08.40#ibcon#read 3, iclass 25, count 2 2006.218.07:54:08.40#ibcon#about to read 4, iclass 25, count 2 2006.218.07:54:08.40#ibcon#read 4, iclass 25, count 2 2006.218.07:54:08.40#ibcon#about to read 5, iclass 25, count 2 2006.218.07:54:08.40#ibcon#read 5, iclass 25, count 2 2006.218.07:54:08.40#ibcon#about to read 6, iclass 25, count 2 2006.218.07:54:08.40#ibcon#read 6, iclass 25, count 2 2006.218.07:54:08.40#ibcon#end of sib2, iclass 25, count 2 2006.218.07:54:08.40#ibcon#*mode == 0, iclass 25, count 2 2006.218.07:54:08.40#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.218.07:54:08.40#ibcon#[25=AT02-04\r\n] 2006.218.07:54:08.40#ibcon#*before write, iclass 25, count 2 2006.218.07:54:08.40#ibcon#enter sib2, iclass 25, count 2 2006.218.07:54:08.40#ibcon#flushed, iclass 25, count 2 2006.218.07:54:08.40#ibcon#about to write, iclass 25, count 2 2006.218.07:54:08.40#ibcon#wrote, iclass 25, count 2 2006.218.07:54:08.40#ibcon#about to read 3, iclass 25, count 2 2006.218.07:54:08.43#ibcon#read 3, iclass 25, count 2 2006.218.07:54:08.43#ibcon#about to read 4, iclass 25, count 2 2006.218.07:54:08.43#ibcon#read 4, iclass 25, count 2 2006.218.07:54:08.43#ibcon#about to read 5, iclass 25, count 2 2006.218.07:54:08.43#ibcon#read 5, iclass 25, count 2 2006.218.07:54:08.43#ibcon#about to read 6, iclass 25, count 2 2006.218.07:54:08.43#ibcon#read 6, iclass 25, count 2 2006.218.07:54:08.43#ibcon#end of sib2, iclass 25, count 2 2006.218.07:54:08.43#ibcon#*after write, iclass 25, count 2 2006.218.07:54:08.43#ibcon#*before return 0, iclass 25, count 2 2006.218.07:54:08.43#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.218.07:54:08.43#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.218.07:54:08.43#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.218.07:54:08.43#ibcon#ireg 7 cls_cnt 0 2006.218.07:54:08.43#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.218.07:54:08.55#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.218.07:54:08.55#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.218.07:54:08.55#ibcon#enter wrdev, iclass 25, count 0 2006.218.07:54:08.55#ibcon#first serial, iclass 25, count 0 2006.218.07:54:08.55#ibcon#enter sib2, iclass 25, count 0 2006.218.07:54:08.55#ibcon#flushed, iclass 25, count 0 2006.218.07:54:08.55#ibcon#about to write, iclass 25, count 0 2006.218.07:54:08.55#ibcon#wrote, iclass 25, count 0 2006.218.07:54:08.55#ibcon#about to read 3, iclass 25, count 0 2006.218.07:54:08.57#ibcon#read 3, iclass 25, count 0 2006.218.07:54:08.57#ibcon#about to read 4, iclass 25, count 0 2006.218.07:54:08.57#ibcon#read 4, iclass 25, count 0 2006.218.07:54:08.57#ibcon#about to read 5, iclass 25, count 0 2006.218.07:54:08.57#ibcon#read 5, iclass 25, count 0 2006.218.07:54:08.57#ibcon#about to read 6, iclass 25, count 0 2006.218.07:54:08.57#ibcon#read 6, iclass 25, count 0 2006.218.07:54:08.57#ibcon#end of sib2, iclass 25, count 0 2006.218.07:54:08.57#ibcon#*mode == 0, iclass 25, count 0 2006.218.07:54:08.57#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.218.07:54:08.57#ibcon#[25=USB\r\n] 2006.218.07:54:08.57#ibcon#*before write, iclass 25, count 0 2006.218.07:54:08.57#ibcon#enter sib2, iclass 25, count 0 2006.218.07:54:08.57#ibcon#flushed, iclass 25, count 0 2006.218.07:54:08.57#ibcon#about to write, iclass 25, count 0 2006.218.07:54:08.57#ibcon#wrote, iclass 25, count 0 2006.218.07:54:08.57#ibcon#about to read 3, iclass 25, count 0 2006.218.07:54:08.60#ibcon#read 3, iclass 25, count 0 2006.218.07:54:08.60#ibcon#about to read 4, iclass 25, count 0 2006.218.07:54:08.60#ibcon#read 4, iclass 25, count 0 2006.218.07:54:08.60#ibcon#about to read 5, iclass 25, count 0 2006.218.07:54:08.60#ibcon#read 5, iclass 25, count 0 2006.218.07:54:08.60#ibcon#about to read 6, iclass 25, count 0 2006.218.07:54:08.60#ibcon#read 6, iclass 25, count 0 2006.218.07:54:08.60#ibcon#end of sib2, iclass 25, count 0 2006.218.07:54:08.60#ibcon#*after write, iclass 25, count 0 2006.218.07:54:08.60#ibcon#*before return 0, iclass 25, count 0 2006.218.07:54:08.60#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.218.07:54:08.60#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.218.07:54:08.60#ibcon#about to clear, iclass 25 cls_cnt 0 2006.218.07:54:08.60#ibcon#cleared, iclass 25 cls_cnt 0 2006.218.07:54:08.60$vc4f8/valo=3,672.99 2006.218.07:54:08.60#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.218.07:54:08.60#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.218.07:54:08.60#ibcon#ireg 17 cls_cnt 0 2006.218.07:54:08.60#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.218.07:54:08.60#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.218.07:54:08.60#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.218.07:54:08.60#ibcon#enter wrdev, iclass 27, count 0 2006.218.07:54:08.60#ibcon#first serial, iclass 27, count 0 2006.218.07:54:08.60#ibcon#enter sib2, iclass 27, count 0 2006.218.07:54:08.60#ibcon#flushed, iclass 27, count 0 2006.218.07:54:08.60#ibcon#about to write, iclass 27, count 0 2006.218.07:54:08.60#ibcon#wrote, iclass 27, count 0 2006.218.07:54:08.60#ibcon#about to read 3, iclass 27, count 0 2006.218.07:54:08.63#ibcon#read 3, iclass 27, count 0 2006.218.07:54:08.63#ibcon#about to read 4, iclass 27, count 0 2006.218.07:54:08.63#ibcon#read 4, iclass 27, count 0 2006.218.07:54:08.63#ibcon#about to read 5, iclass 27, count 0 2006.218.07:54:08.63#ibcon#read 5, iclass 27, count 0 2006.218.07:54:08.63#ibcon#about to read 6, iclass 27, count 0 2006.218.07:54:08.63#ibcon#read 6, iclass 27, count 0 2006.218.07:54:08.63#ibcon#end of sib2, iclass 27, count 0 2006.218.07:54:08.63#ibcon#*mode == 0, iclass 27, count 0 2006.218.07:54:08.63#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.218.07:54:08.63#ibcon#[26=FRQ=03,672.99\r\n] 2006.218.07:54:08.63#ibcon#*before write, iclass 27, count 0 2006.218.07:54:08.63#ibcon#enter sib2, iclass 27, count 0 2006.218.07:54:08.63#ibcon#flushed, iclass 27, count 0 2006.218.07:54:08.63#ibcon#about to write, iclass 27, count 0 2006.218.07:54:08.63#ibcon#wrote, iclass 27, count 0 2006.218.07:54:08.63#ibcon#about to read 3, iclass 27, count 0 2006.218.07:54:08.67#ibcon#read 3, iclass 27, count 0 2006.218.07:54:08.67#ibcon#about to read 4, iclass 27, count 0 2006.218.07:54:08.67#ibcon#read 4, iclass 27, count 0 2006.218.07:54:08.67#ibcon#about to read 5, iclass 27, count 0 2006.218.07:54:08.67#ibcon#read 5, iclass 27, count 0 2006.218.07:54:08.67#ibcon#about to read 6, iclass 27, count 0 2006.218.07:54:08.67#ibcon#read 6, iclass 27, count 0 2006.218.07:54:08.67#ibcon#end of sib2, iclass 27, count 0 2006.218.07:54:08.67#ibcon#*after write, iclass 27, count 0 2006.218.07:54:08.67#ibcon#*before return 0, iclass 27, count 0 2006.218.07:54:08.67#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.218.07:54:08.67#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.218.07:54:08.67#ibcon#about to clear, iclass 27 cls_cnt 0 2006.218.07:54:08.67#ibcon#cleared, iclass 27 cls_cnt 0 2006.218.07:54:08.67$vc4f8/va=3,4 2006.218.07:54:08.67#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.218.07:54:08.67#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.218.07:54:08.67#ibcon#ireg 11 cls_cnt 2 2006.218.07:54:08.67#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.218.07:54:08.73#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.218.07:54:08.73#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.218.07:54:08.73#ibcon#enter wrdev, iclass 29, count 2 2006.218.07:54:08.73#ibcon#first serial, iclass 29, count 2 2006.218.07:54:08.73#ibcon#enter sib2, iclass 29, count 2 2006.218.07:54:08.73#ibcon#flushed, iclass 29, count 2 2006.218.07:54:08.73#ibcon#about to write, iclass 29, count 2 2006.218.07:54:08.73#ibcon#wrote, iclass 29, count 2 2006.218.07:54:08.73#ibcon#about to read 3, iclass 29, count 2 2006.218.07:54:08.74#ibcon#read 3, iclass 29, count 2 2006.218.07:54:08.74#ibcon#about to read 4, iclass 29, count 2 2006.218.07:54:08.74#ibcon#read 4, iclass 29, count 2 2006.218.07:54:08.74#ibcon#about to read 5, iclass 29, count 2 2006.218.07:54:08.74#ibcon#read 5, iclass 29, count 2 2006.218.07:54:08.74#ibcon#about to read 6, iclass 29, count 2 2006.218.07:54:08.74#ibcon#read 6, iclass 29, count 2 2006.218.07:54:08.74#ibcon#end of sib2, iclass 29, count 2 2006.218.07:54:08.74#ibcon#*mode == 0, iclass 29, count 2 2006.218.07:54:08.74#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.218.07:54:08.74#ibcon#[25=AT03-04\r\n] 2006.218.07:54:08.74#ibcon#*before write, iclass 29, count 2 2006.218.07:54:08.74#ibcon#enter sib2, iclass 29, count 2 2006.218.07:54:08.74#ibcon#flushed, iclass 29, count 2 2006.218.07:54:08.74#ibcon#about to write, iclass 29, count 2 2006.218.07:54:08.74#ibcon#wrote, iclass 29, count 2 2006.218.07:54:08.74#ibcon#about to read 3, iclass 29, count 2 2006.218.07:54:08.77#ibcon#read 3, iclass 29, count 2 2006.218.07:54:08.77#ibcon#about to read 4, iclass 29, count 2 2006.218.07:54:08.77#ibcon#read 4, iclass 29, count 2 2006.218.07:54:08.77#ibcon#about to read 5, iclass 29, count 2 2006.218.07:54:08.77#ibcon#read 5, iclass 29, count 2 2006.218.07:54:08.77#ibcon#about to read 6, iclass 29, count 2 2006.218.07:54:08.77#ibcon#read 6, iclass 29, count 2 2006.218.07:54:08.77#ibcon#end of sib2, iclass 29, count 2 2006.218.07:54:08.77#ibcon#*after write, iclass 29, count 2 2006.218.07:54:08.77#ibcon#*before return 0, iclass 29, count 2 2006.218.07:54:08.77#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.218.07:54:08.77#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.218.07:54:08.77#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.218.07:54:08.77#ibcon#ireg 7 cls_cnt 0 2006.218.07:54:08.77#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.218.07:54:08.89#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.218.07:54:08.89#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.218.07:54:08.89#ibcon#enter wrdev, iclass 29, count 0 2006.218.07:54:08.89#ibcon#first serial, iclass 29, count 0 2006.218.07:54:08.89#ibcon#enter sib2, iclass 29, count 0 2006.218.07:54:08.89#ibcon#flushed, iclass 29, count 0 2006.218.07:54:08.89#ibcon#about to write, iclass 29, count 0 2006.218.07:54:08.89#ibcon#wrote, iclass 29, count 0 2006.218.07:54:08.89#ibcon#about to read 3, iclass 29, count 0 2006.218.07:54:08.91#ibcon#read 3, iclass 29, count 0 2006.218.07:54:08.91#ibcon#about to read 4, iclass 29, count 0 2006.218.07:54:08.91#ibcon#read 4, iclass 29, count 0 2006.218.07:54:08.91#ibcon#about to read 5, iclass 29, count 0 2006.218.07:54:08.91#ibcon#read 5, iclass 29, count 0 2006.218.07:54:08.91#ibcon#about to read 6, iclass 29, count 0 2006.218.07:54:08.91#ibcon#read 6, iclass 29, count 0 2006.218.07:54:08.91#ibcon#end of sib2, iclass 29, count 0 2006.218.07:54:08.91#ibcon#*mode == 0, iclass 29, count 0 2006.218.07:54:08.91#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.218.07:54:08.91#ibcon#[25=USB\r\n] 2006.218.07:54:08.91#ibcon#*before write, iclass 29, count 0 2006.218.07:54:08.91#ibcon#enter sib2, iclass 29, count 0 2006.218.07:54:08.91#ibcon#flushed, iclass 29, count 0 2006.218.07:54:08.91#ibcon#about to write, iclass 29, count 0 2006.218.07:54:08.91#ibcon#wrote, iclass 29, count 0 2006.218.07:54:08.91#ibcon#about to read 3, iclass 29, count 0 2006.218.07:54:08.94#ibcon#read 3, iclass 29, count 0 2006.218.07:54:08.94#ibcon#about to read 4, iclass 29, count 0 2006.218.07:54:08.94#ibcon#read 4, iclass 29, count 0 2006.218.07:54:08.94#ibcon#about to read 5, iclass 29, count 0 2006.218.07:54:08.94#ibcon#read 5, iclass 29, count 0 2006.218.07:54:08.94#ibcon#about to read 6, iclass 29, count 0 2006.218.07:54:08.94#ibcon#read 6, iclass 29, count 0 2006.218.07:54:08.94#ibcon#end of sib2, iclass 29, count 0 2006.218.07:54:08.94#ibcon#*after write, iclass 29, count 0 2006.218.07:54:08.94#ibcon#*before return 0, iclass 29, count 0 2006.218.07:54:08.94#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.218.07:54:08.94#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.218.07:54:08.94#ibcon#about to clear, iclass 29 cls_cnt 0 2006.218.07:54:08.94#ibcon#cleared, iclass 29 cls_cnt 0 2006.218.07:54:08.94$vc4f8/valo=4,832.99 2006.218.07:54:08.94#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.218.07:54:08.94#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.218.07:54:08.94#ibcon#ireg 17 cls_cnt 0 2006.218.07:54:08.94#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.218.07:54:08.94#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.218.07:54:08.94#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.218.07:54:08.94#ibcon#enter wrdev, iclass 31, count 0 2006.218.07:54:08.94#ibcon#first serial, iclass 31, count 0 2006.218.07:54:08.94#ibcon#enter sib2, iclass 31, count 0 2006.218.07:54:08.94#ibcon#flushed, iclass 31, count 0 2006.218.07:54:08.94#ibcon#about to write, iclass 31, count 0 2006.218.07:54:08.94#ibcon#wrote, iclass 31, count 0 2006.218.07:54:08.94#ibcon#about to read 3, iclass 31, count 0 2006.218.07:54:08.96#ibcon#read 3, iclass 31, count 0 2006.218.07:54:08.96#ibcon#about to read 4, iclass 31, count 0 2006.218.07:54:08.96#ibcon#read 4, iclass 31, count 0 2006.218.07:54:08.96#ibcon#about to read 5, iclass 31, count 0 2006.218.07:54:08.96#ibcon#read 5, iclass 31, count 0 2006.218.07:54:08.96#ibcon#about to read 6, iclass 31, count 0 2006.218.07:54:08.96#ibcon#read 6, iclass 31, count 0 2006.218.07:54:08.96#ibcon#end of sib2, iclass 31, count 0 2006.218.07:54:08.96#ibcon#*mode == 0, iclass 31, count 0 2006.218.07:54:08.96#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.218.07:54:08.96#ibcon#[26=FRQ=04,832.99\r\n] 2006.218.07:54:08.96#ibcon#*before write, iclass 31, count 0 2006.218.07:54:08.96#ibcon#enter sib2, iclass 31, count 0 2006.218.07:54:08.96#ibcon#flushed, iclass 31, count 0 2006.218.07:54:08.96#ibcon#about to write, iclass 31, count 0 2006.218.07:54:08.96#ibcon#wrote, iclass 31, count 0 2006.218.07:54:08.96#ibcon#about to read 3, iclass 31, count 0 2006.218.07:54:09.00#ibcon#read 3, iclass 31, count 0 2006.218.07:54:09.00#ibcon#about to read 4, iclass 31, count 0 2006.218.07:54:09.00#ibcon#read 4, iclass 31, count 0 2006.218.07:54:09.00#ibcon#about to read 5, iclass 31, count 0 2006.218.07:54:09.00#ibcon#read 5, iclass 31, count 0 2006.218.07:54:09.00#ibcon#about to read 6, iclass 31, count 0 2006.218.07:54:09.00#ibcon#read 6, iclass 31, count 0 2006.218.07:54:09.00#ibcon#end of sib2, iclass 31, count 0 2006.218.07:54:09.00#ibcon#*after write, iclass 31, count 0 2006.218.07:54:09.00#ibcon#*before return 0, iclass 31, count 0 2006.218.07:54:09.00#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.218.07:54:09.00#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.218.07:54:09.00#ibcon#about to clear, iclass 31 cls_cnt 0 2006.218.07:54:09.00#ibcon#cleared, iclass 31 cls_cnt 0 2006.218.07:54:09.00$vc4f8/va=4,4 2006.218.07:54:09.00#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.218.07:54:09.00#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.218.07:54:09.00#ibcon#ireg 11 cls_cnt 2 2006.218.07:54:09.00#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.218.07:54:09.06#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.218.07:54:09.06#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.218.07:54:09.06#ibcon#enter wrdev, iclass 33, count 2 2006.218.07:54:09.06#ibcon#first serial, iclass 33, count 2 2006.218.07:54:09.06#ibcon#enter sib2, iclass 33, count 2 2006.218.07:54:09.06#ibcon#flushed, iclass 33, count 2 2006.218.07:54:09.06#ibcon#about to write, iclass 33, count 2 2006.218.07:54:09.06#ibcon#wrote, iclass 33, count 2 2006.218.07:54:09.06#ibcon#about to read 3, iclass 33, count 2 2006.218.07:54:09.08#ibcon#read 3, iclass 33, count 2 2006.218.07:54:09.08#ibcon#about to read 4, iclass 33, count 2 2006.218.07:54:09.08#ibcon#read 4, iclass 33, count 2 2006.218.07:54:09.08#ibcon#about to read 5, iclass 33, count 2 2006.218.07:54:09.08#ibcon#read 5, iclass 33, count 2 2006.218.07:54:09.08#ibcon#about to read 6, iclass 33, count 2 2006.218.07:54:09.08#ibcon#read 6, iclass 33, count 2 2006.218.07:54:09.08#ibcon#end of sib2, iclass 33, count 2 2006.218.07:54:09.08#ibcon#*mode == 0, iclass 33, count 2 2006.218.07:54:09.08#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.218.07:54:09.08#ibcon#[25=AT04-04\r\n] 2006.218.07:54:09.08#ibcon#*before write, iclass 33, count 2 2006.218.07:54:09.08#ibcon#enter sib2, iclass 33, count 2 2006.218.07:54:09.08#ibcon#flushed, iclass 33, count 2 2006.218.07:54:09.08#ibcon#about to write, iclass 33, count 2 2006.218.07:54:09.08#ibcon#wrote, iclass 33, count 2 2006.218.07:54:09.08#ibcon#about to read 3, iclass 33, count 2 2006.218.07:54:09.11#ibcon#read 3, iclass 33, count 2 2006.218.07:54:09.11#ibcon#about to read 4, iclass 33, count 2 2006.218.07:54:09.11#ibcon#read 4, iclass 33, count 2 2006.218.07:54:09.11#ibcon#about to read 5, iclass 33, count 2 2006.218.07:54:09.11#ibcon#read 5, iclass 33, count 2 2006.218.07:54:09.11#ibcon#about to read 6, iclass 33, count 2 2006.218.07:54:09.11#ibcon#read 6, iclass 33, count 2 2006.218.07:54:09.11#ibcon#end of sib2, iclass 33, count 2 2006.218.07:54:09.11#ibcon#*after write, iclass 33, count 2 2006.218.07:54:09.11#ibcon#*before return 0, iclass 33, count 2 2006.218.07:54:09.11#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.218.07:54:09.11#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.218.07:54:09.11#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.218.07:54:09.11#ibcon#ireg 7 cls_cnt 0 2006.218.07:54:09.11#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.218.07:54:09.23#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.218.07:54:09.23#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.218.07:54:09.23#ibcon#enter wrdev, iclass 33, count 0 2006.218.07:54:09.23#ibcon#first serial, iclass 33, count 0 2006.218.07:54:09.23#ibcon#enter sib2, iclass 33, count 0 2006.218.07:54:09.23#ibcon#flushed, iclass 33, count 0 2006.218.07:54:09.23#ibcon#about to write, iclass 33, count 0 2006.218.07:54:09.23#ibcon#wrote, iclass 33, count 0 2006.218.07:54:09.23#ibcon#about to read 3, iclass 33, count 0 2006.218.07:54:09.25#ibcon#read 3, iclass 33, count 0 2006.218.07:54:09.25#ibcon#about to read 4, iclass 33, count 0 2006.218.07:54:09.25#ibcon#read 4, iclass 33, count 0 2006.218.07:54:09.25#ibcon#about to read 5, iclass 33, count 0 2006.218.07:54:09.25#ibcon#read 5, iclass 33, count 0 2006.218.07:54:09.25#ibcon#about to read 6, iclass 33, count 0 2006.218.07:54:09.25#ibcon#read 6, iclass 33, count 0 2006.218.07:54:09.25#ibcon#end of sib2, iclass 33, count 0 2006.218.07:54:09.25#ibcon#*mode == 0, iclass 33, count 0 2006.218.07:54:09.25#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.218.07:54:09.25#ibcon#[25=USB\r\n] 2006.218.07:54:09.25#ibcon#*before write, iclass 33, count 0 2006.218.07:54:09.25#ibcon#enter sib2, iclass 33, count 0 2006.218.07:54:09.25#ibcon#flushed, iclass 33, count 0 2006.218.07:54:09.25#ibcon#about to write, iclass 33, count 0 2006.218.07:54:09.25#ibcon#wrote, iclass 33, count 0 2006.218.07:54:09.25#ibcon#about to read 3, iclass 33, count 0 2006.218.07:54:09.28#ibcon#read 3, iclass 33, count 0 2006.218.07:54:09.28#ibcon#about to read 4, iclass 33, count 0 2006.218.07:54:09.28#ibcon#read 4, iclass 33, count 0 2006.218.07:54:09.28#ibcon#about to read 5, iclass 33, count 0 2006.218.07:54:09.28#ibcon#read 5, iclass 33, count 0 2006.218.07:54:09.28#ibcon#about to read 6, iclass 33, count 0 2006.218.07:54:09.28#ibcon#read 6, iclass 33, count 0 2006.218.07:54:09.28#ibcon#end of sib2, iclass 33, count 0 2006.218.07:54:09.28#ibcon#*after write, iclass 33, count 0 2006.218.07:54:09.28#ibcon#*before return 0, iclass 33, count 0 2006.218.07:54:09.28#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.218.07:54:09.28#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.218.07:54:09.28#ibcon#about to clear, iclass 33 cls_cnt 0 2006.218.07:54:09.28#ibcon#cleared, iclass 33 cls_cnt 0 2006.218.07:54:09.28$vc4f8/valo=5,652.99 2006.218.07:54:09.28#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.218.07:54:09.28#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.218.07:54:09.28#ibcon#ireg 17 cls_cnt 0 2006.218.07:54:09.28#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.218.07:54:09.28#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.218.07:54:09.28#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.218.07:54:09.28#ibcon#enter wrdev, iclass 35, count 0 2006.218.07:54:09.28#ibcon#first serial, iclass 35, count 0 2006.218.07:54:09.28#ibcon#enter sib2, iclass 35, count 0 2006.218.07:54:09.28#ibcon#flushed, iclass 35, count 0 2006.218.07:54:09.28#ibcon#about to write, iclass 35, count 0 2006.218.07:54:09.28#ibcon#wrote, iclass 35, count 0 2006.218.07:54:09.28#ibcon#about to read 3, iclass 35, count 0 2006.218.07:54:09.30#ibcon#read 3, iclass 35, count 0 2006.218.07:54:09.30#ibcon#about to read 4, iclass 35, count 0 2006.218.07:54:09.30#ibcon#read 4, iclass 35, count 0 2006.218.07:54:09.30#ibcon#about to read 5, iclass 35, count 0 2006.218.07:54:09.30#ibcon#read 5, iclass 35, count 0 2006.218.07:54:09.30#ibcon#about to read 6, iclass 35, count 0 2006.218.07:54:09.30#ibcon#read 6, iclass 35, count 0 2006.218.07:54:09.30#ibcon#end of sib2, iclass 35, count 0 2006.218.07:54:09.30#ibcon#*mode == 0, iclass 35, count 0 2006.218.07:54:09.30#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.218.07:54:09.30#ibcon#[26=FRQ=05,652.99\r\n] 2006.218.07:54:09.30#ibcon#*before write, iclass 35, count 0 2006.218.07:54:09.30#ibcon#enter sib2, iclass 35, count 0 2006.218.07:54:09.30#ibcon#flushed, iclass 35, count 0 2006.218.07:54:09.30#ibcon#about to write, iclass 35, count 0 2006.218.07:54:09.30#ibcon#wrote, iclass 35, count 0 2006.218.07:54:09.30#ibcon#about to read 3, iclass 35, count 0 2006.218.07:54:09.34#ibcon#read 3, iclass 35, count 0 2006.218.07:54:09.34#ibcon#about to read 4, iclass 35, count 0 2006.218.07:54:09.34#ibcon#read 4, iclass 35, count 0 2006.218.07:54:09.34#ibcon#about to read 5, iclass 35, count 0 2006.218.07:54:09.34#ibcon#read 5, iclass 35, count 0 2006.218.07:54:09.34#ibcon#about to read 6, iclass 35, count 0 2006.218.07:54:09.34#ibcon#read 6, iclass 35, count 0 2006.218.07:54:09.34#ibcon#end of sib2, iclass 35, count 0 2006.218.07:54:09.34#ibcon#*after write, iclass 35, count 0 2006.218.07:54:09.34#ibcon#*before return 0, iclass 35, count 0 2006.218.07:54:09.34#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.218.07:54:09.34#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.218.07:54:09.34#ibcon#about to clear, iclass 35 cls_cnt 0 2006.218.07:54:09.34#ibcon#cleared, iclass 35 cls_cnt 0 2006.218.07:54:09.34$vc4f8/va=5,7 2006.218.07:54:09.34#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.218.07:54:09.34#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.218.07:54:09.34#ibcon#ireg 11 cls_cnt 2 2006.218.07:54:09.34#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.218.07:54:09.40#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.218.07:54:09.40#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.218.07:54:09.40#ibcon#enter wrdev, iclass 37, count 2 2006.218.07:54:09.40#ibcon#first serial, iclass 37, count 2 2006.218.07:54:09.40#ibcon#enter sib2, iclass 37, count 2 2006.218.07:54:09.40#ibcon#flushed, iclass 37, count 2 2006.218.07:54:09.40#ibcon#about to write, iclass 37, count 2 2006.218.07:54:09.40#ibcon#wrote, iclass 37, count 2 2006.218.07:54:09.40#ibcon#about to read 3, iclass 37, count 2 2006.218.07:54:09.42#ibcon#read 3, iclass 37, count 2 2006.218.07:54:09.42#ibcon#about to read 4, iclass 37, count 2 2006.218.07:54:09.42#ibcon#read 4, iclass 37, count 2 2006.218.07:54:09.42#ibcon#about to read 5, iclass 37, count 2 2006.218.07:54:09.42#ibcon#read 5, iclass 37, count 2 2006.218.07:54:09.42#ibcon#about to read 6, iclass 37, count 2 2006.218.07:54:09.42#ibcon#read 6, iclass 37, count 2 2006.218.07:54:09.42#ibcon#end of sib2, iclass 37, count 2 2006.218.07:54:09.42#ibcon#*mode == 0, iclass 37, count 2 2006.218.07:54:09.42#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.218.07:54:09.42#ibcon#[25=AT05-07\r\n] 2006.218.07:54:09.42#ibcon#*before write, iclass 37, count 2 2006.218.07:54:09.42#ibcon#enter sib2, iclass 37, count 2 2006.218.07:54:09.42#ibcon#flushed, iclass 37, count 2 2006.218.07:54:09.42#ibcon#about to write, iclass 37, count 2 2006.218.07:54:09.42#ibcon#wrote, iclass 37, count 2 2006.218.07:54:09.42#ibcon#about to read 3, iclass 37, count 2 2006.218.07:54:09.45#ibcon#read 3, iclass 37, count 2 2006.218.07:54:09.45#ibcon#about to read 4, iclass 37, count 2 2006.218.07:54:09.45#ibcon#read 4, iclass 37, count 2 2006.218.07:54:09.45#ibcon#about to read 5, iclass 37, count 2 2006.218.07:54:09.45#ibcon#read 5, iclass 37, count 2 2006.218.07:54:09.45#ibcon#about to read 6, iclass 37, count 2 2006.218.07:54:09.45#ibcon#read 6, iclass 37, count 2 2006.218.07:54:09.45#ibcon#end of sib2, iclass 37, count 2 2006.218.07:54:09.45#ibcon#*after write, iclass 37, count 2 2006.218.07:54:09.45#ibcon#*before return 0, iclass 37, count 2 2006.218.07:54:09.45#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.218.07:54:09.45#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.218.07:54:09.45#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.218.07:54:09.45#ibcon#ireg 7 cls_cnt 0 2006.218.07:54:09.45#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.218.07:54:09.57#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.218.07:54:09.57#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.218.07:54:09.57#ibcon#enter wrdev, iclass 37, count 0 2006.218.07:54:09.57#ibcon#first serial, iclass 37, count 0 2006.218.07:54:09.57#ibcon#enter sib2, iclass 37, count 0 2006.218.07:54:09.57#ibcon#flushed, iclass 37, count 0 2006.218.07:54:09.57#ibcon#about to write, iclass 37, count 0 2006.218.07:54:09.57#ibcon#wrote, iclass 37, count 0 2006.218.07:54:09.57#ibcon#about to read 3, iclass 37, count 0 2006.218.07:54:09.59#ibcon#read 3, iclass 37, count 0 2006.218.07:54:09.59#ibcon#about to read 4, iclass 37, count 0 2006.218.07:54:09.59#ibcon#read 4, iclass 37, count 0 2006.218.07:54:09.59#ibcon#about to read 5, iclass 37, count 0 2006.218.07:54:09.59#ibcon#read 5, iclass 37, count 0 2006.218.07:54:09.59#ibcon#about to read 6, iclass 37, count 0 2006.218.07:54:09.59#ibcon#read 6, iclass 37, count 0 2006.218.07:54:09.59#ibcon#end of sib2, iclass 37, count 0 2006.218.07:54:09.59#ibcon#*mode == 0, iclass 37, count 0 2006.218.07:54:09.59#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.218.07:54:09.59#ibcon#[25=USB\r\n] 2006.218.07:54:09.59#ibcon#*before write, iclass 37, count 0 2006.218.07:54:09.59#ibcon#enter sib2, iclass 37, count 0 2006.218.07:54:09.59#ibcon#flushed, iclass 37, count 0 2006.218.07:54:09.59#ibcon#about to write, iclass 37, count 0 2006.218.07:54:09.59#ibcon#wrote, iclass 37, count 0 2006.218.07:54:09.59#ibcon#about to read 3, iclass 37, count 0 2006.218.07:54:09.62#ibcon#read 3, iclass 37, count 0 2006.218.07:54:09.62#ibcon#about to read 4, iclass 37, count 0 2006.218.07:54:09.62#ibcon#read 4, iclass 37, count 0 2006.218.07:54:09.62#ibcon#about to read 5, iclass 37, count 0 2006.218.07:54:09.62#ibcon#read 5, iclass 37, count 0 2006.218.07:54:09.62#ibcon#about to read 6, iclass 37, count 0 2006.218.07:54:09.62#ibcon#read 6, iclass 37, count 0 2006.218.07:54:09.62#ibcon#end of sib2, iclass 37, count 0 2006.218.07:54:09.62#ibcon#*after write, iclass 37, count 0 2006.218.07:54:09.62#ibcon#*before return 0, iclass 37, count 0 2006.218.07:54:09.62#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.218.07:54:09.62#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.218.07:54:09.62#ibcon#about to clear, iclass 37 cls_cnt 0 2006.218.07:54:09.62#ibcon#cleared, iclass 37 cls_cnt 0 2006.218.07:54:09.62$vc4f8/valo=6,772.99 2006.218.07:54:09.62#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.218.07:54:09.62#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.218.07:54:09.62#ibcon#ireg 17 cls_cnt 0 2006.218.07:54:09.62#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.218.07:54:09.62#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.218.07:54:09.62#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.218.07:54:09.62#ibcon#enter wrdev, iclass 39, count 0 2006.218.07:54:09.62#ibcon#first serial, iclass 39, count 0 2006.218.07:54:09.62#ibcon#enter sib2, iclass 39, count 0 2006.218.07:54:09.62#ibcon#flushed, iclass 39, count 0 2006.218.07:54:09.62#ibcon#about to write, iclass 39, count 0 2006.218.07:54:09.62#ibcon#wrote, iclass 39, count 0 2006.218.07:54:09.62#ibcon#about to read 3, iclass 39, count 0 2006.218.07:54:09.65#ibcon#read 3, iclass 39, count 0 2006.218.07:54:09.65#ibcon#about to read 4, iclass 39, count 0 2006.218.07:54:09.65#ibcon#read 4, iclass 39, count 0 2006.218.07:54:09.65#ibcon#about to read 5, iclass 39, count 0 2006.218.07:54:09.65#ibcon#read 5, iclass 39, count 0 2006.218.07:54:09.65#ibcon#about to read 6, iclass 39, count 0 2006.218.07:54:09.65#ibcon#read 6, iclass 39, count 0 2006.218.07:54:09.65#ibcon#end of sib2, iclass 39, count 0 2006.218.07:54:09.65#ibcon#*mode == 0, iclass 39, count 0 2006.218.07:54:09.65#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.218.07:54:09.65#ibcon#[26=FRQ=06,772.99\r\n] 2006.218.07:54:09.65#ibcon#*before write, iclass 39, count 0 2006.218.07:54:09.65#ibcon#enter sib2, iclass 39, count 0 2006.218.07:54:09.65#ibcon#flushed, iclass 39, count 0 2006.218.07:54:09.65#ibcon#about to write, iclass 39, count 0 2006.218.07:54:09.65#ibcon#wrote, iclass 39, count 0 2006.218.07:54:09.65#ibcon#about to read 3, iclass 39, count 0 2006.218.07:54:09.69#ibcon#read 3, iclass 39, count 0 2006.218.07:54:09.69#ibcon#about to read 4, iclass 39, count 0 2006.218.07:54:09.69#ibcon#read 4, iclass 39, count 0 2006.218.07:54:09.69#ibcon#about to read 5, iclass 39, count 0 2006.218.07:54:09.69#ibcon#read 5, iclass 39, count 0 2006.218.07:54:09.69#ibcon#about to read 6, iclass 39, count 0 2006.218.07:54:09.69#ibcon#read 6, iclass 39, count 0 2006.218.07:54:09.69#ibcon#end of sib2, iclass 39, count 0 2006.218.07:54:09.69#ibcon#*after write, iclass 39, count 0 2006.218.07:54:09.69#ibcon#*before return 0, iclass 39, count 0 2006.218.07:54:09.69#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.218.07:54:09.69#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.218.07:54:09.69#ibcon#about to clear, iclass 39 cls_cnt 0 2006.218.07:54:09.69#ibcon#cleared, iclass 39 cls_cnt 0 2006.218.07:54:09.69$vc4f8/va=6,6 2006.218.07:54:09.69#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.218.07:54:09.69#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.218.07:54:09.69#ibcon#ireg 11 cls_cnt 2 2006.218.07:54:09.69#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.218.07:54:09.74#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.218.07:54:09.74#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.218.07:54:09.74#ibcon#enter wrdev, iclass 3, count 2 2006.218.07:54:09.74#ibcon#first serial, iclass 3, count 2 2006.218.07:54:09.74#ibcon#enter sib2, iclass 3, count 2 2006.218.07:54:09.74#ibcon#flushed, iclass 3, count 2 2006.218.07:54:09.74#ibcon#about to write, iclass 3, count 2 2006.218.07:54:09.74#ibcon#wrote, iclass 3, count 2 2006.218.07:54:09.74#ibcon#about to read 3, iclass 3, count 2 2006.218.07:54:09.76#ibcon#read 3, iclass 3, count 2 2006.218.07:54:09.76#ibcon#about to read 4, iclass 3, count 2 2006.218.07:54:09.76#ibcon#read 4, iclass 3, count 2 2006.218.07:54:09.76#ibcon#about to read 5, iclass 3, count 2 2006.218.07:54:09.76#ibcon#read 5, iclass 3, count 2 2006.218.07:54:09.76#ibcon#about to read 6, iclass 3, count 2 2006.218.07:54:09.76#ibcon#read 6, iclass 3, count 2 2006.218.07:54:09.76#ibcon#end of sib2, iclass 3, count 2 2006.218.07:54:09.76#ibcon#*mode == 0, iclass 3, count 2 2006.218.07:54:09.76#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.218.07:54:09.76#ibcon#[25=AT06-06\r\n] 2006.218.07:54:09.76#ibcon#*before write, iclass 3, count 2 2006.218.07:54:09.76#ibcon#enter sib2, iclass 3, count 2 2006.218.07:54:09.76#ibcon#flushed, iclass 3, count 2 2006.218.07:54:09.76#ibcon#about to write, iclass 3, count 2 2006.218.07:54:09.76#ibcon#wrote, iclass 3, count 2 2006.218.07:54:09.76#ibcon#about to read 3, iclass 3, count 2 2006.218.07:54:09.79#ibcon#read 3, iclass 3, count 2 2006.218.07:54:09.79#ibcon#about to read 4, iclass 3, count 2 2006.218.07:54:09.79#ibcon#read 4, iclass 3, count 2 2006.218.07:54:09.79#ibcon#about to read 5, iclass 3, count 2 2006.218.07:54:09.79#ibcon#read 5, iclass 3, count 2 2006.218.07:54:09.79#ibcon#about to read 6, iclass 3, count 2 2006.218.07:54:09.79#ibcon#read 6, iclass 3, count 2 2006.218.07:54:09.79#ibcon#end of sib2, iclass 3, count 2 2006.218.07:54:09.79#ibcon#*after write, iclass 3, count 2 2006.218.07:54:09.79#ibcon#*before return 0, iclass 3, count 2 2006.218.07:54:09.79#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.218.07:54:09.79#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.218.07:54:09.79#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.218.07:54:09.79#ibcon#ireg 7 cls_cnt 0 2006.218.07:54:09.79#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.218.07:54:09.91#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.218.07:54:09.91#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.218.07:54:09.91#ibcon#enter wrdev, iclass 3, count 0 2006.218.07:54:09.91#ibcon#first serial, iclass 3, count 0 2006.218.07:54:09.91#ibcon#enter sib2, iclass 3, count 0 2006.218.07:54:09.91#ibcon#flushed, iclass 3, count 0 2006.218.07:54:09.91#ibcon#about to write, iclass 3, count 0 2006.218.07:54:09.91#ibcon#wrote, iclass 3, count 0 2006.218.07:54:09.91#ibcon#about to read 3, iclass 3, count 0 2006.218.07:54:09.93#ibcon#read 3, iclass 3, count 0 2006.218.07:54:09.93#ibcon#about to read 4, iclass 3, count 0 2006.218.07:54:09.93#ibcon#read 4, iclass 3, count 0 2006.218.07:54:09.93#ibcon#about to read 5, iclass 3, count 0 2006.218.07:54:09.93#ibcon#read 5, iclass 3, count 0 2006.218.07:54:09.93#ibcon#about to read 6, iclass 3, count 0 2006.218.07:54:09.93#ibcon#read 6, iclass 3, count 0 2006.218.07:54:09.93#ibcon#end of sib2, iclass 3, count 0 2006.218.07:54:09.93#ibcon#*mode == 0, iclass 3, count 0 2006.218.07:54:09.93#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.218.07:54:09.93#ibcon#[25=USB\r\n] 2006.218.07:54:09.93#ibcon#*before write, iclass 3, count 0 2006.218.07:54:09.93#ibcon#enter sib2, iclass 3, count 0 2006.218.07:54:09.93#ibcon#flushed, iclass 3, count 0 2006.218.07:54:09.93#ibcon#about to write, iclass 3, count 0 2006.218.07:54:09.93#ibcon#wrote, iclass 3, count 0 2006.218.07:54:09.93#ibcon#about to read 3, iclass 3, count 0 2006.218.07:54:09.96#ibcon#read 3, iclass 3, count 0 2006.218.07:54:09.96#ibcon#about to read 4, iclass 3, count 0 2006.218.07:54:09.96#ibcon#read 4, iclass 3, count 0 2006.218.07:54:09.96#ibcon#about to read 5, iclass 3, count 0 2006.218.07:54:09.96#ibcon#read 5, iclass 3, count 0 2006.218.07:54:09.96#ibcon#about to read 6, iclass 3, count 0 2006.218.07:54:09.96#ibcon#read 6, iclass 3, count 0 2006.218.07:54:09.96#ibcon#end of sib2, iclass 3, count 0 2006.218.07:54:09.96#ibcon#*after write, iclass 3, count 0 2006.218.07:54:09.96#ibcon#*before return 0, iclass 3, count 0 2006.218.07:54:09.96#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.218.07:54:09.96#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.218.07:54:09.96#ibcon#about to clear, iclass 3 cls_cnt 0 2006.218.07:54:09.96#ibcon#cleared, iclass 3 cls_cnt 0 2006.218.07:54:09.96$vc4f8/valo=7,832.99 2006.218.07:54:09.96#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.218.07:54:09.96#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.218.07:54:09.96#ibcon#ireg 17 cls_cnt 0 2006.218.07:54:09.96#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.218.07:54:09.96#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.218.07:54:09.96#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.218.07:54:09.96#ibcon#enter wrdev, iclass 5, count 0 2006.218.07:54:09.96#ibcon#first serial, iclass 5, count 0 2006.218.07:54:09.96#ibcon#enter sib2, iclass 5, count 0 2006.218.07:54:09.96#ibcon#flushed, iclass 5, count 0 2006.218.07:54:09.96#ibcon#about to write, iclass 5, count 0 2006.218.07:54:09.96#ibcon#wrote, iclass 5, count 0 2006.218.07:54:09.96#ibcon#about to read 3, iclass 5, count 0 2006.218.07:54:09.98#ibcon#read 3, iclass 5, count 0 2006.218.07:54:09.98#ibcon#about to read 4, iclass 5, count 0 2006.218.07:54:09.98#ibcon#read 4, iclass 5, count 0 2006.218.07:54:09.98#ibcon#about to read 5, iclass 5, count 0 2006.218.07:54:09.98#ibcon#read 5, iclass 5, count 0 2006.218.07:54:09.98#ibcon#about to read 6, iclass 5, count 0 2006.218.07:54:09.98#ibcon#read 6, iclass 5, count 0 2006.218.07:54:09.98#ibcon#end of sib2, iclass 5, count 0 2006.218.07:54:09.98#ibcon#*mode == 0, iclass 5, count 0 2006.218.07:54:09.98#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.218.07:54:09.98#ibcon#[26=FRQ=07,832.99\r\n] 2006.218.07:54:09.98#ibcon#*before write, iclass 5, count 0 2006.218.07:54:09.98#ibcon#enter sib2, iclass 5, count 0 2006.218.07:54:09.98#ibcon#flushed, iclass 5, count 0 2006.218.07:54:09.98#ibcon#about to write, iclass 5, count 0 2006.218.07:54:09.98#ibcon#wrote, iclass 5, count 0 2006.218.07:54:09.98#ibcon#about to read 3, iclass 5, count 0 2006.218.07:54:10.02#ibcon#read 3, iclass 5, count 0 2006.218.07:54:10.02#ibcon#about to read 4, iclass 5, count 0 2006.218.07:54:10.02#ibcon#read 4, iclass 5, count 0 2006.218.07:54:10.02#ibcon#about to read 5, iclass 5, count 0 2006.218.07:54:10.02#ibcon#read 5, iclass 5, count 0 2006.218.07:54:10.02#ibcon#about to read 6, iclass 5, count 0 2006.218.07:54:10.02#ibcon#read 6, iclass 5, count 0 2006.218.07:54:10.02#ibcon#end of sib2, iclass 5, count 0 2006.218.07:54:10.02#ibcon#*after write, iclass 5, count 0 2006.218.07:54:10.02#ibcon#*before return 0, iclass 5, count 0 2006.218.07:54:10.02#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.218.07:54:10.02#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.218.07:54:10.02#ibcon#about to clear, iclass 5 cls_cnt 0 2006.218.07:54:10.02#ibcon#cleared, iclass 5 cls_cnt 0 2006.218.07:54:10.02$vc4f8/va=7,6 2006.218.07:54:10.02#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.218.07:54:10.02#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.218.07:54:10.02#ibcon#ireg 11 cls_cnt 2 2006.218.07:54:10.02#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.218.07:54:10.08#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.218.07:54:10.08#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.218.07:54:10.08#ibcon#enter wrdev, iclass 7, count 2 2006.218.07:54:10.08#ibcon#first serial, iclass 7, count 2 2006.218.07:54:10.08#ibcon#enter sib2, iclass 7, count 2 2006.218.07:54:10.08#ibcon#flushed, iclass 7, count 2 2006.218.07:54:10.08#ibcon#about to write, iclass 7, count 2 2006.218.07:54:10.08#ibcon#wrote, iclass 7, count 2 2006.218.07:54:10.08#ibcon#about to read 3, iclass 7, count 2 2006.218.07:54:10.10#ibcon#read 3, iclass 7, count 2 2006.218.07:54:10.10#ibcon#about to read 4, iclass 7, count 2 2006.218.07:54:10.10#ibcon#read 4, iclass 7, count 2 2006.218.07:54:10.10#ibcon#about to read 5, iclass 7, count 2 2006.218.07:54:10.10#ibcon#read 5, iclass 7, count 2 2006.218.07:54:10.10#ibcon#about to read 6, iclass 7, count 2 2006.218.07:54:10.10#ibcon#read 6, iclass 7, count 2 2006.218.07:54:10.10#ibcon#end of sib2, iclass 7, count 2 2006.218.07:54:10.10#ibcon#*mode == 0, iclass 7, count 2 2006.218.07:54:10.10#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.218.07:54:10.10#ibcon#[25=AT07-06\r\n] 2006.218.07:54:10.10#ibcon#*before write, iclass 7, count 2 2006.218.07:54:10.10#ibcon#enter sib2, iclass 7, count 2 2006.218.07:54:10.10#ibcon#flushed, iclass 7, count 2 2006.218.07:54:10.10#ibcon#about to write, iclass 7, count 2 2006.218.07:54:10.10#ibcon#wrote, iclass 7, count 2 2006.218.07:54:10.10#ibcon#about to read 3, iclass 7, count 2 2006.218.07:54:10.13#ibcon#read 3, iclass 7, count 2 2006.218.07:54:10.13#ibcon#about to read 4, iclass 7, count 2 2006.218.07:54:10.13#ibcon#read 4, iclass 7, count 2 2006.218.07:54:10.13#ibcon#about to read 5, iclass 7, count 2 2006.218.07:54:10.13#ibcon#read 5, iclass 7, count 2 2006.218.07:54:10.13#ibcon#about to read 6, iclass 7, count 2 2006.218.07:54:10.13#ibcon#read 6, iclass 7, count 2 2006.218.07:54:10.13#ibcon#end of sib2, iclass 7, count 2 2006.218.07:54:10.13#ibcon#*after write, iclass 7, count 2 2006.218.07:54:10.13#ibcon#*before return 0, iclass 7, count 2 2006.218.07:54:10.13#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.218.07:54:10.13#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.218.07:54:10.13#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.218.07:54:10.13#ibcon#ireg 7 cls_cnt 0 2006.218.07:54:10.13#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.218.07:54:10.25#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.218.07:54:10.25#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.218.07:54:10.25#ibcon#enter wrdev, iclass 7, count 0 2006.218.07:54:10.25#ibcon#first serial, iclass 7, count 0 2006.218.07:54:10.25#ibcon#enter sib2, iclass 7, count 0 2006.218.07:54:10.25#ibcon#flushed, iclass 7, count 0 2006.218.07:54:10.25#ibcon#about to write, iclass 7, count 0 2006.218.07:54:10.25#ibcon#wrote, iclass 7, count 0 2006.218.07:54:10.25#ibcon#about to read 3, iclass 7, count 0 2006.218.07:54:10.27#ibcon#read 3, iclass 7, count 0 2006.218.07:54:10.27#ibcon#about to read 4, iclass 7, count 0 2006.218.07:54:10.27#ibcon#read 4, iclass 7, count 0 2006.218.07:54:10.27#ibcon#about to read 5, iclass 7, count 0 2006.218.07:54:10.27#ibcon#read 5, iclass 7, count 0 2006.218.07:54:10.27#ibcon#about to read 6, iclass 7, count 0 2006.218.07:54:10.27#ibcon#read 6, iclass 7, count 0 2006.218.07:54:10.27#ibcon#end of sib2, iclass 7, count 0 2006.218.07:54:10.27#ibcon#*mode == 0, iclass 7, count 0 2006.218.07:54:10.27#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.218.07:54:10.27#ibcon#[25=USB\r\n] 2006.218.07:54:10.27#ibcon#*before write, iclass 7, count 0 2006.218.07:54:10.27#ibcon#enter sib2, iclass 7, count 0 2006.218.07:54:10.27#ibcon#flushed, iclass 7, count 0 2006.218.07:54:10.27#ibcon#about to write, iclass 7, count 0 2006.218.07:54:10.27#ibcon#wrote, iclass 7, count 0 2006.218.07:54:10.27#ibcon#about to read 3, iclass 7, count 0 2006.218.07:54:10.30#ibcon#read 3, iclass 7, count 0 2006.218.07:54:10.30#ibcon#about to read 4, iclass 7, count 0 2006.218.07:54:10.30#ibcon#read 4, iclass 7, count 0 2006.218.07:54:10.30#ibcon#about to read 5, iclass 7, count 0 2006.218.07:54:10.30#ibcon#read 5, iclass 7, count 0 2006.218.07:54:10.30#ibcon#about to read 6, iclass 7, count 0 2006.218.07:54:10.30#ibcon#read 6, iclass 7, count 0 2006.218.07:54:10.30#ibcon#end of sib2, iclass 7, count 0 2006.218.07:54:10.30#ibcon#*after write, iclass 7, count 0 2006.218.07:54:10.30#ibcon#*before return 0, iclass 7, count 0 2006.218.07:54:10.30#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.218.07:54:10.30#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.218.07:54:10.30#ibcon#about to clear, iclass 7 cls_cnt 0 2006.218.07:54:10.30#ibcon#cleared, iclass 7 cls_cnt 0 2006.218.07:54:10.30$vc4f8/valo=8,852.99 2006.218.07:54:10.30#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.218.07:54:10.30#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.218.07:54:10.30#ibcon#ireg 17 cls_cnt 0 2006.218.07:54:10.30#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.218.07:54:10.30#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.218.07:54:10.30#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.218.07:54:10.30#ibcon#enter wrdev, iclass 11, count 0 2006.218.07:54:10.30#ibcon#first serial, iclass 11, count 0 2006.218.07:54:10.30#ibcon#enter sib2, iclass 11, count 0 2006.218.07:54:10.30#ibcon#flushed, iclass 11, count 0 2006.218.07:54:10.30#ibcon#about to write, iclass 11, count 0 2006.218.07:54:10.30#ibcon#wrote, iclass 11, count 0 2006.218.07:54:10.30#ibcon#about to read 3, iclass 11, count 0 2006.218.07:54:10.33#ibcon#read 3, iclass 11, count 0 2006.218.07:54:10.33#ibcon#about to read 4, iclass 11, count 0 2006.218.07:54:10.33#ibcon#read 4, iclass 11, count 0 2006.218.07:54:10.33#ibcon#about to read 5, iclass 11, count 0 2006.218.07:54:10.33#ibcon#read 5, iclass 11, count 0 2006.218.07:54:10.33#ibcon#about to read 6, iclass 11, count 0 2006.218.07:54:10.33#ibcon#read 6, iclass 11, count 0 2006.218.07:54:10.33#ibcon#end of sib2, iclass 11, count 0 2006.218.07:54:10.33#ibcon#*mode == 0, iclass 11, count 0 2006.218.07:54:10.33#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.218.07:54:10.33#ibcon#[26=FRQ=08,852.99\r\n] 2006.218.07:54:10.33#ibcon#*before write, iclass 11, count 0 2006.218.07:54:10.33#ibcon#enter sib2, iclass 11, count 0 2006.218.07:54:10.33#ibcon#flushed, iclass 11, count 0 2006.218.07:54:10.33#ibcon#about to write, iclass 11, count 0 2006.218.07:54:10.33#ibcon#wrote, iclass 11, count 0 2006.218.07:54:10.33#ibcon#about to read 3, iclass 11, count 0 2006.218.07:54:10.37#ibcon#read 3, iclass 11, count 0 2006.218.07:54:10.37#ibcon#about to read 4, iclass 11, count 0 2006.218.07:54:10.37#ibcon#read 4, iclass 11, count 0 2006.218.07:54:10.37#ibcon#about to read 5, iclass 11, count 0 2006.218.07:54:10.37#ibcon#read 5, iclass 11, count 0 2006.218.07:54:10.37#ibcon#about to read 6, iclass 11, count 0 2006.218.07:54:10.37#ibcon#read 6, iclass 11, count 0 2006.218.07:54:10.37#ibcon#end of sib2, iclass 11, count 0 2006.218.07:54:10.37#ibcon#*after write, iclass 11, count 0 2006.218.07:54:10.37#ibcon#*before return 0, iclass 11, count 0 2006.218.07:54:10.37#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.218.07:54:10.37#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.218.07:54:10.37#ibcon#about to clear, iclass 11 cls_cnt 0 2006.218.07:54:10.37#ibcon#cleared, iclass 11 cls_cnt 0 2006.218.07:54:10.37$vc4f8/va=8,7 2006.218.07:54:10.37#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.218.07:54:10.37#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.218.07:54:10.37#ibcon#ireg 11 cls_cnt 2 2006.218.07:54:10.37#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.218.07:54:10.43#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.218.07:54:10.43#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.218.07:54:10.43#ibcon#enter wrdev, iclass 13, count 2 2006.218.07:54:10.43#ibcon#first serial, iclass 13, count 2 2006.218.07:54:10.43#ibcon#enter sib2, iclass 13, count 2 2006.218.07:54:10.43#ibcon#flushed, iclass 13, count 2 2006.218.07:54:10.43#ibcon#about to write, iclass 13, count 2 2006.218.07:54:10.43#ibcon#wrote, iclass 13, count 2 2006.218.07:54:10.43#ibcon#about to read 3, iclass 13, count 2 2006.218.07:54:10.44#ibcon#read 3, iclass 13, count 2 2006.218.07:54:10.44#ibcon#about to read 4, iclass 13, count 2 2006.218.07:54:10.44#ibcon#read 4, iclass 13, count 2 2006.218.07:54:10.44#ibcon#about to read 5, iclass 13, count 2 2006.218.07:54:10.44#ibcon#read 5, iclass 13, count 2 2006.218.07:54:10.44#ibcon#about to read 6, iclass 13, count 2 2006.218.07:54:10.44#ibcon#read 6, iclass 13, count 2 2006.218.07:54:10.44#ibcon#end of sib2, iclass 13, count 2 2006.218.07:54:10.44#ibcon#*mode == 0, iclass 13, count 2 2006.218.07:54:10.44#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.218.07:54:10.44#ibcon#[25=AT08-07\r\n] 2006.218.07:54:10.44#ibcon#*before write, iclass 13, count 2 2006.218.07:54:10.44#ibcon#enter sib2, iclass 13, count 2 2006.218.07:54:10.44#ibcon#flushed, iclass 13, count 2 2006.218.07:54:10.44#ibcon#about to write, iclass 13, count 2 2006.218.07:54:10.44#ibcon#wrote, iclass 13, count 2 2006.218.07:54:10.44#ibcon#about to read 3, iclass 13, count 2 2006.218.07:54:10.47#ibcon#read 3, iclass 13, count 2 2006.218.07:54:10.47#ibcon#about to read 4, iclass 13, count 2 2006.218.07:54:10.47#ibcon#read 4, iclass 13, count 2 2006.218.07:54:10.47#ibcon#about to read 5, iclass 13, count 2 2006.218.07:54:10.47#ibcon#read 5, iclass 13, count 2 2006.218.07:54:10.47#ibcon#about to read 6, iclass 13, count 2 2006.218.07:54:10.47#ibcon#read 6, iclass 13, count 2 2006.218.07:54:10.47#ibcon#end of sib2, iclass 13, count 2 2006.218.07:54:10.47#ibcon#*after write, iclass 13, count 2 2006.218.07:54:10.47#ibcon#*before return 0, iclass 13, count 2 2006.218.07:54:10.47#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.218.07:54:10.47#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.218.07:54:10.47#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.218.07:54:10.47#ibcon#ireg 7 cls_cnt 0 2006.218.07:54:10.47#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.218.07:54:10.59#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.218.07:54:10.59#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.218.07:54:10.59#ibcon#enter wrdev, iclass 13, count 0 2006.218.07:54:10.59#ibcon#first serial, iclass 13, count 0 2006.218.07:54:10.59#ibcon#enter sib2, iclass 13, count 0 2006.218.07:54:10.59#ibcon#flushed, iclass 13, count 0 2006.218.07:54:10.59#ibcon#about to write, iclass 13, count 0 2006.218.07:54:10.59#ibcon#wrote, iclass 13, count 0 2006.218.07:54:10.59#ibcon#about to read 3, iclass 13, count 0 2006.218.07:54:10.61#ibcon#read 3, iclass 13, count 0 2006.218.07:54:10.61#ibcon#about to read 4, iclass 13, count 0 2006.218.07:54:10.61#ibcon#read 4, iclass 13, count 0 2006.218.07:54:10.61#ibcon#about to read 5, iclass 13, count 0 2006.218.07:54:10.61#ibcon#read 5, iclass 13, count 0 2006.218.07:54:10.61#ibcon#about to read 6, iclass 13, count 0 2006.218.07:54:10.61#ibcon#read 6, iclass 13, count 0 2006.218.07:54:10.61#ibcon#end of sib2, iclass 13, count 0 2006.218.07:54:10.61#ibcon#*mode == 0, iclass 13, count 0 2006.218.07:54:10.61#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.218.07:54:10.61#ibcon#[25=USB\r\n] 2006.218.07:54:10.61#ibcon#*before write, iclass 13, count 0 2006.218.07:54:10.61#ibcon#enter sib2, iclass 13, count 0 2006.218.07:54:10.61#ibcon#flushed, iclass 13, count 0 2006.218.07:54:10.61#ibcon#about to write, iclass 13, count 0 2006.218.07:54:10.61#ibcon#wrote, iclass 13, count 0 2006.218.07:54:10.61#ibcon#about to read 3, iclass 13, count 0 2006.218.07:54:10.64#ibcon#read 3, iclass 13, count 0 2006.218.07:54:10.64#ibcon#about to read 4, iclass 13, count 0 2006.218.07:54:10.64#ibcon#read 4, iclass 13, count 0 2006.218.07:54:10.64#ibcon#about to read 5, iclass 13, count 0 2006.218.07:54:10.64#ibcon#read 5, iclass 13, count 0 2006.218.07:54:10.64#ibcon#about to read 6, iclass 13, count 0 2006.218.07:54:10.64#ibcon#read 6, iclass 13, count 0 2006.218.07:54:10.64#ibcon#end of sib2, iclass 13, count 0 2006.218.07:54:10.64#ibcon#*after write, iclass 13, count 0 2006.218.07:54:10.64#ibcon#*before return 0, iclass 13, count 0 2006.218.07:54:10.64#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.218.07:54:10.64#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.218.07:54:10.64#ibcon#about to clear, iclass 13 cls_cnt 0 2006.218.07:54:10.64#ibcon#cleared, iclass 13 cls_cnt 0 2006.218.07:54:10.64$vc4f8/vblo=1,632.99 2006.218.07:54:10.64#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.218.07:54:10.64#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.218.07:54:10.64#ibcon#ireg 17 cls_cnt 0 2006.218.07:54:10.64#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.218.07:54:10.64#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.218.07:54:10.64#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.218.07:54:10.64#ibcon#enter wrdev, iclass 15, count 0 2006.218.07:54:10.64#ibcon#first serial, iclass 15, count 0 2006.218.07:54:10.64#ibcon#enter sib2, iclass 15, count 0 2006.218.07:54:10.64#ibcon#flushed, iclass 15, count 0 2006.218.07:54:10.64#ibcon#about to write, iclass 15, count 0 2006.218.07:54:10.64#ibcon#wrote, iclass 15, count 0 2006.218.07:54:10.64#ibcon#about to read 3, iclass 15, count 0 2006.218.07:54:10.66#ibcon#read 3, iclass 15, count 0 2006.218.07:54:10.66#ibcon#about to read 4, iclass 15, count 0 2006.218.07:54:10.66#ibcon#read 4, iclass 15, count 0 2006.218.07:54:10.66#ibcon#about to read 5, iclass 15, count 0 2006.218.07:54:10.66#ibcon#read 5, iclass 15, count 0 2006.218.07:54:10.66#ibcon#about to read 6, iclass 15, count 0 2006.218.07:54:10.66#ibcon#read 6, iclass 15, count 0 2006.218.07:54:10.66#ibcon#end of sib2, iclass 15, count 0 2006.218.07:54:10.66#ibcon#*mode == 0, iclass 15, count 0 2006.218.07:54:10.66#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.218.07:54:10.66#ibcon#[28=FRQ=01,632.99\r\n] 2006.218.07:54:10.66#ibcon#*before write, iclass 15, count 0 2006.218.07:54:10.66#ibcon#enter sib2, iclass 15, count 0 2006.218.07:54:10.66#ibcon#flushed, iclass 15, count 0 2006.218.07:54:10.66#ibcon#about to write, iclass 15, count 0 2006.218.07:54:10.66#ibcon#wrote, iclass 15, count 0 2006.218.07:54:10.66#ibcon#about to read 3, iclass 15, count 0 2006.218.07:54:10.70#ibcon#read 3, iclass 15, count 0 2006.218.07:54:10.70#ibcon#about to read 4, iclass 15, count 0 2006.218.07:54:10.70#ibcon#read 4, iclass 15, count 0 2006.218.07:54:10.70#ibcon#about to read 5, iclass 15, count 0 2006.218.07:54:10.70#ibcon#read 5, iclass 15, count 0 2006.218.07:54:10.70#ibcon#about to read 6, iclass 15, count 0 2006.218.07:54:10.70#ibcon#read 6, iclass 15, count 0 2006.218.07:54:10.70#ibcon#end of sib2, iclass 15, count 0 2006.218.07:54:10.70#ibcon#*after write, iclass 15, count 0 2006.218.07:54:10.70#ibcon#*before return 0, iclass 15, count 0 2006.218.07:54:10.70#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.218.07:54:10.70#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.218.07:54:10.70#ibcon#about to clear, iclass 15 cls_cnt 0 2006.218.07:54:10.70#ibcon#cleared, iclass 15 cls_cnt 0 2006.218.07:54:10.70$vc4f8/vb=1,4 2006.218.07:54:10.70#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.218.07:54:10.70#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.218.07:54:10.70#ibcon#ireg 11 cls_cnt 2 2006.218.07:54:10.70#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.218.07:54:10.70#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.218.07:54:10.70#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.218.07:54:10.70#ibcon#enter wrdev, iclass 17, count 2 2006.218.07:54:10.70#ibcon#first serial, iclass 17, count 2 2006.218.07:54:10.70#ibcon#enter sib2, iclass 17, count 2 2006.218.07:54:10.70#ibcon#flushed, iclass 17, count 2 2006.218.07:54:10.70#ibcon#about to write, iclass 17, count 2 2006.218.07:54:10.70#ibcon#wrote, iclass 17, count 2 2006.218.07:54:10.70#ibcon#about to read 3, iclass 17, count 2 2006.218.07:54:10.72#ibcon#read 3, iclass 17, count 2 2006.218.07:54:10.72#ibcon#about to read 4, iclass 17, count 2 2006.218.07:54:10.72#ibcon#read 4, iclass 17, count 2 2006.218.07:54:10.72#ibcon#about to read 5, iclass 17, count 2 2006.218.07:54:10.72#ibcon#read 5, iclass 17, count 2 2006.218.07:54:10.72#ibcon#about to read 6, iclass 17, count 2 2006.218.07:54:10.72#ibcon#read 6, iclass 17, count 2 2006.218.07:54:10.72#ibcon#end of sib2, iclass 17, count 2 2006.218.07:54:10.72#ibcon#*mode == 0, iclass 17, count 2 2006.218.07:54:10.72#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.218.07:54:10.72#ibcon#[27=AT01-04\r\n] 2006.218.07:54:10.72#ibcon#*before write, iclass 17, count 2 2006.218.07:54:10.72#ibcon#enter sib2, iclass 17, count 2 2006.218.07:54:10.72#ibcon#flushed, iclass 17, count 2 2006.218.07:54:10.72#ibcon#about to write, iclass 17, count 2 2006.218.07:54:10.72#ibcon#wrote, iclass 17, count 2 2006.218.07:54:10.72#ibcon#about to read 3, iclass 17, count 2 2006.218.07:54:10.75#ibcon#read 3, iclass 17, count 2 2006.218.07:54:10.75#ibcon#about to read 4, iclass 17, count 2 2006.218.07:54:10.75#ibcon#read 4, iclass 17, count 2 2006.218.07:54:10.75#ibcon#about to read 5, iclass 17, count 2 2006.218.07:54:10.75#ibcon#read 5, iclass 17, count 2 2006.218.07:54:10.75#ibcon#about to read 6, iclass 17, count 2 2006.218.07:54:10.75#ibcon#read 6, iclass 17, count 2 2006.218.07:54:10.75#ibcon#end of sib2, iclass 17, count 2 2006.218.07:54:10.75#ibcon#*after write, iclass 17, count 2 2006.218.07:54:10.75#ibcon#*before return 0, iclass 17, count 2 2006.218.07:54:10.75#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.218.07:54:10.75#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.218.07:54:10.75#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.218.07:54:10.75#ibcon#ireg 7 cls_cnt 0 2006.218.07:54:10.75#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.218.07:54:10.87#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.218.07:54:10.87#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.218.07:54:10.87#ibcon#enter wrdev, iclass 17, count 0 2006.218.07:54:10.87#ibcon#first serial, iclass 17, count 0 2006.218.07:54:10.87#ibcon#enter sib2, iclass 17, count 0 2006.218.07:54:10.87#ibcon#flushed, iclass 17, count 0 2006.218.07:54:10.87#ibcon#about to write, iclass 17, count 0 2006.218.07:54:10.87#ibcon#wrote, iclass 17, count 0 2006.218.07:54:10.87#ibcon#about to read 3, iclass 17, count 0 2006.218.07:54:10.89#ibcon#read 3, iclass 17, count 0 2006.218.07:54:10.89#ibcon#about to read 4, iclass 17, count 0 2006.218.07:54:10.89#ibcon#read 4, iclass 17, count 0 2006.218.07:54:10.89#ibcon#about to read 5, iclass 17, count 0 2006.218.07:54:10.89#ibcon#read 5, iclass 17, count 0 2006.218.07:54:10.89#ibcon#about to read 6, iclass 17, count 0 2006.218.07:54:10.89#ibcon#read 6, iclass 17, count 0 2006.218.07:54:10.89#ibcon#end of sib2, iclass 17, count 0 2006.218.07:54:10.89#ibcon#*mode == 0, iclass 17, count 0 2006.218.07:54:10.89#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.218.07:54:10.89#ibcon#[27=USB\r\n] 2006.218.07:54:10.89#ibcon#*before write, iclass 17, count 0 2006.218.07:54:10.89#ibcon#enter sib2, iclass 17, count 0 2006.218.07:54:10.89#ibcon#flushed, iclass 17, count 0 2006.218.07:54:10.89#ibcon#about to write, iclass 17, count 0 2006.218.07:54:10.89#ibcon#wrote, iclass 17, count 0 2006.218.07:54:10.89#ibcon#about to read 3, iclass 17, count 0 2006.218.07:54:10.92#ibcon#read 3, iclass 17, count 0 2006.218.07:54:10.92#ibcon#about to read 4, iclass 17, count 0 2006.218.07:54:10.92#ibcon#read 4, iclass 17, count 0 2006.218.07:54:10.92#ibcon#about to read 5, iclass 17, count 0 2006.218.07:54:10.92#ibcon#read 5, iclass 17, count 0 2006.218.07:54:10.92#ibcon#about to read 6, iclass 17, count 0 2006.218.07:54:10.92#ibcon#read 6, iclass 17, count 0 2006.218.07:54:10.92#ibcon#end of sib2, iclass 17, count 0 2006.218.07:54:10.92#ibcon#*after write, iclass 17, count 0 2006.218.07:54:10.92#ibcon#*before return 0, iclass 17, count 0 2006.218.07:54:10.92#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.218.07:54:10.92#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.218.07:54:10.92#ibcon#about to clear, iclass 17 cls_cnt 0 2006.218.07:54:10.92#ibcon#cleared, iclass 17 cls_cnt 0 2006.218.07:54:10.92$vc4f8/vblo=2,640.99 2006.218.07:54:10.92#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.218.07:54:10.92#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.218.07:54:10.92#ibcon#ireg 17 cls_cnt 0 2006.218.07:54:10.92#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.218.07:54:10.92#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.218.07:54:10.92#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.218.07:54:10.92#ibcon#enter wrdev, iclass 19, count 0 2006.218.07:54:10.92#ibcon#first serial, iclass 19, count 0 2006.218.07:54:10.92#ibcon#enter sib2, iclass 19, count 0 2006.218.07:54:10.92#ibcon#flushed, iclass 19, count 0 2006.218.07:54:10.92#ibcon#about to write, iclass 19, count 0 2006.218.07:54:10.92#ibcon#wrote, iclass 19, count 0 2006.218.07:54:10.92#ibcon#about to read 3, iclass 19, count 0 2006.218.07:54:10.94#ibcon#read 3, iclass 19, count 0 2006.218.07:54:10.94#ibcon#about to read 4, iclass 19, count 0 2006.218.07:54:10.94#ibcon#read 4, iclass 19, count 0 2006.218.07:54:10.94#ibcon#about to read 5, iclass 19, count 0 2006.218.07:54:10.94#ibcon#read 5, iclass 19, count 0 2006.218.07:54:10.94#ibcon#about to read 6, iclass 19, count 0 2006.218.07:54:10.94#ibcon#read 6, iclass 19, count 0 2006.218.07:54:10.94#ibcon#end of sib2, iclass 19, count 0 2006.218.07:54:10.94#ibcon#*mode == 0, iclass 19, count 0 2006.218.07:54:10.94#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.218.07:54:10.94#ibcon#[28=FRQ=02,640.99\r\n] 2006.218.07:54:10.94#ibcon#*before write, iclass 19, count 0 2006.218.07:54:10.94#ibcon#enter sib2, iclass 19, count 0 2006.218.07:54:10.94#ibcon#flushed, iclass 19, count 0 2006.218.07:54:10.94#ibcon#about to write, iclass 19, count 0 2006.218.07:54:10.94#ibcon#wrote, iclass 19, count 0 2006.218.07:54:10.94#ibcon#about to read 3, iclass 19, count 0 2006.218.07:54:10.98#ibcon#read 3, iclass 19, count 0 2006.218.07:54:10.98#ibcon#about to read 4, iclass 19, count 0 2006.218.07:54:10.98#ibcon#read 4, iclass 19, count 0 2006.218.07:54:10.98#ibcon#about to read 5, iclass 19, count 0 2006.218.07:54:10.98#ibcon#read 5, iclass 19, count 0 2006.218.07:54:10.98#ibcon#about to read 6, iclass 19, count 0 2006.218.07:54:10.98#ibcon#read 6, iclass 19, count 0 2006.218.07:54:10.98#ibcon#end of sib2, iclass 19, count 0 2006.218.07:54:10.98#ibcon#*after write, iclass 19, count 0 2006.218.07:54:10.98#ibcon#*before return 0, iclass 19, count 0 2006.218.07:54:10.98#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.218.07:54:10.98#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.218.07:54:10.98#ibcon#about to clear, iclass 19 cls_cnt 0 2006.218.07:54:10.98#ibcon#cleared, iclass 19 cls_cnt 0 2006.218.07:54:10.98$vc4f8/vb=2,4 2006.218.07:54:10.98#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.218.07:54:10.98#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.218.07:54:10.98#ibcon#ireg 11 cls_cnt 2 2006.218.07:54:10.98#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.218.07:54:11.04#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.218.07:54:11.04#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.218.07:54:11.04#ibcon#enter wrdev, iclass 21, count 2 2006.218.07:54:11.04#ibcon#first serial, iclass 21, count 2 2006.218.07:54:11.04#ibcon#enter sib2, iclass 21, count 2 2006.218.07:54:11.04#ibcon#flushed, iclass 21, count 2 2006.218.07:54:11.04#ibcon#about to write, iclass 21, count 2 2006.218.07:54:11.04#ibcon#wrote, iclass 21, count 2 2006.218.07:54:11.04#ibcon#about to read 3, iclass 21, count 2 2006.218.07:54:11.06#ibcon#read 3, iclass 21, count 2 2006.218.07:54:11.06#ibcon#about to read 4, iclass 21, count 2 2006.218.07:54:11.06#ibcon#read 4, iclass 21, count 2 2006.218.07:54:11.06#ibcon#about to read 5, iclass 21, count 2 2006.218.07:54:11.06#ibcon#read 5, iclass 21, count 2 2006.218.07:54:11.06#ibcon#about to read 6, iclass 21, count 2 2006.218.07:54:11.06#ibcon#read 6, iclass 21, count 2 2006.218.07:54:11.06#ibcon#end of sib2, iclass 21, count 2 2006.218.07:54:11.06#ibcon#*mode == 0, iclass 21, count 2 2006.218.07:54:11.06#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.218.07:54:11.06#ibcon#[27=AT02-04\r\n] 2006.218.07:54:11.06#ibcon#*before write, iclass 21, count 2 2006.218.07:54:11.06#ibcon#enter sib2, iclass 21, count 2 2006.218.07:54:11.06#ibcon#flushed, iclass 21, count 2 2006.218.07:54:11.06#ibcon#about to write, iclass 21, count 2 2006.218.07:54:11.06#ibcon#wrote, iclass 21, count 2 2006.218.07:54:11.06#ibcon#about to read 3, iclass 21, count 2 2006.218.07:54:11.09#ibcon#read 3, iclass 21, count 2 2006.218.07:54:11.09#ibcon#about to read 4, iclass 21, count 2 2006.218.07:54:11.09#ibcon#read 4, iclass 21, count 2 2006.218.07:54:11.09#ibcon#about to read 5, iclass 21, count 2 2006.218.07:54:11.09#ibcon#read 5, iclass 21, count 2 2006.218.07:54:11.09#ibcon#about to read 6, iclass 21, count 2 2006.218.07:54:11.09#ibcon#read 6, iclass 21, count 2 2006.218.07:54:11.09#ibcon#end of sib2, iclass 21, count 2 2006.218.07:54:11.09#ibcon#*after write, iclass 21, count 2 2006.218.07:54:11.09#ibcon#*before return 0, iclass 21, count 2 2006.218.07:54:11.09#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.218.07:54:11.09#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.218.07:54:11.09#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.218.07:54:11.09#ibcon#ireg 7 cls_cnt 0 2006.218.07:54:11.09#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.218.07:54:11.21#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.218.07:54:11.21#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.218.07:54:11.21#ibcon#enter wrdev, iclass 21, count 0 2006.218.07:54:11.21#ibcon#first serial, iclass 21, count 0 2006.218.07:54:11.21#ibcon#enter sib2, iclass 21, count 0 2006.218.07:54:11.21#ibcon#flushed, iclass 21, count 0 2006.218.07:54:11.21#ibcon#about to write, iclass 21, count 0 2006.218.07:54:11.21#ibcon#wrote, iclass 21, count 0 2006.218.07:54:11.21#ibcon#about to read 3, iclass 21, count 0 2006.218.07:54:11.25#ibcon#read 3, iclass 21, count 0 2006.218.07:54:11.25#ibcon#about to read 4, iclass 21, count 0 2006.218.07:54:11.25#ibcon#read 4, iclass 21, count 0 2006.218.07:54:11.25#ibcon#about to read 5, iclass 21, count 0 2006.218.07:54:11.25#ibcon#read 5, iclass 21, count 0 2006.218.07:54:11.25#ibcon#about to read 6, iclass 21, count 0 2006.218.07:54:11.25#ibcon#read 6, iclass 21, count 0 2006.218.07:54:11.25#ibcon#end of sib2, iclass 21, count 0 2006.218.07:54:11.25#ibcon#*mode == 0, iclass 21, count 0 2006.218.07:54:11.25#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.218.07:54:11.25#ibcon#[27=USB\r\n] 2006.218.07:54:11.25#ibcon#*before write, iclass 21, count 0 2006.218.07:54:11.25#ibcon#enter sib2, iclass 21, count 0 2006.218.07:54:11.25#ibcon#flushed, iclass 21, count 0 2006.218.07:54:11.25#ibcon#about to write, iclass 21, count 0 2006.218.07:54:11.25#ibcon#wrote, iclass 21, count 0 2006.218.07:54:11.25#ibcon#about to read 3, iclass 21, count 0 2006.218.07:54:11.27#ibcon#read 3, iclass 21, count 0 2006.218.07:54:11.27#ibcon#about to read 4, iclass 21, count 0 2006.218.07:54:11.27#ibcon#read 4, iclass 21, count 0 2006.218.07:54:11.27#ibcon#about to read 5, iclass 21, count 0 2006.218.07:54:11.27#ibcon#read 5, iclass 21, count 0 2006.218.07:54:11.27#ibcon#about to read 6, iclass 21, count 0 2006.218.07:54:11.27#ibcon#read 6, iclass 21, count 0 2006.218.07:54:11.27#ibcon#end of sib2, iclass 21, count 0 2006.218.07:54:11.27#ibcon#*after write, iclass 21, count 0 2006.218.07:54:11.27#ibcon#*before return 0, iclass 21, count 0 2006.218.07:54:11.27#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.218.07:54:11.27#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.218.07:54:11.27#ibcon#about to clear, iclass 21 cls_cnt 0 2006.218.07:54:11.27#ibcon#cleared, iclass 21 cls_cnt 0 2006.218.07:54:11.27$vc4f8/vblo=3,656.99 2006.218.07:54:11.27#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.218.07:54:11.27#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.218.07:54:11.27#ibcon#ireg 17 cls_cnt 0 2006.218.07:54:11.27#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.218.07:54:11.27#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.218.07:54:11.27#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.218.07:54:11.27#ibcon#enter wrdev, iclass 23, count 0 2006.218.07:54:11.27#ibcon#first serial, iclass 23, count 0 2006.218.07:54:11.27#ibcon#enter sib2, iclass 23, count 0 2006.218.07:54:11.27#ibcon#flushed, iclass 23, count 0 2006.218.07:54:11.27#ibcon#about to write, iclass 23, count 0 2006.218.07:54:11.27#ibcon#wrote, iclass 23, count 0 2006.218.07:54:11.27#ibcon#about to read 3, iclass 23, count 0 2006.218.07:54:11.29#ibcon#read 3, iclass 23, count 0 2006.218.07:54:11.29#ibcon#about to read 4, iclass 23, count 0 2006.218.07:54:11.29#ibcon#read 4, iclass 23, count 0 2006.218.07:54:11.29#ibcon#about to read 5, iclass 23, count 0 2006.218.07:54:11.29#ibcon#read 5, iclass 23, count 0 2006.218.07:54:11.29#ibcon#about to read 6, iclass 23, count 0 2006.218.07:54:11.29#ibcon#read 6, iclass 23, count 0 2006.218.07:54:11.29#ibcon#end of sib2, iclass 23, count 0 2006.218.07:54:11.29#ibcon#*mode == 0, iclass 23, count 0 2006.218.07:54:11.29#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.218.07:54:11.29#ibcon#[28=FRQ=03,656.99\r\n] 2006.218.07:54:11.29#ibcon#*before write, iclass 23, count 0 2006.218.07:54:11.29#ibcon#enter sib2, iclass 23, count 0 2006.218.07:54:11.29#ibcon#flushed, iclass 23, count 0 2006.218.07:54:11.29#ibcon#about to write, iclass 23, count 0 2006.218.07:54:11.29#ibcon#wrote, iclass 23, count 0 2006.218.07:54:11.29#ibcon#about to read 3, iclass 23, count 0 2006.218.07:54:11.33#ibcon#read 3, iclass 23, count 0 2006.218.07:54:11.33#ibcon#about to read 4, iclass 23, count 0 2006.218.07:54:11.33#ibcon#read 4, iclass 23, count 0 2006.218.07:54:11.33#ibcon#about to read 5, iclass 23, count 0 2006.218.07:54:11.33#ibcon#read 5, iclass 23, count 0 2006.218.07:54:11.33#ibcon#about to read 6, iclass 23, count 0 2006.218.07:54:11.33#ibcon#read 6, iclass 23, count 0 2006.218.07:54:11.33#ibcon#end of sib2, iclass 23, count 0 2006.218.07:54:11.33#ibcon#*after write, iclass 23, count 0 2006.218.07:54:11.33#ibcon#*before return 0, iclass 23, count 0 2006.218.07:54:11.33#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.218.07:54:11.33#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.218.07:54:11.33#ibcon#about to clear, iclass 23 cls_cnt 0 2006.218.07:54:11.33#ibcon#cleared, iclass 23 cls_cnt 0 2006.218.07:54:11.33$vc4f8/vb=3,4 2006.218.07:54:11.33#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.218.07:54:11.33#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.218.07:54:11.33#ibcon#ireg 11 cls_cnt 2 2006.218.07:54:11.33#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.218.07:54:11.39#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.218.07:54:11.39#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.218.07:54:11.39#ibcon#enter wrdev, iclass 25, count 2 2006.218.07:54:11.39#ibcon#first serial, iclass 25, count 2 2006.218.07:54:11.39#ibcon#enter sib2, iclass 25, count 2 2006.218.07:54:11.39#ibcon#flushed, iclass 25, count 2 2006.218.07:54:11.39#ibcon#about to write, iclass 25, count 2 2006.218.07:54:11.39#ibcon#wrote, iclass 25, count 2 2006.218.07:54:11.39#ibcon#about to read 3, iclass 25, count 2 2006.218.07:54:11.41#ibcon#read 3, iclass 25, count 2 2006.218.07:54:11.41#ibcon#about to read 4, iclass 25, count 2 2006.218.07:54:11.41#ibcon#read 4, iclass 25, count 2 2006.218.07:54:11.41#ibcon#about to read 5, iclass 25, count 2 2006.218.07:54:11.41#ibcon#read 5, iclass 25, count 2 2006.218.07:54:11.41#ibcon#about to read 6, iclass 25, count 2 2006.218.07:54:11.41#ibcon#read 6, iclass 25, count 2 2006.218.07:54:11.41#ibcon#end of sib2, iclass 25, count 2 2006.218.07:54:11.41#ibcon#*mode == 0, iclass 25, count 2 2006.218.07:54:11.41#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.218.07:54:11.41#ibcon#[27=AT03-04\r\n] 2006.218.07:54:11.41#ibcon#*before write, iclass 25, count 2 2006.218.07:54:11.41#ibcon#enter sib2, iclass 25, count 2 2006.218.07:54:11.41#ibcon#flushed, iclass 25, count 2 2006.218.07:54:11.41#ibcon#about to write, iclass 25, count 2 2006.218.07:54:11.41#ibcon#wrote, iclass 25, count 2 2006.218.07:54:11.41#ibcon#about to read 3, iclass 25, count 2 2006.218.07:54:11.44#ibcon#read 3, iclass 25, count 2 2006.218.07:54:11.44#ibcon#about to read 4, iclass 25, count 2 2006.218.07:54:11.44#ibcon#read 4, iclass 25, count 2 2006.218.07:54:11.44#ibcon#about to read 5, iclass 25, count 2 2006.218.07:54:11.44#ibcon#read 5, iclass 25, count 2 2006.218.07:54:11.44#ibcon#about to read 6, iclass 25, count 2 2006.218.07:54:11.44#ibcon#read 6, iclass 25, count 2 2006.218.07:54:11.44#ibcon#end of sib2, iclass 25, count 2 2006.218.07:54:11.44#ibcon#*after write, iclass 25, count 2 2006.218.07:54:11.44#ibcon#*before return 0, iclass 25, count 2 2006.218.07:54:11.44#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.218.07:54:11.44#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.218.07:54:11.44#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.218.07:54:11.44#ibcon#ireg 7 cls_cnt 0 2006.218.07:54:11.44#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.218.07:54:11.56#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.218.07:54:11.56#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.218.07:54:11.56#ibcon#enter wrdev, iclass 25, count 0 2006.218.07:54:11.56#ibcon#first serial, iclass 25, count 0 2006.218.07:54:11.56#ibcon#enter sib2, iclass 25, count 0 2006.218.07:54:11.56#ibcon#flushed, iclass 25, count 0 2006.218.07:54:11.56#ibcon#about to write, iclass 25, count 0 2006.218.07:54:11.56#ibcon#wrote, iclass 25, count 0 2006.218.07:54:11.56#ibcon#about to read 3, iclass 25, count 0 2006.218.07:54:11.58#ibcon#read 3, iclass 25, count 0 2006.218.07:54:11.58#ibcon#about to read 4, iclass 25, count 0 2006.218.07:54:11.58#ibcon#read 4, iclass 25, count 0 2006.218.07:54:11.58#ibcon#about to read 5, iclass 25, count 0 2006.218.07:54:11.58#ibcon#read 5, iclass 25, count 0 2006.218.07:54:11.58#ibcon#about to read 6, iclass 25, count 0 2006.218.07:54:11.58#ibcon#read 6, iclass 25, count 0 2006.218.07:54:11.58#ibcon#end of sib2, iclass 25, count 0 2006.218.07:54:11.58#ibcon#*mode == 0, iclass 25, count 0 2006.218.07:54:11.58#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.218.07:54:11.58#ibcon#[27=USB\r\n] 2006.218.07:54:11.58#ibcon#*before write, iclass 25, count 0 2006.218.07:54:11.58#ibcon#enter sib2, iclass 25, count 0 2006.218.07:54:11.58#ibcon#flushed, iclass 25, count 0 2006.218.07:54:11.58#ibcon#about to write, iclass 25, count 0 2006.218.07:54:11.58#ibcon#wrote, iclass 25, count 0 2006.218.07:54:11.58#ibcon#about to read 3, iclass 25, count 0 2006.218.07:54:11.61#ibcon#read 3, iclass 25, count 0 2006.218.07:54:11.61#ibcon#about to read 4, iclass 25, count 0 2006.218.07:54:11.61#ibcon#read 4, iclass 25, count 0 2006.218.07:54:11.61#ibcon#about to read 5, iclass 25, count 0 2006.218.07:54:11.61#ibcon#read 5, iclass 25, count 0 2006.218.07:54:11.61#ibcon#about to read 6, iclass 25, count 0 2006.218.07:54:11.61#ibcon#read 6, iclass 25, count 0 2006.218.07:54:11.61#ibcon#end of sib2, iclass 25, count 0 2006.218.07:54:11.61#ibcon#*after write, iclass 25, count 0 2006.218.07:54:11.61#ibcon#*before return 0, iclass 25, count 0 2006.218.07:54:11.61#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.218.07:54:11.61#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.218.07:54:11.61#ibcon#about to clear, iclass 25 cls_cnt 0 2006.218.07:54:11.61#ibcon#cleared, iclass 25 cls_cnt 0 2006.218.07:54:11.61$vc4f8/vblo=4,712.99 2006.218.07:54:11.61#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.218.07:54:11.61#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.218.07:54:11.61#ibcon#ireg 17 cls_cnt 0 2006.218.07:54:11.61#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.218.07:54:11.61#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.218.07:54:11.61#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.218.07:54:11.61#ibcon#enter wrdev, iclass 27, count 0 2006.218.07:54:11.61#ibcon#first serial, iclass 27, count 0 2006.218.07:54:11.61#ibcon#enter sib2, iclass 27, count 0 2006.218.07:54:11.61#ibcon#flushed, iclass 27, count 0 2006.218.07:54:11.61#ibcon#about to write, iclass 27, count 0 2006.218.07:54:11.61#ibcon#wrote, iclass 27, count 0 2006.218.07:54:11.61#ibcon#about to read 3, iclass 27, count 0 2006.218.07:54:11.63#ibcon#read 3, iclass 27, count 0 2006.218.07:54:11.63#ibcon#about to read 4, iclass 27, count 0 2006.218.07:54:11.63#ibcon#read 4, iclass 27, count 0 2006.218.07:54:11.63#ibcon#about to read 5, iclass 27, count 0 2006.218.07:54:11.63#ibcon#read 5, iclass 27, count 0 2006.218.07:54:11.63#ibcon#about to read 6, iclass 27, count 0 2006.218.07:54:11.63#ibcon#read 6, iclass 27, count 0 2006.218.07:54:11.63#ibcon#end of sib2, iclass 27, count 0 2006.218.07:54:11.63#ibcon#*mode == 0, iclass 27, count 0 2006.218.07:54:11.63#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.218.07:54:11.63#ibcon#[28=FRQ=04,712.99\r\n] 2006.218.07:54:11.63#ibcon#*before write, iclass 27, count 0 2006.218.07:54:11.63#ibcon#enter sib2, iclass 27, count 0 2006.218.07:54:11.63#ibcon#flushed, iclass 27, count 0 2006.218.07:54:11.63#ibcon#about to write, iclass 27, count 0 2006.218.07:54:11.63#ibcon#wrote, iclass 27, count 0 2006.218.07:54:11.63#ibcon#about to read 3, iclass 27, count 0 2006.218.07:54:11.67#ibcon#read 3, iclass 27, count 0 2006.218.07:54:11.67#ibcon#about to read 4, iclass 27, count 0 2006.218.07:54:11.67#ibcon#read 4, iclass 27, count 0 2006.218.07:54:11.67#ibcon#about to read 5, iclass 27, count 0 2006.218.07:54:11.67#ibcon#read 5, iclass 27, count 0 2006.218.07:54:11.67#ibcon#about to read 6, iclass 27, count 0 2006.218.07:54:11.67#ibcon#read 6, iclass 27, count 0 2006.218.07:54:11.67#ibcon#end of sib2, iclass 27, count 0 2006.218.07:54:11.67#ibcon#*after write, iclass 27, count 0 2006.218.07:54:11.67#ibcon#*before return 0, iclass 27, count 0 2006.218.07:54:11.67#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.218.07:54:11.67#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.218.07:54:11.67#ibcon#about to clear, iclass 27 cls_cnt 0 2006.218.07:54:11.67#ibcon#cleared, iclass 27 cls_cnt 0 2006.218.07:54:11.67$vc4f8/vb=4,4 2006.218.07:54:11.67#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.218.07:54:11.67#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.218.07:54:11.67#ibcon#ireg 11 cls_cnt 2 2006.218.07:54:11.67#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.218.07:54:11.73#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.218.07:54:11.73#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.218.07:54:11.73#ibcon#enter wrdev, iclass 29, count 2 2006.218.07:54:11.73#ibcon#first serial, iclass 29, count 2 2006.218.07:54:11.73#ibcon#enter sib2, iclass 29, count 2 2006.218.07:54:11.73#ibcon#flushed, iclass 29, count 2 2006.218.07:54:11.73#ibcon#about to write, iclass 29, count 2 2006.218.07:54:11.73#ibcon#wrote, iclass 29, count 2 2006.218.07:54:11.73#ibcon#about to read 3, iclass 29, count 2 2006.218.07:54:11.75#ibcon#read 3, iclass 29, count 2 2006.218.07:54:11.75#ibcon#about to read 4, iclass 29, count 2 2006.218.07:54:11.75#ibcon#read 4, iclass 29, count 2 2006.218.07:54:11.75#ibcon#about to read 5, iclass 29, count 2 2006.218.07:54:11.75#ibcon#read 5, iclass 29, count 2 2006.218.07:54:11.75#ibcon#about to read 6, iclass 29, count 2 2006.218.07:54:11.75#ibcon#read 6, iclass 29, count 2 2006.218.07:54:11.75#ibcon#end of sib2, iclass 29, count 2 2006.218.07:54:11.75#ibcon#*mode == 0, iclass 29, count 2 2006.218.07:54:11.75#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.218.07:54:11.75#ibcon#[27=AT04-04\r\n] 2006.218.07:54:11.75#ibcon#*before write, iclass 29, count 2 2006.218.07:54:11.75#ibcon#enter sib2, iclass 29, count 2 2006.218.07:54:11.75#ibcon#flushed, iclass 29, count 2 2006.218.07:54:11.75#ibcon#about to write, iclass 29, count 2 2006.218.07:54:11.75#ibcon#wrote, iclass 29, count 2 2006.218.07:54:11.75#ibcon#about to read 3, iclass 29, count 2 2006.218.07:54:11.78#ibcon#read 3, iclass 29, count 2 2006.218.07:54:11.78#ibcon#about to read 4, iclass 29, count 2 2006.218.07:54:11.78#ibcon#read 4, iclass 29, count 2 2006.218.07:54:11.78#ibcon#about to read 5, iclass 29, count 2 2006.218.07:54:11.78#ibcon#read 5, iclass 29, count 2 2006.218.07:54:11.78#ibcon#about to read 6, iclass 29, count 2 2006.218.07:54:11.78#ibcon#read 6, iclass 29, count 2 2006.218.07:54:11.78#ibcon#end of sib2, iclass 29, count 2 2006.218.07:54:11.78#ibcon#*after write, iclass 29, count 2 2006.218.07:54:11.78#ibcon#*before return 0, iclass 29, count 2 2006.218.07:54:11.78#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.218.07:54:11.78#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.218.07:54:11.78#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.218.07:54:11.78#ibcon#ireg 7 cls_cnt 0 2006.218.07:54:11.78#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.218.07:54:11.90#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.218.07:54:11.90#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.218.07:54:11.90#ibcon#enter wrdev, iclass 29, count 0 2006.218.07:54:11.90#ibcon#first serial, iclass 29, count 0 2006.218.07:54:11.90#ibcon#enter sib2, iclass 29, count 0 2006.218.07:54:11.90#ibcon#flushed, iclass 29, count 0 2006.218.07:54:11.90#ibcon#about to write, iclass 29, count 0 2006.218.07:54:11.90#ibcon#wrote, iclass 29, count 0 2006.218.07:54:11.90#ibcon#about to read 3, iclass 29, count 0 2006.218.07:54:11.92#ibcon#read 3, iclass 29, count 0 2006.218.07:54:11.92#ibcon#about to read 4, iclass 29, count 0 2006.218.07:54:11.92#ibcon#read 4, iclass 29, count 0 2006.218.07:54:11.92#ibcon#about to read 5, iclass 29, count 0 2006.218.07:54:11.92#ibcon#read 5, iclass 29, count 0 2006.218.07:54:11.92#ibcon#about to read 6, iclass 29, count 0 2006.218.07:54:11.92#ibcon#read 6, iclass 29, count 0 2006.218.07:54:11.92#ibcon#end of sib2, iclass 29, count 0 2006.218.07:54:11.92#ibcon#*mode == 0, iclass 29, count 0 2006.218.07:54:11.92#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.218.07:54:11.92#ibcon#[27=USB\r\n] 2006.218.07:54:11.92#ibcon#*before write, iclass 29, count 0 2006.218.07:54:11.92#ibcon#enter sib2, iclass 29, count 0 2006.218.07:54:11.92#ibcon#flushed, iclass 29, count 0 2006.218.07:54:11.92#ibcon#about to write, iclass 29, count 0 2006.218.07:54:11.92#ibcon#wrote, iclass 29, count 0 2006.218.07:54:11.92#ibcon#about to read 3, iclass 29, count 0 2006.218.07:54:11.95#ibcon#read 3, iclass 29, count 0 2006.218.07:54:11.95#ibcon#about to read 4, iclass 29, count 0 2006.218.07:54:11.95#ibcon#read 4, iclass 29, count 0 2006.218.07:54:11.95#ibcon#about to read 5, iclass 29, count 0 2006.218.07:54:11.95#ibcon#read 5, iclass 29, count 0 2006.218.07:54:11.95#ibcon#about to read 6, iclass 29, count 0 2006.218.07:54:11.95#ibcon#read 6, iclass 29, count 0 2006.218.07:54:11.95#ibcon#end of sib2, iclass 29, count 0 2006.218.07:54:11.95#ibcon#*after write, iclass 29, count 0 2006.218.07:54:11.95#ibcon#*before return 0, iclass 29, count 0 2006.218.07:54:11.95#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.218.07:54:11.95#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.218.07:54:11.95#ibcon#about to clear, iclass 29 cls_cnt 0 2006.218.07:54:11.95#ibcon#cleared, iclass 29 cls_cnt 0 2006.218.07:54:11.95$vc4f8/vblo=5,744.99 2006.218.07:54:11.95#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.218.07:54:11.95#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.218.07:54:11.95#ibcon#ireg 17 cls_cnt 0 2006.218.07:54:11.95#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.218.07:54:11.95#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.218.07:54:11.95#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.218.07:54:11.95#ibcon#enter wrdev, iclass 31, count 0 2006.218.07:54:11.95#ibcon#first serial, iclass 31, count 0 2006.218.07:54:11.95#ibcon#enter sib2, iclass 31, count 0 2006.218.07:54:11.95#ibcon#flushed, iclass 31, count 0 2006.218.07:54:11.95#ibcon#about to write, iclass 31, count 0 2006.218.07:54:11.95#ibcon#wrote, iclass 31, count 0 2006.218.07:54:11.95#ibcon#about to read 3, iclass 31, count 0 2006.218.07:54:11.97#ibcon#read 3, iclass 31, count 0 2006.218.07:54:11.97#ibcon#about to read 4, iclass 31, count 0 2006.218.07:54:11.97#ibcon#read 4, iclass 31, count 0 2006.218.07:54:11.97#ibcon#about to read 5, iclass 31, count 0 2006.218.07:54:11.97#ibcon#read 5, iclass 31, count 0 2006.218.07:54:11.97#ibcon#about to read 6, iclass 31, count 0 2006.218.07:54:11.97#ibcon#read 6, iclass 31, count 0 2006.218.07:54:11.97#ibcon#end of sib2, iclass 31, count 0 2006.218.07:54:11.97#ibcon#*mode == 0, iclass 31, count 0 2006.218.07:54:11.97#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.218.07:54:11.97#ibcon#[28=FRQ=05,744.99\r\n] 2006.218.07:54:11.97#ibcon#*before write, iclass 31, count 0 2006.218.07:54:11.97#ibcon#enter sib2, iclass 31, count 0 2006.218.07:54:11.97#ibcon#flushed, iclass 31, count 0 2006.218.07:54:11.97#ibcon#about to write, iclass 31, count 0 2006.218.07:54:11.97#ibcon#wrote, iclass 31, count 0 2006.218.07:54:11.97#ibcon#about to read 3, iclass 31, count 0 2006.218.07:54:12.01#ibcon#read 3, iclass 31, count 0 2006.218.07:54:12.01#ibcon#about to read 4, iclass 31, count 0 2006.218.07:54:12.01#ibcon#read 4, iclass 31, count 0 2006.218.07:54:12.01#ibcon#about to read 5, iclass 31, count 0 2006.218.07:54:12.01#ibcon#read 5, iclass 31, count 0 2006.218.07:54:12.01#ibcon#about to read 6, iclass 31, count 0 2006.218.07:54:12.01#ibcon#read 6, iclass 31, count 0 2006.218.07:54:12.01#ibcon#end of sib2, iclass 31, count 0 2006.218.07:54:12.01#ibcon#*after write, iclass 31, count 0 2006.218.07:54:12.01#ibcon#*before return 0, iclass 31, count 0 2006.218.07:54:12.01#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.218.07:54:12.01#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.218.07:54:12.01#ibcon#about to clear, iclass 31 cls_cnt 0 2006.218.07:54:12.01#ibcon#cleared, iclass 31 cls_cnt 0 2006.218.07:54:12.01$vc4f8/vb=5,4 2006.218.07:54:12.01#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.218.07:54:12.01#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.218.07:54:12.01#ibcon#ireg 11 cls_cnt 2 2006.218.07:54:12.01#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.218.07:54:12.08#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.218.07:54:12.08#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.218.07:54:12.08#ibcon#enter wrdev, iclass 33, count 2 2006.218.07:54:12.08#ibcon#first serial, iclass 33, count 2 2006.218.07:54:12.08#ibcon#enter sib2, iclass 33, count 2 2006.218.07:54:12.08#ibcon#flushed, iclass 33, count 2 2006.218.07:54:12.08#ibcon#about to write, iclass 33, count 2 2006.218.07:54:12.08#ibcon#wrote, iclass 33, count 2 2006.218.07:54:12.08#ibcon#about to read 3, iclass 33, count 2 2006.218.07:54:12.09#ibcon#read 3, iclass 33, count 2 2006.218.07:54:12.09#ibcon#about to read 4, iclass 33, count 2 2006.218.07:54:12.09#ibcon#read 4, iclass 33, count 2 2006.218.07:54:12.09#ibcon#about to read 5, iclass 33, count 2 2006.218.07:54:12.09#ibcon#read 5, iclass 33, count 2 2006.218.07:54:12.09#ibcon#about to read 6, iclass 33, count 2 2006.218.07:54:12.09#ibcon#read 6, iclass 33, count 2 2006.218.07:54:12.09#ibcon#end of sib2, iclass 33, count 2 2006.218.07:54:12.09#ibcon#*mode == 0, iclass 33, count 2 2006.218.07:54:12.09#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.218.07:54:12.09#ibcon#[27=AT05-04\r\n] 2006.218.07:54:12.09#ibcon#*before write, iclass 33, count 2 2006.218.07:54:12.09#ibcon#enter sib2, iclass 33, count 2 2006.218.07:54:12.09#ibcon#flushed, iclass 33, count 2 2006.218.07:54:12.09#ibcon#about to write, iclass 33, count 2 2006.218.07:54:12.09#ibcon#wrote, iclass 33, count 2 2006.218.07:54:12.09#ibcon#about to read 3, iclass 33, count 2 2006.218.07:54:12.12#ibcon#read 3, iclass 33, count 2 2006.218.07:54:12.12#ibcon#about to read 4, iclass 33, count 2 2006.218.07:54:12.12#ibcon#read 4, iclass 33, count 2 2006.218.07:54:12.12#ibcon#about to read 5, iclass 33, count 2 2006.218.07:54:12.12#ibcon#read 5, iclass 33, count 2 2006.218.07:54:12.12#ibcon#about to read 6, iclass 33, count 2 2006.218.07:54:12.12#ibcon#read 6, iclass 33, count 2 2006.218.07:54:12.12#ibcon#end of sib2, iclass 33, count 2 2006.218.07:54:12.12#ibcon#*after write, iclass 33, count 2 2006.218.07:54:12.12#ibcon#*before return 0, iclass 33, count 2 2006.218.07:54:12.12#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.218.07:54:12.12#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.218.07:54:12.12#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.218.07:54:12.12#ibcon#ireg 7 cls_cnt 0 2006.218.07:54:12.12#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.218.07:54:12.24#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.218.07:54:12.24#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.218.07:54:12.24#ibcon#enter wrdev, iclass 33, count 0 2006.218.07:54:12.24#ibcon#first serial, iclass 33, count 0 2006.218.07:54:12.24#ibcon#enter sib2, iclass 33, count 0 2006.218.07:54:12.24#ibcon#flushed, iclass 33, count 0 2006.218.07:54:12.24#ibcon#about to write, iclass 33, count 0 2006.218.07:54:12.24#ibcon#wrote, iclass 33, count 0 2006.218.07:54:12.24#ibcon#about to read 3, iclass 33, count 0 2006.218.07:54:12.26#ibcon#read 3, iclass 33, count 0 2006.218.07:54:12.26#ibcon#about to read 4, iclass 33, count 0 2006.218.07:54:12.26#ibcon#read 4, iclass 33, count 0 2006.218.07:54:12.26#ibcon#about to read 5, iclass 33, count 0 2006.218.07:54:12.26#ibcon#read 5, iclass 33, count 0 2006.218.07:54:12.26#ibcon#about to read 6, iclass 33, count 0 2006.218.07:54:12.26#ibcon#read 6, iclass 33, count 0 2006.218.07:54:12.26#ibcon#end of sib2, iclass 33, count 0 2006.218.07:54:12.26#ibcon#*mode == 0, iclass 33, count 0 2006.218.07:54:12.26#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.218.07:54:12.26#ibcon#[27=USB\r\n] 2006.218.07:54:12.26#ibcon#*before write, iclass 33, count 0 2006.218.07:54:12.26#ibcon#enter sib2, iclass 33, count 0 2006.218.07:54:12.26#ibcon#flushed, iclass 33, count 0 2006.218.07:54:12.26#ibcon#about to write, iclass 33, count 0 2006.218.07:54:12.26#ibcon#wrote, iclass 33, count 0 2006.218.07:54:12.26#ibcon#about to read 3, iclass 33, count 0 2006.218.07:54:12.29#ibcon#read 3, iclass 33, count 0 2006.218.07:54:12.29#ibcon#about to read 4, iclass 33, count 0 2006.218.07:54:12.29#ibcon#read 4, iclass 33, count 0 2006.218.07:54:12.29#ibcon#about to read 5, iclass 33, count 0 2006.218.07:54:12.29#ibcon#read 5, iclass 33, count 0 2006.218.07:54:12.29#ibcon#about to read 6, iclass 33, count 0 2006.218.07:54:12.29#ibcon#read 6, iclass 33, count 0 2006.218.07:54:12.29#ibcon#end of sib2, iclass 33, count 0 2006.218.07:54:12.29#ibcon#*after write, iclass 33, count 0 2006.218.07:54:12.29#ibcon#*before return 0, iclass 33, count 0 2006.218.07:54:12.29#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.218.07:54:12.29#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.218.07:54:12.29#ibcon#about to clear, iclass 33 cls_cnt 0 2006.218.07:54:12.29#ibcon#cleared, iclass 33 cls_cnt 0 2006.218.07:54:12.29$vc4f8/vblo=6,752.99 2006.218.07:54:12.29#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.218.07:54:12.29#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.218.07:54:12.29#ibcon#ireg 17 cls_cnt 0 2006.218.07:54:12.29#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.218.07:54:12.29#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.218.07:54:12.29#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.218.07:54:12.29#ibcon#enter wrdev, iclass 35, count 0 2006.218.07:54:12.29#ibcon#first serial, iclass 35, count 0 2006.218.07:54:12.29#ibcon#enter sib2, iclass 35, count 0 2006.218.07:54:12.29#ibcon#flushed, iclass 35, count 0 2006.218.07:54:12.29#ibcon#about to write, iclass 35, count 0 2006.218.07:54:12.29#ibcon#wrote, iclass 35, count 0 2006.218.07:54:12.29#ibcon#about to read 3, iclass 35, count 0 2006.218.07:54:12.31#ibcon#read 3, iclass 35, count 0 2006.218.07:54:12.31#ibcon#about to read 4, iclass 35, count 0 2006.218.07:54:12.31#ibcon#read 4, iclass 35, count 0 2006.218.07:54:12.31#ibcon#about to read 5, iclass 35, count 0 2006.218.07:54:12.31#ibcon#read 5, iclass 35, count 0 2006.218.07:54:12.31#ibcon#about to read 6, iclass 35, count 0 2006.218.07:54:12.31#ibcon#read 6, iclass 35, count 0 2006.218.07:54:12.31#ibcon#end of sib2, iclass 35, count 0 2006.218.07:54:12.31#ibcon#*mode == 0, iclass 35, count 0 2006.218.07:54:12.31#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.218.07:54:12.31#ibcon#[28=FRQ=06,752.99\r\n] 2006.218.07:54:12.31#ibcon#*before write, iclass 35, count 0 2006.218.07:54:12.31#ibcon#enter sib2, iclass 35, count 0 2006.218.07:54:12.31#ibcon#flushed, iclass 35, count 0 2006.218.07:54:12.31#ibcon#about to write, iclass 35, count 0 2006.218.07:54:12.31#ibcon#wrote, iclass 35, count 0 2006.218.07:54:12.31#ibcon#about to read 3, iclass 35, count 0 2006.218.07:54:12.35#ibcon#read 3, iclass 35, count 0 2006.218.07:54:12.35#ibcon#about to read 4, iclass 35, count 0 2006.218.07:54:12.35#ibcon#read 4, iclass 35, count 0 2006.218.07:54:12.35#ibcon#about to read 5, iclass 35, count 0 2006.218.07:54:12.35#ibcon#read 5, iclass 35, count 0 2006.218.07:54:12.35#ibcon#about to read 6, iclass 35, count 0 2006.218.07:54:12.35#ibcon#read 6, iclass 35, count 0 2006.218.07:54:12.35#ibcon#end of sib2, iclass 35, count 0 2006.218.07:54:12.35#ibcon#*after write, iclass 35, count 0 2006.218.07:54:12.35#ibcon#*before return 0, iclass 35, count 0 2006.218.07:54:12.35#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.218.07:54:12.35#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.218.07:54:12.35#ibcon#about to clear, iclass 35 cls_cnt 0 2006.218.07:54:12.35#ibcon#cleared, iclass 35 cls_cnt 0 2006.218.07:54:12.35$vc4f8/vb=6,4 2006.218.07:54:12.35#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.218.07:54:12.35#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.218.07:54:12.35#ibcon#ireg 11 cls_cnt 2 2006.218.07:54:12.35#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.218.07:54:12.41#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.218.07:54:12.41#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.218.07:54:12.41#ibcon#enter wrdev, iclass 37, count 2 2006.218.07:54:12.41#ibcon#first serial, iclass 37, count 2 2006.218.07:54:12.41#ibcon#enter sib2, iclass 37, count 2 2006.218.07:54:12.41#ibcon#flushed, iclass 37, count 2 2006.218.07:54:12.41#ibcon#about to write, iclass 37, count 2 2006.218.07:54:12.41#ibcon#wrote, iclass 37, count 2 2006.218.07:54:12.41#ibcon#about to read 3, iclass 37, count 2 2006.218.07:54:12.43#ibcon#read 3, iclass 37, count 2 2006.218.07:54:12.43#ibcon#about to read 4, iclass 37, count 2 2006.218.07:54:12.43#ibcon#read 4, iclass 37, count 2 2006.218.07:54:12.43#ibcon#about to read 5, iclass 37, count 2 2006.218.07:54:12.43#ibcon#read 5, iclass 37, count 2 2006.218.07:54:12.43#ibcon#about to read 6, iclass 37, count 2 2006.218.07:54:12.43#ibcon#read 6, iclass 37, count 2 2006.218.07:54:12.43#ibcon#end of sib2, iclass 37, count 2 2006.218.07:54:12.43#ibcon#*mode == 0, iclass 37, count 2 2006.218.07:54:12.43#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.218.07:54:12.43#ibcon#[27=AT06-04\r\n] 2006.218.07:54:12.43#ibcon#*before write, iclass 37, count 2 2006.218.07:54:12.43#ibcon#enter sib2, iclass 37, count 2 2006.218.07:54:12.43#ibcon#flushed, iclass 37, count 2 2006.218.07:54:12.43#ibcon#about to write, iclass 37, count 2 2006.218.07:54:12.43#ibcon#wrote, iclass 37, count 2 2006.218.07:54:12.43#ibcon#about to read 3, iclass 37, count 2 2006.218.07:54:12.46#ibcon#read 3, iclass 37, count 2 2006.218.07:54:12.46#ibcon#about to read 4, iclass 37, count 2 2006.218.07:54:12.46#ibcon#read 4, iclass 37, count 2 2006.218.07:54:12.46#ibcon#about to read 5, iclass 37, count 2 2006.218.07:54:12.46#ibcon#read 5, iclass 37, count 2 2006.218.07:54:12.46#ibcon#about to read 6, iclass 37, count 2 2006.218.07:54:12.46#ibcon#read 6, iclass 37, count 2 2006.218.07:54:12.46#ibcon#end of sib2, iclass 37, count 2 2006.218.07:54:12.46#ibcon#*after write, iclass 37, count 2 2006.218.07:54:12.46#ibcon#*before return 0, iclass 37, count 2 2006.218.07:54:12.46#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.218.07:54:12.46#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.218.07:54:12.46#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.218.07:54:12.46#ibcon#ireg 7 cls_cnt 0 2006.218.07:54:12.46#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.218.07:54:12.58#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.218.07:54:12.58#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.218.07:54:12.58#ibcon#enter wrdev, iclass 37, count 0 2006.218.07:54:12.58#ibcon#first serial, iclass 37, count 0 2006.218.07:54:12.58#ibcon#enter sib2, iclass 37, count 0 2006.218.07:54:12.58#ibcon#flushed, iclass 37, count 0 2006.218.07:54:12.58#ibcon#about to write, iclass 37, count 0 2006.218.07:54:12.58#ibcon#wrote, iclass 37, count 0 2006.218.07:54:12.58#ibcon#about to read 3, iclass 37, count 0 2006.218.07:54:12.60#ibcon#read 3, iclass 37, count 0 2006.218.07:54:12.60#ibcon#about to read 4, iclass 37, count 0 2006.218.07:54:12.60#ibcon#read 4, iclass 37, count 0 2006.218.07:54:12.60#ibcon#about to read 5, iclass 37, count 0 2006.218.07:54:12.60#ibcon#read 5, iclass 37, count 0 2006.218.07:54:12.60#ibcon#about to read 6, iclass 37, count 0 2006.218.07:54:12.60#ibcon#read 6, iclass 37, count 0 2006.218.07:54:12.60#ibcon#end of sib2, iclass 37, count 0 2006.218.07:54:12.60#ibcon#*mode == 0, iclass 37, count 0 2006.218.07:54:12.60#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.218.07:54:12.60#ibcon#[27=USB\r\n] 2006.218.07:54:12.60#ibcon#*before write, iclass 37, count 0 2006.218.07:54:12.60#ibcon#enter sib2, iclass 37, count 0 2006.218.07:54:12.60#ibcon#flushed, iclass 37, count 0 2006.218.07:54:12.60#ibcon#about to write, iclass 37, count 0 2006.218.07:54:12.60#ibcon#wrote, iclass 37, count 0 2006.218.07:54:12.60#ibcon#about to read 3, iclass 37, count 0 2006.218.07:54:12.63#ibcon#read 3, iclass 37, count 0 2006.218.07:54:12.63#ibcon#about to read 4, iclass 37, count 0 2006.218.07:54:12.63#ibcon#read 4, iclass 37, count 0 2006.218.07:54:12.63#ibcon#about to read 5, iclass 37, count 0 2006.218.07:54:12.63#ibcon#read 5, iclass 37, count 0 2006.218.07:54:12.63#ibcon#about to read 6, iclass 37, count 0 2006.218.07:54:12.63#ibcon#read 6, iclass 37, count 0 2006.218.07:54:12.63#ibcon#end of sib2, iclass 37, count 0 2006.218.07:54:12.63#ibcon#*after write, iclass 37, count 0 2006.218.07:54:12.63#ibcon#*before return 0, iclass 37, count 0 2006.218.07:54:12.63#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.218.07:54:12.63#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.218.07:54:12.63#ibcon#about to clear, iclass 37 cls_cnt 0 2006.218.07:54:12.63#ibcon#cleared, iclass 37 cls_cnt 0 2006.218.07:54:12.63$vc4f8/vabw=wide 2006.218.07:54:12.63#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.218.07:54:12.63#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.218.07:54:12.63#ibcon#ireg 8 cls_cnt 0 2006.218.07:54:12.63#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.218.07:54:12.63#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.218.07:54:12.63#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.218.07:54:12.63#ibcon#enter wrdev, iclass 39, count 0 2006.218.07:54:12.63#ibcon#first serial, iclass 39, count 0 2006.218.07:54:12.63#ibcon#enter sib2, iclass 39, count 0 2006.218.07:54:12.63#ibcon#flushed, iclass 39, count 0 2006.218.07:54:12.63#ibcon#about to write, iclass 39, count 0 2006.218.07:54:12.63#ibcon#wrote, iclass 39, count 0 2006.218.07:54:12.63#ibcon#about to read 3, iclass 39, count 0 2006.218.07:54:12.65#ibcon#read 3, iclass 39, count 0 2006.218.07:54:12.65#ibcon#about to read 4, iclass 39, count 0 2006.218.07:54:12.65#ibcon#read 4, iclass 39, count 0 2006.218.07:54:12.65#ibcon#about to read 5, iclass 39, count 0 2006.218.07:54:12.65#ibcon#read 5, iclass 39, count 0 2006.218.07:54:12.65#ibcon#about to read 6, iclass 39, count 0 2006.218.07:54:12.65#ibcon#read 6, iclass 39, count 0 2006.218.07:54:12.65#ibcon#end of sib2, iclass 39, count 0 2006.218.07:54:12.65#ibcon#*mode == 0, iclass 39, count 0 2006.218.07:54:12.65#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.218.07:54:12.65#ibcon#[25=BW32\r\n] 2006.218.07:54:12.65#ibcon#*before write, iclass 39, count 0 2006.218.07:54:12.65#ibcon#enter sib2, iclass 39, count 0 2006.218.07:54:12.65#ibcon#flushed, iclass 39, count 0 2006.218.07:54:12.65#ibcon#about to write, iclass 39, count 0 2006.218.07:54:12.65#ibcon#wrote, iclass 39, count 0 2006.218.07:54:12.65#ibcon#about to read 3, iclass 39, count 0 2006.218.07:54:12.68#ibcon#read 3, iclass 39, count 0 2006.218.07:54:12.68#ibcon#about to read 4, iclass 39, count 0 2006.218.07:54:12.68#ibcon#read 4, iclass 39, count 0 2006.218.07:54:12.68#ibcon#about to read 5, iclass 39, count 0 2006.218.07:54:12.68#ibcon#read 5, iclass 39, count 0 2006.218.07:54:12.68#ibcon#about to read 6, iclass 39, count 0 2006.218.07:54:12.68#ibcon#read 6, iclass 39, count 0 2006.218.07:54:12.68#ibcon#end of sib2, iclass 39, count 0 2006.218.07:54:12.68#ibcon#*after write, iclass 39, count 0 2006.218.07:54:12.68#ibcon#*before return 0, iclass 39, count 0 2006.218.07:54:12.68#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.218.07:54:12.68#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.218.07:54:12.68#ibcon#about to clear, iclass 39 cls_cnt 0 2006.218.07:54:12.68#ibcon#cleared, iclass 39 cls_cnt 0 2006.218.07:54:12.68$vc4f8/vbbw=wide 2006.218.07:54:12.68#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.218.07:54:12.68#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.218.07:54:12.68#ibcon#ireg 8 cls_cnt 0 2006.218.07:54:12.68#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.218.07:54:12.76#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.218.07:54:12.76#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.218.07:54:12.76#ibcon#enter wrdev, iclass 3, count 0 2006.218.07:54:12.76#ibcon#first serial, iclass 3, count 0 2006.218.07:54:12.76#ibcon#enter sib2, iclass 3, count 0 2006.218.07:54:12.76#ibcon#flushed, iclass 3, count 0 2006.218.07:54:12.76#ibcon#about to write, iclass 3, count 0 2006.218.07:54:12.76#ibcon#wrote, iclass 3, count 0 2006.218.07:54:12.76#ibcon#about to read 3, iclass 3, count 0 2006.218.07:54:12.77#ibcon#read 3, iclass 3, count 0 2006.218.07:54:12.77#ibcon#about to read 4, iclass 3, count 0 2006.218.07:54:12.77#ibcon#read 4, iclass 3, count 0 2006.218.07:54:12.77#ibcon#about to read 5, iclass 3, count 0 2006.218.07:54:12.77#ibcon#read 5, iclass 3, count 0 2006.218.07:54:12.77#ibcon#about to read 6, iclass 3, count 0 2006.218.07:54:12.77#ibcon#read 6, iclass 3, count 0 2006.218.07:54:12.77#ibcon#end of sib2, iclass 3, count 0 2006.218.07:54:12.77#ibcon#*mode == 0, iclass 3, count 0 2006.218.07:54:12.77#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.218.07:54:12.77#ibcon#[27=BW32\r\n] 2006.218.07:54:12.77#ibcon#*before write, iclass 3, count 0 2006.218.07:54:12.77#ibcon#enter sib2, iclass 3, count 0 2006.218.07:54:12.77#ibcon#flushed, iclass 3, count 0 2006.218.07:54:12.77#ibcon#about to write, iclass 3, count 0 2006.218.07:54:12.77#ibcon#wrote, iclass 3, count 0 2006.218.07:54:12.77#ibcon#about to read 3, iclass 3, count 0 2006.218.07:54:12.80#ibcon#read 3, iclass 3, count 0 2006.218.07:54:12.80#ibcon#about to read 4, iclass 3, count 0 2006.218.07:54:12.80#ibcon#read 4, iclass 3, count 0 2006.218.07:54:12.80#ibcon#about to read 5, iclass 3, count 0 2006.218.07:54:12.80#ibcon#read 5, iclass 3, count 0 2006.218.07:54:12.80#ibcon#about to read 6, iclass 3, count 0 2006.218.07:54:12.80#ibcon#read 6, iclass 3, count 0 2006.218.07:54:12.80#ibcon#end of sib2, iclass 3, count 0 2006.218.07:54:12.80#ibcon#*after write, iclass 3, count 0 2006.218.07:54:12.80#ibcon#*before return 0, iclass 3, count 0 2006.218.07:54:12.80#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.218.07:54:12.80#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.218.07:54:12.80#ibcon#about to clear, iclass 3 cls_cnt 0 2006.218.07:54:12.80#ibcon#cleared, iclass 3 cls_cnt 0 2006.218.07:54:12.80$4f8m12a/ifd4f 2006.218.07:54:12.80$ifd4f/lo= 2006.218.07:54:12.80$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.218.07:54:12.80$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.218.07:54:12.80$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.218.07:54:12.80$ifd4f/patch= 2006.218.07:54:12.81$ifd4f/patch=lo1,a1,a2,a3,a4 2006.218.07:54:12.81$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.218.07:54:12.81$ifd4f/patch=lo3,a5,a6,a7,a8 2006.218.07:54:12.81$4f8m12a/"form=m,16.000,1:2 2006.218.07:54:12.81$4f8m12a/"tpicd 2006.218.07:54:12.81$4f8m12a/echo=off 2006.218.07:54:12.81$4f8m12a/xlog=off 2006.218.07:54:12.81:!2006.218.07:55:10 2006.218.07:54:48.13#trakl#Source acquired 2006.218.07:54:48.13#flagr#flagr/antenna,acquired 2006.218.07:55:10.01:preob 2006.218.07:55:11.13/onsource/TRACKING 2006.218.07:55:11.13:!2006.218.07:55:20 2006.218.07:55:20.00:data_valid=on 2006.218.07:55:20.00:midob 2006.218.07:55:20.14/onsource/TRACKING 2006.218.07:55:20.14/wx/31.09,1007.4,73 2006.218.07:55:20.29/cable/+6.3838E-03 2006.218.07:55:21.38/va/01,05,usb,yes,33,35 2006.218.07:55:21.38/va/02,04,usb,yes,31,33 2006.218.07:55:21.38/va/03,04,usb,yes,29,30 2006.218.07:55:21.38/va/04,04,usb,yes,33,35 2006.218.07:55:21.38/va/05,07,usb,yes,35,37 2006.218.07:55:21.38/va/06,06,usb,yes,34,34 2006.218.07:55:21.38/va/07,06,usb,yes,35,35 2006.218.07:55:21.38/va/08,07,usb,yes,33,33 2006.218.07:55:21.61/valo/01,532.99,yes,locked 2006.218.07:55:21.61/valo/02,572.99,yes,locked 2006.218.07:55:21.61/valo/03,672.99,yes,locked 2006.218.07:55:21.61/valo/04,832.99,yes,locked 2006.218.07:55:21.61/valo/05,652.99,yes,locked 2006.218.07:55:21.61/valo/06,772.99,yes,locked 2006.218.07:55:21.61/valo/07,832.99,yes,locked 2006.218.07:55:21.61/valo/08,852.99,yes,locked 2006.218.07:55:22.70/vb/01,04,usb,yes,31,30 2006.218.07:55:22.70/vb/02,04,usb,yes,33,35 2006.218.07:55:22.70/vb/03,04,usb,yes,30,34 2006.218.07:55:22.70/vb/04,04,usb,yes,30,31 2006.218.07:55:22.70/vb/05,04,usb,yes,29,33 2006.218.07:55:22.70/vb/06,04,usb,yes,30,33 2006.218.07:55:22.70/vb/07,04,usb,yes,32,32 2006.218.07:55:22.70/vb/08,04,usb,yes,30,33 2006.218.07:55:22.94/vblo/01,632.99,yes,locked 2006.218.07:55:22.94/vblo/02,640.99,yes,locked 2006.218.07:55:22.94/vblo/03,656.99,yes,locked 2006.218.07:55:22.94/vblo/04,712.99,yes,locked 2006.218.07:55:22.94/vblo/05,744.99,yes,locked 2006.218.07:55:22.94/vblo/06,752.99,yes,locked 2006.218.07:55:22.94/vblo/07,734.99,yes,locked 2006.218.07:55:22.94/vblo/08,744.99,yes,locked 2006.218.07:55:23.09/vabw/8 2006.218.07:55:23.24/vbbw/8 2006.218.07:55:23.34/xfe/off,on,14.7 2006.218.07:55:23.72/ifatt/23,28,28,28 2006.218.07:55:24.07/fmout-gps/S +4.68E-07 2006.218.07:55:24.15:!2006.218.07:56:20 2006.218.07:56:20.01:data_valid=off 2006.218.07:56:20.02:postob 2006.218.07:56:20.15/cable/+6.3854E-03 2006.218.07:56:20.16/wx/31.08,1007.4,73 2006.218.07:56:21.07/fmout-gps/S +4.68E-07 2006.218.07:56:21.08:scan_name=218-0758,k06218,60 2006.218.07:56:21.08:source=1417+385,141946.61,382148.5,2000.0,cw 2006.218.07:56:22.14#flagr#flagr/antenna,new-source 2006.218.07:56:22.15:checkk5 2006.218.07:56:22.52/chk_autoobs//k5ts1/ autoobs is running! 2006.218.07:56:22.90/chk_autoobs//k5ts2/ autoobs is running! 2006.218.07:56:23.27/chk_autoobs//k5ts3/ autoobs is running! 2006.218.07:56:23.65/chk_autoobs//k5ts4/ autoobs is running! 2006.218.07:56:24.02/chk_obsdata//k5ts1/T2180755??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:56:24.39/chk_obsdata//k5ts2/T2180755??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:56:24.76/chk_obsdata//k5ts3/T2180755??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:56:25.13/chk_obsdata//k5ts4/T2180755??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:56:25.83/k5log//k5ts1_log_newline 2006.218.07:56:26.51/k5log//k5ts2_log_newline 2006.218.07:56:27.21/k5log//k5ts3_log_newline 2006.218.07:56:27.89/k5log//k5ts4_log_newline 2006.218.07:56:27.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.218.07:56:27.91:4f8m12a=2 2006.218.07:56:27.91$4f8m12a/echo=on 2006.218.07:56:27.91$4f8m12a/pcalon 2006.218.07:56:27.91$pcalon/"no phase cal control is implemented here 2006.218.07:56:27.92$4f8m12a/"tpicd=stop 2006.218.07:56:27.92$4f8m12a/vc4f8 2006.218.07:56:27.92$vc4f8/valo=1,532.99 2006.218.07:56:27.92#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.218.07:56:27.92#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.218.07:56:27.92#ibcon#ireg 17 cls_cnt 0 2006.218.07:56:27.92#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.218.07:56:27.92#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.218.07:56:27.92#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.218.07:56:27.92#ibcon#enter wrdev, iclass 19, count 0 2006.218.07:56:27.92#ibcon#first serial, iclass 19, count 0 2006.218.07:56:27.92#ibcon#enter sib2, iclass 19, count 0 2006.218.07:56:27.92#ibcon#flushed, iclass 19, count 0 2006.218.07:56:27.92#ibcon#about to write, iclass 19, count 0 2006.218.07:56:27.92#ibcon#wrote, iclass 19, count 0 2006.218.07:56:27.92#ibcon#about to read 3, iclass 19, count 0 2006.218.07:56:27.93#ibcon#read 3, iclass 19, count 0 2006.218.07:56:27.93#ibcon#about to read 4, iclass 19, count 0 2006.218.07:56:27.93#ibcon#read 4, iclass 19, count 0 2006.218.07:56:27.93#ibcon#about to read 5, iclass 19, count 0 2006.218.07:56:27.93#ibcon#read 5, iclass 19, count 0 2006.218.07:56:27.93#ibcon#about to read 6, iclass 19, count 0 2006.218.07:56:27.93#ibcon#read 6, iclass 19, count 0 2006.218.07:56:27.93#ibcon#end of sib2, iclass 19, count 0 2006.218.07:56:27.93#ibcon#*mode == 0, iclass 19, count 0 2006.218.07:56:27.93#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.218.07:56:27.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.218.07:56:27.93#ibcon#*before write, iclass 19, count 0 2006.218.07:56:27.93#ibcon#enter sib2, iclass 19, count 0 2006.218.07:56:27.93#ibcon#flushed, iclass 19, count 0 2006.218.07:56:27.93#ibcon#about to write, iclass 19, count 0 2006.218.07:56:27.93#ibcon#wrote, iclass 19, count 0 2006.218.07:56:27.93#ibcon#about to read 3, iclass 19, count 0 2006.218.07:56:27.98#ibcon#read 3, iclass 19, count 0 2006.218.07:56:27.98#ibcon#about to read 4, iclass 19, count 0 2006.218.07:56:27.98#ibcon#read 4, iclass 19, count 0 2006.218.07:56:27.98#ibcon#about to read 5, iclass 19, count 0 2006.218.07:56:27.98#ibcon#read 5, iclass 19, count 0 2006.218.07:56:27.98#ibcon#about to read 6, iclass 19, count 0 2006.218.07:56:27.98#ibcon#read 6, iclass 19, count 0 2006.218.07:56:27.98#ibcon#end of sib2, iclass 19, count 0 2006.218.07:56:27.98#ibcon#*after write, iclass 19, count 0 2006.218.07:56:27.98#ibcon#*before return 0, iclass 19, count 0 2006.218.07:56:27.98#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.218.07:56:27.98#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.218.07:56:27.98#ibcon#about to clear, iclass 19 cls_cnt 0 2006.218.07:56:27.98#ibcon#cleared, iclass 19 cls_cnt 0 2006.218.07:56:27.98$vc4f8/va=1,5 2006.218.07:56:27.98#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.218.07:56:27.98#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.218.07:56:27.98#ibcon#ireg 11 cls_cnt 2 2006.218.07:56:27.98#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.218.07:56:27.98#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.218.07:56:27.98#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.218.07:56:27.98#ibcon#enter wrdev, iclass 21, count 2 2006.218.07:56:27.98#ibcon#first serial, iclass 21, count 2 2006.218.07:56:27.98#ibcon#enter sib2, iclass 21, count 2 2006.218.07:56:27.98#ibcon#flushed, iclass 21, count 2 2006.218.07:56:27.98#ibcon#about to write, iclass 21, count 2 2006.218.07:56:27.98#ibcon#wrote, iclass 21, count 2 2006.218.07:56:27.98#ibcon#about to read 3, iclass 21, count 2 2006.218.07:56:28.00#ibcon#read 3, iclass 21, count 2 2006.218.07:56:28.00#ibcon#about to read 4, iclass 21, count 2 2006.218.07:56:28.00#ibcon#read 4, iclass 21, count 2 2006.218.07:56:28.00#ibcon#about to read 5, iclass 21, count 2 2006.218.07:56:28.00#ibcon#read 5, iclass 21, count 2 2006.218.07:56:28.00#ibcon#about to read 6, iclass 21, count 2 2006.218.07:56:28.00#ibcon#read 6, iclass 21, count 2 2006.218.07:56:28.00#ibcon#end of sib2, iclass 21, count 2 2006.218.07:56:28.00#ibcon#*mode == 0, iclass 21, count 2 2006.218.07:56:28.00#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.218.07:56:28.00#ibcon#[25=AT01-05\r\n] 2006.218.07:56:28.00#ibcon#*before write, iclass 21, count 2 2006.218.07:56:28.00#ibcon#enter sib2, iclass 21, count 2 2006.218.07:56:28.00#ibcon#flushed, iclass 21, count 2 2006.218.07:56:28.00#ibcon#about to write, iclass 21, count 2 2006.218.07:56:28.00#ibcon#wrote, iclass 21, count 2 2006.218.07:56:28.00#ibcon#about to read 3, iclass 21, count 2 2006.218.07:56:28.04#ibcon#read 3, iclass 21, count 2 2006.218.07:56:28.04#ibcon#about to read 4, iclass 21, count 2 2006.218.07:56:28.04#ibcon#read 4, iclass 21, count 2 2006.218.07:56:28.04#ibcon#about to read 5, iclass 21, count 2 2006.218.07:56:28.04#ibcon#read 5, iclass 21, count 2 2006.218.07:56:28.04#ibcon#about to read 6, iclass 21, count 2 2006.218.07:56:28.04#ibcon#read 6, iclass 21, count 2 2006.218.07:56:28.04#ibcon#end of sib2, iclass 21, count 2 2006.218.07:56:28.04#ibcon#*after write, iclass 21, count 2 2006.218.07:56:28.04#ibcon#*before return 0, iclass 21, count 2 2006.218.07:56:28.04#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.218.07:56:28.04#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.218.07:56:28.04#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.218.07:56:28.04#ibcon#ireg 7 cls_cnt 0 2006.218.07:56:28.04#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.218.07:56:28.15#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.218.07:56:28.15#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.218.07:56:28.15#ibcon#enter wrdev, iclass 21, count 0 2006.218.07:56:28.15#ibcon#first serial, iclass 21, count 0 2006.218.07:56:28.15#ibcon#enter sib2, iclass 21, count 0 2006.218.07:56:28.15#ibcon#flushed, iclass 21, count 0 2006.218.07:56:28.15#ibcon#about to write, iclass 21, count 0 2006.218.07:56:28.15#ibcon#wrote, iclass 21, count 0 2006.218.07:56:28.15#ibcon#about to read 3, iclass 21, count 0 2006.218.07:56:28.17#ibcon#read 3, iclass 21, count 0 2006.218.07:56:28.17#ibcon#about to read 4, iclass 21, count 0 2006.218.07:56:28.17#ibcon#read 4, iclass 21, count 0 2006.218.07:56:28.17#ibcon#about to read 5, iclass 21, count 0 2006.218.07:56:28.17#ibcon#read 5, iclass 21, count 0 2006.218.07:56:28.17#ibcon#about to read 6, iclass 21, count 0 2006.218.07:56:28.17#ibcon#read 6, iclass 21, count 0 2006.218.07:56:28.17#ibcon#end of sib2, iclass 21, count 0 2006.218.07:56:28.17#ibcon#*mode == 0, iclass 21, count 0 2006.218.07:56:28.17#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.218.07:56:28.17#ibcon#[25=USB\r\n] 2006.218.07:56:28.17#ibcon#*before write, iclass 21, count 0 2006.218.07:56:28.17#ibcon#enter sib2, iclass 21, count 0 2006.218.07:56:28.17#ibcon#flushed, iclass 21, count 0 2006.218.07:56:28.17#ibcon#about to write, iclass 21, count 0 2006.218.07:56:28.17#ibcon#wrote, iclass 21, count 0 2006.218.07:56:28.17#ibcon#about to read 3, iclass 21, count 0 2006.218.07:56:28.20#ibcon#read 3, iclass 21, count 0 2006.218.07:56:28.20#ibcon#about to read 4, iclass 21, count 0 2006.218.07:56:28.20#ibcon#read 4, iclass 21, count 0 2006.218.07:56:28.20#ibcon#about to read 5, iclass 21, count 0 2006.218.07:56:28.20#ibcon#read 5, iclass 21, count 0 2006.218.07:56:28.20#ibcon#about to read 6, iclass 21, count 0 2006.218.07:56:28.20#ibcon#read 6, iclass 21, count 0 2006.218.07:56:28.20#ibcon#end of sib2, iclass 21, count 0 2006.218.07:56:28.20#ibcon#*after write, iclass 21, count 0 2006.218.07:56:28.20#ibcon#*before return 0, iclass 21, count 0 2006.218.07:56:28.20#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.218.07:56:28.20#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.218.07:56:28.20#ibcon#about to clear, iclass 21 cls_cnt 0 2006.218.07:56:28.20#ibcon#cleared, iclass 21 cls_cnt 0 2006.218.07:56:28.20$vc4f8/valo=2,572.99 2006.218.07:56:28.20#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.218.07:56:28.20#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.218.07:56:28.20#ibcon#ireg 17 cls_cnt 0 2006.218.07:56:28.20#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.218.07:56:28.20#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.218.07:56:28.20#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.218.07:56:28.20#ibcon#enter wrdev, iclass 23, count 0 2006.218.07:56:28.20#ibcon#first serial, iclass 23, count 0 2006.218.07:56:28.20#ibcon#enter sib2, iclass 23, count 0 2006.218.07:56:28.20#ibcon#flushed, iclass 23, count 0 2006.218.07:56:28.20#ibcon#about to write, iclass 23, count 0 2006.218.07:56:28.20#ibcon#wrote, iclass 23, count 0 2006.218.07:56:28.20#ibcon#about to read 3, iclass 23, count 0 2006.218.07:56:28.23#ibcon#read 3, iclass 23, count 0 2006.218.07:56:28.23#ibcon#about to read 4, iclass 23, count 0 2006.218.07:56:28.23#ibcon#read 4, iclass 23, count 0 2006.218.07:56:28.23#ibcon#about to read 5, iclass 23, count 0 2006.218.07:56:28.23#ibcon#read 5, iclass 23, count 0 2006.218.07:56:28.23#ibcon#about to read 6, iclass 23, count 0 2006.218.07:56:28.23#ibcon#read 6, iclass 23, count 0 2006.218.07:56:28.23#ibcon#end of sib2, iclass 23, count 0 2006.218.07:56:28.23#ibcon#*mode == 0, iclass 23, count 0 2006.218.07:56:28.23#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.218.07:56:28.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.218.07:56:28.23#ibcon#*before write, iclass 23, count 0 2006.218.07:56:28.23#ibcon#enter sib2, iclass 23, count 0 2006.218.07:56:28.23#ibcon#flushed, iclass 23, count 0 2006.218.07:56:28.23#ibcon#about to write, iclass 23, count 0 2006.218.07:56:28.23#ibcon#wrote, iclass 23, count 0 2006.218.07:56:28.23#ibcon#about to read 3, iclass 23, count 0 2006.218.07:56:28.27#ibcon#read 3, iclass 23, count 0 2006.218.07:56:28.27#ibcon#about to read 4, iclass 23, count 0 2006.218.07:56:28.27#ibcon#read 4, iclass 23, count 0 2006.218.07:56:28.27#ibcon#about to read 5, iclass 23, count 0 2006.218.07:56:28.27#ibcon#read 5, iclass 23, count 0 2006.218.07:56:28.27#ibcon#about to read 6, iclass 23, count 0 2006.218.07:56:28.27#ibcon#read 6, iclass 23, count 0 2006.218.07:56:28.27#ibcon#end of sib2, iclass 23, count 0 2006.218.07:56:28.27#ibcon#*after write, iclass 23, count 0 2006.218.07:56:28.27#ibcon#*before return 0, iclass 23, count 0 2006.218.07:56:28.27#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.218.07:56:28.27#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.218.07:56:28.27#ibcon#about to clear, iclass 23 cls_cnt 0 2006.218.07:56:28.27#ibcon#cleared, iclass 23 cls_cnt 0 2006.218.07:56:28.27$vc4f8/va=2,4 2006.218.07:56:28.27#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.218.07:56:28.27#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.218.07:56:28.27#ibcon#ireg 11 cls_cnt 2 2006.218.07:56:28.27#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.218.07:56:28.32#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.218.07:56:28.32#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.218.07:56:28.32#ibcon#enter wrdev, iclass 25, count 2 2006.218.07:56:28.32#ibcon#first serial, iclass 25, count 2 2006.218.07:56:28.32#ibcon#enter sib2, iclass 25, count 2 2006.218.07:56:28.32#ibcon#flushed, iclass 25, count 2 2006.218.07:56:28.32#ibcon#about to write, iclass 25, count 2 2006.218.07:56:28.32#ibcon#wrote, iclass 25, count 2 2006.218.07:56:28.32#ibcon#about to read 3, iclass 25, count 2 2006.218.07:56:28.34#ibcon#read 3, iclass 25, count 2 2006.218.07:56:28.34#ibcon#about to read 4, iclass 25, count 2 2006.218.07:56:28.34#ibcon#read 4, iclass 25, count 2 2006.218.07:56:28.34#ibcon#about to read 5, iclass 25, count 2 2006.218.07:56:28.34#ibcon#read 5, iclass 25, count 2 2006.218.07:56:28.34#ibcon#about to read 6, iclass 25, count 2 2006.218.07:56:28.34#ibcon#read 6, iclass 25, count 2 2006.218.07:56:28.34#ibcon#end of sib2, iclass 25, count 2 2006.218.07:56:28.34#ibcon#*mode == 0, iclass 25, count 2 2006.218.07:56:28.34#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.218.07:56:28.34#ibcon#[25=AT02-04\r\n] 2006.218.07:56:28.34#ibcon#*before write, iclass 25, count 2 2006.218.07:56:28.34#ibcon#enter sib2, iclass 25, count 2 2006.218.07:56:28.34#ibcon#flushed, iclass 25, count 2 2006.218.07:56:28.34#ibcon#about to write, iclass 25, count 2 2006.218.07:56:28.34#ibcon#wrote, iclass 25, count 2 2006.218.07:56:28.34#ibcon#about to read 3, iclass 25, count 2 2006.218.07:56:28.37#ibcon#read 3, iclass 25, count 2 2006.218.07:56:28.37#ibcon#about to read 4, iclass 25, count 2 2006.218.07:56:28.37#ibcon#read 4, iclass 25, count 2 2006.218.07:56:28.37#ibcon#about to read 5, iclass 25, count 2 2006.218.07:56:28.37#ibcon#read 5, iclass 25, count 2 2006.218.07:56:28.37#ibcon#about to read 6, iclass 25, count 2 2006.218.07:56:28.37#ibcon#read 6, iclass 25, count 2 2006.218.07:56:28.37#ibcon#end of sib2, iclass 25, count 2 2006.218.07:56:28.37#ibcon#*after write, iclass 25, count 2 2006.218.07:56:28.37#ibcon#*before return 0, iclass 25, count 2 2006.218.07:56:28.37#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.218.07:56:28.37#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.218.07:56:28.37#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.218.07:56:28.37#ibcon#ireg 7 cls_cnt 0 2006.218.07:56:28.37#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.218.07:56:28.49#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.218.07:56:28.49#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.218.07:56:28.49#ibcon#enter wrdev, iclass 25, count 0 2006.218.07:56:28.49#ibcon#first serial, iclass 25, count 0 2006.218.07:56:28.49#ibcon#enter sib2, iclass 25, count 0 2006.218.07:56:28.49#ibcon#flushed, iclass 25, count 0 2006.218.07:56:28.49#ibcon#about to write, iclass 25, count 0 2006.218.07:56:28.49#ibcon#wrote, iclass 25, count 0 2006.218.07:56:28.49#ibcon#about to read 3, iclass 25, count 0 2006.218.07:56:28.51#ibcon#read 3, iclass 25, count 0 2006.218.07:56:28.51#ibcon#about to read 4, iclass 25, count 0 2006.218.07:56:28.51#ibcon#read 4, iclass 25, count 0 2006.218.07:56:28.51#ibcon#about to read 5, iclass 25, count 0 2006.218.07:56:28.51#ibcon#read 5, iclass 25, count 0 2006.218.07:56:28.51#ibcon#about to read 6, iclass 25, count 0 2006.218.07:56:28.51#ibcon#read 6, iclass 25, count 0 2006.218.07:56:28.51#ibcon#end of sib2, iclass 25, count 0 2006.218.07:56:28.51#ibcon#*mode == 0, iclass 25, count 0 2006.218.07:56:28.51#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.218.07:56:28.51#ibcon#[25=USB\r\n] 2006.218.07:56:28.51#ibcon#*before write, iclass 25, count 0 2006.218.07:56:28.51#ibcon#enter sib2, iclass 25, count 0 2006.218.07:56:28.51#ibcon#flushed, iclass 25, count 0 2006.218.07:56:28.51#ibcon#about to write, iclass 25, count 0 2006.218.07:56:28.51#ibcon#wrote, iclass 25, count 0 2006.218.07:56:28.51#ibcon#about to read 3, iclass 25, count 0 2006.218.07:56:28.54#ibcon#read 3, iclass 25, count 0 2006.218.07:56:28.54#ibcon#about to read 4, iclass 25, count 0 2006.218.07:56:28.54#ibcon#read 4, iclass 25, count 0 2006.218.07:56:28.54#ibcon#about to read 5, iclass 25, count 0 2006.218.07:56:28.54#ibcon#read 5, iclass 25, count 0 2006.218.07:56:28.54#ibcon#about to read 6, iclass 25, count 0 2006.218.07:56:28.54#ibcon#read 6, iclass 25, count 0 2006.218.07:56:28.54#ibcon#end of sib2, iclass 25, count 0 2006.218.07:56:28.54#ibcon#*after write, iclass 25, count 0 2006.218.07:56:28.54#ibcon#*before return 0, iclass 25, count 0 2006.218.07:56:28.54#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.218.07:56:28.54#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.218.07:56:28.54#ibcon#about to clear, iclass 25 cls_cnt 0 2006.218.07:56:28.54#ibcon#cleared, iclass 25 cls_cnt 0 2006.218.07:56:28.54$vc4f8/valo=3,672.99 2006.218.07:56:28.54#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.218.07:56:28.54#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.218.07:56:28.54#ibcon#ireg 17 cls_cnt 0 2006.218.07:56:28.54#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.218.07:56:28.54#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.218.07:56:28.54#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.218.07:56:28.54#ibcon#enter wrdev, iclass 27, count 0 2006.218.07:56:28.54#ibcon#first serial, iclass 27, count 0 2006.218.07:56:28.54#ibcon#enter sib2, iclass 27, count 0 2006.218.07:56:28.54#ibcon#flushed, iclass 27, count 0 2006.218.07:56:28.54#ibcon#about to write, iclass 27, count 0 2006.218.07:56:28.54#ibcon#wrote, iclass 27, count 0 2006.218.07:56:28.54#ibcon#about to read 3, iclass 27, count 0 2006.218.07:56:28.57#ibcon#read 3, iclass 27, count 0 2006.218.07:56:28.57#ibcon#about to read 4, iclass 27, count 0 2006.218.07:56:28.57#ibcon#read 4, iclass 27, count 0 2006.218.07:56:28.57#ibcon#about to read 5, iclass 27, count 0 2006.218.07:56:28.57#ibcon#read 5, iclass 27, count 0 2006.218.07:56:28.57#ibcon#about to read 6, iclass 27, count 0 2006.218.07:56:28.57#ibcon#read 6, iclass 27, count 0 2006.218.07:56:28.57#ibcon#end of sib2, iclass 27, count 0 2006.218.07:56:28.57#ibcon#*mode == 0, iclass 27, count 0 2006.218.07:56:28.57#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.218.07:56:28.57#ibcon#[26=FRQ=03,672.99\r\n] 2006.218.07:56:28.57#ibcon#*before write, iclass 27, count 0 2006.218.07:56:28.57#ibcon#enter sib2, iclass 27, count 0 2006.218.07:56:28.57#ibcon#flushed, iclass 27, count 0 2006.218.07:56:28.57#ibcon#about to write, iclass 27, count 0 2006.218.07:56:28.57#ibcon#wrote, iclass 27, count 0 2006.218.07:56:28.57#ibcon#about to read 3, iclass 27, count 0 2006.218.07:56:28.61#ibcon#read 3, iclass 27, count 0 2006.218.07:56:28.61#ibcon#about to read 4, iclass 27, count 0 2006.218.07:56:28.61#ibcon#read 4, iclass 27, count 0 2006.218.07:56:28.61#ibcon#about to read 5, iclass 27, count 0 2006.218.07:56:28.61#ibcon#read 5, iclass 27, count 0 2006.218.07:56:28.61#ibcon#about to read 6, iclass 27, count 0 2006.218.07:56:28.61#ibcon#read 6, iclass 27, count 0 2006.218.07:56:28.61#ibcon#end of sib2, iclass 27, count 0 2006.218.07:56:28.61#ibcon#*after write, iclass 27, count 0 2006.218.07:56:28.61#ibcon#*before return 0, iclass 27, count 0 2006.218.07:56:28.61#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.218.07:56:28.61#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.218.07:56:28.61#ibcon#about to clear, iclass 27 cls_cnt 0 2006.218.07:56:28.61#ibcon#cleared, iclass 27 cls_cnt 0 2006.218.07:56:28.61$vc4f8/va=3,4 2006.218.07:56:28.61#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.218.07:56:28.61#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.218.07:56:28.61#ibcon#ireg 11 cls_cnt 2 2006.218.07:56:28.61#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.218.07:56:28.66#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.218.07:56:28.66#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.218.07:56:28.66#ibcon#enter wrdev, iclass 29, count 2 2006.218.07:56:28.66#ibcon#first serial, iclass 29, count 2 2006.218.07:56:28.66#ibcon#enter sib2, iclass 29, count 2 2006.218.07:56:28.66#ibcon#flushed, iclass 29, count 2 2006.218.07:56:28.66#ibcon#about to write, iclass 29, count 2 2006.218.07:56:28.66#ibcon#wrote, iclass 29, count 2 2006.218.07:56:28.66#ibcon#about to read 3, iclass 29, count 2 2006.218.07:56:28.68#ibcon#read 3, iclass 29, count 2 2006.218.07:56:28.68#ibcon#about to read 4, iclass 29, count 2 2006.218.07:56:28.68#ibcon#read 4, iclass 29, count 2 2006.218.07:56:28.68#ibcon#about to read 5, iclass 29, count 2 2006.218.07:56:28.68#ibcon#read 5, iclass 29, count 2 2006.218.07:56:28.68#ibcon#about to read 6, iclass 29, count 2 2006.218.07:56:28.68#ibcon#read 6, iclass 29, count 2 2006.218.07:56:28.68#ibcon#end of sib2, iclass 29, count 2 2006.218.07:56:28.68#ibcon#*mode == 0, iclass 29, count 2 2006.218.07:56:28.68#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.218.07:56:28.68#ibcon#[25=AT03-04\r\n] 2006.218.07:56:28.68#ibcon#*before write, iclass 29, count 2 2006.218.07:56:28.68#ibcon#enter sib2, iclass 29, count 2 2006.218.07:56:28.68#ibcon#flushed, iclass 29, count 2 2006.218.07:56:28.68#ibcon#about to write, iclass 29, count 2 2006.218.07:56:28.68#ibcon#wrote, iclass 29, count 2 2006.218.07:56:28.68#ibcon#about to read 3, iclass 29, count 2 2006.218.07:56:28.71#ibcon#read 3, iclass 29, count 2 2006.218.07:56:28.71#ibcon#about to read 4, iclass 29, count 2 2006.218.07:56:28.71#ibcon#read 4, iclass 29, count 2 2006.218.07:56:28.71#ibcon#about to read 5, iclass 29, count 2 2006.218.07:56:28.71#ibcon#read 5, iclass 29, count 2 2006.218.07:56:28.71#ibcon#about to read 6, iclass 29, count 2 2006.218.07:56:28.71#ibcon#read 6, iclass 29, count 2 2006.218.07:56:28.71#ibcon#end of sib2, iclass 29, count 2 2006.218.07:56:28.71#ibcon#*after write, iclass 29, count 2 2006.218.07:56:28.71#ibcon#*before return 0, iclass 29, count 2 2006.218.07:56:28.71#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.218.07:56:28.71#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.218.07:56:28.71#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.218.07:56:28.71#ibcon#ireg 7 cls_cnt 0 2006.218.07:56:28.71#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.218.07:56:28.83#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.218.07:56:28.83#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.218.07:56:28.83#ibcon#enter wrdev, iclass 29, count 0 2006.218.07:56:28.83#ibcon#first serial, iclass 29, count 0 2006.218.07:56:28.83#ibcon#enter sib2, iclass 29, count 0 2006.218.07:56:28.83#ibcon#flushed, iclass 29, count 0 2006.218.07:56:28.83#ibcon#about to write, iclass 29, count 0 2006.218.07:56:28.83#ibcon#wrote, iclass 29, count 0 2006.218.07:56:28.83#ibcon#about to read 3, iclass 29, count 0 2006.218.07:56:28.85#ibcon#read 3, iclass 29, count 0 2006.218.07:56:28.85#ibcon#about to read 4, iclass 29, count 0 2006.218.07:56:28.85#ibcon#read 4, iclass 29, count 0 2006.218.07:56:28.85#ibcon#about to read 5, iclass 29, count 0 2006.218.07:56:28.85#ibcon#read 5, iclass 29, count 0 2006.218.07:56:28.85#ibcon#about to read 6, iclass 29, count 0 2006.218.07:56:28.85#ibcon#read 6, iclass 29, count 0 2006.218.07:56:28.85#ibcon#end of sib2, iclass 29, count 0 2006.218.07:56:28.85#ibcon#*mode == 0, iclass 29, count 0 2006.218.07:56:28.85#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.218.07:56:28.85#ibcon#[25=USB\r\n] 2006.218.07:56:28.85#ibcon#*before write, iclass 29, count 0 2006.218.07:56:28.85#ibcon#enter sib2, iclass 29, count 0 2006.218.07:56:28.85#ibcon#flushed, iclass 29, count 0 2006.218.07:56:28.85#ibcon#about to write, iclass 29, count 0 2006.218.07:56:28.85#ibcon#wrote, iclass 29, count 0 2006.218.07:56:28.85#ibcon#about to read 3, iclass 29, count 0 2006.218.07:56:28.88#ibcon#read 3, iclass 29, count 0 2006.218.07:56:28.88#ibcon#about to read 4, iclass 29, count 0 2006.218.07:56:28.88#ibcon#read 4, iclass 29, count 0 2006.218.07:56:28.88#ibcon#about to read 5, iclass 29, count 0 2006.218.07:56:28.88#ibcon#read 5, iclass 29, count 0 2006.218.07:56:28.88#ibcon#about to read 6, iclass 29, count 0 2006.218.07:56:28.88#ibcon#read 6, iclass 29, count 0 2006.218.07:56:28.88#ibcon#end of sib2, iclass 29, count 0 2006.218.07:56:28.88#ibcon#*after write, iclass 29, count 0 2006.218.07:56:28.88#ibcon#*before return 0, iclass 29, count 0 2006.218.07:56:28.88#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.218.07:56:28.88#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.218.07:56:28.88#ibcon#about to clear, iclass 29 cls_cnt 0 2006.218.07:56:28.88#ibcon#cleared, iclass 29 cls_cnt 0 2006.218.07:56:28.88$vc4f8/valo=4,832.99 2006.218.07:56:28.88#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.218.07:56:28.88#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.218.07:56:28.88#ibcon#ireg 17 cls_cnt 0 2006.218.07:56:28.88#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.218.07:56:28.88#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.218.07:56:28.88#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.218.07:56:28.88#ibcon#enter wrdev, iclass 31, count 0 2006.218.07:56:28.88#ibcon#first serial, iclass 31, count 0 2006.218.07:56:28.88#ibcon#enter sib2, iclass 31, count 0 2006.218.07:56:28.88#ibcon#flushed, iclass 31, count 0 2006.218.07:56:28.88#ibcon#about to write, iclass 31, count 0 2006.218.07:56:28.88#ibcon#wrote, iclass 31, count 0 2006.218.07:56:28.88#ibcon#about to read 3, iclass 31, count 0 2006.218.07:56:28.91#ibcon#read 3, iclass 31, count 0 2006.218.07:56:28.91#ibcon#about to read 4, iclass 31, count 0 2006.218.07:56:28.91#ibcon#read 4, iclass 31, count 0 2006.218.07:56:28.91#ibcon#about to read 5, iclass 31, count 0 2006.218.07:56:28.91#ibcon#read 5, iclass 31, count 0 2006.218.07:56:28.91#ibcon#about to read 6, iclass 31, count 0 2006.218.07:56:28.91#ibcon#read 6, iclass 31, count 0 2006.218.07:56:28.91#ibcon#end of sib2, iclass 31, count 0 2006.218.07:56:28.91#ibcon#*mode == 0, iclass 31, count 0 2006.218.07:56:28.91#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.218.07:56:28.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.218.07:56:28.91#ibcon#*before write, iclass 31, count 0 2006.218.07:56:28.91#ibcon#enter sib2, iclass 31, count 0 2006.218.07:56:28.91#ibcon#flushed, iclass 31, count 0 2006.218.07:56:28.91#ibcon#about to write, iclass 31, count 0 2006.218.07:56:28.91#ibcon#wrote, iclass 31, count 0 2006.218.07:56:28.91#ibcon#about to read 3, iclass 31, count 0 2006.218.07:56:28.95#ibcon#read 3, iclass 31, count 0 2006.218.07:56:28.95#ibcon#about to read 4, iclass 31, count 0 2006.218.07:56:28.95#ibcon#read 4, iclass 31, count 0 2006.218.07:56:28.95#ibcon#about to read 5, iclass 31, count 0 2006.218.07:56:28.95#ibcon#read 5, iclass 31, count 0 2006.218.07:56:28.95#ibcon#about to read 6, iclass 31, count 0 2006.218.07:56:28.95#ibcon#read 6, iclass 31, count 0 2006.218.07:56:28.95#ibcon#end of sib2, iclass 31, count 0 2006.218.07:56:28.95#ibcon#*after write, iclass 31, count 0 2006.218.07:56:28.95#ibcon#*before return 0, iclass 31, count 0 2006.218.07:56:28.95#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.218.07:56:28.95#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.218.07:56:28.95#ibcon#about to clear, iclass 31 cls_cnt 0 2006.218.07:56:28.95#ibcon#cleared, iclass 31 cls_cnt 0 2006.218.07:56:28.95$vc4f8/va=4,4 2006.218.07:56:28.95#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.218.07:56:28.95#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.218.07:56:28.95#ibcon#ireg 11 cls_cnt 2 2006.218.07:56:28.95#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.218.07:56:29.00#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.218.07:56:29.00#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.218.07:56:29.00#ibcon#enter wrdev, iclass 33, count 2 2006.218.07:56:29.00#ibcon#first serial, iclass 33, count 2 2006.218.07:56:29.00#ibcon#enter sib2, iclass 33, count 2 2006.218.07:56:29.00#ibcon#flushed, iclass 33, count 2 2006.218.07:56:29.00#ibcon#about to write, iclass 33, count 2 2006.218.07:56:29.00#ibcon#wrote, iclass 33, count 2 2006.218.07:56:29.00#ibcon#about to read 3, iclass 33, count 2 2006.218.07:56:29.02#ibcon#read 3, iclass 33, count 2 2006.218.07:56:29.02#ibcon#about to read 4, iclass 33, count 2 2006.218.07:56:29.02#ibcon#read 4, iclass 33, count 2 2006.218.07:56:29.02#ibcon#about to read 5, iclass 33, count 2 2006.218.07:56:29.02#ibcon#read 5, iclass 33, count 2 2006.218.07:56:29.02#ibcon#about to read 6, iclass 33, count 2 2006.218.07:56:29.02#ibcon#read 6, iclass 33, count 2 2006.218.07:56:29.02#ibcon#end of sib2, iclass 33, count 2 2006.218.07:56:29.02#ibcon#*mode == 0, iclass 33, count 2 2006.218.07:56:29.02#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.218.07:56:29.02#ibcon#[25=AT04-04\r\n] 2006.218.07:56:29.02#ibcon#*before write, iclass 33, count 2 2006.218.07:56:29.02#ibcon#enter sib2, iclass 33, count 2 2006.218.07:56:29.02#ibcon#flushed, iclass 33, count 2 2006.218.07:56:29.02#ibcon#about to write, iclass 33, count 2 2006.218.07:56:29.02#ibcon#wrote, iclass 33, count 2 2006.218.07:56:29.02#ibcon#about to read 3, iclass 33, count 2 2006.218.07:56:29.05#ibcon#read 3, iclass 33, count 2 2006.218.07:56:29.05#ibcon#about to read 4, iclass 33, count 2 2006.218.07:56:29.05#ibcon#read 4, iclass 33, count 2 2006.218.07:56:29.05#ibcon#about to read 5, iclass 33, count 2 2006.218.07:56:29.05#ibcon#read 5, iclass 33, count 2 2006.218.07:56:29.05#ibcon#about to read 6, iclass 33, count 2 2006.218.07:56:29.05#ibcon#read 6, iclass 33, count 2 2006.218.07:56:29.05#ibcon#end of sib2, iclass 33, count 2 2006.218.07:56:29.05#ibcon#*after write, iclass 33, count 2 2006.218.07:56:29.05#ibcon#*before return 0, iclass 33, count 2 2006.218.07:56:29.05#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.218.07:56:29.05#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.218.07:56:29.05#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.218.07:56:29.05#ibcon#ireg 7 cls_cnt 0 2006.218.07:56:29.05#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.218.07:56:29.17#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.218.07:56:29.17#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.218.07:56:29.17#ibcon#enter wrdev, iclass 33, count 0 2006.218.07:56:29.17#ibcon#first serial, iclass 33, count 0 2006.218.07:56:29.17#ibcon#enter sib2, iclass 33, count 0 2006.218.07:56:29.17#ibcon#flushed, iclass 33, count 0 2006.218.07:56:29.17#ibcon#about to write, iclass 33, count 0 2006.218.07:56:29.17#ibcon#wrote, iclass 33, count 0 2006.218.07:56:29.17#ibcon#about to read 3, iclass 33, count 0 2006.218.07:56:29.19#ibcon#read 3, iclass 33, count 0 2006.218.07:56:29.19#ibcon#about to read 4, iclass 33, count 0 2006.218.07:56:29.19#ibcon#read 4, iclass 33, count 0 2006.218.07:56:29.19#ibcon#about to read 5, iclass 33, count 0 2006.218.07:56:29.19#ibcon#read 5, iclass 33, count 0 2006.218.07:56:29.19#ibcon#about to read 6, iclass 33, count 0 2006.218.07:56:29.19#ibcon#read 6, iclass 33, count 0 2006.218.07:56:29.19#ibcon#end of sib2, iclass 33, count 0 2006.218.07:56:29.19#ibcon#*mode == 0, iclass 33, count 0 2006.218.07:56:29.19#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.218.07:56:29.19#ibcon#[25=USB\r\n] 2006.218.07:56:29.19#ibcon#*before write, iclass 33, count 0 2006.218.07:56:29.19#ibcon#enter sib2, iclass 33, count 0 2006.218.07:56:29.19#ibcon#flushed, iclass 33, count 0 2006.218.07:56:29.19#ibcon#about to write, iclass 33, count 0 2006.218.07:56:29.19#ibcon#wrote, iclass 33, count 0 2006.218.07:56:29.19#ibcon#about to read 3, iclass 33, count 0 2006.218.07:56:29.22#ibcon#read 3, iclass 33, count 0 2006.218.07:56:29.22#ibcon#about to read 4, iclass 33, count 0 2006.218.07:56:29.22#ibcon#read 4, iclass 33, count 0 2006.218.07:56:29.22#ibcon#about to read 5, iclass 33, count 0 2006.218.07:56:29.22#ibcon#read 5, iclass 33, count 0 2006.218.07:56:29.22#ibcon#about to read 6, iclass 33, count 0 2006.218.07:56:29.22#ibcon#read 6, iclass 33, count 0 2006.218.07:56:29.22#ibcon#end of sib2, iclass 33, count 0 2006.218.07:56:29.22#ibcon#*after write, iclass 33, count 0 2006.218.07:56:29.22#ibcon#*before return 0, iclass 33, count 0 2006.218.07:56:29.22#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.218.07:56:29.22#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.218.07:56:29.22#ibcon#about to clear, iclass 33 cls_cnt 0 2006.218.07:56:29.22#ibcon#cleared, iclass 33 cls_cnt 0 2006.218.07:56:29.22$vc4f8/valo=5,652.99 2006.218.07:56:29.22#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.218.07:56:29.22#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.218.07:56:29.22#ibcon#ireg 17 cls_cnt 0 2006.218.07:56:29.22#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.218.07:56:29.22#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.218.07:56:29.22#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.218.07:56:29.22#ibcon#enter wrdev, iclass 35, count 0 2006.218.07:56:29.22#ibcon#first serial, iclass 35, count 0 2006.218.07:56:29.22#ibcon#enter sib2, iclass 35, count 0 2006.218.07:56:29.22#ibcon#flushed, iclass 35, count 0 2006.218.07:56:29.22#ibcon#about to write, iclass 35, count 0 2006.218.07:56:29.22#ibcon#wrote, iclass 35, count 0 2006.218.07:56:29.22#ibcon#about to read 3, iclass 35, count 0 2006.218.07:56:29.24#ibcon#read 3, iclass 35, count 0 2006.218.07:56:29.24#ibcon#about to read 4, iclass 35, count 0 2006.218.07:56:29.24#ibcon#read 4, iclass 35, count 0 2006.218.07:56:29.24#ibcon#about to read 5, iclass 35, count 0 2006.218.07:56:29.24#ibcon#read 5, iclass 35, count 0 2006.218.07:56:29.24#ibcon#about to read 6, iclass 35, count 0 2006.218.07:56:29.24#ibcon#read 6, iclass 35, count 0 2006.218.07:56:29.24#ibcon#end of sib2, iclass 35, count 0 2006.218.07:56:29.24#ibcon#*mode == 0, iclass 35, count 0 2006.218.07:56:29.24#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.218.07:56:29.24#ibcon#[26=FRQ=05,652.99\r\n] 2006.218.07:56:29.24#ibcon#*before write, iclass 35, count 0 2006.218.07:56:29.24#ibcon#enter sib2, iclass 35, count 0 2006.218.07:56:29.24#ibcon#flushed, iclass 35, count 0 2006.218.07:56:29.24#ibcon#about to write, iclass 35, count 0 2006.218.07:56:29.24#ibcon#wrote, iclass 35, count 0 2006.218.07:56:29.24#ibcon#about to read 3, iclass 35, count 0 2006.218.07:56:29.28#ibcon#read 3, iclass 35, count 0 2006.218.07:56:29.28#ibcon#about to read 4, iclass 35, count 0 2006.218.07:56:29.28#ibcon#read 4, iclass 35, count 0 2006.218.07:56:29.28#ibcon#about to read 5, iclass 35, count 0 2006.218.07:56:29.28#ibcon#read 5, iclass 35, count 0 2006.218.07:56:29.28#ibcon#about to read 6, iclass 35, count 0 2006.218.07:56:29.28#ibcon#read 6, iclass 35, count 0 2006.218.07:56:29.28#ibcon#end of sib2, iclass 35, count 0 2006.218.07:56:29.28#ibcon#*after write, iclass 35, count 0 2006.218.07:56:29.28#ibcon#*before return 0, iclass 35, count 0 2006.218.07:56:29.28#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.218.07:56:29.28#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.218.07:56:29.28#ibcon#about to clear, iclass 35 cls_cnt 0 2006.218.07:56:29.28#ibcon#cleared, iclass 35 cls_cnt 0 2006.218.07:56:29.28$vc4f8/va=5,7 2006.218.07:56:29.28#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.218.07:56:29.28#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.218.07:56:29.28#ibcon#ireg 11 cls_cnt 2 2006.218.07:56:29.28#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.218.07:56:29.34#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.218.07:56:29.34#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.218.07:56:29.34#ibcon#enter wrdev, iclass 37, count 2 2006.218.07:56:29.34#ibcon#first serial, iclass 37, count 2 2006.218.07:56:29.34#ibcon#enter sib2, iclass 37, count 2 2006.218.07:56:29.34#ibcon#flushed, iclass 37, count 2 2006.218.07:56:29.34#ibcon#about to write, iclass 37, count 2 2006.218.07:56:29.34#ibcon#wrote, iclass 37, count 2 2006.218.07:56:29.34#ibcon#about to read 3, iclass 37, count 2 2006.218.07:56:29.36#ibcon#read 3, iclass 37, count 2 2006.218.07:56:29.36#ibcon#about to read 4, iclass 37, count 2 2006.218.07:56:29.36#ibcon#read 4, iclass 37, count 2 2006.218.07:56:29.36#ibcon#about to read 5, iclass 37, count 2 2006.218.07:56:29.36#ibcon#read 5, iclass 37, count 2 2006.218.07:56:29.36#ibcon#about to read 6, iclass 37, count 2 2006.218.07:56:29.36#ibcon#read 6, iclass 37, count 2 2006.218.07:56:29.36#ibcon#end of sib2, iclass 37, count 2 2006.218.07:56:29.36#ibcon#*mode == 0, iclass 37, count 2 2006.218.07:56:29.36#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.218.07:56:29.36#ibcon#[25=AT05-07\r\n] 2006.218.07:56:29.36#ibcon#*before write, iclass 37, count 2 2006.218.07:56:29.36#ibcon#enter sib2, iclass 37, count 2 2006.218.07:56:29.36#ibcon#flushed, iclass 37, count 2 2006.218.07:56:29.36#ibcon#about to write, iclass 37, count 2 2006.218.07:56:29.36#ibcon#wrote, iclass 37, count 2 2006.218.07:56:29.36#ibcon#about to read 3, iclass 37, count 2 2006.218.07:56:29.39#ibcon#read 3, iclass 37, count 2 2006.218.07:56:29.39#ibcon#about to read 4, iclass 37, count 2 2006.218.07:56:29.39#ibcon#read 4, iclass 37, count 2 2006.218.07:56:29.39#ibcon#about to read 5, iclass 37, count 2 2006.218.07:56:29.39#ibcon#read 5, iclass 37, count 2 2006.218.07:56:29.39#ibcon#about to read 6, iclass 37, count 2 2006.218.07:56:29.39#ibcon#read 6, iclass 37, count 2 2006.218.07:56:29.39#ibcon#end of sib2, iclass 37, count 2 2006.218.07:56:29.39#ibcon#*after write, iclass 37, count 2 2006.218.07:56:29.39#ibcon#*before return 0, iclass 37, count 2 2006.218.07:56:29.39#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.218.07:56:29.39#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.218.07:56:29.39#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.218.07:56:29.39#ibcon#ireg 7 cls_cnt 0 2006.218.07:56:29.39#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.218.07:56:29.51#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.218.07:56:29.51#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.218.07:56:29.51#ibcon#enter wrdev, iclass 37, count 0 2006.218.07:56:29.51#ibcon#first serial, iclass 37, count 0 2006.218.07:56:29.51#ibcon#enter sib2, iclass 37, count 0 2006.218.07:56:29.51#ibcon#flushed, iclass 37, count 0 2006.218.07:56:29.51#ibcon#about to write, iclass 37, count 0 2006.218.07:56:29.51#ibcon#wrote, iclass 37, count 0 2006.218.07:56:29.51#ibcon#about to read 3, iclass 37, count 0 2006.218.07:56:29.53#ibcon#read 3, iclass 37, count 0 2006.218.07:56:29.53#ibcon#about to read 4, iclass 37, count 0 2006.218.07:56:29.53#ibcon#read 4, iclass 37, count 0 2006.218.07:56:29.53#ibcon#about to read 5, iclass 37, count 0 2006.218.07:56:29.53#ibcon#read 5, iclass 37, count 0 2006.218.07:56:29.53#ibcon#about to read 6, iclass 37, count 0 2006.218.07:56:29.53#ibcon#read 6, iclass 37, count 0 2006.218.07:56:29.53#ibcon#end of sib2, iclass 37, count 0 2006.218.07:56:29.53#ibcon#*mode == 0, iclass 37, count 0 2006.218.07:56:29.53#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.218.07:56:29.53#ibcon#[25=USB\r\n] 2006.218.07:56:29.53#ibcon#*before write, iclass 37, count 0 2006.218.07:56:29.53#ibcon#enter sib2, iclass 37, count 0 2006.218.07:56:29.53#ibcon#flushed, iclass 37, count 0 2006.218.07:56:29.53#ibcon#about to write, iclass 37, count 0 2006.218.07:56:29.53#ibcon#wrote, iclass 37, count 0 2006.218.07:56:29.53#ibcon#about to read 3, iclass 37, count 0 2006.218.07:56:29.56#ibcon#read 3, iclass 37, count 0 2006.218.07:56:29.56#ibcon#about to read 4, iclass 37, count 0 2006.218.07:56:29.56#ibcon#read 4, iclass 37, count 0 2006.218.07:56:29.56#ibcon#about to read 5, iclass 37, count 0 2006.218.07:56:29.56#ibcon#read 5, iclass 37, count 0 2006.218.07:56:29.56#ibcon#about to read 6, iclass 37, count 0 2006.218.07:56:29.56#ibcon#read 6, iclass 37, count 0 2006.218.07:56:29.56#ibcon#end of sib2, iclass 37, count 0 2006.218.07:56:29.56#ibcon#*after write, iclass 37, count 0 2006.218.07:56:29.56#ibcon#*before return 0, iclass 37, count 0 2006.218.07:56:29.56#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.218.07:56:29.56#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.218.07:56:29.56#ibcon#about to clear, iclass 37 cls_cnt 0 2006.218.07:56:29.56#ibcon#cleared, iclass 37 cls_cnt 0 2006.218.07:56:29.56$vc4f8/valo=6,772.99 2006.218.07:56:29.56#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.218.07:56:29.56#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.218.07:56:29.56#ibcon#ireg 17 cls_cnt 0 2006.218.07:56:29.56#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.218.07:56:29.56#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.218.07:56:29.56#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.218.07:56:29.56#ibcon#enter wrdev, iclass 39, count 0 2006.218.07:56:29.56#ibcon#first serial, iclass 39, count 0 2006.218.07:56:29.56#ibcon#enter sib2, iclass 39, count 0 2006.218.07:56:29.56#ibcon#flushed, iclass 39, count 0 2006.218.07:56:29.56#ibcon#about to write, iclass 39, count 0 2006.218.07:56:29.56#ibcon#wrote, iclass 39, count 0 2006.218.07:56:29.56#ibcon#about to read 3, iclass 39, count 0 2006.218.07:56:29.58#ibcon#read 3, iclass 39, count 0 2006.218.07:56:29.58#ibcon#about to read 4, iclass 39, count 0 2006.218.07:56:29.58#ibcon#read 4, iclass 39, count 0 2006.218.07:56:29.58#ibcon#about to read 5, iclass 39, count 0 2006.218.07:56:29.58#ibcon#read 5, iclass 39, count 0 2006.218.07:56:29.58#ibcon#about to read 6, iclass 39, count 0 2006.218.07:56:29.58#ibcon#read 6, iclass 39, count 0 2006.218.07:56:29.58#ibcon#end of sib2, iclass 39, count 0 2006.218.07:56:29.58#ibcon#*mode == 0, iclass 39, count 0 2006.218.07:56:29.58#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.218.07:56:29.58#ibcon#[26=FRQ=06,772.99\r\n] 2006.218.07:56:29.58#ibcon#*before write, iclass 39, count 0 2006.218.07:56:29.58#ibcon#enter sib2, iclass 39, count 0 2006.218.07:56:29.58#ibcon#flushed, iclass 39, count 0 2006.218.07:56:29.58#ibcon#about to write, iclass 39, count 0 2006.218.07:56:29.58#ibcon#wrote, iclass 39, count 0 2006.218.07:56:29.58#ibcon#about to read 3, iclass 39, count 0 2006.218.07:56:29.62#ibcon#read 3, iclass 39, count 0 2006.218.07:56:29.62#ibcon#about to read 4, iclass 39, count 0 2006.218.07:56:29.62#ibcon#read 4, iclass 39, count 0 2006.218.07:56:29.62#ibcon#about to read 5, iclass 39, count 0 2006.218.07:56:29.62#ibcon#read 5, iclass 39, count 0 2006.218.07:56:29.62#ibcon#about to read 6, iclass 39, count 0 2006.218.07:56:29.62#ibcon#read 6, iclass 39, count 0 2006.218.07:56:29.62#ibcon#end of sib2, iclass 39, count 0 2006.218.07:56:29.62#ibcon#*after write, iclass 39, count 0 2006.218.07:56:29.62#ibcon#*before return 0, iclass 39, count 0 2006.218.07:56:29.62#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.218.07:56:29.62#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.218.07:56:29.62#ibcon#about to clear, iclass 39 cls_cnt 0 2006.218.07:56:29.62#ibcon#cleared, iclass 39 cls_cnt 0 2006.218.07:56:29.62$vc4f8/va=6,6 2006.218.07:56:29.62#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.218.07:56:29.62#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.218.07:56:29.62#ibcon#ireg 11 cls_cnt 2 2006.218.07:56:29.62#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.218.07:56:29.68#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.218.07:56:29.68#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.218.07:56:29.68#ibcon#enter wrdev, iclass 3, count 2 2006.218.07:56:29.68#ibcon#first serial, iclass 3, count 2 2006.218.07:56:29.68#ibcon#enter sib2, iclass 3, count 2 2006.218.07:56:29.68#ibcon#flushed, iclass 3, count 2 2006.218.07:56:29.68#ibcon#about to write, iclass 3, count 2 2006.218.07:56:29.68#ibcon#wrote, iclass 3, count 2 2006.218.07:56:29.68#ibcon#about to read 3, iclass 3, count 2 2006.218.07:56:29.70#ibcon#read 3, iclass 3, count 2 2006.218.07:56:29.70#ibcon#about to read 4, iclass 3, count 2 2006.218.07:56:29.70#ibcon#read 4, iclass 3, count 2 2006.218.07:56:29.70#ibcon#about to read 5, iclass 3, count 2 2006.218.07:56:29.70#ibcon#read 5, iclass 3, count 2 2006.218.07:56:29.70#ibcon#about to read 6, iclass 3, count 2 2006.218.07:56:29.70#ibcon#read 6, iclass 3, count 2 2006.218.07:56:29.70#ibcon#end of sib2, iclass 3, count 2 2006.218.07:56:29.70#ibcon#*mode == 0, iclass 3, count 2 2006.218.07:56:29.70#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.218.07:56:29.70#ibcon#[25=AT06-06\r\n] 2006.218.07:56:29.70#ibcon#*before write, iclass 3, count 2 2006.218.07:56:29.70#ibcon#enter sib2, iclass 3, count 2 2006.218.07:56:29.70#ibcon#flushed, iclass 3, count 2 2006.218.07:56:29.70#ibcon#about to write, iclass 3, count 2 2006.218.07:56:29.70#ibcon#wrote, iclass 3, count 2 2006.218.07:56:29.70#ibcon#about to read 3, iclass 3, count 2 2006.218.07:56:29.73#ibcon#read 3, iclass 3, count 2 2006.218.07:56:29.73#ibcon#about to read 4, iclass 3, count 2 2006.218.07:56:29.73#ibcon#read 4, iclass 3, count 2 2006.218.07:56:29.73#ibcon#about to read 5, iclass 3, count 2 2006.218.07:56:29.73#ibcon#read 5, iclass 3, count 2 2006.218.07:56:29.73#ibcon#about to read 6, iclass 3, count 2 2006.218.07:56:29.73#ibcon#read 6, iclass 3, count 2 2006.218.07:56:29.73#ibcon#end of sib2, iclass 3, count 2 2006.218.07:56:29.73#ibcon#*after write, iclass 3, count 2 2006.218.07:56:29.73#ibcon#*before return 0, iclass 3, count 2 2006.218.07:56:29.73#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.218.07:56:29.73#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.218.07:56:29.73#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.218.07:56:29.73#ibcon#ireg 7 cls_cnt 0 2006.218.07:56:29.73#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.218.07:56:29.85#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.218.07:56:29.85#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.218.07:56:29.85#ibcon#enter wrdev, iclass 3, count 0 2006.218.07:56:29.85#ibcon#first serial, iclass 3, count 0 2006.218.07:56:29.85#ibcon#enter sib2, iclass 3, count 0 2006.218.07:56:29.85#ibcon#flushed, iclass 3, count 0 2006.218.07:56:29.85#ibcon#about to write, iclass 3, count 0 2006.218.07:56:29.85#ibcon#wrote, iclass 3, count 0 2006.218.07:56:29.85#ibcon#about to read 3, iclass 3, count 0 2006.218.07:56:29.87#ibcon#read 3, iclass 3, count 0 2006.218.07:56:29.87#ibcon#about to read 4, iclass 3, count 0 2006.218.07:56:29.87#ibcon#read 4, iclass 3, count 0 2006.218.07:56:29.87#ibcon#about to read 5, iclass 3, count 0 2006.218.07:56:29.87#ibcon#read 5, iclass 3, count 0 2006.218.07:56:29.87#ibcon#about to read 6, iclass 3, count 0 2006.218.07:56:29.87#ibcon#read 6, iclass 3, count 0 2006.218.07:56:29.87#ibcon#end of sib2, iclass 3, count 0 2006.218.07:56:29.87#ibcon#*mode == 0, iclass 3, count 0 2006.218.07:56:29.87#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.218.07:56:29.87#ibcon#[25=USB\r\n] 2006.218.07:56:29.87#ibcon#*before write, iclass 3, count 0 2006.218.07:56:29.87#ibcon#enter sib2, iclass 3, count 0 2006.218.07:56:29.87#ibcon#flushed, iclass 3, count 0 2006.218.07:56:29.87#ibcon#about to write, iclass 3, count 0 2006.218.07:56:29.87#ibcon#wrote, iclass 3, count 0 2006.218.07:56:29.87#ibcon#about to read 3, iclass 3, count 0 2006.218.07:56:29.90#ibcon#read 3, iclass 3, count 0 2006.218.07:56:29.90#ibcon#about to read 4, iclass 3, count 0 2006.218.07:56:29.90#ibcon#read 4, iclass 3, count 0 2006.218.07:56:29.90#ibcon#about to read 5, iclass 3, count 0 2006.218.07:56:29.90#ibcon#read 5, iclass 3, count 0 2006.218.07:56:29.90#ibcon#about to read 6, iclass 3, count 0 2006.218.07:56:29.90#ibcon#read 6, iclass 3, count 0 2006.218.07:56:29.90#ibcon#end of sib2, iclass 3, count 0 2006.218.07:56:29.90#ibcon#*after write, iclass 3, count 0 2006.218.07:56:29.90#ibcon#*before return 0, iclass 3, count 0 2006.218.07:56:29.90#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.218.07:56:29.90#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.218.07:56:29.90#ibcon#about to clear, iclass 3 cls_cnt 0 2006.218.07:56:29.90#ibcon#cleared, iclass 3 cls_cnt 0 2006.218.07:56:29.90$vc4f8/valo=7,832.99 2006.218.07:56:29.90#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.218.07:56:29.90#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.218.07:56:29.90#ibcon#ireg 17 cls_cnt 0 2006.218.07:56:29.90#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.218.07:56:29.90#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.218.07:56:29.90#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.218.07:56:29.90#ibcon#enter wrdev, iclass 5, count 0 2006.218.07:56:29.90#ibcon#first serial, iclass 5, count 0 2006.218.07:56:29.90#ibcon#enter sib2, iclass 5, count 0 2006.218.07:56:29.90#ibcon#flushed, iclass 5, count 0 2006.218.07:56:29.90#ibcon#about to write, iclass 5, count 0 2006.218.07:56:29.90#ibcon#wrote, iclass 5, count 0 2006.218.07:56:29.90#ibcon#about to read 3, iclass 5, count 0 2006.218.07:56:29.92#ibcon#read 3, iclass 5, count 0 2006.218.07:56:29.92#ibcon#about to read 4, iclass 5, count 0 2006.218.07:56:29.92#ibcon#read 4, iclass 5, count 0 2006.218.07:56:29.92#ibcon#about to read 5, iclass 5, count 0 2006.218.07:56:29.92#ibcon#read 5, iclass 5, count 0 2006.218.07:56:29.92#ibcon#about to read 6, iclass 5, count 0 2006.218.07:56:29.92#ibcon#read 6, iclass 5, count 0 2006.218.07:56:29.92#ibcon#end of sib2, iclass 5, count 0 2006.218.07:56:29.92#ibcon#*mode == 0, iclass 5, count 0 2006.218.07:56:29.92#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.218.07:56:29.92#ibcon#[26=FRQ=07,832.99\r\n] 2006.218.07:56:29.92#ibcon#*before write, iclass 5, count 0 2006.218.07:56:29.92#ibcon#enter sib2, iclass 5, count 0 2006.218.07:56:29.92#ibcon#flushed, iclass 5, count 0 2006.218.07:56:29.92#ibcon#about to write, iclass 5, count 0 2006.218.07:56:29.92#ibcon#wrote, iclass 5, count 0 2006.218.07:56:29.92#ibcon#about to read 3, iclass 5, count 0 2006.218.07:56:29.96#ibcon#read 3, iclass 5, count 0 2006.218.07:56:29.96#ibcon#about to read 4, iclass 5, count 0 2006.218.07:56:29.96#ibcon#read 4, iclass 5, count 0 2006.218.07:56:29.96#ibcon#about to read 5, iclass 5, count 0 2006.218.07:56:29.96#ibcon#read 5, iclass 5, count 0 2006.218.07:56:29.96#ibcon#about to read 6, iclass 5, count 0 2006.218.07:56:29.96#ibcon#read 6, iclass 5, count 0 2006.218.07:56:29.96#ibcon#end of sib2, iclass 5, count 0 2006.218.07:56:29.96#ibcon#*after write, iclass 5, count 0 2006.218.07:56:29.96#ibcon#*before return 0, iclass 5, count 0 2006.218.07:56:29.96#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.218.07:56:29.96#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.218.07:56:29.96#ibcon#about to clear, iclass 5 cls_cnt 0 2006.218.07:56:29.96#ibcon#cleared, iclass 5 cls_cnt 0 2006.218.07:56:29.96$vc4f8/va=7,6 2006.218.07:56:29.96#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.218.07:56:29.96#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.218.07:56:29.96#ibcon#ireg 11 cls_cnt 2 2006.218.07:56:29.96#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.218.07:56:30.02#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.218.07:56:30.02#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.218.07:56:30.02#ibcon#enter wrdev, iclass 7, count 2 2006.218.07:56:30.02#ibcon#first serial, iclass 7, count 2 2006.218.07:56:30.02#ibcon#enter sib2, iclass 7, count 2 2006.218.07:56:30.02#ibcon#flushed, iclass 7, count 2 2006.218.07:56:30.02#ibcon#about to write, iclass 7, count 2 2006.218.07:56:30.02#ibcon#wrote, iclass 7, count 2 2006.218.07:56:30.02#ibcon#about to read 3, iclass 7, count 2 2006.218.07:56:30.04#ibcon#read 3, iclass 7, count 2 2006.218.07:56:30.04#ibcon#about to read 4, iclass 7, count 2 2006.218.07:56:30.04#ibcon#read 4, iclass 7, count 2 2006.218.07:56:30.04#ibcon#about to read 5, iclass 7, count 2 2006.218.07:56:30.04#ibcon#read 5, iclass 7, count 2 2006.218.07:56:30.04#ibcon#about to read 6, iclass 7, count 2 2006.218.07:56:30.04#ibcon#read 6, iclass 7, count 2 2006.218.07:56:30.04#ibcon#end of sib2, iclass 7, count 2 2006.218.07:56:30.04#ibcon#*mode == 0, iclass 7, count 2 2006.218.07:56:30.04#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.218.07:56:30.04#ibcon#[25=AT07-06\r\n] 2006.218.07:56:30.04#ibcon#*before write, iclass 7, count 2 2006.218.07:56:30.04#ibcon#enter sib2, iclass 7, count 2 2006.218.07:56:30.04#ibcon#flushed, iclass 7, count 2 2006.218.07:56:30.04#ibcon#about to write, iclass 7, count 2 2006.218.07:56:30.04#ibcon#wrote, iclass 7, count 2 2006.218.07:56:30.04#ibcon#about to read 3, iclass 7, count 2 2006.218.07:56:30.07#ibcon#read 3, iclass 7, count 2 2006.218.07:56:30.07#ibcon#about to read 4, iclass 7, count 2 2006.218.07:56:30.07#ibcon#read 4, iclass 7, count 2 2006.218.07:56:30.07#ibcon#about to read 5, iclass 7, count 2 2006.218.07:56:30.07#ibcon#read 5, iclass 7, count 2 2006.218.07:56:30.07#ibcon#about to read 6, iclass 7, count 2 2006.218.07:56:30.07#ibcon#read 6, iclass 7, count 2 2006.218.07:56:30.07#ibcon#end of sib2, iclass 7, count 2 2006.218.07:56:30.07#ibcon#*after write, iclass 7, count 2 2006.218.07:56:30.07#ibcon#*before return 0, iclass 7, count 2 2006.218.07:56:30.07#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.218.07:56:30.07#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.218.07:56:30.07#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.218.07:56:30.07#ibcon#ireg 7 cls_cnt 0 2006.218.07:56:30.07#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.218.07:56:30.18#abcon#<5=/06 4.3 7.2 31.07 731007.4\r\n> 2006.218.07:56:30.19#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.218.07:56:30.19#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.218.07:56:30.19#ibcon#enter wrdev, iclass 7, count 0 2006.218.07:56:30.19#ibcon#first serial, iclass 7, count 0 2006.218.07:56:30.19#ibcon#enter sib2, iclass 7, count 0 2006.218.07:56:30.19#ibcon#flushed, iclass 7, count 0 2006.218.07:56:30.19#ibcon#about to write, iclass 7, count 0 2006.218.07:56:30.19#ibcon#wrote, iclass 7, count 0 2006.218.07:56:30.19#ibcon#about to read 3, iclass 7, count 0 2006.218.07:56:30.23#ibcon#read 3, iclass 7, count 0 2006.218.07:56:30.23#ibcon#about to read 4, iclass 7, count 0 2006.218.07:56:30.23#ibcon#read 4, iclass 7, count 0 2006.218.07:56:30.23#ibcon#about to read 5, iclass 7, count 0 2006.218.07:56:30.23#ibcon#read 5, iclass 7, count 0 2006.218.07:56:30.23#ibcon#about to read 6, iclass 7, count 0 2006.218.07:56:30.23#ibcon#read 6, iclass 7, count 0 2006.218.07:56:30.23#ibcon#end of sib2, iclass 7, count 0 2006.218.07:56:30.23#ibcon#*mode == 0, iclass 7, count 0 2006.218.07:56:30.23#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.218.07:56:30.23#ibcon#[25=USB\r\n] 2006.218.07:56:30.23#ibcon#*before write, iclass 7, count 0 2006.218.07:56:30.23#ibcon#enter sib2, iclass 7, count 0 2006.218.07:56:30.23#ibcon#flushed, iclass 7, count 0 2006.218.07:56:30.23#ibcon#about to write, iclass 7, count 0 2006.218.07:56:30.23#ibcon#wrote, iclass 7, count 0 2006.218.07:56:30.23#ibcon#about to read 3, iclass 7, count 0 2006.218.07:56:30.23#abcon#{5=INTERFACE CLEAR} 2006.218.07:56:30.25#ibcon#read 3, iclass 7, count 0 2006.218.07:56:30.25#ibcon#about to read 4, iclass 7, count 0 2006.218.07:56:30.25#ibcon#read 4, iclass 7, count 0 2006.218.07:56:30.25#ibcon#about to read 5, iclass 7, count 0 2006.218.07:56:30.25#ibcon#read 5, iclass 7, count 0 2006.218.07:56:30.25#ibcon#about to read 6, iclass 7, count 0 2006.218.07:56:30.25#ibcon#read 6, iclass 7, count 0 2006.218.07:56:30.25#ibcon#end of sib2, iclass 7, count 0 2006.218.07:56:30.25#ibcon#*after write, iclass 7, count 0 2006.218.07:56:30.25#ibcon#*before return 0, iclass 7, count 0 2006.218.07:56:30.25#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.218.07:56:30.25#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.218.07:56:30.25#ibcon#about to clear, iclass 7 cls_cnt 0 2006.218.07:56:30.25#ibcon#cleared, iclass 7 cls_cnt 0 2006.218.07:56:30.25$vc4f8/valo=8,852.99 2006.218.07:56:30.25#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.218.07:56:30.25#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.218.07:56:30.25#ibcon#ireg 17 cls_cnt 0 2006.218.07:56:30.25#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.218.07:56:30.25#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.218.07:56:30.25#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.218.07:56:30.25#ibcon#enter wrdev, iclass 14, count 0 2006.218.07:56:30.25#ibcon#first serial, iclass 14, count 0 2006.218.07:56:30.25#ibcon#enter sib2, iclass 14, count 0 2006.218.07:56:30.25#ibcon#flushed, iclass 14, count 0 2006.218.07:56:30.25#ibcon#about to write, iclass 14, count 0 2006.218.07:56:30.25#ibcon#wrote, iclass 14, count 0 2006.218.07:56:30.25#ibcon#about to read 3, iclass 14, count 0 2006.218.07:56:30.27#ibcon#read 3, iclass 14, count 0 2006.218.07:56:30.27#ibcon#about to read 4, iclass 14, count 0 2006.218.07:56:30.27#ibcon#read 4, iclass 14, count 0 2006.218.07:56:30.27#ibcon#about to read 5, iclass 14, count 0 2006.218.07:56:30.27#ibcon#read 5, iclass 14, count 0 2006.218.07:56:30.27#ibcon#about to read 6, iclass 14, count 0 2006.218.07:56:30.27#ibcon#read 6, iclass 14, count 0 2006.218.07:56:30.27#ibcon#end of sib2, iclass 14, count 0 2006.218.07:56:30.27#ibcon#*mode == 0, iclass 14, count 0 2006.218.07:56:30.27#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.218.07:56:30.27#ibcon#[26=FRQ=08,852.99\r\n] 2006.218.07:56:30.27#ibcon#*before write, iclass 14, count 0 2006.218.07:56:30.27#ibcon#enter sib2, iclass 14, count 0 2006.218.07:56:30.27#ibcon#flushed, iclass 14, count 0 2006.218.07:56:30.27#ibcon#about to write, iclass 14, count 0 2006.218.07:56:30.27#ibcon#wrote, iclass 14, count 0 2006.218.07:56:30.27#ibcon#about to read 3, iclass 14, count 0 2006.218.07:56:30.29#abcon#[5=S1D000X0/0*\r\n] 2006.218.07:56:30.31#ibcon#read 3, iclass 14, count 0 2006.218.07:56:30.31#ibcon#about to read 4, iclass 14, count 0 2006.218.07:56:30.31#ibcon#read 4, iclass 14, count 0 2006.218.07:56:30.31#ibcon#about to read 5, iclass 14, count 0 2006.218.07:56:30.31#ibcon#read 5, iclass 14, count 0 2006.218.07:56:30.31#ibcon#about to read 6, iclass 14, count 0 2006.218.07:56:30.31#ibcon#read 6, iclass 14, count 0 2006.218.07:56:30.31#ibcon#end of sib2, iclass 14, count 0 2006.218.07:56:30.31#ibcon#*after write, iclass 14, count 0 2006.218.07:56:30.31#ibcon#*before return 0, iclass 14, count 0 2006.218.07:56:30.31#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.218.07:56:30.31#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.218.07:56:30.31#ibcon#about to clear, iclass 14 cls_cnt 0 2006.218.07:56:30.31#ibcon#cleared, iclass 14 cls_cnt 0 2006.218.07:56:30.31$vc4f8/va=8,7 2006.218.07:56:30.31#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.218.07:56:30.31#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.218.07:56:30.31#ibcon#ireg 11 cls_cnt 2 2006.218.07:56:30.31#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.218.07:56:30.37#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.218.07:56:30.37#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.218.07:56:30.37#ibcon#enter wrdev, iclass 17, count 2 2006.218.07:56:30.37#ibcon#first serial, iclass 17, count 2 2006.218.07:56:30.37#ibcon#enter sib2, iclass 17, count 2 2006.218.07:56:30.37#ibcon#flushed, iclass 17, count 2 2006.218.07:56:30.37#ibcon#about to write, iclass 17, count 2 2006.218.07:56:30.37#ibcon#wrote, iclass 17, count 2 2006.218.07:56:30.37#ibcon#about to read 3, iclass 17, count 2 2006.218.07:56:30.39#ibcon#read 3, iclass 17, count 2 2006.218.07:56:30.39#ibcon#about to read 4, iclass 17, count 2 2006.218.07:56:30.39#ibcon#read 4, iclass 17, count 2 2006.218.07:56:30.39#ibcon#about to read 5, iclass 17, count 2 2006.218.07:56:30.39#ibcon#read 5, iclass 17, count 2 2006.218.07:56:30.39#ibcon#about to read 6, iclass 17, count 2 2006.218.07:56:30.39#ibcon#read 6, iclass 17, count 2 2006.218.07:56:30.39#ibcon#end of sib2, iclass 17, count 2 2006.218.07:56:30.39#ibcon#*mode == 0, iclass 17, count 2 2006.218.07:56:30.39#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.218.07:56:30.39#ibcon#[25=AT08-07\r\n] 2006.218.07:56:30.39#ibcon#*before write, iclass 17, count 2 2006.218.07:56:30.39#ibcon#enter sib2, iclass 17, count 2 2006.218.07:56:30.39#ibcon#flushed, iclass 17, count 2 2006.218.07:56:30.39#ibcon#about to write, iclass 17, count 2 2006.218.07:56:30.39#ibcon#wrote, iclass 17, count 2 2006.218.07:56:30.39#ibcon#about to read 3, iclass 17, count 2 2006.218.07:56:30.42#ibcon#read 3, iclass 17, count 2 2006.218.07:56:30.42#ibcon#about to read 4, iclass 17, count 2 2006.218.07:56:30.42#ibcon#read 4, iclass 17, count 2 2006.218.07:56:30.42#ibcon#about to read 5, iclass 17, count 2 2006.218.07:56:30.42#ibcon#read 5, iclass 17, count 2 2006.218.07:56:30.42#ibcon#about to read 6, iclass 17, count 2 2006.218.07:56:30.42#ibcon#read 6, iclass 17, count 2 2006.218.07:56:30.42#ibcon#end of sib2, iclass 17, count 2 2006.218.07:56:30.42#ibcon#*after write, iclass 17, count 2 2006.218.07:56:30.42#ibcon#*before return 0, iclass 17, count 2 2006.218.07:56:30.42#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.218.07:56:30.42#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.218.07:56:30.42#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.218.07:56:30.42#ibcon#ireg 7 cls_cnt 0 2006.218.07:56:30.42#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.218.07:56:30.54#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.218.07:56:30.54#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.218.07:56:30.54#ibcon#enter wrdev, iclass 17, count 0 2006.218.07:56:30.54#ibcon#first serial, iclass 17, count 0 2006.218.07:56:30.54#ibcon#enter sib2, iclass 17, count 0 2006.218.07:56:30.54#ibcon#flushed, iclass 17, count 0 2006.218.07:56:30.54#ibcon#about to write, iclass 17, count 0 2006.218.07:56:30.54#ibcon#wrote, iclass 17, count 0 2006.218.07:56:30.54#ibcon#about to read 3, iclass 17, count 0 2006.218.07:56:30.56#ibcon#read 3, iclass 17, count 0 2006.218.07:56:30.56#ibcon#about to read 4, iclass 17, count 0 2006.218.07:56:30.56#ibcon#read 4, iclass 17, count 0 2006.218.07:56:30.56#ibcon#about to read 5, iclass 17, count 0 2006.218.07:56:30.56#ibcon#read 5, iclass 17, count 0 2006.218.07:56:30.56#ibcon#about to read 6, iclass 17, count 0 2006.218.07:56:30.56#ibcon#read 6, iclass 17, count 0 2006.218.07:56:30.56#ibcon#end of sib2, iclass 17, count 0 2006.218.07:56:30.56#ibcon#*mode == 0, iclass 17, count 0 2006.218.07:56:30.56#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.218.07:56:30.56#ibcon#[25=USB\r\n] 2006.218.07:56:30.56#ibcon#*before write, iclass 17, count 0 2006.218.07:56:30.56#ibcon#enter sib2, iclass 17, count 0 2006.218.07:56:30.56#ibcon#flushed, iclass 17, count 0 2006.218.07:56:30.56#ibcon#about to write, iclass 17, count 0 2006.218.07:56:30.56#ibcon#wrote, iclass 17, count 0 2006.218.07:56:30.56#ibcon#about to read 3, iclass 17, count 0 2006.218.07:56:30.59#ibcon#read 3, iclass 17, count 0 2006.218.07:56:30.59#ibcon#about to read 4, iclass 17, count 0 2006.218.07:56:30.59#ibcon#read 4, iclass 17, count 0 2006.218.07:56:30.59#ibcon#about to read 5, iclass 17, count 0 2006.218.07:56:30.59#ibcon#read 5, iclass 17, count 0 2006.218.07:56:30.59#ibcon#about to read 6, iclass 17, count 0 2006.218.07:56:30.59#ibcon#read 6, iclass 17, count 0 2006.218.07:56:30.59#ibcon#end of sib2, iclass 17, count 0 2006.218.07:56:30.59#ibcon#*after write, iclass 17, count 0 2006.218.07:56:30.59#ibcon#*before return 0, iclass 17, count 0 2006.218.07:56:30.59#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.218.07:56:30.59#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.218.07:56:30.59#ibcon#about to clear, iclass 17 cls_cnt 0 2006.218.07:56:30.59#ibcon#cleared, iclass 17 cls_cnt 0 2006.218.07:56:30.59$vc4f8/vblo=1,632.99 2006.218.07:56:30.59#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.218.07:56:30.59#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.218.07:56:30.59#ibcon#ireg 17 cls_cnt 0 2006.218.07:56:30.59#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.218.07:56:30.59#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.218.07:56:30.59#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.218.07:56:30.59#ibcon#enter wrdev, iclass 19, count 0 2006.218.07:56:30.59#ibcon#first serial, iclass 19, count 0 2006.218.07:56:30.59#ibcon#enter sib2, iclass 19, count 0 2006.218.07:56:30.59#ibcon#flushed, iclass 19, count 0 2006.218.07:56:30.59#ibcon#about to write, iclass 19, count 0 2006.218.07:56:30.59#ibcon#wrote, iclass 19, count 0 2006.218.07:56:30.59#ibcon#about to read 3, iclass 19, count 0 2006.218.07:56:30.61#ibcon#read 3, iclass 19, count 0 2006.218.07:56:30.61#ibcon#about to read 4, iclass 19, count 0 2006.218.07:56:30.61#ibcon#read 4, iclass 19, count 0 2006.218.07:56:30.61#ibcon#about to read 5, iclass 19, count 0 2006.218.07:56:30.61#ibcon#read 5, iclass 19, count 0 2006.218.07:56:30.61#ibcon#about to read 6, iclass 19, count 0 2006.218.07:56:30.61#ibcon#read 6, iclass 19, count 0 2006.218.07:56:30.61#ibcon#end of sib2, iclass 19, count 0 2006.218.07:56:30.61#ibcon#*mode == 0, iclass 19, count 0 2006.218.07:56:30.61#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.218.07:56:30.61#ibcon#[28=FRQ=01,632.99\r\n] 2006.218.07:56:30.61#ibcon#*before write, iclass 19, count 0 2006.218.07:56:30.61#ibcon#enter sib2, iclass 19, count 0 2006.218.07:56:30.61#ibcon#flushed, iclass 19, count 0 2006.218.07:56:30.61#ibcon#about to write, iclass 19, count 0 2006.218.07:56:30.61#ibcon#wrote, iclass 19, count 0 2006.218.07:56:30.61#ibcon#about to read 3, iclass 19, count 0 2006.218.07:56:30.65#ibcon#read 3, iclass 19, count 0 2006.218.07:56:30.65#ibcon#about to read 4, iclass 19, count 0 2006.218.07:56:30.65#ibcon#read 4, iclass 19, count 0 2006.218.07:56:30.65#ibcon#about to read 5, iclass 19, count 0 2006.218.07:56:30.65#ibcon#read 5, iclass 19, count 0 2006.218.07:56:30.65#ibcon#about to read 6, iclass 19, count 0 2006.218.07:56:30.65#ibcon#read 6, iclass 19, count 0 2006.218.07:56:30.65#ibcon#end of sib2, iclass 19, count 0 2006.218.07:56:30.65#ibcon#*after write, iclass 19, count 0 2006.218.07:56:30.65#ibcon#*before return 0, iclass 19, count 0 2006.218.07:56:30.65#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.218.07:56:30.65#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.218.07:56:30.65#ibcon#about to clear, iclass 19 cls_cnt 0 2006.218.07:56:30.65#ibcon#cleared, iclass 19 cls_cnt 0 2006.218.07:56:30.65$vc4f8/vb=1,4 2006.218.07:56:30.65#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.218.07:56:30.65#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.218.07:56:30.65#ibcon#ireg 11 cls_cnt 2 2006.218.07:56:30.65#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.218.07:56:30.65#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.218.07:56:30.65#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.218.07:56:30.65#ibcon#enter wrdev, iclass 21, count 2 2006.218.07:56:30.65#ibcon#first serial, iclass 21, count 2 2006.218.07:56:30.65#ibcon#enter sib2, iclass 21, count 2 2006.218.07:56:30.65#ibcon#flushed, iclass 21, count 2 2006.218.07:56:30.65#ibcon#about to write, iclass 21, count 2 2006.218.07:56:30.65#ibcon#wrote, iclass 21, count 2 2006.218.07:56:30.65#ibcon#about to read 3, iclass 21, count 2 2006.218.07:56:30.67#ibcon#read 3, iclass 21, count 2 2006.218.07:56:30.67#ibcon#about to read 4, iclass 21, count 2 2006.218.07:56:30.67#ibcon#read 4, iclass 21, count 2 2006.218.07:56:30.67#ibcon#about to read 5, iclass 21, count 2 2006.218.07:56:30.67#ibcon#read 5, iclass 21, count 2 2006.218.07:56:30.67#ibcon#about to read 6, iclass 21, count 2 2006.218.07:56:30.67#ibcon#read 6, iclass 21, count 2 2006.218.07:56:30.67#ibcon#end of sib2, iclass 21, count 2 2006.218.07:56:30.67#ibcon#*mode == 0, iclass 21, count 2 2006.218.07:56:30.67#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.218.07:56:30.67#ibcon#[27=AT01-04\r\n] 2006.218.07:56:30.67#ibcon#*before write, iclass 21, count 2 2006.218.07:56:30.67#ibcon#enter sib2, iclass 21, count 2 2006.218.07:56:30.67#ibcon#flushed, iclass 21, count 2 2006.218.07:56:30.67#ibcon#about to write, iclass 21, count 2 2006.218.07:56:30.67#ibcon#wrote, iclass 21, count 2 2006.218.07:56:30.67#ibcon#about to read 3, iclass 21, count 2 2006.218.07:56:30.70#ibcon#read 3, iclass 21, count 2 2006.218.07:56:30.70#ibcon#about to read 4, iclass 21, count 2 2006.218.07:56:30.70#ibcon#read 4, iclass 21, count 2 2006.218.07:56:30.70#ibcon#about to read 5, iclass 21, count 2 2006.218.07:56:30.70#ibcon#read 5, iclass 21, count 2 2006.218.07:56:30.70#ibcon#about to read 6, iclass 21, count 2 2006.218.07:56:30.70#ibcon#read 6, iclass 21, count 2 2006.218.07:56:30.70#ibcon#end of sib2, iclass 21, count 2 2006.218.07:56:30.70#ibcon#*after write, iclass 21, count 2 2006.218.07:56:30.70#ibcon#*before return 0, iclass 21, count 2 2006.218.07:56:30.70#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.218.07:56:30.70#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.218.07:56:30.70#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.218.07:56:30.70#ibcon#ireg 7 cls_cnt 0 2006.218.07:56:30.70#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.218.07:56:30.82#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.218.07:56:30.82#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.218.07:56:30.82#ibcon#enter wrdev, iclass 21, count 0 2006.218.07:56:30.82#ibcon#first serial, iclass 21, count 0 2006.218.07:56:30.82#ibcon#enter sib2, iclass 21, count 0 2006.218.07:56:30.82#ibcon#flushed, iclass 21, count 0 2006.218.07:56:30.82#ibcon#about to write, iclass 21, count 0 2006.218.07:56:30.82#ibcon#wrote, iclass 21, count 0 2006.218.07:56:30.82#ibcon#about to read 3, iclass 21, count 0 2006.218.07:56:30.84#ibcon#read 3, iclass 21, count 0 2006.218.07:56:30.84#ibcon#about to read 4, iclass 21, count 0 2006.218.07:56:30.84#ibcon#read 4, iclass 21, count 0 2006.218.07:56:30.84#ibcon#about to read 5, iclass 21, count 0 2006.218.07:56:30.84#ibcon#read 5, iclass 21, count 0 2006.218.07:56:30.84#ibcon#about to read 6, iclass 21, count 0 2006.218.07:56:30.84#ibcon#read 6, iclass 21, count 0 2006.218.07:56:30.84#ibcon#end of sib2, iclass 21, count 0 2006.218.07:56:30.84#ibcon#*mode == 0, iclass 21, count 0 2006.218.07:56:30.84#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.218.07:56:30.84#ibcon#[27=USB\r\n] 2006.218.07:56:30.84#ibcon#*before write, iclass 21, count 0 2006.218.07:56:30.84#ibcon#enter sib2, iclass 21, count 0 2006.218.07:56:30.84#ibcon#flushed, iclass 21, count 0 2006.218.07:56:30.84#ibcon#about to write, iclass 21, count 0 2006.218.07:56:30.84#ibcon#wrote, iclass 21, count 0 2006.218.07:56:30.84#ibcon#about to read 3, iclass 21, count 0 2006.218.07:56:30.87#ibcon#read 3, iclass 21, count 0 2006.218.07:56:30.87#ibcon#about to read 4, iclass 21, count 0 2006.218.07:56:30.87#ibcon#read 4, iclass 21, count 0 2006.218.07:56:30.87#ibcon#about to read 5, iclass 21, count 0 2006.218.07:56:30.87#ibcon#read 5, iclass 21, count 0 2006.218.07:56:30.87#ibcon#about to read 6, iclass 21, count 0 2006.218.07:56:30.87#ibcon#read 6, iclass 21, count 0 2006.218.07:56:30.87#ibcon#end of sib2, iclass 21, count 0 2006.218.07:56:30.87#ibcon#*after write, iclass 21, count 0 2006.218.07:56:30.87#ibcon#*before return 0, iclass 21, count 0 2006.218.07:56:30.87#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.218.07:56:30.87#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.218.07:56:30.87#ibcon#about to clear, iclass 21 cls_cnt 0 2006.218.07:56:30.87#ibcon#cleared, iclass 21 cls_cnt 0 2006.218.07:56:30.87$vc4f8/vblo=2,640.99 2006.218.07:56:30.87#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.218.07:56:30.87#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.218.07:56:30.87#ibcon#ireg 17 cls_cnt 0 2006.218.07:56:30.87#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.218.07:56:30.87#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.218.07:56:30.87#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.218.07:56:30.87#ibcon#enter wrdev, iclass 23, count 0 2006.218.07:56:30.87#ibcon#first serial, iclass 23, count 0 2006.218.07:56:30.87#ibcon#enter sib2, iclass 23, count 0 2006.218.07:56:30.87#ibcon#flushed, iclass 23, count 0 2006.218.07:56:30.87#ibcon#about to write, iclass 23, count 0 2006.218.07:56:30.87#ibcon#wrote, iclass 23, count 0 2006.218.07:56:30.87#ibcon#about to read 3, iclass 23, count 0 2006.218.07:56:30.89#ibcon#read 3, iclass 23, count 0 2006.218.07:56:30.89#ibcon#about to read 4, iclass 23, count 0 2006.218.07:56:30.89#ibcon#read 4, iclass 23, count 0 2006.218.07:56:30.89#ibcon#about to read 5, iclass 23, count 0 2006.218.07:56:30.89#ibcon#read 5, iclass 23, count 0 2006.218.07:56:30.89#ibcon#about to read 6, iclass 23, count 0 2006.218.07:56:30.89#ibcon#read 6, iclass 23, count 0 2006.218.07:56:30.89#ibcon#end of sib2, iclass 23, count 0 2006.218.07:56:30.89#ibcon#*mode == 0, iclass 23, count 0 2006.218.07:56:30.89#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.218.07:56:30.89#ibcon#[28=FRQ=02,640.99\r\n] 2006.218.07:56:30.89#ibcon#*before write, iclass 23, count 0 2006.218.07:56:30.89#ibcon#enter sib2, iclass 23, count 0 2006.218.07:56:30.89#ibcon#flushed, iclass 23, count 0 2006.218.07:56:30.89#ibcon#about to write, iclass 23, count 0 2006.218.07:56:30.89#ibcon#wrote, iclass 23, count 0 2006.218.07:56:30.89#ibcon#about to read 3, iclass 23, count 0 2006.218.07:56:30.93#ibcon#read 3, iclass 23, count 0 2006.218.07:56:30.93#ibcon#about to read 4, iclass 23, count 0 2006.218.07:56:30.93#ibcon#read 4, iclass 23, count 0 2006.218.07:56:30.93#ibcon#about to read 5, iclass 23, count 0 2006.218.07:56:30.93#ibcon#read 5, iclass 23, count 0 2006.218.07:56:30.93#ibcon#about to read 6, iclass 23, count 0 2006.218.07:56:30.93#ibcon#read 6, iclass 23, count 0 2006.218.07:56:30.93#ibcon#end of sib2, iclass 23, count 0 2006.218.07:56:30.93#ibcon#*after write, iclass 23, count 0 2006.218.07:56:30.93#ibcon#*before return 0, iclass 23, count 0 2006.218.07:56:30.93#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.218.07:56:30.93#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.218.07:56:30.93#ibcon#about to clear, iclass 23 cls_cnt 0 2006.218.07:56:30.93#ibcon#cleared, iclass 23 cls_cnt 0 2006.218.07:56:30.93$vc4f8/vb=2,4 2006.218.07:56:30.93#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.218.07:56:30.93#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.218.07:56:30.93#ibcon#ireg 11 cls_cnt 2 2006.218.07:56:30.93#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.218.07:56:30.99#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.218.07:56:30.99#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.218.07:56:30.99#ibcon#enter wrdev, iclass 25, count 2 2006.218.07:56:30.99#ibcon#first serial, iclass 25, count 2 2006.218.07:56:30.99#ibcon#enter sib2, iclass 25, count 2 2006.218.07:56:30.99#ibcon#flushed, iclass 25, count 2 2006.218.07:56:30.99#ibcon#about to write, iclass 25, count 2 2006.218.07:56:30.99#ibcon#wrote, iclass 25, count 2 2006.218.07:56:30.99#ibcon#about to read 3, iclass 25, count 2 2006.218.07:56:31.01#ibcon#read 3, iclass 25, count 2 2006.218.07:56:31.01#ibcon#about to read 4, iclass 25, count 2 2006.218.07:56:31.01#ibcon#read 4, iclass 25, count 2 2006.218.07:56:31.01#ibcon#about to read 5, iclass 25, count 2 2006.218.07:56:31.01#ibcon#read 5, iclass 25, count 2 2006.218.07:56:31.01#ibcon#about to read 6, iclass 25, count 2 2006.218.07:56:31.01#ibcon#read 6, iclass 25, count 2 2006.218.07:56:31.01#ibcon#end of sib2, iclass 25, count 2 2006.218.07:56:31.01#ibcon#*mode == 0, iclass 25, count 2 2006.218.07:56:31.01#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.218.07:56:31.01#ibcon#[27=AT02-04\r\n] 2006.218.07:56:31.01#ibcon#*before write, iclass 25, count 2 2006.218.07:56:31.01#ibcon#enter sib2, iclass 25, count 2 2006.218.07:56:31.01#ibcon#flushed, iclass 25, count 2 2006.218.07:56:31.01#ibcon#about to write, iclass 25, count 2 2006.218.07:56:31.01#ibcon#wrote, iclass 25, count 2 2006.218.07:56:31.01#ibcon#about to read 3, iclass 25, count 2 2006.218.07:56:31.04#ibcon#read 3, iclass 25, count 2 2006.218.07:56:31.04#ibcon#about to read 4, iclass 25, count 2 2006.218.07:56:31.04#ibcon#read 4, iclass 25, count 2 2006.218.07:56:31.04#ibcon#about to read 5, iclass 25, count 2 2006.218.07:56:31.04#ibcon#read 5, iclass 25, count 2 2006.218.07:56:31.04#ibcon#about to read 6, iclass 25, count 2 2006.218.07:56:31.04#ibcon#read 6, iclass 25, count 2 2006.218.07:56:31.04#ibcon#end of sib2, iclass 25, count 2 2006.218.07:56:31.04#ibcon#*after write, iclass 25, count 2 2006.218.07:56:31.04#ibcon#*before return 0, iclass 25, count 2 2006.218.07:56:31.04#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.218.07:56:31.04#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.218.07:56:31.04#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.218.07:56:31.04#ibcon#ireg 7 cls_cnt 0 2006.218.07:56:31.04#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.218.07:56:31.16#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.218.07:56:31.16#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.218.07:56:31.16#ibcon#enter wrdev, iclass 25, count 0 2006.218.07:56:31.16#ibcon#first serial, iclass 25, count 0 2006.218.07:56:31.16#ibcon#enter sib2, iclass 25, count 0 2006.218.07:56:31.16#ibcon#flushed, iclass 25, count 0 2006.218.07:56:31.16#ibcon#about to write, iclass 25, count 0 2006.218.07:56:31.16#ibcon#wrote, iclass 25, count 0 2006.218.07:56:31.16#ibcon#about to read 3, iclass 25, count 0 2006.218.07:56:31.18#ibcon#read 3, iclass 25, count 0 2006.218.07:56:31.18#ibcon#about to read 4, iclass 25, count 0 2006.218.07:56:31.18#ibcon#read 4, iclass 25, count 0 2006.218.07:56:31.18#ibcon#about to read 5, iclass 25, count 0 2006.218.07:56:31.18#ibcon#read 5, iclass 25, count 0 2006.218.07:56:31.18#ibcon#about to read 6, iclass 25, count 0 2006.218.07:56:31.18#ibcon#read 6, iclass 25, count 0 2006.218.07:56:31.18#ibcon#end of sib2, iclass 25, count 0 2006.218.07:56:31.18#ibcon#*mode == 0, iclass 25, count 0 2006.218.07:56:31.18#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.218.07:56:31.18#ibcon#[27=USB\r\n] 2006.218.07:56:31.18#ibcon#*before write, iclass 25, count 0 2006.218.07:56:31.18#ibcon#enter sib2, iclass 25, count 0 2006.218.07:56:31.18#ibcon#flushed, iclass 25, count 0 2006.218.07:56:31.18#ibcon#about to write, iclass 25, count 0 2006.218.07:56:31.18#ibcon#wrote, iclass 25, count 0 2006.218.07:56:31.18#ibcon#about to read 3, iclass 25, count 0 2006.218.07:56:31.21#ibcon#read 3, iclass 25, count 0 2006.218.07:56:31.21#ibcon#about to read 4, iclass 25, count 0 2006.218.07:56:31.21#ibcon#read 4, iclass 25, count 0 2006.218.07:56:31.21#ibcon#about to read 5, iclass 25, count 0 2006.218.07:56:31.21#ibcon#read 5, iclass 25, count 0 2006.218.07:56:31.21#ibcon#about to read 6, iclass 25, count 0 2006.218.07:56:31.21#ibcon#read 6, iclass 25, count 0 2006.218.07:56:31.21#ibcon#end of sib2, iclass 25, count 0 2006.218.07:56:31.21#ibcon#*after write, iclass 25, count 0 2006.218.07:56:31.21#ibcon#*before return 0, iclass 25, count 0 2006.218.07:56:31.21#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.218.07:56:31.21#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.218.07:56:31.21#ibcon#about to clear, iclass 25 cls_cnt 0 2006.218.07:56:31.21#ibcon#cleared, iclass 25 cls_cnt 0 2006.218.07:56:31.21$vc4f8/vblo=3,656.99 2006.218.07:56:31.21#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.218.07:56:31.21#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.218.07:56:31.21#ibcon#ireg 17 cls_cnt 0 2006.218.07:56:31.21#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.218.07:56:31.21#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.218.07:56:31.21#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.218.07:56:31.21#ibcon#enter wrdev, iclass 27, count 0 2006.218.07:56:31.21#ibcon#first serial, iclass 27, count 0 2006.218.07:56:31.21#ibcon#enter sib2, iclass 27, count 0 2006.218.07:56:31.21#ibcon#flushed, iclass 27, count 0 2006.218.07:56:31.21#ibcon#about to write, iclass 27, count 0 2006.218.07:56:31.21#ibcon#wrote, iclass 27, count 0 2006.218.07:56:31.21#ibcon#about to read 3, iclass 27, count 0 2006.218.07:56:31.23#ibcon#read 3, iclass 27, count 0 2006.218.07:56:31.23#ibcon#about to read 4, iclass 27, count 0 2006.218.07:56:31.23#ibcon#read 4, iclass 27, count 0 2006.218.07:56:31.23#ibcon#about to read 5, iclass 27, count 0 2006.218.07:56:31.23#ibcon#read 5, iclass 27, count 0 2006.218.07:56:31.23#ibcon#about to read 6, iclass 27, count 0 2006.218.07:56:31.23#ibcon#read 6, iclass 27, count 0 2006.218.07:56:31.23#ibcon#end of sib2, iclass 27, count 0 2006.218.07:56:31.23#ibcon#*mode == 0, iclass 27, count 0 2006.218.07:56:31.23#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.218.07:56:31.23#ibcon#[28=FRQ=03,656.99\r\n] 2006.218.07:56:31.23#ibcon#*before write, iclass 27, count 0 2006.218.07:56:31.23#ibcon#enter sib2, iclass 27, count 0 2006.218.07:56:31.23#ibcon#flushed, iclass 27, count 0 2006.218.07:56:31.23#ibcon#about to write, iclass 27, count 0 2006.218.07:56:31.23#ibcon#wrote, iclass 27, count 0 2006.218.07:56:31.23#ibcon#about to read 3, iclass 27, count 0 2006.218.07:56:31.27#ibcon#read 3, iclass 27, count 0 2006.218.07:56:31.27#ibcon#about to read 4, iclass 27, count 0 2006.218.07:56:31.27#ibcon#read 4, iclass 27, count 0 2006.218.07:56:31.27#ibcon#about to read 5, iclass 27, count 0 2006.218.07:56:31.27#ibcon#read 5, iclass 27, count 0 2006.218.07:56:31.27#ibcon#about to read 6, iclass 27, count 0 2006.218.07:56:31.27#ibcon#read 6, iclass 27, count 0 2006.218.07:56:31.27#ibcon#end of sib2, iclass 27, count 0 2006.218.07:56:31.27#ibcon#*after write, iclass 27, count 0 2006.218.07:56:31.27#ibcon#*before return 0, iclass 27, count 0 2006.218.07:56:31.27#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.218.07:56:31.27#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.218.07:56:31.27#ibcon#about to clear, iclass 27 cls_cnt 0 2006.218.07:56:31.27#ibcon#cleared, iclass 27 cls_cnt 0 2006.218.07:56:31.27$vc4f8/vb=3,4 2006.218.07:56:31.27#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.218.07:56:31.27#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.218.07:56:31.27#ibcon#ireg 11 cls_cnt 2 2006.218.07:56:31.27#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.218.07:56:31.33#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.218.07:56:31.33#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.218.07:56:31.33#ibcon#enter wrdev, iclass 29, count 2 2006.218.07:56:31.33#ibcon#first serial, iclass 29, count 2 2006.218.07:56:31.33#ibcon#enter sib2, iclass 29, count 2 2006.218.07:56:31.33#ibcon#flushed, iclass 29, count 2 2006.218.07:56:31.33#ibcon#about to write, iclass 29, count 2 2006.218.07:56:31.33#ibcon#wrote, iclass 29, count 2 2006.218.07:56:31.33#ibcon#about to read 3, iclass 29, count 2 2006.218.07:56:31.35#ibcon#read 3, iclass 29, count 2 2006.218.07:56:31.35#ibcon#about to read 4, iclass 29, count 2 2006.218.07:56:31.35#ibcon#read 4, iclass 29, count 2 2006.218.07:56:31.35#ibcon#about to read 5, iclass 29, count 2 2006.218.07:56:31.35#ibcon#read 5, iclass 29, count 2 2006.218.07:56:31.35#ibcon#about to read 6, iclass 29, count 2 2006.218.07:56:31.35#ibcon#read 6, iclass 29, count 2 2006.218.07:56:31.35#ibcon#end of sib2, iclass 29, count 2 2006.218.07:56:31.35#ibcon#*mode == 0, iclass 29, count 2 2006.218.07:56:31.35#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.218.07:56:31.35#ibcon#[27=AT03-04\r\n] 2006.218.07:56:31.35#ibcon#*before write, iclass 29, count 2 2006.218.07:56:31.35#ibcon#enter sib2, iclass 29, count 2 2006.218.07:56:31.35#ibcon#flushed, iclass 29, count 2 2006.218.07:56:31.35#ibcon#about to write, iclass 29, count 2 2006.218.07:56:31.35#ibcon#wrote, iclass 29, count 2 2006.218.07:56:31.35#ibcon#about to read 3, iclass 29, count 2 2006.218.07:56:31.38#ibcon#read 3, iclass 29, count 2 2006.218.07:56:31.38#ibcon#about to read 4, iclass 29, count 2 2006.218.07:56:31.38#ibcon#read 4, iclass 29, count 2 2006.218.07:56:31.38#ibcon#about to read 5, iclass 29, count 2 2006.218.07:56:31.38#ibcon#read 5, iclass 29, count 2 2006.218.07:56:31.38#ibcon#about to read 6, iclass 29, count 2 2006.218.07:56:31.38#ibcon#read 6, iclass 29, count 2 2006.218.07:56:31.38#ibcon#end of sib2, iclass 29, count 2 2006.218.07:56:31.38#ibcon#*after write, iclass 29, count 2 2006.218.07:56:31.38#ibcon#*before return 0, iclass 29, count 2 2006.218.07:56:31.38#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.218.07:56:31.38#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.218.07:56:31.38#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.218.07:56:31.38#ibcon#ireg 7 cls_cnt 0 2006.218.07:56:31.38#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.218.07:56:31.50#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.218.07:56:31.50#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.218.07:56:31.50#ibcon#enter wrdev, iclass 29, count 0 2006.218.07:56:31.50#ibcon#first serial, iclass 29, count 0 2006.218.07:56:31.50#ibcon#enter sib2, iclass 29, count 0 2006.218.07:56:31.50#ibcon#flushed, iclass 29, count 0 2006.218.07:56:31.50#ibcon#about to write, iclass 29, count 0 2006.218.07:56:31.50#ibcon#wrote, iclass 29, count 0 2006.218.07:56:31.50#ibcon#about to read 3, iclass 29, count 0 2006.218.07:56:31.52#ibcon#read 3, iclass 29, count 0 2006.218.07:56:31.52#ibcon#about to read 4, iclass 29, count 0 2006.218.07:56:31.52#ibcon#read 4, iclass 29, count 0 2006.218.07:56:31.52#ibcon#about to read 5, iclass 29, count 0 2006.218.07:56:31.52#ibcon#read 5, iclass 29, count 0 2006.218.07:56:31.52#ibcon#about to read 6, iclass 29, count 0 2006.218.07:56:31.52#ibcon#read 6, iclass 29, count 0 2006.218.07:56:31.52#ibcon#end of sib2, iclass 29, count 0 2006.218.07:56:31.52#ibcon#*mode == 0, iclass 29, count 0 2006.218.07:56:31.52#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.218.07:56:31.52#ibcon#[27=USB\r\n] 2006.218.07:56:31.52#ibcon#*before write, iclass 29, count 0 2006.218.07:56:31.52#ibcon#enter sib2, iclass 29, count 0 2006.218.07:56:31.52#ibcon#flushed, iclass 29, count 0 2006.218.07:56:31.52#ibcon#about to write, iclass 29, count 0 2006.218.07:56:31.52#ibcon#wrote, iclass 29, count 0 2006.218.07:56:31.52#ibcon#about to read 3, iclass 29, count 0 2006.218.07:56:31.55#ibcon#read 3, iclass 29, count 0 2006.218.07:56:31.55#ibcon#about to read 4, iclass 29, count 0 2006.218.07:56:31.55#ibcon#read 4, iclass 29, count 0 2006.218.07:56:31.55#ibcon#about to read 5, iclass 29, count 0 2006.218.07:56:31.55#ibcon#read 5, iclass 29, count 0 2006.218.07:56:31.55#ibcon#about to read 6, iclass 29, count 0 2006.218.07:56:31.55#ibcon#read 6, iclass 29, count 0 2006.218.07:56:31.55#ibcon#end of sib2, iclass 29, count 0 2006.218.07:56:31.55#ibcon#*after write, iclass 29, count 0 2006.218.07:56:31.55#ibcon#*before return 0, iclass 29, count 0 2006.218.07:56:31.55#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.218.07:56:31.55#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.218.07:56:31.55#ibcon#about to clear, iclass 29 cls_cnt 0 2006.218.07:56:31.55#ibcon#cleared, iclass 29 cls_cnt 0 2006.218.07:56:31.55$vc4f8/vblo=4,712.99 2006.218.07:56:31.55#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.218.07:56:31.55#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.218.07:56:31.55#ibcon#ireg 17 cls_cnt 0 2006.218.07:56:31.55#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.218.07:56:31.55#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.218.07:56:31.55#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.218.07:56:31.55#ibcon#enter wrdev, iclass 31, count 0 2006.218.07:56:31.55#ibcon#first serial, iclass 31, count 0 2006.218.07:56:31.55#ibcon#enter sib2, iclass 31, count 0 2006.218.07:56:31.55#ibcon#flushed, iclass 31, count 0 2006.218.07:56:31.55#ibcon#about to write, iclass 31, count 0 2006.218.07:56:31.55#ibcon#wrote, iclass 31, count 0 2006.218.07:56:31.55#ibcon#about to read 3, iclass 31, count 0 2006.218.07:56:31.57#ibcon#read 3, iclass 31, count 0 2006.218.07:56:31.57#ibcon#about to read 4, iclass 31, count 0 2006.218.07:56:31.57#ibcon#read 4, iclass 31, count 0 2006.218.07:56:31.57#ibcon#about to read 5, iclass 31, count 0 2006.218.07:56:31.57#ibcon#read 5, iclass 31, count 0 2006.218.07:56:31.57#ibcon#about to read 6, iclass 31, count 0 2006.218.07:56:31.57#ibcon#read 6, iclass 31, count 0 2006.218.07:56:31.57#ibcon#end of sib2, iclass 31, count 0 2006.218.07:56:31.57#ibcon#*mode == 0, iclass 31, count 0 2006.218.07:56:31.57#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.218.07:56:31.57#ibcon#[28=FRQ=04,712.99\r\n] 2006.218.07:56:31.57#ibcon#*before write, iclass 31, count 0 2006.218.07:56:31.57#ibcon#enter sib2, iclass 31, count 0 2006.218.07:56:31.57#ibcon#flushed, iclass 31, count 0 2006.218.07:56:31.57#ibcon#about to write, iclass 31, count 0 2006.218.07:56:31.57#ibcon#wrote, iclass 31, count 0 2006.218.07:56:31.57#ibcon#about to read 3, iclass 31, count 0 2006.218.07:56:31.61#ibcon#read 3, iclass 31, count 0 2006.218.07:56:31.61#ibcon#about to read 4, iclass 31, count 0 2006.218.07:56:31.61#ibcon#read 4, iclass 31, count 0 2006.218.07:56:31.61#ibcon#about to read 5, iclass 31, count 0 2006.218.07:56:31.61#ibcon#read 5, iclass 31, count 0 2006.218.07:56:31.61#ibcon#about to read 6, iclass 31, count 0 2006.218.07:56:31.61#ibcon#read 6, iclass 31, count 0 2006.218.07:56:31.61#ibcon#end of sib2, iclass 31, count 0 2006.218.07:56:31.61#ibcon#*after write, iclass 31, count 0 2006.218.07:56:31.61#ibcon#*before return 0, iclass 31, count 0 2006.218.07:56:31.61#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.218.07:56:31.61#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.218.07:56:31.61#ibcon#about to clear, iclass 31 cls_cnt 0 2006.218.07:56:31.61#ibcon#cleared, iclass 31 cls_cnt 0 2006.218.07:56:31.61$vc4f8/vb=4,4 2006.218.07:56:31.61#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.218.07:56:31.61#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.218.07:56:31.61#ibcon#ireg 11 cls_cnt 2 2006.218.07:56:31.61#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.218.07:56:31.67#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.218.07:56:31.67#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.218.07:56:31.67#ibcon#enter wrdev, iclass 33, count 2 2006.218.07:56:31.67#ibcon#first serial, iclass 33, count 2 2006.218.07:56:31.67#ibcon#enter sib2, iclass 33, count 2 2006.218.07:56:31.67#ibcon#flushed, iclass 33, count 2 2006.218.07:56:31.67#ibcon#about to write, iclass 33, count 2 2006.218.07:56:31.67#ibcon#wrote, iclass 33, count 2 2006.218.07:56:31.67#ibcon#about to read 3, iclass 33, count 2 2006.218.07:56:31.69#ibcon#read 3, iclass 33, count 2 2006.218.07:56:31.69#ibcon#about to read 4, iclass 33, count 2 2006.218.07:56:31.69#ibcon#read 4, iclass 33, count 2 2006.218.07:56:31.69#ibcon#about to read 5, iclass 33, count 2 2006.218.07:56:31.69#ibcon#read 5, iclass 33, count 2 2006.218.07:56:31.69#ibcon#about to read 6, iclass 33, count 2 2006.218.07:56:31.69#ibcon#read 6, iclass 33, count 2 2006.218.07:56:31.69#ibcon#end of sib2, iclass 33, count 2 2006.218.07:56:31.69#ibcon#*mode == 0, iclass 33, count 2 2006.218.07:56:31.69#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.218.07:56:31.69#ibcon#[27=AT04-04\r\n] 2006.218.07:56:31.69#ibcon#*before write, iclass 33, count 2 2006.218.07:56:31.69#ibcon#enter sib2, iclass 33, count 2 2006.218.07:56:31.69#ibcon#flushed, iclass 33, count 2 2006.218.07:56:31.69#ibcon#about to write, iclass 33, count 2 2006.218.07:56:31.69#ibcon#wrote, iclass 33, count 2 2006.218.07:56:31.69#ibcon#about to read 3, iclass 33, count 2 2006.218.07:56:31.72#ibcon#read 3, iclass 33, count 2 2006.218.07:56:31.72#ibcon#about to read 4, iclass 33, count 2 2006.218.07:56:31.72#ibcon#read 4, iclass 33, count 2 2006.218.07:56:31.72#ibcon#about to read 5, iclass 33, count 2 2006.218.07:56:31.72#ibcon#read 5, iclass 33, count 2 2006.218.07:56:31.72#ibcon#about to read 6, iclass 33, count 2 2006.218.07:56:31.72#ibcon#read 6, iclass 33, count 2 2006.218.07:56:31.72#ibcon#end of sib2, iclass 33, count 2 2006.218.07:56:31.72#ibcon#*after write, iclass 33, count 2 2006.218.07:56:31.72#ibcon#*before return 0, iclass 33, count 2 2006.218.07:56:31.72#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.218.07:56:31.72#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.218.07:56:31.72#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.218.07:56:31.72#ibcon#ireg 7 cls_cnt 0 2006.218.07:56:31.72#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.218.07:56:31.84#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.218.07:56:31.84#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.218.07:56:31.84#ibcon#enter wrdev, iclass 33, count 0 2006.218.07:56:31.84#ibcon#first serial, iclass 33, count 0 2006.218.07:56:31.84#ibcon#enter sib2, iclass 33, count 0 2006.218.07:56:31.84#ibcon#flushed, iclass 33, count 0 2006.218.07:56:31.84#ibcon#about to write, iclass 33, count 0 2006.218.07:56:31.84#ibcon#wrote, iclass 33, count 0 2006.218.07:56:31.84#ibcon#about to read 3, iclass 33, count 0 2006.218.07:56:31.86#ibcon#read 3, iclass 33, count 0 2006.218.07:56:31.86#ibcon#about to read 4, iclass 33, count 0 2006.218.07:56:31.86#ibcon#read 4, iclass 33, count 0 2006.218.07:56:31.86#ibcon#about to read 5, iclass 33, count 0 2006.218.07:56:31.86#ibcon#read 5, iclass 33, count 0 2006.218.07:56:31.86#ibcon#about to read 6, iclass 33, count 0 2006.218.07:56:31.86#ibcon#read 6, iclass 33, count 0 2006.218.07:56:31.86#ibcon#end of sib2, iclass 33, count 0 2006.218.07:56:31.86#ibcon#*mode == 0, iclass 33, count 0 2006.218.07:56:31.86#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.218.07:56:31.86#ibcon#[27=USB\r\n] 2006.218.07:56:31.86#ibcon#*before write, iclass 33, count 0 2006.218.07:56:31.86#ibcon#enter sib2, iclass 33, count 0 2006.218.07:56:31.86#ibcon#flushed, iclass 33, count 0 2006.218.07:56:31.86#ibcon#about to write, iclass 33, count 0 2006.218.07:56:31.86#ibcon#wrote, iclass 33, count 0 2006.218.07:56:31.86#ibcon#about to read 3, iclass 33, count 0 2006.218.07:56:31.89#ibcon#read 3, iclass 33, count 0 2006.218.07:56:31.89#ibcon#about to read 4, iclass 33, count 0 2006.218.07:56:31.89#ibcon#read 4, iclass 33, count 0 2006.218.07:56:31.89#ibcon#about to read 5, iclass 33, count 0 2006.218.07:56:31.89#ibcon#read 5, iclass 33, count 0 2006.218.07:56:31.89#ibcon#about to read 6, iclass 33, count 0 2006.218.07:56:31.89#ibcon#read 6, iclass 33, count 0 2006.218.07:56:31.89#ibcon#end of sib2, iclass 33, count 0 2006.218.07:56:31.89#ibcon#*after write, iclass 33, count 0 2006.218.07:56:31.89#ibcon#*before return 0, iclass 33, count 0 2006.218.07:56:31.89#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.218.07:56:31.89#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.218.07:56:31.89#ibcon#about to clear, iclass 33 cls_cnt 0 2006.218.07:56:31.89#ibcon#cleared, iclass 33 cls_cnt 0 2006.218.07:56:31.89$vc4f8/vblo=5,744.99 2006.218.07:56:31.89#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.218.07:56:31.89#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.218.07:56:31.89#ibcon#ireg 17 cls_cnt 0 2006.218.07:56:31.89#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.218.07:56:31.89#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.218.07:56:31.89#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.218.07:56:31.89#ibcon#enter wrdev, iclass 35, count 0 2006.218.07:56:31.89#ibcon#first serial, iclass 35, count 0 2006.218.07:56:31.89#ibcon#enter sib2, iclass 35, count 0 2006.218.07:56:31.89#ibcon#flushed, iclass 35, count 0 2006.218.07:56:31.89#ibcon#about to write, iclass 35, count 0 2006.218.07:56:31.89#ibcon#wrote, iclass 35, count 0 2006.218.07:56:31.89#ibcon#about to read 3, iclass 35, count 0 2006.218.07:56:31.92#ibcon#read 3, iclass 35, count 0 2006.218.07:56:31.92#ibcon#about to read 4, iclass 35, count 0 2006.218.07:56:31.92#ibcon#read 4, iclass 35, count 0 2006.218.07:56:31.92#ibcon#about to read 5, iclass 35, count 0 2006.218.07:56:31.92#ibcon#read 5, iclass 35, count 0 2006.218.07:56:31.92#ibcon#about to read 6, iclass 35, count 0 2006.218.07:56:31.92#ibcon#read 6, iclass 35, count 0 2006.218.07:56:31.92#ibcon#end of sib2, iclass 35, count 0 2006.218.07:56:31.92#ibcon#*mode == 0, iclass 35, count 0 2006.218.07:56:31.92#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.218.07:56:31.92#ibcon#[28=FRQ=05,744.99\r\n] 2006.218.07:56:31.92#ibcon#*before write, iclass 35, count 0 2006.218.07:56:31.92#ibcon#enter sib2, iclass 35, count 0 2006.218.07:56:31.92#ibcon#flushed, iclass 35, count 0 2006.218.07:56:31.92#ibcon#about to write, iclass 35, count 0 2006.218.07:56:31.92#ibcon#wrote, iclass 35, count 0 2006.218.07:56:31.92#ibcon#about to read 3, iclass 35, count 0 2006.218.07:56:31.96#ibcon#read 3, iclass 35, count 0 2006.218.07:56:31.96#ibcon#about to read 4, iclass 35, count 0 2006.218.07:56:31.96#ibcon#read 4, iclass 35, count 0 2006.218.07:56:31.96#ibcon#about to read 5, iclass 35, count 0 2006.218.07:56:31.96#ibcon#read 5, iclass 35, count 0 2006.218.07:56:31.96#ibcon#about to read 6, iclass 35, count 0 2006.218.07:56:31.96#ibcon#read 6, iclass 35, count 0 2006.218.07:56:31.96#ibcon#end of sib2, iclass 35, count 0 2006.218.07:56:31.96#ibcon#*after write, iclass 35, count 0 2006.218.07:56:31.96#ibcon#*before return 0, iclass 35, count 0 2006.218.07:56:31.96#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.218.07:56:31.96#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.218.07:56:31.96#ibcon#about to clear, iclass 35 cls_cnt 0 2006.218.07:56:31.96#ibcon#cleared, iclass 35 cls_cnt 0 2006.218.07:56:31.96$vc4f8/vb=5,4 2006.218.07:56:31.96#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.218.07:56:31.96#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.218.07:56:31.96#ibcon#ireg 11 cls_cnt 2 2006.218.07:56:31.96#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.218.07:56:32.01#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.218.07:56:32.01#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.218.07:56:32.01#ibcon#enter wrdev, iclass 37, count 2 2006.218.07:56:32.01#ibcon#first serial, iclass 37, count 2 2006.218.07:56:32.01#ibcon#enter sib2, iclass 37, count 2 2006.218.07:56:32.01#ibcon#flushed, iclass 37, count 2 2006.218.07:56:32.01#ibcon#about to write, iclass 37, count 2 2006.218.07:56:32.01#ibcon#wrote, iclass 37, count 2 2006.218.07:56:32.01#ibcon#about to read 3, iclass 37, count 2 2006.218.07:56:32.03#ibcon#read 3, iclass 37, count 2 2006.218.07:56:32.03#ibcon#about to read 4, iclass 37, count 2 2006.218.07:56:32.03#ibcon#read 4, iclass 37, count 2 2006.218.07:56:32.03#ibcon#about to read 5, iclass 37, count 2 2006.218.07:56:32.03#ibcon#read 5, iclass 37, count 2 2006.218.07:56:32.03#ibcon#about to read 6, iclass 37, count 2 2006.218.07:56:32.03#ibcon#read 6, iclass 37, count 2 2006.218.07:56:32.03#ibcon#end of sib2, iclass 37, count 2 2006.218.07:56:32.03#ibcon#*mode == 0, iclass 37, count 2 2006.218.07:56:32.03#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.218.07:56:32.03#ibcon#[27=AT05-04\r\n] 2006.218.07:56:32.03#ibcon#*before write, iclass 37, count 2 2006.218.07:56:32.03#ibcon#enter sib2, iclass 37, count 2 2006.218.07:56:32.03#ibcon#flushed, iclass 37, count 2 2006.218.07:56:32.03#ibcon#about to write, iclass 37, count 2 2006.218.07:56:32.03#ibcon#wrote, iclass 37, count 2 2006.218.07:56:32.03#ibcon#about to read 3, iclass 37, count 2 2006.218.07:56:32.06#ibcon#read 3, iclass 37, count 2 2006.218.07:56:32.06#ibcon#about to read 4, iclass 37, count 2 2006.218.07:56:32.06#ibcon#read 4, iclass 37, count 2 2006.218.07:56:32.06#ibcon#about to read 5, iclass 37, count 2 2006.218.07:56:32.06#ibcon#read 5, iclass 37, count 2 2006.218.07:56:32.06#ibcon#about to read 6, iclass 37, count 2 2006.218.07:56:32.06#ibcon#read 6, iclass 37, count 2 2006.218.07:56:32.06#ibcon#end of sib2, iclass 37, count 2 2006.218.07:56:32.06#ibcon#*after write, iclass 37, count 2 2006.218.07:56:32.06#ibcon#*before return 0, iclass 37, count 2 2006.218.07:56:32.06#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.218.07:56:32.06#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.218.07:56:32.06#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.218.07:56:32.06#ibcon#ireg 7 cls_cnt 0 2006.218.07:56:32.06#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.218.07:56:32.18#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.218.07:56:32.18#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.218.07:56:32.18#ibcon#enter wrdev, iclass 37, count 0 2006.218.07:56:32.18#ibcon#first serial, iclass 37, count 0 2006.218.07:56:32.18#ibcon#enter sib2, iclass 37, count 0 2006.218.07:56:32.18#ibcon#flushed, iclass 37, count 0 2006.218.07:56:32.18#ibcon#about to write, iclass 37, count 0 2006.218.07:56:32.18#ibcon#wrote, iclass 37, count 0 2006.218.07:56:32.18#ibcon#about to read 3, iclass 37, count 0 2006.218.07:56:32.20#ibcon#read 3, iclass 37, count 0 2006.218.07:56:32.20#ibcon#about to read 4, iclass 37, count 0 2006.218.07:56:32.20#ibcon#read 4, iclass 37, count 0 2006.218.07:56:32.20#ibcon#about to read 5, iclass 37, count 0 2006.218.07:56:32.20#ibcon#read 5, iclass 37, count 0 2006.218.07:56:32.20#ibcon#about to read 6, iclass 37, count 0 2006.218.07:56:32.20#ibcon#read 6, iclass 37, count 0 2006.218.07:56:32.20#ibcon#end of sib2, iclass 37, count 0 2006.218.07:56:32.20#ibcon#*mode == 0, iclass 37, count 0 2006.218.07:56:32.20#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.218.07:56:32.20#ibcon#[27=USB\r\n] 2006.218.07:56:32.20#ibcon#*before write, iclass 37, count 0 2006.218.07:56:32.20#ibcon#enter sib2, iclass 37, count 0 2006.218.07:56:32.20#ibcon#flushed, iclass 37, count 0 2006.218.07:56:32.20#ibcon#about to write, iclass 37, count 0 2006.218.07:56:32.20#ibcon#wrote, iclass 37, count 0 2006.218.07:56:32.20#ibcon#about to read 3, iclass 37, count 0 2006.218.07:56:32.23#ibcon#read 3, iclass 37, count 0 2006.218.07:56:32.23#ibcon#about to read 4, iclass 37, count 0 2006.218.07:56:32.23#ibcon#read 4, iclass 37, count 0 2006.218.07:56:32.23#ibcon#about to read 5, iclass 37, count 0 2006.218.07:56:32.23#ibcon#read 5, iclass 37, count 0 2006.218.07:56:32.23#ibcon#about to read 6, iclass 37, count 0 2006.218.07:56:32.23#ibcon#read 6, iclass 37, count 0 2006.218.07:56:32.23#ibcon#end of sib2, iclass 37, count 0 2006.218.07:56:32.23#ibcon#*after write, iclass 37, count 0 2006.218.07:56:32.23#ibcon#*before return 0, iclass 37, count 0 2006.218.07:56:32.23#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.218.07:56:32.23#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.218.07:56:32.23#ibcon#about to clear, iclass 37 cls_cnt 0 2006.218.07:56:32.23#ibcon#cleared, iclass 37 cls_cnt 0 2006.218.07:56:32.23$vc4f8/vblo=6,752.99 2006.218.07:56:32.23#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.218.07:56:32.23#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.218.07:56:32.23#ibcon#ireg 17 cls_cnt 0 2006.218.07:56:32.23#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.218.07:56:32.23#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.218.07:56:32.23#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.218.07:56:32.23#ibcon#enter wrdev, iclass 39, count 0 2006.218.07:56:32.23#ibcon#first serial, iclass 39, count 0 2006.218.07:56:32.23#ibcon#enter sib2, iclass 39, count 0 2006.218.07:56:32.23#ibcon#flushed, iclass 39, count 0 2006.218.07:56:32.23#ibcon#about to write, iclass 39, count 0 2006.218.07:56:32.23#ibcon#wrote, iclass 39, count 0 2006.218.07:56:32.23#ibcon#about to read 3, iclass 39, count 0 2006.218.07:56:32.25#ibcon#read 3, iclass 39, count 0 2006.218.07:56:32.25#ibcon#about to read 4, iclass 39, count 0 2006.218.07:56:32.25#ibcon#read 4, iclass 39, count 0 2006.218.07:56:32.25#ibcon#about to read 5, iclass 39, count 0 2006.218.07:56:32.25#ibcon#read 5, iclass 39, count 0 2006.218.07:56:32.25#ibcon#about to read 6, iclass 39, count 0 2006.218.07:56:32.25#ibcon#read 6, iclass 39, count 0 2006.218.07:56:32.25#ibcon#end of sib2, iclass 39, count 0 2006.218.07:56:32.25#ibcon#*mode == 0, iclass 39, count 0 2006.218.07:56:32.25#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.218.07:56:32.25#ibcon#[28=FRQ=06,752.99\r\n] 2006.218.07:56:32.25#ibcon#*before write, iclass 39, count 0 2006.218.07:56:32.25#ibcon#enter sib2, iclass 39, count 0 2006.218.07:56:32.25#ibcon#flushed, iclass 39, count 0 2006.218.07:56:32.25#ibcon#about to write, iclass 39, count 0 2006.218.07:56:32.25#ibcon#wrote, iclass 39, count 0 2006.218.07:56:32.25#ibcon#about to read 3, iclass 39, count 0 2006.218.07:56:32.29#ibcon#read 3, iclass 39, count 0 2006.218.07:56:32.29#ibcon#about to read 4, iclass 39, count 0 2006.218.07:56:32.29#ibcon#read 4, iclass 39, count 0 2006.218.07:56:32.29#ibcon#about to read 5, iclass 39, count 0 2006.218.07:56:32.29#ibcon#read 5, iclass 39, count 0 2006.218.07:56:32.29#ibcon#about to read 6, iclass 39, count 0 2006.218.07:56:32.29#ibcon#read 6, iclass 39, count 0 2006.218.07:56:32.29#ibcon#end of sib2, iclass 39, count 0 2006.218.07:56:32.29#ibcon#*after write, iclass 39, count 0 2006.218.07:56:32.29#ibcon#*before return 0, iclass 39, count 0 2006.218.07:56:32.29#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.218.07:56:32.29#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.218.07:56:32.29#ibcon#about to clear, iclass 39 cls_cnt 0 2006.218.07:56:32.29#ibcon#cleared, iclass 39 cls_cnt 0 2006.218.07:56:32.29$vc4f8/vb=6,4 2006.218.07:56:32.29#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.218.07:56:32.29#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.218.07:56:32.29#ibcon#ireg 11 cls_cnt 2 2006.218.07:56:32.29#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.218.07:56:32.35#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.218.07:56:32.35#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.218.07:56:32.35#ibcon#enter wrdev, iclass 3, count 2 2006.218.07:56:32.35#ibcon#first serial, iclass 3, count 2 2006.218.07:56:32.35#ibcon#enter sib2, iclass 3, count 2 2006.218.07:56:32.35#ibcon#flushed, iclass 3, count 2 2006.218.07:56:32.35#ibcon#about to write, iclass 3, count 2 2006.218.07:56:32.35#ibcon#wrote, iclass 3, count 2 2006.218.07:56:32.35#ibcon#about to read 3, iclass 3, count 2 2006.218.07:56:32.37#ibcon#read 3, iclass 3, count 2 2006.218.07:56:32.37#ibcon#about to read 4, iclass 3, count 2 2006.218.07:56:32.37#ibcon#read 4, iclass 3, count 2 2006.218.07:56:32.37#ibcon#about to read 5, iclass 3, count 2 2006.218.07:56:32.37#ibcon#read 5, iclass 3, count 2 2006.218.07:56:32.37#ibcon#about to read 6, iclass 3, count 2 2006.218.07:56:32.37#ibcon#read 6, iclass 3, count 2 2006.218.07:56:32.37#ibcon#end of sib2, iclass 3, count 2 2006.218.07:56:32.37#ibcon#*mode == 0, iclass 3, count 2 2006.218.07:56:32.37#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.218.07:56:32.37#ibcon#[27=AT06-04\r\n] 2006.218.07:56:32.37#ibcon#*before write, iclass 3, count 2 2006.218.07:56:32.37#ibcon#enter sib2, iclass 3, count 2 2006.218.07:56:32.37#ibcon#flushed, iclass 3, count 2 2006.218.07:56:32.37#ibcon#about to write, iclass 3, count 2 2006.218.07:56:32.37#ibcon#wrote, iclass 3, count 2 2006.218.07:56:32.37#ibcon#about to read 3, iclass 3, count 2 2006.218.07:56:32.40#ibcon#read 3, iclass 3, count 2 2006.218.07:56:32.40#ibcon#about to read 4, iclass 3, count 2 2006.218.07:56:32.40#ibcon#read 4, iclass 3, count 2 2006.218.07:56:32.40#ibcon#about to read 5, iclass 3, count 2 2006.218.07:56:32.40#ibcon#read 5, iclass 3, count 2 2006.218.07:56:32.40#ibcon#about to read 6, iclass 3, count 2 2006.218.07:56:32.40#ibcon#read 6, iclass 3, count 2 2006.218.07:56:32.40#ibcon#end of sib2, iclass 3, count 2 2006.218.07:56:32.40#ibcon#*after write, iclass 3, count 2 2006.218.07:56:32.40#ibcon#*before return 0, iclass 3, count 2 2006.218.07:56:32.40#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.218.07:56:32.40#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.218.07:56:32.40#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.218.07:56:32.40#ibcon#ireg 7 cls_cnt 0 2006.218.07:56:32.40#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.218.07:56:32.52#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.218.07:56:32.52#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.218.07:56:32.52#ibcon#enter wrdev, iclass 3, count 0 2006.218.07:56:32.52#ibcon#first serial, iclass 3, count 0 2006.218.07:56:32.52#ibcon#enter sib2, iclass 3, count 0 2006.218.07:56:32.52#ibcon#flushed, iclass 3, count 0 2006.218.07:56:32.52#ibcon#about to write, iclass 3, count 0 2006.218.07:56:32.52#ibcon#wrote, iclass 3, count 0 2006.218.07:56:32.52#ibcon#about to read 3, iclass 3, count 0 2006.218.07:56:32.54#ibcon#read 3, iclass 3, count 0 2006.218.07:56:32.54#ibcon#about to read 4, iclass 3, count 0 2006.218.07:56:32.54#ibcon#read 4, iclass 3, count 0 2006.218.07:56:32.54#ibcon#about to read 5, iclass 3, count 0 2006.218.07:56:32.54#ibcon#read 5, iclass 3, count 0 2006.218.07:56:32.54#ibcon#about to read 6, iclass 3, count 0 2006.218.07:56:32.54#ibcon#read 6, iclass 3, count 0 2006.218.07:56:32.54#ibcon#end of sib2, iclass 3, count 0 2006.218.07:56:32.54#ibcon#*mode == 0, iclass 3, count 0 2006.218.07:56:32.54#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.218.07:56:32.54#ibcon#[27=USB\r\n] 2006.218.07:56:32.54#ibcon#*before write, iclass 3, count 0 2006.218.07:56:32.54#ibcon#enter sib2, iclass 3, count 0 2006.218.07:56:32.54#ibcon#flushed, iclass 3, count 0 2006.218.07:56:32.54#ibcon#about to write, iclass 3, count 0 2006.218.07:56:32.54#ibcon#wrote, iclass 3, count 0 2006.218.07:56:32.54#ibcon#about to read 3, iclass 3, count 0 2006.218.07:56:32.57#ibcon#read 3, iclass 3, count 0 2006.218.07:56:32.57#ibcon#about to read 4, iclass 3, count 0 2006.218.07:56:32.57#ibcon#read 4, iclass 3, count 0 2006.218.07:56:32.57#ibcon#about to read 5, iclass 3, count 0 2006.218.07:56:32.57#ibcon#read 5, iclass 3, count 0 2006.218.07:56:32.57#ibcon#about to read 6, iclass 3, count 0 2006.218.07:56:32.57#ibcon#read 6, iclass 3, count 0 2006.218.07:56:32.57#ibcon#end of sib2, iclass 3, count 0 2006.218.07:56:32.57#ibcon#*after write, iclass 3, count 0 2006.218.07:56:32.57#ibcon#*before return 0, iclass 3, count 0 2006.218.07:56:32.57#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.218.07:56:32.57#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.218.07:56:32.57#ibcon#about to clear, iclass 3 cls_cnt 0 2006.218.07:56:32.57#ibcon#cleared, iclass 3 cls_cnt 0 2006.218.07:56:32.57$vc4f8/vabw=wide 2006.218.07:56:32.57#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.218.07:56:32.57#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.218.07:56:32.57#ibcon#ireg 8 cls_cnt 0 2006.218.07:56:32.57#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.218.07:56:32.57#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.218.07:56:32.57#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.218.07:56:32.57#ibcon#enter wrdev, iclass 5, count 0 2006.218.07:56:32.57#ibcon#first serial, iclass 5, count 0 2006.218.07:56:32.57#ibcon#enter sib2, iclass 5, count 0 2006.218.07:56:32.57#ibcon#flushed, iclass 5, count 0 2006.218.07:56:32.57#ibcon#about to write, iclass 5, count 0 2006.218.07:56:32.57#ibcon#wrote, iclass 5, count 0 2006.218.07:56:32.57#ibcon#about to read 3, iclass 5, count 0 2006.218.07:56:32.59#ibcon#read 3, iclass 5, count 0 2006.218.07:56:32.59#ibcon#about to read 4, iclass 5, count 0 2006.218.07:56:32.59#ibcon#read 4, iclass 5, count 0 2006.218.07:56:32.59#ibcon#about to read 5, iclass 5, count 0 2006.218.07:56:32.59#ibcon#read 5, iclass 5, count 0 2006.218.07:56:32.59#ibcon#about to read 6, iclass 5, count 0 2006.218.07:56:32.59#ibcon#read 6, iclass 5, count 0 2006.218.07:56:32.59#ibcon#end of sib2, iclass 5, count 0 2006.218.07:56:32.59#ibcon#*mode == 0, iclass 5, count 0 2006.218.07:56:32.59#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.218.07:56:32.59#ibcon#[25=BW32\r\n] 2006.218.07:56:32.59#ibcon#*before write, iclass 5, count 0 2006.218.07:56:32.59#ibcon#enter sib2, iclass 5, count 0 2006.218.07:56:32.59#ibcon#flushed, iclass 5, count 0 2006.218.07:56:32.59#ibcon#about to write, iclass 5, count 0 2006.218.07:56:32.59#ibcon#wrote, iclass 5, count 0 2006.218.07:56:32.59#ibcon#about to read 3, iclass 5, count 0 2006.218.07:56:32.62#ibcon#read 3, iclass 5, count 0 2006.218.07:56:32.62#ibcon#about to read 4, iclass 5, count 0 2006.218.07:56:32.62#ibcon#read 4, iclass 5, count 0 2006.218.07:56:32.62#ibcon#about to read 5, iclass 5, count 0 2006.218.07:56:32.62#ibcon#read 5, iclass 5, count 0 2006.218.07:56:32.62#ibcon#about to read 6, iclass 5, count 0 2006.218.07:56:32.62#ibcon#read 6, iclass 5, count 0 2006.218.07:56:32.62#ibcon#end of sib2, iclass 5, count 0 2006.218.07:56:32.62#ibcon#*after write, iclass 5, count 0 2006.218.07:56:32.62#ibcon#*before return 0, iclass 5, count 0 2006.218.07:56:32.62#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.218.07:56:32.62#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.218.07:56:32.62#ibcon#about to clear, iclass 5 cls_cnt 0 2006.218.07:56:32.62#ibcon#cleared, iclass 5 cls_cnt 0 2006.218.07:56:32.62$vc4f8/vbbw=wide 2006.218.07:56:32.62#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.218.07:56:32.62#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.218.07:56:32.62#ibcon#ireg 8 cls_cnt 0 2006.218.07:56:32.62#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.218.07:56:32.69#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.218.07:56:32.69#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.218.07:56:32.69#ibcon#enter wrdev, iclass 7, count 0 2006.218.07:56:32.69#ibcon#first serial, iclass 7, count 0 2006.218.07:56:32.69#ibcon#enter sib2, iclass 7, count 0 2006.218.07:56:32.69#ibcon#flushed, iclass 7, count 0 2006.218.07:56:32.69#ibcon#about to write, iclass 7, count 0 2006.218.07:56:32.69#ibcon#wrote, iclass 7, count 0 2006.218.07:56:32.69#ibcon#about to read 3, iclass 7, count 0 2006.218.07:56:32.71#ibcon#read 3, iclass 7, count 0 2006.218.07:56:32.71#ibcon#about to read 4, iclass 7, count 0 2006.218.07:56:32.71#ibcon#read 4, iclass 7, count 0 2006.218.07:56:32.71#ibcon#about to read 5, iclass 7, count 0 2006.218.07:56:32.71#ibcon#read 5, iclass 7, count 0 2006.218.07:56:32.71#ibcon#about to read 6, iclass 7, count 0 2006.218.07:56:32.71#ibcon#read 6, iclass 7, count 0 2006.218.07:56:32.71#ibcon#end of sib2, iclass 7, count 0 2006.218.07:56:32.71#ibcon#*mode == 0, iclass 7, count 0 2006.218.07:56:32.71#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.218.07:56:32.71#ibcon#[27=BW32\r\n] 2006.218.07:56:32.71#ibcon#*before write, iclass 7, count 0 2006.218.07:56:32.71#ibcon#enter sib2, iclass 7, count 0 2006.218.07:56:32.71#ibcon#flushed, iclass 7, count 0 2006.218.07:56:32.71#ibcon#about to write, iclass 7, count 0 2006.218.07:56:32.71#ibcon#wrote, iclass 7, count 0 2006.218.07:56:32.71#ibcon#about to read 3, iclass 7, count 0 2006.218.07:56:32.74#ibcon#read 3, iclass 7, count 0 2006.218.07:56:32.74#ibcon#about to read 4, iclass 7, count 0 2006.218.07:56:32.74#ibcon#read 4, iclass 7, count 0 2006.218.07:56:32.74#ibcon#about to read 5, iclass 7, count 0 2006.218.07:56:32.74#ibcon#read 5, iclass 7, count 0 2006.218.07:56:32.74#ibcon#about to read 6, iclass 7, count 0 2006.218.07:56:32.74#ibcon#read 6, iclass 7, count 0 2006.218.07:56:32.74#ibcon#end of sib2, iclass 7, count 0 2006.218.07:56:32.74#ibcon#*after write, iclass 7, count 0 2006.218.07:56:32.74#ibcon#*before return 0, iclass 7, count 0 2006.218.07:56:32.74#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.218.07:56:32.74#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.218.07:56:32.74#ibcon#about to clear, iclass 7 cls_cnt 0 2006.218.07:56:32.74#ibcon#cleared, iclass 7 cls_cnt 0 2006.218.07:56:32.74$4f8m12a/ifd4f 2006.218.07:56:32.74$ifd4f/lo= 2006.218.07:56:32.74$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.218.07:56:32.74$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.218.07:56:32.74$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.218.07:56:32.74$ifd4f/patch= 2006.218.07:56:32.74$ifd4f/patch=lo1,a1,a2,a3,a4 2006.218.07:56:32.74$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.218.07:56:32.74$ifd4f/patch=lo3,a5,a6,a7,a8 2006.218.07:56:32.74$4f8m12a/"form=m,16.000,1:2 2006.218.07:56:32.74$4f8m12a/"tpicd 2006.218.07:56:32.75$4f8m12a/echo=off 2006.218.07:56:32.75$4f8m12a/xlog=off 2006.218.07:56:32.75:!2006.218.07:58:40 2006.218.07:56:52.14#trakl#Source acquired 2006.218.07:56:53.14#flagr#flagr/antenna,acquired 2006.218.07:58:40.01:preob 2006.218.07:58:41.14/onsource/TRACKING 2006.218.07:58:41.14:!2006.218.07:58:50 2006.218.07:58:50.00:data_valid=on 2006.218.07:58:50.00:midob 2006.218.07:58:50.14/onsource/TRACKING 2006.218.07:58:50.14/wx/31.04,1007.5,73 2006.218.07:58:50.37/cable/+6.3856E-03 2006.218.07:58:51.46/va/01,05,usb,yes,31,33 2006.218.07:58:51.46/va/02,04,usb,yes,29,30 2006.218.07:58:51.46/va/03,04,usb,yes,27,28 2006.218.07:58:51.46/va/04,04,usb,yes,31,33 2006.218.07:58:51.46/va/05,07,usb,yes,33,34 2006.218.07:58:51.46/va/06,06,usb,yes,32,31 2006.218.07:58:51.46/va/07,06,usb,yes,32,32 2006.218.07:58:51.46/va/08,07,usb,yes,30,30 2006.218.07:58:51.69/valo/01,532.99,yes,locked 2006.218.07:58:51.69/valo/02,572.99,yes,locked 2006.218.07:58:51.69/valo/03,672.99,yes,locked 2006.218.07:58:51.69/valo/04,832.99,yes,locked 2006.218.07:58:51.69/valo/05,652.99,yes,locked 2006.218.07:58:51.69/valo/06,772.99,yes,locked 2006.218.07:58:51.69/valo/07,832.99,yes,locked 2006.218.07:58:51.69/valo/08,852.99,yes,locked 2006.218.07:58:52.78/vb/01,04,usb,yes,30,29 2006.218.07:58:52.78/vb/02,04,usb,yes,32,33 2006.218.07:58:52.78/vb/03,04,usb,yes,28,32 2006.218.07:58:52.78/vb/04,04,usb,yes,29,29 2006.218.07:58:52.78/vb/05,04,usb,yes,27,32 2006.218.07:58:52.78/vb/06,04,usb,yes,28,31 2006.218.07:58:52.78/vb/07,04,usb,yes,31,31 2006.218.07:58:52.78/vb/08,04,usb,yes,28,31 2006.218.07:58:53.01/vblo/01,632.99,yes,locked 2006.218.07:58:53.01/vblo/02,640.99,yes,locked 2006.218.07:58:53.01/vblo/03,656.99,yes,locked 2006.218.07:58:53.01/vblo/04,712.99,yes,locked 2006.218.07:58:53.01/vblo/05,744.99,yes,locked 2006.218.07:58:53.01/vblo/06,752.99,yes,locked 2006.218.07:58:53.01/vblo/07,734.99,yes,locked 2006.218.07:58:53.01/vblo/08,744.99,yes,locked 2006.218.07:58:53.16/vabw/8 2006.218.07:58:53.31/vbbw/8 2006.218.07:58:53.47/xfe/off,on,15.2 2006.218.07:58:53.85/ifatt/23,28,28,28 2006.218.07:58:54.07/fmout-gps/S +4.66E-07 2006.218.07:58:54.11:!2006.218.07:59:50 2006.218.07:59:50.00:data_valid=off 2006.218.07:59:50.01:postob 2006.218.07:59:50.18/cable/+6.3835E-03 2006.218.07:59:50.19/wx/31.03,1007.5,73 2006.218.07:59:51.07/fmout-gps/S +4.67E-07 2006.218.07:59:51.08:scan_name=218-0800,k06218,60 2006.218.07:59:51.08:source=1044+719,104827.62,714335.9,2000.0,cw 2006.218.07:59:52.14#flagr#flagr/antenna,new-source 2006.218.07:59:52.15:checkk5 2006.218.07:59:52.52/chk_autoobs//k5ts1/ autoobs is running! 2006.218.07:59:52.90/chk_autoobs//k5ts2/ autoobs is running! 2006.218.07:59:53.27/chk_autoobs//k5ts3/ autoobs is running! 2006.218.07:59:53.65/chk_autoobs//k5ts4/ autoobs is running! 2006.218.07:59:54.02/chk_obsdata//k5ts1/T2180758??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:59:54.38/chk_obsdata//k5ts2/T2180758??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:59:54.75/chk_obsdata//k5ts3/T2180758??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:59:55.12/chk_obsdata//k5ts4/T2180758??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.07:59:55.81/k5log//k5ts1_log_newline 2006.218.07:59:56.50/k5log//k5ts2_log_newline 2006.218.07:59:57.19/k5log//k5ts3_log_newline 2006.218.07:59:57.90/k5log//k5ts4_log_newline 2006.218.07:59:57.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.218.07:59:57.92:4f8m12a=2 2006.218.07:59:57.92$4f8m12a/echo=on 2006.218.07:59:57.92$4f8m12a/pcalon 2006.218.07:59:57.92$pcalon/"no phase cal control is implemented here 2006.218.07:59:57.92$4f8m12a/"tpicd=stop 2006.218.07:59:57.92$4f8m12a/vc4f8 2006.218.07:59:57.92$vc4f8/valo=1,532.99 2006.218.07:59:57.93#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.218.07:59:57.93#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.218.07:59:57.93#ibcon#ireg 17 cls_cnt 0 2006.218.07:59:57.93#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.218.07:59:57.93#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.218.07:59:57.93#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.218.07:59:57.93#ibcon#enter wrdev, iclass 20, count 0 2006.218.07:59:57.93#ibcon#first serial, iclass 20, count 0 2006.218.07:59:57.93#ibcon#enter sib2, iclass 20, count 0 2006.218.07:59:57.93#ibcon#flushed, iclass 20, count 0 2006.218.07:59:57.93#ibcon#about to write, iclass 20, count 0 2006.218.07:59:57.93#ibcon#wrote, iclass 20, count 0 2006.218.07:59:57.93#ibcon#about to read 3, iclass 20, count 0 2006.218.07:59:57.97#ibcon#read 3, iclass 20, count 0 2006.218.07:59:57.97#ibcon#about to read 4, iclass 20, count 0 2006.218.07:59:57.97#ibcon#read 4, iclass 20, count 0 2006.218.07:59:57.97#ibcon#about to read 5, iclass 20, count 0 2006.218.07:59:57.97#ibcon#read 5, iclass 20, count 0 2006.218.07:59:57.97#ibcon#about to read 6, iclass 20, count 0 2006.218.07:59:57.97#ibcon#read 6, iclass 20, count 0 2006.218.07:59:57.97#ibcon#end of sib2, iclass 20, count 0 2006.218.07:59:57.97#ibcon#*mode == 0, iclass 20, count 0 2006.218.07:59:57.97#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.218.07:59:57.97#ibcon#[26=FRQ=01,532.99\r\n] 2006.218.07:59:57.97#ibcon#*before write, iclass 20, count 0 2006.218.07:59:57.97#ibcon#enter sib2, iclass 20, count 0 2006.218.07:59:57.97#ibcon#flushed, iclass 20, count 0 2006.218.07:59:57.97#ibcon#about to write, iclass 20, count 0 2006.218.07:59:57.97#ibcon#wrote, iclass 20, count 0 2006.218.07:59:57.97#ibcon#about to read 3, iclass 20, count 0 2006.218.07:59:58.01#ibcon#read 3, iclass 20, count 0 2006.218.07:59:58.01#ibcon#about to read 4, iclass 20, count 0 2006.218.07:59:58.01#ibcon#read 4, iclass 20, count 0 2006.218.07:59:58.01#ibcon#about to read 5, iclass 20, count 0 2006.218.07:59:58.01#ibcon#read 5, iclass 20, count 0 2006.218.07:59:58.01#ibcon#about to read 6, iclass 20, count 0 2006.218.07:59:58.01#ibcon#read 6, iclass 20, count 0 2006.218.07:59:58.01#ibcon#end of sib2, iclass 20, count 0 2006.218.07:59:58.01#ibcon#*after write, iclass 20, count 0 2006.218.07:59:58.01#ibcon#*before return 0, iclass 20, count 0 2006.218.07:59:58.01#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.218.07:59:58.01#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.218.07:59:58.01#ibcon#about to clear, iclass 20 cls_cnt 0 2006.218.07:59:58.01#ibcon#cleared, iclass 20 cls_cnt 0 2006.218.07:59:58.01$vc4f8/va=1,5 2006.218.07:59:58.01#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.218.07:59:58.01#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.218.07:59:58.01#ibcon#ireg 11 cls_cnt 2 2006.218.07:59:58.01#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.218.07:59:58.01#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.218.07:59:58.01#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.218.07:59:58.01#ibcon#enter wrdev, iclass 22, count 2 2006.218.07:59:58.01#ibcon#first serial, iclass 22, count 2 2006.218.07:59:58.01#ibcon#enter sib2, iclass 22, count 2 2006.218.07:59:58.01#ibcon#flushed, iclass 22, count 2 2006.218.07:59:58.01#ibcon#about to write, iclass 22, count 2 2006.218.07:59:58.01#ibcon#wrote, iclass 22, count 2 2006.218.07:59:58.01#ibcon#about to read 3, iclass 22, count 2 2006.218.07:59:58.03#ibcon#read 3, iclass 22, count 2 2006.218.07:59:58.03#ibcon#about to read 4, iclass 22, count 2 2006.218.07:59:58.03#ibcon#read 4, iclass 22, count 2 2006.218.07:59:58.03#ibcon#about to read 5, iclass 22, count 2 2006.218.07:59:58.03#ibcon#read 5, iclass 22, count 2 2006.218.07:59:58.03#ibcon#about to read 6, iclass 22, count 2 2006.218.07:59:58.03#ibcon#read 6, iclass 22, count 2 2006.218.07:59:58.03#ibcon#end of sib2, iclass 22, count 2 2006.218.07:59:58.03#ibcon#*mode == 0, iclass 22, count 2 2006.218.07:59:58.03#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.218.07:59:58.03#ibcon#[25=AT01-05\r\n] 2006.218.07:59:58.03#ibcon#*before write, iclass 22, count 2 2006.218.07:59:58.03#ibcon#enter sib2, iclass 22, count 2 2006.218.07:59:58.03#ibcon#flushed, iclass 22, count 2 2006.218.07:59:58.03#ibcon#about to write, iclass 22, count 2 2006.218.07:59:58.03#ibcon#wrote, iclass 22, count 2 2006.218.07:59:58.03#ibcon#about to read 3, iclass 22, count 2 2006.218.07:59:58.06#ibcon#read 3, iclass 22, count 2 2006.218.07:59:58.06#ibcon#about to read 4, iclass 22, count 2 2006.218.07:59:58.06#ibcon#read 4, iclass 22, count 2 2006.218.07:59:58.06#ibcon#about to read 5, iclass 22, count 2 2006.218.07:59:58.06#ibcon#read 5, iclass 22, count 2 2006.218.07:59:58.06#ibcon#about to read 6, iclass 22, count 2 2006.218.07:59:58.06#ibcon#read 6, iclass 22, count 2 2006.218.07:59:58.06#ibcon#end of sib2, iclass 22, count 2 2006.218.07:59:58.06#ibcon#*after write, iclass 22, count 2 2006.218.07:59:58.06#ibcon#*before return 0, iclass 22, count 2 2006.218.07:59:58.06#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.218.07:59:58.06#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.218.07:59:58.06#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.218.07:59:58.06#ibcon#ireg 7 cls_cnt 0 2006.218.07:59:58.06#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.218.07:59:58.18#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.218.07:59:58.18#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.218.07:59:58.18#ibcon#enter wrdev, iclass 22, count 0 2006.218.07:59:58.18#ibcon#first serial, iclass 22, count 0 2006.218.07:59:58.18#ibcon#enter sib2, iclass 22, count 0 2006.218.07:59:58.18#ibcon#flushed, iclass 22, count 0 2006.218.07:59:58.18#ibcon#about to write, iclass 22, count 0 2006.218.07:59:58.18#ibcon#wrote, iclass 22, count 0 2006.218.07:59:58.18#ibcon#about to read 3, iclass 22, count 0 2006.218.07:59:58.20#ibcon#read 3, iclass 22, count 0 2006.218.07:59:58.20#ibcon#about to read 4, iclass 22, count 0 2006.218.07:59:58.20#ibcon#read 4, iclass 22, count 0 2006.218.07:59:58.20#ibcon#about to read 5, iclass 22, count 0 2006.218.07:59:58.20#ibcon#read 5, iclass 22, count 0 2006.218.07:59:58.20#ibcon#about to read 6, iclass 22, count 0 2006.218.07:59:58.20#ibcon#read 6, iclass 22, count 0 2006.218.07:59:58.20#ibcon#end of sib2, iclass 22, count 0 2006.218.07:59:58.20#ibcon#*mode == 0, iclass 22, count 0 2006.218.07:59:58.20#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.218.07:59:58.20#ibcon#[25=USB\r\n] 2006.218.07:59:58.20#ibcon#*before write, iclass 22, count 0 2006.218.07:59:58.20#ibcon#enter sib2, iclass 22, count 0 2006.218.07:59:58.20#ibcon#flushed, iclass 22, count 0 2006.218.07:59:58.20#ibcon#about to write, iclass 22, count 0 2006.218.07:59:58.20#ibcon#wrote, iclass 22, count 0 2006.218.07:59:58.20#ibcon#about to read 3, iclass 22, count 0 2006.218.07:59:58.23#ibcon#read 3, iclass 22, count 0 2006.218.07:59:58.23#ibcon#about to read 4, iclass 22, count 0 2006.218.07:59:58.23#ibcon#read 4, iclass 22, count 0 2006.218.07:59:58.23#ibcon#about to read 5, iclass 22, count 0 2006.218.07:59:58.23#ibcon#read 5, iclass 22, count 0 2006.218.07:59:58.23#ibcon#about to read 6, iclass 22, count 0 2006.218.07:59:58.23#ibcon#read 6, iclass 22, count 0 2006.218.07:59:58.23#ibcon#end of sib2, iclass 22, count 0 2006.218.07:59:58.23#ibcon#*after write, iclass 22, count 0 2006.218.07:59:58.23#ibcon#*before return 0, iclass 22, count 0 2006.218.07:59:58.23#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.218.07:59:58.23#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.218.07:59:58.23#ibcon#about to clear, iclass 22 cls_cnt 0 2006.218.07:59:58.23#ibcon#cleared, iclass 22 cls_cnt 0 2006.218.07:59:58.23$vc4f8/valo=2,572.99 2006.218.07:59:58.23#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.218.07:59:58.23#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.218.07:59:58.23#ibcon#ireg 17 cls_cnt 0 2006.218.07:59:58.23#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.218.07:59:58.23#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.218.07:59:58.23#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.218.07:59:58.23#ibcon#enter wrdev, iclass 24, count 0 2006.218.07:59:58.23#ibcon#first serial, iclass 24, count 0 2006.218.07:59:58.23#ibcon#enter sib2, iclass 24, count 0 2006.218.07:59:58.23#ibcon#flushed, iclass 24, count 0 2006.218.07:59:58.23#ibcon#about to write, iclass 24, count 0 2006.218.07:59:58.23#ibcon#wrote, iclass 24, count 0 2006.218.07:59:58.23#ibcon#about to read 3, iclass 24, count 0 2006.218.07:59:58.25#ibcon#read 3, iclass 24, count 0 2006.218.07:59:58.25#ibcon#about to read 4, iclass 24, count 0 2006.218.07:59:58.25#ibcon#read 4, iclass 24, count 0 2006.218.07:59:58.25#ibcon#about to read 5, iclass 24, count 0 2006.218.07:59:58.25#ibcon#read 5, iclass 24, count 0 2006.218.07:59:58.25#ibcon#about to read 6, iclass 24, count 0 2006.218.07:59:58.25#ibcon#read 6, iclass 24, count 0 2006.218.07:59:58.25#ibcon#end of sib2, iclass 24, count 0 2006.218.07:59:58.25#ibcon#*mode == 0, iclass 24, count 0 2006.218.07:59:58.25#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.218.07:59:58.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.218.07:59:58.25#ibcon#*before write, iclass 24, count 0 2006.218.07:59:58.25#ibcon#enter sib2, iclass 24, count 0 2006.218.07:59:58.25#ibcon#flushed, iclass 24, count 0 2006.218.07:59:58.25#ibcon#about to write, iclass 24, count 0 2006.218.07:59:58.25#ibcon#wrote, iclass 24, count 0 2006.218.07:59:58.25#ibcon#about to read 3, iclass 24, count 0 2006.218.07:59:58.29#ibcon#read 3, iclass 24, count 0 2006.218.07:59:58.29#ibcon#about to read 4, iclass 24, count 0 2006.218.07:59:58.29#ibcon#read 4, iclass 24, count 0 2006.218.07:59:58.29#ibcon#about to read 5, iclass 24, count 0 2006.218.07:59:58.29#ibcon#read 5, iclass 24, count 0 2006.218.07:59:58.29#ibcon#about to read 6, iclass 24, count 0 2006.218.07:59:58.29#ibcon#read 6, iclass 24, count 0 2006.218.07:59:58.29#ibcon#end of sib2, iclass 24, count 0 2006.218.07:59:58.29#ibcon#*after write, iclass 24, count 0 2006.218.07:59:58.29#ibcon#*before return 0, iclass 24, count 0 2006.218.07:59:58.29#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.218.07:59:58.29#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.218.07:59:58.29#ibcon#about to clear, iclass 24 cls_cnt 0 2006.218.07:59:58.29#ibcon#cleared, iclass 24 cls_cnt 0 2006.218.07:59:58.29$vc4f8/va=2,4 2006.218.07:59:58.29#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.218.07:59:58.29#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.218.07:59:58.29#ibcon#ireg 11 cls_cnt 2 2006.218.07:59:58.29#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.218.07:59:58.35#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.218.07:59:58.35#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.218.07:59:58.35#ibcon#enter wrdev, iclass 26, count 2 2006.218.07:59:58.35#ibcon#first serial, iclass 26, count 2 2006.218.07:59:58.35#ibcon#enter sib2, iclass 26, count 2 2006.218.07:59:58.35#ibcon#flushed, iclass 26, count 2 2006.218.07:59:58.35#ibcon#about to write, iclass 26, count 2 2006.218.07:59:58.35#ibcon#wrote, iclass 26, count 2 2006.218.07:59:58.35#ibcon#about to read 3, iclass 26, count 2 2006.218.07:59:58.37#ibcon#read 3, iclass 26, count 2 2006.218.07:59:58.37#ibcon#about to read 4, iclass 26, count 2 2006.218.07:59:58.37#ibcon#read 4, iclass 26, count 2 2006.218.07:59:58.37#ibcon#about to read 5, iclass 26, count 2 2006.218.07:59:58.37#ibcon#read 5, iclass 26, count 2 2006.218.07:59:58.37#ibcon#about to read 6, iclass 26, count 2 2006.218.07:59:58.37#ibcon#read 6, iclass 26, count 2 2006.218.07:59:58.37#ibcon#end of sib2, iclass 26, count 2 2006.218.07:59:58.37#ibcon#*mode == 0, iclass 26, count 2 2006.218.07:59:58.37#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.218.07:59:58.37#ibcon#[25=AT02-04\r\n] 2006.218.07:59:58.37#ibcon#*before write, iclass 26, count 2 2006.218.07:59:58.37#ibcon#enter sib2, iclass 26, count 2 2006.218.07:59:58.37#ibcon#flushed, iclass 26, count 2 2006.218.07:59:58.37#ibcon#about to write, iclass 26, count 2 2006.218.07:59:58.37#ibcon#wrote, iclass 26, count 2 2006.218.07:59:58.37#ibcon#about to read 3, iclass 26, count 2 2006.218.07:59:58.40#ibcon#read 3, iclass 26, count 2 2006.218.07:59:58.40#ibcon#about to read 4, iclass 26, count 2 2006.218.07:59:58.40#ibcon#read 4, iclass 26, count 2 2006.218.07:59:58.40#ibcon#about to read 5, iclass 26, count 2 2006.218.07:59:58.40#ibcon#read 5, iclass 26, count 2 2006.218.07:59:58.40#ibcon#about to read 6, iclass 26, count 2 2006.218.07:59:58.40#ibcon#read 6, iclass 26, count 2 2006.218.07:59:58.40#ibcon#end of sib2, iclass 26, count 2 2006.218.07:59:58.40#ibcon#*after write, iclass 26, count 2 2006.218.07:59:58.40#ibcon#*before return 0, iclass 26, count 2 2006.218.07:59:58.40#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.218.07:59:58.40#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.218.07:59:58.40#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.218.07:59:58.40#ibcon#ireg 7 cls_cnt 0 2006.218.07:59:58.40#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.218.07:59:58.52#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.218.07:59:58.52#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.218.07:59:58.52#ibcon#enter wrdev, iclass 26, count 0 2006.218.07:59:58.52#ibcon#first serial, iclass 26, count 0 2006.218.07:59:58.52#ibcon#enter sib2, iclass 26, count 0 2006.218.07:59:58.52#ibcon#flushed, iclass 26, count 0 2006.218.07:59:58.52#ibcon#about to write, iclass 26, count 0 2006.218.07:59:58.52#ibcon#wrote, iclass 26, count 0 2006.218.07:59:58.52#ibcon#about to read 3, iclass 26, count 0 2006.218.07:59:58.54#ibcon#read 3, iclass 26, count 0 2006.218.07:59:58.54#ibcon#about to read 4, iclass 26, count 0 2006.218.07:59:58.54#ibcon#read 4, iclass 26, count 0 2006.218.07:59:58.54#ibcon#about to read 5, iclass 26, count 0 2006.218.07:59:58.54#ibcon#read 5, iclass 26, count 0 2006.218.07:59:58.54#ibcon#about to read 6, iclass 26, count 0 2006.218.07:59:58.54#ibcon#read 6, iclass 26, count 0 2006.218.07:59:58.54#ibcon#end of sib2, iclass 26, count 0 2006.218.07:59:58.54#ibcon#*mode == 0, iclass 26, count 0 2006.218.07:59:58.54#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.218.07:59:58.54#ibcon#[25=USB\r\n] 2006.218.07:59:58.54#ibcon#*before write, iclass 26, count 0 2006.218.07:59:58.54#ibcon#enter sib2, iclass 26, count 0 2006.218.07:59:58.54#ibcon#flushed, iclass 26, count 0 2006.218.07:59:58.54#ibcon#about to write, iclass 26, count 0 2006.218.07:59:58.54#ibcon#wrote, iclass 26, count 0 2006.218.07:59:58.54#ibcon#about to read 3, iclass 26, count 0 2006.218.07:59:58.57#ibcon#read 3, iclass 26, count 0 2006.218.07:59:58.57#ibcon#about to read 4, iclass 26, count 0 2006.218.07:59:58.57#ibcon#read 4, iclass 26, count 0 2006.218.07:59:58.57#ibcon#about to read 5, iclass 26, count 0 2006.218.07:59:58.57#ibcon#read 5, iclass 26, count 0 2006.218.07:59:58.57#ibcon#about to read 6, iclass 26, count 0 2006.218.07:59:58.57#ibcon#read 6, iclass 26, count 0 2006.218.07:59:58.57#ibcon#end of sib2, iclass 26, count 0 2006.218.07:59:58.57#ibcon#*after write, iclass 26, count 0 2006.218.07:59:58.57#ibcon#*before return 0, iclass 26, count 0 2006.218.07:59:58.57#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.218.07:59:58.57#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.218.07:59:58.57#ibcon#about to clear, iclass 26 cls_cnt 0 2006.218.07:59:58.57#ibcon#cleared, iclass 26 cls_cnt 0 2006.218.07:59:58.57$vc4f8/valo=3,672.99 2006.218.07:59:58.57#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.218.07:59:58.57#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.218.07:59:58.57#ibcon#ireg 17 cls_cnt 0 2006.218.07:59:58.57#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.218.07:59:58.57#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.218.07:59:58.57#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.218.07:59:58.57#ibcon#enter wrdev, iclass 28, count 0 2006.218.07:59:58.57#ibcon#first serial, iclass 28, count 0 2006.218.07:59:58.57#ibcon#enter sib2, iclass 28, count 0 2006.218.07:59:58.57#ibcon#flushed, iclass 28, count 0 2006.218.07:59:58.57#ibcon#about to write, iclass 28, count 0 2006.218.07:59:58.57#ibcon#wrote, iclass 28, count 0 2006.218.07:59:58.57#ibcon#about to read 3, iclass 28, count 0 2006.218.07:59:58.59#ibcon#read 3, iclass 28, count 0 2006.218.07:59:58.59#ibcon#about to read 4, iclass 28, count 0 2006.218.07:59:58.59#ibcon#read 4, iclass 28, count 0 2006.218.07:59:58.59#ibcon#about to read 5, iclass 28, count 0 2006.218.07:59:58.59#ibcon#read 5, iclass 28, count 0 2006.218.07:59:58.59#ibcon#about to read 6, iclass 28, count 0 2006.218.07:59:58.59#ibcon#read 6, iclass 28, count 0 2006.218.07:59:58.59#ibcon#end of sib2, iclass 28, count 0 2006.218.07:59:58.59#ibcon#*mode == 0, iclass 28, count 0 2006.218.07:59:58.59#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.218.07:59:58.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.218.07:59:58.59#ibcon#*before write, iclass 28, count 0 2006.218.07:59:58.59#ibcon#enter sib2, iclass 28, count 0 2006.218.07:59:58.59#ibcon#flushed, iclass 28, count 0 2006.218.07:59:58.59#ibcon#about to write, iclass 28, count 0 2006.218.07:59:58.59#ibcon#wrote, iclass 28, count 0 2006.218.07:59:58.59#ibcon#about to read 3, iclass 28, count 0 2006.218.07:59:58.64#ibcon#read 3, iclass 28, count 0 2006.218.07:59:58.64#ibcon#about to read 4, iclass 28, count 0 2006.218.07:59:58.64#ibcon#read 4, iclass 28, count 0 2006.218.07:59:58.64#ibcon#about to read 5, iclass 28, count 0 2006.218.07:59:58.64#ibcon#read 5, iclass 28, count 0 2006.218.07:59:58.64#ibcon#about to read 6, iclass 28, count 0 2006.218.07:59:58.64#ibcon#read 6, iclass 28, count 0 2006.218.07:59:58.64#ibcon#end of sib2, iclass 28, count 0 2006.218.07:59:58.64#ibcon#*after write, iclass 28, count 0 2006.218.07:59:58.64#ibcon#*before return 0, iclass 28, count 0 2006.218.07:59:58.64#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.218.07:59:58.64#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.218.07:59:58.64#ibcon#about to clear, iclass 28 cls_cnt 0 2006.218.07:59:58.64#ibcon#cleared, iclass 28 cls_cnt 0 2006.218.07:59:58.64$vc4f8/va=3,4 2006.218.07:59:58.64#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.218.07:59:58.64#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.218.07:59:58.64#ibcon#ireg 11 cls_cnt 2 2006.218.07:59:58.64#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.218.07:59:58.68#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.218.07:59:58.68#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.218.07:59:58.68#ibcon#enter wrdev, iclass 30, count 2 2006.218.07:59:58.68#ibcon#first serial, iclass 30, count 2 2006.218.07:59:58.68#ibcon#enter sib2, iclass 30, count 2 2006.218.07:59:58.68#ibcon#flushed, iclass 30, count 2 2006.218.07:59:58.68#ibcon#about to write, iclass 30, count 2 2006.218.07:59:58.68#ibcon#wrote, iclass 30, count 2 2006.218.07:59:58.68#ibcon#about to read 3, iclass 30, count 2 2006.218.07:59:58.71#ibcon#read 3, iclass 30, count 2 2006.218.07:59:58.71#ibcon#about to read 4, iclass 30, count 2 2006.218.07:59:58.71#ibcon#read 4, iclass 30, count 2 2006.218.07:59:58.71#ibcon#about to read 5, iclass 30, count 2 2006.218.07:59:58.71#ibcon#read 5, iclass 30, count 2 2006.218.07:59:58.71#ibcon#about to read 6, iclass 30, count 2 2006.218.07:59:58.71#ibcon#read 6, iclass 30, count 2 2006.218.07:59:58.71#ibcon#end of sib2, iclass 30, count 2 2006.218.07:59:58.71#ibcon#*mode == 0, iclass 30, count 2 2006.218.07:59:58.71#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.218.07:59:58.71#ibcon#[25=AT03-04\r\n] 2006.218.07:59:58.71#ibcon#*before write, iclass 30, count 2 2006.218.07:59:58.71#ibcon#enter sib2, iclass 30, count 2 2006.218.07:59:58.71#ibcon#flushed, iclass 30, count 2 2006.218.07:59:58.71#ibcon#about to write, iclass 30, count 2 2006.218.07:59:58.71#ibcon#wrote, iclass 30, count 2 2006.218.07:59:58.71#ibcon#about to read 3, iclass 30, count 2 2006.218.07:59:58.74#ibcon#read 3, iclass 30, count 2 2006.218.07:59:58.74#ibcon#about to read 4, iclass 30, count 2 2006.218.07:59:58.74#ibcon#read 4, iclass 30, count 2 2006.218.07:59:58.74#ibcon#about to read 5, iclass 30, count 2 2006.218.07:59:58.74#ibcon#read 5, iclass 30, count 2 2006.218.07:59:58.74#ibcon#about to read 6, iclass 30, count 2 2006.218.07:59:58.74#ibcon#read 6, iclass 30, count 2 2006.218.07:59:58.74#ibcon#end of sib2, iclass 30, count 2 2006.218.07:59:58.74#ibcon#*after write, iclass 30, count 2 2006.218.07:59:58.74#ibcon#*before return 0, iclass 30, count 2 2006.218.07:59:58.74#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.218.07:59:58.74#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.218.07:59:58.74#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.218.07:59:58.74#ibcon#ireg 7 cls_cnt 0 2006.218.07:59:58.74#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.218.07:59:58.86#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.218.07:59:58.86#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.218.07:59:58.86#ibcon#enter wrdev, iclass 30, count 0 2006.218.07:59:58.86#ibcon#first serial, iclass 30, count 0 2006.218.07:59:58.86#ibcon#enter sib2, iclass 30, count 0 2006.218.07:59:58.86#ibcon#flushed, iclass 30, count 0 2006.218.07:59:58.86#ibcon#about to write, iclass 30, count 0 2006.218.07:59:58.86#ibcon#wrote, iclass 30, count 0 2006.218.07:59:58.86#ibcon#about to read 3, iclass 30, count 0 2006.218.07:59:58.88#ibcon#read 3, iclass 30, count 0 2006.218.07:59:58.88#ibcon#about to read 4, iclass 30, count 0 2006.218.07:59:58.88#ibcon#read 4, iclass 30, count 0 2006.218.07:59:58.88#ibcon#about to read 5, iclass 30, count 0 2006.218.07:59:58.88#ibcon#read 5, iclass 30, count 0 2006.218.07:59:58.88#ibcon#about to read 6, iclass 30, count 0 2006.218.07:59:58.88#ibcon#read 6, iclass 30, count 0 2006.218.07:59:58.88#ibcon#end of sib2, iclass 30, count 0 2006.218.07:59:58.88#ibcon#*mode == 0, iclass 30, count 0 2006.218.07:59:58.88#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.218.07:59:58.88#ibcon#[25=USB\r\n] 2006.218.07:59:58.88#ibcon#*before write, iclass 30, count 0 2006.218.07:59:58.88#ibcon#enter sib2, iclass 30, count 0 2006.218.07:59:58.88#ibcon#flushed, iclass 30, count 0 2006.218.07:59:58.88#ibcon#about to write, iclass 30, count 0 2006.218.07:59:58.88#ibcon#wrote, iclass 30, count 0 2006.218.07:59:58.88#ibcon#about to read 3, iclass 30, count 0 2006.218.07:59:58.91#ibcon#read 3, iclass 30, count 0 2006.218.07:59:58.91#ibcon#about to read 4, iclass 30, count 0 2006.218.07:59:58.91#ibcon#read 4, iclass 30, count 0 2006.218.07:59:58.91#ibcon#about to read 5, iclass 30, count 0 2006.218.07:59:58.91#ibcon#read 5, iclass 30, count 0 2006.218.07:59:58.91#ibcon#about to read 6, iclass 30, count 0 2006.218.07:59:58.91#ibcon#read 6, iclass 30, count 0 2006.218.07:59:58.91#ibcon#end of sib2, iclass 30, count 0 2006.218.07:59:58.91#ibcon#*after write, iclass 30, count 0 2006.218.07:59:58.91#ibcon#*before return 0, iclass 30, count 0 2006.218.07:59:58.91#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.218.07:59:58.91#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.218.07:59:58.91#ibcon#about to clear, iclass 30 cls_cnt 0 2006.218.07:59:58.91#ibcon#cleared, iclass 30 cls_cnt 0 2006.218.07:59:58.91$vc4f8/valo=4,832.99 2006.218.07:59:58.91#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.218.07:59:58.91#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.218.07:59:58.91#ibcon#ireg 17 cls_cnt 0 2006.218.07:59:58.91#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.218.07:59:58.91#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.218.07:59:58.91#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.218.07:59:58.91#ibcon#enter wrdev, iclass 32, count 0 2006.218.07:59:58.91#ibcon#first serial, iclass 32, count 0 2006.218.07:59:58.91#ibcon#enter sib2, iclass 32, count 0 2006.218.07:59:58.91#ibcon#flushed, iclass 32, count 0 2006.218.07:59:58.91#ibcon#about to write, iclass 32, count 0 2006.218.07:59:58.91#ibcon#wrote, iclass 32, count 0 2006.218.07:59:58.91#ibcon#about to read 3, iclass 32, count 0 2006.218.07:59:58.93#ibcon#read 3, iclass 32, count 0 2006.218.07:59:58.93#ibcon#about to read 4, iclass 32, count 0 2006.218.07:59:58.93#ibcon#read 4, iclass 32, count 0 2006.218.07:59:58.93#ibcon#about to read 5, iclass 32, count 0 2006.218.07:59:58.93#ibcon#read 5, iclass 32, count 0 2006.218.07:59:58.93#ibcon#about to read 6, iclass 32, count 0 2006.218.07:59:58.93#ibcon#read 6, iclass 32, count 0 2006.218.07:59:58.93#ibcon#end of sib2, iclass 32, count 0 2006.218.07:59:58.93#ibcon#*mode == 0, iclass 32, count 0 2006.218.07:59:58.93#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.218.07:59:58.93#ibcon#[26=FRQ=04,832.99\r\n] 2006.218.07:59:58.93#ibcon#*before write, iclass 32, count 0 2006.218.07:59:58.93#ibcon#enter sib2, iclass 32, count 0 2006.218.07:59:58.93#ibcon#flushed, iclass 32, count 0 2006.218.07:59:58.93#ibcon#about to write, iclass 32, count 0 2006.218.07:59:58.93#ibcon#wrote, iclass 32, count 0 2006.218.07:59:58.93#ibcon#about to read 3, iclass 32, count 0 2006.218.07:59:58.97#ibcon#read 3, iclass 32, count 0 2006.218.07:59:58.97#ibcon#about to read 4, iclass 32, count 0 2006.218.07:59:58.97#ibcon#read 4, iclass 32, count 0 2006.218.07:59:58.97#ibcon#about to read 5, iclass 32, count 0 2006.218.07:59:58.97#ibcon#read 5, iclass 32, count 0 2006.218.07:59:58.97#ibcon#about to read 6, iclass 32, count 0 2006.218.07:59:58.97#ibcon#read 6, iclass 32, count 0 2006.218.07:59:58.97#ibcon#end of sib2, iclass 32, count 0 2006.218.07:59:58.97#ibcon#*after write, iclass 32, count 0 2006.218.07:59:58.97#ibcon#*before return 0, iclass 32, count 0 2006.218.07:59:58.97#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.218.07:59:58.97#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.218.07:59:58.97#ibcon#about to clear, iclass 32 cls_cnt 0 2006.218.07:59:58.97#ibcon#cleared, iclass 32 cls_cnt 0 2006.218.07:59:58.97$vc4f8/va=4,4 2006.218.07:59:58.97#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.218.07:59:58.97#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.218.07:59:58.97#ibcon#ireg 11 cls_cnt 2 2006.218.07:59:58.97#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.218.07:59:59.03#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.218.07:59:59.03#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.218.07:59:59.03#ibcon#enter wrdev, iclass 34, count 2 2006.218.07:59:59.03#ibcon#first serial, iclass 34, count 2 2006.218.07:59:59.03#ibcon#enter sib2, iclass 34, count 2 2006.218.07:59:59.03#ibcon#flushed, iclass 34, count 2 2006.218.07:59:59.03#ibcon#about to write, iclass 34, count 2 2006.218.07:59:59.03#ibcon#wrote, iclass 34, count 2 2006.218.07:59:59.03#ibcon#about to read 3, iclass 34, count 2 2006.218.07:59:59.05#ibcon#read 3, iclass 34, count 2 2006.218.07:59:59.05#ibcon#about to read 4, iclass 34, count 2 2006.218.07:59:59.05#ibcon#read 4, iclass 34, count 2 2006.218.07:59:59.05#ibcon#about to read 5, iclass 34, count 2 2006.218.07:59:59.05#ibcon#read 5, iclass 34, count 2 2006.218.07:59:59.05#ibcon#about to read 6, iclass 34, count 2 2006.218.07:59:59.05#ibcon#read 6, iclass 34, count 2 2006.218.07:59:59.05#ibcon#end of sib2, iclass 34, count 2 2006.218.07:59:59.05#ibcon#*mode == 0, iclass 34, count 2 2006.218.07:59:59.05#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.218.07:59:59.05#ibcon#[25=AT04-04\r\n] 2006.218.07:59:59.05#ibcon#*before write, iclass 34, count 2 2006.218.07:59:59.05#ibcon#enter sib2, iclass 34, count 2 2006.218.07:59:59.05#ibcon#flushed, iclass 34, count 2 2006.218.07:59:59.05#ibcon#about to write, iclass 34, count 2 2006.218.07:59:59.05#ibcon#wrote, iclass 34, count 2 2006.218.07:59:59.05#ibcon#about to read 3, iclass 34, count 2 2006.218.07:59:59.08#ibcon#read 3, iclass 34, count 2 2006.218.07:59:59.08#ibcon#about to read 4, iclass 34, count 2 2006.218.07:59:59.08#ibcon#read 4, iclass 34, count 2 2006.218.07:59:59.08#ibcon#about to read 5, iclass 34, count 2 2006.218.07:59:59.08#ibcon#read 5, iclass 34, count 2 2006.218.07:59:59.08#ibcon#about to read 6, iclass 34, count 2 2006.218.07:59:59.08#ibcon#read 6, iclass 34, count 2 2006.218.07:59:59.08#ibcon#end of sib2, iclass 34, count 2 2006.218.07:59:59.08#ibcon#*after write, iclass 34, count 2 2006.218.07:59:59.08#ibcon#*before return 0, iclass 34, count 2 2006.218.07:59:59.08#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.218.07:59:59.08#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.218.07:59:59.08#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.218.07:59:59.08#ibcon#ireg 7 cls_cnt 0 2006.218.07:59:59.08#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.218.07:59:59.20#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.218.07:59:59.20#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.218.07:59:59.20#ibcon#enter wrdev, iclass 34, count 0 2006.218.07:59:59.20#ibcon#first serial, iclass 34, count 0 2006.218.07:59:59.20#ibcon#enter sib2, iclass 34, count 0 2006.218.07:59:59.20#ibcon#flushed, iclass 34, count 0 2006.218.07:59:59.20#ibcon#about to write, iclass 34, count 0 2006.218.07:59:59.20#ibcon#wrote, iclass 34, count 0 2006.218.07:59:59.20#ibcon#about to read 3, iclass 34, count 0 2006.218.07:59:59.22#ibcon#read 3, iclass 34, count 0 2006.218.07:59:59.22#ibcon#about to read 4, iclass 34, count 0 2006.218.07:59:59.22#ibcon#read 4, iclass 34, count 0 2006.218.07:59:59.22#ibcon#about to read 5, iclass 34, count 0 2006.218.07:59:59.22#ibcon#read 5, iclass 34, count 0 2006.218.07:59:59.22#ibcon#about to read 6, iclass 34, count 0 2006.218.07:59:59.22#ibcon#read 6, iclass 34, count 0 2006.218.07:59:59.22#ibcon#end of sib2, iclass 34, count 0 2006.218.07:59:59.22#ibcon#*mode == 0, iclass 34, count 0 2006.218.07:59:59.22#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.218.07:59:59.22#ibcon#[25=USB\r\n] 2006.218.07:59:59.22#ibcon#*before write, iclass 34, count 0 2006.218.07:59:59.22#ibcon#enter sib2, iclass 34, count 0 2006.218.07:59:59.22#ibcon#flushed, iclass 34, count 0 2006.218.07:59:59.22#ibcon#about to write, iclass 34, count 0 2006.218.07:59:59.22#ibcon#wrote, iclass 34, count 0 2006.218.07:59:59.22#ibcon#about to read 3, iclass 34, count 0 2006.218.07:59:59.25#ibcon#read 3, iclass 34, count 0 2006.218.07:59:59.25#ibcon#about to read 4, iclass 34, count 0 2006.218.07:59:59.25#ibcon#read 4, iclass 34, count 0 2006.218.07:59:59.25#ibcon#about to read 5, iclass 34, count 0 2006.218.07:59:59.25#ibcon#read 5, iclass 34, count 0 2006.218.07:59:59.25#ibcon#about to read 6, iclass 34, count 0 2006.218.07:59:59.25#ibcon#read 6, iclass 34, count 0 2006.218.07:59:59.25#ibcon#end of sib2, iclass 34, count 0 2006.218.07:59:59.25#ibcon#*after write, iclass 34, count 0 2006.218.07:59:59.25#ibcon#*before return 0, iclass 34, count 0 2006.218.07:59:59.25#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.218.07:59:59.25#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.218.07:59:59.25#ibcon#about to clear, iclass 34 cls_cnt 0 2006.218.07:59:59.25#ibcon#cleared, iclass 34 cls_cnt 0 2006.218.07:59:59.25$vc4f8/valo=5,652.99 2006.218.07:59:59.25#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.218.07:59:59.25#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.218.07:59:59.25#ibcon#ireg 17 cls_cnt 0 2006.218.07:59:59.25#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.218.07:59:59.25#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.218.07:59:59.25#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.218.07:59:59.25#ibcon#enter wrdev, iclass 36, count 0 2006.218.07:59:59.25#ibcon#first serial, iclass 36, count 0 2006.218.07:59:59.25#ibcon#enter sib2, iclass 36, count 0 2006.218.07:59:59.25#ibcon#flushed, iclass 36, count 0 2006.218.07:59:59.25#ibcon#about to write, iclass 36, count 0 2006.218.07:59:59.25#ibcon#wrote, iclass 36, count 0 2006.218.07:59:59.25#ibcon#about to read 3, iclass 36, count 0 2006.218.07:59:59.27#ibcon#read 3, iclass 36, count 0 2006.218.07:59:59.27#ibcon#about to read 4, iclass 36, count 0 2006.218.07:59:59.27#ibcon#read 4, iclass 36, count 0 2006.218.07:59:59.27#ibcon#about to read 5, iclass 36, count 0 2006.218.07:59:59.27#ibcon#read 5, iclass 36, count 0 2006.218.07:59:59.27#ibcon#about to read 6, iclass 36, count 0 2006.218.07:59:59.27#ibcon#read 6, iclass 36, count 0 2006.218.07:59:59.27#ibcon#end of sib2, iclass 36, count 0 2006.218.07:59:59.27#ibcon#*mode == 0, iclass 36, count 0 2006.218.07:59:59.27#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.218.07:59:59.27#ibcon#[26=FRQ=05,652.99\r\n] 2006.218.07:59:59.27#ibcon#*before write, iclass 36, count 0 2006.218.07:59:59.27#ibcon#enter sib2, iclass 36, count 0 2006.218.07:59:59.27#ibcon#flushed, iclass 36, count 0 2006.218.07:59:59.27#ibcon#about to write, iclass 36, count 0 2006.218.07:59:59.27#ibcon#wrote, iclass 36, count 0 2006.218.07:59:59.27#ibcon#about to read 3, iclass 36, count 0 2006.218.07:59:59.31#ibcon#read 3, iclass 36, count 0 2006.218.07:59:59.31#ibcon#about to read 4, iclass 36, count 0 2006.218.07:59:59.31#ibcon#read 4, iclass 36, count 0 2006.218.07:59:59.31#ibcon#about to read 5, iclass 36, count 0 2006.218.07:59:59.31#ibcon#read 5, iclass 36, count 0 2006.218.07:59:59.31#ibcon#about to read 6, iclass 36, count 0 2006.218.07:59:59.31#ibcon#read 6, iclass 36, count 0 2006.218.07:59:59.31#ibcon#end of sib2, iclass 36, count 0 2006.218.07:59:59.31#ibcon#*after write, iclass 36, count 0 2006.218.07:59:59.31#ibcon#*before return 0, iclass 36, count 0 2006.218.07:59:59.31#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.218.07:59:59.31#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.218.07:59:59.31#ibcon#about to clear, iclass 36 cls_cnt 0 2006.218.07:59:59.31#ibcon#cleared, iclass 36 cls_cnt 0 2006.218.07:59:59.31$vc4f8/va=5,7 2006.218.07:59:59.31#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.218.07:59:59.31#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.218.07:59:59.31#ibcon#ireg 11 cls_cnt 2 2006.218.07:59:59.31#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.218.07:59:59.37#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.218.07:59:59.37#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.218.07:59:59.37#ibcon#enter wrdev, iclass 38, count 2 2006.218.07:59:59.37#ibcon#first serial, iclass 38, count 2 2006.218.07:59:59.37#ibcon#enter sib2, iclass 38, count 2 2006.218.07:59:59.37#ibcon#flushed, iclass 38, count 2 2006.218.07:59:59.37#ibcon#about to write, iclass 38, count 2 2006.218.07:59:59.37#ibcon#wrote, iclass 38, count 2 2006.218.07:59:59.37#ibcon#about to read 3, iclass 38, count 2 2006.218.07:59:59.39#ibcon#read 3, iclass 38, count 2 2006.218.07:59:59.39#ibcon#about to read 4, iclass 38, count 2 2006.218.07:59:59.39#ibcon#read 4, iclass 38, count 2 2006.218.07:59:59.39#ibcon#about to read 5, iclass 38, count 2 2006.218.07:59:59.39#ibcon#read 5, iclass 38, count 2 2006.218.07:59:59.39#ibcon#about to read 6, iclass 38, count 2 2006.218.07:59:59.39#ibcon#read 6, iclass 38, count 2 2006.218.07:59:59.39#ibcon#end of sib2, iclass 38, count 2 2006.218.07:59:59.39#ibcon#*mode == 0, iclass 38, count 2 2006.218.07:59:59.39#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.218.07:59:59.39#ibcon#[25=AT05-07\r\n] 2006.218.07:59:59.39#ibcon#*before write, iclass 38, count 2 2006.218.07:59:59.39#ibcon#enter sib2, iclass 38, count 2 2006.218.07:59:59.39#ibcon#flushed, iclass 38, count 2 2006.218.07:59:59.39#ibcon#about to write, iclass 38, count 2 2006.218.07:59:59.39#ibcon#wrote, iclass 38, count 2 2006.218.07:59:59.39#ibcon#about to read 3, iclass 38, count 2 2006.218.07:59:59.42#ibcon#read 3, iclass 38, count 2 2006.218.07:59:59.42#ibcon#about to read 4, iclass 38, count 2 2006.218.07:59:59.42#ibcon#read 4, iclass 38, count 2 2006.218.07:59:59.42#ibcon#about to read 5, iclass 38, count 2 2006.218.07:59:59.42#ibcon#read 5, iclass 38, count 2 2006.218.07:59:59.42#ibcon#about to read 6, iclass 38, count 2 2006.218.07:59:59.42#ibcon#read 6, iclass 38, count 2 2006.218.07:59:59.42#ibcon#end of sib2, iclass 38, count 2 2006.218.07:59:59.42#ibcon#*after write, iclass 38, count 2 2006.218.07:59:59.42#ibcon#*before return 0, iclass 38, count 2 2006.218.07:59:59.42#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.218.07:59:59.42#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.218.07:59:59.42#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.218.07:59:59.42#ibcon#ireg 7 cls_cnt 0 2006.218.07:59:59.42#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.218.07:59:59.54#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.218.07:59:59.54#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.218.07:59:59.54#ibcon#enter wrdev, iclass 38, count 0 2006.218.07:59:59.54#ibcon#first serial, iclass 38, count 0 2006.218.07:59:59.54#ibcon#enter sib2, iclass 38, count 0 2006.218.07:59:59.54#ibcon#flushed, iclass 38, count 0 2006.218.07:59:59.54#ibcon#about to write, iclass 38, count 0 2006.218.07:59:59.54#ibcon#wrote, iclass 38, count 0 2006.218.07:59:59.54#ibcon#about to read 3, iclass 38, count 0 2006.218.07:59:59.56#ibcon#read 3, iclass 38, count 0 2006.218.07:59:59.56#ibcon#about to read 4, iclass 38, count 0 2006.218.07:59:59.56#ibcon#read 4, iclass 38, count 0 2006.218.07:59:59.56#ibcon#about to read 5, iclass 38, count 0 2006.218.07:59:59.56#ibcon#read 5, iclass 38, count 0 2006.218.07:59:59.56#ibcon#about to read 6, iclass 38, count 0 2006.218.07:59:59.56#ibcon#read 6, iclass 38, count 0 2006.218.07:59:59.56#ibcon#end of sib2, iclass 38, count 0 2006.218.07:59:59.56#ibcon#*mode == 0, iclass 38, count 0 2006.218.07:59:59.56#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.218.07:59:59.56#ibcon#[25=USB\r\n] 2006.218.07:59:59.56#ibcon#*before write, iclass 38, count 0 2006.218.07:59:59.56#ibcon#enter sib2, iclass 38, count 0 2006.218.07:59:59.56#ibcon#flushed, iclass 38, count 0 2006.218.07:59:59.56#ibcon#about to write, iclass 38, count 0 2006.218.07:59:59.56#ibcon#wrote, iclass 38, count 0 2006.218.07:59:59.56#ibcon#about to read 3, iclass 38, count 0 2006.218.07:59:59.59#ibcon#read 3, iclass 38, count 0 2006.218.07:59:59.59#ibcon#about to read 4, iclass 38, count 0 2006.218.07:59:59.59#ibcon#read 4, iclass 38, count 0 2006.218.07:59:59.59#ibcon#about to read 5, iclass 38, count 0 2006.218.07:59:59.59#ibcon#read 5, iclass 38, count 0 2006.218.07:59:59.59#ibcon#about to read 6, iclass 38, count 0 2006.218.07:59:59.59#ibcon#read 6, iclass 38, count 0 2006.218.07:59:59.59#ibcon#end of sib2, iclass 38, count 0 2006.218.07:59:59.59#ibcon#*after write, iclass 38, count 0 2006.218.07:59:59.59#ibcon#*before return 0, iclass 38, count 0 2006.218.07:59:59.59#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.218.07:59:59.59#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.218.07:59:59.59#ibcon#about to clear, iclass 38 cls_cnt 0 2006.218.07:59:59.59#ibcon#cleared, iclass 38 cls_cnt 0 2006.218.07:59:59.59$vc4f8/valo=6,772.99 2006.218.07:59:59.59#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.218.07:59:59.59#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.218.07:59:59.59#ibcon#ireg 17 cls_cnt 0 2006.218.07:59:59.59#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.218.07:59:59.59#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.218.07:59:59.59#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.218.07:59:59.59#ibcon#enter wrdev, iclass 40, count 0 2006.218.07:59:59.59#ibcon#first serial, iclass 40, count 0 2006.218.07:59:59.59#ibcon#enter sib2, iclass 40, count 0 2006.218.07:59:59.59#ibcon#flushed, iclass 40, count 0 2006.218.07:59:59.59#ibcon#about to write, iclass 40, count 0 2006.218.07:59:59.59#ibcon#wrote, iclass 40, count 0 2006.218.07:59:59.59#ibcon#about to read 3, iclass 40, count 0 2006.218.07:59:59.61#ibcon#read 3, iclass 40, count 0 2006.218.07:59:59.61#ibcon#about to read 4, iclass 40, count 0 2006.218.07:59:59.61#ibcon#read 4, iclass 40, count 0 2006.218.07:59:59.61#ibcon#about to read 5, iclass 40, count 0 2006.218.07:59:59.61#ibcon#read 5, iclass 40, count 0 2006.218.07:59:59.61#ibcon#about to read 6, iclass 40, count 0 2006.218.07:59:59.61#ibcon#read 6, iclass 40, count 0 2006.218.07:59:59.61#ibcon#end of sib2, iclass 40, count 0 2006.218.07:59:59.61#ibcon#*mode == 0, iclass 40, count 0 2006.218.07:59:59.61#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.218.07:59:59.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.218.07:59:59.61#ibcon#*before write, iclass 40, count 0 2006.218.07:59:59.61#ibcon#enter sib2, iclass 40, count 0 2006.218.07:59:59.61#ibcon#flushed, iclass 40, count 0 2006.218.07:59:59.61#ibcon#about to write, iclass 40, count 0 2006.218.07:59:59.61#ibcon#wrote, iclass 40, count 0 2006.218.07:59:59.61#ibcon#about to read 3, iclass 40, count 0 2006.218.07:59:59.65#ibcon#read 3, iclass 40, count 0 2006.218.07:59:59.65#ibcon#about to read 4, iclass 40, count 0 2006.218.07:59:59.65#ibcon#read 4, iclass 40, count 0 2006.218.07:59:59.65#ibcon#about to read 5, iclass 40, count 0 2006.218.07:59:59.65#ibcon#read 5, iclass 40, count 0 2006.218.07:59:59.65#ibcon#about to read 6, iclass 40, count 0 2006.218.07:59:59.65#ibcon#read 6, iclass 40, count 0 2006.218.07:59:59.65#ibcon#end of sib2, iclass 40, count 0 2006.218.07:59:59.65#ibcon#*after write, iclass 40, count 0 2006.218.07:59:59.65#ibcon#*before return 0, iclass 40, count 0 2006.218.07:59:59.65#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.218.07:59:59.65#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.218.07:59:59.65#ibcon#about to clear, iclass 40 cls_cnt 0 2006.218.07:59:59.65#ibcon#cleared, iclass 40 cls_cnt 0 2006.218.07:59:59.65$vc4f8/va=6,6 2006.218.07:59:59.65#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.218.07:59:59.65#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.218.07:59:59.65#ibcon#ireg 11 cls_cnt 2 2006.218.07:59:59.65#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.218.07:59:59.71#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.218.07:59:59.71#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.218.07:59:59.71#ibcon#enter wrdev, iclass 4, count 2 2006.218.07:59:59.71#ibcon#first serial, iclass 4, count 2 2006.218.07:59:59.71#ibcon#enter sib2, iclass 4, count 2 2006.218.07:59:59.71#ibcon#flushed, iclass 4, count 2 2006.218.07:59:59.71#ibcon#about to write, iclass 4, count 2 2006.218.07:59:59.71#ibcon#wrote, iclass 4, count 2 2006.218.07:59:59.71#ibcon#about to read 3, iclass 4, count 2 2006.218.07:59:59.73#ibcon#read 3, iclass 4, count 2 2006.218.07:59:59.73#ibcon#about to read 4, iclass 4, count 2 2006.218.07:59:59.73#ibcon#read 4, iclass 4, count 2 2006.218.07:59:59.73#ibcon#about to read 5, iclass 4, count 2 2006.218.07:59:59.73#ibcon#read 5, iclass 4, count 2 2006.218.07:59:59.73#ibcon#about to read 6, iclass 4, count 2 2006.218.07:59:59.73#ibcon#read 6, iclass 4, count 2 2006.218.07:59:59.73#ibcon#end of sib2, iclass 4, count 2 2006.218.07:59:59.73#ibcon#*mode == 0, iclass 4, count 2 2006.218.07:59:59.73#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.218.07:59:59.73#ibcon#[25=AT06-06\r\n] 2006.218.07:59:59.73#ibcon#*before write, iclass 4, count 2 2006.218.07:59:59.73#ibcon#enter sib2, iclass 4, count 2 2006.218.07:59:59.73#ibcon#flushed, iclass 4, count 2 2006.218.07:59:59.73#ibcon#about to write, iclass 4, count 2 2006.218.07:59:59.73#ibcon#wrote, iclass 4, count 2 2006.218.07:59:59.73#ibcon#about to read 3, iclass 4, count 2 2006.218.07:59:59.76#ibcon#read 3, iclass 4, count 2 2006.218.07:59:59.76#ibcon#about to read 4, iclass 4, count 2 2006.218.07:59:59.76#ibcon#read 4, iclass 4, count 2 2006.218.07:59:59.76#ibcon#about to read 5, iclass 4, count 2 2006.218.07:59:59.76#ibcon#read 5, iclass 4, count 2 2006.218.07:59:59.76#ibcon#about to read 6, iclass 4, count 2 2006.218.07:59:59.76#ibcon#read 6, iclass 4, count 2 2006.218.07:59:59.76#ibcon#end of sib2, iclass 4, count 2 2006.218.07:59:59.76#ibcon#*after write, iclass 4, count 2 2006.218.07:59:59.76#ibcon#*before return 0, iclass 4, count 2 2006.218.07:59:59.76#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.218.07:59:59.76#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.218.07:59:59.76#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.218.07:59:59.76#ibcon#ireg 7 cls_cnt 0 2006.218.07:59:59.76#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.218.07:59:59.88#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.218.07:59:59.88#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.218.07:59:59.88#ibcon#enter wrdev, iclass 4, count 0 2006.218.07:59:59.88#ibcon#first serial, iclass 4, count 0 2006.218.07:59:59.88#ibcon#enter sib2, iclass 4, count 0 2006.218.07:59:59.88#ibcon#flushed, iclass 4, count 0 2006.218.07:59:59.88#ibcon#about to write, iclass 4, count 0 2006.218.07:59:59.88#ibcon#wrote, iclass 4, count 0 2006.218.07:59:59.88#ibcon#about to read 3, iclass 4, count 0 2006.218.07:59:59.90#ibcon#read 3, iclass 4, count 0 2006.218.07:59:59.90#ibcon#about to read 4, iclass 4, count 0 2006.218.07:59:59.90#ibcon#read 4, iclass 4, count 0 2006.218.07:59:59.90#ibcon#about to read 5, iclass 4, count 0 2006.218.07:59:59.90#ibcon#read 5, iclass 4, count 0 2006.218.07:59:59.90#ibcon#about to read 6, iclass 4, count 0 2006.218.07:59:59.90#ibcon#read 6, iclass 4, count 0 2006.218.07:59:59.90#ibcon#end of sib2, iclass 4, count 0 2006.218.07:59:59.90#ibcon#*mode == 0, iclass 4, count 0 2006.218.07:59:59.90#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.218.07:59:59.90#ibcon#[25=USB\r\n] 2006.218.07:59:59.90#ibcon#*before write, iclass 4, count 0 2006.218.07:59:59.90#ibcon#enter sib2, iclass 4, count 0 2006.218.07:59:59.90#ibcon#flushed, iclass 4, count 0 2006.218.07:59:59.90#ibcon#about to write, iclass 4, count 0 2006.218.07:59:59.90#ibcon#wrote, iclass 4, count 0 2006.218.07:59:59.90#ibcon#about to read 3, iclass 4, count 0 2006.218.07:59:59.93#ibcon#read 3, iclass 4, count 0 2006.218.07:59:59.93#ibcon#about to read 4, iclass 4, count 0 2006.218.07:59:59.93#ibcon#read 4, iclass 4, count 0 2006.218.07:59:59.93#ibcon#about to read 5, iclass 4, count 0 2006.218.07:59:59.93#ibcon#read 5, iclass 4, count 0 2006.218.07:59:59.93#ibcon#about to read 6, iclass 4, count 0 2006.218.07:59:59.93#ibcon#read 6, iclass 4, count 0 2006.218.07:59:59.93#ibcon#end of sib2, iclass 4, count 0 2006.218.07:59:59.93#ibcon#*after write, iclass 4, count 0 2006.218.07:59:59.93#ibcon#*before return 0, iclass 4, count 0 2006.218.07:59:59.93#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.218.07:59:59.93#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.218.07:59:59.93#ibcon#about to clear, iclass 4 cls_cnt 0 2006.218.07:59:59.93#ibcon#cleared, iclass 4 cls_cnt 0 2006.218.07:59:59.93$vc4f8/valo=7,832.99 2006.218.07:59:59.93#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.218.07:59:59.93#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.218.07:59:59.93#ibcon#ireg 17 cls_cnt 0 2006.218.07:59:59.93#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.218.07:59:59.93#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.218.07:59:59.93#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.218.07:59:59.93#ibcon#enter wrdev, iclass 6, count 0 2006.218.07:59:59.93#ibcon#first serial, iclass 6, count 0 2006.218.07:59:59.93#ibcon#enter sib2, iclass 6, count 0 2006.218.07:59:59.93#ibcon#flushed, iclass 6, count 0 2006.218.07:59:59.93#ibcon#about to write, iclass 6, count 0 2006.218.07:59:59.93#ibcon#wrote, iclass 6, count 0 2006.218.07:59:59.93#ibcon#about to read 3, iclass 6, count 0 2006.218.07:59:59.95#ibcon#read 3, iclass 6, count 0 2006.218.07:59:59.95#ibcon#about to read 4, iclass 6, count 0 2006.218.07:59:59.95#ibcon#read 4, iclass 6, count 0 2006.218.07:59:59.95#ibcon#about to read 5, iclass 6, count 0 2006.218.07:59:59.95#ibcon#read 5, iclass 6, count 0 2006.218.07:59:59.95#ibcon#about to read 6, iclass 6, count 0 2006.218.07:59:59.95#ibcon#read 6, iclass 6, count 0 2006.218.07:59:59.95#ibcon#end of sib2, iclass 6, count 0 2006.218.07:59:59.95#ibcon#*mode == 0, iclass 6, count 0 2006.218.07:59:59.95#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.218.07:59:59.95#ibcon#[26=FRQ=07,832.99\r\n] 2006.218.07:59:59.95#ibcon#*before write, iclass 6, count 0 2006.218.07:59:59.95#ibcon#enter sib2, iclass 6, count 0 2006.218.07:59:59.95#ibcon#flushed, iclass 6, count 0 2006.218.07:59:59.95#ibcon#about to write, iclass 6, count 0 2006.218.07:59:59.95#ibcon#wrote, iclass 6, count 0 2006.218.07:59:59.95#ibcon#about to read 3, iclass 6, count 0 2006.218.07:59:59.99#ibcon#read 3, iclass 6, count 0 2006.218.07:59:59.99#ibcon#about to read 4, iclass 6, count 0 2006.218.07:59:59.99#ibcon#read 4, iclass 6, count 0 2006.218.07:59:59.99#ibcon#about to read 5, iclass 6, count 0 2006.218.07:59:59.99#ibcon#read 5, iclass 6, count 0 2006.218.07:59:59.99#ibcon#about to read 6, iclass 6, count 0 2006.218.07:59:59.99#ibcon#read 6, iclass 6, count 0 2006.218.07:59:59.99#ibcon#end of sib2, iclass 6, count 0 2006.218.07:59:59.99#ibcon#*after write, iclass 6, count 0 2006.218.07:59:59.99#ibcon#*before return 0, iclass 6, count 0 2006.218.07:59:59.99#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.218.07:59:59.99#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.218.07:59:59.99#ibcon#about to clear, iclass 6 cls_cnt 0 2006.218.07:59:59.99#ibcon#cleared, iclass 6 cls_cnt 0 2006.218.07:59:59.99$vc4f8/va=7,6 2006.218.07:59:59.99#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.218.07:59:59.99#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.218.07:59:59.99#ibcon#ireg 11 cls_cnt 2 2006.218.07:59:59.99#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.218.08:00:00.05#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.218.08:00:00.05#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.218.08:00:00.05#ibcon#enter wrdev, iclass 10, count 2 2006.218.08:00:00.05#ibcon#first serial, iclass 10, count 2 2006.218.08:00:00.05#ibcon#enter sib2, iclass 10, count 2 2006.218.08:00:00.05#ibcon#flushed, iclass 10, count 2 2006.218.08:00:00.05#ibcon#about to write, iclass 10, count 2 2006.218.08:00:00.05#ibcon#wrote, iclass 10, count 2 2006.218.08:00:00.05#ibcon#about to read 3, iclass 10, count 2 2006.218.08:00:00.07#ibcon#read 3, iclass 10, count 2 2006.218.08:00:00.07#ibcon#about to read 4, iclass 10, count 2 2006.218.08:00:00.07#ibcon#read 4, iclass 10, count 2 2006.218.08:00:00.07#ibcon#about to read 5, iclass 10, count 2 2006.218.08:00:00.07#ibcon#read 5, iclass 10, count 2 2006.218.08:00:00.07#ibcon#about to read 6, iclass 10, count 2 2006.218.08:00:00.07#ibcon#read 6, iclass 10, count 2 2006.218.08:00:00.07#ibcon#end of sib2, iclass 10, count 2 2006.218.08:00:00.07#ibcon#*mode == 0, iclass 10, count 2 2006.218.08:00:00.07#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.218.08:00:00.07#ibcon#[25=AT07-06\r\n] 2006.218.08:00:00.07#ibcon#*before write, iclass 10, count 2 2006.218.08:00:00.07#ibcon#enter sib2, iclass 10, count 2 2006.218.08:00:00.07#ibcon#flushed, iclass 10, count 2 2006.218.08:00:00.07#ibcon#about to write, iclass 10, count 2 2006.218.08:00:00.07#ibcon#wrote, iclass 10, count 2 2006.218.08:00:00.07#ibcon#about to read 3, iclass 10, count 2 2006.218.08:00:00.10#ibcon#read 3, iclass 10, count 2 2006.218.08:00:00.10#ibcon#about to read 4, iclass 10, count 2 2006.218.08:00:00.10#ibcon#read 4, iclass 10, count 2 2006.218.08:00:00.10#ibcon#about to read 5, iclass 10, count 2 2006.218.08:00:00.10#ibcon#read 5, iclass 10, count 2 2006.218.08:00:00.10#ibcon#about to read 6, iclass 10, count 2 2006.218.08:00:00.10#ibcon#read 6, iclass 10, count 2 2006.218.08:00:00.10#ibcon#end of sib2, iclass 10, count 2 2006.218.08:00:00.10#ibcon#*after write, iclass 10, count 2 2006.218.08:00:00.10#ibcon#*before return 0, iclass 10, count 2 2006.218.08:00:00.10#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.218.08:00:00.10#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.218.08:00:00.10#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.218.08:00:00.10#ibcon#ireg 7 cls_cnt 0 2006.218.08:00:00.10#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.218.08:00:00.22#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.218.08:00:00.22#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.218.08:00:00.22#ibcon#enter wrdev, iclass 10, count 0 2006.218.08:00:00.22#ibcon#first serial, iclass 10, count 0 2006.218.08:00:00.22#ibcon#enter sib2, iclass 10, count 0 2006.218.08:00:00.22#ibcon#flushed, iclass 10, count 0 2006.218.08:00:00.22#ibcon#about to write, iclass 10, count 0 2006.218.08:00:00.22#ibcon#wrote, iclass 10, count 0 2006.218.08:00:00.22#ibcon#about to read 3, iclass 10, count 0 2006.218.08:00:00.24#ibcon#read 3, iclass 10, count 0 2006.218.08:00:00.24#ibcon#about to read 4, iclass 10, count 0 2006.218.08:00:00.24#ibcon#read 4, iclass 10, count 0 2006.218.08:00:00.24#ibcon#about to read 5, iclass 10, count 0 2006.218.08:00:00.24#ibcon#read 5, iclass 10, count 0 2006.218.08:00:00.24#ibcon#about to read 6, iclass 10, count 0 2006.218.08:00:00.24#ibcon#read 6, iclass 10, count 0 2006.218.08:00:00.24#ibcon#end of sib2, iclass 10, count 0 2006.218.08:00:00.24#ibcon#*mode == 0, iclass 10, count 0 2006.218.08:00:00.24#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.218.08:00:00.24#ibcon#[25=USB\r\n] 2006.218.08:00:00.24#ibcon#*before write, iclass 10, count 0 2006.218.08:00:00.24#ibcon#enter sib2, iclass 10, count 0 2006.218.08:00:00.24#ibcon#flushed, iclass 10, count 0 2006.218.08:00:00.24#ibcon#about to write, iclass 10, count 0 2006.218.08:00:00.24#ibcon#wrote, iclass 10, count 0 2006.218.08:00:00.24#ibcon#about to read 3, iclass 10, count 0 2006.218.08:00:00.27#ibcon#read 3, iclass 10, count 0 2006.218.08:00:00.27#ibcon#about to read 4, iclass 10, count 0 2006.218.08:00:00.27#ibcon#read 4, iclass 10, count 0 2006.218.08:00:00.27#ibcon#about to read 5, iclass 10, count 0 2006.218.08:00:00.27#ibcon#read 5, iclass 10, count 0 2006.218.08:00:00.27#ibcon#about to read 6, iclass 10, count 0 2006.218.08:00:00.27#ibcon#read 6, iclass 10, count 0 2006.218.08:00:00.27#ibcon#end of sib2, iclass 10, count 0 2006.218.08:00:00.27#ibcon#*after write, iclass 10, count 0 2006.218.08:00:00.27#ibcon#*before return 0, iclass 10, count 0 2006.218.08:00:00.27#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.218.08:00:00.27#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.218.08:00:00.27#ibcon#about to clear, iclass 10 cls_cnt 0 2006.218.08:00:00.27#ibcon#cleared, iclass 10 cls_cnt 0 2006.218.08:00:00.27$vc4f8/valo=8,852.99 2006.218.08:00:00.27#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.218.08:00:00.27#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.218.08:00:00.27#ibcon#ireg 17 cls_cnt 0 2006.218.08:00:00.27#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.218.08:00:00.27#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.218.08:00:00.27#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.218.08:00:00.27#ibcon#enter wrdev, iclass 12, count 0 2006.218.08:00:00.27#ibcon#first serial, iclass 12, count 0 2006.218.08:00:00.27#ibcon#enter sib2, iclass 12, count 0 2006.218.08:00:00.27#ibcon#flushed, iclass 12, count 0 2006.218.08:00:00.27#ibcon#about to write, iclass 12, count 0 2006.218.08:00:00.27#ibcon#wrote, iclass 12, count 0 2006.218.08:00:00.27#ibcon#about to read 3, iclass 12, count 0 2006.218.08:00:00.29#ibcon#read 3, iclass 12, count 0 2006.218.08:00:00.29#ibcon#about to read 4, iclass 12, count 0 2006.218.08:00:00.29#ibcon#read 4, iclass 12, count 0 2006.218.08:00:00.29#ibcon#about to read 5, iclass 12, count 0 2006.218.08:00:00.29#ibcon#read 5, iclass 12, count 0 2006.218.08:00:00.29#ibcon#about to read 6, iclass 12, count 0 2006.218.08:00:00.29#ibcon#read 6, iclass 12, count 0 2006.218.08:00:00.29#ibcon#end of sib2, iclass 12, count 0 2006.218.08:00:00.29#ibcon#*mode == 0, iclass 12, count 0 2006.218.08:00:00.29#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.218.08:00:00.29#ibcon#[26=FRQ=08,852.99\r\n] 2006.218.08:00:00.29#ibcon#*before write, iclass 12, count 0 2006.218.08:00:00.29#ibcon#enter sib2, iclass 12, count 0 2006.218.08:00:00.29#ibcon#flushed, iclass 12, count 0 2006.218.08:00:00.29#ibcon#about to write, iclass 12, count 0 2006.218.08:00:00.29#ibcon#wrote, iclass 12, count 0 2006.218.08:00:00.29#ibcon#about to read 3, iclass 12, count 0 2006.218.08:00:00.33#ibcon#read 3, iclass 12, count 0 2006.218.08:00:00.33#ibcon#about to read 4, iclass 12, count 0 2006.218.08:00:00.33#ibcon#read 4, iclass 12, count 0 2006.218.08:00:00.33#ibcon#about to read 5, iclass 12, count 0 2006.218.08:00:00.33#ibcon#read 5, iclass 12, count 0 2006.218.08:00:00.33#ibcon#about to read 6, iclass 12, count 0 2006.218.08:00:00.33#ibcon#read 6, iclass 12, count 0 2006.218.08:00:00.33#ibcon#end of sib2, iclass 12, count 0 2006.218.08:00:00.33#ibcon#*after write, iclass 12, count 0 2006.218.08:00:00.33#ibcon#*before return 0, iclass 12, count 0 2006.218.08:00:00.33#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.218.08:00:00.33#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.218.08:00:00.33#ibcon#about to clear, iclass 12 cls_cnt 0 2006.218.08:00:00.33#ibcon#cleared, iclass 12 cls_cnt 0 2006.218.08:00:00.33$vc4f8/va=8,7 2006.218.08:00:00.33#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.218.08:00:00.33#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.218.08:00:00.33#ibcon#ireg 11 cls_cnt 2 2006.218.08:00:00.33#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.218.08:00:00.39#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.218.08:00:00.39#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.218.08:00:00.39#ibcon#enter wrdev, iclass 14, count 2 2006.218.08:00:00.39#ibcon#first serial, iclass 14, count 2 2006.218.08:00:00.39#ibcon#enter sib2, iclass 14, count 2 2006.218.08:00:00.39#ibcon#flushed, iclass 14, count 2 2006.218.08:00:00.39#ibcon#about to write, iclass 14, count 2 2006.218.08:00:00.39#ibcon#wrote, iclass 14, count 2 2006.218.08:00:00.39#ibcon#about to read 3, iclass 14, count 2 2006.218.08:00:00.41#ibcon#read 3, iclass 14, count 2 2006.218.08:00:00.41#ibcon#about to read 4, iclass 14, count 2 2006.218.08:00:00.41#ibcon#read 4, iclass 14, count 2 2006.218.08:00:00.41#ibcon#about to read 5, iclass 14, count 2 2006.218.08:00:00.41#ibcon#read 5, iclass 14, count 2 2006.218.08:00:00.41#ibcon#about to read 6, iclass 14, count 2 2006.218.08:00:00.41#ibcon#read 6, iclass 14, count 2 2006.218.08:00:00.41#ibcon#end of sib2, iclass 14, count 2 2006.218.08:00:00.41#ibcon#*mode == 0, iclass 14, count 2 2006.218.08:00:00.41#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.218.08:00:00.41#ibcon#[25=AT08-07\r\n] 2006.218.08:00:00.41#ibcon#*before write, iclass 14, count 2 2006.218.08:00:00.41#ibcon#enter sib2, iclass 14, count 2 2006.218.08:00:00.41#ibcon#flushed, iclass 14, count 2 2006.218.08:00:00.41#ibcon#about to write, iclass 14, count 2 2006.218.08:00:00.41#ibcon#wrote, iclass 14, count 2 2006.218.08:00:00.41#ibcon#about to read 3, iclass 14, count 2 2006.218.08:00:00.44#ibcon#read 3, iclass 14, count 2 2006.218.08:00:00.44#ibcon#about to read 4, iclass 14, count 2 2006.218.08:00:00.44#ibcon#read 4, iclass 14, count 2 2006.218.08:00:00.44#ibcon#about to read 5, iclass 14, count 2 2006.218.08:00:00.44#ibcon#read 5, iclass 14, count 2 2006.218.08:00:00.44#ibcon#about to read 6, iclass 14, count 2 2006.218.08:00:00.44#ibcon#read 6, iclass 14, count 2 2006.218.08:00:00.44#ibcon#end of sib2, iclass 14, count 2 2006.218.08:00:00.44#ibcon#*after write, iclass 14, count 2 2006.218.08:00:00.44#ibcon#*before return 0, iclass 14, count 2 2006.218.08:00:00.44#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.218.08:00:00.44#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.218.08:00:00.44#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.218.08:00:00.44#ibcon#ireg 7 cls_cnt 0 2006.218.08:00:00.44#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.218.08:00:00.56#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.218.08:00:00.56#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.218.08:00:00.56#ibcon#enter wrdev, iclass 14, count 0 2006.218.08:00:00.56#ibcon#first serial, iclass 14, count 0 2006.218.08:00:00.56#ibcon#enter sib2, iclass 14, count 0 2006.218.08:00:00.56#ibcon#flushed, iclass 14, count 0 2006.218.08:00:00.56#ibcon#about to write, iclass 14, count 0 2006.218.08:00:00.56#ibcon#wrote, iclass 14, count 0 2006.218.08:00:00.56#ibcon#about to read 3, iclass 14, count 0 2006.218.08:00:00.58#ibcon#read 3, iclass 14, count 0 2006.218.08:00:00.58#ibcon#about to read 4, iclass 14, count 0 2006.218.08:00:00.58#ibcon#read 4, iclass 14, count 0 2006.218.08:00:00.58#ibcon#about to read 5, iclass 14, count 0 2006.218.08:00:00.58#ibcon#read 5, iclass 14, count 0 2006.218.08:00:00.58#ibcon#about to read 6, iclass 14, count 0 2006.218.08:00:00.58#ibcon#read 6, iclass 14, count 0 2006.218.08:00:00.58#ibcon#end of sib2, iclass 14, count 0 2006.218.08:00:00.58#ibcon#*mode == 0, iclass 14, count 0 2006.218.08:00:00.58#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.218.08:00:00.58#ibcon#[25=USB\r\n] 2006.218.08:00:00.58#ibcon#*before write, iclass 14, count 0 2006.218.08:00:00.58#ibcon#enter sib2, iclass 14, count 0 2006.218.08:00:00.58#ibcon#flushed, iclass 14, count 0 2006.218.08:00:00.58#ibcon#about to write, iclass 14, count 0 2006.218.08:00:00.58#ibcon#wrote, iclass 14, count 0 2006.218.08:00:00.58#ibcon#about to read 3, iclass 14, count 0 2006.218.08:00:00.61#ibcon#read 3, iclass 14, count 0 2006.218.08:00:00.61#ibcon#about to read 4, iclass 14, count 0 2006.218.08:00:00.61#ibcon#read 4, iclass 14, count 0 2006.218.08:00:00.61#ibcon#about to read 5, iclass 14, count 0 2006.218.08:00:00.61#ibcon#read 5, iclass 14, count 0 2006.218.08:00:00.61#ibcon#about to read 6, iclass 14, count 0 2006.218.08:00:00.61#ibcon#read 6, iclass 14, count 0 2006.218.08:00:00.61#ibcon#end of sib2, iclass 14, count 0 2006.218.08:00:00.61#ibcon#*after write, iclass 14, count 0 2006.218.08:00:00.61#ibcon#*before return 0, iclass 14, count 0 2006.218.08:00:00.61#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.218.08:00:00.61#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.218.08:00:00.61#ibcon#about to clear, iclass 14 cls_cnt 0 2006.218.08:00:00.61#ibcon#cleared, iclass 14 cls_cnt 0 2006.218.08:00:00.61$vc4f8/vblo=1,632.99 2006.218.08:00:00.61#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.218.08:00:00.61#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.218.08:00:00.61#ibcon#ireg 17 cls_cnt 0 2006.218.08:00:00.61#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.218.08:00:00.61#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.218.08:00:00.61#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.218.08:00:00.61#ibcon#enter wrdev, iclass 16, count 0 2006.218.08:00:00.61#ibcon#first serial, iclass 16, count 0 2006.218.08:00:00.61#ibcon#enter sib2, iclass 16, count 0 2006.218.08:00:00.61#ibcon#flushed, iclass 16, count 0 2006.218.08:00:00.61#ibcon#about to write, iclass 16, count 0 2006.218.08:00:00.61#ibcon#wrote, iclass 16, count 0 2006.218.08:00:00.61#ibcon#about to read 3, iclass 16, count 0 2006.218.08:00:00.63#ibcon#read 3, iclass 16, count 0 2006.218.08:00:00.63#ibcon#about to read 4, iclass 16, count 0 2006.218.08:00:00.63#ibcon#read 4, iclass 16, count 0 2006.218.08:00:00.63#ibcon#about to read 5, iclass 16, count 0 2006.218.08:00:00.63#ibcon#read 5, iclass 16, count 0 2006.218.08:00:00.63#ibcon#about to read 6, iclass 16, count 0 2006.218.08:00:00.63#ibcon#read 6, iclass 16, count 0 2006.218.08:00:00.63#ibcon#end of sib2, iclass 16, count 0 2006.218.08:00:00.63#ibcon#*mode == 0, iclass 16, count 0 2006.218.08:00:00.63#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.218.08:00:00.63#ibcon#[28=FRQ=01,632.99\r\n] 2006.218.08:00:00.63#ibcon#*before write, iclass 16, count 0 2006.218.08:00:00.63#ibcon#enter sib2, iclass 16, count 0 2006.218.08:00:00.63#ibcon#flushed, iclass 16, count 0 2006.218.08:00:00.63#ibcon#about to write, iclass 16, count 0 2006.218.08:00:00.63#ibcon#wrote, iclass 16, count 0 2006.218.08:00:00.63#ibcon#about to read 3, iclass 16, count 0 2006.218.08:00:00.67#ibcon#read 3, iclass 16, count 0 2006.218.08:00:00.67#ibcon#about to read 4, iclass 16, count 0 2006.218.08:00:00.67#ibcon#read 4, iclass 16, count 0 2006.218.08:00:00.67#ibcon#about to read 5, iclass 16, count 0 2006.218.08:00:00.67#ibcon#read 5, iclass 16, count 0 2006.218.08:00:00.67#ibcon#about to read 6, iclass 16, count 0 2006.218.08:00:00.67#ibcon#read 6, iclass 16, count 0 2006.218.08:00:00.67#ibcon#end of sib2, iclass 16, count 0 2006.218.08:00:00.67#ibcon#*after write, iclass 16, count 0 2006.218.08:00:00.67#ibcon#*before return 0, iclass 16, count 0 2006.218.08:00:00.67#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.218.08:00:00.67#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.218.08:00:00.67#ibcon#about to clear, iclass 16 cls_cnt 0 2006.218.08:00:00.67#ibcon#cleared, iclass 16 cls_cnt 0 2006.218.08:00:00.67$vc4f8/vb=1,4 2006.218.08:00:00.67#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.218.08:00:00.67#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.218.08:00:00.67#ibcon#ireg 11 cls_cnt 2 2006.218.08:00:00.67#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.218.08:00:00.67#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.218.08:00:00.67#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.218.08:00:00.67#ibcon#enter wrdev, iclass 18, count 2 2006.218.08:00:00.67#ibcon#first serial, iclass 18, count 2 2006.218.08:00:00.67#ibcon#enter sib2, iclass 18, count 2 2006.218.08:00:00.67#ibcon#flushed, iclass 18, count 2 2006.218.08:00:00.67#ibcon#about to write, iclass 18, count 2 2006.218.08:00:00.67#ibcon#wrote, iclass 18, count 2 2006.218.08:00:00.67#ibcon#about to read 3, iclass 18, count 2 2006.218.08:00:00.69#ibcon#read 3, iclass 18, count 2 2006.218.08:00:00.69#ibcon#about to read 4, iclass 18, count 2 2006.218.08:00:00.69#ibcon#read 4, iclass 18, count 2 2006.218.08:00:00.69#ibcon#about to read 5, iclass 18, count 2 2006.218.08:00:00.69#ibcon#read 5, iclass 18, count 2 2006.218.08:00:00.69#ibcon#about to read 6, iclass 18, count 2 2006.218.08:00:00.69#ibcon#read 6, iclass 18, count 2 2006.218.08:00:00.69#ibcon#end of sib2, iclass 18, count 2 2006.218.08:00:00.69#ibcon#*mode == 0, iclass 18, count 2 2006.218.08:00:00.69#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.218.08:00:00.69#ibcon#[27=AT01-04\r\n] 2006.218.08:00:00.69#ibcon#*before write, iclass 18, count 2 2006.218.08:00:00.69#ibcon#enter sib2, iclass 18, count 2 2006.218.08:00:00.69#ibcon#flushed, iclass 18, count 2 2006.218.08:00:00.69#ibcon#about to write, iclass 18, count 2 2006.218.08:00:00.69#ibcon#wrote, iclass 18, count 2 2006.218.08:00:00.69#ibcon#about to read 3, iclass 18, count 2 2006.218.08:00:00.72#ibcon#read 3, iclass 18, count 2 2006.218.08:00:00.72#ibcon#about to read 4, iclass 18, count 2 2006.218.08:00:00.72#ibcon#read 4, iclass 18, count 2 2006.218.08:00:00.72#ibcon#about to read 5, iclass 18, count 2 2006.218.08:00:00.72#ibcon#read 5, iclass 18, count 2 2006.218.08:00:00.72#ibcon#about to read 6, iclass 18, count 2 2006.218.08:00:00.72#ibcon#read 6, iclass 18, count 2 2006.218.08:00:00.72#ibcon#end of sib2, iclass 18, count 2 2006.218.08:00:00.72#ibcon#*after write, iclass 18, count 2 2006.218.08:00:00.72#ibcon#*before return 0, iclass 18, count 2 2006.218.08:00:00.72#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.218.08:00:00.72#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.218.08:00:00.72#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.218.08:00:00.72#ibcon#ireg 7 cls_cnt 0 2006.218.08:00:00.72#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.218.08:00:00.84#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.218.08:00:00.84#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.218.08:00:00.84#ibcon#enter wrdev, iclass 18, count 0 2006.218.08:00:00.84#ibcon#first serial, iclass 18, count 0 2006.218.08:00:00.84#ibcon#enter sib2, iclass 18, count 0 2006.218.08:00:00.84#ibcon#flushed, iclass 18, count 0 2006.218.08:00:00.84#ibcon#about to write, iclass 18, count 0 2006.218.08:00:00.84#ibcon#wrote, iclass 18, count 0 2006.218.08:00:00.84#ibcon#about to read 3, iclass 18, count 0 2006.218.08:00:00.86#ibcon#read 3, iclass 18, count 0 2006.218.08:00:00.86#ibcon#about to read 4, iclass 18, count 0 2006.218.08:00:00.86#ibcon#read 4, iclass 18, count 0 2006.218.08:00:00.86#ibcon#about to read 5, iclass 18, count 0 2006.218.08:00:00.86#ibcon#read 5, iclass 18, count 0 2006.218.08:00:00.86#ibcon#about to read 6, iclass 18, count 0 2006.218.08:00:00.86#ibcon#read 6, iclass 18, count 0 2006.218.08:00:00.86#ibcon#end of sib2, iclass 18, count 0 2006.218.08:00:00.86#ibcon#*mode == 0, iclass 18, count 0 2006.218.08:00:00.86#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.218.08:00:00.86#ibcon#[27=USB\r\n] 2006.218.08:00:00.86#ibcon#*before write, iclass 18, count 0 2006.218.08:00:00.86#ibcon#enter sib2, iclass 18, count 0 2006.218.08:00:00.86#ibcon#flushed, iclass 18, count 0 2006.218.08:00:00.86#ibcon#about to write, iclass 18, count 0 2006.218.08:00:00.86#ibcon#wrote, iclass 18, count 0 2006.218.08:00:00.86#ibcon#about to read 3, iclass 18, count 0 2006.218.08:00:00.89#ibcon#read 3, iclass 18, count 0 2006.218.08:00:00.89#ibcon#about to read 4, iclass 18, count 0 2006.218.08:00:00.89#ibcon#read 4, iclass 18, count 0 2006.218.08:00:00.89#ibcon#about to read 5, iclass 18, count 0 2006.218.08:00:00.89#ibcon#read 5, iclass 18, count 0 2006.218.08:00:00.89#ibcon#about to read 6, iclass 18, count 0 2006.218.08:00:00.89#ibcon#read 6, iclass 18, count 0 2006.218.08:00:00.89#ibcon#end of sib2, iclass 18, count 0 2006.218.08:00:00.89#ibcon#*after write, iclass 18, count 0 2006.218.08:00:00.89#ibcon#*before return 0, iclass 18, count 0 2006.218.08:00:00.89#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.218.08:00:00.89#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.218.08:00:00.89#ibcon#about to clear, iclass 18 cls_cnt 0 2006.218.08:00:00.89#ibcon#cleared, iclass 18 cls_cnt 0 2006.218.08:00:00.89$vc4f8/vblo=2,640.99 2006.218.08:00:00.89#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.218.08:00:00.89#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.218.08:00:00.89#ibcon#ireg 17 cls_cnt 0 2006.218.08:00:00.89#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.218.08:00:00.89#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.218.08:00:00.89#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.218.08:00:00.89#ibcon#enter wrdev, iclass 20, count 0 2006.218.08:00:00.89#ibcon#first serial, iclass 20, count 0 2006.218.08:00:00.89#ibcon#enter sib2, iclass 20, count 0 2006.218.08:00:00.89#ibcon#flushed, iclass 20, count 0 2006.218.08:00:00.89#ibcon#about to write, iclass 20, count 0 2006.218.08:00:00.89#ibcon#wrote, iclass 20, count 0 2006.218.08:00:00.89#ibcon#about to read 3, iclass 20, count 0 2006.218.08:00:00.91#ibcon#read 3, iclass 20, count 0 2006.218.08:00:00.91#ibcon#about to read 4, iclass 20, count 0 2006.218.08:00:00.91#ibcon#read 4, iclass 20, count 0 2006.218.08:00:00.91#ibcon#about to read 5, iclass 20, count 0 2006.218.08:00:00.91#ibcon#read 5, iclass 20, count 0 2006.218.08:00:00.91#ibcon#about to read 6, iclass 20, count 0 2006.218.08:00:00.91#ibcon#read 6, iclass 20, count 0 2006.218.08:00:00.91#ibcon#end of sib2, iclass 20, count 0 2006.218.08:00:00.91#ibcon#*mode == 0, iclass 20, count 0 2006.218.08:00:00.91#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.218.08:00:00.91#ibcon#[28=FRQ=02,640.99\r\n] 2006.218.08:00:00.91#ibcon#*before write, iclass 20, count 0 2006.218.08:00:00.91#ibcon#enter sib2, iclass 20, count 0 2006.218.08:00:00.91#ibcon#flushed, iclass 20, count 0 2006.218.08:00:00.91#ibcon#about to write, iclass 20, count 0 2006.218.08:00:00.91#ibcon#wrote, iclass 20, count 0 2006.218.08:00:00.91#ibcon#about to read 3, iclass 20, count 0 2006.218.08:00:00.95#ibcon#read 3, iclass 20, count 0 2006.218.08:00:00.95#ibcon#about to read 4, iclass 20, count 0 2006.218.08:00:00.95#ibcon#read 4, iclass 20, count 0 2006.218.08:00:00.95#ibcon#about to read 5, iclass 20, count 0 2006.218.08:00:00.95#ibcon#read 5, iclass 20, count 0 2006.218.08:00:00.95#ibcon#about to read 6, iclass 20, count 0 2006.218.08:00:00.95#ibcon#read 6, iclass 20, count 0 2006.218.08:00:00.95#ibcon#end of sib2, iclass 20, count 0 2006.218.08:00:00.95#ibcon#*after write, iclass 20, count 0 2006.218.08:00:00.95#ibcon#*before return 0, iclass 20, count 0 2006.218.08:00:00.95#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.218.08:00:00.95#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.218.08:00:00.95#ibcon#about to clear, iclass 20 cls_cnt 0 2006.218.08:00:00.95#ibcon#cleared, iclass 20 cls_cnt 0 2006.218.08:00:00.95$vc4f8/vb=2,4 2006.218.08:00:00.95#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.218.08:00:00.95#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.218.08:00:00.95#ibcon#ireg 11 cls_cnt 2 2006.218.08:00:00.95#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.218.08:00:01.01#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.218.08:00:01.01#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.218.08:00:01.01#ibcon#enter wrdev, iclass 22, count 2 2006.218.08:00:01.01#ibcon#first serial, iclass 22, count 2 2006.218.08:00:01.01#ibcon#enter sib2, iclass 22, count 2 2006.218.08:00:01.01#ibcon#flushed, iclass 22, count 2 2006.218.08:00:01.01#ibcon#about to write, iclass 22, count 2 2006.218.08:00:01.01#ibcon#wrote, iclass 22, count 2 2006.218.08:00:01.01#ibcon#about to read 3, iclass 22, count 2 2006.218.08:00:01.03#ibcon#read 3, iclass 22, count 2 2006.218.08:00:01.03#ibcon#about to read 4, iclass 22, count 2 2006.218.08:00:01.03#ibcon#read 4, iclass 22, count 2 2006.218.08:00:01.03#ibcon#about to read 5, iclass 22, count 2 2006.218.08:00:01.03#ibcon#read 5, iclass 22, count 2 2006.218.08:00:01.03#ibcon#about to read 6, iclass 22, count 2 2006.218.08:00:01.03#ibcon#read 6, iclass 22, count 2 2006.218.08:00:01.03#ibcon#end of sib2, iclass 22, count 2 2006.218.08:00:01.03#ibcon#*mode == 0, iclass 22, count 2 2006.218.08:00:01.03#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.218.08:00:01.03#ibcon#[27=AT02-04\r\n] 2006.218.08:00:01.03#ibcon#*before write, iclass 22, count 2 2006.218.08:00:01.03#ibcon#enter sib2, iclass 22, count 2 2006.218.08:00:01.03#ibcon#flushed, iclass 22, count 2 2006.218.08:00:01.03#ibcon#about to write, iclass 22, count 2 2006.218.08:00:01.03#ibcon#wrote, iclass 22, count 2 2006.218.08:00:01.03#ibcon#about to read 3, iclass 22, count 2 2006.218.08:00:01.06#ibcon#read 3, iclass 22, count 2 2006.218.08:00:01.06#ibcon#about to read 4, iclass 22, count 2 2006.218.08:00:01.06#ibcon#read 4, iclass 22, count 2 2006.218.08:00:01.06#ibcon#about to read 5, iclass 22, count 2 2006.218.08:00:01.06#ibcon#read 5, iclass 22, count 2 2006.218.08:00:01.06#ibcon#about to read 6, iclass 22, count 2 2006.218.08:00:01.06#ibcon#read 6, iclass 22, count 2 2006.218.08:00:01.06#ibcon#end of sib2, iclass 22, count 2 2006.218.08:00:01.06#ibcon#*after write, iclass 22, count 2 2006.218.08:00:01.06#ibcon#*before return 0, iclass 22, count 2 2006.218.08:00:01.06#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.218.08:00:01.06#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.218.08:00:01.06#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.218.08:00:01.06#ibcon#ireg 7 cls_cnt 0 2006.218.08:00:01.06#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.218.08:00:01.18#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.218.08:00:01.18#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.218.08:00:01.18#ibcon#enter wrdev, iclass 22, count 0 2006.218.08:00:01.18#ibcon#first serial, iclass 22, count 0 2006.218.08:00:01.18#ibcon#enter sib2, iclass 22, count 0 2006.218.08:00:01.18#ibcon#flushed, iclass 22, count 0 2006.218.08:00:01.18#ibcon#about to write, iclass 22, count 0 2006.218.08:00:01.18#ibcon#wrote, iclass 22, count 0 2006.218.08:00:01.18#ibcon#about to read 3, iclass 22, count 0 2006.218.08:00:01.20#ibcon#read 3, iclass 22, count 0 2006.218.08:00:01.20#ibcon#about to read 4, iclass 22, count 0 2006.218.08:00:01.20#ibcon#read 4, iclass 22, count 0 2006.218.08:00:01.20#ibcon#about to read 5, iclass 22, count 0 2006.218.08:00:01.20#ibcon#read 5, iclass 22, count 0 2006.218.08:00:01.20#ibcon#about to read 6, iclass 22, count 0 2006.218.08:00:01.20#ibcon#read 6, iclass 22, count 0 2006.218.08:00:01.20#ibcon#end of sib2, iclass 22, count 0 2006.218.08:00:01.20#ibcon#*mode == 0, iclass 22, count 0 2006.218.08:00:01.20#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.218.08:00:01.20#ibcon#[27=USB\r\n] 2006.218.08:00:01.20#ibcon#*before write, iclass 22, count 0 2006.218.08:00:01.20#ibcon#enter sib2, iclass 22, count 0 2006.218.08:00:01.20#ibcon#flushed, iclass 22, count 0 2006.218.08:00:01.20#ibcon#about to write, iclass 22, count 0 2006.218.08:00:01.20#ibcon#wrote, iclass 22, count 0 2006.218.08:00:01.20#ibcon#about to read 3, iclass 22, count 0 2006.218.08:00:01.23#ibcon#read 3, iclass 22, count 0 2006.218.08:00:01.23#ibcon#about to read 4, iclass 22, count 0 2006.218.08:00:01.23#ibcon#read 4, iclass 22, count 0 2006.218.08:00:01.23#ibcon#about to read 5, iclass 22, count 0 2006.218.08:00:01.23#ibcon#read 5, iclass 22, count 0 2006.218.08:00:01.23#ibcon#about to read 6, iclass 22, count 0 2006.218.08:00:01.23#ibcon#read 6, iclass 22, count 0 2006.218.08:00:01.23#ibcon#end of sib2, iclass 22, count 0 2006.218.08:00:01.23#ibcon#*after write, iclass 22, count 0 2006.218.08:00:01.23#ibcon#*before return 0, iclass 22, count 0 2006.218.08:00:01.23#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.218.08:00:01.23#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.218.08:00:01.23#ibcon#about to clear, iclass 22 cls_cnt 0 2006.218.08:00:01.23#ibcon#cleared, iclass 22 cls_cnt 0 2006.218.08:00:01.23$vc4f8/vblo=3,656.99 2006.218.08:00:01.23#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.218.08:00:01.23#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.218.08:00:01.23#ibcon#ireg 17 cls_cnt 0 2006.218.08:00:01.23#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.218.08:00:01.23#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.218.08:00:01.23#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.218.08:00:01.23#ibcon#enter wrdev, iclass 24, count 0 2006.218.08:00:01.23#ibcon#first serial, iclass 24, count 0 2006.218.08:00:01.23#ibcon#enter sib2, iclass 24, count 0 2006.218.08:00:01.23#ibcon#flushed, iclass 24, count 0 2006.218.08:00:01.23#ibcon#about to write, iclass 24, count 0 2006.218.08:00:01.23#ibcon#wrote, iclass 24, count 0 2006.218.08:00:01.23#ibcon#about to read 3, iclass 24, count 0 2006.218.08:00:01.25#ibcon#read 3, iclass 24, count 0 2006.218.08:00:01.25#ibcon#about to read 4, iclass 24, count 0 2006.218.08:00:01.25#ibcon#read 4, iclass 24, count 0 2006.218.08:00:01.25#ibcon#about to read 5, iclass 24, count 0 2006.218.08:00:01.25#ibcon#read 5, iclass 24, count 0 2006.218.08:00:01.25#ibcon#about to read 6, iclass 24, count 0 2006.218.08:00:01.25#ibcon#read 6, iclass 24, count 0 2006.218.08:00:01.25#ibcon#end of sib2, iclass 24, count 0 2006.218.08:00:01.25#ibcon#*mode == 0, iclass 24, count 0 2006.218.08:00:01.25#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.218.08:00:01.25#ibcon#[28=FRQ=03,656.99\r\n] 2006.218.08:00:01.25#ibcon#*before write, iclass 24, count 0 2006.218.08:00:01.25#ibcon#enter sib2, iclass 24, count 0 2006.218.08:00:01.25#ibcon#flushed, iclass 24, count 0 2006.218.08:00:01.25#ibcon#about to write, iclass 24, count 0 2006.218.08:00:01.25#ibcon#wrote, iclass 24, count 0 2006.218.08:00:01.25#ibcon#about to read 3, iclass 24, count 0 2006.218.08:00:01.29#ibcon#read 3, iclass 24, count 0 2006.218.08:00:01.29#ibcon#about to read 4, iclass 24, count 0 2006.218.08:00:01.29#ibcon#read 4, iclass 24, count 0 2006.218.08:00:01.29#ibcon#about to read 5, iclass 24, count 0 2006.218.08:00:01.29#ibcon#read 5, iclass 24, count 0 2006.218.08:00:01.29#ibcon#about to read 6, iclass 24, count 0 2006.218.08:00:01.29#ibcon#read 6, iclass 24, count 0 2006.218.08:00:01.29#ibcon#end of sib2, iclass 24, count 0 2006.218.08:00:01.29#ibcon#*after write, iclass 24, count 0 2006.218.08:00:01.29#ibcon#*before return 0, iclass 24, count 0 2006.218.08:00:01.29#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.218.08:00:01.29#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.218.08:00:01.29#ibcon#about to clear, iclass 24 cls_cnt 0 2006.218.08:00:01.29#ibcon#cleared, iclass 24 cls_cnt 0 2006.218.08:00:01.29$vc4f8/vb=3,4 2006.218.08:00:01.29#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.218.08:00:01.29#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.218.08:00:01.29#ibcon#ireg 11 cls_cnt 2 2006.218.08:00:01.29#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.218.08:00:01.35#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.218.08:00:01.35#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.218.08:00:01.35#ibcon#enter wrdev, iclass 26, count 2 2006.218.08:00:01.35#ibcon#first serial, iclass 26, count 2 2006.218.08:00:01.35#ibcon#enter sib2, iclass 26, count 2 2006.218.08:00:01.35#ibcon#flushed, iclass 26, count 2 2006.218.08:00:01.35#ibcon#about to write, iclass 26, count 2 2006.218.08:00:01.35#ibcon#wrote, iclass 26, count 2 2006.218.08:00:01.35#ibcon#about to read 3, iclass 26, count 2 2006.218.08:00:01.37#ibcon#read 3, iclass 26, count 2 2006.218.08:00:01.37#ibcon#about to read 4, iclass 26, count 2 2006.218.08:00:01.37#ibcon#read 4, iclass 26, count 2 2006.218.08:00:01.37#ibcon#about to read 5, iclass 26, count 2 2006.218.08:00:01.37#ibcon#read 5, iclass 26, count 2 2006.218.08:00:01.37#ibcon#about to read 6, iclass 26, count 2 2006.218.08:00:01.37#ibcon#read 6, iclass 26, count 2 2006.218.08:00:01.37#ibcon#end of sib2, iclass 26, count 2 2006.218.08:00:01.37#ibcon#*mode == 0, iclass 26, count 2 2006.218.08:00:01.37#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.218.08:00:01.37#ibcon#[27=AT03-04\r\n] 2006.218.08:00:01.37#ibcon#*before write, iclass 26, count 2 2006.218.08:00:01.37#ibcon#enter sib2, iclass 26, count 2 2006.218.08:00:01.37#ibcon#flushed, iclass 26, count 2 2006.218.08:00:01.37#ibcon#about to write, iclass 26, count 2 2006.218.08:00:01.37#ibcon#wrote, iclass 26, count 2 2006.218.08:00:01.37#ibcon#about to read 3, iclass 26, count 2 2006.218.08:00:01.41#ibcon#read 3, iclass 26, count 2 2006.218.08:00:01.41#ibcon#about to read 4, iclass 26, count 2 2006.218.08:00:01.41#ibcon#read 4, iclass 26, count 2 2006.218.08:00:01.41#ibcon#about to read 5, iclass 26, count 2 2006.218.08:00:01.41#ibcon#read 5, iclass 26, count 2 2006.218.08:00:01.41#ibcon#about to read 6, iclass 26, count 2 2006.218.08:00:01.41#ibcon#read 6, iclass 26, count 2 2006.218.08:00:01.41#ibcon#end of sib2, iclass 26, count 2 2006.218.08:00:01.41#ibcon#*after write, iclass 26, count 2 2006.218.08:00:01.41#ibcon#*before return 0, iclass 26, count 2 2006.218.08:00:01.41#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.218.08:00:01.41#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.218.08:00:01.41#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.218.08:00:01.41#ibcon#ireg 7 cls_cnt 0 2006.218.08:00:01.41#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.218.08:00:01.52#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.218.08:00:01.52#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.218.08:00:01.52#ibcon#enter wrdev, iclass 26, count 0 2006.218.08:00:01.52#ibcon#first serial, iclass 26, count 0 2006.218.08:00:01.52#ibcon#enter sib2, iclass 26, count 0 2006.218.08:00:01.52#ibcon#flushed, iclass 26, count 0 2006.218.08:00:01.52#ibcon#about to write, iclass 26, count 0 2006.218.08:00:01.52#ibcon#wrote, iclass 26, count 0 2006.218.08:00:01.52#ibcon#about to read 3, iclass 26, count 0 2006.218.08:00:01.54#ibcon#read 3, iclass 26, count 0 2006.218.08:00:01.54#ibcon#about to read 4, iclass 26, count 0 2006.218.08:00:01.54#ibcon#read 4, iclass 26, count 0 2006.218.08:00:01.54#ibcon#about to read 5, iclass 26, count 0 2006.218.08:00:01.54#ibcon#read 5, iclass 26, count 0 2006.218.08:00:01.54#ibcon#about to read 6, iclass 26, count 0 2006.218.08:00:01.54#ibcon#read 6, iclass 26, count 0 2006.218.08:00:01.54#ibcon#end of sib2, iclass 26, count 0 2006.218.08:00:01.54#ibcon#*mode == 0, iclass 26, count 0 2006.218.08:00:01.54#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.218.08:00:01.54#ibcon#[27=USB\r\n] 2006.218.08:00:01.54#ibcon#*before write, iclass 26, count 0 2006.218.08:00:01.54#ibcon#enter sib2, iclass 26, count 0 2006.218.08:00:01.54#ibcon#flushed, iclass 26, count 0 2006.218.08:00:01.54#ibcon#about to write, iclass 26, count 0 2006.218.08:00:01.54#ibcon#wrote, iclass 26, count 0 2006.218.08:00:01.54#ibcon#about to read 3, iclass 26, count 0 2006.218.08:00:01.57#ibcon#read 3, iclass 26, count 0 2006.218.08:00:01.57#ibcon#about to read 4, iclass 26, count 0 2006.218.08:00:01.57#ibcon#read 4, iclass 26, count 0 2006.218.08:00:01.57#ibcon#about to read 5, iclass 26, count 0 2006.218.08:00:01.57#ibcon#read 5, iclass 26, count 0 2006.218.08:00:01.57#ibcon#about to read 6, iclass 26, count 0 2006.218.08:00:01.57#ibcon#read 6, iclass 26, count 0 2006.218.08:00:01.57#ibcon#end of sib2, iclass 26, count 0 2006.218.08:00:01.57#ibcon#*after write, iclass 26, count 0 2006.218.08:00:01.57#ibcon#*before return 0, iclass 26, count 0 2006.218.08:00:01.57#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.218.08:00:01.57#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.218.08:00:01.57#ibcon#about to clear, iclass 26 cls_cnt 0 2006.218.08:00:01.57#ibcon#cleared, iclass 26 cls_cnt 0 2006.218.08:00:01.57$vc4f8/vblo=4,712.99 2006.218.08:00:01.57#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.218.08:00:01.57#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.218.08:00:01.57#ibcon#ireg 17 cls_cnt 0 2006.218.08:00:01.57#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.218.08:00:01.57#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.218.08:00:01.57#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.218.08:00:01.57#ibcon#enter wrdev, iclass 28, count 0 2006.218.08:00:01.57#ibcon#first serial, iclass 28, count 0 2006.218.08:00:01.57#ibcon#enter sib2, iclass 28, count 0 2006.218.08:00:01.57#ibcon#flushed, iclass 28, count 0 2006.218.08:00:01.57#ibcon#about to write, iclass 28, count 0 2006.218.08:00:01.57#ibcon#wrote, iclass 28, count 0 2006.218.08:00:01.57#ibcon#about to read 3, iclass 28, count 0 2006.218.08:00:01.59#ibcon#read 3, iclass 28, count 0 2006.218.08:00:01.59#ibcon#about to read 4, iclass 28, count 0 2006.218.08:00:01.59#ibcon#read 4, iclass 28, count 0 2006.218.08:00:01.59#ibcon#about to read 5, iclass 28, count 0 2006.218.08:00:01.59#ibcon#read 5, iclass 28, count 0 2006.218.08:00:01.59#ibcon#about to read 6, iclass 28, count 0 2006.218.08:00:01.59#ibcon#read 6, iclass 28, count 0 2006.218.08:00:01.59#ibcon#end of sib2, iclass 28, count 0 2006.218.08:00:01.59#ibcon#*mode == 0, iclass 28, count 0 2006.218.08:00:01.59#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.218.08:00:01.59#ibcon#[28=FRQ=04,712.99\r\n] 2006.218.08:00:01.59#ibcon#*before write, iclass 28, count 0 2006.218.08:00:01.59#ibcon#enter sib2, iclass 28, count 0 2006.218.08:00:01.59#ibcon#flushed, iclass 28, count 0 2006.218.08:00:01.59#ibcon#about to write, iclass 28, count 0 2006.218.08:00:01.59#ibcon#wrote, iclass 28, count 0 2006.218.08:00:01.59#ibcon#about to read 3, iclass 28, count 0 2006.218.08:00:01.63#ibcon#read 3, iclass 28, count 0 2006.218.08:00:01.63#ibcon#about to read 4, iclass 28, count 0 2006.218.08:00:01.63#ibcon#read 4, iclass 28, count 0 2006.218.08:00:01.63#ibcon#about to read 5, iclass 28, count 0 2006.218.08:00:01.63#ibcon#read 5, iclass 28, count 0 2006.218.08:00:01.63#ibcon#about to read 6, iclass 28, count 0 2006.218.08:00:01.63#ibcon#read 6, iclass 28, count 0 2006.218.08:00:01.63#ibcon#end of sib2, iclass 28, count 0 2006.218.08:00:01.63#ibcon#*after write, iclass 28, count 0 2006.218.08:00:01.63#ibcon#*before return 0, iclass 28, count 0 2006.218.08:00:01.63#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.218.08:00:01.63#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.218.08:00:01.63#ibcon#about to clear, iclass 28 cls_cnt 0 2006.218.08:00:01.63#ibcon#cleared, iclass 28 cls_cnt 0 2006.218.08:00:01.63$vc4f8/vb=4,4 2006.218.08:00:01.63#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.218.08:00:01.63#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.218.08:00:01.63#ibcon#ireg 11 cls_cnt 2 2006.218.08:00:01.63#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.218.08:00:01.69#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.218.08:00:01.69#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.218.08:00:01.69#ibcon#enter wrdev, iclass 30, count 2 2006.218.08:00:01.69#ibcon#first serial, iclass 30, count 2 2006.218.08:00:01.69#ibcon#enter sib2, iclass 30, count 2 2006.218.08:00:01.69#ibcon#flushed, iclass 30, count 2 2006.218.08:00:01.69#ibcon#about to write, iclass 30, count 2 2006.218.08:00:01.69#ibcon#wrote, iclass 30, count 2 2006.218.08:00:01.69#ibcon#about to read 3, iclass 30, count 2 2006.218.08:00:01.71#ibcon#read 3, iclass 30, count 2 2006.218.08:00:01.71#ibcon#about to read 4, iclass 30, count 2 2006.218.08:00:01.71#ibcon#read 4, iclass 30, count 2 2006.218.08:00:01.71#ibcon#about to read 5, iclass 30, count 2 2006.218.08:00:01.71#ibcon#read 5, iclass 30, count 2 2006.218.08:00:01.71#ibcon#about to read 6, iclass 30, count 2 2006.218.08:00:01.71#ibcon#read 6, iclass 30, count 2 2006.218.08:00:01.71#ibcon#end of sib2, iclass 30, count 2 2006.218.08:00:01.71#ibcon#*mode == 0, iclass 30, count 2 2006.218.08:00:01.71#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.218.08:00:01.71#ibcon#[27=AT04-04\r\n] 2006.218.08:00:01.71#ibcon#*before write, iclass 30, count 2 2006.218.08:00:01.71#ibcon#enter sib2, iclass 30, count 2 2006.218.08:00:01.71#ibcon#flushed, iclass 30, count 2 2006.218.08:00:01.71#ibcon#about to write, iclass 30, count 2 2006.218.08:00:01.71#ibcon#wrote, iclass 30, count 2 2006.218.08:00:01.71#ibcon#about to read 3, iclass 30, count 2 2006.218.08:00:01.74#ibcon#read 3, iclass 30, count 2 2006.218.08:00:01.74#ibcon#about to read 4, iclass 30, count 2 2006.218.08:00:01.74#ibcon#read 4, iclass 30, count 2 2006.218.08:00:01.74#ibcon#about to read 5, iclass 30, count 2 2006.218.08:00:01.74#ibcon#read 5, iclass 30, count 2 2006.218.08:00:01.74#ibcon#about to read 6, iclass 30, count 2 2006.218.08:00:01.74#ibcon#read 6, iclass 30, count 2 2006.218.08:00:01.74#ibcon#end of sib2, iclass 30, count 2 2006.218.08:00:01.74#ibcon#*after write, iclass 30, count 2 2006.218.08:00:01.74#ibcon#*before return 0, iclass 30, count 2 2006.218.08:00:01.74#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.218.08:00:01.74#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.218.08:00:01.74#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.218.08:00:01.74#ibcon#ireg 7 cls_cnt 0 2006.218.08:00:01.74#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.218.08:00:01.86#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.218.08:00:01.86#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.218.08:00:01.86#ibcon#enter wrdev, iclass 30, count 0 2006.218.08:00:01.86#ibcon#first serial, iclass 30, count 0 2006.218.08:00:01.86#ibcon#enter sib2, iclass 30, count 0 2006.218.08:00:01.86#ibcon#flushed, iclass 30, count 0 2006.218.08:00:01.86#ibcon#about to write, iclass 30, count 0 2006.218.08:00:01.86#ibcon#wrote, iclass 30, count 0 2006.218.08:00:01.86#ibcon#about to read 3, iclass 30, count 0 2006.218.08:00:01.88#ibcon#read 3, iclass 30, count 0 2006.218.08:00:01.88#ibcon#about to read 4, iclass 30, count 0 2006.218.08:00:01.88#ibcon#read 4, iclass 30, count 0 2006.218.08:00:01.88#ibcon#about to read 5, iclass 30, count 0 2006.218.08:00:01.88#ibcon#read 5, iclass 30, count 0 2006.218.08:00:01.88#ibcon#about to read 6, iclass 30, count 0 2006.218.08:00:01.88#ibcon#read 6, iclass 30, count 0 2006.218.08:00:01.88#ibcon#end of sib2, iclass 30, count 0 2006.218.08:00:01.88#ibcon#*mode == 0, iclass 30, count 0 2006.218.08:00:01.88#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.218.08:00:01.88#ibcon#[27=USB\r\n] 2006.218.08:00:01.88#ibcon#*before write, iclass 30, count 0 2006.218.08:00:01.88#ibcon#enter sib2, iclass 30, count 0 2006.218.08:00:01.88#ibcon#flushed, iclass 30, count 0 2006.218.08:00:01.88#ibcon#about to write, iclass 30, count 0 2006.218.08:00:01.88#ibcon#wrote, iclass 30, count 0 2006.218.08:00:01.88#ibcon#about to read 3, iclass 30, count 0 2006.218.08:00:01.91#ibcon#read 3, iclass 30, count 0 2006.218.08:00:01.91#ibcon#about to read 4, iclass 30, count 0 2006.218.08:00:01.91#ibcon#read 4, iclass 30, count 0 2006.218.08:00:01.91#ibcon#about to read 5, iclass 30, count 0 2006.218.08:00:01.91#ibcon#read 5, iclass 30, count 0 2006.218.08:00:01.91#ibcon#about to read 6, iclass 30, count 0 2006.218.08:00:01.91#ibcon#read 6, iclass 30, count 0 2006.218.08:00:01.91#ibcon#end of sib2, iclass 30, count 0 2006.218.08:00:01.91#ibcon#*after write, iclass 30, count 0 2006.218.08:00:01.91#ibcon#*before return 0, iclass 30, count 0 2006.218.08:00:01.91#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.218.08:00:01.91#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.218.08:00:01.91#ibcon#about to clear, iclass 30 cls_cnt 0 2006.218.08:00:01.91#ibcon#cleared, iclass 30 cls_cnt 0 2006.218.08:00:01.91$vc4f8/vblo=5,744.99 2006.218.08:00:01.91#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.218.08:00:01.91#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.218.08:00:01.91#ibcon#ireg 17 cls_cnt 0 2006.218.08:00:01.91#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.218.08:00:01.91#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.218.08:00:01.91#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.218.08:00:01.91#ibcon#enter wrdev, iclass 32, count 0 2006.218.08:00:01.91#ibcon#first serial, iclass 32, count 0 2006.218.08:00:01.91#ibcon#enter sib2, iclass 32, count 0 2006.218.08:00:01.91#ibcon#flushed, iclass 32, count 0 2006.218.08:00:01.91#ibcon#about to write, iclass 32, count 0 2006.218.08:00:01.91#ibcon#wrote, iclass 32, count 0 2006.218.08:00:01.91#ibcon#about to read 3, iclass 32, count 0 2006.218.08:00:01.93#ibcon#read 3, iclass 32, count 0 2006.218.08:00:01.93#ibcon#about to read 4, iclass 32, count 0 2006.218.08:00:01.93#ibcon#read 4, iclass 32, count 0 2006.218.08:00:01.93#ibcon#about to read 5, iclass 32, count 0 2006.218.08:00:01.93#ibcon#read 5, iclass 32, count 0 2006.218.08:00:01.93#ibcon#about to read 6, iclass 32, count 0 2006.218.08:00:01.93#ibcon#read 6, iclass 32, count 0 2006.218.08:00:01.93#ibcon#end of sib2, iclass 32, count 0 2006.218.08:00:01.93#ibcon#*mode == 0, iclass 32, count 0 2006.218.08:00:01.93#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.218.08:00:01.93#ibcon#[28=FRQ=05,744.99\r\n] 2006.218.08:00:01.93#ibcon#*before write, iclass 32, count 0 2006.218.08:00:01.93#ibcon#enter sib2, iclass 32, count 0 2006.218.08:00:01.93#ibcon#flushed, iclass 32, count 0 2006.218.08:00:01.93#ibcon#about to write, iclass 32, count 0 2006.218.08:00:01.93#ibcon#wrote, iclass 32, count 0 2006.218.08:00:01.93#ibcon#about to read 3, iclass 32, count 0 2006.218.08:00:01.97#ibcon#read 3, iclass 32, count 0 2006.218.08:00:01.97#ibcon#about to read 4, iclass 32, count 0 2006.218.08:00:01.97#ibcon#read 4, iclass 32, count 0 2006.218.08:00:01.97#ibcon#about to read 5, iclass 32, count 0 2006.218.08:00:01.97#ibcon#read 5, iclass 32, count 0 2006.218.08:00:01.97#ibcon#about to read 6, iclass 32, count 0 2006.218.08:00:01.97#ibcon#read 6, iclass 32, count 0 2006.218.08:00:01.97#ibcon#end of sib2, iclass 32, count 0 2006.218.08:00:01.97#ibcon#*after write, iclass 32, count 0 2006.218.08:00:01.97#ibcon#*before return 0, iclass 32, count 0 2006.218.08:00:01.97#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.218.08:00:01.97#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.218.08:00:01.97#ibcon#about to clear, iclass 32 cls_cnt 0 2006.218.08:00:01.97#ibcon#cleared, iclass 32 cls_cnt 0 2006.218.08:00:01.97$vc4f8/vb=5,4 2006.218.08:00:01.97#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.218.08:00:01.97#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.218.08:00:01.97#ibcon#ireg 11 cls_cnt 2 2006.218.08:00:01.97#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.218.08:00:02.03#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.218.08:00:02.03#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.218.08:00:02.03#ibcon#enter wrdev, iclass 34, count 2 2006.218.08:00:02.03#ibcon#first serial, iclass 34, count 2 2006.218.08:00:02.03#ibcon#enter sib2, iclass 34, count 2 2006.218.08:00:02.03#ibcon#flushed, iclass 34, count 2 2006.218.08:00:02.03#ibcon#about to write, iclass 34, count 2 2006.218.08:00:02.03#ibcon#wrote, iclass 34, count 2 2006.218.08:00:02.03#ibcon#about to read 3, iclass 34, count 2 2006.218.08:00:02.05#ibcon#read 3, iclass 34, count 2 2006.218.08:00:02.05#ibcon#about to read 4, iclass 34, count 2 2006.218.08:00:02.05#ibcon#read 4, iclass 34, count 2 2006.218.08:00:02.05#ibcon#about to read 5, iclass 34, count 2 2006.218.08:00:02.05#ibcon#read 5, iclass 34, count 2 2006.218.08:00:02.05#ibcon#about to read 6, iclass 34, count 2 2006.218.08:00:02.05#ibcon#read 6, iclass 34, count 2 2006.218.08:00:02.05#ibcon#end of sib2, iclass 34, count 2 2006.218.08:00:02.05#ibcon#*mode == 0, iclass 34, count 2 2006.218.08:00:02.05#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.218.08:00:02.05#ibcon#[27=AT05-04\r\n] 2006.218.08:00:02.05#ibcon#*before write, iclass 34, count 2 2006.218.08:00:02.05#ibcon#enter sib2, iclass 34, count 2 2006.218.08:00:02.05#ibcon#flushed, iclass 34, count 2 2006.218.08:00:02.05#ibcon#about to write, iclass 34, count 2 2006.218.08:00:02.05#ibcon#wrote, iclass 34, count 2 2006.218.08:00:02.05#ibcon#about to read 3, iclass 34, count 2 2006.218.08:00:02.08#ibcon#read 3, iclass 34, count 2 2006.218.08:00:02.08#ibcon#about to read 4, iclass 34, count 2 2006.218.08:00:02.08#ibcon#read 4, iclass 34, count 2 2006.218.08:00:02.08#ibcon#about to read 5, iclass 34, count 2 2006.218.08:00:02.08#ibcon#read 5, iclass 34, count 2 2006.218.08:00:02.08#ibcon#about to read 6, iclass 34, count 2 2006.218.08:00:02.08#ibcon#read 6, iclass 34, count 2 2006.218.08:00:02.08#ibcon#end of sib2, iclass 34, count 2 2006.218.08:00:02.08#ibcon#*after write, iclass 34, count 2 2006.218.08:00:02.08#ibcon#*before return 0, iclass 34, count 2 2006.218.08:00:02.08#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.218.08:00:02.08#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.218.08:00:02.08#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.218.08:00:02.08#ibcon#ireg 7 cls_cnt 0 2006.218.08:00:02.08#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.218.08:00:02.20#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.218.08:00:02.20#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.218.08:00:02.20#ibcon#enter wrdev, iclass 34, count 0 2006.218.08:00:02.20#ibcon#first serial, iclass 34, count 0 2006.218.08:00:02.20#ibcon#enter sib2, iclass 34, count 0 2006.218.08:00:02.20#ibcon#flushed, iclass 34, count 0 2006.218.08:00:02.20#ibcon#about to write, iclass 34, count 0 2006.218.08:00:02.20#ibcon#wrote, iclass 34, count 0 2006.218.08:00:02.20#ibcon#about to read 3, iclass 34, count 0 2006.218.08:00:02.22#ibcon#read 3, iclass 34, count 0 2006.218.08:00:02.22#ibcon#about to read 4, iclass 34, count 0 2006.218.08:00:02.22#ibcon#read 4, iclass 34, count 0 2006.218.08:00:02.22#ibcon#about to read 5, iclass 34, count 0 2006.218.08:00:02.22#ibcon#read 5, iclass 34, count 0 2006.218.08:00:02.22#ibcon#about to read 6, iclass 34, count 0 2006.218.08:00:02.22#ibcon#read 6, iclass 34, count 0 2006.218.08:00:02.22#ibcon#end of sib2, iclass 34, count 0 2006.218.08:00:02.22#ibcon#*mode == 0, iclass 34, count 0 2006.218.08:00:02.22#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.218.08:00:02.22#ibcon#[27=USB\r\n] 2006.218.08:00:02.22#ibcon#*before write, iclass 34, count 0 2006.218.08:00:02.22#ibcon#enter sib2, iclass 34, count 0 2006.218.08:00:02.22#ibcon#flushed, iclass 34, count 0 2006.218.08:00:02.22#ibcon#about to write, iclass 34, count 0 2006.218.08:00:02.22#ibcon#wrote, iclass 34, count 0 2006.218.08:00:02.22#ibcon#about to read 3, iclass 34, count 0 2006.218.08:00:02.25#ibcon#read 3, iclass 34, count 0 2006.218.08:00:02.25#ibcon#about to read 4, iclass 34, count 0 2006.218.08:00:02.25#ibcon#read 4, iclass 34, count 0 2006.218.08:00:02.25#ibcon#about to read 5, iclass 34, count 0 2006.218.08:00:02.25#ibcon#read 5, iclass 34, count 0 2006.218.08:00:02.25#ibcon#about to read 6, iclass 34, count 0 2006.218.08:00:02.25#ibcon#read 6, iclass 34, count 0 2006.218.08:00:02.25#ibcon#end of sib2, iclass 34, count 0 2006.218.08:00:02.25#ibcon#*after write, iclass 34, count 0 2006.218.08:00:02.25#ibcon#*before return 0, iclass 34, count 0 2006.218.08:00:02.25#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.218.08:00:02.25#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.218.08:00:02.25#ibcon#about to clear, iclass 34 cls_cnt 0 2006.218.08:00:02.25#ibcon#cleared, iclass 34 cls_cnt 0 2006.218.08:00:02.25$vc4f8/vblo=6,752.99 2006.218.08:00:02.25#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.218.08:00:02.25#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.218.08:00:02.25#ibcon#ireg 17 cls_cnt 0 2006.218.08:00:02.25#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.218.08:00:02.25#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.218.08:00:02.25#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.218.08:00:02.25#ibcon#enter wrdev, iclass 36, count 0 2006.218.08:00:02.25#ibcon#first serial, iclass 36, count 0 2006.218.08:00:02.25#ibcon#enter sib2, iclass 36, count 0 2006.218.08:00:02.25#ibcon#flushed, iclass 36, count 0 2006.218.08:00:02.25#ibcon#about to write, iclass 36, count 0 2006.218.08:00:02.25#ibcon#wrote, iclass 36, count 0 2006.218.08:00:02.25#ibcon#about to read 3, iclass 36, count 0 2006.218.08:00:02.27#ibcon#read 3, iclass 36, count 0 2006.218.08:00:02.27#ibcon#about to read 4, iclass 36, count 0 2006.218.08:00:02.27#ibcon#read 4, iclass 36, count 0 2006.218.08:00:02.27#ibcon#about to read 5, iclass 36, count 0 2006.218.08:00:02.27#ibcon#read 5, iclass 36, count 0 2006.218.08:00:02.27#ibcon#about to read 6, iclass 36, count 0 2006.218.08:00:02.27#ibcon#read 6, iclass 36, count 0 2006.218.08:00:02.27#ibcon#end of sib2, iclass 36, count 0 2006.218.08:00:02.27#ibcon#*mode == 0, iclass 36, count 0 2006.218.08:00:02.27#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.218.08:00:02.27#ibcon#[28=FRQ=06,752.99\r\n] 2006.218.08:00:02.27#ibcon#*before write, iclass 36, count 0 2006.218.08:00:02.27#ibcon#enter sib2, iclass 36, count 0 2006.218.08:00:02.27#ibcon#flushed, iclass 36, count 0 2006.218.08:00:02.27#ibcon#about to write, iclass 36, count 0 2006.218.08:00:02.27#ibcon#wrote, iclass 36, count 0 2006.218.08:00:02.27#ibcon#about to read 3, iclass 36, count 0 2006.218.08:00:02.32#ibcon#read 3, iclass 36, count 0 2006.218.08:00:02.32#ibcon#about to read 4, iclass 36, count 0 2006.218.08:00:02.32#ibcon#read 4, iclass 36, count 0 2006.218.08:00:02.32#ibcon#about to read 5, iclass 36, count 0 2006.218.08:00:02.32#ibcon#read 5, iclass 36, count 0 2006.218.08:00:02.32#ibcon#about to read 6, iclass 36, count 0 2006.218.08:00:02.32#ibcon#read 6, iclass 36, count 0 2006.218.08:00:02.32#ibcon#end of sib2, iclass 36, count 0 2006.218.08:00:02.32#ibcon#*after write, iclass 36, count 0 2006.218.08:00:02.32#ibcon#*before return 0, iclass 36, count 0 2006.218.08:00:02.32#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.218.08:00:02.32#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.218.08:00:02.32#ibcon#about to clear, iclass 36 cls_cnt 0 2006.218.08:00:02.32#ibcon#cleared, iclass 36 cls_cnt 0 2006.218.08:00:02.32$vc4f8/vb=6,4 2006.218.08:00:02.32#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.218.08:00:02.32#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.218.08:00:02.32#ibcon#ireg 11 cls_cnt 2 2006.218.08:00:02.32#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.218.08:00:02.36#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.218.08:00:02.36#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.218.08:00:02.36#ibcon#enter wrdev, iclass 38, count 2 2006.218.08:00:02.36#ibcon#first serial, iclass 38, count 2 2006.218.08:00:02.36#ibcon#enter sib2, iclass 38, count 2 2006.218.08:00:02.36#ibcon#flushed, iclass 38, count 2 2006.218.08:00:02.36#ibcon#about to write, iclass 38, count 2 2006.218.08:00:02.36#ibcon#wrote, iclass 38, count 2 2006.218.08:00:02.36#ibcon#about to read 3, iclass 38, count 2 2006.218.08:00:02.38#ibcon#read 3, iclass 38, count 2 2006.218.08:00:02.38#ibcon#about to read 4, iclass 38, count 2 2006.218.08:00:02.38#ibcon#read 4, iclass 38, count 2 2006.218.08:00:02.38#ibcon#about to read 5, iclass 38, count 2 2006.218.08:00:02.38#ibcon#read 5, iclass 38, count 2 2006.218.08:00:02.38#ibcon#about to read 6, iclass 38, count 2 2006.218.08:00:02.38#ibcon#read 6, iclass 38, count 2 2006.218.08:00:02.38#ibcon#end of sib2, iclass 38, count 2 2006.218.08:00:02.38#ibcon#*mode == 0, iclass 38, count 2 2006.218.08:00:02.38#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.218.08:00:02.38#ibcon#[27=AT06-04\r\n] 2006.218.08:00:02.38#ibcon#*before write, iclass 38, count 2 2006.218.08:00:02.38#ibcon#enter sib2, iclass 38, count 2 2006.218.08:00:02.38#ibcon#flushed, iclass 38, count 2 2006.218.08:00:02.38#ibcon#about to write, iclass 38, count 2 2006.218.08:00:02.38#ibcon#wrote, iclass 38, count 2 2006.218.08:00:02.38#ibcon#about to read 3, iclass 38, count 2 2006.218.08:00:02.41#ibcon#read 3, iclass 38, count 2 2006.218.08:00:02.41#ibcon#about to read 4, iclass 38, count 2 2006.218.08:00:02.41#ibcon#read 4, iclass 38, count 2 2006.218.08:00:02.41#ibcon#about to read 5, iclass 38, count 2 2006.218.08:00:02.41#ibcon#read 5, iclass 38, count 2 2006.218.08:00:02.41#ibcon#about to read 6, iclass 38, count 2 2006.218.08:00:02.41#ibcon#read 6, iclass 38, count 2 2006.218.08:00:02.41#ibcon#end of sib2, iclass 38, count 2 2006.218.08:00:02.41#ibcon#*after write, iclass 38, count 2 2006.218.08:00:02.41#ibcon#*before return 0, iclass 38, count 2 2006.218.08:00:02.41#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.218.08:00:02.41#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.218.08:00:02.41#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.218.08:00:02.41#ibcon#ireg 7 cls_cnt 0 2006.218.08:00:02.41#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.218.08:00:02.53#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.218.08:00:02.53#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.218.08:00:02.53#ibcon#enter wrdev, iclass 38, count 0 2006.218.08:00:02.53#ibcon#first serial, iclass 38, count 0 2006.218.08:00:02.53#ibcon#enter sib2, iclass 38, count 0 2006.218.08:00:02.53#ibcon#flushed, iclass 38, count 0 2006.218.08:00:02.53#ibcon#about to write, iclass 38, count 0 2006.218.08:00:02.53#ibcon#wrote, iclass 38, count 0 2006.218.08:00:02.53#ibcon#about to read 3, iclass 38, count 0 2006.218.08:00:02.55#ibcon#read 3, iclass 38, count 0 2006.218.08:00:02.55#ibcon#about to read 4, iclass 38, count 0 2006.218.08:00:02.55#ibcon#read 4, iclass 38, count 0 2006.218.08:00:02.55#ibcon#about to read 5, iclass 38, count 0 2006.218.08:00:02.55#ibcon#read 5, iclass 38, count 0 2006.218.08:00:02.55#ibcon#about to read 6, iclass 38, count 0 2006.218.08:00:02.55#ibcon#read 6, iclass 38, count 0 2006.218.08:00:02.55#ibcon#end of sib2, iclass 38, count 0 2006.218.08:00:02.55#ibcon#*mode == 0, iclass 38, count 0 2006.218.08:00:02.55#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.218.08:00:02.55#ibcon#[27=USB\r\n] 2006.218.08:00:02.55#ibcon#*before write, iclass 38, count 0 2006.218.08:00:02.55#ibcon#enter sib2, iclass 38, count 0 2006.218.08:00:02.55#ibcon#flushed, iclass 38, count 0 2006.218.08:00:02.55#ibcon#about to write, iclass 38, count 0 2006.218.08:00:02.55#ibcon#wrote, iclass 38, count 0 2006.218.08:00:02.55#ibcon#about to read 3, iclass 38, count 0 2006.218.08:00:02.58#ibcon#read 3, iclass 38, count 0 2006.218.08:00:02.58#ibcon#about to read 4, iclass 38, count 0 2006.218.08:00:02.58#ibcon#read 4, iclass 38, count 0 2006.218.08:00:02.58#ibcon#about to read 5, iclass 38, count 0 2006.218.08:00:02.58#ibcon#read 5, iclass 38, count 0 2006.218.08:00:02.58#ibcon#about to read 6, iclass 38, count 0 2006.218.08:00:02.58#ibcon#read 6, iclass 38, count 0 2006.218.08:00:02.58#ibcon#end of sib2, iclass 38, count 0 2006.218.08:00:02.58#ibcon#*after write, iclass 38, count 0 2006.218.08:00:02.58#ibcon#*before return 0, iclass 38, count 0 2006.218.08:00:02.58#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.218.08:00:02.58#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.218.08:00:02.58#ibcon#about to clear, iclass 38 cls_cnt 0 2006.218.08:00:02.58#ibcon#cleared, iclass 38 cls_cnt 0 2006.218.08:00:02.58$vc4f8/vabw=wide 2006.218.08:00:02.58#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.218.08:00:02.58#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.218.08:00:02.58#ibcon#ireg 8 cls_cnt 0 2006.218.08:00:02.58#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.218.08:00:02.58#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.218.08:00:02.58#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.218.08:00:02.58#ibcon#enter wrdev, iclass 40, count 0 2006.218.08:00:02.58#ibcon#first serial, iclass 40, count 0 2006.218.08:00:02.58#ibcon#enter sib2, iclass 40, count 0 2006.218.08:00:02.58#ibcon#flushed, iclass 40, count 0 2006.218.08:00:02.58#ibcon#about to write, iclass 40, count 0 2006.218.08:00:02.58#ibcon#wrote, iclass 40, count 0 2006.218.08:00:02.58#ibcon#about to read 3, iclass 40, count 0 2006.218.08:00:02.60#ibcon#read 3, iclass 40, count 0 2006.218.08:00:02.60#ibcon#about to read 4, iclass 40, count 0 2006.218.08:00:02.60#ibcon#read 4, iclass 40, count 0 2006.218.08:00:02.60#ibcon#about to read 5, iclass 40, count 0 2006.218.08:00:02.60#ibcon#read 5, iclass 40, count 0 2006.218.08:00:02.60#ibcon#about to read 6, iclass 40, count 0 2006.218.08:00:02.60#ibcon#read 6, iclass 40, count 0 2006.218.08:00:02.60#ibcon#end of sib2, iclass 40, count 0 2006.218.08:00:02.60#ibcon#*mode == 0, iclass 40, count 0 2006.218.08:00:02.60#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.218.08:00:02.60#ibcon#[25=BW32\r\n] 2006.218.08:00:02.60#ibcon#*before write, iclass 40, count 0 2006.218.08:00:02.60#ibcon#enter sib2, iclass 40, count 0 2006.218.08:00:02.60#ibcon#flushed, iclass 40, count 0 2006.218.08:00:02.60#ibcon#about to write, iclass 40, count 0 2006.218.08:00:02.60#ibcon#wrote, iclass 40, count 0 2006.218.08:00:02.60#ibcon#about to read 3, iclass 40, count 0 2006.218.08:00:02.63#ibcon#read 3, iclass 40, count 0 2006.218.08:00:02.63#ibcon#about to read 4, iclass 40, count 0 2006.218.08:00:02.63#ibcon#read 4, iclass 40, count 0 2006.218.08:00:02.63#ibcon#about to read 5, iclass 40, count 0 2006.218.08:00:02.63#ibcon#read 5, iclass 40, count 0 2006.218.08:00:02.63#ibcon#about to read 6, iclass 40, count 0 2006.218.08:00:02.63#ibcon#read 6, iclass 40, count 0 2006.218.08:00:02.63#ibcon#end of sib2, iclass 40, count 0 2006.218.08:00:02.63#ibcon#*after write, iclass 40, count 0 2006.218.08:00:02.63#ibcon#*before return 0, iclass 40, count 0 2006.218.08:00:02.63#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.218.08:00:02.63#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.218.08:00:02.63#ibcon#about to clear, iclass 40 cls_cnt 0 2006.218.08:00:02.63#ibcon#cleared, iclass 40 cls_cnt 0 2006.218.08:00:02.63$vc4f8/vbbw=wide 2006.218.08:00:02.63#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.218.08:00:02.63#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.218.08:00:02.63#ibcon#ireg 8 cls_cnt 0 2006.218.08:00:02.63#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.218.08:00:02.70#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.218.08:00:02.70#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.218.08:00:02.70#ibcon#enter wrdev, iclass 4, count 0 2006.218.08:00:02.70#ibcon#first serial, iclass 4, count 0 2006.218.08:00:02.70#ibcon#enter sib2, iclass 4, count 0 2006.218.08:00:02.70#ibcon#flushed, iclass 4, count 0 2006.218.08:00:02.70#ibcon#about to write, iclass 4, count 0 2006.218.08:00:02.70#ibcon#wrote, iclass 4, count 0 2006.218.08:00:02.70#ibcon#about to read 3, iclass 4, count 0 2006.218.08:00:02.72#ibcon#read 3, iclass 4, count 0 2006.218.08:00:02.72#ibcon#about to read 4, iclass 4, count 0 2006.218.08:00:02.72#ibcon#read 4, iclass 4, count 0 2006.218.08:00:02.72#ibcon#about to read 5, iclass 4, count 0 2006.218.08:00:02.72#ibcon#read 5, iclass 4, count 0 2006.218.08:00:02.72#ibcon#about to read 6, iclass 4, count 0 2006.218.08:00:02.72#ibcon#read 6, iclass 4, count 0 2006.218.08:00:02.72#ibcon#end of sib2, iclass 4, count 0 2006.218.08:00:02.72#ibcon#*mode == 0, iclass 4, count 0 2006.218.08:00:02.72#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.218.08:00:02.72#ibcon#[27=BW32\r\n] 2006.218.08:00:02.72#ibcon#*before write, iclass 4, count 0 2006.218.08:00:02.72#ibcon#enter sib2, iclass 4, count 0 2006.218.08:00:02.72#ibcon#flushed, iclass 4, count 0 2006.218.08:00:02.72#ibcon#about to write, iclass 4, count 0 2006.218.08:00:02.72#ibcon#wrote, iclass 4, count 0 2006.218.08:00:02.72#ibcon#about to read 3, iclass 4, count 0 2006.218.08:00:02.75#ibcon#read 3, iclass 4, count 0 2006.218.08:00:02.75#ibcon#about to read 4, iclass 4, count 0 2006.218.08:00:02.75#ibcon#read 4, iclass 4, count 0 2006.218.08:00:02.75#ibcon#about to read 5, iclass 4, count 0 2006.218.08:00:02.75#ibcon#read 5, iclass 4, count 0 2006.218.08:00:02.75#ibcon#about to read 6, iclass 4, count 0 2006.218.08:00:02.75#ibcon#read 6, iclass 4, count 0 2006.218.08:00:02.75#ibcon#end of sib2, iclass 4, count 0 2006.218.08:00:02.75#ibcon#*after write, iclass 4, count 0 2006.218.08:00:02.75#ibcon#*before return 0, iclass 4, count 0 2006.218.08:00:02.75#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.218.08:00:02.75#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.218.08:00:02.75#ibcon#about to clear, iclass 4 cls_cnt 0 2006.218.08:00:02.75#ibcon#cleared, iclass 4 cls_cnt 0 2006.218.08:00:02.75$4f8m12a/ifd4f 2006.218.08:00:02.75$ifd4f/lo= 2006.218.08:00:02.75$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.218.08:00:02.75$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.218.08:00:02.75$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.218.08:00:02.75$ifd4f/patch= 2006.218.08:00:02.75$ifd4f/patch=lo1,a1,a2,a3,a4 2006.218.08:00:02.75$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.218.08:00:02.75$ifd4f/patch=lo3,a5,a6,a7,a8 2006.218.08:00:02.75$4f8m12a/"form=m,16.000,1:2 2006.218.08:00:02.75$4f8m12a/"tpicd 2006.218.08:00:02.75$4f8m12a/echo=off 2006.218.08:00:02.75$4f8m12a/xlog=off 2006.218.08:00:02.75:!2006.218.08:00:40 2006.218.08:00:18.14#trakl#Source acquired 2006.218.08:00:20.14#flagr#flagr/antenna,acquired 2006.218.08:00:40.00:preob 2006.218.08:00:40.14/onsource/TRACKING 2006.218.08:00:40.14:!2006.218.08:00:50 2006.218.08:00:50.00:data_valid=on 2006.218.08:00:50.00:midob 2006.218.08:00:50.14/onsource/TRACKING 2006.218.08:00:50.14/wx/31.02,1007.5,72 2006.218.08:00:50.29/cable/+6.3843E-03 2006.218.08:00:51.38/va/01,05,usb,yes,32,33 2006.218.08:00:51.38/va/02,04,usb,yes,30,31 2006.218.08:00:51.38/va/03,04,usb,yes,28,28 2006.218.08:00:51.38/va/04,04,usb,yes,31,33 2006.218.08:00:51.38/va/05,07,usb,yes,33,35 2006.218.08:00:51.38/va/06,06,usb,yes,32,32 2006.218.08:00:51.38/va/07,06,usb,yes,33,32 2006.218.08:00:51.38/va/08,07,usb,yes,31,30 2006.218.08:00:51.61/valo/01,532.99,yes,locked 2006.218.08:00:51.61/valo/02,572.99,yes,locked 2006.218.08:00:51.61/valo/03,672.99,yes,locked 2006.218.08:00:51.61/valo/04,832.99,yes,locked 2006.218.08:00:51.61/valo/05,652.99,yes,locked 2006.218.08:00:51.61/valo/06,772.99,yes,locked 2006.218.08:00:51.61/valo/07,832.99,yes,locked 2006.218.08:00:51.61/valo/08,852.99,yes,locked 2006.218.08:00:52.70/vb/01,04,usb,yes,30,29 2006.218.08:00:52.70/vb/02,04,usb,yes,32,33 2006.218.08:00:52.70/vb/03,04,usb,yes,28,32 2006.218.08:00:52.70/vb/04,04,usb,yes,29,29 2006.218.08:00:52.70/vb/05,04,usb,yes,28,32 2006.218.08:00:52.70/vb/06,04,usb,yes,28,31 2006.218.08:00:52.70/vb/07,04,usb,yes,31,31 2006.218.08:00:52.70/vb/08,04,usb,yes,28,32 2006.218.08:00:52.94/vblo/01,632.99,yes,locked 2006.218.08:00:52.94/vblo/02,640.99,yes,locked 2006.218.08:00:52.94/vblo/03,656.99,yes,locked 2006.218.08:00:52.94/vblo/04,712.99,yes,locked 2006.218.08:00:52.94/vblo/05,744.99,yes,locked 2006.218.08:00:52.94/vblo/06,752.99,yes,locked 2006.218.08:00:52.94/vblo/07,734.99,yes,locked 2006.218.08:00:52.94/vblo/08,744.99,yes,locked 2006.218.08:00:53.09/vabw/8 2006.218.08:00:53.24/vbbw/8 2006.218.08:00:53.33/xfe/off,on,15.5 2006.218.08:00:53.72/ifatt/23,28,28,28 2006.218.08:00:54.07/fmout-gps/S +4.68E-07 2006.218.08:00:54.15:!2006.218.08:01:50 2006.218.08:01:50.01:data_valid=off 2006.218.08:01:50.02:postob 2006.218.08:01:50.25/cable/+6.3832E-03 2006.218.08:01:50.26/wx/31.01,1007.5,72 2006.218.08:01:51.07/fmout-gps/S +4.67E-07 2006.218.08:01:51.08:scan_name=218-0802,k06218,60 2006.218.08:01:51.08:source=0642+449,064632.03,445116.6,2000.0,cw 2006.218.08:01:51.13#flagr#flagr/antenna,new-source 2006.218.08:01:52.13:checkk5 2006.218.08:01:52.51/chk_autoobs//k5ts1/ autoobs is running! 2006.218.08:01:52.89/chk_autoobs//k5ts2/ autoobs is running! 2006.218.08:01:53.27/chk_autoobs//k5ts3/ autoobs is running! 2006.218.08:01:53.65/chk_autoobs//k5ts4/ autoobs is running! 2006.218.08:01:54.01/chk_obsdata//k5ts1/T2180800??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.08:01:54.38/chk_obsdata//k5ts2/T2180800??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.08:01:54.75/chk_obsdata//k5ts3/T2180800??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.08:01:55.12/chk_obsdata//k5ts4/T2180800??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.08:01:55.81/k5log//k5ts1_log_newline 2006.218.08:01:56.49/k5log//k5ts2_log_newline 2006.218.08:01:57.18/k5log//k5ts3_log_newline 2006.218.08:01:57.87/k5log//k5ts4_log_newline 2006.218.08:01:57.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.218.08:01:57.90:4f8m12a=2 2006.218.08:01:57.90$4f8m12a/echo=on 2006.218.08:01:57.90$4f8m12a/pcalon 2006.218.08:01:57.90$pcalon/"no phase cal control is implemented here 2006.218.08:01:57.90$4f8m12a/"tpicd=stop 2006.218.08:01:57.90$4f8m12a/vc4f8 2006.218.08:01:57.90$vc4f8/valo=1,532.99 2006.218.08:01:57.90#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.218.08:01:57.90#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.218.08:01:57.90#ibcon#ireg 17 cls_cnt 0 2006.218.08:01:57.90#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.218.08:01:57.90#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.218.08:01:57.90#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.218.08:01:57.90#ibcon#enter wrdev, iclass 21, count 0 2006.218.08:01:57.90#ibcon#first serial, iclass 21, count 0 2006.218.08:01:57.90#ibcon#enter sib2, iclass 21, count 0 2006.218.08:01:57.90#ibcon#flushed, iclass 21, count 0 2006.218.08:01:57.90#ibcon#about to write, iclass 21, count 0 2006.218.08:01:57.90#ibcon#wrote, iclass 21, count 0 2006.218.08:01:57.90#ibcon#about to read 3, iclass 21, count 0 2006.218.08:01:57.91#ibcon#read 3, iclass 21, count 0 2006.218.08:01:57.91#ibcon#about to read 4, iclass 21, count 0 2006.218.08:01:57.91#ibcon#read 4, iclass 21, count 0 2006.218.08:01:57.91#ibcon#about to read 5, iclass 21, count 0 2006.218.08:01:57.91#ibcon#read 5, iclass 21, count 0 2006.218.08:01:57.91#ibcon#about to read 6, iclass 21, count 0 2006.218.08:01:57.91#ibcon#read 6, iclass 21, count 0 2006.218.08:01:57.91#ibcon#end of sib2, iclass 21, count 0 2006.218.08:01:57.91#ibcon#*mode == 0, iclass 21, count 0 2006.218.08:01:57.91#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.218.08:01:57.91#ibcon#[26=FRQ=01,532.99\r\n] 2006.218.08:01:57.91#ibcon#*before write, iclass 21, count 0 2006.218.08:01:57.91#ibcon#enter sib2, iclass 21, count 0 2006.218.08:01:57.91#ibcon#flushed, iclass 21, count 0 2006.218.08:01:57.91#ibcon#about to write, iclass 21, count 0 2006.218.08:01:57.91#ibcon#wrote, iclass 21, count 0 2006.218.08:01:57.91#ibcon#about to read 3, iclass 21, count 0 2006.218.08:01:57.96#ibcon#read 3, iclass 21, count 0 2006.218.08:01:57.96#ibcon#about to read 4, iclass 21, count 0 2006.218.08:01:57.96#ibcon#read 4, iclass 21, count 0 2006.218.08:01:57.96#ibcon#about to read 5, iclass 21, count 0 2006.218.08:01:57.96#ibcon#read 5, iclass 21, count 0 2006.218.08:01:57.96#ibcon#about to read 6, iclass 21, count 0 2006.218.08:01:57.96#ibcon#read 6, iclass 21, count 0 2006.218.08:01:57.96#ibcon#end of sib2, iclass 21, count 0 2006.218.08:01:57.96#ibcon#*after write, iclass 21, count 0 2006.218.08:01:57.96#ibcon#*before return 0, iclass 21, count 0 2006.218.08:01:57.96#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.218.08:01:57.96#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.218.08:01:57.96#ibcon#about to clear, iclass 21 cls_cnt 0 2006.218.08:01:57.96#ibcon#cleared, iclass 21 cls_cnt 0 2006.218.08:01:57.96$vc4f8/va=1,5 2006.218.08:01:57.96#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.218.08:01:57.96#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.218.08:01:57.96#ibcon#ireg 11 cls_cnt 2 2006.218.08:01:57.96#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.218.08:01:57.96#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.218.08:01:57.96#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.218.08:01:57.96#ibcon#enter wrdev, iclass 23, count 2 2006.218.08:01:57.96#ibcon#first serial, iclass 23, count 2 2006.218.08:01:57.96#ibcon#enter sib2, iclass 23, count 2 2006.218.08:01:57.96#ibcon#flushed, iclass 23, count 2 2006.218.08:01:57.96#ibcon#about to write, iclass 23, count 2 2006.218.08:01:57.96#ibcon#wrote, iclass 23, count 2 2006.218.08:01:57.96#ibcon#about to read 3, iclass 23, count 2 2006.218.08:01:57.98#ibcon#read 3, iclass 23, count 2 2006.218.08:01:57.98#ibcon#about to read 4, iclass 23, count 2 2006.218.08:01:57.98#ibcon#read 4, iclass 23, count 2 2006.218.08:01:57.98#ibcon#about to read 5, iclass 23, count 2 2006.218.08:01:57.98#ibcon#read 5, iclass 23, count 2 2006.218.08:01:57.98#ibcon#about to read 6, iclass 23, count 2 2006.218.08:01:57.98#ibcon#read 6, iclass 23, count 2 2006.218.08:01:57.98#ibcon#end of sib2, iclass 23, count 2 2006.218.08:01:57.98#ibcon#*mode == 0, iclass 23, count 2 2006.218.08:01:57.98#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.218.08:01:57.98#ibcon#[25=AT01-05\r\n] 2006.218.08:01:57.98#ibcon#*before write, iclass 23, count 2 2006.218.08:01:57.98#ibcon#enter sib2, iclass 23, count 2 2006.218.08:01:57.98#ibcon#flushed, iclass 23, count 2 2006.218.08:01:57.98#ibcon#about to write, iclass 23, count 2 2006.218.08:01:57.98#ibcon#wrote, iclass 23, count 2 2006.218.08:01:57.98#ibcon#about to read 3, iclass 23, count 2 2006.218.08:01:58.01#ibcon#read 3, iclass 23, count 2 2006.218.08:01:58.01#ibcon#about to read 4, iclass 23, count 2 2006.218.08:01:58.01#ibcon#read 4, iclass 23, count 2 2006.218.08:01:58.01#ibcon#about to read 5, iclass 23, count 2 2006.218.08:01:58.01#ibcon#read 5, iclass 23, count 2 2006.218.08:01:58.01#ibcon#about to read 6, iclass 23, count 2 2006.218.08:01:58.01#ibcon#read 6, iclass 23, count 2 2006.218.08:01:58.01#ibcon#end of sib2, iclass 23, count 2 2006.218.08:01:58.01#ibcon#*after write, iclass 23, count 2 2006.218.08:01:58.01#ibcon#*before return 0, iclass 23, count 2 2006.218.08:01:58.01#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.218.08:01:58.01#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.218.08:01:58.01#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.218.08:01:58.01#ibcon#ireg 7 cls_cnt 0 2006.218.08:01:58.01#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.218.08:01:58.14#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.218.08:01:58.14#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.218.08:01:58.14#ibcon#enter wrdev, iclass 23, count 0 2006.218.08:01:58.14#ibcon#first serial, iclass 23, count 0 2006.218.08:01:58.14#ibcon#enter sib2, iclass 23, count 0 2006.218.08:01:58.14#ibcon#flushed, iclass 23, count 0 2006.218.08:01:58.14#ibcon#about to write, iclass 23, count 0 2006.218.08:01:58.14#ibcon#wrote, iclass 23, count 0 2006.218.08:01:58.14#ibcon#about to read 3, iclass 23, count 0 2006.218.08:01:58.15#ibcon#read 3, iclass 23, count 0 2006.218.08:01:58.15#ibcon#about to read 4, iclass 23, count 0 2006.218.08:01:58.15#ibcon#read 4, iclass 23, count 0 2006.218.08:01:58.15#ibcon#about to read 5, iclass 23, count 0 2006.218.08:01:58.15#ibcon#read 5, iclass 23, count 0 2006.218.08:01:58.15#ibcon#about to read 6, iclass 23, count 0 2006.218.08:01:58.15#ibcon#read 6, iclass 23, count 0 2006.218.08:01:58.15#ibcon#end of sib2, iclass 23, count 0 2006.218.08:01:58.15#ibcon#*mode == 0, iclass 23, count 0 2006.218.08:01:58.15#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.218.08:01:58.15#ibcon#[25=USB\r\n] 2006.218.08:01:58.15#ibcon#*before write, iclass 23, count 0 2006.218.08:01:58.15#ibcon#enter sib2, iclass 23, count 0 2006.218.08:01:58.15#ibcon#flushed, iclass 23, count 0 2006.218.08:01:58.15#ibcon#about to write, iclass 23, count 0 2006.218.08:01:58.15#ibcon#wrote, iclass 23, count 0 2006.218.08:01:58.15#ibcon#about to read 3, iclass 23, count 0 2006.218.08:01:58.18#ibcon#read 3, iclass 23, count 0 2006.218.08:01:58.18#ibcon#about to read 4, iclass 23, count 0 2006.218.08:01:58.18#ibcon#read 4, iclass 23, count 0 2006.218.08:01:58.18#ibcon#about to read 5, iclass 23, count 0 2006.218.08:01:58.18#ibcon#read 5, iclass 23, count 0 2006.218.08:01:58.18#ibcon#about to read 6, iclass 23, count 0 2006.218.08:01:58.18#ibcon#read 6, iclass 23, count 0 2006.218.08:01:58.18#ibcon#end of sib2, iclass 23, count 0 2006.218.08:01:58.18#ibcon#*after write, iclass 23, count 0 2006.218.08:01:58.18#ibcon#*before return 0, iclass 23, count 0 2006.218.08:01:58.18#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.218.08:01:58.18#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.218.08:01:58.18#ibcon#about to clear, iclass 23 cls_cnt 0 2006.218.08:01:58.18#ibcon#cleared, iclass 23 cls_cnt 0 2006.218.08:01:58.18$vc4f8/valo=2,572.99 2006.218.08:01:58.18#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.218.08:01:58.18#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.218.08:01:58.18#ibcon#ireg 17 cls_cnt 0 2006.218.08:01:58.18#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.218.08:01:58.18#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.218.08:01:58.18#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.218.08:01:58.18#ibcon#enter wrdev, iclass 25, count 0 2006.218.08:01:58.18#ibcon#first serial, iclass 25, count 0 2006.218.08:01:58.18#ibcon#enter sib2, iclass 25, count 0 2006.218.08:01:58.18#ibcon#flushed, iclass 25, count 0 2006.218.08:01:58.18#ibcon#about to write, iclass 25, count 0 2006.218.08:01:58.18#ibcon#wrote, iclass 25, count 0 2006.218.08:01:58.18#ibcon#about to read 3, iclass 25, count 0 2006.218.08:01:58.21#ibcon#read 3, iclass 25, count 0 2006.218.08:01:58.21#ibcon#about to read 4, iclass 25, count 0 2006.218.08:01:58.21#ibcon#read 4, iclass 25, count 0 2006.218.08:01:58.21#ibcon#about to read 5, iclass 25, count 0 2006.218.08:01:58.21#ibcon#read 5, iclass 25, count 0 2006.218.08:01:58.21#ibcon#about to read 6, iclass 25, count 0 2006.218.08:01:58.21#ibcon#read 6, iclass 25, count 0 2006.218.08:01:58.21#ibcon#end of sib2, iclass 25, count 0 2006.218.08:01:58.21#ibcon#*mode == 0, iclass 25, count 0 2006.218.08:01:58.21#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.218.08:01:58.21#ibcon#[26=FRQ=02,572.99\r\n] 2006.218.08:01:58.21#ibcon#*before write, iclass 25, count 0 2006.218.08:01:58.21#ibcon#enter sib2, iclass 25, count 0 2006.218.08:01:58.21#ibcon#flushed, iclass 25, count 0 2006.218.08:01:58.21#ibcon#about to write, iclass 25, count 0 2006.218.08:01:58.21#ibcon#wrote, iclass 25, count 0 2006.218.08:01:58.21#ibcon#about to read 3, iclass 25, count 0 2006.218.08:01:58.25#ibcon#read 3, iclass 25, count 0 2006.218.08:01:58.25#ibcon#about to read 4, iclass 25, count 0 2006.218.08:01:58.25#ibcon#read 4, iclass 25, count 0 2006.218.08:01:58.25#ibcon#about to read 5, iclass 25, count 0 2006.218.08:01:58.25#ibcon#read 5, iclass 25, count 0 2006.218.08:01:58.25#ibcon#about to read 6, iclass 25, count 0 2006.218.08:01:58.25#ibcon#read 6, iclass 25, count 0 2006.218.08:01:58.25#ibcon#end of sib2, iclass 25, count 0 2006.218.08:01:58.25#ibcon#*after write, iclass 25, count 0 2006.218.08:01:58.25#ibcon#*before return 0, iclass 25, count 0 2006.218.08:01:58.25#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.218.08:01:58.25#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.218.08:01:58.25#ibcon#about to clear, iclass 25 cls_cnt 0 2006.218.08:01:58.25#ibcon#cleared, iclass 25 cls_cnt 0 2006.218.08:01:58.25$vc4f8/va=2,4 2006.218.08:01:58.25#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.218.08:01:58.25#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.218.08:01:58.25#ibcon#ireg 11 cls_cnt 2 2006.218.08:01:58.25#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.218.08:01:58.30#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.218.08:01:58.30#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.218.08:01:58.30#ibcon#enter wrdev, iclass 27, count 2 2006.218.08:01:58.30#ibcon#first serial, iclass 27, count 2 2006.218.08:01:58.30#ibcon#enter sib2, iclass 27, count 2 2006.218.08:01:58.30#ibcon#flushed, iclass 27, count 2 2006.218.08:01:58.30#ibcon#about to write, iclass 27, count 2 2006.218.08:01:58.30#ibcon#wrote, iclass 27, count 2 2006.218.08:01:58.30#ibcon#about to read 3, iclass 27, count 2 2006.218.08:01:58.32#ibcon#read 3, iclass 27, count 2 2006.218.08:01:58.32#ibcon#about to read 4, iclass 27, count 2 2006.218.08:01:58.32#ibcon#read 4, iclass 27, count 2 2006.218.08:01:58.32#ibcon#about to read 5, iclass 27, count 2 2006.218.08:01:58.32#ibcon#read 5, iclass 27, count 2 2006.218.08:01:58.32#ibcon#about to read 6, iclass 27, count 2 2006.218.08:01:58.32#ibcon#read 6, iclass 27, count 2 2006.218.08:01:58.32#ibcon#end of sib2, iclass 27, count 2 2006.218.08:01:58.32#ibcon#*mode == 0, iclass 27, count 2 2006.218.08:01:58.32#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.218.08:01:58.32#ibcon#[25=AT02-04\r\n] 2006.218.08:01:58.32#ibcon#*before write, iclass 27, count 2 2006.218.08:01:58.32#ibcon#enter sib2, iclass 27, count 2 2006.218.08:01:58.32#ibcon#flushed, iclass 27, count 2 2006.218.08:01:58.32#ibcon#about to write, iclass 27, count 2 2006.218.08:01:58.32#ibcon#wrote, iclass 27, count 2 2006.218.08:01:58.32#ibcon#about to read 3, iclass 27, count 2 2006.218.08:01:58.35#ibcon#read 3, iclass 27, count 2 2006.218.08:01:58.35#ibcon#about to read 4, iclass 27, count 2 2006.218.08:01:58.35#ibcon#read 4, iclass 27, count 2 2006.218.08:01:58.35#ibcon#about to read 5, iclass 27, count 2 2006.218.08:01:58.35#ibcon#read 5, iclass 27, count 2 2006.218.08:01:58.35#ibcon#about to read 6, iclass 27, count 2 2006.218.08:01:58.35#ibcon#read 6, iclass 27, count 2 2006.218.08:01:58.35#ibcon#end of sib2, iclass 27, count 2 2006.218.08:01:58.35#ibcon#*after write, iclass 27, count 2 2006.218.08:01:58.35#ibcon#*before return 0, iclass 27, count 2 2006.218.08:01:58.35#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.218.08:01:58.35#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.218.08:01:58.35#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.218.08:01:58.35#ibcon#ireg 7 cls_cnt 0 2006.218.08:01:58.35#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.218.08:01:58.47#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.218.08:01:58.47#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.218.08:01:58.47#ibcon#enter wrdev, iclass 27, count 0 2006.218.08:01:58.47#ibcon#first serial, iclass 27, count 0 2006.218.08:01:58.47#ibcon#enter sib2, iclass 27, count 0 2006.218.08:01:58.47#ibcon#flushed, iclass 27, count 0 2006.218.08:01:58.47#ibcon#about to write, iclass 27, count 0 2006.218.08:01:58.47#ibcon#wrote, iclass 27, count 0 2006.218.08:01:58.47#ibcon#about to read 3, iclass 27, count 0 2006.218.08:01:58.49#ibcon#read 3, iclass 27, count 0 2006.218.08:01:58.49#ibcon#about to read 4, iclass 27, count 0 2006.218.08:01:58.49#ibcon#read 4, iclass 27, count 0 2006.218.08:01:58.49#ibcon#about to read 5, iclass 27, count 0 2006.218.08:01:58.49#ibcon#read 5, iclass 27, count 0 2006.218.08:01:58.49#ibcon#about to read 6, iclass 27, count 0 2006.218.08:01:58.49#ibcon#read 6, iclass 27, count 0 2006.218.08:01:58.49#ibcon#end of sib2, iclass 27, count 0 2006.218.08:01:58.49#ibcon#*mode == 0, iclass 27, count 0 2006.218.08:01:58.49#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.218.08:01:58.49#ibcon#[25=USB\r\n] 2006.218.08:01:58.49#ibcon#*before write, iclass 27, count 0 2006.218.08:01:58.49#ibcon#enter sib2, iclass 27, count 0 2006.218.08:01:58.49#ibcon#flushed, iclass 27, count 0 2006.218.08:01:58.49#ibcon#about to write, iclass 27, count 0 2006.218.08:01:58.49#ibcon#wrote, iclass 27, count 0 2006.218.08:01:58.49#ibcon#about to read 3, iclass 27, count 0 2006.218.08:01:58.52#ibcon#read 3, iclass 27, count 0 2006.218.08:01:58.52#ibcon#about to read 4, iclass 27, count 0 2006.218.08:01:58.52#ibcon#read 4, iclass 27, count 0 2006.218.08:01:58.52#ibcon#about to read 5, iclass 27, count 0 2006.218.08:01:58.52#ibcon#read 5, iclass 27, count 0 2006.218.08:01:58.52#ibcon#about to read 6, iclass 27, count 0 2006.218.08:01:58.52#ibcon#read 6, iclass 27, count 0 2006.218.08:01:58.52#ibcon#end of sib2, iclass 27, count 0 2006.218.08:01:58.52#ibcon#*after write, iclass 27, count 0 2006.218.08:01:58.52#ibcon#*before return 0, iclass 27, count 0 2006.218.08:01:58.52#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.218.08:01:58.52#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.218.08:01:58.52#ibcon#about to clear, iclass 27 cls_cnt 0 2006.218.08:01:58.52#ibcon#cleared, iclass 27 cls_cnt 0 2006.218.08:01:58.52$vc4f8/valo=3,672.99 2006.218.08:01:58.52#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.218.08:01:58.52#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.218.08:01:58.52#ibcon#ireg 17 cls_cnt 0 2006.218.08:01:58.52#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.218.08:01:58.52#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.218.08:01:58.52#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.218.08:01:58.52#ibcon#enter wrdev, iclass 29, count 0 2006.218.08:01:58.52#ibcon#first serial, iclass 29, count 0 2006.218.08:01:58.52#ibcon#enter sib2, iclass 29, count 0 2006.218.08:01:58.52#ibcon#flushed, iclass 29, count 0 2006.218.08:01:58.52#ibcon#about to write, iclass 29, count 0 2006.218.08:01:58.52#ibcon#wrote, iclass 29, count 0 2006.218.08:01:58.52#ibcon#about to read 3, iclass 29, count 0 2006.218.08:01:58.54#ibcon#read 3, iclass 29, count 0 2006.218.08:01:58.54#ibcon#about to read 4, iclass 29, count 0 2006.218.08:01:58.54#ibcon#read 4, iclass 29, count 0 2006.218.08:01:58.54#ibcon#about to read 5, iclass 29, count 0 2006.218.08:01:58.54#ibcon#read 5, iclass 29, count 0 2006.218.08:01:58.54#ibcon#about to read 6, iclass 29, count 0 2006.218.08:01:58.54#ibcon#read 6, iclass 29, count 0 2006.218.08:01:58.54#ibcon#end of sib2, iclass 29, count 0 2006.218.08:01:58.54#ibcon#*mode == 0, iclass 29, count 0 2006.218.08:01:58.54#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.218.08:01:58.54#ibcon#[26=FRQ=03,672.99\r\n] 2006.218.08:01:58.54#ibcon#*before write, iclass 29, count 0 2006.218.08:01:58.54#ibcon#enter sib2, iclass 29, count 0 2006.218.08:01:58.54#ibcon#flushed, iclass 29, count 0 2006.218.08:01:58.54#ibcon#about to write, iclass 29, count 0 2006.218.08:01:58.54#ibcon#wrote, iclass 29, count 0 2006.218.08:01:58.54#ibcon#about to read 3, iclass 29, count 0 2006.218.08:01:58.58#ibcon#read 3, iclass 29, count 0 2006.218.08:01:58.58#ibcon#about to read 4, iclass 29, count 0 2006.218.08:01:58.58#ibcon#read 4, iclass 29, count 0 2006.218.08:01:58.58#ibcon#about to read 5, iclass 29, count 0 2006.218.08:01:58.58#ibcon#read 5, iclass 29, count 0 2006.218.08:01:58.58#ibcon#about to read 6, iclass 29, count 0 2006.218.08:01:58.58#ibcon#read 6, iclass 29, count 0 2006.218.08:01:58.58#ibcon#end of sib2, iclass 29, count 0 2006.218.08:01:58.58#ibcon#*after write, iclass 29, count 0 2006.218.08:01:58.58#ibcon#*before return 0, iclass 29, count 0 2006.218.08:01:58.58#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.218.08:01:58.58#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.218.08:01:58.58#ibcon#about to clear, iclass 29 cls_cnt 0 2006.218.08:01:58.58#ibcon#cleared, iclass 29 cls_cnt 0 2006.218.08:01:58.58$vc4f8/va=3,4 2006.218.08:01:58.58#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.218.08:01:58.58#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.218.08:01:58.58#ibcon#ireg 11 cls_cnt 2 2006.218.08:01:58.58#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.218.08:01:58.65#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.218.08:01:58.65#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.218.08:01:58.65#ibcon#enter wrdev, iclass 31, count 2 2006.218.08:01:58.65#ibcon#first serial, iclass 31, count 2 2006.218.08:01:58.65#ibcon#enter sib2, iclass 31, count 2 2006.218.08:01:58.65#ibcon#flushed, iclass 31, count 2 2006.218.08:01:58.65#ibcon#about to write, iclass 31, count 2 2006.218.08:01:58.65#ibcon#wrote, iclass 31, count 2 2006.218.08:01:58.65#ibcon#about to read 3, iclass 31, count 2 2006.218.08:01:58.66#ibcon#read 3, iclass 31, count 2 2006.218.08:01:58.66#ibcon#about to read 4, iclass 31, count 2 2006.218.08:01:58.66#ibcon#read 4, iclass 31, count 2 2006.218.08:01:58.66#ibcon#about to read 5, iclass 31, count 2 2006.218.08:01:58.66#ibcon#read 5, iclass 31, count 2 2006.218.08:01:58.66#ibcon#about to read 6, iclass 31, count 2 2006.218.08:01:58.66#ibcon#read 6, iclass 31, count 2 2006.218.08:01:58.66#ibcon#end of sib2, iclass 31, count 2 2006.218.08:01:58.66#ibcon#*mode == 0, iclass 31, count 2 2006.218.08:01:58.66#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.218.08:01:58.66#ibcon#[25=AT03-04\r\n] 2006.218.08:01:58.66#ibcon#*before write, iclass 31, count 2 2006.218.08:01:58.66#ibcon#enter sib2, iclass 31, count 2 2006.218.08:01:58.66#ibcon#flushed, iclass 31, count 2 2006.218.08:01:58.66#ibcon#about to write, iclass 31, count 2 2006.218.08:01:58.66#ibcon#wrote, iclass 31, count 2 2006.218.08:01:58.66#ibcon#about to read 3, iclass 31, count 2 2006.218.08:01:58.69#ibcon#read 3, iclass 31, count 2 2006.218.08:01:58.69#ibcon#about to read 4, iclass 31, count 2 2006.218.08:01:58.69#ibcon#read 4, iclass 31, count 2 2006.218.08:01:58.69#ibcon#about to read 5, iclass 31, count 2 2006.218.08:01:58.69#ibcon#read 5, iclass 31, count 2 2006.218.08:01:58.69#ibcon#about to read 6, iclass 31, count 2 2006.218.08:01:58.69#ibcon#read 6, iclass 31, count 2 2006.218.08:01:58.69#ibcon#end of sib2, iclass 31, count 2 2006.218.08:01:58.69#ibcon#*after write, iclass 31, count 2 2006.218.08:01:58.69#ibcon#*before return 0, iclass 31, count 2 2006.218.08:01:58.69#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.218.08:01:58.69#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.218.08:01:58.69#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.218.08:01:58.69#ibcon#ireg 7 cls_cnt 0 2006.218.08:01:58.69#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.218.08:01:58.81#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.218.08:01:58.81#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.218.08:01:58.81#ibcon#enter wrdev, iclass 31, count 0 2006.218.08:01:58.81#ibcon#first serial, iclass 31, count 0 2006.218.08:01:58.81#ibcon#enter sib2, iclass 31, count 0 2006.218.08:01:58.81#ibcon#flushed, iclass 31, count 0 2006.218.08:01:58.81#ibcon#about to write, iclass 31, count 0 2006.218.08:01:58.81#ibcon#wrote, iclass 31, count 0 2006.218.08:01:58.81#ibcon#about to read 3, iclass 31, count 0 2006.218.08:01:58.83#ibcon#read 3, iclass 31, count 0 2006.218.08:01:58.83#ibcon#about to read 4, iclass 31, count 0 2006.218.08:01:58.83#ibcon#read 4, iclass 31, count 0 2006.218.08:01:58.83#ibcon#about to read 5, iclass 31, count 0 2006.218.08:01:58.83#ibcon#read 5, iclass 31, count 0 2006.218.08:01:58.83#ibcon#about to read 6, iclass 31, count 0 2006.218.08:01:58.83#ibcon#read 6, iclass 31, count 0 2006.218.08:01:58.83#ibcon#end of sib2, iclass 31, count 0 2006.218.08:01:58.83#ibcon#*mode == 0, iclass 31, count 0 2006.218.08:01:58.83#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.218.08:01:58.83#ibcon#[25=USB\r\n] 2006.218.08:01:58.83#ibcon#*before write, iclass 31, count 0 2006.218.08:01:58.83#ibcon#enter sib2, iclass 31, count 0 2006.218.08:01:58.83#ibcon#flushed, iclass 31, count 0 2006.218.08:01:58.83#ibcon#about to write, iclass 31, count 0 2006.218.08:01:58.83#ibcon#wrote, iclass 31, count 0 2006.218.08:01:58.83#ibcon#about to read 3, iclass 31, count 0 2006.218.08:01:58.86#ibcon#read 3, iclass 31, count 0 2006.218.08:01:58.86#ibcon#about to read 4, iclass 31, count 0 2006.218.08:01:58.86#ibcon#read 4, iclass 31, count 0 2006.218.08:01:58.86#ibcon#about to read 5, iclass 31, count 0 2006.218.08:01:58.86#ibcon#read 5, iclass 31, count 0 2006.218.08:01:58.86#ibcon#about to read 6, iclass 31, count 0 2006.218.08:01:58.86#ibcon#read 6, iclass 31, count 0 2006.218.08:01:58.86#ibcon#end of sib2, iclass 31, count 0 2006.218.08:01:58.86#ibcon#*after write, iclass 31, count 0 2006.218.08:01:58.86#ibcon#*before return 0, iclass 31, count 0 2006.218.08:01:58.86#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.218.08:01:58.86#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.218.08:01:58.86#ibcon#about to clear, iclass 31 cls_cnt 0 2006.218.08:01:58.86#ibcon#cleared, iclass 31 cls_cnt 0 2006.218.08:01:58.86$vc4f8/valo=4,832.99 2006.218.08:01:58.86#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.218.08:01:58.86#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.218.08:01:58.86#ibcon#ireg 17 cls_cnt 0 2006.218.08:01:58.86#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.218.08:01:58.86#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.218.08:01:58.86#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.218.08:01:58.86#ibcon#enter wrdev, iclass 33, count 0 2006.218.08:01:58.86#ibcon#first serial, iclass 33, count 0 2006.218.08:01:58.86#ibcon#enter sib2, iclass 33, count 0 2006.218.08:01:58.86#ibcon#flushed, iclass 33, count 0 2006.218.08:01:58.86#ibcon#about to write, iclass 33, count 0 2006.218.08:01:58.86#ibcon#wrote, iclass 33, count 0 2006.218.08:01:58.86#ibcon#about to read 3, iclass 33, count 0 2006.218.08:01:58.88#ibcon#read 3, iclass 33, count 0 2006.218.08:01:58.88#ibcon#about to read 4, iclass 33, count 0 2006.218.08:01:58.88#ibcon#read 4, iclass 33, count 0 2006.218.08:01:58.88#ibcon#about to read 5, iclass 33, count 0 2006.218.08:01:58.88#ibcon#read 5, iclass 33, count 0 2006.218.08:01:58.88#ibcon#about to read 6, iclass 33, count 0 2006.218.08:01:58.88#ibcon#read 6, iclass 33, count 0 2006.218.08:01:58.88#ibcon#end of sib2, iclass 33, count 0 2006.218.08:01:58.88#ibcon#*mode == 0, iclass 33, count 0 2006.218.08:01:58.88#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.218.08:01:58.88#ibcon#[26=FRQ=04,832.99\r\n] 2006.218.08:01:58.88#ibcon#*before write, iclass 33, count 0 2006.218.08:01:58.88#ibcon#enter sib2, iclass 33, count 0 2006.218.08:01:58.88#ibcon#flushed, iclass 33, count 0 2006.218.08:01:58.88#ibcon#about to write, iclass 33, count 0 2006.218.08:01:58.88#ibcon#wrote, iclass 33, count 0 2006.218.08:01:58.88#ibcon#about to read 3, iclass 33, count 0 2006.218.08:01:58.92#ibcon#read 3, iclass 33, count 0 2006.218.08:01:58.92#ibcon#about to read 4, iclass 33, count 0 2006.218.08:01:58.92#ibcon#read 4, iclass 33, count 0 2006.218.08:01:58.92#ibcon#about to read 5, iclass 33, count 0 2006.218.08:01:58.92#ibcon#read 5, iclass 33, count 0 2006.218.08:01:58.92#ibcon#about to read 6, iclass 33, count 0 2006.218.08:01:58.92#ibcon#read 6, iclass 33, count 0 2006.218.08:01:58.92#ibcon#end of sib2, iclass 33, count 0 2006.218.08:01:58.92#ibcon#*after write, iclass 33, count 0 2006.218.08:01:58.92#ibcon#*before return 0, iclass 33, count 0 2006.218.08:01:58.92#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.218.08:01:58.92#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.218.08:01:58.92#ibcon#about to clear, iclass 33 cls_cnt 0 2006.218.08:01:58.92#ibcon#cleared, iclass 33 cls_cnt 0 2006.218.08:01:58.92$vc4f8/va=4,4 2006.218.08:01:58.92#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.218.08:01:58.92#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.218.08:01:58.92#ibcon#ireg 11 cls_cnt 2 2006.218.08:01:58.92#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.218.08:01:58.98#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.218.08:01:58.98#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.218.08:01:58.98#ibcon#enter wrdev, iclass 35, count 2 2006.218.08:01:58.98#ibcon#first serial, iclass 35, count 2 2006.218.08:01:58.98#ibcon#enter sib2, iclass 35, count 2 2006.218.08:01:58.98#ibcon#flushed, iclass 35, count 2 2006.218.08:01:58.98#ibcon#about to write, iclass 35, count 2 2006.218.08:01:58.98#ibcon#wrote, iclass 35, count 2 2006.218.08:01:58.98#ibcon#about to read 3, iclass 35, count 2 2006.218.08:01:59.00#ibcon#read 3, iclass 35, count 2 2006.218.08:01:59.00#ibcon#about to read 4, iclass 35, count 2 2006.218.08:01:59.00#ibcon#read 4, iclass 35, count 2 2006.218.08:01:59.00#ibcon#about to read 5, iclass 35, count 2 2006.218.08:01:59.00#ibcon#read 5, iclass 35, count 2 2006.218.08:01:59.00#ibcon#about to read 6, iclass 35, count 2 2006.218.08:01:59.00#ibcon#read 6, iclass 35, count 2 2006.218.08:01:59.00#ibcon#end of sib2, iclass 35, count 2 2006.218.08:01:59.00#ibcon#*mode == 0, iclass 35, count 2 2006.218.08:01:59.00#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.218.08:01:59.00#ibcon#[25=AT04-04\r\n] 2006.218.08:01:59.00#ibcon#*before write, iclass 35, count 2 2006.218.08:01:59.00#ibcon#enter sib2, iclass 35, count 2 2006.218.08:01:59.00#ibcon#flushed, iclass 35, count 2 2006.218.08:01:59.00#ibcon#about to write, iclass 35, count 2 2006.218.08:01:59.00#ibcon#wrote, iclass 35, count 2 2006.218.08:01:59.00#ibcon#about to read 3, iclass 35, count 2 2006.218.08:01:59.03#ibcon#read 3, iclass 35, count 2 2006.218.08:01:59.03#ibcon#about to read 4, iclass 35, count 2 2006.218.08:01:59.03#ibcon#read 4, iclass 35, count 2 2006.218.08:01:59.03#ibcon#about to read 5, iclass 35, count 2 2006.218.08:01:59.03#ibcon#read 5, iclass 35, count 2 2006.218.08:01:59.03#ibcon#about to read 6, iclass 35, count 2 2006.218.08:01:59.03#ibcon#read 6, iclass 35, count 2 2006.218.08:01:59.03#ibcon#end of sib2, iclass 35, count 2 2006.218.08:01:59.03#ibcon#*after write, iclass 35, count 2 2006.218.08:01:59.03#ibcon#*before return 0, iclass 35, count 2 2006.218.08:01:59.03#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.218.08:01:59.03#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.218.08:01:59.03#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.218.08:01:59.03#ibcon#ireg 7 cls_cnt 0 2006.218.08:01:59.03#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.218.08:01:59.15#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.218.08:01:59.15#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.218.08:01:59.15#ibcon#enter wrdev, iclass 35, count 0 2006.218.08:01:59.15#ibcon#first serial, iclass 35, count 0 2006.218.08:01:59.15#ibcon#enter sib2, iclass 35, count 0 2006.218.08:01:59.15#ibcon#flushed, iclass 35, count 0 2006.218.08:01:59.15#ibcon#about to write, iclass 35, count 0 2006.218.08:01:59.15#ibcon#wrote, iclass 35, count 0 2006.218.08:01:59.15#ibcon#about to read 3, iclass 35, count 0 2006.218.08:01:59.17#ibcon#read 3, iclass 35, count 0 2006.218.08:01:59.17#ibcon#about to read 4, iclass 35, count 0 2006.218.08:01:59.17#ibcon#read 4, iclass 35, count 0 2006.218.08:01:59.17#ibcon#about to read 5, iclass 35, count 0 2006.218.08:01:59.17#ibcon#read 5, iclass 35, count 0 2006.218.08:01:59.17#ibcon#about to read 6, iclass 35, count 0 2006.218.08:01:59.17#ibcon#read 6, iclass 35, count 0 2006.218.08:01:59.17#ibcon#end of sib2, iclass 35, count 0 2006.218.08:01:59.17#ibcon#*mode == 0, iclass 35, count 0 2006.218.08:01:59.17#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.218.08:01:59.17#ibcon#[25=USB\r\n] 2006.218.08:01:59.17#ibcon#*before write, iclass 35, count 0 2006.218.08:01:59.17#ibcon#enter sib2, iclass 35, count 0 2006.218.08:01:59.17#ibcon#flushed, iclass 35, count 0 2006.218.08:01:59.17#ibcon#about to write, iclass 35, count 0 2006.218.08:01:59.17#ibcon#wrote, iclass 35, count 0 2006.218.08:01:59.17#ibcon#about to read 3, iclass 35, count 0 2006.218.08:01:59.20#ibcon#read 3, iclass 35, count 0 2006.218.08:01:59.20#ibcon#about to read 4, iclass 35, count 0 2006.218.08:01:59.20#ibcon#read 4, iclass 35, count 0 2006.218.08:01:59.20#ibcon#about to read 5, iclass 35, count 0 2006.218.08:01:59.20#ibcon#read 5, iclass 35, count 0 2006.218.08:01:59.20#ibcon#about to read 6, iclass 35, count 0 2006.218.08:01:59.20#ibcon#read 6, iclass 35, count 0 2006.218.08:01:59.20#ibcon#end of sib2, iclass 35, count 0 2006.218.08:01:59.20#ibcon#*after write, iclass 35, count 0 2006.218.08:01:59.20#ibcon#*before return 0, iclass 35, count 0 2006.218.08:01:59.20#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.218.08:01:59.20#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.218.08:01:59.20#ibcon#about to clear, iclass 35 cls_cnt 0 2006.218.08:01:59.20#ibcon#cleared, iclass 35 cls_cnt 0 2006.218.08:01:59.20$vc4f8/valo=5,652.99 2006.218.08:01:59.20#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.218.08:01:59.20#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.218.08:01:59.20#ibcon#ireg 17 cls_cnt 0 2006.218.08:01:59.20#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.218.08:01:59.20#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.218.08:01:59.20#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.218.08:01:59.20#ibcon#enter wrdev, iclass 37, count 0 2006.218.08:01:59.20#ibcon#first serial, iclass 37, count 0 2006.218.08:01:59.20#ibcon#enter sib2, iclass 37, count 0 2006.218.08:01:59.20#ibcon#flushed, iclass 37, count 0 2006.218.08:01:59.20#ibcon#about to write, iclass 37, count 0 2006.218.08:01:59.20#ibcon#wrote, iclass 37, count 0 2006.218.08:01:59.20#ibcon#about to read 3, iclass 37, count 0 2006.218.08:01:59.22#ibcon#read 3, iclass 37, count 0 2006.218.08:01:59.22#ibcon#about to read 4, iclass 37, count 0 2006.218.08:01:59.22#ibcon#read 4, iclass 37, count 0 2006.218.08:01:59.22#ibcon#about to read 5, iclass 37, count 0 2006.218.08:01:59.22#ibcon#read 5, iclass 37, count 0 2006.218.08:01:59.22#ibcon#about to read 6, iclass 37, count 0 2006.218.08:01:59.22#ibcon#read 6, iclass 37, count 0 2006.218.08:01:59.22#ibcon#end of sib2, iclass 37, count 0 2006.218.08:01:59.22#ibcon#*mode == 0, iclass 37, count 0 2006.218.08:01:59.22#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.218.08:01:59.22#ibcon#[26=FRQ=05,652.99\r\n] 2006.218.08:01:59.22#ibcon#*before write, iclass 37, count 0 2006.218.08:01:59.22#ibcon#enter sib2, iclass 37, count 0 2006.218.08:01:59.22#ibcon#flushed, iclass 37, count 0 2006.218.08:01:59.22#ibcon#about to write, iclass 37, count 0 2006.218.08:01:59.22#ibcon#wrote, iclass 37, count 0 2006.218.08:01:59.22#ibcon#about to read 3, iclass 37, count 0 2006.218.08:01:59.26#ibcon#read 3, iclass 37, count 0 2006.218.08:01:59.26#ibcon#about to read 4, iclass 37, count 0 2006.218.08:01:59.26#ibcon#read 4, iclass 37, count 0 2006.218.08:01:59.26#ibcon#about to read 5, iclass 37, count 0 2006.218.08:01:59.26#ibcon#read 5, iclass 37, count 0 2006.218.08:01:59.26#ibcon#about to read 6, iclass 37, count 0 2006.218.08:01:59.26#ibcon#read 6, iclass 37, count 0 2006.218.08:01:59.26#ibcon#end of sib2, iclass 37, count 0 2006.218.08:01:59.26#ibcon#*after write, iclass 37, count 0 2006.218.08:01:59.26#ibcon#*before return 0, iclass 37, count 0 2006.218.08:01:59.26#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.218.08:01:59.26#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.218.08:01:59.26#ibcon#about to clear, iclass 37 cls_cnt 0 2006.218.08:01:59.26#ibcon#cleared, iclass 37 cls_cnt 0 2006.218.08:01:59.26$vc4f8/va=5,7 2006.218.08:01:59.26#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.218.08:01:59.26#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.218.08:01:59.26#ibcon#ireg 11 cls_cnt 2 2006.218.08:01:59.26#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.218.08:01:59.32#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.218.08:01:59.32#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.218.08:01:59.32#ibcon#enter wrdev, iclass 39, count 2 2006.218.08:01:59.32#ibcon#first serial, iclass 39, count 2 2006.218.08:01:59.32#ibcon#enter sib2, iclass 39, count 2 2006.218.08:01:59.32#ibcon#flushed, iclass 39, count 2 2006.218.08:01:59.32#ibcon#about to write, iclass 39, count 2 2006.218.08:01:59.32#ibcon#wrote, iclass 39, count 2 2006.218.08:01:59.32#ibcon#about to read 3, iclass 39, count 2 2006.218.08:01:59.34#ibcon#read 3, iclass 39, count 2 2006.218.08:01:59.34#ibcon#about to read 4, iclass 39, count 2 2006.218.08:01:59.34#ibcon#read 4, iclass 39, count 2 2006.218.08:01:59.34#ibcon#about to read 5, iclass 39, count 2 2006.218.08:01:59.34#ibcon#read 5, iclass 39, count 2 2006.218.08:01:59.34#ibcon#about to read 6, iclass 39, count 2 2006.218.08:01:59.34#ibcon#read 6, iclass 39, count 2 2006.218.08:01:59.34#ibcon#end of sib2, iclass 39, count 2 2006.218.08:01:59.34#ibcon#*mode == 0, iclass 39, count 2 2006.218.08:01:59.34#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.218.08:01:59.34#ibcon#[25=AT05-07\r\n] 2006.218.08:01:59.34#ibcon#*before write, iclass 39, count 2 2006.218.08:01:59.34#ibcon#enter sib2, iclass 39, count 2 2006.218.08:01:59.34#ibcon#flushed, iclass 39, count 2 2006.218.08:01:59.34#ibcon#about to write, iclass 39, count 2 2006.218.08:01:59.34#ibcon#wrote, iclass 39, count 2 2006.218.08:01:59.34#ibcon#about to read 3, iclass 39, count 2 2006.218.08:01:59.37#ibcon#read 3, iclass 39, count 2 2006.218.08:01:59.37#ibcon#about to read 4, iclass 39, count 2 2006.218.08:01:59.37#ibcon#read 4, iclass 39, count 2 2006.218.08:01:59.37#ibcon#about to read 5, iclass 39, count 2 2006.218.08:01:59.37#ibcon#read 5, iclass 39, count 2 2006.218.08:01:59.37#ibcon#about to read 6, iclass 39, count 2 2006.218.08:01:59.37#ibcon#read 6, iclass 39, count 2 2006.218.08:01:59.37#ibcon#end of sib2, iclass 39, count 2 2006.218.08:01:59.37#ibcon#*after write, iclass 39, count 2 2006.218.08:01:59.37#ibcon#*before return 0, iclass 39, count 2 2006.218.08:01:59.37#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.218.08:01:59.37#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.218.08:01:59.37#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.218.08:01:59.37#ibcon#ireg 7 cls_cnt 0 2006.218.08:01:59.37#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.218.08:01:59.49#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.218.08:01:59.49#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.218.08:01:59.49#ibcon#enter wrdev, iclass 39, count 0 2006.218.08:01:59.49#ibcon#first serial, iclass 39, count 0 2006.218.08:01:59.49#ibcon#enter sib2, iclass 39, count 0 2006.218.08:01:59.49#ibcon#flushed, iclass 39, count 0 2006.218.08:01:59.49#ibcon#about to write, iclass 39, count 0 2006.218.08:01:59.49#ibcon#wrote, iclass 39, count 0 2006.218.08:01:59.49#ibcon#about to read 3, iclass 39, count 0 2006.218.08:01:59.51#ibcon#read 3, iclass 39, count 0 2006.218.08:01:59.51#ibcon#about to read 4, iclass 39, count 0 2006.218.08:01:59.51#ibcon#read 4, iclass 39, count 0 2006.218.08:01:59.51#ibcon#about to read 5, iclass 39, count 0 2006.218.08:01:59.51#ibcon#read 5, iclass 39, count 0 2006.218.08:01:59.51#ibcon#about to read 6, iclass 39, count 0 2006.218.08:01:59.51#ibcon#read 6, iclass 39, count 0 2006.218.08:01:59.51#ibcon#end of sib2, iclass 39, count 0 2006.218.08:01:59.51#ibcon#*mode == 0, iclass 39, count 0 2006.218.08:01:59.51#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.218.08:01:59.51#ibcon#[25=USB\r\n] 2006.218.08:01:59.51#ibcon#*before write, iclass 39, count 0 2006.218.08:01:59.51#ibcon#enter sib2, iclass 39, count 0 2006.218.08:01:59.51#ibcon#flushed, iclass 39, count 0 2006.218.08:01:59.51#ibcon#about to write, iclass 39, count 0 2006.218.08:01:59.51#ibcon#wrote, iclass 39, count 0 2006.218.08:01:59.51#ibcon#about to read 3, iclass 39, count 0 2006.218.08:01:59.54#ibcon#read 3, iclass 39, count 0 2006.218.08:01:59.54#ibcon#about to read 4, iclass 39, count 0 2006.218.08:01:59.54#ibcon#read 4, iclass 39, count 0 2006.218.08:01:59.54#ibcon#about to read 5, iclass 39, count 0 2006.218.08:01:59.54#ibcon#read 5, iclass 39, count 0 2006.218.08:01:59.54#ibcon#about to read 6, iclass 39, count 0 2006.218.08:01:59.54#ibcon#read 6, iclass 39, count 0 2006.218.08:01:59.54#ibcon#end of sib2, iclass 39, count 0 2006.218.08:01:59.54#ibcon#*after write, iclass 39, count 0 2006.218.08:01:59.54#ibcon#*before return 0, iclass 39, count 0 2006.218.08:01:59.54#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.218.08:01:59.54#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.218.08:01:59.54#ibcon#about to clear, iclass 39 cls_cnt 0 2006.218.08:01:59.54#ibcon#cleared, iclass 39 cls_cnt 0 2006.218.08:01:59.54$vc4f8/valo=6,772.99 2006.218.08:01:59.54#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.218.08:01:59.54#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.218.08:01:59.54#ibcon#ireg 17 cls_cnt 0 2006.218.08:01:59.54#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.218.08:01:59.54#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.218.08:01:59.54#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.218.08:01:59.54#ibcon#enter wrdev, iclass 3, count 0 2006.218.08:01:59.54#ibcon#first serial, iclass 3, count 0 2006.218.08:01:59.54#ibcon#enter sib2, iclass 3, count 0 2006.218.08:01:59.54#ibcon#flushed, iclass 3, count 0 2006.218.08:01:59.54#ibcon#about to write, iclass 3, count 0 2006.218.08:01:59.54#ibcon#wrote, iclass 3, count 0 2006.218.08:01:59.54#ibcon#about to read 3, iclass 3, count 0 2006.218.08:01:59.56#ibcon#read 3, iclass 3, count 0 2006.218.08:01:59.56#ibcon#about to read 4, iclass 3, count 0 2006.218.08:01:59.56#ibcon#read 4, iclass 3, count 0 2006.218.08:01:59.56#ibcon#about to read 5, iclass 3, count 0 2006.218.08:01:59.56#ibcon#read 5, iclass 3, count 0 2006.218.08:01:59.56#ibcon#about to read 6, iclass 3, count 0 2006.218.08:01:59.56#ibcon#read 6, iclass 3, count 0 2006.218.08:01:59.56#ibcon#end of sib2, iclass 3, count 0 2006.218.08:01:59.56#ibcon#*mode == 0, iclass 3, count 0 2006.218.08:01:59.56#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.218.08:01:59.56#ibcon#[26=FRQ=06,772.99\r\n] 2006.218.08:01:59.56#ibcon#*before write, iclass 3, count 0 2006.218.08:01:59.56#ibcon#enter sib2, iclass 3, count 0 2006.218.08:01:59.56#ibcon#flushed, iclass 3, count 0 2006.218.08:01:59.56#ibcon#about to write, iclass 3, count 0 2006.218.08:01:59.56#ibcon#wrote, iclass 3, count 0 2006.218.08:01:59.56#ibcon#about to read 3, iclass 3, count 0 2006.218.08:01:59.60#ibcon#read 3, iclass 3, count 0 2006.218.08:01:59.60#ibcon#about to read 4, iclass 3, count 0 2006.218.08:01:59.60#ibcon#read 4, iclass 3, count 0 2006.218.08:01:59.60#ibcon#about to read 5, iclass 3, count 0 2006.218.08:01:59.60#ibcon#read 5, iclass 3, count 0 2006.218.08:01:59.60#ibcon#about to read 6, iclass 3, count 0 2006.218.08:01:59.60#ibcon#read 6, iclass 3, count 0 2006.218.08:01:59.60#ibcon#end of sib2, iclass 3, count 0 2006.218.08:01:59.60#ibcon#*after write, iclass 3, count 0 2006.218.08:01:59.60#ibcon#*before return 0, iclass 3, count 0 2006.218.08:01:59.60#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.218.08:01:59.60#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.218.08:01:59.60#ibcon#about to clear, iclass 3 cls_cnt 0 2006.218.08:01:59.60#ibcon#cleared, iclass 3 cls_cnt 0 2006.218.08:01:59.60$vc4f8/va=6,6 2006.218.08:01:59.60#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.218.08:01:59.60#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.218.08:01:59.60#ibcon#ireg 11 cls_cnt 2 2006.218.08:01:59.60#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.218.08:01:59.67#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.218.08:01:59.67#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.218.08:01:59.67#ibcon#enter wrdev, iclass 5, count 2 2006.218.08:01:59.67#ibcon#first serial, iclass 5, count 2 2006.218.08:01:59.67#ibcon#enter sib2, iclass 5, count 2 2006.218.08:01:59.67#ibcon#flushed, iclass 5, count 2 2006.218.08:01:59.67#ibcon#about to write, iclass 5, count 2 2006.218.08:01:59.67#ibcon#wrote, iclass 5, count 2 2006.218.08:01:59.67#ibcon#about to read 3, iclass 5, count 2 2006.218.08:01:59.68#ibcon#read 3, iclass 5, count 2 2006.218.08:01:59.68#ibcon#about to read 4, iclass 5, count 2 2006.218.08:01:59.68#ibcon#read 4, iclass 5, count 2 2006.218.08:01:59.68#ibcon#about to read 5, iclass 5, count 2 2006.218.08:01:59.68#ibcon#read 5, iclass 5, count 2 2006.218.08:01:59.68#ibcon#about to read 6, iclass 5, count 2 2006.218.08:01:59.68#ibcon#read 6, iclass 5, count 2 2006.218.08:01:59.68#ibcon#end of sib2, iclass 5, count 2 2006.218.08:01:59.68#ibcon#*mode == 0, iclass 5, count 2 2006.218.08:01:59.68#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.218.08:01:59.68#ibcon#[25=AT06-06\r\n] 2006.218.08:01:59.68#ibcon#*before write, iclass 5, count 2 2006.218.08:01:59.68#ibcon#enter sib2, iclass 5, count 2 2006.218.08:01:59.68#ibcon#flushed, iclass 5, count 2 2006.218.08:01:59.68#ibcon#about to write, iclass 5, count 2 2006.218.08:01:59.68#ibcon#wrote, iclass 5, count 2 2006.218.08:01:59.68#ibcon#about to read 3, iclass 5, count 2 2006.218.08:01:59.71#ibcon#read 3, iclass 5, count 2 2006.218.08:01:59.71#ibcon#about to read 4, iclass 5, count 2 2006.218.08:01:59.71#ibcon#read 4, iclass 5, count 2 2006.218.08:01:59.71#ibcon#about to read 5, iclass 5, count 2 2006.218.08:01:59.71#ibcon#read 5, iclass 5, count 2 2006.218.08:01:59.71#ibcon#about to read 6, iclass 5, count 2 2006.218.08:01:59.71#ibcon#read 6, iclass 5, count 2 2006.218.08:01:59.71#ibcon#end of sib2, iclass 5, count 2 2006.218.08:01:59.71#ibcon#*after write, iclass 5, count 2 2006.218.08:01:59.71#ibcon#*before return 0, iclass 5, count 2 2006.218.08:01:59.71#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.218.08:01:59.71#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.218.08:01:59.71#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.218.08:01:59.71#ibcon#ireg 7 cls_cnt 0 2006.218.08:01:59.71#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.218.08:01:59.83#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.218.08:01:59.83#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.218.08:01:59.83#ibcon#enter wrdev, iclass 5, count 0 2006.218.08:01:59.83#ibcon#first serial, iclass 5, count 0 2006.218.08:01:59.83#ibcon#enter sib2, iclass 5, count 0 2006.218.08:01:59.83#ibcon#flushed, iclass 5, count 0 2006.218.08:01:59.83#ibcon#about to write, iclass 5, count 0 2006.218.08:01:59.83#ibcon#wrote, iclass 5, count 0 2006.218.08:01:59.83#ibcon#about to read 3, iclass 5, count 0 2006.218.08:01:59.85#ibcon#read 3, iclass 5, count 0 2006.218.08:01:59.85#ibcon#about to read 4, iclass 5, count 0 2006.218.08:01:59.85#ibcon#read 4, iclass 5, count 0 2006.218.08:01:59.85#ibcon#about to read 5, iclass 5, count 0 2006.218.08:01:59.85#ibcon#read 5, iclass 5, count 0 2006.218.08:01:59.85#ibcon#about to read 6, iclass 5, count 0 2006.218.08:01:59.85#ibcon#read 6, iclass 5, count 0 2006.218.08:01:59.85#ibcon#end of sib2, iclass 5, count 0 2006.218.08:01:59.85#ibcon#*mode == 0, iclass 5, count 0 2006.218.08:01:59.85#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.218.08:01:59.85#ibcon#[25=USB\r\n] 2006.218.08:01:59.85#ibcon#*before write, iclass 5, count 0 2006.218.08:01:59.85#ibcon#enter sib2, iclass 5, count 0 2006.218.08:01:59.85#ibcon#flushed, iclass 5, count 0 2006.218.08:01:59.85#ibcon#about to write, iclass 5, count 0 2006.218.08:01:59.85#ibcon#wrote, iclass 5, count 0 2006.218.08:01:59.85#ibcon#about to read 3, iclass 5, count 0 2006.218.08:01:59.88#ibcon#read 3, iclass 5, count 0 2006.218.08:01:59.88#ibcon#about to read 4, iclass 5, count 0 2006.218.08:01:59.88#ibcon#read 4, iclass 5, count 0 2006.218.08:01:59.88#ibcon#about to read 5, iclass 5, count 0 2006.218.08:01:59.88#ibcon#read 5, iclass 5, count 0 2006.218.08:01:59.88#ibcon#about to read 6, iclass 5, count 0 2006.218.08:01:59.88#ibcon#read 6, iclass 5, count 0 2006.218.08:01:59.88#ibcon#end of sib2, iclass 5, count 0 2006.218.08:01:59.88#ibcon#*after write, iclass 5, count 0 2006.218.08:01:59.88#ibcon#*before return 0, iclass 5, count 0 2006.218.08:01:59.88#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.218.08:01:59.88#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.218.08:01:59.88#ibcon#about to clear, iclass 5 cls_cnt 0 2006.218.08:01:59.88#ibcon#cleared, iclass 5 cls_cnt 0 2006.218.08:01:59.88$vc4f8/valo=7,832.99 2006.218.08:01:59.88#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.218.08:01:59.88#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.218.08:01:59.88#ibcon#ireg 17 cls_cnt 0 2006.218.08:01:59.88#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.218.08:01:59.88#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.218.08:01:59.88#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.218.08:01:59.88#ibcon#enter wrdev, iclass 7, count 0 2006.218.08:01:59.88#ibcon#first serial, iclass 7, count 0 2006.218.08:01:59.88#ibcon#enter sib2, iclass 7, count 0 2006.218.08:01:59.88#ibcon#flushed, iclass 7, count 0 2006.218.08:01:59.88#ibcon#about to write, iclass 7, count 0 2006.218.08:01:59.88#ibcon#wrote, iclass 7, count 0 2006.218.08:01:59.88#ibcon#about to read 3, iclass 7, count 0 2006.218.08:01:59.90#ibcon#read 3, iclass 7, count 0 2006.218.08:01:59.90#ibcon#about to read 4, iclass 7, count 0 2006.218.08:01:59.90#ibcon#read 4, iclass 7, count 0 2006.218.08:01:59.90#ibcon#about to read 5, iclass 7, count 0 2006.218.08:01:59.90#ibcon#read 5, iclass 7, count 0 2006.218.08:01:59.90#ibcon#about to read 6, iclass 7, count 0 2006.218.08:01:59.90#ibcon#read 6, iclass 7, count 0 2006.218.08:01:59.90#ibcon#end of sib2, iclass 7, count 0 2006.218.08:01:59.90#ibcon#*mode == 0, iclass 7, count 0 2006.218.08:01:59.90#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.218.08:01:59.90#ibcon#[26=FRQ=07,832.99\r\n] 2006.218.08:01:59.90#ibcon#*before write, iclass 7, count 0 2006.218.08:01:59.90#ibcon#enter sib2, iclass 7, count 0 2006.218.08:01:59.90#ibcon#flushed, iclass 7, count 0 2006.218.08:01:59.90#ibcon#about to write, iclass 7, count 0 2006.218.08:01:59.90#ibcon#wrote, iclass 7, count 0 2006.218.08:01:59.90#ibcon#about to read 3, iclass 7, count 0 2006.218.08:01:59.94#ibcon#read 3, iclass 7, count 0 2006.218.08:01:59.94#ibcon#about to read 4, iclass 7, count 0 2006.218.08:01:59.94#ibcon#read 4, iclass 7, count 0 2006.218.08:01:59.94#ibcon#about to read 5, iclass 7, count 0 2006.218.08:01:59.94#ibcon#read 5, iclass 7, count 0 2006.218.08:01:59.94#ibcon#about to read 6, iclass 7, count 0 2006.218.08:01:59.94#ibcon#read 6, iclass 7, count 0 2006.218.08:01:59.94#ibcon#end of sib2, iclass 7, count 0 2006.218.08:01:59.94#ibcon#*after write, iclass 7, count 0 2006.218.08:01:59.94#ibcon#*before return 0, iclass 7, count 0 2006.218.08:01:59.94#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.218.08:01:59.94#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.218.08:01:59.94#ibcon#about to clear, iclass 7 cls_cnt 0 2006.218.08:01:59.94#ibcon#cleared, iclass 7 cls_cnt 0 2006.218.08:01:59.94$vc4f8/va=7,6 2006.218.08:01:59.94#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.218.08:01:59.94#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.218.08:01:59.94#ibcon#ireg 11 cls_cnt 2 2006.218.08:01:59.94#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.218.08:02:00.00#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.218.08:02:00.00#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.218.08:02:00.00#ibcon#enter wrdev, iclass 11, count 2 2006.218.08:02:00.00#ibcon#first serial, iclass 11, count 2 2006.218.08:02:00.00#ibcon#enter sib2, iclass 11, count 2 2006.218.08:02:00.00#ibcon#flushed, iclass 11, count 2 2006.218.08:02:00.00#ibcon#about to write, iclass 11, count 2 2006.218.08:02:00.00#ibcon#wrote, iclass 11, count 2 2006.218.08:02:00.00#ibcon#about to read 3, iclass 11, count 2 2006.218.08:02:00.02#ibcon#read 3, iclass 11, count 2 2006.218.08:02:00.02#ibcon#about to read 4, iclass 11, count 2 2006.218.08:02:00.02#ibcon#read 4, iclass 11, count 2 2006.218.08:02:00.02#ibcon#about to read 5, iclass 11, count 2 2006.218.08:02:00.02#ibcon#read 5, iclass 11, count 2 2006.218.08:02:00.02#ibcon#about to read 6, iclass 11, count 2 2006.218.08:02:00.02#ibcon#read 6, iclass 11, count 2 2006.218.08:02:00.02#ibcon#end of sib2, iclass 11, count 2 2006.218.08:02:00.02#ibcon#*mode == 0, iclass 11, count 2 2006.218.08:02:00.02#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.218.08:02:00.02#ibcon#[25=AT07-06\r\n] 2006.218.08:02:00.02#ibcon#*before write, iclass 11, count 2 2006.218.08:02:00.02#ibcon#enter sib2, iclass 11, count 2 2006.218.08:02:00.02#ibcon#flushed, iclass 11, count 2 2006.218.08:02:00.02#ibcon#about to write, iclass 11, count 2 2006.218.08:02:00.02#ibcon#wrote, iclass 11, count 2 2006.218.08:02:00.02#ibcon#about to read 3, iclass 11, count 2 2006.218.08:02:00.05#ibcon#read 3, iclass 11, count 2 2006.218.08:02:00.05#ibcon#about to read 4, iclass 11, count 2 2006.218.08:02:00.05#ibcon#read 4, iclass 11, count 2 2006.218.08:02:00.05#ibcon#about to read 5, iclass 11, count 2 2006.218.08:02:00.05#ibcon#read 5, iclass 11, count 2 2006.218.08:02:00.05#ibcon#about to read 6, iclass 11, count 2 2006.218.08:02:00.05#ibcon#read 6, iclass 11, count 2 2006.218.08:02:00.05#ibcon#end of sib2, iclass 11, count 2 2006.218.08:02:00.05#ibcon#*after write, iclass 11, count 2 2006.218.08:02:00.05#ibcon#*before return 0, iclass 11, count 2 2006.218.08:02:00.05#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.218.08:02:00.05#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.218.08:02:00.05#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.218.08:02:00.05#ibcon#ireg 7 cls_cnt 0 2006.218.08:02:00.05#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.218.08:02:00.17#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.218.08:02:00.17#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.218.08:02:00.17#ibcon#enter wrdev, iclass 11, count 0 2006.218.08:02:00.17#ibcon#first serial, iclass 11, count 0 2006.218.08:02:00.17#ibcon#enter sib2, iclass 11, count 0 2006.218.08:02:00.17#ibcon#flushed, iclass 11, count 0 2006.218.08:02:00.17#ibcon#about to write, iclass 11, count 0 2006.218.08:02:00.17#ibcon#wrote, iclass 11, count 0 2006.218.08:02:00.17#ibcon#about to read 3, iclass 11, count 0 2006.218.08:02:00.20#ibcon#read 3, iclass 11, count 0 2006.218.08:02:00.20#ibcon#about to read 4, iclass 11, count 0 2006.218.08:02:00.20#ibcon#read 4, iclass 11, count 0 2006.218.08:02:00.20#ibcon#about to read 5, iclass 11, count 0 2006.218.08:02:00.20#ibcon#read 5, iclass 11, count 0 2006.218.08:02:00.20#ibcon#about to read 6, iclass 11, count 0 2006.218.08:02:00.20#ibcon#read 6, iclass 11, count 0 2006.218.08:02:00.20#ibcon#end of sib2, iclass 11, count 0 2006.218.08:02:00.20#ibcon#*mode == 0, iclass 11, count 0 2006.218.08:02:00.20#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.218.08:02:00.20#ibcon#[25=USB\r\n] 2006.218.08:02:00.20#ibcon#*before write, iclass 11, count 0 2006.218.08:02:00.20#ibcon#enter sib2, iclass 11, count 0 2006.218.08:02:00.20#ibcon#flushed, iclass 11, count 0 2006.218.08:02:00.20#ibcon#about to write, iclass 11, count 0 2006.218.08:02:00.20#ibcon#wrote, iclass 11, count 0 2006.218.08:02:00.20#ibcon#about to read 3, iclass 11, count 0 2006.218.08:02:00.23#ibcon#read 3, iclass 11, count 0 2006.218.08:02:00.23#ibcon#about to read 4, iclass 11, count 0 2006.218.08:02:00.23#ibcon#read 4, iclass 11, count 0 2006.218.08:02:00.23#ibcon#about to read 5, iclass 11, count 0 2006.218.08:02:00.23#ibcon#read 5, iclass 11, count 0 2006.218.08:02:00.23#ibcon#about to read 6, iclass 11, count 0 2006.218.08:02:00.23#ibcon#read 6, iclass 11, count 0 2006.218.08:02:00.23#ibcon#end of sib2, iclass 11, count 0 2006.218.08:02:00.23#ibcon#*after write, iclass 11, count 0 2006.218.08:02:00.23#ibcon#*before return 0, iclass 11, count 0 2006.218.08:02:00.23#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.218.08:02:00.23#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.218.08:02:00.23#ibcon#about to clear, iclass 11 cls_cnt 0 2006.218.08:02:00.23#ibcon#cleared, iclass 11 cls_cnt 0 2006.218.08:02:00.23$vc4f8/valo=8,852.99 2006.218.08:02:00.23#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.218.08:02:00.23#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.218.08:02:00.23#ibcon#ireg 17 cls_cnt 0 2006.218.08:02:00.23#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.218.08:02:00.23#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.218.08:02:00.23#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.218.08:02:00.23#ibcon#enter wrdev, iclass 13, count 0 2006.218.08:02:00.23#ibcon#first serial, iclass 13, count 0 2006.218.08:02:00.23#ibcon#enter sib2, iclass 13, count 0 2006.218.08:02:00.23#ibcon#flushed, iclass 13, count 0 2006.218.08:02:00.23#ibcon#about to write, iclass 13, count 0 2006.218.08:02:00.23#ibcon#wrote, iclass 13, count 0 2006.218.08:02:00.23#ibcon#about to read 3, iclass 13, count 0 2006.218.08:02:00.25#ibcon#read 3, iclass 13, count 0 2006.218.08:02:00.25#ibcon#about to read 4, iclass 13, count 0 2006.218.08:02:00.25#ibcon#read 4, iclass 13, count 0 2006.218.08:02:00.25#ibcon#about to read 5, iclass 13, count 0 2006.218.08:02:00.25#ibcon#read 5, iclass 13, count 0 2006.218.08:02:00.25#ibcon#about to read 6, iclass 13, count 0 2006.218.08:02:00.25#ibcon#read 6, iclass 13, count 0 2006.218.08:02:00.25#ibcon#end of sib2, iclass 13, count 0 2006.218.08:02:00.25#ibcon#*mode == 0, iclass 13, count 0 2006.218.08:02:00.25#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.218.08:02:00.25#ibcon#[26=FRQ=08,852.99\r\n] 2006.218.08:02:00.25#ibcon#*before write, iclass 13, count 0 2006.218.08:02:00.25#ibcon#enter sib2, iclass 13, count 0 2006.218.08:02:00.25#ibcon#flushed, iclass 13, count 0 2006.218.08:02:00.25#ibcon#about to write, iclass 13, count 0 2006.218.08:02:00.25#ibcon#wrote, iclass 13, count 0 2006.218.08:02:00.25#ibcon#about to read 3, iclass 13, count 0 2006.218.08:02:00.29#ibcon#read 3, iclass 13, count 0 2006.218.08:02:00.29#ibcon#about to read 4, iclass 13, count 0 2006.218.08:02:00.29#ibcon#read 4, iclass 13, count 0 2006.218.08:02:00.29#ibcon#about to read 5, iclass 13, count 0 2006.218.08:02:00.29#ibcon#read 5, iclass 13, count 0 2006.218.08:02:00.29#ibcon#about to read 6, iclass 13, count 0 2006.218.08:02:00.29#ibcon#read 6, iclass 13, count 0 2006.218.08:02:00.29#ibcon#end of sib2, iclass 13, count 0 2006.218.08:02:00.29#ibcon#*after write, iclass 13, count 0 2006.218.08:02:00.29#ibcon#*before return 0, iclass 13, count 0 2006.218.08:02:00.29#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.218.08:02:00.29#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.218.08:02:00.29#ibcon#about to clear, iclass 13 cls_cnt 0 2006.218.08:02:00.29#ibcon#cleared, iclass 13 cls_cnt 0 2006.218.08:02:00.29$vc4f8/va=8,7 2006.218.08:02:00.29#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.218.08:02:00.29#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.218.08:02:00.29#ibcon#ireg 11 cls_cnt 2 2006.218.08:02:00.29#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.218.08:02:00.35#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.218.08:02:00.35#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.218.08:02:00.35#ibcon#enter wrdev, iclass 15, count 2 2006.218.08:02:00.35#ibcon#first serial, iclass 15, count 2 2006.218.08:02:00.35#ibcon#enter sib2, iclass 15, count 2 2006.218.08:02:00.35#ibcon#flushed, iclass 15, count 2 2006.218.08:02:00.35#ibcon#about to write, iclass 15, count 2 2006.218.08:02:00.35#ibcon#wrote, iclass 15, count 2 2006.218.08:02:00.35#ibcon#about to read 3, iclass 15, count 2 2006.218.08:02:00.37#ibcon#read 3, iclass 15, count 2 2006.218.08:02:00.37#ibcon#about to read 4, iclass 15, count 2 2006.218.08:02:00.37#ibcon#read 4, iclass 15, count 2 2006.218.08:02:00.37#ibcon#about to read 5, iclass 15, count 2 2006.218.08:02:00.37#ibcon#read 5, iclass 15, count 2 2006.218.08:02:00.37#ibcon#about to read 6, iclass 15, count 2 2006.218.08:02:00.37#ibcon#read 6, iclass 15, count 2 2006.218.08:02:00.37#ibcon#end of sib2, iclass 15, count 2 2006.218.08:02:00.37#ibcon#*mode == 0, iclass 15, count 2 2006.218.08:02:00.37#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.218.08:02:00.37#ibcon#[25=AT08-07\r\n] 2006.218.08:02:00.37#ibcon#*before write, iclass 15, count 2 2006.218.08:02:00.37#ibcon#enter sib2, iclass 15, count 2 2006.218.08:02:00.37#ibcon#flushed, iclass 15, count 2 2006.218.08:02:00.37#ibcon#about to write, iclass 15, count 2 2006.218.08:02:00.37#ibcon#wrote, iclass 15, count 2 2006.218.08:02:00.37#ibcon#about to read 3, iclass 15, count 2 2006.218.08:02:00.40#ibcon#read 3, iclass 15, count 2 2006.218.08:02:00.40#ibcon#about to read 4, iclass 15, count 2 2006.218.08:02:00.40#ibcon#read 4, iclass 15, count 2 2006.218.08:02:00.40#ibcon#about to read 5, iclass 15, count 2 2006.218.08:02:00.40#ibcon#read 5, iclass 15, count 2 2006.218.08:02:00.40#ibcon#about to read 6, iclass 15, count 2 2006.218.08:02:00.40#ibcon#read 6, iclass 15, count 2 2006.218.08:02:00.40#ibcon#end of sib2, iclass 15, count 2 2006.218.08:02:00.40#ibcon#*after write, iclass 15, count 2 2006.218.08:02:00.40#ibcon#*before return 0, iclass 15, count 2 2006.218.08:02:00.40#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.218.08:02:00.40#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.218.08:02:00.40#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.218.08:02:00.40#ibcon#ireg 7 cls_cnt 0 2006.218.08:02:00.40#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.218.08:02:00.52#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.218.08:02:00.52#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.218.08:02:00.52#ibcon#enter wrdev, iclass 15, count 0 2006.218.08:02:00.52#ibcon#first serial, iclass 15, count 0 2006.218.08:02:00.52#ibcon#enter sib2, iclass 15, count 0 2006.218.08:02:00.52#ibcon#flushed, iclass 15, count 0 2006.218.08:02:00.52#ibcon#about to write, iclass 15, count 0 2006.218.08:02:00.52#ibcon#wrote, iclass 15, count 0 2006.218.08:02:00.52#ibcon#about to read 3, iclass 15, count 0 2006.218.08:02:00.54#ibcon#read 3, iclass 15, count 0 2006.218.08:02:00.54#ibcon#about to read 4, iclass 15, count 0 2006.218.08:02:00.54#ibcon#read 4, iclass 15, count 0 2006.218.08:02:00.54#ibcon#about to read 5, iclass 15, count 0 2006.218.08:02:00.54#ibcon#read 5, iclass 15, count 0 2006.218.08:02:00.54#ibcon#about to read 6, iclass 15, count 0 2006.218.08:02:00.54#ibcon#read 6, iclass 15, count 0 2006.218.08:02:00.54#ibcon#end of sib2, iclass 15, count 0 2006.218.08:02:00.54#ibcon#*mode == 0, iclass 15, count 0 2006.218.08:02:00.54#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.218.08:02:00.54#ibcon#[25=USB\r\n] 2006.218.08:02:00.54#ibcon#*before write, iclass 15, count 0 2006.218.08:02:00.54#ibcon#enter sib2, iclass 15, count 0 2006.218.08:02:00.54#ibcon#flushed, iclass 15, count 0 2006.218.08:02:00.54#ibcon#about to write, iclass 15, count 0 2006.218.08:02:00.54#ibcon#wrote, iclass 15, count 0 2006.218.08:02:00.54#ibcon#about to read 3, iclass 15, count 0 2006.218.08:02:00.57#ibcon#read 3, iclass 15, count 0 2006.218.08:02:00.57#ibcon#about to read 4, iclass 15, count 0 2006.218.08:02:00.57#ibcon#read 4, iclass 15, count 0 2006.218.08:02:00.57#ibcon#about to read 5, iclass 15, count 0 2006.218.08:02:00.57#ibcon#read 5, iclass 15, count 0 2006.218.08:02:00.57#ibcon#about to read 6, iclass 15, count 0 2006.218.08:02:00.57#ibcon#read 6, iclass 15, count 0 2006.218.08:02:00.57#ibcon#end of sib2, iclass 15, count 0 2006.218.08:02:00.57#ibcon#*after write, iclass 15, count 0 2006.218.08:02:00.57#ibcon#*before return 0, iclass 15, count 0 2006.218.08:02:00.57#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.218.08:02:00.57#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.218.08:02:00.57#ibcon#about to clear, iclass 15 cls_cnt 0 2006.218.08:02:00.57#ibcon#cleared, iclass 15 cls_cnt 0 2006.218.08:02:00.57$vc4f8/vblo=1,632.99 2006.218.08:02:00.57#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.218.08:02:00.57#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.218.08:02:00.57#ibcon#ireg 17 cls_cnt 0 2006.218.08:02:00.57#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.218.08:02:00.57#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.218.08:02:00.57#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.218.08:02:00.57#ibcon#enter wrdev, iclass 17, count 0 2006.218.08:02:00.57#ibcon#first serial, iclass 17, count 0 2006.218.08:02:00.57#ibcon#enter sib2, iclass 17, count 0 2006.218.08:02:00.57#ibcon#flushed, iclass 17, count 0 2006.218.08:02:00.57#ibcon#about to write, iclass 17, count 0 2006.218.08:02:00.57#ibcon#wrote, iclass 17, count 0 2006.218.08:02:00.57#ibcon#about to read 3, iclass 17, count 0 2006.218.08:02:00.59#ibcon#read 3, iclass 17, count 0 2006.218.08:02:00.59#ibcon#about to read 4, iclass 17, count 0 2006.218.08:02:00.59#ibcon#read 4, iclass 17, count 0 2006.218.08:02:00.59#ibcon#about to read 5, iclass 17, count 0 2006.218.08:02:00.59#ibcon#read 5, iclass 17, count 0 2006.218.08:02:00.59#ibcon#about to read 6, iclass 17, count 0 2006.218.08:02:00.59#ibcon#read 6, iclass 17, count 0 2006.218.08:02:00.59#ibcon#end of sib2, iclass 17, count 0 2006.218.08:02:00.59#ibcon#*mode == 0, iclass 17, count 0 2006.218.08:02:00.59#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.218.08:02:00.59#ibcon#[28=FRQ=01,632.99\r\n] 2006.218.08:02:00.59#ibcon#*before write, iclass 17, count 0 2006.218.08:02:00.59#ibcon#enter sib2, iclass 17, count 0 2006.218.08:02:00.59#ibcon#flushed, iclass 17, count 0 2006.218.08:02:00.59#ibcon#about to write, iclass 17, count 0 2006.218.08:02:00.59#ibcon#wrote, iclass 17, count 0 2006.218.08:02:00.59#ibcon#about to read 3, iclass 17, count 0 2006.218.08:02:00.63#ibcon#read 3, iclass 17, count 0 2006.218.08:02:00.63#ibcon#about to read 4, iclass 17, count 0 2006.218.08:02:00.63#ibcon#read 4, iclass 17, count 0 2006.218.08:02:00.63#ibcon#about to read 5, iclass 17, count 0 2006.218.08:02:00.63#ibcon#read 5, iclass 17, count 0 2006.218.08:02:00.63#ibcon#about to read 6, iclass 17, count 0 2006.218.08:02:00.63#ibcon#read 6, iclass 17, count 0 2006.218.08:02:00.63#ibcon#end of sib2, iclass 17, count 0 2006.218.08:02:00.63#ibcon#*after write, iclass 17, count 0 2006.218.08:02:00.63#ibcon#*before return 0, iclass 17, count 0 2006.218.08:02:00.63#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.218.08:02:00.63#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.218.08:02:00.63#ibcon#about to clear, iclass 17 cls_cnt 0 2006.218.08:02:00.63#ibcon#cleared, iclass 17 cls_cnt 0 2006.218.08:02:00.63$vc4f8/vb=1,4 2006.218.08:02:00.63#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.218.08:02:00.63#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.218.08:02:00.63#ibcon#ireg 11 cls_cnt 2 2006.218.08:02:00.63#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.218.08:02:00.63#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.218.08:02:00.63#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.218.08:02:00.63#ibcon#enter wrdev, iclass 19, count 2 2006.218.08:02:00.63#ibcon#first serial, iclass 19, count 2 2006.218.08:02:00.63#ibcon#enter sib2, iclass 19, count 2 2006.218.08:02:00.63#ibcon#flushed, iclass 19, count 2 2006.218.08:02:00.63#ibcon#about to write, iclass 19, count 2 2006.218.08:02:00.63#ibcon#wrote, iclass 19, count 2 2006.218.08:02:00.63#ibcon#about to read 3, iclass 19, count 2 2006.218.08:02:00.65#ibcon#read 3, iclass 19, count 2 2006.218.08:02:00.65#ibcon#about to read 4, iclass 19, count 2 2006.218.08:02:00.65#ibcon#read 4, iclass 19, count 2 2006.218.08:02:00.65#ibcon#about to read 5, iclass 19, count 2 2006.218.08:02:00.65#ibcon#read 5, iclass 19, count 2 2006.218.08:02:00.65#ibcon#about to read 6, iclass 19, count 2 2006.218.08:02:00.65#ibcon#read 6, iclass 19, count 2 2006.218.08:02:00.65#ibcon#end of sib2, iclass 19, count 2 2006.218.08:02:00.65#ibcon#*mode == 0, iclass 19, count 2 2006.218.08:02:00.65#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.218.08:02:00.65#ibcon#[27=AT01-04\r\n] 2006.218.08:02:00.65#ibcon#*before write, iclass 19, count 2 2006.218.08:02:00.65#ibcon#enter sib2, iclass 19, count 2 2006.218.08:02:00.65#ibcon#flushed, iclass 19, count 2 2006.218.08:02:00.65#ibcon#about to write, iclass 19, count 2 2006.218.08:02:00.65#ibcon#wrote, iclass 19, count 2 2006.218.08:02:00.65#ibcon#about to read 3, iclass 19, count 2 2006.218.08:02:00.68#ibcon#read 3, iclass 19, count 2 2006.218.08:02:00.68#ibcon#about to read 4, iclass 19, count 2 2006.218.08:02:00.68#ibcon#read 4, iclass 19, count 2 2006.218.08:02:00.68#ibcon#about to read 5, iclass 19, count 2 2006.218.08:02:00.68#ibcon#read 5, iclass 19, count 2 2006.218.08:02:00.68#ibcon#about to read 6, iclass 19, count 2 2006.218.08:02:00.68#ibcon#read 6, iclass 19, count 2 2006.218.08:02:00.68#ibcon#end of sib2, iclass 19, count 2 2006.218.08:02:00.68#ibcon#*after write, iclass 19, count 2 2006.218.08:02:00.68#ibcon#*before return 0, iclass 19, count 2 2006.218.08:02:00.68#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.218.08:02:00.68#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.218.08:02:00.68#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.218.08:02:00.68#ibcon#ireg 7 cls_cnt 0 2006.218.08:02:00.68#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.218.08:02:00.80#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.218.08:02:00.80#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.218.08:02:00.80#ibcon#enter wrdev, iclass 19, count 0 2006.218.08:02:00.80#ibcon#first serial, iclass 19, count 0 2006.218.08:02:00.80#ibcon#enter sib2, iclass 19, count 0 2006.218.08:02:00.80#ibcon#flushed, iclass 19, count 0 2006.218.08:02:00.80#ibcon#about to write, iclass 19, count 0 2006.218.08:02:00.80#ibcon#wrote, iclass 19, count 0 2006.218.08:02:00.80#ibcon#about to read 3, iclass 19, count 0 2006.218.08:02:00.82#ibcon#read 3, iclass 19, count 0 2006.218.08:02:00.82#ibcon#about to read 4, iclass 19, count 0 2006.218.08:02:00.82#ibcon#read 4, iclass 19, count 0 2006.218.08:02:00.82#ibcon#about to read 5, iclass 19, count 0 2006.218.08:02:00.82#ibcon#read 5, iclass 19, count 0 2006.218.08:02:00.82#ibcon#about to read 6, iclass 19, count 0 2006.218.08:02:00.82#ibcon#read 6, iclass 19, count 0 2006.218.08:02:00.82#ibcon#end of sib2, iclass 19, count 0 2006.218.08:02:00.82#ibcon#*mode == 0, iclass 19, count 0 2006.218.08:02:00.82#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.218.08:02:00.82#ibcon#[27=USB\r\n] 2006.218.08:02:00.82#ibcon#*before write, iclass 19, count 0 2006.218.08:02:00.82#ibcon#enter sib2, iclass 19, count 0 2006.218.08:02:00.82#ibcon#flushed, iclass 19, count 0 2006.218.08:02:00.82#ibcon#about to write, iclass 19, count 0 2006.218.08:02:00.82#ibcon#wrote, iclass 19, count 0 2006.218.08:02:00.82#ibcon#about to read 3, iclass 19, count 0 2006.218.08:02:00.85#ibcon#read 3, iclass 19, count 0 2006.218.08:02:00.85#ibcon#about to read 4, iclass 19, count 0 2006.218.08:02:00.85#ibcon#read 4, iclass 19, count 0 2006.218.08:02:00.85#ibcon#about to read 5, iclass 19, count 0 2006.218.08:02:00.85#ibcon#read 5, iclass 19, count 0 2006.218.08:02:00.85#ibcon#about to read 6, iclass 19, count 0 2006.218.08:02:00.85#ibcon#read 6, iclass 19, count 0 2006.218.08:02:00.85#ibcon#end of sib2, iclass 19, count 0 2006.218.08:02:00.85#ibcon#*after write, iclass 19, count 0 2006.218.08:02:00.85#ibcon#*before return 0, iclass 19, count 0 2006.218.08:02:00.85#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.218.08:02:00.85#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.218.08:02:00.85#ibcon#about to clear, iclass 19 cls_cnt 0 2006.218.08:02:00.85#ibcon#cleared, iclass 19 cls_cnt 0 2006.218.08:02:00.85$vc4f8/vblo=2,640.99 2006.218.08:02:00.85#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.218.08:02:00.85#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.218.08:02:00.85#ibcon#ireg 17 cls_cnt 0 2006.218.08:02:00.85#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.218.08:02:00.85#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.218.08:02:00.85#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.218.08:02:00.85#ibcon#enter wrdev, iclass 21, count 0 2006.218.08:02:00.85#ibcon#first serial, iclass 21, count 0 2006.218.08:02:00.85#ibcon#enter sib2, iclass 21, count 0 2006.218.08:02:00.85#ibcon#flushed, iclass 21, count 0 2006.218.08:02:00.85#ibcon#about to write, iclass 21, count 0 2006.218.08:02:00.85#ibcon#wrote, iclass 21, count 0 2006.218.08:02:00.85#ibcon#about to read 3, iclass 21, count 0 2006.218.08:02:00.87#ibcon#read 3, iclass 21, count 0 2006.218.08:02:00.87#ibcon#about to read 4, iclass 21, count 0 2006.218.08:02:00.87#ibcon#read 4, iclass 21, count 0 2006.218.08:02:00.87#ibcon#about to read 5, iclass 21, count 0 2006.218.08:02:00.87#ibcon#read 5, iclass 21, count 0 2006.218.08:02:00.87#ibcon#about to read 6, iclass 21, count 0 2006.218.08:02:00.87#ibcon#read 6, iclass 21, count 0 2006.218.08:02:00.87#ibcon#end of sib2, iclass 21, count 0 2006.218.08:02:00.87#ibcon#*mode == 0, iclass 21, count 0 2006.218.08:02:00.87#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.218.08:02:00.87#ibcon#[28=FRQ=02,640.99\r\n] 2006.218.08:02:00.87#ibcon#*before write, iclass 21, count 0 2006.218.08:02:00.87#ibcon#enter sib2, iclass 21, count 0 2006.218.08:02:00.87#ibcon#flushed, iclass 21, count 0 2006.218.08:02:00.87#ibcon#about to write, iclass 21, count 0 2006.218.08:02:00.87#ibcon#wrote, iclass 21, count 0 2006.218.08:02:00.87#ibcon#about to read 3, iclass 21, count 0 2006.218.08:02:00.91#ibcon#read 3, iclass 21, count 0 2006.218.08:02:00.91#ibcon#about to read 4, iclass 21, count 0 2006.218.08:02:00.91#ibcon#read 4, iclass 21, count 0 2006.218.08:02:00.91#ibcon#about to read 5, iclass 21, count 0 2006.218.08:02:00.91#ibcon#read 5, iclass 21, count 0 2006.218.08:02:00.91#ibcon#about to read 6, iclass 21, count 0 2006.218.08:02:00.91#ibcon#read 6, iclass 21, count 0 2006.218.08:02:00.91#ibcon#end of sib2, iclass 21, count 0 2006.218.08:02:00.91#ibcon#*after write, iclass 21, count 0 2006.218.08:02:00.91#ibcon#*before return 0, iclass 21, count 0 2006.218.08:02:00.91#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.218.08:02:00.91#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.218.08:02:00.91#ibcon#about to clear, iclass 21 cls_cnt 0 2006.218.08:02:00.91#ibcon#cleared, iclass 21 cls_cnt 0 2006.218.08:02:00.91$vc4f8/vb=2,4 2006.218.08:02:00.91#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.218.08:02:00.91#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.218.08:02:00.91#ibcon#ireg 11 cls_cnt 2 2006.218.08:02:00.91#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.218.08:02:00.97#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.218.08:02:00.97#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.218.08:02:00.97#ibcon#enter wrdev, iclass 23, count 2 2006.218.08:02:00.97#ibcon#first serial, iclass 23, count 2 2006.218.08:02:00.97#ibcon#enter sib2, iclass 23, count 2 2006.218.08:02:00.97#ibcon#flushed, iclass 23, count 2 2006.218.08:02:00.97#ibcon#about to write, iclass 23, count 2 2006.218.08:02:00.97#ibcon#wrote, iclass 23, count 2 2006.218.08:02:00.97#ibcon#about to read 3, iclass 23, count 2 2006.218.08:02:00.99#ibcon#read 3, iclass 23, count 2 2006.218.08:02:00.99#ibcon#about to read 4, iclass 23, count 2 2006.218.08:02:00.99#ibcon#read 4, iclass 23, count 2 2006.218.08:02:00.99#ibcon#about to read 5, iclass 23, count 2 2006.218.08:02:00.99#ibcon#read 5, iclass 23, count 2 2006.218.08:02:00.99#ibcon#about to read 6, iclass 23, count 2 2006.218.08:02:00.99#ibcon#read 6, iclass 23, count 2 2006.218.08:02:00.99#ibcon#end of sib2, iclass 23, count 2 2006.218.08:02:00.99#ibcon#*mode == 0, iclass 23, count 2 2006.218.08:02:00.99#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.218.08:02:00.99#ibcon#[27=AT02-04\r\n] 2006.218.08:02:00.99#ibcon#*before write, iclass 23, count 2 2006.218.08:02:00.99#ibcon#enter sib2, iclass 23, count 2 2006.218.08:02:00.99#ibcon#flushed, iclass 23, count 2 2006.218.08:02:00.99#ibcon#about to write, iclass 23, count 2 2006.218.08:02:00.99#ibcon#wrote, iclass 23, count 2 2006.218.08:02:00.99#ibcon#about to read 3, iclass 23, count 2 2006.218.08:02:01.02#ibcon#read 3, iclass 23, count 2 2006.218.08:02:01.02#ibcon#about to read 4, iclass 23, count 2 2006.218.08:02:01.02#ibcon#read 4, iclass 23, count 2 2006.218.08:02:01.02#ibcon#about to read 5, iclass 23, count 2 2006.218.08:02:01.02#ibcon#read 5, iclass 23, count 2 2006.218.08:02:01.02#ibcon#about to read 6, iclass 23, count 2 2006.218.08:02:01.02#ibcon#read 6, iclass 23, count 2 2006.218.08:02:01.02#ibcon#end of sib2, iclass 23, count 2 2006.218.08:02:01.02#ibcon#*after write, iclass 23, count 2 2006.218.08:02:01.02#ibcon#*before return 0, iclass 23, count 2 2006.218.08:02:01.02#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.218.08:02:01.02#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.218.08:02:01.02#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.218.08:02:01.02#ibcon#ireg 7 cls_cnt 0 2006.218.08:02:01.02#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.218.08:02:01.14#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.218.08:02:01.14#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.218.08:02:01.14#ibcon#enter wrdev, iclass 23, count 0 2006.218.08:02:01.14#ibcon#first serial, iclass 23, count 0 2006.218.08:02:01.14#ibcon#enter sib2, iclass 23, count 0 2006.218.08:02:01.14#ibcon#flushed, iclass 23, count 0 2006.218.08:02:01.14#ibcon#about to write, iclass 23, count 0 2006.218.08:02:01.14#ibcon#wrote, iclass 23, count 0 2006.218.08:02:01.14#ibcon#about to read 3, iclass 23, count 0 2006.218.08:02:01.16#ibcon#read 3, iclass 23, count 0 2006.218.08:02:01.16#ibcon#about to read 4, iclass 23, count 0 2006.218.08:02:01.16#ibcon#read 4, iclass 23, count 0 2006.218.08:02:01.16#ibcon#about to read 5, iclass 23, count 0 2006.218.08:02:01.16#ibcon#read 5, iclass 23, count 0 2006.218.08:02:01.16#ibcon#about to read 6, iclass 23, count 0 2006.218.08:02:01.16#ibcon#read 6, iclass 23, count 0 2006.218.08:02:01.16#ibcon#end of sib2, iclass 23, count 0 2006.218.08:02:01.16#ibcon#*mode == 0, iclass 23, count 0 2006.218.08:02:01.16#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.218.08:02:01.16#ibcon#[27=USB\r\n] 2006.218.08:02:01.16#ibcon#*before write, iclass 23, count 0 2006.218.08:02:01.16#ibcon#enter sib2, iclass 23, count 0 2006.218.08:02:01.16#ibcon#flushed, iclass 23, count 0 2006.218.08:02:01.16#ibcon#about to write, iclass 23, count 0 2006.218.08:02:01.16#ibcon#wrote, iclass 23, count 0 2006.218.08:02:01.16#ibcon#about to read 3, iclass 23, count 0 2006.218.08:02:01.19#ibcon#read 3, iclass 23, count 0 2006.218.08:02:01.19#ibcon#about to read 4, iclass 23, count 0 2006.218.08:02:01.19#ibcon#read 4, iclass 23, count 0 2006.218.08:02:01.19#ibcon#about to read 5, iclass 23, count 0 2006.218.08:02:01.19#ibcon#read 5, iclass 23, count 0 2006.218.08:02:01.19#ibcon#about to read 6, iclass 23, count 0 2006.218.08:02:01.19#ibcon#read 6, iclass 23, count 0 2006.218.08:02:01.19#ibcon#end of sib2, iclass 23, count 0 2006.218.08:02:01.19#ibcon#*after write, iclass 23, count 0 2006.218.08:02:01.19#ibcon#*before return 0, iclass 23, count 0 2006.218.08:02:01.19#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.218.08:02:01.19#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.218.08:02:01.19#ibcon#about to clear, iclass 23 cls_cnt 0 2006.218.08:02:01.19#ibcon#cleared, iclass 23 cls_cnt 0 2006.218.08:02:01.19$vc4f8/vblo=3,656.99 2006.218.08:02:01.19#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.218.08:02:01.19#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.218.08:02:01.19#ibcon#ireg 17 cls_cnt 0 2006.218.08:02:01.19#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.218.08:02:01.19#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.218.08:02:01.19#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.218.08:02:01.19#ibcon#enter wrdev, iclass 25, count 0 2006.218.08:02:01.19#ibcon#first serial, iclass 25, count 0 2006.218.08:02:01.19#ibcon#enter sib2, iclass 25, count 0 2006.218.08:02:01.19#ibcon#flushed, iclass 25, count 0 2006.218.08:02:01.19#ibcon#about to write, iclass 25, count 0 2006.218.08:02:01.19#ibcon#wrote, iclass 25, count 0 2006.218.08:02:01.19#ibcon#about to read 3, iclass 25, count 0 2006.218.08:02:01.21#ibcon#read 3, iclass 25, count 0 2006.218.08:02:01.21#ibcon#about to read 4, iclass 25, count 0 2006.218.08:02:01.21#ibcon#read 4, iclass 25, count 0 2006.218.08:02:01.21#ibcon#about to read 5, iclass 25, count 0 2006.218.08:02:01.21#ibcon#read 5, iclass 25, count 0 2006.218.08:02:01.21#ibcon#about to read 6, iclass 25, count 0 2006.218.08:02:01.21#ibcon#read 6, iclass 25, count 0 2006.218.08:02:01.21#ibcon#end of sib2, iclass 25, count 0 2006.218.08:02:01.21#ibcon#*mode == 0, iclass 25, count 0 2006.218.08:02:01.21#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.218.08:02:01.21#ibcon#[28=FRQ=03,656.99\r\n] 2006.218.08:02:01.21#ibcon#*before write, iclass 25, count 0 2006.218.08:02:01.21#ibcon#enter sib2, iclass 25, count 0 2006.218.08:02:01.21#ibcon#flushed, iclass 25, count 0 2006.218.08:02:01.21#ibcon#about to write, iclass 25, count 0 2006.218.08:02:01.21#ibcon#wrote, iclass 25, count 0 2006.218.08:02:01.21#ibcon#about to read 3, iclass 25, count 0 2006.218.08:02:01.25#ibcon#read 3, iclass 25, count 0 2006.218.08:02:01.25#ibcon#about to read 4, iclass 25, count 0 2006.218.08:02:01.25#ibcon#read 4, iclass 25, count 0 2006.218.08:02:01.25#ibcon#about to read 5, iclass 25, count 0 2006.218.08:02:01.25#ibcon#read 5, iclass 25, count 0 2006.218.08:02:01.25#ibcon#about to read 6, iclass 25, count 0 2006.218.08:02:01.25#ibcon#read 6, iclass 25, count 0 2006.218.08:02:01.25#ibcon#end of sib2, iclass 25, count 0 2006.218.08:02:01.25#ibcon#*after write, iclass 25, count 0 2006.218.08:02:01.25#ibcon#*before return 0, iclass 25, count 0 2006.218.08:02:01.25#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.218.08:02:01.25#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.218.08:02:01.25#ibcon#about to clear, iclass 25 cls_cnt 0 2006.218.08:02:01.25#ibcon#cleared, iclass 25 cls_cnt 0 2006.218.08:02:01.25$vc4f8/vb=3,4 2006.218.08:02:01.25#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.218.08:02:01.25#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.218.08:02:01.25#ibcon#ireg 11 cls_cnt 2 2006.218.08:02:01.25#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.218.08:02:01.31#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.218.08:02:01.31#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.218.08:02:01.31#ibcon#enter wrdev, iclass 27, count 2 2006.218.08:02:01.31#ibcon#first serial, iclass 27, count 2 2006.218.08:02:01.31#ibcon#enter sib2, iclass 27, count 2 2006.218.08:02:01.31#ibcon#flushed, iclass 27, count 2 2006.218.08:02:01.31#ibcon#about to write, iclass 27, count 2 2006.218.08:02:01.31#ibcon#wrote, iclass 27, count 2 2006.218.08:02:01.31#ibcon#about to read 3, iclass 27, count 2 2006.218.08:02:01.33#ibcon#read 3, iclass 27, count 2 2006.218.08:02:01.33#ibcon#about to read 4, iclass 27, count 2 2006.218.08:02:01.33#ibcon#read 4, iclass 27, count 2 2006.218.08:02:01.33#ibcon#about to read 5, iclass 27, count 2 2006.218.08:02:01.33#ibcon#read 5, iclass 27, count 2 2006.218.08:02:01.33#ibcon#about to read 6, iclass 27, count 2 2006.218.08:02:01.33#ibcon#read 6, iclass 27, count 2 2006.218.08:02:01.33#ibcon#end of sib2, iclass 27, count 2 2006.218.08:02:01.33#ibcon#*mode == 0, iclass 27, count 2 2006.218.08:02:01.33#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.218.08:02:01.33#ibcon#[27=AT03-04\r\n] 2006.218.08:02:01.33#ibcon#*before write, iclass 27, count 2 2006.218.08:02:01.33#ibcon#enter sib2, iclass 27, count 2 2006.218.08:02:01.33#ibcon#flushed, iclass 27, count 2 2006.218.08:02:01.33#ibcon#about to write, iclass 27, count 2 2006.218.08:02:01.33#ibcon#wrote, iclass 27, count 2 2006.218.08:02:01.33#ibcon#about to read 3, iclass 27, count 2 2006.218.08:02:01.36#ibcon#read 3, iclass 27, count 2 2006.218.08:02:01.36#ibcon#about to read 4, iclass 27, count 2 2006.218.08:02:01.36#ibcon#read 4, iclass 27, count 2 2006.218.08:02:01.36#ibcon#about to read 5, iclass 27, count 2 2006.218.08:02:01.36#ibcon#read 5, iclass 27, count 2 2006.218.08:02:01.36#ibcon#about to read 6, iclass 27, count 2 2006.218.08:02:01.36#ibcon#read 6, iclass 27, count 2 2006.218.08:02:01.36#ibcon#end of sib2, iclass 27, count 2 2006.218.08:02:01.36#ibcon#*after write, iclass 27, count 2 2006.218.08:02:01.36#ibcon#*before return 0, iclass 27, count 2 2006.218.08:02:01.36#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.218.08:02:01.36#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.218.08:02:01.36#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.218.08:02:01.36#ibcon#ireg 7 cls_cnt 0 2006.218.08:02:01.36#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.218.08:02:01.48#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.218.08:02:01.48#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.218.08:02:01.48#ibcon#enter wrdev, iclass 27, count 0 2006.218.08:02:01.48#ibcon#first serial, iclass 27, count 0 2006.218.08:02:01.48#ibcon#enter sib2, iclass 27, count 0 2006.218.08:02:01.48#ibcon#flushed, iclass 27, count 0 2006.218.08:02:01.48#ibcon#about to write, iclass 27, count 0 2006.218.08:02:01.48#ibcon#wrote, iclass 27, count 0 2006.218.08:02:01.48#ibcon#about to read 3, iclass 27, count 0 2006.218.08:02:01.50#ibcon#read 3, iclass 27, count 0 2006.218.08:02:01.50#ibcon#about to read 4, iclass 27, count 0 2006.218.08:02:01.50#ibcon#read 4, iclass 27, count 0 2006.218.08:02:01.50#ibcon#about to read 5, iclass 27, count 0 2006.218.08:02:01.50#ibcon#read 5, iclass 27, count 0 2006.218.08:02:01.50#ibcon#about to read 6, iclass 27, count 0 2006.218.08:02:01.50#ibcon#read 6, iclass 27, count 0 2006.218.08:02:01.50#ibcon#end of sib2, iclass 27, count 0 2006.218.08:02:01.50#ibcon#*mode == 0, iclass 27, count 0 2006.218.08:02:01.50#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.218.08:02:01.50#ibcon#[27=USB\r\n] 2006.218.08:02:01.50#ibcon#*before write, iclass 27, count 0 2006.218.08:02:01.50#ibcon#enter sib2, iclass 27, count 0 2006.218.08:02:01.50#ibcon#flushed, iclass 27, count 0 2006.218.08:02:01.50#ibcon#about to write, iclass 27, count 0 2006.218.08:02:01.50#ibcon#wrote, iclass 27, count 0 2006.218.08:02:01.50#ibcon#about to read 3, iclass 27, count 0 2006.218.08:02:01.53#ibcon#read 3, iclass 27, count 0 2006.218.08:02:01.53#ibcon#about to read 4, iclass 27, count 0 2006.218.08:02:01.53#ibcon#read 4, iclass 27, count 0 2006.218.08:02:01.53#ibcon#about to read 5, iclass 27, count 0 2006.218.08:02:01.53#ibcon#read 5, iclass 27, count 0 2006.218.08:02:01.53#ibcon#about to read 6, iclass 27, count 0 2006.218.08:02:01.53#ibcon#read 6, iclass 27, count 0 2006.218.08:02:01.53#ibcon#end of sib2, iclass 27, count 0 2006.218.08:02:01.53#ibcon#*after write, iclass 27, count 0 2006.218.08:02:01.53#ibcon#*before return 0, iclass 27, count 0 2006.218.08:02:01.53#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.218.08:02:01.53#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.218.08:02:01.53#ibcon#about to clear, iclass 27 cls_cnt 0 2006.218.08:02:01.53#ibcon#cleared, iclass 27 cls_cnt 0 2006.218.08:02:01.53$vc4f8/vblo=4,712.99 2006.218.08:02:01.53#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.218.08:02:01.53#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.218.08:02:01.53#ibcon#ireg 17 cls_cnt 0 2006.218.08:02:01.53#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.218.08:02:01.53#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.218.08:02:01.53#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.218.08:02:01.53#ibcon#enter wrdev, iclass 29, count 0 2006.218.08:02:01.53#ibcon#first serial, iclass 29, count 0 2006.218.08:02:01.53#ibcon#enter sib2, iclass 29, count 0 2006.218.08:02:01.53#ibcon#flushed, iclass 29, count 0 2006.218.08:02:01.53#ibcon#about to write, iclass 29, count 0 2006.218.08:02:01.53#ibcon#wrote, iclass 29, count 0 2006.218.08:02:01.53#ibcon#about to read 3, iclass 29, count 0 2006.218.08:02:01.55#ibcon#read 3, iclass 29, count 0 2006.218.08:02:01.55#ibcon#about to read 4, iclass 29, count 0 2006.218.08:02:01.55#ibcon#read 4, iclass 29, count 0 2006.218.08:02:01.55#ibcon#about to read 5, iclass 29, count 0 2006.218.08:02:01.55#ibcon#read 5, iclass 29, count 0 2006.218.08:02:01.55#ibcon#about to read 6, iclass 29, count 0 2006.218.08:02:01.55#ibcon#read 6, iclass 29, count 0 2006.218.08:02:01.55#ibcon#end of sib2, iclass 29, count 0 2006.218.08:02:01.55#ibcon#*mode == 0, iclass 29, count 0 2006.218.08:02:01.55#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.218.08:02:01.55#ibcon#[28=FRQ=04,712.99\r\n] 2006.218.08:02:01.55#ibcon#*before write, iclass 29, count 0 2006.218.08:02:01.55#ibcon#enter sib2, iclass 29, count 0 2006.218.08:02:01.55#ibcon#flushed, iclass 29, count 0 2006.218.08:02:01.55#ibcon#about to write, iclass 29, count 0 2006.218.08:02:01.55#ibcon#wrote, iclass 29, count 0 2006.218.08:02:01.55#ibcon#about to read 3, iclass 29, count 0 2006.218.08:02:01.59#ibcon#read 3, iclass 29, count 0 2006.218.08:02:01.59#ibcon#about to read 4, iclass 29, count 0 2006.218.08:02:01.59#ibcon#read 4, iclass 29, count 0 2006.218.08:02:01.59#ibcon#about to read 5, iclass 29, count 0 2006.218.08:02:01.59#ibcon#read 5, iclass 29, count 0 2006.218.08:02:01.59#ibcon#about to read 6, iclass 29, count 0 2006.218.08:02:01.59#ibcon#read 6, iclass 29, count 0 2006.218.08:02:01.59#ibcon#end of sib2, iclass 29, count 0 2006.218.08:02:01.59#ibcon#*after write, iclass 29, count 0 2006.218.08:02:01.59#ibcon#*before return 0, iclass 29, count 0 2006.218.08:02:01.59#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.218.08:02:01.59#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.218.08:02:01.59#ibcon#about to clear, iclass 29 cls_cnt 0 2006.218.08:02:01.59#ibcon#cleared, iclass 29 cls_cnt 0 2006.218.08:02:01.59$vc4f8/vb=4,4 2006.218.08:02:01.59#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.218.08:02:01.59#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.218.08:02:01.59#ibcon#ireg 11 cls_cnt 2 2006.218.08:02:01.59#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.218.08:02:01.65#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.218.08:02:01.65#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.218.08:02:01.65#ibcon#enter wrdev, iclass 31, count 2 2006.218.08:02:01.65#ibcon#first serial, iclass 31, count 2 2006.218.08:02:01.65#ibcon#enter sib2, iclass 31, count 2 2006.218.08:02:01.65#ibcon#flushed, iclass 31, count 2 2006.218.08:02:01.65#ibcon#about to write, iclass 31, count 2 2006.218.08:02:01.65#ibcon#wrote, iclass 31, count 2 2006.218.08:02:01.65#ibcon#about to read 3, iclass 31, count 2 2006.218.08:02:01.67#ibcon#read 3, iclass 31, count 2 2006.218.08:02:01.67#ibcon#about to read 4, iclass 31, count 2 2006.218.08:02:01.67#ibcon#read 4, iclass 31, count 2 2006.218.08:02:01.67#ibcon#about to read 5, iclass 31, count 2 2006.218.08:02:01.67#ibcon#read 5, iclass 31, count 2 2006.218.08:02:01.67#ibcon#about to read 6, iclass 31, count 2 2006.218.08:02:01.67#ibcon#read 6, iclass 31, count 2 2006.218.08:02:01.67#ibcon#end of sib2, iclass 31, count 2 2006.218.08:02:01.67#ibcon#*mode == 0, iclass 31, count 2 2006.218.08:02:01.67#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.218.08:02:01.67#ibcon#[27=AT04-04\r\n] 2006.218.08:02:01.67#ibcon#*before write, iclass 31, count 2 2006.218.08:02:01.67#ibcon#enter sib2, iclass 31, count 2 2006.218.08:02:01.67#ibcon#flushed, iclass 31, count 2 2006.218.08:02:01.67#ibcon#about to write, iclass 31, count 2 2006.218.08:02:01.67#ibcon#wrote, iclass 31, count 2 2006.218.08:02:01.67#ibcon#about to read 3, iclass 31, count 2 2006.218.08:02:01.70#ibcon#read 3, iclass 31, count 2 2006.218.08:02:01.70#ibcon#about to read 4, iclass 31, count 2 2006.218.08:02:01.70#ibcon#read 4, iclass 31, count 2 2006.218.08:02:01.70#ibcon#about to read 5, iclass 31, count 2 2006.218.08:02:01.70#ibcon#read 5, iclass 31, count 2 2006.218.08:02:01.70#ibcon#about to read 6, iclass 31, count 2 2006.218.08:02:01.70#ibcon#read 6, iclass 31, count 2 2006.218.08:02:01.70#ibcon#end of sib2, iclass 31, count 2 2006.218.08:02:01.70#ibcon#*after write, iclass 31, count 2 2006.218.08:02:01.70#ibcon#*before return 0, iclass 31, count 2 2006.218.08:02:01.70#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.218.08:02:01.70#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.218.08:02:01.70#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.218.08:02:01.70#ibcon#ireg 7 cls_cnt 0 2006.218.08:02:01.70#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.218.08:02:01.82#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.218.08:02:01.82#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.218.08:02:01.82#ibcon#enter wrdev, iclass 31, count 0 2006.218.08:02:01.82#ibcon#first serial, iclass 31, count 0 2006.218.08:02:01.82#ibcon#enter sib2, iclass 31, count 0 2006.218.08:02:01.82#ibcon#flushed, iclass 31, count 0 2006.218.08:02:01.82#ibcon#about to write, iclass 31, count 0 2006.218.08:02:01.82#ibcon#wrote, iclass 31, count 0 2006.218.08:02:01.82#ibcon#about to read 3, iclass 31, count 0 2006.218.08:02:01.84#ibcon#read 3, iclass 31, count 0 2006.218.08:02:01.84#ibcon#about to read 4, iclass 31, count 0 2006.218.08:02:01.84#ibcon#read 4, iclass 31, count 0 2006.218.08:02:01.84#ibcon#about to read 5, iclass 31, count 0 2006.218.08:02:01.84#ibcon#read 5, iclass 31, count 0 2006.218.08:02:01.84#ibcon#about to read 6, iclass 31, count 0 2006.218.08:02:01.84#ibcon#read 6, iclass 31, count 0 2006.218.08:02:01.84#ibcon#end of sib2, iclass 31, count 0 2006.218.08:02:01.84#ibcon#*mode == 0, iclass 31, count 0 2006.218.08:02:01.84#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.218.08:02:01.84#ibcon#[27=USB\r\n] 2006.218.08:02:01.84#ibcon#*before write, iclass 31, count 0 2006.218.08:02:01.84#ibcon#enter sib2, iclass 31, count 0 2006.218.08:02:01.84#ibcon#flushed, iclass 31, count 0 2006.218.08:02:01.84#ibcon#about to write, iclass 31, count 0 2006.218.08:02:01.84#ibcon#wrote, iclass 31, count 0 2006.218.08:02:01.84#ibcon#about to read 3, iclass 31, count 0 2006.218.08:02:01.87#ibcon#read 3, iclass 31, count 0 2006.218.08:02:01.87#ibcon#about to read 4, iclass 31, count 0 2006.218.08:02:01.87#ibcon#read 4, iclass 31, count 0 2006.218.08:02:01.87#ibcon#about to read 5, iclass 31, count 0 2006.218.08:02:01.87#ibcon#read 5, iclass 31, count 0 2006.218.08:02:01.87#ibcon#about to read 6, iclass 31, count 0 2006.218.08:02:01.87#ibcon#read 6, iclass 31, count 0 2006.218.08:02:01.87#ibcon#end of sib2, iclass 31, count 0 2006.218.08:02:01.87#ibcon#*after write, iclass 31, count 0 2006.218.08:02:01.87#ibcon#*before return 0, iclass 31, count 0 2006.218.08:02:01.87#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.218.08:02:01.87#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.218.08:02:01.87#ibcon#about to clear, iclass 31 cls_cnt 0 2006.218.08:02:01.87#ibcon#cleared, iclass 31 cls_cnt 0 2006.218.08:02:01.87$vc4f8/vblo=5,744.99 2006.218.08:02:01.87#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.218.08:02:01.87#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.218.08:02:01.87#ibcon#ireg 17 cls_cnt 0 2006.218.08:02:01.87#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.218.08:02:01.87#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.218.08:02:01.87#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.218.08:02:01.87#ibcon#enter wrdev, iclass 33, count 0 2006.218.08:02:01.87#ibcon#first serial, iclass 33, count 0 2006.218.08:02:01.87#ibcon#enter sib2, iclass 33, count 0 2006.218.08:02:01.87#ibcon#flushed, iclass 33, count 0 2006.218.08:02:01.87#ibcon#about to write, iclass 33, count 0 2006.218.08:02:01.87#ibcon#wrote, iclass 33, count 0 2006.218.08:02:01.87#ibcon#about to read 3, iclass 33, count 0 2006.218.08:02:01.89#ibcon#read 3, iclass 33, count 0 2006.218.08:02:01.89#ibcon#about to read 4, iclass 33, count 0 2006.218.08:02:01.89#ibcon#read 4, iclass 33, count 0 2006.218.08:02:01.89#ibcon#about to read 5, iclass 33, count 0 2006.218.08:02:01.89#ibcon#read 5, iclass 33, count 0 2006.218.08:02:01.89#ibcon#about to read 6, iclass 33, count 0 2006.218.08:02:01.89#ibcon#read 6, iclass 33, count 0 2006.218.08:02:01.89#ibcon#end of sib2, iclass 33, count 0 2006.218.08:02:01.89#ibcon#*mode == 0, iclass 33, count 0 2006.218.08:02:01.89#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.218.08:02:01.89#ibcon#[28=FRQ=05,744.99\r\n] 2006.218.08:02:01.89#ibcon#*before write, iclass 33, count 0 2006.218.08:02:01.89#ibcon#enter sib2, iclass 33, count 0 2006.218.08:02:01.89#ibcon#flushed, iclass 33, count 0 2006.218.08:02:01.89#ibcon#about to write, iclass 33, count 0 2006.218.08:02:01.89#ibcon#wrote, iclass 33, count 0 2006.218.08:02:01.89#ibcon#about to read 3, iclass 33, count 0 2006.218.08:02:01.93#ibcon#read 3, iclass 33, count 0 2006.218.08:02:01.93#ibcon#about to read 4, iclass 33, count 0 2006.218.08:02:01.93#ibcon#read 4, iclass 33, count 0 2006.218.08:02:01.93#ibcon#about to read 5, iclass 33, count 0 2006.218.08:02:01.93#ibcon#read 5, iclass 33, count 0 2006.218.08:02:01.93#ibcon#about to read 6, iclass 33, count 0 2006.218.08:02:01.93#ibcon#read 6, iclass 33, count 0 2006.218.08:02:01.93#ibcon#end of sib2, iclass 33, count 0 2006.218.08:02:01.93#ibcon#*after write, iclass 33, count 0 2006.218.08:02:01.93#ibcon#*before return 0, iclass 33, count 0 2006.218.08:02:01.93#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.218.08:02:01.93#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.218.08:02:01.93#ibcon#about to clear, iclass 33 cls_cnt 0 2006.218.08:02:01.93#ibcon#cleared, iclass 33 cls_cnt 0 2006.218.08:02:01.93$vc4f8/vb=5,4 2006.218.08:02:01.93#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.218.08:02:01.93#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.218.08:02:01.93#ibcon#ireg 11 cls_cnt 2 2006.218.08:02:01.93#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.218.08:02:02.00#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.218.08:02:02.00#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.218.08:02:02.00#ibcon#enter wrdev, iclass 35, count 2 2006.218.08:02:02.00#ibcon#first serial, iclass 35, count 2 2006.218.08:02:02.00#ibcon#enter sib2, iclass 35, count 2 2006.218.08:02:02.00#ibcon#flushed, iclass 35, count 2 2006.218.08:02:02.00#ibcon#about to write, iclass 35, count 2 2006.218.08:02:02.00#ibcon#wrote, iclass 35, count 2 2006.218.08:02:02.00#ibcon#about to read 3, iclass 35, count 2 2006.218.08:02:02.01#ibcon#read 3, iclass 35, count 2 2006.218.08:02:02.01#ibcon#about to read 4, iclass 35, count 2 2006.218.08:02:02.01#ibcon#read 4, iclass 35, count 2 2006.218.08:02:02.01#ibcon#about to read 5, iclass 35, count 2 2006.218.08:02:02.01#ibcon#read 5, iclass 35, count 2 2006.218.08:02:02.01#ibcon#about to read 6, iclass 35, count 2 2006.218.08:02:02.01#ibcon#read 6, iclass 35, count 2 2006.218.08:02:02.01#ibcon#end of sib2, iclass 35, count 2 2006.218.08:02:02.01#ibcon#*mode == 0, iclass 35, count 2 2006.218.08:02:02.01#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.218.08:02:02.01#ibcon#[27=AT05-04\r\n] 2006.218.08:02:02.01#ibcon#*before write, iclass 35, count 2 2006.218.08:02:02.01#ibcon#enter sib2, iclass 35, count 2 2006.218.08:02:02.01#ibcon#flushed, iclass 35, count 2 2006.218.08:02:02.01#ibcon#about to write, iclass 35, count 2 2006.218.08:02:02.01#ibcon#wrote, iclass 35, count 2 2006.218.08:02:02.01#ibcon#about to read 3, iclass 35, count 2 2006.218.08:02:02.04#ibcon#read 3, iclass 35, count 2 2006.218.08:02:02.04#ibcon#about to read 4, iclass 35, count 2 2006.218.08:02:02.04#ibcon#read 4, iclass 35, count 2 2006.218.08:02:02.04#ibcon#about to read 5, iclass 35, count 2 2006.218.08:02:02.04#ibcon#read 5, iclass 35, count 2 2006.218.08:02:02.04#ibcon#about to read 6, iclass 35, count 2 2006.218.08:02:02.04#ibcon#read 6, iclass 35, count 2 2006.218.08:02:02.04#ibcon#end of sib2, iclass 35, count 2 2006.218.08:02:02.04#ibcon#*after write, iclass 35, count 2 2006.218.08:02:02.04#ibcon#*before return 0, iclass 35, count 2 2006.218.08:02:02.04#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.218.08:02:02.04#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.218.08:02:02.04#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.218.08:02:02.04#ibcon#ireg 7 cls_cnt 0 2006.218.08:02:02.04#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.218.08:02:02.16#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.218.08:02:02.16#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.218.08:02:02.16#ibcon#enter wrdev, iclass 35, count 0 2006.218.08:02:02.16#ibcon#first serial, iclass 35, count 0 2006.218.08:02:02.16#ibcon#enter sib2, iclass 35, count 0 2006.218.08:02:02.16#ibcon#flushed, iclass 35, count 0 2006.218.08:02:02.16#ibcon#about to write, iclass 35, count 0 2006.218.08:02:02.16#ibcon#wrote, iclass 35, count 0 2006.218.08:02:02.16#ibcon#about to read 3, iclass 35, count 0 2006.218.08:02:02.18#ibcon#read 3, iclass 35, count 0 2006.218.08:02:02.18#ibcon#about to read 4, iclass 35, count 0 2006.218.08:02:02.18#ibcon#read 4, iclass 35, count 0 2006.218.08:02:02.18#ibcon#about to read 5, iclass 35, count 0 2006.218.08:02:02.18#ibcon#read 5, iclass 35, count 0 2006.218.08:02:02.18#ibcon#about to read 6, iclass 35, count 0 2006.218.08:02:02.18#ibcon#read 6, iclass 35, count 0 2006.218.08:02:02.18#ibcon#end of sib2, iclass 35, count 0 2006.218.08:02:02.18#ibcon#*mode == 0, iclass 35, count 0 2006.218.08:02:02.18#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.218.08:02:02.18#ibcon#[27=USB\r\n] 2006.218.08:02:02.18#ibcon#*before write, iclass 35, count 0 2006.218.08:02:02.18#ibcon#enter sib2, iclass 35, count 0 2006.218.08:02:02.18#ibcon#flushed, iclass 35, count 0 2006.218.08:02:02.18#ibcon#about to write, iclass 35, count 0 2006.218.08:02:02.18#ibcon#wrote, iclass 35, count 0 2006.218.08:02:02.18#ibcon#about to read 3, iclass 35, count 0 2006.218.08:02:02.21#ibcon#read 3, iclass 35, count 0 2006.218.08:02:02.21#ibcon#about to read 4, iclass 35, count 0 2006.218.08:02:02.21#ibcon#read 4, iclass 35, count 0 2006.218.08:02:02.21#ibcon#about to read 5, iclass 35, count 0 2006.218.08:02:02.21#ibcon#read 5, iclass 35, count 0 2006.218.08:02:02.21#ibcon#about to read 6, iclass 35, count 0 2006.218.08:02:02.21#ibcon#read 6, iclass 35, count 0 2006.218.08:02:02.21#ibcon#end of sib2, iclass 35, count 0 2006.218.08:02:02.21#ibcon#*after write, iclass 35, count 0 2006.218.08:02:02.21#ibcon#*before return 0, iclass 35, count 0 2006.218.08:02:02.21#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.218.08:02:02.21#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.218.08:02:02.21#ibcon#about to clear, iclass 35 cls_cnt 0 2006.218.08:02:02.21#ibcon#cleared, iclass 35 cls_cnt 0 2006.218.08:02:02.21$vc4f8/vblo=6,752.99 2006.218.08:02:02.21#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.218.08:02:02.21#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.218.08:02:02.21#ibcon#ireg 17 cls_cnt 0 2006.218.08:02:02.21#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.218.08:02:02.21#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.218.08:02:02.21#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.218.08:02:02.21#ibcon#enter wrdev, iclass 37, count 0 2006.218.08:02:02.21#ibcon#first serial, iclass 37, count 0 2006.218.08:02:02.21#ibcon#enter sib2, iclass 37, count 0 2006.218.08:02:02.21#ibcon#flushed, iclass 37, count 0 2006.218.08:02:02.21#ibcon#about to write, iclass 37, count 0 2006.218.08:02:02.21#ibcon#wrote, iclass 37, count 0 2006.218.08:02:02.21#ibcon#about to read 3, iclass 37, count 0 2006.218.08:02:02.23#ibcon#read 3, iclass 37, count 0 2006.218.08:02:02.23#ibcon#about to read 4, iclass 37, count 0 2006.218.08:02:02.23#ibcon#read 4, iclass 37, count 0 2006.218.08:02:02.23#ibcon#about to read 5, iclass 37, count 0 2006.218.08:02:02.23#ibcon#read 5, iclass 37, count 0 2006.218.08:02:02.23#ibcon#about to read 6, iclass 37, count 0 2006.218.08:02:02.23#ibcon#read 6, iclass 37, count 0 2006.218.08:02:02.23#ibcon#end of sib2, iclass 37, count 0 2006.218.08:02:02.23#ibcon#*mode == 0, iclass 37, count 0 2006.218.08:02:02.23#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.218.08:02:02.23#ibcon#[28=FRQ=06,752.99\r\n] 2006.218.08:02:02.23#ibcon#*before write, iclass 37, count 0 2006.218.08:02:02.23#ibcon#enter sib2, iclass 37, count 0 2006.218.08:02:02.23#ibcon#flushed, iclass 37, count 0 2006.218.08:02:02.23#ibcon#about to write, iclass 37, count 0 2006.218.08:02:02.23#ibcon#wrote, iclass 37, count 0 2006.218.08:02:02.23#ibcon#about to read 3, iclass 37, count 0 2006.218.08:02:02.27#ibcon#read 3, iclass 37, count 0 2006.218.08:02:02.27#ibcon#about to read 4, iclass 37, count 0 2006.218.08:02:02.27#ibcon#read 4, iclass 37, count 0 2006.218.08:02:02.27#ibcon#about to read 5, iclass 37, count 0 2006.218.08:02:02.27#ibcon#read 5, iclass 37, count 0 2006.218.08:02:02.27#ibcon#about to read 6, iclass 37, count 0 2006.218.08:02:02.27#ibcon#read 6, iclass 37, count 0 2006.218.08:02:02.27#ibcon#end of sib2, iclass 37, count 0 2006.218.08:02:02.27#ibcon#*after write, iclass 37, count 0 2006.218.08:02:02.27#ibcon#*before return 0, iclass 37, count 0 2006.218.08:02:02.27#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.218.08:02:02.27#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.218.08:02:02.27#ibcon#about to clear, iclass 37 cls_cnt 0 2006.218.08:02:02.27#ibcon#cleared, iclass 37 cls_cnt 0 2006.218.08:02:02.27$vc4f8/vb=6,4 2006.218.08:02:02.27#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.218.08:02:02.27#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.218.08:02:02.27#ibcon#ireg 11 cls_cnt 2 2006.218.08:02:02.27#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.218.08:02:02.33#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.218.08:02:02.33#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.218.08:02:02.33#ibcon#enter wrdev, iclass 39, count 2 2006.218.08:02:02.33#ibcon#first serial, iclass 39, count 2 2006.218.08:02:02.33#ibcon#enter sib2, iclass 39, count 2 2006.218.08:02:02.33#ibcon#flushed, iclass 39, count 2 2006.218.08:02:02.33#ibcon#about to write, iclass 39, count 2 2006.218.08:02:02.33#ibcon#wrote, iclass 39, count 2 2006.218.08:02:02.33#ibcon#about to read 3, iclass 39, count 2 2006.218.08:02:02.35#ibcon#read 3, iclass 39, count 2 2006.218.08:02:02.35#ibcon#about to read 4, iclass 39, count 2 2006.218.08:02:02.35#ibcon#read 4, iclass 39, count 2 2006.218.08:02:02.35#ibcon#about to read 5, iclass 39, count 2 2006.218.08:02:02.35#ibcon#read 5, iclass 39, count 2 2006.218.08:02:02.35#ibcon#about to read 6, iclass 39, count 2 2006.218.08:02:02.35#ibcon#read 6, iclass 39, count 2 2006.218.08:02:02.35#ibcon#end of sib2, iclass 39, count 2 2006.218.08:02:02.35#ibcon#*mode == 0, iclass 39, count 2 2006.218.08:02:02.35#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.218.08:02:02.35#ibcon#[27=AT06-04\r\n] 2006.218.08:02:02.35#ibcon#*before write, iclass 39, count 2 2006.218.08:02:02.35#ibcon#enter sib2, iclass 39, count 2 2006.218.08:02:02.35#ibcon#flushed, iclass 39, count 2 2006.218.08:02:02.35#ibcon#about to write, iclass 39, count 2 2006.218.08:02:02.35#ibcon#wrote, iclass 39, count 2 2006.218.08:02:02.35#ibcon#about to read 3, iclass 39, count 2 2006.218.08:02:02.38#ibcon#read 3, iclass 39, count 2 2006.218.08:02:02.38#ibcon#about to read 4, iclass 39, count 2 2006.218.08:02:02.38#ibcon#read 4, iclass 39, count 2 2006.218.08:02:02.38#ibcon#about to read 5, iclass 39, count 2 2006.218.08:02:02.38#ibcon#read 5, iclass 39, count 2 2006.218.08:02:02.38#ibcon#about to read 6, iclass 39, count 2 2006.218.08:02:02.38#ibcon#read 6, iclass 39, count 2 2006.218.08:02:02.38#ibcon#end of sib2, iclass 39, count 2 2006.218.08:02:02.38#ibcon#*after write, iclass 39, count 2 2006.218.08:02:02.38#ibcon#*before return 0, iclass 39, count 2 2006.218.08:02:02.38#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.218.08:02:02.38#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.218.08:02:02.38#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.218.08:02:02.38#ibcon#ireg 7 cls_cnt 0 2006.218.08:02:02.38#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.218.08:02:02.50#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.218.08:02:02.50#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.218.08:02:02.50#ibcon#enter wrdev, iclass 39, count 0 2006.218.08:02:02.50#ibcon#first serial, iclass 39, count 0 2006.218.08:02:02.50#ibcon#enter sib2, iclass 39, count 0 2006.218.08:02:02.50#ibcon#flushed, iclass 39, count 0 2006.218.08:02:02.50#ibcon#about to write, iclass 39, count 0 2006.218.08:02:02.50#ibcon#wrote, iclass 39, count 0 2006.218.08:02:02.50#ibcon#about to read 3, iclass 39, count 0 2006.218.08:02:02.52#ibcon#read 3, iclass 39, count 0 2006.218.08:02:02.52#ibcon#about to read 4, iclass 39, count 0 2006.218.08:02:02.52#ibcon#read 4, iclass 39, count 0 2006.218.08:02:02.52#ibcon#about to read 5, iclass 39, count 0 2006.218.08:02:02.52#ibcon#read 5, iclass 39, count 0 2006.218.08:02:02.52#ibcon#about to read 6, iclass 39, count 0 2006.218.08:02:02.52#ibcon#read 6, iclass 39, count 0 2006.218.08:02:02.52#ibcon#end of sib2, iclass 39, count 0 2006.218.08:02:02.52#ibcon#*mode == 0, iclass 39, count 0 2006.218.08:02:02.52#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.218.08:02:02.52#ibcon#[27=USB\r\n] 2006.218.08:02:02.52#ibcon#*before write, iclass 39, count 0 2006.218.08:02:02.52#ibcon#enter sib2, iclass 39, count 0 2006.218.08:02:02.52#ibcon#flushed, iclass 39, count 0 2006.218.08:02:02.52#ibcon#about to write, iclass 39, count 0 2006.218.08:02:02.52#ibcon#wrote, iclass 39, count 0 2006.218.08:02:02.52#ibcon#about to read 3, iclass 39, count 0 2006.218.08:02:02.55#ibcon#read 3, iclass 39, count 0 2006.218.08:02:02.55#ibcon#about to read 4, iclass 39, count 0 2006.218.08:02:02.55#ibcon#read 4, iclass 39, count 0 2006.218.08:02:02.55#ibcon#about to read 5, iclass 39, count 0 2006.218.08:02:02.55#ibcon#read 5, iclass 39, count 0 2006.218.08:02:02.55#ibcon#about to read 6, iclass 39, count 0 2006.218.08:02:02.55#ibcon#read 6, iclass 39, count 0 2006.218.08:02:02.55#ibcon#end of sib2, iclass 39, count 0 2006.218.08:02:02.55#ibcon#*after write, iclass 39, count 0 2006.218.08:02:02.55#ibcon#*before return 0, iclass 39, count 0 2006.218.08:02:02.55#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.218.08:02:02.55#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.218.08:02:02.55#ibcon#about to clear, iclass 39 cls_cnt 0 2006.218.08:02:02.55#ibcon#cleared, iclass 39 cls_cnt 0 2006.218.08:02:02.55$vc4f8/vabw=wide 2006.218.08:02:02.55#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.218.08:02:02.55#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.218.08:02:02.55#ibcon#ireg 8 cls_cnt 0 2006.218.08:02:02.55#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.218.08:02:02.55#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.218.08:02:02.55#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.218.08:02:02.55#ibcon#enter wrdev, iclass 3, count 0 2006.218.08:02:02.55#ibcon#first serial, iclass 3, count 0 2006.218.08:02:02.55#ibcon#enter sib2, iclass 3, count 0 2006.218.08:02:02.55#ibcon#flushed, iclass 3, count 0 2006.218.08:02:02.55#ibcon#about to write, iclass 3, count 0 2006.218.08:02:02.55#ibcon#wrote, iclass 3, count 0 2006.218.08:02:02.55#ibcon#about to read 3, iclass 3, count 0 2006.218.08:02:02.57#ibcon#read 3, iclass 3, count 0 2006.218.08:02:02.57#ibcon#about to read 4, iclass 3, count 0 2006.218.08:02:02.57#ibcon#read 4, iclass 3, count 0 2006.218.08:02:02.57#ibcon#about to read 5, iclass 3, count 0 2006.218.08:02:02.57#ibcon#read 5, iclass 3, count 0 2006.218.08:02:02.57#ibcon#about to read 6, iclass 3, count 0 2006.218.08:02:02.57#ibcon#read 6, iclass 3, count 0 2006.218.08:02:02.57#ibcon#end of sib2, iclass 3, count 0 2006.218.08:02:02.57#ibcon#*mode == 0, iclass 3, count 0 2006.218.08:02:02.57#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.218.08:02:02.57#ibcon#[25=BW32\r\n] 2006.218.08:02:02.57#ibcon#*before write, iclass 3, count 0 2006.218.08:02:02.57#ibcon#enter sib2, iclass 3, count 0 2006.218.08:02:02.57#ibcon#flushed, iclass 3, count 0 2006.218.08:02:02.57#ibcon#about to write, iclass 3, count 0 2006.218.08:02:02.57#ibcon#wrote, iclass 3, count 0 2006.218.08:02:02.57#ibcon#about to read 3, iclass 3, count 0 2006.218.08:02:02.60#ibcon#read 3, iclass 3, count 0 2006.218.08:02:02.60#ibcon#about to read 4, iclass 3, count 0 2006.218.08:02:02.60#ibcon#read 4, iclass 3, count 0 2006.218.08:02:02.60#ibcon#about to read 5, iclass 3, count 0 2006.218.08:02:02.60#ibcon#read 5, iclass 3, count 0 2006.218.08:02:02.60#ibcon#about to read 6, iclass 3, count 0 2006.218.08:02:02.60#ibcon#read 6, iclass 3, count 0 2006.218.08:02:02.60#ibcon#end of sib2, iclass 3, count 0 2006.218.08:02:02.60#ibcon#*after write, iclass 3, count 0 2006.218.08:02:02.60#ibcon#*before return 0, iclass 3, count 0 2006.218.08:02:02.60#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.218.08:02:02.60#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.218.08:02:02.60#ibcon#about to clear, iclass 3 cls_cnt 0 2006.218.08:02:02.60#ibcon#cleared, iclass 3 cls_cnt 0 2006.218.08:02:02.60$vc4f8/vbbw=wide 2006.218.08:02:02.60#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.218.08:02:02.60#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.218.08:02:02.60#ibcon#ireg 8 cls_cnt 0 2006.218.08:02:02.60#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.218.08:02:02.68#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.218.08:02:02.68#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.218.08:02:02.68#ibcon#enter wrdev, iclass 5, count 0 2006.218.08:02:02.68#ibcon#first serial, iclass 5, count 0 2006.218.08:02:02.68#ibcon#enter sib2, iclass 5, count 0 2006.218.08:02:02.68#ibcon#flushed, iclass 5, count 0 2006.218.08:02:02.68#ibcon#about to write, iclass 5, count 0 2006.218.08:02:02.68#ibcon#wrote, iclass 5, count 0 2006.218.08:02:02.68#ibcon#about to read 3, iclass 5, count 0 2006.218.08:02:02.69#ibcon#read 3, iclass 5, count 0 2006.218.08:02:02.69#ibcon#about to read 4, iclass 5, count 0 2006.218.08:02:02.69#ibcon#read 4, iclass 5, count 0 2006.218.08:02:02.69#ibcon#about to read 5, iclass 5, count 0 2006.218.08:02:02.69#ibcon#read 5, iclass 5, count 0 2006.218.08:02:02.69#ibcon#about to read 6, iclass 5, count 0 2006.218.08:02:02.69#ibcon#read 6, iclass 5, count 0 2006.218.08:02:02.69#ibcon#end of sib2, iclass 5, count 0 2006.218.08:02:02.69#ibcon#*mode == 0, iclass 5, count 0 2006.218.08:02:02.69#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.218.08:02:02.69#ibcon#[27=BW32\r\n] 2006.218.08:02:02.69#ibcon#*before write, iclass 5, count 0 2006.218.08:02:02.69#ibcon#enter sib2, iclass 5, count 0 2006.218.08:02:02.69#ibcon#flushed, iclass 5, count 0 2006.218.08:02:02.69#ibcon#about to write, iclass 5, count 0 2006.218.08:02:02.69#ibcon#wrote, iclass 5, count 0 2006.218.08:02:02.69#ibcon#about to read 3, iclass 5, count 0 2006.218.08:02:02.72#ibcon#read 3, iclass 5, count 0 2006.218.08:02:02.72#ibcon#about to read 4, iclass 5, count 0 2006.218.08:02:02.72#ibcon#read 4, iclass 5, count 0 2006.218.08:02:02.72#ibcon#about to read 5, iclass 5, count 0 2006.218.08:02:02.72#ibcon#read 5, iclass 5, count 0 2006.218.08:02:02.72#ibcon#about to read 6, iclass 5, count 0 2006.218.08:02:02.72#ibcon#read 6, iclass 5, count 0 2006.218.08:02:02.72#ibcon#end of sib2, iclass 5, count 0 2006.218.08:02:02.72#ibcon#*after write, iclass 5, count 0 2006.218.08:02:02.72#ibcon#*before return 0, iclass 5, count 0 2006.218.08:02:02.72#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.218.08:02:02.72#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.218.08:02:02.72#ibcon#about to clear, iclass 5 cls_cnt 0 2006.218.08:02:02.72#ibcon#cleared, iclass 5 cls_cnt 0 2006.218.08:02:02.72$4f8m12a/ifd4f 2006.218.08:02:02.72$ifd4f/lo= 2006.218.08:02:02.72$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.218.08:02:02.72$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.218.08:02:02.72$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.218.08:02:02.72$ifd4f/patch= 2006.218.08:02:02.72$ifd4f/patch=lo1,a1,a2,a3,a4 2006.218.08:02:02.72$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.218.08:02:02.72$ifd4f/patch=lo3,a5,a6,a7,a8 2006.218.08:02:02.72$4f8m12a/"form=m,16.000,1:2 2006.218.08:02:02.72$4f8m12a/"tpicd 2006.218.08:02:02.72$4f8m12a/echo=off 2006.218.08:02:02.72$4f8m12a/xlog=off 2006.218.08:02:02.72:!2006.218.08:02:30 2006.218.08:02:16.13#trakl#Source acquired 2006.218.08:02:18.13#flagr#flagr/antenna,acquired 2006.218.08:02:30.00:preob 2006.218.08:02:31.13/onsource/TRACKING 2006.218.08:02:31.13:!2006.218.08:02:40 2006.218.08:02:40.00:data_valid=on 2006.218.08:02:40.00:midob 2006.218.08:02:40.13/onsource/TRACKING 2006.218.08:02:40.13/wx/31.00,1007.5,73 2006.218.08:02:40.26/cable/+6.3849E-03 2006.218.08:02:41.35/va/01,05,usb,yes,42,44 2006.218.08:02:41.35/va/02,04,usb,yes,40,41 2006.218.08:02:41.35/va/03,04,usb,yes,37,38 2006.218.08:02:41.35/va/04,04,usb,yes,42,45 2006.218.08:02:41.35/va/05,07,usb,yes,46,49 2006.218.08:02:41.35/va/06,06,usb,yes,45,45 2006.218.08:02:41.35/va/07,06,usb,yes,45,45 2006.218.08:02:41.35/va/08,07,usb,yes,43,42 2006.218.08:02:41.58/valo/01,532.99,yes,locked 2006.218.08:02:41.58/valo/02,572.99,yes,locked 2006.218.08:02:41.58/valo/03,672.99,yes,locked 2006.218.08:02:41.58/valo/04,832.99,yes,locked 2006.218.08:02:41.58/valo/05,652.99,yes,locked 2006.218.08:02:41.58/valo/06,772.99,yes,locked 2006.218.08:02:41.58/valo/07,832.99,yes,locked 2006.218.08:02:41.58/valo/08,852.99,yes,locked 2006.218.08:02:42.67/vb/01,04,usb,yes,36,34 2006.218.08:02:42.67/vb/02,04,usb,yes,38,39 2006.218.08:02:42.67/vb/03,04,usb,yes,34,38 2006.218.08:02:42.67/vb/04,04,usb,yes,35,35 2006.218.08:02:42.67/vb/05,04,usb,yes,33,38 2006.218.08:02:42.67/vb/06,04,usb,yes,35,38 2006.218.08:02:42.67/vb/07,04,usb,yes,37,37 2006.218.08:02:42.67/vb/08,04,usb,yes,34,38 2006.218.08:02:42.90/vblo/01,632.99,yes,locked 2006.218.08:02:42.90/vblo/02,640.99,yes,locked 2006.218.08:02:42.90/vblo/03,656.99,yes,locked 2006.218.08:02:42.90/vblo/04,712.99,yes,locked 2006.218.08:02:42.90/vblo/05,744.99,yes,locked 2006.218.08:02:42.90/vblo/06,752.99,yes,locked 2006.218.08:02:42.90/vblo/07,734.99,yes,locked 2006.218.08:02:42.90/vblo/08,744.99,yes,locked 2006.218.08:02:43.05/vabw/8 2006.218.08:02:43.20/vbbw/8 2006.218.08:02:43.29/xfe/off,on,15.5 2006.218.08:02:43.67/ifatt/23,28,28,28 2006.218.08:02:44.07/fmout-gps/S +4.68E-07 2006.218.08:02:44.11:!2006.218.08:03:40 2006.218.08:03:40.00:data_valid=off 2006.218.08:03:40.00:postob 2006.218.08:03:40.08/cable/+6.3849E-03 2006.218.08:03:40.09/wx/31.00,1007.5,72 2006.218.08:03:41.07/fmout-gps/S +4.69E-07 2006.218.08:03:41.07:scan_name=218-0804,k06218,60 2006.218.08:03:41.08:source=4c39.25,092703.01,390220.9,2000.0,cw 2006.218.08:03:41.13#flagr#flagr/antenna,new-source 2006.218.08:03:42.14:checkk5 2006.218.08:03:42.49/chk_autoobs//k5ts1/ autoobs is running! 2006.218.08:03:42.86/chk_autoobs//k5ts2/ autoobs is running! 2006.218.08:03:43.23/chk_autoobs//k5ts3/ autoobs is running! 2006.218.08:03:43.61/chk_autoobs//k5ts4/ autoobs is running! 2006.218.08:03:43.97/chk_obsdata//k5ts1/T2180802??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.08:03:44.34/chk_obsdata//k5ts2/T2180802??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.08:03:44.71/chk_obsdata//k5ts3/T2180802??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.08:03:45.09/chk_obsdata//k5ts4/T2180802??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.08:03:45.78/k5log//k5ts1_log_newline 2006.218.08:03:46.46/k5log//k5ts2_log_newline 2006.218.08:03:47.15/k5log//k5ts3_log_newline 2006.218.08:03:47.83/k5log//k5ts4_log_newline 2006.218.08:03:47.85/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.218.08:03:47.86:4f8m12a=2 2006.218.08:03:47.86$4f8m12a/echo=on 2006.218.08:03:47.86$4f8m12a/pcalon 2006.218.08:03:47.86$pcalon/"no phase cal control is implemented here 2006.218.08:03:47.86$4f8m12a/"tpicd=stop 2006.218.08:03:47.86$4f8m12a/vc4f8 2006.218.08:03:47.86$vc4f8/valo=1,532.99 2006.218.08:03:47.86#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.218.08:03:47.86#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.218.08:03:47.86#ibcon#ireg 17 cls_cnt 0 2006.218.08:03:47.86#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.218.08:03:47.86#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.218.08:03:47.86#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.218.08:03:47.86#ibcon#enter wrdev, iclass 15, count 0 2006.218.08:03:47.86#ibcon#first serial, iclass 15, count 0 2006.218.08:03:47.86#ibcon#enter sib2, iclass 15, count 0 2006.218.08:03:47.86#ibcon#flushed, iclass 15, count 0 2006.218.08:03:47.86#ibcon#about to write, iclass 15, count 0 2006.218.08:03:47.86#ibcon#wrote, iclass 15, count 0 2006.218.08:03:47.86#ibcon#about to read 3, iclass 15, count 0 2006.218.08:03:47.90#ibcon#read 3, iclass 15, count 0 2006.218.08:03:47.90#ibcon#about to read 4, iclass 15, count 0 2006.218.08:03:47.90#ibcon#read 4, iclass 15, count 0 2006.218.08:03:47.90#ibcon#about to read 5, iclass 15, count 0 2006.218.08:03:47.90#ibcon#read 5, iclass 15, count 0 2006.218.08:03:47.90#ibcon#about to read 6, iclass 15, count 0 2006.218.08:03:47.90#ibcon#read 6, iclass 15, count 0 2006.218.08:03:47.90#ibcon#end of sib2, iclass 15, count 0 2006.218.08:03:47.90#ibcon#*mode == 0, iclass 15, count 0 2006.218.08:03:47.90#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.218.08:03:47.90#ibcon#[26=FRQ=01,532.99\r\n] 2006.218.08:03:47.90#ibcon#*before write, iclass 15, count 0 2006.218.08:03:47.90#ibcon#enter sib2, iclass 15, count 0 2006.218.08:03:47.90#ibcon#flushed, iclass 15, count 0 2006.218.08:03:47.90#ibcon#about to write, iclass 15, count 0 2006.218.08:03:47.90#ibcon#wrote, iclass 15, count 0 2006.218.08:03:47.90#ibcon#about to read 3, iclass 15, count 0 2006.218.08:03:47.94#abcon#{5=INTERFACE CLEAR} 2006.218.08:03:47.94#ibcon#read 3, iclass 15, count 0 2006.218.08:03:47.94#ibcon#about to read 4, iclass 15, count 0 2006.218.08:03:47.94#ibcon#read 4, iclass 15, count 0 2006.218.08:03:47.94#ibcon#about to read 5, iclass 15, count 0 2006.218.08:03:47.94#ibcon#read 5, iclass 15, count 0 2006.218.08:03:47.94#ibcon#about to read 6, iclass 15, count 0 2006.218.08:03:47.94#ibcon#read 6, iclass 15, count 0 2006.218.08:03:47.94#ibcon#end of sib2, iclass 15, count 0 2006.218.08:03:47.94#ibcon#*after write, iclass 15, count 0 2006.218.08:03:47.94#ibcon#*before return 0, iclass 15, count 0 2006.218.08:03:47.94#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.218.08:03:47.94#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.218.08:03:47.94#ibcon#about to clear, iclass 15 cls_cnt 0 2006.218.08:03:47.94#ibcon#cleared, iclass 15 cls_cnt 0 2006.218.08:03:47.94$vc4f8/va=1,5 2006.218.08:03:47.94#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.218.08:03:47.94#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.218.08:03:47.94#ibcon#ireg 11 cls_cnt 2 2006.218.08:03:47.94#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.218.08:03:47.94#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.218.08:03:47.94#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.218.08:03:47.94#ibcon#enter wrdev, iclass 19, count 2 2006.218.08:03:47.94#ibcon#first serial, iclass 19, count 2 2006.218.08:03:47.94#ibcon#enter sib2, iclass 19, count 2 2006.218.08:03:47.94#ibcon#flushed, iclass 19, count 2 2006.218.08:03:47.94#ibcon#about to write, iclass 19, count 2 2006.218.08:03:47.94#ibcon#wrote, iclass 19, count 2 2006.218.08:03:47.94#ibcon#about to read 3, iclass 19, count 2 2006.218.08:03:47.96#ibcon#read 3, iclass 19, count 2 2006.218.08:03:47.96#ibcon#about to read 4, iclass 19, count 2 2006.218.08:03:47.96#ibcon#read 4, iclass 19, count 2 2006.218.08:03:47.96#ibcon#about to read 5, iclass 19, count 2 2006.218.08:03:47.96#ibcon#read 5, iclass 19, count 2 2006.218.08:03:47.96#ibcon#about to read 6, iclass 19, count 2 2006.218.08:03:47.96#ibcon#read 6, iclass 19, count 2 2006.218.08:03:47.96#ibcon#end of sib2, iclass 19, count 2 2006.218.08:03:47.96#ibcon#*mode == 0, iclass 19, count 2 2006.218.08:03:47.96#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.218.08:03:47.96#ibcon#[25=AT01-05\r\n] 2006.218.08:03:47.96#ibcon#*before write, iclass 19, count 2 2006.218.08:03:47.96#ibcon#enter sib2, iclass 19, count 2 2006.218.08:03:47.96#ibcon#flushed, iclass 19, count 2 2006.218.08:03:47.96#ibcon#about to write, iclass 19, count 2 2006.218.08:03:47.96#ibcon#wrote, iclass 19, count 2 2006.218.08:03:47.96#ibcon#about to read 3, iclass 19, count 2 2006.218.08:03:47.99#ibcon#read 3, iclass 19, count 2 2006.218.08:03:47.99#ibcon#about to read 4, iclass 19, count 2 2006.218.08:03:47.99#ibcon#read 4, iclass 19, count 2 2006.218.08:03:47.99#ibcon#about to read 5, iclass 19, count 2 2006.218.08:03:47.99#ibcon#read 5, iclass 19, count 2 2006.218.08:03:47.99#ibcon#about to read 6, iclass 19, count 2 2006.218.08:03:47.99#ibcon#read 6, iclass 19, count 2 2006.218.08:03:47.99#ibcon#end of sib2, iclass 19, count 2 2006.218.08:03:47.99#ibcon#*after write, iclass 19, count 2 2006.218.08:03:47.99#ibcon#*before return 0, iclass 19, count 2 2006.218.08:03:47.99#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.218.08:03:47.99#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.218.08:03:47.99#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.218.08:03:47.99#ibcon#ireg 7 cls_cnt 0 2006.218.08:03:47.99#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.218.08:03:48.00#abcon#[5=S1D000X0/0*\r\n] 2006.218.08:03:48.11#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.218.08:03:48.11#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.218.08:03:48.11#ibcon#enter wrdev, iclass 19, count 0 2006.218.08:03:48.11#ibcon#first serial, iclass 19, count 0 2006.218.08:03:48.11#ibcon#enter sib2, iclass 19, count 0 2006.218.08:03:48.11#ibcon#flushed, iclass 19, count 0 2006.218.08:03:48.11#ibcon#about to write, iclass 19, count 0 2006.218.08:03:48.11#ibcon#wrote, iclass 19, count 0 2006.218.08:03:48.11#ibcon#about to read 3, iclass 19, count 0 2006.218.08:03:48.13#ibcon#read 3, iclass 19, count 0 2006.218.08:03:48.13#ibcon#about to read 4, iclass 19, count 0 2006.218.08:03:48.13#ibcon#read 4, iclass 19, count 0 2006.218.08:03:48.13#ibcon#about to read 5, iclass 19, count 0 2006.218.08:03:48.13#ibcon#read 5, iclass 19, count 0 2006.218.08:03:48.13#ibcon#about to read 6, iclass 19, count 0 2006.218.08:03:48.13#ibcon#read 6, iclass 19, count 0 2006.218.08:03:48.13#ibcon#end of sib2, iclass 19, count 0 2006.218.08:03:48.13#ibcon#*mode == 0, iclass 19, count 0 2006.218.08:03:48.13#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.218.08:03:48.13#ibcon#[25=USB\r\n] 2006.218.08:03:48.13#ibcon#*before write, iclass 19, count 0 2006.218.08:03:48.13#ibcon#enter sib2, iclass 19, count 0 2006.218.08:03:48.13#ibcon#flushed, iclass 19, count 0 2006.218.08:03:48.13#ibcon#about to write, iclass 19, count 0 2006.218.08:03:48.13#ibcon#wrote, iclass 19, count 0 2006.218.08:03:48.13#ibcon#about to read 3, iclass 19, count 0 2006.218.08:03:48.16#ibcon#read 3, iclass 19, count 0 2006.218.08:03:48.16#ibcon#about to read 4, iclass 19, count 0 2006.218.08:03:48.16#ibcon#read 4, iclass 19, count 0 2006.218.08:03:48.16#ibcon#about to read 5, iclass 19, count 0 2006.218.08:03:48.16#ibcon#read 5, iclass 19, count 0 2006.218.08:03:48.16#ibcon#about to read 6, iclass 19, count 0 2006.218.08:03:48.16#ibcon#read 6, iclass 19, count 0 2006.218.08:03:48.16#ibcon#end of sib2, iclass 19, count 0 2006.218.08:03:48.16#ibcon#*after write, iclass 19, count 0 2006.218.08:03:48.16#ibcon#*before return 0, iclass 19, count 0 2006.218.08:03:48.16#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.218.08:03:48.16#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.218.08:03:48.16#ibcon#about to clear, iclass 19 cls_cnt 0 2006.218.08:03:48.16#ibcon#cleared, iclass 19 cls_cnt 0 2006.218.08:03:48.16$vc4f8/valo=2,572.99 2006.218.08:03:48.16#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.218.08:03:48.16#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.218.08:03:48.16#ibcon#ireg 17 cls_cnt 0 2006.218.08:03:48.16#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.218.08:03:48.16#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.218.08:03:48.16#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.218.08:03:48.16#ibcon#enter wrdev, iclass 22, count 0 2006.218.08:03:48.16#ibcon#first serial, iclass 22, count 0 2006.218.08:03:48.16#ibcon#enter sib2, iclass 22, count 0 2006.218.08:03:48.16#ibcon#flushed, iclass 22, count 0 2006.218.08:03:48.16#ibcon#about to write, iclass 22, count 0 2006.218.08:03:48.16#ibcon#wrote, iclass 22, count 0 2006.218.08:03:48.16#ibcon#about to read 3, iclass 22, count 0 2006.218.08:03:48.19#ibcon#read 3, iclass 22, count 0 2006.218.08:03:48.19#ibcon#about to read 4, iclass 22, count 0 2006.218.08:03:48.19#ibcon#read 4, iclass 22, count 0 2006.218.08:03:48.19#ibcon#about to read 5, iclass 22, count 0 2006.218.08:03:48.19#ibcon#read 5, iclass 22, count 0 2006.218.08:03:48.19#ibcon#about to read 6, iclass 22, count 0 2006.218.08:03:48.19#ibcon#read 6, iclass 22, count 0 2006.218.08:03:48.19#ibcon#end of sib2, iclass 22, count 0 2006.218.08:03:48.19#ibcon#*mode == 0, iclass 22, count 0 2006.218.08:03:48.19#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.218.08:03:48.19#ibcon#[26=FRQ=02,572.99\r\n] 2006.218.08:03:48.19#ibcon#*before write, iclass 22, count 0 2006.218.08:03:48.19#ibcon#enter sib2, iclass 22, count 0 2006.218.08:03:48.19#ibcon#flushed, iclass 22, count 0 2006.218.08:03:48.19#ibcon#about to write, iclass 22, count 0 2006.218.08:03:48.19#ibcon#wrote, iclass 22, count 0 2006.218.08:03:48.19#ibcon#about to read 3, iclass 22, count 0 2006.218.08:03:48.23#ibcon#read 3, iclass 22, count 0 2006.218.08:03:48.23#ibcon#about to read 4, iclass 22, count 0 2006.218.08:03:48.23#ibcon#read 4, iclass 22, count 0 2006.218.08:03:48.23#ibcon#about to read 5, iclass 22, count 0 2006.218.08:03:48.23#ibcon#read 5, iclass 22, count 0 2006.218.08:03:48.23#ibcon#about to read 6, iclass 22, count 0 2006.218.08:03:48.23#ibcon#read 6, iclass 22, count 0 2006.218.08:03:48.23#ibcon#end of sib2, iclass 22, count 0 2006.218.08:03:48.23#ibcon#*after write, iclass 22, count 0 2006.218.08:03:48.23#ibcon#*before return 0, iclass 22, count 0 2006.218.08:03:48.23#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.218.08:03:48.23#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.218.08:03:48.23#ibcon#about to clear, iclass 22 cls_cnt 0 2006.218.08:03:48.23#ibcon#cleared, iclass 22 cls_cnt 0 2006.218.08:03:48.23$vc4f8/va=2,4 2006.218.08:03:48.23#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.218.08:03:48.23#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.218.08:03:48.23#ibcon#ireg 11 cls_cnt 2 2006.218.08:03:48.23#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.218.08:03:48.28#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.218.08:03:48.28#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.218.08:03:48.28#ibcon#enter wrdev, iclass 24, count 2 2006.218.08:03:48.28#ibcon#first serial, iclass 24, count 2 2006.218.08:03:48.28#ibcon#enter sib2, iclass 24, count 2 2006.218.08:03:48.28#ibcon#flushed, iclass 24, count 2 2006.218.08:03:48.28#ibcon#about to write, iclass 24, count 2 2006.218.08:03:48.28#ibcon#wrote, iclass 24, count 2 2006.218.08:03:48.28#ibcon#about to read 3, iclass 24, count 2 2006.218.08:03:48.30#ibcon#read 3, iclass 24, count 2 2006.218.08:03:48.30#ibcon#about to read 4, iclass 24, count 2 2006.218.08:03:48.30#ibcon#read 4, iclass 24, count 2 2006.218.08:03:48.30#ibcon#about to read 5, iclass 24, count 2 2006.218.08:03:48.30#ibcon#read 5, iclass 24, count 2 2006.218.08:03:48.30#ibcon#about to read 6, iclass 24, count 2 2006.218.08:03:48.30#ibcon#read 6, iclass 24, count 2 2006.218.08:03:48.30#ibcon#end of sib2, iclass 24, count 2 2006.218.08:03:48.30#ibcon#*mode == 0, iclass 24, count 2 2006.218.08:03:48.30#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.218.08:03:48.30#ibcon#[25=AT02-04\r\n] 2006.218.08:03:48.30#ibcon#*before write, iclass 24, count 2 2006.218.08:03:48.30#ibcon#enter sib2, iclass 24, count 2 2006.218.08:03:48.30#ibcon#flushed, iclass 24, count 2 2006.218.08:03:48.30#ibcon#about to write, iclass 24, count 2 2006.218.08:03:48.30#ibcon#wrote, iclass 24, count 2 2006.218.08:03:48.30#ibcon#about to read 3, iclass 24, count 2 2006.218.08:03:48.33#ibcon#read 3, iclass 24, count 2 2006.218.08:03:48.33#ibcon#about to read 4, iclass 24, count 2 2006.218.08:03:48.33#ibcon#read 4, iclass 24, count 2 2006.218.08:03:48.33#ibcon#about to read 5, iclass 24, count 2 2006.218.08:03:48.33#ibcon#read 5, iclass 24, count 2 2006.218.08:03:48.33#ibcon#about to read 6, iclass 24, count 2 2006.218.08:03:48.33#ibcon#read 6, iclass 24, count 2 2006.218.08:03:48.33#ibcon#end of sib2, iclass 24, count 2 2006.218.08:03:48.33#ibcon#*after write, iclass 24, count 2 2006.218.08:03:48.33#ibcon#*before return 0, iclass 24, count 2 2006.218.08:03:48.33#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.218.08:03:48.33#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.218.08:03:48.33#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.218.08:03:48.33#ibcon#ireg 7 cls_cnt 0 2006.218.08:03:48.33#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.218.08:03:48.45#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.218.08:03:48.45#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.218.08:03:48.45#ibcon#enter wrdev, iclass 24, count 0 2006.218.08:03:48.45#ibcon#first serial, iclass 24, count 0 2006.218.08:03:48.45#ibcon#enter sib2, iclass 24, count 0 2006.218.08:03:48.45#ibcon#flushed, iclass 24, count 0 2006.218.08:03:48.45#ibcon#about to write, iclass 24, count 0 2006.218.08:03:48.45#ibcon#wrote, iclass 24, count 0 2006.218.08:03:48.45#ibcon#about to read 3, iclass 24, count 0 2006.218.08:03:48.47#ibcon#read 3, iclass 24, count 0 2006.218.08:03:48.47#ibcon#about to read 4, iclass 24, count 0 2006.218.08:03:48.47#ibcon#read 4, iclass 24, count 0 2006.218.08:03:48.47#ibcon#about to read 5, iclass 24, count 0 2006.218.08:03:48.47#ibcon#read 5, iclass 24, count 0 2006.218.08:03:48.47#ibcon#about to read 6, iclass 24, count 0 2006.218.08:03:48.47#ibcon#read 6, iclass 24, count 0 2006.218.08:03:48.47#ibcon#end of sib2, iclass 24, count 0 2006.218.08:03:48.47#ibcon#*mode == 0, iclass 24, count 0 2006.218.08:03:48.47#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.218.08:03:48.47#ibcon#[25=USB\r\n] 2006.218.08:03:48.47#ibcon#*before write, iclass 24, count 0 2006.218.08:03:48.47#ibcon#enter sib2, iclass 24, count 0 2006.218.08:03:48.47#ibcon#flushed, iclass 24, count 0 2006.218.08:03:48.47#ibcon#about to write, iclass 24, count 0 2006.218.08:03:48.47#ibcon#wrote, iclass 24, count 0 2006.218.08:03:48.47#ibcon#about to read 3, iclass 24, count 0 2006.218.08:03:48.50#ibcon#read 3, iclass 24, count 0 2006.218.08:03:48.50#ibcon#about to read 4, iclass 24, count 0 2006.218.08:03:48.50#ibcon#read 4, iclass 24, count 0 2006.218.08:03:48.50#ibcon#about to read 5, iclass 24, count 0 2006.218.08:03:48.50#ibcon#read 5, iclass 24, count 0 2006.218.08:03:48.50#ibcon#about to read 6, iclass 24, count 0 2006.218.08:03:48.50#ibcon#read 6, iclass 24, count 0 2006.218.08:03:48.50#ibcon#end of sib2, iclass 24, count 0 2006.218.08:03:48.50#ibcon#*after write, iclass 24, count 0 2006.218.08:03:48.50#ibcon#*before return 0, iclass 24, count 0 2006.218.08:03:48.50#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.218.08:03:48.50#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.218.08:03:48.50#ibcon#about to clear, iclass 24 cls_cnt 0 2006.218.08:03:48.50#ibcon#cleared, iclass 24 cls_cnt 0 2006.218.08:03:48.50$vc4f8/valo=3,672.99 2006.218.08:03:48.50#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.218.08:03:48.50#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.218.08:03:48.50#ibcon#ireg 17 cls_cnt 0 2006.218.08:03:48.50#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.218.08:03:48.50#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.218.08:03:48.50#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.218.08:03:48.50#ibcon#enter wrdev, iclass 26, count 0 2006.218.08:03:48.50#ibcon#first serial, iclass 26, count 0 2006.218.08:03:48.50#ibcon#enter sib2, iclass 26, count 0 2006.218.08:03:48.50#ibcon#flushed, iclass 26, count 0 2006.218.08:03:48.50#ibcon#about to write, iclass 26, count 0 2006.218.08:03:48.50#ibcon#wrote, iclass 26, count 0 2006.218.08:03:48.50#ibcon#about to read 3, iclass 26, count 0 2006.218.08:03:48.53#ibcon#read 3, iclass 26, count 0 2006.218.08:03:48.53#ibcon#about to read 4, iclass 26, count 0 2006.218.08:03:48.53#ibcon#read 4, iclass 26, count 0 2006.218.08:03:48.53#ibcon#about to read 5, iclass 26, count 0 2006.218.08:03:48.53#ibcon#read 5, iclass 26, count 0 2006.218.08:03:48.53#ibcon#about to read 6, iclass 26, count 0 2006.218.08:03:48.53#ibcon#read 6, iclass 26, count 0 2006.218.08:03:48.53#ibcon#end of sib2, iclass 26, count 0 2006.218.08:03:48.53#ibcon#*mode == 0, iclass 26, count 0 2006.218.08:03:48.53#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.218.08:03:48.53#ibcon#[26=FRQ=03,672.99\r\n] 2006.218.08:03:48.53#ibcon#*before write, iclass 26, count 0 2006.218.08:03:48.53#ibcon#enter sib2, iclass 26, count 0 2006.218.08:03:48.53#ibcon#flushed, iclass 26, count 0 2006.218.08:03:48.53#ibcon#about to write, iclass 26, count 0 2006.218.08:03:48.53#ibcon#wrote, iclass 26, count 0 2006.218.08:03:48.53#ibcon#about to read 3, iclass 26, count 0 2006.218.08:03:48.57#ibcon#read 3, iclass 26, count 0 2006.218.08:03:48.57#ibcon#about to read 4, iclass 26, count 0 2006.218.08:03:48.57#ibcon#read 4, iclass 26, count 0 2006.218.08:03:48.57#ibcon#about to read 5, iclass 26, count 0 2006.218.08:03:48.57#ibcon#read 5, iclass 26, count 0 2006.218.08:03:48.57#ibcon#about to read 6, iclass 26, count 0 2006.218.08:03:48.57#ibcon#read 6, iclass 26, count 0 2006.218.08:03:48.57#ibcon#end of sib2, iclass 26, count 0 2006.218.08:03:48.57#ibcon#*after write, iclass 26, count 0 2006.218.08:03:48.57#ibcon#*before return 0, iclass 26, count 0 2006.218.08:03:48.57#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.218.08:03:48.57#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.218.08:03:48.57#ibcon#about to clear, iclass 26 cls_cnt 0 2006.218.08:03:48.57#ibcon#cleared, iclass 26 cls_cnt 0 2006.218.08:03:48.57$vc4f8/va=3,4 2006.218.08:03:48.57#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.218.08:03:48.57#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.218.08:03:48.57#ibcon#ireg 11 cls_cnt 2 2006.218.08:03:48.57#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.218.08:03:48.62#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.218.08:03:48.62#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.218.08:03:48.62#ibcon#enter wrdev, iclass 28, count 2 2006.218.08:03:48.62#ibcon#first serial, iclass 28, count 2 2006.218.08:03:48.62#ibcon#enter sib2, iclass 28, count 2 2006.218.08:03:48.62#ibcon#flushed, iclass 28, count 2 2006.218.08:03:48.62#ibcon#about to write, iclass 28, count 2 2006.218.08:03:48.62#ibcon#wrote, iclass 28, count 2 2006.218.08:03:48.62#ibcon#about to read 3, iclass 28, count 2 2006.218.08:03:48.64#ibcon#read 3, iclass 28, count 2 2006.218.08:03:48.64#ibcon#about to read 4, iclass 28, count 2 2006.218.08:03:48.64#ibcon#read 4, iclass 28, count 2 2006.218.08:03:48.64#ibcon#about to read 5, iclass 28, count 2 2006.218.08:03:48.64#ibcon#read 5, iclass 28, count 2 2006.218.08:03:48.64#ibcon#about to read 6, iclass 28, count 2 2006.218.08:03:48.64#ibcon#read 6, iclass 28, count 2 2006.218.08:03:48.64#ibcon#end of sib2, iclass 28, count 2 2006.218.08:03:48.64#ibcon#*mode == 0, iclass 28, count 2 2006.218.08:03:48.64#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.218.08:03:48.64#ibcon#[25=AT03-04\r\n] 2006.218.08:03:48.64#ibcon#*before write, iclass 28, count 2 2006.218.08:03:48.64#ibcon#enter sib2, iclass 28, count 2 2006.218.08:03:48.64#ibcon#flushed, iclass 28, count 2 2006.218.08:03:48.64#ibcon#about to write, iclass 28, count 2 2006.218.08:03:48.64#ibcon#wrote, iclass 28, count 2 2006.218.08:03:48.64#ibcon#about to read 3, iclass 28, count 2 2006.218.08:03:48.67#ibcon#read 3, iclass 28, count 2 2006.218.08:03:48.67#ibcon#about to read 4, iclass 28, count 2 2006.218.08:03:48.67#ibcon#read 4, iclass 28, count 2 2006.218.08:03:48.67#ibcon#about to read 5, iclass 28, count 2 2006.218.08:03:48.67#ibcon#read 5, iclass 28, count 2 2006.218.08:03:48.67#ibcon#about to read 6, iclass 28, count 2 2006.218.08:03:48.67#ibcon#read 6, iclass 28, count 2 2006.218.08:03:48.67#ibcon#end of sib2, iclass 28, count 2 2006.218.08:03:48.67#ibcon#*after write, iclass 28, count 2 2006.218.08:03:48.67#ibcon#*before return 0, iclass 28, count 2 2006.218.08:03:48.67#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.218.08:03:48.67#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.218.08:03:48.67#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.218.08:03:48.67#ibcon#ireg 7 cls_cnt 0 2006.218.08:03:48.67#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.218.08:03:48.79#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.218.08:03:48.79#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.218.08:03:48.79#ibcon#enter wrdev, iclass 28, count 0 2006.218.08:03:48.79#ibcon#first serial, iclass 28, count 0 2006.218.08:03:48.79#ibcon#enter sib2, iclass 28, count 0 2006.218.08:03:48.79#ibcon#flushed, iclass 28, count 0 2006.218.08:03:48.79#ibcon#about to write, iclass 28, count 0 2006.218.08:03:48.79#ibcon#wrote, iclass 28, count 0 2006.218.08:03:48.79#ibcon#about to read 3, iclass 28, count 0 2006.218.08:03:48.81#ibcon#read 3, iclass 28, count 0 2006.218.08:03:48.81#ibcon#about to read 4, iclass 28, count 0 2006.218.08:03:48.81#ibcon#read 4, iclass 28, count 0 2006.218.08:03:48.81#ibcon#about to read 5, iclass 28, count 0 2006.218.08:03:48.81#ibcon#read 5, iclass 28, count 0 2006.218.08:03:48.81#ibcon#about to read 6, iclass 28, count 0 2006.218.08:03:48.81#ibcon#read 6, iclass 28, count 0 2006.218.08:03:48.81#ibcon#end of sib2, iclass 28, count 0 2006.218.08:03:48.81#ibcon#*mode == 0, iclass 28, count 0 2006.218.08:03:48.81#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.218.08:03:48.81#ibcon#[25=USB\r\n] 2006.218.08:03:48.81#ibcon#*before write, iclass 28, count 0 2006.218.08:03:48.81#ibcon#enter sib2, iclass 28, count 0 2006.218.08:03:48.81#ibcon#flushed, iclass 28, count 0 2006.218.08:03:48.81#ibcon#about to write, iclass 28, count 0 2006.218.08:03:48.81#ibcon#wrote, iclass 28, count 0 2006.218.08:03:48.81#ibcon#about to read 3, iclass 28, count 0 2006.218.08:03:48.84#ibcon#read 3, iclass 28, count 0 2006.218.08:03:48.84#ibcon#about to read 4, iclass 28, count 0 2006.218.08:03:48.84#ibcon#read 4, iclass 28, count 0 2006.218.08:03:48.84#ibcon#about to read 5, iclass 28, count 0 2006.218.08:03:48.84#ibcon#read 5, iclass 28, count 0 2006.218.08:03:48.84#ibcon#about to read 6, iclass 28, count 0 2006.218.08:03:48.84#ibcon#read 6, iclass 28, count 0 2006.218.08:03:48.84#ibcon#end of sib2, iclass 28, count 0 2006.218.08:03:48.84#ibcon#*after write, iclass 28, count 0 2006.218.08:03:48.84#ibcon#*before return 0, iclass 28, count 0 2006.218.08:03:48.84#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.218.08:03:48.84#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.218.08:03:48.84#ibcon#about to clear, iclass 28 cls_cnt 0 2006.218.08:03:48.84#ibcon#cleared, iclass 28 cls_cnt 0 2006.218.08:03:48.84$vc4f8/valo=4,832.99 2006.218.08:03:48.84#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.218.08:03:48.84#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.218.08:03:48.84#ibcon#ireg 17 cls_cnt 0 2006.218.08:03:48.84#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.218.08:03:48.84#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.218.08:03:48.84#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.218.08:03:48.84#ibcon#enter wrdev, iclass 30, count 0 2006.218.08:03:48.84#ibcon#first serial, iclass 30, count 0 2006.218.08:03:48.84#ibcon#enter sib2, iclass 30, count 0 2006.218.08:03:48.84#ibcon#flushed, iclass 30, count 0 2006.218.08:03:48.84#ibcon#about to write, iclass 30, count 0 2006.218.08:03:48.84#ibcon#wrote, iclass 30, count 0 2006.218.08:03:48.84#ibcon#about to read 3, iclass 30, count 0 2006.218.08:03:48.87#ibcon#read 3, iclass 30, count 0 2006.218.08:03:48.87#ibcon#about to read 4, iclass 30, count 0 2006.218.08:03:48.87#ibcon#read 4, iclass 30, count 0 2006.218.08:03:48.87#ibcon#about to read 5, iclass 30, count 0 2006.218.08:03:48.87#ibcon#read 5, iclass 30, count 0 2006.218.08:03:48.87#ibcon#about to read 6, iclass 30, count 0 2006.218.08:03:48.87#ibcon#read 6, iclass 30, count 0 2006.218.08:03:48.87#ibcon#end of sib2, iclass 30, count 0 2006.218.08:03:48.87#ibcon#*mode == 0, iclass 30, count 0 2006.218.08:03:48.87#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.218.08:03:48.87#ibcon#[26=FRQ=04,832.99\r\n] 2006.218.08:03:48.87#ibcon#*before write, iclass 30, count 0 2006.218.08:03:48.87#ibcon#enter sib2, iclass 30, count 0 2006.218.08:03:48.87#ibcon#flushed, iclass 30, count 0 2006.218.08:03:48.87#ibcon#about to write, iclass 30, count 0 2006.218.08:03:48.87#ibcon#wrote, iclass 30, count 0 2006.218.08:03:48.87#ibcon#about to read 3, iclass 30, count 0 2006.218.08:03:48.91#ibcon#read 3, iclass 30, count 0 2006.218.08:03:48.91#ibcon#about to read 4, iclass 30, count 0 2006.218.08:03:48.91#ibcon#read 4, iclass 30, count 0 2006.218.08:03:48.91#ibcon#about to read 5, iclass 30, count 0 2006.218.08:03:48.91#ibcon#read 5, iclass 30, count 0 2006.218.08:03:48.91#ibcon#about to read 6, iclass 30, count 0 2006.218.08:03:48.91#ibcon#read 6, iclass 30, count 0 2006.218.08:03:48.91#ibcon#end of sib2, iclass 30, count 0 2006.218.08:03:48.91#ibcon#*after write, iclass 30, count 0 2006.218.08:03:48.91#ibcon#*before return 0, iclass 30, count 0 2006.218.08:03:48.91#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.218.08:03:48.91#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.218.08:03:48.91#ibcon#about to clear, iclass 30 cls_cnt 0 2006.218.08:03:48.91#ibcon#cleared, iclass 30 cls_cnt 0 2006.218.08:03:48.91$vc4f8/va=4,4 2006.218.08:03:48.91#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.218.08:03:48.91#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.218.08:03:48.91#ibcon#ireg 11 cls_cnt 2 2006.218.08:03:48.91#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.218.08:03:48.96#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.218.08:03:48.96#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.218.08:03:48.96#ibcon#enter wrdev, iclass 32, count 2 2006.218.08:03:48.96#ibcon#first serial, iclass 32, count 2 2006.218.08:03:48.96#ibcon#enter sib2, iclass 32, count 2 2006.218.08:03:48.96#ibcon#flushed, iclass 32, count 2 2006.218.08:03:48.96#ibcon#about to write, iclass 32, count 2 2006.218.08:03:48.96#ibcon#wrote, iclass 32, count 2 2006.218.08:03:48.96#ibcon#about to read 3, iclass 32, count 2 2006.218.08:03:48.98#ibcon#read 3, iclass 32, count 2 2006.218.08:03:48.98#ibcon#about to read 4, iclass 32, count 2 2006.218.08:03:48.98#ibcon#read 4, iclass 32, count 2 2006.218.08:03:48.98#ibcon#about to read 5, iclass 32, count 2 2006.218.08:03:48.98#ibcon#read 5, iclass 32, count 2 2006.218.08:03:48.98#ibcon#about to read 6, iclass 32, count 2 2006.218.08:03:48.98#ibcon#read 6, iclass 32, count 2 2006.218.08:03:48.98#ibcon#end of sib2, iclass 32, count 2 2006.218.08:03:48.98#ibcon#*mode == 0, iclass 32, count 2 2006.218.08:03:48.98#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.218.08:03:48.98#ibcon#[25=AT04-04\r\n] 2006.218.08:03:48.98#ibcon#*before write, iclass 32, count 2 2006.218.08:03:48.98#ibcon#enter sib2, iclass 32, count 2 2006.218.08:03:48.98#ibcon#flushed, iclass 32, count 2 2006.218.08:03:48.98#ibcon#about to write, iclass 32, count 2 2006.218.08:03:48.98#ibcon#wrote, iclass 32, count 2 2006.218.08:03:48.98#ibcon#about to read 3, iclass 32, count 2 2006.218.08:03:49.01#ibcon#read 3, iclass 32, count 2 2006.218.08:03:49.01#ibcon#about to read 4, iclass 32, count 2 2006.218.08:03:49.01#ibcon#read 4, iclass 32, count 2 2006.218.08:03:49.01#ibcon#about to read 5, iclass 32, count 2 2006.218.08:03:49.01#ibcon#read 5, iclass 32, count 2 2006.218.08:03:49.01#ibcon#about to read 6, iclass 32, count 2 2006.218.08:03:49.01#ibcon#read 6, iclass 32, count 2 2006.218.08:03:49.01#ibcon#end of sib2, iclass 32, count 2 2006.218.08:03:49.01#ibcon#*after write, iclass 32, count 2 2006.218.08:03:49.01#ibcon#*before return 0, iclass 32, count 2 2006.218.08:03:49.01#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.218.08:03:49.01#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.218.08:03:49.01#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.218.08:03:49.01#ibcon#ireg 7 cls_cnt 0 2006.218.08:03:49.01#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.218.08:03:49.13#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.218.08:03:49.13#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.218.08:03:49.13#ibcon#enter wrdev, iclass 32, count 0 2006.218.08:03:49.13#ibcon#first serial, iclass 32, count 0 2006.218.08:03:49.13#ibcon#enter sib2, iclass 32, count 0 2006.218.08:03:49.13#ibcon#flushed, iclass 32, count 0 2006.218.08:03:49.13#ibcon#about to write, iclass 32, count 0 2006.218.08:03:49.13#ibcon#wrote, iclass 32, count 0 2006.218.08:03:49.13#ibcon#about to read 3, iclass 32, count 0 2006.218.08:03:49.15#ibcon#read 3, iclass 32, count 0 2006.218.08:03:49.15#ibcon#about to read 4, iclass 32, count 0 2006.218.08:03:49.15#ibcon#read 4, iclass 32, count 0 2006.218.08:03:49.15#ibcon#about to read 5, iclass 32, count 0 2006.218.08:03:49.15#ibcon#read 5, iclass 32, count 0 2006.218.08:03:49.15#ibcon#about to read 6, iclass 32, count 0 2006.218.08:03:49.15#ibcon#read 6, iclass 32, count 0 2006.218.08:03:49.15#ibcon#end of sib2, iclass 32, count 0 2006.218.08:03:49.15#ibcon#*mode == 0, iclass 32, count 0 2006.218.08:03:49.15#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.218.08:03:49.15#ibcon#[25=USB\r\n] 2006.218.08:03:49.15#ibcon#*before write, iclass 32, count 0 2006.218.08:03:49.15#ibcon#enter sib2, iclass 32, count 0 2006.218.08:03:49.15#ibcon#flushed, iclass 32, count 0 2006.218.08:03:49.15#ibcon#about to write, iclass 32, count 0 2006.218.08:03:49.15#ibcon#wrote, iclass 32, count 0 2006.218.08:03:49.15#ibcon#about to read 3, iclass 32, count 0 2006.218.08:03:49.18#ibcon#read 3, iclass 32, count 0 2006.218.08:03:49.18#ibcon#about to read 4, iclass 32, count 0 2006.218.08:03:49.18#ibcon#read 4, iclass 32, count 0 2006.218.08:03:49.18#ibcon#about to read 5, iclass 32, count 0 2006.218.08:03:49.18#ibcon#read 5, iclass 32, count 0 2006.218.08:03:49.18#ibcon#about to read 6, iclass 32, count 0 2006.218.08:03:49.18#ibcon#read 6, iclass 32, count 0 2006.218.08:03:49.18#ibcon#end of sib2, iclass 32, count 0 2006.218.08:03:49.18#ibcon#*after write, iclass 32, count 0 2006.218.08:03:49.18#ibcon#*before return 0, iclass 32, count 0 2006.218.08:03:49.18#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.218.08:03:49.18#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.218.08:03:49.18#ibcon#about to clear, iclass 32 cls_cnt 0 2006.218.08:03:49.18#ibcon#cleared, iclass 32 cls_cnt 0 2006.218.08:03:49.18$vc4f8/valo=5,652.99 2006.218.08:03:49.18#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.218.08:03:49.18#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.218.08:03:49.18#ibcon#ireg 17 cls_cnt 0 2006.218.08:03:49.18#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.218.08:03:49.18#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.218.08:03:49.18#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.218.08:03:49.18#ibcon#enter wrdev, iclass 34, count 0 2006.218.08:03:49.18#ibcon#first serial, iclass 34, count 0 2006.218.08:03:49.18#ibcon#enter sib2, iclass 34, count 0 2006.218.08:03:49.18#ibcon#flushed, iclass 34, count 0 2006.218.08:03:49.18#ibcon#about to write, iclass 34, count 0 2006.218.08:03:49.18#ibcon#wrote, iclass 34, count 0 2006.218.08:03:49.18#ibcon#about to read 3, iclass 34, count 0 2006.218.08:03:49.20#ibcon#read 3, iclass 34, count 0 2006.218.08:03:49.20#ibcon#about to read 4, iclass 34, count 0 2006.218.08:03:49.20#ibcon#read 4, iclass 34, count 0 2006.218.08:03:49.20#ibcon#about to read 5, iclass 34, count 0 2006.218.08:03:49.20#ibcon#read 5, iclass 34, count 0 2006.218.08:03:49.20#ibcon#about to read 6, iclass 34, count 0 2006.218.08:03:49.20#ibcon#read 6, iclass 34, count 0 2006.218.08:03:49.20#ibcon#end of sib2, iclass 34, count 0 2006.218.08:03:49.20#ibcon#*mode == 0, iclass 34, count 0 2006.218.08:03:49.20#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.218.08:03:49.20#ibcon#[26=FRQ=05,652.99\r\n] 2006.218.08:03:49.20#ibcon#*before write, iclass 34, count 0 2006.218.08:03:49.20#ibcon#enter sib2, iclass 34, count 0 2006.218.08:03:49.20#ibcon#flushed, iclass 34, count 0 2006.218.08:03:49.20#ibcon#about to write, iclass 34, count 0 2006.218.08:03:49.20#ibcon#wrote, iclass 34, count 0 2006.218.08:03:49.20#ibcon#about to read 3, iclass 34, count 0 2006.218.08:03:49.24#ibcon#read 3, iclass 34, count 0 2006.218.08:03:49.24#ibcon#about to read 4, iclass 34, count 0 2006.218.08:03:49.24#ibcon#read 4, iclass 34, count 0 2006.218.08:03:49.24#ibcon#about to read 5, iclass 34, count 0 2006.218.08:03:49.24#ibcon#read 5, iclass 34, count 0 2006.218.08:03:49.24#ibcon#about to read 6, iclass 34, count 0 2006.218.08:03:49.24#ibcon#read 6, iclass 34, count 0 2006.218.08:03:49.24#ibcon#end of sib2, iclass 34, count 0 2006.218.08:03:49.24#ibcon#*after write, iclass 34, count 0 2006.218.08:03:49.24#ibcon#*before return 0, iclass 34, count 0 2006.218.08:03:49.24#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.218.08:03:49.24#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.218.08:03:49.24#ibcon#about to clear, iclass 34 cls_cnt 0 2006.218.08:03:49.24#ibcon#cleared, iclass 34 cls_cnt 0 2006.218.08:03:49.24$vc4f8/va=5,7 2006.218.08:03:49.24#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.218.08:03:49.24#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.218.08:03:49.24#ibcon#ireg 11 cls_cnt 2 2006.218.08:03:49.24#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.218.08:03:49.30#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.218.08:03:49.30#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.218.08:03:49.30#ibcon#enter wrdev, iclass 36, count 2 2006.218.08:03:49.30#ibcon#first serial, iclass 36, count 2 2006.218.08:03:49.30#ibcon#enter sib2, iclass 36, count 2 2006.218.08:03:49.30#ibcon#flushed, iclass 36, count 2 2006.218.08:03:49.30#ibcon#about to write, iclass 36, count 2 2006.218.08:03:49.30#ibcon#wrote, iclass 36, count 2 2006.218.08:03:49.30#ibcon#about to read 3, iclass 36, count 2 2006.218.08:03:49.32#ibcon#read 3, iclass 36, count 2 2006.218.08:03:49.32#ibcon#about to read 4, iclass 36, count 2 2006.218.08:03:49.32#ibcon#read 4, iclass 36, count 2 2006.218.08:03:49.32#ibcon#about to read 5, iclass 36, count 2 2006.218.08:03:49.32#ibcon#read 5, iclass 36, count 2 2006.218.08:03:49.32#ibcon#about to read 6, iclass 36, count 2 2006.218.08:03:49.32#ibcon#read 6, iclass 36, count 2 2006.218.08:03:49.32#ibcon#end of sib2, iclass 36, count 2 2006.218.08:03:49.32#ibcon#*mode == 0, iclass 36, count 2 2006.218.08:03:49.32#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.218.08:03:49.32#ibcon#[25=AT05-07\r\n] 2006.218.08:03:49.32#ibcon#*before write, iclass 36, count 2 2006.218.08:03:49.32#ibcon#enter sib2, iclass 36, count 2 2006.218.08:03:49.32#ibcon#flushed, iclass 36, count 2 2006.218.08:03:49.32#ibcon#about to write, iclass 36, count 2 2006.218.08:03:49.32#ibcon#wrote, iclass 36, count 2 2006.218.08:03:49.32#ibcon#about to read 3, iclass 36, count 2 2006.218.08:03:49.35#ibcon#read 3, iclass 36, count 2 2006.218.08:03:49.35#ibcon#about to read 4, iclass 36, count 2 2006.218.08:03:49.35#ibcon#read 4, iclass 36, count 2 2006.218.08:03:49.35#ibcon#about to read 5, iclass 36, count 2 2006.218.08:03:49.35#ibcon#read 5, iclass 36, count 2 2006.218.08:03:49.35#ibcon#about to read 6, iclass 36, count 2 2006.218.08:03:49.35#ibcon#read 6, iclass 36, count 2 2006.218.08:03:49.35#ibcon#end of sib2, iclass 36, count 2 2006.218.08:03:49.35#ibcon#*after write, iclass 36, count 2 2006.218.08:03:49.35#ibcon#*before return 0, iclass 36, count 2 2006.218.08:03:49.35#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.218.08:03:49.35#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.218.08:03:49.35#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.218.08:03:49.35#ibcon#ireg 7 cls_cnt 0 2006.218.08:03:49.35#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.218.08:03:49.47#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.218.08:03:49.47#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.218.08:03:49.47#ibcon#enter wrdev, iclass 36, count 0 2006.218.08:03:49.47#ibcon#first serial, iclass 36, count 0 2006.218.08:03:49.47#ibcon#enter sib2, iclass 36, count 0 2006.218.08:03:49.47#ibcon#flushed, iclass 36, count 0 2006.218.08:03:49.47#ibcon#about to write, iclass 36, count 0 2006.218.08:03:49.47#ibcon#wrote, iclass 36, count 0 2006.218.08:03:49.47#ibcon#about to read 3, iclass 36, count 0 2006.218.08:03:49.49#ibcon#read 3, iclass 36, count 0 2006.218.08:03:49.49#ibcon#about to read 4, iclass 36, count 0 2006.218.08:03:49.49#ibcon#read 4, iclass 36, count 0 2006.218.08:03:49.49#ibcon#about to read 5, iclass 36, count 0 2006.218.08:03:49.49#ibcon#read 5, iclass 36, count 0 2006.218.08:03:49.49#ibcon#about to read 6, iclass 36, count 0 2006.218.08:03:49.49#ibcon#read 6, iclass 36, count 0 2006.218.08:03:49.49#ibcon#end of sib2, iclass 36, count 0 2006.218.08:03:49.49#ibcon#*mode == 0, iclass 36, count 0 2006.218.08:03:49.49#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.218.08:03:49.49#ibcon#[25=USB\r\n] 2006.218.08:03:49.49#ibcon#*before write, iclass 36, count 0 2006.218.08:03:49.49#ibcon#enter sib2, iclass 36, count 0 2006.218.08:03:49.49#ibcon#flushed, iclass 36, count 0 2006.218.08:03:49.49#ibcon#about to write, iclass 36, count 0 2006.218.08:03:49.49#ibcon#wrote, iclass 36, count 0 2006.218.08:03:49.49#ibcon#about to read 3, iclass 36, count 0 2006.218.08:03:49.52#ibcon#read 3, iclass 36, count 0 2006.218.08:03:49.52#ibcon#about to read 4, iclass 36, count 0 2006.218.08:03:49.52#ibcon#read 4, iclass 36, count 0 2006.218.08:03:49.52#ibcon#about to read 5, iclass 36, count 0 2006.218.08:03:49.52#ibcon#read 5, iclass 36, count 0 2006.218.08:03:49.52#ibcon#about to read 6, iclass 36, count 0 2006.218.08:03:49.52#ibcon#read 6, iclass 36, count 0 2006.218.08:03:49.52#ibcon#end of sib2, iclass 36, count 0 2006.218.08:03:49.52#ibcon#*after write, iclass 36, count 0 2006.218.08:03:49.52#ibcon#*before return 0, iclass 36, count 0 2006.218.08:03:49.52#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.218.08:03:49.52#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.218.08:03:49.52#ibcon#about to clear, iclass 36 cls_cnt 0 2006.218.08:03:49.52#ibcon#cleared, iclass 36 cls_cnt 0 2006.218.08:03:49.52$vc4f8/valo=6,772.99 2006.218.08:03:49.52#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.218.08:03:49.52#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.218.08:03:49.52#ibcon#ireg 17 cls_cnt 0 2006.218.08:03:49.52#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.218.08:03:49.52#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.218.08:03:49.52#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.218.08:03:49.52#ibcon#enter wrdev, iclass 38, count 0 2006.218.08:03:49.52#ibcon#first serial, iclass 38, count 0 2006.218.08:03:49.52#ibcon#enter sib2, iclass 38, count 0 2006.218.08:03:49.52#ibcon#flushed, iclass 38, count 0 2006.218.08:03:49.52#ibcon#about to write, iclass 38, count 0 2006.218.08:03:49.52#ibcon#wrote, iclass 38, count 0 2006.218.08:03:49.52#ibcon#about to read 3, iclass 38, count 0 2006.218.08:03:49.55#ibcon#read 3, iclass 38, count 0 2006.218.08:03:49.55#ibcon#about to read 4, iclass 38, count 0 2006.218.08:03:49.55#ibcon#read 4, iclass 38, count 0 2006.218.08:03:49.55#ibcon#about to read 5, iclass 38, count 0 2006.218.08:03:49.55#ibcon#read 5, iclass 38, count 0 2006.218.08:03:49.55#ibcon#about to read 6, iclass 38, count 0 2006.218.08:03:49.55#ibcon#read 6, iclass 38, count 0 2006.218.08:03:49.55#ibcon#end of sib2, iclass 38, count 0 2006.218.08:03:49.55#ibcon#*mode == 0, iclass 38, count 0 2006.218.08:03:49.55#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.218.08:03:49.55#ibcon#[26=FRQ=06,772.99\r\n] 2006.218.08:03:49.55#ibcon#*before write, iclass 38, count 0 2006.218.08:03:49.55#ibcon#enter sib2, iclass 38, count 0 2006.218.08:03:49.55#ibcon#flushed, iclass 38, count 0 2006.218.08:03:49.55#ibcon#about to write, iclass 38, count 0 2006.218.08:03:49.55#ibcon#wrote, iclass 38, count 0 2006.218.08:03:49.55#ibcon#about to read 3, iclass 38, count 0 2006.218.08:03:49.59#ibcon#read 3, iclass 38, count 0 2006.218.08:03:49.59#ibcon#about to read 4, iclass 38, count 0 2006.218.08:03:49.59#ibcon#read 4, iclass 38, count 0 2006.218.08:03:49.59#ibcon#about to read 5, iclass 38, count 0 2006.218.08:03:49.59#ibcon#read 5, iclass 38, count 0 2006.218.08:03:49.59#ibcon#about to read 6, iclass 38, count 0 2006.218.08:03:49.59#ibcon#read 6, iclass 38, count 0 2006.218.08:03:49.59#ibcon#end of sib2, iclass 38, count 0 2006.218.08:03:49.59#ibcon#*after write, iclass 38, count 0 2006.218.08:03:49.59#ibcon#*before return 0, iclass 38, count 0 2006.218.08:03:49.59#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.218.08:03:49.59#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.218.08:03:49.59#ibcon#about to clear, iclass 38 cls_cnt 0 2006.218.08:03:49.59#ibcon#cleared, iclass 38 cls_cnt 0 2006.218.08:03:49.59$vc4f8/va=6,6 2006.218.08:03:49.59#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.218.08:03:49.59#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.218.08:03:49.59#ibcon#ireg 11 cls_cnt 2 2006.218.08:03:49.59#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.218.08:03:49.64#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.218.08:03:49.64#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.218.08:03:49.64#ibcon#enter wrdev, iclass 40, count 2 2006.218.08:03:49.64#ibcon#first serial, iclass 40, count 2 2006.218.08:03:49.64#ibcon#enter sib2, iclass 40, count 2 2006.218.08:03:49.64#ibcon#flushed, iclass 40, count 2 2006.218.08:03:49.64#ibcon#about to write, iclass 40, count 2 2006.218.08:03:49.64#ibcon#wrote, iclass 40, count 2 2006.218.08:03:49.64#ibcon#about to read 3, iclass 40, count 2 2006.218.08:03:49.66#ibcon#read 3, iclass 40, count 2 2006.218.08:03:49.66#ibcon#about to read 4, iclass 40, count 2 2006.218.08:03:49.66#ibcon#read 4, iclass 40, count 2 2006.218.08:03:49.66#ibcon#about to read 5, iclass 40, count 2 2006.218.08:03:49.66#ibcon#read 5, iclass 40, count 2 2006.218.08:03:49.66#ibcon#about to read 6, iclass 40, count 2 2006.218.08:03:49.66#ibcon#read 6, iclass 40, count 2 2006.218.08:03:49.66#ibcon#end of sib2, iclass 40, count 2 2006.218.08:03:49.66#ibcon#*mode == 0, iclass 40, count 2 2006.218.08:03:49.66#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.218.08:03:49.66#ibcon#[25=AT06-06\r\n] 2006.218.08:03:49.66#ibcon#*before write, iclass 40, count 2 2006.218.08:03:49.66#ibcon#enter sib2, iclass 40, count 2 2006.218.08:03:49.66#ibcon#flushed, iclass 40, count 2 2006.218.08:03:49.66#ibcon#about to write, iclass 40, count 2 2006.218.08:03:49.66#ibcon#wrote, iclass 40, count 2 2006.218.08:03:49.66#ibcon#about to read 3, iclass 40, count 2 2006.218.08:03:49.69#ibcon#read 3, iclass 40, count 2 2006.218.08:03:49.69#ibcon#about to read 4, iclass 40, count 2 2006.218.08:03:49.69#ibcon#read 4, iclass 40, count 2 2006.218.08:03:49.69#ibcon#about to read 5, iclass 40, count 2 2006.218.08:03:49.69#ibcon#read 5, iclass 40, count 2 2006.218.08:03:49.69#ibcon#about to read 6, iclass 40, count 2 2006.218.08:03:49.69#ibcon#read 6, iclass 40, count 2 2006.218.08:03:49.69#ibcon#end of sib2, iclass 40, count 2 2006.218.08:03:49.69#ibcon#*after write, iclass 40, count 2 2006.218.08:03:49.69#ibcon#*before return 0, iclass 40, count 2 2006.218.08:03:49.69#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.218.08:03:49.69#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.218.08:03:49.69#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.218.08:03:49.69#ibcon#ireg 7 cls_cnt 0 2006.218.08:03:49.69#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.218.08:03:49.81#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.218.08:03:49.81#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.218.08:03:49.81#ibcon#enter wrdev, iclass 40, count 0 2006.218.08:03:49.81#ibcon#first serial, iclass 40, count 0 2006.218.08:03:49.81#ibcon#enter sib2, iclass 40, count 0 2006.218.08:03:49.81#ibcon#flushed, iclass 40, count 0 2006.218.08:03:49.81#ibcon#about to write, iclass 40, count 0 2006.218.08:03:49.81#ibcon#wrote, iclass 40, count 0 2006.218.08:03:49.81#ibcon#about to read 3, iclass 40, count 0 2006.218.08:03:49.83#ibcon#read 3, iclass 40, count 0 2006.218.08:03:49.83#ibcon#about to read 4, iclass 40, count 0 2006.218.08:03:49.83#ibcon#read 4, iclass 40, count 0 2006.218.08:03:49.83#ibcon#about to read 5, iclass 40, count 0 2006.218.08:03:49.83#ibcon#read 5, iclass 40, count 0 2006.218.08:03:49.83#ibcon#about to read 6, iclass 40, count 0 2006.218.08:03:49.83#ibcon#read 6, iclass 40, count 0 2006.218.08:03:49.83#ibcon#end of sib2, iclass 40, count 0 2006.218.08:03:49.83#ibcon#*mode == 0, iclass 40, count 0 2006.218.08:03:49.83#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.218.08:03:49.83#ibcon#[25=USB\r\n] 2006.218.08:03:49.83#ibcon#*before write, iclass 40, count 0 2006.218.08:03:49.83#ibcon#enter sib2, iclass 40, count 0 2006.218.08:03:49.83#ibcon#flushed, iclass 40, count 0 2006.218.08:03:49.83#ibcon#about to write, iclass 40, count 0 2006.218.08:03:49.83#ibcon#wrote, iclass 40, count 0 2006.218.08:03:49.83#ibcon#about to read 3, iclass 40, count 0 2006.218.08:03:49.86#ibcon#read 3, iclass 40, count 0 2006.218.08:03:49.86#ibcon#about to read 4, iclass 40, count 0 2006.218.08:03:49.86#ibcon#read 4, iclass 40, count 0 2006.218.08:03:49.86#ibcon#about to read 5, iclass 40, count 0 2006.218.08:03:49.86#ibcon#read 5, iclass 40, count 0 2006.218.08:03:49.86#ibcon#about to read 6, iclass 40, count 0 2006.218.08:03:49.86#ibcon#read 6, iclass 40, count 0 2006.218.08:03:49.86#ibcon#end of sib2, iclass 40, count 0 2006.218.08:03:49.86#ibcon#*after write, iclass 40, count 0 2006.218.08:03:49.86#ibcon#*before return 0, iclass 40, count 0 2006.218.08:03:49.86#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.218.08:03:49.86#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.218.08:03:49.86#ibcon#about to clear, iclass 40 cls_cnt 0 2006.218.08:03:49.86#ibcon#cleared, iclass 40 cls_cnt 0 2006.218.08:03:49.86$vc4f8/valo=7,832.99 2006.218.08:03:49.86#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.218.08:03:49.86#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.218.08:03:49.86#ibcon#ireg 17 cls_cnt 0 2006.218.08:03:49.86#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.218.08:03:49.86#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.218.08:03:49.86#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.218.08:03:49.86#ibcon#enter wrdev, iclass 4, count 0 2006.218.08:03:49.86#ibcon#first serial, iclass 4, count 0 2006.218.08:03:49.86#ibcon#enter sib2, iclass 4, count 0 2006.218.08:03:49.86#ibcon#flushed, iclass 4, count 0 2006.218.08:03:49.86#ibcon#about to write, iclass 4, count 0 2006.218.08:03:49.86#ibcon#wrote, iclass 4, count 0 2006.218.08:03:49.86#ibcon#about to read 3, iclass 4, count 0 2006.218.08:03:49.88#ibcon#read 3, iclass 4, count 0 2006.218.08:03:49.88#ibcon#about to read 4, iclass 4, count 0 2006.218.08:03:49.88#ibcon#read 4, iclass 4, count 0 2006.218.08:03:49.88#ibcon#about to read 5, iclass 4, count 0 2006.218.08:03:49.88#ibcon#read 5, iclass 4, count 0 2006.218.08:03:49.88#ibcon#about to read 6, iclass 4, count 0 2006.218.08:03:49.88#ibcon#read 6, iclass 4, count 0 2006.218.08:03:49.88#ibcon#end of sib2, iclass 4, count 0 2006.218.08:03:49.88#ibcon#*mode == 0, iclass 4, count 0 2006.218.08:03:49.88#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.218.08:03:49.88#ibcon#[26=FRQ=07,832.99\r\n] 2006.218.08:03:49.88#ibcon#*before write, iclass 4, count 0 2006.218.08:03:49.88#ibcon#enter sib2, iclass 4, count 0 2006.218.08:03:49.88#ibcon#flushed, iclass 4, count 0 2006.218.08:03:49.88#ibcon#about to write, iclass 4, count 0 2006.218.08:03:49.88#ibcon#wrote, iclass 4, count 0 2006.218.08:03:49.88#ibcon#about to read 3, iclass 4, count 0 2006.218.08:03:49.92#ibcon#read 3, iclass 4, count 0 2006.218.08:03:49.92#ibcon#about to read 4, iclass 4, count 0 2006.218.08:03:49.92#ibcon#read 4, iclass 4, count 0 2006.218.08:03:49.92#ibcon#about to read 5, iclass 4, count 0 2006.218.08:03:49.92#ibcon#read 5, iclass 4, count 0 2006.218.08:03:49.92#ibcon#about to read 6, iclass 4, count 0 2006.218.08:03:49.92#ibcon#read 6, iclass 4, count 0 2006.218.08:03:49.92#ibcon#end of sib2, iclass 4, count 0 2006.218.08:03:49.92#ibcon#*after write, iclass 4, count 0 2006.218.08:03:49.92#ibcon#*before return 0, iclass 4, count 0 2006.218.08:03:49.92#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.218.08:03:49.92#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.218.08:03:49.92#ibcon#about to clear, iclass 4 cls_cnt 0 2006.218.08:03:49.92#ibcon#cleared, iclass 4 cls_cnt 0 2006.218.08:03:49.92$vc4f8/va=7,6 2006.218.08:03:49.92#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.218.08:03:49.92#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.218.08:03:49.92#ibcon#ireg 11 cls_cnt 2 2006.218.08:03:49.92#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.218.08:03:49.98#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.218.08:03:49.98#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.218.08:03:49.98#ibcon#enter wrdev, iclass 6, count 2 2006.218.08:03:49.98#ibcon#first serial, iclass 6, count 2 2006.218.08:03:49.98#ibcon#enter sib2, iclass 6, count 2 2006.218.08:03:49.98#ibcon#flushed, iclass 6, count 2 2006.218.08:03:49.98#ibcon#about to write, iclass 6, count 2 2006.218.08:03:49.98#ibcon#wrote, iclass 6, count 2 2006.218.08:03:49.98#ibcon#about to read 3, iclass 6, count 2 2006.218.08:03:50.00#ibcon#read 3, iclass 6, count 2 2006.218.08:03:50.00#ibcon#about to read 4, iclass 6, count 2 2006.218.08:03:50.00#ibcon#read 4, iclass 6, count 2 2006.218.08:03:50.00#ibcon#about to read 5, iclass 6, count 2 2006.218.08:03:50.00#ibcon#read 5, iclass 6, count 2 2006.218.08:03:50.00#ibcon#about to read 6, iclass 6, count 2 2006.218.08:03:50.00#ibcon#read 6, iclass 6, count 2 2006.218.08:03:50.00#ibcon#end of sib2, iclass 6, count 2 2006.218.08:03:50.00#ibcon#*mode == 0, iclass 6, count 2 2006.218.08:03:50.00#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.218.08:03:50.00#ibcon#[25=AT07-06\r\n] 2006.218.08:03:50.00#ibcon#*before write, iclass 6, count 2 2006.218.08:03:50.00#ibcon#enter sib2, iclass 6, count 2 2006.218.08:03:50.00#ibcon#flushed, iclass 6, count 2 2006.218.08:03:50.00#ibcon#about to write, iclass 6, count 2 2006.218.08:03:50.00#ibcon#wrote, iclass 6, count 2 2006.218.08:03:50.00#ibcon#about to read 3, iclass 6, count 2 2006.218.08:03:50.03#ibcon#read 3, iclass 6, count 2 2006.218.08:03:50.03#ibcon#about to read 4, iclass 6, count 2 2006.218.08:03:50.03#ibcon#read 4, iclass 6, count 2 2006.218.08:03:50.03#ibcon#about to read 5, iclass 6, count 2 2006.218.08:03:50.03#ibcon#read 5, iclass 6, count 2 2006.218.08:03:50.03#ibcon#about to read 6, iclass 6, count 2 2006.218.08:03:50.03#ibcon#read 6, iclass 6, count 2 2006.218.08:03:50.03#ibcon#end of sib2, iclass 6, count 2 2006.218.08:03:50.03#ibcon#*after write, iclass 6, count 2 2006.218.08:03:50.03#ibcon#*before return 0, iclass 6, count 2 2006.218.08:03:50.03#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.218.08:03:50.03#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.218.08:03:50.03#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.218.08:03:50.03#ibcon#ireg 7 cls_cnt 0 2006.218.08:03:50.03#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.218.08:03:50.15#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.218.08:03:50.15#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.218.08:03:50.15#ibcon#enter wrdev, iclass 6, count 0 2006.218.08:03:50.15#ibcon#first serial, iclass 6, count 0 2006.218.08:03:50.15#ibcon#enter sib2, iclass 6, count 0 2006.218.08:03:50.15#ibcon#flushed, iclass 6, count 0 2006.218.08:03:50.15#ibcon#about to write, iclass 6, count 0 2006.218.08:03:50.15#ibcon#wrote, iclass 6, count 0 2006.218.08:03:50.15#ibcon#about to read 3, iclass 6, count 0 2006.218.08:03:50.17#ibcon#read 3, iclass 6, count 0 2006.218.08:03:50.17#ibcon#about to read 4, iclass 6, count 0 2006.218.08:03:50.17#ibcon#read 4, iclass 6, count 0 2006.218.08:03:50.17#ibcon#about to read 5, iclass 6, count 0 2006.218.08:03:50.17#ibcon#read 5, iclass 6, count 0 2006.218.08:03:50.17#ibcon#about to read 6, iclass 6, count 0 2006.218.08:03:50.17#ibcon#read 6, iclass 6, count 0 2006.218.08:03:50.17#ibcon#end of sib2, iclass 6, count 0 2006.218.08:03:50.17#ibcon#*mode == 0, iclass 6, count 0 2006.218.08:03:50.17#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.218.08:03:50.17#ibcon#[25=USB\r\n] 2006.218.08:03:50.17#ibcon#*before write, iclass 6, count 0 2006.218.08:03:50.17#ibcon#enter sib2, iclass 6, count 0 2006.218.08:03:50.17#ibcon#flushed, iclass 6, count 0 2006.218.08:03:50.17#ibcon#about to write, iclass 6, count 0 2006.218.08:03:50.17#ibcon#wrote, iclass 6, count 0 2006.218.08:03:50.17#ibcon#about to read 3, iclass 6, count 0 2006.218.08:03:50.20#ibcon#read 3, iclass 6, count 0 2006.218.08:03:50.20#ibcon#about to read 4, iclass 6, count 0 2006.218.08:03:50.20#ibcon#read 4, iclass 6, count 0 2006.218.08:03:50.20#ibcon#about to read 5, iclass 6, count 0 2006.218.08:03:50.20#ibcon#read 5, iclass 6, count 0 2006.218.08:03:50.20#ibcon#about to read 6, iclass 6, count 0 2006.218.08:03:50.20#ibcon#read 6, iclass 6, count 0 2006.218.08:03:50.20#ibcon#end of sib2, iclass 6, count 0 2006.218.08:03:50.20#ibcon#*after write, iclass 6, count 0 2006.218.08:03:50.20#ibcon#*before return 0, iclass 6, count 0 2006.218.08:03:50.20#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.218.08:03:50.20#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.218.08:03:50.20#ibcon#about to clear, iclass 6 cls_cnt 0 2006.218.08:03:50.20#ibcon#cleared, iclass 6 cls_cnt 0 2006.218.08:03:50.20$vc4f8/valo=8,852.99 2006.218.08:03:50.20#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.218.08:03:50.20#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.218.08:03:50.20#ibcon#ireg 17 cls_cnt 0 2006.218.08:03:50.20#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.218.08:03:50.20#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.218.08:03:50.20#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.218.08:03:50.20#ibcon#enter wrdev, iclass 10, count 0 2006.218.08:03:50.20#ibcon#first serial, iclass 10, count 0 2006.218.08:03:50.20#ibcon#enter sib2, iclass 10, count 0 2006.218.08:03:50.20#ibcon#flushed, iclass 10, count 0 2006.218.08:03:50.20#ibcon#about to write, iclass 10, count 0 2006.218.08:03:50.20#ibcon#wrote, iclass 10, count 0 2006.218.08:03:50.20#ibcon#about to read 3, iclass 10, count 0 2006.218.08:03:50.22#ibcon#read 3, iclass 10, count 0 2006.218.08:03:50.22#ibcon#about to read 4, iclass 10, count 0 2006.218.08:03:50.22#ibcon#read 4, iclass 10, count 0 2006.218.08:03:50.22#ibcon#about to read 5, iclass 10, count 0 2006.218.08:03:50.22#ibcon#read 5, iclass 10, count 0 2006.218.08:03:50.22#ibcon#about to read 6, iclass 10, count 0 2006.218.08:03:50.22#ibcon#read 6, iclass 10, count 0 2006.218.08:03:50.22#ibcon#end of sib2, iclass 10, count 0 2006.218.08:03:50.22#ibcon#*mode == 0, iclass 10, count 0 2006.218.08:03:50.22#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.218.08:03:50.22#ibcon#[26=FRQ=08,852.99\r\n] 2006.218.08:03:50.22#ibcon#*before write, iclass 10, count 0 2006.218.08:03:50.22#ibcon#enter sib2, iclass 10, count 0 2006.218.08:03:50.22#ibcon#flushed, iclass 10, count 0 2006.218.08:03:50.22#ibcon#about to write, iclass 10, count 0 2006.218.08:03:50.22#ibcon#wrote, iclass 10, count 0 2006.218.08:03:50.22#ibcon#about to read 3, iclass 10, count 0 2006.218.08:03:50.26#ibcon#read 3, iclass 10, count 0 2006.218.08:03:50.26#ibcon#about to read 4, iclass 10, count 0 2006.218.08:03:50.26#ibcon#read 4, iclass 10, count 0 2006.218.08:03:50.26#ibcon#about to read 5, iclass 10, count 0 2006.218.08:03:50.26#ibcon#read 5, iclass 10, count 0 2006.218.08:03:50.26#ibcon#about to read 6, iclass 10, count 0 2006.218.08:03:50.26#ibcon#read 6, iclass 10, count 0 2006.218.08:03:50.26#ibcon#end of sib2, iclass 10, count 0 2006.218.08:03:50.26#ibcon#*after write, iclass 10, count 0 2006.218.08:03:50.26#ibcon#*before return 0, iclass 10, count 0 2006.218.08:03:50.26#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.218.08:03:50.26#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.218.08:03:50.26#ibcon#about to clear, iclass 10 cls_cnt 0 2006.218.08:03:50.26#ibcon#cleared, iclass 10 cls_cnt 0 2006.218.08:03:50.26$vc4f8/va=8,7 2006.218.08:03:50.26#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.218.08:03:50.26#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.218.08:03:50.26#ibcon#ireg 11 cls_cnt 2 2006.218.08:03:50.26#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.218.08:03:50.32#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.218.08:03:50.32#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.218.08:03:50.32#ibcon#enter wrdev, iclass 12, count 2 2006.218.08:03:50.32#ibcon#first serial, iclass 12, count 2 2006.218.08:03:50.32#ibcon#enter sib2, iclass 12, count 2 2006.218.08:03:50.32#ibcon#flushed, iclass 12, count 2 2006.218.08:03:50.32#ibcon#about to write, iclass 12, count 2 2006.218.08:03:50.32#ibcon#wrote, iclass 12, count 2 2006.218.08:03:50.32#ibcon#about to read 3, iclass 12, count 2 2006.218.08:03:50.34#ibcon#read 3, iclass 12, count 2 2006.218.08:03:50.34#ibcon#about to read 4, iclass 12, count 2 2006.218.08:03:50.34#ibcon#read 4, iclass 12, count 2 2006.218.08:03:50.34#ibcon#about to read 5, iclass 12, count 2 2006.218.08:03:50.34#ibcon#read 5, iclass 12, count 2 2006.218.08:03:50.34#ibcon#about to read 6, iclass 12, count 2 2006.218.08:03:50.34#ibcon#read 6, iclass 12, count 2 2006.218.08:03:50.34#ibcon#end of sib2, iclass 12, count 2 2006.218.08:03:50.34#ibcon#*mode == 0, iclass 12, count 2 2006.218.08:03:50.34#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.218.08:03:50.34#ibcon#[25=AT08-07\r\n] 2006.218.08:03:50.34#ibcon#*before write, iclass 12, count 2 2006.218.08:03:50.34#ibcon#enter sib2, iclass 12, count 2 2006.218.08:03:50.34#ibcon#flushed, iclass 12, count 2 2006.218.08:03:50.34#ibcon#about to write, iclass 12, count 2 2006.218.08:03:50.34#ibcon#wrote, iclass 12, count 2 2006.218.08:03:50.34#ibcon#about to read 3, iclass 12, count 2 2006.218.08:03:50.37#ibcon#read 3, iclass 12, count 2 2006.218.08:03:50.37#ibcon#about to read 4, iclass 12, count 2 2006.218.08:03:50.37#ibcon#read 4, iclass 12, count 2 2006.218.08:03:50.37#ibcon#about to read 5, iclass 12, count 2 2006.218.08:03:50.37#ibcon#read 5, iclass 12, count 2 2006.218.08:03:50.37#ibcon#about to read 6, iclass 12, count 2 2006.218.08:03:50.37#ibcon#read 6, iclass 12, count 2 2006.218.08:03:50.37#ibcon#end of sib2, iclass 12, count 2 2006.218.08:03:50.37#ibcon#*after write, iclass 12, count 2 2006.218.08:03:50.37#ibcon#*before return 0, iclass 12, count 2 2006.218.08:03:50.37#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.218.08:03:50.37#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.218.08:03:50.37#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.218.08:03:50.37#ibcon#ireg 7 cls_cnt 0 2006.218.08:03:50.37#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.218.08:03:50.49#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.218.08:03:50.49#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.218.08:03:50.49#ibcon#enter wrdev, iclass 12, count 0 2006.218.08:03:50.49#ibcon#first serial, iclass 12, count 0 2006.218.08:03:50.49#ibcon#enter sib2, iclass 12, count 0 2006.218.08:03:50.49#ibcon#flushed, iclass 12, count 0 2006.218.08:03:50.49#ibcon#about to write, iclass 12, count 0 2006.218.08:03:50.49#ibcon#wrote, iclass 12, count 0 2006.218.08:03:50.49#ibcon#about to read 3, iclass 12, count 0 2006.218.08:03:50.51#ibcon#read 3, iclass 12, count 0 2006.218.08:03:50.51#ibcon#about to read 4, iclass 12, count 0 2006.218.08:03:50.51#ibcon#read 4, iclass 12, count 0 2006.218.08:03:50.51#ibcon#about to read 5, iclass 12, count 0 2006.218.08:03:50.51#ibcon#read 5, iclass 12, count 0 2006.218.08:03:50.51#ibcon#about to read 6, iclass 12, count 0 2006.218.08:03:50.51#ibcon#read 6, iclass 12, count 0 2006.218.08:03:50.51#ibcon#end of sib2, iclass 12, count 0 2006.218.08:03:50.51#ibcon#*mode == 0, iclass 12, count 0 2006.218.08:03:50.51#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.218.08:03:50.51#ibcon#[25=USB\r\n] 2006.218.08:03:50.51#ibcon#*before write, iclass 12, count 0 2006.218.08:03:50.51#ibcon#enter sib2, iclass 12, count 0 2006.218.08:03:50.51#ibcon#flushed, iclass 12, count 0 2006.218.08:03:50.51#ibcon#about to write, iclass 12, count 0 2006.218.08:03:50.51#ibcon#wrote, iclass 12, count 0 2006.218.08:03:50.51#ibcon#about to read 3, iclass 12, count 0 2006.218.08:03:50.54#ibcon#read 3, iclass 12, count 0 2006.218.08:03:50.54#ibcon#about to read 4, iclass 12, count 0 2006.218.08:03:50.54#ibcon#read 4, iclass 12, count 0 2006.218.08:03:50.54#ibcon#about to read 5, iclass 12, count 0 2006.218.08:03:50.54#ibcon#read 5, iclass 12, count 0 2006.218.08:03:50.54#ibcon#about to read 6, iclass 12, count 0 2006.218.08:03:50.54#ibcon#read 6, iclass 12, count 0 2006.218.08:03:50.54#ibcon#end of sib2, iclass 12, count 0 2006.218.08:03:50.54#ibcon#*after write, iclass 12, count 0 2006.218.08:03:50.54#ibcon#*before return 0, iclass 12, count 0 2006.218.08:03:50.54#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.218.08:03:50.54#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.218.08:03:50.54#ibcon#about to clear, iclass 12 cls_cnt 0 2006.218.08:03:50.54#ibcon#cleared, iclass 12 cls_cnt 0 2006.218.08:03:50.54$vc4f8/vblo=1,632.99 2006.218.08:03:50.54#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.218.08:03:50.54#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.218.08:03:50.54#ibcon#ireg 17 cls_cnt 0 2006.218.08:03:50.54#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.218.08:03:50.54#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.218.08:03:50.54#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.218.08:03:50.54#ibcon#enter wrdev, iclass 14, count 0 2006.218.08:03:50.54#ibcon#first serial, iclass 14, count 0 2006.218.08:03:50.54#ibcon#enter sib2, iclass 14, count 0 2006.218.08:03:50.54#ibcon#flushed, iclass 14, count 0 2006.218.08:03:50.54#ibcon#about to write, iclass 14, count 0 2006.218.08:03:50.54#ibcon#wrote, iclass 14, count 0 2006.218.08:03:50.54#ibcon#about to read 3, iclass 14, count 0 2006.218.08:03:50.56#ibcon#read 3, iclass 14, count 0 2006.218.08:03:50.56#ibcon#about to read 4, iclass 14, count 0 2006.218.08:03:50.56#ibcon#read 4, iclass 14, count 0 2006.218.08:03:50.56#ibcon#about to read 5, iclass 14, count 0 2006.218.08:03:50.56#ibcon#read 5, iclass 14, count 0 2006.218.08:03:50.56#ibcon#about to read 6, iclass 14, count 0 2006.218.08:03:50.56#ibcon#read 6, iclass 14, count 0 2006.218.08:03:50.56#ibcon#end of sib2, iclass 14, count 0 2006.218.08:03:50.56#ibcon#*mode == 0, iclass 14, count 0 2006.218.08:03:50.56#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.218.08:03:50.56#ibcon#[28=FRQ=01,632.99\r\n] 2006.218.08:03:50.56#ibcon#*before write, iclass 14, count 0 2006.218.08:03:50.56#ibcon#enter sib2, iclass 14, count 0 2006.218.08:03:50.56#ibcon#flushed, iclass 14, count 0 2006.218.08:03:50.56#ibcon#about to write, iclass 14, count 0 2006.218.08:03:50.56#ibcon#wrote, iclass 14, count 0 2006.218.08:03:50.56#ibcon#about to read 3, iclass 14, count 0 2006.218.08:03:50.60#ibcon#read 3, iclass 14, count 0 2006.218.08:03:50.60#ibcon#about to read 4, iclass 14, count 0 2006.218.08:03:50.60#ibcon#read 4, iclass 14, count 0 2006.218.08:03:50.60#ibcon#about to read 5, iclass 14, count 0 2006.218.08:03:50.60#ibcon#read 5, iclass 14, count 0 2006.218.08:03:50.60#ibcon#about to read 6, iclass 14, count 0 2006.218.08:03:50.60#ibcon#read 6, iclass 14, count 0 2006.218.08:03:50.60#ibcon#end of sib2, iclass 14, count 0 2006.218.08:03:50.60#ibcon#*after write, iclass 14, count 0 2006.218.08:03:50.60#ibcon#*before return 0, iclass 14, count 0 2006.218.08:03:50.60#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.218.08:03:50.60#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.218.08:03:50.60#ibcon#about to clear, iclass 14 cls_cnt 0 2006.218.08:03:50.60#ibcon#cleared, iclass 14 cls_cnt 0 2006.218.08:03:50.60$vc4f8/vb=1,4 2006.218.08:03:50.60#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.218.08:03:50.60#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.218.08:03:50.60#ibcon#ireg 11 cls_cnt 2 2006.218.08:03:50.60#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.218.08:03:50.60#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.218.08:03:50.60#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.218.08:03:50.60#ibcon#enter wrdev, iclass 16, count 2 2006.218.08:03:50.60#ibcon#first serial, iclass 16, count 2 2006.218.08:03:50.60#ibcon#enter sib2, iclass 16, count 2 2006.218.08:03:50.60#ibcon#flushed, iclass 16, count 2 2006.218.08:03:50.60#ibcon#about to write, iclass 16, count 2 2006.218.08:03:50.60#ibcon#wrote, iclass 16, count 2 2006.218.08:03:50.60#ibcon#about to read 3, iclass 16, count 2 2006.218.08:03:50.62#ibcon#read 3, iclass 16, count 2 2006.218.08:03:50.62#ibcon#about to read 4, iclass 16, count 2 2006.218.08:03:50.62#ibcon#read 4, iclass 16, count 2 2006.218.08:03:50.62#ibcon#about to read 5, iclass 16, count 2 2006.218.08:03:50.62#ibcon#read 5, iclass 16, count 2 2006.218.08:03:50.62#ibcon#about to read 6, iclass 16, count 2 2006.218.08:03:50.62#ibcon#read 6, iclass 16, count 2 2006.218.08:03:50.62#ibcon#end of sib2, iclass 16, count 2 2006.218.08:03:50.62#ibcon#*mode == 0, iclass 16, count 2 2006.218.08:03:50.62#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.218.08:03:50.62#ibcon#[27=AT01-04\r\n] 2006.218.08:03:50.62#ibcon#*before write, iclass 16, count 2 2006.218.08:03:50.62#ibcon#enter sib2, iclass 16, count 2 2006.218.08:03:50.62#ibcon#flushed, iclass 16, count 2 2006.218.08:03:50.62#ibcon#about to write, iclass 16, count 2 2006.218.08:03:50.62#ibcon#wrote, iclass 16, count 2 2006.218.08:03:50.62#ibcon#about to read 3, iclass 16, count 2 2006.218.08:03:50.65#ibcon#read 3, iclass 16, count 2 2006.218.08:03:50.65#ibcon#about to read 4, iclass 16, count 2 2006.218.08:03:50.65#ibcon#read 4, iclass 16, count 2 2006.218.08:03:50.65#ibcon#about to read 5, iclass 16, count 2 2006.218.08:03:50.65#ibcon#read 5, iclass 16, count 2 2006.218.08:03:50.65#ibcon#about to read 6, iclass 16, count 2 2006.218.08:03:50.65#ibcon#read 6, iclass 16, count 2 2006.218.08:03:50.65#ibcon#end of sib2, iclass 16, count 2 2006.218.08:03:50.65#ibcon#*after write, iclass 16, count 2 2006.218.08:03:50.65#ibcon#*before return 0, iclass 16, count 2 2006.218.08:03:50.65#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.218.08:03:50.65#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.218.08:03:50.65#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.218.08:03:50.65#ibcon#ireg 7 cls_cnt 0 2006.218.08:03:50.65#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.218.08:03:50.77#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.218.08:03:50.77#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.218.08:03:50.77#ibcon#enter wrdev, iclass 16, count 0 2006.218.08:03:50.77#ibcon#first serial, iclass 16, count 0 2006.218.08:03:50.77#ibcon#enter sib2, iclass 16, count 0 2006.218.08:03:50.77#ibcon#flushed, iclass 16, count 0 2006.218.08:03:50.77#ibcon#about to write, iclass 16, count 0 2006.218.08:03:50.77#ibcon#wrote, iclass 16, count 0 2006.218.08:03:50.77#ibcon#about to read 3, iclass 16, count 0 2006.218.08:03:50.79#ibcon#read 3, iclass 16, count 0 2006.218.08:03:50.79#ibcon#about to read 4, iclass 16, count 0 2006.218.08:03:50.79#ibcon#read 4, iclass 16, count 0 2006.218.08:03:50.79#ibcon#about to read 5, iclass 16, count 0 2006.218.08:03:50.79#ibcon#read 5, iclass 16, count 0 2006.218.08:03:50.79#ibcon#about to read 6, iclass 16, count 0 2006.218.08:03:50.79#ibcon#read 6, iclass 16, count 0 2006.218.08:03:50.79#ibcon#end of sib2, iclass 16, count 0 2006.218.08:03:50.79#ibcon#*mode == 0, iclass 16, count 0 2006.218.08:03:50.79#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.218.08:03:50.79#ibcon#[27=USB\r\n] 2006.218.08:03:50.79#ibcon#*before write, iclass 16, count 0 2006.218.08:03:50.79#ibcon#enter sib2, iclass 16, count 0 2006.218.08:03:50.79#ibcon#flushed, iclass 16, count 0 2006.218.08:03:50.79#ibcon#about to write, iclass 16, count 0 2006.218.08:03:50.79#ibcon#wrote, iclass 16, count 0 2006.218.08:03:50.79#ibcon#about to read 3, iclass 16, count 0 2006.218.08:03:50.82#ibcon#read 3, iclass 16, count 0 2006.218.08:03:50.82#ibcon#about to read 4, iclass 16, count 0 2006.218.08:03:50.82#ibcon#read 4, iclass 16, count 0 2006.218.08:03:50.82#ibcon#about to read 5, iclass 16, count 0 2006.218.08:03:50.82#ibcon#read 5, iclass 16, count 0 2006.218.08:03:50.82#ibcon#about to read 6, iclass 16, count 0 2006.218.08:03:50.82#ibcon#read 6, iclass 16, count 0 2006.218.08:03:50.82#ibcon#end of sib2, iclass 16, count 0 2006.218.08:03:50.82#ibcon#*after write, iclass 16, count 0 2006.218.08:03:50.82#ibcon#*before return 0, iclass 16, count 0 2006.218.08:03:50.82#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.218.08:03:50.82#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.218.08:03:50.82#ibcon#about to clear, iclass 16 cls_cnt 0 2006.218.08:03:50.82#ibcon#cleared, iclass 16 cls_cnt 0 2006.218.08:03:50.82$vc4f8/vblo=2,640.99 2006.218.08:03:50.82#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.218.08:03:50.82#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.218.08:03:50.82#ibcon#ireg 17 cls_cnt 0 2006.218.08:03:50.82#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.218.08:03:50.82#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.218.08:03:50.82#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.218.08:03:50.82#ibcon#enter wrdev, iclass 18, count 0 2006.218.08:03:50.82#ibcon#first serial, iclass 18, count 0 2006.218.08:03:50.82#ibcon#enter sib2, iclass 18, count 0 2006.218.08:03:50.82#ibcon#flushed, iclass 18, count 0 2006.218.08:03:50.82#ibcon#about to write, iclass 18, count 0 2006.218.08:03:50.82#ibcon#wrote, iclass 18, count 0 2006.218.08:03:50.82#ibcon#about to read 3, iclass 18, count 0 2006.218.08:03:50.84#ibcon#read 3, iclass 18, count 0 2006.218.08:03:50.84#ibcon#about to read 4, iclass 18, count 0 2006.218.08:03:50.84#ibcon#read 4, iclass 18, count 0 2006.218.08:03:50.84#ibcon#about to read 5, iclass 18, count 0 2006.218.08:03:50.84#ibcon#read 5, iclass 18, count 0 2006.218.08:03:50.84#ibcon#about to read 6, iclass 18, count 0 2006.218.08:03:50.84#ibcon#read 6, iclass 18, count 0 2006.218.08:03:50.84#ibcon#end of sib2, iclass 18, count 0 2006.218.08:03:50.84#ibcon#*mode == 0, iclass 18, count 0 2006.218.08:03:50.84#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.218.08:03:50.84#ibcon#[28=FRQ=02,640.99\r\n] 2006.218.08:03:50.84#ibcon#*before write, iclass 18, count 0 2006.218.08:03:50.84#ibcon#enter sib2, iclass 18, count 0 2006.218.08:03:50.84#ibcon#flushed, iclass 18, count 0 2006.218.08:03:50.84#ibcon#about to write, iclass 18, count 0 2006.218.08:03:50.84#ibcon#wrote, iclass 18, count 0 2006.218.08:03:50.84#ibcon#about to read 3, iclass 18, count 0 2006.218.08:03:50.88#ibcon#read 3, iclass 18, count 0 2006.218.08:03:50.88#ibcon#about to read 4, iclass 18, count 0 2006.218.08:03:50.88#ibcon#read 4, iclass 18, count 0 2006.218.08:03:50.88#ibcon#about to read 5, iclass 18, count 0 2006.218.08:03:50.88#ibcon#read 5, iclass 18, count 0 2006.218.08:03:50.88#ibcon#about to read 6, iclass 18, count 0 2006.218.08:03:50.88#ibcon#read 6, iclass 18, count 0 2006.218.08:03:50.88#ibcon#end of sib2, iclass 18, count 0 2006.218.08:03:50.88#ibcon#*after write, iclass 18, count 0 2006.218.08:03:50.88#ibcon#*before return 0, iclass 18, count 0 2006.218.08:03:50.88#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.218.08:03:50.88#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.218.08:03:50.88#ibcon#about to clear, iclass 18 cls_cnt 0 2006.218.08:03:50.88#ibcon#cleared, iclass 18 cls_cnt 0 2006.218.08:03:50.88$vc4f8/vb=2,4 2006.218.08:03:50.88#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.218.08:03:50.88#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.218.08:03:50.88#ibcon#ireg 11 cls_cnt 2 2006.218.08:03:50.88#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.218.08:03:50.94#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.218.08:03:50.94#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.218.08:03:50.94#ibcon#enter wrdev, iclass 20, count 2 2006.218.08:03:50.94#ibcon#first serial, iclass 20, count 2 2006.218.08:03:50.94#ibcon#enter sib2, iclass 20, count 2 2006.218.08:03:50.94#ibcon#flushed, iclass 20, count 2 2006.218.08:03:50.94#ibcon#about to write, iclass 20, count 2 2006.218.08:03:50.94#ibcon#wrote, iclass 20, count 2 2006.218.08:03:50.94#ibcon#about to read 3, iclass 20, count 2 2006.218.08:03:50.96#ibcon#read 3, iclass 20, count 2 2006.218.08:03:50.96#ibcon#about to read 4, iclass 20, count 2 2006.218.08:03:50.96#ibcon#read 4, iclass 20, count 2 2006.218.08:03:50.96#ibcon#about to read 5, iclass 20, count 2 2006.218.08:03:50.96#ibcon#read 5, iclass 20, count 2 2006.218.08:03:50.96#ibcon#about to read 6, iclass 20, count 2 2006.218.08:03:50.96#ibcon#read 6, iclass 20, count 2 2006.218.08:03:50.96#ibcon#end of sib2, iclass 20, count 2 2006.218.08:03:50.96#ibcon#*mode == 0, iclass 20, count 2 2006.218.08:03:50.96#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.218.08:03:50.96#ibcon#[27=AT02-04\r\n] 2006.218.08:03:50.96#ibcon#*before write, iclass 20, count 2 2006.218.08:03:50.96#ibcon#enter sib2, iclass 20, count 2 2006.218.08:03:50.96#ibcon#flushed, iclass 20, count 2 2006.218.08:03:50.96#ibcon#about to write, iclass 20, count 2 2006.218.08:03:50.96#ibcon#wrote, iclass 20, count 2 2006.218.08:03:50.96#ibcon#about to read 3, iclass 20, count 2 2006.218.08:03:50.99#ibcon#read 3, iclass 20, count 2 2006.218.08:03:50.99#ibcon#about to read 4, iclass 20, count 2 2006.218.08:03:50.99#ibcon#read 4, iclass 20, count 2 2006.218.08:03:50.99#ibcon#about to read 5, iclass 20, count 2 2006.218.08:03:50.99#ibcon#read 5, iclass 20, count 2 2006.218.08:03:50.99#ibcon#about to read 6, iclass 20, count 2 2006.218.08:03:50.99#ibcon#read 6, iclass 20, count 2 2006.218.08:03:50.99#ibcon#end of sib2, iclass 20, count 2 2006.218.08:03:50.99#ibcon#*after write, iclass 20, count 2 2006.218.08:03:50.99#ibcon#*before return 0, iclass 20, count 2 2006.218.08:03:50.99#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.218.08:03:50.99#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.218.08:03:50.99#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.218.08:03:50.99#ibcon#ireg 7 cls_cnt 0 2006.218.08:03:50.99#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.218.08:03:51.11#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.218.08:03:51.11#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.218.08:03:51.11#ibcon#enter wrdev, iclass 20, count 0 2006.218.08:03:51.11#ibcon#first serial, iclass 20, count 0 2006.218.08:03:51.11#ibcon#enter sib2, iclass 20, count 0 2006.218.08:03:51.11#ibcon#flushed, iclass 20, count 0 2006.218.08:03:51.11#ibcon#about to write, iclass 20, count 0 2006.218.08:03:51.11#ibcon#wrote, iclass 20, count 0 2006.218.08:03:51.11#ibcon#about to read 3, iclass 20, count 0 2006.218.08:03:51.13#ibcon#read 3, iclass 20, count 0 2006.218.08:03:51.13#ibcon#about to read 4, iclass 20, count 0 2006.218.08:03:51.13#ibcon#read 4, iclass 20, count 0 2006.218.08:03:51.13#ibcon#about to read 5, iclass 20, count 0 2006.218.08:03:51.13#ibcon#read 5, iclass 20, count 0 2006.218.08:03:51.13#ibcon#about to read 6, iclass 20, count 0 2006.218.08:03:51.13#ibcon#read 6, iclass 20, count 0 2006.218.08:03:51.13#ibcon#end of sib2, iclass 20, count 0 2006.218.08:03:51.13#ibcon#*mode == 0, iclass 20, count 0 2006.218.08:03:51.13#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.218.08:03:51.13#ibcon#[27=USB\r\n] 2006.218.08:03:51.13#ibcon#*before write, iclass 20, count 0 2006.218.08:03:51.13#ibcon#enter sib2, iclass 20, count 0 2006.218.08:03:51.13#ibcon#flushed, iclass 20, count 0 2006.218.08:03:51.13#ibcon#about to write, iclass 20, count 0 2006.218.08:03:51.13#ibcon#wrote, iclass 20, count 0 2006.218.08:03:51.13#ibcon#about to read 3, iclass 20, count 0 2006.218.08:03:51.16#ibcon#read 3, iclass 20, count 0 2006.218.08:03:51.16#ibcon#about to read 4, iclass 20, count 0 2006.218.08:03:51.16#ibcon#read 4, iclass 20, count 0 2006.218.08:03:51.16#ibcon#about to read 5, iclass 20, count 0 2006.218.08:03:51.16#ibcon#read 5, iclass 20, count 0 2006.218.08:03:51.16#ibcon#about to read 6, iclass 20, count 0 2006.218.08:03:51.16#ibcon#read 6, iclass 20, count 0 2006.218.08:03:51.16#ibcon#end of sib2, iclass 20, count 0 2006.218.08:03:51.16#ibcon#*after write, iclass 20, count 0 2006.218.08:03:51.16#ibcon#*before return 0, iclass 20, count 0 2006.218.08:03:51.16#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.218.08:03:51.16#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.218.08:03:51.16#ibcon#about to clear, iclass 20 cls_cnt 0 2006.218.08:03:51.16#ibcon#cleared, iclass 20 cls_cnt 0 2006.218.08:03:51.16$vc4f8/vblo=3,656.99 2006.218.08:03:51.16#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.218.08:03:51.16#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.218.08:03:51.16#ibcon#ireg 17 cls_cnt 0 2006.218.08:03:51.16#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.218.08:03:51.16#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.218.08:03:51.16#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.218.08:03:51.16#ibcon#enter wrdev, iclass 22, count 0 2006.218.08:03:51.16#ibcon#first serial, iclass 22, count 0 2006.218.08:03:51.16#ibcon#enter sib2, iclass 22, count 0 2006.218.08:03:51.16#ibcon#flushed, iclass 22, count 0 2006.218.08:03:51.16#ibcon#about to write, iclass 22, count 0 2006.218.08:03:51.16#ibcon#wrote, iclass 22, count 0 2006.218.08:03:51.16#ibcon#about to read 3, iclass 22, count 0 2006.218.08:03:51.18#ibcon#read 3, iclass 22, count 0 2006.218.08:03:51.18#ibcon#about to read 4, iclass 22, count 0 2006.218.08:03:51.18#ibcon#read 4, iclass 22, count 0 2006.218.08:03:51.18#ibcon#about to read 5, iclass 22, count 0 2006.218.08:03:51.18#ibcon#read 5, iclass 22, count 0 2006.218.08:03:51.18#ibcon#about to read 6, iclass 22, count 0 2006.218.08:03:51.18#ibcon#read 6, iclass 22, count 0 2006.218.08:03:51.18#ibcon#end of sib2, iclass 22, count 0 2006.218.08:03:51.18#ibcon#*mode == 0, iclass 22, count 0 2006.218.08:03:51.18#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.218.08:03:51.18#ibcon#[28=FRQ=03,656.99\r\n] 2006.218.08:03:51.18#ibcon#*before write, iclass 22, count 0 2006.218.08:03:51.18#ibcon#enter sib2, iclass 22, count 0 2006.218.08:03:51.18#ibcon#flushed, iclass 22, count 0 2006.218.08:03:51.18#ibcon#about to write, iclass 22, count 0 2006.218.08:03:51.18#ibcon#wrote, iclass 22, count 0 2006.218.08:03:51.18#ibcon#about to read 3, iclass 22, count 0 2006.218.08:03:51.22#ibcon#read 3, iclass 22, count 0 2006.218.08:03:51.22#ibcon#about to read 4, iclass 22, count 0 2006.218.08:03:51.22#ibcon#read 4, iclass 22, count 0 2006.218.08:03:51.22#ibcon#about to read 5, iclass 22, count 0 2006.218.08:03:51.22#ibcon#read 5, iclass 22, count 0 2006.218.08:03:51.22#ibcon#about to read 6, iclass 22, count 0 2006.218.08:03:51.22#ibcon#read 6, iclass 22, count 0 2006.218.08:03:51.22#ibcon#end of sib2, iclass 22, count 0 2006.218.08:03:51.22#ibcon#*after write, iclass 22, count 0 2006.218.08:03:51.22#ibcon#*before return 0, iclass 22, count 0 2006.218.08:03:51.22#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.218.08:03:51.22#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.218.08:03:51.22#ibcon#about to clear, iclass 22 cls_cnt 0 2006.218.08:03:51.22#ibcon#cleared, iclass 22 cls_cnt 0 2006.218.08:03:51.22$vc4f8/vb=3,4 2006.218.08:03:51.22#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.218.08:03:51.22#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.218.08:03:51.22#ibcon#ireg 11 cls_cnt 2 2006.218.08:03:51.22#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.218.08:03:51.28#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.218.08:03:51.28#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.218.08:03:51.28#ibcon#enter wrdev, iclass 24, count 2 2006.218.08:03:51.28#ibcon#first serial, iclass 24, count 2 2006.218.08:03:51.28#ibcon#enter sib2, iclass 24, count 2 2006.218.08:03:51.28#ibcon#flushed, iclass 24, count 2 2006.218.08:03:51.28#ibcon#about to write, iclass 24, count 2 2006.218.08:03:51.28#ibcon#wrote, iclass 24, count 2 2006.218.08:03:51.28#ibcon#about to read 3, iclass 24, count 2 2006.218.08:03:51.30#ibcon#read 3, iclass 24, count 2 2006.218.08:03:51.30#ibcon#about to read 4, iclass 24, count 2 2006.218.08:03:51.30#ibcon#read 4, iclass 24, count 2 2006.218.08:03:51.30#ibcon#about to read 5, iclass 24, count 2 2006.218.08:03:51.30#ibcon#read 5, iclass 24, count 2 2006.218.08:03:51.30#ibcon#about to read 6, iclass 24, count 2 2006.218.08:03:51.30#ibcon#read 6, iclass 24, count 2 2006.218.08:03:51.30#ibcon#end of sib2, iclass 24, count 2 2006.218.08:03:51.30#ibcon#*mode == 0, iclass 24, count 2 2006.218.08:03:51.30#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.218.08:03:51.30#ibcon#[27=AT03-04\r\n] 2006.218.08:03:51.30#ibcon#*before write, iclass 24, count 2 2006.218.08:03:51.30#ibcon#enter sib2, iclass 24, count 2 2006.218.08:03:51.30#ibcon#flushed, iclass 24, count 2 2006.218.08:03:51.30#ibcon#about to write, iclass 24, count 2 2006.218.08:03:51.30#ibcon#wrote, iclass 24, count 2 2006.218.08:03:51.30#ibcon#about to read 3, iclass 24, count 2 2006.218.08:03:51.33#ibcon#read 3, iclass 24, count 2 2006.218.08:03:51.33#ibcon#about to read 4, iclass 24, count 2 2006.218.08:03:51.33#ibcon#read 4, iclass 24, count 2 2006.218.08:03:51.33#ibcon#about to read 5, iclass 24, count 2 2006.218.08:03:51.33#ibcon#read 5, iclass 24, count 2 2006.218.08:03:51.33#ibcon#about to read 6, iclass 24, count 2 2006.218.08:03:51.33#ibcon#read 6, iclass 24, count 2 2006.218.08:03:51.33#ibcon#end of sib2, iclass 24, count 2 2006.218.08:03:51.33#ibcon#*after write, iclass 24, count 2 2006.218.08:03:51.33#ibcon#*before return 0, iclass 24, count 2 2006.218.08:03:51.33#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.218.08:03:51.33#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.218.08:03:51.33#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.218.08:03:51.33#ibcon#ireg 7 cls_cnt 0 2006.218.08:03:51.33#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.218.08:03:51.45#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.218.08:03:51.45#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.218.08:03:51.45#ibcon#enter wrdev, iclass 24, count 0 2006.218.08:03:51.45#ibcon#first serial, iclass 24, count 0 2006.218.08:03:51.45#ibcon#enter sib2, iclass 24, count 0 2006.218.08:03:51.45#ibcon#flushed, iclass 24, count 0 2006.218.08:03:51.45#ibcon#about to write, iclass 24, count 0 2006.218.08:03:51.45#ibcon#wrote, iclass 24, count 0 2006.218.08:03:51.45#ibcon#about to read 3, iclass 24, count 0 2006.218.08:03:51.47#ibcon#read 3, iclass 24, count 0 2006.218.08:03:51.47#ibcon#about to read 4, iclass 24, count 0 2006.218.08:03:51.47#ibcon#read 4, iclass 24, count 0 2006.218.08:03:51.47#ibcon#about to read 5, iclass 24, count 0 2006.218.08:03:51.47#ibcon#read 5, iclass 24, count 0 2006.218.08:03:51.47#ibcon#about to read 6, iclass 24, count 0 2006.218.08:03:51.47#ibcon#read 6, iclass 24, count 0 2006.218.08:03:51.47#ibcon#end of sib2, iclass 24, count 0 2006.218.08:03:51.47#ibcon#*mode == 0, iclass 24, count 0 2006.218.08:03:51.47#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.218.08:03:51.47#ibcon#[27=USB\r\n] 2006.218.08:03:51.47#ibcon#*before write, iclass 24, count 0 2006.218.08:03:51.47#ibcon#enter sib2, iclass 24, count 0 2006.218.08:03:51.47#ibcon#flushed, iclass 24, count 0 2006.218.08:03:51.47#ibcon#about to write, iclass 24, count 0 2006.218.08:03:51.47#ibcon#wrote, iclass 24, count 0 2006.218.08:03:51.47#ibcon#about to read 3, iclass 24, count 0 2006.218.08:03:51.50#ibcon#read 3, iclass 24, count 0 2006.218.08:03:51.50#ibcon#about to read 4, iclass 24, count 0 2006.218.08:03:51.50#ibcon#read 4, iclass 24, count 0 2006.218.08:03:51.50#ibcon#about to read 5, iclass 24, count 0 2006.218.08:03:51.50#ibcon#read 5, iclass 24, count 0 2006.218.08:03:51.50#ibcon#about to read 6, iclass 24, count 0 2006.218.08:03:51.50#ibcon#read 6, iclass 24, count 0 2006.218.08:03:51.50#ibcon#end of sib2, iclass 24, count 0 2006.218.08:03:51.50#ibcon#*after write, iclass 24, count 0 2006.218.08:03:51.50#ibcon#*before return 0, iclass 24, count 0 2006.218.08:03:51.50#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.218.08:03:51.50#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.218.08:03:51.50#ibcon#about to clear, iclass 24 cls_cnt 0 2006.218.08:03:51.50#ibcon#cleared, iclass 24 cls_cnt 0 2006.218.08:03:51.50$vc4f8/vblo=4,712.99 2006.218.08:03:51.50#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.218.08:03:51.50#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.218.08:03:51.50#ibcon#ireg 17 cls_cnt 0 2006.218.08:03:51.50#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.218.08:03:51.50#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.218.08:03:51.50#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.218.08:03:51.50#ibcon#enter wrdev, iclass 26, count 0 2006.218.08:03:51.50#ibcon#first serial, iclass 26, count 0 2006.218.08:03:51.50#ibcon#enter sib2, iclass 26, count 0 2006.218.08:03:51.50#ibcon#flushed, iclass 26, count 0 2006.218.08:03:51.50#ibcon#about to write, iclass 26, count 0 2006.218.08:03:51.50#ibcon#wrote, iclass 26, count 0 2006.218.08:03:51.50#ibcon#about to read 3, iclass 26, count 0 2006.218.08:03:51.52#ibcon#read 3, iclass 26, count 0 2006.218.08:03:51.52#ibcon#about to read 4, iclass 26, count 0 2006.218.08:03:51.52#ibcon#read 4, iclass 26, count 0 2006.218.08:03:51.52#ibcon#about to read 5, iclass 26, count 0 2006.218.08:03:51.52#ibcon#read 5, iclass 26, count 0 2006.218.08:03:51.52#ibcon#about to read 6, iclass 26, count 0 2006.218.08:03:51.52#ibcon#read 6, iclass 26, count 0 2006.218.08:03:51.52#ibcon#end of sib2, iclass 26, count 0 2006.218.08:03:51.52#ibcon#*mode == 0, iclass 26, count 0 2006.218.08:03:51.52#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.218.08:03:51.52#ibcon#[28=FRQ=04,712.99\r\n] 2006.218.08:03:51.52#ibcon#*before write, iclass 26, count 0 2006.218.08:03:51.52#ibcon#enter sib2, iclass 26, count 0 2006.218.08:03:51.52#ibcon#flushed, iclass 26, count 0 2006.218.08:03:51.52#ibcon#about to write, iclass 26, count 0 2006.218.08:03:51.52#ibcon#wrote, iclass 26, count 0 2006.218.08:03:51.52#ibcon#about to read 3, iclass 26, count 0 2006.218.08:03:51.56#ibcon#read 3, iclass 26, count 0 2006.218.08:03:51.56#ibcon#about to read 4, iclass 26, count 0 2006.218.08:03:51.56#ibcon#read 4, iclass 26, count 0 2006.218.08:03:51.56#ibcon#about to read 5, iclass 26, count 0 2006.218.08:03:51.56#ibcon#read 5, iclass 26, count 0 2006.218.08:03:51.56#ibcon#about to read 6, iclass 26, count 0 2006.218.08:03:51.56#ibcon#read 6, iclass 26, count 0 2006.218.08:03:51.56#ibcon#end of sib2, iclass 26, count 0 2006.218.08:03:51.56#ibcon#*after write, iclass 26, count 0 2006.218.08:03:51.56#ibcon#*before return 0, iclass 26, count 0 2006.218.08:03:51.56#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.218.08:03:51.56#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.218.08:03:51.56#ibcon#about to clear, iclass 26 cls_cnt 0 2006.218.08:03:51.56#ibcon#cleared, iclass 26 cls_cnt 0 2006.218.08:03:51.56$vc4f8/vb=4,4 2006.218.08:03:51.56#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.218.08:03:51.56#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.218.08:03:51.56#ibcon#ireg 11 cls_cnt 2 2006.218.08:03:51.56#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.218.08:03:51.62#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.218.08:03:51.62#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.218.08:03:51.62#ibcon#enter wrdev, iclass 28, count 2 2006.218.08:03:51.62#ibcon#first serial, iclass 28, count 2 2006.218.08:03:51.62#ibcon#enter sib2, iclass 28, count 2 2006.218.08:03:51.62#ibcon#flushed, iclass 28, count 2 2006.218.08:03:51.62#ibcon#about to write, iclass 28, count 2 2006.218.08:03:51.62#ibcon#wrote, iclass 28, count 2 2006.218.08:03:51.62#ibcon#about to read 3, iclass 28, count 2 2006.218.08:03:51.64#ibcon#read 3, iclass 28, count 2 2006.218.08:03:51.64#ibcon#about to read 4, iclass 28, count 2 2006.218.08:03:51.64#ibcon#read 4, iclass 28, count 2 2006.218.08:03:51.64#ibcon#about to read 5, iclass 28, count 2 2006.218.08:03:51.64#ibcon#read 5, iclass 28, count 2 2006.218.08:03:51.64#ibcon#about to read 6, iclass 28, count 2 2006.218.08:03:51.64#ibcon#read 6, iclass 28, count 2 2006.218.08:03:51.64#ibcon#end of sib2, iclass 28, count 2 2006.218.08:03:51.64#ibcon#*mode == 0, iclass 28, count 2 2006.218.08:03:51.64#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.218.08:03:51.64#ibcon#[27=AT04-04\r\n] 2006.218.08:03:51.64#ibcon#*before write, iclass 28, count 2 2006.218.08:03:51.64#ibcon#enter sib2, iclass 28, count 2 2006.218.08:03:51.64#ibcon#flushed, iclass 28, count 2 2006.218.08:03:51.64#ibcon#about to write, iclass 28, count 2 2006.218.08:03:51.64#ibcon#wrote, iclass 28, count 2 2006.218.08:03:51.64#ibcon#about to read 3, iclass 28, count 2 2006.218.08:03:51.67#ibcon#read 3, iclass 28, count 2 2006.218.08:03:51.67#ibcon#about to read 4, iclass 28, count 2 2006.218.08:03:51.67#ibcon#read 4, iclass 28, count 2 2006.218.08:03:51.67#ibcon#about to read 5, iclass 28, count 2 2006.218.08:03:51.67#ibcon#read 5, iclass 28, count 2 2006.218.08:03:51.67#ibcon#about to read 6, iclass 28, count 2 2006.218.08:03:51.67#ibcon#read 6, iclass 28, count 2 2006.218.08:03:51.67#ibcon#end of sib2, iclass 28, count 2 2006.218.08:03:51.67#ibcon#*after write, iclass 28, count 2 2006.218.08:03:51.67#ibcon#*before return 0, iclass 28, count 2 2006.218.08:03:51.67#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.218.08:03:51.67#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.218.08:03:51.67#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.218.08:03:51.67#ibcon#ireg 7 cls_cnt 0 2006.218.08:03:51.67#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.218.08:03:51.79#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.218.08:03:51.79#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.218.08:03:51.79#ibcon#enter wrdev, iclass 28, count 0 2006.218.08:03:51.79#ibcon#first serial, iclass 28, count 0 2006.218.08:03:51.79#ibcon#enter sib2, iclass 28, count 0 2006.218.08:03:51.79#ibcon#flushed, iclass 28, count 0 2006.218.08:03:51.79#ibcon#about to write, iclass 28, count 0 2006.218.08:03:51.79#ibcon#wrote, iclass 28, count 0 2006.218.08:03:51.79#ibcon#about to read 3, iclass 28, count 0 2006.218.08:03:51.81#ibcon#read 3, iclass 28, count 0 2006.218.08:03:51.81#ibcon#about to read 4, iclass 28, count 0 2006.218.08:03:51.81#ibcon#read 4, iclass 28, count 0 2006.218.08:03:51.81#ibcon#about to read 5, iclass 28, count 0 2006.218.08:03:51.81#ibcon#read 5, iclass 28, count 0 2006.218.08:03:51.81#ibcon#about to read 6, iclass 28, count 0 2006.218.08:03:51.81#ibcon#read 6, iclass 28, count 0 2006.218.08:03:51.81#ibcon#end of sib2, iclass 28, count 0 2006.218.08:03:51.81#ibcon#*mode == 0, iclass 28, count 0 2006.218.08:03:51.81#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.218.08:03:51.81#ibcon#[27=USB\r\n] 2006.218.08:03:51.81#ibcon#*before write, iclass 28, count 0 2006.218.08:03:51.81#ibcon#enter sib2, iclass 28, count 0 2006.218.08:03:51.81#ibcon#flushed, iclass 28, count 0 2006.218.08:03:51.81#ibcon#about to write, iclass 28, count 0 2006.218.08:03:51.81#ibcon#wrote, iclass 28, count 0 2006.218.08:03:51.81#ibcon#about to read 3, iclass 28, count 0 2006.218.08:03:51.84#ibcon#read 3, iclass 28, count 0 2006.218.08:03:51.84#ibcon#about to read 4, iclass 28, count 0 2006.218.08:03:51.84#ibcon#read 4, iclass 28, count 0 2006.218.08:03:51.84#ibcon#about to read 5, iclass 28, count 0 2006.218.08:03:51.84#ibcon#read 5, iclass 28, count 0 2006.218.08:03:51.84#ibcon#about to read 6, iclass 28, count 0 2006.218.08:03:51.84#ibcon#read 6, iclass 28, count 0 2006.218.08:03:51.84#ibcon#end of sib2, iclass 28, count 0 2006.218.08:03:51.84#ibcon#*after write, iclass 28, count 0 2006.218.08:03:51.84#ibcon#*before return 0, iclass 28, count 0 2006.218.08:03:51.84#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.218.08:03:51.84#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.218.08:03:51.84#ibcon#about to clear, iclass 28 cls_cnt 0 2006.218.08:03:51.84#ibcon#cleared, iclass 28 cls_cnt 0 2006.218.08:03:51.84$vc4f8/vblo=5,744.99 2006.218.08:03:51.84#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.218.08:03:51.84#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.218.08:03:51.84#ibcon#ireg 17 cls_cnt 0 2006.218.08:03:51.84#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.218.08:03:51.84#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.218.08:03:51.84#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.218.08:03:51.84#ibcon#enter wrdev, iclass 30, count 0 2006.218.08:03:51.84#ibcon#first serial, iclass 30, count 0 2006.218.08:03:51.84#ibcon#enter sib2, iclass 30, count 0 2006.218.08:03:51.84#ibcon#flushed, iclass 30, count 0 2006.218.08:03:51.84#ibcon#about to write, iclass 30, count 0 2006.218.08:03:51.84#ibcon#wrote, iclass 30, count 0 2006.218.08:03:51.84#ibcon#about to read 3, iclass 30, count 0 2006.218.08:03:51.87#ibcon#read 3, iclass 30, count 0 2006.218.08:03:51.87#ibcon#about to read 4, iclass 30, count 0 2006.218.08:03:51.87#ibcon#read 4, iclass 30, count 0 2006.218.08:03:51.87#ibcon#about to read 5, iclass 30, count 0 2006.218.08:03:51.87#ibcon#read 5, iclass 30, count 0 2006.218.08:03:51.87#ibcon#about to read 6, iclass 30, count 0 2006.218.08:03:51.87#ibcon#read 6, iclass 30, count 0 2006.218.08:03:51.87#ibcon#end of sib2, iclass 30, count 0 2006.218.08:03:51.87#ibcon#*mode == 0, iclass 30, count 0 2006.218.08:03:51.87#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.218.08:03:51.87#ibcon#[28=FRQ=05,744.99\r\n] 2006.218.08:03:51.87#ibcon#*before write, iclass 30, count 0 2006.218.08:03:51.87#ibcon#enter sib2, iclass 30, count 0 2006.218.08:03:51.87#ibcon#flushed, iclass 30, count 0 2006.218.08:03:51.87#ibcon#about to write, iclass 30, count 0 2006.218.08:03:51.87#ibcon#wrote, iclass 30, count 0 2006.218.08:03:51.87#ibcon#about to read 3, iclass 30, count 0 2006.218.08:03:51.91#ibcon#read 3, iclass 30, count 0 2006.218.08:03:51.91#ibcon#about to read 4, iclass 30, count 0 2006.218.08:03:51.91#ibcon#read 4, iclass 30, count 0 2006.218.08:03:51.91#ibcon#about to read 5, iclass 30, count 0 2006.218.08:03:51.91#ibcon#read 5, iclass 30, count 0 2006.218.08:03:51.91#ibcon#about to read 6, iclass 30, count 0 2006.218.08:03:51.91#ibcon#read 6, iclass 30, count 0 2006.218.08:03:51.91#ibcon#end of sib2, iclass 30, count 0 2006.218.08:03:51.91#ibcon#*after write, iclass 30, count 0 2006.218.08:03:51.91#ibcon#*before return 0, iclass 30, count 0 2006.218.08:03:51.91#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.218.08:03:51.91#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.218.08:03:51.91#ibcon#about to clear, iclass 30 cls_cnt 0 2006.218.08:03:51.91#ibcon#cleared, iclass 30 cls_cnt 0 2006.218.08:03:51.91$vc4f8/vb=5,4 2006.218.08:03:51.91#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.218.08:03:51.91#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.218.08:03:51.91#ibcon#ireg 11 cls_cnt 2 2006.218.08:03:51.91#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.218.08:03:51.96#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.218.08:03:51.96#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.218.08:03:51.96#ibcon#enter wrdev, iclass 32, count 2 2006.218.08:03:51.96#ibcon#first serial, iclass 32, count 2 2006.218.08:03:51.96#ibcon#enter sib2, iclass 32, count 2 2006.218.08:03:51.96#ibcon#flushed, iclass 32, count 2 2006.218.08:03:51.96#ibcon#about to write, iclass 32, count 2 2006.218.08:03:51.96#ibcon#wrote, iclass 32, count 2 2006.218.08:03:51.96#ibcon#about to read 3, iclass 32, count 2 2006.218.08:03:51.98#ibcon#read 3, iclass 32, count 2 2006.218.08:03:51.98#ibcon#about to read 4, iclass 32, count 2 2006.218.08:03:51.98#ibcon#read 4, iclass 32, count 2 2006.218.08:03:51.98#ibcon#about to read 5, iclass 32, count 2 2006.218.08:03:51.98#ibcon#read 5, iclass 32, count 2 2006.218.08:03:51.98#ibcon#about to read 6, iclass 32, count 2 2006.218.08:03:51.98#ibcon#read 6, iclass 32, count 2 2006.218.08:03:51.98#ibcon#end of sib2, iclass 32, count 2 2006.218.08:03:51.98#ibcon#*mode == 0, iclass 32, count 2 2006.218.08:03:51.98#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.218.08:03:51.98#ibcon#[27=AT05-04\r\n] 2006.218.08:03:51.98#ibcon#*before write, iclass 32, count 2 2006.218.08:03:51.98#ibcon#enter sib2, iclass 32, count 2 2006.218.08:03:51.98#ibcon#flushed, iclass 32, count 2 2006.218.08:03:51.98#ibcon#about to write, iclass 32, count 2 2006.218.08:03:51.98#ibcon#wrote, iclass 32, count 2 2006.218.08:03:51.98#ibcon#about to read 3, iclass 32, count 2 2006.218.08:03:52.01#ibcon#read 3, iclass 32, count 2 2006.218.08:03:52.01#ibcon#about to read 4, iclass 32, count 2 2006.218.08:03:52.01#ibcon#read 4, iclass 32, count 2 2006.218.08:03:52.01#ibcon#about to read 5, iclass 32, count 2 2006.218.08:03:52.01#ibcon#read 5, iclass 32, count 2 2006.218.08:03:52.01#ibcon#about to read 6, iclass 32, count 2 2006.218.08:03:52.01#ibcon#read 6, iclass 32, count 2 2006.218.08:03:52.01#ibcon#end of sib2, iclass 32, count 2 2006.218.08:03:52.01#ibcon#*after write, iclass 32, count 2 2006.218.08:03:52.01#ibcon#*before return 0, iclass 32, count 2 2006.218.08:03:52.01#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.218.08:03:52.01#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.218.08:03:52.01#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.218.08:03:52.01#ibcon#ireg 7 cls_cnt 0 2006.218.08:03:52.01#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.218.08:03:52.13#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.218.08:03:52.13#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.218.08:03:52.13#ibcon#enter wrdev, iclass 32, count 0 2006.218.08:03:52.13#ibcon#first serial, iclass 32, count 0 2006.218.08:03:52.13#ibcon#enter sib2, iclass 32, count 0 2006.218.08:03:52.13#ibcon#flushed, iclass 32, count 0 2006.218.08:03:52.13#ibcon#about to write, iclass 32, count 0 2006.218.08:03:52.13#ibcon#wrote, iclass 32, count 0 2006.218.08:03:52.13#ibcon#about to read 3, iclass 32, count 0 2006.218.08:03:52.15#ibcon#read 3, iclass 32, count 0 2006.218.08:03:52.15#ibcon#about to read 4, iclass 32, count 0 2006.218.08:03:52.15#ibcon#read 4, iclass 32, count 0 2006.218.08:03:52.15#ibcon#about to read 5, iclass 32, count 0 2006.218.08:03:52.15#ibcon#read 5, iclass 32, count 0 2006.218.08:03:52.15#ibcon#about to read 6, iclass 32, count 0 2006.218.08:03:52.15#ibcon#read 6, iclass 32, count 0 2006.218.08:03:52.15#ibcon#end of sib2, iclass 32, count 0 2006.218.08:03:52.15#ibcon#*mode == 0, iclass 32, count 0 2006.218.08:03:52.15#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.218.08:03:52.15#ibcon#[27=USB\r\n] 2006.218.08:03:52.15#ibcon#*before write, iclass 32, count 0 2006.218.08:03:52.15#ibcon#enter sib2, iclass 32, count 0 2006.218.08:03:52.15#ibcon#flushed, iclass 32, count 0 2006.218.08:03:52.15#ibcon#about to write, iclass 32, count 0 2006.218.08:03:52.15#ibcon#wrote, iclass 32, count 0 2006.218.08:03:52.15#ibcon#about to read 3, iclass 32, count 0 2006.218.08:03:52.18#ibcon#read 3, iclass 32, count 0 2006.218.08:03:52.18#ibcon#about to read 4, iclass 32, count 0 2006.218.08:03:52.18#ibcon#read 4, iclass 32, count 0 2006.218.08:03:52.18#ibcon#about to read 5, iclass 32, count 0 2006.218.08:03:52.18#ibcon#read 5, iclass 32, count 0 2006.218.08:03:52.18#ibcon#about to read 6, iclass 32, count 0 2006.218.08:03:52.18#ibcon#read 6, iclass 32, count 0 2006.218.08:03:52.18#ibcon#end of sib2, iclass 32, count 0 2006.218.08:03:52.18#ibcon#*after write, iclass 32, count 0 2006.218.08:03:52.18#ibcon#*before return 0, iclass 32, count 0 2006.218.08:03:52.18#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.218.08:03:52.18#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.218.08:03:52.18#ibcon#about to clear, iclass 32 cls_cnt 0 2006.218.08:03:52.18#ibcon#cleared, iclass 32 cls_cnt 0 2006.218.08:03:52.18$vc4f8/vblo=6,752.99 2006.218.08:03:52.18#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.218.08:03:52.18#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.218.08:03:52.18#ibcon#ireg 17 cls_cnt 0 2006.218.08:03:52.18#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.218.08:03:52.18#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.218.08:03:52.18#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.218.08:03:52.18#ibcon#enter wrdev, iclass 34, count 0 2006.218.08:03:52.18#ibcon#first serial, iclass 34, count 0 2006.218.08:03:52.18#ibcon#enter sib2, iclass 34, count 0 2006.218.08:03:52.18#ibcon#flushed, iclass 34, count 0 2006.218.08:03:52.18#ibcon#about to write, iclass 34, count 0 2006.218.08:03:52.18#ibcon#wrote, iclass 34, count 0 2006.218.08:03:52.18#ibcon#about to read 3, iclass 34, count 0 2006.218.08:03:52.20#ibcon#read 3, iclass 34, count 0 2006.218.08:03:52.20#ibcon#about to read 4, iclass 34, count 0 2006.218.08:03:52.20#ibcon#read 4, iclass 34, count 0 2006.218.08:03:52.20#ibcon#about to read 5, iclass 34, count 0 2006.218.08:03:52.20#ibcon#read 5, iclass 34, count 0 2006.218.08:03:52.20#ibcon#about to read 6, iclass 34, count 0 2006.218.08:03:52.20#ibcon#read 6, iclass 34, count 0 2006.218.08:03:52.20#ibcon#end of sib2, iclass 34, count 0 2006.218.08:03:52.20#ibcon#*mode == 0, iclass 34, count 0 2006.218.08:03:52.20#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.218.08:03:52.20#ibcon#[28=FRQ=06,752.99\r\n] 2006.218.08:03:52.20#ibcon#*before write, iclass 34, count 0 2006.218.08:03:52.20#ibcon#enter sib2, iclass 34, count 0 2006.218.08:03:52.20#ibcon#flushed, iclass 34, count 0 2006.218.08:03:52.20#ibcon#about to write, iclass 34, count 0 2006.218.08:03:52.20#ibcon#wrote, iclass 34, count 0 2006.218.08:03:52.20#ibcon#about to read 3, iclass 34, count 0 2006.218.08:03:52.24#ibcon#read 3, iclass 34, count 0 2006.218.08:03:52.24#ibcon#about to read 4, iclass 34, count 0 2006.218.08:03:52.24#ibcon#read 4, iclass 34, count 0 2006.218.08:03:52.24#ibcon#about to read 5, iclass 34, count 0 2006.218.08:03:52.24#ibcon#read 5, iclass 34, count 0 2006.218.08:03:52.24#ibcon#about to read 6, iclass 34, count 0 2006.218.08:03:52.24#ibcon#read 6, iclass 34, count 0 2006.218.08:03:52.24#ibcon#end of sib2, iclass 34, count 0 2006.218.08:03:52.24#ibcon#*after write, iclass 34, count 0 2006.218.08:03:52.24#ibcon#*before return 0, iclass 34, count 0 2006.218.08:03:52.24#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.218.08:03:52.24#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.218.08:03:52.24#ibcon#about to clear, iclass 34 cls_cnt 0 2006.218.08:03:52.24#ibcon#cleared, iclass 34 cls_cnt 0 2006.218.08:03:52.24$vc4f8/vb=6,4 2006.218.08:03:52.24#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.218.08:03:52.24#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.218.08:03:52.24#ibcon#ireg 11 cls_cnt 2 2006.218.08:03:52.24#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.218.08:03:52.30#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.218.08:03:52.30#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.218.08:03:52.30#ibcon#enter wrdev, iclass 36, count 2 2006.218.08:03:52.30#ibcon#first serial, iclass 36, count 2 2006.218.08:03:52.30#ibcon#enter sib2, iclass 36, count 2 2006.218.08:03:52.30#ibcon#flushed, iclass 36, count 2 2006.218.08:03:52.30#ibcon#about to write, iclass 36, count 2 2006.218.08:03:52.30#ibcon#wrote, iclass 36, count 2 2006.218.08:03:52.30#ibcon#about to read 3, iclass 36, count 2 2006.218.08:03:52.32#ibcon#read 3, iclass 36, count 2 2006.218.08:03:52.32#ibcon#about to read 4, iclass 36, count 2 2006.218.08:03:52.32#ibcon#read 4, iclass 36, count 2 2006.218.08:03:52.32#ibcon#about to read 5, iclass 36, count 2 2006.218.08:03:52.32#ibcon#read 5, iclass 36, count 2 2006.218.08:03:52.32#ibcon#about to read 6, iclass 36, count 2 2006.218.08:03:52.32#ibcon#read 6, iclass 36, count 2 2006.218.08:03:52.32#ibcon#end of sib2, iclass 36, count 2 2006.218.08:03:52.32#ibcon#*mode == 0, iclass 36, count 2 2006.218.08:03:52.32#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.218.08:03:52.32#ibcon#[27=AT06-04\r\n] 2006.218.08:03:52.32#ibcon#*before write, iclass 36, count 2 2006.218.08:03:52.32#ibcon#enter sib2, iclass 36, count 2 2006.218.08:03:52.32#ibcon#flushed, iclass 36, count 2 2006.218.08:03:52.32#ibcon#about to write, iclass 36, count 2 2006.218.08:03:52.32#ibcon#wrote, iclass 36, count 2 2006.218.08:03:52.32#ibcon#about to read 3, iclass 36, count 2 2006.218.08:03:52.35#ibcon#read 3, iclass 36, count 2 2006.218.08:03:52.35#ibcon#about to read 4, iclass 36, count 2 2006.218.08:03:52.35#ibcon#read 4, iclass 36, count 2 2006.218.08:03:52.35#ibcon#about to read 5, iclass 36, count 2 2006.218.08:03:52.35#ibcon#read 5, iclass 36, count 2 2006.218.08:03:52.35#ibcon#about to read 6, iclass 36, count 2 2006.218.08:03:52.35#ibcon#read 6, iclass 36, count 2 2006.218.08:03:52.35#ibcon#end of sib2, iclass 36, count 2 2006.218.08:03:52.35#ibcon#*after write, iclass 36, count 2 2006.218.08:03:52.35#ibcon#*before return 0, iclass 36, count 2 2006.218.08:03:52.35#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.218.08:03:52.35#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.218.08:03:52.35#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.218.08:03:52.35#ibcon#ireg 7 cls_cnt 0 2006.218.08:03:52.35#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.218.08:03:52.47#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.218.08:03:52.47#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.218.08:03:52.47#ibcon#enter wrdev, iclass 36, count 0 2006.218.08:03:52.47#ibcon#first serial, iclass 36, count 0 2006.218.08:03:52.47#ibcon#enter sib2, iclass 36, count 0 2006.218.08:03:52.47#ibcon#flushed, iclass 36, count 0 2006.218.08:03:52.47#ibcon#about to write, iclass 36, count 0 2006.218.08:03:52.47#ibcon#wrote, iclass 36, count 0 2006.218.08:03:52.47#ibcon#about to read 3, iclass 36, count 0 2006.218.08:03:52.49#ibcon#read 3, iclass 36, count 0 2006.218.08:03:52.49#ibcon#about to read 4, iclass 36, count 0 2006.218.08:03:52.49#ibcon#read 4, iclass 36, count 0 2006.218.08:03:52.49#ibcon#about to read 5, iclass 36, count 0 2006.218.08:03:52.49#ibcon#read 5, iclass 36, count 0 2006.218.08:03:52.49#ibcon#about to read 6, iclass 36, count 0 2006.218.08:03:52.49#ibcon#read 6, iclass 36, count 0 2006.218.08:03:52.49#ibcon#end of sib2, iclass 36, count 0 2006.218.08:03:52.49#ibcon#*mode == 0, iclass 36, count 0 2006.218.08:03:52.49#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.218.08:03:52.49#ibcon#[27=USB\r\n] 2006.218.08:03:52.49#ibcon#*before write, iclass 36, count 0 2006.218.08:03:52.49#ibcon#enter sib2, iclass 36, count 0 2006.218.08:03:52.49#ibcon#flushed, iclass 36, count 0 2006.218.08:03:52.49#ibcon#about to write, iclass 36, count 0 2006.218.08:03:52.49#ibcon#wrote, iclass 36, count 0 2006.218.08:03:52.49#ibcon#about to read 3, iclass 36, count 0 2006.218.08:03:52.52#ibcon#read 3, iclass 36, count 0 2006.218.08:03:52.52#ibcon#about to read 4, iclass 36, count 0 2006.218.08:03:52.52#ibcon#read 4, iclass 36, count 0 2006.218.08:03:52.52#ibcon#about to read 5, iclass 36, count 0 2006.218.08:03:52.52#ibcon#read 5, iclass 36, count 0 2006.218.08:03:52.52#ibcon#about to read 6, iclass 36, count 0 2006.218.08:03:52.52#ibcon#read 6, iclass 36, count 0 2006.218.08:03:52.52#ibcon#end of sib2, iclass 36, count 0 2006.218.08:03:52.52#ibcon#*after write, iclass 36, count 0 2006.218.08:03:52.52#ibcon#*before return 0, iclass 36, count 0 2006.218.08:03:52.52#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.218.08:03:52.52#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.218.08:03:52.52#ibcon#about to clear, iclass 36 cls_cnt 0 2006.218.08:03:52.52#ibcon#cleared, iclass 36 cls_cnt 0 2006.218.08:03:52.52$vc4f8/vabw=wide 2006.218.08:03:52.52#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.218.08:03:52.52#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.218.08:03:52.52#ibcon#ireg 8 cls_cnt 0 2006.218.08:03:52.52#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.218.08:03:52.52#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.218.08:03:52.52#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.218.08:03:52.52#ibcon#enter wrdev, iclass 38, count 0 2006.218.08:03:52.52#ibcon#first serial, iclass 38, count 0 2006.218.08:03:52.52#ibcon#enter sib2, iclass 38, count 0 2006.218.08:03:52.52#ibcon#flushed, iclass 38, count 0 2006.218.08:03:52.52#ibcon#about to write, iclass 38, count 0 2006.218.08:03:52.52#ibcon#wrote, iclass 38, count 0 2006.218.08:03:52.52#ibcon#about to read 3, iclass 38, count 0 2006.218.08:03:52.54#ibcon#read 3, iclass 38, count 0 2006.218.08:03:52.54#ibcon#about to read 4, iclass 38, count 0 2006.218.08:03:52.54#ibcon#read 4, iclass 38, count 0 2006.218.08:03:52.54#ibcon#about to read 5, iclass 38, count 0 2006.218.08:03:52.54#ibcon#read 5, iclass 38, count 0 2006.218.08:03:52.54#ibcon#about to read 6, iclass 38, count 0 2006.218.08:03:52.54#ibcon#read 6, iclass 38, count 0 2006.218.08:03:52.54#ibcon#end of sib2, iclass 38, count 0 2006.218.08:03:52.54#ibcon#*mode == 0, iclass 38, count 0 2006.218.08:03:52.54#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.218.08:03:52.54#ibcon#[25=BW32\r\n] 2006.218.08:03:52.54#ibcon#*before write, iclass 38, count 0 2006.218.08:03:52.54#ibcon#enter sib2, iclass 38, count 0 2006.218.08:03:52.54#ibcon#flushed, iclass 38, count 0 2006.218.08:03:52.54#ibcon#about to write, iclass 38, count 0 2006.218.08:03:52.54#ibcon#wrote, iclass 38, count 0 2006.218.08:03:52.54#ibcon#about to read 3, iclass 38, count 0 2006.218.08:03:52.57#ibcon#read 3, iclass 38, count 0 2006.218.08:03:52.57#ibcon#about to read 4, iclass 38, count 0 2006.218.08:03:52.57#ibcon#read 4, iclass 38, count 0 2006.218.08:03:52.57#ibcon#about to read 5, iclass 38, count 0 2006.218.08:03:52.57#ibcon#read 5, iclass 38, count 0 2006.218.08:03:52.57#ibcon#about to read 6, iclass 38, count 0 2006.218.08:03:52.57#ibcon#read 6, iclass 38, count 0 2006.218.08:03:52.57#ibcon#end of sib2, iclass 38, count 0 2006.218.08:03:52.57#ibcon#*after write, iclass 38, count 0 2006.218.08:03:52.57#ibcon#*before return 0, iclass 38, count 0 2006.218.08:03:52.57#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.218.08:03:52.57#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.218.08:03:52.57#ibcon#about to clear, iclass 38 cls_cnt 0 2006.218.08:03:52.57#ibcon#cleared, iclass 38 cls_cnt 0 2006.218.08:03:52.57$vc4f8/vbbw=wide 2006.218.08:03:52.57#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.218.08:03:52.57#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.218.08:03:52.57#ibcon#ireg 8 cls_cnt 0 2006.218.08:03:52.57#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.218.08:03:52.64#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.218.08:03:52.64#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.218.08:03:52.64#ibcon#enter wrdev, iclass 40, count 0 2006.218.08:03:52.64#ibcon#first serial, iclass 40, count 0 2006.218.08:03:52.64#ibcon#enter sib2, iclass 40, count 0 2006.218.08:03:52.64#ibcon#flushed, iclass 40, count 0 2006.218.08:03:52.64#ibcon#about to write, iclass 40, count 0 2006.218.08:03:52.64#ibcon#wrote, iclass 40, count 0 2006.218.08:03:52.64#ibcon#about to read 3, iclass 40, count 0 2006.218.08:03:52.66#ibcon#read 3, iclass 40, count 0 2006.218.08:03:52.66#ibcon#about to read 4, iclass 40, count 0 2006.218.08:03:52.66#ibcon#read 4, iclass 40, count 0 2006.218.08:03:52.66#ibcon#about to read 5, iclass 40, count 0 2006.218.08:03:52.66#ibcon#read 5, iclass 40, count 0 2006.218.08:03:52.66#ibcon#about to read 6, iclass 40, count 0 2006.218.08:03:52.66#ibcon#read 6, iclass 40, count 0 2006.218.08:03:52.66#ibcon#end of sib2, iclass 40, count 0 2006.218.08:03:52.66#ibcon#*mode == 0, iclass 40, count 0 2006.218.08:03:52.66#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.218.08:03:52.66#ibcon#[27=BW32\r\n] 2006.218.08:03:52.66#ibcon#*before write, iclass 40, count 0 2006.218.08:03:52.66#ibcon#enter sib2, iclass 40, count 0 2006.218.08:03:52.66#ibcon#flushed, iclass 40, count 0 2006.218.08:03:52.66#ibcon#about to write, iclass 40, count 0 2006.218.08:03:52.66#ibcon#wrote, iclass 40, count 0 2006.218.08:03:52.66#ibcon#about to read 3, iclass 40, count 0 2006.218.08:03:52.69#ibcon#read 3, iclass 40, count 0 2006.218.08:03:52.69#ibcon#about to read 4, iclass 40, count 0 2006.218.08:03:52.69#ibcon#read 4, iclass 40, count 0 2006.218.08:03:52.69#ibcon#about to read 5, iclass 40, count 0 2006.218.08:03:52.69#ibcon#read 5, iclass 40, count 0 2006.218.08:03:52.69#ibcon#about to read 6, iclass 40, count 0 2006.218.08:03:52.69#ibcon#read 6, iclass 40, count 0 2006.218.08:03:52.69#ibcon#end of sib2, iclass 40, count 0 2006.218.08:03:52.69#ibcon#*after write, iclass 40, count 0 2006.218.08:03:52.69#ibcon#*before return 0, iclass 40, count 0 2006.218.08:03:52.69#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.218.08:03:52.69#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.218.08:03:52.69#ibcon#about to clear, iclass 40 cls_cnt 0 2006.218.08:03:52.69#ibcon#cleared, iclass 40 cls_cnt 0 2006.218.08:03:52.69$4f8m12a/ifd4f 2006.218.08:03:52.69$ifd4f/lo= 2006.218.08:03:52.69$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.218.08:03:52.69$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.218.08:03:52.69$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.218.08:03:52.69$ifd4f/patch= 2006.218.08:03:52.69$ifd4f/patch=lo1,a1,a2,a3,a4 2006.218.08:03:52.69$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.218.08:03:52.69$ifd4f/patch=lo3,a5,a6,a7,a8 2006.218.08:03:52.69$4f8m12a/"form=m,16.000,1:2 2006.218.08:03:52.69$4f8m12a/"tpicd 2006.218.08:03:52.69$4f8m12a/echo=off 2006.218.08:03:52.69$4f8m12a/xlog=off 2006.218.08:03:52.69:!2006.218.08:04:20 2006.218.08:04:01.14#trakl#Source acquired 2006.218.08:04:02.14#flagr#flagr/antenna,acquired 2006.218.08:04:20.00:preob 2006.218.08:04:21.14/onsource/TRACKING 2006.218.08:04:21.14:!2006.218.08:04:30 2006.218.08:04:30.00:data_valid=on 2006.218.08:04:30.00:midob 2006.218.08:04:30.14/onsource/TRACKING 2006.218.08:04:30.14/wx/30.99,1007.5,72 2006.218.08:04:30.26/cable/+6.3849E-03 2006.218.08:04:31.35/va/01,05,usb,yes,33,35 2006.218.08:04:31.35/va/02,04,usb,yes,31,32 2006.218.08:04:31.35/va/03,04,usb,yes,29,29 2006.218.08:04:31.35/va/04,04,usb,yes,33,35 2006.218.08:04:31.35/va/05,07,usb,yes,35,37 2006.218.08:04:31.35/va/06,06,usb,yes,34,34 2006.218.08:04:31.35/va/07,06,usb,yes,34,34 2006.218.08:04:31.35/va/08,07,usb,yes,33,32 2006.218.08:04:31.58/valo/01,532.99,yes,locked 2006.218.08:04:31.58/valo/02,572.99,yes,locked 2006.218.08:04:31.58/valo/03,672.99,yes,locked 2006.218.08:04:31.58/valo/04,832.99,yes,locked 2006.218.08:04:31.58/valo/05,652.99,yes,locked 2006.218.08:04:31.58/valo/06,772.99,yes,locked 2006.218.08:04:31.58/valo/07,832.99,yes,locked 2006.218.08:04:31.58/valo/08,852.99,yes,locked 2006.218.08:04:32.67/vb/01,04,usb,yes,31,30 2006.218.08:04:32.67/vb/02,04,usb,yes,33,34 2006.218.08:04:32.67/vb/03,04,usb,yes,29,33 2006.218.08:04:32.67/vb/04,04,usb,yes,30,30 2006.218.08:04:32.67/vb/05,04,usb,yes,28,32 2006.218.08:04:32.67/vb/06,04,usb,yes,29,32 2006.218.08:04:32.67/vb/07,04,usb,yes,32,31 2006.218.08:04:32.67/vb/08,04,usb,yes,29,32 2006.218.08:04:32.90/vblo/01,632.99,yes,locked 2006.218.08:04:32.90/vblo/02,640.99,yes,locked 2006.218.08:04:32.90/vblo/03,656.99,yes,locked 2006.218.08:04:32.90/vblo/04,712.99,yes,locked 2006.218.08:04:32.90/vblo/05,744.99,yes,locked 2006.218.08:04:32.90/vblo/06,752.99,yes,locked 2006.218.08:04:32.90/vblo/07,734.99,yes,locked 2006.218.08:04:32.90/vblo/08,744.99,yes,locked 2006.218.08:04:33.05/vabw/8 2006.218.08:04:33.21/vbbw/8 2006.218.08:04:33.30/xfe/off,on,16.0 2006.218.08:04:33.68/ifatt/23,28,28,28 2006.218.08:04:34.07/fmout-gps/S +4.67E-07 2006.218.08:04:34.15:!2006.218.08:05:30 2006.218.08:05:30.01:data_valid=off 2006.218.08:05:30.01:postob 2006.218.08:05:30.19/cable/+6.3847E-03 2006.218.08:05:30.19/wx/30.97,1007.5,72 2006.218.08:05:31.07/fmout-gps/S +4.66E-07 2006.218.08:05:31.07:scan_name=218-0806,k06218,60 2006.218.08:05:31.08:source=1128+385,113053.28,381518.5,2000.0,cw 2006.218.08:05:31.14#flagr#flagr/antenna,new-source 2006.218.08:05:32.14:checkk5 2006.218.08:05:32.51/chk_autoobs//k5ts1/ autoobs is running! 2006.218.08:05:32.86/chk_autoobs//k5ts2/ autoobs is running! 2006.218.08:05:33.23/chk_autoobs//k5ts3/ autoobs is running! 2006.218.08:05:33.61/chk_autoobs//k5ts4/ autoobs is running! 2006.218.08:05:33.98/chk_obsdata//k5ts1/T2180804??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.08:05:34.35/chk_obsdata//k5ts2/T2180804??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.08:05:34.71/chk_obsdata//k5ts3/T2180804??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.08:05:35.09/chk_obsdata//k5ts4/T2180804??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.08:05:35.78/k5log//k5ts1_log_newline 2006.218.08:05:36.46/k5log//k5ts2_log_newline 2006.218.08:05:37.15/k5log//k5ts3_log_newline 2006.218.08:05:37.84/k5log//k5ts4_log_newline 2006.218.08:05:37.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.218.08:05:37.87:4f8m12a=2 2006.218.08:05:37.87$4f8m12a/echo=on 2006.218.08:05:37.87$4f8m12a/pcalon 2006.218.08:05:37.87$pcalon/"no phase cal control is implemented here 2006.218.08:05:37.87$4f8m12a/"tpicd=stop 2006.218.08:05:37.87$4f8m12a/vc4f8 2006.218.08:05:37.87$vc4f8/valo=1,532.99 2006.218.08:05:37.87#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.218.08:05:37.87#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.218.08:05:37.87#ibcon#ireg 17 cls_cnt 0 2006.218.08:05:37.87#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.218.08:05:37.87#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.218.08:05:37.87#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.218.08:05:37.87#ibcon#enter wrdev, iclass 11, count 0 2006.218.08:05:37.87#ibcon#first serial, iclass 11, count 0 2006.218.08:05:37.87#ibcon#enter sib2, iclass 11, count 0 2006.218.08:05:37.87#ibcon#flushed, iclass 11, count 0 2006.218.08:05:37.87#ibcon#about to write, iclass 11, count 0 2006.218.08:05:37.87#ibcon#wrote, iclass 11, count 0 2006.218.08:05:37.87#ibcon#about to read 3, iclass 11, count 0 2006.218.08:05:37.91#ibcon#read 3, iclass 11, count 0 2006.218.08:05:37.91#ibcon#about to read 4, iclass 11, count 0 2006.218.08:05:37.91#ibcon#read 4, iclass 11, count 0 2006.218.08:05:37.91#ibcon#about to read 5, iclass 11, count 0 2006.218.08:05:37.91#ibcon#read 5, iclass 11, count 0 2006.218.08:05:37.91#ibcon#about to read 6, iclass 11, count 0 2006.218.08:05:37.91#ibcon#read 6, iclass 11, count 0 2006.218.08:05:37.91#ibcon#end of sib2, iclass 11, count 0 2006.218.08:05:37.91#ibcon#*mode == 0, iclass 11, count 0 2006.218.08:05:37.91#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.218.08:05:37.91#ibcon#[26=FRQ=01,532.99\r\n] 2006.218.08:05:37.91#ibcon#*before write, iclass 11, count 0 2006.218.08:05:37.91#ibcon#enter sib2, iclass 11, count 0 2006.218.08:05:37.91#ibcon#flushed, iclass 11, count 0 2006.218.08:05:37.91#ibcon#about to write, iclass 11, count 0 2006.218.08:05:37.91#ibcon#wrote, iclass 11, count 0 2006.218.08:05:37.91#ibcon#about to read 3, iclass 11, count 0 2006.218.08:05:37.95#ibcon#read 3, iclass 11, count 0 2006.218.08:05:37.95#ibcon#about to read 4, iclass 11, count 0 2006.218.08:05:37.95#ibcon#read 4, iclass 11, count 0 2006.218.08:05:37.95#ibcon#about to read 5, iclass 11, count 0 2006.218.08:05:37.95#ibcon#read 5, iclass 11, count 0 2006.218.08:05:37.95#ibcon#about to read 6, iclass 11, count 0 2006.218.08:05:37.95#ibcon#read 6, iclass 11, count 0 2006.218.08:05:37.95#ibcon#end of sib2, iclass 11, count 0 2006.218.08:05:37.95#ibcon#*after write, iclass 11, count 0 2006.218.08:05:37.95#ibcon#*before return 0, iclass 11, count 0 2006.218.08:05:37.95#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.218.08:05:37.95#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.218.08:05:37.95#ibcon#about to clear, iclass 11 cls_cnt 0 2006.218.08:05:37.95#ibcon#cleared, iclass 11 cls_cnt 0 2006.218.08:05:37.95$vc4f8/va=1,5 2006.218.08:05:37.95#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.218.08:05:37.95#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.218.08:05:37.95#ibcon#ireg 11 cls_cnt 2 2006.218.08:05:37.95#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.218.08:05:37.95#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.218.08:05:37.95#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.218.08:05:37.95#ibcon#enter wrdev, iclass 13, count 2 2006.218.08:05:37.95#ibcon#first serial, iclass 13, count 2 2006.218.08:05:37.95#ibcon#enter sib2, iclass 13, count 2 2006.218.08:05:37.95#ibcon#flushed, iclass 13, count 2 2006.218.08:05:37.95#ibcon#about to write, iclass 13, count 2 2006.218.08:05:37.95#ibcon#wrote, iclass 13, count 2 2006.218.08:05:37.95#ibcon#about to read 3, iclass 13, count 2 2006.218.08:05:37.97#ibcon#read 3, iclass 13, count 2 2006.218.08:05:37.97#ibcon#about to read 4, iclass 13, count 2 2006.218.08:05:37.97#ibcon#read 4, iclass 13, count 2 2006.218.08:05:37.97#ibcon#about to read 5, iclass 13, count 2 2006.218.08:05:37.97#ibcon#read 5, iclass 13, count 2 2006.218.08:05:37.97#ibcon#about to read 6, iclass 13, count 2 2006.218.08:05:37.97#ibcon#read 6, iclass 13, count 2 2006.218.08:05:37.97#ibcon#end of sib2, iclass 13, count 2 2006.218.08:05:37.97#ibcon#*mode == 0, iclass 13, count 2 2006.218.08:05:37.97#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.218.08:05:37.97#ibcon#[25=AT01-05\r\n] 2006.218.08:05:37.97#ibcon#*before write, iclass 13, count 2 2006.218.08:05:37.97#ibcon#enter sib2, iclass 13, count 2 2006.218.08:05:37.97#ibcon#flushed, iclass 13, count 2 2006.218.08:05:37.97#ibcon#about to write, iclass 13, count 2 2006.218.08:05:37.97#ibcon#wrote, iclass 13, count 2 2006.218.08:05:37.97#ibcon#about to read 3, iclass 13, count 2 2006.218.08:05:38.00#ibcon#read 3, iclass 13, count 2 2006.218.08:05:38.00#ibcon#about to read 4, iclass 13, count 2 2006.218.08:05:38.00#ibcon#read 4, iclass 13, count 2 2006.218.08:05:38.00#ibcon#about to read 5, iclass 13, count 2 2006.218.08:05:38.00#ibcon#read 5, iclass 13, count 2 2006.218.08:05:38.00#ibcon#about to read 6, iclass 13, count 2 2006.218.08:05:38.00#ibcon#read 6, iclass 13, count 2 2006.218.08:05:38.00#ibcon#end of sib2, iclass 13, count 2 2006.218.08:05:38.00#ibcon#*after write, iclass 13, count 2 2006.218.08:05:38.00#ibcon#*before return 0, iclass 13, count 2 2006.218.08:05:38.00#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.218.08:05:38.00#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.218.08:05:38.00#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.218.08:05:38.00#ibcon#ireg 7 cls_cnt 0 2006.218.08:05:38.00#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.218.08:05:38.12#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.218.08:05:38.12#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.218.08:05:38.12#ibcon#enter wrdev, iclass 13, count 0 2006.218.08:05:38.12#ibcon#first serial, iclass 13, count 0 2006.218.08:05:38.12#ibcon#enter sib2, iclass 13, count 0 2006.218.08:05:38.12#ibcon#flushed, iclass 13, count 0 2006.218.08:05:38.12#ibcon#about to write, iclass 13, count 0 2006.218.08:05:38.12#ibcon#wrote, iclass 13, count 0 2006.218.08:05:38.12#ibcon#about to read 3, iclass 13, count 0 2006.218.08:05:38.14#ibcon#read 3, iclass 13, count 0 2006.218.08:05:38.14#ibcon#about to read 4, iclass 13, count 0 2006.218.08:05:38.14#ibcon#read 4, iclass 13, count 0 2006.218.08:05:38.14#ibcon#about to read 5, iclass 13, count 0 2006.218.08:05:38.14#ibcon#read 5, iclass 13, count 0 2006.218.08:05:38.14#ibcon#about to read 6, iclass 13, count 0 2006.218.08:05:38.14#ibcon#read 6, iclass 13, count 0 2006.218.08:05:38.14#ibcon#end of sib2, iclass 13, count 0 2006.218.08:05:38.14#ibcon#*mode == 0, iclass 13, count 0 2006.218.08:05:38.14#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.218.08:05:38.14#ibcon#[25=USB\r\n] 2006.218.08:05:38.14#ibcon#*before write, iclass 13, count 0 2006.218.08:05:38.14#ibcon#enter sib2, iclass 13, count 0 2006.218.08:05:38.14#ibcon#flushed, iclass 13, count 0 2006.218.08:05:38.14#ibcon#about to write, iclass 13, count 0 2006.218.08:05:38.14#ibcon#wrote, iclass 13, count 0 2006.218.08:05:38.14#ibcon#about to read 3, iclass 13, count 0 2006.218.08:05:38.17#ibcon#read 3, iclass 13, count 0 2006.218.08:05:38.17#ibcon#about to read 4, iclass 13, count 0 2006.218.08:05:38.17#ibcon#read 4, iclass 13, count 0 2006.218.08:05:38.17#ibcon#about to read 5, iclass 13, count 0 2006.218.08:05:38.17#ibcon#read 5, iclass 13, count 0 2006.218.08:05:38.17#ibcon#about to read 6, iclass 13, count 0 2006.218.08:05:38.17#ibcon#read 6, iclass 13, count 0 2006.218.08:05:38.17#ibcon#end of sib2, iclass 13, count 0 2006.218.08:05:38.17#ibcon#*after write, iclass 13, count 0 2006.218.08:05:38.17#ibcon#*before return 0, iclass 13, count 0 2006.218.08:05:38.17#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.218.08:05:38.17#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.218.08:05:38.17#ibcon#about to clear, iclass 13 cls_cnt 0 2006.218.08:05:38.17#ibcon#cleared, iclass 13 cls_cnt 0 2006.218.08:05:38.17$vc4f8/valo=2,572.99 2006.218.08:05:38.17#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.218.08:05:38.17#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.218.08:05:38.17#ibcon#ireg 17 cls_cnt 0 2006.218.08:05:38.17#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.218.08:05:38.17#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.218.08:05:38.17#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.218.08:05:38.17#ibcon#enter wrdev, iclass 15, count 0 2006.218.08:05:38.17#ibcon#first serial, iclass 15, count 0 2006.218.08:05:38.17#ibcon#enter sib2, iclass 15, count 0 2006.218.08:05:38.17#ibcon#flushed, iclass 15, count 0 2006.218.08:05:38.17#ibcon#about to write, iclass 15, count 0 2006.218.08:05:38.17#ibcon#wrote, iclass 15, count 0 2006.218.08:05:38.17#ibcon#about to read 3, iclass 15, count 0 2006.218.08:05:38.19#ibcon#read 3, iclass 15, count 0 2006.218.08:05:38.19#ibcon#about to read 4, iclass 15, count 0 2006.218.08:05:38.19#ibcon#read 4, iclass 15, count 0 2006.218.08:05:38.19#ibcon#about to read 5, iclass 15, count 0 2006.218.08:05:38.19#ibcon#read 5, iclass 15, count 0 2006.218.08:05:38.19#ibcon#about to read 6, iclass 15, count 0 2006.218.08:05:38.19#ibcon#read 6, iclass 15, count 0 2006.218.08:05:38.19#ibcon#end of sib2, iclass 15, count 0 2006.218.08:05:38.19#ibcon#*mode == 0, iclass 15, count 0 2006.218.08:05:38.19#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.218.08:05:38.19#ibcon#[26=FRQ=02,572.99\r\n] 2006.218.08:05:38.19#ibcon#*before write, iclass 15, count 0 2006.218.08:05:38.19#ibcon#enter sib2, iclass 15, count 0 2006.218.08:05:38.19#ibcon#flushed, iclass 15, count 0 2006.218.08:05:38.19#ibcon#about to write, iclass 15, count 0 2006.218.08:05:38.19#ibcon#wrote, iclass 15, count 0 2006.218.08:05:38.19#ibcon#about to read 3, iclass 15, count 0 2006.218.08:05:38.23#ibcon#read 3, iclass 15, count 0 2006.218.08:05:38.23#ibcon#about to read 4, iclass 15, count 0 2006.218.08:05:38.23#ibcon#read 4, iclass 15, count 0 2006.218.08:05:38.23#ibcon#about to read 5, iclass 15, count 0 2006.218.08:05:38.23#ibcon#read 5, iclass 15, count 0 2006.218.08:05:38.23#ibcon#about to read 6, iclass 15, count 0 2006.218.08:05:38.23#ibcon#read 6, iclass 15, count 0 2006.218.08:05:38.23#ibcon#end of sib2, iclass 15, count 0 2006.218.08:05:38.23#ibcon#*after write, iclass 15, count 0 2006.218.08:05:38.23#ibcon#*before return 0, iclass 15, count 0 2006.218.08:05:38.23#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.218.08:05:38.23#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.218.08:05:38.23#ibcon#about to clear, iclass 15 cls_cnt 0 2006.218.08:05:38.23#ibcon#cleared, iclass 15 cls_cnt 0 2006.218.08:05:38.23$vc4f8/va=2,4 2006.218.08:05:38.23#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.218.08:05:38.23#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.218.08:05:38.23#ibcon#ireg 11 cls_cnt 2 2006.218.08:05:38.23#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.218.08:05:38.30#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.218.08:05:38.30#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.218.08:05:38.30#ibcon#enter wrdev, iclass 17, count 2 2006.218.08:05:38.30#ibcon#first serial, iclass 17, count 2 2006.218.08:05:38.30#ibcon#enter sib2, iclass 17, count 2 2006.218.08:05:38.30#ibcon#flushed, iclass 17, count 2 2006.218.08:05:38.30#ibcon#about to write, iclass 17, count 2 2006.218.08:05:38.30#ibcon#wrote, iclass 17, count 2 2006.218.08:05:38.30#ibcon#about to read 3, iclass 17, count 2 2006.218.08:05:38.31#ibcon#read 3, iclass 17, count 2 2006.218.08:05:38.31#ibcon#about to read 4, iclass 17, count 2 2006.218.08:05:38.31#ibcon#read 4, iclass 17, count 2 2006.218.08:05:38.31#ibcon#about to read 5, iclass 17, count 2 2006.218.08:05:38.31#ibcon#read 5, iclass 17, count 2 2006.218.08:05:38.31#ibcon#about to read 6, iclass 17, count 2 2006.218.08:05:38.31#ibcon#read 6, iclass 17, count 2 2006.218.08:05:38.31#ibcon#end of sib2, iclass 17, count 2 2006.218.08:05:38.31#ibcon#*mode == 0, iclass 17, count 2 2006.218.08:05:38.31#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.218.08:05:38.31#ibcon#[25=AT02-04\r\n] 2006.218.08:05:38.31#ibcon#*before write, iclass 17, count 2 2006.218.08:05:38.31#ibcon#enter sib2, iclass 17, count 2 2006.218.08:05:38.31#ibcon#flushed, iclass 17, count 2 2006.218.08:05:38.31#ibcon#about to write, iclass 17, count 2 2006.218.08:05:38.31#ibcon#wrote, iclass 17, count 2 2006.218.08:05:38.31#ibcon#about to read 3, iclass 17, count 2 2006.218.08:05:38.34#ibcon#read 3, iclass 17, count 2 2006.218.08:05:38.34#ibcon#about to read 4, iclass 17, count 2 2006.218.08:05:38.34#ibcon#read 4, iclass 17, count 2 2006.218.08:05:38.34#ibcon#about to read 5, iclass 17, count 2 2006.218.08:05:38.34#ibcon#read 5, iclass 17, count 2 2006.218.08:05:38.34#ibcon#about to read 6, iclass 17, count 2 2006.218.08:05:38.34#ibcon#read 6, iclass 17, count 2 2006.218.08:05:38.34#ibcon#end of sib2, iclass 17, count 2 2006.218.08:05:38.34#ibcon#*after write, iclass 17, count 2 2006.218.08:05:38.34#ibcon#*before return 0, iclass 17, count 2 2006.218.08:05:38.34#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.218.08:05:38.34#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.218.08:05:38.34#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.218.08:05:38.34#ibcon#ireg 7 cls_cnt 0 2006.218.08:05:38.34#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.218.08:05:38.47#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.218.08:05:38.47#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.218.08:05:38.47#ibcon#enter wrdev, iclass 17, count 0 2006.218.08:05:38.47#ibcon#first serial, iclass 17, count 0 2006.218.08:05:38.47#ibcon#enter sib2, iclass 17, count 0 2006.218.08:05:38.47#ibcon#flushed, iclass 17, count 0 2006.218.08:05:38.47#ibcon#about to write, iclass 17, count 0 2006.218.08:05:38.47#ibcon#wrote, iclass 17, count 0 2006.218.08:05:38.47#ibcon#about to read 3, iclass 17, count 0 2006.218.08:05:38.49#ibcon#read 3, iclass 17, count 0 2006.218.08:05:38.49#ibcon#about to read 4, iclass 17, count 0 2006.218.08:05:38.49#ibcon#read 4, iclass 17, count 0 2006.218.08:05:38.49#ibcon#about to read 5, iclass 17, count 0 2006.218.08:05:38.49#ibcon#read 5, iclass 17, count 0 2006.218.08:05:38.49#ibcon#about to read 6, iclass 17, count 0 2006.218.08:05:38.49#ibcon#read 6, iclass 17, count 0 2006.218.08:05:38.49#ibcon#end of sib2, iclass 17, count 0 2006.218.08:05:38.49#ibcon#*mode == 0, iclass 17, count 0 2006.218.08:05:38.49#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.218.08:05:38.49#ibcon#[25=USB\r\n] 2006.218.08:05:38.49#ibcon#*before write, iclass 17, count 0 2006.218.08:05:38.49#ibcon#enter sib2, iclass 17, count 0 2006.218.08:05:38.49#ibcon#flushed, iclass 17, count 0 2006.218.08:05:38.49#ibcon#about to write, iclass 17, count 0 2006.218.08:05:38.49#ibcon#wrote, iclass 17, count 0 2006.218.08:05:38.49#ibcon#about to read 3, iclass 17, count 0 2006.218.08:05:38.52#ibcon#read 3, iclass 17, count 0 2006.218.08:05:38.52#ibcon#about to read 4, iclass 17, count 0 2006.218.08:05:38.52#ibcon#read 4, iclass 17, count 0 2006.218.08:05:38.52#ibcon#about to read 5, iclass 17, count 0 2006.218.08:05:38.52#ibcon#read 5, iclass 17, count 0 2006.218.08:05:38.52#ibcon#about to read 6, iclass 17, count 0 2006.218.08:05:38.52#ibcon#read 6, iclass 17, count 0 2006.218.08:05:38.52#ibcon#end of sib2, iclass 17, count 0 2006.218.08:05:38.52#ibcon#*after write, iclass 17, count 0 2006.218.08:05:38.52#ibcon#*before return 0, iclass 17, count 0 2006.218.08:05:38.52#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.218.08:05:38.52#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.218.08:05:38.52#ibcon#about to clear, iclass 17 cls_cnt 0 2006.218.08:05:38.52#ibcon#cleared, iclass 17 cls_cnt 0 2006.218.08:05:38.52$vc4f8/valo=3,672.99 2006.218.08:05:38.52#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.218.08:05:38.52#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.218.08:05:38.52#ibcon#ireg 17 cls_cnt 0 2006.218.08:05:38.52#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.218.08:05:38.52#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.218.08:05:38.52#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.218.08:05:38.52#ibcon#enter wrdev, iclass 19, count 0 2006.218.08:05:38.52#ibcon#first serial, iclass 19, count 0 2006.218.08:05:38.52#ibcon#enter sib2, iclass 19, count 0 2006.218.08:05:38.52#ibcon#flushed, iclass 19, count 0 2006.218.08:05:38.52#ibcon#about to write, iclass 19, count 0 2006.218.08:05:38.52#ibcon#wrote, iclass 19, count 0 2006.218.08:05:38.52#ibcon#about to read 3, iclass 19, count 0 2006.218.08:05:38.55#ibcon#read 3, iclass 19, count 0 2006.218.08:05:38.55#ibcon#about to read 4, iclass 19, count 0 2006.218.08:05:38.55#ibcon#read 4, iclass 19, count 0 2006.218.08:05:38.55#ibcon#about to read 5, iclass 19, count 0 2006.218.08:05:38.55#ibcon#read 5, iclass 19, count 0 2006.218.08:05:38.55#ibcon#about to read 6, iclass 19, count 0 2006.218.08:05:38.55#ibcon#read 6, iclass 19, count 0 2006.218.08:05:38.55#ibcon#end of sib2, iclass 19, count 0 2006.218.08:05:38.55#ibcon#*mode == 0, iclass 19, count 0 2006.218.08:05:38.55#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.218.08:05:38.55#ibcon#[26=FRQ=03,672.99\r\n] 2006.218.08:05:38.55#ibcon#*before write, iclass 19, count 0 2006.218.08:05:38.55#ibcon#enter sib2, iclass 19, count 0 2006.218.08:05:38.55#ibcon#flushed, iclass 19, count 0 2006.218.08:05:38.55#ibcon#about to write, iclass 19, count 0 2006.218.08:05:38.55#ibcon#wrote, iclass 19, count 0 2006.218.08:05:38.55#ibcon#about to read 3, iclass 19, count 0 2006.218.08:05:38.59#ibcon#read 3, iclass 19, count 0 2006.218.08:05:38.59#ibcon#about to read 4, iclass 19, count 0 2006.218.08:05:38.59#ibcon#read 4, iclass 19, count 0 2006.218.08:05:38.59#ibcon#about to read 5, iclass 19, count 0 2006.218.08:05:38.59#ibcon#read 5, iclass 19, count 0 2006.218.08:05:38.59#ibcon#about to read 6, iclass 19, count 0 2006.218.08:05:38.59#ibcon#read 6, iclass 19, count 0 2006.218.08:05:38.59#ibcon#end of sib2, iclass 19, count 0 2006.218.08:05:38.59#ibcon#*after write, iclass 19, count 0 2006.218.08:05:38.59#ibcon#*before return 0, iclass 19, count 0 2006.218.08:05:38.59#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.218.08:05:38.59#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.218.08:05:38.59#ibcon#about to clear, iclass 19 cls_cnt 0 2006.218.08:05:38.59#ibcon#cleared, iclass 19 cls_cnt 0 2006.218.08:05:38.59$vc4f8/va=3,4 2006.218.08:05:38.59#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.218.08:05:38.59#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.218.08:05:38.59#ibcon#ireg 11 cls_cnt 2 2006.218.08:05:38.59#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.218.08:05:38.64#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.218.08:05:38.64#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.218.08:05:38.64#ibcon#enter wrdev, iclass 21, count 2 2006.218.08:05:38.64#ibcon#first serial, iclass 21, count 2 2006.218.08:05:38.64#ibcon#enter sib2, iclass 21, count 2 2006.218.08:05:38.64#ibcon#flushed, iclass 21, count 2 2006.218.08:05:38.64#ibcon#about to write, iclass 21, count 2 2006.218.08:05:38.64#ibcon#wrote, iclass 21, count 2 2006.218.08:05:38.64#ibcon#about to read 3, iclass 21, count 2 2006.218.08:05:38.66#ibcon#read 3, iclass 21, count 2 2006.218.08:05:38.66#ibcon#about to read 4, iclass 21, count 2 2006.218.08:05:38.66#ibcon#read 4, iclass 21, count 2 2006.218.08:05:38.66#ibcon#about to read 5, iclass 21, count 2 2006.218.08:05:38.66#ibcon#read 5, iclass 21, count 2 2006.218.08:05:38.66#ibcon#about to read 6, iclass 21, count 2 2006.218.08:05:38.66#ibcon#read 6, iclass 21, count 2 2006.218.08:05:38.66#ibcon#end of sib2, iclass 21, count 2 2006.218.08:05:38.66#ibcon#*mode == 0, iclass 21, count 2 2006.218.08:05:38.66#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.218.08:05:38.66#ibcon#[25=AT03-04\r\n] 2006.218.08:05:38.66#ibcon#*before write, iclass 21, count 2 2006.218.08:05:38.66#ibcon#enter sib2, iclass 21, count 2 2006.218.08:05:38.66#ibcon#flushed, iclass 21, count 2 2006.218.08:05:38.66#ibcon#about to write, iclass 21, count 2 2006.218.08:05:38.66#ibcon#wrote, iclass 21, count 2 2006.218.08:05:38.66#ibcon#about to read 3, iclass 21, count 2 2006.218.08:05:38.69#ibcon#read 3, iclass 21, count 2 2006.218.08:05:38.69#ibcon#about to read 4, iclass 21, count 2 2006.218.08:05:38.69#ibcon#read 4, iclass 21, count 2 2006.218.08:05:38.69#ibcon#about to read 5, iclass 21, count 2 2006.218.08:05:38.69#ibcon#read 5, iclass 21, count 2 2006.218.08:05:38.69#ibcon#about to read 6, iclass 21, count 2 2006.218.08:05:38.69#ibcon#read 6, iclass 21, count 2 2006.218.08:05:38.69#ibcon#end of sib2, iclass 21, count 2 2006.218.08:05:38.69#ibcon#*after write, iclass 21, count 2 2006.218.08:05:38.69#ibcon#*before return 0, iclass 21, count 2 2006.218.08:05:38.69#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.218.08:05:38.69#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.218.08:05:38.69#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.218.08:05:38.69#ibcon#ireg 7 cls_cnt 0 2006.218.08:05:38.69#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.218.08:05:38.81#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.218.08:05:38.81#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.218.08:05:38.81#ibcon#enter wrdev, iclass 21, count 0 2006.218.08:05:38.81#ibcon#first serial, iclass 21, count 0 2006.218.08:05:38.81#ibcon#enter sib2, iclass 21, count 0 2006.218.08:05:38.81#ibcon#flushed, iclass 21, count 0 2006.218.08:05:38.81#ibcon#about to write, iclass 21, count 0 2006.218.08:05:38.81#ibcon#wrote, iclass 21, count 0 2006.218.08:05:38.81#ibcon#about to read 3, iclass 21, count 0 2006.218.08:05:38.83#ibcon#read 3, iclass 21, count 0 2006.218.08:05:38.83#ibcon#about to read 4, iclass 21, count 0 2006.218.08:05:38.83#ibcon#read 4, iclass 21, count 0 2006.218.08:05:38.83#ibcon#about to read 5, iclass 21, count 0 2006.218.08:05:38.83#ibcon#read 5, iclass 21, count 0 2006.218.08:05:38.83#ibcon#about to read 6, iclass 21, count 0 2006.218.08:05:38.83#ibcon#read 6, iclass 21, count 0 2006.218.08:05:38.83#ibcon#end of sib2, iclass 21, count 0 2006.218.08:05:38.83#ibcon#*mode == 0, iclass 21, count 0 2006.218.08:05:38.83#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.218.08:05:38.83#ibcon#[25=USB\r\n] 2006.218.08:05:38.83#ibcon#*before write, iclass 21, count 0 2006.218.08:05:38.83#ibcon#enter sib2, iclass 21, count 0 2006.218.08:05:38.83#ibcon#flushed, iclass 21, count 0 2006.218.08:05:38.83#ibcon#about to write, iclass 21, count 0 2006.218.08:05:38.83#ibcon#wrote, iclass 21, count 0 2006.218.08:05:38.83#ibcon#about to read 3, iclass 21, count 0 2006.218.08:05:38.86#ibcon#read 3, iclass 21, count 0 2006.218.08:05:38.86#ibcon#about to read 4, iclass 21, count 0 2006.218.08:05:38.86#ibcon#read 4, iclass 21, count 0 2006.218.08:05:38.86#ibcon#about to read 5, iclass 21, count 0 2006.218.08:05:38.86#ibcon#read 5, iclass 21, count 0 2006.218.08:05:38.86#ibcon#about to read 6, iclass 21, count 0 2006.218.08:05:38.86#ibcon#read 6, iclass 21, count 0 2006.218.08:05:38.86#ibcon#end of sib2, iclass 21, count 0 2006.218.08:05:38.86#ibcon#*after write, iclass 21, count 0 2006.218.08:05:38.86#ibcon#*before return 0, iclass 21, count 0 2006.218.08:05:38.86#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.218.08:05:38.86#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.218.08:05:38.86#ibcon#about to clear, iclass 21 cls_cnt 0 2006.218.08:05:38.86#ibcon#cleared, iclass 21 cls_cnt 0 2006.218.08:05:38.86$vc4f8/valo=4,832.99 2006.218.08:05:38.86#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.218.08:05:38.86#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.218.08:05:38.86#ibcon#ireg 17 cls_cnt 0 2006.218.08:05:38.86#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.218.08:05:38.86#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.218.08:05:38.86#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.218.08:05:38.86#ibcon#enter wrdev, iclass 23, count 0 2006.218.08:05:38.86#ibcon#first serial, iclass 23, count 0 2006.218.08:05:38.86#ibcon#enter sib2, iclass 23, count 0 2006.218.08:05:38.86#ibcon#flushed, iclass 23, count 0 2006.218.08:05:38.86#ibcon#about to write, iclass 23, count 0 2006.218.08:05:38.86#ibcon#wrote, iclass 23, count 0 2006.218.08:05:38.86#ibcon#about to read 3, iclass 23, count 0 2006.218.08:05:38.88#ibcon#read 3, iclass 23, count 0 2006.218.08:05:38.88#ibcon#about to read 4, iclass 23, count 0 2006.218.08:05:38.88#ibcon#read 4, iclass 23, count 0 2006.218.08:05:38.88#ibcon#about to read 5, iclass 23, count 0 2006.218.08:05:38.88#ibcon#read 5, iclass 23, count 0 2006.218.08:05:38.88#ibcon#about to read 6, iclass 23, count 0 2006.218.08:05:38.88#ibcon#read 6, iclass 23, count 0 2006.218.08:05:38.88#ibcon#end of sib2, iclass 23, count 0 2006.218.08:05:38.88#ibcon#*mode == 0, iclass 23, count 0 2006.218.08:05:38.88#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.218.08:05:38.88#ibcon#[26=FRQ=04,832.99\r\n] 2006.218.08:05:38.88#ibcon#*before write, iclass 23, count 0 2006.218.08:05:38.88#ibcon#enter sib2, iclass 23, count 0 2006.218.08:05:38.88#ibcon#flushed, iclass 23, count 0 2006.218.08:05:38.88#ibcon#about to write, iclass 23, count 0 2006.218.08:05:38.88#ibcon#wrote, iclass 23, count 0 2006.218.08:05:38.88#ibcon#about to read 3, iclass 23, count 0 2006.218.08:05:38.92#ibcon#read 3, iclass 23, count 0 2006.218.08:05:38.92#ibcon#about to read 4, iclass 23, count 0 2006.218.08:05:38.92#ibcon#read 4, iclass 23, count 0 2006.218.08:05:38.92#ibcon#about to read 5, iclass 23, count 0 2006.218.08:05:38.92#ibcon#read 5, iclass 23, count 0 2006.218.08:05:38.92#ibcon#about to read 6, iclass 23, count 0 2006.218.08:05:38.92#ibcon#read 6, iclass 23, count 0 2006.218.08:05:38.92#ibcon#end of sib2, iclass 23, count 0 2006.218.08:05:38.92#ibcon#*after write, iclass 23, count 0 2006.218.08:05:38.92#ibcon#*before return 0, iclass 23, count 0 2006.218.08:05:38.92#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.218.08:05:38.92#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.218.08:05:38.92#ibcon#about to clear, iclass 23 cls_cnt 0 2006.218.08:05:38.92#ibcon#cleared, iclass 23 cls_cnt 0 2006.218.08:05:38.92$vc4f8/va=4,4 2006.218.08:05:38.92#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.218.08:05:38.92#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.218.08:05:38.92#ibcon#ireg 11 cls_cnt 2 2006.218.08:05:38.92#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.218.08:05:38.98#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.218.08:05:38.98#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.218.08:05:38.98#ibcon#enter wrdev, iclass 25, count 2 2006.218.08:05:38.98#ibcon#first serial, iclass 25, count 2 2006.218.08:05:38.98#ibcon#enter sib2, iclass 25, count 2 2006.218.08:05:38.98#ibcon#flushed, iclass 25, count 2 2006.218.08:05:38.98#ibcon#about to write, iclass 25, count 2 2006.218.08:05:38.98#ibcon#wrote, iclass 25, count 2 2006.218.08:05:38.98#ibcon#about to read 3, iclass 25, count 2 2006.218.08:05:39.00#ibcon#read 3, iclass 25, count 2 2006.218.08:05:39.00#ibcon#about to read 4, iclass 25, count 2 2006.218.08:05:39.00#ibcon#read 4, iclass 25, count 2 2006.218.08:05:39.00#ibcon#about to read 5, iclass 25, count 2 2006.218.08:05:39.00#ibcon#read 5, iclass 25, count 2 2006.218.08:05:39.00#ibcon#about to read 6, iclass 25, count 2 2006.218.08:05:39.00#ibcon#read 6, iclass 25, count 2 2006.218.08:05:39.00#ibcon#end of sib2, iclass 25, count 2 2006.218.08:05:39.00#ibcon#*mode == 0, iclass 25, count 2 2006.218.08:05:39.00#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.218.08:05:39.00#ibcon#[25=AT04-04\r\n] 2006.218.08:05:39.00#ibcon#*before write, iclass 25, count 2 2006.218.08:05:39.00#ibcon#enter sib2, iclass 25, count 2 2006.218.08:05:39.00#ibcon#flushed, iclass 25, count 2 2006.218.08:05:39.00#ibcon#about to write, iclass 25, count 2 2006.218.08:05:39.00#ibcon#wrote, iclass 25, count 2 2006.218.08:05:39.00#ibcon#about to read 3, iclass 25, count 2 2006.218.08:05:39.03#ibcon#read 3, iclass 25, count 2 2006.218.08:05:39.03#ibcon#about to read 4, iclass 25, count 2 2006.218.08:05:39.03#ibcon#read 4, iclass 25, count 2 2006.218.08:05:39.03#ibcon#about to read 5, iclass 25, count 2 2006.218.08:05:39.03#ibcon#read 5, iclass 25, count 2 2006.218.08:05:39.03#ibcon#about to read 6, iclass 25, count 2 2006.218.08:05:39.03#ibcon#read 6, iclass 25, count 2 2006.218.08:05:39.03#ibcon#end of sib2, iclass 25, count 2 2006.218.08:05:39.03#ibcon#*after write, iclass 25, count 2 2006.218.08:05:39.03#ibcon#*before return 0, iclass 25, count 2 2006.218.08:05:39.03#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.218.08:05:39.03#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.218.08:05:39.03#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.218.08:05:39.03#ibcon#ireg 7 cls_cnt 0 2006.218.08:05:39.03#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.218.08:05:39.15#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.218.08:05:39.15#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.218.08:05:39.15#ibcon#enter wrdev, iclass 25, count 0 2006.218.08:05:39.15#ibcon#first serial, iclass 25, count 0 2006.218.08:05:39.15#ibcon#enter sib2, iclass 25, count 0 2006.218.08:05:39.15#ibcon#flushed, iclass 25, count 0 2006.218.08:05:39.15#ibcon#about to write, iclass 25, count 0 2006.218.08:05:39.15#ibcon#wrote, iclass 25, count 0 2006.218.08:05:39.15#ibcon#about to read 3, iclass 25, count 0 2006.218.08:05:39.17#ibcon#read 3, iclass 25, count 0 2006.218.08:05:39.17#ibcon#about to read 4, iclass 25, count 0 2006.218.08:05:39.17#ibcon#read 4, iclass 25, count 0 2006.218.08:05:39.17#ibcon#about to read 5, iclass 25, count 0 2006.218.08:05:39.17#ibcon#read 5, iclass 25, count 0 2006.218.08:05:39.17#ibcon#about to read 6, iclass 25, count 0 2006.218.08:05:39.17#ibcon#read 6, iclass 25, count 0 2006.218.08:05:39.17#ibcon#end of sib2, iclass 25, count 0 2006.218.08:05:39.17#ibcon#*mode == 0, iclass 25, count 0 2006.218.08:05:39.17#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.218.08:05:39.17#ibcon#[25=USB\r\n] 2006.218.08:05:39.17#ibcon#*before write, iclass 25, count 0 2006.218.08:05:39.17#ibcon#enter sib2, iclass 25, count 0 2006.218.08:05:39.17#ibcon#flushed, iclass 25, count 0 2006.218.08:05:39.17#ibcon#about to write, iclass 25, count 0 2006.218.08:05:39.17#ibcon#wrote, iclass 25, count 0 2006.218.08:05:39.17#ibcon#about to read 3, iclass 25, count 0 2006.218.08:05:39.20#ibcon#read 3, iclass 25, count 0 2006.218.08:05:39.20#ibcon#about to read 4, iclass 25, count 0 2006.218.08:05:39.20#ibcon#read 4, iclass 25, count 0 2006.218.08:05:39.20#ibcon#about to read 5, iclass 25, count 0 2006.218.08:05:39.20#ibcon#read 5, iclass 25, count 0 2006.218.08:05:39.20#ibcon#about to read 6, iclass 25, count 0 2006.218.08:05:39.20#ibcon#read 6, iclass 25, count 0 2006.218.08:05:39.20#ibcon#end of sib2, iclass 25, count 0 2006.218.08:05:39.20#ibcon#*after write, iclass 25, count 0 2006.218.08:05:39.20#ibcon#*before return 0, iclass 25, count 0 2006.218.08:05:39.20#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.218.08:05:39.20#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.218.08:05:39.20#ibcon#about to clear, iclass 25 cls_cnt 0 2006.218.08:05:39.20#ibcon#cleared, iclass 25 cls_cnt 0 2006.218.08:05:39.20$vc4f8/valo=5,652.99 2006.218.08:05:39.20#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.218.08:05:39.20#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.218.08:05:39.20#ibcon#ireg 17 cls_cnt 0 2006.218.08:05:39.20#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.218.08:05:39.20#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.218.08:05:39.20#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.218.08:05:39.20#ibcon#enter wrdev, iclass 27, count 0 2006.218.08:05:39.20#ibcon#first serial, iclass 27, count 0 2006.218.08:05:39.20#ibcon#enter sib2, iclass 27, count 0 2006.218.08:05:39.20#ibcon#flushed, iclass 27, count 0 2006.218.08:05:39.20#ibcon#about to write, iclass 27, count 0 2006.218.08:05:39.20#ibcon#wrote, iclass 27, count 0 2006.218.08:05:39.20#ibcon#about to read 3, iclass 27, count 0 2006.218.08:05:39.22#ibcon#read 3, iclass 27, count 0 2006.218.08:05:39.22#ibcon#about to read 4, iclass 27, count 0 2006.218.08:05:39.22#ibcon#read 4, iclass 27, count 0 2006.218.08:05:39.22#ibcon#about to read 5, iclass 27, count 0 2006.218.08:05:39.22#ibcon#read 5, iclass 27, count 0 2006.218.08:05:39.22#ibcon#about to read 6, iclass 27, count 0 2006.218.08:05:39.22#ibcon#read 6, iclass 27, count 0 2006.218.08:05:39.22#ibcon#end of sib2, iclass 27, count 0 2006.218.08:05:39.22#ibcon#*mode == 0, iclass 27, count 0 2006.218.08:05:39.22#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.218.08:05:39.22#ibcon#[26=FRQ=05,652.99\r\n] 2006.218.08:05:39.22#ibcon#*before write, iclass 27, count 0 2006.218.08:05:39.22#ibcon#enter sib2, iclass 27, count 0 2006.218.08:05:39.22#ibcon#flushed, iclass 27, count 0 2006.218.08:05:39.22#ibcon#about to write, iclass 27, count 0 2006.218.08:05:39.22#ibcon#wrote, iclass 27, count 0 2006.218.08:05:39.22#ibcon#about to read 3, iclass 27, count 0 2006.218.08:05:39.26#ibcon#read 3, iclass 27, count 0 2006.218.08:05:39.26#ibcon#about to read 4, iclass 27, count 0 2006.218.08:05:39.26#ibcon#read 4, iclass 27, count 0 2006.218.08:05:39.26#ibcon#about to read 5, iclass 27, count 0 2006.218.08:05:39.26#ibcon#read 5, iclass 27, count 0 2006.218.08:05:39.26#ibcon#about to read 6, iclass 27, count 0 2006.218.08:05:39.26#ibcon#read 6, iclass 27, count 0 2006.218.08:05:39.26#ibcon#end of sib2, iclass 27, count 0 2006.218.08:05:39.26#ibcon#*after write, iclass 27, count 0 2006.218.08:05:39.26#ibcon#*before return 0, iclass 27, count 0 2006.218.08:05:39.26#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.218.08:05:39.26#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.218.08:05:39.26#ibcon#about to clear, iclass 27 cls_cnt 0 2006.218.08:05:39.26#ibcon#cleared, iclass 27 cls_cnt 0 2006.218.08:05:39.26$vc4f8/va=5,7 2006.218.08:05:39.26#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.218.08:05:39.26#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.218.08:05:39.26#ibcon#ireg 11 cls_cnt 2 2006.218.08:05:39.26#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.218.08:05:39.32#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.218.08:05:39.32#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.218.08:05:39.32#ibcon#enter wrdev, iclass 29, count 2 2006.218.08:05:39.32#ibcon#first serial, iclass 29, count 2 2006.218.08:05:39.32#ibcon#enter sib2, iclass 29, count 2 2006.218.08:05:39.32#ibcon#flushed, iclass 29, count 2 2006.218.08:05:39.32#ibcon#about to write, iclass 29, count 2 2006.218.08:05:39.32#ibcon#wrote, iclass 29, count 2 2006.218.08:05:39.32#ibcon#about to read 3, iclass 29, count 2 2006.218.08:05:39.34#ibcon#read 3, iclass 29, count 2 2006.218.08:05:39.34#ibcon#about to read 4, iclass 29, count 2 2006.218.08:05:39.34#ibcon#read 4, iclass 29, count 2 2006.218.08:05:39.34#ibcon#about to read 5, iclass 29, count 2 2006.218.08:05:39.34#ibcon#read 5, iclass 29, count 2 2006.218.08:05:39.34#ibcon#about to read 6, iclass 29, count 2 2006.218.08:05:39.34#ibcon#read 6, iclass 29, count 2 2006.218.08:05:39.34#ibcon#end of sib2, iclass 29, count 2 2006.218.08:05:39.34#ibcon#*mode == 0, iclass 29, count 2 2006.218.08:05:39.34#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.218.08:05:39.34#ibcon#[25=AT05-07\r\n] 2006.218.08:05:39.34#ibcon#*before write, iclass 29, count 2 2006.218.08:05:39.34#ibcon#enter sib2, iclass 29, count 2 2006.218.08:05:39.34#ibcon#flushed, iclass 29, count 2 2006.218.08:05:39.34#ibcon#about to write, iclass 29, count 2 2006.218.08:05:39.34#ibcon#wrote, iclass 29, count 2 2006.218.08:05:39.34#ibcon#about to read 3, iclass 29, count 2 2006.218.08:05:39.37#ibcon#read 3, iclass 29, count 2 2006.218.08:05:39.37#ibcon#about to read 4, iclass 29, count 2 2006.218.08:05:39.37#ibcon#read 4, iclass 29, count 2 2006.218.08:05:39.37#ibcon#about to read 5, iclass 29, count 2 2006.218.08:05:39.37#ibcon#read 5, iclass 29, count 2 2006.218.08:05:39.37#ibcon#about to read 6, iclass 29, count 2 2006.218.08:05:39.37#ibcon#read 6, iclass 29, count 2 2006.218.08:05:39.37#ibcon#end of sib2, iclass 29, count 2 2006.218.08:05:39.37#ibcon#*after write, iclass 29, count 2 2006.218.08:05:39.37#ibcon#*before return 0, iclass 29, count 2 2006.218.08:05:39.37#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.218.08:05:39.37#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.218.08:05:39.37#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.218.08:05:39.37#ibcon#ireg 7 cls_cnt 0 2006.218.08:05:39.37#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.218.08:05:39.49#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.218.08:05:39.49#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.218.08:05:39.49#ibcon#enter wrdev, iclass 29, count 0 2006.218.08:05:39.49#ibcon#first serial, iclass 29, count 0 2006.218.08:05:39.49#ibcon#enter sib2, iclass 29, count 0 2006.218.08:05:39.49#ibcon#flushed, iclass 29, count 0 2006.218.08:05:39.49#ibcon#about to write, iclass 29, count 0 2006.218.08:05:39.49#ibcon#wrote, iclass 29, count 0 2006.218.08:05:39.49#ibcon#about to read 3, iclass 29, count 0 2006.218.08:05:39.51#ibcon#read 3, iclass 29, count 0 2006.218.08:05:39.51#ibcon#about to read 4, iclass 29, count 0 2006.218.08:05:39.51#ibcon#read 4, iclass 29, count 0 2006.218.08:05:39.51#ibcon#about to read 5, iclass 29, count 0 2006.218.08:05:39.51#ibcon#read 5, iclass 29, count 0 2006.218.08:05:39.51#ibcon#about to read 6, iclass 29, count 0 2006.218.08:05:39.51#ibcon#read 6, iclass 29, count 0 2006.218.08:05:39.51#ibcon#end of sib2, iclass 29, count 0 2006.218.08:05:39.51#ibcon#*mode == 0, iclass 29, count 0 2006.218.08:05:39.51#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.218.08:05:39.51#ibcon#[25=USB\r\n] 2006.218.08:05:39.51#ibcon#*before write, iclass 29, count 0 2006.218.08:05:39.51#ibcon#enter sib2, iclass 29, count 0 2006.218.08:05:39.51#ibcon#flushed, iclass 29, count 0 2006.218.08:05:39.51#ibcon#about to write, iclass 29, count 0 2006.218.08:05:39.51#ibcon#wrote, iclass 29, count 0 2006.218.08:05:39.51#ibcon#about to read 3, iclass 29, count 0 2006.218.08:05:39.54#ibcon#read 3, iclass 29, count 0 2006.218.08:05:39.54#ibcon#about to read 4, iclass 29, count 0 2006.218.08:05:39.54#ibcon#read 4, iclass 29, count 0 2006.218.08:05:39.54#ibcon#about to read 5, iclass 29, count 0 2006.218.08:05:39.54#ibcon#read 5, iclass 29, count 0 2006.218.08:05:39.54#ibcon#about to read 6, iclass 29, count 0 2006.218.08:05:39.54#ibcon#read 6, iclass 29, count 0 2006.218.08:05:39.54#ibcon#end of sib2, iclass 29, count 0 2006.218.08:05:39.54#ibcon#*after write, iclass 29, count 0 2006.218.08:05:39.54#ibcon#*before return 0, iclass 29, count 0 2006.218.08:05:39.54#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.218.08:05:39.54#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.218.08:05:39.54#ibcon#about to clear, iclass 29 cls_cnt 0 2006.218.08:05:39.54#ibcon#cleared, iclass 29 cls_cnt 0 2006.218.08:05:39.54$vc4f8/valo=6,772.99 2006.218.08:05:39.54#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.218.08:05:39.54#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.218.08:05:39.54#ibcon#ireg 17 cls_cnt 0 2006.218.08:05:39.54#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.218.08:05:39.54#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.218.08:05:39.54#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.218.08:05:39.54#ibcon#enter wrdev, iclass 31, count 0 2006.218.08:05:39.54#ibcon#first serial, iclass 31, count 0 2006.218.08:05:39.54#ibcon#enter sib2, iclass 31, count 0 2006.218.08:05:39.54#ibcon#flushed, iclass 31, count 0 2006.218.08:05:39.54#ibcon#about to write, iclass 31, count 0 2006.218.08:05:39.54#ibcon#wrote, iclass 31, count 0 2006.218.08:05:39.54#ibcon#about to read 3, iclass 31, count 0 2006.218.08:05:39.56#ibcon#read 3, iclass 31, count 0 2006.218.08:05:39.56#ibcon#about to read 4, iclass 31, count 0 2006.218.08:05:39.56#ibcon#read 4, iclass 31, count 0 2006.218.08:05:39.56#ibcon#about to read 5, iclass 31, count 0 2006.218.08:05:39.56#ibcon#read 5, iclass 31, count 0 2006.218.08:05:39.56#ibcon#about to read 6, iclass 31, count 0 2006.218.08:05:39.56#ibcon#read 6, iclass 31, count 0 2006.218.08:05:39.56#ibcon#end of sib2, iclass 31, count 0 2006.218.08:05:39.56#ibcon#*mode == 0, iclass 31, count 0 2006.218.08:05:39.56#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.218.08:05:39.56#ibcon#[26=FRQ=06,772.99\r\n] 2006.218.08:05:39.56#ibcon#*before write, iclass 31, count 0 2006.218.08:05:39.56#ibcon#enter sib2, iclass 31, count 0 2006.218.08:05:39.56#ibcon#flushed, iclass 31, count 0 2006.218.08:05:39.56#ibcon#about to write, iclass 31, count 0 2006.218.08:05:39.56#ibcon#wrote, iclass 31, count 0 2006.218.08:05:39.56#ibcon#about to read 3, iclass 31, count 0 2006.218.08:05:39.60#ibcon#read 3, iclass 31, count 0 2006.218.08:05:39.60#ibcon#about to read 4, iclass 31, count 0 2006.218.08:05:39.60#ibcon#read 4, iclass 31, count 0 2006.218.08:05:39.60#ibcon#about to read 5, iclass 31, count 0 2006.218.08:05:39.60#ibcon#read 5, iclass 31, count 0 2006.218.08:05:39.60#ibcon#about to read 6, iclass 31, count 0 2006.218.08:05:39.60#ibcon#read 6, iclass 31, count 0 2006.218.08:05:39.60#ibcon#end of sib2, iclass 31, count 0 2006.218.08:05:39.60#ibcon#*after write, iclass 31, count 0 2006.218.08:05:39.60#ibcon#*before return 0, iclass 31, count 0 2006.218.08:05:39.60#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.218.08:05:39.60#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.218.08:05:39.60#ibcon#about to clear, iclass 31 cls_cnt 0 2006.218.08:05:39.60#ibcon#cleared, iclass 31 cls_cnt 0 2006.218.08:05:39.60$vc4f8/va=6,6 2006.218.08:05:39.60#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.218.08:05:39.60#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.218.08:05:39.60#ibcon#ireg 11 cls_cnt 2 2006.218.08:05:39.60#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.218.08:05:39.67#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.218.08:05:39.67#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.218.08:05:39.67#ibcon#enter wrdev, iclass 33, count 2 2006.218.08:05:39.67#ibcon#first serial, iclass 33, count 2 2006.218.08:05:39.67#ibcon#enter sib2, iclass 33, count 2 2006.218.08:05:39.67#ibcon#flushed, iclass 33, count 2 2006.218.08:05:39.67#ibcon#about to write, iclass 33, count 2 2006.218.08:05:39.67#ibcon#wrote, iclass 33, count 2 2006.218.08:05:39.67#ibcon#about to read 3, iclass 33, count 2 2006.218.08:05:39.68#ibcon#read 3, iclass 33, count 2 2006.218.08:05:39.68#ibcon#about to read 4, iclass 33, count 2 2006.218.08:05:39.68#ibcon#read 4, iclass 33, count 2 2006.218.08:05:39.68#ibcon#about to read 5, iclass 33, count 2 2006.218.08:05:39.68#ibcon#read 5, iclass 33, count 2 2006.218.08:05:39.68#ibcon#about to read 6, iclass 33, count 2 2006.218.08:05:39.68#ibcon#read 6, iclass 33, count 2 2006.218.08:05:39.68#ibcon#end of sib2, iclass 33, count 2 2006.218.08:05:39.68#ibcon#*mode == 0, iclass 33, count 2 2006.218.08:05:39.68#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.218.08:05:39.68#ibcon#[25=AT06-06\r\n] 2006.218.08:05:39.68#ibcon#*before write, iclass 33, count 2 2006.218.08:05:39.68#ibcon#enter sib2, iclass 33, count 2 2006.218.08:05:39.68#ibcon#flushed, iclass 33, count 2 2006.218.08:05:39.68#ibcon#about to write, iclass 33, count 2 2006.218.08:05:39.68#ibcon#wrote, iclass 33, count 2 2006.218.08:05:39.68#ibcon#about to read 3, iclass 33, count 2 2006.218.08:05:39.71#ibcon#read 3, iclass 33, count 2 2006.218.08:05:39.71#ibcon#about to read 4, iclass 33, count 2 2006.218.08:05:39.71#ibcon#read 4, iclass 33, count 2 2006.218.08:05:39.71#ibcon#about to read 5, iclass 33, count 2 2006.218.08:05:39.71#ibcon#read 5, iclass 33, count 2 2006.218.08:05:39.71#ibcon#about to read 6, iclass 33, count 2 2006.218.08:05:39.71#ibcon#read 6, iclass 33, count 2 2006.218.08:05:39.71#ibcon#end of sib2, iclass 33, count 2 2006.218.08:05:39.71#ibcon#*after write, iclass 33, count 2 2006.218.08:05:39.71#ibcon#*before return 0, iclass 33, count 2 2006.218.08:05:39.71#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.218.08:05:39.71#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.218.08:05:39.71#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.218.08:05:39.71#ibcon#ireg 7 cls_cnt 0 2006.218.08:05:39.71#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.218.08:05:39.83#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.218.08:05:39.83#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.218.08:05:39.83#ibcon#enter wrdev, iclass 33, count 0 2006.218.08:05:39.83#ibcon#first serial, iclass 33, count 0 2006.218.08:05:39.83#ibcon#enter sib2, iclass 33, count 0 2006.218.08:05:39.83#ibcon#flushed, iclass 33, count 0 2006.218.08:05:39.83#ibcon#about to write, iclass 33, count 0 2006.218.08:05:39.83#ibcon#wrote, iclass 33, count 0 2006.218.08:05:39.83#ibcon#about to read 3, iclass 33, count 0 2006.218.08:05:39.85#ibcon#read 3, iclass 33, count 0 2006.218.08:05:39.85#ibcon#about to read 4, iclass 33, count 0 2006.218.08:05:39.85#ibcon#read 4, iclass 33, count 0 2006.218.08:05:39.85#ibcon#about to read 5, iclass 33, count 0 2006.218.08:05:39.85#ibcon#read 5, iclass 33, count 0 2006.218.08:05:39.85#ibcon#about to read 6, iclass 33, count 0 2006.218.08:05:39.85#ibcon#read 6, iclass 33, count 0 2006.218.08:05:39.85#ibcon#end of sib2, iclass 33, count 0 2006.218.08:05:39.85#ibcon#*mode == 0, iclass 33, count 0 2006.218.08:05:39.85#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.218.08:05:39.85#ibcon#[25=USB\r\n] 2006.218.08:05:39.85#ibcon#*before write, iclass 33, count 0 2006.218.08:05:39.85#ibcon#enter sib2, iclass 33, count 0 2006.218.08:05:39.85#ibcon#flushed, iclass 33, count 0 2006.218.08:05:39.85#ibcon#about to write, iclass 33, count 0 2006.218.08:05:39.85#ibcon#wrote, iclass 33, count 0 2006.218.08:05:39.85#ibcon#about to read 3, iclass 33, count 0 2006.218.08:05:39.88#abcon#<5=/06 4.2 7.4 30.97 721007.5\r\n> 2006.218.08:05:39.88#ibcon#read 3, iclass 33, count 0 2006.218.08:05:39.88#ibcon#about to read 4, iclass 33, count 0 2006.218.08:05:39.88#ibcon#read 4, iclass 33, count 0 2006.218.08:05:39.88#ibcon#about to read 5, iclass 33, count 0 2006.218.08:05:39.88#ibcon#read 5, iclass 33, count 0 2006.218.08:05:39.88#ibcon#about to read 6, iclass 33, count 0 2006.218.08:05:39.88#ibcon#read 6, iclass 33, count 0 2006.218.08:05:39.88#ibcon#end of sib2, iclass 33, count 0 2006.218.08:05:39.88#ibcon#*after write, iclass 33, count 0 2006.218.08:05:39.88#ibcon#*before return 0, iclass 33, count 0 2006.218.08:05:39.88#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.218.08:05:39.88#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.218.08:05:39.88#ibcon#about to clear, iclass 33 cls_cnt 0 2006.218.08:05:39.88#ibcon#cleared, iclass 33 cls_cnt 0 2006.218.08:05:39.88$vc4f8/valo=7,832.99 2006.218.08:05:39.88#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.218.08:05:39.88#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.218.08:05:39.88#ibcon#ireg 17 cls_cnt 0 2006.218.08:05:39.88#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.218.08:05:39.88#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.218.08:05:39.88#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.218.08:05:39.88#ibcon#enter wrdev, iclass 38, count 0 2006.218.08:05:39.88#ibcon#first serial, iclass 38, count 0 2006.218.08:05:39.88#ibcon#enter sib2, iclass 38, count 0 2006.218.08:05:39.88#ibcon#flushed, iclass 38, count 0 2006.218.08:05:39.88#ibcon#about to write, iclass 38, count 0 2006.218.08:05:39.88#ibcon#wrote, iclass 38, count 0 2006.218.08:05:39.88#ibcon#about to read 3, iclass 38, count 0 2006.218.08:05:39.90#abcon#{5=INTERFACE CLEAR} 2006.218.08:05:39.90#ibcon#read 3, iclass 38, count 0 2006.218.08:05:39.90#ibcon#about to read 4, iclass 38, count 0 2006.218.08:05:39.90#ibcon#read 4, iclass 38, count 0 2006.218.08:05:39.90#ibcon#about to read 5, iclass 38, count 0 2006.218.08:05:39.90#ibcon#read 5, iclass 38, count 0 2006.218.08:05:39.90#ibcon#about to read 6, iclass 38, count 0 2006.218.08:05:39.90#ibcon#read 6, iclass 38, count 0 2006.218.08:05:39.90#ibcon#end of sib2, iclass 38, count 0 2006.218.08:05:39.90#ibcon#*mode == 0, iclass 38, count 0 2006.218.08:05:39.90#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.218.08:05:39.90#ibcon#[26=FRQ=07,832.99\r\n] 2006.218.08:05:39.90#ibcon#*before write, iclass 38, count 0 2006.218.08:05:39.90#ibcon#enter sib2, iclass 38, count 0 2006.218.08:05:39.90#ibcon#flushed, iclass 38, count 0 2006.218.08:05:39.90#ibcon#about to write, iclass 38, count 0 2006.218.08:05:39.90#ibcon#wrote, iclass 38, count 0 2006.218.08:05:39.90#ibcon#about to read 3, iclass 38, count 0 2006.218.08:05:39.94#ibcon#read 3, iclass 38, count 0 2006.218.08:05:39.94#ibcon#about to read 4, iclass 38, count 0 2006.218.08:05:39.94#ibcon#read 4, iclass 38, count 0 2006.218.08:05:39.94#ibcon#about to read 5, iclass 38, count 0 2006.218.08:05:39.94#ibcon#read 5, iclass 38, count 0 2006.218.08:05:39.94#ibcon#about to read 6, iclass 38, count 0 2006.218.08:05:39.94#ibcon#read 6, iclass 38, count 0 2006.218.08:05:39.94#ibcon#end of sib2, iclass 38, count 0 2006.218.08:05:39.94#ibcon#*after write, iclass 38, count 0 2006.218.08:05:39.94#ibcon#*before return 0, iclass 38, count 0 2006.218.08:05:39.94#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.218.08:05:39.94#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.218.08:05:39.94#ibcon#about to clear, iclass 38 cls_cnt 0 2006.218.08:05:39.94#ibcon#cleared, iclass 38 cls_cnt 0 2006.218.08:05:39.94$vc4f8/va=7,6 2006.218.08:05:39.94#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.218.08:05:39.94#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.218.08:05:39.94#ibcon#ireg 11 cls_cnt 2 2006.218.08:05:39.94#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.218.08:05:39.96#abcon#[5=S1D000X0/0*\r\n] 2006.218.08:05:40.00#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.218.08:05:40.00#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.218.08:05:40.00#ibcon#enter wrdev, iclass 40, count 2 2006.218.08:05:40.00#ibcon#first serial, iclass 40, count 2 2006.218.08:05:40.00#ibcon#enter sib2, iclass 40, count 2 2006.218.08:05:40.00#ibcon#flushed, iclass 40, count 2 2006.218.08:05:40.00#ibcon#about to write, iclass 40, count 2 2006.218.08:05:40.00#ibcon#wrote, iclass 40, count 2 2006.218.08:05:40.00#ibcon#about to read 3, iclass 40, count 2 2006.218.08:05:40.02#ibcon#read 3, iclass 40, count 2 2006.218.08:05:40.02#ibcon#about to read 4, iclass 40, count 2 2006.218.08:05:40.02#ibcon#read 4, iclass 40, count 2 2006.218.08:05:40.02#ibcon#about to read 5, iclass 40, count 2 2006.218.08:05:40.02#ibcon#read 5, iclass 40, count 2 2006.218.08:05:40.02#ibcon#about to read 6, iclass 40, count 2 2006.218.08:05:40.02#ibcon#read 6, iclass 40, count 2 2006.218.08:05:40.02#ibcon#end of sib2, iclass 40, count 2 2006.218.08:05:40.02#ibcon#*mode == 0, iclass 40, count 2 2006.218.08:05:40.02#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.218.08:05:40.02#ibcon#[25=AT07-06\r\n] 2006.218.08:05:40.02#ibcon#*before write, iclass 40, count 2 2006.218.08:05:40.02#ibcon#enter sib2, iclass 40, count 2 2006.218.08:05:40.02#ibcon#flushed, iclass 40, count 2 2006.218.08:05:40.02#ibcon#about to write, iclass 40, count 2 2006.218.08:05:40.02#ibcon#wrote, iclass 40, count 2 2006.218.08:05:40.02#ibcon#about to read 3, iclass 40, count 2 2006.218.08:05:40.05#ibcon#read 3, iclass 40, count 2 2006.218.08:05:40.05#ibcon#about to read 4, iclass 40, count 2 2006.218.08:05:40.05#ibcon#read 4, iclass 40, count 2 2006.218.08:05:40.05#ibcon#about to read 5, iclass 40, count 2 2006.218.08:05:40.05#ibcon#read 5, iclass 40, count 2 2006.218.08:05:40.05#ibcon#about to read 6, iclass 40, count 2 2006.218.08:05:40.05#ibcon#read 6, iclass 40, count 2 2006.218.08:05:40.05#ibcon#end of sib2, iclass 40, count 2 2006.218.08:05:40.05#ibcon#*after write, iclass 40, count 2 2006.218.08:05:40.05#ibcon#*before return 0, iclass 40, count 2 2006.218.08:05:40.05#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.218.08:05:40.05#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.218.08:05:40.05#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.218.08:05:40.05#ibcon#ireg 7 cls_cnt 0 2006.218.08:05:40.05#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.218.08:05:40.17#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.218.08:05:40.17#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.218.08:05:40.17#ibcon#enter wrdev, iclass 40, count 0 2006.218.08:05:40.17#ibcon#first serial, iclass 40, count 0 2006.218.08:05:40.17#ibcon#enter sib2, iclass 40, count 0 2006.218.08:05:40.17#ibcon#flushed, iclass 40, count 0 2006.218.08:05:40.17#ibcon#about to write, iclass 40, count 0 2006.218.08:05:40.17#ibcon#wrote, iclass 40, count 0 2006.218.08:05:40.17#ibcon#about to read 3, iclass 40, count 0 2006.218.08:05:40.19#ibcon#read 3, iclass 40, count 0 2006.218.08:05:40.19#ibcon#about to read 4, iclass 40, count 0 2006.218.08:05:40.19#ibcon#read 4, iclass 40, count 0 2006.218.08:05:40.19#ibcon#about to read 5, iclass 40, count 0 2006.218.08:05:40.19#ibcon#read 5, iclass 40, count 0 2006.218.08:05:40.19#ibcon#about to read 6, iclass 40, count 0 2006.218.08:05:40.19#ibcon#read 6, iclass 40, count 0 2006.218.08:05:40.19#ibcon#end of sib2, iclass 40, count 0 2006.218.08:05:40.19#ibcon#*mode == 0, iclass 40, count 0 2006.218.08:05:40.19#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.218.08:05:40.19#ibcon#[25=USB\r\n] 2006.218.08:05:40.19#ibcon#*before write, iclass 40, count 0 2006.218.08:05:40.19#ibcon#enter sib2, iclass 40, count 0 2006.218.08:05:40.19#ibcon#flushed, iclass 40, count 0 2006.218.08:05:40.19#ibcon#about to write, iclass 40, count 0 2006.218.08:05:40.19#ibcon#wrote, iclass 40, count 0 2006.218.08:05:40.19#ibcon#about to read 3, iclass 40, count 0 2006.218.08:05:40.22#ibcon#read 3, iclass 40, count 0 2006.218.08:05:40.22#ibcon#about to read 4, iclass 40, count 0 2006.218.08:05:40.22#ibcon#read 4, iclass 40, count 0 2006.218.08:05:40.22#ibcon#about to read 5, iclass 40, count 0 2006.218.08:05:40.22#ibcon#read 5, iclass 40, count 0 2006.218.08:05:40.22#ibcon#about to read 6, iclass 40, count 0 2006.218.08:05:40.22#ibcon#read 6, iclass 40, count 0 2006.218.08:05:40.22#ibcon#end of sib2, iclass 40, count 0 2006.218.08:05:40.22#ibcon#*after write, iclass 40, count 0 2006.218.08:05:40.22#ibcon#*before return 0, iclass 40, count 0 2006.218.08:05:40.22#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.218.08:05:40.22#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.218.08:05:40.22#ibcon#about to clear, iclass 40 cls_cnt 0 2006.218.08:05:40.22#ibcon#cleared, iclass 40 cls_cnt 0 2006.218.08:05:40.22$vc4f8/valo=8,852.99 2006.218.08:05:40.22#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.218.08:05:40.22#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.218.08:05:40.22#ibcon#ireg 17 cls_cnt 0 2006.218.08:05:40.22#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.218.08:05:40.22#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.218.08:05:40.22#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.218.08:05:40.22#ibcon#enter wrdev, iclass 5, count 0 2006.218.08:05:40.22#ibcon#first serial, iclass 5, count 0 2006.218.08:05:40.22#ibcon#enter sib2, iclass 5, count 0 2006.218.08:05:40.22#ibcon#flushed, iclass 5, count 0 2006.218.08:05:40.22#ibcon#about to write, iclass 5, count 0 2006.218.08:05:40.22#ibcon#wrote, iclass 5, count 0 2006.218.08:05:40.22#ibcon#about to read 3, iclass 5, count 0 2006.218.08:05:40.24#ibcon#read 3, iclass 5, count 0 2006.218.08:05:40.24#ibcon#about to read 4, iclass 5, count 0 2006.218.08:05:40.24#ibcon#read 4, iclass 5, count 0 2006.218.08:05:40.24#ibcon#about to read 5, iclass 5, count 0 2006.218.08:05:40.24#ibcon#read 5, iclass 5, count 0 2006.218.08:05:40.24#ibcon#about to read 6, iclass 5, count 0 2006.218.08:05:40.24#ibcon#read 6, iclass 5, count 0 2006.218.08:05:40.24#ibcon#end of sib2, iclass 5, count 0 2006.218.08:05:40.24#ibcon#*mode == 0, iclass 5, count 0 2006.218.08:05:40.24#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.218.08:05:40.24#ibcon#[26=FRQ=08,852.99\r\n] 2006.218.08:05:40.24#ibcon#*before write, iclass 5, count 0 2006.218.08:05:40.24#ibcon#enter sib2, iclass 5, count 0 2006.218.08:05:40.24#ibcon#flushed, iclass 5, count 0 2006.218.08:05:40.24#ibcon#about to write, iclass 5, count 0 2006.218.08:05:40.24#ibcon#wrote, iclass 5, count 0 2006.218.08:05:40.24#ibcon#about to read 3, iclass 5, count 0 2006.218.08:05:40.28#ibcon#read 3, iclass 5, count 0 2006.218.08:05:40.28#ibcon#about to read 4, iclass 5, count 0 2006.218.08:05:40.28#ibcon#read 4, iclass 5, count 0 2006.218.08:05:40.28#ibcon#about to read 5, iclass 5, count 0 2006.218.08:05:40.28#ibcon#read 5, iclass 5, count 0 2006.218.08:05:40.28#ibcon#about to read 6, iclass 5, count 0 2006.218.08:05:40.28#ibcon#read 6, iclass 5, count 0 2006.218.08:05:40.28#ibcon#end of sib2, iclass 5, count 0 2006.218.08:05:40.28#ibcon#*after write, iclass 5, count 0 2006.218.08:05:40.28#ibcon#*before return 0, iclass 5, count 0 2006.218.08:05:40.28#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.218.08:05:40.28#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.218.08:05:40.28#ibcon#about to clear, iclass 5 cls_cnt 0 2006.218.08:05:40.28#ibcon#cleared, iclass 5 cls_cnt 0 2006.218.08:05:40.28$vc4f8/va=8,7 2006.218.08:05:40.28#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.218.08:05:40.28#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.218.08:05:40.28#ibcon#ireg 11 cls_cnt 2 2006.218.08:05:40.28#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.218.08:05:40.34#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.218.08:05:40.34#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.218.08:05:40.34#ibcon#enter wrdev, iclass 7, count 2 2006.218.08:05:40.34#ibcon#first serial, iclass 7, count 2 2006.218.08:05:40.34#ibcon#enter sib2, iclass 7, count 2 2006.218.08:05:40.34#ibcon#flushed, iclass 7, count 2 2006.218.08:05:40.34#ibcon#about to write, iclass 7, count 2 2006.218.08:05:40.34#ibcon#wrote, iclass 7, count 2 2006.218.08:05:40.34#ibcon#about to read 3, iclass 7, count 2 2006.218.08:05:40.36#ibcon#read 3, iclass 7, count 2 2006.218.08:05:40.36#ibcon#about to read 4, iclass 7, count 2 2006.218.08:05:40.36#ibcon#read 4, iclass 7, count 2 2006.218.08:05:40.36#ibcon#about to read 5, iclass 7, count 2 2006.218.08:05:40.36#ibcon#read 5, iclass 7, count 2 2006.218.08:05:40.36#ibcon#about to read 6, iclass 7, count 2 2006.218.08:05:40.36#ibcon#read 6, iclass 7, count 2 2006.218.08:05:40.36#ibcon#end of sib2, iclass 7, count 2 2006.218.08:05:40.36#ibcon#*mode == 0, iclass 7, count 2 2006.218.08:05:40.36#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.218.08:05:40.36#ibcon#[25=AT08-07\r\n] 2006.218.08:05:40.36#ibcon#*before write, iclass 7, count 2 2006.218.08:05:40.36#ibcon#enter sib2, iclass 7, count 2 2006.218.08:05:40.36#ibcon#flushed, iclass 7, count 2 2006.218.08:05:40.36#ibcon#about to write, iclass 7, count 2 2006.218.08:05:40.36#ibcon#wrote, iclass 7, count 2 2006.218.08:05:40.36#ibcon#about to read 3, iclass 7, count 2 2006.218.08:05:40.39#ibcon#read 3, iclass 7, count 2 2006.218.08:05:40.39#ibcon#about to read 4, iclass 7, count 2 2006.218.08:05:40.39#ibcon#read 4, iclass 7, count 2 2006.218.08:05:40.39#ibcon#about to read 5, iclass 7, count 2 2006.218.08:05:40.39#ibcon#read 5, iclass 7, count 2 2006.218.08:05:40.39#ibcon#about to read 6, iclass 7, count 2 2006.218.08:05:40.39#ibcon#read 6, iclass 7, count 2 2006.218.08:05:40.39#ibcon#end of sib2, iclass 7, count 2 2006.218.08:05:40.39#ibcon#*after write, iclass 7, count 2 2006.218.08:05:40.39#ibcon#*before return 0, iclass 7, count 2 2006.218.08:05:40.39#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.218.08:05:40.39#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.218.08:05:40.39#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.218.08:05:40.39#ibcon#ireg 7 cls_cnt 0 2006.218.08:05:40.39#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.218.08:05:40.51#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.218.08:05:40.51#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.218.08:05:40.51#ibcon#enter wrdev, iclass 7, count 0 2006.218.08:05:40.51#ibcon#first serial, iclass 7, count 0 2006.218.08:05:40.51#ibcon#enter sib2, iclass 7, count 0 2006.218.08:05:40.51#ibcon#flushed, iclass 7, count 0 2006.218.08:05:40.51#ibcon#about to write, iclass 7, count 0 2006.218.08:05:40.51#ibcon#wrote, iclass 7, count 0 2006.218.08:05:40.51#ibcon#about to read 3, iclass 7, count 0 2006.218.08:05:40.53#ibcon#read 3, iclass 7, count 0 2006.218.08:05:40.53#ibcon#about to read 4, iclass 7, count 0 2006.218.08:05:40.53#ibcon#read 4, iclass 7, count 0 2006.218.08:05:40.53#ibcon#about to read 5, iclass 7, count 0 2006.218.08:05:40.53#ibcon#read 5, iclass 7, count 0 2006.218.08:05:40.53#ibcon#about to read 6, iclass 7, count 0 2006.218.08:05:40.53#ibcon#read 6, iclass 7, count 0 2006.218.08:05:40.53#ibcon#end of sib2, iclass 7, count 0 2006.218.08:05:40.53#ibcon#*mode == 0, iclass 7, count 0 2006.218.08:05:40.53#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.218.08:05:40.53#ibcon#[25=USB\r\n] 2006.218.08:05:40.53#ibcon#*before write, iclass 7, count 0 2006.218.08:05:40.53#ibcon#enter sib2, iclass 7, count 0 2006.218.08:05:40.53#ibcon#flushed, iclass 7, count 0 2006.218.08:05:40.53#ibcon#about to write, iclass 7, count 0 2006.218.08:05:40.53#ibcon#wrote, iclass 7, count 0 2006.218.08:05:40.53#ibcon#about to read 3, iclass 7, count 0 2006.218.08:05:40.56#ibcon#read 3, iclass 7, count 0 2006.218.08:05:40.56#ibcon#about to read 4, iclass 7, count 0 2006.218.08:05:40.56#ibcon#read 4, iclass 7, count 0 2006.218.08:05:40.56#ibcon#about to read 5, iclass 7, count 0 2006.218.08:05:40.56#ibcon#read 5, iclass 7, count 0 2006.218.08:05:40.56#ibcon#about to read 6, iclass 7, count 0 2006.218.08:05:40.56#ibcon#read 6, iclass 7, count 0 2006.218.08:05:40.56#ibcon#end of sib2, iclass 7, count 0 2006.218.08:05:40.56#ibcon#*after write, iclass 7, count 0 2006.218.08:05:40.56#ibcon#*before return 0, iclass 7, count 0 2006.218.08:05:40.56#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.218.08:05:40.56#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.218.08:05:40.56#ibcon#about to clear, iclass 7 cls_cnt 0 2006.218.08:05:40.56#ibcon#cleared, iclass 7 cls_cnt 0 2006.218.08:05:40.56$vc4f8/vblo=1,632.99 2006.218.08:05:40.56#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.218.08:05:40.56#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.218.08:05:40.56#ibcon#ireg 17 cls_cnt 0 2006.218.08:05:40.56#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.218.08:05:40.56#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.218.08:05:40.56#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.218.08:05:40.56#ibcon#enter wrdev, iclass 11, count 0 2006.218.08:05:40.56#ibcon#first serial, iclass 11, count 0 2006.218.08:05:40.56#ibcon#enter sib2, iclass 11, count 0 2006.218.08:05:40.56#ibcon#flushed, iclass 11, count 0 2006.218.08:05:40.56#ibcon#about to write, iclass 11, count 0 2006.218.08:05:40.56#ibcon#wrote, iclass 11, count 0 2006.218.08:05:40.56#ibcon#about to read 3, iclass 11, count 0 2006.218.08:05:40.58#ibcon#read 3, iclass 11, count 0 2006.218.08:05:40.58#ibcon#about to read 4, iclass 11, count 0 2006.218.08:05:40.58#ibcon#read 4, iclass 11, count 0 2006.218.08:05:40.58#ibcon#about to read 5, iclass 11, count 0 2006.218.08:05:40.58#ibcon#read 5, iclass 11, count 0 2006.218.08:05:40.58#ibcon#about to read 6, iclass 11, count 0 2006.218.08:05:40.58#ibcon#read 6, iclass 11, count 0 2006.218.08:05:40.58#ibcon#end of sib2, iclass 11, count 0 2006.218.08:05:40.58#ibcon#*mode == 0, iclass 11, count 0 2006.218.08:05:40.58#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.218.08:05:40.58#ibcon#[28=FRQ=01,632.99\r\n] 2006.218.08:05:40.58#ibcon#*before write, iclass 11, count 0 2006.218.08:05:40.58#ibcon#enter sib2, iclass 11, count 0 2006.218.08:05:40.58#ibcon#flushed, iclass 11, count 0 2006.218.08:05:40.58#ibcon#about to write, iclass 11, count 0 2006.218.08:05:40.58#ibcon#wrote, iclass 11, count 0 2006.218.08:05:40.58#ibcon#about to read 3, iclass 11, count 0 2006.218.08:05:40.62#ibcon#read 3, iclass 11, count 0 2006.218.08:05:40.62#ibcon#about to read 4, iclass 11, count 0 2006.218.08:05:40.62#ibcon#read 4, iclass 11, count 0 2006.218.08:05:40.62#ibcon#about to read 5, iclass 11, count 0 2006.218.08:05:40.62#ibcon#read 5, iclass 11, count 0 2006.218.08:05:40.62#ibcon#about to read 6, iclass 11, count 0 2006.218.08:05:40.62#ibcon#read 6, iclass 11, count 0 2006.218.08:05:40.62#ibcon#end of sib2, iclass 11, count 0 2006.218.08:05:40.62#ibcon#*after write, iclass 11, count 0 2006.218.08:05:40.62#ibcon#*before return 0, iclass 11, count 0 2006.218.08:05:40.62#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.218.08:05:40.62#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.218.08:05:40.62#ibcon#about to clear, iclass 11 cls_cnt 0 2006.218.08:05:40.62#ibcon#cleared, iclass 11 cls_cnt 0 2006.218.08:05:40.62$vc4f8/vb=1,4 2006.218.08:05:40.62#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.218.08:05:40.62#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.218.08:05:40.62#ibcon#ireg 11 cls_cnt 2 2006.218.08:05:40.62#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.218.08:05:40.62#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.218.08:05:40.62#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.218.08:05:40.62#ibcon#enter wrdev, iclass 13, count 2 2006.218.08:05:40.62#ibcon#first serial, iclass 13, count 2 2006.218.08:05:40.62#ibcon#enter sib2, iclass 13, count 2 2006.218.08:05:40.62#ibcon#flushed, iclass 13, count 2 2006.218.08:05:40.62#ibcon#about to write, iclass 13, count 2 2006.218.08:05:40.62#ibcon#wrote, iclass 13, count 2 2006.218.08:05:40.62#ibcon#about to read 3, iclass 13, count 2 2006.218.08:05:40.64#ibcon#read 3, iclass 13, count 2 2006.218.08:05:40.64#ibcon#about to read 4, iclass 13, count 2 2006.218.08:05:40.64#ibcon#read 4, iclass 13, count 2 2006.218.08:05:40.64#ibcon#about to read 5, iclass 13, count 2 2006.218.08:05:40.64#ibcon#read 5, iclass 13, count 2 2006.218.08:05:40.64#ibcon#about to read 6, iclass 13, count 2 2006.218.08:05:40.64#ibcon#read 6, iclass 13, count 2 2006.218.08:05:40.64#ibcon#end of sib2, iclass 13, count 2 2006.218.08:05:40.64#ibcon#*mode == 0, iclass 13, count 2 2006.218.08:05:40.64#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.218.08:05:40.64#ibcon#[27=AT01-04\r\n] 2006.218.08:05:40.64#ibcon#*before write, iclass 13, count 2 2006.218.08:05:40.64#ibcon#enter sib2, iclass 13, count 2 2006.218.08:05:40.64#ibcon#flushed, iclass 13, count 2 2006.218.08:05:40.64#ibcon#about to write, iclass 13, count 2 2006.218.08:05:40.64#ibcon#wrote, iclass 13, count 2 2006.218.08:05:40.64#ibcon#about to read 3, iclass 13, count 2 2006.218.08:05:40.67#ibcon#read 3, iclass 13, count 2 2006.218.08:05:40.67#ibcon#about to read 4, iclass 13, count 2 2006.218.08:05:40.67#ibcon#read 4, iclass 13, count 2 2006.218.08:05:40.67#ibcon#about to read 5, iclass 13, count 2 2006.218.08:05:40.67#ibcon#read 5, iclass 13, count 2 2006.218.08:05:40.67#ibcon#about to read 6, iclass 13, count 2 2006.218.08:05:40.67#ibcon#read 6, iclass 13, count 2 2006.218.08:05:40.67#ibcon#end of sib2, iclass 13, count 2 2006.218.08:05:40.67#ibcon#*after write, iclass 13, count 2 2006.218.08:05:40.67#ibcon#*before return 0, iclass 13, count 2 2006.218.08:05:40.67#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.218.08:05:40.67#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.218.08:05:40.67#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.218.08:05:40.67#ibcon#ireg 7 cls_cnt 0 2006.218.08:05:40.67#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.218.08:05:40.79#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.218.08:05:40.79#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.218.08:05:40.79#ibcon#enter wrdev, iclass 13, count 0 2006.218.08:05:40.79#ibcon#first serial, iclass 13, count 0 2006.218.08:05:40.79#ibcon#enter sib2, iclass 13, count 0 2006.218.08:05:40.79#ibcon#flushed, iclass 13, count 0 2006.218.08:05:40.79#ibcon#about to write, iclass 13, count 0 2006.218.08:05:40.79#ibcon#wrote, iclass 13, count 0 2006.218.08:05:40.79#ibcon#about to read 3, iclass 13, count 0 2006.218.08:05:40.81#ibcon#read 3, iclass 13, count 0 2006.218.08:05:40.81#ibcon#about to read 4, iclass 13, count 0 2006.218.08:05:40.81#ibcon#read 4, iclass 13, count 0 2006.218.08:05:40.81#ibcon#about to read 5, iclass 13, count 0 2006.218.08:05:40.81#ibcon#read 5, iclass 13, count 0 2006.218.08:05:40.81#ibcon#about to read 6, iclass 13, count 0 2006.218.08:05:40.81#ibcon#read 6, iclass 13, count 0 2006.218.08:05:40.81#ibcon#end of sib2, iclass 13, count 0 2006.218.08:05:40.81#ibcon#*mode == 0, iclass 13, count 0 2006.218.08:05:40.81#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.218.08:05:40.81#ibcon#[27=USB\r\n] 2006.218.08:05:40.81#ibcon#*before write, iclass 13, count 0 2006.218.08:05:40.81#ibcon#enter sib2, iclass 13, count 0 2006.218.08:05:40.81#ibcon#flushed, iclass 13, count 0 2006.218.08:05:40.81#ibcon#about to write, iclass 13, count 0 2006.218.08:05:40.81#ibcon#wrote, iclass 13, count 0 2006.218.08:05:40.81#ibcon#about to read 3, iclass 13, count 0 2006.218.08:05:40.84#ibcon#read 3, iclass 13, count 0 2006.218.08:05:40.84#ibcon#about to read 4, iclass 13, count 0 2006.218.08:05:40.84#ibcon#read 4, iclass 13, count 0 2006.218.08:05:40.84#ibcon#about to read 5, iclass 13, count 0 2006.218.08:05:40.84#ibcon#read 5, iclass 13, count 0 2006.218.08:05:40.84#ibcon#about to read 6, iclass 13, count 0 2006.218.08:05:40.84#ibcon#read 6, iclass 13, count 0 2006.218.08:05:40.84#ibcon#end of sib2, iclass 13, count 0 2006.218.08:05:40.84#ibcon#*after write, iclass 13, count 0 2006.218.08:05:40.84#ibcon#*before return 0, iclass 13, count 0 2006.218.08:05:40.84#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.218.08:05:40.84#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.218.08:05:40.84#ibcon#about to clear, iclass 13 cls_cnt 0 2006.218.08:05:40.84#ibcon#cleared, iclass 13 cls_cnt 0 2006.218.08:05:40.84$vc4f8/vblo=2,640.99 2006.218.08:05:40.84#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.218.08:05:40.84#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.218.08:05:40.84#ibcon#ireg 17 cls_cnt 0 2006.218.08:05:40.84#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.218.08:05:40.84#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.218.08:05:40.84#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.218.08:05:40.84#ibcon#enter wrdev, iclass 15, count 0 2006.218.08:05:40.84#ibcon#first serial, iclass 15, count 0 2006.218.08:05:40.84#ibcon#enter sib2, iclass 15, count 0 2006.218.08:05:40.84#ibcon#flushed, iclass 15, count 0 2006.218.08:05:40.84#ibcon#about to write, iclass 15, count 0 2006.218.08:05:40.84#ibcon#wrote, iclass 15, count 0 2006.218.08:05:40.84#ibcon#about to read 3, iclass 15, count 0 2006.218.08:05:40.86#ibcon#read 3, iclass 15, count 0 2006.218.08:05:40.86#ibcon#about to read 4, iclass 15, count 0 2006.218.08:05:40.86#ibcon#read 4, iclass 15, count 0 2006.218.08:05:40.86#ibcon#about to read 5, iclass 15, count 0 2006.218.08:05:40.86#ibcon#read 5, iclass 15, count 0 2006.218.08:05:40.86#ibcon#about to read 6, iclass 15, count 0 2006.218.08:05:40.86#ibcon#read 6, iclass 15, count 0 2006.218.08:05:40.86#ibcon#end of sib2, iclass 15, count 0 2006.218.08:05:40.86#ibcon#*mode == 0, iclass 15, count 0 2006.218.08:05:40.86#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.218.08:05:40.86#ibcon#[28=FRQ=02,640.99\r\n] 2006.218.08:05:40.86#ibcon#*before write, iclass 15, count 0 2006.218.08:05:40.86#ibcon#enter sib2, iclass 15, count 0 2006.218.08:05:40.86#ibcon#flushed, iclass 15, count 0 2006.218.08:05:40.86#ibcon#about to write, iclass 15, count 0 2006.218.08:05:40.86#ibcon#wrote, iclass 15, count 0 2006.218.08:05:40.86#ibcon#about to read 3, iclass 15, count 0 2006.218.08:05:40.90#ibcon#read 3, iclass 15, count 0 2006.218.08:05:40.90#ibcon#about to read 4, iclass 15, count 0 2006.218.08:05:40.90#ibcon#read 4, iclass 15, count 0 2006.218.08:05:40.90#ibcon#about to read 5, iclass 15, count 0 2006.218.08:05:40.90#ibcon#read 5, iclass 15, count 0 2006.218.08:05:40.90#ibcon#about to read 6, iclass 15, count 0 2006.218.08:05:40.90#ibcon#read 6, iclass 15, count 0 2006.218.08:05:40.90#ibcon#end of sib2, iclass 15, count 0 2006.218.08:05:40.90#ibcon#*after write, iclass 15, count 0 2006.218.08:05:40.90#ibcon#*before return 0, iclass 15, count 0 2006.218.08:05:40.90#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.218.08:05:40.90#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.218.08:05:40.90#ibcon#about to clear, iclass 15 cls_cnt 0 2006.218.08:05:40.90#ibcon#cleared, iclass 15 cls_cnt 0 2006.218.08:05:40.90$vc4f8/vb=2,4 2006.218.08:05:40.90#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.218.08:05:40.90#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.218.08:05:40.90#ibcon#ireg 11 cls_cnt 2 2006.218.08:05:40.90#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.218.08:05:40.96#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.218.08:05:40.96#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.218.08:05:40.96#ibcon#enter wrdev, iclass 17, count 2 2006.218.08:05:40.96#ibcon#first serial, iclass 17, count 2 2006.218.08:05:40.96#ibcon#enter sib2, iclass 17, count 2 2006.218.08:05:40.96#ibcon#flushed, iclass 17, count 2 2006.218.08:05:40.96#ibcon#about to write, iclass 17, count 2 2006.218.08:05:40.96#ibcon#wrote, iclass 17, count 2 2006.218.08:05:40.96#ibcon#about to read 3, iclass 17, count 2 2006.218.08:05:40.98#ibcon#read 3, iclass 17, count 2 2006.218.08:05:40.98#ibcon#about to read 4, iclass 17, count 2 2006.218.08:05:40.98#ibcon#read 4, iclass 17, count 2 2006.218.08:05:40.98#ibcon#about to read 5, iclass 17, count 2 2006.218.08:05:40.98#ibcon#read 5, iclass 17, count 2 2006.218.08:05:40.98#ibcon#about to read 6, iclass 17, count 2 2006.218.08:05:40.98#ibcon#read 6, iclass 17, count 2 2006.218.08:05:40.98#ibcon#end of sib2, iclass 17, count 2 2006.218.08:05:40.98#ibcon#*mode == 0, iclass 17, count 2 2006.218.08:05:40.98#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.218.08:05:40.98#ibcon#[27=AT02-04\r\n] 2006.218.08:05:40.98#ibcon#*before write, iclass 17, count 2 2006.218.08:05:40.98#ibcon#enter sib2, iclass 17, count 2 2006.218.08:05:40.98#ibcon#flushed, iclass 17, count 2 2006.218.08:05:40.98#ibcon#about to write, iclass 17, count 2 2006.218.08:05:40.98#ibcon#wrote, iclass 17, count 2 2006.218.08:05:40.98#ibcon#about to read 3, iclass 17, count 2 2006.218.08:05:41.01#ibcon#read 3, iclass 17, count 2 2006.218.08:05:41.01#ibcon#about to read 4, iclass 17, count 2 2006.218.08:05:41.01#ibcon#read 4, iclass 17, count 2 2006.218.08:05:41.01#ibcon#about to read 5, iclass 17, count 2 2006.218.08:05:41.01#ibcon#read 5, iclass 17, count 2 2006.218.08:05:41.01#ibcon#about to read 6, iclass 17, count 2 2006.218.08:05:41.01#ibcon#read 6, iclass 17, count 2 2006.218.08:05:41.01#ibcon#end of sib2, iclass 17, count 2 2006.218.08:05:41.01#ibcon#*after write, iclass 17, count 2 2006.218.08:05:41.01#ibcon#*before return 0, iclass 17, count 2 2006.218.08:05:41.01#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.218.08:05:41.01#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.218.08:05:41.01#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.218.08:05:41.01#ibcon#ireg 7 cls_cnt 0 2006.218.08:05:41.01#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.218.08:05:41.13#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.218.08:05:41.13#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.218.08:05:41.13#ibcon#enter wrdev, iclass 17, count 0 2006.218.08:05:41.13#ibcon#first serial, iclass 17, count 0 2006.218.08:05:41.13#ibcon#enter sib2, iclass 17, count 0 2006.218.08:05:41.13#ibcon#flushed, iclass 17, count 0 2006.218.08:05:41.13#ibcon#about to write, iclass 17, count 0 2006.218.08:05:41.13#ibcon#wrote, iclass 17, count 0 2006.218.08:05:41.13#ibcon#about to read 3, iclass 17, count 0 2006.218.08:05:41.15#ibcon#read 3, iclass 17, count 0 2006.218.08:05:41.15#ibcon#about to read 4, iclass 17, count 0 2006.218.08:05:41.15#ibcon#read 4, iclass 17, count 0 2006.218.08:05:41.15#ibcon#about to read 5, iclass 17, count 0 2006.218.08:05:41.15#ibcon#read 5, iclass 17, count 0 2006.218.08:05:41.15#ibcon#about to read 6, iclass 17, count 0 2006.218.08:05:41.15#ibcon#read 6, iclass 17, count 0 2006.218.08:05:41.15#ibcon#end of sib2, iclass 17, count 0 2006.218.08:05:41.15#ibcon#*mode == 0, iclass 17, count 0 2006.218.08:05:41.15#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.218.08:05:41.15#ibcon#[27=USB\r\n] 2006.218.08:05:41.15#ibcon#*before write, iclass 17, count 0 2006.218.08:05:41.15#ibcon#enter sib2, iclass 17, count 0 2006.218.08:05:41.15#ibcon#flushed, iclass 17, count 0 2006.218.08:05:41.15#ibcon#about to write, iclass 17, count 0 2006.218.08:05:41.15#ibcon#wrote, iclass 17, count 0 2006.218.08:05:41.15#ibcon#about to read 3, iclass 17, count 0 2006.218.08:05:41.18#ibcon#read 3, iclass 17, count 0 2006.218.08:05:41.18#ibcon#about to read 4, iclass 17, count 0 2006.218.08:05:41.18#ibcon#read 4, iclass 17, count 0 2006.218.08:05:41.18#ibcon#about to read 5, iclass 17, count 0 2006.218.08:05:41.18#ibcon#read 5, iclass 17, count 0 2006.218.08:05:41.18#ibcon#about to read 6, iclass 17, count 0 2006.218.08:05:41.18#ibcon#read 6, iclass 17, count 0 2006.218.08:05:41.18#ibcon#end of sib2, iclass 17, count 0 2006.218.08:05:41.18#ibcon#*after write, iclass 17, count 0 2006.218.08:05:41.18#ibcon#*before return 0, iclass 17, count 0 2006.218.08:05:41.18#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.218.08:05:41.18#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.218.08:05:41.18#ibcon#about to clear, iclass 17 cls_cnt 0 2006.218.08:05:41.18#ibcon#cleared, iclass 17 cls_cnt 0 2006.218.08:05:41.18$vc4f8/vblo=3,656.99 2006.218.08:05:41.18#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.218.08:05:41.18#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.218.08:05:41.18#ibcon#ireg 17 cls_cnt 0 2006.218.08:05:41.18#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.218.08:05:41.18#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.218.08:05:41.18#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.218.08:05:41.18#ibcon#enter wrdev, iclass 19, count 0 2006.218.08:05:41.18#ibcon#first serial, iclass 19, count 0 2006.218.08:05:41.18#ibcon#enter sib2, iclass 19, count 0 2006.218.08:05:41.18#ibcon#flushed, iclass 19, count 0 2006.218.08:05:41.18#ibcon#about to write, iclass 19, count 0 2006.218.08:05:41.18#ibcon#wrote, iclass 19, count 0 2006.218.08:05:41.18#ibcon#about to read 3, iclass 19, count 0 2006.218.08:05:41.20#ibcon#read 3, iclass 19, count 0 2006.218.08:05:41.20#ibcon#about to read 4, iclass 19, count 0 2006.218.08:05:41.20#ibcon#read 4, iclass 19, count 0 2006.218.08:05:41.20#ibcon#about to read 5, iclass 19, count 0 2006.218.08:05:41.20#ibcon#read 5, iclass 19, count 0 2006.218.08:05:41.20#ibcon#about to read 6, iclass 19, count 0 2006.218.08:05:41.20#ibcon#read 6, iclass 19, count 0 2006.218.08:05:41.20#ibcon#end of sib2, iclass 19, count 0 2006.218.08:05:41.20#ibcon#*mode == 0, iclass 19, count 0 2006.218.08:05:41.20#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.218.08:05:41.20#ibcon#[28=FRQ=03,656.99\r\n] 2006.218.08:05:41.20#ibcon#*before write, iclass 19, count 0 2006.218.08:05:41.20#ibcon#enter sib2, iclass 19, count 0 2006.218.08:05:41.20#ibcon#flushed, iclass 19, count 0 2006.218.08:05:41.20#ibcon#about to write, iclass 19, count 0 2006.218.08:05:41.20#ibcon#wrote, iclass 19, count 0 2006.218.08:05:41.20#ibcon#about to read 3, iclass 19, count 0 2006.218.08:05:41.24#ibcon#read 3, iclass 19, count 0 2006.218.08:05:41.24#ibcon#about to read 4, iclass 19, count 0 2006.218.08:05:41.24#ibcon#read 4, iclass 19, count 0 2006.218.08:05:41.24#ibcon#about to read 5, iclass 19, count 0 2006.218.08:05:41.24#ibcon#read 5, iclass 19, count 0 2006.218.08:05:41.24#ibcon#about to read 6, iclass 19, count 0 2006.218.08:05:41.24#ibcon#read 6, iclass 19, count 0 2006.218.08:05:41.24#ibcon#end of sib2, iclass 19, count 0 2006.218.08:05:41.24#ibcon#*after write, iclass 19, count 0 2006.218.08:05:41.24#ibcon#*before return 0, iclass 19, count 0 2006.218.08:05:41.24#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.218.08:05:41.24#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.218.08:05:41.24#ibcon#about to clear, iclass 19 cls_cnt 0 2006.218.08:05:41.24#ibcon#cleared, iclass 19 cls_cnt 0 2006.218.08:05:41.24$vc4f8/vb=3,4 2006.218.08:05:41.24#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.218.08:05:41.24#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.218.08:05:41.24#ibcon#ireg 11 cls_cnt 2 2006.218.08:05:41.24#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.218.08:05:41.31#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.218.08:05:41.31#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.218.08:05:41.31#ibcon#enter wrdev, iclass 21, count 2 2006.218.08:05:41.31#ibcon#first serial, iclass 21, count 2 2006.218.08:05:41.31#ibcon#enter sib2, iclass 21, count 2 2006.218.08:05:41.31#ibcon#flushed, iclass 21, count 2 2006.218.08:05:41.31#ibcon#about to write, iclass 21, count 2 2006.218.08:05:41.31#ibcon#wrote, iclass 21, count 2 2006.218.08:05:41.31#ibcon#about to read 3, iclass 21, count 2 2006.218.08:05:41.32#ibcon#read 3, iclass 21, count 2 2006.218.08:05:41.32#ibcon#about to read 4, iclass 21, count 2 2006.218.08:05:41.32#ibcon#read 4, iclass 21, count 2 2006.218.08:05:41.32#ibcon#about to read 5, iclass 21, count 2 2006.218.08:05:41.32#ibcon#read 5, iclass 21, count 2 2006.218.08:05:41.32#ibcon#about to read 6, iclass 21, count 2 2006.218.08:05:41.32#ibcon#read 6, iclass 21, count 2 2006.218.08:05:41.32#ibcon#end of sib2, iclass 21, count 2 2006.218.08:05:41.32#ibcon#*mode == 0, iclass 21, count 2 2006.218.08:05:41.32#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.218.08:05:41.32#ibcon#[27=AT03-04\r\n] 2006.218.08:05:41.32#ibcon#*before write, iclass 21, count 2 2006.218.08:05:41.32#ibcon#enter sib2, iclass 21, count 2 2006.218.08:05:41.32#ibcon#flushed, iclass 21, count 2 2006.218.08:05:41.32#ibcon#about to write, iclass 21, count 2 2006.218.08:05:41.32#ibcon#wrote, iclass 21, count 2 2006.218.08:05:41.32#ibcon#about to read 3, iclass 21, count 2 2006.218.08:05:41.35#ibcon#read 3, iclass 21, count 2 2006.218.08:05:41.35#ibcon#about to read 4, iclass 21, count 2 2006.218.08:05:41.35#ibcon#read 4, iclass 21, count 2 2006.218.08:05:41.35#ibcon#about to read 5, iclass 21, count 2 2006.218.08:05:41.35#ibcon#read 5, iclass 21, count 2 2006.218.08:05:41.35#ibcon#about to read 6, iclass 21, count 2 2006.218.08:05:41.35#ibcon#read 6, iclass 21, count 2 2006.218.08:05:41.35#ibcon#end of sib2, iclass 21, count 2 2006.218.08:05:41.35#ibcon#*after write, iclass 21, count 2 2006.218.08:05:41.35#ibcon#*before return 0, iclass 21, count 2 2006.218.08:05:41.35#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.218.08:05:41.35#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.218.08:05:41.35#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.218.08:05:41.35#ibcon#ireg 7 cls_cnt 0 2006.218.08:05:41.35#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.218.08:05:41.47#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.218.08:05:41.47#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.218.08:05:41.47#ibcon#enter wrdev, iclass 21, count 0 2006.218.08:05:41.47#ibcon#first serial, iclass 21, count 0 2006.218.08:05:41.47#ibcon#enter sib2, iclass 21, count 0 2006.218.08:05:41.47#ibcon#flushed, iclass 21, count 0 2006.218.08:05:41.47#ibcon#about to write, iclass 21, count 0 2006.218.08:05:41.47#ibcon#wrote, iclass 21, count 0 2006.218.08:05:41.47#ibcon#about to read 3, iclass 21, count 0 2006.218.08:05:41.49#ibcon#read 3, iclass 21, count 0 2006.218.08:05:41.49#ibcon#about to read 4, iclass 21, count 0 2006.218.08:05:41.49#ibcon#read 4, iclass 21, count 0 2006.218.08:05:41.49#ibcon#about to read 5, iclass 21, count 0 2006.218.08:05:41.49#ibcon#read 5, iclass 21, count 0 2006.218.08:05:41.49#ibcon#about to read 6, iclass 21, count 0 2006.218.08:05:41.49#ibcon#read 6, iclass 21, count 0 2006.218.08:05:41.49#ibcon#end of sib2, iclass 21, count 0 2006.218.08:05:41.49#ibcon#*mode == 0, iclass 21, count 0 2006.218.08:05:41.49#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.218.08:05:41.49#ibcon#[27=USB\r\n] 2006.218.08:05:41.49#ibcon#*before write, iclass 21, count 0 2006.218.08:05:41.49#ibcon#enter sib2, iclass 21, count 0 2006.218.08:05:41.49#ibcon#flushed, iclass 21, count 0 2006.218.08:05:41.49#ibcon#about to write, iclass 21, count 0 2006.218.08:05:41.49#ibcon#wrote, iclass 21, count 0 2006.218.08:05:41.49#ibcon#about to read 3, iclass 21, count 0 2006.218.08:05:41.52#ibcon#read 3, iclass 21, count 0 2006.218.08:05:41.52#ibcon#about to read 4, iclass 21, count 0 2006.218.08:05:41.52#ibcon#read 4, iclass 21, count 0 2006.218.08:05:41.52#ibcon#about to read 5, iclass 21, count 0 2006.218.08:05:41.52#ibcon#read 5, iclass 21, count 0 2006.218.08:05:41.52#ibcon#about to read 6, iclass 21, count 0 2006.218.08:05:41.52#ibcon#read 6, iclass 21, count 0 2006.218.08:05:41.52#ibcon#end of sib2, iclass 21, count 0 2006.218.08:05:41.52#ibcon#*after write, iclass 21, count 0 2006.218.08:05:41.52#ibcon#*before return 0, iclass 21, count 0 2006.218.08:05:41.52#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.218.08:05:41.52#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.218.08:05:41.52#ibcon#about to clear, iclass 21 cls_cnt 0 2006.218.08:05:41.52#ibcon#cleared, iclass 21 cls_cnt 0 2006.218.08:05:41.52$vc4f8/vblo=4,712.99 2006.218.08:05:41.52#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.218.08:05:41.52#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.218.08:05:41.52#ibcon#ireg 17 cls_cnt 0 2006.218.08:05:41.52#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.218.08:05:41.52#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.218.08:05:41.52#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.218.08:05:41.52#ibcon#enter wrdev, iclass 23, count 0 2006.218.08:05:41.52#ibcon#first serial, iclass 23, count 0 2006.218.08:05:41.52#ibcon#enter sib2, iclass 23, count 0 2006.218.08:05:41.52#ibcon#flushed, iclass 23, count 0 2006.218.08:05:41.52#ibcon#about to write, iclass 23, count 0 2006.218.08:05:41.52#ibcon#wrote, iclass 23, count 0 2006.218.08:05:41.52#ibcon#about to read 3, iclass 23, count 0 2006.218.08:05:41.54#ibcon#read 3, iclass 23, count 0 2006.218.08:05:41.54#ibcon#about to read 4, iclass 23, count 0 2006.218.08:05:41.54#ibcon#read 4, iclass 23, count 0 2006.218.08:05:41.54#ibcon#about to read 5, iclass 23, count 0 2006.218.08:05:41.54#ibcon#read 5, iclass 23, count 0 2006.218.08:05:41.54#ibcon#about to read 6, iclass 23, count 0 2006.218.08:05:41.54#ibcon#read 6, iclass 23, count 0 2006.218.08:05:41.54#ibcon#end of sib2, iclass 23, count 0 2006.218.08:05:41.54#ibcon#*mode == 0, iclass 23, count 0 2006.218.08:05:41.54#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.218.08:05:41.54#ibcon#[28=FRQ=04,712.99\r\n] 2006.218.08:05:41.54#ibcon#*before write, iclass 23, count 0 2006.218.08:05:41.54#ibcon#enter sib2, iclass 23, count 0 2006.218.08:05:41.54#ibcon#flushed, iclass 23, count 0 2006.218.08:05:41.54#ibcon#about to write, iclass 23, count 0 2006.218.08:05:41.54#ibcon#wrote, iclass 23, count 0 2006.218.08:05:41.54#ibcon#about to read 3, iclass 23, count 0 2006.218.08:05:41.58#ibcon#read 3, iclass 23, count 0 2006.218.08:05:41.58#ibcon#about to read 4, iclass 23, count 0 2006.218.08:05:41.58#ibcon#read 4, iclass 23, count 0 2006.218.08:05:41.58#ibcon#about to read 5, iclass 23, count 0 2006.218.08:05:41.58#ibcon#read 5, iclass 23, count 0 2006.218.08:05:41.58#ibcon#about to read 6, iclass 23, count 0 2006.218.08:05:41.58#ibcon#read 6, iclass 23, count 0 2006.218.08:05:41.58#ibcon#end of sib2, iclass 23, count 0 2006.218.08:05:41.58#ibcon#*after write, iclass 23, count 0 2006.218.08:05:41.58#ibcon#*before return 0, iclass 23, count 0 2006.218.08:05:41.58#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.218.08:05:41.58#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.218.08:05:41.58#ibcon#about to clear, iclass 23 cls_cnt 0 2006.218.08:05:41.58#ibcon#cleared, iclass 23 cls_cnt 0 2006.218.08:05:41.58$vc4f8/vb=4,4 2006.218.08:05:41.58#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.218.08:05:41.58#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.218.08:05:41.58#ibcon#ireg 11 cls_cnt 2 2006.218.08:05:41.58#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.218.08:05:41.64#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.218.08:05:41.64#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.218.08:05:41.64#ibcon#enter wrdev, iclass 25, count 2 2006.218.08:05:41.64#ibcon#first serial, iclass 25, count 2 2006.218.08:05:41.64#ibcon#enter sib2, iclass 25, count 2 2006.218.08:05:41.64#ibcon#flushed, iclass 25, count 2 2006.218.08:05:41.64#ibcon#about to write, iclass 25, count 2 2006.218.08:05:41.64#ibcon#wrote, iclass 25, count 2 2006.218.08:05:41.64#ibcon#about to read 3, iclass 25, count 2 2006.218.08:05:41.66#ibcon#read 3, iclass 25, count 2 2006.218.08:05:41.66#ibcon#about to read 4, iclass 25, count 2 2006.218.08:05:41.66#ibcon#read 4, iclass 25, count 2 2006.218.08:05:41.66#ibcon#about to read 5, iclass 25, count 2 2006.218.08:05:41.66#ibcon#read 5, iclass 25, count 2 2006.218.08:05:41.66#ibcon#about to read 6, iclass 25, count 2 2006.218.08:05:41.66#ibcon#read 6, iclass 25, count 2 2006.218.08:05:41.66#ibcon#end of sib2, iclass 25, count 2 2006.218.08:05:41.66#ibcon#*mode == 0, iclass 25, count 2 2006.218.08:05:41.66#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.218.08:05:41.66#ibcon#[27=AT04-04\r\n] 2006.218.08:05:41.66#ibcon#*before write, iclass 25, count 2 2006.218.08:05:41.66#ibcon#enter sib2, iclass 25, count 2 2006.218.08:05:41.66#ibcon#flushed, iclass 25, count 2 2006.218.08:05:41.66#ibcon#about to write, iclass 25, count 2 2006.218.08:05:41.66#ibcon#wrote, iclass 25, count 2 2006.218.08:05:41.66#ibcon#about to read 3, iclass 25, count 2 2006.218.08:05:41.69#ibcon#read 3, iclass 25, count 2 2006.218.08:05:41.69#ibcon#about to read 4, iclass 25, count 2 2006.218.08:05:41.69#ibcon#read 4, iclass 25, count 2 2006.218.08:05:41.69#ibcon#about to read 5, iclass 25, count 2 2006.218.08:05:41.69#ibcon#read 5, iclass 25, count 2 2006.218.08:05:41.69#ibcon#about to read 6, iclass 25, count 2 2006.218.08:05:41.69#ibcon#read 6, iclass 25, count 2 2006.218.08:05:41.69#ibcon#end of sib2, iclass 25, count 2 2006.218.08:05:41.69#ibcon#*after write, iclass 25, count 2 2006.218.08:05:41.69#ibcon#*before return 0, iclass 25, count 2 2006.218.08:05:41.69#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.218.08:05:41.69#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.218.08:05:41.69#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.218.08:05:41.69#ibcon#ireg 7 cls_cnt 0 2006.218.08:05:41.69#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.218.08:05:41.81#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.218.08:05:41.81#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.218.08:05:41.81#ibcon#enter wrdev, iclass 25, count 0 2006.218.08:05:41.81#ibcon#first serial, iclass 25, count 0 2006.218.08:05:41.81#ibcon#enter sib2, iclass 25, count 0 2006.218.08:05:41.81#ibcon#flushed, iclass 25, count 0 2006.218.08:05:41.81#ibcon#about to write, iclass 25, count 0 2006.218.08:05:41.81#ibcon#wrote, iclass 25, count 0 2006.218.08:05:41.81#ibcon#about to read 3, iclass 25, count 0 2006.218.08:05:41.83#ibcon#read 3, iclass 25, count 0 2006.218.08:05:41.83#ibcon#about to read 4, iclass 25, count 0 2006.218.08:05:41.83#ibcon#read 4, iclass 25, count 0 2006.218.08:05:41.83#ibcon#about to read 5, iclass 25, count 0 2006.218.08:05:41.83#ibcon#read 5, iclass 25, count 0 2006.218.08:05:41.83#ibcon#about to read 6, iclass 25, count 0 2006.218.08:05:41.83#ibcon#read 6, iclass 25, count 0 2006.218.08:05:41.83#ibcon#end of sib2, iclass 25, count 0 2006.218.08:05:41.83#ibcon#*mode == 0, iclass 25, count 0 2006.218.08:05:41.83#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.218.08:05:41.83#ibcon#[27=USB\r\n] 2006.218.08:05:41.83#ibcon#*before write, iclass 25, count 0 2006.218.08:05:41.83#ibcon#enter sib2, iclass 25, count 0 2006.218.08:05:41.83#ibcon#flushed, iclass 25, count 0 2006.218.08:05:41.83#ibcon#about to write, iclass 25, count 0 2006.218.08:05:41.83#ibcon#wrote, iclass 25, count 0 2006.218.08:05:41.83#ibcon#about to read 3, iclass 25, count 0 2006.218.08:05:41.86#ibcon#read 3, iclass 25, count 0 2006.218.08:05:41.86#ibcon#about to read 4, iclass 25, count 0 2006.218.08:05:41.86#ibcon#read 4, iclass 25, count 0 2006.218.08:05:41.86#ibcon#about to read 5, iclass 25, count 0 2006.218.08:05:41.86#ibcon#read 5, iclass 25, count 0 2006.218.08:05:41.86#ibcon#about to read 6, iclass 25, count 0 2006.218.08:05:41.86#ibcon#read 6, iclass 25, count 0 2006.218.08:05:41.86#ibcon#end of sib2, iclass 25, count 0 2006.218.08:05:41.86#ibcon#*after write, iclass 25, count 0 2006.218.08:05:41.86#ibcon#*before return 0, iclass 25, count 0 2006.218.08:05:41.86#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.218.08:05:41.86#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.218.08:05:41.86#ibcon#about to clear, iclass 25 cls_cnt 0 2006.218.08:05:41.86#ibcon#cleared, iclass 25 cls_cnt 0 2006.218.08:05:41.86$vc4f8/vblo=5,744.99 2006.218.08:05:41.86#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.218.08:05:41.86#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.218.08:05:41.86#ibcon#ireg 17 cls_cnt 0 2006.218.08:05:41.86#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.218.08:05:41.86#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.218.08:05:41.86#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.218.08:05:41.86#ibcon#enter wrdev, iclass 27, count 0 2006.218.08:05:41.86#ibcon#first serial, iclass 27, count 0 2006.218.08:05:41.86#ibcon#enter sib2, iclass 27, count 0 2006.218.08:05:41.86#ibcon#flushed, iclass 27, count 0 2006.218.08:05:41.86#ibcon#about to write, iclass 27, count 0 2006.218.08:05:41.86#ibcon#wrote, iclass 27, count 0 2006.218.08:05:41.86#ibcon#about to read 3, iclass 27, count 0 2006.218.08:05:41.88#ibcon#read 3, iclass 27, count 0 2006.218.08:05:41.88#ibcon#about to read 4, iclass 27, count 0 2006.218.08:05:41.88#ibcon#read 4, iclass 27, count 0 2006.218.08:05:41.88#ibcon#about to read 5, iclass 27, count 0 2006.218.08:05:41.88#ibcon#read 5, iclass 27, count 0 2006.218.08:05:41.88#ibcon#about to read 6, iclass 27, count 0 2006.218.08:05:41.88#ibcon#read 6, iclass 27, count 0 2006.218.08:05:41.88#ibcon#end of sib2, iclass 27, count 0 2006.218.08:05:41.88#ibcon#*mode == 0, iclass 27, count 0 2006.218.08:05:41.88#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.218.08:05:41.88#ibcon#[28=FRQ=05,744.99\r\n] 2006.218.08:05:41.88#ibcon#*before write, iclass 27, count 0 2006.218.08:05:41.88#ibcon#enter sib2, iclass 27, count 0 2006.218.08:05:41.88#ibcon#flushed, iclass 27, count 0 2006.218.08:05:41.88#ibcon#about to write, iclass 27, count 0 2006.218.08:05:41.88#ibcon#wrote, iclass 27, count 0 2006.218.08:05:41.88#ibcon#about to read 3, iclass 27, count 0 2006.218.08:05:41.92#ibcon#read 3, iclass 27, count 0 2006.218.08:05:41.92#ibcon#about to read 4, iclass 27, count 0 2006.218.08:05:41.92#ibcon#read 4, iclass 27, count 0 2006.218.08:05:41.92#ibcon#about to read 5, iclass 27, count 0 2006.218.08:05:41.92#ibcon#read 5, iclass 27, count 0 2006.218.08:05:41.92#ibcon#about to read 6, iclass 27, count 0 2006.218.08:05:41.92#ibcon#read 6, iclass 27, count 0 2006.218.08:05:41.92#ibcon#end of sib2, iclass 27, count 0 2006.218.08:05:41.92#ibcon#*after write, iclass 27, count 0 2006.218.08:05:41.92#ibcon#*before return 0, iclass 27, count 0 2006.218.08:05:41.92#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.218.08:05:41.92#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.218.08:05:41.92#ibcon#about to clear, iclass 27 cls_cnt 0 2006.218.08:05:41.92#ibcon#cleared, iclass 27 cls_cnt 0 2006.218.08:05:41.92$vc4f8/vb=5,4 2006.218.08:05:41.92#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.218.08:05:41.92#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.218.08:05:41.92#ibcon#ireg 11 cls_cnt 2 2006.218.08:05:41.92#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.218.08:05:41.99#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.218.08:05:41.99#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.218.08:05:41.99#ibcon#enter wrdev, iclass 29, count 2 2006.218.08:05:41.99#ibcon#first serial, iclass 29, count 2 2006.218.08:05:41.99#ibcon#enter sib2, iclass 29, count 2 2006.218.08:05:41.99#ibcon#flushed, iclass 29, count 2 2006.218.08:05:41.99#ibcon#about to write, iclass 29, count 2 2006.218.08:05:41.99#ibcon#wrote, iclass 29, count 2 2006.218.08:05:41.99#ibcon#about to read 3, iclass 29, count 2 2006.218.08:05:42.00#ibcon#read 3, iclass 29, count 2 2006.218.08:05:42.00#ibcon#about to read 4, iclass 29, count 2 2006.218.08:05:42.00#ibcon#read 4, iclass 29, count 2 2006.218.08:05:42.00#ibcon#about to read 5, iclass 29, count 2 2006.218.08:05:42.00#ibcon#read 5, iclass 29, count 2 2006.218.08:05:42.00#ibcon#about to read 6, iclass 29, count 2 2006.218.08:05:42.00#ibcon#read 6, iclass 29, count 2 2006.218.08:05:42.00#ibcon#end of sib2, iclass 29, count 2 2006.218.08:05:42.00#ibcon#*mode == 0, iclass 29, count 2 2006.218.08:05:42.00#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.218.08:05:42.00#ibcon#[27=AT05-04\r\n] 2006.218.08:05:42.00#ibcon#*before write, iclass 29, count 2 2006.218.08:05:42.00#ibcon#enter sib2, iclass 29, count 2 2006.218.08:05:42.00#ibcon#flushed, iclass 29, count 2 2006.218.08:05:42.00#ibcon#about to write, iclass 29, count 2 2006.218.08:05:42.00#ibcon#wrote, iclass 29, count 2 2006.218.08:05:42.00#ibcon#about to read 3, iclass 29, count 2 2006.218.08:05:42.03#ibcon#read 3, iclass 29, count 2 2006.218.08:05:42.03#ibcon#about to read 4, iclass 29, count 2 2006.218.08:05:42.03#ibcon#read 4, iclass 29, count 2 2006.218.08:05:42.03#ibcon#about to read 5, iclass 29, count 2 2006.218.08:05:42.03#ibcon#read 5, iclass 29, count 2 2006.218.08:05:42.03#ibcon#about to read 6, iclass 29, count 2 2006.218.08:05:42.03#ibcon#read 6, iclass 29, count 2 2006.218.08:05:42.03#ibcon#end of sib2, iclass 29, count 2 2006.218.08:05:42.03#ibcon#*after write, iclass 29, count 2 2006.218.08:05:42.03#ibcon#*before return 0, iclass 29, count 2 2006.218.08:05:42.03#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.218.08:05:42.03#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.218.08:05:42.03#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.218.08:05:42.03#ibcon#ireg 7 cls_cnt 0 2006.218.08:05:42.03#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.218.08:05:42.15#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.218.08:05:42.15#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.218.08:05:42.15#ibcon#enter wrdev, iclass 29, count 0 2006.218.08:05:42.15#ibcon#first serial, iclass 29, count 0 2006.218.08:05:42.15#ibcon#enter sib2, iclass 29, count 0 2006.218.08:05:42.15#ibcon#flushed, iclass 29, count 0 2006.218.08:05:42.15#ibcon#about to write, iclass 29, count 0 2006.218.08:05:42.15#ibcon#wrote, iclass 29, count 0 2006.218.08:05:42.15#ibcon#about to read 3, iclass 29, count 0 2006.218.08:05:42.17#ibcon#read 3, iclass 29, count 0 2006.218.08:05:42.17#ibcon#about to read 4, iclass 29, count 0 2006.218.08:05:42.17#ibcon#read 4, iclass 29, count 0 2006.218.08:05:42.17#ibcon#about to read 5, iclass 29, count 0 2006.218.08:05:42.17#ibcon#read 5, iclass 29, count 0 2006.218.08:05:42.17#ibcon#about to read 6, iclass 29, count 0 2006.218.08:05:42.17#ibcon#read 6, iclass 29, count 0 2006.218.08:05:42.17#ibcon#end of sib2, iclass 29, count 0 2006.218.08:05:42.17#ibcon#*mode == 0, iclass 29, count 0 2006.218.08:05:42.17#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.218.08:05:42.17#ibcon#[27=USB\r\n] 2006.218.08:05:42.17#ibcon#*before write, iclass 29, count 0 2006.218.08:05:42.17#ibcon#enter sib2, iclass 29, count 0 2006.218.08:05:42.17#ibcon#flushed, iclass 29, count 0 2006.218.08:05:42.17#ibcon#about to write, iclass 29, count 0 2006.218.08:05:42.17#ibcon#wrote, iclass 29, count 0 2006.218.08:05:42.17#ibcon#about to read 3, iclass 29, count 0 2006.218.08:05:42.20#ibcon#read 3, iclass 29, count 0 2006.218.08:05:42.20#ibcon#about to read 4, iclass 29, count 0 2006.218.08:05:42.20#ibcon#read 4, iclass 29, count 0 2006.218.08:05:42.20#ibcon#about to read 5, iclass 29, count 0 2006.218.08:05:42.20#ibcon#read 5, iclass 29, count 0 2006.218.08:05:42.20#ibcon#about to read 6, iclass 29, count 0 2006.218.08:05:42.20#ibcon#read 6, iclass 29, count 0 2006.218.08:05:42.20#ibcon#end of sib2, iclass 29, count 0 2006.218.08:05:42.20#ibcon#*after write, iclass 29, count 0 2006.218.08:05:42.20#ibcon#*before return 0, iclass 29, count 0 2006.218.08:05:42.20#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.218.08:05:42.20#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.218.08:05:42.20#ibcon#about to clear, iclass 29 cls_cnt 0 2006.218.08:05:42.20#ibcon#cleared, iclass 29 cls_cnt 0 2006.218.08:05:42.20$vc4f8/vblo=6,752.99 2006.218.08:05:42.20#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.218.08:05:42.20#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.218.08:05:42.20#ibcon#ireg 17 cls_cnt 0 2006.218.08:05:42.20#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.218.08:05:42.20#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.218.08:05:42.20#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.218.08:05:42.20#ibcon#enter wrdev, iclass 31, count 0 2006.218.08:05:42.20#ibcon#first serial, iclass 31, count 0 2006.218.08:05:42.20#ibcon#enter sib2, iclass 31, count 0 2006.218.08:05:42.20#ibcon#flushed, iclass 31, count 0 2006.218.08:05:42.20#ibcon#about to write, iclass 31, count 0 2006.218.08:05:42.20#ibcon#wrote, iclass 31, count 0 2006.218.08:05:42.20#ibcon#about to read 3, iclass 31, count 0 2006.218.08:05:42.22#ibcon#read 3, iclass 31, count 0 2006.218.08:05:42.22#ibcon#about to read 4, iclass 31, count 0 2006.218.08:05:42.22#ibcon#read 4, iclass 31, count 0 2006.218.08:05:42.22#ibcon#about to read 5, iclass 31, count 0 2006.218.08:05:42.22#ibcon#read 5, iclass 31, count 0 2006.218.08:05:42.22#ibcon#about to read 6, iclass 31, count 0 2006.218.08:05:42.22#ibcon#read 6, iclass 31, count 0 2006.218.08:05:42.22#ibcon#end of sib2, iclass 31, count 0 2006.218.08:05:42.22#ibcon#*mode == 0, iclass 31, count 0 2006.218.08:05:42.22#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.218.08:05:42.22#ibcon#[28=FRQ=06,752.99\r\n] 2006.218.08:05:42.22#ibcon#*before write, iclass 31, count 0 2006.218.08:05:42.22#ibcon#enter sib2, iclass 31, count 0 2006.218.08:05:42.22#ibcon#flushed, iclass 31, count 0 2006.218.08:05:42.22#ibcon#about to write, iclass 31, count 0 2006.218.08:05:42.22#ibcon#wrote, iclass 31, count 0 2006.218.08:05:42.22#ibcon#about to read 3, iclass 31, count 0 2006.218.08:05:42.26#ibcon#read 3, iclass 31, count 0 2006.218.08:05:42.26#ibcon#about to read 4, iclass 31, count 0 2006.218.08:05:42.26#ibcon#read 4, iclass 31, count 0 2006.218.08:05:42.26#ibcon#about to read 5, iclass 31, count 0 2006.218.08:05:42.26#ibcon#read 5, iclass 31, count 0 2006.218.08:05:42.26#ibcon#about to read 6, iclass 31, count 0 2006.218.08:05:42.26#ibcon#read 6, iclass 31, count 0 2006.218.08:05:42.26#ibcon#end of sib2, iclass 31, count 0 2006.218.08:05:42.26#ibcon#*after write, iclass 31, count 0 2006.218.08:05:42.26#ibcon#*before return 0, iclass 31, count 0 2006.218.08:05:42.26#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.218.08:05:42.26#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.218.08:05:42.26#ibcon#about to clear, iclass 31 cls_cnt 0 2006.218.08:05:42.26#ibcon#cleared, iclass 31 cls_cnt 0 2006.218.08:05:42.26$vc4f8/vb=6,4 2006.218.08:05:42.26#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.218.08:05:42.26#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.218.08:05:42.26#ibcon#ireg 11 cls_cnt 2 2006.218.08:05:42.26#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.218.08:05:42.32#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.218.08:05:42.32#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.218.08:05:42.32#ibcon#enter wrdev, iclass 33, count 2 2006.218.08:05:42.32#ibcon#first serial, iclass 33, count 2 2006.218.08:05:42.32#ibcon#enter sib2, iclass 33, count 2 2006.218.08:05:42.32#ibcon#flushed, iclass 33, count 2 2006.218.08:05:42.32#ibcon#about to write, iclass 33, count 2 2006.218.08:05:42.32#ibcon#wrote, iclass 33, count 2 2006.218.08:05:42.32#ibcon#about to read 3, iclass 33, count 2 2006.218.08:05:42.34#ibcon#read 3, iclass 33, count 2 2006.218.08:05:42.34#ibcon#about to read 4, iclass 33, count 2 2006.218.08:05:42.34#ibcon#read 4, iclass 33, count 2 2006.218.08:05:42.34#ibcon#about to read 5, iclass 33, count 2 2006.218.08:05:42.34#ibcon#read 5, iclass 33, count 2 2006.218.08:05:42.34#ibcon#about to read 6, iclass 33, count 2 2006.218.08:05:42.34#ibcon#read 6, iclass 33, count 2 2006.218.08:05:42.34#ibcon#end of sib2, iclass 33, count 2 2006.218.08:05:42.34#ibcon#*mode == 0, iclass 33, count 2 2006.218.08:05:42.34#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.218.08:05:42.34#ibcon#[27=AT06-04\r\n] 2006.218.08:05:42.34#ibcon#*before write, iclass 33, count 2 2006.218.08:05:42.34#ibcon#enter sib2, iclass 33, count 2 2006.218.08:05:42.34#ibcon#flushed, iclass 33, count 2 2006.218.08:05:42.34#ibcon#about to write, iclass 33, count 2 2006.218.08:05:42.34#ibcon#wrote, iclass 33, count 2 2006.218.08:05:42.34#ibcon#about to read 3, iclass 33, count 2 2006.218.08:05:42.37#ibcon#read 3, iclass 33, count 2 2006.218.08:05:42.37#ibcon#about to read 4, iclass 33, count 2 2006.218.08:05:42.37#ibcon#read 4, iclass 33, count 2 2006.218.08:05:42.37#ibcon#about to read 5, iclass 33, count 2 2006.218.08:05:42.37#ibcon#read 5, iclass 33, count 2 2006.218.08:05:42.37#ibcon#about to read 6, iclass 33, count 2 2006.218.08:05:42.37#ibcon#read 6, iclass 33, count 2 2006.218.08:05:42.37#ibcon#end of sib2, iclass 33, count 2 2006.218.08:05:42.37#ibcon#*after write, iclass 33, count 2 2006.218.08:05:42.37#ibcon#*before return 0, iclass 33, count 2 2006.218.08:05:42.37#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.218.08:05:42.37#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.218.08:05:42.37#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.218.08:05:42.37#ibcon#ireg 7 cls_cnt 0 2006.218.08:05:42.37#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.218.08:05:42.49#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.218.08:05:42.49#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.218.08:05:42.49#ibcon#enter wrdev, iclass 33, count 0 2006.218.08:05:42.49#ibcon#first serial, iclass 33, count 0 2006.218.08:05:42.49#ibcon#enter sib2, iclass 33, count 0 2006.218.08:05:42.49#ibcon#flushed, iclass 33, count 0 2006.218.08:05:42.49#ibcon#about to write, iclass 33, count 0 2006.218.08:05:42.49#ibcon#wrote, iclass 33, count 0 2006.218.08:05:42.49#ibcon#about to read 3, iclass 33, count 0 2006.218.08:05:42.51#ibcon#read 3, iclass 33, count 0 2006.218.08:05:42.51#ibcon#about to read 4, iclass 33, count 0 2006.218.08:05:42.51#ibcon#read 4, iclass 33, count 0 2006.218.08:05:42.51#ibcon#about to read 5, iclass 33, count 0 2006.218.08:05:42.51#ibcon#read 5, iclass 33, count 0 2006.218.08:05:42.51#ibcon#about to read 6, iclass 33, count 0 2006.218.08:05:42.51#ibcon#read 6, iclass 33, count 0 2006.218.08:05:42.51#ibcon#end of sib2, iclass 33, count 0 2006.218.08:05:42.51#ibcon#*mode == 0, iclass 33, count 0 2006.218.08:05:42.51#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.218.08:05:42.51#ibcon#[27=USB\r\n] 2006.218.08:05:42.51#ibcon#*before write, iclass 33, count 0 2006.218.08:05:42.51#ibcon#enter sib2, iclass 33, count 0 2006.218.08:05:42.51#ibcon#flushed, iclass 33, count 0 2006.218.08:05:42.51#ibcon#about to write, iclass 33, count 0 2006.218.08:05:42.51#ibcon#wrote, iclass 33, count 0 2006.218.08:05:42.51#ibcon#about to read 3, iclass 33, count 0 2006.218.08:05:42.54#ibcon#read 3, iclass 33, count 0 2006.218.08:05:42.54#ibcon#about to read 4, iclass 33, count 0 2006.218.08:05:42.54#ibcon#read 4, iclass 33, count 0 2006.218.08:05:42.54#ibcon#about to read 5, iclass 33, count 0 2006.218.08:05:42.54#ibcon#read 5, iclass 33, count 0 2006.218.08:05:42.54#ibcon#about to read 6, iclass 33, count 0 2006.218.08:05:42.54#ibcon#read 6, iclass 33, count 0 2006.218.08:05:42.54#ibcon#end of sib2, iclass 33, count 0 2006.218.08:05:42.54#ibcon#*after write, iclass 33, count 0 2006.218.08:05:42.54#ibcon#*before return 0, iclass 33, count 0 2006.218.08:05:42.54#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.218.08:05:42.54#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.218.08:05:42.54#ibcon#about to clear, iclass 33 cls_cnt 0 2006.218.08:05:42.54#ibcon#cleared, iclass 33 cls_cnt 0 2006.218.08:05:42.54$vc4f8/vabw=wide 2006.218.08:05:42.54#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.218.08:05:42.54#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.218.08:05:42.54#ibcon#ireg 8 cls_cnt 0 2006.218.08:05:42.54#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.218.08:05:42.54#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.218.08:05:42.54#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.218.08:05:42.54#ibcon#enter wrdev, iclass 35, count 0 2006.218.08:05:42.54#ibcon#first serial, iclass 35, count 0 2006.218.08:05:42.54#ibcon#enter sib2, iclass 35, count 0 2006.218.08:05:42.54#ibcon#flushed, iclass 35, count 0 2006.218.08:05:42.54#ibcon#about to write, iclass 35, count 0 2006.218.08:05:42.54#ibcon#wrote, iclass 35, count 0 2006.218.08:05:42.54#ibcon#about to read 3, iclass 35, count 0 2006.218.08:05:42.56#ibcon#read 3, iclass 35, count 0 2006.218.08:05:42.56#ibcon#about to read 4, iclass 35, count 0 2006.218.08:05:42.56#ibcon#read 4, iclass 35, count 0 2006.218.08:05:42.56#ibcon#about to read 5, iclass 35, count 0 2006.218.08:05:42.56#ibcon#read 5, iclass 35, count 0 2006.218.08:05:42.56#ibcon#about to read 6, iclass 35, count 0 2006.218.08:05:42.56#ibcon#read 6, iclass 35, count 0 2006.218.08:05:42.56#ibcon#end of sib2, iclass 35, count 0 2006.218.08:05:42.56#ibcon#*mode == 0, iclass 35, count 0 2006.218.08:05:42.56#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.218.08:05:42.56#ibcon#[25=BW32\r\n] 2006.218.08:05:42.56#ibcon#*before write, iclass 35, count 0 2006.218.08:05:42.56#ibcon#enter sib2, iclass 35, count 0 2006.218.08:05:42.56#ibcon#flushed, iclass 35, count 0 2006.218.08:05:42.56#ibcon#about to write, iclass 35, count 0 2006.218.08:05:42.56#ibcon#wrote, iclass 35, count 0 2006.218.08:05:42.56#ibcon#about to read 3, iclass 35, count 0 2006.218.08:05:42.59#ibcon#read 3, iclass 35, count 0 2006.218.08:05:42.59#ibcon#about to read 4, iclass 35, count 0 2006.218.08:05:42.59#ibcon#read 4, iclass 35, count 0 2006.218.08:05:42.59#ibcon#about to read 5, iclass 35, count 0 2006.218.08:05:42.59#ibcon#read 5, iclass 35, count 0 2006.218.08:05:42.59#ibcon#about to read 6, iclass 35, count 0 2006.218.08:05:42.59#ibcon#read 6, iclass 35, count 0 2006.218.08:05:42.59#ibcon#end of sib2, iclass 35, count 0 2006.218.08:05:42.59#ibcon#*after write, iclass 35, count 0 2006.218.08:05:42.59#ibcon#*before return 0, iclass 35, count 0 2006.218.08:05:42.59#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.218.08:05:42.59#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.218.08:05:42.59#ibcon#about to clear, iclass 35 cls_cnt 0 2006.218.08:05:42.59#ibcon#cleared, iclass 35 cls_cnt 0 2006.218.08:05:42.59$vc4f8/vbbw=wide 2006.218.08:05:42.59#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.218.08:05:42.59#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.218.08:05:42.59#ibcon#ireg 8 cls_cnt 0 2006.218.08:05:42.59#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.218.08:05:42.66#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.218.08:05:42.66#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.218.08:05:42.66#ibcon#enter wrdev, iclass 37, count 0 2006.218.08:05:42.66#ibcon#first serial, iclass 37, count 0 2006.218.08:05:42.66#ibcon#enter sib2, iclass 37, count 0 2006.218.08:05:42.66#ibcon#flushed, iclass 37, count 0 2006.218.08:05:42.66#ibcon#about to write, iclass 37, count 0 2006.218.08:05:42.66#ibcon#wrote, iclass 37, count 0 2006.218.08:05:42.66#ibcon#about to read 3, iclass 37, count 0 2006.218.08:05:42.68#ibcon#read 3, iclass 37, count 0 2006.218.08:05:42.68#ibcon#about to read 4, iclass 37, count 0 2006.218.08:05:42.68#ibcon#read 4, iclass 37, count 0 2006.218.08:05:42.68#ibcon#about to read 5, iclass 37, count 0 2006.218.08:05:42.68#ibcon#read 5, iclass 37, count 0 2006.218.08:05:42.68#ibcon#about to read 6, iclass 37, count 0 2006.218.08:05:42.68#ibcon#read 6, iclass 37, count 0 2006.218.08:05:42.68#ibcon#end of sib2, iclass 37, count 0 2006.218.08:05:42.68#ibcon#*mode == 0, iclass 37, count 0 2006.218.08:05:42.68#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.218.08:05:42.68#ibcon#[27=BW32\r\n] 2006.218.08:05:42.68#ibcon#*before write, iclass 37, count 0 2006.218.08:05:42.68#ibcon#enter sib2, iclass 37, count 0 2006.218.08:05:42.68#ibcon#flushed, iclass 37, count 0 2006.218.08:05:42.68#ibcon#about to write, iclass 37, count 0 2006.218.08:05:42.68#ibcon#wrote, iclass 37, count 0 2006.218.08:05:42.68#ibcon#about to read 3, iclass 37, count 0 2006.218.08:05:42.71#ibcon#read 3, iclass 37, count 0 2006.218.08:05:42.71#ibcon#about to read 4, iclass 37, count 0 2006.218.08:05:42.71#ibcon#read 4, iclass 37, count 0 2006.218.08:05:42.71#ibcon#about to read 5, iclass 37, count 0 2006.218.08:05:42.71#ibcon#read 5, iclass 37, count 0 2006.218.08:05:42.71#ibcon#about to read 6, iclass 37, count 0 2006.218.08:05:42.71#ibcon#read 6, iclass 37, count 0 2006.218.08:05:42.71#ibcon#end of sib2, iclass 37, count 0 2006.218.08:05:42.71#ibcon#*after write, iclass 37, count 0 2006.218.08:05:42.71#ibcon#*before return 0, iclass 37, count 0 2006.218.08:05:42.71#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.218.08:05:42.71#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.218.08:05:42.71#ibcon#about to clear, iclass 37 cls_cnt 0 2006.218.08:05:42.71#ibcon#cleared, iclass 37 cls_cnt 0 2006.218.08:05:42.71$4f8m12a/ifd4f 2006.218.08:05:42.71$ifd4f/lo= 2006.218.08:05:42.71$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.218.08:05:42.71$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.218.08:05:42.71$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.218.08:05:42.71$ifd4f/patch= 2006.218.08:05:42.71$ifd4f/patch=lo1,a1,a2,a3,a4 2006.218.08:05:42.71$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.218.08:05:42.71$ifd4f/patch=lo3,a5,a6,a7,a8 2006.218.08:05:42.71$4f8m12a/"form=m,16.000,1:2 2006.218.08:05:42.71$4f8m12a/"tpicd 2006.218.08:05:42.71$4f8m12a/echo=off 2006.218.08:05:42.71$4f8m12a/xlog=off 2006.218.08:05:42.71:!2006.218.08:06:10 2006.218.08:05:51.14#trakl#Source acquired 2006.218.08:05:52.14#flagr#flagr/antenna,acquired 2006.218.08:06:10.00:preob 2006.218.08:06:11.14/onsource/TRACKING 2006.218.08:06:11.14:!2006.218.08:06:20 2006.218.08:06:20.00:data_valid=on 2006.218.08:06:20.00:midob 2006.218.08:06:20.14/onsource/TRACKING 2006.218.08:06:20.14/wx/30.96,1007.5,72 2006.218.08:06:20.26/cable/+6.3846E-03 2006.218.08:06:21.35/va/01,05,usb,yes,31,33 2006.218.08:06:21.35/va/02,04,usb,yes,29,31 2006.218.08:06:21.35/va/03,04,usb,yes,27,28 2006.218.08:06:21.35/va/04,04,usb,yes,31,33 2006.218.08:06:21.35/va/05,07,usb,yes,33,35 2006.218.08:06:21.35/va/06,06,usb,yes,32,32 2006.218.08:06:21.35/va/07,06,usb,yes,32,32 2006.218.08:06:21.35/va/08,07,usb,yes,31,30 2006.218.08:06:21.58/valo/01,532.99,yes,locked 2006.218.08:06:21.58/valo/02,572.99,yes,locked 2006.218.08:06:21.58/valo/03,672.99,yes,locked 2006.218.08:06:21.58/valo/04,832.99,yes,locked 2006.218.08:06:21.58/valo/05,652.99,yes,locked 2006.218.08:06:21.58/valo/06,772.99,yes,locked 2006.218.08:06:21.58/valo/07,832.99,yes,locked 2006.218.08:06:21.58/valo/08,852.99,yes,locked 2006.218.08:06:22.67/vb/01,04,usb,yes,30,29 2006.218.08:06:22.67/vb/02,04,usb,yes,32,33 2006.218.08:06:22.67/vb/03,04,usb,yes,28,32 2006.218.08:06:22.67/vb/04,04,usb,yes,29,29 2006.218.08:06:22.67/vb/05,04,usb,yes,27,31 2006.218.08:06:22.67/vb/06,04,usb,yes,28,31 2006.218.08:06:22.67/vb/07,04,usb,yes,31,30 2006.218.08:06:22.67/vb/08,04,usb,yes,28,31 2006.218.08:06:22.90/vblo/01,632.99,yes,locked 2006.218.08:06:22.90/vblo/02,640.99,yes,locked 2006.218.08:06:22.90/vblo/03,656.99,yes,locked 2006.218.08:06:22.90/vblo/04,712.99,yes,locked 2006.218.08:06:22.90/vblo/05,744.99,yes,locked 2006.218.08:06:22.90/vblo/06,752.99,yes,locked 2006.218.08:06:22.90/vblo/07,734.99,yes,locked 2006.218.08:06:22.90/vblo/08,744.99,yes,locked 2006.218.08:06:23.05/vabw/8 2006.218.08:06:23.20/vbbw/8 2006.218.08:06:23.29/xfe/off,on,15.5 2006.218.08:06:23.67/ifatt/23,28,28,28 2006.218.08:06:24.07/fmout-gps/S +4.67E-07 2006.218.08:06:24.11:!2006.218.08:07:20 2006.218.08:07:20.00:data_valid=off 2006.218.08:07:20.00:postob 2006.218.08:07:20.10/cable/+6.3833E-03 2006.218.08:07:20.10/wx/30.95,1007.5,72 2006.218.08:07:21.07/fmout-gps/S +4.65E-07 2006.218.08:07:21.07:scan_name=218-0808,k06218,70 2006.218.08:07:21.08:source=1116+128,111857.30,123441.7,2000.0,cw 2006.218.08:07:21.14#flagr#flagr/antenna,new-source 2006.218.08:07:22.14:checkk5 2006.218.08:07:22.51/chk_autoobs//k5ts1/ autoobs is running! 2006.218.08:07:22.90/chk_autoobs//k5ts2/ autoobs is running! 2006.218.08:07:23.28/chk_autoobs//k5ts3/ autoobs is running! 2006.218.08:07:23.65/chk_autoobs//k5ts4/ autoobs is running! 2006.218.08:07:24.02/chk_obsdata//k5ts1/T2180806??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.08:07:24.39/chk_obsdata//k5ts2/T2180806??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.08:07:24.76/chk_obsdata//k5ts3/T2180806??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.08:07:25.13/chk_obsdata//k5ts4/T2180806??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.08:07:25.82/k5log//k5ts1_log_newline 2006.218.08:07:26.50/k5log//k5ts2_log_newline 2006.218.08:07:27.19/k5log//k5ts3_log_newline 2006.218.08:07:27.89/k5log//k5ts4_log_newline 2006.218.08:07:27.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.218.08:07:27.91:4f8m12a=2 2006.218.08:07:27.91$4f8m12a/echo=on 2006.218.08:07:27.91$4f8m12a/pcalon 2006.218.08:07:27.91$pcalon/"no phase cal control is implemented here 2006.218.08:07:27.91$4f8m12a/"tpicd=stop 2006.218.08:07:27.91$4f8m12a/vc4f8 2006.218.08:07:27.91$vc4f8/valo=1,532.99 2006.218.08:07:27.92#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.218.08:07:27.92#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.218.08:07:27.92#ibcon#ireg 17 cls_cnt 0 2006.218.08:07:27.92#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.218.08:07:27.92#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.218.08:07:27.92#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.218.08:07:27.92#ibcon#enter wrdev, iclass 6, count 0 2006.218.08:07:27.92#ibcon#first serial, iclass 6, count 0 2006.218.08:07:27.92#ibcon#enter sib2, iclass 6, count 0 2006.218.08:07:27.92#ibcon#flushed, iclass 6, count 0 2006.218.08:07:27.92#ibcon#about to write, iclass 6, count 0 2006.218.08:07:27.92#ibcon#wrote, iclass 6, count 0 2006.218.08:07:27.92#ibcon#about to read 3, iclass 6, count 0 2006.218.08:07:27.93#ibcon#read 3, iclass 6, count 0 2006.218.08:07:27.93#ibcon#about to read 4, iclass 6, count 0 2006.218.08:07:27.93#ibcon#read 4, iclass 6, count 0 2006.218.08:07:27.93#ibcon#about to read 5, iclass 6, count 0 2006.218.08:07:27.93#ibcon#read 5, iclass 6, count 0 2006.218.08:07:27.93#ibcon#about to read 6, iclass 6, count 0 2006.218.08:07:27.93#ibcon#read 6, iclass 6, count 0 2006.218.08:07:27.93#ibcon#end of sib2, iclass 6, count 0 2006.218.08:07:27.93#ibcon#*mode == 0, iclass 6, count 0 2006.218.08:07:27.93#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.218.08:07:27.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.218.08:07:27.93#ibcon#*before write, iclass 6, count 0 2006.218.08:07:27.93#ibcon#enter sib2, iclass 6, count 0 2006.218.08:07:27.93#ibcon#flushed, iclass 6, count 0 2006.218.08:07:27.93#ibcon#about to write, iclass 6, count 0 2006.218.08:07:27.93#ibcon#wrote, iclass 6, count 0 2006.218.08:07:27.93#ibcon#about to read 3, iclass 6, count 0 2006.218.08:07:27.98#ibcon#read 3, iclass 6, count 0 2006.218.08:07:27.98#ibcon#about to read 4, iclass 6, count 0 2006.218.08:07:27.98#ibcon#read 4, iclass 6, count 0 2006.218.08:07:27.98#ibcon#about to read 5, iclass 6, count 0 2006.218.08:07:27.98#ibcon#read 5, iclass 6, count 0 2006.218.08:07:27.98#ibcon#about to read 6, iclass 6, count 0 2006.218.08:07:27.98#ibcon#read 6, iclass 6, count 0 2006.218.08:07:27.98#ibcon#end of sib2, iclass 6, count 0 2006.218.08:07:27.98#ibcon#*after write, iclass 6, count 0 2006.218.08:07:27.98#ibcon#*before return 0, iclass 6, count 0 2006.218.08:07:27.98#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.218.08:07:27.98#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.218.08:07:27.98#ibcon#about to clear, iclass 6 cls_cnt 0 2006.218.08:07:27.98#ibcon#cleared, iclass 6 cls_cnt 0 2006.218.08:07:27.98$vc4f8/va=1,5 2006.218.08:07:27.98#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.218.08:07:27.98#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.218.08:07:27.98#ibcon#ireg 11 cls_cnt 2 2006.218.08:07:27.98#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.218.08:07:27.98#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.218.08:07:27.98#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.218.08:07:27.98#ibcon#enter wrdev, iclass 10, count 2 2006.218.08:07:27.98#ibcon#first serial, iclass 10, count 2 2006.218.08:07:27.98#ibcon#enter sib2, iclass 10, count 2 2006.218.08:07:27.98#ibcon#flushed, iclass 10, count 2 2006.218.08:07:27.98#ibcon#about to write, iclass 10, count 2 2006.218.08:07:27.98#ibcon#wrote, iclass 10, count 2 2006.218.08:07:27.98#ibcon#about to read 3, iclass 10, count 2 2006.218.08:07:28.00#ibcon#read 3, iclass 10, count 2 2006.218.08:07:28.00#ibcon#about to read 4, iclass 10, count 2 2006.218.08:07:28.00#ibcon#read 4, iclass 10, count 2 2006.218.08:07:28.00#ibcon#about to read 5, iclass 10, count 2 2006.218.08:07:28.00#ibcon#read 5, iclass 10, count 2 2006.218.08:07:28.00#ibcon#about to read 6, iclass 10, count 2 2006.218.08:07:28.00#ibcon#read 6, iclass 10, count 2 2006.218.08:07:28.00#ibcon#end of sib2, iclass 10, count 2 2006.218.08:07:28.00#ibcon#*mode == 0, iclass 10, count 2 2006.218.08:07:28.00#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.218.08:07:28.00#ibcon#[25=AT01-05\r\n] 2006.218.08:07:28.00#ibcon#*before write, iclass 10, count 2 2006.218.08:07:28.00#ibcon#enter sib2, iclass 10, count 2 2006.218.08:07:28.00#ibcon#flushed, iclass 10, count 2 2006.218.08:07:28.00#ibcon#about to write, iclass 10, count 2 2006.218.08:07:28.00#ibcon#wrote, iclass 10, count 2 2006.218.08:07:28.00#ibcon#about to read 3, iclass 10, count 2 2006.218.08:07:28.03#ibcon#read 3, iclass 10, count 2 2006.218.08:07:28.03#ibcon#about to read 4, iclass 10, count 2 2006.218.08:07:28.03#ibcon#read 4, iclass 10, count 2 2006.218.08:07:28.03#ibcon#about to read 5, iclass 10, count 2 2006.218.08:07:28.03#ibcon#read 5, iclass 10, count 2 2006.218.08:07:28.03#ibcon#about to read 6, iclass 10, count 2 2006.218.08:07:28.03#ibcon#read 6, iclass 10, count 2 2006.218.08:07:28.03#ibcon#end of sib2, iclass 10, count 2 2006.218.08:07:28.03#ibcon#*after write, iclass 10, count 2 2006.218.08:07:28.03#ibcon#*before return 0, iclass 10, count 2 2006.218.08:07:28.03#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.218.08:07:28.03#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.218.08:07:28.03#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.218.08:07:28.03#ibcon#ireg 7 cls_cnt 0 2006.218.08:07:28.03#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.218.08:07:28.16#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.218.08:07:28.16#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.218.08:07:28.16#ibcon#enter wrdev, iclass 10, count 0 2006.218.08:07:28.16#ibcon#first serial, iclass 10, count 0 2006.218.08:07:28.16#ibcon#enter sib2, iclass 10, count 0 2006.218.08:07:28.16#ibcon#flushed, iclass 10, count 0 2006.218.08:07:28.16#ibcon#about to write, iclass 10, count 0 2006.218.08:07:28.16#ibcon#wrote, iclass 10, count 0 2006.218.08:07:28.16#ibcon#about to read 3, iclass 10, count 0 2006.218.08:07:28.17#ibcon#read 3, iclass 10, count 0 2006.218.08:07:28.17#ibcon#about to read 4, iclass 10, count 0 2006.218.08:07:28.17#ibcon#read 4, iclass 10, count 0 2006.218.08:07:28.17#ibcon#about to read 5, iclass 10, count 0 2006.218.08:07:28.17#ibcon#read 5, iclass 10, count 0 2006.218.08:07:28.17#ibcon#about to read 6, iclass 10, count 0 2006.218.08:07:28.17#ibcon#read 6, iclass 10, count 0 2006.218.08:07:28.17#ibcon#end of sib2, iclass 10, count 0 2006.218.08:07:28.17#ibcon#*mode == 0, iclass 10, count 0 2006.218.08:07:28.17#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.218.08:07:28.17#ibcon#[25=USB\r\n] 2006.218.08:07:28.17#ibcon#*before write, iclass 10, count 0 2006.218.08:07:28.17#ibcon#enter sib2, iclass 10, count 0 2006.218.08:07:28.17#ibcon#flushed, iclass 10, count 0 2006.218.08:07:28.17#ibcon#about to write, iclass 10, count 0 2006.218.08:07:28.17#ibcon#wrote, iclass 10, count 0 2006.218.08:07:28.17#ibcon#about to read 3, iclass 10, count 0 2006.218.08:07:28.20#ibcon#read 3, iclass 10, count 0 2006.218.08:07:28.20#ibcon#about to read 4, iclass 10, count 0 2006.218.08:07:28.20#ibcon#read 4, iclass 10, count 0 2006.218.08:07:28.20#ibcon#about to read 5, iclass 10, count 0 2006.218.08:07:28.20#ibcon#read 5, iclass 10, count 0 2006.218.08:07:28.20#ibcon#about to read 6, iclass 10, count 0 2006.218.08:07:28.20#ibcon#read 6, iclass 10, count 0 2006.218.08:07:28.20#ibcon#end of sib2, iclass 10, count 0 2006.218.08:07:28.20#ibcon#*after write, iclass 10, count 0 2006.218.08:07:28.20#ibcon#*before return 0, iclass 10, count 0 2006.218.08:07:28.20#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.218.08:07:28.20#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.218.08:07:28.20#ibcon#about to clear, iclass 10 cls_cnt 0 2006.218.08:07:28.20#ibcon#cleared, iclass 10 cls_cnt 0 2006.218.08:07:28.20$vc4f8/valo=2,572.99 2006.218.08:07:28.20#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.218.08:07:28.20#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.218.08:07:28.20#ibcon#ireg 17 cls_cnt 0 2006.218.08:07:28.20#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.218.08:07:28.20#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.218.08:07:28.20#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.218.08:07:28.20#ibcon#enter wrdev, iclass 12, count 0 2006.218.08:07:28.20#ibcon#first serial, iclass 12, count 0 2006.218.08:07:28.20#ibcon#enter sib2, iclass 12, count 0 2006.218.08:07:28.20#ibcon#flushed, iclass 12, count 0 2006.218.08:07:28.20#ibcon#about to write, iclass 12, count 0 2006.218.08:07:28.20#ibcon#wrote, iclass 12, count 0 2006.218.08:07:28.20#ibcon#about to read 3, iclass 12, count 0 2006.218.08:07:28.23#ibcon#read 3, iclass 12, count 0 2006.218.08:07:28.23#ibcon#about to read 4, iclass 12, count 0 2006.218.08:07:28.23#ibcon#read 4, iclass 12, count 0 2006.218.08:07:28.23#ibcon#about to read 5, iclass 12, count 0 2006.218.08:07:28.23#ibcon#read 5, iclass 12, count 0 2006.218.08:07:28.23#ibcon#about to read 6, iclass 12, count 0 2006.218.08:07:28.23#ibcon#read 6, iclass 12, count 0 2006.218.08:07:28.23#ibcon#end of sib2, iclass 12, count 0 2006.218.08:07:28.23#ibcon#*mode == 0, iclass 12, count 0 2006.218.08:07:28.23#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.218.08:07:28.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.218.08:07:28.23#ibcon#*before write, iclass 12, count 0 2006.218.08:07:28.23#ibcon#enter sib2, iclass 12, count 0 2006.218.08:07:28.23#ibcon#flushed, iclass 12, count 0 2006.218.08:07:28.23#ibcon#about to write, iclass 12, count 0 2006.218.08:07:28.23#ibcon#wrote, iclass 12, count 0 2006.218.08:07:28.23#ibcon#about to read 3, iclass 12, count 0 2006.218.08:07:28.27#ibcon#read 3, iclass 12, count 0 2006.218.08:07:28.27#ibcon#about to read 4, iclass 12, count 0 2006.218.08:07:28.27#ibcon#read 4, iclass 12, count 0 2006.218.08:07:28.27#ibcon#about to read 5, iclass 12, count 0 2006.218.08:07:28.27#ibcon#read 5, iclass 12, count 0 2006.218.08:07:28.27#ibcon#about to read 6, iclass 12, count 0 2006.218.08:07:28.27#ibcon#read 6, iclass 12, count 0 2006.218.08:07:28.27#ibcon#end of sib2, iclass 12, count 0 2006.218.08:07:28.27#ibcon#*after write, iclass 12, count 0 2006.218.08:07:28.27#ibcon#*before return 0, iclass 12, count 0 2006.218.08:07:28.27#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.218.08:07:28.27#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.218.08:07:28.27#ibcon#about to clear, iclass 12 cls_cnt 0 2006.218.08:07:28.27#ibcon#cleared, iclass 12 cls_cnt 0 2006.218.08:07:28.27$vc4f8/va=2,4 2006.218.08:07:28.27#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.218.08:07:28.27#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.218.08:07:28.27#ibcon#ireg 11 cls_cnt 2 2006.218.08:07:28.27#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.218.08:07:28.32#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.218.08:07:28.32#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.218.08:07:28.32#ibcon#enter wrdev, iclass 14, count 2 2006.218.08:07:28.32#ibcon#first serial, iclass 14, count 2 2006.218.08:07:28.32#ibcon#enter sib2, iclass 14, count 2 2006.218.08:07:28.32#ibcon#flushed, iclass 14, count 2 2006.218.08:07:28.32#ibcon#about to write, iclass 14, count 2 2006.218.08:07:28.32#ibcon#wrote, iclass 14, count 2 2006.218.08:07:28.32#ibcon#about to read 3, iclass 14, count 2 2006.218.08:07:28.34#ibcon#read 3, iclass 14, count 2 2006.218.08:07:28.34#ibcon#about to read 4, iclass 14, count 2 2006.218.08:07:28.34#ibcon#read 4, iclass 14, count 2 2006.218.08:07:28.34#ibcon#about to read 5, iclass 14, count 2 2006.218.08:07:28.34#ibcon#read 5, iclass 14, count 2 2006.218.08:07:28.34#ibcon#about to read 6, iclass 14, count 2 2006.218.08:07:28.34#ibcon#read 6, iclass 14, count 2 2006.218.08:07:28.34#ibcon#end of sib2, iclass 14, count 2 2006.218.08:07:28.34#ibcon#*mode == 0, iclass 14, count 2 2006.218.08:07:28.34#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.218.08:07:28.34#ibcon#[25=AT02-04\r\n] 2006.218.08:07:28.34#ibcon#*before write, iclass 14, count 2 2006.218.08:07:28.34#ibcon#enter sib2, iclass 14, count 2 2006.218.08:07:28.34#ibcon#flushed, iclass 14, count 2 2006.218.08:07:28.34#ibcon#about to write, iclass 14, count 2 2006.218.08:07:28.34#ibcon#wrote, iclass 14, count 2 2006.218.08:07:28.34#ibcon#about to read 3, iclass 14, count 2 2006.218.08:07:28.37#ibcon#read 3, iclass 14, count 2 2006.218.08:07:28.37#ibcon#about to read 4, iclass 14, count 2 2006.218.08:07:28.37#ibcon#read 4, iclass 14, count 2 2006.218.08:07:28.37#ibcon#about to read 5, iclass 14, count 2 2006.218.08:07:28.37#ibcon#read 5, iclass 14, count 2 2006.218.08:07:28.37#ibcon#about to read 6, iclass 14, count 2 2006.218.08:07:28.37#ibcon#read 6, iclass 14, count 2 2006.218.08:07:28.37#ibcon#end of sib2, iclass 14, count 2 2006.218.08:07:28.37#ibcon#*after write, iclass 14, count 2 2006.218.08:07:28.37#ibcon#*before return 0, iclass 14, count 2 2006.218.08:07:28.37#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.218.08:07:28.37#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.218.08:07:28.37#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.218.08:07:28.37#ibcon#ireg 7 cls_cnt 0 2006.218.08:07:28.37#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.218.08:07:28.49#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.218.08:07:28.49#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.218.08:07:28.49#ibcon#enter wrdev, iclass 14, count 0 2006.218.08:07:28.49#ibcon#first serial, iclass 14, count 0 2006.218.08:07:28.49#ibcon#enter sib2, iclass 14, count 0 2006.218.08:07:28.49#ibcon#flushed, iclass 14, count 0 2006.218.08:07:28.49#ibcon#about to write, iclass 14, count 0 2006.218.08:07:28.49#ibcon#wrote, iclass 14, count 0 2006.218.08:07:28.49#ibcon#about to read 3, iclass 14, count 0 2006.218.08:07:28.51#ibcon#read 3, iclass 14, count 0 2006.218.08:07:28.51#ibcon#about to read 4, iclass 14, count 0 2006.218.08:07:28.51#ibcon#read 4, iclass 14, count 0 2006.218.08:07:28.51#ibcon#about to read 5, iclass 14, count 0 2006.218.08:07:28.51#ibcon#read 5, iclass 14, count 0 2006.218.08:07:28.51#ibcon#about to read 6, iclass 14, count 0 2006.218.08:07:28.51#ibcon#read 6, iclass 14, count 0 2006.218.08:07:28.51#ibcon#end of sib2, iclass 14, count 0 2006.218.08:07:28.51#ibcon#*mode == 0, iclass 14, count 0 2006.218.08:07:28.51#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.218.08:07:28.51#ibcon#[25=USB\r\n] 2006.218.08:07:28.51#ibcon#*before write, iclass 14, count 0 2006.218.08:07:28.51#ibcon#enter sib2, iclass 14, count 0 2006.218.08:07:28.51#ibcon#flushed, iclass 14, count 0 2006.218.08:07:28.51#ibcon#about to write, iclass 14, count 0 2006.218.08:07:28.51#ibcon#wrote, iclass 14, count 0 2006.218.08:07:28.51#ibcon#about to read 3, iclass 14, count 0 2006.218.08:07:28.54#ibcon#read 3, iclass 14, count 0 2006.218.08:07:28.54#ibcon#about to read 4, iclass 14, count 0 2006.218.08:07:28.54#ibcon#read 4, iclass 14, count 0 2006.218.08:07:28.54#ibcon#about to read 5, iclass 14, count 0 2006.218.08:07:28.54#ibcon#read 5, iclass 14, count 0 2006.218.08:07:28.54#ibcon#about to read 6, iclass 14, count 0 2006.218.08:07:28.54#ibcon#read 6, iclass 14, count 0 2006.218.08:07:28.54#ibcon#end of sib2, iclass 14, count 0 2006.218.08:07:28.54#ibcon#*after write, iclass 14, count 0 2006.218.08:07:28.54#ibcon#*before return 0, iclass 14, count 0 2006.218.08:07:28.54#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.218.08:07:28.54#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.218.08:07:28.54#ibcon#about to clear, iclass 14 cls_cnt 0 2006.218.08:07:28.54#ibcon#cleared, iclass 14 cls_cnt 0 2006.218.08:07:28.54$vc4f8/valo=3,672.99 2006.218.08:07:28.54#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.218.08:07:28.54#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.218.08:07:28.54#ibcon#ireg 17 cls_cnt 0 2006.218.08:07:28.54#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.218.08:07:28.54#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.218.08:07:28.54#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.218.08:07:28.54#ibcon#enter wrdev, iclass 16, count 0 2006.218.08:07:28.54#ibcon#first serial, iclass 16, count 0 2006.218.08:07:28.54#ibcon#enter sib2, iclass 16, count 0 2006.218.08:07:28.54#ibcon#flushed, iclass 16, count 0 2006.218.08:07:28.54#ibcon#about to write, iclass 16, count 0 2006.218.08:07:28.54#ibcon#wrote, iclass 16, count 0 2006.218.08:07:28.54#ibcon#about to read 3, iclass 16, count 0 2006.218.08:07:28.57#ibcon#read 3, iclass 16, count 0 2006.218.08:07:28.57#ibcon#about to read 4, iclass 16, count 0 2006.218.08:07:28.57#ibcon#read 4, iclass 16, count 0 2006.218.08:07:28.57#ibcon#about to read 5, iclass 16, count 0 2006.218.08:07:28.57#ibcon#read 5, iclass 16, count 0 2006.218.08:07:28.57#ibcon#about to read 6, iclass 16, count 0 2006.218.08:07:28.57#ibcon#read 6, iclass 16, count 0 2006.218.08:07:28.57#ibcon#end of sib2, iclass 16, count 0 2006.218.08:07:28.57#ibcon#*mode == 0, iclass 16, count 0 2006.218.08:07:28.57#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.218.08:07:28.57#ibcon#[26=FRQ=03,672.99\r\n] 2006.218.08:07:28.57#ibcon#*before write, iclass 16, count 0 2006.218.08:07:28.57#ibcon#enter sib2, iclass 16, count 0 2006.218.08:07:28.57#ibcon#flushed, iclass 16, count 0 2006.218.08:07:28.57#ibcon#about to write, iclass 16, count 0 2006.218.08:07:28.57#ibcon#wrote, iclass 16, count 0 2006.218.08:07:28.57#ibcon#about to read 3, iclass 16, count 0 2006.218.08:07:28.61#ibcon#read 3, iclass 16, count 0 2006.218.08:07:28.61#ibcon#about to read 4, iclass 16, count 0 2006.218.08:07:28.61#ibcon#read 4, iclass 16, count 0 2006.218.08:07:28.61#ibcon#about to read 5, iclass 16, count 0 2006.218.08:07:28.61#ibcon#read 5, iclass 16, count 0 2006.218.08:07:28.61#ibcon#about to read 6, iclass 16, count 0 2006.218.08:07:28.61#ibcon#read 6, iclass 16, count 0 2006.218.08:07:28.61#ibcon#end of sib2, iclass 16, count 0 2006.218.08:07:28.61#ibcon#*after write, iclass 16, count 0 2006.218.08:07:28.61#ibcon#*before return 0, iclass 16, count 0 2006.218.08:07:28.61#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.218.08:07:28.61#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.218.08:07:28.61#ibcon#about to clear, iclass 16 cls_cnt 0 2006.218.08:07:28.61#ibcon#cleared, iclass 16 cls_cnt 0 2006.218.08:07:28.61$vc4f8/va=3,4 2006.218.08:07:28.61#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.218.08:07:28.61#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.218.08:07:28.61#ibcon#ireg 11 cls_cnt 2 2006.218.08:07:28.61#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.218.08:07:28.66#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.218.08:07:28.66#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.218.08:07:28.66#ibcon#enter wrdev, iclass 18, count 2 2006.218.08:07:28.66#ibcon#first serial, iclass 18, count 2 2006.218.08:07:28.66#ibcon#enter sib2, iclass 18, count 2 2006.218.08:07:28.66#ibcon#flushed, iclass 18, count 2 2006.218.08:07:28.66#ibcon#about to write, iclass 18, count 2 2006.218.08:07:28.66#ibcon#wrote, iclass 18, count 2 2006.218.08:07:28.66#ibcon#about to read 3, iclass 18, count 2 2006.218.08:07:28.68#ibcon#read 3, iclass 18, count 2 2006.218.08:07:28.68#ibcon#about to read 4, iclass 18, count 2 2006.218.08:07:28.68#ibcon#read 4, iclass 18, count 2 2006.218.08:07:28.68#ibcon#about to read 5, iclass 18, count 2 2006.218.08:07:28.68#ibcon#read 5, iclass 18, count 2 2006.218.08:07:28.68#ibcon#about to read 6, iclass 18, count 2 2006.218.08:07:28.68#ibcon#read 6, iclass 18, count 2 2006.218.08:07:28.68#ibcon#end of sib2, iclass 18, count 2 2006.218.08:07:28.68#ibcon#*mode == 0, iclass 18, count 2 2006.218.08:07:28.68#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.218.08:07:28.68#ibcon#[25=AT03-04\r\n] 2006.218.08:07:28.68#ibcon#*before write, iclass 18, count 2 2006.218.08:07:28.68#ibcon#enter sib2, iclass 18, count 2 2006.218.08:07:28.68#ibcon#flushed, iclass 18, count 2 2006.218.08:07:28.68#ibcon#about to write, iclass 18, count 2 2006.218.08:07:28.68#ibcon#wrote, iclass 18, count 2 2006.218.08:07:28.68#ibcon#about to read 3, iclass 18, count 2 2006.218.08:07:28.71#ibcon#read 3, iclass 18, count 2 2006.218.08:07:28.71#ibcon#about to read 4, iclass 18, count 2 2006.218.08:07:28.71#ibcon#read 4, iclass 18, count 2 2006.218.08:07:28.71#ibcon#about to read 5, iclass 18, count 2 2006.218.08:07:28.71#ibcon#read 5, iclass 18, count 2 2006.218.08:07:28.71#ibcon#about to read 6, iclass 18, count 2 2006.218.08:07:28.71#ibcon#read 6, iclass 18, count 2 2006.218.08:07:28.71#ibcon#end of sib2, iclass 18, count 2 2006.218.08:07:28.71#ibcon#*after write, iclass 18, count 2 2006.218.08:07:28.71#ibcon#*before return 0, iclass 18, count 2 2006.218.08:07:28.71#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.218.08:07:28.71#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.218.08:07:28.71#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.218.08:07:28.71#ibcon#ireg 7 cls_cnt 0 2006.218.08:07:28.71#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.218.08:07:28.83#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.218.08:07:28.83#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.218.08:07:28.83#ibcon#enter wrdev, iclass 18, count 0 2006.218.08:07:28.83#ibcon#first serial, iclass 18, count 0 2006.218.08:07:28.83#ibcon#enter sib2, iclass 18, count 0 2006.218.08:07:28.83#ibcon#flushed, iclass 18, count 0 2006.218.08:07:28.83#ibcon#about to write, iclass 18, count 0 2006.218.08:07:28.83#ibcon#wrote, iclass 18, count 0 2006.218.08:07:28.83#ibcon#about to read 3, iclass 18, count 0 2006.218.08:07:28.85#ibcon#read 3, iclass 18, count 0 2006.218.08:07:28.85#ibcon#about to read 4, iclass 18, count 0 2006.218.08:07:28.85#ibcon#read 4, iclass 18, count 0 2006.218.08:07:28.85#ibcon#about to read 5, iclass 18, count 0 2006.218.08:07:28.85#ibcon#read 5, iclass 18, count 0 2006.218.08:07:28.85#ibcon#about to read 6, iclass 18, count 0 2006.218.08:07:28.85#ibcon#read 6, iclass 18, count 0 2006.218.08:07:28.85#ibcon#end of sib2, iclass 18, count 0 2006.218.08:07:28.85#ibcon#*mode == 0, iclass 18, count 0 2006.218.08:07:28.85#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.218.08:07:28.85#ibcon#[25=USB\r\n] 2006.218.08:07:28.85#ibcon#*before write, iclass 18, count 0 2006.218.08:07:28.85#ibcon#enter sib2, iclass 18, count 0 2006.218.08:07:28.85#ibcon#flushed, iclass 18, count 0 2006.218.08:07:28.85#ibcon#about to write, iclass 18, count 0 2006.218.08:07:28.85#ibcon#wrote, iclass 18, count 0 2006.218.08:07:28.85#ibcon#about to read 3, iclass 18, count 0 2006.218.08:07:28.88#ibcon#read 3, iclass 18, count 0 2006.218.08:07:28.88#ibcon#about to read 4, iclass 18, count 0 2006.218.08:07:28.88#ibcon#read 4, iclass 18, count 0 2006.218.08:07:28.88#ibcon#about to read 5, iclass 18, count 0 2006.218.08:07:28.88#ibcon#read 5, iclass 18, count 0 2006.218.08:07:28.88#ibcon#about to read 6, iclass 18, count 0 2006.218.08:07:28.88#ibcon#read 6, iclass 18, count 0 2006.218.08:07:28.88#ibcon#end of sib2, iclass 18, count 0 2006.218.08:07:28.88#ibcon#*after write, iclass 18, count 0 2006.218.08:07:28.88#ibcon#*before return 0, iclass 18, count 0 2006.218.08:07:28.88#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.218.08:07:28.88#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.218.08:07:28.88#ibcon#about to clear, iclass 18 cls_cnt 0 2006.218.08:07:28.88#ibcon#cleared, iclass 18 cls_cnt 0 2006.218.08:07:28.88$vc4f8/valo=4,832.99 2006.218.08:07:28.88#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.218.08:07:28.88#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.218.08:07:28.88#ibcon#ireg 17 cls_cnt 0 2006.218.08:07:28.88#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.218.08:07:28.88#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.218.08:07:28.88#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.218.08:07:28.88#ibcon#enter wrdev, iclass 20, count 0 2006.218.08:07:28.88#ibcon#first serial, iclass 20, count 0 2006.218.08:07:28.88#ibcon#enter sib2, iclass 20, count 0 2006.218.08:07:28.88#ibcon#flushed, iclass 20, count 0 2006.218.08:07:28.88#ibcon#about to write, iclass 20, count 0 2006.218.08:07:28.88#ibcon#wrote, iclass 20, count 0 2006.218.08:07:28.88#ibcon#about to read 3, iclass 20, count 0 2006.218.08:07:28.91#ibcon#read 3, iclass 20, count 0 2006.218.08:07:28.91#ibcon#about to read 4, iclass 20, count 0 2006.218.08:07:28.91#ibcon#read 4, iclass 20, count 0 2006.218.08:07:28.91#ibcon#about to read 5, iclass 20, count 0 2006.218.08:07:28.91#ibcon#read 5, iclass 20, count 0 2006.218.08:07:28.91#ibcon#about to read 6, iclass 20, count 0 2006.218.08:07:28.91#ibcon#read 6, iclass 20, count 0 2006.218.08:07:28.91#ibcon#end of sib2, iclass 20, count 0 2006.218.08:07:28.91#ibcon#*mode == 0, iclass 20, count 0 2006.218.08:07:28.91#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.218.08:07:28.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.218.08:07:28.91#ibcon#*before write, iclass 20, count 0 2006.218.08:07:28.91#ibcon#enter sib2, iclass 20, count 0 2006.218.08:07:28.91#ibcon#flushed, iclass 20, count 0 2006.218.08:07:28.91#ibcon#about to write, iclass 20, count 0 2006.218.08:07:28.91#ibcon#wrote, iclass 20, count 0 2006.218.08:07:28.91#ibcon#about to read 3, iclass 20, count 0 2006.218.08:07:28.95#ibcon#read 3, iclass 20, count 0 2006.218.08:07:28.95#ibcon#about to read 4, iclass 20, count 0 2006.218.08:07:28.95#ibcon#read 4, iclass 20, count 0 2006.218.08:07:28.95#ibcon#about to read 5, iclass 20, count 0 2006.218.08:07:28.95#ibcon#read 5, iclass 20, count 0 2006.218.08:07:28.95#ibcon#about to read 6, iclass 20, count 0 2006.218.08:07:28.95#ibcon#read 6, iclass 20, count 0 2006.218.08:07:28.95#ibcon#end of sib2, iclass 20, count 0 2006.218.08:07:28.95#ibcon#*after write, iclass 20, count 0 2006.218.08:07:28.95#ibcon#*before return 0, iclass 20, count 0 2006.218.08:07:28.95#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.218.08:07:28.95#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.218.08:07:28.95#ibcon#about to clear, iclass 20 cls_cnt 0 2006.218.08:07:28.95#ibcon#cleared, iclass 20 cls_cnt 0 2006.218.08:07:28.95$vc4f8/va=4,4 2006.218.08:07:28.95#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.218.08:07:28.95#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.218.08:07:28.95#ibcon#ireg 11 cls_cnt 2 2006.218.08:07:28.95#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.218.08:07:29.00#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.218.08:07:29.00#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.218.08:07:29.00#ibcon#enter wrdev, iclass 22, count 2 2006.218.08:07:29.00#ibcon#first serial, iclass 22, count 2 2006.218.08:07:29.00#ibcon#enter sib2, iclass 22, count 2 2006.218.08:07:29.00#ibcon#flushed, iclass 22, count 2 2006.218.08:07:29.00#ibcon#about to write, iclass 22, count 2 2006.218.08:07:29.00#ibcon#wrote, iclass 22, count 2 2006.218.08:07:29.00#ibcon#about to read 3, iclass 22, count 2 2006.218.08:07:29.02#ibcon#read 3, iclass 22, count 2 2006.218.08:07:29.02#ibcon#about to read 4, iclass 22, count 2 2006.218.08:07:29.02#ibcon#read 4, iclass 22, count 2 2006.218.08:07:29.02#ibcon#about to read 5, iclass 22, count 2 2006.218.08:07:29.02#ibcon#read 5, iclass 22, count 2 2006.218.08:07:29.02#ibcon#about to read 6, iclass 22, count 2 2006.218.08:07:29.02#ibcon#read 6, iclass 22, count 2 2006.218.08:07:29.02#ibcon#end of sib2, iclass 22, count 2 2006.218.08:07:29.02#ibcon#*mode == 0, iclass 22, count 2 2006.218.08:07:29.02#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.218.08:07:29.02#ibcon#[25=AT04-04\r\n] 2006.218.08:07:29.02#ibcon#*before write, iclass 22, count 2 2006.218.08:07:29.02#ibcon#enter sib2, iclass 22, count 2 2006.218.08:07:29.02#ibcon#flushed, iclass 22, count 2 2006.218.08:07:29.02#ibcon#about to write, iclass 22, count 2 2006.218.08:07:29.02#ibcon#wrote, iclass 22, count 2 2006.218.08:07:29.02#ibcon#about to read 3, iclass 22, count 2 2006.218.08:07:29.05#ibcon#read 3, iclass 22, count 2 2006.218.08:07:29.05#ibcon#about to read 4, iclass 22, count 2 2006.218.08:07:29.05#ibcon#read 4, iclass 22, count 2 2006.218.08:07:29.05#ibcon#about to read 5, iclass 22, count 2 2006.218.08:07:29.05#ibcon#read 5, iclass 22, count 2 2006.218.08:07:29.05#ibcon#about to read 6, iclass 22, count 2 2006.218.08:07:29.05#ibcon#read 6, iclass 22, count 2 2006.218.08:07:29.05#ibcon#end of sib2, iclass 22, count 2 2006.218.08:07:29.05#ibcon#*after write, iclass 22, count 2 2006.218.08:07:29.05#ibcon#*before return 0, iclass 22, count 2 2006.218.08:07:29.05#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.218.08:07:29.05#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.218.08:07:29.05#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.218.08:07:29.05#ibcon#ireg 7 cls_cnt 0 2006.218.08:07:29.05#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.218.08:07:29.17#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.218.08:07:29.17#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.218.08:07:29.17#ibcon#enter wrdev, iclass 22, count 0 2006.218.08:07:29.17#ibcon#first serial, iclass 22, count 0 2006.218.08:07:29.17#ibcon#enter sib2, iclass 22, count 0 2006.218.08:07:29.17#ibcon#flushed, iclass 22, count 0 2006.218.08:07:29.17#ibcon#about to write, iclass 22, count 0 2006.218.08:07:29.17#ibcon#wrote, iclass 22, count 0 2006.218.08:07:29.17#ibcon#about to read 3, iclass 22, count 0 2006.218.08:07:29.19#ibcon#read 3, iclass 22, count 0 2006.218.08:07:29.19#ibcon#about to read 4, iclass 22, count 0 2006.218.08:07:29.19#ibcon#read 4, iclass 22, count 0 2006.218.08:07:29.19#ibcon#about to read 5, iclass 22, count 0 2006.218.08:07:29.19#ibcon#read 5, iclass 22, count 0 2006.218.08:07:29.19#ibcon#about to read 6, iclass 22, count 0 2006.218.08:07:29.19#ibcon#read 6, iclass 22, count 0 2006.218.08:07:29.19#ibcon#end of sib2, iclass 22, count 0 2006.218.08:07:29.19#ibcon#*mode == 0, iclass 22, count 0 2006.218.08:07:29.19#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.218.08:07:29.19#ibcon#[25=USB\r\n] 2006.218.08:07:29.19#ibcon#*before write, iclass 22, count 0 2006.218.08:07:29.19#ibcon#enter sib2, iclass 22, count 0 2006.218.08:07:29.19#ibcon#flushed, iclass 22, count 0 2006.218.08:07:29.19#ibcon#about to write, iclass 22, count 0 2006.218.08:07:29.19#ibcon#wrote, iclass 22, count 0 2006.218.08:07:29.19#ibcon#about to read 3, iclass 22, count 0 2006.218.08:07:29.22#ibcon#read 3, iclass 22, count 0 2006.218.08:07:29.22#ibcon#about to read 4, iclass 22, count 0 2006.218.08:07:29.22#ibcon#read 4, iclass 22, count 0 2006.218.08:07:29.22#ibcon#about to read 5, iclass 22, count 0 2006.218.08:07:29.22#ibcon#read 5, iclass 22, count 0 2006.218.08:07:29.22#ibcon#about to read 6, iclass 22, count 0 2006.218.08:07:29.22#ibcon#read 6, iclass 22, count 0 2006.218.08:07:29.22#ibcon#end of sib2, iclass 22, count 0 2006.218.08:07:29.22#ibcon#*after write, iclass 22, count 0 2006.218.08:07:29.22#ibcon#*before return 0, iclass 22, count 0 2006.218.08:07:29.22#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.218.08:07:29.22#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.218.08:07:29.22#ibcon#about to clear, iclass 22 cls_cnt 0 2006.218.08:07:29.22#ibcon#cleared, iclass 22 cls_cnt 0 2006.218.08:07:29.22$vc4f8/valo=5,652.99 2006.218.08:07:29.22#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.218.08:07:29.22#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.218.08:07:29.22#ibcon#ireg 17 cls_cnt 0 2006.218.08:07:29.22#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.218.08:07:29.22#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.218.08:07:29.22#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.218.08:07:29.22#ibcon#enter wrdev, iclass 24, count 0 2006.218.08:07:29.22#ibcon#first serial, iclass 24, count 0 2006.218.08:07:29.22#ibcon#enter sib2, iclass 24, count 0 2006.218.08:07:29.22#ibcon#flushed, iclass 24, count 0 2006.218.08:07:29.22#ibcon#about to write, iclass 24, count 0 2006.218.08:07:29.22#ibcon#wrote, iclass 24, count 0 2006.218.08:07:29.22#ibcon#about to read 3, iclass 24, count 0 2006.218.08:07:29.24#ibcon#read 3, iclass 24, count 0 2006.218.08:07:29.24#ibcon#about to read 4, iclass 24, count 0 2006.218.08:07:29.24#ibcon#read 4, iclass 24, count 0 2006.218.08:07:29.24#ibcon#about to read 5, iclass 24, count 0 2006.218.08:07:29.24#ibcon#read 5, iclass 24, count 0 2006.218.08:07:29.24#ibcon#about to read 6, iclass 24, count 0 2006.218.08:07:29.24#ibcon#read 6, iclass 24, count 0 2006.218.08:07:29.24#ibcon#end of sib2, iclass 24, count 0 2006.218.08:07:29.24#ibcon#*mode == 0, iclass 24, count 0 2006.218.08:07:29.24#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.218.08:07:29.24#ibcon#[26=FRQ=05,652.99\r\n] 2006.218.08:07:29.24#ibcon#*before write, iclass 24, count 0 2006.218.08:07:29.24#ibcon#enter sib2, iclass 24, count 0 2006.218.08:07:29.24#ibcon#flushed, iclass 24, count 0 2006.218.08:07:29.24#ibcon#about to write, iclass 24, count 0 2006.218.08:07:29.24#ibcon#wrote, iclass 24, count 0 2006.218.08:07:29.24#ibcon#about to read 3, iclass 24, count 0 2006.218.08:07:29.28#ibcon#read 3, iclass 24, count 0 2006.218.08:07:29.28#ibcon#about to read 4, iclass 24, count 0 2006.218.08:07:29.28#ibcon#read 4, iclass 24, count 0 2006.218.08:07:29.28#ibcon#about to read 5, iclass 24, count 0 2006.218.08:07:29.28#ibcon#read 5, iclass 24, count 0 2006.218.08:07:29.28#ibcon#about to read 6, iclass 24, count 0 2006.218.08:07:29.28#ibcon#read 6, iclass 24, count 0 2006.218.08:07:29.28#ibcon#end of sib2, iclass 24, count 0 2006.218.08:07:29.28#ibcon#*after write, iclass 24, count 0 2006.218.08:07:29.28#ibcon#*before return 0, iclass 24, count 0 2006.218.08:07:29.28#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.218.08:07:29.28#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.218.08:07:29.28#ibcon#about to clear, iclass 24 cls_cnt 0 2006.218.08:07:29.28#ibcon#cleared, iclass 24 cls_cnt 0 2006.218.08:07:29.28$vc4f8/va=5,7 2006.218.08:07:29.28#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.218.08:07:29.28#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.218.08:07:29.28#ibcon#ireg 11 cls_cnt 2 2006.218.08:07:29.28#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.218.08:07:29.34#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.218.08:07:29.34#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.218.08:07:29.34#ibcon#enter wrdev, iclass 26, count 2 2006.218.08:07:29.34#ibcon#first serial, iclass 26, count 2 2006.218.08:07:29.34#ibcon#enter sib2, iclass 26, count 2 2006.218.08:07:29.34#ibcon#flushed, iclass 26, count 2 2006.218.08:07:29.34#ibcon#about to write, iclass 26, count 2 2006.218.08:07:29.34#ibcon#wrote, iclass 26, count 2 2006.218.08:07:29.34#ibcon#about to read 3, iclass 26, count 2 2006.218.08:07:29.36#ibcon#read 3, iclass 26, count 2 2006.218.08:07:29.36#ibcon#about to read 4, iclass 26, count 2 2006.218.08:07:29.36#ibcon#read 4, iclass 26, count 2 2006.218.08:07:29.36#ibcon#about to read 5, iclass 26, count 2 2006.218.08:07:29.36#ibcon#read 5, iclass 26, count 2 2006.218.08:07:29.36#ibcon#about to read 6, iclass 26, count 2 2006.218.08:07:29.36#ibcon#read 6, iclass 26, count 2 2006.218.08:07:29.36#ibcon#end of sib2, iclass 26, count 2 2006.218.08:07:29.36#ibcon#*mode == 0, iclass 26, count 2 2006.218.08:07:29.36#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.218.08:07:29.36#ibcon#[25=AT05-07\r\n] 2006.218.08:07:29.36#ibcon#*before write, iclass 26, count 2 2006.218.08:07:29.36#ibcon#enter sib2, iclass 26, count 2 2006.218.08:07:29.36#ibcon#flushed, iclass 26, count 2 2006.218.08:07:29.36#ibcon#about to write, iclass 26, count 2 2006.218.08:07:29.36#ibcon#wrote, iclass 26, count 2 2006.218.08:07:29.36#ibcon#about to read 3, iclass 26, count 2 2006.218.08:07:29.39#ibcon#read 3, iclass 26, count 2 2006.218.08:07:29.39#ibcon#about to read 4, iclass 26, count 2 2006.218.08:07:29.39#ibcon#read 4, iclass 26, count 2 2006.218.08:07:29.39#ibcon#about to read 5, iclass 26, count 2 2006.218.08:07:29.39#ibcon#read 5, iclass 26, count 2 2006.218.08:07:29.39#ibcon#about to read 6, iclass 26, count 2 2006.218.08:07:29.39#ibcon#read 6, iclass 26, count 2 2006.218.08:07:29.39#ibcon#end of sib2, iclass 26, count 2 2006.218.08:07:29.39#ibcon#*after write, iclass 26, count 2 2006.218.08:07:29.39#ibcon#*before return 0, iclass 26, count 2 2006.218.08:07:29.39#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.218.08:07:29.39#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.218.08:07:29.39#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.218.08:07:29.39#ibcon#ireg 7 cls_cnt 0 2006.218.08:07:29.39#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.218.08:07:29.51#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.218.08:07:29.51#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.218.08:07:29.51#ibcon#enter wrdev, iclass 26, count 0 2006.218.08:07:29.51#ibcon#first serial, iclass 26, count 0 2006.218.08:07:29.51#ibcon#enter sib2, iclass 26, count 0 2006.218.08:07:29.51#ibcon#flushed, iclass 26, count 0 2006.218.08:07:29.51#ibcon#about to write, iclass 26, count 0 2006.218.08:07:29.51#ibcon#wrote, iclass 26, count 0 2006.218.08:07:29.51#ibcon#about to read 3, iclass 26, count 0 2006.218.08:07:29.53#ibcon#read 3, iclass 26, count 0 2006.218.08:07:29.53#ibcon#about to read 4, iclass 26, count 0 2006.218.08:07:29.53#ibcon#read 4, iclass 26, count 0 2006.218.08:07:29.53#ibcon#about to read 5, iclass 26, count 0 2006.218.08:07:29.53#ibcon#read 5, iclass 26, count 0 2006.218.08:07:29.53#ibcon#about to read 6, iclass 26, count 0 2006.218.08:07:29.53#ibcon#read 6, iclass 26, count 0 2006.218.08:07:29.53#ibcon#end of sib2, iclass 26, count 0 2006.218.08:07:29.53#ibcon#*mode == 0, iclass 26, count 0 2006.218.08:07:29.53#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.218.08:07:29.53#ibcon#[25=USB\r\n] 2006.218.08:07:29.53#ibcon#*before write, iclass 26, count 0 2006.218.08:07:29.53#ibcon#enter sib2, iclass 26, count 0 2006.218.08:07:29.53#ibcon#flushed, iclass 26, count 0 2006.218.08:07:29.53#ibcon#about to write, iclass 26, count 0 2006.218.08:07:29.53#ibcon#wrote, iclass 26, count 0 2006.218.08:07:29.53#ibcon#about to read 3, iclass 26, count 0 2006.218.08:07:29.56#ibcon#read 3, iclass 26, count 0 2006.218.08:07:29.56#ibcon#about to read 4, iclass 26, count 0 2006.218.08:07:29.56#ibcon#read 4, iclass 26, count 0 2006.218.08:07:29.56#ibcon#about to read 5, iclass 26, count 0 2006.218.08:07:29.56#ibcon#read 5, iclass 26, count 0 2006.218.08:07:29.56#ibcon#about to read 6, iclass 26, count 0 2006.218.08:07:29.56#ibcon#read 6, iclass 26, count 0 2006.218.08:07:29.56#ibcon#end of sib2, iclass 26, count 0 2006.218.08:07:29.56#ibcon#*after write, iclass 26, count 0 2006.218.08:07:29.56#ibcon#*before return 0, iclass 26, count 0 2006.218.08:07:29.56#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.218.08:07:29.56#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.218.08:07:29.56#ibcon#about to clear, iclass 26 cls_cnt 0 2006.218.08:07:29.56#ibcon#cleared, iclass 26 cls_cnt 0 2006.218.08:07:29.56$vc4f8/valo=6,772.99 2006.218.08:07:29.56#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.218.08:07:29.56#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.218.08:07:29.56#ibcon#ireg 17 cls_cnt 0 2006.218.08:07:29.56#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.218.08:07:29.56#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.218.08:07:29.56#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.218.08:07:29.56#ibcon#enter wrdev, iclass 28, count 0 2006.218.08:07:29.56#ibcon#first serial, iclass 28, count 0 2006.218.08:07:29.56#ibcon#enter sib2, iclass 28, count 0 2006.218.08:07:29.56#ibcon#flushed, iclass 28, count 0 2006.218.08:07:29.56#ibcon#about to write, iclass 28, count 0 2006.218.08:07:29.56#ibcon#wrote, iclass 28, count 0 2006.218.08:07:29.56#ibcon#about to read 3, iclass 28, count 0 2006.218.08:07:29.59#ibcon#read 3, iclass 28, count 0 2006.218.08:07:29.59#ibcon#about to read 4, iclass 28, count 0 2006.218.08:07:29.59#ibcon#read 4, iclass 28, count 0 2006.218.08:07:29.59#ibcon#about to read 5, iclass 28, count 0 2006.218.08:07:29.59#ibcon#read 5, iclass 28, count 0 2006.218.08:07:29.59#ibcon#about to read 6, iclass 28, count 0 2006.218.08:07:29.59#ibcon#read 6, iclass 28, count 0 2006.218.08:07:29.59#ibcon#end of sib2, iclass 28, count 0 2006.218.08:07:29.59#ibcon#*mode == 0, iclass 28, count 0 2006.218.08:07:29.59#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.218.08:07:29.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.218.08:07:29.59#ibcon#*before write, iclass 28, count 0 2006.218.08:07:29.59#ibcon#enter sib2, iclass 28, count 0 2006.218.08:07:29.59#ibcon#flushed, iclass 28, count 0 2006.218.08:07:29.59#ibcon#about to write, iclass 28, count 0 2006.218.08:07:29.59#ibcon#wrote, iclass 28, count 0 2006.218.08:07:29.59#ibcon#about to read 3, iclass 28, count 0 2006.218.08:07:29.63#ibcon#read 3, iclass 28, count 0 2006.218.08:07:29.63#ibcon#about to read 4, iclass 28, count 0 2006.218.08:07:29.63#ibcon#read 4, iclass 28, count 0 2006.218.08:07:29.63#ibcon#about to read 5, iclass 28, count 0 2006.218.08:07:29.63#ibcon#read 5, iclass 28, count 0 2006.218.08:07:29.63#ibcon#about to read 6, iclass 28, count 0 2006.218.08:07:29.63#ibcon#read 6, iclass 28, count 0 2006.218.08:07:29.63#ibcon#end of sib2, iclass 28, count 0 2006.218.08:07:29.63#ibcon#*after write, iclass 28, count 0 2006.218.08:07:29.63#ibcon#*before return 0, iclass 28, count 0 2006.218.08:07:29.63#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.218.08:07:29.63#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.218.08:07:29.63#ibcon#about to clear, iclass 28 cls_cnt 0 2006.218.08:07:29.63#ibcon#cleared, iclass 28 cls_cnt 0 2006.218.08:07:29.63$vc4f8/va=6,6 2006.218.08:07:29.63#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.218.08:07:29.63#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.218.08:07:29.63#ibcon#ireg 11 cls_cnt 2 2006.218.08:07:29.63#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.218.08:07:29.68#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.218.08:07:29.68#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.218.08:07:29.68#ibcon#enter wrdev, iclass 30, count 2 2006.218.08:07:29.68#ibcon#first serial, iclass 30, count 2 2006.218.08:07:29.68#ibcon#enter sib2, iclass 30, count 2 2006.218.08:07:29.68#ibcon#flushed, iclass 30, count 2 2006.218.08:07:29.68#ibcon#about to write, iclass 30, count 2 2006.218.08:07:29.68#ibcon#wrote, iclass 30, count 2 2006.218.08:07:29.68#ibcon#about to read 3, iclass 30, count 2 2006.218.08:07:29.70#ibcon#read 3, iclass 30, count 2 2006.218.08:07:29.70#ibcon#about to read 4, iclass 30, count 2 2006.218.08:07:29.70#ibcon#read 4, iclass 30, count 2 2006.218.08:07:29.70#ibcon#about to read 5, iclass 30, count 2 2006.218.08:07:29.70#ibcon#read 5, iclass 30, count 2 2006.218.08:07:29.70#ibcon#about to read 6, iclass 30, count 2 2006.218.08:07:29.70#ibcon#read 6, iclass 30, count 2 2006.218.08:07:29.70#ibcon#end of sib2, iclass 30, count 2 2006.218.08:07:29.70#ibcon#*mode == 0, iclass 30, count 2 2006.218.08:07:29.70#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.218.08:07:29.70#ibcon#[25=AT06-06\r\n] 2006.218.08:07:29.70#ibcon#*before write, iclass 30, count 2 2006.218.08:07:29.70#ibcon#enter sib2, iclass 30, count 2 2006.218.08:07:29.70#ibcon#flushed, iclass 30, count 2 2006.218.08:07:29.70#ibcon#about to write, iclass 30, count 2 2006.218.08:07:29.70#ibcon#wrote, iclass 30, count 2 2006.218.08:07:29.70#ibcon#about to read 3, iclass 30, count 2 2006.218.08:07:29.73#ibcon#read 3, iclass 30, count 2 2006.218.08:07:29.73#ibcon#about to read 4, iclass 30, count 2 2006.218.08:07:29.73#ibcon#read 4, iclass 30, count 2 2006.218.08:07:29.73#ibcon#about to read 5, iclass 30, count 2 2006.218.08:07:29.73#ibcon#read 5, iclass 30, count 2 2006.218.08:07:29.73#ibcon#about to read 6, iclass 30, count 2 2006.218.08:07:29.73#ibcon#read 6, iclass 30, count 2 2006.218.08:07:29.73#ibcon#end of sib2, iclass 30, count 2 2006.218.08:07:29.73#ibcon#*after write, iclass 30, count 2 2006.218.08:07:29.73#ibcon#*before return 0, iclass 30, count 2 2006.218.08:07:29.73#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.218.08:07:29.73#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.218.08:07:29.73#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.218.08:07:29.73#ibcon#ireg 7 cls_cnt 0 2006.218.08:07:29.73#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.218.08:07:29.85#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.218.08:07:29.85#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.218.08:07:29.85#ibcon#enter wrdev, iclass 30, count 0 2006.218.08:07:29.85#ibcon#first serial, iclass 30, count 0 2006.218.08:07:29.85#ibcon#enter sib2, iclass 30, count 0 2006.218.08:07:29.85#ibcon#flushed, iclass 30, count 0 2006.218.08:07:29.85#ibcon#about to write, iclass 30, count 0 2006.218.08:07:29.85#ibcon#wrote, iclass 30, count 0 2006.218.08:07:29.85#ibcon#about to read 3, iclass 30, count 0 2006.218.08:07:29.87#ibcon#read 3, iclass 30, count 0 2006.218.08:07:29.87#ibcon#about to read 4, iclass 30, count 0 2006.218.08:07:29.87#ibcon#read 4, iclass 30, count 0 2006.218.08:07:29.87#ibcon#about to read 5, iclass 30, count 0 2006.218.08:07:29.87#ibcon#read 5, iclass 30, count 0 2006.218.08:07:29.87#ibcon#about to read 6, iclass 30, count 0 2006.218.08:07:29.87#ibcon#read 6, iclass 30, count 0 2006.218.08:07:29.87#ibcon#end of sib2, iclass 30, count 0 2006.218.08:07:29.87#ibcon#*mode == 0, iclass 30, count 0 2006.218.08:07:29.87#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.218.08:07:29.87#ibcon#[25=USB\r\n] 2006.218.08:07:29.87#ibcon#*before write, iclass 30, count 0 2006.218.08:07:29.87#ibcon#enter sib2, iclass 30, count 0 2006.218.08:07:29.87#ibcon#flushed, iclass 30, count 0 2006.218.08:07:29.87#ibcon#about to write, iclass 30, count 0 2006.218.08:07:29.87#ibcon#wrote, iclass 30, count 0 2006.218.08:07:29.87#ibcon#about to read 3, iclass 30, count 0 2006.218.08:07:29.90#ibcon#read 3, iclass 30, count 0 2006.218.08:07:29.90#ibcon#about to read 4, iclass 30, count 0 2006.218.08:07:29.90#ibcon#read 4, iclass 30, count 0 2006.218.08:07:29.90#ibcon#about to read 5, iclass 30, count 0 2006.218.08:07:29.90#ibcon#read 5, iclass 30, count 0 2006.218.08:07:29.90#ibcon#about to read 6, iclass 30, count 0 2006.218.08:07:29.90#ibcon#read 6, iclass 30, count 0 2006.218.08:07:29.90#ibcon#end of sib2, iclass 30, count 0 2006.218.08:07:29.90#ibcon#*after write, iclass 30, count 0 2006.218.08:07:29.90#ibcon#*before return 0, iclass 30, count 0 2006.218.08:07:29.90#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.218.08:07:29.90#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.218.08:07:29.90#ibcon#about to clear, iclass 30 cls_cnt 0 2006.218.08:07:29.90#ibcon#cleared, iclass 30 cls_cnt 0 2006.218.08:07:29.90$vc4f8/valo=7,832.99 2006.218.08:07:29.90#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.218.08:07:29.90#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.218.08:07:29.90#ibcon#ireg 17 cls_cnt 0 2006.218.08:07:29.90#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.218.08:07:29.90#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.218.08:07:29.90#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.218.08:07:29.90#ibcon#enter wrdev, iclass 32, count 0 2006.218.08:07:29.90#ibcon#first serial, iclass 32, count 0 2006.218.08:07:29.90#ibcon#enter sib2, iclass 32, count 0 2006.218.08:07:29.90#ibcon#flushed, iclass 32, count 0 2006.218.08:07:29.90#ibcon#about to write, iclass 32, count 0 2006.218.08:07:29.90#ibcon#wrote, iclass 32, count 0 2006.218.08:07:29.90#ibcon#about to read 3, iclass 32, count 0 2006.218.08:07:29.92#ibcon#read 3, iclass 32, count 0 2006.218.08:07:29.92#ibcon#about to read 4, iclass 32, count 0 2006.218.08:07:29.92#ibcon#read 4, iclass 32, count 0 2006.218.08:07:29.92#ibcon#about to read 5, iclass 32, count 0 2006.218.08:07:29.92#ibcon#read 5, iclass 32, count 0 2006.218.08:07:29.92#ibcon#about to read 6, iclass 32, count 0 2006.218.08:07:29.92#ibcon#read 6, iclass 32, count 0 2006.218.08:07:29.92#ibcon#end of sib2, iclass 32, count 0 2006.218.08:07:29.92#ibcon#*mode == 0, iclass 32, count 0 2006.218.08:07:29.92#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.218.08:07:29.92#ibcon#[26=FRQ=07,832.99\r\n] 2006.218.08:07:29.92#ibcon#*before write, iclass 32, count 0 2006.218.08:07:29.92#ibcon#enter sib2, iclass 32, count 0 2006.218.08:07:29.92#ibcon#flushed, iclass 32, count 0 2006.218.08:07:29.92#ibcon#about to write, iclass 32, count 0 2006.218.08:07:29.92#ibcon#wrote, iclass 32, count 0 2006.218.08:07:29.92#ibcon#about to read 3, iclass 32, count 0 2006.218.08:07:29.96#ibcon#read 3, iclass 32, count 0 2006.218.08:07:29.96#ibcon#about to read 4, iclass 32, count 0 2006.218.08:07:29.96#ibcon#read 4, iclass 32, count 0 2006.218.08:07:29.96#ibcon#about to read 5, iclass 32, count 0 2006.218.08:07:29.96#ibcon#read 5, iclass 32, count 0 2006.218.08:07:29.96#ibcon#about to read 6, iclass 32, count 0 2006.218.08:07:29.96#ibcon#read 6, iclass 32, count 0 2006.218.08:07:29.96#ibcon#end of sib2, iclass 32, count 0 2006.218.08:07:29.96#ibcon#*after write, iclass 32, count 0 2006.218.08:07:29.96#ibcon#*before return 0, iclass 32, count 0 2006.218.08:07:29.96#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.218.08:07:29.96#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.218.08:07:29.96#ibcon#about to clear, iclass 32 cls_cnt 0 2006.218.08:07:29.96#ibcon#cleared, iclass 32 cls_cnt 0 2006.218.08:07:29.96$vc4f8/va=7,6 2006.218.08:07:29.96#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.218.08:07:29.96#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.218.08:07:29.96#ibcon#ireg 11 cls_cnt 2 2006.218.08:07:29.96#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.218.08:07:30.02#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.218.08:07:30.02#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.218.08:07:30.02#ibcon#enter wrdev, iclass 34, count 2 2006.218.08:07:30.02#ibcon#first serial, iclass 34, count 2 2006.218.08:07:30.02#ibcon#enter sib2, iclass 34, count 2 2006.218.08:07:30.02#ibcon#flushed, iclass 34, count 2 2006.218.08:07:30.02#ibcon#about to write, iclass 34, count 2 2006.218.08:07:30.02#ibcon#wrote, iclass 34, count 2 2006.218.08:07:30.02#ibcon#about to read 3, iclass 34, count 2 2006.218.08:07:30.04#ibcon#read 3, iclass 34, count 2 2006.218.08:07:30.04#ibcon#about to read 4, iclass 34, count 2 2006.218.08:07:30.04#ibcon#read 4, iclass 34, count 2 2006.218.08:07:30.04#ibcon#about to read 5, iclass 34, count 2 2006.218.08:07:30.04#ibcon#read 5, iclass 34, count 2 2006.218.08:07:30.04#ibcon#about to read 6, iclass 34, count 2 2006.218.08:07:30.04#ibcon#read 6, iclass 34, count 2 2006.218.08:07:30.04#ibcon#end of sib2, iclass 34, count 2 2006.218.08:07:30.04#ibcon#*mode == 0, iclass 34, count 2 2006.218.08:07:30.04#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.218.08:07:30.04#ibcon#[25=AT07-06\r\n] 2006.218.08:07:30.04#ibcon#*before write, iclass 34, count 2 2006.218.08:07:30.04#ibcon#enter sib2, iclass 34, count 2 2006.218.08:07:30.04#ibcon#flushed, iclass 34, count 2 2006.218.08:07:30.04#ibcon#about to write, iclass 34, count 2 2006.218.08:07:30.04#ibcon#wrote, iclass 34, count 2 2006.218.08:07:30.04#ibcon#about to read 3, iclass 34, count 2 2006.218.08:07:30.07#ibcon#read 3, iclass 34, count 2 2006.218.08:07:30.07#ibcon#about to read 4, iclass 34, count 2 2006.218.08:07:30.07#ibcon#read 4, iclass 34, count 2 2006.218.08:07:30.07#ibcon#about to read 5, iclass 34, count 2 2006.218.08:07:30.07#ibcon#read 5, iclass 34, count 2 2006.218.08:07:30.07#ibcon#about to read 6, iclass 34, count 2 2006.218.08:07:30.07#ibcon#read 6, iclass 34, count 2 2006.218.08:07:30.07#ibcon#end of sib2, iclass 34, count 2 2006.218.08:07:30.07#ibcon#*after write, iclass 34, count 2 2006.218.08:07:30.07#ibcon#*before return 0, iclass 34, count 2 2006.218.08:07:30.07#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.218.08:07:30.07#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.218.08:07:30.07#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.218.08:07:30.07#ibcon#ireg 7 cls_cnt 0 2006.218.08:07:30.07#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.218.08:07:30.19#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.218.08:07:30.19#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.218.08:07:30.19#ibcon#enter wrdev, iclass 34, count 0 2006.218.08:07:30.19#ibcon#first serial, iclass 34, count 0 2006.218.08:07:30.19#ibcon#enter sib2, iclass 34, count 0 2006.218.08:07:30.19#ibcon#flushed, iclass 34, count 0 2006.218.08:07:30.19#ibcon#about to write, iclass 34, count 0 2006.218.08:07:30.19#ibcon#wrote, iclass 34, count 0 2006.218.08:07:30.19#ibcon#about to read 3, iclass 34, count 0 2006.218.08:07:30.21#ibcon#read 3, iclass 34, count 0 2006.218.08:07:30.21#ibcon#about to read 4, iclass 34, count 0 2006.218.08:07:30.21#ibcon#read 4, iclass 34, count 0 2006.218.08:07:30.21#ibcon#about to read 5, iclass 34, count 0 2006.218.08:07:30.21#ibcon#read 5, iclass 34, count 0 2006.218.08:07:30.21#ibcon#about to read 6, iclass 34, count 0 2006.218.08:07:30.21#ibcon#read 6, iclass 34, count 0 2006.218.08:07:30.21#ibcon#end of sib2, iclass 34, count 0 2006.218.08:07:30.21#ibcon#*mode == 0, iclass 34, count 0 2006.218.08:07:30.21#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.218.08:07:30.21#ibcon#[25=USB\r\n] 2006.218.08:07:30.21#ibcon#*before write, iclass 34, count 0 2006.218.08:07:30.21#ibcon#enter sib2, iclass 34, count 0 2006.218.08:07:30.21#ibcon#flushed, iclass 34, count 0 2006.218.08:07:30.21#ibcon#about to write, iclass 34, count 0 2006.218.08:07:30.21#ibcon#wrote, iclass 34, count 0 2006.218.08:07:30.21#ibcon#about to read 3, iclass 34, count 0 2006.218.08:07:30.24#ibcon#read 3, iclass 34, count 0 2006.218.08:07:30.24#ibcon#about to read 4, iclass 34, count 0 2006.218.08:07:30.24#ibcon#read 4, iclass 34, count 0 2006.218.08:07:30.24#ibcon#about to read 5, iclass 34, count 0 2006.218.08:07:30.24#ibcon#read 5, iclass 34, count 0 2006.218.08:07:30.24#ibcon#about to read 6, iclass 34, count 0 2006.218.08:07:30.24#ibcon#read 6, iclass 34, count 0 2006.218.08:07:30.24#ibcon#end of sib2, iclass 34, count 0 2006.218.08:07:30.24#ibcon#*after write, iclass 34, count 0 2006.218.08:07:30.24#ibcon#*before return 0, iclass 34, count 0 2006.218.08:07:30.24#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.218.08:07:30.24#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.218.08:07:30.24#ibcon#about to clear, iclass 34 cls_cnt 0 2006.218.08:07:30.24#ibcon#cleared, iclass 34 cls_cnt 0 2006.218.08:07:30.24$vc4f8/valo=8,852.99 2006.218.08:07:30.24#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.218.08:07:30.24#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.218.08:07:30.24#ibcon#ireg 17 cls_cnt 0 2006.218.08:07:30.24#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.218.08:07:30.24#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.218.08:07:30.24#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.218.08:07:30.24#ibcon#enter wrdev, iclass 36, count 0 2006.218.08:07:30.24#ibcon#first serial, iclass 36, count 0 2006.218.08:07:30.24#ibcon#enter sib2, iclass 36, count 0 2006.218.08:07:30.24#ibcon#flushed, iclass 36, count 0 2006.218.08:07:30.24#ibcon#about to write, iclass 36, count 0 2006.218.08:07:30.24#ibcon#wrote, iclass 36, count 0 2006.218.08:07:30.24#ibcon#about to read 3, iclass 36, count 0 2006.218.08:07:30.26#ibcon#read 3, iclass 36, count 0 2006.218.08:07:30.26#ibcon#about to read 4, iclass 36, count 0 2006.218.08:07:30.26#ibcon#read 4, iclass 36, count 0 2006.218.08:07:30.26#ibcon#about to read 5, iclass 36, count 0 2006.218.08:07:30.26#ibcon#read 5, iclass 36, count 0 2006.218.08:07:30.26#ibcon#about to read 6, iclass 36, count 0 2006.218.08:07:30.26#ibcon#read 6, iclass 36, count 0 2006.218.08:07:30.26#ibcon#end of sib2, iclass 36, count 0 2006.218.08:07:30.26#ibcon#*mode == 0, iclass 36, count 0 2006.218.08:07:30.26#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.218.08:07:30.26#ibcon#[26=FRQ=08,852.99\r\n] 2006.218.08:07:30.26#ibcon#*before write, iclass 36, count 0 2006.218.08:07:30.26#ibcon#enter sib2, iclass 36, count 0 2006.218.08:07:30.26#ibcon#flushed, iclass 36, count 0 2006.218.08:07:30.26#ibcon#about to write, iclass 36, count 0 2006.218.08:07:30.26#ibcon#wrote, iclass 36, count 0 2006.218.08:07:30.26#ibcon#about to read 3, iclass 36, count 0 2006.218.08:07:30.30#ibcon#read 3, iclass 36, count 0 2006.218.08:07:30.30#ibcon#about to read 4, iclass 36, count 0 2006.218.08:07:30.30#ibcon#read 4, iclass 36, count 0 2006.218.08:07:30.30#ibcon#about to read 5, iclass 36, count 0 2006.218.08:07:30.30#ibcon#read 5, iclass 36, count 0 2006.218.08:07:30.30#ibcon#about to read 6, iclass 36, count 0 2006.218.08:07:30.30#ibcon#read 6, iclass 36, count 0 2006.218.08:07:30.30#ibcon#end of sib2, iclass 36, count 0 2006.218.08:07:30.30#ibcon#*after write, iclass 36, count 0 2006.218.08:07:30.30#ibcon#*before return 0, iclass 36, count 0 2006.218.08:07:30.30#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.218.08:07:30.30#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.218.08:07:30.30#ibcon#about to clear, iclass 36 cls_cnt 0 2006.218.08:07:30.30#ibcon#cleared, iclass 36 cls_cnt 0 2006.218.08:07:30.30$vc4f8/va=8,7 2006.218.08:07:30.30#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.218.08:07:30.30#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.218.08:07:30.30#ibcon#ireg 11 cls_cnt 2 2006.218.08:07:30.30#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.218.08:07:30.36#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.218.08:07:30.36#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.218.08:07:30.36#ibcon#enter wrdev, iclass 38, count 2 2006.218.08:07:30.36#ibcon#first serial, iclass 38, count 2 2006.218.08:07:30.36#ibcon#enter sib2, iclass 38, count 2 2006.218.08:07:30.36#ibcon#flushed, iclass 38, count 2 2006.218.08:07:30.36#ibcon#about to write, iclass 38, count 2 2006.218.08:07:30.36#ibcon#wrote, iclass 38, count 2 2006.218.08:07:30.36#ibcon#about to read 3, iclass 38, count 2 2006.218.08:07:30.38#ibcon#read 3, iclass 38, count 2 2006.218.08:07:30.38#ibcon#about to read 4, iclass 38, count 2 2006.218.08:07:30.38#ibcon#read 4, iclass 38, count 2 2006.218.08:07:30.38#ibcon#about to read 5, iclass 38, count 2 2006.218.08:07:30.38#ibcon#read 5, iclass 38, count 2 2006.218.08:07:30.38#ibcon#about to read 6, iclass 38, count 2 2006.218.08:07:30.38#ibcon#read 6, iclass 38, count 2 2006.218.08:07:30.38#ibcon#end of sib2, iclass 38, count 2 2006.218.08:07:30.38#ibcon#*mode == 0, iclass 38, count 2 2006.218.08:07:30.38#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.218.08:07:30.38#ibcon#[25=AT08-07\r\n] 2006.218.08:07:30.38#ibcon#*before write, iclass 38, count 2 2006.218.08:07:30.38#ibcon#enter sib2, iclass 38, count 2 2006.218.08:07:30.38#ibcon#flushed, iclass 38, count 2 2006.218.08:07:30.39#ibcon#about to write, iclass 38, count 2 2006.218.08:07:30.39#ibcon#wrote, iclass 38, count 2 2006.218.08:07:30.39#ibcon#about to read 3, iclass 38, count 2 2006.218.08:07:30.42#ibcon#read 3, iclass 38, count 2 2006.218.08:07:30.42#ibcon#about to read 4, iclass 38, count 2 2006.218.08:07:30.42#ibcon#read 4, iclass 38, count 2 2006.218.08:07:30.42#ibcon#about to read 5, iclass 38, count 2 2006.218.08:07:30.42#ibcon#read 5, iclass 38, count 2 2006.218.08:07:30.42#ibcon#about to read 6, iclass 38, count 2 2006.218.08:07:30.42#ibcon#read 6, iclass 38, count 2 2006.218.08:07:30.42#ibcon#end of sib2, iclass 38, count 2 2006.218.08:07:30.42#ibcon#*after write, iclass 38, count 2 2006.218.08:07:30.42#ibcon#*before return 0, iclass 38, count 2 2006.218.08:07:30.42#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.218.08:07:30.42#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.218.08:07:30.42#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.218.08:07:30.42#ibcon#ireg 7 cls_cnt 0 2006.218.08:07:30.42#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.218.08:07:30.54#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.218.08:07:30.54#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.218.08:07:30.54#ibcon#enter wrdev, iclass 38, count 0 2006.218.08:07:30.54#ibcon#first serial, iclass 38, count 0 2006.218.08:07:30.54#ibcon#enter sib2, iclass 38, count 0 2006.218.08:07:30.54#ibcon#flushed, iclass 38, count 0 2006.218.08:07:30.54#ibcon#about to write, iclass 38, count 0 2006.218.08:07:30.54#ibcon#wrote, iclass 38, count 0 2006.218.08:07:30.54#ibcon#about to read 3, iclass 38, count 0 2006.218.08:07:30.56#ibcon#read 3, iclass 38, count 0 2006.218.08:07:30.56#ibcon#about to read 4, iclass 38, count 0 2006.218.08:07:30.56#ibcon#read 4, iclass 38, count 0 2006.218.08:07:30.56#ibcon#about to read 5, iclass 38, count 0 2006.218.08:07:30.56#ibcon#read 5, iclass 38, count 0 2006.218.08:07:30.56#ibcon#about to read 6, iclass 38, count 0 2006.218.08:07:30.56#ibcon#read 6, iclass 38, count 0 2006.218.08:07:30.56#ibcon#end of sib2, iclass 38, count 0 2006.218.08:07:30.56#ibcon#*mode == 0, iclass 38, count 0 2006.218.08:07:30.56#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.218.08:07:30.56#ibcon#[25=USB\r\n] 2006.218.08:07:30.56#ibcon#*before write, iclass 38, count 0 2006.218.08:07:30.56#ibcon#enter sib2, iclass 38, count 0 2006.218.08:07:30.56#ibcon#flushed, iclass 38, count 0 2006.218.08:07:30.56#ibcon#about to write, iclass 38, count 0 2006.218.08:07:30.56#ibcon#wrote, iclass 38, count 0 2006.218.08:07:30.56#ibcon#about to read 3, iclass 38, count 0 2006.218.08:07:30.59#ibcon#read 3, iclass 38, count 0 2006.218.08:07:30.59#ibcon#about to read 4, iclass 38, count 0 2006.218.08:07:30.59#ibcon#read 4, iclass 38, count 0 2006.218.08:07:30.59#ibcon#about to read 5, iclass 38, count 0 2006.218.08:07:30.59#ibcon#read 5, iclass 38, count 0 2006.218.08:07:30.59#ibcon#about to read 6, iclass 38, count 0 2006.218.08:07:30.59#ibcon#read 6, iclass 38, count 0 2006.218.08:07:30.59#ibcon#end of sib2, iclass 38, count 0 2006.218.08:07:30.59#ibcon#*after write, iclass 38, count 0 2006.218.08:07:30.59#ibcon#*before return 0, iclass 38, count 0 2006.218.08:07:30.59#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.218.08:07:30.59#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.218.08:07:30.59#ibcon#about to clear, iclass 38 cls_cnt 0 2006.218.08:07:30.59#ibcon#cleared, iclass 38 cls_cnt 0 2006.218.08:07:30.59$vc4f8/vblo=1,632.99 2006.218.08:07:30.59#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.218.08:07:30.59#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.218.08:07:30.59#ibcon#ireg 17 cls_cnt 0 2006.218.08:07:30.59#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.218.08:07:30.59#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.218.08:07:30.59#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.218.08:07:30.59#ibcon#enter wrdev, iclass 40, count 0 2006.218.08:07:30.59#ibcon#first serial, iclass 40, count 0 2006.218.08:07:30.59#ibcon#enter sib2, iclass 40, count 0 2006.218.08:07:30.59#ibcon#flushed, iclass 40, count 0 2006.218.08:07:30.59#ibcon#about to write, iclass 40, count 0 2006.218.08:07:30.59#ibcon#wrote, iclass 40, count 0 2006.218.08:07:30.59#ibcon#about to read 3, iclass 40, count 0 2006.218.08:07:30.61#ibcon#read 3, iclass 40, count 0 2006.218.08:07:30.61#ibcon#about to read 4, iclass 40, count 0 2006.218.08:07:30.61#ibcon#read 4, iclass 40, count 0 2006.218.08:07:30.61#ibcon#about to read 5, iclass 40, count 0 2006.218.08:07:30.61#ibcon#read 5, iclass 40, count 0 2006.218.08:07:30.61#ibcon#about to read 6, iclass 40, count 0 2006.218.08:07:30.61#ibcon#read 6, iclass 40, count 0 2006.218.08:07:30.61#ibcon#end of sib2, iclass 40, count 0 2006.218.08:07:30.61#ibcon#*mode == 0, iclass 40, count 0 2006.218.08:07:30.61#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.218.08:07:30.61#ibcon#[28=FRQ=01,632.99\r\n] 2006.218.08:07:30.61#ibcon#*before write, iclass 40, count 0 2006.218.08:07:30.61#ibcon#enter sib2, iclass 40, count 0 2006.218.08:07:30.61#ibcon#flushed, iclass 40, count 0 2006.218.08:07:30.61#ibcon#about to write, iclass 40, count 0 2006.218.08:07:30.61#ibcon#wrote, iclass 40, count 0 2006.218.08:07:30.61#ibcon#about to read 3, iclass 40, count 0 2006.218.08:07:30.65#ibcon#read 3, iclass 40, count 0 2006.218.08:07:30.65#ibcon#about to read 4, iclass 40, count 0 2006.218.08:07:30.65#ibcon#read 4, iclass 40, count 0 2006.218.08:07:30.65#ibcon#about to read 5, iclass 40, count 0 2006.218.08:07:30.65#ibcon#read 5, iclass 40, count 0 2006.218.08:07:30.65#ibcon#about to read 6, iclass 40, count 0 2006.218.08:07:30.65#ibcon#read 6, iclass 40, count 0 2006.218.08:07:30.65#ibcon#end of sib2, iclass 40, count 0 2006.218.08:07:30.65#ibcon#*after write, iclass 40, count 0 2006.218.08:07:30.65#ibcon#*before return 0, iclass 40, count 0 2006.218.08:07:30.65#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.218.08:07:30.65#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.218.08:07:30.65#ibcon#about to clear, iclass 40 cls_cnt 0 2006.218.08:07:30.65#ibcon#cleared, iclass 40 cls_cnt 0 2006.218.08:07:30.65$vc4f8/vb=1,4 2006.218.08:07:30.65#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.218.08:07:30.65#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.218.08:07:30.65#ibcon#ireg 11 cls_cnt 2 2006.218.08:07:30.65#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.218.08:07:30.65#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.218.08:07:30.65#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.218.08:07:30.65#ibcon#enter wrdev, iclass 4, count 2 2006.218.08:07:30.65#ibcon#first serial, iclass 4, count 2 2006.218.08:07:30.65#ibcon#enter sib2, iclass 4, count 2 2006.218.08:07:30.65#ibcon#flushed, iclass 4, count 2 2006.218.08:07:30.65#ibcon#about to write, iclass 4, count 2 2006.218.08:07:30.65#ibcon#wrote, iclass 4, count 2 2006.218.08:07:30.65#ibcon#about to read 3, iclass 4, count 2 2006.218.08:07:30.67#ibcon#read 3, iclass 4, count 2 2006.218.08:07:30.67#ibcon#about to read 4, iclass 4, count 2 2006.218.08:07:30.67#ibcon#read 4, iclass 4, count 2 2006.218.08:07:30.67#ibcon#about to read 5, iclass 4, count 2 2006.218.08:07:30.67#ibcon#read 5, iclass 4, count 2 2006.218.08:07:30.67#ibcon#about to read 6, iclass 4, count 2 2006.218.08:07:30.67#ibcon#read 6, iclass 4, count 2 2006.218.08:07:30.67#ibcon#end of sib2, iclass 4, count 2 2006.218.08:07:30.67#ibcon#*mode == 0, iclass 4, count 2 2006.218.08:07:30.67#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.218.08:07:30.67#ibcon#[27=AT01-04\r\n] 2006.218.08:07:30.67#ibcon#*before write, iclass 4, count 2 2006.218.08:07:30.67#ibcon#enter sib2, iclass 4, count 2 2006.218.08:07:30.67#ibcon#flushed, iclass 4, count 2 2006.218.08:07:30.67#ibcon#about to write, iclass 4, count 2 2006.218.08:07:30.67#ibcon#wrote, iclass 4, count 2 2006.218.08:07:30.67#ibcon#about to read 3, iclass 4, count 2 2006.218.08:07:30.70#ibcon#read 3, iclass 4, count 2 2006.218.08:07:30.70#ibcon#about to read 4, iclass 4, count 2 2006.218.08:07:30.70#ibcon#read 4, iclass 4, count 2 2006.218.08:07:30.70#ibcon#about to read 5, iclass 4, count 2 2006.218.08:07:30.70#ibcon#read 5, iclass 4, count 2 2006.218.08:07:30.70#ibcon#about to read 6, iclass 4, count 2 2006.218.08:07:30.70#ibcon#read 6, iclass 4, count 2 2006.218.08:07:30.70#ibcon#end of sib2, iclass 4, count 2 2006.218.08:07:30.70#ibcon#*after write, iclass 4, count 2 2006.218.08:07:30.70#ibcon#*before return 0, iclass 4, count 2 2006.218.08:07:30.70#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.218.08:07:30.70#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.218.08:07:30.70#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.218.08:07:30.70#ibcon#ireg 7 cls_cnt 0 2006.218.08:07:30.70#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.218.08:07:30.82#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.218.08:07:30.82#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.218.08:07:30.82#ibcon#enter wrdev, iclass 4, count 0 2006.218.08:07:30.82#ibcon#first serial, iclass 4, count 0 2006.218.08:07:30.82#ibcon#enter sib2, iclass 4, count 0 2006.218.08:07:30.82#ibcon#flushed, iclass 4, count 0 2006.218.08:07:30.82#ibcon#about to write, iclass 4, count 0 2006.218.08:07:30.82#ibcon#wrote, iclass 4, count 0 2006.218.08:07:30.82#ibcon#about to read 3, iclass 4, count 0 2006.218.08:07:30.84#ibcon#read 3, iclass 4, count 0 2006.218.08:07:30.84#ibcon#about to read 4, iclass 4, count 0 2006.218.08:07:30.84#ibcon#read 4, iclass 4, count 0 2006.218.08:07:30.84#ibcon#about to read 5, iclass 4, count 0 2006.218.08:07:30.84#ibcon#read 5, iclass 4, count 0 2006.218.08:07:30.84#ibcon#about to read 6, iclass 4, count 0 2006.218.08:07:30.84#ibcon#read 6, iclass 4, count 0 2006.218.08:07:30.84#ibcon#end of sib2, iclass 4, count 0 2006.218.08:07:30.84#ibcon#*mode == 0, iclass 4, count 0 2006.218.08:07:30.84#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.218.08:07:30.84#ibcon#[27=USB\r\n] 2006.218.08:07:30.84#ibcon#*before write, iclass 4, count 0 2006.218.08:07:30.84#ibcon#enter sib2, iclass 4, count 0 2006.218.08:07:30.84#ibcon#flushed, iclass 4, count 0 2006.218.08:07:30.84#ibcon#about to write, iclass 4, count 0 2006.218.08:07:30.84#ibcon#wrote, iclass 4, count 0 2006.218.08:07:30.84#ibcon#about to read 3, iclass 4, count 0 2006.218.08:07:30.87#ibcon#read 3, iclass 4, count 0 2006.218.08:07:30.87#ibcon#about to read 4, iclass 4, count 0 2006.218.08:07:30.87#ibcon#read 4, iclass 4, count 0 2006.218.08:07:30.87#ibcon#about to read 5, iclass 4, count 0 2006.218.08:07:30.87#ibcon#read 5, iclass 4, count 0 2006.218.08:07:30.87#ibcon#about to read 6, iclass 4, count 0 2006.218.08:07:30.87#ibcon#read 6, iclass 4, count 0 2006.218.08:07:30.87#ibcon#end of sib2, iclass 4, count 0 2006.218.08:07:30.87#ibcon#*after write, iclass 4, count 0 2006.218.08:07:30.87#ibcon#*before return 0, iclass 4, count 0 2006.218.08:07:30.87#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.218.08:07:30.87#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.218.08:07:30.87#ibcon#about to clear, iclass 4 cls_cnt 0 2006.218.08:07:30.87#ibcon#cleared, iclass 4 cls_cnt 0 2006.218.08:07:30.87$vc4f8/vblo=2,640.99 2006.218.08:07:30.87#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.218.08:07:30.87#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.218.08:07:30.87#ibcon#ireg 17 cls_cnt 0 2006.218.08:07:30.87#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.218.08:07:30.87#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.218.08:07:30.87#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.218.08:07:30.87#ibcon#enter wrdev, iclass 6, count 0 2006.218.08:07:30.87#ibcon#first serial, iclass 6, count 0 2006.218.08:07:30.87#ibcon#enter sib2, iclass 6, count 0 2006.218.08:07:30.87#ibcon#flushed, iclass 6, count 0 2006.218.08:07:30.87#ibcon#about to write, iclass 6, count 0 2006.218.08:07:30.87#ibcon#wrote, iclass 6, count 0 2006.218.08:07:30.87#ibcon#about to read 3, iclass 6, count 0 2006.218.08:07:30.89#ibcon#read 3, iclass 6, count 0 2006.218.08:07:30.89#ibcon#about to read 4, iclass 6, count 0 2006.218.08:07:30.89#ibcon#read 4, iclass 6, count 0 2006.218.08:07:30.89#ibcon#about to read 5, iclass 6, count 0 2006.218.08:07:30.89#ibcon#read 5, iclass 6, count 0 2006.218.08:07:30.89#ibcon#about to read 6, iclass 6, count 0 2006.218.08:07:30.89#ibcon#read 6, iclass 6, count 0 2006.218.08:07:30.89#ibcon#end of sib2, iclass 6, count 0 2006.218.08:07:30.89#ibcon#*mode == 0, iclass 6, count 0 2006.218.08:07:30.89#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.218.08:07:30.89#ibcon#[28=FRQ=02,640.99\r\n] 2006.218.08:07:30.89#ibcon#*before write, iclass 6, count 0 2006.218.08:07:30.89#ibcon#enter sib2, iclass 6, count 0 2006.218.08:07:30.89#ibcon#flushed, iclass 6, count 0 2006.218.08:07:30.89#ibcon#about to write, iclass 6, count 0 2006.218.08:07:30.89#ibcon#wrote, iclass 6, count 0 2006.218.08:07:30.89#ibcon#about to read 3, iclass 6, count 0 2006.218.08:07:30.93#ibcon#read 3, iclass 6, count 0 2006.218.08:07:30.93#ibcon#about to read 4, iclass 6, count 0 2006.218.08:07:30.93#ibcon#read 4, iclass 6, count 0 2006.218.08:07:30.93#ibcon#about to read 5, iclass 6, count 0 2006.218.08:07:30.93#ibcon#read 5, iclass 6, count 0 2006.218.08:07:30.93#ibcon#about to read 6, iclass 6, count 0 2006.218.08:07:30.93#ibcon#read 6, iclass 6, count 0 2006.218.08:07:30.93#ibcon#end of sib2, iclass 6, count 0 2006.218.08:07:30.93#ibcon#*after write, iclass 6, count 0 2006.218.08:07:30.93#ibcon#*before return 0, iclass 6, count 0 2006.218.08:07:30.93#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.218.08:07:30.93#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.218.08:07:30.93#ibcon#about to clear, iclass 6 cls_cnt 0 2006.218.08:07:30.93#ibcon#cleared, iclass 6 cls_cnt 0 2006.218.08:07:30.93$vc4f8/vb=2,4 2006.218.08:07:30.93#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.218.08:07:30.93#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.218.08:07:30.93#ibcon#ireg 11 cls_cnt 2 2006.218.08:07:30.93#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.218.08:07:30.99#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.218.08:07:30.99#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.218.08:07:30.99#ibcon#enter wrdev, iclass 10, count 2 2006.218.08:07:30.99#ibcon#first serial, iclass 10, count 2 2006.218.08:07:30.99#ibcon#enter sib2, iclass 10, count 2 2006.218.08:07:30.99#ibcon#flushed, iclass 10, count 2 2006.218.08:07:30.99#ibcon#about to write, iclass 10, count 2 2006.218.08:07:30.99#ibcon#wrote, iclass 10, count 2 2006.218.08:07:30.99#ibcon#about to read 3, iclass 10, count 2 2006.218.08:07:31.01#ibcon#read 3, iclass 10, count 2 2006.218.08:07:31.01#ibcon#about to read 4, iclass 10, count 2 2006.218.08:07:31.01#ibcon#read 4, iclass 10, count 2 2006.218.08:07:31.01#ibcon#about to read 5, iclass 10, count 2 2006.218.08:07:31.01#ibcon#read 5, iclass 10, count 2 2006.218.08:07:31.01#ibcon#about to read 6, iclass 10, count 2 2006.218.08:07:31.01#ibcon#read 6, iclass 10, count 2 2006.218.08:07:31.01#ibcon#end of sib2, iclass 10, count 2 2006.218.08:07:31.01#ibcon#*mode == 0, iclass 10, count 2 2006.218.08:07:31.01#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.218.08:07:31.01#ibcon#[27=AT02-04\r\n] 2006.218.08:07:31.01#ibcon#*before write, iclass 10, count 2 2006.218.08:07:31.01#ibcon#enter sib2, iclass 10, count 2 2006.218.08:07:31.01#ibcon#flushed, iclass 10, count 2 2006.218.08:07:31.01#ibcon#about to write, iclass 10, count 2 2006.218.08:07:31.01#ibcon#wrote, iclass 10, count 2 2006.218.08:07:31.01#ibcon#about to read 3, iclass 10, count 2 2006.218.08:07:31.04#ibcon#read 3, iclass 10, count 2 2006.218.08:07:31.04#ibcon#about to read 4, iclass 10, count 2 2006.218.08:07:31.04#ibcon#read 4, iclass 10, count 2 2006.218.08:07:31.04#ibcon#about to read 5, iclass 10, count 2 2006.218.08:07:31.04#ibcon#read 5, iclass 10, count 2 2006.218.08:07:31.04#ibcon#about to read 6, iclass 10, count 2 2006.218.08:07:31.04#ibcon#read 6, iclass 10, count 2 2006.218.08:07:31.04#ibcon#end of sib2, iclass 10, count 2 2006.218.08:07:31.04#ibcon#*after write, iclass 10, count 2 2006.218.08:07:31.04#ibcon#*before return 0, iclass 10, count 2 2006.218.08:07:31.04#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.218.08:07:31.04#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.218.08:07:31.04#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.218.08:07:31.04#ibcon#ireg 7 cls_cnt 0 2006.218.08:07:31.04#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.218.08:07:31.16#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.218.08:07:31.16#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.218.08:07:31.16#ibcon#enter wrdev, iclass 10, count 0 2006.218.08:07:31.16#ibcon#first serial, iclass 10, count 0 2006.218.08:07:31.16#ibcon#enter sib2, iclass 10, count 0 2006.218.08:07:31.16#ibcon#flushed, iclass 10, count 0 2006.218.08:07:31.16#ibcon#about to write, iclass 10, count 0 2006.218.08:07:31.16#ibcon#wrote, iclass 10, count 0 2006.218.08:07:31.16#ibcon#about to read 3, iclass 10, count 0 2006.218.08:07:31.18#ibcon#read 3, iclass 10, count 0 2006.218.08:07:31.18#ibcon#about to read 4, iclass 10, count 0 2006.218.08:07:31.18#ibcon#read 4, iclass 10, count 0 2006.218.08:07:31.18#ibcon#about to read 5, iclass 10, count 0 2006.218.08:07:31.18#ibcon#read 5, iclass 10, count 0 2006.218.08:07:31.18#ibcon#about to read 6, iclass 10, count 0 2006.218.08:07:31.18#ibcon#read 6, iclass 10, count 0 2006.218.08:07:31.18#ibcon#end of sib2, iclass 10, count 0 2006.218.08:07:31.18#ibcon#*mode == 0, iclass 10, count 0 2006.218.08:07:31.18#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.218.08:07:31.18#ibcon#[27=USB\r\n] 2006.218.08:07:31.18#ibcon#*before write, iclass 10, count 0 2006.218.08:07:31.18#ibcon#enter sib2, iclass 10, count 0 2006.218.08:07:31.18#ibcon#flushed, iclass 10, count 0 2006.218.08:07:31.18#ibcon#about to write, iclass 10, count 0 2006.218.08:07:31.18#ibcon#wrote, iclass 10, count 0 2006.218.08:07:31.18#ibcon#about to read 3, iclass 10, count 0 2006.218.08:07:31.21#ibcon#read 3, iclass 10, count 0 2006.218.08:07:31.21#ibcon#about to read 4, iclass 10, count 0 2006.218.08:07:31.21#ibcon#read 4, iclass 10, count 0 2006.218.08:07:31.21#ibcon#about to read 5, iclass 10, count 0 2006.218.08:07:31.21#ibcon#read 5, iclass 10, count 0 2006.218.08:07:31.21#ibcon#about to read 6, iclass 10, count 0 2006.218.08:07:31.21#ibcon#read 6, iclass 10, count 0 2006.218.08:07:31.21#ibcon#end of sib2, iclass 10, count 0 2006.218.08:07:31.21#ibcon#*after write, iclass 10, count 0 2006.218.08:07:31.21#ibcon#*before return 0, iclass 10, count 0 2006.218.08:07:31.21#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.218.08:07:31.21#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.218.08:07:31.21#ibcon#about to clear, iclass 10 cls_cnt 0 2006.218.08:07:31.21#ibcon#cleared, iclass 10 cls_cnt 0 2006.218.08:07:31.21$vc4f8/vblo=3,656.99 2006.218.08:07:31.21#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.218.08:07:31.21#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.218.08:07:31.21#ibcon#ireg 17 cls_cnt 0 2006.218.08:07:31.21#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.218.08:07:31.21#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.218.08:07:31.21#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.218.08:07:31.21#ibcon#enter wrdev, iclass 12, count 0 2006.218.08:07:31.21#ibcon#first serial, iclass 12, count 0 2006.218.08:07:31.21#ibcon#enter sib2, iclass 12, count 0 2006.218.08:07:31.21#ibcon#flushed, iclass 12, count 0 2006.218.08:07:31.21#ibcon#about to write, iclass 12, count 0 2006.218.08:07:31.21#ibcon#wrote, iclass 12, count 0 2006.218.08:07:31.21#ibcon#about to read 3, iclass 12, count 0 2006.218.08:07:31.23#ibcon#read 3, iclass 12, count 0 2006.218.08:07:31.23#ibcon#about to read 4, iclass 12, count 0 2006.218.08:07:31.23#ibcon#read 4, iclass 12, count 0 2006.218.08:07:31.23#ibcon#about to read 5, iclass 12, count 0 2006.218.08:07:31.23#ibcon#read 5, iclass 12, count 0 2006.218.08:07:31.23#ibcon#about to read 6, iclass 12, count 0 2006.218.08:07:31.23#ibcon#read 6, iclass 12, count 0 2006.218.08:07:31.23#ibcon#end of sib2, iclass 12, count 0 2006.218.08:07:31.23#ibcon#*mode == 0, iclass 12, count 0 2006.218.08:07:31.23#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.218.08:07:31.23#ibcon#[28=FRQ=03,656.99\r\n] 2006.218.08:07:31.23#ibcon#*before write, iclass 12, count 0 2006.218.08:07:31.23#ibcon#enter sib2, iclass 12, count 0 2006.218.08:07:31.23#ibcon#flushed, iclass 12, count 0 2006.218.08:07:31.23#ibcon#about to write, iclass 12, count 0 2006.218.08:07:31.23#ibcon#wrote, iclass 12, count 0 2006.218.08:07:31.23#ibcon#about to read 3, iclass 12, count 0 2006.218.08:07:31.27#ibcon#read 3, iclass 12, count 0 2006.218.08:07:31.27#ibcon#about to read 4, iclass 12, count 0 2006.218.08:07:31.27#ibcon#read 4, iclass 12, count 0 2006.218.08:07:31.27#ibcon#about to read 5, iclass 12, count 0 2006.218.08:07:31.27#ibcon#read 5, iclass 12, count 0 2006.218.08:07:31.27#ibcon#about to read 6, iclass 12, count 0 2006.218.08:07:31.27#ibcon#read 6, iclass 12, count 0 2006.218.08:07:31.27#ibcon#end of sib2, iclass 12, count 0 2006.218.08:07:31.27#ibcon#*after write, iclass 12, count 0 2006.218.08:07:31.27#ibcon#*before return 0, iclass 12, count 0 2006.218.08:07:31.27#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.218.08:07:31.27#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.218.08:07:31.27#ibcon#about to clear, iclass 12 cls_cnt 0 2006.218.08:07:31.27#ibcon#cleared, iclass 12 cls_cnt 0 2006.218.08:07:31.27$vc4f8/vb=3,4 2006.218.08:07:31.27#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.218.08:07:31.27#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.218.08:07:31.27#ibcon#ireg 11 cls_cnt 2 2006.218.08:07:31.27#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.218.08:07:31.33#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.218.08:07:31.33#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.218.08:07:31.33#ibcon#enter wrdev, iclass 14, count 2 2006.218.08:07:31.33#ibcon#first serial, iclass 14, count 2 2006.218.08:07:31.33#ibcon#enter sib2, iclass 14, count 2 2006.218.08:07:31.33#ibcon#flushed, iclass 14, count 2 2006.218.08:07:31.33#ibcon#about to write, iclass 14, count 2 2006.218.08:07:31.33#ibcon#wrote, iclass 14, count 2 2006.218.08:07:31.33#ibcon#about to read 3, iclass 14, count 2 2006.218.08:07:31.35#ibcon#read 3, iclass 14, count 2 2006.218.08:07:31.35#ibcon#about to read 4, iclass 14, count 2 2006.218.08:07:31.35#ibcon#read 4, iclass 14, count 2 2006.218.08:07:31.35#ibcon#about to read 5, iclass 14, count 2 2006.218.08:07:31.35#ibcon#read 5, iclass 14, count 2 2006.218.08:07:31.35#ibcon#about to read 6, iclass 14, count 2 2006.218.08:07:31.35#ibcon#read 6, iclass 14, count 2 2006.218.08:07:31.35#ibcon#end of sib2, iclass 14, count 2 2006.218.08:07:31.35#ibcon#*mode == 0, iclass 14, count 2 2006.218.08:07:31.35#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.218.08:07:31.35#ibcon#[27=AT03-04\r\n] 2006.218.08:07:31.35#ibcon#*before write, iclass 14, count 2 2006.218.08:07:31.35#ibcon#enter sib2, iclass 14, count 2 2006.218.08:07:31.35#ibcon#flushed, iclass 14, count 2 2006.218.08:07:31.35#ibcon#about to write, iclass 14, count 2 2006.218.08:07:31.35#ibcon#wrote, iclass 14, count 2 2006.218.08:07:31.35#ibcon#about to read 3, iclass 14, count 2 2006.218.08:07:31.38#ibcon#read 3, iclass 14, count 2 2006.218.08:07:31.38#ibcon#about to read 4, iclass 14, count 2 2006.218.08:07:31.38#ibcon#read 4, iclass 14, count 2 2006.218.08:07:31.38#ibcon#about to read 5, iclass 14, count 2 2006.218.08:07:31.38#ibcon#read 5, iclass 14, count 2 2006.218.08:07:31.38#ibcon#about to read 6, iclass 14, count 2 2006.218.08:07:31.38#ibcon#read 6, iclass 14, count 2 2006.218.08:07:31.38#ibcon#end of sib2, iclass 14, count 2 2006.218.08:07:31.38#ibcon#*after write, iclass 14, count 2 2006.218.08:07:31.38#ibcon#*before return 0, iclass 14, count 2 2006.218.08:07:31.38#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.218.08:07:31.38#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.218.08:07:31.38#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.218.08:07:31.38#ibcon#ireg 7 cls_cnt 0 2006.218.08:07:31.38#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.218.08:07:31.50#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.218.08:07:31.50#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.218.08:07:31.50#ibcon#enter wrdev, iclass 14, count 0 2006.218.08:07:31.50#ibcon#first serial, iclass 14, count 0 2006.218.08:07:31.50#ibcon#enter sib2, iclass 14, count 0 2006.218.08:07:31.50#ibcon#flushed, iclass 14, count 0 2006.218.08:07:31.50#ibcon#about to write, iclass 14, count 0 2006.218.08:07:31.50#ibcon#wrote, iclass 14, count 0 2006.218.08:07:31.50#ibcon#about to read 3, iclass 14, count 0 2006.218.08:07:31.52#ibcon#read 3, iclass 14, count 0 2006.218.08:07:31.52#ibcon#about to read 4, iclass 14, count 0 2006.218.08:07:31.52#ibcon#read 4, iclass 14, count 0 2006.218.08:07:31.52#ibcon#about to read 5, iclass 14, count 0 2006.218.08:07:31.52#ibcon#read 5, iclass 14, count 0 2006.218.08:07:31.52#ibcon#about to read 6, iclass 14, count 0 2006.218.08:07:31.52#ibcon#read 6, iclass 14, count 0 2006.218.08:07:31.52#ibcon#end of sib2, iclass 14, count 0 2006.218.08:07:31.52#ibcon#*mode == 0, iclass 14, count 0 2006.218.08:07:31.52#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.218.08:07:31.52#ibcon#[27=USB\r\n] 2006.218.08:07:31.52#ibcon#*before write, iclass 14, count 0 2006.218.08:07:31.52#ibcon#enter sib2, iclass 14, count 0 2006.218.08:07:31.52#ibcon#flushed, iclass 14, count 0 2006.218.08:07:31.52#ibcon#about to write, iclass 14, count 0 2006.218.08:07:31.52#ibcon#wrote, iclass 14, count 0 2006.218.08:07:31.52#ibcon#about to read 3, iclass 14, count 0 2006.218.08:07:31.55#ibcon#read 3, iclass 14, count 0 2006.218.08:07:31.55#ibcon#about to read 4, iclass 14, count 0 2006.218.08:07:31.55#ibcon#read 4, iclass 14, count 0 2006.218.08:07:31.55#ibcon#about to read 5, iclass 14, count 0 2006.218.08:07:31.55#ibcon#read 5, iclass 14, count 0 2006.218.08:07:31.55#ibcon#about to read 6, iclass 14, count 0 2006.218.08:07:31.55#ibcon#read 6, iclass 14, count 0 2006.218.08:07:31.55#ibcon#end of sib2, iclass 14, count 0 2006.218.08:07:31.55#ibcon#*after write, iclass 14, count 0 2006.218.08:07:31.55#ibcon#*before return 0, iclass 14, count 0 2006.218.08:07:31.55#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.218.08:07:31.55#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.218.08:07:31.55#ibcon#about to clear, iclass 14 cls_cnt 0 2006.218.08:07:31.55#ibcon#cleared, iclass 14 cls_cnt 0 2006.218.08:07:31.55$vc4f8/vblo=4,712.99 2006.218.08:07:31.55#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.218.08:07:31.55#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.218.08:07:31.55#ibcon#ireg 17 cls_cnt 0 2006.218.08:07:31.55#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.218.08:07:31.55#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.218.08:07:31.55#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.218.08:07:31.55#ibcon#enter wrdev, iclass 16, count 0 2006.218.08:07:31.55#ibcon#first serial, iclass 16, count 0 2006.218.08:07:31.55#ibcon#enter sib2, iclass 16, count 0 2006.218.08:07:31.55#ibcon#flushed, iclass 16, count 0 2006.218.08:07:31.55#ibcon#about to write, iclass 16, count 0 2006.218.08:07:31.55#ibcon#wrote, iclass 16, count 0 2006.218.08:07:31.55#ibcon#about to read 3, iclass 16, count 0 2006.218.08:07:31.57#ibcon#read 3, iclass 16, count 0 2006.218.08:07:31.57#ibcon#about to read 4, iclass 16, count 0 2006.218.08:07:31.57#ibcon#read 4, iclass 16, count 0 2006.218.08:07:31.57#ibcon#about to read 5, iclass 16, count 0 2006.218.08:07:31.57#ibcon#read 5, iclass 16, count 0 2006.218.08:07:31.57#ibcon#about to read 6, iclass 16, count 0 2006.218.08:07:31.57#ibcon#read 6, iclass 16, count 0 2006.218.08:07:31.57#ibcon#end of sib2, iclass 16, count 0 2006.218.08:07:31.57#ibcon#*mode == 0, iclass 16, count 0 2006.218.08:07:31.57#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.218.08:07:31.57#ibcon#[28=FRQ=04,712.99\r\n] 2006.218.08:07:31.57#ibcon#*before write, iclass 16, count 0 2006.218.08:07:31.57#ibcon#enter sib2, iclass 16, count 0 2006.218.08:07:31.57#ibcon#flushed, iclass 16, count 0 2006.218.08:07:31.57#ibcon#about to write, iclass 16, count 0 2006.218.08:07:31.57#ibcon#wrote, iclass 16, count 0 2006.218.08:07:31.57#ibcon#about to read 3, iclass 16, count 0 2006.218.08:07:31.61#ibcon#read 3, iclass 16, count 0 2006.218.08:07:31.61#ibcon#about to read 4, iclass 16, count 0 2006.218.08:07:31.61#ibcon#read 4, iclass 16, count 0 2006.218.08:07:31.61#ibcon#about to read 5, iclass 16, count 0 2006.218.08:07:31.61#ibcon#read 5, iclass 16, count 0 2006.218.08:07:31.61#ibcon#about to read 6, iclass 16, count 0 2006.218.08:07:31.61#ibcon#read 6, iclass 16, count 0 2006.218.08:07:31.61#ibcon#end of sib2, iclass 16, count 0 2006.218.08:07:31.61#ibcon#*after write, iclass 16, count 0 2006.218.08:07:31.61#ibcon#*before return 0, iclass 16, count 0 2006.218.08:07:31.61#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.218.08:07:31.61#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.218.08:07:31.61#ibcon#about to clear, iclass 16 cls_cnt 0 2006.218.08:07:31.61#ibcon#cleared, iclass 16 cls_cnt 0 2006.218.08:07:31.61$vc4f8/vb=4,4 2006.218.08:07:31.61#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.218.08:07:31.61#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.218.08:07:31.61#ibcon#ireg 11 cls_cnt 2 2006.218.08:07:31.61#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.218.08:07:31.67#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.218.08:07:31.67#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.218.08:07:31.67#ibcon#enter wrdev, iclass 18, count 2 2006.218.08:07:31.67#ibcon#first serial, iclass 18, count 2 2006.218.08:07:31.67#ibcon#enter sib2, iclass 18, count 2 2006.218.08:07:31.67#ibcon#flushed, iclass 18, count 2 2006.218.08:07:31.67#ibcon#about to write, iclass 18, count 2 2006.218.08:07:31.67#ibcon#wrote, iclass 18, count 2 2006.218.08:07:31.67#ibcon#about to read 3, iclass 18, count 2 2006.218.08:07:31.69#ibcon#read 3, iclass 18, count 2 2006.218.08:07:31.69#ibcon#about to read 4, iclass 18, count 2 2006.218.08:07:31.69#ibcon#read 4, iclass 18, count 2 2006.218.08:07:31.69#ibcon#about to read 5, iclass 18, count 2 2006.218.08:07:31.69#ibcon#read 5, iclass 18, count 2 2006.218.08:07:31.69#ibcon#about to read 6, iclass 18, count 2 2006.218.08:07:31.69#ibcon#read 6, iclass 18, count 2 2006.218.08:07:31.69#ibcon#end of sib2, iclass 18, count 2 2006.218.08:07:31.69#ibcon#*mode == 0, iclass 18, count 2 2006.218.08:07:31.69#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.218.08:07:31.69#ibcon#[27=AT04-04\r\n] 2006.218.08:07:31.69#ibcon#*before write, iclass 18, count 2 2006.218.08:07:31.69#ibcon#enter sib2, iclass 18, count 2 2006.218.08:07:31.69#ibcon#flushed, iclass 18, count 2 2006.218.08:07:31.69#ibcon#about to write, iclass 18, count 2 2006.218.08:07:31.69#ibcon#wrote, iclass 18, count 2 2006.218.08:07:31.69#ibcon#about to read 3, iclass 18, count 2 2006.218.08:07:31.72#ibcon#read 3, iclass 18, count 2 2006.218.08:07:31.72#ibcon#about to read 4, iclass 18, count 2 2006.218.08:07:31.72#ibcon#read 4, iclass 18, count 2 2006.218.08:07:31.72#ibcon#about to read 5, iclass 18, count 2 2006.218.08:07:31.72#ibcon#read 5, iclass 18, count 2 2006.218.08:07:31.72#ibcon#about to read 6, iclass 18, count 2 2006.218.08:07:31.72#ibcon#read 6, iclass 18, count 2 2006.218.08:07:31.72#ibcon#end of sib2, iclass 18, count 2 2006.218.08:07:31.72#ibcon#*after write, iclass 18, count 2 2006.218.08:07:31.72#ibcon#*before return 0, iclass 18, count 2 2006.218.08:07:31.72#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.218.08:07:31.72#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.218.08:07:31.72#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.218.08:07:31.72#ibcon#ireg 7 cls_cnt 0 2006.218.08:07:31.72#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.218.08:07:31.75#abcon#<5=/05 4.2 7.4 30.94 721007.5\r\n> 2006.218.08:07:31.77#abcon#{5=INTERFACE CLEAR} 2006.218.08:07:31.83#abcon#[5=S1D000X0/0*\r\n] 2006.218.08:07:31.84#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.218.08:07:31.84#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.218.08:07:31.84#ibcon#enter wrdev, iclass 18, count 0 2006.218.08:07:31.84#ibcon#first serial, iclass 18, count 0 2006.218.08:07:31.84#ibcon#enter sib2, iclass 18, count 0 2006.218.08:07:31.84#ibcon#flushed, iclass 18, count 0 2006.218.08:07:31.84#ibcon#about to write, iclass 18, count 0 2006.218.08:07:31.84#ibcon#wrote, iclass 18, count 0 2006.218.08:07:31.84#ibcon#about to read 3, iclass 18, count 0 2006.218.08:07:31.86#ibcon#read 3, iclass 18, count 0 2006.218.08:07:31.86#ibcon#about to read 4, iclass 18, count 0 2006.218.08:07:31.86#ibcon#read 4, iclass 18, count 0 2006.218.08:07:31.86#ibcon#about to read 5, iclass 18, count 0 2006.218.08:07:31.86#ibcon#read 5, iclass 18, count 0 2006.218.08:07:31.86#ibcon#about to read 6, iclass 18, count 0 2006.218.08:07:31.86#ibcon#read 6, iclass 18, count 0 2006.218.08:07:31.86#ibcon#end of sib2, iclass 18, count 0 2006.218.08:07:31.86#ibcon#*mode == 0, iclass 18, count 0 2006.218.08:07:31.86#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.218.08:07:31.86#ibcon#[27=USB\r\n] 2006.218.08:07:31.86#ibcon#*before write, iclass 18, count 0 2006.218.08:07:31.86#ibcon#enter sib2, iclass 18, count 0 2006.218.08:07:31.86#ibcon#flushed, iclass 18, count 0 2006.218.08:07:31.86#ibcon#about to write, iclass 18, count 0 2006.218.08:07:31.86#ibcon#wrote, iclass 18, count 0 2006.218.08:07:31.86#ibcon#about to read 3, iclass 18, count 0 2006.218.08:07:31.89#ibcon#read 3, iclass 18, count 0 2006.218.08:07:31.89#ibcon#about to read 4, iclass 18, count 0 2006.218.08:07:31.89#ibcon#read 4, iclass 18, count 0 2006.218.08:07:31.89#ibcon#about to read 5, iclass 18, count 0 2006.218.08:07:31.89#ibcon#read 5, iclass 18, count 0 2006.218.08:07:31.89#ibcon#about to read 6, iclass 18, count 0 2006.218.08:07:31.89#ibcon#read 6, iclass 18, count 0 2006.218.08:07:31.89#ibcon#end of sib2, iclass 18, count 0 2006.218.08:07:31.89#ibcon#*after write, iclass 18, count 0 2006.218.08:07:31.89#ibcon#*before return 0, iclass 18, count 0 2006.218.08:07:31.89#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.218.08:07:31.89#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.218.08:07:31.89#ibcon#about to clear, iclass 18 cls_cnt 0 2006.218.08:07:31.89#ibcon#cleared, iclass 18 cls_cnt 0 2006.218.08:07:31.89$vc4f8/vblo=5,744.99 2006.218.08:07:31.89#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.218.08:07:31.89#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.218.08:07:31.89#ibcon#ireg 17 cls_cnt 0 2006.218.08:07:31.89#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.218.08:07:31.89#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.218.08:07:31.89#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.218.08:07:31.89#ibcon#enter wrdev, iclass 24, count 0 2006.218.08:07:31.89#ibcon#first serial, iclass 24, count 0 2006.218.08:07:31.89#ibcon#enter sib2, iclass 24, count 0 2006.218.08:07:31.89#ibcon#flushed, iclass 24, count 0 2006.218.08:07:31.89#ibcon#about to write, iclass 24, count 0 2006.218.08:07:31.89#ibcon#wrote, iclass 24, count 0 2006.218.08:07:31.89#ibcon#about to read 3, iclass 24, count 0 2006.218.08:07:31.91#ibcon#read 3, iclass 24, count 0 2006.218.08:07:31.91#ibcon#about to read 4, iclass 24, count 0 2006.218.08:07:31.91#ibcon#read 4, iclass 24, count 0 2006.218.08:07:31.91#ibcon#about to read 5, iclass 24, count 0 2006.218.08:07:31.91#ibcon#read 5, iclass 24, count 0 2006.218.08:07:31.91#ibcon#about to read 6, iclass 24, count 0 2006.218.08:07:31.91#ibcon#read 6, iclass 24, count 0 2006.218.08:07:31.91#ibcon#end of sib2, iclass 24, count 0 2006.218.08:07:31.91#ibcon#*mode == 0, iclass 24, count 0 2006.218.08:07:31.91#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.218.08:07:31.91#ibcon#[28=FRQ=05,744.99\r\n] 2006.218.08:07:31.91#ibcon#*before write, iclass 24, count 0 2006.218.08:07:31.91#ibcon#enter sib2, iclass 24, count 0 2006.218.08:07:31.91#ibcon#flushed, iclass 24, count 0 2006.218.08:07:31.91#ibcon#about to write, iclass 24, count 0 2006.218.08:07:31.91#ibcon#wrote, iclass 24, count 0 2006.218.08:07:31.91#ibcon#about to read 3, iclass 24, count 0 2006.218.08:07:31.95#ibcon#read 3, iclass 24, count 0 2006.218.08:07:31.95#ibcon#about to read 4, iclass 24, count 0 2006.218.08:07:31.95#ibcon#read 4, iclass 24, count 0 2006.218.08:07:31.95#ibcon#about to read 5, iclass 24, count 0 2006.218.08:07:31.95#ibcon#read 5, iclass 24, count 0 2006.218.08:07:31.95#ibcon#about to read 6, iclass 24, count 0 2006.218.08:07:31.95#ibcon#read 6, iclass 24, count 0 2006.218.08:07:31.95#ibcon#end of sib2, iclass 24, count 0 2006.218.08:07:31.95#ibcon#*after write, iclass 24, count 0 2006.218.08:07:31.95#ibcon#*before return 0, iclass 24, count 0 2006.218.08:07:31.95#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.218.08:07:31.95#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.218.08:07:31.95#ibcon#about to clear, iclass 24 cls_cnt 0 2006.218.08:07:31.95#ibcon#cleared, iclass 24 cls_cnt 0 2006.218.08:07:31.95$vc4f8/vb=5,4 2006.218.08:07:31.95#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.218.08:07:31.95#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.218.08:07:31.95#ibcon#ireg 11 cls_cnt 2 2006.218.08:07:31.95#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.218.08:07:32.01#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.218.08:07:32.01#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.218.08:07:32.01#ibcon#enter wrdev, iclass 26, count 2 2006.218.08:07:32.01#ibcon#first serial, iclass 26, count 2 2006.218.08:07:32.01#ibcon#enter sib2, iclass 26, count 2 2006.218.08:07:32.01#ibcon#flushed, iclass 26, count 2 2006.218.08:07:32.01#ibcon#about to write, iclass 26, count 2 2006.218.08:07:32.01#ibcon#wrote, iclass 26, count 2 2006.218.08:07:32.01#ibcon#about to read 3, iclass 26, count 2 2006.218.08:07:32.03#ibcon#read 3, iclass 26, count 2 2006.218.08:07:32.03#ibcon#about to read 4, iclass 26, count 2 2006.218.08:07:32.03#ibcon#read 4, iclass 26, count 2 2006.218.08:07:32.03#ibcon#about to read 5, iclass 26, count 2 2006.218.08:07:32.03#ibcon#read 5, iclass 26, count 2 2006.218.08:07:32.03#ibcon#about to read 6, iclass 26, count 2 2006.218.08:07:32.03#ibcon#read 6, iclass 26, count 2 2006.218.08:07:32.03#ibcon#end of sib2, iclass 26, count 2 2006.218.08:07:32.03#ibcon#*mode == 0, iclass 26, count 2 2006.218.08:07:32.03#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.218.08:07:32.03#ibcon#[27=AT05-04\r\n] 2006.218.08:07:32.03#ibcon#*before write, iclass 26, count 2 2006.218.08:07:32.03#ibcon#enter sib2, iclass 26, count 2 2006.218.08:07:32.03#ibcon#flushed, iclass 26, count 2 2006.218.08:07:32.03#ibcon#about to write, iclass 26, count 2 2006.218.08:07:32.03#ibcon#wrote, iclass 26, count 2 2006.218.08:07:32.03#ibcon#about to read 3, iclass 26, count 2 2006.218.08:07:32.06#ibcon#read 3, iclass 26, count 2 2006.218.08:07:32.06#ibcon#about to read 4, iclass 26, count 2 2006.218.08:07:32.06#ibcon#read 4, iclass 26, count 2 2006.218.08:07:32.06#ibcon#about to read 5, iclass 26, count 2 2006.218.08:07:32.06#ibcon#read 5, iclass 26, count 2 2006.218.08:07:32.06#ibcon#about to read 6, iclass 26, count 2 2006.218.08:07:32.06#ibcon#read 6, iclass 26, count 2 2006.218.08:07:32.06#ibcon#end of sib2, iclass 26, count 2 2006.218.08:07:32.06#ibcon#*after write, iclass 26, count 2 2006.218.08:07:32.06#ibcon#*before return 0, iclass 26, count 2 2006.218.08:07:32.06#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.218.08:07:32.06#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.218.08:07:32.06#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.218.08:07:32.06#ibcon#ireg 7 cls_cnt 0 2006.218.08:07:32.06#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.218.08:07:32.18#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.218.08:07:32.18#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.218.08:07:32.18#ibcon#enter wrdev, iclass 26, count 0 2006.218.08:07:32.18#ibcon#first serial, iclass 26, count 0 2006.218.08:07:32.18#ibcon#enter sib2, iclass 26, count 0 2006.218.08:07:32.18#ibcon#flushed, iclass 26, count 0 2006.218.08:07:32.18#ibcon#about to write, iclass 26, count 0 2006.218.08:07:32.18#ibcon#wrote, iclass 26, count 0 2006.218.08:07:32.18#ibcon#about to read 3, iclass 26, count 0 2006.218.08:07:32.20#ibcon#read 3, iclass 26, count 0 2006.218.08:07:32.20#ibcon#about to read 4, iclass 26, count 0 2006.218.08:07:32.20#ibcon#read 4, iclass 26, count 0 2006.218.08:07:32.20#ibcon#about to read 5, iclass 26, count 0 2006.218.08:07:32.20#ibcon#read 5, iclass 26, count 0 2006.218.08:07:32.20#ibcon#about to read 6, iclass 26, count 0 2006.218.08:07:32.20#ibcon#read 6, iclass 26, count 0 2006.218.08:07:32.20#ibcon#end of sib2, iclass 26, count 0 2006.218.08:07:32.20#ibcon#*mode == 0, iclass 26, count 0 2006.218.08:07:32.20#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.218.08:07:32.20#ibcon#[27=USB\r\n] 2006.218.08:07:32.20#ibcon#*before write, iclass 26, count 0 2006.218.08:07:32.20#ibcon#enter sib2, iclass 26, count 0 2006.218.08:07:32.20#ibcon#flushed, iclass 26, count 0 2006.218.08:07:32.20#ibcon#about to write, iclass 26, count 0 2006.218.08:07:32.20#ibcon#wrote, iclass 26, count 0 2006.218.08:07:32.20#ibcon#about to read 3, iclass 26, count 0 2006.218.08:07:32.23#ibcon#read 3, iclass 26, count 0 2006.218.08:07:32.23#ibcon#about to read 4, iclass 26, count 0 2006.218.08:07:32.23#ibcon#read 4, iclass 26, count 0 2006.218.08:07:32.23#ibcon#about to read 5, iclass 26, count 0 2006.218.08:07:32.23#ibcon#read 5, iclass 26, count 0 2006.218.08:07:32.23#ibcon#about to read 6, iclass 26, count 0 2006.218.08:07:32.23#ibcon#read 6, iclass 26, count 0 2006.218.08:07:32.23#ibcon#end of sib2, iclass 26, count 0 2006.218.08:07:32.23#ibcon#*after write, iclass 26, count 0 2006.218.08:07:32.23#ibcon#*before return 0, iclass 26, count 0 2006.218.08:07:32.23#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.218.08:07:32.23#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.218.08:07:32.23#ibcon#about to clear, iclass 26 cls_cnt 0 2006.218.08:07:32.23#ibcon#cleared, iclass 26 cls_cnt 0 2006.218.08:07:32.23$vc4f8/vblo=6,752.99 2006.218.08:07:32.23#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.218.08:07:32.23#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.218.08:07:32.23#ibcon#ireg 17 cls_cnt 0 2006.218.08:07:32.23#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.218.08:07:32.23#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.218.08:07:32.23#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.218.08:07:32.23#ibcon#enter wrdev, iclass 28, count 0 2006.218.08:07:32.23#ibcon#first serial, iclass 28, count 0 2006.218.08:07:32.23#ibcon#enter sib2, iclass 28, count 0 2006.218.08:07:32.23#ibcon#flushed, iclass 28, count 0 2006.218.08:07:32.23#ibcon#about to write, iclass 28, count 0 2006.218.08:07:32.23#ibcon#wrote, iclass 28, count 0 2006.218.08:07:32.23#ibcon#about to read 3, iclass 28, count 0 2006.218.08:07:32.25#ibcon#read 3, iclass 28, count 0 2006.218.08:07:32.25#ibcon#about to read 4, iclass 28, count 0 2006.218.08:07:32.25#ibcon#read 4, iclass 28, count 0 2006.218.08:07:32.25#ibcon#about to read 5, iclass 28, count 0 2006.218.08:07:32.25#ibcon#read 5, iclass 28, count 0 2006.218.08:07:32.25#ibcon#about to read 6, iclass 28, count 0 2006.218.08:07:32.25#ibcon#read 6, iclass 28, count 0 2006.218.08:07:32.25#ibcon#end of sib2, iclass 28, count 0 2006.218.08:07:32.25#ibcon#*mode == 0, iclass 28, count 0 2006.218.08:07:32.25#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.218.08:07:32.25#ibcon#[28=FRQ=06,752.99\r\n] 2006.218.08:07:32.25#ibcon#*before write, iclass 28, count 0 2006.218.08:07:32.25#ibcon#enter sib2, iclass 28, count 0 2006.218.08:07:32.25#ibcon#flushed, iclass 28, count 0 2006.218.08:07:32.25#ibcon#about to write, iclass 28, count 0 2006.218.08:07:32.25#ibcon#wrote, iclass 28, count 0 2006.218.08:07:32.25#ibcon#about to read 3, iclass 28, count 0 2006.218.08:07:32.29#ibcon#read 3, iclass 28, count 0 2006.218.08:07:32.29#ibcon#about to read 4, iclass 28, count 0 2006.218.08:07:32.29#ibcon#read 4, iclass 28, count 0 2006.218.08:07:32.29#ibcon#about to read 5, iclass 28, count 0 2006.218.08:07:32.29#ibcon#read 5, iclass 28, count 0 2006.218.08:07:32.29#ibcon#about to read 6, iclass 28, count 0 2006.218.08:07:32.29#ibcon#read 6, iclass 28, count 0 2006.218.08:07:32.29#ibcon#end of sib2, iclass 28, count 0 2006.218.08:07:32.29#ibcon#*after write, iclass 28, count 0 2006.218.08:07:32.29#ibcon#*before return 0, iclass 28, count 0 2006.218.08:07:32.29#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.218.08:07:32.29#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.218.08:07:32.29#ibcon#about to clear, iclass 28 cls_cnt 0 2006.218.08:07:32.29#ibcon#cleared, iclass 28 cls_cnt 0 2006.218.08:07:32.29$vc4f8/vb=6,4 2006.218.08:07:32.29#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.218.08:07:32.29#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.218.08:07:32.29#ibcon#ireg 11 cls_cnt 2 2006.218.08:07:32.29#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.218.08:07:32.35#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.218.08:07:32.35#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.218.08:07:32.35#ibcon#enter wrdev, iclass 30, count 2 2006.218.08:07:32.35#ibcon#first serial, iclass 30, count 2 2006.218.08:07:32.35#ibcon#enter sib2, iclass 30, count 2 2006.218.08:07:32.35#ibcon#flushed, iclass 30, count 2 2006.218.08:07:32.35#ibcon#about to write, iclass 30, count 2 2006.218.08:07:32.35#ibcon#wrote, iclass 30, count 2 2006.218.08:07:32.35#ibcon#about to read 3, iclass 30, count 2 2006.218.08:07:32.37#ibcon#read 3, iclass 30, count 2 2006.218.08:07:32.37#ibcon#about to read 4, iclass 30, count 2 2006.218.08:07:32.37#ibcon#read 4, iclass 30, count 2 2006.218.08:07:32.37#ibcon#about to read 5, iclass 30, count 2 2006.218.08:07:32.37#ibcon#read 5, iclass 30, count 2 2006.218.08:07:32.37#ibcon#about to read 6, iclass 30, count 2 2006.218.08:07:32.37#ibcon#read 6, iclass 30, count 2 2006.218.08:07:32.37#ibcon#end of sib2, iclass 30, count 2 2006.218.08:07:32.37#ibcon#*mode == 0, iclass 30, count 2 2006.218.08:07:32.37#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.218.08:07:32.37#ibcon#[27=AT06-04\r\n] 2006.218.08:07:32.37#ibcon#*before write, iclass 30, count 2 2006.218.08:07:32.37#ibcon#enter sib2, iclass 30, count 2 2006.218.08:07:32.37#ibcon#flushed, iclass 30, count 2 2006.218.08:07:32.37#ibcon#about to write, iclass 30, count 2 2006.218.08:07:32.37#ibcon#wrote, iclass 30, count 2 2006.218.08:07:32.37#ibcon#about to read 3, iclass 30, count 2 2006.218.08:07:32.40#ibcon#read 3, iclass 30, count 2 2006.218.08:07:32.40#ibcon#about to read 4, iclass 30, count 2 2006.218.08:07:32.40#ibcon#read 4, iclass 30, count 2 2006.218.08:07:32.40#ibcon#about to read 5, iclass 30, count 2 2006.218.08:07:32.40#ibcon#read 5, iclass 30, count 2 2006.218.08:07:32.40#ibcon#about to read 6, iclass 30, count 2 2006.218.08:07:32.40#ibcon#read 6, iclass 30, count 2 2006.218.08:07:32.40#ibcon#end of sib2, iclass 30, count 2 2006.218.08:07:32.40#ibcon#*after write, iclass 30, count 2 2006.218.08:07:32.40#ibcon#*before return 0, iclass 30, count 2 2006.218.08:07:32.40#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.218.08:07:32.40#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.218.08:07:32.40#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.218.08:07:32.40#ibcon#ireg 7 cls_cnt 0 2006.218.08:07:32.40#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.218.08:07:32.52#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.218.08:07:32.52#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.218.08:07:32.52#ibcon#enter wrdev, iclass 30, count 0 2006.218.08:07:32.52#ibcon#first serial, iclass 30, count 0 2006.218.08:07:32.52#ibcon#enter sib2, iclass 30, count 0 2006.218.08:07:32.52#ibcon#flushed, iclass 30, count 0 2006.218.08:07:32.52#ibcon#about to write, iclass 30, count 0 2006.218.08:07:32.52#ibcon#wrote, iclass 30, count 0 2006.218.08:07:32.52#ibcon#about to read 3, iclass 30, count 0 2006.218.08:07:32.54#ibcon#read 3, iclass 30, count 0 2006.218.08:07:32.54#ibcon#about to read 4, iclass 30, count 0 2006.218.08:07:32.54#ibcon#read 4, iclass 30, count 0 2006.218.08:07:32.54#ibcon#about to read 5, iclass 30, count 0 2006.218.08:07:32.54#ibcon#read 5, iclass 30, count 0 2006.218.08:07:32.54#ibcon#about to read 6, iclass 30, count 0 2006.218.08:07:32.54#ibcon#read 6, iclass 30, count 0 2006.218.08:07:32.54#ibcon#end of sib2, iclass 30, count 0 2006.218.08:07:32.54#ibcon#*mode == 0, iclass 30, count 0 2006.218.08:07:32.54#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.218.08:07:32.54#ibcon#[27=USB\r\n] 2006.218.08:07:32.54#ibcon#*before write, iclass 30, count 0 2006.218.08:07:32.54#ibcon#enter sib2, iclass 30, count 0 2006.218.08:07:32.54#ibcon#flushed, iclass 30, count 0 2006.218.08:07:32.54#ibcon#about to write, iclass 30, count 0 2006.218.08:07:32.54#ibcon#wrote, iclass 30, count 0 2006.218.08:07:32.54#ibcon#about to read 3, iclass 30, count 0 2006.218.08:07:32.57#ibcon#read 3, iclass 30, count 0 2006.218.08:07:32.57#ibcon#about to read 4, iclass 30, count 0 2006.218.08:07:32.57#ibcon#read 4, iclass 30, count 0 2006.218.08:07:32.57#ibcon#about to read 5, iclass 30, count 0 2006.218.08:07:32.57#ibcon#read 5, iclass 30, count 0 2006.218.08:07:32.57#ibcon#about to read 6, iclass 30, count 0 2006.218.08:07:32.57#ibcon#read 6, iclass 30, count 0 2006.218.08:07:32.57#ibcon#end of sib2, iclass 30, count 0 2006.218.08:07:32.57#ibcon#*after write, iclass 30, count 0 2006.218.08:07:32.57#ibcon#*before return 0, iclass 30, count 0 2006.218.08:07:32.57#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.218.08:07:32.57#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.218.08:07:32.57#ibcon#about to clear, iclass 30 cls_cnt 0 2006.218.08:07:32.57#ibcon#cleared, iclass 30 cls_cnt 0 2006.218.08:07:32.57$vc4f8/vabw=wide 2006.218.08:07:32.57#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.218.08:07:32.57#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.218.08:07:32.57#ibcon#ireg 8 cls_cnt 0 2006.218.08:07:32.57#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.218.08:07:32.57#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.218.08:07:32.57#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.218.08:07:32.57#ibcon#enter wrdev, iclass 32, count 0 2006.218.08:07:32.57#ibcon#first serial, iclass 32, count 0 2006.218.08:07:32.57#ibcon#enter sib2, iclass 32, count 0 2006.218.08:07:32.57#ibcon#flushed, iclass 32, count 0 2006.218.08:07:32.57#ibcon#about to write, iclass 32, count 0 2006.218.08:07:32.57#ibcon#wrote, iclass 32, count 0 2006.218.08:07:32.57#ibcon#about to read 3, iclass 32, count 0 2006.218.08:07:32.59#ibcon#read 3, iclass 32, count 0 2006.218.08:07:32.59#ibcon#about to read 4, iclass 32, count 0 2006.218.08:07:32.59#ibcon#read 4, iclass 32, count 0 2006.218.08:07:32.59#ibcon#about to read 5, iclass 32, count 0 2006.218.08:07:32.59#ibcon#read 5, iclass 32, count 0 2006.218.08:07:32.59#ibcon#about to read 6, iclass 32, count 0 2006.218.08:07:32.59#ibcon#read 6, iclass 32, count 0 2006.218.08:07:32.59#ibcon#end of sib2, iclass 32, count 0 2006.218.08:07:32.59#ibcon#*mode == 0, iclass 32, count 0 2006.218.08:07:32.59#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.218.08:07:32.59#ibcon#[25=BW32\r\n] 2006.218.08:07:32.59#ibcon#*before write, iclass 32, count 0 2006.218.08:07:32.59#ibcon#enter sib2, iclass 32, count 0 2006.218.08:07:32.59#ibcon#flushed, iclass 32, count 0 2006.218.08:07:32.59#ibcon#about to write, iclass 32, count 0 2006.218.08:07:32.59#ibcon#wrote, iclass 32, count 0 2006.218.08:07:32.59#ibcon#about to read 3, iclass 32, count 0 2006.218.08:07:32.62#ibcon#read 3, iclass 32, count 0 2006.218.08:07:32.62#ibcon#about to read 4, iclass 32, count 0 2006.218.08:07:32.62#ibcon#read 4, iclass 32, count 0 2006.218.08:07:32.62#ibcon#about to read 5, iclass 32, count 0 2006.218.08:07:32.62#ibcon#read 5, iclass 32, count 0 2006.218.08:07:32.62#ibcon#about to read 6, iclass 32, count 0 2006.218.08:07:32.62#ibcon#read 6, iclass 32, count 0 2006.218.08:07:32.62#ibcon#end of sib2, iclass 32, count 0 2006.218.08:07:32.62#ibcon#*after write, iclass 32, count 0 2006.218.08:07:32.62#ibcon#*before return 0, iclass 32, count 0 2006.218.08:07:32.62#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.218.08:07:32.62#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.218.08:07:32.62#ibcon#about to clear, iclass 32 cls_cnt 0 2006.218.08:07:32.62#ibcon#cleared, iclass 32 cls_cnt 0 2006.218.08:07:32.62$vc4f8/vbbw=wide 2006.218.08:07:32.62#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.218.08:07:32.62#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.218.08:07:32.62#ibcon#ireg 8 cls_cnt 0 2006.218.08:07:32.62#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.218.08:07:32.69#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.218.08:07:32.69#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.218.08:07:32.69#ibcon#enter wrdev, iclass 34, count 0 2006.218.08:07:32.69#ibcon#first serial, iclass 34, count 0 2006.218.08:07:32.69#ibcon#enter sib2, iclass 34, count 0 2006.218.08:07:32.69#ibcon#flushed, iclass 34, count 0 2006.218.08:07:32.69#ibcon#about to write, iclass 34, count 0 2006.218.08:07:32.69#ibcon#wrote, iclass 34, count 0 2006.218.08:07:32.69#ibcon#about to read 3, iclass 34, count 0 2006.218.08:07:32.71#ibcon#read 3, iclass 34, count 0 2006.218.08:07:32.71#ibcon#about to read 4, iclass 34, count 0 2006.218.08:07:32.71#ibcon#read 4, iclass 34, count 0 2006.218.08:07:32.71#ibcon#about to read 5, iclass 34, count 0 2006.218.08:07:32.71#ibcon#read 5, iclass 34, count 0 2006.218.08:07:32.71#ibcon#about to read 6, iclass 34, count 0 2006.218.08:07:32.71#ibcon#read 6, iclass 34, count 0 2006.218.08:07:32.71#ibcon#end of sib2, iclass 34, count 0 2006.218.08:07:32.71#ibcon#*mode == 0, iclass 34, count 0 2006.218.08:07:32.71#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.218.08:07:32.71#ibcon#[27=BW32\r\n] 2006.218.08:07:32.71#ibcon#*before write, iclass 34, count 0 2006.218.08:07:32.71#ibcon#enter sib2, iclass 34, count 0 2006.218.08:07:32.71#ibcon#flushed, iclass 34, count 0 2006.218.08:07:32.71#ibcon#about to write, iclass 34, count 0 2006.218.08:07:32.71#ibcon#wrote, iclass 34, count 0 2006.218.08:07:32.71#ibcon#about to read 3, iclass 34, count 0 2006.218.08:07:32.74#ibcon#read 3, iclass 34, count 0 2006.218.08:07:32.74#ibcon#about to read 4, iclass 34, count 0 2006.218.08:07:32.74#ibcon#read 4, iclass 34, count 0 2006.218.08:07:32.74#ibcon#about to read 5, iclass 34, count 0 2006.218.08:07:32.74#ibcon#read 5, iclass 34, count 0 2006.218.08:07:32.74#ibcon#about to read 6, iclass 34, count 0 2006.218.08:07:32.74#ibcon#read 6, iclass 34, count 0 2006.218.08:07:32.74#ibcon#end of sib2, iclass 34, count 0 2006.218.08:07:32.74#ibcon#*after write, iclass 34, count 0 2006.218.08:07:32.74#ibcon#*before return 0, iclass 34, count 0 2006.218.08:07:32.74#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.218.08:07:32.74#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.218.08:07:32.74#ibcon#about to clear, iclass 34 cls_cnt 0 2006.218.08:07:32.74#ibcon#cleared, iclass 34 cls_cnt 0 2006.218.08:07:32.74$4f8m12a/ifd4f 2006.218.08:07:32.74$ifd4f/lo= 2006.218.08:07:32.74$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.218.08:07:32.74$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.218.08:07:32.74$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.218.08:07:32.74$ifd4f/patch= 2006.218.08:07:32.74$ifd4f/patch=lo1,a1,a2,a3,a4 2006.218.08:07:32.74$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.218.08:07:32.74$ifd4f/patch=lo3,a5,a6,a7,a8 2006.218.08:07:32.74$4f8m12a/"form=m,16.000,1:2 2006.218.08:07:32.74$4f8m12a/"tpicd 2006.218.08:07:32.74$4f8m12a/echo=off 2006.218.08:07:32.74$4f8m12a/xlog=off 2006.218.08:07:32.74:!2006.218.08:08:00 2006.218.08:07:42.14#trakl#Source acquired 2006.218.08:07:42.14#flagr#flagr/antenna,acquired 2006.218.08:08:00.00:preob 2006.218.08:08:01.14/onsource/TRACKING 2006.218.08:08:01.14:!2006.218.08:08:10 2006.218.08:08:10.00:data_valid=on 2006.218.08:08:10.00:midob 2006.218.08:08:10.14/onsource/TRACKING 2006.218.08:08:10.14/wx/30.93,1007.5,72 2006.218.08:08:10.23/cable/+6.3843E-03 2006.218.08:08:11.32/va/01,05,usb,yes,32,33 2006.218.08:08:11.32/va/02,04,usb,yes,30,31 2006.218.08:08:11.32/va/03,04,usb,yes,28,28 2006.218.08:08:11.32/va/04,04,usb,yes,31,33 2006.218.08:08:11.32/va/05,07,usb,yes,33,35 2006.218.08:08:11.32/va/06,06,usb,yes,32,32 2006.218.08:08:11.32/va/07,06,usb,yes,33,32 2006.218.08:08:11.32/va/08,07,usb,yes,31,30 2006.218.08:08:11.55/valo/01,532.99,yes,locked 2006.218.08:08:11.55/valo/02,572.99,yes,locked 2006.218.08:08:11.55/valo/03,672.99,yes,locked 2006.218.08:08:11.55/valo/04,832.99,yes,locked 2006.218.08:08:11.55/valo/05,652.99,yes,locked 2006.218.08:08:11.55/valo/06,772.99,yes,locked 2006.218.08:08:11.55/valo/07,832.99,yes,locked 2006.218.08:08:11.55/valo/08,852.99,yes,locked 2006.218.08:08:12.64/vb/01,04,usb,yes,30,29 2006.218.08:08:12.64/vb/02,04,usb,yes,32,34 2006.218.08:08:12.64/vb/03,04,usb,yes,28,32 2006.218.08:08:12.64/vb/04,04,usb,yes,29,29 2006.218.08:08:12.64/vb/05,04,usb,yes,28,32 2006.218.08:08:12.64/vb/06,04,usb,yes,29,32 2006.218.08:08:12.64/vb/07,04,usb,yes,31,31 2006.218.08:08:12.64/vb/08,04,usb,yes,28,32 2006.218.08:08:12.87/vblo/01,632.99,yes,locked 2006.218.08:08:12.87/vblo/02,640.99,yes,locked 2006.218.08:08:12.87/vblo/03,656.99,yes,locked 2006.218.08:08:12.87/vblo/04,712.99,yes,locked 2006.218.08:08:12.87/vblo/05,744.99,yes,locked 2006.218.08:08:12.87/vblo/06,752.99,yes,locked 2006.218.08:08:12.87/vblo/07,734.99,yes,locked 2006.218.08:08:12.87/vblo/08,744.99,yes,locked 2006.218.08:08:13.02/vabw/8 2006.218.08:08:13.17/vbbw/8 2006.218.08:08:13.26/xfe/off,on,15.5 2006.218.08:08:13.64/ifatt/23,28,28,28 2006.218.08:08:14.07/fmout-gps/S +4.63E-07 2006.218.08:08:14.15:!2006.218.08:09:20 2006.218.08:09:20.01:data_valid=off 2006.218.08:09:20.01:postob 2006.218.08:09:20.11/cable/+6.3850E-03 2006.218.08:09:20.11/wx/30.91,1007.5,72 2006.218.08:09:21.07/fmout-gps/S +4.62E-07 2006.218.08:09:21.07:scan_name=218-0810,k06218,60 2006.218.08:09:21.08:source=0804+499,080839.67,495036.5,2000.0,cw 2006.218.08:09:22.14#flagr#flagr/antenna,new-source 2006.218.08:09:22.14:checkk5 2006.218.08:09:22.52/chk_autoobs//k5ts1/ autoobs is running! 2006.218.08:09:22.89/chk_autoobs//k5ts2/ autoobs is running! 2006.218.08:09:23.27/chk_autoobs//k5ts3/ autoobs is running! 2006.218.08:09:23.64/chk_autoobs//k5ts4/ autoobs is running! 2006.218.08:09:24.01/chk_obsdata//k5ts1/T2180808??a.dat file size is correct (nominal:560MB, actual:552MB). 2006.218.08:09:24.37/chk_obsdata//k5ts2/T2180808??b.dat file size is correct (nominal:560MB, actual:552MB). 2006.218.08:09:24.74/chk_obsdata//k5ts3/T2180808??c.dat file size is correct (nominal:560MB, actual:552MB). 2006.218.08:09:25.10/chk_obsdata//k5ts4/T2180808??d.dat file size is correct (nominal:560MB, actual:552MB). 2006.218.08:09:25.79/k5log//k5ts1_log_newline 2006.218.08:09:26.49/k5log//k5ts2_log_newline 2006.218.08:09:27.18/k5log//k5ts3_log_newline 2006.218.08:09:27.86/k5log//k5ts4_log_newline 2006.218.08:09:27.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.218.08:09:27.89:4f8m12a=2 2006.218.08:09:27.89$4f8m12a/echo=on 2006.218.08:09:27.89$4f8m12a/pcalon 2006.218.08:09:27.89$pcalon/"no phase cal control is implemented here 2006.218.08:09:27.89$4f8m12a/"tpicd=stop 2006.218.08:09:27.89$4f8m12a/vc4f8 2006.218.08:09:27.89$vc4f8/valo=1,532.99 2006.218.08:09:27.89#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.218.08:09:27.89#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.218.08:09:27.89#ibcon#ireg 17 cls_cnt 0 2006.218.08:09:27.89#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.218.08:09:27.89#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.218.08:09:27.89#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.218.08:09:27.89#ibcon#enter wrdev, iclass 7, count 0 2006.218.08:09:27.89#ibcon#first serial, iclass 7, count 0 2006.218.08:09:27.89#ibcon#enter sib2, iclass 7, count 0 2006.218.08:09:27.89#ibcon#flushed, iclass 7, count 0 2006.218.08:09:27.89#ibcon#about to write, iclass 7, count 0 2006.218.08:09:27.89#ibcon#wrote, iclass 7, count 0 2006.218.08:09:27.89#ibcon#about to read 3, iclass 7, count 0 2006.218.08:09:27.93#ibcon#read 3, iclass 7, count 0 2006.218.08:09:27.93#ibcon#about to read 4, iclass 7, count 0 2006.218.08:09:27.93#ibcon#read 4, iclass 7, count 0 2006.218.08:09:27.93#ibcon#about to read 5, iclass 7, count 0 2006.218.08:09:27.93#ibcon#read 5, iclass 7, count 0 2006.218.08:09:27.93#ibcon#about to read 6, iclass 7, count 0 2006.218.08:09:27.93#ibcon#read 6, iclass 7, count 0 2006.218.08:09:27.93#ibcon#end of sib2, iclass 7, count 0 2006.218.08:09:27.93#ibcon#*mode == 0, iclass 7, count 0 2006.218.08:09:27.93#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.218.08:09:27.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.218.08:09:27.93#ibcon#*before write, iclass 7, count 0 2006.218.08:09:27.93#ibcon#enter sib2, iclass 7, count 0 2006.218.08:09:27.93#ibcon#flushed, iclass 7, count 0 2006.218.08:09:27.93#ibcon#about to write, iclass 7, count 0 2006.218.08:09:27.93#ibcon#wrote, iclass 7, count 0 2006.218.08:09:27.93#ibcon#about to read 3, iclass 7, count 0 2006.218.08:09:27.98#ibcon#read 3, iclass 7, count 0 2006.218.08:09:27.98#ibcon#about to read 4, iclass 7, count 0 2006.218.08:09:27.98#ibcon#read 4, iclass 7, count 0 2006.218.08:09:27.98#ibcon#about to read 5, iclass 7, count 0 2006.218.08:09:27.98#ibcon#read 5, iclass 7, count 0 2006.218.08:09:27.98#ibcon#about to read 6, iclass 7, count 0 2006.218.08:09:27.98#ibcon#read 6, iclass 7, count 0 2006.218.08:09:27.98#ibcon#end of sib2, iclass 7, count 0 2006.218.08:09:27.98#ibcon#*after write, iclass 7, count 0 2006.218.08:09:27.98#ibcon#*before return 0, iclass 7, count 0 2006.218.08:09:27.98#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.218.08:09:27.98#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.218.08:09:27.98#ibcon#about to clear, iclass 7 cls_cnt 0 2006.218.08:09:27.98#ibcon#cleared, iclass 7 cls_cnt 0 2006.218.08:09:27.98$vc4f8/va=1,5 2006.218.08:09:27.98#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.218.08:09:27.98#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.218.08:09:27.98#ibcon#ireg 11 cls_cnt 2 2006.218.08:09:27.98#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.218.08:09:27.98#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.218.08:09:27.98#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.218.08:09:27.98#ibcon#enter wrdev, iclass 11, count 2 2006.218.08:09:27.98#ibcon#first serial, iclass 11, count 2 2006.218.08:09:27.98#ibcon#enter sib2, iclass 11, count 2 2006.218.08:09:27.98#ibcon#flushed, iclass 11, count 2 2006.218.08:09:27.98#ibcon#about to write, iclass 11, count 2 2006.218.08:09:27.98#ibcon#wrote, iclass 11, count 2 2006.218.08:09:27.98#ibcon#about to read 3, iclass 11, count 2 2006.218.08:09:28.01#ibcon#read 3, iclass 11, count 2 2006.218.08:09:28.01#ibcon#about to read 4, iclass 11, count 2 2006.218.08:09:28.01#ibcon#read 4, iclass 11, count 2 2006.218.08:09:28.01#ibcon#about to read 5, iclass 11, count 2 2006.218.08:09:28.01#ibcon#read 5, iclass 11, count 2 2006.218.08:09:28.01#ibcon#about to read 6, iclass 11, count 2 2006.218.08:09:28.01#ibcon#read 6, iclass 11, count 2 2006.218.08:09:28.01#ibcon#end of sib2, iclass 11, count 2 2006.218.08:09:28.01#ibcon#*mode == 0, iclass 11, count 2 2006.218.08:09:28.01#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.218.08:09:28.01#ibcon#[25=AT01-05\r\n] 2006.218.08:09:28.01#ibcon#*before write, iclass 11, count 2 2006.218.08:09:28.01#ibcon#enter sib2, iclass 11, count 2 2006.218.08:09:28.01#ibcon#flushed, iclass 11, count 2 2006.218.08:09:28.01#ibcon#about to write, iclass 11, count 2 2006.218.08:09:28.01#ibcon#wrote, iclass 11, count 2 2006.218.08:09:28.01#ibcon#about to read 3, iclass 11, count 2 2006.218.08:09:28.04#ibcon#read 3, iclass 11, count 2 2006.218.08:09:28.04#ibcon#about to read 4, iclass 11, count 2 2006.218.08:09:28.04#ibcon#read 4, iclass 11, count 2 2006.218.08:09:28.04#ibcon#about to read 5, iclass 11, count 2 2006.218.08:09:28.04#ibcon#read 5, iclass 11, count 2 2006.218.08:09:28.04#ibcon#about to read 6, iclass 11, count 2 2006.218.08:09:28.04#ibcon#read 6, iclass 11, count 2 2006.218.08:09:28.04#ibcon#end of sib2, iclass 11, count 2 2006.218.08:09:28.04#ibcon#*after write, iclass 11, count 2 2006.218.08:09:28.04#ibcon#*before return 0, iclass 11, count 2 2006.218.08:09:28.04#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.218.08:09:28.04#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.218.08:09:28.04#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.218.08:09:28.04#ibcon#ireg 7 cls_cnt 0 2006.218.08:09:28.04#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.218.08:09:28.16#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.218.08:09:28.16#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.218.08:09:28.16#ibcon#enter wrdev, iclass 11, count 0 2006.218.08:09:28.16#ibcon#first serial, iclass 11, count 0 2006.218.08:09:28.16#ibcon#enter sib2, iclass 11, count 0 2006.218.08:09:28.16#ibcon#flushed, iclass 11, count 0 2006.218.08:09:28.16#ibcon#about to write, iclass 11, count 0 2006.218.08:09:28.16#ibcon#wrote, iclass 11, count 0 2006.218.08:09:28.16#ibcon#about to read 3, iclass 11, count 0 2006.218.08:09:28.18#ibcon#read 3, iclass 11, count 0 2006.218.08:09:28.18#ibcon#about to read 4, iclass 11, count 0 2006.218.08:09:28.18#ibcon#read 4, iclass 11, count 0 2006.218.08:09:28.18#ibcon#about to read 5, iclass 11, count 0 2006.218.08:09:28.18#ibcon#read 5, iclass 11, count 0 2006.218.08:09:28.18#ibcon#about to read 6, iclass 11, count 0 2006.218.08:09:28.18#ibcon#read 6, iclass 11, count 0 2006.218.08:09:28.18#ibcon#end of sib2, iclass 11, count 0 2006.218.08:09:28.18#ibcon#*mode == 0, iclass 11, count 0 2006.218.08:09:28.18#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.218.08:09:28.18#ibcon#[25=USB\r\n] 2006.218.08:09:28.18#ibcon#*before write, iclass 11, count 0 2006.218.08:09:28.18#ibcon#enter sib2, iclass 11, count 0 2006.218.08:09:28.18#ibcon#flushed, iclass 11, count 0 2006.218.08:09:28.18#ibcon#about to write, iclass 11, count 0 2006.218.08:09:28.18#ibcon#wrote, iclass 11, count 0 2006.218.08:09:28.18#ibcon#about to read 3, iclass 11, count 0 2006.218.08:09:28.21#ibcon#read 3, iclass 11, count 0 2006.218.08:09:28.21#ibcon#about to read 4, iclass 11, count 0 2006.218.08:09:28.21#ibcon#read 4, iclass 11, count 0 2006.218.08:09:28.21#ibcon#about to read 5, iclass 11, count 0 2006.218.08:09:28.21#ibcon#read 5, iclass 11, count 0 2006.218.08:09:28.21#ibcon#about to read 6, iclass 11, count 0 2006.218.08:09:28.21#ibcon#read 6, iclass 11, count 0 2006.218.08:09:28.21#ibcon#end of sib2, iclass 11, count 0 2006.218.08:09:28.21#ibcon#*after write, iclass 11, count 0 2006.218.08:09:28.21#ibcon#*before return 0, iclass 11, count 0 2006.218.08:09:28.21#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.218.08:09:28.21#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.218.08:09:28.21#ibcon#about to clear, iclass 11 cls_cnt 0 2006.218.08:09:28.21#ibcon#cleared, iclass 11 cls_cnt 0 2006.218.08:09:28.21$vc4f8/valo=2,572.99 2006.218.08:09:28.21#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.218.08:09:28.21#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.218.08:09:28.21#ibcon#ireg 17 cls_cnt 0 2006.218.08:09:28.21#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.218.08:09:28.21#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.218.08:09:28.21#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.218.08:09:28.21#ibcon#enter wrdev, iclass 13, count 0 2006.218.08:09:28.21#ibcon#first serial, iclass 13, count 0 2006.218.08:09:28.21#ibcon#enter sib2, iclass 13, count 0 2006.218.08:09:28.21#ibcon#flushed, iclass 13, count 0 2006.218.08:09:28.21#ibcon#about to write, iclass 13, count 0 2006.218.08:09:28.21#ibcon#wrote, iclass 13, count 0 2006.218.08:09:28.21#ibcon#about to read 3, iclass 13, count 0 2006.218.08:09:28.23#ibcon#read 3, iclass 13, count 0 2006.218.08:09:28.23#ibcon#about to read 4, iclass 13, count 0 2006.218.08:09:28.23#ibcon#read 4, iclass 13, count 0 2006.218.08:09:28.23#ibcon#about to read 5, iclass 13, count 0 2006.218.08:09:28.23#ibcon#read 5, iclass 13, count 0 2006.218.08:09:28.23#ibcon#about to read 6, iclass 13, count 0 2006.218.08:09:28.23#ibcon#read 6, iclass 13, count 0 2006.218.08:09:28.23#ibcon#end of sib2, iclass 13, count 0 2006.218.08:09:28.23#ibcon#*mode == 0, iclass 13, count 0 2006.218.08:09:28.23#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.218.08:09:28.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.218.08:09:28.23#ibcon#*before write, iclass 13, count 0 2006.218.08:09:28.23#ibcon#enter sib2, iclass 13, count 0 2006.218.08:09:28.23#ibcon#flushed, iclass 13, count 0 2006.218.08:09:28.23#ibcon#about to write, iclass 13, count 0 2006.218.08:09:28.23#ibcon#wrote, iclass 13, count 0 2006.218.08:09:28.23#ibcon#about to read 3, iclass 13, count 0 2006.218.08:09:28.27#ibcon#read 3, iclass 13, count 0 2006.218.08:09:28.27#ibcon#about to read 4, iclass 13, count 0 2006.218.08:09:28.27#ibcon#read 4, iclass 13, count 0 2006.218.08:09:28.27#ibcon#about to read 5, iclass 13, count 0 2006.218.08:09:28.27#ibcon#read 5, iclass 13, count 0 2006.218.08:09:28.27#ibcon#about to read 6, iclass 13, count 0 2006.218.08:09:28.27#ibcon#read 6, iclass 13, count 0 2006.218.08:09:28.27#ibcon#end of sib2, iclass 13, count 0 2006.218.08:09:28.27#ibcon#*after write, iclass 13, count 0 2006.218.08:09:28.27#ibcon#*before return 0, iclass 13, count 0 2006.218.08:09:28.27#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.218.08:09:28.27#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.218.08:09:28.27#ibcon#about to clear, iclass 13 cls_cnt 0 2006.218.08:09:28.27#ibcon#cleared, iclass 13 cls_cnt 0 2006.218.08:09:28.27$vc4f8/va=2,4 2006.218.08:09:28.27#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.218.08:09:28.27#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.218.08:09:28.27#ibcon#ireg 11 cls_cnt 2 2006.218.08:09:28.27#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.218.08:09:28.33#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.218.08:09:28.33#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.218.08:09:28.33#ibcon#enter wrdev, iclass 15, count 2 2006.218.08:09:28.33#ibcon#first serial, iclass 15, count 2 2006.218.08:09:28.33#ibcon#enter sib2, iclass 15, count 2 2006.218.08:09:28.33#ibcon#flushed, iclass 15, count 2 2006.218.08:09:28.33#ibcon#about to write, iclass 15, count 2 2006.218.08:09:28.33#ibcon#wrote, iclass 15, count 2 2006.218.08:09:28.33#ibcon#about to read 3, iclass 15, count 2 2006.218.08:09:28.35#ibcon#read 3, iclass 15, count 2 2006.218.08:09:28.35#ibcon#about to read 4, iclass 15, count 2 2006.218.08:09:28.35#ibcon#read 4, iclass 15, count 2 2006.218.08:09:28.35#ibcon#about to read 5, iclass 15, count 2 2006.218.08:09:28.35#ibcon#read 5, iclass 15, count 2 2006.218.08:09:28.35#ibcon#about to read 6, iclass 15, count 2 2006.218.08:09:28.35#ibcon#read 6, iclass 15, count 2 2006.218.08:09:28.35#ibcon#end of sib2, iclass 15, count 2 2006.218.08:09:28.35#ibcon#*mode == 0, iclass 15, count 2 2006.218.08:09:28.35#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.218.08:09:28.35#ibcon#[25=AT02-04\r\n] 2006.218.08:09:28.35#ibcon#*before write, iclass 15, count 2 2006.218.08:09:28.35#ibcon#enter sib2, iclass 15, count 2 2006.218.08:09:28.35#ibcon#flushed, iclass 15, count 2 2006.218.08:09:28.35#ibcon#about to write, iclass 15, count 2 2006.218.08:09:28.35#ibcon#wrote, iclass 15, count 2 2006.218.08:09:28.35#ibcon#about to read 3, iclass 15, count 2 2006.218.08:09:28.39#ibcon#read 3, iclass 15, count 2 2006.218.08:09:28.39#ibcon#about to read 4, iclass 15, count 2 2006.218.08:09:28.39#ibcon#read 4, iclass 15, count 2 2006.218.08:09:28.39#ibcon#about to read 5, iclass 15, count 2 2006.218.08:09:28.39#ibcon#read 5, iclass 15, count 2 2006.218.08:09:28.39#ibcon#about to read 6, iclass 15, count 2 2006.218.08:09:28.39#ibcon#read 6, iclass 15, count 2 2006.218.08:09:28.39#ibcon#end of sib2, iclass 15, count 2 2006.218.08:09:28.39#ibcon#*after write, iclass 15, count 2 2006.218.08:09:28.39#ibcon#*before return 0, iclass 15, count 2 2006.218.08:09:28.39#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.218.08:09:28.39#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.218.08:09:28.39#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.218.08:09:28.39#ibcon#ireg 7 cls_cnt 0 2006.218.08:09:28.39#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.218.08:09:28.50#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.218.08:09:28.50#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.218.08:09:28.50#ibcon#enter wrdev, iclass 15, count 0 2006.218.08:09:28.50#ibcon#first serial, iclass 15, count 0 2006.218.08:09:28.50#ibcon#enter sib2, iclass 15, count 0 2006.218.08:09:28.50#ibcon#flushed, iclass 15, count 0 2006.218.08:09:28.50#ibcon#about to write, iclass 15, count 0 2006.218.08:09:28.50#ibcon#wrote, iclass 15, count 0 2006.218.08:09:28.50#ibcon#about to read 3, iclass 15, count 0 2006.218.08:09:28.52#ibcon#read 3, iclass 15, count 0 2006.218.08:09:28.52#ibcon#about to read 4, iclass 15, count 0 2006.218.08:09:28.52#ibcon#read 4, iclass 15, count 0 2006.218.08:09:28.52#ibcon#about to read 5, iclass 15, count 0 2006.218.08:09:28.52#ibcon#read 5, iclass 15, count 0 2006.218.08:09:28.52#ibcon#about to read 6, iclass 15, count 0 2006.218.08:09:28.52#ibcon#read 6, iclass 15, count 0 2006.218.08:09:28.52#ibcon#end of sib2, iclass 15, count 0 2006.218.08:09:28.52#ibcon#*mode == 0, iclass 15, count 0 2006.218.08:09:28.52#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.218.08:09:28.52#ibcon#[25=USB\r\n] 2006.218.08:09:28.52#ibcon#*before write, iclass 15, count 0 2006.218.08:09:28.52#ibcon#enter sib2, iclass 15, count 0 2006.218.08:09:28.52#ibcon#flushed, iclass 15, count 0 2006.218.08:09:28.52#ibcon#about to write, iclass 15, count 0 2006.218.08:09:28.52#ibcon#wrote, iclass 15, count 0 2006.218.08:09:28.52#ibcon#about to read 3, iclass 15, count 0 2006.218.08:09:28.55#ibcon#read 3, iclass 15, count 0 2006.218.08:09:28.55#ibcon#about to read 4, iclass 15, count 0 2006.218.08:09:28.55#ibcon#read 4, iclass 15, count 0 2006.218.08:09:28.55#ibcon#about to read 5, iclass 15, count 0 2006.218.08:09:28.55#ibcon#read 5, iclass 15, count 0 2006.218.08:09:28.55#ibcon#about to read 6, iclass 15, count 0 2006.218.08:09:28.55#ibcon#read 6, iclass 15, count 0 2006.218.08:09:28.55#ibcon#end of sib2, iclass 15, count 0 2006.218.08:09:28.55#ibcon#*after write, iclass 15, count 0 2006.218.08:09:28.55#ibcon#*before return 0, iclass 15, count 0 2006.218.08:09:28.55#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.218.08:09:28.55#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.218.08:09:28.55#ibcon#about to clear, iclass 15 cls_cnt 0 2006.218.08:09:28.55#ibcon#cleared, iclass 15 cls_cnt 0 2006.218.08:09:28.55$vc4f8/valo=3,672.99 2006.218.08:09:28.55#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.218.08:09:28.55#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.218.08:09:28.55#ibcon#ireg 17 cls_cnt 0 2006.218.08:09:28.55#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.218.08:09:28.55#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.218.08:09:28.55#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.218.08:09:28.55#ibcon#enter wrdev, iclass 17, count 0 2006.218.08:09:28.55#ibcon#first serial, iclass 17, count 0 2006.218.08:09:28.55#ibcon#enter sib2, iclass 17, count 0 2006.218.08:09:28.55#ibcon#flushed, iclass 17, count 0 2006.218.08:09:28.55#ibcon#about to write, iclass 17, count 0 2006.218.08:09:28.55#ibcon#wrote, iclass 17, count 0 2006.218.08:09:28.55#ibcon#about to read 3, iclass 17, count 0 2006.218.08:09:28.58#ibcon#read 3, iclass 17, count 0 2006.218.08:09:28.58#ibcon#about to read 4, iclass 17, count 0 2006.218.08:09:28.58#ibcon#read 4, iclass 17, count 0 2006.218.08:09:28.58#ibcon#about to read 5, iclass 17, count 0 2006.218.08:09:28.58#ibcon#read 5, iclass 17, count 0 2006.218.08:09:28.58#ibcon#about to read 6, iclass 17, count 0 2006.218.08:09:28.58#ibcon#read 6, iclass 17, count 0 2006.218.08:09:28.58#ibcon#end of sib2, iclass 17, count 0 2006.218.08:09:28.58#ibcon#*mode == 0, iclass 17, count 0 2006.218.08:09:28.58#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.218.08:09:28.58#ibcon#[26=FRQ=03,672.99\r\n] 2006.218.08:09:28.58#ibcon#*before write, iclass 17, count 0 2006.218.08:09:28.58#ibcon#enter sib2, iclass 17, count 0 2006.218.08:09:28.58#ibcon#flushed, iclass 17, count 0 2006.218.08:09:28.58#ibcon#about to write, iclass 17, count 0 2006.218.08:09:28.58#ibcon#wrote, iclass 17, count 0 2006.218.08:09:28.58#ibcon#about to read 3, iclass 17, count 0 2006.218.08:09:28.62#ibcon#read 3, iclass 17, count 0 2006.218.08:09:28.62#ibcon#about to read 4, iclass 17, count 0 2006.218.08:09:28.62#ibcon#read 4, iclass 17, count 0 2006.218.08:09:28.62#ibcon#about to read 5, iclass 17, count 0 2006.218.08:09:28.62#ibcon#read 5, iclass 17, count 0 2006.218.08:09:28.62#ibcon#about to read 6, iclass 17, count 0 2006.218.08:09:28.62#ibcon#read 6, iclass 17, count 0 2006.218.08:09:28.62#ibcon#end of sib2, iclass 17, count 0 2006.218.08:09:28.62#ibcon#*after write, iclass 17, count 0 2006.218.08:09:28.62#ibcon#*before return 0, iclass 17, count 0 2006.218.08:09:28.62#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.218.08:09:28.62#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.218.08:09:28.62#ibcon#about to clear, iclass 17 cls_cnt 0 2006.218.08:09:28.62#ibcon#cleared, iclass 17 cls_cnt 0 2006.218.08:09:28.62$vc4f8/va=3,4 2006.218.08:09:28.62#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.218.08:09:28.62#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.218.08:09:28.62#ibcon#ireg 11 cls_cnt 2 2006.218.08:09:28.62#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.218.08:09:28.67#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.218.08:09:28.67#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.218.08:09:28.67#ibcon#enter wrdev, iclass 19, count 2 2006.218.08:09:28.67#ibcon#first serial, iclass 19, count 2 2006.218.08:09:28.67#ibcon#enter sib2, iclass 19, count 2 2006.218.08:09:28.67#ibcon#flushed, iclass 19, count 2 2006.218.08:09:28.67#ibcon#about to write, iclass 19, count 2 2006.218.08:09:28.67#ibcon#wrote, iclass 19, count 2 2006.218.08:09:28.67#ibcon#about to read 3, iclass 19, count 2 2006.218.08:09:28.69#ibcon#read 3, iclass 19, count 2 2006.218.08:09:28.69#ibcon#about to read 4, iclass 19, count 2 2006.218.08:09:28.69#ibcon#read 4, iclass 19, count 2 2006.218.08:09:28.69#ibcon#about to read 5, iclass 19, count 2 2006.218.08:09:28.69#ibcon#read 5, iclass 19, count 2 2006.218.08:09:28.69#ibcon#about to read 6, iclass 19, count 2 2006.218.08:09:28.69#ibcon#read 6, iclass 19, count 2 2006.218.08:09:28.69#ibcon#end of sib2, iclass 19, count 2 2006.218.08:09:28.69#ibcon#*mode == 0, iclass 19, count 2 2006.218.08:09:28.69#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.218.08:09:28.69#ibcon#[25=AT03-04\r\n] 2006.218.08:09:28.69#ibcon#*before write, iclass 19, count 2 2006.218.08:09:28.69#ibcon#enter sib2, iclass 19, count 2 2006.218.08:09:28.69#ibcon#flushed, iclass 19, count 2 2006.218.08:09:28.69#ibcon#about to write, iclass 19, count 2 2006.218.08:09:28.69#ibcon#wrote, iclass 19, count 2 2006.218.08:09:28.69#ibcon#about to read 3, iclass 19, count 2 2006.218.08:09:28.72#ibcon#read 3, iclass 19, count 2 2006.218.08:09:28.72#ibcon#about to read 4, iclass 19, count 2 2006.218.08:09:28.72#ibcon#read 4, iclass 19, count 2 2006.218.08:09:28.72#ibcon#about to read 5, iclass 19, count 2 2006.218.08:09:28.72#ibcon#read 5, iclass 19, count 2 2006.218.08:09:28.72#ibcon#about to read 6, iclass 19, count 2 2006.218.08:09:28.72#ibcon#read 6, iclass 19, count 2 2006.218.08:09:28.72#ibcon#end of sib2, iclass 19, count 2 2006.218.08:09:28.72#ibcon#*after write, iclass 19, count 2 2006.218.08:09:28.72#ibcon#*before return 0, iclass 19, count 2 2006.218.08:09:28.72#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.218.08:09:28.72#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.218.08:09:28.72#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.218.08:09:28.72#ibcon#ireg 7 cls_cnt 0 2006.218.08:09:28.72#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.218.08:09:28.84#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.218.08:09:28.84#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.218.08:09:28.84#ibcon#enter wrdev, iclass 19, count 0 2006.218.08:09:28.84#ibcon#first serial, iclass 19, count 0 2006.218.08:09:28.84#ibcon#enter sib2, iclass 19, count 0 2006.218.08:09:28.84#ibcon#flushed, iclass 19, count 0 2006.218.08:09:28.84#ibcon#about to write, iclass 19, count 0 2006.218.08:09:28.84#ibcon#wrote, iclass 19, count 0 2006.218.08:09:28.84#ibcon#about to read 3, iclass 19, count 0 2006.218.08:09:28.86#ibcon#read 3, iclass 19, count 0 2006.218.08:09:28.86#ibcon#about to read 4, iclass 19, count 0 2006.218.08:09:28.86#ibcon#read 4, iclass 19, count 0 2006.218.08:09:28.86#ibcon#about to read 5, iclass 19, count 0 2006.218.08:09:28.86#ibcon#read 5, iclass 19, count 0 2006.218.08:09:28.86#ibcon#about to read 6, iclass 19, count 0 2006.218.08:09:28.86#ibcon#read 6, iclass 19, count 0 2006.218.08:09:28.86#ibcon#end of sib2, iclass 19, count 0 2006.218.08:09:28.86#ibcon#*mode == 0, iclass 19, count 0 2006.218.08:09:28.86#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.218.08:09:28.86#ibcon#[25=USB\r\n] 2006.218.08:09:28.86#ibcon#*before write, iclass 19, count 0 2006.218.08:09:28.86#ibcon#enter sib2, iclass 19, count 0 2006.218.08:09:28.86#ibcon#flushed, iclass 19, count 0 2006.218.08:09:28.86#ibcon#about to write, iclass 19, count 0 2006.218.08:09:28.86#ibcon#wrote, iclass 19, count 0 2006.218.08:09:28.86#ibcon#about to read 3, iclass 19, count 0 2006.218.08:09:28.89#ibcon#read 3, iclass 19, count 0 2006.218.08:09:28.89#ibcon#about to read 4, iclass 19, count 0 2006.218.08:09:28.89#ibcon#read 4, iclass 19, count 0 2006.218.08:09:28.89#ibcon#about to read 5, iclass 19, count 0 2006.218.08:09:28.89#ibcon#read 5, iclass 19, count 0 2006.218.08:09:28.89#ibcon#about to read 6, iclass 19, count 0 2006.218.08:09:28.89#ibcon#read 6, iclass 19, count 0 2006.218.08:09:28.89#ibcon#end of sib2, iclass 19, count 0 2006.218.08:09:28.89#ibcon#*after write, iclass 19, count 0 2006.218.08:09:28.89#ibcon#*before return 0, iclass 19, count 0 2006.218.08:09:28.89#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.218.08:09:28.89#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.218.08:09:28.89#ibcon#about to clear, iclass 19 cls_cnt 0 2006.218.08:09:28.89#ibcon#cleared, iclass 19 cls_cnt 0 2006.218.08:09:28.89$vc4f8/valo=4,832.99 2006.218.08:09:28.89#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.218.08:09:28.89#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.218.08:09:28.89#ibcon#ireg 17 cls_cnt 0 2006.218.08:09:28.89#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.218.08:09:28.89#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.218.08:09:28.89#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.218.08:09:28.89#ibcon#enter wrdev, iclass 21, count 0 2006.218.08:09:28.89#ibcon#first serial, iclass 21, count 0 2006.218.08:09:28.89#ibcon#enter sib2, iclass 21, count 0 2006.218.08:09:28.89#ibcon#flushed, iclass 21, count 0 2006.218.08:09:28.89#ibcon#about to write, iclass 21, count 0 2006.218.08:09:28.89#ibcon#wrote, iclass 21, count 0 2006.218.08:09:28.89#ibcon#about to read 3, iclass 21, count 0 2006.218.08:09:28.91#ibcon#read 3, iclass 21, count 0 2006.218.08:09:28.91#ibcon#about to read 4, iclass 21, count 0 2006.218.08:09:28.91#ibcon#read 4, iclass 21, count 0 2006.218.08:09:28.91#ibcon#about to read 5, iclass 21, count 0 2006.218.08:09:28.91#ibcon#read 5, iclass 21, count 0 2006.218.08:09:28.91#ibcon#about to read 6, iclass 21, count 0 2006.218.08:09:28.91#ibcon#read 6, iclass 21, count 0 2006.218.08:09:28.91#ibcon#end of sib2, iclass 21, count 0 2006.218.08:09:28.91#ibcon#*mode == 0, iclass 21, count 0 2006.218.08:09:28.91#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.218.08:09:28.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.218.08:09:28.91#ibcon#*before write, iclass 21, count 0 2006.218.08:09:28.91#ibcon#enter sib2, iclass 21, count 0 2006.218.08:09:28.91#ibcon#flushed, iclass 21, count 0 2006.218.08:09:28.91#ibcon#about to write, iclass 21, count 0 2006.218.08:09:28.91#ibcon#wrote, iclass 21, count 0 2006.218.08:09:28.91#ibcon#about to read 3, iclass 21, count 0 2006.218.08:09:28.95#ibcon#read 3, iclass 21, count 0 2006.218.08:09:28.95#ibcon#about to read 4, iclass 21, count 0 2006.218.08:09:28.95#ibcon#read 4, iclass 21, count 0 2006.218.08:09:28.95#ibcon#about to read 5, iclass 21, count 0 2006.218.08:09:28.95#ibcon#read 5, iclass 21, count 0 2006.218.08:09:28.95#ibcon#about to read 6, iclass 21, count 0 2006.218.08:09:28.95#ibcon#read 6, iclass 21, count 0 2006.218.08:09:28.95#ibcon#end of sib2, iclass 21, count 0 2006.218.08:09:28.95#ibcon#*after write, iclass 21, count 0 2006.218.08:09:28.95#ibcon#*before return 0, iclass 21, count 0 2006.218.08:09:28.95#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.218.08:09:28.95#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.218.08:09:28.95#ibcon#about to clear, iclass 21 cls_cnt 0 2006.218.08:09:28.95#ibcon#cleared, iclass 21 cls_cnt 0 2006.218.08:09:28.95$vc4f8/va=4,4 2006.218.08:09:28.95#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.218.08:09:28.95#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.218.08:09:28.95#ibcon#ireg 11 cls_cnt 2 2006.218.08:09:28.95#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.218.08:09:29.01#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.218.08:09:29.01#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.218.08:09:29.01#ibcon#enter wrdev, iclass 23, count 2 2006.218.08:09:29.01#ibcon#first serial, iclass 23, count 2 2006.218.08:09:29.01#ibcon#enter sib2, iclass 23, count 2 2006.218.08:09:29.01#ibcon#flushed, iclass 23, count 2 2006.218.08:09:29.01#ibcon#about to write, iclass 23, count 2 2006.218.08:09:29.01#ibcon#wrote, iclass 23, count 2 2006.218.08:09:29.01#ibcon#about to read 3, iclass 23, count 2 2006.218.08:09:29.03#ibcon#read 3, iclass 23, count 2 2006.218.08:09:29.03#ibcon#about to read 4, iclass 23, count 2 2006.218.08:09:29.03#ibcon#read 4, iclass 23, count 2 2006.218.08:09:29.03#ibcon#about to read 5, iclass 23, count 2 2006.218.08:09:29.03#ibcon#read 5, iclass 23, count 2 2006.218.08:09:29.03#ibcon#about to read 6, iclass 23, count 2 2006.218.08:09:29.03#ibcon#read 6, iclass 23, count 2 2006.218.08:09:29.03#ibcon#end of sib2, iclass 23, count 2 2006.218.08:09:29.03#ibcon#*mode == 0, iclass 23, count 2 2006.218.08:09:29.03#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.218.08:09:29.03#ibcon#[25=AT04-04\r\n] 2006.218.08:09:29.03#ibcon#*before write, iclass 23, count 2 2006.218.08:09:29.03#ibcon#enter sib2, iclass 23, count 2 2006.218.08:09:29.03#ibcon#flushed, iclass 23, count 2 2006.218.08:09:29.03#ibcon#about to write, iclass 23, count 2 2006.218.08:09:29.03#ibcon#wrote, iclass 23, count 2 2006.218.08:09:29.03#ibcon#about to read 3, iclass 23, count 2 2006.218.08:09:29.06#ibcon#read 3, iclass 23, count 2 2006.218.08:09:29.06#ibcon#about to read 4, iclass 23, count 2 2006.218.08:09:29.06#ibcon#read 4, iclass 23, count 2 2006.218.08:09:29.06#ibcon#about to read 5, iclass 23, count 2 2006.218.08:09:29.06#ibcon#read 5, iclass 23, count 2 2006.218.08:09:29.06#ibcon#about to read 6, iclass 23, count 2 2006.218.08:09:29.06#ibcon#read 6, iclass 23, count 2 2006.218.08:09:29.06#ibcon#end of sib2, iclass 23, count 2 2006.218.08:09:29.06#ibcon#*after write, iclass 23, count 2 2006.218.08:09:29.06#ibcon#*before return 0, iclass 23, count 2 2006.218.08:09:29.06#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.218.08:09:29.06#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.218.08:09:29.06#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.218.08:09:29.06#ibcon#ireg 7 cls_cnt 0 2006.218.08:09:29.06#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.218.08:09:29.18#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.218.08:09:29.18#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.218.08:09:29.18#ibcon#enter wrdev, iclass 23, count 0 2006.218.08:09:29.18#ibcon#first serial, iclass 23, count 0 2006.218.08:09:29.18#ibcon#enter sib2, iclass 23, count 0 2006.218.08:09:29.18#ibcon#flushed, iclass 23, count 0 2006.218.08:09:29.18#ibcon#about to write, iclass 23, count 0 2006.218.08:09:29.18#ibcon#wrote, iclass 23, count 0 2006.218.08:09:29.18#ibcon#about to read 3, iclass 23, count 0 2006.218.08:09:29.20#ibcon#read 3, iclass 23, count 0 2006.218.08:09:29.20#ibcon#about to read 4, iclass 23, count 0 2006.218.08:09:29.20#ibcon#read 4, iclass 23, count 0 2006.218.08:09:29.20#ibcon#about to read 5, iclass 23, count 0 2006.218.08:09:29.20#ibcon#read 5, iclass 23, count 0 2006.218.08:09:29.20#ibcon#about to read 6, iclass 23, count 0 2006.218.08:09:29.20#ibcon#read 6, iclass 23, count 0 2006.218.08:09:29.20#ibcon#end of sib2, iclass 23, count 0 2006.218.08:09:29.20#ibcon#*mode == 0, iclass 23, count 0 2006.218.08:09:29.20#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.218.08:09:29.20#ibcon#[25=USB\r\n] 2006.218.08:09:29.20#ibcon#*before write, iclass 23, count 0 2006.218.08:09:29.20#ibcon#enter sib2, iclass 23, count 0 2006.218.08:09:29.20#ibcon#flushed, iclass 23, count 0 2006.218.08:09:29.20#ibcon#about to write, iclass 23, count 0 2006.218.08:09:29.20#ibcon#wrote, iclass 23, count 0 2006.218.08:09:29.20#ibcon#about to read 3, iclass 23, count 0 2006.218.08:09:29.23#ibcon#read 3, iclass 23, count 0 2006.218.08:09:29.23#ibcon#about to read 4, iclass 23, count 0 2006.218.08:09:29.23#ibcon#read 4, iclass 23, count 0 2006.218.08:09:29.23#ibcon#about to read 5, iclass 23, count 0 2006.218.08:09:29.23#ibcon#read 5, iclass 23, count 0 2006.218.08:09:29.23#ibcon#about to read 6, iclass 23, count 0 2006.218.08:09:29.23#ibcon#read 6, iclass 23, count 0 2006.218.08:09:29.23#ibcon#end of sib2, iclass 23, count 0 2006.218.08:09:29.23#ibcon#*after write, iclass 23, count 0 2006.218.08:09:29.23#ibcon#*before return 0, iclass 23, count 0 2006.218.08:09:29.23#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.218.08:09:29.23#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.218.08:09:29.23#ibcon#about to clear, iclass 23 cls_cnt 0 2006.218.08:09:29.23#ibcon#cleared, iclass 23 cls_cnt 0 2006.218.08:09:29.23$vc4f8/valo=5,652.99 2006.218.08:09:29.23#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.218.08:09:29.23#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.218.08:09:29.23#ibcon#ireg 17 cls_cnt 0 2006.218.08:09:29.23#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.218.08:09:29.23#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.218.08:09:29.23#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.218.08:09:29.23#ibcon#enter wrdev, iclass 25, count 0 2006.218.08:09:29.23#ibcon#first serial, iclass 25, count 0 2006.218.08:09:29.23#ibcon#enter sib2, iclass 25, count 0 2006.218.08:09:29.23#ibcon#flushed, iclass 25, count 0 2006.218.08:09:29.23#ibcon#about to write, iclass 25, count 0 2006.218.08:09:29.23#ibcon#wrote, iclass 25, count 0 2006.218.08:09:29.23#ibcon#about to read 3, iclass 25, count 0 2006.218.08:09:29.25#ibcon#read 3, iclass 25, count 0 2006.218.08:09:29.25#ibcon#about to read 4, iclass 25, count 0 2006.218.08:09:29.25#ibcon#read 4, iclass 25, count 0 2006.218.08:09:29.25#ibcon#about to read 5, iclass 25, count 0 2006.218.08:09:29.25#ibcon#read 5, iclass 25, count 0 2006.218.08:09:29.25#ibcon#about to read 6, iclass 25, count 0 2006.218.08:09:29.25#ibcon#read 6, iclass 25, count 0 2006.218.08:09:29.25#ibcon#end of sib2, iclass 25, count 0 2006.218.08:09:29.25#ibcon#*mode == 0, iclass 25, count 0 2006.218.08:09:29.25#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.218.08:09:29.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.218.08:09:29.25#ibcon#*before write, iclass 25, count 0 2006.218.08:09:29.25#ibcon#enter sib2, iclass 25, count 0 2006.218.08:09:29.25#ibcon#flushed, iclass 25, count 0 2006.218.08:09:29.25#ibcon#about to write, iclass 25, count 0 2006.218.08:09:29.25#ibcon#wrote, iclass 25, count 0 2006.218.08:09:29.25#ibcon#about to read 3, iclass 25, count 0 2006.218.08:09:29.29#ibcon#read 3, iclass 25, count 0 2006.218.08:09:29.29#ibcon#about to read 4, iclass 25, count 0 2006.218.08:09:29.29#ibcon#read 4, iclass 25, count 0 2006.218.08:09:29.29#ibcon#about to read 5, iclass 25, count 0 2006.218.08:09:29.29#ibcon#read 5, iclass 25, count 0 2006.218.08:09:29.29#ibcon#about to read 6, iclass 25, count 0 2006.218.08:09:29.29#ibcon#read 6, iclass 25, count 0 2006.218.08:09:29.29#ibcon#end of sib2, iclass 25, count 0 2006.218.08:09:29.29#ibcon#*after write, iclass 25, count 0 2006.218.08:09:29.29#ibcon#*before return 0, iclass 25, count 0 2006.218.08:09:29.29#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.218.08:09:29.29#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.218.08:09:29.29#ibcon#about to clear, iclass 25 cls_cnt 0 2006.218.08:09:29.29#ibcon#cleared, iclass 25 cls_cnt 0 2006.218.08:09:29.29$vc4f8/va=5,7 2006.218.08:09:29.29#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.218.08:09:29.29#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.218.08:09:29.29#ibcon#ireg 11 cls_cnt 2 2006.218.08:09:29.29#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.218.08:09:29.35#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.218.08:09:29.35#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.218.08:09:29.35#ibcon#enter wrdev, iclass 27, count 2 2006.218.08:09:29.35#ibcon#first serial, iclass 27, count 2 2006.218.08:09:29.35#ibcon#enter sib2, iclass 27, count 2 2006.218.08:09:29.35#ibcon#flushed, iclass 27, count 2 2006.218.08:09:29.35#ibcon#about to write, iclass 27, count 2 2006.218.08:09:29.35#ibcon#wrote, iclass 27, count 2 2006.218.08:09:29.35#ibcon#about to read 3, iclass 27, count 2 2006.218.08:09:29.37#ibcon#read 3, iclass 27, count 2 2006.218.08:09:29.37#ibcon#about to read 4, iclass 27, count 2 2006.218.08:09:29.37#ibcon#read 4, iclass 27, count 2 2006.218.08:09:29.37#ibcon#about to read 5, iclass 27, count 2 2006.218.08:09:29.37#ibcon#read 5, iclass 27, count 2 2006.218.08:09:29.37#ibcon#about to read 6, iclass 27, count 2 2006.218.08:09:29.37#ibcon#read 6, iclass 27, count 2 2006.218.08:09:29.37#ibcon#end of sib2, iclass 27, count 2 2006.218.08:09:29.37#ibcon#*mode == 0, iclass 27, count 2 2006.218.08:09:29.37#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.218.08:09:29.37#ibcon#[25=AT05-07\r\n] 2006.218.08:09:29.37#ibcon#*before write, iclass 27, count 2 2006.218.08:09:29.37#ibcon#enter sib2, iclass 27, count 2 2006.218.08:09:29.37#ibcon#flushed, iclass 27, count 2 2006.218.08:09:29.37#ibcon#about to write, iclass 27, count 2 2006.218.08:09:29.37#ibcon#wrote, iclass 27, count 2 2006.218.08:09:29.37#ibcon#about to read 3, iclass 27, count 2 2006.218.08:09:29.40#ibcon#read 3, iclass 27, count 2 2006.218.08:09:29.40#ibcon#about to read 4, iclass 27, count 2 2006.218.08:09:29.40#ibcon#read 4, iclass 27, count 2 2006.218.08:09:29.40#ibcon#about to read 5, iclass 27, count 2 2006.218.08:09:29.40#ibcon#read 5, iclass 27, count 2 2006.218.08:09:29.40#ibcon#about to read 6, iclass 27, count 2 2006.218.08:09:29.40#ibcon#read 6, iclass 27, count 2 2006.218.08:09:29.40#ibcon#end of sib2, iclass 27, count 2 2006.218.08:09:29.40#ibcon#*after write, iclass 27, count 2 2006.218.08:09:29.40#ibcon#*before return 0, iclass 27, count 2 2006.218.08:09:29.40#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.218.08:09:29.40#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.218.08:09:29.40#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.218.08:09:29.40#ibcon#ireg 7 cls_cnt 0 2006.218.08:09:29.40#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.218.08:09:29.52#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.218.08:09:29.52#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.218.08:09:29.52#ibcon#enter wrdev, iclass 27, count 0 2006.218.08:09:29.52#ibcon#first serial, iclass 27, count 0 2006.218.08:09:29.52#ibcon#enter sib2, iclass 27, count 0 2006.218.08:09:29.52#ibcon#flushed, iclass 27, count 0 2006.218.08:09:29.52#ibcon#about to write, iclass 27, count 0 2006.218.08:09:29.52#ibcon#wrote, iclass 27, count 0 2006.218.08:09:29.52#ibcon#about to read 3, iclass 27, count 0 2006.218.08:09:29.54#ibcon#read 3, iclass 27, count 0 2006.218.08:09:29.54#ibcon#about to read 4, iclass 27, count 0 2006.218.08:09:29.54#ibcon#read 4, iclass 27, count 0 2006.218.08:09:29.54#ibcon#about to read 5, iclass 27, count 0 2006.218.08:09:29.54#ibcon#read 5, iclass 27, count 0 2006.218.08:09:29.54#ibcon#about to read 6, iclass 27, count 0 2006.218.08:09:29.54#ibcon#read 6, iclass 27, count 0 2006.218.08:09:29.54#ibcon#end of sib2, iclass 27, count 0 2006.218.08:09:29.54#ibcon#*mode == 0, iclass 27, count 0 2006.218.08:09:29.54#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.218.08:09:29.54#ibcon#[25=USB\r\n] 2006.218.08:09:29.54#ibcon#*before write, iclass 27, count 0 2006.218.08:09:29.54#ibcon#enter sib2, iclass 27, count 0 2006.218.08:09:29.54#ibcon#flushed, iclass 27, count 0 2006.218.08:09:29.54#ibcon#about to write, iclass 27, count 0 2006.218.08:09:29.54#ibcon#wrote, iclass 27, count 0 2006.218.08:09:29.54#ibcon#about to read 3, iclass 27, count 0 2006.218.08:09:29.57#ibcon#read 3, iclass 27, count 0 2006.218.08:09:29.57#ibcon#about to read 4, iclass 27, count 0 2006.218.08:09:29.57#ibcon#read 4, iclass 27, count 0 2006.218.08:09:29.57#ibcon#about to read 5, iclass 27, count 0 2006.218.08:09:29.57#ibcon#read 5, iclass 27, count 0 2006.218.08:09:29.57#ibcon#about to read 6, iclass 27, count 0 2006.218.08:09:29.57#ibcon#read 6, iclass 27, count 0 2006.218.08:09:29.57#ibcon#end of sib2, iclass 27, count 0 2006.218.08:09:29.57#ibcon#*after write, iclass 27, count 0 2006.218.08:09:29.57#ibcon#*before return 0, iclass 27, count 0 2006.218.08:09:29.57#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.218.08:09:29.57#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.218.08:09:29.57#ibcon#about to clear, iclass 27 cls_cnt 0 2006.218.08:09:29.57#ibcon#cleared, iclass 27 cls_cnt 0 2006.218.08:09:29.57$vc4f8/valo=6,772.99 2006.218.08:09:29.57#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.218.08:09:29.57#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.218.08:09:29.57#ibcon#ireg 17 cls_cnt 0 2006.218.08:09:29.57#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.218.08:09:29.57#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.218.08:09:29.57#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.218.08:09:29.57#ibcon#enter wrdev, iclass 29, count 0 2006.218.08:09:29.57#ibcon#first serial, iclass 29, count 0 2006.218.08:09:29.57#ibcon#enter sib2, iclass 29, count 0 2006.218.08:09:29.57#ibcon#flushed, iclass 29, count 0 2006.218.08:09:29.57#ibcon#about to write, iclass 29, count 0 2006.218.08:09:29.57#ibcon#wrote, iclass 29, count 0 2006.218.08:09:29.57#ibcon#about to read 3, iclass 29, count 0 2006.218.08:09:29.59#ibcon#read 3, iclass 29, count 0 2006.218.08:09:29.59#ibcon#about to read 4, iclass 29, count 0 2006.218.08:09:29.59#ibcon#read 4, iclass 29, count 0 2006.218.08:09:29.59#ibcon#about to read 5, iclass 29, count 0 2006.218.08:09:29.59#ibcon#read 5, iclass 29, count 0 2006.218.08:09:29.59#ibcon#about to read 6, iclass 29, count 0 2006.218.08:09:29.59#ibcon#read 6, iclass 29, count 0 2006.218.08:09:29.59#ibcon#end of sib2, iclass 29, count 0 2006.218.08:09:29.59#ibcon#*mode == 0, iclass 29, count 0 2006.218.08:09:29.59#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.218.08:09:29.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.218.08:09:29.59#ibcon#*before write, iclass 29, count 0 2006.218.08:09:29.59#ibcon#enter sib2, iclass 29, count 0 2006.218.08:09:29.59#ibcon#flushed, iclass 29, count 0 2006.218.08:09:29.59#ibcon#about to write, iclass 29, count 0 2006.218.08:09:29.59#ibcon#wrote, iclass 29, count 0 2006.218.08:09:29.59#ibcon#about to read 3, iclass 29, count 0 2006.218.08:09:29.63#ibcon#read 3, iclass 29, count 0 2006.218.08:09:29.63#ibcon#about to read 4, iclass 29, count 0 2006.218.08:09:29.63#ibcon#read 4, iclass 29, count 0 2006.218.08:09:29.63#ibcon#about to read 5, iclass 29, count 0 2006.218.08:09:29.63#ibcon#read 5, iclass 29, count 0 2006.218.08:09:29.63#ibcon#about to read 6, iclass 29, count 0 2006.218.08:09:29.63#ibcon#read 6, iclass 29, count 0 2006.218.08:09:29.63#ibcon#end of sib2, iclass 29, count 0 2006.218.08:09:29.63#ibcon#*after write, iclass 29, count 0 2006.218.08:09:29.63#ibcon#*before return 0, iclass 29, count 0 2006.218.08:09:29.63#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.218.08:09:29.63#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.218.08:09:29.63#ibcon#about to clear, iclass 29 cls_cnt 0 2006.218.08:09:29.63#ibcon#cleared, iclass 29 cls_cnt 0 2006.218.08:09:29.63$vc4f8/va=6,6 2006.218.08:09:29.63#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.218.08:09:29.63#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.218.08:09:29.63#ibcon#ireg 11 cls_cnt 2 2006.218.08:09:29.63#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.218.08:09:29.69#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.218.08:09:29.69#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.218.08:09:29.69#ibcon#enter wrdev, iclass 31, count 2 2006.218.08:09:29.69#ibcon#first serial, iclass 31, count 2 2006.218.08:09:29.69#ibcon#enter sib2, iclass 31, count 2 2006.218.08:09:29.69#ibcon#flushed, iclass 31, count 2 2006.218.08:09:29.69#ibcon#about to write, iclass 31, count 2 2006.218.08:09:29.69#ibcon#wrote, iclass 31, count 2 2006.218.08:09:29.69#ibcon#about to read 3, iclass 31, count 2 2006.218.08:09:29.71#ibcon#read 3, iclass 31, count 2 2006.218.08:09:29.71#ibcon#about to read 4, iclass 31, count 2 2006.218.08:09:29.71#ibcon#read 4, iclass 31, count 2 2006.218.08:09:29.71#ibcon#about to read 5, iclass 31, count 2 2006.218.08:09:29.71#ibcon#read 5, iclass 31, count 2 2006.218.08:09:29.71#ibcon#about to read 6, iclass 31, count 2 2006.218.08:09:29.71#ibcon#read 6, iclass 31, count 2 2006.218.08:09:29.71#ibcon#end of sib2, iclass 31, count 2 2006.218.08:09:29.71#ibcon#*mode == 0, iclass 31, count 2 2006.218.08:09:29.71#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.218.08:09:29.71#ibcon#[25=AT06-06\r\n] 2006.218.08:09:29.71#ibcon#*before write, iclass 31, count 2 2006.218.08:09:29.71#ibcon#enter sib2, iclass 31, count 2 2006.218.08:09:29.71#ibcon#flushed, iclass 31, count 2 2006.218.08:09:29.71#ibcon#about to write, iclass 31, count 2 2006.218.08:09:29.71#ibcon#wrote, iclass 31, count 2 2006.218.08:09:29.71#ibcon#about to read 3, iclass 31, count 2 2006.218.08:09:29.74#ibcon#read 3, iclass 31, count 2 2006.218.08:09:29.74#ibcon#about to read 4, iclass 31, count 2 2006.218.08:09:29.74#ibcon#read 4, iclass 31, count 2 2006.218.08:09:29.74#ibcon#about to read 5, iclass 31, count 2 2006.218.08:09:29.74#ibcon#read 5, iclass 31, count 2 2006.218.08:09:29.74#ibcon#about to read 6, iclass 31, count 2 2006.218.08:09:29.74#ibcon#read 6, iclass 31, count 2 2006.218.08:09:29.74#ibcon#end of sib2, iclass 31, count 2 2006.218.08:09:29.74#ibcon#*after write, iclass 31, count 2 2006.218.08:09:29.74#ibcon#*before return 0, iclass 31, count 2 2006.218.08:09:29.74#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.218.08:09:29.74#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.218.08:09:29.74#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.218.08:09:29.74#ibcon#ireg 7 cls_cnt 0 2006.218.08:09:29.74#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.218.08:09:29.86#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.218.08:09:29.86#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.218.08:09:29.86#ibcon#enter wrdev, iclass 31, count 0 2006.218.08:09:29.86#ibcon#first serial, iclass 31, count 0 2006.218.08:09:29.86#ibcon#enter sib2, iclass 31, count 0 2006.218.08:09:29.86#ibcon#flushed, iclass 31, count 0 2006.218.08:09:29.86#ibcon#about to write, iclass 31, count 0 2006.218.08:09:29.86#ibcon#wrote, iclass 31, count 0 2006.218.08:09:29.86#ibcon#about to read 3, iclass 31, count 0 2006.218.08:09:29.88#ibcon#read 3, iclass 31, count 0 2006.218.08:09:29.88#ibcon#about to read 4, iclass 31, count 0 2006.218.08:09:29.88#ibcon#read 4, iclass 31, count 0 2006.218.08:09:29.88#ibcon#about to read 5, iclass 31, count 0 2006.218.08:09:29.88#ibcon#read 5, iclass 31, count 0 2006.218.08:09:29.88#ibcon#about to read 6, iclass 31, count 0 2006.218.08:09:29.88#ibcon#read 6, iclass 31, count 0 2006.218.08:09:29.88#ibcon#end of sib2, iclass 31, count 0 2006.218.08:09:29.88#ibcon#*mode == 0, iclass 31, count 0 2006.218.08:09:29.88#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.218.08:09:29.88#ibcon#[25=USB\r\n] 2006.218.08:09:29.88#ibcon#*before write, iclass 31, count 0 2006.218.08:09:29.88#ibcon#enter sib2, iclass 31, count 0 2006.218.08:09:29.88#ibcon#flushed, iclass 31, count 0 2006.218.08:09:29.88#ibcon#about to write, iclass 31, count 0 2006.218.08:09:29.88#ibcon#wrote, iclass 31, count 0 2006.218.08:09:29.88#ibcon#about to read 3, iclass 31, count 0 2006.218.08:09:29.91#ibcon#read 3, iclass 31, count 0 2006.218.08:09:29.91#ibcon#about to read 4, iclass 31, count 0 2006.218.08:09:29.91#ibcon#read 4, iclass 31, count 0 2006.218.08:09:29.91#ibcon#about to read 5, iclass 31, count 0 2006.218.08:09:29.91#ibcon#read 5, iclass 31, count 0 2006.218.08:09:29.91#ibcon#about to read 6, iclass 31, count 0 2006.218.08:09:29.91#ibcon#read 6, iclass 31, count 0 2006.218.08:09:29.91#ibcon#end of sib2, iclass 31, count 0 2006.218.08:09:29.91#ibcon#*after write, iclass 31, count 0 2006.218.08:09:29.91#ibcon#*before return 0, iclass 31, count 0 2006.218.08:09:29.91#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.218.08:09:29.91#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.218.08:09:29.91#ibcon#about to clear, iclass 31 cls_cnt 0 2006.218.08:09:29.91#ibcon#cleared, iclass 31 cls_cnt 0 2006.218.08:09:29.91$vc4f8/valo=7,832.99 2006.218.08:09:29.91#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.218.08:09:29.91#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.218.08:09:29.91#ibcon#ireg 17 cls_cnt 0 2006.218.08:09:29.91#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.218.08:09:29.91#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.218.08:09:29.91#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.218.08:09:29.91#ibcon#enter wrdev, iclass 33, count 0 2006.218.08:09:29.91#ibcon#first serial, iclass 33, count 0 2006.218.08:09:29.91#ibcon#enter sib2, iclass 33, count 0 2006.218.08:09:29.91#ibcon#flushed, iclass 33, count 0 2006.218.08:09:29.91#ibcon#about to write, iclass 33, count 0 2006.218.08:09:29.91#ibcon#wrote, iclass 33, count 0 2006.218.08:09:29.91#ibcon#about to read 3, iclass 33, count 0 2006.218.08:09:29.93#ibcon#read 3, iclass 33, count 0 2006.218.08:09:29.93#ibcon#about to read 4, iclass 33, count 0 2006.218.08:09:29.93#ibcon#read 4, iclass 33, count 0 2006.218.08:09:29.93#ibcon#about to read 5, iclass 33, count 0 2006.218.08:09:29.93#ibcon#read 5, iclass 33, count 0 2006.218.08:09:29.93#ibcon#about to read 6, iclass 33, count 0 2006.218.08:09:29.93#ibcon#read 6, iclass 33, count 0 2006.218.08:09:29.93#ibcon#end of sib2, iclass 33, count 0 2006.218.08:09:29.93#ibcon#*mode == 0, iclass 33, count 0 2006.218.08:09:29.93#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.218.08:09:29.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.218.08:09:29.93#ibcon#*before write, iclass 33, count 0 2006.218.08:09:29.93#ibcon#enter sib2, iclass 33, count 0 2006.218.08:09:29.93#ibcon#flushed, iclass 33, count 0 2006.218.08:09:29.93#ibcon#about to write, iclass 33, count 0 2006.218.08:09:29.93#ibcon#wrote, iclass 33, count 0 2006.218.08:09:29.93#ibcon#about to read 3, iclass 33, count 0 2006.218.08:09:29.97#ibcon#read 3, iclass 33, count 0 2006.218.08:09:29.97#ibcon#about to read 4, iclass 33, count 0 2006.218.08:09:29.97#ibcon#read 4, iclass 33, count 0 2006.218.08:09:29.97#ibcon#about to read 5, iclass 33, count 0 2006.218.08:09:29.97#ibcon#read 5, iclass 33, count 0 2006.218.08:09:29.97#ibcon#about to read 6, iclass 33, count 0 2006.218.08:09:29.97#ibcon#read 6, iclass 33, count 0 2006.218.08:09:29.97#ibcon#end of sib2, iclass 33, count 0 2006.218.08:09:29.97#ibcon#*after write, iclass 33, count 0 2006.218.08:09:29.97#ibcon#*before return 0, iclass 33, count 0 2006.218.08:09:29.97#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.218.08:09:29.97#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.218.08:09:29.97#ibcon#about to clear, iclass 33 cls_cnt 0 2006.218.08:09:29.97#ibcon#cleared, iclass 33 cls_cnt 0 2006.218.08:09:29.97$vc4f8/va=7,6 2006.218.08:09:29.97#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.218.08:09:29.97#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.218.08:09:29.97#ibcon#ireg 11 cls_cnt 2 2006.218.08:09:29.97#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.218.08:09:30.03#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.218.08:09:30.03#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.218.08:09:30.03#ibcon#enter wrdev, iclass 35, count 2 2006.218.08:09:30.03#ibcon#first serial, iclass 35, count 2 2006.218.08:09:30.03#ibcon#enter sib2, iclass 35, count 2 2006.218.08:09:30.03#ibcon#flushed, iclass 35, count 2 2006.218.08:09:30.03#ibcon#about to write, iclass 35, count 2 2006.218.08:09:30.03#ibcon#wrote, iclass 35, count 2 2006.218.08:09:30.03#ibcon#about to read 3, iclass 35, count 2 2006.218.08:09:30.05#ibcon#read 3, iclass 35, count 2 2006.218.08:09:30.05#ibcon#about to read 4, iclass 35, count 2 2006.218.08:09:30.05#ibcon#read 4, iclass 35, count 2 2006.218.08:09:30.05#ibcon#about to read 5, iclass 35, count 2 2006.218.08:09:30.05#ibcon#read 5, iclass 35, count 2 2006.218.08:09:30.05#ibcon#about to read 6, iclass 35, count 2 2006.218.08:09:30.05#ibcon#read 6, iclass 35, count 2 2006.218.08:09:30.05#ibcon#end of sib2, iclass 35, count 2 2006.218.08:09:30.05#ibcon#*mode == 0, iclass 35, count 2 2006.218.08:09:30.05#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.218.08:09:30.05#ibcon#[25=AT07-06\r\n] 2006.218.08:09:30.05#ibcon#*before write, iclass 35, count 2 2006.218.08:09:30.05#ibcon#enter sib2, iclass 35, count 2 2006.218.08:09:30.05#ibcon#flushed, iclass 35, count 2 2006.218.08:09:30.05#ibcon#about to write, iclass 35, count 2 2006.218.08:09:30.05#ibcon#wrote, iclass 35, count 2 2006.218.08:09:30.05#ibcon#about to read 3, iclass 35, count 2 2006.218.08:09:30.08#ibcon#read 3, iclass 35, count 2 2006.218.08:09:30.08#ibcon#about to read 4, iclass 35, count 2 2006.218.08:09:30.08#ibcon#read 4, iclass 35, count 2 2006.218.08:09:30.08#ibcon#about to read 5, iclass 35, count 2 2006.218.08:09:30.08#ibcon#read 5, iclass 35, count 2 2006.218.08:09:30.08#ibcon#about to read 6, iclass 35, count 2 2006.218.08:09:30.08#ibcon#read 6, iclass 35, count 2 2006.218.08:09:30.08#ibcon#end of sib2, iclass 35, count 2 2006.218.08:09:30.08#ibcon#*after write, iclass 35, count 2 2006.218.08:09:30.08#ibcon#*before return 0, iclass 35, count 2 2006.218.08:09:30.08#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.218.08:09:30.08#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.218.08:09:30.08#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.218.08:09:30.08#ibcon#ireg 7 cls_cnt 0 2006.218.08:09:30.08#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.218.08:09:30.20#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.218.08:09:30.20#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.218.08:09:30.20#ibcon#enter wrdev, iclass 35, count 0 2006.218.08:09:30.20#ibcon#first serial, iclass 35, count 0 2006.218.08:09:30.20#ibcon#enter sib2, iclass 35, count 0 2006.218.08:09:30.20#ibcon#flushed, iclass 35, count 0 2006.218.08:09:30.20#ibcon#about to write, iclass 35, count 0 2006.218.08:09:30.20#ibcon#wrote, iclass 35, count 0 2006.218.08:09:30.20#ibcon#about to read 3, iclass 35, count 0 2006.218.08:09:30.22#ibcon#read 3, iclass 35, count 0 2006.218.08:09:30.22#ibcon#about to read 4, iclass 35, count 0 2006.218.08:09:30.22#ibcon#read 4, iclass 35, count 0 2006.218.08:09:30.22#ibcon#about to read 5, iclass 35, count 0 2006.218.08:09:30.22#ibcon#read 5, iclass 35, count 0 2006.218.08:09:30.22#ibcon#about to read 6, iclass 35, count 0 2006.218.08:09:30.22#ibcon#read 6, iclass 35, count 0 2006.218.08:09:30.22#ibcon#end of sib2, iclass 35, count 0 2006.218.08:09:30.22#ibcon#*mode == 0, iclass 35, count 0 2006.218.08:09:30.22#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.218.08:09:30.22#ibcon#[25=USB\r\n] 2006.218.08:09:30.22#ibcon#*before write, iclass 35, count 0 2006.218.08:09:30.22#ibcon#enter sib2, iclass 35, count 0 2006.218.08:09:30.22#ibcon#flushed, iclass 35, count 0 2006.218.08:09:30.22#ibcon#about to write, iclass 35, count 0 2006.218.08:09:30.22#ibcon#wrote, iclass 35, count 0 2006.218.08:09:30.22#ibcon#about to read 3, iclass 35, count 0 2006.218.08:09:30.25#ibcon#read 3, iclass 35, count 0 2006.218.08:09:30.25#ibcon#about to read 4, iclass 35, count 0 2006.218.08:09:30.25#ibcon#read 4, iclass 35, count 0 2006.218.08:09:30.25#ibcon#about to read 5, iclass 35, count 0 2006.218.08:09:30.25#ibcon#read 5, iclass 35, count 0 2006.218.08:09:30.25#ibcon#about to read 6, iclass 35, count 0 2006.218.08:09:30.25#ibcon#read 6, iclass 35, count 0 2006.218.08:09:30.25#ibcon#end of sib2, iclass 35, count 0 2006.218.08:09:30.25#ibcon#*after write, iclass 35, count 0 2006.218.08:09:30.25#ibcon#*before return 0, iclass 35, count 0 2006.218.08:09:30.25#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.218.08:09:30.25#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.218.08:09:30.25#ibcon#about to clear, iclass 35 cls_cnt 0 2006.218.08:09:30.25#ibcon#cleared, iclass 35 cls_cnt 0 2006.218.08:09:30.25$vc4f8/valo=8,852.99 2006.218.08:09:30.25#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.218.08:09:30.25#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.218.08:09:30.25#ibcon#ireg 17 cls_cnt 0 2006.218.08:09:30.25#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.218.08:09:30.25#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.218.08:09:30.25#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.218.08:09:30.25#ibcon#enter wrdev, iclass 37, count 0 2006.218.08:09:30.25#ibcon#first serial, iclass 37, count 0 2006.218.08:09:30.25#ibcon#enter sib2, iclass 37, count 0 2006.218.08:09:30.25#ibcon#flushed, iclass 37, count 0 2006.218.08:09:30.25#ibcon#about to write, iclass 37, count 0 2006.218.08:09:30.25#ibcon#wrote, iclass 37, count 0 2006.218.08:09:30.25#ibcon#about to read 3, iclass 37, count 0 2006.218.08:09:30.27#ibcon#read 3, iclass 37, count 0 2006.218.08:09:30.27#ibcon#about to read 4, iclass 37, count 0 2006.218.08:09:30.27#ibcon#read 4, iclass 37, count 0 2006.218.08:09:30.27#ibcon#about to read 5, iclass 37, count 0 2006.218.08:09:30.27#ibcon#read 5, iclass 37, count 0 2006.218.08:09:30.27#ibcon#about to read 6, iclass 37, count 0 2006.218.08:09:30.27#ibcon#read 6, iclass 37, count 0 2006.218.08:09:30.27#ibcon#end of sib2, iclass 37, count 0 2006.218.08:09:30.27#ibcon#*mode == 0, iclass 37, count 0 2006.218.08:09:30.27#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.218.08:09:30.27#ibcon#[26=FRQ=08,852.99\r\n] 2006.218.08:09:30.27#ibcon#*before write, iclass 37, count 0 2006.218.08:09:30.27#ibcon#enter sib2, iclass 37, count 0 2006.218.08:09:30.27#ibcon#flushed, iclass 37, count 0 2006.218.08:09:30.27#ibcon#about to write, iclass 37, count 0 2006.218.08:09:30.27#ibcon#wrote, iclass 37, count 0 2006.218.08:09:30.27#ibcon#about to read 3, iclass 37, count 0 2006.218.08:09:30.32#ibcon#read 3, iclass 37, count 0 2006.218.08:09:30.32#ibcon#about to read 4, iclass 37, count 0 2006.218.08:09:30.32#ibcon#read 4, iclass 37, count 0 2006.218.08:09:30.32#ibcon#about to read 5, iclass 37, count 0 2006.218.08:09:30.32#ibcon#read 5, iclass 37, count 0 2006.218.08:09:30.32#ibcon#about to read 6, iclass 37, count 0 2006.218.08:09:30.32#ibcon#read 6, iclass 37, count 0 2006.218.08:09:30.32#ibcon#end of sib2, iclass 37, count 0 2006.218.08:09:30.32#ibcon#*after write, iclass 37, count 0 2006.218.08:09:30.32#ibcon#*before return 0, iclass 37, count 0 2006.218.08:09:30.32#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.218.08:09:30.32#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.218.08:09:30.32#ibcon#about to clear, iclass 37 cls_cnt 0 2006.218.08:09:30.32#ibcon#cleared, iclass 37 cls_cnt 0 2006.218.08:09:30.32$vc4f8/va=8,7 2006.218.08:09:30.32#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.218.08:09:30.32#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.218.08:09:30.32#ibcon#ireg 11 cls_cnt 2 2006.218.08:09:30.32#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.218.08:09:30.36#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.218.08:09:30.36#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.218.08:09:30.36#ibcon#enter wrdev, iclass 39, count 2 2006.218.08:09:30.36#ibcon#first serial, iclass 39, count 2 2006.218.08:09:30.36#ibcon#enter sib2, iclass 39, count 2 2006.218.08:09:30.36#ibcon#flushed, iclass 39, count 2 2006.218.08:09:30.36#ibcon#about to write, iclass 39, count 2 2006.218.08:09:30.36#ibcon#wrote, iclass 39, count 2 2006.218.08:09:30.36#ibcon#about to read 3, iclass 39, count 2 2006.218.08:09:30.38#ibcon#read 3, iclass 39, count 2 2006.218.08:09:30.38#ibcon#about to read 4, iclass 39, count 2 2006.218.08:09:30.38#ibcon#read 4, iclass 39, count 2 2006.218.08:09:30.38#ibcon#about to read 5, iclass 39, count 2 2006.218.08:09:30.38#ibcon#read 5, iclass 39, count 2 2006.218.08:09:30.38#ibcon#about to read 6, iclass 39, count 2 2006.218.08:09:30.38#ibcon#read 6, iclass 39, count 2 2006.218.08:09:30.38#ibcon#end of sib2, iclass 39, count 2 2006.218.08:09:30.38#ibcon#*mode == 0, iclass 39, count 2 2006.218.08:09:30.38#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.218.08:09:30.38#ibcon#[25=AT08-07\r\n] 2006.218.08:09:30.38#ibcon#*before write, iclass 39, count 2 2006.218.08:09:30.38#ibcon#enter sib2, iclass 39, count 2 2006.218.08:09:30.38#ibcon#flushed, iclass 39, count 2 2006.218.08:09:30.38#ibcon#about to write, iclass 39, count 2 2006.218.08:09:30.38#ibcon#wrote, iclass 39, count 2 2006.218.08:09:30.38#ibcon#about to read 3, iclass 39, count 2 2006.218.08:09:30.41#ibcon#read 3, iclass 39, count 2 2006.218.08:09:30.41#ibcon#about to read 4, iclass 39, count 2 2006.218.08:09:30.41#ibcon#read 4, iclass 39, count 2 2006.218.08:09:30.41#ibcon#about to read 5, iclass 39, count 2 2006.218.08:09:30.41#ibcon#read 5, iclass 39, count 2 2006.218.08:09:30.41#ibcon#about to read 6, iclass 39, count 2 2006.218.08:09:30.41#ibcon#read 6, iclass 39, count 2 2006.218.08:09:30.41#ibcon#end of sib2, iclass 39, count 2 2006.218.08:09:30.41#ibcon#*after write, iclass 39, count 2 2006.218.08:09:30.41#ibcon#*before return 0, iclass 39, count 2 2006.218.08:09:30.41#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.218.08:09:30.41#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.218.08:09:30.41#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.218.08:09:30.41#ibcon#ireg 7 cls_cnt 0 2006.218.08:09:30.41#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.218.08:09:30.53#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.218.08:09:30.53#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.218.08:09:30.53#ibcon#enter wrdev, iclass 39, count 0 2006.218.08:09:30.53#ibcon#first serial, iclass 39, count 0 2006.218.08:09:30.53#ibcon#enter sib2, iclass 39, count 0 2006.218.08:09:30.53#ibcon#flushed, iclass 39, count 0 2006.218.08:09:30.53#ibcon#about to write, iclass 39, count 0 2006.218.08:09:30.53#ibcon#wrote, iclass 39, count 0 2006.218.08:09:30.53#ibcon#about to read 3, iclass 39, count 0 2006.218.08:09:30.55#ibcon#read 3, iclass 39, count 0 2006.218.08:09:30.55#ibcon#about to read 4, iclass 39, count 0 2006.218.08:09:30.55#ibcon#read 4, iclass 39, count 0 2006.218.08:09:30.55#ibcon#about to read 5, iclass 39, count 0 2006.218.08:09:30.55#ibcon#read 5, iclass 39, count 0 2006.218.08:09:30.55#ibcon#about to read 6, iclass 39, count 0 2006.218.08:09:30.55#ibcon#read 6, iclass 39, count 0 2006.218.08:09:30.55#ibcon#end of sib2, iclass 39, count 0 2006.218.08:09:30.55#ibcon#*mode == 0, iclass 39, count 0 2006.218.08:09:30.55#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.218.08:09:30.55#ibcon#[25=USB\r\n] 2006.218.08:09:30.55#ibcon#*before write, iclass 39, count 0 2006.218.08:09:30.55#ibcon#enter sib2, iclass 39, count 0 2006.218.08:09:30.55#ibcon#flushed, iclass 39, count 0 2006.218.08:09:30.55#ibcon#about to write, iclass 39, count 0 2006.218.08:09:30.55#ibcon#wrote, iclass 39, count 0 2006.218.08:09:30.55#ibcon#about to read 3, iclass 39, count 0 2006.218.08:09:30.58#ibcon#read 3, iclass 39, count 0 2006.218.08:09:30.58#ibcon#about to read 4, iclass 39, count 0 2006.218.08:09:30.58#ibcon#read 4, iclass 39, count 0 2006.218.08:09:30.58#ibcon#about to read 5, iclass 39, count 0 2006.218.08:09:30.58#ibcon#read 5, iclass 39, count 0 2006.218.08:09:30.58#ibcon#about to read 6, iclass 39, count 0 2006.218.08:09:30.58#ibcon#read 6, iclass 39, count 0 2006.218.08:09:30.58#ibcon#end of sib2, iclass 39, count 0 2006.218.08:09:30.58#ibcon#*after write, iclass 39, count 0 2006.218.08:09:30.58#ibcon#*before return 0, iclass 39, count 0 2006.218.08:09:30.58#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.218.08:09:30.58#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.218.08:09:30.58#ibcon#about to clear, iclass 39 cls_cnt 0 2006.218.08:09:30.58#ibcon#cleared, iclass 39 cls_cnt 0 2006.218.08:09:30.58$vc4f8/vblo=1,632.99 2006.218.08:09:30.58#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.218.08:09:30.58#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.218.08:09:30.58#ibcon#ireg 17 cls_cnt 0 2006.218.08:09:30.58#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.218.08:09:30.58#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.218.08:09:30.58#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.218.08:09:30.58#ibcon#enter wrdev, iclass 3, count 0 2006.218.08:09:30.58#ibcon#first serial, iclass 3, count 0 2006.218.08:09:30.58#ibcon#enter sib2, iclass 3, count 0 2006.218.08:09:30.58#ibcon#flushed, iclass 3, count 0 2006.218.08:09:30.58#ibcon#about to write, iclass 3, count 0 2006.218.08:09:30.58#ibcon#wrote, iclass 3, count 0 2006.218.08:09:30.58#ibcon#about to read 3, iclass 3, count 0 2006.218.08:09:30.60#ibcon#read 3, iclass 3, count 0 2006.218.08:09:30.60#ibcon#about to read 4, iclass 3, count 0 2006.218.08:09:30.60#ibcon#read 4, iclass 3, count 0 2006.218.08:09:30.60#ibcon#about to read 5, iclass 3, count 0 2006.218.08:09:30.60#ibcon#read 5, iclass 3, count 0 2006.218.08:09:30.60#ibcon#about to read 6, iclass 3, count 0 2006.218.08:09:30.60#ibcon#read 6, iclass 3, count 0 2006.218.08:09:30.60#ibcon#end of sib2, iclass 3, count 0 2006.218.08:09:30.60#ibcon#*mode == 0, iclass 3, count 0 2006.218.08:09:30.60#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.218.08:09:30.60#ibcon#[28=FRQ=01,632.99\r\n] 2006.218.08:09:30.60#ibcon#*before write, iclass 3, count 0 2006.218.08:09:30.60#ibcon#enter sib2, iclass 3, count 0 2006.218.08:09:30.60#ibcon#flushed, iclass 3, count 0 2006.218.08:09:30.60#ibcon#about to write, iclass 3, count 0 2006.218.08:09:30.60#ibcon#wrote, iclass 3, count 0 2006.218.08:09:30.60#ibcon#about to read 3, iclass 3, count 0 2006.218.08:09:30.64#ibcon#read 3, iclass 3, count 0 2006.218.08:09:30.64#ibcon#about to read 4, iclass 3, count 0 2006.218.08:09:30.64#ibcon#read 4, iclass 3, count 0 2006.218.08:09:30.64#ibcon#about to read 5, iclass 3, count 0 2006.218.08:09:30.64#ibcon#read 5, iclass 3, count 0 2006.218.08:09:30.64#ibcon#about to read 6, iclass 3, count 0 2006.218.08:09:30.64#ibcon#read 6, iclass 3, count 0 2006.218.08:09:30.64#ibcon#end of sib2, iclass 3, count 0 2006.218.08:09:30.64#ibcon#*after write, iclass 3, count 0 2006.218.08:09:30.64#ibcon#*before return 0, iclass 3, count 0 2006.218.08:09:30.64#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.218.08:09:30.64#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.218.08:09:30.64#ibcon#about to clear, iclass 3 cls_cnt 0 2006.218.08:09:30.64#ibcon#cleared, iclass 3 cls_cnt 0 2006.218.08:09:30.64$vc4f8/vb=1,4 2006.218.08:09:30.64#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.218.08:09:30.64#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.218.08:09:30.64#ibcon#ireg 11 cls_cnt 2 2006.218.08:09:30.64#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.218.08:09:30.64#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.218.08:09:30.64#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.218.08:09:30.64#ibcon#enter wrdev, iclass 5, count 2 2006.218.08:09:30.64#ibcon#first serial, iclass 5, count 2 2006.218.08:09:30.64#ibcon#enter sib2, iclass 5, count 2 2006.218.08:09:30.64#ibcon#flushed, iclass 5, count 2 2006.218.08:09:30.64#ibcon#about to write, iclass 5, count 2 2006.218.08:09:30.64#ibcon#wrote, iclass 5, count 2 2006.218.08:09:30.64#ibcon#about to read 3, iclass 5, count 2 2006.218.08:09:30.66#ibcon#read 3, iclass 5, count 2 2006.218.08:09:30.66#ibcon#about to read 4, iclass 5, count 2 2006.218.08:09:30.66#ibcon#read 4, iclass 5, count 2 2006.218.08:09:30.66#ibcon#about to read 5, iclass 5, count 2 2006.218.08:09:30.66#ibcon#read 5, iclass 5, count 2 2006.218.08:09:30.66#ibcon#about to read 6, iclass 5, count 2 2006.218.08:09:30.66#ibcon#read 6, iclass 5, count 2 2006.218.08:09:30.66#ibcon#end of sib2, iclass 5, count 2 2006.218.08:09:30.66#ibcon#*mode == 0, iclass 5, count 2 2006.218.08:09:30.66#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.218.08:09:30.66#ibcon#[27=AT01-04\r\n] 2006.218.08:09:30.66#ibcon#*before write, iclass 5, count 2 2006.218.08:09:30.66#ibcon#enter sib2, iclass 5, count 2 2006.218.08:09:30.66#ibcon#flushed, iclass 5, count 2 2006.218.08:09:30.66#ibcon#about to write, iclass 5, count 2 2006.218.08:09:30.66#ibcon#wrote, iclass 5, count 2 2006.218.08:09:30.66#ibcon#about to read 3, iclass 5, count 2 2006.218.08:09:30.69#ibcon#read 3, iclass 5, count 2 2006.218.08:09:30.69#ibcon#about to read 4, iclass 5, count 2 2006.218.08:09:30.69#ibcon#read 4, iclass 5, count 2 2006.218.08:09:30.69#ibcon#about to read 5, iclass 5, count 2 2006.218.08:09:30.69#ibcon#read 5, iclass 5, count 2 2006.218.08:09:30.69#ibcon#about to read 6, iclass 5, count 2 2006.218.08:09:30.69#ibcon#read 6, iclass 5, count 2 2006.218.08:09:30.69#ibcon#end of sib2, iclass 5, count 2 2006.218.08:09:30.69#ibcon#*after write, iclass 5, count 2 2006.218.08:09:30.69#ibcon#*before return 0, iclass 5, count 2 2006.218.08:09:30.69#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.218.08:09:30.69#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.218.08:09:30.69#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.218.08:09:30.69#ibcon#ireg 7 cls_cnt 0 2006.218.08:09:30.69#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.218.08:09:30.81#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.218.08:09:30.81#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.218.08:09:30.81#ibcon#enter wrdev, iclass 5, count 0 2006.218.08:09:30.81#ibcon#first serial, iclass 5, count 0 2006.218.08:09:30.81#ibcon#enter sib2, iclass 5, count 0 2006.218.08:09:30.81#ibcon#flushed, iclass 5, count 0 2006.218.08:09:30.81#ibcon#about to write, iclass 5, count 0 2006.218.08:09:30.81#ibcon#wrote, iclass 5, count 0 2006.218.08:09:30.81#ibcon#about to read 3, iclass 5, count 0 2006.218.08:09:30.83#ibcon#read 3, iclass 5, count 0 2006.218.08:09:30.83#ibcon#about to read 4, iclass 5, count 0 2006.218.08:09:30.83#ibcon#read 4, iclass 5, count 0 2006.218.08:09:30.83#ibcon#about to read 5, iclass 5, count 0 2006.218.08:09:30.83#ibcon#read 5, iclass 5, count 0 2006.218.08:09:30.83#ibcon#about to read 6, iclass 5, count 0 2006.218.08:09:30.83#ibcon#read 6, iclass 5, count 0 2006.218.08:09:30.83#ibcon#end of sib2, iclass 5, count 0 2006.218.08:09:30.83#ibcon#*mode == 0, iclass 5, count 0 2006.218.08:09:30.83#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.218.08:09:30.83#ibcon#[27=USB\r\n] 2006.218.08:09:30.83#ibcon#*before write, iclass 5, count 0 2006.218.08:09:30.83#ibcon#enter sib2, iclass 5, count 0 2006.218.08:09:30.83#ibcon#flushed, iclass 5, count 0 2006.218.08:09:30.83#ibcon#about to write, iclass 5, count 0 2006.218.08:09:30.83#ibcon#wrote, iclass 5, count 0 2006.218.08:09:30.83#ibcon#about to read 3, iclass 5, count 0 2006.218.08:09:30.86#ibcon#read 3, iclass 5, count 0 2006.218.08:09:30.86#ibcon#about to read 4, iclass 5, count 0 2006.218.08:09:30.86#ibcon#read 4, iclass 5, count 0 2006.218.08:09:30.86#ibcon#about to read 5, iclass 5, count 0 2006.218.08:09:30.86#ibcon#read 5, iclass 5, count 0 2006.218.08:09:30.86#ibcon#about to read 6, iclass 5, count 0 2006.218.08:09:30.86#ibcon#read 6, iclass 5, count 0 2006.218.08:09:30.86#ibcon#end of sib2, iclass 5, count 0 2006.218.08:09:30.86#ibcon#*after write, iclass 5, count 0 2006.218.08:09:30.86#ibcon#*before return 0, iclass 5, count 0 2006.218.08:09:30.86#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.218.08:09:30.86#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.218.08:09:30.86#ibcon#about to clear, iclass 5 cls_cnt 0 2006.218.08:09:30.86#ibcon#cleared, iclass 5 cls_cnt 0 2006.218.08:09:30.86$vc4f8/vblo=2,640.99 2006.218.08:09:30.86#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.218.08:09:30.86#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.218.08:09:30.86#ibcon#ireg 17 cls_cnt 0 2006.218.08:09:30.86#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.218.08:09:30.86#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.218.08:09:30.86#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.218.08:09:30.86#ibcon#enter wrdev, iclass 7, count 0 2006.218.08:09:30.86#ibcon#first serial, iclass 7, count 0 2006.218.08:09:30.86#ibcon#enter sib2, iclass 7, count 0 2006.218.08:09:30.86#ibcon#flushed, iclass 7, count 0 2006.218.08:09:30.86#ibcon#about to write, iclass 7, count 0 2006.218.08:09:30.86#ibcon#wrote, iclass 7, count 0 2006.218.08:09:30.86#ibcon#about to read 3, iclass 7, count 0 2006.218.08:09:30.88#ibcon#read 3, iclass 7, count 0 2006.218.08:09:30.88#ibcon#about to read 4, iclass 7, count 0 2006.218.08:09:30.88#ibcon#read 4, iclass 7, count 0 2006.218.08:09:30.88#ibcon#about to read 5, iclass 7, count 0 2006.218.08:09:30.88#ibcon#read 5, iclass 7, count 0 2006.218.08:09:30.88#ibcon#about to read 6, iclass 7, count 0 2006.218.08:09:30.88#ibcon#read 6, iclass 7, count 0 2006.218.08:09:30.88#ibcon#end of sib2, iclass 7, count 0 2006.218.08:09:30.88#ibcon#*mode == 0, iclass 7, count 0 2006.218.08:09:30.88#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.218.08:09:30.88#ibcon#[28=FRQ=02,640.99\r\n] 2006.218.08:09:30.88#ibcon#*before write, iclass 7, count 0 2006.218.08:09:30.88#ibcon#enter sib2, iclass 7, count 0 2006.218.08:09:30.88#ibcon#flushed, iclass 7, count 0 2006.218.08:09:30.88#ibcon#about to write, iclass 7, count 0 2006.218.08:09:30.88#ibcon#wrote, iclass 7, count 0 2006.218.08:09:30.88#ibcon#about to read 3, iclass 7, count 0 2006.218.08:09:30.92#ibcon#read 3, iclass 7, count 0 2006.218.08:09:30.92#ibcon#about to read 4, iclass 7, count 0 2006.218.08:09:30.92#ibcon#read 4, iclass 7, count 0 2006.218.08:09:30.92#ibcon#about to read 5, iclass 7, count 0 2006.218.08:09:30.92#ibcon#read 5, iclass 7, count 0 2006.218.08:09:30.92#ibcon#about to read 6, iclass 7, count 0 2006.218.08:09:30.92#ibcon#read 6, iclass 7, count 0 2006.218.08:09:30.92#ibcon#end of sib2, iclass 7, count 0 2006.218.08:09:30.92#ibcon#*after write, iclass 7, count 0 2006.218.08:09:30.92#ibcon#*before return 0, iclass 7, count 0 2006.218.08:09:30.92#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.218.08:09:30.92#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.218.08:09:30.92#ibcon#about to clear, iclass 7 cls_cnt 0 2006.218.08:09:30.92#ibcon#cleared, iclass 7 cls_cnt 0 2006.218.08:09:30.92$vc4f8/vb=2,4 2006.218.08:09:30.92#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.218.08:09:30.92#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.218.08:09:30.92#ibcon#ireg 11 cls_cnt 2 2006.218.08:09:30.92#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.218.08:09:30.98#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.218.08:09:30.98#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.218.08:09:30.98#ibcon#enter wrdev, iclass 11, count 2 2006.218.08:09:30.98#ibcon#first serial, iclass 11, count 2 2006.218.08:09:30.98#ibcon#enter sib2, iclass 11, count 2 2006.218.08:09:30.98#ibcon#flushed, iclass 11, count 2 2006.218.08:09:30.98#ibcon#about to write, iclass 11, count 2 2006.218.08:09:30.98#ibcon#wrote, iclass 11, count 2 2006.218.08:09:30.98#ibcon#about to read 3, iclass 11, count 2 2006.218.08:09:31.00#ibcon#read 3, iclass 11, count 2 2006.218.08:09:31.00#ibcon#about to read 4, iclass 11, count 2 2006.218.08:09:31.00#ibcon#read 4, iclass 11, count 2 2006.218.08:09:31.00#ibcon#about to read 5, iclass 11, count 2 2006.218.08:09:31.00#ibcon#read 5, iclass 11, count 2 2006.218.08:09:31.00#ibcon#about to read 6, iclass 11, count 2 2006.218.08:09:31.00#ibcon#read 6, iclass 11, count 2 2006.218.08:09:31.00#ibcon#end of sib2, iclass 11, count 2 2006.218.08:09:31.00#ibcon#*mode == 0, iclass 11, count 2 2006.218.08:09:31.00#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.218.08:09:31.00#ibcon#[27=AT02-04\r\n] 2006.218.08:09:31.00#ibcon#*before write, iclass 11, count 2 2006.218.08:09:31.00#ibcon#enter sib2, iclass 11, count 2 2006.218.08:09:31.00#ibcon#flushed, iclass 11, count 2 2006.218.08:09:31.00#ibcon#about to write, iclass 11, count 2 2006.218.08:09:31.00#ibcon#wrote, iclass 11, count 2 2006.218.08:09:31.00#ibcon#about to read 3, iclass 11, count 2 2006.218.08:09:31.03#ibcon#read 3, iclass 11, count 2 2006.218.08:09:31.03#ibcon#about to read 4, iclass 11, count 2 2006.218.08:09:31.03#ibcon#read 4, iclass 11, count 2 2006.218.08:09:31.03#ibcon#about to read 5, iclass 11, count 2 2006.218.08:09:31.03#ibcon#read 5, iclass 11, count 2 2006.218.08:09:31.03#ibcon#about to read 6, iclass 11, count 2 2006.218.08:09:31.03#ibcon#read 6, iclass 11, count 2 2006.218.08:09:31.03#ibcon#end of sib2, iclass 11, count 2 2006.218.08:09:31.03#ibcon#*after write, iclass 11, count 2 2006.218.08:09:31.03#ibcon#*before return 0, iclass 11, count 2 2006.218.08:09:31.03#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.218.08:09:31.03#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.218.08:09:31.03#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.218.08:09:31.03#ibcon#ireg 7 cls_cnt 0 2006.218.08:09:31.03#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.218.08:09:31.15#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.218.08:09:31.15#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.218.08:09:31.15#ibcon#enter wrdev, iclass 11, count 0 2006.218.08:09:31.15#ibcon#first serial, iclass 11, count 0 2006.218.08:09:31.15#ibcon#enter sib2, iclass 11, count 0 2006.218.08:09:31.15#ibcon#flushed, iclass 11, count 0 2006.218.08:09:31.15#ibcon#about to write, iclass 11, count 0 2006.218.08:09:31.15#ibcon#wrote, iclass 11, count 0 2006.218.08:09:31.15#ibcon#about to read 3, iclass 11, count 0 2006.218.08:09:31.17#ibcon#read 3, iclass 11, count 0 2006.218.08:09:31.17#ibcon#about to read 4, iclass 11, count 0 2006.218.08:09:31.17#ibcon#read 4, iclass 11, count 0 2006.218.08:09:31.17#ibcon#about to read 5, iclass 11, count 0 2006.218.08:09:31.17#ibcon#read 5, iclass 11, count 0 2006.218.08:09:31.17#ibcon#about to read 6, iclass 11, count 0 2006.218.08:09:31.17#ibcon#read 6, iclass 11, count 0 2006.218.08:09:31.17#ibcon#end of sib2, iclass 11, count 0 2006.218.08:09:31.17#ibcon#*mode == 0, iclass 11, count 0 2006.218.08:09:31.17#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.218.08:09:31.17#ibcon#[27=USB\r\n] 2006.218.08:09:31.17#ibcon#*before write, iclass 11, count 0 2006.218.08:09:31.17#ibcon#enter sib2, iclass 11, count 0 2006.218.08:09:31.17#ibcon#flushed, iclass 11, count 0 2006.218.08:09:31.17#ibcon#about to write, iclass 11, count 0 2006.218.08:09:31.17#ibcon#wrote, iclass 11, count 0 2006.218.08:09:31.17#ibcon#about to read 3, iclass 11, count 0 2006.218.08:09:31.20#ibcon#read 3, iclass 11, count 0 2006.218.08:09:31.20#ibcon#about to read 4, iclass 11, count 0 2006.218.08:09:31.20#ibcon#read 4, iclass 11, count 0 2006.218.08:09:31.20#ibcon#about to read 5, iclass 11, count 0 2006.218.08:09:31.20#ibcon#read 5, iclass 11, count 0 2006.218.08:09:31.20#ibcon#about to read 6, iclass 11, count 0 2006.218.08:09:31.20#ibcon#read 6, iclass 11, count 0 2006.218.08:09:31.20#ibcon#end of sib2, iclass 11, count 0 2006.218.08:09:31.20#ibcon#*after write, iclass 11, count 0 2006.218.08:09:31.20#ibcon#*before return 0, iclass 11, count 0 2006.218.08:09:31.20#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.218.08:09:31.20#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.218.08:09:31.20#ibcon#about to clear, iclass 11 cls_cnt 0 2006.218.08:09:31.20#ibcon#cleared, iclass 11 cls_cnt 0 2006.218.08:09:31.20$vc4f8/vblo=3,656.99 2006.218.08:09:31.20#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.218.08:09:31.20#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.218.08:09:31.20#ibcon#ireg 17 cls_cnt 0 2006.218.08:09:31.20#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.218.08:09:31.20#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.218.08:09:31.20#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.218.08:09:31.20#ibcon#enter wrdev, iclass 13, count 0 2006.218.08:09:31.20#ibcon#first serial, iclass 13, count 0 2006.218.08:09:31.20#ibcon#enter sib2, iclass 13, count 0 2006.218.08:09:31.20#ibcon#flushed, iclass 13, count 0 2006.218.08:09:31.20#ibcon#about to write, iclass 13, count 0 2006.218.08:09:31.20#ibcon#wrote, iclass 13, count 0 2006.218.08:09:31.20#ibcon#about to read 3, iclass 13, count 0 2006.218.08:09:31.22#ibcon#read 3, iclass 13, count 0 2006.218.08:09:31.22#ibcon#about to read 4, iclass 13, count 0 2006.218.08:09:31.22#ibcon#read 4, iclass 13, count 0 2006.218.08:09:31.22#ibcon#about to read 5, iclass 13, count 0 2006.218.08:09:31.22#ibcon#read 5, iclass 13, count 0 2006.218.08:09:31.22#ibcon#about to read 6, iclass 13, count 0 2006.218.08:09:31.22#ibcon#read 6, iclass 13, count 0 2006.218.08:09:31.22#ibcon#end of sib2, iclass 13, count 0 2006.218.08:09:31.22#ibcon#*mode == 0, iclass 13, count 0 2006.218.08:09:31.22#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.218.08:09:31.22#ibcon#[28=FRQ=03,656.99\r\n] 2006.218.08:09:31.22#ibcon#*before write, iclass 13, count 0 2006.218.08:09:31.22#ibcon#enter sib2, iclass 13, count 0 2006.218.08:09:31.22#ibcon#flushed, iclass 13, count 0 2006.218.08:09:31.22#ibcon#about to write, iclass 13, count 0 2006.218.08:09:31.22#ibcon#wrote, iclass 13, count 0 2006.218.08:09:31.22#ibcon#about to read 3, iclass 13, count 0 2006.218.08:09:31.26#ibcon#read 3, iclass 13, count 0 2006.218.08:09:31.26#ibcon#about to read 4, iclass 13, count 0 2006.218.08:09:31.26#ibcon#read 4, iclass 13, count 0 2006.218.08:09:31.26#ibcon#about to read 5, iclass 13, count 0 2006.218.08:09:31.26#ibcon#read 5, iclass 13, count 0 2006.218.08:09:31.26#ibcon#about to read 6, iclass 13, count 0 2006.218.08:09:31.26#ibcon#read 6, iclass 13, count 0 2006.218.08:09:31.26#ibcon#end of sib2, iclass 13, count 0 2006.218.08:09:31.26#ibcon#*after write, iclass 13, count 0 2006.218.08:09:31.26#ibcon#*before return 0, iclass 13, count 0 2006.218.08:09:31.26#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.218.08:09:31.26#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.218.08:09:31.26#ibcon#about to clear, iclass 13 cls_cnt 0 2006.218.08:09:31.26#ibcon#cleared, iclass 13 cls_cnt 0 2006.218.08:09:31.26$vc4f8/vb=3,4 2006.218.08:09:31.26#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.218.08:09:31.26#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.218.08:09:31.26#ibcon#ireg 11 cls_cnt 2 2006.218.08:09:31.26#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.218.08:09:31.32#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.218.08:09:31.32#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.218.08:09:31.32#ibcon#enter wrdev, iclass 15, count 2 2006.218.08:09:31.32#ibcon#first serial, iclass 15, count 2 2006.218.08:09:31.32#ibcon#enter sib2, iclass 15, count 2 2006.218.08:09:31.32#ibcon#flushed, iclass 15, count 2 2006.218.08:09:31.32#ibcon#about to write, iclass 15, count 2 2006.218.08:09:31.32#ibcon#wrote, iclass 15, count 2 2006.218.08:09:31.32#ibcon#about to read 3, iclass 15, count 2 2006.218.08:09:31.34#ibcon#read 3, iclass 15, count 2 2006.218.08:09:31.34#ibcon#about to read 4, iclass 15, count 2 2006.218.08:09:31.34#ibcon#read 4, iclass 15, count 2 2006.218.08:09:31.34#ibcon#about to read 5, iclass 15, count 2 2006.218.08:09:31.34#ibcon#read 5, iclass 15, count 2 2006.218.08:09:31.34#ibcon#about to read 6, iclass 15, count 2 2006.218.08:09:31.34#ibcon#read 6, iclass 15, count 2 2006.218.08:09:31.34#ibcon#end of sib2, iclass 15, count 2 2006.218.08:09:31.34#ibcon#*mode == 0, iclass 15, count 2 2006.218.08:09:31.34#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.218.08:09:31.34#ibcon#[27=AT03-04\r\n] 2006.218.08:09:31.34#ibcon#*before write, iclass 15, count 2 2006.218.08:09:31.34#ibcon#enter sib2, iclass 15, count 2 2006.218.08:09:31.34#ibcon#flushed, iclass 15, count 2 2006.218.08:09:31.34#ibcon#about to write, iclass 15, count 2 2006.218.08:09:31.34#ibcon#wrote, iclass 15, count 2 2006.218.08:09:31.34#ibcon#about to read 3, iclass 15, count 2 2006.218.08:09:31.37#ibcon#read 3, iclass 15, count 2 2006.218.08:09:31.37#ibcon#about to read 4, iclass 15, count 2 2006.218.08:09:31.37#ibcon#read 4, iclass 15, count 2 2006.218.08:09:31.37#ibcon#about to read 5, iclass 15, count 2 2006.218.08:09:31.37#ibcon#read 5, iclass 15, count 2 2006.218.08:09:31.37#ibcon#about to read 6, iclass 15, count 2 2006.218.08:09:31.37#ibcon#read 6, iclass 15, count 2 2006.218.08:09:31.37#ibcon#end of sib2, iclass 15, count 2 2006.218.08:09:31.37#ibcon#*after write, iclass 15, count 2 2006.218.08:09:31.37#ibcon#*before return 0, iclass 15, count 2 2006.218.08:09:31.37#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.218.08:09:31.37#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.218.08:09:31.37#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.218.08:09:31.37#ibcon#ireg 7 cls_cnt 0 2006.218.08:09:31.37#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.218.08:09:31.49#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.218.08:09:31.49#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.218.08:09:31.49#ibcon#enter wrdev, iclass 15, count 0 2006.218.08:09:31.49#ibcon#first serial, iclass 15, count 0 2006.218.08:09:31.49#ibcon#enter sib2, iclass 15, count 0 2006.218.08:09:31.49#ibcon#flushed, iclass 15, count 0 2006.218.08:09:31.49#ibcon#about to write, iclass 15, count 0 2006.218.08:09:31.49#ibcon#wrote, iclass 15, count 0 2006.218.08:09:31.49#ibcon#about to read 3, iclass 15, count 0 2006.218.08:09:31.51#ibcon#read 3, iclass 15, count 0 2006.218.08:09:31.51#ibcon#about to read 4, iclass 15, count 0 2006.218.08:09:31.51#ibcon#read 4, iclass 15, count 0 2006.218.08:09:31.51#ibcon#about to read 5, iclass 15, count 0 2006.218.08:09:31.51#ibcon#read 5, iclass 15, count 0 2006.218.08:09:31.51#ibcon#about to read 6, iclass 15, count 0 2006.218.08:09:31.51#ibcon#read 6, iclass 15, count 0 2006.218.08:09:31.51#ibcon#end of sib2, iclass 15, count 0 2006.218.08:09:31.51#ibcon#*mode == 0, iclass 15, count 0 2006.218.08:09:31.51#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.218.08:09:31.51#ibcon#[27=USB\r\n] 2006.218.08:09:31.51#ibcon#*before write, iclass 15, count 0 2006.218.08:09:31.51#ibcon#enter sib2, iclass 15, count 0 2006.218.08:09:31.51#ibcon#flushed, iclass 15, count 0 2006.218.08:09:31.51#ibcon#about to write, iclass 15, count 0 2006.218.08:09:31.51#ibcon#wrote, iclass 15, count 0 2006.218.08:09:31.51#ibcon#about to read 3, iclass 15, count 0 2006.218.08:09:31.54#ibcon#read 3, iclass 15, count 0 2006.218.08:09:31.54#ibcon#about to read 4, iclass 15, count 0 2006.218.08:09:31.54#ibcon#read 4, iclass 15, count 0 2006.218.08:09:31.54#ibcon#about to read 5, iclass 15, count 0 2006.218.08:09:31.54#ibcon#read 5, iclass 15, count 0 2006.218.08:09:31.54#ibcon#about to read 6, iclass 15, count 0 2006.218.08:09:31.54#ibcon#read 6, iclass 15, count 0 2006.218.08:09:31.54#ibcon#end of sib2, iclass 15, count 0 2006.218.08:09:31.54#ibcon#*after write, iclass 15, count 0 2006.218.08:09:31.54#ibcon#*before return 0, iclass 15, count 0 2006.218.08:09:31.54#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.218.08:09:31.54#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.218.08:09:31.54#ibcon#about to clear, iclass 15 cls_cnt 0 2006.218.08:09:31.54#ibcon#cleared, iclass 15 cls_cnt 0 2006.218.08:09:31.54$vc4f8/vblo=4,712.99 2006.218.08:09:31.54#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.218.08:09:31.54#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.218.08:09:31.54#ibcon#ireg 17 cls_cnt 0 2006.218.08:09:31.54#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.218.08:09:31.54#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.218.08:09:31.54#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.218.08:09:31.54#ibcon#enter wrdev, iclass 17, count 0 2006.218.08:09:31.54#ibcon#first serial, iclass 17, count 0 2006.218.08:09:31.54#ibcon#enter sib2, iclass 17, count 0 2006.218.08:09:31.54#ibcon#flushed, iclass 17, count 0 2006.218.08:09:31.54#ibcon#about to write, iclass 17, count 0 2006.218.08:09:31.54#ibcon#wrote, iclass 17, count 0 2006.218.08:09:31.54#ibcon#about to read 3, iclass 17, count 0 2006.218.08:09:31.56#ibcon#read 3, iclass 17, count 0 2006.218.08:09:31.56#ibcon#about to read 4, iclass 17, count 0 2006.218.08:09:31.56#ibcon#read 4, iclass 17, count 0 2006.218.08:09:31.56#ibcon#about to read 5, iclass 17, count 0 2006.218.08:09:31.56#ibcon#read 5, iclass 17, count 0 2006.218.08:09:31.56#ibcon#about to read 6, iclass 17, count 0 2006.218.08:09:31.56#ibcon#read 6, iclass 17, count 0 2006.218.08:09:31.56#ibcon#end of sib2, iclass 17, count 0 2006.218.08:09:31.56#ibcon#*mode == 0, iclass 17, count 0 2006.218.08:09:31.56#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.218.08:09:31.56#ibcon#[28=FRQ=04,712.99\r\n] 2006.218.08:09:31.56#ibcon#*before write, iclass 17, count 0 2006.218.08:09:31.56#ibcon#enter sib2, iclass 17, count 0 2006.218.08:09:31.56#ibcon#flushed, iclass 17, count 0 2006.218.08:09:31.56#ibcon#about to write, iclass 17, count 0 2006.218.08:09:31.56#ibcon#wrote, iclass 17, count 0 2006.218.08:09:31.56#ibcon#about to read 3, iclass 17, count 0 2006.218.08:09:31.60#ibcon#read 3, iclass 17, count 0 2006.218.08:09:31.60#ibcon#about to read 4, iclass 17, count 0 2006.218.08:09:31.60#ibcon#read 4, iclass 17, count 0 2006.218.08:09:31.60#ibcon#about to read 5, iclass 17, count 0 2006.218.08:09:31.60#ibcon#read 5, iclass 17, count 0 2006.218.08:09:31.60#ibcon#about to read 6, iclass 17, count 0 2006.218.08:09:31.60#ibcon#read 6, iclass 17, count 0 2006.218.08:09:31.60#ibcon#end of sib2, iclass 17, count 0 2006.218.08:09:31.60#ibcon#*after write, iclass 17, count 0 2006.218.08:09:31.60#ibcon#*before return 0, iclass 17, count 0 2006.218.08:09:31.60#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.218.08:09:31.60#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.218.08:09:31.60#ibcon#about to clear, iclass 17 cls_cnt 0 2006.218.08:09:31.60#ibcon#cleared, iclass 17 cls_cnt 0 2006.218.08:09:31.60$vc4f8/vb=4,4 2006.218.08:09:31.60#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.218.08:09:31.60#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.218.08:09:31.60#ibcon#ireg 11 cls_cnt 2 2006.218.08:09:31.60#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.218.08:09:31.66#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.218.08:09:31.66#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.218.08:09:31.66#ibcon#enter wrdev, iclass 19, count 2 2006.218.08:09:31.66#ibcon#first serial, iclass 19, count 2 2006.218.08:09:31.66#ibcon#enter sib2, iclass 19, count 2 2006.218.08:09:31.66#ibcon#flushed, iclass 19, count 2 2006.218.08:09:31.66#ibcon#about to write, iclass 19, count 2 2006.218.08:09:31.66#ibcon#wrote, iclass 19, count 2 2006.218.08:09:31.66#ibcon#about to read 3, iclass 19, count 2 2006.218.08:09:31.68#ibcon#read 3, iclass 19, count 2 2006.218.08:09:31.68#ibcon#about to read 4, iclass 19, count 2 2006.218.08:09:31.68#ibcon#read 4, iclass 19, count 2 2006.218.08:09:31.68#ibcon#about to read 5, iclass 19, count 2 2006.218.08:09:31.68#ibcon#read 5, iclass 19, count 2 2006.218.08:09:31.68#ibcon#about to read 6, iclass 19, count 2 2006.218.08:09:31.68#ibcon#read 6, iclass 19, count 2 2006.218.08:09:31.68#ibcon#end of sib2, iclass 19, count 2 2006.218.08:09:31.68#ibcon#*mode == 0, iclass 19, count 2 2006.218.08:09:31.68#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.218.08:09:31.68#ibcon#[27=AT04-04\r\n] 2006.218.08:09:31.68#ibcon#*before write, iclass 19, count 2 2006.218.08:09:31.68#ibcon#enter sib2, iclass 19, count 2 2006.218.08:09:31.68#ibcon#flushed, iclass 19, count 2 2006.218.08:09:31.68#ibcon#about to write, iclass 19, count 2 2006.218.08:09:31.68#ibcon#wrote, iclass 19, count 2 2006.218.08:09:31.68#ibcon#about to read 3, iclass 19, count 2 2006.218.08:09:31.71#ibcon#read 3, iclass 19, count 2 2006.218.08:09:31.71#ibcon#about to read 4, iclass 19, count 2 2006.218.08:09:31.71#ibcon#read 4, iclass 19, count 2 2006.218.08:09:31.71#ibcon#about to read 5, iclass 19, count 2 2006.218.08:09:31.71#ibcon#read 5, iclass 19, count 2 2006.218.08:09:31.71#ibcon#about to read 6, iclass 19, count 2 2006.218.08:09:31.71#ibcon#read 6, iclass 19, count 2 2006.218.08:09:31.71#ibcon#end of sib2, iclass 19, count 2 2006.218.08:09:31.71#ibcon#*after write, iclass 19, count 2 2006.218.08:09:31.71#ibcon#*before return 0, iclass 19, count 2 2006.218.08:09:31.71#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.218.08:09:31.71#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.218.08:09:31.71#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.218.08:09:31.71#ibcon#ireg 7 cls_cnt 0 2006.218.08:09:31.71#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.218.08:09:31.83#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.218.08:09:31.83#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.218.08:09:31.83#ibcon#enter wrdev, iclass 19, count 0 2006.218.08:09:31.83#ibcon#first serial, iclass 19, count 0 2006.218.08:09:31.83#ibcon#enter sib2, iclass 19, count 0 2006.218.08:09:31.83#ibcon#flushed, iclass 19, count 0 2006.218.08:09:31.83#ibcon#about to write, iclass 19, count 0 2006.218.08:09:31.83#ibcon#wrote, iclass 19, count 0 2006.218.08:09:31.83#ibcon#about to read 3, iclass 19, count 0 2006.218.08:09:31.85#ibcon#read 3, iclass 19, count 0 2006.218.08:09:31.85#ibcon#about to read 4, iclass 19, count 0 2006.218.08:09:31.85#ibcon#read 4, iclass 19, count 0 2006.218.08:09:31.85#ibcon#about to read 5, iclass 19, count 0 2006.218.08:09:31.85#ibcon#read 5, iclass 19, count 0 2006.218.08:09:31.85#ibcon#about to read 6, iclass 19, count 0 2006.218.08:09:31.85#ibcon#read 6, iclass 19, count 0 2006.218.08:09:31.85#ibcon#end of sib2, iclass 19, count 0 2006.218.08:09:31.85#ibcon#*mode == 0, iclass 19, count 0 2006.218.08:09:31.85#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.218.08:09:31.85#ibcon#[27=USB\r\n] 2006.218.08:09:31.85#ibcon#*before write, iclass 19, count 0 2006.218.08:09:31.85#ibcon#enter sib2, iclass 19, count 0 2006.218.08:09:31.85#ibcon#flushed, iclass 19, count 0 2006.218.08:09:31.85#ibcon#about to write, iclass 19, count 0 2006.218.08:09:31.85#ibcon#wrote, iclass 19, count 0 2006.218.08:09:31.85#ibcon#about to read 3, iclass 19, count 0 2006.218.08:09:31.88#ibcon#read 3, iclass 19, count 0 2006.218.08:09:31.88#ibcon#about to read 4, iclass 19, count 0 2006.218.08:09:31.88#ibcon#read 4, iclass 19, count 0 2006.218.08:09:31.88#ibcon#about to read 5, iclass 19, count 0 2006.218.08:09:31.88#ibcon#read 5, iclass 19, count 0 2006.218.08:09:31.88#ibcon#about to read 6, iclass 19, count 0 2006.218.08:09:31.88#ibcon#read 6, iclass 19, count 0 2006.218.08:09:31.88#ibcon#end of sib2, iclass 19, count 0 2006.218.08:09:31.88#ibcon#*after write, iclass 19, count 0 2006.218.08:09:31.88#ibcon#*before return 0, iclass 19, count 0 2006.218.08:09:31.88#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.218.08:09:31.88#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.218.08:09:31.88#ibcon#about to clear, iclass 19 cls_cnt 0 2006.218.08:09:31.88#ibcon#cleared, iclass 19 cls_cnt 0 2006.218.08:09:31.88$vc4f8/vblo=5,744.99 2006.218.08:09:31.88#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.218.08:09:31.88#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.218.08:09:31.88#ibcon#ireg 17 cls_cnt 0 2006.218.08:09:31.88#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.218.08:09:31.88#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.218.08:09:31.88#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.218.08:09:31.88#ibcon#enter wrdev, iclass 21, count 0 2006.218.08:09:31.88#ibcon#first serial, iclass 21, count 0 2006.218.08:09:31.88#ibcon#enter sib2, iclass 21, count 0 2006.218.08:09:31.88#ibcon#flushed, iclass 21, count 0 2006.218.08:09:31.88#ibcon#about to write, iclass 21, count 0 2006.218.08:09:31.88#ibcon#wrote, iclass 21, count 0 2006.218.08:09:31.88#ibcon#about to read 3, iclass 21, count 0 2006.218.08:09:31.90#ibcon#read 3, iclass 21, count 0 2006.218.08:09:31.90#ibcon#about to read 4, iclass 21, count 0 2006.218.08:09:31.90#ibcon#read 4, iclass 21, count 0 2006.218.08:09:31.90#ibcon#about to read 5, iclass 21, count 0 2006.218.08:09:31.90#ibcon#read 5, iclass 21, count 0 2006.218.08:09:31.90#ibcon#about to read 6, iclass 21, count 0 2006.218.08:09:31.90#ibcon#read 6, iclass 21, count 0 2006.218.08:09:31.90#ibcon#end of sib2, iclass 21, count 0 2006.218.08:09:31.90#ibcon#*mode == 0, iclass 21, count 0 2006.218.08:09:31.90#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.218.08:09:31.90#ibcon#[28=FRQ=05,744.99\r\n] 2006.218.08:09:31.90#ibcon#*before write, iclass 21, count 0 2006.218.08:09:31.90#ibcon#enter sib2, iclass 21, count 0 2006.218.08:09:31.90#ibcon#flushed, iclass 21, count 0 2006.218.08:09:31.90#ibcon#about to write, iclass 21, count 0 2006.218.08:09:31.90#ibcon#wrote, iclass 21, count 0 2006.218.08:09:31.90#ibcon#about to read 3, iclass 21, count 0 2006.218.08:09:31.94#ibcon#read 3, iclass 21, count 0 2006.218.08:09:31.94#ibcon#about to read 4, iclass 21, count 0 2006.218.08:09:31.94#ibcon#read 4, iclass 21, count 0 2006.218.08:09:31.94#ibcon#about to read 5, iclass 21, count 0 2006.218.08:09:31.94#ibcon#read 5, iclass 21, count 0 2006.218.08:09:31.94#ibcon#about to read 6, iclass 21, count 0 2006.218.08:09:31.94#ibcon#read 6, iclass 21, count 0 2006.218.08:09:31.94#ibcon#end of sib2, iclass 21, count 0 2006.218.08:09:31.94#ibcon#*after write, iclass 21, count 0 2006.218.08:09:31.94#ibcon#*before return 0, iclass 21, count 0 2006.218.08:09:31.94#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.218.08:09:31.94#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.218.08:09:31.94#ibcon#about to clear, iclass 21 cls_cnt 0 2006.218.08:09:31.94#ibcon#cleared, iclass 21 cls_cnt 0 2006.218.08:09:31.94$vc4f8/vb=5,4 2006.218.08:09:31.94#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.218.08:09:31.94#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.218.08:09:31.94#ibcon#ireg 11 cls_cnt 2 2006.218.08:09:31.94#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.218.08:09:32.00#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.218.08:09:32.00#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.218.08:09:32.00#ibcon#enter wrdev, iclass 23, count 2 2006.218.08:09:32.00#ibcon#first serial, iclass 23, count 2 2006.218.08:09:32.00#ibcon#enter sib2, iclass 23, count 2 2006.218.08:09:32.00#ibcon#flushed, iclass 23, count 2 2006.218.08:09:32.00#ibcon#about to write, iclass 23, count 2 2006.218.08:09:32.00#ibcon#wrote, iclass 23, count 2 2006.218.08:09:32.00#ibcon#about to read 3, iclass 23, count 2 2006.218.08:09:32.02#ibcon#read 3, iclass 23, count 2 2006.218.08:09:32.02#ibcon#about to read 4, iclass 23, count 2 2006.218.08:09:32.02#ibcon#read 4, iclass 23, count 2 2006.218.08:09:32.02#ibcon#about to read 5, iclass 23, count 2 2006.218.08:09:32.02#ibcon#read 5, iclass 23, count 2 2006.218.08:09:32.02#ibcon#about to read 6, iclass 23, count 2 2006.218.08:09:32.02#ibcon#read 6, iclass 23, count 2 2006.218.08:09:32.02#ibcon#end of sib2, iclass 23, count 2 2006.218.08:09:32.02#ibcon#*mode == 0, iclass 23, count 2 2006.218.08:09:32.02#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.218.08:09:32.02#ibcon#[27=AT05-04\r\n] 2006.218.08:09:32.02#ibcon#*before write, iclass 23, count 2 2006.218.08:09:32.02#ibcon#enter sib2, iclass 23, count 2 2006.218.08:09:32.02#ibcon#flushed, iclass 23, count 2 2006.218.08:09:32.02#ibcon#about to write, iclass 23, count 2 2006.218.08:09:32.02#ibcon#wrote, iclass 23, count 2 2006.218.08:09:32.02#ibcon#about to read 3, iclass 23, count 2 2006.218.08:09:32.05#ibcon#read 3, iclass 23, count 2 2006.218.08:09:32.05#ibcon#about to read 4, iclass 23, count 2 2006.218.08:09:32.05#ibcon#read 4, iclass 23, count 2 2006.218.08:09:32.05#ibcon#about to read 5, iclass 23, count 2 2006.218.08:09:32.05#ibcon#read 5, iclass 23, count 2 2006.218.08:09:32.05#ibcon#about to read 6, iclass 23, count 2 2006.218.08:09:32.05#ibcon#read 6, iclass 23, count 2 2006.218.08:09:32.05#ibcon#end of sib2, iclass 23, count 2 2006.218.08:09:32.05#ibcon#*after write, iclass 23, count 2 2006.218.08:09:32.05#ibcon#*before return 0, iclass 23, count 2 2006.218.08:09:32.05#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.218.08:09:32.05#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.218.08:09:32.05#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.218.08:09:32.05#ibcon#ireg 7 cls_cnt 0 2006.218.08:09:32.05#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.218.08:09:32.17#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.218.08:09:32.17#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.218.08:09:32.17#ibcon#enter wrdev, iclass 23, count 0 2006.218.08:09:32.17#ibcon#first serial, iclass 23, count 0 2006.218.08:09:32.17#ibcon#enter sib2, iclass 23, count 0 2006.218.08:09:32.17#ibcon#flushed, iclass 23, count 0 2006.218.08:09:32.17#ibcon#about to write, iclass 23, count 0 2006.218.08:09:32.17#ibcon#wrote, iclass 23, count 0 2006.218.08:09:32.17#ibcon#about to read 3, iclass 23, count 0 2006.218.08:09:32.19#ibcon#read 3, iclass 23, count 0 2006.218.08:09:32.19#ibcon#about to read 4, iclass 23, count 0 2006.218.08:09:32.19#ibcon#read 4, iclass 23, count 0 2006.218.08:09:32.19#ibcon#about to read 5, iclass 23, count 0 2006.218.08:09:32.19#ibcon#read 5, iclass 23, count 0 2006.218.08:09:32.19#ibcon#about to read 6, iclass 23, count 0 2006.218.08:09:32.19#ibcon#read 6, iclass 23, count 0 2006.218.08:09:32.19#ibcon#end of sib2, iclass 23, count 0 2006.218.08:09:32.19#ibcon#*mode == 0, iclass 23, count 0 2006.218.08:09:32.19#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.218.08:09:32.19#ibcon#[27=USB\r\n] 2006.218.08:09:32.19#ibcon#*before write, iclass 23, count 0 2006.218.08:09:32.19#ibcon#enter sib2, iclass 23, count 0 2006.218.08:09:32.19#ibcon#flushed, iclass 23, count 0 2006.218.08:09:32.19#ibcon#about to write, iclass 23, count 0 2006.218.08:09:32.19#ibcon#wrote, iclass 23, count 0 2006.218.08:09:32.19#ibcon#about to read 3, iclass 23, count 0 2006.218.08:09:32.22#ibcon#read 3, iclass 23, count 0 2006.218.08:09:32.22#ibcon#about to read 4, iclass 23, count 0 2006.218.08:09:32.22#ibcon#read 4, iclass 23, count 0 2006.218.08:09:32.22#ibcon#about to read 5, iclass 23, count 0 2006.218.08:09:32.22#ibcon#read 5, iclass 23, count 0 2006.218.08:09:32.22#ibcon#about to read 6, iclass 23, count 0 2006.218.08:09:32.22#ibcon#read 6, iclass 23, count 0 2006.218.08:09:32.22#ibcon#end of sib2, iclass 23, count 0 2006.218.08:09:32.22#ibcon#*after write, iclass 23, count 0 2006.218.08:09:32.22#ibcon#*before return 0, iclass 23, count 0 2006.218.08:09:32.22#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.218.08:09:32.22#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.218.08:09:32.22#ibcon#about to clear, iclass 23 cls_cnt 0 2006.218.08:09:32.22#ibcon#cleared, iclass 23 cls_cnt 0 2006.218.08:09:32.22$vc4f8/vblo=6,752.99 2006.218.08:09:32.22#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.218.08:09:32.22#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.218.08:09:32.22#ibcon#ireg 17 cls_cnt 0 2006.218.08:09:32.22#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.218.08:09:32.22#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.218.08:09:32.22#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.218.08:09:32.22#ibcon#enter wrdev, iclass 25, count 0 2006.218.08:09:32.22#ibcon#first serial, iclass 25, count 0 2006.218.08:09:32.22#ibcon#enter sib2, iclass 25, count 0 2006.218.08:09:32.22#ibcon#flushed, iclass 25, count 0 2006.218.08:09:32.22#ibcon#about to write, iclass 25, count 0 2006.218.08:09:32.22#ibcon#wrote, iclass 25, count 0 2006.218.08:09:32.22#ibcon#about to read 3, iclass 25, count 0 2006.218.08:09:32.24#ibcon#read 3, iclass 25, count 0 2006.218.08:09:32.24#ibcon#about to read 4, iclass 25, count 0 2006.218.08:09:32.24#ibcon#read 4, iclass 25, count 0 2006.218.08:09:32.24#ibcon#about to read 5, iclass 25, count 0 2006.218.08:09:32.24#ibcon#read 5, iclass 25, count 0 2006.218.08:09:32.24#ibcon#about to read 6, iclass 25, count 0 2006.218.08:09:32.24#ibcon#read 6, iclass 25, count 0 2006.218.08:09:32.24#ibcon#end of sib2, iclass 25, count 0 2006.218.08:09:32.24#ibcon#*mode == 0, iclass 25, count 0 2006.218.08:09:32.24#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.218.08:09:32.24#ibcon#[28=FRQ=06,752.99\r\n] 2006.218.08:09:32.24#ibcon#*before write, iclass 25, count 0 2006.218.08:09:32.24#ibcon#enter sib2, iclass 25, count 0 2006.218.08:09:32.24#ibcon#flushed, iclass 25, count 0 2006.218.08:09:32.24#ibcon#about to write, iclass 25, count 0 2006.218.08:09:32.24#ibcon#wrote, iclass 25, count 0 2006.218.08:09:32.24#ibcon#about to read 3, iclass 25, count 0 2006.218.08:09:32.28#ibcon#read 3, iclass 25, count 0 2006.218.08:09:32.28#ibcon#about to read 4, iclass 25, count 0 2006.218.08:09:32.28#ibcon#read 4, iclass 25, count 0 2006.218.08:09:32.28#ibcon#about to read 5, iclass 25, count 0 2006.218.08:09:32.28#ibcon#read 5, iclass 25, count 0 2006.218.08:09:32.28#ibcon#about to read 6, iclass 25, count 0 2006.218.08:09:32.28#ibcon#read 6, iclass 25, count 0 2006.218.08:09:32.28#ibcon#end of sib2, iclass 25, count 0 2006.218.08:09:32.28#ibcon#*after write, iclass 25, count 0 2006.218.08:09:32.28#ibcon#*before return 0, iclass 25, count 0 2006.218.08:09:32.28#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.218.08:09:32.28#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.218.08:09:32.28#ibcon#about to clear, iclass 25 cls_cnt 0 2006.218.08:09:32.28#ibcon#cleared, iclass 25 cls_cnt 0 2006.218.08:09:32.28$vc4f8/vb=6,4 2006.218.08:09:32.28#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.218.08:09:32.28#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.218.08:09:32.28#ibcon#ireg 11 cls_cnt 2 2006.218.08:09:32.28#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.218.08:09:32.34#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.218.08:09:32.34#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.218.08:09:32.34#ibcon#enter wrdev, iclass 27, count 2 2006.218.08:09:32.34#ibcon#first serial, iclass 27, count 2 2006.218.08:09:32.34#ibcon#enter sib2, iclass 27, count 2 2006.218.08:09:32.34#ibcon#flushed, iclass 27, count 2 2006.218.08:09:32.34#ibcon#about to write, iclass 27, count 2 2006.218.08:09:32.34#ibcon#wrote, iclass 27, count 2 2006.218.08:09:32.34#ibcon#about to read 3, iclass 27, count 2 2006.218.08:09:32.36#ibcon#read 3, iclass 27, count 2 2006.218.08:09:32.36#ibcon#about to read 4, iclass 27, count 2 2006.218.08:09:32.36#ibcon#read 4, iclass 27, count 2 2006.218.08:09:32.36#ibcon#about to read 5, iclass 27, count 2 2006.218.08:09:32.36#ibcon#read 5, iclass 27, count 2 2006.218.08:09:32.36#ibcon#about to read 6, iclass 27, count 2 2006.218.08:09:32.36#ibcon#read 6, iclass 27, count 2 2006.218.08:09:32.36#ibcon#end of sib2, iclass 27, count 2 2006.218.08:09:32.36#ibcon#*mode == 0, iclass 27, count 2 2006.218.08:09:32.36#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.218.08:09:32.36#ibcon#[27=AT06-04\r\n] 2006.218.08:09:32.36#ibcon#*before write, iclass 27, count 2 2006.218.08:09:32.36#ibcon#enter sib2, iclass 27, count 2 2006.218.08:09:32.36#ibcon#flushed, iclass 27, count 2 2006.218.08:09:32.36#ibcon#about to write, iclass 27, count 2 2006.218.08:09:32.36#ibcon#wrote, iclass 27, count 2 2006.218.08:09:32.36#ibcon#about to read 3, iclass 27, count 2 2006.218.08:09:32.39#ibcon#read 3, iclass 27, count 2 2006.218.08:09:32.39#ibcon#about to read 4, iclass 27, count 2 2006.218.08:09:32.39#ibcon#read 4, iclass 27, count 2 2006.218.08:09:32.39#ibcon#about to read 5, iclass 27, count 2 2006.218.08:09:32.39#ibcon#read 5, iclass 27, count 2 2006.218.08:09:32.39#ibcon#about to read 6, iclass 27, count 2 2006.218.08:09:32.39#ibcon#read 6, iclass 27, count 2 2006.218.08:09:32.39#ibcon#end of sib2, iclass 27, count 2 2006.218.08:09:32.39#ibcon#*after write, iclass 27, count 2 2006.218.08:09:32.39#ibcon#*before return 0, iclass 27, count 2 2006.218.08:09:32.39#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.218.08:09:32.39#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.218.08:09:32.39#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.218.08:09:32.39#ibcon#ireg 7 cls_cnt 0 2006.218.08:09:32.39#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.218.08:09:32.51#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.218.08:09:32.51#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.218.08:09:32.51#ibcon#enter wrdev, iclass 27, count 0 2006.218.08:09:32.51#ibcon#first serial, iclass 27, count 0 2006.218.08:09:32.51#ibcon#enter sib2, iclass 27, count 0 2006.218.08:09:32.51#ibcon#flushed, iclass 27, count 0 2006.218.08:09:32.51#ibcon#about to write, iclass 27, count 0 2006.218.08:09:32.51#ibcon#wrote, iclass 27, count 0 2006.218.08:09:32.51#ibcon#about to read 3, iclass 27, count 0 2006.218.08:09:32.53#ibcon#read 3, iclass 27, count 0 2006.218.08:09:32.53#ibcon#about to read 4, iclass 27, count 0 2006.218.08:09:32.53#ibcon#read 4, iclass 27, count 0 2006.218.08:09:32.53#ibcon#about to read 5, iclass 27, count 0 2006.218.08:09:32.53#ibcon#read 5, iclass 27, count 0 2006.218.08:09:32.53#ibcon#about to read 6, iclass 27, count 0 2006.218.08:09:32.53#ibcon#read 6, iclass 27, count 0 2006.218.08:09:32.53#ibcon#end of sib2, iclass 27, count 0 2006.218.08:09:32.53#ibcon#*mode == 0, iclass 27, count 0 2006.218.08:09:32.53#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.218.08:09:32.53#ibcon#[27=USB\r\n] 2006.218.08:09:32.53#ibcon#*before write, iclass 27, count 0 2006.218.08:09:32.53#ibcon#enter sib2, iclass 27, count 0 2006.218.08:09:32.53#ibcon#flushed, iclass 27, count 0 2006.218.08:09:32.53#ibcon#about to write, iclass 27, count 0 2006.218.08:09:32.53#ibcon#wrote, iclass 27, count 0 2006.218.08:09:32.53#ibcon#about to read 3, iclass 27, count 0 2006.218.08:09:32.56#ibcon#read 3, iclass 27, count 0 2006.218.08:09:32.56#ibcon#about to read 4, iclass 27, count 0 2006.218.08:09:32.56#ibcon#read 4, iclass 27, count 0 2006.218.08:09:32.56#ibcon#about to read 5, iclass 27, count 0 2006.218.08:09:32.56#ibcon#read 5, iclass 27, count 0 2006.218.08:09:32.56#ibcon#about to read 6, iclass 27, count 0 2006.218.08:09:32.56#ibcon#read 6, iclass 27, count 0 2006.218.08:09:32.56#ibcon#end of sib2, iclass 27, count 0 2006.218.08:09:32.56#ibcon#*after write, iclass 27, count 0 2006.218.08:09:32.56#ibcon#*before return 0, iclass 27, count 0 2006.218.08:09:32.56#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.218.08:09:32.56#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.218.08:09:32.56#ibcon#about to clear, iclass 27 cls_cnt 0 2006.218.08:09:32.56#ibcon#cleared, iclass 27 cls_cnt 0 2006.218.08:09:32.56$vc4f8/vabw=wide 2006.218.08:09:32.56#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.218.08:09:32.56#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.218.08:09:32.56#ibcon#ireg 8 cls_cnt 0 2006.218.08:09:32.56#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.218.08:09:32.56#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.218.08:09:32.56#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.218.08:09:32.56#ibcon#enter wrdev, iclass 29, count 0 2006.218.08:09:32.56#ibcon#first serial, iclass 29, count 0 2006.218.08:09:32.56#ibcon#enter sib2, iclass 29, count 0 2006.218.08:09:32.56#ibcon#flushed, iclass 29, count 0 2006.218.08:09:32.56#ibcon#about to write, iclass 29, count 0 2006.218.08:09:32.56#ibcon#wrote, iclass 29, count 0 2006.218.08:09:32.56#ibcon#about to read 3, iclass 29, count 0 2006.218.08:09:32.58#ibcon#read 3, iclass 29, count 0 2006.218.08:09:32.58#ibcon#about to read 4, iclass 29, count 0 2006.218.08:09:32.58#ibcon#read 4, iclass 29, count 0 2006.218.08:09:32.58#ibcon#about to read 5, iclass 29, count 0 2006.218.08:09:32.58#ibcon#read 5, iclass 29, count 0 2006.218.08:09:32.58#ibcon#about to read 6, iclass 29, count 0 2006.218.08:09:32.58#ibcon#read 6, iclass 29, count 0 2006.218.08:09:32.58#ibcon#end of sib2, iclass 29, count 0 2006.218.08:09:32.58#ibcon#*mode == 0, iclass 29, count 0 2006.218.08:09:32.58#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.218.08:09:32.58#ibcon#[25=BW32\r\n] 2006.218.08:09:32.58#ibcon#*before write, iclass 29, count 0 2006.218.08:09:32.58#ibcon#enter sib2, iclass 29, count 0 2006.218.08:09:32.58#ibcon#flushed, iclass 29, count 0 2006.218.08:09:32.58#ibcon#about to write, iclass 29, count 0 2006.218.08:09:32.58#ibcon#wrote, iclass 29, count 0 2006.218.08:09:32.58#ibcon#about to read 3, iclass 29, count 0 2006.218.08:09:32.61#ibcon#read 3, iclass 29, count 0 2006.218.08:09:32.61#ibcon#about to read 4, iclass 29, count 0 2006.218.08:09:32.61#ibcon#read 4, iclass 29, count 0 2006.218.08:09:32.61#ibcon#about to read 5, iclass 29, count 0 2006.218.08:09:32.61#ibcon#read 5, iclass 29, count 0 2006.218.08:09:32.61#ibcon#about to read 6, iclass 29, count 0 2006.218.08:09:32.61#ibcon#read 6, iclass 29, count 0 2006.218.08:09:32.61#ibcon#end of sib2, iclass 29, count 0 2006.218.08:09:32.61#ibcon#*after write, iclass 29, count 0 2006.218.08:09:32.61#ibcon#*before return 0, iclass 29, count 0 2006.218.08:09:32.61#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.218.08:09:32.61#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.218.08:09:32.61#ibcon#about to clear, iclass 29 cls_cnt 0 2006.218.08:09:32.61#ibcon#cleared, iclass 29 cls_cnt 0 2006.218.08:09:32.61$vc4f8/vbbw=wide 2006.218.08:09:32.61#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.218.08:09:32.61#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.218.08:09:32.61#ibcon#ireg 8 cls_cnt 0 2006.218.08:09:32.61#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.218.08:09:32.68#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.218.08:09:32.68#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.218.08:09:32.68#ibcon#enter wrdev, iclass 31, count 0 2006.218.08:09:32.68#ibcon#first serial, iclass 31, count 0 2006.218.08:09:32.68#ibcon#enter sib2, iclass 31, count 0 2006.218.08:09:32.68#ibcon#flushed, iclass 31, count 0 2006.218.08:09:32.68#ibcon#about to write, iclass 31, count 0 2006.218.08:09:32.68#ibcon#wrote, iclass 31, count 0 2006.218.08:09:32.68#ibcon#about to read 3, iclass 31, count 0 2006.218.08:09:32.70#ibcon#read 3, iclass 31, count 0 2006.218.08:09:32.70#ibcon#about to read 4, iclass 31, count 0 2006.218.08:09:32.70#ibcon#read 4, iclass 31, count 0 2006.218.08:09:32.70#ibcon#about to read 5, iclass 31, count 0 2006.218.08:09:32.70#ibcon#read 5, iclass 31, count 0 2006.218.08:09:32.70#ibcon#about to read 6, iclass 31, count 0 2006.218.08:09:32.70#ibcon#read 6, iclass 31, count 0 2006.218.08:09:32.70#ibcon#end of sib2, iclass 31, count 0 2006.218.08:09:32.70#ibcon#*mode == 0, iclass 31, count 0 2006.218.08:09:32.70#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.218.08:09:32.70#ibcon#[27=BW32\r\n] 2006.218.08:09:32.70#ibcon#*before write, iclass 31, count 0 2006.218.08:09:32.70#ibcon#enter sib2, iclass 31, count 0 2006.218.08:09:32.70#ibcon#flushed, iclass 31, count 0 2006.218.08:09:32.70#ibcon#about to write, iclass 31, count 0 2006.218.08:09:32.70#ibcon#wrote, iclass 31, count 0 2006.218.08:09:32.70#ibcon#about to read 3, iclass 31, count 0 2006.218.08:09:32.73#ibcon#read 3, iclass 31, count 0 2006.218.08:09:32.73#ibcon#about to read 4, iclass 31, count 0 2006.218.08:09:32.73#ibcon#read 4, iclass 31, count 0 2006.218.08:09:32.73#ibcon#about to read 5, iclass 31, count 0 2006.218.08:09:32.73#ibcon#read 5, iclass 31, count 0 2006.218.08:09:32.73#ibcon#about to read 6, iclass 31, count 0 2006.218.08:09:32.73#ibcon#read 6, iclass 31, count 0 2006.218.08:09:32.73#ibcon#end of sib2, iclass 31, count 0 2006.218.08:09:32.73#ibcon#*after write, iclass 31, count 0 2006.218.08:09:32.73#ibcon#*before return 0, iclass 31, count 0 2006.218.08:09:32.73#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.218.08:09:32.73#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.218.08:09:32.73#ibcon#about to clear, iclass 31 cls_cnt 0 2006.218.08:09:32.73#ibcon#cleared, iclass 31 cls_cnt 0 2006.218.08:09:32.73$4f8m12a/ifd4f 2006.218.08:09:32.73$ifd4f/lo= 2006.218.08:09:32.73$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.218.08:09:32.73$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.218.08:09:32.73$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.218.08:09:32.73$ifd4f/patch= 2006.218.08:09:32.73$ifd4f/patch=lo1,a1,a2,a3,a4 2006.218.08:09:32.73$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.218.08:09:32.73$ifd4f/patch=lo3,a5,a6,a7,a8 2006.218.08:09:32.73$4f8m12a/"form=m,16.000,1:2 2006.218.08:09:32.73$4f8m12a/"tpicd 2006.218.08:09:32.73$4f8m12a/echo=off 2006.218.08:09:32.73$4f8m12a/xlog=off 2006.218.08:09:32.73:!2006.218.08:10:10 2006.218.08:09:51.14#trakl#Source acquired 2006.218.08:09:53.14#flagr#flagr/antenna,acquired 2006.218.08:10:10.00:preob 2006.218.08:10:10.13/onsource/TRACKING 2006.218.08:10:10.13:!2006.218.08:10:20 2006.218.08:10:20.00:data_valid=on 2006.218.08:10:20.00:midob 2006.218.08:10:20.13/onsource/TRACKING 2006.218.08:10:20.13/wx/30.90,1007.5,73 2006.218.08:10:20.22/cable/+6.3849E-03 2006.218.08:10:21.31/va/01,05,usb,yes,33,35 2006.218.08:10:21.31/va/02,04,usb,yes,31,33 2006.218.08:10:21.31/va/03,04,usb,yes,29,30 2006.218.08:10:21.31/va/04,04,usb,yes,33,35 2006.218.08:10:21.31/va/05,07,usb,yes,35,37 2006.218.08:10:21.31/va/06,06,usb,yes,34,34 2006.218.08:10:21.31/va/07,06,usb,yes,35,35 2006.218.08:10:21.31/va/08,07,usb,yes,33,33 2006.218.08:10:21.54/valo/01,532.99,yes,locked 2006.218.08:10:21.54/valo/02,572.99,yes,locked 2006.218.08:10:21.54/valo/03,672.99,yes,locked 2006.218.08:10:21.54/valo/04,832.99,yes,locked 2006.218.08:10:21.54/valo/05,652.99,yes,locked 2006.218.08:10:21.54/valo/06,772.99,yes,locked 2006.218.08:10:21.54/valo/07,832.99,yes,locked 2006.218.08:10:21.54/valo/08,852.99,yes,locked 2006.218.08:10:22.63/vb/01,04,usb,yes,31,30 2006.218.08:10:22.63/vb/02,04,usb,yes,33,34 2006.218.08:10:22.63/vb/03,04,usb,yes,29,33 2006.218.08:10:22.63/vb/04,04,usb,yes,30,30 2006.218.08:10:22.63/vb/05,04,usb,yes,28,33 2006.218.08:10:22.63/vb/06,04,usb,yes,29,32 2006.218.08:10:22.63/vb/07,04,usb,yes,32,32 2006.218.08:10:22.63/vb/08,04,usb,yes,29,33 2006.218.08:10:22.86/vblo/01,632.99,yes,locked 2006.218.08:10:22.86/vblo/02,640.99,yes,locked 2006.218.08:10:22.86/vblo/03,656.99,yes,locked 2006.218.08:10:22.86/vblo/04,712.99,yes,locked 2006.218.08:10:22.86/vblo/05,744.99,yes,locked 2006.218.08:10:22.86/vblo/06,752.99,yes,locked 2006.218.08:10:22.86/vblo/07,734.99,yes,locked 2006.218.08:10:22.86/vblo/08,744.99,yes,locked 2006.218.08:10:23.01/vabw/8 2006.218.08:10:23.16/vbbw/8 2006.218.08:10:23.25/xfe/off,on,16.0 2006.218.08:10:23.62/ifatt/23,28,28,28 2006.218.08:10:24.07/fmout-gps/S +4.61E-07 2006.218.08:10:24.14:!2006.218.08:11:20 2006.218.08:11:20.01:data_valid=off 2006.218.08:11:20.01:postob 2006.218.08:11:20.19/cable/+6.3850E-03 2006.218.08:11:20.19/wx/30.88,1007.6,73 2006.218.08:11:21.08/fmout-gps/S +4.63E-07 2006.218.08:11:21.08:scan_name=218-0812,k06218,60 2006.218.08:11:21.09:source=0602+673,060752.67,672055.4,2000.0,cw 2006.218.08:11:21.13#flagr#flagr/antenna,new-source 2006.218.08:11:22.13:checkk5 2006.218.08:11:22.50/chk_autoobs//k5ts1/ autoobs is running! 2006.218.08:11:22.88/chk_autoobs//k5ts2/ autoobs is running! 2006.218.08:11:23.26/chk_autoobs//k5ts3/ autoobs is running! 2006.218.08:11:23.63/chk_autoobs//k5ts4/ autoobs is running! 2006.218.08:11:23.99/chk_obsdata//k5ts1/T2180810??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.218.08:11:24.37/chk_obsdata//k5ts2/T2180810??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.218.08:11:24.73/chk_obsdata//k5ts3/T2180810??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.218.08:11:25.10/chk_obsdata//k5ts4/T2180810??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.218.08:11:25.79/k5log//k5ts1_log_newline 2006.218.08:11:26.47/k5log//k5ts2_log_newline 2006.218.08:11:27.17/k5log//k5ts3_log_newline 2006.218.08:11:27.85/k5log//k5ts4_log_newline 2006.218.08:11:27.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.218.08:11:27.88:4f8m12a=2 2006.218.08:11:27.88$4f8m12a/echo=on 2006.218.08:11:27.88$4f8m12a/pcalon 2006.218.08:11:27.88$pcalon/"no phase cal control is implemented here 2006.218.08:11:27.88$4f8m12a/"tpicd=stop 2006.218.08:11:27.88$4f8m12a/vc4f8 2006.218.08:11:27.88$vc4f8/valo=1,532.99 2006.218.08:11:27.88#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.218.08:11:27.88#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.218.08:11:27.88#ibcon#ireg 17 cls_cnt 0 2006.218.08:11:27.88#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.218.08:11:27.88#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.218.08:11:27.88#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.218.08:11:27.88#ibcon#enter wrdev, iclass 10, count 0 2006.218.08:11:27.88#ibcon#first serial, iclass 10, count 0 2006.218.08:11:27.88#ibcon#enter sib2, iclass 10, count 0 2006.218.08:11:27.88#ibcon#flushed, iclass 10, count 0 2006.218.08:11:27.88#ibcon#about to write, iclass 10, count 0 2006.218.08:11:27.88#ibcon#wrote, iclass 10, count 0 2006.218.08:11:27.88#ibcon#about to read 3, iclass 10, count 0 2006.218.08:11:27.92#ibcon#read 3, iclass 10, count 0 2006.218.08:11:27.92#ibcon#about to read 4, iclass 10, count 0 2006.218.08:11:27.92#ibcon#read 4, iclass 10, count 0 2006.218.08:11:27.92#ibcon#about to read 5, iclass 10, count 0 2006.218.08:11:27.92#ibcon#read 5, iclass 10, count 0 2006.218.08:11:27.92#ibcon#about to read 6, iclass 10, count 0 2006.218.08:11:27.92#ibcon#read 6, iclass 10, count 0 2006.218.08:11:27.92#ibcon#end of sib2, iclass 10, count 0 2006.218.08:11:27.92#ibcon#*mode == 0, iclass 10, count 0 2006.218.08:11:27.92#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.218.08:11:27.92#ibcon#[26=FRQ=01,532.99\r\n] 2006.218.08:11:27.92#ibcon#*before write, iclass 10, count 0 2006.218.08:11:27.92#ibcon#enter sib2, iclass 10, count 0 2006.218.08:11:27.92#ibcon#flushed, iclass 10, count 0 2006.218.08:11:27.92#ibcon#about to write, iclass 10, count 0 2006.218.08:11:27.92#ibcon#wrote, iclass 10, count 0 2006.218.08:11:27.92#ibcon#about to read 3, iclass 10, count 0 2006.218.08:11:27.97#ibcon#read 3, iclass 10, count 0 2006.218.08:11:27.97#ibcon#about to read 4, iclass 10, count 0 2006.218.08:11:27.97#ibcon#read 4, iclass 10, count 0 2006.218.08:11:27.97#ibcon#about to read 5, iclass 10, count 0 2006.218.08:11:27.97#ibcon#read 5, iclass 10, count 0 2006.218.08:11:27.97#ibcon#about to read 6, iclass 10, count 0 2006.218.08:11:27.97#ibcon#read 6, iclass 10, count 0 2006.218.08:11:27.97#ibcon#end of sib2, iclass 10, count 0 2006.218.08:11:27.97#ibcon#*after write, iclass 10, count 0 2006.218.08:11:27.97#ibcon#*before return 0, iclass 10, count 0 2006.218.08:11:27.97#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.218.08:11:27.97#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.218.08:11:27.97#ibcon#about to clear, iclass 10 cls_cnt 0 2006.218.08:11:27.97#ibcon#cleared, iclass 10 cls_cnt 0 2006.218.08:11:27.97$vc4f8/va=1,5 2006.218.08:11:27.97#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.218.08:11:27.97#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.218.08:11:27.97#ibcon#ireg 11 cls_cnt 2 2006.218.08:11:27.97#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.218.08:11:27.97#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.218.08:11:27.97#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.218.08:11:27.97#ibcon#enter wrdev, iclass 12, count 2 2006.218.08:11:27.97#ibcon#first serial, iclass 12, count 2 2006.218.08:11:27.97#ibcon#enter sib2, iclass 12, count 2 2006.218.08:11:27.97#ibcon#flushed, iclass 12, count 2 2006.218.08:11:27.97#ibcon#about to write, iclass 12, count 2 2006.218.08:11:27.97#ibcon#wrote, iclass 12, count 2 2006.218.08:11:27.97#ibcon#about to read 3, iclass 12, count 2 2006.218.08:11:27.99#ibcon#read 3, iclass 12, count 2 2006.218.08:11:27.99#ibcon#about to read 4, iclass 12, count 2 2006.218.08:11:27.99#ibcon#read 4, iclass 12, count 2 2006.218.08:11:27.99#ibcon#about to read 5, iclass 12, count 2 2006.218.08:11:27.99#ibcon#read 5, iclass 12, count 2 2006.218.08:11:27.99#ibcon#about to read 6, iclass 12, count 2 2006.218.08:11:27.99#ibcon#read 6, iclass 12, count 2 2006.218.08:11:27.99#ibcon#end of sib2, iclass 12, count 2 2006.218.08:11:27.99#ibcon#*mode == 0, iclass 12, count 2 2006.218.08:11:27.99#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.218.08:11:27.99#ibcon#[25=AT01-05\r\n] 2006.218.08:11:27.99#ibcon#*before write, iclass 12, count 2 2006.218.08:11:27.99#ibcon#enter sib2, iclass 12, count 2 2006.218.08:11:27.99#ibcon#flushed, iclass 12, count 2 2006.218.08:11:27.99#ibcon#about to write, iclass 12, count 2 2006.218.08:11:27.99#ibcon#wrote, iclass 12, count 2 2006.218.08:11:27.99#ibcon#about to read 3, iclass 12, count 2 2006.218.08:11:28.03#ibcon#read 3, iclass 12, count 2 2006.218.08:11:28.03#ibcon#about to read 4, iclass 12, count 2 2006.218.08:11:28.03#ibcon#read 4, iclass 12, count 2 2006.218.08:11:28.03#ibcon#about to read 5, iclass 12, count 2 2006.218.08:11:28.03#ibcon#read 5, iclass 12, count 2 2006.218.08:11:28.03#ibcon#about to read 6, iclass 12, count 2 2006.218.08:11:28.03#ibcon#read 6, iclass 12, count 2 2006.218.08:11:28.03#ibcon#end of sib2, iclass 12, count 2 2006.218.08:11:28.03#ibcon#*after write, iclass 12, count 2 2006.218.08:11:28.03#ibcon#*before return 0, iclass 12, count 2 2006.218.08:11:28.03#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.218.08:11:28.03#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.218.08:11:28.03#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.218.08:11:28.03#ibcon#ireg 7 cls_cnt 0 2006.218.08:11:28.03#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.218.08:11:28.15#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.218.08:11:28.15#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.218.08:11:28.15#ibcon#enter wrdev, iclass 12, count 0 2006.218.08:11:28.15#ibcon#first serial, iclass 12, count 0 2006.218.08:11:28.15#ibcon#enter sib2, iclass 12, count 0 2006.218.08:11:28.15#ibcon#flushed, iclass 12, count 0 2006.218.08:11:28.15#ibcon#about to write, iclass 12, count 0 2006.218.08:11:28.15#ibcon#wrote, iclass 12, count 0 2006.218.08:11:28.15#ibcon#about to read 3, iclass 12, count 0 2006.218.08:11:28.17#ibcon#read 3, iclass 12, count 0 2006.218.08:11:28.17#ibcon#about to read 4, iclass 12, count 0 2006.218.08:11:28.17#ibcon#read 4, iclass 12, count 0 2006.218.08:11:28.17#ibcon#about to read 5, iclass 12, count 0 2006.218.08:11:28.17#ibcon#read 5, iclass 12, count 0 2006.218.08:11:28.17#ibcon#about to read 6, iclass 12, count 0 2006.218.08:11:28.17#ibcon#read 6, iclass 12, count 0 2006.218.08:11:28.17#ibcon#end of sib2, iclass 12, count 0 2006.218.08:11:28.17#ibcon#*mode == 0, iclass 12, count 0 2006.218.08:11:28.17#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.218.08:11:28.17#ibcon#[25=USB\r\n] 2006.218.08:11:28.17#ibcon#*before write, iclass 12, count 0 2006.218.08:11:28.17#ibcon#enter sib2, iclass 12, count 0 2006.218.08:11:28.17#ibcon#flushed, iclass 12, count 0 2006.218.08:11:28.17#ibcon#about to write, iclass 12, count 0 2006.218.08:11:28.17#ibcon#wrote, iclass 12, count 0 2006.218.08:11:28.17#ibcon#about to read 3, iclass 12, count 0 2006.218.08:11:28.20#ibcon#read 3, iclass 12, count 0 2006.218.08:11:28.20#ibcon#about to read 4, iclass 12, count 0 2006.218.08:11:28.20#ibcon#read 4, iclass 12, count 0 2006.218.08:11:28.20#ibcon#about to read 5, iclass 12, count 0 2006.218.08:11:28.20#ibcon#read 5, iclass 12, count 0 2006.218.08:11:28.20#ibcon#about to read 6, iclass 12, count 0 2006.218.08:11:28.20#ibcon#read 6, iclass 12, count 0 2006.218.08:11:28.20#ibcon#end of sib2, iclass 12, count 0 2006.218.08:11:28.20#ibcon#*after write, iclass 12, count 0 2006.218.08:11:28.20#ibcon#*before return 0, iclass 12, count 0 2006.218.08:11:28.20#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.218.08:11:28.20#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.218.08:11:28.20#ibcon#about to clear, iclass 12 cls_cnt 0 2006.218.08:11:28.20#ibcon#cleared, iclass 12 cls_cnt 0 2006.218.08:11:28.20$vc4f8/valo=2,572.99 2006.218.08:11:28.20#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.218.08:11:28.20#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.218.08:11:28.20#ibcon#ireg 17 cls_cnt 0 2006.218.08:11:28.20#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.218.08:11:28.20#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.218.08:11:28.20#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.218.08:11:28.20#ibcon#enter wrdev, iclass 14, count 0 2006.218.08:11:28.20#ibcon#first serial, iclass 14, count 0 2006.218.08:11:28.20#ibcon#enter sib2, iclass 14, count 0 2006.218.08:11:28.20#ibcon#flushed, iclass 14, count 0 2006.218.08:11:28.20#ibcon#about to write, iclass 14, count 0 2006.218.08:11:28.20#ibcon#wrote, iclass 14, count 0 2006.218.08:11:28.20#ibcon#about to read 3, iclass 14, count 0 2006.218.08:11:28.22#ibcon#read 3, iclass 14, count 0 2006.218.08:11:28.22#ibcon#about to read 4, iclass 14, count 0 2006.218.08:11:28.22#ibcon#read 4, iclass 14, count 0 2006.218.08:11:28.22#ibcon#about to read 5, iclass 14, count 0 2006.218.08:11:28.22#ibcon#read 5, iclass 14, count 0 2006.218.08:11:28.22#ibcon#about to read 6, iclass 14, count 0 2006.218.08:11:28.22#ibcon#read 6, iclass 14, count 0 2006.218.08:11:28.22#ibcon#end of sib2, iclass 14, count 0 2006.218.08:11:28.22#ibcon#*mode == 0, iclass 14, count 0 2006.218.08:11:28.22#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.218.08:11:28.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.218.08:11:28.22#ibcon#*before write, iclass 14, count 0 2006.218.08:11:28.22#ibcon#enter sib2, iclass 14, count 0 2006.218.08:11:28.22#ibcon#flushed, iclass 14, count 0 2006.218.08:11:28.22#ibcon#about to write, iclass 14, count 0 2006.218.08:11:28.22#ibcon#wrote, iclass 14, count 0 2006.218.08:11:28.22#ibcon#about to read 3, iclass 14, count 0 2006.218.08:11:28.26#ibcon#read 3, iclass 14, count 0 2006.218.08:11:28.26#ibcon#about to read 4, iclass 14, count 0 2006.218.08:11:28.26#ibcon#read 4, iclass 14, count 0 2006.218.08:11:28.26#ibcon#about to read 5, iclass 14, count 0 2006.218.08:11:28.26#ibcon#read 5, iclass 14, count 0 2006.218.08:11:28.26#ibcon#about to read 6, iclass 14, count 0 2006.218.08:11:28.26#ibcon#read 6, iclass 14, count 0 2006.218.08:11:28.26#ibcon#end of sib2, iclass 14, count 0 2006.218.08:11:28.26#ibcon#*after write, iclass 14, count 0 2006.218.08:11:28.26#ibcon#*before return 0, iclass 14, count 0 2006.218.08:11:28.26#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.218.08:11:28.26#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.218.08:11:28.26#ibcon#about to clear, iclass 14 cls_cnt 0 2006.218.08:11:28.26#ibcon#cleared, iclass 14 cls_cnt 0 2006.218.08:11:28.26$vc4f8/va=2,4 2006.218.08:11:28.26#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.218.08:11:28.26#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.218.08:11:28.26#ibcon#ireg 11 cls_cnt 2 2006.218.08:11:28.26#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.218.08:11:28.32#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.218.08:11:28.32#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.218.08:11:28.32#ibcon#enter wrdev, iclass 16, count 2 2006.218.08:11:28.32#ibcon#first serial, iclass 16, count 2 2006.218.08:11:28.32#ibcon#enter sib2, iclass 16, count 2 2006.218.08:11:28.32#ibcon#flushed, iclass 16, count 2 2006.218.08:11:28.32#ibcon#about to write, iclass 16, count 2 2006.218.08:11:28.32#ibcon#wrote, iclass 16, count 2 2006.218.08:11:28.32#ibcon#about to read 3, iclass 16, count 2 2006.218.08:11:28.34#ibcon#read 3, iclass 16, count 2 2006.218.08:11:28.34#ibcon#about to read 4, iclass 16, count 2 2006.218.08:11:28.34#ibcon#read 4, iclass 16, count 2 2006.218.08:11:28.34#ibcon#about to read 5, iclass 16, count 2 2006.218.08:11:28.34#ibcon#read 5, iclass 16, count 2 2006.218.08:11:28.34#ibcon#about to read 6, iclass 16, count 2 2006.218.08:11:28.34#ibcon#read 6, iclass 16, count 2 2006.218.08:11:28.34#ibcon#end of sib2, iclass 16, count 2 2006.218.08:11:28.34#ibcon#*mode == 0, iclass 16, count 2 2006.218.08:11:28.34#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.218.08:11:28.34#ibcon#[25=AT02-04\r\n] 2006.218.08:11:28.34#ibcon#*before write, iclass 16, count 2 2006.218.08:11:28.34#ibcon#enter sib2, iclass 16, count 2 2006.218.08:11:28.34#ibcon#flushed, iclass 16, count 2 2006.218.08:11:28.34#ibcon#about to write, iclass 16, count 2 2006.218.08:11:28.34#ibcon#wrote, iclass 16, count 2 2006.218.08:11:28.34#ibcon#about to read 3, iclass 16, count 2 2006.218.08:11:28.37#ibcon#read 3, iclass 16, count 2 2006.218.08:11:28.37#ibcon#about to read 4, iclass 16, count 2 2006.218.08:11:28.37#ibcon#read 4, iclass 16, count 2 2006.218.08:11:28.37#ibcon#about to read 5, iclass 16, count 2 2006.218.08:11:28.37#ibcon#read 5, iclass 16, count 2 2006.218.08:11:28.37#ibcon#about to read 6, iclass 16, count 2 2006.218.08:11:28.37#ibcon#read 6, iclass 16, count 2 2006.218.08:11:28.37#ibcon#end of sib2, iclass 16, count 2 2006.218.08:11:28.37#ibcon#*after write, iclass 16, count 2 2006.218.08:11:28.37#ibcon#*before return 0, iclass 16, count 2 2006.218.08:11:28.37#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.218.08:11:28.37#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.218.08:11:28.37#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.218.08:11:28.37#ibcon#ireg 7 cls_cnt 0 2006.218.08:11:28.37#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.218.08:11:28.49#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.218.08:11:28.49#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.218.08:11:28.49#ibcon#enter wrdev, iclass 16, count 0 2006.218.08:11:28.49#ibcon#first serial, iclass 16, count 0 2006.218.08:11:28.49#ibcon#enter sib2, iclass 16, count 0 2006.218.08:11:28.49#ibcon#flushed, iclass 16, count 0 2006.218.08:11:28.49#ibcon#about to write, iclass 16, count 0 2006.218.08:11:28.49#ibcon#wrote, iclass 16, count 0 2006.218.08:11:28.49#ibcon#about to read 3, iclass 16, count 0 2006.218.08:11:28.51#ibcon#read 3, iclass 16, count 0 2006.218.08:11:28.51#ibcon#about to read 4, iclass 16, count 0 2006.218.08:11:28.51#ibcon#read 4, iclass 16, count 0 2006.218.08:11:28.51#ibcon#about to read 5, iclass 16, count 0 2006.218.08:11:28.51#ibcon#read 5, iclass 16, count 0 2006.218.08:11:28.51#ibcon#about to read 6, iclass 16, count 0 2006.218.08:11:28.51#ibcon#read 6, iclass 16, count 0 2006.218.08:11:28.51#ibcon#end of sib2, iclass 16, count 0 2006.218.08:11:28.51#ibcon#*mode == 0, iclass 16, count 0 2006.218.08:11:28.51#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.218.08:11:28.51#ibcon#[25=USB\r\n] 2006.218.08:11:28.51#ibcon#*before write, iclass 16, count 0 2006.218.08:11:28.51#ibcon#enter sib2, iclass 16, count 0 2006.218.08:11:28.51#ibcon#flushed, iclass 16, count 0 2006.218.08:11:28.51#ibcon#about to write, iclass 16, count 0 2006.218.08:11:28.51#ibcon#wrote, iclass 16, count 0 2006.218.08:11:28.51#ibcon#about to read 3, iclass 16, count 0 2006.218.08:11:28.54#ibcon#read 3, iclass 16, count 0 2006.218.08:11:28.54#ibcon#about to read 4, iclass 16, count 0 2006.218.08:11:28.54#ibcon#read 4, iclass 16, count 0 2006.218.08:11:28.54#ibcon#about to read 5, iclass 16, count 0 2006.218.08:11:28.54#ibcon#read 5, iclass 16, count 0 2006.218.08:11:28.54#ibcon#about to read 6, iclass 16, count 0 2006.218.08:11:28.54#ibcon#read 6, iclass 16, count 0 2006.218.08:11:28.54#ibcon#end of sib2, iclass 16, count 0 2006.218.08:11:28.54#ibcon#*after write, iclass 16, count 0 2006.218.08:11:28.54#ibcon#*before return 0, iclass 16, count 0 2006.218.08:11:28.54#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.218.08:11:28.54#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.218.08:11:28.54#ibcon#about to clear, iclass 16 cls_cnt 0 2006.218.08:11:28.54#ibcon#cleared, iclass 16 cls_cnt 0 2006.218.08:11:28.54$vc4f8/valo=3,672.99 2006.218.08:11:28.54#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.218.08:11:28.54#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.218.08:11:28.54#ibcon#ireg 17 cls_cnt 0 2006.218.08:11:28.54#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.218.08:11:28.54#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.218.08:11:28.54#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.218.08:11:28.54#ibcon#enter wrdev, iclass 18, count 0 2006.218.08:11:28.54#ibcon#first serial, iclass 18, count 0 2006.218.08:11:28.54#ibcon#enter sib2, iclass 18, count 0 2006.218.08:11:28.54#ibcon#flushed, iclass 18, count 0 2006.218.08:11:28.54#ibcon#about to write, iclass 18, count 0 2006.218.08:11:28.54#ibcon#wrote, iclass 18, count 0 2006.218.08:11:28.54#ibcon#about to read 3, iclass 18, count 0 2006.218.08:11:28.56#ibcon#read 3, iclass 18, count 0 2006.218.08:11:28.56#ibcon#about to read 4, iclass 18, count 0 2006.218.08:11:28.56#ibcon#read 4, iclass 18, count 0 2006.218.08:11:28.56#ibcon#about to read 5, iclass 18, count 0 2006.218.08:11:28.56#ibcon#read 5, iclass 18, count 0 2006.218.08:11:28.56#ibcon#about to read 6, iclass 18, count 0 2006.218.08:11:28.56#ibcon#read 6, iclass 18, count 0 2006.218.08:11:28.56#ibcon#end of sib2, iclass 18, count 0 2006.218.08:11:28.56#ibcon#*mode == 0, iclass 18, count 0 2006.218.08:11:28.56#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.218.08:11:28.56#ibcon#[26=FRQ=03,672.99\r\n] 2006.218.08:11:28.56#ibcon#*before write, iclass 18, count 0 2006.218.08:11:28.56#ibcon#enter sib2, iclass 18, count 0 2006.218.08:11:28.56#ibcon#flushed, iclass 18, count 0 2006.218.08:11:28.56#ibcon#about to write, iclass 18, count 0 2006.218.08:11:28.56#ibcon#wrote, iclass 18, count 0 2006.218.08:11:28.56#ibcon#about to read 3, iclass 18, count 0 2006.218.08:11:28.60#ibcon#read 3, iclass 18, count 0 2006.218.08:11:28.60#ibcon#about to read 4, iclass 18, count 0 2006.218.08:11:28.60#ibcon#read 4, iclass 18, count 0 2006.218.08:11:28.60#ibcon#about to read 5, iclass 18, count 0 2006.218.08:11:28.60#ibcon#read 5, iclass 18, count 0 2006.218.08:11:28.60#ibcon#about to read 6, iclass 18, count 0 2006.218.08:11:28.60#ibcon#read 6, iclass 18, count 0 2006.218.08:11:28.60#ibcon#end of sib2, iclass 18, count 0 2006.218.08:11:28.60#ibcon#*after write, iclass 18, count 0 2006.218.08:11:28.60#ibcon#*before return 0, iclass 18, count 0 2006.218.08:11:28.60#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.218.08:11:28.60#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.218.08:11:28.60#ibcon#about to clear, iclass 18 cls_cnt 0 2006.218.08:11:28.60#ibcon#cleared, iclass 18 cls_cnt 0 2006.218.08:11:28.60$vc4f8/va=3,4 2006.218.08:11:28.60#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.218.08:11:28.60#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.218.08:11:28.60#ibcon#ireg 11 cls_cnt 2 2006.218.08:11:28.60#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.218.08:11:28.66#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.218.08:11:28.66#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.218.08:11:28.66#ibcon#enter wrdev, iclass 20, count 2 2006.218.08:11:28.66#ibcon#first serial, iclass 20, count 2 2006.218.08:11:28.66#ibcon#enter sib2, iclass 20, count 2 2006.218.08:11:28.66#ibcon#flushed, iclass 20, count 2 2006.218.08:11:28.66#ibcon#about to write, iclass 20, count 2 2006.218.08:11:28.66#ibcon#wrote, iclass 20, count 2 2006.218.08:11:28.66#ibcon#about to read 3, iclass 20, count 2 2006.218.08:11:28.69#ibcon#read 3, iclass 20, count 2 2006.218.08:11:28.69#ibcon#about to read 4, iclass 20, count 2 2006.218.08:11:28.69#ibcon#read 4, iclass 20, count 2 2006.218.08:11:28.69#ibcon#about to read 5, iclass 20, count 2 2006.218.08:11:28.69#ibcon#read 5, iclass 20, count 2 2006.218.08:11:28.69#ibcon#about to read 6, iclass 20, count 2 2006.218.08:11:28.69#ibcon#read 6, iclass 20, count 2 2006.218.08:11:28.69#ibcon#end of sib2, iclass 20, count 2 2006.218.08:11:28.69#ibcon#*mode == 0, iclass 20, count 2 2006.218.08:11:28.69#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.218.08:11:28.69#ibcon#[25=AT03-04\r\n] 2006.218.08:11:28.69#ibcon#*before write, iclass 20, count 2 2006.218.08:11:28.69#ibcon#enter sib2, iclass 20, count 2 2006.218.08:11:28.69#ibcon#flushed, iclass 20, count 2 2006.218.08:11:28.69#ibcon#about to write, iclass 20, count 2 2006.218.08:11:28.69#ibcon#wrote, iclass 20, count 2 2006.218.08:11:28.69#ibcon#about to read 3, iclass 20, count 2 2006.218.08:11:28.72#ibcon#read 3, iclass 20, count 2 2006.218.08:11:28.72#ibcon#about to read 4, iclass 20, count 2 2006.218.08:11:28.72#ibcon#read 4, iclass 20, count 2 2006.218.08:11:28.72#ibcon#about to read 5, iclass 20, count 2 2006.218.08:11:28.72#ibcon#read 5, iclass 20, count 2 2006.218.08:11:28.72#ibcon#about to read 6, iclass 20, count 2 2006.218.08:11:28.72#ibcon#read 6, iclass 20, count 2 2006.218.08:11:28.72#ibcon#end of sib2, iclass 20, count 2 2006.218.08:11:28.72#ibcon#*after write, iclass 20, count 2 2006.218.08:11:28.72#ibcon#*before return 0, iclass 20, count 2 2006.218.08:11:28.72#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.218.08:11:28.72#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.218.08:11:28.72#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.218.08:11:28.72#ibcon#ireg 7 cls_cnt 0 2006.218.08:11:28.72#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.218.08:11:28.84#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.218.08:11:28.84#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.218.08:11:28.84#ibcon#enter wrdev, iclass 20, count 0 2006.218.08:11:28.84#ibcon#first serial, iclass 20, count 0 2006.218.08:11:28.84#ibcon#enter sib2, iclass 20, count 0 2006.218.08:11:28.84#ibcon#flushed, iclass 20, count 0 2006.218.08:11:28.84#ibcon#about to write, iclass 20, count 0 2006.218.08:11:28.84#ibcon#wrote, iclass 20, count 0 2006.218.08:11:28.84#ibcon#about to read 3, iclass 20, count 0 2006.218.08:11:28.86#ibcon#read 3, iclass 20, count 0 2006.218.08:11:28.86#ibcon#about to read 4, iclass 20, count 0 2006.218.08:11:28.86#ibcon#read 4, iclass 20, count 0 2006.218.08:11:28.86#ibcon#about to read 5, iclass 20, count 0 2006.218.08:11:28.86#ibcon#read 5, iclass 20, count 0 2006.218.08:11:28.86#ibcon#about to read 6, iclass 20, count 0 2006.218.08:11:28.86#ibcon#read 6, iclass 20, count 0 2006.218.08:11:28.86#ibcon#end of sib2, iclass 20, count 0 2006.218.08:11:28.86#ibcon#*mode == 0, iclass 20, count 0 2006.218.08:11:28.86#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.218.08:11:28.86#ibcon#[25=USB\r\n] 2006.218.08:11:28.86#ibcon#*before write, iclass 20, count 0 2006.218.08:11:28.86#ibcon#enter sib2, iclass 20, count 0 2006.218.08:11:28.86#ibcon#flushed, iclass 20, count 0 2006.218.08:11:28.86#ibcon#about to write, iclass 20, count 0 2006.218.08:11:28.86#ibcon#wrote, iclass 20, count 0 2006.218.08:11:28.86#ibcon#about to read 3, iclass 20, count 0 2006.218.08:11:28.89#ibcon#read 3, iclass 20, count 0 2006.218.08:11:28.89#ibcon#about to read 4, iclass 20, count 0 2006.218.08:11:28.89#ibcon#read 4, iclass 20, count 0 2006.218.08:11:28.89#ibcon#about to read 5, iclass 20, count 0 2006.218.08:11:28.89#ibcon#read 5, iclass 20, count 0 2006.218.08:11:28.89#ibcon#about to read 6, iclass 20, count 0 2006.218.08:11:28.89#ibcon#read 6, iclass 20, count 0 2006.218.08:11:28.89#ibcon#end of sib2, iclass 20, count 0 2006.218.08:11:28.89#ibcon#*after write, iclass 20, count 0 2006.218.08:11:28.89#ibcon#*before return 0, iclass 20, count 0 2006.218.08:11:28.89#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.218.08:11:28.89#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.218.08:11:28.89#ibcon#about to clear, iclass 20 cls_cnt 0 2006.218.08:11:28.89#ibcon#cleared, iclass 20 cls_cnt 0 2006.218.08:11:28.89$vc4f8/valo=4,832.99 2006.218.08:11:28.89#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.218.08:11:28.89#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.218.08:11:28.89#ibcon#ireg 17 cls_cnt 0 2006.218.08:11:28.89#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.218.08:11:28.89#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.218.08:11:28.89#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.218.08:11:28.89#ibcon#enter wrdev, iclass 22, count 0 2006.218.08:11:28.89#ibcon#first serial, iclass 22, count 0 2006.218.08:11:28.89#ibcon#enter sib2, iclass 22, count 0 2006.218.08:11:28.89#ibcon#flushed, iclass 22, count 0 2006.218.08:11:28.89#ibcon#about to write, iclass 22, count 0 2006.218.08:11:28.89#ibcon#wrote, iclass 22, count 0 2006.218.08:11:28.89#ibcon#about to read 3, iclass 22, count 0 2006.218.08:11:28.91#ibcon#read 3, iclass 22, count 0 2006.218.08:11:28.91#ibcon#about to read 4, iclass 22, count 0 2006.218.08:11:28.91#ibcon#read 4, iclass 22, count 0 2006.218.08:11:28.91#ibcon#about to read 5, iclass 22, count 0 2006.218.08:11:28.91#ibcon#read 5, iclass 22, count 0 2006.218.08:11:28.91#ibcon#about to read 6, iclass 22, count 0 2006.218.08:11:28.91#ibcon#read 6, iclass 22, count 0 2006.218.08:11:28.91#ibcon#end of sib2, iclass 22, count 0 2006.218.08:11:28.91#ibcon#*mode == 0, iclass 22, count 0 2006.218.08:11:28.91#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.218.08:11:28.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.218.08:11:28.91#ibcon#*before write, iclass 22, count 0 2006.218.08:11:28.91#ibcon#enter sib2, iclass 22, count 0 2006.218.08:11:28.91#ibcon#flushed, iclass 22, count 0 2006.218.08:11:28.91#ibcon#about to write, iclass 22, count 0 2006.218.08:11:28.91#ibcon#wrote, iclass 22, count 0 2006.218.08:11:28.91#ibcon#about to read 3, iclass 22, count 0 2006.218.08:11:28.95#ibcon#read 3, iclass 22, count 0 2006.218.08:11:28.95#ibcon#about to read 4, iclass 22, count 0 2006.218.08:11:28.95#ibcon#read 4, iclass 22, count 0 2006.218.08:11:28.95#ibcon#about to read 5, iclass 22, count 0 2006.218.08:11:28.95#ibcon#read 5, iclass 22, count 0 2006.218.08:11:28.95#ibcon#about to read 6, iclass 22, count 0 2006.218.08:11:28.95#ibcon#read 6, iclass 22, count 0 2006.218.08:11:28.95#ibcon#end of sib2, iclass 22, count 0 2006.218.08:11:28.95#ibcon#*after write, iclass 22, count 0 2006.218.08:11:28.95#ibcon#*before return 0, iclass 22, count 0 2006.218.08:11:28.95#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.218.08:11:28.95#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.218.08:11:28.95#ibcon#about to clear, iclass 22 cls_cnt 0 2006.218.08:11:28.95#ibcon#cleared, iclass 22 cls_cnt 0 2006.218.08:11:28.95$vc4f8/va=4,4 2006.218.08:11:28.95#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.218.08:11:28.95#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.218.08:11:28.95#ibcon#ireg 11 cls_cnt 2 2006.218.08:11:28.95#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.218.08:11:29.01#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.218.08:11:29.01#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.218.08:11:29.01#ibcon#enter wrdev, iclass 24, count 2 2006.218.08:11:29.01#ibcon#first serial, iclass 24, count 2 2006.218.08:11:29.01#ibcon#enter sib2, iclass 24, count 2 2006.218.08:11:29.01#ibcon#flushed, iclass 24, count 2 2006.218.08:11:29.01#ibcon#about to write, iclass 24, count 2 2006.218.08:11:29.01#ibcon#wrote, iclass 24, count 2 2006.218.08:11:29.01#ibcon#about to read 3, iclass 24, count 2 2006.218.08:11:29.03#ibcon#read 3, iclass 24, count 2 2006.218.08:11:29.03#ibcon#about to read 4, iclass 24, count 2 2006.218.08:11:29.03#ibcon#read 4, iclass 24, count 2 2006.218.08:11:29.03#ibcon#about to read 5, iclass 24, count 2 2006.218.08:11:29.03#ibcon#read 5, iclass 24, count 2 2006.218.08:11:29.03#ibcon#about to read 6, iclass 24, count 2 2006.218.08:11:29.03#ibcon#read 6, iclass 24, count 2 2006.218.08:11:29.03#ibcon#end of sib2, iclass 24, count 2 2006.218.08:11:29.03#ibcon#*mode == 0, iclass 24, count 2 2006.218.08:11:29.03#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.218.08:11:29.03#ibcon#[25=AT04-04\r\n] 2006.218.08:11:29.03#ibcon#*before write, iclass 24, count 2 2006.218.08:11:29.03#ibcon#enter sib2, iclass 24, count 2 2006.218.08:11:29.03#ibcon#flushed, iclass 24, count 2 2006.218.08:11:29.03#ibcon#about to write, iclass 24, count 2 2006.218.08:11:29.03#ibcon#wrote, iclass 24, count 2 2006.218.08:11:29.03#ibcon#about to read 3, iclass 24, count 2 2006.218.08:11:29.06#ibcon#read 3, iclass 24, count 2 2006.218.08:11:29.06#ibcon#about to read 4, iclass 24, count 2 2006.218.08:11:29.06#ibcon#read 4, iclass 24, count 2 2006.218.08:11:29.06#ibcon#about to read 5, iclass 24, count 2 2006.218.08:11:29.06#ibcon#read 5, iclass 24, count 2 2006.218.08:11:29.06#ibcon#about to read 6, iclass 24, count 2 2006.218.08:11:29.06#ibcon#read 6, iclass 24, count 2 2006.218.08:11:29.06#ibcon#end of sib2, iclass 24, count 2 2006.218.08:11:29.06#ibcon#*after write, iclass 24, count 2 2006.218.08:11:29.06#ibcon#*before return 0, iclass 24, count 2 2006.218.08:11:29.06#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.218.08:11:29.06#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.218.08:11:29.06#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.218.08:11:29.06#ibcon#ireg 7 cls_cnt 0 2006.218.08:11:29.06#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.218.08:11:29.18#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.218.08:11:29.18#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.218.08:11:29.18#ibcon#enter wrdev, iclass 24, count 0 2006.218.08:11:29.18#ibcon#first serial, iclass 24, count 0 2006.218.08:11:29.18#ibcon#enter sib2, iclass 24, count 0 2006.218.08:11:29.18#ibcon#flushed, iclass 24, count 0 2006.218.08:11:29.18#ibcon#about to write, iclass 24, count 0 2006.218.08:11:29.18#ibcon#wrote, iclass 24, count 0 2006.218.08:11:29.18#ibcon#about to read 3, iclass 24, count 0 2006.218.08:11:29.20#ibcon#read 3, iclass 24, count 0 2006.218.08:11:29.20#ibcon#about to read 4, iclass 24, count 0 2006.218.08:11:29.20#ibcon#read 4, iclass 24, count 0 2006.218.08:11:29.20#ibcon#about to read 5, iclass 24, count 0 2006.218.08:11:29.20#ibcon#read 5, iclass 24, count 0 2006.218.08:11:29.20#ibcon#about to read 6, iclass 24, count 0 2006.218.08:11:29.20#ibcon#read 6, iclass 24, count 0 2006.218.08:11:29.20#ibcon#end of sib2, iclass 24, count 0 2006.218.08:11:29.20#ibcon#*mode == 0, iclass 24, count 0 2006.218.08:11:29.20#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.218.08:11:29.20#ibcon#[25=USB\r\n] 2006.218.08:11:29.20#ibcon#*before write, iclass 24, count 0 2006.218.08:11:29.20#ibcon#enter sib2, iclass 24, count 0 2006.218.08:11:29.20#ibcon#flushed, iclass 24, count 0 2006.218.08:11:29.20#ibcon#about to write, iclass 24, count 0 2006.218.08:11:29.20#ibcon#wrote, iclass 24, count 0 2006.218.08:11:29.20#ibcon#about to read 3, iclass 24, count 0 2006.218.08:11:29.23#ibcon#read 3, iclass 24, count 0 2006.218.08:11:29.23#ibcon#about to read 4, iclass 24, count 0 2006.218.08:11:29.23#ibcon#read 4, iclass 24, count 0 2006.218.08:11:29.23#ibcon#about to read 5, iclass 24, count 0 2006.218.08:11:29.23#ibcon#read 5, iclass 24, count 0 2006.218.08:11:29.23#ibcon#about to read 6, iclass 24, count 0 2006.218.08:11:29.23#ibcon#read 6, iclass 24, count 0 2006.218.08:11:29.23#ibcon#end of sib2, iclass 24, count 0 2006.218.08:11:29.23#ibcon#*after write, iclass 24, count 0 2006.218.08:11:29.23#ibcon#*before return 0, iclass 24, count 0 2006.218.08:11:29.23#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.218.08:11:29.23#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.218.08:11:29.23#ibcon#about to clear, iclass 24 cls_cnt 0 2006.218.08:11:29.23#ibcon#cleared, iclass 24 cls_cnt 0 2006.218.08:11:29.23$vc4f8/valo=5,652.99 2006.218.08:11:29.23#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.218.08:11:29.23#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.218.08:11:29.23#ibcon#ireg 17 cls_cnt 0 2006.218.08:11:29.23#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.218.08:11:29.23#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.218.08:11:29.23#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.218.08:11:29.23#ibcon#enter wrdev, iclass 26, count 0 2006.218.08:11:29.23#ibcon#first serial, iclass 26, count 0 2006.218.08:11:29.23#ibcon#enter sib2, iclass 26, count 0 2006.218.08:11:29.23#ibcon#flushed, iclass 26, count 0 2006.218.08:11:29.23#ibcon#about to write, iclass 26, count 0 2006.218.08:11:29.23#ibcon#wrote, iclass 26, count 0 2006.218.08:11:29.23#ibcon#about to read 3, iclass 26, count 0 2006.218.08:11:29.25#ibcon#read 3, iclass 26, count 0 2006.218.08:11:29.25#ibcon#about to read 4, iclass 26, count 0 2006.218.08:11:29.25#ibcon#read 4, iclass 26, count 0 2006.218.08:11:29.25#ibcon#about to read 5, iclass 26, count 0 2006.218.08:11:29.25#ibcon#read 5, iclass 26, count 0 2006.218.08:11:29.25#ibcon#about to read 6, iclass 26, count 0 2006.218.08:11:29.25#ibcon#read 6, iclass 26, count 0 2006.218.08:11:29.25#ibcon#end of sib2, iclass 26, count 0 2006.218.08:11:29.25#ibcon#*mode == 0, iclass 26, count 0 2006.218.08:11:29.25#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.218.08:11:29.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.218.08:11:29.25#ibcon#*before write, iclass 26, count 0 2006.218.08:11:29.25#ibcon#enter sib2, iclass 26, count 0 2006.218.08:11:29.25#ibcon#flushed, iclass 26, count 0 2006.218.08:11:29.25#ibcon#about to write, iclass 26, count 0 2006.218.08:11:29.25#ibcon#wrote, iclass 26, count 0 2006.218.08:11:29.25#ibcon#about to read 3, iclass 26, count 0 2006.218.08:11:29.29#ibcon#read 3, iclass 26, count 0 2006.218.08:11:29.29#ibcon#about to read 4, iclass 26, count 0 2006.218.08:11:29.29#ibcon#read 4, iclass 26, count 0 2006.218.08:11:29.29#ibcon#about to read 5, iclass 26, count 0 2006.218.08:11:29.29#ibcon#read 5, iclass 26, count 0 2006.218.08:11:29.29#ibcon#about to read 6, iclass 26, count 0 2006.218.08:11:29.29#ibcon#read 6, iclass 26, count 0 2006.218.08:11:29.29#ibcon#end of sib2, iclass 26, count 0 2006.218.08:11:29.29#ibcon#*after write, iclass 26, count 0 2006.218.08:11:29.29#ibcon#*before return 0, iclass 26, count 0 2006.218.08:11:29.29#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.218.08:11:29.29#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.218.08:11:29.29#ibcon#about to clear, iclass 26 cls_cnt 0 2006.218.08:11:29.29#ibcon#cleared, iclass 26 cls_cnt 0 2006.218.08:11:29.29$vc4f8/va=5,7 2006.218.08:11:29.29#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.218.08:11:29.29#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.218.08:11:29.29#ibcon#ireg 11 cls_cnt 2 2006.218.08:11:29.29#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.218.08:11:29.35#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.218.08:11:29.35#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.218.08:11:29.35#ibcon#enter wrdev, iclass 28, count 2 2006.218.08:11:29.35#ibcon#first serial, iclass 28, count 2 2006.218.08:11:29.35#ibcon#enter sib2, iclass 28, count 2 2006.218.08:11:29.35#ibcon#flushed, iclass 28, count 2 2006.218.08:11:29.35#ibcon#about to write, iclass 28, count 2 2006.218.08:11:29.35#ibcon#wrote, iclass 28, count 2 2006.218.08:11:29.35#ibcon#about to read 3, iclass 28, count 2 2006.218.08:11:29.37#ibcon#read 3, iclass 28, count 2 2006.218.08:11:29.37#ibcon#about to read 4, iclass 28, count 2 2006.218.08:11:29.37#ibcon#read 4, iclass 28, count 2 2006.218.08:11:29.37#ibcon#about to read 5, iclass 28, count 2 2006.218.08:11:29.37#ibcon#read 5, iclass 28, count 2 2006.218.08:11:29.37#ibcon#about to read 6, iclass 28, count 2 2006.218.08:11:29.37#ibcon#read 6, iclass 28, count 2 2006.218.08:11:29.37#ibcon#end of sib2, iclass 28, count 2 2006.218.08:11:29.37#ibcon#*mode == 0, iclass 28, count 2 2006.218.08:11:29.37#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.218.08:11:29.37#ibcon#[25=AT05-07\r\n] 2006.218.08:11:29.37#ibcon#*before write, iclass 28, count 2 2006.218.08:11:29.37#ibcon#enter sib2, iclass 28, count 2 2006.218.08:11:29.37#ibcon#flushed, iclass 28, count 2 2006.218.08:11:29.37#ibcon#about to write, iclass 28, count 2 2006.218.08:11:29.37#ibcon#wrote, iclass 28, count 2 2006.218.08:11:29.37#ibcon#about to read 3, iclass 28, count 2 2006.218.08:11:29.40#ibcon#read 3, iclass 28, count 2 2006.218.08:11:29.40#ibcon#about to read 4, iclass 28, count 2 2006.218.08:11:29.40#ibcon#read 4, iclass 28, count 2 2006.218.08:11:29.40#ibcon#about to read 5, iclass 28, count 2 2006.218.08:11:29.40#ibcon#read 5, iclass 28, count 2 2006.218.08:11:29.40#ibcon#about to read 6, iclass 28, count 2 2006.218.08:11:29.40#ibcon#read 6, iclass 28, count 2 2006.218.08:11:29.40#ibcon#end of sib2, iclass 28, count 2 2006.218.08:11:29.40#ibcon#*after write, iclass 28, count 2 2006.218.08:11:29.40#ibcon#*before return 0, iclass 28, count 2 2006.218.08:11:29.40#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.218.08:11:29.40#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.218.08:11:29.40#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.218.08:11:29.40#ibcon#ireg 7 cls_cnt 0 2006.218.08:11:29.40#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.218.08:11:29.52#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.218.08:11:29.52#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.218.08:11:29.52#ibcon#enter wrdev, iclass 28, count 0 2006.218.08:11:29.52#ibcon#first serial, iclass 28, count 0 2006.218.08:11:29.52#ibcon#enter sib2, iclass 28, count 0 2006.218.08:11:29.52#ibcon#flushed, iclass 28, count 0 2006.218.08:11:29.52#ibcon#about to write, iclass 28, count 0 2006.218.08:11:29.52#ibcon#wrote, iclass 28, count 0 2006.218.08:11:29.52#ibcon#about to read 3, iclass 28, count 0 2006.218.08:11:29.54#ibcon#read 3, iclass 28, count 0 2006.218.08:11:29.54#ibcon#about to read 4, iclass 28, count 0 2006.218.08:11:29.54#ibcon#read 4, iclass 28, count 0 2006.218.08:11:29.54#ibcon#about to read 5, iclass 28, count 0 2006.218.08:11:29.54#ibcon#read 5, iclass 28, count 0 2006.218.08:11:29.54#ibcon#about to read 6, iclass 28, count 0 2006.218.08:11:29.54#ibcon#read 6, iclass 28, count 0 2006.218.08:11:29.54#ibcon#end of sib2, iclass 28, count 0 2006.218.08:11:29.54#ibcon#*mode == 0, iclass 28, count 0 2006.218.08:11:29.54#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.218.08:11:29.54#ibcon#[25=USB\r\n] 2006.218.08:11:29.54#ibcon#*before write, iclass 28, count 0 2006.218.08:11:29.54#ibcon#enter sib2, iclass 28, count 0 2006.218.08:11:29.54#ibcon#flushed, iclass 28, count 0 2006.218.08:11:29.54#ibcon#about to write, iclass 28, count 0 2006.218.08:11:29.54#ibcon#wrote, iclass 28, count 0 2006.218.08:11:29.54#ibcon#about to read 3, iclass 28, count 0 2006.218.08:11:29.57#ibcon#read 3, iclass 28, count 0 2006.218.08:11:29.57#ibcon#about to read 4, iclass 28, count 0 2006.218.08:11:29.57#ibcon#read 4, iclass 28, count 0 2006.218.08:11:29.57#ibcon#about to read 5, iclass 28, count 0 2006.218.08:11:29.57#ibcon#read 5, iclass 28, count 0 2006.218.08:11:29.57#ibcon#about to read 6, iclass 28, count 0 2006.218.08:11:29.57#ibcon#read 6, iclass 28, count 0 2006.218.08:11:29.57#ibcon#end of sib2, iclass 28, count 0 2006.218.08:11:29.57#ibcon#*after write, iclass 28, count 0 2006.218.08:11:29.57#ibcon#*before return 0, iclass 28, count 0 2006.218.08:11:29.57#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.218.08:11:29.57#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.218.08:11:29.57#ibcon#about to clear, iclass 28 cls_cnt 0 2006.218.08:11:29.57#ibcon#cleared, iclass 28 cls_cnt 0 2006.218.08:11:29.57$vc4f8/valo=6,772.99 2006.218.08:11:29.57#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.218.08:11:29.57#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.218.08:11:29.57#ibcon#ireg 17 cls_cnt 0 2006.218.08:11:29.57#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.218.08:11:29.57#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.218.08:11:29.57#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.218.08:11:29.57#ibcon#enter wrdev, iclass 30, count 0 2006.218.08:11:29.57#ibcon#first serial, iclass 30, count 0 2006.218.08:11:29.57#ibcon#enter sib2, iclass 30, count 0 2006.218.08:11:29.57#ibcon#flushed, iclass 30, count 0 2006.218.08:11:29.57#ibcon#about to write, iclass 30, count 0 2006.218.08:11:29.57#ibcon#wrote, iclass 30, count 0 2006.218.08:11:29.57#ibcon#about to read 3, iclass 30, count 0 2006.218.08:11:29.59#ibcon#read 3, iclass 30, count 0 2006.218.08:11:29.59#ibcon#about to read 4, iclass 30, count 0 2006.218.08:11:29.59#ibcon#read 4, iclass 30, count 0 2006.218.08:11:29.59#ibcon#about to read 5, iclass 30, count 0 2006.218.08:11:29.59#ibcon#read 5, iclass 30, count 0 2006.218.08:11:29.59#ibcon#about to read 6, iclass 30, count 0 2006.218.08:11:29.59#ibcon#read 6, iclass 30, count 0 2006.218.08:11:29.59#ibcon#end of sib2, iclass 30, count 0 2006.218.08:11:29.59#ibcon#*mode == 0, iclass 30, count 0 2006.218.08:11:29.59#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.218.08:11:29.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.218.08:11:29.59#ibcon#*before write, iclass 30, count 0 2006.218.08:11:29.59#ibcon#enter sib2, iclass 30, count 0 2006.218.08:11:29.59#ibcon#flushed, iclass 30, count 0 2006.218.08:11:29.59#ibcon#about to write, iclass 30, count 0 2006.218.08:11:29.59#ibcon#wrote, iclass 30, count 0 2006.218.08:11:29.59#ibcon#about to read 3, iclass 30, count 0 2006.218.08:11:29.63#ibcon#read 3, iclass 30, count 0 2006.218.08:11:29.63#ibcon#about to read 4, iclass 30, count 0 2006.218.08:11:29.63#ibcon#read 4, iclass 30, count 0 2006.218.08:11:29.63#ibcon#about to read 5, iclass 30, count 0 2006.218.08:11:29.63#ibcon#read 5, iclass 30, count 0 2006.218.08:11:29.63#ibcon#about to read 6, iclass 30, count 0 2006.218.08:11:29.63#ibcon#read 6, iclass 30, count 0 2006.218.08:11:29.63#ibcon#end of sib2, iclass 30, count 0 2006.218.08:11:29.63#ibcon#*after write, iclass 30, count 0 2006.218.08:11:29.63#ibcon#*before return 0, iclass 30, count 0 2006.218.08:11:29.63#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.218.08:11:29.63#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.218.08:11:29.63#ibcon#about to clear, iclass 30 cls_cnt 0 2006.218.08:11:29.63#ibcon#cleared, iclass 30 cls_cnt 0 2006.218.08:11:29.63$vc4f8/va=6,6 2006.218.08:11:29.63#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.218.08:11:29.63#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.218.08:11:29.63#ibcon#ireg 11 cls_cnt 2 2006.218.08:11:29.63#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.218.08:11:29.69#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.218.08:11:29.69#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.218.08:11:29.69#ibcon#enter wrdev, iclass 32, count 2 2006.218.08:11:29.69#ibcon#first serial, iclass 32, count 2 2006.218.08:11:29.69#ibcon#enter sib2, iclass 32, count 2 2006.218.08:11:29.69#ibcon#flushed, iclass 32, count 2 2006.218.08:11:29.69#ibcon#about to write, iclass 32, count 2 2006.218.08:11:29.69#ibcon#wrote, iclass 32, count 2 2006.218.08:11:29.69#ibcon#about to read 3, iclass 32, count 2 2006.218.08:11:29.71#ibcon#read 3, iclass 32, count 2 2006.218.08:11:29.71#ibcon#about to read 4, iclass 32, count 2 2006.218.08:11:29.71#ibcon#read 4, iclass 32, count 2 2006.218.08:11:29.71#ibcon#about to read 5, iclass 32, count 2 2006.218.08:11:29.71#ibcon#read 5, iclass 32, count 2 2006.218.08:11:29.71#ibcon#about to read 6, iclass 32, count 2 2006.218.08:11:29.71#ibcon#read 6, iclass 32, count 2 2006.218.08:11:29.71#ibcon#end of sib2, iclass 32, count 2 2006.218.08:11:29.71#ibcon#*mode == 0, iclass 32, count 2 2006.218.08:11:29.71#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.218.08:11:29.71#ibcon#[25=AT06-06\r\n] 2006.218.08:11:29.71#ibcon#*before write, iclass 32, count 2 2006.218.08:11:29.71#ibcon#enter sib2, iclass 32, count 2 2006.218.08:11:29.71#ibcon#flushed, iclass 32, count 2 2006.218.08:11:29.71#ibcon#about to write, iclass 32, count 2 2006.218.08:11:29.71#ibcon#wrote, iclass 32, count 2 2006.218.08:11:29.71#ibcon#about to read 3, iclass 32, count 2 2006.218.08:11:29.74#ibcon#read 3, iclass 32, count 2 2006.218.08:11:29.74#ibcon#about to read 4, iclass 32, count 2 2006.218.08:11:29.74#ibcon#read 4, iclass 32, count 2 2006.218.08:11:29.74#ibcon#about to read 5, iclass 32, count 2 2006.218.08:11:29.74#ibcon#read 5, iclass 32, count 2 2006.218.08:11:29.74#ibcon#about to read 6, iclass 32, count 2 2006.218.08:11:29.74#ibcon#read 6, iclass 32, count 2 2006.218.08:11:29.74#ibcon#end of sib2, iclass 32, count 2 2006.218.08:11:29.74#ibcon#*after write, iclass 32, count 2 2006.218.08:11:29.74#ibcon#*before return 0, iclass 32, count 2 2006.218.08:11:29.74#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.218.08:11:29.74#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.218.08:11:29.74#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.218.08:11:29.74#ibcon#ireg 7 cls_cnt 0 2006.218.08:11:29.74#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.218.08:11:29.86#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.218.08:11:29.86#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.218.08:11:29.86#ibcon#enter wrdev, iclass 32, count 0 2006.218.08:11:29.86#ibcon#first serial, iclass 32, count 0 2006.218.08:11:29.86#ibcon#enter sib2, iclass 32, count 0 2006.218.08:11:29.86#ibcon#flushed, iclass 32, count 0 2006.218.08:11:29.86#ibcon#about to write, iclass 32, count 0 2006.218.08:11:29.86#ibcon#wrote, iclass 32, count 0 2006.218.08:11:29.86#ibcon#about to read 3, iclass 32, count 0 2006.218.08:11:29.88#ibcon#read 3, iclass 32, count 0 2006.218.08:11:29.88#ibcon#about to read 4, iclass 32, count 0 2006.218.08:11:29.88#ibcon#read 4, iclass 32, count 0 2006.218.08:11:29.88#ibcon#about to read 5, iclass 32, count 0 2006.218.08:11:29.88#ibcon#read 5, iclass 32, count 0 2006.218.08:11:29.88#ibcon#about to read 6, iclass 32, count 0 2006.218.08:11:29.88#ibcon#read 6, iclass 32, count 0 2006.218.08:11:29.88#ibcon#end of sib2, iclass 32, count 0 2006.218.08:11:29.88#ibcon#*mode == 0, iclass 32, count 0 2006.218.08:11:29.88#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.218.08:11:29.88#ibcon#[25=USB\r\n] 2006.218.08:11:29.88#ibcon#*before write, iclass 32, count 0 2006.218.08:11:29.88#ibcon#enter sib2, iclass 32, count 0 2006.218.08:11:29.88#ibcon#flushed, iclass 32, count 0 2006.218.08:11:29.88#ibcon#about to write, iclass 32, count 0 2006.218.08:11:29.88#ibcon#wrote, iclass 32, count 0 2006.218.08:11:29.88#ibcon#about to read 3, iclass 32, count 0 2006.218.08:11:29.91#ibcon#read 3, iclass 32, count 0 2006.218.08:11:29.91#ibcon#about to read 4, iclass 32, count 0 2006.218.08:11:29.91#ibcon#read 4, iclass 32, count 0 2006.218.08:11:29.91#ibcon#about to read 5, iclass 32, count 0 2006.218.08:11:29.91#ibcon#read 5, iclass 32, count 0 2006.218.08:11:29.91#ibcon#about to read 6, iclass 32, count 0 2006.218.08:11:29.91#ibcon#read 6, iclass 32, count 0 2006.218.08:11:29.91#ibcon#end of sib2, iclass 32, count 0 2006.218.08:11:29.91#ibcon#*after write, iclass 32, count 0 2006.218.08:11:29.91#ibcon#*before return 0, iclass 32, count 0 2006.218.08:11:29.91#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.218.08:11:29.91#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.218.08:11:29.91#ibcon#about to clear, iclass 32 cls_cnt 0 2006.218.08:11:29.91#ibcon#cleared, iclass 32 cls_cnt 0 2006.218.08:11:29.91$vc4f8/valo=7,832.99 2006.218.08:11:29.91#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.218.08:11:29.91#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.218.08:11:29.91#ibcon#ireg 17 cls_cnt 0 2006.218.08:11:29.91#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.218.08:11:29.91#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.218.08:11:29.91#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.218.08:11:29.91#ibcon#enter wrdev, iclass 34, count 0 2006.218.08:11:29.91#ibcon#first serial, iclass 34, count 0 2006.218.08:11:29.91#ibcon#enter sib2, iclass 34, count 0 2006.218.08:11:29.91#ibcon#flushed, iclass 34, count 0 2006.218.08:11:29.91#ibcon#about to write, iclass 34, count 0 2006.218.08:11:29.91#ibcon#wrote, iclass 34, count 0 2006.218.08:11:29.91#ibcon#about to read 3, iclass 34, count 0 2006.218.08:11:29.93#ibcon#read 3, iclass 34, count 0 2006.218.08:11:29.93#ibcon#about to read 4, iclass 34, count 0 2006.218.08:11:29.93#ibcon#read 4, iclass 34, count 0 2006.218.08:11:29.93#ibcon#about to read 5, iclass 34, count 0 2006.218.08:11:29.93#ibcon#read 5, iclass 34, count 0 2006.218.08:11:29.93#ibcon#about to read 6, iclass 34, count 0 2006.218.08:11:29.93#ibcon#read 6, iclass 34, count 0 2006.218.08:11:29.93#ibcon#end of sib2, iclass 34, count 0 2006.218.08:11:29.93#ibcon#*mode == 0, iclass 34, count 0 2006.218.08:11:29.93#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.218.08:11:29.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.218.08:11:29.93#ibcon#*before write, iclass 34, count 0 2006.218.08:11:29.93#ibcon#enter sib2, iclass 34, count 0 2006.218.08:11:29.93#ibcon#flushed, iclass 34, count 0 2006.218.08:11:29.93#ibcon#about to write, iclass 34, count 0 2006.218.08:11:29.93#ibcon#wrote, iclass 34, count 0 2006.218.08:11:29.93#ibcon#about to read 3, iclass 34, count 0 2006.218.08:11:29.97#ibcon#read 3, iclass 34, count 0 2006.218.08:11:29.97#ibcon#about to read 4, iclass 34, count 0 2006.218.08:11:29.97#ibcon#read 4, iclass 34, count 0 2006.218.08:11:29.97#ibcon#about to read 5, iclass 34, count 0 2006.218.08:11:29.97#ibcon#read 5, iclass 34, count 0 2006.218.08:11:29.97#ibcon#about to read 6, iclass 34, count 0 2006.218.08:11:29.97#ibcon#read 6, iclass 34, count 0 2006.218.08:11:29.97#ibcon#end of sib2, iclass 34, count 0 2006.218.08:11:29.97#ibcon#*after write, iclass 34, count 0 2006.218.08:11:29.97#ibcon#*before return 0, iclass 34, count 0 2006.218.08:11:29.97#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.218.08:11:29.97#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.218.08:11:29.97#ibcon#about to clear, iclass 34 cls_cnt 0 2006.218.08:11:29.97#ibcon#cleared, iclass 34 cls_cnt 0 2006.218.08:11:29.97$vc4f8/va=7,6 2006.218.08:11:29.97#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.218.08:11:29.97#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.218.08:11:29.97#ibcon#ireg 11 cls_cnt 2 2006.218.08:11:29.97#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.218.08:11:30.03#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.218.08:11:30.03#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.218.08:11:30.03#ibcon#enter wrdev, iclass 36, count 2 2006.218.08:11:30.03#ibcon#first serial, iclass 36, count 2 2006.218.08:11:30.03#ibcon#enter sib2, iclass 36, count 2 2006.218.08:11:30.03#ibcon#flushed, iclass 36, count 2 2006.218.08:11:30.03#ibcon#about to write, iclass 36, count 2 2006.218.08:11:30.03#ibcon#wrote, iclass 36, count 2 2006.218.08:11:30.03#ibcon#about to read 3, iclass 36, count 2 2006.218.08:11:30.05#ibcon#read 3, iclass 36, count 2 2006.218.08:11:30.05#ibcon#about to read 4, iclass 36, count 2 2006.218.08:11:30.05#ibcon#read 4, iclass 36, count 2 2006.218.08:11:30.05#ibcon#about to read 5, iclass 36, count 2 2006.218.08:11:30.05#ibcon#read 5, iclass 36, count 2 2006.218.08:11:30.05#ibcon#about to read 6, iclass 36, count 2 2006.218.08:11:30.05#ibcon#read 6, iclass 36, count 2 2006.218.08:11:30.05#ibcon#end of sib2, iclass 36, count 2 2006.218.08:11:30.05#ibcon#*mode == 0, iclass 36, count 2 2006.218.08:11:30.05#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.218.08:11:30.05#ibcon#[25=AT07-06\r\n] 2006.218.08:11:30.05#ibcon#*before write, iclass 36, count 2 2006.218.08:11:30.05#ibcon#enter sib2, iclass 36, count 2 2006.218.08:11:30.05#ibcon#flushed, iclass 36, count 2 2006.218.08:11:30.05#ibcon#about to write, iclass 36, count 2 2006.218.08:11:30.05#ibcon#wrote, iclass 36, count 2 2006.218.08:11:30.05#ibcon#about to read 3, iclass 36, count 2 2006.218.08:11:30.08#ibcon#read 3, iclass 36, count 2 2006.218.08:11:30.08#ibcon#about to read 4, iclass 36, count 2 2006.218.08:11:30.08#ibcon#read 4, iclass 36, count 2 2006.218.08:11:30.08#ibcon#about to read 5, iclass 36, count 2 2006.218.08:11:30.08#ibcon#read 5, iclass 36, count 2 2006.218.08:11:30.08#ibcon#about to read 6, iclass 36, count 2 2006.218.08:11:30.08#ibcon#read 6, iclass 36, count 2 2006.218.08:11:30.08#ibcon#end of sib2, iclass 36, count 2 2006.218.08:11:30.08#ibcon#*after write, iclass 36, count 2 2006.218.08:11:30.08#ibcon#*before return 0, iclass 36, count 2 2006.218.08:11:30.08#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.218.08:11:30.08#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.218.08:11:30.08#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.218.08:11:30.08#ibcon#ireg 7 cls_cnt 0 2006.218.08:11:30.08#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.218.08:11:30.20#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.218.08:11:30.20#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.218.08:11:30.20#ibcon#enter wrdev, iclass 36, count 0 2006.218.08:11:30.20#ibcon#first serial, iclass 36, count 0 2006.218.08:11:30.20#ibcon#enter sib2, iclass 36, count 0 2006.218.08:11:30.20#ibcon#flushed, iclass 36, count 0 2006.218.08:11:30.20#ibcon#about to write, iclass 36, count 0 2006.218.08:11:30.20#ibcon#wrote, iclass 36, count 0 2006.218.08:11:30.20#ibcon#about to read 3, iclass 36, count 0 2006.218.08:11:30.22#ibcon#read 3, iclass 36, count 0 2006.218.08:11:30.22#ibcon#about to read 4, iclass 36, count 0 2006.218.08:11:30.22#ibcon#read 4, iclass 36, count 0 2006.218.08:11:30.22#ibcon#about to read 5, iclass 36, count 0 2006.218.08:11:30.22#ibcon#read 5, iclass 36, count 0 2006.218.08:11:30.22#ibcon#about to read 6, iclass 36, count 0 2006.218.08:11:30.22#ibcon#read 6, iclass 36, count 0 2006.218.08:11:30.22#ibcon#end of sib2, iclass 36, count 0 2006.218.08:11:30.22#ibcon#*mode == 0, iclass 36, count 0 2006.218.08:11:30.22#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.218.08:11:30.22#ibcon#[25=USB\r\n] 2006.218.08:11:30.22#ibcon#*before write, iclass 36, count 0 2006.218.08:11:30.22#ibcon#enter sib2, iclass 36, count 0 2006.218.08:11:30.22#ibcon#flushed, iclass 36, count 0 2006.218.08:11:30.22#ibcon#about to write, iclass 36, count 0 2006.218.08:11:30.22#ibcon#wrote, iclass 36, count 0 2006.218.08:11:30.22#ibcon#about to read 3, iclass 36, count 0 2006.218.08:11:30.25#ibcon#read 3, iclass 36, count 0 2006.218.08:11:30.25#ibcon#about to read 4, iclass 36, count 0 2006.218.08:11:30.25#ibcon#read 4, iclass 36, count 0 2006.218.08:11:30.25#ibcon#about to read 5, iclass 36, count 0 2006.218.08:11:30.25#ibcon#read 5, iclass 36, count 0 2006.218.08:11:30.25#ibcon#about to read 6, iclass 36, count 0 2006.218.08:11:30.25#ibcon#read 6, iclass 36, count 0 2006.218.08:11:30.25#ibcon#end of sib2, iclass 36, count 0 2006.218.08:11:30.25#ibcon#*after write, iclass 36, count 0 2006.218.08:11:30.25#ibcon#*before return 0, iclass 36, count 0 2006.218.08:11:30.25#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.218.08:11:30.25#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.218.08:11:30.25#ibcon#about to clear, iclass 36 cls_cnt 0 2006.218.08:11:30.25#ibcon#cleared, iclass 36 cls_cnt 0 2006.218.08:11:30.25$vc4f8/valo=8,852.99 2006.218.08:11:30.25#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.218.08:11:30.25#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.218.08:11:30.25#ibcon#ireg 17 cls_cnt 0 2006.218.08:11:30.25#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.218.08:11:30.25#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.218.08:11:30.25#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.218.08:11:30.25#ibcon#enter wrdev, iclass 38, count 0 2006.218.08:11:30.25#ibcon#first serial, iclass 38, count 0 2006.218.08:11:30.25#ibcon#enter sib2, iclass 38, count 0 2006.218.08:11:30.25#ibcon#flushed, iclass 38, count 0 2006.218.08:11:30.25#ibcon#about to write, iclass 38, count 0 2006.218.08:11:30.25#ibcon#wrote, iclass 38, count 0 2006.218.08:11:30.25#ibcon#about to read 3, iclass 38, count 0 2006.218.08:11:30.27#ibcon#read 3, iclass 38, count 0 2006.218.08:11:30.27#ibcon#about to read 4, iclass 38, count 0 2006.218.08:11:30.27#ibcon#read 4, iclass 38, count 0 2006.218.08:11:30.27#ibcon#about to read 5, iclass 38, count 0 2006.218.08:11:30.27#ibcon#read 5, iclass 38, count 0 2006.218.08:11:30.27#ibcon#about to read 6, iclass 38, count 0 2006.218.08:11:30.27#ibcon#read 6, iclass 38, count 0 2006.218.08:11:30.27#ibcon#end of sib2, iclass 38, count 0 2006.218.08:11:30.27#ibcon#*mode == 0, iclass 38, count 0 2006.218.08:11:30.27#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.218.08:11:30.27#ibcon#[26=FRQ=08,852.99\r\n] 2006.218.08:11:30.27#ibcon#*before write, iclass 38, count 0 2006.218.08:11:30.27#ibcon#enter sib2, iclass 38, count 0 2006.218.08:11:30.27#ibcon#flushed, iclass 38, count 0 2006.218.08:11:30.27#ibcon#about to write, iclass 38, count 0 2006.218.08:11:30.27#ibcon#wrote, iclass 38, count 0 2006.218.08:11:30.27#ibcon#about to read 3, iclass 38, count 0 2006.218.08:11:30.31#ibcon#read 3, iclass 38, count 0 2006.218.08:11:30.31#ibcon#about to read 4, iclass 38, count 0 2006.218.08:11:30.31#ibcon#read 4, iclass 38, count 0 2006.218.08:11:30.31#ibcon#about to read 5, iclass 38, count 0 2006.218.08:11:30.31#ibcon#read 5, iclass 38, count 0 2006.218.08:11:30.31#ibcon#about to read 6, iclass 38, count 0 2006.218.08:11:30.31#ibcon#read 6, iclass 38, count 0 2006.218.08:11:30.31#ibcon#end of sib2, iclass 38, count 0 2006.218.08:11:30.31#ibcon#*after write, iclass 38, count 0 2006.218.08:11:30.31#ibcon#*before return 0, iclass 38, count 0 2006.218.08:11:30.31#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.218.08:11:30.31#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.218.08:11:30.31#ibcon#about to clear, iclass 38 cls_cnt 0 2006.218.08:11:30.31#ibcon#cleared, iclass 38 cls_cnt 0 2006.218.08:11:30.31$vc4f8/va=8,7 2006.218.08:11:30.31#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.218.08:11:30.31#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.218.08:11:30.31#ibcon#ireg 11 cls_cnt 2 2006.218.08:11:30.31#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.218.08:11:30.37#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.218.08:11:30.37#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.218.08:11:30.37#ibcon#enter wrdev, iclass 40, count 2 2006.218.08:11:30.37#ibcon#first serial, iclass 40, count 2 2006.218.08:11:30.37#ibcon#enter sib2, iclass 40, count 2 2006.218.08:11:30.37#ibcon#flushed, iclass 40, count 2 2006.218.08:11:30.37#ibcon#about to write, iclass 40, count 2 2006.218.08:11:30.37#ibcon#wrote, iclass 40, count 2 2006.218.08:11:30.37#ibcon#about to read 3, iclass 40, count 2 2006.218.08:11:30.39#ibcon#read 3, iclass 40, count 2 2006.218.08:11:30.39#ibcon#about to read 4, iclass 40, count 2 2006.218.08:11:30.39#ibcon#read 4, iclass 40, count 2 2006.218.08:11:30.39#ibcon#about to read 5, iclass 40, count 2 2006.218.08:11:30.39#ibcon#read 5, iclass 40, count 2 2006.218.08:11:30.39#ibcon#about to read 6, iclass 40, count 2 2006.218.08:11:30.39#ibcon#read 6, iclass 40, count 2 2006.218.08:11:30.39#ibcon#end of sib2, iclass 40, count 2 2006.218.08:11:30.39#ibcon#*mode == 0, iclass 40, count 2 2006.218.08:11:30.39#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.218.08:11:30.39#ibcon#[25=AT08-07\r\n] 2006.218.08:11:30.39#ibcon#*before write, iclass 40, count 2 2006.218.08:11:30.39#ibcon#enter sib2, iclass 40, count 2 2006.218.08:11:30.39#ibcon#flushed, iclass 40, count 2 2006.218.08:11:30.39#ibcon#about to write, iclass 40, count 2 2006.218.08:11:30.39#ibcon#wrote, iclass 40, count 2 2006.218.08:11:30.39#ibcon#about to read 3, iclass 40, count 2 2006.218.08:11:30.42#ibcon#read 3, iclass 40, count 2 2006.218.08:11:30.42#ibcon#about to read 4, iclass 40, count 2 2006.218.08:11:30.42#ibcon#read 4, iclass 40, count 2 2006.218.08:11:30.42#ibcon#about to read 5, iclass 40, count 2 2006.218.08:11:30.42#ibcon#read 5, iclass 40, count 2 2006.218.08:11:30.42#ibcon#about to read 6, iclass 40, count 2 2006.218.08:11:30.42#ibcon#read 6, iclass 40, count 2 2006.218.08:11:30.42#ibcon#end of sib2, iclass 40, count 2 2006.218.08:11:30.42#ibcon#*after write, iclass 40, count 2 2006.218.08:11:30.42#ibcon#*before return 0, iclass 40, count 2 2006.218.08:11:30.42#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.218.08:11:30.42#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.218.08:11:30.42#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.218.08:11:30.42#ibcon#ireg 7 cls_cnt 0 2006.218.08:11:30.42#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.218.08:11:30.54#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.218.08:11:30.54#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.218.08:11:30.54#ibcon#enter wrdev, iclass 40, count 0 2006.218.08:11:30.54#ibcon#first serial, iclass 40, count 0 2006.218.08:11:30.54#ibcon#enter sib2, iclass 40, count 0 2006.218.08:11:30.54#ibcon#flushed, iclass 40, count 0 2006.218.08:11:30.54#ibcon#about to write, iclass 40, count 0 2006.218.08:11:30.54#ibcon#wrote, iclass 40, count 0 2006.218.08:11:30.54#ibcon#about to read 3, iclass 40, count 0 2006.218.08:11:30.56#ibcon#read 3, iclass 40, count 0 2006.218.08:11:30.56#ibcon#about to read 4, iclass 40, count 0 2006.218.08:11:30.56#ibcon#read 4, iclass 40, count 0 2006.218.08:11:30.56#ibcon#about to read 5, iclass 40, count 0 2006.218.08:11:30.56#ibcon#read 5, iclass 40, count 0 2006.218.08:11:30.56#ibcon#about to read 6, iclass 40, count 0 2006.218.08:11:30.56#ibcon#read 6, iclass 40, count 0 2006.218.08:11:30.56#ibcon#end of sib2, iclass 40, count 0 2006.218.08:11:30.56#ibcon#*mode == 0, iclass 40, count 0 2006.218.08:11:30.56#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.218.08:11:30.56#ibcon#[25=USB\r\n] 2006.218.08:11:30.56#ibcon#*before write, iclass 40, count 0 2006.218.08:11:30.56#ibcon#enter sib2, iclass 40, count 0 2006.218.08:11:30.56#ibcon#flushed, iclass 40, count 0 2006.218.08:11:30.56#ibcon#about to write, iclass 40, count 0 2006.218.08:11:30.56#ibcon#wrote, iclass 40, count 0 2006.218.08:11:30.56#ibcon#about to read 3, iclass 40, count 0 2006.218.08:11:30.59#ibcon#read 3, iclass 40, count 0 2006.218.08:11:30.59#ibcon#about to read 4, iclass 40, count 0 2006.218.08:11:30.59#ibcon#read 4, iclass 40, count 0 2006.218.08:11:30.59#ibcon#about to read 5, iclass 40, count 0 2006.218.08:11:30.59#ibcon#read 5, iclass 40, count 0 2006.218.08:11:30.59#ibcon#about to read 6, iclass 40, count 0 2006.218.08:11:30.59#ibcon#read 6, iclass 40, count 0 2006.218.08:11:30.59#ibcon#end of sib2, iclass 40, count 0 2006.218.08:11:30.59#ibcon#*after write, iclass 40, count 0 2006.218.08:11:30.59#ibcon#*before return 0, iclass 40, count 0 2006.218.08:11:30.59#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.218.08:11:30.59#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.218.08:11:30.59#ibcon#about to clear, iclass 40 cls_cnt 0 2006.218.08:11:30.59#ibcon#cleared, iclass 40 cls_cnt 0 2006.218.08:11:30.59$vc4f8/vblo=1,632.99 2006.218.08:11:30.59#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.218.08:11:30.59#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.218.08:11:30.59#ibcon#ireg 17 cls_cnt 0 2006.218.08:11:30.59#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.218.08:11:30.59#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.218.08:11:30.59#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.218.08:11:30.59#ibcon#enter wrdev, iclass 4, count 0 2006.218.08:11:30.59#ibcon#first serial, iclass 4, count 0 2006.218.08:11:30.59#ibcon#enter sib2, iclass 4, count 0 2006.218.08:11:30.59#ibcon#flushed, iclass 4, count 0 2006.218.08:11:30.59#ibcon#about to write, iclass 4, count 0 2006.218.08:11:30.59#ibcon#wrote, iclass 4, count 0 2006.218.08:11:30.59#ibcon#about to read 3, iclass 4, count 0 2006.218.08:11:30.61#ibcon#read 3, iclass 4, count 0 2006.218.08:11:30.61#ibcon#about to read 4, iclass 4, count 0 2006.218.08:11:30.61#ibcon#read 4, iclass 4, count 0 2006.218.08:11:30.61#ibcon#about to read 5, iclass 4, count 0 2006.218.08:11:30.61#ibcon#read 5, iclass 4, count 0 2006.218.08:11:30.61#ibcon#about to read 6, iclass 4, count 0 2006.218.08:11:30.61#ibcon#read 6, iclass 4, count 0 2006.218.08:11:30.61#ibcon#end of sib2, iclass 4, count 0 2006.218.08:11:30.61#ibcon#*mode == 0, iclass 4, count 0 2006.218.08:11:30.61#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.218.08:11:30.61#ibcon#[28=FRQ=01,632.99\r\n] 2006.218.08:11:30.61#ibcon#*before write, iclass 4, count 0 2006.218.08:11:30.61#ibcon#enter sib2, iclass 4, count 0 2006.218.08:11:30.61#ibcon#flushed, iclass 4, count 0 2006.218.08:11:30.61#ibcon#about to write, iclass 4, count 0 2006.218.08:11:30.61#ibcon#wrote, iclass 4, count 0 2006.218.08:11:30.61#ibcon#about to read 3, iclass 4, count 0 2006.218.08:11:30.65#ibcon#read 3, iclass 4, count 0 2006.218.08:11:30.65#ibcon#about to read 4, iclass 4, count 0 2006.218.08:11:30.65#ibcon#read 4, iclass 4, count 0 2006.218.08:11:30.65#ibcon#about to read 5, iclass 4, count 0 2006.218.08:11:30.65#ibcon#read 5, iclass 4, count 0 2006.218.08:11:30.65#ibcon#about to read 6, iclass 4, count 0 2006.218.08:11:30.65#ibcon#read 6, iclass 4, count 0 2006.218.08:11:30.65#ibcon#end of sib2, iclass 4, count 0 2006.218.08:11:30.65#ibcon#*after write, iclass 4, count 0 2006.218.08:11:30.65#ibcon#*before return 0, iclass 4, count 0 2006.218.08:11:30.65#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.218.08:11:30.65#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.218.08:11:30.65#ibcon#about to clear, iclass 4 cls_cnt 0 2006.218.08:11:30.65#ibcon#cleared, iclass 4 cls_cnt 0 2006.218.08:11:30.65$vc4f8/vb=1,4 2006.218.08:11:30.65#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.218.08:11:30.65#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.218.08:11:30.65#ibcon#ireg 11 cls_cnt 2 2006.218.08:11:30.65#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.218.08:11:30.65#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.218.08:11:30.65#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.218.08:11:30.65#ibcon#enter wrdev, iclass 6, count 2 2006.218.08:11:30.65#ibcon#first serial, iclass 6, count 2 2006.218.08:11:30.65#ibcon#enter sib2, iclass 6, count 2 2006.218.08:11:30.65#ibcon#flushed, iclass 6, count 2 2006.218.08:11:30.65#ibcon#about to write, iclass 6, count 2 2006.218.08:11:30.65#ibcon#wrote, iclass 6, count 2 2006.218.08:11:30.65#ibcon#about to read 3, iclass 6, count 2 2006.218.08:11:30.67#ibcon#read 3, iclass 6, count 2 2006.218.08:11:30.67#ibcon#about to read 4, iclass 6, count 2 2006.218.08:11:30.67#ibcon#read 4, iclass 6, count 2 2006.218.08:11:30.67#ibcon#about to read 5, iclass 6, count 2 2006.218.08:11:30.67#ibcon#read 5, iclass 6, count 2 2006.218.08:11:30.67#ibcon#about to read 6, iclass 6, count 2 2006.218.08:11:30.67#ibcon#read 6, iclass 6, count 2 2006.218.08:11:30.67#ibcon#end of sib2, iclass 6, count 2 2006.218.08:11:30.67#ibcon#*mode == 0, iclass 6, count 2 2006.218.08:11:30.67#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.218.08:11:30.67#ibcon#[27=AT01-04\r\n] 2006.218.08:11:30.67#ibcon#*before write, iclass 6, count 2 2006.218.08:11:30.67#ibcon#enter sib2, iclass 6, count 2 2006.218.08:11:30.67#ibcon#flushed, iclass 6, count 2 2006.218.08:11:30.67#ibcon#about to write, iclass 6, count 2 2006.218.08:11:30.67#ibcon#wrote, iclass 6, count 2 2006.218.08:11:30.67#ibcon#about to read 3, iclass 6, count 2 2006.218.08:11:30.70#ibcon#read 3, iclass 6, count 2 2006.218.08:11:30.70#ibcon#about to read 4, iclass 6, count 2 2006.218.08:11:30.70#ibcon#read 4, iclass 6, count 2 2006.218.08:11:30.70#ibcon#about to read 5, iclass 6, count 2 2006.218.08:11:30.70#ibcon#read 5, iclass 6, count 2 2006.218.08:11:30.70#ibcon#about to read 6, iclass 6, count 2 2006.218.08:11:30.70#ibcon#read 6, iclass 6, count 2 2006.218.08:11:30.70#ibcon#end of sib2, iclass 6, count 2 2006.218.08:11:30.70#ibcon#*after write, iclass 6, count 2 2006.218.08:11:30.70#ibcon#*before return 0, iclass 6, count 2 2006.218.08:11:30.70#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.218.08:11:30.70#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.218.08:11:30.70#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.218.08:11:30.70#ibcon#ireg 7 cls_cnt 0 2006.218.08:11:30.70#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.218.08:11:30.82#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.218.08:11:30.82#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.218.08:11:30.82#ibcon#enter wrdev, iclass 6, count 0 2006.218.08:11:30.82#ibcon#first serial, iclass 6, count 0 2006.218.08:11:30.82#ibcon#enter sib2, iclass 6, count 0 2006.218.08:11:30.82#ibcon#flushed, iclass 6, count 0 2006.218.08:11:30.82#ibcon#about to write, iclass 6, count 0 2006.218.08:11:30.82#ibcon#wrote, iclass 6, count 0 2006.218.08:11:30.82#ibcon#about to read 3, iclass 6, count 0 2006.218.08:11:30.84#ibcon#read 3, iclass 6, count 0 2006.218.08:11:30.84#ibcon#about to read 4, iclass 6, count 0 2006.218.08:11:30.84#ibcon#read 4, iclass 6, count 0 2006.218.08:11:30.84#ibcon#about to read 5, iclass 6, count 0 2006.218.08:11:30.84#ibcon#read 5, iclass 6, count 0 2006.218.08:11:30.84#ibcon#about to read 6, iclass 6, count 0 2006.218.08:11:30.84#ibcon#read 6, iclass 6, count 0 2006.218.08:11:30.84#ibcon#end of sib2, iclass 6, count 0 2006.218.08:11:30.84#ibcon#*mode == 0, iclass 6, count 0 2006.218.08:11:30.84#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.218.08:11:30.84#ibcon#[27=USB\r\n] 2006.218.08:11:30.84#ibcon#*before write, iclass 6, count 0 2006.218.08:11:30.84#ibcon#enter sib2, iclass 6, count 0 2006.218.08:11:30.84#ibcon#flushed, iclass 6, count 0 2006.218.08:11:30.84#ibcon#about to write, iclass 6, count 0 2006.218.08:11:30.84#ibcon#wrote, iclass 6, count 0 2006.218.08:11:30.84#ibcon#about to read 3, iclass 6, count 0 2006.218.08:11:30.87#ibcon#read 3, iclass 6, count 0 2006.218.08:11:30.87#ibcon#about to read 4, iclass 6, count 0 2006.218.08:11:30.87#ibcon#read 4, iclass 6, count 0 2006.218.08:11:30.87#ibcon#about to read 5, iclass 6, count 0 2006.218.08:11:30.87#ibcon#read 5, iclass 6, count 0 2006.218.08:11:30.87#ibcon#about to read 6, iclass 6, count 0 2006.218.08:11:30.87#ibcon#read 6, iclass 6, count 0 2006.218.08:11:30.87#ibcon#end of sib2, iclass 6, count 0 2006.218.08:11:30.87#ibcon#*after write, iclass 6, count 0 2006.218.08:11:30.87#ibcon#*before return 0, iclass 6, count 0 2006.218.08:11:30.87#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.218.08:11:30.87#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.218.08:11:30.87#ibcon#about to clear, iclass 6 cls_cnt 0 2006.218.08:11:30.87#ibcon#cleared, iclass 6 cls_cnt 0 2006.218.08:11:30.87$vc4f8/vblo=2,640.99 2006.218.08:11:30.87#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.218.08:11:30.87#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.218.08:11:30.87#ibcon#ireg 17 cls_cnt 0 2006.218.08:11:30.87#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.218.08:11:30.87#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.218.08:11:30.87#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.218.08:11:30.87#ibcon#enter wrdev, iclass 10, count 0 2006.218.08:11:30.87#ibcon#first serial, iclass 10, count 0 2006.218.08:11:30.87#ibcon#enter sib2, iclass 10, count 0 2006.218.08:11:30.87#ibcon#flushed, iclass 10, count 0 2006.218.08:11:30.87#ibcon#about to write, iclass 10, count 0 2006.218.08:11:30.87#ibcon#wrote, iclass 10, count 0 2006.218.08:11:30.87#ibcon#about to read 3, iclass 10, count 0 2006.218.08:11:30.89#ibcon#read 3, iclass 10, count 0 2006.218.08:11:30.89#ibcon#about to read 4, iclass 10, count 0 2006.218.08:11:30.89#ibcon#read 4, iclass 10, count 0 2006.218.08:11:30.89#ibcon#about to read 5, iclass 10, count 0 2006.218.08:11:30.89#ibcon#read 5, iclass 10, count 0 2006.218.08:11:30.89#ibcon#about to read 6, iclass 10, count 0 2006.218.08:11:30.89#ibcon#read 6, iclass 10, count 0 2006.218.08:11:30.89#ibcon#end of sib2, iclass 10, count 0 2006.218.08:11:30.89#ibcon#*mode == 0, iclass 10, count 0 2006.218.08:11:30.89#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.218.08:11:30.89#ibcon#[28=FRQ=02,640.99\r\n] 2006.218.08:11:30.89#ibcon#*before write, iclass 10, count 0 2006.218.08:11:30.89#ibcon#enter sib2, iclass 10, count 0 2006.218.08:11:30.89#ibcon#flushed, iclass 10, count 0 2006.218.08:11:30.89#ibcon#about to write, iclass 10, count 0 2006.218.08:11:30.89#ibcon#wrote, iclass 10, count 0 2006.218.08:11:30.89#ibcon#about to read 3, iclass 10, count 0 2006.218.08:11:30.93#ibcon#read 3, iclass 10, count 0 2006.218.08:11:30.93#ibcon#about to read 4, iclass 10, count 0 2006.218.08:11:30.93#ibcon#read 4, iclass 10, count 0 2006.218.08:11:30.93#ibcon#about to read 5, iclass 10, count 0 2006.218.08:11:30.93#ibcon#read 5, iclass 10, count 0 2006.218.08:11:30.93#ibcon#about to read 6, iclass 10, count 0 2006.218.08:11:30.93#ibcon#read 6, iclass 10, count 0 2006.218.08:11:30.93#ibcon#end of sib2, iclass 10, count 0 2006.218.08:11:30.93#ibcon#*after write, iclass 10, count 0 2006.218.08:11:30.93#ibcon#*before return 0, iclass 10, count 0 2006.218.08:11:30.93#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.218.08:11:30.93#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.218.08:11:30.93#ibcon#about to clear, iclass 10 cls_cnt 0 2006.218.08:11:30.93#ibcon#cleared, iclass 10 cls_cnt 0 2006.218.08:11:30.93$vc4f8/vb=2,4 2006.218.08:11:30.93#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.218.08:11:30.93#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.218.08:11:30.93#ibcon#ireg 11 cls_cnt 2 2006.218.08:11:30.93#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.218.08:11:30.99#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.218.08:11:30.99#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.218.08:11:30.99#ibcon#enter wrdev, iclass 12, count 2 2006.218.08:11:30.99#ibcon#first serial, iclass 12, count 2 2006.218.08:11:30.99#ibcon#enter sib2, iclass 12, count 2 2006.218.08:11:30.99#ibcon#flushed, iclass 12, count 2 2006.218.08:11:30.99#ibcon#about to write, iclass 12, count 2 2006.218.08:11:30.99#ibcon#wrote, iclass 12, count 2 2006.218.08:11:30.99#ibcon#about to read 3, iclass 12, count 2 2006.218.08:11:31.01#ibcon#read 3, iclass 12, count 2 2006.218.08:11:31.01#ibcon#about to read 4, iclass 12, count 2 2006.218.08:11:31.01#ibcon#read 4, iclass 12, count 2 2006.218.08:11:31.01#ibcon#about to read 5, iclass 12, count 2 2006.218.08:11:31.01#ibcon#read 5, iclass 12, count 2 2006.218.08:11:31.01#ibcon#about to read 6, iclass 12, count 2 2006.218.08:11:31.01#ibcon#read 6, iclass 12, count 2 2006.218.08:11:31.01#ibcon#end of sib2, iclass 12, count 2 2006.218.08:11:31.01#ibcon#*mode == 0, iclass 12, count 2 2006.218.08:11:31.01#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.218.08:11:31.01#ibcon#[27=AT02-04\r\n] 2006.218.08:11:31.01#ibcon#*before write, iclass 12, count 2 2006.218.08:11:31.01#ibcon#enter sib2, iclass 12, count 2 2006.218.08:11:31.01#ibcon#flushed, iclass 12, count 2 2006.218.08:11:31.01#ibcon#about to write, iclass 12, count 2 2006.218.08:11:31.01#ibcon#wrote, iclass 12, count 2 2006.218.08:11:31.01#ibcon#about to read 3, iclass 12, count 2 2006.218.08:11:31.04#ibcon#read 3, iclass 12, count 2 2006.218.08:11:31.04#ibcon#about to read 4, iclass 12, count 2 2006.218.08:11:31.04#ibcon#read 4, iclass 12, count 2 2006.218.08:11:31.04#ibcon#about to read 5, iclass 12, count 2 2006.218.08:11:31.04#ibcon#read 5, iclass 12, count 2 2006.218.08:11:31.04#ibcon#about to read 6, iclass 12, count 2 2006.218.08:11:31.04#ibcon#read 6, iclass 12, count 2 2006.218.08:11:31.04#ibcon#end of sib2, iclass 12, count 2 2006.218.08:11:31.04#ibcon#*after write, iclass 12, count 2 2006.218.08:11:31.04#ibcon#*before return 0, iclass 12, count 2 2006.218.08:11:31.04#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.218.08:11:31.04#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.218.08:11:31.04#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.218.08:11:31.04#ibcon#ireg 7 cls_cnt 0 2006.218.08:11:31.04#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.218.08:11:31.16#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.218.08:11:31.16#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.218.08:11:31.16#ibcon#enter wrdev, iclass 12, count 0 2006.218.08:11:31.16#ibcon#first serial, iclass 12, count 0 2006.218.08:11:31.16#ibcon#enter sib2, iclass 12, count 0 2006.218.08:11:31.16#ibcon#flushed, iclass 12, count 0 2006.218.08:11:31.16#ibcon#about to write, iclass 12, count 0 2006.218.08:11:31.16#ibcon#wrote, iclass 12, count 0 2006.218.08:11:31.16#ibcon#about to read 3, iclass 12, count 0 2006.218.08:11:31.18#ibcon#read 3, iclass 12, count 0 2006.218.08:11:31.18#ibcon#about to read 4, iclass 12, count 0 2006.218.08:11:31.18#ibcon#read 4, iclass 12, count 0 2006.218.08:11:31.18#ibcon#about to read 5, iclass 12, count 0 2006.218.08:11:31.18#ibcon#read 5, iclass 12, count 0 2006.218.08:11:31.18#ibcon#about to read 6, iclass 12, count 0 2006.218.08:11:31.18#ibcon#read 6, iclass 12, count 0 2006.218.08:11:31.18#ibcon#end of sib2, iclass 12, count 0 2006.218.08:11:31.18#ibcon#*mode == 0, iclass 12, count 0 2006.218.08:11:31.18#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.218.08:11:31.18#ibcon#[27=USB\r\n] 2006.218.08:11:31.18#ibcon#*before write, iclass 12, count 0 2006.218.08:11:31.18#ibcon#enter sib2, iclass 12, count 0 2006.218.08:11:31.18#ibcon#flushed, iclass 12, count 0 2006.218.08:11:31.18#ibcon#about to write, iclass 12, count 0 2006.218.08:11:31.18#ibcon#wrote, iclass 12, count 0 2006.218.08:11:31.18#ibcon#about to read 3, iclass 12, count 0 2006.218.08:11:31.21#ibcon#read 3, iclass 12, count 0 2006.218.08:11:31.21#ibcon#about to read 4, iclass 12, count 0 2006.218.08:11:31.21#ibcon#read 4, iclass 12, count 0 2006.218.08:11:31.21#ibcon#about to read 5, iclass 12, count 0 2006.218.08:11:31.21#ibcon#read 5, iclass 12, count 0 2006.218.08:11:31.21#ibcon#about to read 6, iclass 12, count 0 2006.218.08:11:31.21#ibcon#read 6, iclass 12, count 0 2006.218.08:11:31.21#ibcon#end of sib2, iclass 12, count 0 2006.218.08:11:31.21#ibcon#*after write, iclass 12, count 0 2006.218.08:11:31.21#ibcon#*before return 0, iclass 12, count 0 2006.218.08:11:31.21#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.218.08:11:31.21#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.218.08:11:31.21#ibcon#about to clear, iclass 12 cls_cnt 0 2006.218.08:11:31.21#ibcon#cleared, iclass 12 cls_cnt 0 2006.218.08:11:31.21$vc4f8/vblo=3,656.99 2006.218.08:11:31.21#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.218.08:11:31.21#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.218.08:11:31.21#ibcon#ireg 17 cls_cnt 0 2006.218.08:11:31.21#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.218.08:11:31.21#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.218.08:11:31.21#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.218.08:11:31.21#ibcon#enter wrdev, iclass 14, count 0 2006.218.08:11:31.21#ibcon#first serial, iclass 14, count 0 2006.218.08:11:31.21#ibcon#enter sib2, iclass 14, count 0 2006.218.08:11:31.21#ibcon#flushed, iclass 14, count 0 2006.218.08:11:31.21#ibcon#about to write, iclass 14, count 0 2006.218.08:11:31.21#ibcon#wrote, iclass 14, count 0 2006.218.08:11:31.21#ibcon#about to read 3, iclass 14, count 0 2006.218.08:11:31.23#ibcon#read 3, iclass 14, count 0 2006.218.08:11:31.23#ibcon#about to read 4, iclass 14, count 0 2006.218.08:11:31.23#ibcon#read 4, iclass 14, count 0 2006.218.08:11:31.23#ibcon#about to read 5, iclass 14, count 0 2006.218.08:11:31.23#ibcon#read 5, iclass 14, count 0 2006.218.08:11:31.23#ibcon#about to read 6, iclass 14, count 0 2006.218.08:11:31.23#ibcon#read 6, iclass 14, count 0 2006.218.08:11:31.23#ibcon#end of sib2, iclass 14, count 0 2006.218.08:11:31.23#ibcon#*mode == 0, iclass 14, count 0 2006.218.08:11:31.23#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.218.08:11:31.23#ibcon#[28=FRQ=03,656.99\r\n] 2006.218.08:11:31.23#ibcon#*before write, iclass 14, count 0 2006.218.08:11:31.23#ibcon#enter sib2, iclass 14, count 0 2006.218.08:11:31.23#ibcon#flushed, iclass 14, count 0 2006.218.08:11:31.23#ibcon#about to write, iclass 14, count 0 2006.218.08:11:31.23#ibcon#wrote, iclass 14, count 0 2006.218.08:11:31.23#ibcon#about to read 3, iclass 14, count 0 2006.218.08:11:31.27#ibcon#read 3, iclass 14, count 0 2006.218.08:11:31.27#ibcon#about to read 4, iclass 14, count 0 2006.218.08:11:31.27#ibcon#read 4, iclass 14, count 0 2006.218.08:11:31.27#ibcon#about to read 5, iclass 14, count 0 2006.218.08:11:31.27#ibcon#read 5, iclass 14, count 0 2006.218.08:11:31.27#ibcon#about to read 6, iclass 14, count 0 2006.218.08:11:31.27#ibcon#read 6, iclass 14, count 0 2006.218.08:11:31.27#ibcon#end of sib2, iclass 14, count 0 2006.218.08:11:31.27#ibcon#*after write, iclass 14, count 0 2006.218.08:11:31.27#ibcon#*before return 0, iclass 14, count 0 2006.218.08:11:31.27#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.218.08:11:31.27#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.218.08:11:31.27#ibcon#about to clear, iclass 14 cls_cnt 0 2006.218.08:11:31.27#ibcon#cleared, iclass 14 cls_cnt 0 2006.218.08:11:31.27$vc4f8/vb=3,4 2006.218.08:11:31.27#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.218.08:11:31.27#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.218.08:11:31.27#ibcon#ireg 11 cls_cnt 2 2006.218.08:11:31.27#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.218.08:11:31.33#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.218.08:11:31.33#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.218.08:11:31.33#ibcon#enter wrdev, iclass 16, count 2 2006.218.08:11:31.33#ibcon#first serial, iclass 16, count 2 2006.218.08:11:31.33#ibcon#enter sib2, iclass 16, count 2 2006.218.08:11:31.33#ibcon#flushed, iclass 16, count 2 2006.218.08:11:31.33#ibcon#about to write, iclass 16, count 2 2006.218.08:11:31.33#ibcon#wrote, iclass 16, count 2 2006.218.08:11:31.33#ibcon#about to read 3, iclass 16, count 2 2006.218.08:11:31.35#ibcon#read 3, iclass 16, count 2 2006.218.08:11:31.35#ibcon#about to read 4, iclass 16, count 2 2006.218.08:11:31.35#ibcon#read 4, iclass 16, count 2 2006.218.08:11:31.35#ibcon#about to read 5, iclass 16, count 2 2006.218.08:11:31.35#ibcon#read 5, iclass 16, count 2 2006.218.08:11:31.35#ibcon#about to read 6, iclass 16, count 2 2006.218.08:11:31.35#ibcon#read 6, iclass 16, count 2 2006.218.08:11:31.35#ibcon#end of sib2, iclass 16, count 2 2006.218.08:11:31.35#ibcon#*mode == 0, iclass 16, count 2 2006.218.08:11:31.35#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.218.08:11:31.35#ibcon#[27=AT03-04\r\n] 2006.218.08:11:31.35#ibcon#*before write, iclass 16, count 2 2006.218.08:11:31.35#ibcon#enter sib2, iclass 16, count 2 2006.218.08:11:31.35#ibcon#flushed, iclass 16, count 2 2006.218.08:11:31.35#ibcon#about to write, iclass 16, count 2 2006.218.08:11:31.35#ibcon#wrote, iclass 16, count 2 2006.218.08:11:31.35#ibcon#about to read 3, iclass 16, count 2 2006.218.08:11:31.38#ibcon#read 3, iclass 16, count 2 2006.218.08:11:31.39#ibcon#about to read 4, iclass 16, count 2 2006.218.08:11:31.39#ibcon#read 4, iclass 16, count 2 2006.218.08:11:31.39#ibcon#about to read 5, iclass 16, count 2 2006.218.08:11:31.39#ibcon#read 5, iclass 16, count 2 2006.218.08:11:31.39#ibcon#about to read 6, iclass 16, count 2 2006.218.08:11:31.39#ibcon#read 6, iclass 16, count 2 2006.218.08:11:31.39#ibcon#end of sib2, iclass 16, count 2 2006.218.08:11:31.39#ibcon#*after write, iclass 16, count 2 2006.218.08:11:31.39#ibcon#*before return 0, iclass 16, count 2 2006.218.08:11:31.39#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.218.08:11:31.39#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.218.08:11:31.39#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.218.08:11:31.39#ibcon#ireg 7 cls_cnt 0 2006.218.08:11:31.39#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.218.08:11:31.50#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.218.08:11:31.50#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.218.08:11:31.50#ibcon#enter wrdev, iclass 16, count 0 2006.218.08:11:31.50#ibcon#first serial, iclass 16, count 0 2006.218.08:11:31.50#ibcon#enter sib2, iclass 16, count 0 2006.218.08:11:31.50#ibcon#flushed, iclass 16, count 0 2006.218.08:11:31.50#ibcon#about to write, iclass 16, count 0 2006.218.08:11:31.50#ibcon#wrote, iclass 16, count 0 2006.218.08:11:31.50#ibcon#about to read 3, iclass 16, count 0 2006.218.08:11:31.52#ibcon#read 3, iclass 16, count 0 2006.218.08:11:31.52#ibcon#about to read 4, iclass 16, count 0 2006.218.08:11:31.52#ibcon#read 4, iclass 16, count 0 2006.218.08:11:31.52#ibcon#about to read 5, iclass 16, count 0 2006.218.08:11:31.52#ibcon#read 5, iclass 16, count 0 2006.218.08:11:31.52#ibcon#about to read 6, iclass 16, count 0 2006.218.08:11:31.52#ibcon#read 6, iclass 16, count 0 2006.218.08:11:31.52#ibcon#end of sib2, iclass 16, count 0 2006.218.08:11:31.52#ibcon#*mode == 0, iclass 16, count 0 2006.218.08:11:31.52#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.218.08:11:31.52#ibcon#[27=USB\r\n] 2006.218.08:11:31.52#ibcon#*before write, iclass 16, count 0 2006.218.08:11:31.52#ibcon#enter sib2, iclass 16, count 0 2006.218.08:11:31.52#ibcon#flushed, iclass 16, count 0 2006.218.08:11:31.52#ibcon#about to write, iclass 16, count 0 2006.218.08:11:31.52#ibcon#wrote, iclass 16, count 0 2006.218.08:11:31.52#ibcon#about to read 3, iclass 16, count 0 2006.218.08:11:31.55#ibcon#read 3, iclass 16, count 0 2006.218.08:11:31.55#ibcon#about to read 4, iclass 16, count 0 2006.218.08:11:31.55#ibcon#read 4, iclass 16, count 0 2006.218.08:11:31.55#ibcon#about to read 5, iclass 16, count 0 2006.218.08:11:31.55#ibcon#read 5, iclass 16, count 0 2006.218.08:11:31.55#ibcon#about to read 6, iclass 16, count 0 2006.218.08:11:31.55#ibcon#read 6, iclass 16, count 0 2006.218.08:11:31.55#ibcon#end of sib2, iclass 16, count 0 2006.218.08:11:31.55#ibcon#*after write, iclass 16, count 0 2006.218.08:11:31.55#ibcon#*before return 0, iclass 16, count 0 2006.218.08:11:31.55#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.218.08:11:31.55#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.218.08:11:31.55#ibcon#about to clear, iclass 16 cls_cnt 0 2006.218.08:11:31.55#ibcon#cleared, iclass 16 cls_cnt 0 2006.218.08:11:31.55$vc4f8/vblo=4,712.99 2006.218.08:11:31.55#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.218.08:11:31.55#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.218.08:11:31.55#ibcon#ireg 17 cls_cnt 0 2006.218.08:11:31.55#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.218.08:11:31.55#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.218.08:11:31.55#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.218.08:11:31.55#ibcon#enter wrdev, iclass 18, count 0 2006.218.08:11:31.55#ibcon#first serial, iclass 18, count 0 2006.218.08:11:31.55#ibcon#enter sib2, iclass 18, count 0 2006.218.08:11:31.55#ibcon#flushed, iclass 18, count 0 2006.218.08:11:31.55#ibcon#about to write, iclass 18, count 0 2006.218.08:11:31.55#ibcon#wrote, iclass 18, count 0 2006.218.08:11:31.55#ibcon#about to read 3, iclass 18, count 0 2006.218.08:11:31.57#ibcon#read 3, iclass 18, count 0 2006.218.08:11:31.57#ibcon#about to read 4, iclass 18, count 0 2006.218.08:11:31.57#ibcon#read 4, iclass 18, count 0 2006.218.08:11:31.57#ibcon#about to read 5, iclass 18, count 0 2006.218.08:11:31.57#ibcon#read 5, iclass 18, count 0 2006.218.08:11:31.57#ibcon#about to read 6, iclass 18, count 0 2006.218.08:11:31.57#ibcon#read 6, iclass 18, count 0 2006.218.08:11:31.57#ibcon#end of sib2, iclass 18, count 0 2006.218.08:11:31.57#ibcon#*mode == 0, iclass 18, count 0 2006.218.08:11:31.57#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.218.08:11:31.57#ibcon#[28=FRQ=04,712.99\r\n] 2006.218.08:11:31.57#ibcon#*before write, iclass 18, count 0 2006.218.08:11:31.57#ibcon#enter sib2, iclass 18, count 0 2006.218.08:11:31.57#ibcon#flushed, iclass 18, count 0 2006.218.08:11:31.57#ibcon#about to write, iclass 18, count 0 2006.218.08:11:31.57#ibcon#wrote, iclass 18, count 0 2006.218.08:11:31.57#ibcon#about to read 3, iclass 18, count 0 2006.218.08:11:31.61#ibcon#read 3, iclass 18, count 0 2006.218.08:11:31.61#ibcon#about to read 4, iclass 18, count 0 2006.218.08:11:31.61#ibcon#read 4, iclass 18, count 0 2006.218.08:11:31.61#ibcon#about to read 5, iclass 18, count 0 2006.218.08:11:31.61#ibcon#read 5, iclass 18, count 0 2006.218.08:11:31.61#ibcon#about to read 6, iclass 18, count 0 2006.218.08:11:31.61#ibcon#read 6, iclass 18, count 0 2006.218.08:11:31.61#ibcon#end of sib2, iclass 18, count 0 2006.218.08:11:31.61#ibcon#*after write, iclass 18, count 0 2006.218.08:11:31.61#ibcon#*before return 0, iclass 18, count 0 2006.218.08:11:31.61#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.218.08:11:31.61#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.218.08:11:31.61#ibcon#about to clear, iclass 18 cls_cnt 0 2006.218.08:11:31.61#ibcon#cleared, iclass 18 cls_cnt 0 2006.218.08:11:31.61$vc4f8/vb=4,4 2006.218.08:11:31.61#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.218.08:11:31.61#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.218.08:11:31.61#ibcon#ireg 11 cls_cnt 2 2006.218.08:11:31.61#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.218.08:11:31.67#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.218.08:11:31.67#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.218.08:11:31.67#ibcon#enter wrdev, iclass 20, count 2 2006.218.08:11:31.67#ibcon#first serial, iclass 20, count 2 2006.218.08:11:31.67#ibcon#enter sib2, iclass 20, count 2 2006.218.08:11:31.67#ibcon#flushed, iclass 20, count 2 2006.218.08:11:31.67#ibcon#about to write, iclass 20, count 2 2006.218.08:11:31.67#ibcon#wrote, iclass 20, count 2 2006.218.08:11:31.67#ibcon#about to read 3, iclass 20, count 2 2006.218.08:11:31.69#ibcon#read 3, iclass 20, count 2 2006.218.08:11:31.69#ibcon#about to read 4, iclass 20, count 2 2006.218.08:11:31.69#ibcon#read 4, iclass 20, count 2 2006.218.08:11:31.69#ibcon#about to read 5, iclass 20, count 2 2006.218.08:11:31.69#ibcon#read 5, iclass 20, count 2 2006.218.08:11:31.69#ibcon#about to read 6, iclass 20, count 2 2006.218.08:11:31.69#ibcon#read 6, iclass 20, count 2 2006.218.08:11:31.69#ibcon#end of sib2, iclass 20, count 2 2006.218.08:11:31.69#ibcon#*mode == 0, iclass 20, count 2 2006.218.08:11:31.69#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.218.08:11:31.69#ibcon#[27=AT04-04\r\n] 2006.218.08:11:31.69#ibcon#*before write, iclass 20, count 2 2006.218.08:11:31.69#ibcon#enter sib2, iclass 20, count 2 2006.218.08:11:31.69#ibcon#flushed, iclass 20, count 2 2006.218.08:11:31.69#ibcon#about to write, iclass 20, count 2 2006.218.08:11:31.69#ibcon#wrote, iclass 20, count 2 2006.218.08:11:31.69#ibcon#about to read 3, iclass 20, count 2 2006.218.08:11:31.72#ibcon#read 3, iclass 20, count 2 2006.218.08:11:31.72#ibcon#about to read 4, iclass 20, count 2 2006.218.08:11:31.72#ibcon#read 4, iclass 20, count 2 2006.218.08:11:31.72#ibcon#about to read 5, iclass 20, count 2 2006.218.08:11:31.72#ibcon#read 5, iclass 20, count 2 2006.218.08:11:31.72#ibcon#about to read 6, iclass 20, count 2 2006.218.08:11:31.72#ibcon#read 6, iclass 20, count 2 2006.218.08:11:31.72#ibcon#end of sib2, iclass 20, count 2 2006.218.08:11:31.72#ibcon#*after write, iclass 20, count 2 2006.218.08:11:31.72#ibcon#*before return 0, iclass 20, count 2 2006.218.08:11:31.72#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.218.08:11:31.72#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.218.08:11:31.72#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.218.08:11:31.72#ibcon#ireg 7 cls_cnt 0 2006.218.08:11:31.72#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.218.08:11:31.84#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.218.08:11:31.84#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.218.08:11:31.84#ibcon#enter wrdev, iclass 20, count 0 2006.218.08:11:31.84#ibcon#first serial, iclass 20, count 0 2006.218.08:11:31.84#ibcon#enter sib2, iclass 20, count 0 2006.218.08:11:31.84#ibcon#flushed, iclass 20, count 0 2006.218.08:11:31.84#ibcon#about to write, iclass 20, count 0 2006.218.08:11:31.84#ibcon#wrote, iclass 20, count 0 2006.218.08:11:31.84#ibcon#about to read 3, iclass 20, count 0 2006.218.08:11:31.86#ibcon#read 3, iclass 20, count 0 2006.218.08:11:31.86#ibcon#about to read 4, iclass 20, count 0 2006.218.08:11:31.86#ibcon#read 4, iclass 20, count 0 2006.218.08:11:31.86#ibcon#about to read 5, iclass 20, count 0 2006.218.08:11:31.86#ibcon#read 5, iclass 20, count 0 2006.218.08:11:31.86#ibcon#about to read 6, iclass 20, count 0 2006.218.08:11:31.86#ibcon#read 6, iclass 20, count 0 2006.218.08:11:31.86#ibcon#end of sib2, iclass 20, count 0 2006.218.08:11:31.86#ibcon#*mode == 0, iclass 20, count 0 2006.218.08:11:31.86#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.218.08:11:31.86#ibcon#[27=USB\r\n] 2006.218.08:11:31.86#ibcon#*before write, iclass 20, count 0 2006.218.08:11:31.86#ibcon#enter sib2, iclass 20, count 0 2006.218.08:11:31.86#ibcon#flushed, iclass 20, count 0 2006.218.08:11:31.86#ibcon#about to write, iclass 20, count 0 2006.218.08:11:31.86#ibcon#wrote, iclass 20, count 0 2006.218.08:11:31.86#ibcon#about to read 3, iclass 20, count 0 2006.218.08:11:31.89#ibcon#read 3, iclass 20, count 0 2006.218.08:11:31.89#ibcon#about to read 4, iclass 20, count 0 2006.218.08:11:31.89#ibcon#read 4, iclass 20, count 0 2006.218.08:11:31.89#ibcon#about to read 5, iclass 20, count 0 2006.218.08:11:31.89#ibcon#read 5, iclass 20, count 0 2006.218.08:11:31.89#ibcon#about to read 6, iclass 20, count 0 2006.218.08:11:31.89#ibcon#read 6, iclass 20, count 0 2006.218.08:11:31.89#ibcon#end of sib2, iclass 20, count 0 2006.218.08:11:31.89#ibcon#*after write, iclass 20, count 0 2006.218.08:11:31.89#ibcon#*before return 0, iclass 20, count 0 2006.218.08:11:31.89#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.218.08:11:31.89#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.218.08:11:31.89#ibcon#about to clear, iclass 20 cls_cnt 0 2006.218.08:11:31.89#ibcon#cleared, iclass 20 cls_cnt 0 2006.218.08:11:31.89$vc4f8/vblo=5,744.99 2006.218.08:11:31.89#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.218.08:11:31.89#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.218.08:11:31.89#ibcon#ireg 17 cls_cnt 0 2006.218.08:11:31.89#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.218.08:11:31.89#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.218.08:11:31.89#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.218.08:11:31.89#ibcon#enter wrdev, iclass 22, count 0 2006.218.08:11:31.89#ibcon#first serial, iclass 22, count 0 2006.218.08:11:31.89#ibcon#enter sib2, iclass 22, count 0 2006.218.08:11:31.89#ibcon#flushed, iclass 22, count 0 2006.218.08:11:31.89#ibcon#about to write, iclass 22, count 0 2006.218.08:11:31.89#ibcon#wrote, iclass 22, count 0 2006.218.08:11:31.89#ibcon#about to read 3, iclass 22, count 0 2006.218.08:11:31.91#ibcon#read 3, iclass 22, count 0 2006.218.08:11:31.91#ibcon#about to read 4, iclass 22, count 0 2006.218.08:11:31.91#ibcon#read 4, iclass 22, count 0 2006.218.08:11:31.91#ibcon#about to read 5, iclass 22, count 0 2006.218.08:11:31.91#ibcon#read 5, iclass 22, count 0 2006.218.08:11:31.91#ibcon#about to read 6, iclass 22, count 0 2006.218.08:11:31.91#ibcon#read 6, iclass 22, count 0 2006.218.08:11:31.91#ibcon#end of sib2, iclass 22, count 0 2006.218.08:11:31.91#ibcon#*mode == 0, iclass 22, count 0 2006.218.08:11:31.91#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.218.08:11:31.91#ibcon#[28=FRQ=05,744.99\r\n] 2006.218.08:11:31.91#ibcon#*before write, iclass 22, count 0 2006.218.08:11:31.91#ibcon#enter sib2, iclass 22, count 0 2006.218.08:11:31.91#ibcon#flushed, iclass 22, count 0 2006.218.08:11:31.91#ibcon#about to write, iclass 22, count 0 2006.218.08:11:31.91#ibcon#wrote, iclass 22, count 0 2006.218.08:11:31.91#ibcon#about to read 3, iclass 22, count 0 2006.218.08:11:31.95#ibcon#read 3, iclass 22, count 0 2006.218.08:11:31.95#ibcon#about to read 4, iclass 22, count 0 2006.218.08:11:31.95#ibcon#read 4, iclass 22, count 0 2006.218.08:11:31.95#ibcon#about to read 5, iclass 22, count 0 2006.218.08:11:31.95#ibcon#read 5, iclass 22, count 0 2006.218.08:11:31.95#ibcon#about to read 6, iclass 22, count 0 2006.218.08:11:31.95#ibcon#read 6, iclass 22, count 0 2006.218.08:11:31.95#ibcon#end of sib2, iclass 22, count 0 2006.218.08:11:31.95#ibcon#*after write, iclass 22, count 0 2006.218.08:11:31.95#ibcon#*before return 0, iclass 22, count 0 2006.218.08:11:31.95#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.218.08:11:31.95#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.218.08:11:31.95#ibcon#about to clear, iclass 22 cls_cnt 0 2006.218.08:11:31.95#ibcon#cleared, iclass 22 cls_cnt 0 2006.218.08:11:31.95$vc4f8/vb=5,4 2006.218.08:11:31.95#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.218.08:11:31.95#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.218.08:11:31.95#ibcon#ireg 11 cls_cnt 2 2006.218.08:11:31.95#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.218.08:11:32.01#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.218.08:11:32.01#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.218.08:11:32.01#ibcon#enter wrdev, iclass 24, count 2 2006.218.08:11:32.01#ibcon#first serial, iclass 24, count 2 2006.218.08:11:32.01#ibcon#enter sib2, iclass 24, count 2 2006.218.08:11:32.01#ibcon#flushed, iclass 24, count 2 2006.218.08:11:32.01#ibcon#about to write, iclass 24, count 2 2006.218.08:11:32.01#ibcon#wrote, iclass 24, count 2 2006.218.08:11:32.01#ibcon#about to read 3, iclass 24, count 2 2006.218.08:11:32.03#ibcon#read 3, iclass 24, count 2 2006.218.08:11:32.03#ibcon#about to read 4, iclass 24, count 2 2006.218.08:11:32.03#ibcon#read 4, iclass 24, count 2 2006.218.08:11:32.03#ibcon#about to read 5, iclass 24, count 2 2006.218.08:11:32.03#ibcon#read 5, iclass 24, count 2 2006.218.08:11:32.03#ibcon#about to read 6, iclass 24, count 2 2006.218.08:11:32.03#ibcon#read 6, iclass 24, count 2 2006.218.08:11:32.03#ibcon#end of sib2, iclass 24, count 2 2006.218.08:11:32.03#ibcon#*mode == 0, iclass 24, count 2 2006.218.08:11:32.03#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.218.08:11:32.03#ibcon#[27=AT05-04\r\n] 2006.218.08:11:32.03#ibcon#*before write, iclass 24, count 2 2006.218.08:11:32.03#ibcon#enter sib2, iclass 24, count 2 2006.218.08:11:32.03#ibcon#flushed, iclass 24, count 2 2006.218.08:11:32.03#ibcon#about to write, iclass 24, count 2 2006.218.08:11:32.03#ibcon#wrote, iclass 24, count 2 2006.218.08:11:32.03#ibcon#about to read 3, iclass 24, count 2 2006.218.08:11:32.06#ibcon#read 3, iclass 24, count 2 2006.218.08:11:32.06#ibcon#about to read 4, iclass 24, count 2 2006.218.08:11:32.06#ibcon#read 4, iclass 24, count 2 2006.218.08:11:32.06#ibcon#about to read 5, iclass 24, count 2 2006.218.08:11:32.06#ibcon#read 5, iclass 24, count 2 2006.218.08:11:32.06#ibcon#about to read 6, iclass 24, count 2 2006.218.08:11:32.06#ibcon#read 6, iclass 24, count 2 2006.218.08:11:32.06#ibcon#end of sib2, iclass 24, count 2 2006.218.08:11:32.06#ibcon#*after write, iclass 24, count 2 2006.218.08:11:32.06#ibcon#*before return 0, iclass 24, count 2 2006.218.08:11:32.06#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.218.08:11:32.06#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.218.08:11:32.06#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.218.08:11:32.06#ibcon#ireg 7 cls_cnt 0 2006.218.08:11:32.06#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.218.08:11:32.18#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.218.08:11:32.18#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.218.08:11:32.18#ibcon#enter wrdev, iclass 24, count 0 2006.218.08:11:32.18#ibcon#first serial, iclass 24, count 0 2006.218.08:11:32.18#ibcon#enter sib2, iclass 24, count 0 2006.218.08:11:32.18#ibcon#flushed, iclass 24, count 0 2006.218.08:11:32.18#ibcon#about to write, iclass 24, count 0 2006.218.08:11:32.18#ibcon#wrote, iclass 24, count 0 2006.218.08:11:32.18#ibcon#about to read 3, iclass 24, count 0 2006.218.08:11:32.20#ibcon#read 3, iclass 24, count 0 2006.218.08:11:32.20#ibcon#about to read 4, iclass 24, count 0 2006.218.08:11:32.20#ibcon#read 4, iclass 24, count 0 2006.218.08:11:32.20#ibcon#about to read 5, iclass 24, count 0 2006.218.08:11:32.20#ibcon#read 5, iclass 24, count 0 2006.218.08:11:32.20#ibcon#about to read 6, iclass 24, count 0 2006.218.08:11:32.20#ibcon#read 6, iclass 24, count 0 2006.218.08:11:32.20#ibcon#end of sib2, iclass 24, count 0 2006.218.08:11:32.20#ibcon#*mode == 0, iclass 24, count 0 2006.218.08:11:32.20#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.218.08:11:32.20#ibcon#[27=USB\r\n] 2006.218.08:11:32.20#ibcon#*before write, iclass 24, count 0 2006.218.08:11:32.20#ibcon#enter sib2, iclass 24, count 0 2006.218.08:11:32.20#ibcon#flushed, iclass 24, count 0 2006.218.08:11:32.20#ibcon#about to write, iclass 24, count 0 2006.218.08:11:32.20#ibcon#wrote, iclass 24, count 0 2006.218.08:11:32.20#ibcon#about to read 3, iclass 24, count 0 2006.218.08:11:32.23#ibcon#read 3, iclass 24, count 0 2006.218.08:11:32.23#ibcon#about to read 4, iclass 24, count 0 2006.218.08:11:32.23#ibcon#read 4, iclass 24, count 0 2006.218.08:11:32.23#ibcon#about to read 5, iclass 24, count 0 2006.218.08:11:32.23#ibcon#read 5, iclass 24, count 0 2006.218.08:11:32.23#ibcon#about to read 6, iclass 24, count 0 2006.218.08:11:32.23#ibcon#read 6, iclass 24, count 0 2006.218.08:11:32.23#ibcon#end of sib2, iclass 24, count 0 2006.218.08:11:32.23#ibcon#*after write, iclass 24, count 0 2006.218.08:11:32.23#ibcon#*before return 0, iclass 24, count 0 2006.218.08:11:32.23#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.218.08:11:32.23#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.218.08:11:32.23#ibcon#about to clear, iclass 24 cls_cnt 0 2006.218.08:11:32.23#ibcon#cleared, iclass 24 cls_cnt 0 2006.218.08:11:32.23$vc4f8/vblo=6,752.99 2006.218.08:11:32.23#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.218.08:11:32.23#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.218.08:11:32.23#ibcon#ireg 17 cls_cnt 0 2006.218.08:11:32.23#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.218.08:11:32.23#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.218.08:11:32.23#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.218.08:11:32.23#ibcon#enter wrdev, iclass 26, count 0 2006.218.08:11:32.23#ibcon#first serial, iclass 26, count 0 2006.218.08:11:32.23#ibcon#enter sib2, iclass 26, count 0 2006.218.08:11:32.23#ibcon#flushed, iclass 26, count 0 2006.218.08:11:32.23#ibcon#about to write, iclass 26, count 0 2006.218.08:11:32.23#ibcon#wrote, iclass 26, count 0 2006.218.08:11:32.23#ibcon#about to read 3, iclass 26, count 0 2006.218.08:11:32.25#ibcon#read 3, iclass 26, count 0 2006.218.08:11:32.25#ibcon#about to read 4, iclass 26, count 0 2006.218.08:11:32.25#ibcon#read 4, iclass 26, count 0 2006.218.08:11:32.25#ibcon#about to read 5, iclass 26, count 0 2006.218.08:11:32.25#ibcon#read 5, iclass 26, count 0 2006.218.08:11:32.25#ibcon#about to read 6, iclass 26, count 0 2006.218.08:11:32.25#ibcon#read 6, iclass 26, count 0 2006.218.08:11:32.25#ibcon#end of sib2, iclass 26, count 0 2006.218.08:11:32.25#ibcon#*mode == 0, iclass 26, count 0 2006.218.08:11:32.25#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.218.08:11:32.25#ibcon#[28=FRQ=06,752.99\r\n] 2006.218.08:11:32.25#ibcon#*before write, iclass 26, count 0 2006.218.08:11:32.25#ibcon#enter sib2, iclass 26, count 0 2006.218.08:11:32.25#ibcon#flushed, iclass 26, count 0 2006.218.08:11:32.25#ibcon#about to write, iclass 26, count 0 2006.218.08:11:32.25#ibcon#wrote, iclass 26, count 0 2006.218.08:11:32.25#ibcon#about to read 3, iclass 26, count 0 2006.218.08:11:32.29#ibcon#read 3, iclass 26, count 0 2006.218.08:11:32.29#ibcon#about to read 4, iclass 26, count 0 2006.218.08:11:32.29#ibcon#read 4, iclass 26, count 0 2006.218.08:11:32.29#ibcon#about to read 5, iclass 26, count 0 2006.218.08:11:32.29#ibcon#read 5, iclass 26, count 0 2006.218.08:11:32.29#ibcon#about to read 6, iclass 26, count 0 2006.218.08:11:32.29#ibcon#read 6, iclass 26, count 0 2006.218.08:11:32.29#ibcon#end of sib2, iclass 26, count 0 2006.218.08:11:32.29#ibcon#*after write, iclass 26, count 0 2006.218.08:11:32.29#ibcon#*before return 0, iclass 26, count 0 2006.218.08:11:32.29#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.218.08:11:32.29#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.218.08:11:32.29#ibcon#about to clear, iclass 26 cls_cnt 0 2006.218.08:11:32.29#ibcon#cleared, iclass 26 cls_cnt 0 2006.218.08:11:32.29$vc4f8/vb=6,4 2006.218.08:11:32.29#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.218.08:11:32.29#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.218.08:11:32.29#ibcon#ireg 11 cls_cnt 2 2006.218.08:11:32.29#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.218.08:11:32.35#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.218.08:11:32.35#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.218.08:11:32.35#ibcon#enter wrdev, iclass 28, count 2 2006.218.08:11:32.35#ibcon#first serial, iclass 28, count 2 2006.218.08:11:32.35#ibcon#enter sib2, iclass 28, count 2 2006.218.08:11:32.35#ibcon#flushed, iclass 28, count 2 2006.218.08:11:32.35#ibcon#about to write, iclass 28, count 2 2006.218.08:11:32.35#ibcon#wrote, iclass 28, count 2 2006.218.08:11:32.35#ibcon#about to read 3, iclass 28, count 2 2006.218.08:11:32.37#ibcon#read 3, iclass 28, count 2 2006.218.08:11:32.37#ibcon#about to read 4, iclass 28, count 2 2006.218.08:11:32.37#ibcon#read 4, iclass 28, count 2 2006.218.08:11:32.37#ibcon#about to read 5, iclass 28, count 2 2006.218.08:11:32.37#ibcon#read 5, iclass 28, count 2 2006.218.08:11:32.37#ibcon#about to read 6, iclass 28, count 2 2006.218.08:11:32.37#ibcon#read 6, iclass 28, count 2 2006.218.08:11:32.37#ibcon#end of sib2, iclass 28, count 2 2006.218.08:11:32.37#ibcon#*mode == 0, iclass 28, count 2 2006.218.08:11:32.37#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.218.08:11:32.37#ibcon#[27=AT06-04\r\n] 2006.218.08:11:32.37#ibcon#*before write, iclass 28, count 2 2006.218.08:11:32.37#ibcon#enter sib2, iclass 28, count 2 2006.218.08:11:32.37#ibcon#flushed, iclass 28, count 2 2006.218.08:11:32.37#ibcon#about to write, iclass 28, count 2 2006.218.08:11:32.37#ibcon#wrote, iclass 28, count 2 2006.218.08:11:32.37#ibcon#about to read 3, iclass 28, count 2 2006.218.08:11:32.40#ibcon#read 3, iclass 28, count 2 2006.218.08:11:32.40#ibcon#about to read 4, iclass 28, count 2 2006.218.08:11:32.40#ibcon#read 4, iclass 28, count 2 2006.218.08:11:32.40#ibcon#about to read 5, iclass 28, count 2 2006.218.08:11:32.40#ibcon#read 5, iclass 28, count 2 2006.218.08:11:32.40#ibcon#about to read 6, iclass 28, count 2 2006.218.08:11:32.40#ibcon#read 6, iclass 28, count 2 2006.218.08:11:32.40#ibcon#end of sib2, iclass 28, count 2 2006.218.08:11:32.40#ibcon#*after write, iclass 28, count 2 2006.218.08:11:32.40#ibcon#*before return 0, iclass 28, count 2 2006.218.08:11:32.40#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.218.08:11:32.40#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.218.08:11:32.40#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.218.08:11:32.40#ibcon#ireg 7 cls_cnt 0 2006.218.08:11:32.40#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.218.08:11:32.52#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.218.08:11:32.52#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.218.08:11:32.52#ibcon#enter wrdev, iclass 28, count 0 2006.218.08:11:32.52#ibcon#first serial, iclass 28, count 0 2006.218.08:11:32.52#ibcon#enter sib2, iclass 28, count 0 2006.218.08:11:32.52#ibcon#flushed, iclass 28, count 0 2006.218.08:11:32.52#ibcon#about to write, iclass 28, count 0 2006.218.08:11:32.52#ibcon#wrote, iclass 28, count 0 2006.218.08:11:32.52#ibcon#about to read 3, iclass 28, count 0 2006.218.08:11:32.54#ibcon#read 3, iclass 28, count 0 2006.218.08:11:32.54#ibcon#about to read 4, iclass 28, count 0 2006.218.08:11:32.54#ibcon#read 4, iclass 28, count 0 2006.218.08:11:32.54#ibcon#about to read 5, iclass 28, count 0 2006.218.08:11:32.54#ibcon#read 5, iclass 28, count 0 2006.218.08:11:32.54#ibcon#about to read 6, iclass 28, count 0 2006.218.08:11:32.54#ibcon#read 6, iclass 28, count 0 2006.218.08:11:32.54#ibcon#end of sib2, iclass 28, count 0 2006.218.08:11:32.54#ibcon#*mode == 0, iclass 28, count 0 2006.218.08:11:32.54#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.218.08:11:32.54#ibcon#[27=USB\r\n] 2006.218.08:11:32.54#ibcon#*before write, iclass 28, count 0 2006.218.08:11:32.54#ibcon#enter sib2, iclass 28, count 0 2006.218.08:11:32.54#ibcon#flushed, iclass 28, count 0 2006.218.08:11:32.54#ibcon#about to write, iclass 28, count 0 2006.218.08:11:32.54#ibcon#wrote, iclass 28, count 0 2006.218.08:11:32.54#ibcon#about to read 3, iclass 28, count 0 2006.218.08:11:32.57#ibcon#read 3, iclass 28, count 0 2006.218.08:11:32.57#ibcon#about to read 4, iclass 28, count 0 2006.218.08:11:32.57#ibcon#read 4, iclass 28, count 0 2006.218.08:11:32.57#ibcon#about to read 5, iclass 28, count 0 2006.218.08:11:32.57#ibcon#read 5, iclass 28, count 0 2006.218.08:11:32.57#ibcon#about to read 6, iclass 28, count 0 2006.218.08:11:32.57#ibcon#read 6, iclass 28, count 0 2006.218.08:11:32.57#ibcon#end of sib2, iclass 28, count 0 2006.218.08:11:32.57#ibcon#*after write, iclass 28, count 0 2006.218.08:11:32.57#ibcon#*before return 0, iclass 28, count 0 2006.218.08:11:32.57#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.218.08:11:32.57#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.218.08:11:32.57#ibcon#about to clear, iclass 28 cls_cnt 0 2006.218.08:11:32.57#ibcon#cleared, iclass 28 cls_cnt 0 2006.218.08:11:32.57$vc4f8/vabw=wide 2006.218.08:11:32.57#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.218.08:11:32.57#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.218.08:11:32.57#ibcon#ireg 8 cls_cnt 0 2006.218.08:11:32.57#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.218.08:11:32.57#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.218.08:11:32.57#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.218.08:11:32.57#ibcon#enter wrdev, iclass 30, count 0 2006.218.08:11:32.57#ibcon#first serial, iclass 30, count 0 2006.218.08:11:32.57#ibcon#enter sib2, iclass 30, count 0 2006.218.08:11:32.57#ibcon#flushed, iclass 30, count 0 2006.218.08:11:32.57#ibcon#about to write, iclass 30, count 0 2006.218.08:11:32.57#ibcon#wrote, iclass 30, count 0 2006.218.08:11:32.57#ibcon#about to read 3, iclass 30, count 0 2006.218.08:11:32.59#ibcon#read 3, iclass 30, count 0 2006.218.08:11:32.59#ibcon#about to read 4, iclass 30, count 0 2006.218.08:11:32.59#ibcon#read 4, iclass 30, count 0 2006.218.08:11:32.59#ibcon#about to read 5, iclass 30, count 0 2006.218.08:11:32.59#ibcon#read 5, iclass 30, count 0 2006.218.08:11:32.59#ibcon#about to read 6, iclass 30, count 0 2006.218.08:11:32.59#ibcon#read 6, iclass 30, count 0 2006.218.08:11:32.59#ibcon#end of sib2, iclass 30, count 0 2006.218.08:11:32.59#ibcon#*mode == 0, iclass 30, count 0 2006.218.08:11:32.59#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.218.08:11:32.59#ibcon#[25=BW32\r\n] 2006.218.08:11:32.59#ibcon#*before write, iclass 30, count 0 2006.218.08:11:32.59#ibcon#enter sib2, iclass 30, count 0 2006.218.08:11:32.59#ibcon#flushed, iclass 30, count 0 2006.218.08:11:32.59#ibcon#about to write, iclass 30, count 0 2006.218.08:11:32.59#ibcon#wrote, iclass 30, count 0 2006.218.08:11:32.59#ibcon#about to read 3, iclass 30, count 0 2006.218.08:11:32.62#ibcon#read 3, iclass 30, count 0 2006.218.08:11:32.62#ibcon#about to read 4, iclass 30, count 0 2006.218.08:11:32.62#ibcon#read 4, iclass 30, count 0 2006.218.08:11:32.62#ibcon#about to read 5, iclass 30, count 0 2006.218.08:11:32.62#ibcon#read 5, iclass 30, count 0 2006.218.08:11:32.62#ibcon#about to read 6, iclass 30, count 0 2006.218.08:11:32.62#ibcon#read 6, iclass 30, count 0 2006.218.08:11:32.62#ibcon#end of sib2, iclass 30, count 0 2006.218.08:11:32.62#ibcon#*after write, iclass 30, count 0 2006.218.08:11:32.62#ibcon#*before return 0, iclass 30, count 0 2006.218.08:11:32.62#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.218.08:11:32.62#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.218.08:11:32.62#ibcon#about to clear, iclass 30 cls_cnt 0 2006.218.08:11:32.62#ibcon#cleared, iclass 30 cls_cnt 0 2006.218.08:11:32.62$vc4f8/vbbw=wide 2006.218.08:11:32.62#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.218.08:11:32.62#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.218.08:11:32.62#ibcon#ireg 8 cls_cnt 0 2006.218.08:11:32.62#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.218.08:11:32.69#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.218.08:11:32.69#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.218.08:11:32.69#ibcon#enter wrdev, iclass 32, count 0 2006.218.08:11:32.69#ibcon#first serial, iclass 32, count 0 2006.218.08:11:32.69#ibcon#enter sib2, iclass 32, count 0 2006.218.08:11:32.69#ibcon#flushed, iclass 32, count 0 2006.218.08:11:32.69#ibcon#about to write, iclass 32, count 0 2006.218.08:11:32.69#ibcon#wrote, iclass 32, count 0 2006.218.08:11:32.69#ibcon#about to read 3, iclass 32, count 0 2006.218.08:11:32.71#ibcon#read 3, iclass 32, count 0 2006.218.08:11:32.71#ibcon#about to read 4, iclass 32, count 0 2006.218.08:11:32.71#ibcon#read 4, iclass 32, count 0 2006.218.08:11:32.71#ibcon#about to read 5, iclass 32, count 0 2006.218.08:11:32.71#ibcon#read 5, iclass 32, count 0 2006.218.08:11:32.71#ibcon#about to read 6, iclass 32, count 0 2006.218.08:11:32.71#ibcon#read 6, iclass 32, count 0 2006.218.08:11:32.71#ibcon#end of sib2, iclass 32, count 0 2006.218.08:11:32.71#ibcon#*mode == 0, iclass 32, count 0 2006.218.08:11:32.71#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.218.08:11:32.71#ibcon#[27=BW32\r\n] 2006.218.08:11:32.71#ibcon#*before write, iclass 32, count 0 2006.218.08:11:32.71#ibcon#enter sib2, iclass 32, count 0 2006.218.08:11:32.71#ibcon#flushed, iclass 32, count 0 2006.218.08:11:32.71#ibcon#about to write, iclass 32, count 0 2006.218.08:11:32.71#ibcon#wrote, iclass 32, count 0 2006.218.08:11:32.71#ibcon#about to read 3, iclass 32, count 0 2006.218.08:11:32.74#ibcon#read 3, iclass 32, count 0 2006.218.08:11:32.74#ibcon#about to read 4, iclass 32, count 0 2006.218.08:11:32.74#ibcon#read 4, iclass 32, count 0 2006.218.08:11:32.74#ibcon#about to read 5, iclass 32, count 0 2006.218.08:11:32.74#ibcon#read 5, iclass 32, count 0 2006.218.08:11:32.74#ibcon#about to read 6, iclass 32, count 0 2006.218.08:11:32.74#ibcon#read 6, iclass 32, count 0 2006.218.08:11:32.74#ibcon#end of sib2, iclass 32, count 0 2006.218.08:11:32.74#ibcon#*after write, iclass 32, count 0 2006.218.08:11:32.74#ibcon#*before return 0, iclass 32, count 0 2006.218.08:11:32.74#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.218.08:11:32.74#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.218.08:11:32.74#ibcon#about to clear, iclass 32 cls_cnt 0 2006.218.08:11:32.74#ibcon#cleared, iclass 32 cls_cnt 0 2006.218.08:11:32.74$4f8m12a/ifd4f 2006.218.08:11:32.74$ifd4f/lo= 2006.218.08:11:32.74$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.218.08:11:32.74$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.218.08:11:32.74$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.218.08:11:32.74$ifd4f/patch= 2006.218.08:11:32.74$ifd4f/patch=lo1,a1,a2,a3,a4 2006.218.08:11:32.74$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.218.08:11:32.74$ifd4f/patch=lo3,a5,a6,a7,a8 2006.218.08:11:32.74$4f8m12a/"form=m,16.000,1:2 2006.218.08:11:32.74$4f8m12a/"tpicd 2006.218.08:11:32.74$4f8m12a/echo=off 2006.218.08:11:32.74$4f8m12a/xlog=off 2006.218.08:11:32.74:!2006.218.08:12:00 2006.218.08:11:39.13#trakl#Source acquired 2006.218.08:11:39.13#flagr#flagr/antenna,acquired 2006.218.08:12:00.00:preob 2006.218.08:12:01.14/onsource/TRACKING 2006.218.08:12:01.14:!2006.218.08:12:10 2006.218.08:12:10.00:data_valid=on 2006.218.08:12:10.00:midob 2006.218.08:12:10.14/onsource/TRACKING 2006.218.08:12:10.14/wx/30.87,1007.5,73 2006.218.08:12:10.26/cable/+6.3844E-03 2006.218.08:12:11.35/va/01,05,usb,yes,34,36 2006.218.08:12:11.35/va/02,04,usb,yes,32,33 2006.218.08:12:11.35/va/03,04,usb,yes,30,30 2006.218.08:12:11.35/va/04,04,usb,yes,33,36 2006.218.08:12:11.35/va/05,07,usb,yes,35,38 2006.218.08:12:11.35/va/06,06,usb,yes,35,34 2006.218.08:12:11.35/va/07,06,usb,yes,35,35 2006.218.08:12:11.35/va/08,07,usb,yes,33,33 2006.218.08:12:11.58/valo/01,532.99,yes,locked 2006.218.08:12:11.58/valo/02,572.99,yes,locked 2006.218.08:12:11.58/valo/03,672.99,yes,locked 2006.218.08:12:11.58/valo/04,832.99,yes,locked 2006.218.08:12:11.58/valo/05,652.99,yes,locked 2006.218.08:12:11.58/valo/06,772.99,yes,locked 2006.218.08:12:11.58/valo/07,832.99,yes,locked 2006.218.08:12:11.58/valo/08,852.99,yes,locked 2006.218.08:12:12.67/vb/01,04,usb,yes,31,30 2006.218.08:12:12.67/vb/02,04,usb,yes,33,35 2006.218.08:12:12.67/vb/03,04,usb,yes,29,33 2006.218.08:12:12.67/vb/04,04,usb,yes,30,31 2006.218.08:12:12.67/vb/05,04,usb,yes,29,33 2006.218.08:12:12.67/vb/06,04,usb,yes,30,33 2006.218.08:12:12.67/vb/07,04,usb,yes,32,32 2006.218.08:12:12.67/vb/08,04,usb,yes,29,33 2006.218.08:12:12.91/vblo/01,632.99,yes,locked 2006.218.08:12:12.91/vblo/02,640.99,yes,locked 2006.218.08:12:12.91/vblo/03,656.99,yes,locked 2006.218.08:12:12.91/vblo/04,712.99,yes,locked 2006.218.08:12:12.91/vblo/05,744.99,yes,locked 2006.218.08:12:12.91/vblo/06,752.99,yes,locked 2006.218.08:12:12.91/vblo/07,734.99,yes,locked 2006.218.08:12:12.91/vblo/08,744.99,yes,locked 2006.218.08:12:13.06/vabw/8 2006.218.08:12:13.21/vbbw/8 2006.218.08:12:13.31/xfe/off,on,15.5 2006.218.08:12:13.69/ifatt/23,28,28,28 2006.218.08:12:14.07/fmout-gps/S +4.62E-07 2006.218.08:12:14.11:!2006.218.08:13:10 2006.218.08:13:10.00:data_valid=off 2006.218.08:13:10.00:postob 2006.218.08:13:10.08/cable/+6.3853E-03 2006.218.08:13:10.08/wx/30.85,1007.6,74 2006.218.08:13:11.07/fmout-gps/S +4.61E-07 2006.218.08:13:11.07:scan_name=218-0814,k06218,60 2006.218.08:13:11.07:source=1044+719,104827.62,714335.9,2000.0,cw 2006.218.08:13:11.14#flagr#flagr/antenna,new-source 2006.218.08:13:12.14:checkk5 2006.218.08:13:12.51/chk_autoobs//k5ts1/ autoobs is running! 2006.218.08:13:12.88/chk_autoobs//k5ts2/ autoobs is running! 2006.218.08:13:13.26/chk_autoobs//k5ts3/ autoobs is running! 2006.218.08:13:13.63/chk_autoobs//k5ts4/ autoobs is running! 2006.218.08:13:13.99/chk_obsdata//k5ts1/T2180812??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.08:13:14.36/chk_obsdata//k5ts2/T2180812??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.08:13:14.77/chk_obsdata//k5ts3/T2180812??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.08:13:15.25/chk_obsdata//k5ts4/T2180812??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.08:13:15.95/k5log//k5ts1_log_newline 2006.218.08:13:16.64/k5log//k5ts2_log_newline 2006.218.08:13:17.32/k5log//k5ts3_log_newline 2006.218.08:13:18.00/k5log//k5ts4_log_newline 2006.218.08:13:18.03/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.218.08:13:18.03:4f8m12a=2 2006.218.08:13:18.03$4f8m12a/echo=on 2006.218.08:13:18.03$4f8m12a/pcalon 2006.218.08:13:18.03$pcalon/"no phase cal control is implemented here 2006.218.08:13:18.03$4f8m12a/"tpicd=stop 2006.218.08:13:18.03$4f8m12a/vc4f8 2006.218.08:13:18.03$vc4f8/valo=1,532.99 2006.218.08:13:18.04#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.218.08:13:18.04#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.218.08:13:18.04#ibcon#ireg 17 cls_cnt 0 2006.218.08:13:18.04#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.218.08:13:18.04#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.218.08:13:18.04#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.218.08:13:18.04#ibcon#enter wrdev, iclass 5, count 0 2006.218.08:13:18.04#ibcon#first serial, iclass 5, count 0 2006.218.08:13:18.04#ibcon#enter sib2, iclass 5, count 0 2006.218.08:13:18.04#ibcon#flushed, iclass 5, count 0 2006.218.08:13:18.04#ibcon#about to write, iclass 5, count 0 2006.218.08:13:18.04#ibcon#wrote, iclass 5, count 0 2006.218.08:13:18.04#ibcon#about to read 3, iclass 5, count 0 2006.218.08:13:18.07#ibcon#read 3, iclass 5, count 0 2006.218.08:13:18.07#ibcon#about to read 4, iclass 5, count 0 2006.218.08:13:18.07#ibcon#read 4, iclass 5, count 0 2006.218.08:13:18.07#ibcon#about to read 5, iclass 5, count 0 2006.218.08:13:18.07#ibcon#read 5, iclass 5, count 0 2006.218.08:13:18.07#ibcon#about to read 6, iclass 5, count 0 2006.218.08:13:18.07#ibcon#read 6, iclass 5, count 0 2006.218.08:13:18.07#ibcon#end of sib2, iclass 5, count 0 2006.218.08:13:18.07#ibcon#*mode == 0, iclass 5, count 0 2006.218.08:13:18.07#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.218.08:13:18.07#ibcon#[26=FRQ=01,532.99\r\n] 2006.218.08:13:18.07#ibcon#*before write, iclass 5, count 0 2006.218.08:13:18.07#ibcon#enter sib2, iclass 5, count 0 2006.218.08:13:18.07#ibcon#flushed, iclass 5, count 0 2006.218.08:13:18.07#ibcon#about to write, iclass 5, count 0 2006.218.08:13:18.07#ibcon#wrote, iclass 5, count 0 2006.218.08:13:18.07#ibcon#about to read 3, iclass 5, count 0 2006.218.08:13:18.12#ibcon#read 3, iclass 5, count 0 2006.218.08:13:18.12#ibcon#about to read 4, iclass 5, count 0 2006.218.08:13:18.12#ibcon#read 4, iclass 5, count 0 2006.218.08:13:18.12#ibcon#about to read 5, iclass 5, count 0 2006.218.08:13:18.12#ibcon#read 5, iclass 5, count 0 2006.218.08:13:18.12#ibcon#about to read 6, iclass 5, count 0 2006.218.08:13:18.12#ibcon#read 6, iclass 5, count 0 2006.218.08:13:18.12#ibcon#end of sib2, iclass 5, count 0 2006.218.08:13:18.12#ibcon#*after write, iclass 5, count 0 2006.218.08:13:18.12#ibcon#*before return 0, iclass 5, count 0 2006.218.08:13:18.12#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.218.08:13:18.12#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.218.08:13:18.12#ibcon#about to clear, iclass 5 cls_cnt 0 2006.218.08:13:18.12#ibcon#cleared, iclass 5 cls_cnt 0 2006.218.08:13:18.12$vc4f8/va=1,5 2006.218.08:13:18.12#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.218.08:13:18.12#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.218.08:13:18.12#ibcon#ireg 11 cls_cnt 2 2006.218.08:13:18.12#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.218.08:13:18.12#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.218.08:13:18.12#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.218.08:13:18.12#ibcon#enter wrdev, iclass 7, count 2 2006.218.08:13:18.12#ibcon#first serial, iclass 7, count 2 2006.218.08:13:18.12#ibcon#enter sib2, iclass 7, count 2 2006.218.08:13:18.12#ibcon#flushed, iclass 7, count 2 2006.218.08:13:18.12#ibcon#about to write, iclass 7, count 2 2006.218.08:13:18.12#ibcon#wrote, iclass 7, count 2 2006.218.08:13:18.12#ibcon#about to read 3, iclass 7, count 2 2006.218.08:13:18.14#ibcon#read 3, iclass 7, count 2 2006.218.08:13:18.14#ibcon#about to read 4, iclass 7, count 2 2006.218.08:13:18.14#ibcon#read 4, iclass 7, count 2 2006.218.08:13:18.14#ibcon#about to read 5, iclass 7, count 2 2006.218.08:13:18.14#ibcon#read 5, iclass 7, count 2 2006.218.08:13:18.14#ibcon#about to read 6, iclass 7, count 2 2006.218.08:13:18.14#ibcon#read 6, iclass 7, count 2 2006.218.08:13:18.14#ibcon#end of sib2, iclass 7, count 2 2006.218.08:13:18.14#ibcon#*mode == 0, iclass 7, count 2 2006.218.08:13:18.14#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.218.08:13:18.14#ibcon#[25=AT01-05\r\n] 2006.218.08:13:18.14#ibcon#*before write, iclass 7, count 2 2006.218.08:13:18.14#ibcon#enter sib2, iclass 7, count 2 2006.218.08:13:18.14#ibcon#flushed, iclass 7, count 2 2006.218.08:13:18.14#ibcon#about to write, iclass 7, count 2 2006.218.08:13:18.14#ibcon#wrote, iclass 7, count 2 2006.218.08:13:18.14#ibcon#about to read 3, iclass 7, count 2 2006.218.08:13:18.17#ibcon#read 3, iclass 7, count 2 2006.218.08:13:18.17#ibcon#about to read 4, iclass 7, count 2 2006.218.08:13:18.17#ibcon#read 4, iclass 7, count 2 2006.218.08:13:18.17#ibcon#about to read 5, iclass 7, count 2 2006.218.08:13:18.17#ibcon#read 5, iclass 7, count 2 2006.218.08:13:18.17#ibcon#about to read 6, iclass 7, count 2 2006.218.08:13:18.17#ibcon#read 6, iclass 7, count 2 2006.218.08:13:18.17#ibcon#end of sib2, iclass 7, count 2 2006.218.08:13:18.17#ibcon#*after write, iclass 7, count 2 2006.218.08:13:18.17#ibcon#*before return 0, iclass 7, count 2 2006.218.08:13:18.17#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.218.08:13:18.17#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.218.08:13:18.17#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.218.08:13:18.17#ibcon#ireg 7 cls_cnt 0 2006.218.08:13:18.17#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.218.08:13:18.29#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.218.08:13:18.29#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.218.08:13:18.29#ibcon#enter wrdev, iclass 7, count 0 2006.218.08:13:18.29#ibcon#first serial, iclass 7, count 0 2006.218.08:13:18.29#ibcon#enter sib2, iclass 7, count 0 2006.218.08:13:18.29#ibcon#flushed, iclass 7, count 0 2006.218.08:13:18.29#ibcon#about to write, iclass 7, count 0 2006.218.08:13:18.29#ibcon#wrote, iclass 7, count 0 2006.218.08:13:18.29#ibcon#about to read 3, iclass 7, count 0 2006.218.08:13:18.31#ibcon#read 3, iclass 7, count 0 2006.218.08:13:18.31#ibcon#about to read 4, iclass 7, count 0 2006.218.08:13:18.31#ibcon#read 4, iclass 7, count 0 2006.218.08:13:18.31#ibcon#about to read 5, iclass 7, count 0 2006.218.08:13:18.31#ibcon#read 5, iclass 7, count 0 2006.218.08:13:18.31#ibcon#about to read 6, iclass 7, count 0 2006.218.08:13:18.31#ibcon#read 6, iclass 7, count 0 2006.218.08:13:18.31#ibcon#end of sib2, iclass 7, count 0 2006.218.08:13:18.31#ibcon#*mode == 0, iclass 7, count 0 2006.218.08:13:18.31#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.218.08:13:18.31#ibcon#[25=USB\r\n] 2006.218.08:13:18.31#ibcon#*before write, iclass 7, count 0 2006.218.08:13:18.31#ibcon#enter sib2, iclass 7, count 0 2006.218.08:13:18.31#ibcon#flushed, iclass 7, count 0 2006.218.08:13:18.31#ibcon#about to write, iclass 7, count 0 2006.218.08:13:18.31#ibcon#wrote, iclass 7, count 0 2006.218.08:13:18.31#ibcon#about to read 3, iclass 7, count 0 2006.218.08:13:18.34#ibcon#read 3, iclass 7, count 0 2006.218.08:13:18.34#ibcon#about to read 4, iclass 7, count 0 2006.218.08:13:18.34#ibcon#read 4, iclass 7, count 0 2006.218.08:13:18.34#ibcon#about to read 5, iclass 7, count 0 2006.218.08:13:18.34#ibcon#read 5, iclass 7, count 0 2006.218.08:13:18.34#ibcon#about to read 6, iclass 7, count 0 2006.218.08:13:18.34#ibcon#read 6, iclass 7, count 0 2006.218.08:13:18.34#ibcon#end of sib2, iclass 7, count 0 2006.218.08:13:18.34#ibcon#*after write, iclass 7, count 0 2006.218.08:13:18.34#ibcon#*before return 0, iclass 7, count 0 2006.218.08:13:18.34#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.218.08:13:18.34#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.218.08:13:18.34#ibcon#about to clear, iclass 7 cls_cnt 0 2006.218.08:13:18.34#ibcon#cleared, iclass 7 cls_cnt 0 2006.218.08:13:18.34$vc4f8/valo=2,572.99 2006.218.08:13:18.34#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.218.08:13:18.34#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.218.08:13:18.34#ibcon#ireg 17 cls_cnt 0 2006.218.08:13:18.34#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.218.08:13:18.34#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.218.08:13:18.34#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.218.08:13:18.34#ibcon#enter wrdev, iclass 11, count 0 2006.218.08:13:18.34#ibcon#first serial, iclass 11, count 0 2006.218.08:13:18.34#ibcon#enter sib2, iclass 11, count 0 2006.218.08:13:18.34#ibcon#flushed, iclass 11, count 0 2006.218.08:13:18.34#ibcon#about to write, iclass 11, count 0 2006.218.08:13:18.34#ibcon#wrote, iclass 11, count 0 2006.218.08:13:18.34#ibcon#about to read 3, iclass 11, count 0 2006.218.08:13:18.36#ibcon#read 3, iclass 11, count 0 2006.218.08:13:18.36#ibcon#about to read 4, iclass 11, count 0 2006.218.08:13:18.36#ibcon#read 4, iclass 11, count 0 2006.218.08:13:18.36#ibcon#about to read 5, iclass 11, count 0 2006.218.08:13:18.36#ibcon#read 5, iclass 11, count 0 2006.218.08:13:18.36#ibcon#about to read 6, iclass 11, count 0 2006.218.08:13:18.36#ibcon#read 6, iclass 11, count 0 2006.218.08:13:18.36#ibcon#end of sib2, iclass 11, count 0 2006.218.08:13:18.36#ibcon#*mode == 0, iclass 11, count 0 2006.218.08:13:18.36#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.218.08:13:18.36#ibcon#[26=FRQ=02,572.99\r\n] 2006.218.08:13:18.36#ibcon#*before write, iclass 11, count 0 2006.218.08:13:18.36#ibcon#enter sib2, iclass 11, count 0 2006.218.08:13:18.36#ibcon#flushed, iclass 11, count 0 2006.218.08:13:18.36#ibcon#about to write, iclass 11, count 0 2006.218.08:13:18.36#ibcon#wrote, iclass 11, count 0 2006.218.08:13:18.36#ibcon#about to read 3, iclass 11, count 0 2006.218.08:13:18.40#ibcon#read 3, iclass 11, count 0 2006.218.08:13:18.40#ibcon#about to read 4, iclass 11, count 0 2006.218.08:13:18.40#ibcon#read 4, iclass 11, count 0 2006.218.08:13:18.40#ibcon#about to read 5, iclass 11, count 0 2006.218.08:13:18.40#ibcon#read 5, iclass 11, count 0 2006.218.08:13:18.40#ibcon#about to read 6, iclass 11, count 0 2006.218.08:13:18.40#ibcon#read 6, iclass 11, count 0 2006.218.08:13:18.40#ibcon#end of sib2, iclass 11, count 0 2006.218.08:13:18.40#ibcon#*after write, iclass 11, count 0 2006.218.08:13:18.40#ibcon#*before return 0, iclass 11, count 0 2006.218.08:13:18.40#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.218.08:13:18.40#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.218.08:13:18.40#ibcon#about to clear, iclass 11 cls_cnt 0 2006.218.08:13:18.40#ibcon#cleared, iclass 11 cls_cnt 0 2006.218.08:13:18.40$vc4f8/va=2,4 2006.218.08:13:18.40#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.218.08:13:18.40#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.218.08:13:18.40#ibcon#ireg 11 cls_cnt 2 2006.218.08:13:18.40#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.218.08:13:18.46#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.218.08:13:18.46#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.218.08:13:18.46#ibcon#enter wrdev, iclass 13, count 2 2006.218.08:13:18.46#ibcon#first serial, iclass 13, count 2 2006.218.08:13:18.46#ibcon#enter sib2, iclass 13, count 2 2006.218.08:13:18.46#ibcon#flushed, iclass 13, count 2 2006.218.08:13:18.46#ibcon#about to write, iclass 13, count 2 2006.218.08:13:18.46#ibcon#wrote, iclass 13, count 2 2006.218.08:13:18.46#ibcon#about to read 3, iclass 13, count 2 2006.218.08:13:18.48#ibcon#read 3, iclass 13, count 2 2006.218.08:13:18.48#ibcon#about to read 4, iclass 13, count 2 2006.218.08:13:18.48#ibcon#read 4, iclass 13, count 2 2006.218.08:13:18.48#ibcon#about to read 5, iclass 13, count 2 2006.218.08:13:18.48#ibcon#read 5, iclass 13, count 2 2006.218.08:13:18.48#ibcon#about to read 6, iclass 13, count 2 2006.218.08:13:18.48#ibcon#read 6, iclass 13, count 2 2006.218.08:13:18.48#ibcon#end of sib2, iclass 13, count 2 2006.218.08:13:18.48#ibcon#*mode == 0, iclass 13, count 2 2006.218.08:13:18.48#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.218.08:13:18.48#ibcon#[25=AT02-04\r\n] 2006.218.08:13:18.48#ibcon#*before write, iclass 13, count 2 2006.218.08:13:18.48#ibcon#enter sib2, iclass 13, count 2 2006.218.08:13:18.48#ibcon#flushed, iclass 13, count 2 2006.218.08:13:18.48#ibcon#about to write, iclass 13, count 2 2006.218.08:13:18.48#ibcon#wrote, iclass 13, count 2 2006.218.08:13:18.48#ibcon#about to read 3, iclass 13, count 2 2006.218.08:13:18.51#ibcon#read 3, iclass 13, count 2 2006.218.08:13:18.51#ibcon#about to read 4, iclass 13, count 2 2006.218.08:13:18.51#ibcon#read 4, iclass 13, count 2 2006.218.08:13:18.51#ibcon#about to read 5, iclass 13, count 2 2006.218.08:13:18.51#ibcon#read 5, iclass 13, count 2 2006.218.08:13:18.51#ibcon#about to read 6, iclass 13, count 2 2006.218.08:13:18.51#ibcon#read 6, iclass 13, count 2 2006.218.08:13:18.51#ibcon#end of sib2, iclass 13, count 2 2006.218.08:13:18.51#ibcon#*after write, iclass 13, count 2 2006.218.08:13:18.51#ibcon#*before return 0, iclass 13, count 2 2006.218.08:13:18.51#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.218.08:13:18.51#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.218.08:13:18.51#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.218.08:13:18.51#ibcon#ireg 7 cls_cnt 0 2006.218.08:13:18.51#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.218.08:13:18.63#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.218.08:13:18.63#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.218.08:13:18.63#ibcon#enter wrdev, iclass 13, count 0 2006.218.08:13:18.63#ibcon#first serial, iclass 13, count 0 2006.218.08:13:18.63#ibcon#enter sib2, iclass 13, count 0 2006.218.08:13:18.63#ibcon#flushed, iclass 13, count 0 2006.218.08:13:18.63#ibcon#about to write, iclass 13, count 0 2006.218.08:13:18.63#ibcon#wrote, iclass 13, count 0 2006.218.08:13:18.63#ibcon#about to read 3, iclass 13, count 0 2006.218.08:13:18.65#ibcon#read 3, iclass 13, count 0 2006.218.08:13:18.65#ibcon#about to read 4, iclass 13, count 0 2006.218.08:13:18.65#ibcon#read 4, iclass 13, count 0 2006.218.08:13:18.65#ibcon#about to read 5, iclass 13, count 0 2006.218.08:13:18.65#ibcon#read 5, iclass 13, count 0 2006.218.08:13:18.65#ibcon#about to read 6, iclass 13, count 0 2006.218.08:13:18.65#ibcon#read 6, iclass 13, count 0 2006.218.08:13:18.65#ibcon#end of sib2, iclass 13, count 0 2006.218.08:13:18.65#ibcon#*mode == 0, iclass 13, count 0 2006.218.08:13:18.65#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.218.08:13:18.65#ibcon#[25=USB\r\n] 2006.218.08:13:18.65#ibcon#*before write, iclass 13, count 0 2006.218.08:13:18.65#ibcon#enter sib2, iclass 13, count 0 2006.218.08:13:18.65#ibcon#flushed, iclass 13, count 0 2006.218.08:13:18.65#ibcon#about to write, iclass 13, count 0 2006.218.08:13:18.65#ibcon#wrote, iclass 13, count 0 2006.218.08:13:18.65#ibcon#about to read 3, iclass 13, count 0 2006.218.08:13:18.68#ibcon#read 3, iclass 13, count 0 2006.218.08:13:18.68#ibcon#about to read 4, iclass 13, count 0 2006.218.08:13:18.68#ibcon#read 4, iclass 13, count 0 2006.218.08:13:18.68#ibcon#about to read 5, iclass 13, count 0 2006.218.08:13:18.68#ibcon#read 5, iclass 13, count 0 2006.218.08:13:18.68#ibcon#about to read 6, iclass 13, count 0 2006.218.08:13:18.68#ibcon#read 6, iclass 13, count 0 2006.218.08:13:18.68#ibcon#end of sib2, iclass 13, count 0 2006.218.08:13:18.68#ibcon#*after write, iclass 13, count 0 2006.218.08:13:18.68#ibcon#*before return 0, iclass 13, count 0 2006.218.08:13:18.68#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.218.08:13:18.68#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.218.08:13:18.68#ibcon#about to clear, iclass 13 cls_cnt 0 2006.218.08:13:18.68#ibcon#cleared, iclass 13 cls_cnt 0 2006.218.08:13:18.68$vc4f8/valo=3,672.99 2006.218.08:13:18.68#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.218.08:13:18.68#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.218.08:13:18.68#ibcon#ireg 17 cls_cnt 0 2006.218.08:13:18.68#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.218.08:13:18.68#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.218.08:13:18.68#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.218.08:13:18.68#ibcon#enter wrdev, iclass 15, count 0 2006.218.08:13:18.68#ibcon#first serial, iclass 15, count 0 2006.218.08:13:18.68#ibcon#enter sib2, iclass 15, count 0 2006.218.08:13:18.68#ibcon#flushed, iclass 15, count 0 2006.218.08:13:18.68#ibcon#about to write, iclass 15, count 0 2006.218.08:13:18.68#ibcon#wrote, iclass 15, count 0 2006.218.08:13:18.68#ibcon#about to read 3, iclass 15, count 0 2006.218.08:13:18.70#ibcon#read 3, iclass 15, count 0 2006.218.08:13:18.70#ibcon#about to read 4, iclass 15, count 0 2006.218.08:13:18.70#ibcon#read 4, iclass 15, count 0 2006.218.08:13:18.70#ibcon#about to read 5, iclass 15, count 0 2006.218.08:13:18.70#ibcon#read 5, iclass 15, count 0 2006.218.08:13:18.70#ibcon#about to read 6, iclass 15, count 0 2006.218.08:13:18.70#ibcon#read 6, iclass 15, count 0 2006.218.08:13:18.70#ibcon#end of sib2, iclass 15, count 0 2006.218.08:13:18.70#ibcon#*mode == 0, iclass 15, count 0 2006.218.08:13:18.70#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.218.08:13:18.70#ibcon#[26=FRQ=03,672.99\r\n] 2006.218.08:13:18.70#ibcon#*before write, iclass 15, count 0 2006.218.08:13:18.70#ibcon#enter sib2, iclass 15, count 0 2006.218.08:13:18.70#ibcon#flushed, iclass 15, count 0 2006.218.08:13:18.70#ibcon#about to write, iclass 15, count 0 2006.218.08:13:18.70#ibcon#wrote, iclass 15, count 0 2006.218.08:13:18.70#ibcon#about to read 3, iclass 15, count 0 2006.218.08:13:18.74#ibcon#read 3, iclass 15, count 0 2006.218.08:13:18.74#ibcon#about to read 4, iclass 15, count 0 2006.218.08:13:18.74#ibcon#read 4, iclass 15, count 0 2006.218.08:13:18.74#ibcon#about to read 5, iclass 15, count 0 2006.218.08:13:18.74#ibcon#read 5, iclass 15, count 0 2006.218.08:13:18.74#ibcon#about to read 6, iclass 15, count 0 2006.218.08:13:18.74#ibcon#read 6, iclass 15, count 0 2006.218.08:13:18.74#ibcon#end of sib2, iclass 15, count 0 2006.218.08:13:18.74#ibcon#*after write, iclass 15, count 0 2006.218.08:13:18.74#ibcon#*before return 0, iclass 15, count 0 2006.218.08:13:18.74#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.218.08:13:18.74#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.218.08:13:18.74#ibcon#about to clear, iclass 15 cls_cnt 0 2006.218.08:13:18.74#ibcon#cleared, iclass 15 cls_cnt 0 2006.218.08:13:18.74$vc4f8/va=3,4 2006.218.08:13:18.74#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.218.08:13:18.74#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.218.08:13:18.74#ibcon#ireg 11 cls_cnt 2 2006.218.08:13:18.74#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.218.08:13:18.80#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.218.08:13:18.80#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.218.08:13:18.80#ibcon#enter wrdev, iclass 17, count 2 2006.218.08:13:18.80#ibcon#first serial, iclass 17, count 2 2006.218.08:13:18.80#ibcon#enter sib2, iclass 17, count 2 2006.218.08:13:18.80#ibcon#flushed, iclass 17, count 2 2006.218.08:13:18.80#ibcon#about to write, iclass 17, count 2 2006.218.08:13:18.80#ibcon#wrote, iclass 17, count 2 2006.218.08:13:18.80#ibcon#about to read 3, iclass 17, count 2 2006.218.08:13:18.82#ibcon#read 3, iclass 17, count 2 2006.218.08:13:18.82#ibcon#about to read 4, iclass 17, count 2 2006.218.08:13:18.82#ibcon#read 4, iclass 17, count 2 2006.218.08:13:18.82#ibcon#about to read 5, iclass 17, count 2 2006.218.08:13:18.82#ibcon#read 5, iclass 17, count 2 2006.218.08:13:18.82#ibcon#about to read 6, iclass 17, count 2 2006.218.08:13:18.82#ibcon#read 6, iclass 17, count 2 2006.218.08:13:18.82#ibcon#end of sib2, iclass 17, count 2 2006.218.08:13:18.82#ibcon#*mode == 0, iclass 17, count 2 2006.218.08:13:18.82#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.218.08:13:18.82#ibcon#[25=AT03-04\r\n] 2006.218.08:13:18.82#ibcon#*before write, iclass 17, count 2 2006.218.08:13:18.82#ibcon#enter sib2, iclass 17, count 2 2006.218.08:13:18.82#ibcon#flushed, iclass 17, count 2 2006.218.08:13:18.82#ibcon#about to write, iclass 17, count 2 2006.218.08:13:18.82#ibcon#wrote, iclass 17, count 2 2006.218.08:13:18.82#ibcon#about to read 3, iclass 17, count 2 2006.218.08:13:18.85#ibcon#read 3, iclass 17, count 2 2006.218.08:13:18.85#ibcon#about to read 4, iclass 17, count 2 2006.218.08:13:18.85#ibcon#read 4, iclass 17, count 2 2006.218.08:13:18.85#ibcon#about to read 5, iclass 17, count 2 2006.218.08:13:18.85#ibcon#read 5, iclass 17, count 2 2006.218.08:13:18.85#ibcon#about to read 6, iclass 17, count 2 2006.218.08:13:18.85#ibcon#read 6, iclass 17, count 2 2006.218.08:13:18.85#ibcon#end of sib2, iclass 17, count 2 2006.218.08:13:18.85#ibcon#*after write, iclass 17, count 2 2006.218.08:13:18.85#ibcon#*before return 0, iclass 17, count 2 2006.218.08:13:18.85#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.218.08:13:18.85#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.218.08:13:18.85#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.218.08:13:18.85#ibcon#ireg 7 cls_cnt 0 2006.218.08:13:18.85#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.218.08:13:18.97#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.218.08:13:18.97#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.218.08:13:18.97#ibcon#enter wrdev, iclass 17, count 0 2006.218.08:13:18.97#ibcon#first serial, iclass 17, count 0 2006.218.08:13:18.97#ibcon#enter sib2, iclass 17, count 0 2006.218.08:13:18.97#ibcon#flushed, iclass 17, count 0 2006.218.08:13:18.97#ibcon#about to write, iclass 17, count 0 2006.218.08:13:18.97#ibcon#wrote, iclass 17, count 0 2006.218.08:13:18.97#ibcon#about to read 3, iclass 17, count 0 2006.218.08:13:18.99#ibcon#read 3, iclass 17, count 0 2006.218.08:13:18.99#ibcon#about to read 4, iclass 17, count 0 2006.218.08:13:18.99#ibcon#read 4, iclass 17, count 0 2006.218.08:13:18.99#ibcon#about to read 5, iclass 17, count 0 2006.218.08:13:18.99#ibcon#read 5, iclass 17, count 0 2006.218.08:13:18.99#ibcon#about to read 6, iclass 17, count 0 2006.218.08:13:18.99#ibcon#read 6, iclass 17, count 0 2006.218.08:13:18.99#ibcon#end of sib2, iclass 17, count 0 2006.218.08:13:18.99#ibcon#*mode == 0, iclass 17, count 0 2006.218.08:13:18.99#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.218.08:13:18.99#ibcon#[25=USB\r\n] 2006.218.08:13:18.99#ibcon#*before write, iclass 17, count 0 2006.218.08:13:18.99#ibcon#enter sib2, iclass 17, count 0 2006.218.08:13:18.99#ibcon#flushed, iclass 17, count 0 2006.218.08:13:18.99#ibcon#about to write, iclass 17, count 0 2006.218.08:13:18.99#ibcon#wrote, iclass 17, count 0 2006.218.08:13:18.99#ibcon#about to read 3, iclass 17, count 0 2006.218.08:13:19.02#ibcon#read 3, iclass 17, count 0 2006.218.08:13:19.02#ibcon#about to read 4, iclass 17, count 0 2006.218.08:13:19.02#ibcon#read 4, iclass 17, count 0 2006.218.08:13:19.02#ibcon#about to read 5, iclass 17, count 0 2006.218.08:13:19.02#ibcon#read 5, iclass 17, count 0 2006.218.08:13:19.02#ibcon#about to read 6, iclass 17, count 0 2006.218.08:13:19.02#ibcon#read 6, iclass 17, count 0 2006.218.08:13:19.02#ibcon#end of sib2, iclass 17, count 0 2006.218.08:13:19.02#ibcon#*after write, iclass 17, count 0 2006.218.08:13:19.02#ibcon#*before return 0, iclass 17, count 0 2006.218.08:13:19.02#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.218.08:13:19.02#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.218.08:13:19.02#ibcon#about to clear, iclass 17 cls_cnt 0 2006.218.08:13:19.02#ibcon#cleared, iclass 17 cls_cnt 0 2006.218.08:13:19.02$vc4f8/valo=4,832.99 2006.218.08:13:19.02#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.218.08:13:19.02#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.218.08:13:19.02#ibcon#ireg 17 cls_cnt 0 2006.218.08:13:19.02#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.218.08:13:19.02#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.218.08:13:19.02#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.218.08:13:19.02#ibcon#enter wrdev, iclass 19, count 0 2006.218.08:13:19.02#ibcon#first serial, iclass 19, count 0 2006.218.08:13:19.02#ibcon#enter sib2, iclass 19, count 0 2006.218.08:13:19.02#ibcon#flushed, iclass 19, count 0 2006.218.08:13:19.02#ibcon#about to write, iclass 19, count 0 2006.218.08:13:19.02#ibcon#wrote, iclass 19, count 0 2006.218.08:13:19.02#ibcon#about to read 3, iclass 19, count 0 2006.218.08:13:19.04#ibcon#read 3, iclass 19, count 0 2006.218.08:13:19.04#ibcon#about to read 4, iclass 19, count 0 2006.218.08:13:19.04#ibcon#read 4, iclass 19, count 0 2006.218.08:13:19.04#ibcon#about to read 5, iclass 19, count 0 2006.218.08:13:19.04#ibcon#read 5, iclass 19, count 0 2006.218.08:13:19.04#ibcon#about to read 6, iclass 19, count 0 2006.218.08:13:19.04#ibcon#read 6, iclass 19, count 0 2006.218.08:13:19.04#ibcon#end of sib2, iclass 19, count 0 2006.218.08:13:19.04#ibcon#*mode == 0, iclass 19, count 0 2006.218.08:13:19.04#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.218.08:13:19.04#ibcon#[26=FRQ=04,832.99\r\n] 2006.218.08:13:19.04#ibcon#*before write, iclass 19, count 0 2006.218.08:13:19.04#ibcon#enter sib2, iclass 19, count 0 2006.218.08:13:19.04#ibcon#flushed, iclass 19, count 0 2006.218.08:13:19.04#ibcon#about to write, iclass 19, count 0 2006.218.08:13:19.04#ibcon#wrote, iclass 19, count 0 2006.218.08:13:19.04#ibcon#about to read 3, iclass 19, count 0 2006.218.08:13:19.08#ibcon#read 3, iclass 19, count 0 2006.218.08:13:19.08#ibcon#about to read 4, iclass 19, count 0 2006.218.08:13:19.08#ibcon#read 4, iclass 19, count 0 2006.218.08:13:19.08#ibcon#about to read 5, iclass 19, count 0 2006.218.08:13:19.08#ibcon#read 5, iclass 19, count 0 2006.218.08:13:19.08#ibcon#about to read 6, iclass 19, count 0 2006.218.08:13:19.08#ibcon#read 6, iclass 19, count 0 2006.218.08:13:19.08#ibcon#end of sib2, iclass 19, count 0 2006.218.08:13:19.08#ibcon#*after write, iclass 19, count 0 2006.218.08:13:19.08#ibcon#*before return 0, iclass 19, count 0 2006.218.08:13:19.08#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.218.08:13:19.08#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.218.08:13:19.08#ibcon#about to clear, iclass 19 cls_cnt 0 2006.218.08:13:19.08#ibcon#cleared, iclass 19 cls_cnt 0 2006.218.08:13:19.08$vc4f8/va=4,4 2006.218.08:13:19.08#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.218.08:13:19.08#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.218.08:13:19.08#ibcon#ireg 11 cls_cnt 2 2006.218.08:13:19.08#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.218.08:13:19.14#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.218.08:13:19.14#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.218.08:13:19.14#ibcon#enter wrdev, iclass 21, count 2 2006.218.08:13:19.14#ibcon#first serial, iclass 21, count 2 2006.218.08:13:19.14#ibcon#enter sib2, iclass 21, count 2 2006.218.08:13:19.14#ibcon#flushed, iclass 21, count 2 2006.218.08:13:19.14#ibcon#about to write, iclass 21, count 2 2006.218.08:13:19.14#ibcon#wrote, iclass 21, count 2 2006.218.08:13:19.14#ibcon#about to read 3, iclass 21, count 2 2006.218.08:13:19.16#ibcon#read 3, iclass 21, count 2 2006.218.08:13:19.16#ibcon#about to read 4, iclass 21, count 2 2006.218.08:13:19.16#ibcon#read 4, iclass 21, count 2 2006.218.08:13:19.16#ibcon#about to read 5, iclass 21, count 2 2006.218.08:13:19.16#ibcon#read 5, iclass 21, count 2 2006.218.08:13:19.16#ibcon#about to read 6, iclass 21, count 2 2006.218.08:13:19.16#ibcon#read 6, iclass 21, count 2 2006.218.08:13:19.16#ibcon#end of sib2, iclass 21, count 2 2006.218.08:13:19.16#ibcon#*mode == 0, iclass 21, count 2 2006.218.08:13:19.16#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.218.08:13:19.16#ibcon#[25=AT04-04\r\n] 2006.218.08:13:19.16#ibcon#*before write, iclass 21, count 2 2006.218.08:13:19.16#ibcon#enter sib2, iclass 21, count 2 2006.218.08:13:19.16#ibcon#flushed, iclass 21, count 2 2006.218.08:13:19.16#ibcon#about to write, iclass 21, count 2 2006.218.08:13:19.16#ibcon#wrote, iclass 21, count 2 2006.218.08:13:19.16#ibcon#about to read 3, iclass 21, count 2 2006.218.08:13:19.19#ibcon#read 3, iclass 21, count 2 2006.218.08:13:19.19#ibcon#about to read 4, iclass 21, count 2 2006.218.08:13:19.19#ibcon#read 4, iclass 21, count 2 2006.218.08:13:19.19#ibcon#about to read 5, iclass 21, count 2 2006.218.08:13:19.19#ibcon#read 5, iclass 21, count 2 2006.218.08:13:19.19#ibcon#about to read 6, iclass 21, count 2 2006.218.08:13:19.19#ibcon#read 6, iclass 21, count 2 2006.218.08:13:19.19#ibcon#end of sib2, iclass 21, count 2 2006.218.08:13:19.19#ibcon#*after write, iclass 21, count 2 2006.218.08:13:19.19#ibcon#*before return 0, iclass 21, count 2 2006.218.08:13:19.19#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.218.08:13:19.19#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.218.08:13:19.19#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.218.08:13:19.19#ibcon#ireg 7 cls_cnt 0 2006.218.08:13:19.19#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.218.08:13:19.31#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.218.08:13:19.31#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.218.08:13:19.31#ibcon#enter wrdev, iclass 21, count 0 2006.218.08:13:19.31#ibcon#first serial, iclass 21, count 0 2006.218.08:13:19.31#ibcon#enter sib2, iclass 21, count 0 2006.218.08:13:19.31#ibcon#flushed, iclass 21, count 0 2006.218.08:13:19.31#ibcon#about to write, iclass 21, count 0 2006.218.08:13:19.31#ibcon#wrote, iclass 21, count 0 2006.218.08:13:19.31#ibcon#about to read 3, iclass 21, count 0 2006.218.08:13:19.33#ibcon#read 3, iclass 21, count 0 2006.218.08:13:19.33#ibcon#about to read 4, iclass 21, count 0 2006.218.08:13:19.33#ibcon#read 4, iclass 21, count 0 2006.218.08:13:19.33#ibcon#about to read 5, iclass 21, count 0 2006.218.08:13:19.33#ibcon#read 5, iclass 21, count 0 2006.218.08:13:19.33#ibcon#about to read 6, iclass 21, count 0 2006.218.08:13:19.33#ibcon#read 6, iclass 21, count 0 2006.218.08:13:19.33#ibcon#end of sib2, iclass 21, count 0 2006.218.08:13:19.33#ibcon#*mode == 0, iclass 21, count 0 2006.218.08:13:19.33#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.218.08:13:19.33#ibcon#[25=USB\r\n] 2006.218.08:13:19.33#ibcon#*before write, iclass 21, count 0 2006.218.08:13:19.33#ibcon#enter sib2, iclass 21, count 0 2006.218.08:13:19.33#ibcon#flushed, iclass 21, count 0 2006.218.08:13:19.33#ibcon#about to write, iclass 21, count 0 2006.218.08:13:19.33#ibcon#wrote, iclass 21, count 0 2006.218.08:13:19.33#ibcon#about to read 3, iclass 21, count 0 2006.218.08:13:19.36#ibcon#read 3, iclass 21, count 0 2006.218.08:13:19.36#ibcon#about to read 4, iclass 21, count 0 2006.218.08:13:19.36#ibcon#read 4, iclass 21, count 0 2006.218.08:13:19.36#ibcon#about to read 5, iclass 21, count 0 2006.218.08:13:19.36#ibcon#read 5, iclass 21, count 0 2006.218.08:13:19.36#ibcon#about to read 6, iclass 21, count 0 2006.218.08:13:19.36#ibcon#read 6, iclass 21, count 0 2006.218.08:13:19.36#ibcon#end of sib2, iclass 21, count 0 2006.218.08:13:19.36#ibcon#*after write, iclass 21, count 0 2006.218.08:13:19.36#ibcon#*before return 0, iclass 21, count 0 2006.218.08:13:19.36#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.218.08:13:19.36#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.218.08:13:19.36#ibcon#about to clear, iclass 21 cls_cnt 0 2006.218.08:13:19.36#ibcon#cleared, iclass 21 cls_cnt 0 2006.218.08:13:19.36$vc4f8/valo=5,652.99 2006.218.08:13:19.36#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.218.08:13:19.36#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.218.08:13:19.36#ibcon#ireg 17 cls_cnt 0 2006.218.08:13:19.36#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.218.08:13:19.36#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.218.08:13:19.36#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.218.08:13:19.36#ibcon#enter wrdev, iclass 23, count 0 2006.218.08:13:19.36#ibcon#first serial, iclass 23, count 0 2006.218.08:13:19.36#ibcon#enter sib2, iclass 23, count 0 2006.218.08:13:19.36#ibcon#flushed, iclass 23, count 0 2006.218.08:13:19.36#ibcon#about to write, iclass 23, count 0 2006.218.08:13:19.36#ibcon#wrote, iclass 23, count 0 2006.218.08:13:19.36#ibcon#about to read 3, iclass 23, count 0 2006.218.08:13:19.38#ibcon#read 3, iclass 23, count 0 2006.218.08:13:19.38#ibcon#about to read 4, iclass 23, count 0 2006.218.08:13:19.38#ibcon#read 4, iclass 23, count 0 2006.218.08:13:19.38#ibcon#about to read 5, iclass 23, count 0 2006.218.08:13:19.38#ibcon#read 5, iclass 23, count 0 2006.218.08:13:19.38#ibcon#about to read 6, iclass 23, count 0 2006.218.08:13:19.38#ibcon#read 6, iclass 23, count 0 2006.218.08:13:19.38#ibcon#end of sib2, iclass 23, count 0 2006.218.08:13:19.38#ibcon#*mode == 0, iclass 23, count 0 2006.218.08:13:19.38#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.218.08:13:19.38#ibcon#[26=FRQ=05,652.99\r\n] 2006.218.08:13:19.38#ibcon#*before write, iclass 23, count 0 2006.218.08:13:19.38#ibcon#enter sib2, iclass 23, count 0 2006.218.08:13:19.38#ibcon#flushed, iclass 23, count 0 2006.218.08:13:19.38#ibcon#about to write, iclass 23, count 0 2006.218.08:13:19.38#ibcon#wrote, iclass 23, count 0 2006.218.08:13:19.38#ibcon#about to read 3, iclass 23, count 0 2006.218.08:13:19.42#ibcon#read 3, iclass 23, count 0 2006.218.08:13:19.42#ibcon#about to read 4, iclass 23, count 0 2006.218.08:13:19.42#ibcon#read 4, iclass 23, count 0 2006.218.08:13:19.42#ibcon#about to read 5, iclass 23, count 0 2006.218.08:13:19.42#ibcon#read 5, iclass 23, count 0 2006.218.08:13:19.42#ibcon#about to read 6, iclass 23, count 0 2006.218.08:13:19.42#ibcon#read 6, iclass 23, count 0 2006.218.08:13:19.42#ibcon#end of sib2, iclass 23, count 0 2006.218.08:13:19.42#ibcon#*after write, iclass 23, count 0 2006.218.08:13:19.42#ibcon#*before return 0, iclass 23, count 0 2006.218.08:13:19.42#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.218.08:13:19.42#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.218.08:13:19.42#ibcon#about to clear, iclass 23 cls_cnt 0 2006.218.08:13:19.42#ibcon#cleared, iclass 23 cls_cnt 0 2006.218.08:13:19.42$vc4f8/va=5,7 2006.218.08:13:19.42#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.218.08:13:19.42#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.218.08:13:19.42#ibcon#ireg 11 cls_cnt 2 2006.218.08:13:19.42#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.218.08:13:19.48#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.218.08:13:19.48#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.218.08:13:19.48#ibcon#enter wrdev, iclass 25, count 2 2006.218.08:13:19.48#ibcon#first serial, iclass 25, count 2 2006.218.08:13:19.48#ibcon#enter sib2, iclass 25, count 2 2006.218.08:13:19.48#ibcon#flushed, iclass 25, count 2 2006.218.08:13:19.48#ibcon#about to write, iclass 25, count 2 2006.218.08:13:19.48#ibcon#wrote, iclass 25, count 2 2006.218.08:13:19.48#ibcon#about to read 3, iclass 25, count 2 2006.218.08:13:19.50#ibcon#read 3, iclass 25, count 2 2006.218.08:13:19.50#ibcon#about to read 4, iclass 25, count 2 2006.218.08:13:19.50#ibcon#read 4, iclass 25, count 2 2006.218.08:13:19.50#ibcon#about to read 5, iclass 25, count 2 2006.218.08:13:19.50#ibcon#read 5, iclass 25, count 2 2006.218.08:13:19.50#ibcon#about to read 6, iclass 25, count 2 2006.218.08:13:19.50#ibcon#read 6, iclass 25, count 2 2006.218.08:13:19.50#ibcon#end of sib2, iclass 25, count 2 2006.218.08:13:19.50#ibcon#*mode == 0, iclass 25, count 2 2006.218.08:13:19.50#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.218.08:13:19.50#ibcon#[25=AT05-07\r\n] 2006.218.08:13:19.50#ibcon#*before write, iclass 25, count 2 2006.218.08:13:19.50#ibcon#enter sib2, iclass 25, count 2 2006.218.08:13:19.50#ibcon#flushed, iclass 25, count 2 2006.218.08:13:19.50#ibcon#about to write, iclass 25, count 2 2006.218.08:13:19.50#ibcon#wrote, iclass 25, count 2 2006.218.08:13:19.50#ibcon#about to read 3, iclass 25, count 2 2006.218.08:13:19.53#ibcon#read 3, iclass 25, count 2 2006.218.08:13:19.53#ibcon#about to read 4, iclass 25, count 2 2006.218.08:13:19.53#ibcon#read 4, iclass 25, count 2 2006.218.08:13:19.53#ibcon#about to read 5, iclass 25, count 2 2006.218.08:13:19.53#ibcon#read 5, iclass 25, count 2 2006.218.08:13:19.53#ibcon#about to read 6, iclass 25, count 2 2006.218.08:13:19.53#ibcon#read 6, iclass 25, count 2 2006.218.08:13:19.53#ibcon#end of sib2, iclass 25, count 2 2006.218.08:13:19.53#ibcon#*after write, iclass 25, count 2 2006.218.08:13:19.53#ibcon#*before return 0, iclass 25, count 2 2006.218.08:13:19.53#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.218.08:13:19.53#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.218.08:13:19.53#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.218.08:13:19.53#ibcon#ireg 7 cls_cnt 0 2006.218.08:13:19.53#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.218.08:13:19.65#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.218.08:13:19.65#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.218.08:13:19.65#ibcon#enter wrdev, iclass 25, count 0 2006.218.08:13:19.65#ibcon#first serial, iclass 25, count 0 2006.218.08:13:19.65#ibcon#enter sib2, iclass 25, count 0 2006.218.08:13:19.65#ibcon#flushed, iclass 25, count 0 2006.218.08:13:19.65#ibcon#about to write, iclass 25, count 0 2006.218.08:13:19.65#ibcon#wrote, iclass 25, count 0 2006.218.08:13:19.65#ibcon#about to read 3, iclass 25, count 0 2006.218.08:13:19.67#ibcon#read 3, iclass 25, count 0 2006.218.08:13:19.67#ibcon#about to read 4, iclass 25, count 0 2006.218.08:13:19.67#ibcon#read 4, iclass 25, count 0 2006.218.08:13:19.67#ibcon#about to read 5, iclass 25, count 0 2006.218.08:13:19.67#ibcon#read 5, iclass 25, count 0 2006.218.08:13:19.67#ibcon#about to read 6, iclass 25, count 0 2006.218.08:13:19.67#ibcon#read 6, iclass 25, count 0 2006.218.08:13:19.67#ibcon#end of sib2, iclass 25, count 0 2006.218.08:13:19.67#ibcon#*mode == 0, iclass 25, count 0 2006.218.08:13:19.67#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.218.08:13:19.67#ibcon#[25=USB\r\n] 2006.218.08:13:19.67#ibcon#*before write, iclass 25, count 0 2006.218.08:13:19.67#ibcon#enter sib2, iclass 25, count 0 2006.218.08:13:19.67#ibcon#flushed, iclass 25, count 0 2006.218.08:13:19.67#ibcon#about to write, iclass 25, count 0 2006.218.08:13:19.67#ibcon#wrote, iclass 25, count 0 2006.218.08:13:19.67#ibcon#about to read 3, iclass 25, count 0 2006.218.08:13:19.70#ibcon#read 3, iclass 25, count 0 2006.218.08:13:19.70#ibcon#about to read 4, iclass 25, count 0 2006.218.08:13:19.70#ibcon#read 4, iclass 25, count 0 2006.218.08:13:19.70#ibcon#about to read 5, iclass 25, count 0 2006.218.08:13:19.70#ibcon#read 5, iclass 25, count 0 2006.218.08:13:19.70#ibcon#about to read 6, iclass 25, count 0 2006.218.08:13:19.70#ibcon#read 6, iclass 25, count 0 2006.218.08:13:19.70#ibcon#end of sib2, iclass 25, count 0 2006.218.08:13:19.70#ibcon#*after write, iclass 25, count 0 2006.218.08:13:19.70#ibcon#*before return 0, iclass 25, count 0 2006.218.08:13:19.70#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.218.08:13:19.70#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.218.08:13:19.70#ibcon#about to clear, iclass 25 cls_cnt 0 2006.218.08:13:19.70#ibcon#cleared, iclass 25 cls_cnt 0 2006.218.08:13:19.70$vc4f8/valo=6,772.99 2006.218.08:13:19.70#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.218.08:13:19.70#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.218.08:13:19.70#ibcon#ireg 17 cls_cnt 0 2006.218.08:13:19.70#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.218.08:13:19.70#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.218.08:13:19.70#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.218.08:13:19.70#ibcon#enter wrdev, iclass 27, count 0 2006.218.08:13:19.70#ibcon#first serial, iclass 27, count 0 2006.218.08:13:19.70#ibcon#enter sib2, iclass 27, count 0 2006.218.08:13:19.70#ibcon#flushed, iclass 27, count 0 2006.218.08:13:19.70#ibcon#about to write, iclass 27, count 0 2006.218.08:13:19.70#ibcon#wrote, iclass 27, count 0 2006.218.08:13:19.70#ibcon#about to read 3, iclass 27, count 0 2006.218.08:13:19.72#ibcon#read 3, iclass 27, count 0 2006.218.08:13:19.72#ibcon#about to read 4, iclass 27, count 0 2006.218.08:13:19.72#ibcon#read 4, iclass 27, count 0 2006.218.08:13:19.72#ibcon#about to read 5, iclass 27, count 0 2006.218.08:13:19.72#ibcon#read 5, iclass 27, count 0 2006.218.08:13:19.72#ibcon#about to read 6, iclass 27, count 0 2006.218.08:13:19.72#ibcon#read 6, iclass 27, count 0 2006.218.08:13:19.72#ibcon#end of sib2, iclass 27, count 0 2006.218.08:13:19.72#ibcon#*mode == 0, iclass 27, count 0 2006.218.08:13:19.72#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.218.08:13:19.72#ibcon#[26=FRQ=06,772.99\r\n] 2006.218.08:13:19.72#ibcon#*before write, iclass 27, count 0 2006.218.08:13:19.72#ibcon#enter sib2, iclass 27, count 0 2006.218.08:13:19.72#ibcon#flushed, iclass 27, count 0 2006.218.08:13:19.72#ibcon#about to write, iclass 27, count 0 2006.218.08:13:19.72#ibcon#wrote, iclass 27, count 0 2006.218.08:13:19.72#ibcon#about to read 3, iclass 27, count 0 2006.218.08:13:19.76#ibcon#read 3, iclass 27, count 0 2006.218.08:13:19.76#ibcon#about to read 4, iclass 27, count 0 2006.218.08:13:19.76#ibcon#read 4, iclass 27, count 0 2006.218.08:13:19.76#ibcon#about to read 5, iclass 27, count 0 2006.218.08:13:19.76#ibcon#read 5, iclass 27, count 0 2006.218.08:13:19.76#ibcon#about to read 6, iclass 27, count 0 2006.218.08:13:19.76#ibcon#read 6, iclass 27, count 0 2006.218.08:13:19.76#ibcon#end of sib2, iclass 27, count 0 2006.218.08:13:19.76#ibcon#*after write, iclass 27, count 0 2006.218.08:13:19.76#ibcon#*before return 0, iclass 27, count 0 2006.218.08:13:19.76#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.218.08:13:19.76#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.218.08:13:19.76#ibcon#about to clear, iclass 27 cls_cnt 0 2006.218.08:13:19.76#ibcon#cleared, iclass 27 cls_cnt 0 2006.218.08:13:19.76$vc4f8/va=6,6 2006.218.08:13:19.76#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.218.08:13:19.76#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.218.08:13:19.76#ibcon#ireg 11 cls_cnt 2 2006.218.08:13:19.76#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.218.08:13:19.82#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.218.08:13:19.82#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.218.08:13:19.82#ibcon#enter wrdev, iclass 29, count 2 2006.218.08:13:19.82#ibcon#first serial, iclass 29, count 2 2006.218.08:13:19.82#ibcon#enter sib2, iclass 29, count 2 2006.218.08:13:19.82#ibcon#flushed, iclass 29, count 2 2006.218.08:13:19.82#ibcon#about to write, iclass 29, count 2 2006.218.08:13:19.82#ibcon#wrote, iclass 29, count 2 2006.218.08:13:19.82#ibcon#about to read 3, iclass 29, count 2 2006.218.08:13:19.84#ibcon#read 3, iclass 29, count 2 2006.218.08:13:19.84#ibcon#about to read 4, iclass 29, count 2 2006.218.08:13:19.84#ibcon#read 4, iclass 29, count 2 2006.218.08:13:19.84#ibcon#about to read 5, iclass 29, count 2 2006.218.08:13:19.84#ibcon#read 5, iclass 29, count 2 2006.218.08:13:19.84#ibcon#about to read 6, iclass 29, count 2 2006.218.08:13:19.84#ibcon#read 6, iclass 29, count 2 2006.218.08:13:19.84#ibcon#end of sib2, iclass 29, count 2 2006.218.08:13:19.84#ibcon#*mode == 0, iclass 29, count 2 2006.218.08:13:19.84#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.218.08:13:19.84#ibcon#[25=AT06-06\r\n] 2006.218.08:13:19.84#ibcon#*before write, iclass 29, count 2 2006.218.08:13:19.84#ibcon#enter sib2, iclass 29, count 2 2006.218.08:13:19.84#ibcon#flushed, iclass 29, count 2 2006.218.08:13:19.84#ibcon#about to write, iclass 29, count 2 2006.218.08:13:19.84#ibcon#wrote, iclass 29, count 2 2006.218.08:13:19.84#ibcon#about to read 3, iclass 29, count 2 2006.218.08:13:19.87#ibcon#read 3, iclass 29, count 2 2006.218.08:13:19.87#ibcon#about to read 4, iclass 29, count 2 2006.218.08:13:19.87#ibcon#read 4, iclass 29, count 2 2006.218.08:13:19.87#ibcon#about to read 5, iclass 29, count 2 2006.218.08:13:19.87#ibcon#read 5, iclass 29, count 2 2006.218.08:13:19.87#ibcon#about to read 6, iclass 29, count 2 2006.218.08:13:19.87#ibcon#read 6, iclass 29, count 2 2006.218.08:13:19.87#ibcon#end of sib2, iclass 29, count 2 2006.218.08:13:19.87#ibcon#*after write, iclass 29, count 2 2006.218.08:13:19.87#ibcon#*before return 0, iclass 29, count 2 2006.218.08:13:19.87#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.218.08:13:19.87#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.218.08:13:19.87#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.218.08:13:19.87#ibcon#ireg 7 cls_cnt 0 2006.218.08:13:19.87#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.218.08:13:19.99#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.218.08:13:19.99#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.218.08:13:19.99#ibcon#enter wrdev, iclass 29, count 0 2006.218.08:13:19.99#ibcon#first serial, iclass 29, count 0 2006.218.08:13:19.99#ibcon#enter sib2, iclass 29, count 0 2006.218.08:13:19.99#ibcon#flushed, iclass 29, count 0 2006.218.08:13:19.99#ibcon#about to write, iclass 29, count 0 2006.218.08:13:19.99#ibcon#wrote, iclass 29, count 0 2006.218.08:13:19.99#ibcon#about to read 3, iclass 29, count 0 2006.218.08:13:20.01#ibcon#read 3, iclass 29, count 0 2006.218.08:13:20.01#ibcon#about to read 4, iclass 29, count 0 2006.218.08:13:20.01#ibcon#read 4, iclass 29, count 0 2006.218.08:13:20.01#ibcon#about to read 5, iclass 29, count 0 2006.218.08:13:20.01#ibcon#read 5, iclass 29, count 0 2006.218.08:13:20.01#ibcon#about to read 6, iclass 29, count 0 2006.218.08:13:20.01#ibcon#read 6, iclass 29, count 0 2006.218.08:13:20.01#ibcon#end of sib2, iclass 29, count 0 2006.218.08:13:20.01#ibcon#*mode == 0, iclass 29, count 0 2006.218.08:13:20.01#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.218.08:13:20.01#ibcon#[25=USB\r\n] 2006.218.08:13:20.01#ibcon#*before write, iclass 29, count 0 2006.218.08:13:20.01#ibcon#enter sib2, iclass 29, count 0 2006.218.08:13:20.01#ibcon#flushed, iclass 29, count 0 2006.218.08:13:20.01#ibcon#about to write, iclass 29, count 0 2006.218.08:13:20.01#ibcon#wrote, iclass 29, count 0 2006.218.08:13:20.01#ibcon#about to read 3, iclass 29, count 0 2006.218.08:13:20.04#ibcon#read 3, iclass 29, count 0 2006.218.08:13:20.04#ibcon#about to read 4, iclass 29, count 0 2006.218.08:13:20.04#ibcon#read 4, iclass 29, count 0 2006.218.08:13:20.04#ibcon#about to read 5, iclass 29, count 0 2006.218.08:13:20.04#ibcon#read 5, iclass 29, count 0 2006.218.08:13:20.04#ibcon#about to read 6, iclass 29, count 0 2006.218.08:13:20.04#ibcon#read 6, iclass 29, count 0 2006.218.08:13:20.04#ibcon#end of sib2, iclass 29, count 0 2006.218.08:13:20.04#ibcon#*after write, iclass 29, count 0 2006.218.08:13:20.04#ibcon#*before return 0, iclass 29, count 0 2006.218.08:13:20.04#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.218.08:13:20.04#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.218.08:13:20.04#ibcon#about to clear, iclass 29 cls_cnt 0 2006.218.08:13:20.04#ibcon#cleared, iclass 29 cls_cnt 0 2006.218.08:13:20.04$vc4f8/valo=7,832.99 2006.218.08:13:20.04#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.218.08:13:20.04#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.218.08:13:20.04#ibcon#ireg 17 cls_cnt 0 2006.218.08:13:20.04#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.218.08:13:20.04#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.218.08:13:20.04#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.218.08:13:20.04#ibcon#enter wrdev, iclass 31, count 0 2006.218.08:13:20.04#ibcon#first serial, iclass 31, count 0 2006.218.08:13:20.04#ibcon#enter sib2, iclass 31, count 0 2006.218.08:13:20.04#ibcon#flushed, iclass 31, count 0 2006.218.08:13:20.04#ibcon#about to write, iclass 31, count 0 2006.218.08:13:20.04#ibcon#wrote, iclass 31, count 0 2006.218.08:13:20.04#ibcon#about to read 3, iclass 31, count 0 2006.218.08:13:20.06#ibcon#read 3, iclass 31, count 0 2006.218.08:13:20.06#ibcon#about to read 4, iclass 31, count 0 2006.218.08:13:20.06#ibcon#read 4, iclass 31, count 0 2006.218.08:13:20.06#ibcon#about to read 5, iclass 31, count 0 2006.218.08:13:20.06#ibcon#read 5, iclass 31, count 0 2006.218.08:13:20.06#ibcon#about to read 6, iclass 31, count 0 2006.218.08:13:20.06#ibcon#read 6, iclass 31, count 0 2006.218.08:13:20.06#ibcon#end of sib2, iclass 31, count 0 2006.218.08:13:20.06#ibcon#*mode == 0, iclass 31, count 0 2006.218.08:13:20.06#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.218.08:13:20.06#ibcon#[26=FRQ=07,832.99\r\n] 2006.218.08:13:20.06#ibcon#*before write, iclass 31, count 0 2006.218.08:13:20.06#ibcon#enter sib2, iclass 31, count 0 2006.218.08:13:20.06#ibcon#flushed, iclass 31, count 0 2006.218.08:13:20.06#ibcon#about to write, iclass 31, count 0 2006.218.08:13:20.06#ibcon#wrote, iclass 31, count 0 2006.218.08:13:20.06#ibcon#about to read 3, iclass 31, count 0 2006.218.08:13:20.10#ibcon#read 3, iclass 31, count 0 2006.218.08:13:20.10#ibcon#about to read 4, iclass 31, count 0 2006.218.08:13:20.10#ibcon#read 4, iclass 31, count 0 2006.218.08:13:20.10#ibcon#about to read 5, iclass 31, count 0 2006.218.08:13:20.10#ibcon#read 5, iclass 31, count 0 2006.218.08:13:20.10#ibcon#about to read 6, iclass 31, count 0 2006.218.08:13:20.10#ibcon#read 6, iclass 31, count 0 2006.218.08:13:20.10#ibcon#end of sib2, iclass 31, count 0 2006.218.08:13:20.10#ibcon#*after write, iclass 31, count 0 2006.218.08:13:20.10#ibcon#*before return 0, iclass 31, count 0 2006.218.08:13:20.10#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.218.08:13:20.10#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.218.08:13:20.10#ibcon#about to clear, iclass 31 cls_cnt 0 2006.218.08:13:20.10#ibcon#cleared, iclass 31 cls_cnt 0 2006.218.08:13:20.10$vc4f8/va=7,6 2006.218.08:13:20.10#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.218.08:13:20.10#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.218.08:13:20.10#ibcon#ireg 11 cls_cnt 2 2006.218.08:13:20.10#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.218.08:13:20.16#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.218.08:13:20.16#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.218.08:13:20.16#ibcon#enter wrdev, iclass 33, count 2 2006.218.08:13:20.16#ibcon#first serial, iclass 33, count 2 2006.218.08:13:20.16#ibcon#enter sib2, iclass 33, count 2 2006.218.08:13:20.16#ibcon#flushed, iclass 33, count 2 2006.218.08:13:20.16#ibcon#about to write, iclass 33, count 2 2006.218.08:13:20.16#ibcon#wrote, iclass 33, count 2 2006.218.08:13:20.16#ibcon#about to read 3, iclass 33, count 2 2006.218.08:13:20.18#ibcon#read 3, iclass 33, count 2 2006.218.08:13:20.18#ibcon#about to read 4, iclass 33, count 2 2006.218.08:13:20.18#ibcon#read 4, iclass 33, count 2 2006.218.08:13:20.18#ibcon#about to read 5, iclass 33, count 2 2006.218.08:13:20.18#ibcon#read 5, iclass 33, count 2 2006.218.08:13:20.18#ibcon#about to read 6, iclass 33, count 2 2006.218.08:13:20.18#ibcon#read 6, iclass 33, count 2 2006.218.08:13:20.18#ibcon#end of sib2, iclass 33, count 2 2006.218.08:13:20.18#ibcon#*mode == 0, iclass 33, count 2 2006.218.08:13:20.18#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.218.08:13:20.18#ibcon#[25=AT07-06\r\n] 2006.218.08:13:20.18#ibcon#*before write, iclass 33, count 2 2006.218.08:13:20.18#ibcon#enter sib2, iclass 33, count 2 2006.218.08:13:20.18#ibcon#flushed, iclass 33, count 2 2006.218.08:13:20.18#ibcon#about to write, iclass 33, count 2 2006.218.08:13:20.18#ibcon#wrote, iclass 33, count 2 2006.218.08:13:20.18#ibcon#about to read 3, iclass 33, count 2 2006.218.08:13:20.21#ibcon#read 3, iclass 33, count 2 2006.218.08:13:20.21#ibcon#about to read 4, iclass 33, count 2 2006.218.08:13:20.21#ibcon#read 4, iclass 33, count 2 2006.218.08:13:20.21#ibcon#about to read 5, iclass 33, count 2 2006.218.08:13:20.21#ibcon#read 5, iclass 33, count 2 2006.218.08:13:20.21#ibcon#about to read 6, iclass 33, count 2 2006.218.08:13:20.21#ibcon#read 6, iclass 33, count 2 2006.218.08:13:20.21#ibcon#end of sib2, iclass 33, count 2 2006.218.08:13:20.21#ibcon#*after write, iclass 33, count 2 2006.218.08:13:20.21#ibcon#*before return 0, iclass 33, count 2 2006.218.08:13:20.21#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.218.08:13:20.21#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.218.08:13:20.21#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.218.08:13:20.21#ibcon#ireg 7 cls_cnt 0 2006.218.08:13:20.21#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.218.08:13:20.33#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.218.08:13:20.33#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.218.08:13:20.33#ibcon#enter wrdev, iclass 33, count 0 2006.218.08:13:20.33#ibcon#first serial, iclass 33, count 0 2006.218.08:13:20.33#ibcon#enter sib2, iclass 33, count 0 2006.218.08:13:20.33#ibcon#flushed, iclass 33, count 0 2006.218.08:13:20.33#ibcon#about to write, iclass 33, count 0 2006.218.08:13:20.33#ibcon#wrote, iclass 33, count 0 2006.218.08:13:20.33#ibcon#about to read 3, iclass 33, count 0 2006.218.08:13:20.35#ibcon#read 3, iclass 33, count 0 2006.218.08:13:20.35#ibcon#about to read 4, iclass 33, count 0 2006.218.08:13:20.35#ibcon#read 4, iclass 33, count 0 2006.218.08:13:20.35#ibcon#about to read 5, iclass 33, count 0 2006.218.08:13:20.35#ibcon#read 5, iclass 33, count 0 2006.218.08:13:20.35#ibcon#about to read 6, iclass 33, count 0 2006.218.08:13:20.35#ibcon#read 6, iclass 33, count 0 2006.218.08:13:20.35#ibcon#end of sib2, iclass 33, count 0 2006.218.08:13:20.35#ibcon#*mode == 0, iclass 33, count 0 2006.218.08:13:20.35#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.218.08:13:20.35#ibcon#[25=USB\r\n] 2006.218.08:13:20.35#ibcon#*before write, iclass 33, count 0 2006.218.08:13:20.35#ibcon#enter sib2, iclass 33, count 0 2006.218.08:13:20.35#ibcon#flushed, iclass 33, count 0 2006.218.08:13:20.35#ibcon#about to write, iclass 33, count 0 2006.218.08:13:20.35#ibcon#wrote, iclass 33, count 0 2006.218.08:13:20.35#ibcon#about to read 3, iclass 33, count 0 2006.218.08:13:20.38#ibcon#read 3, iclass 33, count 0 2006.218.08:13:20.38#ibcon#about to read 4, iclass 33, count 0 2006.218.08:13:20.38#ibcon#read 4, iclass 33, count 0 2006.218.08:13:20.38#ibcon#about to read 5, iclass 33, count 0 2006.218.08:13:20.38#ibcon#read 5, iclass 33, count 0 2006.218.08:13:20.38#ibcon#about to read 6, iclass 33, count 0 2006.218.08:13:20.38#ibcon#read 6, iclass 33, count 0 2006.218.08:13:20.38#ibcon#end of sib2, iclass 33, count 0 2006.218.08:13:20.38#ibcon#*after write, iclass 33, count 0 2006.218.08:13:20.38#ibcon#*before return 0, iclass 33, count 0 2006.218.08:13:20.38#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.218.08:13:20.38#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.218.08:13:20.38#ibcon#about to clear, iclass 33 cls_cnt 0 2006.218.08:13:20.38#ibcon#cleared, iclass 33 cls_cnt 0 2006.218.08:13:20.38$vc4f8/valo=8,852.99 2006.218.08:13:20.38#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.218.08:13:20.38#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.218.08:13:20.38#ibcon#ireg 17 cls_cnt 0 2006.218.08:13:20.38#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.218.08:13:20.38#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.218.08:13:20.38#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.218.08:13:20.38#ibcon#enter wrdev, iclass 35, count 0 2006.218.08:13:20.38#ibcon#first serial, iclass 35, count 0 2006.218.08:13:20.38#ibcon#enter sib2, iclass 35, count 0 2006.218.08:13:20.38#ibcon#flushed, iclass 35, count 0 2006.218.08:13:20.38#ibcon#about to write, iclass 35, count 0 2006.218.08:13:20.38#ibcon#wrote, iclass 35, count 0 2006.218.08:13:20.38#ibcon#about to read 3, iclass 35, count 0 2006.218.08:13:20.40#ibcon#read 3, iclass 35, count 0 2006.218.08:13:20.40#ibcon#about to read 4, iclass 35, count 0 2006.218.08:13:20.40#ibcon#read 4, iclass 35, count 0 2006.218.08:13:20.40#ibcon#about to read 5, iclass 35, count 0 2006.218.08:13:20.40#ibcon#read 5, iclass 35, count 0 2006.218.08:13:20.40#ibcon#about to read 6, iclass 35, count 0 2006.218.08:13:20.40#ibcon#read 6, iclass 35, count 0 2006.218.08:13:20.40#ibcon#end of sib2, iclass 35, count 0 2006.218.08:13:20.40#ibcon#*mode == 0, iclass 35, count 0 2006.218.08:13:20.40#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.218.08:13:20.40#ibcon#[26=FRQ=08,852.99\r\n] 2006.218.08:13:20.40#ibcon#*before write, iclass 35, count 0 2006.218.08:13:20.40#ibcon#enter sib2, iclass 35, count 0 2006.218.08:13:20.40#ibcon#flushed, iclass 35, count 0 2006.218.08:13:20.40#ibcon#about to write, iclass 35, count 0 2006.218.08:13:20.40#ibcon#wrote, iclass 35, count 0 2006.218.08:13:20.40#ibcon#about to read 3, iclass 35, count 0 2006.218.08:13:20.44#ibcon#read 3, iclass 35, count 0 2006.218.08:13:20.44#ibcon#about to read 4, iclass 35, count 0 2006.218.08:13:20.44#ibcon#read 4, iclass 35, count 0 2006.218.08:13:20.44#ibcon#about to read 5, iclass 35, count 0 2006.218.08:13:20.44#ibcon#read 5, iclass 35, count 0 2006.218.08:13:20.44#ibcon#about to read 6, iclass 35, count 0 2006.218.08:13:20.44#ibcon#read 6, iclass 35, count 0 2006.218.08:13:20.44#ibcon#end of sib2, iclass 35, count 0 2006.218.08:13:20.44#ibcon#*after write, iclass 35, count 0 2006.218.08:13:20.44#ibcon#*before return 0, iclass 35, count 0 2006.218.08:13:20.44#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.218.08:13:20.44#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.218.08:13:20.44#ibcon#about to clear, iclass 35 cls_cnt 0 2006.218.08:13:20.44#ibcon#cleared, iclass 35 cls_cnt 0 2006.218.08:13:20.44$vc4f8/va=8,7 2006.218.08:13:20.44#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.218.08:13:20.44#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.218.08:13:20.44#ibcon#ireg 11 cls_cnt 2 2006.218.08:13:20.44#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.218.08:13:20.50#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.218.08:13:20.50#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.218.08:13:20.50#ibcon#enter wrdev, iclass 37, count 2 2006.218.08:13:20.50#ibcon#first serial, iclass 37, count 2 2006.218.08:13:20.50#ibcon#enter sib2, iclass 37, count 2 2006.218.08:13:20.50#ibcon#flushed, iclass 37, count 2 2006.218.08:13:20.50#ibcon#about to write, iclass 37, count 2 2006.218.08:13:20.50#ibcon#wrote, iclass 37, count 2 2006.218.08:13:20.50#ibcon#about to read 3, iclass 37, count 2 2006.218.08:13:20.52#ibcon#read 3, iclass 37, count 2 2006.218.08:13:20.52#ibcon#about to read 4, iclass 37, count 2 2006.218.08:13:20.52#ibcon#read 4, iclass 37, count 2 2006.218.08:13:20.52#ibcon#about to read 5, iclass 37, count 2 2006.218.08:13:20.52#ibcon#read 5, iclass 37, count 2 2006.218.08:13:20.52#ibcon#about to read 6, iclass 37, count 2 2006.218.08:13:20.52#ibcon#read 6, iclass 37, count 2 2006.218.08:13:20.52#ibcon#end of sib2, iclass 37, count 2 2006.218.08:13:20.52#ibcon#*mode == 0, iclass 37, count 2 2006.218.08:13:20.52#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.218.08:13:20.52#ibcon#[25=AT08-07\r\n] 2006.218.08:13:20.52#ibcon#*before write, iclass 37, count 2 2006.218.08:13:20.52#ibcon#enter sib2, iclass 37, count 2 2006.218.08:13:20.52#ibcon#flushed, iclass 37, count 2 2006.218.08:13:20.52#ibcon#about to write, iclass 37, count 2 2006.218.08:13:20.52#ibcon#wrote, iclass 37, count 2 2006.218.08:13:20.52#ibcon#about to read 3, iclass 37, count 2 2006.218.08:13:20.55#ibcon#read 3, iclass 37, count 2 2006.218.08:13:20.55#ibcon#about to read 4, iclass 37, count 2 2006.218.08:13:20.55#ibcon#read 4, iclass 37, count 2 2006.218.08:13:20.55#ibcon#about to read 5, iclass 37, count 2 2006.218.08:13:20.55#ibcon#read 5, iclass 37, count 2 2006.218.08:13:20.55#ibcon#about to read 6, iclass 37, count 2 2006.218.08:13:20.55#ibcon#read 6, iclass 37, count 2 2006.218.08:13:20.55#ibcon#end of sib2, iclass 37, count 2 2006.218.08:13:20.55#ibcon#*after write, iclass 37, count 2 2006.218.08:13:20.55#ibcon#*before return 0, iclass 37, count 2 2006.218.08:13:20.55#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.218.08:13:20.55#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.218.08:13:20.55#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.218.08:13:20.55#ibcon#ireg 7 cls_cnt 0 2006.218.08:13:20.55#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.218.08:13:20.67#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.218.08:13:20.67#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.218.08:13:20.67#ibcon#enter wrdev, iclass 37, count 0 2006.218.08:13:20.67#ibcon#first serial, iclass 37, count 0 2006.218.08:13:20.67#ibcon#enter sib2, iclass 37, count 0 2006.218.08:13:20.67#ibcon#flushed, iclass 37, count 0 2006.218.08:13:20.67#ibcon#about to write, iclass 37, count 0 2006.218.08:13:20.67#ibcon#wrote, iclass 37, count 0 2006.218.08:13:20.67#ibcon#about to read 3, iclass 37, count 0 2006.218.08:13:20.69#ibcon#read 3, iclass 37, count 0 2006.218.08:13:20.69#ibcon#about to read 4, iclass 37, count 0 2006.218.08:13:20.69#ibcon#read 4, iclass 37, count 0 2006.218.08:13:20.69#ibcon#about to read 5, iclass 37, count 0 2006.218.08:13:20.69#ibcon#read 5, iclass 37, count 0 2006.218.08:13:20.69#ibcon#about to read 6, iclass 37, count 0 2006.218.08:13:20.69#ibcon#read 6, iclass 37, count 0 2006.218.08:13:20.69#ibcon#end of sib2, iclass 37, count 0 2006.218.08:13:20.69#ibcon#*mode == 0, iclass 37, count 0 2006.218.08:13:20.69#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.218.08:13:20.69#ibcon#[25=USB\r\n] 2006.218.08:13:20.69#ibcon#*before write, iclass 37, count 0 2006.218.08:13:20.69#ibcon#enter sib2, iclass 37, count 0 2006.218.08:13:20.69#ibcon#flushed, iclass 37, count 0 2006.218.08:13:20.69#ibcon#about to write, iclass 37, count 0 2006.218.08:13:20.69#ibcon#wrote, iclass 37, count 0 2006.218.08:13:20.69#ibcon#about to read 3, iclass 37, count 0 2006.218.08:13:20.72#ibcon#read 3, iclass 37, count 0 2006.218.08:13:20.72#ibcon#about to read 4, iclass 37, count 0 2006.218.08:13:20.72#ibcon#read 4, iclass 37, count 0 2006.218.08:13:20.72#ibcon#about to read 5, iclass 37, count 0 2006.218.08:13:20.72#ibcon#read 5, iclass 37, count 0 2006.218.08:13:20.72#ibcon#about to read 6, iclass 37, count 0 2006.218.08:13:20.72#ibcon#read 6, iclass 37, count 0 2006.218.08:13:20.72#ibcon#end of sib2, iclass 37, count 0 2006.218.08:13:20.72#ibcon#*after write, iclass 37, count 0 2006.218.08:13:20.72#ibcon#*before return 0, iclass 37, count 0 2006.218.08:13:20.72#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.218.08:13:20.72#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.218.08:13:20.72#ibcon#about to clear, iclass 37 cls_cnt 0 2006.218.08:13:20.72#ibcon#cleared, iclass 37 cls_cnt 0 2006.218.08:13:20.72$vc4f8/vblo=1,632.99 2006.218.08:13:20.72#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.218.08:13:20.72#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.218.08:13:20.72#ibcon#ireg 17 cls_cnt 0 2006.218.08:13:20.72#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.218.08:13:20.72#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.218.08:13:20.72#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.218.08:13:20.72#ibcon#enter wrdev, iclass 39, count 0 2006.218.08:13:20.72#ibcon#first serial, iclass 39, count 0 2006.218.08:13:20.72#ibcon#enter sib2, iclass 39, count 0 2006.218.08:13:20.72#ibcon#flushed, iclass 39, count 0 2006.218.08:13:20.72#ibcon#about to write, iclass 39, count 0 2006.218.08:13:20.72#ibcon#wrote, iclass 39, count 0 2006.218.08:13:20.72#ibcon#about to read 3, iclass 39, count 0 2006.218.08:13:20.74#ibcon#read 3, iclass 39, count 0 2006.218.08:13:20.74#ibcon#about to read 4, iclass 39, count 0 2006.218.08:13:20.74#ibcon#read 4, iclass 39, count 0 2006.218.08:13:20.74#ibcon#about to read 5, iclass 39, count 0 2006.218.08:13:20.74#ibcon#read 5, iclass 39, count 0 2006.218.08:13:20.74#ibcon#about to read 6, iclass 39, count 0 2006.218.08:13:20.74#ibcon#read 6, iclass 39, count 0 2006.218.08:13:20.74#ibcon#end of sib2, iclass 39, count 0 2006.218.08:13:20.74#ibcon#*mode == 0, iclass 39, count 0 2006.218.08:13:20.74#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.218.08:13:20.74#ibcon#[28=FRQ=01,632.99\r\n] 2006.218.08:13:20.74#ibcon#*before write, iclass 39, count 0 2006.218.08:13:20.74#ibcon#enter sib2, iclass 39, count 0 2006.218.08:13:20.74#ibcon#flushed, iclass 39, count 0 2006.218.08:13:20.74#ibcon#about to write, iclass 39, count 0 2006.218.08:13:20.74#ibcon#wrote, iclass 39, count 0 2006.218.08:13:20.74#ibcon#about to read 3, iclass 39, count 0 2006.218.08:13:20.78#ibcon#read 3, iclass 39, count 0 2006.218.08:13:20.78#ibcon#about to read 4, iclass 39, count 0 2006.218.08:13:20.78#ibcon#read 4, iclass 39, count 0 2006.218.08:13:20.78#ibcon#about to read 5, iclass 39, count 0 2006.218.08:13:20.78#ibcon#read 5, iclass 39, count 0 2006.218.08:13:20.78#ibcon#about to read 6, iclass 39, count 0 2006.218.08:13:20.78#ibcon#read 6, iclass 39, count 0 2006.218.08:13:20.78#ibcon#end of sib2, iclass 39, count 0 2006.218.08:13:20.78#ibcon#*after write, iclass 39, count 0 2006.218.08:13:20.78#ibcon#*before return 0, iclass 39, count 0 2006.218.08:13:20.78#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.218.08:13:20.78#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.218.08:13:20.78#ibcon#about to clear, iclass 39 cls_cnt 0 2006.218.08:13:20.78#ibcon#cleared, iclass 39 cls_cnt 0 2006.218.08:13:20.78$vc4f8/vb=1,4 2006.218.08:13:20.78#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.218.08:13:20.78#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.218.08:13:20.78#ibcon#ireg 11 cls_cnt 2 2006.218.08:13:20.78#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.218.08:13:20.78#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.218.08:13:20.78#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.218.08:13:20.78#ibcon#enter wrdev, iclass 3, count 2 2006.218.08:13:20.78#ibcon#first serial, iclass 3, count 2 2006.218.08:13:20.78#ibcon#enter sib2, iclass 3, count 2 2006.218.08:13:20.78#ibcon#flushed, iclass 3, count 2 2006.218.08:13:20.78#ibcon#about to write, iclass 3, count 2 2006.218.08:13:20.78#ibcon#wrote, iclass 3, count 2 2006.218.08:13:20.78#ibcon#about to read 3, iclass 3, count 2 2006.218.08:13:20.80#ibcon#read 3, iclass 3, count 2 2006.218.08:13:20.80#ibcon#about to read 4, iclass 3, count 2 2006.218.08:13:20.80#ibcon#read 4, iclass 3, count 2 2006.218.08:13:20.80#ibcon#about to read 5, iclass 3, count 2 2006.218.08:13:20.80#ibcon#read 5, iclass 3, count 2 2006.218.08:13:20.80#ibcon#about to read 6, iclass 3, count 2 2006.218.08:13:20.80#ibcon#read 6, iclass 3, count 2 2006.218.08:13:20.80#ibcon#end of sib2, iclass 3, count 2 2006.218.08:13:20.80#ibcon#*mode == 0, iclass 3, count 2 2006.218.08:13:20.80#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.218.08:13:20.80#ibcon#[27=AT01-04\r\n] 2006.218.08:13:20.80#ibcon#*before write, iclass 3, count 2 2006.218.08:13:20.80#ibcon#enter sib2, iclass 3, count 2 2006.218.08:13:20.80#ibcon#flushed, iclass 3, count 2 2006.218.08:13:20.80#ibcon#about to write, iclass 3, count 2 2006.218.08:13:20.80#ibcon#wrote, iclass 3, count 2 2006.218.08:13:20.80#ibcon#about to read 3, iclass 3, count 2 2006.218.08:13:20.83#ibcon#read 3, iclass 3, count 2 2006.218.08:13:20.83#ibcon#about to read 4, iclass 3, count 2 2006.218.08:13:20.83#ibcon#read 4, iclass 3, count 2 2006.218.08:13:20.83#ibcon#about to read 5, iclass 3, count 2 2006.218.08:13:20.83#ibcon#read 5, iclass 3, count 2 2006.218.08:13:20.83#ibcon#about to read 6, iclass 3, count 2 2006.218.08:13:20.83#ibcon#read 6, iclass 3, count 2 2006.218.08:13:20.83#ibcon#end of sib2, iclass 3, count 2 2006.218.08:13:20.83#ibcon#*after write, iclass 3, count 2 2006.218.08:13:20.83#ibcon#*before return 0, iclass 3, count 2 2006.218.08:13:20.83#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.218.08:13:20.83#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.218.08:13:20.83#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.218.08:13:20.83#ibcon#ireg 7 cls_cnt 0 2006.218.08:13:20.83#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.218.08:13:20.95#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.218.08:13:20.95#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.218.08:13:20.95#ibcon#enter wrdev, iclass 3, count 0 2006.218.08:13:20.95#ibcon#first serial, iclass 3, count 0 2006.218.08:13:20.95#ibcon#enter sib2, iclass 3, count 0 2006.218.08:13:20.95#ibcon#flushed, iclass 3, count 0 2006.218.08:13:20.95#ibcon#about to write, iclass 3, count 0 2006.218.08:13:20.95#ibcon#wrote, iclass 3, count 0 2006.218.08:13:20.95#ibcon#about to read 3, iclass 3, count 0 2006.218.08:13:20.97#ibcon#read 3, iclass 3, count 0 2006.218.08:13:20.97#ibcon#about to read 4, iclass 3, count 0 2006.218.08:13:20.97#ibcon#read 4, iclass 3, count 0 2006.218.08:13:20.97#ibcon#about to read 5, iclass 3, count 0 2006.218.08:13:20.97#ibcon#read 5, iclass 3, count 0 2006.218.08:13:20.97#ibcon#about to read 6, iclass 3, count 0 2006.218.08:13:20.97#ibcon#read 6, iclass 3, count 0 2006.218.08:13:20.97#ibcon#end of sib2, iclass 3, count 0 2006.218.08:13:20.97#ibcon#*mode == 0, iclass 3, count 0 2006.218.08:13:20.97#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.218.08:13:20.97#ibcon#[27=USB\r\n] 2006.218.08:13:20.97#ibcon#*before write, iclass 3, count 0 2006.218.08:13:20.97#ibcon#enter sib2, iclass 3, count 0 2006.218.08:13:20.97#ibcon#flushed, iclass 3, count 0 2006.218.08:13:20.97#ibcon#about to write, iclass 3, count 0 2006.218.08:13:20.97#ibcon#wrote, iclass 3, count 0 2006.218.08:13:20.97#ibcon#about to read 3, iclass 3, count 0 2006.218.08:13:21.00#ibcon#read 3, iclass 3, count 0 2006.218.08:13:21.00#ibcon#about to read 4, iclass 3, count 0 2006.218.08:13:21.00#ibcon#read 4, iclass 3, count 0 2006.218.08:13:21.00#ibcon#about to read 5, iclass 3, count 0 2006.218.08:13:21.00#ibcon#read 5, iclass 3, count 0 2006.218.08:13:21.00#ibcon#about to read 6, iclass 3, count 0 2006.218.08:13:21.00#ibcon#read 6, iclass 3, count 0 2006.218.08:13:21.00#ibcon#end of sib2, iclass 3, count 0 2006.218.08:13:21.00#ibcon#*after write, iclass 3, count 0 2006.218.08:13:21.00#ibcon#*before return 0, iclass 3, count 0 2006.218.08:13:21.00#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.218.08:13:21.00#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.218.08:13:21.00#ibcon#about to clear, iclass 3 cls_cnt 0 2006.218.08:13:21.00#ibcon#cleared, iclass 3 cls_cnt 0 2006.218.08:13:21.00$vc4f8/vblo=2,640.99 2006.218.08:13:21.00#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.218.08:13:21.00#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.218.08:13:21.00#ibcon#ireg 17 cls_cnt 0 2006.218.08:13:21.00#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.218.08:13:21.00#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.218.08:13:21.00#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.218.08:13:21.00#ibcon#enter wrdev, iclass 5, count 0 2006.218.08:13:21.00#ibcon#first serial, iclass 5, count 0 2006.218.08:13:21.00#ibcon#enter sib2, iclass 5, count 0 2006.218.08:13:21.00#ibcon#flushed, iclass 5, count 0 2006.218.08:13:21.00#ibcon#about to write, iclass 5, count 0 2006.218.08:13:21.00#ibcon#wrote, iclass 5, count 0 2006.218.08:13:21.00#ibcon#about to read 3, iclass 5, count 0 2006.218.08:13:21.02#ibcon#read 3, iclass 5, count 0 2006.218.08:13:21.02#ibcon#about to read 4, iclass 5, count 0 2006.218.08:13:21.02#ibcon#read 4, iclass 5, count 0 2006.218.08:13:21.02#ibcon#about to read 5, iclass 5, count 0 2006.218.08:13:21.02#ibcon#read 5, iclass 5, count 0 2006.218.08:13:21.02#ibcon#about to read 6, iclass 5, count 0 2006.218.08:13:21.02#ibcon#read 6, iclass 5, count 0 2006.218.08:13:21.02#ibcon#end of sib2, iclass 5, count 0 2006.218.08:13:21.02#ibcon#*mode == 0, iclass 5, count 0 2006.218.08:13:21.02#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.218.08:13:21.02#ibcon#[28=FRQ=02,640.99\r\n] 2006.218.08:13:21.02#ibcon#*before write, iclass 5, count 0 2006.218.08:13:21.02#ibcon#enter sib2, iclass 5, count 0 2006.218.08:13:21.02#ibcon#flushed, iclass 5, count 0 2006.218.08:13:21.02#ibcon#about to write, iclass 5, count 0 2006.218.08:13:21.02#ibcon#wrote, iclass 5, count 0 2006.218.08:13:21.02#ibcon#about to read 3, iclass 5, count 0 2006.218.08:13:21.06#ibcon#read 3, iclass 5, count 0 2006.218.08:13:21.06#ibcon#about to read 4, iclass 5, count 0 2006.218.08:13:21.06#ibcon#read 4, iclass 5, count 0 2006.218.08:13:21.06#ibcon#about to read 5, iclass 5, count 0 2006.218.08:13:21.06#ibcon#read 5, iclass 5, count 0 2006.218.08:13:21.06#ibcon#about to read 6, iclass 5, count 0 2006.218.08:13:21.06#ibcon#read 6, iclass 5, count 0 2006.218.08:13:21.06#ibcon#end of sib2, iclass 5, count 0 2006.218.08:13:21.06#ibcon#*after write, iclass 5, count 0 2006.218.08:13:21.06#ibcon#*before return 0, iclass 5, count 0 2006.218.08:13:21.06#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.218.08:13:21.06#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.218.08:13:21.06#ibcon#about to clear, iclass 5 cls_cnt 0 2006.218.08:13:21.06#ibcon#cleared, iclass 5 cls_cnt 0 2006.218.08:13:21.06$vc4f8/vb=2,4 2006.218.08:13:21.06#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.218.08:13:21.06#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.218.08:13:21.06#ibcon#ireg 11 cls_cnt 2 2006.218.08:13:21.06#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.218.08:13:21.12#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.218.08:13:21.12#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.218.08:13:21.12#ibcon#enter wrdev, iclass 7, count 2 2006.218.08:13:21.12#ibcon#first serial, iclass 7, count 2 2006.218.08:13:21.12#ibcon#enter sib2, iclass 7, count 2 2006.218.08:13:21.12#ibcon#flushed, iclass 7, count 2 2006.218.08:13:21.12#ibcon#about to write, iclass 7, count 2 2006.218.08:13:21.12#ibcon#wrote, iclass 7, count 2 2006.218.08:13:21.12#ibcon#about to read 3, iclass 7, count 2 2006.218.08:13:21.14#ibcon#read 3, iclass 7, count 2 2006.218.08:13:21.14#ibcon#about to read 4, iclass 7, count 2 2006.218.08:13:21.14#ibcon#read 4, iclass 7, count 2 2006.218.08:13:21.14#ibcon#about to read 5, iclass 7, count 2 2006.218.08:13:21.14#ibcon#read 5, iclass 7, count 2 2006.218.08:13:21.14#ibcon#about to read 6, iclass 7, count 2 2006.218.08:13:21.14#ibcon#read 6, iclass 7, count 2 2006.218.08:13:21.14#ibcon#end of sib2, iclass 7, count 2 2006.218.08:13:21.14#ibcon#*mode == 0, iclass 7, count 2 2006.218.08:13:21.14#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.218.08:13:21.14#ibcon#[27=AT02-04\r\n] 2006.218.08:13:21.14#ibcon#*before write, iclass 7, count 2 2006.218.08:13:21.14#ibcon#enter sib2, iclass 7, count 2 2006.218.08:13:21.14#ibcon#flushed, iclass 7, count 2 2006.218.08:13:21.14#ibcon#about to write, iclass 7, count 2 2006.218.08:13:21.14#ibcon#wrote, iclass 7, count 2 2006.218.08:13:21.14#ibcon#about to read 3, iclass 7, count 2 2006.218.08:13:21.17#ibcon#read 3, iclass 7, count 2 2006.218.08:13:21.17#ibcon#about to read 4, iclass 7, count 2 2006.218.08:13:21.17#ibcon#read 4, iclass 7, count 2 2006.218.08:13:21.17#ibcon#about to read 5, iclass 7, count 2 2006.218.08:13:21.17#ibcon#read 5, iclass 7, count 2 2006.218.08:13:21.17#ibcon#about to read 6, iclass 7, count 2 2006.218.08:13:21.17#ibcon#read 6, iclass 7, count 2 2006.218.08:13:21.17#ibcon#end of sib2, iclass 7, count 2 2006.218.08:13:21.17#ibcon#*after write, iclass 7, count 2 2006.218.08:13:21.17#ibcon#*before return 0, iclass 7, count 2 2006.218.08:13:21.17#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.218.08:13:21.17#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.218.08:13:21.17#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.218.08:13:21.17#ibcon#ireg 7 cls_cnt 0 2006.218.08:13:21.17#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.218.08:13:21.29#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.218.08:13:21.29#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.218.08:13:21.29#ibcon#enter wrdev, iclass 7, count 0 2006.218.08:13:21.29#ibcon#first serial, iclass 7, count 0 2006.218.08:13:21.29#ibcon#enter sib2, iclass 7, count 0 2006.218.08:13:21.29#ibcon#flushed, iclass 7, count 0 2006.218.08:13:21.29#ibcon#about to write, iclass 7, count 0 2006.218.08:13:21.29#ibcon#wrote, iclass 7, count 0 2006.218.08:13:21.29#ibcon#about to read 3, iclass 7, count 0 2006.218.08:13:21.31#ibcon#read 3, iclass 7, count 0 2006.218.08:13:21.31#ibcon#about to read 4, iclass 7, count 0 2006.218.08:13:21.31#ibcon#read 4, iclass 7, count 0 2006.218.08:13:21.31#ibcon#about to read 5, iclass 7, count 0 2006.218.08:13:21.31#ibcon#read 5, iclass 7, count 0 2006.218.08:13:21.31#ibcon#about to read 6, iclass 7, count 0 2006.218.08:13:21.31#ibcon#read 6, iclass 7, count 0 2006.218.08:13:21.31#ibcon#end of sib2, iclass 7, count 0 2006.218.08:13:21.31#ibcon#*mode == 0, iclass 7, count 0 2006.218.08:13:21.31#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.218.08:13:21.31#ibcon#[27=USB\r\n] 2006.218.08:13:21.31#ibcon#*before write, iclass 7, count 0 2006.218.08:13:21.31#ibcon#enter sib2, iclass 7, count 0 2006.218.08:13:21.31#ibcon#flushed, iclass 7, count 0 2006.218.08:13:21.31#ibcon#about to write, iclass 7, count 0 2006.218.08:13:21.31#ibcon#wrote, iclass 7, count 0 2006.218.08:13:21.31#ibcon#about to read 3, iclass 7, count 0 2006.218.08:13:21.34#ibcon#read 3, iclass 7, count 0 2006.218.08:13:21.34#ibcon#about to read 4, iclass 7, count 0 2006.218.08:13:21.34#ibcon#read 4, iclass 7, count 0 2006.218.08:13:21.34#ibcon#about to read 5, iclass 7, count 0 2006.218.08:13:21.34#ibcon#read 5, iclass 7, count 0 2006.218.08:13:21.34#ibcon#about to read 6, iclass 7, count 0 2006.218.08:13:21.34#ibcon#read 6, iclass 7, count 0 2006.218.08:13:21.34#ibcon#end of sib2, iclass 7, count 0 2006.218.08:13:21.34#ibcon#*after write, iclass 7, count 0 2006.218.08:13:21.34#ibcon#*before return 0, iclass 7, count 0 2006.218.08:13:21.34#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.218.08:13:21.34#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.218.08:13:21.34#ibcon#about to clear, iclass 7 cls_cnt 0 2006.218.08:13:21.34#ibcon#cleared, iclass 7 cls_cnt 0 2006.218.08:13:21.34$vc4f8/vblo=3,656.99 2006.218.08:13:21.34#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.218.08:13:21.34#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.218.08:13:21.34#ibcon#ireg 17 cls_cnt 0 2006.218.08:13:21.34#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.218.08:13:21.34#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.218.08:13:21.34#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.218.08:13:21.34#ibcon#enter wrdev, iclass 11, count 0 2006.218.08:13:21.34#ibcon#first serial, iclass 11, count 0 2006.218.08:13:21.34#ibcon#enter sib2, iclass 11, count 0 2006.218.08:13:21.34#ibcon#flushed, iclass 11, count 0 2006.218.08:13:21.34#ibcon#about to write, iclass 11, count 0 2006.218.08:13:21.34#ibcon#wrote, iclass 11, count 0 2006.218.08:13:21.34#ibcon#about to read 3, iclass 11, count 0 2006.218.08:13:21.36#ibcon#read 3, iclass 11, count 0 2006.218.08:13:21.36#ibcon#about to read 4, iclass 11, count 0 2006.218.08:13:21.36#ibcon#read 4, iclass 11, count 0 2006.218.08:13:21.36#ibcon#about to read 5, iclass 11, count 0 2006.218.08:13:21.36#ibcon#read 5, iclass 11, count 0 2006.218.08:13:21.36#ibcon#about to read 6, iclass 11, count 0 2006.218.08:13:21.36#ibcon#read 6, iclass 11, count 0 2006.218.08:13:21.36#ibcon#end of sib2, iclass 11, count 0 2006.218.08:13:21.36#ibcon#*mode == 0, iclass 11, count 0 2006.218.08:13:21.36#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.218.08:13:21.36#ibcon#[28=FRQ=03,656.99\r\n] 2006.218.08:13:21.36#ibcon#*before write, iclass 11, count 0 2006.218.08:13:21.36#ibcon#enter sib2, iclass 11, count 0 2006.218.08:13:21.36#ibcon#flushed, iclass 11, count 0 2006.218.08:13:21.36#ibcon#about to write, iclass 11, count 0 2006.218.08:13:21.36#ibcon#wrote, iclass 11, count 0 2006.218.08:13:21.36#ibcon#about to read 3, iclass 11, count 0 2006.218.08:13:21.40#ibcon#read 3, iclass 11, count 0 2006.218.08:13:21.40#ibcon#about to read 4, iclass 11, count 0 2006.218.08:13:21.40#ibcon#read 4, iclass 11, count 0 2006.218.08:13:21.40#ibcon#about to read 5, iclass 11, count 0 2006.218.08:13:21.40#ibcon#read 5, iclass 11, count 0 2006.218.08:13:21.40#ibcon#about to read 6, iclass 11, count 0 2006.218.08:13:21.40#ibcon#read 6, iclass 11, count 0 2006.218.08:13:21.40#ibcon#end of sib2, iclass 11, count 0 2006.218.08:13:21.40#ibcon#*after write, iclass 11, count 0 2006.218.08:13:21.40#ibcon#*before return 0, iclass 11, count 0 2006.218.08:13:21.40#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.218.08:13:21.40#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.218.08:13:21.40#ibcon#about to clear, iclass 11 cls_cnt 0 2006.218.08:13:21.40#ibcon#cleared, iclass 11 cls_cnt 0 2006.218.08:13:21.40$vc4f8/vb=3,4 2006.218.08:13:21.40#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.218.08:13:21.40#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.218.08:13:21.40#ibcon#ireg 11 cls_cnt 2 2006.218.08:13:21.40#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.218.08:13:21.46#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.218.08:13:21.46#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.218.08:13:21.46#ibcon#enter wrdev, iclass 13, count 2 2006.218.08:13:21.46#ibcon#first serial, iclass 13, count 2 2006.218.08:13:21.46#ibcon#enter sib2, iclass 13, count 2 2006.218.08:13:21.46#ibcon#flushed, iclass 13, count 2 2006.218.08:13:21.46#ibcon#about to write, iclass 13, count 2 2006.218.08:13:21.46#ibcon#wrote, iclass 13, count 2 2006.218.08:13:21.46#ibcon#about to read 3, iclass 13, count 2 2006.218.08:13:21.48#ibcon#read 3, iclass 13, count 2 2006.218.08:13:21.48#ibcon#about to read 4, iclass 13, count 2 2006.218.08:13:21.48#ibcon#read 4, iclass 13, count 2 2006.218.08:13:21.48#ibcon#about to read 5, iclass 13, count 2 2006.218.08:13:21.48#ibcon#read 5, iclass 13, count 2 2006.218.08:13:21.48#ibcon#about to read 6, iclass 13, count 2 2006.218.08:13:21.48#ibcon#read 6, iclass 13, count 2 2006.218.08:13:21.48#ibcon#end of sib2, iclass 13, count 2 2006.218.08:13:21.48#ibcon#*mode == 0, iclass 13, count 2 2006.218.08:13:21.48#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.218.08:13:21.48#ibcon#[27=AT03-04\r\n] 2006.218.08:13:21.48#ibcon#*before write, iclass 13, count 2 2006.218.08:13:21.48#ibcon#enter sib2, iclass 13, count 2 2006.218.08:13:21.48#ibcon#flushed, iclass 13, count 2 2006.218.08:13:21.48#ibcon#about to write, iclass 13, count 2 2006.218.08:13:21.48#ibcon#wrote, iclass 13, count 2 2006.218.08:13:21.48#ibcon#about to read 3, iclass 13, count 2 2006.218.08:13:21.51#ibcon#read 3, iclass 13, count 2 2006.218.08:13:21.51#ibcon#about to read 4, iclass 13, count 2 2006.218.08:13:21.51#ibcon#read 4, iclass 13, count 2 2006.218.08:13:21.51#ibcon#about to read 5, iclass 13, count 2 2006.218.08:13:21.51#ibcon#read 5, iclass 13, count 2 2006.218.08:13:21.51#ibcon#about to read 6, iclass 13, count 2 2006.218.08:13:21.51#ibcon#read 6, iclass 13, count 2 2006.218.08:13:21.51#ibcon#end of sib2, iclass 13, count 2 2006.218.08:13:21.51#ibcon#*after write, iclass 13, count 2 2006.218.08:13:21.51#ibcon#*before return 0, iclass 13, count 2 2006.218.08:13:21.51#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.218.08:13:21.51#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.218.08:13:21.51#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.218.08:13:21.51#ibcon#ireg 7 cls_cnt 0 2006.218.08:13:21.51#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.218.08:13:21.63#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.218.08:13:21.63#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.218.08:13:21.63#ibcon#enter wrdev, iclass 13, count 0 2006.218.08:13:21.63#ibcon#first serial, iclass 13, count 0 2006.218.08:13:21.63#ibcon#enter sib2, iclass 13, count 0 2006.218.08:13:21.63#ibcon#flushed, iclass 13, count 0 2006.218.08:13:21.63#ibcon#about to write, iclass 13, count 0 2006.218.08:13:21.63#ibcon#wrote, iclass 13, count 0 2006.218.08:13:21.63#ibcon#about to read 3, iclass 13, count 0 2006.218.08:13:21.65#ibcon#read 3, iclass 13, count 0 2006.218.08:13:21.65#ibcon#about to read 4, iclass 13, count 0 2006.218.08:13:21.65#ibcon#read 4, iclass 13, count 0 2006.218.08:13:21.65#ibcon#about to read 5, iclass 13, count 0 2006.218.08:13:21.65#ibcon#read 5, iclass 13, count 0 2006.218.08:13:21.65#ibcon#about to read 6, iclass 13, count 0 2006.218.08:13:21.65#ibcon#read 6, iclass 13, count 0 2006.218.08:13:21.65#ibcon#end of sib2, iclass 13, count 0 2006.218.08:13:21.65#ibcon#*mode == 0, iclass 13, count 0 2006.218.08:13:21.65#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.218.08:13:21.65#ibcon#[27=USB\r\n] 2006.218.08:13:21.65#ibcon#*before write, iclass 13, count 0 2006.218.08:13:21.65#ibcon#enter sib2, iclass 13, count 0 2006.218.08:13:21.65#ibcon#flushed, iclass 13, count 0 2006.218.08:13:21.65#ibcon#about to write, iclass 13, count 0 2006.218.08:13:21.65#ibcon#wrote, iclass 13, count 0 2006.218.08:13:21.65#ibcon#about to read 3, iclass 13, count 0 2006.218.08:13:21.68#ibcon#read 3, iclass 13, count 0 2006.218.08:13:21.68#ibcon#about to read 4, iclass 13, count 0 2006.218.08:13:21.68#ibcon#read 4, iclass 13, count 0 2006.218.08:13:21.68#ibcon#about to read 5, iclass 13, count 0 2006.218.08:13:21.68#ibcon#read 5, iclass 13, count 0 2006.218.08:13:21.68#ibcon#about to read 6, iclass 13, count 0 2006.218.08:13:21.68#ibcon#read 6, iclass 13, count 0 2006.218.08:13:21.68#ibcon#end of sib2, iclass 13, count 0 2006.218.08:13:21.68#ibcon#*after write, iclass 13, count 0 2006.218.08:13:21.68#ibcon#*before return 0, iclass 13, count 0 2006.218.08:13:21.68#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.218.08:13:21.68#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.218.08:13:21.68#ibcon#about to clear, iclass 13 cls_cnt 0 2006.218.08:13:21.68#ibcon#cleared, iclass 13 cls_cnt 0 2006.218.08:13:21.68$vc4f8/vblo=4,712.99 2006.218.08:13:21.68#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.218.08:13:21.68#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.218.08:13:21.68#ibcon#ireg 17 cls_cnt 0 2006.218.08:13:21.68#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.218.08:13:21.68#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.218.08:13:21.68#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.218.08:13:21.68#ibcon#enter wrdev, iclass 15, count 0 2006.218.08:13:21.68#ibcon#first serial, iclass 15, count 0 2006.218.08:13:21.68#ibcon#enter sib2, iclass 15, count 0 2006.218.08:13:21.68#ibcon#flushed, iclass 15, count 0 2006.218.08:13:21.68#ibcon#about to write, iclass 15, count 0 2006.218.08:13:21.68#ibcon#wrote, iclass 15, count 0 2006.218.08:13:21.68#ibcon#about to read 3, iclass 15, count 0 2006.218.08:13:21.70#ibcon#read 3, iclass 15, count 0 2006.218.08:13:21.70#ibcon#about to read 4, iclass 15, count 0 2006.218.08:13:21.70#ibcon#read 4, iclass 15, count 0 2006.218.08:13:21.70#ibcon#about to read 5, iclass 15, count 0 2006.218.08:13:21.70#ibcon#read 5, iclass 15, count 0 2006.218.08:13:21.70#ibcon#about to read 6, iclass 15, count 0 2006.218.08:13:21.70#ibcon#read 6, iclass 15, count 0 2006.218.08:13:21.70#ibcon#end of sib2, iclass 15, count 0 2006.218.08:13:21.70#ibcon#*mode == 0, iclass 15, count 0 2006.218.08:13:21.70#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.218.08:13:21.70#ibcon#[28=FRQ=04,712.99\r\n] 2006.218.08:13:21.70#ibcon#*before write, iclass 15, count 0 2006.218.08:13:21.70#ibcon#enter sib2, iclass 15, count 0 2006.218.08:13:21.70#ibcon#flushed, iclass 15, count 0 2006.218.08:13:21.70#ibcon#about to write, iclass 15, count 0 2006.218.08:13:21.70#ibcon#wrote, iclass 15, count 0 2006.218.08:13:21.70#ibcon#about to read 3, iclass 15, count 0 2006.218.08:13:21.74#ibcon#read 3, iclass 15, count 0 2006.218.08:13:21.74#ibcon#about to read 4, iclass 15, count 0 2006.218.08:13:21.74#ibcon#read 4, iclass 15, count 0 2006.218.08:13:21.74#ibcon#about to read 5, iclass 15, count 0 2006.218.08:13:21.74#ibcon#read 5, iclass 15, count 0 2006.218.08:13:21.74#ibcon#about to read 6, iclass 15, count 0 2006.218.08:13:21.74#ibcon#read 6, iclass 15, count 0 2006.218.08:13:21.74#ibcon#end of sib2, iclass 15, count 0 2006.218.08:13:21.74#ibcon#*after write, iclass 15, count 0 2006.218.08:13:21.74#ibcon#*before return 0, iclass 15, count 0 2006.218.08:13:21.74#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.218.08:13:21.74#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.218.08:13:21.74#ibcon#about to clear, iclass 15 cls_cnt 0 2006.218.08:13:21.74#ibcon#cleared, iclass 15 cls_cnt 0 2006.218.08:13:21.74$vc4f8/vb=4,4 2006.218.08:13:21.74#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.218.08:13:21.74#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.218.08:13:21.74#ibcon#ireg 11 cls_cnt 2 2006.218.08:13:21.74#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.218.08:13:21.80#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.218.08:13:21.80#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.218.08:13:21.80#ibcon#enter wrdev, iclass 17, count 2 2006.218.08:13:21.80#ibcon#first serial, iclass 17, count 2 2006.218.08:13:21.80#ibcon#enter sib2, iclass 17, count 2 2006.218.08:13:21.80#ibcon#flushed, iclass 17, count 2 2006.218.08:13:21.80#ibcon#about to write, iclass 17, count 2 2006.218.08:13:21.80#ibcon#wrote, iclass 17, count 2 2006.218.08:13:21.80#ibcon#about to read 3, iclass 17, count 2 2006.218.08:13:21.82#ibcon#read 3, iclass 17, count 2 2006.218.08:13:21.82#ibcon#about to read 4, iclass 17, count 2 2006.218.08:13:21.82#ibcon#read 4, iclass 17, count 2 2006.218.08:13:21.82#ibcon#about to read 5, iclass 17, count 2 2006.218.08:13:21.82#ibcon#read 5, iclass 17, count 2 2006.218.08:13:21.82#ibcon#about to read 6, iclass 17, count 2 2006.218.08:13:21.82#ibcon#read 6, iclass 17, count 2 2006.218.08:13:21.82#ibcon#end of sib2, iclass 17, count 2 2006.218.08:13:21.82#ibcon#*mode == 0, iclass 17, count 2 2006.218.08:13:21.82#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.218.08:13:21.82#ibcon#[27=AT04-04\r\n] 2006.218.08:13:21.82#ibcon#*before write, iclass 17, count 2 2006.218.08:13:21.82#ibcon#enter sib2, iclass 17, count 2 2006.218.08:13:21.82#ibcon#flushed, iclass 17, count 2 2006.218.08:13:21.82#ibcon#about to write, iclass 17, count 2 2006.218.08:13:21.82#ibcon#wrote, iclass 17, count 2 2006.218.08:13:21.82#ibcon#about to read 3, iclass 17, count 2 2006.218.08:13:21.85#ibcon#read 3, iclass 17, count 2 2006.218.08:13:21.85#ibcon#about to read 4, iclass 17, count 2 2006.218.08:13:21.85#ibcon#read 4, iclass 17, count 2 2006.218.08:13:21.85#ibcon#about to read 5, iclass 17, count 2 2006.218.08:13:21.85#ibcon#read 5, iclass 17, count 2 2006.218.08:13:21.85#ibcon#about to read 6, iclass 17, count 2 2006.218.08:13:21.85#ibcon#read 6, iclass 17, count 2 2006.218.08:13:21.85#ibcon#end of sib2, iclass 17, count 2 2006.218.08:13:21.85#ibcon#*after write, iclass 17, count 2 2006.218.08:13:21.85#ibcon#*before return 0, iclass 17, count 2 2006.218.08:13:21.85#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.218.08:13:21.85#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.218.08:13:21.85#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.218.08:13:21.85#ibcon#ireg 7 cls_cnt 0 2006.218.08:13:21.85#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.218.08:13:21.97#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.218.08:13:21.97#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.218.08:13:21.97#ibcon#enter wrdev, iclass 17, count 0 2006.218.08:13:21.97#ibcon#first serial, iclass 17, count 0 2006.218.08:13:21.97#ibcon#enter sib2, iclass 17, count 0 2006.218.08:13:21.97#ibcon#flushed, iclass 17, count 0 2006.218.08:13:21.97#ibcon#about to write, iclass 17, count 0 2006.218.08:13:21.97#ibcon#wrote, iclass 17, count 0 2006.218.08:13:21.97#ibcon#about to read 3, iclass 17, count 0 2006.218.08:13:21.99#ibcon#read 3, iclass 17, count 0 2006.218.08:13:21.99#ibcon#about to read 4, iclass 17, count 0 2006.218.08:13:21.99#ibcon#read 4, iclass 17, count 0 2006.218.08:13:21.99#ibcon#about to read 5, iclass 17, count 0 2006.218.08:13:21.99#ibcon#read 5, iclass 17, count 0 2006.218.08:13:21.99#ibcon#about to read 6, iclass 17, count 0 2006.218.08:13:21.99#ibcon#read 6, iclass 17, count 0 2006.218.08:13:21.99#ibcon#end of sib2, iclass 17, count 0 2006.218.08:13:21.99#ibcon#*mode == 0, iclass 17, count 0 2006.218.08:13:21.99#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.218.08:13:21.99#ibcon#[27=USB\r\n] 2006.218.08:13:21.99#ibcon#*before write, iclass 17, count 0 2006.218.08:13:21.99#ibcon#enter sib2, iclass 17, count 0 2006.218.08:13:21.99#ibcon#flushed, iclass 17, count 0 2006.218.08:13:21.99#ibcon#about to write, iclass 17, count 0 2006.218.08:13:21.99#ibcon#wrote, iclass 17, count 0 2006.218.08:13:21.99#ibcon#about to read 3, iclass 17, count 0 2006.218.08:13:22.02#ibcon#read 3, iclass 17, count 0 2006.218.08:13:22.02#ibcon#about to read 4, iclass 17, count 0 2006.218.08:13:22.02#ibcon#read 4, iclass 17, count 0 2006.218.08:13:22.02#ibcon#about to read 5, iclass 17, count 0 2006.218.08:13:22.02#ibcon#read 5, iclass 17, count 0 2006.218.08:13:22.02#ibcon#about to read 6, iclass 17, count 0 2006.218.08:13:22.02#ibcon#read 6, iclass 17, count 0 2006.218.08:13:22.02#ibcon#end of sib2, iclass 17, count 0 2006.218.08:13:22.02#ibcon#*after write, iclass 17, count 0 2006.218.08:13:22.02#ibcon#*before return 0, iclass 17, count 0 2006.218.08:13:22.02#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.218.08:13:22.02#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.218.08:13:22.02#ibcon#about to clear, iclass 17 cls_cnt 0 2006.218.08:13:22.02#ibcon#cleared, iclass 17 cls_cnt 0 2006.218.08:13:22.02$vc4f8/vblo=5,744.99 2006.218.08:13:22.02#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.218.08:13:22.02#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.218.08:13:22.02#ibcon#ireg 17 cls_cnt 0 2006.218.08:13:22.02#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.218.08:13:22.02#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.218.08:13:22.02#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.218.08:13:22.02#ibcon#enter wrdev, iclass 19, count 0 2006.218.08:13:22.02#ibcon#first serial, iclass 19, count 0 2006.218.08:13:22.02#ibcon#enter sib2, iclass 19, count 0 2006.218.08:13:22.02#ibcon#flushed, iclass 19, count 0 2006.218.08:13:22.02#ibcon#about to write, iclass 19, count 0 2006.218.08:13:22.02#ibcon#wrote, iclass 19, count 0 2006.218.08:13:22.02#ibcon#about to read 3, iclass 19, count 0 2006.218.08:13:22.04#ibcon#read 3, iclass 19, count 0 2006.218.08:13:22.04#ibcon#about to read 4, iclass 19, count 0 2006.218.08:13:22.04#ibcon#read 4, iclass 19, count 0 2006.218.08:13:22.04#ibcon#about to read 5, iclass 19, count 0 2006.218.08:13:22.04#ibcon#read 5, iclass 19, count 0 2006.218.08:13:22.04#ibcon#about to read 6, iclass 19, count 0 2006.218.08:13:22.04#ibcon#read 6, iclass 19, count 0 2006.218.08:13:22.04#ibcon#end of sib2, iclass 19, count 0 2006.218.08:13:22.04#ibcon#*mode == 0, iclass 19, count 0 2006.218.08:13:22.04#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.218.08:13:22.04#ibcon#[28=FRQ=05,744.99\r\n] 2006.218.08:13:22.04#ibcon#*before write, iclass 19, count 0 2006.218.08:13:22.04#ibcon#enter sib2, iclass 19, count 0 2006.218.08:13:22.04#ibcon#flushed, iclass 19, count 0 2006.218.08:13:22.04#ibcon#about to write, iclass 19, count 0 2006.218.08:13:22.04#ibcon#wrote, iclass 19, count 0 2006.218.08:13:22.04#ibcon#about to read 3, iclass 19, count 0 2006.218.08:13:22.08#ibcon#read 3, iclass 19, count 0 2006.218.08:13:22.08#ibcon#about to read 4, iclass 19, count 0 2006.218.08:13:22.08#ibcon#read 4, iclass 19, count 0 2006.218.08:13:22.08#ibcon#about to read 5, iclass 19, count 0 2006.218.08:13:22.08#ibcon#read 5, iclass 19, count 0 2006.218.08:13:22.08#ibcon#about to read 6, iclass 19, count 0 2006.218.08:13:22.08#ibcon#read 6, iclass 19, count 0 2006.218.08:13:22.08#ibcon#end of sib2, iclass 19, count 0 2006.218.08:13:22.08#ibcon#*after write, iclass 19, count 0 2006.218.08:13:22.08#ibcon#*before return 0, iclass 19, count 0 2006.218.08:13:22.08#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.218.08:13:22.08#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.218.08:13:22.08#ibcon#about to clear, iclass 19 cls_cnt 0 2006.218.08:13:22.08#ibcon#cleared, iclass 19 cls_cnt 0 2006.218.08:13:22.08$vc4f8/vb=5,4 2006.218.08:13:22.08#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.218.08:13:22.08#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.218.08:13:22.08#ibcon#ireg 11 cls_cnt 2 2006.218.08:13:22.08#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.218.08:13:22.14#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.218.08:13:22.14#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.218.08:13:22.14#ibcon#enter wrdev, iclass 21, count 2 2006.218.08:13:22.14#ibcon#first serial, iclass 21, count 2 2006.218.08:13:22.14#ibcon#enter sib2, iclass 21, count 2 2006.218.08:13:22.14#ibcon#flushed, iclass 21, count 2 2006.218.08:13:22.14#ibcon#about to write, iclass 21, count 2 2006.218.08:13:22.14#ibcon#wrote, iclass 21, count 2 2006.218.08:13:22.14#ibcon#about to read 3, iclass 21, count 2 2006.218.08:13:22.16#ibcon#read 3, iclass 21, count 2 2006.218.08:13:22.16#ibcon#about to read 4, iclass 21, count 2 2006.218.08:13:22.16#ibcon#read 4, iclass 21, count 2 2006.218.08:13:22.16#ibcon#about to read 5, iclass 21, count 2 2006.218.08:13:22.16#ibcon#read 5, iclass 21, count 2 2006.218.08:13:22.16#ibcon#about to read 6, iclass 21, count 2 2006.218.08:13:22.16#ibcon#read 6, iclass 21, count 2 2006.218.08:13:22.16#ibcon#end of sib2, iclass 21, count 2 2006.218.08:13:22.16#ibcon#*mode == 0, iclass 21, count 2 2006.218.08:13:22.16#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.218.08:13:22.16#ibcon#[27=AT05-04\r\n] 2006.218.08:13:22.16#ibcon#*before write, iclass 21, count 2 2006.218.08:13:22.16#ibcon#enter sib2, iclass 21, count 2 2006.218.08:13:22.16#ibcon#flushed, iclass 21, count 2 2006.218.08:13:22.16#ibcon#about to write, iclass 21, count 2 2006.218.08:13:22.16#ibcon#wrote, iclass 21, count 2 2006.218.08:13:22.16#ibcon#about to read 3, iclass 21, count 2 2006.218.08:13:22.19#ibcon#read 3, iclass 21, count 2 2006.218.08:13:22.19#ibcon#about to read 4, iclass 21, count 2 2006.218.08:13:22.19#ibcon#read 4, iclass 21, count 2 2006.218.08:13:22.19#ibcon#about to read 5, iclass 21, count 2 2006.218.08:13:22.19#ibcon#read 5, iclass 21, count 2 2006.218.08:13:22.19#ibcon#about to read 6, iclass 21, count 2 2006.218.08:13:22.19#ibcon#read 6, iclass 21, count 2 2006.218.08:13:22.19#ibcon#end of sib2, iclass 21, count 2 2006.218.08:13:22.19#ibcon#*after write, iclass 21, count 2 2006.218.08:13:22.19#ibcon#*before return 0, iclass 21, count 2 2006.218.08:13:22.19#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.218.08:13:22.19#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.218.08:13:22.19#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.218.08:13:22.19#ibcon#ireg 7 cls_cnt 0 2006.218.08:13:22.19#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.218.08:13:22.31#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.218.08:13:22.31#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.218.08:13:22.31#ibcon#enter wrdev, iclass 21, count 0 2006.218.08:13:22.31#ibcon#first serial, iclass 21, count 0 2006.218.08:13:22.31#ibcon#enter sib2, iclass 21, count 0 2006.218.08:13:22.31#ibcon#flushed, iclass 21, count 0 2006.218.08:13:22.31#ibcon#about to write, iclass 21, count 0 2006.218.08:13:22.31#ibcon#wrote, iclass 21, count 0 2006.218.08:13:22.31#ibcon#about to read 3, iclass 21, count 0 2006.218.08:13:22.33#ibcon#read 3, iclass 21, count 0 2006.218.08:13:22.33#ibcon#about to read 4, iclass 21, count 0 2006.218.08:13:22.33#ibcon#read 4, iclass 21, count 0 2006.218.08:13:22.33#ibcon#about to read 5, iclass 21, count 0 2006.218.08:13:22.33#ibcon#read 5, iclass 21, count 0 2006.218.08:13:22.33#ibcon#about to read 6, iclass 21, count 0 2006.218.08:13:22.33#ibcon#read 6, iclass 21, count 0 2006.218.08:13:22.33#ibcon#end of sib2, iclass 21, count 0 2006.218.08:13:22.33#ibcon#*mode == 0, iclass 21, count 0 2006.218.08:13:22.33#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.218.08:13:22.33#ibcon#[27=USB\r\n] 2006.218.08:13:22.33#ibcon#*before write, iclass 21, count 0 2006.218.08:13:22.33#ibcon#enter sib2, iclass 21, count 0 2006.218.08:13:22.33#ibcon#flushed, iclass 21, count 0 2006.218.08:13:22.33#ibcon#about to write, iclass 21, count 0 2006.218.08:13:22.33#ibcon#wrote, iclass 21, count 0 2006.218.08:13:22.33#ibcon#about to read 3, iclass 21, count 0 2006.218.08:13:22.36#ibcon#read 3, iclass 21, count 0 2006.218.08:13:22.36#ibcon#about to read 4, iclass 21, count 0 2006.218.08:13:22.36#ibcon#read 4, iclass 21, count 0 2006.218.08:13:22.36#ibcon#about to read 5, iclass 21, count 0 2006.218.08:13:22.36#ibcon#read 5, iclass 21, count 0 2006.218.08:13:22.36#ibcon#about to read 6, iclass 21, count 0 2006.218.08:13:22.36#ibcon#read 6, iclass 21, count 0 2006.218.08:13:22.36#ibcon#end of sib2, iclass 21, count 0 2006.218.08:13:22.36#ibcon#*after write, iclass 21, count 0 2006.218.08:13:22.36#ibcon#*before return 0, iclass 21, count 0 2006.218.08:13:22.36#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.218.08:13:22.36#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.218.08:13:22.36#ibcon#about to clear, iclass 21 cls_cnt 0 2006.218.08:13:22.36#ibcon#cleared, iclass 21 cls_cnt 0 2006.218.08:13:22.36$vc4f8/vblo=6,752.99 2006.218.08:13:22.36#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.218.08:13:22.36#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.218.08:13:22.36#ibcon#ireg 17 cls_cnt 0 2006.218.08:13:22.36#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.218.08:13:22.36#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.218.08:13:22.36#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.218.08:13:22.36#ibcon#enter wrdev, iclass 23, count 0 2006.218.08:13:22.36#ibcon#first serial, iclass 23, count 0 2006.218.08:13:22.36#ibcon#enter sib2, iclass 23, count 0 2006.218.08:13:22.36#ibcon#flushed, iclass 23, count 0 2006.218.08:13:22.36#ibcon#about to write, iclass 23, count 0 2006.218.08:13:22.36#ibcon#wrote, iclass 23, count 0 2006.218.08:13:22.36#ibcon#about to read 3, iclass 23, count 0 2006.218.08:13:22.38#ibcon#read 3, iclass 23, count 0 2006.218.08:13:22.38#ibcon#about to read 4, iclass 23, count 0 2006.218.08:13:22.38#ibcon#read 4, iclass 23, count 0 2006.218.08:13:22.38#ibcon#about to read 5, iclass 23, count 0 2006.218.08:13:22.38#ibcon#read 5, iclass 23, count 0 2006.218.08:13:22.38#ibcon#about to read 6, iclass 23, count 0 2006.218.08:13:22.38#ibcon#read 6, iclass 23, count 0 2006.218.08:13:22.38#ibcon#end of sib2, iclass 23, count 0 2006.218.08:13:22.38#ibcon#*mode == 0, iclass 23, count 0 2006.218.08:13:22.38#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.218.08:13:22.38#ibcon#[28=FRQ=06,752.99\r\n] 2006.218.08:13:22.38#ibcon#*before write, iclass 23, count 0 2006.218.08:13:22.38#ibcon#enter sib2, iclass 23, count 0 2006.218.08:13:22.38#ibcon#flushed, iclass 23, count 0 2006.218.08:13:22.38#ibcon#about to write, iclass 23, count 0 2006.218.08:13:22.38#ibcon#wrote, iclass 23, count 0 2006.218.08:13:22.38#ibcon#about to read 3, iclass 23, count 0 2006.218.08:13:22.42#ibcon#read 3, iclass 23, count 0 2006.218.08:13:22.42#ibcon#about to read 4, iclass 23, count 0 2006.218.08:13:22.42#ibcon#read 4, iclass 23, count 0 2006.218.08:13:22.42#ibcon#about to read 5, iclass 23, count 0 2006.218.08:13:22.42#ibcon#read 5, iclass 23, count 0 2006.218.08:13:22.42#ibcon#about to read 6, iclass 23, count 0 2006.218.08:13:22.42#ibcon#read 6, iclass 23, count 0 2006.218.08:13:22.42#ibcon#end of sib2, iclass 23, count 0 2006.218.08:13:22.42#ibcon#*after write, iclass 23, count 0 2006.218.08:13:22.42#ibcon#*before return 0, iclass 23, count 0 2006.218.08:13:22.42#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.218.08:13:22.42#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.218.08:13:22.42#ibcon#about to clear, iclass 23 cls_cnt 0 2006.218.08:13:22.42#ibcon#cleared, iclass 23 cls_cnt 0 2006.218.08:13:22.42$vc4f8/vb=6,4 2006.218.08:13:22.42#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.218.08:13:22.42#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.218.08:13:22.42#ibcon#ireg 11 cls_cnt 2 2006.218.08:13:22.42#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.218.08:13:22.48#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.218.08:13:22.48#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.218.08:13:22.48#ibcon#enter wrdev, iclass 25, count 2 2006.218.08:13:22.48#ibcon#first serial, iclass 25, count 2 2006.218.08:13:22.48#ibcon#enter sib2, iclass 25, count 2 2006.218.08:13:22.48#ibcon#flushed, iclass 25, count 2 2006.218.08:13:22.48#ibcon#about to write, iclass 25, count 2 2006.218.08:13:22.48#ibcon#wrote, iclass 25, count 2 2006.218.08:13:22.48#ibcon#about to read 3, iclass 25, count 2 2006.218.08:13:22.50#ibcon#read 3, iclass 25, count 2 2006.218.08:13:22.50#ibcon#about to read 4, iclass 25, count 2 2006.218.08:13:22.50#ibcon#read 4, iclass 25, count 2 2006.218.08:13:22.50#ibcon#about to read 5, iclass 25, count 2 2006.218.08:13:22.50#ibcon#read 5, iclass 25, count 2 2006.218.08:13:22.50#ibcon#about to read 6, iclass 25, count 2 2006.218.08:13:22.50#ibcon#read 6, iclass 25, count 2 2006.218.08:13:22.50#ibcon#end of sib2, iclass 25, count 2 2006.218.08:13:22.50#ibcon#*mode == 0, iclass 25, count 2 2006.218.08:13:22.50#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.218.08:13:22.50#ibcon#[27=AT06-04\r\n] 2006.218.08:13:22.50#ibcon#*before write, iclass 25, count 2 2006.218.08:13:22.50#ibcon#enter sib2, iclass 25, count 2 2006.218.08:13:22.50#ibcon#flushed, iclass 25, count 2 2006.218.08:13:22.50#ibcon#about to write, iclass 25, count 2 2006.218.08:13:22.50#ibcon#wrote, iclass 25, count 2 2006.218.08:13:22.50#ibcon#about to read 3, iclass 25, count 2 2006.218.08:13:22.53#ibcon#read 3, iclass 25, count 2 2006.218.08:13:22.53#ibcon#about to read 4, iclass 25, count 2 2006.218.08:13:22.53#ibcon#read 4, iclass 25, count 2 2006.218.08:13:22.53#ibcon#about to read 5, iclass 25, count 2 2006.218.08:13:22.53#ibcon#read 5, iclass 25, count 2 2006.218.08:13:22.53#ibcon#about to read 6, iclass 25, count 2 2006.218.08:13:22.53#ibcon#read 6, iclass 25, count 2 2006.218.08:13:22.53#ibcon#end of sib2, iclass 25, count 2 2006.218.08:13:22.53#ibcon#*after write, iclass 25, count 2 2006.218.08:13:22.53#ibcon#*before return 0, iclass 25, count 2 2006.218.08:13:22.53#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.218.08:13:22.53#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.218.08:13:22.53#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.218.08:13:22.53#ibcon#ireg 7 cls_cnt 0 2006.218.08:13:22.53#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.218.08:13:22.65#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.218.08:13:22.65#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.218.08:13:22.65#ibcon#enter wrdev, iclass 25, count 0 2006.218.08:13:22.65#ibcon#first serial, iclass 25, count 0 2006.218.08:13:22.65#ibcon#enter sib2, iclass 25, count 0 2006.218.08:13:22.65#ibcon#flushed, iclass 25, count 0 2006.218.08:13:22.65#ibcon#about to write, iclass 25, count 0 2006.218.08:13:22.65#ibcon#wrote, iclass 25, count 0 2006.218.08:13:22.65#ibcon#about to read 3, iclass 25, count 0 2006.218.08:13:22.67#ibcon#read 3, iclass 25, count 0 2006.218.08:13:22.67#ibcon#about to read 4, iclass 25, count 0 2006.218.08:13:22.67#ibcon#read 4, iclass 25, count 0 2006.218.08:13:22.67#ibcon#about to read 5, iclass 25, count 0 2006.218.08:13:22.67#ibcon#read 5, iclass 25, count 0 2006.218.08:13:22.67#ibcon#about to read 6, iclass 25, count 0 2006.218.08:13:22.67#ibcon#read 6, iclass 25, count 0 2006.218.08:13:22.67#ibcon#end of sib2, iclass 25, count 0 2006.218.08:13:22.67#ibcon#*mode == 0, iclass 25, count 0 2006.218.08:13:22.67#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.218.08:13:22.67#ibcon#[27=USB\r\n] 2006.218.08:13:22.67#ibcon#*before write, iclass 25, count 0 2006.218.08:13:22.67#ibcon#enter sib2, iclass 25, count 0 2006.218.08:13:22.67#ibcon#flushed, iclass 25, count 0 2006.218.08:13:22.67#ibcon#about to write, iclass 25, count 0 2006.218.08:13:22.67#ibcon#wrote, iclass 25, count 0 2006.218.08:13:22.67#ibcon#about to read 3, iclass 25, count 0 2006.218.08:13:22.70#ibcon#read 3, iclass 25, count 0 2006.218.08:13:22.70#ibcon#about to read 4, iclass 25, count 0 2006.218.08:13:22.70#ibcon#read 4, iclass 25, count 0 2006.218.08:13:22.70#ibcon#about to read 5, iclass 25, count 0 2006.218.08:13:22.70#ibcon#read 5, iclass 25, count 0 2006.218.08:13:22.70#ibcon#about to read 6, iclass 25, count 0 2006.218.08:13:22.70#ibcon#read 6, iclass 25, count 0 2006.218.08:13:22.70#ibcon#end of sib2, iclass 25, count 0 2006.218.08:13:22.70#ibcon#*after write, iclass 25, count 0 2006.218.08:13:22.70#ibcon#*before return 0, iclass 25, count 0 2006.218.08:13:22.70#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.218.08:13:22.70#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.218.08:13:22.70#ibcon#about to clear, iclass 25 cls_cnt 0 2006.218.08:13:22.70#ibcon#cleared, iclass 25 cls_cnt 0 2006.218.08:13:22.70$vc4f8/vabw=wide 2006.218.08:13:22.70#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.218.08:13:22.70#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.218.08:13:22.70#ibcon#ireg 8 cls_cnt 0 2006.218.08:13:22.70#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.218.08:13:22.70#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.218.08:13:22.70#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.218.08:13:22.70#ibcon#enter wrdev, iclass 27, count 0 2006.218.08:13:22.70#ibcon#first serial, iclass 27, count 0 2006.218.08:13:22.70#ibcon#enter sib2, iclass 27, count 0 2006.218.08:13:22.70#ibcon#flushed, iclass 27, count 0 2006.218.08:13:22.70#ibcon#about to write, iclass 27, count 0 2006.218.08:13:22.70#ibcon#wrote, iclass 27, count 0 2006.218.08:13:22.70#ibcon#about to read 3, iclass 27, count 0 2006.218.08:13:22.72#ibcon#read 3, iclass 27, count 0 2006.218.08:13:22.72#ibcon#about to read 4, iclass 27, count 0 2006.218.08:13:22.72#ibcon#read 4, iclass 27, count 0 2006.218.08:13:22.72#ibcon#about to read 5, iclass 27, count 0 2006.218.08:13:22.72#ibcon#read 5, iclass 27, count 0 2006.218.08:13:22.72#ibcon#about to read 6, iclass 27, count 0 2006.218.08:13:22.72#ibcon#read 6, iclass 27, count 0 2006.218.08:13:22.72#ibcon#end of sib2, iclass 27, count 0 2006.218.08:13:22.72#ibcon#*mode == 0, iclass 27, count 0 2006.218.08:13:22.72#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.218.08:13:22.72#ibcon#[25=BW32\r\n] 2006.218.08:13:22.72#ibcon#*before write, iclass 27, count 0 2006.218.08:13:22.72#ibcon#enter sib2, iclass 27, count 0 2006.218.08:13:22.72#ibcon#flushed, iclass 27, count 0 2006.218.08:13:22.72#ibcon#about to write, iclass 27, count 0 2006.218.08:13:22.72#ibcon#wrote, iclass 27, count 0 2006.218.08:13:22.72#ibcon#about to read 3, iclass 27, count 0 2006.218.08:13:22.75#ibcon#read 3, iclass 27, count 0 2006.218.08:13:22.75#ibcon#about to read 4, iclass 27, count 0 2006.218.08:13:22.75#ibcon#read 4, iclass 27, count 0 2006.218.08:13:22.75#ibcon#about to read 5, iclass 27, count 0 2006.218.08:13:22.75#ibcon#read 5, iclass 27, count 0 2006.218.08:13:22.75#ibcon#about to read 6, iclass 27, count 0 2006.218.08:13:22.75#ibcon#read 6, iclass 27, count 0 2006.218.08:13:22.75#ibcon#end of sib2, iclass 27, count 0 2006.218.08:13:22.75#ibcon#*after write, iclass 27, count 0 2006.218.08:13:22.75#ibcon#*before return 0, iclass 27, count 0 2006.218.08:13:22.75#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.218.08:13:22.75#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.218.08:13:22.75#ibcon#about to clear, iclass 27 cls_cnt 0 2006.218.08:13:22.75#ibcon#cleared, iclass 27 cls_cnt 0 2006.218.08:13:22.75$vc4f8/vbbw=wide 2006.218.08:13:22.75#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.218.08:13:22.75#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.218.08:13:22.75#ibcon#ireg 8 cls_cnt 0 2006.218.08:13:22.75#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.218.08:13:22.82#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.218.08:13:22.82#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.218.08:13:22.82#ibcon#enter wrdev, iclass 29, count 0 2006.218.08:13:22.82#ibcon#first serial, iclass 29, count 0 2006.218.08:13:22.82#ibcon#enter sib2, iclass 29, count 0 2006.218.08:13:22.82#ibcon#flushed, iclass 29, count 0 2006.218.08:13:22.82#ibcon#about to write, iclass 29, count 0 2006.218.08:13:22.82#ibcon#wrote, iclass 29, count 0 2006.218.08:13:22.82#ibcon#about to read 3, iclass 29, count 0 2006.218.08:13:22.84#ibcon#read 3, iclass 29, count 0 2006.218.08:13:22.84#ibcon#about to read 4, iclass 29, count 0 2006.218.08:13:22.84#ibcon#read 4, iclass 29, count 0 2006.218.08:13:22.84#ibcon#about to read 5, iclass 29, count 0 2006.218.08:13:22.84#ibcon#read 5, iclass 29, count 0 2006.218.08:13:22.84#ibcon#about to read 6, iclass 29, count 0 2006.218.08:13:22.84#ibcon#read 6, iclass 29, count 0 2006.218.08:13:22.84#ibcon#end of sib2, iclass 29, count 0 2006.218.08:13:22.84#ibcon#*mode == 0, iclass 29, count 0 2006.218.08:13:22.84#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.218.08:13:22.84#ibcon#[27=BW32\r\n] 2006.218.08:13:22.84#ibcon#*before write, iclass 29, count 0 2006.218.08:13:22.84#ibcon#enter sib2, iclass 29, count 0 2006.218.08:13:22.84#ibcon#flushed, iclass 29, count 0 2006.218.08:13:22.84#ibcon#about to write, iclass 29, count 0 2006.218.08:13:22.84#ibcon#wrote, iclass 29, count 0 2006.218.08:13:22.84#ibcon#about to read 3, iclass 29, count 0 2006.218.08:13:22.87#ibcon#read 3, iclass 29, count 0 2006.218.08:13:22.87#ibcon#about to read 4, iclass 29, count 0 2006.218.08:13:22.87#ibcon#read 4, iclass 29, count 0 2006.218.08:13:22.87#ibcon#about to read 5, iclass 29, count 0 2006.218.08:13:22.87#ibcon#read 5, iclass 29, count 0 2006.218.08:13:22.87#ibcon#about to read 6, iclass 29, count 0 2006.218.08:13:22.87#ibcon#read 6, iclass 29, count 0 2006.218.08:13:22.87#ibcon#end of sib2, iclass 29, count 0 2006.218.08:13:22.87#ibcon#*after write, iclass 29, count 0 2006.218.08:13:22.87#ibcon#*before return 0, iclass 29, count 0 2006.218.08:13:22.87#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.218.08:13:22.87#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.218.08:13:22.87#ibcon#about to clear, iclass 29 cls_cnt 0 2006.218.08:13:22.87#ibcon#cleared, iclass 29 cls_cnt 0 2006.218.08:13:22.87$4f8m12a/ifd4f 2006.218.08:13:22.87$ifd4f/lo= 2006.218.08:13:22.87$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.218.08:13:22.87$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.218.08:13:22.87$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.218.08:13:22.87$ifd4f/patch= 2006.218.08:13:22.87$ifd4f/patch=lo1,a1,a2,a3,a4 2006.218.08:13:22.87$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.218.08:13:22.87$ifd4f/patch=lo3,a5,a6,a7,a8 2006.218.08:13:22.87$4f8m12a/"form=m,16.000,1:2 2006.218.08:13:22.87$4f8m12a/"tpicd 2006.218.08:13:22.87$4f8m12a/echo=off 2006.218.08:13:22.87$4f8m12a/xlog=off 2006.218.08:13:22.87:!2006.218.08:13:50 2006.218.08:13:31.14#trakl#Source acquired 2006.218.08:13:32.14#flagr#flagr/antenna,acquired 2006.218.08:13:50.00:preob 2006.218.08:13:51.14/onsource/TRACKING 2006.218.08:13:51.14:!2006.218.08:14:00 2006.218.08:14:00.00:data_valid=on 2006.218.08:14:00.00:midob 2006.218.08:14:00.14/onsource/TRACKING 2006.218.08:14:00.14/wx/30.84,1007.6,74 2006.218.08:14:00.34/cable/+6.3845E-03 2006.218.08:14:01.43/va/01,05,usb,yes,32,33 2006.218.08:14:01.43/va/02,04,usb,yes,30,31 2006.218.08:14:01.43/va/03,04,usb,yes,28,28 2006.218.08:14:01.43/va/04,04,usb,yes,31,33 2006.218.08:14:01.43/va/05,07,usb,yes,33,35 2006.218.08:14:01.43/va/06,06,usb,yes,32,32 2006.218.08:14:01.43/va/07,06,usb,yes,33,33 2006.218.08:14:01.43/va/08,07,usb,yes,31,31 2006.218.08:14:01.66/valo/01,532.99,yes,locked 2006.218.08:14:01.66/valo/02,572.99,yes,locked 2006.218.08:14:01.66/valo/03,672.99,yes,locked 2006.218.08:14:01.66/valo/04,832.99,yes,locked 2006.218.08:14:01.66/valo/05,652.99,yes,locked 2006.218.08:14:01.66/valo/06,772.99,yes,locked 2006.218.08:14:01.66/valo/07,832.99,yes,locked 2006.218.08:14:01.66/valo/08,852.99,yes,locked 2006.218.08:14:02.75/vb/01,04,usb,yes,30,29 2006.218.08:14:02.75/vb/02,04,usb,yes,32,33 2006.218.08:14:02.75/vb/03,04,usb,yes,29,32 2006.218.08:14:02.75/vb/04,04,usb,yes,29,29 2006.218.08:14:02.75/vb/05,04,usb,yes,28,32 2006.218.08:14:02.75/vb/06,04,usb,yes,29,31 2006.218.08:14:02.75/vb/07,04,usb,yes,31,31 2006.218.08:14:02.75/vb/08,04,usb,yes,28,32 2006.218.08:14:02.99/vblo/01,632.99,yes,locked 2006.218.08:14:02.99/vblo/02,640.99,yes,locked 2006.218.08:14:02.99/vblo/03,656.99,yes,locked 2006.218.08:14:02.99/vblo/04,712.99,yes,locked 2006.218.08:14:02.99/vblo/05,744.99,yes,locked 2006.218.08:14:02.99/vblo/06,752.99,yes,locked 2006.218.08:14:02.99/vblo/07,734.99,yes,locked 2006.218.08:14:02.99/vblo/08,744.99,yes,locked 2006.218.08:14:03.14/vabw/8 2006.218.08:14:03.29/vbbw/8 2006.218.08:14:03.38/xfe/off,on,15.0 2006.218.08:14:03.77/ifatt/23,28,28,28 2006.218.08:14:04.08/fmout-gps/S +4.62E-07 2006.218.08:14:04.15:!2006.218.08:15:00 2006.218.08:15:00.01:data_valid=off 2006.218.08:15:00.01:postob 2006.218.08:15:00.09/cable/+6.3847E-03 2006.218.08:15:00.10/wx/30.82,1007.6,74 2006.218.08:15:01.07/fmout-gps/S +4.60E-07 2006.218.08:15:01.07:scan_name=218-0815,k06218,60 2006.218.08:15:01.07:source=1417+385,141946.61,382148.5,2000.0,cw 2006.218.08:15:01.14#flagr#flagr/antenna,new-source 2006.218.08:15:02.14:checkk5 2006.218.08:15:02.51/chk_autoobs//k5ts1/ autoobs is running! 2006.218.08:15:02.89/chk_autoobs//k5ts2/ autoobs is running! 2006.218.08:15:03.26/chk_autoobs//k5ts3/ autoobs is running! 2006.218.08:15:03.63/chk_autoobs//k5ts4/ autoobs is running! 2006.218.08:15:04.00/chk_obsdata//k5ts1/T2180814??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.08:15:04.36/chk_obsdata//k5ts2/T2180814??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.08:15:04.73/chk_obsdata//k5ts3/T2180814??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.08:15:05.11/chk_obsdata//k5ts4/T2180814??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.08:15:05.81/k5log//k5ts1_log_newline 2006.218.08:15:06.51/k5log//k5ts2_log_newline 2006.218.08:15:07.21/k5log//k5ts3_log_newline 2006.218.08:15:07.91/k5log//k5ts4_log_newline 2006.218.08:15:07.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.218.08:15:07.93:4f8m12a=2 2006.218.08:15:07.93$4f8m12a/echo=on 2006.218.08:15:07.93$4f8m12a/pcalon 2006.218.08:15:07.93$pcalon/"no phase cal control is implemented here 2006.218.08:15:07.93$4f8m12a/"tpicd=stop 2006.218.08:15:07.93$4f8m12a/vc4f8 2006.218.08:15:07.93$vc4f8/valo=1,532.99 2006.218.08:15:07.94#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.218.08:15:07.94#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.218.08:15:07.94#ibcon#ireg 17 cls_cnt 0 2006.218.08:15:07.94#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.218.08:15:07.94#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.218.08:15:07.94#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.218.08:15:07.94#ibcon#enter wrdev, iclass 36, count 0 2006.218.08:15:07.94#ibcon#first serial, iclass 36, count 0 2006.218.08:15:07.94#ibcon#enter sib2, iclass 36, count 0 2006.218.08:15:07.94#ibcon#flushed, iclass 36, count 0 2006.218.08:15:07.94#ibcon#about to write, iclass 36, count 0 2006.218.08:15:07.94#ibcon#wrote, iclass 36, count 0 2006.218.08:15:07.94#ibcon#about to read 3, iclass 36, count 0 2006.218.08:15:07.98#ibcon#read 3, iclass 36, count 0 2006.218.08:15:07.98#ibcon#about to read 4, iclass 36, count 0 2006.218.08:15:07.98#ibcon#read 4, iclass 36, count 0 2006.218.08:15:07.98#ibcon#about to read 5, iclass 36, count 0 2006.218.08:15:07.98#ibcon#read 5, iclass 36, count 0 2006.218.08:15:07.98#ibcon#about to read 6, iclass 36, count 0 2006.218.08:15:07.98#ibcon#read 6, iclass 36, count 0 2006.218.08:15:07.98#ibcon#end of sib2, iclass 36, count 0 2006.218.08:15:07.98#ibcon#*mode == 0, iclass 36, count 0 2006.218.08:15:07.98#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.218.08:15:07.98#ibcon#[26=FRQ=01,532.99\r\n] 2006.218.08:15:07.98#ibcon#*before write, iclass 36, count 0 2006.218.08:15:07.98#ibcon#enter sib2, iclass 36, count 0 2006.218.08:15:07.98#ibcon#flushed, iclass 36, count 0 2006.218.08:15:07.98#ibcon#about to write, iclass 36, count 0 2006.218.08:15:07.98#ibcon#wrote, iclass 36, count 0 2006.218.08:15:07.98#ibcon#about to read 3, iclass 36, count 0 2006.218.08:15:08.02#ibcon#read 3, iclass 36, count 0 2006.218.08:15:08.02#ibcon#about to read 4, iclass 36, count 0 2006.218.08:15:08.02#ibcon#read 4, iclass 36, count 0 2006.218.08:15:08.02#ibcon#about to read 5, iclass 36, count 0 2006.218.08:15:08.02#ibcon#read 5, iclass 36, count 0 2006.218.08:15:08.02#ibcon#about to read 6, iclass 36, count 0 2006.218.08:15:08.02#ibcon#read 6, iclass 36, count 0 2006.218.08:15:08.02#ibcon#end of sib2, iclass 36, count 0 2006.218.08:15:08.02#ibcon#*after write, iclass 36, count 0 2006.218.08:15:08.02#ibcon#*before return 0, iclass 36, count 0 2006.218.08:15:08.02#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.218.08:15:08.02#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.218.08:15:08.02#ibcon#about to clear, iclass 36 cls_cnt 0 2006.218.08:15:08.02#ibcon#cleared, iclass 36 cls_cnt 0 2006.218.08:15:08.02$vc4f8/va=1,5 2006.218.08:15:08.02#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.218.08:15:08.02#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.218.08:15:08.02#ibcon#ireg 11 cls_cnt 2 2006.218.08:15:08.02#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.218.08:15:08.02#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.218.08:15:08.02#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.218.08:15:08.02#ibcon#enter wrdev, iclass 38, count 2 2006.218.08:15:08.02#ibcon#first serial, iclass 38, count 2 2006.218.08:15:08.02#ibcon#enter sib2, iclass 38, count 2 2006.218.08:15:08.02#ibcon#flushed, iclass 38, count 2 2006.218.08:15:08.02#ibcon#about to write, iclass 38, count 2 2006.218.08:15:08.02#ibcon#wrote, iclass 38, count 2 2006.218.08:15:08.02#ibcon#about to read 3, iclass 38, count 2 2006.218.08:15:08.04#ibcon#read 3, iclass 38, count 2 2006.218.08:15:08.04#ibcon#about to read 4, iclass 38, count 2 2006.218.08:15:08.04#ibcon#read 4, iclass 38, count 2 2006.218.08:15:08.04#ibcon#about to read 5, iclass 38, count 2 2006.218.08:15:08.04#ibcon#read 5, iclass 38, count 2 2006.218.08:15:08.04#ibcon#about to read 6, iclass 38, count 2 2006.218.08:15:08.04#ibcon#read 6, iclass 38, count 2 2006.218.08:15:08.04#ibcon#end of sib2, iclass 38, count 2 2006.218.08:15:08.04#ibcon#*mode == 0, iclass 38, count 2 2006.218.08:15:08.04#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.218.08:15:08.04#ibcon#[25=AT01-05\r\n] 2006.218.08:15:08.04#ibcon#*before write, iclass 38, count 2 2006.218.08:15:08.04#ibcon#enter sib2, iclass 38, count 2 2006.218.08:15:08.04#ibcon#flushed, iclass 38, count 2 2006.218.08:15:08.04#ibcon#about to write, iclass 38, count 2 2006.218.08:15:08.04#ibcon#wrote, iclass 38, count 2 2006.218.08:15:08.04#ibcon#about to read 3, iclass 38, count 2 2006.218.08:15:08.07#ibcon#read 3, iclass 38, count 2 2006.218.08:15:08.07#ibcon#about to read 4, iclass 38, count 2 2006.218.08:15:08.07#ibcon#read 4, iclass 38, count 2 2006.218.08:15:08.07#ibcon#about to read 5, iclass 38, count 2 2006.218.08:15:08.07#ibcon#read 5, iclass 38, count 2 2006.218.08:15:08.07#ibcon#about to read 6, iclass 38, count 2 2006.218.08:15:08.07#ibcon#read 6, iclass 38, count 2 2006.218.08:15:08.07#ibcon#end of sib2, iclass 38, count 2 2006.218.08:15:08.07#ibcon#*after write, iclass 38, count 2 2006.218.08:15:08.07#ibcon#*before return 0, iclass 38, count 2 2006.218.08:15:08.07#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.218.08:15:08.07#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.218.08:15:08.07#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.218.08:15:08.07#ibcon#ireg 7 cls_cnt 0 2006.218.08:15:08.07#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.218.08:15:08.19#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.218.08:15:08.19#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.218.08:15:08.19#ibcon#enter wrdev, iclass 38, count 0 2006.218.08:15:08.19#ibcon#first serial, iclass 38, count 0 2006.218.08:15:08.19#ibcon#enter sib2, iclass 38, count 0 2006.218.08:15:08.19#ibcon#flushed, iclass 38, count 0 2006.218.08:15:08.19#ibcon#about to write, iclass 38, count 0 2006.218.08:15:08.19#ibcon#wrote, iclass 38, count 0 2006.218.08:15:08.19#ibcon#about to read 3, iclass 38, count 0 2006.218.08:15:08.21#ibcon#read 3, iclass 38, count 0 2006.218.08:15:08.21#ibcon#about to read 4, iclass 38, count 0 2006.218.08:15:08.21#ibcon#read 4, iclass 38, count 0 2006.218.08:15:08.21#ibcon#about to read 5, iclass 38, count 0 2006.218.08:15:08.21#ibcon#read 5, iclass 38, count 0 2006.218.08:15:08.21#ibcon#about to read 6, iclass 38, count 0 2006.218.08:15:08.21#ibcon#read 6, iclass 38, count 0 2006.218.08:15:08.21#ibcon#end of sib2, iclass 38, count 0 2006.218.08:15:08.21#ibcon#*mode == 0, iclass 38, count 0 2006.218.08:15:08.21#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.218.08:15:08.21#ibcon#[25=USB\r\n] 2006.218.08:15:08.21#ibcon#*before write, iclass 38, count 0 2006.218.08:15:08.21#ibcon#enter sib2, iclass 38, count 0 2006.218.08:15:08.21#ibcon#flushed, iclass 38, count 0 2006.218.08:15:08.21#ibcon#about to write, iclass 38, count 0 2006.218.08:15:08.21#ibcon#wrote, iclass 38, count 0 2006.218.08:15:08.21#ibcon#about to read 3, iclass 38, count 0 2006.218.08:15:08.24#ibcon#read 3, iclass 38, count 0 2006.218.08:15:08.24#ibcon#about to read 4, iclass 38, count 0 2006.218.08:15:08.24#ibcon#read 4, iclass 38, count 0 2006.218.08:15:08.24#ibcon#about to read 5, iclass 38, count 0 2006.218.08:15:08.24#ibcon#read 5, iclass 38, count 0 2006.218.08:15:08.24#ibcon#about to read 6, iclass 38, count 0 2006.218.08:15:08.24#ibcon#read 6, iclass 38, count 0 2006.218.08:15:08.24#ibcon#end of sib2, iclass 38, count 0 2006.218.08:15:08.24#ibcon#*after write, iclass 38, count 0 2006.218.08:15:08.24#ibcon#*before return 0, iclass 38, count 0 2006.218.08:15:08.24#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.218.08:15:08.24#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.218.08:15:08.24#ibcon#about to clear, iclass 38 cls_cnt 0 2006.218.08:15:08.24#ibcon#cleared, iclass 38 cls_cnt 0 2006.218.08:15:08.24$vc4f8/valo=2,572.99 2006.218.08:15:08.24#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.218.08:15:08.24#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.218.08:15:08.24#ibcon#ireg 17 cls_cnt 0 2006.218.08:15:08.24#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.218.08:15:08.24#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.218.08:15:08.24#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.218.08:15:08.24#ibcon#enter wrdev, iclass 40, count 0 2006.218.08:15:08.24#ibcon#first serial, iclass 40, count 0 2006.218.08:15:08.24#ibcon#enter sib2, iclass 40, count 0 2006.218.08:15:08.24#ibcon#flushed, iclass 40, count 0 2006.218.08:15:08.24#ibcon#about to write, iclass 40, count 0 2006.218.08:15:08.24#ibcon#wrote, iclass 40, count 0 2006.218.08:15:08.24#ibcon#about to read 3, iclass 40, count 0 2006.218.08:15:08.26#ibcon#read 3, iclass 40, count 0 2006.218.08:15:08.26#ibcon#about to read 4, iclass 40, count 0 2006.218.08:15:08.26#ibcon#read 4, iclass 40, count 0 2006.218.08:15:08.26#ibcon#about to read 5, iclass 40, count 0 2006.218.08:15:08.26#ibcon#read 5, iclass 40, count 0 2006.218.08:15:08.26#ibcon#about to read 6, iclass 40, count 0 2006.218.08:15:08.26#ibcon#read 6, iclass 40, count 0 2006.218.08:15:08.26#ibcon#end of sib2, iclass 40, count 0 2006.218.08:15:08.26#ibcon#*mode == 0, iclass 40, count 0 2006.218.08:15:08.26#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.218.08:15:08.26#ibcon#[26=FRQ=02,572.99\r\n] 2006.218.08:15:08.26#ibcon#*before write, iclass 40, count 0 2006.218.08:15:08.26#ibcon#enter sib2, iclass 40, count 0 2006.218.08:15:08.26#ibcon#flushed, iclass 40, count 0 2006.218.08:15:08.26#ibcon#about to write, iclass 40, count 0 2006.218.08:15:08.26#ibcon#wrote, iclass 40, count 0 2006.218.08:15:08.26#ibcon#about to read 3, iclass 40, count 0 2006.218.08:15:08.30#ibcon#read 3, iclass 40, count 0 2006.218.08:15:08.30#ibcon#about to read 4, iclass 40, count 0 2006.218.08:15:08.30#ibcon#read 4, iclass 40, count 0 2006.218.08:15:08.30#ibcon#about to read 5, iclass 40, count 0 2006.218.08:15:08.30#ibcon#read 5, iclass 40, count 0 2006.218.08:15:08.30#ibcon#about to read 6, iclass 40, count 0 2006.218.08:15:08.30#ibcon#read 6, iclass 40, count 0 2006.218.08:15:08.30#ibcon#end of sib2, iclass 40, count 0 2006.218.08:15:08.30#ibcon#*after write, iclass 40, count 0 2006.218.08:15:08.30#ibcon#*before return 0, iclass 40, count 0 2006.218.08:15:08.30#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.218.08:15:08.30#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.218.08:15:08.30#ibcon#about to clear, iclass 40 cls_cnt 0 2006.218.08:15:08.30#ibcon#cleared, iclass 40 cls_cnt 0 2006.218.08:15:08.30$vc4f8/va=2,4 2006.218.08:15:08.30#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.218.08:15:08.30#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.218.08:15:08.30#ibcon#ireg 11 cls_cnt 2 2006.218.08:15:08.30#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.218.08:15:08.36#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.218.08:15:08.36#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.218.08:15:08.36#ibcon#enter wrdev, iclass 4, count 2 2006.218.08:15:08.36#ibcon#first serial, iclass 4, count 2 2006.218.08:15:08.36#ibcon#enter sib2, iclass 4, count 2 2006.218.08:15:08.36#ibcon#flushed, iclass 4, count 2 2006.218.08:15:08.36#ibcon#about to write, iclass 4, count 2 2006.218.08:15:08.36#ibcon#wrote, iclass 4, count 2 2006.218.08:15:08.36#ibcon#about to read 3, iclass 4, count 2 2006.218.08:15:08.38#ibcon#read 3, iclass 4, count 2 2006.218.08:15:08.38#ibcon#about to read 4, iclass 4, count 2 2006.218.08:15:08.38#ibcon#read 4, iclass 4, count 2 2006.218.08:15:08.38#ibcon#about to read 5, iclass 4, count 2 2006.218.08:15:08.38#ibcon#read 5, iclass 4, count 2 2006.218.08:15:08.38#ibcon#about to read 6, iclass 4, count 2 2006.218.08:15:08.38#ibcon#read 6, iclass 4, count 2 2006.218.08:15:08.38#ibcon#end of sib2, iclass 4, count 2 2006.218.08:15:08.38#ibcon#*mode == 0, iclass 4, count 2 2006.218.08:15:08.38#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.218.08:15:08.38#ibcon#[25=AT02-04\r\n] 2006.218.08:15:08.38#ibcon#*before write, iclass 4, count 2 2006.218.08:15:08.38#ibcon#enter sib2, iclass 4, count 2 2006.218.08:15:08.38#ibcon#flushed, iclass 4, count 2 2006.218.08:15:08.38#ibcon#about to write, iclass 4, count 2 2006.218.08:15:08.38#ibcon#wrote, iclass 4, count 2 2006.218.08:15:08.38#ibcon#about to read 3, iclass 4, count 2 2006.218.08:15:08.41#ibcon#read 3, iclass 4, count 2 2006.218.08:15:08.41#ibcon#about to read 4, iclass 4, count 2 2006.218.08:15:08.41#ibcon#read 4, iclass 4, count 2 2006.218.08:15:08.41#ibcon#about to read 5, iclass 4, count 2 2006.218.08:15:08.41#ibcon#read 5, iclass 4, count 2 2006.218.08:15:08.41#ibcon#about to read 6, iclass 4, count 2 2006.218.08:15:08.41#ibcon#read 6, iclass 4, count 2 2006.218.08:15:08.41#ibcon#end of sib2, iclass 4, count 2 2006.218.08:15:08.41#ibcon#*after write, iclass 4, count 2 2006.218.08:15:08.41#ibcon#*before return 0, iclass 4, count 2 2006.218.08:15:08.41#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.218.08:15:08.41#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.218.08:15:08.41#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.218.08:15:08.41#ibcon#ireg 7 cls_cnt 0 2006.218.08:15:08.41#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.218.08:15:08.53#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.218.08:15:08.53#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.218.08:15:08.53#ibcon#enter wrdev, iclass 4, count 0 2006.218.08:15:08.53#ibcon#first serial, iclass 4, count 0 2006.218.08:15:08.53#ibcon#enter sib2, iclass 4, count 0 2006.218.08:15:08.53#ibcon#flushed, iclass 4, count 0 2006.218.08:15:08.53#ibcon#about to write, iclass 4, count 0 2006.218.08:15:08.53#ibcon#wrote, iclass 4, count 0 2006.218.08:15:08.53#ibcon#about to read 3, iclass 4, count 0 2006.218.08:15:08.55#ibcon#read 3, iclass 4, count 0 2006.218.08:15:08.55#ibcon#about to read 4, iclass 4, count 0 2006.218.08:15:08.55#ibcon#read 4, iclass 4, count 0 2006.218.08:15:08.55#ibcon#about to read 5, iclass 4, count 0 2006.218.08:15:08.55#ibcon#read 5, iclass 4, count 0 2006.218.08:15:08.55#ibcon#about to read 6, iclass 4, count 0 2006.218.08:15:08.55#ibcon#read 6, iclass 4, count 0 2006.218.08:15:08.55#ibcon#end of sib2, iclass 4, count 0 2006.218.08:15:08.55#ibcon#*mode == 0, iclass 4, count 0 2006.218.08:15:08.55#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.218.08:15:08.55#ibcon#[25=USB\r\n] 2006.218.08:15:08.55#ibcon#*before write, iclass 4, count 0 2006.218.08:15:08.55#ibcon#enter sib2, iclass 4, count 0 2006.218.08:15:08.55#ibcon#flushed, iclass 4, count 0 2006.218.08:15:08.55#ibcon#about to write, iclass 4, count 0 2006.218.08:15:08.55#ibcon#wrote, iclass 4, count 0 2006.218.08:15:08.55#ibcon#about to read 3, iclass 4, count 0 2006.218.08:15:08.58#ibcon#read 3, iclass 4, count 0 2006.218.08:15:08.58#ibcon#about to read 4, iclass 4, count 0 2006.218.08:15:08.58#ibcon#read 4, iclass 4, count 0 2006.218.08:15:08.58#ibcon#about to read 5, iclass 4, count 0 2006.218.08:15:08.58#ibcon#read 5, iclass 4, count 0 2006.218.08:15:08.58#ibcon#about to read 6, iclass 4, count 0 2006.218.08:15:08.58#ibcon#read 6, iclass 4, count 0 2006.218.08:15:08.58#ibcon#end of sib2, iclass 4, count 0 2006.218.08:15:08.58#ibcon#*after write, iclass 4, count 0 2006.218.08:15:08.58#ibcon#*before return 0, iclass 4, count 0 2006.218.08:15:08.58#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.218.08:15:08.58#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.218.08:15:08.58#ibcon#about to clear, iclass 4 cls_cnt 0 2006.218.08:15:08.58#ibcon#cleared, iclass 4 cls_cnt 0 2006.218.08:15:08.58$vc4f8/valo=3,672.99 2006.218.08:15:08.58#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.218.08:15:08.58#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.218.08:15:08.58#ibcon#ireg 17 cls_cnt 0 2006.218.08:15:08.58#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.218.08:15:08.58#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.218.08:15:08.58#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.218.08:15:08.58#ibcon#enter wrdev, iclass 6, count 0 2006.218.08:15:08.58#ibcon#first serial, iclass 6, count 0 2006.218.08:15:08.58#ibcon#enter sib2, iclass 6, count 0 2006.218.08:15:08.58#ibcon#flushed, iclass 6, count 0 2006.218.08:15:08.58#ibcon#about to write, iclass 6, count 0 2006.218.08:15:08.58#ibcon#wrote, iclass 6, count 0 2006.218.08:15:08.58#ibcon#about to read 3, iclass 6, count 0 2006.218.08:15:08.60#ibcon#read 3, iclass 6, count 0 2006.218.08:15:08.60#ibcon#about to read 4, iclass 6, count 0 2006.218.08:15:08.60#ibcon#read 4, iclass 6, count 0 2006.218.08:15:08.60#ibcon#about to read 5, iclass 6, count 0 2006.218.08:15:08.60#ibcon#read 5, iclass 6, count 0 2006.218.08:15:08.60#ibcon#about to read 6, iclass 6, count 0 2006.218.08:15:08.60#ibcon#read 6, iclass 6, count 0 2006.218.08:15:08.60#ibcon#end of sib2, iclass 6, count 0 2006.218.08:15:08.60#ibcon#*mode == 0, iclass 6, count 0 2006.218.08:15:08.60#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.218.08:15:08.60#ibcon#[26=FRQ=03,672.99\r\n] 2006.218.08:15:08.60#ibcon#*before write, iclass 6, count 0 2006.218.08:15:08.60#ibcon#enter sib2, iclass 6, count 0 2006.218.08:15:08.60#ibcon#flushed, iclass 6, count 0 2006.218.08:15:08.60#ibcon#about to write, iclass 6, count 0 2006.218.08:15:08.60#ibcon#wrote, iclass 6, count 0 2006.218.08:15:08.60#ibcon#about to read 3, iclass 6, count 0 2006.218.08:15:08.64#ibcon#read 3, iclass 6, count 0 2006.218.08:15:08.64#ibcon#about to read 4, iclass 6, count 0 2006.218.08:15:08.64#ibcon#read 4, iclass 6, count 0 2006.218.08:15:08.64#ibcon#about to read 5, iclass 6, count 0 2006.218.08:15:08.64#ibcon#read 5, iclass 6, count 0 2006.218.08:15:08.64#ibcon#about to read 6, iclass 6, count 0 2006.218.08:15:08.64#ibcon#read 6, iclass 6, count 0 2006.218.08:15:08.64#ibcon#end of sib2, iclass 6, count 0 2006.218.08:15:08.64#ibcon#*after write, iclass 6, count 0 2006.218.08:15:08.64#ibcon#*before return 0, iclass 6, count 0 2006.218.08:15:08.64#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.218.08:15:08.64#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.218.08:15:08.64#ibcon#about to clear, iclass 6 cls_cnt 0 2006.218.08:15:08.64#ibcon#cleared, iclass 6 cls_cnt 0 2006.218.08:15:08.64$vc4f8/va=3,4 2006.218.08:15:08.64#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.218.08:15:08.64#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.218.08:15:08.64#ibcon#ireg 11 cls_cnt 2 2006.218.08:15:08.64#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.218.08:15:08.70#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.218.08:15:08.70#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.218.08:15:08.70#ibcon#enter wrdev, iclass 10, count 2 2006.218.08:15:08.70#ibcon#first serial, iclass 10, count 2 2006.218.08:15:08.70#ibcon#enter sib2, iclass 10, count 2 2006.218.08:15:08.70#ibcon#flushed, iclass 10, count 2 2006.218.08:15:08.70#ibcon#about to write, iclass 10, count 2 2006.218.08:15:08.70#ibcon#wrote, iclass 10, count 2 2006.218.08:15:08.70#ibcon#about to read 3, iclass 10, count 2 2006.218.08:15:08.72#ibcon#read 3, iclass 10, count 2 2006.218.08:15:08.72#ibcon#about to read 4, iclass 10, count 2 2006.218.08:15:08.72#ibcon#read 4, iclass 10, count 2 2006.218.08:15:08.72#ibcon#about to read 5, iclass 10, count 2 2006.218.08:15:08.72#ibcon#read 5, iclass 10, count 2 2006.218.08:15:08.72#ibcon#about to read 6, iclass 10, count 2 2006.218.08:15:08.72#ibcon#read 6, iclass 10, count 2 2006.218.08:15:08.72#ibcon#end of sib2, iclass 10, count 2 2006.218.08:15:08.72#ibcon#*mode == 0, iclass 10, count 2 2006.218.08:15:08.72#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.218.08:15:08.72#ibcon#[25=AT03-04\r\n] 2006.218.08:15:08.72#ibcon#*before write, iclass 10, count 2 2006.218.08:15:08.72#ibcon#enter sib2, iclass 10, count 2 2006.218.08:15:08.72#ibcon#flushed, iclass 10, count 2 2006.218.08:15:08.72#ibcon#about to write, iclass 10, count 2 2006.218.08:15:08.72#ibcon#wrote, iclass 10, count 2 2006.218.08:15:08.72#ibcon#about to read 3, iclass 10, count 2 2006.218.08:15:08.75#ibcon#read 3, iclass 10, count 2 2006.218.08:15:08.75#ibcon#about to read 4, iclass 10, count 2 2006.218.08:15:08.75#ibcon#read 4, iclass 10, count 2 2006.218.08:15:08.75#ibcon#about to read 5, iclass 10, count 2 2006.218.08:15:08.75#ibcon#read 5, iclass 10, count 2 2006.218.08:15:08.75#ibcon#about to read 6, iclass 10, count 2 2006.218.08:15:08.75#ibcon#read 6, iclass 10, count 2 2006.218.08:15:08.75#ibcon#end of sib2, iclass 10, count 2 2006.218.08:15:08.75#ibcon#*after write, iclass 10, count 2 2006.218.08:15:08.75#ibcon#*before return 0, iclass 10, count 2 2006.218.08:15:08.75#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.218.08:15:08.75#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.218.08:15:08.75#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.218.08:15:08.75#ibcon#ireg 7 cls_cnt 0 2006.218.08:15:08.75#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.218.08:15:08.87#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.218.08:15:08.87#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.218.08:15:08.87#ibcon#enter wrdev, iclass 10, count 0 2006.218.08:15:08.87#ibcon#first serial, iclass 10, count 0 2006.218.08:15:08.87#ibcon#enter sib2, iclass 10, count 0 2006.218.08:15:08.87#ibcon#flushed, iclass 10, count 0 2006.218.08:15:08.87#ibcon#about to write, iclass 10, count 0 2006.218.08:15:08.87#ibcon#wrote, iclass 10, count 0 2006.218.08:15:08.87#ibcon#about to read 3, iclass 10, count 0 2006.218.08:15:08.89#ibcon#read 3, iclass 10, count 0 2006.218.08:15:08.89#ibcon#about to read 4, iclass 10, count 0 2006.218.08:15:08.89#ibcon#read 4, iclass 10, count 0 2006.218.08:15:08.89#ibcon#about to read 5, iclass 10, count 0 2006.218.08:15:08.89#ibcon#read 5, iclass 10, count 0 2006.218.08:15:08.89#ibcon#about to read 6, iclass 10, count 0 2006.218.08:15:08.89#ibcon#read 6, iclass 10, count 0 2006.218.08:15:08.89#ibcon#end of sib2, iclass 10, count 0 2006.218.08:15:08.89#ibcon#*mode == 0, iclass 10, count 0 2006.218.08:15:08.89#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.218.08:15:08.89#ibcon#[25=USB\r\n] 2006.218.08:15:08.89#ibcon#*before write, iclass 10, count 0 2006.218.08:15:08.89#ibcon#enter sib2, iclass 10, count 0 2006.218.08:15:08.89#ibcon#flushed, iclass 10, count 0 2006.218.08:15:08.89#ibcon#about to write, iclass 10, count 0 2006.218.08:15:08.89#ibcon#wrote, iclass 10, count 0 2006.218.08:15:08.89#ibcon#about to read 3, iclass 10, count 0 2006.218.08:15:08.92#ibcon#read 3, iclass 10, count 0 2006.218.08:15:08.92#ibcon#about to read 4, iclass 10, count 0 2006.218.08:15:08.92#ibcon#read 4, iclass 10, count 0 2006.218.08:15:08.92#ibcon#about to read 5, iclass 10, count 0 2006.218.08:15:08.92#ibcon#read 5, iclass 10, count 0 2006.218.08:15:08.92#ibcon#about to read 6, iclass 10, count 0 2006.218.08:15:08.92#ibcon#read 6, iclass 10, count 0 2006.218.08:15:08.92#ibcon#end of sib2, iclass 10, count 0 2006.218.08:15:08.92#ibcon#*after write, iclass 10, count 0 2006.218.08:15:08.92#ibcon#*before return 0, iclass 10, count 0 2006.218.08:15:08.92#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.218.08:15:08.92#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.218.08:15:08.92#ibcon#about to clear, iclass 10 cls_cnt 0 2006.218.08:15:08.92#ibcon#cleared, iclass 10 cls_cnt 0 2006.218.08:15:08.92$vc4f8/valo=4,832.99 2006.218.08:15:08.92#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.218.08:15:08.92#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.218.08:15:08.92#ibcon#ireg 17 cls_cnt 0 2006.218.08:15:08.92#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.218.08:15:08.92#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.218.08:15:08.92#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.218.08:15:08.92#ibcon#enter wrdev, iclass 12, count 0 2006.218.08:15:08.92#ibcon#first serial, iclass 12, count 0 2006.218.08:15:08.92#ibcon#enter sib2, iclass 12, count 0 2006.218.08:15:08.92#ibcon#flushed, iclass 12, count 0 2006.218.08:15:08.92#ibcon#about to write, iclass 12, count 0 2006.218.08:15:08.92#ibcon#wrote, iclass 12, count 0 2006.218.08:15:08.92#ibcon#about to read 3, iclass 12, count 0 2006.218.08:15:08.94#ibcon#read 3, iclass 12, count 0 2006.218.08:15:08.94#ibcon#about to read 4, iclass 12, count 0 2006.218.08:15:08.94#ibcon#read 4, iclass 12, count 0 2006.218.08:15:08.94#ibcon#about to read 5, iclass 12, count 0 2006.218.08:15:08.94#ibcon#read 5, iclass 12, count 0 2006.218.08:15:08.94#ibcon#about to read 6, iclass 12, count 0 2006.218.08:15:08.94#ibcon#read 6, iclass 12, count 0 2006.218.08:15:08.94#ibcon#end of sib2, iclass 12, count 0 2006.218.08:15:08.94#ibcon#*mode == 0, iclass 12, count 0 2006.218.08:15:08.94#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.218.08:15:08.94#ibcon#[26=FRQ=04,832.99\r\n] 2006.218.08:15:08.94#ibcon#*before write, iclass 12, count 0 2006.218.08:15:08.94#ibcon#enter sib2, iclass 12, count 0 2006.218.08:15:08.94#ibcon#flushed, iclass 12, count 0 2006.218.08:15:08.94#ibcon#about to write, iclass 12, count 0 2006.218.08:15:08.94#ibcon#wrote, iclass 12, count 0 2006.218.08:15:08.94#ibcon#about to read 3, iclass 12, count 0 2006.218.08:15:08.98#ibcon#read 3, iclass 12, count 0 2006.218.08:15:08.98#ibcon#about to read 4, iclass 12, count 0 2006.218.08:15:08.98#ibcon#read 4, iclass 12, count 0 2006.218.08:15:08.98#ibcon#about to read 5, iclass 12, count 0 2006.218.08:15:08.98#ibcon#read 5, iclass 12, count 0 2006.218.08:15:08.98#ibcon#about to read 6, iclass 12, count 0 2006.218.08:15:08.98#ibcon#read 6, iclass 12, count 0 2006.218.08:15:08.98#ibcon#end of sib2, iclass 12, count 0 2006.218.08:15:08.98#ibcon#*after write, iclass 12, count 0 2006.218.08:15:08.98#ibcon#*before return 0, iclass 12, count 0 2006.218.08:15:08.98#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.218.08:15:08.98#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.218.08:15:08.98#ibcon#about to clear, iclass 12 cls_cnt 0 2006.218.08:15:08.98#ibcon#cleared, iclass 12 cls_cnt 0 2006.218.08:15:08.98$vc4f8/va=4,4 2006.218.08:15:08.98#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.218.08:15:08.98#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.218.08:15:08.98#ibcon#ireg 11 cls_cnt 2 2006.218.08:15:08.98#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.218.08:15:09.04#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.218.08:15:09.04#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.218.08:15:09.04#ibcon#enter wrdev, iclass 14, count 2 2006.218.08:15:09.04#ibcon#first serial, iclass 14, count 2 2006.218.08:15:09.04#ibcon#enter sib2, iclass 14, count 2 2006.218.08:15:09.04#ibcon#flushed, iclass 14, count 2 2006.218.08:15:09.04#ibcon#about to write, iclass 14, count 2 2006.218.08:15:09.04#ibcon#wrote, iclass 14, count 2 2006.218.08:15:09.04#ibcon#about to read 3, iclass 14, count 2 2006.218.08:15:09.06#ibcon#read 3, iclass 14, count 2 2006.218.08:15:09.06#ibcon#about to read 4, iclass 14, count 2 2006.218.08:15:09.06#ibcon#read 4, iclass 14, count 2 2006.218.08:15:09.06#ibcon#about to read 5, iclass 14, count 2 2006.218.08:15:09.06#ibcon#read 5, iclass 14, count 2 2006.218.08:15:09.06#ibcon#about to read 6, iclass 14, count 2 2006.218.08:15:09.06#ibcon#read 6, iclass 14, count 2 2006.218.08:15:09.06#ibcon#end of sib2, iclass 14, count 2 2006.218.08:15:09.06#ibcon#*mode == 0, iclass 14, count 2 2006.218.08:15:09.06#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.218.08:15:09.06#ibcon#[25=AT04-04\r\n] 2006.218.08:15:09.06#ibcon#*before write, iclass 14, count 2 2006.218.08:15:09.06#ibcon#enter sib2, iclass 14, count 2 2006.218.08:15:09.06#ibcon#flushed, iclass 14, count 2 2006.218.08:15:09.06#ibcon#about to write, iclass 14, count 2 2006.218.08:15:09.06#ibcon#wrote, iclass 14, count 2 2006.218.08:15:09.06#ibcon#about to read 3, iclass 14, count 2 2006.218.08:15:09.09#ibcon#read 3, iclass 14, count 2 2006.218.08:15:09.09#ibcon#about to read 4, iclass 14, count 2 2006.218.08:15:09.09#ibcon#read 4, iclass 14, count 2 2006.218.08:15:09.09#ibcon#about to read 5, iclass 14, count 2 2006.218.08:15:09.09#ibcon#read 5, iclass 14, count 2 2006.218.08:15:09.09#ibcon#about to read 6, iclass 14, count 2 2006.218.08:15:09.09#ibcon#read 6, iclass 14, count 2 2006.218.08:15:09.09#ibcon#end of sib2, iclass 14, count 2 2006.218.08:15:09.09#ibcon#*after write, iclass 14, count 2 2006.218.08:15:09.09#ibcon#*before return 0, iclass 14, count 2 2006.218.08:15:09.09#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.218.08:15:09.09#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.218.08:15:09.09#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.218.08:15:09.09#ibcon#ireg 7 cls_cnt 0 2006.218.08:15:09.09#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.218.08:15:09.21#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.218.08:15:09.21#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.218.08:15:09.21#ibcon#enter wrdev, iclass 14, count 0 2006.218.08:15:09.21#ibcon#first serial, iclass 14, count 0 2006.218.08:15:09.21#ibcon#enter sib2, iclass 14, count 0 2006.218.08:15:09.21#ibcon#flushed, iclass 14, count 0 2006.218.08:15:09.21#ibcon#about to write, iclass 14, count 0 2006.218.08:15:09.21#ibcon#wrote, iclass 14, count 0 2006.218.08:15:09.21#ibcon#about to read 3, iclass 14, count 0 2006.218.08:15:09.23#ibcon#read 3, iclass 14, count 0 2006.218.08:15:09.23#ibcon#about to read 4, iclass 14, count 0 2006.218.08:15:09.23#ibcon#read 4, iclass 14, count 0 2006.218.08:15:09.23#ibcon#about to read 5, iclass 14, count 0 2006.218.08:15:09.23#ibcon#read 5, iclass 14, count 0 2006.218.08:15:09.23#ibcon#about to read 6, iclass 14, count 0 2006.218.08:15:09.23#ibcon#read 6, iclass 14, count 0 2006.218.08:15:09.23#ibcon#end of sib2, iclass 14, count 0 2006.218.08:15:09.23#ibcon#*mode == 0, iclass 14, count 0 2006.218.08:15:09.23#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.218.08:15:09.23#ibcon#[25=USB\r\n] 2006.218.08:15:09.23#ibcon#*before write, iclass 14, count 0 2006.218.08:15:09.23#ibcon#enter sib2, iclass 14, count 0 2006.218.08:15:09.23#ibcon#flushed, iclass 14, count 0 2006.218.08:15:09.23#ibcon#about to write, iclass 14, count 0 2006.218.08:15:09.23#ibcon#wrote, iclass 14, count 0 2006.218.08:15:09.23#ibcon#about to read 3, iclass 14, count 0 2006.218.08:15:09.26#ibcon#read 3, iclass 14, count 0 2006.218.08:15:09.26#ibcon#about to read 4, iclass 14, count 0 2006.218.08:15:09.26#ibcon#read 4, iclass 14, count 0 2006.218.08:15:09.26#ibcon#about to read 5, iclass 14, count 0 2006.218.08:15:09.26#ibcon#read 5, iclass 14, count 0 2006.218.08:15:09.26#ibcon#about to read 6, iclass 14, count 0 2006.218.08:15:09.26#ibcon#read 6, iclass 14, count 0 2006.218.08:15:09.26#ibcon#end of sib2, iclass 14, count 0 2006.218.08:15:09.26#ibcon#*after write, iclass 14, count 0 2006.218.08:15:09.26#ibcon#*before return 0, iclass 14, count 0 2006.218.08:15:09.26#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.218.08:15:09.26#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.218.08:15:09.26#ibcon#about to clear, iclass 14 cls_cnt 0 2006.218.08:15:09.26#ibcon#cleared, iclass 14 cls_cnt 0 2006.218.08:15:09.26$vc4f8/valo=5,652.99 2006.218.08:15:09.26#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.218.08:15:09.26#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.218.08:15:09.26#ibcon#ireg 17 cls_cnt 0 2006.218.08:15:09.26#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.218.08:15:09.26#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.218.08:15:09.26#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.218.08:15:09.26#ibcon#enter wrdev, iclass 16, count 0 2006.218.08:15:09.26#ibcon#first serial, iclass 16, count 0 2006.218.08:15:09.26#ibcon#enter sib2, iclass 16, count 0 2006.218.08:15:09.26#ibcon#flushed, iclass 16, count 0 2006.218.08:15:09.26#ibcon#about to write, iclass 16, count 0 2006.218.08:15:09.26#ibcon#wrote, iclass 16, count 0 2006.218.08:15:09.26#ibcon#about to read 3, iclass 16, count 0 2006.218.08:15:09.28#ibcon#read 3, iclass 16, count 0 2006.218.08:15:09.28#ibcon#about to read 4, iclass 16, count 0 2006.218.08:15:09.28#ibcon#read 4, iclass 16, count 0 2006.218.08:15:09.28#ibcon#about to read 5, iclass 16, count 0 2006.218.08:15:09.28#ibcon#read 5, iclass 16, count 0 2006.218.08:15:09.28#ibcon#about to read 6, iclass 16, count 0 2006.218.08:15:09.28#ibcon#read 6, iclass 16, count 0 2006.218.08:15:09.28#ibcon#end of sib2, iclass 16, count 0 2006.218.08:15:09.28#ibcon#*mode == 0, iclass 16, count 0 2006.218.08:15:09.28#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.218.08:15:09.28#ibcon#[26=FRQ=05,652.99\r\n] 2006.218.08:15:09.28#ibcon#*before write, iclass 16, count 0 2006.218.08:15:09.28#ibcon#enter sib2, iclass 16, count 0 2006.218.08:15:09.28#ibcon#flushed, iclass 16, count 0 2006.218.08:15:09.28#ibcon#about to write, iclass 16, count 0 2006.218.08:15:09.28#ibcon#wrote, iclass 16, count 0 2006.218.08:15:09.28#ibcon#about to read 3, iclass 16, count 0 2006.218.08:15:09.32#ibcon#read 3, iclass 16, count 0 2006.218.08:15:09.32#ibcon#about to read 4, iclass 16, count 0 2006.218.08:15:09.32#ibcon#read 4, iclass 16, count 0 2006.218.08:15:09.32#ibcon#about to read 5, iclass 16, count 0 2006.218.08:15:09.32#ibcon#read 5, iclass 16, count 0 2006.218.08:15:09.32#ibcon#about to read 6, iclass 16, count 0 2006.218.08:15:09.32#ibcon#read 6, iclass 16, count 0 2006.218.08:15:09.32#ibcon#end of sib2, iclass 16, count 0 2006.218.08:15:09.32#ibcon#*after write, iclass 16, count 0 2006.218.08:15:09.32#ibcon#*before return 0, iclass 16, count 0 2006.218.08:15:09.32#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.218.08:15:09.32#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.218.08:15:09.32#ibcon#about to clear, iclass 16 cls_cnt 0 2006.218.08:15:09.32#ibcon#cleared, iclass 16 cls_cnt 0 2006.218.08:15:09.32$vc4f8/va=5,7 2006.218.08:15:09.32#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.218.08:15:09.32#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.218.08:15:09.32#ibcon#ireg 11 cls_cnt 2 2006.218.08:15:09.32#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.218.08:15:09.38#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.218.08:15:09.38#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.218.08:15:09.38#ibcon#enter wrdev, iclass 18, count 2 2006.218.08:15:09.38#ibcon#first serial, iclass 18, count 2 2006.218.08:15:09.38#ibcon#enter sib2, iclass 18, count 2 2006.218.08:15:09.38#ibcon#flushed, iclass 18, count 2 2006.218.08:15:09.38#ibcon#about to write, iclass 18, count 2 2006.218.08:15:09.38#ibcon#wrote, iclass 18, count 2 2006.218.08:15:09.38#ibcon#about to read 3, iclass 18, count 2 2006.218.08:15:09.40#ibcon#read 3, iclass 18, count 2 2006.218.08:15:09.40#ibcon#about to read 4, iclass 18, count 2 2006.218.08:15:09.40#ibcon#read 4, iclass 18, count 2 2006.218.08:15:09.40#ibcon#about to read 5, iclass 18, count 2 2006.218.08:15:09.40#ibcon#read 5, iclass 18, count 2 2006.218.08:15:09.40#ibcon#about to read 6, iclass 18, count 2 2006.218.08:15:09.40#ibcon#read 6, iclass 18, count 2 2006.218.08:15:09.40#ibcon#end of sib2, iclass 18, count 2 2006.218.08:15:09.40#ibcon#*mode == 0, iclass 18, count 2 2006.218.08:15:09.40#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.218.08:15:09.40#ibcon#[25=AT05-07\r\n] 2006.218.08:15:09.40#ibcon#*before write, iclass 18, count 2 2006.218.08:15:09.40#ibcon#enter sib2, iclass 18, count 2 2006.218.08:15:09.40#ibcon#flushed, iclass 18, count 2 2006.218.08:15:09.40#ibcon#about to write, iclass 18, count 2 2006.218.08:15:09.40#ibcon#wrote, iclass 18, count 2 2006.218.08:15:09.40#ibcon#about to read 3, iclass 18, count 2 2006.218.08:15:09.43#ibcon#read 3, iclass 18, count 2 2006.218.08:15:09.43#ibcon#about to read 4, iclass 18, count 2 2006.218.08:15:09.43#ibcon#read 4, iclass 18, count 2 2006.218.08:15:09.43#ibcon#about to read 5, iclass 18, count 2 2006.218.08:15:09.43#ibcon#read 5, iclass 18, count 2 2006.218.08:15:09.43#ibcon#about to read 6, iclass 18, count 2 2006.218.08:15:09.43#ibcon#read 6, iclass 18, count 2 2006.218.08:15:09.43#ibcon#end of sib2, iclass 18, count 2 2006.218.08:15:09.43#ibcon#*after write, iclass 18, count 2 2006.218.08:15:09.43#ibcon#*before return 0, iclass 18, count 2 2006.218.08:15:09.43#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.218.08:15:09.43#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.218.08:15:09.43#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.218.08:15:09.43#ibcon#ireg 7 cls_cnt 0 2006.218.08:15:09.43#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.218.08:15:09.55#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.218.08:15:09.55#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.218.08:15:09.55#ibcon#enter wrdev, iclass 18, count 0 2006.218.08:15:09.55#ibcon#first serial, iclass 18, count 0 2006.218.08:15:09.55#ibcon#enter sib2, iclass 18, count 0 2006.218.08:15:09.55#ibcon#flushed, iclass 18, count 0 2006.218.08:15:09.55#ibcon#about to write, iclass 18, count 0 2006.218.08:15:09.55#ibcon#wrote, iclass 18, count 0 2006.218.08:15:09.55#ibcon#about to read 3, iclass 18, count 0 2006.218.08:15:09.57#ibcon#read 3, iclass 18, count 0 2006.218.08:15:09.57#ibcon#about to read 4, iclass 18, count 0 2006.218.08:15:09.57#ibcon#read 4, iclass 18, count 0 2006.218.08:15:09.57#ibcon#about to read 5, iclass 18, count 0 2006.218.08:15:09.57#ibcon#read 5, iclass 18, count 0 2006.218.08:15:09.57#ibcon#about to read 6, iclass 18, count 0 2006.218.08:15:09.57#ibcon#read 6, iclass 18, count 0 2006.218.08:15:09.57#ibcon#end of sib2, iclass 18, count 0 2006.218.08:15:09.57#ibcon#*mode == 0, iclass 18, count 0 2006.218.08:15:09.57#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.218.08:15:09.57#ibcon#[25=USB\r\n] 2006.218.08:15:09.57#ibcon#*before write, iclass 18, count 0 2006.218.08:15:09.57#ibcon#enter sib2, iclass 18, count 0 2006.218.08:15:09.57#ibcon#flushed, iclass 18, count 0 2006.218.08:15:09.57#ibcon#about to write, iclass 18, count 0 2006.218.08:15:09.57#ibcon#wrote, iclass 18, count 0 2006.218.08:15:09.57#ibcon#about to read 3, iclass 18, count 0 2006.218.08:15:09.60#ibcon#read 3, iclass 18, count 0 2006.218.08:15:09.60#ibcon#about to read 4, iclass 18, count 0 2006.218.08:15:09.60#ibcon#read 4, iclass 18, count 0 2006.218.08:15:09.60#ibcon#about to read 5, iclass 18, count 0 2006.218.08:15:09.60#ibcon#read 5, iclass 18, count 0 2006.218.08:15:09.60#ibcon#about to read 6, iclass 18, count 0 2006.218.08:15:09.60#ibcon#read 6, iclass 18, count 0 2006.218.08:15:09.60#ibcon#end of sib2, iclass 18, count 0 2006.218.08:15:09.60#ibcon#*after write, iclass 18, count 0 2006.218.08:15:09.60#ibcon#*before return 0, iclass 18, count 0 2006.218.08:15:09.60#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.218.08:15:09.60#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.218.08:15:09.60#ibcon#about to clear, iclass 18 cls_cnt 0 2006.218.08:15:09.60#ibcon#cleared, iclass 18 cls_cnt 0 2006.218.08:15:09.60$vc4f8/valo=6,772.99 2006.218.08:15:09.60#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.218.08:15:09.60#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.218.08:15:09.60#ibcon#ireg 17 cls_cnt 0 2006.218.08:15:09.60#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.218.08:15:09.60#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.218.08:15:09.60#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.218.08:15:09.60#ibcon#enter wrdev, iclass 20, count 0 2006.218.08:15:09.60#ibcon#first serial, iclass 20, count 0 2006.218.08:15:09.60#ibcon#enter sib2, iclass 20, count 0 2006.218.08:15:09.60#ibcon#flushed, iclass 20, count 0 2006.218.08:15:09.60#ibcon#about to write, iclass 20, count 0 2006.218.08:15:09.60#ibcon#wrote, iclass 20, count 0 2006.218.08:15:09.60#ibcon#about to read 3, iclass 20, count 0 2006.218.08:15:09.62#ibcon#read 3, iclass 20, count 0 2006.218.08:15:09.62#ibcon#about to read 4, iclass 20, count 0 2006.218.08:15:09.62#ibcon#read 4, iclass 20, count 0 2006.218.08:15:09.62#ibcon#about to read 5, iclass 20, count 0 2006.218.08:15:09.62#ibcon#read 5, iclass 20, count 0 2006.218.08:15:09.62#ibcon#about to read 6, iclass 20, count 0 2006.218.08:15:09.62#ibcon#read 6, iclass 20, count 0 2006.218.08:15:09.62#ibcon#end of sib2, iclass 20, count 0 2006.218.08:15:09.62#ibcon#*mode == 0, iclass 20, count 0 2006.218.08:15:09.62#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.218.08:15:09.62#ibcon#[26=FRQ=06,772.99\r\n] 2006.218.08:15:09.62#ibcon#*before write, iclass 20, count 0 2006.218.08:15:09.62#ibcon#enter sib2, iclass 20, count 0 2006.218.08:15:09.62#ibcon#flushed, iclass 20, count 0 2006.218.08:15:09.62#ibcon#about to write, iclass 20, count 0 2006.218.08:15:09.62#ibcon#wrote, iclass 20, count 0 2006.218.08:15:09.62#ibcon#about to read 3, iclass 20, count 0 2006.218.08:15:09.66#ibcon#read 3, iclass 20, count 0 2006.218.08:15:09.66#ibcon#about to read 4, iclass 20, count 0 2006.218.08:15:09.66#ibcon#read 4, iclass 20, count 0 2006.218.08:15:09.66#ibcon#about to read 5, iclass 20, count 0 2006.218.08:15:09.66#ibcon#read 5, iclass 20, count 0 2006.218.08:15:09.66#ibcon#about to read 6, iclass 20, count 0 2006.218.08:15:09.66#ibcon#read 6, iclass 20, count 0 2006.218.08:15:09.66#ibcon#end of sib2, iclass 20, count 0 2006.218.08:15:09.66#ibcon#*after write, iclass 20, count 0 2006.218.08:15:09.66#ibcon#*before return 0, iclass 20, count 0 2006.218.08:15:09.66#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.218.08:15:09.66#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.218.08:15:09.66#ibcon#about to clear, iclass 20 cls_cnt 0 2006.218.08:15:09.66#ibcon#cleared, iclass 20 cls_cnt 0 2006.218.08:15:09.66$vc4f8/va=6,6 2006.218.08:15:09.66#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.218.08:15:09.66#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.218.08:15:09.66#ibcon#ireg 11 cls_cnt 2 2006.218.08:15:09.66#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.218.08:15:09.67#abcon#<5=/06 4.2 7.4 30.82 741007.6\r\n> 2006.218.08:15:09.69#abcon#{5=INTERFACE CLEAR} 2006.218.08:15:09.72#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.218.08:15:09.72#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.218.08:15:09.72#ibcon#enter wrdev, iclass 23, count 2 2006.218.08:15:09.72#ibcon#first serial, iclass 23, count 2 2006.218.08:15:09.72#ibcon#enter sib2, iclass 23, count 2 2006.218.08:15:09.72#ibcon#flushed, iclass 23, count 2 2006.218.08:15:09.72#ibcon#about to write, iclass 23, count 2 2006.218.08:15:09.72#ibcon#wrote, iclass 23, count 2 2006.218.08:15:09.72#ibcon#about to read 3, iclass 23, count 2 2006.218.08:15:09.74#ibcon#read 3, iclass 23, count 2 2006.218.08:15:09.74#ibcon#about to read 4, iclass 23, count 2 2006.218.08:15:09.74#ibcon#read 4, iclass 23, count 2 2006.218.08:15:09.74#ibcon#about to read 5, iclass 23, count 2 2006.218.08:15:09.74#ibcon#read 5, iclass 23, count 2 2006.218.08:15:09.74#ibcon#about to read 6, iclass 23, count 2 2006.218.08:15:09.74#ibcon#read 6, iclass 23, count 2 2006.218.08:15:09.74#ibcon#end of sib2, iclass 23, count 2 2006.218.08:15:09.74#ibcon#*mode == 0, iclass 23, count 2 2006.218.08:15:09.74#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.218.08:15:09.74#ibcon#[25=AT06-06\r\n] 2006.218.08:15:09.74#ibcon#*before write, iclass 23, count 2 2006.218.08:15:09.74#ibcon#enter sib2, iclass 23, count 2 2006.218.08:15:09.74#ibcon#flushed, iclass 23, count 2 2006.218.08:15:09.74#ibcon#about to write, iclass 23, count 2 2006.218.08:15:09.74#ibcon#wrote, iclass 23, count 2 2006.218.08:15:09.74#ibcon#about to read 3, iclass 23, count 2 2006.218.08:15:09.75#abcon#[5=S1D000X0/0*\r\n] 2006.218.08:15:09.77#ibcon#read 3, iclass 23, count 2 2006.218.08:15:09.77#ibcon#about to read 4, iclass 23, count 2 2006.218.08:15:09.77#ibcon#read 4, iclass 23, count 2 2006.218.08:15:09.77#ibcon#about to read 5, iclass 23, count 2 2006.218.08:15:09.77#ibcon#read 5, iclass 23, count 2 2006.218.08:15:09.77#ibcon#about to read 6, iclass 23, count 2 2006.218.08:15:09.77#ibcon#read 6, iclass 23, count 2 2006.218.08:15:09.77#ibcon#end of sib2, iclass 23, count 2 2006.218.08:15:09.77#ibcon#*after write, iclass 23, count 2 2006.218.08:15:09.77#ibcon#*before return 0, iclass 23, count 2 2006.218.08:15:09.77#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.218.08:15:09.77#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.218.08:15:09.77#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.218.08:15:09.77#ibcon#ireg 7 cls_cnt 0 2006.218.08:15:09.77#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.218.08:15:09.89#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.218.08:15:09.89#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.218.08:15:09.89#ibcon#enter wrdev, iclass 23, count 0 2006.218.08:15:09.89#ibcon#first serial, iclass 23, count 0 2006.218.08:15:09.89#ibcon#enter sib2, iclass 23, count 0 2006.218.08:15:09.89#ibcon#flushed, iclass 23, count 0 2006.218.08:15:09.89#ibcon#about to write, iclass 23, count 0 2006.218.08:15:09.89#ibcon#wrote, iclass 23, count 0 2006.218.08:15:09.89#ibcon#about to read 3, iclass 23, count 0 2006.218.08:15:09.91#ibcon#read 3, iclass 23, count 0 2006.218.08:15:09.91#ibcon#about to read 4, iclass 23, count 0 2006.218.08:15:09.91#ibcon#read 4, iclass 23, count 0 2006.218.08:15:09.91#ibcon#about to read 5, iclass 23, count 0 2006.218.08:15:09.91#ibcon#read 5, iclass 23, count 0 2006.218.08:15:09.91#ibcon#about to read 6, iclass 23, count 0 2006.218.08:15:09.91#ibcon#read 6, iclass 23, count 0 2006.218.08:15:09.91#ibcon#end of sib2, iclass 23, count 0 2006.218.08:15:09.91#ibcon#*mode == 0, iclass 23, count 0 2006.218.08:15:09.91#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.218.08:15:09.91#ibcon#[25=USB\r\n] 2006.218.08:15:09.91#ibcon#*before write, iclass 23, count 0 2006.218.08:15:09.91#ibcon#enter sib2, iclass 23, count 0 2006.218.08:15:09.91#ibcon#flushed, iclass 23, count 0 2006.218.08:15:09.91#ibcon#about to write, iclass 23, count 0 2006.218.08:15:09.91#ibcon#wrote, iclass 23, count 0 2006.218.08:15:09.91#ibcon#about to read 3, iclass 23, count 0 2006.218.08:15:09.94#ibcon#read 3, iclass 23, count 0 2006.218.08:15:09.94#ibcon#about to read 4, iclass 23, count 0 2006.218.08:15:09.94#ibcon#read 4, iclass 23, count 0 2006.218.08:15:09.94#ibcon#about to read 5, iclass 23, count 0 2006.218.08:15:09.94#ibcon#read 5, iclass 23, count 0 2006.218.08:15:09.94#ibcon#about to read 6, iclass 23, count 0 2006.218.08:15:09.94#ibcon#read 6, iclass 23, count 0 2006.218.08:15:09.94#ibcon#end of sib2, iclass 23, count 0 2006.218.08:15:09.94#ibcon#*after write, iclass 23, count 0 2006.218.08:15:09.94#ibcon#*before return 0, iclass 23, count 0 2006.218.08:15:09.94#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.218.08:15:09.94#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.218.08:15:09.94#ibcon#about to clear, iclass 23 cls_cnt 0 2006.218.08:15:09.94#ibcon#cleared, iclass 23 cls_cnt 0 2006.218.08:15:09.94$vc4f8/valo=7,832.99 2006.218.08:15:09.94#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.218.08:15:09.94#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.218.08:15:09.94#ibcon#ireg 17 cls_cnt 0 2006.218.08:15:09.94#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.218.08:15:09.94#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.218.08:15:09.94#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.218.08:15:09.94#ibcon#enter wrdev, iclass 28, count 0 2006.218.08:15:09.94#ibcon#first serial, iclass 28, count 0 2006.218.08:15:09.94#ibcon#enter sib2, iclass 28, count 0 2006.218.08:15:09.94#ibcon#flushed, iclass 28, count 0 2006.218.08:15:09.94#ibcon#about to write, iclass 28, count 0 2006.218.08:15:09.94#ibcon#wrote, iclass 28, count 0 2006.218.08:15:09.94#ibcon#about to read 3, iclass 28, count 0 2006.218.08:15:09.96#ibcon#read 3, iclass 28, count 0 2006.218.08:15:09.96#ibcon#about to read 4, iclass 28, count 0 2006.218.08:15:09.96#ibcon#read 4, iclass 28, count 0 2006.218.08:15:09.96#ibcon#about to read 5, iclass 28, count 0 2006.218.08:15:09.96#ibcon#read 5, iclass 28, count 0 2006.218.08:15:09.96#ibcon#about to read 6, iclass 28, count 0 2006.218.08:15:09.96#ibcon#read 6, iclass 28, count 0 2006.218.08:15:09.96#ibcon#end of sib2, iclass 28, count 0 2006.218.08:15:09.96#ibcon#*mode == 0, iclass 28, count 0 2006.218.08:15:09.96#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.218.08:15:09.96#ibcon#[26=FRQ=07,832.99\r\n] 2006.218.08:15:09.96#ibcon#*before write, iclass 28, count 0 2006.218.08:15:09.96#ibcon#enter sib2, iclass 28, count 0 2006.218.08:15:09.96#ibcon#flushed, iclass 28, count 0 2006.218.08:15:09.96#ibcon#about to write, iclass 28, count 0 2006.218.08:15:09.96#ibcon#wrote, iclass 28, count 0 2006.218.08:15:09.96#ibcon#about to read 3, iclass 28, count 0 2006.218.08:15:10.00#ibcon#read 3, iclass 28, count 0 2006.218.08:15:10.00#ibcon#about to read 4, iclass 28, count 0 2006.218.08:15:10.00#ibcon#read 4, iclass 28, count 0 2006.218.08:15:10.00#ibcon#about to read 5, iclass 28, count 0 2006.218.08:15:10.00#ibcon#read 5, iclass 28, count 0 2006.218.08:15:10.00#ibcon#about to read 6, iclass 28, count 0 2006.218.08:15:10.00#ibcon#read 6, iclass 28, count 0 2006.218.08:15:10.00#ibcon#end of sib2, iclass 28, count 0 2006.218.08:15:10.00#ibcon#*after write, iclass 28, count 0 2006.218.08:15:10.00#ibcon#*before return 0, iclass 28, count 0 2006.218.08:15:10.00#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.218.08:15:10.00#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.218.08:15:10.00#ibcon#about to clear, iclass 28 cls_cnt 0 2006.218.08:15:10.00#ibcon#cleared, iclass 28 cls_cnt 0 2006.218.08:15:10.00$vc4f8/va=7,6 2006.218.08:15:10.00#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.218.08:15:10.00#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.218.08:15:10.00#ibcon#ireg 11 cls_cnt 2 2006.218.08:15:10.00#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.218.08:15:10.06#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.218.08:15:10.06#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.218.08:15:10.06#ibcon#enter wrdev, iclass 30, count 2 2006.218.08:15:10.06#ibcon#first serial, iclass 30, count 2 2006.218.08:15:10.06#ibcon#enter sib2, iclass 30, count 2 2006.218.08:15:10.06#ibcon#flushed, iclass 30, count 2 2006.218.08:15:10.06#ibcon#about to write, iclass 30, count 2 2006.218.08:15:10.06#ibcon#wrote, iclass 30, count 2 2006.218.08:15:10.06#ibcon#about to read 3, iclass 30, count 2 2006.218.08:15:10.08#ibcon#read 3, iclass 30, count 2 2006.218.08:15:10.08#ibcon#about to read 4, iclass 30, count 2 2006.218.08:15:10.08#ibcon#read 4, iclass 30, count 2 2006.218.08:15:10.08#ibcon#about to read 5, iclass 30, count 2 2006.218.08:15:10.08#ibcon#read 5, iclass 30, count 2 2006.218.08:15:10.08#ibcon#about to read 6, iclass 30, count 2 2006.218.08:15:10.08#ibcon#read 6, iclass 30, count 2 2006.218.08:15:10.08#ibcon#end of sib2, iclass 30, count 2 2006.218.08:15:10.08#ibcon#*mode == 0, iclass 30, count 2 2006.218.08:15:10.08#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.218.08:15:10.08#ibcon#[25=AT07-06\r\n] 2006.218.08:15:10.08#ibcon#*before write, iclass 30, count 2 2006.218.08:15:10.08#ibcon#enter sib2, iclass 30, count 2 2006.218.08:15:10.08#ibcon#flushed, iclass 30, count 2 2006.218.08:15:10.08#ibcon#about to write, iclass 30, count 2 2006.218.08:15:10.08#ibcon#wrote, iclass 30, count 2 2006.218.08:15:10.08#ibcon#about to read 3, iclass 30, count 2 2006.218.08:15:10.11#ibcon#read 3, iclass 30, count 2 2006.218.08:15:10.11#ibcon#about to read 4, iclass 30, count 2 2006.218.08:15:10.11#ibcon#read 4, iclass 30, count 2 2006.218.08:15:10.11#ibcon#about to read 5, iclass 30, count 2 2006.218.08:15:10.11#ibcon#read 5, iclass 30, count 2 2006.218.08:15:10.11#ibcon#about to read 6, iclass 30, count 2 2006.218.08:15:10.11#ibcon#read 6, iclass 30, count 2 2006.218.08:15:10.11#ibcon#end of sib2, iclass 30, count 2 2006.218.08:15:10.11#ibcon#*after write, iclass 30, count 2 2006.218.08:15:10.11#ibcon#*before return 0, iclass 30, count 2 2006.218.08:15:10.11#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.218.08:15:10.11#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.218.08:15:10.11#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.218.08:15:10.11#ibcon#ireg 7 cls_cnt 0 2006.218.08:15:10.11#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.218.08:15:10.23#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.218.08:15:10.23#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.218.08:15:10.23#ibcon#enter wrdev, iclass 30, count 0 2006.218.08:15:10.23#ibcon#first serial, iclass 30, count 0 2006.218.08:15:10.23#ibcon#enter sib2, iclass 30, count 0 2006.218.08:15:10.23#ibcon#flushed, iclass 30, count 0 2006.218.08:15:10.23#ibcon#about to write, iclass 30, count 0 2006.218.08:15:10.23#ibcon#wrote, iclass 30, count 0 2006.218.08:15:10.23#ibcon#about to read 3, iclass 30, count 0 2006.218.08:15:10.25#ibcon#read 3, iclass 30, count 0 2006.218.08:15:10.25#ibcon#about to read 4, iclass 30, count 0 2006.218.08:15:10.25#ibcon#read 4, iclass 30, count 0 2006.218.08:15:10.25#ibcon#about to read 5, iclass 30, count 0 2006.218.08:15:10.25#ibcon#read 5, iclass 30, count 0 2006.218.08:15:10.25#ibcon#about to read 6, iclass 30, count 0 2006.218.08:15:10.25#ibcon#read 6, iclass 30, count 0 2006.218.08:15:10.25#ibcon#end of sib2, iclass 30, count 0 2006.218.08:15:10.25#ibcon#*mode == 0, iclass 30, count 0 2006.218.08:15:10.25#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.218.08:15:10.25#ibcon#[25=USB\r\n] 2006.218.08:15:10.25#ibcon#*before write, iclass 30, count 0 2006.218.08:15:10.25#ibcon#enter sib2, iclass 30, count 0 2006.218.08:15:10.25#ibcon#flushed, iclass 30, count 0 2006.218.08:15:10.25#ibcon#about to write, iclass 30, count 0 2006.218.08:15:10.25#ibcon#wrote, iclass 30, count 0 2006.218.08:15:10.25#ibcon#about to read 3, iclass 30, count 0 2006.218.08:15:10.28#ibcon#read 3, iclass 30, count 0 2006.218.08:15:10.28#ibcon#about to read 4, iclass 30, count 0 2006.218.08:15:10.28#ibcon#read 4, iclass 30, count 0 2006.218.08:15:10.28#ibcon#about to read 5, iclass 30, count 0 2006.218.08:15:10.28#ibcon#read 5, iclass 30, count 0 2006.218.08:15:10.28#ibcon#about to read 6, iclass 30, count 0 2006.218.08:15:10.28#ibcon#read 6, iclass 30, count 0 2006.218.08:15:10.28#ibcon#end of sib2, iclass 30, count 0 2006.218.08:15:10.28#ibcon#*after write, iclass 30, count 0 2006.218.08:15:10.28#ibcon#*before return 0, iclass 30, count 0 2006.218.08:15:10.28#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.218.08:15:10.28#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.218.08:15:10.28#ibcon#about to clear, iclass 30 cls_cnt 0 2006.218.08:15:10.28#ibcon#cleared, iclass 30 cls_cnt 0 2006.218.08:15:10.28$vc4f8/valo=8,852.99 2006.218.08:15:10.28#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.218.08:15:10.28#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.218.08:15:10.28#ibcon#ireg 17 cls_cnt 0 2006.218.08:15:10.28#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.218.08:15:10.28#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.218.08:15:10.28#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.218.08:15:10.28#ibcon#enter wrdev, iclass 32, count 0 2006.218.08:15:10.28#ibcon#first serial, iclass 32, count 0 2006.218.08:15:10.28#ibcon#enter sib2, iclass 32, count 0 2006.218.08:15:10.28#ibcon#flushed, iclass 32, count 0 2006.218.08:15:10.28#ibcon#about to write, iclass 32, count 0 2006.218.08:15:10.28#ibcon#wrote, iclass 32, count 0 2006.218.08:15:10.28#ibcon#about to read 3, iclass 32, count 0 2006.218.08:15:10.30#ibcon#read 3, iclass 32, count 0 2006.218.08:15:10.30#ibcon#about to read 4, iclass 32, count 0 2006.218.08:15:10.30#ibcon#read 4, iclass 32, count 0 2006.218.08:15:10.30#ibcon#about to read 5, iclass 32, count 0 2006.218.08:15:10.30#ibcon#read 5, iclass 32, count 0 2006.218.08:15:10.30#ibcon#about to read 6, iclass 32, count 0 2006.218.08:15:10.30#ibcon#read 6, iclass 32, count 0 2006.218.08:15:10.30#ibcon#end of sib2, iclass 32, count 0 2006.218.08:15:10.30#ibcon#*mode == 0, iclass 32, count 0 2006.218.08:15:10.30#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.218.08:15:10.30#ibcon#[26=FRQ=08,852.99\r\n] 2006.218.08:15:10.30#ibcon#*before write, iclass 32, count 0 2006.218.08:15:10.30#ibcon#enter sib2, iclass 32, count 0 2006.218.08:15:10.30#ibcon#flushed, iclass 32, count 0 2006.218.08:15:10.30#ibcon#about to write, iclass 32, count 0 2006.218.08:15:10.30#ibcon#wrote, iclass 32, count 0 2006.218.08:15:10.30#ibcon#about to read 3, iclass 32, count 0 2006.218.08:15:10.35#ibcon#read 3, iclass 32, count 0 2006.218.08:15:10.35#ibcon#about to read 4, iclass 32, count 0 2006.218.08:15:10.35#ibcon#read 4, iclass 32, count 0 2006.218.08:15:10.35#ibcon#about to read 5, iclass 32, count 0 2006.218.08:15:10.35#ibcon#read 5, iclass 32, count 0 2006.218.08:15:10.35#ibcon#about to read 6, iclass 32, count 0 2006.218.08:15:10.35#ibcon#read 6, iclass 32, count 0 2006.218.08:15:10.35#ibcon#end of sib2, iclass 32, count 0 2006.218.08:15:10.35#ibcon#*after write, iclass 32, count 0 2006.218.08:15:10.35#ibcon#*before return 0, iclass 32, count 0 2006.218.08:15:10.35#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.218.08:15:10.35#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.218.08:15:10.35#ibcon#about to clear, iclass 32 cls_cnt 0 2006.218.08:15:10.35#ibcon#cleared, iclass 32 cls_cnt 0 2006.218.08:15:10.35$vc4f8/va=8,7 2006.218.08:15:10.35#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.218.08:15:10.35#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.218.08:15:10.35#ibcon#ireg 11 cls_cnt 2 2006.218.08:15:10.35#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.218.08:15:10.40#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.218.08:15:10.40#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.218.08:15:10.40#ibcon#enter wrdev, iclass 34, count 2 2006.218.08:15:10.40#ibcon#first serial, iclass 34, count 2 2006.218.08:15:10.40#ibcon#enter sib2, iclass 34, count 2 2006.218.08:15:10.40#ibcon#flushed, iclass 34, count 2 2006.218.08:15:10.40#ibcon#about to write, iclass 34, count 2 2006.218.08:15:10.40#ibcon#wrote, iclass 34, count 2 2006.218.08:15:10.40#ibcon#about to read 3, iclass 34, count 2 2006.218.08:15:10.42#ibcon#read 3, iclass 34, count 2 2006.218.08:15:10.42#ibcon#about to read 4, iclass 34, count 2 2006.218.08:15:10.42#ibcon#read 4, iclass 34, count 2 2006.218.08:15:10.42#ibcon#about to read 5, iclass 34, count 2 2006.218.08:15:10.42#ibcon#read 5, iclass 34, count 2 2006.218.08:15:10.42#ibcon#about to read 6, iclass 34, count 2 2006.218.08:15:10.42#ibcon#read 6, iclass 34, count 2 2006.218.08:15:10.42#ibcon#end of sib2, iclass 34, count 2 2006.218.08:15:10.42#ibcon#*mode == 0, iclass 34, count 2 2006.218.08:15:10.42#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.218.08:15:10.42#ibcon#[25=AT08-07\r\n] 2006.218.08:15:10.42#ibcon#*before write, iclass 34, count 2 2006.218.08:15:10.42#ibcon#enter sib2, iclass 34, count 2 2006.218.08:15:10.42#ibcon#flushed, iclass 34, count 2 2006.218.08:15:10.42#ibcon#about to write, iclass 34, count 2 2006.218.08:15:10.42#ibcon#wrote, iclass 34, count 2 2006.218.08:15:10.42#ibcon#about to read 3, iclass 34, count 2 2006.218.08:15:10.45#ibcon#read 3, iclass 34, count 2 2006.218.08:15:10.45#ibcon#about to read 4, iclass 34, count 2 2006.218.08:15:10.45#ibcon#read 4, iclass 34, count 2 2006.218.08:15:10.45#ibcon#about to read 5, iclass 34, count 2 2006.218.08:15:10.45#ibcon#read 5, iclass 34, count 2 2006.218.08:15:10.45#ibcon#about to read 6, iclass 34, count 2 2006.218.08:15:10.45#ibcon#read 6, iclass 34, count 2 2006.218.08:15:10.45#ibcon#end of sib2, iclass 34, count 2 2006.218.08:15:10.45#ibcon#*after write, iclass 34, count 2 2006.218.08:15:10.45#ibcon#*before return 0, iclass 34, count 2 2006.218.08:15:10.45#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.218.08:15:10.45#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.218.08:15:10.45#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.218.08:15:10.45#ibcon#ireg 7 cls_cnt 0 2006.218.08:15:10.45#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.218.08:15:10.57#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.218.08:15:10.57#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.218.08:15:10.57#ibcon#enter wrdev, iclass 34, count 0 2006.218.08:15:10.57#ibcon#first serial, iclass 34, count 0 2006.218.08:15:10.57#ibcon#enter sib2, iclass 34, count 0 2006.218.08:15:10.57#ibcon#flushed, iclass 34, count 0 2006.218.08:15:10.57#ibcon#about to write, iclass 34, count 0 2006.218.08:15:10.57#ibcon#wrote, iclass 34, count 0 2006.218.08:15:10.57#ibcon#about to read 3, iclass 34, count 0 2006.218.08:15:10.59#ibcon#read 3, iclass 34, count 0 2006.218.08:15:10.59#ibcon#about to read 4, iclass 34, count 0 2006.218.08:15:10.59#ibcon#read 4, iclass 34, count 0 2006.218.08:15:10.59#ibcon#about to read 5, iclass 34, count 0 2006.218.08:15:10.59#ibcon#read 5, iclass 34, count 0 2006.218.08:15:10.59#ibcon#about to read 6, iclass 34, count 0 2006.218.08:15:10.59#ibcon#read 6, iclass 34, count 0 2006.218.08:15:10.59#ibcon#end of sib2, iclass 34, count 0 2006.218.08:15:10.59#ibcon#*mode == 0, iclass 34, count 0 2006.218.08:15:10.59#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.218.08:15:10.59#ibcon#[25=USB\r\n] 2006.218.08:15:10.59#ibcon#*before write, iclass 34, count 0 2006.218.08:15:10.59#ibcon#enter sib2, iclass 34, count 0 2006.218.08:15:10.59#ibcon#flushed, iclass 34, count 0 2006.218.08:15:10.59#ibcon#about to write, iclass 34, count 0 2006.218.08:15:10.59#ibcon#wrote, iclass 34, count 0 2006.218.08:15:10.59#ibcon#about to read 3, iclass 34, count 0 2006.218.08:15:10.62#ibcon#read 3, iclass 34, count 0 2006.218.08:15:10.62#ibcon#about to read 4, iclass 34, count 0 2006.218.08:15:10.62#ibcon#read 4, iclass 34, count 0 2006.218.08:15:10.62#ibcon#about to read 5, iclass 34, count 0 2006.218.08:15:10.62#ibcon#read 5, iclass 34, count 0 2006.218.08:15:10.62#ibcon#about to read 6, iclass 34, count 0 2006.218.08:15:10.62#ibcon#read 6, iclass 34, count 0 2006.218.08:15:10.62#ibcon#end of sib2, iclass 34, count 0 2006.218.08:15:10.62#ibcon#*after write, iclass 34, count 0 2006.218.08:15:10.62#ibcon#*before return 0, iclass 34, count 0 2006.218.08:15:10.62#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.218.08:15:10.62#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.218.08:15:10.62#ibcon#about to clear, iclass 34 cls_cnt 0 2006.218.08:15:10.62#ibcon#cleared, iclass 34 cls_cnt 0 2006.218.08:15:10.62$vc4f8/vblo=1,632.99 2006.218.08:15:10.62#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.218.08:15:10.62#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.218.08:15:10.62#ibcon#ireg 17 cls_cnt 0 2006.218.08:15:10.62#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.218.08:15:10.62#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.218.08:15:10.62#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.218.08:15:10.62#ibcon#enter wrdev, iclass 36, count 0 2006.218.08:15:10.62#ibcon#first serial, iclass 36, count 0 2006.218.08:15:10.62#ibcon#enter sib2, iclass 36, count 0 2006.218.08:15:10.62#ibcon#flushed, iclass 36, count 0 2006.218.08:15:10.62#ibcon#about to write, iclass 36, count 0 2006.218.08:15:10.62#ibcon#wrote, iclass 36, count 0 2006.218.08:15:10.62#ibcon#about to read 3, iclass 36, count 0 2006.218.08:15:10.64#ibcon#read 3, iclass 36, count 0 2006.218.08:15:10.64#ibcon#about to read 4, iclass 36, count 0 2006.218.08:15:10.64#ibcon#read 4, iclass 36, count 0 2006.218.08:15:10.64#ibcon#about to read 5, iclass 36, count 0 2006.218.08:15:10.64#ibcon#read 5, iclass 36, count 0 2006.218.08:15:10.64#ibcon#about to read 6, iclass 36, count 0 2006.218.08:15:10.64#ibcon#read 6, iclass 36, count 0 2006.218.08:15:10.64#ibcon#end of sib2, iclass 36, count 0 2006.218.08:15:10.64#ibcon#*mode == 0, iclass 36, count 0 2006.218.08:15:10.64#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.218.08:15:10.64#ibcon#[28=FRQ=01,632.99\r\n] 2006.218.08:15:10.64#ibcon#*before write, iclass 36, count 0 2006.218.08:15:10.64#ibcon#enter sib2, iclass 36, count 0 2006.218.08:15:10.64#ibcon#flushed, iclass 36, count 0 2006.218.08:15:10.64#ibcon#about to write, iclass 36, count 0 2006.218.08:15:10.64#ibcon#wrote, iclass 36, count 0 2006.218.08:15:10.64#ibcon#about to read 3, iclass 36, count 0 2006.218.08:15:10.68#ibcon#read 3, iclass 36, count 0 2006.218.08:15:10.68#ibcon#about to read 4, iclass 36, count 0 2006.218.08:15:10.68#ibcon#read 4, iclass 36, count 0 2006.218.08:15:10.68#ibcon#about to read 5, iclass 36, count 0 2006.218.08:15:10.68#ibcon#read 5, iclass 36, count 0 2006.218.08:15:10.68#ibcon#about to read 6, iclass 36, count 0 2006.218.08:15:10.68#ibcon#read 6, iclass 36, count 0 2006.218.08:15:10.68#ibcon#end of sib2, iclass 36, count 0 2006.218.08:15:10.68#ibcon#*after write, iclass 36, count 0 2006.218.08:15:10.68#ibcon#*before return 0, iclass 36, count 0 2006.218.08:15:10.68#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.218.08:15:10.68#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.218.08:15:10.68#ibcon#about to clear, iclass 36 cls_cnt 0 2006.218.08:15:10.68#ibcon#cleared, iclass 36 cls_cnt 0 2006.218.08:15:10.68$vc4f8/vb=1,4 2006.218.08:15:10.68#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.218.08:15:10.68#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.218.08:15:10.68#ibcon#ireg 11 cls_cnt 2 2006.218.08:15:10.68#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.218.08:15:10.68#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.218.08:15:10.68#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.218.08:15:10.68#ibcon#enter wrdev, iclass 38, count 2 2006.218.08:15:10.68#ibcon#first serial, iclass 38, count 2 2006.218.08:15:10.68#ibcon#enter sib2, iclass 38, count 2 2006.218.08:15:10.68#ibcon#flushed, iclass 38, count 2 2006.218.08:15:10.68#ibcon#about to write, iclass 38, count 2 2006.218.08:15:10.68#ibcon#wrote, iclass 38, count 2 2006.218.08:15:10.68#ibcon#about to read 3, iclass 38, count 2 2006.218.08:15:10.70#ibcon#read 3, iclass 38, count 2 2006.218.08:15:10.70#ibcon#about to read 4, iclass 38, count 2 2006.218.08:15:10.70#ibcon#read 4, iclass 38, count 2 2006.218.08:15:10.70#ibcon#about to read 5, iclass 38, count 2 2006.218.08:15:10.70#ibcon#read 5, iclass 38, count 2 2006.218.08:15:10.70#ibcon#about to read 6, iclass 38, count 2 2006.218.08:15:10.70#ibcon#read 6, iclass 38, count 2 2006.218.08:15:10.70#ibcon#end of sib2, iclass 38, count 2 2006.218.08:15:10.70#ibcon#*mode == 0, iclass 38, count 2 2006.218.08:15:10.70#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.218.08:15:10.70#ibcon#[27=AT01-04\r\n] 2006.218.08:15:10.70#ibcon#*before write, iclass 38, count 2 2006.218.08:15:10.70#ibcon#enter sib2, iclass 38, count 2 2006.218.08:15:10.70#ibcon#flushed, iclass 38, count 2 2006.218.08:15:10.70#ibcon#about to write, iclass 38, count 2 2006.218.08:15:10.70#ibcon#wrote, iclass 38, count 2 2006.218.08:15:10.70#ibcon#about to read 3, iclass 38, count 2 2006.218.08:15:10.73#ibcon#read 3, iclass 38, count 2 2006.218.08:15:10.73#ibcon#about to read 4, iclass 38, count 2 2006.218.08:15:10.73#ibcon#read 4, iclass 38, count 2 2006.218.08:15:10.73#ibcon#about to read 5, iclass 38, count 2 2006.218.08:15:10.73#ibcon#read 5, iclass 38, count 2 2006.218.08:15:10.73#ibcon#about to read 6, iclass 38, count 2 2006.218.08:15:10.73#ibcon#read 6, iclass 38, count 2 2006.218.08:15:10.73#ibcon#end of sib2, iclass 38, count 2 2006.218.08:15:10.73#ibcon#*after write, iclass 38, count 2 2006.218.08:15:10.73#ibcon#*before return 0, iclass 38, count 2 2006.218.08:15:10.73#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.218.08:15:10.73#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.218.08:15:10.73#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.218.08:15:10.73#ibcon#ireg 7 cls_cnt 0 2006.218.08:15:10.73#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.218.08:15:10.85#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.218.08:15:10.85#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.218.08:15:10.85#ibcon#enter wrdev, iclass 38, count 0 2006.218.08:15:10.85#ibcon#first serial, iclass 38, count 0 2006.218.08:15:10.85#ibcon#enter sib2, iclass 38, count 0 2006.218.08:15:10.85#ibcon#flushed, iclass 38, count 0 2006.218.08:15:10.85#ibcon#about to write, iclass 38, count 0 2006.218.08:15:10.85#ibcon#wrote, iclass 38, count 0 2006.218.08:15:10.85#ibcon#about to read 3, iclass 38, count 0 2006.218.08:15:10.87#ibcon#read 3, iclass 38, count 0 2006.218.08:15:10.87#ibcon#about to read 4, iclass 38, count 0 2006.218.08:15:10.87#ibcon#read 4, iclass 38, count 0 2006.218.08:15:10.87#ibcon#about to read 5, iclass 38, count 0 2006.218.08:15:10.87#ibcon#read 5, iclass 38, count 0 2006.218.08:15:10.87#ibcon#about to read 6, iclass 38, count 0 2006.218.08:15:10.87#ibcon#read 6, iclass 38, count 0 2006.218.08:15:10.87#ibcon#end of sib2, iclass 38, count 0 2006.218.08:15:10.87#ibcon#*mode == 0, iclass 38, count 0 2006.218.08:15:10.87#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.218.08:15:10.87#ibcon#[27=USB\r\n] 2006.218.08:15:10.87#ibcon#*before write, iclass 38, count 0 2006.218.08:15:10.87#ibcon#enter sib2, iclass 38, count 0 2006.218.08:15:10.87#ibcon#flushed, iclass 38, count 0 2006.218.08:15:10.87#ibcon#about to write, iclass 38, count 0 2006.218.08:15:10.87#ibcon#wrote, iclass 38, count 0 2006.218.08:15:10.87#ibcon#about to read 3, iclass 38, count 0 2006.218.08:15:10.90#ibcon#read 3, iclass 38, count 0 2006.218.08:15:10.90#ibcon#about to read 4, iclass 38, count 0 2006.218.08:15:10.90#ibcon#read 4, iclass 38, count 0 2006.218.08:15:10.90#ibcon#about to read 5, iclass 38, count 0 2006.218.08:15:10.90#ibcon#read 5, iclass 38, count 0 2006.218.08:15:10.90#ibcon#about to read 6, iclass 38, count 0 2006.218.08:15:10.90#ibcon#read 6, iclass 38, count 0 2006.218.08:15:10.90#ibcon#end of sib2, iclass 38, count 0 2006.218.08:15:10.90#ibcon#*after write, iclass 38, count 0 2006.218.08:15:10.90#ibcon#*before return 0, iclass 38, count 0 2006.218.08:15:10.90#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.218.08:15:10.90#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.218.08:15:10.90#ibcon#about to clear, iclass 38 cls_cnt 0 2006.218.08:15:10.90#ibcon#cleared, iclass 38 cls_cnt 0 2006.218.08:15:10.90$vc4f8/vblo=2,640.99 2006.218.08:15:10.90#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.218.08:15:10.90#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.218.08:15:10.90#ibcon#ireg 17 cls_cnt 0 2006.218.08:15:10.90#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.218.08:15:10.90#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.218.08:15:10.90#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.218.08:15:10.90#ibcon#enter wrdev, iclass 40, count 0 2006.218.08:15:10.90#ibcon#first serial, iclass 40, count 0 2006.218.08:15:10.90#ibcon#enter sib2, iclass 40, count 0 2006.218.08:15:10.90#ibcon#flushed, iclass 40, count 0 2006.218.08:15:10.90#ibcon#about to write, iclass 40, count 0 2006.218.08:15:10.90#ibcon#wrote, iclass 40, count 0 2006.218.08:15:10.90#ibcon#about to read 3, iclass 40, count 0 2006.218.08:15:10.92#ibcon#read 3, iclass 40, count 0 2006.218.08:15:10.92#ibcon#about to read 4, iclass 40, count 0 2006.218.08:15:10.92#ibcon#read 4, iclass 40, count 0 2006.218.08:15:10.92#ibcon#about to read 5, iclass 40, count 0 2006.218.08:15:10.92#ibcon#read 5, iclass 40, count 0 2006.218.08:15:10.92#ibcon#about to read 6, iclass 40, count 0 2006.218.08:15:10.92#ibcon#read 6, iclass 40, count 0 2006.218.08:15:10.92#ibcon#end of sib2, iclass 40, count 0 2006.218.08:15:10.92#ibcon#*mode == 0, iclass 40, count 0 2006.218.08:15:10.92#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.218.08:15:10.92#ibcon#[28=FRQ=02,640.99\r\n] 2006.218.08:15:10.92#ibcon#*before write, iclass 40, count 0 2006.218.08:15:10.92#ibcon#enter sib2, iclass 40, count 0 2006.218.08:15:10.92#ibcon#flushed, iclass 40, count 0 2006.218.08:15:10.92#ibcon#about to write, iclass 40, count 0 2006.218.08:15:10.92#ibcon#wrote, iclass 40, count 0 2006.218.08:15:10.92#ibcon#about to read 3, iclass 40, count 0 2006.218.08:15:10.96#ibcon#read 3, iclass 40, count 0 2006.218.08:15:10.96#ibcon#about to read 4, iclass 40, count 0 2006.218.08:15:10.96#ibcon#read 4, iclass 40, count 0 2006.218.08:15:10.96#ibcon#about to read 5, iclass 40, count 0 2006.218.08:15:10.96#ibcon#read 5, iclass 40, count 0 2006.218.08:15:10.96#ibcon#about to read 6, iclass 40, count 0 2006.218.08:15:10.96#ibcon#read 6, iclass 40, count 0 2006.218.08:15:10.96#ibcon#end of sib2, iclass 40, count 0 2006.218.08:15:10.96#ibcon#*after write, iclass 40, count 0 2006.218.08:15:10.96#ibcon#*before return 0, iclass 40, count 0 2006.218.08:15:10.96#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.218.08:15:10.96#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.218.08:15:10.96#ibcon#about to clear, iclass 40 cls_cnt 0 2006.218.08:15:10.96#ibcon#cleared, iclass 40 cls_cnt 0 2006.218.08:15:10.96$vc4f8/vb=2,4 2006.218.08:15:10.96#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.218.08:15:10.96#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.218.08:15:10.96#ibcon#ireg 11 cls_cnt 2 2006.218.08:15:10.96#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.218.08:15:11.02#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.218.08:15:11.02#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.218.08:15:11.02#ibcon#enter wrdev, iclass 4, count 2 2006.218.08:15:11.02#ibcon#first serial, iclass 4, count 2 2006.218.08:15:11.02#ibcon#enter sib2, iclass 4, count 2 2006.218.08:15:11.02#ibcon#flushed, iclass 4, count 2 2006.218.08:15:11.02#ibcon#about to write, iclass 4, count 2 2006.218.08:15:11.02#ibcon#wrote, iclass 4, count 2 2006.218.08:15:11.02#ibcon#about to read 3, iclass 4, count 2 2006.218.08:15:11.04#ibcon#read 3, iclass 4, count 2 2006.218.08:15:11.04#ibcon#about to read 4, iclass 4, count 2 2006.218.08:15:11.04#ibcon#read 4, iclass 4, count 2 2006.218.08:15:11.04#ibcon#about to read 5, iclass 4, count 2 2006.218.08:15:11.04#ibcon#read 5, iclass 4, count 2 2006.218.08:15:11.04#ibcon#about to read 6, iclass 4, count 2 2006.218.08:15:11.04#ibcon#read 6, iclass 4, count 2 2006.218.08:15:11.04#ibcon#end of sib2, iclass 4, count 2 2006.218.08:15:11.04#ibcon#*mode == 0, iclass 4, count 2 2006.218.08:15:11.04#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.218.08:15:11.04#ibcon#[27=AT02-04\r\n] 2006.218.08:15:11.04#ibcon#*before write, iclass 4, count 2 2006.218.08:15:11.04#ibcon#enter sib2, iclass 4, count 2 2006.218.08:15:11.04#ibcon#flushed, iclass 4, count 2 2006.218.08:15:11.04#ibcon#about to write, iclass 4, count 2 2006.218.08:15:11.04#ibcon#wrote, iclass 4, count 2 2006.218.08:15:11.04#ibcon#about to read 3, iclass 4, count 2 2006.218.08:15:11.07#ibcon#read 3, iclass 4, count 2 2006.218.08:15:11.07#ibcon#about to read 4, iclass 4, count 2 2006.218.08:15:11.07#ibcon#read 4, iclass 4, count 2 2006.218.08:15:11.07#ibcon#about to read 5, iclass 4, count 2 2006.218.08:15:11.07#ibcon#read 5, iclass 4, count 2 2006.218.08:15:11.07#ibcon#about to read 6, iclass 4, count 2 2006.218.08:15:11.07#ibcon#read 6, iclass 4, count 2 2006.218.08:15:11.07#ibcon#end of sib2, iclass 4, count 2 2006.218.08:15:11.07#ibcon#*after write, iclass 4, count 2 2006.218.08:15:11.07#ibcon#*before return 0, iclass 4, count 2 2006.218.08:15:11.07#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.218.08:15:11.07#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.218.08:15:11.07#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.218.08:15:11.07#ibcon#ireg 7 cls_cnt 0 2006.218.08:15:11.07#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.218.08:15:11.19#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.218.08:15:11.19#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.218.08:15:11.19#ibcon#enter wrdev, iclass 4, count 0 2006.218.08:15:11.19#ibcon#first serial, iclass 4, count 0 2006.218.08:15:11.19#ibcon#enter sib2, iclass 4, count 0 2006.218.08:15:11.19#ibcon#flushed, iclass 4, count 0 2006.218.08:15:11.19#ibcon#about to write, iclass 4, count 0 2006.218.08:15:11.19#ibcon#wrote, iclass 4, count 0 2006.218.08:15:11.19#ibcon#about to read 3, iclass 4, count 0 2006.218.08:15:11.22#ibcon#read 3, iclass 4, count 0 2006.218.08:15:11.22#ibcon#about to read 4, iclass 4, count 0 2006.218.08:15:11.22#ibcon#read 4, iclass 4, count 0 2006.218.08:15:11.22#ibcon#about to read 5, iclass 4, count 0 2006.218.08:15:11.22#ibcon#read 5, iclass 4, count 0 2006.218.08:15:11.22#ibcon#about to read 6, iclass 4, count 0 2006.218.08:15:11.22#ibcon#read 6, iclass 4, count 0 2006.218.08:15:11.22#ibcon#end of sib2, iclass 4, count 0 2006.218.08:15:11.22#ibcon#*mode == 0, iclass 4, count 0 2006.218.08:15:11.22#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.218.08:15:11.22#ibcon#[27=USB\r\n] 2006.218.08:15:11.22#ibcon#*before write, iclass 4, count 0 2006.218.08:15:11.22#ibcon#enter sib2, iclass 4, count 0 2006.218.08:15:11.22#ibcon#flushed, iclass 4, count 0 2006.218.08:15:11.22#ibcon#about to write, iclass 4, count 0 2006.218.08:15:11.22#ibcon#wrote, iclass 4, count 0 2006.218.08:15:11.22#ibcon#about to read 3, iclass 4, count 0 2006.218.08:15:11.25#ibcon#read 3, iclass 4, count 0 2006.218.08:15:11.25#ibcon#about to read 4, iclass 4, count 0 2006.218.08:15:11.25#ibcon#read 4, iclass 4, count 0 2006.218.08:15:11.25#ibcon#about to read 5, iclass 4, count 0 2006.218.08:15:11.25#ibcon#read 5, iclass 4, count 0 2006.218.08:15:11.25#ibcon#about to read 6, iclass 4, count 0 2006.218.08:15:11.25#ibcon#read 6, iclass 4, count 0 2006.218.08:15:11.25#ibcon#end of sib2, iclass 4, count 0 2006.218.08:15:11.25#ibcon#*after write, iclass 4, count 0 2006.218.08:15:11.25#ibcon#*before return 0, iclass 4, count 0 2006.218.08:15:11.25#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.218.08:15:11.25#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.218.08:15:11.25#ibcon#about to clear, iclass 4 cls_cnt 0 2006.218.08:15:11.25#ibcon#cleared, iclass 4 cls_cnt 0 2006.218.08:15:11.25$vc4f8/vblo=3,656.99 2006.218.08:15:11.25#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.218.08:15:11.25#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.218.08:15:11.25#ibcon#ireg 17 cls_cnt 0 2006.218.08:15:11.25#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.218.08:15:11.25#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.218.08:15:11.25#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.218.08:15:11.25#ibcon#enter wrdev, iclass 6, count 0 2006.218.08:15:11.25#ibcon#first serial, iclass 6, count 0 2006.218.08:15:11.25#ibcon#enter sib2, iclass 6, count 0 2006.218.08:15:11.25#ibcon#flushed, iclass 6, count 0 2006.218.08:15:11.25#ibcon#about to write, iclass 6, count 0 2006.218.08:15:11.25#ibcon#wrote, iclass 6, count 0 2006.218.08:15:11.25#ibcon#about to read 3, iclass 6, count 0 2006.218.08:15:11.27#ibcon#read 3, iclass 6, count 0 2006.218.08:15:11.27#ibcon#about to read 4, iclass 6, count 0 2006.218.08:15:11.27#ibcon#read 4, iclass 6, count 0 2006.218.08:15:11.27#ibcon#about to read 5, iclass 6, count 0 2006.218.08:15:11.27#ibcon#read 5, iclass 6, count 0 2006.218.08:15:11.27#ibcon#about to read 6, iclass 6, count 0 2006.218.08:15:11.27#ibcon#read 6, iclass 6, count 0 2006.218.08:15:11.27#ibcon#end of sib2, iclass 6, count 0 2006.218.08:15:11.27#ibcon#*mode == 0, iclass 6, count 0 2006.218.08:15:11.27#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.218.08:15:11.27#ibcon#[28=FRQ=03,656.99\r\n] 2006.218.08:15:11.27#ibcon#*before write, iclass 6, count 0 2006.218.08:15:11.27#ibcon#enter sib2, iclass 6, count 0 2006.218.08:15:11.27#ibcon#flushed, iclass 6, count 0 2006.218.08:15:11.27#ibcon#about to write, iclass 6, count 0 2006.218.08:15:11.27#ibcon#wrote, iclass 6, count 0 2006.218.08:15:11.27#ibcon#about to read 3, iclass 6, count 0 2006.218.08:15:11.31#ibcon#read 3, iclass 6, count 0 2006.218.08:15:11.31#ibcon#about to read 4, iclass 6, count 0 2006.218.08:15:11.31#ibcon#read 4, iclass 6, count 0 2006.218.08:15:11.31#ibcon#about to read 5, iclass 6, count 0 2006.218.08:15:11.31#ibcon#read 5, iclass 6, count 0 2006.218.08:15:11.31#ibcon#about to read 6, iclass 6, count 0 2006.218.08:15:11.31#ibcon#read 6, iclass 6, count 0 2006.218.08:15:11.31#ibcon#end of sib2, iclass 6, count 0 2006.218.08:15:11.31#ibcon#*after write, iclass 6, count 0 2006.218.08:15:11.31#ibcon#*before return 0, iclass 6, count 0 2006.218.08:15:11.31#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.218.08:15:11.31#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.218.08:15:11.31#ibcon#about to clear, iclass 6 cls_cnt 0 2006.218.08:15:11.31#ibcon#cleared, iclass 6 cls_cnt 0 2006.218.08:15:11.31$vc4f8/vb=3,4 2006.218.08:15:11.31#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.218.08:15:11.31#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.218.08:15:11.31#ibcon#ireg 11 cls_cnt 2 2006.218.08:15:11.31#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.218.08:15:11.37#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.218.08:15:11.37#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.218.08:15:11.37#ibcon#enter wrdev, iclass 10, count 2 2006.218.08:15:11.37#ibcon#first serial, iclass 10, count 2 2006.218.08:15:11.37#ibcon#enter sib2, iclass 10, count 2 2006.218.08:15:11.37#ibcon#flushed, iclass 10, count 2 2006.218.08:15:11.37#ibcon#about to write, iclass 10, count 2 2006.218.08:15:11.37#ibcon#wrote, iclass 10, count 2 2006.218.08:15:11.37#ibcon#about to read 3, iclass 10, count 2 2006.218.08:15:11.39#ibcon#read 3, iclass 10, count 2 2006.218.08:15:11.39#ibcon#about to read 4, iclass 10, count 2 2006.218.08:15:11.39#ibcon#read 4, iclass 10, count 2 2006.218.08:15:11.39#ibcon#about to read 5, iclass 10, count 2 2006.218.08:15:11.39#ibcon#read 5, iclass 10, count 2 2006.218.08:15:11.39#ibcon#about to read 6, iclass 10, count 2 2006.218.08:15:11.39#ibcon#read 6, iclass 10, count 2 2006.218.08:15:11.39#ibcon#end of sib2, iclass 10, count 2 2006.218.08:15:11.39#ibcon#*mode == 0, iclass 10, count 2 2006.218.08:15:11.39#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.218.08:15:11.39#ibcon#[27=AT03-04\r\n] 2006.218.08:15:11.39#ibcon#*before write, iclass 10, count 2 2006.218.08:15:11.39#ibcon#enter sib2, iclass 10, count 2 2006.218.08:15:11.39#ibcon#flushed, iclass 10, count 2 2006.218.08:15:11.39#ibcon#about to write, iclass 10, count 2 2006.218.08:15:11.39#ibcon#wrote, iclass 10, count 2 2006.218.08:15:11.39#ibcon#about to read 3, iclass 10, count 2 2006.218.08:15:11.42#ibcon#read 3, iclass 10, count 2 2006.218.08:15:11.42#ibcon#about to read 4, iclass 10, count 2 2006.218.08:15:11.42#ibcon#read 4, iclass 10, count 2 2006.218.08:15:11.42#ibcon#about to read 5, iclass 10, count 2 2006.218.08:15:11.42#ibcon#read 5, iclass 10, count 2 2006.218.08:15:11.42#ibcon#about to read 6, iclass 10, count 2 2006.218.08:15:11.42#ibcon#read 6, iclass 10, count 2 2006.218.08:15:11.42#ibcon#end of sib2, iclass 10, count 2 2006.218.08:15:11.42#ibcon#*after write, iclass 10, count 2 2006.218.08:15:11.42#ibcon#*before return 0, iclass 10, count 2 2006.218.08:15:11.42#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.218.08:15:11.42#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.218.08:15:11.42#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.218.08:15:11.42#ibcon#ireg 7 cls_cnt 0 2006.218.08:15:11.42#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.218.08:15:11.54#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.218.08:15:11.54#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.218.08:15:11.54#ibcon#enter wrdev, iclass 10, count 0 2006.218.08:15:11.54#ibcon#first serial, iclass 10, count 0 2006.218.08:15:11.54#ibcon#enter sib2, iclass 10, count 0 2006.218.08:15:11.54#ibcon#flushed, iclass 10, count 0 2006.218.08:15:11.54#ibcon#about to write, iclass 10, count 0 2006.218.08:15:11.54#ibcon#wrote, iclass 10, count 0 2006.218.08:15:11.54#ibcon#about to read 3, iclass 10, count 0 2006.218.08:15:11.56#ibcon#read 3, iclass 10, count 0 2006.218.08:15:11.56#ibcon#about to read 4, iclass 10, count 0 2006.218.08:15:11.56#ibcon#read 4, iclass 10, count 0 2006.218.08:15:11.56#ibcon#about to read 5, iclass 10, count 0 2006.218.08:15:11.56#ibcon#read 5, iclass 10, count 0 2006.218.08:15:11.56#ibcon#about to read 6, iclass 10, count 0 2006.218.08:15:11.56#ibcon#read 6, iclass 10, count 0 2006.218.08:15:11.56#ibcon#end of sib2, iclass 10, count 0 2006.218.08:15:11.56#ibcon#*mode == 0, iclass 10, count 0 2006.218.08:15:11.56#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.218.08:15:11.56#ibcon#[27=USB\r\n] 2006.218.08:15:11.56#ibcon#*before write, iclass 10, count 0 2006.218.08:15:11.56#ibcon#enter sib2, iclass 10, count 0 2006.218.08:15:11.56#ibcon#flushed, iclass 10, count 0 2006.218.08:15:11.56#ibcon#about to write, iclass 10, count 0 2006.218.08:15:11.56#ibcon#wrote, iclass 10, count 0 2006.218.08:15:11.56#ibcon#about to read 3, iclass 10, count 0 2006.218.08:15:11.59#ibcon#read 3, iclass 10, count 0 2006.218.08:15:11.59#ibcon#about to read 4, iclass 10, count 0 2006.218.08:15:11.59#ibcon#read 4, iclass 10, count 0 2006.218.08:15:11.59#ibcon#about to read 5, iclass 10, count 0 2006.218.08:15:11.59#ibcon#read 5, iclass 10, count 0 2006.218.08:15:11.59#ibcon#about to read 6, iclass 10, count 0 2006.218.08:15:11.59#ibcon#read 6, iclass 10, count 0 2006.218.08:15:11.59#ibcon#end of sib2, iclass 10, count 0 2006.218.08:15:11.59#ibcon#*after write, iclass 10, count 0 2006.218.08:15:11.59#ibcon#*before return 0, iclass 10, count 0 2006.218.08:15:11.59#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.218.08:15:11.59#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.218.08:15:11.59#ibcon#about to clear, iclass 10 cls_cnt 0 2006.218.08:15:11.59#ibcon#cleared, iclass 10 cls_cnt 0 2006.218.08:15:11.59$vc4f8/vblo=4,712.99 2006.218.08:15:11.59#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.218.08:15:11.59#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.218.08:15:11.59#ibcon#ireg 17 cls_cnt 0 2006.218.08:15:11.59#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.218.08:15:11.59#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.218.08:15:11.59#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.218.08:15:11.59#ibcon#enter wrdev, iclass 12, count 0 2006.218.08:15:11.59#ibcon#first serial, iclass 12, count 0 2006.218.08:15:11.59#ibcon#enter sib2, iclass 12, count 0 2006.218.08:15:11.59#ibcon#flushed, iclass 12, count 0 2006.218.08:15:11.59#ibcon#about to write, iclass 12, count 0 2006.218.08:15:11.59#ibcon#wrote, iclass 12, count 0 2006.218.08:15:11.59#ibcon#about to read 3, iclass 12, count 0 2006.218.08:15:11.61#ibcon#read 3, iclass 12, count 0 2006.218.08:15:11.61#ibcon#about to read 4, iclass 12, count 0 2006.218.08:15:11.61#ibcon#read 4, iclass 12, count 0 2006.218.08:15:11.61#ibcon#about to read 5, iclass 12, count 0 2006.218.08:15:11.61#ibcon#read 5, iclass 12, count 0 2006.218.08:15:11.61#ibcon#about to read 6, iclass 12, count 0 2006.218.08:15:11.61#ibcon#read 6, iclass 12, count 0 2006.218.08:15:11.61#ibcon#end of sib2, iclass 12, count 0 2006.218.08:15:11.61#ibcon#*mode == 0, iclass 12, count 0 2006.218.08:15:11.61#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.218.08:15:11.61#ibcon#[28=FRQ=04,712.99\r\n] 2006.218.08:15:11.61#ibcon#*before write, iclass 12, count 0 2006.218.08:15:11.61#ibcon#enter sib2, iclass 12, count 0 2006.218.08:15:11.61#ibcon#flushed, iclass 12, count 0 2006.218.08:15:11.61#ibcon#about to write, iclass 12, count 0 2006.218.08:15:11.61#ibcon#wrote, iclass 12, count 0 2006.218.08:15:11.61#ibcon#about to read 3, iclass 12, count 0 2006.218.08:15:11.65#ibcon#read 3, iclass 12, count 0 2006.218.08:15:11.65#ibcon#about to read 4, iclass 12, count 0 2006.218.08:15:11.65#ibcon#read 4, iclass 12, count 0 2006.218.08:15:11.65#ibcon#about to read 5, iclass 12, count 0 2006.218.08:15:11.65#ibcon#read 5, iclass 12, count 0 2006.218.08:15:11.65#ibcon#about to read 6, iclass 12, count 0 2006.218.08:15:11.65#ibcon#read 6, iclass 12, count 0 2006.218.08:15:11.65#ibcon#end of sib2, iclass 12, count 0 2006.218.08:15:11.65#ibcon#*after write, iclass 12, count 0 2006.218.08:15:11.65#ibcon#*before return 0, iclass 12, count 0 2006.218.08:15:11.65#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.218.08:15:11.65#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.218.08:15:11.65#ibcon#about to clear, iclass 12 cls_cnt 0 2006.218.08:15:11.65#ibcon#cleared, iclass 12 cls_cnt 0 2006.218.08:15:11.65$vc4f8/vb=4,4 2006.218.08:15:11.65#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.218.08:15:11.65#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.218.08:15:11.65#ibcon#ireg 11 cls_cnt 2 2006.218.08:15:11.65#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.218.08:15:11.71#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.218.08:15:11.71#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.218.08:15:11.71#ibcon#enter wrdev, iclass 14, count 2 2006.218.08:15:11.71#ibcon#first serial, iclass 14, count 2 2006.218.08:15:11.71#ibcon#enter sib2, iclass 14, count 2 2006.218.08:15:11.71#ibcon#flushed, iclass 14, count 2 2006.218.08:15:11.71#ibcon#about to write, iclass 14, count 2 2006.218.08:15:11.71#ibcon#wrote, iclass 14, count 2 2006.218.08:15:11.71#ibcon#about to read 3, iclass 14, count 2 2006.218.08:15:11.73#ibcon#read 3, iclass 14, count 2 2006.218.08:15:11.73#ibcon#about to read 4, iclass 14, count 2 2006.218.08:15:11.73#ibcon#read 4, iclass 14, count 2 2006.218.08:15:11.73#ibcon#about to read 5, iclass 14, count 2 2006.218.08:15:11.73#ibcon#read 5, iclass 14, count 2 2006.218.08:15:11.73#ibcon#about to read 6, iclass 14, count 2 2006.218.08:15:11.73#ibcon#read 6, iclass 14, count 2 2006.218.08:15:11.73#ibcon#end of sib2, iclass 14, count 2 2006.218.08:15:11.73#ibcon#*mode == 0, iclass 14, count 2 2006.218.08:15:11.73#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.218.08:15:11.73#ibcon#[27=AT04-04\r\n] 2006.218.08:15:11.73#ibcon#*before write, iclass 14, count 2 2006.218.08:15:11.73#ibcon#enter sib2, iclass 14, count 2 2006.218.08:15:11.73#ibcon#flushed, iclass 14, count 2 2006.218.08:15:11.73#ibcon#about to write, iclass 14, count 2 2006.218.08:15:11.73#ibcon#wrote, iclass 14, count 2 2006.218.08:15:11.73#ibcon#about to read 3, iclass 14, count 2 2006.218.08:15:11.76#ibcon#read 3, iclass 14, count 2 2006.218.08:15:11.76#ibcon#about to read 4, iclass 14, count 2 2006.218.08:15:11.76#ibcon#read 4, iclass 14, count 2 2006.218.08:15:11.76#ibcon#about to read 5, iclass 14, count 2 2006.218.08:15:11.76#ibcon#read 5, iclass 14, count 2 2006.218.08:15:11.76#ibcon#about to read 6, iclass 14, count 2 2006.218.08:15:11.76#ibcon#read 6, iclass 14, count 2 2006.218.08:15:11.76#ibcon#end of sib2, iclass 14, count 2 2006.218.08:15:11.76#ibcon#*after write, iclass 14, count 2 2006.218.08:15:11.76#ibcon#*before return 0, iclass 14, count 2 2006.218.08:15:11.76#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.218.08:15:11.76#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.218.08:15:11.76#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.218.08:15:11.76#ibcon#ireg 7 cls_cnt 0 2006.218.08:15:11.76#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.218.08:15:11.88#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.218.08:15:11.88#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.218.08:15:11.88#ibcon#enter wrdev, iclass 14, count 0 2006.218.08:15:11.88#ibcon#first serial, iclass 14, count 0 2006.218.08:15:11.88#ibcon#enter sib2, iclass 14, count 0 2006.218.08:15:11.88#ibcon#flushed, iclass 14, count 0 2006.218.08:15:11.88#ibcon#about to write, iclass 14, count 0 2006.218.08:15:11.88#ibcon#wrote, iclass 14, count 0 2006.218.08:15:11.88#ibcon#about to read 3, iclass 14, count 0 2006.218.08:15:11.90#ibcon#read 3, iclass 14, count 0 2006.218.08:15:11.90#ibcon#about to read 4, iclass 14, count 0 2006.218.08:15:11.90#ibcon#read 4, iclass 14, count 0 2006.218.08:15:11.90#ibcon#about to read 5, iclass 14, count 0 2006.218.08:15:11.90#ibcon#read 5, iclass 14, count 0 2006.218.08:15:11.90#ibcon#about to read 6, iclass 14, count 0 2006.218.08:15:11.90#ibcon#read 6, iclass 14, count 0 2006.218.08:15:11.90#ibcon#end of sib2, iclass 14, count 0 2006.218.08:15:11.90#ibcon#*mode == 0, iclass 14, count 0 2006.218.08:15:11.90#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.218.08:15:11.90#ibcon#[27=USB\r\n] 2006.218.08:15:11.90#ibcon#*before write, iclass 14, count 0 2006.218.08:15:11.90#ibcon#enter sib2, iclass 14, count 0 2006.218.08:15:11.90#ibcon#flushed, iclass 14, count 0 2006.218.08:15:11.90#ibcon#about to write, iclass 14, count 0 2006.218.08:15:11.90#ibcon#wrote, iclass 14, count 0 2006.218.08:15:11.90#ibcon#about to read 3, iclass 14, count 0 2006.218.08:15:11.93#ibcon#read 3, iclass 14, count 0 2006.218.08:15:11.93#ibcon#about to read 4, iclass 14, count 0 2006.218.08:15:11.93#ibcon#read 4, iclass 14, count 0 2006.218.08:15:11.93#ibcon#about to read 5, iclass 14, count 0 2006.218.08:15:11.93#ibcon#read 5, iclass 14, count 0 2006.218.08:15:11.93#ibcon#about to read 6, iclass 14, count 0 2006.218.08:15:11.93#ibcon#read 6, iclass 14, count 0 2006.218.08:15:11.93#ibcon#end of sib2, iclass 14, count 0 2006.218.08:15:11.93#ibcon#*after write, iclass 14, count 0 2006.218.08:15:11.93#ibcon#*before return 0, iclass 14, count 0 2006.218.08:15:11.93#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.218.08:15:11.93#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.218.08:15:11.93#ibcon#about to clear, iclass 14 cls_cnt 0 2006.218.08:15:11.93#ibcon#cleared, iclass 14 cls_cnt 0 2006.218.08:15:11.93$vc4f8/vblo=5,744.99 2006.218.08:15:11.93#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.218.08:15:11.93#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.218.08:15:11.93#ibcon#ireg 17 cls_cnt 0 2006.218.08:15:11.93#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.218.08:15:11.93#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.218.08:15:11.93#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.218.08:15:11.93#ibcon#enter wrdev, iclass 16, count 0 2006.218.08:15:11.93#ibcon#first serial, iclass 16, count 0 2006.218.08:15:11.93#ibcon#enter sib2, iclass 16, count 0 2006.218.08:15:11.93#ibcon#flushed, iclass 16, count 0 2006.218.08:15:11.93#ibcon#about to write, iclass 16, count 0 2006.218.08:15:11.93#ibcon#wrote, iclass 16, count 0 2006.218.08:15:11.93#ibcon#about to read 3, iclass 16, count 0 2006.218.08:15:11.95#ibcon#read 3, iclass 16, count 0 2006.218.08:15:11.95#ibcon#about to read 4, iclass 16, count 0 2006.218.08:15:11.95#ibcon#read 4, iclass 16, count 0 2006.218.08:15:11.95#ibcon#about to read 5, iclass 16, count 0 2006.218.08:15:11.95#ibcon#read 5, iclass 16, count 0 2006.218.08:15:11.95#ibcon#about to read 6, iclass 16, count 0 2006.218.08:15:11.95#ibcon#read 6, iclass 16, count 0 2006.218.08:15:11.95#ibcon#end of sib2, iclass 16, count 0 2006.218.08:15:11.95#ibcon#*mode == 0, iclass 16, count 0 2006.218.08:15:11.95#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.218.08:15:11.95#ibcon#[28=FRQ=05,744.99\r\n] 2006.218.08:15:11.95#ibcon#*before write, iclass 16, count 0 2006.218.08:15:11.95#ibcon#enter sib2, iclass 16, count 0 2006.218.08:15:11.95#ibcon#flushed, iclass 16, count 0 2006.218.08:15:11.95#ibcon#about to write, iclass 16, count 0 2006.218.08:15:11.95#ibcon#wrote, iclass 16, count 0 2006.218.08:15:11.95#ibcon#about to read 3, iclass 16, count 0 2006.218.08:15:11.99#ibcon#read 3, iclass 16, count 0 2006.218.08:15:11.99#ibcon#about to read 4, iclass 16, count 0 2006.218.08:15:11.99#ibcon#read 4, iclass 16, count 0 2006.218.08:15:11.99#ibcon#about to read 5, iclass 16, count 0 2006.218.08:15:11.99#ibcon#read 5, iclass 16, count 0 2006.218.08:15:11.99#ibcon#about to read 6, iclass 16, count 0 2006.218.08:15:11.99#ibcon#read 6, iclass 16, count 0 2006.218.08:15:11.99#ibcon#end of sib2, iclass 16, count 0 2006.218.08:15:11.99#ibcon#*after write, iclass 16, count 0 2006.218.08:15:11.99#ibcon#*before return 0, iclass 16, count 0 2006.218.08:15:11.99#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.218.08:15:11.99#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.218.08:15:11.99#ibcon#about to clear, iclass 16 cls_cnt 0 2006.218.08:15:11.99#ibcon#cleared, iclass 16 cls_cnt 0 2006.218.08:15:11.99$vc4f8/vb=5,4 2006.218.08:15:11.99#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.218.08:15:11.99#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.218.08:15:11.99#ibcon#ireg 11 cls_cnt 2 2006.218.08:15:11.99#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.218.08:15:12.05#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.218.08:15:12.05#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.218.08:15:12.05#ibcon#enter wrdev, iclass 18, count 2 2006.218.08:15:12.05#ibcon#first serial, iclass 18, count 2 2006.218.08:15:12.05#ibcon#enter sib2, iclass 18, count 2 2006.218.08:15:12.05#ibcon#flushed, iclass 18, count 2 2006.218.08:15:12.05#ibcon#about to write, iclass 18, count 2 2006.218.08:15:12.05#ibcon#wrote, iclass 18, count 2 2006.218.08:15:12.05#ibcon#about to read 3, iclass 18, count 2 2006.218.08:15:12.07#ibcon#read 3, iclass 18, count 2 2006.218.08:15:12.07#ibcon#about to read 4, iclass 18, count 2 2006.218.08:15:12.07#ibcon#read 4, iclass 18, count 2 2006.218.08:15:12.07#ibcon#about to read 5, iclass 18, count 2 2006.218.08:15:12.07#ibcon#read 5, iclass 18, count 2 2006.218.08:15:12.07#ibcon#about to read 6, iclass 18, count 2 2006.218.08:15:12.07#ibcon#read 6, iclass 18, count 2 2006.218.08:15:12.07#ibcon#end of sib2, iclass 18, count 2 2006.218.08:15:12.07#ibcon#*mode == 0, iclass 18, count 2 2006.218.08:15:12.07#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.218.08:15:12.07#ibcon#[27=AT05-04\r\n] 2006.218.08:15:12.07#ibcon#*before write, iclass 18, count 2 2006.218.08:15:12.07#ibcon#enter sib2, iclass 18, count 2 2006.218.08:15:12.07#ibcon#flushed, iclass 18, count 2 2006.218.08:15:12.07#ibcon#about to write, iclass 18, count 2 2006.218.08:15:12.07#ibcon#wrote, iclass 18, count 2 2006.218.08:15:12.07#ibcon#about to read 3, iclass 18, count 2 2006.218.08:15:12.10#ibcon#read 3, iclass 18, count 2 2006.218.08:15:12.10#ibcon#about to read 4, iclass 18, count 2 2006.218.08:15:12.10#ibcon#read 4, iclass 18, count 2 2006.218.08:15:12.10#ibcon#about to read 5, iclass 18, count 2 2006.218.08:15:12.10#ibcon#read 5, iclass 18, count 2 2006.218.08:15:12.10#ibcon#about to read 6, iclass 18, count 2 2006.218.08:15:12.10#ibcon#read 6, iclass 18, count 2 2006.218.08:15:12.10#ibcon#end of sib2, iclass 18, count 2 2006.218.08:15:12.10#ibcon#*after write, iclass 18, count 2 2006.218.08:15:12.10#ibcon#*before return 0, iclass 18, count 2 2006.218.08:15:12.10#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.218.08:15:12.10#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.218.08:15:12.10#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.218.08:15:12.10#ibcon#ireg 7 cls_cnt 0 2006.218.08:15:12.10#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.218.08:15:12.22#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.218.08:15:12.22#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.218.08:15:12.22#ibcon#enter wrdev, iclass 18, count 0 2006.218.08:15:12.22#ibcon#first serial, iclass 18, count 0 2006.218.08:15:12.22#ibcon#enter sib2, iclass 18, count 0 2006.218.08:15:12.22#ibcon#flushed, iclass 18, count 0 2006.218.08:15:12.22#ibcon#about to write, iclass 18, count 0 2006.218.08:15:12.22#ibcon#wrote, iclass 18, count 0 2006.218.08:15:12.22#ibcon#about to read 3, iclass 18, count 0 2006.218.08:15:12.24#ibcon#read 3, iclass 18, count 0 2006.218.08:15:12.24#ibcon#about to read 4, iclass 18, count 0 2006.218.08:15:12.24#ibcon#read 4, iclass 18, count 0 2006.218.08:15:12.24#ibcon#about to read 5, iclass 18, count 0 2006.218.08:15:12.24#ibcon#read 5, iclass 18, count 0 2006.218.08:15:12.24#ibcon#about to read 6, iclass 18, count 0 2006.218.08:15:12.24#ibcon#read 6, iclass 18, count 0 2006.218.08:15:12.24#ibcon#end of sib2, iclass 18, count 0 2006.218.08:15:12.24#ibcon#*mode == 0, iclass 18, count 0 2006.218.08:15:12.24#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.218.08:15:12.24#ibcon#[27=USB\r\n] 2006.218.08:15:12.24#ibcon#*before write, iclass 18, count 0 2006.218.08:15:12.24#ibcon#enter sib2, iclass 18, count 0 2006.218.08:15:12.24#ibcon#flushed, iclass 18, count 0 2006.218.08:15:12.24#ibcon#about to write, iclass 18, count 0 2006.218.08:15:12.24#ibcon#wrote, iclass 18, count 0 2006.218.08:15:12.24#ibcon#about to read 3, iclass 18, count 0 2006.218.08:15:12.27#ibcon#read 3, iclass 18, count 0 2006.218.08:15:12.27#ibcon#about to read 4, iclass 18, count 0 2006.218.08:15:12.27#ibcon#read 4, iclass 18, count 0 2006.218.08:15:12.27#ibcon#about to read 5, iclass 18, count 0 2006.218.08:15:12.27#ibcon#read 5, iclass 18, count 0 2006.218.08:15:12.27#ibcon#about to read 6, iclass 18, count 0 2006.218.08:15:12.27#ibcon#read 6, iclass 18, count 0 2006.218.08:15:12.27#ibcon#end of sib2, iclass 18, count 0 2006.218.08:15:12.27#ibcon#*after write, iclass 18, count 0 2006.218.08:15:12.27#ibcon#*before return 0, iclass 18, count 0 2006.218.08:15:12.27#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.218.08:15:12.27#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.218.08:15:12.27#ibcon#about to clear, iclass 18 cls_cnt 0 2006.218.08:15:12.27#ibcon#cleared, iclass 18 cls_cnt 0 2006.218.08:15:12.27$vc4f8/vblo=6,752.99 2006.218.08:15:12.27#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.218.08:15:12.27#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.218.08:15:12.27#ibcon#ireg 17 cls_cnt 0 2006.218.08:15:12.27#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.218.08:15:12.27#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.218.08:15:12.27#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.218.08:15:12.27#ibcon#enter wrdev, iclass 20, count 0 2006.218.08:15:12.27#ibcon#first serial, iclass 20, count 0 2006.218.08:15:12.27#ibcon#enter sib2, iclass 20, count 0 2006.218.08:15:12.27#ibcon#flushed, iclass 20, count 0 2006.218.08:15:12.27#ibcon#about to write, iclass 20, count 0 2006.218.08:15:12.27#ibcon#wrote, iclass 20, count 0 2006.218.08:15:12.27#ibcon#about to read 3, iclass 20, count 0 2006.218.08:15:12.29#ibcon#read 3, iclass 20, count 0 2006.218.08:15:12.29#ibcon#about to read 4, iclass 20, count 0 2006.218.08:15:12.29#ibcon#read 4, iclass 20, count 0 2006.218.08:15:12.29#ibcon#about to read 5, iclass 20, count 0 2006.218.08:15:12.29#ibcon#read 5, iclass 20, count 0 2006.218.08:15:12.29#ibcon#about to read 6, iclass 20, count 0 2006.218.08:15:12.29#ibcon#read 6, iclass 20, count 0 2006.218.08:15:12.29#ibcon#end of sib2, iclass 20, count 0 2006.218.08:15:12.29#ibcon#*mode == 0, iclass 20, count 0 2006.218.08:15:12.29#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.218.08:15:12.29#ibcon#[28=FRQ=06,752.99\r\n] 2006.218.08:15:12.29#ibcon#*before write, iclass 20, count 0 2006.218.08:15:12.29#ibcon#enter sib2, iclass 20, count 0 2006.218.08:15:12.29#ibcon#flushed, iclass 20, count 0 2006.218.08:15:12.29#ibcon#about to write, iclass 20, count 0 2006.218.08:15:12.29#ibcon#wrote, iclass 20, count 0 2006.218.08:15:12.29#ibcon#about to read 3, iclass 20, count 0 2006.218.08:15:12.33#ibcon#read 3, iclass 20, count 0 2006.218.08:15:12.33#ibcon#about to read 4, iclass 20, count 0 2006.218.08:15:12.33#ibcon#read 4, iclass 20, count 0 2006.218.08:15:12.33#ibcon#about to read 5, iclass 20, count 0 2006.218.08:15:12.33#ibcon#read 5, iclass 20, count 0 2006.218.08:15:12.33#ibcon#about to read 6, iclass 20, count 0 2006.218.08:15:12.33#ibcon#read 6, iclass 20, count 0 2006.218.08:15:12.33#ibcon#end of sib2, iclass 20, count 0 2006.218.08:15:12.33#ibcon#*after write, iclass 20, count 0 2006.218.08:15:12.33#ibcon#*before return 0, iclass 20, count 0 2006.218.08:15:12.33#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.218.08:15:12.33#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.218.08:15:12.33#ibcon#about to clear, iclass 20 cls_cnt 0 2006.218.08:15:12.33#ibcon#cleared, iclass 20 cls_cnt 0 2006.218.08:15:12.33$vc4f8/vb=6,4 2006.218.08:15:12.33#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.218.08:15:12.33#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.218.08:15:12.33#ibcon#ireg 11 cls_cnt 2 2006.218.08:15:12.33#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.218.08:15:12.39#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.218.08:15:12.39#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.218.08:15:12.39#ibcon#enter wrdev, iclass 22, count 2 2006.218.08:15:12.39#ibcon#first serial, iclass 22, count 2 2006.218.08:15:12.39#ibcon#enter sib2, iclass 22, count 2 2006.218.08:15:12.39#ibcon#flushed, iclass 22, count 2 2006.218.08:15:12.39#ibcon#about to write, iclass 22, count 2 2006.218.08:15:12.39#ibcon#wrote, iclass 22, count 2 2006.218.08:15:12.39#ibcon#about to read 3, iclass 22, count 2 2006.218.08:15:12.41#ibcon#read 3, iclass 22, count 2 2006.218.08:15:12.41#ibcon#about to read 4, iclass 22, count 2 2006.218.08:15:12.41#ibcon#read 4, iclass 22, count 2 2006.218.08:15:12.41#ibcon#about to read 5, iclass 22, count 2 2006.218.08:15:12.41#ibcon#read 5, iclass 22, count 2 2006.218.08:15:12.41#ibcon#about to read 6, iclass 22, count 2 2006.218.08:15:12.41#ibcon#read 6, iclass 22, count 2 2006.218.08:15:12.41#ibcon#end of sib2, iclass 22, count 2 2006.218.08:15:12.41#ibcon#*mode == 0, iclass 22, count 2 2006.218.08:15:12.41#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.218.08:15:12.41#ibcon#[27=AT06-04\r\n] 2006.218.08:15:12.41#ibcon#*before write, iclass 22, count 2 2006.218.08:15:12.41#ibcon#enter sib2, iclass 22, count 2 2006.218.08:15:12.41#ibcon#flushed, iclass 22, count 2 2006.218.08:15:12.41#ibcon#about to write, iclass 22, count 2 2006.218.08:15:12.41#ibcon#wrote, iclass 22, count 2 2006.218.08:15:12.41#ibcon#about to read 3, iclass 22, count 2 2006.218.08:15:12.44#ibcon#read 3, iclass 22, count 2 2006.218.08:15:12.44#ibcon#about to read 4, iclass 22, count 2 2006.218.08:15:12.44#ibcon#read 4, iclass 22, count 2 2006.218.08:15:12.44#ibcon#about to read 5, iclass 22, count 2 2006.218.08:15:12.44#ibcon#read 5, iclass 22, count 2 2006.218.08:15:12.44#ibcon#about to read 6, iclass 22, count 2 2006.218.08:15:12.44#ibcon#read 6, iclass 22, count 2 2006.218.08:15:12.44#ibcon#end of sib2, iclass 22, count 2 2006.218.08:15:12.44#ibcon#*after write, iclass 22, count 2 2006.218.08:15:12.44#ibcon#*before return 0, iclass 22, count 2 2006.218.08:15:12.44#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.218.08:15:12.44#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.218.08:15:12.44#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.218.08:15:12.44#ibcon#ireg 7 cls_cnt 0 2006.218.08:15:12.44#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.218.08:15:12.56#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.218.08:15:12.56#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.218.08:15:12.56#ibcon#enter wrdev, iclass 22, count 0 2006.218.08:15:12.56#ibcon#first serial, iclass 22, count 0 2006.218.08:15:12.56#ibcon#enter sib2, iclass 22, count 0 2006.218.08:15:12.56#ibcon#flushed, iclass 22, count 0 2006.218.08:15:12.56#ibcon#about to write, iclass 22, count 0 2006.218.08:15:12.56#ibcon#wrote, iclass 22, count 0 2006.218.08:15:12.56#ibcon#about to read 3, iclass 22, count 0 2006.218.08:15:12.58#ibcon#read 3, iclass 22, count 0 2006.218.08:15:12.58#ibcon#about to read 4, iclass 22, count 0 2006.218.08:15:12.58#ibcon#read 4, iclass 22, count 0 2006.218.08:15:12.58#ibcon#about to read 5, iclass 22, count 0 2006.218.08:15:12.58#ibcon#read 5, iclass 22, count 0 2006.218.08:15:12.58#ibcon#about to read 6, iclass 22, count 0 2006.218.08:15:12.58#ibcon#read 6, iclass 22, count 0 2006.218.08:15:12.58#ibcon#end of sib2, iclass 22, count 0 2006.218.08:15:12.58#ibcon#*mode == 0, iclass 22, count 0 2006.218.08:15:12.58#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.218.08:15:12.58#ibcon#[27=USB\r\n] 2006.218.08:15:12.58#ibcon#*before write, iclass 22, count 0 2006.218.08:15:12.58#ibcon#enter sib2, iclass 22, count 0 2006.218.08:15:12.58#ibcon#flushed, iclass 22, count 0 2006.218.08:15:12.58#ibcon#about to write, iclass 22, count 0 2006.218.08:15:12.58#ibcon#wrote, iclass 22, count 0 2006.218.08:15:12.58#ibcon#about to read 3, iclass 22, count 0 2006.218.08:15:12.61#ibcon#read 3, iclass 22, count 0 2006.218.08:15:12.61#ibcon#about to read 4, iclass 22, count 0 2006.218.08:15:12.61#ibcon#read 4, iclass 22, count 0 2006.218.08:15:12.61#ibcon#about to read 5, iclass 22, count 0 2006.218.08:15:12.61#ibcon#read 5, iclass 22, count 0 2006.218.08:15:12.61#ibcon#about to read 6, iclass 22, count 0 2006.218.08:15:12.61#ibcon#read 6, iclass 22, count 0 2006.218.08:15:12.61#ibcon#end of sib2, iclass 22, count 0 2006.218.08:15:12.61#ibcon#*after write, iclass 22, count 0 2006.218.08:15:12.61#ibcon#*before return 0, iclass 22, count 0 2006.218.08:15:12.61#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.218.08:15:12.61#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.218.08:15:12.61#ibcon#about to clear, iclass 22 cls_cnt 0 2006.218.08:15:12.61#ibcon#cleared, iclass 22 cls_cnt 0 2006.218.08:15:12.61$vc4f8/vabw=wide 2006.218.08:15:12.61#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.218.08:15:12.61#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.218.08:15:12.61#ibcon#ireg 8 cls_cnt 0 2006.218.08:15:12.61#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.218.08:15:12.61#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.218.08:15:12.61#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.218.08:15:12.61#ibcon#enter wrdev, iclass 24, count 0 2006.218.08:15:12.61#ibcon#first serial, iclass 24, count 0 2006.218.08:15:12.61#ibcon#enter sib2, iclass 24, count 0 2006.218.08:15:12.61#ibcon#flushed, iclass 24, count 0 2006.218.08:15:12.61#ibcon#about to write, iclass 24, count 0 2006.218.08:15:12.61#ibcon#wrote, iclass 24, count 0 2006.218.08:15:12.61#ibcon#about to read 3, iclass 24, count 0 2006.218.08:15:12.63#ibcon#read 3, iclass 24, count 0 2006.218.08:15:12.63#ibcon#about to read 4, iclass 24, count 0 2006.218.08:15:12.63#ibcon#read 4, iclass 24, count 0 2006.218.08:15:12.63#ibcon#about to read 5, iclass 24, count 0 2006.218.08:15:12.63#ibcon#read 5, iclass 24, count 0 2006.218.08:15:12.63#ibcon#about to read 6, iclass 24, count 0 2006.218.08:15:12.63#ibcon#read 6, iclass 24, count 0 2006.218.08:15:12.63#ibcon#end of sib2, iclass 24, count 0 2006.218.08:15:12.63#ibcon#*mode == 0, iclass 24, count 0 2006.218.08:15:12.63#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.218.08:15:12.63#ibcon#[25=BW32\r\n] 2006.218.08:15:12.63#ibcon#*before write, iclass 24, count 0 2006.218.08:15:12.63#ibcon#enter sib2, iclass 24, count 0 2006.218.08:15:12.63#ibcon#flushed, iclass 24, count 0 2006.218.08:15:12.63#ibcon#about to write, iclass 24, count 0 2006.218.08:15:12.63#ibcon#wrote, iclass 24, count 0 2006.218.08:15:12.63#ibcon#about to read 3, iclass 24, count 0 2006.218.08:15:12.66#ibcon#read 3, iclass 24, count 0 2006.218.08:15:12.66#ibcon#about to read 4, iclass 24, count 0 2006.218.08:15:12.66#ibcon#read 4, iclass 24, count 0 2006.218.08:15:12.66#ibcon#about to read 5, iclass 24, count 0 2006.218.08:15:12.66#ibcon#read 5, iclass 24, count 0 2006.218.08:15:12.66#ibcon#about to read 6, iclass 24, count 0 2006.218.08:15:12.66#ibcon#read 6, iclass 24, count 0 2006.218.08:15:12.66#ibcon#end of sib2, iclass 24, count 0 2006.218.08:15:12.66#ibcon#*after write, iclass 24, count 0 2006.218.08:15:12.66#ibcon#*before return 0, iclass 24, count 0 2006.218.08:15:12.66#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.218.08:15:12.66#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.218.08:15:12.66#ibcon#about to clear, iclass 24 cls_cnt 0 2006.218.08:15:12.66#ibcon#cleared, iclass 24 cls_cnt 0 2006.218.08:15:12.66$vc4f8/vbbw=wide 2006.218.08:15:12.66#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.218.08:15:12.66#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.218.08:15:12.66#ibcon#ireg 8 cls_cnt 0 2006.218.08:15:12.66#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.218.08:15:12.73#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.218.08:15:12.73#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.218.08:15:12.73#ibcon#enter wrdev, iclass 26, count 0 2006.218.08:15:12.73#ibcon#first serial, iclass 26, count 0 2006.218.08:15:12.73#ibcon#enter sib2, iclass 26, count 0 2006.218.08:15:12.73#ibcon#flushed, iclass 26, count 0 2006.218.08:15:12.73#ibcon#about to write, iclass 26, count 0 2006.218.08:15:12.73#ibcon#wrote, iclass 26, count 0 2006.218.08:15:12.73#ibcon#about to read 3, iclass 26, count 0 2006.218.08:15:12.75#ibcon#read 3, iclass 26, count 0 2006.218.08:15:12.75#ibcon#about to read 4, iclass 26, count 0 2006.218.08:15:12.75#ibcon#read 4, iclass 26, count 0 2006.218.08:15:12.75#ibcon#about to read 5, iclass 26, count 0 2006.218.08:15:12.75#ibcon#read 5, iclass 26, count 0 2006.218.08:15:12.75#ibcon#about to read 6, iclass 26, count 0 2006.218.08:15:12.75#ibcon#read 6, iclass 26, count 0 2006.218.08:15:12.75#ibcon#end of sib2, iclass 26, count 0 2006.218.08:15:12.75#ibcon#*mode == 0, iclass 26, count 0 2006.218.08:15:12.75#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.218.08:15:12.75#ibcon#[27=BW32\r\n] 2006.218.08:15:12.75#ibcon#*before write, iclass 26, count 0 2006.218.08:15:12.75#ibcon#enter sib2, iclass 26, count 0 2006.218.08:15:12.75#ibcon#flushed, iclass 26, count 0 2006.218.08:15:12.75#ibcon#about to write, iclass 26, count 0 2006.218.08:15:12.75#ibcon#wrote, iclass 26, count 0 2006.218.08:15:12.75#ibcon#about to read 3, iclass 26, count 0 2006.218.08:15:12.78#ibcon#read 3, iclass 26, count 0 2006.218.08:15:12.78#ibcon#about to read 4, iclass 26, count 0 2006.218.08:15:12.78#ibcon#read 4, iclass 26, count 0 2006.218.08:15:12.78#ibcon#about to read 5, iclass 26, count 0 2006.218.08:15:12.78#ibcon#read 5, iclass 26, count 0 2006.218.08:15:12.78#ibcon#about to read 6, iclass 26, count 0 2006.218.08:15:12.78#ibcon#read 6, iclass 26, count 0 2006.218.08:15:12.78#ibcon#end of sib2, iclass 26, count 0 2006.218.08:15:12.78#ibcon#*after write, iclass 26, count 0 2006.218.08:15:12.78#ibcon#*before return 0, iclass 26, count 0 2006.218.08:15:12.78#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.218.08:15:12.78#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.218.08:15:12.78#ibcon#about to clear, iclass 26 cls_cnt 0 2006.218.08:15:12.78#ibcon#cleared, iclass 26 cls_cnt 0 2006.218.08:15:12.78$4f8m12a/ifd4f 2006.218.08:15:12.78$ifd4f/lo= 2006.218.08:15:12.78$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.218.08:15:12.78$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.218.08:15:12.78$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.218.08:15:12.78$ifd4f/patch= 2006.218.08:15:12.78$ifd4f/patch=lo1,a1,a2,a3,a4 2006.218.08:15:12.78$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.218.08:15:12.78$ifd4f/patch=lo3,a5,a6,a7,a8 2006.218.08:15:12.78$4f8m12a/"form=m,16.000,1:2 2006.218.08:15:12.78$4f8m12a/"tpicd 2006.218.08:15:12.78$4f8m12a/echo=off 2006.218.08:15:12.78$4f8m12a/xlog=off 2006.218.08:15:12.78:!2006.218.08:15:40 2006.218.08:15:26.14#trakl#Source acquired 2006.218.08:15:28.14#flagr#flagr/antenna,acquired 2006.218.08:15:40.00:preob 2006.218.08:15:41.14/onsource/TRACKING 2006.218.08:15:41.14:!2006.218.08:15:50 2006.218.08:15:50.00:data_valid=on 2006.218.08:15:50.00:midob 2006.218.08:15:50.14/onsource/TRACKING 2006.218.08:15:50.14/wx/30.81,1007.6,74 2006.218.08:15:50.34/cable/+6.3847E-03 2006.218.08:15:51.43/va/01,05,usb,yes,31,33 2006.218.08:15:51.43/va/02,04,usb,yes,29,30 2006.218.08:15:51.43/va/03,04,usb,yes,27,28 2006.218.08:15:51.43/va/04,04,usb,yes,31,33 2006.218.08:15:51.43/va/05,07,usb,yes,33,35 2006.218.08:15:51.43/va/06,06,usb,yes,32,32 2006.218.08:15:51.43/va/07,06,usb,yes,33,32 2006.218.08:15:51.43/va/08,07,usb,yes,31,30 2006.218.08:15:51.66/valo/01,532.99,yes,locked 2006.218.08:15:51.66/valo/02,572.99,yes,locked 2006.218.08:15:51.66/valo/03,672.99,yes,locked 2006.218.08:15:51.66/valo/04,832.99,yes,locked 2006.218.08:15:51.66/valo/05,652.99,yes,locked 2006.218.08:15:51.66/valo/06,772.99,yes,locked 2006.218.08:15:51.66/valo/07,832.99,yes,locked 2006.218.08:15:51.66/valo/08,852.99,yes,locked 2006.218.08:15:52.75/vb/01,04,usb,yes,30,29 2006.218.08:15:52.75/vb/02,04,usb,yes,32,33 2006.218.08:15:52.75/vb/03,04,usb,yes,28,32 2006.218.08:15:52.75/vb/04,04,usb,yes,29,29 2006.218.08:15:52.75/vb/05,04,usb,yes,27,31 2006.218.08:15:52.75/vb/06,04,usb,yes,28,31 2006.218.08:15:52.75/vb/07,04,usb,yes,31,30 2006.218.08:15:52.75/vb/08,04,usb,yes,28,31 2006.218.08:15:52.98/vblo/01,632.99,yes,locked 2006.218.08:15:52.98/vblo/02,640.99,yes,locked 2006.218.08:15:52.98/vblo/03,656.99,yes,locked 2006.218.08:15:52.98/vblo/04,712.99,yes,locked 2006.218.08:15:52.98/vblo/05,744.99,yes,locked 2006.218.08:15:52.98/vblo/06,752.99,yes,locked 2006.218.08:15:52.98/vblo/07,734.99,yes,locked 2006.218.08:15:52.98/vblo/08,744.99,yes,locked 2006.218.08:15:53.13/vabw/8 2006.218.08:15:53.28/vbbw/8 2006.218.08:15:53.39/xfe/off,on,15.0 2006.218.08:15:53.76/ifatt/23,28,28,28 2006.218.08:15:54.07/fmout-gps/S +4.61E-07 2006.218.08:15:54.11:!2006.218.08:16:50 2006.218.08:16:50.00:data_valid=off 2006.218.08:16:50.00:postob 2006.218.08:16:50.14/cable/+6.3846E-03 2006.218.08:16:50.14/wx/30.78,1007.6,74 2006.218.08:16:51.08/fmout-gps/S +4.61E-07 2006.218.08:16:51.08:scan_name=218-0817,k06218,60 2006.218.08:16:51.08:source=4c39.25,092703.01,390220.9,2000.0,cw 2006.218.08:16:51.14#flagr#flagr/antenna,new-source 2006.218.08:16:52.14:checkk5 2006.218.08:16:52.51/chk_autoobs//k5ts1/ autoobs is running! 2006.218.08:16:52.89/chk_autoobs//k5ts2/ autoobs is running! 2006.218.08:16:53.26/chk_autoobs//k5ts3/ autoobs is running! 2006.218.08:16:53.63/chk_autoobs//k5ts4/ autoobs is running! 2006.218.08:16:54.00/chk_obsdata//k5ts1/T2180815??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.08:16:54.37/chk_obsdata//k5ts2/T2180815??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.08:16:54.73/chk_obsdata//k5ts3/T2180815??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.08:16:55.11/chk_obsdata//k5ts4/T2180815??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.08:16:55.81/k5log//k5ts1_log_newline 2006.218.08:16:56.51/k5log//k5ts2_log_newline 2006.218.08:16:57.20/k5log//k5ts3_log_newline 2006.218.08:16:57.90/k5log//k5ts4_log_newline 2006.218.08:16:57.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.218.08:16:57.93:4f8m12a=2 2006.218.08:16:57.93$4f8m12a/echo=on 2006.218.08:16:57.93$4f8m12a/pcalon 2006.218.08:16:57.93$pcalon/"no phase cal control is implemented here 2006.218.08:16:57.93$4f8m12a/"tpicd=stop 2006.218.08:16:57.93$4f8m12a/vc4f8 2006.218.08:16:57.93$vc4f8/valo=1,532.99 2006.218.08:16:57.93#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.218.08:16:57.93#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.218.08:16:57.93#ibcon#ireg 17 cls_cnt 0 2006.218.08:16:57.93#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.218.08:16:57.93#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.218.08:16:57.93#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.218.08:16:57.93#ibcon#enter wrdev, iclass 33, count 0 2006.218.08:16:57.93#ibcon#first serial, iclass 33, count 0 2006.218.08:16:57.93#ibcon#enter sib2, iclass 33, count 0 2006.218.08:16:57.93#ibcon#flushed, iclass 33, count 0 2006.218.08:16:57.93#ibcon#about to write, iclass 33, count 0 2006.218.08:16:57.93#ibcon#wrote, iclass 33, count 0 2006.218.08:16:57.93#ibcon#about to read 3, iclass 33, count 0 2006.218.08:16:57.95#ibcon#read 3, iclass 33, count 0 2006.218.08:16:57.95#ibcon#about to read 4, iclass 33, count 0 2006.218.08:16:57.95#ibcon#read 4, iclass 33, count 0 2006.218.08:16:57.95#ibcon#about to read 5, iclass 33, count 0 2006.218.08:16:57.95#ibcon#read 5, iclass 33, count 0 2006.218.08:16:57.95#ibcon#about to read 6, iclass 33, count 0 2006.218.08:16:57.95#ibcon#read 6, iclass 33, count 0 2006.218.08:16:57.95#ibcon#end of sib2, iclass 33, count 0 2006.218.08:16:57.95#ibcon#*mode == 0, iclass 33, count 0 2006.218.08:16:57.95#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.218.08:16:57.95#ibcon#[26=FRQ=01,532.99\r\n] 2006.218.08:16:57.95#ibcon#*before write, iclass 33, count 0 2006.218.08:16:57.95#ibcon#enter sib2, iclass 33, count 0 2006.218.08:16:57.95#ibcon#flushed, iclass 33, count 0 2006.218.08:16:57.95#ibcon#about to write, iclass 33, count 0 2006.218.08:16:57.95#ibcon#wrote, iclass 33, count 0 2006.218.08:16:57.95#ibcon#about to read 3, iclass 33, count 0 2006.218.08:16:58.00#ibcon#read 3, iclass 33, count 0 2006.218.08:16:58.00#ibcon#about to read 4, iclass 33, count 0 2006.218.08:16:58.00#ibcon#read 4, iclass 33, count 0 2006.218.08:16:58.00#ibcon#about to read 5, iclass 33, count 0 2006.218.08:16:58.00#ibcon#read 5, iclass 33, count 0 2006.218.08:16:58.00#ibcon#about to read 6, iclass 33, count 0 2006.218.08:16:58.00#ibcon#read 6, iclass 33, count 0 2006.218.08:16:58.00#ibcon#end of sib2, iclass 33, count 0 2006.218.08:16:58.00#ibcon#*after write, iclass 33, count 0 2006.218.08:16:58.00#ibcon#*before return 0, iclass 33, count 0 2006.218.08:16:58.00#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.218.08:16:58.00#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.218.08:16:58.00#ibcon#about to clear, iclass 33 cls_cnt 0 2006.218.08:16:58.00#ibcon#cleared, iclass 33 cls_cnt 0 2006.218.08:16:58.00$vc4f8/va=1,5 2006.218.08:16:58.00#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.218.08:16:58.00#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.218.08:16:58.00#ibcon#ireg 11 cls_cnt 2 2006.218.08:16:58.00#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.218.08:16:58.00#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.218.08:16:58.00#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.218.08:16:58.00#ibcon#enter wrdev, iclass 35, count 2 2006.218.08:16:58.00#ibcon#first serial, iclass 35, count 2 2006.218.08:16:58.00#ibcon#enter sib2, iclass 35, count 2 2006.218.08:16:58.00#ibcon#flushed, iclass 35, count 2 2006.218.08:16:58.00#ibcon#about to write, iclass 35, count 2 2006.218.08:16:58.00#ibcon#wrote, iclass 35, count 2 2006.218.08:16:58.00#ibcon#about to read 3, iclass 35, count 2 2006.218.08:16:58.02#ibcon#read 3, iclass 35, count 2 2006.218.08:16:58.02#ibcon#about to read 4, iclass 35, count 2 2006.218.08:16:58.02#ibcon#read 4, iclass 35, count 2 2006.218.08:16:58.02#ibcon#about to read 5, iclass 35, count 2 2006.218.08:16:58.02#ibcon#read 5, iclass 35, count 2 2006.218.08:16:58.02#ibcon#about to read 6, iclass 35, count 2 2006.218.08:16:58.02#ibcon#read 6, iclass 35, count 2 2006.218.08:16:58.02#ibcon#end of sib2, iclass 35, count 2 2006.218.08:16:58.02#ibcon#*mode == 0, iclass 35, count 2 2006.218.08:16:58.02#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.218.08:16:58.02#ibcon#[25=AT01-05\r\n] 2006.218.08:16:58.02#ibcon#*before write, iclass 35, count 2 2006.218.08:16:58.02#ibcon#enter sib2, iclass 35, count 2 2006.218.08:16:58.02#ibcon#flushed, iclass 35, count 2 2006.218.08:16:58.02#ibcon#about to write, iclass 35, count 2 2006.218.08:16:58.02#ibcon#wrote, iclass 35, count 2 2006.218.08:16:58.02#ibcon#about to read 3, iclass 35, count 2 2006.218.08:16:58.05#ibcon#read 3, iclass 35, count 2 2006.218.08:16:58.05#ibcon#about to read 4, iclass 35, count 2 2006.218.08:16:58.05#ibcon#read 4, iclass 35, count 2 2006.218.08:16:58.05#ibcon#about to read 5, iclass 35, count 2 2006.218.08:16:58.05#ibcon#read 5, iclass 35, count 2 2006.218.08:16:58.05#ibcon#about to read 6, iclass 35, count 2 2006.218.08:16:58.05#ibcon#read 6, iclass 35, count 2 2006.218.08:16:58.05#ibcon#end of sib2, iclass 35, count 2 2006.218.08:16:58.05#ibcon#*after write, iclass 35, count 2 2006.218.08:16:58.05#ibcon#*before return 0, iclass 35, count 2 2006.218.08:16:58.05#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.218.08:16:58.05#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.218.08:16:58.05#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.218.08:16:58.05#ibcon#ireg 7 cls_cnt 0 2006.218.08:16:58.05#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.218.08:16:58.17#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.218.08:16:58.17#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.218.08:16:58.17#ibcon#enter wrdev, iclass 35, count 0 2006.218.08:16:58.17#ibcon#first serial, iclass 35, count 0 2006.218.08:16:58.17#ibcon#enter sib2, iclass 35, count 0 2006.218.08:16:58.17#ibcon#flushed, iclass 35, count 0 2006.218.08:16:58.17#ibcon#about to write, iclass 35, count 0 2006.218.08:16:58.17#ibcon#wrote, iclass 35, count 0 2006.218.08:16:58.17#ibcon#about to read 3, iclass 35, count 0 2006.218.08:16:58.19#ibcon#read 3, iclass 35, count 0 2006.218.08:16:58.19#ibcon#about to read 4, iclass 35, count 0 2006.218.08:16:58.19#ibcon#read 4, iclass 35, count 0 2006.218.08:16:58.19#ibcon#about to read 5, iclass 35, count 0 2006.218.08:16:58.19#ibcon#read 5, iclass 35, count 0 2006.218.08:16:58.19#ibcon#about to read 6, iclass 35, count 0 2006.218.08:16:58.19#ibcon#read 6, iclass 35, count 0 2006.218.08:16:58.19#ibcon#end of sib2, iclass 35, count 0 2006.218.08:16:58.19#ibcon#*mode == 0, iclass 35, count 0 2006.218.08:16:58.19#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.218.08:16:58.19#ibcon#[25=USB\r\n] 2006.218.08:16:58.19#ibcon#*before write, iclass 35, count 0 2006.218.08:16:58.19#ibcon#enter sib2, iclass 35, count 0 2006.218.08:16:58.19#ibcon#flushed, iclass 35, count 0 2006.218.08:16:58.19#ibcon#about to write, iclass 35, count 0 2006.218.08:16:58.19#ibcon#wrote, iclass 35, count 0 2006.218.08:16:58.19#ibcon#about to read 3, iclass 35, count 0 2006.218.08:16:58.22#ibcon#read 3, iclass 35, count 0 2006.218.08:16:58.22#ibcon#about to read 4, iclass 35, count 0 2006.218.08:16:58.22#ibcon#read 4, iclass 35, count 0 2006.218.08:16:58.22#ibcon#about to read 5, iclass 35, count 0 2006.218.08:16:58.22#ibcon#read 5, iclass 35, count 0 2006.218.08:16:58.22#ibcon#about to read 6, iclass 35, count 0 2006.218.08:16:58.22#ibcon#read 6, iclass 35, count 0 2006.218.08:16:58.22#ibcon#end of sib2, iclass 35, count 0 2006.218.08:16:58.22#ibcon#*after write, iclass 35, count 0 2006.218.08:16:58.22#ibcon#*before return 0, iclass 35, count 0 2006.218.08:16:58.22#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.218.08:16:58.22#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.218.08:16:58.22#ibcon#about to clear, iclass 35 cls_cnt 0 2006.218.08:16:58.22#ibcon#cleared, iclass 35 cls_cnt 0 2006.218.08:16:58.22$vc4f8/valo=2,572.99 2006.218.08:16:58.22#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.218.08:16:58.22#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.218.08:16:58.22#ibcon#ireg 17 cls_cnt 0 2006.218.08:16:58.22#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.218.08:16:58.22#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.218.08:16:58.22#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.218.08:16:58.22#ibcon#enter wrdev, iclass 37, count 0 2006.218.08:16:58.22#ibcon#first serial, iclass 37, count 0 2006.218.08:16:58.22#ibcon#enter sib2, iclass 37, count 0 2006.218.08:16:58.22#ibcon#flushed, iclass 37, count 0 2006.218.08:16:58.22#ibcon#about to write, iclass 37, count 0 2006.218.08:16:58.22#ibcon#wrote, iclass 37, count 0 2006.218.08:16:58.22#ibcon#about to read 3, iclass 37, count 0 2006.218.08:16:58.24#ibcon#read 3, iclass 37, count 0 2006.218.08:16:58.24#ibcon#about to read 4, iclass 37, count 0 2006.218.08:16:58.24#ibcon#read 4, iclass 37, count 0 2006.218.08:16:58.24#ibcon#about to read 5, iclass 37, count 0 2006.218.08:16:58.24#ibcon#read 5, iclass 37, count 0 2006.218.08:16:58.24#ibcon#about to read 6, iclass 37, count 0 2006.218.08:16:58.24#ibcon#read 6, iclass 37, count 0 2006.218.08:16:58.24#ibcon#end of sib2, iclass 37, count 0 2006.218.08:16:58.24#ibcon#*mode == 0, iclass 37, count 0 2006.218.08:16:58.24#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.218.08:16:58.24#ibcon#[26=FRQ=02,572.99\r\n] 2006.218.08:16:58.24#ibcon#*before write, iclass 37, count 0 2006.218.08:16:58.24#ibcon#enter sib2, iclass 37, count 0 2006.218.08:16:58.24#ibcon#flushed, iclass 37, count 0 2006.218.08:16:58.24#ibcon#about to write, iclass 37, count 0 2006.218.08:16:58.24#ibcon#wrote, iclass 37, count 0 2006.218.08:16:58.24#ibcon#about to read 3, iclass 37, count 0 2006.218.08:16:58.29#ibcon#read 3, iclass 37, count 0 2006.218.08:16:58.29#ibcon#about to read 4, iclass 37, count 0 2006.218.08:16:58.29#ibcon#read 4, iclass 37, count 0 2006.218.08:16:58.29#ibcon#about to read 5, iclass 37, count 0 2006.218.08:16:58.29#ibcon#read 5, iclass 37, count 0 2006.218.08:16:58.29#ibcon#about to read 6, iclass 37, count 0 2006.218.08:16:58.29#ibcon#read 6, iclass 37, count 0 2006.218.08:16:58.29#ibcon#end of sib2, iclass 37, count 0 2006.218.08:16:58.29#ibcon#*after write, iclass 37, count 0 2006.218.08:16:58.29#ibcon#*before return 0, iclass 37, count 0 2006.218.08:16:58.29#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.218.08:16:58.29#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.218.08:16:58.29#ibcon#about to clear, iclass 37 cls_cnt 0 2006.218.08:16:58.29#ibcon#cleared, iclass 37 cls_cnt 0 2006.218.08:16:58.29$vc4f8/va=2,4 2006.218.08:16:58.29#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.218.08:16:58.29#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.218.08:16:58.29#ibcon#ireg 11 cls_cnt 2 2006.218.08:16:58.29#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.218.08:16:58.34#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.218.08:16:58.34#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.218.08:16:58.34#ibcon#enter wrdev, iclass 39, count 2 2006.218.08:16:58.34#ibcon#first serial, iclass 39, count 2 2006.218.08:16:58.34#ibcon#enter sib2, iclass 39, count 2 2006.218.08:16:58.34#ibcon#flushed, iclass 39, count 2 2006.218.08:16:58.34#ibcon#about to write, iclass 39, count 2 2006.218.08:16:58.34#ibcon#wrote, iclass 39, count 2 2006.218.08:16:58.34#ibcon#about to read 3, iclass 39, count 2 2006.218.08:16:58.36#ibcon#read 3, iclass 39, count 2 2006.218.08:16:58.36#ibcon#about to read 4, iclass 39, count 2 2006.218.08:16:58.36#ibcon#read 4, iclass 39, count 2 2006.218.08:16:58.36#ibcon#about to read 5, iclass 39, count 2 2006.218.08:16:58.36#ibcon#read 5, iclass 39, count 2 2006.218.08:16:58.36#ibcon#about to read 6, iclass 39, count 2 2006.218.08:16:58.36#ibcon#read 6, iclass 39, count 2 2006.218.08:16:58.36#ibcon#end of sib2, iclass 39, count 2 2006.218.08:16:58.36#ibcon#*mode == 0, iclass 39, count 2 2006.218.08:16:58.36#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.218.08:16:58.36#ibcon#[25=AT02-04\r\n] 2006.218.08:16:58.36#ibcon#*before write, iclass 39, count 2 2006.218.08:16:58.36#ibcon#enter sib2, iclass 39, count 2 2006.218.08:16:58.36#ibcon#flushed, iclass 39, count 2 2006.218.08:16:58.36#ibcon#about to write, iclass 39, count 2 2006.218.08:16:58.36#ibcon#wrote, iclass 39, count 2 2006.218.08:16:58.36#ibcon#about to read 3, iclass 39, count 2 2006.218.08:16:58.39#ibcon#read 3, iclass 39, count 2 2006.218.08:16:58.39#ibcon#about to read 4, iclass 39, count 2 2006.218.08:16:58.39#ibcon#read 4, iclass 39, count 2 2006.218.08:16:58.39#ibcon#about to read 5, iclass 39, count 2 2006.218.08:16:58.39#ibcon#read 5, iclass 39, count 2 2006.218.08:16:58.39#ibcon#about to read 6, iclass 39, count 2 2006.218.08:16:58.39#ibcon#read 6, iclass 39, count 2 2006.218.08:16:58.39#ibcon#end of sib2, iclass 39, count 2 2006.218.08:16:58.39#ibcon#*after write, iclass 39, count 2 2006.218.08:16:58.39#ibcon#*before return 0, iclass 39, count 2 2006.218.08:16:58.39#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.218.08:16:58.39#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.218.08:16:58.39#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.218.08:16:58.39#ibcon#ireg 7 cls_cnt 0 2006.218.08:16:58.39#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.218.08:16:58.51#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.218.08:16:58.51#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.218.08:16:58.51#ibcon#enter wrdev, iclass 39, count 0 2006.218.08:16:58.51#ibcon#first serial, iclass 39, count 0 2006.218.08:16:58.51#ibcon#enter sib2, iclass 39, count 0 2006.218.08:16:58.51#ibcon#flushed, iclass 39, count 0 2006.218.08:16:58.51#ibcon#about to write, iclass 39, count 0 2006.218.08:16:58.51#ibcon#wrote, iclass 39, count 0 2006.218.08:16:58.51#ibcon#about to read 3, iclass 39, count 0 2006.218.08:16:58.53#ibcon#read 3, iclass 39, count 0 2006.218.08:16:58.53#ibcon#about to read 4, iclass 39, count 0 2006.218.08:16:58.53#ibcon#read 4, iclass 39, count 0 2006.218.08:16:58.53#ibcon#about to read 5, iclass 39, count 0 2006.218.08:16:58.53#ibcon#read 5, iclass 39, count 0 2006.218.08:16:58.53#ibcon#about to read 6, iclass 39, count 0 2006.218.08:16:58.53#ibcon#read 6, iclass 39, count 0 2006.218.08:16:58.53#ibcon#end of sib2, iclass 39, count 0 2006.218.08:16:58.53#ibcon#*mode == 0, iclass 39, count 0 2006.218.08:16:58.53#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.218.08:16:58.53#ibcon#[25=USB\r\n] 2006.218.08:16:58.53#ibcon#*before write, iclass 39, count 0 2006.218.08:16:58.53#ibcon#enter sib2, iclass 39, count 0 2006.218.08:16:58.53#ibcon#flushed, iclass 39, count 0 2006.218.08:16:58.53#ibcon#about to write, iclass 39, count 0 2006.218.08:16:58.53#ibcon#wrote, iclass 39, count 0 2006.218.08:16:58.53#ibcon#about to read 3, iclass 39, count 0 2006.218.08:16:58.56#ibcon#read 3, iclass 39, count 0 2006.218.08:16:58.56#ibcon#about to read 4, iclass 39, count 0 2006.218.08:16:58.56#ibcon#read 4, iclass 39, count 0 2006.218.08:16:58.56#ibcon#about to read 5, iclass 39, count 0 2006.218.08:16:58.56#ibcon#read 5, iclass 39, count 0 2006.218.08:16:58.56#ibcon#about to read 6, iclass 39, count 0 2006.218.08:16:58.56#ibcon#read 6, iclass 39, count 0 2006.218.08:16:58.56#ibcon#end of sib2, iclass 39, count 0 2006.218.08:16:58.56#ibcon#*after write, iclass 39, count 0 2006.218.08:16:58.56#ibcon#*before return 0, iclass 39, count 0 2006.218.08:16:58.56#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.218.08:16:58.56#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.218.08:16:58.56#ibcon#about to clear, iclass 39 cls_cnt 0 2006.218.08:16:58.56#ibcon#cleared, iclass 39 cls_cnt 0 2006.218.08:16:58.56$vc4f8/valo=3,672.99 2006.218.08:16:58.56#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.218.08:16:58.56#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.218.08:16:58.56#ibcon#ireg 17 cls_cnt 0 2006.218.08:16:58.56#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.218.08:16:58.56#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.218.08:16:58.56#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.218.08:16:58.56#ibcon#enter wrdev, iclass 3, count 0 2006.218.08:16:58.56#ibcon#first serial, iclass 3, count 0 2006.218.08:16:58.56#ibcon#enter sib2, iclass 3, count 0 2006.218.08:16:58.56#ibcon#flushed, iclass 3, count 0 2006.218.08:16:58.56#ibcon#about to write, iclass 3, count 0 2006.218.08:16:58.56#ibcon#wrote, iclass 3, count 0 2006.218.08:16:58.56#ibcon#about to read 3, iclass 3, count 0 2006.218.08:16:58.58#ibcon#read 3, iclass 3, count 0 2006.218.08:16:58.58#ibcon#about to read 4, iclass 3, count 0 2006.218.08:16:58.58#ibcon#read 4, iclass 3, count 0 2006.218.08:16:58.58#ibcon#about to read 5, iclass 3, count 0 2006.218.08:16:58.58#ibcon#read 5, iclass 3, count 0 2006.218.08:16:58.58#ibcon#about to read 6, iclass 3, count 0 2006.218.08:16:58.58#ibcon#read 6, iclass 3, count 0 2006.218.08:16:58.58#ibcon#end of sib2, iclass 3, count 0 2006.218.08:16:58.58#ibcon#*mode == 0, iclass 3, count 0 2006.218.08:16:58.58#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.218.08:16:58.58#ibcon#[26=FRQ=03,672.99\r\n] 2006.218.08:16:58.58#ibcon#*before write, iclass 3, count 0 2006.218.08:16:58.58#ibcon#enter sib2, iclass 3, count 0 2006.218.08:16:58.58#ibcon#flushed, iclass 3, count 0 2006.218.08:16:58.58#ibcon#about to write, iclass 3, count 0 2006.218.08:16:58.58#ibcon#wrote, iclass 3, count 0 2006.218.08:16:58.58#ibcon#about to read 3, iclass 3, count 0 2006.218.08:16:58.62#ibcon#read 3, iclass 3, count 0 2006.218.08:16:58.62#ibcon#about to read 4, iclass 3, count 0 2006.218.08:16:58.62#ibcon#read 4, iclass 3, count 0 2006.218.08:16:58.62#ibcon#about to read 5, iclass 3, count 0 2006.218.08:16:58.62#ibcon#read 5, iclass 3, count 0 2006.218.08:16:58.62#ibcon#about to read 6, iclass 3, count 0 2006.218.08:16:58.62#ibcon#read 6, iclass 3, count 0 2006.218.08:16:58.62#ibcon#end of sib2, iclass 3, count 0 2006.218.08:16:58.62#ibcon#*after write, iclass 3, count 0 2006.218.08:16:58.62#ibcon#*before return 0, iclass 3, count 0 2006.218.08:16:58.62#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.218.08:16:58.62#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.218.08:16:58.62#ibcon#about to clear, iclass 3 cls_cnt 0 2006.218.08:16:58.62#ibcon#cleared, iclass 3 cls_cnt 0 2006.218.08:16:58.62$vc4f8/va=3,4 2006.218.08:16:58.62#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.218.08:16:58.62#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.218.08:16:58.62#ibcon#ireg 11 cls_cnt 2 2006.218.08:16:58.62#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.218.08:16:58.68#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.218.08:16:58.68#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.218.08:16:58.68#ibcon#enter wrdev, iclass 5, count 2 2006.218.08:16:58.68#ibcon#first serial, iclass 5, count 2 2006.218.08:16:58.68#ibcon#enter sib2, iclass 5, count 2 2006.218.08:16:58.68#ibcon#flushed, iclass 5, count 2 2006.218.08:16:58.68#ibcon#about to write, iclass 5, count 2 2006.218.08:16:58.68#ibcon#wrote, iclass 5, count 2 2006.218.08:16:58.68#ibcon#about to read 3, iclass 5, count 2 2006.218.08:16:58.70#ibcon#read 3, iclass 5, count 2 2006.218.08:16:58.70#ibcon#about to read 4, iclass 5, count 2 2006.218.08:16:58.70#ibcon#read 4, iclass 5, count 2 2006.218.08:16:58.70#ibcon#about to read 5, iclass 5, count 2 2006.218.08:16:58.70#ibcon#read 5, iclass 5, count 2 2006.218.08:16:58.70#ibcon#about to read 6, iclass 5, count 2 2006.218.08:16:58.70#ibcon#read 6, iclass 5, count 2 2006.218.08:16:58.70#ibcon#end of sib2, iclass 5, count 2 2006.218.08:16:58.70#ibcon#*mode == 0, iclass 5, count 2 2006.218.08:16:58.70#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.218.08:16:58.70#ibcon#[25=AT03-04\r\n] 2006.218.08:16:58.70#ibcon#*before write, iclass 5, count 2 2006.218.08:16:58.70#ibcon#enter sib2, iclass 5, count 2 2006.218.08:16:58.70#ibcon#flushed, iclass 5, count 2 2006.218.08:16:58.70#ibcon#about to write, iclass 5, count 2 2006.218.08:16:58.70#ibcon#wrote, iclass 5, count 2 2006.218.08:16:58.70#ibcon#about to read 3, iclass 5, count 2 2006.218.08:16:58.73#ibcon#read 3, iclass 5, count 2 2006.218.08:16:58.73#ibcon#about to read 4, iclass 5, count 2 2006.218.08:16:58.73#ibcon#read 4, iclass 5, count 2 2006.218.08:16:58.73#ibcon#about to read 5, iclass 5, count 2 2006.218.08:16:58.73#ibcon#read 5, iclass 5, count 2 2006.218.08:16:58.73#ibcon#about to read 6, iclass 5, count 2 2006.218.08:16:58.73#ibcon#read 6, iclass 5, count 2 2006.218.08:16:58.73#ibcon#end of sib2, iclass 5, count 2 2006.218.08:16:58.73#ibcon#*after write, iclass 5, count 2 2006.218.08:16:58.73#ibcon#*before return 0, iclass 5, count 2 2006.218.08:16:58.73#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.218.08:16:58.73#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.218.08:16:58.73#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.218.08:16:58.73#ibcon#ireg 7 cls_cnt 0 2006.218.08:16:58.73#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.218.08:16:58.85#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.218.08:16:58.85#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.218.08:16:58.85#ibcon#enter wrdev, iclass 5, count 0 2006.218.08:16:58.85#ibcon#first serial, iclass 5, count 0 2006.218.08:16:58.85#ibcon#enter sib2, iclass 5, count 0 2006.218.08:16:58.85#ibcon#flushed, iclass 5, count 0 2006.218.08:16:58.85#ibcon#about to write, iclass 5, count 0 2006.218.08:16:58.85#ibcon#wrote, iclass 5, count 0 2006.218.08:16:58.85#ibcon#about to read 3, iclass 5, count 0 2006.218.08:16:58.87#ibcon#read 3, iclass 5, count 0 2006.218.08:16:58.87#ibcon#about to read 4, iclass 5, count 0 2006.218.08:16:58.87#ibcon#read 4, iclass 5, count 0 2006.218.08:16:58.87#ibcon#about to read 5, iclass 5, count 0 2006.218.08:16:58.87#ibcon#read 5, iclass 5, count 0 2006.218.08:16:58.87#ibcon#about to read 6, iclass 5, count 0 2006.218.08:16:58.87#ibcon#read 6, iclass 5, count 0 2006.218.08:16:58.87#ibcon#end of sib2, iclass 5, count 0 2006.218.08:16:58.87#ibcon#*mode == 0, iclass 5, count 0 2006.218.08:16:58.87#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.218.08:16:58.87#ibcon#[25=USB\r\n] 2006.218.08:16:58.87#ibcon#*before write, iclass 5, count 0 2006.218.08:16:58.87#ibcon#enter sib2, iclass 5, count 0 2006.218.08:16:58.87#ibcon#flushed, iclass 5, count 0 2006.218.08:16:58.87#ibcon#about to write, iclass 5, count 0 2006.218.08:16:58.87#ibcon#wrote, iclass 5, count 0 2006.218.08:16:58.87#ibcon#about to read 3, iclass 5, count 0 2006.218.08:16:58.90#ibcon#read 3, iclass 5, count 0 2006.218.08:16:58.90#ibcon#about to read 4, iclass 5, count 0 2006.218.08:16:58.90#ibcon#read 4, iclass 5, count 0 2006.218.08:16:58.90#ibcon#about to read 5, iclass 5, count 0 2006.218.08:16:58.90#ibcon#read 5, iclass 5, count 0 2006.218.08:16:58.90#ibcon#about to read 6, iclass 5, count 0 2006.218.08:16:58.90#ibcon#read 6, iclass 5, count 0 2006.218.08:16:58.90#ibcon#end of sib2, iclass 5, count 0 2006.218.08:16:58.90#ibcon#*after write, iclass 5, count 0 2006.218.08:16:58.90#ibcon#*before return 0, iclass 5, count 0 2006.218.08:16:58.90#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.218.08:16:58.90#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.218.08:16:58.90#ibcon#about to clear, iclass 5 cls_cnt 0 2006.218.08:16:58.90#ibcon#cleared, iclass 5 cls_cnt 0 2006.218.08:16:58.90$vc4f8/valo=4,832.99 2006.218.08:16:58.90#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.218.08:16:58.90#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.218.08:16:58.90#ibcon#ireg 17 cls_cnt 0 2006.218.08:16:58.90#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.218.08:16:58.90#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.218.08:16:58.90#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.218.08:16:58.90#ibcon#enter wrdev, iclass 7, count 0 2006.218.08:16:58.90#ibcon#first serial, iclass 7, count 0 2006.218.08:16:58.90#ibcon#enter sib2, iclass 7, count 0 2006.218.08:16:58.90#ibcon#flushed, iclass 7, count 0 2006.218.08:16:58.90#ibcon#about to write, iclass 7, count 0 2006.218.08:16:58.90#ibcon#wrote, iclass 7, count 0 2006.218.08:16:58.90#ibcon#about to read 3, iclass 7, count 0 2006.218.08:16:58.92#ibcon#read 3, iclass 7, count 0 2006.218.08:16:58.92#ibcon#about to read 4, iclass 7, count 0 2006.218.08:16:58.92#ibcon#read 4, iclass 7, count 0 2006.218.08:16:58.92#ibcon#about to read 5, iclass 7, count 0 2006.218.08:16:58.92#ibcon#read 5, iclass 7, count 0 2006.218.08:16:58.92#ibcon#about to read 6, iclass 7, count 0 2006.218.08:16:58.92#ibcon#read 6, iclass 7, count 0 2006.218.08:16:58.92#ibcon#end of sib2, iclass 7, count 0 2006.218.08:16:58.92#ibcon#*mode == 0, iclass 7, count 0 2006.218.08:16:58.92#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.218.08:16:58.92#ibcon#[26=FRQ=04,832.99\r\n] 2006.218.08:16:58.92#ibcon#*before write, iclass 7, count 0 2006.218.08:16:58.92#ibcon#enter sib2, iclass 7, count 0 2006.218.08:16:58.92#ibcon#flushed, iclass 7, count 0 2006.218.08:16:58.92#ibcon#about to write, iclass 7, count 0 2006.218.08:16:58.92#ibcon#wrote, iclass 7, count 0 2006.218.08:16:58.92#ibcon#about to read 3, iclass 7, count 0 2006.218.08:16:58.96#ibcon#read 3, iclass 7, count 0 2006.218.08:16:58.96#ibcon#about to read 4, iclass 7, count 0 2006.218.08:16:58.96#ibcon#read 4, iclass 7, count 0 2006.218.08:16:58.96#ibcon#about to read 5, iclass 7, count 0 2006.218.08:16:58.96#ibcon#read 5, iclass 7, count 0 2006.218.08:16:58.96#ibcon#about to read 6, iclass 7, count 0 2006.218.08:16:58.96#ibcon#read 6, iclass 7, count 0 2006.218.08:16:58.96#ibcon#end of sib2, iclass 7, count 0 2006.218.08:16:58.96#ibcon#*after write, iclass 7, count 0 2006.218.08:16:58.96#ibcon#*before return 0, iclass 7, count 0 2006.218.08:16:58.96#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.218.08:16:58.96#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.218.08:16:58.96#ibcon#about to clear, iclass 7 cls_cnt 0 2006.218.08:16:58.96#ibcon#cleared, iclass 7 cls_cnt 0 2006.218.08:16:58.96$vc4f8/va=4,4 2006.218.08:16:58.96#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.218.08:16:58.96#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.218.08:16:58.96#ibcon#ireg 11 cls_cnt 2 2006.218.08:16:58.96#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.218.08:16:59.02#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.218.08:16:59.02#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.218.08:16:59.02#ibcon#enter wrdev, iclass 11, count 2 2006.218.08:16:59.02#ibcon#first serial, iclass 11, count 2 2006.218.08:16:59.02#ibcon#enter sib2, iclass 11, count 2 2006.218.08:16:59.02#ibcon#flushed, iclass 11, count 2 2006.218.08:16:59.02#ibcon#about to write, iclass 11, count 2 2006.218.08:16:59.02#ibcon#wrote, iclass 11, count 2 2006.218.08:16:59.02#ibcon#about to read 3, iclass 11, count 2 2006.218.08:16:59.04#ibcon#read 3, iclass 11, count 2 2006.218.08:16:59.04#ibcon#about to read 4, iclass 11, count 2 2006.218.08:16:59.04#ibcon#read 4, iclass 11, count 2 2006.218.08:16:59.04#ibcon#about to read 5, iclass 11, count 2 2006.218.08:16:59.04#ibcon#read 5, iclass 11, count 2 2006.218.08:16:59.04#ibcon#about to read 6, iclass 11, count 2 2006.218.08:16:59.04#ibcon#read 6, iclass 11, count 2 2006.218.08:16:59.04#ibcon#end of sib2, iclass 11, count 2 2006.218.08:16:59.04#ibcon#*mode == 0, iclass 11, count 2 2006.218.08:16:59.04#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.218.08:16:59.04#ibcon#[25=AT04-04\r\n] 2006.218.08:16:59.04#ibcon#*before write, iclass 11, count 2 2006.218.08:16:59.04#ibcon#enter sib2, iclass 11, count 2 2006.218.08:16:59.04#ibcon#flushed, iclass 11, count 2 2006.218.08:16:59.04#ibcon#about to write, iclass 11, count 2 2006.218.08:16:59.04#ibcon#wrote, iclass 11, count 2 2006.218.08:16:59.04#ibcon#about to read 3, iclass 11, count 2 2006.218.08:16:59.07#ibcon#read 3, iclass 11, count 2 2006.218.08:16:59.07#ibcon#about to read 4, iclass 11, count 2 2006.218.08:16:59.07#ibcon#read 4, iclass 11, count 2 2006.218.08:16:59.07#ibcon#about to read 5, iclass 11, count 2 2006.218.08:16:59.07#ibcon#read 5, iclass 11, count 2 2006.218.08:16:59.07#ibcon#about to read 6, iclass 11, count 2 2006.218.08:16:59.07#ibcon#read 6, iclass 11, count 2 2006.218.08:16:59.07#ibcon#end of sib2, iclass 11, count 2 2006.218.08:16:59.07#ibcon#*after write, iclass 11, count 2 2006.218.08:16:59.07#ibcon#*before return 0, iclass 11, count 2 2006.218.08:16:59.07#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.218.08:16:59.07#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.218.08:16:59.07#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.218.08:16:59.07#ibcon#ireg 7 cls_cnt 0 2006.218.08:16:59.07#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.218.08:16:59.19#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.218.08:16:59.19#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.218.08:16:59.19#ibcon#enter wrdev, iclass 11, count 0 2006.218.08:16:59.19#ibcon#first serial, iclass 11, count 0 2006.218.08:16:59.19#ibcon#enter sib2, iclass 11, count 0 2006.218.08:16:59.19#ibcon#flushed, iclass 11, count 0 2006.218.08:16:59.19#ibcon#about to write, iclass 11, count 0 2006.218.08:16:59.19#ibcon#wrote, iclass 11, count 0 2006.218.08:16:59.19#ibcon#about to read 3, iclass 11, count 0 2006.218.08:16:59.21#ibcon#read 3, iclass 11, count 0 2006.218.08:16:59.21#ibcon#about to read 4, iclass 11, count 0 2006.218.08:16:59.21#ibcon#read 4, iclass 11, count 0 2006.218.08:16:59.21#ibcon#about to read 5, iclass 11, count 0 2006.218.08:16:59.21#ibcon#read 5, iclass 11, count 0 2006.218.08:16:59.21#ibcon#about to read 6, iclass 11, count 0 2006.218.08:16:59.21#ibcon#read 6, iclass 11, count 0 2006.218.08:16:59.21#ibcon#end of sib2, iclass 11, count 0 2006.218.08:16:59.21#ibcon#*mode == 0, iclass 11, count 0 2006.218.08:16:59.21#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.218.08:16:59.21#ibcon#[25=USB\r\n] 2006.218.08:16:59.21#ibcon#*before write, iclass 11, count 0 2006.218.08:16:59.21#ibcon#enter sib2, iclass 11, count 0 2006.218.08:16:59.21#ibcon#flushed, iclass 11, count 0 2006.218.08:16:59.21#ibcon#about to write, iclass 11, count 0 2006.218.08:16:59.21#ibcon#wrote, iclass 11, count 0 2006.218.08:16:59.21#ibcon#about to read 3, iclass 11, count 0 2006.218.08:16:59.24#ibcon#read 3, iclass 11, count 0 2006.218.08:16:59.24#ibcon#about to read 4, iclass 11, count 0 2006.218.08:16:59.24#ibcon#read 4, iclass 11, count 0 2006.218.08:16:59.24#ibcon#about to read 5, iclass 11, count 0 2006.218.08:16:59.24#ibcon#read 5, iclass 11, count 0 2006.218.08:16:59.24#ibcon#about to read 6, iclass 11, count 0 2006.218.08:16:59.24#ibcon#read 6, iclass 11, count 0 2006.218.08:16:59.24#ibcon#end of sib2, iclass 11, count 0 2006.218.08:16:59.24#ibcon#*after write, iclass 11, count 0 2006.218.08:16:59.24#ibcon#*before return 0, iclass 11, count 0 2006.218.08:16:59.24#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.218.08:16:59.24#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.218.08:16:59.24#ibcon#about to clear, iclass 11 cls_cnt 0 2006.218.08:16:59.24#ibcon#cleared, iclass 11 cls_cnt 0 2006.218.08:16:59.24$vc4f8/valo=5,652.99 2006.218.08:16:59.24#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.218.08:16:59.24#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.218.08:16:59.24#ibcon#ireg 17 cls_cnt 0 2006.218.08:16:59.24#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.218.08:16:59.24#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.218.08:16:59.24#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.218.08:16:59.24#ibcon#enter wrdev, iclass 13, count 0 2006.218.08:16:59.24#ibcon#first serial, iclass 13, count 0 2006.218.08:16:59.24#ibcon#enter sib2, iclass 13, count 0 2006.218.08:16:59.24#ibcon#flushed, iclass 13, count 0 2006.218.08:16:59.24#ibcon#about to write, iclass 13, count 0 2006.218.08:16:59.24#ibcon#wrote, iclass 13, count 0 2006.218.08:16:59.24#ibcon#about to read 3, iclass 13, count 0 2006.218.08:16:59.26#ibcon#read 3, iclass 13, count 0 2006.218.08:16:59.26#ibcon#about to read 4, iclass 13, count 0 2006.218.08:16:59.26#ibcon#read 4, iclass 13, count 0 2006.218.08:16:59.26#ibcon#about to read 5, iclass 13, count 0 2006.218.08:16:59.26#ibcon#read 5, iclass 13, count 0 2006.218.08:16:59.26#ibcon#about to read 6, iclass 13, count 0 2006.218.08:16:59.26#ibcon#read 6, iclass 13, count 0 2006.218.08:16:59.26#ibcon#end of sib2, iclass 13, count 0 2006.218.08:16:59.26#ibcon#*mode == 0, iclass 13, count 0 2006.218.08:16:59.26#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.218.08:16:59.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.218.08:16:59.26#ibcon#*before write, iclass 13, count 0 2006.218.08:16:59.26#ibcon#enter sib2, iclass 13, count 0 2006.218.08:16:59.26#ibcon#flushed, iclass 13, count 0 2006.218.08:16:59.26#ibcon#about to write, iclass 13, count 0 2006.218.08:16:59.26#ibcon#wrote, iclass 13, count 0 2006.218.08:16:59.26#ibcon#about to read 3, iclass 13, count 0 2006.218.08:16:59.30#ibcon#read 3, iclass 13, count 0 2006.218.08:16:59.30#ibcon#about to read 4, iclass 13, count 0 2006.218.08:16:59.30#ibcon#read 4, iclass 13, count 0 2006.218.08:16:59.30#ibcon#about to read 5, iclass 13, count 0 2006.218.08:16:59.30#ibcon#read 5, iclass 13, count 0 2006.218.08:16:59.30#ibcon#about to read 6, iclass 13, count 0 2006.218.08:16:59.30#ibcon#read 6, iclass 13, count 0 2006.218.08:16:59.30#ibcon#end of sib2, iclass 13, count 0 2006.218.08:16:59.30#ibcon#*after write, iclass 13, count 0 2006.218.08:16:59.30#ibcon#*before return 0, iclass 13, count 0 2006.218.08:16:59.30#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.218.08:16:59.30#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.218.08:16:59.30#ibcon#about to clear, iclass 13 cls_cnt 0 2006.218.08:16:59.30#ibcon#cleared, iclass 13 cls_cnt 0 2006.218.08:16:59.30$vc4f8/va=5,7 2006.218.08:16:59.30#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.218.08:16:59.30#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.218.08:16:59.30#ibcon#ireg 11 cls_cnt 2 2006.218.08:16:59.30#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.218.08:16:59.36#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.218.08:16:59.36#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.218.08:16:59.36#ibcon#enter wrdev, iclass 15, count 2 2006.218.08:16:59.36#ibcon#first serial, iclass 15, count 2 2006.218.08:16:59.36#ibcon#enter sib2, iclass 15, count 2 2006.218.08:16:59.36#ibcon#flushed, iclass 15, count 2 2006.218.08:16:59.36#ibcon#about to write, iclass 15, count 2 2006.218.08:16:59.36#ibcon#wrote, iclass 15, count 2 2006.218.08:16:59.36#ibcon#about to read 3, iclass 15, count 2 2006.218.08:16:59.38#ibcon#read 3, iclass 15, count 2 2006.218.08:16:59.38#ibcon#about to read 4, iclass 15, count 2 2006.218.08:16:59.38#ibcon#read 4, iclass 15, count 2 2006.218.08:16:59.38#ibcon#about to read 5, iclass 15, count 2 2006.218.08:16:59.38#ibcon#read 5, iclass 15, count 2 2006.218.08:16:59.38#ibcon#about to read 6, iclass 15, count 2 2006.218.08:16:59.38#ibcon#read 6, iclass 15, count 2 2006.218.08:16:59.38#ibcon#end of sib2, iclass 15, count 2 2006.218.08:16:59.38#ibcon#*mode == 0, iclass 15, count 2 2006.218.08:16:59.38#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.218.08:16:59.38#ibcon#[25=AT05-07\r\n] 2006.218.08:16:59.38#ibcon#*before write, iclass 15, count 2 2006.218.08:16:59.38#ibcon#enter sib2, iclass 15, count 2 2006.218.08:16:59.38#ibcon#flushed, iclass 15, count 2 2006.218.08:16:59.38#ibcon#about to write, iclass 15, count 2 2006.218.08:16:59.38#ibcon#wrote, iclass 15, count 2 2006.218.08:16:59.38#ibcon#about to read 3, iclass 15, count 2 2006.218.08:16:59.41#ibcon#read 3, iclass 15, count 2 2006.218.08:16:59.41#ibcon#about to read 4, iclass 15, count 2 2006.218.08:16:59.41#ibcon#read 4, iclass 15, count 2 2006.218.08:16:59.41#ibcon#about to read 5, iclass 15, count 2 2006.218.08:16:59.41#ibcon#read 5, iclass 15, count 2 2006.218.08:16:59.41#ibcon#about to read 6, iclass 15, count 2 2006.218.08:16:59.41#ibcon#read 6, iclass 15, count 2 2006.218.08:16:59.41#ibcon#end of sib2, iclass 15, count 2 2006.218.08:16:59.41#ibcon#*after write, iclass 15, count 2 2006.218.08:16:59.41#ibcon#*before return 0, iclass 15, count 2 2006.218.08:16:59.41#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.218.08:16:59.41#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.218.08:16:59.41#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.218.08:16:59.41#ibcon#ireg 7 cls_cnt 0 2006.218.08:16:59.41#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.218.08:16:59.53#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.218.08:16:59.53#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.218.08:16:59.53#ibcon#enter wrdev, iclass 15, count 0 2006.218.08:16:59.53#ibcon#first serial, iclass 15, count 0 2006.218.08:16:59.53#ibcon#enter sib2, iclass 15, count 0 2006.218.08:16:59.53#ibcon#flushed, iclass 15, count 0 2006.218.08:16:59.53#ibcon#about to write, iclass 15, count 0 2006.218.08:16:59.53#ibcon#wrote, iclass 15, count 0 2006.218.08:16:59.53#ibcon#about to read 3, iclass 15, count 0 2006.218.08:16:59.55#ibcon#read 3, iclass 15, count 0 2006.218.08:16:59.55#ibcon#about to read 4, iclass 15, count 0 2006.218.08:16:59.55#ibcon#read 4, iclass 15, count 0 2006.218.08:16:59.55#ibcon#about to read 5, iclass 15, count 0 2006.218.08:16:59.55#ibcon#read 5, iclass 15, count 0 2006.218.08:16:59.55#ibcon#about to read 6, iclass 15, count 0 2006.218.08:16:59.55#ibcon#read 6, iclass 15, count 0 2006.218.08:16:59.55#ibcon#end of sib2, iclass 15, count 0 2006.218.08:16:59.55#ibcon#*mode == 0, iclass 15, count 0 2006.218.08:16:59.55#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.218.08:16:59.55#ibcon#[25=USB\r\n] 2006.218.08:16:59.55#ibcon#*before write, iclass 15, count 0 2006.218.08:16:59.55#ibcon#enter sib2, iclass 15, count 0 2006.218.08:16:59.55#ibcon#flushed, iclass 15, count 0 2006.218.08:16:59.55#ibcon#about to write, iclass 15, count 0 2006.218.08:16:59.55#ibcon#wrote, iclass 15, count 0 2006.218.08:16:59.55#ibcon#about to read 3, iclass 15, count 0 2006.218.08:16:59.58#ibcon#read 3, iclass 15, count 0 2006.218.08:16:59.58#ibcon#about to read 4, iclass 15, count 0 2006.218.08:16:59.58#ibcon#read 4, iclass 15, count 0 2006.218.08:16:59.58#ibcon#about to read 5, iclass 15, count 0 2006.218.08:16:59.58#ibcon#read 5, iclass 15, count 0 2006.218.08:16:59.58#ibcon#about to read 6, iclass 15, count 0 2006.218.08:16:59.58#ibcon#read 6, iclass 15, count 0 2006.218.08:16:59.58#ibcon#end of sib2, iclass 15, count 0 2006.218.08:16:59.58#ibcon#*after write, iclass 15, count 0 2006.218.08:16:59.58#ibcon#*before return 0, iclass 15, count 0 2006.218.08:16:59.58#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.218.08:16:59.58#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.218.08:16:59.58#ibcon#about to clear, iclass 15 cls_cnt 0 2006.218.08:16:59.58#ibcon#cleared, iclass 15 cls_cnt 0 2006.218.08:16:59.58$vc4f8/valo=6,772.99 2006.218.08:16:59.58#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.218.08:16:59.58#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.218.08:16:59.58#ibcon#ireg 17 cls_cnt 0 2006.218.08:16:59.58#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.218.08:16:59.58#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.218.08:16:59.58#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.218.08:16:59.58#ibcon#enter wrdev, iclass 17, count 0 2006.218.08:16:59.58#ibcon#first serial, iclass 17, count 0 2006.218.08:16:59.58#ibcon#enter sib2, iclass 17, count 0 2006.218.08:16:59.58#ibcon#flushed, iclass 17, count 0 2006.218.08:16:59.58#ibcon#about to write, iclass 17, count 0 2006.218.08:16:59.58#ibcon#wrote, iclass 17, count 0 2006.218.08:16:59.58#ibcon#about to read 3, iclass 17, count 0 2006.218.08:16:59.60#ibcon#read 3, iclass 17, count 0 2006.218.08:16:59.60#ibcon#about to read 4, iclass 17, count 0 2006.218.08:16:59.60#ibcon#read 4, iclass 17, count 0 2006.218.08:16:59.60#ibcon#about to read 5, iclass 17, count 0 2006.218.08:16:59.60#ibcon#read 5, iclass 17, count 0 2006.218.08:16:59.60#ibcon#about to read 6, iclass 17, count 0 2006.218.08:16:59.60#ibcon#read 6, iclass 17, count 0 2006.218.08:16:59.60#ibcon#end of sib2, iclass 17, count 0 2006.218.08:16:59.60#ibcon#*mode == 0, iclass 17, count 0 2006.218.08:16:59.60#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.218.08:16:59.60#ibcon#[26=FRQ=06,772.99\r\n] 2006.218.08:16:59.60#ibcon#*before write, iclass 17, count 0 2006.218.08:16:59.60#ibcon#enter sib2, iclass 17, count 0 2006.218.08:16:59.60#ibcon#flushed, iclass 17, count 0 2006.218.08:16:59.60#ibcon#about to write, iclass 17, count 0 2006.218.08:16:59.60#ibcon#wrote, iclass 17, count 0 2006.218.08:16:59.60#ibcon#about to read 3, iclass 17, count 0 2006.218.08:16:59.64#ibcon#read 3, iclass 17, count 0 2006.218.08:16:59.64#ibcon#about to read 4, iclass 17, count 0 2006.218.08:16:59.64#ibcon#read 4, iclass 17, count 0 2006.218.08:16:59.64#ibcon#about to read 5, iclass 17, count 0 2006.218.08:16:59.64#ibcon#read 5, iclass 17, count 0 2006.218.08:16:59.64#ibcon#about to read 6, iclass 17, count 0 2006.218.08:16:59.64#ibcon#read 6, iclass 17, count 0 2006.218.08:16:59.64#ibcon#end of sib2, iclass 17, count 0 2006.218.08:16:59.64#ibcon#*after write, iclass 17, count 0 2006.218.08:16:59.64#ibcon#*before return 0, iclass 17, count 0 2006.218.08:16:59.64#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.218.08:16:59.64#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.218.08:16:59.64#ibcon#about to clear, iclass 17 cls_cnt 0 2006.218.08:16:59.64#ibcon#cleared, iclass 17 cls_cnt 0 2006.218.08:16:59.64$vc4f8/va=6,6 2006.218.08:16:59.64#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.218.08:16:59.64#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.218.08:16:59.64#ibcon#ireg 11 cls_cnt 2 2006.218.08:16:59.64#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.218.08:16:59.70#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.218.08:16:59.70#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.218.08:16:59.70#ibcon#enter wrdev, iclass 19, count 2 2006.218.08:16:59.70#ibcon#first serial, iclass 19, count 2 2006.218.08:16:59.70#ibcon#enter sib2, iclass 19, count 2 2006.218.08:16:59.70#ibcon#flushed, iclass 19, count 2 2006.218.08:16:59.70#ibcon#about to write, iclass 19, count 2 2006.218.08:16:59.70#ibcon#wrote, iclass 19, count 2 2006.218.08:16:59.70#ibcon#about to read 3, iclass 19, count 2 2006.218.08:16:59.72#ibcon#read 3, iclass 19, count 2 2006.218.08:16:59.72#ibcon#about to read 4, iclass 19, count 2 2006.218.08:16:59.72#ibcon#read 4, iclass 19, count 2 2006.218.08:16:59.72#ibcon#about to read 5, iclass 19, count 2 2006.218.08:16:59.72#ibcon#read 5, iclass 19, count 2 2006.218.08:16:59.72#ibcon#about to read 6, iclass 19, count 2 2006.218.08:16:59.72#ibcon#read 6, iclass 19, count 2 2006.218.08:16:59.72#ibcon#end of sib2, iclass 19, count 2 2006.218.08:16:59.72#ibcon#*mode == 0, iclass 19, count 2 2006.218.08:16:59.72#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.218.08:16:59.72#ibcon#[25=AT06-06\r\n] 2006.218.08:16:59.72#ibcon#*before write, iclass 19, count 2 2006.218.08:16:59.72#ibcon#enter sib2, iclass 19, count 2 2006.218.08:16:59.72#ibcon#flushed, iclass 19, count 2 2006.218.08:16:59.72#ibcon#about to write, iclass 19, count 2 2006.218.08:16:59.72#ibcon#wrote, iclass 19, count 2 2006.218.08:16:59.72#ibcon#about to read 3, iclass 19, count 2 2006.218.08:16:59.75#ibcon#read 3, iclass 19, count 2 2006.218.08:16:59.75#ibcon#about to read 4, iclass 19, count 2 2006.218.08:16:59.75#ibcon#read 4, iclass 19, count 2 2006.218.08:16:59.75#ibcon#about to read 5, iclass 19, count 2 2006.218.08:16:59.75#ibcon#read 5, iclass 19, count 2 2006.218.08:16:59.75#ibcon#about to read 6, iclass 19, count 2 2006.218.08:16:59.75#ibcon#read 6, iclass 19, count 2 2006.218.08:16:59.75#ibcon#end of sib2, iclass 19, count 2 2006.218.08:16:59.75#ibcon#*after write, iclass 19, count 2 2006.218.08:16:59.75#ibcon#*before return 0, iclass 19, count 2 2006.218.08:16:59.75#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.218.08:16:59.75#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.218.08:16:59.75#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.218.08:16:59.75#ibcon#ireg 7 cls_cnt 0 2006.218.08:16:59.75#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.218.08:16:59.87#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.218.08:16:59.87#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.218.08:16:59.87#ibcon#enter wrdev, iclass 19, count 0 2006.218.08:16:59.87#ibcon#first serial, iclass 19, count 0 2006.218.08:16:59.87#ibcon#enter sib2, iclass 19, count 0 2006.218.08:16:59.87#ibcon#flushed, iclass 19, count 0 2006.218.08:16:59.87#ibcon#about to write, iclass 19, count 0 2006.218.08:16:59.87#ibcon#wrote, iclass 19, count 0 2006.218.08:16:59.87#ibcon#about to read 3, iclass 19, count 0 2006.218.08:16:59.89#ibcon#read 3, iclass 19, count 0 2006.218.08:16:59.89#ibcon#about to read 4, iclass 19, count 0 2006.218.08:16:59.89#ibcon#read 4, iclass 19, count 0 2006.218.08:16:59.89#ibcon#about to read 5, iclass 19, count 0 2006.218.08:16:59.89#ibcon#read 5, iclass 19, count 0 2006.218.08:16:59.89#ibcon#about to read 6, iclass 19, count 0 2006.218.08:16:59.89#ibcon#read 6, iclass 19, count 0 2006.218.08:16:59.89#ibcon#end of sib2, iclass 19, count 0 2006.218.08:16:59.89#ibcon#*mode == 0, iclass 19, count 0 2006.218.08:16:59.89#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.218.08:16:59.89#ibcon#[25=USB\r\n] 2006.218.08:16:59.89#ibcon#*before write, iclass 19, count 0 2006.218.08:16:59.89#ibcon#enter sib2, iclass 19, count 0 2006.218.08:16:59.89#ibcon#flushed, iclass 19, count 0 2006.218.08:16:59.89#ibcon#about to write, iclass 19, count 0 2006.218.08:16:59.89#ibcon#wrote, iclass 19, count 0 2006.218.08:16:59.89#ibcon#about to read 3, iclass 19, count 0 2006.218.08:16:59.92#ibcon#read 3, iclass 19, count 0 2006.218.08:16:59.92#ibcon#about to read 4, iclass 19, count 0 2006.218.08:16:59.92#ibcon#read 4, iclass 19, count 0 2006.218.08:16:59.92#ibcon#about to read 5, iclass 19, count 0 2006.218.08:16:59.92#ibcon#read 5, iclass 19, count 0 2006.218.08:16:59.92#ibcon#about to read 6, iclass 19, count 0 2006.218.08:16:59.92#ibcon#read 6, iclass 19, count 0 2006.218.08:16:59.92#ibcon#end of sib2, iclass 19, count 0 2006.218.08:16:59.92#ibcon#*after write, iclass 19, count 0 2006.218.08:16:59.92#ibcon#*before return 0, iclass 19, count 0 2006.218.08:16:59.92#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.218.08:16:59.92#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.218.08:16:59.92#ibcon#about to clear, iclass 19 cls_cnt 0 2006.218.08:16:59.92#ibcon#cleared, iclass 19 cls_cnt 0 2006.218.08:16:59.92$vc4f8/valo=7,832.99 2006.218.08:16:59.92#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.218.08:16:59.92#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.218.08:16:59.92#ibcon#ireg 17 cls_cnt 0 2006.218.08:16:59.92#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.218.08:16:59.92#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.218.08:16:59.92#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.218.08:16:59.92#ibcon#enter wrdev, iclass 21, count 0 2006.218.08:16:59.92#ibcon#first serial, iclass 21, count 0 2006.218.08:16:59.92#ibcon#enter sib2, iclass 21, count 0 2006.218.08:16:59.92#ibcon#flushed, iclass 21, count 0 2006.218.08:16:59.92#ibcon#about to write, iclass 21, count 0 2006.218.08:16:59.92#ibcon#wrote, iclass 21, count 0 2006.218.08:16:59.92#ibcon#about to read 3, iclass 21, count 0 2006.218.08:16:59.94#ibcon#read 3, iclass 21, count 0 2006.218.08:16:59.94#ibcon#about to read 4, iclass 21, count 0 2006.218.08:16:59.94#ibcon#read 4, iclass 21, count 0 2006.218.08:16:59.94#ibcon#about to read 5, iclass 21, count 0 2006.218.08:16:59.94#ibcon#read 5, iclass 21, count 0 2006.218.08:16:59.94#ibcon#about to read 6, iclass 21, count 0 2006.218.08:16:59.94#ibcon#read 6, iclass 21, count 0 2006.218.08:16:59.94#ibcon#end of sib2, iclass 21, count 0 2006.218.08:16:59.94#ibcon#*mode == 0, iclass 21, count 0 2006.218.08:16:59.94#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.218.08:16:59.94#ibcon#[26=FRQ=07,832.99\r\n] 2006.218.08:16:59.94#ibcon#*before write, iclass 21, count 0 2006.218.08:16:59.94#ibcon#enter sib2, iclass 21, count 0 2006.218.08:16:59.94#ibcon#flushed, iclass 21, count 0 2006.218.08:16:59.94#ibcon#about to write, iclass 21, count 0 2006.218.08:16:59.94#ibcon#wrote, iclass 21, count 0 2006.218.08:16:59.94#ibcon#about to read 3, iclass 21, count 0 2006.218.08:16:59.98#ibcon#read 3, iclass 21, count 0 2006.218.08:16:59.98#ibcon#about to read 4, iclass 21, count 0 2006.218.08:16:59.98#ibcon#read 4, iclass 21, count 0 2006.218.08:16:59.98#ibcon#about to read 5, iclass 21, count 0 2006.218.08:16:59.98#ibcon#read 5, iclass 21, count 0 2006.218.08:16:59.98#ibcon#about to read 6, iclass 21, count 0 2006.218.08:16:59.98#ibcon#read 6, iclass 21, count 0 2006.218.08:16:59.98#ibcon#end of sib2, iclass 21, count 0 2006.218.08:16:59.98#ibcon#*after write, iclass 21, count 0 2006.218.08:16:59.98#ibcon#*before return 0, iclass 21, count 0 2006.218.08:16:59.98#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.218.08:16:59.98#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.218.08:16:59.98#ibcon#about to clear, iclass 21 cls_cnt 0 2006.218.08:16:59.98#ibcon#cleared, iclass 21 cls_cnt 0 2006.218.08:16:59.98$vc4f8/va=7,6 2006.218.08:16:59.98#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.218.08:16:59.98#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.218.08:16:59.98#ibcon#ireg 11 cls_cnt 2 2006.218.08:16:59.98#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.218.08:17:00.04#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.218.08:17:00.04#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.218.08:17:00.04#ibcon#enter wrdev, iclass 23, count 2 2006.218.08:17:00.04#ibcon#first serial, iclass 23, count 2 2006.218.08:17:00.04#ibcon#enter sib2, iclass 23, count 2 2006.218.08:17:00.04#ibcon#flushed, iclass 23, count 2 2006.218.08:17:00.04#ibcon#about to write, iclass 23, count 2 2006.218.08:17:00.04#ibcon#wrote, iclass 23, count 2 2006.218.08:17:00.04#ibcon#about to read 3, iclass 23, count 2 2006.218.08:17:00.06#ibcon#read 3, iclass 23, count 2 2006.218.08:17:00.06#ibcon#about to read 4, iclass 23, count 2 2006.218.08:17:00.06#ibcon#read 4, iclass 23, count 2 2006.218.08:17:00.06#ibcon#about to read 5, iclass 23, count 2 2006.218.08:17:00.06#ibcon#read 5, iclass 23, count 2 2006.218.08:17:00.06#ibcon#about to read 6, iclass 23, count 2 2006.218.08:17:00.06#ibcon#read 6, iclass 23, count 2 2006.218.08:17:00.06#ibcon#end of sib2, iclass 23, count 2 2006.218.08:17:00.06#ibcon#*mode == 0, iclass 23, count 2 2006.218.08:17:00.06#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.218.08:17:00.06#ibcon#[25=AT07-06\r\n] 2006.218.08:17:00.06#ibcon#*before write, iclass 23, count 2 2006.218.08:17:00.06#ibcon#enter sib2, iclass 23, count 2 2006.218.08:17:00.06#ibcon#flushed, iclass 23, count 2 2006.218.08:17:00.06#ibcon#about to write, iclass 23, count 2 2006.218.08:17:00.06#ibcon#wrote, iclass 23, count 2 2006.218.08:17:00.06#ibcon#about to read 3, iclass 23, count 2 2006.218.08:17:00.09#ibcon#read 3, iclass 23, count 2 2006.218.08:17:00.09#ibcon#about to read 4, iclass 23, count 2 2006.218.08:17:00.09#ibcon#read 4, iclass 23, count 2 2006.218.08:17:00.09#ibcon#about to read 5, iclass 23, count 2 2006.218.08:17:00.09#ibcon#read 5, iclass 23, count 2 2006.218.08:17:00.09#ibcon#about to read 6, iclass 23, count 2 2006.218.08:17:00.09#ibcon#read 6, iclass 23, count 2 2006.218.08:17:00.09#ibcon#end of sib2, iclass 23, count 2 2006.218.08:17:00.09#ibcon#*after write, iclass 23, count 2 2006.218.08:17:00.09#ibcon#*before return 0, iclass 23, count 2 2006.218.08:17:00.09#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.218.08:17:00.09#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.218.08:17:00.09#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.218.08:17:00.09#ibcon#ireg 7 cls_cnt 0 2006.218.08:17:00.09#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.218.08:17:00.21#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.218.08:17:00.21#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.218.08:17:00.21#ibcon#enter wrdev, iclass 23, count 0 2006.218.08:17:00.21#ibcon#first serial, iclass 23, count 0 2006.218.08:17:00.21#ibcon#enter sib2, iclass 23, count 0 2006.218.08:17:00.21#ibcon#flushed, iclass 23, count 0 2006.218.08:17:00.21#ibcon#about to write, iclass 23, count 0 2006.218.08:17:00.21#ibcon#wrote, iclass 23, count 0 2006.218.08:17:00.21#ibcon#about to read 3, iclass 23, count 0 2006.218.08:17:00.23#ibcon#read 3, iclass 23, count 0 2006.218.08:17:00.23#ibcon#about to read 4, iclass 23, count 0 2006.218.08:17:00.23#ibcon#read 4, iclass 23, count 0 2006.218.08:17:00.23#ibcon#about to read 5, iclass 23, count 0 2006.218.08:17:00.23#ibcon#read 5, iclass 23, count 0 2006.218.08:17:00.23#ibcon#about to read 6, iclass 23, count 0 2006.218.08:17:00.23#ibcon#read 6, iclass 23, count 0 2006.218.08:17:00.23#ibcon#end of sib2, iclass 23, count 0 2006.218.08:17:00.23#ibcon#*mode == 0, iclass 23, count 0 2006.218.08:17:00.23#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.218.08:17:00.23#ibcon#[25=USB\r\n] 2006.218.08:17:00.23#ibcon#*before write, iclass 23, count 0 2006.218.08:17:00.23#ibcon#enter sib2, iclass 23, count 0 2006.218.08:17:00.23#ibcon#flushed, iclass 23, count 0 2006.218.08:17:00.23#ibcon#about to write, iclass 23, count 0 2006.218.08:17:00.23#ibcon#wrote, iclass 23, count 0 2006.218.08:17:00.23#ibcon#about to read 3, iclass 23, count 0 2006.218.08:17:00.26#ibcon#read 3, iclass 23, count 0 2006.218.08:17:00.26#ibcon#about to read 4, iclass 23, count 0 2006.218.08:17:00.26#ibcon#read 4, iclass 23, count 0 2006.218.08:17:00.26#ibcon#about to read 5, iclass 23, count 0 2006.218.08:17:00.26#ibcon#read 5, iclass 23, count 0 2006.218.08:17:00.26#ibcon#about to read 6, iclass 23, count 0 2006.218.08:17:00.26#ibcon#read 6, iclass 23, count 0 2006.218.08:17:00.26#ibcon#end of sib2, iclass 23, count 0 2006.218.08:17:00.26#ibcon#*after write, iclass 23, count 0 2006.218.08:17:00.26#ibcon#*before return 0, iclass 23, count 0 2006.218.08:17:00.26#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.218.08:17:00.26#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.218.08:17:00.26#ibcon#about to clear, iclass 23 cls_cnt 0 2006.218.08:17:00.26#ibcon#cleared, iclass 23 cls_cnt 0 2006.218.08:17:00.26$vc4f8/valo=8,852.99 2006.218.08:17:00.26#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.218.08:17:00.26#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.218.08:17:00.26#ibcon#ireg 17 cls_cnt 0 2006.218.08:17:00.26#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.218.08:17:00.26#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.218.08:17:00.26#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.218.08:17:00.26#ibcon#enter wrdev, iclass 25, count 0 2006.218.08:17:00.26#ibcon#first serial, iclass 25, count 0 2006.218.08:17:00.26#ibcon#enter sib2, iclass 25, count 0 2006.218.08:17:00.26#ibcon#flushed, iclass 25, count 0 2006.218.08:17:00.26#ibcon#about to write, iclass 25, count 0 2006.218.08:17:00.26#ibcon#wrote, iclass 25, count 0 2006.218.08:17:00.26#ibcon#about to read 3, iclass 25, count 0 2006.218.08:17:00.28#ibcon#read 3, iclass 25, count 0 2006.218.08:17:00.28#ibcon#about to read 4, iclass 25, count 0 2006.218.08:17:00.28#ibcon#read 4, iclass 25, count 0 2006.218.08:17:00.28#ibcon#about to read 5, iclass 25, count 0 2006.218.08:17:00.28#ibcon#read 5, iclass 25, count 0 2006.218.08:17:00.28#ibcon#about to read 6, iclass 25, count 0 2006.218.08:17:00.28#ibcon#read 6, iclass 25, count 0 2006.218.08:17:00.28#ibcon#end of sib2, iclass 25, count 0 2006.218.08:17:00.28#ibcon#*mode == 0, iclass 25, count 0 2006.218.08:17:00.28#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.218.08:17:00.28#ibcon#[26=FRQ=08,852.99\r\n] 2006.218.08:17:00.28#ibcon#*before write, iclass 25, count 0 2006.218.08:17:00.28#ibcon#enter sib2, iclass 25, count 0 2006.218.08:17:00.28#ibcon#flushed, iclass 25, count 0 2006.218.08:17:00.28#ibcon#about to write, iclass 25, count 0 2006.218.08:17:00.28#ibcon#wrote, iclass 25, count 0 2006.218.08:17:00.28#ibcon#about to read 3, iclass 25, count 0 2006.218.08:17:00.32#ibcon#read 3, iclass 25, count 0 2006.218.08:17:00.32#ibcon#about to read 4, iclass 25, count 0 2006.218.08:17:00.32#ibcon#read 4, iclass 25, count 0 2006.218.08:17:00.32#ibcon#about to read 5, iclass 25, count 0 2006.218.08:17:00.32#ibcon#read 5, iclass 25, count 0 2006.218.08:17:00.32#ibcon#about to read 6, iclass 25, count 0 2006.218.08:17:00.32#ibcon#read 6, iclass 25, count 0 2006.218.08:17:00.32#ibcon#end of sib2, iclass 25, count 0 2006.218.08:17:00.32#ibcon#*after write, iclass 25, count 0 2006.218.08:17:00.32#ibcon#*before return 0, iclass 25, count 0 2006.218.08:17:00.32#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.218.08:17:00.32#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.218.08:17:00.32#ibcon#about to clear, iclass 25 cls_cnt 0 2006.218.08:17:00.32#ibcon#cleared, iclass 25 cls_cnt 0 2006.218.08:17:00.32$vc4f8/va=8,7 2006.218.08:17:00.32#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.218.08:17:00.32#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.218.08:17:00.32#ibcon#ireg 11 cls_cnt 2 2006.218.08:17:00.32#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.218.08:17:00.38#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.218.08:17:00.38#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.218.08:17:00.38#ibcon#enter wrdev, iclass 27, count 2 2006.218.08:17:00.38#ibcon#first serial, iclass 27, count 2 2006.218.08:17:00.38#ibcon#enter sib2, iclass 27, count 2 2006.218.08:17:00.38#ibcon#flushed, iclass 27, count 2 2006.218.08:17:00.38#ibcon#about to write, iclass 27, count 2 2006.218.08:17:00.38#ibcon#wrote, iclass 27, count 2 2006.218.08:17:00.38#ibcon#about to read 3, iclass 27, count 2 2006.218.08:17:00.40#ibcon#read 3, iclass 27, count 2 2006.218.08:17:00.40#ibcon#about to read 4, iclass 27, count 2 2006.218.08:17:00.40#ibcon#read 4, iclass 27, count 2 2006.218.08:17:00.40#ibcon#about to read 5, iclass 27, count 2 2006.218.08:17:00.40#ibcon#read 5, iclass 27, count 2 2006.218.08:17:00.40#ibcon#about to read 6, iclass 27, count 2 2006.218.08:17:00.40#ibcon#read 6, iclass 27, count 2 2006.218.08:17:00.40#ibcon#end of sib2, iclass 27, count 2 2006.218.08:17:00.40#ibcon#*mode == 0, iclass 27, count 2 2006.218.08:17:00.40#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.218.08:17:00.40#ibcon#[25=AT08-07\r\n] 2006.218.08:17:00.40#ibcon#*before write, iclass 27, count 2 2006.218.08:17:00.40#ibcon#enter sib2, iclass 27, count 2 2006.218.08:17:00.40#ibcon#flushed, iclass 27, count 2 2006.218.08:17:00.40#ibcon#about to write, iclass 27, count 2 2006.218.08:17:00.40#ibcon#wrote, iclass 27, count 2 2006.218.08:17:00.40#ibcon#about to read 3, iclass 27, count 2 2006.218.08:17:00.44#ibcon#read 3, iclass 27, count 2 2006.218.08:17:00.44#ibcon#about to read 4, iclass 27, count 2 2006.218.08:17:00.44#ibcon#read 4, iclass 27, count 2 2006.218.08:17:00.44#ibcon#about to read 5, iclass 27, count 2 2006.218.08:17:00.44#ibcon#read 5, iclass 27, count 2 2006.218.08:17:00.44#ibcon#about to read 6, iclass 27, count 2 2006.218.08:17:00.44#ibcon#read 6, iclass 27, count 2 2006.218.08:17:00.44#ibcon#end of sib2, iclass 27, count 2 2006.218.08:17:00.44#ibcon#*after write, iclass 27, count 2 2006.218.08:17:00.44#ibcon#*before return 0, iclass 27, count 2 2006.218.08:17:00.44#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.218.08:17:00.44#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.218.08:17:00.44#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.218.08:17:00.44#ibcon#ireg 7 cls_cnt 0 2006.218.08:17:00.44#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.218.08:17:00.56#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.218.08:17:00.56#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.218.08:17:00.56#ibcon#enter wrdev, iclass 27, count 0 2006.218.08:17:00.56#ibcon#first serial, iclass 27, count 0 2006.218.08:17:00.56#ibcon#enter sib2, iclass 27, count 0 2006.218.08:17:00.56#ibcon#flushed, iclass 27, count 0 2006.218.08:17:00.56#ibcon#about to write, iclass 27, count 0 2006.218.08:17:00.56#ibcon#wrote, iclass 27, count 0 2006.218.08:17:00.56#ibcon#about to read 3, iclass 27, count 0 2006.218.08:17:00.58#ibcon#read 3, iclass 27, count 0 2006.218.08:17:00.58#ibcon#about to read 4, iclass 27, count 0 2006.218.08:17:00.58#ibcon#read 4, iclass 27, count 0 2006.218.08:17:00.58#ibcon#about to read 5, iclass 27, count 0 2006.218.08:17:00.58#ibcon#read 5, iclass 27, count 0 2006.218.08:17:00.58#ibcon#about to read 6, iclass 27, count 0 2006.218.08:17:00.58#ibcon#read 6, iclass 27, count 0 2006.218.08:17:00.58#ibcon#end of sib2, iclass 27, count 0 2006.218.08:17:00.58#ibcon#*mode == 0, iclass 27, count 0 2006.218.08:17:00.58#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.218.08:17:00.58#ibcon#[25=USB\r\n] 2006.218.08:17:00.58#ibcon#*before write, iclass 27, count 0 2006.218.08:17:00.58#ibcon#enter sib2, iclass 27, count 0 2006.218.08:17:00.58#ibcon#flushed, iclass 27, count 0 2006.218.08:17:00.58#ibcon#about to write, iclass 27, count 0 2006.218.08:17:00.58#ibcon#wrote, iclass 27, count 0 2006.218.08:17:00.58#ibcon#about to read 3, iclass 27, count 0 2006.218.08:17:00.61#ibcon#read 3, iclass 27, count 0 2006.218.08:17:00.61#ibcon#about to read 4, iclass 27, count 0 2006.218.08:17:00.61#ibcon#read 4, iclass 27, count 0 2006.218.08:17:00.61#ibcon#about to read 5, iclass 27, count 0 2006.218.08:17:00.61#ibcon#read 5, iclass 27, count 0 2006.218.08:17:00.61#ibcon#about to read 6, iclass 27, count 0 2006.218.08:17:00.61#ibcon#read 6, iclass 27, count 0 2006.218.08:17:00.61#ibcon#end of sib2, iclass 27, count 0 2006.218.08:17:00.61#ibcon#*after write, iclass 27, count 0 2006.218.08:17:00.61#ibcon#*before return 0, iclass 27, count 0 2006.218.08:17:00.61#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.218.08:17:00.61#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.218.08:17:00.61#ibcon#about to clear, iclass 27 cls_cnt 0 2006.218.08:17:00.61#ibcon#cleared, iclass 27 cls_cnt 0 2006.218.08:17:00.61$vc4f8/vblo=1,632.99 2006.218.08:17:00.61#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.218.08:17:00.61#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.218.08:17:00.61#ibcon#ireg 17 cls_cnt 0 2006.218.08:17:00.61#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.218.08:17:00.61#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.218.08:17:00.61#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.218.08:17:00.61#ibcon#enter wrdev, iclass 29, count 0 2006.218.08:17:00.61#ibcon#first serial, iclass 29, count 0 2006.218.08:17:00.61#ibcon#enter sib2, iclass 29, count 0 2006.218.08:17:00.61#ibcon#flushed, iclass 29, count 0 2006.218.08:17:00.61#ibcon#about to write, iclass 29, count 0 2006.218.08:17:00.61#ibcon#wrote, iclass 29, count 0 2006.218.08:17:00.61#ibcon#about to read 3, iclass 29, count 0 2006.218.08:17:00.63#ibcon#read 3, iclass 29, count 0 2006.218.08:17:00.63#ibcon#about to read 4, iclass 29, count 0 2006.218.08:17:00.63#ibcon#read 4, iclass 29, count 0 2006.218.08:17:00.63#ibcon#about to read 5, iclass 29, count 0 2006.218.08:17:00.63#ibcon#read 5, iclass 29, count 0 2006.218.08:17:00.63#ibcon#about to read 6, iclass 29, count 0 2006.218.08:17:00.63#ibcon#read 6, iclass 29, count 0 2006.218.08:17:00.63#ibcon#end of sib2, iclass 29, count 0 2006.218.08:17:00.63#ibcon#*mode == 0, iclass 29, count 0 2006.218.08:17:00.63#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.218.08:17:00.63#ibcon#[28=FRQ=01,632.99\r\n] 2006.218.08:17:00.63#ibcon#*before write, iclass 29, count 0 2006.218.08:17:00.63#ibcon#enter sib2, iclass 29, count 0 2006.218.08:17:00.63#ibcon#flushed, iclass 29, count 0 2006.218.08:17:00.63#ibcon#about to write, iclass 29, count 0 2006.218.08:17:00.63#ibcon#wrote, iclass 29, count 0 2006.218.08:17:00.63#ibcon#about to read 3, iclass 29, count 0 2006.218.08:17:00.67#ibcon#read 3, iclass 29, count 0 2006.218.08:17:00.67#ibcon#about to read 4, iclass 29, count 0 2006.218.08:17:00.67#ibcon#read 4, iclass 29, count 0 2006.218.08:17:00.67#ibcon#about to read 5, iclass 29, count 0 2006.218.08:17:00.67#ibcon#read 5, iclass 29, count 0 2006.218.08:17:00.67#ibcon#about to read 6, iclass 29, count 0 2006.218.08:17:00.67#ibcon#read 6, iclass 29, count 0 2006.218.08:17:00.67#ibcon#end of sib2, iclass 29, count 0 2006.218.08:17:00.67#ibcon#*after write, iclass 29, count 0 2006.218.08:17:00.67#ibcon#*before return 0, iclass 29, count 0 2006.218.08:17:00.67#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.218.08:17:00.67#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.218.08:17:00.67#ibcon#about to clear, iclass 29 cls_cnt 0 2006.218.08:17:00.67#ibcon#cleared, iclass 29 cls_cnt 0 2006.218.08:17:00.67$vc4f8/vb=1,4 2006.218.08:17:00.67#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.218.08:17:00.67#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.218.08:17:00.67#ibcon#ireg 11 cls_cnt 2 2006.218.08:17:00.67#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.218.08:17:00.67#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.218.08:17:00.67#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.218.08:17:00.67#ibcon#enter wrdev, iclass 31, count 2 2006.218.08:17:00.67#ibcon#first serial, iclass 31, count 2 2006.218.08:17:00.67#ibcon#enter sib2, iclass 31, count 2 2006.218.08:17:00.67#ibcon#flushed, iclass 31, count 2 2006.218.08:17:00.67#ibcon#about to write, iclass 31, count 2 2006.218.08:17:00.67#ibcon#wrote, iclass 31, count 2 2006.218.08:17:00.67#ibcon#about to read 3, iclass 31, count 2 2006.218.08:17:00.69#ibcon#read 3, iclass 31, count 2 2006.218.08:17:00.69#ibcon#about to read 4, iclass 31, count 2 2006.218.08:17:00.69#ibcon#read 4, iclass 31, count 2 2006.218.08:17:00.69#ibcon#about to read 5, iclass 31, count 2 2006.218.08:17:00.69#ibcon#read 5, iclass 31, count 2 2006.218.08:17:00.69#ibcon#about to read 6, iclass 31, count 2 2006.218.08:17:00.69#ibcon#read 6, iclass 31, count 2 2006.218.08:17:00.69#ibcon#end of sib2, iclass 31, count 2 2006.218.08:17:00.69#ibcon#*mode == 0, iclass 31, count 2 2006.218.08:17:00.69#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.218.08:17:00.69#ibcon#[27=AT01-04\r\n] 2006.218.08:17:00.69#ibcon#*before write, iclass 31, count 2 2006.218.08:17:00.69#ibcon#enter sib2, iclass 31, count 2 2006.218.08:17:00.69#ibcon#flushed, iclass 31, count 2 2006.218.08:17:00.69#ibcon#about to write, iclass 31, count 2 2006.218.08:17:00.69#ibcon#wrote, iclass 31, count 2 2006.218.08:17:00.69#ibcon#about to read 3, iclass 31, count 2 2006.218.08:17:00.72#ibcon#read 3, iclass 31, count 2 2006.218.08:17:00.72#ibcon#about to read 4, iclass 31, count 2 2006.218.08:17:00.72#ibcon#read 4, iclass 31, count 2 2006.218.08:17:00.72#ibcon#about to read 5, iclass 31, count 2 2006.218.08:17:00.72#ibcon#read 5, iclass 31, count 2 2006.218.08:17:00.72#ibcon#about to read 6, iclass 31, count 2 2006.218.08:17:00.72#ibcon#read 6, iclass 31, count 2 2006.218.08:17:00.72#ibcon#end of sib2, iclass 31, count 2 2006.218.08:17:00.72#ibcon#*after write, iclass 31, count 2 2006.218.08:17:00.72#ibcon#*before return 0, iclass 31, count 2 2006.218.08:17:00.72#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.218.08:17:00.72#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.218.08:17:00.72#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.218.08:17:00.72#ibcon#ireg 7 cls_cnt 0 2006.218.08:17:00.72#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.218.08:17:00.84#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.218.08:17:00.84#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.218.08:17:00.84#ibcon#enter wrdev, iclass 31, count 0 2006.218.08:17:00.84#ibcon#first serial, iclass 31, count 0 2006.218.08:17:00.84#ibcon#enter sib2, iclass 31, count 0 2006.218.08:17:00.84#ibcon#flushed, iclass 31, count 0 2006.218.08:17:00.84#ibcon#about to write, iclass 31, count 0 2006.218.08:17:00.84#ibcon#wrote, iclass 31, count 0 2006.218.08:17:00.84#ibcon#about to read 3, iclass 31, count 0 2006.218.08:17:00.86#ibcon#read 3, iclass 31, count 0 2006.218.08:17:00.86#ibcon#about to read 4, iclass 31, count 0 2006.218.08:17:00.86#ibcon#read 4, iclass 31, count 0 2006.218.08:17:00.86#ibcon#about to read 5, iclass 31, count 0 2006.218.08:17:00.86#ibcon#read 5, iclass 31, count 0 2006.218.08:17:00.86#ibcon#about to read 6, iclass 31, count 0 2006.218.08:17:00.86#ibcon#read 6, iclass 31, count 0 2006.218.08:17:00.86#ibcon#end of sib2, iclass 31, count 0 2006.218.08:17:00.86#ibcon#*mode == 0, iclass 31, count 0 2006.218.08:17:00.86#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.218.08:17:00.86#ibcon#[27=USB\r\n] 2006.218.08:17:00.86#ibcon#*before write, iclass 31, count 0 2006.218.08:17:00.86#ibcon#enter sib2, iclass 31, count 0 2006.218.08:17:00.86#ibcon#flushed, iclass 31, count 0 2006.218.08:17:00.86#ibcon#about to write, iclass 31, count 0 2006.218.08:17:00.86#ibcon#wrote, iclass 31, count 0 2006.218.08:17:00.86#ibcon#about to read 3, iclass 31, count 0 2006.218.08:17:00.89#ibcon#read 3, iclass 31, count 0 2006.218.08:17:00.89#ibcon#about to read 4, iclass 31, count 0 2006.218.08:17:00.89#ibcon#read 4, iclass 31, count 0 2006.218.08:17:00.89#ibcon#about to read 5, iclass 31, count 0 2006.218.08:17:00.89#ibcon#read 5, iclass 31, count 0 2006.218.08:17:00.89#ibcon#about to read 6, iclass 31, count 0 2006.218.08:17:00.89#ibcon#read 6, iclass 31, count 0 2006.218.08:17:00.89#ibcon#end of sib2, iclass 31, count 0 2006.218.08:17:00.89#ibcon#*after write, iclass 31, count 0 2006.218.08:17:00.89#ibcon#*before return 0, iclass 31, count 0 2006.218.08:17:00.89#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.218.08:17:00.89#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.218.08:17:00.89#ibcon#about to clear, iclass 31 cls_cnt 0 2006.218.08:17:00.89#ibcon#cleared, iclass 31 cls_cnt 0 2006.218.08:17:00.89$vc4f8/vblo=2,640.99 2006.218.08:17:00.89#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.218.08:17:00.89#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.218.08:17:00.89#ibcon#ireg 17 cls_cnt 0 2006.218.08:17:00.89#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.218.08:17:00.89#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.218.08:17:00.89#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.218.08:17:00.89#ibcon#enter wrdev, iclass 33, count 0 2006.218.08:17:00.89#ibcon#first serial, iclass 33, count 0 2006.218.08:17:00.89#ibcon#enter sib2, iclass 33, count 0 2006.218.08:17:00.89#ibcon#flushed, iclass 33, count 0 2006.218.08:17:00.89#ibcon#about to write, iclass 33, count 0 2006.218.08:17:00.89#ibcon#wrote, iclass 33, count 0 2006.218.08:17:00.89#ibcon#about to read 3, iclass 33, count 0 2006.218.08:17:00.91#ibcon#read 3, iclass 33, count 0 2006.218.08:17:00.91#ibcon#about to read 4, iclass 33, count 0 2006.218.08:17:00.91#ibcon#read 4, iclass 33, count 0 2006.218.08:17:00.91#ibcon#about to read 5, iclass 33, count 0 2006.218.08:17:00.91#ibcon#read 5, iclass 33, count 0 2006.218.08:17:00.91#ibcon#about to read 6, iclass 33, count 0 2006.218.08:17:00.91#ibcon#read 6, iclass 33, count 0 2006.218.08:17:00.91#ibcon#end of sib2, iclass 33, count 0 2006.218.08:17:00.91#ibcon#*mode == 0, iclass 33, count 0 2006.218.08:17:00.91#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.218.08:17:00.91#ibcon#[28=FRQ=02,640.99\r\n] 2006.218.08:17:00.91#ibcon#*before write, iclass 33, count 0 2006.218.08:17:00.91#ibcon#enter sib2, iclass 33, count 0 2006.218.08:17:00.91#ibcon#flushed, iclass 33, count 0 2006.218.08:17:00.91#ibcon#about to write, iclass 33, count 0 2006.218.08:17:00.91#ibcon#wrote, iclass 33, count 0 2006.218.08:17:00.91#ibcon#about to read 3, iclass 33, count 0 2006.218.08:17:00.95#ibcon#read 3, iclass 33, count 0 2006.218.08:17:00.95#ibcon#about to read 4, iclass 33, count 0 2006.218.08:17:00.95#ibcon#read 4, iclass 33, count 0 2006.218.08:17:00.95#ibcon#about to read 5, iclass 33, count 0 2006.218.08:17:00.95#ibcon#read 5, iclass 33, count 0 2006.218.08:17:00.95#ibcon#about to read 6, iclass 33, count 0 2006.218.08:17:00.95#ibcon#read 6, iclass 33, count 0 2006.218.08:17:00.95#ibcon#end of sib2, iclass 33, count 0 2006.218.08:17:00.95#ibcon#*after write, iclass 33, count 0 2006.218.08:17:00.95#ibcon#*before return 0, iclass 33, count 0 2006.218.08:17:00.95#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.218.08:17:00.95#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.218.08:17:00.95#ibcon#about to clear, iclass 33 cls_cnt 0 2006.218.08:17:00.95#ibcon#cleared, iclass 33 cls_cnt 0 2006.218.08:17:00.95$vc4f8/vb=2,4 2006.218.08:17:00.95#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.218.08:17:00.95#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.218.08:17:00.95#ibcon#ireg 11 cls_cnt 2 2006.218.08:17:00.95#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.218.08:17:01.01#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.218.08:17:01.01#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.218.08:17:01.01#ibcon#enter wrdev, iclass 35, count 2 2006.218.08:17:01.01#ibcon#first serial, iclass 35, count 2 2006.218.08:17:01.01#ibcon#enter sib2, iclass 35, count 2 2006.218.08:17:01.01#ibcon#flushed, iclass 35, count 2 2006.218.08:17:01.01#ibcon#about to write, iclass 35, count 2 2006.218.08:17:01.01#ibcon#wrote, iclass 35, count 2 2006.218.08:17:01.01#ibcon#about to read 3, iclass 35, count 2 2006.218.08:17:01.03#ibcon#read 3, iclass 35, count 2 2006.218.08:17:01.03#ibcon#about to read 4, iclass 35, count 2 2006.218.08:17:01.03#ibcon#read 4, iclass 35, count 2 2006.218.08:17:01.03#ibcon#about to read 5, iclass 35, count 2 2006.218.08:17:01.03#ibcon#read 5, iclass 35, count 2 2006.218.08:17:01.03#ibcon#about to read 6, iclass 35, count 2 2006.218.08:17:01.03#ibcon#read 6, iclass 35, count 2 2006.218.08:17:01.03#ibcon#end of sib2, iclass 35, count 2 2006.218.08:17:01.03#ibcon#*mode == 0, iclass 35, count 2 2006.218.08:17:01.03#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.218.08:17:01.03#ibcon#[27=AT02-04\r\n] 2006.218.08:17:01.03#ibcon#*before write, iclass 35, count 2 2006.218.08:17:01.03#ibcon#enter sib2, iclass 35, count 2 2006.218.08:17:01.03#ibcon#flushed, iclass 35, count 2 2006.218.08:17:01.03#ibcon#about to write, iclass 35, count 2 2006.218.08:17:01.03#ibcon#wrote, iclass 35, count 2 2006.218.08:17:01.03#ibcon#about to read 3, iclass 35, count 2 2006.218.08:17:01.06#ibcon#read 3, iclass 35, count 2 2006.218.08:17:01.06#ibcon#about to read 4, iclass 35, count 2 2006.218.08:17:01.06#ibcon#read 4, iclass 35, count 2 2006.218.08:17:01.06#ibcon#about to read 5, iclass 35, count 2 2006.218.08:17:01.06#ibcon#read 5, iclass 35, count 2 2006.218.08:17:01.06#ibcon#about to read 6, iclass 35, count 2 2006.218.08:17:01.06#ibcon#read 6, iclass 35, count 2 2006.218.08:17:01.06#ibcon#end of sib2, iclass 35, count 2 2006.218.08:17:01.06#ibcon#*after write, iclass 35, count 2 2006.218.08:17:01.06#ibcon#*before return 0, iclass 35, count 2 2006.218.08:17:01.06#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.218.08:17:01.06#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.218.08:17:01.06#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.218.08:17:01.06#ibcon#ireg 7 cls_cnt 0 2006.218.08:17:01.06#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.218.08:17:01.18#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.218.08:17:01.18#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.218.08:17:01.18#ibcon#enter wrdev, iclass 35, count 0 2006.218.08:17:01.18#ibcon#first serial, iclass 35, count 0 2006.218.08:17:01.18#ibcon#enter sib2, iclass 35, count 0 2006.218.08:17:01.18#ibcon#flushed, iclass 35, count 0 2006.218.08:17:01.18#ibcon#about to write, iclass 35, count 0 2006.218.08:17:01.18#ibcon#wrote, iclass 35, count 0 2006.218.08:17:01.18#ibcon#about to read 3, iclass 35, count 0 2006.218.08:17:01.20#ibcon#read 3, iclass 35, count 0 2006.218.08:17:01.20#ibcon#about to read 4, iclass 35, count 0 2006.218.08:17:01.20#ibcon#read 4, iclass 35, count 0 2006.218.08:17:01.20#ibcon#about to read 5, iclass 35, count 0 2006.218.08:17:01.20#ibcon#read 5, iclass 35, count 0 2006.218.08:17:01.20#ibcon#about to read 6, iclass 35, count 0 2006.218.08:17:01.20#ibcon#read 6, iclass 35, count 0 2006.218.08:17:01.20#ibcon#end of sib2, iclass 35, count 0 2006.218.08:17:01.20#ibcon#*mode == 0, iclass 35, count 0 2006.218.08:17:01.20#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.218.08:17:01.20#ibcon#[27=USB\r\n] 2006.218.08:17:01.20#ibcon#*before write, iclass 35, count 0 2006.218.08:17:01.20#ibcon#enter sib2, iclass 35, count 0 2006.218.08:17:01.20#ibcon#flushed, iclass 35, count 0 2006.218.08:17:01.20#ibcon#about to write, iclass 35, count 0 2006.218.08:17:01.20#ibcon#wrote, iclass 35, count 0 2006.218.08:17:01.20#ibcon#about to read 3, iclass 35, count 0 2006.218.08:17:01.23#ibcon#read 3, iclass 35, count 0 2006.218.08:17:01.23#ibcon#about to read 4, iclass 35, count 0 2006.218.08:17:01.23#ibcon#read 4, iclass 35, count 0 2006.218.08:17:01.23#ibcon#about to read 5, iclass 35, count 0 2006.218.08:17:01.23#ibcon#read 5, iclass 35, count 0 2006.218.08:17:01.23#ibcon#about to read 6, iclass 35, count 0 2006.218.08:17:01.23#ibcon#read 6, iclass 35, count 0 2006.218.08:17:01.23#ibcon#end of sib2, iclass 35, count 0 2006.218.08:17:01.23#ibcon#*after write, iclass 35, count 0 2006.218.08:17:01.23#ibcon#*before return 0, iclass 35, count 0 2006.218.08:17:01.23#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.218.08:17:01.23#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.218.08:17:01.23#ibcon#about to clear, iclass 35 cls_cnt 0 2006.218.08:17:01.23#ibcon#cleared, iclass 35 cls_cnt 0 2006.218.08:17:01.23$vc4f8/vblo=3,656.99 2006.218.08:17:01.23#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.218.08:17:01.23#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.218.08:17:01.23#ibcon#ireg 17 cls_cnt 0 2006.218.08:17:01.23#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.218.08:17:01.23#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.218.08:17:01.23#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.218.08:17:01.23#ibcon#enter wrdev, iclass 37, count 0 2006.218.08:17:01.23#ibcon#first serial, iclass 37, count 0 2006.218.08:17:01.23#ibcon#enter sib2, iclass 37, count 0 2006.218.08:17:01.23#ibcon#flushed, iclass 37, count 0 2006.218.08:17:01.23#ibcon#about to write, iclass 37, count 0 2006.218.08:17:01.23#ibcon#wrote, iclass 37, count 0 2006.218.08:17:01.23#ibcon#about to read 3, iclass 37, count 0 2006.218.08:17:01.25#ibcon#read 3, iclass 37, count 0 2006.218.08:17:01.25#ibcon#about to read 4, iclass 37, count 0 2006.218.08:17:01.25#ibcon#read 4, iclass 37, count 0 2006.218.08:17:01.25#ibcon#about to read 5, iclass 37, count 0 2006.218.08:17:01.25#ibcon#read 5, iclass 37, count 0 2006.218.08:17:01.25#ibcon#about to read 6, iclass 37, count 0 2006.218.08:17:01.25#ibcon#read 6, iclass 37, count 0 2006.218.08:17:01.25#ibcon#end of sib2, iclass 37, count 0 2006.218.08:17:01.25#ibcon#*mode == 0, iclass 37, count 0 2006.218.08:17:01.25#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.218.08:17:01.25#ibcon#[28=FRQ=03,656.99\r\n] 2006.218.08:17:01.25#ibcon#*before write, iclass 37, count 0 2006.218.08:17:01.25#ibcon#enter sib2, iclass 37, count 0 2006.218.08:17:01.25#ibcon#flushed, iclass 37, count 0 2006.218.08:17:01.25#ibcon#about to write, iclass 37, count 0 2006.218.08:17:01.25#ibcon#wrote, iclass 37, count 0 2006.218.08:17:01.25#ibcon#about to read 3, iclass 37, count 0 2006.218.08:17:01.29#ibcon#read 3, iclass 37, count 0 2006.218.08:17:01.29#ibcon#about to read 4, iclass 37, count 0 2006.218.08:17:01.29#ibcon#read 4, iclass 37, count 0 2006.218.08:17:01.29#ibcon#about to read 5, iclass 37, count 0 2006.218.08:17:01.29#ibcon#read 5, iclass 37, count 0 2006.218.08:17:01.29#ibcon#about to read 6, iclass 37, count 0 2006.218.08:17:01.29#ibcon#read 6, iclass 37, count 0 2006.218.08:17:01.29#ibcon#end of sib2, iclass 37, count 0 2006.218.08:17:01.29#ibcon#*after write, iclass 37, count 0 2006.218.08:17:01.29#ibcon#*before return 0, iclass 37, count 0 2006.218.08:17:01.29#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.218.08:17:01.29#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.218.08:17:01.29#ibcon#about to clear, iclass 37 cls_cnt 0 2006.218.08:17:01.29#ibcon#cleared, iclass 37 cls_cnt 0 2006.218.08:17:01.29$vc4f8/vb=3,4 2006.218.08:17:01.29#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.218.08:17:01.29#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.218.08:17:01.29#ibcon#ireg 11 cls_cnt 2 2006.218.08:17:01.29#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.218.08:17:01.35#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.218.08:17:01.35#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.218.08:17:01.35#ibcon#enter wrdev, iclass 39, count 2 2006.218.08:17:01.35#ibcon#first serial, iclass 39, count 2 2006.218.08:17:01.35#ibcon#enter sib2, iclass 39, count 2 2006.218.08:17:01.35#ibcon#flushed, iclass 39, count 2 2006.218.08:17:01.35#ibcon#about to write, iclass 39, count 2 2006.218.08:17:01.35#ibcon#wrote, iclass 39, count 2 2006.218.08:17:01.35#ibcon#about to read 3, iclass 39, count 2 2006.218.08:17:01.37#ibcon#read 3, iclass 39, count 2 2006.218.08:17:01.37#ibcon#about to read 4, iclass 39, count 2 2006.218.08:17:01.37#ibcon#read 4, iclass 39, count 2 2006.218.08:17:01.37#ibcon#about to read 5, iclass 39, count 2 2006.218.08:17:01.37#ibcon#read 5, iclass 39, count 2 2006.218.08:17:01.37#ibcon#about to read 6, iclass 39, count 2 2006.218.08:17:01.37#ibcon#read 6, iclass 39, count 2 2006.218.08:17:01.37#ibcon#end of sib2, iclass 39, count 2 2006.218.08:17:01.37#ibcon#*mode == 0, iclass 39, count 2 2006.218.08:17:01.37#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.218.08:17:01.37#ibcon#[27=AT03-04\r\n] 2006.218.08:17:01.37#ibcon#*before write, iclass 39, count 2 2006.218.08:17:01.37#ibcon#enter sib2, iclass 39, count 2 2006.218.08:17:01.37#ibcon#flushed, iclass 39, count 2 2006.218.08:17:01.37#ibcon#about to write, iclass 39, count 2 2006.218.08:17:01.37#ibcon#wrote, iclass 39, count 2 2006.218.08:17:01.37#ibcon#about to read 3, iclass 39, count 2 2006.218.08:17:01.41#ibcon#read 3, iclass 39, count 2 2006.218.08:17:01.41#ibcon#about to read 4, iclass 39, count 2 2006.218.08:17:01.41#ibcon#read 4, iclass 39, count 2 2006.218.08:17:01.41#ibcon#about to read 5, iclass 39, count 2 2006.218.08:17:01.41#ibcon#read 5, iclass 39, count 2 2006.218.08:17:01.41#ibcon#about to read 6, iclass 39, count 2 2006.218.08:17:01.41#ibcon#read 6, iclass 39, count 2 2006.218.08:17:01.41#ibcon#end of sib2, iclass 39, count 2 2006.218.08:17:01.41#ibcon#*after write, iclass 39, count 2 2006.218.08:17:01.41#ibcon#*before return 0, iclass 39, count 2 2006.218.08:17:01.41#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.218.08:17:01.41#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.218.08:17:01.41#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.218.08:17:01.41#ibcon#ireg 7 cls_cnt 0 2006.218.08:17:01.41#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.218.08:17:01.53#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.218.08:17:01.53#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.218.08:17:01.53#ibcon#enter wrdev, iclass 39, count 0 2006.218.08:17:01.53#ibcon#first serial, iclass 39, count 0 2006.218.08:17:01.53#ibcon#enter sib2, iclass 39, count 0 2006.218.08:17:01.53#ibcon#flushed, iclass 39, count 0 2006.218.08:17:01.53#ibcon#about to write, iclass 39, count 0 2006.218.08:17:01.53#ibcon#wrote, iclass 39, count 0 2006.218.08:17:01.53#ibcon#about to read 3, iclass 39, count 0 2006.218.08:17:01.55#ibcon#read 3, iclass 39, count 0 2006.218.08:17:01.55#ibcon#about to read 4, iclass 39, count 0 2006.218.08:17:01.55#ibcon#read 4, iclass 39, count 0 2006.218.08:17:01.55#ibcon#about to read 5, iclass 39, count 0 2006.218.08:17:01.55#ibcon#read 5, iclass 39, count 0 2006.218.08:17:01.55#ibcon#about to read 6, iclass 39, count 0 2006.218.08:17:01.55#ibcon#read 6, iclass 39, count 0 2006.218.08:17:01.55#ibcon#end of sib2, iclass 39, count 0 2006.218.08:17:01.55#ibcon#*mode == 0, iclass 39, count 0 2006.218.08:17:01.55#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.218.08:17:01.55#ibcon#[27=USB\r\n] 2006.218.08:17:01.55#ibcon#*before write, iclass 39, count 0 2006.218.08:17:01.55#ibcon#enter sib2, iclass 39, count 0 2006.218.08:17:01.55#ibcon#flushed, iclass 39, count 0 2006.218.08:17:01.55#ibcon#about to write, iclass 39, count 0 2006.218.08:17:01.55#ibcon#wrote, iclass 39, count 0 2006.218.08:17:01.55#ibcon#about to read 3, iclass 39, count 0 2006.218.08:17:01.58#ibcon#read 3, iclass 39, count 0 2006.218.08:17:01.58#ibcon#about to read 4, iclass 39, count 0 2006.218.08:17:01.58#ibcon#read 4, iclass 39, count 0 2006.218.08:17:01.58#ibcon#about to read 5, iclass 39, count 0 2006.218.08:17:01.58#ibcon#read 5, iclass 39, count 0 2006.218.08:17:01.58#ibcon#about to read 6, iclass 39, count 0 2006.218.08:17:01.58#ibcon#read 6, iclass 39, count 0 2006.218.08:17:01.58#ibcon#end of sib2, iclass 39, count 0 2006.218.08:17:01.58#ibcon#*after write, iclass 39, count 0 2006.218.08:17:01.58#ibcon#*before return 0, iclass 39, count 0 2006.218.08:17:01.58#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.218.08:17:01.58#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.218.08:17:01.58#ibcon#about to clear, iclass 39 cls_cnt 0 2006.218.08:17:01.58#ibcon#cleared, iclass 39 cls_cnt 0 2006.218.08:17:01.58$vc4f8/vblo=4,712.99 2006.218.08:17:01.58#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.218.08:17:01.58#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.218.08:17:01.58#ibcon#ireg 17 cls_cnt 0 2006.218.08:17:01.58#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.218.08:17:01.58#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.218.08:17:01.58#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.218.08:17:01.58#ibcon#enter wrdev, iclass 3, count 0 2006.218.08:17:01.58#ibcon#first serial, iclass 3, count 0 2006.218.08:17:01.58#ibcon#enter sib2, iclass 3, count 0 2006.218.08:17:01.58#ibcon#flushed, iclass 3, count 0 2006.218.08:17:01.58#ibcon#about to write, iclass 3, count 0 2006.218.08:17:01.58#ibcon#wrote, iclass 3, count 0 2006.218.08:17:01.58#ibcon#about to read 3, iclass 3, count 0 2006.218.08:17:01.60#ibcon#read 3, iclass 3, count 0 2006.218.08:17:01.60#ibcon#about to read 4, iclass 3, count 0 2006.218.08:17:01.60#ibcon#read 4, iclass 3, count 0 2006.218.08:17:01.60#ibcon#about to read 5, iclass 3, count 0 2006.218.08:17:01.60#ibcon#read 5, iclass 3, count 0 2006.218.08:17:01.60#ibcon#about to read 6, iclass 3, count 0 2006.218.08:17:01.60#ibcon#read 6, iclass 3, count 0 2006.218.08:17:01.60#ibcon#end of sib2, iclass 3, count 0 2006.218.08:17:01.60#ibcon#*mode == 0, iclass 3, count 0 2006.218.08:17:01.60#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.218.08:17:01.60#ibcon#[28=FRQ=04,712.99\r\n] 2006.218.08:17:01.60#ibcon#*before write, iclass 3, count 0 2006.218.08:17:01.60#ibcon#enter sib2, iclass 3, count 0 2006.218.08:17:01.60#ibcon#flushed, iclass 3, count 0 2006.218.08:17:01.60#ibcon#about to write, iclass 3, count 0 2006.218.08:17:01.60#ibcon#wrote, iclass 3, count 0 2006.218.08:17:01.60#ibcon#about to read 3, iclass 3, count 0 2006.218.08:17:01.63#abcon#<5=/06 4.2 7.3 30.78 741007.6\r\n> 2006.218.08:17:01.64#ibcon#read 3, iclass 3, count 0 2006.218.08:17:01.64#ibcon#about to read 4, iclass 3, count 0 2006.218.08:17:01.64#ibcon#read 4, iclass 3, count 0 2006.218.08:17:01.64#ibcon#about to read 5, iclass 3, count 0 2006.218.08:17:01.64#ibcon#read 5, iclass 3, count 0 2006.218.08:17:01.64#ibcon#about to read 6, iclass 3, count 0 2006.218.08:17:01.64#ibcon#read 6, iclass 3, count 0 2006.218.08:17:01.64#ibcon#end of sib2, iclass 3, count 0 2006.218.08:17:01.64#ibcon#*after write, iclass 3, count 0 2006.218.08:17:01.64#ibcon#*before return 0, iclass 3, count 0 2006.218.08:17:01.64#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.218.08:17:01.64#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.218.08:17:01.64#ibcon#about to clear, iclass 3 cls_cnt 0 2006.218.08:17:01.64#ibcon#cleared, iclass 3 cls_cnt 0 2006.218.08:17:01.64$vc4f8/vb=4,4 2006.218.08:17:01.64#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.218.08:17:01.64#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.218.08:17:01.64#ibcon#ireg 11 cls_cnt 2 2006.218.08:17:01.64#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.218.08:17:01.65#abcon#{5=INTERFACE CLEAR} 2006.218.08:17:01.70#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.218.08:17:01.70#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.218.08:17:01.70#ibcon#enter wrdev, iclass 10, count 2 2006.218.08:17:01.70#ibcon#first serial, iclass 10, count 2 2006.218.08:17:01.70#ibcon#enter sib2, iclass 10, count 2 2006.218.08:17:01.70#ibcon#flushed, iclass 10, count 2 2006.218.08:17:01.70#ibcon#about to write, iclass 10, count 2 2006.218.08:17:01.70#ibcon#wrote, iclass 10, count 2 2006.218.08:17:01.70#ibcon#about to read 3, iclass 10, count 2 2006.218.08:17:01.71#abcon#[5=S1D000X0/0*\r\n] 2006.218.08:17:01.72#ibcon#read 3, iclass 10, count 2 2006.218.08:17:01.72#ibcon#about to read 4, iclass 10, count 2 2006.218.08:17:01.72#ibcon#read 4, iclass 10, count 2 2006.218.08:17:01.72#ibcon#about to read 5, iclass 10, count 2 2006.218.08:17:01.72#ibcon#read 5, iclass 10, count 2 2006.218.08:17:01.72#ibcon#about to read 6, iclass 10, count 2 2006.218.08:17:01.72#ibcon#read 6, iclass 10, count 2 2006.218.08:17:01.72#ibcon#end of sib2, iclass 10, count 2 2006.218.08:17:01.72#ibcon#*mode == 0, iclass 10, count 2 2006.218.08:17:01.72#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.218.08:17:01.72#ibcon#[27=AT04-04\r\n] 2006.218.08:17:01.72#ibcon#*before write, iclass 10, count 2 2006.218.08:17:01.72#ibcon#enter sib2, iclass 10, count 2 2006.218.08:17:01.72#ibcon#flushed, iclass 10, count 2 2006.218.08:17:01.72#ibcon#about to write, iclass 10, count 2 2006.218.08:17:01.72#ibcon#wrote, iclass 10, count 2 2006.218.08:17:01.72#ibcon#about to read 3, iclass 10, count 2 2006.218.08:17:01.75#ibcon#read 3, iclass 10, count 2 2006.218.08:17:01.75#ibcon#about to read 4, iclass 10, count 2 2006.218.08:17:01.75#ibcon#read 4, iclass 10, count 2 2006.218.08:17:01.75#ibcon#about to read 5, iclass 10, count 2 2006.218.08:17:01.75#ibcon#read 5, iclass 10, count 2 2006.218.08:17:01.75#ibcon#about to read 6, iclass 10, count 2 2006.218.08:17:01.75#ibcon#read 6, iclass 10, count 2 2006.218.08:17:01.75#ibcon#end of sib2, iclass 10, count 2 2006.218.08:17:01.75#ibcon#*after write, iclass 10, count 2 2006.218.08:17:01.75#ibcon#*before return 0, iclass 10, count 2 2006.218.08:17:01.75#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.218.08:17:01.75#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.218.08:17:01.75#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.218.08:17:01.75#ibcon#ireg 7 cls_cnt 0 2006.218.08:17:01.75#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.218.08:17:01.87#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.218.08:17:01.87#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.218.08:17:01.87#ibcon#enter wrdev, iclass 10, count 0 2006.218.08:17:01.87#ibcon#first serial, iclass 10, count 0 2006.218.08:17:01.87#ibcon#enter sib2, iclass 10, count 0 2006.218.08:17:01.87#ibcon#flushed, iclass 10, count 0 2006.218.08:17:01.87#ibcon#about to write, iclass 10, count 0 2006.218.08:17:01.87#ibcon#wrote, iclass 10, count 0 2006.218.08:17:01.87#ibcon#about to read 3, iclass 10, count 0 2006.218.08:17:01.89#ibcon#read 3, iclass 10, count 0 2006.218.08:17:01.89#ibcon#about to read 4, iclass 10, count 0 2006.218.08:17:01.89#ibcon#read 4, iclass 10, count 0 2006.218.08:17:01.89#ibcon#about to read 5, iclass 10, count 0 2006.218.08:17:01.89#ibcon#read 5, iclass 10, count 0 2006.218.08:17:01.89#ibcon#about to read 6, iclass 10, count 0 2006.218.08:17:01.89#ibcon#read 6, iclass 10, count 0 2006.218.08:17:01.89#ibcon#end of sib2, iclass 10, count 0 2006.218.08:17:01.89#ibcon#*mode == 0, iclass 10, count 0 2006.218.08:17:01.89#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.218.08:17:01.89#ibcon#[27=USB\r\n] 2006.218.08:17:01.89#ibcon#*before write, iclass 10, count 0 2006.218.08:17:01.89#ibcon#enter sib2, iclass 10, count 0 2006.218.08:17:01.89#ibcon#flushed, iclass 10, count 0 2006.218.08:17:01.89#ibcon#about to write, iclass 10, count 0 2006.218.08:17:01.89#ibcon#wrote, iclass 10, count 0 2006.218.08:17:01.89#ibcon#about to read 3, iclass 10, count 0 2006.218.08:17:01.92#ibcon#read 3, iclass 10, count 0 2006.218.08:17:01.92#ibcon#about to read 4, iclass 10, count 0 2006.218.08:17:01.92#ibcon#read 4, iclass 10, count 0 2006.218.08:17:01.92#ibcon#about to read 5, iclass 10, count 0 2006.218.08:17:01.92#ibcon#read 5, iclass 10, count 0 2006.218.08:17:01.92#ibcon#about to read 6, iclass 10, count 0 2006.218.08:17:01.92#ibcon#read 6, iclass 10, count 0 2006.218.08:17:01.92#ibcon#end of sib2, iclass 10, count 0 2006.218.08:17:01.92#ibcon#*after write, iclass 10, count 0 2006.218.08:17:01.92#ibcon#*before return 0, iclass 10, count 0 2006.218.08:17:01.92#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.218.08:17:01.92#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.218.08:17:01.92#ibcon#about to clear, iclass 10 cls_cnt 0 2006.218.08:17:01.92#ibcon#cleared, iclass 10 cls_cnt 0 2006.218.08:17:01.92$vc4f8/vblo=5,744.99 2006.218.08:17:01.92#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.218.08:17:01.92#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.218.08:17:01.92#ibcon#ireg 17 cls_cnt 0 2006.218.08:17:01.92#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.218.08:17:01.92#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.218.08:17:01.92#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.218.08:17:01.92#ibcon#enter wrdev, iclass 13, count 0 2006.218.08:17:01.92#ibcon#first serial, iclass 13, count 0 2006.218.08:17:01.92#ibcon#enter sib2, iclass 13, count 0 2006.218.08:17:01.92#ibcon#flushed, iclass 13, count 0 2006.218.08:17:01.92#ibcon#about to write, iclass 13, count 0 2006.218.08:17:01.92#ibcon#wrote, iclass 13, count 0 2006.218.08:17:01.92#ibcon#about to read 3, iclass 13, count 0 2006.218.08:17:01.94#ibcon#read 3, iclass 13, count 0 2006.218.08:17:01.94#ibcon#about to read 4, iclass 13, count 0 2006.218.08:17:01.94#ibcon#read 4, iclass 13, count 0 2006.218.08:17:01.94#ibcon#about to read 5, iclass 13, count 0 2006.218.08:17:01.94#ibcon#read 5, iclass 13, count 0 2006.218.08:17:01.94#ibcon#about to read 6, iclass 13, count 0 2006.218.08:17:01.94#ibcon#read 6, iclass 13, count 0 2006.218.08:17:01.94#ibcon#end of sib2, iclass 13, count 0 2006.218.08:17:01.94#ibcon#*mode == 0, iclass 13, count 0 2006.218.08:17:01.94#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.218.08:17:01.94#ibcon#[28=FRQ=05,744.99\r\n] 2006.218.08:17:01.94#ibcon#*before write, iclass 13, count 0 2006.218.08:17:01.94#ibcon#enter sib2, iclass 13, count 0 2006.218.08:17:01.94#ibcon#flushed, iclass 13, count 0 2006.218.08:17:01.94#ibcon#about to write, iclass 13, count 0 2006.218.08:17:01.94#ibcon#wrote, iclass 13, count 0 2006.218.08:17:01.94#ibcon#about to read 3, iclass 13, count 0 2006.218.08:17:01.98#ibcon#read 3, iclass 13, count 0 2006.218.08:17:01.98#ibcon#about to read 4, iclass 13, count 0 2006.218.08:17:01.98#ibcon#read 4, iclass 13, count 0 2006.218.08:17:01.98#ibcon#about to read 5, iclass 13, count 0 2006.218.08:17:01.98#ibcon#read 5, iclass 13, count 0 2006.218.08:17:01.98#ibcon#about to read 6, iclass 13, count 0 2006.218.08:17:01.98#ibcon#read 6, iclass 13, count 0 2006.218.08:17:01.98#ibcon#end of sib2, iclass 13, count 0 2006.218.08:17:01.98#ibcon#*after write, iclass 13, count 0 2006.218.08:17:01.98#ibcon#*before return 0, iclass 13, count 0 2006.218.08:17:01.98#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.218.08:17:01.98#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.218.08:17:01.98#ibcon#about to clear, iclass 13 cls_cnt 0 2006.218.08:17:01.98#ibcon#cleared, iclass 13 cls_cnt 0 2006.218.08:17:01.98$vc4f8/vb=5,4 2006.218.08:17:01.98#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.218.08:17:01.98#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.218.08:17:01.98#ibcon#ireg 11 cls_cnt 2 2006.218.08:17:01.98#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.218.08:17:02.04#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.218.08:17:02.04#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.218.08:17:02.04#ibcon#enter wrdev, iclass 15, count 2 2006.218.08:17:02.04#ibcon#first serial, iclass 15, count 2 2006.218.08:17:02.04#ibcon#enter sib2, iclass 15, count 2 2006.218.08:17:02.04#ibcon#flushed, iclass 15, count 2 2006.218.08:17:02.04#ibcon#about to write, iclass 15, count 2 2006.218.08:17:02.04#ibcon#wrote, iclass 15, count 2 2006.218.08:17:02.04#ibcon#about to read 3, iclass 15, count 2 2006.218.08:17:02.06#ibcon#read 3, iclass 15, count 2 2006.218.08:17:02.06#ibcon#about to read 4, iclass 15, count 2 2006.218.08:17:02.06#ibcon#read 4, iclass 15, count 2 2006.218.08:17:02.06#ibcon#about to read 5, iclass 15, count 2 2006.218.08:17:02.06#ibcon#read 5, iclass 15, count 2 2006.218.08:17:02.06#ibcon#about to read 6, iclass 15, count 2 2006.218.08:17:02.06#ibcon#read 6, iclass 15, count 2 2006.218.08:17:02.06#ibcon#end of sib2, iclass 15, count 2 2006.218.08:17:02.06#ibcon#*mode == 0, iclass 15, count 2 2006.218.08:17:02.06#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.218.08:17:02.06#ibcon#[27=AT05-04\r\n] 2006.218.08:17:02.06#ibcon#*before write, iclass 15, count 2 2006.218.08:17:02.06#ibcon#enter sib2, iclass 15, count 2 2006.218.08:17:02.06#ibcon#flushed, iclass 15, count 2 2006.218.08:17:02.06#ibcon#about to write, iclass 15, count 2 2006.218.08:17:02.06#ibcon#wrote, iclass 15, count 2 2006.218.08:17:02.06#ibcon#about to read 3, iclass 15, count 2 2006.218.08:17:02.09#ibcon#read 3, iclass 15, count 2 2006.218.08:17:02.09#ibcon#about to read 4, iclass 15, count 2 2006.218.08:17:02.09#ibcon#read 4, iclass 15, count 2 2006.218.08:17:02.09#ibcon#about to read 5, iclass 15, count 2 2006.218.08:17:02.09#ibcon#read 5, iclass 15, count 2 2006.218.08:17:02.09#ibcon#about to read 6, iclass 15, count 2 2006.218.08:17:02.09#ibcon#read 6, iclass 15, count 2 2006.218.08:17:02.09#ibcon#end of sib2, iclass 15, count 2 2006.218.08:17:02.09#ibcon#*after write, iclass 15, count 2 2006.218.08:17:02.09#ibcon#*before return 0, iclass 15, count 2 2006.218.08:17:02.09#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.218.08:17:02.09#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.218.08:17:02.09#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.218.08:17:02.09#ibcon#ireg 7 cls_cnt 0 2006.218.08:17:02.09#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.218.08:17:02.21#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.218.08:17:02.21#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.218.08:17:02.21#ibcon#enter wrdev, iclass 15, count 0 2006.218.08:17:02.21#ibcon#first serial, iclass 15, count 0 2006.218.08:17:02.21#ibcon#enter sib2, iclass 15, count 0 2006.218.08:17:02.21#ibcon#flushed, iclass 15, count 0 2006.218.08:17:02.21#ibcon#about to write, iclass 15, count 0 2006.218.08:17:02.21#ibcon#wrote, iclass 15, count 0 2006.218.08:17:02.21#ibcon#about to read 3, iclass 15, count 0 2006.218.08:17:02.23#ibcon#read 3, iclass 15, count 0 2006.218.08:17:02.23#ibcon#about to read 4, iclass 15, count 0 2006.218.08:17:02.23#ibcon#read 4, iclass 15, count 0 2006.218.08:17:02.23#ibcon#about to read 5, iclass 15, count 0 2006.218.08:17:02.23#ibcon#read 5, iclass 15, count 0 2006.218.08:17:02.23#ibcon#about to read 6, iclass 15, count 0 2006.218.08:17:02.23#ibcon#read 6, iclass 15, count 0 2006.218.08:17:02.23#ibcon#end of sib2, iclass 15, count 0 2006.218.08:17:02.23#ibcon#*mode == 0, iclass 15, count 0 2006.218.08:17:02.23#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.218.08:17:02.23#ibcon#[27=USB\r\n] 2006.218.08:17:02.23#ibcon#*before write, iclass 15, count 0 2006.218.08:17:02.23#ibcon#enter sib2, iclass 15, count 0 2006.218.08:17:02.23#ibcon#flushed, iclass 15, count 0 2006.218.08:17:02.23#ibcon#about to write, iclass 15, count 0 2006.218.08:17:02.23#ibcon#wrote, iclass 15, count 0 2006.218.08:17:02.23#ibcon#about to read 3, iclass 15, count 0 2006.218.08:17:02.26#ibcon#read 3, iclass 15, count 0 2006.218.08:17:02.26#ibcon#about to read 4, iclass 15, count 0 2006.218.08:17:02.26#ibcon#read 4, iclass 15, count 0 2006.218.08:17:02.26#ibcon#about to read 5, iclass 15, count 0 2006.218.08:17:02.26#ibcon#read 5, iclass 15, count 0 2006.218.08:17:02.26#ibcon#about to read 6, iclass 15, count 0 2006.218.08:17:02.26#ibcon#read 6, iclass 15, count 0 2006.218.08:17:02.26#ibcon#end of sib2, iclass 15, count 0 2006.218.08:17:02.26#ibcon#*after write, iclass 15, count 0 2006.218.08:17:02.26#ibcon#*before return 0, iclass 15, count 0 2006.218.08:17:02.26#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.218.08:17:02.26#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.218.08:17:02.26#ibcon#about to clear, iclass 15 cls_cnt 0 2006.218.08:17:02.26#ibcon#cleared, iclass 15 cls_cnt 0 2006.218.08:17:02.26$vc4f8/vblo=6,752.99 2006.218.08:17:02.26#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.218.08:17:02.26#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.218.08:17:02.26#ibcon#ireg 17 cls_cnt 0 2006.218.08:17:02.26#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.218.08:17:02.26#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.218.08:17:02.26#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.218.08:17:02.26#ibcon#enter wrdev, iclass 17, count 0 2006.218.08:17:02.26#ibcon#first serial, iclass 17, count 0 2006.218.08:17:02.26#ibcon#enter sib2, iclass 17, count 0 2006.218.08:17:02.26#ibcon#flushed, iclass 17, count 0 2006.218.08:17:02.26#ibcon#about to write, iclass 17, count 0 2006.218.08:17:02.26#ibcon#wrote, iclass 17, count 0 2006.218.08:17:02.26#ibcon#about to read 3, iclass 17, count 0 2006.218.08:17:02.28#ibcon#read 3, iclass 17, count 0 2006.218.08:17:02.28#ibcon#about to read 4, iclass 17, count 0 2006.218.08:17:02.28#ibcon#read 4, iclass 17, count 0 2006.218.08:17:02.28#ibcon#about to read 5, iclass 17, count 0 2006.218.08:17:02.28#ibcon#read 5, iclass 17, count 0 2006.218.08:17:02.28#ibcon#about to read 6, iclass 17, count 0 2006.218.08:17:02.28#ibcon#read 6, iclass 17, count 0 2006.218.08:17:02.28#ibcon#end of sib2, iclass 17, count 0 2006.218.08:17:02.28#ibcon#*mode == 0, iclass 17, count 0 2006.218.08:17:02.28#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.218.08:17:02.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.218.08:17:02.28#ibcon#*before write, iclass 17, count 0 2006.218.08:17:02.28#ibcon#enter sib2, iclass 17, count 0 2006.218.08:17:02.28#ibcon#flushed, iclass 17, count 0 2006.218.08:17:02.28#ibcon#about to write, iclass 17, count 0 2006.218.08:17:02.28#ibcon#wrote, iclass 17, count 0 2006.218.08:17:02.28#ibcon#about to read 3, iclass 17, count 0 2006.218.08:17:02.32#ibcon#read 3, iclass 17, count 0 2006.218.08:17:02.32#ibcon#about to read 4, iclass 17, count 0 2006.218.08:17:02.32#ibcon#read 4, iclass 17, count 0 2006.218.08:17:02.32#ibcon#about to read 5, iclass 17, count 0 2006.218.08:17:02.32#ibcon#read 5, iclass 17, count 0 2006.218.08:17:02.32#ibcon#about to read 6, iclass 17, count 0 2006.218.08:17:02.32#ibcon#read 6, iclass 17, count 0 2006.218.08:17:02.32#ibcon#end of sib2, iclass 17, count 0 2006.218.08:17:02.32#ibcon#*after write, iclass 17, count 0 2006.218.08:17:02.32#ibcon#*before return 0, iclass 17, count 0 2006.218.08:17:02.32#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.218.08:17:02.32#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.218.08:17:02.32#ibcon#about to clear, iclass 17 cls_cnt 0 2006.218.08:17:02.32#ibcon#cleared, iclass 17 cls_cnt 0 2006.218.08:17:02.32$vc4f8/vb=6,4 2006.218.08:17:02.32#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.218.08:17:02.32#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.218.08:17:02.32#ibcon#ireg 11 cls_cnt 2 2006.218.08:17:02.32#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.218.08:17:02.38#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.218.08:17:02.38#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.218.08:17:02.38#ibcon#enter wrdev, iclass 19, count 2 2006.218.08:17:02.38#ibcon#first serial, iclass 19, count 2 2006.218.08:17:02.38#ibcon#enter sib2, iclass 19, count 2 2006.218.08:17:02.38#ibcon#flushed, iclass 19, count 2 2006.218.08:17:02.38#ibcon#about to write, iclass 19, count 2 2006.218.08:17:02.38#ibcon#wrote, iclass 19, count 2 2006.218.08:17:02.38#ibcon#about to read 3, iclass 19, count 2 2006.218.08:17:02.40#ibcon#read 3, iclass 19, count 2 2006.218.08:17:02.40#ibcon#about to read 4, iclass 19, count 2 2006.218.08:17:02.40#ibcon#read 4, iclass 19, count 2 2006.218.08:17:02.40#ibcon#about to read 5, iclass 19, count 2 2006.218.08:17:02.40#ibcon#read 5, iclass 19, count 2 2006.218.08:17:02.40#ibcon#about to read 6, iclass 19, count 2 2006.218.08:17:02.40#ibcon#read 6, iclass 19, count 2 2006.218.08:17:02.40#ibcon#end of sib2, iclass 19, count 2 2006.218.08:17:02.40#ibcon#*mode == 0, iclass 19, count 2 2006.218.08:17:02.40#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.218.08:17:02.40#ibcon#[27=AT06-04\r\n] 2006.218.08:17:02.40#ibcon#*before write, iclass 19, count 2 2006.218.08:17:02.40#ibcon#enter sib2, iclass 19, count 2 2006.218.08:17:02.40#ibcon#flushed, iclass 19, count 2 2006.218.08:17:02.40#ibcon#about to write, iclass 19, count 2 2006.218.08:17:02.40#ibcon#wrote, iclass 19, count 2 2006.218.08:17:02.40#ibcon#about to read 3, iclass 19, count 2 2006.218.08:17:02.43#ibcon#read 3, iclass 19, count 2 2006.218.08:17:02.43#ibcon#about to read 4, iclass 19, count 2 2006.218.08:17:02.43#ibcon#read 4, iclass 19, count 2 2006.218.08:17:02.43#ibcon#about to read 5, iclass 19, count 2 2006.218.08:17:02.43#ibcon#read 5, iclass 19, count 2 2006.218.08:17:02.43#ibcon#about to read 6, iclass 19, count 2 2006.218.08:17:02.43#ibcon#read 6, iclass 19, count 2 2006.218.08:17:02.43#ibcon#end of sib2, iclass 19, count 2 2006.218.08:17:02.43#ibcon#*after write, iclass 19, count 2 2006.218.08:17:02.43#ibcon#*before return 0, iclass 19, count 2 2006.218.08:17:02.43#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.218.08:17:02.43#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.218.08:17:02.43#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.218.08:17:02.43#ibcon#ireg 7 cls_cnt 0 2006.218.08:17:02.43#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.218.08:17:02.55#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.218.08:17:02.55#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.218.08:17:02.55#ibcon#enter wrdev, iclass 19, count 0 2006.218.08:17:02.55#ibcon#first serial, iclass 19, count 0 2006.218.08:17:02.55#ibcon#enter sib2, iclass 19, count 0 2006.218.08:17:02.55#ibcon#flushed, iclass 19, count 0 2006.218.08:17:02.55#ibcon#about to write, iclass 19, count 0 2006.218.08:17:02.55#ibcon#wrote, iclass 19, count 0 2006.218.08:17:02.55#ibcon#about to read 3, iclass 19, count 0 2006.218.08:17:02.57#ibcon#read 3, iclass 19, count 0 2006.218.08:17:02.57#ibcon#about to read 4, iclass 19, count 0 2006.218.08:17:02.57#ibcon#read 4, iclass 19, count 0 2006.218.08:17:02.57#ibcon#about to read 5, iclass 19, count 0 2006.218.08:17:02.57#ibcon#read 5, iclass 19, count 0 2006.218.08:17:02.57#ibcon#about to read 6, iclass 19, count 0 2006.218.08:17:02.57#ibcon#read 6, iclass 19, count 0 2006.218.08:17:02.57#ibcon#end of sib2, iclass 19, count 0 2006.218.08:17:02.57#ibcon#*mode == 0, iclass 19, count 0 2006.218.08:17:02.57#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.218.08:17:02.57#ibcon#[27=USB\r\n] 2006.218.08:17:02.57#ibcon#*before write, iclass 19, count 0 2006.218.08:17:02.57#ibcon#enter sib2, iclass 19, count 0 2006.218.08:17:02.57#ibcon#flushed, iclass 19, count 0 2006.218.08:17:02.57#ibcon#about to write, iclass 19, count 0 2006.218.08:17:02.57#ibcon#wrote, iclass 19, count 0 2006.218.08:17:02.57#ibcon#about to read 3, iclass 19, count 0 2006.218.08:17:02.60#ibcon#read 3, iclass 19, count 0 2006.218.08:17:02.60#ibcon#about to read 4, iclass 19, count 0 2006.218.08:17:02.60#ibcon#read 4, iclass 19, count 0 2006.218.08:17:02.60#ibcon#about to read 5, iclass 19, count 0 2006.218.08:17:02.60#ibcon#read 5, iclass 19, count 0 2006.218.08:17:02.60#ibcon#about to read 6, iclass 19, count 0 2006.218.08:17:02.60#ibcon#read 6, iclass 19, count 0 2006.218.08:17:02.60#ibcon#end of sib2, iclass 19, count 0 2006.218.08:17:02.60#ibcon#*after write, iclass 19, count 0 2006.218.08:17:02.60#ibcon#*before return 0, iclass 19, count 0 2006.218.08:17:02.60#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.218.08:17:02.60#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.218.08:17:02.60#ibcon#about to clear, iclass 19 cls_cnt 0 2006.218.08:17:02.60#ibcon#cleared, iclass 19 cls_cnt 0 2006.218.08:17:02.60$vc4f8/vabw=wide 2006.218.08:17:02.60#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.218.08:17:02.60#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.218.08:17:02.60#ibcon#ireg 8 cls_cnt 0 2006.218.08:17:02.60#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.218.08:17:02.60#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.218.08:17:02.60#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.218.08:17:02.60#ibcon#enter wrdev, iclass 21, count 0 2006.218.08:17:02.60#ibcon#first serial, iclass 21, count 0 2006.218.08:17:02.60#ibcon#enter sib2, iclass 21, count 0 2006.218.08:17:02.60#ibcon#flushed, iclass 21, count 0 2006.218.08:17:02.60#ibcon#about to write, iclass 21, count 0 2006.218.08:17:02.60#ibcon#wrote, iclass 21, count 0 2006.218.08:17:02.60#ibcon#about to read 3, iclass 21, count 0 2006.218.08:17:02.62#ibcon#read 3, iclass 21, count 0 2006.218.08:17:02.62#ibcon#about to read 4, iclass 21, count 0 2006.218.08:17:02.62#ibcon#read 4, iclass 21, count 0 2006.218.08:17:02.62#ibcon#about to read 5, iclass 21, count 0 2006.218.08:17:02.62#ibcon#read 5, iclass 21, count 0 2006.218.08:17:02.62#ibcon#about to read 6, iclass 21, count 0 2006.218.08:17:02.62#ibcon#read 6, iclass 21, count 0 2006.218.08:17:02.62#ibcon#end of sib2, iclass 21, count 0 2006.218.08:17:02.62#ibcon#*mode == 0, iclass 21, count 0 2006.218.08:17:02.62#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.218.08:17:02.62#ibcon#[25=BW32\r\n] 2006.218.08:17:02.62#ibcon#*before write, iclass 21, count 0 2006.218.08:17:02.62#ibcon#enter sib2, iclass 21, count 0 2006.218.08:17:02.62#ibcon#flushed, iclass 21, count 0 2006.218.08:17:02.62#ibcon#about to write, iclass 21, count 0 2006.218.08:17:02.62#ibcon#wrote, iclass 21, count 0 2006.218.08:17:02.62#ibcon#about to read 3, iclass 21, count 0 2006.218.08:17:02.65#ibcon#read 3, iclass 21, count 0 2006.218.08:17:02.65#ibcon#about to read 4, iclass 21, count 0 2006.218.08:17:02.65#ibcon#read 4, iclass 21, count 0 2006.218.08:17:02.65#ibcon#about to read 5, iclass 21, count 0 2006.218.08:17:02.65#ibcon#read 5, iclass 21, count 0 2006.218.08:17:02.65#ibcon#about to read 6, iclass 21, count 0 2006.218.08:17:02.65#ibcon#read 6, iclass 21, count 0 2006.218.08:17:02.65#ibcon#end of sib2, iclass 21, count 0 2006.218.08:17:02.65#ibcon#*after write, iclass 21, count 0 2006.218.08:17:02.65#ibcon#*before return 0, iclass 21, count 0 2006.218.08:17:02.65#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.218.08:17:02.65#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.218.08:17:02.65#ibcon#about to clear, iclass 21 cls_cnt 0 2006.218.08:17:02.65#ibcon#cleared, iclass 21 cls_cnt 0 2006.218.08:17:02.65$vc4f8/vbbw=wide 2006.218.08:17:02.65#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.218.08:17:02.65#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.218.08:17:02.65#ibcon#ireg 8 cls_cnt 0 2006.218.08:17:02.65#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.218.08:17:02.72#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.218.08:17:02.72#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.218.08:17:02.72#ibcon#enter wrdev, iclass 23, count 0 2006.218.08:17:02.72#ibcon#first serial, iclass 23, count 0 2006.218.08:17:02.72#ibcon#enter sib2, iclass 23, count 0 2006.218.08:17:02.72#ibcon#flushed, iclass 23, count 0 2006.218.08:17:02.72#ibcon#about to write, iclass 23, count 0 2006.218.08:17:02.72#ibcon#wrote, iclass 23, count 0 2006.218.08:17:02.72#ibcon#about to read 3, iclass 23, count 0 2006.218.08:17:02.74#ibcon#read 3, iclass 23, count 0 2006.218.08:17:02.74#ibcon#about to read 4, iclass 23, count 0 2006.218.08:17:02.74#ibcon#read 4, iclass 23, count 0 2006.218.08:17:02.74#ibcon#about to read 5, iclass 23, count 0 2006.218.08:17:02.74#ibcon#read 5, iclass 23, count 0 2006.218.08:17:02.74#ibcon#about to read 6, iclass 23, count 0 2006.218.08:17:02.74#ibcon#read 6, iclass 23, count 0 2006.218.08:17:02.74#ibcon#end of sib2, iclass 23, count 0 2006.218.08:17:02.74#ibcon#*mode == 0, iclass 23, count 0 2006.218.08:17:02.74#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.218.08:17:02.74#ibcon#[27=BW32\r\n] 2006.218.08:17:02.74#ibcon#*before write, iclass 23, count 0 2006.218.08:17:02.74#ibcon#enter sib2, iclass 23, count 0 2006.218.08:17:02.74#ibcon#flushed, iclass 23, count 0 2006.218.08:17:02.74#ibcon#about to write, iclass 23, count 0 2006.218.08:17:02.74#ibcon#wrote, iclass 23, count 0 2006.218.08:17:02.74#ibcon#about to read 3, iclass 23, count 0 2006.218.08:17:02.77#ibcon#read 3, iclass 23, count 0 2006.218.08:17:02.77#ibcon#about to read 4, iclass 23, count 0 2006.218.08:17:02.77#ibcon#read 4, iclass 23, count 0 2006.218.08:17:02.77#ibcon#about to read 5, iclass 23, count 0 2006.218.08:17:02.77#ibcon#read 5, iclass 23, count 0 2006.218.08:17:02.77#ibcon#about to read 6, iclass 23, count 0 2006.218.08:17:02.77#ibcon#read 6, iclass 23, count 0 2006.218.08:17:02.77#ibcon#end of sib2, iclass 23, count 0 2006.218.08:17:02.77#ibcon#*after write, iclass 23, count 0 2006.218.08:17:02.77#ibcon#*before return 0, iclass 23, count 0 2006.218.08:17:02.77#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.218.08:17:02.77#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.218.08:17:02.77#ibcon#about to clear, iclass 23 cls_cnt 0 2006.218.08:17:02.77#ibcon#cleared, iclass 23 cls_cnt 0 2006.218.08:17:02.77$4f8m12a/ifd4f 2006.218.08:17:02.77$ifd4f/lo= 2006.218.08:17:02.77$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.218.08:17:02.77$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.218.08:17:02.77$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.218.08:17:02.77$ifd4f/patch= 2006.218.08:17:02.77$ifd4f/patch=lo1,a1,a2,a3,a4 2006.218.08:17:02.77$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.218.08:17:02.77$ifd4f/patch=lo3,a5,a6,a7,a8 2006.218.08:17:02.77$4f8m12a/"form=m,16.000,1:2 2006.218.08:17:02.77$4f8m12a/"tpicd 2006.218.08:17:02.77$4f8m12a/echo=off 2006.218.08:17:02.77$4f8m12a/xlog=off 2006.218.08:17:02.77:!2006.218.08:17:40 2006.218.08:17:23.14#trakl#Source acquired 2006.218.08:17:24.14#flagr#flagr/antenna,acquired 2006.218.08:17:40.00:preob 2006.218.08:17:40.14/onsource/TRACKING 2006.218.08:17:40.14:!2006.218.08:17:50 2006.218.08:17:50.00:data_valid=on 2006.218.08:17:50.00:midob 2006.218.08:17:51.14/onsource/TRACKING 2006.218.08:17:51.14/wx/30.76,1007.6,74 2006.218.08:17:51.26/cable/+6.3867E-03 2006.218.08:17:52.35/va/01,05,usb,yes,33,35 2006.218.08:17:52.35/va/02,04,usb,yes,31,33 2006.218.08:17:52.35/va/03,04,usb,yes,29,29 2006.218.08:17:52.35/va/04,04,usb,yes,33,35 2006.218.08:17:52.35/va/05,07,usb,yes,35,37 2006.218.08:17:52.35/va/06,06,usb,yes,34,34 2006.218.08:17:52.35/va/07,06,usb,yes,35,34 2006.218.08:17:52.35/va/08,07,usb,yes,33,32 2006.218.08:17:52.58/valo/01,532.99,yes,locked 2006.218.08:17:52.58/valo/02,572.99,yes,locked 2006.218.08:17:52.58/valo/03,672.99,yes,locked 2006.218.08:17:52.58/valo/04,832.99,yes,locked 2006.218.08:17:52.58/valo/05,652.99,yes,locked 2006.218.08:17:52.58/valo/06,772.99,yes,locked 2006.218.08:17:52.58/valo/07,832.99,yes,locked 2006.218.08:17:52.58/valo/08,852.99,yes,locked 2006.218.08:17:53.67/vb/01,04,usb,yes,31,30 2006.218.08:17:53.67/vb/02,04,usb,yes,33,34 2006.218.08:17:53.67/vb/03,04,usb,yes,29,33 2006.218.08:17:53.67/vb/04,04,usb,yes,30,30 2006.218.08:17:53.67/vb/05,04,usb,yes,28,33 2006.218.08:17:53.67/vb/06,04,usb,yes,29,32 2006.218.08:17:53.67/vb/07,04,usb,yes,32,31 2006.218.08:17:53.67/vb/08,04,usb,yes,29,33 2006.218.08:17:53.90/vblo/01,632.99,yes,locked 2006.218.08:17:53.90/vblo/02,640.99,yes,locked 2006.218.08:17:53.90/vblo/03,656.99,yes,locked 2006.218.08:17:53.90/vblo/04,712.99,yes,locked 2006.218.08:17:53.90/vblo/05,744.99,yes,locked 2006.218.08:17:53.90/vblo/06,752.99,yes,locked 2006.218.08:17:53.90/vblo/07,734.99,yes,locked 2006.218.08:17:53.90/vblo/08,744.99,yes,locked 2006.218.08:17:54.05/vabw/8 2006.218.08:17:54.21/vbbw/8 2006.218.08:17:54.30/xfe/off,on,15.0 2006.218.08:17:54.67/ifatt/23,28,28,28 2006.218.08:17:55.07/fmout-gps/S +4.59E-07 2006.218.08:17:55.14:!2006.218.08:18:50 2006.218.08:18:50.01:data_valid=off 2006.218.08:18:50.01:postob 2006.218.08:18:50.09/cable/+6.3859E-03 2006.218.08:18:50.09/wx/30.73,1007.6,75 2006.218.08:18:51.07/fmout-gps/S +4.58E-07 2006.218.08:18:51.07:scan_name=218-0820,k06218,60 2006.218.08:18:51.07:source=0642+449,064632.03,445116.6,2000.0,cw 2006.218.08:18:51.13#flagr#flagr/antenna,new-source 2006.218.08:18:52.13:checkk5 2006.218.08:18:52.51/chk_autoobs//k5ts1/ autoobs is running! 2006.218.08:18:52.88/chk_autoobs//k5ts2/ autoobs is running! 2006.218.08:18:53.26/chk_autoobs//k5ts3/ autoobs is running! 2006.218.08:18:53.63/chk_autoobs//k5ts4/ autoobs is running! 2006.218.08:18:54.00/chk_obsdata//k5ts1/T2180817??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.08:18:54.37/chk_obsdata//k5ts2/T2180817??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.08:18:54.73/chk_obsdata//k5ts3/T2180817??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.08:18:55.11/chk_obsdata//k5ts4/T2180817??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.08:18:55.80/k5log//k5ts1_log_newline 2006.218.08:18:56.48/k5log//k5ts2_log_newline 2006.218.08:18:57.17/k5log//k5ts3_log_newline 2006.218.08:18:57.86/k5log//k5ts4_log_newline 2006.218.08:18:57.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.218.08:18:57.89:4f8m12a=3 2006.218.08:18:57.89$4f8m12a/echo=on 2006.218.08:18:57.89$4f8m12a/pcalon 2006.218.08:18:57.89$pcalon/"no phase cal control is implemented here 2006.218.08:18:57.89$4f8m12a/"tpicd=stop 2006.218.08:18:57.89$4f8m12a/vc4f8 2006.218.08:18:57.89$vc4f8/valo=1,532.99 2006.218.08:18:57.89#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.218.08:18:57.89#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.218.08:18:57.89#ibcon#ireg 17 cls_cnt 0 2006.218.08:18:57.89#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.218.08:18:57.89#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.218.08:18:57.89#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.218.08:18:57.89#ibcon#enter wrdev, iclass 34, count 0 2006.218.08:18:57.89#ibcon#first serial, iclass 34, count 0 2006.218.08:18:57.89#ibcon#enter sib2, iclass 34, count 0 2006.218.08:18:57.89#ibcon#flushed, iclass 34, count 0 2006.218.08:18:57.89#ibcon#about to write, iclass 34, count 0 2006.218.08:18:57.89#ibcon#wrote, iclass 34, count 0 2006.218.08:18:57.89#ibcon#about to read 3, iclass 34, count 0 2006.218.08:18:57.93#ibcon#read 3, iclass 34, count 0 2006.218.08:18:57.93#ibcon#about to read 4, iclass 34, count 0 2006.218.08:18:57.93#ibcon#read 4, iclass 34, count 0 2006.218.08:18:57.93#ibcon#about to read 5, iclass 34, count 0 2006.218.08:18:57.93#ibcon#read 5, iclass 34, count 0 2006.218.08:18:57.93#ibcon#about to read 6, iclass 34, count 0 2006.218.08:18:57.93#ibcon#read 6, iclass 34, count 0 2006.218.08:18:57.93#ibcon#end of sib2, iclass 34, count 0 2006.218.08:18:57.93#ibcon#*mode == 0, iclass 34, count 0 2006.218.08:18:57.93#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.218.08:18:57.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.218.08:18:57.93#ibcon#*before write, iclass 34, count 0 2006.218.08:18:57.93#ibcon#enter sib2, iclass 34, count 0 2006.218.08:18:57.93#ibcon#flushed, iclass 34, count 0 2006.218.08:18:57.93#ibcon#about to write, iclass 34, count 0 2006.218.08:18:57.93#ibcon#wrote, iclass 34, count 0 2006.218.08:18:57.93#ibcon#about to read 3, iclass 34, count 0 2006.218.08:18:57.98#ibcon#read 3, iclass 34, count 0 2006.218.08:18:57.98#ibcon#about to read 4, iclass 34, count 0 2006.218.08:18:57.98#ibcon#read 4, iclass 34, count 0 2006.218.08:18:57.98#ibcon#about to read 5, iclass 34, count 0 2006.218.08:18:57.98#ibcon#read 5, iclass 34, count 0 2006.218.08:18:57.98#ibcon#about to read 6, iclass 34, count 0 2006.218.08:18:57.98#ibcon#read 6, iclass 34, count 0 2006.218.08:18:57.98#ibcon#end of sib2, iclass 34, count 0 2006.218.08:18:57.98#ibcon#*after write, iclass 34, count 0 2006.218.08:18:57.98#ibcon#*before return 0, iclass 34, count 0 2006.218.08:18:57.98#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.218.08:18:57.98#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.218.08:18:57.98#ibcon#about to clear, iclass 34 cls_cnt 0 2006.218.08:18:57.98#ibcon#cleared, iclass 34 cls_cnt 0 2006.218.08:18:57.98$vc4f8/va=1,5 2006.218.08:18:57.98#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.218.08:18:57.98#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.218.08:18:57.98#ibcon#ireg 11 cls_cnt 2 2006.218.08:18:57.98#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.218.08:18:57.98#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.218.08:18:57.98#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.218.08:18:57.98#ibcon#enter wrdev, iclass 36, count 2 2006.218.08:18:57.98#ibcon#first serial, iclass 36, count 2 2006.218.08:18:57.98#ibcon#enter sib2, iclass 36, count 2 2006.218.08:18:57.98#ibcon#flushed, iclass 36, count 2 2006.218.08:18:57.98#ibcon#about to write, iclass 36, count 2 2006.218.08:18:57.98#ibcon#wrote, iclass 36, count 2 2006.218.08:18:57.98#ibcon#about to read 3, iclass 36, count 2 2006.218.08:18:58.00#ibcon#read 3, iclass 36, count 2 2006.218.08:18:58.00#ibcon#about to read 4, iclass 36, count 2 2006.218.08:18:58.00#ibcon#read 4, iclass 36, count 2 2006.218.08:18:58.00#ibcon#about to read 5, iclass 36, count 2 2006.218.08:18:58.00#ibcon#read 5, iclass 36, count 2 2006.218.08:18:58.00#ibcon#about to read 6, iclass 36, count 2 2006.218.08:18:58.00#ibcon#read 6, iclass 36, count 2 2006.218.08:18:58.00#ibcon#end of sib2, iclass 36, count 2 2006.218.08:18:58.00#ibcon#*mode == 0, iclass 36, count 2 2006.218.08:18:58.00#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.218.08:18:58.00#ibcon#[25=AT01-05\r\n] 2006.218.08:18:58.00#ibcon#*before write, iclass 36, count 2 2006.218.08:18:58.00#ibcon#enter sib2, iclass 36, count 2 2006.218.08:18:58.00#ibcon#flushed, iclass 36, count 2 2006.218.08:18:58.00#ibcon#about to write, iclass 36, count 2 2006.218.08:18:58.00#ibcon#wrote, iclass 36, count 2 2006.218.08:18:58.00#ibcon#about to read 3, iclass 36, count 2 2006.218.08:18:58.03#ibcon#read 3, iclass 36, count 2 2006.218.08:18:58.03#ibcon#about to read 4, iclass 36, count 2 2006.218.08:18:58.03#ibcon#read 4, iclass 36, count 2 2006.218.08:18:58.03#ibcon#about to read 5, iclass 36, count 2 2006.218.08:18:58.03#ibcon#read 5, iclass 36, count 2 2006.218.08:18:58.03#ibcon#about to read 6, iclass 36, count 2 2006.218.08:18:58.03#ibcon#read 6, iclass 36, count 2 2006.218.08:18:58.03#ibcon#end of sib2, iclass 36, count 2 2006.218.08:18:58.03#ibcon#*after write, iclass 36, count 2 2006.218.08:18:58.03#ibcon#*before return 0, iclass 36, count 2 2006.218.08:18:58.03#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.218.08:18:58.03#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.218.08:18:58.03#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.218.08:18:58.03#ibcon#ireg 7 cls_cnt 0 2006.218.08:18:58.03#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.218.08:18:58.15#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.218.08:18:58.15#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.218.08:18:58.15#ibcon#enter wrdev, iclass 36, count 0 2006.218.08:18:58.15#ibcon#first serial, iclass 36, count 0 2006.218.08:18:58.15#ibcon#enter sib2, iclass 36, count 0 2006.218.08:18:58.15#ibcon#flushed, iclass 36, count 0 2006.218.08:18:58.15#ibcon#about to write, iclass 36, count 0 2006.218.08:18:58.15#ibcon#wrote, iclass 36, count 0 2006.218.08:18:58.15#ibcon#about to read 3, iclass 36, count 0 2006.218.08:18:58.17#ibcon#read 3, iclass 36, count 0 2006.218.08:18:58.17#ibcon#about to read 4, iclass 36, count 0 2006.218.08:18:58.17#ibcon#read 4, iclass 36, count 0 2006.218.08:18:58.17#ibcon#about to read 5, iclass 36, count 0 2006.218.08:18:58.17#ibcon#read 5, iclass 36, count 0 2006.218.08:18:58.17#ibcon#about to read 6, iclass 36, count 0 2006.218.08:18:58.17#ibcon#read 6, iclass 36, count 0 2006.218.08:18:58.17#ibcon#end of sib2, iclass 36, count 0 2006.218.08:18:58.17#ibcon#*mode == 0, iclass 36, count 0 2006.218.08:18:58.17#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.218.08:18:58.17#ibcon#[25=USB\r\n] 2006.218.08:18:58.17#ibcon#*before write, iclass 36, count 0 2006.218.08:18:58.17#ibcon#enter sib2, iclass 36, count 0 2006.218.08:18:58.17#ibcon#flushed, iclass 36, count 0 2006.218.08:18:58.17#ibcon#about to write, iclass 36, count 0 2006.218.08:18:58.17#ibcon#wrote, iclass 36, count 0 2006.218.08:18:58.17#ibcon#about to read 3, iclass 36, count 0 2006.218.08:18:58.20#ibcon#read 3, iclass 36, count 0 2006.218.08:18:58.20#ibcon#about to read 4, iclass 36, count 0 2006.218.08:18:58.20#ibcon#read 4, iclass 36, count 0 2006.218.08:18:58.20#ibcon#about to read 5, iclass 36, count 0 2006.218.08:18:58.20#ibcon#read 5, iclass 36, count 0 2006.218.08:18:58.20#ibcon#about to read 6, iclass 36, count 0 2006.218.08:18:58.20#ibcon#read 6, iclass 36, count 0 2006.218.08:18:58.20#ibcon#end of sib2, iclass 36, count 0 2006.218.08:18:58.20#ibcon#*after write, iclass 36, count 0 2006.218.08:18:58.20#ibcon#*before return 0, iclass 36, count 0 2006.218.08:18:58.20#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.218.08:18:58.20#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.218.08:18:58.20#ibcon#about to clear, iclass 36 cls_cnt 0 2006.218.08:18:58.20#ibcon#cleared, iclass 36 cls_cnt 0 2006.218.08:18:58.20$vc4f8/valo=2,572.99 2006.218.08:18:58.20#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.218.08:18:58.20#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.218.08:18:58.20#ibcon#ireg 17 cls_cnt 0 2006.218.08:18:58.20#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.218.08:18:58.20#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.218.08:18:58.20#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.218.08:18:58.20#ibcon#enter wrdev, iclass 38, count 0 2006.218.08:18:58.20#ibcon#first serial, iclass 38, count 0 2006.218.08:18:58.20#ibcon#enter sib2, iclass 38, count 0 2006.218.08:18:58.20#ibcon#flushed, iclass 38, count 0 2006.218.08:18:58.20#ibcon#about to write, iclass 38, count 0 2006.218.08:18:58.20#ibcon#wrote, iclass 38, count 0 2006.218.08:18:58.20#ibcon#about to read 3, iclass 38, count 0 2006.218.08:18:58.22#ibcon#read 3, iclass 38, count 0 2006.218.08:18:58.22#ibcon#about to read 4, iclass 38, count 0 2006.218.08:18:58.22#ibcon#read 4, iclass 38, count 0 2006.218.08:18:58.22#ibcon#about to read 5, iclass 38, count 0 2006.218.08:18:58.22#ibcon#read 5, iclass 38, count 0 2006.218.08:18:58.22#ibcon#about to read 6, iclass 38, count 0 2006.218.08:18:58.22#ibcon#read 6, iclass 38, count 0 2006.218.08:18:58.22#ibcon#end of sib2, iclass 38, count 0 2006.218.08:18:58.22#ibcon#*mode == 0, iclass 38, count 0 2006.218.08:18:58.22#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.218.08:18:58.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.218.08:18:58.22#ibcon#*before write, iclass 38, count 0 2006.218.08:18:58.22#ibcon#enter sib2, iclass 38, count 0 2006.218.08:18:58.22#ibcon#flushed, iclass 38, count 0 2006.218.08:18:58.22#ibcon#about to write, iclass 38, count 0 2006.218.08:18:58.22#ibcon#wrote, iclass 38, count 0 2006.218.08:18:58.22#ibcon#about to read 3, iclass 38, count 0 2006.218.08:18:58.26#ibcon#read 3, iclass 38, count 0 2006.218.08:18:58.26#ibcon#about to read 4, iclass 38, count 0 2006.218.08:18:58.26#ibcon#read 4, iclass 38, count 0 2006.218.08:18:58.26#ibcon#about to read 5, iclass 38, count 0 2006.218.08:18:58.26#ibcon#read 5, iclass 38, count 0 2006.218.08:18:58.26#ibcon#about to read 6, iclass 38, count 0 2006.218.08:18:58.26#ibcon#read 6, iclass 38, count 0 2006.218.08:18:58.26#ibcon#end of sib2, iclass 38, count 0 2006.218.08:18:58.26#ibcon#*after write, iclass 38, count 0 2006.218.08:18:58.26#ibcon#*before return 0, iclass 38, count 0 2006.218.08:18:58.26#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.218.08:18:58.26#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.218.08:18:58.26#ibcon#about to clear, iclass 38 cls_cnt 0 2006.218.08:18:58.26#ibcon#cleared, iclass 38 cls_cnt 0 2006.218.08:18:58.26$vc4f8/va=2,4 2006.218.08:18:58.26#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.218.08:18:58.26#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.218.08:18:58.26#ibcon#ireg 11 cls_cnt 2 2006.218.08:18:58.26#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.218.08:18:58.32#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.218.08:18:58.32#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.218.08:18:58.32#ibcon#enter wrdev, iclass 40, count 2 2006.218.08:18:58.32#ibcon#first serial, iclass 40, count 2 2006.218.08:18:58.32#ibcon#enter sib2, iclass 40, count 2 2006.218.08:18:58.32#ibcon#flushed, iclass 40, count 2 2006.218.08:18:58.32#ibcon#about to write, iclass 40, count 2 2006.218.08:18:58.32#ibcon#wrote, iclass 40, count 2 2006.218.08:18:58.32#ibcon#about to read 3, iclass 40, count 2 2006.218.08:18:58.34#ibcon#read 3, iclass 40, count 2 2006.218.08:18:58.34#ibcon#about to read 4, iclass 40, count 2 2006.218.08:18:58.34#ibcon#read 4, iclass 40, count 2 2006.218.08:18:58.34#ibcon#about to read 5, iclass 40, count 2 2006.218.08:18:58.34#ibcon#read 5, iclass 40, count 2 2006.218.08:18:58.34#ibcon#about to read 6, iclass 40, count 2 2006.218.08:18:58.34#ibcon#read 6, iclass 40, count 2 2006.218.08:18:58.34#ibcon#end of sib2, iclass 40, count 2 2006.218.08:18:58.34#ibcon#*mode == 0, iclass 40, count 2 2006.218.08:18:58.34#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.218.08:18:58.34#ibcon#[25=AT02-04\r\n] 2006.218.08:18:58.34#ibcon#*before write, iclass 40, count 2 2006.218.08:18:58.34#ibcon#enter sib2, iclass 40, count 2 2006.218.08:18:58.34#ibcon#flushed, iclass 40, count 2 2006.218.08:18:58.34#ibcon#about to write, iclass 40, count 2 2006.218.08:18:58.34#ibcon#wrote, iclass 40, count 2 2006.218.08:18:58.34#ibcon#about to read 3, iclass 40, count 2 2006.218.08:18:58.37#ibcon#read 3, iclass 40, count 2 2006.218.08:18:58.37#ibcon#about to read 4, iclass 40, count 2 2006.218.08:18:58.37#ibcon#read 4, iclass 40, count 2 2006.218.08:18:58.37#ibcon#about to read 5, iclass 40, count 2 2006.218.08:18:58.37#ibcon#read 5, iclass 40, count 2 2006.218.08:18:58.37#ibcon#about to read 6, iclass 40, count 2 2006.218.08:18:58.37#ibcon#read 6, iclass 40, count 2 2006.218.08:18:58.37#ibcon#end of sib2, iclass 40, count 2 2006.218.08:18:58.37#ibcon#*after write, iclass 40, count 2 2006.218.08:18:58.37#ibcon#*before return 0, iclass 40, count 2 2006.218.08:18:58.37#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.218.08:18:58.37#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.218.08:18:58.37#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.218.08:18:58.37#ibcon#ireg 7 cls_cnt 0 2006.218.08:18:58.37#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.218.08:18:58.49#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.218.08:18:58.49#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.218.08:18:58.49#ibcon#enter wrdev, iclass 40, count 0 2006.218.08:18:58.49#ibcon#first serial, iclass 40, count 0 2006.218.08:18:58.49#ibcon#enter sib2, iclass 40, count 0 2006.218.08:18:58.49#ibcon#flushed, iclass 40, count 0 2006.218.08:18:58.49#ibcon#about to write, iclass 40, count 0 2006.218.08:18:58.49#ibcon#wrote, iclass 40, count 0 2006.218.08:18:58.49#ibcon#about to read 3, iclass 40, count 0 2006.218.08:18:58.51#ibcon#read 3, iclass 40, count 0 2006.218.08:18:58.51#ibcon#about to read 4, iclass 40, count 0 2006.218.08:18:58.51#ibcon#read 4, iclass 40, count 0 2006.218.08:18:58.51#ibcon#about to read 5, iclass 40, count 0 2006.218.08:18:58.51#ibcon#read 5, iclass 40, count 0 2006.218.08:18:58.51#ibcon#about to read 6, iclass 40, count 0 2006.218.08:18:58.51#ibcon#read 6, iclass 40, count 0 2006.218.08:18:58.51#ibcon#end of sib2, iclass 40, count 0 2006.218.08:18:58.51#ibcon#*mode == 0, iclass 40, count 0 2006.218.08:18:58.51#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.218.08:18:58.51#ibcon#[25=USB\r\n] 2006.218.08:18:58.51#ibcon#*before write, iclass 40, count 0 2006.218.08:18:58.51#ibcon#enter sib2, iclass 40, count 0 2006.218.08:18:58.51#ibcon#flushed, iclass 40, count 0 2006.218.08:18:58.51#ibcon#about to write, iclass 40, count 0 2006.218.08:18:58.51#ibcon#wrote, iclass 40, count 0 2006.218.08:18:58.51#ibcon#about to read 3, iclass 40, count 0 2006.218.08:18:58.54#ibcon#read 3, iclass 40, count 0 2006.218.08:18:58.54#ibcon#about to read 4, iclass 40, count 0 2006.218.08:18:58.54#ibcon#read 4, iclass 40, count 0 2006.218.08:18:58.54#ibcon#about to read 5, iclass 40, count 0 2006.218.08:18:58.54#ibcon#read 5, iclass 40, count 0 2006.218.08:18:58.54#ibcon#about to read 6, iclass 40, count 0 2006.218.08:18:58.54#ibcon#read 6, iclass 40, count 0 2006.218.08:18:58.54#ibcon#end of sib2, iclass 40, count 0 2006.218.08:18:58.54#ibcon#*after write, iclass 40, count 0 2006.218.08:18:58.54#ibcon#*before return 0, iclass 40, count 0 2006.218.08:18:58.54#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.218.08:18:58.54#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.218.08:18:58.54#ibcon#about to clear, iclass 40 cls_cnt 0 2006.218.08:18:58.54#ibcon#cleared, iclass 40 cls_cnt 0 2006.218.08:18:58.54$vc4f8/valo=3,672.99 2006.218.08:18:58.54#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.218.08:18:58.54#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.218.08:18:58.54#ibcon#ireg 17 cls_cnt 0 2006.218.08:18:58.54#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.218.08:18:58.54#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.218.08:18:58.54#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.218.08:18:58.54#ibcon#enter wrdev, iclass 4, count 0 2006.218.08:18:58.54#ibcon#first serial, iclass 4, count 0 2006.218.08:18:58.54#ibcon#enter sib2, iclass 4, count 0 2006.218.08:18:58.54#ibcon#flushed, iclass 4, count 0 2006.218.08:18:58.54#ibcon#about to write, iclass 4, count 0 2006.218.08:18:58.54#ibcon#wrote, iclass 4, count 0 2006.218.08:18:58.54#ibcon#about to read 3, iclass 4, count 0 2006.218.08:18:58.56#ibcon#read 3, iclass 4, count 0 2006.218.08:18:58.56#ibcon#about to read 4, iclass 4, count 0 2006.218.08:18:58.56#ibcon#read 4, iclass 4, count 0 2006.218.08:18:58.56#ibcon#about to read 5, iclass 4, count 0 2006.218.08:18:58.56#ibcon#read 5, iclass 4, count 0 2006.218.08:18:58.56#ibcon#about to read 6, iclass 4, count 0 2006.218.08:18:58.56#ibcon#read 6, iclass 4, count 0 2006.218.08:18:58.56#ibcon#end of sib2, iclass 4, count 0 2006.218.08:18:58.56#ibcon#*mode == 0, iclass 4, count 0 2006.218.08:18:58.56#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.218.08:18:58.56#ibcon#[26=FRQ=03,672.99\r\n] 2006.218.08:18:58.56#ibcon#*before write, iclass 4, count 0 2006.218.08:18:58.56#ibcon#enter sib2, iclass 4, count 0 2006.218.08:18:58.56#ibcon#flushed, iclass 4, count 0 2006.218.08:18:58.56#ibcon#about to write, iclass 4, count 0 2006.218.08:18:58.56#ibcon#wrote, iclass 4, count 0 2006.218.08:18:58.56#ibcon#about to read 3, iclass 4, count 0 2006.218.08:18:58.61#ibcon#read 3, iclass 4, count 0 2006.218.08:18:58.61#ibcon#about to read 4, iclass 4, count 0 2006.218.08:18:58.61#ibcon#read 4, iclass 4, count 0 2006.218.08:18:58.61#ibcon#about to read 5, iclass 4, count 0 2006.218.08:18:58.61#ibcon#read 5, iclass 4, count 0 2006.218.08:18:58.61#ibcon#about to read 6, iclass 4, count 0 2006.218.08:18:58.61#ibcon#read 6, iclass 4, count 0 2006.218.08:18:58.61#ibcon#end of sib2, iclass 4, count 0 2006.218.08:18:58.61#ibcon#*after write, iclass 4, count 0 2006.218.08:18:58.61#ibcon#*before return 0, iclass 4, count 0 2006.218.08:18:58.61#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.218.08:18:58.61#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.218.08:18:58.61#ibcon#about to clear, iclass 4 cls_cnt 0 2006.218.08:18:58.61#ibcon#cleared, iclass 4 cls_cnt 0 2006.218.08:18:58.61$vc4f8/va=3,4 2006.218.08:18:58.61#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.218.08:18:58.61#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.218.08:18:58.61#ibcon#ireg 11 cls_cnt 2 2006.218.08:18:58.61#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.218.08:18:58.66#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.218.08:18:58.66#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.218.08:18:58.66#ibcon#enter wrdev, iclass 6, count 2 2006.218.08:18:58.66#ibcon#first serial, iclass 6, count 2 2006.218.08:18:58.66#ibcon#enter sib2, iclass 6, count 2 2006.218.08:18:58.66#ibcon#flushed, iclass 6, count 2 2006.218.08:18:58.66#ibcon#about to write, iclass 6, count 2 2006.218.08:18:58.66#ibcon#wrote, iclass 6, count 2 2006.218.08:18:58.66#ibcon#about to read 3, iclass 6, count 2 2006.218.08:18:58.68#ibcon#read 3, iclass 6, count 2 2006.218.08:18:58.68#ibcon#about to read 4, iclass 6, count 2 2006.218.08:18:58.68#ibcon#read 4, iclass 6, count 2 2006.218.08:18:58.68#ibcon#about to read 5, iclass 6, count 2 2006.218.08:18:58.68#ibcon#read 5, iclass 6, count 2 2006.218.08:18:58.68#ibcon#about to read 6, iclass 6, count 2 2006.218.08:18:58.68#ibcon#read 6, iclass 6, count 2 2006.218.08:18:58.68#ibcon#end of sib2, iclass 6, count 2 2006.218.08:18:58.68#ibcon#*mode == 0, iclass 6, count 2 2006.218.08:18:58.68#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.218.08:18:58.68#ibcon#[25=AT03-04\r\n] 2006.218.08:18:58.68#ibcon#*before write, iclass 6, count 2 2006.218.08:18:58.68#ibcon#enter sib2, iclass 6, count 2 2006.218.08:18:58.68#ibcon#flushed, iclass 6, count 2 2006.218.08:18:58.68#ibcon#about to write, iclass 6, count 2 2006.218.08:18:58.68#ibcon#wrote, iclass 6, count 2 2006.218.08:18:58.68#ibcon#about to read 3, iclass 6, count 2 2006.218.08:18:58.71#ibcon#read 3, iclass 6, count 2 2006.218.08:18:58.71#ibcon#about to read 4, iclass 6, count 2 2006.218.08:18:58.71#ibcon#read 4, iclass 6, count 2 2006.218.08:18:58.71#ibcon#about to read 5, iclass 6, count 2 2006.218.08:18:58.71#ibcon#read 5, iclass 6, count 2 2006.218.08:18:58.71#ibcon#about to read 6, iclass 6, count 2 2006.218.08:18:58.71#ibcon#read 6, iclass 6, count 2 2006.218.08:18:58.71#ibcon#end of sib2, iclass 6, count 2 2006.218.08:18:58.71#ibcon#*after write, iclass 6, count 2 2006.218.08:18:58.71#ibcon#*before return 0, iclass 6, count 2 2006.218.08:18:58.71#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.218.08:18:58.71#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.218.08:18:58.71#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.218.08:18:58.71#ibcon#ireg 7 cls_cnt 0 2006.218.08:18:58.71#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.218.08:18:58.83#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.218.08:18:58.83#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.218.08:18:58.83#ibcon#enter wrdev, iclass 6, count 0 2006.218.08:18:58.83#ibcon#first serial, iclass 6, count 0 2006.218.08:18:58.83#ibcon#enter sib2, iclass 6, count 0 2006.218.08:18:58.83#ibcon#flushed, iclass 6, count 0 2006.218.08:18:58.83#ibcon#about to write, iclass 6, count 0 2006.218.08:18:58.83#ibcon#wrote, iclass 6, count 0 2006.218.08:18:58.83#ibcon#about to read 3, iclass 6, count 0 2006.218.08:18:58.85#ibcon#read 3, iclass 6, count 0 2006.218.08:18:58.85#ibcon#about to read 4, iclass 6, count 0 2006.218.08:18:58.85#ibcon#read 4, iclass 6, count 0 2006.218.08:18:58.85#ibcon#about to read 5, iclass 6, count 0 2006.218.08:18:58.85#ibcon#read 5, iclass 6, count 0 2006.218.08:18:58.85#ibcon#about to read 6, iclass 6, count 0 2006.218.08:18:58.85#ibcon#read 6, iclass 6, count 0 2006.218.08:18:58.85#ibcon#end of sib2, iclass 6, count 0 2006.218.08:18:58.85#ibcon#*mode == 0, iclass 6, count 0 2006.218.08:18:58.85#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.218.08:18:58.85#ibcon#[25=USB\r\n] 2006.218.08:18:58.85#ibcon#*before write, iclass 6, count 0 2006.218.08:18:58.85#ibcon#enter sib2, iclass 6, count 0 2006.218.08:18:58.85#ibcon#flushed, iclass 6, count 0 2006.218.08:18:58.85#ibcon#about to write, iclass 6, count 0 2006.218.08:18:58.85#ibcon#wrote, iclass 6, count 0 2006.218.08:18:58.85#ibcon#about to read 3, iclass 6, count 0 2006.218.08:18:58.88#ibcon#read 3, iclass 6, count 0 2006.218.08:18:58.88#ibcon#about to read 4, iclass 6, count 0 2006.218.08:18:58.88#ibcon#read 4, iclass 6, count 0 2006.218.08:18:58.88#ibcon#about to read 5, iclass 6, count 0 2006.218.08:18:58.88#ibcon#read 5, iclass 6, count 0 2006.218.08:18:58.88#ibcon#about to read 6, iclass 6, count 0 2006.218.08:18:58.88#ibcon#read 6, iclass 6, count 0 2006.218.08:18:58.88#ibcon#end of sib2, iclass 6, count 0 2006.218.08:18:58.88#ibcon#*after write, iclass 6, count 0 2006.218.08:18:58.88#ibcon#*before return 0, iclass 6, count 0 2006.218.08:18:58.88#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.218.08:18:58.88#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.218.08:18:58.88#ibcon#about to clear, iclass 6 cls_cnt 0 2006.218.08:18:58.88#ibcon#cleared, iclass 6 cls_cnt 0 2006.218.08:18:58.88$vc4f8/valo=4,832.99 2006.218.08:18:58.88#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.218.08:18:58.88#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.218.08:18:58.88#ibcon#ireg 17 cls_cnt 0 2006.218.08:18:58.88#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.218.08:18:58.88#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.218.08:18:58.88#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.218.08:18:58.88#ibcon#enter wrdev, iclass 10, count 0 2006.218.08:18:58.88#ibcon#first serial, iclass 10, count 0 2006.218.08:18:58.88#ibcon#enter sib2, iclass 10, count 0 2006.218.08:18:58.88#ibcon#flushed, iclass 10, count 0 2006.218.08:18:58.88#ibcon#about to write, iclass 10, count 0 2006.218.08:18:58.88#ibcon#wrote, iclass 10, count 0 2006.218.08:18:58.88#ibcon#about to read 3, iclass 10, count 0 2006.218.08:18:58.90#ibcon#read 3, iclass 10, count 0 2006.218.08:18:58.90#ibcon#about to read 4, iclass 10, count 0 2006.218.08:18:58.90#ibcon#read 4, iclass 10, count 0 2006.218.08:18:58.90#ibcon#about to read 5, iclass 10, count 0 2006.218.08:18:58.90#ibcon#read 5, iclass 10, count 0 2006.218.08:18:58.90#ibcon#about to read 6, iclass 10, count 0 2006.218.08:18:58.90#ibcon#read 6, iclass 10, count 0 2006.218.08:18:58.90#ibcon#end of sib2, iclass 10, count 0 2006.218.08:18:58.90#ibcon#*mode == 0, iclass 10, count 0 2006.218.08:18:58.90#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.218.08:18:58.90#ibcon#[26=FRQ=04,832.99\r\n] 2006.218.08:18:58.90#ibcon#*before write, iclass 10, count 0 2006.218.08:18:58.90#ibcon#enter sib2, iclass 10, count 0 2006.218.08:18:58.90#ibcon#flushed, iclass 10, count 0 2006.218.08:18:58.90#ibcon#about to write, iclass 10, count 0 2006.218.08:18:58.90#ibcon#wrote, iclass 10, count 0 2006.218.08:18:58.90#ibcon#about to read 3, iclass 10, count 0 2006.218.08:18:58.94#ibcon#read 3, iclass 10, count 0 2006.218.08:18:58.94#ibcon#about to read 4, iclass 10, count 0 2006.218.08:18:58.94#ibcon#read 4, iclass 10, count 0 2006.218.08:18:58.94#ibcon#about to read 5, iclass 10, count 0 2006.218.08:18:58.94#ibcon#read 5, iclass 10, count 0 2006.218.08:18:58.94#ibcon#about to read 6, iclass 10, count 0 2006.218.08:18:58.94#ibcon#read 6, iclass 10, count 0 2006.218.08:18:58.94#ibcon#end of sib2, iclass 10, count 0 2006.218.08:18:58.94#ibcon#*after write, iclass 10, count 0 2006.218.08:18:58.94#ibcon#*before return 0, iclass 10, count 0 2006.218.08:18:58.94#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.218.08:18:58.94#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.218.08:18:58.94#ibcon#about to clear, iclass 10 cls_cnt 0 2006.218.08:18:58.94#ibcon#cleared, iclass 10 cls_cnt 0 2006.218.08:18:58.94$vc4f8/va=4,4 2006.218.08:18:58.94#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.218.08:18:58.94#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.218.08:18:58.94#ibcon#ireg 11 cls_cnt 2 2006.218.08:18:58.94#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.218.08:18:59.00#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.218.08:18:59.00#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.218.08:18:59.00#ibcon#enter wrdev, iclass 12, count 2 2006.218.08:18:59.00#ibcon#first serial, iclass 12, count 2 2006.218.08:18:59.00#ibcon#enter sib2, iclass 12, count 2 2006.218.08:18:59.00#ibcon#flushed, iclass 12, count 2 2006.218.08:18:59.00#ibcon#about to write, iclass 12, count 2 2006.218.08:18:59.00#ibcon#wrote, iclass 12, count 2 2006.218.08:18:59.00#ibcon#about to read 3, iclass 12, count 2 2006.218.08:18:59.02#ibcon#read 3, iclass 12, count 2 2006.218.08:18:59.02#ibcon#about to read 4, iclass 12, count 2 2006.218.08:18:59.02#ibcon#read 4, iclass 12, count 2 2006.218.08:18:59.02#ibcon#about to read 5, iclass 12, count 2 2006.218.08:18:59.02#ibcon#read 5, iclass 12, count 2 2006.218.08:18:59.02#ibcon#about to read 6, iclass 12, count 2 2006.218.08:18:59.02#ibcon#read 6, iclass 12, count 2 2006.218.08:18:59.02#ibcon#end of sib2, iclass 12, count 2 2006.218.08:18:59.02#ibcon#*mode == 0, iclass 12, count 2 2006.218.08:18:59.02#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.218.08:18:59.02#ibcon#[25=AT04-04\r\n] 2006.218.08:18:59.02#ibcon#*before write, iclass 12, count 2 2006.218.08:18:59.02#ibcon#enter sib2, iclass 12, count 2 2006.218.08:18:59.02#ibcon#flushed, iclass 12, count 2 2006.218.08:18:59.02#ibcon#about to write, iclass 12, count 2 2006.218.08:18:59.02#ibcon#wrote, iclass 12, count 2 2006.218.08:18:59.02#ibcon#about to read 3, iclass 12, count 2 2006.218.08:18:59.05#ibcon#read 3, iclass 12, count 2 2006.218.08:18:59.05#ibcon#about to read 4, iclass 12, count 2 2006.218.08:18:59.05#ibcon#read 4, iclass 12, count 2 2006.218.08:18:59.05#ibcon#about to read 5, iclass 12, count 2 2006.218.08:18:59.05#ibcon#read 5, iclass 12, count 2 2006.218.08:18:59.05#ibcon#about to read 6, iclass 12, count 2 2006.218.08:18:59.05#ibcon#read 6, iclass 12, count 2 2006.218.08:18:59.05#ibcon#end of sib2, iclass 12, count 2 2006.218.08:18:59.05#ibcon#*after write, iclass 12, count 2 2006.218.08:18:59.05#ibcon#*before return 0, iclass 12, count 2 2006.218.08:18:59.05#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.218.08:18:59.05#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.218.08:18:59.05#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.218.08:18:59.05#ibcon#ireg 7 cls_cnt 0 2006.218.08:18:59.05#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.218.08:18:59.17#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.218.08:18:59.17#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.218.08:18:59.17#ibcon#enter wrdev, iclass 12, count 0 2006.218.08:18:59.17#ibcon#first serial, iclass 12, count 0 2006.218.08:18:59.17#ibcon#enter sib2, iclass 12, count 0 2006.218.08:18:59.17#ibcon#flushed, iclass 12, count 0 2006.218.08:18:59.17#ibcon#about to write, iclass 12, count 0 2006.218.08:18:59.17#ibcon#wrote, iclass 12, count 0 2006.218.08:18:59.17#ibcon#about to read 3, iclass 12, count 0 2006.218.08:18:59.19#ibcon#read 3, iclass 12, count 0 2006.218.08:18:59.19#ibcon#about to read 4, iclass 12, count 0 2006.218.08:18:59.19#ibcon#read 4, iclass 12, count 0 2006.218.08:18:59.19#ibcon#about to read 5, iclass 12, count 0 2006.218.08:18:59.19#ibcon#read 5, iclass 12, count 0 2006.218.08:18:59.19#ibcon#about to read 6, iclass 12, count 0 2006.218.08:18:59.19#ibcon#read 6, iclass 12, count 0 2006.218.08:18:59.19#ibcon#end of sib2, iclass 12, count 0 2006.218.08:18:59.19#ibcon#*mode == 0, iclass 12, count 0 2006.218.08:18:59.19#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.218.08:18:59.19#ibcon#[25=USB\r\n] 2006.218.08:18:59.19#ibcon#*before write, iclass 12, count 0 2006.218.08:18:59.19#ibcon#enter sib2, iclass 12, count 0 2006.218.08:18:59.19#ibcon#flushed, iclass 12, count 0 2006.218.08:18:59.19#ibcon#about to write, iclass 12, count 0 2006.218.08:18:59.19#ibcon#wrote, iclass 12, count 0 2006.218.08:18:59.19#ibcon#about to read 3, iclass 12, count 0 2006.218.08:18:59.22#ibcon#read 3, iclass 12, count 0 2006.218.08:18:59.22#ibcon#about to read 4, iclass 12, count 0 2006.218.08:18:59.22#ibcon#read 4, iclass 12, count 0 2006.218.08:18:59.22#ibcon#about to read 5, iclass 12, count 0 2006.218.08:18:59.22#ibcon#read 5, iclass 12, count 0 2006.218.08:18:59.22#ibcon#about to read 6, iclass 12, count 0 2006.218.08:18:59.22#ibcon#read 6, iclass 12, count 0 2006.218.08:18:59.22#ibcon#end of sib2, iclass 12, count 0 2006.218.08:18:59.22#ibcon#*after write, iclass 12, count 0 2006.218.08:18:59.22#ibcon#*before return 0, iclass 12, count 0 2006.218.08:18:59.22#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.218.08:18:59.22#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.218.08:18:59.22#ibcon#about to clear, iclass 12 cls_cnt 0 2006.218.08:18:59.22#ibcon#cleared, iclass 12 cls_cnt 0 2006.218.08:18:59.22$vc4f8/valo=5,652.99 2006.218.08:18:59.22#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.218.08:18:59.22#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.218.08:18:59.22#ibcon#ireg 17 cls_cnt 0 2006.218.08:18:59.22#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.218.08:18:59.22#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.218.08:18:59.22#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.218.08:18:59.22#ibcon#enter wrdev, iclass 14, count 0 2006.218.08:18:59.22#ibcon#first serial, iclass 14, count 0 2006.218.08:18:59.22#ibcon#enter sib2, iclass 14, count 0 2006.218.08:18:59.22#ibcon#flushed, iclass 14, count 0 2006.218.08:18:59.22#ibcon#about to write, iclass 14, count 0 2006.218.08:18:59.22#ibcon#wrote, iclass 14, count 0 2006.218.08:18:59.22#ibcon#about to read 3, iclass 14, count 0 2006.218.08:18:59.24#ibcon#read 3, iclass 14, count 0 2006.218.08:18:59.24#ibcon#about to read 4, iclass 14, count 0 2006.218.08:18:59.24#ibcon#read 4, iclass 14, count 0 2006.218.08:18:59.24#ibcon#about to read 5, iclass 14, count 0 2006.218.08:18:59.24#ibcon#read 5, iclass 14, count 0 2006.218.08:18:59.24#ibcon#about to read 6, iclass 14, count 0 2006.218.08:18:59.24#ibcon#read 6, iclass 14, count 0 2006.218.08:18:59.24#ibcon#end of sib2, iclass 14, count 0 2006.218.08:18:59.24#ibcon#*mode == 0, iclass 14, count 0 2006.218.08:18:59.24#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.218.08:18:59.24#ibcon#[26=FRQ=05,652.99\r\n] 2006.218.08:18:59.24#ibcon#*before write, iclass 14, count 0 2006.218.08:18:59.24#ibcon#enter sib2, iclass 14, count 0 2006.218.08:18:59.24#ibcon#flushed, iclass 14, count 0 2006.218.08:18:59.24#ibcon#about to write, iclass 14, count 0 2006.218.08:18:59.24#ibcon#wrote, iclass 14, count 0 2006.218.08:18:59.24#ibcon#about to read 3, iclass 14, count 0 2006.218.08:18:59.28#ibcon#read 3, iclass 14, count 0 2006.218.08:18:59.28#ibcon#about to read 4, iclass 14, count 0 2006.218.08:18:59.28#ibcon#read 4, iclass 14, count 0 2006.218.08:18:59.28#ibcon#about to read 5, iclass 14, count 0 2006.218.08:18:59.28#ibcon#read 5, iclass 14, count 0 2006.218.08:18:59.28#ibcon#about to read 6, iclass 14, count 0 2006.218.08:18:59.28#ibcon#read 6, iclass 14, count 0 2006.218.08:18:59.28#ibcon#end of sib2, iclass 14, count 0 2006.218.08:18:59.28#ibcon#*after write, iclass 14, count 0 2006.218.08:18:59.28#ibcon#*before return 0, iclass 14, count 0 2006.218.08:18:59.28#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.218.08:18:59.28#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.218.08:18:59.28#ibcon#about to clear, iclass 14 cls_cnt 0 2006.218.08:18:59.28#ibcon#cleared, iclass 14 cls_cnt 0 2006.218.08:18:59.28$vc4f8/va=5,7 2006.218.08:18:59.28#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.218.08:18:59.28#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.218.08:18:59.28#ibcon#ireg 11 cls_cnt 2 2006.218.08:18:59.28#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.218.08:18:59.34#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.218.08:18:59.34#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.218.08:18:59.34#ibcon#enter wrdev, iclass 16, count 2 2006.218.08:18:59.34#ibcon#first serial, iclass 16, count 2 2006.218.08:18:59.34#ibcon#enter sib2, iclass 16, count 2 2006.218.08:18:59.34#ibcon#flushed, iclass 16, count 2 2006.218.08:18:59.34#ibcon#about to write, iclass 16, count 2 2006.218.08:18:59.34#ibcon#wrote, iclass 16, count 2 2006.218.08:18:59.34#ibcon#about to read 3, iclass 16, count 2 2006.218.08:18:59.36#ibcon#read 3, iclass 16, count 2 2006.218.08:18:59.36#ibcon#about to read 4, iclass 16, count 2 2006.218.08:18:59.36#ibcon#read 4, iclass 16, count 2 2006.218.08:18:59.36#ibcon#about to read 5, iclass 16, count 2 2006.218.08:18:59.36#ibcon#read 5, iclass 16, count 2 2006.218.08:18:59.36#ibcon#about to read 6, iclass 16, count 2 2006.218.08:18:59.36#ibcon#read 6, iclass 16, count 2 2006.218.08:18:59.36#ibcon#end of sib2, iclass 16, count 2 2006.218.08:18:59.36#ibcon#*mode == 0, iclass 16, count 2 2006.218.08:18:59.36#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.218.08:18:59.36#ibcon#[25=AT05-07\r\n] 2006.218.08:18:59.36#ibcon#*before write, iclass 16, count 2 2006.218.08:18:59.36#ibcon#enter sib2, iclass 16, count 2 2006.218.08:18:59.36#ibcon#flushed, iclass 16, count 2 2006.218.08:18:59.36#ibcon#about to write, iclass 16, count 2 2006.218.08:18:59.36#ibcon#wrote, iclass 16, count 2 2006.218.08:18:59.36#ibcon#about to read 3, iclass 16, count 2 2006.218.08:18:59.39#ibcon#read 3, iclass 16, count 2 2006.218.08:18:59.39#ibcon#about to read 4, iclass 16, count 2 2006.218.08:18:59.39#ibcon#read 4, iclass 16, count 2 2006.218.08:18:59.39#ibcon#about to read 5, iclass 16, count 2 2006.218.08:18:59.39#ibcon#read 5, iclass 16, count 2 2006.218.08:18:59.39#ibcon#about to read 6, iclass 16, count 2 2006.218.08:18:59.39#ibcon#read 6, iclass 16, count 2 2006.218.08:18:59.39#ibcon#end of sib2, iclass 16, count 2 2006.218.08:18:59.39#ibcon#*after write, iclass 16, count 2 2006.218.08:18:59.39#ibcon#*before return 0, iclass 16, count 2 2006.218.08:18:59.39#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.218.08:18:59.39#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.218.08:18:59.39#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.218.08:18:59.39#ibcon#ireg 7 cls_cnt 0 2006.218.08:18:59.39#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.218.08:18:59.51#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.218.08:18:59.51#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.218.08:18:59.51#ibcon#enter wrdev, iclass 16, count 0 2006.218.08:18:59.51#ibcon#first serial, iclass 16, count 0 2006.218.08:18:59.51#ibcon#enter sib2, iclass 16, count 0 2006.218.08:18:59.51#ibcon#flushed, iclass 16, count 0 2006.218.08:18:59.51#ibcon#about to write, iclass 16, count 0 2006.218.08:18:59.51#ibcon#wrote, iclass 16, count 0 2006.218.08:18:59.51#ibcon#about to read 3, iclass 16, count 0 2006.218.08:18:59.53#ibcon#read 3, iclass 16, count 0 2006.218.08:18:59.53#ibcon#about to read 4, iclass 16, count 0 2006.218.08:18:59.53#ibcon#read 4, iclass 16, count 0 2006.218.08:18:59.53#ibcon#about to read 5, iclass 16, count 0 2006.218.08:18:59.53#ibcon#read 5, iclass 16, count 0 2006.218.08:18:59.53#ibcon#about to read 6, iclass 16, count 0 2006.218.08:18:59.53#ibcon#read 6, iclass 16, count 0 2006.218.08:18:59.53#ibcon#end of sib2, iclass 16, count 0 2006.218.08:18:59.53#ibcon#*mode == 0, iclass 16, count 0 2006.218.08:18:59.53#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.218.08:18:59.53#ibcon#[25=USB\r\n] 2006.218.08:18:59.53#ibcon#*before write, iclass 16, count 0 2006.218.08:18:59.53#ibcon#enter sib2, iclass 16, count 0 2006.218.08:18:59.53#ibcon#flushed, iclass 16, count 0 2006.218.08:18:59.53#ibcon#about to write, iclass 16, count 0 2006.218.08:18:59.53#ibcon#wrote, iclass 16, count 0 2006.218.08:18:59.53#ibcon#about to read 3, iclass 16, count 0 2006.218.08:18:59.56#ibcon#read 3, iclass 16, count 0 2006.218.08:18:59.56#ibcon#about to read 4, iclass 16, count 0 2006.218.08:18:59.56#ibcon#read 4, iclass 16, count 0 2006.218.08:18:59.56#ibcon#about to read 5, iclass 16, count 0 2006.218.08:18:59.56#ibcon#read 5, iclass 16, count 0 2006.218.08:18:59.56#ibcon#about to read 6, iclass 16, count 0 2006.218.08:18:59.56#ibcon#read 6, iclass 16, count 0 2006.218.08:18:59.56#ibcon#end of sib2, iclass 16, count 0 2006.218.08:18:59.56#ibcon#*after write, iclass 16, count 0 2006.218.08:18:59.56#ibcon#*before return 0, iclass 16, count 0 2006.218.08:18:59.56#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.218.08:18:59.56#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.218.08:18:59.56#ibcon#about to clear, iclass 16 cls_cnt 0 2006.218.08:18:59.56#ibcon#cleared, iclass 16 cls_cnt 0 2006.218.08:18:59.56$vc4f8/valo=6,772.99 2006.218.08:18:59.56#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.218.08:18:59.56#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.218.08:18:59.56#ibcon#ireg 17 cls_cnt 0 2006.218.08:18:59.56#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.218.08:18:59.56#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.218.08:18:59.56#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.218.08:18:59.56#ibcon#enter wrdev, iclass 18, count 0 2006.218.08:18:59.56#ibcon#first serial, iclass 18, count 0 2006.218.08:18:59.56#ibcon#enter sib2, iclass 18, count 0 2006.218.08:18:59.56#ibcon#flushed, iclass 18, count 0 2006.218.08:18:59.56#ibcon#about to write, iclass 18, count 0 2006.218.08:18:59.56#ibcon#wrote, iclass 18, count 0 2006.218.08:18:59.56#ibcon#about to read 3, iclass 18, count 0 2006.218.08:18:59.58#ibcon#read 3, iclass 18, count 0 2006.218.08:18:59.58#ibcon#about to read 4, iclass 18, count 0 2006.218.08:18:59.58#ibcon#read 4, iclass 18, count 0 2006.218.08:18:59.58#ibcon#about to read 5, iclass 18, count 0 2006.218.08:18:59.58#ibcon#read 5, iclass 18, count 0 2006.218.08:18:59.58#ibcon#about to read 6, iclass 18, count 0 2006.218.08:18:59.58#ibcon#read 6, iclass 18, count 0 2006.218.08:18:59.58#ibcon#end of sib2, iclass 18, count 0 2006.218.08:18:59.58#ibcon#*mode == 0, iclass 18, count 0 2006.218.08:18:59.58#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.218.08:18:59.58#ibcon#[26=FRQ=06,772.99\r\n] 2006.218.08:18:59.58#ibcon#*before write, iclass 18, count 0 2006.218.08:18:59.58#ibcon#enter sib2, iclass 18, count 0 2006.218.08:18:59.58#ibcon#flushed, iclass 18, count 0 2006.218.08:18:59.58#ibcon#about to write, iclass 18, count 0 2006.218.08:18:59.58#ibcon#wrote, iclass 18, count 0 2006.218.08:18:59.58#ibcon#about to read 3, iclass 18, count 0 2006.218.08:18:59.63#ibcon#read 3, iclass 18, count 0 2006.218.08:18:59.63#ibcon#about to read 4, iclass 18, count 0 2006.218.08:18:59.63#ibcon#read 4, iclass 18, count 0 2006.218.08:18:59.63#ibcon#about to read 5, iclass 18, count 0 2006.218.08:18:59.63#ibcon#read 5, iclass 18, count 0 2006.218.08:18:59.63#ibcon#about to read 6, iclass 18, count 0 2006.218.08:18:59.63#ibcon#read 6, iclass 18, count 0 2006.218.08:18:59.63#ibcon#end of sib2, iclass 18, count 0 2006.218.08:18:59.63#ibcon#*after write, iclass 18, count 0 2006.218.08:18:59.63#ibcon#*before return 0, iclass 18, count 0 2006.218.08:18:59.63#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.218.08:18:59.63#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.218.08:18:59.63#ibcon#about to clear, iclass 18 cls_cnt 0 2006.218.08:18:59.63#ibcon#cleared, iclass 18 cls_cnt 0 2006.218.08:18:59.63$vc4f8/va=6,6 2006.218.08:18:59.63#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.218.08:18:59.63#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.218.08:18:59.63#ibcon#ireg 11 cls_cnt 2 2006.218.08:18:59.63#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.218.08:18:59.68#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.218.08:18:59.68#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.218.08:18:59.68#ibcon#enter wrdev, iclass 20, count 2 2006.218.08:18:59.68#ibcon#first serial, iclass 20, count 2 2006.218.08:18:59.68#ibcon#enter sib2, iclass 20, count 2 2006.218.08:18:59.68#ibcon#flushed, iclass 20, count 2 2006.218.08:18:59.68#ibcon#about to write, iclass 20, count 2 2006.218.08:18:59.68#ibcon#wrote, iclass 20, count 2 2006.218.08:18:59.68#ibcon#about to read 3, iclass 20, count 2 2006.218.08:18:59.70#ibcon#read 3, iclass 20, count 2 2006.218.08:18:59.70#ibcon#about to read 4, iclass 20, count 2 2006.218.08:18:59.70#ibcon#read 4, iclass 20, count 2 2006.218.08:18:59.70#ibcon#about to read 5, iclass 20, count 2 2006.218.08:18:59.70#ibcon#read 5, iclass 20, count 2 2006.218.08:18:59.70#ibcon#about to read 6, iclass 20, count 2 2006.218.08:18:59.70#ibcon#read 6, iclass 20, count 2 2006.218.08:18:59.70#ibcon#end of sib2, iclass 20, count 2 2006.218.08:18:59.70#ibcon#*mode == 0, iclass 20, count 2 2006.218.08:18:59.70#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.218.08:18:59.70#ibcon#[25=AT06-06\r\n] 2006.218.08:18:59.70#ibcon#*before write, iclass 20, count 2 2006.218.08:18:59.70#ibcon#enter sib2, iclass 20, count 2 2006.218.08:18:59.70#ibcon#flushed, iclass 20, count 2 2006.218.08:18:59.70#ibcon#about to write, iclass 20, count 2 2006.218.08:18:59.70#ibcon#wrote, iclass 20, count 2 2006.218.08:18:59.70#ibcon#about to read 3, iclass 20, count 2 2006.218.08:18:59.73#ibcon#read 3, iclass 20, count 2 2006.218.08:18:59.73#ibcon#about to read 4, iclass 20, count 2 2006.218.08:18:59.73#ibcon#read 4, iclass 20, count 2 2006.218.08:18:59.73#ibcon#about to read 5, iclass 20, count 2 2006.218.08:18:59.73#ibcon#read 5, iclass 20, count 2 2006.218.08:18:59.73#ibcon#about to read 6, iclass 20, count 2 2006.218.08:18:59.73#ibcon#read 6, iclass 20, count 2 2006.218.08:18:59.73#ibcon#end of sib2, iclass 20, count 2 2006.218.08:18:59.73#ibcon#*after write, iclass 20, count 2 2006.218.08:18:59.73#ibcon#*before return 0, iclass 20, count 2 2006.218.08:18:59.73#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.218.08:18:59.73#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.218.08:18:59.73#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.218.08:18:59.73#ibcon#ireg 7 cls_cnt 0 2006.218.08:18:59.73#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.218.08:18:59.85#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.218.08:18:59.85#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.218.08:18:59.85#ibcon#enter wrdev, iclass 20, count 0 2006.218.08:18:59.85#ibcon#first serial, iclass 20, count 0 2006.218.08:18:59.85#ibcon#enter sib2, iclass 20, count 0 2006.218.08:18:59.85#ibcon#flushed, iclass 20, count 0 2006.218.08:18:59.85#ibcon#about to write, iclass 20, count 0 2006.218.08:18:59.85#ibcon#wrote, iclass 20, count 0 2006.218.08:18:59.85#ibcon#about to read 3, iclass 20, count 0 2006.218.08:18:59.87#ibcon#read 3, iclass 20, count 0 2006.218.08:18:59.87#ibcon#about to read 4, iclass 20, count 0 2006.218.08:18:59.87#ibcon#read 4, iclass 20, count 0 2006.218.08:18:59.87#ibcon#about to read 5, iclass 20, count 0 2006.218.08:18:59.87#ibcon#read 5, iclass 20, count 0 2006.218.08:18:59.87#ibcon#about to read 6, iclass 20, count 0 2006.218.08:18:59.87#ibcon#read 6, iclass 20, count 0 2006.218.08:18:59.87#ibcon#end of sib2, iclass 20, count 0 2006.218.08:18:59.87#ibcon#*mode == 0, iclass 20, count 0 2006.218.08:18:59.87#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.218.08:18:59.87#ibcon#[25=USB\r\n] 2006.218.08:18:59.87#ibcon#*before write, iclass 20, count 0 2006.218.08:18:59.87#ibcon#enter sib2, iclass 20, count 0 2006.218.08:18:59.87#ibcon#flushed, iclass 20, count 0 2006.218.08:18:59.87#ibcon#about to write, iclass 20, count 0 2006.218.08:18:59.87#ibcon#wrote, iclass 20, count 0 2006.218.08:18:59.87#ibcon#about to read 3, iclass 20, count 0 2006.218.08:18:59.90#ibcon#read 3, iclass 20, count 0 2006.218.08:18:59.90#ibcon#about to read 4, iclass 20, count 0 2006.218.08:18:59.90#ibcon#read 4, iclass 20, count 0 2006.218.08:18:59.90#ibcon#about to read 5, iclass 20, count 0 2006.218.08:18:59.90#ibcon#read 5, iclass 20, count 0 2006.218.08:18:59.90#ibcon#about to read 6, iclass 20, count 0 2006.218.08:18:59.90#ibcon#read 6, iclass 20, count 0 2006.218.08:18:59.90#ibcon#end of sib2, iclass 20, count 0 2006.218.08:18:59.90#ibcon#*after write, iclass 20, count 0 2006.218.08:18:59.90#ibcon#*before return 0, iclass 20, count 0 2006.218.08:18:59.90#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.218.08:18:59.90#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.218.08:18:59.90#ibcon#about to clear, iclass 20 cls_cnt 0 2006.218.08:18:59.90#ibcon#cleared, iclass 20 cls_cnt 0 2006.218.08:18:59.90$vc4f8/valo=7,832.99 2006.218.08:18:59.90#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.218.08:18:59.90#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.218.08:18:59.90#ibcon#ireg 17 cls_cnt 0 2006.218.08:18:59.90#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.218.08:18:59.90#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.218.08:18:59.90#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.218.08:18:59.90#ibcon#enter wrdev, iclass 22, count 0 2006.218.08:18:59.90#ibcon#first serial, iclass 22, count 0 2006.218.08:18:59.90#ibcon#enter sib2, iclass 22, count 0 2006.218.08:18:59.90#ibcon#flushed, iclass 22, count 0 2006.218.08:18:59.90#ibcon#about to write, iclass 22, count 0 2006.218.08:18:59.90#ibcon#wrote, iclass 22, count 0 2006.218.08:18:59.90#ibcon#about to read 3, iclass 22, count 0 2006.218.08:18:59.92#ibcon#read 3, iclass 22, count 0 2006.218.08:18:59.92#ibcon#about to read 4, iclass 22, count 0 2006.218.08:18:59.92#ibcon#read 4, iclass 22, count 0 2006.218.08:18:59.92#ibcon#about to read 5, iclass 22, count 0 2006.218.08:18:59.92#ibcon#read 5, iclass 22, count 0 2006.218.08:18:59.92#ibcon#about to read 6, iclass 22, count 0 2006.218.08:18:59.92#ibcon#read 6, iclass 22, count 0 2006.218.08:18:59.92#ibcon#end of sib2, iclass 22, count 0 2006.218.08:18:59.92#ibcon#*mode == 0, iclass 22, count 0 2006.218.08:18:59.92#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.218.08:18:59.92#ibcon#[26=FRQ=07,832.99\r\n] 2006.218.08:18:59.92#ibcon#*before write, iclass 22, count 0 2006.218.08:18:59.92#ibcon#enter sib2, iclass 22, count 0 2006.218.08:18:59.92#ibcon#flushed, iclass 22, count 0 2006.218.08:18:59.92#ibcon#about to write, iclass 22, count 0 2006.218.08:18:59.92#ibcon#wrote, iclass 22, count 0 2006.218.08:18:59.92#ibcon#about to read 3, iclass 22, count 0 2006.218.08:18:59.96#ibcon#read 3, iclass 22, count 0 2006.218.08:18:59.96#ibcon#about to read 4, iclass 22, count 0 2006.218.08:18:59.96#ibcon#read 4, iclass 22, count 0 2006.218.08:18:59.96#ibcon#about to read 5, iclass 22, count 0 2006.218.08:18:59.96#ibcon#read 5, iclass 22, count 0 2006.218.08:18:59.96#ibcon#about to read 6, iclass 22, count 0 2006.218.08:18:59.96#ibcon#read 6, iclass 22, count 0 2006.218.08:18:59.96#ibcon#end of sib2, iclass 22, count 0 2006.218.08:18:59.96#ibcon#*after write, iclass 22, count 0 2006.218.08:18:59.96#ibcon#*before return 0, iclass 22, count 0 2006.218.08:18:59.96#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.218.08:18:59.96#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.218.08:18:59.96#ibcon#about to clear, iclass 22 cls_cnt 0 2006.218.08:18:59.96#ibcon#cleared, iclass 22 cls_cnt 0 2006.218.08:18:59.96$vc4f8/va=7,6 2006.218.08:18:59.96#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.218.08:18:59.96#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.218.08:18:59.96#ibcon#ireg 11 cls_cnt 2 2006.218.08:18:59.96#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.218.08:19:00.02#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.218.08:19:00.02#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.218.08:19:00.02#ibcon#enter wrdev, iclass 24, count 2 2006.218.08:19:00.02#ibcon#first serial, iclass 24, count 2 2006.218.08:19:00.02#ibcon#enter sib2, iclass 24, count 2 2006.218.08:19:00.02#ibcon#flushed, iclass 24, count 2 2006.218.08:19:00.02#ibcon#about to write, iclass 24, count 2 2006.218.08:19:00.02#ibcon#wrote, iclass 24, count 2 2006.218.08:19:00.02#ibcon#about to read 3, iclass 24, count 2 2006.218.08:19:00.04#ibcon#read 3, iclass 24, count 2 2006.218.08:19:00.04#ibcon#about to read 4, iclass 24, count 2 2006.218.08:19:00.04#ibcon#read 4, iclass 24, count 2 2006.218.08:19:00.04#ibcon#about to read 5, iclass 24, count 2 2006.218.08:19:00.04#ibcon#read 5, iclass 24, count 2 2006.218.08:19:00.04#ibcon#about to read 6, iclass 24, count 2 2006.218.08:19:00.04#ibcon#read 6, iclass 24, count 2 2006.218.08:19:00.04#ibcon#end of sib2, iclass 24, count 2 2006.218.08:19:00.04#ibcon#*mode == 0, iclass 24, count 2 2006.218.08:19:00.04#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.218.08:19:00.04#ibcon#[25=AT07-06\r\n] 2006.218.08:19:00.04#ibcon#*before write, iclass 24, count 2 2006.218.08:19:00.04#ibcon#enter sib2, iclass 24, count 2 2006.218.08:19:00.04#ibcon#flushed, iclass 24, count 2 2006.218.08:19:00.04#ibcon#about to write, iclass 24, count 2 2006.218.08:19:00.04#ibcon#wrote, iclass 24, count 2 2006.218.08:19:00.04#ibcon#about to read 3, iclass 24, count 2 2006.218.08:19:00.07#ibcon#read 3, iclass 24, count 2 2006.218.08:19:00.07#ibcon#about to read 4, iclass 24, count 2 2006.218.08:19:00.07#ibcon#read 4, iclass 24, count 2 2006.218.08:19:00.07#ibcon#about to read 5, iclass 24, count 2 2006.218.08:19:00.07#ibcon#read 5, iclass 24, count 2 2006.218.08:19:00.07#ibcon#about to read 6, iclass 24, count 2 2006.218.08:19:00.07#ibcon#read 6, iclass 24, count 2 2006.218.08:19:00.07#ibcon#end of sib2, iclass 24, count 2 2006.218.08:19:00.07#ibcon#*after write, iclass 24, count 2 2006.218.08:19:00.07#ibcon#*before return 0, iclass 24, count 2 2006.218.08:19:00.07#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.218.08:19:00.07#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.218.08:19:00.07#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.218.08:19:00.07#ibcon#ireg 7 cls_cnt 0 2006.218.08:19:00.07#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.218.08:19:00.19#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.218.08:19:00.19#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.218.08:19:00.19#ibcon#enter wrdev, iclass 24, count 0 2006.218.08:19:00.19#ibcon#first serial, iclass 24, count 0 2006.218.08:19:00.19#ibcon#enter sib2, iclass 24, count 0 2006.218.08:19:00.19#ibcon#flushed, iclass 24, count 0 2006.218.08:19:00.19#ibcon#about to write, iclass 24, count 0 2006.218.08:19:00.19#ibcon#wrote, iclass 24, count 0 2006.218.08:19:00.19#ibcon#about to read 3, iclass 24, count 0 2006.218.08:19:00.21#ibcon#read 3, iclass 24, count 0 2006.218.08:19:00.21#ibcon#about to read 4, iclass 24, count 0 2006.218.08:19:00.21#ibcon#read 4, iclass 24, count 0 2006.218.08:19:00.21#ibcon#about to read 5, iclass 24, count 0 2006.218.08:19:00.21#ibcon#read 5, iclass 24, count 0 2006.218.08:19:00.21#ibcon#about to read 6, iclass 24, count 0 2006.218.08:19:00.21#ibcon#read 6, iclass 24, count 0 2006.218.08:19:00.21#ibcon#end of sib2, iclass 24, count 0 2006.218.08:19:00.21#ibcon#*mode == 0, iclass 24, count 0 2006.218.08:19:00.21#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.218.08:19:00.21#ibcon#[25=USB\r\n] 2006.218.08:19:00.21#ibcon#*before write, iclass 24, count 0 2006.218.08:19:00.21#ibcon#enter sib2, iclass 24, count 0 2006.218.08:19:00.21#ibcon#flushed, iclass 24, count 0 2006.218.08:19:00.21#ibcon#about to write, iclass 24, count 0 2006.218.08:19:00.21#ibcon#wrote, iclass 24, count 0 2006.218.08:19:00.21#ibcon#about to read 3, iclass 24, count 0 2006.218.08:19:00.24#ibcon#read 3, iclass 24, count 0 2006.218.08:19:00.24#ibcon#about to read 4, iclass 24, count 0 2006.218.08:19:00.24#ibcon#read 4, iclass 24, count 0 2006.218.08:19:00.24#ibcon#about to read 5, iclass 24, count 0 2006.218.08:19:00.24#ibcon#read 5, iclass 24, count 0 2006.218.08:19:00.24#ibcon#about to read 6, iclass 24, count 0 2006.218.08:19:00.24#ibcon#read 6, iclass 24, count 0 2006.218.08:19:00.24#ibcon#end of sib2, iclass 24, count 0 2006.218.08:19:00.24#ibcon#*after write, iclass 24, count 0 2006.218.08:19:00.24#ibcon#*before return 0, iclass 24, count 0 2006.218.08:19:00.24#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.218.08:19:00.24#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.218.08:19:00.24#ibcon#about to clear, iclass 24 cls_cnt 0 2006.218.08:19:00.24#ibcon#cleared, iclass 24 cls_cnt 0 2006.218.08:19:00.24$vc4f8/valo=8,852.99 2006.218.08:19:00.24#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.218.08:19:00.24#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.218.08:19:00.24#ibcon#ireg 17 cls_cnt 0 2006.218.08:19:00.24#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.218.08:19:00.24#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.218.08:19:00.24#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.218.08:19:00.24#ibcon#enter wrdev, iclass 26, count 0 2006.218.08:19:00.24#ibcon#first serial, iclass 26, count 0 2006.218.08:19:00.24#ibcon#enter sib2, iclass 26, count 0 2006.218.08:19:00.24#ibcon#flushed, iclass 26, count 0 2006.218.08:19:00.24#ibcon#about to write, iclass 26, count 0 2006.218.08:19:00.24#ibcon#wrote, iclass 26, count 0 2006.218.08:19:00.24#ibcon#about to read 3, iclass 26, count 0 2006.218.08:19:00.26#ibcon#read 3, iclass 26, count 0 2006.218.08:19:00.26#ibcon#about to read 4, iclass 26, count 0 2006.218.08:19:00.26#ibcon#read 4, iclass 26, count 0 2006.218.08:19:00.26#ibcon#about to read 5, iclass 26, count 0 2006.218.08:19:00.26#ibcon#read 5, iclass 26, count 0 2006.218.08:19:00.26#ibcon#about to read 6, iclass 26, count 0 2006.218.08:19:00.26#ibcon#read 6, iclass 26, count 0 2006.218.08:19:00.26#ibcon#end of sib2, iclass 26, count 0 2006.218.08:19:00.26#ibcon#*mode == 0, iclass 26, count 0 2006.218.08:19:00.26#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.218.08:19:00.26#ibcon#[26=FRQ=08,852.99\r\n] 2006.218.08:19:00.26#ibcon#*before write, iclass 26, count 0 2006.218.08:19:00.26#ibcon#enter sib2, iclass 26, count 0 2006.218.08:19:00.26#ibcon#flushed, iclass 26, count 0 2006.218.08:19:00.26#ibcon#about to write, iclass 26, count 0 2006.218.08:19:00.26#ibcon#wrote, iclass 26, count 0 2006.218.08:19:00.26#ibcon#about to read 3, iclass 26, count 0 2006.218.08:19:00.30#ibcon#read 3, iclass 26, count 0 2006.218.08:19:00.30#ibcon#about to read 4, iclass 26, count 0 2006.218.08:19:00.30#ibcon#read 4, iclass 26, count 0 2006.218.08:19:00.30#ibcon#about to read 5, iclass 26, count 0 2006.218.08:19:00.30#ibcon#read 5, iclass 26, count 0 2006.218.08:19:00.30#ibcon#about to read 6, iclass 26, count 0 2006.218.08:19:00.30#ibcon#read 6, iclass 26, count 0 2006.218.08:19:00.30#ibcon#end of sib2, iclass 26, count 0 2006.218.08:19:00.30#ibcon#*after write, iclass 26, count 0 2006.218.08:19:00.30#ibcon#*before return 0, iclass 26, count 0 2006.218.08:19:00.30#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.218.08:19:00.30#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.218.08:19:00.30#ibcon#about to clear, iclass 26 cls_cnt 0 2006.218.08:19:00.30#ibcon#cleared, iclass 26 cls_cnt 0 2006.218.08:19:00.30$vc4f8/va=8,7 2006.218.08:19:00.30#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.218.08:19:00.30#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.218.08:19:00.30#ibcon#ireg 11 cls_cnt 2 2006.218.08:19:00.30#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.218.08:19:00.36#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.218.08:19:00.36#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.218.08:19:00.36#ibcon#enter wrdev, iclass 28, count 2 2006.218.08:19:00.36#ibcon#first serial, iclass 28, count 2 2006.218.08:19:00.36#ibcon#enter sib2, iclass 28, count 2 2006.218.08:19:00.36#ibcon#flushed, iclass 28, count 2 2006.218.08:19:00.36#ibcon#about to write, iclass 28, count 2 2006.218.08:19:00.36#ibcon#wrote, iclass 28, count 2 2006.218.08:19:00.36#ibcon#about to read 3, iclass 28, count 2 2006.218.08:19:00.38#ibcon#read 3, iclass 28, count 2 2006.218.08:19:00.38#ibcon#about to read 4, iclass 28, count 2 2006.218.08:19:00.38#ibcon#read 4, iclass 28, count 2 2006.218.08:19:00.38#ibcon#about to read 5, iclass 28, count 2 2006.218.08:19:00.38#ibcon#read 5, iclass 28, count 2 2006.218.08:19:00.38#ibcon#about to read 6, iclass 28, count 2 2006.218.08:19:00.38#ibcon#read 6, iclass 28, count 2 2006.218.08:19:00.38#ibcon#end of sib2, iclass 28, count 2 2006.218.08:19:00.38#ibcon#*mode == 0, iclass 28, count 2 2006.218.08:19:00.38#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.218.08:19:00.38#ibcon#[25=AT08-07\r\n] 2006.218.08:19:00.38#ibcon#*before write, iclass 28, count 2 2006.218.08:19:00.38#ibcon#enter sib2, iclass 28, count 2 2006.218.08:19:00.38#ibcon#flushed, iclass 28, count 2 2006.218.08:19:00.38#ibcon#about to write, iclass 28, count 2 2006.218.08:19:00.38#ibcon#wrote, iclass 28, count 2 2006.218.08:19:00.38#ibcon#about to read 3, iclass 28, count 2 2006.218.08:19:00.42#ibcon#read 3, iclass 28, count 2 2006.218.08:19:00.42#ibcon#about to read 4, iclass 28, count 2 2006.218.08:19:00.42#ibcon#read 4, iclass 28, count 2 2006.218.08:19:00.42#ibcon#about to read 5, iclass 28, count 2 2006.218.08:19:00.42#ibcon#read 5, iclass 28, count 2 2006.218.08:19:00.42#ibcon#about to read 6, iclass 28, count 2 2006.218.08:19:00.42#ibcon#read 6, iclass 28, count 2 2006.218.08:19:00.42#ibcon#end of sib2, iclass 28, count 2 2006.218.08:19:00.42#ibcon#*after write, iclass 28, count 2 2006.218.08:19:00.42#ibcon#*before return 0, iclass 28, count 2 2006.218.08:19:00.42#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.218.08:19:00.42#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.218.08:19:00.42#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.218.08:19:00.42#ibcon#ireg 7 cls_cnt 0 2006.218.08:19:00.42#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.218.08:19:00.54#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.218.08:19:00.54#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.218.08:19:00.54#ibcon#enter wrdev, iclass 28, count 0 2006.218.08:19:00.54#ibcon#first serial, iclass 28, count 0 2006.218.08:19:00.54#ibcon#enter sib2, iclass 28, count 0 2006.218.08:19:00.54#ibcon#flushed, iclass 28, count 0 2006.218.08:19:00.54#ibcon#about to write, iclass 28, count 0 2006.218.08:19:00.54#ibcon#wrote, iclass 28, count 0 2006.218.08:19:00.54#ibcon#about to read 3, iclass 28, count 0 2006.218.08:19:00.56#ibcon#read 3, iclass 28, count 0 2006.218.08:19:00.56#ibcon#about to read 4, iclass 28, count 0 2006.218.08:19:00.56#ibcon#read 4, iclass 28, count 0 2006.218.08:19:00.56#ibcon#about to read 5, iclass 28, count 0 2006.218.08:19:00.56#ibcon#read 5, iclass 28, count 0 2006.218.08:19:00.56#ibcon#about to read 6, iclass 28, count 0 2006.218.08:19:00.56#ibcon#read 6, iclass 28, count 0 2006.218.08:19:00.56#ibcon#end of sib2, iclass 28, count 0 2006.218.08:19:00.56#ibcon#*mode == 0, iclass 28, count 0 2006.218.08:19:00.56#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.218.08:19:00.56#ibcon#[25=USB\r\n] 2006.218.08:19:00.56#ibcon#*before write, iclass 28, count 0 2006.218.08:19:00.56#ibcon#enter sib2, iclass 28, count 0 2006.218.08:19:00.56#ibcon#flushed, iclass 28, count 0 2006.218.08:19:00.56#ibcon#about to write, iclass 28, count 0 2006.218.08:19:00.56#ibcon#wrote, iclass 28, count 0 2006.218.08:19:00.56#ibcon#about to read 3, iclass 28, count 0 2006.218.08:19:00.59#ibcon#read 3, iclass 28, count 0 2006.218.08:19:00.59#ibcon#about to read 4, iclass 28, count 0 2006.218.08:19:00.59#ibcon#read 4, iclass 28, count 0 2006.218.08:19:00.59#ibcon#about to read 5, iclass 28, count 0 2006.218.08:19:00.59#ibcon#read 5, iclass 28, count 0 2006.218.08:19:00.59#ibcon#about to read 6, iclass 28, count 0 2006.218.08:19:00.59#ibcon#read 6, iclass 28, count 0 2006.218.08:19:00.59#ibcon#end of sib2, iclass 28, count 0 2006.218.08:19:00.59#ibcon#*after write, iclass 28, count 0 2006.218.08:19:00.59#ibcon#*before return 0, iclass 28, count 0 2006.218.08:19:00.59#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.218.08:19:00.59#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.218.08:19:00.59#ibcon#about to clear, iclass 28 cls_cnt 0 2006.218.08:19:00.59#ibcon#cleared, iclass 28 cls_cnt 0 2006.218.08:19:00.59$vc4f8/vblo=1,632.99 2006.218.08:19:00.59#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.218.08:19:00.59#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.218.08:19:00.59#ibcon#ireg 17 cls_cnt 0 2006.218.08:19:00.59#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.218.08:19:00.59#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.218.08:19:00.59#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.218.08:19:00.59#ibcon#enter wrdev, iclass 30, count 0 2006.218.08:19:00.59#ibcon#first serial, iclass 30, count 0 2006.218.08:19:00.59#ibcon#enter sib2, iclass 30, count 0 2006.218.08:19:00.59#ibcon#flushed, iclass 30, count 0 2006.218.08:19:00.59#ibcon#about to write, iclass 30, count 0 2006.218.08:19:00.59#ibcon#wrote, iclass 30, count 0 2006.218.08:19:00.59#ibcon#about to read 3, iclass 30, count 0 2006.218.08:19:00.61#ibcon#read 3, iclass 30, count 0 2006.218.08:19:00.61#ibcon#about to read 4, iclass 30, count 0 2006.218.08:19:00.61#ibcon#read 4, iclass 30, count 0 2006.218.08:19:00.61#ibcon#about to read 5, iclass 30, count 0 2006.218.08:19:00.61#ibcon#read 5, iclass 30, count 0 2006.218.08:19:00.61#ibcon#about to read 6, iclass 30, count 0 2006.218.08:19:00.61#ibcon#read 6, iclass 30, count 0 2006.218.08:19:00.61#ibcon#end of sib2, iclass 30, count 0 2006.218.08:19:00.61#ibcon#*mode == 0, iclass 30, count 0 2006.218.08:19:00.61#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.218.08:19:00.61#ibcon#[28=FRQ=01,632.99\r\n] 2006.218.08:19:00.61#ibcon#*before write, iclass 30, count 0 2006.218.08:19:00.61#ibcon#enter sib2, iclass 30, count 0 2006.218.08:19:00.61#ibcon#flushed, iclass 30, count 0 2006.218.08:19:00.61#ibcon#about to write, iclass 30, count 0 2006.218.08:19:00.61#ibcon#wrote, iclass 30, count 0 2006.218.08:19:00.61#ibcon#about to read 3, iclass 30, count 0 2006.218.08:19:00.65#ibcon#read 3, iclass 30, count 0 2006.218.08:19:00.65#ibcon#about to read 4, iclass 30, count 0 2006.218.08:19:00.65#ibcon#read 4, iclass 30, count 0 2006.218.08:19:00.65#ibcon#about to read 5, iclass 30, count 0 2006.218.08:19:00.65#ibcon#read 5, iclass 30, count 0 2006.218.08:19:00.65#ibcon#about to read 6, iclass 30, count 0 2006.218.08:19:00.65#ibcon#read 6, iclass 30, count 0 2006.218.08:19:00.65#ibcon#end of sib2, iclass 30, count 0 2006.218.08:19:00.65#ibcon#*after write, iclass 30, count 0 2006.218.08:19:00.65#ibcon#*before return 0, iclass 30, count 0 2006.218.08:19:00.65#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.218.08:19:00.65#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.218.08:19:00.65#ibcon#about to clear, iclass 30 cls_cnt 0 2006.218.08:19:00.65#ibcon#cleared, iclass 30 cls_cnt 0 2006.218.08:19:00.65$vc4f8/vb=1,4 2006.218.08:19:00.65#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.218.08:19:00.65#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.218.08:19:00.65#ibcon#ireg 11 cls_cnt 2 2006.218.08:19:00.65#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.218.08:19:00.65#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.218.08:19:00.65#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.218.08:19:00.65#ibcon#enter wrdev, iclass 32, count 2 2006.218.08:19:00.65#ibcon#first serial, iclass 32, count 2 2006.218.08:19:00.65#ibcon#enter sib2, iclass 32, count 2 2006.218.08:19:00.65#ibcon#flushed, iclass 32, count 2 2006.218.08:19:00.65#ibcon#about to write, iclass 32, count 2 2006.218.08:19:00.65#ibcon#wrote, iclass 32, count 2 2006.218.08:19:00.65#ibcon#about to read 3, iclass 32, count 2 2006.218.08:19:00.67#ibcon#read 3, iclass 32, count 2 2006.218.08:19:00.67#ibcon#about to read 4, iclass 32, count 2 2006.218.08:19:00.67#ibcon#read 4, iclass 32, count 2 2006.218.08:19:00.67#ibcon#about to read 5, iclass 32, count 2 2006.218.08:19:00.67#ibcon#read 5, iclass 32, count 2 2006.218.08:19:00.67#ibcon#about to read 6, iclass 32, count 2 2006.218.08:19:00.67#ibcon#read 6, iclass 32, count 2 2006.218.08:19:00.67#ibcon#end of sib2, iclass 32, count 2 2006.218.08:19:00.67#ibcon#*mode == 0, iclass 32, count 2 2006.218.08:19:00.67#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.218.08:19:00.67#ibcon#[27=AT01-04\r\n] 2006.218.08:19:00.67#ibcon#*before write, iclass 32, count 2 2006.218.08:19:00.67#ibcon#enter sib2, iclass 32, count 2 2006.218.08:19:00.67#ibcon#flushed, iclass 32, count 2 2006.218.08:19:00.67#ibcon#about to write, iclass 32, count 2 2006.218.08:19:00.67#ibcon#wrote, iclass 32, count 2 2006.218.08:19:00.67#ibcon#about to read 3, iclass 32, count 2 2006.218.08:19:00.70#ibcon#read 3, iclass 32, count 2 2006.218.08:19:00.70#ibcon#about to read 4, iclass 32, count 2 2006.218.08:19:00.70#ibcon#read 4, iclass 32, count 2 2006.218.08:19:00.70#ibcon#about to read 5, iclass 32, count 2 2006.218.08:19:00.70#ibcon#read 5, iclass 32, count 2 2006.218.08:19:00.70#ibcon#about to read 6, iclass 32, count 2 2006.218.08:19:00.70#ibcon#read 6, iclass 32, count 2 2006.218.08:19:00.70#ibcon#end of sib2, iclass 32, count 2 2006.218.08:19:00.70#ibcon#*after write, iclass 32, count 2 2006.218.08:19:00.70#ibcon#*before return 0, iclass 32, count 2 2006.218.08:19:00.70#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.218.08:19:00.70#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.218.08:19:00.70#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.218.08:19:00.70#ibcon#ireg 7 cls_cnt 0 2006.218.08:19:00.70#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.218.08:19:00.82#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.218.08:19:00.82#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.218.08:19:00.82#ibcon#enter wrdev, iclass 32, count 0 2006.218.08:19:00.82#ibcon#first serial, iclass 32, count 0 2006.218.08:19:00.82#ibcon#enter sib2, iclass 32, count 0 2006.218.08:19:00.82#ibcon#flushed, iclass 32, count 0 2006.218.08:19:00.82#ibcon#about to write, iclass 32, count 0 2006.218.08:19:00.82#ibcon#wrote, iclass 32, count 0 2006.218.08:19:00.82#ibcon#about to read 3, iclass 32, count 0 2006.218.08:19:00.84#ibcon#read 3, iclass 32, count 0 2006.218.08:19:00.84#ibcon#about to read 4, iclass 32, count 0 2006.218.08:19:00.84#ibcon#read 4, iclass 32, count 0 2006.218.08:19:00.84#ibcon#about to read 5, iclass 32, count 0 2006.218.08:19:00.84#ibcon#read 5, iclass 32, count 0 2006.218.08:19:00.84#ibcon#about to read 6, iclass 32, count 0 2006.218.08:19:00.84#ibcon#read 6, iclass 32, count 0 2006.218.08:19:00.84#ibcon#end of sib2, iclass 32, count 0 2006.218.08:19:00.84#ibcon#*mode == 0, iclass 32, count 0 2006.218.08:19:00.84#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.218.08:19:00.84#ibcon#[27=USB\r\n] 2006.218.08:19:00.84#ibcon#*before write, iclass 32, count 0 2006.218.08:19:00.84#ibcon#enter sib2, iclass 32, count 0 2006.218.08:19:00.84#ibcon#flushed, iclass 32, count 0 2006.218.08:19:00.84#ibcon#about to write, iclass 32, count 0 2006.218.08:19:00.84#ibcon#wrote, iclass 32, count 0 2006.218.08:19:00.84#ibcon#about to read 3, iclass 32, count 0 2006.218.08:19:00.87#ibcon#read 3, iclass 32, count 0 2006.218.08:19:00.87#ibcon#about to read 4, iclass 32, count 0 2006.218.08:19:00.87#ibcon#read 4, iclass 32, count 0 2006.218.08:19:00.87#ibcon#about to read 5, iclass 32, count 0 2006.218.08:19:00.87#ibcon#read 5, iclass 32, count 0 2006.218.08:19:00.87#ibcon#about to read 6, iclass 32, count 0 2006.218.08:19:00.87#ibcon#read 6, iclass 32, count 0 2006.218.08:19:00.87#ibcon#end of sib2, iclass 32, count 0 2006.218.08:19:00.87#ibcon#*after write, iclass 32, count 0 2006.218.08:19:00.87#ibcon#*before return 0, iclass 32, count 0 2006.218.08:19:00.87#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.218.08:19:00.87#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.218.08:19:00.87#ibcon#about to clear, iclass 32 cls_cnt 0 2006.218.08:19:00.87#ibcon#cleared, iclass 32 cls_cnt 0 2006.218.08:19:00.87$vc4f8/vblo=2,640.99 2006.218.08:19:00.87#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.218.08:19:00.87#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.218.08:19:00.87#ibcon#ireg 17 cls_cnt 0 2006.218.08:19:00.87#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.218.08:19:00.87#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.218.08:19:00.87#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.218.08:19:00.87#ibcon#enter wrdev, iclass 34, count 0 2006.218.08:19:00.87#ibcon#first serial, iclass 34, count 0 2006.218.08:19:00.87#ibcon#enter sib2, iclass 34, count 0 2006.218.08:19:00.87#ibcon#flushed, iclass 34, count 0 2006.218.08:19:00.87#ibcon#about to write, iclass 34, count 0 2006.218.08:19:00.87#ibcon#wrote, iclass 34, count 0 2006.218.08:19:00.87#ibcon#about to read 3, iclass 34, count 0 2006.218.08:19:00.89#ibcon#read 3, iclass 34, count 0 2006.218.08:19:00.89#ibcon#about to read 4, iclass 34, count 0 2006.218.08:19:00.89#ibcon#read 4, iclass 34, count 0 2006.218.08:19:00.89#ibcon#about to read 5, iclass 34, count 0 2006.218.08:19:00.89#ibcon#read 5, iclass 34, count 0 2006.218.08:19:00.89#ibcon#about to read 6, iclass 34, count 0 2006.218.08:19:00.89#ibcon#read 6, iclass 34, count 0 2006.218.08:19:00.89#ibcon#end of sib2, iclass 34, count 0 2006.218.08:19:00.89#ibcon#*mode == 0, iclass 34, count 0 2006.218.08:19:00.89#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.218.08:19:00.89#ibcon#[28=FRQ=02,640.99\r\n] 2006.218.08:19:00.89#ibcon#*before write, iclass 34, count 0 2006.218.08:19:00.89#ibcon#enter sib2, iclass 34, count 0 2006.218.08:19:00.89#ibcon#flushed, iclass 34, count 0 2006.218.08:19:00.89#ibcon#about to write, iclass 34, count 0 2006.218.08:19:00.89#ibcon#wrote, iclass 34, count 0 2006.218.08:19:00.89#ibcon#about to read 3, iclass 34, count 0 2006.218.08:19:00.93#ibcon#read 3, iclass 34, count 0 2006.218.08:19:00.93#ibcon#about to read 4, iclass 34, count 0 2006.218.08:19:00.93#ibcon#read 4, iclass 34, count 0 2006.218.08:19:00.93#ibcon#about to read 5, iclass 34, count 0 2006.218.08:19:00.93#ibcon#read 5, iclass 34, count 0 2006.218.08:19:00.93#ibcon#about to read 6, iclass 34, count 0 2006.218.08:19:00.93#ibcon#read 6, iclass 34, count 0 2006.218.08:19:00.93#ibcon#end of sib2, iclass 34, count 0 2006.218.08:19:00.93#ibcon#*after write, iclass 34, count 0 2006.218.08:19:00.93#ibcon#*before return 0, iclass 34, count 0 2006.218.08:19:00.93#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.218.08:19:00.93#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.218.08:19:00.93#ibcon#about to clear, iclass 34 cls_cnt 0 2006.218.08:19:00.93#ibcon#cleared, iclass 34 cls_cnt 0 2006.218.08:19:00.93$vc4f8/vb=2,4 2006.218.08:19:00.93#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.218.08:19:00.93#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.218.08:19:00.93#ibcon#ireg 11 cls_cnt 2 2006.218.08:19:00.93#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.218.08:19:00.99#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.218.08:19:00.99#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.218.08:19:00.99#ibcon#enter wrdev, iclass 36, count 2 2006.218.08:19:00.99#ibcon#first serial, iclass 36, count 2 2006.218.08:19:00.99#ibcon#enter sib2, iclass 36, count 2 2006.218.08:19:00.99#ibcon#flushed, iclass 36, count 2 2006.218.08:19:00.99#ibcon#about to write, iclass 36, count 2 2006.218.08:19:00.99#ibcon#wrote, iclass 36, count 2 2006.218.08:19:00.99#ibcon#about to read 3, iclass 36, count 2 2006.218.08:19:01.01#ibcon#read 3, iclass 36, count 2 2006.218.08:19:01.01#ibcon#about to read 4, iclass 36, count 2 2006.218.08:19:01.01#ibcon#read 4, iclass 36, count 2 2006.218.08:19:01.01#ibcon#about to read 5, iclass 36, count 2 2006.218.08:19:01.01#ibcon#read 5, iclass 36, count 2 2006.218.08:19:01.01#ibcon#about to read 6, iclass 36, count 2 2006.218.08:19:01.01#ibcon#read 6, iclass 36, count 2 2006.218.08:19:01.01#ibcon#end of sib2, iclass 36, count 2 2006.218.08:19:01.01#ibcon#*mode == 0, iclass 36, count 2 2006.218.08:19:01.01#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.218.08:19:01.01#ibcon#[27=AT02-04\r\n] 2006.218.08:19:01.01#ibcon#*before write, iclass 36, count 2 2006.218.08:19:01.01#ibcon#enter sib2, iclass 36, count 2 2006.218.08:19:01.01#ibcon#flushed, iclass 36, count 2 2006.218.08:19:01.01#ibcon#about to write, iclass 36, count 2 2006.218.08:19:01.01#ibcon#wrote, iclass 36, count 2 2006.218.08:19:01.01#ibcon#about to read 3, iclass 36, count 2 2006.218.08:19:01.04#ibcon#read 3, iclass 36, count 2 2006.218.08:19:01.04#ibcon#about to read 4, iclass 36, count 2 2006.218.08:19:01.04#ibcon#read 4, iclass 36, count 2 2006.218.08:19:01.04#ibcon#about to read 5, iclass 36, count 2 2006.218.08:19:01.04#ibcon#read 5, iclass 36, count 2 2006.218.08:19:01.04#ibcon#about to read 6, iclass 36, count 2 2006.218.08:19:01.04#ibcon#read 6, iclass 36, count 2 2006.218.08:19:01.04#ibcon#end of sib2, iclass 36, count 2 2006.218.08:19:01.04#ibcon#*after write, iclass 36, count 2 2006.218.08:19:01.04#ibcon#*before return 0, iclass 36, count 2 2006.218.08:19:01.04#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.218.08:19:01.04#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.218.08:19:01.04#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.218.08:19:01.04#ibcon#ireg 7 cls_cnt 0 2006.218.08:19:01.04#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.218.08:19:01.16#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.218.08:19:01.16#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.218.08:19:01.16#ibcon#enter wrdev, iclass 36, count 0 2006.218.08:19:01.16#ibcon#first serial, iclass 36, count 0 2006.218.08:19:01.16#ibcon#enter sib2, iclass 36, count 0 2006.218.08:19:01.16#ibcon#flushed, iclass 36, count 0 2006.218.08:19:01.16#ibcon#about to write, iclass 36, count 0 2006.218.08:19:01.16#ibcon#wrote, iclass 36, count 0 2006.218.08:19:01.16#ibcon#about to read 3, iclass 36, count 0 2006.218.08:19:01.19#ibcon#read 3, iclass 36, count 0 2006.218.08:19:01.19#ibcon#about to read 4, iclass 36, count 0 2006.218.08:19:01.19#ibcon#read 4, iclass 36, count 0 2006.218.08:19:01.19#ibcon#about to read 5, iclass 36, count 0 2006.218.08:19:01.19#ibcon#read 5, iclass 36, count 0 2006.218.08:19:01.19#ibcon#about to read 6, iclass 36, count 0 2006.218.08:19:01.19#ibcon#read 6, iclass 36, count 0 2006.218.08:19:01.19#ibcon#end of sib2, iclass 36, count 0 2006.218.08:19:01.19#ibcon#*mode == 0, iclass 36, count 0 2006.218.08:19:01.19#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.218.08:19:01.19#ibcon#[27=USB\r\n] 2006.218.08:19:01.19#ibcon#*before write, iclass 36, count 0 2006.218.08:19:01.19#ibcon#enter sib2, iclass 36, count 0 2006.218.08:19:01.19#ibcon#flushed, iclass 36, count 0 2006.218.08:19:01.19#ibcon#about to write, iclass 36, count 0 2006.218.08:19:01.19#ibcon#wrote, iclass 36, count 0 2006.218.08:19:01.19#ibcon#about to read 3, iclass 36, count 0 2006.218.08:19:01.22#ibcon#read 3, iclass 36, count 0 2006.218.08:19:01.22#ibcon#about to read 4, iclass 36, count 0 2006.218.08:19:01.22#ibcon#read 4, iclass 36, count 0 2006.218.08:19:01.22#ibcon#about to read 5, iclass 36, count 0 2006.218.08:19:01.22#ibcon#read 5, iclass 36, count 0 2006.218.08:19:01.22#ibcon#about to read 6, iclass 36, count 0 2006.218.08:19:01.22#ibcon#read 6, iclass 36, count 0 2006.218.08:19:01.22#ibcon#end of sib2, iclass 36, count 0 2006.218.08:19:01.22#ibcon#*after write, iclass 36, count 0 2006.218.08:19:01.22#ibcon#*before return 0, iclass 36, count 0 2006.218.08:19:01.22#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.218.08:19:01.22#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.218.08:19:01.22#ibcon#about to clear, iclass 36 cls_cnt 0 2006.218.08:19:01.22#ibcon#cleared, iclass 36 cls_cnt 0 2006.218.08:19:01.22$vc4f8/vblo=3,656.99 2006.218.08:19:01.22#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.218.08:19:01.22#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.218.08:19:01.22#ibcon#ireg 17 cls_cnt 0 2006.218.08:19:01.22#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.218.08:19:01.22#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.218.08:19:01.22#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.218.08:19:01.22#ibcon#enter wrdev, iclass 38, count 0 2006.218.08:19:01.22#ibcon#first serial, iclass 38, count 0 2006.218.08:19:01.22#ibcon#enter sib2, iclass 38, count 0 2006.218.08:19:01.22#ibcon#flushed, iclass 38, count 0 2006.218.08:19:01.22#ibcon#about to write, iclass 38, count 0 2006.218.08:19:01.22#ibcon#wrote, iclass 38, count 0 2006.218.08:19:01.22#ibcon#about to read 3, iclass 38, count 0 2006.218.08:19:01.24#ibcon#read 3, iclass 38, count 0 2006.218.08:19:01.24#ibcon#about to read 4, iclass 38, count 0 2006.218.08:19:01.24#ibcon#read 4, iclass 38, count 0 2006.218.08:19:01.24#ibcon#about to read 5, iclass 38, count 0 2006.218.08:19:01.24#ibcon#read 5, iclass 38, count 0 2006.218.08:19:01.24#ibcon#about to read 6, iclass 38, count 0 2006.218.08:19:01.24#ibcon#read 6, iclass 38, count 0 2006.218.08:19:01.24#ibcon#end of sib2, iclass 38, count 0 2006.218.08:19:01.24#ibcon#*mode == 0, iclass 38, count 0 2006.218.08:19:01.24#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.218.08:19:01.24#ibcon#[28=FRQ=03,656.99\r\n] 2006.218.08:19:01.24#ibcon#*before write, iclass 38, count 0 2006.218.08:19:01.24#ibcon#enter sib2, iclass 38, count 0 2006.218.08:19:01.24#ibcon#flushed, iclass 38, count 0 2006.218.08:19:01.24#ibcon#about to write, iclass 38, count 0 2006.218.08:19:01.24#ibcon#wrote, iclass 38, count 0 2006.218.08:19:01.24#ibcon#about to read 3, iclass 38, count 0 2006.218.08:19:01.28#ibcon#read 3, iclass 38, count 0 2006.218.08:19:01.28#ibcon#about to read 4, iclass 38, count 0 2006.218.08:19:01.28#ibcon#read 4, iclass 38, count 0 2006.218.08:19:01.28#ibcon#about to read 5, iclass 38, count 0 2006.218.08:19:01.28#ibcon#read 5, iclass 38, count 0 2006.218.08:19:01.28#ibcon#about to read 6, iclass 38, count 0 2006.218.08:19:01.28#ibcon#read 6, iclass 38, count 0 2006.218.08:19:01.28#ibcon#end of sib2, iclass 38, count 0 2006.218.08:19:01.28#ibcon#*after write, iclass 38, count 0 2006.218.08:19:01.28#ibcon#*before return 0, iclass 38, count 0 2006.218.08:19:01.28#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.218.08:19:01.28#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.218.08:19:01.28#ibcon#about to clear, iclass 38 cls_cnt 0 2006.218.08:19:01.28#ibcon#cleared, iclass 38 cls_cnt 0 2006.218.08:19:01.28$vc4f8/vb=3,4 2006.218.08:19:01.28#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.218.08:19:01.28#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.218.08:19:01.28#ibcon#ireg 11 cls_cnt 2 2006.218.08:19:01.28#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.218.08:19:01.34#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.218.08:19:01.34#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.218.08:19:01.34#ibcon#enter wrdev, iclass 40, count 2 2006.218.08:19:01.34#ibcon#first serial, iclass 40, count 2 2006.218.08:19:01.34#ibcon#enter sib2, iclass 40, count 2 2006.218.08:19:01.34#ibcon#flushed, iclass 40, count 2 2006.218.08:19:01.34#ibcon#about to write, iclass 40, count 2 2006.218.08:19:01.34#ibcon#wrote, iclass 40, count 2 2006.218.08:19:01.34#ibcon#about to read 3, iclass 40, count 2 2006.218.08:19:01.36#ibcon#read 3, iclass 40, count 2 2006.218.08:19:01.36#ibcon#about to read 4, iclass 40, count 2 2006.218.08:19:01.36#ibcon#read 4, iclass 40, count 2 2006.218.08:19:01.36#ibcon#about to read 5, iclass 40, count 2 2006.218.08:19:01.36#ibcon#read 5, iclass 40, count 2 2006.218.08:19:01.36#ibcon#about to read 6, iclass 40, count 2 2006.218.08:19:01.36#ibcon#read 6, iclass 40, count 2 2006.218.08:19:01.36#ibcon#end of sib2, iclass 40, count 2 2006.218.08:19:01.36#ibcon#*mode == 0, iclass 40, count 2 2006.218.08:19:01.36#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.218.08:19:01.36#ibcon#[27=AT03-04\r\n] 2006.218.08:19:01.36#ibcon#*before write, iclass 40, count 2 2006.218.08:19:01.36#ibcon#enter sib2, iclass 40, count 2 2006.218.08:19:01.36#ibcon#flushed, iclass 40, count 2 2006.218.08:19:01.36#ibcon#about to write, iclass 40, count 2 2006.218.08:19:01.36#ibcon#wrote, iclass 40, count 2 2006.218.08:19:01.36#ibcon#about to read 3, iclass 40, count 2 2006.218.08:19:01.39#ibcon#read 3, iclass 40, count 2 2006.218.08:19:01.39#ibcon#about to read 4, iclass 40, count 2 2006.218.08:19:01.39#ibcon#read 4, iclass 40, count 2 2006.218.08:19:01.39#ibcon#about to read 5, iclass 40, count 2 2006.218.08:19:01.39#ibcon#read 5, iclass 40, count 2 2006.218.08:19:01.39#ibcon#about to read 6, iclass 40, count 2 2006.218.08:19:01.39#ibcon#read 6, iclass 40, count 2 2006.218.08:19:01.39#ibcon#end of sib2, iclass 40, count 2 2006.218.08:19:01.39#ibcon#*after write, iclass 40, count 2 2006.218.08:19:01.39#ibcon#*before return 0, iclass 40, count 2 2006.218.08:19:01.39#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.218.08:19:01.39#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.218.08:19:01.39#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.218.08:19:01.39#ibcon#ireg 7 cls_cnt 0 2006.218.08:19:01.39#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.218.08:19:01.51#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.218.08:19:01.51#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.218.08:19:01.51#ibcon#enter wrdev, iclass 40, count 0 2006.218.08:19:01.51#ibcon#first serial, iclass 40, count 0 2006.218.08:19:01.51#ibcon#enter sib2, iclass 40, count 0 2006.218.08:19:01.51#ibcon#flushed, iclass 40, count 0 2006.218.08:19:01.51#ibcon#about to write, iclass 40, count 0 2006.218.08:19:01.51#ibcon#wrote, iclass 40, count 0 2006.218.08:19:01.51#ibcon#about to read 3, iclass 40, count 0 2006.218.08:19:01.53#ibcon#read 3, iclass 40, count 0 2006.218.08:19:01.53#ibcon#about to read 4, iclass 40, count 0 2006.218.08:19:01.53#ibcon#read 4, iclass 40, count 0 2006.218.08:19:01.53#ibcon#about to read 5, iclass 40, count 0 2006.218.08:19:01.53#ibcon#read 5, iclass 40, count 0 2006.218.08:19:01.53#ibcon#about to read 6, iclass 40, count 0 2006.218.08:19:01.53#ibcon#read 6, iclass 40, count 0 2006.218.08:19:01.53#ibcon#end of sib2, iclass 40, count 0 2006.218.08:19:01.53#ibcon#*mode == 0, iclass 40, count 0 2006.218.08:19:01.53#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.218.08:19:01.53#ibcon#[27=USB\r\n] 2006.218.08:19:01.53#ibcon#*before write, iclass 40, count 0 2006.218.08:19:01.53#ibcon#enter sib2, iclass 40, count 0 2006.218.08:19:01.53#ibcon#flushed, iclass 40, count 0 2006.218.08:19:01.53#ibcon#about to write, iclass 40, count 0 2006.218.08:19:01.53#ibcon#wrote, iclass 40, count 0 2006.218.08:19:01.53#ibcon#about to read 3, iclass 40, count 0 2006.218.08:19:01.56#ibcon#read 3, iclass 40, count 0 2006.218.08:19:01.56#ibcon#about to read 4, iclass 40, count 0 2006.218.08:19:01.56#ibcon#read 4, iclass 40, count 0 2006.218.08:19:01.56#ibcon#about to read 5, iclass 40, count 0 2006.218.08:19:01.56#ibcon#read 5, iclass 40, count 0 2006.218.08:19:01.56#ibcon#about to read 6, iclass 40, count 0 2006.218.08:19:01.56#ibcon#read 6, iclass 40, count 0 2006.218.08:19:01.56#ibcon#end of sib2, iclass 40, count 0 2006.218.08:19:01.56#ibcon#*after write, iclass 40, count 0 2006.218.08:19:01.56#ibcon#*before return 0, iclass 40, count 0 2006.218.08:19:01.56#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.218.08:19:01.56#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.218.08:19:01.56#ibcon#about to clear, iclass 40 cls_cnt 0 2006.218.08:19:01.56#ibcon#cleared, iclass 40 cls_cnt 0 2006.218.08:19:01.56$vc4f8/vblo=4,712.99 2006.218.08:19:01.56#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.218.08:19:01.56#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.218.08:19:01.56#ibcon#ireg 17 cls_cnt 0 2006.218.08:19:01.56#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.218.08:19:01.56#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.218.08:19:01.56#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.218.08:19:01.56#ibcon#enter wrdev, iclass 4, count 0 2006.218.08:19:01.56#ibcon#first serial, iclass 4, count 0 2006.218.08:19:01.56#ibcon#enter sib2, iclass 4, count 0 2006.218.08:19:01.56#ibcon#flushed, iclass 4, count 0 2006.218.08:19:01.56#ibcon#about to write, iclass 4, count 0 2006.218.08:19:01.56#ibcon#wrote, iclass 4, count 0 2006.218.08:19:01.56#ibcon#about to read 3, iclass 4, count 0 2006.218.08:19:01.58#ibcon#read 3, iclass 4, count 0 2006.218.08:19:01.58#ibcon#about to read 4, iclass 4, count 0 2006.218.08:19:01.58#ibcon#read 4, iclass 4, count 0 2006.218.08:19:01.58#ibcon#about to read 5, iclass 4, count 0 2006.218.08:19:01.58#ibcon#read 5, iclass 4, count 0 2006.218.08:19:01.58#ibcon#about to read 6, iclass 4, count 0 2006.218.08:19:01.58#ibcon#read 6, iclass 4, count 0 2006.218.08:19:01.58#ibcon#end of sib2, iclass 4, count 0 2006.218.08:19:01.58#ibcon#*mode == 0, iclass 4, count 0 2006.218.08:19:01.58#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.218.08:19:01.58#ibcon#[28=FRQ=04,712.99\r\n] 2006.218.08:19:01.58#ibcon#*before write, iclass 4, count 0 2006.218.08:19:01.58#ibcon#enter sib2, iclass 4, count 0 2006.218.08:19:01.58#ibcon#flushed, iclass 4, count 0 2006.218.08:19:01.58#ibcon#about to write, iclass 4, count 0 2006.218.08:19:01.58#ibcon#wrote, iclass 4, count 0 2006.218.08:19:01.58#ibcon#about to read 3, iclass 4, count 0 2006.218.08:19:01.62#ibcon#read 3, iclass 4, count 0 2006.218.08:19:01.62#ibcon#about to read 4, iclass 4, count 0 2006.218.08:19:01.62#ibcon#read 4, iclass 4, count 0 2006.218.08:19:01.62#ibcon#about to read 5, iclass 4, count 0 2006.218.08:19:01.62#ibcon#read 5, iclass 4, count 0 2006.218.08:19:01.62#ibcon#about to read 6, iclass 4, count 0 2006.218.08:19:01.62#ibcon#read 6, iclass 4, count 0 2006.218.08:19:01.62#ibcon#end of sib2, iclass 4, count 0 2006.218.08:19:01.62#ibcon#*after write, iclass 4, count 0 2006.218.08:19:01.62#ibcon#*before return 0, iclass 4, count 0 2006.218.08:19:01.62#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.218.08:19:01.62#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.218.08:19:01.62#ibcon#about to clear, iclass 4 cls_cnt 0 2006.218.08:19:01.62#ibcon#cleared, iclass 4 cls_cnt 0 2006.218.08:19:01.62$vc4f8/vb=4,4 2006.218.08:19:01.62#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.218.08:19:01.62#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.218.08:19:01.62#ibcon#ireg 11 cls_cnt 2 2006.218.08:19:01.62#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.218.08:19:01.68#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.218.08:19:01.68#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.218.08:19:01.68#ibcon#enter wrdev, iclass 6, count 2 2006.218.08:19:01.68#ibcon#first serial, iclass 6, count 2 2006.218.08:19:01.68#ibcon#enter sib2, iclass 6, count 2 2006.218.08:19:01.68#ibcon#flushed, iclass 6, count 2 2006.218.08:19:01.68#ibcon#about to write, iclass 6, count 2 2006.218.08:19:01.68#ibcon#wrote, iclass 6, count 2 2006.218.08:19:01.68#ibcon#about to read 3, iclass 6, count 2 2006.218.08:19:01.70#ibcon#read 3, iclass 6, count 2 2006.218.08:19:01.70#ibcon#about to read 4, iclass 6, count 2 2006.218.08:19:01.70#ibcon#read 4, iclass 6, count 2 2006.218.08:19:01.70#ibcon#about to read 5, iclass 6, count 2 2006.218.08:19:01.70#ibcon#read 5, iclass 6, count 2 2006.218.08:19:01.70#ibcon#about to read 6, iclass 6, count 2 2006.218.08:19:01.70#ibcon#read 6, iclass 6, count 2 2006.218.08:19:01.70#ibcon#end of sib2, iclass 6, count 2 2006.218.08:19:01.70#ibcon#*mode == 0, iclass 6, count 2 2006.218.08:19:01.70#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.218.08:19:01.70#ibcon#[27=AT04-04\r\n] 2006.218.08:19:01.70#ibcon#*before write, iclass 6, count 2 2006.218.08:19:01.70#ibcon#enter sib2, iclass 6, count 2 2006.218.08:19:01.70#ibcon#flushed, iclass 6, count 2 2006.218.08:19:01.70#ibcon#about to write, iclass 6, count 2 2006.218.08:19:01.70#ibcon#wrote, iclass 6, count 2 2006.218.08:19:01.70#ibcon#about to read 3, iclass 6, count 2 2006.218.08:19:01.73#ibcon#read 3, iclass 6, count 2 2006.218.08:19:01.73#ibcon#about to read 4, iclass 6, count 2 2006.218.08:19:01.73#ibcon#read 4, iclass 6, count 2 2006.218.08:19:01.73#ibcon#about to read 5, iclass 6, count 2 2006.218.08:19:01.73#ibcon#read 5, iclass 6, count 2 2006.218.08:19:01.73#ibcon#about to read 6, iclass 6, count 2 2006.218.08:19:01.73#ibcon#read 6, iclass 6, count 2 2006.218.08:19:01.73#ibcon#end of sib2, iclass 6, count 2 2006.218.08:19:01.73#ibcon#*after write, iclass 6, count 2 2006.218.08:19:01.73#ibcon#*before return 0, iclass 6, count 2 2006.218.08:19:01.73#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.218.08:19:01.73#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.218.08:19:01.73#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.218.08:19:01.73#ibcon#ireg 7 cls_cnt 0 2006.218.08:19:01.73#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.218.08:19:01.85#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.218.08:19:01.85#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.218.08:19:01.85#ibcon#enter wrdev, iclass 6, count 0 2006.218.08:19:01.85#ibcon#first serial, iclass 6, count 0 2006.218.08:19:01.85#ibcon#enter sib2, iclass 6, count 0 2006.218.08:19:01.85#ibcon#flushed, iclass 6, count 0 2006.218.08:19:01.85#ibcon#about to write, iclass 6, count 0 2006.218.08:19:01.85#ibcon#wrote, iclass 6, count 0 2006.218.08:19:01.85#ibcon#about to read 3, iclass 6, count 0 2006.218.08:19:01.87#ibcon#read 3, iclass 6, count 0 2006.218.08:19:01.87#ibcon#about to read 4, iclass 6, count 0 2006.218.08:19:01.87#ibcon#read 4, iclass 6, count 0 2006.218.08:19:01.87#ibcon#about to read 5, iclass 6, count 0 2006.218.08:19:01.87#ibcon#read 5, iclass 6, count 0 2006.218.08:19:01.87#ibcon#about to read 6, iclass 6, count 0 2006.218.08:19:01.87#ibcon#read 6, iclass 6, count 0 2006.218.08:19:01.87#ibcon#end of sib2, iclass 6, count 0 2006.218.08:19:01.87#ibcon#*mode == 0, iclass 6, count 0 2006.218.08:19:01.87#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.218.08:19:01.87#ibcon#[27=USB\r\n] 2006.218.08:19:01.87#ibcon#*before write, iclass 6, count 0 2006.218.08:19:01.87#ibcon#enter sib2, iclass 6, count 0 2006.218.08:19:01.87#ibcon#flushed, iclass 6, count 0 2006.218.08:19:01.87#ibcon#about to write, iclass 6, count 0 2006.218.08:19:01.87#ibcon#wrote, iclass 6, count 0 2006.218.08:19:01.87#ibcon#about to read 3, iclass 6, count 0 2006.218.08:19:01.90#ibcon#read 3, iclass 6, count 0 2006.218.08:19:01.90#ibcon#about to read 4, iclass 6, count 0 2006.218.08:19:01.90#ibcon#read 4, iclass 6, count 0 2006.218.08:19:01.90#ibcon#about to read 5, iclass 6, count 0 2006.218.08:19:01.90#ibcon#read 5, iclass 6, count 0 2006.218.08:19:01.90#ibcon#about to read 6, iclass 6, count 0 2006.218.08:19:01.90#ibcon#read 6, iclass 6, count 0 2006.218.08:19:01.90#ibcon#end of sib2, iclass 6, count 0 2006.218.08:19:01.90#ibcon#*after write, iclass 6, count 0 2006.218.08:19:01.90#ibcon#*before return 0, iclass 6, count 0 2006.218.08:19:01.90#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.218.08:19:01.90#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.218.08:19:01.90#ibcon#about to clear, iclass 6 cls_cnt 0 2006.218.08:19:01.90#ibcon#cleared, iclass 6 cls_cnt 0 2006.218.08:19:01.90$vc4f8/vblo=5,744.99 2006.218.08:19:01.90#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.218.08:19:01.90#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.218.08:19:01.90#ibcon#ireg 17 cls_cnt 0 2006.218.08:19:01.90#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.218.08:19:01.90#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.218.08:19:01.90#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.218.08:19:01.90#ibcon#enter wrdev, iclass 10, count 0 2006.218.08:19:01.90#ibcon#first serial, iclass 10, count 0 2006.218.08:19:01.90#ibcon#enter sib2, iclass 10, count 0 2006.218.08:19:01.90#ibcon#flushed, iclass 10, count 0 2006.218.08:19:01.90#ibcon#about to write, iclass 10, count 0 2006.218.08:19:01.90#ibcon#wrote, iclass 10, count 0 2006.218.08:19:01.90#ibcon#about to read 3, iclass 10, count 0 2006.218.08:19:01.92#ibcon#read 3, iclass 10, count 0 2006.218.08:19:01.92#ibcon#about to read 4, iclass 10, count 0 2006.218.08:19:01.92#ibcon#read 4, iclass 10, count 0 2006.218.08:19:01.92#ibcon#about to read 5, iclass 10, count 0 2006.218.08:19:01.92#ibcon#read 5, iclass 10, count 0 2006.218.08:19:01.92#ibcon#about to read 6, iclass 10, count 0 2006.218.08:19:01.92#ibcon#read 6, iclass 10, count 0 2006.218.08:19:01.92#ibcon#end of sib2, iclass 10, count 0 2006.218.08:19:01.92#ibcon#*mode == 0, iclass 10, count 0 2006.218.08:19:01.92#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.218.08:19:01.92#ibcon#[28=FRQ=05,744.99\r\n] 2006.218.08:19:01.92#ibcon#*before write, iclass 10, count 0 2006.218.08:19:01.92#ibcon#enter sib2, iclass 10, count 0 2006.218.08:19:01.92#ibcon#flushed, iclass 10, count 0 2006.218.08:19:01.92#ibcon#about to write, iclass 10, count 0 2006.218.08:19:01.92#ibcon#wrote, iclass 10, count 0 2006.218.08:19:01.92#ibcon#about to read 3, iclass 10, count 0 2006.218.08:19:01.97#ibcon#read 3, iclass 10, count 0 2006.218.08:19:01.97#ibcon#about to read 4, iclass 10, count 0 2006.218.08:19:01.97#ibcon#read 4, iclass 10, count 0 2006.218.08:19:01.97#ibcon#about to read 5, iclass 10, count 0 2006.218.08:19:01.97#ibcon#read 5, iclass 10, count 0 2006.218.08:19:01.97#ibcon#about to read 6, iclass 10, count 0 2006.218.08:19:01.97#ibcon#read 6, iclass 10, count 0 2006.218.08:19:01.97#ibcon#end of sib2, iclass 10, count 0 2006.218.08:19:01.97#ibcon#*after write, iclass 10, count 0 2006.218.08:19:01.97#ibcon#*before return 0, iclass 10, count 0 2006.218.08:19:01.97#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.218.08:19:01.97#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.218.08:19:01.97#ibcon#about to clear, iclass 10 cls_cnt 0 2006.218.08:19:01.97#ibcon#cleared, iclass 10 cls_cnt 0 2006.218.08:19:01.97$vc4f8/vb=5,4 2006.218.08:19:01.97#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.218.08:19:01.97#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.218.08:19:01.97#ibcon#ireg 11 cls_cnt 2 2006.218.08:19:01.97#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.218.08:19:02.02#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.218.08:19:02.02#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.218.08:19:02.02#ibcon#enter wrdev, iclass 12, count 2 2006.218.08:19:02.02#ibcon#first serial, iclass 12, count 2 2006.218.08:19:02.02#ibcon#enter sib2, iclass 12, count 2 2006.218.08:19:02.02#ibcon#flushed, iclass 12, count 2 2006.218.08:19:02.02#ibcon#about to write, iclass 12, count 2 2006.218.08:19:02.02#ibcon#wrote, iclass 12, count 2 2006.218.08:19:02.02#ibcon#about to read 3, iclass 12, count 2 2006.218.08:19:02.04#ibcon#read 3, iclass 12, count 2 2006.218.08:19:02.04#ibcon#about to read 4, iclass 12, count 2 2006.218.08:19:02.04#ibcon#read 4, iclass 12, count 2 2006.218.08:19:02.04#ibcon#about to read 5, iclass 12, count 2 2006.218.08:19:02.04#ibcon#read 5, iclass 12, count 2 2006.218.08:19:02.04#ibcon#about to read 6, iclass 12, count 2 2006.218.08:19:02.04#ibcon#read 6, iclass 12, count 2 2006.218.08:19:02.04#ibcon#end of sib2, iclass 12, count 2 2006.218.08:19:02.04#ibcon#*mode == 0, iclass 12, count 2 2006.218.08:19:02.04#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.218.08:19:02.04#ibcon#[27=AT05-04\r\n] 2006.218.08:19:02.04#ibcon#*before write, iclass 12, count 2 2006.218.08:19:02.04#ibcon#enter sib2, iclass 12, count 2 2006.218.08:19:02.04#ibcon#flushed, iclass 12, count 2 2006.218.08:19:02.04#ibcon#about to write, iclass 12, count 2 2006.218.08:19:02.04#ibcon#wrote, iclass 12, count 2 2006.218.08:19:02.04#ibcon#about to read 3, iclass 12, count 2 2006.218.08:19:02.07#ibcon#read 3, iclass 12, count 2 2006.218.08:19:02.07#ibcon#about to read 4, iclass 12, count 2 2006.218.08:19:02.07#ibcon#read 4, iclass 12, count 2 2006.218.08:19:02.07#ibcon#about to read 5, iclass 12, count 2 2006.218.08:19:02.07#ibcon#read 5, iclass 12, count 2 2006.218.08:19:02.07#ibcon#about to read 6, iclass 12, count 2 2006.218.08:19:02.07#ibcon#read 6, iclass 12, count 2 2006.218.08:19:02.07#ibcon#end of sib2, iclass 12, count 2 2006.218.08:19:02.07#ibcon#*after write, iclass 12, count 2 2006.218.08:19:02.07#ibcon#*before return 0, iclass 12, count 2 2006.218.08:19:02.07#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.218.08:19:02.07#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.218.08:19:02.07#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.218.08:19:02.07#ibcon#ireg 7 cls_cnt 0 2006.218.08:19:02.07#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.218.08:19:02.19#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.218.08:19:02.19#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.218.08:19:02.19#ibcon#enter wrdev, iclass 12, count 0 2006.218.08:19:02.19#ibcon#first serial, iclass 12, count 0 2006.218.08:19:02.19#ibcon#enter sib2, iclass 12, count 0 2006.218.08:19:02.19#ibcon#flushed, iclass 12, count 0 2006.218.08:19:02.19#ibcon#about to write, iclass 12, count 0 2006.218.08:19:02.19#ibcon#wrote, iclass 12, count 0 2006.218.08:19:02.19#ibcon#about to read 3, iclass 12, count 0 2006.218.08:19:02.21#ibcon#read 3, iclass 12, count 0 2006.218.08:19:02.21#ibcon#about to read 4, iclass 12, count 0 2006.218.08:19:02.21#ibcon#read 4, iclass 12, count 0 2006.218.08:19:02.21#ibcon#about to read 5, iclass 12, count 0 2006.218.08:19:02.21#ibcon#read 5, iclass 12, count 0 2006.218.08:19:02.21#ibcon#about to read 6, iclass 12, count 0 2006.218.08:19:02.21#ibcon#read 6, iclass 12, count 0 2006.218.08:19:02.21#ibcon#end of sib2, iclass 12, count 0 2006.218.08:19:02.21#ibcon#*mode == 0, iclass 12, count 0 2006.218.08:19:02.21#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.218.08:19:02.21#ibcon#[27=USB\r\n] 2006.218.08:19:02.21#ibcon#*before write, iclass 12, count 0 2006.218.08:19:02.21#ibcon#enter sib2, iclass 12, count 0 2006.218.08:19:02.21#ibcon#flushed, iclass 12, count 0 2006.218.08:19:02.21#ibcon#about to write, iclass 12, count 0 2006.218.08:19:02.21#ibcon#wrote, iclass 12, count 0 2006.218.08:19:02.21#ibcon#about to read 3, iclass 12, count 0 2006.218.08:19:02.24#ibcon#read 3, iclass 12, count 0 2006.218.08:19:02.24#ibcon#about to read 4, iclass 12, count 0 2006.218.08:19:02.24#ibcon#read 4, iclass 12, count 0 2006.218.08:19:02.24#ibcon#about to read 5, iclass 12, count 0 2006.218.08:19:02.24#ibcon#read 5, iclass 12, count 0 2006.218.08:19:02.24#ibcon#about to read 6, iclass 12, count 0 2006.218.08:19:02.24#ibcon#read 6, iclass 12, count 0 2006.218.08:19:02.24#ibcon#end of sib2, iclass 12, count 0 2006.218.08:19:02.24#ibcon#*after write, iclass 12, count 0 2006.218.08:19:02.24#ibcon#*before return 0, iclass 12, count 0 2006.218.08:19:02.24#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.218.08:19:02.24#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.218.08:19:02.24#ibcon#about to clear, iclass 12 cls_cnt 0 2006.218.08:19:02.24#ibcon#cleared, iclass 12 cls_cnt 0 2006.218.08:19:02.24$vc4f8/vblo=6,752.99 2006.218.08:19:02.24#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.218.08:19:02.24#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.218.08:19:02.24#ibcon#ireg 17 cls_cnt 0 2006.218.08:19:02.24#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.218.08:19:02.24#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.218.08:19:02.24#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.218.08:19:02.24#ibcon#enter wrdev, iclass 14, count 0 2006.218.08:19:02.24#ibcon#first serial, iclass 14, count 0 2006.218.08:19:02.24#ibcon#enter sib2, iclass 14, count 0 2006.218.08:19:02.24#ibcon#flushed, iclass 14, count 0 2006.218.08:19:02.24#ibcon#about to write, iclass 14, count 0 2006.218.08:19:02.24#ibcon#wrote, iclass 14, count 0 2006.218.08:19:02.24#ibcon#about to read 3, iclass 14, count 0 2006.218.08:19:02.26#ibcon#read 3, iclass 14, count 0 2006.218.08:19:02.26#ibcon#about to read 4, iclass 14, count 0 2006.218.08:19:02.26#ibcon#read 4, iclass 14, count 0 2006.218.08:19:02.26#ibcon#about to read 5, iclass 14, count 0 2006.218.08:19:02.26#ibcon#read 5, iclass 14, count 0 2006.218.08:19:02.26#ibcon#about to read 6, iclass 14, count 0 2006.218.08:19:02.26#ibcon#read 6, iclass 14, count 0 2006.218.08:19:02.26#ibcon#end of sib2, iclass 14, count 0 2006.218.08:19:02.26#ibcon#*mode == 0, iclass 14, count 0 2006.218.08:19:02.26#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.218.08:19:02.26#ibcon#[28=FRQ=06,752.99\r\n] 2006.218.08:19:02.26#ibcon#*before write, iclass 14, count 0 2006.218.08:19:02.26#ibcon#enter sib2, iclass 14, count 0 2006.218.08:19:02.26#ibcon#flushed, iclass 14, count 0 2006.218.08:19:02.26#ibcon#about to write, iclass 14, count 0 2006.218.08:19:02.26#ibcon#wrote, iclass 14, count 0 2006.218.08:19:02.26#ibcon#about to read 3, iclass 14, count 0 2006.218.08:19:02.30#ibcon#read 3, iclass 14, count 0 2006.218.08:19:02.30#ibcon#about to read 4, iclass 14, count 0 2006.218.08:19:02.30#ibcon#read 4, iclass 14, count 0 2006.218.08:19:02.30#ibcon#about to read 5, iclass 14, count 0 2006.218.08:19:02.30#ibcon#read 5, iclass 14, count 0 2006.218.08:19:02.30#ibcon#about to read 6, iclass 14, count 0 2006.218.08:19:02.30#ibcon#read 6, iclass 14, count 0 2006.218.08:19:02.30#ibcon#end of sib2, iclass 14, count 0 2006.218.08:19:02.30#ibcon#*after write, iclass 14, count 0 2006.218.08:19:02.30#ibcon#*before return 0, iclass 14, count 0 2006.218.08:19:02.30#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.218.08:19:02.30#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.218.08:19:02.30#ibcon#about to clear, iclass 14 cls_cnt 0 2006.218.08:19:02.30#ibcon#cleared, iclass 14 cls_cnt 0 2006.218.08:19:02.30$vc4f8/vb=6,4 2006.218.08:19:02.30#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.218.08:19:02.30#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.218.08:19:02.30#ibcon#ireg 11 cls_cnt 2 2006.218.08:19:02.30#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.218.08:19:02.36#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.218.08:19:02.36#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.218.08:19:02.36#ibcon#enter wrdev, iclass 16, count 2 2006.218.08:19:02.36#ibcon#first serial, iclass 16, count 2 2006.218.08:19:02.36#ibcon#enter sib2, iclass 16, count 2 2006.218.08:19:02.36#ibcon#flushed, iclass 16, count 2 2006.218.08:19:02.36#ibcon#about to write, iclass 16, count 2 2006.218.08:19:02.36#ibcon#wrote, iclass 16, count 2 2006.218.08:19:02.36#ibcon#about to read 3, iclass 16, count 2 2006.218.08:19:02.38#ibcon#read 3, iclass 16, count 2 2006.218.08:19:02.38#ibcon#about to read 4, iclass 16, count 2 2006.218.08:19:02.38#ibcon#read 4, iclass 16, count 2 2006.218.08:19:02.38#ibcon#about to read 5, iclass 16, count 2 2006.218.08:19:02.38#ibcon#read 5, iclass 16, count 2 2006.218.08:19:02.38#ibcon#about to read 6, iclass 16, count 2 2006.218.08:19:02.38#ibcon#read 6, iclass 16, count 2 2006.218.08:19:02.38#ibcon#end of sib2, iclass 16, count 2 2006.218.08:19:02.38#ibcon#*mode == 0, iclass 16, count 2 2006.218.08:19:02.38#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.218.08:19:02.38#ibcon#[27=AT06-04\r\n] 2006.218.08:19:02.38#ibcon#*before write, iclass 16, count 2 2006.218.08:19:02.38#ibcon#enter sib2, iclass 16, count 2 2006.218.08:19:02.38#ibcon#flushed, iclass 16, count 2 2006.218.08:19:02.38#ibcon#about to write, iclass 16, count 2 2006.218.08:19:02.38#ibcon#wrote, iclass 16, count 2 2006.218.08:19:02.38#ibcon#about to read 3, iclass 16, count 2 2006.218.08:19:02.41#ibcon#read 3, iclass 16, count 2 2006.218.08:19:02.41#ibcon#about to read 4, iclass 16, count 2 2006.218.08:19:02.41#ibcon#read 4, iclass 16, count 2 2006.218.08:19:02.41#ibcon#about to read 5, iclass 16, count 2 2006.218.08:19:02.41#ibcon#read 5, iclass 16, count 2 2006.218.08:19:02.41#ibcon#about to read 6, iclass 16, count 2 2006.218.08:19:02.41#ibcon#read 6, iclass 16, count 2 2006.218.08:19:02.41#ibcon#end of sib2, iclass 16, count 2 2006.218.08:19:02.41#ibcon#*after write, iclass 16, count 2 2006.218.08:19:02.41#ibcon#*before return 0, iclass 16, count 2 2006.218.08:19:02.41#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.218.08:19:02.41#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.218.08:19:02.41#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.218.08:19:02.41#ibcon#ireg 7 cls_cnt 0 2006.218.08:19:02.41#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.218.08:19:02.53#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.218.08:19:02.53#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.218.08:19:02.53#ibcon#enter wrdev, iclass 16, count 0 2006.218.08:19:02.53#ibcon#first serial, iclass 16, count 0 2006.218.08:19:02.53#ibcon#enter sib2, iclass 16, count 0 2006.218.08:19:02.53#ibcon#flushed, iclass 16, count 0 2006.218.08:19:02.53#ibcon#about to write, iclass 16, count 0 2006.218.08:19:02.53#ibcon#wrote, iclass 16, count 0 2006.218.08:19:02.53#ibcon#about to read 3, iclass 16, count 0 2006.218.08:19:02.55#ibcon#read 3, iclass 16, count 0 2006.218.08:19:02.55#ibcon#about to read 4, iclass 16, count 0 2006.218.08:19:02.55#ibcon#read 4, iclass 16, count 0 2006.218.08:19:02.55#ibcon#about to read 5, iclass 16, count 0 2006.218.08:19:02.55#ibcon#read 5, iclass 16, count 0 2006.218.08:19:02.55#ibcon#about to read 6, iclass 16, count 0 2006.218.08:19:02.55#ibcon#read 6, iclass 16, count 0 2006.218.08:19:02.55#ibcon#end of sib2, iclass 16, count 0 2006.218.08:19:02.55#ibcon#*mode == 0, iclass 16, count 0 2006.218.08:19:02.55#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.218.08:19:02.55#ibcon#[27=USB\r\n] 2006.218.08:19:02.55#ibcon#*before write, iclass 16, count 0 2006.218.08:19:02.55#ibcon#enter sib2, iclass 16, count 0 2006.218.08:19:02.55#ibcon#flushed, iclass 16, count 0 2006.218.08:19:02.55#ibcon#about to write, iclass 16, count 0 2006.218.08:19:02.55#ibcon#wrote, iclass 16, count 0 2006.218.08:19:02.55#ibcon#about to read 3, iclass 16, count 0 2006.218.08:19:02.58#ibcon#read 3, iclass 16, count 0 2006.218.08:19:02.58#ibcon#about to read 4, iclass 16, count 0 2006.218.08:19:02.58#ibcon#read 4, iclass 16, count 0 2006.218.08:19:02.58#ibcon#about to read 5, iclass 16, count 0 2006.218.08:19:02.58#ibcon#read 5, iclass 16, count 0 2006.218.08:19:02.58#ibcon#about to read 6, iclass 16, count 0 2006.218.08:19:02.58#ibcon#read 6, iclass 16, count 0 2006.218.08:19:02.58#ibcon#end of sib2, iclass 16, count 0 2006.218.08:19:02.58#ibcon#*after write, iclass 16, count 0 2006.218.08:19:02.58#ibcon#*before return 0, iclass 16, count 0 2006.218.08:19:02.58#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.218.08:19:02.58#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.218.08:19:02.58#ibcon#about to clear, iclass 16 cls_cnt 0 2006.218.08:19:02.58#ibcon#cleared, iclass 16 cls_cnt 0 2006.218.08:19:02.58$vc4f8/vabw=wide 2006.218.08:19:02.58#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.218.08:19:02.58#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.218.08:19:02.58#ibcon#ireg 8 cls_cnt 0 2006.218.08:19:02.58#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.218.08:19:02.58#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.218.08:19:02.58#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.218.08:19:02.58#ibcon#enter wrdev, iclass 18, count 0 2006.218.08:19:02.58#ibcon#first serial, iclass 18, count 0 2006.218.08:19:02.58#ibcon#enter sib2, iclass 18, count 0 2006.218.08:19:02.58#ibcon#flushed, iclass 18, count 0 2006.218.08:19:02.58#ibcon#about to write, iclass 18, count 0 2006.218.08:19:02.58#ibcon#wrote, iclass 18, count 0 2006.218.08:19:02.58#ibcon#about to read 3, iclass 18, count 0 2006.218.08:19:02.60#ibcon#read 3, iclass 18, count 0 2006.218.08:19:02.60#ibcon#about to read 4, iclass 18, count 0 2006.218.08:19:02.60#ibcon#read 4, iclass 18, count 0 2006.218.08:19:02.60#ibcon#about to read 5, iclass 18, count 0 2006.218.08:19:02.60#ibcon#read 5, iclass 18, count 0 2006.218.08:19:02.60#ibcon#about to read 6, iclass 18, count 0 2006.218.08:19:02.60#ibcon#read 6, iclass 18, count 0 2006.218.08:19:02.60#ibcon#end of sib2, iclass 18, count 0 2006.218.08:19:02.60#ibcon#*mode == 0, iclass 18, count 0 2006.218.08:19:02.60#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.218.08:19:02.60#ibcon#[25=BW32\r\n] 2006.218.08:19:02.60#ibcon#*before write, iclass 18, count 0 2006.218.08:19:02.60#ibcon#enter sib2, iclass 18, count 0 2006.218.08:19:02.60#ibcon#flushed, iclass 18, count 0 2006.218.08:19:02.60#ibcon#about to write, iclass 18, count 0 2006.218.08:19:02.60#ibcon#wrote, iclass 18, count 0 2006.218.08:19:02.60#ibcon#about to read 3, iclass 18, count 0 2006.218.08:19:02.63#ibcon#read 3, iclass 18, count 0 2006.218.08:19:02.63#ibcon#about to read 4, iclass 18, count 0 2006.218.08:19:02.63#ibcon#read 4, iclass 18, count 0 2006.218.08:19:02.63#ibcon#about to read 5, iclass 18, count 0 2006.218.08:19:02.63#ibcon#read 5, iclass 18, count 0 2006.218.08:19:02.63#ibcon#about to read 6, iclass 18, count 0 2006.218.08:19:02.63#ibcon#read 6, iclass 18, count 0 2006.218.08:19:02.63#ibcon#end of sib2, iclass 18, count 0 2006.218.08:19:02.63#ibcon#*after write, iclass 18, count 0 2006.218.08:19:02.63#ibcon#*before return 0, iclass 18, count 0 2006.218.08:19:02.63#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.218.08:19:02.63#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.218.08:19:02.63#ibcon#about to clear, iclass 18 cls_cnt 0 2006.218.08:19:02.63#ibcon#cleared, iclass 18 cls_cnt 0 2006.218.08:19:02.63$vc4f8/vbbw=wide 2006.218.08:19:02.63#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.218.08:19:02.63#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.218.08:19:02.63#ibcon#ireg 8 cls_cnt 0 2006.218.08:19:02.63#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.218.08:19:02.70#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.218.08:19:02.70#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.218.08:19:02.70#ibcon#enter wrdev, iclass 20, count 0 2006.218.08:19:02.70#ibcon#first serial, iclass 20, count 0 2006.218.08:19:02.70#ibcon#enter sib2, iclass 20, count 0 2006.218.08:19:02.70#ibcon#flushed, iclass 20, count 0 2006.218.08:19:02.70#ibcon#about to write, iclass 20, count 0 2006.218.08:19:02.70#ibcon#wrote, iclass 20, count 0 2006.218.08:19:02.70#ibcon#about to read 3, iclass 20, count 0 2006.218.08:19:02.72#ibcon#read 3, iclass 20, count 0 2006.218.08:19:02.72#ibcon#about to read 4, iclass 20, count 0 2006.218.08:19:02.72#ibcon#read 4, iclass 20, count 0 2006.218.08:19:02.72#ibcon#about to read 5, iclass 20, count 0 2006.218.08:19:02.72#ibcon#read 5, iclass 20, count 0 2006.218.08:19:02.72#ibcon#about to read 6, iclass 20, count 0 2006.218.08:19:02.72#ibcon#read 6, iclass 20, count 0 2006.218.08:19:02.72#ibcon#end of sib2, iclass 20, count 0 2006.218.08:19:02.72#ibcon#*mode == 0, iclass 20, count 0 2006.218.08:19:02.72#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.218.08:19:02.72#ibcon#[27=BW32\r\n] 2006.218.08:19:02.72#ibcon#*before write, iclass 20, count 0 2006.218.08:19:02.72#ibcon#enter sib2, iclass 20, count 0 2006.218.08:19:02.72#ibcon#flushed, iclass 20, count 0 2006.218.08:19:02.72#ibcon#about to write, iclass 20, count 0 2006.218.08:19:02.72#ibcon#wrote, iclass 20, count 0 2006.218.08:19:02.72#ibcon#about to read 3, iclass 20, count 0 2006.218.08:19:02.75#ibcon#read 3, iclass 20, count 0 2006.218.08:19:02.75#ibcon#about to read 4, iclass 20, count 0 2006.218.08:19:02.75#ibcon#read 4, iclass 20, count 0 2006.218.08:19:02.75#ibcon#about to read 5, iclass 20, count 0 2006.218.08:19:02.75#ibcon#read 5, iclass 20, count 0 2006.218.08:19:02.75#ibcon#about to read 6, iclass 20, count 0 2006.218.08:19:02.75#ibcon#read 6, iclass 20, count 0 2006.218.08:19:02.75#ibcon#end of sib2, iclass 20, count 0 2006.218.08:19:02.75#ibcon#*after write, iclass 20, count 0 2006.218.08:19:02.75#ibcon#*before return 0, iclass 20, count 0 2006.218.08:19:02.75#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.218.08:19:02.75#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.218.08:19:02.75#ibcon#about to clear, iclass 20 cls_cnt 0 2006.218.08:19:02.75#ibcon#cleared, iclass 20 cls_cnt 0 2006.218.08:19:02.75$4f8m12a/ifd4f 2006.218.08:19:02.75$ifd4f/lo= 2006.218.08:19:02.75$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.218.08:19:02.75$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.218.08:19:02.75$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.218.08:19:02.75$ifd4f/patch= 2006.218.08:19:02.75$ifd4f/patch=lo1,a1,a2,a3,a4 2006.218.08:19:02.75$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.218.08:19:02.75$ifd4f/patch=lo3,a5,a6,a7,a8 2006.218.08:19:02.75$4f8m12a/"form=m,16.000,1:2 2006.218.08:19:02.75$4f8m12a/"tpicd 2006.218.08:19:02.75$4f8m12a/echo=off 2006.218.08:19:02.75$4f8m12a/xlog=off 2006.218.08:19:02.75:!2006.218.08:20:30 2006.218.08:19:13.13#trakl#Source acquired 2006.218.08:19:15.13#flagr#flagr/antenna,acquired 2006.218.08:20:30.00:preob 2006.218.08:20:31.14/onsource/TRACKING 2006.218.08:20:31.14:!2006.218.08:20:40 2006.218.08:20:40.00:data_valid=on 2006.218.08:20:40.00:midob 2006.218.08:20:40.14/onsource/TRACKING 2006.218.08:20:40.14/wx/30.67,1007.6,75 2006.218.08:20:40.19/cable/+6.3862E-03 2006.218.08:20:41.28/va/01,05,usb,yes,41,43 2006.218.08:20:41.28/va/02,04,usb,yes,39,40 2006.218.08:20:41.28/va/03,04,usb,yes,37,37 2006.218.08:20:41.28/va/04,04,usb,yes,41,44 2006.218.08:20:41.28/va/05,07,usb,yes,45,48 2006.218.08:20:41.28/va/06,06,usb,yes,44,44 2006.218.08:20:41.28/va/07,06,usb,yes,45,44 2006.218.08:20:41.28/va/08,07,usb,yes,42,42 2006.218.08:20:41.51/valo/01,532.99,yes,locked 2006.218.08:20:41.51/valo/02,572.99,yes,locked 2006.218.08:20:41.51/valo/03,672.99,yes,locked 2006.218.08:20:41.51/valo/04,832.99,yes,locked 2006.218.08:20:41.51/valo/05,652.99,yes,locked 2006.218.08:20:41.51/valo/06,772.99,yes,locked 2006.218.08:20:41.51/valo/07,832.99,yes,locked 2006.218.08:20:41.51/valo/08,852.99,yes,locked 2006.218.08:20:42.60/vb/01,04,usb,yes,35,34 2006.218.08:20:42.60/vb/02,04,usb,yes,37,39 2006.218.08:20:42.60/vb/03,04,usb,yes,33,37 2006.218.08:20:42.60/vb/04,04,usb,yes,34,35 2006.218.08:20:42.60/vb/05,04,usb,yes,33,37 2006.218.08:20:42.60/vb/06,04,usb,yes,34,37 2006.218.08:20:42.60/vb/07,04,usb,yes,36,36 2006.218.08:20:42.60/vb/08,04,usb,yes,33,37 2006.218.08:20:42.84/vblo/01,632.99,yes,locked 2006.218.08:20:42.84/vblo/02,640.99,yes,locked 2006.218.08:20:42.84/vblo/03,656.99,yes,locked 2006.218.08:20:42.84/vblo/04,712.99,yes,locked 2006.218.08:20:42.84/vblo/05,744.99,yes,locked 2006.218.08:20:42.84/vblo/06,752.99,yes,locked 2006.218.08:20:42.84/vblo/07,734.99,yes,locked 2006.218.08:20:42.84/vblo/08,744.99,yes,locked 2006.218.08:20:42.99/vabw/8 2006.218.08:20:43.14/vbbw/8 2006.218.08:20:43.32/xfe/off,on,14.7 2006.218.08:20:43.71/ifatt/23,28,28,28 2006.218.08:20:44.08/fmout-gps/S +4.57E-07 2006.218.08:20:44.12:!2006.218.08:21:40 2006.218.08:21:40.01:data_valid=off 2006.218.08:21:40.01:postob 2006.218.08:21:40.26/cable/+6.3862E-03 2006.218.08:21:40.26/wx/30.64,1007.6,75 2006.218.08:21:41.07/fmout-gps/S +4.57E-07 2006.218.08:21:41.07:scan_name=218-0824,k06218,60 2006.218.08:21:41.07:source=3c418,203837.03,511912.7,2000.0,cw 2006.218.08:21:41.14#flagr#flagr/antenna,new-source 2006.218.08:21:42.14:checkk5 2006.218.08:21:42.53/chk_autoobs//k5ts1/ autoobs is running! 2006.218.08:21:42.92/chk_autoobs//k5ts2/ autoobs is running! 2006.218.08:21:43.30/chk_autoobs//k5ts3/ autoobs is running! 2006.218.08:21:43.67/chk_autoobs//k5ts4/ autoobs is running! 2006.218.08:21:44.03/chk_obsdata//k5ts1/T2180820??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.08:21:44.40/chk_obsdata//k5ts2/T2180820??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.08:21:44.77/chk_obsdata//k5ts3/T2180820??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.08:21:45.14/chk_obsdata//k5ts4/T2180820??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.08:21:45.83/k5log//k5ts1_log_newline 2006.218.08:21:46.51/k5log//k5ts2_log_newline 2006.218.08:21:47.20/k5log//k5ts3_log_newline 2006.218.08:21:47.88/k5log//k5ts4_log_newline 2006.218.08:21:47.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.218.08:21:47.91:4f8m12a=3 2006.218.08:21:47.91$4f8m12a/echo=on 2006.218.08:21:47.91$4f8m12a/pcalon 2006.218.08:21:47.91$pcalon/"no phase cal control is implemented here 2006.218.08:21:47.91$4f8m12a/"tpicd=stop 2006.218.08:21:47.91$4f8m12a/vc4f8 2006.218.08:21:47.91$vc4f8/valo=1,532.99 2006.218.08:21:47.91#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.218.08:21:47.91#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.218.08:21:47.91#ibcon#ireg 17 cls_cnt 0 2006.218.08:21:47.91#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.218.08:21:47.91#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.218.08:21:47.91#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.218.08:21:47.91#ibcon#enter wrdev, iclass 19, count 0 2006.218.08:21:47.91#ibcon#first serial, iclass 19, count 0 2006.218.08:21:47.91#ibcon#enter sib2, iclass 19, count 0 2006.218.08:21:47.91#ibcon#flushed, iclass 19, count 0 2006.218.08:21:47.91#ibcon#about to write, iclass 19, count 0 2006.218.08:21:47.91#ibcon#wrote, iclass 19, count 0 2006.218.08:21:47.91#ibcon#about to read 3, iclass 19, count 0 2006.218.08:21:47.95#ibcon#read 3, iclass 19, count 0 2006.218.08:21:47.95#ibcon#about to read 4, iclass 19, count 0 2006.218.08:21:47.95#ibcon#read 4, iclass 19, count 0 2006.218.08:21:47.95#ibcon#about to read 5, iclass 19, count 0 2006.218.08:21:47.95#ibcon#read 5, iclass 19, count 0 2006.218.08:21:47.95#ibcon#about to read 6, iclass 19, count 0 2006.218.08:21:47.95#ibcon#read 6, iclass 19, count 0 2006.218.08:21:47.95#ibcon#end of sib2, iclass 19, count 0 2006.218.08:21:47.95#ibcon#*mode == 0, iclass 19, count 0 2006.218.08:21:47.95#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.218.08:21:47.95#ibcon#[26=FRQ=01,532.99\r\n] 2006.218.08:21:47.95#ibcon#*before write, iclass 19, count 0 2006.218.08:21:47.95#ibcon#enter sib2, iclass 19, count 0 2006.218.08:21:47.95#ibcon#flushed, iclass 19, count 0 2006.218.08:21:47.95#ibcon#about to write, iclass 19, count 0 2006.218.08:21:47.95#ibcon#wrote, iclass 19, count 0 2006.218.08:21:47.95#ibcon#about to read 3, iclass 19, count 0 2006.218.08:21:48.00#ibcon#read 3, iclass 19, count 0 2006.218.08:21:48.00#ibcon#about to read 4, iclass 19, count 0 2006.218.08:21:48.00#ibcon#read 4, iclass 19, count 0 2006.218.08:21:48.00#ibcon#about to read 5, iclass 19, count 0 2006.218.08:21:48.00#ibcon#read 5, iclass 19, count 0 2006.218.08:21:48.00#ibcon#about to read 6, iclass 19, count 0 2006.218.08:21:48.00#ibcon#read 6, iclass 19, count 0 2006.218.08:21:48.00#ibcon#end of sib2, iclass 19, count 0 2006.218.08:21:48.00#ibcon#*after write, iclass 19, count 0 2006.218.08:21:48.00#ibcon#*before return 0, iclass 19, count 0 2006.218.08:21:48.00#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.218.08:21:48.00#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.218.08:21:48.00#ibcon#about to clear, iclass 19 cls_cnt 0 2006.218.08:21:48.00#ibcon#cleared, iclass 19 cls_cnt 0 2006.218.08:21:48.00$vc4f8/va=1,5 2006.218.08:21:48.00#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.218.08:21:48.00#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.218.08:21:48.00#ibcon#ireg 11 cls_cnt 2 2006.218.08:21:48.00#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.218.08:21:48.00#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.218.08:21:48.00#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.218.08:21:48.00#ibcon#enter wrdev, iclass 21, count 2 2006.218.08:21:48.00#ibcon#first serial, iclass 21, count 2 2006.218.08:21:48.00#ibcon#enter sib2, iclass 21, count 2 2006.218.08:21:48.00#ibcon#flushed, iclass 21, count 2 2006.218.08:21:48.00#ibcon#about to write, iclass 21, count 2 2006.218.08:21:48.00#ibcon#wrote, iclass 21, count 2 2006.218.08:21:48.00#ibcon#about to read 3, iclass 21, count 2 2006.218.08:21:48.02#ibcon#read 3, iclass 21, count 2 2006.218.08:21:48.02#ibcon#about to read 4, iclass 21, count 2 2006.218.08:21:48.02#ibcon#read 4, iclass 21, count 2 2006.218.08:21:48.02#ibcon#about to read 5, iclass 21, count 2 2006.218.08:21:48.02#ibcon#read 5, iclass 21, count 2 2006.218.08:21:48.02#ibcon#about to read 6, iclass 21, count 2 2006.218.08:21:48.02#ibcon#read 6, iclass 21, count 2 2006.218.08:21:48.02#ibcon#end of sib2, iclass 21, count 2 2006.218.08:21:48.02#ibcon#*mode == 0, iclass 21, count 2 2006.218.08:21:48.02#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.218.08:21:48.02#ibcon#[25=AT01-05\r\n] 2006.218.08:21:48.02#ibcon#*before write, iclass 21, count 2 2006.218.08:21:48.02#ibcon#enter sib2, iclass 21, count 2 2006.218.08:21:48.02#ibcon#flushed, iclass 21, count 2 2006.218.08:21:48.02#ibcon#about to write, iclass 21, count 2 2006.218.08:21:48.02#ibcon#wrote, iclass 21, count 2 2006.218.08:21:48.02#ibcon#about to read 3, iclass 21, count 2 2006.218.08:21:48.05#ibcon#read 3, iclass 21, count 2 2006.218.08:21:48.05#ibcon#about to read 4, iclass 21, count 2 2006.218.08:21:48.05#ibcon#read 4, iclass 21, count 2 2006.218.08:21:48.05#ibcon#about to read 5, iclass 21, count 2 2006.218.08:21:48.05#ibcon#read 5, iclass 21, count 2 2006.218.08:21:48.05#ibcon#about to read 6, iclass 21, count 2 2006.218.08:21:48.05#ibcon#read 6, iclass 21, count 2 2006.218.08:21:48.05#ibcon#end of sib2, iclass 21, count 2 2006.218.08:21:48.05#ibcon#*after write, iclass 21, count 2 2006.218.08:21:48.05#ibcon#*before return 0, iclass 21, count 2 2006.218.08:21:48.05#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.218.08:21:48.05#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.218.08:21:48.05#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.218.08:21:48.05#ibcon#ireg 7 cls_cnt 0 2006.218.08:21:48.05#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.218.08:21:48.17#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.218.08:21:48.17#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.218.08:21:48.17#ibcon#enter wrdev, iclass 21, count 0 2006.218.08:21:48.17#ibcon#first serial, iclass 21, count 0 2006.218.08:21:48.17#ibcon#enter sib2, iclass 21, count 0 2006.218.08:21:48.17#ibcon#flushed, iclass 21, count 0 2006.218.08:21:48.17#ibcon#about to write, iclass 21, count 0 2006.218.08:21:48.17#ibcon#wrote, iclass 21, count 0 2006.218.08:21:48.17#ibcon#about to read 3, iclass 21, count 0 2006.218.08:21:48.19#ibcon#read 3, iclass 21, count 0 2006.218.08:21:48.19#ibcon#about to read 4, iclass 21, count 0 2006.218.08:21:48.19#ibcon#read 4, iclass 21, count 0 2006.218.08:21:48.19#ibcon#about to read 5, iclass 21, count 0 2006.218.08:21:48.19#ibcon#read 5, iclass 21, count 0 2006.218.08:21:48.19#ibcon#about to read 6, iclass 21, count 0 2006.218.08:21:48.19#ibcon#read 6, iclass 21, count 0 2006.218.08:21:48.19#ibcon#end of sib2, iclass 21, count 0 2006.218.08:21:48.19#ibcon#*mode == 0, iclass 21, count 0 2006.218.08:21:48.19#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.218.08:21:48.19#ibcon#[25=USB\r\n] 2006.218.08:21:48.19#ibcon#*before write, iclass 21, count 0 2006.218.08:21:48.19#ibcon#enter sib2, iclass 21, count 0 2006.218.08:21:48.19#ibcon#flushed, iclass 21, count 0 2006.218.08:21:48.19#ibcon#about to write, iclass 21, count 0 2006.218.08:21:48.19#ibcon#wrote, iclass 21, count 0 2006.218.08:21:48.19#ibcon#about to read 3, iclass 21, count 0 2006.218.08:21:48.22#ibcon#read 3, iclass 21, count 0 2006.218.08:21:48.22#ibcon#about to read 4, iclass 21, count 0 2006.218.08:21:48.22#ibcon#read 4, iclass 21, count 0 2006.218.08:21:48.22#ibcon#about to read 5, iclass 21, count 0 2006.218.08:21:48.22#ibcon#read 5, iclass 21, count 0 2006.218.08:21:48.22#ibcon#about to read 6, iclass 21, count 0 2006.218.08:21:48.22#ibcon#read 6, iclass 21, count 0 2006.218.08:21:48.22#ibcon#end of sib2, iclass 21, count 0 2006.218.08:21:48.22#ibcon#*after write, iclass 21, count 0 2006.218.08:21:48.22#ibcon#*before return 0, iclass 21, count 0 2006.218.08:21:48.22#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.218.08:21:48.22#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.218.08:21:48.22#ibcon#about to clear, iclass 21 cls_cnt 0 2006.218.08:21:48.22#ibcon#cleared, iclass 21 cls_cnt 0 2006.218.08:21:48.22$vc4f8/valo=2,572.99 2006.218.08:21:48.22#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.218.08:21:48.22#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.218.08:21:48.22#ibcon#ireg 17 cls_cnt 0 2006.218.08:21:48.22#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.218.08:21:48.22#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.218.08:21:48.22#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.218.08:21:48.22#ibcon#enter wrdev, iclass 23, count 0 2006.218.08:21:48.22#ibcon#first serial, iclass 23, count 0 2006.218.08:21:48.22#ibcon#enter sib2, iclass 23, count 0 2006.218.08:21:48.22#ibcon#flushed, iclass 23, count 0 2006.218.08:21:48.22#ibcon#about to write, iclass 23, count 0 2006.218.08:21:48.22#ibcon#wrote, iclass 23, count 0 2006.218.08:21:48.22#ibcon#about to read 3, iclass 23, count 0 2006.218.08:21:48.24#ibcon#read 3, iclass 23, count 0 2006.218.08:21:48.24#ibcon#about to read 4, iclass 23, count 0 2006.218.08:21:48.24#ibcon#read 4, iclass 23, count 0 2006.218.08:21:48.24#ibcon#about to read 5, iclass 23, count 0 2006.218.08:21:48.24#ibcon#read 5, iclass 23, count 0 2006.218.08:21:48.24#ibcon#about to read 6, iclass 23, count 0 2006.218.08:21:48.24#ibcon#read 6, iclass 23, count 0 2006.218.08:21:48.24#ibcon#end of sib2, iclass 23, count 0 2006.218.08:21:48.24#ibcon#*mode == 0, iclass 23, count 0 2006.218.08:21:48.24#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.218.08:21:48.24#ibcon#[26=FRQ=02,572.99\r\n] 2006.218.08:21:48.24#ibcon#*before write, iclass 23, count 0 2006.218.08:21:48.24#ibcon#enter sib2, iclass 23, count 0 2006.218.08:21:48.24#ibcon#flushed, iclass 23, count 0 2006.218.08:21:48.24#ibcon#about to write, iclass 23, count 0 2006.218.08:21:48.24#ibcon#wrote, iclass 23, count 0 2006.218.08:21:48.24#ibcon#about to read 3, iclass 23, count 0 2006.218.08:21:48.28#ibcon#read 3, iclass 23, count 0 2006.218.08:21:48.28#ibcon#about to read 4, iclass 23, count 0 2006.218.08:21:48.28#ibcon#read 4, iclass 23, count 0 2006.218.08:21:48.28#ibcon#about to read 5, iclass 23, count 0 2006.218.08:21:48.28#ibcon#read 5, iclass 23, count 0 2006.218.08:21:48.28#ibcon#about to read 6, iclass 23, count 0 2006.218.08:21:48.28#ibcon#read 6, iclass 23, count 0 2006.218.08:21:48.28#ibcon#end of sib2, iclass 23, count 0 2006.218.08:21:48.28#ibcon#*after write, iclass 23, count 0 2006.218.08:21:48.28#ibcon#*before return 0, iclass 23, count 0 2006.218.08:21:48.28#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.218.08:21:48.28#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.218.08:21:48.28#ibcon#about to clear, iclass 23 cls_cnt 0 2006.218.08:21:48.28#ibcon#cleared, iclass 23 cls_cnt 0 2006.218.08:21:48.28$vc4f8/va=2,4 2006.218.08:21:48.28#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.218.08:21:48.28#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.218.08:21:48.28#ibcon#ireg 11 cls_cnt 2 2006.218.08:21:48.28#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.218.08:21:48.34#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.218.08:21:48.34#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.218.08:21:48.34#ibcon#enter wrdev, iclass 25, count 2 2006.218.08:21:48.34#ibcon#first serial, iclass 25, count 2 2006.218.08:21:48.34#ibcon#enter sib2, iclass 25, count 2 2006.218.08:21:48.34#ibcon#flushed, iclass 25, count 2 2006.218.08:21:48.34#ibcon#about to write, iclass 25, count 2 2006.218.08:21:48.34#ibcon#wrote, iclass 25, count 2 2006.218.08:21:48.34#ibcon#about to read 3, iclass 25, count 2 2006.218.08:21:48.36#ibcon#read 3, iclass 25, count 2 2006.218.08:21:48.36#ibcon#about to read 4, iclass 25, count 2 2006.218.08:21:48.36#ibcon#read 4, iclass 25, count 2 2006.218.08:21:48.36#ibcon#about to read 5, iclass 25, count 2 2006.218.08:21:48.36#ibcon#read 5, iclass 25, count 2 2006.218.08:21:48.36#ibcon#about to read 6, iclass 25, count 2 2006.218.08:21:48.36#ibcon#read 6, iclass 25, count 2 2006.218.08:21:48.36#ibcon#end of sib2, iclass 25, count 2 2006.218.08:21:48.36#ibcon#*mode == 0, iclass 25, count 2 2006.218.08:21:48.36#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.218.08:21:48.36#ibcon#[25=AT02-04\r\n] 2006.218.08:21:48.36#ibcon#*before write, iclass 25, count 2 2006.218.08:21:48.36#ibcon#enter sib2, iclass 25, count 2 2006.218.08:21:48.36#ibcon#flushed, iclass 25, count 2 2006.218.08:21:48.36#ibcon#about to write, iclass 25, count 2 2006.218.08:21:48.36#ibcon#wrote, iclass 25, count 2 2006.218.08:21:48.36#ibcon#about to read 3, iclass 25, count 2 2006.218.08:21:48.39#ibcon#read 3, iclass 25, count 2 2006.218.08:21:48.39#ibcon#about to read 4, iclass 25, count 2 2006.218.08:21:48.39#ibcon#read 4, iclass 25, count 2 2006.218.08:21:48.39#ibcon#about to read 5, iclass 25, count 2 2006.218.08:21:48.39#ibcon#read 5, iclass 25, count 2 2006.218.08:21:48.39#ibcon#about to read 6, iclass 25, count 2 2006.218.08:21:48.39#ibcon#read 6, iclass 25, count 2 2006.218.08:21:48.39#ibcon#end of sib2, iclass 25, count 2 2006.218.08:21:48.39#ibcon#*after write, iclass 25, count 2 2006.218.08:21:48.39#ibcon#*before return 0, iclass 25, count 2 2006.218.08:21:48.39#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.218.08:21:48.39#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.218.08:21:48.39#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.218.08:21:48.39#ibcon#ireg 7 cls_cnt 0 2006.218.08:21:48.39#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.218.08:21:48.51#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.218.08:21:48.51#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.218.08:21:48.51#ibcon#enter wrdev, iclass 25, count 0 2006.218.08:21:48.51#ibcon#first serial, iclass 25, count 0 2006.218.08:21:48.51#ibcon#enter sib2, iclass 25, count 0 2006.218.08:21:48.51#ibcon#flushed, iclass 25, count 0 2006.218.08:21:48.51#ibcon#about to write, iclass 25, count 0 2006.218.08:21:48.51#ibcon#wrote, iclass 25, count 0 2006.218.08:21:48.51#ibcon#about to read 3, iclass 25, count 0 2006.218.08:21:48.53#ibcon#read 3, iclass 25, count 0 2006.218.08:21:48.53#ibcon#about to read 4, iclass 25, count 0 2006.218.08:21:48.53#ibcon#read 4, iclass 25, count 0 2006.218.08:21:48.53#ibcon#about to read 5, iclass 25, count 0 2006.218.08:21:48.53#ibcon#read 5, iclass 25, count 0 2006.218.08:21:48.53#ibcon#about to read 6, iclass 25, count 0 2006.218.08:21:48.53#ibcon#read 6, iclass 25, count 0 2006.218.08:21:48.53#ibcon#end of sib2, iclass 25, count 0 2006.218.08:21:48.53#ibcon#*mode == 0, iclass 25, count 0 2006.218.08:21:48.53#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.218.08:21:48.53#ibcon#[25=USB\r\n] 2006.218.08:21:48.53#ibcon#*before write, iclass 25, count 0 2006.218.08:21:48.53#ibcon#enter sib2, iclass 25, count 0 2006.218.08:21:48.53#ibcon#flushed, iclass 25, count 0 2006.218.08:21:48.53#ibcon#about to write, iclass 25, count 0 2006.218.08:21:48.53#ibcon#wrote, iclass 25, count 0 2006.218.08:21:48.53#ibcon#about to read 3, iclass 25, count 0 2006.218.08:21:48.56#ibcon#read 3, iclass 25, count 0 2006.218.08:21:48.56#ibcon#about to read 4, iclass 25, count 0 2006.218.08:21:48.56#ibcon#read 4, iclass 25, count 0 2006.218.08:21:48.56#ibcon#about to read 5, iclass 25, count 0 2006.218.08:21:48.56#ibcon#read 5, iclass 25, count 0 2006.218.08:21:48.56#ibcon#about to read 6, iclass 25, count 0 2006.218.08:21:48.56#ibcon#read 6, iclass 25, count 0 2006.218.08:21:48.56#ibcon#end of sib2, iclass 25, count 0 2006.218.08:21:48.56#ibcon#*after write, iclass 25, count 0 2006.218.08:21:48.56#ibcon#*before return 0, iclass 25, count 0 2006.218.08:21:48.56#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.218.08:21:48.56#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.218.08:21:48.56#ibcon#about to clear, iclass 25 cls_cnt 0 2006.218.08:21:48.56#ibcon#cleared, iclass 25 cls_cnt 0 2006.218.08:21:48.56$vc4f8/valo=3,672.99 2006.218.08:21:48.56#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.218.08:21:48.56#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.218.08:21:48.56#ibcon#ireg 17 cls_cnt 0 2006.218.08:21:48.56#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.218.08:21:48.56#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.218.08:21:48.56#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.218.08:21:48.56#ibcon#enter wrdev, iclass 27, count 0 2006.218.08:21:48.56#ibcon#first serial, iclass 27, count 0 2006.218.08:21:48.56#ibcon#enter sib2, iclass 27, count 0 2006.218.08:21:48.56#ibcon#flushed, iclass 27, count 0 2006.218.08:21:48.56#ibcon#about to write, iclass 27, count 0 2006.218.08:21:48.56#ibcon#wrote, iclass 27, count 0 2006.218.08:21:48.56#ibcon#about to read 3, iclass 27, count 0 2006.218.08:21:48.58#ibcon#read 3, iclass 27, count 0 2006.218.08:21:48.58#ibcon#about to read 4, iclass 27, count 0 2006.218.08:21:48.58#ibcon#read 4, iclass 27, count 0 2006.218.08:21:48.58#ibcon#about to read 5, iclass 27, count 0 2006.218.08:21:48.58#ibcon#read 5, iclass 27, count 0 2006.218.08:21:48.58#ibcon#about to read 6, iclass 27, count 0 2006.218.08:21:48.58#ibcon#read 6, iclass 27, count 0 2006.218.08:21:48.58#ibcon#end of sib2, iclass 27, count 0 2006.218.08:21:48.58#ibcon#*mode == 0, iclass 27, count 0 2006.218.08:21:48.58#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.218.08:21:48.58#ibcon#[26=FRQ=03,672.99\r\n] 2006.218.08:21:48.58#ibcon#*before write, iclass 27, count 0 2006.218.08:21:48.58#ibcon#enter sib2, iclass 27, count 0 2006.218.08:21:48.58#ibcon#flushed, iclass 27, count 0 2006.218.08:21:48.58#ibcon#about to write, iclass 27, count 0 2006.218.08:21:48.58#ibcon#wrote, iclass 27, count 0 2006.218.08:21:48.58#ibcon#about to read 3, iclass 27, count 0 2006.218.08:21:48.62#ibcon#read 3, iclass 27, count 0 2006.218.08:21:48.62#ibcon#about to read 4, iclass 27, count 0 2006.218.08:21:48.62#ibcon#read 4, iclass 27, count 0 2006.218.08:21:48.62#ibcon#about to read 5, iclass 27, count 0 2006.218.08:21:48.62#ibcon#read 5, iclass 27, count 0 2006.218.08:21:48.62#ibcon#about to read 6, iclass 27, count 0 2006.218.08:21:48.62#ibcon#read 6, iclass 27, count 0 2006.218.08:21:48.62#ibcon#end of sib2, iclass 27, count 0 2006.218.08:21:48.62#ibcon#*after write, iclass 27, count 0 2006.218.08:21:48.62#ibcon#*before return 0, iclass 27, count 0 2006.218.08:21:48.62#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.218.08:21:48.62#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.218.08:21:48.62#ibcon#about to clear, iclass 27 cls_cnt 0 2006.218.08:21:48.62#ibcon#cleared, iclass 27 cls_cnt 0 2006.218.08:21:48.62$vc4f8/va=3,4 2006.218.08:21:48.62#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.218.08:21:48.62#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.218.08:21:48.62#ibcon#ireg 11 cls_cnt 2 2006.218.08:21:48.62#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.218.08:21:48.68#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.218.08:21:48.68#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.218.08:21:48.68#ibcon#enter wrdev, iclass 29, count 2 2006.218.08:21:48.68#ibcon#first serial, iclass 29, count 2 2006.218.08:21:48.68#ibcon#enter sib2, iclass 29, count 2 2006.218.08:21:48.68#ibcon#flushed, iclass 29, count 2 2006.218.08:21:48.68#ibcon#about to write, iclass 29, count 2 2006.218.08:21:48.68#ibcon#wrote, iclass 29, count 2 2006.218.08:21:48.68#ibcon#about to read 3, iclass 29, count 2 2006.218.08:21:48.70#ibcon#read 3, iclass 29, count 2 2006.218.08:21:48.70#ibcon#about to read 4, iclass 29, count 2 2006.218.08:21:48.70#ibcon#read 4, iclass 29, count 2 2006.218.08:21:48.70#ibcon#about to read 5, iclass 29, count 2 2006.218.08:21:48.70#ibcon#read 5, iclass 29, count 2 2006.218.08:21:48.70#ibcon#about to read 6, iclass 29, count 2 2006.218.08:21:48.70#ibcon#read 6, iclass 29, count 2 2006.218.08:21:48.70#ibcon#end of sib2, iclass 29, count 2 2006.218.08:21:48.70#ibcon#*mode == 0, iclass 29, count 2 2006.218.08:21:48.70#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.218.08:21:48.70#ibcon#[25=AT03-04\r\n] 2006.218.08:21:48.70#ibcon#*before write, iclass 29, count 2 2006.218.08:21:48.70#ibcon#enter sib2, iclass 29, count 2 2006.218.08:21:48.70#ibcon#flushed, iclass 29, count 2 2006.218.08:21:48.70#ibcon#about to write, iclass 29, count 2 2006.218.08:21:48.70#ibcon#wrote, iclass 29, count 2 2006.218.08:21:48.70#ibcon#about to read 3, iclass 29, count 2 2006.218.08:21:48.73#ibcon#read 3, iclass 29, count 2 2006.218.08:21:48.73#ibcon#about to read 4, iclass 29, count 2 2006.218.08:21:48.73#ibcon#read 4, iclass 29, count 2 2006.218.08:21:48.73#ibcon#about to read 5, iclass 29, count 2 2006.218.08:21:48.73#ibcon#read 5, iclass 29, count 2 2006.218.08:21:48.73#ibcon#about to read 6, iclass 29, count 2 2006.218.08:21:48.73#ibcon#read 6, iclass 29, count 2 2006.218.08:21:48.73#ibcon#end of sib2, iclass 29, count 2 2006.218.08:21:48.73#ibcon#*after write, iclass 29, count 2 2006.218.08:21:48.73#ibcon#*before return 0, iclass 29, count 2 2006.218.08:21:48.73#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.218.08:21:48.73#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.218.08:21:48.73#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.218.08:21:48.73#ibcon#ireg 7 cls_cnt 0 2006.218.08:21:48.73#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.218.08:21:48.85#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.218.08:21:48.85#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.218.08:21:48.85#ibcon#enter wrdev, iclass 29, count 0 2006.218.08:21:48.85#ibcon#first serial, iclass 29, count 0 2006.218.08:21:48.85#ibcon#enter sib2, iclass 29, count 0 2006.218.08:21:48.85#ibcon#flushed, iclass 29, count 0 2006.218.08:21:48.85#ibcon#about to write, iclass 29, count 0 2006.218.08:21:48.85#ibcon#wrote, iclass 29, count 0 2006.218.08:21:48.85#ibcon#about to read 3, iclass 29, count 0 2006.218.08:21:48.87#ibcon#read 3, iclass 29, count 0 2006.218.08:21:48.87#ibcon#about to read 4, iclass 29, count 0 2006.218.08:21:48.87#ibcon#read 4, iclass 29, count 0 2006.218.08:21:48.87#ibcon#about to read 5, iclass 29, count 0 2006.218.08:21:48.87#ibcon#read 5, iclass 29, count 0 2006.218.08:21:48.87#ibcon#about to read 6, iclass 29, count 0 2006.218.08:21:48.87#ibcon#read 6, iclass 29, count 0 2006.218.08:21:48.87#ibcon#end of sib2, iclass 29, count 0 2006.218.08:21:48.87#ibcon#*mode == 0, iclass 29, count 0 2006.218.08:21:48.87#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.218.08:21:48.87#ibcon#[25=USB\r\n] 2006.218.08:21:48.87#ibcon#*before write, iclass 29, count 0 2006.218.08:21:48.87#ibcon#enter sib2, iclass 29, count 0 2006.218.08:21:48.87#ibcon#flushed, iclass 29, count 0 2006.218.08:21:48.87#ibcon#about to write, iclass 29, count 0 2006.218.08:21:48.87#ibcon#wrote, iclass 29, count 0 2006.218.08:21:48.87#ibcon#about to read 3, iclass 29, count 0 2006.218.08:21:48.90#ibcon#read 3, iclass 29, count 0 2006.218.08:21:48.90#ibcon#about to read 4, iclass 29, count 0 2006.218.08:21:48.90#ibcon#read 4, iclass 29, count 0 2006.218.08:21:48.90#ibcon#about to read 5, iclass 29, count 0 2006.218.08:21:48.90#ibcon#read 5, iclass 29, count 0 2006.218.08:21:48.90#ibcon#about to read 6, iclass 29, count 0 2006.218.08:21:48.90#ibcon#read 6, iclass 29, count 0 2006.218.08:21:48.90#ibcon#end of sib2, iclass 29, count 0 2006.218.08:21:48.90#ibcon#*after write, iclass 29, count 0 2006.218.08:21:48.90#ibcon#*before return 0, iclass 29, count 0 2006.218.08:21:48.90#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.218.08:21:48.90#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.218.08:21:48.90#ibcon#about to clear, iclass 29 cls_cnt 0 2006.218.08:21:48.90#ibcon#cleared, iclass 29 cls_cnt 0 2006.218.08:21:48.90$vc4f8/valo=4,832.99 2006.218.08:21:48.90#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.218.08:21:48.90#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.218.08:21:48.90#ibcon#ireg 17 cls_cnt 0 2006.218.08:21:48.90#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.218.08:21:48.90#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.218.08:21:48.90#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.218.08:21:48.90#ibcon#enter wrdev, iclass 31, count 0 2006.218.08:21:48.90#ibcon#first serial, iclass 31, count 0 2006.218.08:21:48.90#ibcon#enter sib2, iclass 31, count 0 2006.218.08:21:48.90#ibcon#flushed, iclass 31, count 0 2006.218.08:21:48.90#ibcon#about to write, iclass 31, count 0 2006.218.08:21:48.90#ibcon#wrote, iclass 31, count 0 2006.218.08:21:48.90#ibcon#about to read 3, iclass 31, count 0 2006.218.08:21:48.92#ibcon#read 3, iclass 31, count 0 2006.218.08:21:48.92#ibcon#about to read 4, iclass 31, count 0 2006.218.08:21:48.92#ibcon#read 4, iclass 31, count 0 2006.218.08:21:48.92#ibcon#about to read 5, iclass 31, count 0 2006.218.08:21:48.92#ibcon#read 5, iclass 31, count 0 2006.218.08:21:48.92#ibcon#about to read 6, iclass 31, count 0 2006.218.08:21:48.92#ibcon#read 6, iclass 31, count 0 2006.218.08:21:48.92#ibcon#end of sib2, iclass 31, count 0 2006.218.08:21:48.92#ibcon#*mode == 0, iclass 31, count 0 2006.218.08:21:48.92#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.218.08:21:48.92#ibcon#[26=FRQ=04,832.99\r\n] 2006.218.08:21:48.92#ibcon#*before write, iclass 31, count 0 2006.218.08:21:48.92#ibcon#enter sib2, iclass 31, count 0 2006.218.08:21:48.92#ibcon#flushed, iclass 31, count 0 2006.218.08:21:48.92#ibcon#about to write, iclass 31, count 0 2006.218.08:21:48.92#ibcon#wrote, iclass 31, count 0 2006.218.08:21:48.92#ibcon#about to read 3, iclass 31, count 0 2006.218.08:21:48.96#ibcon#read 3, iclass 31, count 0 2006.218.08:21:48.96#ibcon#about to read 4, iclass 31, count 0 2006.218.08:21:48.96#ibcon#read 4, iclass 31, count 0 2006.218.08:21:48.96#ibcon#about to read 5, iclass 31, count 0 2006.218.08:21:48.96#ibcon#read 5, iclass 31, count 0 2006.218.08:21:48.96#ibcon#about to read 6, iclass 31, count 0 2006.218.08:21:48.96#ibcon#read 6, iclass 31, count 0 2006.218.08:21:48.96#ibcon#end of sib2, iclass 31, count 0 2006.218.08:21:48.96#ibcon#*after write, iclass 31, count 0 2006.218.08:21:48.96#ibcon#*before return 0, iclass 31, count 0 2006.218.08:21:48.96#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.218.08:21:48.96#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.218.08:21:48.96#ibcon#about to clear, iclass 31 cls_cnt 0 2006.218.08:21:48.96#ibcon#cleared, iclass 31 cls_cnt 0 2006.218.08:21:48.96$vc4f8/va=4,4 2006.218.08:21:48.96#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.218.08:21:48.96#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.218.08:21:48.96#ibcon#ireg 11 cls_cnt 2 2006.218.08:21:48.96#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.218.08:21:49.02#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.218.08:21:49.02#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.218.08:21:49.02#ibcon#enter wrdev, iclass 33, count 2 2006.218.08:21:49.02#ibcon#first serial, iclass 33, count 2 2006.218.08:21:49.02#ibcon#enter sib2, iclass 33, count 2 2006.218.08:21:49.02#ibcon#flushed, iclass 33, count 2 2006.218.08:21:49.02#ibcon#about to write, iclass 33, count 2 2006.218.08:21:49.02#ibcon#wrote, iclass 33, count 2 2006.218.08:21:49.02#ibcon#about to read 3, iclass 33, count 2 2006.218.08:21:49.04#ibcon#read 3, iclass 33, count 2 2006.218.08:21:49.04#ibcon#about to read 4, iclass 33, count 2 2006.218.08:21:49.04#ibcon#read 4, iclass 33, count 2 2006.218.08:21:49.04#ibcon#about to read 5, iclass 33, count 2 2006.218.08:21:49.04#ibcon#read 5, iclass 33, count 2 2006.218.08:21:49.04#ibcon#about to read 6, iclass 33, count 2 2006.218.08:21:49.04#ibcon#read 6, iclass 33, count 2 2006.218.08:21:49.04#ibcon#end of sib2, iclass 33, count 2 2006.218.08:21:49.04#ibcon#*mode == 0, iclass 33, count 2 2006.218.08:21:49.04#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.218.08:21:49.04#ibcon#[25=AT04-04\r\n] 2006.218.08:21:49.04#ibcon#*before write, iclass 33, count 2 2006.218.08:21:49.04#ibcon#enter sib2, iclass 33, count 2 2006.218.08:21:49.04#ibcon#flushed, iclass 33, count 2 2006.218.08:21:49.04#ibcon#about to write, iclass 33, count 2 2006.218.08:21:49.04#ibcon#wrote, iclass 33, count 2 2006.218.08:21:49.04#ibcon#about to read 3, iclass 33, count 2 2006.218.08:21:49.07#ibcon#read 3, iclass 33, count 2 2006.218.08:21:49.07#ibcon#about to read 4, iclass 33, count 2 2006.218.08:21:49.07#ibcon#read 4, iclass 33, count 2 2006.218.08:21:49.07#ibcon#about to read 5, iclass 33, count 2 2006.218.08:21:49.07#ibcon#read 5, iclass 33, count 2 2006.218.08:21:49.07#ibcon#about to read 6, iclass 33, count 2 2006.218.08:21:49.07#ibcon#read 6, iclass 33, count 2 2006.218.08:21:49.07#ibcon#end of sib2, iclass 33, count 2 2006.218.08:21:49.07#ibcon#*after write, iclass 33, count 2 2006.218.08:21:49.07#ibcon#*before return 0, iclass 33, count 2 2006.218.08:21:49.07#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.218.08:21:49.07#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.218.08:21:49.07#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.218.08:21:49.07#ibcon#ireg 7 cls_cnt 0 2006.218.08:21:49.07#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.218.08:21:49.19#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.218.08:21:49.19#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.218.08:21:49.19#ibcon#enter wrdev, iclass 33, count 0 2006.218.08:21:49.19#ibcon#first serial, iclass 33, count 0 2006.218.08:21:49.19#ibcon#enter sib2, iclass 33, count 0 2006.218.08:21:49.19#ibcon#flushed, iclass 33, count 0 2006.218.08:21:49.19#ibcon#about to write, iclass 33, count 0 2006.218.08:21:49.19#ibcon#wrote, iclass 33, count 0 2006.218.08:21:49.19#ibcon#about to read 3, iclass 33, count 0 2006.218.08:21:49.21#ibcon#read 3, iclass 33, count 0 2006.218.08:21:49.21#ibcon#about to read 4, iclass 33, count 0 2006.218.08:21:49.21#ibcon#read 4, iclass 33, count 0 2006.218.08:21:49.21#ibcon#about to read 5, iclass 33, count 0 2006.218.08:21:49.21#ibcon#read 5, iclass 33, count 0 2006.218.08:21:49.21#ibcon#about to read 6, iclass 33, count 0 2006.218.08:21:49.21#ibcon#read 6, iclass 33, count 0 2006.218.08:21:49.21#ibcon#end of sib2, iclass 33, count 0 2006.218.08:21:49.21#ibcon#*mode == 0, iclass 33, count 0 2006.218.08:21:49.21#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.218.08:21:49.21#ibcon#[25=USB\r\n] 2006.218.08:21:49.21#ibcon#*before write, iclass 33, count 0 2006.218.08:21:49.21#ibcon#enter sib2, iclass 33, count 0 2006.218.08:21:49.21#ibcon#flushed, iclass 33, count 0 2006.218.08:21:49.21#ibcon#about to write, iclass 33, count 0 2006.218.08:21:49.21#ibcon#wrote, iclass 33, count 0 2006.218.08:21:49.21#ibcon#about to read 3, iclass 33, count 0 2006.218.08:21:49.24#ibcon#read 3, iclass 33, count 0 2006.218.08:21:49.24#ibcon#about to read 4, iclass 33, count 0 2006.218.08:21:49.24#ibcon#read 4, iclass 33, count 0 2006.218.08:21:49.24#ibcon#about to read 5, iclass 33, count 0 2006.218.08:21:49.24#ibcon#read 5, iclass 33, count 0 2006.218.08:21:49.24#ibcon#about to read 6, iclass 33, count 0 2006.218.08:21:49.24#ibcon#read 6, iclass 33, count 0 2006.218.08:21:49.24#ibcon#end of sib2, iclass 33, count 0 2006.218.08:21:49.24#ibcon#*after write, iclass 33, count 0 2006.218.08:21:49.24#ibcon#*before return 0, iclass 33, count 0 2006.218.08:21:49.24#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.218.08:21:49.24#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.218.08:21:49.24#ibcon#about to clear, iclass 33 cls_cnt 0 2006.218.08:21:49.24#ibcon#cleared, iclass 33 cls_cnt 0 2006.218.08:21:49.24$vc4f8/valo=5,652.99 2006.218.08:21:49.24#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.218.08:21:49.24#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.218.08:21:49.24#ibcon#ireg 17 cls_cnt 0 2006.218.08:21:49.24#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.218.08:21:49.24#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.218.08:21:49.24#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.218.08:21:49.24#ibcon#enter wrdev, iclass 35, count 0 2006.218.08:21:49.24#ibcon#first serial, iclass 35, count 0 2006.218.08:21:49.24#ibcon#enter sib2, iclass 35, count 0 2006.218.08:21:49.24#ibcon#flushed, iclass 35, count 0 2006.218.08:21:49.24#ibcon#about to write, iclass 35, count 0 2006.218.08:21:49.24#ibcon#wrote, iclass 35, count 0 2006.218.08:21:49.24#ibcon#about to read 3, iclass 35, count 0 2006.218.08:21:49.26#ibcon#read 3, iclass 35, count 0 2006.218.08:21:49.26#ibcon#about to read 4, iclass 35, count 0 2006.218.08:21:49.26#ibcon#read 4, iclass 35, count 0 2006.218.08:21:49.26#ibcon#about to read 5, iclass 35, count 0 2006.218.08:21:49.26#ibcon#read 5, iclass 35, count 0 2006.218.08:21:49.26#ibcon#about to read 6, iclass 35, count 0 2006.218.08:21:49.26#ibcon#read 6, iclass 35, count 0 2006.218.08:21:49.26#ibcon#end of sib2, iclass 35, count 0 2006.218.08:21:49.26#ibcon#*mode == 0, iclass 35, count 0 2006.218.08:21:49.26#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.218.08:21:49.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.218.08:21:49.26#ibcon#*before write, iclass 35, count 0 2006.218.08:21:49.26#ibcon#enter sib2, iclass 35, count 0 2006.218.08:21:49.26#ibcon#flushed, iclass 35, count 0 2006.218.08:21:49.26#ibcon#about to write, iclass 35, count 0 2006.218.08:21:49.26#ibcon#wrote, iclass 35, count 0 2006.218.08:21:49.26#ibcon#about to read 3, iclass 35, count 0 2006.218.08:21:49.30#ibcon#read 3, iclass 35, count 0 2006.218.08:21:49.30#ibcon#about to read 4, iclass 35, count 0 2006.218.08:21:49.30#ibcon#read 4, iclass 35, count 0 2006.218.08:21:49.30#ibcon#about to read 5, iclass 35, count 0 2006.218.08:21:49.30#ibcon#read 5, iclass 35, count 0 2006.218.08:21:49.30#ibcon#about to read 6, iclass 35, count 0 2006.218.08:21:49.30#ibcon#read 6, iclass 35, count 0 2006.218.08:21:49.30#ibcon#end of sib2, iclass 35, count 0 2006.218.08:21:49.30#ibcon#*after write, iclass 35, count 0 2006.218.08:21:49.30#ibcon#*before return 0, iclass 35, count 0 2006.218.08:21:49.30#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.218.08:21:49.30#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.218.08:21:49.30#ibcon#about to clear, iclass 35 cls_cnt 0 2006.218.08:21:49.30#ibcon#cleared, iclass 35 cls_cnt 0 2006.218.08:21:49.30$vc4f8/va=5,7 2006.218.08:21:49.30#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.218.08:21:49.30#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.218.08:21:49.30#ibcon#ireg 11 cls_cnt 2 2006.218.08:21:49.30#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.218.08:21:49.36#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.218.08:21:49.36#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.218.08:21:49.36#ibcon#enter wrdev, iclass 37, count 2 2006.218.08:21:49.36#ibcon#first serial, iclass 37, count 2 2006.218.08:21:49.36#ibcon#enter sib2, iclass 37, count 2 2006.218.08:21:49.36#ibcon#flushed, iclass 37, count 2 2006.218.08:21:49.36#ibcon#about to write, iclass 37, count 2 2006.218.08:21:49.36#ibcon#wrote, iclass 37, count 2 2006.218.08:21:49.36#ibcon#about to read 3, iclass 37, count 2 2006.218.08:21:49.38#ibcon#read 3, iclass 37, count 2 2006.218.08:21:49.38#ibcon#about to read 4, iclass 37, count 2 2006.218.08:21:49.38#ibcon#read 4, iclass 37, count 2 2006.218.08:21:49.38#ibcon#about to read 5, iclass 37, count 2 2006.218.08:21:49.38#ibcon#read 5, iclass 37, count 2 2006.218.08:21:49.38#ibcon#about to read 6, iclass 37, count 2 2006.218.08:21:49.38#ibcon#read 6, iclass 37, count 2 2006.218.08:21:49.38#ibcon#end of sib2, iclass 37, count 2 2006.218.08:21:49.38#ibcon#*mode == 0, iclass 37, count 2 2006.218.08:21:49.38#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.218.08:21:49.38#ibcon#[25=AT05-07\r\n] 2006.218.08:21:49.38#ibcon#*before write, iclass 37, count 2 2006.218.08:21:49.38#ibcon#enter sib2, iclass 37, count 2 2006.218.08:21:49.38#ibcon#flushed, iclass 37, count 2 2006.218.08:21:49.38#ibcon#about to write, iclass 37, count 2 2006.218.08:21:49.38#ibcon#wrote, iclass 37, count 2 2006.218.08:21:49.38#ibcon#about to read 3, iclass 37, count 2 2006.218.08:21:49.41#ibcon#read 3, iclass 37, count 2 2006.218.08:21:49.41#ibcon#about to read 4, iclass 37, count 2 2006.218.08:21:49.41#ibcon#read 4, iclass 37, count 2 2006.218.08:21:49.41#ibcon#about to read 5, iclass 37, count 2 2006.218.08:21:49.41#ibcon#read 5, iclass 37, count 2 2006.218.08:21:49.41#ibcon#about to read 6, iclass 37, count 2 2006.218.08:21:49.41#ibcon#read 6, iclass 37, count 2 2006.218.08:21:49.41#ibcon#end of sib2, iclass 37, count 2 2006.218.08:21:49.41#ibcon#*after write, iclass 37, count 2 2006.218.08:21:49.41#ibcon#*before return 0, iclass 37, count 2 2006.218.08:21:49.41#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.218.08:21:49.41#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.218.08:21:49.41#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.218.08:21:49.41#ibcon#ireg 7 cls_cnt 0 2006.218.08:21:49.41#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.218.08:21:49.53#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.218.08:21:49.53#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.218.08:21:49.53#ibcon#enter wrdev, iclass 37, count 0 2006.218.08:21:49.53#ibcon#first serial, iclass 37, count 0 2006.218.08:21:49.53#ibcon#enter sib2, iclass 37, count 0 2006.218.08:21:49.53#ibcon#flushed, iclass 37, count 0 2006.218.08:21:49.53#ibcon#about to write, iclass 37, count 0 2006.218.08:21:49.53#ibcon#wrote, iclass 37, count 0 2006.218.08:21:49.53#ibcon#about to read 3, iclass 37, count 0 2006.218.08:21:49.55#ibcon#read 3, iclass 37, count 0 2006.218.08:21:49.55#ibcon#about to read 4, iclass 37, count 0 2006.218.08:21:49.55#ibcon#read 4, iclass 37, count 0 2006.218.08:21:49.55#ibcon#about to read 5, iclass 37, count 0 2006.218.08:21:49.55#ibcon#read 5, iclass 37, count 0 2006.218.08:21:49.55#ibcon#about to read 6, iclass 37, count 0 2006.218.08:21:49.55#ibcon#read 6, iclass 37, count 0 2006.218.08:21:49.55#ibcon#end of sib2, iclass 37, count 0 2006.218.08:21:49.55#ibcon#*mode == 0, iclass 37, count 0 2006.218.08:21:49.55#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.218.08:21:49.55#ibcon#[25=USB\r\n] 2006.218.08:21:49.55#ibcon#*before write, iclass 37, count 0 2006.218.08:21:49.55#ibcon#enter sib2, iclass 37, count 0 2006.218.08:21:49.55#ibcon#flushed, iclass 37, count 0 2006.218.08:21:49.55#ibcon#about to write, iclass 37, count 0 2006.218.08:21:49.55#ibcon#wrote, iclass 37, count 0 2006.218.08:21:49.55#ibcon#about to read 3, iclass 37, count 0 2006.218.08:21:49.58#ibcon#read 3, iclass 37, count 0 2006.218.08:21:49.58#ibcon#about to read 4, iclass 37, count 0 2006.218.08:21:49.58#ibcon#read 4, iclass 37, count 0 2006.218.08:21:49.58#ibcon#about to read 5, iclass 37, count 0 2006.218.08:21:49.58#ibcon#read 5, iclass 37, count 0 2006.218.08:21:49.58#ibcon#about to read 6, iclass 37, count 0 2006.218.08:21:49.58#ibcon#read 6, iclass 37, count 0 2006.218.08:21:49.58#ibcon#end of sib2, iclass 37, count 0 2006.218.08:21:49.58#ibcon#*after write, iclass 37, count 0 2006.218.08:21:49.58#ibcon#*before return 0, iclass 37, count 0 2006.218.08:21:49.58#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.218.08:21:49.58#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.218.08:21:49.58#ibcon#about to clear, iclass 37 cls_cnt 0 2006.218.08:21:49.58#ibcon#cleared, iclass 37 cls_cnt 0 2006.218.08:21:49.58$vc4f8/valo=6,772.99 2006.218.08:21:49.58#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.218.08:21:49.58#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.218.08:21:49.58#ibcon#ireg 17 cls_cnt 0 2006.218.08:21:49.58#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.218.08:21:49.58#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.218.08:21:49.58#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.218.08:21:49.58#ibcon#enter wrdev, iclass 39, count 0 2006.218.08:21:49.58#ibcon#first serial, iclass 39, count 0 2006.218.08:21:49.58#ibcon#enter sib2, iclass 39, count 0 2006.218.08:21:49.58#ibcon#flushed, iclass 39, count 0 2006.218.08:21:49.58#ibcon#about to write, iclass 39, count 0 2006.218.08:21:49.58#ibcon#wrote, iclass 39, count 0 2006.218.08:21:49.58#ibcon#about to read 3, iclass 39, count 0 2006.218.08:21:49.60#ibcon#read 3, iclass 39, count 0 2006.218.08:21:49.60#ibcon#about to read 4, iclass 39, count 0 2006.218.08:21:49.60#ibcon#read 4, iclass 39, count 0 2006.218.08:21:49.60#ibcon#about to read 5, iclass 39, count 0 2006.218.08:21:49.60#ibcon#read 5, iclass 39, count 0 2006.218.08:21:49.60#ibcon#about to read 6, iclass 39, count 0 2006.218.08:21:49.60#ibcon#read 6, iclass 39, count 0 2006.218.08:21:49.60#ibcon#end of sib2, iclass 39, count 0 2006.218.08:21:49.60#ibcon#*mode == 0, iclass 39, count 0 2006.218.08:21:49.60#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.218.08:21:49.60#ibcon#[26=FRQ=06,772.99\r\n] 2006.218.08:21:49.60#ibcon#*before write, iclass 39, count 0 2006.218.08:21:49.60#ibcon#enter sib2, iclass 39, count 0 2006.218.08:21:49.60#ibcon#flushed, iclass 39, count 0 2006.218.08:21:49.60#ibcon#about to write, iclass 39, count 0 2006.218.08:21:49.60#ibcon#wrote, iclass 39, count 0 2006.218.08:21:49.60#ibcon#about to read 3, iclass 39, count 0 2006.218.08:21:49.64#ibcon#read 3, iclass 39, count 0 2006.218.08:21:49.64#ibcon#about to read 4, iclass 39, count 0 2006.218.08:21:49.64#ibcon#read 4, iclass 39, count 0 2006.218.08:21:49.64#ibcon#about to read 5, iclass 39, count 0 2006.218.08:21:49.64#ibcon#read 5, iclass 39, count 0 2006.218.08:21:49.64#ibcon#about to read 6, iclass 39, count 0 2006.218.08:21:49.64#ibcon#read 6, iclass 39, count 0 2006.218.08:21:49.64#ibcon#end of sib2, iclass 39, count 0 2006.218.08:21:49.64#ibcon#*after write, iclass 39, count 0 2006.218.08:21:49.64#ibcon#*before return 0, iclass 39, count 0 2006.218.08:21:49.64#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.218.08:21:49.64#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.218.08:21:49.64#ibcon#about to clear, iclass 39 cls_cnt 0 2006.218.08:21:49.64#ibcon#cleared, iclass 39 cls_cnt 0 2006.218.08:21:49.64$vc4f8/va=6,6 2006.218.08:21:49.64#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.218.08:21:49.64#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.218.08:21:49.64#ibcon#ireg 11 cls_cnt 2 2006.218.08:21:49.64#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.218.08:21:49.70#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.218.08:21:49.70#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.218.08:21:49.70#ibcon#enter wrdev, iclass 3, count 2 2006.218.08:21:49.70#ibcon#first serial, iclass 3, count 2 2006.218.08:21:49.70#ibcon#enter sib2, iclass 3, count 2 2006.218.08:21:49.70#ibcon#flushed, iclass 3, count 2 2006.218.08:21:49.70#ibcon#about to write, iclass 3, count 2 2006.218.08:21:49.70#ibcon#wrote, iclass 3, count 2 2006.218.08:21:49.70#ibcon#about to read 3, iclass 3, count 2 2006.218.08:21:49.72#ibcon#read 3, iclass 3, count 2 2006.218.08:21:49.72#ibcon#about to read 4, iclass 3, count 2 2006.218.08:21:49.72#ibcon#read 4, iclass 3, count 2 2006.218.08:21:49.72#ibcon#about to read 5, iclass 3, count 2 2006.218.08:21:49.72#ibcon#read 5, iclass 3, count 2 2006.218.08:21:49.72#ibcon#about to read 6, iclass 3, count 2 2006.218.08:21:49.72#ibcon#read 6, iclass 3, count 2 2006.218.08:21:49.72#ibcon#end of sib2, iclass 3, count 2 2006.218.08:21:49.72#ibcon#*mode == 0, iclass 3, count 2 2006.218.08:21:49.72#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.218.08:21:49.72#ibcon#[25=AT06-06\r\n] 2006.218.08:21:49.72#ibcon#*before write, iclass 3, count 2 2006.218.08:21:49.72#ibcon#enter sib2, iclass 3, count 2 2006.218.08:21:49.72#ibcon#flushed, iclass 3, count 2 2006.218.08:21:49.72#ibcon#about to write, iclass 3, count 2 2006.218.08:21:49.72#ibcon#wrote, iclass 3, count 2 2006.218.08:21:49.72#ibcon#about to read 3, iclass 3, count 2 2006.218.08:21:49.75#ibcon#read 3, iclass 3, count 2 2006.218.08:21:49.75#ibcon#about to read 4, iclass 3, count 2 2006.218.08:21:49.75#ibcon#read 4, iclass 3, count 2 2006.218.08:21:49.75#ibcon#about to read 5, iclass 3, count 2 2006.218.08:21:49.75#ibcon#read 5, iclass 3, count 2 2006.218.08:21:49.75#ibcon#about to read 6, iclass 3, count 2 2006.218.08:21:49.75#ibcon#read 6, iclass 3, count 2 2006.218.08:21:49.75#ibcon#end of sib2, iclass 3, count 2 2006.218.08:21:49.75#ibcon#*after write, iclass 3, count 2 2006.218.08:21:49.75#ibcon#*before return 0, iclass 3, count 2 2006.218.08:21:49.75#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.218.08:21:49.75#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.218.08:21:49.75#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.218.08:21:49.75#ibcon#ireg 7 cls_cnt 0 2006.218.08:21:49.75#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.218.08:21:49.87#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.218.08:21:49.87#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.218.08:21:49.87#ibcon#enter wrdev, iclass 3, count 0 2006.218.08:21:49.87#ibcon#first serial, iclass 3, count 0 2006.218.08:21:49.87#ibcon#enter sib2, iclass 3, count 0 2006.218.08:21:49.87#ibcon#flushed, iclass 3, count 0 2006.218.08:21:49.87#ibcon#about to write, iclass 3, count 0 2006.218.08:21:49.87#ibcon#wrote, iclass 3, count 0 2006.218.08:21:49.87#ibcon#about to read 3, iclass 3, count 0 2006.218.08:21:49.89#ibcon#read 3, iclass 3, count 0 2006.218.08:21:49.89#ibcon#about to read 4, iclass 3, count 0 2006.218.08:21:49.89#ibcon#read 4, iclass 3, count 0 2006.218.08:21:49.89#ibcon#about to read 5, iclass 3, count 0 2006.218.08:21:49.89#ibcon#read 5, iclass 3, count 0 2006.218.08:21:49.89#ibcon#about to read 6, iclass 3, count 0 2006.218.08:21:49.89#ibcon#read 6, iclass 3, count 0 2006.218.08:21:49.89#ibcon#end of sib2, iclass 3, count 0 2006.218.08:21:49.89#ibcon#*mode == 0, iclass 3, count 0 2006.218.08:21:49.89#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.218.08:21:49.89#ibcon#[25=USB\r\n] 2006.218.08:21:49.89#ibcon#*before write, iclass 3, count 0 2006.218.08:21:49.89#ibcon#enter sib2, iclass 3, count 0 2006.218.08:21:49.89#ibcon#flushed, iclass 3, count 0 2006.218.08:21:49.89#ibcon#about to write, iclass 3, count 0 2006.218.08:21:49.89#ibcon#wrote, iclass 3, count 0 2006.218.08:21:49.89#ibcon#about to read 3, iclass 3, count 0 2006.218.08:21:49.92#ibcon#read 3, iclass 3, count 0 2006.218.08:21:49.92#ibcon#about to read 4, iclass 3, count 0 2006.218.08:21:49.92#ibcon#read 4, iclass 3, count 0 2006.218.08:21:49.92#ibcon#about to read 5, iclass 3, count 0 2006.218.08:21:49.92#ibcon#read 5, iclass 3, count 0 2006.218.08:21:49.92#ibcon#about to read 6, iclass 3, count 0 2006.218.08:21:49.92#ibcon#read 6, iclass 3, count 0 2006.218.08:21:49.92#ibcon#end of sib2, iclass 3, count 0 2006.218.08:21:49.92#ibcon#*after write, iclass 3, count 0 2006.218.08:21:49.92#ibcon#*before return 0, iclass 3, count 0 2006.218.08:21:49.92#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.218.08:21:49.92#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.218.08:21:49.92#ibcon#about to clear, iclass 3 cls_cnt 0 2006.218.08:21:49.92#ibcon#cleared, iclass 3 cls_cnt 0 2006.218.08:21:49.92$vc4f8/valo=7,832.99 2006.218.08:21:49.92#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.218.08:21:49.92#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.218.08:21:49.92#ibcon#ireg 17 cls_cnt 0 2006.218.08:21:49.92#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.218.08:21:49.92#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.218.08:21:49.92#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.218.08:21:49.92#ibcon#enter wrdev, iclass 5, count 0 2006.218.08:21:49.92#ibcon#first serial, iclass 5, count 0 2006.218.08:21:49.92#ibcon#enter sib2, iclass 5, count 0 2006.218.08:21:49.92#ibcon#flushed, iclass 5, count 0 2006.218.08:21:49.92#ibcon#about to write, iclass 5, count 0 2006.218.08:21:49.92#ibcon#wrote, iclass 5, count 0 2006.218.08:21:49.92#ibcon#about to read 3, iclass 5, count 0 2006.218.08:21:49.94#ibcon#read 3, iclass 5, count 0 2006.218.08:21:49.94#ibcon#about to read 4, iclass 5, count 0 2006.218.08:21:49.94#ibcon#read 4, iclass 5, count 0 2006.218.08:21:49.94#ibcon#about to read 5, iclass 5, count 0 2006.218.08:21:49.94#ibcon#read 5, iclass 5, count 0 2006.218.08:21:49.94#ibcon#about to read 6, iclass 5, count 0 2006.218.08:21:49.94#ibcon#read 6, iclass 5, count 0 2006.218.08:21:49.94#ibcon#end of sib2, iclass 5, count 0 2006.218.08:21:49.94#ibcon#*mode == 0, iclass 5, count 0 2006.218.08:21:49.94#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.218.08:21:49.94#ibcon#[26=FRQ=07,832.99\r\n] 2006.218.08:21:49.94#ibcon#*before write, iclass 5, count 0 2006.218.08:21:49.94#ibcon#enter sib2, iclass 5, count 0 2006.218.08:21:49.94#ibcon#flushed, iclass 5, count 0 2006.218.08:21:49.94#ibcon#about to write, iclass 5, count 0 2006.218.08:21:49.94#ibcon#wrote, iclass 5, count 0 2006.218.08:21:49.94#ibcon#about to read 3, iclass 5, count 0 2006.218.08:21:49.98#ibcon#read 3, iclass 5, count 0 2006.218.08:21:49.98#ibcon#about to read 4, iclass 5, count 0 2006.218.08:21:49.98#ibcon#read 4, iclass 5, count 0 2006.218.08:21:49.98#ibcon#about to read 5, iclass 5, count 0 2006.218.08:21:49.98#ibcon#read 5, iclass 5, count 0 2006.218.08:21:49.98#ibcon#about to read 6, iclass 5, count 0 2006.218.08:21:49.98#ibcon#read 6, iclass 5, count 0 2006.218.08:21:49.98#ibcon#end of sib2, iclass 5, count 0 2006.218.08:21:49.98#ibcon#*after write, iclass 5, count 0 2006.218.08:21:49.98#ibcon#*before return 0, iclass 5, count 0 2006.218.08:21:49.98#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.218.08:21:49.98#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.218.08:21:49.98#ibcon#about to clear, iclass 5 cls_cnt 0 2006.218.08:21:49.98#ibcon#cleared, iclass 5 cls_cnt 0 2006.218.08:21:49.98$vc4f8/va=7,6 2006.218.08:21:49.98#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.218.08:21:49.98#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.218.08:21:49.98#ibcon#ireg 11 cls_cnt 2 2006.218.08:21:49.98#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.218.08:21:50.04#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.218.08:21:50.04#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.218.08:21:50.04#ibcon#enter wrdev, iclass 7, count 2 2006.218.08:21:50.04#ibcon#first serial, iclass 7, count 2 2006.218.08:21:50.04#ibcon#enter sib2, iclass 7, count 2 2006.218.08:21:50.04#ibcon#flushed, iclass 7, count 2 2006.218.08:21:50.04#ibcon#about to write, iclass 7, count 2 2006.218.08:21:50.04#ibcon#wrote, iclass 7, count 2 2006.218.08:21:50.04#ibcon#about to read 3, iclass 7, count 2 2006.218.08:21:50.06#ibcon#read 3, iclass 7, count 2 2006.218.08:21:50.06#ibcon#about to read 4, iclass 7, count 2 2006.218.08:21:50.06#ibcon#read 4, iclass 7, count 2 2006.218.08:21:50.06#ibcon#about to read 5, iclass 7, count 2 2006.218.08:21:50.06#ibcon#read 5, iclass 7, count 2 2006.218.08:21:50.06#ibcon#about to read 6, iclass 7, count 2 2006.218.08:21:50.06#ibcon#read 6, iclass 7, count 2 2006.218.08:21:50.06#ibcon#end of sib2, iclass 7, count 2 2006.218.08:21:50.06#ibcon#*mode == 0, iclass 7, count 2 2006.218.08:21:50.06#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.218.08:21:50.06#ibcon#[25=AT07-06\r\n] 2006.218.08:21:50.06#ibcon#*before write, iclass 7, count 2 2006.218.08:21:50.06#ibcon#enter sib2, iclass 7, count 2 2006.218.08:21:50.06#ibcon#flushed, iclass 7, count 2 2006.218.08:21:50.06#ibcon#about to write, iclass 7, count 2 2006.218.08:21:50.06#ibcon#wrote, iclass 7, count 2 2006.218.08:21:50.06#ibcon#about to read 3, iclass 7, count 2 2006.218.08:21:50.09#ibcon#read 3, iclass 7, count 2 2006.218.08:21:50.09#ibcon#about to read 4, iclass 7, count 2 2006.218.08:21:50.09#ibcon#read 4, iclass 7, count 2 2006.218.08:21:50.09#ibcon#about to read 5, iclass 7, count 2 2006.218.08:21:50.09#ibcon#read 5, iclass 7, count 2 2006.218.08:21:50.09#ibcon#about to read 6, iclass 7, count 2 2006.218.08:21:50.09#ibcon#read 6, iclass 7, count 2 2006.218.08:21:50.09#ibcon#end of sib2, iclass 7, count 2 2006.218.08:21:50.09#ibcon#*after write, iclass 7, count 2 2006.218.08:21:50.09#ibcon#*before return 0, iclass 7, count 2 2006.218.08:21:50.09#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.218.08:21:50.09#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.218.08:21:50.09#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.218.08:21:50.09#ibcon#ireg 7 cls_cnt 0 2006.218.08:21:50.09#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.218.08:21:50.21#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.218.08:21:50.21#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.218.08:21:50.21#ibcon#enter wrdev, iclass 7, count 0 2006.218.08:21:50.21#ibcon#first serial, iclass 7, count 0 2006.218.08:21:50.21#ibcon#enter sib2, iclass 7, count 0 2006.218.08:21:50.21#ibcon#flushed, iclass 7, count 0 2006.218.08:21:50.21#ibcon#about to write, iclass 7, count 0 2006.218.08:21:50.21#ibcon#wrote, iclass 7, count 0 2006.218.08:21:50.21#ibcon#about to read 3, iclass 7, count 0 2006.218.08:21:50.23#ibcon#read 3, iclass 7, count 0 2006.218.08:21:50.23#ibcon#about to read 4, iclass 7, count 0 2006.218.08:21:50.23#ibcon#read 4, iclass 7, count 0 2006.218.08:21:50.23#ibcon#about to read 5, iclass 7, count 0 2006.218.08:21:50.23#ibcon#read 5, iclass 7, count 0 2006.218.08:21:50.23#ibcon#about to read 6, iclass 7, count 0 2006.218.08:21:50.23#ibcon#read 6, iclass 7, count 0 2006.218.08:21:50.23#ibcon#end of sib2, iclass 7, count 0 2006.218.08:21:50.23#ibcon#*mode == 0, iclass 7, count 0 2006.218.08:21:50.23#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.218.08:21:50.23#ibcon#[25=USB\r\n] 2006.218.08:21:50.23#ibcon#*before write, iclass 7, count 0 2006.218.08:21:50.23#ibcon#enter sib2, iclass 7, count 0 2006.218.08:21:50.23#ibcon#flushed, iclass 7, count 0 2006.218.08:21:50.23#ibcon#about to write, iclass 7, count 0 2006.218.08:21:50.23#ibcon#wrote, iclass 7, count 0 2006.218.08:21:50.23#ibcon#about to read 3, iclass 7, count 0 2006.218.08:21:50.26#ibcon#read 3, iclass 7, count 0 2006.218.08:21:50.26#ibcon#about to read 4, iclass 7, count 0 2006.218.08:21:50.26#ibcon#read 4, iclass 7, count 0 2006.218.08:21:50.26#ibcon#about to read 5, iclass 7, count 0 2006.218.08:21:50.26#ibcon#read 5, iclass 7, count 0 2006.218.08:21:50.26#ibcon#about to read 6, iclass 7, count 0 2006.218.08:21:50.26#ibcon#read 6, iclass 7, count 0 2006.218.08:21:50.26#ibcon#end of sib2, iclass 7, count 0 2006.218.08:21:50.26#ibcon#*after write, iclass 7, count 0 2006.218.08:21:50.26#ibcon#*before return 0, iclass 7, count 0 2006.218.08:21:50.26#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.218.08:21:50.26#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.218.08:21:50.26#ibcon#about to clear, iclass 7 cls_cnt 0 2006.218.08:21:50.26#ibcon#cleared, iclass 7 cls_cnt 0 2006.218.08:21:50.26$vc4f8/valo=8,852.99 2006.218.08:21:50.26#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.218.08:21:50.26#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.218.08:21:50.26#ibcon#ireg 17 cls_cnt 0 2006.218.08:21:50.26#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.218.08:21:50.26#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.218.08:21:50.26#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.218.08:21:50.26#ibcon#enter wrdev, iclass 11, count 0 2006.218.08:21:50.26#ibcon#first serial, iclass 11, count 0 2006.218.08:21:50.26#ibcon#enter sib2, iclass 11, count 0 2006.218.08:21:50.26#ibcon#flushed, iclass 11, count 0 2006.218.08:21:50.26#ibcon#about to write, iclass 11, count 0 2006.218.08:21:50.26#ibcon#wrote, iclass 11, count 0 2006.218.08:21:50.26#ibcon#about to read 3, iclass 11, count 0 2006.218.08:21:50.28#ibcon#read 3, iclass 11, count 0 2006.218.08:21:50.28#ibcon#about to read 4, iclass 11, count 0 2006.218.08:21:50.28#ibcon#read 4, iclass 11, count 0 2006.218.08:21:50.28#ibcon#about to read 5, iclass 11, count 0 2006.218.08:21:50.28#ibcon#read 5, iclass 11, count 0 2006.218.08:21:50.28#ibcon#about to read 6, iclass 11, count 0 2006.218.08:21:50.28#ibcon#read 6, iclass 11, count 0 2006.218.08:21:50.28#ibcon#end of sib2, iclass 11, count 0 2006.218.08:21:50.28#ibcon#*mode == 0, iclass 11, count 0 2006.218.08:21:50.28#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.218.08:21:50.28#ibcon#[26=FRQ=08,852.99\r\n] 2006.218.08:21:50.28#ibcon#*before write, iclass 11, count 0 2006.218.08:21:50.28#ibcon#enter sib2, iclass 11, count 0 2006.218.08:21:50.28#ibcon#flushed, iclass 11, count 0 2006.218.08:21:50.28#ibcon#about to write, iclass 11, count 0 2006.218.08:21:50.28#ibcon#wrote, iclass 11, count 0 2006.218.08:21:50.28#ibcon#about to read 3, iclass 11, count 0 2006.218.08:21:50.32#ibcon#read 3, iclass 11, count 0 2006.218.08:21:50.32#ibcon#about to read 4, iclass 11, count 0 2006.218.08:21:50.32#ibcon#read 4, iclass 11, count 0 2006.218.08:21:50.32#ibcon#about to read 5, iclass 11, count 0 2006.218.08:21:50.32#ibcon#read 5, iclass 11, count 0 2006.218.08:21:50.32#ibcon#about to read 6, iclass 11, count 0 2006.218.08:21:50.32#ibcon#read 6, iclass 11, count 0 2006.218.08:21:50.32#ibcon#end of sib2, iclass 11, count 0 2006.218.08:21:50.32#ibcon#*after write, iclass 11, count 0 2006.218.08:21:50.32#ibcon#*before return 0, iclass 11, count 0 2006.218.08:21:50.32#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.218.08:21:50.32#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.218.08:21:50.32#ibcon#about to clear, iclass 11 cls_cnt 0 2006.218.08:21:50.32#ibcon#cleared, iclass 11 cls_cnt 0 2006.218.08:21:50.32$vc4f8/va=8,7 2006.218.08:21:50.32#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.218.08:21:50.32#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.218.08:21:50.32#ibcon#ireg 11 cls_cnt 2 2006.218.08:21:50.32#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.218.08:21:50.38#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.218.08:21:50.38#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.218.08:21:50.38#ibcon#enter wrdev, iclass 13, count 2 2006.218.08:21:50.38#ibcon#first serial, iclass 13, count 2 2006.218.08:21:50.38#ibcon#enter sib2, iclass 13, count 2 2006.218.08:21:50.38#ibcon#flushed, iclass 13, count 2 2006.218.08:21:50.38#ibcon#about to write, iclass 13, count 2 2006.218.08:21:50.38#ibcon#wrote, iclass 13, count 2 2006.218.08:21:50.38#ibcon#about to read 3, iclass 13, count 2 2006.218.08:21:50.40#ibcon#read 3, iclass 13, count 2 2006.218.08:21:50.40#ibcon#about to read 4, iclass 13, count 2 2006.218.08:21:50.40#ibcon#read 4, iclass 13, count 2 2006.218.08:21:50.40#ibcon#about to read 5, iclass 13, count 2 2006.218.08:21:50.40#ibcon#read 5, iclass 13, count 2 2006.218.08:21:50.40#ibcon#about to read 6, iclass 13, count 2 2006.218.08:21:50.40#ibcon#read 6, iclass 13, count 2 2006.218.08:21:50.40#ibcon#end of sib2, iclass 13, count 2 2006.218.08:21:50.40#ibcon#*mode == 0, iclass 13, count 2 2006.218.08:21:50.40#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.218.08:21:50.40#ibcon#[25=AT08-07\r\n] 2006.218.08:21:50.40#ibcon#*before write, iclass 13, count 2 2006.218.08:21:50.40#ibcon#enter sib2, iclass 13, count 2 2006.218.08:21:50.40#ibcon#flushed, iclass 13, count 2 2006.218.08:21:50.40#ibcon#about to write, iclass 13, count 2 2006.218.08:21:50.40#ibcon#wrote, iclass 13, count 2 2006.218.08:21:50.40#ibcon#about to read 3, iclass 13, count 2 2006.218.08:21:50.43#ibcon#read 3, iclass 13, count 2 2006.218.08:21:50.43#ibcon#about to read 4, iclass 13, count 2 2006.218.08:21:50.43#ibcon#read 4, iclass 13, count 2 2006.218.08:21:50.43#ibcon#about to read 5, iclass 13, count 2 2006.218.08:21:50.43#ibcon#read 5, iclass 13, count 2 2006.218.08:21:50.43#ibcon#about to read 6, iclass 13, count 2 2006.218.08:21:50.43#ibcon#read 6, iclass 13, count 2 2006.218.08:21:50.43#ibcon#end of sib2, iclass 13, count 2 2006.218.08:21:50.43#ibcon#*after write, iclass 13, count 2 2006.218.08:21:50.43#ibcon#*before return 0, iclass 13, count 2 2006.218.08:21:50.43#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.218.08:21:50.43#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.218.08:21:50.43#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.218.08:21:50.43#ibcon#ireg 7 cls_cnt 0 2006.218.08:21:50.43#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.218.08:21:50.55#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.218.08:21:50.55#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.218.08:21:50.55#ibcon#enter wrdev, iclass 13, count 0 2006.218.08:21:50.55#ibcon#first serial, iclass 13, count 0 2006.218.08:21:50.55#ibcon#enter sib2, iclass 13, count 0 2006.218.08:21:50.55#ibcon#flushed, iclass 13, count 0 2006.218.08:21:50.55#ibcon#about to write, iclass 13, count 0 2006.218.08:21:50.55#ibcon#wrote, iclass 13, count 0 2006.218.08:21:50.55#ibcon#about to read 3, iclass 13, count 0 2006.218.08:21:50.57#ibcon#read 3, iclass 13, count 0 2006.218.08:21:50.57#ibcon#about to read 4, iclass 13, count 0 2006.218.08:21:50.57#ibcon#read 4, iclass 13, count 0 2006.218.08:21:50.57#ibcon#about to read 5, iclass 13, count 0 2006.218.08:21:50.57#ibcon#read 5, iclass 13, count 0 2006.218.08:21:50.57#ibcon#about to read 6, iclass 13, count 0 2006.218.08:21:50.57#ibcon#read 6, iclass 13, count 0 2006.218.08:21:50.57#ibcon#end of sib2, iclass 13, count 0 2006.218.08:21:50.57#ibcon#*mode == 0, iclass 13, count 0 2006.218.08:21:50.57#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.218.08:21:50.57#ibcon#[25=USB\r\n] 2006.218.08:21:50.57#ibcon#*before write, iclass 13, count 0 2006.218.08:21:50.57#ibcon#enter sib2, iclass 13, count 0 2006.218.08:21:50.57#ibcon#flushed, iclass 13, count 0 2006.218.08:21:50.57#ibcon#about to write, iclass 13, count 0 2006.218.08:21:50.57#ibcon#wrote, iclass 13, count 0 2006.218.08:21:50.57#ibcon#about to read 3, iclass 13, count 0 2006.218.08:21:50.60#ibcon#read 3, iclass 13, count 0 2006.218.08:21:50.60#ibcon#about to read 4, iclass 13, count 0 2006.218.08:21:50.60#ibcon#read 4, iclass 13, count 0 2006.218.08:21:50.60#ibcon#about to read 5, iclass 13, count 0 2006.218.08:21:50.60#ibcon#read 5, iclass 13, count 0 2006.218.08:21:50.60#ibcon#about to read 6, iclass 13, count 0 2006.218.08:21:50.60#ibcon#read 6, iclass 13, count 0 2006.218.08:21:50.60#ibcon#end of sib2, iclass 13, count 0 2006.218.08:21:50.60#ibcon#*after write, iclass 13, count 0 2006.218.08:21:50.60#ibcon#*before return 0, iclass 13, count 0 2006.218.08:21:50.60#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.218.08:21:50.60#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.218.08:21:50.60#ibcon#about to clear, iclass 13 cls_cnt 0 2006.218.08:21:50.60#ibcon#cleared, iclass 13 cls_cnt 0 2006.218.08:21:50.60$vc4f8/vblo=1,632.99 2006.218.08:21:50.60#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.218.08:21:50.60#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.218.08:21:50.60#ibcon#ireg 17 cls_cnt 0 2006.218.08:21:50.60#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.218.08:21:50.60#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.218.08:21:50.60#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.218.08:21:50.60#ibcon#enter wrdev, iclass 15, count 0 2006.218.08:21:50.60#ibcon#first serial, iclass 15, count 0 2006.218.08:21:50.60#ibcon#enter sib2, iclass 15, count 0 2006.218.08:21:50.60#ibcon#flushed, iclass 15, count 0 2006.218.08:21:50.60#ibcon#about to write, iclass 15, count 0 2006.218.08:21:50.60#ibcon#wrote, iclass 15, count 0 2006.218.08:21:50.60#ibcon#about to read 3, iclass 15, count 0 2006.218.08:21:50.62#ibcon#read 3, iclass 15, count 0 2006.218.08:21:50.62#ibcon#about to read 4, iclass 15, count 0 2006.218.08:21:50.62#ibcon#read 4, iclass 15, count 0 2006.218.08:21:50.62#ibcon#about to read 5, iclass 15, count 0 2006.218.08:21:50.62#ibcon#read 5, iclass 15, count 0 2006.218.08:21:50.62#ibcon#about to read 6, iclass 15, count 0 2006.218.08:21:50.62#ibcon#read 6, iclass 15, count 0 2006.218.08:21:50.62#ibcon#end of sib2, iclass 15, count 0 2006.218.08:21:50.62#ibcon#*mode == 0, iclass 15, count 0 2006.218.08:21:50.62#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.218.08:21:50.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.218.08:21:50.62#ibcon#*before write, iclass 15, count 0 2006.218.08:21:50.62#ibcon#enter sib2, iclass 15, count 0 2006.218.08:21:50.62#ibcon#flushed, iclass 15, count 0 2006.218.08:21:50.62#ibcon#about to write, iclass 15, count 0 2006.218.08:21:50.62#ibcon#wrote, iclass 15, count 0 2006.218.08:21:50.62#ibcon#about to read 3, iclass 15, count 0 2006.218.08:21:50.66#ibcon#read 3, iclass 15, count 0 2006.218.08:21:50.66#ibcon#about to read 4, iclass 15, count 0 2006.218.08:21:50.66#ibcon#read 4, iclass 15, count 0 2006.218.08:21:50.66#ibcon#about to read 5, iclass 15, count 0 2006.218.08:21:50.66#ibcon#read 5, iclass 15, count 0 2006.218.08:21:50.66#ibcon#about to read 6, iclass 15, count 0 2006.218.08:21:50.66#ibcon#read 6, iclass 15, count 0 2006.218.08:21:50.66#ibcon#end of sib2, iclass 15, count 0 2006.218.08:21:50.66#ibcon#*after write, iclass 15, count 0 2006.218.08:21:50.66#ibcon#*before return 0, iclass 15, count 0 2006.218.08:21:50.66#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.218.08:21:50.66#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.218.08:21:50.66#ibcon#about to clear, iclass 15 cls_cnt 0 2006.218.08:21:50.66#ibcon#cleared, iclass 15 cls_cnt 0 2006.218.08:21:50.66$vc4f8/vb=1,4 2006.218.08:21:50.66#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.218.08:21:50.66#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.218.08:21:50.66#ibcon#ireg 11 cls_cnt 2 2006.218.08:21:50.66#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.218.08:21:50.66#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.218.08:21:50.66#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.218.08:21:50.66#ibcon#enter wrdev, iclass 17, count 2 2006.218.08:21:50.66#ibcon#first serial, iclass 17, count 2 2006.218.08:21:50.66#ibcon#enter sib2, iclass 17, count 2 2006.218.08:21:50.66#ibcon#flushed, iclass 17, count 2 2006.218.08:21:50.66#ibcon#about to write, iclass 17, count 2 2006.218.08:21:50.66#ibcon#wrote, iclass 17, count 2 2006.218.08:21:50.66#ibcon#about to read 3, iclass 17, count 2 2006.218.08:21:50.68#ibcon#read 3, iclass 17, count 2 2006.218.08:21:50.68#ibcon#about to read 4, iclass 17, count 2 2006.218.08:21:50.68#ibcon#read 4, iclass 17, count 2 2006.218.08:21:50.68#ibcon#about to read 5, iclass 17, count 2 2006.218.08:21:50.68#ibcon#read 5, iclass 17, count 2 2006.218.08:21:50.68#ibcon#about to read 6, iclass 17, count 2 2006.218.08:21:50.68#ibcon#read 6, iclass 17, count 2 2006.218.08:21:50.68#ibcon#end of sib2, iclass 17, count 2 2006.218.08:21:50.68#ibcon#*mode == 0, iclass 17, count 2 2006.218.08:21:50.68#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.218.08:21:50.68#ibcon#[27=AT01-04\r\n] 2006.218.08:21:50.68#ibcon#*before write, iclass 17, count 2 2006.218.08:21:50.68#ibcon#enter sib2, iclass 17, count 2 2006.218.08:21:50.68#ibcon#flushed, iclass 17, count 2 2006.218.08:21:50.68#ibcon#about to write, iclass 17, count 2 2006.218.08:21:50.68#ibcon#wrote, iclass 17, count 2 2006.218.08:21:50.68#ibcon#about to read 3, iclass 17, count 2 2006.218.08:21:50.71#ibcon#read 3, iclass 17, count 2 2006.218.08:21:50.71#ibcon#about to read 4, iclass 17, count 2 2006.218.08:21:50.71#ibcon#read 4, iclass 17, count 2 2006.218.08:21:50.71#ibcon#about to read 5, iclass 17, count 2 2006.218.08:21:50.71#ibcon#read 5, iclass 17, count 2 2006.218.08:21:50.71#ibcon#about to read 6, iclass 17, count 2 2006.218.08:21:50.71#ibcon#read 6, iclass 17, count 2 2006.218.08:21:50.71#ibcon#end of sib2, iclass 17, count 2 2006.218.08:21:50.71#ibcon#*after write, iclass 17, count 2 2006.218.08:21:50.71#ibcon#*before return 0, iclass 17, count 2 2006.218.08:21:50.71#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.218.08:21:50.71#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.218.08:21:50.71#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.218.08:21:50.71#ibcon#ireg 7 cls_cnt 0 2006.218.08:21:50.71#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.218.08:21:50.83#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.218.08:21:50.83#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.218.08:21:50.83#ibcon#enter wrdev, iclass 17, count 0 2006.218.08:21:50.83#ibcon#first serial, iclass 17, count 0 2006.218.08:21:50.83#ibcon#enter sib2, iclass 17, count 0 2006.218.08:21:50.83#ibcon#flushed, iclass 17, count 0 2006.218.08:21:50.83#ibcon#about to write, iclass 17, count 0 2006.218.08:21:50.83#ibcon#wrote, iclass 17, count 0 2006.218.08:21:50.83#ibcon#about to read 3, iclass 17, count 0 2006.218.08:21:50.85#ibcon#read 3, iclass 17, count 0 2006.218.08:21:50.85#ibcon#about to read 4, iclass 17, count 0 2006.218.08:21:50.85#ibcon#read 4, iclass 17, count 0 2006.218.08:21:50.85#ibcon#about to read 5, iclass 17, count 0 2006.218.08:21:50.85#ibcon#read 5, iclass 17, count 0 2006.218.08:21:50.85#ibcon#about to read 6, iclass 17, count 0 2006.218.08:21:50.85#ibcon#read 6, iclass 17, count 0 2006.218.08:21:50.85#ibcon#end of sib2, iclass 17, count 0 2006.218.08:21:50.85#ibcon#*mode == 0, iclass 17, count 0 2006.218.08:21:50.85#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.218.08:21:50.85#ibcon#[27=USB\r\n] 2006.218.08:21:50.85#ibcon#*before write, iclass 17, count 0 2006.218.08:21:50.85#ibcon#enter sib2, iclass 17, count 0 2006.218.08:21:50.85#ibcon#flushed, iclass 17, count 0 2006.218.08:21:50.85#ibcon#about to write, iclass 17, count 0 2006.218.08:21:50.85#ibcon#wrote, iclass 17, count 0 2006.218.08:21:50.85#ibcon#about to read 3, iclass 17, count 0 2006.218.08:21:50.88#ibcon#read 3, iclass 17, count 0 2006.218.08:21:50.88#ibcon#about to read 4, iclass 17, count 0 2006.218.08:21:50.88#ibcon#read 4, iclass 17, count 0 2006.218.08:21:50.88#ibcon#about to read 5, iclass 17, count 0 2006.218.08:21:50.88#ibcon#read 5, iclass 17, count 0 2006.218.08:21:50.88#ibcon#about to read 6, iclass 17, count 0 2006.218.08:21:50.88#ibcon#read 6, iclass 17, count 0 2006.218.08:21:50.88#ibcon#end of sib2, iclass 17, count 0 2006.218.08:21:50.88#ibcon#*after write, iclass 17, count 0 2006.218.08:21:50.88#ibcon#*before return 0, iclass 17, count 0 2006.218.08:21:50.88#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.218.08:21:50.88#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.218.08:21:50.88#ibcon#about to clear, iclass 17 cls_cnt 0 2006.218.08:21:50.88#ibcon#cleared, iclass 17 cls_cnt 0 2006.218.08:21:50.88$vc4f8/vblo=2,640.99 2006.218.08:21:50.88#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.218.08:21:50.88#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.218.08:21:50.88#ibcon#ireg 17 cls_cnt 0 2006.218.08:21:50.88#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.218.08:21:50.88#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.218.08:21:50.88#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.218.08:21:50.88#ibcon#enter wrdev, iclass 19, count 0 2006.218.08:21:50.88#ibcon#first serial, iclass 19, count 0 2006.218.08:21:50.88#ibcon#enter sib2, iclass 19, count 0 2006.218.08:21:50.88#ibcon#flushed, iclass 19, count 0 2006.218.08:21:50.88#ibcon#about to write, iclass 19, count 0 2006.218.08:21:50.88#ibcon#wrote, iclass 19, count 0 2006.218.08:21:50.88#ibcon#about to read 3, iclass 19, count 0 2006.218.08:21:50.90#ibcon#read 3, iclass 19, count 0 2006.218.08:21:50.90#ibcon#about to read 4, iclass 19, count 0 2006.218.08:21:50.90#ibcon#read 4, iclass 19, count 0 2006.218.08:21:50.90#ibcon#about to read 5, iclass 19, count 0 2006.218.08:21:50.90#ibcon#read 5, iclass 19, count 0 2006.218.08:21:50.90#ibcon#about to read 6, iclass 19, count 0 2006.218.08:21:50.90#ibcon#read 6, iclass 19, count 0 2006.218.08:21:50.90#ibcon#end of sib2, iclass 19, count 0 2006.218.08:21:50.90#ibcon#*mode == 0, iclass 19, count 0 2006.218.08:21:50.90#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.218.08:21:50.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.218.08:21:50.90#ibcon#*before write, iclass 19, count 0 2006.218.08:21:50.90#ibcon#enter sib2, iclass 19, count 0 2006.218.08:21:50.90#ibcon#flushed, iclass 19, count 0 2006.218.08:21:50.90#ibcon#about to write, iclass 19, count 0 2006.218.08:21:50.90#ibcon#wrote, iclass 19, count 0 2006.218.08:21:50.90#ibcon#about to read 3, iclass 19, count 0 2006.218.08:21:50.94#ibcon#read 3, iclass 19, count 0 2006.218.08:21:50.94#ibcon#about to read 4, iclass 19, count 0 2006.218.08:21:50.94#ibcon#read 4, iclass 19, count 0 2006.218.08:21:50.94#ibcon#about to read 5, iclass 19, count 0 2006.218.08:21:50.94#ibcon#read 5, iclass 19, count 0 2006.218.08:21:50.94#ibcon#about to read 6, iclass 19, count 0 2006.218.08:21:50.94#ibcon#read 6, iclass 19, count 0 2006.218.08:21:50.94#ibcon#end of sib2, iclass 19, count 0 2006.218.08:21:50.94#ibcon#*after write, iclass 19, count 0 2006.218.08:21:50.94#ibcon#*before return 0, iclass 19, count 0 2006.218.08:21:50.94#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.218.08:21:50.94#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.218.08:21:50.94#ibcon#about to clear, iclass 19 cls_cnt 0 2006.218.08:21:50.94#ibcon#cleared, iclass 19 cls_cnt 0 2006.218.08:21:50.94$vc4f8/vb=2,4 2006.218.08:21:50.94#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.218.08:21:50.94#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.218.08:21:50.94#ibcon#ireg 11 cls_cnt 2 2006.218.08:21:50.94#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.218.08:21:51.00#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.218.08:21:51.00#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.218.08:21:51.00#ibcon#enter wrdev, iclass 21, count 2 2006.218.08:21:51.00#ibcon#first serial, iclass 21, count 2 2006.218.08:21:51.00#ibcon#enter sib2, iclass 21, count 2 2006.218.08:21:51.00#ibcon#flushed, iclass 21, count 2 2006.218.08:21:51.00#ibcon#about to write, iclass 21, count 2 2006.218.08:21:51.00#ibcon#wrote, iclass 21, count 2 2006.218.08:21:51.00#ibcon#about to read 3, iclass 21, count 2 2006.218.08:21:51.02#ibcon#read 3, iclass 21, count 2 2006.218.08:21:51.02#ibcon#about to read 4, iclass 21, count 2 2006.218.08:21:51.02#ibcon#read 4, iclass 21, count 2 2006.218.08:21:51.02#ibcon#about to read 5, iclass 21, count 2 2006.218.08:21:51.02#ibcon#read 5, iclass 21, count 2 2006.218.08:21:51.02#ibcon#about to read 6, iclass 21, count 2 2006.218.08:21:51.02#ibcon#read 6, iclass 21, count 2 2006.218.08:21:51.02#ibcon#end of sib2, iclass 21, count 2 2006.218.08:21:51.02#ibcon#*mode == 0, iclass 21, count 2 2006.218.08:21:51.02#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.218.08:21:51.02#ibcon#[27=AT02-04\r\n] 2006.218.08:21:51.02#ibcon#*before write, iclass 21, count 2 2006.218.08:21:51.02#ibcon#enter sib2, iclass 21, count 2 2006.218.08:21:51.02#ibcon#flushed, iclass 21, count 2 2006.218.08:21:51.02#ibcon#about to write, iclass 21, count 2 2006.218.08:21:51.02#ibcon#wrote, iclass 21, count 2 2006.218.08:21:51.02#ibcon#about to read 3, iclass 21, count 2 2006.218.08:21:51.05#ibcon#read 3, iclass 21, count 2 2006.218.08:21:51.05#ibcon#about to read 4, iclass 21, count 2 2006.218.08:21:51.05#ibcon#read 4, iclass 21, count 2 2006.218.08:21:51.05#ibcon#about to read 5, iclass 21, count 2 2006.218.08:21:51.05#ibcon#read 5, iclass 21, count 2 2006.218.08:21:51.05#ibcon#about to read 6, iclass 21, count 2 2006.218.08:21:51.05#ibcon#read 6, iclass 21, count 2 2006.218.08:21:51.05#ibcon#end of sib2, iclass 21, count 2 2006.218.08:21:51.05#ibcon#*after write, iclass 21, count 2 2006.218.08:21:51.05#ibcon#*before return 0, iclass 21, count 2 2006.218.08:21:51.05#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.218.08:21:51.05#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.218.08:21:51.05#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.218.08:21:51.05#ibcon#ireg 7 cls_cnt 0 2006.218.08:21:51.05#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.218.08:21:51.17#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.218.08:21:51.17#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.218.08:21:51.17#ibcon#enter wrdev, iclass 21, count 0 2006.218.08:21:51.17#ibcon#first serial, iclass 21, count 0 2006.218.08:21:51.17#ibcon#enter sib2, iclass 21, count 0 2006.218.08:21:51.17#ibcon#flushed, iclass 21, count 0 2006.218.08:21:51.17#ibcon#about to write, iclass 21, count 0 2006.218.08:21:51.17#ibcon#wrote, iclass 21, count 0 2006.218.08:21:51.17#ibcon#about to read 3, iclass 21, count 0 2006.218.08:21:51.19#ibcon#read 3, iclass 21, count 0 2006.218.08:21:51.19#ibcon#about to read 4, iclass 21, count 0 2006.218.08:21:51.19#ibcon#read 4, iclass 21, count 0 2006.218.08:21:51.19#ibcon#about to read 5, iclass 21, count 0 2006.218.08:21:51.19#ibcon#read 5, iclass 21, count 0 2006.218.08:21:51.19#ibcon#about to read 6, iclass 21, count 0 2006.218.08:21:51.19#ibcon#read 6, iclass 21, count 0 2006.218.08:21:51.19#ibcon#end of sib2, iclass 21, count 0 2006.218.08:21:51.19#ibcon#*mode == 0, iclass 21, count 0 2006.218.08:21:51.19#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.218.08:21:51.19#ibcon#[27=USB\r\n] 2006.218.08:21:51.19#ibcon#*before write, iclass 21, count 0 2006.218.08:21:51.19#ibcon#enter sib2, iclass 21, count 0 2006.218.08:21:51.19#ibcon#flushed, iclass 21, count 0 2006.218.08:21:51.19#ibcon#about to write, iclass 21, count 0 2006.218.08:21:51.19#ibcon#wrote, iclass 21, count 0 2006.218.08:21:51.19#ibcon#about to read 3, iclass 21, count 0 2006.218.08:21:51.22#ibcon#read 3, iclass 21, count 0 2006.218.08:21:51.22#ibcon#about to read 4, iclass 21, count 0 2006.218.08:21:51.22#ibcon#read 4, iclass 21, count 0 2006.218.08:21:51.22#ibcon#about to read 5, iclass 21, count 0 2006.218.08:21:51.22#ibcon#read 5, iclass 21, count 0 2006.218.08:21:51.22#ibcon#about to read 6, iclass 21, count 0 2006.218.08:21:51.22#ibcon#read 6, iclass 21, count 0 2006.218.08:21:51.22#ibcon#end of sib2, iclass 21, count 0 2006.218.08:21:51.22#ibcon#*after write, iclass 21, count 0 2006.218.08:21:51.22#ibcon#*before return 0, iclass 21, count 0 2006.218.08:21:51.22#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.218.08:21:51.22#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.218.08:21:51.22#ibcon#about to clear, iclass 21 cls_cnt 0 2006.218.08:21:51.22#ibcon#cleared, iclass 21 cls_cnt 0 2006.218.08:21:51.22$vc4f8/vblo=3,656.99 2006.218.08:21:51.22#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.218.08:21:51.22#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.218.08:21:51.22#ibcon#ireg 17 cls_cnt 0 2006.218.08:21:51.22#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.218.08:21:51.22#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.218.08:21:51.22#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.218.08:21:51.22#ibcon#enter wrdev, iclass 23, count 0 2006.218.08:21:51.22#ibcon#first serial, iclass 23, count 0 2006.218.08:21:51.22#ibcon#enter sib2, iclass 23, count 0 2006.218.08:21:51.22#ibcon#flushed, iclass 23, count 0 2006.218.08:21:51.22#ibcon#about to write, iclass 23, count 0 2006.218.08:21:51.22#ibcon#wrote, iclass 23, count 0 2006.218.08:21:51.22#ibcon#about to read 3, iclass 23, count 0 2006.218.08:21:51.24#ibcon#read 3, iclass 23, count 0 2006.218.08:21:51.24#ibcon#about to read 4, iclass 23, count 0 2006.218.08:21:51.24#ibcon#read 4, iclass 23, count 0 2006.218.08:21:51.24#ibcon#about to read 5, iclass 23, count 0 2006.218.08:21:51.24#ibcon#read 5, iclass 23, count 0 2006.218.08:21:51.24#ibcon#about to read 6, iclass 23, count 0 2006.218.08:21:51.24#ibcon#read 6, iclass 23, count 0 2006.218.08:21:51.24#ibcon#end of sib2, iclass 23, count 0 2006.218.08:21:51.24#ibcon#*mode == 0, iclass 23, count 0 2006.218.08:21:51.24#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.218.08:21:51.24#ibcon#[28=FRQ=03,656.99\r\n] 2006.218.08:21:51.24#ibcon#*before write, iclass 23, count 0 2006.218.08:21:51.24#ibcon#enter sib2, iclass 23, count 0 2006.218.08:21:51.24#ibcon#flushed, iclass 23, count 0 2006.218.08:21:51.24#ibcon#about to write, iclass 23, count 0 2006.218.08:21:51.24#ibcon#wrote, iclass 23, count 0 2006.218.08:21:51.24#ibcon#about to read 3, iclass 23, count 0 2006.218.08:21:51.28#ibcon#read 3, iclass 23, count 0 2006.218.08:21:51.28#ibcon#about to read 4, iclass 23, count 0 2006.218.08:21:51.28#ibcon#read 4, iclass 23, count 0 2006.218.08:21:51.28#ibcon#about to read 5, iclass 23, count 0 2006.218.08:21:51.28#ibcon#read 5, iclass 23, count 0 2006.218.08:21:51.28#ibcon#about to read 6, iclass 23, count 0 2006.218.08:21:51.28#ibcon#read 6, iclass 23, count 0 2006.218.08:21:51.28#ibcon#end of sib2, iclass 23, count 0 2006.218.08:21:51.28#ibcon#*after write, iclass 23, count 0 2006.218.08:21:51.28#ibcon#*before return 0, iclass 23, count 0 2006.218.08:21:51.28#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.218.08:21:51.28#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.218.08:21:51.28#ibcon#about to clear, iclass 23 cls_cnt 0 2006.218.08:21:51.28#ibcon#cleared, iclass 23 cls_cnt 0 2006.218.08:21:51.28$vc4f8/vb=3,4 2006.218.08:21:51.28#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.218.08:21:51.28#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.218.08:21:51.28#ibcon#ireg 11 cls_cnt 2 2006.218.08:21:51.28#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.218.08:21:51.34#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.218.08:21:51.34#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.218.08:21:51.34#ibcon#enter wrdev, iclass 25, count 2 2006.218.08:21:51.34#ibcon#first serial, iclass 25, count 2 2006.218.08:21:51.34#ibcon#enter sib2, iclass 25, count 2 2006.218.08:21:51.34#ibcon#flushed, iclass 25, count 2 2006.218.08:21:51.34#ibcon#about to write, iclass 25, count 2 2006.218.08:21:51.34#ibcon#wrote, iclass 25, count 2 2006.218.08:21:51.34#ibcon#about to read 3, iclass 25, count 2 2006.218.08:21:51.36#ibcon#read 3, iclass 25, count 2 2006.218.08:21:51.36#ibcon#about to read 4, iclass 25, count 2 2006.218.08:21:51.36#ibcon#read 4, iclass 25, count 2 2006.218.08:21:51.36#ibcon#about to read 5, iclass 25, count 2 2006.218.08:21:51.36#ibcon#read 5, iclass 25, count 2 2006.218.08:21:51.36#ibcon#about to read 6, iclass 25, count 2 2006.218.08:21:51.36#ibcon#read 6, iclass 25, count 2 2006.218.08:21:51.36#ibcon#end of sib2, iclass 25, count 2 2006.218.08:21:51.36#ibcon#*mode == 0, iclass 25, count 2 2006.218.08:21:51.36#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.218.08:21:51.36#ibcon#[27=AT03-04\r\n] 2006.218.08:21:51.36#ibcon#*before write, iclass 25, count 2 2006.218.08:21:51.36#ibcon#enter sib2, iclass 25, count 2 2006.218.08:21:51.36#ibcon#flushed, iclass 25, count 2 2006.218.08:21:51.36#ibcon#about to write, iclass 25, count 2 2006.218.08:21:51.36#ibcon#wrote, iclass 25, count 2 2006.218.08:21:51.36#ibcon#about to read 3, iclass 25, count 2 2006.218.08:21:51.39#ibcon#read 3, iclass 25, count 2 2006.218.08:21:51.39#ibcon#about to read 4, iclass 25, count 2 2006.218.08:21:51.39#ibcon#read 4, iclass 25, count 2 2006.218.08:21:51.39#ibcon#about to read 5, iclass 25, count 2 2006.218.08:21:51.39#ibcon#read 5, iclass 25, count 2 2006.218.08:21:51.39#ibcon#about to read 6, iclass 25, count 2 2006.218.08:21:51.39#ibcon#read 6, iclass 25, count 2 2006.218.08:21:51.39#ibcon#end of sib2, iclass 25, count 2 2006.218.08:21:51.39#ibcon#*after write, iclass 25, count 2 2006.218.08:21:51.39#ibcon#*before return 0, iclass 25, count 2 2006.218.08:21:51.39#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.218.08:21:51.39#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.218.08:21:51.39#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.218.08:21:51.39#ibcon#ireg 7 cls_cnt 0 2006.218.08:21:51.39#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.218.08:21:51.51#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.218.08:21:51.51#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.218.08:21:51.51#ibcon#enter wrdev, iclass 25, count 0 2006.218.08:21:51.51#ibcon#first serial, iclass 25, count 0 2006.218.08:21:51.51#ibcon#enter sib2, iclass 25, count 0 2006.218.08:21:51.51#ibcon#flushed, iclass 25, count 0 2006.218.08:21:51.51#ibcon#about to write, iclass 25, count 0 2006.218.08:21:51.51#ibcon#wrote, iclass 25, count 0 2006.218.08:21:51.51#ibcon#about to read 3, iclass 25, count 0 2006.218.08:21:51.53#ibcon#read 3, iclass 25, count 0 2006.218.08:21:51.53#ibcon#about to read 4, iclass 25, count 0 2006.218.08:21:51.53#ibcon#read 4, iclass 25, count 0 2006.218.08:21:51.53#ibcon#about to read 5, iclass 25, count 0 2006.218.08:21:51.53#ibcon#read 5, iclass 25, count 0 2006.218.08:21:51.53#ibcon#about to read 6, iclass 25, count 0 2006.218.08:21:51.53#ibcon#read 6, iclass 25, count 0 2006.218.08:21:51.53#ibcon#end of sib2, iclass 25, count 0 2006.218.08:21:51.53#ibcon#*mode == 0, iclass 25, count 0 2006.218.08:21:51.53#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.218.08:21:51.53#ibcon#[27=USB\r\n] 2006.218.08:21:51.53#ibcon#*before write, iclass 25, count 0 2006.218.08:21:51.53#ibcon#enter sib2, iclass 25, count 0 2006.218.08:21:51.53#ibcon#flushed, iclass 25, count 0 2006.218.08:21:51.53#ibcon#about to write, iclass 25, count 0 2006.218.08:21:51.53#ibcon#wrote, iclass 25, count 0 2006.218.08:21:51.53#ibcon#about to read 3, iclass 25, count 0 2006.218.08:21:51.56#ibcon#read 3, iclass 25, count 0 2006.218.08:21:51.56#ibcon#about to read 4, iclass 25, count 0 2006.218.08:21:51.56#ibcon#read 4, iclass 25, count 0 2006.218.08:21:51.56#ibcon#about to read 5, iclass 25, count 0 2006.218.08:21:51.56#ibcon#read 5, iclass 25, count 0 2006.218.08:21:51.56#ibcon#about to read 6, iclass 25, count 0 2006.218.08:21:51.56#ibcon#read 6, iclass 25, count 0 2006.218.08:21:51.56#ibcon#end of sib2, iclass 25, count 0 2006.218.08:21:51.56#ibcon#*after write, iclass 25, count 0 2006.218.08:21:51.56#ibcon#*before return 0, iclass 25, count 0 2006.218.08:21:51.56#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.218.08:21:51.56#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.218.08:21:51.56#ibcon#about to clear, iclass 25 cls_cnt 0 2006.218.08:21:51.56#ibcon#cleared, iclass 25 cls_cnt 0 2006.218.08:21:51.56$vc4f8/vblo=4,712.99 2006.218.08:21:51.56#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.218.08:21:51.56#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.218.08:21:51.56#ibcon#ireg 17 cls_cnt 0 2006.218.08:21:51.56#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.218.08:21:51.56#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.218.08:21:51.56#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.218.08:21:51.56#ibcon#enter wrdev, iclass 27, count 0 2006.218.08:21:51.56#ibcon#first serial, iclass 27, count 0 2006.218.08:21:51.56#ibcon#enter sib2, iclass 27, count 0 2006.218.08:21:51.56#ibcon#flushed, iclass 27, count 0 2006.218.08:21:51.56#ibcon#about to write, iclass 27, count 0 2006.218.08:21:51.56#ibcon#wrote, iclass 27, count 0 2006.218.08:21:51.56#ibcon#about to read 3, iclass 27, count 0 2006.218.08:21:51.58#ibcon#read 3, iclass 27, count 0 2006.218.08:21:51.58#ibcon#about to read 4, iclass 27, count 0 2006.218.08:21:51.58#ibcon#read 4, iclass 27, count 0 2006.218.08:21:51.58#ibcon#about to read 5, iclass 27, count 0 2006.218.08:21:51.58#ibcon#read 5, iclass 27, count 0 2006.218.08:21:51.58#ibcon#about to read 6, iclass 27, count 0 2006.218.08:21:51.58#ibcon#read 6, iclass 27, count 0 2006.218.08:21:51.58#ibcon#end of sib2, iclass 27, count 0 2006.218.08:21:51.58#ibcon#*mode == 0, iclass 27, count 0 2006.218.08:21:51.58#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.218.08:21:51.58#ibcon#[28=FRQ=04,712.99\r\n] 2006.218.08:21:51.58#ibcon#*before write, iclass 27, count 0 2006.218.08:21:51.58#ibcon#enter sib2, iclass 27, count 0 2006.218.08:21:51.58#ibcon#flushed, iclass 27, count 0 2006.218.08:21:51.58#ibcon#about to write, iclass 27, count 0 2006.218.08:21:51.58#ibcon#wrote, iclass 27, count 0 2006.218.08:21:51.58#ibcon#about to read 3, iclass 27, count 0 2006.218.08:21:51.62#ibcon#read 3, iclass 27, count 0 2006.218.08:21:51.62#ibcon#about to read 4, iclass 27, count 0 2006.218.08:21:51.62#ibcon#read 4, iclass 27, count 0 2006.218.08:21:51.62#ibcon#about to read 5, iclass 27, count 0 2006.218.08:21:51.62#ibcon#read 5, iclass 27, count 0 2006.218.08:21:51.62#ibcon#about to read 6, iclass 27, count 0 2006.218.08:21:51.62#ibcon#read 6, iclass 27, count 0 2006.218.08:21:51.62#ibcon#end of sib2, iclass 27, count 0 2006.218.08:21:51.62#ibcon#*after write, iclass 27, count 0 2006.218.08:21:51.62#ibcon#*before return 0, iclass 27, count 0 2006.218.08:21:51.62#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.218.08:21:51.62#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.218.08:21:51.62#ibcon#about to clear, iclass 27 cls_cnt 0 2006.218.08:21:51.62#ibcon#cleared, iclass 27 cls_cnt 0 2006.218.08:21:51.62$vc4f8/vb=4,4 2006.218.08:21:51.62#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.218.08:21:51.62#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.218.08:21:51.62#ibcon#ireg 11 cls_cnt 2 2006.218.08:21:51.62#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.218.08:21:51.68#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.218.08:21:51.68#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.218.08:21:51.68#ibcon#enter wrdev, iclass 29, count 2 2006.218.08:21:51.68#ibcon#first serial, iclass 29, count 2 2006.218.08:21:51.68#ibcon#enter sib2, iclass 29, count 2 2006.218.08:21:51.68#ibcon#flushed, iclass 29, count 2 2006.218.08:21:51.68#ibcon#about to write, iclass 29, count 2 2006.218.08:21:51.68#ibcon#wrote, iclass 29, count 2 2006.218.08:21:51.68#ibcon#about to read 3, iclass 29, count 2 2006.218.08:21:51.70#ibcon#read 3, iclass 29, count 2 2006.218.08:21:51.70#ibcon#about to read 4, iclass 29, count 2 2006.218.08:21:51.70#ibcon#read 4, iclass 29, count 2 2006.218.08:21:51.70#ibcon#about to read 5, iclass 29, count 2 2006.218.08:21:51.70#ibcon#read 5, iclass 29, count 2 2006.218.08:21:51.70#ibcon#about to read 6, iclass 29, count 2 2006.218.08:21:51.70#ibcon#read 6, iclass 29, count 2 2006.218.08:21:51.70#ibcon#end of sib2, iclass 29, count 2 2006.218.08:21:51.70#ibcon#*mode == 0, iclass 29, count 2 2006.218.08:21:51.70#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.218.08:21:51.70#ibcon#[27=AT04-04\r\n] 2006.218.08:21:51.70#ibcon#*before write, iclass 29, count 2 2006.218.08:21:51.70#ibcon#enter sib2, iclass 29, count 2 2006.218.08:21:51.70#ibcon#flushed, iclass 29, count 2 2006.218.08:21:51.70#ibcon#about to write, iclass 29, count 2 2006.218.08:21:51.70#ibcon#wrote, iclass 29, count 2 2006.218.08:21:51.70#ibcon#about to read 3, iclass 29, count 2 2006.218.08:21:51.73#ibcon#read 3, iclass 29, count 2 2006.218.08:21:51.73#ibcon#about to read 4, iclass 29, count 2 2006.218.08:21:51.73#ibcon#read 4, iclass 29, count 2 2006.218.08:21:51.73#ibcon#about to read 5, iclass 29, count 2 2006.218.08:21:51.73#ibcon#read 5, iclass 29, count 2 2006.218.08:21:51.73#ibcon#about to read 6, iclass 29, count 2 2006.218.08:21:51.73#ibcon#read 6, iclass 29, count 2 2006.218.08:21:51.73#ibcon#end of sib2, iclass 29, count 2 2006.218.08:21:51.73#ibcon#*after write, iclass 29, count 2 2006.218.08:21:51.73#ibcon#*before return 0, iclass 29, count 2 2006.218.08:21:51.73#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.218.08:21:51.73#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.218.08:21:51.73#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.218.08:21:51.73#ibcon#ireg 7 cls_cnt 0 2006.218.08:21:51.73#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.218.08:21:51.85#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.218.08:21:51.85#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.218.08:21:51.85#ibcon#enter wrdev, iclass 29, count 0 2006.218.08:21:51.85#ibcon#first serial, iclass 29, count 0 2006.218.08:21:51.85#ibcon#enter sib2, iclass 29, count 0 2006.218.08:21:51.85#ibcon#flushed, iclass 29, count 0 2006.218.08:21:51.85#ibcon#about to write, iclass 29, count 0 2006.218.08:21:51.85#ibcon#wrote, iclass 29, count 0 2006.218.08:21:51.85#ibcon#about to read 3, iclass 29, count 0 2006.218.08:21:51.87#ibcon#read 3, iclass 29, count 0 2006.218.08:21:51.87#ibcon#about to read 4, iclass 29, count 0 2006.218.08:21:51.87#ibcon#read 4, iclass 29, count 0 2006.218.08:21:51.87#ibcon#about to read 5, iclass 29, count 0 2006.218.08:21:51.87#ibcon#read 5, iclass 29, count 0 2006.218.08:21:51.87#ibcon#about to read 6, iclass 29, count 0 2006.218.08:21:51.87#ibcon#read 6, iclass 29, count 0 2006.218.08:21:51.87#ibcon#end of sib2, iclass 29, count 0 2006.218.08:21:51.87#ibcon#*mode == 0, iclass 29, count 0 2006.218.08:21:51.87#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.218.08:21:51.87#ibcon#[27=USB\r\n] 2006.218.08:21:51.87#ibcon#*before write, iclass 29, count 0 2006.218.08:21:51.87#ibcon#enter sib2, iclass 29, count 0 2006.218.08:21:51.87#ibcon#flushed, iclass 29, count 0 2006.218.08:21:51.87#ibcon#about to write, iclass 29, count 0 2006.218.08:21:51.87#ibcon#wrote, iclass 29, count 0 2006.218.08:21:51.87#ibcon#about to read 3, iclass 29, count 0 2006.218.08:21:51.90#ibcon#read 3, iclass 29, count 0 2006.218.08:21:51.90#ibcon#about to read 4, iclass 29, count 0 2006.218.08:21:51.90#ibcon#read 4, iclass 29, count 0 2006.218.08:21:51.90#ibcon#about to read 5, iclass 29, count 0 2006.218.08:21:51.90#ibcon#read 5, iclass 29, count 0 2006.218.08:21:51.90#ibcon#about to read 6, iclass 29, count 0 2006.218.08:21:51.90#ibcon#read 6, iclass 29, count 0 2006.218.08:21:51.90#ibcon#end of sib2, iclass 29, count 0 2006.218.08:21:51.90#ibcon#*after write, iclass 29, count 0 2006.218.08:21:51.90#ibcon#*before return 0, iclass 29, count 0 2006.218.08:21:51.90#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.218.08:21:51.90#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.218.08:21:51.90#ibcon#about to clear, iclass 29 cls_cnt 0 2006.218.08:21:51.90#ibcon#cleared, iclass 29 cls_cnt 0 2006.218.08:21:51.90$vc4f8/vblo=5,744.99 2006.218.08:21:51.90#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.218.08:21:51.90#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.218.08:21:51.90#ibcon#ireg 17 cls_cnt 0 2006.218.08:21:51.90#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.218.08:21:51.90#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.218.08:21:51.90#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.218.08:21:51.90#ibcon#enter wrdev, iclass 31, count 0 2006.218.08:21:51.90#ibcon#first serial, iclass 31, count 0 2006.218.08:21:51.90#ibcon#enter sib2, iclass 31, count 0 2006.218.08:21:51.90#ibcon#flushed, iclass 31, count 0 2006.218.08:21:51.90#ibcon#about to write, iclass 31, count 0 2006.218.08:21:51.90#ibcon#wrote, iclass 31, count 0 2006.218.08:21:51.90#ibcon#about to read 3, iclass 31, count 0 2006.218.08:21:51.92#ibcon#read 3, iclass 31, count 0 2006.218.08:21:51.92#ibcon#about to read 4, iclass 31, count 0 2006.218.08:21:51.92#ibcon#read 4, iclass 31, count 0 2006.218.08:21:51.92#ibcon#about to read 5, iclass 31, count 0 2006.218.08:21:51.92#ibcon#read 5, iclass 31, count 0 2006.218.08:21:51.92#ibcon#about to read 6, iclass 31, count 0 2006.218.08:21:51.92#ibcon#read 6, iclass 31, count 0 2006.218.08:21:51.92#ibcon#end of sib2, iclass 31, count 0 2006.218.08:21:51.92#ibcon#*mode == 0, iclass 31, count 0 2006.218.08:21:51.92#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.218.08:21:51.92#ibcon#[28=FRQ=05,744.99\r\n] 2006.218.08:21:51.92#ibcon#*before write, iclass 31, count 0 2006.218.08:21:51.92#ibcon#enter sib2, iclass 31, count 0 2006.218.08:21:51.92#ibcon#flushed, iclass 31, count 0 2006.218.08:21:51.92#ibcon#about to write, iclass 31, count 0 2006.218.08:21:51.92#ibcon#wrote, iclass 31, count 0 2006.218.08:21:51.92#ibcon#about to read 3, iclass 31, count 0 2006.218.08:21:51.96#ibcon#read 3, iclass 31, count 0 2006.218.08:21:51.96#ibcon#about to read 4, iclass 31, count 0 2006.218.08:21:51.96#ibcon#read 4, iclass 31, count 0 2006.218.08:21:51.96#ibcon#about to read 5, iclass 31, count 0 2006.218.08:21:51.96#ibcon#read 5, iclass 31, count 0 2006.218.08:21:51.96#ibcon#about to read 6, iclass 31, count 0 2006.218.08:21:51.96#ibcon#read 6, iclass 31, count 0 2006.218.08:21:51.96#ibcon#end of sib2, iclass 31, count 0 2006.218.08:21:51.96#ibcon#*after write, iclass 31, count 0 2006.218.08:21:51.96#ibcon#*before return 0, iclass 31, count 0 2006.218.08:21:51.96#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.218.08:21:51.96#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.218.08:21:51.96#ibcon#about to clear, iclass 31 cls_cnt 0 2006.218.08:21:51.96#ibcon#cleared, iclass 31 cls_cnt 0 2006.218.08:21:51.96$vc4f8/vb=5,4 2006.218.08:21:51.96#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.218.08:21:51.96#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.218.08:21:51.96#ibcon#ireg 11 cls_cnt 2 2006.218.08:21:51.96#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.218.08:21:52.02#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.218.08:21:52.02#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.218.08:21:52.02#ibcon#enter wrdev, iclass 33, count 2 2006.218.08:21:52.02#ibcon#first serial, iclass 33, count 2 2006.218.08:21:52.02#ibcon#enter sib2, iclass 33, count 2 2006.218.08:21:52.02#ibcon#flushed, iclass 33, count 2 2006.218.08:21:52.02#ibcon#about to write, iclass 33, count 2 2006.218.08:21:52.02#ibcon#wrote, iclass 33, count 2 2006.218.08:21:52.02#ibcon#about to read 3, iclass 33, count 2 2006.218.08:21:52.04#ibcon#read 3, iclass 33, count 2 2006.218.08:21:52.04#ibcon#about to read 4, iclass 33, count 2 2006.218.08:21:52.04#ibcon#read 4, iclass 33, count 2 2006.218.08:21:52.04#ibcon#about to read 5, iclass 33, count 2 2006.218.08:21:52.04#ibcon#read 5, iclass 33, count 2 2006.218.08:21:52.04#ibcon#about to read 6, iclass 33, count 2 2006.218.08:21:52.04#ibcon#read 6, iclass 33, count 2 2006.218.08:21:52.04#ibcon#end of sib2, iclass 33, count 2 2006.218.08:21:52.04#ibcon#*mode == 0, iclass 33, count 2 2006.218.08:21:52.04#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.218.08:21:52.04#ibcon#[27=AT05-04\r\n] 2006.218.08:21:52.04#ibcon#*before write, iclass 33, count 2 2006.218.08:21:52.04#ibcon#enter sib2, iclass 33, count 2 2006.218.08:21:52.04#ibcon#flushed, iclass 33, count 2 2006.218.08:21:52.04#ibcon#about to write, iclass 33, count 2 2006.218.08:21:52.04#ibcon#wrote, iclass 33, count 2 2006.218.08:21:52.04#ibcon#about to read 3, iclass 33, count 2 2006.218.08:21:52.07#ibcon#read 3, iclass 33, count 2 2006.218.08:21:52.07#ibcon#about to read 4, iclass 33, count 2 2006.218.08:21:52.07#ibcon#read 4, iclass 33, count 2 2006.218.08:21:52.07#ibcon#about to read 5, iclass 33, count 2 2006.218.08:21:52.07#ibcon#read 5, iclass 33, count 2 2006.218.08:21:52.07#ibcon#about to read 6, iclass 33, count 2 2006.218.08:21:52.07#ibcon#read 6, iclass 33, count 2 2006.218.08:21:52.07#ibcon#end of sib2, iclass 33, count 2 2006.218.08:21:52.07#ibcon#*after write, iclass 33, count 2 2006.218.08:21:52.07#ibcon#*before return 0, iclass 33, count 2 2006.218.08:21:52.07#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.218.08:21:52.07#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.218.08:21:52.07#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.218.08:21:52.07#ibcon#ireg 7 cls_cnt 0 2006.218.08:21:52.07#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.218.08:21:52.19#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.218.08:21:52.19#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.218.08:21:52.19#ibcon#enter wrdev, iclass 33, count 0 2006.218.08:21:52.19#ibcon#first serial, iclass 33, count 0 2006.218.08:21:52.19#ibcon#enter sib2, iclass 33, count 0 2006.218.08:21:52.19#ibcon#flushed, iclass 33, count 0 2006.218.08:21:52.19#ibcon#about to write, iclass 33, count 0 2006.218.08:21:52.19#ibcon#wrote, iclass 33, count 0 2006.218.08:21:52.19#ibcon#about to read 3, iclass 33, count 0 2006.218.08:21:52.21#ibcon#read 3, iclass 33, count 0 2006.218.08:21:52.21#ibcon#about to read 4, iclass 33, count 0 2006.218.08:21:52.21#ibcon#read 4, iclass 33, count 0 2006.218.08:21:52.21#ibcon#about to read 5, iclass 33, count 0 2006.218.08:21:52.21#ibcon#read 5, iclass 33, count 0 2006.218.08:21:52.21#ibcon#about to read 6, iclass 33, count 0 2006.218.08:21:52.21#ibcon#read 6, iclass 33, count 0 2006.218.08:21:52.21#ibcon#end of sib2, iclass 33, count 0 2006.218.08:21:52.21#ibcon#*mode == 0, iclass 33, count 0 2006.218.08:21:52.21#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.218.08:21:52.21#ibcon#[27=USB\r\n] 2006.218.08:21:52.21#ibcon#*before write, iclass 33, count 0 2006.218.08:21:52.21#ibcon#enter sib2, iclass 33, count 0 2006.218.08:21:52.21#ibcon#flushed, iclass 33, count 0 2006.218.08:21:52.21#ibcon#about to write, iclass 33, count 0 2006.218.08:21:52.21#ibcon#wrote, iclass 33, count 0 2006.218.08:21:52.21#ibcon#about to read 3, iclass 33, count 0 2006.218.08:21:52.24#ibcon#read 3, iclass 33, count 0 2006.218.08:21:52.24#ibcon#about to read 4, iclass 33, count 0 2006.218.08:21:52.24#ibcon#read 4, iclass 33, count 0 2006.218.08:21:52.24#ibcon#about to read 5, iclass 33, count 0 2006.218.08:21:52.24#ibcon#read 5, iclass 33, count 0 2006.218.08:21:52.24#ibcon#about to read 6, iclass 33, count 0 2006.218.08:21:52.24#ibcon#read 6, iclass 33, count 0 2006.218.08:21:52.24#ibcon#end of sib2, iclass 33, count 0 2006.218.08:21:52.24#ibcon#*after write, iclass 33, count 0 2006.218.08:21:52.24#ibcon#*before return 0, iclass 33, count 0 2006.218.08:21:52.24#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.218.08:21:52.24#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.218.08:21:52.24#ibcon#about to clear, iclass 33 cls_cnt 0 2006.218.08:21:52.24#ibcon#cleared, iclass 33 cls_cnt 0 2006.218.08:21:52.24$vc4f8/vblo=6,752.99 2006.218.08:21:52.24#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.218.08:21:52.24#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.218.08:21:52.24#ibcon#ireg 17 cls_cnt 0 2006.218.08:21:52.24#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.218.08:21:52.24#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.218.08:21:52.24#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.218.08:21:52.24#ibcon#enter wrdev, iclass 35, count 0 2006.218.08:21:52.24#ibcon#first serial, iclass 35, count 0 2006.218.08:21:52.24#ibcon#enter sib2, iclass 35, count 0 2006.218.08:21:52.24#ibcon#flushed, iclass 35, count 0 2006.218.08:21:52.24#ibcon#about to write, iclass 35, count 0 2006.218.08:21:52.24#ibcon#wrote, iclass 35, count 0 2006.218.08:21:52.24#ibcon#about to read 3, iclass 35, count 0 2006.218.08:21:52.26#ibcon#read 3, iclass 35, count 0 2006.218.08:21:52.26#ibcon#about to read 4, iclass 35, count 0 2006.218.08:21:52.26#ibcon#read 4, iclass 35, count 0 2006.218.08:21:52.26#ibcon#about to read 5, iclass 35, count 0 2006.218.08:21:52.26#ibcon#read 5, iclass 35, count 0 2006.218.08:21:52.26#ibcon#about to read 6, iclass 35, count 0 2006.218.08:21:52.26#ibcon#read 6, iclass 35, count 0 2006.218.08:21:52.26#ibcon#end of sib2, iclass 35, count 0 2006.218.08:21:52.26#ibcon#*mode == 0, iclass 35, count 0 2006.218.08:21:52.26#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.218.08:21:52.26#ibcon#[28=FRQ=06,752.99\r\n] 2006.218.08:21:52.26#ibcon#*before write, iclass 35, count 0 2006.218.08:21:52.26#ibcon#enter sib2, iclass 35, count 0 2006.218.08:21:52.26#ibcon#flushed, iclass 35, count 0 2006.218.08:21:52.26#ibcon#about to write, iclass 35, count 0 2006.218.08:21:52.26#ibcon#wrote, iclass 35, count 0 2006.218.08:21:52.26#ibcon#about to read 3, iclass 35, count 0 2006.218.08:21:52.30#ibcon#read 3, iclass 35, count 0 2006.218.08:21:52.30#ibcon#about to read 4, iclass 35, count 0 2006.218.08:21:52.30#ibcon#read 4, iclass 35, count 0 2006.218.08:21:52.30#ibcon#about to read 5, iclass 35, count 0 2006.218.08:21:52.30#ibcon#read 5, iclass 35, count 0 2006.218.08:21:52.30#ibcon#about to read 6, iclass 35, count 0 2006.218.08:21:52.30#ibcon#read 6, iclass 35, count 0 2006.218.08:21:52.30#ibcon#end of sib2, iclass 35, count 0 2006.218.08:21:52.30#ibcon#*after write, iclass 35, count 0 2006.218.08:21:52.30#ibcon#*before return 0, iclass 35, count 0 2006.218.08:21:52.30#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.218.08:21:52.30#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.218.08:21:52.30#ibcon#about to clear, iclass 35 cls_cnt 0 2006.218.08:21:52.30#ibcon#cleared, iclass 35 cls_cnt 0 2006.218.08:21:52.30$vc4f8/vb=6,4 2006.218.08:21:52.30#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.218.08:21:52.30#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.218.08:21:52.30#ibcon#ireg 11 cls_cnt 2 2006.218.08:21:52.30#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.218.08:21:52.36#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.218.08:21:52.36#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.218.08:21:52.36#ibcon#enter wrdev, iclass 37, count 2 2006.218.08:21:52.36#ibcon#first serial, iclass 37, count 2 2006.218.08:21:52.36#ibcon#enter sib2, iclass 37, count 2 2006.218.08:21:52.36#ibcon#flushed, iclass 37, count 2 2006.218.08:21:52.36#ibcon#about to write, iclass 37, count 2 2006.218.08:21:52.36#ibcon#wrote, iclass 37, count 2 2006.218.08:21:52.36#ibcon#about to read 3, iclass 37, count 2 2006.218.08:21:52.38#ibcon#read 3, iclass 37, count 2 2006.218.08:21:52.38#ibcon#about to read 4, iclass 37, count 2 2006.218.08:21:52.38#ibcon#read 4, iclass 37, count 2 2006.218.08:21:52.38#ibcon#about to read 5, iclass 37, count 2 2006.218.08:21:52.38#ibcon#read 5, iclass 37, count 2 2006.218.08:21:52.38#ibcon#about to read 6, iclass 37, count 2 2006.218.08:21:52.38#ibcon#read 6, iclass 37, count 2 2006.218.08:21:52.38#ibcon#end of sib2, iclass 37, count 2 2006.218.08:21:52.38#ibcon#*mode == 0, iclass 37, count 2 2006.218.08:21:52.38#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.218.08:21:52.38#ibcon#[27=AT06-04\r\n] 2006.218.08:21:52.38#ibcon#*before write, iclass 37, count 2 2006.218.08:21:52.38#ibcon#enter sib2, iclass 37, count 2 2006.218.08:21:52.38#ibcon#flushed, iclass 37, count 2 2006.218.08:21:52.38#ibcon#about to write, iclass 37, count 2 2006.218.08:21:52.38#ibcon#wrote, iclass 37, count 2 2006.218.08:21:52.38#ibcon#about to read 3, iclass 37, count 2 2006.218.08:21:52.41#ibcon#read 3, iclass 37, count 2 2006.218.08:21:52.41#ibcon#about to read 4, iclass 37, count 2 2006.218.08:21:52.41#ibcon#read 4, iclass 37, count 2 2006.218.08:21:52.41#ibcon#about to read 5, iclass 37, count 2 2006.218.08:21:52.41#ibcon#read 5, iclass 37, count 2 2006.218.08:21:52.41#ibcon#about to read 6, iclass 37, count 2 2006.218.08:21:52.41#ibcon#read 6, iclass 37, count 2 2006.218.08:21:52.41#ibcon#end of sib2, iclass 37, count 2 2006.218.08:21:52.41#ibcon#*after write, iclass 37, count 2 2006.218.08:21:52.41#ibcon#*before return 0, iclass 37, count 2 2006.218.08:21:52.41#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.218.08:21:52.41#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.218.08:21:52.41#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.218.08:21:52.41#ibcon#ireg 7 cls_cnt 0 2006.218.08:21:52.41#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.218.08:21:52.53#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.218.08:21:52.53#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.218.08:21:52.53#ibcon#enter wrdev, iclass 37, count 0 2006.218.08:21:52.53#ibcon#first serial, iclass 37, count 0 2006.218.08:21:52.53#ibcon#enter sib2, iclass 37, count 0 2006.218.08:21:52.53#ibcon#flushed, iclass 37, count 0 2006.218.08:21:52.53#ibcon#about to write, iclass 37, count 0 2006.218.08:21:52.53#ibcon#wrote, iclass 37, count 0 2006.218.08:21:52.53#ibcon#about to read 3, iclass 37, count 0 2006.218.08:21:52.55#ibcon#read 3, iclass 37, count 0 2006.218.08:21:52.55#ibcon#about to read 4, iclass 37, count 0 2006.218.08:21:52.55#ibcon#read 4, iclass 37, count 0 2006.218.08:21:52.55#ibcon#about to read 5, iclass 37, count 0 2006.218.08:21:52.55#ibcon#read 5, iclass 37, count 0 2006.218.08:21:52.55#ibcon#about to read 6, iclass 37, count 0 2006.218.08:21:52.55#ibcon#read 6, iclass 37, count 0 2006.218.08:21:52.55#ibcon#end of sib2, iclass 37, count 0 2006.218.08:21:52.55#ibcon#*mode == 0, iclass 37, count 0 2006.218.08:21:52.55#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.218.08:21:52.55#ibcon#[27=USB\r\n] 2006.218.08:21:52.55#ibcon#*before write, iclass 37, count 0 2006.218.08:21:52.55#ibcon#enter sib2, iclass 37, count 0 2006.218.08:21:52.55#ibcon#flushed, iclass 37, count 0 2006.218.08:21:52.55#ibcon#about to write, iclass 37, count 0 2006.218.08:21:52.55#ibcon#wrote, iclass 37, count 0 2006.218.08:21:52.55#ibcon#about to read 3, iclass 37, count 0 2006.218.08:21:52.58#ibcon#read 3, iclass 37, count 0 2006.218.08:21:52.58#ibcon#about to read 4, iclass 37, count 0 2006.218.08:21:52.58#ibcon#read 4, iclass 37, count 0 2006.218.08:21:52.58#ibcon#about to read 5, iclass 37, count 0 2006.218.08:21:52.58#ibcon#read 5, iclass 37, count 0 2006.218.08:21:52.58#ibcon#about to read 6, iclass 37, count 0 2006.218.08:21:52.58#ibcon#read 6, iclass 37, count 0 2006.218.08:21:52.58#ibcon#end of sib2, iclass 37, count 0 2006.218.08:21:52.58#ibcon#*after write, iclass 37, count 0 2006.218.08:21:52.58#ibcon#*before return 0, iclass 37, count 0 2006.218.08:21:52.58#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.218.08:21:52.58#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.218.08:21:52.58#ibcon#about to clear, iclass 37 cls_cnt 0 2006.218.08:21:52.58#ibcon#cleared, iclass 37 cls_cnt 0 2006.218.08:21:52.58$vc4f8/vabw=wide 2006.218.08:21:52.58#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.218.08:21:52.58#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.218.08:21:52.58#ibcon#ireg 8 cls_cnt 0 2006.218.08:21:52.58#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.218.08:21:52.58#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.218.08:21:52.58#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.218.08:21:52.58#ibcon#enter wrdev, iclass 39, count 0 2006.218.08:21:52.58#ibcon#first serial, iclass 39, count 0 2006.218.08:21:52.58#ibcon#enter sib2, iclass 39, count 0 2006.218.08:21:52.58#ibcon#flushed, iclass 39, count 0 2006.218.08:21:52.58#ibcon#about to write, iclass 39, count 0 2006.218.08:21:52.58#ibcon#wrote, iclass 39, count 0 2006.218.08:21:52.58#ibcon#about to read 3, iclass 39, count 0 2006.218.08:21:52.60#ibcon#read 3, iclass 39, count 0 2006.218.08:21:52.60#ibcon#about to read 4, iclass 39, count 0 2006.218.08:21:52.60#ibcon#read 4, iclass 39, count 0 2006.218.08:21:52.60#ibcon#about to read 5, iclass 39, count 0 2006.218.08:21:52.60#ibcon#read 5, iclass 39, count 0 2006.218.08:21:52.60#ibcon#about to read 6, iclass 39, count 0 2006.218.08:21:52.60#ibcon#read 6, iclass 39, count 0 2006.218.08:21:52.60#ibcon#end of sib2, iclass 39, count 0 2006.218.08:21:52.60#ibcon#*mode == 0, iclass 39, count 0 2006.218.08:21:52.60#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.218.08:21:52.60#ibcon#[25=BW32\r\n] 2006.218.08:21:52.60#ibcon#*before write, iclass 39, count 0 2006.218.08:21:52.60#ibcon#enter sib2, iclass 39, count 0 2006.218.08:21:52.60#ibcon#flushed, iclass 39, count 0 2006.218.08:21:52.60#ibcon#about to write, iclass 39, count 0 2006.218.08:21:52.60#ibcon#wrote, iclass 39, count 0 2006.218.08:21:52.60#ibcon#about to read 3, iclass 39, count 0 2006.218.08:21:52.63#ibcon#read 3, iclass 39, count 0 2006.218.08:21:52.63#ibcon#about to read 4, iclass 39, count 0 2006.218.08:21:52.63#ibcon#read 4, iclass 39, count 0 2006.218.08:21:52.63#ibcon#about to read 5, iclass 39, count 0 2006.218.08:21:52.63#ibcon#read 5, iclass 39, count 0 2006.218.08:21:52.63#ibcon#about to read 6, iclass 39, count 0 2006.218.08:21:52.63#ibcon#read 6, iclass 39, count 0 2006.218.08:21:52.63#ibcon#end of sib2, iclass 39, count 0 2006.218.08:21:52.63#ibcon#*after write, iclass 39, count 0 2006.218.08:21:52.63#ibcon#*before return 0, iclass 39, count 0 2006.218.08:21:52.63#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.218.08:21:52.63#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.218.08:21:52.63#ibcon#about to clear, iclass 39 cls_cnt 0 2006.218.08:21:52.63#ibcon#cleared, iclass 39 cls_cnt 0 2006.218.08:21:52.63$vc4f8/vbbw=wide 2006.218.08:21:52.63#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.218.08:21:52.63#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.218.08:21:52.63#ibcon#ireg 8 cls_cnt 0 2006.218.08:21:52.63#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.218.08:21:52.70#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.218.08:21:52.70#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.218.08:21:52.70#ibcon#enter wrdev, iclass 3, count 0 2006.218.08:21:52.70#ibcon#first serial, iclass 3, count 0 2006.218.08:21:52.70#ibcon#enter sib2, iclass 3, count 0 2006.218.08:21:52.70#ibcon#flushed, iclass 3, count 0 2006.218.08:21:52.70#ibcon#about to write, iclass 3, count 0 2006.218.08:21:52.70#ibcon#wrote, iclass 3, count 0 2006.218.08:21:52.70#ibcon#about to read 3, iclass 3, count 0 2006.218.08:21:52.72#ibcon#read 3, iclass 3, count 0 2006.218.08:21:52.72#ibcon#about to read 4, iclass 3, count 0 2006.218.08:21:52.72#ibcon#read 4, iclass 3, count 0 2006.218.08:21:52.72#ibcon#about to read 5, iclass 3, count 0 2006.218.08:21:52.72#ibcon#read 5, iclass 3, count 0 2006.218.08:21:52.72#ibcon#about to read 6, iclass 3, count 0 2006.218.08:21:52.72#ibcon#read 6, iclass 3, count 0 2006.218.08:21:52.72#ibcon#end of sib2, iclass 3, count 0 2006.218.08:21:52.72#ibcon#*mode == 0, iclass 3, count 0 2006.218.08:21:52.72#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.218.08:21:52.72#ibcon#[27=BW32\r\n] 2006.218.08:21:52.72#ibcon#*before write, iclass 3, count 0 2006.218.08:21:52.72#ibcon#enter sib2, iclass 3, count 0 2006.218.08:21:52.72#ibcon#flushed, iclass 3, count 0 2006.218.08:21:52.72#ibcon#about to write, iclass 3, count 0 2006.218.08:21:52.72#ibcon#wrote, iclass 3, count 0 2006.218.08:21:52.72#ibcon#about to read 3, iclass 3, count 0 2006.218.08:21:52.75#ibcon#read 3, iclass 3, count 0 2006.218.08:21:52.75#ibcon#about to read 4, iclass 3, count 0 2006.218.08:21:52.75#ibcon#read 4, iclass 3, count 0 2006.218.08:21:52.75#ibcon#about to read 5, iclass 3, count 0 2006.218.08:21:52.75#ibcon#read 5, iclass 3, count 0 2006.218.08:21:52.75#ibcon#about to read 6, iclass 3, count 0 2006.218.08:21:52.75#ibcon#read 6, iclass 3, count 0 2006.218.08:21:52.75#ibcon#end of sib2, iclass 3, count 0 2006.218.08:21:52.75#ibcon#*after write, iclass 3, count 0 2006.218.08:21:52.75#ibcon#*before return 0, iclass 3, count 0 2006.218.08:21:52.75#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.218.08:21:52.75#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.218.08:21:52.75#ibcon#about to clear, iclass 3 cls_cnt 0 2006.218.08:21:52.75#ibcon#cleared, iclass 3 cls_cnt 0 2006.218.08:21:52.75$4f8m12a/ifd4f 2006.218.08:21:52.75$ifd4f/lo= 2006.218.08:21:52.75$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.218.08:21:52.75$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.218.08:21:52.75$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.218.08:21:52.75$ifd4f/patch= 2006.218.08:21:52.75$ifd4f/patch=lo1,a1,a2,a3,a4 2006.218.08:21:52.75$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.218.08:21:52.75$ifd4f/patch=lo3,a5,a6,a7,a8 2006.218.08:21:52.75$4f8m12a/"form=m,16.000,1:2 2006.218.08:21:52.75$4f8m12a/"tpicd 2006.218.08:21:52.75$4f8m12a/echo=off 2006.218.08:21:52.75$4f8m12a/xlog=off 2006.218.08:21:52.75:!2006.218.08:24:00 2006.218.08:22:18.14#trakl#Source acquired 2006.218.08:22:20.14#flagr#flagr/antenna,acquired 2006.218.08:24:00.00:preob 2006.218.08:24:00.14/onsource/TRACKING 2006.218.08:24:00.14:!2006.218.08:24:10 2006.218.08:24:10.00:data_valid=on 2006.218.08:24:10.00:midob 2006.218.08:24:11.14/onsource/TRACKING 2006.218.08:24:11.14/wx/30.57,1007.6,76 2006.218.08:24:11.30/cable/+6.3823E-03 2006.218.08:24:12.39/va/01,05,usb,yes,33,35 2006.218.08:24:12.39/va/02,04,usb,yes,31,32 2006.218.08:24:12.39/va/03,04,usb,yes,29,29 2006.218.08:24:12.39/va/04,04,usb,yes,32,35 2006.218.08:24:12.39/va/05,07,usb,yes,35,37 2006.218.08:24:12.39/va/06,06,usb,yes,34,34 2006.218.08:24:12.39/va/07,06,usb,yes,35,34 2006.218.08:24:12.39/va/08,07,usb,yes,33,32 2006.218.08:24:12.62/valo/01,532.99,yes,locked 2006.218.08:24:12.62/valo/02,572.99,yes,locked 2006.218.08:24:12.62/valo/03,672.99,yes,locked 2006.218.08:24:12.62/valo/04,832.99,yes,locked 2006.218.08:24:12.62/valo/05,652.99,yes,locked 2006.218.08:24:12.62/valo/06,772.99,yes,locked 2006.218.08:24:12.62/valo/07,832.99,yes,locked 2006.218.08:24:12.62/valo/08,852.99,yes,locked 2006.218.08:24:13.71/vb/01,04,usb,yes,31,30 2006.218.08:24:13.71/vb/02,04,usb,yes,33,34 2006.218.08:24:13.71/vb/03,04,usb,yes,29,33 2006.218.08:24:13.71/vb/04,04,usb,yes,30,30 2006.218.08:24:13.71/vb/05,04,usb,yes,29,33 2006.218.08:24:13.71/vb/06,04,usb,yes,30,33 2006.218.08:24:13.71/vb/07,04,usb,yes,32,32 2006.218.08:24:13.71/vb/08,04,usb,yes,29,33 2006.218.08:24:13.94/vblo/01,632.99,yes,locked 2006.218.08:24:13.94/vblo/02,640.99,yes,locked 2006.218.08:24:13.94/vblo/03,656.99,yes,locked 2006.218.08:24:13.94/vblo/04,712.99,yes,locked 2006.218.08:24:13.94/vblo/05,744.99,yes,locked 2006.218.08:24:13.94/vblo/06,752.99,yes,locked 2006.218.08:24:13.94/vblo/07,734.99,yes,locked 2006.218.08:24:13.94/vblo/08,744.99,yes,locked 2006.218.08:24:14.09/vabw/8 2006.218.08:24:14.24/vbbw/8 2006.218.08:24:14.33/xfe/off,on,15.2 2006.218.08:24:14.72/ifatt/23,28,28,28 2006.218.08:24:15.08/fmout-gps/S +4.55E-07 2006.218.08:24:15.12:!2006.218.08:25:10 2006.218.08:25:10.02:data_valid=off 2006.218.08:25:10.02:postob 2006.218.08:25:10.11/cable/+6.3852E-03 2006.218.08:25:10.11/wx/30.54,1007.6,76 2006.218.08:25:11.07/fmout-gps/S +4.55E-07 2006.218.08:25:11.07:scan_name=218-0826,k06218,70 2006.218.08:25:11.07:source=1116+128,111857.30,123441.7,2000.0,ccw 2006.218.08:25:11.14#flagr#flagr/antenna,new-source 2006.218.08:25:12.14:checkk5 2006.218.08:25:12.49/chk_autoobs//k5ts1/ autoobs is running! 2006.218.08:25:12.86/chk_autoobs//k5ts2/ autoobs is running! 2006.218.08:25:13.23/chk_autoobs//k5ts3/ autoobs is running! 2006.218.08:25:13.60/chk_autoobs//k5ts4/ autoobs is running! 2006.218.08:25:13.97/chk_obsdata//k5ts1/T2180824??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.08:25:14.34/chk_obsdata//k5ts2/T2180824??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.08:25:14.71/chk_obsdata//k5ts3/T2180824??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.08:25:15.08/chk_obsdata//k5ts4/T2180824??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.218.08:25:15.76/k5log//k5ts1_log_newline 2006.218.08:25:16.46/k5log//k5ts2_log_newline 2006.218.08:25:17.15/k5log//k5ts3_log_newline 2006.218.08:25:17.83/k5log//k5ts4_log_newline 2006.218.08:25:17.86/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.218.08:25:17.86:4f8m12a=3 2006.218.08:25:17.86$4f8m12a/echo=on 2006.218.08:25:17.86$4f8m12a/pcalon 2006.218.08:25:17.86$pcalon/"no phase cal control is implemented here 2006.218.08:25:17.86$4f8m12a/"tpicd=stop 2006.218.08:25:17.86$4f8m12a/vc4f8 2006.218.08:25:17.86$vc4f8/valo=1,532.99 2006.218.08:25:17.86#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.218.08:25:17.86#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.218.08:25:17.86#ibcon#ireg 17 cls_cnt 0 2006.218.08:25:17.86#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.218.08:25:17.86#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.218.08:25:17.86#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.218.08:25:17.86#ibcon#enter wrdev, iclass 16, count 0 2006.218.08:25:17.86#ibcon#first serial, iclass 16, count 0 2006.218.08:25:17.86#ibcon#enter sib2, iclass 16, count 0 2006.218.08:25:17.86#ibcon#flushed, iclass 16, count 0 2006.218.08:25:17.86#ibcon#about to write, iclass 16, count 0 2006.218.08:25:17.86#ibcon#wrote, iclass 16, count 0 2006.218.08:25:17.86#ibcon#about to read 3, iclass 16, count 0 2006.218.08:25:17.87#ibcon#read 3, iclass 16, count 0 2006.218.08:25:17.87#ibcon#about to read 4, iclass 16, count 0 2006.218.08:25:17.87#ibcon#read 4, iclass 16, count 0 2006.218.08:25:17.88#ibcon#about to read 5, iclass 16, count 0 2006.218.08:25:17.88#ibcon#read 5, iclass 16, count 0 2006.218.08:25:17.88#ibcon#about to read 6, iclass 16, count 0 2006.218.08:25:17.88#ibcon#read 6, iclass 16, count 0 2006.218.08:25:17.88#ibcon#end of sib2, iclass 16, count 0 2006.218.08:25:17.88#ibcon#*mode == 0, iclass 16, count 0 2006.218.08:25:17.88#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.218.08:25:17.88#ibcon#[26=FRQ=01,532.99\r\n] 2006.218.08:25:17.88#ibcon#*before write, iclass 16, count 0 2006.218.08:25:17.88#ibcon#enter sib2, iclass 16, count 0 2006.218.08:25:17.88#ibcon#flushed, iclass 16, count 0 2006.218.08:25:17.88#ibcon#about to write, iclass 16, count 0 2006.218.08:25:17.88#ibcon#wrote, iclass 16, count 0 2006.218.08:25:17.88#ibcon#about to read 3, iclass 16, count 0 2006.218.08:25:17.92#ibcon#read 3, iclass 16, count 0 2006.218.08:25:17.92#ibcon#about to read 4, iclass 16, count 0 2006.218.08:25:17.92#ibcon#read 4, iclass 16, count 0 2006.218.08:25:17.92#ibcon#about to read 5, iclass 16, count 0 2006.218.08:25:17.93#ibcon#read 5, iclass 16, count 0 2006.218.08:25:17.93#ibcon#about to read 6, iclass 16, count 0 2006.218.08:25:17.93#ibcon#read 6, iclass 16, count 0 2006.218.08:25:17.93#ibcon#end of sib2, iclass 16, count 0 2006.218.08:25:17.93#ibcon#*after write, iclass 16, count 0 2006.218.08:25:17.93#ibcon#*before return 0, iclass 16, count 0 2006.218.08:25:17.93#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.218.08:25:17.93#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.218.08:25:17.93#ibcon#about to clear, iclass 16 cls_cnt 0 2006.218.08:25:17.93#ibcon#cleared, iclass 16 cls_cnt 0 2006.218.08:25:17.93$vc4f8/va=1,5 2006.218.08:25:17.93#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.218.08:25:17.93#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.218.08:25:17.93#ibcon#ireg 11 cls_cnt 2 2006.218.08:25:17.93#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.218.08:25:17.93#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.218.08:25:17.93#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.218.08:25:17.93#ibcon#enter wrdev, iclass 18, count 2 2006.218.08:25:17.93#ibcon#first serial, iclass 18, count 2 2006.218.08:25:17.93#ibcon#enter sib2, iclass 18, count 2 2006.218.08:25:17.93#ibcon#flushed, iclass 18, count 2 2006.218.08:25:17.93#ibcon#about to write, iclass 18, count 2 2006.218.08:25:17.93#ibcon#wrote, iclass 18, count 2 2006.218.08:25:17.93#ibcon#about to read 3, iclass 18, count 2 2006.218.08:25:17.94#ibcon#read 3, iclass 18, count 2 2006.218.08:25:17.94#ibcon#about to read 4, iclass 18, count 2 2006.218.08:25:17.94#ibcon#read 4, iclass 18, count 2 2006.218.08:25:17.95#ibcon#about to read 5, iclass 18, count 2 2006.218.08:25:17.95#ibcon#read 5, iclass 18, count 2 2006.218.08:25:17.95#ibcon#about to read 6, iclass 18, count 2 2006.218.08:25:17.95#ibcon#read 6, iclass 18, count 2 2006.218.08:25:17.95#ibcon#end of sib2, iclass 18, count 2 2006.218.08:25:17.95#ibcon#*mode == 0, iclass 18, count 2 2006.218.08:25:17.95#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.218.08:25:17.95#ibcon#[25=AT01-05\r\n] 2006.218.08:25:17.95#ibcon#*before write, iclass 18, count 2 2006.218.08:25:17.95#ibcon#enter sib2, iclass 18, count 2 2006.218.08:25:17.95#ibcon#flushed, iclass 18, count 2 2006.218.08:25:17.95#ibcon#about to write, iclass 18, count 2 2006.218.08:25:17.95#ibcon#wrote, iclass 18, count 2 2006.218.08:25:17.95#ibcon#about to read 3, iclass 18, count 2 2006.218.08:25:17.97#ibcon#read 3, iclass 18, count 2 2006.218.08:25:17.97#ibcon#about to read 4, iclass 18, count 2 2006.218.08:25:17.97#ibcon#read 4, iclass 18, count 2 2006.218.08:25:17.97#ibcon#about to read 5, iclass 18, count 2 2006.218.08:25:17.98#ibcon#read 5, iclass 18, count 2 2006.218.08:25:17.98#ibcon#about to read 6, iclass 18, count 2 2006.218.08:25:17.98#ibcon#read 6, iclass 18, count 2 2006.218.08:25:17.98#ibcon#end of sib2, iclass 18, count 2 2006.218.08:25:17.98#ibcon#*after write, iclass 18, count 2 2006.218.08:25:17.98#ibcon#*before return 0, iclass 18, count 2 2006.218.08:25:17.98#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.218.08:25:17.98#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.218.08:25:17.98#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.218.08:25:17.98#ibcon#ireg 7 cls_cnt 0 2006.218.08:25:17.98#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.218.08:25:18.10#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.218.08:25:18.10#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.218.08:25:18.10#ibcon#enter wrdev, iclass 18, count 0 2006.218.08:25:18.10#ibcon#first serial, iclass 18, count 0 2006.218.08:25:18.10#ibcon#enter sib2, iclass 18, count 0 2006.218.08:25:18.10#ibcon#flushed, iclass 18, count 0 2006.218.08:25:18.10#ibcon#about to write, iclass 18, count 0 2006.218.08:25:18.10#ibcon#wrote, iclass 18, count 0 2006.218.08:25:18.10#ibcon#about to read 3, iclass 18, count 0 2006.218.08:25:18.11#ibcon#read 3, iclass 18, count 0 2006.218.08:25:18.11#ibcon#about to read 4, iclass 18, count 0 2006.218.08:25:18.11#ibcon#read 4, iclass 18, count 0 2006.218.08:25:18.12#ibcon#about to read 5, iclass 18, count 0 2006.218.08:25:18.12#ibcon#read 5, iclass 18, count 0 2006.218.08:25:18.12#ibcon#about to read 6, iclass 18, count 0 2006.218.08:25:18.12#ibcon#read 6, iclass 18, count 0 2006.218.08:25:18.12#ibcon#end of sib2, iclass 18, count 0 2006.218.08:25:18.12#ibcon#*mode == 0, iclass 18, count 0 2006.218.08:25:18.12#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.218.08:25:18.12#ibcon#[25=USB\r\n] 2006.218.08:25:18.12#ibcon#*before write, iclass 18, count 0 2006.218.08:25:18.12#ibcon#enter sib2, iclass 18, count 0 2006.218.08:25:18.12#ibcon#flushed, iclass 18, count 0 2006.218.08:25:18.12#ibcon#about to write, iclass 18, count 0 2006.218.08:25:18.12#ibcon#wrote, iclass 18, count 0 2006.218.08:25:18.12#ibcon#about to read 3, iclass 18, count 0 2006.218.08:25:18.14#ibcon#read 3, iclass 18, count 0 2006.218.08:25:18.14#ibcon#about to read 4, iclass 18, count 0 2006.218.08:25:18.14#ibcon#read 4, iclass 18, count 0 2006.218.08:25:18.14#ibcon#about to read 5, iclass 18, count 0 2006.218.08:25:18.14#ibcon#read 5, iclass 18, count 0 2006.218.08:25:18.14#ibcon#about to read 6, iclass 18, count 0 2006.218.08:25:18.15#ibcon#read 6, iclass 18, count 0 2006.218.08:25:18.15#ibcon#end of sib2, iclass 18, count 0 2006.218.08:25:18.15#ibcon#*after write, iclass 18, count 0 2006.218.08:25:18.15#ibcon#*before return 0, iclass 18, count 0 2006.218.08:25:18.15#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.218.08:25:18.15#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.218.08:25:18.15#ibcon#about to clear, iclass 18 cls_cnt 0 2006.218.08:25:18.15#ibcon#cleared, iclass 18 cls_cnt 0 2006.218.08:25:18.15$vc4f8/valo=2,572.99 2006.218.08:25:18.15#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.218.08:25:18.15#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.218.08:25:18.15#ibcon#ireg 17 cls_cnt 0 2006.218.08:25:18.15#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.218.08:25:18.15#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.218.08:25:18.15#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.218.08:25:18.15#ibcon#enter wrdev, iclass 20, count 0 2006.218.08:25:18.15#ibcon#first serial, iclass 20, count 0 2006.218.08:25:18.15#ibcon#enter sib2, iclass 20, count 0 2006.218.08:25:18.15#ibcon#flushed, iclass 20, count 0 2006.218.08:25:18.15#ibcon#about to write, iclass 20, count 0 2006.218.08:25:18.15#ibcon#wrote, iclass 20, count 0 2006.218.08:25:18.15#ibcon#about to read 3, iclass 20, count 0 2006.218.08:25:18.17#ibcon#read 3, iclass 20, count 0 2006.218.08:25:18.17#ibcon#about to read 4, iclass 20, count 0 2006.218.08:25:18.17#ibcon#read 4, iclass 20, count 0 2006.218.08:25:18.17#ibcon#about to read 5, iclass 20, count 0 2006.218.08:25:18.17#ibcon#read 5, iclass 20, count 0 2006.218.08:25:18.17#ibcon#about to read 6, iclass 20, count 0 2006.218.08:25:18.17#ibcon#read 6, iclass 20, count 0 2006.218.08:25:18.17#ibcon#end of sib2, iclass 20, count 0 2006.218.08:25:18.17#ibcon#*mode == 0, iclass 20, count 0 2006.218.08:25:18.17#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.218.08:25:18.17#ibcon#[26=FRQ=02,572.99\r\n] 2006.218.08:25:18.17#ibcon#*before write, iclass 20, count 0 2006.218.08:25:18.17#ibcon#enter sib2, iclass 20, count 0 2006.218.08:25:18.17#ibcon#flushed, iclass 20, count 0 2006.218.08:25:18.17#ibcon#about to write, iclass 20, count 0 2006.218.08:25:18.17#ibcon#wrote, iclass 20, count 0 2006.218.08:25:18.17#ibcon#about to read 3, iclass 20, count 0 2006.218.08:25:18.21#ibcon#read 3, iclass 20, count 0 2006.218.08:25:18.21#ibcon#about to read 4, iclass 20, count 0 2006.218.08:25:18.22#ibcon#read 4, iclass 20, count 0 2006.218.08:25:18.22#ibcon#about to read 5, iclass 20, count 0 2006.218.08:25:18.22#ibcon#read 5, iclass 20, count 0 2006.218.08:25:18.22#ibcon#about to read 6, iclass 20, count 0 2006.218.08:25:18.22#ibcon#read 6, iclass 20, count 0 2006.218.08:25:18.22#ibcon#end of sib2, iclass 20, count 0 2006.218.08:25:18.22#ibcon#*after write, iclass 20, count 0 2006.218.08:25:18.22#ibcon#*before return 0, iclass 20, count 0 2006.218.08:25:18.22#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.218.08:25:18.22#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.218.08:25:18.22#ibcon#about to clear, iclass 20 cls_cnt 0 2006.218.08:25:18.22#ibcon#cleared, iclass 20 cls_cnt 0 2006.218.08:25:18.22$vc4f8/va=2,4 2006.218.08:25:18.22#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.218.08:25:18.22#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.218.08:25:18.22#ibcon#ireg 11 cls_cnt 2 2006.218.08:25:18.22#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.218.08:25:18.27#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.218.08:25:18.27#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.218.08:25:18.27#ibcon#enter wrdev, iclass 22, count 2 2006.218.08:25:18.27#ibcon#first serial, iclass 22, count 2 2006.218.08:25:18.27#ibcon#enter sib2, iclass 22, count 2 2006.218.08:25:18.27#ibcon#flushed, iclass 22, count 2 2006.218.08:25:18.27#ibcon#about to write, iclass 22, count 2 2006.218.08:25:18.27#ibcon#wrote, iclass 22, count 2 2006.218.08:25:18.27#ibcon#about to read 3, iclass 22, count 2 2006.218.08:25:18.28#ibcon#read 3, iclass 22, count 2 2006.218.08:25:18.28#ibcon#about to read 4, iclass 22, count 2 2006.218.08:25:18.29#ibcon#read 4, iclass 22, count 2 2006.218.08:25:18.29#ibcon#about to read 5, iclass 22, count 2 2006.218.08:25:18.29#ibcon#read 5, iclass 22, count 2 2006.218.08:25:18.29#ibcon#about to read 6, iclass 22, count 2 2006.218.08:25:18.29#ibcon#read 6, iclass 22, count 2 2006.218.08:25:18.29#ibcon#end of sib2, iclass 22, count 2 2006.218.08:25:18.29#ibcon#*mode == 0, iclass 22, count 2 2006.218.08:25:18.29#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.218.08:25:18.29#ibcon#[25=AT02-04\r\n] 2006.218.08:25:18.29#ibcon#*before write, iclass 22, count 2 2006.218.08:25:18.29#ibcon#enter sib2, iclass 22, count 2 2006.218.08:25:18.29#ibcon#flushed, iclass 22, count 2 2006.218.08:25:18.29#ibcon#about to write, iclass 22, count 2 2006.218.08:25:18.29#ibcon#wrote, iclass 22, count 2 2006.218.08:25:18.29#ibcon#about to read 3, iclass 22, count 2 2006.218.08:25:18.31#ibcon#read 3, iclass 22, count 2 2006.218.08:25:18.31#ibcon#about to read 4, iclass 22, count 2 2006.218.08:25:18.32#ibcon#read 4, iclass 22, count 2 2006.218.08:25:18.32#ibcon#about to read 5, iclass 22, count 2 2006.218.08:25:18.32#ibcon#read 5, iclass 22, count 2 2006.218.08:25:18.32#ibcon#about to read 6, iclass 22, count 2 2006.218.08:25:18.32#ibcon#read 6, iclass 22, count 2 2006.218.08:25:18.32#ibcon#end of sib2, iclass 22, count 2 2006.218.08:25:18.32#ibcon#*after write, iclass 22, count 2 2006.218.08:25:18.32#ibcon#*before return 0, iclass 22, count 2 2006.218.08:25:18.32#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.218.08:25:18.32#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.218.08:25:18.32#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.218.08:25:18.32#ibcon#ireg 7 cls_cnt 0 2006.218.08:25:18.32#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.218.08:25:18.43#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.218.08:25:18.43#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.218.08:25:18.43#ibcon#enter wrdev, iclass 22, count 0 2006.218.08:25:18.43#ibcon#first serial, iclass 22, count 0 2006.218.08:25:18.43#ibcon#enter sib2, iclass 22, count 0 2006.218.08:25:18.44#ibcon#flushed, iclass 22, count 0 2006.218.08:25:18.44#ibcon#about to write, iclass 22, count 0 2006.218.08:25:18.44#ibcon#wrote, iclass 22, count 0 2006.218.08:25:18.44#ibcon#about to read 3, iclass 22, count 0 2006.218.08:25:18.45#ibcon#read 3, iclass 22, count 0 2006.218.08:25:18.45#ibcon#about to read 4, iclass 22, count 0 2006.218.08:25:18.45#ibcon#read 4, iclass 22, count 0 2006.218.08:25:18.45#ibcon#about to read 5, iclass 22, count 0 2006.218.08:25:18.46#ibcon#read 5, iclass 22, count 0 2006.218.08:25:18.46#ibcon#about to read 6, iclass 22, count 0 2006.218.08:25:18.46#ibcon#read 6, iclass 22, count 0 2006.218.08:25:18.46#ibcon#end of sib2, iclass 22, count 0 2006.218.08:25:18.46#ibcon#*mode == 0, iclass 22, count 0 2006.218.08:25:18.46#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.218.08:25:18.46#ibcon#[25=USB\r\n] 2006.218.08:25:18.46#ibcon#*before write, iclass 22, count 0 2006.218.08:25:18.46#ibcon#enter sib2, iclass 22, count 0 2006.218.08:25:18.46#ibcon#flushed, iclass 22, count 0 2006.218.08:25:18.46#ibcon#about to write, iclass 22, count 0 2006.218.08:25:18.46#ibcon#wrote, iclass 22, count 0 2006.218.08:25:18.46#ibcon#about to read 3, iclass 22, count 0 2006.218.08:25:18.48#ibcon#read 3, iclass 22, count 0 2006.218.08:25:18.48#ibcon#about to read 4, iclass 22, count 0 2006.218.08:25:18.48#ibcon#read 4, iclass 22, count 0 2006.218.08:25:18.48#ibcon#about to read 5, iclass 22, count 0 2006.218.08:25:18.49#ibcon#read 5, iclass 22, count 0 2006.218.08:25:18.49#ibcon#about to read 6, iclass 22, count 0 2006.218.08:25:18.49#ibcon#read 6, iclass 22, count 0 2006.218.08:25:18.49#ibcon#end of sib2, iclass 22, count 0 2006.218.08:25:18.49#ibcon#*after write, iclass 22, count 0 2006.218.08:25:18.49#ibcon#*before return 0, iclass 22, count 0 2006.218.08:25:18.49#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.218.08:25:18.49#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.218.08:25:18.49#ibcon#about to clear, iclass 22 cls_cnt 0 2006.218.08:25:18.49#ibcon#cleared, iclass 22 cls_cnt 0 2006.218.08:25:18.49$vc4f8/valo=3,672.99 2006.218.08:25:18.49#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.218.08:25:18.49#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.218.08:25:18.49#ibcon#ireg 17 cls_cnt 0 2006.218.08:25:18.49#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.218.08:25:18.49#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.218.08:25:18.49#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.218.08:25:18.49#ibcon#enter wrdev, iclass 24, count 0 2006.218.08:25:18.49#ibcon#first serial, iclass 24, count 0 2006.218.08:25:18.49#ibcon#enter sib2, iclass 24, count 0 2006.218.08:25:18.49#ibcon#flushed, iclass 24, count 0 2006.218.08:25:18.49#ibcon#about to write, iclass 24, count 0 2006.218.08:25:18.49#ibcon#wrote, iclass 24, count 0 2006.218.08:25:18.49#ibcon#about to read 3, iclass 24, count 0 2006.218.08:25:18.51#ibcon#read 3, iclass 24, count 0 2006.218.08:25:18.51#ibcon#about to read 4, iclass 24, count 0 2006.218.08:25:18.51#ibcon#read 4, iclass 24, count 0 2006.218.08:25:18.51#ibcon#about to read 5, iclass 24, count 0 2006.218.08:25:18.51#ibcon#read 5, iclass 24, count 0 2006.218.08:25:18.51#ibcon#about to read 6, iclass 24, count 0 2006.218.08:25:18.51#ibcon#read 6, iclass 24, count 0 2006.218.08:25:18.51#ibcon#end of sib2, iclass 24, count 0 2006.218.08:25:18.51#ibcon#*mode == 0, iclass 24, count 0 2006.218.08:25:18.51#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.218.08:25:18.51#ibcon#[26=FRQ=03,672.99\r\n] 2006.218.08:25:18.51#ibcon#*before write, iclass 24, count 0 2006.218.08:25:18.51#ibcon#enter sib2, iclass 24, count 0 2006.218.08:25:18.51#ibcon#flushed, iclass 24, count 0 2006.218.08:25:18.51#ibcon#about to write, iclass 24, count 0 2006.218.08:25:18.51#ibcon#wrote, iclass 24, count 0 2006.218.08:25:18.51#ibcon#about to read 3, iclass 24, count 0 2006.218.08:25:18.55#ibcon#read 3, iclass 24, count 0 2006.218.08:25:18.55#ibcon#about to read 4, iclass 24, count 0 2006.218.08:25:18.56#ibcon#read 4, iclass 24, count 0 2006.218.08:25:18.56#ibcon#about to read 5, iclass 24, count 0 2006.218.08:25:18.56#ibcon#read 5, iclass 24, count 0 2006.218.08:25:18.56#ibcon#about to read 6, iclass 24, count 0 2006.218.08:25:18.56#ibcon#read 6, iclass 24, count 0 2006.218.08:25:18.56#ibcon#end of sib2, iclass 24, count 0 2006.218.08:25:18.56#ibcon#*after write, iclass 24, count 0 2006.218.08:25:18.56#ibcon#*before return 0, iclass 24, count 0 2006.218.08:25:18.56#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.218.08:25:18.56#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.218.08:25:18.56#ibcon#about to clear, iclass 24 cls_cnt 0 2006.218.08:25:18.56#ibcon#cleared, iclass 24 cls_cnt 0 2006.218.08:25:18.56$vc4f8/va=3,4 2006.218.08:25:18.56#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.218.08:25:18.56#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.218.08:25:18.56#ibcon#ireg 11 cls_cnt 2 2006.218.08:25:18.56#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.218.08:25:18.61#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.218.08:25:18.61#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.218.08:25:18.61#ibcon#enter wrdev, iclass 26, count 2 2006.218.08:25:18.61#ibcon#first serial, iclass 26, count 2 2006.218.08:25:18.61#ibcon#enter sib2, iclass 26, count 2 2006.218.08:25:18.61#ibcon#flushed, iclass 26, count 2 2006.218.08:25:18.61#ibcon#about to write, iclass 26, count 2 2006.218.08:25:18.61#ibcon#wrote, iclass 26, count 2 2006.218.08:25:18.61#ibcon#about to read 3, iclass 26, count 2 2006.218.08:25:18.62#ibcon#read 3, iclass 26, count 2 2006.218.08:25:18.62#ibcon#about to read 4, iclass 26, count 2 2006.218.08:25:18.63#ibcon#read 4, iclass 26, count 2 2006.218.08:25:18.63#ibcon#about to read 5, iclass 26, count 2 2006.218.08:25:18.63#ibcon#read 5, iclass 26, count 2 2006.218.08:25:18.63#ibcon#about to read 6, iclass 26, count 2 2006.218.08:25:18.63#ibcon#read 6, iclass 26, count 2 2006.218.08:25:18.63#ibcon#end of sib2, iclass 26, count 2 2006.218.08:25:18.63#ibcon#*mode == 0, iclass 26, count 2 2006.218.08:25:18.63#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.218.08:25:18.63#ibcon#[25=AT03-04\r\n] 2006.218.08:25:18.63#ibcon#*before write, iclass 26, count 2 2006.218.08:25:18.63#ibcon#enter sib2, iclass 26, count 2 2006.218.08:25:18.63#ibcon#flushed, iclass 26, count 2 2006.218.08:25:18.63#ibcon#about to write, iclass 26, count 2 2006.218.08:25:18.63#ibcon#wrote, iclass 26, count 2 2006.218.08:25:18.63#ibcon#about to read 3, iclass 26, count 2 2006.218.08:25:18.65#ibcon#read 3, iclass 26, count 2 2006.218.08:25:18.65#ibcon#about to read 4, iclass 26, count 2 2006.218.08:25:18.66#ibcon#read 4, iclass 26, count 2 2006.218.08:25:18.66#ibcon#about to read 5, iclass 26, count 2 2006.218.08:25:18.66#ibcon#read 5, iclass 26, count 2 2006.218.08:25:18.66#ibcon#about to read 6, iclass 26, count 2 2006.218.08:25:18.66#ibcon#read 6, iclass 26, count 2 2006.218.08:25:18.66#ibcon#end of sib2, iclass 26, count 2 2006.218.08:25:18.66#ibcon#*after write, iclass 26, count 2 2006.218.08:25:18.66#ibcon#*before return 0, iclass 26, count 2 2006.218.08:25:18.66#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.218.08:25:18.66#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.218.08:25:18.66#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.218.08:25:18.66#ibcon#ireg 7 cls_cnt 0 2006.218.08:25:18.66#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.218.08:25:18.77#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.218.08:25:18.77#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.218.08:25:18.77#ibcon#enter wrdev, iclass 26, count 0 2006.218.08:25:18.77#ibcon#first serial, iclass 26, count 0 2006.218.08:25:18.77#ibcon#enter sib2, iclass 26, count 0 2006.218.08:25:18.78#ibcon#flushed, iclass 26, count 0 2006.218.08:25:18.78#ibcon#about to write, iclass 26, count 0 2006.218.08:25:18.78#ibcon#wrote, iclass 26, count 0 2006.218.08:25:18.78#ibcon#about to read 3, iclass 26, count 0 2006.218.08:25:18.79#ibcon#read 3, iclass 26, count 0 2006.218.08:25:18.79#ibcon#about to read 4, iclass 26, count 0 2006.218.08:25:18.79#ibcon#read 4, iclass 26, count 0 2006.218.08:25:18.79#ibcon#about to read 5, iclass 26, count 0 2006.218.08:25:18.80#ibcon#read 5, iclass 26, count 0 2006.218.08:25:18.80#ibcon#about to read 6, iclass 26, count 0 2006.218.08:25:18.80#ibcon#read 6, iclass 26, count 0 2006.218.08:25:18.80#ibcon#end of sib2, iclass 26, count 0 2006.218.08:25:18.80#ibcon#*mode == 0, iclass 26, count 0 2006.218.08:25:18.80#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.218.08:25:18.80#ibcon#[25=USB\r\n] 2006.218.08:25:18.80#ibcon#*before write, iclass 26, count 0 2006.218.08:25:18.80#ibcon#enter sib2, iclass 26, count 0 2006.218.08:25:18.80#ibcon#flushed, iclass 26, count 0 2006.218.08:25:18.80#ibcon#about to write, iclass 26, count 0 2006.218.08:25:18.80#ibcon#wrote, iclass 26, count 0 2006.218.08:25:18.80#ibcon#about to read 3, iclass 26, count 0 2006.218.08:25:18.82#ibcon#read 3, iclass 26, count 0 2006.218.08:25:18.82#ibcon#about to read 4, iclass 26, count 0 2006.218.08:25:18.82#ibcon#read 4, iclass 26, count 0 2006.218.08:25:18.82#ibcon#about to read 5, iclass 26, count 0 2006.218.08:25:18.83#ibcon#read 5, iclass 26, count 0 2006.218.08:25:18.83#ibcon#about to read 6, iclass 26, count 0 2006.218.08:25:18.83#ibcon#read 6, iclass 26, count 0 2006.218.08:25:18.83#ibcon#end of sib2, iclass 26, count 0 2006.218.08:25:18.83#ibcon#*after write, iclass 26, count 0 2006.218.08:25:18.83#ibcon#*before return 0, iclass 26, count 0 2006.218.08:25:18.83#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.218.08:25:18.83#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.218.08:25:18.83#ibcon#about to clear, iclass 26 cls_cnt 0 2006.218.08:25:18.83#ibcon#cleared, iclass 26 cls_cnt 0 2006.218.08:25:18.83$vc4f8/valo=4,832.99 2006.218.08:25:18.83#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.218.08:25:18.83#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.218.08:25:18.83#ibcon#ireg 17 cls_cnt 0 2006.218.08:25:18.83#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.218.08:25:18.83#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.218.08:25:18.83#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.218.08:25:18.83#ibcon#enter wrdev, iclass 28, count 0 2006.218.08:25:18.83#ibcon#first serial, iclass 28, count 0 2006.218.08:25:18.83#ibcon#enter sib2, iclass 28, count 0 2006.218.08:25:18.83#ibcon#flushed, iclass 28, count 0 2006.218.08:25:18.83#ibcon#about to write, iclass 28, count 0 2006.218.08:25:18.83#ibcon#wrote, iclass 28, count 0 2006.218.08:25:18.83#ibcon#about to read 3, iclass 28, count 0 2006.218.08:25:18.85#ibcon#read 3, iclass 28, count 0 2006.218.08:25:18.85#ibcon#about to read 4, iclass 28, count 0 2006.218.08:25:18.85#ibcon#read 4, iclass 28, count 0 2006.218.08:25:18.85#ibcon#about to read 5, iclass 28, count 0 2006.218.08:25:18.85#ibcon#read 5, iclass 28, count 0 2006.218.08:25:18.85#ibcon#about to read 6, iclass 28, count 0 2006.218.08:25:18.85#ibcon#read 6, iclass 28, count 0 2006.218.08:25:18.85#ibcon#end of sib2, iclass 28, count 0 2006.218.08:25:18.85#ibcon#*mode == 0, iclass 28, count 0 2006.218.08:25:18.85#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.218.08:25:18.85#ibcon#[26=FRQ=04,832.99\r\n] 2006.218.08:25:18.85#ibcon#*before write, iclass 28, count 0 2006.218.08:25:18.85#ibcon#enter sib2, iclass 28, count 0 2006.218.08:25:18.85#ibcon#flushed, iclass 28, count 0 2006.218.08:25:18.85#ibcon#about to write, iclass 28, count 0 2006.218.08:25:18.85#ibcon#wrote, iclass 28, count 0 2006.218.08:25:18.85#ibcon#about to read 3, iclass 28, count 0 2006.218.08:25:18.89#ibcon#read 3, iclass 28, count 0 2006.218.08:25:18.89#ibcon#about to read 4, iclass 28, count 0 2006.218.08:25:18.90#ibcon#read 4, iclass 28, count 0 2006.218.08:25:18.90#ibcon#about to read 5, iclass 28, count 0 2006.218.08:25:18.90#ibcon#read 5, iclass 28, count 0 2006.218.08:25:18.90#ibcon#about to read 6, iclass 28, count 0 2006.218.08:25:18.90#ibcon#read 6, iclass 28, count 0 2006.218.08:25:18.90#ibcon#end of sib2, iclass 28, count 0 2006.218.08:25:18.90#ibcon#*after write, iclass 28, count 0 2006.218.08:25:18.90#ibcon#*before return 0, iclass 28, count 0 2006.218.08:25:18.90#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.218.08:25:18.90#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.218.08:25:18.90#ibcon#about to clear, iclass 28 cls_cnt 0 2006.218.08:25:18.90#ibcon#cleared, iclass 28 cls_cnt 0 2006.218.08:25:18.90$vc4f8/va=4,4 2006.218.08:25:18.90#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.218.08:25:18.90#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.218.08:25:18.90#ibcon#ireg 11 cls_cnt 2 2006.218.08:25:18.90#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.218.08:25:18.95#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.218.08:25:18.95#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.218.08:25:18.95#ibcon#enter wrdev, iclass 30, count 2 2006.218.08:25:18.95#ibcon#first serial, iclass 30, count 2 2006.218.08:25:18.95#ibcon#enter sib2, iclass 30, count 2 2006.218.08:25:18.95#ibcon#flushed, iclass 30, count 2 2006.218.08:25:18.95#ibcon#about to write, iclass 30, count 2 2006.218.08:25:18.95#ibcon#wrote, iclass 30, count 2 2006.218.08:25:18.95#ibcon#about to read 3, iclass 30, count 2 2006.218.08:25:18.96#ibcon#read 3, iclass 30, count 2 2006.218.08:25:18.96#ibcon#about to read 4, iclass 30, count 2 2006.218.08:25:18.96#ibcon#read 4, iclass 30, count 2 2006.218.08:25:18.97#ibcon#about to read 5, iclass 30, count 2 2006.218.08:25:18.97#ibcon#read 5, iclass 30, count 2 2006.218.08:25:18.97#ibcon#about to read 6, iclass 30, count 2 2006.218.08:25:18.97#ibcon#read 6, iclass 30, count 2 2006.218.08:25:18.97#ibcon#end of sib2, iclass 30, count 2 2006.218.08:25:18.97#ibcon#*mode == 0, iclass 30, count 2 2006.218.08:25:18.97#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.218.08:25:18.97#ibcon#[25=AT04-04\r\n] 2006.218.08:25:18.97#ibcon#*before write, iclass 30, count 2 2006.218.08:25:18.97#ibcon#enter sib2, iclass 30, count 2 2006.218.08:25:18.97#ibcon#flushed, iclass 30, count 2 2006.218.08:25:18.97#ibcon#about to write, iclass 30, count 2 2006.218.08:25:18.97#ibcon#wrote, iclass 30, count 2 2006.218.08:25:18.97#ibcon#about to read 3, iclass 30, count 2 2006.218.08:25:18.99#ibcon#read 3, iclass 30, count 2 2006.218.08:25:18.99#ibcon#about to read 4, iclass 30, count 2 2006.218.08:25:19.00#ibcon#read 4, iclass 30, count 2 2006.218.08:25:19.00#ibcon#about to read 5, iclass 30, count 2 2006.218.08:25:19.00#ibcon#read 5, iclass 30, count 2 2006.218.08:25:19.00#ibcon#about to read 6, iclass 30, count 2 2006.218.08:25:19.00#ibcon#read 6, iclass 30, count 2 2006.218.08:25:19.00#ibcon#end of sib2, iclass 30, count 2 2006.218.08:25:19.00#ibcon#*after write, iclass 30, count 2 2006.218.08:25:19.00#ibcon#*before return 0, iclass 30, count 2 2006.218.08:25:19.00#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.218.08:25:19.00#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.218.08:25:19.00#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.218.08:25:19.00#ibcon#ireg 7 cls_cnt 0 2006.218.08:25:19.00#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.218.08:25:19.11#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.218.08:25:19.11#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.218.08:25:19.11#ibcon#enter wrdev, iclass 30, count 0 2006.218.08:25:19.11#ibcon#first serial, iclass 30, count 0 2006.218.08:25:19.11#ibcon#enter sib2, iclass 30, count 0 2006.218.08:25:19.12#ibcon#flushed, iclass 30, count 0 2006.218.08:25:19.12#ibcon#about to write, iclass 30, count 0 2006.218.08:25:19.12#ibcon#wrote, iclass 30, count 0 2006.218.08:25:19.12#ibcon#about to read 3, iclass 30, count 0 2006.218.08:25:19.13#ibcon#read 3, iclass 30, count 0 2006.218.08:25:19.13#ibcon#about to read 4, iclass 30, count 0 2006.218.08:25:19.13#ibcon#read 4, iclass 30, count 0 2006.218.08:25:19.13#ibcon#about to read 5, iclass 30, count 0 2006.218.08:25:19.14#ibcon#read 5, iclass 30, count 0 2006.218.08:25:19.14#ibcon#about to read 6, iclass 30, count 0 2006.218.08:25:19.14#ibcon#read 6, iclass 30, count 0 2006.218.08:25:19.14#ibcon#end of sib2, iclass 30, count 0 2006.218.08:25:19.14#ibcon#*mode == 0, iclass 30, count 0 2006.218.08:25:19.14#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.218.08:25:19.14#ibcon#[25=USB\r\n] 2006.218.08:25:19.14#ibcon#*before write, iclass 30, count 0 2006.218.08:25:19.14#ibcon#enter sib2, iclass 30, count 0 2006.218.08:25:19.14#ibcon#flushed, iclass 30, count 0 2006.218.08:25:19.14#ibcon#about to write, iclass 30, count 0 2006.218.08:25:19.14#ibcon#wrote, iclass 30, count 0 2006.218.08:25:19.14#ibcon#about to read 3, iclass 30, count 0 2006.218.08:25:19.16#ibcon#read 3, iclass 30, count 0 2006.218.08:25:19.16#ibcon#about to read 4, iclass 30, count 0 2006.218.08:25:19.16#ibcon#read 4, iclass 30, count 0 2006.218.08:25:19.16#ibcon#about to read 5, iclass 30, count 0 2006.218.08:25:19.17#ibcon#read 5, iclass 30, count 0 2006.218.08:25:19.17#ibcon#about to read 6, iclass 30, count 0 2006.218.08:25:19.17#ibcon#read 6, iclass 30, count 0 2006.218.08:25:19.17#ibcon#end of sib2, iclass 30, count 0 2006.218.08:25:19.17#ibcon#*after write, iclass 30, count 0 2006.218.08:25:19.17#ibcon#*before return 0, iclass 30, count 0 2006.218.08:25:19.17#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.218.08:25:19.17#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.218.08:25:19.17#ibcon#about to clear, iclass 30 cls_cnt 0 2006.218.08:25:19.17#ibcon#cleared, iclass 30 cls_cnt 0 2006.218.08:25:19.17$vc4f8/valo=5,652.99 2006.218.08:25:19.17#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.218.08:25:19.17#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.218.08:25:19.17#ibcon#ireg 17 cls_cnt 0 2006.218.08:25:19.17#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.218.08:25:19.17#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.218.08:25:19.17#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.218.08:25:19.17#ibcon#enter wrdev, iclass 32, count 0 2006.218.08:25:19.17#ibcon#first serial, iclass 32, count 0 2006.218.08:25:19.17#ibcon#enter sib2, iclass 32, count 0 2006.218.08:25:19.17#ibcon#flushed, iclass 32, count 0 2006.218.08:25:19.17#ibcon#about to write, iclass 32, count 0 2006.218.08:25:19.17#ibcon#wrote, iclass 32, count 0 2006.218.08:25:19.17#ibcon#about to read 3, iclass 32, count 0 2006.218.08:25:19.18#ibcon#read 3, iclass 32, count 0 2006.218.08:25:19.18#ibcon#about to read 4, iclass 32, count 0 2006.218.08:25:19.18#ibcon#read 4, iclass 32, count 0 2006.218.08:25:19.18#ibcon#about to read 5, iclass 32, count 0 2006.218.08:25:19.19#ibcon#read 5, iclass 32, count 0 2006.218.08:25:19.19#ibcon#about to read 6, iclass 32, count 0 2006.218.08:25:19.19#ibcon#read 6, iclass 32, count 0 2006.218.08:25:19.19#ibcon#end of sib2, iclass 32, count 0 2006.218.08:25:19.19#ibcon#*mode == 0, iclass 32, count 0 2006.218.08:25:19.19#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.218.08:25:19.19#ibcon#[26=FRQ=05,652.99\r\n] 2006.218.08:25:19.19#ibcon#*before write, iclass 32, count 0 2006.218.08:25:19.19#ibcon#enter sib2, iclass 32, count 0 2006.218.08:25:19.19#ibcon#flushed, iclass 32, count 0 2006.218.08:25:19.19#ibcon#about to write, iclass 32, count 0 2006.218.08:25:19.19#ibcon#wrote, iclass 32, count 0 2006.218.08:25:19.19#ibcon#about to read 3, iclass 32, count 0 2006.218.08:25:19.22#ibcon#read 3, iclass 32, count 0 2006.218.08:25:19.22#ibcon#about to read 4, iclass 32, count 0 2006.218.08:25:19.22#ibcon#read 4, iclass 32, count 0 2006.218.08:25:19.22#ibcon#about to read 5, iclass 32, count 0 2006.218.08:25:19.23#ibcon#read 5, iclass 32, count 0 2006.218.08:25:19.23#ibcon#about to read 6, iclass 32, count 0 2006.218.08:25:19.23#ibcon#read 6, iclass 32, count 0 2006.218.08:25:19.23#ibcon#end of sib2, iclass 32, count 0 2006.218.08:25:19.23#ibcon#*after write, iclass 32, count 0 2006.218.08:25:19.23#ibcon#*before return 0, iclass 32, count 0 2006.218.08:25:19.23#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.218.08:25:19.23#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.218.08:25:19.23#ibcon#about to clear, iclass 32 cls_cnt 0 2006.218.08:25:19.23#ibcon#cleared, iclass 32 cls_cnt 0 2006.218.08:25:19.23$vc4f8/va=5,7 2006.218.08:25:19.23#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.218.08:25:19.23#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.218.08:25:19.23#ibcon#ireg 11 cls_cnt 2 2006.218.08:25:19.23#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.218.08:25:19.28#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.218.08:25:19.28#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.218.08:25:19.28#ibcon#enter wrdev, iclass 34, count 2 2006.218.08:25:19.28#ibcon#first serial, iclass 34, count 2 2006.218.08:25:19.28#ibcon#enter sib2, iclass 34, count 2 2006.218.08:25:19.29#ibcon#flushed, iclass 34, count 2 2006.218.08:25:19.29#ibcon#about to write, iclass 34, count 2 2006.218.08:25:19.29#ibcon#wrote, iclass 34, count 2 2006.218.08:25:19.29#ibcon#about to read 3, iclass 34, count 2 2006.218.08:25:19.30#ibcon#read 3, iclass 34, count 2 2006.218.08:25:19.30#ibcon#about to read 4, iclass 34, count 2 2006.218.08:25:19.30#ibcon#read 4, iclass 34, count 2 2006.218.08:25:19.30#ibcon#about to read 5, iclass 34, count 2 2006.218.08:25:19.31#ibcon#read 5, iclass 34, count 2 2006.218.08:25:19.31#ibcon#about to read 6, iclass 34, count 2 2006.218.08:25:19.31#ibcon#read 6, iclass 34, count 2 2006.218.08:25:19.31#ibcon#end of sib2, iclass 34, count 2 2006.218.08:25:19.31#ibcon#*mode == 0, iclass 34, count 2 2006.218.08:25:19.31#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.218.08:25:19.31#ibcon#[25=AT05-07\r\n] 2006.218.08:25:19.31#ibcon#*before write, iclass 34, count 2 2006.218.08:25:19.31#ibcon#enter sib2, iclass 34, count 2 2006.218.08:25:19.31#ibcon#flushed, iclass 34, count 2 2006.218.08:25:19.31#ibcon#about to write, iclass 34, count 2 2006.218.08:25:19.31#ibcon#wrote, iclass 34, count 2 2006.218.08:25:19.31#ibcon#about to read 3, iclass 34, count 2 2006.218.08:25:19.33#ibcon#read 3, iclass 34, count 2 2006.218.08:25:19.33#ibcon#about to read 4, iclass 34, count 2 2006.218.08:25:19.34#ibcon#read 4, iclass 34, count 2 2006.218.08:25:19.34#ibcon#about to read 5, iclass 34, count 2 2006.218.08:25:19.34#ibcon#read 5, iclass 34, count 2 2006.218.08:25:19.34#ibcon#about to read 6, iclass 34, count 2 2006.218.08:25:19.34#ibcon#read 6, iclass 34, count 2 2006.218.08:25:19.34#ibcon#end of sib2, iclass 34, count 2 2006.218.08:25:19.34#ibcon#*after write, iclass 34, count 2 2006.218.08:25:19.34#ibcon#*before return 0, iclass 34, count 2 2006.218.08:25:19.34#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.218.08:25:19.34#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.218.08:25:19.34#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.218.08:25:19.34#ibcon#ireg 7 cls_cnt 0 2006.218.08:25:19.34#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.218.08:25:19.45#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.218.08:25:19.45#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.218.08:25:19.45#ibcon#enter wrdev, iclass 34, count 0 2006.218.08:25:19.45#ibcon#first serial, iclass 34, count 0 2006.218.08:25:19.45#ibcon#enter sib2, iclass 34, count 0 2006.218.08:25:19.45#ibcon#flushed, iclass 34, count 0 2006.218.08:25:19.46#ibcon#about to write, iclass 34, count 0 2006.218.08:25:19.46#ibcon#wrote, iclass 34, count 0 2006.218.08:25:19.46#ibcon#about to read 3, iclass 34, count 0 2006.218.08:25:19.47#ibcon#read 3, iclass 34, count 0 2006.218.08:25:19.47#ibcon#about to read 4, iclass 34, count 0 2006.218.08:25:19.47#ibcon#read 4, iclass 34, count 0 2006.218.08:25:19.47#ibcon#about to read 5, iclass 34, count 0 2006.218.08:25:19.48#ibcon#read 5, iclass 34, count 0 2006.218.08:25:19.48#ibcon#about to read 6, iclass 34, count 0 2006.218.08:25:19.48#ibcon#read 6, iclass 34, count 0 2006.218.08:25:19.48#ibcon#end of sib2, iclass 34, count 0 2006.218.08:25:19.48#ibcon#*mode == 0, iclass 34, count 0 2006.218.08:25:19.48#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.218.08:25:19.48#ibcon#[25=USB\r\n] 2006.218.08:25:19.48#ibcon#*before write, iclass 34, count 0 2006.218.08:25:19.48#ibcon#enter sib2, iclass 34, count 0 2006.218.08:25:19.48#ibcon#flushed, iclass 34, count 0 2006.218.08:25:19.48#ibcon#about to write, iclass 34, count 0 2006.218.08:25:19.48#ibcon#wrote, iclass 34, count 0 2006.218.08:25:19.48#ibcon#about to read 3, iclass 34, count 0 2006.218.08:25:19.50#ibcon#read 3, iclass 34, count 0 2006.218.08:25:19.50#ibcon#about to read 4, iclass 34, count 0 2006.218.08:25:19.50#ibcon#read 4, iclass 34, count 0 2006.218.08:25:19.50#ibcon#about to read 5, iclass 34, count 0 2006.218.08:25:19.51#ibcon#read 5, iclass 34, count 0 2006.218.08:25:19.51#ibcon#about to read 6, iclass 34, count 0 2006.218.08:25:19.51#ibcon#read 6, iclass 34, count 0 2006.218.08:25:19.51#ibcon#end of sib2, iclass 34, count 0 2006.218.08:25:19.51#ibcon#*after write, iclass 34, count 0 2006.218.08:25:19.51#ibcon#*before return 0, iclass 34, count 0 2006.218.08:25:19.51#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.218.08:25:19.51#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.218.08:25:19.51#ibcon#about to clear, iclass 34 cls_cnt 0 2006.218.08:25:19.51#ibcon#cleared, iclass 34 cls_cnt 0 2006.218.08:25:19.51$vc4f8/valo=6,772.99 2006.218.08:25:19.51#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.218.08:25:19.51#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.218.08:25:19.51#ibcon#ireg 17 cls_cnt 0 2006.218.08:25:19.51#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.218.08:25:19.51#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.218.08:25:19.51#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.218.08:25:19.51#ibcon#enter wrdev, iclass 36, count 0 2006.218.08:25:19.51#ibcon#first serial, iclass 36, count 0 2006.218.08:25:19.51#ibcon#enter sib2, iclass 36, count 0 2006.218.08:25:19.51#ibcon#flushed, iclass 36, count 0 2006.218.08:25:19.51#ibcon#about to write, iclass 36, count 0 2006.218.08:25:19.51#ibcon#wrote, iclass 36, count 0 2006.218.08:25:19.51#ibcon#about to read 3, iclass 36, count 0 2006.218.08:25:19.53#ibcon#read 3, iclass 36, count 0 2006.218.08:25:19.53#ibcon#about to read 4, iclass 36, count 0 2006.218.08:25:19.53#ibcon#read 4, iclass 36, count 0 2006.218.08:25:19.53#ibcon#about to read 5, iclass 36, count 0 2006.218.08:25:19.53#ibcon#read 5, iclass 36, count 0 2006.218.08:25:19.53#ibcon#about to read 6, iclass 36, count 0 2006.218.08:25:19.53#ibcon#read 6, iclass 36, count 0 2006.218.08:25:19.53#ibcon#end of sib2, iclass 36, count 0 2006.218.08:25:19.53#ibcon#*mode == 0, iclass 36, count 0 2006.218.08:25:19.53#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.218.08:25:19.53#ibcon#[26=FRQ=06,772.99\r\n] 2006.218.08:25:19.53#ibcon#*before write, iclass 36, count 0 2006.218.08:25:19.53#ibcon#enter sib2, iclass 36, count 0 2006.218.08:25:19.53#ibcon#flushed, iclass 36, count 0 2006.218.08:25:19.53#ibcon#about to write, iclass 36, count 0 2006.218.08:25:19.53#ibcon#wrote, iclass 36, count 0 2006.218.08:25:19.53#ibcon#about to read 3, iclass 36, count 0 2006.218.08:25:19.57#ibcon#read 3, iclass 36, count 0 2006.218.08:25:19.57#ibcon#about to read 4, iclass 36, count 0 2006.218.08:25:19.58#ibcon#read 4, iclass 36, count 0 2006.218.08:25:19.58#ibcon#about to read 5, iclass 36, count 0 2006.218.08:25:19.58#ibcon#read 5, iclass 36, count 0 2006.218.08:25:19.58#ibcon#about to read 6, iclass 36, count 0 2006.218.08:25:19.58#ibcon#read 6, iclass 36, count 0 2006.218.08:25:19.58#ibcon#end of sib2, iclass 36, count 0 2006.218.08:25:19.58#ibcon#*after write, iclass 36, count 0 2006.218.08:25:19.58#ibcon#*before return 0, iclass 36, count 0 2006.218.08:25:19.58#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.218.08:25:19.58#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.218.08:25:19.58#ibcon#about to clear, iclass 36 cls_cnt 0 2006.218.08:25:19.58#ibcon#cleared, iclass 36 cls_cnt 0 2006.218.08:25:19.58$vc4f8/va=6,6 2006.218.08:25:19.58#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.218.08:25:19.58#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.218.08:25:19.58#ibcon#ireg 11 cls_cnt 2 2006.218.08:25:19.58#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.218.08:25:19.63#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.218.08:25:19.63#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.218.08:25:19.63#ibcon#enter wrdev, iclass 38, count 2 2006.218.08:25:19.63#ibcon#first serial, iclass 38, count 2 2006.218.08:25:19.63#ibcon#enter sib2, iclass 38, count 2 2006.218.08:25:19.63#ibcon#flushed, iclass 38, count 2 2006.218.08:25:19.63#ibcon#about to write, iclass 38, count 2 2006.218.08:25:19.63#ibcon#wrote, iclass 38, count 2 2006.218.08:25:19.63#ibcon#about to read 3, iclass 38, count 2 2006.218.08:25:19.64#ibcon#read 3, iclass 38, count 2 2006.218.08:25:19.65#ibcon#about to read 4, iclass 38, count 2 2006.218.08:25:19.65#ibcon#read 4, iclass 38, count 2 2006.218.08:25:19.65#ibcon#about to read 5, iclass 38, count 2 2006.218.08:25:19.65#ibcon#read 5, iclass 38, count 2 2006.218.08:25:19.65#ibcon#about to read 6, iclass 38, count 2 2006.218.08:25:19.65#ibcon#read 6, iclass 38, count 2 2006.218.08:25:19.65#ibcon#end of sib2, iclass 38, count 2 2006.218.08:25:19.65#ibcon#*mode == 0, iclass 38, count 2 2006.218.08:25:19.65#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.218.08:25:19.65#ibcon#[25=AT06-06\r\n] 2006.218.08:25:19.65#ibcon#*before write, iclass 38, count 2 2006.218.08:25:19.65#ibcon#enter sib2, iclass 38, count 2 2006.218.08:25:19.65#ibcon#flushed, iclass 38, count 2 2006.218.08:25:19.65#ibcon#about to write, iclass 38, count 2 2006.218.08:25:19.65#ibcon#wrote, iclass 38, count 2 2006.218.08:25:19.65#ibcon#about to read 3, iclass 38, count 2 2006.218.08:25:19.67#ibcon#read 3, iclass 38, count 2 2006.218.08:25:19.67#ibcon#about to read 4, iclass 38, count 2 2006.218.08:25:19.68#ibcon#read 4, iclass 38, count 2 2006.218.08:25:19.68#ibcon#about to read 5, iclass 38, count 2 2006.218.08:25:19.68#ibcon#read 5, iclass 38, count 2 2006.218.08:25:19.68#ibcon#about to read 6, iclass 38, count 2 2006.218.08:25:19.68#ibcon#read 6, iclass 38, count 2 2006.218.08:25:19.68#ibcon#end of sib2, iclass 38, count 2 2006.218.08:25:19.68#ibcon#*after write, iclass 38, count 2 2006.218.08:25:19.68#ibcon#*before return 0, iclass 38, count 2 2006.218.08:25:19.68#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.218.08:25:19.68#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.218.08:25:19.68#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.218.08:25:19.68#ibcon#ireg 7 cls_cnt 0 2006.218.08:25:19.68#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.218.08:25:19.79#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.218.08:25:19.79#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.218.08:25:19.79#ibcon#enter wrdev, iclass 38, count 0 2006.218.08:25:19.79#ibcon#first serial, iclass 38, count 0 2006.218.08:25:19.79#ibcon#enter sib2, iclass 38, count 0 2006.218.08:25:19.79#ibcon#flushed, iclass 38, count 0 2006.218.08:25:19.80#ibcon#about to write, iclass 38, count 0 2006.218.08:25:19.80#ibcon#wrote, iclass 38, count 0 2006.218.08:25:19.80#ibcon#about to read 3, iclass 38, count 0 2006.218.08:25:19.81#ibcon#read 3, iclass 38, count 0 2006.218.08:25:19.81#ibcon#about to read 4, iclass 38, count 0 2006.218.08:25:19.81#ibcon#read 4, iclass 38, count 0 2006.218.08:25:19.81#ibcon#about to read 5, iclass 38, count 0 2006.218.08:25:19.82#ibcon#read 5, iclass 38, count 0 2006.218.08:25:19.82#ibcon#about to read 6, iclass 38, count 0 2006.218.08:25:19.82#ibcon#read 6, iclass 38, count 0 2006.218.08:25:19.82#ibcon#end of sib2, iclass 38, count 0 2006.218.08:25:19.82#ibcon#*mode == 0, iclass 38, count 0 2006.218.08:25:19.82#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.218.08:25:19.82#ibcon#[25=USB\r\n] 2006.218.08:25:19.82#ibcon#*before write, iclass 38, count 0 2006.218.08:25:19.82#ibcon#enter sib2, iclass 38, count 0 2006.218.08:25:19.82#ibcon#flushed, iclass 38, count 0 2006.218.08:25:19.82#ibcon#about to write, iclass 38, count 0 2006.218.08:25:19.82#ibcon#wrote, iclass 38, count 0 2006.218.08:25:19.82#ibcon#about to read 3, iclass 38, count 0 2006.218.08:25:19.84#ibcon#read 3, iclass 38, count 0 2006.218.08:25:19.84#ibcon#about to read 4, iclass 38, count 0 2006.218.08:25:19.84#ibcon#read 4, iclass 38, count 0 2006.218.08:25:19.84#ibcon#about to read 5, iclass 38, count 0 2006.218.08:25:19.85#ibcon#read 5, iclass 38, count 0 2006.218.08:25:19.85#ibcon#about to read 6, iclass 38, count 0 2006.218.08:25:19.85#ibcon#read 6, iclass 38, count 0 2006.218.08:25:19.85#ibcon#end of sib2, iclass 38, count 0 2006.218.08:25:19.85#ibcon#*after write, iclass 38, count 0 2006.218.08:25:19.85#ibcon#*before return 0, iclass 38, count 0 2006.218.08:25:19.85#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.218.08:25:19.85#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.218.08:25:19.85#ibcon#about to clear, iclass 38 cls_cnt 0 2006.218.08:25:19.85#ibcon#cleared, iclass 38 cls_cnt 0 2006.218.08:25:19.85$vc4f8/valo=7,832.99 2006.218.08:25:19.85#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.218.08:25:19.85#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.218.08:25:19.85#ibcon#ireg 17 cls_cnt 0 2006.218.08:25:19.85#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.218.08:25:19.85#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.218.08:25:19.85#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.218.08:25:19.85#ibcon#enter wrdev, iclass 40, count 0 2006.218.08:25:19.85#ibcon#first serial, iclass 40, count 0 2006.218.08:25:19.85#ibcon#enter sib2, iclass 40, count 0 2006.218.08:25:19.85#ibcon#flushed, iclass 40, count 0 2006.218.08:25:19.85#ibcon#about to write, iclass 40, count 0 2006.218.08:25:19.85#ibcon#wrote, iclass 40, count 0 2006.218.08:25:19.85#ibcon#about to read 3, iclass 40, count 0 2006.218.08:25:19.86#ibcon#read 3, iclass 40, count 0 2006.218.08:25:19.86#ibcon#about to read 4, iclass 40, count 0 2006.218.08:25:19.86#ibcon#read 4, iclass 40, count 0 2006.218.08:25:19.86#ibcon#about to read 5, iclass 40, count 0 2006.218.08:25:19.87#ibcon#read 5, iclass 40, count 0 2006.218.08:25:19.87#ibcon#about to read 6, iclass 40, count 0 2006.218.08:25:19.87#ibcon#read 6, iclass 40, count 0 2006.218.08:25:19.87#ibcon#end of sib2, iclass 40, count 0 2006.218.08:25:19.87#ibcon#*mode == 0, iclass 40, count 0 2006.218.08:25:19.87#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.218.08:25:19.87#ibcon#[26=FRQ=07,832.99\r\n] 2006.218.08:25:19.87#ibcon#*before write, iclass 40, count 0 2006.218.08:25:19.87#ibcon#enter sib2, iclass 40, count 0 2006.218.08:25:19.87#ibcon#flushed, iclass 40, count 0 2006.218.08:25:19.87#ibcon#about to write, iclass 40, count 0 2006.218.08:25:19.87#ibcon#wrote, iclass 40, count 0 2006.218.08:25:19.87#ibcon#about to read 3, iclass 40, count 0 2006.218.08:25:19.90#ibcon#read 3, iclass 40, count 0 2006.218.08:25:19.90#ibcon#about to read 4, iclass 40, count 0 2006.218.08:25:19.90#ibcon#read 4, iclass 40, count 0 2006.218.08:25:19.90#ibcon#about to read 5, iclass 40, count 0 2006.218.08:25:19.91#ibcon#read 5, iclass 40, count 0 2006.218.08:25:19.91#ibcon#about to read 6, iclass 40, count 0 2006.218.08:25:19.91#ibcon#read 6, iclass 40, count 0 2006.218.08:25:19.91#ibcon#end of sib2, iclass 40, count 0 2006.218.08:25:19.91#ibcon#*after write, iclass 40, count 0 2006.218.08:25:19.91#ibcon#*before return 0, iclass 40, count 0 2006.218.08:25:19.91#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.218.08:25:19.91#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.218.08:25:19.91#ibcon#about to clear, iclass 40 cls_cnt 0 2006.218.08:25:19.91#ibcon#cleared, iclass 40 cls_cnt 0 2006.218.08:25:19.91$vc4f8/va=7,6 2006.218.08:25:19.91#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.218.08:25:19.91#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.218.08:25:19.91#ibcon#ireg 11 cls_cnt 2 2006.218.08:25:19.91#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.218.08:25:19.96#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.218.08:25:19.96#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.218.08:25:19.96#ibcon#enter wrdev, iclass 4, count 2 2006.218.08:25:19.96#ibcon#first serial, iclass 4, count 2 2006.218.08:25:19.96#ibcon#enter sib2, iclass 4, count 2 2006.218.08:25:19.97#ibcon#flushed, iclass 4, count 2 2006.218.08:25:19.97#ibcon#about to write, iclass 4, count 2 2006.218.08:25:19.97#ibcon#wrote, iclass 4, count 2 2006.218.08:25:19.97#ibcon#about to read 3, iclass 4, count 2 2006.218.08:25:19.98#ibcon#read 3, iclass 4, count 2 2006.218.08:25:19.98#ibcon#about to read 4, iclass 4, count 2 2006.218.08:25:19.98#ibcon#read 4, iclass 4, count 2 2006.218.08:25:19.98#ibcon#about to read 5, iclass 4, count 2 2006.218.08:25:19.99#ibcon#read 5, iclass 4, count 2 2006.218.08:25:19.99#ibcon#about to read 6, iclass 4, count 2 2006.218.08:25:19.99#ibcon#read 6, iclass 4, count 2 2006.218.08:25:19.99#ibcon#end of sib2, iclass 4, count 2 2006.218.08:25:19.99#ibcon#*mode == 0, iclass 4, count 2 2006.218.08:25:19.99#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.218.08:25:19.99#ibcon#[25=AT07-06\r\n] 2006.218.08:25:19.99#ibcon#*before write, iclass 4, count 2 2006.218.08:25:19.99#ibcon#enter sib2, iclass 4, count 2 2006.218.08:25:19.99#ibcon#flushed, iclass 4, count 2 2006.218.08:25:19.99#ibcon#about to write, iclass 4, count 2 2006.218.08:25:19.99#ibcon#wrote, iclass 4, count 2 2006.218.08:25:19.99#ibcon#about to read 3, iclass 4, count 2 2006.218.08:25:20.02#ibcon#read 3, iclass 4, count 2 2006.218.08:25:20.02#ibcon#about to read 4, iclass 4, count 2 2006.218.08:25:20.02#ibcon#read 4, iclass 4, count 2 2006.218.08:25:20.02#ibcon#about to read 5, iclass 4, count 2 2006.218.08:25:20.02#ibcon#read 5, iclass 4, count 2 2006.218.08:25:20.02#ibcon#about to read 6, iclass 4, count 2 2006.218.08:25:20.02#ibcon#read 6, iclass 4, count 2 2006.218.08:25:20.02#ibcon#end of sib2, iclass 4, count 2 2006.218.08:25:20.02#ibcon#*after write, iclass 4, count 2 2006.218.08:25:20.02#ibcon#*before return 0, iclass 4, count 2 2006.218.08:25:20.02#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.218.08:25:20.02#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.218.08:25:20.02#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.218.08:25:20.02#ibcon#ireg 7 cls_cnt 0 2006.218.08:25:20.02#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.218.08:25:20.04#abcon#<5=/06 4.3 7.5 30.54 761007.6\r\n> 2006.218.08:25:20.06#abcon#{5=INTERFACE CLEAR} 2006.218.08:25:20.12#abcon#[5=S1D000X0/0*\r\n] 2006.218.08:25:20.14#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.218.08:25:20.14#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.218.08:25:20.14#ibcon#enter wrdev, iclass 4, count 0 2006.218.08:25:20.14#ibcon#first serial, iclass 4, count 0 2006.218.08:25:20.14#ibcon#enter sib2, iclass 4, count 0 2006.218.08:25:20.14#ibcon#flushed, iclass 4, count 0 2006.218.08:25:20.14#ibcon#about to write, iclass 4, count 0 2006.218.08:25:20.14#ibcon#wrote, iclass 4, count 0 2006.218.08:25:20.14#ibcon#about to read 3, iclass 4, count 0 2006.218.08:25:20.15#ibcon#read 3, iclass 4, count 0 2006.218.08:25:20.15#ibcon#about to read 4, iclass 4, count 0 2006.218.08:25:20.15#ibcon#read 4, iclass 4, count 0 2006.218.08:25:20.15#ibcon#about to read 5, iclass 4, count 0 2006.218.08:25:20.15#ibcon#read 5, iclass 4, count 0 2006.218.08:25:20.15#ibcon#about to read 6, iclass 4, count 0 2006.218.08:25:20.16#ibcon#read 6, iclass 4, count 0 2006.218.08:25:20.16#ibcon#end of sib2, iclass 4, count 0 2006.218.08:25:20.16#ibcon#*mode == 0, iclass 4, count 0 2006.218.08:25:20.16#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.218.08:25:20.16#ibcon#[25=USB\r\n] 2006.218.08:25:20.16#ibcon#*before write, iclass 4, count 0 2006.218.08:25:20.16#ibcon#enter sib2, iclass 4, count 0 2006.218.08:25:20.16#ibcon#flushed, iclass 4, count 0 2006.218.08:25:20.16#ibcon#about to write, iclass 4, count 0 2006.218.08:25:20.16#ibcon#wrote, iclass 4, count 0 2006.218.08:25:20.16#ibcon#about to read 3, iclass 4, count 0 2006.218.08:25:20.18#ibcon#read 3, iclass 4, count 0 2006.218.08:25:20.18#ibcon#about to read 4, iclass 4, count 0 2006.218.08:25:20.19#ibcon#read 4, iclass 4, count 0 2006.218.08:25:20.19#ibcon#about to read 5, iclass 4, count 0 2006.218.08:25:20.19#ibcon#read 5, iclass 4, count 0 2006.218.08:25:20.19#ibcon#about to read 6, iclass 4, count 0 2006.218.08:25:20.19#ibcon#read 6, iclass 4, count 0 2006.218.08:25:20.19#ibcon#end of sib2, iclass 4, count 0 2006.218.08:25:20.19#ibcon#*after write, iclass 4, count 0 2006.218.08:25:20.19#ibcon#*before return 0, iclass 4, count 0 2006.218.08:25:20.19#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.218.08:25:20.19#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.218.08:25:20.19#ibcon#about to clear, iclass 4 cls_cnt 0 2006.218.08:25:20.19#ibcon#cleared, iclass 4 cls_cnt 0 2006.218.08:25:20.19$vc4f8/valo=8,852.99 2006.218.08:25:20.19#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.218.08:25:20.19#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.218.08:25:20.19#ibcon#ireg 17 cls_cnt 0 2006.218.08:25:20.19#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.218.08:25:20.19#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.218.08:25:20.19#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.218.08:25:20.19#ibcon#enter wrdev, iclass 12, count 0 2006.218.08:25:20.19#ibcon#first serial, iclass 12, count 0 2006.218.08:25:20.19#ibcon#enter sib2, iclass 12, count 0 2006.218.08:25:20.19#ibcon#flushed, iclass 12, count 0 2006.218.08:25:20.19#ibcon#about to write, iclass 12, count 0 2006.218.08:25:20.19#ibcon#wrote, iclass 12, count 0 2006.218.08:25:20.19#ibcon#about to read 3, iclass 12, count 0 2006.218.08:25:20.20#ibcon#read 3, iclass 12, count 0 2006.218.08:25:20.20#ibcon#about to read 4, iclass 12, count 0 2006.218.08:25:20.20#ibcon#read 4, iclass 12, count 0 2006.218.08:25:20.20#ibcon#about to read 5, iclass 12, count 0 2006.218.08:25:20.21#ibcon#read 5, iclass 12, count 0 2006.218.08:25:20.21#ibcon#about to read 6, iclass 12, count 0 2006.218.08:25:20.21#ibcon#read 6, iclass 12, count 0 2006.218.08:25:20.21#ibcon#end of sib2, iclass 12, count 0 2006.218.08:25:20.21#ibcon#*mode == 0, iclass 12, count 0 2006.218.08:25:20.21#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.218.08:25:20.21#ibcon#[26=FRQ=08,852.99\r\n] 2006.218.08:25:20.21#ibcon#*before write, iclass 12, count 0 2006.218.08:25:20.21#ibcon#enter sib2, iclass 12, count 0 2006.218.08:25:20.21#ibcon#flushed, iclass 12, count 0 2006.218.08:25:20.21#ibcon#about to write, iclass 12, count 0 2006.218.08:25:20.21#ibcon#wrote, iclass 12, count 0 2006.218.08:25:20.21#ibcon#about to read 3, iclass 12, count 0 2006.218.08:25:20.24#ibcon#read 3, iclass 12, count 0 2006.218.08:25:20.24#ibcon#about to read 4, iclass 12, count 0 2006.218.08:25:20.24#ibcon#read 4, iclass 12, count 0 2006.218.08:25:20.25#ibcon#about to read 5, iclass 12, count 0 2006.218.08:25:20.25#ibcon#read 5, iclass 12, count 0 2006.218.08:25:20.25#ibcon#about to read 6, iclass 12, count 0 2006.218.08:25:20.25#ibcon#read 6, iclass 12, count 0 2006.218.08:25:20.25#ibcon#end of sib2, iclass 12, count 0 2006.218.08:25:20.25#ibcon#*after write, iclass 12, count 0 2006.218.08:25:20.25#ibcon#*before return 0, iclass 12, count 0 2006.218.08:25:20.25#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.218.08:25:20.25#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.218.08:25:20.25#ibcon#about to clear, iclass 12 cls_cnt 0 2006.218.08:25:20.25#ibcon#cleared, iclass 12 cls_cnt 0 2006.218.08:25:20.25$vc4f8/va=8,7 2006.218.08:25:20.25#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.218.08:25:20.25#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.218.08:25:20.25#ibcon#ireg 11 cls_cnt 2 2006.218.08:25:20.25#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.218.08:25:20.30#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.218.08:25:20.30#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.218.08:25:20.30#ibcon#enter wrdev, iclass 14, count 2 2006.218.08:25:20.30#ibcon#first serial, iclass 14, count 2 2006.218.08:25:20.30#ibcon#enter sib2, iclass 14, count 2 2006.218.08:25:20.31#ibcon#flushed, iclass 14, count 2 2006.218.08:25:20.31#ibcon#about to write, iclass 14, count 2 2006.218.08:25:20.31#ibcon#wrote, iclass 14, count 2 2006.218.08:25:20.31#ibcon#about to read 3, iclass 14, count 2 2006.218.08:25:20.32#ibcon#read 3, iclass 14, count 2 2006.218.08:25:20.32#ibcon#about to read 4, iclass 14, count 2 2006.218.08:25:20.32#ibcon#read 4, iclass 14, count 2 2006.218.08:25:20.32#ibcon#about to read 5, iclass 14, count 2 2006.218.08:25:20.33#ibcon#read 5, iclass 14, count 2 2006.218.08:25:20.33#ibcon#about to read 6, iclass 14, count 2 2006.218.08:25:20.33#ibcon#read 6, iclass 14, count 2 2006.218.08:25:20.33#ibcon#end of sib2, iclass 14, count 2 2006.218.08:25:20.33#ibcon#*mode == 0, iclass 14, count 2 2006.218.08:25:20.33#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.218.08:25:20.33#ibcon#[25=AT08-07\r\n] 2006.218.08:25:20.33#ibcon#*before write, iclass 14, count 2 2006.218.08:25:20.33#ibcon#enter sib2, iclass 14, count 2 2006.218.08:25:20.33#ibcon#flushed, iclass 14, count 2 2006.218.08:25:20.33#ibcon#about to write, iclass 14, count 2 2006.218.08:25:20.33#ibcon#wrote, iclass 14, count 2 2006.218.08:25:20.33#ibcon#about to read 3, iclass 14, count 2 2006.218.08:25:20.35#ibcon#read 3, iclass 14, count 2 2006.218.08:25:20.35#ibcon#about to read 4, iclass 14, count 2 2006.218.08:25:20.35#ibcon#read 4, iclass 14, count 2 2006.218.08:25:20.35#ibcon#about to read 5, iclass 14, count 2 2006.218.08:25:20.35#ibcon#read 5, iclass 14, count 2 2006.218.08:25:20.36#ibcon#about to read 6, iclass 14, count 2 2006.218.08:25:20.36#ibcon#read 6, iclass 14, count 2 2006.218.08:25:20.36#ibcon#end of sib2, iclass 14, count 2 2006.218.08:25:20.36#ibcon#*after write, iclass 14, count 2 2006.218.08:25:20.36#ibcon#*before return 0, iclass 14, count 2 2006.218.08:25:20.36#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.218.08:25:20.36#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.218.08:25:20.36#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.218.08:25:20.36#ibcon#ireg 7 cls_cnt 0 2006.218.08:25:20.36#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.218.08:25:20.47#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.218.08:25:20.47#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.218.08:25:20.47#ibcon#enter wrdev, iclass 14, count 0 2006.218.08:25:20.47#ibcon#first serial, iclass 14, count 0 2006.218.08:25:20.47#ibcon#enter sib2, iclass 14, count 0 2006.218.08:25:20.47#ibcon#flushed, iclass 14, count 0 2006.218.08:25:20.48#ibcon#about to write, iclass 14, count 0 2006.218.08:25:20.48#ibcon#wrote, iclass 14, count 0 2006.218.08:25:20.48#ibcon#about to read 3, iclass 14, count 0 2006.218.08:25:20.49#ibcon#read 3, iclass 14, count 0 2006.218.08:25:20.49#ibcon#about to read 4, iclass 14, count 0 2006.218.08:25:20.49#ibcon#read 4, iclass 14, count 0 2006.218.08:25:20.49#ibcon#about to read 5, iclass 14, count 0 2006.218.08:25:20.50#ibcon#read 5, iclass 14, count 0 2006.218.08:25:20.50#ibcon#about to read 6, iclass 14, count 0 2006.218.08:25:20.50#ibcon#read 6, iclass 14, count 0 2006.218.08:25:20.50#ibcon#end of sib2, iclass 14, count 0 2006.218.08:25:20.50#ibcon#*mode == 0, iclass 14, count 0 2006.218.08:25:20.50#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.218.08:25:20.50#ibcon#[25=USB\r\n] 2006.218.08:25:20.50#ibcon#*before write, iclass 14, count 0 2006.218.08:25:20.50#ibcon#enter sib2, iclass 14, count 0 2006.218.08:25:20.50#ibcon#flushed, iclass 14, count 0 2006.218.08:25:20.50#ibcon#about to write, iclass 14, count 0 2006.218.08:25:20.50#ibcon#wrote, iclass 14, count 0 2006.218.08:25:20.50#ibcon#about to read 3, iclass 14, count 0 2006.218.08:25:20.52#ibcon#read 3, iclass 14, count 0 2006.218.08:25:20.52#ibcon#about to read 4, iclass 14, count 0 2006.218.08:25:20.52#ibcon#read 4, iclass 14, count 0 2006.218.08:25:20.52#ibcon#about to read 5, iclass 14, count 0 2006.218.08:25:20.53#ibcon#read 5, iclass 14, count 0 2006.218.08:25:20.53#ibcon#about to read 6, iclass 14, count 0 2006.218.08:25:20.53#ibcon#read 6, iclass 14, count 0 2006.218.08:25:20.53#ibcon#end of sib2, iclass 14, count 0 2006.218.08:25:20.53#ibcon#*after write, iclass 14, count 0 2006.218.08:25:20.53#ibcon#*before return 0, iclass 14, count 0 2006.218.08:25:20.53#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.218.08:25:20.53#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.218.08:25:20.53#ibcon#about to clear, iclass 14 cls_cnt 0 2006.218.08:25:20.53#ibcon#cleared, iclass 14 cls_cnt 0 2006.218.08:25:20.53$vc4f8/vblo=1,632.99 2006.218.08:25:20.53#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.218.08:25:20.53#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.218.08:25:20.53#ibcon#ireg 17 cls_cnt 0 2006.218.08:25:20.53#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.218.08:25:20.53#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.218.08:25:20.53#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.218.08:25:20.53#ibcon#enter wrdev, iclass 16, count 0 2006.218.08:25:20.53#ibcon#first serial, iclass 16, count 0 2006.218.08:25:20.53#ibcon#enter sib2, iclass 16, count 0 2006.218.08:25:20.53#ibcon#flushed, iclass 16, count 0 2006.218.08:25:20.53#ibcon#about to write, iclass 16, count 0 2006.218.08:25:20.53#ibcon#wrote, iclass 16, count 0 2006.218.08:25:20.53#ibcon#about to read 3, iclass 16, count 0 2006.218.08:25:20.55#ibcon#read 3, iclass 16, count 0 2006.218.08:25:20.55#ibcon#about to read 4, iclass 16, count 0 2006.218.08:25:20.55#ibcon#read 4, iclass 16, count 0 2006.218.08:25:20.55#ibcon#about to read 5, iclass 16, count 0 2006.218.08:25:20.55#ibcon#read 5, iclass 16, count 0 2006.218.08:25:20.55#ibcon#about to read 6, iclass 16, count 0 2006.218.08:25:20.55#ibcon#read 6, iclass 16, count 0 2006.218.08:25:20.55#ibcon#end of sib2, iclass 16, count 0 2006.218.08:25:20.55#ibcon#*mode == 0, iclass 16, count 0 2006.218.08:25:20.55#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.218.08:25:20.55#ibcon#[28=FRQ=01,632.99\r\n] 2006.218.08:25:20.55#ibcon#*before write, iclass 16, count 0 2006.218.08:25:20.55#ibcon#enter sib2, iclass 16, count 0 2006.218.08:25:20.55#ibcon#flushed, iclass 16, count 0 2006.218.08:25:20.55#ibcon#about to write, iclass 16, count 0 2006.218.08:25:20.55#ibcon#wrote, iclass 16, count 0 2006.218.08:25:20.55#ibcon#about to read 3, iclass 16, count 0 2006.218.08:25:20.59#ibcon#read 3, iclass 16, count 0 2006.218.08:25:20.59#ibcon#about to read 4, iclass 16, count 0 2006.218.08:25:20.60#ibcon#read 4, iclass 16, count 0 2006.218.08:25:20.60#ibcon#about to read 5, iclass 16, count 0 2006.218.08:25:20.60#ibcon#read 5, iclass 16, count 0 2006.218.08:25:20.60#ibcon#about to read 6, iclass 16, count 0 2006.218.08:25:20.60#ibcon#read 6, iclass 16, count 0 2006.218.08:25:20.60#ibcon#end of sib2, iclass 16, count 0 2006.218.08:25:20.60#ibcon#*after write, iclass 16, count 0 2006.218.08:25:20.60#ibcon#*before return 0, iclass 16, count 0 2006.218.08:25:20.60#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.218.08:25:20.60#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.218.08:25:20.60#ibcon#about to clear, iclass 16 cls_cnt 0 2006.218.08:25:20.60#ibcon#cleared, iclass 16 cls_cnt 0 2006.218.08:25:20.60$vc4f8/vb=1,4 2006.218.08:25:20.60#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.218.08:25:20.60#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.218.08:25:20.60#ibcon#ireg 11 cls_cnt 2 2006.218.08:25:20.60#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.218.08:25:20.60#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.218.08:25:20.60#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.218.08:25:20.60#ibcon#enter wrdev, iclass 18, count 2 2006.218.08:25:20.60#ibcon#first serial, iclass 18, count 2 2006.218.08:25:20.60#ibcon#enter sib2, iclass 18, count 2 2006.218.08:25:20.60#ibcon#flushed, iclass 18, count 2 2006.218.08:25:20.60#ibcon#about to write, iclass 18, count 2 2006.218.08:25:20.60#ibcon#wrote, iclass 18, count 2 2006.218.08:25:20.60#ibcon#about to read 3, iclass 18, count 2 2006.218.08:25:20.61#ibcon#read 3, iclass 18, count 2 2006.218.08:25:20.61#ibcon#about to read 4, iclass 18, count 2 2006.218.08:25:20.61#ibcon#read 4, iclass 18, count 2 2006.218.08:25:20.61#ibcon#about to read 5, iclass 18, count 2 2006.218.08:25:20.62#ibcon#read 5, iclass 18, count 2 2006.218.08:25:20.62#ibcon#about to read 6, iclass 18, count 2 2006.218.08:25:20.62#ibcon#read 6, iclass 18, count 2 2006.218.08:25:20.62#ibcon#end of sib2, iclass 18, count 2 2006.218.08:25:20.62#ibcon#*mode == 0, iclass 18, count 2 2006.218.08:25:20.62#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.218.08:25:20.62#ibcon#[27=AT01-04\r\n] 2006.218.08:25:20.62#ibcon#*before write, iclass 18, count 2 2006.218.08:25:20.62#ibcon#enter sib2, iclass 18, count 2 2006.218.08:25:20.62#ibcon#flushed, iclass 18, count 2 2006.218.08:25:20.62#ibcon#about to write, iclass 18, count 2 2006.218.08:25:20.62#ibcon#wrote, iclass 18, count 2 2006.218.08:25:20.62#ibcon#about to read 3, iclass 18, count 2 2006.218.08:25:20.64#ibcon#read 3, iclass 18, count 2 2006.218.08:25:20.64#ibcon#about to read 4, iclass 18, count 2 2006.218.08:25:20.64#ibcon#read 4, iclass 18, count 2 2006.218.08:25:20.64#ibcon#about to read 5, iclass 18, count 2 2006.218.08:25:20.65#ibcon#read 5, iclass 18, count 2 2006.218.08:25:20.65#ibcon#about to read 6, iclass 18, count 2 2006.218.08:25:20.65#ibcon#read 6, iclass 18, count 2 2006.218.08:25:20.65#ibcon#end of sib2, iclass 18, count 2 2006.218.08:25:20.65#ibcon#*after write, iclass 18, count 2 2006.218.08:25:20.65#ibcon#*before return 0, iclass 18, count 2 2006.218.08:25:20.65#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.218.08:25:20.65#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.218.08:25:20.65#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.218.08:25:20.65#ibcon#ireg 7 cls_cnt 0 2006.218.08:25:20.65#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.218.08:25:20.76#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.218.08:25:20.76#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.218.08:25:20.76#ibcon#enter wrdev, iclass 18, count 0 2006.218.08:25:20.76#ibcon#first serial, iclass 18, count 0 2006.218.08:25:20.76#ibcon#enter sib2, iclass 18, count 0 2006.218.08:25:20.76#ibcon#flushed, iclass 18, count 0 2006.218.08:25:20.77#ibcon#about to write, iclass 18, count 0 2006.218.08:25:20.77#ibcon#wrote, iclass 18, count 0 2006.218.08:25:20.77#ibcon#about to read 3, iclass 18, count 0 2006.218.08:25:20.78#ibcon#read 3, iclass 18, count 0 2006.218.08:25:20.78#ibcon#about to read 4, iclass 18, count 0 2006.218.08:25:20.78#ibcon#read 4, iclass 18, count 0 2006.218.08:25:20.78#ibcon#about to read 5, iclass 18, count 0 2006.218.08:25:20.79#ibcon#read 5, iclass 18, count 0 2006.218.08:25:20.79#ibcon#about to read 6, iclass 18, count 0 2006.218.08:25:20.79#ibcon#read 6, iclass 18, count 0 2006.218.08:25:20.79#ibcon#end of sib2, iclass 18, count 0 2006.218.08:25:20.79#ibcon#*mode == 0, iclass 18, count 0 2006.218.08:25:20.79#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.218.08:25:20.79#ibcon#[27=USB\r\n] 2006.218.08:25:20.79#ibcon#*before write, iclass 18, count 0 2006.218.08:25:20.79#ibcon#enter sib2, iclass 18, count 0 2006.218.08:25:20.79#ibcon#flushed, iclass 18, count 0 2006.218.08:25:20.79#ibcon#about to write, iclass 18, count 0 2006.218.08:25:20.79#ibcon#wrote, iclass 18, count 0 2006.218.08:25:20.79#ibcon#about to read 3, iclass 18, count 0 2006.218.08:25:20.81#ibcon#read 3, iclass 18, count 0 2006.218.08:25:20.81#ibcon#about to read 4, iclass 18, count 0 2006.218.08:25:20.81#ibcon#read 4, iclass 18, count 0 2006.218.08:25:20.81#ibcon#about to read 5, iclass 18, count 0 2006.218.08:25:20.82#ibcon#read 5, iclass 18, count 0 2006.218.08:25:20.82#ibcon#about to read 6, iclass 18, count 0 2006.218.08:25:20.82#ibcon#read 6, iclass 18, count 0 2006.218.08:25:20.82#ibcon#end of sib2, iclass 18, count 0 2006.218.08:25:20.82#ibcon#*after write, iclass 18, count 0 2006.218.08:25:20.82#ibcon#*before return 0, iclass 18, count 0 2006.218.08:25:20.82#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.218.08:25:20.82#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.218.08:25:20.82#ibcon#about to clear, iclass 18 cls_cnt 0 2006.218.08:25:20.82#ibcon#cleared, iclass 18 cls_cnt 0 2006.218.08:25:20.82$vc4f8/vblo=2,640.99 2006.218.08:25:20.82#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.218.08:25:20.82#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.218.08:25:20.82#ibcon#ireg 17 cls_cnt 0 2006.218.08:25:20.82#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.218.08:25:20.82#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.218.08:25:20.82#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.218.08:25:20.82#ibcon#enter wrdev, iclass 20, count 0 2006.218.08:25:20.82#ibcon#first serial, iclass 20, count 0 2006.218.08:25:20.82#ibcon#enter sib2, iclass 20, count 0 2006.218.08:25:20.82#ibcon#flushed, iclass 20, count 0 2006.218.08:25:20.82#ibcon#about to write, iclass 20, count 0 2006.218.08:25:20.82#ibcon#wrote, iclass 20, count 0 2006.218.08:25:20.82#ibcon#about to read 3, iclass 20, count 0 2006.218.08:25:20.83#ibcon#read 3, iclass 20, count 0 2006.218.08:25:20.83#ibcon#about to read 4, iclass 20, count 0 2006.218.08:25:20.83#ibcon#read 4, iclass 20, count 0 2006.218.08:25:20.83#ibcon#about to read 5, iclass 20, count 0 2006.218.08:25:20.84#ibcon#read 5, iclass 20, count 0 2006.218.08:25:20.84#ibcon#about to read 6, iclass 20, count 0 2006.218.08:25:20.84#ibcon#read 6, iclass 20, count 0 2006.218.08:25:20.84#ibcon#end of sib2, iclass 20, count 0 2006.218.08:25:20.84#ibcon#*mode == 0, iclass 20, count 0 2006.218.08:25:20.84#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.218.08:25:20.84#ibcon#[28=FRQ=02,640.99\r\n] 2006.218.08:25:20.84#ibcon#*before write, iclass 20, count 0 2006.218.08:25:20.84#ibcon#enter sib2, iclass 20, count 0 2006.218.08:25:20.84#ibcon#flushed, iclass 20, count 0 2006.218.08:25:20.84#ibcon#about to write, iclass 20, count 0 2006.218.08:25:20.84#ibcon#wrote, iclass 20, count 0 2006.218.08:25:20.84#ibcon#about to read 3, iclass 20, count 0 2006.218.08:25:20.87#ibcon#read 3, iclass 20, count 0 2006.218.08:25:20.87#ibcon#about to read 4, iclass 20, count 0 2006.218.08:25:20.87#ibcon#read 4, iclass 20, count 0 2006.218.08:25:20.88#ibcon#about to read 5, iclass 20, count 0 2006.218.08:25:20.88#ibcon#read 5, iclass 20, count 0 2006.218.08:25:20.88#ibcon#about to read 6, iclass 20, count 0 2006.218.08:25:20.88#ibcon#read 6, iclass 20, count 0 2006.218.08:25:20.88#ibcon#end of sib2, iclass 20, count 0 2006.218.08:25:20.88#ibcon#*after write, iclass 20, count 0 2006.218.08:25:20.88#ibcon#*before return 0, iclass 20, count 0 2006.218.08:25:20.88#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.218.08:25:20.88#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.218.08:25:20.88#ibcon#about to clear, iclass 20 cls_cnt 0 2006.218.08:25:20.88#ibcon#cleared, iclass 20 cls_cnt 0 2006.218.08:25:20.88$vc4f8/vb=2,4 2006.218.08:25:20.88#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.218.08:25:20.88#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.218.08:25:20.88#ibcon#ireg 11 cls_cnt 2 2006.218.08:25:20.88#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.218.08:25:20.93#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.218.08:25:20.93#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.218.08:25:20.93#ibcon#enter wrdev, iclass 22, count 2 2006.218.08:25:20.93#ibcon#first serial, iclass 22, count 2 2006.218.08:25:20.93#ibcon#enter sib2, iclass 22, count 2 2006.218.08:25:20.93#ibcon#flushed, iclass 22, count 2 2006.218.08:25:20.94#ibcon#about to write, iclass 22, count 2 2006.218.08:25:20.94#ibcon#wrote, iclass 22, count 2 2006.218.08:25:20.94#ibcon#about to read 3, iclass 22, count 2 2006.218.08:25:20.95#ibcon#read 3, iclass 22, count 2 2006.218.08:25:20.95#ibcon#about to read 4, iclass 22, count 2 2006.218.08:25:20.95#ibcon#read 4, iclass 22, count 2 2006.218.08:25:20.95#ibcon#about to read 5, iclass 22, count 2 2006.218.08:25:20.95#ibcon#read 5, iclass 22, count 2 2006.218.08:25:20.96#ibcon#about to read 6, iclass 22, count 2 2006.218.08:25:20.96#ibcon#read 6, iclass 22, count 2 2006.218.08:25:20.96#ibcon#end of sib2, iclass 22, count 2 2006.218.08:25:20.96#ibcon#*mode == 0, iclass 22, count 2 2006.218.08:25:20.96#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.218.08:25:20.96#ibcon#[27=AT02-04\r\n] 2006.218.08:25:20.96#ibcon#*before write, iclass 22, count 2 2006.218.08:25:20.96#ibcon#enter sib2, iclass 22, count 2 2006.218.08:25:20.96#ibcon#flushed, iclass 22, count 2 2006.218.08:25:20.96#ibcon#about to write, iclass 22, count 2 2006.218.08:25:20.96#ibcon#wrote, iclass 22, count 2 2006.218.08:25:20.96#ibcon#about to read 3, iclass 22, count 2 2006.218.08:25:20.98#ibcon#read 3, iclass 22, count 2 2006.218.08:25:20.98#ibcon#about to read 4, iclass 22, count 2 2006.218.08:25:20.98#ibcon#read 4, iclass 22, count 2 2006.218.08:25:20.98#ibcon#about to read 5, iclass 22, count 2 2006.218.08:25:20.99#ibcon#read 5, iclass 22, count 2 2006.218.08:25:20.99#ibcon#about to read 6, iclass 22, count 2 2006.218.08:25:20.99#ibcon#read 6, iclass 22, count 2 2006.218.08:25:20.99#ibcon#end of sib2, iclass 22, count 2 2006.218.08:25:20.99#ibcon#*after write, iclass 22, count 2 2006.218.08:25:20.99#ibcon#*before return 0, iclass 22, count 2 2006.218.08:25:20.99#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.218.08:25:20.99#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.218.08:25:20.99#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.218.08:25:20.99#ibcon#ireg 7 cls_cnt 0 2006.218.08:25:20.99#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.218.08:25:21.10#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.218.08:25:21.10#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.218.08:25:21.10#ibcon#enter wrdev, iclass 22, count 0 2006.218.08:25:21.10#ibcon#first serial, iclass 22, count 0 2006.218.08:25:21.10#ibcon#enter sib2, iclass 22, count 0 2006.218.08:25:21.10#ibcon#flushed, iclass 22, count 0 2006.218.08:25:21.11#ibcon#about to write, iclass 22, count 0 2006.218.08:25:21.11#ibcon#wrote, iclass 22, count 0 2006.218.08:25:21.11#ibcon#about to read 3, iclass 22, count 0 2006.218.08:25:21.12#ibcon#read 3, iclass 22, count 0 2006.218.08:25:21.12#ibcon#about to read 4, iclass 22, count 0 2006.218.08:25:21.12#ibcon#read 4, iclass 22, count 0 2006.218.08:25:21.12#ibcon#about to read 5, iclass 22, count 0 2006.218.08:25:21.12#ibcon#read 5, iclass 22, count 0 2006.218.08:25:21.13#ibcon#about to read 6, iclass 22, count 0 2006.218.08:25:21.13#ibcon#read 6, iclass 22, count 0 2006.218.08:25:21.13#ibcon#end of sib2, iclass 22, count 0 2006.218.08:25:21.13#ibcon#*mode == 0, iclass 22, count 0 2006.218.08:25:21.13#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.218.08:25:21.13#ibcon#[27=USB\r\n] 2006.218.08:25:21.13#ibcon#*before write, iclass 22, count 0 2006.218.08:25:21.13#ibcon#enter sib2, iclass 22, count 0 2006.218.08:25:21.13#ibcon#flushed, iclass 22, count 0 2006.218.08:25:21.13#ibcon#about to write, iclass 22, count 0 2006.218.08:25:21.13#ibcon#wrote, iclass 22, count 0 2006.218.08:25:21.13#ibcon#about to read 3, iclass 22, count 0 2006.218.08:25:21.15#ibcon#read 3, iclass 22, count 0 2006.218.08:25:21.15#ibcon#about to read 4, iclass 22, count 0 2006.218.08:25:21.15#ibcon#read 4, iclass 22, count 0 2006.218.08:25:21.15#ibcon#about to read 5, iclass 22, count 0 2006.218.08:25:21.16#ibcon#read 5, iclass 22, count 0 2006.218.08:25:21.16#ibcon#about to read 6, iclass 22, count 0 2006.218.08:25:21.16#ibcon#read 6, iclass 22, count 0 2006.218.08:25:21.16#ibcon#end of sib2, iclass 22, count 0 2006.218.08:25:21.16#ibcon#*after write, iclass 22, count 0 2006.218.08:25:21.16#ibcon#*before return 0, iclass 22, count 0 2006.218.08:25:21.16#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.218.08:25:21.16#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.218.08:25:21.16#ibcon#about to clear, iclass 22 cls_cnt 0 2006.218.08:25:21.16#ibcon#cleared, iclass 22 cls_cnt 0 2006.218.08:25:21.16$vc4f8/vblo=3,656.99 2006.218.08:25:21.16#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.218.08:25:21.16#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.218.08:25:21.16#ibcon#ireg 17 cls_cnt 0 2006.218.08:25:21.16#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.218.08:25:21.16#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.218.08:25:21.16#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.218.08:25:21.16#ibcon#enter wrdev, iclass 24, count 0 2006.218.08:25:21.16#ibcon#first serial, iclass 24, count 0 2006.218.08:25:21.16#ibcon#enter sib2, iclass 24, count 0 2006.218.08:25:21.16#ibcon#flushed, iclass 24, count 0 2006.218.08:25:21.16#ibcon#about to write, iclass 24, count 0 2006.218.08:25:21.16#ibcon#wrote, iclass 24, count 0 2006.218.08:25:21.16#ibcon#about to read 3, iclass 24, count 0 2006.218.08:25:21.17#ibcon#read 3, iclass 24, count 0 2006.218.08:25:21.17#ibcon#about to read 4, iclass 24, count 0 2006.218.08:25:21.17#ibcon#read 4, iclass 24, count 0 2006.218.08:25:21.17#ibcon#about to read 5, iclass 24, count 0 2006.218.08:25:21.18#ibcon#read 5, iclass 24, count 0 2006.218.08:25:21.18#ibcon#about to read 6, iclass 24, count 0 2006.218.08:25:21.18#ibcon#read 6, iclass 24, count 0 2006.218.08:25:21.18#ibcon#end of sib2, iclass 24, count 0 2006.218.08:25:21.18#ibcon#*mode == 0, iclass 24, count 0 2006.218.08:25:21.18#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.218.08:25:21.18#ibcon#[28=FRQ=03,656.99\r\n] 2006.218.08:25:21.18#ibcon#*before write, iclass 24, count 0 2006.218.08:25:21.18#ibcon#enter sib2, iclass 24, count 0 2006.218.08:25:21.18#ibcon#flushed, iclass 24, count 0 2006.218.08:25:21.18#ibcon#about to write, iclass 24, count 0 2006.218.08:25:21.18#ibcon#wrote, iclass 24, count 0 2006.218.08:25:21.18#ibcon#about to read 3, iclass 24, count 0 2006.218.08:25:21.21#ibcon#read 3, iclass 24, count 0 2006.218.08:25:21.21#ibcon#about to read 4, iclass 24, count 0 2006.218.08:25:21.21#ibcon#read 4, iclass 24, count 0 2006.218.08:25:21.21#ibcon#about to read 5, iclass 24, count 0 2006.218.08:25:21.22#ibcon#read 5, iclass 24, count 0 2006.218.08:25:21.22#ibcon#about to read 6, iclass 24, count 0 2006.218.08:25:21.22#ibcon#read 6, iclass 24, count 0 2006.218.08:25:21.22#ibcon#end of sib2, iclass 24, count 0 2006.218.08:25:21.22#ibcon#*after write, iclass 24, count 0 2006.218.08:25:21.22#ibcon#*before return 0, iclass 24, count 0 2006.218.08:25:21.22#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.218.08:25:21.22#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.218.08:25:21.22#ibcon#about to clear, iclass 24 cls_cnt 0 2006.218.08:25:21.22#ibcon#cleared, iclass 24 cls_cnt 0 2006.218.08:25:21.22$vc4f8/vb=3,4 2006.218.08:25:21.22#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.218.08:25:21.22#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.218.08:25:21.22#ibcon#ireg 11 cls_cnt 2 2006.218.08:25:21.22#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.218.08:25:21.27#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.218.08:25:21.27#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.218.08:25:21.27#ibcon#enter wrdev, iclass 26, count 2 2006.218.08:25:21.27#ibcon#first serial, iclass 26, count 2 2006.218.08:25:21.27#ibcon#enter sib2, iclass 26, count 2 2006.218.08:25:21.27#ibcon#flushed, iclass 26, count 2 2006.218.08:25:21.28#ibcon#about to write, iclass 26, count 2 2006.218.08:25:21.28#ibcon#wrote, iclass 26, count 2 2006.218.08:25:21.28#ibcon#about to read 3, iclass 26, count 2 2006.218.08:25:21.29#ibcon#read 3, iclass 26, count 2 2006.218.08:25:21.29#ibcon#about to read 4, iclass 26, count 2 2006.218.08:25:21.29#ibcon#read 4, iclass 26, count 2 2006.218.08:25:21.29#ibcon#about to read 5, iclass 26, count 2 2006.218.08:25:21.30#ibcon#read 5, iclass 26, count 2 2006.218.08:25:21.30#ibcon#about to read 6, iclass 26, count 2 2006.218.08:25:21.30#ibcon#read 6, iclass 26, count 2 2006.218.08:25:21.30#ibcon#end of sib2, iclass 26, count 2 2006.218.08:25:21.30#ibcon#*mode == 0, iclass 26, count 2 2006.218.08:25:21.30#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.218.08:25:21.30#ibcon#[27=AT03-04\r\n] 2006.218.08:25:21.30#ibcon#*before write, iclass 26, count 2 2006.218.08:25:21.30#ibcon#enter sib2, iclass 26, count 2 2006.218.08:25:21.30#ibcon#flushed, iclass 26, count 2 2006.218.08:25:21.30#ibcon#about to write, iclass 26, count 2 2006.218.08:25:21.30#ibcon#wrote, iclass 26, count 2 2006.218.08:25:21.30#ibcon#about to read 3, iclass 26, count 2 2006.218.08:25:21.32#ibcon#read 3, iclass 26, count 2 2006.218.08:25:21.32#ibcon#about to read 4, iclass 26, count 2 2006.218.08:25:21.32#ibcon#read 4, iclass 26, count 2 2006.218.08:25:21.32#ibcon#about to read 5, iclass 26, count 2 2006.218.08:25:21.33#ibcon#read 5, iclass 26, count 2 2006.218.08:25:21.33#ibcon#about to read 6, iclass 26, count 2 2006.218.08:25:21.33#ibcon#read 6, iclass 26, count 2 2006.218.08:25:21.33#ibcon#end of sib2, iclass 26, count 2 2006.218.08:25:21.33#ibcon#*after write, iclass 26, count 2 2006.218.08:25:21.33#ibcon#*before return 0, iclass 26, count 2 2006.218.08:25:21.33#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.218.08:25:21.33#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.218.08:25:21.33#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.218.08:25:21.33#ibcon#ireg 7 cls_cnt 0 2006.218.08:25:21.33#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.218.08:25:21.44#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.218.08:25:21.44#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.218.08:25:21.44#ibcon#enter wrdev, iclass 26, count 0 2006.218.08:25:21.44#ibcon#first serial, iclass 26, count 0 2006.218.08:25:21.44#ibcon#enter sib2, iclass 26, count 0 2006.218.08:25:21.44#ibcon#flushed, iclass 26, count 0 2006.218.08:25:21.45#ibcon#about to write, iclass 26, count 0 2006.218.08:25:21.45#ibcon#wrote, iclass 26, count 0 2006.218.08:25:21.45#ibcon#about to read 3, iclass 26, count 0 2006.218.08:25:21.46#ibcon#read 3, iclass 26, count 0 2006.218.08:25:21.46#ibcon#about to read 4, iclass 26, count 0 2006.218.08:25:21.46#ibcon#read 4, iclass 26, count 0 2006.218.08:25:21.46#ibcon#about to read 5, iclass 26, count 0 2006.218.08:25:21.46#ibcon#read 5, iclass 26, count 0 2006.218.08:25:21.47#ibcon#about to read 6, iclass 26, count 0 2006.218.08:25:21.47#ibcon#read 6, iclass 26, count 0 2006.218.08:25:21.47#ibcon#end of sib2, iclass 26, count 0 2006.218.08:25:21.47#ibcon#*mode == 0, iclass 26, count 0 2006.218.08:25:21.47#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.218.08:25:21.47#ibcon#[27=USB\r\n] 2006.218.08:25:21.47#ibcon#*before write, iclass 26, count 0 2006.218.08:25:21.47#ibcon#enter sib2, iclass 26, count 0 2006.218.08:25:21.47#ibcon#flushed, iclass 26, count 0 2006.218.08:25:21.47#ibcon#about to write, iclass 26, count 0 2006.218.08:25:21.47#ibcon#wrote, iclass 26, count 0 2006.218.08:25:21.47#ibcon#about to read 3, iclass 26, count 0 2006.218.08:25:21.49#ibcon#read 3, iclass 26, count 0 2006.218.08:25:21.49#ibcon#about to read 4, iclass 26, count 0 2006.218.08:25:21.49#ibcon#read 4, iclass 26, count 0 2006.218.08:25:21.49#ibcon#about to read 5, iclass 26, count 0 2006.218.08:25:21.50#ibcon#read 5, iclass 26, count 0 2006.218.08:25:21.50#ibcon#about to read 6, iclass 26, count 0 2006.218.08:25:21.50#ibcon#read 6, iclass 26, count 0 2006.218.08:25:21.50#ibcon#end of sib2, iclass 26, count 0 2006.218.08:25:21.50#ibcon#*after write, iclass 26, count 0 2006.218.08:25:21.50#ibcon#*before return 0, iclass 26, count 0 2006.218.08:25:21.50#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.218.08:25:21.50#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.218.08:25:21.50#ibcon#about to clear, iclass 26 cls_cnt 0 2006.218.08:25:21.50#ibcon#cleared, iclass 26 cls_cnt 0 2006.218.08:25:21.50$vc4f8/vblo=4,712.99 2006.218.08:25:21.50#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.218.08:25:21.50#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.218.08:25:21.50#ibcon#ireg 17 cls_cnt 0 2006.218.08:25:21.50#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.218.08:25:21.50#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.218.08:25:21.50#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.218.08:25:21.50#ibcon#enter wrdev, iclass 28, count 0 2006.218.08:25:21.50#ibcon#first serial, iclass 28, count 0 2006.218.08:25:21.50#ibcon#enter sib2, iclass 28, count 0 2006.218.08:25:21.50#ibcon#flushed, iclass 28, count 0 2006.218.08:25:21.50#ibcon#about to write, iclass 28, count 0 2006.218.08:25:21.50#ibcon#wrote, iclass 28, count 0 2006.218.08:25:21.50#ibcon#about to read 3, iclass 28, count 0 2006.218.08:25:21.51#ibcon#read 3, iclass 28, count 0 2006.218.08:25:21.51#ibcon#about to read 4, iclass 28, count 0 2006.218.08:25:21.51#ibcon#read 4, iclass 28, count 0 2006.218.08:25:21.51#ibcon#about to read 5, iclass 28, count 0 2006.218.08:25:21.52#ibcon#read 5, iclass 28, count 0 2006.218.08:25:21.52#ibcon#about to read 6, iclass 28, count 0 2006.218.08:25:21.52#ibcon#read 6, iclass 28, count 0 2006.218.08:25:21.52#ibcon#end of sib2, iclass 28, count 0 2006.218.08:25:21.52#ibcon#*mode == 0, iclass 28, count 0 2006.218.08:25:21.52#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.218.08:25:21.52#ibcon#[28=FRQ=04,712.99\r\n] 2006.218.08:25:21.52#ibcon#*before write, iclass 28, count 0 2006.218.08:25:21.52#ibcon#enter sib2, iclass 28, count 0 2006.218.08:25:21.52#ibcon#flushed, iclass 28, count 0 2006.218.08:25:21.52#ibcon#about to write, iclass 28, count 0 2006.218.08:25:21.52#ibcon#wrote, iclass 28, count 0 2006.218.08:25:21.52#ibcon#about to read 3, iclass 28, count 0 2006.218.08:25:21.55#ibcon#read 3, iclass 28, count 0 2006.218.08:25:21.55#ibcon#about to read 4, iclass 28, count 0 2006.218.08:25:21.55#ibcon#read 4, iclass 28, count 0 2006.218.08:25:21.55#ibcon#about to read 5, iclass 28, count 0 2006.218.08:25:21.56#ibcon#read 5, iclass 28, count 0 2006.218.08:25:21.56#ibcon#about to read 6, iclass 28, count 0 2006.218.08:25:21.56#ibcon#read 6, iclass 28, count 0 2006.218.08:25:21.56#ibcon#end of sib2, iclass 28, count 0 2006.218.08:25:21.56#ibcon#*after write, iclass 28, count 0 2006.218.08:25:21.56#ibcon#*before return 0, iclass 28, count 0 2006.218.08:25:21.56#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.218.08:25:21.56#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.218.08:25:21.56#ibcon#about to clear, iclass 28 cls_cnt 0 2006.218.08:25:21.56#ibcon#cleared, iclass 28 cls_cnt 0 2006.218.08:25:21.56$vc4f8/vb=4,4 2006.218.08:25:21.56#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.218.08:25:21.56#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.218.08:25:21.56#ibcon#ireg 11 cls_cnt 2 2006.218.08:25:21.56#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.218.08:25:21.61#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.218.08:25:21.61#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.218.08:25:21.61#ibcon#enter wrdev, iclass 30, count 2 2006.218.08:25:21.61#ibcon#first serial, iclass 30, count 2 2006.218.08:25:21.61#ibcon#enter sib2, iclass 30, count 2 2006.218.08:25:21.61#ibcon#flushed, iclass 30, count 2 2006.218.08:25:21.62#ibcon#about to write, iclass 30, count 2 2006.218.08:25:21.62#ibcon#wrote, iclass 30, count 2 2006.218.08:25:21.62#ibcon#about to read 3, iclass 30, count 2 2006.218.08:25:21.63#ibcon#read 3, iclass 30, count 2 2006.218.08:25:21.63#ibcon#about to read 4, iclass 30, count 2 2006.218.08:25:21.63#ibcon#read 4, iclass 30, count 2 2006.218.08:25:21.63#ibcon#about to read 5, iclass 30, count 2 2006.218.08:25:21.63#ibcon#read 5, iclass 30, count 2 2006.218.08:25:21.64#ibcon#about to read 6, iclass 30, count 2 2006.218.08:25:21.64#ibcon#read 6, iclass 30, count 2 2006.218.08:25:21.64#ibcon#end of sib2, iclass 30, count 2 2006.218.08:25:21.64#ibcon#*mode == 0, iclass 30, count 2 2006.218.08:25:21.64#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.218.08:25:21.64#ibcon#[27=AT04-04\r\n] 2006.218.08:25:21.64#ibcon#*before write, iclass 30, count 2 2006.218.08:25:21.64#ibcon#enter sib2, iclass 30, count 2 2006.218.08:25:21.64#ibcon#flushed, iclass 30, count 2 2006.218.08:25:21.64#ibcon#about to write, iclass 30, count 2 2006.218.08:25:21.64#ibcon#wrote, iclass 30, count 2 2006.218.08:25:21.64#ibcon#about to read 3, iclass 30, count 2 2006.218.08:25:21.66#ibcon#read 3, iclass 30, count 2 2006.218.08:25:21.66#ibcon#about to read 4, iclass 30, count 2 2006.218.08:25:21.67#ibcon#read 4, iclass 30, count 2 2006.218.08:25:21.67#ibcon#about to read 5, iclass 30, count 2 2006.218.08:25:21.67#ibcon#read 5, iclass 30, count 2 2006.218.08:25:21.67#ibcon#about to read 6, iclass 30, count 2 2006.218.08:25:21.67#ibcon#read 6, iclass 30, count 2 2006.218.08:25:21.67#ibcon#end of sib2, iclass 30, count 2 2006.218.08:25:21.67#ibcon#*after write, iclass 30, count 2 2006.218.08:25:21.67#ibcon#*before return 0, iclass 30, count 2 2006.218.08:25:21.67#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.218.08:25:21.67#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.218.08:25:21.67#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.218.08:25:21.67#ibcon#ireg 7 cls_cnt 0 2006.218.08:25:21.67#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.218.08:25:21.78#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.218.08:25:21.78#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.218.08:25:21.78#ibcon#enter wrdev, iclass 30, count 0 2006.218.08:25:21.78#ibcon#first serial, iclass 30, count 0 2006.218.08:25:21.78#ibcon#enter sib2, iclass 30, count 0 2006.218.08:25:21.78#ibcon#flushed, iclass 30, count 0 2006.218.08:25:21.79#ibcon#about to write, iclass 30, count 0 2006.218.08:25:21.79#ibcon#wrote, iclass 30, count 0 2006.218.08:25:21.79#ibcon#about to read 3, iclass 30, count 0 2006.218.08:25:21.80#ibcon#read 3, iclass 30, count 0 2006.218.08:25:21.80#ibcon#about to read 4, iclass 30, count 0 2006.218.08:25:21.80#ibcon#read 4, iclass 30, count 0 2006.218.08:25:21.80#ibcon#about to read 5, iclass 30, count 0 2006.218.08:25:21.80#ibcon#read 5, iclass 30, count 0 2006.218.08:25:21.81#ibcon#about to read 6, iclass 30, count 0 2006.218.08:25:21.81#ibcon#read 6, iclass 30, count 0 2006.218.08:25:21.81#ibcon#end of sib2, iclass 30, count 0 2006.218.08:25:21.81#ibcon#*mode == 0, iclass 30, count 0 2006.218.08:25:21.81#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.218.08:25:21.81#ibcon#[27=USB\r\n] 2006.218.08:25:21.81#ibcon#*before write, iclass 30, count 0 2006.218.08:25:21.81#ibcon#enter sib2, iclass 30, count 0 2006.218.08:25:21.81#ibcon#flushed, iclass 30, count 0 2006.218.08:25:21.81#ibcon#about to write, iclass 30, count 0 2006.218.08:25:21.81#ibcon#wrote, iclass 30, count 0 2006.218.08:25:21.81#ibcon#about to read 3, iclass 30, count 0 2006.218.08:25:21.83#ibcon#read 3, iclass 30, count 0 2006.218.08:25:21.83#ibcon#about to read 4, iclass 30, count 0 2006.218.08:25:21.83#ibcon#read 4, iclass 30, count 0 2006.218.08:25:21.83#ibcon#about to read 5, iclass 30, count 0 2006.218.08:25:21.84#ibcon#read 5, iclass 30, count 0 2006.218.08:25:21.84#ibcon#about to read 6, iclass 30, count 0 2006.218.08:25:21.84#ibcon#read 6, iclass 30, count 0 2006.218.08:25:21.84#ibcon#end of sib2, iclass 30, count 0 2006.218.08:25:21.84#ibcon#*after write, iclass 30, count 0 2006.218.08:25:21.84#ibcon#*before return 0, iclass 30, count 0 2006.218.08:25:21.84#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.218.08:25:21.84#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.218.08:25:21.84#ibcon#about to clear, iclass 30 cls_cnt 0 2006.218.08:25:21.84#ibcon#cleared, iclass 30 cls_cnt 0 2006.218.08:25:21.84$vc4f8/vblo=5,744.99 2006.218.08:25:21.84#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.218.08:25:21.84#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.218.08:25:21.84#ibcon#ireg 17 cls_cnt 0 2006.218.08:25:21.84#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.218.08:25:21.84#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.218.08:25:21.84#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.218.08:25:21.84#ibcon#enter wrdev, iclass 32, count 0 2006.218.08:25:21.84#ibcon#first serial, iclass 32, count 0 2006.218.08:25:21.84#ibcon#enter sib2, iclass 32, count 0 2006.218.08:25:21.84#ibcon#flushed, iclass 32, count 0 2006.218.08:25:21.84#ibcon#about to write, iclass 32, count 0 2006.218.08:25:21.84#ibcon#wrote, iclass 32, count 0 2006.218.08:25:21.84#ibcon#about to read 3, iclass 32, count 0 2006.218.08:25:21.85#ibcon#read 3, iclass 32, count 0 2006.218.08:25:21.85#ibcon#about to read 4, iclass 32, count 0 2006.218.08:25:21.85#ibcon#read 4, iclass 32, count 0 2006.218.08:25:21.85#ibcon#about to read 5, iclass 32, count 0 2006.218.08:25:21.85#ibcon#read 5, iclass 32, count 0 2006.218.08:25:21.86#ibcon#about to read 6, iclass 32, count 0 2006.218.08:25:21.86#ibcon#read 6, iclass 32, count 0 2006.218.08:25:21.86#ibcon#end of sib2, iclass 32, count 0 2006.218.08:25:21.86#ibcon#*mode == 0, iclass 32, count 0 2006.218.08:25:21.86#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.218.08:25:21.86#ibcon#[28=FRQ=05,744.99\r\n] 2006.218.08:25:21.86#ibcon#*before write, iclass 32, count 0 2006.218.08:25:21.86#ibcon#enter sib2, iclass 32, count 0 2006.218.08:25:21.86#ibcon#flushed, iclass 32, count 0 2006.218.08:25:21.86#ibcon#about to write, iclass 32, count 0 2006.218.08:25:21.86#ibcon#wrote, iclass 32, count 0 2006.218.08:25:21.86#ibcon#about to read 3, iclass 32, count 0 2006.218.08:25:21.89#ibcon#read 3, iclass 32, count 0 2006.218.08:25:21.89#ibcon#about to read 4, iclass 32, count 0 2006.218.08:25:21.89#ibcon#read 4, iclass 32, count 0 2006.218.08:25:21.89#ibcon#about to read 5, iclass 32, count 0 2006.218.08:25:21.90#ibcon#read 5, iclass 32, count 0 2006.218.08:25:21.90#ibcon#about to read 6, iclass 32, count 0 2006.218.08:25:21.90#ibcon#read 6, iclass 32, count 0 2006.218.08:25:21.90#ibcon#end of sib2, iclass 32, count 0 2006.218.08:25:21.90#ibcon#*after write, iclass 32, count 0 2006.218.08:25:21.90#ibcon#*before return 0, iclass 32, count 0 2006.218.08:25:21.90#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.218.08:25:21.90#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.218.08:25:21.90#ibcon#about to clear, iclass 32 cls_cnt 0 2006.218.08:25:21.90#ibcon#cleared, iclass 32 cls_cnt 0 2006.218.08:25:21.90$vc4f8/vb=5,4 2006.218.08:25:21.90#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.218.08:25:21.90#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.218.08:25:21.90#ibcon#ireg 11 cls_cnt 2 2006.218.08:25:21.90#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.218.08:25:21.95#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.218.08:25:21.95#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.218.08:25:21.95#ibcon#enter wrdev, iclass 34, count 2 2006.218.08:25:21.95#ibcon#first serial, iclass 34, count 2 2006.218.08:25:21.95#ibcon#enter sib2, iclass 34, count 2 2006.218.08:25:21.95#ibcon#flushed, iclass 34, count 2 2006.218.08:25:21.96#ibcon#about to write, iclass 34, count 2 2006.218.08:25:21.96#ibcon#wrote, iclass 34, count 2 2006.218.08:25:21.96#ibcon#about to read 3, iclass 34, count 2 2006.218.08:25:21.97#ibcon#read 3, iclass 34, count 2 2006.218.08:25:21.97#ibcon#about to read 4, iclass 34, count 2 2006.218.08:25:21.97#ibcon#read 4, iclass 34, count 2 2006.218.08:25:21.97#ibcon#about to read 5, iclass 34, count 2 2006.218.08:25:21.97#ibcon#read 5, iclass 34, count 2 2006.218.08:25:21.98#ibcon#about to read 6, iclass 34, count 2 2006.218.08:25:21.98#ibcon#read 6, iclass 34, count 2 2006.218.08:25:21.98#ibcon#end of sib2, iclass 34, count 2 2006.218.08:25:21.98#ibcon#*mode == 0, iclass 34, count 2 2006.218.08:25:21.98#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.218.08:25:21.98#ibcon#[27=AT05-04\r\n] 2006.218.08:25:21.98#ibcon#*before write, iclass 34, count 2 2006.218.08:25:21.98#ibcon#enter sib2, iclass 34, count 2 2006.218.08:25:21.98#ibcon#flushed, iclass 34, count 2 2006.218.08:25:21.98#ibcon#about to write, iclass 34, count 2 2006.218.08:25:21.98#ibcon#wrote, iclass 34, count 2 2006.218.08:25:21.98#ibcon#about to read 3, iclass 34, count 2 2006.218.08:25:22.00#ibcon#read 3, iclass 34, count 2 2006.218.08:25:22.00#ibcon#about to read 4, iclass 34, count 2 2006.218.08:25:22.00#ibcon#read 4, iclass 34, count 2 2006.218.08:25:22.00#ibcon#about to read 5, iclass 34, count 2 2006.218.08:25:22.01#ibcon#read 5, iclass 34, count 2 2006.218.08:25:22.01#ibcon#about to read 6, iclass 34, count 2 2006.218.08:25:22.01#ibcon#read 6, iclass 34, count 2 2006.218.08:25:22.01#ibcon#end of sib2, iclass 34, count 2 2006.218.08:25:22.01#ibcon#*after write, iclass 34, count 2 2006.218.08:25:22.01#ibcon#*before return 0, iclass 34, count 2 2006.218.08:25:22.01#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.218.08:25:22.01#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.218.08:25:22.01#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.218.08:25:22.01#ibcon#ireg 7 cls_cnt 0 2006.218.08:25:22.01#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.218.08:25:22.12#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.218.08:25:22.12#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.218.08:25:22.12#ibcon#enter wrdev, iclass 34, count 0 2006.218.08:25:22.12#ibcon#first serial, iclass 34, count 0 2006.218.08:25:22.12#ibcon#enter sib2, iclass 34, count 0 2006.218.08:25:22.12#ibcon#flushed, iclass 34, count 0 2006.218.08:25:22.13#ibcon#about to write, iclass 34, count 0 2006.218.08:25:22.13#ibcon#wrote, iclass 34, count 0 2006.218.08:25:22.13#ibcon#about to read 3, iclass 34, count 0 2006.218.08:25:22.14#ibcon#read 3, iclass 34, count 0 2006.218.08:25:22.14#ibcon#about to read 4, iclass 34, count 0 2006.218.08:25:22.14#ibcon#read 4, iclass 34, count 0 2006.218.08:25:22.14#ibcon#about to read 5, iclass 34, count 0 2006.218.08:25:22.14#ibcon#read 5, iclass 34, count 0 2006.218.08:25:22.15#ibcon#about to read 6, iclass 34, count 0 2006.218.08:25:22.15#ibcon#read 6, iclass 34, count 0 2006.218.08:25:22.15#ibcon#end of sib2, iclass 34, count 0 2006.218.08:25:22.15#ibcon#*mode == 0, iclass 34, count 0 2006.218.08:25:22.15#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.218.08:25:22.15#ibcon#[27=USB\r\n] 2006.218.08:25:22.15#ibcon#*before write, iclass 34, count 0 2006.218.08:25:22.15#ibcon#enter sib2, iclass 34, count 0 2006.218.08:25:22.15#ibcon#flushed, iclass 34, count 0 2006.218.08:25:22.15#ibcon#about to write, iclass 34, count 0 2006.218.08:25:22.15#ibcon#wrote, iclass 34, count 0 2006.218.08:25:22.15#ibcon#about to read 3, iclass 34, count 0 2006.218.08:25:22.17#ibcon#read 3, iclass 34, count 0 2006.218.08:25:22.17#ibcon#about to read 4, iclass 34, count 0 2006.218.08:25:22.17#ibcon#read 4, iclass 34, count 0 2006.218.08:25:22.17#ibcon#about to read 5, iclass 34, count 0 2006.218.08:25:22.17#ibcon#read 5, iclass 34, count 0 2006.218.08:25:22.18#ibcon#about to read 6, iclass 34, count 0 2006.218.08:25:22.18#ibcon#read 6, iclass 34, count 0 2006.218.08:25:22.18#ibcon#end of sib2, iclass 34, count 0 2006.218.08:25:22.18#ibcon#*after write, iclass 34, count 0 2006.218.08:25:22.18#ibcon#*before return 0, iclass 34, count 0 2006.218.08:25:22.18#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.218.08:25:22.18#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.218.08:25:22.18#ibcon#about to clear, iclass 34 cls_cnt 0 2006.218.08:25:22.18#ibcon#cleared, iclass 34 cls_cnt 0 2006.218.08:25:22.18$vc4f8/vblo=6,752.99 2006.218.08:25:22.18#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.218.08:25:22.18#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.218.08:25:22.18#ibcon#ireg 17 cls_cnt 0 2006.218.08:25:22.18#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.218.08:25:22.18#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.218.08:25:22.18#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.218.08:25:22.18#ibcon#enter wrdev, iclass 36, count 0 2006.218.08:25:22.18#ibcon#first serial, iclass 36, count 0 2006.218.08:25:22.18#ibcon#enter sib2, iclass 36, count 0 2006.218.08:25:22.18#ibcon#flushed, iclass 36, count 0 2006.218.08:25:22.18#ibcon#about to write, iclass 36, count 0 2006.218.08:25:22.18#ibcon#wrote, iclass 36, count 0 2006.218.08:25:22.18#ibcon#about to read 3, iclass 36, count 0 2006.218.08:25:22.19#ibcon#read 3, iclass 36, count 0 2006.218.08:25:22.19#ibcon#about to read 4, iclass 36, count 0 2006.218.08:25:22.19#ibcon#read 4, iclass 36, count 0 2006.218.08:25:22.19#ibcon#about to read 5, iclass 36, count 0 2006.218.08:25:22.20#ibcon#read 5, iclass 36, count 0 2006.218.08:25:22.20#ibcon#about to read 6, iclass 36, count 0 2006.218.08:25:22.20#ibcon#read 6, iclass 36, count 0 2006.218.08:25:22.20#ibcon#end of sib2, iclass 36, count 0 2006.218.08:25:22.20#ibcon#*mode == 0, iclass 36, count 0 2006.218.08:25:22.20#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.218.08:25:22.20#ibcon#[28=FRQ=06,752.99\r\n] 2006.218.08:25:22.20#ibcon#*before write, iclass 36, count 0 2006.218.08:25:22.20#ibcon#enter sib2, iclass 36, count 0 2006.218.08:25:22.20#ibcon#flushed, iclass 36, count 0 2006.218.08:25:22.20#ibcon#about to write, iclass 36, count 0 2006.218.08:25:22.20#ibcon#wrote, iclass 36, count 0 2006.218.08:25:22.20#ibcon#about to read 3, iclass 36, count 0 2006.218.08:25:22.23#ibcon#read 3, iclass 36, count 0 2006.218.08:25:22.23#ibcon#about to read 4, iclass 36, count 0 2006.218.08:25:22.23#ibcon#read 4, iclass 36, count 0 2006.218.08:25:22.23#ibcon#about to read 5, iclass 36, count 0 2006.218.08:25:22.24#ibcon#read 5, iclass 36, count 0 2006.218.08:25:22.24#ibcon#about to read 6, iclass 36, count 0 2006.218.08:25:22.24#ibcon#read 6, iclass 36, count 0 2006.218.08:25:22.24#ibcon#end of sib2, iclass 36, count 0 2006.218.08:25:22.24#ibcon#*after write, iclass 36, count 0 2006.218.08:25:22.24#ibcon#*before return 0, iclass 36, count 0 2006.218.08:25:22.24#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.218.08:25:22.24#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.218.08:25:22.24#ibcon#about to clear, iclass 36 cls_cnt 0 2006.218.08:25:22.24#ibcon#cleared, iclass 36 cls_cnt 0 2006.218.08:25:22.24$vc4f8/vb=6,4 2006.218.08:25:22.24#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.218.08:25:22.24#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.218.08:25:22.24#ibcon#ireg 11 cls_cnt 2 2006.218.08:25:22.24#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.218.08:25:22.30#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.218.08:25:22.30#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.218.08:25:22.30#ibcon#enter wrdev, iclass 38, count 2 2006.218.08:25:22.30#ibcon#first serial, iclass 38, count 2 2006.218.08:25:22.30#ibcon#enter sib2, iclass 38, count 2 2006.218.08:25:22.30#ibcon#flushed, iclass 38, count 2 2006.218.08:25:22.30#ibcon#about to write, iclass 38, count 2 2006.218.08:25:22.30#ibcon#wrote, iclass 38, count 2 2006.218.08:25:22.30#ibcon#about to read 3, iclass 38, count 2 2006.218.08:25:22.31#ibcon#read 3, iclass 38, count 2 2006.218.08:25:22.31#ibcon#about to read 4, iclass 38, count 2 2006.218.08:25:22.32#ibcon#read 4, iclass 38, count 2 2006.218.08:25:22.32#ibcon#about to read 5, iclass 38, count 2 2006.218.08:25:22.32#ibcon#read 5, iclass 38, count 2 2006.218.08:25:22.32#ibcon#about to read 6, iclass 38, count 2 2006.218.08:25:22.32#ibcon#read 6, iclass 38, count 2 2006.218.08:25:22.32#ibcon#end of sib2, iclass 38, count 2 2006.218.08:25:22.32#ibcon#*mode == 0, iclass 38, count 2 2006.218.08:25:22.32#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.218.08:25:22.32#ibcon#[27=AT06-04\r\n] 2006.218.08:25:22.32#ibcon#*before write, iclass 38, count 2 2006.218.08:25:22.32#ibcon#enter sib2, iclass 38, count 2 2006.218.08:25:22.32#ibcon#flushed, iclass 38, count 2 2006.218.08:25:22.32#ibcon#about to write, iclass 38, count 2 2006.218.08:25:22.32#ibcon#wrote, iclass 38, count 2 2006.218.08:25:22.32#ibcon#about to read 3, iclass 38, count 2 2006.218.08:25:22.34#ibcon#read 3, iclass 38, count 2 2006.218.08:25:22.34#ibcon#about to read 4, iclass 38, count 2 2006.218.08:25:22.35#ibcon#read 4, iclass 38, count 2 2006.218.08:25:22.35#ibcon#about to read 5, iclass 38, count 2 2006.218.08:25:22.35#ibcon#read 5, iclass 38, count 2 2006.218.08:25:22.35#ibcon#about to read 6, iclass 38, count 2 2006.218.08:25:22.35#ibcon#read 6, iclass 38, count 2 2006.218.08:25:22.35#ibcon#end of sib2, iclass 38, count 2 2006.218.08:25:22.35#ibcon#*after write, iclass 38, count 2 2006.218.08:25:22.35#ibcon#*before return 0, iclass 38, count 2 2006.218.08:25:22.35#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.218.08:25:22.35#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.218.08:25:22.35#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.218.08:25:22.35#ibcon#ireg 7 cls_cnt 0 2006.218.08:25:22.35#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.218.08:25:22.46#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.218.08:25:22.46#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.218.08:25:22.46#ibcon#enter wrdev, iclass 38, count 0 2006.218.08:25:22.46#ibcon#first serial, iclass 38, count 0 2006.218.08:25:22.46#ibcon#enter sib2, iclass 38, count 0 2006.218.08:25:22.46#ibcon#flushed, iclass 38, count 0 2006.218.08:25:22.46#ibcon#about to write, iclass 38, count 0 2006.218.08:25:22.47#ibcon#wrote, iclass 38, count 0 2006.218.08:25:22.47#ibcon#about to read 3, iclass 38, count 0 2006.218.08:25:22.48#ibcon#read 3, iclass 38, count 0 2006.218.08:25:22.48#ibcon#about to read 4, iclass 38, count 0 2006.218.08:25:22.48#ibcon#read 4, iclass 38, count 0 2006.218.08:25:22.48#ibcon#about to read 5, iclass 38, count 0 2006.218.08:25:22.48#ibcon#read 5, iclass 38, count 0 2006.218.08:25:22.49#ibcon#about to read 6, iclass 38, count 0 2006.218.08:25:22.49#ibcon#read 6, iclass 38, count 0 2006.218.08:25:22.49#ibcon#end of sib2, iclass 38, count 0 2006.218.08:25:22.49#ibcon#*mode == 0, iclass 38, count 0 2006.218.08:25:22.49#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.218.08:25:22.49#ibcon#[27=USB\r\n] 2006.218.08:25:22.49#ibcon#*before write, iclass 38, count 0 2006.218.08:25:22.49#ibcon#enter sib2, iclass 38, count 0 2006.218.08:25:22.49#ibcon#flushed, iclass 38, count 0 2006.218.08:25:22.49#ibcon#about to write, iclass 38, count 0 2006.218.08:25:22.49#ibcon#wrote, iclass 38, count 0 2006.218.08:25:22.49#ibcon#about to read 3, iclass 38, count 0 2006.218.08:25:22.51#ibcon#read 3, iclass 38, count 0 2006.218.08:25:22.51#ibcon#about to read 4, iclass 38, count 0 2006.218.08:25:22.51#ibcon#read 4, iclass 38, count 0 2006.218.08:25:22.51#ibcon#about to read 5, iclass 38, count 0 2006.218.08:25:22.51#ibcon#read 5, iclass 38, count 0 2006.218.08:25:22.52#ibcon#about to read 6, iclass 38, count 0 2006.218.08:25:22.52#ibcon#read 6, iclass 38, count 0 2006.218.08:25:22.52#ibcon#end of sib2, iclass 38, count 0 2006.218.08:25:22.52#ibcon#*after write, iclass 38, count 0 2006.218.08:25:22.52#ibcon#*before return 0, iclass 38, count 0 2006.218.08:25:22.52#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.218.08:25:22.52#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.218.08:25:22.52#ibcon#about to clear, iclass 38 cls_cnt 0 2006.218.08:25:22.52#ibcon#cleared, iclass 38 cls_cnt 0 2006.218.08:25:22.52$vc4f8/vabw=wide 2006.218.08:25:22.52#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.218.08:25:22.52#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.218.08:25:22.52#ibcon#ireg 8 cls_cnt 0 2006.218.08:25:22.52#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.218.08:25:22.52#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.218.08:25:22.52#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.218.08:25:22.52#ibcon#enter wrdev, iclass 40, count 0 2006.218.08:25:22.52#ibcon#first serial, iclass 40, count 0 2006.218.08:25:22.52#ibcon#enter sib2, iclass 40, count 0 2006.218.08:25:22.52#ibcon#flushed, iclass 40, count 0 2006.218.08:25:22.52#ibcon#about to write, iclass 40, count 0 2006.218.08:25:22.52#ibcon#wrote, iclass 40, count 0 2006.218.08:25:22.52#ibcon#about to read 3, iclass 40, count 0 2006.218.08:25:22.53#ibcon#read 3, iclass 40, count 0 2006.218.08:25:22.53#ibcon#about to read 4, iclass 40, count 0 2006.218.08:25:22.53#ibcon#read 4, iclass 40, count 0 2006.218.08:25:22.53#ibcon#about to read 5, iclass 40, count 0 2006.218.08:25:22.54#ibcon#read 5, iclass 40, count 0 2006.218.08:25:22.54#ibcon#about to read 6, iclass 40, count 0 2006.218.08:25:22.54#ibcon#read 6, iclass 40, count 0 2006.218.08:25:22.54#ibcon#end of sib2, iclass 40, count 0 2006.218.08:25:22.54#ibcon#*mode == 0, iclass 40, count 0 2006.218.08:25:22.54#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.218.08:25:22.54#ibcon#[25=BW32\r\n] 2006.218.08:25:22.54#ibcon#*before write, iclass 40, count 0 2006.218.08:25:22.54#ibcon#enter sib2, iclass 40, count 0 2006.218.08:25:22.54#ibcon#flushed, iclass 40, count 0 2006.218.08:25:22.54#ibcon#about to write, iclass 40, count 0 2006.218.08:25:22.54#ibcon#wrote, iclass 40, count 0 2006.218.08:25:22.54#ibcon#about to read 3, iclass 40, count 0 2006.218.08:25:22.56#ibcon#read 3, iclass 40, count 0 2006.218.08:25:22.56#ibcon#about to read 4, iclass 40, count 0 2006.218.08:25:22.56#ibcon#read 4, iclass 40, count 0 2006.218.08:25:22.56#ibcon#about to read 5, iclass 40, count 0 2006.218.08:25:22.56#ibcon#read 5, iclass 40, count 0 2006.218.08:25:22.57#ibcon#about to read 6, iclass 40, count 0 2006.218.08:25:22.57#ibcon#read 6, iclass 40, count 0 2006.218.08:25:22.57#ibcon#end of sib2, iclass 40, count 0 2006.218.08:25:22.57#ibcon#*after write, iclass 40, count 0 2006.218.08:25:22.57#ibcon#*before return 0, iclass 40, count 0 2006.218.08:25:22.57#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.218.08:25:22.57#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.218.08:25:22.57#ibcon#about to clear, iclass 40 cls_cnt 0 2006.218.08:25:22.57#ibcon#cleared, iclass 40 cls_cnt 0 2006.218.08:25:22.57$vc4f8/vbbw=wide 2006.218.08:25:22.57#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.218.08:25:22.57#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.218.08:25:22.57#ibcon#ireg 8 cls_cnt 0 2006.218.08:25:22.57#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.218.08:25:22.63#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.218.08:25:22.63#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.218.08:25:22.63#ibcon#enter wrdev, iclass 4, count 0 2006.218.08:25:22.63#ibcon#first serial, iclass 4, count 0 2006.218.08:25:22.63#ibcon#enter sib2, iclass 4, count 0 2006.218.08:25:22.63#ibcon#flushed, iclass 4, count 0 2006.218.08:25:22.64#ibcon#about to write, iclass 4, count 0 2006.218.08:25:22.64#ibcon#wrote, iclass 4, count 0 2006.218.08:25:22.64#ibcon#about to read 3, iclass 4, count 0 2006.218.08:25:22.65#ibcon#read 3, iclass 4, count 0 2006.218.08:25:22.65#ibcon#about to read 4, iclass 4, count 0 2006.218.08:25:22.65#ibcon#read 4, iclass 4, count 0 2006.218.08:25:22.65#ibcon#about to read 5, iclass 4, count 0 2006.218.08:25:22.65#ibcon#read 5, iclass 4, count 0 2006.218.08:25:22.66#ibcon#about to read 6, iclass 4, count 0 2006.218.08:25:22.66#ibcon#read 6, iclass 4, count 0 2006.218.08:25:22.66#ibcon#end of sib2, iclass 4, count 0 2006.218.08:25:22.66#ibcon#*mode == 0, iclass 4, count 0 2006.218.08:25:22.66#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.218.08:25:22.66#ibcon#[27=BW32\r\n] 2006.218.08:25:22.66#ibcon#*before write, iclass 4, count 0 2006.218.08:25:22.66#ibcon#enter sib2, iclass 4, count 0 2006.218.08:25:22.66#ibcon#flushed, iclass 4, count 0 2006.218.08:25:22.66#ibcon#about to write, iclass 4, count 0 2006.218.08:25:22.66#ibcon#wrote, iclass 4, count 0 2006.218.08:25:22.66#ibcon#about to read 3, iclass 4, count 0 2006.218.08:25:22.68#ibcon#read 3, iclass 4, count 0 2006.218.08:25:22.68#ibcon#about to read 4, iclass 4, count 0 2006.218.08:25:22.69#ibcon#read 4, iclass 4, count 0 2006.218.08:25:22.69#ibcon#about to read 5, iclass 4, count 0 2006.218.08:25:22.69#ibcon#read 5, iclass 4, count 0 2006.218.08:25:22.69#ibcon#about to read 6, iclass 4, count 0 2006.218.08:25:22.69#ibcon#read 6, iclass 4, count 0 2006.218.08:25:22.69#ibcon#end of sib2, iclass 4, count 0 2006.218.08:25:22.69#ibcon#*after write, iclass 4, count 0 2006.218.08:25:22.69#ibcon#*before return 0, iclass 4, count 0 2006.218.08:25:22.69#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.218.08:25:22.69#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.218.08:25:22.69#ibcon#about to clear, iclass 4 cls_cnt 0 2006.218.08:25:22.69#ibcon#cleared, iclass 4 cls_cnt 0 2006.218.08:25:22.69$4f8m12a/ifd4f 2006.218.08:25:22.69$ifd4f/lo= 2006.218.08:25:22.69$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.218.08:25:22.69$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.218.08:25:22.69$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.218.08:25:22.69$ifd4f/patch= 2006.218.08:25:22.69$ifd4f/patch=lo1,a1,a2,a3,a4 2006.218.08:25:22.69$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.218.08:25:22.69$ifd4f/patch=lo3,a5,a6,a7,a8 2006.218.08:25:22.69$4f8m12a/"form=m,16.000,1:2 2006.218.08:25:22.69$4f8m12a/"tpicd 2006.218.08:25:22.69$4f8m12a/echo=off 2006.218.08:25:22.69$4f8m12a/xlog=off 2006.218.08:25:22.69:!2006.218.08:26:30 2006.218.08:26:07.14#trakl#Source acquired 2006.218.08:26:08.15#flagr#flagr/antenna,acquired 2006.218.08:26:30.02:preob 2006.218.08:26:31.15/onsource/TRACKING 2006.218.08:26:31.15:!2006.218.08:26:40 2006.218.08:26:40.02:data_valid=on 2006.218.08:26:40.02:midob 2006.218.08:26:41.15/onsource/TRACKING 2006.218.08:26:41.15/wx/30.51,1007.6,76 2006.218.08:26:41.25/cable/+6.3870E-03 2006.218.08:26:42.34/va/01,05,usb,yes,32,34 2006.218.08:26:42.34/va/02,04,usb,yes,30,31 2006.218.08:26:42.34/va/03,04,usb,yes,28,28 2006.218.08:26:42.34/va/04,04,usb,yes,31,34 2006.218.08:26:42.34/va/05,07,usb,yes,33,35 2006.218.08:26:42.34/va/06,06,usb,yes,33,32 2006.218.08:26:42.34/va/07,06,usb,yes,33,33 2006.218.08:26:42.34/va/08,07,usb,yes,31,31 2006.218.08:26:42.57/valo/01,532.99,yes,locked 2006.218.08:26:42.57/valo/02,572.99,yes,locked 2006.218.08:26:42.57/valo/03,672.99,yes,locked 2006.218.08:26:42.57/valo/04,832.99,yes,locked 2006.218.08:26:42.57/valo/05,652.99,yes,locked 2006.218.08:26:42.57/valo/06,772.99,yes,locked 2006.218.08:26:42.57/valo/07,832.99,yes,locked 2006.218.08:26:42.57/valo/08,852.99,yes,locked 2006.218.08:26:43.66/vb/01,04,usb,yes,30,29 2006.218.08:26:43.66/vb/02,04,usb,yes,32,34 2006.218.08:26:43.66/vb/03,04,usb,yes,29,32 2006.218.08:26:43.66/vb/04,04,usb,yes,29,30 2006.218.08:26:43.66/vb/05,04,usb,yes,28,32 2006.218.08:26:43.66/vb/06,04,usb,yes,29,32 2006.218.08:26:43.66/vb/07,04,usb,yes,31,31 2006.218.08:26:43.66/vb/08,04,usb,yes,28,32 2006.218.08:26:43.89/vblo/01,632.99,yes,locked 2006.218.08:26:43.89/vblo/02,640.99,yes,locked 2006.218.08:26:43.89/vblo/03,656.99,yes,locked 2006.218.08:26:43.89/vblo/04,712.99,yes,locked 2006.218.08:26:43.89/vblo/05,744.99,yes,locked 2006.218.08:26:43.89/vblo/06,752.99,yes,locked 2006.218.08:26:43.89/vblo/07,734.99,yes,locked 2006.218.08:26:43.89/vblo/08,744.99,yes,locked 2006.218.08:26:44.04/vabw/8 2006.218.08:26:44.19/vbbw/8 2006.218.08:26:44.28/xfe/off,on,15.5 2006.218.08:26:44.67/ifatt/23,28,28,28 2006.218.08:26:45.07/fmout-gps/S +4.54E-07 2006.218.08:26:45.12:!2006.218.08:27:50 2006.218.08:27:50.02:data_valid=off 2006.218.08:27:50.02:postob 2006.218.08:27:50.18/cable/+6.3868E-03 2006.218.08:27:50.19/wx/30.47,1007.6,76 2006.218.08:27:51.07/fmout-gps/S +4.55E-07 2006.218.08:27:51.08:checkk5last 2006.218.08:27:51.08&checkk5last/chk_obsdata=1 2006.218.08:27:51.08&checkk5last/chk_obsdata=2 2006.218.08:27:51.08&checkk5last/chk_obsdata=3 2006.218.08:27:51.08&checkk5last/chk_obsdata=4 2006.218.08:27:51.08&checkk5last/k5log=1 2006.218.08:27:51.08&checkk5last/k5log=2 2006.218.08:27:51.08&checkk5last/k5log=3 2006.218.08:27:51.08&checkk5last/k5log=4 2006.218.08:27:51.08&checkk5last/obsinfo 2006.218.08:27:51.47/chk_obsdata//k5ts1/T2180826??a.dat file size is correct (nominal:560MB, actual:552MB). 2006.218.08:27:51.83/chk_obsdata//k5ts2/T2180826??b.dat file size is correct (nominal:560MB, actual:552MB). 2006.218.08:27:52.21/chk_obsdata//k5ts3/T2180826??c.dat file size is correct (nominal:560MB, actual:552MB). 2006.218.08:27:52.59/chk_obsdata//k5ts4/T2180826??d.dat file size is correct (nominal:560MB, actual:552MB). 2006.218.08:27:53.29/k5log//k5ts1_log_newline 2006.218.08:27:53.98/k5log//k5ts2_log_newline 2006.218.08:27:54.67/k5log//k5ts3_log_newline 2006.218.08:27:55.36/k5log//k5ts4_log_newline 2006.218.08:27:55.38/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.218.08:27:55.38:sched_end 2006.218.08:27:55.38&sched_end/stopcheck 2006.218.08:27:55.38&stopcheck/sy=killall check_fsrun.pl 2006.218.08:27:55.38&stopcheck/" sy=killall chmem.sh 2006.218.08:27:55.47:source=idle 2006.218.08:27:56.13#flagr#flagr/antenna,new-source 2006.218.08:27:56.14:stow 2006.218.08:27:56.14&stow/source=idle 2006.218.08:27:56.15&stow/"this is stow command. 2006.218.08:27:56.15&stow/antenna=m3 2006.218.08:28:00.02:!+10m 2006.218.08:38:00.03:standby 2006.218.08:38:00.03&standby/"this is standby command. 2006.218.08:38:00.04&standby/antenna=m0 2006.218.08:38:01.01:checkk5hdd 2006.218.08:38:01.02&checkk5hdd/chk_hdd=1 2006.218.08:38:01.02&checkk5hdd/chk_hdd=2 2006.218.08:38:01.02&checkk5hdd/chk_hdd=3 2006.218.08:38:01.03&checkk5hdd/chk_hdd=4 2006.218.08:38:03.84/chk_hdd//k5ts1/GSI00275:T218073000a.dat~T218082640a.dat[13233356800Byte] 2006.218.08:38:06.66/chk_hdd//k5ts2/GSI00163:T218073000b.dat~T218082640b.dat[13233356800Byte] 2006.218.08:38:09.48/chk_hdd//k5ts3/GSI00278:T218073000c.dat~T218082640c.dat[13233356800Byte] 2006.218.08:38:12.33/chk_hdd//k5ts4/GSI00294:T218073000d.dat~T218082640d.dat[13233356800Byte] 2006.218.08:38:12.33:sy=cp /usr2/log/k06218ts.log /usr2/log_backup/ 2006.218.08:38:12.42:*end of schedule 2006.218.12:37:48.29?ERROR st -97 Trouble decoding pressure data 2006.218.12:37:48.29#wxget#07 0.9 1.9 26.80 931009.5 2006.218.17:59:08.26?ERROR st -97 Trouble decoding pressure data 2006.218.17:59:08.26#wxget#05 0.8 1.1 24.361001008.6