2006.217.07:24:50.09:Log Opened: Mark IV Field System Version 9.7.7 2006.217.07:24:50.09:location,TSUKUB32,-140.09,36.10,61.0 2006.217.07:24:50.09:horizon1,0.,5.,360. 2006.217.07:24:50.10:antenna,32.0,180.0,180.0,10.0,710.0,5.0,88.0,azel 2006.217.07:24:50.10:equip,k42c/mk4,vlbab,vlbab,mk4,500.10,3,a/d,101,60,20,none,41,1,in,8bit,cdp,3 2006.217.07:24:50.10:drivev11,330,270,no 2006.217.07:24:50.11:drivev12,mvme117,0,11.400,2548.000,152.780,-6.655,0.014,152,10.000,54500 2006.217.07:24:50.11:drivev13,15.000,268,10.000,10.000,10.000 2006.217.07:24:50.11:drivev21,330,270,no 2006.217.07:24:50.12:drivev22,mvme117,0,11.500,2821.000,127.500,-8.640,0.015,152,14.000,54500 2006.217.07:24:50.12:drivev23,15.000,268,10.000,10.000,10.000 2006.217.07:24:50.12:head10,all,all,all,odd,adaptive,no,5.0000,1 2006.217.07:24:50.17:head11,131.5,16.4,-291.0,131.5,16.4,0.8,168.30,168.30 2006.217.07:24:50.17:head12,122.8,13.9,-150.8,122.8,14.7,2.5,167.61,167.61 2006.217.07:24:50.17:head20,all,all,all,odd,adaptive,no,5.0000,1 2006.217.07:24:50.18:head21,145.3,16.1,-209.3,137.2,16.1,58.9,165.28,165.28 2006.217.07:24:50.18:head22,157.5,17.4,-203.7,149.2,16.6,56.5,169.73,169.73 2006.217.07:24:50.18:time,-0.364,101.533,rate 2006.217.07:24:50.19:flagr,200 2006.217.07:24:50.19:proc=k06217ts 2006.217.07:24:50.19:" k06217 2006 tsukub32 t ts 2006.217.07:24:50.20:" t tsukub32 azel .0000 180.0 14 10.0 710.0 180.0 14 5.0 88.0 32.0 ts 108 2006.217.07:24:50.20:" ts tsukub32 -3957408.75120 3310229.34660 3737494.83600 73452301 2006.217.07:24:50.20:" 108 tsukub32 14 17400 2006.217.07:24:50.25:" drudg version 050216 compiled under fs 9.7.07 2006.217.07:24:50.25:" rack=k4-2/m4 recorder 1=k5 recorder 2=none 2006.217.07:24:50.26:sy=/usr2/oper/k5/bin/freeze_chk.pl & 2006.217.07:24:50.28:source=azel,0d,88d 2006.217.07:24:50.28#antcn#PM 1 00019 2005 228 00 22 31 00 2006.217.07:24:50.28#antcn#PM 2 90.0000 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 2006.217.07:24:50.28#antcn#PM 2 -0.0279715 0.0000000 -0.0282214 -0.0241630 -0.0014011 2006.217.07:24:50.28#antcn#PM 3 -0.0059899 0.0042895 -0.0643783 0.0000000 0.0000000 2006.217.07:24:50.28#antcn#PM 4 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.217.07:24:50.28#antcn#PM 5 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.217.07:24:51.13#flagr#flagr/antenna,new-source 2006.217.07:24:51.13:!+2m 2006.217.07:25:18.13#trakl#Source acquired 2006.217.07:25:19.13#flagr#flagr/antenna,acquired 2006.217.07:26:51.16:scan_name=217-0730,k06217,60 2006.217.07:26:51.16:source=3c418,203837.03,511912.7,2000.0,ccw 2006.217.07:26:53.14#flagr#flagr/antenna,new-source 2006.217.07:26:53.14:ready_k5 2006.217.07:26:53.15&ready_k5/obsinfo=st 2006.217.07:26:53.15&ready_k5/autoobs=1 2006.217.07:26:53.15&ready_k5/autoobs=2 2006.217.07:26:53.16&ready_k5/autoobs=3 2006.217.07:26:53.16&ready_k5/autoobs=4 2006.217.07:26:53.16&ready_k5/obsinfo 2006.217.07:26:53.17/obsinfo=st/error_log.tmp was not found (or not removed). 2006.217.07:26:56.38/autoobs//k5ts1/ autoobs started! 2006.217.07:26:59.50/autoobs//k5ts2/ autoobs started! 2006.217.07:27:02.62/autoobs//k5ts3/ autoobs started! 2006.217.07:27:05.73/autoobs//k5ts4/ autoobs started! 2006.217.07:27:05.77/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.217.07:27:05.77:4f8m12a=1 2006.217.07:27:05.77&4f8m12a/xlog=on 2006.217.07:27:05.77&4f8m12a/echo=on 2006.217.07:27:05.77&4f8m12a/pcalon 2006.217.07:27:05.77&4f8m12a/"tpicd=stop 2006.217.07:27:05.77&4f8m12a/vc4f8 2006.217.07:27:05.77&4f8m12a/ifd4f 2006.217.07:27:05.77&4f8m12a/"form=m,16.000,1:2 2006.217.07:27:05.77&4f8m12a/"tpicd 2006.217.07:27:05.77&4f8m12a/echo=off 2006.217.07:27:05.77&4f8m12a/xlog=off 2006.217.07:27:05.77$4f8m12a/echo=on 2006.217.07:27:05.77$4f8m12a/pcalon 2006.217.07:27:05.77&pcalon/"no phase cal control is implemented here 2006.217.07:27:05.77$pcalon/"no phase cal control is implemented here 2006.217.07:27:05.77$4f8m12a/"tpicd=stop 2006.217.07:27:05.77$4f8m12a/vc4f8 2006.217.07:27:05.77&vc4f8/valo=1,532.99 2006.217.07:27:05.77&vc4f8/va=1,5 2006.217.07:27:05.77&vc4f8/valo=2,572.99 2006.217.07:27:05.77&vc4f8/va=2,4 2006.217.07:27:05.77&vc4f8/valo=3,672.99 2006.217.07:27:05.77&vc4f8/va=3,4 2006.217.07:27:05.77&vc4f8/valo=4,832.99 2006.217.07:27:05.77&vc4f8/va=4,4 2006.217.07:27:05.77&vc4f8/valo=5,652.99 2006.217.07:27:05.77&vc4f8/va=5,7 2006.217.07:27:05.77&vc4f8/valo=6,772.99 2006.217.07:27:05.77&vc4f8/va=6,6 2006.217.07:27:05.77&vc4f8/valo=7,832.99 2006.217.07:27:05.77&vc4f8/va=7,6 2006.217.07:27:05.77&vc4f8/valo=8,852.99 2006.217.07:27:05.77&vc4f8/va=8,7 2006.217.07:27:05.77&vc4f8/vblo=1,632.99 2006.217.07:27:05.77&vc4f8/vb=1,4 2006.217.07:27:05.77&vc4f8/vblo=2,640.99 2006.217.07:27:05.77&vc4f8/vb=2,4 2006.217.07:27:05.77&vc4f8/vblo=3,656.99 2006.217.07:27:05.77&vc4f8/vb=3,4 2006.217.07:27:05.77&vc4f8/vblo=4,712.99 2006.217.07:27:05.77&vc4f8/vb=4,4 2006.217.07:27:05.77&vc4f8/vblo=5,744.99 2006.217.07:27:05.77&vc4f8/vb=5,4 2006.217.07:27:05.77&vc4f8/vblo=6,752.99 2006.217.07:27:05.77&vc4f8/vb=6,4 2006.217.07:27:05.77&vc4f8/vabw=wide 2006.217.07:27:05.77&vc4f8/vbbw=wide 2006.217.07:27:05.77$vc4f8/valo=1,532.99 2006.217.07:27:05.77#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.217.07:27:05.77#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.217.07:27:05.77#ibcon#ireg 17 cls_cnt 0 2006.217.07:27:05.77#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.217.07:27:05.77#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.217.07:27:05.77#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.217.07:27:05.77#ibcon#enter wrdev, iclass 25, count 0 2006.217.07:27:05.77#ibcon#first serial, iclass 25, count 0 2006.217.07:27:05.77#ibcon#enter sib2, iclass 25, count 0 2006.217.07:27:05.77#ibcon#flushed, iclass 25, count 0 2006.217.07:27:05.77#ibcon#about to write, iclass 25, count 0 2006.217.07:27:05.77#ibcon#wrote, iclass 25, count 0 2006.217.07:27:05.77#ibcon#about to read 3, iclass 25, count 0 2006.217.07:27:05.80#ibcon#read 3, iclass 25, count 0 2006.217.07:27:05.80#ibcon#about to read 4, iclass 25, count 0 2006.217.07:27:05.80#ibcon#read 4, iclass 25, count 0 2006.217.07:27:05.80#ibcon#about to read 5, iclass 25, count 0 2006.217.07:27:05.80#ibcon#read 5, iclass 25, count 0 2006.217.07:27:05.80#ibcon#about to read 6, iclass 25, count 0 2006.217.07:27:05.80#ibcon#read 6, iclass 25, count 0 2006.217.07:27:05.80#ibcon#end of sib2, iclass 25, count 0 2006.217.07:27:05.80#ibcon#*mode == 0, iclass 25, count 0 2006.217.07:27:05.80#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.217.07:27:05.80#ibcon#[26=FRQ=01,532.99\r\n] 2006.217.07:27:05.80#ibcon#*before write, iclass 25, count 0 2006.217.07:27:05.80#ibcon#enter sib2, iclass 25, count 0 2006.217.07:27:05.80#ibcon#flushed, iclass 25, count 0 2006.217.07:27:05.80#ibcon#about to write, iclass 25, count 0 2006.217.07:27:05.81#ibcon#wrote, iclass 25, count 0 2006.217.07:27:05.81#ibcon#about to read 3, iclass 25, count 0 2006.217.07:27:05.85#ibcon#read 3, iclass 25, count 0 2006.217.07:27:05.85#ibcon#about to read 4, iclass 25, count 0 2006.217.07:27:05.85#ibcon#read 4, iclass 25, count 0 2006.217.07:27:05.85#ibcon#about to read 5, iclass 25, count 0 2006.217.07:27:05.85#ibcon#read 5, iclass 25, count 0 2006.217.07:27:05.85#ibcon#about to read 6, iclass 25, count 0 2006.217.07:27:05.85#ibcon#read 6, iclass 25, count 0 2006.217.07:27:05.85#ibcon#end of sib2, iclass 25, count 0 2006.217.07:27:05.85#ibcon#*after write, iclass 25, count 0 2006.217.07:27:05.85#ibcon#*before return 0, iclass 25, count 0 2006.217.07:27:05.85#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.217.07:27:05.85#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.217.07:27:05.85#ibcon#about to clear, iclass 25 cls_cnt 0 2006.217.07:27:05.85#ibcon#cleared, iclass 25 cls_cnt 0 2006.217.07:27:05.85$vc4f8/va=1,5 2006.217.07:27:05.85#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.217.07:27:05.85#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.217.07:27:05.85#ibcon#ireg 11 cls_cnt 2 2006.217.07:27:05.85#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.217.07:27:05.85#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.217.07:27:05.85#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.217.07:27:05.85#ibcon#enter wrdev, iclass 27, count 2 2006.217.07:27:05.85#ibcon#first serial, iclass 27, count 2 2006.217.07:27:05.85#ibcon#enter sib2, iclass 27, count 2 2006.217.07:27:05.85#ibcon#flushed, iclass 27, count 2 2006.217.07:27:05.85#ibcon#about to write, iclass 27, count 2 2006.217.07:27:05.85#ibcon#wrote, iclass 27, count 2 2006.217.07:27:05.85#ibcon#about to read 3, iclass 27, count 2 2006.217.07:27:05.87#ibcon#read 3, iclass 27, count 2 2006.217.07:27:05.87#ibcon#about to read 4, iclass 27, count 2 2006.217.07:27:05.87#ibcon#read 4, iclass 27, count 2 2006.217.07:27:05.87#ibcon#about to read 5, iclass 27, count 2 2006.217.07:27:05.87#ibcon#read 5, iclass 27, count 2 2006.217.07:27:05.87#ibcon#about to read 6, iclass 27, count 2 2006.217.07:27:05.87#ibcon#read 6, iclass 27, count 2 2006.217.07:27:05.87#ibcon#end of sib2, iclass 27, count 2 2006.217.07:27:05.87#ibcon#*mode == 0, iclass 27, count 2 2006.217.07:27:05.87#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.217.07:27:05.87#ibcon#[25=AT01-05\r\n] 2006.217.07:27:05.87#ibcon#*before write, iclass 27, count 2 2006.217.07:27:05.87#ibcon#enter sib2, iclass 27, count 2 2006.217.07:27:05.87#ibcon#flushed, iclass 27, count 2 2006.217.07:27:05.87#ibcon#about to write, iclass 27, count 2 2006.217.07:27:05.87#ibcon#wrote, iclass 27, count 2 2006.217.07:27:05.87#ibcon#about to read 3, iclass 27, count 2 2006.217.07:27:05.90#ibcon#read 3, iclass 27, count 2 2006.217.07:27:05.90#ibcon#about to read 4, iclass 27, count 2 2006.217.07:27:05.90#ibcon#read 4, iclass 27, count 2 2006.217.07:27:05.90#ibcon#about to read 5, iclass 27, count 2 2006.217.07:27:05.90#ibcon#read 5, iclass 27, count 2 2006.217.07:27:05.90#ibcon#about to read 6, iclass 27, count 2 2006.217.07:27:05.90#ibcon#read 6, iclass 27, count 2 2006.217.07:27:05.90#ibcon#end of sib2, iclass 27, count 2 2006.217.07:27:05.90#ibcon#*after write, iclass 27, count 2 2006.217.07:27:05.90#ibcon#*before return 0, iclass 27, count 2 2006.217.07:27:05.90#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.217.07:27:05.90#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.217.07:27:05.90#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.217.07:27:05.90#ibcon#ireg 7 cls_cnt 0 2006.217.07:27:05.90#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.217.07:27:06.02#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.217.07:27:06.02#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.217.07:27:06.02#ibcon#enter wrdev, iclass 27, count 0 2006.217.07:27:06.02#ibcon#first serial, iclass 27, count 0 2006.217.07:27:06.02#ibcon#enter sib2, iclass 27, count 0 2006.217.07:27:06.02#ibcon#flushed, iclass 27, count 0 2006.217.07:27:06.02#ibcon#about to write, iclass 27, count 0 2006.217.07:27:06.02#ibcon#wrote, iclass 27, count 0 2006.217.07:27:06.02#ibcon#about to read 3, iclass 27, count 0 2006.217.07:27:06.04#ibcon#read 3, iclass 27, count 0 2006.217.07:27:06.04#ibcon#about to read 4, iclass 27, count 0 2006.217.07:27:06.04#ibcon#read 4, iclass 27, count 0 2006.217.07:27:06.04#ibcon#about to read 5, iclass 27, count 0 2006.217.07:27:06.04#ibcon#read 5, iclass 27, count 0 2006.217.07:27:06.04#ibcon#about to read 6, iclass 27, count 0 2006.217.07:27:06.04#ibcon#read 6, iclass 27, count 0 2006.217.07:27:06.04#ibcon#end of sib2, iclass 27, count 0 2006.217.07:27:06.04#ibcon#*mode == 0, iclass 27, count 0 2006.217.07:27:06.04#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.217.07:27:06.04#ibcon#[25=USB\r\n] 2006.217.07:27:06.04#ibcon#*before write, iclass 27, count 0 2006.217.07:27:06.04#ibcon#enter sib2, iclass 27, count 0 2006.217.07:27:06.04#ibcon#flushed, iclass 27, count 0 2006.217.07:27:06.04#ibcon#about to write, iclass 27, count 0 2006.217.07:27:06.04#ibcon#wrote, iclass 27, count 0 2006.217.07:27:06.04#ibcon#about to read 3, iclass 27, count 0 2006.217.07:27:06.07#ibcon#read 3, iclass 27, count 0 2006.217.07:27:06.07#ibcon#about to read 4, iclass 27, count 0 2006.217.07:27:06.07#ibcon#read 4, iclass 27, count 0 2006.217.07:27:06.07#ibcon#about to read 5, iclass 27, count 0 2006.217.07:27:06.07#ibcon#read 5, iclass 27, count 0 2006.217.07:27:06.07#ibcon#about to read 6, iclass 27, count 0 2006.217.07:27:06.07#ibcon#read 6, iclass 27, count 0 2006.217.07:27:06.07#ibcon#end of sib2, iclass 27, count 0 2006.217.07:27:06.07#ibcon#*after write, iclass 27, count 0 2006.217.07:27:06.07#ibcon#*before return 0, iclass 27, count 0 2006.217.07:27:06.07#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.217.07:27:06.07#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.217.07:27:06.07#ibcon#about to clear, iclass 27 cls_cnt 0 2006.217.07:27:06.07#ibcon#cleared, iclass 27 cls_cnt 0 2006.217.07:27:06.07$vc4f8/valo=2,572.99 2006.217.07:27:06.07#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.217.07:27:06.07#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.217.07:27:06.07#ibcon#ireg 17 cls_cnt 0 2006.217.07:27:06.07#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.217.07:27:06.07#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.217.07:27:06.07#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.217.07:27:06.07#ibcon#enter wrdev, iclass 29, count 0 2006.217.07:27:06.07#ibcon#first serial, iclass 29, count 0 2006.217.07:27:06.07#ibcon#enter sib2, iclass 29, count 0 2006.217.07:27:06.07#ibcon#flushed, iclass 29, count 0 2006.217.07:27:06.07#ibcon#about to write, iclass 29, count 0 2006.217.07:27:06.07#ibcon#wrote, iclass 29, count 0 2006.217.07:27:06.07#ibcon#about to read 3, iclass 29, count 0 2006.217.07:27:06.09#ibcon#read 3, iclass 29, count 0 2006.217.07:27:06.09#ibcon#about to read 4, iclass 29, count 0 2006.217.07:27:06.09#ibcon#read 4, iclass 29, count 0 2006.217.07:27:06.09#ibcon#about to read 5, iclass 29, count 0 2006.217.07:27:06.09#ibcon#read 5, iclass 29, count 0 2006.217.07:27:06.09#ibcon#about to read 6, iclass 29, count 0 2006.217.07:27:06.09#ibcon#read 6, iclass 29, count 0 2006.217.07:27:06.09#ibcon#end of sib2, iclass 29, count 0 2006.217.07:27:06.09#ibcon#*mode == 0, iclass 29, count 0 2006.217.07:27:06.09#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.217.07:27:06.09#ibcon#[26=FRQ=02,572.99\r\n] 2006.217.07:27:06.09#ibcon#*before write, iclass 29, count 0 2006.217.07:27:06.09#ibcon#enter sib2, iclass 29, count 0 2006.217.07:27:06.09#ibcon#flushed, iclass 29, count 0 2006.217.07:27:06.09#ibcon#about to write, iclass 29, count 0 2006.217.07:27:06.09#ibcon#wrote, iclass 29, count 0 2006.217.07:27:06.09#ibcon#about to read 3, iclass 29, count 0 2006.217.07:27:06.13#ibcon#read 3, iclass 29, count 0 2006.217.07:27:06.13#ibcon#about to read 4, iclass 29, count 0 2006.217.07:27:06.13#ibcon#read 4, iclass 29, count 0 2006.217.07:27:06.13#ibcon#about to read 5, iclass 29, count 0 2006.217.07:27:06.13#ibcon#read 5, iclass 29, count 0 2006.217.07:27:06.13#ibcon#about to read 6, iclass 29, count 0 2006.217.07:27:06.13#ibcon#read 6, iclass 29, count 0 2006.217.07:27:06.13#ibcon#end of sib2, iclass 29, count 0 2006.217.07:27:06.13#ibcon#*after write, iclass 29, count 0 2006.217.07:27:06.13#ibcon#*before return 0, iclass 29, count 0 2006.217.07:27:06.13#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.217.07:27:06.13#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.217.07:27:06.13#ibcon#about to clear, iclass 29 cls_cnt 0 2006.217.07:27:06.13#ibcon#cleared, iclass 29 cls_cnt 0 2006.217.07:27:06.13$vc4f8/va=2,4 2006.217.07:27:06.13#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.217.07:27:06.13#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.217.07:27:06.13#ibcon#ireg 11 cls_cnt 2 2006.217.07:27:06.13#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.217.07:27:06.19#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.217.07:27:06.19#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.217.07:27:06.19#ibcon#enter wrdev, iclass 31, count 2 2006.217.07:27:06.19#ibcon#first serial, iclass 31, count 2 2006.217.07:27:06.19#ibcon#enter sib2, iclass 31, count 2 2006.217.07:27:06.19#ibcon#flushed, iclass 31, count 2 2006.217.07:27:06.19#ibcon#about to write, iclass 31, count 2 2006.217.07:27:06.19#ibcon#wrote, iclass 31, count 2 2006.217.07:27:06.19#ibcon#about to read 3, iclass 31, count 2 2006.217.07:27:06.21#ibcon#read 3, iclass 31, count 2 2006.217.07:27:06.21#ibcon#about to read 4, iclass 31, count 2 2006.217.07:27:06.21#ibcon#read 4, iclass 31, count 2 2006.217.07:27:06.21#ibcon#about to read 5, iclass 31, count 2 2006.217.07:27:06.21#ibcon#read 5, iclass 31, count 2 2006.217.07:27:06.21#ibcon#about to read 6, iclass 31, count 2 2006.217.07:27:06.21#ibcon#read 6, iclass 31, count 2 2006.217.07:27:06.21#ibcon#end of sib2, iclass 31, count 2 2006.217.07:27:06.21#ibcon#*mode == 0, iclass 31, count 2 2006.217.07:27:06.21#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.217.07:27:06.21#ibcon#[25=AT02-04\r\n] 2006.217.07:27:06.21#ibcon#*before write, iclass 31, count 2 2006.217.07:27:06.21#ibcon#enter sib2, iclass 31, count 2 2006.217.07:27:06.21#ibcon#flushed, iclass 31, count 2 2006.217.07:27:06.21#ibcon#about to write, iclass 31, count 2 2006.217.07:27:06.21#ibcon#wrote, iclass 31, count 2 2006.217.07:27:06.21#ibcon#about to read 3, iclass 31, count 2 2006.217.07:27:06.24#ibcon#read 3, iclass 31, count 2 2006.217.07:27:06.24#ibcon#about to read 4, iclass 31, count 2 2006.217.07:27:06.24#ibcon#read 4, iclass 31, count 2 2006.217.07:27:06.24#ibcon#about to read 5, iclass 31, count 2 2006.217.07:27:06.24#ibcon#read 5, iclass 31, count 2 2006.217.07:27:06.24#ibcon#about to read 6, iclass 31, count 2 2006.217.07:27:06.24#ibcon#read 6, iclass 31, count 2 2006.217.07:27:06.24#ibcon#end of sib2, iclass 31, count 2 2006.217.07:27:06.24#ibcon#*after write, iclass 31, count 2 2006.217.07:27:06.24#ibcon#*before return 0, iclass 31, count 2 2006.217.07:27:06.24#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.217.07:27:06.24#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.217.07:27:06.24#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.217.07:27:06.24#ibcon#ireg 7 cls_cnt 0 2006.217.07:27:06.24#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.217.07:27:06.36#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.217.07:27:06.36#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.217.07:27:06.36#ibcon#enter wrdev, iclass 31, count 0 2006.217.07:27:06.36#ibcon#first serial, iclass 31, count 0 2006.217.07:27:06.36#ibcon#enter sib2, iclass 31, count 0 2006.217.07:27:06.36#ibcon#flushed, iclass 31, count 0 2006.217.07:27:06.36#ibcon#about to write, iclass 31, count 0 2006.217.07:27:06.36#ibcon#wrote, iclass 31, count 0 2006.217.07:27:06.36#ibcon#about to read 3, iclass 31, count 0 2006.217.07:27:06.38#ibcon#read 3, iclass 31, count 0 2006.217.07:27:06.38#ibcon#about to read 4, iclass 31, count 0 2006.217.07:27:06.38#ibcon#read 4, iclass 31, count 0 2006.217.07:27:06.38#ibcon#about to read 5, iclass 31, count 0 2006.217.07:27:06.38#ibcon#read 5, iclass 31, count 0 2006.217.07:27:06.38#ibcon#about to read 6, iclass 31, count 0 2006.217.07:27:06.38#ibcon#read 6, iclass 31, count 0 2006.217.07:27:06.38#ibcon#end of sib2, iclass 31, count 0 2006.217.07:27:06.38#ibcon#*mode == 0, iclass 31, count 0 2006.217.07:27:06.38#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.217.07:27:06.38#ibcon#[25=USB\r\n] 2006.217.07:27:06.38#ibcon#*before write, iclass 31, count 0 2006.217.07:27:06.38#ibcon#enter sib2, iclass 31, count 0 2006.217.07:27:06.38#ibcon#flushed, iclass 31, count 0 2006.217.07:27:06.38#ibcon#about to write, iclass 31, count 0 2006.217.07:27:06.38#ibcon#wrote, iclass 31, count 0 2006.217.07:27:06.38#ibcon#about to read 3, iclass 31, count 0 2006.217.07:27:06.41#ibcon#read 3, iclass 31, count 0 2006.217.07:27:06.41#ibcon#about to read 4, iclass 31, count 0 2006.217.07:27:06.41#ibcon#read 4, iclass 31, count 0 2006.217.07:27:06.41#ibcon#about to read 5, iclass 31, count 0 2006.217.07:27:06.41#ibcon#read 5, iclass 31, count 0 2006.217.07:27:06.41#ibcon#about to read 6, iclass 31, count 0 2006.217.07:27:06.41#ibcon#read 6, iclass 31, count 0 2006.217.07:27:06.41#ibcon#end of sib2, iclass 31, count 0 2006.217.07:27:06.41#ibcon#*after write, iclass 31, count 0 2006.217.07:27:06.41#ibcon#*before return 0, iclass 31, count 0 2006.217.07:27:06.41#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.217.07:27:06.41#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.217.07:27:06.41#ibcon#about to clear, iclass 31 cls_cnt 0 2006.217.07:27:06.41#ibcon#cleared, iclass 31 cls_cnt 0 2006.217.07:27:06.41$vc4f8/valo=3,672.99 2006.217.07:27:06.41#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.217.07:27:06.41#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.217.07:27:06.41#ibcon#ireg 17 cls_cnt 0 2006.217.07:27:06.41#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.217.07:27:06.41#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.217.07:27:06.41#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.217.07:27:06.41#ibcon#enter wrdev, iclass 33, count 0 2006.217.07:27:06.41#ibcon#first serial, iclass 33, count 0 2006.217.07:27:06.41#ibcon#enter sib2, iclass 33, count 0 2006.217.07:27:06.41#ibcon#flushed, iclass 33, count 0 2006.217.07:27:06.41#ibcon#about to write, iclass 33, count 0 2006.217.07:27:06.41#ibcon#wrote, iclass 33, count 0 2006.217.07:27:06.41#ibcon#about to read 3, iclass 33, count 0 2006.217.07:27:06.43#ibcon#read 3, iclass 33, count 0 2006.217.07:27:06.43#ibcon#about to read 4, iclass 33, count 0 2006.217.07:27:06.43#ibcon#read 4, iclass 33, count 0 2006.217.07:27:06.43#ibcon#about to read 5, iclass 33, count 0 2006.217.07:27:06.43#ibcon#read 5, iclass 33, count 0 2006.217.07:27:06.43#ibcon#about to read 6, iclass 33, count 0 2006.217.07:27:06.43#ibcon#read 6, iclass 33, count 0 2006.217.07:27:06.43#ibcon#end of sib2, iclass 33, count 0 2006.217.07:27:06.43#ibcon#*mode == 0, iclass 33, count 0 2006.217.07:27:06.43#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.217.07:27:06.43#ibcon#[26=FRQ=03,672.99\r\n] 2006.217.07:27:06.43#ibcon#*before write, iclass 33, count 0 2006.217.07:27:06.43#ibcon#enter sib2, iclass 33, count 0 2006.217.07:27:06.43#ibcon#flushed, iclass 33, count 0 2006.217.07:27:06.43#ibcon#about to write, iclass 33, count 0 2006.217.07:27:06.43#ibcon#wrote, iclass 33, count 0 2006.217.07:27:06.43#ibcon#about to read 3, iclass 33, count 0 2006.217.07:27:06.47#ibcon#read 3, iclass 33, count 0 2006.217.07:27:06.47#ibcon#about to read 4, iclass 33, count 0 2006.217.07:27:06.47#ibcon#read 4, iclass 33, count 0 2006.217.07:27:06.47#ibcon#about to read 5, iclass 33, count 0 2006.217.07:27:06.47#ibcon#read 5, iclass 33, count 0 2006.217.07:27:06.47#ibcon#about to read 6, iclass 33, count 0 2006.217.07:27:06.47#ibcon#read 6, iclass 33, count 0 2006.217.07:27:06.47#ibcon#end of sib2, iclass 33, count 0 2006.217.07:27:06.47#ibcon#*after write, iclass 33, count 0 2006.217.07:27:06.47#ibcon#*before return 0, iclass 33, count 0 2006.217.07:27:06.47#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.217.07:27:06.47#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.217.07:27:06.47#ibcon#about to clear, iclass 33 cls_cnt 0 2006.217.07:27:06.47#ibcon#cleared, iclass 33 cls_cnt 0 2006.217.07:27:06.47$vc4f8/va=3,4 2006.217.07:27:06.47#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.217.07:27:06.47#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.217.07:27:06.47#ibcon#ireg 11 cls_cnt 2 2006.217.07:27:06.47#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.217.07:27:06.53#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.217.07:27:06.53#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.217.07:27:06.53#ibcon#enter wrdev, iclass 35, count 2 2006.217.07:27:06.53#ibcon#first serial, iclass 35, count 2 2006.217.07:27:06.53#ibcon#enter sib2, iclass 35, count 2 2006.217.07:27:06.53#ibcon#flushed, iclass 35, count 2 2006.217.07:27:06.53#ibcon#about to write, iclass 35, count 2 2006.217.07:27:06.53#ibcon#wrote, iclass 35, count 2 2006.217.07:27:06.53#ibcon#about to read 3, iclass 35, count 2 2006.217.07:27:06.55#ibcon#read 3, iclass 35, count 2 2006.217.07:27:06.55#ibcon#about to read 4, iclass 35, count 2 2006.217.07:27:06.55#ibcon#read 4, iclass 35, count 2 2006.217.07:27:06.55#ibcon#about to read 5, iclass 35, count 2 2006.217.07:27:06.55#ibcon#read 5, iclass 35, count 2 2006.217.07:27:06.55#ibcon#about to read 6, iclass 35, count 2 2006.217.07:27:06.55#ibcon#read 6, iclass 35, count 2 2006.217.07:27:06.55#ibcon#end of sib2, iclass 35, count 2 2006.217.07:27:06.55#ibcon#*mode == 0, iclass 35, count 2 2006.217.07:27:06.55#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.217.07:27:06.55#ibcon#[25=AT03-04\r\n] 2006.217.07:27:06.55#ibcon#*before write, iclass 35, count 2 2006.217.07:27:06.55#ibcon#enter sib2, iclass 35, count 2 2006.217.07:27:06.55#ibcon#flushed, iclass 35, count 2 2006.217.07:27:06.55#ibcon#about to write, iclass 35, count 2 2006.217.07:27:06.55#ibcon#wrote, iclass 35, count 2 2006.217.07:27:06.55#ibcon#about to read 3, iclass 35, count 2 2006.217.07:27:06.58#ibcon#read 3, iclass 35, count 2 2006.217.07:27:06.58#ibcon#about to read 4, iclass 35, count 2 2006.217.07:27:06.58#ibcon#read 4, iclass 35, count 2 2006.217.07:27:06.58#ibcon#about to read 5, iclass 35, count 2 2006.217.07:27:06.58#ibcon#read 5, iclass 35, count 2 2006.217.07:27:06.58#ibcon#about to read 6, iclass 35, count 2 2006.217.07:27:06.58#ibcon#read 6, iclass 35, count 2 2006.217.07:27:06.58#ibcon#end of sib2, iclass 35, count 2 2006.217.07:27:06.58#ibcon#*after write, iclass 35, count 2 2006.217.07:27:06.58#ibcon#*before return 0, iclass 35, count 2 2006.217.07:27:06.58#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.217.07:27:06.58#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.217.07:27:06.58#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.217.07:27:06.58#ibcon#ireg 7 cls_cnt 0 2006.217.07:27:06.58#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.217.07:27:06.70#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.217.07:27:06.70#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.217.07:27:06.70#ibcon#enter wrdev, iclass 35, count 0 2006.217.07:27:06.70#ibcon#first serial, iclass 35, count 0 2006.217.07:27:06.70#ibcon#enter sib2, iclass 35, count 0 2006.217.07:27:06.70#ibcon#flushed, iclass 35, count 0 2006.217.07:27:06.70#ibcon#about to write, iclass 35, count 0 2006.217.07:27:06.70#ibcon#wrote, iclass 35, count 0 2006.217.07:27:06.70#ibcon#about to read 3, iclass 35, count 0 2006.217.07:27:06.72#ibcon#read 3, iclass 35, count 0 2006.217.07:27:06.72#ibcon#about to read 4, iclass 35, count 0 2006.217.07:27:06.72#ibcon#read 4, iclass 35, count 0 2006.217.07:27:06.72#ibcon#about to read 5, iclass 35, count 0 2006.217.07:27:06.72#ibcon#read 5, iclass 35, count 0 2006.217.07:27:06.72#ibcon#about to read 6, iclass 35, count 0 2006.217.07:27:06.72#ibcon#read 6, iclass 35, count 0 2006.217.07:27:06.72#ibcon#end of sib2, iclass 35, count 0 2006.217.07:27:06.72#ibcon#*mode == 0, iclass 35, count 0 2006.217.07:27:06.72#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.217.07:27:06.72#ibcon#[25=USB\r\n] 2006.217.07:27:06.72#ibcon#*before write, iclass 35, count 0 2006.217.07:27:06.72#ibcon#enter sib2, iclass 35, count 0 2006.217.07:27:06.72#ibcon#flushed, iclass 35, count 0 2006.217.07:27:06.72#ibcon#about to write, iclass 35, count 0 2006.217.07:27:06.72#ibcon#wrote, iclass 35, count 0 2006.217.07:27:06.72#ibcon#about to read 3, iclass 35, count 0 2006.217.07:27:06.75#ibcon#read 3, iclass 35, count 0 2006.217.07:27:06.75#ibcon#about to read 4, iclass 35, count 0 2006.217.07:27:06.75#ibcon#read 4, iclass 35, count 0 2006.217.07:27:06.75#ibcon#about to read 5, iclass 35, count 0 2006.217.07:27:06.75#ibcon#read 5, iclass 35, count 0 2006.217.07:27:06.75#ibcon#about to read 6, iclass 35, count 0 2006.217.07:27:06.75#ibcon#read 6, iclass 35, count 0 2006.217.07:27:06.75#ibcon#end of sib2, iclass 35, count 0 2006.217.07:27:06.75#ibcon#*after write, iclass 35, count 0 2006.217.07:27:06.75#ibcon#*before return 0, iclass 35, count 0 2006.217.07:27:06.75#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.217.07:27:06.75#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.217.07:27:06.75#ibcon#about to clear, iclass 35 cls_cnt 0 2006.217.07:27:06.75#ibcon#cleared, iclass 35 cls_cnt 0 2006.217.07:27:06.75$vc4f8/valo=4,832.99 2006.217.07:27:06.75#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.217.07:27:06.75#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.217.07:27:06.75#ibcon#ireg 17 cls_cnt 0 2006.217.07:27:06.75#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.217.07:27:06.75#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.217.07:27:06.75#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.217.07:27:06.75#ibcon#enter wrdev, iclass 37, count 0 2006.217.07:27:06.75#ibcon#first serial, iclass 37, count 0 2006.217.07:27:06.75#ibcon#enter sib2, iclass 37, count 0 2006.217.07:27:06.75#ibcon#flushed, iclass 37, count 0 2006.217.07:27:06.75#ibcon#about to write, iclass 37, count 0 2006.217.07:27:06.75#ibcon#wrote, iclass 37, count 0 2006.217.07:27:06.75#ibcon#about to read 3, iclass 37, count 0 2006.217.07:27:06.77#ibcon#read 3, iclass 37, count 0 2006.217.07:27:06.77#ibcon#about to read 4, iclass 37, count 0 2006.217.07:27:06.77#ibcon#read 4, iclass 37, count 0 2006.217.07:27:06.77#ibcon#about to read 5, iclass 37, count 0 2006.217.07:27:06.77#ibcon#read 5, iclass 37, count 0 2006.217.07:27:06.77#ibcon#about to read 6, iclass 37, count 0 2006.217.07:27:06.77#ibcon#read 6, iclass 37, count 0 2006.217.07:27:06.77#ibcon#end of sib2, iclass 37, count 0 2006.217.07:27:06.77#ibcon#*mode == 0, iclass 37, count 0 2006.217.07:27:06.77#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.217.07:27:06.77#ibcon#[26=FRQ=04,832.99\r\n] 2006.217.07:27:06.77#ibcon#*before write, iclass 37, count 0 2006.217.07:27:06.77#ibcon#enter sib2, iclass 37, count 0 2006.217.07:27:06.77#ibcon#flushed, iclass 37, count 0 2006.217.07:27:06.77#ibcon#about to write, iclass 37, count 0 2006.217.07:27:06.77#ibcon#wrote, iclass 37, count 0 2006.217.07:27:06.77#ibcon#about to read 3, iclass 37, count 0 2006.217.07:27:06.81#ibcon#read 3, iclass 37, count 0 2006.217.07:27:06.81#ibcon#about to read 4, iclass 37, count 0 2006.217.07:27:06.81#ibcon#read 4, iclass 37, count 0 2006.217.07:27:06.81#ibcon#about to read 5, iclass 37, count 0 2006.217.07:27:06.81#ibcon#read 5, iclass 37, count 0 2006.217.07:27:06.81#ibcon#about to read 6, iclass 37, count 0 2006.217.07:27:06.81#ibcon#read 6, iclass 37, count 0 2006.217.07:27:06.81#ibcon#end of sib2, iclass 37, count 0 2006.217.07:27:06.81#ibcon#*after write, iclass 37, count 0 2006.217.07:27:06.81#ibcon#*before return 0, iclass 37, count 0 2006.217.07:27:06.81#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.217.07:27:06.81#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.217.07:27:06.81#ibcon#about to clear, iclass 37 cls_cnt 0 2006.217.07:27:06.81#ibcon#cleared, iclass 37 cls_cnt 0 2006.217.07:27:06.81$vc4f8/va=4,4 2006.217.07:27:06.81#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.217.07:27:06.81#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.217.07:27:06.81#ibcon#ireg 11 cls_cnt 2 2006.217.07:27:06.81#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.217.07:27:06.87#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.217.07:27:06.87#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.217.07:27:06.87#ibcon#enter wrdev, iclass 39, count 2 2006.217.07:27:06.87#ibcon#first serial, iclass 39, count 2 2006.217.07:27:06.87#ibcon#enter sib2, iclass 39, count 2 2006.217.07:27:06.87#ibcon#flushed, iclass 39, count 2 2006.217.07:27:06.87#ibcon#about to write, iclass 39, count 2 2006.217.07:27:06.87#ibcon#wrote, iclass 39, count 2 2006.217.07:27:06.87#ibcon#about to read 3, iclass 39, count 2 2006.217.07:27:06.89#ibcon#read 3, iclass 39, count 2 2006.217.07:27:06.89#ibcon#about to read 4, iclass 39, count 2 2006.217.07:27:06.89#ibcon#read 4, iclass 39, count 2 2006.217.07:27:06.89#ibcon#about to read 5, iclass 39, count 2 2006.217.07:27:06.89#ibcon#read 5, iclass 39, count 2 2006.217.07:27:06.89#ibcon#about to read 6, iclass 39, count 2 2006.217.07:27:06.89#ibcon#read 6, iclass 39, count 2 2006.217.07:27:06.89#ibcon#end of sib2, iclass 39, count 2 2006.217.07:27:06.89#ibcon#*mode == 0, iclass 39, count 2 2006.217.07:27:06.89#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.217.07:27:06.89#ibcon#[25=AT04-04\r\n] 2006.217.07:27:06.89#ibcon#*before write, iclass 39, count 2 2006.217.07:27:06.89#ibcon#enter sib2, iclass 39, count 2 2006.217.07:27:06.89#ibcon#flushed, iclass 39, count 2 2006.217.07:27:06.89#ibcon#about to write, iclass 39, count 2 2006.217.07:27:06.89#ibcon#wrote, iclass 39, count 2 2006.217.07:27:06.89#ibcon#about to read 3, iclass 39, count 2 2006.217.07:27:06.92#ibcon#read 3, iclass 39, count 2 2006.217.07:27:06.92#ibcon#about to read 4, iclass 39, count 2 2006.217.07:27:06.92#ibcon#read 4, iclass 39, count 2 2006.217.07:27:06.92#ibcon#about to read 5, iclass 39, count 2 2006.217.07:27:06.92#ibcon#read 5, iclass 39, count 2 2006.217.07:27:06.92#ibcon#about to read 6, iclass 39, count 2 2006.217.07:27:06.92#ibcon#read 6, iclass 39, count 2 2006.217.07:27:06.92#ibcon#end of sib2, iclass 39, count 2 2006.217.07:27:06.92#ibcon#*after write, iclass 39, count 2 2006.217.07:27:06.92#ibcon#*before return 0, iclass 39, count 2 2006.217.07:27:06.92#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.217.07:27:06.92#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.217.07:27:06.92#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.217.07:27:06.92#ibcon#ireg 7 cls_cnt 0 2006.217.07:27:06.92#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.217.07:27:07.04#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.217.07:27:07.04#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.217.07:27:07.04#ibcon#enter wrdev, iclass 39, count 0 2006.217.07:27:07.04#ibcon#first serial, iclass 39, count 0 2006.217.07:27:07.04#ibcon#enter sib2, iclass 39, count 0 2006.217.07:27:07.04#ibcon#flushed, iclass 39, count 0 2006.217.07:27:07.04#ibcon#about to write, iclass 39, count 0 2006.217.07:27:07.04#ibcon#wrote, iclass 39, count 0 2006.217.07:27:07.04#ibcon#about to read 3, iclass 39, count 0 2006.217.07:27:07.06#ibcon#read 3, iclass 39, count 0 2006.217.07:27:07.06#ibcon#about to read 4, iclass 39, count 0 2006.217.07:27:07.06#ibcon#read 4, iclass 39, count 0 2006.217.07:27:07.06#ibcon#about to read 5, iclass 39, count 0 2006.217.07:27:07.06#ibcon#read 5, iclass 39, count 0 2006.217.07:27:07.06#ibcon#about to read 6, iclass 39, count 0 2006.217.07:27:07.06#ibcon#read 6, iclass 39, count 0 2006.217.07:27:07.06#ibcon#end of sib2, iclass 39, count 0 2006.217.07:27:07.06#ibcon#*mode == 0, iclass 39, count 0 2006.217.07:27:07.06#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.217.07:27:07.06#ibcon#[25=USB\r\n] 2006.217.07:27:07.06#ibcon#*before write, iclass 39, count 0 2006.217.07:27:07.06#ibcon#enter sib2, iclass 39, count 0 2006.217.07:27:07.06#ibcon#flushed, iclass 39, count 0 2006.217.07:27:07.06#ibcon#about to write, iclass 39, count 0 2006.217.07:27:07.06#ibcon#wrote, iclass 39, count 0 2006.217.07:27:07.06#ibcon#about to read 3, iclass 39, count 0 2006.217.07:27:07.09#ibcon#read 3, iclass 39, count 0 2006.217.07:27:07.09#ibcon#about to read 4, iclass 39, count 0 2006.217.07:27:07.09#ibcon#read 4, iclass 39, count 0 2006.217.07:27:07.09#ibcon#about to read 5, iclass 39, count 0 2006.217.07:27:07.09#ibcon#read 5, iclass 39, count 0 2006.217.07:27:07.09#ibcon#about to read 6, iclass 39, count 0 2006.217.07:27:07.09#ibcon#read 6, iclass 39, count 0 2006.217.07:27:07.09#ibcon#end of sib2, iclass 39, count 0 2006.217.07:27:07.09#ibcon#*after write, iclass 39, count 0 2006.217.07:27:07.09#ibcon#*before return 0, iclass 39, count 0 2006.217.07:27:07.09#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.217.07:27:07.09#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.217.07:27:07.09#ibcon#about to clear, iclass 39 cls_cnt 0 2006.217.07:27:07.09#ibcon#cleared, iclass 39 cls_cnt 0 2006.217.07:27:07.09$vc4f8/valo=5,652.99 2006.217.07:27:07.09#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.217.07:27:07.09#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.217.07:27:07.09#ibcon#ireg 17 cls_cnt 0 2006.217.07:27:07.09#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.217.07:27:07.09#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.217.07:27:07.09#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.217.07:27:07.09#ibcon#enter wrdev, iclass 3, count 0 2006.217.07:27:07.09#ibcon#first serial, iclass 3, count 0 2006.217.07:27:07.09#ibcon#enter sib2, iclass 3, count 0 2006.217.07:27:07.09#ibcon#flushed, iclass 3, count 0 2006.217.07:27:07.09#ibcon#about to write, iclass 3, count 0 2006.217.07:27:07.09#ibcon#wrote, iclass 3, count 0 2006.217.07:27:07.09#ibcon#about to read 3, iclass 3, count 0 2006.217.07:27:07.11#ibcon#read 3, iclass 3, count 0 2006.217.07:27:07.11#ibcon#about to read 4, iclass 3, count 0 2006.217.07:27:07.11#ibcon#read 4, iclass 3, count 0 2006.217.07:27:07.11#ibcon#about to read 5, iclass 3, count 0 2006.217.07:27:07.11#ibcon#read 5, iclass 3, count 0 2006.217.07:27:07.11#ibcon#about to read 6, iclass 3, count 0 2006.217.07:27:07.11#ibcon#read 6, iclass 3, count 0 2006.217.07:27:07.11#ibcon#end of sib2, iclass 3, count 0 2006.217.07:27:07.11#ibcon#*mode == 0, iclass 3, count 0 2006.217.07:27:07.11#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.217.07:27:07.11#ibcon#[26=FRQ=05,652.99\r\n] 2006.217.07:27:07.11#ibcon#*before write, iclass 3, count 0 2006.217.07:27:07.11#ibcon#enter sib2, iclass 3, count 0 2006.217.07:27:07.11#ibcon#flushed, iclass 3, count 0 2006.217.07:27:07.11#ibcon#about to write, iclass 3, count 0 2006.217.07:27:07.11#ibcon#wrote, iclass 3, count 0 2006.217.07:27:07.11#ibcon#about to read 3, iclass 3, count 0 2006.217.07:27:07.15#ibcon#read 3, iclass 3, count 0 2006.217.07:27:07.15#ibcon#about to read 4, iclass 3, count 0 2006.217.07:27:07.15#ibcon#read 4, iclass 3, count 0 2006.217.07:27:07.15#ibcon#about to read 5, iclass 3, count 0 2006.217.07:27:07.15#ibcon#read 5, iclass 3, count 0 2006.217.07:27:07.15#ibcon#about to read 6, iclass 3, count 0 2006.217.07:27:07.15#ibcon#read 6, iclass 3, count 0 2006.217.07:27:07.15#ibcon#end of sib2, iclass 3, count 0 2006.217.07:27:07.15#ibcon#*after write, iclass 3, count 0 2006.217.07:27:07.15#ibcon#*before return 0, iclass 3, count 0 2006.217.07:27:07.15#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.217.07:27:07.15#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.217.07:27:07.15#ibcon#about to clear, iclass 3 cls_cnt 0 2006.217.07:27:07.15#ibcon#cleared, iclass 3 cls_cnt 0 2006.217.07:27:07.15$vc4f8/va=5,7 2006.217.07:27:07.15#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.217.07:27:07.15#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.217.07:27:07.15#ibcon#ireg 11 cls_cnt 2 2006.217.07:27:07.15#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.217.07:27:07.21#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.217.07:27:07.21#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.217.07:27:07.21#ibcon#enter wrdev, iclass 5, count 2 2006.217.07:27:07.21#ibcon#first serial, iclass 5, count 2 2006.217.07:27:07.21#ibcon#enter sib2, iclass 5, count 2 2006.217.07:27:07.21#ibcon#flushed, iclass 5, count 2 2006.217.07:27:07.21#ibcon#about to write, iclass 5, count 2 2006.217.07:27:07.21#ibcon#wrote, iclass 5, count 2 2006.217.07:27:07.21#ibcon#about to read 3, iclass 5, count 2 2006.217.07:27:07.23#ibcon#read 3, iclass 5, count 2 2006.217.07:27:07.23#ibcon#about to read 4, iclass 5, count 2 2006.217.07:27:07.23#ibcon#read 4, iclass 5, count 2 2006.217.07:27:07.23#ibcon#about to read 5, iclass 5, count 2 2006.217.07:27:07.23#ibcon#read 5, iclass 5, count 2 2006.217.07:27:07.23#ibcon#about to read 6, iclass 5, count 2 2006.217.07:27:07.23#ibcon#read 6, iclass 5, count 2 2006.217.07:27:07.23#ibcon#end of sib2, iclass 5, count 2 2006.217.07:27:07.23#ibcon#*mode == 0, iclass 5, count 2 2006.217.07:27:07.23#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.217.07:27:07.23#ibcon#[25=AT05-07\r\n] 2006.217.07:27:07.23#ibcon#*before write, iclass 5, count 2 2006.217.07:27:07.23#ibcon#enter sib2, iclass 5, count 2 2006.217.07:27:07.23#ibcon#flushed, iclass 5, count 2 2006.217.07:27:07.23#ibcon#about to write, iclass 5, count 2 2006.217.07:27:07.23#ibcon#wrote, iclass 5, count 2 2006.217.07:27:07.23#ibcon#about to read 3, iclass 5, count 2 2006.217.07:27:07.26#ibcon#read 3, iclass 5, count 2 2006.217.07:27:07.26#ibcon#about to read 4, iclass 5, count 2 2006.217.07:27:07.26#ibcon#read 4, iclass 5, count 2 2006.217.07:27:07.26#ibcon#about to read 5, iclass 5, count 2 2006.217.07:27:07.26#ibcon#read 5, iclass 5, count 2 2006.217.07:27:07.26#ibcon#about to read 6, iclass 5, count 2 2006.217.07:27:07.26#ibcon#read 6, iclass 5, count 2 2006.217.07:27:07.26#ibcon#end of sib2, iclass 5, count 2 2006.217.07:27:07.26#ibcon#*after write, iclass 5, count 2 2006.217.07:27:07.26#ibcon#*before return 0, iclass 5, count 2 2006.217.07:27:07.26#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.217.07:27:07.26#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.217.07:27:07.26#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.217.07:27:07.26#ibcon#ireg 7 cls_cnt 0 2006.217.07:27:07.26#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.217.07:27:07.38#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.217.07:27:07.38#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.217.07:27:07.38#ibcon#enter wrdev, iclass 5, count 0 2006.217.07:27:07.38#ibcon#first serial, iclass 5, count 0 2006.217.07:27:07.38#ibcon#enter sib2, iclass 5, count 0 2006.217.07:27:07.38#ibcon#flushed, iclass 5, count 0 2006.217.07:27:07.38#ibcon#about to write, iclass 5, count 0 2006.217.07:27:07.38#ibcon#wrote, iclass 5, count 0 2006.217.07:27:07.38#ibcon#about to read 3, iclass 5, count 0 2006.217.07:27:07.40#ibcon#read 3, iclass 5, count 0 2006.217.07:27:07.40#ibcon#about to read 4, iclass 5, count 0 2006.217.07:27:07.40#ibcon#read 4, iclass 5, count 0 2006.217.07:27:07.40#ibcon#about to read 5, iclass 5, count 0 2006.217.07:27:07.40#ibcon#read 5, iclass 5, count 0 2006.217.07:27:07.40#ibcon#about to read 6, iclass 5, count 0 2006.217.07:27:07.40#ibcon#read 6, iclass 5, count 0 2006.217.07:27:07.40#ibcon#end of sib2, iclass 5, count 0 2006.217.07:27:07.40#ibcon#*mode == 0, iclass 5, count 0 2006.217.07:27:07.40#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.217.07:27:07.40#ibcon#[25=USB\r\n] 2006.217.07:27:07.40#ibcon#*before write, iclass 5, count 0 2006.217.07:27:07.40#ibcon#enter sib2, iclass 5, count 0 2006.217.07:27:07.40#ibcon#flushed, iclass 5, count 0 2006.217.07:27:07.40#ibcon#about to write, iclass 5, count 0 2006.217.07:27:07.40#ibcon#wrote, iclass 5, count 0 2006.217.07:27:07.40#ibcon#about to read 3, iclass 5, count 0 2006.217.07:27:07.43#ibcon#read 3, iclass 5, count 0 2006.217.07:27:07.43#ibcon#about to read 4, iclass 5, count 0 2006.217.07:27:07.43#ibcon#read 4, iclass 5, count 0 2006.217.07:27:07.43#ibcon#about to read 5, iclass 5, count 0 2006.217.07:27:07.43#ibcon#read 5, iclass 5, count 0 2006.217.07:27:07.43#ibcon#about to read 6, iclass 5, count 0 2006.217.07:27:07.43#ibcon#read 6, iclass 5, count 0 2006.217.07:27:07.43#ibcon#end of sib2, iclass 5, count 0 2006.217.07:27:07.43#ibcon#*after write, iclass 5, count 0 2006.217.07:27:07.43#ibcon#*before return 0, iclass 5, count 0 2006.217.07:27:07.43#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.217.07:27:07.43#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.217.07:27:07.43#ibcon#about to clear, iclass 5 cls_cnt 0 2006.217.07:27:07.43#ibcon#cleared, iclass 5 cls_cnt 0 2006.217.07:27:07.43$vc4f8/valo=6,772.99 2006.217.07:27:07.43#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.217.07:27:07.43#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.217.07:27:07.43#ibcon#ireg 17 cls_cnt 0 2006.217.07:27:07.43#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.217.07:27:07.43#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.217.07:27:07.43#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.217.07:27:07.43#ibcon#enter wrdev, iclass 7, count 0 2006.217.07:27:07.43#ibcon#first serial, iclass 7, count 0 2006.217.07:27:07.43#ibcon#enter sib2, iclass 7, count 0 2006.217.07:27:07.43#ibcon#flushed, iclass 7, count 0 2006.217.07:27:07.43#ibcon#about to write, iclass 7, count 0 2006.217.07:27:07.43#ibcon#wrote, iclass 7, count 0 2006.217.07:27:07.43#ibcon#about to read 3, iclass 7, count 0 2006.217.07:27:07.45#ibcon#read 3, iclass 7, count 0 2006.217.07:27:07.45#ibcon#about to read 4, iclass 7, count 0 2006.217.07:27:07.45#ibcon#read 4, iclass 7, count 0 2006.217.07:27:07.45#ibcon#about to read 5, iclass 7, count 0 2006.217.07:27:07.45#ibcon#read 5, iclass 7, count 0 2006.217.07:27:07.45#ibcon#about to read 6, iclass 7, count 0 2006.217.07:27:07.45#ibcon#read 6, iclass 7, count 0 2006.217.07:27:07.45#ibcon#end of sib2, iclass 7, count 0 2006.217.07:27:07.45#ibcon#*mode == 0, iclass 7, count 0 2006.217.07:27:07.45#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.217.07:27:07.45#ibcon#[26=FRQ=06,772.99\r\n] 2006.217.07:27:07.45#ibcon#*before write, iclass 7, count 0 2006.217.07:27:07.45#ibcon#enter sib2, iclass 7, count 0 2006.217.07:27:07.45#ibcon#flushed, iclass 7, count 0 2006.217.07:27:07.45#ibcon#about to write, iclass 7, count 0 2006.217.07:27:07.45#ibcon#wrote, iclass 7, count 0 2006.217.07:27:07.45#ibcon#about to read 3, iclass 7, count 0 2006.217.07:27:07.49#ibcon#read 3, iclass 7, count 0 2006.217.07:27:07.49#ibcon#about to read 4, iclass 7, count 0 2006.217.07:27:07.49#ibcon#read 4, iclass 7, count 0 2006.217.07:27:07.49#ibcon#about to read 5, iclass 7, count 0 2006.217.07:27:07.49#ibcon#read 5, iclass 7, count 0 2006.217.07:27:07.49#ibcon#about to read 6, iclass 7, count 0 2006.217.07:27:07.49#ibcon#read 6, iclass 7, count 0 2006.217.07:27:07.49#ibcon#end of sib2, iclass 7, count 0 2006.217.07:27:07.49#ibcon#*after write, iclass 7, count 0 2006.217.07:27:07.49#ibcon#*before return 0, iclass 7, count 0 2006.217.07:27:07.49#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.217.07:27:07.49#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.217.07:27:07.49#ibcon#about to clear, iclass 7 cls_cnt 0 2006.217.07:27:07.49#ibcon#cleared, iclass 7 cls_cnt 0 2006.217.07:27:07.49$vc4f8/va=6,6 2006.217.07:27:07.49#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.217.07:27:07.49#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.217.07:27:07.49#ibcon#ireg 11 cls_cnt 2 2006.217.07:27:07.49#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.217.07:27:07.55#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.217.07:27:07.55#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.217.07:27:07.55#ibcon#enter wrdev, iclass 11, count 2 2006.217.07:27:07.55#ibcon#first serial, iclass 11, count 2 2006.217.07:27:07.55#ibcon#enter sib2, iclass 11, count 2 2006.217.07:27:07.55#ibcon#flushed, iclass 11, count 2 2006.217.07:27:07.55#ibcon#about to write, iclass 11, count 2 2006.217.07:27:07.55#ibcon#wrote, iclass 11, count 2 2006.217.07:27:07.55#ibcon#about to read 3, iclass 11, count 2 2006.217.07:27:07.57#ibcon#read 3, iclass 11, count 2 2006.217.07:27:07.57#ibcon#about to read 4, iclass 11, count 2 2006.217.07:27:07.57#ibcon#read 4, iclass 11, count 2 2006.217.07:27:07.57#ibcon#about to read 5, iclass 11, count 2 2006.217.07:27:07.57#ibcon#read 5, iclass 11, count 2 2006.217.07:27:07.57#ibcon#about to read 6, iclass 11, count 2 2006.217.07:27:07.57#ibcon#read 6, iclass 11, count 2 2006.217.07:27:07.57#ibcon#end of sib2, iclass 11, count 2 2006.217.07:27:07.57#ibcon#*mode == 0, iclass 11, count 2 2006.217.07:27:07.57#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.217.07:27:07.57#ibcon#[25=AT06-06\r\n] 2006.217.07:27:07.57#ibcon#*before write, iclass 11, count 2 2006.217.07:27:07.57#ibcon#enter sib2, iclass 11, count 2 2006.217.07:27:07.57#ibcon#flushed, iclass 11, count 2 2006.217.07:27:07.57#ibcon#about to write, iclass 11, count 2 2006.217.07:27:07.57#ibcon#wrote, iclass 11, count 2 2006.217.07:27:07.57#ibcon#about to read 3, iclass 11, count 2 2006.217.07:27:07.60#ibcon#read 3, iclass 11, count 2 2006.217.07:27:07.60#ibcon#about to read 4, iclass 11, count 2 2006.217.07:27:07.60#ibcon#read 4, iclass 11, count 2 2006.217.07:27:07.60#ibcon#about to read 5, iclass 11, count 2 2006.217.07:27:07.60#ibcon#read 5, iclass 11, count 2 2006.217.07:27:07.60#ibcon#about to read 6, iclass 11, count 2 2006.217.07:27:07.60#ibcon#read 6, iclass 11, count 2 2006.217.07:27:07.60#ibcon#end of sib2, iclass 11, count 2 2006.217.07:27:07.60#ibcon#*after write, iclass 11, count 2 2006.217.07:27:07.60#ibcon#*before return 0, iclass 11, count 2 2006.217.07:27:07.60#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.217.07:27:07.60#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.217.07:27:07.60#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.217.07:27:07.60#ibcon#ireg 7 cls_cnt 0 2006.217.07:27:07.60#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.217.07:27:07.72#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.217.07:27:07.72#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.217.07:27:07.72#ibcon#enter wrdev, iclass 11, count 0 2006.217.07:27:07.72#ibcon#first serial, iclass 11, count 0 2006.217.07:27:07.72#ibcon#enter sib2, iclass 11, count 0 2006.217.07:27:07.72#ibcon#flushed, iclass 11, count 0 2006.217.07:27:07.72#ibcon#about to write, iclass 11, count 0 2006.217.07:27:07.72#ibcon#wrote, iclass 11, count 0 2006.217.07:27:07.72#ibcon#about to read 3, iclass 11, count 0 2006.217.07:27:07.74#ibcon#read 3, iclass 11, count 0 2006.217.07:27:07.74#ibcon#about to read 4, iclass 11, count 0 2006.217.07:27:07.74#ibcon#read 4, iclass 11, count 0 2006.217.07:27:07.74#ibcon#about to read 5, iclass 11, count 0 2006.217.07:27:07.74#ibcon#read 5, iclass 11, count 0 2006.217.07:27:07.74#ibcon#about to read 6, iclass 11, count 0 2006.217.07:27:07.74#ibcon#read 6, iclass 11, count 0 2006.217.07:27:07.74#ibcon#end of sib2, iclass 11, count 0 2006.217.07:27:07.74#ibcon#*mode == 0, iclass 11, count 0 2006.217.07:27:07.74#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.217.07:27:07.74#ibcon#[25=USB\r\n] 2006.217.07:27:07.74#ibcon#*before write, iclass 11, count 0 2006.217.07:27:07.74#ibcon#enter sib2, iclass 11, count 0 2006.217.07:27:07.74#ibcon#flushed, iclass 11, count 0 2006.217.07:27:07.74#ibcon#about to write, iclass 11, count 0 2006.217.07:27:07.74#ibcon#wrote, iclass 11, count 0 2006.217.07:27:07.74#ibcon#about to read 3, iclass 11, count 0 2006.217.07:27:07.77#ibcon#read 3, iclass 11, count 0 2006.217.07:27:07.77#ibcon#about to read 4, iclass 11, count 0 2006.217.07:27:07.77#ibcon#read 4, iclass 11, count 0 2006.217.07:27:07.77#ibcon#about to read 5, iclass 11, count 0 2006.217.07:27:07.77#ibcon#read 5, iclass 11, count 0 2006.217.07:27:07.77#ibcon#about to read 6, iclass 11, count 0 2006.217.07:27:07.77#ibcon#read 6, iclass 11, count 0 2006.217.07:27:07.77#ibcon#end of sib2, iclass 11, count 0 2006.217.07:27:07.77#ibcon#*after write, iclass 11, count 0 2006.217.07:27:07.77#ibcon#*before return 0, iclass 11, count 0 2006.217.07:27:07.77#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.217.07:27:07.77#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.217.07:27:07.77#ibcon#about to clear, iclass 11 cls_cnt 0 2006.217.07:27:07.77#ibcon#cleared, iclass 11 cls_cnt 0 2006.217.07:27:07.77$vc4f8/valo=7,832.99 2006.217.07:27:07.77#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.217.07:27:07.77#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.217.07:27:07.77#ibcon#ireg 17 cls_cnt 0 2006.217.07:27:07.77#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.217.07:27:07.77#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.217.07:27:07.77#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.217.07:27:07.77#ibcon#enter wrdev, iclass 13, count 0 2006.217.07:27:07.77#ibcon#first serial, iclass 13, count 0 2006.217.07:27:07.77#ibcon#enter sib2, iclass 13, count 0 2006.217.07:27:07.77#ibcon#flushed, iclass 13, count 0 2006.217.07:27:07.77#ibcon#about to write, iclass 13, count 0 2006.217.07:27:07.77#ibcon#wrote, iclass 13, count 0 2006.217.07:27:07.77#ibcon#about to read 3, iclass 13, count 0 2006.217.07:27:07.79#ibcon#read 3, iclass 13, count 0 2006.217.07:27:07.79#ibcon#about to read 4, iclass 13, count 0 2006.217.07:27:07.79#ibcon#read 4, iclass 13, count 0 2006.217.07:27:07.79#ibcon#about to read 5, iclass 13, count 0 2006.217.07:27:07.79#ibcon#read 5, iclass 13, count 0 2006.217.07:27:07.79#ibcon#about to read 6, iclass 13, count 0 2006.217.07:27:07.79#ibcon#read 6, iclass 13, count 0 2006.217.07:27:07.79#ibcon#end of sib2, iclass 13, count 0 2006.217.07:27:07.79#ibcon#*mode == 0, iclass 13, count 0 2006.217.07:27:07.79#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.217.07:27:07.79#ibcon#[26=FRQ=07,832.99\r\n] 2006.217.07:27:07.79#ibcon#*before write, iclass 13, count 0 2006.217.07:27:07.79#ibcon#enter sib2, iclass 13, count 0 2006.217.07:27:07.79#ibcon#flushed, iclass 13, count 0 2006.217.07:27:07.79#ibcon#about to write, iclass 13, count 0 2006.217.07:27:07.79#ibcon#wrote, iclass 13, count 0 2006.217.07:27:07.79#ibcon#about to read 3, iclass 13, count 0 2006.217.07:27:07.83#ibcon#read 3, iclass 13, count 0 2006.217.07:27:07.83#ibcon#about to read 4, iclass 13, count 0 2006.217.07:27:07.83#ibcon#read 4, iclass 13, count 0 2006.217.07:27:07.83#ibcon#about to read 5, iclass 13, count 0 2006.217.07:27:07.83#ibcon#read 5, iclass 13, count 0 2006.217.07:27:07.83#ibcon#about to read 6, iclass 13, count 0 2006.217.07:27:07.83#ibcon#read 6, iclass 13, count 0 2006.217.07:27:07.83#ibcon#end of sib2, iclass 13, count 0 2006.217.07:27:07.83#ibcon#*after write, iclass 13, count 0 2006.217.07:27:07.83#ibcon#*before return 0, iclass 13, count 0 2006.217.07:27:07.83#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.217.07:27:07.83#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.217.07:27:07.83#ibcon#about to clear, iclass 13 cls_cnt 0 2006.217.07:27:07.83#ibcon#cleared, iclass 13 cls_cnt 0 2006.217.07:27:07.83$vc4f8/va=7,6 2006.217.07:27:07.83#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.217.07:27:07.83#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.217.07:27:07.83#ibcon#ireg 11 cls_cnt 2 2006.217.07:27:07.83#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.217.07:27:07.89#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.217.07:27:07.89#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.217.07:27:07.89#ibcon#enter wrdev, iclass 15, count 2 2006.217.07:27:07.89#ibcon#first serial, iclass 15, count 2 2006.217.07:27:07.89#ibcon#enter sib2, iclass 15, count 2 2006.217.07:27:07.89#ibcon#flushed, iclass 15, count 2 2006.217.07:27:07.89#ibcon#about to write, iclass 15, count 2 2006.217.07:27:07.89#ibcon#wrote, iclass 15, count 2 2006.217.07:27:07.89#ibcon#about to read 3, iclass 15, count 2 2006.217.07:27:07.91#ibcon#read 3, iclass 15, count 2 2006.217.07:27:07.91#ibcon#about to read 4, iclass 15, count 2 2006.217.07:27:07.91#ibcon#read 4, iclass 15, count 2 2006.217.07:27:07.91#ibcon#about to read 5, iclass 15, count 2 2006.217.07:27:07.91#ibcon#read 5, iclass 15, count 2 2006.217.07:27:07.91#ibcon#about to read 6, iclass 15, count 2 2006.217.07:27:07.91#ibcon#read 6, iclass 15, count 2 2006.217.07:27:07.91#ibcon#end of sib2, iclass 15, count 2 2006.217.07:27:07.91#ibcon#*mode == 0, iclass 15, count 2 2006.217.07:27:07.91#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.217.07:27:07.91#ibcon#[25=AT07-06\r\n] 2006.217.07:27:07.91#ibcon#*before write, iclass 15, count 2 2006.217.07:27:07.91#ibcon#enter sib2, iclass 15, count 2 2006.217.07:27:07.91#ibcon#flushed, iclass 15, count 2 2006.217.07:27:07.91#ibcon#about to write, iclass 15, count 2 2006.217.07:27:07.91#ibcon#wrote, iclass 15, count 2 2006.217.07:27:07.91#ibcon#about to read 3, iclass 15, count 2 2006.217.07:27:07.94#ibcon#read 3, iclass 15, count 2 2006.217.07:27:07.94#ibcon#about to read 4, iclass 15, count 2 2006.217.07:27:07.94#ibcon#read 4, iclass 15, count 2 2006.217.07:27:07.94#ibcon#about to read 5, iclass 15, count 2 2006.217.07:27:07.94#ibcon#read 5, iclass 15, count 2 2006.217.07:27:07.94#ibcon#about to read 6, iclass 15, count 2 2006.217.07:27:07.94#ibcon#read 6, iclass 15, count 2 2006.217.07:27:07.94#ibcon#end of sib2, iclass 15, count 2 2006.217.07:27:07.94#ibcon#*after write, iclass 15, count 2 2006.217.07:27:07.94#ibcon#*before return 0, iclass 15, count 2 2006.217.07:27:07.94#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.217.07:27:07.94#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.217.07:27:07.94#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.217.07:27:07.94#ibcon#ireg 7 cls_cnt 0 2006.217.07:27:07.94#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.217.07:27:08.02#abcon#<5=/05 4.5 8.9 31.40 611008.5\r\n> 2006.217.07:27:08.04#abcon#{5=INTERFACE CLEAR} 2006.217.07:27:08.06#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.217.07:27:08.06#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.217.07:27:08.06#ibcon#enter wrdev, iclass 15, count 0 2006.217.07:27:08.06#ibcon#first serial, iclass 15, count 0 2006.217.07:27:08.06#ibcon#enter sib2, iclass 15, count 0 2006.217.07:27:08.06#ibcon#flushed, iclass 15, count 0 2006.217.07:27:08.06#ibcon#about to write, iclass 15, count 0 2006.217.07:27:08.06#ibcon#wrote, iclass 15, count 0 2006.217.07:27:08.06#ibcon#about to read 3, iclass 15, count 0 2006.217.07:27:08.08#ibcon#read 3, iclass 15, count 0 2006.217.07:27:08.08#ibcon#about to read 4, iclass 15, count 0 2006.217.07:27:08.08#ibcon#read 4, iclass 15, count 0 2006.217.07:27:08.08#ibcon#about to read 5, iclass 15, count 0 2006.217.07:27:08.08#ibcon#read 5, iclass 15, count 0 2006.217.07:27:08.08#ibcon#about to read 6, iclass 15, count 0 2006.217.07:27:08.08#ibcon#read 6, iclass 15, count 0 2006.217.07:27:08.08#ibcon#end of sib2, iclass 15, count 0 2006.217.07:27:08.08#ibcon#*mode == 0, iclass 15, count 0 2006.217.07:27:08.08#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.217.07:27:08.08#ibcon#[25=USB\r\n] 2006.217.07:27:08.08#ibcon#*before write, iclass 15, count 0 2006.217.07:27:08.08#ibcon#enter sib2, iclass 15, count 0 2006.217.07:27:08.08#ibcon#flushed, iclass 15, count 0 2006.217.07:27:08.08#ibcon#about to write, iclass 15, count 0 2006.217.07:27:08.08#ibcon#wrote, iclass 15, count 0 2006.217.07:27:08.08#ibcon#about to read 3, iclass 15, count 0 2006.217.07:27:08.10#abcon#[5=S1D000X0/0*\r\n] 2006.217.07:27:08.11#ibcon#read 3, iclass 15, count 0 2006.217.07:27:08.11#ibcon#about to read 4, iclass 15, count 0 2006.217.07:27:08.11#ibcon#read 4, iclass 15, count 0 2006.217.07:27:08.11#ibcon#about to read 5, iclass 15, count 0 2006.217.07:27:08.11#ibcon#read 5, iclass 15, count 0 2006.217.07:27:08.11#ibcon#about to read 6, iclass 15, count 0 2006.217.07:27:08.11#ibcon#read 6, iclass 15, count 0 2006.217.07:27:08.11#ibcon#end of sib2, iclass 15, count 0 2006.217.07:27:08.11#ibcon#*after write, iclass 15, count 0 2006.217.07:27:08.11#ibcon#*before return 0, iclass 15, count 0 2006.217.07:27:08.11#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.217.07:27:08.11#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.217.07:27:08.11#ibcon#about to clear, iclass 15 cls_cnt 0 2006.217.07:27:08.11#ibcon#cleared, iclass 15 cls_cnt 0 2006.217.07:27:08.11$vc4f8/valo=8,852.99 2006.217.07:27:08.11#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.217.07:27:08.11#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.217.07:27:08.11#ibcon#ireg 17 cls_cnt 0 2006.217.07:27:08.11#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.217.07:27:08.11#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.217.07:27:08.11#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.217.07:27:08.11#ibcon#enter wrdev, iclass 21, count 0 2006.217.07:27:08.11#ibcon#first serial, iclass 21, count 0 2006.217.07:27:08.11#ibcon#enter sib2, iclass 21, count 0 2006.217.07:27:08.11#ibcon#flushed, iclass 21, count 0 2006.217.07:27:08.11#ibcon#about to write, iclass 21, count 0 2006.217.07:27:08.11#ibcon#wrote, iclass 21, count 0 2006.217.07:27:08.11#ibcon#about to read 3, iclass 21, count 0 2006.217.07:27:08.13#ibcon#read 3, iclass 21, count 0 2006.217.07:27:08.13#ibcon#about to read 4, iclass 21, count 0 2006.217.07:27:08.13#ibcon#read 4, iclass 21, count 0 2006.217.07:27:08.13#ibcon#about to read 5, iclass 21, count 0 2006.217.07:27:08.13#ibcon#read 5, iclass 21, count 0 2006.217.07:27:08.13#ibcon#about to read 6, iclass 21, count 0 2006.217.07:27:08.13#ibcon#read 6, iclass 21, count 0 2006.217.07:27:08.13#ibcon#end of sib2, iclass 21, count 0 2006.217.07:27:08.13#ibcon#*mode == 0, iclass 21, count 0 2006.217.07:27:08.13#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.217.07:27:08.13#ibcon#[26=FRQ=08,852.99\r\n] 2006.217.07:27:08.13#ibcon#*before write, iclass 21, count 0 2006.217.07:27:08.13#ibcon#enter sib2, iclass 21, count 0 2006.217.07:27:08.13#ibcon#flushed, iclass 21, count 0 2006.217.07:27:08.13#ibcon#about to write, iclass 21, count 0 2006.217.07:27:08.13#ibcon#wrote, iclass 21, count 0 2006.217.07:27:08.13#ibcon#about to read 3, iclass 21, count 0 2006.217.07:27:08.17#ibcon#read 3, iclass 21, count 0 2006.217.07:27:08.17#ibcon#about to read 4, iclass 21, count 0 2006.217.07:27:08.17#ibcon#read 4, iclass 21, count 0 2006.217.07:27:08.17#ibcon#about to read 5, iclass 21, count 0 2006.217.07:27:08.17#ibcon#read 5, iclass 21, count 0 2006.217.07:27:08.17#ibcon#about to read 6, iclass 21, count 0 2006.217.07:27:08.17#ibcon#read 6, iclass 21, count 0 2006.217.07:27:08.17#ibcon#end of sib2, iclass 21, count 0 2006.217.07:27:08.17#ibcon#*after write, iclass 21, count 0 2006.217.07:27:08.17#ibcon#*before return 0, iclass 21, count 0 2006.217.07:27:08.17#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.217.07:27:08.17#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.217.07:27:08.17#ibcon#about to clear, iclass 21 cls_cnt 0 2006.217.07:27:08.17#ibcon#cleared, iclass 21 cls_cnt 0 2006.217.07:27:08.17$vc4f8/va=8,7 2006.217.07:27:08.17#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.217.07:27:08.17#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.217.07:27:08.17#ibcon#ireg 11 cls_cnt 2 2006.217.07:27:08.17#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.217.07:27:08.23#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.217.07:27:08.23#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.217.07:27:08.23#ibcon#enter wrdev, iclass 23, count 2 2006.217.07:27:08.23#ibcon#first serial, iclass 23, count 2 2006.217.07:27:08.23#ibcon#enter sib2, iclass 23, count 2 2006.217.07:27:08.23#ibcon#flushed, iclass 23, count 2 2006.217.07:27:08.23#ibcon#about to write, iclass 23, count 2 2006.217.07:27:08.23#ibcon#wrote, iclass 23, count 2 2006.217.07:27:08.23#ibcon#about to read 3, iclass 23, count 2 2006.217.07:27:08.25#ibcon#read 3, iclass 23, count 2 2006.217.07:27:08.25#ibcon#about to read 4, iclass 23, count 2 2006.217.07:27:08.25#ibcon#read 4, iclass 23, count 2 2006.217.07:27:08.25#ibcon#about to read 5, iclass 23, count 2 2006.217.07:27:08.25#ibcon#read 5, iclass 23, count 2 2006.217.07:27:08.25#ibcon#about to read 6, iclass 23, count 2 2006.217.07:27:08.25#ibcon#read 6, iclass 23, count 2 2006.217.07:27:08.25#ibcon#end of sib2, iclass 23, count 2 2006.217.07:27:08.25#ibcon#*mode == 0, iclass 23, count 2 2006.217.07:27:08.25#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.217.07:27:08.25#ibcon#[25=AT08-07\r\n] 2006.217.07:27:08.25#ibcon#*before write, iclass 23, count 2 2006.217.07:27:08.25#ibcon#enter sib2, iclass 23, count 2 2006.217.07:27:08.25#ibcon#flushed, iclass 23, count 2 2006.217.07:27:08.25#ibcon#about to write, iclass 23, count 2 2006.217.07:27:08.25#ibcon#wrote, iclass 23, count 2 2006.217.07:27:08.25#ibcon#about to read 3, iclass 23, count 2 2006.217.07:27:08.28#ibcon#read 3, iclass 23, count 2 2006.217.07:27:08.28#ibcon#about to read 4, iclass 23, count 2 2006.217.07:27:08.28#ibcon#read 4, iclass 23, count 2 2006.217.07:27:08.28#ibcon#about to read 5, iclass 23, count 2 2006.217.07:27:08.28#ibcon#read 5, iclass 23, count 2 2006.217.07:27:08.28#ibcon#about to read 6, iclass 23, count 2 2006.217.07:27:08.28#ibcon#read 6, iclass 23, count 2 2006.217.07:27:08.28#ibcon#end of sib2, iclass 23, count 2 2006.217.07:27:08.28#ibcon#*after write, iclass 23, count 2 2006.217.07:27:08.28#ibcon#*before return 0, iclass 23, count 2 2006.217.07:27:08.28#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.217.07:27:08.28#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.217.07:27:08.28#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.217.07:27:08.28#ibcon#ireg 7 cls_cnt 0 2006.217.07:27:08.28#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.217.07:27:08.40#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.217.07:27:08.40#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.217.07:27:08.40#ibcon#enter wrdev, iclass 23, count 0 2006.217.07:27:08.40#ibcon#first serial, iclass 23, count 0 2006.217.07:27:08.40#ibcon#enter sib2, iclass 23, count 0 2006.217.07:27:08.40#ibcon#flushed, iclass 23, count 0 2006.217.07:27:08.40#ibcon#about to write, iclass 23, count 0 2006.217.07:27:08.40#ibcon#wrote, iclass 23, count 0 2006.217.07:27:08.40#ibcon#about to read 3, iclass 23, count 0 2006.217.07:27:08.42#ibcon#read 3, iclass 23, count 0 2006.217.07:27:08.42#ibcon#about to read 4, iclass 23, count 0 2006.217.07:27:08.42#ibcon#read 4, iclass 23, count 0 2006.217.07:27:08.42#ibcon#about to read 5, iclass 23, count 0 2006.217.07:27:08.42#ibcon#read 5, iclass 23, count 0 2006.217.07:27:08.42#ibcon#about to read 6, iclass 23, count 0 2006.217.07:27:08.42#ibcon#read 6, iclass 23, count 0 2006.217.07:27:08.42#ibcon#end of sib2, iclass 23, count 0 2006.217.07:27:08.42#ibcon#*mode == 0, iclass 23, count 0 2006.217.07:27:08.42#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.217.07:27:08.42#ibcon#[25=USB\r\n] 2006.217.07:27:08.42#ibcon#*before write, iclass 23, count 0 2006.217.07:27:08.42#ibcon#enter sib2, iclass 23, count 0 2006.217.07:27:08.42#ibcon#flushed, iclass 23, count 0 2006.217.07:27:08.42#ibcon#about to write, iclass 23, count 0 2006.217.07:27:08.42#ibcon#wrote, iclass 23, count 0 2006.217.07:27:08.42#ibcon#about to read 3, iclass 23, count 0 2006.217.07:27:08.45#ibcon#read 3, iclass 23, count 0 2006.217.07:27:08.45#ibcon#about to read 4, iclass 23, count 0 2006.217.07:27:08.45#ibcon#read 4, iclass 23, count 0 2006.217.07:27:08.45#ibcon#about to read 5, iclass 23, count 0 2006.217.07:27:08.45#ibcon#read 5, iclass 23, count 0 2006.217.07:27:08.45#ibcon#about to read 6, iclass 23, count 0 2006.217.07:27:08.45#ibcon#read 6, iclass 23, count 0 2006.217.07:27:08.45#ibcon#end of sib2, iclass 23, count 0 2006.217.07:27:08.45#ibcon#*after write, iclass 23, count 0 2006.217.07:27:08.45#ibcon#*before return 0, iclass 23, count 0 2006.217.07:27:08.45#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.217.07:27:08.45#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.217.07:27:08.45#ibcon#about to clear, iclass 23 cls_cnt 0 2006.217.07:27:08.45#ibcon#cleared, iclass 23 cls_cnt 0 2006.217.07:27:08.45$vc4f8/vblo=1,632.99 2006.217.07:27:08.45#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.217.07:27:08.45#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.217.07:27:08.45#ibcon#ireg 17 cls_cnt 0 2006.217.07:27:08.45#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.217.07:27:08.45#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.217.07:27:08.45#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.217.07:27:08.45#ibcon#enter wrdev, iclass 25, count 0 2006.217.07:27:08.45#ibcon#first serial, iclass 25, count 0 2006.217.07:27:08.45#ibcon#enter sib2, iclass 25, count 0 2006.217.07:27:08.45#ibcon#flushed, iclass 25, count 0 2006.217.07:27:08.45#ibcon#about to write, iclass 25, count 0 2006.217.07:27:08.45#ibcon#wrote, iclass 25, count 0 2006.217.07:27:08.45#ibcon#about to read 3, iclass 25, count 0 2006.217.07:27:08.47#ibcon#read 3, iclass 25, count 0 2006.217.07:27:08.47#ibcon#about to read 4, iclass 25, count 0 2006.217.07:27:08.47#ibcon#read 4, iclass 25, count 0 2006.217.07:27:08.47#ibcon#about to read 5, iclass 25, count 0 2006.217.07:27:08.47#ibcon#read 5, iclass 25, count 0 2006.217.07:27:08.47#ibcon#about to read 6, iclass 25, count 0 2006.217.07:27:08.47#ibcon#read 6, iclass 25, count 0 2006.217.07:27:08.47#ibcon#end of sib2, iclass 25, count 0 2006.217.07:27:08.47#ibcon#*mode == 0, iclass 25, count 0 2006.217.07:27:08.47#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.217.07:27:08.47#ibcon#[28=FRQ=01,632.99\r\n] 2006.217.07:27:08.47#ibcon#*before write, iclass 25, count 0 2006.217.07:27:08.47#ibcon#enter sib2, iclass 25, count 0 2006.217.07:27:08.47#ibcon#flushed, iclass 25, count 0 2006.217.07:27:08.47#ibcon#about to write, iclass 25, count 0 2006.217.07:27:08.47#ibcon#wrote, iclass 25, count 0 2006.217.07:27:08.47#ibcon#about to read 3, iclass 25, count 0 2006.217.07:27:08.51#ibcon#read 3, iclass 25, count 0 2006.217.07:27:08.51#ibcon#about to read 4, iclass 25, count 0 2006.217.07:27:08.51#ibcon#read 4, iclass 25, count 0 2006.217.07:27:08.51#ibcon#about to read 5, iclass 25, count 0 2006.217.07:27:08.51#ibcon#read 5, iclass 25, count 0 2006.217.07:27:08.51#ibcon#about to read 6, iclass 25, count 0 2006.217.07:27:08.51#ibcon#read 6, iclass 25, count 0 2006.217.07:27:08.51#ibcon#end of sib2, iclass 25, count 0 2006.217.07:27:08.51#ibcon#*after write, iclass 25, count 0 2006.217.07:27:08.51#ibcon#*before return 0, iclass 25, count 0 2006.217.07:27:08.51#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.217.07:27:08.51#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.217.07:27:08.51#ibcon#about to clear, iclass 25 cls_cnt 0 2006.217.07:27:08.51#ibcon#cleared, iclass 25 cls_cnt 0 2006.217.07:27:08.51$vc4f8/vb=1,4 2006.217.07:27:08.51#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.217.07:27:08.51#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.217.07:27:08.51#ibcon#ireg 11 cls_cnt 2 2006.217.07:27:08.51#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.217.07:27:08.51#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.217.07:27:08.51#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.217.07:27:08.51#ibcon#enter wrdev, iclass 27, count 2 2006.217.07:27:08.51#ibcon#first serial, iclass 27, count 2 2006.217.07:27:08.51#ibcon#enter sib2, iclass 27, count 2 2006.217.07:27:08.51#ibcon#flushed, iclass 27, count 2 2006.217.07:27:08.51#ibcon#about to write, iclass 27, count 2 2006.217.07:27:08.51#ibcon#wrote, iclass 27, count 2 2006.217.07:27:08.51#ibcon#about to read 3, iclass 27, count 2 2006.217.07:27:08.53#ibcon#read 3, iclass 27, count 2 2006.217.07:27:08.53#ibcon#about to read 4, iclass 27, count 2 2006.217.07:27:08.53#ibcon#read 4, iclass 27, count 2 2006.217.07:27:08.53#ibcon#about to read 5, iclass 27, count 2 2006.217.07:27:08.53#ibcon#read 5, iclass 27, count 2 2006.217.07:27:08.53#ibcon#about to read 6, iclass 27, count 2 2006.217.07:27:08.53#ibcon#read 6, iclass 27, count 2 2006.217.07:27:08.53#ibcon#end of sib2, iclass 27, count 2 2006.217.07:27:08.53#ibcon#*mode == 0, iclass 27, count 2 2006.217.07:27:08.53#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.217.07:27:08.53#ibcon#[27=AT01-04\r\n] 2006.217.07:27:08.53#ibcon#*before write, iclass 27, count 2 2006.217.07:27:08.53#ibcon#enter sib2, iclass 27, count 2 2006.217.07:27:08.53#ibcon#flushed, iclass 27, count 2 2006.217.07:27:08.53#ibcon#about to write, iclass 27, count 2 2006.217.07:27:08.53#ibcon#wrote, iclass 27, count 2 2006.217.07:27:08.53#ibcon#about to read 3, iclass 27, count 2 2006.217.07:27:08.56#ibcon#read 3, iclass 27, count 2 2006.217.07:27:08.56#ibcon#about to read 4, iclass 27, count 2 2006.217.07:27:08.56#ibcon#read 4, iclass 27, count 2 2006.217.07:27:08.56#ibcon#about to read 5, iclass 27, count 2 2006.217.07:27:08.56#ibcon#read 5, iclass 27, count 2 2006.217.07:27:08.56#ibcon#about to read 6, iclass 27, count 2 2006.217.07:27:08.56#ibcon#read 6, iclass 27, count 2 2006.217.07:27:08.56#ibcon#end of sib2, iclass 27, count 2 2006.217.07:27:08.56#ibcon#*after write, iclass 27, count 2 2006.217.07:27:08.56#ibcon#*before return 0, iclass 27, count 2 2006.217.07:27:08.56#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.217.07:27:08.56#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.217.07:27:08.56#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.217.07:27:08.56#ibcon#ireg 7 cls_cnt 0 2006.217.07:27:08.56#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.217.07:27:08.68#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.217.07:27:08.68#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.217.07:27:08.68#ibcon#enter wrdev, iclass 27, count 0 2006.217.07:27:08.68#ibcon#first serial, iclass 27, count 0 2006.217.07:27:08.68#ibcon#enter sib2, iclass 27, count 0 2006.217.07:27:08.68#ibcon#flushed, iclass 27, count 0 2006.217.07:27:08.68#ibcon#about to write, iclass 27, count 0 2006.217.07:27:08.68#ibcon#wrote, iclass 27, count 0 2006.217.07:27:08.68#ibcon#about to read 3, iclass 27, count 0 2006.217.07:27:08.70#ibcon#read 3, iclass 27, count 0 2006.217.07:27:08.70#ibcon#about to read 4, iclass 27, count 0 2006.217.07:27:08.70#ibcon#read 4, iclass 27, count 0 2006.217.07:27:08.70#ibcon#about to read 5, iclass 27, count 0 2006.217.07:27:08.70#ibcon#read 5, iclass 27, count 0 2006.217.07:27:08.70#ibcon#about to read 6, iclass 27, count 0 2006.217.07:27:08.70#ibcon#read 6, iclass 27, count 0 2006.217.07:27:08.70#ibcon#end of sib2, iclass 27, count 0 2006.217.07:27:08.70#ibcon#*mode == 0, iclass 27, count 0 2006.217.07:27:08.70#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.217.07:27:08.70#ibcon#[27=USB\r\n] 2006.217.07:27:08.70#ibcon#*before write, iclass 27, count 0 2006.217.07:27:08.70#ibcon#enter sib2, iclass 27, count 0 2006.217.07:27:08.70#ibcon#flushed, iclass 27, count 0 2006.217.07:27:08.70#ibcon#about to write, iclass 27, count 0 2006.217.07:27:08.70#ibcon#wrote, iclass 27, count 0 2006.217.07:27:08.70#ibcon#about to read 3, iclass 27, count 0 2006.217.07:27:08.73#ibcon#read 3, iclass 27, count 0 2006.217.07:27:08.73#ibcon#about to read 4, iclass 27, count 0 2006.217.07:27:08.73#ibcon#read 4, iclass 27, count 0 2006.217.07:27:08.73#ibcon#about to read 5, iclass 27, count 0 2006.217.07:27:08.73#ibcon#read 5, iclass 27, count 0 2006.217.07:27:08.73#ibcon#about to read 6, iclass 27, count 0 2006.217.07:27:08.73#ibcon#read 6, iclass 27, count 0 2006.217.07:27:08.73#ibcon#end of sib2, iclass 27, count 0 2006.217.07:27:08.73#ibcon#*after write, iclass 27, count 0 2006.217.07:27:08.73#ibcon#*before return 0, iclass 27, count 0 2006.217.07:27:08.73#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.217.07:27:08.73#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.217.07:27:08.73#ibcon#about to clear, iclass 27 cls_cnt 0 2006.217.07:27:08.73#ibcon#cleared, iclass 27 cls_cnt 0 2006.217.07:27:08.73$vc4f8/vblo=2,640.99 2006.217.07:27:08.73#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.217.07:27:08.73#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.217.07:27:08.73#ibcon#ireg 17 cls_cnt 0 2006.217.07:27:08.73#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.217.07:27:08.73#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.217.07:27:08.73#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.217.07:27:08.73#ibcon#enter wrdev, iclass 29, count 0 2006.217.07:27:08.73#ibcon#first serial, iclass 29, count 0 2006.217.07:27:08.73#ibcon#enter sib2, iclass 29, count 0 2006.217.07:27:08.73#ibcon#flushed, iclass 29, count 0 2006.217.07:27:08.73#ibcon#about to write, iclass 29, count 0 2006.217.07:27:08.73#ibcon#wrote, iclass 29, count 0 2006.217.07:27:08.73#ibcon#about to read 3, iclass 29, count 0 2006.217.07:27:08.75#ibcon#read 3, iclass 29, count 0 2006.217.07:27:08.75#ibcon#about to read 4, iclass 29, count 0 2006.217.07:27:08.75#ibcon#read 4, iclass 29, count 0 2006.217.07:27:08.75#ibcon#about to read 5, iclass 29, count 0 2006.217.07:27:08.75#ibcon#read 5, iclass 29, count 0 2006.217.07:27:08.75#ibcon#about to read 6, iclass 29, count 0 2006.217.07:27:08.75#ibcon#read 6, iclass 29, count 0 2006.217.07:27:08.75#ibcon#end of sib2, iclass 29, count 0 2006.217.07:27:08.75#ibcon#*mode == 0, iclass 29, count 0 2006.217.07:27:08.75#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.217.07:27:08.75#ibcon#[28=FRQ=02,640.99\r\n] 2006.217.07:27:08.75#ibcon#*before write, iclass 29, count 0 2006.217.07:27:08.75#ibcon#enter sib2, iclass 29, count 0 2006.217.07:27:08.75#ibcon#flushed, iclass 29, count 0 2006.217.07:27:08.75#ibcon#about to write, iclass 29, count 0 2006.217.07:27:08.75#ibcon#wrote, iclass 29, count 0 2006.217.07:27:08.75#ibcon#about to read 3, iclass 29, count 0 2006.217.07:27:08.79#ibcon#read 3, iclass 29, count 0 2006.217.07:27:08.79#ibcon#about to read 4, iclass 29, count 0 2006.217.07:27:08.79#ibcon#read 4, iclass 29, count 0 2006.217.07:27:08.79#ibcon#about to read 5, iclass 29, count 0 2006.217.07:27:08.79#ibcon#read 5, iclass 29, count 0 2006.217.07:27:08.79#ibcon#about to read 6, iclass 29, count 0 2006.217.07:27:08.79#ibcon#read 6, iclass 29, count 0 2006.217.07:27:08.79#ibcon#end of sib2, iclass 29, count 0 2006.217.07:27:08.79#ibcon#*after write, iclass 29, count 0 2006.217.07:27:08.79#ibcon#*before return 0, iclass 29, count 0 2006.217.07:27:08.79#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.217.07:27:08.79#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.217.07:27:08.79#ibcon#about to clear, iclass 29 cls_cnt 0 2006.217.07:27:08.79#ibcon#cleared, iclass 29 cls_cnt 0 2006.217.07:27:08.79$vc4f8/vb=2,4 2006.217.07:27:08.79#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.217.07:27:08.79#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.217.07:27:08.79#ibcon#ireg 11 cls_cnt 2 2006.217.07:27:08.79#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.217.07:27:08.85#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.217.07:27:08.85#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.217.07:27:08.85#ibcon#enter wrdev, iclass 31, count 2 2006.217.07:27:08.85#ibcon#first serial, iclass 31, count 2 2006.217.07:27:08.85#ibcon#enter sib2, iclass 31, count 2 2006.217.07:27:08.85#ibcon#flushed, iclass 31, count 2 2006.217.07:27:08.85#ibcon#about to write, iclass 31, count 2 2006.217.07:27:08.85#ibcon#wrote, iclass 31, count 2 2006.217.07:27:08.85#ibcon#about to read 3, iclass 31, count 2 2006.217.07:27:08.87#ibcon#read 3, iclass 31, count 2 2006.217.07:27:08.87#ibcon#about to read 4, iclass 31, count 2 2006.217.07:27:08.87#ibcon#read 4, iclass 31, count 2 2006.217.07:27:08.87#ibcon#about to read 5, iclass 31, count 2 2006.217.07:27:08.87#ibcon#read 5, iclass 31, count 2 2006.217.07:27:08.87#ibcon#about to read 6, iclass 31, count 2 2006.217.07:27:08.87#ibcon#read 6, iclass 31, count 2 2006.217.07:27:08.87#ibcon#end of sib2, iclass 31, count 2 2006.217.07:27:08.87#ibcon#*mode == 0, iclass 31, count 2 2006.217.07:27:08.87#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.217.07:27:08.87#ibcon#[27=AT02-04\r\n] 2006.217.07:27:08.87#ibcon#*before write, iclass 31, count 2 2006.217.07:27:08.87#ibcon#enter sib2, iclass 31, count 2 2006.217.07:27:08.87#ibcon#flushed, iclass 31, count 2 2006.217.07:27:08.87#ibcon#about to write, iclass 31, count 2 2006.217.07:27:08.87#ibcon#wrote, iclass 31, count 2 2006.217.07:27:08.87#ibcon#about to read 3, iclass 31, count 2 2006.217.07:27:08.90#ibcon#read 3, iclass 31, count 2 2006.217.07:27:08.90#ibcon#about to read 4, iclass 31, count 2 2006.217.07:27:08.90#ibcon#read 4, iclass 31, count 2 2006.217.07:27:08.90#ibcon#about to read 5, iclass 31, count 2 2006.217.07:27:08.90#ibcon#read 5, iclass 31, count 2 2006.217.07:27:08.90#ibcon#about to read 6, iclass 31, count 2 2006.217.07:27:08.90#ibcon#read 6, iclass 31, count 2 2006.217.07:27:08.90#ibcon#end of sib2, iclass 31, count 2 2006.217.07:27:08.90#ibcon#*after write, iclass 31, count 2 2006.217.07:27:08.90#ibcon#*before return 0, iclass 31, count 2 2006.217.07:27:08.90#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.217.07:27:08.90#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.217.07:27:08.90#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.217.07:27:08.90#ibcon#ireg 7 cls_cnt 0 2006.217.07:27:08.90#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.217.07:27:09.02#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.217.07:27:09.02#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.217.07:27:09.02#ibcon#enter wrdev, iclass 31, count 0 2006.217.07:27:09.02#ibcon#first serial, iclass 31, count 0 2006.217.07:27:09.02#ibcon#enter sib2, iclass 31, count 0 2006.217.07:27:09.02#ibcon#flushed, iclass 31, count 0 2006.217.07:27:09.02#ibcon#about to write, iclass 31, count 0 2006.217.07:27:09.02#ibcon#wrote, iclass 31, count 0 2006.217.07:27:09.02#ibcon#about to read 3, iclass 31, count 0 2006.217.07:27:09.04#ibcon#read 3, iclass 31, count 0 2006.217.07:27:09.04#ibcon#about to read 4, iclass 31, count 0 2006.217.07:27:09.04#ibcon#read 4, iclass 31, count 0 2006.217.07:27:09.04#ibcon#about to read 5, iclass 31, count 0 2006.217.07:27:09.04#ibcon#read 5, iclass 31, count 0 2006.217.07:27:09.04#ibcon#about to read 6, iclass 31, count 0 2006.217.07:27:09.04#ibcon#read 6, iclass 31, count 0 2006.217.07:27:09.04#ibcon#end of sib2, iclass 31, count 0 2006.217.07:27:09.04#ibcon#*mode == 0, iclass 31, count 0 2006.217.07:27:09.04#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.217.07:27:09.04#ibcon#[27=USB\r\n] 2006.217.07:27:09.04#ibcon#*before write, iclass 31, count 0 2006.217.07:27:09.04#ibcon#enter sib2, iclass 31, count 0 2006.217.07:27:09.04#ibcon#flushed, iclass 31, count 0 2006.217.07:27:09.04#ibcon#about to write, iclass 31, count 0 2006.217.07:27:09.04#ibcon#wrote, iclass 31, count 0 2006.217.07:27:09.04#ibcon#about to read 3, iclass 31, count 0 2006.217.07:27:09.08#ibcon#read 3, iclass 31, count 0 2006.217.07:27:09.08#ibcon#about to read 4, iclass 31, count 0 2006.217.07:27:09.08#ibcon#read 4, iclass 31, count 0 2006.217.07:27:09.08#ibcon#about to read 5, iclass 31, count 0 2006.217.07:27:09.08#ibcon#read 5, iclass 31, count 0 2006.217.07:27:09.08#ibcon#about to read 6, iclass 31, count 0 2006.217.07:27:09.08#ibcon#read 6, iclass 31, count 0 2006.217.07:27:09.08#ibcon#end of sib2, iclass 31, count 0 2006.217.07:27:09.08#ibcon#*after write, iclass 31, count 0 2006.217.07:27:09.08#ibcon#*before return 0, iclass 31, count 0 2006.217.07:27:09.08#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.217.07:27:09.08#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.217.07:27:09.08#ibcon#about to clear, iclass 31 cls_cnt 0 2006.217.07:27:09.08#ibcon#cleared, iclass 31 cls_cnt 0 2006.217.07:27:09.08$vc4f8/vblo=3,656.99 2006.217.07:27:09.08#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.217.07:27:09.08#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.217.07:27:09.08#ibcon#ireg 17 cls_cnt 0 2006.217.07:27:09.08#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.217.07:27:09.08#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.217.07:27:09.08#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.217.07:27:09.08#ibcon#enter wrdev, iclass 33, count 0 2006.217.07:27:09.08#ibcon#first serial, iclass 33, count 0 2006.217.07:27:09.08#ibcon#enter sib2, iclass 33, count 0 2006.217.07:27:09.08#ibcon#flushed, iclass 33, count 0 2006.217.07:27:09.08#ibcon#about to write, iclass 33, count 0 2006.217.07:27:09.08#ibcon#wrote, iclass 33, count 0 2006.217.07:27:09.08#ibcon#about to read 3, iclass 33, count 0 2006.217.07:27:09.09#ibcon#read 3, iclass 33, count 0 2006.217.07:27:09.09#ibcon#about to read 4, iclass 33, count 0 2006.217.07:27:09.09#ibcon#read 4, iclass 33, count 0 2006.217.07:27:09.09#ibcon#about to read 5, iclass 33, count 0 2006.217.07:27:09.09#ibcon#read 5, iclass 33, count 0 2006.217.07:27:09.09#ibcon#about to read 6, iclass 33, count 0 2006.217.07:27:09.09#ibcon#read 6, iclass 33, count 0 2006.217.07:27:09.09#ibcon#end of sib2, iclass 33, count 0 2006.217.07:27:09.09#ibcon#*mode == 0, iclass 33, count 0 2006.217.07:27:09.09#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.217.07:27:09.09#ibcon#[28=FRQ=03,656.99\r\n] 2006.217.07:27:09.09#ibcon#*before write, iclass 33, count 0 2006.217.07:27:09.09#ibcon#enter sib2, iclass 33, count 0 2006.217.07:27:09.09#ibcon#flushed, iclass 33, count 0 2006.217.07:27:09.09#ibcon#about to write, iclass 33, count 0 2006.217.07:27:09.09#ibcon#wrote, iclass 33, count 0 2006.217.07:27:09.09#ibcon#about to read 3, iclass 33, count 0 2006.217.07:27:09.13#ibcon#read 3, iclass 33, count 0 2006.217.07:27:09.13#ibcon#about to read 4, iclass 33, count 0 2006.217.07:27:09.13#ibcon#read 4, iclass 33, count 0 2006.217.07:27:09.13#ibcon#about to read 5, iclass 33, count 0 2006.217.07:27:09.13#ibcon#read 5, iclass 33, count 0 2006.217.07:27:09.13#ibcon#about to read 6, iclass 33, count 0 2006.217.07:27:09.13#ibcon#read 6, iclass 33, count 0 2006.217.07:27:09.13#ibcon#end of sib2, iclass 33, count 0 2006.217.07:27:09.13#ibcon#*after write, iclass 33, count 0 2006.217.07:27:09.13#ibcon#*before return 0, iclass 33, count 0 2006.217.07:27:09.13#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.217.07:27:09.13#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.217.07:27:09.13#ibcon#about to clear, iclass 33 cls_cnt 0 2006.217.07:27:09.13#ibcon#cleared, iclass 33 cls_cnt 0 2006.217.07:27:09.13$vc4f8/vb=3,4 2006.217.07:27:09.13#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.217.07:27:09.13#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.217.07:27:09.13#ibcon#ireg 11 cls_cnt 2 2006.217.07:27:09.13#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.217.07:27:09.20#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.217.07:27:09.20#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.217.07:27:09.20#ibcon#enter wrdev, iclass 35, count 2 2006.217.07:27:09.20#ibcon#first serial, iclass 35, count 2 2006.217.07:27:09.20#ibcon#enter sib2, iclass 35, count 2 2006.217.07:27:09.20#ibcon#flushed, iclass 35, count 2 2006.217.07:27:09.20#ibcon#about to write, iclass 35, count 2 2006.217.07:27:09.20#ibcon#wrote, iclass 35, count 2 2006.217.07:27:09.20#ibcon#about to read 3, iclass 35, count 2 2006.217.07:27:09.22#ibcon#read 3, iclass 35, count 2 2006.217.07:27:09.22#ibcon#about to read 4, iclass 35, count 2 2006.217.07:27:09.22#ibcon#read 4, iclass 35, count 2 2006.217.07:27:09.22#ibcon#about to read 5, iclass 35, count 2 2006.217.07:27:09.22#ibcon#read 5, iclass 35, count 2 2006.217.07:27:09.22#ibcon#about to read 6, iclass 35, count 2 2006.217.07:27:09.22#ibcon#read 6, iclass 35, count 2 2006.217.07:27:09.22#ibcon#end of sib2, iclass 35, count 2 2006.217.07:27:09.22#ibcon#*mode == 0, iclass 35, count 2 2006.217.07:27:09.22#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.217.07:27:09.22#ibcon#[27=AT03-04\r\n] 2006.217.07:27:09.22#ibcon#*before write, iclass 35, count 2 2006.217.07:27:09.22#ibcon#enter sib2, iclass 35, count 2 2006.217.07:27:09.22#ibcon#flushed, iclass 35, count 2 2006.217.07:27:09.22#ibcon#about to write, iclass 35, count 2 2006.217.07:27:09.22#ibcon#wrote, iclass 35, count 2 2006.217.07:27:09.22#ibcon#about to read 3, iclass 35, count 2 2006.217.07:27:09.25#ibcon#read 3, iclass 35, count 2 2006.217.07:27:09.25#ibcon#about to read 4, iclass 35, count 2 2006.217.07:27:09.25#ibcon#read 4, iclass 35, count 2 2006.217.07:27:09.25#ibcon#about to read 5, iclass 35, count 2 2006.217.07:27:09.25#ibcon#read 5, iclass 35, count 2 2006.217.07:27:09.25#ibcon#about to read 6, iclass 35, count 2 2006.217.07:27:09.25#ibcon#read 6, iclass 35, count 2 2006.217.07:27:09.25#ibcon#end of sib2, iclass 35, count 2 2006.217.07:27:09.25#ibcon#*after write, iclass 35, count 2 2006.217.07:27:09.25#ibcon#*before return 0, iclass 35, count 2 2006.217.07:27:09.25#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.217.07:27:09.25#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.217.07:27:09.25#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.217.07:27:09.25#ibcon#ireg 7 cls_cnt 0 2006.217.07:27:09.25#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.217.07:27:09.37#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.217.07:27:09.37#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.217.07:27:09.37#ibcon#enter wrdev, iclass 35, count 0 2006.217.07:27:09.37#ibcon#first serial, iclass 35, count 0 2006.217.07:27:09.37#ibcon#enter sib2, iclass 35, count 0 2006.217.07:27:09.37#ibcon#flushed, iclass 35, count 0 2006.217.07:27:09.37#ibcon#about to write, iclass 35, count 0 2006.217.07:27:09.37#ibcon#wrote, iclass 35, count 0 2006.217.07:27:09.37#ibcon#about to read 3, iclass 35, count 0 2006.217.07:27:09.39#ibcon#read 3, iclass 35, count 0 2006.217.07:27:09.39#ibcon#about to read 4, iclass 35, count 0 2006.217.07:27:09.39#ibcon#read 4, iclass 35, count 0 2006.217.07:27:09.39#ibcon#about to read 5, iclass 35, count 0 2006.217.07:27:09.39#ibcon#read 5, iclass 35, count 0 2006.217.07:27:09.39#ibcon#about to read 6, iclass 35, count 0 2006.217.07:27:09.39#ibcon#read 6, iclass 35, count 0 2006.217.07:27:09.39#ibcon#end of sib2, iclass 35, count 0 2006.217.07:27:09.39#ibcon#*mode == 0, iclass 35, count 0 2006.217.07:27:09.39#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.217.07:27:09.39#ibcon#[27=USB\r\n] 2006.217.07:27:09.39#ibcon#*before write, iclass 35, count 0 2006.217.07:27:09.39#ibcon#enter sib2, iclass 35, count 0 2006.217.07:27:09.39#ibcon#flushed, iclass 35, count 0 2006.217.07:27:09.39#ibcon#about to write, iclass 35, count 0 2006.217.07:27:09.39#ibcon#wrote, iclass 35, count 0 2006.217.07:27:09.39#ibcon#about to read 3, iclass 35, count 0 2006.217.07:27:09.42#ibcon#read 3, iclass 35, count 0 2006.217.07:27:09.42#ibcon#about to read 4, iclass 35, count 0 2006.217.07:27:09.42#ibcon#read 4, iclass 35, count 0 2006.217.07:27:09.42#ibcon#about to read 5, iclass 35, count 0 2006.217.07:27:09.42#ibcon#read 5, iclass 35, count 0 2006.217.07:27:09.42#ibcon#about to read 6, iclass 35, count 0 2006.217.07:27:09.42#ibcon#read 6, iclass 35, count 0 2006.217.07:27:09.42#ibcon#end of sib2, iclass 35, count 0 2006.217.07:27:09.42#ibcon#*after write, iclass 35, count 0 2006.217.07:27:09.42#ibcon#*before return 0, iclass 35, count 0 2006.217.07:27:09.42#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.217.07:27:09.42#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.217.07:27:09.42#ibcon#about to clear, iclass 35 cls_cnt 0 2006.217.07:27:09.42#ibcon#cleared, iclass 35 cls_cnt 0 2006.217.07:27:09.42$vc4f8/vblo=4,712.99 2006.217.07:27:09.42#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.217.07:27:09.42#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.217.07:27:09.42#ibcon#ireg 17 cls_cnt 0 2006.217.07:27:09.42#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.217.07:27:09.42#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.217.07:27:09.42#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.217.07:27:09.42#ibcon#enter wrdev, iclass 37, count 0 2006.217.07:27:09.42#ibcon#first serial, iclass 37, count 0 2006.217.07:27:09.42#ibcon#enter sib2, iclass 37, count 0 2006.217.07:27:09.42#ibcon#flushed, iclass 37, count 0 2006.217.07:27:09.42#ibcon#about to write, iclass 37, count 0 2006.217.07:27:09.42#ibcon#wrote, iclass 37, count 0 2006.217.07:27:09.42#ibcon#about to read 3, iclass 37, count 0 2006.217.07:27:09.44#ibcon#read 3, iclass 37, count 0 2006.217.07:27:09.44#ibcon#about to read 4, iclass 37, count 0 2006.217.07:27:09.44#ibcon#read 4, iclass 37, count 0 2006.217.07:27:09.44#ibcon#about to read 5, iclass 37, count 0 2006.217.07:27:09.44#ibcon#read 5, iclass 37, count 0 2006.217.07:27:09.44#ibcon#about to read 6, iclass 37, count 0 2006.217.07:27:09.44#ibcon#read 6, iclass 37, count 0 2006.217.07:27:09.44#ibcon#end of sib2, iclass 37, count 0 2006.217.07:27:09.44#ibcon#*mode == 0, iclass 37, count 0 2006.217.07:27:09.44#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.217.07:27:09.44#ibcon#[28=FRQ=04,712.99\r\n] 2006.217.07:27:09.44#ibcon#*before write, iclass 37, count 0 2006.217.07:27:09.44#ibcon#enter sib2, iclass 37, count 0 2006.217.07:27:09.44#ibcon#flushed, iclass 37, count 0 2006.217.07:27:09.44#ibcon#about to write, iclass 37, count 0 2006.217.07:27:09.44#ibcon#wrote, iclass 37, count 0 2006.217.07:27:09.44#ibcon#about to read 3, iclass 37, count 0 2006.217.07:27:09.48#ibcon#read 3, iclass 37, count 0 2006.217.07:27:09.48#ibcon#about to read 4, iclass 37, count 0 2006.217.07:27:09.48#ibcon#read 4, iclass 37, count 0 2006.217.07:27:09.48#ibcon#about to read 5, iclass 37, count 0 2006.217.07:27:09.48#ibcon#read 5, iclass 37, count 0 2006.217.07:27:09.48#ibcon#about to read 6, iclass 37, count 0 2006.217.07:27:09.48#ibcon#read 6, iclass 37, count 0 2006.217.07:27:09.48#ibcon#end of sib2, iclass 37, count 0 2006.217.07:27:09.48#ibcon#*after write, iclass 37, count 0 2006.217.07:27:09.48#ibcon#*before return 0, iclass 37, count 0 2006.217.07:27:09.48#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.217.07:27:09.48#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.217.07:27:09.48#ibcon#about to clear, iclass 37 cls_cnt 0 2006.217.07:27:09.48#ibcon#cleared, iclass 37 cls_cnt 0 2006.217.07:27:09.48$vc4f8/vb=4,4 2006.217.07:27:09.48#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.217.07:27:09.48#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.217.07:27:09.48#ibcon#ireg 11 cls_cnt 2 2006.217.07:27:09.48#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.217.07:27:09.54#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.217.07:27:09.54#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.217.07:27:09.54#ibcon#enter wrdev, iclass 39, count 2 2006.217.07:27:09.54#ibcon#first serial, iclass 39, count 2 2006.217.07:27:09.54#ibcon#enter sib2, iclass 39, count 2 2006.217.07:27:09.54#ibcon#flushed, iclass 39, count 2 2006.217.07:27:09.54#ibcon#about to write, iclass 39, count 2 2006.217.07:27:09.54#ibcon#wrote, iclass 39, count 2 2006.217.07:27:09.54#ibcon#about to read 3, iclass 39, count 2 2006.217.07:27:09.56#ibcon#read 3, iclass 39, count 2 2006.217.07:27:09.56#ibcon#about to read 4, iclass 39, count 2 2006.217.07:27:09.56#ibcon#read 4, iclass 39, count 2 2006.217.07:27:09.56#ibcon#about to read 5, iclass 39, count 2 2006.217.07:27:09.56#ibcon#read 5, iclass 39, count 2 2006.217.07:27:09.56#ibcon#about to read 6, iclass 39, count 2 2006.217.07:27:09.56#ibcon#read 6, iclass 39, count 2 2006.217.07:27:09.56#ibcon#end of sib2, iclass 39, count 2 2006.217.07:27:09.56#ibcon#*mode == 0, iclass 39, count 2 2006.217.07:27:09.56#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.217.07:27:09.56#ibcon#[27=AT04-04\r\n] 2006.217.07:27:09.56#ibcon#*before write, iclass 39, count 2 2006.217.07:27:09.56#ibcon#enter sib2, iclass 39, count 2 2006.217.07:27:09.56#ibcon#flushed, iclass 39, count 2 2006.217.07:27:09.56#ibcon#about to write, iclass 39, count 2 2006.217.07:27:09.56#ibcon#wrote, iclass 39, count 2 2006.217.07:27:09.56#ibcon#about to read 3, iclass 39, count 2 2006.217.07:27:09.59#ibcon#read 3, iclass 39, count 2 2006.217.07:27:09.59#ibcon#about to read 4, iclass 39, count 2 2006.217.07:27:09.59#ibcon#read 4, iclass 39, count 2 2006.217.07:27:09.59#ibcon#about to read 5, iclass 39, count 2 2006.217.07:27:09.59#ibcon#read 5, iclass 39, count 2 2006.217.07:27:09.59#ibcon#about to read 6, iclass 39, count 2 2006.217.07:27:09.59#ibcon#read 6, iclass 39, count 2 2006.217.07:27:09.59#ibcon#end of sib2, iclass 39, count 2 2006.217.07:27:09.59#ibcon#*after write, iclass 39, count 2 2006.217.07:27:09.59#ibcon#*before return 0, iclass 39, count 2 2006.217.07:27:09.59#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.217.07:27:09.59#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.217.07:27:09.59#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.217.07:27:09.59#ibcon#ireg 7 cls_cnt 0 2006.217.07:27:09.59#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.217.07:27:09.71#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.217.07:27:09.71#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.217.07:27:09.71#ibcon#enter wrdev, iclass 39, count 0 2006.217.07:27:09.71#ibcon#first serial, iclass 39, count 0 2006.217.07:27:09.71#ibcon#enter sib2, iclass 39, count 0 2006.217.07:27:09.71#ibcon#flushed, iclass 39, count 0 2006.217.07:27:09.71#ibcon#about to write, iclass 39, count 0 2006.217.07:27:09.71#ibcon#wrote, iclass 39, count 0 2006.217.07:27:09.71#ibcon#about to read 3, iclass 39, count 0 2006.217.07:27:09.73#ibcon#read 3, iclass 39, count 0 2006.217.07:27:09.73#ibcon#about to read 4, iclass 39, count 0 2006.217.07:27:09.73#ibcon#read 4, iclass 39, count 0 2006.217.07:27:09.73#ibcon#about to read 5, iclass 39, count 0 2006.217.07:27:09.73#ibcon#read 5, iclass 39, count 0 2006.217.07:27:09.73#ibcon#about to read 6, iclass 39, count 0 2006.217.07:27:09.73#ibcon#read 6, iclass 39, count 0 2006.217.07:27:09.73#ibcon#end of sib2, iclass 39, count 0 2006.217.07:27:09.73#ibcon#*mode == 0, iclass 39, count 0 2006.217.07:27:09.73#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.217.07:27:09.73#ibcon#[27=USB\r\n] 2006.217.07:27:09.73#ibcon#*before write, iclass 39, count 0 2006.217.07:27:09.73#ibcon#enter sib2, iclass 39, count 0 2006.217.07:27:09.73#ibcon#flushed, iclass 39, count 0 2006.217.07:27:09.73#ibcon#about to write, iclass 39, count 0 2006.217.07:27:09.73#ibcon#wrote, iclass 39, count 0 2006.217.07:27:09.73#ibcon#about to read 3, iclass 39, count 0 2006.217.07:27:09.76#ibcon#read 3, iclass 39, count 0 2006.217.07:27:09.76#ibcon#about to read 4, iclass 39, count 0 2006.217.07:27:09.76#ibcon#read 4, iclass 39, count 0 2006.217.07:27:09.76#ibcon#about to read 5, iclass 39, count 0 2006.217.07:27:09.76#ibcon#read 5, iclass 39, count 0 2006.217.07:27:09.76#ibcon#about to read 6, iclass 39, count 0 2006.217.07:27:09.76#ibcon#read 6, iclass 39, count 0 2006.217.07:27:09.76#ibcon#end of sib2, iclass 39, count 0 2006.217.07:27:09.76#ibcon#*after write, iclass 39, count 0 2006.217.07:27:09.76#ibcon#*before return 0, iclass 39, count 0 2006.217.07:27:09.76#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.217.07:27:09.76#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.217.07:27:09.76#ibcon#about to clear, iclass 39 cls_cnt 0 2006.217.07:27:09.76#ibcon#cleared, iclass 39 cls_cnt 0 2006.217.07:27:09.76$vc4f8/vblo=5,744.99 2006.217.07:27:09.76#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.217.07:27:09.76#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.217.07:27:09.76#ibcon#ireg 17 cls_cnt 0 2006.217.07:27:09.76#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.217.07:27:09.76#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.217.07:27:09.76#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.217.07:27:09.76#ibcon#enter wrdev, iclass 3, count 0 2006.217.07:27:09.76#ibcon#first serial, iclass 3, count 0 2006.217.07:27:09.76#ibcon#enter sib2, iclass 3, count 0 2006.217.07:27:09.76#ibcon#flushed, iclass 3, count 0 2006.217.07:27:09.76#ibcon#about to write, iclass 3, count 0 2006.217.07:27:09.76#ibcon#wrote, iclass 3, count 0 2006.217.07:27:09.76#ibcon#about to read 3, iclass 3, count 0 2006.217.07:27:09.78#ibcon#read 3, iclass 3, count 0 2006.217.07:27:09.78#ibcon#about to read 4, iclass 3, count 0 2006.217.07:27:09.78#ibcon#read 4, iclass 3, count 0 2006.217.07:27:09.78#ibcon#about to read 5, iclass 3, count 0 2006.217.07:27:09.78#ibcon#read 5, iclass 3, count 0 2006.217.07:27:09.78#ibcon#about to read 6, iclass 3, count 0 2006.217.07:27:09.78#ibcon#read 6, iclass 3, count 0 2006.217.07:27:09.78#ibcon#end of sib2, iclass 3, count 0 2006.217.07:27:09.78#ibcon#*mode == 0, iclass 3, count 0 2006.217.07:27:09.78#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.217.07:27:09.78#ibcon#[28=FRQ=05,744.99\r\n] 2006.217.07:27:09.78#ibcon#*before write, iclass 3, count 0 2006.217.07:27:09.78#ibcon#enter sib2, iclass 3, count 0 2006.217.07:27:09.78#ibcon#flushed, iclass 3, count 0 2006.217.07:27:09.78#ibcon#about to write, iclass 3, count 0 2006.217.07:27:09.78#ibcon#wrote, iclass 3, count 0 2006.217.07:27:09.78#ibcon#about to read 3, iclass 3, count 0 2006.217.07:27:09.82#ibcon#read 3, iclass 3, count 0 2006.217.07:27:09.82#ibcon#about to read 4, iclass 3, count 0 2006.217.07:27:09.82#ibcon#read 4, iclass 3, count 0 2006.217.07:27:09.82#ibcon#about to read 5, iclass 3, count 0 2006.217.07:27:09.82#ibcon#read 5, iclass 3, count 0 2006.217.07:27:09.82#ibcon#about to read 6, iclass 3, count 0 2006.217.07:27:09.82#ibcon#read 6, iclass 3, count 0 2006.217.07:27:09.82#ibcon#end of sib2, iclass 3, count 0 2006.217.07:27:09.82#ibcon#*after write, iclass 3, count 0 2006.217.07:27:09.82#ibcon#*before return 0, iclass 3, count 0 2006.217.07:27:09.82#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.217.07:27:09.82#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.217.07:27:09.82#ibcon#about to clear, iclass 3 cls_cnt 0 2006.217.07:27:09.82#ibcon#cleared, iclass 3 cls_cnt 0 2006.217.07:27:09.82$vc4f8/vb=5,4 2006.217.07:27:09.82#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.217.07:27:09.82#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.217.07:27:09.82#ibcon#ireg 11 cls_cnt 2 2006.217.07:27:09.82#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.217.07:27:09.88#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.217.07:27:09.88#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.217.07:27:09.88#ibcon#enter wrdev, iclass 5, count 2 2006.217.07:27:09.88#ibcon#first serial, iclass 5, count 2 2006.217.07:27:09.88#ibcon#enter sib2, iclass 5, count 2 2006.217.07:27:09.88#ibcon#flushed, iclass 5, count 2 2006.217.07:27:09.88#ibcon#about to write, iclass 5, count 2 2006.217.07:27:09.88#ibcon#wrote, iclass 5, count 2 2006.217.07:27:09.88#ibcon#about to read 3, iclass 5, count 2 2006.217.07:27:09.90#ibcon#read 3, iclass 5, count 2 2006.217.07:27:09.90#ibcon#about to read 4, iclass 5, count 2 2006.217.07:27:09.90#ibcon#read 4, iclass 5, count 2 2006.217.07:27:09.90#ibcon#about to read 5, iclass 5, count 2 2006.217.07:27:09.90#ibcon#read 5, iclass 5, count 2 2006.217.07:27:09.90#ibcon#about to read 6, iclass 5, count 2 2006.217.07:27:09.90#ibcon#read 6, iclass 5, count 2 2006.217.07:27:09.90#ibcon#end of sib2, iclass 5, count 2 2006.217.07:27:09.90#ibcon#*mode == 0, iclass 5, count 2 2006.217.07:27:09.90#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.217.07:27:09.90#ibcon#[27=AT05-04\r\n] 2006.217.07:27:09.90#ibcon#*before write, iclass 5, count 2 2006.217.07:27:09.90#ibcon#enter sib2, iclass 5, count 2 2006.217.07:27:09.90#ibcon#flushed, iclass 5, count 2 2006.217.07:27:09.90#ibcon#about to write, iclass 5, count 2 2006.217.07:27:09.90#ibcon#wrote, iclass 5, count 2 2006.217.07:27:09.90#ibcon#about to read 3, iclass 5, count 2 2006.217.07:27:09.93#ibcon#read 3, iclass 5, count 2 2006.217.07:27:09.93#ibcon#about to read 4, iclass 5, count 2 2006.217.07:27:09.93#ibcon#read 4, iclass 5, count 2 2006.217.07:27:09.93#ibcon#about to read 5, iclass 5, count 2 2006.217.07:27:09.93#ibcon#read 5, iclass 5, count 2 2006.217.07:27:09.93#ibcon#about to read 6, iclass 5, count 2 2006.217.07:27:09.93#ibcon#read 6, iclass 5, count 2 2006.217.07:27:09.93#ibcon#end of sib2, iclass 5, count 2 2006.217.07:27:09.93#ibcon#*after write, iclass 5, count 2 2006.217.07:27:09.93#ibcon#*before return 0, iclass 5, count 2 2006.217.07:27:09.93#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.217.07:27:09.93#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.217.07:27:09.93#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.217.07:27:09.93#ibcon#ireg 7 cls_cnt 0 2006.217.07:27:09.93#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.217.07:27:10.05#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.217.07:27:10.05#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.217.07:27:10.05#ibcon#enter wrdev, iclass 5, count 0 2006.217.07:27:10.05#ibcon#first serial, iclass 5, count 0 2006.217.07:27:10.05#ibcon#enter sib2, iclass 5, count 0 2006.217.07:27:10.05#ibcon#flushed, iclass 5, count 0 2006.217.07:27:10.05#ibcon#about to write, iclass 5, count 0 2006.217.07:27:10.05#ibcon#wrote, iclass 5, count 0 2006.217.07:27:10.05#ibcon#about to read 3, iclass 5, count 0 2006.217.07:27:10.07#ibcon#read 3, iclass 5, count 0 2006.217.07:27:10.07#ibcon#about to read 4, iclass 5, count 0 2006.217.07:27:10.07#ibcon#read 4, iclass 5, count 0 2006.217.07:27:10.07#ibcon#about to read 5, iclass 5, count 0 2006.217.07:27:10.07#ibcon#read 5, iclass 5, count 0 2006.217.07:27:10.07#ibcon#about to read 6, iclass 5, count 0 2006.217.07:27:10.07#ibcon#read 6, iclass 5, count 0 2006.217.07:27:10.07#ibcon#end of sib2, iclass 5, count 0 2006.217.07:27:10.07#ibcon#*mode == 0, iclass 5, count 0 2006.217.07:27:10.07#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.217.07:27:10.07#ibcon#[27=USB\r\n] 2006.217.07:27:10.07#ibcon#*before write, iclass 5, count 0 2006.217.07:27:10.07#ibcon#enter sib2, iclass 5, count 0 2006.217.07:27:10.07#ibcon#flushed, iclass 5, count 0 2006.217.07:27:10.07#ibcon#about to write, iclass 5, count 0 2006.217.07:27:10.07#ibcon#wrote, iclass 5, count 0 2006.217.07:27:10.07#ibcon#about to read 3, iclass 5, count 0 2006.217.07:27:10.10#ibcon#read 3, iclass 5, count 0 2006.217.07:27:10.10#ibcon#about to read 4, iclass 5, count 0 2006.217.07:27:10.10#ibcon#read 4, iclass 5, count 0 2006.217.07:27:10.10#ibcon#about to read 5, iclass 5, count 0 2006.217.07:27:10.10#ibcon#read 5, iclass 5, count 0 2006.217.07:27:10.10#ibcon#about to read 6, iclass 5, count 0 2006.217.07:27:10.10#ibcon#read 6, iclass 5, count 0 2006.217.07:27:10.10#ibcon#end of sib2, iclass 5, count 0 2006.217.07:27:10.10#ibcon#*after write, iclass 5, count 0 2006.217.07:27:10.10#ibcon#*before return 0, iclass 5, count 0 2006.217.07:27:10.10#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.217.07:27:10.10#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.217.07:27:10.10#ibcon#about to clear, iclass 5 cls_cnt 0 2006.217.07:27:10.10#ibcon#cleared, iclass 5 cls_cnt 0 2006.217.07:27:10.10$vc4f8/vblo=6,752.99 2006.217.07:27:10.10#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.217.07:27:10.10#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.217.07:27:10.10#ibcon#ireg 17 cls_cnt 0 2006.217.07:27:10.10#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.217.07:27:10.10#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.217.07:27:10.10#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.217.07:27:10.10#ibcon#enter wrdev, iclass 7, count 0 2006.217.07:27:10.10#ibcon#first serial, iclass 7, count 0 2006.217.07:27:10.10#ibcon#enter sib2, iclass 7, count 0 2006.217.07:27:10.10#ibcon#flushed, iclass 7, count 0 2006.217.07:27:10.10#ibcon#about to write, iclass 7, count 0 2006.217.07:27:10.10#ibcon#wrote, iclass 7, count 0 2006.217.07:27:10.10#ibcon#about to read 3, iclass 7, count 0 2006.217.07:27:10.12#ibcon#read 3, iclass 7, count 0 2006.217.07:27:10.12#ibcon#about to read 4, iclass 7, count 0 2006.217.07:27:10.12#ibcon#read 4, iclass 7, count 0 2006.217.07:27:10.12#ibcon#about to read 5, iclass 7, count 0 2006.217.07:27:10.12#ibcon#read 5, iclass 7, count 0 2006.217.07:27:10.12#ibcon#about to read 6, iclass 7, count 0 2006.217.07:27:10.12#ibcon#read 6, iclass 7, count 0 2006.217.07:27:10.12#ibcon#end of sib2, iclass 7, count 0 2006.217.07:27:10.12#ibcon#*mode == 0, iclass 7, count 0 2006.217.07:27:10.12#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.217.07:27:10.12#ibcon#[28=FRQ=06,752.99\r\n] 2006.217.07:27:10.12#ibcon#*before write, iclass 7, count 0 2006.217.07:27:10.12#ibcon#enter sib2, iclass 7, count 0 2006.217.07:27:10.12#ibcon#flushed, iclass 7, count 0 2006.217.07:27:10.12#ibcon#about to write, iclass 7, count 0 2006.217.07:27:10.12#ibcon#wrote, iclass 7, count 0 2006.217.07:27:10.12#ibcon#about to read 3, iclass 7, count 0 2006.217.07:27:10.16#ibcon#read 3, iclass 7, count 0 2006.217.07:27:10.16#ibcon#about to read 4, iclass 7, count 0 2006.217.07:27:10.16#ibcon#read 4, iclass 7, count 0 2006.217.07:27:10.16#ibcon#about to read 5, iclass 7, count 0 2006.217.07:27:10.16#ibcon#read 5, iclass 7, count 0 2006.217.07:27:10.16#ibcon#about to read 6, iclass 7, count 0 2006.217.07:27:10.16#ibcon#read 6, iclass 7, count 0 2006.217.07:27:10.16#ibcon#end of sib2, iclass 7, count 0 2006.217.07:27:10.16#ibcon#*after write, iclass 7, count 0 2006.217.07:27:10.16#ibcon#*before return 0, iclass 7, count 0 2006.217.07:27:10.16#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.217.07:27:10.16#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.217.07:27:10.16#ibcon#about to clear, iclass 7 cls_cnt 0 2006.217.07:27:10.16#ibcon#cleared, iclass 7 cls_cnt 0 2006.217.07:27:10.16$vc4f8/vb=6,4 2006.217.07:27:10.16#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.217.07:27:10.16#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.217.07:27:10.16#ibcon#ireg 11 cls_cnt 2 2006.217.07:27:10.16#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.217.07:27:10.22#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.217.07:27:10.22#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.217.07:27:10.22#ibcon#enter wrdev, iclass 11, count 2 2006.217.07:27:10.22#ibcon#first serial, iclass 11, count 2 2006.217.07:27:10.22#ibcon#enter sib2, iclass 11, count 2 2006.217.07:27:10.22#ibcon#flushed, iclass 11, count 2 2006.217.07:27:10.22#ibcon#about to write, iclass 11, count 2 2006.217.07:27:10.22#ibcon#wrote, iclass 11, count 2 2006.217.07:27:10.22#ibcon#about to read 3, iclass 11, count 2 2006.217.07:27:10.24#ibcon#read 3, iclass 11, count 2 2006.217.07:27:10.24#ibcon#about to read 4, iclass 11, count 2 2006.217.07:27:10.24#ibcon#read 4, iclass 11, count 2 2006.217.07:27:10.24#ibcon#about to read 5, iclass 11, count 2 2006.217.07:27:10.24#ibcon#read 5, iclass 11, count 2 2006.217.07:27:10.24#ibcon#about to read 6, iclass 11, count 2 2006.217.07:27:10.24#ibcon#read 6, iclass 11, count 2 2006.217.07:27:10.24#ibcon#end of sib2, iclass 11, count 2 2006.217.07:27:10.24#ibcon#*mode == 0, iclass 11, count 2 2006.217.07:27:10.24#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.217.07:27:10.24#ibcon#[27=AT06-04\r\n] 2006.217.07:27:10.24#ibcon#*before write, iclass 11, count 2 2006.217.07:27:10.24#ibcon#enter sib2, iclass 11, count 2 2006.217.07:27:10.24#ibcon#flushed, iclass 11, count 2 2006.217.07:27:10.24#ibcon#about to write, iclass 11, count 2 2006.217.07:27:10.24#ibcon#wrote, iclass 11, count 2 2006.217.07:27:10.24#ibcon#about to read 3, iclass 11, count 2 2006.217.07:27:10.27#ibcon#read 3, iclass 11, count 2 2006.217.07:27:10.27#ibcon#about to read 4, iclass 11, count 2 2006.217.07:27:10.27#ibcon#read 4, iclass 11, count 2 2006.217.07:27:10.27#ibcon#about to read 5, iclass 11, count 2 2006.217.07:27:10.27#ibcon#read 5, iclass 11, count 2 2006.217.07:27:10.27#ibcon#about to read 6, iclass 11, count 2 2006.217.07:27:10.27#ibcon#read 6, iclass 11, count 2 2006.217.07:27:10.27#ibcon#end of sib2, iclass 11, count 2 2006.217.07:27:10.27#ibcon#*after write, iclass 11, count 2 2006.217.07:27:10.27#ibcon#*before return 0, iclass 11, count 2 2006.217.07:27:10.27#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.217.07:27:10.27#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.217.07:27:10.27#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.217.07:27:10.27#ibcon#ireg 7 cls_cnt 0 2006.217.07:27:10.27#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.217.07:27:10.39#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.217.07:27:10.39#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.217.07:27:10.39#ibcon#enter wrdev, iclass 11, count 0 2006.217.07:27:10.39#ibcon#first serial, iclass 11, count 0 2006.217.07:27:10.39#ibcon#enter sib2, iclass 11, count 0 2006.217.07:27:10.39#ibcon#flushed, iclass 11, count 0 2006.217.07:27:10.39#ibcon#about to write, iclass 11, count 0 2006.217.07:27:10.39#ibcon#wrote, iclass 11, count 0 2006.217.07:27:10.39#ibcon#about to read 3, iclass 11, count 0 2006.217.07:27:10.41#ibcon#read 3, iclass 11, count 0 2006.217.07:27:10.41#ibcon#about to read 4, iclass 11, count 0 2006.217.07:27:10.41#ibcon#read 4, iclass 11, count 0 2006.217.07:27:10.41#ibcon#about to read 5, iclass 11, count 0 2006.217.07:27:10.41#ibcon#read 5, iclass 11, count 0 2006.217.07:27:10.41#ibcon#about to read 6, iclass 11, count 0 2006.217.07:27:10.41#ibcon#read 6, iclass 11, count 0 2006.217.07:27:10.41#ibcon#end of sib2, iclass 11, count 0 2006.217.07:27:10.41#ibcon#*mode == 0, iclass 11, count 0 2006.217.07:27:10.41#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.217.07:27:10.41#ibcon#[27=USB\r\n] 2006.217.07:27:10.41#ibcon#*before write, iclass 11, count 0 2006.217.07:27:10.41#ibcon#enter sib2, iclass 11, count 0 2006.217.07:27:10.41#ibcon#flushed, iclass 11, count 0 2006.217.07:27:10.41#ibcon#about to write, iclass 11, count 0 2006.217.07:27:10.41#ibcon#wrote, iclass 11, count 0 2006.217.07:27:10.41#ibcon#about to read 3, iclass 11, count 0 2006.217.07:27:10.44#ibcon#read 3, iclass 11, count 0 2006.217.07:27:10.44#ibcon#about to read 4, iclass 11, count 0 2006.217.07:27:10.44#ibcon#read 4, iclass 11, count 0 2006.217.07:27:10.44#ibcon#about to read 5, iclass 11, count 0 2006.217.07:27:10.44#ibcon#read 5, iclass 11, count 0 2006.217.07:27:10.44#ibcon#about to read 6, iclass 11, count 0 2006.217.07:27:10.44#ibcon#read 6, iclass 11, count 0 2006.217.07:27:10.44#ibcon#end of sib2, iclass 11, count 0 2006.217.07:27:10.44#ibcon#*after write, iclass 11, count 0 2006.217.07:27:10.44#ibcon#*before return 0, iclass 11, count 0 2006.217.07:27:10.44#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.217.07:27:10.44#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.217.07:27:10.44#ibcon#about to clear, iclass 11 cls_cnt 0 2006.217.07:27:10.44#ibcon#cleared, iclass 11 cls_cnt 0 2006.217.07:27:10.44$vc4f8/vabw=wide 2006.217.07:27:10.44#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.217.07:27:10.44#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.217.07:27:10.44#ibcon#ireg 8 cls_cnt 0 2006.217.07:27:10.44#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.217.07:27:10.44#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.217.07:27:10.44#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.217.07:27:10.44#ibcon#enter wrdev, iclass 13, count 0 2006.217.07:27:10.44#ibcon#first serial, iclass 13, count 0 2006.217.07:27:10.44#ibcon#enter sib2, iclass 13, count 0 2006.217.07:27:10.44#ibcon#flushed, iclass 13, count 0 2006.217.07:27:10.44#ibcon#about to write, iclass 13, count 0 2006.217.07:27:10.44#ibcon#wrote, iclass 13, count 0 2006.217.07:27:10.44#ibcon#about to read 3, iclass 13, count 0 2006.217.07:27:10.46#ibcon#read 3, iclass 13, count 0 2006.217.07:27:10.46#ibcon#about to read 4, iclass 13, count 0 2006.217.07:27:10.46#ibcon#read 4, iclass 13, count 0 2006.217.07:27:10.46#ibcon#about to read 5, iclass 13, count 0 2006.217.07:27:10.46#ibcon#read 5, iclass 13, count 0 2006.217.07:27:10.46#ibcon#about to read 6, iclass 13, count 0 2006.217.07:27:10.46#ibcon#read 6, iclass 13, count 0 2006.217.07:27:10.46#ibcon#end of sib2, iclass 13, count 0 2006.217.07:27:10.46#ibcon#*mode == 0, iclass 13, count 0 2006.217.07:27:10.46#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.217.07:27:10.46#ibcon#[25=BW32\r\n] 2006.217.07:27:10.46#ibcon#*before write, iclass 13, count 0 2006.217.07:27:10.46#ibcon#enter sib2, iclass 13, count 0 2006.217.07:27:10.46#ibcon#flushed, iclass 13, count 0 2006.217.07:27:10.46#ibcon#about to write, iclass 13, count 0 2006.217.07:27:10.46#ibcon#wrote, iclass 13, count 0 2006.217.07:27:10.46#ibcon#about to read 3, iclass 13, count 0 2006.217.07:27:10.49#ibcon#read 3, iclass 13, count 0 2006.217.07:27:10.49#ibcon#about to read 4, iclass 13, count 0 2006.217.07:27:10.49#ibcon#read 4, iclass 13, count 0 2006.217.07:27:10.49#ibcon#about to read 5, iclass 13, count 0 2006.217.07:27:10.49#ibcon#read 5, iclass 13, count 0 2006.217.07:27:10.49#ibcon#about to read 6, iclass 13, count 0 2006.217.07:27:10.49#ibcon#read 6, iclass 13, count 0 2006.217.07:27:10.49#ibcon#end of sib2, iclass 13, count 0 2006.217.07:27:10.49#ibcon#*after write, iclass 13, count 0 2006.217.07:27:10.49#ibcon#*before return 0, iclass 13, count 0 2006.217.07:27:10.49#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.217.07:27:10.49#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.217.07:27:10.49#ibcon#about to clear, iclass 13 cls_cnt 0 2006.217.07:27:10.49#ibcon#cleared, iclass 13 cls_cnt 0 2006.217.07:27:10.49$vc4f8/vbbw=wide 2006.217.07:27:10.49#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.217.07:27:10.49#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.217.07:27:10.49#ibcon#ireg 8 cls_cnt 0 2006.217.07:27:10.49#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.217.07:27:10.56#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.217.07:27:10.56#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.217.07:27:10.56#ibcon#enter wrdev, iclass 15, count 0 2006.217.07:27:10.56#ibcon#first serial, iclass 15, count 0 2006.217.07:27:10.56#ibcon#enter sib2, iclass 15, count 0 2006.217.07:27:10.56#ibcon#flushed, iclass 15, count 0 2006.217.07:27:10.56#ibcon#about to write, iclass 15, count 0 2006.217.07:27:10.56#ibcon#wrote, iclass 15, count 0 2006.217.07:27:10.56#ibcon#about to read 3, iclass 15, count 0 2006.217.07:27:10.58#ibcon#read 3, iclass 15, count 0 2006.217.07:27:10.58#ibcon#about to read 4, iclass 15, count 0 2006.217.07:27:10.58#ibcon#read 4, iclass 15, count 0 2006.217.07:27:10.58#ibcon#about to read 5, iclass 15, count 0 2006.217.07:27:10.58#ibcon#read 5, iclass 15, count 0 2006.217.07:27:10.58#ibcon#about to read 6, iclass 15, count 0 2006.217.07:27:10.58#ibcon#read 6, iclass 15, count 0 2006.217.07:27:10.58#ibcon#end of sib2, iclass 15, count 0 2006.217.07:27:10.58#ibcon#*mode == 0, iclass 15, count 0 2006.217.07:27:10.58#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.217.07:27:10.58#ibcon#[27=BW32\r\n] 2006.217.07:27:10.58#ibcon#*before write, iclass 15, count 0 2006.217.07:27:10.58#ibcon#enter sib2, iclass 15, count 0 2006.217.07:27:10.58#ibcon#flushed, iclass 15, count 0 2006.217.07:27:10.58#ibcon#about to write, iclass 15, count 0 2006.217.07:27:10.58#ibcon#wrote, iclass 15, count 0 2006.217.07:27:10.58#ibcon#about to read 3, iclass 15, count 0 2006.217.07:27:10.61#ibcon#read 3, iclass 15, count 0 2006.217.07:27:10.61#ibcon#about to read 4, iclass 15, count 0 2006.217.07:27:10.61#ibcon#read 4, iclass 15, count 0 2006.217.07:27:10.61#ibcon#about to read 5, iclass 15, count 0 2006.217.07:27:10.61#ibcon#read 5, iclass 15, count 0 2006.217.07:27:10.61#ibcon#about to read 6, iclass 15, count 0 2006.217.07:27:10.61#ibcon#read 6, iclass 15, count 0 2006.217.07:27:10.61#ibcon#end of sib2, iclass 15, count 0 2006.217.07:27:10.61#ibcon#*after write, iclass 15, count 0 2006.217.07:27:10.61#ibcon#*before return 0, iclass 15, count 0 2006.217.07:27:10.61#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.217.07:27:10.61#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.217.07:27:10.61#ibcon#about to clear, iclass 15 cls_cnt 0 2006.217.07:27:10.61#ibcon#cleared, iclass 15 cls_cnt 0 2006.217.07:27:10.61$4f8m12a/ifd4f 2006.217.07:27:10.61&ifd4f/lo= 2006.217.07:27:10.61&ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.217.07:27:10.61&ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.217.07:27:10.61&ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.217.07:27:10.61&ifd4f/patch= 2006.217.07:27:10.61&ifd4f/patch=lo1,a1,a2,a3,a4 2006.217.07:27:10.61&ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.217.07:27:10.61&ifd4f/patch=lo3,a5,a6,a7,a8 2006.217.07:27:10.61$ifd4f/lo= 2006.217.07:27:10.61$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.217.07:27:10.61$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.217.07:27:10.61$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.217.07:27:10.61$ifd4f/patch= 2006.217.07:27:10.61$ifd4f/patch=lo1,a1,a2,a3,a4 2006.217.07:27:10.61$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.217.07:27:10.61$ifd4f/patch=lo3,a5,a6,a7,a8 2006.217.07:27:10.61$4f8m12a/"form=m,16.000,1:2 2006.217.07:27:10.61$4f8m12a/"tpicd 2006.217.07:27:10.61$4f8m12a/echo=off 2006.217.07:27:10.61$4f8m12a/xlog=off 2006.217.07:27:10.61:!2006.217.07:29:50 2006.217.07:27:27.14#trakl#Source acquired 2006.217.07:27:27.14#flagr#flagr/antenna,acquired 2006.217.07:29:50.00:preob 2006.217.07:29:50.00&preob/onsource 2006.217.07:29:50.14/onsource/TRACKING 2006.217.07:29:50.14:!2006.217.07:30:00 2006.217.07:30:00.00:data_valid=on 2006.217.07:30:00.00:midob 2006.217.07:30:00.00&midob/onsource 2006.217.07:30:00.00&midob/wx 2006.217.07:30:00.00&midob/cable 2006.217.07:30:00.00&midob/va 2006.217.07:30:00.00&midob/valo 2006.217.07:30:00.00&midob/vb 2006.217.07:30:00.00&midob/vblo 2006.217.07:30:00.00&midob/vabw 2006.217.07:30:00.00&midob/vbbw 2006.217.07:30:00.00&midob/"form 2006.217.07:30:00.00&midob/xfe 2006.217.07:30:00.00&midob/ifatt 2006.217.07:30:00.00&midob/clockoff 2006.217.07:30:00.00&midob/sy=logmail 2006.217.07:30:00.00&midob/"sy=run setcl adapt & 2006.217.07:30:00.14/onsource/TRACKING 2006.217.07:30:00.14/wx/31.37,1008.5,61 2006.217.07:30:00.26/cable/+6.3841E-03 2006.217.07:30:01.35/va/01,05,usb,yes,34,35 2006.217.07:30:01.35/va/02,04,usb,yes,32,33 2006.217.07:30:01.35/va/03,04,usb,yes,30,30 2006.217.07:30:01.35/va/04,04,usb,yes,33,36 2006.217.07:30:01.35/va/05,07,usb,yes,36,38 2006.217.07:30:01.35/va/06,06,usb,yes,35,35 2006.217.07:30:01.35/va/07,06,usb,yes,35,35 2006.217.07:30:01.35/va/08,07,usb,yes,34,33 2006.217.07:30:01.58/valo/01,532.99,yes,locked 2006.217.07:30:01.58/valo/02,572.99,yes,locked 2006.217.07:30:01.58/valo/03,672.99,yes,locked 2006.217.07:30:01.58/valo/04,832.99,yes,locked 2006.217.07:30:01.58/valo/05,652.99,yes,locked 2006.217.07:30:01.58/valo/06,772.99,yes,locked 2006.217.07:30:01.58/valo/07,832.99,yes,locked 2006.217.07:30:01.58/valo/08,852.99,yes,locked 2006.217.07:30:02.67/vb/01,04,usb,yes,32,30 2006.217.07:30:02.67/vb/02,04,usb,yes,34,35 2006.217.07:30:02.67/vb/03,04,usb,yes,30,34 2006.217.07:30:02.67/vb/04,04,usb,yes,31,31 2006.217.07:30:02.67/vb/05,04,usb,yes,29,33 2006.217.07:30:02.67/vb/06,04,usb,yes,30,33 2006.217.07:30:02.67/vb/07,04,usb,yes,33,33 2006.217.07:30:02.67/vb/08,04,usb,yes,30,33 2006.217.07:30:02.90/vblo/01,632.99,yes,locked 2006.217.07:30:02.90/vblo/02,640.99,yes,locked 2006.217.07:30:02.90/vblo/03,656.99,yes,locked 2006.217.07:30:02.90/vblo/04,712.99,yes,locked 2006.217.07:30:02.90/vblo/05,744.99,yes,locked 2006.217.07:30:02.90/vblo/06,752.99,yes,locked 2006.217.07:30:02.90/vblo/07,734.99,yes,locked 2006.217.07:30:02.90/vblo/08,744.99,yes,locked 2006.217.07:30:03.05/vabw/8 2006.217.07:30:03.20/vbbw/8 2006.217.07:30:03.29/xfe/off,on,15.0 2006.217.07:30:03.68/ifatt/23,28,28,28 2006.217.07:30:03.68&clockoff/"gps-fmout=1p 2006.217.07:30:03.68&clockoff/fmout-gps=1p 2006.217.07:30:04.07/fmout-gps/S +4.44E-07 2006.217.07:30:04.14:!2006.217.07:31:00 2006.217.07:31:00.01:data_valid=off 2006.217.07:31:00.01:postob 2006.217.07:31:00.02&postob/cable 2006.217.07:31:00.02&postob/wx 2006.217.07:31:00.02&postob/clockoff 2006.217.07:31:00.09/cable/+6.3860E-03 2006.217.07:31:00.10/wx/31.36,1008.5,60 2006.217.07:31:00.17/fmout-gps/S +4.38E-07 2006.217.07:31:00.18:scan_name=217-0733,k06217,60 2006.217.07:31:00.18:source=0823+033,082550.34,030924.5,2000.0,ccw 2006.217.07:31:01.14#flagr#flagr/antenna,new-source 2006.217.07:31:01.14:checkk5 2006.217.07:31:01.15&checkk5/chk_autoobs=1 2006.217.07:31:01.15&checkk5/chk_autoobs=2 2006.217.07:31:01.15&checkk5/chk_autoobs=3 2006.217.07:31:01.15&checkk5/chk_autoobs=4 2006.217.07:31:01.16&checkk5/chk_obsdata=1 2006.217.07:31:01.16&checkk5/chk_obsdata=2 2006.217.07:31:01.16&checkk5/chk_obsdata=3 2006.217.07:31:01.17&checkk5/chk_obsdata=4 2006.217.07:31:01.17&checkk5/k5log=1 2006.217.07:31:01.17&checkk5/k5log=2 2006.217.07:31:01.18&checkk5/k5log=3 2006.217.07:31:01.22&checkk5/k5log=4 2006.217.07:31:01.23&checkk5/obsinfo 2006.217.07:31:01.62/chk_autoobs//k5ts1/ autoobs is running! 2006.217.07:31:02.00/chk_autoobs//k5ts2/ autoobs is running! 2006.217.07:31:02.42/chk_autoobs//k5ts3/ autoobs is running! 2006.217.07:31:02.81/chk_autoobs//k5ts4/ autoobs is running! 2006.217.07:31:03.19/chk_obsdata//k5ts1/T2170730??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:31:03.56/chk_obsdata//k5ts2/T2170730??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:31:03.93/chk_obsdata//k5ts3/T2170730??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:31:04.30/chk_obsdata//k5ts4/T2170730??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:31:05.00/k5log//k5ts1_log_newline 2006.217.07:31:05.69/k5log//k5ts2_log_newline 2006.217.07:31:06.38/k5log//k5ts3_log_newline 2006.217.07:31:07.07/k5log//k5ts4_log_newline 2006.217.07:31:07.09/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.217.07:31:07.09:4f8m12a=1 2006.217.07:31:07.09$4f8m12a/echo=on 2006.217.07:31:07.09$4f8m12a/pcalon 2006.217.07:31:07.09$pcalon/"no phase cal control is implemented here 2006.217.07:31:07.09$4f8m12a/"tpicd=stop 2006.217.07:31:07.09$4f8m12a/vc4f8 2006.217.07:31:07.09$vc4f8/valo=1,532.99 2006.217.07:31:07.10#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.217.07:31:07.10#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.217.07:31:07.10#ibcon#ireg 17 cls_cnt 0 2006.217.07:31:07.10#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.217.07:31:07.10#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.217.07:31:07.10#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.217.07:31:07.10#ibcon#enter wrdev, iclass 38, count 0 2006.217.07:31:07.10#ibcon#first serial, iclass 38, count 0 2006.217.07:31:07.10#ibcon#enter sib2, iclass 38, count 0 2006.217.07:31:07.10#ibcon#flushed, iclass 38, count 0 2006.217.07:31:07.10#ibcon#about to write, iclass 38, count 0 2006.217.07:31:07.10#ibcon#wrote, iclass 38, count 0 2006.217.07:31:07.10#ibcon#about to read 3, iclass 38, count 0 2006.217.07:31:07.14#ibcon#read 3, iclass 38, count 0 2006.217.07:31:07.14#ibcon#about to read 4, iclass 38, count 0 2006.217.07:31:07.14#ibcon#read 4, iclass 38, count 0 2006.217.07:31:07.14#ibcon#about to read 5, iclass 38, count 0 2006.217.07:31:07.14#ibcon#read 5, iclass 38, count 0 2006.217.07:31:07.14#ibcon#about to read 6, iclass 38, count 0 2006.217.07:31:07.14#ibcon#read 6, iclass 38, count 0 2006.217.07:31:07.14#ibcon#end of sib2, iclass 38, count 0 2006.217.07:31:07.14#ibcon#*mode == 0, iclass 38, count 0 2006.217.07:31:07.14#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.217.07:31:07.14#ibcon#[26=FRQ=01,532.99\r\n] 2006.217.07:31:07.14#ibcon#*before write, iclass 38, count 0 2006.217.07:31:07.14#ibcon#enter sib2, iclass 38, count 0 2006.217.07:31:07.14#ibcon#flushed, iclass 38, count 0 2006.217.07:31:07.14#ibcon#about to write, iclass 38, count 0 2006.217.07:31:07.14#ibcon#wrote, iclass 38, count 0 2006.217.07:31:07.14#ibcon#about to read 3, iclass 38, count 0 2006.217.07:31:07.19#ibcon#read 3, iclass 38, count 0 2006.217.07:31:07.19#ibcon#about to read 4, iclass 38, count 0 2006.217.07:31:07.19#ibcon#read 4, iclass 38, count 0 2006.217.07:31:07.19#ibcon#about to read 5, iclass 38, count 0 2006.217.07:31:07.19#ibcon#read 5, iclass 38, count 0 2006.217.07:31:07.19#ibcon#about to read 6, iclass 38, count 0 2006.217.07:31:07.19#ibcon#read 6, iclass 38, count 0 2006.217.07:31:07.19#ibcon#end of sib2, iclass 38, count 0 2006.217.07:31:07.19#ibcon#*after write, iclass 38, count 0 2006.217.07:31:07.19#ibcon#*before return 0, iclass 38, count 0 2006.217.07:31:07.19#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.217.07:31:07.19#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.217.07:31:07.19#ibcon#about to clear, iclass 38 cls_cnt 0 2006.217.07:31:07.19#ibcon#cleared, iclass 38 cls_cnt 0 2006.217.07:31:07.19$vc4f8/va=1,5 2006.217.07:31:07.19#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.217.07:31:07.19#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.217.07:31:07.19#ibcon#ireg 11 cls_cnt 2 2006.217.07:31:07.19#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.217.07:31:07.19#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.217.07:31:07.19#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.217.07:31:07.19#ibcon#enter wrdev, iclass 40, count 2 2006.217.07:31:07.19#ibcon#first serial, iclass 40, count 2 2006.217.07:31:07.19#ibcon#enter sib2, iclass 40, count 2 2006.217.07:31:07.19#ibcon#flushed, iclass 40, count 2 2006.217.07:31:07.19#ibcon#about to write, iclass 40, count 2 2006.217.07:31:07.19#ibcon#wrote, iclass 40, count 2 2006.217.07:31:07.19#ibcon#about to read 3, iclass 40, count 2 2006.217.07:31:07.21#ibcon#read 3, iclass 40, count 2 2006.217.07:31:07.21#ibcon#about to read 4, iclass 40, count 2 2006.217.07:31:07.21#ibcon#read 4, iclass 40, count 2 2006.217.07:31:07.21#ibcon#about to read 5, iclass 40, count 2 2006.217.07:31:07.21#ibcon#read 5, iclass 40, count 2 2006.217.07:31:07.21#ibcon#about to read 6, iclass 40, count 2 2006.217.07:31:07.21#ibcon#read 6, iclass 40, count 2 2006.217.07:31:07.21#ibcon#end of sib2, iclass 40, count 2 2006.217.07:31:07.21#ibcon#*mode == 0, iclass 40, count 2 2006.217.07:31:07.21#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.217.07:31:07.21#ibcon#[25=AT01-05\r\n] 2006.217.07:31:07.21#ibcon#*before write, iclass 40, count 2 2006.217.07:31:07.21#ibcon#enter sib2, iclass 40, count 2 2006.217.07:31:07.21#ibcon#flushed, iclass 40, count 2 2006.217.07:31:07.21#ibcon#about to write, iclass 40, count 2 2006.217.07:31:07.21#ibcon#wrote, iclass 40, count 2 2006.217.07:31:07.21#ibcon#about to read 3, iclass 40, count 2 2006.217.07:31:07.24#ibcon#read 3, iclass 40, count 2 2006.217.07:31:07.24#ibcon#about to read 4, iclass 40, count 2 2006.217.07:31:07.24#ibcon#read 4, iclass 40, count 2 2006.217.07:31:07.24#ibcon#about to read 5, iclass 40, count 2 2006.217.07:31:07.24#ibcon#read 5, iclass 40, count 2 2006.217.07:31:07.24#ibcon#about to read 6, iclass 40, count 2 2006.217.07:31:07.24#ibcon#read 6, iclass 40, count 2 2006.217.07:31:07.24#ibcon#end of sib2, iclass 40, count 2 2006.217.07:31:07.24#ibcon#*after write, iclass 40, count 2 2006.217.07:31:07.24#ibcon#*before return 0, iclass 40, count 2 2006.217.07:31:07.24#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.217.07:31:07.24#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.217.07:31:07.24#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.217.07:31:07.24#ibcon#ireg 7 cls_cnt 0 2006.217.07:31:07.24#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.217.07:31:07.36#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.217.07:31:07.36#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.217.07:31:07.36#ibcon#enter wrdev, iclass 40, count 0 2006.217.07:31:07.36#ibcon#first serial, iclass 40, count 0 2006.217.07:31:07.36#ibcon#enter sib2, iclass 40, count 0 2006.217.07:31:07.36#ibcon#flushed, iclass 40, count 0 2006.217.07:31:07.36#ibcon#about to write, iclass 40, count 0 2006.217.07:31:07.36#ibcon#wrote, iclass 40, count 0 2006.217.07:31:07.36#ibcon#about to read 3, iclass 40, count 0 2006.217.07:31:07.38#ibcon#read 3, iclass 40, count 0 2006.217.07:31:07.38#ibcon#about to read 4, iclass 40, count 0 2006.217.07:31:07.38#ibcon#read 4, iclass 40, count 0 2006.217.07:31:07.38#ibcon#about to read 5, iclass 40, count 0 2006.217.07:31:07.38#ibcon#read 5, iclass 40, count 0 2006.217.07:31:07.38#ibcon#about to read 6, iclass 40, count 0 2006.217.07:31:07.38#ibcon#read 6, iclass 40, count 0 2006.217.07:31:07.38#ibcon#end of sib2, iclass 40, count 0 2006.217.07:31:07.38#ibcon#*mode == 0, iclass 40, count 0 2006.217.07:31:07.38#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.217.07:31:07.38#ibcon#[25=USB\r\n] 2006.217.07:31:07.38#ibcon#*before write, iclass 40, count 0 2006.217.07:31:07.38#ibcon#enter sib2, iclass 40, count 0 2006.217.07:31:07.38#ibcon#flushed, iclass 40, count 0 2006.217.07:31:07.38#ibcon#about to write, iclass 40, count 0 2006.217.07:31:07.38#ibcon#wrote, iclass 40, count 0 2006.217.07:31:07.38#ibcon#about to read 3, iclass 40, count 0 2006.217.07:31:07.41#ibcon#read 3, iclass 40, count 0 2006.217.07:31:07.41#ibcon#about to read 4, iclass 40, count 0 2006.217.07:31:07.41#ibcon#read 4, iclass 40, count 0 2006.217.07:31:07.41#ibcon#about to read 5, iclass 40, count 0 2006.217.07:31:07.41#ibcon#read 5, iclass 40, count 0 2006.217.07:31:07.41#ibcon#about to read 6, iclass 40, count 0 2006.217.07:31:07.41#ibcon#read 6, iclass 40, count 0 2006.217.07:31:07.41#ibcon#end of sib2, iclass 40, count 0 2006.217.07:31:07.41#ibcon#*after write, iclass 40, count 0 2006.217.07:31:07.41#ibcon#*before return 0, iclass 40, count 0 2006.217.07:31:07.41#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.217.07:31:07.41#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.217.07:31:07.41#ibcon#about to clear, iclass 40 cls_cnt 0 2006.217.07:31:07.41#ibcon#cleared, iclass 40 cls_cnt 0 2006.217.07:31:07.41$vc4f8/valo=2,572.99 2006.217.07:31:07.41#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.217.07:31:07.41#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.217.07:31:07.41#ibcon#ireg 17 cls_cnt 0 2006.217.07:31:07.41#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.217.07:31:07.41#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.217.07:31:07.41#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.217.07:31:07.41#ibcon#enter wrdev, iclass 4, count 0 2006.217.07:31:07.41#ibcon#first serial, iclass 4, count 0 2006.217.07:31:07.41#ibcon#enter sib2, iclass 4, count 0 2006.217.07:31:07.41#ibcon#flushed, iclass 4, count 0 2006.217.07:31:07.41#ibcon#about to write, iclass 4, count 0 2006.217.07:31:07.41#ibcon#wrote, iclass 4, count 0 2006.217.07:31:07.41#ibcon#about to read 3, iclass 4, count 0 2006.217.07:31:07.43#ibcon#read 3, iclass 4, count 0 2006.217.07:31:07.43#ibcon#about to read 4, iclass 4, count 0 2006.217.07:31:07.43#ibcon#read 4, iclass 4, count 0 2006.217.07:31:07.43#ibcon#about to read 5, iclass 4, count 0 2006.217.07:31:07.43#ibcon#read 5, iclass 4, count 0 2006.217.07:31:07.43#ibcon#about to read 6, iclass 4, count 0 2006.217.07:31:07.43#ibcon#read 6, iclass 4, count 0 2006.217.07:31:07.43#ibcon#end of sib2, iclass 4, count 0 2006.217.07:31:07.43#ibcon#*mode == 0, iclass 4, count 0 2006.217.07:31:07.43#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.217.07:31:07.43#ibcon#[26=FRQ=02,572.99\r\n] 2006.217.07:31:07.43#ibcon#*before write, iclass 4, count 0 2006.217.07:31:07.43#ibcon#enter sib2, iclass 4, count 0 2006.217.07:31:07.43#ibcon#flushed, iclass 4, count 0 2006.217.07:31:07.43#ibcon#about to write, iclass 4, count 0 2006.217.07:31:07.43#ibcon#wrote, iclass 4, count 0 2006.217.07:31:07.43#ibcon#about to read 3, iclass 4, count 0 2006.217.07:31:07.48#ibcon#read 3, iclass 4, count 0 2006.217.07:31:07.48#ibcon#about to read 4, iclass 4, count 0 2006.217.07:31:07.48#ibcon#read 4, iclass 4, count 0 2006.217.07:31:07.48#ibcon#about to read 5, iclass 4, count 0 2006.217.07:31:07.48#ibcon#read 5, iclass 4, count 0 2006.217.07:31:07.48#ibcon#about to read 6, iclass 4, count 0 2006.217.07:31:07.48#ibcon#read 6, iclass 4, count 0 2006.217.07:31:07.48#ibcon#end of sib2, iclass 4, count 0 2006.217.07:31:07.48#ibcon#*after write, iclass 4, count 0 2006.217.07:31:07.48#ibcon#*before return 0, iclass 4, count 0 2006.217.07:31:07.48#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.217.07:31:07.48#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.217.07:31:07.48#ibcon#about to clear, iclass 4 cls_cnt 0 2006.217.07:31:07.48#ibcon#cleared, iclass 4 cls_cnt 0 2006.217.07:31:07.48$vc4f8/va=2,4 2006.217.07:31:07.48#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.217.07:31:07.48#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.217.07:31:07.48#ibcon#ireg 11 cls_cnt 2 2006.217.07:31:07.48#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.217.07:31:07.53#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.217.07:31:07.53#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.217.07:31:07.53#ibcon#enter wrdev, iclass 6, count 2 2006.217.07:31:07.53#ibcon#first serial, iclass 6, count 2 2006.217.07:31:07.53#ibcon#enter sib2, iclass 6, count 2 2006.217.07:31:07.53#ibcon#flushed, iclass 6, count 2 2006.217.07:31:07.53#ibcon#about to write, iclass 6, count 2 2006.217.07:31:07.53#ibcon#wrote, iclass 6, count 2 2006.217.07:31:07.53#ibcon#about to read 3, iclass 6, count 2 2006.217.07:31:07.55#ibcon#read 3, iclass 6, count 2 2006.217.07:31:07.55#ibcon#about to read 4, iclass 6, count 2 2006.217.07:31:07.55#ibcon#read 4, iclass 6, count 2 2006.217.07:31:07.55#ibcon#about to read 5, iclass 6, count 2 2006.217.07:31:07.55#ibcon#read 5, iclass 6, count 2 2006.217.07:31:07.55#ibcon#about to read 6, iclass 6, count 2 2006.217.07:31:07.55#ibcon#read 6, iclass 6, count 2 2006.217.07:31:07.55#ibcon#end of sib2, iclass 6, count 2 2006.217.07:31:07.55#ibcon#*mode == 0, iclass 6, count 2 2006.217.07:31:07.55#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.217.07:31:07.55#ibcon#[25=AT02-04\r\n] 2006.217.07:31:07.55#ibcon#*before write, iclass 6, count 2 2006.217.07:31:07.55#ibcon#enter sib2, iclass 6, count 2 2006.217.07:31:07.55#ibcon#flushed, iclass 6, count 2 2006.217.07:31:07.55#ibcon#about to write, iclass 6, count 2 2006.217.07:31:07.55#ibcon#wrote, iclass 6, count 2 2006.217.07:31:07.55#ibcon#about to read 3, iclass 6, count 2 2006.217.07:31:07.58#ibcon#read 3, iclass 6, count 2 2006.217.07:31:07.58#ibcon#about to read 4, iclass 6, count 2 2006.217.07:31:07.58#ibcon#read 4, iclass 6, count 2 2006.217.07:31:07.58#ibcon#about to read 5, iclass 6, count 2 2006.217.07:31:07.58#ibcon#read 5, iclass 6, count 2 2006.217.07:31:07.58#ibcon#about to read 6, iclass 6, count 2 2006.217.07:31:07.58#ibcon#read 6, iclass 6, count 2 2006.217.07:31:07.58#ibcon#end of sib2, iclass 6, count 2 2006.217.07:31:07.58#ibcon#*after write, iclass 6, count 2 2006.217.07:31:07.58#ibcon#*before return 0, iclass 6, count 2 2006.217.07:31:07.58#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.217.07:31:07.58#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.217.07:31:07.58#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.217.07:31:07.58#ibcon#ireg 7 cls_cnt 0 2006.217.07:31:07.58#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.217.07:31:07.70#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.217.07:31:07.70#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.217.07:31:07.70#ibcon#enter wrdev, iclass 6, count 0 2006.217.07:31:07.70#ibcon#first serial, iclass 6, count 0 2006.217.07:31:07.70#ibcon#enter sib2, iclass 6, count 0 2006.217.07:31:07.70#ibcon#flushed, iclass 6, count 0 2006.217.07:31:07.70#ibcon#about to write, iclass 6, count 0 2006.217.07:31:07.70#ibcon#wrote, iclass 6, count 0 2006.217.07:31:07.70#ibcon#about to read 3, iclass 6, count 0 2006.217.07:31:07.72#ibcon#read 3, iclass 6, count 0 2006.217.07:31:07.72#ibcon#about to read 4, iclass 6, count 0 2006.217.07:31:07.72#ibcon#read 4, iclass 6, count 0 2006.217.07:31:07.72#ibcon#about to read 5, iclass 6, count 0 2006.217.07:31:07.72#ibcon#read 5, iclass 6, count 0 2006.217.07:31:07.72#ibcon#about to read 6, iclass 6, count 0 2006.217.07:31:07.72#ibcon#read 6, iclass 6, count 0 2006.217.07:31:07.72#ibcon#end of sib2, iclass 6, count 0 2006.217.07:31:07.72#ibcon#*mode == 0, iclass 6, count 0 2006.217.07:31:07.72#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.217.07:31:07.72#ibcon#[25=USB\r\n] 2006.217.07:31:07.72#ibcon#*before write, iclass 6, count 0 2006.217.07:31:07.72#ibcon#enter sib2, iclass 6, count 0 2006.217.07:31:07.72#ibcon#flushed, iclass 6, count 0 2006.217.07:31:07.72#ibcon#about to write, iclass 6, count 0 2006.217.07:31:07.72#ibcon#wrote, iclass 6, count 0 2006.217.07:31:07.72#ibcon#about to read 3, iclass 6, count 0 2006.217.07:31:07.75#ibcon#read 3, iclass 6, count 0 2006.217.07:31:07.75#ibcon#about to read 4, iclass 6, count 0 2006.217.07:31:07.75#ibcon#read 4, iclass 6, count 0 2006.217.07:31:07.75#ibcon#about to read 5, iclass 6, count 0 2006.217.07:31:07.75#ibcon#read 5, iclass 6, count 0 2006.217.07:31:07.75#ibcon#about to read 6, iclass 6, count 0 2006.217.07:31:07.75#ibcon#read 6, iclass 6, count 0 2006.217.07:31:07.75#ibcon#end of sib2, iclass 6, count 0 2006.217.07:31:07.75#ibcon#*after write, iclass 6, count 0 2006.217.07:31:07.75#ibcon#*before return 0, iclass 6, count 0 2006.217.07:31:07.75#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.217.07:31:07.75#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.217.07:31:07.75#ibcon#about to clear, iclass 6 cls_cnt 0 2006.217.07:31:07.75#ibcon#cleared, iclass 6 cls_cnt 0 2006.217.07:31:07.75$vc4f8/valo=3,672.99 2006.217.07:31:07.75#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.217.07:31:07.75#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.217.07:31:07.75#ibcon#ireg 17 cls_cnt 0 2006.217.07:31:07.75#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.217.07:31:07.75#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.217.07:31:07.75#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.217.07:31:07.75#ibcon#enter wrdev, iclass 10, count 0 2006.217.07:31:07.75#ibcon#first serial, iclass 10, count 0 2006.217.07:31:07.75#ibcon#enter sib2, iclass 10, count 0 2006.217.07:31:07.75#ibcon#flushed, iclass 10, count 0 2006.217.07:31:07.75#ibcon#about to write, iclass 10, count 0 2006.217.07:31:07.75#ibcon#wrote, iclass 10, count 0 2006.217.07:31:07.75#ibcon#about to read 3, iclass 10, count 0 2006.217.07:31:07.77#ibcon#read 3, iclass 10, count 0 2006.217.07:31:07.77#ibcon#about to read 4, iclass 10, count 0 2006.217.07:31:07.77#ibcon#read 4, iclass 10, count 0 2006.217.07:31:07.77#ibcon#about to read 5, iclass 10, count 0 2006.217.07:31:07.77#ibcon#read 5, iclass 10, count 0 2006.217.07:31:07.77#ibcon#about to read 6, iclass 10, count 0 2006.217.07:31:07.77#ibcon#read 6, iclass 10, count 0 2006.217.07:31:07.77#ibcon#end of sib2, iclass 10, count 0 2006.217.07:31:07.77#ibcon#*mode == 0, iclass 10, count 0 2006.217.07:31:07.77#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.217.07:31:07.77#ibcon#[26=FRQ=03,672.99\r\n] 2006.217.07:31:07.77#ibcon#*before write, iclass 10, count 0 2006.217.07:31:07.77#ibcon#enter sib2, iclass 10, count 0 2006.217.07:31:07.77#ibcon#flushed, iclass 10, count 0 2006.217.07:31:07.77#ibcon#about to write, iclass 10, count 0 2006.217.07:31:07.77#ibcon#wrote, iclass 10, count 0 2006.217.07:31:07.77#ibcon#about to read 3, iclass 10, count 0 2006.217.07:31:07.82#ibcon#read 3, iclass 10, count 0 2006.217.07:31:07.82#ibcon#about to read 4, iclass 10, count 0 2006.217.07:31:07.82#ibcon#read 4, iclass 10, count 0 2006.217.07:31:07.82#ibcon#about to read 5, iclass 10, count 0 2006.217.07:31:07.82#ibcon#read 5, iclass 10, count 0 2006.217.07:31:07.82#ibcon#about to read 6, iclass 10, count 0 2006.217.07:31:07.82#ibcon#read 6, iclass 10, count 0 2006.217.07:31:07.82#ibcon#end of sib2, iclass 10, count 0 2006.217.07:31:07.82#ibcon#*after write, iclass 10, count 0 2006.217.07:31:07.82#ibcon#*before return 0, iclass 10, count 0 2006.217.07:31:07.82#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.217.07:31:07.82#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.217.07:31:07.82#ibcon#about to clear, iclass 10 cls_cnt 0 2006.217.07:31:07.82#ibcon#cleared, iclass 10 cls_cnt 0 2006.217.07:31:07.82$vc4f8/va=3,4 2006.217.07:31:07.82#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.217.07:31:07.82#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.217.07:31:07.82#ibcon#ireg 11 cls_cnt 2 2006.217.07:31:07.82#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.217.07:31:07.87#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.217.07:31:07.87#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.217.07:31:07.87#ibcon#enter wrdev, iclass 12, count 2 2006.217.07:31:07.87#ibcon#first serial, iclass 12, count 2 2006.217.07:31:07.87#ibcon#enter sib2, iclass 12, count 2 2006.217.07:31:07.87#ibcon#flushed, iclass 12, count 2 2006.217.07:31:07.87#ibcon#about to write, iclass 12, count 2 2006.217.07:31:07.87#ibcon#wrote, iclass 12, count 2 2006.217.07:31:07.87#ibcon#about to read 3, iclass 12, count 2 2006.217.07:31:07.89#ibcon#read 3, iclass 12, count 2 2006.217.07:31:07.89#ibcon#about to read 4, iclass 12, count 2 2006.217.07:31:07.89#ibcon#read 4, iclass 12, count 2 2006.217.07:31:07.89#ibcon#about to read 5, iclass 12, count 2 2006.217.07:31:07.89#ibcon#read 5, iclass 12, count 2 2006.217.07:31:07.89#ibcon#about to read 6, iclass 12, count 2 2006.217.07:31:07.89#ibcon#read 6, iclass 12, count 2 2006.217.07:31:07.89#ibcon#end of sib2, iclass 12, count 2 2006.217.07:31:07.89#ibcon#*mode == 0, iclass 12, count 2 2006.217.07:31:07.89#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.217.07:31:07.89#ibcon#[25=AT03-04\r\n] 2006.217.07:31:07.89#ibcon#*before write, iclass 12, count 2 2006.217.07:31:07.89#ibcon#enter sib2, iclass 12, count 2 2006.217.07:31:07.89#ibcon#flushed, iclass 12, count 2 2006.217.07:31:07.89#ibcon#about to write, iclass 12, count 2 2006.217.07:31:07.89#ibcon#wrote, iclass 12, count 2 2006.217.07:31:07.89#ibcon#about to read 3, iclass 12, count 2 2006.217.07:31:07.92#ibcon#read 3, iclass 12, count 2 2006.217.07:31:07.92#ibcon#about to read 4, iclass 12, count 2 2006.217.07:31:07.92#ibcon#read 4, iclass 12, count 2 2006.217.07:31:07.92#ibcon#about to read 5, iclass 12, count 2 2006.217.07:31:07.92#ibcon#read 5, iclass 12, count 2 2006.217.07:31:07.92#ibcon#about to read 6, iclass 12, count 2 2006.217.07:31:07.92#ibcon#read 6, iclass 12, count 2 2006.217.07:31:07.92#ibcon#end of sib2, iclass 12, count 2 2006.217.07:31:07.92#ibcon#*after write, iclass 12, count 2 2006.217.07:31:07.92#ibcon#*before return 0, iclass 12, count 2 2006.217.07:31:07.92#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.217.07:31:07.92#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.217.07:31:07.92#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.217.07:31:07.92#ibcon#ireg 7 cls_cnt 0 2006.217.07:31:07.92#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.217.07:31:08.04#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.217.07:31:08.04#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.217.07:31:08.04#ibcon#enter wrdev, iclass 12, count 0 2006.217.07:31:08.04#ibcon#first serial, iclass 12, count 0 2006.217.07:31:08.04#ibcon#enter sib2, iclass 12, count 0 2006.217.07:31:08.04#ibcon#flushed, iclass 12, count 0 2006.217.07:31:08.04#ibcon#about to write, iclass 12, count 0 2006.217.07:31:08.04#ibcon#wrote, iclass 12, count 0 2006.217.07:31:08.04#ibcon#about to read 3, iclass 12, count 0 2006.217.07:31:08.07#ibcon#read 3, iclass 12, count 0 2006.217.07:31:08.07#ibcon#about to read 4, iclass 12, count 0 2006.217.07:31:08.07#ibcon#read 4, iclass 12, count 0 2006.217.07:31:08.07#ibcon#about to read 5, iclass 12, count 0 2006.217.07:31:08.07#ibcon#read 5, iclass 12, count 0 2006.217.07:31:08.07#ibcon#about to read 6, iclass 12, count 0 2006.217.07:31:08.07#ibcon#read 6, iclass 12, count 0 2006.217.07:31:08.07#ibcon#end of sib2, iclass 12, count 0 2006.217.07:31:08.07#ibcon#*mode == 0, iclass 12, count 0 2006.217.07:31:08.07#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.217.07:31:08.07#ibcon#[25=USB\r\n] 2006.217.07:31:08.07#ibcon#*before write, iclass 12, count 0 2006.217.07:31:08.07#ibcon#enter sib2, iclass 12, count 0 2006.217.07:31:08.07#ibcon#flushed, iclass 12, count 0 2006.217.07:31:08.07#ibcon#about to write, iclass 12, count 0 2006.217.07:31:08.07#ibcon#wrote, iclass 12, count 0 2006.217.07:31:08.07#ibcon#about to read 3, iclass 12, count 0 2006.217.07:31:08.10#ibcon#read 3, iclass 12, count 0 2006.217.07:31:08.10#ibcon#about to read 4, iclass 12, count 0 2006.217.07:31:08.10#ibcon#read 4, iclass 12, count 0 2006.217.07:31:08.10#ibcon#about to read 5, iclass 12, count 0 2006.217.07:31:08.10#ibcon#read 5, iclass 12, count 0 2006.217.07:31:08.10#ibcon#about to read 6, iclass 12, count 0 2006.217.07:31:08.10#ibcon#read 6, iclass 12, count 0 2006.217.07:31:08.10#ibcon#end of sib2, iclass 12, count 0 2006.217.07:31:08.10#ibcon#*after write, iclass 12, count 0 2006.217.07:31:08.10#ibcon#*before return 0, iclass 12, count 0 2006.217.07:31:08.10#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.217.07:31:08.10#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.217.07:31:08.10#ibcon#about to clear, iclass 12 cls_cnt 0 2006.217.07:31:08.10#ibcon#cleared, iclass 12 cls_cnt 0 2006.217.07:31:08.10$vc4f8/valo=4,832.99 2006.217.07:31:08.10#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.217.07:31:08.10#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.217.07:31:08.10#ibcon#ireg 17 cls_cnt 0 2006.217.07:31:08.10#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.217.07:31:08.10#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.217.07:31:08.10#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.217.07:31:08.10#ibcon#enter wrdev, iclass 14, count 0 2006.217.07:31:08.10#ibcon#first serial, iclass 14, count 0 2006.217.07:31:08.10#ibcon#enter sib2, iclass 14, count 0 2006.217.07:31:08.10#ibcon#flushed, iclass 14, count 0 2006.217.07:31:08.10#ibcon#about to write, iclass 14, count 0 2006.217.07:31:08.10#ibcon#wrote, iclass 14, count 0 2006.217.07:31:08.10#ibcon#about to read 3, iclass 14, count 0 2006.217.07:31:08.12#ibcon#read 3, iclass 14, count 0 2006.217.07:31:08.12#ibcon#about to read 4, iclass 14, count 0 2006.217.07:31:08.12#ibcon#read 4, iclass 14, count 0 2006.217.07:31:08.12#ibcon#about to read 5, iclass 14, count 0 2006.217.07:31:08.12#ibcon#read 5, iclass 14, count 0 2006.217.07:31:08.12#ibcon#about to read 6, iclass 14, count 0 2006.217.07:31:08.12#ibcon#read 6, iclass 14, count 0 2006.217.07:31:08.12#ibcon#end of sib2, iclass 14, count 0 2006.217.07:31:08.12#ibcon#*mode == 0, iclass 14, count 0 2006.217.07:31:08.12#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.217.07:31:08.12#ibcon#[26=FRQ=04,832.99\r\n] 2006.217.07:31:08.12#ibcon#*before write, iclass 14, count 0 2006.217.07:31:08.12#ibcon#enter sib2, iclass 14, count 0 2006.217.07:31:08.12#ibcon#flushed, iclass 14, count 0 2006.217.07:31:08.12#ibcon#about to write, iclass 14, count 0 2006.217.07:31:08.12#ibcon#wrote, iclass 14, count 0 2006.217.07:31:08.12#ibcon#about to read 3, iclass 14, count 0 2006.217.07:31:08.16#ibcon#read 3, iclass 14, count 0 2006.217.07:31:08.16#ibcon#about to read 4, iclass 14, count 0 2006.217.07:31:08.16#ibcon#read 4, iclass 14, count 0 2006.217.07:31:08.16#ibcon#about to read 5, iclass 14, count 0 2006.217.07:31:08.16#ibcon#read 5, iclass 14, count 0 2006.217.07:31:08.16#ibcon#about to read 6, iclass 14, count 0 2006.217.07:31:08.16#ibcon#read 6, iclass 14, count 0 2006.217.07:31:08.16#ibcon#end of sib2, iclass 14, count 0 2006.217.07:31:08.16#ibcon#*after write, iclass 14, count 0 2006.217.07:31:08.16#ibcon#*before return 0, iclass 14, count 0 2006.217.07:31:08.16#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.217.07:31:08.16#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.217.07:31:08.16#ibcon#about to clear, iclass 14 cls_cnt 0 2006.217.07:31:08.16#ibcon#cleared, iclass 14 cls_cnt 0 2006.217.07:31:08.16$vc4f8/va=4,4 2006.217.07:31:08.16#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.217.07:31:08.16#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.217.07:31:08.16#ibcon#ireg 11 cls_cnt 2 2006.217.07:31:08.16#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.217.07:31:08.22#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.217.07:31:08.22#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.217.07:31:08.22#ibcon#enter wrdev, iclass 16, count 2 2006.217.07:31:08.22#ibcon#first serial, iclass 16, count 2 2006.217.07:31:08.22#ibcon#enter sib2, iclass 16, count 2 2006.217.07:31:08.22#ibcon#flushed, iclass 16, count 2 2006.217.07:31:08.22#ibcon#about to write, iclass 16, count 2 2006.217.07:31:08.22#ibcon#wrote, iclass 16, count 2 2006.217.07:31:08.22#ibcon#about to read 3, iclass 16, count 2 2006.217.07:31:08.24#ibcon#read 3, iclass 16, count 2 2006.217.07:31:08.24#ibcon#about to read 4, iclass 16, count 2 2006.217.07:31:08.24#ibcon#read 4, iclass 16, count 2 2006.217.07:31:08.24#ibcon#about to read 5, iclass 16, count 2 2006.217.07:31:08.24#ibcon#read 5, iclass 16, count 2 2006.217.07:31:08.24#ibcon#about to read 6, iclass 16, count 2 2006.217.07:31:08.24#ibcon#read 6, iclass 16, count 2 2006.217.07:31:08.24#ibcon#end of sib2, iclass 16, count 2 2006.217.07:31:08.24#ibcon#*mode == 0, iclass 16, count 2 2006.217.07:31:08.24#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.217.07:31:08.24#ibcon#[25=AT04-04\r\n] 2006.217.07:31:08.24#ibcon#*before write, iclass 16, count 2 2006.217.07:31:08.24#ibcon#enter sib2, iclass 16, count 2 2006.217.07:31:08.24#ibcon#flushed, iclass 16, count 2 2006.217.07:31:08.24#ibcon#about to write, iclass 16, count 2 2006.217.07:31:08.24#ibcon#wrote, iclass 16, count 2 2006.217.07:31:08.24#ibcon#about to read 3, iclass 16, count 2 2006.217.07:31:08.27#ibcon#read 3, iclass 16, count 2 2006.217.07:31:08.27#ibcon#about to read 4, iclass 16, count 2 2006.217.07:31:08.27#ibcon#read 4, iclass 16, count 2 2006.217.07:31:08.27#ibcon#about to read 5, iclass 16, count 2 2006.217.07:31:08.27#ibcon#read 5, iclass 16, count 2 2006.217.07:31:08.27#ibcon#about to read 6, iclass 16, count 2 2006.217.07:31:08.27#ibcon#read 6, iclass 16, count 2 2006.217.07:31:08.27#ibcon#end of sib2, iclass 16, count 2 2006.217.07:31:08.27#ibcon#*after write, iclass 16, count 2 2006.217.07:31:08.27#ibcon#*before return 0, iclass 16, count 2 2006.217.07:31:08.27#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.217.07:31:08.27#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.217.07:31:08.27#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.217.07:31:08.27#ibcon#ireg 7 cls_cnt 0 2006.217.07:31:08.27#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.217.07:31:08.39#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.217.07:31:08.39#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.217.07:31:08.39#ibcon#enter wrdev, iclass 16, count 0 2006.217.07:31:08.39#ibcon#first serial, iclass 16, count 0 2006.217.07:31:08.39#ibcon#enter sib2, iclass 16, count 0 2006.217.07:31:08.39#ibcon#flushed, iclass 16, count 0 2006.217.07:31:08.39#ibcon#about to write, iclass 16, count 0 2006.217.07:31:08.39#ibcon#wrote, iclass 16, count 0 2006.217.07:31:08.39#ibcon#about to read 3, iclass 16, count 0 2006.217.07:31:08.41#ibcon#read 3, iclass 16, count 0 2006.217.07:31:08.41#ibcon#about to read 4, iclass 16, count 0 2006.217.07:31:08.41#ibcon#read 4, iclass 16, count 0 2006.217.07:31:08.41#ibcon#about to read 5, iclass 16, count 0 2006.217.07:31:08.41#ibcon#read 5, iclass 16, count 0 2006.217.07:31:08.41#ibcon#about to read 6, iclass 16, count 0 2006.217.07:31:08.41#ibcon#read 6, iclass 16, count 0 2006.217.07:31:08.41#ibcon#end of sib2, iclass 16, count 0 2006.217.07:31:08.41#ibcon#*mode == 0, iclass 16, count 0 2006.217.07:31:08.41#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.217.07:31:08.41#ibcon#[25=USB\r\n] 2006.217.07:31:08.41#ibcon#*before write, iclass 16, count 0 2006.217.07:31:08.41#ibcon#enter sib2, iclass 16, count 0 2006.217.07:31:08.41#ibcon#flushed, iclass 16, count 0 2006.217.07:31:08.41#ibcon#about to write, iclass 16, count 0 2006.217.07:31:08.41#ibcon#wrote, iclass 16, count 0 2006.217.07:31:08.41#ibcon#about to read 3, iclass 16, count 0 2006.217.07:31:08.44#ibcon#read 3, iclass 16, count 0 2006.217.07:31:08.44#ibcon#about to read 4, iclass 16, count 0 2006.217.07:31:08.44#ibcon#read 4, iclass 16, count 0 2006.217.07:31:08.44#ibcon#about to read 5, iclass 16, count 0 2006.217.07:31:08.44#ibcon#read 5, iclass 16, count 0 2006.217.07:31:08.44#ibcon#about to read 6, iclass 16, count 0 2006.217.07:31:08.44#ibcon#read 6, iclass 16, count 0 2006.217.07:31:08.44#ibcon#end of sib2, iclass 16, count 0 2006.217.07:31:08.44#ibcon#*after write, iclass 16, count 0 2006.217.07:31:08.44#ibcon#*before return 0, iclass 16, count 0 2006.217.07:31:08.44#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.217.07:31:08.44#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.217.07:31:08.44#ibcon#about to clear, iclass 16 cls_cnt 0 2006.217.07:31:08.44#ibcon#cleared, iclass 16 cls_cnt 0 2006.217.07:31:08.44$vc4f8/valo=5,652.99 2006.217.07:31:08.44#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.217.07:31:08.44#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.217.07:31:08.44#ibcon#ireg 17 cls_cnt 0 2006.217.07:31:08.44#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.217.07:31:08.44#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.217.07:31:08.44#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.217.07:31:08.44#ibcon#enter wrdev, iclass 18, count 0 2006.217.07:31:08.44#ibcon#first serial, iclass 18, count 0 2006.217.07:31:08.44#ibcon#enter sib2, iclass 18, count 0 2006.217.07:31:08.44#ibcon#flushed, iclass 18, count 0 2006.217.07:31:08.44#ibcon#about to write, iclass 18, count 0 2006.217.07:31:08.44#ibcon#wrote, iclass 18, count 0 2006.217.07:31:08.44#ibcon#about to read 3, iclass 18, count 0 2006.217.07:31:08.46#ibcon#read 3, iclass 18, count 0 2006.217.07:31:08.46#ibcon#about to read 4, iclass 18, count 0 2006.217.07:31:08.46#ibcon#read 4, iclass 18, count 0 2006.217.07:31:08.46#ibcon#about to read 5, iclass 18, count 0 2006.217.07:31:08.46#ibcon#read 5, iclass 18, count 0 2006.217.07:31:08.46#ibcon#about to read 6, iclass 18, count 0 2006.217.07:31:08.46#ibcon#read 6, iclass 18, count 0 2006.217.07:31:08.46#ibcon#end of sib2, iclass 18, count 0 2006.217.07:31:08.46#ibcon#*mode == 0, iclass 18, count 0 2006.217.07:31:08.46#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.217.07:31:08.46#ibcon#[26=FRQ=05,652.99\r\n] 2006.217.07:31:08.46#ibcon#*before write, iclass 18, count 0 2006.217.07:31:08.46#ibcon#enter sib2, iclass 18, count 0 2006.217.07:31:08.46#ibcon#flushed, iclass 18, count 0 2006.217.07:31:08.46#ibcon#about to write, iclass 18, count 0 2006.217.07:31:08.46#ibcon#wrote, iclass 18, count 0 2006.217.07:31:08.46#ibcon#about to read 3, iclass 18, count 0 2006.217.07:31:08.50#ibcon#read 3, iclass 18, count 0 2006.217.07:31:08.50#ibcon#about to read 4, iclass 18, count 0 2006.217.07:31:08.50#ibcon#read 4, iclass 18, count 0 2006.217.07:31:08.50#ibcon#about to read 5, iclass 18, count 0 2006.217.07:31:08.50#ibcon#read 5, iclass 18, count 0 2006.217.07:31:08.50#ibcon#about to read 6, iclass 18, count 0 2006.217.07:31:08.50#ibcon#read 6, iclass 18, count 0 2006.217.07:31:08.50#ibcon#end of sib2, iclass 18, count 0 2006.217.07:31:08.50#ibcon#*after write, iclass 18, count 0 2006.217.07:31:08.50#ibcon#*before return 0, iclass 18, count 0 2006.217.07:31:08.50#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.217.07:31:08.50#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.217.07:31:08.50#ibcon#about to clear, iclass 18 cls_cnt 0 2006.217.07:31:08.50#ibcon#cleared, iclass 18 cls_cnt 0 2006.217.07:31:08.50$vc4f8/va=5,7 2006.217.07:31:08.50#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.217.07:31:08.50#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.217.07:31:08.50#ibcon#ireg 11 cls_cnt 2 2006.217.07:31:08.50#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.217.07:31:08.56#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.217.07:31:08.56#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.217.07:31:08.56#ibcon#enter wrdev, iclass 20, count 2 2006.217.07:31:08.56#ibcon#first serial, iclass 20, count 2 2006.217.07:31:08.56#ibcon#enter sib2, iclass 20, count 2 2006.217.07:31:08.56#ibcon#flushed, iclass 20, count 2 2006.217.07:31:08.56#ibcon#about to write, iclass 20, count 2 2006.217.07:31:08.56#ibcon#wrote, iclass 20, count 2 2006.217.07:31:08.56#ibcon#about to read 3, iclass 20, count 2 2006.217.07:31:08.58#ibcon#read 3, iclass 20, count 2 2006.217.07:31:08.58#ibcon#about to read 4, iclass 20, count 2 2006.217.07:31:08.58#ibcon#read 4, iclass 20, count 2 2006.217.07:31:08.58#ibcon#about to read 5, iclass 20, count 2 2006.217.07:31:08.58#ibcon#read 5, iclass 20, count 2 2006.217.07:31:08.58#ibcon#about to read 6, iclass 20, count 2 2006.217.07:31:08.58#ibcon#read 6, iclass 20, count 2 2006.217.07:31:08.58#ibcon#end of sib2, iclass 20, count 2 2006.217.07:31:08.58#ibcon#*mode == 0, iclass 20, count 2 2006.217.07:31:08.58#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.217.07:31:08.58#ibcon#[25=AT05-07\r\n] 2006.217.07:31:08.58#ibcon#*before write, iclass 20, count 2 2006.217.07:31:08.58#ibcon#enter sib2, iclass 20, count 2 2006.217.07:31:08.58#ibcon#flushed, iclass 20, count 2 2006.217.07:31:08.58#ibcon#about to write, iclass 20, count 2 2006.217.07:31:08.58#ibcon#wrote, iclass 20, count 2 2006.217.07:31:08.58#ibcon#about to read 3, iclass 20, count 2 2006.217.07:31:08.61#ibcon#read 3, iclass 20, count 2 2006.217.07:31:08.61#ibcon#about to read 4, iclass 20, count 2 2006.217.07:31:08.61#ibcon#read 4, iclass 20, count 2 2006.217.07:31:08.61#ibcon#about to read 5, iclass 20, count 2 2006.217.07:31:08.61#ibcon#read 5, iclass 20, count 2 2006.217.07:31:08.61#ibcon#about to read 6, iclass 20, count 2 2006.217.07:31:08.61#ibcon#read 6, iclass 20, count 2 2006.217.07:31:08.61#ibcon#end of sib2, iclass 20, count 2 2006.217.07:31:08.61#ibcon#*after write, iclass 20, count 2 2006.217.07:31:08.61#ibcon#*before return 0, iclass 20, count 2 2006.217.07:31:08.61#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.217.07:31:08.61#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.217.07:31:08.61#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.217.07:31:08.61#ibcon#ireg 7 cls_cnt 0 2006.217.07:31:08.61#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.217.07:31:08.73#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.217.07:31:08.73#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.217.07:31:08.73#ibcon#enter wrdev, iclass 20, count 0 2006.217.07:31:08.73#ibcon#first serial, iclass 20, count 0 2006.217.07:31:08.73#ibcon#enter sib2, iclass 20, count 0 2006.217.07:31:08.73#ibcon#flushed, iclass 20, count 0 2006.217.07:31:08.73#ibcon#about to write, iclass 20, count 0 2006.217.07:31:08.73#ibcon#wrote, iclass 20, count 0 2006.217.07:31:08.73#ibcon#about to read 3, iclass 20, count 0 2006.217.07:31:08.75#ibcon#read 3, iclass 20, count 0 2006.217.07:31:08.75#ibcon#about to read 4, iclass 20, count 0 2006.217.07:31:08.75#ibcon#read 4, iclass 20, count 0 2006.217.07:31:08.75#ibcon#about to read 5, iclass 20, count 0 2006.217.07:31:08.75#ibcon#read 5, iclass 20, count 0 2006.217.07:31:08.75#ibcon#about to read 6, iclass 20, count 0 2006.217.07:31:08.75#ibcon#read 6, iclass 20, count 0 2006.217.07:31:08.75#ibcon#end of sib2, iclass 20, count 0 2006.217.07:31:08.75#ibcon#*mode == 0, iclass 20, count 0 2006.217.07:31:08.75#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.217.07:31:08.75#ibcon#[25=USB\r\n] 2006.217.07:31:08.75#ibcon#*before write, iclass 20, count 0 2006.217.07:31:08.75#ibcon#enter sib2, iclass 20, count 0 2006.217.07:31:08.75#ibcon#flushed, iclass 20, count 0 2006.217.07:31:08.75#ibcon#about to write, iclass 20, count 0 2006.217.07:31:08.75#ibcon#wrote, iclass 20, count 0 2006.217.07:31:08.75#ibcon#about to read 3, iclass 20, count 0 2006.217.07:31:08.78#ibcon#read 3, iclass 20, count 0 2006.217.07:31:08.78#ibcon#about to read 4, iclass 20, count 0 2006.217.07:31:08.78#ibcon#read 4, iclass 20, count 0 2006.217.07:31:08.78#ibcon#about to read 5, iclass 20, count 0 2006.217.07:31:08.78#ibcon#read 5, iclass 20, count 0 2006.217.07:31:08.78#ibcon#about to read 6, iclass 20, count 0 2006.217.07:31:08.78#ibcon#read 6, iclass 20, count 0 2006.217.07:31:08.78#ibcon#end of sib2, iclass 20, count 0 2006.217.07:31:08.78#ibcon#*after write, iclass 20, count 0 2006.217.07:31:08.78#ibcon#*before return 0, iclass 20, count 0 2006.217.07:31:08.78#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.217.07:31:08.78#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.217.07:31:08.78#ibcon#about to clear, iclass 20 cls_cnt 0 2006.217.07:31:08.78#ibcon#cleared, iclass 20 cls_cnt 0 2006.217.07:31:08.78$vc4f8/valo=6,772.99 2006.217.07:31:08.78#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.217.07:31:08.78#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.217.07:31:08.78#ibcon#ireg 17 cls_cnt 0 2006.217.07:31:08.78#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.217.07:31:08.78#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.217.07:31:08.78#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.217.07:31:08.78#ibcon#enter wrdev, iclass 22, count 0 2006.217.07:31:08.78#ibcon#first serial, iclass 22, count 0 2006.217.07:31:08.78#ibcon#enter sib2, iclass 22, count 0 2006.217.07:31:08.78#ibcon#flushed, iclass 22, count 0 2006.217.07:31:08.78#ibcon#about to write, iclass 22, count 0 2006.217.07:31:08.78#ibcon#wrote, iclass 22, count 0 2006.217.07:31:08.78#ibcon#about to read 3, iclass 22, count 0 2006.217.07:31:08.80#ibcon#read 3, iclass 22, count 0 2006.217.07:31:08.80#ibcon#about to read 4, iclass 22, count 0 2006.217.07:31:08.80#ibcon#read 4, iclass 22, count 0 2006.217.07:31:08.80#ibcon#about to read 5, iclass 22, count 0 2006.217.07:31:08.80#ibcon#read 5, iclass 22, count 0 2006.217.07:31:08.80#ibcon#about to read 6, iclass 22, count 0 2006.217.07:31:08.80#ibcon#read 6, iclass 22, count 0 2006.217.07:31:08.80#ibcon#end of sib2, iclass 22, count 0 2006.217.07:31:08.80#ibcon#*mode == 0, iclass 22, count 0 2006.217.07:31:08.80#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.217.07:31:08.80#ibcon#[26=FRQ=06,772.99\r\n] 2006.217.07:31:08.80#ibcon#*before write, iclass 22, count 0 2006.217.07:31:08.80#ibcon#enter sib2, iclass 22, count 0 2006.217.07:31:08.80#ibcon#flushed, iclass 22, count 0 2006.217.07:31:08.80#ibcon#about to write, iclass 22, count 0 2006.217.07:31:08.80#ibcon#wrote, iclass 22, count 0 2006.217.07:31:08.80#ibcon#about to read 3, iclass 22, count 0 2006.217.07:31:08.84#ibcon#read 3, iclass 22, count 0 2006.217.07:31:08.84#ibcon#about to read 4, iclass 22, count 0 2006.217.07:31:08.84#ibcon#read 4, iclass 22, count 0 2006.217.07:31:08.84#ibcon#about to read 5, iclass 22, count 0 2006.217.07:31:08.84#ibcon#read 5, iclass 22, count 0 2006.217.07:31:08.84#ibcon#about to read 6, iclass 22, count 0 2006.217.07:31:08.84#ibcon#read 6, iclass 22, count 0 2006.217.07:31:08.84#ibcon#end of sib2, iclass 22, count 0 2006.217.07:31:08.84#ibcon#*after write, iclass 22, count 0 2006.217.07:31:08.84#ibcon#*before return 0, iclass 22, count 0 2006.217.07:31:08.84#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.217.07:31:08.84#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.217.07:31:08.84#ibcon#about to clear, iclass 22 cls_cnt 0 2006.217.07:31:08.84#ibcon#cleared, iclass 22 cls_cnt 0 2006.217.07:31:08.84$vc4f8/va=6,6 2006.217.07:31:08.84#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.217.07:31:08.84#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.217.07:31:08.84#ibcon#ireg 11 cls_cnt 2 2006.217.07:31:08.84#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.217.07:31:08.90#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.217.07:31:08.90#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.217.07:31:08.90#ibcon#enter wrdev, iclass 24, count 2 2006.217.07:31:08.90#ibcon#first serial, iclass 24, count 2 2006.217.07:31:08.90#ibcon#enter sib2, iclass 24, count 2 2006.217.07:31:08.90#ibcon#flushed, iclass 24, count 2 2006.217.07:31:08.90#ibcon#about to write, iclass 24, count 2 2006.217.07:31:08.90#ibcon#wrote, iclass 24, count 2 2006.217.07:31:08.90#ibcon#about to read 3, iclass 24, count 2 2006.217.07:31:08.92#ibcon#read 3, iclass 24, count 2 2006.217.07:31:08.92#ibcon#about to read 4, iclass 24, count 2 2006.217.07:31:08.92#ibcon#read 4, iclass 24, count 2 2006.217.07:31:08.92#ibcon#about to read 5, iclass 24, count 2 2006.217.07:31:08.92#ibcon#read 5, iclass 24, count 2 2006.217.07:31:08.92#ibcon#about to read 6, iclass 24, count 2 2006.217.07:31:08.92#ibcon#read 6, iclass 24, count 2 2006.217.07:31:08.92#ibcon#end of sib2, iclass 24, count 2 2006.217.07:31:08.92#ibcon#*mode == 0, iclass 24, count 2 2006.217.07:31:08.92#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.217.07:31:08.92#ibcon#[25=AT06-06\r\n] 2006.217.07:31:08.92#ibcon#*before write, iclass 24, count 2 2006.217.07:31:08.92#ibcon#enter sib2, iclass 24, count 2 2006.217.07:31:08.92#ibcon#flushed, iclass 24, count 2 2006.217.07:31:08.92#ibcon#about to write, iclass 24, count 2 2006.217.07:31:08.92#ibcon#wrote, iclass 24, count 2 2006.217.07:31:08.92#ibcon#about to read 3, iclass 24, count 2 2006.217.07:31:08.95#ibcon#read 3, iclass 24, count 2 2006.217.07:31:08.95#ibcon#about to read 4, iclass 24, count 2 2006.217.07:31:08.95#ibcon#read 4, iclass 24, count 2 2006.217.07:31:08.95#ibcon#about to read 5, iclass 24, count 2 2006.217.07:31:08.95#ibcon#read 5, iclass 24, count 2 2006.217.07:31:08.95#ibcon#about to read 6, iclass 24, count 2 2006.217.07:31:08.95#ibcon#read 6, iclass 24, count 2 2006.217.07:31:08.95#ibcon#end of sib2, iclass 24, count 2 2006.217.07:31:08.95#ibcon#*after write, iclass 24, count 2 2006.217.07:31:08.95#ibcon#*before return 0, iclass 24, count 2 2006.217.07:31:08.95#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.217.07:31:08.95#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.217.07:31:08.95#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.217.07:31:08.95#ibcon#ireg 7 cls_cnt 0 2006.217.07:31:08.95#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.217.07:31:09.07#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.217.07:31:09.07#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.217.07:31:09.07#ibcon#enter wrdev, iclass 24, count 0 2006.217.07:31:09.07#ibcon#first serial, iclass 24, count 0 2006.217.07:31:09.07#ibcon#enter sib2, iclass 24, count 0 2006.217.07:31:09.07#ibcon#flushed, iclass 24, count 0 2006.217.07:31:09.07#ibcon#about to write, iclass 24, count 0 2006.217.07:31:09.07#ibcon#wrote, iclass 24, count 0 2006.217.07:31:09.07#ibcon#about to read 3, iclass 24, count 0 2006.217.07:31:09.09#ibcon#read 3, iclass 24, count 0 2006.217.07:31:09.09#ibcon#about to read 4, iclass 24, count 0 2006.217.07:31:09.09#ibcon#read 4, iclass 24, count 0 2006.217.07:31:09.09#ibcon#about to read 5, iclass 24, count 0 2006.217.07:31:09.09#ibcon#read 5, iclass 24, count 0 2006.217.07:31:09.09#ibcon#about to read 6, iclass 24, count 0 2006.217.07:31:09.09#ibcon#read 6, iclass 24, count 0 2006.217.07:31:09.09#ibcon#end of sib2, iclass 24, count 0 2006.217.07:31:09.09#ibcon#*mode == 0, iclass 24, count 0 2006.217.07:31:09.09#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.217.07:31:09.09#ibcon#[25=USB\r\n] 2006.217.07:31:09.09#ibcon#*before write, iclass 24, count 0 2006.217.07:31:09.09#ibcon#enter sib2, iclass 24, count 0 2006.217.07:31:09.09#ibcon#flushed, iclass 24, count 0 2006.217.07:31:09.09#ibcon#about to write, iclass 24, count 0 2006.217.07:31:09.09#ibcon#wrote, iclass 24, count 0 2006.217.07:31:09.09#ibcon#about to read 3, iclass 24, count 0 2006.217.07:31:09.12#ibcon#read 3, iclass 24, count 0 2006.217.07:31:09.12#ibcon#about to read 4, iclass 24, count 0 2006.217.07:31:09.12#ibcon#read 4, iclass 24, count 0 2006.217.07:31:09.12#ibcon#about to read 5, iclass 24, count 0 2006.217.07:31:09.12#ibcon#read 5, iclass 24, count 0 2006.217.07:31:09.12#ibcon#about to read 6, iclass 24, count 0 2006.217.07:31:09.12#ibcon#read 6, iclass 24, count 0 2006.217.07:31:09.12#ibcon#end of sib2, iclass 24, count 0 2006.217.07:31:09.12#ibcon#*after write, iclass 24, count 0 2006.217.07:31:09.12#ibcon#*before return 0, iclass 24, count 0 2006.217.07:31:09.12#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.217.07:31:09.12#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.217.07:31:09.12#ibcon#about to clear, iclass 24 cls_cnt 0 2006.217.07:31:09.12#ibcon#cleared, iclass 24 cls_cnt 0 2006.217.07:31:09.12$vc4f8/valo=7,832.99 2006.217.07:31:09.12#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.217.07:31:09.12#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.217.07:31:09.12#ibcon#ireg 17 cls_cnt 0 2006.217.07:31:09.12#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.217.07:31:09.12#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.217.07:31:09.12#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.217.07:31:09.12#ibcon#enter wrdev, iclass 26, count 0 2006.217.07:31:09.12#ibcon#first serial, iclass 26, count 0 2006.217.07:31:09.12#ibcon#enter sib2, iclass 26, count 0 2006.217.07:31:09.12#ibcon#flushed, iclass 26, count 0 2006.217.07:31:09.12#ibcon#about to write, iclass 26, count 0 2006.217.07:31:09.12#ibcon#wrote, iclass 26, count 0 2006.217.07:31:09.12#ibcon#about to read 3, iclass 26, count 0 2006.217.07:31:09.14#ibcon#read 3, iclass 26, count 0 2006.217.07:31:09.14#ibcon#about to read 4, iclass 26, count 0 2006.217.07:31:09.14#ibcon#read 4, iclass 26, count 0 2006.217.07:31:09.14#ibcon#about to read 5, iclass 26, count 0 2006.217.07:31:09.14#ibcon#read 5, iclass 26, count 0 2006.217.07:31:09.14#ibcon#about to read 6, iclass 26, count 0 2006.217.07:31:09.14#ibcon#read 6, iclass 26, count 0 2006.217.07:31:09.14#ibcon#end of sib2, iclass 26, count 0 2006.217.07:31:09.14#ibcon#*mode == 0, iclass 26, count 0 2006.217.07:31:09.14#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.217.07:31:09.14#ibcon#[26=FRQ=07,832.99\r\n] 2006.217.07:31:09.14#ibcon#*before write, iclass 26, count 0 2006.217.07:31:09.14#ibcon#enter sib2, iclass 26, count 0 2006.217.07:31:09.14#ibcon#flushed, iclass 26, count 0 2006.217.07:31:09.14#ibcon#about to write, iclass 26, count 0 2006.217.07:31:09.14#ibcon#wrote, iclass 26, count 0 2006.217.07:31:09.14#ibcon#about to read 3, iclass 26, count 0 2006.217.07:31:09.18#ibcon#read 3, iclass 26, count 0 2006.217.07:31:09.18#ibcon#about to read 4, iclass 26, count 0 2006.217.07:31:09.18#ibcon#read 4, iclass 26, count 0 2006.217.07:31:09.18#ibcon#about to read 5, iclass 26, count 0 2006.217.07:31:09.18#ibcon#read 5, iclass 26, count 0 2006.217.07:31:09.18#ibcon#about to read 6, iclass 26, count 0 2006.217.07:31:09.18#ibcon#read 6, iclass 26, count 0 2006.217.07:31:09.18#ibcon#end of sib2, iclass 26, count 0 2006.217.07:31:09.18#ibcon#*after write, iclass 26, count 0 2006.217.07:31:09.18#ibcon#*before return 0, iclass 26, count 0 2006.217.07:31:09.18#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.217.07:31:09.18#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.217.07:31:09.18#ibcon#about to clear, iclass 26 cls_cnt 0 2006.217.07:31:09.18#ibcon#cleared, iclass 26 cls_cnt 0 2006.217.07:31:09.18$vc4f8/va=7,6 2006.217.07:31:09.18#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.217.07:31:09.18#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.217.07:31:09.18#ibcon#ireg 11 cls_cnt 2 2006.217.07:31:09.18#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.217.07:31:09.24#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.217.07:31:09.24#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.217.07:31:09.24#ibcon#enter wrdev, iclass 28, count 2 2006.217.07:31:09.24#ibcon#first serial, iclass 28, count 2 2006.217.07:31:09.24#ibcon#enter sib2, iclass 28, count 2 2006.217.07:31:09.24#ibcon#flushed, iclass 28, count 2 2006.217.07:31:09.24#ibcon#about to write, iclass 28, count 2 2006.217.07:31:09.24#ibcon#wrote, iclass 28, count 2 2006.217.07:31:09.24#ibcon#about to read 3, iclass 28, count 2 2006.217.07:31:09.26#ibcon#read 3, iclass 28, count 2 2006.217.07:31:09.26#ibcon#about to read 4, iclass 28, count 2 2006.217.07:31:09.26#ibcon#read 4, iclass 28, count 2 2006.217.07:31:09.26#ibcon#about to read 5, iclass 28, count 2 2006.217.07:31:09.26#ibcon#read 5, iclass 28, count 2 2006.217.07:31:09.26#ibcon#about to read 6, iclass 28, count 2 2006.217.07:31:09.26#ibcon#read 6, iclass 28, count 2 2006.217.07:31:09.26#ibcon#end of sib2, iclass 28, count 2 2006.217.07:31:09.26#ibcon#*mode == 0, iclass 28, count 2 2006.217.07:31:09.26#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.217.07:31:09.26#ibcon#[25=AT07-06\r\n] 2006.217.07:31:09.26#ibcon#*before write, iclass 28, count 2 2006.217.07:31:09.26#ibcon#enter sib2, iclass 28, count 2 2006.217.07:31:09.26#ibcon#flushed, iclass 28, count 2 2006.217.07:31:09.26#ibcon#about to write, iclass 28, count 2 2006.217.07:31:09.26#ibcon#wrote, iclass 28, count 2 2006.217.07:31:09.26#ibcon#about to read 3, iclass 28, count 2 2006.217.07:31:09.29#ibcon#read 3, iclass 28, count 2 2006.217.07:31:09.29#ibcon#about to read 4, iclass 28, count 2 2006.217.07:31:09.29#ibcon#read 4, iclass 28, count 2 2006.217.07:31:09.29#ibcon#about to read 5, iclass 28, count 2 2006.217.07:31:09.29#ibcon#read 5, iclass 28, count 2 2006.217.07:31:09.29#ibcon#about to read 6, iclass 28, count 2 2006.217.07:31:09.29#ibcon#read 6, iclass 28, count 2 2006.217.07:31:09.29#ibcon#end of sib2, iclass 28, count 2 2006.217.07:31:09.29#ibcon#*after write, iclass 28, count 2 2006.217.07:31:09.29#ibcon#*before return 0, iclass 28, count 2 2006.217.07:31:09.29#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.217.07:31:09.29#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.217.07:31:09.29#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.217.07:31:09.29#ibcon#ireg 7 cls_cnt 0 2006.217.07:31:09.29#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.217.07:31:09.41#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.217.07:31:09.41#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.217.07:31:09.41#ibcon#enter wrdev, iclass 28, count 0 2006.217.07:31:09.41#ibcon#first serial, iclass 28, count 0 2006.217.07:31:09.41#ibcon#enter sib2, iclass 28, count 0 2006.217.07:31:09.41#ibcon#flushed, iclass 28, count 0 2006.217.07:31:09.41#ibcon#about to write, iclass 28, count 0 2006.217.07:31:09.41#ibcon#wrote, iclass 28, count 0 2006.217.07:31:09.41#ibcon#about to read 3, iclass 28, count 0 2006.217.07:31:09.43#ibcon#read 3, iclass 28, count 0 2006.217.07:31:09.43#ibcon#about to read 4, iclass 28, count 0 2006.217.07:31:09.43#ibcon#read 4, iclass 28, count 0 2006.217.07:31:09.43#ibcon#about to read 5, iclass 28, count 0 2006.217.07:31:09.43#ibcon#read 5, iclass 28, count 0 2006.217.07:31:09.43#ibcon#about to read 6, iclass 28, count 0 2006.217.07:31:09.43#ibcon#read 6, iclass 28, count 0 2006.217.07:31:09.43#ibcon#end of sib2, iclass 28, count 0 2006.217.07:31:09.43#ibcon#*mode == 0, iclass 28, count 0 2006.217.07:31:09.43#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.217.07:31:09.43#ibcon#[25=USB\r\n] 2006.217.07:31:09.43#ibcon#*before write, iclass 28, count 0 2006.217.07:31:09.43#ibcon#enter sib2, iclass 28, count 0 2006.217.07:31:09.43#ibcon#flushed, iclass 28, count 0 2006.217.07:31:09.43#ibcon#about to write, iclass 28, count 0 2006.217.07:31:09.43#ibcon#wrote, iclass 28, count 0 2006.217.07:31:09.43#ibcon#about to read 3, iclass 28, count 0 2006.217.07:31:09.46#ibcon#read 3, iclass 28, count 0 2006.217.07:31:09.46#ibcon#about to read 4, iclass 28, count 0 2006.217.07:31:09.46#ibcon#read 4, iclass 28, count 0 2006.217.07:31:09.46#ibcon#about to read 5, iclass 28, count 0 2006.217.07:31:09.46#ibcon#read 5, iclass 28, count 0 2006.217.07:31:09.46#ibcon#about to read 6, iclass 28, count 0 2006.217.07:31:09.46#ibcon#read 6, iclass 28, count 0 2006.217.07:31:09.46#ibcon#end of sib2, iclass 28, count 0 2006.217.07:31:09.46#ibcon#*after write, iclass 28, count 0 2006.217.07:31:09.46#ibcon#*before return 0, iclass 28, count 0 2006.217.07:31:09.46#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.217.07:31:09.46#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.217.07:31:09.46#ibcon#about to clear, iclass 28 cls_cnt 0 2006.217.07:31:09.46#ibcon#cleared, iclass 28 cls_cnt 0 2006.217.07:31:09.46$vc4f8/valo=8,852.99 2006.217.07:31:09.46#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.217.07:31:09.46#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.217.07:31:09.46#ibcon#ireg 17 cls_cnt 0 2006.217.07:31:09.46#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.217.07:31:09.46#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.217.07:31:09.46#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.217.07:31:09.46#ibcon#enter wrdev, iclass 30, count 0 2006.217.07:31:09.46#ibcon#first serial, iclass 30, count 0 2006.217.07:31:09.46#ibcon#enter sib2, iclass 30, count 0 2006.217.07:31:09.46#ibcon#flushed, iclass 30, count 0 2006.217.07:31:09.46#ibcon#about to write, iclass 30, count 0 2006.217.07:31:09.46#ibcon#wrote, iclass 30, count 0 2006.217.07:31:09.46#ibcon#about to read 3, iclass 30, count 0 2006.217.07:31:09.48#ibcon#read 3, iclass 30, count 0 2006.217.07:31:09.48#ibcon#about to read 4, iclass 30, count 0 2006.217.07:31:09.48#ibcon#read 4, iclass 30, count 0 2006.217.07:31:09.48#ibcon#about to read 5, iclass 30, count 0 2006.217.07:31:09.48#ibcon#read 5, iclass 30, count 0 2006.217.07:31:09.48#ibcon#about to read 6, iclass 30, count 0 2006.217.07:31:09.48#ibcon#read 6, iclass 30, count 0 2006.217.07:31:09.48#ibcon#end of sib2, iclass 30, count 0 2006.217.07:31:09.48#ibcon#*mode == 0, iclass 30, count 0 2006.217.07:31:09.48#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.217.07:31:09.48#ibcon#[26=FRQ=08,852.99\r\n] 2006.217.07:31:09.48#ibcon#*before write, iclass 30, count 0 2006.217.07:31:09.48#ibcon#enter sib2, iclass 30, count 0 2006.217.07:31:09.48#ibcon#flushed, iclass 30, count 0 2006.217.07:31:09.48#ibcon#about to write, iclass 30, count 0 2006.217.07:31:09.48#ibcon#wrote, iclass 30, count 0 2006.217.07:31:09.48#ibcon#about to read 3, iclass 30, count 0 2006.217.07:31:09.52#ibcon#read 3, iclass 30, count 0 2006.217.07:31:09.52#ibcon#about to read 4, iclass 30, count 0 2006.217.07:31:09.52#ibcon#read 4, iclass 30, count 0 2006.217.07:31:09.52#ibcon#about to read 5, iclass 30, count 0 2006.217.07:31:09.52#ibcon#read 5, iclass 30, count 0 2006.217.07:31:09.52#ibcon#about to read 6, iclass 30, count 0 2006.217.07:31:09.52#ibcon#read 6, iclass 30, count 0 2006.217.07:31:09.52#ibcon#end of sib2, iclass 30, count 0 2006.217.07:31:09.52#ibcon#*after write, iclass 30, count 0 2006.217.07:31:09.52#ibcon#*before return 0, iclass 30, count 0 2006.217.07:31:09.52#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.217.07:31:09.52#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.217.07:31:09.52#ibcon#about to clear, iclass 30 cls_cnt 0 2006.217.07:31:09.52#ibcon#cleared, iclass 30 cls_cnt 0 2006.217.07:31:09.52$vc4f8/va=8,7 2006.217.07:31:09.52#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.217.07:31:09.52#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.217.07:31:09.52#ibcon#ireg 11 cls_cnt 2 2006.217.07:31:09.52#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.217.07:31:09.58#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.217.07:31:09.58#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.217.07:31:09.58#ibcon#enter wrdev, iclass 32, count 2 2006.217.07:31:09.58#ibcon#first serial, iclass 32, count 2 2006.217.07:31:09.58#ibcon#enter sib2, iclass 32, count 2 2006.217.07:31:09.58#ibcon#flushed, iclass 32, count 2 2006.217.07:31:09.58#ibcon#about to write, iclass 32, count 2 2006.217.07:31:09.58#ibcon#wrote, iclass 32, count 2 2006.217.07:31:09.58#ibcon#about to read 3, iclass 32, count 2 2006.217.07:31:09.60#ibcon#read 3, iclass 32, count 2 2006.217.07:31:09.60#ibcon#about to read 4, iclass 32, count 2 2006.217.07:31:09.60#ibcon#read 4, iclass 32, count 2 2006.217.07:31:09.60#ibcon#about to read 5, iclass 32, count 2 2006.217.07:31:09.60#ibcon#read 5, iclass 32, count 2 2006.217.07:31:09.60#ibcon#about to read 6, iclass 32, count 2 2006.217.07:31:09.60#ibcon#read 6, iclass 32, count 2 2006.217.07:31:09.60#ibcon#end of sib2, iclass 32, count 2 2006.217.07:31:09.60#ibcon#*mode == 0, iclass 32, count 2 2006.217.07:31:09.60#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.217.07:31:09.60#ibcon#[25=AT08-07\r\n] 2006.217.07:31:09.60#ibcon#*before write, iclass 32, count 2 2006.217.07:31:09.60#ibcon#enter sib2, iclass 32, count 2 2006.217.07:31:09.60#ibcon#flushed, iclass 32, count 2 2006.217.07:31:09.60#ibcon#about to write, iclass 32, count 2 2006.217.07:31:09.60#ibcon#wrote, iclass 32, count 2 2006.217.07:31:09.60#ibcon#about to read 3, iclass 32, count 2 2006.217.07:31:09.63#ibcon#read 3, iclass 32, count 2 2006.217.07:31:09.63#ibcon#about to read 4, iclass 32, count 2 2006.217.07:31:09.63#ibcon#read 4, iclass 32, count 2 2006.217.07:31:09.63#ibcon#about to read 5, iclass 32, count 2 2006.217.07:31:09.63#ibcon#read 5, iclass 32, count 2 2006.217.07:31:09.63#ibcon#about to read 6, iclass 32, count 2 2006.217.07:31:09.63#ibcon#read 6, iclass 32, count 2 2006.217.07:31:09.63#ibcon#end of sib2, iclass 32, count 2 2006.217.07:31:09.63#ibcon#*after write, iclass 32, count 2 2006.217.07:31:09.63#ibcon#*before return 0, iclass 32, count 2 2006.217.07:31:09.63#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.217.07:31:09.63#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.217.07:31:09.63#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.217.07:31:09.63#ibcon#ireg 7 cls_cnt 0 2006.217.07:31:09.63#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.217.07:31:09.75#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.217.07:31:09.75#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.217.07:31:09.75#ibcon#enter wrdev, iclass 32, count 0 2006.217.07:31:09.75#ibcon#first serial, iclass 32, count 0 2006.217.07:31:09.75#ibcon#enter sib2, iclass 32, count 0 2006.217.07:31:09.75#ibcon#flushed, iclass 32, count 0 2006.217.07:31:09.75#ibcon#about to write, iclass 32, count 0 2006.217.07:31:09.75#ibcon#wrote, iclass 32, count 0 2006.217.07:31:09.75#ibcon#about to read 3, iclass 32, count 0 2006.217.07:31:09.77#ibcon#read 3, iclass 32, count 0 2006.217.07:31:09.77#ibcon#about to read 4, iclass 32, count 0 2006.217.07:31:09.77#ibcon#read 4, iclass 32, count 0 2006.217.07:31:09.77#ibcon#about to read 5, iclass 32, count 0 2006.217.07:31:09.77#ibcon#read 5, iclass 32, count 0 2006.217.07:31:09.77#ibcon#about to read 6, iclass 32, count 0 2006.217.07:31:09.77#ibcon#read 6, iclass 32, count 0 2006.217.07:31:09.77#ibcon#end of sib2, iclass 32, count 0 2006.217.07:31:09.77#ibcon#*mode == 0, iclass 32, count 0 2006.217.07:31:09.77#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.217.07:31:09.77#ibcon#[25=USB\r\n] 2006.217.07:31:09.77#ibcon#*before write, iclass 32, count 0 2006.217.07:31:09.77#ibcon#enter sib2, iclass 32, count 0 2006.217.07:31:09.77#ibcon#flushed, iclass 32, count 0 2006.217.07:31:09.77#ibcon#about to write, iclass 32, count 0 2006.217.07:31:09.77#ibcon#wrote, iclass 32, count 0 2006.217.07:31:09.77#ibcon#about to read 3, iclass 32, count 0 2006.217.07:31:09.80#ibcon#read 3, iclass 32, count 0 2006.217.07:31:09.80#ibcon#about to read 4, iclass 32, count 0 2006.217.07:31:09.80#ibcon#read 4, iclass 32, count 0 2006.217.07:31:09.80#ibcon#about to read 5, iclass 32, count 0 2006.217.07:31:09.80#ibcon#read 5, iclass 32, count 0 2006.217.07:31:09.80#ibcon#about to read 6, iclass 32, count 0 2006.217.07:31:09.80#ibcon#read 6, iclass 32, count 0 2006.217.07:31:09.80#ibcon#end of sib2, iclass 32, count 0 2006.217.07:31:09.80#ibcon#*after write, iclass 32, count 0 2006.217.07:31:09.80#ibcon#*before return 0, iclass 32, count 0 2006.217.07:31:09.80#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.217.07:31:09.80#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.217.07:31:09.80#ibcon#about to clear, iclass 32 cls_cnt 0 2006.217.07:31:09.80#ibcon#cleared, iclass 32 cls_cnt 0 2006.217.07:31:09.80$vc4f8/vblo=1,632.99 2006.217.07:31:09.80#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.217.07:31:09.80#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.217.07:31:09.80#ibcon#ireg 17 cls_cnt 0 2006.217.07:31:09.80#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.217.07:31:09.80#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.217.07:31:09.80#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.217.07:31:09.80#ibcon#enter wrdev, iclass 34, count 0 2006.217.07:31:09.80#ibcon#first serial, iclass 34, count 0 2006.217.07:31:09.80#ibcon#enter sib2, iclass 34, count 0 2006.217.07:31:09.80#ibcon#flushed, iclass 34, count 0 2006.217.07:31:09.80#ibcon#about to write, iclass 34, count 0 2006.217.07:31:09.80#ibcon#wrote, iclass 34, count 0 2006.217.07:31:09.80#ibcon#about to read 3, iclass 34, count 0 2006.217.07:31:09.82#ibcon#read 3, iclass 34, count 0 2006.217.07:31:09.82#ibcon#about to read 4, iclass 34, count 0 2006.217.07:31:09.82#ibcon#read 4, iclass 34, count 0 2006.217.07:31:09.82#ibcon#about to read 5, iclass 34, count 0 2006.217.07:31:09.82#ibcon#read 5, iclass 34, count 0 2006.217.07:31:09.82#ibcon#about to read 6, iclass 34, count 0 2006.217.07:31:09.82#ibcon#read 6, iclass 34, count 0 2006.217.07:31:09.82#ibcon#end of sib2, iclass 34, count 0 2006.217.07:31:09.82#ibcon#*mode == 0, iclass 34, count 0 2006.217.07:31:09.82#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.217.07:31:09.82#ibcon#[28=FRQ=01,632.99\r\n] 2006.217.07:31:09.82#ibcon#*before write, iclass 34, count 0 2006.217.07:31:09.82#ibcon#enter sib2, iclass 34, count 0 2006.217.07:31:09.82#ibcon#flushed, iclass 34, count 0 2006.217.07:31:09.82#ibcon#about to write, iclass 34, count 0 2006.217.07:31:09.82#ibcon#wrote, iclass 34, count 0 2006.217.07:31:09.82#ibcon#about to read 3, iclass 34, count 0 2006.217.07:31:09.87#ibcon#read 3, iclass 34, count 0 2006.217.07:31:09.87#ibcon#about to read 4, iclass 34, count 0 2006.217.07:31:09.87#ibcon#read 4, iclass 34, count 0 2006.217.07:31:09.87#ibcon#about to read 5, iclass 34, count 0 2006.217.07:31:09.87#ibcon#read 5, iclass 34, count 0 2006.217.07:31:09.87#ibcon#about to read 6, iclass 34, count 0 2006.217.07:31:09.87#ibcon#read 6, iclass 34, count 0 2006.217.07:31:09.87#ibcon#end of sib2, iclass 34, count 0 2006.217.07:31:09.87#ibcon#*after write, iclass 34, count 0 2006.217.07:31:09.87#ibcon#*before return 0, iclass 34, count 0 2006.217.07:31:09.87#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.217.07:31:09.87#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.217.07:31:09.87#ibcon#about to clear, iclass 34 cls_cnt 0 2006.217.07:31:09.87#ibcon#cleared, iclass 34 cls_cnt 0 2006.217.07:31:09.87$vc4f8/vb=1,4 2006.217.07:31:09.87#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.217.07:31:09.87#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.217.07:31:09.87#ibcon#ireg 11 cls_cnt 2 2006.217.07:31:09.87#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.217.07:31:09.87#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.217.07:31:09.87#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.217.07:31:09.87#ibcon#enter wrdev, iclass 36, count 2 2006.217.07:31:09.87#ibcon#first serial, iclass 36, count 2 2006.217.07:31:09.87#ibcon#enter sib2, iclass 36, count 2 2006.217.07:31:09.87#ibcon#flushed, iclass 36, count 2 2006.217.07:31:09.87#ibcon#about to write, iclass 36, count 2 2006.217.07:31:09.87#ibcon#wrote, iclass 36, count 2 2006.217.07:31:09.87#ibcon#about to read 3, iclass 36, count 2 2006.217.07:31:09.89#ibcon#read 3, iclass 36, count 2 2006.217.07:31:09.89#ibcon#about to read 4, iclass 36, count 2 2006.217.07:31:09.89#ibcon#read 4, iclass 36, count 2 2006.217.07:31:09.89#ibcon#about to read 5, iclass 36, count 2 2006.217.07:31:09.89#ibcon#read 5, iclass 36, count 2 2006.217.07:31:09.89#ibcon#about to read 6, iclass 36, count 2 2006.217.07:31:09.89#ibcon#read 6, iclass 36, count 2 2006.217.07:31:09.89#ibcon#end of sib2, iclass 36, count 2 2006.217.07:31:09.89#ibcon#*mode == 0, iclass 36, count 2 2006.217.07:31:09.89#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.217.07:31:09.89#ibcon#[27=AT01-04\r\n] 2006.217.07:31:09.89#ibcon#*before write, iclass 36, count 2 2006.217.07:31:09.89#ibcon#enter sib2, iclass 36, count 2 2006.217.07:31:09.89#ibcon#flushed, iclass 36, count 2 2006.217.07:31:09.89#ibcon#about to write, iclass 36, count 2 2006.217.07:31:09.89#ibcon#wrote, iclass 36, count 2 2006.217.07:31:09.89#ibcon#about to read 3, iclass 36, count 2 2006.217.07:31:09.92#ibcon#read 3, iclass 36, count 2 2006.217.07:31:09.92#ibcon#about to read 4, iclass 36, count 2 2006.217.07:31:09.92#ibcon#read 4, iclass 36, count 2 2006.217.07:31:09.92#ibcon#about to read 5, iclass 36, count 2 2006.217.07:31:09.92#ibcon#read 5, iclass 36, count 2 2006.217.07:31:09.92#ibcon#about to read 6, iclass 36, count 2 2006.217.07:31:09.92#ibcon#read 6, iclass 36, count 2 2006.217.07:31:09.92#ibcon#end of sib2, iclass 36, count 2 2006.217.07:31:09.92#ibcon#*after write, iclass 36, count 2 2006.217.07:31:09.92#ibcon#*before return 0, iclass 36, count 2 2006.217.07:31:09.92#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.217.07:31:09.92#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.217.07:31:09.92#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.217.07:31:09.92#ibcon#ireg 7 cls_cnt 0 2006.217.07:31:09.92#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.217.07:31:10.04#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.217.07:31:10.04#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.217.07:31:10.04#ibcon#enter wrdev, iclass 36, count 0 2006.217.07:31:10.04#ibcon#first serial, iclass 36, count 0 2006.217.07:31:10.04#ibcon#enter sib2, iclass 36, count 0 2006.217.07:31:10.04#ibcon#flushed, iclass 36, count 0 2006.217.07:31:10.04#ibcon#about to write, iclass 36, count 0 2006.217.07:31:10.04#ibcon#wrote, iclass 36, count 0 2006.217.07:31:10.04#ibcon#about to read 3, iclass 36, count 0 2006.217.07:31:10.06#ibcon#read 3, iclass 36, count 0 2006.217.07:31:10.06#ibcon#about to read 4, iclass 36, count 0 2006.217.07:31:10.06#ibcon#read 4, iclass 36, count 0 2006.217.07:31:10.06#ibcon#about to read 5, iclass 36, count 0 2006.217.07:31:10.06#ibcon#read 5, iclass 36, count 0 2006.217.07:31:10.06#ibcon#about to read 6, iclass 36, count 0 2006.217.07:31:10.06#ibcon#read 6, iclass 36, count 0 2006.217.07:31:10.06#ibcon#end of sib2, iclass 36, count 0 2006.217.07:31:10.06#ibcon#*mode == 0, iclass 36, count 0 2006.217.07:31:10.06#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.217.07:31:10.06#ibcon#[27=USB\r\n] 2006.217.07:31:10.06#ibcon#*before write, iclass 36, count 0 2006.217.07:31:10.06#ibcon#enter sib2, iclass 36, count 0 2006.217.07:31:10.06#ibcon#flushed, iclass 36, count 0 2006.217.07:31:10.06#ibcon#about to write, iclass 36, count 0 2006.217.07:31:10.06#ibcon#wrote, iclass 36, count 0 2006.217.07:31:10.06#ibcon#about to read 3, iclass 36, count 0 2006.217.07:31:10.09#ibcon#read 3, iclass 36, count 0 2006.217.07:31:10.09#ibcon#about to read 4, iclass 36, count 0 2006.217.07:31:10.09#ibcon#read 4, iclass 36, count 0 2006.217.07:31:10.09#ibcon#about to read 5, iclass 36, count 0 2006.217.07:31:10.09#ibcon#read 5, iclass 36, count 0 2006.217.07:31:10.09#ibcon#about to read 6, iclass 36, count 0 2006.217.07:31:10.09#ibcon#read 6, iclass 36, count 0 2006.217.07:31:10.09#ibcon#end of sib2, iclass 36, count 0 2006.217.07:31:10.09#ibcon#*after write, iclass 36, count 0 2006.217.07:31:10.09#ibcon#*before return 0, iclass 36, count 0 2006.217.07:31:10.09#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.217.07:31:10.09#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.217.07:31:10.09#ibcon#about to clear, iclass 36 cls_cnt 0 2006.217.07:31:10.09#ibcon#cleared, iclass 36 cls_cnt 0 2006.217.07:31:10.09$vc4f8/vblo=2,640.99 2006.217.07:31:10.09#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.217.07:31:10.09#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.217.07:31:10.09#ibcon#ireg 17 cls_cnt 0 2006.217.07:31:10.09#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.217.07:31:10.09#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.217.07:31:10.09#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.217.07:31:10.09#ibcon#enter wrdev, iclass 38, count 0 2006.217.07:31:10.09#ibcon#first serial, iclass 38, count 0 2006.217.07:31:10.09#ibcon#enter sib2, iclass 38, count 0 2006.217.07:31:10.09#ibcon#flushed, iclass 38, count 0 2006.217.07:31:10.09#ibcon#about to write, iclass 38, count 0 2006.217.07:31:10.09#ibcon#wrote, iclass 38, count 0 2006.217.07:31:10.09#ibcon#about to read 3, iclass 38, count 0 2006.217.07:31:10.11#ibcon#read 3, iclass 38, count 0 2006.217.07:31:10.11#ibcon#about to read 4, iclass 38, count 0 2006.217.07:31:10.11#ibcon#read 4, iclass 38, count 0 2006.217.07:31:10.11#ibcon#about to read 5, iclass 38, count 0 2006.217.07:31:10.11#ibcon#read 5, iclass 38, count 0 2006.217.07:31:10.11#ibcon#about to read 6, iclass 38, count 0 2006.217.07:31:10.11#ibcon#read 6, iclass 38, count 0 2006.217.07:31:10.11#ibcon#end of sib2, iclass 38, count 0 2006.217.07:31:10.11#ibcon#*mode == 0, iclass 38, count 0 2006.217.07:31:10.11#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.217.07:31:10.11#ibcon#[28=FRQ=02,640.99\r\n] 2006.217.07:31:10.11#ibcon#*before write, iclass 38, count 0 2006.217.07:31:10.11#ibcon#enter sib2, iclass 38, count 0 2006.217.07:31:10.11#ibcon#flushed, iclass 38, count 0 2006.217.07:31:10.11#ibcon#about to write, iclass 38, count 0 2006.217.07:31:10.11#ibcon#wrote, iclass 38, count 0 2006.217.07:31:10.11#ibcon#about to read 3, iclass 38, count 0 2006.217.07:31:10.15#ibcon#read 3, iclass 38, count 0 2006.217.07:31:10.15#ibcon#about to read 4, iclass 38, count 0 2006.217.07:31:10.15#ibcon#read 4, iclass 38, count 0 2006.217.07:31:10.15#ibcon#about to read 5, iclass 38, count 0 2006.217.07:31:10.15#ibcon#read 5, iclass 38, count 0 2006.217.07:31:10.15#ibcon#about to read 6, iclass 38, count 0 2006.217.07:31:10.15#ibcon#read 6, iclass 38, count 0 2006.217.07:31:10.15#ibcon#end of sib2, iclass 38, count 0 2006.217.07:31:10.15#ibcon#*after write, iclass 38, count 0 2006.217.07:31:10.15#ibcon#*before return 0, iclass 38, count 0 2006.217.07:31:10.15#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.217.07:31:10.15#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.217.07:31:10.15#ibcon#about to clear, iclass 38 cls_cnt 0 2006.217.07:31:10.15#ibcon#cleared, iclass 38 cls_cnt 0 2006.217.07:31:10.15$vc4f8/vb=2,4 2006.217.07:31:10.15#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.217.07:31:10.15#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.217.07:31:10.15#ibcon#ireg 11 cls_cnt 2 2006.217.07:31:10.15#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.217.07:31:10.21#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.217.07:31:10.21#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.217.07:31:10.21#ibcon#enter wrdev, iclass 40, count 2 2006.217.07:31:10.21#ibcon#first serial, iclass 40, count 2 2006.217.07:31:10.21#ibcon#enter sib2, iclass 40, count 2 2006.217.07:31:10.21#ibcon#flushed, iclass 40, count 2 2006.217.07:31:10.21#ibcon#about to write, iclass 40, count 2 2006.217.07:31:10.21#ibcon#wrote, iclass 40, count 2 2006.217.07:31:10.21#ibcon#about to read 3, iclass 40, count 2 2006.217.07:31:10.23#ibcon#read 3, iclass 40, count 2 2006.217.07:31:10.23#ibcon#about to read 4, iclass 40, count 2 2006.217.07:31:10.23#ibcon#read 4, iclass 40, count 2 2006.217.07:31:10.23#ibcon#about to read 5, iclass 40, count 2 2006.217.07:31:10.23#ibcon#read 5, iclass 40, count 2 2006.217.07:31:10.23#ibcon#about to read 6, iclass 40, count 2 2006.217.07:31:10.23#ibcon#read 6, iclass 40, count 2 2006.217.07:31:10.23#ibcon#end of sib2, iclass 40, count 2 2006.217.07:31:10.23#ibcon#*mode == 0, iclass 40, count 2 2006.217.07:31:10.23#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.217.07:31:10.23#ibcon#[27=AT02-04\r\n] 2006.217.07:31:10.23#ibcon#*before write, iclass 40, count 2 2006.217.07:31:10.23#ibcon#enter sib2, iclass 40, count 2 2006.217.07:31:10.23#ibcon#flushed, iclass 40, count 2 2006.217.07:31:10.23#ibcon#about to write, iclass 40, count 2 2006.217.07:31:10.23#ibcon#wrote, iclass 40, count 2 2006.217.07:31:10.23#ibcon#about to read 3, iclass 40, count 2 2006.217.07:31:10.26#ibcon#read 3, iclass 40, count 2 2006.217.07:31:10.26#ibcon#about to read 4, iclass 40, count 2 2006.217.07:31:10.26#ibcon#read 4, iclass 40, count 2 2006.217.07:31:10.26#ibcon#about to read 5, iclass 40, count 2 2006.217.07:31:10.26#ibcon#read 5, iclass 40, count 2 2006.217.07:31:10.26#ibcon#about to read 6, iclass 40, count 2 2006.217.07:31:10.26#ibcon#read 6, iclass 40, count 2 2006.217.07:31:10.26#ibcon#end of sib2, iclass 40, count 2 2006.217.07:31:10.26#ibcon#*after write, iclass 40, count 2 2006.217.07:31:10.26#ibcon#*before return 0, iclass 40, count 2 2006.217.07:31:10.26#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.217.07:31:10.26#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.217.07:31:10.26#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.217.07:31:10.26#ibcon#ireg 7 cls_cnt 0 2006.217.07:31:10.26#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.217.07:31:10.38#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.217.07:31:10.38#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.217.07:31:10.38#ibcon#enter wrdev, iclass 40, count 0 2006.217.07:31:10.38#ibcon#first serial, iclass 40, count 0 2006.217.07:31:10.38#ibcon#enter sib2, iclass 40, count 0 2006.217.07:31:10.38#ibcon#flushed, iclass 40, count 0 2006.217.07:31:10.38#ibcon#about to write, iclass 40, count 0 2006.217.07:31:10.38#ibcon#wrote, iclass 40, count 0 2006.217.07:31:10.38#ibcon#about to read 3, iclass 40, count 0 2006.217.07:31:10.40#ibcon#read 3, iclass 40, count 0 2006.217.07:31:10.40#ibcon#about to read 4, iclass 40, count 0 2006.217.07:31:10.40#ibcon#read 4, iclass 40, count 0 2006.217.07:31:10.40#ibcon#about to read 5, iclass 40, count 0 2006.217.07:31:10.40#ibcon#read 5, iclass 40, count 0 2006.217.07:31:10.40#ibcon#about to read 6, iclass 40, count 0 2006.217.07:31:10.40#ibcon#read 6, iclass 40, count 0 2006.217.07:31:10.40#ibcon#end of sib2, iclass 40, count 0 2006.217.07:31:10.40#ibcon#*mode == 0, iclass 40, count 0 2006.217.07:31:10.40#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.217.07:31:10.40#ibcon#[27=USB\r\n] 2006.217.07:31:10.40#ibcon#*before write, iclass 40, count 0 2006.217.07:31:10.40#ibcon#enter sib2, iclass 40, count 0 2006.217.07:31:10.40#ibcon#flushed, iclass 40, count 0 2006.217.07:31:10.40#ibcon#about to write, iclass 40, count 0 2006.217.07:31:10.40#ibcon#wrote, iclass 40, count 0 2006.217.07:31:10.40#ibcon#about to read 3, iclass 40, count 0 2006.217.07:31:10.43#ibcon#read 3, iclass 40, count 0 2006.217.07:31:10.43#ibcon#about to read 4, iclass 40, count 0 2006.217.07:31:10.43#ibcon#read 4, iclass 40, count 0 2006.217.07:31:10.43#ibcon#about to read 5, iclass 40, count 0 2006.217.07:31:10.43#ibcon#read 5, iclass 40, count 0 2006.217.07:31:10.43#ibcon#about to read 6, iclass 40, count 0 2006.217.07:31:10.43#ibcon#read 6, iclass 40, count 0 2006.217.07:31:10.43#ibcon#end of sib2, iclass 40, count 0 2006.217.07:31:10.43#ibcon#*after write, iclass 40, count 0 2006.217.07:31:10.43#ibcon#*before return 0, iclass 40, count 0 2006.217.07:31:10.43#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.217.07:31:10.43#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.217.07:31:10.43#ibcon#about to clear, iclass 40 cls_cnt 0 2006.217.07:31:10.43#ibcon#cleared, iclass 40 cls_cnt 0 2006.217.07:31:10.43$vc4f8/vblo=3,656.99 2006.217.07:31:10.43#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.217.07:31:10.43#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.217.07:31:10.43#ibcon#ireg 17 cls_cnt 0 2006.217.07:31:10.43#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.217.07:31:10.43#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.217.07:31:10.43#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.217.07:31:10.43#ibcon#enter wrdev, iclass 4, count 0 2006.217.07:31:10.43#ibcon#first serial, iclass 4, count 0 2006.217.07:31:10.43#ibcon#enter sib2, iclass 4, count 0 2006.217.07:31:10.43#ibcon#flushed, iclass 4, count 0 2006.217.07:31:10.43#ibcon#about to write, iclass 4, count 0 2006.217.07:31:10.43#ibcon#wrote, iclass 4, count 0 2006.217.07:31:10.43#ibcon#about to read 3, iclass 4, count 0 2006.217.07:31:10.45#ibcon#read 3, iclass 4, count 0 2006.217.07:31:10.45#ibcon#about to read 4, iclass 4, count 0 2006.217.07:31:10.45#ibcon#read 4, iclass 4, count 0 2006.217.07:31:10.45#ibcon#about to read 5, iclass 4, count 0 2006.217.07:31:10.45#ibcon#read 5, iclass 4, count 0 2006.217.07:31:10.45#ibcon#about to read 6, iclass 4, count 0 2006.217.07:31:10.45#ibcon#read 6, iclass 4, count 0 2006.217.07:31:10.45#ibcon#end of sib2, iclass 4, count 0 2006.217.07:31:10.45#ibcon#*mode == 0, iclass 4, count 0 2006.217.07:31:10.45#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.217.07:31:10.45#ibcon#[28=FRQ=03,656.99\r\n] 2006.217.07:31:10.45#ibcon#*before write, iclass 4, count 0 2006.217.07:31:10.45#ibcon#enter sib2, iclass 4, count 0 2006.217.07:31:10.45#ibcon#flushed, iclass 4, count 0 2006.217.07:31:10.45#ibcon#about to write, iclass 4, count 0 2006.217.07:31:10.45#ibcon#wrote, iclass 4, count 0 2006.217.07:31:10.45#ibcon#about to read 3, iclass 4, count 0 2006.217.07:31:10.49#ibcon#read 3, iclass 4, count 0 2006.217.07:31:10.49#ibcon#about to read 4, iclass 4, count 0 2006.217.07:31:10.49#ibcon#read 4, iclass 4, count 0 2006.217.07:31:10.49#ibcon#about to read 5, iclass 4, count 0 2006.217.07:31:10.49#ibcon#read 5, iclass 4, count 0 2006.217.07:31:10.49#ibcon#about to read 6, iclass 4, count 0 2006.217.07:31:10.49#ibcon#read 6, iclass 4, count 0 2006.217.07:31:10.49#ibcon#end of sib2, iclass 4, count 0 2006.217.07:31:10.49#ibcon#*after write, iclass 4, count 0 2006.217.07:31:10.49#ibcon#*before return 0, iclass 4, count 0 2006.217.07:31:10.49#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.217.07:31:10.49#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.217.07:31:10.49#ibcon#about to clear, iclass 4 cls_cnt 0 2006.217.07:31:10.49#ibcon#cleared, iclass 4 cls_cnt 0 2006.217.07:31:10.49$vc4f8/vb=3,4 2006.217.07:31:10.49#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.217.07:31:10.49#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.217.07:31:10.49#ibcon#ireg 11 cls_cnt 2 2006.217.07:31:10.49#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.217.07:31:10.55#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.217.07:31:10.55#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.217.07:31:10.55#ibcon#enter wrdev, iclass 6, count 2 2006.217.07:31:10.55#ibcon#first serial, iclass 6, count 2 2006.217.07:31:10.55#ibcon#enter sib2, iclass 6, count 2 2006.217.07:31:10.55#ibcon#flushed, iclass 6, count 2 2006.217.07:31:10.55#ibcon#about to write, iclass 6, count 2 2006.217.07:31:10.55#ibcon#wrote, iclass 6, count 2 2006.217.07:31:10.55#ibcon#about to read 3, iclass 6, count 2 2006.217.07:31:10.57#ibcon#read 3, iclass 6, count 2 2006.217.07:31:10.57#ibcon#about to read 4, iclass 6, count 2 2006.217.07:31:10.57#ibcon#read 4, iclass 6, count 2 2006.217.07:31:10.57#ibcon#about to read 5, iclass 6, count 2 2006.217.07:31:10.57#ibcon#read 5, iclass 6, count 2 2006.217.07:31:10.57#ibcon#about to read 6, iclass 6, count 2 2006.217.07:31:10.57#ibcon#read 6, iclass 6, count 2 2006.217.07:31:10.57#ibcon#end of sib2, iclass 6, count 2 2006.217.07:31:10.57#ibcon#*mode == 0, iclass 6, count 2 2006.217.07:31:10.57#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.217.07:31:10.57#ibcon#[27=AT03-04\r\n] 2006.217.07:31:10.57#ibcon#*before write, iclass 6, count 2 2006.217.07:31:10.57#ibcon#enter sib2, iclass 6, count 2 2006.217.07:31:10.57#ibcon#flushed, iclass 6, count 2 2006.217.07:31:10.57#ibcon#about to write, iclass 6, count 2 2006.217.07:31:10.57#ibcon#wrote, iclass 6, count 2 2006.217.07:31:10.57#ibcon#about to read 3, iclass 6, count 2 2006.217.07:31:10.60#ibcon#read 3, iclass 6, count 2 2006.217.07:31:10.60#ibcon#about to read 4, iclass 6, count 2 2006.217.07:31:10.60#ibcon#read 4, iclass 6, count 2 2006.217.07:31:10.60#ibcon#about to read 5, iclass 6, count 2 2006.217.07:31:10.60#ibcon#read 5, iclass 6, count 2 2006.217.07:31:10.60#ibcon#about to read 6, iclass 6, count 2 2006.217.07:31:10.60#ibcon#read 6, iclass 6, count 2 2006.217.07:31:10.60#ibcon#end of sib2, iclass 6, count 2 2006.217.07:31:10.60#ibcon#*after write, iclass 6, count 2 2006.217.07:31:10.60#ibcon#*before return 0, iclass 6, count 2 2006.217.07:31:10.60#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.217.07:31:10.60#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.217.07:31:10.60#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.217.07:31:10.60#ibcon#ireg 7 cls_cnt 0 2006.217.07:31:10.60#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.217.07:31:10.72#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.217.07:31:10.72#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.217.07:31:10.72#ibcon#enter wrdev, iclass 6, count 0 2006.217.07:31:10.72#ibcon#first serial, iclass 6, count 0 2006.217.07:31:10.72#ibcon#enter sib2, iclass 6, count 0 2006.217.07:31:10.72#ibcon#flushed, iclass 6, count 0 2006.217.07:31:10.72#ibcon#about to write, iclass 6, count 0 2006.217.07:31:10.72#ibcon#wrote, iclass 6, count 0 2006.217.07:31:10.72#ibcon#about to read 3, iclass 6, count 0 2006.217.07:31:10.74#ibcon#read 3, iclass 6, count 0 2006.217.07:31:10.74#ibcon#about to read 4, iclass 6, count 0 2006.217.07:31:10.74#ibcon#read 4, iclass 6, count 0 2006.217.07:31:10.74#ibcon#about to read 5, iclass 6, count 0 2006.217.07:31:10.74#ibcon#read 5, iclass 6, count 0 2006.217.07:31:10.74#ibcon#about to read 6, iclass 6, count 0 2006.217.07:31:10.74#ibcon#read 6, iclass 6, count 0 2006.217.07:31:10.74#ibcon#end of sib2, iclass 6, count 0 2006.217.07:31:10.74#ibcon#*mode == 0, iclass 6, count 0 2006.217.07:31:10.74#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.217.07:31:10.74#ibcon#[27=USB\r\n] 2006.217.07:31:10.74#ibcon#*before write, iclass 6, count 0 2006.217.07:31:10.74#ibcon#enter sib2, iclass 6, count 0 2006.217.07:31:10.74#ibcon#flushed, iclass 6, count 0 2006.217.07:31:10.74#ibcon#about to write, iclass 6, count 0 2006.217.07:31:10.74#ibcon#wrote, iclass 6, count 0 2006.217.07:31:10.74#ibcon#about to read 3, iclass 6, count 0 2006.217.07:31:10.77#ibcon#read 3, iclass 6, count 0 2006.217.07:31:10.77#ibcon#about to read 4, iclass 6, count 0 2006.217.07:31:10.77#ibcon#read 4, iclass 6, count 0 2006.217.07:31:10.77#ibcon#about to read 5, iclass 6, count 0 2006.217.07:31:10.77#ibcon#read 5, iclass 6, count 0 2006.217.07:31:10.77#ibcon#about to read 6, iclass 6, count 0 2006.217.07:31:10.77#ibcon#read 6, iclass 6, count 0 2006.217.07:31:10.77#ibcon#end of sib2, iclass 6, count 0 2006.217.07:31:10.77#ibcon#*after write, iclass 6, count 0 2006.217.07:31:10.77#ibcon#*before return 0, iclass 6, count 0 2006.217.07:31:10.77#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.217.07:31:10.77#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.217.07:31:10.77#ibcon#about to clear, iclass 6 cls_cnt 0 2006.217.07:31:10.77#ibcon#cleared, iclass 6 cls_cnt 0 2006.217.07:31:10.77$vc4f8/vblo=4,712.99 2006.217.07:31:10.77#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.217.07:31:10.77#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.217.07:31:10.77#ibcon#ireg 17 cls_cnt 0 2006.217.07:31:10.77#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.217.07:31:10.77#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.217.07:31:10.77#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.217.07:31:10.77#ibcon#enter wrdev, iclass 10, count 0 2006.217.07:31:10.77#ibcon#first serial, iclass 10, count 0 2006.217.07:31:10.77#ibcon#enter sib2, iclass 10, count 0 2006.217.07:31:10.77#ibcon#flushed, iclass 10, count 0 2006.217.07:31:10.77#ibcon#about to write, iclass 10, count 0 2006.217.07:31:10.77#ibcon#wrote, iclass 10, count 0 2006.217.07:31:10.77#ibcon#about to read 3, iclass 10, count 0 2006.217.07:31:10.79#ibcon#read 3, iclass 10, count 0 2006.217.07:31:10.79#ibcon#about to read 4, iclass 10, count 0 2006.217.07:31:10.79#ibcon#read 4, iclass 10, count 0 2006.217.07:31:10.79#ibcon#about to read 5, iclass 10, count 0 2006.217.07:31:10.79#ibcon#read 5, iclass 10, count 0 2006.217.07:31:10.79#ibcon#about to read 6, iclass 10, count 0 2006.217.07:31:10.79#ibcon#read 6, iclass 10, count 0 2006.217.07:31:10.79#ibcon#end of sib2, iclass 10, count 0 2006.217.07:31:10.79#ibcon#*mode == 0, iclass 10, count 0 2006.217.07:31:10.79#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.217.07:31:10.79#ibcon#[28=FRQ=04,712.99\r\n] 2006.217.07:31:10.79#ibcon#*before write, iclass 10, count 0 2006.217.07:31:10.79#ibcon#enter sib2, iclass 10, count 0 2006.217.07:31:10.79#ibcon#flushed, iclass 10, count 0 2006.217.07:31:10.79#ibcon#about to write, iclass 10, count 0 2006.217.07:31:10.79#ibcon#wrote, iclass 10, count 0 2006.217.07:31:10.79#ibcon#about to read 3, iclass 10, count 0 2006.217.07:31:10.84#ibcon#read 3, iclass 10, count 0 2006.217.07:31:10.84#ibcon#about to read 4, iclass 10, count 0 2006.217.07:31:10.84#ibcon#read 4, iclass 10, count 0 2006.217.07:31:10.84#ibcon#about to read 5, iclass 10, count 0 2006.217.07:31:10.84#ibcon#read 5, iclass 10, count 0 2006.217.07:31:10.84#ibcon#about to read 6, iclass 10, count 0 2006.217.07:31:10.84#ibcon#read 6, iclass 10, count 0 2006.217.07:31:10.84#ibcon#end of sib2, iclass 10, count 0 2006.217.07:31:10.84#ibcon#*after write, iclass 10, count 0 2006.217.07:31:10.84#ibcon#*before return 0, iclass 10, count 0 2006.217.07:31:10.84#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.217.07:31:10.84#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.217.07:31:10.84#ibcon#about to clear, iclass 10 cls_cnt 0 2006.217.07:31:10.84#ibcon#cleared, iclass 10 cls_cnt 0 2006.217.07:31:10.84$vc4f8/vb=4,4 2006.217.07:31:10.84#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.217.07:31:10.84#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.217.07:31:10.84#ibcon#ireg 11 cls_cnt 2 2006.217.07:31:10.84#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.217.07:31:10.89#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.217.07:31:10.89#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.217.07:31:10.89#ibcon#enter wrdev, iclass 12, count 2 2006.217.07:31:10.89#ibcon#first serial, iclass 12, count 2 2006.217.07:31:10.89#ibcon#enter sib2, iclass 12, count 2 2006.217.07:31:10.89#ibcon#flushed, iclass 12, count 2 2006.217.07:31:10.89#ibcon#about to write, iclass 12, count 2 2006.217.07:31:10.89#ibcon#wrote, iclass 12, count 2 2006.217.07:31:10.89#ibcon#about to read 3, iclass 12, count 2 2006.217.07:31:10.91#ibcon#read 3, iclass 12, count 2 2006.217.07:31:10.91#ibcon#about to read 4, iclass 12, count 2 2006.217.07:31:10.91#ibcon#read 4, iclass 12, count 2 2006.217.07:31:10.91#ibcon#about to read 5, iclass 12, count 2 2006.217.07:31:10.91#ibcon#read 5, iclass 12, count 2 2006.217.07:31:10.91#ibcon#about to read 6, iclass 12, count 2 2006.217.07:31:10.91#ibcon#read 6, iclass 12, count 2 2006.217.07:31:10.91#ibcon#end of sib2, iclass 12, count 2 2006.217.07:31:10.91#ibcon#*mode == 0, iclass 12, count 2 2006.217.07:31:10.91#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.217.07:31:10.91#ibcon#[27=AT04-04\r\n] 2006.217.07:31:10.91#ibcon#*before write, iclass 12, count 2 2006.217.07:31:10.91#ibcon#enter sib2, iclass 12, count 2 2006.217.07:31:10.91#ibcon#flushed, iclass 12, count 2 2006.217.07:31:10.91#ibcon#about to write, iclass 12, count 2 2006.217.07:31:10.91#ibcon#wrote, iclass 12, count 2 2006.217.07:31:10.91#ibcon#about to read 3, iclass 12, count 2 2006.217.07:31:10.94#ibcon#read 3, iclass 12, count 2 2006.217.07:31:10.94#ibcon#about to read 4, iclass 12, count 2 2006.217.07:31:10.94#ibcon#read 4, iclass 12, count 2 2006.217.07:31:10.94#ibcon#about to read 5, iclass 12, count 2 2006.217.07:31:10.94#ibcon#read 5, iclass 12, count 2 2006.217.07:31:10.94#ibcon#about to read 6, iclass 12, count 2 2006.217.07:31:10.94#ibcon#read 6, iclass 12, count 2 2006.217.07:31:10.94#ibcon#end of sib2, iclass 12, count 2 2006.217.07:31:10.94#ibcon#*after write, iclass 12, count 2 2006.217.07:31:10.94#ibcon#*before return 0, iclass 12, count 2 2006.217.07:31:10.94#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.217.07:31:10.94#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.217.07:31:10.94#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.217.07:31:10.94#ibcon#ireg 7 cls_cnt 0 2006.217.07:31:10.94#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.217.07:31:11.06#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.217.07:31:11.06#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.217.07:31:11.06#ibcon#enter wrdev, iclass 12, count 0 2006.217.07:31:11.06#ibcon#first serial, iclass 12, count 0 2006.217.07:31:11.06#ibcon#enter sib2, iclass 12, count 0 2006.217.07:31:11.06#ibcon#flushed, iclass 12, count 0 2006.217.07:31:11.06#ibcon#about to write, iclass 12, count 0 2006.217.07:31:11.06#ibcon#wrote, iclass 12, count 0 2006.217.07:31:11.06#ibcon#about to read 3, iclass 12, count 0 2006.217.07:31:11.08#ibcon#read 3, iclass 12, count 0 2006.217.07:31:11.08#ibcon#about to read 4, iclass 12, count 0 2006.217.07:31:11.08#ibcon#read 4, iclass 12, count 0 2006.217.07:31:11.08#ibcon#about to read 5, iclass 12, count 0 2006.217.07:31:11.08#ibcon#read 5, iclass 12, count 0 2006.217.07:31:11.08#ibcon#about to read 6, iclass 12, count 0 2006.217.07:31:11.08#ibcon#read 6, iclass 12, count 0 2006.217.07:31:11.08#ibcon#end of sib2, iclass 12, count 0 2006.217.07:31:11.08#ibcon#*mode == 0, iclass 12, count 0 2006.217.07:31:11.08#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.217.07:31:11.08#ibcon#[27=USB\r\n] 2006.217.07:31:11.08#ibcon#*before write, iclass 12, count 0 2006.217.07:31:11.08#ibcon#enter sib2, iclass 12, count 0 2006.217.07:31:11.08#ibcon#flushed, iclass 12, count 0 2006.217.07:31:11.08#ibcon#about to write, iclass 12, count 0 2006.217.07:31:11.08#ibcon#wrote, iclass 12, count 0 2006.217.07:31:11.08#ibcon#about to read 3, iclass 12, count 0 2006.217.07:31:11.11#ibcon#read 3, iclass 12, count 0 2006.217.07:31:11.11#ibcon#about to read 4, iclass 12, count 0 2006.217.07:31:11.11#ibcon#read 4, iclass 12, count 0 2006.217.07:31:11.11#ibcon#about to read 5, iclass 12, count 0 2006.217.07:31:11.11#ibcon#read 5, iclass 12, count 0 2006.217.07:31:11.11#ibcon#about to read 6, iclass 12, count 0 2006.217.07:31:11.11#ibcon#read 6, iclass 12, count 0 2006.217.07:31:11.11#ibcon#end of sib2, iclass 12, count 0 2006.217.07:31:11.11#ibcon#*after write, iclass 12, count 0 2006.217.07:31:11.11#ibcon#*before return 0, iclass 12, count 0 2006.217.07:31:11.11#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.217.07:31:11.11#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.217.07:31:11.11#ibcon#about to clear, iclass 12 cls_cnt 0 2006.217.07:31:11.11#ibcon#cleared, iclass 12 cls_cnt 0 2006.217.07:31:11.11$vc4f8/vblo=5,744.99 2006.217.07:31:11.11#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.217.07:31:11.11#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.217.07:31:11.11#ibcon#ireg 17 cls_cnt 0 2006.217.07:31:11.11#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.217.07:31:11.11#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.217.07:31:11.11#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.217.07:31:11.11#ibcon#enter wrdev, iclass 14, count 0 2006.217.07:31:11.11#ibcon#first serial, iclass 14, count 0 2006.217.07:31:11.11#ibcon#enter sib2, iclass 14, count 0 2006.217.07:31:11.11#ibcon#flushed, iclass 14, count 0 2006.217.07:31:11.11#ibcon#about to write, iclass 14, count 0 2006.217.07:31:11.11#ibcon#wrote, iclass 14, count 0 2006.217.07:31:11.11#ibcon#about to read 3, iclass 14, count 0 2006.217.07:31:11.13#ibcon#read 3, iclass 14, count 0 2006.217.07:31:11.13#ibcon#about to read 4, iclass 14, count 0 2006.217.07:31:11.13#ibcon#read 4, iclass 14, count 0 2006.217.07:31:11.13#ibcon#about to read 5, iclass 14, count 0 2006.217.07:31:11.13#ibcon#read 5, iclass 14, count 0 2006.217.07:31:11.13#ibcon#about to read 6, iclass 14, count 0 2006.217.07:31:11.13#ibcon#read 6, iclass 14, count 0 2006.217.07:31:11.13#ibcon#end of sib2, iclass 14, count 0 2006.217.07:31:11.13#ibcon#*mode == 0, iclass 14, count 0 2006.217.07:31:11.13#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.217.07:31:11.13#ibcon#[28=FRQ=05,744.99\r\n] 2006.217.07:31:11.13#ibcon#*before write, iclass 14, count 0 2006.217.07:31:11.13#ibcon#enter sib2, iclass 14, count 0 2006.217.07:31:11.13#ibcon#flushed, iclass 14, count 0 2006.217.07:31:11.13#ibcon#about to write, iclass 14, count 0 2006.217.07:31:11.13#ibcon#wrote, iclass 14, count 0 2006.217.07:31:11.13#ibcon#about to read 3, iclass 14, count 0 2006.217.07:31:11.17#ibcon#read 3, iclass 14, count 0 2006.217.07:31:11.17#ibcon#about to read 4, iclass 14, count 0 2006.217.07:31:11.17#ibcon#read 4, iclass 14, count 0 2006.217.07:31:11.17#ibcon#about to read 5, iclass 14, count 0 2006.217.07:31:11.17#ibcon#read 5, iclass 14, count 0 2006.217.07:31:11.17#ibcon#about to read 6, iclass 14, count 0 2006.217.07:31:11.17#ibcon#read 6, iclass 14, count 0 2006.217.07:31:11.17#ibcon#end of sib2, iclass 14, count 0 2006.217.07:31:11.17#ibcon#*after write, iclass 14, count 0 2006.217.07:31:11.17#ibcon#*before return 0, iclass 14, count 0 2006.217.07:31:11.17#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.217.07:31:11.17#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.217.07:31:11.17#ibcon#about to clear, iclass 14 cls_cnt 0 2006.217.07:31:11.17#ibcon#cleared, iclass 14 cls_cnt 0 2006.217.07:31:11.17$vc4f8/vb=5,4 2006.217.07:31:11.17#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.217.07:31:11.17#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.217.07:31:11.17#ibcon#ireg 11 cls_cnt 2 2006.217.07:31:11.17#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.217.07:31:11.23#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.217.07:31:11.23#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.217.07:31:11.23#ibcon#enter wrdev, iclass 16, count 2 2006.217.07:31:11.23#ibcon#first serial, iclass 16, count 2 2006.217.07:31:11.23#ibcon#enter sib2, iclass 16, count 2 2006.217.07:31:11.23#ibcon#flushed, iclass 16, count 2 2006.217.07:31:11.23#ibcon#about to write, iclass 16, count 2 2006.217.07:31:11.23#ibcon#wrote, iclass 16, count 2 2006.217.07:31:11.23#ibcon#about to read 3, iclass 16, count 2 2006.217.07:31:11.25#ibcon#read 3, iclass 16, count 2 2006.217.07:31:11.25#ibcon#about to read 4, iclass 16, count 2 2006.217.07:31:11.25#ibcon#read 4, iclass 16, count 2 2006.217.07:31:11.25#ibcon#about to read 5, iclass 16, count 2 2006.217.07:31:11.25#ibcon#read 5, iclass 16, count 2 2006.217.07:31:11.25#ibcon#about to read 6, iclass 16, count 2 2006.217.07:31:11.25#ibcon#read 6, iclass 16, count 2 2006.217.07:31:11.25#ibcon#end of sib2, iclass 16, count 2 2006.217.07:31:11.25#ibcon#*mode == 0, iclass 16, count 2 2006.217.07:31:11.25#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.217.07:31:11.25#ibcon#[27=AT05-04\r\n] 2006.217.07:31:11.25#ibcon#*before write, iclass 16, count 2 2006.217.07:31:11.25#ibcon#enter sib2, iclass 16, count 2 2006.217.07:31:11.25#ibcon#flushed, iclass 16, count 2 2006.217.07:31:11.25#ibcon#about to write, iclass 16, count 2 2006.217.07:31:11.25#ibcon#wrote, iclass 16, count 2 2006.217.07:31:11.25#ibcon#about to read 3, iclass 16, count 2 2006.217.07:31:11.28#ibcon#read 3, iclass 16, count 2 2006.217.07:31:11.28#ibcon#about to read 4, iclass 16, count 2 2006.217.07:31:11.28#ibcon#read 4, iclass 16, count 2 2006.217.07:31:11.28#ibcon#about to read 5, iclass 16, count 2 2006.217.07:31:11.28#ibcon#read 5, iclass 16, count 2 2006.217.07:31:11.28#ibcon#about to read 6, iclass 16, count 2 2006.217.07:31:11.28#ibcon#read 6, iclass 16, count 2 2006.217.07:31:11.28#ibcon#end of sib2, iclass 16, count 2 2006.217.07:31:11.28#ibcon#*after write, iclass 16, count 2 2006.217.07:31:11.28#ibcon#*before return 0, iclass 16, count 2 2006.217.07:31:11.28#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.217.07:31:11.28#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.217.07:31:11.28#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.217.07:31:11.28#ibcon#ireg 7 cls_cnt 0 2006.217.07:31:11.28#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.217.07:31:11.40#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.217.07:31:11.40#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.217.07:31:11.40#ibcon#enter wrdev, iclass 16, count 0 2006.217.07:31:11.40#ibcon#first serial, iclass 16, count 0 2006.217.07:31:11.40#ibcon#enter sib2, iclass 16, count 0 2006.217.07:31:11.40#ibcon#flushed, iclass 16, count 0 2006.217.07:31:11.40#ibcon#about to write, iclass 16, count 0 2006.217.07:31:11.40#ibcon#wrote, iclass 16, count 0 2006.217.07:31:11.40#ibcon#about to read 3, iclass 16, count 0 2006.217.07:31:11.42#ibcon#read 3, iclass 16, count 0 2006.217.07:31:11.42#ibcon#about to read 4, iclass 16, count 0 2006.217.07:31:11.42#ibcon#read 4, iclass 16, count 0 2006.217.07:31:11.42#ibcon#about to read 5, iclass 16, count 0 2006.217.07:31:11.42#ibcon#read 5, iclass 16, count 0 2006.217.07:31:11.42#ibcon#about to read 6, iclass 16, count 0 2006.217.07:31:11.42#ibcon#read 6, iclass 16, count 0 2006.217.07:31:11.42#ibcon#end of sib2, iclass 16, count 0 2006.217.07:31:11.42#ibcon#*mode == 0, iclass 16, count 0 2006.217.07:31:11.42#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.217.07:31:11.42#ibcon#[27=USB\r\n] 2006.217.07:31:11.42#ibcon#*before write, iclass 16, count 0 2006.217.07:31:11.42#ibcon#enter sib2, iclass 16, count 0 2006.217.07:31:11.42#ibcon#flushed, iclass 16, count 0 2006.217.07:31:11.42#ibcon#about to write, iclass 16, count 0 2006.217.07:31:11.42#ibcon#wrote, iclass 16, count 0 2006.217.07:31:11.42#ibcon#about to read 3, iclass 16, count 0 2006.217.07:31:11.45#ibcon#read 3, iclass 16, count 0 2006.217.07:31:11.45#ibcon#about to read 4, iclass 16, count 0 2006.217.07:31:11.45#ibcon#read 4, iclass 16, count 0 2006.217.07:31:11.45#ibcon#about to read 5, iclass 16, count 0 2006.217.07:31:11.45#ibcon#read 5, iclass 16, count 0 2006.217.07:31:11.45#ibcon#about to read 6, iclass 16, count 0 2006.217.07:31:11.45#ibcon#read 6, iclass 16, count 0 2006.217.07:31:11.45#ibcon#end of sib2, iclass 16, count 0 2006.217.07:31:11.45#ibcon#*after write, iclass 16, count 0 2006.217.07:31:11.45#ibcon#*before return 0, iclass 16, count 0 2006.217.07:31:11.45#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.217.07:31:11.45#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.217.07:31:11.45#ibcon#about to clear, iclass 16 cls_cnt 0 2006.217.07:31:11.45#ibcon#cleared, iclass 16 cls_cnt 0 2006.217.07:31:11.45$vc4f8/vblo=6,752.99 2006.217.07:31:11.45#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.217.07:31:11.45#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.217.07:31:11.45#ibcon#ireg 17 cls_cnt 0 2006.217.07:31:11.45#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.217.07:31:11.45#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.217.07:31:11.45#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.217.07:31:11.45#ibcon#enter wrdev, iclass 18, count 0 2006.217.07:31:11.45#ibcon#first serial, iclass 18, count 0 2006.217.07:31:11.45#ibcon#enter sib2, iclass 18, count 0 2006.217.07:31:11.45#ibcon#flushed, iclass 18, count 0 2006.217.07:31:11.45#ibcon#about to write, iclass 18, count 0 2006.217.07:31:11.45#ibcon#wrote, iclass 18, count 0 2006.217.07:31:11.45#ibcon#about to read 3, iclass 18, count 0 2006.217.07:31:11.47#ibcon#read 3, iclass 18, count 0 2006.217.07:31:11.47#ibcon#about to read 4, iclass 18, count 0 2006.217.07:31:11.47#ibcon#read 4, iclass 18, count 0 2006.217.07:31:11.47#ibcon#about to read 5, iclass 18, count 0 2006.217.07:31:11.47#ibcon#read 5, iclass 18, count 0 2006.217.07:31:11.47#ibcon#about to read 6, iclass 18, count 0 2006.217.07:31:11.47#ibcon#read 6, iclass 18, count 0 2006.217.07:31:11.47#ibcon#end of sib2, iclass 18, count 0 2006.217.07:31:11.47#ibcon#*mode == 0, iclass 18, count 0 2006.217.07:31:11.47#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.217.07:31:11.47#ibcon#[28=FRQ=06,752.99\r\n] 2006.217.07:31:11.47#ibcon#*before write, iclass 18, count 0 2006.217.07:31:11.47#ibcon#enter sib2, iclass 18, count 0 2006.217.07:31:11.47#ibcon#flushed, iclass 18, count 0 2006.217.07:31:11.47#ibcon#about to write, iclass 18, count 0 2006.217.07:31:11.47#ibcon#wrote, iclass 18, count 0 2006.217.07:31:11.47#ibcon#about to read 3, iclass 18, count 0 2006.217.07:31:11.52#ibcon#read 3, iclass 18, count 0 2006.217.07:31:11.52#ibcon#about to read 4, iclass 18, count 0 2006.217.07:31:11.52#ibcon#read 4, iclass 18, count 0 2006.217.07:31:11.52#ibcon#about to read 5, iclass 18, count 0 2006.217.07:31:11.52#ibcon#read 5, iclass 18, count 0 2006.217.07:31:11.52#ibcon#about to read 6, iclass 18, count 0 2006.217.07:31:11.52#ibcon#read 6, iclass 18, count 0 2006.217.07:31:11.52#ibcon#end of sib2, iclass 18, count 0 2006.217.07:31:11.52#ibcon#*after write, iclass 18, count 0 2006.217.07:31:11.52#ibcon#*before return 0, iclass 18, count 0 2006.217.07:31:11.52#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.217.07:31:11.52#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.217.07:31:11.52#ibcon#about to clear, iclass 18 cls_cnt 0 2006.217.07:31:11.52#ibcon#cleared, iclass 18 cls_cnt 0 2006.217.07:31:11.52$vc4f8/vb=6,4 2006.217.07:31:11.52#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.217.07:31:11.52#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.217.07:31:11.52#ibcon#ireg 11 cls_cnt 2 2006.217.07:31:11.52#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.217.07:31:11.57#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.217.07:31:11.57#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.217.07:31:11.57#ibcon#enter wrdev, iclass 20, count 2 2006.217.07:31:11.57#ibcon#first serial, iclass 20, count 2 2006.217.07:31:11.57#ibcon#enter sib2, iclass 20, count 2 2006.217.07:31:11.57#ibcon#flushed, iclass 20, count 2 2006.217.07:31:11.57#ibcon#about to write, iclass 20, count 2 2006.217.07:31:11.57#ibcon#wrote, iclass 20, count 2 2006.217.07:31:11.57#ibcon#about to read 3, iclass 20, count 2 2006.217.07:31:11.59#ibcon#read 3, iclass 20, count 2 2006.217.07:31:11.59#ibcon#about to read 4, iclass 20, count 2 2006.217.07:31:11.59#ibcon#read 4, iclass 20, count 2 2006.217.07:31:11.59#ibcon#about to read 5, iclass 20, count 2 2006.217.07:31:11.59#ibcon#read 5, iclass 20, count 2 2006.217.07:31:11.59#ibcon#about to read 6, iclass 20, count 2 2006.217.07:31:11.59#ibcon#read 6, iclass 20, count 2 2006.217.07:31:11.59#ibcon#end of sib2, iclass 20, count 2 2006.217.07:31:11.59#ibcon#*mode == 0, iclass 20, count 2 2006.217.07:31:11.59#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.217.07:31:11.59#ibcon#[27=AT06-04\r\n] 2006.217.07:31:11.59#ibcon#*before write, iclass 20, count 2 2006.217.07:31:11.59#ibcon#enter sib2, iclass 20, count 2 2006.217.07:31:11.59#ibcon#flushed, iclass 20, count 2 2006.217.07:31:11.59#ibcon#about to write, iclass 20, count 2 2006.217.07:31:11.59#ibcon#wrote, iclass 20, count 2 2006.217.07:31:11.59#ibcon#about to read 3, iclass 20, count 2 2006.217.07:31:11.62#ibcon#read 3, iclass 20, count 2 2006.217.07:31:11.62#ibcon#about to read 4, iclass 20, count 2 2006.217.07:31:11.62#ibcon#read 4, iclass 20, count 2 2006.217.07:31:11.62#ibcon#about to read 5, iclass 20, count 2 2006.217.07:31:11.62#ibcon#read 5, iclass 20, count 2 2006.217.07:31:11.62#ibcon#about to read 6, iclass 20, count 2 2006.217.07:31:11.62#ibcon#read 6, iclass 20, count 2 2006.217.07:31:11.62#ibcon#end of sib2, iclass 20, count 2 2006.217.07:31:11.62#ibcon#*after write, iclass 20, count 2 2006.217.07:31:11.62#ibcon#*before return 0, iclass 20, count 2 2006.217.07:31:11.62#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.217.07:31:11.62#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.217.07:31:11.62#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.217.07:31:11.62#ibcon#ireg 7 cls_cnt 0 2006.217.07:31:11.62#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.217.07:31:11.74#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.217.07:31:11.74#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.217.07:31:11.74#ibcon#enter wrdev, iclass 20, count 0 2006.217.07:31:11.74#ibcon#first serial, iclass 20, count 0 2006.217.07:31:11.74#ibcon#enter sib2, iclass 20, count 0 2006.217.07:31:11.74#ibcon#flushed, iclass 20, count 0 2006.217.07:31:11.74#ibcon#about to write, iclass 20, count 0 2006.217.07:31:11.74#ibcon#wrote, iclass 20, count 0 2006.217.07:31:11.74#ibcon#about to read 3, iclass 20, count 0 2006.217.07:31:11.76#ibcon#read 3, iclass 20, count 0 2006.217.07:31:11.76#ibcon#about to read 4, iclass 20, count 0 2006.217.07:31:11.76#ibcon#read 4, iclass 20, count 0 2006.217.07:31:11.76#ibcon#about to read 5, iclass 20, count 0 2006.217.07:31:11.76#ibcon#read 5, iclass 20, count 0 2006.217.07:31:11.76#ibcon#about to read 6, iclass 20, count 0 2006.217.07:31:11.76#ibcon#read 6, iclass 20, count 0 2006.217.07:31:11.76#ibcon#end of sib2, iclass 20, count 0 2006.217.07:31:11.76#ibcon#*mode == 0, iclass 20, count 0 2006.217.07:31:11.76#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.217.07:31:11.76#ibcon#[27=USB\r\n] 2006.217.07:31:11.76#ibcon#*before write, iclass 20, count 0 2006.217.07:31:11.76#ibcon#enter sib2, iclass 20, count 0 2006.217.07:31:11.76#ibcon#flushed, iclass 20, count 0 2006.217.07:31:11.76#ibcon#about to write, iclass 20, count 0 2006.217.07:31:11.76#ibcon#wrote, iclass 20, count 0 2006.217.07:31:11.76#ibcon#about to read 3, iclass 20, count 0 2006.217.07:31:11.79#ibcon#read 3, iclass 20, count 0 2006.217.07:31:11.79#ibcon#about to read 4, iclass 20, count 0 2006.217.07:31:11.79#ibcon#read 4, iclass 20, count 0 2006.217.07:31:11.79#ibcon#about to read 5, iclass 20, count 0 2006.217.07:31:11.79#ibcon#read 5, iclass 20, count 0 2006.217.07:31:11.79#ibcon#about to read 6, iclass 20, count 0 2006.217.07:31:11.79#ibcon#read 6, iclass 20, count 0 2006.217.07:31:11.79#ibcon#end of sib2, iclass 20, count 0 2006.217.07:31:11.79#ibcon#*after write, iclass 20, count 0 2006.217.07:31:11.79#ibcon#*before return 0, iclass 20, count 0 2006.217.07:31:11.79#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.217.07:31:11.79#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.217.07:31:11.79#ibcon#about to clear, iclass 20 cls_cnt 0 2006.217.07:31:11.79#ibcon#cleared, iclass 20 cls_cnt 0 2006.217.07:31:11.79$vc4f8/vabw=wide 2006.217.07:31:11.79#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.217.07:31:11.79#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.217.07:31:11.79#ibcon#ireg 8 cls_cnt 0 2006.217.07:31:11.79#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.217.07:31:11.79#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.217.07:31:11.79#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.217.07:31:11.79#ibcon#enter wrdev, iclass 22, count 0 2006.217.07:31:11.79#ibcon#first serial, iclass 22, count 0 2006.217.07:31:11.79#ibcon#enter sib2, iclass 22, count 0 2006.217.07:31:11.79#ibcon#flushed, iclass 22, count 0 2006.217.07:31:11.79#ibcon#about to write, iclass 22, count 0 2006.217.07:31:11.79#ibcon#wrote, iclass 22, count 0 2006.217.07:31:11.79#ibcon#about to read 3, iclass 22, count 0 2006.217.07:31:11.81#ibcon#read 3, iclass 22, count 0 2006.217.07:31:11.81#ibcon#about to read 4, iclass 22, count 0 2006.217.07:31:11.81#ibcon#read 4, iclass 22, count 0 2006.217.07:31:11.81#ibcon#about to read 5, iclass 22, count 0 2006.217.07:31:11.81#ibcon#read 5, iclass 22, count 0 2006.217.07:31:11.81#ibcon#about to read 6, iclass 22, count 0 2006.217.07:31:11.81#ibcon#read 6, iclass 22, count 0 2006.217.07:31:11.81#ibcon#end of sib2, iclass 22, count 0 2006.217.07:31:11.81#ibcon#*mode == 0, iclass 22, count 0 2006.217.07:31:11.81#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.217.07:31:11.81#ibcon#[25=BW32\r\n] 2006.217.07:31:11.81#ibcon#*before write, iclass 22, count 0 2006.217.07:31:11.81#ibcon#enter sib2, iclass 22, count 0 2006.217.07:31:11.81#ibcon#flushed, iclass 22, count 0 2006.217.07:31:11.81#ibcon#about to write, iclass 22, count 0 2006.217.07:31:11.81#ibcon#wrote, iclass 22, count 0 2006.217.07:31:11.81#ibcon#about to read 3, iclass 22, count 0 2006.217.07:31:11.84#ibcon#read 3, iclass 22, count 0 2006.217.07:31:11.84#ibcon#about to read 4, iclass 22, count 0 2006.217.07:31:11.84#ibcon#read 4, iclass 22, count 0 2006.217.07:31:11.84#ibcon#about to read 5, iclass 22, count 0 2006.217.07:31:11.84#ibcon#read 5, iclass 22, count 0 2006.217.07:31:11.84#ibcon#about to read 6, iclass 22, count 0 2006.217.07:31:11.84#ibcon#read 6, iclass 22, count 0 2006.217.07:31:11.84#ibcon#end of sib2, iclass 22, count 0 2006.217.07:31:11.84#ibcon#*after write, iclass 22, count 0 2006.217.07:31:11.84#ibcon#*before return 0, iclass 22, count 0 2006.217.07:31:11.84#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.217.07:31:11.84#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.217.07:31:11.84#ibcon#about to clear, iclass 22 cls_cnt 0 2006.217.07:31:11.84#ibcon#cleared, iclass 22 cls_cnt 0 2006.217.07:31:11.84$vc4f8/vbbw=wide 2006.217.07:31:11.84#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.217.07:31:11.84#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.217.07:31:11.84#ibcon#ireg 8 cls_cnt 0 2006.217.07:31:11.84#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.217.07:31:11.91#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.217.07:31:11.91#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.217.07:31:11.91#ibcon#enter wrdev, iclass 24, count 0 2006.217.07:31:11.91#ibcon#first serial, iclass 24, count 0 2006.217.07:31:11.91#ibcon#enter sib2, iclass 24, count 0 2006.217.07:31:11.91#ibcon#flushed, iclass 24, count 0 2006.217.07:31:11.91#ibcon#about to write, iclass 24, count 0 2006.217.07:31:11.91#ibcon#wrote, iclass 24, count 0 2006.217.07:31:11.91#ibcon#about to read 3, iclass 24, count 0 2006.217.07:31:11.93#ibcon#read 3, iclass 24, count 0 2006.217.07:31:11.93#ibcon#about to read 4, iclass 24, count 0 2006.217.07:31:11.93#ibcon#read 4, iclass 24, count 0 2006.217.07:31:11.93#ibcon#about to read 5, iclass 24, count 0 2006.217.07:31:11.93#ibcon#read 5, iclass 24, count 0 2006.217.07:31:11.93#ibcon#about to read 6, iclass 24, count 0 2006.217.07:31:11.93#ibcon#read 6, iclass 24, count 0 2006.217.07:31:11.93#ibcon#end of sib2, iclass 24, count 0 2006.217.07:31:11.93#ibcon#*mode == 0, iclass 24, count 0 2006.217.07:31:11.93#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.217.07:31:11.93#ibcon#[27=BW32\r\n] 2006.217.07:31:11.93#ibcon#*before write, iclass 24, count 0 2006.217.07:31:11.93#ibcon#enter sib2, iclass 24, count 0 2006.217.07:31:11.93#ibcon#flushed, iclass 24, count 0 2006.217.07:31:11.93#ibcon#about to write, iclass 24, count 0 2006.217.07:31:11.93#ibcon#wrote, iclass 24, count 0 2006.217.07:31:11.93#ibcon#about to read 3, iclass 24, count 0 2006.217.07:31:11.96#ibcon#read 3, iclass 24, count 0 2006.217.07:31:11.96#ibcon#about to read 4, iclass 24, count 0 2006.217.07:31:11.96#ibcon#read 4, iclass 24, count 0 2006.217.07:31:11.96#ibcon#about to read 5, iclass 24, count 0 2006.217.07:31:11.96#ibcon#read 5, iclass 24, count 0 2006.217.07:31:11.96#ibcon#about to read 6, iclass 24, count 0 2006.217.07:31:11.96#ibcon#read 6, iclass 24, count 0 2006.217.07:31:11.96#ibcon#end of sib2, iclass 24, count 0 2006.217.07:31:11.96#ibcon#*after write, iclass 24, count 0 2006.217.07:31:11.96#ibcon#*before return 0, iclass 24, count 0 2006.217.07:31:11.96#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.217.07:31:11.96#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.217.07:31:11.96#ibcon#about to clear, iclass 24 cls_cnt 0 2006.217.07:31:11.96#ibcon#cleared, iclass 24 cls_cnt 0 2006.217.07:31:11.96$4f8m12a/ifd4f 2006.217.07:31:11.96$ifd4f/lo= 2006.217.07:31:11.96$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.217.07:31:11.96$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.217.07:31:11.96$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.217.07:31:11.96$ifd4f/patch= 2006.217.07:31:11.96$ifd4f/patch=lo1,a1,a2,a3,a4 2006.217.07:31:11.96$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.217.07:31:11.96$ifd4f/patch=lo3,a5,a6,a7,a8 2006.217.07:31:11.96$4f8m12a/"form=m,16.000,1:2 2006.217.07:31:11.96$4f8m12a/"tpicd 2006.217.07:31:11.96$4f8m12a/echo=off 2006.217.07:31:11.96$4f8m12a/xlog=off 2006.217.07:31:11.96:!2006.217.07:33:20 2006.217.07:31:52.14#trakl#Source acquired 2006.217.07:31:54.14#flagr#flagr/antenna,acquired 2006.217.07:33:20.00:preob 2006.217.07:33:20.13/onsource/TRACKING 2006.217.07:33:20.13:!2006.217.07:33:30 2006.217.07:33:30.00:data_valid=on 2006.217.07:33:30.00:midob 2006.217.07:33:30.13/onsource/TRACKING 2006.217.07:33:30.13/wx/31.33,1008.5,59 2006.217.07:33:30.25/cable/+6.3836E-03 2006.217.07:33:31.34/va/01,05,usb,yes,38,40 2006.217.07:33:31.34/va/02,04,usb,yes,35,37 2006.217.07:33:31.34/va/03,04,usb,yes,33,34 2006.217.07:33:31.34/va/04,04,usb,yes,37,40 2006.217.07:33:31.34/va/05,07,usb,yes,39,42 2006.217.07:33:31.34/va/06,06,usb,yes,39,38 2006.217.07:33:31.34/va/07,06,usb,yes,39,39 2006.217.07:33:31.34/va/08,07,usb,yes,37,36 2006.217.07:33:31.57/valo/01,532.99,yes,locked 2006.217.07:33:31.57/valo/02,572.99,yes,locked 2006.217.07:33:31.57/valo/03,672.99,yes,locked 2006.217.07:33:31.57/valo/04,832.99,yes,locked 2006.217.07:33:31.57/valo/05,652.99,yes,locked 2006.217.07:33:31.57/valo/06,772.99,yes,locked 2006.217.07:33:31.57/valo/07,832.99,yes,locked 2006.217.07:33:31.57/valo/08,852.99,yes,locked 2006.217.07:33:32.66/vb/01,04,usb,yes,32,30 2006.217.07:33:32.66/vb/02,04,usb,yes,34,35 2006.217.07:33:32.66/vb/03,04,usb,yes,30,34 2006.217.07:33:32.66/vb/04,04,usb,yes,31,31 2006.217.07:33:32.66/vb/05,04,usb,yes,29,34 2006.217.07:33:32.66/vb/06,04,usb,yes,30,33 2006.217.07:33:32.66/vb/07,04,usb,yes,33,33 2006.217.07:33:32.66/vb/08,04,usb,yes,30,34 2006.217.07:33:32.90/vblo/01,632.99,yes,locked 2006.217.07:33:32.90/vblo/02,640.99,yes,locked 2006.217.07:33:32.90/vblo/03,656.99,yes,locked 2006.217.07:33:32.90/vblo/04,712.99,yes,locked 2006.217.07:33:32.90/vblo/05,744.99,yes,locked 2006.217.07:33:32.90/vblo/06,752.99,yes,locked 2006.217.07:33:32.90/vblo/07,734.99,yes,locked 2006.217.07:33:32.90/vblo/08,744.99,yes,locked 2006.217.07:33:33.05/vabw/8 2006.217.07:33:33.20/vbbw/8 2006.217.07:33:33.29/xfe/off,on,15.0 2006.217.07:33:33.67/ifatt/23,28,28,28 2006.217.07:33:34.08/fmout-gps/S +4.36E-07 2006.217.07:33:34.12:!2006.217.07:34:30 2006.217.07:34:30.00:data_valid=off 2006.217.07:34:30.00:postob 2006.217.07:34:30.10/cable/+6.3867E-03 2006.217.07:34:30.10/wx/31.32,1008.6,59 2006.217.07:34:31.08/fmout-gps/S +4.34E-07 2006.217.07:34:31.08:scan_name=217-0735,k06217,60 2006.217.07:34:31.08:source=0955+476,095819.67,472507.8,2000.0,ccw 2006.217.07:34:31.14#flagr#flagr/antenna,new-source 2006.217.07:34:32.14:checkk5 2006.217.07:34:32.51/chk_autoobs//k5ts1/ autoobs is running! 2006.217.07:34:32.88/chk_autoobs//k5ts2/ autoobs is running! 2006.217.07:34:33.26/chk_autoobs//k5ts3/ autoobs is running! 2006.217.07:34:33.63/chk_autoobs//k5ts4/ autoobs is running! 2006.217.07:34:34.00/chk_obsdata//k5ts1/T2170733??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:34:34.37/chk_obsdata//k5ts2/T2170733??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:34:34.74/chk_obsdata//k5ts3/T2170733??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:34:35.11/chk_obsdata//k5ts4/T2170733??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:34:35.80/k5log//k5ts1_log_newline 2006.217.07:34:36.50/k5log//k5ts2_log_newline 2006.217.07:34:37.18/k5log//k5ts3_log_newline 2006.217.07:34:37.87/k5log//k5ts4_log_newline 2006.217.07:34:37.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.217.07:34:37.89:4f8m12a=1 2006.217.07:34:37.89$4f8m12a/echo=on 2006.217.07:34:37.89$4f8m12a/pcalon 2006.217.07:34:37.89$pcalon/"no phase cal control is implemented here 2006.217.07:34:37.89$4f8m12a/"tpicd=stop 2006.217.07:34:37.89$4f8m12a/vc4f8 2006.217.07:34:37.89$vc4f8/valo=1,532.99 2006.217.07:34:37.90#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.217.07:34:37.90#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.217.07:34:37.90#ibcon#ireg 17 cls_cnt 0 2006.217.07:34:37.90#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.217.07:34:37.90#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.217.07:34:37.90#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.217.07:34:37.90#ibcon#enter wrdev, iclass 39, count 0 2006.217.07:34:37.90#ibcon#first serial, iclass 39, count 0 2006.217.07:34:37.90#ibcon#enter sib2, iclass 39, count 0 2006.217.07:34:37.90#ibcon#flushed, iclass 39, count 0 2006.217.07:34:37.90#ibcon#about to write, iclass 39, count 0 2006.217.07:34:37.90#ibcon#wrote, iclass 39, count 0 2006.217.07:34:37.90#ibcon#about to read 3, iclass 39, count 0 2006.217.07:34:37.94#ibcon#read 3, iclass 39, count 0 2006.217.07:34:37.94#ibcon#about to read 4, iclass 39, count 0 2006.217.07:34:37.94#ibcon#read 4, iclass 39, count 0 2006.217.07:34:37.94#ibcon#about to read 5, iclass 39, count 0 2006.217.07:34:37.94#ibcon#read 5, iclass 39, count 0 2006.217.07:34:37.94#ibcon#about to read 6, iclass 39, count 0 2006.217.07:34:37.94#ibcon#read 6, iclass 39, count 0 2006.217.07:34:37.94#ibcon#end of sib2, iclass 39, count 0 2006.217.07:34:37.94#ibcon#*mode == 0, iclass 39, count 0 2006.217.07:34:37.94#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.217.07:34:37.94#ibcon#[26=FRQ=01,532.99\r\n] 2006.217.07:34:37.94#ibcon#*before write, iclass 39, count 0 2006.217.07:34:37.94#ibcon#enter sib2, iclass 39, count 0 2006.217.07:34:37.94#ibcon#flushed, iclass 39, count 0 2006.217.07:34:37.94#ibcon#about to write, iclass 39, count 0 2006.217.07:34:37.94#ibcon#wrote, iclass 39, count 0 2006.217.07:34:37.94#ibcon#about to read 3, iclass 39, count 0 2006.217.07:34:37.99#ibcon#read 3, iclass 39, count 0 2006.217.07:34:37.99#ibcon#about to read 4, iclass 39, count 0 2006.217.07:34:37.99#ibcon#read 4, iclass 39, count 0 2006.217.07:34:37.99#ibcon#about to read 5, iclass 39, count 0 2006.217.07:34:37.99#ibcon#read 5, iclass 39, count 0 2006.217.07:34:37.99#ibcon#about to read 6, iclass 39, count 0 2006.217.07:34:37.99#ibcon#read 6, iclass 39, count 0 2006.217.07:34:37.99#ibcon#end of sib2, iclass 39, count 0 2006.217.07:34:37.99#ibcon#*after write, iclass 39, count 0 2006.217.07:34:37.99#ibcon#*before return 0, iclass 39, count 0 2006.217.07:34:37.99#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.217.07:34:37.99#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.217.07:34:37.99#ibcon#about to clear, iclass 39 cls_cnt 0 2006.217.07:34:37.99#ibcon#cleared, iclass 39 cls_cnt 0 2006.217.07:34:37.99$vc4f8/va=1,5 2006.217.07:34:37.99#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.217.07:34:37.99#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.217.07:34:37.99#ibcon#ireg 11 cls_cnt 2 2006.217.07:34:37.99#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.217.07:34:37.99#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.217.07:34:37.99#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.217.07:34:37.99#ibcon#enter wrdev, iclass 3, count 2 2006.217.07:34:37.99#ibcon#first serial, iclass 3, count 2 2006.217.07:34:37.99#ibcon#enter sib2, iclass 3, count 2 2006.217.07:34:37.99#ibcon#flushed, iclass 3, count 2 2006.217.07:34:37.99#ibcon#about to write, iclass 3, count 2 2006.217.07:34:37.99#ibcon#wrote, iclass 3, count 2 2006.217.07:34:37.99#ibcon#about to read 3, iclass 3, count 2 2006.217.07:34:38.01#ibcon#read 3, iclass 3, count 2 2006.217.07:34:38.01#ibcon#about to read 4, iclass 3, count 2 2006.217.07:34:38.01#ibcon#read 4, iclass 3, count 2 2006.217.07:34:38.01#ibcon#about to read 5, iclass 3, count 2 2006.217.07:34:38.01#ibcon#read 5, iclass 3, count 2 2006.217.07:34:38.01#ibcon#about to read 6, iclass 3, count 2 2006.217.07:34:38.01#ibcon#read 6, iclass 3, count 2 2006.217.07:34:38.01#ibcon#end of sib2, iclass 3, count 2 2006.217.07:34:38.01#ibcon#*mode == 0, iclass 3, count 2 2006.217.07:34:38.01#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.217.07:34:38.01#ibcon#[25=AT01-05\r\n] 2006.217.07:34:38.01#ibcon#*before write, iclass 3, count 2 2006.217.07:34:38.01#ibcon#enter sib2, iclass 3, count 2 2006.217.07:34:38.01#ibcon#flushed, iclass 3, count 2 2006.217.07:34:38.01#ibcon#about to write, iclass 3, count 2 2006.217.07:34:38.01#ibcon#wrote, iclass 3, count 2 2006.217.07:34:38.01#ibcon#about to read 3, iclass 3, count 2 2006.217.07:34:38.04#ibcon#read 3, iclass 3, count 2 2006.217.07:34:38.04#ibcon#about to read 4, iclass 3, count 2 2006.217.07:34:38.04#ibcon#read 4, iclass 3, count 2 2006.217.07:34:38.04#ibcon#about to read 5, iclass 3, count 2 2006.217.07:34:38.04#ibcon#read 5, iclass 3, count 2 2006.217.07:34:38.04#ibcon#about to read 6, iclass 3, count 2 2006.217.07:34:38.04#ibcon#read 6, iclass 3, count 2 2006.217.07:34:38.04#ibcon#end of sib2, iclass 3, count 2 2006.217.07:34:38.04#ibcon#*after write, iclass 3, count 2 2006.217.07:34:38.04#ibcon#*before return 0, iclass 3, count 2 2006.217.07:34:38.04#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.217.07:34:38.04#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.217.07:34:38.04#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.217.07:34:38.04#ibcon#ireg 7 cls_cnt 0 2006.217.07:34:38.04#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.217.07:34:38.16#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.217.07:34:38.16#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.217.07:34:38.16#ibcon#enter wrdev, iclass 3, count 0 2006.217.07:34:38.16#ibcon#first serial, iclass 3, count 0 2006.217.07:34:38.16#ibcon#enter sib2, iclass 3, count 0 2006.217.07:34:38.16#ibcon#flushed, iclass 3, count 0 2006.217.07:34:38.16#ibcon#about to write, iclass 3, count 0 2006.217.07:34:38.16#ibcon#wrote, iclass 3, count 0 2006.217.07:34:38.16#ibcon#about to read 3, iclass 3, count 0 2006.217.07:34:38.18#ibcon#read 3, iclass 3, count 0 2006.217.07:34:38.18#ibcon#about to read 4, iclass 3, count 0 2006.217.07:34:38.18#ibcon#read 4, iclass 3, count 0 2006.217.07:34:38.18#ibcon#about to read 5, iclass 3, count 0 2006.217.07:34:38.18#ibcon#read 5, iclass 3, count 0 2006.217.07:34:38.18#ibcon#about to read 6, iclass 3, count 0 2006.217.07:34:38.18#ibcon#read 6, iclass 3, count 0 2006.217.07:34:38.18#ibcon#end of sib2, iclass 3, count 0 2006.217.07:34:38.18#ibcon#*mode == 0, iclass 3, count 0 2006.217.07:34:38.18#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.217.07:34:38.18#ibcon#[25=USB\r\n] 2006.217.07:34:38.18#ibcon#*before write, iclass 3, count 0 2006.217.07:34:38.18#ibcon#enter sib2, iclass 3, count 0 2006.217.07:34:38.18#ibcon#flushed, iclass 3, count 0 2006.217.07:34:38.18#ibcon#about to write, iclass 3, count 0 2006.217.07:34:38.18#ibcon#wrote, iclass 3, count 0 2006.217.07:34:38.18#ibcon#about to read 3, iclass 3, count 0 2006.217.07:34:38.21#ibcon#read 3, iclass 3, count 0 2006.217.07:34:38.21#ibcon#about to read 4, iclass 3, count 0 2006.217.07:34:38.21#ibcon#read 4, iclass 3, count 0 2006.217.07:34:38.21#ibcon#about to read 5, iclass 3, count 0 2006.217.07:34:38.21#ibcon#read 5, iclass 3, count 0 2006.217.07:34:38.21#ibcon#about to read 6, iclass 3, count 0 2006.217.07:34:38.21#ibcon#read 6, iclass 3, count 0 2006.217.07:34:38.21#ibcon#end of sib2, iclass 3, count 0 2006.217.07:34:38.21#ibcon#*after write, iclass 3, count 0 2006.217.07:34:38.21#ibcon#*before return 0, iclass 3, count 0 2006.217.07:34:38.21#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.217.07:34:38.21#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.217.07:34:38.21#ibcon#about to clear, iclass 3 cls_cnt 0 2006.217.07:34:38.21#ibcon#cleared, iclass 3 cls_cnt 0 2006.217.07:34:38.21$vc4f8/valo=2,572.99 2006.217.07:34:38.21#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.217.07:34:38.21#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.217.07:34:38.21#ibcon#ireg 17 cls_cnt 0 2006.217.07:34:38.21#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.217.07:34:38.21#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.217.07:34:38.21#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.217.07:34:38.21#ibcon#enter wrdev, iclass 5, count 0 2006.217.07:34:38.21#ibcon#first serial, iclass 5, count 0 2006.217.07:34:38.21#ibcon#enter sib2, iclass 5, count 0 2006.217.07:34:38.21#ibcon#flushed, iclass 5, count 0 2006.217.07:34:38.21#ibcon#about to write, iclass 5, count 0 2006.217.07:34:38.21#ibcon#wrote, iclass 5, count 0 2006.217.07:34:38.21#ibcon#about to read 3, iclass 5, count 0 2006.217.07:34:38.23#ibcon#read 3, iclass 5, count 0 2006.217.07:34:38.23#ibcon#about to read 4, iclass 5, count 0 2006.217.07:34:38.23#ibcon#read 4, iclass 5, count 0 2006.217.07:34:38.23#ibcon#about to read 5, iclass 5, count 0 2006.217.07:34:38.23#ibcon#read 5, iclass 5, count 0 2006.217.07:34:38.23#ibcon#about to read 6, iclass 5, count 0 2006.217.07:34:38.23#ibcon#read 6, iclass 5, count 0 2006.217.07:34:38.23#ibcon#end of sib2, iclass 5, count 0 2006.217.07:34:38.23#ibcon#*mode == 0, iclass 5, count 0 2006.217.07:34:38.23#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.217.07:34:38.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.217.07:34:38.23#ibcon#*before write, iclass 5, count 0 2006.217.07:34:38.23#ibcon#enter sib2, iclass 5, count 0 2006.217.07:34:38.23#ibcon#flushed, iclass 5, count 0 2006.217.07:34:38.23#ibcon#about to write, iclass 5, count 0 2006.217.07:34:38.23#ibcon#wrote, iclass 5, count 0 2006.217.07:34:38.23#ibcon#about to read 3, iclass 5, count 0 2006.217.07:34:38.27#ibcon#read 3, iclass 5, count 0 2006.217.07:34:38.27#ibcon#about to read 4, iclass 5, count 0 2006.217.07:34:38.27#ibcon#read 4, iclass 5, count 0 2006.217.07:34:38.27#ibcon#about to read 5, iclass 5, count 0 2006.217.07:34:38.27#ibcon#read 5, iclass 5, count 0 2006.217.07:34:38.27#ibcon#about to read 6, iclass 5, count 0 2006.217.07:34:38.27#ibcon#read 6, iclass 5, count 0 2006.217.07:34:38.27#ibcon#end of sib2, iclass 5, count 0 2006.217.07:34:38.27#ibcon#*after write, iclass 5, count 0 2006.217.07:34:38.27#ibcon#*before return 0, iclass 5, count 0 2006.217.07:34:38.27#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.217.07:34:38.27#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.217.07:34:38.27#ibcon#about to clear, iclass 5 cls_cnt 0 2006.217.07:34:38.27#ibcon#cleared, iclass 5 cls_cnt 0 2006.217.07:34:38.27$vc4f8/va=2,4 2006.217.07:34:38.27#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.217.07:34:38.27#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.217.07:34:38.27#ibcon#ireg 11 cls_cnt 2 2006.217.07:34:38.27#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.217.07:34:38.33#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.217.07:34:38.33#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.217.07:34:38.33#ibcon#enter wrdev, iclass 7, count 2 2006.217.07:34:38.33#ibcon#first serial, iclass 7, count 2 2006.217.07:34:38.33#ibcon#enter sib2, iclass 7, count 2 2006.217.07:34:38.33#ibcon#flushed, iclass 7, count 2 2006.217.07:34:38.33#ibcon#about to write, iclass 7, count 2 2006.217.07:34:38.33#ibcon#wrote, iclass 7, count 2 2006.217.07:34:38.33#ibcon#about to read 3, iclass 7, count 2 2006.217.07:34:38.35#ibcon#read 3, iclass 7, count 2 2006.217.07:34:38.35#ibcon#about to read 4, iclass 7, count 2 2006.217.07:34:38.35#ibcon#read 4, iclass 7, count 2 2006.217.07:34:38.35#ibcon#about to read 5, iclass 7, count 2 2006.217.07:34:38.35#ibcon#read 5, iclass 7, count 2 2006.217.07:34:38.35#ibcon#about to read 6, iclass 7, count 2 2006.217.07:34:38.35#ibcon#read 6, iclass 7, count 2 2006.217.07:34:38.35#ibcon#end of sib2, iclass 7, count 2 2006.217.07:34:38.35#ibcon#*mode == 0, iclass 7, count 2 2006.217.07:34:38.35#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.217.07:34:38.35#ibcon#[25=AT02-04\r\n] 2006.217.07:34:38.35#ibcon#*before write, iclass 7, count 2 2006.217.07:34:38.35#ibcon#enter sib2, iclass 7, count 2 2006.217.07:34:38.35#ibcon#flushed, iclass 7, count 2 2006.217.07:34:38.35#ibcon#about to write, iclass 7, count 2 2006.217.07:34:38.35#ibcon#wrote, iclass 7, count 2 2006.217.07:34:38.35#ibcon#about to read 3, iclass 7, count 2 2006.217.07:34:38.38#ibcon#read 3, iclass 7, count 2 2006.217.07:34:38.38#ibcon#about to read 4, iclass 7, count 2 2006.217.07:34:38.38#ibcon#read 4, iclass 7, count 2 2006.217.07:34:38.38#ibcon#about to read 5, iclass 7, count 2 2006.217.07:34:38.38#ibcon#read 5, iclass 7, count 2 2006.217.07:34:38.38#ibcon#about to read 6, iclass 7, count 2 2006.217.07:34:38.38#ibcon#read 6, iclass 7, count 2 2006.217.07:34:38.38#ibcon#end of sib2, iclass 7, count 2 2006.217.07:34:38.38#ibcon#*after write, iclass 7, count 2 2006.217.07:34:38.38#ibcon#*before return 0, iclass 7, count 2 2006.217.07:34:38.38#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.217.07:34:38.38#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.217.07:34:38.38#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.217.07:34:38.38#ibcon#ireg 7 cls_cnt 0 2006.217.07:34:38.38#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.217.07:34:38.50#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.217.07:34:38.50#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.217.07:34:38.50#ibcon#enter wrdev, iclass 7, count 0 2006.217.07:34:38.50#ibcon#first serial, iclass 7, count 0 2006.217.07:34:38.50#ibcon#enter sib2, iclass 7, count 0 2006.217.07:34:38.50#ibcon#flushed, iclass 7, count 0 2006.217.07:34:38.50#ibcon#about to write, iclass 7, count 0 2006.217.07:34:38.50#ibcon#wrote, iclass 7, count 0 2006.217.07:34:38.50#ibcon#about to read 3, iclass 7, count 0 2006.217.07:34:38.52#ibcon#read 3, iclass 7, count 0 2006.217.07:34:38.52#ibcon#about to read 4, iclass 7, count 0 2006.217.07:34:38.52#ibcon#read 4, iclass 7, count 0 2006.217.07:34:38.52#ibcon#about to read 5, iclass 7, count 0 2006.217.07:34:38.52#ibcon#read 5, iclass 7, count 0 2006.217.07:34:38.52#ibcon#about to read 6, iclass 7, count 0 2006.217.07:34:38.52#ibcon#read 6, iclass 7, count 0 2006.217.07:34:38.52#ibcon#end of sib2, iclass 7, count 0 2006.217.07:34:38.52#ibcon#*mode == 0, iclass 7, count 0 2006.217.07:34:38.52#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.217.07:34:38.52#ibcon#[25=USB\r\n] 2006.217.07:34:38.52#ibcon#*before write, iclass 7, count 0 2006.217.07:34:38.52#ibcon#enter sib2, iclass 7, count 0 2006.217.07:34:38.52#ibcon#flushed, iclass 7, count 0 2006.217.07:34:38.52#ibcon#about to write, iclass 7, count 0 2006.217.07:34:38.52#ibcon#wrote, iclass 7, count 0 2006.217.07:34:38.52#ibcon#about to read 3, iclass 7, count 0 2006.217.07:34:38.55#ibcon#read 3, iclass 7, count 0 2006.217.07:34:38.55#ibcon#about to read 4, iclass 7, count 0 2006.217.07:34:38.55#ibcon#read 4, iclass 7, count 0 2006.217.07:34:38.55#ibcon#about to read 5, iclass 7, count 0 2006.217.07:34:38.55#ibcon#read 5, iclass 7, count 0 2006.217.07:34:38.55#ibcon#about to read 6, iclass 7, count 0 2006.217.07:34:38.55#ibcon#read 6, iclass 7, count 0 2006.217.07:34:38.55#ibcon#end of sib2, iclass 7, count 0 2006.217.07:34:38.55#ibcon#*after write, iclass 7, count 0 2006.217.07:34:38.55#ibcon#*before return 0, iclass 7, count 0 2006.217.07:34:38.55#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.217.07:34:38.55#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.217.07:34:38.55#ibcon#about to clear, iclass 7 cls_cnt 0 2006.217.07:34:38.55#ibcon#cleared, iclass 7 cls_cnt 0 2006.217.07:34:38.55$vc4f8/valo=3,672.99 2006.217.07:34:38.55#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.217.07:34:38.55#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.217.07:34:38.55#ibcon#ireg 17 cls_cnt 0 2006.217.07:34:38.55#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.217.07:34:38.55#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.217.07:34:38.55#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.217.07:34:38.55#ibcon#enter wrdev, iclass 11, count 0 2006.217.07:34:38.55#ibcon#first serial, iclass 11, count 0 2006.217.07:34:38.55#ibcon#enter sib2, iclass 11, count 0 2006.217.07:34:38.55#ibcon#flushed, iclass 11, count 0 2006.217.07:34:38.55#ibcon#about to write, iclass 11, count 0 2006.217.07:34:38.55#ibcon#wrote, iclass 11, count 0 2006.217.07:34:38.55#ibcon#about to read 3, iclass 11, count 0 2006.217.07:34:38.57#ibcon#read 3, iclass 11, count 0 2006.217.07:34:38.57#ibcon#about to read 4, iclass 11, count 0 2006.217.07:34:38.57#ibcon#read 4, iclass 11, count 0 2006.217.07:34:38.57#ibcon#about to read 5, iclass 11, count 0 2006.217.07:34:38.57#ibcon#read 5, iclass 11, count 0 2006.217.07:34:38.57#ibcon#about to read 6, iclass 11, count 0 2006.217.07:34:38.57#ibcon#read 6, iclass 11, count 0 2006.217.07:34:38.57#ibcon#end of sib2, iclass 11, count 0 2006.217.07:34:38.57#ibcon#*mode == 0, iclass 11, count 0 2006.217.07:34:38.57#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.217.07:34:38.57#ibcon#[26=FRQ=03,672.99\r\n] 2006.217.07:34:38.57#ibcon#*before write, iclass 11, count 0 2006.217.07:34:38.57#ibcon#enter sib2, iclass 11, count 0 2006.217.07:34:38.57#ibcon#flushed, iclass 11, count 0 2006.217.07:34:38.57#ibcon#about to write, iclass 11, count 0 2006.217.07:34:38.57#ibcon#wrote, iclass 11, count 0 2006.217.07:34:38.57#ibcon#about to read 3, iclass 11, count 0 2006.217.07:34:38.61#ibcon#read 3, iclass 11, count 0 2006.217.07:34:38.61#ibcon#about to read 4, iclass 11, count 0 2006.217.07:34:38.61#ibcon#read 4, iclass 11, count 0 2006.217.07:34:38.61#ibcon#about to read 5, iclass 11, count 0 2006.217.07:34:38.61#ibcon#read 5, iclass 11, count 0 2006.217.07:34:38.61#ibcon#about to read 6, iclass 11, count 0 2006.217.07:34:38.61#ibcon#read 6, iclass 11, count 0 2006.217.07:34:38.61#ibcon#end of sib2, iclass 11, count 0 2006.217.07:34:38.61#ibcon#*after write, iclass 11, count 0 2006.217.07:34:38.61#ibcon#*before return 0, iclass 11, count 0 2006.217.07:34:38.61#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.217.07:34:38.61#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.217.07:34:38.61#ibcon#about to clear, iclass 11 cls_cnt 0 2006.217.07:34:38.61#ibcon#cleared, iclass 11 cls_cnt 0 2006.217.07:34:38.61$vc4f8/va=3,4 2006.217.07:34:38.61#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.217.07:34:38.61#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.217.07:34:38.61#ibcon#ireg 11 cls_cnt 2 2006.217.07:34:38.61#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.217.07:34:38.67#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.217.07:34:38.67#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.217.07:34:38.67#ibcon#enter wrdev, iclass 13, count 2 2006.217.07:34:38.67#ibcon#first serial, iclass 13, count 2 2006.217.07:34:38.67#ibcon#enter sib2, iclass 13, count 2 2006.217.07:34:38.67#ibcon#flushed, iclass 13, count 2 2006.217.07:34:38.67#ibcon#about to write, iclass 13, count 2 2006.217.07:34:38.67#ibcon#wrote, iclass 13, count 2 2006.217.07:34:38.67#ibcon#about to read 3, iclass 13, count 2 2006.217.07:34:38.69#ibcon#read 3, iclass 13, count 2 2006.217.07:34:38.69#ibcon#about to read 4, iclass 13, count 2 2006.217.07:34:38.69#ibcon#read 4, iclass 13, count 2 2006.217.07:34:38.69#ibcon#about to read 5, iclass 13, count 2 2006.217.07:34:38.69#ibcon#read 5, iclass 13, count 2 2006.217.07:34:38.69#ibcon#about to read 6, iclass 13, count 2 2006.217.07:34:38.69#ibcon#read 6, iclass 13, count 2 2006.217.07:34:38.69#ibcon#end of sib2, iclass 13, count 2 2006.217.07:34:38.69#ibcon#*mode == 0, iclass 13, count 2 2006.217.07:34:38.69#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.217.07:34:38.69#ibcon#[25=AT03-04\r\n] 2006.217.07:34:38.69#ibcon#*before write, iclass 13, count 2 2006.217.07:34:38.69#ibcon#enter sib2, iclass 13, count 2 2006.217.07:34:38.69#ibcon#flushed, iclass 13, count 2 2006.217.07:34:38.69#ibcon#about to write, iclass 13, count 2 2006.217.07:34:38.69#ibcon#wrote, iclass 13, count 2 2006.217.07:34:38.69#ibcon#about to read 3, iclass 13, count 2 2006.217.07:34:38.73#ibcon#read 3, iclass 13, count 2 2006.217.07:34:38.73#ibcon#about to read 4, iclass 13, count 2 2006.217.07:34:38.73#ibcon#read 4, iclass 13, count 2 2006.217.07:34:38.73#ibcon#about to read 5, iclass 13, count 2 2006.217.07:34:38.73#ibcon#read 5, iclass 13, count 2 2006.217.07:34:38.73#ibcon#about to read 6, iclass 13, count 2 2006.217.07:34:38.73#ibcon#read 6, iclass 13, count 2 2006.217.07:34:38.73#ibcon#end of sib2, iclass 13, count 2 2006.217.07:34:38.73#ibcon#*after write, iclass 13, count 2 2006.217.07:34:38.73#ibcon#*before return 0, iclass 13, count 2 2006.217.07:34:38.73#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.217.07:34:38.73#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.217.07:34:38.73#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.217.07:34:38.73#ibcon#ireg 7 cls_cnt 0 2006.217.07:34:38.73#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.217.07:34:38.85#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.217.07:34:38.85#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.217.07:34:38.85#ibcon#enter wrdev, iclass 13, count 0 2006.217.07:34:38.85#ibcon#first serial, iclass 13, count 0 2006.217.07:34:38.85#ibcon#enter sib2, iclass 13, count 0 2006.217.07:34:38.85#ibcon#flushed, iclass 13, count 0 2006.217.07:34:38.85#ibcon#about to write, iclass 13, count 0 2006.217.07:34:38.85#ibcon#wrote, iclass 13, count 0 2006.217.07:34:38.85#ibcon#about to read 3, iclass 13, count 0 2006.217.07:34:38.87#ibcon#read 3, iclass 13, count 0 2006.217.07:34:38.87#ibcon#about to read 4, iclass 13, count 0 2006.217.07:34:38.87#ibcon#read 4, iclass 13, count 0 2006.217.07:34:38.87#ibcon#about to read 5, iclass 13, count 0 2006.217.07:34:38.87#ibcon#read 5, iclass 13, count 0 2006.217.07:34:38.87#ibcon#about to read 6, iclass 13, count 0 2006.217.07:34:38.87#ibcon#read 6, iclass 13, count 0 2006.217.07:34:38.87#ibcon#end of sib2, iclass 13, count 0 2006.217.07:34:38.87#ibcon#*mode == 0, iclass 13, count 0 2006.217.07:34:38.87#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.217.07:34:38.87#ibcon#[25=USB\r\n] 2006.217.07:34:38.87#ibcon#*before write, iclass 13, count 0 2006.217.07:34:38.87#ibcon#enter sib2, iclass 13, count 0 2006.217.07:34:38.87#ibcon#flushed, iclass 13, count 0 2006.217.07:34:38.87#ibcon#about to write, iclass 13, count 0 2006.217.07:34:38.87#ibcon#wrote, iclass 13, count 0 2006.217.07:34:38.87#ibcon#about to read 3, iclass 13, count 0 2006.217.07:34:38.90#ibcon#read 3, iclass 13, count 0 2006.217.07:34:38.90#ibcon#about to read 4, iclass 13, count 0 2006.217.07:34:38.90#ibcon#read 4, iclass 13, count 0 2006.217.07:34:38.90#ibcon#about to read 5, iclass 13, count 0 2006.217.07:34:38.90#ibcon#read 5, iclass 13, count 0 2006.217.07:34:38.90#ibcon#about to read 6, iclass 13, count 0 2006.217.07:34:38.90#ibcon#read 6, iclass 13, count 0 2006.217.07:34:38.90#ibcon#end of sib2, iclass 13, count 0 2006.217.07:34:38.90#ibcon#*after write, iclass 13, count 0 2006.217.07:34:38.90#ibcon#*before return 0, iclass 13, count 0 2006.217.07:34:38.90#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.217.07:34:38.90#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.217.07:34:38.90#ibcon#about to clear, iclass 13 cls_cnt 0 2006.217.07:34:38.90#ibcon#cleared, iclass 13 cls_cnt 0 2006.217.07:34:38.90$vc4f8/valo=4,832.99 2006.217.07:34:38.90#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.217.07:34:38.90#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.217.07:34:38.90#ibcon#ireg 17 cls_cnt 0 2006.217.07:34:38.90#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.217.07:34:38.90#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.217.07:34:38.90#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.217.07:34:38.90#ibcon#enter wrdev, iclass 15, count 0 2006.217.07:34:38.90#ibcon#first serial, iclass 15, count 0 2006.217.07:34:38.90#ibcon#enter sib2, iclass 15, count 0 2006.217.07:34:38.90#ibcon#flushed, iclass 15, count 0 2006.217.07:34:38.90#ibcon#about to write, iclass 15, count 0 2006.217.07:34:38.90#ibcon#wrote, iclass 15, count 0 2006.217.07:34:38.90#ibcon#about to read 3, iclass 15, count 0 2006.217.07:34:38.92#ibcon#read 3, iclass 15, count 0 2006.217.07:34:38.92#ibcon#about to read 4, iclass 15, count 0 2006.217.07:34:38.92#ibcon#read 4, iclass 15, count 0 2006.217.07:34:38.92#ibcon#about to read 5, iclass 15, count 0 2006.217.07:34:38.92#ibcon#read 5, iclass 15, count 0 2006.217.07:34:38.92#ibcon#about to read 6, iclass 15, count 0 2006.217.07:34:38.92#ibcon#read 6, iclass 15, count 0 2006.217.07:34:38.92#ibcon#end of sib2, iclass 15, count 0 2006.217.07:34:38.92#ibcon#*mode == 0, iclass 15, count 0 2006.217.07:34:38.92#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.217.07:34:38.92#ibcon#[26=FRQ=04,832.99\r\n] 2006.217.07:34:38.92#ibcon#*before write, iclass 15, count 0 2006.217.07:34:38.92#ibcon#enter sib2, iclass 15, count 0 2006.217.07:34:38.92#ibcon#flushed, iclass 15, count 0 2006.217.07:34:38.92#ibcon#about to write, iclass 15, count 0 2006.217.07:34:38.92#ibcon#wrote, iclass 15, count 0 2006.217.07:34:38.92#ibcon#about to read 3, iclass 15, count 0 2006.217.07:34:38.96#ibcon#read 3, iclass 15, count 0 2006.217.07:34:38.96#ibcon#about to read 4, iclass 15, count 0 2006.217.07:34:38.96#ibcon#read 4, iclass 15, count 0 2006.217.07:34:38.96#ibcon#about to read 5, iclass 15, count 0 2006.217.07:34:38.96#ibcon#read 5, iclass 15, count 0 2006.217.07:34:38.96#ibcon#about to read 6, iclass 15, count 0 2006.217.07:34:38.96#ibcon#read 6, iclass 15, count 0 2006.217.07:34:38.96#ibcon#end of sib2, iclass 15, count 0 2006.217.07:34:38.96#ibcon#*after write, iclass 15, count 0 2006.217.07:34:38.96#ibcon#*before return 0, iclass 15, count 0 2006.217.07:34:38.96#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.217.07:34:38.96#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.217.07:34:38.96#ibcon#about to clear, iclass 15 cls_cnt 0 2006.217.07:34:38.96#ibcon#cleared, iclass 15 cls_cnt 0 2006.217.07:34:38.96$vc4f8/va=4,4 2006.217.07:34:38.96#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.217.07:34:38.96#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.217.07:34:38.96#ibcon#ireg 11 cls_cnt 2 2006.217.07:34:38.96#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.217.07:34:39.02#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.217.07:34:39.02#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.217.07:34:39.02#ibcon#enter wrdev, iclass 17, count 2 2006.217.07:34:39.02#ibcon#first serial, iclass 17, count 2 2006.217.07:34:39.02#ibcon#enter sib2, iclass 17, count 2 2006.217.07:34:39.02#ibcon#flushed, iclass 17, count 2 2006.217.07:34:39.02#ibcon#about to write, iclass 17, count 2 2006.217.07:34:39.02#ibcon#wrote, iclass 17, count 2 2006.217.07:34:39.02#ibcon#about to read 3, iclass 17, count 2 2006.217.07:34:39.04#ibcon#read 3, iclass 17, count 2 2006.217.07:34:39.04#ibcon#about to read 4, iclass 17, count 2 2006.217.07:34:39.04#ibcon#read 4, iclass 17, count 2 2006.217.07:34:39.04#ibcon#about to read 5, iclass 17, count 2 2006.217.07:34:39.04#ibcon#read 5, iclass 17, count 2 2006.217.07:34:39.04#ibcon#about to read 6, iclass 17, count 2 2006.217.07:34:39.04#ibcon#read 6, iclass 17, count 2 2006.217.07:34:39.04#ibcon#end of sib2, iclass 17, count 2 2006.217.07:34:39.04#ibcon#*mode == 0, iclass 17, count 2 2006.217.07:34:39.04#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.217.07:34:39.04#ibcon#[25=AT04-04\r\n] 2006.217.07:34:39.04#ibcon#*before write, iclass 17, count 2 2006.217.07:34:39.04#ibcon#enter sib2, iclass 17, count 2 2006.217.07:34:39.04#ibcon#flushed, iclass 17, count 2 2006.217.07:34:39.04#ibcon#about to write, iclass 17, count 2 2006.217.07:34:39.04#ibcon#wrote, iclass 17, count 2 2006.217.07:34:39.04#ibcon#about to read 3, iclass 17, count 2 2006.217.07:34:39.07#ibcon#read 3, iclass 17, count 2 2006.217.07:34:39.07#ibcon#about to read 4, iclass 17, count 2 2006.217.07:34:39.07#ibcon#read 4, iclass 17, count 2 2006.217.07:34:39.07#ibcon#about to read 5, iclass 17, count 2 2006.217.07:34:39.07#ibcon#read 5, iclass 17, count 2 2006.217.07:34:39.07#ibcon#about to read 6, iclass 17, count 2 2006.217.07:34:39.07#ibcon#read 6, iclass 17, count 2 2006.217.07:34:39.07#ibcon#end of sib2, iclass 17, count 2 2006.217.07:34:39.07#ibcon#*after write, iclass 17, count 2 2006.217.07:34:39.07#ibcon#*before return 0, iclass 17, count 2 2006.217.07:34:39.07#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.217.07:34:39.07#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.217.07:34:39.07#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.217.07:34:39.07#ibcon#ireg 7 cls_cnt 0 2006.217.07:34:39.07#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.217.07:34:39.19#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.217.07:34:39.19#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.217.07:34:39.19#ibcon#enter wrdev, iclass 17, count 0 2006.217.07:34:39.19#ibcon#first serial, iclass 17, count 0 2006.217.07:34:39.19#ibcon#enter sib2, iclass 17, count 0 2006.217.07:34:39.19#ibcon#flushed, iclass 17, count 0 2006.217.07:34:39.19#ibcon#about to write, iclass 17, count 0 2006.217.07:34:39.19#ibcon#wrote, iclass 17, count 0 2006.217.07:34:39.19#ibcon#about to read 3, iclass 17, count 0 2006.217.07:34:39.21#ibcon#read 3, iclass 17, count 0 2006.217.07:34:39.21#ibcon#about to read 4, iclass 17, count 0 2006.217.07:34:39.21#ibcon#read 4, iclass 17, count 0 2006.217.07:34:39.21#ibcon#about to read 5, iclass 17, count 0 2006.217.07:34:39.21#ibcon#read 5, iclass 17, count 0 2006.217.07:34:39.21#ibcon#about to read 6, iclass 17, count 0 2006.217.07:34:39.21#ibcon#read 6, iclass 17, count 0 2006.217.07:34:39.21#ibcon#end of sib2, iclass 17, count 0 2006.217.07:34:39.21#ibcon#*mode == 0, iclass 17, count 0 2006.217.07:34:39.21#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.217.07:34:39.21#ibcon#[25=USB\r\n] 2006.217.07:34:39.21#ibcon#*before write, iclass 17, count 0 2006.217.07:34:39.21#ibcon#enter sib2, iclass 17, count 0 2006.217.07:34:39.21#ibcon#flushed, iclass 17, count 0 2006.217.07:34:39.21#ibcon#about to write, iclass 17, count 0 2006.217.07:34:39.21#ibcon#wrote, iclass 17, count 0 2006.217.07:34:39.21#ibcon#about to read 3, iclass 17, count 0 2006.217.07:34:39.24#ibcon#read 3, iclass 17, count 0 2006.217.07:34:39.24#ibcon#about to read 4, iclass 17, count 0 2006.217.07:34:39.24#ibcon#read 4, iclass 17, count 0 2006.217.07:34:39.24#ibcon#about to read 5, iclass 17, count 0 2006.217.07:34:39.24#ibcon#read 5, iclass 17, count 0 2006.217.07:34:39.24#ibcon#about to read 6, iclass 17, count 0 2006.217.07:34:39.24#ibcon#read 6, iclass 17, count 0 2006.217.07:34:39.24#ibcon#end of sib2, iclass 17, count 0 2006.217.07:34:39.24#ibcon#*after write, iclass 17, count 0 2006.217.07:34:39.24#ibcon#*before return 0, iclass 17, count 0 2006.217.07:34:39.24#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.217.07:34:39.24#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.217.07:34:39.24#ibcon#about to clear, iclass 17 cls_cnt 0 2006.217.07:34:39.24#ibcon#cleared, iclass 17 cls_cnt 0 2006.217.07:34:39.24$vc4f8/valo=5,652.99 2006.217.07:34:39.24#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.217.07:34:39.24#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.217.07:34:39.24#ibcon#ireg 17 cls_cnt 0 2006.217.07:34:39.24#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.217.07:34:39.24#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.217.07:34:39.24#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.217.07:34:39.24#ibcon#enter wrdev, iclass 19, count 0 2006.217.07:34:39.24#ibcon#first serial, iclass 19, count 0 2006.217.07:34:39.24#ibcon#enter sib2, iclass 19, count 0 2006.217.07:34:39.24#ibcon#flushed, iclass 19, count 0 2006.217.07:34:39.24#ibcon#about to write, iclass 19, count 0 2006.217.07:34:39.24#ibcon#wrote, iclass 19, count 0 2006.217.07:34:39.24#ibcon#about to read 3, iclass 19, count 0 2006.217.07:34:39.26#ibcon#read 3, iclass 19, count 0 2006.217.07:34:39.26#ibcon#about to read 4, iclass 19, count 0 2006.217.07:34:39.26#ibcon#read 4, iclass 19, count 0 2006.217.07:34:39.26#ibcon#about to read 5, iclass 19, count 0 2006.217.07:34:39.26#ibcon#read 5, iclass 19, count 0 2006.217.07:34:39.26#ibcon#about to read 6, iclass 19, count 0 2006.217.07:34:39.26#ibcon#read 6, iclass 19, count 0 2006.217.07:34:39.26#ibcon#end of sib2, iclass 19, count 0 2006.217.07:34:39.26#ibcon#*mode == 0, iclass 19, count 0 2006.217.07:34:39.26#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.217.07:34:39.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.217.07:34:39.26#ibcon#*before write, iclass 19, count 0 2006.217.07:34:39.26#ibcon#enter sib2, iclass 19, count 0 2006.217.07:34:39.26#ibcon#flushed, iclass 19, count 0 2006.217.07:34:39.26#ibcon#about to write, iclass 19, count 0 2006.217.07:34:39.26#ibcon#wrote, iclass 19, count 0 2006.217.07:34:39.26#ibcon#about to read 3, iclass 19, count 0 2006.217.07:34:39.30#ibcon#read 3, iclass 19, count 0 2006.217.07:34:39.30#ibcon#about to read 4, iclass 19, count 0 2006.217.07:34:39.30#ibcon#read 4, iclass 19, count 0 2006.217.07:34:39.30#ibcon#about to read 5, iclass 19, count 0 2006.217.07:34:39.30#ibcon#read 5, iclass 19, count 0 2006.217.07:34:39.30#ibcon#about to read 6, iclass 19, count 0 2006.217.07:34:39.30#ibcon#read 6, iclass 19, count 0 2006.217.07:34:39.30#ibcon#end of sib2, iclass 19, count 0 2006.217.07:34:39.30#ibcon#*after write, iclass 19, count 0 2006.217.07:34:39.30#ibcon#*before return 0, iclass 19, count 0 2006.217.07:34:39.30#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.217.07:34:39.30#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.217.07:34:39.30#ibcon#about to clear, iclass 19 cls_cnt 0 2006.217.07:34:39.30#ibcon#cleared, iclass 19 cls_cnt 0 2006.217.07:34:39.30$vc4f8/va=5,7 2006.217.07:34:39.30#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.217.07:34:39.30#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.217.07:34:39.30#ibcon#ireg 11 cls_cnt 2 2006.217.07:34:39.30#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.217.07:34:39.36#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.217.07:34:39.36#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.217.07:34:39.36#ibcon#enter wrdev, iclass 21, count 2 2006.217.07:34:39.36#ibcon#first serial, iclass 21, count 2 2006.217.07:34:39.36#ibcon#enter sib2, iclass 21, count 2 2006.217.07:34:39.36#ibcon#flushed, iclass 21, count 2 2006.217.07:34:39.36#ibcon#about to write, iclass 21, count 2 2006.217.07:34:39.36#ibcon#wrote, iclass 21, count 2 2006.217.07:34:39.36#ibcon#about to read 3, iclass 21, count 2 2006.217.07:34:39.38#ibcon#read 3, iclass 21, count 2 2006.217.07:34:39.38#ibcon#about to read 4, iclass 21, count 2 2006.217.07:34:39.38#ibcon#read 4, iclass 21, count 2 2006.217.07:34:39.38#ibcon#about to read 5, iclass 21, count 2 2006.217.07:34:39.38#ibcon#read 5, iclass 21, count 2 2006.217.07:34:39.38#ibcon#about to read 6, iclass 21, count 2 2006.217.07:34:39.38#ibcon#read 6, iclass 21, count 2 2006.217.07:34:39.38#ibcon#end of sib2, iclass 21, count 2 2006.217.07:34:39.38#ibcon#*mode == 0, iclass 21, count 2 2006.217.07:34:39.38#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.217.07:34:39.38#ibcon#[25=AT05-07\r\n] 2006.217.07:34:39.38#ibcon#*before write, iclass 21, count 2 2006.217.07:34:39.38#ibcon#enter sib2, iclass 21, count 2 2006.217.07:34:39.38#ibcon#flushed, iclass 21, count 2 2006.217.07:34:39.38#ibcon#about to write, iclass 21, count 2 2006.217.07:34:39.38#ibcon#wrote, iclass 21, count 2 2006.217.07:34:39.38#ibcon#about to read 3, iclass 21, count 2 2006.217.07:34:39.41#ibcon#read 3, iclass 21, count 2 2006.217.07:34:39.41#ibcon#about to read 4, iclass 21, count 2 2006.217.07:34:39.41#ibcon#read 4, iclass 21, count 2 2006.217.07:34:39.41#ibcon#about to read 5, iclass 21, count 2 2006.217.07:34:39.41#ibcon#read 5, iclass 21, count 2 2006.217.07:34:39.41#ibcon#about to read 6, iclass 21, count 2 2006.217.07:34:39.41#ibcon#read 6, iclass 21, count 2 2006.217.07:34:39.41#ibcon#end of sib2, iclass 21, count 2 2006.217.07:34:39.41#ibcon#*after write, iclass 21, count 2 2006.217.07:34:39.41#ibcon#*before return 0, iclass 21, count 2 2006.217.07:34:39.41#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.217.07:34:39.41#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.217.07:34:39.41#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.217.07:34:39.41#ibcon#ireg 7 cls_cnt 0 2006.217.07:34:39.41#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.217.07:34:39.53#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.217.07:34:39.53#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.217.07:34:39.53#ibcon#enter wrdev, iclass 21, count 0 2006.217.07:34:39.53#ibcon#first serial, iclass 21, count 0 2006.217.07:34:39.53#ibcon#enter sib2, iclass 21, count 0 2006.217.07:34:39.53#ibcon#flushed, iclass 21, count 0 2006.217.07:34:39.53#ibcon#about to write, iclass 21, count 0 2006.217.07:34:39.53#ibcon#wrote, iclass 21, count 0 2006.217.07:34:39.53#ibcon#about to read 3, iclass 21, count 0 2006.217.07:34:39.55#ibcon#read 3, iclass 21, count 0 2006.217.07:34:39.55#ibcon#about to read 4, iclass 21, count 0 2006.217.07:34:39.55#ibcon#read 4, iclass 21, count 0 2006.217.07:34:39.55#ibcon#about to read 5, iclass 21, count 0 2006.217.07:34:39.55#ibcon#read 5, iclass 21, count 0 2006.217.07:34:39.55#ibcon#about to read 6, iclass 21, count 0 2006.217.07:34:39.55#ibcon#read 6, iclass 21, count 0 2006.217.07:34:39.55#ibcon#end of sib2, iclass 21, count 0 2006.217.07:34:39.55#ibcon#*mode == 0, iclass 21, count 0 2006.217.07:34:39.55#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.217.07:34:39.55#ibcon#[25=USB\r\n] 2006.217.07:34:39.55#ibcon#*before write, iclass 21, count 0 2006.217.07:34:39.55#ibcon#enter sib2, iclass 21, count 0 2006.217.07:34:39.55#ibcon#flushed, iclass 21, count 0 2006.217.07:34:39.55#ibcon#about to write, iclass 21, count 0 2006.217.07:34:39.55#ibcon#wrote, iclass 21, count 0 2006.217.07:34:39.55#ibcon#about to read 3, iclass 21, count 0 2006.217.07:34:39.58#ibcon#read 3, iclass 21, count 0 2006.217.07:34:39.58#ibcon#about to read 4, iclass 21, count 0 2006.217.07:34:39.58#ibcon#read 4, iclass 21, count 0 2006.217.07:34:39.58#ibcon#about to read 5, iclass 21, count 0 2006.217.07:34:39.58#ibcon#read 5, iclass 21, count 0 2006.217.07:34:39.58#ibcon#about to read 6, iclass 21, count 0 2006.217.07:34:39.58#ibcon#read 6, iclass 21, count 0 2006.217.07:34:39.58#ibcon#end of sib2, iclass 21, count 0 2006.217.07:34:39.58#ibcon#*after write, iclass 21, count 0 2006.217.07:34:39.58#ibcon#*before return 0, iclass 21, count 0 2006.217.07:34:39.58#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.217.07:34:39.58#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.217.07:34:39.58#ibcon#about to clear, iclass 21 cls_cnt 0 2006.217.07:34:39.58#ibcon#cleared, iclass 21 cls_cnt 0 2006.217.07:34:39.58$vc4f8/valo=6,772.99 2006.217.07:34:39.58#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.217.07:34:39.58#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.217.07:34:39.58#ibcon#ireg 17 cls_cnt 0 2006.217.07:34:39.58#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.217.07:34:39.58#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.217.07:34:39.58#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.217.07:34:39.58#ibcon#enter wrdev, iclass 23, count 0 2006.217.07:34:39.58#ibcon#first serial, iclass 23, count 0 2006.217.07:34:39.58#ibcon#enter sib2, iclass 23, count 0 2006.217.07:34:39.58#ibcon#flushed, iclass 23, count 0 2006.217.07:34:39.58#ibcon#about to write, iclass 23, count 0 2006.217.07:34:39.58#ibcon#wrote, iclass 23, count 0 2006.217.07:34:39.58#ibcon#about to read 3, iclass 23, count 0 2006.217.07:34:39.60#ibcon#read 3, iclass 23, count 0 2006.217.07:34:39.60#ibcon#about to read 4, iclass 23, count 0 2006.217.07:34:39.60#ibcon#read 4, iclass 23, count 0 2006.217.07:34:39.60#ibcon#about to read 5, iclass 23, count 0 2006.217.07:34:39.60#ibcon#read 5, iclass 23, count 0 2006.217.07:34:39.60#ibcon#about to read 6, iclass 23, count 0 2006.217.07:34:39.60#ibcon#read 6, iclass 23, count 0 2006.217.07:34:39.60#ibcon#end of sib2, iclass 23, count 0 2006.217.07:34:39.60#ibcon#*mode == 0, iclass 23, count 0 2006.217.07:34:39.60#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.217.07:34:39.60#ibcon#[26=FRQ=06,772.99\r\n] 2006.217.07:34:39.60#ibcon#*before write, iclass 23, count 0 2006.217.07:34:39.60#ibcon#enter sib2, iclass 23, count 0 2006.217.07:34:39.60#ibcon#flushed, iclass 23, count 0 2006.217.07:34:39.60#ibcon#about to write, iclass 23, count 0 2006.217.07:34:39.60#ibcon#wrote, iclass 23, count 0 2006.217.07:34:39.60#ibcon#about to read 3, iclass 23, count 0 2006.217.07:34:39.64#ibcon#read 3, iclass 23, count 0 2006.217.07:34:39.64#ibcon#about to read 4, iclass 23, count 0 2006.217.07:34:39.64#ibcon#read 4, iclass 23, count 0 2006.217.07:34:39.64#ibcon#about to read 5, iclass 23, count 0 2006.217.07:34:39.64#ibcon#read 5, iclass 23, count 0 2006.217.07:34:39.64#ibcon#about to read 6, iclass 23, count 0 2006.217.07:34:39.64#ibcon#read 6, iclass 23, count 0 2006.217.07:34:39.64#ibcon#end of sib2, iclass 23, count 0 2006.217.07:34:39.64#ibcon#*after write, iclass 23, count 0 2006.217.07:34:39.64#ibcon#*before return 0, iclass 23, count 0 2006.217.07:34:39.64#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.217.07:34:39.64#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.217.07:34:39.64#ibcon#about to clear, iclass 23 cls_cnt 0 2006.217.07:34:39.64#ibcon#cleared, iclass 23 cls_cnt 0 2006.217.07:34:39.64$vc4f8/va=6,6 2006.217.07:34:39.64#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.217.07:34:39.64#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.217.07:34:39.64#ibcon#ireg 11 cls_cnt 2 2006.217.07:34:39.64#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.217.07:34:39.70#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.217.07:34:39.70#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.217.07:34:39.70#ibcon#enter wrdev, iclass 25, count 2 2006.217.07:34:39.70#ibcon#first serial, iclass 25, count 2 2006.217.07:34:39.70#ibcon#enter sib2, iclass 25, count 2 2006.217.07:34:39.70#ibcon#flushed, iclass 25, count 2 2006.217.07:34:39.70#ibcon#about to write, iclass 25, count 2 2006.217.07:34:39.70#ibcon#wrote, iclass 25, count 2 2006.217.07:34:39.70#ibcon#about to read 3, iclass 25, count 2 2006.217.07:34:39.72#ibcon#read 3, iclass 25, count 2 2006.217.07:34:39.72#ibcon#about to read 4, iclass 25, count 2 2006.217.07:34:39.72#ibcon#read 4, iclass 25, count 2 2006.217.07:34:39.72#ibcon#about to read 5, iclass 25, count 2 2006.217.07:34:39.72#ibcon#read 5, iclass 25, count 2 2006.217.07:34:39.72#ibcon#about to read 6, iclass 25, count 2 2006.217.07:34:39.72#ibcon#read 6, iclass 25, count 2 2006.217.07:34:39.72#ibcon#end of sib2, iclass 25, count 2 2006.217.07:34:39.72#ibcon#*mode == 0, iclass 25, count 2 2006.217.07:34:39.72#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.217.07:34:39.72#ibcon#[25=AT06-06\r\n] 2006.217.07:34:39.72#ibcon#*before write, iclass 25, count 2 2006.217.07:34:39.72#ibcon#enter sib2, iclass 25, count 2 2006.217.07:34:39.72#ibcon#flushed, iclass 25, count 2 2006.217.07:34:39.72#ibcon#about to write, iclass 25, count 2 2006.217.07:34:39.72#ibcon#wrote, iclass 25, count 2 2006.217.07:34:39.72#ibcon#about to read 3, iclass 25, count 2 2006.217.07:34:39.75#ibcon#read 3, iclass 25, count 2 2006.217.07:34:39.75#ibcon#about to read 4, iclass 25, count 2 2006.217.07:34:39.75#ibcon#read 4, iclass 25, count 2 2006.217.07:34:39.75#ibcon#about to read 5, iclass 25, count 2 2006.217.07:34:39.75#ibcon#read 5, iclass 25, count 2 2006.217.07:34:39.75#ibcon#about to read 6, iclass 25, count 2 2006.217.07:34:39.75#ibcon#read 6, iclass 25, count 2 2006.217.07:34:39.75#ibcon#end of sib2, iclass 25, count 2 2006.217.07:34:39.75#ibcon#*after write, iclass 25, count 2 2006.217.07:34:39.75#ibcon#*before return 0, iclass 25, count 2 2006.217.07:34:39.75#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.217.07:34:39.75#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.217.07:34:39.75#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.217.07:34:39.75#ibcon#ireg 7 cls_cnt 0 2006.217.07:34:39.75#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.217.07:34:39.87#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.217.07:34:39.87#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.217.07:34:39.87#ibcon#enter wrdev, iclass 25, count 0 2006.217.07:34:39.87#ibcon#first serial, iclass 25, count 0 2006.217.07:34:39.87#ibcon#enter sib2, iclass 25, count 0 2006.217.07:34:39.87#ibcon#flushed, iclass 25, count 0 2006.217.07:34:39.87#ibcon#about to write, iclass 25, count 0 2006.217.07:34:39.87#ibcon#wrote, iclass 25, count 0 2006.217.07:34:39.87#ibcon#about to read 3, iclass 25, count 0 2006.217.07:34:39.89#ibcon#read 3, iclass 25, count 0 2006.217.07:34:39.89#ibcon#about to read 4, iclass 25, count 0 2006.217.07:34:39.89#ibcon#read 4, iclass 25, count 0 2006.217.07:34:39.89#ibcon#about to read 5, iclass 25, count 0 2006.217.07:34:39.89#ibcon#read 5, iclass 25, count 0 2006.217.07:34:39.89#ibcon#about to read 6, iclass 25, count 0 2006.217.07:34:39.89#ibcon#read 6, iclass 25, count 0 2006.217.07:34:39.89#ibcon#end of sib2, iclass 25, count 0 2006.217.07:34:39.89#ibcon#*mode == 0, iclass 25, count 0 2006.217.07:34:39.89#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.217.07:34:39.89#ibcon#[25=USB\r\n] 2006.217.07:34:39.89#ibcon#*before write, iclass 25, count 0 2006.217.07:34:39.89#ibcon#enter sib2, iclass 25, count 0 2006.217.07:34:39.89#ibcon#flushed, iclass 25, count 0 2006.217.07:34:39.89#ibcon#about to write, iclass 25, count 0 2006.217.07:34:39.89#ibcon#wrote, iclass 25, count 0 2006.217.07:34:39.89#ibcon#about to read 3, iclass 25, count 0 2006.217.07:34:39.92#ibcon#read 3, iclass 25, count 0 2006.217.07:34:39.92#ibcon#about to read 4, iclass 25, count 0 2006.217.07:34:39.92#ibcon#read 4, iclass 25, count 0 2006.217.07:34:39.92#ibcon#about to read 5, iclass 25, count 0 2006.217.07:34:39.92#ibcon#read 5, iclass 25, count 0 2006.217.07:34:39.92#ibcon#about to read 6, iclass 25, count 0 2006.217.07:34:39.92#ibcon#read 6, iclass 25, count 0 2006.217.07:34:39.92#ibcon#end of sib2, iclass 25, count 0 2006.217.07:34:39.92#ibcon#*after write, iclass 25, count 0 2006.217.07:34:39.92#ibcon#*before return 0, iclass 25, count 0 2006.217.07:34:39.92#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.217.07:34:39.92#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.217.07:34:39.92#ibcon#about to clear, iclass 25 cls_cnt 0 2006.217.07:34:39.92#ibcon#cleared, iclass 25 cls_cnt 0 2006.217.07:34:39.92$vc4f8/valo=7,832.99 2006.217.07:34:39.92#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.217.07:34:39.92#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.217.07:34:39.92#ibcon#ireg 17 cls_cnt 0 2006.217.07:34:39.92#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.217.07:34:39.92#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.217.07:34:39.92#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.217.07:34:39.92#ibcon#enter wrdev, iclass 27, count 0 2006.217.07:34:39.92#ibcon#first serial, iclass 27, count 0 2006.217.07:34:39.92#ibcon#enter sib2, iclass 27, count 0 2006.217.07:34:39.92#ibcon#flushed, iclass 27, count 0 2006.217.07:34:39.92#ibcon#about to write, iclass 27, count 0 2006.217.07:34:39.92#ibcon#wrote, iclass 27, count 0 2006.217.07:34:39.92#ibcon#about to read 3, iclass 27, count 0 2006.217.07:34:39.94#ibcon#read 3, iclass 27, count 0 2006.217.07:34:39.94#ibcon#about to read 4, iclass 27, count 0 2006.217.07:34:39.94#ibcon#read 4, iclass 27, count 0 2006.217.07:34:39.94#ibcon#about to read 5, iclass 27, count 0 2006.217.07:34:39.94#ibcon#read 5, iclass 27, count 0 2006.217.07:34:39.94#ibcon#about to read 6, iclass 27, count 0 2006.217.07:34:39.94#ibcon#read 6, iclass 27, count 0 2006.217.07:34:39.94#ibcon#end of sib2, iclass 27, count 0 2006.217.07:34:39.94#ibcon#*mode == 0, iclass 27, count 0 2006.217.07:34:39.94#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.217.07:34:39.94#ibcon#[26=FRQ=07,832.99\r\n] 2006.217.07:34:39.94#ibcon#*before write, iclass 27, count 0 2006.217.07:34:39.94#ibcon#enter sib2, iclass 27, count 0 2006.217.07:34:39.94#ibcon#flushed, iclass 27, count 0 2006.217.07:34:39.94#ibcon#about to write, iclass 27, count 0 2006.217.07:34:39.94#ibcon#wrote, iclass 27, count 0 2006.217.07:34:39.94#ibcon#about to read 3, iclass 27, count 0 2006.217.07:34:39.98#ibcon#read 3, iclass 27, count 0 2006.217.07:34:39.98#ibcon#about to read 4, iclass 27, count 0 2006.217.07:34:39.98#ibcon#read 4, iclass 27, count 0 2006.217.07:34:39.98#ibcon#about to read 5, iclass 27, count 0 2006.217.07:34:39.98#ibcon#read 5, iclass 27, count 0 2006.217.07:34:39.98#ibcon#about to read 6, iclass 27, count 0 2006.217.07:34:39.98#ibcon#read 6, iclass 27, count 0 2006.217.07:34:39.98#ibcon#end of sib2, iclass 27, count 0 2006.217.07:34:39.98#ibcon#*after write, iclass 27, count 0 2006.217.07:34:39.98#ibcon#*before return 0, iclass 27, count 0 2006.217.07:34:39.98#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.217.07:34:39.98#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.217.07:34:39.98#ibcon#about to clear, iclass 27 cls_cnt 0 2006.217.07:34:39.98#ibcon#cleared, iclass 27 cls_cnt 0 2006.217.07:34:39.98$vc4f8/va=7,6 2006.217.07:34:39.98#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.217.07:34:39.98#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.217.07:34:39.98#ibcon#ireg 11 cls_cnt 2 2006.217.07:34:39.98#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.217.07:34:40.04#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.217.07:34:40.04#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.217.07:34:40.04#ibcon#enter wrdev, iclass 29, count 2 2006.217.07:34:40.04#ibcon#first serial, iclass 29, count 2 2006.217.07:34:40.04#ibcon#enter sib2, iclass 29, count 2 2006.217.07:34:40.04#ibcon#flushed, iclass 29, count 2 2006.217.07:34:40.04#ibcon#about to write, iclass 29, count 2 2006.217.07:34:40.04#ibcon#wrote, iclass 29, count 2 2006.217.07:34:40.04#ibcon#about to read 3, iclass 29, count 2 2006.217.07:34:40.06#ibcon#read 3, iclass 29, count 2 2006.217.07:34:40.06#ibcon#about to read 4, iclass 29, count 2 2006.217.07:34:40.06#ibcon#read 4, iclass 29, count 2 2006.217.07:34:40.06#ibcon#about to read 5, iclass 29, count 2 2006.217.07:34:40.06#ibcon#read 5, iclass 29, count 2 2006.217.07:34:40.06#ibcon#about to read 6, iclass 29, count 2 2006.217.07:34:40.06#ibcon#read 6, iclass 29, count 2 2006.217.07:34:40.06#ibcon#end of sib2, iclass 29, count 2 2006.217.07:34:40.06#ibcon#*mode == 0, iclass 29, count 2 2006.217.07:34:40.06#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.217.07:34:40.06#ibcon#[25=AT07-06\r\n] 2006.217.07:34:40.06#ibcon#*before write, iclass 29, count 2 2006.217.07:34:40.06#ibcon#enter sib2, iclass 29, count 2 2006.217.07:34:40.06#ibcon#flushed, iclass 29, count 2 2006.217.07:34:40.06#ibcon#about to write, iclass 29, count 2 2006.217.07:34:40.06#ibcon#wrote, iclass 29, count 2 2006.217.07:34:40.06#ibcon#about to read 3, iclass 29, count 2 2006.217.07:34:40.09#ibcon#read 3, iclass 29, count 2 2006.217.07:34:40.09#ibcon#about to read 4, iclass 29, count 2 2006.217.07:34:40.09#ibcon#read 4, iclass 29, count 2 2006.217.07:34:40.09#ibcon#about to read 5, iclass 29, count 2 2006.217.07:34:40.09#ibcon#read 5, iclass 29, count 2 2006.217.07:34:40.09#ibcon#about to read 6, iclass 29, count 2 2006.217.07:34:40.09#ibcon#read 6, iclass 29, count 2 2006.217.07:34:40.09#ibcon#end of sib2, iclass 29, count 2 2006.217.07:34:40.09#ibcon#*after write, iclass 29, count 2 2006.217.07:34:40.09#ibcon#*before return 0, iclass 29, count 2 2006.217.07:34:40.09#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.217.07:34:40.09#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.217.07:34:40.09#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.217.07:34:40.09#ibcon#ireg 7 cls_cnt 0 2006.217.07:34:40.09#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.217.07:34:40.21#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.217.07:34:40.21#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.217.07:34:40.21#ibcon#enter wrdev, iclass 29, count 0 2006.217.07:34:40.21#ibcon#first serial, iclass 29, count 0 2006.217.07:34:40.21#ibcon#enter sib2, iclass 29, count 0 2006.217.07:34:40.21#ibcon#flushed, iclass 29, count 0 2006.217.07:34:40.21#ibcon#about to write, iclass 29, count 0 2006.217.07:34:40.21#ibcon#wrote, iclass 29, count 0 2006.217.07:34:40.21#ibcon#about to read 3, iclass 29, count 0 2006.217.07:34:40.23#ibcon#read 3, iclass 29, count 0 2006.217.07:34:40.23#ibcon#about to read 4, iclass 29, count 0 2006.217.07:34:40.23#ibcon#read 4, iclass 29, count 0 2006.217.07:34:40.23#ibcon#about to read 5, iclass 29, count 0 2006.217.07:34:40.23#ibcon#read 5, iclass 29, count 0 2006.217.07:34:40.23#ibcon#about to read 6, iclass 29, count 0 2006.217.07:34:40.23#ibcon#read 6, iclass 29, count 0 2006.217.07:34:40.23#ibcon#end of sib2, iclass 29, count 0 2006.217.07:34:40.23#ibcon#*mode == 0, iclass 29, count 0 2006.217.07:34:40.23#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.217.07:34:40.23#ibcon#[25=USB\r\n] 2006.217.07:34:40.23#ibcon#*before write, iclass 29, count 0 2006.217.07:34:40.23#ibcon#enter sib2, iclass 29, count 0 2006.217.07:34:40.23#ibcon#flushed, iclass 29, count 0 2006.217.07:34:40.23#ibcon#about to write, iclass 29, count 0 2006.217.07:34:40.23#ibcon#wrote, iclass 29, count 0 2006.217.07:34:40.23#ibcon#about to read 3, iclass 29, count 0 2006.217.07:34:40.26#ibcon#read 3, iclass 29, count 0 2006.217.07:34:40.26#ibcon#about to read 4, iclass 29, count 0 2006.217.07:34:40.26#ibcon#read 4, iclass 29, count 0 2006.217.07:34:40.26#ibcon#about to read 5, iclass 29, count 0 2006.217.07:34:40.26#ibcon#read 5, iclass 29, count 0 2006.217.07:34:40.26#ibcon#about to read 6, iclass 29, count 0 2006.217.07:34:40.26#ibcon#read 6, iclass 29, count 0 2006.217.07:34:40.26#ibcon#end of sib2, iclass 29, count 0 2006.217.07:34:40.26#ibcon#*after write, iclass 29, count 0 2006.217.07:34:40.26#ibcon#*before return 0, iclass 29, count 0 2006.217.07:34:40.26#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.217.07:34:40.26#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.217.07:34:40.26#ibcon#about to clear, iclass 29 cls_cnt 0 2006.217.07:34:40.26#ibcon#cleared, iclass 29 cls_cnt 0 2006.217.07:34:40.26$vc4f8/valo=8,852.99 2006.217.07:34:40.26#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.217.07:34:40.26#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.217.07:34:40.26#ibcon#ireg 17 cls_cnt 0 2006.217.07:34:40.26#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.217.07:34:40.26#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.217.07:34:40.26#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.217.07:34:40.26#ibcon#enter wrdev, iclass 31, count 0 2006.217.07:34:40.26#ibcon#first serial, iclass 31, count 0 2006.217.07:34:40.26#ibcon#enter sib2, iclass 31, count 0 2006.217.07:34:40.26#ibcon#flushed, iclass 31, count 0 2006.217.07:34:40.26#ibcon#about to write, iclass 31, count 0 2006.217.07:34:40.26#ibcon#wrote, iclass 31, count 0 2006.217.07:34:40.26#ibcon#about to read 3, iclass 31, count 0 2006.217.07:34:40.28#ibcon#read 3, iclass 31, count 0 2006.217.07:34:40.28#ibcon#about to read 4, iclass 31, count 0 2006.217.07:34:40.28#ibcon#read 4, iclass 31, count 0 2006.217.07:34:40.28#ibcon#about to read 5, iclass 31, count 0 2006.217.07:34:40.28#ibcon#read 5, iclass 31, count 0 2006.217.07:34:40.28#ibcon#about to read 6, iclass 31, count 0 2006.217.07:34:40.28#ibcon#read 6, iclass 31, count 0 2006.217.07:34:40.28#ibcon#end of sib2, iclass 31, count 0 2006.217.07:34:40.28#ibcon#*mode == 0, iclass 31, count 0 2006.217.07:34:40.28#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.217.07:34:40.28#ibcon#[26=FRQ=08,852.99\r\n] 2006.217.07:34:40.28#ibcon#*before write, iclass 31, count 0 2006.217.07:34:40.28#ibcon#enter sib2, iclass 31, count 0 2006.217.07:34:40.28#ibcon#flushed, iclass 31, count 0 2006.217.07:34:40.28#ibcon#about to write, iclass 31, count 0 2006.217.07:34:40.28#ibcon#wrote, iclass 31, count 0 2006.217.07:34:40.28#ibcon#about to read 3, iclass 31, count 0 2006.217.07:34:40.32#ibcon#read 3, iclass 31, count 0 2006.217.07:34:40.32#ibcon#about to read 4, iclass 31, count 0 2006.217.07:34:40.32#ibcon#read 4, iclass 31, count 0 2006.217.07:34:40.32#ibcon#about to read 5, iclass 31, count 0 2006.217.07:34:40.32#ibcon#read 5, iclass 31, count 0 2006.217.07:34:40.32#ibcon#about to read 6, iclass 31, count 0 2006.217.07:34:40.32#ibcon#read 6, iclass 31, count 0 2006.217.07:34:40.32#ibcon#end of sib2, iclass 31, count 0 2006.217.07:34:40.32#ibcon#*after write, iclass 31, count 0 2006.217.07:34:40.32#ibcon#*before return 0, iclass 31, count 0 2006.217.07:34:40.32#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.217.07:34:40.32#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.217.07:34:40.32#ibcon#about to clear, iclass 31 cls_cnt 0 2006.217.07:34:40.32#ibcon#cleared, iclass 31 cls_cnt 0 2006.217.07:34:40.32$vc4f8/va=8,7 2006.217.07:34:40.32#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.217.07:34:40.32#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.217.07:34:40.32#ibcon#ireg 11 cls_cnt 2 2006.217.07:34:40.32#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.217.07:34:40.38#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.217.07:34:40.38#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.217.07:34:40.38#ibcon#enter wrdev, iclass 33, count 2 2006.217.07:34:40.38#ibcon#first serial, iclass 33, count 2 2006.217.07:34:40.38#ibcon#enter sib2, iclass 33, count 2 2006.217.07:34:40.38#ibcon#flushed, iclass 33, count 2 2006.217.07:34:40.38#ibcon#about to write, iclass 33, count 2 2006.217.07:34:40.38#ibcon#wrote, iclass 33, count 2 2006.217.07:34:40.38#ibcon#about to read 3, iclass 33, count 2 2006.217.07:34:40.40#ibcon#read 3, iclass 33, count 2 2006.217.07:34:40.40#ibcon#about to read 4, iclass 33, count 2 2006.217.07:34:40.40#ibcon#read 4, iclass 33, count 2 2006.217.07:34:40.40#ibcon#about to read 5, iclass 33, count 2 2006.217.07:34:40.40#ibcon#read 5, iclass 33, count 2 2006.217.07:34:40.40#ibcon#about to read 6, iclass 33, count 2 2006.217.07:34:40.40#ibcon#read 6, iclass 33, count 2 2006.217.07:34:40.40#ibcon#end of sib2, iclass 33, count 2 2006.217.07:34:40.40#ibcon#*mode == 0, iclass 33, count 2 2006.217.07:34:40.40#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.217.07:34:40.40#ibcon#[25=AT08-07\r\n] 2006.217.07:34:40.40#ibcon#*before write, iclass 33, count 2 2006.217.07:34:40.40#ibcon#enter sib2, iclass 33, count 2 2006.217.07:34:40.40#ibcon#flushed, iclass 33, count 2 2006.217.07:34:40.40#ibcon#about to write, iclass 33, count 2 2006.217.07:34:40.40#ibcon#wrote, iclass 33, count 2 2006.217.07:34:40.40#ibcon#about to read 3, iclass 33, count 2 2006.217.07:34:40.43#ibcon#read 3, iclass 33, count 2 2006.217.07:34:40.43#ibcon#about to read 4, iclass 33, count 2 2006.217.07:34:40.43#ibcon#read 4, iclass 33, count 2 2006.217.07:34:40.43#ibcon#about to read 5, iclass 33, count 2 2006.217.07:34:40.43#ibcon#read 5, iclass 33, count 2 2006.217.07:34:40.43#ibcon#about to read 6, iclass 33, count 2 2006.217.07:34:40.43#ibcon#read 6, iclass 33, count 2 2006.217.07:34:40.43#ibcon#end of sib2, iclass 33, count 2 2006.217.07:34:40.43#ibcon#*after write, iclass 33, count 2 2006.217.07:34:40.43#ibcon#*before return 0, iclass 33, count 2 2006.217.07:34:40.43#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.217.07:34:40.43#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.217.07:34:40.43#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.217.07:34:40.43#ibcon#ireg 7 cls_cnt 0 2006.217.07:34:40.43#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.217.07:34:40.55#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.217.07:34:40.55#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.217.07:34:40.55#ibcon#enter wrdev, iclass 33, count 0 2006.217.07:34:40.55#ibcon#first serial, iclass 33, count 0 2006.217.07:34:40.55#ibcon#enter sib2, iclass 33, count 0 2006.217.07:34:40.55#ibcon#flushed, iclass 33, count 0 2006.217.07:34:40.55#ibcon#about to write, iclass 33, count 0 2006.217.07:34:40.55#ibcon#wrote, iclass 33, count 0 2006.217.07:34:40.55#ibcon#about to read 3, iclass 33, count 0 2006.217.07:34:40.57#ibcon#read 3, iclass 33, count 0 2006.217.07:34:40.57#ibcon#about to read 4, iclass 33, count 0 2006.217.07:34:40.57#ibcon#read 4, iclass 33, count 0 2006.217.07:34:40.57#ibcon#about to read 5, iclass 33, count 0 2006.217.07:34:40.57#ibcon#read 5, iclass 33, count 0 2006.217.07:34:40.57#ibcon#about to read 6, iclass 33, count 0 2006.217.07:34:40.57#ibcon#read 6, iclass 33, count 0 2006.217.07:34:40.57#ibcon#end of sib2, iclass 33, count 0 2006.217.07:34:40.57#ibcon#*mode == 0, iclass 33, count 0 2006.217.07:34:40.57#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.217.07:34:40.57#ibcon#[25=USB\r\n] 2006.217.07:34:40.57#ibcon#*before write, iclass 33, count 0 2006.217.07:34:40.57#ibcon#enter sib2, iclass 33, count 0 2006.217.07:34:40.57#ibcon#flushed, iclass 33, count 0 2006.217.07:34:40.57#ibcon#about to write, iclass 33, count 0 2006.217.07:34:40.57#ibcon#wrote, iclass 33, count 0 2006.217.07:34:40.57#ibcon#about to read 3, iclass 33, count 0 2006.217.07:34:40.60#ibcon#read 3, iclass 33, count 0 2006.217.07:34:40.60#ibcon#about to read 4, iclass 33, count 0 2006.217.07:34:40.60#ibcon#read 4, iclass 33, count 0 2006.217.07:34:40.60#ibcon#about to read 5, iclass 33, count 0 2006.217.07:34:40.60#ibcon#read 5, iclass 33, count 0 2006.217.07:34:40.60#ibcon#about to read 6, iclass 33, count 0 2006.217.07:34:40.60#ibcon#read 6, iclass 33, count 0 2006.217.07:34:40.60#ibcon#end of sib2, iclass 33, count 0 2006.217.07:34:40.60#ibcon#*after write, iclass 33, count 0 2006.217.07:34:40.60#ibcon#*before return 0, iclass 33, count 0 2006.217.07:34:40.60#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.217.07:34:40.60#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.217.07:34:40.60#ibcon#about to clear, iclass 33 cls_cnt 0 2006.217.07:34:40.60#ibcon#cleared, iclass 33 cls_cnt 0 2006.217.07:34:40.60$vc4f8/vblo=1,632.99 2006.217.07:34:40.60#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.217.07:34:40.60#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.217.07:34:40.60#ibcon#ireg 17 cls_cnt 0 2006.217.07:34:40.60#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.217.07:34:40.60#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.217.07:34:40.60#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.217.07:34:40.60#ibcon#enter wrdev, iclass 35, count 0 2006.217.07:34:40.60#ibcon#first serial, iclass 35, count 0 2006.217.07:34:40.60#ibcon#enter sib2, iclass 35, count 0 2006.217.07:34:40.60#ibcon#flushed, iclass 35, count 0 2006.217.07:34:40.60#ibcon#about to write, iclass 35, count 0 2006.217.07:34:40.60#ibcon#wrote, iclass 35, count 0 2006.217.07:34:40.60#ibcon#about to read 3, iclass 35, count 0 2006.217.07:34:40.62#ibcon#read 3, iclass 35, count 0 2006.217.07:34:40.62#ibcon#about to read 4, iclass 35, count 0 2006.217.07:34:40.62#ibcon#read 4, iclass 35, count 0 2006.217.07:34:40.62#ibcon#about to read 5, iclass 35, count 0 2006.217.07:34:40.62#ibcon#read 5, iclass 35, count 0 2006.217.07:34:40.62#ibcon#about to read 6, iclass 35, count 0 2006.217.07:34:40.62#ibcon#read 6, iclass 35, count 0 2006.217.07:34:40.62#ibcon#end of sib2, iclass 35, count 0 2006.217.07:34:40.62#ibcon#*mode == 0, iclass 35, count 0 2006.217.07:34:40.62#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.217.07:34:40.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.217.07:34:40.62#ibcon#*before write, iclass 35, count 0 2006.217.07:34:40.62#ibcon#enter sib2, iclass 35, count 0 2006.217.07:34:40.62#ibcon#flushed, iclass 35, count 0 2006.217.07:34:40.62#ibcon#about to write, iclass 35, count 0 2006.217.07:34:40.62#ibcon#wrote, iclass 35, count 0 2006.217.07:34:40.62#ibcon#about to read 3, iclass 35, count 0 2006.217.07:34:40.67#ibcon#read 3, iclass 35, count 0 2006.217.07:34:40.67#ibcon#about to read 4, iclass 35, count 0 2006.217.07:34:40.67#ibcon#read 4, iclass 35, count 0 2006.217.07:34:40.67#ibcon#about to read 5, iclass 35, count 0 2006.217.07:34:40.67#ibcon#read 5, iclass 35, count 0 2006.217.07:34:40.67#ibcon#about to read 6, iclass 35, count 0 2006.217.07:34:40.67#ibcon#read 6, iclass 35, count 0 2006.217.07:34:40.67#ibcon#end of sib2, iclass 35, count 0 2006.217.07:34:40.67#ibcon#*after write, iclass 35, count 0 2006.217.07:34:40.67#ibcon#*before return 0, iclass 35, count 0 2006.217.07:34:40.67#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.217.07:34:40.67#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.217.07:34:40.67#ibcon#about to clear, iclass 35 cls_cnt 0 2006.217.07:34:40.67#ibcon#cleared, iclass 35 cls_cnt 0 2006.217.07:34:40.67$vc4f8/vb=1,4 2006.217.07:34:40.67#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.217.07:34:40.67#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.217.07:34:40.67#ibcon#ireg 11 cls_cnt 2 2006.217.07:34:40.67#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.217.07:34:40.67#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.217.07:34:40.67#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.217.07:34:40.67#ibcon#enter wrdev, iclass 37, count 2 2006.217.07:34:40.67#ibcon#first serial, iclass 37, count 2 2006.217.07:34:40.67#ibcon#enter sib2, iclass 37, count 2 2006.217.07:34:40.67#ibcon#flushed, iclass 37, count 2 2006.217.07:34:40.67#ibcon#about to write, iclass 37, count 2 2006.217.07:34:40.67#ibcon#wrote, iclass 37, count 2 2006.217.07:34:40.67#ibcon#about to read 3, iclass 37, count 2 2006.217.07:34:40.69#ibcon#read 3, iclass 37, count 2 2006.217.07:34:40.69#ibcon#about to read 4, iclass 37, count 2 2006.217.07:34:40.69#ibcon#read 4, iclass 37, count 2 2006.217.07:34:40.69#ibcon#about to read 5, iclass 37, count 2 2006.217.07:34:40.69#ibcon#read 5, iclass 37, count 2 2006.217.07:34:40.69#ibcon#about to read 6, iclass 37, count 2 2006.217.07:34:40.69#ibcon#read 6, iclass 37, count 2 2006.217.07:34:40.69#ibcon#end of sib2, iclass 37, count 2 2006.217.07:34:40.69#ibcon#*mode == 0, iclass 37, count 2 2006.217.07:34:40.69#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.217.07:34:40.69#ibcon#[27=AT01-04\r\n] 2006.217.07:34:40.69#ibcon#*before write, iclass 37, count 2 2006.217.07:34:40.69#ibcon#enter sib2, iclass 37, count 2 2006.217.07:34:40.69#ibcon#flushed, iclass 37, count 2 2006.217.07:34:40.69#ibcon#about to write, iclass 37, count 2 2006.217.07:34:40.69#ibcon#wrote, iclass 37, count 2 2006.217.07:34:40.69#ibcon#about to read 3, iclass 37, count 2 2006.217.07:34:40.72#ibcon#read 3, iclass 37, count 2 2006.217.07:34:40.72#ibcon#about to read 4, iclass 37, count 2 2006.217.07:34:40.72#ibcon#read 4, iclass 37, count 2 2006.217.07:34:40.72#ibcon#about to read 5, iclass 37, count 2 2006.217.07:34:40.72#ibcon#read 5, iclass 37, count 2 2006.217.07:34:40.72#ibcon#about to read 6, iclass 37, count 2 2006.217.07:34:40.72#ibcon#read 6, iclass 37, count 2 2006.217.07:34:40.72#ibcon#end of sib2, iclass 37, count 2 2006.217.07:34:40.72#ibcon#*after write, iclass 37, count 2 2006.217.07:34:40.72#ibcon#*before return 0, iclass 37, count 2 2006.217.07:34:40.72#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.217.07:34:40.72#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.217.07:34:40.72#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.217.07:34:40.72#ibcon#ireg 7 cls_cnt 0 2006.217.07:34:40.72#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.217.07:34:40.84#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.217.07:34:40.84#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.217.07:34:40.84#ibcon#enter wrdev, iclass 37, count 0 2006.217.07:34:40.84#ibcon#first serial, iclass 37, count 0 2006.217.07:34:40.84#ibcon#enter sib2, iclass 37, count 0 2006.217.07:34:40.84#ibcon#flushed, iclass 37, count 0 2006.217.07:34:40.84#ibcon#about to write, iclass 37, count 0 2006.217.07:34:40.84#ibcon#wrote, iclass 37, count 0 2006.217.07:34:40.84#ibcon#about to read 3, iclass 37, count 0 2006.217.07:34:40.86#ibcon#read 3, iclass 37, count 0 2006.217.07:34:40.86#ibcon#about to read 4, iclass 37, count 0 2006.217.07:34:40.86#ibcon#read 4, iclass 37, count 0 2006.217.07:34:40.86#ibcon#about to read 5, iclass 37, count 0 2006.217.07:34:40.86#ibcon#read 5, iclass 37, count 0 2006.217.07:34:40.86#ibcon#about to read 6, iclass 37, count 0 2006.217.07:34:40.86#ibcon#read 6, iclass 37, count 0 2006.217.07:34:40.86#ibcon#end of sib2, iclass 37, count 0 2006.217.07:34:40.86#ibcon#*mode == 0, iclass 37, count 0 2006.217.07:34:40.86#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.217.07:34:40.86#ibcon#[27=USB\r\n] 2006.217.07:34:40.86#ibcon#*before write, iclass 37, count 0 2006.217.07:34:40.86#ibcon#enter sib2, iclass 37, count 0 2006.217.07:34:40.86#ibcon#flushed, iclass 37, count 0 2006.217.07:34:40.86#ibcon#about to write, iclass 37, count 0 2006.217.07:34:40.86#ibcon#wrote, iclass 37, count 0 2006.217.07:34:40.86#ibcon#about to read 3, iclass 37, count 0 2006.217.07:34:40.89#ibcon#read 3, iclass 37, count 0 2006.217.07:34:40.89#ibcon#about to read 4, iclass 37, count 0 2006.217.07:34:40.89#ibcon#read 4, iclass 37, count 0 2006.217.07:34:40.89#ibcon#about to read 5, iclass 37, count 0 2006.217.07:34:40.89#ibcon#read 5, iclass 37, count 0 2006.217.07:34:40.89#ibcon#about to read 6, iclass 37, count 0 2006.217.07:34:40.89#ibcon#read 6, iclass 37, count 0 2006.217.07:34:40.89#ibcon#end of sib2, iclass 37, count 0 2006.217.07:34:40.89#ibcon#*after write, iclass 37, count 0 2006.217.07:34:40.89#ibcon#*before return 0, iclass 37, count 0 2006.217.07:34:40.89#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.217.07:34:40.89#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.217.07:34:40.89#ibcon#about to clear, iclass 37 cls_cnt 0 2006.217.07:34:40.89#ibcon#cleared, iclass 37 cls_cnt 0 2006.217.07:34:40.89$vc4f8/vblo=2,640.99 2006.217.07:34:40.89#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.217.07:34:40.89#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.217.07:34:40.89#ibcon#ireg 17 cls_cnt 0 2006.217.07:34:40.89#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.217.07:34:40.89#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.217.07:34:40.89#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.217.07:34:40.89#ibcon#enter wrdev, iclass 39, count 0 2006.217.07:34:40.89#ibcon#first serial, iclass 39, count 0 2006.217.07:34:40.89#ibcon#enter sib2, iclass 39, count 0 2006.217.07:34:40.89#ibcon#flushed, iclass 39, count 0 2006.217.07:34:40.89#ibcon#about to write, iclass 39, count 0 2006.217.07:34:40.89#ibcon#wrote, iclass 39, count 0 2006.217.07:34:40.89#ibcon#about to read 3, iclass 39, count 0 2006.217.07:34:40.91#ibcon#read 3, iclass 39, count 0 2006.217.07:34:40.91#ibcon#about to read 4, iclass 39, count 0 2006.217.07:34:40.91#ibcon#read 4, iclass 39, count 0 2006.217.07:34:40.91#ibcon#about to read 5, iclass 39, count 0 2006.217.07:34:40.91#ibcon#read 5, iclass 39, count 0 2006.217.07:34:40.91#ibcon#about to read 6, iclass 39, count 0 2006.217.07:34:40.91#ibcon#read 6, iclass 39, count 0 2006.217.07:34:40.91#ibcon#end of sib2, iclass 39, count 0 2006.217.07:34:40.91#ibcon#*mode == 0, iclass 39, count 0 2006.217.07:34:40.91#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.217.07:34:40.91#ibcon#[28=FRQ=02,640.99\r\n] 2006.217.07:34:40.91#ibcon#*before write, iclass 39, count 0 2006.217.07:34:40.91#ibcon#enter sib2, iclass 39, count 0 2006.217.07:34:40.91#ibcon#flushed, iclass 39, count 0 2006.217.07:34:40.91#ibcon#about to write, iclass 39, count 0 2006.217.07:34:40.91#ibcon#wrote, iclass 39, count 0 2006.217.07:34:40.91#ibcon#about to read 3, iclass 39, count 0 2006.217.07:34:40.95#ibcon#read 3, iclass 39, count 0 2006.217.07:34:40.95#ibcon#about to read 4, iclass 39, count 0 2006.217.07:34:40.95#ibcon#read 4, iclass 39, count 0 2006.217.07:34:40.95#ibcon#about to read 5, iclass 39, count 0 2006.217.07:34:40.95#ibcon#read 5, iclass 39, count 0 2006.217.07:34:40.95#ibcon#about to read 6, iclass 39, count 0 2006.217.07:34:40.95#ibcon#read 6, iclass 39, count 0 2006.217.07:34:40.95#ibcon#end of sib2, iclass 39, count 0 2006.217.07:34:40.95#ibcon#*after write, iclass 39, count 0 2006.217.07:34:40.95#ibcon#*before return 0, iclass 39, count 0 2006.217.07:34:40.95#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.217.07:34:40.95#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.217.07:34:40.95#ibcon#about to clear, iclass 39 cls_cnt 0 2006.217.07:34:40.95#ibcon#cleared, iclass 39 cls_cnt 0 2006.217.07:34:40.95$vc4f8/vb=2,4 2006.217.07:34:40.95#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.217.07:34:40.95#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.217.07:34:40.95#ibcon#ireg 11 cls_cnt 2 2006.217.07:34:40.95#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.217.07:34:41.01#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.217.07:34:41.01#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.217.07:34:41.01#ibcon#enter wrdev, iclass 3, count 2 2006.217.07:34:41.01#ibcon#first serial, iclass 3, count 2 2006.217.07:34:41.01#ibcon#enter sib2, iclass 3, count 2 2006.217.07:34:41.01#ibcon#flushed, iclass 3, count 2 2006.217.07:34:41.01#ibcon#about to write, iclass 3, count 2 2006.217.07:34:41.01#ibcon#wrote, iclass 3, count 2 2006.217.07:34:41.01#ibcon#about to read 3, iclass 3, count 2 2006.217.07:34:41.03#ibcon#read 3, iclass 3, count 2 2006.217.07:34:41.03#ibcon#about to read 4, iclass 3, count 2 2006.217.07:34:41.03#ibcon#read 4, iclass 3, count 2 2006.217.07:34:41.03#ibcon#about to read 5, iclass 3, count 2 2006.217.07:34:41.03#ibcon#read 5, iclass 3, count 2 2006.217.07:34:41.03#ibcon#about to read 6, iclass 3, count 2 2006.217.07:34:41.03#ibcon#read 6, iclass 3, count 2 2006.217.07:34:41.03#ibcon#end of sib2, iclass 3, count 2 2006.217.07:34:41.03#ibcon#*mode == 0, iclass 3, count 2 2006.217.07:34:41.03#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.217.07:34:41.03#ibcon#[27=AT02-04\r\n] 2006.217.07:34:41.03#ibcon#*before write, iclass 3, count 2 2006.217.07:34:41.03#ibcon#enter sib2, iclass 3, count 2 2006.217.07:34:41.03#ibcon#flushed, iclass 3, count 2 2006.217.07:34:41.03#ibcon#about to write, iclass 3, count 2 2006.217.07:34:41.03#ibcon#wrote, iclass 3, count 2 2006.217.07:34:41.03#ibcon#about to read 3, iclass 3, count 2 2006.217.07:34:41.06#ibcon#read 3, iclass 3, count 2 2006.217.07:34:41.06#ibcon#about to read 4, iclass 3, count 2 2006.217.07:34:41.06#ibcon#read 4, iclass 3, count 2 2006.217.07:34:41.06#ibcon#about to read 5, iclass 3, count 2 2006.217.07:34:41.06#ibcon#read 5, iclass 3, count 2 2006.217.07:34:41.06#ibcon#about to read 6, iclass 3, count 2 2006.217.07:34:41.06#ibcon#read 6, iclass 3, count 2 2006.217.07:34:41.06#ibcon#end of sib2, iclass 3, count 2 2006.217.07:34:41.06#ibcon#*after write, iclass 3, count 2 2006.217.07:34:41.06#ibcon#*before return 0, iclass 3, count 2 2006.217.07:34:41.06#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.217.07:34:41.06#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.217.07:34:41.06#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.217.07:34:41.06#ibcon#ireg 7 cls_cnt 0 2006.217.07:34:41.06#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.217.07:34:41.18#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.217.07:34:41.18#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.217.07:34:41.18#ibcon#enter wrdev, iclass 3, count 0 2006.217.07:34:41.18#ibcon#first serial, iclass 3, count 0 2006.217.07:34:41.18#ibcon#enter sib2, iclass 3, count 0 2006.217.07:34:41.18#ibcon#flushed, iclass 3, count 0 2006.217.07:34:41.18#ibcon#about to write, iclass 3, count 0 2006.217.07:34:41.18#ibcon#wrote, iclass 3, count 0 2006.217.07:34:41.18#ibcon#about to read 3, iclass 3, count 0 2006.217.07:34:41.20#ibcon#read 3, iclass 3, count 0 2006.217.07:34:41.20#ibcon#about to read 4, iclass 3, count 0 2006.217.07:34:41.20#ibcon#read 4, iclass 3, count 0 2006.217.07:34:41.20#ibcon#about to read 5, iclass 3, count 0 2006.217.07:34:41.20#ibcon#read 5, iclass 3, count 0 2006.217.07:34:41.20#ibcon#about to read 6, iclass 3, count 0 2006.217.07:34:41.20#ibcon#read 6, iclass 3, count 0 2006.217.07:34:41.20#ibcon#end of sib2, iclass 3, count 0 2006.217.07:34:41.20#ibcon#*mode == 0, iclass 3, count 0 2006.217.07:34:41.20#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.217.07:34:41.20#ibcon#[27=USB\r\n] 2006.217.07:34:41.20#ibcon#*before write, iclass 3, count 0 2006.217.07:34:41.20#ibcon#enter sib2, iclass 3, count 0 2006.217.07:34:41.20#ibcon#flushed, iclass 3, count 0 2006.217.07:34:41.20#ibcon#about to write, iclass 3, count 0 2006.217.07:34:41.20#ibcon#wrote, iclass 3, count 0 2006.217.07:34:41.20#ibcon#about to read 3, iclass 3, count 0 2006.217.07:34:41.23#ibcon#read 3, iclass 3, count 0 2006.217.07:34:41.23#ibcon#about to read 4, iclass 3, count 0 2006.217.07:34:41.23#ibcon#read 4, iclass 3, count 0 2006.217.07:34:41.23#ibcon#about to read 5, iclass 3, count 0 2006.217.07:34:41.23#ibcon#read 5, iclass 3, count 0 2006.217.07:34:41.23#ibcon#about to read 6, iclass 3, count 0 2006.217.07:34:41.23#ibcon#read 6, iclass 3, count 0 2006.217.07:34:41.23#ibcon#end of sib2, iclass 3, count 0 2006.217.07:34:41.23#ibcon#*after write, iclass 3, count 0 2006.217.07:34:41.23#ibcon#*before return 0, iclass 3, count 0 2006.217.07:34:41.23#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.217.07:34:41.23#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.217.07:34:41.23#ibcon#about to clear, iclass 3 cls_cnt 0 2006.217.07:34:41.23#ibcon#cleared, iclass 3 cls_cnt 0 2006.217.07:34:41.23$vc4f8/vblo=3,656.99 2006.217.07:34:41.23#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.217.07:34:41.23#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.217.07:34:41.23#ibcon#ireg 17 cls_cnt 0 2006.217.07:34:41.23#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.217.07:34:41.23#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.217.07:34:41.23#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.217.07:34:41.23#ibcon#enter wrdev, iclass 5, count 0 2006.217.07:34:41.23#ibcon#first serial, iclass 5, count 0 2006.217.07:34:41.23#ibcon#enter sib2, iclass 5, count 0 2006.217.07:34:41.23#ibcon#flushed, iclass 5, count 0 2006.217.07:34:41.23#ibcon#about to write, iclass 5, count 0 2006.217.07:34:41.23#ibcon#wrote, iclass 5, count 0 2006.217.07:34:41.23#ibcon#about to read 3, iclass 5, count 0 2006.217.07:34:41.25#ibcon#read 3, iclass 5, count 0 2006.217.07:34:41.25#ibcon#about to read 4, iclass 5, count 0 2006.217.07:34:41.25#ibcon#read 4, iclass 5, count 0 2006.217.07:34:41.25#ibcon#about to read 5, iclass 5, count 0 2006.217.07:34:41.25#ibcon#read 5, iclass 5, count 0 2006.217.07:34:41.25#ibcon#about to read 6, iclass 5, count 0 2006.217.07:34:41.25#ibcon#read 6, iclass 5, count 0 2006.217.07:34:41.25#ibcon#end of sib2, iclass 5, count 0 2006.217.07:34:41.25#ibcon#*mode == 0, iclass 5, count 0 2006.217.07:34:41.25#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.217.07:34:41.25#ibcon#[28=FRQ=03,656.99\r\n] 2006.217.07:34:41.25#ibcon#*before write, iclass 5, count 0 2006.217.07:34:41.25#ibcon#enter sib2, iclass 5, count 0 2006.217.07:34:41.25#ibcon#flushed, iclass 5, count 0 2006.217.07:34:41.25#ibcon#about to write, iclass 5, count 0 2006.217.07:34:41.25#ibcon#wrote, iclass 5, count 0 2006.217.07:34:41.25#ibcon#about to read 3, iclass 5, count 0 2006.217.07:34:41.29#ibcon#read 3, iclass 5, count 0 2006.217.07:34:41.29#ibcon#about to read 4, iclass 5, count 0 2006.217.07:34:41.29#ibcon#read 4, iclass 5, count 0 2006.217.07:34:41.29#ibcon#about to read 5, iclass 5, count 0 2006.217.07:34:41.29#ibcon#read 5, iclass 5, count 0 2006.217.07:34:41.29#ibcon#about to read 6, iclass 5, count 0 2006.217.07:34:41.29#ibcon#read 6, iclass 5, count 0 2006.217.07:34:41.29#ibcon#end of sib2, iclass 5, count 0 2006.217.07:34:41.29#ibcon#*after write, iclass 5, count 0 2006.217.07:34:41.29#ibcon#*before return 0, iclass 5, count 0 2006.217.07:34:41.29#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.217.07:34:41.29#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.217.07:34:41.29#ibcon#about to clear, iclass 5 cls_cnt 0 2006.217.07:34:41.29#ibcon#cleared, iclass 5 cls_cnt 0 2006.217.07:34:41.29$vc4f8/vb=3,4 2006.217.07:34:41.29#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.217.07:34:41.29#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.217.07:34:41.29#ibcon#ireg 11 cls_cnt 2 2006.217.07:34:41.29#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.217.07:34:41.35#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.217.07:34:41.35#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.217.07:34:41.35#ibcon#enter wrdev, iclass 7, count 2 2006.217.07:34:41.35#ibcon#first serial, iclass 7, count 2 2006.217.07:34:41.35#ibcon#enter sib2, iclass 7, count 2 2006.217.07:34:41.35#ibcon#flushed, iclass 7, count 2 2006.217.07:34:41.35#ibcon#about to write, iclass 7, count 2 2006.217.07:34:41.35#ibcon#wrote, iclass 7, count 2 2006.217.07:34:41.35#ibcon#about to read 3, iclass 7, count 2 2006.217.07:34:41.37#ibcon#read 3, iclass 7, count 2 2006.217.07:34:41.37#ibcon#about to read 4, iclass 7, count 2 2006.217.07:34:41.37#ibcon#read 4, iclass 7, count 2 2006.217.07:34:41.37#ibcon#about to read 5, iclass 7, count 2 2006.217.07:34:41.37#ibcon#read 5, iclass 7, count 2 2006.217.07:34:41.37#ibcon#about to read 6, iclass 7, count 2 2006.217.07:34:41.37#ibcon#read 6, iclass 7, count 2 2006.217.07:34:41.37#ibcon#end of sib2, iclass 7, count 2 2006.217.07:34:41.37#ibcon#*mode == 0, iclass 7, count 2 2006.217.07:34:41.37#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.217.07:34:41.37#ibcon#[27=AT03-04\r\n] 2006.217.07:34:41.37#ibcon#*before write, iclass 7, count 2 2006.217.07:34:41.37#ibcon#enter sib2, iclass 7, count 2 2006.217.07:34:41.37#ibcon#flushed, iclass 7, count 2 2006.217.07:34:41.37#ibcon#about to write, iclass 7, count 2 2006.217.07:34:41.37#ibcon#wrote, iclass 7, count 2 2006.217.07:34:41.37#ibcon#about to read 3, iclass 7, count 2 2006.217.07:34:41.40#ibcon#read 3, iclass 7, count 2 2006.217.07:34:41.40#ibcon#about to read 4, iclass 7, count 2 2006.217.07:34:41.40#ibcon#read 4, iclass 7, count 2 2006.217.07:34:41.40#ibcon#about to read 5, iclass 7, count 2 2006.217.07:34:41.40#ibcon#read 5, iclass 7, count 2 2006.217.07:34:41.40#ibcon#about to read 6, iclass 7, count 2 2006.217.07:34:41.40#ibcon#read 6, iclass 7, count 2 2006.217.07:34:41.40#ibcon#end of sib2, iclass 7, count 2 2006.217.07:34:41.40#ibcon#*after write, iclass 7, count 2 2006.217.07:34:41.40#ibcon#*before return 0, iclass 7, count 2 2006.217.07:34:41.40#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.217.07:34:41.40#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.217.07:34:41.40#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.217.07:34:41.40#ibcon#ireg 7 cls_cnt 0 2006.217.07:34:41.40#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.217.07:34:41.52#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.217.07:34:41.52#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.217.07:34:41.52#ibcon#enter wrdev, iclass 7, count 0 2006.217.07:34:41.52#ibcon#first serial, iclass 7, count 0 2006.217.07:34:41.52#ibcon#enter sib2, iclass 7, count 0 2006.217.07:34:41.52#ibcon#flushed, iclass 7, count 0 2006.217.07:34:41.52#ibcon#about to write, iclass 7, count 0 2006.217.07:34:41.52#ibcon#wrote, iclass 7, count 0 2006.217.07:34:41.52#ibcon#about to read 3, iclass 7, count 0 2006.217.07:34:41.54#ibcon#read 3, iclass 7, count 0 2006.217.07:34:41.54#ibcon#about to read 4, iclass 7, count 0 2006.217.07:34:41.54#ibcon#read 4, iclass 7, count 0 2006.217.07:34:41.54#ibcon#about to read 5, iclass 7, count 0 2006.217.07:34:41.54#ibcon#read 5, iclass 7, count 0 2006.217.07:34:41.54#ibcon#about to read 6, iclass 7, count 0 2006.217.07:34:41.54#ibcon#read 6, iclass 7, count 0 2006.217.07:34:41.54#ibcon#end of sib2, iclass 7, count 0 2006.217.07:34:41.54#ibcon#*mode == 0, iclass 7, count 0 2006.217.07:34:41.54#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.217.07:34:41.54#ibcon#[27=USB\r\n] 2006.217.07:34:41.54#ibcon#*before write, iclass 7, count 0 2006.217.07:34:41.54#ibcon#enter sib2, iclass 7, count 0 2006.217.07:34:41.54#ibcon#flushed, iclass 7, count 0 2006.217.07:34:41.54#ibcon#about to write, iclass 7, count 0 2006.217.07:34:41.54#ibcon#wrote, iclass 7, count 0 2006.217.07:34:41.54#ibcon#about to read 3, iclass 7, count 0 2006.217.07:34:41.57#ibcon#read 3, iclass 7, count 0 2006.217.07:34:41.57#ibcon#about to read 4, iclass 7, count 0 2006.217.07:34:41.57#ibcon#read 4, iclass 7, count 0 2006.217.07:34:41.57#ibcon#about to read 5, iclass 7, count 0 2006.217.07:34:41.57#ibcon#read 5, iclass 7, count 0 2006.217.07:34:41.57#ibcon#about to read 6, iclass 7, count 0 2006.217.07:34:41.57#ibcon#read 6, iclass 7, count 0 2006.217.07:34:41.57#ibcon#end of sib2, iclass 7, count 0 2006.217.07:34:41.57#ibcon#*after write, iclass 7, count 0 2006.217.07:34:41.57#ibcon#*before return 0, iclass 7, count 0 2006.217.07:34:41.57#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.217.07:34:41.57#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.217.07:34:41.57#ibcon#about to clear, iclass 7 cls_cnt 0 2006.217.07:34:41.57#ibcon#cleared, iclass 7 cls_cnt 0 2006.217.07:34:41.57$vc4f8/vblo=4,712.99 2006.217.07:34:41.57#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.217.07:34:41.57#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.217.07:34:41.57#ibcon#ireg 17 cls_cnt 0 2006.217.07:34:41.57#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.217.07:34:41.57#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.217.07:34:41.57#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.217.07:34:41.57#ibcon#enter wrdev, iclass 11, count 0 2006.217.07:34:41.57#ibcon#first serial, iclass 11, count 0 2006.217.07:34:41.57#ibcon#enter sib2, iclass 11, count 0 2006.217.07:34:41.57#ibcon#flushed, iclass 11, count 0 2006.217.07:34:41.57#ibcon#about to write, iclass 11, count 0 2006.217.07:34:41.57#ibcon#wrote, iclass 11, count 0 2006.217.07:34:41.57#ibcon#about to read 3, iclass 11, count 0 2006.217.07:34:41.59#ibcon#read 3, iclass 11, count 0 2006.217.07:34:41.59#ibcon#about to read 4, iclass 11, count 0 2006.217.07:34:41.59#ibcon#read 4, iclass 11, count 0 2006.217.07:34:41.59#ibcon#about to read 5, iclass 11, count 0 2006.217.07:34:41.59#ibcon#read 5, iclass 11, count 0 2006.217.07:34:41.59#ibcon#about to read 6, iclass 11, count 0 2006.217.07:34:41.59#ibcon#read 6, iclass 11, count 0 2006.217.07:34:41.59#ibcon#end of sib2, iclass 11, count 0 2006.217.07:34:41.59#ibcon#*mode == 0, iclass 11, count 0 2006.217.07:34:41.59#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.217.07:34:41.59#ibcon#[28=FRQ=04,712.99\r\n] 2006.217.07:34:41.59#ibcon#*before write, iclass 11, count 0 2006.217.07:34:41.59#ibcon#enter sib2, iclass 11, count 0 2006.217.07:34:41.59#ibcon#flushed, iclass 11, count 0 2006.217.07:34:41.59#ibcon#about to write, iclass 11, count 0 2006.217.07:34:41.59#ibcon#wrote, iclass 11, count 0 2006.217.07:34:41.59#ibcon#about to read 3, iclass 11, count 0 2006.217.07:34:41.63#ibcon#read 3, iclass 11, count 0 2006.217.07:34:41.63#ibcon#about to read 4, iclass 11, count 0 2006.217.07:34:41.63#ibcon#read 4, iclass 11, count 0 2006.217.07:34:41.63#ibcon#about to read 5, iclass 11, count 0 2006.217.07:34:41.63#ibcon#read 5, iclass 11, count 0 2006.217.07:34:41.63#ibcon#about to read 6, iclass 11, count 0 2006.217.07:34:41.63#ibcon#read 6, iclass 11, count 0 2006.217.07:34:41.63#ibcon#end of sib2, iclass 11, count 0 2006.217.07:34:41.63#ibcon#*after write, iclass 11, count 0 2006.217.07:34:41.63#ibcon#*before return 0, iclass 11, count 0 2006.217.07:34:41.63#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.217.07:34:41.63#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.217.07:34:41.63#ibcon#about to clear, iclass 11 cls_cnt 0 2006.217.07:34:41.63#ibcon#cleared, iclass 11 cls_cnt 0 2006.217.07:34:41.63$vc4f8/vb=4,4 2006.217.07:34:41.63#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.217.07:34:41.63#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.217.07:34:41.63#ibcon#ireg 11 cls_cnt 2 2006.217.07:34:41.63#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.217.07:34:41.69#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.217.07:34:41.69#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.217.07:34:41.69#ibcon#enter wrdev, iclass 13, count 2 2006.217.07:34:41.69#ibcon#first serial, iclass 13, count 2 2006.217.07:34:41.69#ibcon#enter sib2, iclass 13, count 2 2006.217.07:34:41.69#ibcon#flushed, iclass 13, count 2 2006.217.07:34:41.69#ibcon#about to write, iclass 13, count 2 2006.217.07:34:41.69#ibcon#wrote, iclass 13, count 2 2006.217.07:34:41.69#ibcon#about to read 3, iclass 13, count 2 2006.217.07:34:41.71#ibcon#read 3, iclass 13, count 2 2006.217.07:34:41.71#ibcon#about to read 4, iclass 13, count 2 2006.217.07:34:41.71#ibcon#read 4, iclass 13, count 2 2006.217.07:34:41.71#ibcon#about to read 5, iclass 13, count 2 2006.217.07:34:41.71#ibcon#read 5, iclass 13, count 2 2006.217.07:34:41.71#ibcon#about to read 6, iclass 13, count 2 2006.217.07:34:41.71#ibcon#read 6, iclass 13, count 2 2006.217.07:34:41.71#ibcon#end of sib2, iclass 13, count 2 2006.217.07:34:41.71#ibcon#*mode == 0, iclass 13, count 2 2006.217.07:34:41.71#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.217.07:34:41.71#ibcon#[27=AT04-04\r\n] 2006.217.07:34:41.71#ibcon#*before write, iclass 13, count 2 2006.217.07:34:41.71#ibcon#enter sib2, iclass 13, count 2 2006.217.07:34:41.71#ibcon#flushed, iclass 13, count 2 2006.217.07:34:41.71#ibcon#about to write, iclass 13, count 2 2006.217.07:34:41.71#ibcon#wrote, iclass 13, count 2 2006.217.07:34:41.71#ibcon#about to read 3, iclass 13, count 2 2006.217.07:34:41.74#ibcon#read 3, iclass 13, count 2 2006.217.07:34:41.74#ibcon#about to read 4, iclass 13, count 2 2006.217.07:34:41.74#ibcon#read 4, iclass 13, count 2 2006.217.07:34:41.74#ibcon#about to read 5, iclass 13, count 2 2006.217.07:34:41.74#ibcon#read 5, iclass 13, count 2 2006.217.07:34:41.74#ibcon#about to read 6, iclass 13, count 2 2006.217.07:34:41.74#ibcon#read 6, iclass 13, count 2 2006.217.07:34:41.74#ibcon#end of sib2, iclass 13, count 2 2006.217.07:34:41.74#ibcon#*after write, iclass 13, count 2 2006.217.07:34:41.74#ibcon#*before return 0, iclass 13, count 2 2006.217.07:34:41.74#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.217.07:34:41.74#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.217.07:34:41.74#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.217.07:34:41.74#ibcon#ireg 7 cls_cnt 0 2006.217.07:34:41.74#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.217.07:34:41.86#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.217.07:34:41.86#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.217.07:34:41.86#ibcon#enter wrdev, iclass 13, count 0 2006.217.07:34:41.86#ibcon#first serial, iclass 13, count 0 2006.217.07:34:41.86#ibcon#enter sib2, iclass 13, count 0 2006.217.07:34:41.86#ibcon#flushed, iclass 13, count 0 2006.217.07:34:41.86#ibcon#about to write, iclass 13, count 0 2006.217.07:34:41.86#ibcon#wrote, iclass 13, count 0 2006.217.07:34:41.86#ibcon#about to read 3, iclass 13, count 0 2006.217.07:34:41.88#ibcon#read 3, iclass 13, count 0 2006.217.07:34:41.88#ibcon#about to read 4, iclass 13, count 0 2006.217.07:34:41.88#ibcon#read 4, iclass 13, count 0 2006.217.07:34:41.88#ibcon#about to read 5, iclass 13, count 0 2006.217.07:34:41.88#ibcon#read 5, iclass 13, count 0 2006.217.07:34:41.88#ibcon#about to read 6, iclass 13, count 0 2006.217.07:34:41.88#ibcon#read 6, iclass 13, count 0 2006.217.07:34:41.88#ibcon#end of sib2, iclass 13, count 0 2006.217.07:34:41.88#ibcon#*mode == 0, iclass 13, count 0 2006.217.07:34:41.88#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.217.07:34:41.88#ibcon#[27=USB\r\n] 2006.217.07:34:41.88#ibcon#*before write, iclass 13, count 0 2006.217.07:34:41.88#ibcon#enter sib2, iclass 13, count 0 2006.217.07:34:41.88#ibcon#flushed, iclass 13, count 0 2006.217.07:34:41.88#ibcon#about to write, iclass 13, count 0 2006.217.07:34:41.88#ibcon#wrote, iclass 13, count 0 2006.217.07:34:41.88#ibcon#about to read 3, iclass 13, count 0 2006.217.07:34:41.91#ibcon#read 3, iclass 13, count 0 2006.217.07:34:41.91#ibcon#about to read 4, iclass 13, count 0 2006.217.07:34:41.91#ibcon#read 4, iclass 13, count 0 2006.217.07:34:41.91#ibcon#about to read 5, iclass 13, count 0 2006.217.07:34:41.91#ibcon#read 5, iclass 13, count 0 2006.217.07:34:41.91#ibcon#about to read 6, iclass 13, count 0 2006.217.07:34:41.91#ibcon#read 6, iclass 13, count 0 2006.217.07:34:41.91#ibcon#end of sib2, iclass 13, count 0 2006.217.07:34:41.91#ibcon#*after write, iclass 13, count 0 2006.217.07:34:41.91#ibcon#*before return 0, iclass 13, count 0 2006.217.07:34:41.91#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.217.07:34:41.91#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.217.07:34:41.91#ibcon#about to clear, iclass 13 cls_cnt 0 2006.217.07:34:41.91#ibcon#cleared, iclass 13 cls_cnt 0 2006.217.07:34:41.91$vc4f8/vblo=5,744.99 2006.217.07:34:41.91#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.217.07:34:41.91#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.217.07:34:41.91#ibcon#ireg 17 cls_cnt 0 2006.217.07:34:41.91#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.217.07:34:41.91#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.217.07:34:41.91#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.217.07:34:41.91#ibcon#enter wrdev, iclass 15, count 0 2006.217.07:34:41.91#ibcon#first serial, iclass 15, count 0 2006.217.07:34:41.91#ibcon#enter sib2, iclass 15, count 0 2006.217.07:34:41.91#ibcon#flushed, iclass 15, count 0 2006.217.07:34:41.91#ibcon#about to write, iclass 15, count 0 2006.217.07:34:41.91#ibcon#wrote, iclass 15, count 0 2006.217.07:34:41.91#ibcon#about to read 3, iclass 15, count 0 2006.217.07:34:41.93#ibcon#read 3, iclass 15, count 0 2006.217.07:34:41.93#ibcon#about to read 4, iclass 15, count 0 2006.217.07:34:41.93#ibcon#read 4, iclass 15, count 0 2006.217.07:34:41.93#ibcon#about to read 5, iclass 15, count 0 2006.217.07:34:41.93#ibcon#read 5, iclass 15, count 0 2006.217.07:34:41.93#ibcon#about to read 6, iclass 15, count 0 2006.217.07:34:41.93#ibcon#read 6, iclass 15, count 0 2006.217.07:34:41.93#ibcon#end of sib2, iclass 15, count 0 2006.217.07:34:41.93#ibcon#*mode == 0, iclass 15, count 0 2006.217.07:34:41.93#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.217.07:34:41.93#ibcon#[28=FRQ=05,744.99\r\n] 2006.217.07:34:41.93#ibcon#*before write, iclass 15, count 0 2006.217.07:34:41.93#ibcon#enter sib2, iclass 15, count 0 2006.217.07:34:41.93#ibcon#flushed, iclass 15, count 0 2006.217.07:34:41.93#ibcon#about to write, iclass 15, count 0 2006.217.07:34:41.93#ibcon#wrote, iclass 15, count 0 2006.217.07:34:41.93#ibcon#about to read 3, iclass 15, count 0 2006.217.07:34:41.97#ibcon#read 3, iclass 15, count 0 2006.217.07:34:41.97#ibcon#about to read 4, iclass 15, count 0 2006.217.07:34:41.97#ibcon#read 4, iclass 15, count 0 2006.217.07:34:41.97#ibcon#about to read 5, iclass 15, count 0 2006.217.07:34:41.97#ibcon#read 5, iclass 15, count 0 2006.217.07:34:41.97#ibcon#about to read 6, iclass 15, count 0 2006.217.07:34:41.97#ibcon#read 6, iclass 15, count 0 2006.217.07:34:41.97#ibcon#end of sib2, iclass 15, count 0 2006.217.07:34:41.97#ibcon#*after write, iclass 15, count 0 2006.217.07:34:41.97#ibcon#*before return 0, iclass 15, count 0 2006.217.07:34:41.97#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.217.07:34:41.97#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.217.07:34:41.97#ibcon#about to clear, iclass 15 cls_cnt 0 2006.217.07:34:41.97#ibcon#cleared, iclass 15 cls_cnt 0 2006.217.07:34:41.97$vc4f8/vb=5,4 2006.217.07:34:41.97#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.217.07:34:41.97#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.217.07:34:41.97#ibcon#ireg 11 cls_cnt 2 2006.217.07:34:41.97#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.217.07:34:42.03#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.217.07:34:42.03#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.217.07:34:42.03#ibcon#enter wrdev, iclass 17, count 2 2006.217.07:34:42.03#ibcon#first serial, iclass 17, count 2 2006.217.07:34:42.03#ibcon#enter sib2, iclass 17, count 2 2006.217.07:34:42.03#ibcon#flushed, iclass 17, count 2 2006.217.07:34:42.03#ibcon#about to write, iclass 17, count 2 2006.217.07:34:42.03#ibcon#wrote, iclass 17, count 2 2006.217.07:34:42.03#ibcon#about to read 3, iclass 17, count 2 2006.217.07:34:42.05#ibcon#read 3, iclass 17, count 2 2006.217.07:34:42.05#ibcon#about to read 4, iclass 17, count 2 2006.217.07:34:42.05#ibcon#read 4, iclass 17, count 2 2006.217.07:34:42.05#ibcon#about to read 5, iclass 17, count 2 2006.217.07:34:42.05#ibcon#read 5, iclass 17, count 2 2006.217.07:34:42.05#ibcon#about to read 6, iclass 17, count 2 2006.217.07:34:42.05#ibcon#read 6, iclass 17, count 2 2006.217.07:34:42.05#ibcon#end of sib2, iclass 17, count 2 2006.217.07:34:42.05#ibcon#*mode == 0, iclass 17, count 2 2006.217.07:34:42.05#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.217.07:34:42.05#ibcon#[27=AT05-04\r\n] 2006.217.07:34:42.05#ibcon#*before write, iclass 17, count 2 2006.217.07:34:42.05#ibcon#enter sib2, iclass 17, count 2 2006.217.07:34:42.05#ibcon#flushed, iclass 17, count 2 2006.217.07:34:42.05#ibcon#about to write, iclass 17, count 2 2006.217.07:34:42.05#ibcon#wrote, iclass 17, count 2 2006.217.07:34:42.05#ibcon#about to read 3, iclass 17, count 2 2006.217.07:34:42.08#ibcon#read 3, iclass 17, count 2 2006.217.07:34:42.08#ibcon#about to read 4, iclass 17, count 2 2006.217.07:34:42.08#ibcon#read 4, iclass 17, count 2 2006.217.07:34:42.08#ibcon#about to read 5, iclass 17, count 2 2006.217.07:34:42.08#ibcon#read 5, iclass 17, count 2 2006.217.07:34:42.08#ibcon#about to read 6, iclass 17, count 2 2006.217.07:34:42.08#ibcon#read 6, iclass 17, count 2 2006.217.07:34:42.08#ibcon#end of sib2, iclass 17, count 2 2006.217.07:34:42.08#ibcon#*after write, iclass 17, count 2 2006.217.07:34:42.08#ibcon#*before return 0, iclass 17, count 2 2006.217.07:34:42.08#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.217.07:34:42.08#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.217.07:34:42.08#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.217.07:34:42.08#ibcon#ireg 7 cls_cnt 0 2006.217.07:34:42.08#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.217.07:34:42.20#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.217.07:34:42.20#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.217.07:34:42.20#ibcon#enter wrdev, iclass 17, count 0 2006.217.07:34:42.20#ibcon#first serial, iclass 17, count 0 2006.217.07:34:42.20#ibcon#enter sib2, iclass 17, count 0 2006.217.07:34:42.20#ibcon#flushed, iclass 17, count 0 2006.217.07:34:42.20#ibcon#about to write, iclass 17, count 0 2006.217.07:34:42.20#ibcon#wrote, iclass 17, count 0 2006.217.07:34:42.20#ibcon#about to read 3, iclass 17, count 0 2006.217.07:34:42.22#ibcon#read 3, iclass 17, count 0 2006.217.07:34:42.22#ibcon#about to read 4, iclass 17, count 0 2006.217.07:34:42.22#ibcon#read 4, iclass 17, count 0 2006.217.07:34:42.22#ibcon#about to read 5, iclass 17, count 0 2006.217.07:34:42.22#ibcon#read 5, iclass 17, count 0 2006.217.07:34:42.22#ibcon#about to read 6, iclass 17, count 0 2006.217.07:34:42.22#ibcon#read 6, iclass 17, count 0 2006.217.07:34:42.22#ibcon#end of sib2, iclass 17, count 0 2006.217.07:34:42.22#ibcon#*mode == 0, iclass 17, count 0 2006.217.07:34:42.22#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.217.07:34:42.22#ibcon#[27=USB\r\n] 2006.217.07:34:42.22#ibcon#*before write, iclass 17, count 0 2006.217.07:34:42.22#ibcon#enter sib2, iclass 17, count 0 2006.217.07:34:42.22#ibcon#flushed, iclass 17, count 0 2006.217.07:34:42.22#ibcon#about to write, iclass 17, count 0 2006.217.07:34:42.22#ibcon#wrote, iclass 17, count 0 2006.217.07:34:42.22#ibcon#about to read 3, iclass 17, count 0 2006.217.07:34:42.25#ibcon#read 3, iclass 17, count 0 2006.217.07:34:42.25#ibcon#about to read 4, iclass 17, count 0 2006.217.07:34:42.25#ibcon#read 4, iclass 17, count 0 2006.217.07:34:42.25#ibcon#about to read 5, iclass 17, count 0 2006.217.07:34:42.25#ibcon#read 5, iclass 17, count 0 2006.217.07:34:42.25#ibcon#about to read 6, iclass 17, count 0 2006.217.07:34:42.25#ibcon#read 6, iclass 17, count 0 2006.217.07:34:42.25#ibcon#end of sib2, iclass 17, count 0 2006.217.07:34:42.25#ibcon#*after write, iclass 17, count 0 2006.217.07:34:42.25#ibcon#*before return 0, iclass 17, count 0 2006.217.07:34:42.25#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.217.07:34:42.25#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.217.07:34:42.25#ibcon#about to clear, iclass 17 cls_cnt 0 2006.217.07:34:42.25#ibcon#cleared, iclass 17 cls_cnt 0 2006.217.07:34:42.25$vc4f8/vblo=6,752.99 2006.217.07:34:42.25#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.217.07:34:42.25#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.217.07:34:42.25#ibcon#ireg 17 cls_cnt 0 2006.217.07:34:42.25#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.217.07:34:42.25#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.217.07:34:42.25#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.217.07:34:42.25#ibcon#enter wrdev, iclass 19, count 0 2006.217.07:34:42.25#ibcon#first serial, iclass 19, count 0 2006.217.07:34:42.25#ibcon#enter sib2, iclass 19, count 0 2006.217.07:34:42.25#ibcon#flushed, iclass 19, count 0 2006.217.07:34:42.25#ibcon#about to write, iclass 19, count 0 2006.217.07:34:42.25#ibcon#wrote, iclass 19, count 0 2006.217.07:34:42.25#ibcon#about to read 3, iclass 19, count 0 2006.217.07:34:42.27#ibcon#read 3, iclass 19, count 0 2006.217.07:34:42.27#ibcon#about to read 4, iclass 19, count 0 2006.217.07:34:42.27#ibcon#read 4, iclass 19, count 0 2006.217.07:34:42.27#ibcon#about to read 5, iclass 19, count 0 2006.217.07:34:42.27#ibcon#read 5, iclass 19, count 0 2006.217.07:34:42.27#ibcon#about to read 6, iclass 19, count 0 2006.217.07:34:42.27#ibcon#read 6, iclass 19, count 0 2006.217.07:34:42.27#ibcon#end of sib2, iclass 19, count 0 2006.217.07:34:42.27#ibcon#*mode == 0, iclass 19, count 0 2006.217.07:34:42.27#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.217.07:34:42.27#ibcon#[28=FRQ=06,752.99\r\n] 2006.217.07:34:42.27#ibcon#*before write, iclass 19, count 0 2006.217.07:34:42.27#ibcon#enter sib2, iclass 19, count 0 2006.217.07:34:42.27#ibcon#flushed, iclass 19, count 0 2006.217.07:34:42.27#ibcon#about to write, iclass 19, count 0 2006.217.07:34:42.27#ibcon#wrote, iclass 19, count 0 2006.217.07:34:42.27#ibcon#about to read 3, iclass 19, count 0 2006.217.07:34:42.31#ibcon#read 3, iclass 19, count 0 2006.217.07:34:42.31#ibcon#about to read 4, iclass 19, count 0 2006.217.07:34:42.31#ibcon#read 4, iclass 19, count 0 2006.217.07:34:42.31#ibcon#about to read 5, iclass 19, count 0 2006.217.07:34:42.31#ibcon#read 5, iclass 19, count 0 2006.217.07:34:42.31#ibcon#about to read 6, iclass 19, count 0 2006.217.07:34:42.31#ibcon#read 6, iclass 19, count 0 2006.217.07:34:42.31#ibcon#end of sib2, iclass 19, count 0 2006.217.07:34:42.31#ibcon#*after write, iclass 19, count 0 2006.217.07:34:42.31#ibcon#*before return 0, iclass 19, count 0 2006.217.07:34:42.31#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.217.07:34:42.31#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.217.07:34:42.31#ibcon#about to clear, iclass 19 cls_cnt 0 2006.217.07:34:42.31#ibcon#cleared, iclass 19 cls_cnt 0 2006.217.07:34:42.31$vc4f8/vb=6,4 2006.217.07:34:42.31#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.217.07:34:42.31#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.217.07:34:42.31#ibcon#ireg 11 cls_cnt 2 2006.217.07:34:42.31#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.217.07:34:42.37#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.217.07:34:42.37#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.217.07:34:42.37#ibcon#enter wrdev, iclass 21, count 2 2006.217.07:34:42.37#ibcon#first serial, iclass 21, count 2 2006.217.07:34:42.37#ibcon#enter sib2, iclass 21, count 2 2006.217.07:34:42.37#ibcon#flushed, iclass 21, count 2 2006.217.07:34:42.37#ibcon#about to write, iclass 21, count 2 2006.217.07:34:42.37#ibcon#wrote, iclass 21, count 2 2006.217.07:34:42.37#ibcon#about to read 3, iclass 21, count 2 2006.217.07:34:42.39#ibcon#read 3, iclass 21, count 2 2006.217.07:34:42.39#ibcon#about to read 4, iclass 21, count 2 2006.217.07:34:42.39#ibcon#read 4, iclass 21, count 2 2006.217.07:34:42.39#ibcon#about to read 5, iclass 21, count 2 2006.217.07:34:42.39#ibcon#read 5, iclass 21, count 2 2006.217.07:34:42.39#ibcon#about to read 6, iclass 21, count 2 2006.217.07:34:42.39#ibcon#read 6, iclass 21, count 2 2006.217.07:34:42.39#ibcon#end of sib2, iclass 21, count 2 2006.217.07:34:42.39#ibcon#*mode == 0, iclass 21, count 2 2006.217.07:34:42.39#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.217.07:34:42.39#ibcon#[27=AT06-04\r\n] 2006.217.07:34:42.39#ibcon#*before write, iclass 21, count 2 2006.217.07:34:42.39#ibcon#enter sib2, iclass 21, count 2 2006.217.07:34:42.39#ibcon#flushed, iclass 21, count 2 2006.217.07:34:42.39#ibcon#about to write, iclass 21, count 2 2006.217.07:34:42.39#ibcon#wrote, iclass 21, count 2 2006.217.07:34:42.39#ibcon#about to read 3, iclass 21, count 2 2006.217.07:34:42.42#ibcon#read 3, iclass 21, count 2 2006.217.07:34:42.42#ibcon#about to read 4, iclass 21, count 2 2006.217.07:34:42.42#ibcon#read 4, iclass 21, count 2 2006.217.07:34:42.42#ibcon#about to read 5, iclass 21, count 2 2006.217.07:34:42.42#ibcon#read 5, iclass 21, count 2 2006.217.07:34:42.42#ibcon#about to read 6, iclass 21, count 2 2006.217.07:34:42.42#ibcon#read 6, iclass 21, count 2 2006.217.07:34:42.42#ibcon#end of sib2, iclass 21, count 2 2006.217.07:34:42.42#ibcon#*after write, iclass 21, count 2 2006.217.07:34:42.42#ibcon#*before return 0, iclass 21, count 2 2006.217.07:34:42.42#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.217.07:34:42.42#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.217.07:34:42.42#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.217.07:34:42.42#ibcon#ireg 7 cls_cnt 0 2006.217.07:34:42.42#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.217.07:34:42.54#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.217.07:34:42.54#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.217.07:34:42.54#ibcon#enter wrdev, iclass 21, count 0 2006.217.07:34:42.54#ibcon#first serial, iclass 21, count 0 2006.217.07:34:42.54#ibcon#enter sib2, iclass 21, count 0 2006.217.07:34:42.54#ibcon#flushed, iclass 21, count 0 2006.217.07:34:42.54#ibcon#about to write, iclass 21, count 0 2006.217.07:34:42.54#ibcon#wrote, iclass 21, count 0 2006.217.07:34:42.54#ibcon#about to read 3, iclass 21, count 0 2006.217.07:34:42.56#ibcon#read 3, iclass 21, count 0 2006.217.07:34:42.56#ibcon#about to read 4, iclass 21, count 0 2006.217.07:34:42.56#ibcon#read 4, iclass 21, count 0 2006.217.07:34:42.56#ibcon#about to read 5, iclass 21, count 0 2006.217.07:34:42.56#ibcon#read 5, iclass 21, count 0 2006.217.07:34:42.56#ibcon#about to read 6, iclass 21, count 0 2006.217.07:34:42.56#ibcon#read 6, iclass 21, count 0 2006.217.07:34:42.56#ibcon#end of sib2, iclass 21, count 0 2006.217.07:34:42.56#ibcon#*mode == 0, iclass 21, count 0 2006.217.07:34:42.56#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.217.07:34:42.56#ibcon#[27=USB\r\n] 2006.217.07:34:42.56#ibcon#*before write, iclass 21, count 0 2006.217.07:34:42.56#ibcon#enter sib2, iclass 21, count 0 2006.217.07:34:42.56#ibcon#flushed, iclass 21, count 0 2006.217.07:34:42.56#ibcon#about to write, iclass 21, count 0 2006.217.07:34:42.56#ibcon#wrote, iclass 21, count 0 2006.217.07:34:42.56#ibcon#about to read 3, iclass 21, count 0 2006.217.07:34:42.59#ibcon#read 3, iclass 21, count 0 2006.217.07:34:42.59#ibcon#about to read 4, iclass 21, count 0 2006.217.07:34:42.59#ibcon#read 4, iclass 21, count 0 2006.217.07:34:42.59#ibcon#about to read 5, iclass 21, count 0 2006.217.07:34:42.59#ibcon#read 5, iclass 21, count 0 2006.217.07:34:42.59#ibcon#about to read 6, iclass 21, count 0 2006.217.07:34:42.59#ibcon#read 6, iclass 21, count 0 2006.217.07:34:42.59#ibcon#end of sib2, iclass 21, count 0 2006.217.07:34:42.59#ibcon#*after write, iclass 21, count 0 2006.217.07:34:42.59#ibcon#*before return 0, iclass 21, count 0 2006.217.07:34:42.59#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.217.07:34:42.59#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.217.07:34:42.59#ibcon#about to clear, iclass 21 cls_cnt 0 2006.217.07:34:42.59#ibcon#cleared, iclass 21 cls_cnt 0 2006.217.07:34:42.59$vc4f8/vabw=wide 2006.217.07:34:42.59#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.217.07:34:42.59#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.217.07:34:42.59#ibcon#ireg 8 cls_cnt 0 2006.217.07:34:42.59#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.217.07:34:42.59#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.217.07:34:42.59#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.217.07:34:42.59#ibcon#enter wrdev, iclass 23, count 0 2006.217.07:34:42.59#ibcon#first serial, iclass 23, count 0 2006.217.07:34:42.59#ibcon#enter sib2, iclass 23, count 0 2006.217.07:34:42.59#ibcon#flushed, iclass 23, count 0 2006.217.07:34:42.59#ibcon#about to write, iclass 23, count 0 2006.217.07:34:42.59#ibcon#wrote, iclass 23, count 0 2006.217.07:34:42.59#ibcon#about to read 3, iclass 23, count 0 2006.217.07:34:42.61#ibcon#read 3, iclass 23, count 0 2006.217.07:34:42.61#ibcon#about to read 4, iclass 23, count 0 2006.217.07:34:42.61#ibcon#read 4, iclass 23, count 0 2006.217.07:34:42.61#ibcon#about to read 5, iclass 23, count 0 2006.217.07:34:42.61#ibcon#read 5, iclass 23, count 0 2006.217.07:34:42.61#ibcon#about to read 6, iclass 23, count 0 2006.217.07:34:42.61#ibcon#read 6, iclass 23, count 0 2006.217.07:34:42.61#ibcon#end of sib2, iclass 23, count 0 2006.217.07:34:42.61#ibcon#*mode == 0, iclass 23, count 0 2006.217.07:34:42.61#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.217.07:34:42.61#ibcon#[25=BW32\r\n] 2006.217.07:34:42.61#ibcon#*before write, iclass 23, count 0 2006.217.07:34:42.61#ibcon#enter sib2, iclass 23, count 0 2006.217.07:34:42.61#ibcon#flushed, iclass 23, count 0 2006.217.07:34:42.61#ibcon#about to write, iclass 23, count 0 2006.217.07:34:42.61#ibcon#wrote, iclass 23, count 0 2006.217.07:34:42.61#ibcon#about to read 3, iclass 23, count 0 2006.217.07:34:42.64#ibcon#read 3, iclass 23, count 0 2006.217.07:34:42.64#ibcon#about to read 4, iclass 23, count 0 2006.217.07:34:42.64#ibcon#read 4, iclass 23, count 0 2006.217.07:34:42.64#ibcon#about to read 5, iclass 23, count 0 2006.217.07:34:42.64#ibcon#read 5, iclass 23, count 0 2006.217.07:34:42.64#ibcon#about to read 6, iclass 23, count 0 2006.217.07:34:42.64#ibcon#read 6, iclass 23, count 0 2006.217.07:34:42.64#ibcon#end of sib2, iclass 23, count 0 2006.217.07:34:42.64#ibcon#*after write, iclass 23, count 0 2006.217.07:34:42.64#ibcon#*before return 0, iclass 23, count 0 2006.217.07:34:42.64#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.217.07:34:42.64#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.217.07:34:42.64#ibcon#about to clear, iclass 23 cls_cnt 0 2006.217.07:34:42.64#ibcon#cleared, iclass 23 cls_cnt 0 2006.217.07:34:42.64$vc4f8/vbbw=wide 2006.217.07:34:42.64#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.217.07:34:42.64#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.217.07:34:42.64#ibcon#ireg 8 cls_cnt 0 2006.217.07:34:42.64#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.217.07:34:42.71#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.217.07:34:42.71#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.217.07:34:42.71#ibcon#enter wrdev, iclass 25, count 0 2006.217.07:34:42.71#ibcon#first serial, iclass 25, count 0 2006.217.07:34:42.71#ibcon#enter sib2, iclass 25, count 0 2006.217.07:34:42.71#ibcon#flushed, iclass 25, count 0 2006.217.07:34:42.71#ibcon#about to write, iclass 25, count 0 2006.217.07:34:42.71#ibcon#wrote, iclass 25, count 0 2006.217.07:34:42.71#ibcon#about to read 3, iclass 25, count 0 2006.217.07:34:42.73#ibcon#read 3, iclass 25, count 0 2006.217.07:34:42.73#ibcon#about to read 4, iclass 25, count 0 2006.217.07:34:42.73#ibcon#read 4, iclass 25, count 0 2006.217.07:34:42.73#ibcon#about to read 5, iclass 25, count 0 2006.217.07:34:42.73#ibcon#read 5, iclass 25, count 0 2006.217.07:34:42.73#ibcon#about to read 6, iclass 25, count 0 2006.217.07:34:42.73#ibcon#read 6, iclass 25, count 0 2006.217.07:34:42.73#ibcon#end of sib2, iclass 25, count 0 2006.217.07:34:42.73#ibcon#*mode == 0, iclass 25, count 0 2006.217.07:34:42.73#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.217.07:34:42.73#ibcon#[27=BW32\r\n] 2006.217.07:34:42.73#ibcon#*before write, iclass 25, count 0 2006.217.07:34:42.73#ibcon#enter sib2, iclass 25, count 0 2006.217.07:34:42.73#ibcon#flushed, iclass 25, count 0 2006.217.07:34:42.73#ibcon#about to write, iclass 25, count 0 2006.217.07:34:42.73#ibcon#wrote, iclass 25, count 0 2006.217.07:34:42.73#ibcon#about to read 3, iclass 25, count 0 2006.217.07:34:42.76#ibcon#read 3, iclass 25, count 0 2006.217.07:34:42.76#ibcon#about to read 4, iclass 25, count 0 2006.217.07:34:42.76#ibcon#read 4, iclass 25, count 0 2006.217.07:34:42.76#ibcon#about to read 5, iclass 25, count 0 2006.217.07:34:42.76#ibcon#read 5, iclass 25, count 0 2006.217.07:34:42.76#ibcon#about to read 6, iclass 25, count 0 2006.217.07:34:42.76#ibcon#read 6, iclass 25, count 0 2006.217.07:34:42.76#ibcon#end of sib2, iclass 25, count 0 2006.217.07:34:42.76#ibcon#*after write, iclass 25, count 0 2006.217.07:34:42.76#ibcon#*before return 0, iclass 25, count 0 2006.217.07:34:42.76#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.217.07:34:42.76#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.217.07:34:42.76#ibcon#about to clear, iclass 25 cls_cnt 0 2006.217.07:34:42.76#ibcon#cleared, iclass 25 cls_cnt 0 2006.217.07:34:42.76$4f8m12a/ifd4f 2006.217.07:34:42.76$ifd4f/lo= 2006.217.07:34:42.76$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.217.07:34:42.76$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.217.07:34:42.76$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.217.07:34:42.76$ifd4f/patch= 2006.217.07:34:42.76$ifd4f/patch=lo1,a1,a2,a3,a4 2006.217.07:34:42.76$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.217.07:34:42.76$ifd4f/patch=lo3,a5,a6,a7,a8 2006.217.07:34:42.76$4f8m12a/"form=m,16.000,1:2 2006.217.07:34:42.76$4f8m12a/"tpicd 2006.217.07:34:42.76$4f8m12a/echo=off 2006.217.07:34:42.76$4f8m12a/xlog=off 2006.217.07:34:42.76:!2006.217.07:35:10 2006.217.07:34:55.14#trakl#Source acquired 2006.217.07:34:55.14#flagr#flagr/antenna,acquired 2006.217.07:35:10.00:preob 2006.217.07:35:11.14/onsource/TRACKING 2006.217.07:35:11.14:!2006.217.07:35:20 2006.217.07:35:20.00:data_valid=on 2006.217.07:35:20.00:midob 2006.217.07:35:20.14/onsource/TRACKING 2006.217.07:35:20.14/wx/31.31,1008.5,57 2006.217.07:35:20.35/cable/+6.3855E-03 2006.217.07:35:21.44/va/01,05,usb,yes,32,33 2006.217.07:35:21.44/va/02,04,usb,yes,29,31 2006.217.07:35:21.44/va/03,04,usb,yes,28,28 2006.217.07:35:21.44/va/04,04,usb,yes,31,33 2006.217.07:35:21.44/va/05,07,usb,yes,33,35 2006.217.07:35:21.44/va/06,06,usb,yes,32,32 2006.217.07:35:21.44/va/07,06,usb,yes,33,32 2006.217.07:35:21.44/va/08,07,usb,yes,31,30 2006.217.07:35:21.67/valo/01,532.99,yes,locked 2006.217.07:35:21.67/valo/02,572.99,yes,locked 2006.217.07:35:21.67/valo/03,672.99,yes,locked 2006.217.07:35:21.67/valo/04,832.99,yes,locked 2006.217.07:35:21.67/valo/05,652.99,yes,locked 2006.217.07:35:21.67/valo/06,772.99,yes,locked 2006.217.07:35:21.67/valo/07,832.99,yes,locked 2006.217.07:35:21.67/valo/08,852.99,yes,locked 2006.217.07:35:22.76/vb/01,04,usb,yes,30,29 2006.217.07:35:22.76/vb/02,04,usb,yes,32,33 2006.217.07:35:22.76/vb/03,04,usb,yes,28,32 2006.217.07:35:22.76/vb/04,04,usb,yes,30,29 2006.217.07:35:22.76/vb/05,04,usb,yes,28,32 2006.217.07:35:22.76/vb/06,04,usb,yes,28,31 2006.217.07:35:22.76/vb/07,04,usb,yes,31,31 2006.217.07:35:22.76/vb/08,04,usb,yes,28,32 2006.217.07:35:23.00/vblo/01,632.99,yes,locked 2006.217.07:35:23.00/vblo/02,640.99,yes,locked 2006.217.07:35:23.00/vblo/03,656.99,yes,locked 2006.217.07:35:23.00/vblo/04,712.99,yes,locked 2006.217.07:35:23.00/vblo/05,744.99,yes,locked 2006.217.07:35:23.00/vblo/06,752.99,yes,locked 2006.217.07:35:23.00/vblo/07,734.99,yes,locked 2006.217.07:35:23.00/vblo/08,744.99,yes,locked 2006.217.07:35:23.15/vabw/8 2006.217.07:35:23.30/vbbw/8 2006.217.07:35:23.39/xfe/off,on,15.2 2006.217.07:35:23.76/ifatt/23,28,28,28 2006.217.07:35:24.07/fmout-gps/S +4.37E-07 2006.217.07:35:24.11:!2006.217.07:36:20 2006.217.07:36:20.00:data_valid=off 2006.217.07:36:20.00:postob 2006.217.07:36:20.19/cable/+6.3858E-03 2006.217.07:36:20.19/wx/31.30,1008.6,62 2006.217.07:36:21.07/fmout-gps/S +4.37E-07 2006.217.07:36:21.07:scan_name=217-0737,k06217,60 2006.217.07:36:21.07:source=0602+673,060752.67,672055.4,2000.0,ccw 2006.217.07:36:21.14#flagr#flagr/antenna,new-source 2006.217.07:36:22.14:checkk5 2006.217.07:36:22.51/chk_autoobs//k5ts1/ autoobs is running! 2006.217.07:36:22.88/chk_autoobs//k5ts2/ autoobs is running! 2006.217.07:36:23.26/chk_autoobs//k5ts3/ autoobs is running! 2006.217.07:36:23.63/chk_autoobs//k5ts4/ autoobs is running! 2006.217.07:36:24.00/chk_obsdata//k5ts1/T2170735??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:36:24.37/chk_obsdata//k5ts2/T2170735??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:36:24.73/chk_obsdata//k5ts3/T2170735??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:36:25.10/chk_obsdata//k5ts4/T2170735??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:36:25.79/k5log//k5ts1_log_newline 2006.217.07:36:26.49/k5log//k5ts2_log_newline 2006.217.07:36:27.17/k5log//k5ts3_log_newline 2006.217.07:36:27.88/k5log//k5ts4_log_newline 2006.217.07:36:27.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.217.07:36:27.90:4f8m12a=1 2006.217.07:36:27.90$4f8m12a/echo=on 2006.217.07:36:27.90$4f8m12a/pcalon 2006.217.07:36:27.90$pcalon/"no phase cal control is implemented here 2006.217.07:36:27.90$4f8m12a/"tpicd=stop 2006.217.07:36:27.90$4f8m12a/vc4f8 2006.217.07:36:27.90$vc4f8/valo=1,532.99 2006.217.07:36:27.91#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.217.07:36:27.91#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.217.07:36:27.91#ibcon#ireg 17 cls_cnt 0 2006.217.07:36:27.91#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.217.07:36:27.91#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.217.07:36:27.91#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.217.07:36:27.91#ibcon#enter wrdev, iclass 36, count 0 2006.217.07:36:27.91#ibcon#first serial, iclass 36, count 0 2006.217.07:36:27.91#ibcon#enter sib2, iclass 36, count 0 2006.217.07:36:27.91#ibcon#flushed, iclass 36, count 0 2006.217.07:36:27.91#ibcon#about to write, iclass 36, count 0 2006.217.07:36:27.91#ibcon#wrote, iclass 36, count 0 2006.217.07:36:27.91#ibcon#about to read 3, iclass 36, count 0 2006.217.07:36:27.95#ibcon#read 3, iclass 36, count 0 2006.217.07:36:27.95#ibcon#about to read 4, iclass 36, count 0 2006.217.07:36:27.95#ibcon#read 4, iclass 36, count 0 2006.217.07:36:27.95#ibcon#about to read 5, iclass 36, count 0 2006.217.07:36:27.95#ibcon#read 5, iclass 36, count 0 2006.217.07:36:27.95#ibcon#about to read 6, iclass 36, count 0 2006.217.07:36:27.95#ibcon#read 6, iclass 36, count 0 2006.217.07:36:27.95#ibcon#end of sib2, iclass 36, count 0 2006.217.07:36:27.95#ibcon#*mode == 0, iclass 36, count 0 2006.217.07:36:27.95#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.217.07:36:27.95#ibcon#[26=FRQ=01,532.99\r\n] 2006.217.07:36:27.95#ibcon#*before write, iclass 36, count 0 2006.217.07:36:27.95#ibcon#enter sib2, iclass 36, count 0 2006.217.07:36:27.95#ibcon#flushed, iclass 36, count 0 2006.217.07:36:27.95#ibcon#about to write, iclass 36, count 0 2006.217.07:36:27.95#ibcon#wrote, iclass 36, count 0 2006.217.07:36:27.95#ibcon#about to read 3, iclass 36, count 0 2006.217.07:36:28.00#ibcon#read 3, iclass 36, count 0 2006.217.07:36:28.00#ibcon#about to read 4, iclass 36, count 0 2006.217.07:36:28.00#ibcon#read 4, iclass 36, count 0 2006.217.07:36:28.00#ibcon#about to read 5, iclass 36, count 0 2006.217.07:36:28.00#ibcon#read 5, iclass 36, count 0 2006.217.07:36:28.00#ibcon#about to read 6, iclass 36, count 0 2006.217.07:36:28.00#ibcon#read 6, iclass 36, count 0 2006.217.07:36:28.00#ibcon#end of sib2, iclass 36, count 0 2006.217.07:36:28.00#ibcon#*after write, iclass 36, count 0 2006.217.07:36:28.00#ibcon#*before return 0, iclass 36, count 0 2006.217.07:36:28.00#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.217.07:36:28.00#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.217.07:36:28.00#ibcon#about to clear, iclass 36 cls_cnt 0 2006.217.07:36:28.00#ibcon#cleared, iclass 36 cls_cnt 0 2006.217.07:36:28.00$vc4f8/va=1,5 2006.217.07:36:28.00#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.217.07:36:28.00#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.217.07:36:28.00#ibcon#ireg 11 cls_cnt 2 2006.217.07:36:28.00#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.217.07:36:28.00#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.217.07:36:28.00#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.217.07:36:28.00#ibcon#enter wrdev, iclass 38, count 2 2006.217.07:36:28.00#ibcon#first serial, iclass 38, count 2 2006.217.07:36:28.00#ibcon#enter sib2, iclass 38, count 2 2006.217.07:36:28.00#ibcon#flushed, iclass 38, count 2 2006.217.07:36:28.00#ibcon#about to write, iclass 38, count 2 2006.217.07:36:28.00#ibcon#wrote, iclass 38, count 2 2006.217.07:36:28.00#ibcon#about to read 3, iclass 38, count 2 2006.217.07:36:28.02#ibcon#read 3, iclass 38, count 2 2006.217.07:36:28.02#ibcon#about to read 4, iclass 38, count 2 2006.217.07:36:28.02#ibcon#read 4, iclass 38, count 2 2006.217.07:36:28.02#ibcon#about to read 5, iclass 38, count 2 2006.217.07:36:28.02#ibcon#read 5, iclass 38, count 2 2006.217.07:36:28.02#ibcon#about to read 6, iclass 38, count 2 2006.217.07:36:28.02#ibcon#read 6, iclass 38, count 2 2006.217.07:36:28.02#ibcon#end of sib2, iclass 38, count 2 2006.217.07:36:28.02#ibcon#*mode == 0, iclass 38, count 2 2006.217.07:36:28.02#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.217.07:36:28.02#ibcon#[25=AT01-05\r\n] 2006.217.07:36:28.02#ibcon#*before write, iclass 38, count 2 2006.217.07:36:28.02#ibcon#enter sib2, iclass 38, count 2 2006.217.07:36:28.02#ibcon#flushed, iclass 38, count 2 2006.217.07:36:28.02#ibcon#about to write, iclass 38, count 2 2006.217.07:36:28.02#ibcon#wrote, iclass 38, count 2 2006.217.07:36:28.02#ibcon#about to read 3, iclass 38, count 2 2006.217.07:36:28.05#ibcon#read 3, iclass 38, count 2 2006.217.07:36:28.05#ibcon#about to read 4, iclass 38, count 2 2006.217.07:36:28.05#ibcon#read 4, iclass 38, count 2 2006.217.07:36:28.05#ibcon#about to read 5, iclass 38, count 2 2006.217.07:36:28.05#ibcon#read 5, iclass 38, count 2 2006.217.07:36:28.05#ibcon#about to read 6, iclass 38, count 2 2006.217.07:36:28.05#ibcon#read 6, iclass 38, count 2 2006.217.07:36:28.05#ibcon#end of sib2, iclass 38, count 2 2006.217.07:36:28.05#ibcon#*after write, iclass 38, count 2 2006.217.07:36:28.05#ibcon#*before return 0, iclass 38, count 2 2006.217.07:36:28.05#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.217.07:36:28.05#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.217.07:36:28.05#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.217.07:36:28.05#ibcon#ireg 7 cls_cnt 0 2006.217.07:36:28.05#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.217.07:36:28.17#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.217.07:36:28.17#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.217.07:36:28.17#ibcon#enter wrdev, iclass 38, count 0 2006.217.07:36:28.17#ibcon#first serial, iclass 38, count 0 2006.217.07:36:28.17#ibcon#enter sib2, iclass 38, count 0 2006.217.07:36:28.17#ibcon#flushed, iclass 38, count 0 2006.217.07:36:28.17#ibcon#about to write, iclass 38, count 0 2006.217.07:36:28.17#ibcon#wrote, iclass 38, count 0 2006.217.07:36:28.17#ibcon#about to read 3, iclass 38, count 0 2006.217.07:36:28.19#ibcon#read 3, iclass 38, count 0 2006.217.07:36:28.19#ibcon#about to read 4, iclass 38, count 0 2006.217.07:36:28.19#ibcon#read 4, iclass 38, count 0 2006.217.07:36:28.19#ibcon#about to read 5, iclass 38, count 0 2006.217.07:36:28.19#ibcon#read 5, iclass 38, count 0 2006.217.07:36:28.19#ibcon#about to read 6, iclass 38, count 0 2006.217.07:36:28.19#ibcon#read 6, iclass 38, count 0 2006.217.07:36:28.19#ibcon#end of sib2, iclass 38, count 0 2006.217.07:36:28.19#ibcon#*mode == 0, iclass 38, count 0 2006.217.07:36:28.19#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.217.07:36:28.19#ibcon#[25=USB\r\n] 2006.217.07:36:28.19#ibcon#*before write, iclass 38, count 0 2006.217.07:36:28.19#ibcon#enter sib2, iclass 38, count 0 2006.217.07:36:28.19#ibcon#flushed, iclass 38, count 0 2006.217.07:36:28.19#ibcon#about to write, iclass 38, count 0 2006.217.07:36:28.19#ibcon#wrote, iclass 38, count 0 2006.217.07:36:28.19#ibcon#about to read 3, iclass 38, count 0 2006.217.07:36:28.22#ibcon#read 3, iclass 38, count 0 2006.217.07:36:28.22#ibcon#about to read 4, iclass 38, count 0 2006.217.07:36:28.22#ibcon#read 4, iclass 38, count 0 2006.217.07:36:28.22#ibcon#about to read 5, iclass 38, count 0 2006.217.07:36:28.22#ibcon#read 5, iclass 38, count 0 2006.217.07:36:28.22#ibcon#about to read 6, iclass 38, count 0 2006.217.07:36:28.22#ibcon#read 6, iclass 38, count 0 2006.217.07:36:28.22#ibcon#end of sib2, iclass 38, count 0 2006.217.07:36:28.22#ibcon#*after write, iclass 38, count 0 2006.217.07:36:28.22#ibcon#*before return 0, iclass 38, count 0 2006.217.07:36:28.22#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.217.07:36:28.22#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.217.07:36:28.22#ibcon#about to clear, iclass 38 cls_cnt 0 2006.217.07:36:28.22#ibcon#cleared, iclass 38 cls_cnt 0 2006.217.07:36:28.22$vc4f8/valo=2,572.99 2006.217.07:36:28.22#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.217.07:36:28.22#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.217.07:36:28.22#ibcon#ireg 17 cls_cnt 0 2006.217.07:36:28.22#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.217.07:36:28.22#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.217.07:36:28.22#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.217.07:36:28.22#ibcon#enter wrdev, iclass 40, count 0 2006.217.07:36:28.22#ibcon#first serial, iclass 40, count 0 2006.217.07:36:28.22#ibcon#enter sib2, iclass 40, count 0 2006.217.07:36:28.22#ibcon#flushed, iclass 40, count 0 2006.217.07:36:28.22#ibcon#about to write, iclass 40, count 0 2006.217.07:36:28.22#ibcon#wrote, iclass 40, count 0 2006.217.07:36:28.22#ibcon#about to read 3, iclass 40, count 0 2006.217.07:36:28.24#ibcon#read 3, iclass 40, count 0 2006.217.07:36:28.24#ibcon#about to read 4, iclass 40, count 0 2006.217.07:36:28.24#ibcon#read 4, iclass 40, count 0 2006.217.07:36:28.24#ibcon#about to read 5, iclass 40, count 0 2006.217.07:36:28.24#ibcon#read 5, iclass 40, count 0 2006.217.07:36:28.24#ibcon#about to read 6, iclass 40, count 0 2006.217.07:36:28.24#ibcon#read 6, iclass 40, count 0 2006.217.07:36:28.24#ibcon#end of sib2, iclass 40, count 0 2006.217.07:36:28.24#ibcon#*mode == 0, iclass 40, count 0 2006.217.07:36:28.24#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.217.07:36:28.24#ibcon#[26=FRQ=02,572.99\r\n] 2006.217.07:36:28.24#ibcon#*before write, iclass 40, count 0 2006.217.07:36:28.24#ibcon#enter sib2, iclass 40, count 0 2006.217.07:36:28.24#ibcon#flushed, iclass 40, count 0 2006.217.07:36:28.24#ibcon#about to write, iclass 40, count 0 2006.217.07:36:28.24#ibcon#wrote, iclass 40, count 0 2006.217.07:36:28.24#ibcon#about to read 3, iclass 40, count 0 2006.217.07:36:28.28#ibcon#read 3, iclass 40, count 0 2006.217.07:36:28.28#ibcon#about to read 4, iclass 40, count 0 2006.217.07:36:28.28#ibcon#read 4, iclass 40, count 0 2006.217.07:36:28.28#ibcon#about to read 5, iclass 40, count 0 2006.217.07:36:28.28#ibcon#read 5, iclass 40, count 0 2006.217.07:36:28.28#ibcon#about to read 6, iclass 40, count 0 2006.217.07:36:28.28#ibcon#read 6, iclass 40, count 0 2006.217.07:36:28.28#ibcon#end of sib2, iclass 40, count 0 2006.217.07:36:28.28#ibcon#*after write, iclass 40, count 0 2006.217.07:36:28.28#ibcon#*before return 0, iclass 40, count 0 2006.217.07:36:28.28#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.217.07:36:28.28#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.217.07:36:28.28#ibcon#about to clear, iclass 40 cls_cnt 0 2006.217.07:36:28.28#ibcon#cleared, iclass 40 cls_cnt 0 2006.217.07:36:28.28$vc4f8/va=2,4 2006.217.07:36:28.28#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.217.07:36:28.28#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.217.07:36:28.28#ibcon#ireg 11 cls_cnt 2 2006.217.07:36:28.28#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.217.07:36:28.34#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.217.07:36:28.34#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.217.07:36:28.34#ibcon#enter wrdev, iclass 4, count 2 2006.217.07:36:28.34#ibcon#first serial, iclass 4, count 2 2006.217.07:36:28.34#ibcon#enter sib2, iclass 4, count 2 2006.217.07:36:28.34#ibcon#flushed, iclass 4, count 2 2006.217.07:36:28.34#ibcon#about to write, iclass 4, count 2 2006.217.07:36:28.34#ibcon#wrote, iclass 4, count 2 2006.217.07:36:28.34#ibcon#about to read 3, iclass 4, count 2 2006.217.07:36:28.36#ibcon#read 3, iclass 4, count 2 2006.217.07:36:28.36#ibcon#about to read 4, iclass 4, count 2 2006.217.07:36:28.36#ibcon#read 4, iclass 4, count 2 2006.217.07:36:28.36#ibcon#about to read 5, iclass 4, count 2 2006.217.07:36:28.36#ibcon#read 5, iclass 4, count 2 2006.217.07:36:28.36#ibcon#about to read 6, iclass 4, count 2 2006.217.07:36:28.36#ibcon#read 6, iclass 4, count 2 2006.217.07:36:28.36#ibcon#end of sib2, iclass 4, count 2 2006.217.07:36:28.36#ibcon#*mode == 0, iclass 4, count 2 2006.217.07:36:28.36#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.217.07:36:28.36#ibcon#[25=AT02-04\r\n] 2006.217.07:36:28.36#ibcon#*before write, iclass 4, count 2 2006.217.07:36:28.36#ibcon#enter sib2, iclass 4, count 2 2006.217.07:36:28.36#ibcon#flushed, iclass 4, count 2 2006.217.07:36:28.36#ibcon#about to write, iclass 4, count 2 2006.217.07:36:28.36#ibcon#wrote, iclass 4, count 2 2006.217.07:36:28.36#ibcon#about to read 3, iclass 4, count 2 2006.217.07:36:28.39#ibcon#read 3, iclass 4, count 2 2006.217.07:36:28.39#ibcon#about to read 4, iclass 4, count 2 2006.217.07:36:28.39#ibcon#read 4, iclass 4, count 2 2006.217.07:36:28.39#ibcon#about to read 5, iclass 4, count 2 2006.217.07:36:28.39#ibcon#read 5, iclass 4, count 2 2006.217.07:36:28.39#ibcon#about to read 6, iclass 4, count 2 2006.217.07:36:28.39#ibcon#read 6, iclass 4, count 2 2006.217.07:36:28.39#ibcon#end of sib2, iclass 4, count 2 2006.217.07:36:28.39#ibcon#*after write, iclass 4, count 2 2006.217.07:36:28.39#ibcon#*before return 0, iclass 4, count 2 2006.217.07:36:28.39#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.217.07:36:28.39#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.217.07:36:28.39#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.217.07:36:28.39#ibcon#ireg 7 cls_cnt 0 2006.217.07:36:28.39#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.217.07:36:28.51#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.217.07:36:28.51#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.217.07:36:28.51#ibcon#enter wrdev, iclass 4, count 0 2006.217.07:36:28.51#ibcon#first serial, iclass 4, count 0 2006.217.07:36:28.51#ibcon#enter sib2, iclass 4, count 0 2006.217.07:36:28.51#ibcon#flushed, iclass 4, count 0 2006.217.07:36:28.51#ibcon#about to write, iclass 4, count 0 2006.217.07:36:28.51#ibcon#wrote, iclass 4, count 0 2006.217.07:36:28.51#ibcon#about to read 3, iclass 4, count 0 2006.217.07:36:28.53#ibcon#read 3, iclass 4, count 0 2006.217.07:36:28.53#ibcon#about to read 4, iclass 4, count 0 2006.217.07:36:28.53#ibcon#read 4, iclass 4, count 0 2006.217.07:36:28.53#ibcon#about to read 5, iclass 4, count 0 2006.217.07:36:28.53#ibcon#read 5, iclass 4, count 0 2006.217.07:36:28.53#ibcon#about to read 6, iclass 4, count 0 2006.217.07:36:28.53#ibcon#read 6, iclass 4, count 0 2006.217.07:36:28.53#ibcon#end of sib2, iclass 4, count 0 2006.217.07:36:28.53#ibcon#*mode == 0, iclass 4, count 0 2006.217.07:36:28.53#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.217.07:36:28.53#ibcon#[25=USB\r\n] 2006.217.07:36:28.53#ibcon#*before write, iclass 4, count 0 2006.217.07:36:28.53#ibcon#enter sib2, iclass 4, count 0 2006.217.07:36:28.53#ibcon#flushed, iclass 4, count 0 2006.217.07:36:28.53#ibcon#about to write, iclass 4, count 0 2006.217.07:36:28.53#ibcon#wrote, iclass 4, count 0 2006.217.07:36:28.53#ibcon#about to read 3, iclass 4, count 0 2006.217.07:36:28.56#ibcon#read 3, iclass 4, count 0 2006.217.07:36:28.56#ibcon#about to read 4, iclass 4, count 0 2006.217.07:36:28.56#ibcon#read 4, iclass 4, count 0 2006.217.07:36:28.56#ibcon#about to read 5, iclass 4, count 0 2006.217.07:36:28.56#ibcon#read 5, iclass 4, count 0 2006.217.07:36:28.56#ibcon#about to read 6, iclass 4, count 0 2006.217.07:36:28.56#ibcon#read 6, iclass 4, count 0 2006.217.07:36:28.56#ibcon#end of sib2, iclass 4, count 0 2006.217.07:36:28.56#ibcon#*after write, iclass 4, count 0 2006.217.07:36:28.56#ibcon#*before return 0, iclass 4, count 0 2006.217.07:36:28.56#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.217.07:36:28.56#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.217.07:36:28.56#ibcon#about to clear, iclass 4 cls_cnt 0 2006.217.07:36:28.56#ibcon#cleared, iclass 4 cls_cnt 0 2006.217.07:36:28.56$vc4f8/valo=3,672.99 2006.217.07:36:28.56#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.217.07:36:28.56#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.217.07:36:28.56#ibcon#ireg 17 cls_cnt 0 2006.217.07:36:28.56#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.217.07:36:28.56#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.217.07:36:28.56#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.217.07:36:28.56#ibcon#enter wrdev, iclass 6, count 0 2006.217.07:36:28.56#ibcon#first serial, iclass 6, count 0 2006.217.07:36:28.56#ibcon#enter sib2, iclass 6, count 0 2006.217.07:36:28.56#ibcon#flushed, iclass 6, count 0 2006.217.07:36:28.56#ibcon#about to write, iclass 6, count 0 2006.217.07:36:28.56#ibcon#wrote, iclass 6, count 0 2006.217.07:36:28.56#ibcon#about to read 3, iclass 6, count 0 2006.217.07:36:28.58#ibcon#read 3, iclass 6, count 0 2006.217.07:36:28.58#ibcon#about to read 4, iclass 6, count 0 2006.217.07:36:28.58#ibcon#read 4, iclass 6, count 0 2006.217.07:36:28.58#ibcon#about to read 5, iclass 6, count 0 2006.217.07:36:28.58#ibcon#read 5, iclass 6, count 0 2006.217.07:36:28.58#ibcon#about to read 6, iclass 6, count 0 2006.217.07:36:28.58#ibcon#read 6, iclass 6, count 0 2006.217.07:36:28.58#ibcon#end of sib2, iclass 6, count 0 2006.217.07:36:28.58#ibcon#*mode == 0, iclass 6, count 0 2006.217.07:36:28.58#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.217.07:36:28.58#ibcon#[26=FRQ=03,672.99\r\n] 2006.217.07:36:28.58#ibcon#*before write, iclass 6, count 0 2006.217.07:36:28.58#ibcon#enter sib2, iclass 6, count 0 2006.217.07:36:28.58#ibcon#flushed, iclass 6, count 0 2006.217.07:36:28.58#ibcon#about to write, iclass 6, count 0 2006.217.07:36:28.58#ibcon#wrote, iclass 6, count 0 2006.217.07:36:28.58#ibcon#about to read 3, iclass 6, count 0 2006.217.07:36:28.63#ibcon#read 3, iclass 6, count 0 2006.217.07:36:28.63#ibcon#about to read 4, iclass 6, count 0 2006.217.07:36:28.63#ibcon#read 4, iclass 6, count 0 2006.217.07:36:28.63#ibcon#about to read 5, iclass 6, count 0 2006.217.07:36:28.63#ibcon#read 5, iclass 6, count 0 2006.217.07:36:28.63#ibcon#about to read 6, iclass 6, count 0 2006.217.07:36:28.63#ibcon#read 6, iclass 6, count 0 2006.217.07:36:28.63#ibcon#end of sib2, iclass 6, count 0 2006.217.07:36:28.63#ibcon#*after write, iclass 6, count 0 2006.217.07:36:28.63#ibcon#*before return 0, iclass 6, count 0 2006.217.07:36:28.63#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.217.07:36:28.63#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.217.07:36:28.63#ibcon#about to clear, iclass 6 cls_cnt 0 2006.217.07:36:28.63#ibcon#cleared, iclass 6 cls_cnt 0 2006.217.07:36:28.63$vc4f8/va=3,4 2006.217.07:36:28.63#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.217.07:36:28.63#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.217.07:36:28.63#ibcon#ireg 11 cls_cnt 2 2006.217.07:36:28.63#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.217.07:36:28.68#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.217.07:36:28.68#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.217.07:36:28.68#ibcon#enter wrdev, iclass 10, count 2 2006.217.07:36:28.68#ibcon#first serial, iclass 10, count 2 2006.217.07:36:28.68#ibcon#enter sib2, iclass 10, count 2 2006.217.07:36:28.68#ibcon#flushed, iclass 10, count 2 2006.217.07:36:28.68#ibcon#about to write, iclass 10, count 2 2006.217.07:36:28.68#ibcon#wrote, iclass 10, count 2 2006.217.07:36:28.68#ibcon#about to read 3, iclass 10, count 2 2006.217.07:36:28.70#ibcon#read 3, iclass 10, count 2 2006.217.07:36:28.70#ibcon#about to read 4, iclass 10, count 2 2006.217.07:36:28.70#ibcon#read 4, iclass 10, count 2 2006.217.07:36:28.70#ibcon#about to read 5, iclass 10, count 2 2006.217.07:36:28.70#ibcon#read 5, iclass 10, count 2 2006.217.07:36:28.70#ibcon#about to read 6, iclass 10, count 2 2006.217.07:36:28.70#ibcon#read 6, iclass 10, count 2 2006.217.07:36:28.70#ibcon#end of sib2, iclass 10, count 2 2006.217.07:36:28.70#ibcon#*mode == 0, iclass 10, count 2 2006.217.07:36:28.70#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.217.07:36:28.70#ibcon#[25=AT03-04\r\n] 2006.217.07:36:28.70#ibcon#*before write, iclass 10, count 2 2006.217.07:36:28.70#ibcon#enter sib2, iclass 10, count 2 2006.217.07:36:28.70#ibcon#flushed, iclass 10, count 2 2006.217.07:36:28.70#ibcon#about to write, iclass 10, count 2 2006.217.07:36:28.70#ibcon#wrote, iclass 10, count 2 2006.217.07:36:28.70#ibcon#about to read 3, iclass 10, count 2 2006.217.07:36:28.73#ibcon#read 3, iclass 10, count 2 2006.217.07:36:28.73#ibcon#about to read 4, iclass 10, count 2 2006.217.07:36:28.73#ibcon#read 4, iclass 10, count 2 2006.217.07:36:28.73#ibcon#about to read 5, iclass 10, count 2 2006.217.07:36:28.73#ibcon#read 5, iclass 10, count 2 2006.217.07:36:28.73#ibcon#about to read 6, iclass 10, count 2 2006.217.07:36:28.73#ibcon#read 6, iclass 10, count 2 2006.217.07:36:28.73#ibcon#end of sib2, iclass 10, count 2 2006.217.07:36:28.73#ibcon#*after write, iclass 10, count 2 2006.217.07:36:28.73#ibcon#*before return 0, iclass 10, count 2 2006.217.07:36:28.73#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.217.07:36:28.73#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.217.07:36:28.73#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.217.07:36:28.73#ibcon#ireg 7 cls_cnt 0 2006.217.07:36:28.73#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.217.07:36:28.85#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.217.07:36:28.85#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.217.07:36:28.85#ibcon#enter wrdev, iclass 10, count 0 2006.217.07:36:28.85#ibcon#first serial, iclass 10, count 0 2006.217.07:36:28.85#ibcon#enter sib2, iclass 10, count 0 2006.217.07:36:28.85#ibcon#flushed, iclass 10, count 0 2006.217.07:36:28.85#ibcon#about to write, iclass 10, count 0 2006.217.07:36:28.85#ibcon#wrote, iclass 10, count 0 2006.217.07:36:28.85#ibcon#about to read 3, iclass 10, count 0 2006.217.07:36:28.87#ibcon#read 3, iclass 10, count 0 2006.217.07:36:28.87#ibcon#about to read 4, iclass 10, count 0 2006.217.07:36:28.87#ibcon#read 4, iclass 10, count 0 2006.217.07:36:28.87#ibcon#about to read 5, iclass 10, count 0 2006.217.07:36:28.87#ibcon#read 5, iclass 10, count 0 2006.217.07:36:28.87#ibcon#about to read 6, iclass 10, count 0 2006.217.07:36:28.87#ibcon#read 6, iclass 10, count 0 2006.217.07:36:28.87#ibcon#end of sib2, iclass 10, count 0 2006.217.07:36:28.87#ibcon#*mode == 0, iclass 10, count 0 2006.217.07:36:28.87#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.217.07:36:28.87#ibcon#[25=USB\r\n] 2006.217.07:36:28.87#ibcon#*before write, iclass 10, count 0 2006.217.07:36:28.87#ibcon#enter sib2, iclass 10, count 0 2006.217.07:36:28.87#ibcon#flushed, iclass 10, count 0 2006.217.07:36:28.87#ibcon#about to write, iclass 10, count 0 2006.217.07:36:28.87#ibcon#wrote, iclass 10, count 0 2006.217.07:36:28.87#ibcon#about to read 3, iclass 10, count 0 2006.217.07:36:28.90#ibcon#read 3, iclass 10, count 0 2006.217.07:36:28.90#ibcon#about to read 4, iclass 10, count 0 2006.217.07:36:28.90#ibcon#read 4, iclass 10, count 0 2006.217.07:36:28.90#ibcon#about to read 5, iclass 10, count 0 2006.217.07:36:28.90#ibcon#read 5, iclass 10, count 0 2006.217.07:36:28.90#ibcon#about to read 6, iclass 10, count 0 2006.217.07:36:28.90#ibcon#read 6, iclass 10, count 0 2006.217.07:36:28.90#ibcon#end of sib2, iclass 10, count 0 2006.217.07:36:28.90#ibcon#*after write, iclass 10, count 0 2006.217.07:36:28.90#ibcon#*before return 0, iclass 10, count 0 2006.217.07:36:28.90#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.217.07:36:28.90#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.217.07:36:28.90#ibcon#about to clear, iclass 10 cls_cnt 0 2006.217.07:36:28.90#ibcon#cleared, iclass 10 cls_cnt 0 2006.217.07:36:28.90$vc4f8/valo=4,832.99 2006.217.07:36:28.90#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.217.07:36:28.90#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.217.07:36:28.90#ibcon#ireg 17 cls_cnt 0 2006.217.07:36:28.90#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.217.07:36:28.90#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.217.07:36:28.90#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.217.07:36:28.90#ibcon#enter wrdev, iclass 12, count 0 2006.217.07:36:28.90#ibcon#first serial, iclass 12, count 0 2006.217.07:36:28.90#ibcon#enter sib2, iclass 12, count 0 2006.217.07:36:28.90#ibcon#flushed, iclass 12, count 0 2006.217.07:36:28.90#ibcon#about to write, iclass 12, count 0 2006.217.07:36:28.90#ibcon#wrote, iclass 12, count 0 2006.217.07:36:28.90#ibcon#about to read 3, iclass 12, count 0 2006.217.07:36:28.92#ibcon#read 3, iclass 12, count 0 2006.217.07:36:28.92#ibcon#about to read 4, iclass 12, count 0 2006.217.07:36:28.92#ibcon#read 4, iclass 12, count 0 2006.217.07:36:28.92#ibcon#about to read 5, iclass 12, count 0 2006.217.07:36:28.92#ibcon#read 5, iclass 12, count 0 2006.217.07:36:28.92#ibcon#about to read 6, iclass 12, count 0 2006.217.07:36:28.92#ibcon#read 6, iclass 12, count 0 2006.217.07:36:28.92#ibcon#end of sib2, iclass 12, count 0 2006.217.07:36:28.92#ibcon#*mode == 0, iclass 12, count 0 2006.217.07:36:28.92#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.217.07:36:28.92#ibcon#[26=FRQ=04,832.99\r\n] 2006.217.07:36:28.92#ibcon#*before write, iclass 12, count 0 2006.217.07:36:28.92#ibcon#enter sib2, iclass 12, count 0 2006.217.07:36:28.92#ibcon#flushed, iclass 12, count 0 2006.217.07:36:28.92#ibcon#about to write, iclass 12, count 0 2006.217.07:36:28.92#ibcon#wrote, iclass 12, count 0 2006.217.07:36:28.92#ibcon#about to read 3, iclass 12, count 0 2006.217.07:36:28.96#ibcon#read 3, iclass 12, count 0 2006.217.07:36:28.96#ibcon#about to read 4, iclass 12, count 0 2006.217.07:36:28.96#ibcon#read 4, iclass 12, count 0 2006.217.07:36:28.96#ibcon#about to read 5, iclass 12, count 0 2006.217.07:36:28.96#ibcon#read 5, iclass 12, count 0 2006.217.07:36:28.96#ibcon#about to read 6, iclass 12, count 0 2006.217.07:36:28.96#ibcon#read 6, iclass 12, count 0 2006.217.07:36:28.96#ibcon#end of sib2, iclass 12, count 0 2006.217.07:36:28.96#ibcon#*after write, iclass 12, count 0 2006.217.07:36:28.96#ibcon#*before return 0, iclass 12, count 0 2006.217.07:36:28.96#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.217.07:36:28.96#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.217.07:36:28.96#ibcon#about to clear, iclass 12 cls_cnt 0 2006.217.07:36:28.96#ibcon#cleared, iclass 12 cls_cnt 0 2006.217.07:36:28.96$vc4f8/va=4,4 2006.217.07:36:28.96#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.217.07:36:28.96#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.217.07:36:28.96#ibcon#ireg 11 cls_cnt 2 2006.217.07:36:28.96#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.217.07:36:29.02#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.217.07:36:29.02#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.217.07:36:29.02#ibcon#enter wrdev, iclass 14, count 2 2006.217.07:36:29.02#ibcon#first serial, iclass 14, count 2 2006.217.07:36:29.02#ibcon#enter sib2, iclass 14, count 2 2006.217.07:36:29.02#ibcon#flushed, iclass 14, count 2 2006.217.07:36:29.02#ibcon#about to write, iclass 14, count 2 2006.217.07:36:29.02#ibcon#wrote, iclass 14, count 2 2006.217.07:36:29.02#ibcon#about to read 3, iclass 14, count 2 2006.217.07:36:29.04#ibcon#read 3, iclass 14, count 2 2006.217.07:36:29.04#ibcon#about to read 4, iclass 14, count 2 2006.217.07:36:29.04#ibcon#read 4, iclass 14, count 2 2006.217.07:36:29.04#ibcon#about to read 5, iclass 14, count 2 2006.217.07:36:29.04#ibcon#read 5, iclass 14, count 2 2006.217.07:36:29.04#ibcon#about to read 6, iclass 14, count 2 2006.217.07:36:29.04#ibcon#read 6, iclass 14, count 2 2006.217.07:36:29.04#ibcon#end of sib2, iclass 14, count 2 2006.217.07:36:29.04#ibcon#*mode == 0, iclass 14, count 2 2006.217.07:36:29.04#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.217.07:36:29.04#ibcon#[25=AT04-04\r\n] 2006.217.07:36:29.04#ibcon#*before write, iclass 14, count 2 2006.217.07:36:29.04#ibcon#enter sib2, iclass 14, count 2 2006.217.07:36:29.04#ibcon#flushed, iclass 14, count 2 2006.217.07:36:29.04#ibcon#about to write, iclass 14, count 2 2006.217.07:36:29.04#ibcon#wrote, iclass 14, count 2 2006.217.07:36:29.04#ibcon#about to read 3, iclass 14, count 2 2006.217.07:36:29.07#ibcon#read 3, iclass 14, count 2 2006.217.07:36:29.07#ibcon#about to read 4, iclass 14, count 2 2006.217.07:36:29.07#ibcon#read 4, iclass 14, count 2 2006.217.07:36:29.07#ibcon#about to read 5, iclass 14, count 2 2006.217.07:36:29.07#ibcon#read 5, iclass 14, count 2 2006.217.07:36:29.07#ibcon#about to read 6, iclass 14, count 2 2006.217.07:36:29.07#ibcon#read 6, iclass 14, count 2 2006.217.07:36:29.07#ibcon#end of sib2, iclass 14, count 2 2006.217.07:36:29.07#ibcon#*after write, iclass 14, count 2 2006.217.07:36:29.07#ibcon#*before return 0, iclass 14, count 2 2006.217.07:36:29.07#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.217.07:36:29.07#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.217.07:36:29.07#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.217.07:36:29.07#ibcon#ireg 7 cls_cnt 0 2006.217.07:36:29.07#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.217.07:36:29.19#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.217.07:36:29.19#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.217.07:36:29.19#ibcon#enter wrdev, iclass 14, count 0 2006.217.07:36:29.19#ibcon#first serial, iclass 14, count 0 2006.217.07:36:29.19#ibcon#enter sib2, iclass 14, count 0 2006.217.07:36:29.19#ibcon#flushed, iclass 14, count 0 2006.217.07:36:29.19#ibcon#about to write, iclass 14, count 0 2006.217.07:36:29.19#ibcon#wrote, iclass 14, count 0 2006.217.07:36:29.19#ibcon#about to read 3, iclass 14, count 0 2006.217.07:36:29.21#ibcon#read 3, iclass 14, count 0 2006.217.07:36:29.21#ibcon#about to read 4, iclass 14, count 0 2006.217.07:36:29.21#ibcon#read 4, iclass 14, count 0 2006.217.07:36:29.21#ibcon#about to read 5, iclass 14, count 0 2006.217.07:36:29.21#ibcon#read 5, iclass 14, count 0 2006.217.07:36:29.21#ibcon#about to read 6, iclass 14, count 0 2006.217.07:36:29.21#ibcon#read 6, iclass 14, count 0 2006.217.07:36:29.21#ibcon#end of sib2, iclass 14, count 0 2006.217.07:36:29.21#ibcon#*mode == 0, iclass 14, count 0 2006.217.07:36:29.21#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.217.07:36:29.21#ibcon#[25=USB\r\n] 2006.217.07:36:29.21#ibcon#*before write, iclass 14, count 0 2006.217.07:36:29.21#ibcon#enter sib2, iclass 14, count 0 2006.217.07:36:29.21#ibcon#flushed, iclass 14, count 0 2006.217.07:36:29.21#ibcon#about to write, iclass 14, count 0 2006.217.07:36:29.21#ibcon#wrote, iclass 14, count 0 2006.217.07:36:29.21#ibcon#about to read 3, iclass 14, count 0 2006.217.07:36:29.24#ibcon#read 3, iclass 14, count 0 2006.217.07:36:29.24#ibcon#about to read 4, iclass 14, count 0 2006.217.07:36:29.24#ibcon#read 4, iclass 14, count 0 2006.217.07:36:29.24#ibcon#about to read 5, iclass 14, count 0 2006.217.07:36:29.24#ibcon#read 5, iclass 14, count 0 2006.217.07:36:29.24#ibcon#about to read 6, iclass 14, count 0 2006.217.07:36:29.24#ibcon#read 6, iclass 14, count 0 2006.217.07:36:29.24#ibcon#end of sib2, iclass 14, count 0 2006.217.07:36:29.24#ibcon#*after write, iclass 14, count 0 2006.217.07:36:29.24#ibcon#*before return 0, iclass 14, count 0 2006.217.07:36:29.24#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.217.07:36:29.24#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.217.07:36:29.24#ibcon#about to clear, iclass 14 cls_cnt 0 2006.217.07:36:29.24#ibcon#cleared, iclass 14 cls_cnt 0 2006.217.07:36:29.24$vc4f8/valo=5,652.99 2006.217.07:36:29.24#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.217.07:36:29.24#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.217.07:36:29.24#ibcon#ireg 17 cls_cnt 0 2006.217.07:36:29.24#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.217.07:36:29.24#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.217.07:36:29.24#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.217.07:36:29.24#ibcon#enter wrdev, iclass 16, count 0 2006.217.07:36:29.24#ibcon#first serial, iclass 16, count 0 2006.217.07:36:29.24#ibcon#enter sib2, iclass 16, count 0 2006.217.07:36:29.24#ibcon#flushed, iclass 16, count 0 2006.217.07:36:29.24#ibcon#about to write, iclass 16, count 0 2006.217.07:36:29.24#ibcon#wrote, iclass 16, count 0 2006.217.07:36:29.24#ibcon#about to read 3, iclass 16, count 0 2006.217.07:36:29.26#ibcon#read 3, iclass 16, count 0 2006.217.07:36:29.26#ibcon#about to read 4, iclass 16, count 0 2006.217.07:36:29.26#ibcon#read 4, iclass 16, count 0 2006.217.07:36:29.26#ibcon#about to read 5, iclass 16, count 0 2006.217.07:36:29.26#ibcon#read 5, iclass 16, count 0 2006.217.07:36:29.26#ibcon#about to read 6, iclass 16, count 0 2006.217.07:36:29.26#ibcon#read 6, iclass 16, count 0 2006.217.07:36:29.26#ibcon#end of sib2, iclass 16, count 0 2006.217.07:36:29.26#ibcon#*mode == 0, iclass 16, count 0 2006.217.07:36:29.26#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.217.07:36:29.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.217.07:36:29.26#ibcon#*before write, iclass 16, count 0 2006.217.07:36:29.26#ibcon#enter sib2, iclass 16, count 0 2006.217.07:36:29.26#ibcon#flushed, iclass 16, count 0 2006.217.07:36:29.26#ibcon#about to write, iclass 16, count 0 2006.217.07:36:29.26#ibcon#wrote, iclass 16, count 0 2006.217.07:36:29.26#ibcon#about to read 3, iclass 16, count 0 2006.217.07:36:29.30#ibcon#read 3, iclass 16, count 0 2006.217.07:36:29.30#ibcon#about to read 4, iclass 16, count 0 2006.217.07:36:29.30#ibcon#read 4, iclass 16, count 0 2006.217.07:36:29.30#ibcon#about to read 5, iclass 16, count 0 2006.217.07:36:29.30#ibcon#read 5, iclass 16, count 0 2006.217.07:36:29.30#ibcon#about to read 6, iclass 16, count 0 2006.217.07:36:29.30#ibcon#read 6, iclass 16, count 0 2006.217.07:36:29.30#ibcon#end of sib2, iclass 16, count 0 2006.217.07:36:29.30#ibcon#*after write, iclass 16, count 0 2006.217.07:36:29.30#ibcon#*before return 0, iclass 16, count 0 2006.217.07:36:29.30#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.217.07:36:29.30#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.217.07:36:29.30#ibcon#about to clear, iclass 16 cls_cnt 0 2006.217.07:36:29.30#ibcon#cleared, iclass 16 cls_cnt 0 2006.217.07:36:29.30$vc4f8/va=5,7 2006.217.07:36:29.30#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.217.07:36:29.30#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.217.07:36:29.30#ibcon#ireg 11 cls_cnt 2 2006.217.07:36:29.30#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.217.07:36:29.36#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.217.07:36:29.36#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.217.07:36:29.36#ibcon#enter wrdev, iclass 18, count 2 2006.217.07:36:29.36#ibcon#first serial, iclass 18, count 2 2006.217.07:36:29.36#ibcon#enter sib2, iclass 18, count 2 2006.217.07:36:29.36#ibcon#flushed, iclass 18, count 2 2006.217.07:36:29.36#ibcon#about to write, iclass 18, count 2 2006.217.07:36:29.36#ibcon#wrote, iclass 18, count 2 2006.217.07:36:29.36#ibcon#about to read 3, iclass 18, count 2 2006.217.07:36:29.38#ibcon#read 3, iclass 18, count 2 2006.217.07:36:29.38#ibcon#about to read 4, iclass 18, count 2 2006.217.07:36:29.38#ibcon#read 4, iclass 18, count 2 2006.217.07:36:29.38#ibcon#about to read 5, iclass 18, count 2 2006.217.07:36:29.38#ibcon#read 5, iclass 18, count 2 2006.217.07:36:29.38#ibcon#about to read 6, iclass 18, count 2 2006.217.07:36:29.38#ibcon#read 6, iclass 18, count 2 2006.217.07:36:29.38#ibcon#end of sib2, iclass 18, count 2 2006.217.07:36:29.38#ibcon#*mode == 0, iclass 18, count 2 2006.217.07:36:29.38#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.217.07:36:29.38#ibcon#[25=AT05-07\r\n] 2006.217.07:36:29.38#ibcon#*before write, iclass 18, count 2 2006.217.07:36:29.38#ibcon#enter sib2, iclass 18, count 2 2006.217.07:36:29.38#ibcon#flushed, iclass 18, count 2 2006.217.07:36:29.38#ibcon#about to write, iclass 18, count 2 2006.217.07:36:29.38#ibcon#wrote, iclass 18, count 2 2006.217.07:36:29.38#ibcon#about to read 3, iclass 18, count 2 2006.217.07:36:29.41#ibcon#read 3, iclass 18, count 2 2006.217.07:36:29.41#ibcon#about to read 4, iclass 18, count 2 2006.217.07:36:29.41#ibcon#read 4, iclass 18, count 2 2006.217.07:36:29.41#ibcon#about to read 5, iclass 18, count 2 2006.217.07:36:29.41#ibcon#read 5, iclass 18, count 2 2006.217.07:36:29.41#ibcon#about to read 6, iclass 18, count 2 2006.217.07:36:29.41#ibcon#read 6, iclass 18, count 2 2006.217.07:36:29.41#ibcon#end of sib2, iclass 18, count 2 2006.217.07:36:29.41#ibcon#*after write, iclass 18, count 2 2006.217.07:36:29.41#ibcon#*before return 0, iclass 18, count 2 2006.217.07:36:29.41#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.217.07:36:29.41#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.217.07:36:29.41#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.217.07:36:29.41#ibcon#ireg 7 cls_cnt 0 2006.217.07:36:29.41#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.217.07:36:29.53#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.217.07:36:29.53#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.217.07:36:29.53#ibcon#enter wrdev, iclass 18, count 0 2006.217.07:36:29.53#ibcon#first serial, iclass 18, count 0 2006.217.07:36:29.53#ibcon#enter sib2, iclass 18, count 0 2006.217.07:36:29.53#ibcon#flushed, iclass 18, count 0 2006.217.07:36:29.53#ibcon#about to write, iclass 18, count 0 2006.217.07:36:29.53#ibcon#wrote, iclass 18, count 0 2006.217.07:36:29.53#ibcon#about to read 3, iclass 18, count 0 2006.217.07:36:29.55#ibcon#read 3, iclass 18, count 0 2006.217.07:36:29.55#ibcon#about to read 4, iclass 18, count 0 2006.217.07:36:29.55#ibcon#read 4, iclass 18, count 0 2006.217.07:36:29.55#ibcon#about to read 5, iclass 18, count 0 2006.217.07:36:29.55#ibcon#read 5, iclass 18, count 0 2006.217.07:36:29.55#ibcon#about to read 6, iclass 18, count 0 2006.217.07:36:29.55#ibcon#read 6, iclass 18, count 0 2006.217.07:36:29.55#ibcon#end of sib2, iclass 18, count 0 2006.217.07:36:29.55#ibcon#*mode == 0, iclass 18, count 0 2006.217.07:36:29.55#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.217.07:36:29.55#ibcon#[25=USB\r\n] 2006.217.07:36:29.55#ibcon#*before write, iclass 18, count 0 2006.217.07:36:29.55#ibcon#enter sib2, iclass 18, count 0 2006.217.07:36:29.55#ibcon#flushed, iclass 18, count 0 2006.217.07:36:29.55#ibcon#about to write, iclass 18, count 0 2006.217.07:36:29.55#ibcon#wrote, iclass 18, count 0 2006.217.07:36:29.55#ibcon#about to read 3, iclass 18, count 0 2006.217.07:36:29.58#ibcon#read 3, iclass 18, count 0 2006.217.07:36:29.58#ibcon#about to read 4, iclass 18, count 0 2006.217.07:36:29.58#ibcon#read 4, iclass 18, count 0 2006.217.07:36:29.58#ibcon#about to read 5, iclass 18, count 0 2006.217.07:36:29.58#ibcon#read 5, iclass 18, count 0 2006.217.07:36:29.58#ibcon#about to read 6, iclass 18, count 0 2006.217.07:36:29.58#ibcon#read 6, iclass 18, count 0 2006.217.07:36:29.58#ibcon#end of sib2, iclass 18, count 0 2006.217.07:36:29.58#ibcon#*after write, iclass 18, count 0 2006.217.07:36:29.58#ibcon#*before return 0, iclass 18, count 0 2006.217.07:36:29.58#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.217.07:36:29.58#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.217.07:36:29.58#ibcon#about to clear, iclass 18 cls_cnt 0 2006.217.07:36:29.58#ibcon#cleared, iclass 18 cls_cnt 0 2006.217.07:36:29.58$vc4f8/valo=6,772.99 2006.217.07:36:29.58#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.217.07:36:29.58#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.217.07:36:29.58#ibcon#ireg 17 cls_cnt 0 2006.217.07:36:29.58#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.217.07:36:29.58#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.217.07:36:29.58#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.217.07:36:29.58#ibcon#enter wrdev, iclass 20, count 0 2006.217.07:36:29.58#ibcon#first serial, iclass 20, count 0 2006.217.07:36:29.58#ibcon#enter sib2, iclass 20, count 0 2006.217.07:36:29.58#ibcon#flushed, iclass 20, count 0 2006.217.07:36:29.58#ibcon#about to write, iclass 20, count 0 2006.217.07:36:29.58#ibcon#wrote, iclass 20, count 0 2006.217.07:36:29.58#ibcon#about to read 3, iclass 20, count 0 2006.217.07:36:29.60#ibcon#read 3, iclass 20, count 0 2006.217.07:36:29.60#ibcon#about to read 4, iclass 20, count 0 2006.217.07:36:29.60#ibcon#read 4, iclass 20, count 0 2006.217.07:36:29.60#ibcon#about to read 5, iclass 20, count 0 2006.217.07:36:29.60#ibcon#read 5, iclass 20, count 0 2006.217.07:36:29.60#ibcon#about to read 6, iclass 20, count 0 2006.217.07:36:29.60#ibcon#read 6, iclass 20, count 0 2006.217.07:36:29.60#ibcon#end of sib2, iclass 20, count 0 2006.217.07:36:29.60#ibcon#*mode == 0, iclass 20, count 0 2006.217.07:36:29.60#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.217.07:36:29.60#ibcon#[26=FRQ=06,772.99\r\n] 2006.217.07:36:29.60#ibcon#*before write, iclass 20, count 0 2006.217.07:36:29.60#ibcon#enter sib2, iclass 20, count 0 2006.217.07:36:29.60#ibcon#flushed, iclass 20, count 0 2006.217.07:36:29.60#ibcon#about to write, iclass 20, count 0 2006.217.07:36:29.60#ibcon#wrote, iclass 20, count 0 2006.217.07:36:29.60#ibcon#about to read 3, iclass 20, count 0 2006.217.07:36:29.65#ibcon#read 3, iclass 20, count 0 2006.217.07:36:29.65#ibcon#about to read 4, iclass 20, count 0 2006.217.07:36:29.65#ibcon#read 4, iclass 20, count 0 2006.217.07:36:29.65#ibcon#about to read 5, iclass 20, count 0 2006.217.07:36:29.65#ibcon#read 5, iclass 20, count 0 2006.217.07:36:29.65#ibcon#about to read 6, iclass 20, count 0 2006.217.07:36:29.65#ibcon#read 6, iclass 20, count 0 2006.217.07:36:29.65#ibcon#end of sib2, iclass 20, count 0 2006.217.07:36:29.65#ibcon#*after write, iclass 20, count 0 2006.217.07:36:29.65#ibcon#*before return 0, iclass 20, count 0 2006.217.07:36:29.65#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.217.07:36:29.65#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.217.07:36:29.65#ibcon#about to clear, iclass 20 cls_cnt 0 2006.217.07:36:29.65#ibcon#cleared, iclass 20 cls_cnt 0 2006.217.07:36:29.65$vc4f8/va=6,6 2006.217.07:36:29.65#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.217.07:36:29.65#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.217.07:36:29.65#ibcon#ireg 11 cls_cnt 2 2006.217.07:36:29.65#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.217.07:36:29.70#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.217.07:36:29.70#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.217.07:36:29.70#ibcon#enter wrdev, iclass 22, count 2 2006.217.07:36:29.70#ibcon#first serial, iclass 22, count 2 2006.217.07:36:29.70#ibcon#enter sib2, iclass 22, count 2 2006.217.07:36:29.70#ibcon#flushed, iclass 22, count 2 2006.217.07:36:29.70#ibcon#about to write, iclass 22, count 2 2006.217.07:36:29.70#ibcon#wrote, iclass 22, count 2 2006.217.07:36:29.70#ibcon#about to read 3, iclass 22, count 2 2006.217.07:36:29.72#ibcon#read 3, iclass 22, count 2 2006.217.07:36:29.72#ibcon#about to read 4, iclass 22, count 2 2006.217.07:36:29.72#ibcon#read 4, iclass 22, count 2 2006.217.07:36:29.72#ibcon#about to read 5, iclass 22, count 2 2006.217.07:36:29.72#ibcon#read 5, iclass 22, count 2 2006.217.07:36:29.72#ibcon#about to read 6, iclass 22, count 2 2006.217.07:36:29.72#ibcon#read 6, iclass 22, count 2 2006.217.07:36:29.72#ibcon#end of sib2, iclass 22, count 2 2006.217.07:36:29.72#ibcon#*mode == 0, iclass 22, count 2 2006.217.07:36:29.72#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.217.07:36:29.72#ibcon#[25=AT06-06\r\n] 2006.217.07:36:29.72#ibcon#*before write, iclass 22, count 2 2006.217.07:36:29.72#ibcon#enter sib2, iclass 22, count 2 2006.217.07:36:29.72#ibcon#flushed, iclass 22, count 2 2006.217.07:36:29.72#ibcon#about to write, iclass 22, count 2 2006.217.07:36:29.72#ibcon#wrote, iclass 22, count 2 2006.217.07:36:29.72#ibcon#about to read 3, iclass 22, count 2 2006.217.07:36:29.75#ibcon#read 3, iclass 22, count 2 2006.217.07:36:29.75#ibcon#about to read 4, iclass 22, count 2 2006.217.07:36:29.75#ibcon#read 4, iclass 22, count 2 2006.217.07:36:29.75#ibcon#about to read 5, iclass 22, count 2 2006.217.07:36:29.75#ibcon#read 5, iclass 22, count 2 2006.217.07:36:29.75#ibcon#about to read 6, iclass 22, count 2 2006.217.07:36:29.75#ibcon#read 6, iclass 22, count 2 2006.217.07:36:29.75#ibcon#end of sib2, iclass 22, count 2 2006.217.07:36:29.75#ibcon#*after write, iclass 22, count 2 2006.217.07:36:29.75#ibcon#*before return 0, iclass 22, count 2 2006.217.07:36:29.75#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.217.07:36:29.75#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.217.07:36:29.75#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.217.07:36:29.75#ibcon#ireg 7 cls_cnt 0 2006.217.07:36:29.75#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.217.07:36:29.87#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.217.07:36:29.87#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.217.07:36:29.87#ibcon#enter wrdev, iclass 22, count 0 2006.217.07:36:29.87#ibcon#first serial, iclass 22, count 0 2006.217.07:36:29.87#ibcon#enter sib2, iclass 22, count 0 2006.217.07:36:29.87#ibcon#flushed, iclass 22, count 0 2006.217.07:36:29.87#ibcon#about to write, iclass 22, count 0 2006.217.07:36:29.87#ibcon#wrote, iclass 22, count 0 2006.217.07:36:29.87#ibcon#about to read 3, iclass 22, count 0 2006.217.07:36:29.89#ibcon#read 3, iclass 22, count 0 2006.217.07:36:29.89#ibcon#about to read 4, iclass 22, count 0 2006.217.07:36:29.89#ibcon#read 4, iclass 22, count 0 2006.217.07:36:29.89#ibcon#about to read 5, iclass 22, count 0 2006.217.07:36:29.89#ibcon#read 5, iclass 22, count 0 2006.217.07:36:29.89#ibcon#about to read 6, iclass 22, count 0 2006.217.07:36:29.89#ibcon#read 6, iclass 22, count 0 2006.217.07:36:29.89#ibcon#end of sib2, iclass 22, count 0 2006.217.07:36:29.89#ibcon#*mode == 0, iclass 22, count 0 2006.217.07:36:29.89#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.217.07:36:29.89#ibcon#[25=USB\r\n] 2006.217.07:36:29.89#ibcon#*before write, iclass 22, count 0 2006.217.07:36:29.89#ibcon#enter sib2, iclass 22, count 0 2006.217.07:36:29.89#ibcon#flushed, iclass 22, count 0 2006.217.07:36:29.89#ibcon#about to write, iclass 22, count 0 2006.217.07:36:29.89#ibcon#wrote, iclass 22, count 0 2006.217.07:36:29.89#ibcon#about to read 3, iclass 22, count 0 2006.217.07:36:29.92#ibcon#read 3, iclass 22, count 0 2006.217.07:36:29.92#ibcon#about to read 4, iclass 22, count 0 2006.217.07:36:29.92#ibcon#read 4, iclass 22, count 0 2006.217.07:36:29.92#ibcon#about to read 5, iclass 22, count 0 2006.217.07:36:29.92#ibcon#read 5, iclass 22, count 0 2006.217.07:36:29.92#ibcon#about to read 6, iclass 22, count 0 2006.217.07:36:29.92#ibcon#read 6, iclass 22, count 0 2006.217.07:36:29.92#ibcon#end of sib2, iclass 22, count 0 2006.217.07:36:29.92#ibcon#*after write, iclass 22, count 0 2006.217.07:36:29.92#ibcon#*before return 0, iclass 22, count 0 2006.217.07:36:29.92#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.217.07:36:29.92#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.217.07:36:29.92#ibcon#about to clear, iclass 22 cls_cnt 0 2006.217.07:36:29.92#ibcon#cleared, iclass 22 cls_cnt 0 2006.217.07:36:29.92$vc4f8/valo=7,832.99 2006.217.07:36:29.92#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.217.07:36:29.92#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.217.07:36:29.92#ibcon#ireg 17 cls_cnt 0 2006.217.07:36:29.92#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.217.07:36:29.92#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.217.07:36:29.92#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.217.07:36:29.92#ibcon#enter wrdev, iclass 24, count 0 2006.217.07:36:29.92#ibcon#first serial, iclass 24, count 0 2006.217.07:36:29.92#ibcon#enter sib2, iclass 24, count 0 2006.217.07:36:29.92#ibcon#flushed, iclass 24, count 0 2006.217.07:36:29.92#ibcon#about to write, iclass 24, count 0 2006.217.07:36:29.92#ibcon#wrote, iclass 24, count 0 2006.217.07:36:29.92#ibcon#about to read 3, iclass 24, count 0 2006.217.07:36:29.94#ibcon#read 3, iclass 24, count 0 2006.217.07:36:29.94#ibcon#about to read 4, iclass 24, count 0 2006.217.07:36:29.94#ibcon#read 4, iclass 24, count 0 2006.217.07:36:29.94#ibcon#about to read 5, iclass 24, count 0 2006.217.07:36:29.94#ibcon#read 5, iclass 24, count 0 2006.217.07:36:29.94#ibcon#about to read 6, iclass 24, count 0 2006.217.07:36:29.94#ibcon#read 6, iclass 24, count 0 2006.217.07:36:29.94#ibcon#end of sib2, iclass 24, count 0 2006.217.07:36:29.94#ibcon#*mode == 0, iclass 24, count 0 2006.217.07:36:29.94#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.217.07:36:29.94#ibcon#[26=FRQ=07,832.99\r\n] 2006.217.07:36:29.94#ibcon#*before write, iclass 24, count 0 2006.217.07:36:29.94#ibcon#enter sib2, iclass 24, count 0 2006.217.07:36:29.94#ibcon#flushed, iclass 24, count 0 2006.217.07:36:29.94#ibcon#about to write, iclass 24, count 0 2006.217.07:36:29.94#ibcon#wrote, iclass 24, count 0 2006.217.07:36:29.94#ibcon#about to read 3, iclass 24, count 0 2006.217.07:36:29.98#ibcon#read 3, iclass 24, count 0 2006.217.07:36:29.98#ibcon#about to read 4, iclass 24, count 0 2006.217.07:36:29.98#ibcon#read 4, iclass 24, count 0 2006.217.07:36:29.98#ibcon#about to read 5, iclass 24, count 0 2006.217.07:36:29.98#ibcon#read 5, iclass 24, count 0 2006.217.07:36:29.98#ibcon#about to read 6, iclass 24, count 0 2006.217.07:36:29.98#ibcon#read 6, iclass 24, count 0 2006.217.07:36:29.98#ibcon#end of sib2, iclass 24, count 0 2006.217.07:36:29.98#ibcon#*after write, iclass 24, count 0 2006.217.07:36:29.98#ibcon#*before return 0, iclass 24, count 0 2006.217.07:36:29.98#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.217.07:36:29.98#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.217.07:36:29.98#ibcon#about to clear, iclass 24 cls_cnt 0 2006.217.07:36:29.98#ibcon#cleared, iclass 24 cls_cnt 0 2006.217.07:36:29.98$vc4f8/va=7,6 2006.217.07:36:29.98#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.217.07:36:29.98#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.217.07:36:29.98#ibcon#ireg 11 cls_cnt 2 2006.217.07:36:29.98#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.217.07:36:30.04#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.217.07:36:30.04#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.217.07:36:30.04#ibcon#enter wrdev, iclass 26, count 2 2006.217.07:36:30.04#ibcon#first serial, iclass 26, count 2 2006.217.07:36:30.04#ibcon#enter sib2, iclass 26, count 2 2006.217.07:36:30.04#ibcon#flushed, iclass 26, count 2 2006.217.07:36:30.04#ibcon#about to write, iclass 26, count 2 2006.217.07:36:30.04#ibcon#wrote, iclass 26, count 2 2006.217.07:36:30.04#ibcon#about to read 3, iclass 26, count 2 2006.217.07:36:30.06#ibcon#read 3, iclass 26, count 2 2006.217.07:36:30.06#ibcon#about to read 4, iclass 26, count 2 2006.217.07:36:30.06#ibcon#read 4, iclass 26, count 2 2006.217.07:36:30.06#ibcon#about to read 5, iclass 26, count 2 2006.217.07:36:30.06#ibcon#read 5, iclass 26, count 2 2006.217.07:36:30.06#ibcon#about to read 6, iclass 26, count 2 2006.217.07:36:30.06#ibcon#read 6, iclass 26, count 2 2006.217.07:36:30.06#ibcon#end of sib2, iclass 26, count 2 2006.217.07:36:30.06#ibcon#*mode == 0, iclass 26, count 2 2006.217.07:36:30.06#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.217.07:36:30.06#ibcon#[25=AT07-06\r\n] 2006.217.07:36:30.06#ibcon#*before write, iclass 26, count 2 2006.217.07:36:30.06#ibcon#enter sib2, iclass 26, count 2 2006.217.07:36:30.06#ibcon#flushed, iclass 26, count 2 2006.217.07:36:30.06#ibcon#about to write, iclass 26, count 2 2006.217.07:36:30.06#ibcon#wrote, iclass 26, count 2 2006.217.07:36:30.06#ibcon#about to read 3, iclass 26, count 2 2006.217.07:36:30.09#ibcon#read 3, iclass 26, count 2 2006.217.07:36:30.09#ibcon#about to read 4, iclass 26, count 2 2006.217.07:36:30.09#ibcon#read 4, iclass 26, count 2 2006.217.07:36:30.09#ibcon#about to read 5, iclass 26, count 2 2006.217.07:36:30.09#ibcon#read 5, iclass 26, count 2 2006.217.07:36:30.09#ibcon#about to read 6, iclass 26, count 2 2006.217.07:36:30.09#ibcon#read 6, iclass 26, count 2 2006.217.07:36:30.09#ibcon#end of sib2, iclass 26, count 2 2006.217.07:36:30.09#ibcon#*after write, iclass 26, count 2 2006.217.07:36:30.09#ibcon#*before return 0, iclass 26, count 2 2006.217.07:36:30.09#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.217.07:36:30.09#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.217.07:36:30.09#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.217.07:36:30.09#ibcon#ireg 7 cls_cnt 0 2006.217.07:36:30.09#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.217.07:36:30.21#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.217.07:36:30.21#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.217.07:36:30.21#ibcon#enter wrdev, iclass 26, count 0 2006.217.07:36:30.21#ibcon#first serial, iclass 26, count 0 2006.217.07:36:30.21#ibcon#enter sib2, iclass 26, count 0 2006.217.07:36:30.21#ibcon#flushed, iclass 26, count 0 2006.217.07:36:30.21#ibcon#about to write, iclass 26, count 0 2006.217.07:36:30.21#ibcon#wrote, iclass 26, count 0 2006.217.07:36:30.21#ibcon#about to read 3, iclass 26, count 0 2006.217.07:36:30.23#ibcon#read 3, iclass 26, count 0 2006.217.07:36:30.23#ibcon#about to read 4, iclass 26, count 0 2006.217.07:36:30.23#ibcon#read 4, iclass 26, count 0 2006.217.07:36:30.23#ibcon#about to read 5, iclass 26, count 0 2006.217.07:36:30.23#ibcon#read 5, iclass 26, count 0 2006.217.07:36:30.23#ibcon#about to read 6, iclass 26, count 0 2006.217.07:36:30.23#ibcon#read 6, iclass 26, count 0 2006.217.07:36:30.23#ibcon#end of sib2, iclass 26, count 0 2006.217.07:36:30.23#ibcon#*mode == 0, iclass 26, count 0 2006.217.07:36:30.23#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.217.07:36:30.23#ibcon#[25=USB\r\n] 2006.217.07:36:30.23#ibcon#*before write, iclass 26, count 0 2006.217.07:36:30.23#ibcon#enter sib2, iclass 26, count 0 2006.217.07:36:30.23#ibcon#flushed, iclass 26, count 0 2006.217.07:36:30.23#ibcon#about to write, iclass 26, count 0 2006.217.07:36:30.23#ibcon#wrote, iclass 26, count 0 2006.217.07:36:30.23#ibcon#about to read 3, iclass 26, count 0 2006.217.07:36:30.26#ibcon#read 3, iclass 26, count 0 2006.217.07:36:30.26#ibcon#about to read 4, iclass 26, count 0 2006.217.07:36:30.26#ibcon#read 4, iclass 26, count 0 2006.217.07:36:30.26#ibcon#about to read 5, iclass 26, count 0 2006.217.07:36:30.26#ibcon#read 5, iclass 26, count 0 2006.217.07:36:30.26#ibcon#about to read 6, iclass 26, count 0 2006.217.07:36:30.26#ibcon#read 6, iclass 26, count 0 2006.217.07:36:30.26#ibcon#end of sib2, iclass 26, count 0 2006.217.07:36:30.26#ibcon#*after write, iclass 26, count 0 2006.217.07:36:30.26#ibcon#*before return 0, iclass 26, count 0 2006.217.07:36:30.26#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.217.07:36:30.26#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.217.07:36:30.26#ibcon#about to clear, iclass 26 cls_cnt 0 2006.217.07:36:30.26#ibcon#cleared, iclass 26 cls_cnt 0 2006.217.07:36:30.26$vc4f8/valo=8,852.99 2006.217.07:36:30.26#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.217.07:36:30.26#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.217.07:36:30.26#ibcon#ireg 17 cls_cnt 0 2006.217.07:36:30.26#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.217.07:36:30.26#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.217.07:36:30.26#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.217.07:36:30.26#ibcon#enter wrdev, iclass 28, count 0 2006.217.07:36:30.26#ibcon#first serial, iclass 28, count 0 2006.217.07:36:30.26#ibcon#enter sib2, iclass 28, count 0 2006.217.07:36:30.26#ibcon#flushed, iclass 28, count 0 2006.217.07:36:30.26#ibcon#about to write, iclass 28, count 0 2006.217.07:36:30.26#ibcon#wrote, iclass 28, count 0 2006.217.07:36:30.26#ibcon#about to read 3, iclass 28, count 0 2006.217.07:36:30.28#ibcon#read 3, iclass 28, count 0 2006.217.07:36:30.28#ibcon#about to read 4, iclass 28, count 0 2006.217.07:36:30.28#ibcon#read 4, iclass 28, count 0 2006.217.07:36:30.28#ibcon#about to read 5, iclass 28, count 0 2006.217.07:36:30.28#ibcon#read 5, iclass 28, count 0 2006.217.07:36:30.28#ibcon#about to read 6, iclass 28, count 0 2006.217.07:36:30.28#ibcon#read 6, iclass 28, count 0 2006.217.07:36:30.28#ibcon#end of sib2, iclass 28, count 0 2006.217.07:36:30.28#ibcon#*mode == 0, iclass 28, count 0 2006.217.07:36:30.28#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.217.07:36:30.28#ibcon#[26=FRQ=08,852.99\r\n] 2006.217.07:36:30.28#ibcon#*before write, iclass 28, count 0 2006.217.07:36:30.28#ibcon#enter sib2, iclass 28, count 0 2006.217.07:36:30.28#ibcon#flushed, iclass 28, count 0 2006.217.07:36:30.28#ibcon#about to write, iclass 28, count 0 2006.217.07:36:30.28#ibcon#wrote, iclass 28, count 0 2006.217.07:36:30.28#ibcon#about to read 3, iclass 28, count 0 2006.217.07:36:30.32#ibcon#read 3, iclass 28, count 0 2006.217.07:36:30.32#ibcon#about to read 4, iclass 28, count 0 2006.217.07:36:30.32#ibcon#read 4, iclass 28, count 0 2006.217.07:36:30.32#ibcon#about to read 5, iclass 28, count 0 2006.217.07:36:30.32#ibcon#read 5, iclass 28, count 0 2006.217.07:36:30.32#ibcon#about to read 6, iclass 28, count 0 2006.217.07:36:30.32#ibcon#read 6, iclass 28, count 0 2006.217.07:36:30.32#ibcon#end of sib2, iclass 28, count 0 2006.217.07:36:30.32#ibcon#*after write, iclass 28, count 0 2006.217.07:36:30.32#ibcon#*before return 0, iclass 28, count 0 2006.217.07:36:30.32#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.217.07:36:30.32#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.217.07:36:30.32#ibcon#about to clear, iclass 28 cls_cnt 0 2006.217.07:36:30.32#ibcon#cleared, iclass 28 cls_cnt 0 2006.217.07:36:30.32$vc4f8/va=8,7 2006.217.07:36:30.32#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.217.07:36:30.32#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.217.07:36:30.32#ibcon#ireg 11 cls_cnt 2 2006.217.07:36:30.32#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.217.07:36:30.38#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.217.07:36:30.38#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.217.07:36:30.38#ibcon#enter wrdev, iclass 30, count 2 2006.217.07:36:30.38#ibcon#first serial, iclass 30, count 2 2006.217.07:36:30.38#ibcon#enter sib2, iclass 30, count 2 2006.217.07:36:30.38#ibcon#flushed, iclass 30, count 2 2006.217.07:36:30.38#ibcon#about to write, iclass 30, count 2 2006.217.07:36:30.38#ibcon#wrote, iclass 30, count 2 2006.217.07:36:30.38#ibcon#about to read 3, iclass 30, count 2 2006.217.07:36:30.40#ibcon#read 3, iclass 30, count 2 2006.217.07:36:30.40#ibcon#about to read 4, iclass 30, count 2 2006.217.07:36:30.40#ibcon#read 4, iclass 30, count 2 2006.217.07:36:30.40#ibcon#about to read 5, iclass 30, count 2 2006.217.07:36:30.40#ibcon#read 5, iclass 30, count 2 2006.217.07:36:30.40#ibcon#about to read 6, iclass 30, count 2 2006.217.07:36:30.40#ibcon#read 6, iclass 30, count 2 2006.217.07:36:30.40#ibcon#end of sib2, iclass 30, count 2 2006.217.07:36:30.40#ibcon#*mode == 0, iclass 30, count 2 2006.217.07:36:30.40#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.217.07:36:30.40#ibcon#[25=AT08-07\r\n] 2006.217.07:36:30.40#ibcon#*before write, iclass 30, count 2 2006.217.07:36:30.40#ibcon#enter sib2, iclass 30, count 2 2006.217.07:36:30.40#ibcon#flushed, iclass 30, count 2 2006.217.07:36:30.40#ibcon#about to write, iclass 30, count 2 2006.217.07:36:30.40#ibcon#wrote, iclass 30, count 2 2006.217.07:36:30.40#ibcon#about to read 3, iclass 30, count 2 2006.217.07:36:30.43#ibcon#read 3, iclass 30, count 2 2006.217.07:36:30.43#ibcon#about to read 4, iclass 30, count 2 2006.217.07:36:30.43#ibcon#read 4, iclass 30, count 2 2006.217.07:36:30.43#ibcon#about to read 5, iclass 30, count 2 2006.217.07:36:30.43#ibcon#read 5, iclass 30, count 2 2006.217.07:36:30.43#ibcon#about to read 6, iclass 30, count 2 2006.217.07:36:30.43#ibcon#read 6, iclass 30, count 2 2006.217.07:36:30.43#ibcon#end of sib2, iclass 30, count 2 2006.217.07:36:30.43#ibcon#*after write, iclass 30, count 2 2006.217.07:36:30.43#ibcon#*before return 0, iclass 30, count 2 2006.217.07:36:30.43#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.217.07:36:30.43#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.217.07:36:30.43#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.217.07:36:30.43#ibcon#ireg 7 cls_cnt 0 2006.217.07:36:30.43#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.217.07:36:30.55#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.217.07:36:30.55#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.217.07:36:30.55#ibcon#enter wrdev, iclass 30, count 0 2006.217.07:36:30.55#ibcon#first serial, iclass 30, count 0 2006.217.07:36:30.55#ibcon#enter sib2, iclass 30, count 0 2006.217.07:36:30.55#ibcon#flushed, iclass 30, count 0 2006.217.07:36:30.55#ibcon#about to write, iclass 30, count 0 2006.217.07:36:30.55#ibcon#wrote, iclass 30, count 0 2006.217.07:36:30.55#ibcon#about to read 3, iclass 30, count 0 2006.217.07:36:30.57#ibcon#read 3, iclass 30, count 0 2006.217.07:36:30.57#ibcon#about to read 4, iclass 30, count 0 2006.217.07:36:30.57#ibcon#read 4, iclass 30, count 0 2006.217.07:36:30.57#ibcon#about to read 5, iclass 30, count 0 2006.217.07:36:30.57#ibcon#read 5, iclass 30, count 0 2006.217.07:36:30.57#ibcon#about to read 6, iclass 30, count 0 2006.217.07:36:30.57#ibcon#read 6, iclass 30, count 0 2006.217.07:36:30.57#ibcon#end of sib2, iclass 30, count 0 2006.217.07:36:30.57#ibcon#*mode == 0, iclass 30, count 0 2006.217.07:36:30.57#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.217.07:36:30.57#ibcon#[25=USB\r\n] 2006.217.07:36:30.57#ibcon#*before write, iclass 30, count 0 2006.217.07:36:30.57#ibcon#enter sib2, iclass 30, count 0 2006.217.07:36:30.57#ibcon#flushed, iclass 30, count 0 2006.217.07:36:30.57#ibcon#about to write, iclass 30, count 0 2006.217.07:36:30.57#ibcon#wrote, iclass 30, count 0 2006.217.07:36:30.57#ibcon#about to read 3, iclass 30, count 0 2006.217.07:36:30.60#ibcon#read 3, iclass 30, count 0 2006.217.07:36:30.60#ibcon#about to read 4, iclass 30, count 0 2006.217.07:36:30.60#ibcon#read 4, iclass 30, count 0 2006.217.07:36:30.60#ibcon#about to read 5, iclass 30, count 0 2006.217.07:36:30.60#ibcon#read 5, iclass 30, count 0 2006.217.07:36:30.60#ibcon#about to read 6, iclass 30, count 0 2006.217.07:36:30.60#ibcon#read 6, iclass 30, count 0 2006.217.07:36:30.60#ibcon#end of sib2, iclass 30, count 0 2006.217.07:36:30.60#ibcon#*after write, iclass 30, count 0 2006.217.07:36:30.60#ibcon#*before return 0, iclass 30, count 0 2006.217.07:36:30.60#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.217.07:36:30.60#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.217.07:36:30.60#ibcon#about to clear, iclass 30 cls_cnt 0 2006.217.07:36:30.60#ibcon#cleared, iclass 30 cls_cnt 0 2006.217.07:36:30.60$vc4f8/vblo=1,632.99 2006.217.07:36:30.60#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.217.07:36:30.60#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.217.07:36:30.60#ibcon#ireg 17 cls_cnt 0 2006.217.07:36:30.60#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.217.07:36:30.60#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.217.07:36:30.60#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.217.07:36:30.60#ibcon#enter wrdev, iclass 32, count 0 2006.217.07:36:30.60#ibcon#first serial, iclass 32, count 0 2006.217.07:36:30.60#ibcon#enter sib2, iclass 32, count 0 2006.217.07:36:30.60#ibcon#flushed, iclass 32, count 0 2006.217.07:36:30.60#ibcon#about to write, iclass 32, count 0 2006.217.07:36:30.60#ibcon#wrote, iclass 32, count 0 2006.217.07:36:30.60#ibcon#about to read 3, iclass 32, count 0 2006.217.07:36:30.62#ibcon#read 3, iclass 32, count 0 2006.217.07:36:30.62#ibcon#about to read 4, iclass 32, count 0 2006.217.07:36:30.62#ibcon#read 4, iclass 32, count 0 2006.217.07:36:30.62#ibcon#about to read 5, iclass 32, count 0 2006.217.07:36:30.62#ibcon#read 5, iclass 32, count 0 2006.217.07:36:30.62#ibcon#about to read 6, iclass 32, count 0 2006.217.07:36:30.62#ibcon#read 6, iclass 32, count 0 2006.217.07:36:30.62#ibcon#end of sib2, iclass 32, count 0 2006.217.07:36:30.62#ibcon#*mode == 0, iclass 32, count 0 2006.217.07:36:30.62#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.217.07:36:30.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.217.07:36:30.62#ibcon#*before write, iclass 32, count 0 2006.217.07:36:30.62#ibcon#enter sib2, iclass 32, count 0 2006.217.07:36:30.62#ibcon#flushed, iclass 32, count 0 2006.217.07:36:30.62#ibcon#about to write, iclass 32, count 0 2006.217.07:36:30.62#ibcon#wrote, iclass 32, count 0 2006.217.07:36:30.62#ibcon#about to read 3, iclass 32, count 0 2006.217.07:36:30.67#ibcon#read 3, iclass 32, count 0 2006.217.07:36:30.67#ibcon#about to read 4, iclass 32, count 0 2006.217.07:36:30.67#ibcon#read 4, iclass 32, count 0 2006.217.07:36:30.67#ibcon#about to read 5, iclass 32, count 0 2006.217.07:36:30.67#ibcon#read 5, iclass 32, count 0 2006.217.07:36:30.67#ibcon#about to read 6, iclass 32, count 0 2006.217.07:36:30.67#ibcon#read 6, iclass 32, count 0 2006.217.07:36:30.67#ibcon#end of sib2, iclass 32, count 0 2006.217.07:36:30.67#ibcon#*after write, iclass 32, count 0 2006.217.07:36:30.67#ibcon#*before return 0, iclass 32, count 0 2006.217.07:36:30.67#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.217.07:36:30.67#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.217.07:36:30.67#ibcon#about to clear, iclass 32 cls_cnt 0 2006.217.07:36:30.67#ibcon#cleared, iclass 32 cls_cnt 0 2006.217.07:36:30.67$vc4f8/vb=1,4 2006.217.07:36:30.67#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.217.07:36:30.67#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.217.07:36:30.67#ibcon#ireg 11 cls_cnt 2 2006.217.07:36:30.67#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.217.07:36:30.67#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.217.07:36:30.67#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.217.07:36:30.67#ibcon#enter wrdev, iclass 34, count 2 2006.217.07:36:30.67#ibcon#first serial, iclass 34, count 2 2006.217.07:36:30.67#ibcon#enter sib2, iclass 34, count 2 2006.217.07:36:30.67#ibcon#flushed, iclass 34, count 2 2006.217.07:36:30.67#ibcon#about to write, iclass 34, count 2 2006.217.07:36:30.67#ibcon#wrote, iclass 34, count 2 2006.217.07:36:30.67#ibcon#about to read 3, iclass 34, count 2 2006.217.07:36:30.69#ibcon#read 3, iclass 34, count 2 2006.217.07:36:30.69#ibcon#about to read 4, iclass 34, count 2 2006.217.07:36:30.69#ibcon#read 4, iclass 34, count 2 2006.217.07:36:30.69#ibcon#about to read 5, iclass 34, count 2 2006.217.07:36:30.69#ibcon#read 5, iclass 34, count 2 2006.217.07:36:30.69#ibcon#about to read 6, iclass 34, count 2 2006.217.07:36:30.69#ibcon#read 6, iclass 34, count 2 2006.217.07:36:30.69#ibcon#end of sib2, iclass 34, count 2 2006.217.07:36:30.69#ibcon#*mode == 0, iclass 34, count 2 2006.217.07:36:30.69#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.217.07:36:30.69#ibcon#[27=AT01-04\r\n] 2006.217.07:36:30.69#ibcon#*before write, iclass 34, count 2 2006.217.07:36:30.69#ibcon#enter sib2, iclass 34, count 2 2006.217.07:36:30.69#ibcon#flushed, iclass 34, count 2 2006.217.07:36:30.69#ibcon#about to write, iclass 34, count 2 2006.217.07:36:30.69#ibcon#wrote, iclass 34, count 2 2006.217.07:36:30.69#ibcon#about to read 3, iclass 34, count 2 2006.217.07:36:30.72#ibcon#read 3, iclass 34, count 2 2006.217.07:36:30.72#ibcon#about to read 4, iclass 34, count 2 2006.217.07:36:30.72#ibcon#read 4, iclass 34, count 2 2006.217.07:36:30.72#ibcon#about to read 5, iclass 34, count 2 2006.217.07:36:30.72#ibcon#read 5, iclass 34, count 2 2006.217.07:36:30.72#ibcon#about to read 6, iclass 34, count 2 2006.217.07:36:30.72#ibcon#read 6, iclass 34, count 2 2006.217.07:36:30.72#ibcon#end of sib2, iclass 34, count 2 2006.217.07:36:30.72#ibcon#*after write, iclass 34, count 2 2006.217.07:36:30.72#ibcon#*before return 0, iclass 34, count 2 2006.217.07:36:30.72#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.217.07:36:30.72#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.217.07:36:30.72#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.217.07:36:30.72#ibcon#ireg 7 cls_cnt 0 2006.217.07:36:30.72#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.217.07:36:30.84#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.217.07:36:30.84#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.217.07:36:30.84#ibcon#enter wrdev, iclass 34, count 0 2006.217.07:36:30.84#ibcon#first serial, iclass 34, count 0 2006.217.07:36:30.84#ibcon#enter sib2, iclass 34, count 0 2006.217.07:36:30.84#ibcon#flushed, iclass 34, count 0 2006.217.07:36:30.84#ibcon#about to write, iclass 34, count 0 2006.217.07:36:30.84#ibcon#wrote, iclass 34, count 0 2006.217.07:36:30.84#ibcon#about to read 3, iclass 34, count 0 2006.217.07:36:30.86#ibcon#read 3, iclass 34, count 0 2006.217.07:36:30.86#ibcon#about to read 4, iclass 34, count 0 2006.217.07:36:30.86#ibcon#read 4, iclass 34, count 0 2006.217.07:36:30.86#ibcon#about to read 5, iclass 34, count 0 2006.217.07:36:30.86#ibcon#read 5, iclass 34, count 0 2006.217.07:36:30.86#ibcon#about to read 6, iclass 34, count 0 2006.217.07:36:30.86#ibcon#read 6, iclass 34, count 0 2006.217.07:36:30.86#ibcon#end of sib2, iclass 34, count 0 2006.217.07:36:30.86#ibcon#*mode == 0, iclass 34, count 0 2006.217.07:36:30.86#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.217.07:36:30.86#ibcon#[27=USB\r\n] 2006.217.07:36:30.86#ibcon#*before write, iclass 34, count 0 2006.217.07:36:30.86#ibcon#enter sib2, iclass 34, count 0 2006.217.07:36:30.86#ibcon#flushed, iclass 34, count 0 2006.217.07:36:30.86#ibcon#about to write, iclass 34, count 0 2006.217.07:36:30.86#ibcon#wrote, iclass 34, count 0 2006.217.07:36:30.86#ibcon#about to read 3, iclass 34, count 0 2006.217.07:36:30.89#ibcon#read 3, iclass 34, count 0 2006.217.07:36:30.89#ibcon#about to read 4, iclass 34, count 0 2006.217.07:36:30.89#ibcon#read 4, iclass 34, count 0 2006.217.07:36:30.89#ibcon#about to read 5, iclass 34, count 0 2006.217.07:36:30.89#ibcon#read 5, iclass 34, count 0 2006.217.07:36:30.89#ibcon#about to read 6, iclass 34, count 0 2006.217.07:36:30.89#ibcon#read 6, iclass 34, count 0 2006.217.07:36:30.89#ibcon#end of sib2, iclass 34, count 0 2006.217.07:36:30.89#ibcon#*after write, iclass 34, count 0 2006.217.07:36:30.89#ibcon#*before return 0, iclass 34, count 0 2006.217.07:36:30.89#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.217.07:36:30.89#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.217.07:36:30.89#ibcon#about to clear, iclass 34 cls_cnt 0 2006.217.07:36:30.89#ibcon#cleared, iclass 34 cls_cnt 0 2006.217.07:36:30.89$vc4f8/vblo=2,640.99 2006.217.07:36:30.89#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.217.07:36:30.89#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.217.07:36:30.89#ibcon#ireg 17 cls_cnt 0 2006.217.07:36:30.89#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.217.07:36:30.89#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.217.07:36:30.89#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.217.07:36:30.89#ibcon#enter wrdev, iclass 36, count 0 2006.217.07:36:30.89#ibcon#first serial, iclass 36, count 0 2006.217.07:36:30.89#ibcon#enter sib2, iclass 36, count 0 2006.217.07:36:30.89#ibcon#flushed, iclass 36, count 0 2006.217.07:36:30.89#ibcon#about to write, iclass 36, count 0 2006.217.07:36:30.89#ibcon#wrote, iclass 36, count 0 2006.217.07:36:30.89#ibcon#about to read 3, iclass 36, count 0 2006.217.07:36:30.91#ibcon#read 3, iclass 36, count 0 2006.217.07:36:30.91#ibcon#about to read 4, iclass 36, count 0 2006.217.07:36:30.91#ibcon#read 4, iclass 36, count 0 2006.217.07:36:30.91#ibcon#about to read 5, iclass 36, count 0 2006.217.07:36:30.91#ibcon#read 5, iclass 36, count 0 2006.217.07:36:30.91#ibcon#about to read 6, iclass 36, count 0 2006.217.07:36:30.91#ibcon#read 6, iclass 36, count 0 2006.217.07:36:30.91#ibcon#end of sib2, iclass 36, count 0 2006.217.07:36:30.91#ibcon#*mode == 0, iclass 36, count 0 2006.217.07:36:30.91#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.217.07:36:30.91#ibcon#[28=FRQ=02,640.99\r\n] 2006.217.07:36:30.91#ibcon#*before write, iclass 36, count 0 2006.217.07:36:30.91#ibcon#enter sib2, iclass 36, count 0 2006.217.07:36:30.91#ibcon#flushed, iclass 36, count 0 2006.217.07:36:30.91#ibcon#about to write, iclass 36, count 0 2006.217.07:36:30.91#ibcon#wrote, iclass 36, count 0 2006.217.07:36:30.91#ibcon#about to read 3, iclass 36, count 0 2006.217.07:36:30.95#ibcon#read 3, iclass 36, count 0 2006.217.07:36:30.95#ibcon#about to read 4, iclass 36, count 0 2006.217.07:36:30.95#ibcon#read 4, iclass 36, count 0 2006.217.07:36:30.95#ibcon#about to read 5, iclass 36, count 0 2006.217.07:36:30.95#ibcon#read 5, iclass 36, count 0 2006.217.07:36:30.95#ibcon#about to read 6, iclass 36, count 0 2006.217.07:36:30.95#ibcon#read 6, iclass 36, count 0 2006.217.07:36:30.95#ibcon#end of sib2, iclass 36, count 0 2006.217.07:36:30.95#ibcon#*after write, iclass 36, count 0 2006.217.07:36:30.95#ibcon#*before return 0, iclass 36, count 0 2006.217.07:36:30.95#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.217.07:36:30.95#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.217.07:36:30.95#ibcon#about to clear, iclass 36 cls_cnt 0 2006.217.07:36:30.95#ibcon#cleared, iclass 36 cls_cnt 0 2006.217.07:36:30.95$vc4f8/vb=2,4 2006.217.07:36:30.95#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.217.07:36:30.95#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.217.07:36:30.95#ibcon#ireg 11 cls_cnt 2 2006.217.07:36:30.95#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.217.07:36:31.01#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.217.07:36:31.01#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.217.07:36:31.01#ibcon#enter wrdev, iclass 38, count 2 2006.217.07:36:31.01#ibcon#first serial, iclass 38, count 2 2006.217.07:36:31.01#ibcon#enter sib2, iclass 38, count 2 2006.217.07:36:31.01#ibcon#flushed, iclass 38, count 2 2006.217.07:36:31.01#ibcon#about to write, iclass 38, count 2 2006.217.07:36:31.01#ibcon#wrote, iclass 38, count 2 2006.217.07:36:31.01#ibcon#about to read 3, iclass 38, count 2 2006.217.07:36:31.03#ibcon#read 3, iclass 38, count 2 2006.217.07:36:31.03#ibcon#about to read 4, iclass 38, count 2 2006.217.07:36:31.03#ibcon#read 4, iclass 38, count 2 2006.217.07:36:31.03#ibcon#about to read 5, iclass 38, count 2 2006.217.07:36:31.03#ibcon#read 5, iclass 38, count 2 2006.217.07:36:31.03#ibcon#about to read 6, iclass 38, count 2 2006.217.07:36:31.03#ibcon#read 6, iclass 38, count 2 2006.217.07:36:31.03#ibcon#end of sib2, iclass 38, count 2 2006.217.07:36:31.03#ibcon#*mode == 0, iclass 38, count 2 2006.217.07:36:31.03#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.217.07:36:31.03#ibcon#[27=AT02-04\r\n] 2006.217.07:36:31.03#ibcon#*before write, iclass 38, count 2 2006.217.07:36:31.03#ibcon#enter sib2, iclass 38, count 2 2006.217.07:36:31.03#ibcon#flushed, iclass 38, count 2 2006.217.07:36:31.03#ibcon#about to write, iclass 38, count 2 2006.217.07:36:31.03#ibcon#wrote, iclass 38, count 2 2006.217.07:36:31.03#ibcon#about to read 3, iclass 38, count 2 2006.217.07:36:31.06#ibcon#read 3, iclass 38, count 2 2006.217.07:36:31.06#ibcon#about to read 4, iclass 38, count 2 2006.217.07:36:31.06#ibcon#read 4, iclass 38, count 2 2006.217.07:36:31.06#ibcon#about to read 5, iclass 38, count 2 2006.217.07:36:31.06#ibcon#read 5, iclass 38, count 2 2006.217.07:36:31.06#ibcon#about to read 6, iclass 38, count 2 2006.217.07:36:31.06#ibcon#read 6, iclass 38, count 2 2006.217.07:36:31.06#ibcon#end of sib2, iclass 38, count 2 2006.217.07:36:31.06#ibcon#*after write, iclass 38, count 2 2006.217.07:36:31.06#ibcon#*before return 0, iclass 38, count 2 2006.217.07:36:31.06#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.217.07:36:31.06#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.217.07:36:31.06#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.217.07:36:31.06#ibcon#ireg 7 cls_cnt 0 2006.217.07:36:31.06#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.217.07:36:31.18#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.217.07:36:31.18#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.217.07:36:31.18#ibcon#enter wrdev, iclass 38, count 0 2006.217.07:36:31.18#ibcon#first serial, iclass 38, count 0 2006.217.07:36:31.18#ibcon#enter sib2, iclass 38, count 0 2006.217.07:36:31.18#ibcon#flushed, iclass 38, count 0 2006.217.07:36:31.18#ibcon#about to write, iclass 38, count 0 2006.217.07:36:31.18#ibcon#wrote, iclass 38, count 0 2006.217.07:36:31.18#ibcon#about to read 3, iclass 38, count 0 2006.217.07:36:31.20#ibcon#read 3, iclass 38, count 0 2006.217.07:36:31.20#ibcon#about to read 4, iclass 38, count 0 2006.217.07:36:31.20#ibcon#read 4, iclass 38, count 0 2006.217.07:36:31.20#ibcon#about to read 5, iclass 38, count 0 2006.217.07:36:31.20#ibcon#read 5, iclass 38, count 0 2006.217.07:36:31.20#ibcon#about to read 6, iclass 38, count 0 2006.217.07:36:31.20#ibcon#read 6, iclass 38, count 0 2006.217.07:36:31.20#ibcon#end of sib2, iclass 38, count 0 2006.217.07:36:31.20#ibcon#*mode == 0, iclass 38, count 0 2006.217.07:36:31.20#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.217.07:36:31.20#ibcon#[27=USB\r\n] 2006.217.07:36:31.20#ibcon#*before write, iclass 38, count 0 2006.217.07:36:31.20#ibcon#enter sib2, iclass 38, count 0 2006.217.07:36:31.20#ibcon#flushed, iclass 38, count 0 2006.217.07:36:31.20#ibcon#about to write, iclass 38, count 0 2006.217.07:36:31.20#ibcon#wrote, iclass 38, count 0 2006.217.07:36:31.20#ibcon#about to read 3, iclass 38, count 0 2006.217.07:36:31.23#ibcon#read 3, iclass 38, count 0 2006.217.07:36:31.23#ibcon#about to read 4, iclass 38, count 0 2006.217.07:36:31.23#ibcon#read 4, iclass 38, count 0 2006.217.07:36:31.23#ibcon#about to read 5, iclass 38, count 0 2006.217.07:36:31.23#ibcon#read 5, iclass 38, count 0 2006.217.07:36:31.23#ibcon#about to read 6, iclass 38, count 0 2006.217.07:36:31.23#ibcon#read 6, iclass 38, count 0 2006.217.07:36:31.23#ibcon#end of sib2, iclass 38, count 0 2006.217.07:36:31.23#ibcon#*after write, iclass 38, count 0 2006.217.07:36:31.23#ibcon#*before return 0, iclass 38, count 0 2006.217.07:36:31.23#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.217.07:36:31.23#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.217.07:36:31.23#ibcon#about to clear, iclass 38 cls_cnt 0 2006.217.07:36:31.23#ibcon#cleared, iclass 38 cls_cnt 0 2006.217.07:36:31.23$vc4f8/vblo=3,656.99 2006.217.07:36:31.23#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.217.07:36:31.23#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.217.07:36:31.23#ibcon#ireg 17 cls_cnt 0 2006.217.07:36:31.23#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.217.07:36:31.23#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.217.07:36:31.23#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.217.07:36:31.23#ibcon#enter wrdev, iclass 40, count 0 2006.217.07:36:31.23#ibcon#first serial, iclass 40, count 0 2006.217.07:36:31.23#ibcon#enter sib2, iclass 40, count 0 2006.217.07:36:31.23#ibcon#flushed, iclass 40, count 0 2006.217.07:36:31.23#ibcon#about to write, iclass 40, count 0 2006.217.07:36:31.23#ibcon#wrote, iclass 40, count 0 2006.217.07:36:31.23#ibcon#about to read 3, iclass 40, count 0 2006.217.07:36:31.25#ibcon#read 3, iclass 40, count 0 2006.217.07:36:31.25#ibcon#about to read 4, iclass 40, count 0 2006.217.07:36:31.25#ibcon#read 4, iclass 40, count 0 2006.217.07:36:31.25#ibcon#about to read 5, iclass 40, count 0 2006.217.07:36:31.25#ibcon#read 5, iclass 40, count 0 2006.217.07:36:31.25#ibcon#about to read 6, iclass 40, count 0 2006.217.07:36:31.25#ibcon#read 6, iclass 40, count 0 2006.217.07:36:31.25#ibcon#end of sib2, iclass 40, count 0 2006.217.07:36:31.25#ibcon#*mode == 0, iclass 40, count 0 2006.217.07:36:31.25#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.217.07:36:31.25#ibcon#[28=FRQ=03,656.99\r\n] 2006.217.07:36:31.25#ibcon#*before write, iclass 40, count 0 2006.217.07:36:31.25#ibcon#enter sib2, iclass 40, count 0 2006.217.07:36:31.25#ibcon#flushed, iclass 40, count 0 2006.217.07:36:31.25#ibcon#about to write, iclass 40, count 0 2006.217.07:36:31.25#ibcon#wrote, iclass 40, count 0 2006.217.07:36:31.25#ibcon#about to read 3, iclass 40, count 0 2006.217.07:36:31.29#ibcon#read 3, iclass 40, count 0 2006.217.07:36:31.29#ibcon#about to read 4, iclass 40, count 0 2006.217.07:36:31.29#ibcon#read 4, iclass 40, count 0 2006.217.07:36:31.29#ibcon#about to read 5, iclass 40, count 0 2006.217.07:36:31.29#ibcon#read 5, iclass 40, count 0 2006.217.07:36:31.29#ibcon#about to read 6, iclass 40, count 0 2006.217.07:36:31.29#ibcon#read 6, iclass 40, count 0 2006.217.07:36:31.29#ibcon#end of sib2, iclass 40, count 0 2006.217.07:36:31.29#ibcon#*after write, iclass 40, count 0 2006.217.07:36:31.29#ibcon#*before return 0, iclass 40, count 0 2006.217.07:36:31.29#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.217.07:36:31.29#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.217.07:36:31.29#ibcon#about to clear, iclass 40 cls_cnt 0 2006.217.07:36:31.29#ibcon#cleared, iclass 40 cls_cnt 0 2006.217.07:36:31.29$vc4f8/vb=3,4 2006.217.07:36:31.29#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.217.07:36:31.29#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.217.07:36:31.29#ibcon#ireg 11 cls_cnt 2 2006.217.07:36:31.29#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.217.07:36:31.35#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.217.07:36:31.35#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.217.07:36:31.35#ibcon#enter wrdev, iclass 4, count 2 2006.217.07:36:31.35#ibcon#first serial, iclass 4, count 2 2006.217.07:36:31.35#ibcon#enter sib2, iclass 4, count 2 2006.217.07:36:31.35#ibcon#flushed, iclass 4, count 2 2006.217.07:36:31.35#ibcon#about to write, iclass 4, count 2 2006.217.07:36:31.35#ibcon#wrote, iclass 4, count 2 2006.217.07:36:31.35#ibcon#about to read 3, iclass 4, count 2 2006.217.07:36:31.37#ibcon#read 3, iclass 4, count 2 2006.217.07:36:31.37#ibcon#about to read 4, iclass 4, count 2 2006.217.07:36:31.37#ibcon#read 4, iclass 4, count 2 2006.217.07:36:31.37#ibcon#about to read 5, iclass 4, count 2 2006.217.07:36:31.37#ibcon#read 5, iclass 4, count 2 2006.217.07:36:31.37#ibcon#about to read 6, iclass 4, count 2 2006.217.07:36:31.37#ibcon#read 6, iclass 4, count 2 2006.217.07:36:31.37#ibcon#end of sib2, iclass 4, count 2 2006.217.07:36:31.37#ibcon#*mode == 0, iclass 4, count 2 2006.217.07:36:31.37#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.217.07:36:31.37#ibcon#[27=AT03-04\r\n] 2006.217.07:36:31.37#ibcon#*before write, iclass 4, count 2 2006.217.07:36:31.37#ibcon#enter sib2, iclass 4, count 2 2006.217.07:36:31.37#ibcon#flushed, iclass 4, count 2 2006.217.07:36:31.37#ibcon#about to write, iclass 4, count 2 2006.217.07:36:31.37#ibcon#wrote, iclass 4, count 2 2006.217.07:36:31.37#ibcon#about to read 3, iclass 4, count 2 2006.217.07:36:31.40#ibcon#read 3, iclass 4, count 2 2006.217.07:36:31.40#ibcon#about to read 4, iclass 4, count 2 2006.217.07:36:31.40#ibcon#read 4, iclass 4, count 2 2006.217.07:36:31.40#ibcon#about to read 5, iclass 4, count 2 2006.217.07:36:31.40#ibcon#read 5, iclass 4, count 2 2006.217.07:36:31.40#ibcon#about to read 6, iclass 4, count 2 2006.217.07:36:31.40#ibcon#read 6, iclass 4, count 2 2006.217.07:36:31.40#ibcon#end of sib2, iclass 4, count 2 2006.217.07:36:31.40#ibcon#*after write, iclass 4, count 2 2006.217.07:36:31.40#ibcon#*before return 0, iclass 4, count 2 2006.217.07:36:31.40#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.217.07:36:31.40#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.217.07:36:31.40#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.217.07:36:31.40#ibcon#ireg 7 cls_cnt 0 2006.217.07:36:31.40#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.217.07:36:31.52#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.217.07:36:31.52#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.217.07:36:31.52#ibcon#enter wrdev, iclass 4, count 0 2006.217.07:36:31.52#ibcon#first serial, iclass 4, count 0 2006.217.07:36:31.52#ibcon#enter sib2, iclass 4, count 0 2006.217.07:36:31.52#ibcon#flushed, iclass 4, count 0 2006.217.07:36:31.52#ibcon#about to write, iclass 4, count 0 2006.217.07:36:31.52#ibcon#wrote, iclass 4, count 0 2006.217.07:36:31.52#ibcon#about to read 3, iclass 4, count 0 2006.217.07:36:31.54#ibcon#read 3, iclass 4, count 0 2006.217.07:36:31.54#ibcon#about to read 4, iclass 4, count 0 2006.217.07:36:31.54#ibcon#read 4, iclass 4, count 0 2006.217.07:36:31.54#ibcon#about to read 5, iclass 4, count 0 2006.217.07:36:31.54#ibcon#read 5, iclass 4, count 0 2006.217.07:36:31.54#ibcon#about to read 6, iclass 4, count 0 2006.217.07:36:31.54#ibcon#read 6, iclass 4, count 0 2006.217.07:36:31.54#ibcon#end of sib2, iclass 4, count 0 2006.217.07:36:31.54#ibcon#*mode == 0, iclass 4, count 0 2006.217.07:36:31.54#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.217.07:36:31.54#ibcon#[27=USB\r\n] 2006.217.07:36:31.54#ibcon#*before write, iclass 4, count 0 2006.217.07:36:31.54#ibcon#enter sib2, iclass 4, count 0 2006.217.07:36:31.54#ibcon#flushed, iclass 4, count 0 2006.217.07:36:31.54#ibcon#about to write, iclass 4, count 0 2006.217.07:36:31.54#ibcon#wrote, iclass 4, count 0 2006.217.07:36:31.54#ibcon#about to read 3, iclass 4, count 0 2006.217.07:36:31.57#ibcon#read 3, iclass 4, count 0 2006.217.07:36:31.57#ibcon#about to read 4, iclass 4, count 0 2006.217.07:36:31.57#ibcon#read 4, iclass 4, count 0 2006.217.07:36:31.57#ibcon#about to read 5, iclass 4, count 0 2006.217.07:36:31.57#ibcon#read 5, iclass 4, count 0 2006.217.07:36:31.57#ibcon#about to read 6, iclass 4, count 0 2006.217.07:36:31.57#ibcon#read 6, iclass 4, count 0 2006.217.07:36:31.57#ibcon#end of sib2, iclass 4, count 0 2006.217.07:36:31.57#ibcon#*after write, iclass 4, count 0 2006.217.07:36:31.57#ibcon#*before return 0, iclass 4, count 0 2006.217.07:36:31.57#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.217.07:36:31.57#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.217.07:36:31.57#ibcon#about to clear, iclass 4 cls_cnt 0 2006.217.07:36:31.57#ibcon#cleared, iclass 4 cls_cnt 0 2006.217.07:36:31.57$vc4f8/vblo=4,712.99 2006.217.07:36:31.57#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.217.07:36:31.57#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.217.07:36:31.57#ibcon#ireg 17 cls_cnt 0 2006.217.07:36:31.57#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.217.07:36:31.57#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.217.07:36:31.57#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.217.07:36:31.57#ibcon#enter wrdev, iclass 6, count 0 2006.217.07:36:31.57#ibcon#first serial, iclass 6, count 0 2006.217.07:36:31.57#ibcon#enter sib2, iclass 6, count 0 2006.217.07:36:31.57#ibcon#flushed, iclass 6, count 0 2006.217.07:36:31.57#ibcon#about to write, iclass 6, count 0 2006.217.07:36:31.57#ibcon#wrote, iclass 6, count 0 2006.217.07:36:31.57#ibcon#about to read 3, iclass 6, count 0 2006.217.07:36:31.59#ibcon#read 3, iclass 6, count 0 2006.217.07:36:31.59#ibcon#about to read 4, iclass 6, count 0 2006.217.07:36:31.59#ibcon#read 4, iclass 6, count 0 2006.217.07:36:31.59#ibcon#about to read 5, iclass 6, count 0 2006.217.07:36:31.59#ibcon#read 5, iclass 6, count 0 2006.217.07:36:31.59#ibcon#about to read 6, iclass 6, count 0 2006.217.07:36:31.59#ibcon#read 6, iclass 6, count 0 2006.217.07:36:31.59#ibcon#end of sib2, iclass 6, count 0 2006.217.07:36:31.59#ibcon#*mode == 0, iclass 6, count 0 2006.217.07:36:31.59#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.217.07:36:31.59#ibcon#[28=FRQ=04,712.99\r\n] 2006.217.07:36:31.59#ibcon#*before write, iclass 6, count 0 2006.217.07:36:31.59#ibcon#enter sib2, iclass 6, count 0 2006.217.07:36:31.59#ibcon#flushed, iclass 6, count 0 2006.217.07:36:31.59#ibcon#about to write, iclass 6, count 0 2006.217.07:36:31.59#ibcon#wrote, iclass 6, count 0 2006.217.07:36:31.59#ibcon#about to read 3, iclass 6, count 0 2006.217.07:36:31.64#ibcon#read 3, iclass 6, count 0 2006.217.07:36:31.64#ibcon#about to read 4, iclass 6, count 0 2006.217.07:36:31.64#ibcon#read 4, iclass 6, count 0 2006.217.07:36:31.64#ibcon#about to read 5, iclass 6, count 0 2006.217.07:36:31.64#ibcon#read 5, iclass 6, count 0 2006.217.07:36:31.64#ibcon#about to read 6, iclass 6, count 0 2006.217.07:36:31.64#ibcon#read 6, iclass 6, count 0 2006.217.07:36:31.64#ibcon#end of sib2, iclass 6, count 0 2006.217.07:36:31.64#ibcon#*after write, iclass 6, count 0 2006.217.07:36:31.64#ibcon#*before return 0, iclass 6, count 0 2006.217.07:36:31.64#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.217.07:36:31.64#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.217.07:36:31.64#ibcon#about to clear, iclass 6 cls_cnt 0 2006.217.07:36:31.64#ibcon#cleared, iclass 6 cls_cnt 0 2006.217.07:36:31.64$vc4f8/vb=4,4 2006.217.07:36:31.64#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.217.07:36:31.64#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.217.07:36:31.64#ibcon#ireg 11 cls_cnt 2 2006.217.07:36:31.64#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.217.07:36:31.69#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.217.07:36:31.69#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.217.07:36:31.69#ibcon#enter wrdev, iclass 10, count 2 2006.217.07:36:31.69#ibcon#first serial, iclass 10, count 2 2006.217.07:36:31.69#ibcon#enter sib2, iclass 10, count 2 2006.217.07:36:31.69#ibcon#flushed, iclass 10, count 2 2006.217.07:36:31.69#ibcon#about to write, iclass 10, count 2 2006.217.07:36:31.69#ibcon#wrote, iclass 10, count 2 2006.217.07:36:31.69#ibcon#about to read 3, iclass 10, count 2 2006.217.07:36:31.71#ibcon#read 3, iclass 10, count 2 2006.217.07:36:31.71#ibcon#about to read 4, iclass 10, count 2 2006.217.07:36:31.71#ibcon#read 4, iclass 10, count 2 2006.217.07:36:31.71#ibcon#about to read 5, iclass 10, count 2 2006.217.07:36:31.71#ibcon#read 5, iclass 10, count 2 2006.217.07:36:31.71#ibcon#about to read 6, iclass 10, count 2 2006.217.07:36:31.71#ibcon#read 6, iclass 10, count 2 2006.217.07:36:31.71#ibcon#end of sib2, iclass 10, count 2 2006.217.07:36:31.71#ibcon#*mode == 0, iclass 10, count 2 2006.217.07:36:31.71#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.217.07:36:31.71#ibcon#[27=AT04-04\r\n] 2006.217.07:36:31.71#ibcon#*before write, iclass 10, count 2 2006.217.07:36:31.71#ibcon#enter sib2, iclass 10, count 2 2006.217.07:36:31.71#ibcon#flushed, iclass 10, count 2 2006.217.07:36:31.71#ibcon#about to write, iclass 10, count 2 2006.217.07:36:31.71#ibcon#wrote, iclass 10, count 2 2006.217.07:36:31.71#ibcon#about to read 3, iclass 10, count 2 2006.217.07:36:31.74#ibcon#read 3, iclass 10, count 2 2006.217.07:36:31.74#ibcon#about to read 4, iclass 10, count 2 2006.217.07:36:31.74#ibcon#read 4, iclass 10, count 2 2006.217.07:36:31.74#ibcon#about to read 5, iclass 10, count 2 2006.217.07:36:31.74#ibcon#read 5, iclass 10, count 2 2006.217.07:36:31.74#ibcon#about to read 6, iclass 10, count 2 2006.217.07:36:31.74#ibcon#read 6, iclass 10, count 2 2006.217.07:36:31.74#ibcon#end of sib2, iclass 10, count 2 2006.217.07:36:31.74#ibcon#*after write, iclass 10, count 2 2006.217.07:36:31.74#ibcon#*before return 0, iclass 10, count 2 2006.217.07:36:31.74#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.217.07:36:31.74#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.217.07:36:31.74#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.217.07:36:31.74#ibcon#ireg 7 cls_cnt 0 2006.217.07:36:31.74#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.217.07:36:31.86#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.217.07:36:31.86#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.217.07:36:31.86#ibcon#enter wrdev, iclass 10, count 0 2006.217.07:36:31.86#ibcon#first serial, iclass 10, count 0 2006.217.07:36:31.86#ibcon#enter sib2, iclass 10, count 0 2006.217.07:36:31.86#ibcon#flushed, iclass 10, count 0 2006.217.07:36:31.86#ibcon#about to write, iclass 10, count 0 2006.217.07:36:31.86#ibcon#wrote, iclass 10, count 0 2006.217.07:36:31.86#ibcon#about to read 3, iclass 10, count 0 2006.217.07:36:31.88#ibcon#read 3, iclass 10, count 0 2006.217.07:36:31.88#ibcon#about to read 4, iclass 10, count 0 2006.217.07:36:31.88#ibcon#read 4, iclass 10, count 0 2006.217.07:36:31.88#ibcon#about to read 5, iclass 10, count 0 2006.217.07:36:31.88#ibcon#read 5, iclass 10, count 0 2006.217.07:36:31.88#ibcon#about to read 6, iclass 10, count 0 2006.217.07:36:31.88#ibcon#read 6, iclass 10, count 0 2006.217.07:36:31.88#ibcon#end of sib2, iclass 10, count 0 2006.217.07:36:31.88#ibcon#*mode == 0, iclass 10, count 0 2006.217.07:36:31.88#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.217.07:36:31.88#ibcon#[27=USB\r\n] 2006.217.07:36:31.88#ibcon#*before write, iclass 10, count 0 2006.217.07:36:31.88#ibcon#enter sib2, iclass 10, count 0 2006.217.07:36:31.88#ibcon#flushed, iclass 10, count 0 2006.217.07:36:31.88#ibcon#about to write, iclass 10, count 0 2006.217.07:36:31.88#ibcon#wrote, iclass 10, count 0 2006.217.07:36:31.88#ibcon#about to read 3, iclass 10, count 0 2006.217.07:36:31.91#ibcon#read 3, iclass 10, count 0 2006.217.07:36:31.91#ibcon#about to read 4, iclass 10, count 0 2006.217.07:36:31.91#ibcon#read 4, iclass 10, count 0 2006.217.07:36:31.91#ibcon#about to read 5, iclass 10, count 0 2006.217.07:36:31.91#ibcon#read 5, iclass 10, count 0 2006.217.07:36:31.91#ibcon#about to read 6, iclass 10, count 0 2006.217.07:36:31.91#ibcon#read 6, iclass 10, count 0 2006.217.07:36:31.91#ibcon#end of sib2, iclass 10, count 0 2006.217.07:36:31.91#ibcon#*after write, iclass 10, count 0 2006.217.07:36:31.91#ibcon#*before return 0, iclass 10, count 0 2006.217.07:36:31.91#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.217.07:36:31.91#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.217.07:36:31.91#ibcon#about to clear, iclass 10 cls_cnt 0 2006.217.07:36:31.91#ibcon#cleared, iclass 10 cls_cnt 0 2006.217.07:36:31.91$vc4f8/vblo=5,744.99 2006.217.07:36:31.91#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.217.07:36:31.91#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.217.07:36:31.91#ibcon#ireg 17 cls_cnt 0 2006.217.07:36:31.91#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.217.07:36:31.91#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.217.07:36:31.91#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.217.07:36:31.91#ibcon#enter wrdev, iclass 12, count 0 2006.217.07:36:31.91#ibcon#first serial, iclass 12, count 0 2006.217.07:36:31.91#ibcon#enter sib2, iclass 12, count 0 2006.217.07:36:31.91#ibcon#flushed, iclass 12, count 0 2006.217.07:36:31.91#ibcon#about to write, iclass 12, count 0 2006.217.07:36:31.91#ibcon#wrote, iclass 12, count 0 2006.217.07:36:31.91#ibcon#about to read 3, iclass 12, count 0 2006.217.07:36:31.93#ibcon#read 3, iclass 12, count 0 2006.217.07:36:31.93#ibcon#about to read 4, iclass 12, count 0 2006.217.07:36:31.93#ibcon#read 4, iclass 12, count 0 2006.217.07:36:31.93#ibcon#about to read 5, iclass 12, count 0 2006.217.07:36:31.93#ibcon#read 5, iclass 12, count 0 2006.217.07:36:31.93#ibcon#about to read 6, iclass 12, count 0 2006.217.07:36:31.93#ibcon#read 6, iclass 12, count 0 2006.217.07:36:31.93#ibcon#end of sib2, iclass 12, count 0 2006.217.07:36:31.93#ibcon#*mode == 0, iclass 12, count 0 2006.217.07:36:31.93#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.217.07:36:31.93#ibcon#[28=FRQ=05,744.99\r\n] 2006.217.07:36:31.93#ibcon#*before write, iclass 12, count 0 2006.217.07:36:31.93#ibcon#enter sib2, iclass 12, count 0 2006.217.07:36:31.93#ibcon#flushed, iclass 12, count 0 2006.217.07:36:31.93#ibcon#about to write, iclass 12, count 0 2006.217.07:36:31.93#ibcon#wrote, iclass 12, count 0 2006.217.07:36:31.93#ibcon#about to read 3, iclass 12, count 0 2006.217.07:36:31.97#ibcon#read 3, iclass 12, count 0 2006.217.07:36:31.97#ibcon#about to read 4, iclass 12, count 0 2006.217.07:36:31.97#ibcon#read 4, iclass 12, count 0 2006.217.07:36:31.97#ibcon#about to read 5, iclass 12, count 0 2006.217.07:36:31.97#ibcon#read 5, iclass 12, count 0 2006.217.07:36:31.97#ibcon#about to read 6, iclass 12, count 0 2006.217.07:36:31.97#ibcon#read 6, iclass 12, count 0 2006.217.07:36:31.97#ibcon#end of sib2, iclass 12, count 0 2006.217.07:36:31.97#ibcon#*after write, iclass 12, count 0 2006.217.07:36:31.97#ibcon#*before return 0, iclass 12, count 0 2006.217.07:36:31.97#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.217.07:36:31.97#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.217.07:36:31.97#ibcon#about to clear, iclass 12 cls_cnt 0 2006.217.07:36:31.97#ibcon#cleared, iclass 12 cls_cnt 0 2006.217.07:36:31.97$vc4f8/vb=5,4 2006.217.07:36:31.97#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.217.07:36:31.97#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.217.07:36:31.97#ibcon#ireg 11 cls_cnt 2 2006.217.07:36:31.97#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.217.07:36:32.03#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.217.07:36:32.03#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.217.07:36:32.03#ibcon#enter wrdev, iclass 14, count 2 2006.217.07:36:32.03#ibcon#first serial, iclass 14, count 2 2006.217.07:36:32.03#ibcon#enter sib2, iclass 14, count 2 2006.217.07:36:32.03#ibcon#flushed, iclass 14, count 2 2006.217.07:36:32.03#ibcon#about to write, iclass 14, count 2 2006.217.07:36:32.03#ibcon#wrote, iclass 14, count 2 2006.217.07:36:32.03#ibcon#about to read 3, iclass 14, count 2 2006.217.07:36:32.05#ibcon#read 3, iclass 14, count 2 2006.217.07:36:32.05#ibcon#about to read 4, iclass 14, count 2 2006.217.07:36:32.05#ibcon#read 4, iclass 14, count 2 2006.217.07:36:32.05#ibcon#about to read 5, iclass 14, count 2 2006.217.07:36:32.05#ibcon#read 5, iclass 14, count 2 2006.217.07:36:32.05#ibcon#about to read 6, iclass 14, count 2 2006.217.07:36:32.05#ibcon#read 6, iclass 14, count 2 2006.217.07:36:32.05#ibcon#end of sib2, iclass 14, count 2 2006.217.07:36:32.05#ibcon#*mode == 0, iclass 14, count 2 2006.217.07:36:32.05#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.217.07:36:32.05#ibcon#[27=AT05-04\r\n] 2006.217.07:36:32.05#ibcon#*before write, iclass 14, count 2 2006.217.07:36:32.05#ibcon#enter sib2, iclass 14, count 2 2006.217.07:36:32.05#ibcon#flushed, iclass 14, count 2 2006.217.07:36:32.05#ibcon#about to write, iclass 14, count 2 2006.217.07:36:32.05#ibcon#wrote, iclass 14, count 2 2006.217.07:36:32.05#ibcon#about to read 3, iclass 14, count 2 2006.217.07:36:32.08#ibcon#read 3, iclass 14, count 2 2006.217.07:36:32.08#ibcon#about to read 4, iclass 14, count 2 2006.217.07:36:32.08#ibcon#read 4, iclass 14, count 2 2006.217.07:36:32.08#ibcon#about to read 5, iclass 14, count 2 2006.217.07:36:32.08#ibcon#read 5, iclass 14, count 2 2006.217.07:36:32.08#ibcon#about to read 6, iclass 14, count 2 2006.217.07:36:32.08#ibcon#read 6, iclass 14, count 2 2006.217.07:36:32.08#ibcon#end of sib2, iclass 14, count 2 2006.217.07:36:32.08#ibcon#*after write, iclass 14, count 2 2006.217.07:36:32.08#ibcon#*before return 0, iclass 14, count 2 2006.217.07:36:32.08#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.217.07:36:32.08#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.217.07:36:32.08#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.217.07:36:32.08#ibcon#ireg 7 cls_cnt 0 2006.217.07:36:32.08#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.217.07:36:32.20#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.217.07:36:32.20#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.217.07:36:32.20#ibcon#enter wrdev, iclass 14, count 0 2006.217.07:36:32.20#ibcon#first serial, iclass 14, count 0 2006.217.07:36:32.20#ibcon#enter sib2, iclass 14, count 0 2006.217.07:36:32.20#ibcon#flushed, iclass 14, count 0 2006.217.07:36:32.20#ibcon#about to write, iclass 14, count 0 2006.217.07:36:32.20#ibcon#wrote, iclass 14, count 0 2006.217.07:36:32.20#ibcon#about to read 3, iclass 14, count 0 2006.217.07:36:32.22#ibcon#read 3, iclass 14, count 0 2006.217.07:36:32.22#ibcon#about to read 4, iclass 14, count 0 2006.217.07:36:32.22#ibcon#read 4, iclass 14, count 0 2006.217.07:36:32.22#ibcon#about to read 5, iclass 14, count 0 2006.217.07:36:32.22#ibcon#read 5, iclass 14, count 0 2006.217.07:36:32.22#ibcon#about to read 6, iclass 14, count 0 2006.217.07:36:32.22#ibcon#read 6, iclass 14, count 0 2006.217.07:36:32.22#ibcon#end of sib2, iclass 14, count 0 2006.217.07:36:32.22#ibcon#*mode == 0, iclass 14, count 0 2006.217.07:36:32.22#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.217.07:36:32.22#ibcon#[27=USB\r\n] 2006.217.07:36:32.22#ibcon#*before write, iclass 14, count 0 2006.217.07:36:32.22#ibcon#enter sib2, iclass 14, count 0 2006.217.07:36:32.22#ibcon#flushed, iclass 14, count 0 2006.217.07:36:32.22#ibcon#about to write, iclass 14, count 0 2006.217.07:36:32.22#ibcon#wrote, iclass 14, count 0 2006.217.07:36:32.22#ibcon#about to read 3, iclass 14, count 0 2006.217.07:36:32.25#ibcon#read 3, iclass 14, count 0 2006.217.07:36:32.25#ibcon#about to read 4, iclass 14, count 0 2006.217.07:36:32.25#ibcon#read 4, iclass 14, count 0 2006.217.07:36:32.25#ibcon#about to read 5, iclass 14, count 0 2006.217.07:36:32.25#ibcon#read 5, iclass 14, count 0 2006.217.07:36:32.25#ibcon#about to read 6, iclass 14, count 0 2006.217.07:36:32.25#ibcon#read 6, iclass 14, count 0 2006.217.07:36:32.25#ibcon#end of sib2, iclass 14, count 0 2006.217.07:36:32.25#ibcon#*after write, iclass 14, count 0 2006.217.07:36:32.25#ibcon#*before return 0, iclass 14, count 0 2006.217.07:36:32.25#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.217.07:36:32.25#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.217.07:36:32.25#ibcon#about to clear, iclass 14 cls_cnt 0 2006.217.07:36:32.25#ibcon#cleared, iclass 14 cls_cnt 0 2006.217.07:36:32.25$vc4f8/vblo=6,752.99 2006.217.07:36:32.25#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.217.07:36:32.25#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.217.07:36:32.25#ibcon#ireg 17 cls_cnt 0 2006.217.07:36:32.25#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.217.07:36:32.25#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.217.07:36:32.25#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.217.07:36:32.25#ibcon#enter wrdev, iclass 16, count 0 2006.217.07:36:32.25#ibcon#first serial, iclass 16, count 0 2006.217.07:36:32.25#ibcon#enter sib2, iclass 16, count 0 2006.217.07:36:32.25#ibcon#flushed, iclass 16, count 0 2006.217.07:36:32.25#ibcon#about to write, iclass 16, count 0 2006.217.07:36:32.25#ibcon#wrote, iclass 16, count 0 2006.217.07:36:32.25#ibcon#about to read 3, iclass 16, count 0 2006.217.07:36:32.27#ibcon#read 3, iclass 16, count 0 2006.217.07:36:32.27#ibcon#about to read 4, iclass 16, count 0 2006.217.07:36:32.27#ibcon#read 4, iclass 16, count 0 2006.217.07:36:32.27#ibcon#about to read 5, iclass 16, count 0 2006.217.07:36:32.27#ibcon#read 5, iclass 16, count 0 2006.217.07:36:32.27#ibcon#about to read 6, iclass 16, count 0 2006.217.07:36:32.27#ibcon#read 6, iclass 16, count 0 2006.217.07:36:32.27#ibcon#end of sib2, iclass 16, count 0 2006.217.07:36:32.27#ibcon#*mode == 0, iclass 16, count 0 2006.217.07:36:32.27#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.217.07:36:32.27#ibcon#[28=FRQ=06,752.99\r\n] 2006.217.07:36:32.27#ibcon#*before write, iclass 16, count 0 2006.217.07:36:32.27#ibcon#enter sib2, iclass 16, count 0 2006.217.07:36:32.27#ibcon#flushed, iclass 16, count 0 2006.217.07:36:32.27#ibcon#about to write, iclass 16, count 0 2006.217.07:36:32.27#ibcon#wrote, iclass 16, count 0 2006.217.07:36:32.27#ibcon#about to read 3, iclass 16, count 0 2006.217.07:36:32.31#ibcon#read 3, iclass 16, count 0 2006.217.07:36:32.31#ibcon#about to read 4, iclass 16, count 0 2006.217.07:36:32.31#ibcon#read 4, iclass 16, count 0 2006.217.07:36:32.31#ibcon#about to read 5, iclass 16, count 0 2006.217.07:36:32.31#ibcon#read 5, iclass 16, count 0 2006.217.07:36:32.31#ibcon#about to read 6, iclass 16, count 0 2006.217.07:36:32.31#ibcon#read 6, iclass 16, count 0 2006.217.07:36:32.31#ibcon#end of sib2, iclass 16, count 0 2006.217.07:36:32.31#ibcon#*after write, iclass 16, count 0 2006.217.07:36:32.31#ibcon#*before return 0, iclass 16, count 0 2006.217.07:36:32.31#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.217.07:36:32.31#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.217.07:36:32.31#ibcon#about to clear, iclass 16 cls_cnt 0 2006.217.07:36:32.31#ibcon#cleared, iclass 16 cls_cnt 0 2006.217.07:36:32.31$vc4f8/vb=6,4 2006.217.07:36:32.31#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.217.07:36:32.31#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.217.07:36:32.31#ibcon#ireg 11 cls_cnt 2 2006.217.07:36:32.31#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.217.07:36:32.37#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.217.07:36:32.37#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.217.07:36:32.37#ibcon#enter wrdev, iclass 18, count 2 2006.217.07:36:32.37#ibcon#first serial, iclass 18, count 2 2006.217.07:36:32.37#ibcon#enter sib2, iclass 18, count 2 2006.217.07:36:32.37#ibcon#flushed, iclass 18, count 2 2006.217.07:36:32.37#ibcon#about to write, iclass 18, count 2 2006.217.07:36:32.37#ibcon#wrote, iclass 18, count 2 2006.217.07:36:32.37#ibcon#about to read 3, iclass 18, count 2 2006.217.07:36:32.39#ibcon#read 3, iclass 18, count 2 2006.217.07:36:32.39#ibcon#about to read 4, iclass 18, count 2 2006.217.07:36:32.39#ibcon#read 4, iclass 18, count 2 2006.217.07:36:32.39#ibcon#about to read 5, iclass 18, count 2 2006.217.07:36:32.39#ibcon#read 5, iclass 18, count 2 2006.217.07:36:32.39#ibcon#about to read 6, iclass 18, count 2 2006.217.07:36:32.39#ibcon#read 6, iclass 18, count 2 2006.217.07:36:32.39#ibcon#end of sib2, iclass 18, count 2 2006.217.07:36:32.39#ibcon#*mode == 0, iclass 18, count 2 2006.217.07:36:32.39#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.217.07:36:32.39#ibcon#[27=AT06-04\r\n] 2006.217.07:36:32.39#ibcon#*before write, iclass 18, count 2 2006.217.07:36:32.39#ibcon#enter sib2, iclass 18, count 2 2006.217.07:36:32.39#ibcon#flushed, iclass 18, count 2 2006.217.07:36:32.39#ibcon#about to write, iclass 18, count 2 2006.217.07:36:32.39#ibcon#wrote, iclass 18, count 2 2006.217.07:36:32.39#ibcon#about to read 3, iclass 18, count 2 2006.217.07:36:32.42#ibcon#read 3, iclass 18, count 2 2006.217.07:36:32.42#ibcon#about to read 4, iclass 18, count 2 2006.217.07:36:32.42#ibcon#read 4, iclass 18, count 2 2006.217.07:36:32.42#ibcon#about to read 5, iclass 18, count 2 2006.217.07:36:32.42#ibcon#read 5, iclass 18, count 2 2006.217.07:36:32.42#ibcon#about to read 6, iclass 18, count 2 2006.217.07:36:32.42#ibcon#read 6, iclass 18, count 2 2006.217.07:36:32.42#ibcon#end of sib2, iclass 18, count 2 2006.217.07:36:32.42#ibcon#*after write, iclass 18, count 2 2006.217.07:36:32.42#ibcon#*before return 0, iclass 18, count 2 2006.217.07:36:32.42#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.217.07:36:32.42#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.217.07:36:32.42#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.217.07:36:32.42#ibcon#ireg 7 cls_cnt 0 2006.217.07:36:32.42#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.217.07:36:32.54#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.217.07:36:32.54#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.217.07:36:32.54#ibcon#enter wrdev, iclass 18, count 0 2006.217.07:36:32.54#ibcon#first serial, iclass 18, count 0 2006.217.07:36:32.54#ibcon#enter sib2, iclass 18, count 0 2006.217.07:36:32.54#ibcon#flushed, iclass 18, count 0 2006.217.07:36:32.54#ibcon#about to write, iclass 18, count 0 2006.217.07:36:32.54#ibcon#wrote, iclass 18, count 0 2006.217.07:36:32.54#ibcon#about to read 3, iclass 18, count 0 2006.217.07:36:32.56#ibcon#read 3, iclass 18, count 0 2006.217.07:36:32.56#ibcon#about to read 4, iclass 18, count 0 2006.217.07:36:32.56#ibcon#read 4, iclass 18, count 0 2006.217.07:36:32.56#ibcon#about to read 5, iclass 18, count 0 2006.217.07:36:32.56#ibcon#read 5, iclass 18, count 0 2006.217.07:36:32.56#ibcon#about to read 6, iclass 18, count 0 2006.217.07:36:32.56#ibcon#read 6, iclass 18, count 0 2006.217.07:36:32.56#ibcon#end of sib2, iclass 18, count 0 2006.217.07:36:32.56#ibcon#*mode == 0, iclass 18, count 0 2006.217.07:36:32.56#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.217.07:36:32.56#ibcon#[27=USB\r\n] 2006.217.07:36:32.56#ibcon#*before write, iclass 18, count 0 2006.217.07:36:32.56#ibcon#enter sib2, iclass 18, count 0 2006.217.07:36:32.56#ibcon#flushed, iclass 18, count 0 2006.217.07:36:32.56#ibcon#about to write, iclass 18, count 0 2006.217.07:36:32.56#ibcon#wrote, iclass 18, count 0 2006.217.07:36:32.56#ibcon#about to read 3, iclass 18, count 0 2006.217.07:36:32.59#ibcon#read 3, iclass 18, count 0 2006.217.07:36:32.59#ibcon#about to read 4, iclass 18, count 0 2006.217.07:36:32.59#ibcon#read 4, iclass 18, count 0 2006.217.07:36:32.59#ibcon#about to read 5, iclass 18, count 0 2006.217.07:36:32.59#ibcon#read 5, iclass 18, count 0 2006.217.07:36:32.59#ibcon#about to read 6, iclass 18, count 0 2006.217.07:36:32.59#ibcon#read 6, iclass 18, count 0 2006.217.07:36:32.59#ibcon#end of sib2, iclass 18, count 0 2006.217.07:36:32.59#ibcon#*after write, iclass 18, count 0 2006.217.07:36:32.59#ibcon#*before return 0, iclass 18, count 0 2006.217.07:36:32.59#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.217.07:36:32.59#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.217.07:36:32.59#ibcon#about to clear, iclass 18 cls_cnt 0 2006.217.07:36:32.59#ibcon#cleared, iclass 18 cls_cnt 0 2006.217.07:36:32.59$vc4f8/vabw=wide 2006.217.07:36:32.59#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.217.07:36:32.59#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.217.07:36:32.59#ibcon#ireg 8 cls_cnt 0 2006.217.07:36:32.59#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.217.07:36:32.59#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.217.07:36:32.59#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.217.07:36:32.59#ibcon#enter wrdev, iclass 20, count 0 2006.217.07:36:32.59#ibcon#first serial, iclass 20, count 0 2006.217.07:36:32.59#ibcon#enter sib2, iclass 20, count 0 2006.217.07:36:32.59#ibcon#flushed, iclass 20, count 0 2006.217.07:36:32.59#ibcon#about to write, iclass 20, count 0 2006.217.07:36:32.59#ibcon#wrote, iclass 20, count 0 2006.217.07:36:32.59#ibcon#about to read 3, iclass 20, count 0 2006.217.07:36:32.61#ibcon#read 3, iclass 20, count 0 2006.217.07:36:32.61#ibcon#about to read 4, iclass 20, count 0 2006.217.07:36:32.61#ibcon#read 4, iclass 20, count 0 2006.217.07:36:32.61#ibcon#about to read 5, iclass 20, count 0 2006.217.07:36:32.61#ibcon#read 5, iclass 20, count 0 2006.217.07:36:32.61#ibcon#about to read 6, iclass 20, count 0 2006.217.07:36:32.61#ibcon#read 6, iclass 20, count 0 2006.217.07:36:32.61#ibcon#end of sib2, iclass 20, count 0 2006.217.07:36:32.61#ibcon#*mode == 0, iclass 20, count 0 2006.217.07:36:32.61#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.217.07:36:32.61#ibcon#[25=BW32\r\n] 2006.217.07:36:32.61#ibcon#*before write, iclass 20, count 0 2006.217.07:36:32.61#ibcon#enter sib2, iclass 20, count 0 2006.217.07:36:32.61#ibcon#flushed, iclass 20, count 0 2006.217.07:36:32.61#ibcon#about to write, iclass 20, count 0 2006.217.07:36:32.61#ibcon#wrote, iclass 20, count 0 2006.217.07:36:32.61#ibcon#about to read 3, iclass 20, count 0 2006.217.07:36:32.64#ibcon#read 3, iclass 20, count 0 2006.217.07:36:32.64#ibcon#about to read 4, iclass 20, count 0 2006.217.07:36:32.64#ibcon#read 4, iclass 20, count 0 2006.217.07:36:32.64#ibcon#about to read 5, iclass 20, count 0 2006.217.07:36:32.64#ibcon#read 5, iclass 20, count 0 2006.217.07:36:32.64#ibcon#about to read 6, iclass 20, count 0 2006.217.07:36:32.64#ibcon#read 6, iclass 20, count 0 2006.217.07:36:32.64#ibcon#end of sib2, iclass 20, count 0 2006.217.07:36:32.64#ibcon#*after write, iclass 20, count 0 2006.217.07:36:32.64#ibcon#*before return 0, iclass 20, count 0 2006.217.07:36:32.64#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.217.07:36:32.64#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.217.07:36:32.64#ibcon#about to clear, iclass 20 cls_cnt 0 2006.217.07:36:32.64#ibcon#cleared, iclass 20 cls_cnt 0 2006.217.07:36:32.64$vc4f8/vbbw=wide 2006.217.07:36:32.64#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.217.07:36:32.64#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.217.07:36:32.64#ibcon#ireg 8 cls_cnt 0 2006.217.07:36:32.64#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.217.07:36:32.71#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.217.07:36:32.71#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.217.07:36:32.71#ibcon#enter wrdev, iclass 22, count 0 2006.217.07:36:32.71#ibcon#first serial, iclass 22, count 0 2006.217.07:36:32.71#ibcon#enter sib2, iclass 22, count 0 2006.217.07:36:32.71#ibcon#flushed, iclass 22, count 0 2006.217.07:36:32.71#ibcon#about to write, iclass 22, count 0 2006.217.07:36:32.71#ibcon#wrote, iclass 22, count 0 2006.217.07:36:32.71#ibcon#about to read 3, iclass 22, count 0 2006.217.07:36:32.73#ibcon#read 3, iclass 22, count 0 2006.217.07:36:32.73#ibcon#about to read 4, iclass 22, count 0 2006.217.07:36:32.73#ibcon#read 4, iclass 22, count 0 2006.217.07:36:32.73#ibcon#about to read 5, iclass 22, count 0 2006.217.07:36:32.73#ibcon#read 5, iclass 22, count 0 2006.217.07:36:32.73#ibcon#about to read 6, iclass 22, count 0 2006.217.07:36:32.73#ibcon#read 6, iclass 22, count 0 2006.217.07:36:32.73#ibcon#end of sib2, iclass 22, count 0 2006.217.07:36:32.73#ibcon#*mode == 0, iclass 22, count 0 2006.217.07:36:32.73#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.217.07:36:32.73#ibcon#[27=BW32\r\n] 2006.217.07:36:32.73#ibcon#*before write, iclass 22, count 0 2006.217.07:36:32.73#ibcon#enter sib2, iclass 22, count 0 2006.217.07:36:32.73#ibcon#flushed, iclass 22, count 0 2006.217.07:36:32.73#ibcon#about to write, iclass 22, count 0 2006.217.07:36:32.73#ibcon#wrote, iclass 22, count 0 2006.217.07:36:32.73#ibcon#about to read 3, iclass 22, count 0 2006.217.07:36:32.76#ibcon#read 3, iclass 22, count 0 2006.217.07:36:32.76#ibcon#about to read 4, iclass 22, count 0 2006.217.07:36:32.76#ibcon#read 4, iclass 22, count 0 2006.217.07:36:32.76#ibcon#about to read 5, iclass 22, count 0 2006.217.07:36:32.76#ibcon#read 5, iclass 22, count 0 2006.217.07:36:32.76#ibcon#about to read 6, iclass 22, count 0 2006.217.07:36:32.76#ibcon#read 6, iclass 22, count 0 2006.217.07:36:32.76#ibcon#end of sib2, iclass 22, count 0 2006.217.07:36:32.76#ibcon#*after write, iclass 22, count 0 2006.217.07:36:32.76#ibcon#*before return 0, iclass 22, count 0 2006.217.07:36:32.76#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.217.07:36:32.76#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.217.07:36:32.76#ibcon#about to clear, iclass 22 cls_cnt 0 2006.217.07:36:32.76#ibcon#cleared, iclass 22 cls_cnt 0 2006.217.07:36:32.76$4f8m12a/ifd4f 2006.217.07:36:32.76$ifd4f/lo= 2006.217.07:36:32.76$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.217.07:36:32.76$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.217.07:36:32.76$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.217.07:36:32.76$ifd4f/patch= 2006.217.07:36:32.76$ifd4f/patch=lo1,a1,a2,a3,a4 2006.217.07:36:32.76$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.217.07:36:32.76$ifd4f/patch=lo3,a5,a6,a7,a8 2006.217.07:36:32.76$4f8m12a/"form=m,16.000,1:2 2006.217.07:36:32.76$4f8m12a/"tpicd 2006.217.07:36:32.76$4f8m12a/echo=off 2006.217.07:36:32.76$4f8m12a/xlog=off 2006.217.07:36:32.76:!2006.217.07:37:00 2006.217.07:36:42.14#trakl#Source acquired 2006.217.07:36:42.14#flagr#flagr/antenna,acquired 2006.217.07:37:00.00:preob 2006.217.07:37:01.14/onsource/TRACKING 2006.217.07:37:01.14:!2006.217.07:37:10 2006.217.07:37:10.00:data_valid=on 2006.217.07:37:10.00:midob 2006.217.07:37:10.14/onsource/TRACKING 2006.217.07:37:10.14/wx/31.30,1008.6,61 2006.217.07:37:10.22/cable/+6.3867E-03 2006.217.07:37:11.31/va/01,05,usb,yes,33,35 2006.217.07:37:11.31/va/02,04,usb,yes,31,32 2006.217.07:37:11.31/va/03,04,usb,yes,29,29 2006.217.07:37:11.31/va/04,04,usb,yes,33,35 2006.217.07:37:11.31/va/05,07,usb,yes,35,37 2006.217.07:37:11.31/va/06,06,usb,yes,34,34 2006.217.07:37:11.31/va/07,06,usb,yes,34,34 2006.217.07:37:11.31/va/08,07,usb,yes,33,32 2006.217.07:37:11.54/valo/01,532.99,yes,locked 2006.217.07:37:11.54/valo/02,572.99,yes,locked 2006.217.07:37:11.54/valo/03,672.99,yes,locked 2006.217.07:37:11.54/valo/04,832.99,yes,locked 2006.217.07:37:11.54/valo/05,652.99,yes,locked 2006.217.07:37:11.54/valo/06,772.99,yes,locked 2006.217.07:37:11.54/valo/07,832.99,yes,locked 2006.217.07:37:11.54/valo/08,852.99,yes,locked 2006.217.07:37:12.63/vb/01,04,usb,yes,31,30 2006.217.07:37:12.63/vb/02,04,usb,yes,33,34 2006.217.07:37:12.63/vb/03,04,usb,yes,29,33 2006.217.07:37:12.63/vb/04,04,usb,yes,30,30 2006.217.07:37:12.63/vb/05,04,usb,yes,29,33 2006.217.07:37:12.63/vb/06,04,usb,yes,29,32 2006.217.07:37:12.63/vb/07,04,usb,yes,32,32 2006.217.07:37:12.63/vb/08,04,usb,yes,29,33 2006.217.07:37:12.86/vblo/01,632.99,yes,locked 2006.217.07:37:12.86/vblo/02,640.99,yes,locked 2006.217.07:37:12.86/vblo/03,656.99,yes,locked 2006.217.07:37:12.86/vblo/04,712.99,yes,locked 2006.217.07:37:12.86/vblo/05,744.99,yes,locked 2006.217.07:37:12.86/vblo/06,752.99,yes,locked 2006.217.07:37:12.86/vblo/07,734.99,yes,locked 2006.217.07:37:12.86/vblo/08,744.99,yes,locked 2006.217.07:37:13.01/vabw/8 2006.217.07:37:13.16/vbbw/8 2006.217.07:37:13.25/xfe/off,on,15.0 2006.217.07:37:13.64/ifatt/23,28,28,28 2006.217.07:37:14.08/fmout-gps/S +4.37E-07 2006.217.07:37:14.15:!2006.217.07:38:10 2006.217.07:38:10.00:data_valid=off 2006.217.07:38:10.00:postob 2006.217.07:38:10.18/cable/+6.3850E-03 2006.217.07:38:10.21/wx/31.30,1008.6,62 2006.217.07:38:11.08/fmout-gps/S +4.36E-07 2006.217.07:38:11.08:scan_name=217-0739,k06217,60 2006.217.07:38:11.08:source=1357+769,135755.37,764321.1,2000.0,neutral 2006.217.07:38:11.14#flagr#flagr/antenna,new-source 2006.217.07:38:12.14:checkk5 2006.217.07:38:12.51/chk_autoobs//k5ts1/ autoobs is running! 2006.217.07:38:12.88/chk_autoobs//k5ts2/ autoobs is running! 2006.217.07:38:13.26/chk_autoobs//k5ts3/ autoobs is running! 2006.217.07:38:13.64/chk_autoobs//k5ts4/ autoobs is running! 2006.217.07:38:14.00/chk_obsdata//k5ts1/T2170737??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:38:14.37/chk_obsdata//k5ts2/T2170737??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:38:14.73/chk_obsdata//k5ts3/T2170737??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:38:15.11/chk_obsdata//k5ts4/T2170737??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:38:15.80/k5log//k5ts1_log_newline 2006.217.07:38:16.49/k5log//k5ts2_log_newline 2006.217.07:38:17.17/k5log//k5ts3_log_newline 2006.217.07:38:17.86/k5log//k5ts4_log_newline 2006.217.07:38:17.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.217.07:38:17.88:4f8m12a=1 2006.217.07:38:17.88$4f8m12a/echo=on 2006.217.07:38:17.88$4f8m12a/pcalon 2006.217.07:38:17.88$pcalon/"no phase cal control is implemented here 2006.217.07:38:17.88$4f8m12a/"tpicd=stop 2006.217.07:38:17.88$4f8m12a/vc4f8 2006.217.07:38:17.88$vc4f8/valo=1,532.99 2006.217.07:38:17.89#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.217.07:38:17.89#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.217.07:38:17.89#ibcon#ireg 17 cls_cnt 0 2006.217.07:38:17.89#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.217.07:38:17.89#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.217.07:38:17.89#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.217.07:38:17.89#ibcon#enter wrdev, iclass 29, count 0 2006.217.07:38:17.89#ibcon#first serial, iclass 29, count 0 2006.217.07:38:17.89#ibcon#enter sib2, iclass 29, count 0 2006.217.07:38:17.89#ibcon#flushed, iclass 29, count 0 2006.217.07:38:17.89#ibcon#about to write, iclass 29, count 0 2006.217.07:38:17.89#ibcon#wrote, iclass 29, count 0 2006.217.07:38:17.89#ibcon#about to read 3, iclass 29, count 0 2006.217.07:38:17.93#ibcon#read 3, iclass 29, count 0 2006.217.07:38:17.93#ibcon#about to read 4, iclass 29, count 0 2006.217.07:38:17.93#ibcon#read 4, iclass 29, count 0 2006.217.07:38:17.93#ibcon#about to read 5, iclass 29, count 0 2006.217.07:38:17.93#ibcon#read 5, iclass 29, count 0 2006.217.07:38:17.93#ibcon#about to read 6, iclass 29, count 0 2006.217.07:38:17.93#ibcon#read 6, iclass 29, count 0 2006.217.07:38:17.93#ibcon#end of sib2, iclass 29, count 0 2006.217.07:38:17.93#ibcon#*mode == 0, iclass 29, count 0 2006.217.07:38:17.93#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.217.07:38:17.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.217.07:38:17.93#ibcon#*before write, iclass 29, count 0 2006.217.07:38:17.93#ibcon#enter sib2, iclass 29, count 0 2006.217.07:38:17.93#ibcon#flushed, iclass 29, count 0 2006.217.07:38:17.93#ibcon#about to write, iclass 29, count 0 2006.217.07:38:17.93#ibcon#wrote, iclass 29, count 0 2006.217.07:38:17.93#ibcon#about to read 3, iclass 29, count 0 2006.217.07:38:17.98#ibcon#read 3, iclass 29, count 0 2006.217.07:38:17.98#ibcon#about to read 4, iclass 29, count 0 2006.217.07:38:17.98#ibcon#read 4, iclass 29, count 0 2006.217.07:38:17.98#ibcon#about to read 5, iclass 29, count 0 2006.217.07:38:17.98#ibcon#read 5, iclass 29, count 0 2006.217.07:38:17.98#ibcon#about to read 6, iclass 29, count 0 2006.217.07:38:17.98#ibcon#read 6, iclass 29, count 0 2006.217.07:38:17.98#ibcon#end of sib2, iclass 29, count 0 2006.217.07:38:17.98#ibcon#*after write, iclass 29, count 0 2006.217.07:38:17.98#ibcon#*before return 0, iclass 29, count 0 2006.217.07:38:17.98#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.217.07:38:17.98#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.217.07:38:17.98#ibcon#about to clear, iclass 29 cls_cnt 0 2006.217.07:38:17.98#ibcon#cleared, iclass 29 cls_cnt 0 2006.217.07:38:17.98$vc4f8/va=1,5 2006.217.07:38:17.98#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.217.07:38:17.98#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.217.07:38:17.98#ibcon#ireg 11 cls_cnt 2 2006.217.07:38:17.98#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.217.07:38:17.98#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.217.07:38:17.98#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.217.07:38:17.98#ibcon#enter wrdev, iclass 31, count 2 2006.217.07:38:17.98#ibcon#first serial, iclass 31, count 2 2006.217.07:38:17.98#ibcon#enter sib2, iclass 31, count 2 2006.217.07:38:17.98#ibcon#flushed, iclass 31, count 2 2006.217.07:38:17.98#ibcon#about to write, iclass 31, count 2 2006.217.07:38:17.98#ibcon#wrote, iclass 31, count 2 2006.217.07:38:17.98#ibcon#about to read 3, iclass 31, count 2 2006.217.07:38:18.00#ibcon#read 3, iclass 31, count 2 2006.217.07:38:18.00#ibcon#about to read 4, iclass 31, count 2 2006.217.07:38:18.00#ibcon#read 4, iclass 31, count 2 2006.217.07:38:18.00#ibcon#about to read 5, iclass 31, count 2 2006.217.07:38:18.00#ibcon#read 5, iclass 31, count 2 2006.217.07:38:18.00#ibcon#about to read 6, iclass 31, count 2 2006.217.07:38:18.00#ibcon#read 6, iclass 31, count 2 2006.217.07:38:18.00#ibcon#end of sib2, iclass 31, count 2 2006.217.07:38:18.00#ibcon#*mode == 0, iclass 31, count 2 2006.217.07:38:18.00#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.217.07:38:18.00#ibcon#[25=AT01-05\r\n] 2006.217.07:38:18.00#ibcon#*before write, iclass 31, count 2 2006.217.07:38:18.00#ibcon#enter sib2, iclass 31, count 2 2006.217.07:38:18.00#ibcon#flushed, iclass 31, count 2 2006.217.07:38:18.00#ibcon#about to write, iclass 31, count 2 2006.217.07:38:18.00#ibcon#wrote, iclass 31, count 2 2006.217.07:38:18.00#ibcon#about to read 3, iclass 31, count 2 2006.217.07:38:18.03#ibcon#read 3, iclass 31, count 2 2006.217.07:38:18.03#ibcon#about to read 4, iclass 31, count 2 2006.217.07:38:18.03#ibcon#read 4, iclass 31, count 2 2006.217.07:38:18.03#ibcon#about to read 5, iclass 31, count 2 2006.217.07:38:18.03#ibcon#read 5, iclass 31, count 2 2006.217.07:38:18.03#ibcon#about to read 6, iclass 31, count 2 2006.217.07:38:18.03#ibcon#read 6, iclass 31, count 2 2006.217.07:38:18.03#ibcon#end of sib2, iclass 31, count 2 2006.217.07:38:18.03#ibcon#*after write, iclass 31, count 2 2006.217.07:38:18.03#ibcon#*before return 0, iclass 31, count 2 2006.217.07:38:18.03#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.217.07:38:18.03#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.217.07:38:18.03#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.217.07:38:18.03#ibcon#ireg 7 cls_cnt 0 2006.217.07:38:18.03#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.217.07:38:18.15#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.217.07:38:18.15#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.217.07:38:18.15#ibcon#enter wrdev, iclass 31, count 0 2006.217.07:38:18.15#ibcon#first serial, iclass 31, count 0 2006.217.07:38:18.15#ibcon#enter sib2, iclass 31, count 0 2006.217.07:38:18.15#ibcon#flushed, iclass 31, count 0 2006.217.07:38:18.15#ibcon#about to write, iclass 31, count 0 2006.217.07:38:18.15#ibcon#wrote, iclass 31, count 0 2006.217.07:38:18.15#ibcon#about to read 3, iclass 31, count 0 2006.217.07:38:18.17#ibcon#read 3, iclass 31, count 0 2006.217.07:38:18.17#ibcon#about to read 4, iclass 31, count 0 2006.217.07:38:18.17#ibcon#read 4, iclass 31, count 0 2006.217.07:38:18.17#ibcon#about to read 5, iclass 31, count 0 2006.217.07:38:18.17#ibcon#read 5, iclass 31, count 0 2006.217.07:38:18.17#ibcon#about to read 6, iclass 31, count 0 2006.217.07:38:18.17#ibcon#read 6, iclass 31, count 0 2006.217.07:38:18.17#ibcon#end of sib2, iclass 31, count 0 2006.217.07:38:18.17#ibcon#*mode == 0, iclass 31, count 0 2006.217.07:38:18.17#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.217.07:38:18.17#ibcon#[25=USB\r\n] 2006.217.07:38:18.17#ibcon#*before write, iclass 31, count 0 2006.217.07:38:18.17#ibcon#enter sib2, iclass 31, count 0 2006.217.07:38:18.17#ibcon#flushed, iclass 31, count 0 2006.217.07:38:18.17#ibcon#about to write, iclass 31, count 0 2006.217.07:38:18.17#ibcon#wrote, iclass 31, count 0 2006.217.07:38:18.17#ibcon#about to read 3, iclass 31, count 0 2006.217.07:38:18.20#ibcon#read 3, iclass 31, count 0 2006.217.07:38:18.20#ibcon#about to read 4, iclass 31, count 0 2006.217.07:38:18.20#ibcon#read 4, iclass 31, count 0 2006.217.07:38:18.20#ibcon#about to read 5, iclass 31, count 0 2006.217.07:38:18.20#ibcon#read 5, iclass 31, count 0 2006.217.07:38:18.20#ibcon#about to read 6, iclass 31, count 0 2006.217.07:38:18.20#ibcon#read 6, iclass 31, count 0 2006.217.07:38:18.20#ibcon#end of sib2, iclass 31, count 0 2006.217.07:38:18.20#ibcon#*after write, iclass 31, count 0 2006.217.07:38:18.20#ibcon#*before return 0, iclass 31, count 0 2006.217.07:38:18.20#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.217.07:38:18.20#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.217.07:38:18.20#ibcon#about to clear, iclass 31 cls_cnt 0 2006.217.07:38:18.20#ibcon#cleared, iclass 31 cls_cnt 0 2006.217.07:38:18.20$vc4f8/valo=2,572.99 2006.217.07:38:18.20#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.217.07:38:18.20#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.217.07:38:18.20#ibcon#ireg 17 cls_cnt 0 2006.217.07:38:18.20#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.217.07:38:18.20#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.217.07:38:18.20#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.217.07:38:18.20#ibcon#enter wrdev, iclass 33, count 0 2006.217.07:38:18.20#ibcon#first serial, iclass 33, count 0 2006.217.07:38:18.20#ibcon#enter sib2, iclass 33, count 0 2006.217.07:38:18.20#ibcon#flushed, iclass 33, count 0 2006.217.07:38:18.20#ibcon#about to write, iclass 33, count 0 2006.217.07:38:18.20#ibcon#wrote, iclass 33, count 0 2006.217.07:38:18.20#ibcon#about to read 3, iclass 33, count 0 2006.217.07:38:18.22#ibcon#read 3, iclass 33, count 0 2006.217.07:38:18.22#ibcon#about to read 4, iclass 33, count 0 2006.217.07:38:18.22#ibcon#read 4, iclass 33, count 0 2006.217.07:38:18.22#ibcon#about to read 5, iclass 33, count 0 2006.217.07:38:18.22#ibcon#read 5, iclass 33, count 0 2006.217.07:38:18.22#ibcon#about to read 6, iclass 33, count 0 2006.217.07:38:18.22#ibcon#read 6, iclass 33, count 0 2006.217.07:38:18.22#ibcon#end of sib2, iclass 33, count 0 2006.217.07:38:18.22#ibcon#*mode == 0, iclass 33, count 0 2006.217.07:38:18.22#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.217.07:38:18.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.217.07:38:18.22#ibcon#*before write, iclass 33, count 0 2006.217.07:38:18.22#ibcon#enter sib2, iclass 33, count 0 2006.217.07:38:18.22#ibcon#flushed, iclass 33, count 0 2006.217.07:38:18.22#ibcon#about to write, iclass 33, count 0 2006.217.07:38:18.22#ibcon#wrote, iclass 33, count 0 2006.217.07:38:18.22#ibcon#about to read 3, iclass 33, count 0 2006.217.07:38:18.27#ibcon#read 3, iclass 33, count 0 2006.217.07:38:18.27#ibcon#about to read 4, iclass 33, count 0 2006.217.07:38:18.27#ibcon#read 4, iclass 33, count 0 2006.217.07:38:18.27#ibcon#about to read 5, iclass 33, count 0 2006.217.07:38:18.27#ibcon#read 5, iclass 33, count 0 2006.217.07:38:18.27#ibcon#about to read 6, iclass 33, count 0 2006.217.07:38:18.27#ibcon#read 6, iclass 33, count 0 2006.217.07:38:18.27#ibcon#end of sib2, iclass 33, count 0 2006.217.07:38:18.27#ibcon#*after write, iclass 33, count 0 2006.217.07:38:18.27#ibcon#*before return 0, iclass 33, count 0 2006.217.07:38:18.27#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.217.07:38:18.27#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.217.07:38:18.27#ibcon#about to clear, iclass 33 cls_cnt 0 2006.217.07:38:18.27#ibcon#cleared, iclass 33 cls_cnt 0 2006.217.07:38:18.27$vc4f8/va=2,4 2006.217.07:38:18.27#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.217.07:38:18.27#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.217.07:38:18.27#ibcon#ireg 11 cls_cnt 2 2006.217.07:38:18.27#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.217.07:38:18.32#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.217.07:38:18.32#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.217.07:38:18.32#ibcon#enter wrdev, iclass 35, count 2 2006.217.07:38:18.32#ibcon#first serial, iclass 35, count 2 2006.217.07:38:18.32#ibcon#enter sib2, iclass 35, count 2 2006.217.07:38:18.32#ibcon#flushed, iclass 35, count 2 2006.217.07:38:18.32#ibcon#about to write, iclass 35, count 2 2006.217.07:38:18.32#ibcon#wrote, iclass 35, count 2 2006.217.07:38:18.32#ibcon#about to read 3, iclass 35, count 2 2006.217.07:38:18.34#ibcon#read 3, iclass 35, count 2 2006.217.07:38:18.34#ibcon#about to read 4, iclass 35, count 2 2006.217.07:38:18.34#ibcon#read 4, iclass 35, count 2 2006.217.07:38:18.34#ibcon#about to read 5, iclass 35, count 2 2006.217.07:38:18.34#ibcon#read 5, iclass 35, count 2 2006.217.07:38:18.34#ibcon#about to read 6, iclass 35, count 2 2006.217.07:38:18.34#ibcon#read 6, iclass 35, count 2 2006.217.07:38:18.34#ibcon#end of sib2, iclass 35, count 2 2006.217.07:38:18.34#ibcon#*mode == 0, iclass 35, count 2 2006.217.07:38:18.34#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.217.07:38:18.34#ibcon#[25=AT02-04\r\n] 2006.217.07:38:18.34#ibcon#*before write, iclass 35, count 2 2006.217.07:38:18.34#ibcon#enter sib2, iclass 35, count 2 2006.217.07:38:18.34#ibcon#flushed, iclass 35, count 2 2006.217.07:38:18.34#ibcon#about to write, iclass 35, count 2 2006.217.07:38:18.34#ibcon#wrote, iclass 35, count 2 2006.217.07:38:18.34#ibcon#about to read 3, iclass 35, count 2 2006.217.07:38:18.37#ibcon#read 3, iclass 35, count 2 2006.217.07:38:18.37#ibcon#about to read 4, iclass 35, count 2 2006.217.07:38:18.37#ibcon#read 4, iclass 35, count 2 2006.217.07:38:18.37#ibcon#about to read 5, iclass 35, count 2 2006.217.07:38:18.37#ibcon#read 5, iclass 35, count 2 2006.217.07:38:18.37#ibcon#about to read 6, iclass 35, count 2 2006.217.07:38:18.37#ibcon#read 6, iclass 35, count 2 2006.217.07:38:18.37#ibcon#end of sib2, iclass 35, count 2 2006.217.07:38:18.37#ibcon#*after write, iclass 35, count 2 2006.217.07:38:18.37#ibcon#*before return 0, iclass 35, count 2 2006.217.07:38:18.37#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.217.07:38:18.37#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.217.07:38:18.37#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.217.07:38:18.37#ibcon#ireg 7 cls_cnt 0 2006.217.07:38:18.37#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.217.07:38:18.49#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.217.07:38:18.49#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.217.07:38:18.49#ibcon#enter wrdev, iclass 35, count 0 2006.217.07:38:18.49#ibcon#first serial, iclass 35, count 0 2006.217.07:38:18.49#ibcon#enter sib2, iclass 35, count 0 2006.217.07:38:18.49#ibcon#flushed, iclass 35, count 0 2006.217.07:38:18.49#ibcon#about to write, iclass 35, count 0 2006.217.07:38:18.49#ibcon#wrote, iclass 35, count 0 2006.217.07:38:18.49#ibcon#about to read 3, iclass 35, count 0 2006.217.07:38:18.51#ibcon#read 3, iclass 35, count 0 2006.217.07:38:18.51#ibcon#about to read 4, iclass 35, count 0 2006.217.07:38:18.51#ibcon#read 4, iclass 35, count 0 2006.217.07:38:18.51#ibcon#about to read 5, iclass 35, count 0 2006.217.07:38:18.51#ibcon#read 5, iclass 35, count 0 2006.217.07:38:18.51#ibcon#about to read 6, iclass 35, count 0 2006.217.07:38:18.51#ibcon#read 6, iclass 35, count 0 2006.217.07:38:18.51#ibcon#end of sib2, iclass 35, count 0 2006.217.07:38:18.51#ibcon#*mode == 0, iclass 35, count 0 2006.217.07:38:18.51#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.217.07:38:18.51#ibcon#[25=USB\r\n] 2006.217.07:38:18.51#ibcon#*before write, iclass 35, count 0 2006.217.07:38:18.51#ibcon#enter sib2, iclass 35, count 0 2006.217.07:38:18.51#ibcon#flushed, iclass 35, count 0 2006.217.07:38:18.51#ibcon#about to write, iclass 35, count 0 2006.217.07:38:18.51#ibcon#wrote, iclass 35, count 0 2006.217.07:38:18.51#ibcon#about to read 3, iclass 35, count 0 2006.217.07:38:18.54#ibcon#read 3, iclass 35, count 0 2006.217.07:38:18.54#ibcon#about to read 4, iclass 35, count 0 2006.217.07:38:18.54#ibcon#read 4, iclass 35, count 0 2006.217.07:38:18.54#ibcon#about to read 5, iclass 35, count 0 2006.217.07:38:18.54#ibcon#read 5, iclass 35, count 0 2006.217.07:38:18.54#ibcon#about to read 6, iclass 35, count 0 2006.217.07:38:18.54#ibcon#read 6, iclass 35, count 0 2006.217.07:38:18.54#ibcon#end of sib2, iclass 35, count 0 2006.217.07:38:18.54#ibcon#*after write, iclass 35, count 0 2006.217.07:38:18.54#ibcon#*before return 0, iclass 35, count 0 2006.217.07:38:18.54#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.217.07:38:18.54#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.217.07:38:18.54#ibcon#about to clear, iclass 35 cls_cnt 0 2006.217.07:38:18.54#ibcon#cleared, iclass 35 cls_cnt 0 2006.217.07:38:18.54$vc4f8/valo=3,672.99 2006.217.07:38:18.54#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.217.07:38:18.54#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.217.07:38:18.54#ibcon#ireg 17 cls_cnt 0 2006.217.07:38:18.54#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.217.07:38:18.54#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.217.07:38:18.54#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.217.07:38:18.54#ibcon#enter wrdev, iclass 37, count 0 2006.217.07:38:18.54#ibcon#first serial, iclass 37, count 0 2006.217.07:38:18.54#ibcon#enter sib2, iclass 37, count 0 2006.217.07:38:18.54#ibcon#flushed, iclass 37, count 0 2006.217.07:38:18.54#ibcon#about to write, iclass 37, count 0 2006.217.07:38:18.54#ibcon#wrote, iclass 37, count 0 2006.217.07:38:18.54#ibcon#about to read 3, iclass 37, count 0 2006.217.07:38:18.56#ibcon#read 3, iclass 37, count 0 2006.217.07:38:18.56#ibcon#about to read 4, iclass 37, count 0 2006.217.07:38:18.56#ibcon#read 4, iclass 37, count 0 2006.217.07:38:18.56#ibcon#about to read 5, iclass 37, count 0 2006.217.07:38:18.56#ibcon#read 5, iclass 37, count 0 2006.217.07:38:18.56#ibcon#about to read 6, iclass 37, count 0 2006.217.07:38:18.56#ibcon#read 6, iclass 37, count 0 2006.217.07:38:18.56#ibcon#end of sib2, iclass 37, count 0 2006.217.07:38:18.56#ibcon#*mode == 0, iclass 37, count 0 2006.217.07:38:18.56#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.217.07:38:18.56#ibcon#[26=FRQ=03,672.99\r\n] 2006.217.07:38:18.56#ibcon#*before write, iclass 37, count 0 2006.217.07:38:18.56#ibcon#enter sib2, iclass 37, count 0 2006.217.07:38:18.56#ibcon#flushed, iclass 37, count 0 2006.217.07:38:18.56#ibcon#about to write, iclass 37, count 0 2006.217.07:38:18.56#ibcon#wrote, iclass 37, count 0 2006.217.07:38:18.56#ibcon#about to read 3, iclass 37, count 0 2006.217.07:38:18.61#ibcon#read 3, iclass 37, count 0 2006.217.07:38:18.61#ibcon#about to read 4, iclass 37, count 0 2006.217.07:38:18.61#ibcon#read 4, iclass 37, count 0 2006.217.07:38:18.61#ibcon#about to read 5, iclass 37, count 0 2006.217.07:38:18.61#ibcon#read 5, iclass 37, count 0 2006.217.07:38:18.61#ibcon#about to read 6, iclass 37, count 0 2006.217.07:38:18.61#ibcon#read 6, iclass 37, count 0 2006.217.07:38:18.61#ibcon#end of sib2, iclass 37, count 0 2006.217.07:38:18.61#ibcon#*after write, iclass 37, count 0 2006.217.07:38:18.61#ibcon#*before return 0, iclass 37, count 0 2006.217.07:38:18.61#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.217.07:38:18.61#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.217.07:38:18.61#ibcon#about to clear, iclass 37 cls_cnt 0 2006.217.07:38:18.61#ibcon#cleared, iclass 37 cls_cnt 0 2006.217.07:38:18.61$vc4f8/va=3,4 2006.217.07:38:18.61#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.217.07:38:18.61#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.217.07:38:18.61#ibcon#ireg 11 cls_cnt 2 2006.217.07:38:18.61#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.217.07:38:18.66#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.217.07:38:18.66#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.217.07:38:18.66#ibcon#enter wrdev, iclass 39, count 2 2006.217.07:38:18.66#ibcon#first serial, iclass 39, count 2 2006.217.07:38:18.66#ibcon#enter sib2, iclass 39, count 2 2006.217.07:38:18.66#ibcon#flushed, iclass 39, count 2 2006.217.07:38:18.66#ibcon#about to write, iclass 39, count 2 2006.217.07:38:18.66#ibcon#wrote, iclass 39, count 2 2006.217.07:38:18.66#ibcon#about to read 3, iclass 39, count 2 2006.217.07:38:18.68#ibcon#read 3, iclass 39, count 2 2006.217.07:38:18.68#ibcon#about to read 4, iclass 39, count 2 2006.217.07:38:18.68#ibcon#read 4, iclass 39, count 2 2006.217.07:38:18.68#ibcon#about to read 5, iclass 39, count 2 2006.217.07:38:18.68#ibcon#read 5, iclass 39, count 2 2006.217.07:38:18.68#ibcon#about to read 6, iclass 39, count 2 2006.217.07:38:18.68#ibcon#read 6, iclass 39, count 2 2006.217.07:38:18.68#ibcon#end of sib2, iclass 39, count 2 2006.217.07:38:18.68#ibcon#*mode == 0, iclass 39, count 2 2006.217.07:38:18.68#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.217.07:38:18.68#ibcon#[25=AT03-04\r\n] 2006.217.07:38:18.68#ibcon#*before write, iclass 39, count 2 2006.217.07:38:18.68#ibcon#enter sib2, iclass 39, count 2 2006.217.07:38:18.68#ibcon#flushed, iclass 39, count 2 2006.217.07:38:18.68#ibcon#about to write, iclass 39, count 2 2006.217.07:38:18.68#ibcon#wrote, iclass 39, count 2 2006.217.07:38:18.68#ibcon#about to read 3, iclass 39, count 2 2006.217.07:38:18.71#ibcon#read 3, iclass 39, count 2 2006.217.07:38:18.71#ibcon#about to read 4, iclass 39, count 2 2006.217.07:38:18.71#ibcon#read 4, iclass 39, count 2 2006.217.07:38:18.71#ibcon#about to read 5, iclass 39, count 2 2006.217.07:38:18.71#ibcon#read 5, iclass 39, count 2 2006.217.07:38:18.71#ibcon#about to read 6, iclass 39, count 2 2006.217.07:38:18.71#ibcon#read 6, iclass 39, count 2 2006.217.07:38:18.71#ibcon#end of sib2, iclass 39, count 2 2006.217.07:38:18.71#ibcon#*after write, iclass 39, count 2 2006.217.07:38:18.71#ibcon#*before return 0, iclass 39, count 2 2006.217.07:38:18.71#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.217.07:38:18.71#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.217.07:38:18.71#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.217.07:38:18.71#ibcon#ireg 7 cls_cnt 0 2006.217.07:38:18.71#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.217.07:38:18.83#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.217.07:38:18.83#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.217.07:38:18.83#ibcon#enter wrdev, iclass 39, count 0 2006.217.07:38:18.83#ibcon#first serial, iclass 39, count 0 2006.217.07:38:18.83#ibcon#enter sib2, iclass 39, count 0 2006.217.07:38:18.83#ibcon#flushed, iclass 39, count 0 2006.217.07:38:18.83#ibcon#about to write, iclass 39, count 0 2006.217.07:38:18.83#ibcon#wrote, iclass 39, count 0 2006.217.07:38:18.83#ibcon#about to read 3, iclass 39, count 0 2006.217.07:38:18.85#ibcon#read 3, iclass 39, count 0 2006.217.07:38:18.85#ibcon#about to read 4, iclass 39, count 0 2006.217.07:38:18.85#ibcon#read 4, iclass 39, count 0 2006.217.07:38:18.85#ibcon#about to read 5, iclass 39, count 0 2006.217.07:38:18.85#ibcon#read 5, iclass 39, count 0 2006.217.07:38:18.85#ibcon#about to read 6, iclass 39, count 0 2006.217.07:38:18.85#ibcon#read 6, iclass 39, count 0 2006.217.07:38:18.85#ibcon#end of sib2, iclass 39, count 0 2006.217.07:38:18.85#ibcon#*mode == 0, iclass 39, count 0 2006.217.07:38:18.85#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.217.07:38:18.85#ibcon#[25=USB\r\n] 2006.217.07:38:18.85#ibcon#*before write, iclass 39, count 0 2006.217.07:38:18.85#ibcon#enter sib2, iclass 39, count 0 2006.217.07:38:18.85#ibcon#flushed, iclass 39, count 0 2006.217.07:38:18.85#ibcon#about to write, iclass 39, count 0 2006.217.07:38:18.85#ibcon#wrote, iclass 39, count 0 2006.217.07:38:18.85#ibcon#about to read 3, iclass 39, count 0 2006.217.07:38:18.88#ibcon#read 3, iclass 39, count 0 2006.217.07:38:18.88#ibcon#about to read 4, iclass 39, count 0 2006.217.07:38:18.88#ibcon#read 4, iclass 39, count 0 2006.217.07:38:18.88#ibcon#about to read 5, iclass 39, count 0 2006.217.07:38:18.88#ibcon#read 5, iclass 39, count 0 2006.217.07:38:18.88#ibcon#about to read 6, iclass 39, count 0 2006.217.07:38:18.88#ibcon#read 6, iclass 39, count 0 2006.217.07:38:18.88#ibcon#end of sib2, iclass 39, count 0 2006.217.07:38:18.88#ibcon#*after write, iclass 39, count 0 2006.217.07:38:18.88#ibcon#*before return 0, iclass 39, count 0 2006.217.07:38:18.88#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.217.07:38:18.88#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.217.07:38:18.88#ibcon#about to clear, iclass 39 cls_cnt 0 2006.217.07:38:18.88#ibcon#cleared, iclass 39 cls_cnt 0 2006.217.07:38:18.88$vc4f8/valo=4,832.99 2006.217.07:38:18.88#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.217.07:38:18.88#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.217.07:38:18.88#ibcon#ireg 17 cls_cnt 0 2006.217.07:38:18.88#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.217.07:38:18.88#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.217.07:38:18.88#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.217.07:38:18.88#ibcon#enter wrdev, iclass 3, count 0 2006.217.07:38:18.88#ibcon#first serial, iclass 3, count 0 2006.217.07:38:18.88#ibcon#enter sib2, iclass 3, count 0 2006.217.07:38:18.88#ibcon#flushed, iclass 3, count 0 2006.217.07:38:18.88#ibcon#about to write, iclass 3, count 0 2006.217.07:38:18.88#ibcon#wrote, iclass 3, count 0 2006.217.07:38:18.88#ibcon#about to read 3, iclass 3, count 0 2006.217.07:38:18.90#ibcon#read 3, iclass 3, count 0 2006.217.07:38:18.90#ibcon#about to read 4, iclass 3, count 0 2006.217.07:38:18.90#ibcon#read 4, iclass 3, count 0 2006.217.07:38:18.90#ibcon#about to read 5, iclass 3, count 0 2006.217.07:38:18.90#ibcon#read 5, iclass 3, count 0 2006.217.07:38:18.90#ibcon#about to read 6, iclass 3, count 0 2006.217.07:38:18.90#ibcon#read 6, iclass 3, count 0 2006.217.07:38:18.90#ibcon#end of sib2, iclass 3, count 0 2006.217.07:38:18.90#ibcon#*mode == 0, iclass 3, count 0 2006.217.07:38:18.90#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.217.07:38:18.90#ibcon#[26=FRQ=04,832.99\r\n] 2006.217.07:38:18.90#ibcon#*before write, iclass 3, count 0 2006.217.07:38:18.90#ibcon#enter sib2, iclass 3, count 0 2006.217.07:38:18.90#ibcon#flushed, iclass 3, count 0 2006.217.07:38:18.90#ibcon#about to write, iclass 3, count 0 2006.217.07:38:18.90#ibcon#wrote, iclass 3, count 0 2006.217.07:38:18.90#ibcon#about to read 3, iclass 3, count 0 2006.217.07:38:18.94#ibcon#read 3, iclass 3, count 0 2006.217.07:38:18.94#ibcon#about to read 4, iclass 3, count 0 2006.217.07:38:18.94#ibcon#read 4, iclass 3, count 0 2006.217.07:38:18.94#ibcon#about to read 5, iclass 3, count 0 2006.217.07:38:18.94#ibcon#read 5, iclass 3, count 0 2006.217.07:38:18.94#ibcon#about to read 6, iclass 3, count 0 2006.217.07:38:18.94#ibcon#read 6, iclass 3, count 0 2006.217.07:38:18.94#ibcon#end of sib2, iclass 3, count 0 2006.217.07:38:18.94#ibcon#*after write, iclass 3, count 0 2006.217.07:38:18.94#ibcon#*before return 0, iclass 3, count 0 2006.217.07:38:18.94#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.217.07:38:18.94#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.217.07:38:18.94#ibcon#about to clear, iclass 3 cls_cnt 0 2006.217.07:38:18.94#ibcon#cleared, iclass 3 cls_cnt 0 2006.217.07:38:18.94$vc4f8/va=4,4 2006.217.07:38:18.94#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.217.07:38:18.94#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.217.07:38:18.94#ibcon#ireg 11 cls_cnt 2 2006.217.07:38:18.94#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.217.07:38:19.00#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.217.07:38:19.00#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.217.07:38:19.00#ibcon#enter wrdev, iclass 5, count 2 2006.217.07:38:19.00#ibcon#first serial, iclass 5, count 2 2006.217.07:38:19.00#ibcon#enter sib2, iclass 5, count 2 2006.217.07:38:19.00#ibcon#flushed, iclass 5, count 2 2006.217.07:38:19.00#ibcon#about to write, iclass 5, count 2 2006.217.07:38:19.00#ibcon#wrote, iclass 5, count 2 2006.217.07:38:19.00#ibcon#about to read 3, iclass 5, count 2 2006.217.07:38:19.02#ibcon#read 3, iclass 5, count 2 2006.217.07:38:19.02#ibcon#about to read 4, iclass 5, count 2 2006.217.07:38:19.02#ibcon#read 4, iclass 5, count 2 2006.217.07:38:19.02#ibcon#about to read 5, iclass 5, count 2 2006.217.07:38:19.02#ibcon#read 5, iclass 5, count 2 2006.217.07:38:19.02#ibcon#about to read 6, iclass 5, count 2 2006.217.07:38:19.02#ibcon#read 6, iclass 5, count 2 2006.217.07:38:19.02#ibcon#end of sib2, iclass 5, count 2 2006.217.07:38:19.02#ibcon#*mode == 0, iclass 5, count 2 2006.217.07:38:19.02#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.217.07:38:19.02#ibcon#[25=AT04-04\r\n] 2006.217.07:38:19.02#ibcon#*before write, iclass 5, count 2 2006.217.07:38:19.02#ibcon#enter sib2, iclass 5, count 2 2006.217.07:38:19.02#ibcon#flushed, iclass 5, count 2 2006.217.07:38:19.02#ibcon#about to write, iclass 5, count 2 2006.217.07:38:19.02#ibcon#wrote, iclass 5, count 2 2006.217.07:38:19.02#ibcon#about to read 3, iclass 5, count 2 2006.217.07:38:19.05#ibcon#read 3, iclass 5, count 2 2006.217.07:38:19.05#ibcon#about to read 4, iclass 5, count 2 2006.217.07:38:19.05#ibcon#read 4, iclass 5, count 2 2006.217.07:38:19.05#ibcon#about to read 5, iclass 5, count 2 2006.217.07:38:19.05#ibcon#read 5, iclass 5, count 2 2006.217.07:38:19.05#ibcon#about to read 6, iclass 5, count 2 2006.217.07:38:19.05#ibcon#read 6, iclass 5, count 2 2006.217.07:38:19.05#ibcon#end of sib2, iclass 5, count 2 2006.217.07:38:19.05#ibcon#*after write, iclass 5, count 2 2006.217.07:38:19.05#ibcon#*before return 0, iclass 5, count 2 2006.217.07:38:19.05#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.217.07:38:19.05#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.217.07:38:19.05#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.217.07:38:19.05#ibcon#ireg 7 cls_cnt 0 2006.217.07:38:19.05#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.217.07:38:19.17#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.217.07:38:19.17#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.217.07:38:19.17#ibcon#enter wrdev, iclass 5, count 0 2006.217.07:38:19.17#ibcon#first serial, iclass 5, count 0 2006.217.07:38:19.17#ibcon#enter sib2, iclass 5, count 0 2006.217.07:38:19.17#ibcon#flushed, iclass 5, count 0 2006.217.07:38:19.17#ibcon#about to write, iclass 5, count 0 2006.217.07:38:19.17#ibcon#wrote, iclass 5, count 0 2006.217.07:38:19.17#ibcon#about to read 3, iclass 5, count 0 2006.217.07:38:19.19#ibcon#read 3, iclass 5, count 0 2006.217.07:38:19.19#ibcon#about to read 4, iclass 5, count 0 2006.217.07:38:19.19#ibcon#read 4, iclass 5, count 0 2006.217.07:38:19.19#ibcon#about to read 5, iclass 5, count 0 2006.217.07:38:19.19#ibcon#read 5, iclass 5, count 0 2006.217.07:38:19.19#ibcon#about to read 6, iclass 5, count 0 2006.217.07:38:19.19#ibcon#read 6, iclass 5, count 0 2006.217.07:38:19.19#ibcon#end of sib2, iclass 5, count 0 2006.217.07:38:19.19#ibcon#*mode == 0, iclass 5, count 0 2006.217.07:38:19.19#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.217.07:38:19.19#ibcon#[25=USB\r\n] 2006.217.07:38:19.19#ibcon#*before write, iclass 5, count 0 2006.217.07:38:19.19#ibcon#enter sib2, iclass 5, count 0 2006.217.07:38:19.19#ibcon#flushed, iclass 5, count 0 2006.217.07:38:19.19#ibcon#about to write, iclass 5, count 0 2006.217.07:38:19.19#ibcon#wrote, iclass 5, count 0 2006.217.07:38:19.19#ibcon#about to read 3, iclass 5, count 0 2006.217.07:38:19.22#ibcon#read 3, iclass 5, count 0 2006.217.07:38:19.22#ibcon#about to read 4, iclass 5, count 0 2006.217.07:38:19.22#ibcon#read 4, iclass 5, count 0 2006.217.07:38:19.22#ibcon#about to read 5, iclass 5, count 0 2006.217.07:38:19.22#ibcon#read 5, iclass 5, count 0 2006.217.07:38:19.22#ibcon#about to read 6, iclass 5, count 0 2006.217.07:38:19.22#ibcon#read 6, iclass 5, count 0 2006.217.07:38:19.22#ibcon#end of sib2, iclass 5, count 0 2006.217.07:38:19.22#ibcon#*after write, iclass 5, count 0 2006.217.07:38:19.22#ibcon#*before return 0, iclass 5, count 0 2006.217.07:38:19.22#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.217.07:38:19.22#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.217.07:38:19.22#ibcon#about to clear, iclass 5 cls_cnt 0 2006.217.07:38:19.22#ibcon#cleared, iclass 5 cls_cnt 0 2006.217.07:38:19.22$vc4f8/valo=5,652.99 2006.217.07:38:19.22#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.217.07:38:19.22#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.217.07:38:19.22#ibcon#ireg 17 cls_cnt 0 2006.217.07:38:19.22#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.217.07:38:19.22#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.217.07:38:19.22#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.217.07:38:19.22#ibcon#enter wrdev, iclass 7, count 0 2006.217.07:38:19.22#ibcon#first serial, iclass 7, count 0 2006.217.07:38:19.22#ibcon#enter sib2, iclass 7, count 0 2006.217.07:38:19.22#ibcon#flushed, iclass 7, count 0 2006.217.07:38:19.22#ibcon#about to write, iclass 7, count 0 2006.217.07:38:19.22#ibcon#wrote, iclass 7, count 0 2006.217.07:38:19.22#ibcon#about to read 3, iclass 7, count 0 2006.217.07:38:19.24#ibcon#read 3, iclass 7, count 0 2006.217.07:38:19.24#ibcon#about to read 4, iclass 7, count 0 2006.217.07:38:19.24#ibcon#read 4, iclass 7, count 0 2006.217.07:38:19.24#ibcon#about to read 5, iclass 7, count 0 2006.217.07:38:19.24#ibcon#read 5, iclass 7, count 0 2006.217.07:38:19.24#ibcon#about to read 6, iclass 7, count 0 2006.217.07:38:19.24#ibcon#read 6, iclass 7, count 0 2006.217.07:38:19.24#ibcon#end of sib2, iclass 7, count 0 2006.217.07:38:19.24#ibcon#*mode == 0, iclass 7, count 0 2006.217.07:38:19.24#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.217.07:38:19.24#ibcon#[26=FRQ=05,652.99\r\n] 2006.217.07:38:19.24#ibcon#*before write, iclass 7, count 0 2006.217.07:38:19.24#ibcon#enter sib2, iclass 7, count 0 2006.217.07:38:19.24#ibcon#flushed, iclass 7, count 0 2006.217.07:38:19.24#ibcon#about to write, iclass 7, count 0 2006.217.07:38:19.24#ibcon#wrote, iclass 7, count 0 2006.217.07:38:19.24#ibcon#about to read 3, iclass 7, count 0 2006.217.07:38:19.28#ibcon#read 3, iclass 7, count 0 2006.217.07:38:19.28#ibcon#about to read 4, iclass 7, count 0 2006.217.07:38:19.28#ibcon#read 4, iclass 7, count 0 2006.217.07:38:19.28#ibcon#about to read 5, iclass 7, count 0 2006.217.07:38:19.28#ibcon#read 5, iclass 7, count 0 2006.217.07:38:19.28#ibcon#about to read 6, iclass 7, count 0 2006.217.07:38:19.28#ibcon#read 6, iclass 7, count 0 2006.217.07:38:19.28#ibcon#end of sib2, iclass 7, count 0 2006.217.07:38:19.28#ibcon#*after write, iclass 7, count 0 2006.217.07:38:19.28#ibcon#*before return 0, iclass 7, count 0 2006.217.07:38:19.28#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.217.07:38:19.28#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.217.07:38:19.28#ibcon#about to clear, iclass 7 cls_cnt 0 2006.217.07:38:19.28#ibcon#cleared, iclass 7 cls_cnt 0 2006.217.07:38:19.28$vc4f8/va=5,7 2006.217.07:38:19.28#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.217.07:38:19.28#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.217.07:38:19.28#ibcon#ireg 11 cls_cnt 2 2006.217.07:38:19.28#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.217.07:38:19.34#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.217.07:38:19.34#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.217.07:38:19.34#ibcon#enter wrdev, iclass 11, count 2 2006.217.07:38:19.34#ibcon#first serial, iclass 11, count 2 2006.217.07:38:19.34#ibcon#enter sib2, iclass 11, count 2 2006.217.07:38:19.34#ibcon#flushed, iclass 11, count 2 2006.217.07:38:19.34#ibcon#about to write, iclass 11, count 2 2006.217.07:38:19.34#ibcon#wrote, iclass 11, count 2 2006.217.07:38:19.34#ibcon#about to read 3, iclass 11, count 2 2006.217.07:38:19.36#ibcon#read 3, iclass 11, count 2 2006.217.07:38:19.36#ibcon#about to read 4, iclass 11, count 2 2006.217.07:38:19.36#ibcon#read 4, iclass 11, count 2 2006.217.07:38:19.36#ibcon#about to read 5, iclass 11, count 2 2006.217.07:38:19.36#ibcon#read 5, iclass 11, count 2 2006.217.07:38:19.36#ibcon#about to read 6, iclass 11, count 2 2006.217.07:38:19.36#ibcon#read 6, iclass 11, count 2 2006.217.07:38:19.36#ibcon#end of sib2, iclass 11, count 2 2006.217.07:38:19.36#ibcon#*mode == 0, iclass 11, count 2 2006.217.07:38:19.36#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.217.07:38:19.36#ibcon#[25=AT05-07\r\n] 2006.217.07:38:19.36#ibcon#*before write, iclass 11, count 2 2006.217.07:38:19.36#ibcon#enter sib2, iclass 11, count 2 2006.217.07:38:19.36#ibcon#flushed, iclass 11, count 2 2006.217.07:38:19.36#ibcon#about to write, iclass 11, count 2 2006.217.07:38:19.36#ibcon#wrote, iclass 11, count 2 2006.217.07:38:19.36#ibcon#about to read 3, iclass 11, count 2 2006.217.07:38:19.39#ibcon#read 3, iclass 11, count 2 2006.217.07:38:19.39#ibcon#about to read 4, iclass 11, count 2 2006.217.07:38:19.39#ibcon#read 4, iclass 11, count 2 2006.217.07:38:19.39#ibcon#about to read 5, iclass 11, count 2 2006.217.07:38:19.39#ibcon#read 5, iclass 11, count 2 2006.217.07:38:19.39#ibcon#about to read 6, iclass 11, count 2 2006.217.07:38:19.39#ibcon#read 6, iclass 11, count 2 2006.217.07:38:19.39#ibcon#end of sib2, iclass 11, count 2 2006.217.07:38:19.39#ibcon#*after write, iclass 11, count 2 2006.217.07:38:19.39#ibcon#*before return 0, iclass 11, count 2 2006.217.07:38:19.39#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.217.07:38:19.39#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.217.07:38:19.39#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.217.07:38:19.39#ibcon#ireg 7 cls_cnt 0 2006.217.07:38:19.39#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.217.07:38:19.51#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.217.07:38:19.51#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.217.07:38:19.51#ibcon#enter wrdev, iclass 11, count 0 2006.217.07:38:19.51#ibcon#first serial, iclass 11, count 0 2006.217.07:38:19.51#ibcon#enter sib2, iclass 11, count 0 2006.217.07:38:19.51#ibcon#flushed, iclass 11, count 0 2006.217.07:38:19.51#ibcon#about to write, iclass 11, count 0 2006.217.07:38:19.51#ibcon#wrote, iclass 11, count 0 2006.217.07:38:19.51#ibcon#about to read 3, iclass 11, count 0 2006.217.07:38:19.53#ibcon#read 3, iclass 11, count 0 2006.217.07:38:19.53#ibcon#about to read 4, iclass 11, count 0 2006.217.07:38:19.53#ibcon#read 4, iclass 11, count 0 2006.217.07:38:19.53#ibcon#about to read 5, iclass 11, count 0 2006.217.07:38:19.53#ibcon#read 5, iclass 11, count 0 2006.217.07:38:19.53#ibcon#about to read 6, iclass 11, count 0 2006.217.07:38:19.53#ibcon#read 6, iclass 11, count 0 2006.217.07:38:19.53#ibcon#end of sib2, iclass 11, count 0 2006.217.07:38:19.53#ibcon#*mode == 0, iclass 11, count 0 2006.217.07:38:19.53#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.217.07:38:19.53#ibcon#[25=USB\r\n] 2006.217.07:38:19.53#ibcon#*before write, iclass 11, count 0 2006.217.07:38:19.53#ibcon#enter sib2, iclass 11, count 0 2006.217.07:38:19.53#ibcon#flushed, iclass 11, count 0 2006.217.07:38:19.53#ibcon#about to write, iclass 11, count 0 2006.217.07:38:19.53#ibcon#wrote, iclass 11, count 0 2006.217.07:38:19.53#ibcon#about to read 3, iclass 11, count 0 2006.217.07:38:19.56#ibcon#read 3, iclass 11, count 0 2006.217.07:38:19.56#ibcon#about to read 4, iclass 11, count 0 2006.217.07:38:19.56#ibcon#read 4, iclass 11, count 0 2006.217.07:38:19.56#ibcon#about to read 5, iclass 11, count 0 2006.217.07:38:19.56#ibcon#read 5, iclass 11, count 0 2006.217.07:38:19.56#ibcon#about to read 6, iclass 11, count 0 2006.217.07:38:19.56#ibcon#read 6, iclass 11, count 0 2006.217.07:38:19.56#ibcon#end of sib2, iclass 11, count 0 2006.217.07:38:19.56#ibcon#*after write, iclass 11, count 0 2006.217.07:38:19.56#ibcon#*before return 0, iclass 11, count 0 2006.217.07:38:19.56#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.217.07:38:19.56#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.217.07:38:19.56#ibcon#about to clear, iclass 11 cls_cnt 0 2006.217.07:38:19.56#ibcon#cleared, iclass 11 cls_cnt 0 2006.217.07:38:19.56$vc4f8/valo=6,772.99 2006.217.07:38:19.56#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.217.07:38:19.56#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.217.07:38:19.56#ibcon#ireg 17 cls_cnt 0 2006.217.07:38:19.56#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.217.07:38:19.56#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.217.07:38:19.56#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.217.07:38:19.56#ibcon#enter wrdev, iclass 13, count 0 2006.217.07:38:19.56#ibcon#first serial, iclass 13, count 0 2006.217.07:38:19.56#ibcon#enter sib2, iclass 13, count 0 2006.217.07:38:19.56#ibcon#flushed, iclass 13, count 0 2006.217.07:38:19.56#ibcon#about to write, iclass 13, count 0 2006.217.07:38:19.56#ibcon#wrote, iclass 13, count 0 2006.217.07:38:19.56#ibcon#about to read 3, iclass 13, count 0 2006.217.07:38:19.58#ibcon#read 3, iclass 13, count 0 2006.217.07:38:19.58#ibcon#about to read 4, iclass 13, count 0 2006.217.07:38:19.58#ibcon#read 4, iclass 13, count 0 2006.217.07:38:19.58#ibcon#about to read 5, iclass 13, count 0 2006.217.07:38:19.58#ibcon#read 5, iclass 13, count 0 2006.217.07:38:19.58#ibcon#about to read 6, iclass 13, count 0 2006.217.07:38:19.58#ibcon#read 6, iclass 13, count 0 2006.217.07:38:19.58#ibcon#end of sib2, iclass 13, count 0 2006.217.07:38:19.58#ibcon#*mode == 0, iclass 13, count 0 2006.217.07:38:19.58#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.217.07:38:19.58#ibcon#[26=FRQ=06,772.99\r\n] 2006.217.07:38:19.58#ibcon#*before write, iclass 13, count 0 2006.217.07:38:19.58#ibcon#enter sib2, iclass 13, count 0 2006.217.07:38:19.58#ibcon#flushed, iclass 13, count 0 2006.217.07:38:19.58#ibcon#about to write, iclass 13, count 0 2006.217.07:38:19.58#ibcon#wrote, iclass 13, count 0 2006.217.07:38:19.58#ibcon#about to read 3, iclass 13, count 0 2006.217.07:38:19.62#ibcon#read 3, iclass 13, count 0 2006.217.07:38:19.62#ibcon#about to read 4, iclass 13, count 0 2006.217.07:38:19.62#ibcon#read 4, iclass 13, count 0 2006.217.07:38:19.62#ibcon#about to read 5, iclass 13, count 0 2006.217.07:38:19.62#ibcon#read 5, iclass 13, count 0 2006.217.07:38:19.62#ibcon#about to read 6, iclass 13, count 0 2006.217.07:38:19.62#ibcon#read 6, iclass 13, count 0 2006.217.07:38:19.62#ibcon#end of sib2, iclass 13, count 0 2006.217.07:38:19.62#ibcon#*after write, iclass 13, count 0 2006.217.07:38:19.62#ibcon#*before return 0, iclass 13, count 0 2006.217.07:38:19.62#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.217.07:38:19.62#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.217.07:38:19.62#ibcon#about to clear, iclass 13 cls_cnt 0 2006.217.07:38:19.62#ibcon#cleared, iclass 13 cls_cnt 0 2006.217.07:38:19.62$vc4f8/va=6,6 2006.217.07:38:19.62#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.217.07:38:19.62#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.217.07:38:19.62#ibcon#ireg 11 cls_cnt 2 2006.217.07:38:19.62#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.217.07:38:19.65#abcon#<5=/05 4.0 8.9 31.29 621008.6\r\n> 2006.217.07:38:19.67#abcon#{5=INTERFACE CLEAR} 2006.217.07:38:19.68#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.217.07:38:19.68#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.217.07:38:19.68#ibcon#enter wrdev, iclass 16, count 2 2006.217.07:38:19.68#ibcon#first serial, iclass 16, count 2 2006.217.07:38:19.68#ibcon#enter sib2, iclass 16, count 2 2006.217.07:38:19.68#ibcon#flushed, iclass 16, count 2 2006.217.07:38:19.68#ibcon#about to write, iclass 16, count 2 2006.217.07:38:19.68#ibcon#wrote, iclass 16, count 2 2006.217.07:38:19.68#ibcon#about to read 3, iclass 16, count 2 2006.217.07:38:19.70#ibcon#read 3, iclass 16, count 2 2006.217.07:38:19.70#ibcon#about to read 4, iclass 16, count 2 2006.217.07:38:19.70#ibcon#read 4, iclass 16, count 2 2006.217.07:38:19.70#ibcon#about to read 5, iclass 16, count 2 2006.217.07:38:19.70#ibcon#read 5, iclass 16, count 2 2006.217.07:38:19.70#ibcon#about to read 6, iclass 16, count 2 2006.217.07:38:19.70#ibcon#read 6, iclass 16, count 2 2006.217.07:38:19.70#ibcon#end of sib2, iclass 16, count 2 2006.217.07:38:19.70#ibcon#*mode == 0, iclass 16, count 2 2006.217.07:38:19.70#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.217.07:38:19.70#ibcon#[25=AT06-06\r\n] 2006.217.07:38:19.70#ibcon#*before write, iclass 16, count 2 2006.217.07:38:19.70#ibcon#enter sib2, iclass 16, count 2 2006.217.07:38:19.70#ibcon#flushed, iclass 16, count 2 2006.217.07:38:19.70#ibcon#about to write, iclass 16, count 2 2006.217.07:38:19.70#ibcon#wrote, iclass 16, count 2 2006.217.07:38:19.70#ibcon#about to read 3, iclass 16, count 2 2006.217.07:38:19.73#abcon#[5=S1D000X0/0*\r\n] 2006.217.07:38:19.73#ibcon#read 3, iclass 16, count 2 2006.217.07:38:19.73#ibcon#about to read 4, iclass 16, count 2 2006.217.07:38:19.73#ibcon#read 4, iclass 16, count 2 2006.217.07:38:19.73#ibcon#about to read 5, iclass 16, count 2 2006.217.07:38:19.73#ibcon#read 5, iclass 16, count 2 2006.217.07:38:19.73#ibcon#about to read 6, iclass 16, count 2 2006.217.07:38:19.73#ibcon#read 6, iclass 16, count 2 2006.217.07:38:19.73#ibcon#end of sib2, iclass 16, count 2 2006.217.07:38:19.73#ibcon#*after write, iclass 16, count 2 2006.217.07:38:19.73#ibcon#*before return 0, iclass 16, count 2 2006.217.07:38:19.73#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.217.07:38:19.73#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.217.07:38:19.73#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.217.07:38:19.73#ibcon#ireg 7 cls_cnt 0 2006.217.07:38:19.73#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.217.07:38:19.85#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.217.07:38:19.85#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.217.07:38:19.85#ibcon#enter wrdev, iclass 16, count 0 2006.217.07:38:19.85#ibcon#first serial, iclass 16, count 0 2006.217.07:38:19.85#ibcon#enter sib2, iclass 16, count 0 2006.217.07:38:19.85#ibcon#flushed, iclass 16, count 0 2006.217.07:38:19.85#ibcon#about to write, iclass 16, count 0 2006.217.07:38:19.85#ibcon#wrote, iclass 16, count 0 2006.217.07:38:19.85#ibcon#about to read 3, iclass 16, count 0 2006.217.07:38:19.87#ibcon#read 3, iclass 16, count 0 2006.217.07:38:19.87#ibcon#about to read 4, iclass 16, count 0 2006.217.07:38:19.87#ibcon#read 4, iclass 16, count 0 2006.217.07:38:19.87#ibcon#about to read 5, iclass 16, count 0 2006.217.07:38:19.87#ibcon#read 5, iclass 16, count 0 2006.217.07:38:19.87#ibcon#about to read 6, iclass 16, count 0 2006.217.07:38:19.87#ibcon#read 6, iclass 16, count 0 2006.217.07:38:19.87#ibcon#end of sib2, iclass 16, count 0 2006.217.07:38:19.87#ibcon#*mode == 0, iclass 16, count 0 2006.217.07:38:19.87#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.217.07:38:19.87#ibcon#[25=USB\r\n] 2006.217.07:38:19.87#ibcon#*before write, iclass 16, count 0 2006.217.07:38:19.87#ibcon#enter sib2, iclass 16, count 0 2006.217.07:38:19.87#ibcon#flushed, iclass 16, count 0 2006.217.07:38:19.87#ibcon#about to write, iclass 16, count 0 2006.217.07:38:19.87#ibcon#wrote, iclass 16, count 0 2006.217.07:38:19.87#ibcon#about to read 3, iclass 16, count 0 2006.217.07:38:19.90#ibcon#read 3, iclass 16, count 0 2006.217.07:38:19.90#ibcon#about to read 4, iclass 16, count 0 2006.217.07:38:19.90#ibcon#read 4, iclass 16, count 0 2006.217.07:38:19.90#ibcon#about to read 5, iclass 16, count 0 2006.217.07:38:19.90#ibcon#read 5, iclass 16, count 0 2006.217.07:38:19.90#ibcon#about to read 6, iclass 16, count 0 2006.217.07:38:19.90#ibcon#read 6, iclass 16, count 0 2006.217.07:38:19.90#ibcon#end of sib2, iclass 16, count 0 2006.217.07:38:19.90#ibcon#*after write, iclass 16, count 0 2006.217.07:38:19.90#ibcon#*before return 0, iclass 16, count 0 2006.217.07:38:19.90#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.217.07:38:19.90#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.217.07:38:19.90#ibcon#about to clear, iclass 16 cls_cnt 0 2006.217.07:38:19.90#ibcon#cleared, iclass 16 cls_cnt 0 2006.217.07:38:19.90$vc4f8/valo=7,832.99 2006.217.07:38:19.90#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.217.07:38:19.90#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.217.07:38:19.90#ibcon#ireg 17 cls_cnt 0 2006.217.07:38:19.90#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.217.07:38:19.90#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.217.07:38:19.90#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.217.07:38:19.90#ibcon#enter wrdev, iclass 21, count 0 2006.217.07:38:19.90#ibcon#first serial, iclass 21, count 0 2006.217.07:38:19.90#ibcon#enter sib2, iclass 21, count 0 2006.217.07:38:19.90#ibcon#flushed, iclass 21, count 0 2006.217.07:38:19.90#ibcon#about to write, iclass 21, count 0 2006.217.07:38:19.90#ibcon#wrote, iclass 21, count 0 2006.217.07:38:19.90#ibcon#about to read 3, iclass 21, count 0 2006.217.07:38:19.92#ibcon#read 3, iclass 21, count 0 2006.217.07:38:19.92#ibcon#about to read 4, iclass 21, count 0 2006.217.07:38:19.92#ibcon#read 4, iclass 21, count 0 2006.217.07:38:19.92#ibcon#about to read 5, iclass 21, count 0 2006.217.07:38:19.92#ibcon#read 5, iclass 21, count 0 2006.217.07:38:19.92#ibcon#about to read 6, iclass 21, count 0 2006.217.07:38:19.92#ibcon#read 6, iclass 21, count 0 2006.217.07:38:19.92#ibcon#end of sib2, iclass 21, count 0 2006.217.07:38:19.92#ibcon#*mode == 0, iclass 21, count 0 2006.217.07:38:19.92#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.217.07:38:19.92#ibcon#[26=FRQ=07,832.99\r\n] 2006.217.07:38:19.92#ibcon#*before write, iclass 21, count 0 2006.217.07:38:19.92#ibcon#enter sib2, iclass 21, count 0 2006.217.07:38:19.92#ibcon#flushed, iclass 21, count 0 2006.217.07:38:19.92#ibcon#about to write, iclass 21, count 0 2006.217.07:38:19.92#ibcon#wrote, iclass 21, count 0 2006.217.07:38:19.92#ibcon#about to read 3, iclass 21, count 0 2006.217.07:38:19.96#ibcon#read 3, iclass 21, count 0 2006.217.07:38:19.96#ibcon#about to read 4, iclass 21, count 0 2006.217.07:38:19.96#ibcon#read 4, iclass 21, count 0 2006.217.07:38:19.96#ibcon#about to read 5, iclass 21, count 0 2006.217.07:38:19.96#ibcon#read 5, iclass 21, count 0 2006.217.07:38:19.96#ibcon#about to read 6, iclass 21, count 0 2006.217.07:38:19.96#ibcon#read 6, iclass 21, count 0 2006.217.07:38:19.96#ibcon#end of sib2, iclass 21, count 0 2006.217.07:38:19.96#ibcon#*after write, iclass 21, count 0 2006.217.07:38:19.96#ibcon#*before return 0, iclass 21, count 0 2006.217.07:38:19.96#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.217.07:38:19.96#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.217.07:38:19.96#ibcon#about to clear, iclass 21 cls_cnt 0 2006.217.07:38:19.96#ibcon#cleared, iclass 21 cls_cnt 0 2006.217.07:38:19.96$vc4f8/va=7,6 2006.217.07:38:19.96#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.217.07:38:19.96#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.217.07:38:19.96#ibcon#ireg 11 cls_cnt 2 2006.217.07:38:19.96#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.217.07:38:20.02#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.217.07:38:20.02#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.217.07:38:20.02#ibcon#enter wrdev, iclass 23, count 2 2006.217.07:38:20.02#ibcon#first serial, iclass 23, count 2 2006.217.07:38:20.02#ibcon#enter sib2, iclass 23, count 2 2006.217.07:38:20.02#ibcon#flushed, iclass 23, count 2 2006.217.07:38:20.02#ibcon#about to write, iclass 23, count 2 2006.217.07:38:20.02#ibcon#wrote, iclass 23, count 2 2006.217.07:38:20.02#ibcon#about to read 3, iclass 23, count 2 2006.217.07:38:20.04#ibcon#read 3, iclass 23, count 2 2006.217.07:38:20.04#ibcon#about to read 4, iclass 23, count 2 2006.217.07:38:20.04#ibcon#read 4, iclass 23, count 2 2006.217.07:38:20.04#ibcon#about to read 5, iclass 23, count 2 2006.217.07:38:20.04#ibcon#read 5, iclass 23, count 2 2006.217.07:38:20.04#ibcon#about to read 6, iclass 23, count 2 2006.217.07:38:20.04#ibcon#read 6, iclass 23, count 2 2006.217.07:38:20.04#ibcon#end of sib2, iclass 23, count 2 2006.217.07:38:20.04#ibcon#*mode == 0, iclass 23, count 2 2006.217.07:38:20.04#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.217.07:38:20.04#ibcon#[25=AT07-06\r\n] 2006.217.07:38:20.04#ibcon#*before write, iclass 23, count 2 2006.217.07:38:20.04#ibcon#enter sib2, iclass 23, count 2 2006.217.07:38:20.04#ibcon#flushed, iclass 23, count 2 2006.217.07:38:20.04#ibcon#about to write, iclass 23, count 2 2006.217.07:38:20.04#ibcon#wrote, iclass 23, count 2 2006.217.07:38:20.04#ibcon#about to read 3, iclass 23, count 2 2006.217.07:38:20.07#ibcon#read 3, iclass 23, count 2 2006.217.07:38:20.07#ibcon#about to read 4, iclass 23, count 2 2006.217.07:38:20.07#ibcon#read 4, iclass 23, count 2 2006.217.07:38:20.07#ibcon#about to read 5, iclass 23, count 2 2006.217.07:38:20.07#ibcon#read 5, iclass 23, count 2 2006.217.07:38:20.07#ibcon#about to read 6, iclass 23, count 2 2006.217.07:38:20.07#ibcon#read 6, iclass 23, count 2 2006.217.07:38:20.07#ibcon#end of sib2, iclass 23, count 2 2006.217.07:38:20.07#ibcon#*after write, iclass 23, count 2 2006.217.07:38:20.07#ibcon#*before return 0, iclass 23, count 2 2006.217.07:38:20.07#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.217.07:38:20.07#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.217.07:38:20.07#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.217.07:38:20.07#ibcon#ireg 7 cls_cnt 0 2006.217.07:38:20.07#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.217.07:38:20.19#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.217.07:38:20.19#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.217.07:38:20.19#ibcon#enter wrdev, iclass 23, count 0 2006.217.07:38:20.19#ibcon#first serial, iclass 23, count 0 2006.217.07:38:20.19#ibcon#enter sib2, iclass 23, count 0 2006.217.07:38:20.19#ibcon#flushed, iclass 23, count 0 2006.217.07:38:20.19#ibcon#about to write, iclass 23, count 0 2006.217.07:38:20.19#ibcon#wrote, iclass 23, count 0 2006.217.07:38:20.19#ibcon#about to read 3, iclass 23, count 0 2006.217.07:38:20.21#ibcon#read 3, iclass 23, count 0 2006.217.07:38:20.21#ibcon#about to read 4, iclass 23, count 0 2006.217.07:38:20.21#ibcon#read 4, iclass 23, count 0 2006.217.07:38:20.21#ibcon#about to read 5, iclass 23, count 0 2006.217.07:38:20.21#ibcon#read 5, iclass 23, count 0 2006.217.07:38:20.21#ibcon#about to read 6, iclass 23, count 0 2006.217.07:38:20.21#ibcon#read 6, iclass 23, count 0 2006.217.07:38:20.21#ibcon#end of sib2, iclass 23, count 0 2006.217.07:38:20.21#ibcon#*mode == 0, iclass 23, count 0 2006.217.07:38:20.21#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.217.07:38:20.21#ibcon#[25=USB\r\n] 2006.217.07:38:20.21#ibcon#*before write, iclass 23, count 0 2006.217.07:38:20.21#ibcon#enter sib2, iclass 23, count 0 2006.217.07:38:20.21#ibcon#flushed, iclass 23, count 0 2006.217.07:38:20.21#ibcon#about to write, iclass 23, count 0 2006.217.07:38:20.21#ibcon#wrote, iclass 23, count 0 2006.217.07:38:20.21#ibcon#about to read 3, iclass 23, count 0 2006.217.07:38:20.24#ibcon#read 3, iclass 23, count 0 2006.217.07:38:20.24#ibcon#about to read 4, iclass 23, count 0 2006.217.07:38:20.24#ibcon#read 4, iclass 23, count 0 2006.217.07:38:20.24#ibcon#about to read 5, iclass 23, count 0 2006.217.07:38:20.24#ibcon#read 5, iclass 23, count 0 2006.217.07:38:20.24#ibcon#about to read 6, iclass 23, count 0 2006.217.07:38:20.24#ibcon#read 6, iclass 23, count 0 2006.217.07:38:20.24#ibcon#end of sib2, iclass 23, count 0 2006.217.07:38:20.24#ibcon#*after write, iclass 23, count 0 2006.217.07:38:20.24#ibcon#*before return 0, iclass 23, count 0 2006.217.07:38:20.24#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.217.07:38:20.24#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.217.07:38:20.24#ibcon#about to clear, iclass 23 cls_cnt 0 2006.217.07:38:20.24#ibcon#cleared, iclass 23 cls_cnt 0 2006.217.07:38:20.24$vc4f8/valo=8,852.99 2006.217.07:38:20.24#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.217.07:38:20.24#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.217.07:38:20.24#ibcon#ireg 17 cls_cnt 0 2006.217.07:38:20.24#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.217.07:38:20.24#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.217.07:38:20.24#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.217.07:38:20.24#ibcon#enter wrdev, iclass 25, count 0 2006.217.07:38:20.24#ibcon#first serial, iclass 25, count 0 2006.217.07:38:20.24#ibcon#enter sib2, iclass 25, count 0 2006.217.07:38:20.24#ibcon#flushed, iclass 25, count 0 2006.217.07:38:20.24#ibcon#about to write, iclass 25, count 0 2006.217.07:38:20.24#ibcon#wrote, iclass 25, count 0 2006.217.07:38:20.24#ibcon#about to read 3, iclass 25, count 0 2006.217.07:38:20.26#ibcon#read 3, iclass 25, count 0 2006.217.07:38:20.26#ibcon#about to read 4, iclass 25, count 0 2006.217.07:38:20.26#ibcon#read 4, iclass 25, count 0 2006.217.07:38:20.26#ibcon#about to read 5, iclass 25, count 0 2006.217.07:38:20.26#ibcon#read 5, iclass 25, count 0 2006.217.07:38:20.26#ibcon#about to read 6, iclass 25, count 0 2006.217.07:38:20.26#ibcon#read 6, iclass 25, count 0 2006.217.07:38:20.26#ibcon#end of sib2, iclass 25, count 0 2006.217.07:38:20.26#ibcon#*mode == 0, iclass 25, count 0 2006.217.07:38:20.26#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.217.07:38:20.26#ibcon#[26=FRQ=08,852.99\r\n] 2006.217.07:38:20.26#ibcon#*before write, iclass 25, count 0 2006.217.07:38:20.26#ibcon#enter sib2, iclass 25, count 0 2006.217.07:38:20.26#ibcon#flushed, iclass 25, count 0 2006.217.07:38:20.26#ibcon#about to write, iclass 25, count 0 2006.217.07:38:20.26#ibcon#wrote, iclass 25, count 0 2006.217.07:38:20.26#ibcon#about to read 3, iclass 25, count 0 2006.217.07:38:20.30#ibcon#read 3, iclass 25, count 0 2006.217.07:38:20.30#ibcon#about to read 4, iclass 25, count 0 2006.217.07:38:20.30#ibcon#read 4, iclass 25, count 0 2006.217.07:38:20.30#ibcon#about to read 5, iclass 25, count 0 2006.217.07:38:20.30#ibcon#read 5, iclass 25, count 0 2006.217.07:38:20.30#ibcon#about to read 6, iclass 25, count 0 2006.217.07:38:20.30#ibcon#read 6, iclass 25, count 0 2006.217.07:38:20.30#ibcon#end of sib2, iclass 25, count 0 2006.217.07:38:20.30#ibcon#*after write, iclass 25, count 0 2006.217.07:38:20.30#ibcon#*before return 0, iclass 25, count 0 2006.217.07:38:20.30#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.217.07:38:20.30#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.217.07:38:20.30#ibcon#about to clear, iclass 25 cls_cnt 0 2006.217.07:38:20.30#ibcon#cleared, iclass 25 cls_cnt 0 2006.217.07:38:20.30$vc4f8/va=8,7 2006.217.07:38:20.30#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.217.07:38:20.30#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.217.07:38:20.30#ibcon#ireg 11 cls_cnt 2 2006.217.07:38:20.30#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.217.07:38:20.36#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.217.07:38:20.36#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.217.07:38:20.36#ibcon#enter wrdev, iclass 27, count 2 2006.217.07:38:20.36#ibcon#first serial, iclass 27, count 2 2006.217.07:38:20.36#ibcon#enter sib2, iclass 27, count 2 2006.217.07:38:20.36#ibcon#flushed, iclass 27, count 2 2006.217.07:38:20.36#ibcon#about to write, iclass 27, count 2 2006.217.07:38:20.36#ibcon#wrote, iclass 27, count 2 2006.217.07:38:20.36#ibcon#about to read 3, iclass 27, count 2 2006.217.07:38:20.38#ibcon#read 3, iclass 27, count 2 2006.217.07:38:20.38#ibcon#about to read 4, iclass 27, count 2 2006.217.07:38:20.38#ibcon#read 4, iclass 27, count 2 2006.217.07:38:20.38#ibcon#about to read 5, iclass 27, count 2 2006.217.07:38:20.38#ibcon#read 5, iclass 27, count 2 2006.217.07:38:20.38#ibcon#about to read 6, iclass 27, count 2 2006.217.07:38:20.38#ibcon#read 6, iclass 27, count 2 2006.217.07:38:20.38#ibcon#end of sib2, iclass 27, count 2 2006.217.07:38:20.38#ibcon#*mode == 0, iclass 27, count 2 2006.217.07:38:20.38#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.217.07:38:20.38#ibcon#[25=AT08-07\r\n] 2006.217.07:38:20.38#ibcon#*before write, iclass 27, count 2 2006.217.07:38:20.38#ibcon#enter sib2, iclass 27, count 2 2006.217.07:38:20.38#ibcon#flushed, iclass 27, count 2 2006.217.07:38:20.38#ibcon#about to write, iclass 27, count 2 2006.217.07:38:20.38#ibcon#wrote, iclass 27, count 2 2006.217.07:38:20.38#ibcon#about to read 3, iclass 27, count 2 2006.217.07:38:20.41#ibcon#read 3, iclass 27, count 2 2006.217.07:38:20.41#ibcon#about to read 4, iclass 27, count 2 2006.217.07:38:20.41#ibcon#read 4, iclass 27, count 2 2006.217.07:38:20.41#ibcon#about to read 5, iclass 27, count 2 2006.217.07:38:20.41#ibcon#read 5, iclass 27, count 2 2006.217.07:38:20.41#ibcon#about to read 6, iclass 27, count 2 2006.217.07:38:20.41#ibcon#read 6, iclass 27, count 2 2006.217.07:38:20.41#ibcon#end of sib2, iclass 27, count 2 2006.217.07:38:20.41#ibcon#*after write, iclass 27, count 2 2006.217.07:38:20.41#ibcon#*before return 0, iclass 27, count 2 2006.217.07:38:20.41#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.217.07:38:20.41#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.217.07:38:20.41#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.217.07:38:20.41#ibcon#ireg 7 cls_cnt 0 2006.217.07:38:20.41#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.217.07:38:20.53#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.217.07:38:20.53#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.217.07:38:20.53#ibcon#enter wrdev, iclass 27, count 0 2006.217.07:38:20.53#ibcon#first serial, iclass 27, count 0 2006.217.07:38:20.53#ibcon#enter sib2, iclass 27, count 0 2006.217.07:38:20.53#ibcon#flushed, iclass 27, count 0 2006.217.07:38:20.53#ibcon#about to write, iclass 27, count 0 2006.217.07:38:20.53#ibcon#wrote, iclass 27, count 0 2006.217.07:38:20.53#ibcon#about to read 3, iclass 27, count 0 2006.217.07:38:20.55#ibcon#read 3, iclass 27, count 0 2006.217.07:38:20.55#ibcon#about to read 4, iclass 27, count 0 2006.217.07:38:20.55#ibcon#read 4, iclass 27, count 0 2006.217.07:38:20.55#ibcon#about to read 5, iclass 27, count 0 2006.217.07:38:20.55#ibcon#read 5, iclass 27, count 0 2006.217.07:38:20.55#ibcon#about to read 6, iclass 27, count 0 2006.217.07:38:20.55#ibcon#read 6, iclass 27, count 0 2006.217.07:38:20.55#ibcon#end of sib2, iclass 27, count 0 2006.217.07:38:20.55#ibcon#*mode == 0, iclass 27, count 0 2006.217.07:38:20.55#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.217.07:38:20.55#ibcon#[25=USB\r\n] 2006.217.07:38:20.55#ibcon#*before write, iclass 27, count 0 2006.217.07:38:20.55#ibcon#enter sib2, iclass 27, count 0 2006.217.07:38:20.55#ibcon#flushed, iclass 27, count 0 2006.217.07:38:20.55#ibcon#about to write, iclass 27, count 0 2006.217.07:38:20.55#ibcon#wrote, iclass 27, count 0 2006.217.07:38:20.55#ibcon#about to read 3, iclass 27, count 0 2006.217.07:38:20.58#ibcon#read 3, iclass 27, count 0 2006.217.07:38:20.58#ibcon#about to read 4, iclass 27, count 0 2006.217.07:38:20.58#ibcon#read 4, iclass 27, count 0 2006.217.07:38:20.58#ibcon#about to read 5, iclass 27, count 0 2006.217.07:38:20.58#ibcon#read 5, iclass 27, count 0 2006.217.07:38:20.58#ibcon#about to read 6, iclass 27, count 0 2006.217.07:38:20.58#ibcon#read 6, iclass 27, count 0 2006.217.07:38:20.58#ibcon#end of sib2, iclass 27, count 0 2006.217.07:38:20.58#ibcon#*after write, iclass 27, count 0 2006.217.07:38:20.58#ibcon#*before return 0, iclass 27, count 0 2006.217.07:38:20.58#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.217.07:38:20.58#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.217.07:38:20.58#ibcon#about to clear, iclass 27 cls_cnt 0 2006.217.07:38:20.58#ibcon#cleared, iclass 27 cls_cnt 0 2006.217.07:38:20.58$vc4f8/vblo=1,632.99 2006.217.07:38:20.58#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.217.07:38:20.58#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.217.07:38:20.58#ibcon#ireg 17 cls_cnt 0 2006.217.07:38:20.58#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.217.07:38:20.58#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.217.07:38:20.58#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.217.07:38:20.58#ibcon#enter wrdev, iclass 29, count 0 2006.217.07:38:20.58#ibcon#first serial, iclass 29, count 0 2006.217.07:38:20.58#ibcon#enter sib2, iclass 29, count 0 2006.217.07:38:20.58#ibcon#flushed, iclass 29, count 0 2006.217.07:38:20.58#ibcon#about to write, iclass 29, count 0 2006.217.07:38:20.58#ibcon#wrote, iclass 29, count 0 2006.217.07:38:20.58#ibcon#about to read 3, iclass 29, count 0 2006.217.07:38:20.60#ibcon#read 3, iclass 29, count 0 2006.217.07:38:20.60#ibcon#about to read 4, iclass 29, count 0 2006.217.07:38:20.60#ibcon#read 4, iclass 29, count 0 2006.217.07:38:20.60#ibcon#about to read 5, iclass 29, count 0 2006.217.07:38:20.60#ibcon#read 5, iclass 29, count 0 2006.217.07:38:20.60#ibcon#about to read 6, iclass 29, count 0 2006.217.07:38:20.60#ibcon#read 6, iclass 29, count 0 2006.217.07:38:20.60#ibcon#end of sib2, iclass 29, count 0 2006.217.07:38:20.60#ibcon#*mode == 0, iclass 29, count 0 2006.217.07:38:20.60#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.217.07:38:20.60#ibcon#[28=FRQ=01,632.99\r\n] 2006.217.07:38:20.60#ibcon#*before write, iclass 29, count 0 2006.217.07:38:20.60#ibcon#enter sib2, iclass 29, count 0 2006.217.07:38:20.60#ibcon#flushed, iclass 29, count 0 2006.217.07:38:20.60#ibcon#about to write, iclass 29, count 0 2006.217.07:38:20.60#ibcon#wrote, iclass 29, count 0 2006.217.07:38:20.60#ibcon#about to read 3, iclass 29, count 0 2006.217.07:38:20.64#ibcon#read 3, iclass 29, count 0 2006.217.07:38:20.64#ibcon#about to read 4, iclass 29, count 0 2006.217.07:38:20.64#ibcon#read 4, iclass 29, count 0 2006.217.07:38:20.64#ibcon#about to read 5, iclass 29, count 0 2006.217.07:38:20.64#ibcon#read 5, iclass 29, count 0 2006.217.07:38:20.64#ibcon#about to read 6, iclass 29, count 0 2006.217.07:38:20.64#ibcon#read 6, iclass 29, count 0 2006.217.07:38:20.64#ibcon#end of sib2, iclass 29, count 0 2006.217.07:38:20.64#ibcon#*after write, iclass 29, count 0 2006.217.07:38:20.64#ibcon#*before return 0, iclass 29, count 0 2006.217.07:38:20.64#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.217.07:38:20.64#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.217.07:38:20.64#ibcon#about to clear, iclass 29 cls_cnt 0 2006.217.07:38:20.64#ibcon#cleared, iclass 29 cls_cnt 0 2006.217.07:38:20.64$vc4f8/vb=1,4 2006.217.07:38:20.64#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.217.07:38:20.64#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.217.07:38:20.64#ibcon#ireg 11 cls_cnt 2 2006.217.07:38:20.64#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.217.07:38:20.64#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.217.07:38:20.64#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.217.07:38:20.64#ibcon#enter wrdev, iclass 31, count 2 2006.217.07:38:20.64#ibcon#first serial, iclass 31, count 2 2006.217.07:38:20.64#ibcon#enter sib2, iclass 31, count 2 2006.217.07:38:20.64#ibcon#flushed, iclass 31, count 2 2006.217.07:38:20.64#ibcon#about to write, iclass 31, count 2 2006.217.07:38:20.64#ibcon#wrote, iclass 31, count 2 2006.217.07:38:20.64#ibcon#about to read 3, iclass 31, count 2 2006.217.07:38:20.66#ibcon#read 3, iclass 31, count 2 2006.217.07:38:20.66#ibcon#about to read 4, iclass 31, count 2 2006.217.07:38:20.66#ibcon#read 4, iclass 31, count 2 2006.217.07:38:20.66#ibcon#about to read 5, iclass 31, count 2 2006.217.07:38:20.66#ibcon#read 5, iclass 31, count 2 2006.217.07:38:20.66#ibcon#about to read 6, iclass 31, count 2 2006.217.07:38:20.66#ibcon#read 6, iclass 31, count 2 2006.217.07:38:20.66#ibcon#end of sib2, iclass 31, count 2 2006.217.07:38:20.66#ibcon#*mode == 0, iclass 31, count 2 2006.217.07:38:20.66#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.217.07:38:20.66#ibcon#[27=AT01-04\r\n] 2006.217.07:38:20.66#ibcon#*before write, iclass 31, count 2 2006.217.07:38:20.66#ibcon#enter sib2, iclass 31, count 2 2006.217.07:38:20.66#ibcon#flushed, iclass 31, count 2 2006.217.07:38:20.66#ibcon#about to write, iclass 31, count 2 2006.217.07:38:20.66#ibcon#wrote, iclass 31, count 2 2006.217.07:38:20.66#ibcon#about to read 3, iclass 31, count 2 2006.217.07:38:20.69#ibcon#read 3, iclass 31, count 2 2006.217.07:38:20.69#ibcon#about to read 4, iclass 31, count 2 2006.217.07:38:20.69#ibcon#read 4, iclass 31, count 2 2006.217.07:38:20.69#ibcon#about to read 5, iclass 31, count 2 2006.217.07:38:20.69#ibcon#read 5, iclass 31, count 2 2006.217.07:38:20.69#ibcon#about to read 6, iclass 31, count 2 2006.217.07:38:20.69#ibcon#read 6, iclass 31, count 2 2006.217.07:38:20.69#ibcon#end of sib2, iclass 31, count 2 2006.217.07:38:20.69#ibcon#*after write, iclass 31, count 2 2006.217.07:38:20.69#ibcon#*before return 0, iclass 31, count 2 2006.217.07:38:20.69#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.217.07:38:20.69#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.217.07:38:20.69#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.217.07:38:20.69#ibcon#ireg 7 cls_cnt 0 2006.217.07:38:20.69#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.217.07:38:20.81#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.217.07:38:20.81#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.217.07:38:20.81#ibcon#enter wrdev, iclass 31, count 0 2006.217.07:38:20.81#ibcon#first serial, iclass 31, count 0 2006.217.07:38:20.81#ibcon#enter sib2, iclass 31, count 0 2006.217.07:38:20.81#ibcon#flushed, iclass 31, count 0 2006.217.07:38:20.81#ibcon#about to write, iclass 31, count 0 2006.217.07:38:20.81#ibcon#wrote, iclass 31, count 0 2006.217.07:38:20.81#ibcon#about to read 3, iclass 31, count 0 2006.217.07:38:20.83#ibcon#read 3, iclass 31, count 0 2006.217.07:38:20.83#ibcon#about to read 4, iclass 31, count 0 2006.217.07:38:20.83#ibcon#read 4, iclass 31, count 0 2006.217.07:38:20.83#ibcon#about to read 5, iclass 31, count 0 2006.217.07:38:20.83#ibcon#read 5, iclass 31, count 0 2006.217.07:38:20.83#ibcon#about to read 6, iclass 31, count 0 2006.217.07:38:20.83#ibcon#read 6, iclass 31, count 0 2006.217.07:38:20.83#ibcon#end of sib2, iclass 31, count 0 2006.217.07:38:20.83#ibcon#*mode == 0, iclass 31, count 0 2006.217.07:38:20.83#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.217.07:38:20.83#ibcon#[27=USB\r\n] 2006.217.07:38:20.83#ibcon#*before write, iclass 31, count 0 2006.217.07:38:20.83#ibcon#enter sib2, iclass 31, count 0 2006.217.07:38:20.83#ibcon#flushed, iclass 31, count 0 2006.217.07:38:20.83#ibcon#about to write, iclass 31, count 0 2006.217.07:38:20.83#ibcon#wrote, iclass 31, count 0 2006.217.07:38:20.83#ibcon#about to read 3, iclass 31, count 0 2006.217.07:38:20.86#ibcon#read 3, iclass 31, count 0 2006.217.07:38:20.86#ibcon#about to read 4, iclass 31, count 0 2006.217.07:38:20.86#ibcon#read 4, iclass 31, count 0 2006.217.07:38:20.86#ibcon#about to read 5, iclass 31, count 0 2006.217.07:38:20.86#ibcon#read 5, iclass 31, count 0 2006.217.07:38:20.86#ibcon#about to read 6, iclass 31, count 0 2006.217.07:38:20.86#ibcon#read 6, iclass 31, count 0 2006.217.07:38:20.86#ibcon#end of sib2, iclass 31, count 0 2006.217.07:38:20.86#ibcon#*after write, iclass 31, count 0 2006.217.07:38:20.86#ibcon#*before return 0, iclass 31, count 0 2006.217.07:38:20.86#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.217.07:38:20.86#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.217.07:38:20.86#ibcon#about to clear, iclass 31 cls_cnt 0 2006.217.07:38:20.86#ibcon#cleared, iclass 31 cls_cnt 0 2006.217.07:38:20.86$vc4f8/vblo=2,640.99 2006.217.07:38:20.86#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.217.07:38:20.86#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.217.07:38:20.86#ibcon#ireg 17 cls_cnt 0 2006.217.07:38:20.86#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.217.07:38:20.86#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.217.07:38:20.86#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.217.07:38:20.86#ibcon#enter wrdev, iclass 33, count 0 2006.217.07:38:20.86#ibcon#first serial, iclass 33, count 0 2006.217.07:38:20.86#ibcon#enter sib2, iclass 33, count 0 2006.217.07:38:20.86#ibcon#flushed, iclass 33, count 0 2006.217.07:38:20.86#ibcon#about to write, iclass 33, count 0 2006.217.07:38:20.86#ibcon#wrote, iclass 33, count 0 2006.217.07:38:20.86#ibcon#about to read 3, iclass 33, count 0 2006.217.07:38:20.88#ibcon#read 3, iclass 33, count 0 2006.217.07:38:20.88#ibcon#about to read 4, iclass 33, count 0 2006.217.07:38:20.88#ibcon#read 4, iclass 33, count 0 2006.217.07:38:20.88#ibcon#about to read 5, iclass 33, count 0 2006.217.07:38:20.88#ibcon#read 5, iclass 33, count 0 2006.217.07:38:20.88#ibcon#about to read 6, iclass 33, count 0 2006.217.07:38:20.88#ibcon#read 6, iclass 33, count 0 2006.217.07:38:20.88#ibcon#end of sib2, iclass 33, count 0 2006.217.07:38:20.88#ibcon#*mode == 0, iclass 33, count 0 2006.217.07:38:20.88#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.217.07:38:20.88#ibcon#[28=FRQ=02,640.99\r\n] 2006.217.07:38:20.88#ibcon#*before write, iclass 33, count 0 2006.217.07:38:20.88#ibcon#enter sib2, iclass 33, count 0 2006.217.07:38:20.88#ibcon#flushed, iclass 33, count 0 2006.217.07:38:20.88#ibcon#about to write, iclass 33, count 0 2006.217.07:38:20.88#ibcon#wrote, iclass 33, count 0 2006.217.07:38:20.88#ibcon#about to read 3, iclass 33, count 0 2006.217.07:38:20.92#ibcon#read 3, iclass 33, count 0 2006.217.07:38:20.92#ibcon#about to read 4, iclass 33, count 0 2006.217.07:38:20.92#ibcon#read 4, iclass 33, count 0 2006.217.07:38:20.92#ibcon#about to read 5, iclass 33, count 0 2006.217.07:38:20.92#ibcon#read 5, iclass 33, count 0 2006.217.07:38:20.92#ibcon#about to read 6, iclass 33, count 0 2006.217.07:38:20.92#ibcon#read 6, iclass 33, count 0 2006.217.07:38:20.92#ibcon#end of sib2, iclass 33, count 0 2006.217.07:38:20.92#ibcon#*after write, iclass 33, count 0 2006.217.07:38:20.92#ibcon#*before return 0, iclass 33, count 0 2006.217.07:38:20.92#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.217.07:38:20.92#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.217.07:38:20.92#ibcon#about to clear, iclass 33 cls_cnt 0 2006.217.07:38:20.92#ibcon#cleared, iclass 33 cls_cnt 0 2006.217.07:38:20.92$vc4f8/vb=2,4 2006.217.07:38:20.92#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.217.07:38:20.92#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.217.07:38:20.92#ibcon#ireg 11 cls_cnt 2 2006.217.07:38:20.92#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.217.07:38:20.98#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.217.07:38:20.98#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.217.07:38:20.98#ibcon#enter wrdev, iclass 35, count 2 2006.217.07:38:20.98#ibcon#first serial, iclass 35, count 2 2006.217.07:38:20.98#ibcon#enter sib2, iclass 35, count 2 2006.217.07:38:20.98#ibcon#flushed, iclass 35, count 2 2006.217.07:38:20.98#ibcon#about to write, iclass 35, count 2 2006.217.07:38:20.98#ibcon#wrote, iclass 35, count 2 2006.217.07:38:20.98#ibcon#about to read 3, iclass 35, count 2 2006.217.07:38:21.00#ibcon#read 3, iclass 35, count 2 2006.217.07:38:21.00#ibcon#about to read 4, iclass 35, count 2 2006.217.07:38:21.00#ibcon#read 4, iclass 35, count 2 2006.217.07:38:21.00#ibcon#about to read 5, iclass 35, count 2 2006.217.07:38:21.00#ibcon#read 5, iclass 35, count 2 2006.217.07:38:21.00#ibcon#about to read 6, iclass 35, count 2 2006.217.07:38:21.00#ibcon#read 6, iclass 35, count 2 2006.217.07:38:21.00#ibcon#end of sib2, iclass 35, count 2 2006.217.07:38:21.00#ibcon#*mode == 0, iclass 35, count 2 2006.217.07:38:21.00#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.217.07:38:21.00#ibcon#[27=AT02-04\r\n] 2006.217.07:38:21.00#ibcon#*before write, iclass 35, count 2 2006.217.07:38:21.00#ibcon#enter sib2, iclass 35, count 2 2006.217.07:38:21.00#ibcon#flushed, iclass 35, count 2 2006.217.07:38:21.00#ibcon#about to write, iclass 35, count 2 2006.217.07:38:21.00#ibcon#wrote, iclass 35, count 2 2006.217.07:38:21.00#ibcon#about to read 3, iclass 35, count 2 2006.217.07:38:21.03#ibcon#read 3, iclass 35, count 2 2006.217.07:38:21.03#ibcon#about to read 4, iclass 35, count 2 2006.217.07:38:21.03#ibcon#read 4, iclass 35, count 2 2006.217.07:38:21.03#ibcon#about to read 5, iclass 35, count 2 2006.217.07:38:21.03#ibcon#read 5, iclass 35, count 2 2006.217.07:38:21.03#ibcon#about to read 6, iclass 35, count 2 2006.217.07:38:21.03#ibcon#read 6, iclass 35, count 2 2006.217.07:38:21.03#ibcon#end of sib2, iclass 35, count 2 2006.217.07:38:21.03#ibcon#*after write, iclass 35, count 2 2006.217.07:38:21.03#ibcon#*before return 0, iclass 35, count 2 2006.217.07:38:21.03#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.217.07:38:21.03#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.217.07:38:21.03#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.217.07:38:21.03#ibcon#ireg 7 cls_cnt 0 2006.217.07:38:21.03#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.217.07:38:21.15#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.217.07:38:21.15#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.217.07:38:21.15#ibcon#enter wrdev, iclass 35, count 0 2006.217.07:38:21.15#ibcon#first serial, iclass 35, count 0 2006.217.07:38:21.15#ibcon#enter sib2, iclass 35, count 0 2006.217.07:38:21.15#ibcon#flushed, iclass 35, count 0 2006.217.07:38:21.15#ibcon#about to write, iclass 35, count 0 2006.217.07:38:21.15#ibcon#wrote, iclass 35, count 0 2006.217.07:38:21.15#ibcon#about to read 3, iclass 35, count 0 2006.217.07:38:21.17#ibcon#read 3, iclass 35, count 0 2006.217.07:38:21.17#ibcon#about to read 4, iclass 35, count 0 2006.217.07:38:21.17#ibcon#read 4, iclass 35, count 0 2006.217.07:38:21.17#ibcon#about to read 5, iclass 35, count 0 2006.217.07:38:21.17#ibcon#read 5, iclass 35, count 0 2006.217.07:38:21.17#ibcon#about to read 6, iclass 35, count 0 2006.217.07:38:21.17#ibcon#read 6, iclass 35, count 0 2006.217.07:38:21.17#ibcon#end of sib2, iclass 35, count 0 2006.217.07:38:21.17#ibcon#*mode == 0, iclass 35, count 0 2006.217.07:38:21.17#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.217.07:38:21.17#ibcon#[27=USB\r\n] 2006.217.07:38:21.17#ibcon#*before write, iclass 35, count 0 2006.217.07:38:21.17#ibcon#enter sib2, iclass 35, count 0 2006.217.07:38:21.17#ibcon#flushed, iclass 35, count 0 2006.217.07:38:21.17#ibcon#about to write, iclass 35, count 0 2006.217.07:38:21.17#ibcon#wrote, iclass 35, count 0 2006.217.07:38:21.17#ibcon#about to read 3, iclass 35, count 0 2006.217.07:38:21.20#ibcon#read 3, iclass 35, count 0 2006.217.07:38:21.20#ibcon#about to read 4, iclass 35, count 0 2006.217.07:38:21.20#ibcon#read 4, iclass 35, count 0 2006.217.07:38:21.20#ibcon#about to read 5, iclass 35, count 0 2006.217.07:38:21.20#ibcon#read 5, iclass 35, count 0 2006.217.07:38:21.20#ibcon#about to read 6, iclass 35, count 0 2006.217.07:38:21.20#ibcon#read 6, iclass 35, count 0 2006.217.07:38:21.20#ibcon#end of sib2, iclass 35, count 0 2006.217.07:38:21.20#ibcon#*after write, iclass 35, count 0 2006.217.07:38:21.20#ibcon#*before return 0, iclass 35, count 0 2006.217.07:38:21.20#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.217.07:38:21.20#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.217.07:38:21.20#ibcon#about to clear, iclass 35 cls_cnt 0 2006.217.07:38:21.20#ibcon#cleared, iclass 35 cls_cnt 0 2006.217.07:38:21.20$vc4f8/vblo=3,656.99 2006.217.07:38:21.20#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.217.07:38:21.20#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.217.07:38:21.20#ibcon#ireg 17 cls_cnt 0 2006.217.07:38:21.20#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.217.07:38:21.20#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.217.07:38:21.20#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.217.07:38:21.20#ibcon#enter wrdev, iclass 37, count 0 2006.217.07:38:21.20#ibcon#first serial, iclass 37, count 0 2006.217.07:38:21.20#ibcon#enter sib2, iclass 37, count 0 2006.217.07:38:21.20#ibcon#flushed, iclass 37, count 0 2006.217.07:38:21.20#ibcon#about to write, iclass 37, count 0 2006.217.07:38:21.20#ibcon#wrote, iclass 37, count 0 2006.217.07:38:21.20#ibcon#about to read 3, iclass 37, count 0 2006.217.07:38:21.22#ibcon#read 3, iclass 37, count 0 2006.217.07:38:21.22#ibcon#about to read 4, iclass 37, count 0 2006.217.07:38:21.22#ibcon#read 4, iclass 37, count 0 2006.217.07:38:21.22#ibcon#about to read 5, iclass 37, count 0 2006.217.07:38:21.22#ibcon#read 5, iclass 37, count 0 2006.217.07:38:21.22#ibcon#about to read 6, iclass 37, count 0 2006.217.07:38:21.22#ibcon#read 6, iclass 37, count 0 2006.217.07:38:21.22#ibcon#end of sib2, iclass 37, count 0 2006.217.07:38:21.22#ibcon#*mode == 0, iclass 37, count 0 2006.217.07:38:21.22#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.217.07:38:21.22#ibcon#[28=FRQ=03,656.99\r\n] 2006.217.07:38:21.22#ibcon#*before write, iclass 37, count 0 2006.217.07:38:21.22#ibcon#enter sib2, iclass 37, count 0 2006.217.07:38:21.22#ibcon#flushed, iclass 37, count 0 2006.217.07:38:21.22#ibcon#about to write, iclass 37, count 0 2006.217.07:38:21.22#ibcon#wrote, iclass 37, count 0 2006.217.07:38:21.22#ibcon#about to read 3, iclass 37, count 0 2006.217.07:38:21.26#ibcon#read 3, iclass 37, count 0 2006.217.07:38:21.26#ibcon#about to read 4, iclass 37, count 0 2006.217.07:38:21.26#ibcon#read 4, iclass 37, count 0 2006.217.07:38:21.26#ibcon#about to read 5, iclass 37, count 0 2006.217.07:38:21.26#ibcon#read 5, iclass 37, count 0 2006.217.07:38:21.26#ibcon#about to read 6, iclass 37, count 0 2006.217.07:38:21.26#ibcon#read 6, iclass 37, count 0 2006.217.07:38:21.26#ibcon#end of sib2, iclass 37, count 0 2006.217.07:38:21.26#ibcon#*after write, iclass 37, count 0 2006.217.07:38:21.26#ibcon#*before return 0, iclass 37, count 0 2006.217.07:38:21.26#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.217.07:38:21.26#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.217.07:38:21.26#ibcon#about to clear, iclass 37 cls_cnt 0 2006.217.07:38:21.26#ibcon#cleared, iclass 37 cls_cnt 0 2006.217.07:38:21.26$vc4f8/vb=3,4 2006.217.07:38:21.26#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.217.07:38:21.26#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.217.07:38:21.26#ibcon#ireg 11 cls_cnt 2 2006.217.07:38:21.26#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.217.07:38:21.32#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.217.07:38:21.32#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.217.07:38:21.32#ibcon#enter wrdev, iclass 39, count 2 2006.217.07:38:21.32#ibcon#first serial, iclass 39, count 2 2006.217.07:38:21.32#ibcon#enter sib2, iclass 39, count 2 2006.217.07:38:21.32#ibcon#flushed, iclass 39, count 2 2006.217.07:38:21.32#ibcon#about to write, iclass 39, count 2 2006.217.07:38:21.32#ibcon#wrote, iclass 39, count 2 2006.217.07:38:21.32#ibcon#about to read 3, iclass 39, count 2 2006.217.07:38:21.34#ibcon#read 3, iclass 39, count 2 2006.217.07:38:21.34#ibcon#about to read 4, iclass 39, count 2 2006.217.07:38:21.34#ibcon#read 4, iclass 39, count 2 2006.217.07:38:21.34#ibcon#about to read 5, iclass 39, count 2 2006.217.07:38:21.34#ibcon#read 5, iclass 39, count 2 2006.217.07:38:21.34#ibcon#about to read 6, iclass 39, count 2 2006.217.07:38:21.34#ibcon#read 6, iclass 39, count 2 2006.217.07:38:21.34#ibcon#end of sib2, iclass 39, count 2 2006.217.07:38:21.34#ibcon#*mode == 0, iclass 39, count 2 2006.217.07:38:21.34#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.217.07:38:21.34#ibcon#[27=AT03-04\r\n] 2006.217.07:38:21.34#ibcon#*before write, iclass 39, count 2 2006.217.07:38:21.34#ibcon#enter sib2, iclass 39, count 2 2006.217.07:38:21.34#ibcon#flushed, iclass 39, count 2 2006.217.07:38:21.34#ibcon#about to write, iclass 39, count 2 2006.217.07:38:21.34#ibcon#wrote, iclass 39, count 2 2006.217.07:38:21.34#ibcon#about to read 3, iclass 39, count 2 2006.217.07:38:21.37#ibcon#read 3, iclass 39, count 2 2006.217.07:38:21.37#ibcon#about to read 4, iclass 39, count 2 2006.217.07:38:21.37#ibcon#read 4, iclass 39, count 2 2006.217.07:38:21.37#ibcon#about to read 5, iclass 39, count 2 2006.217.07:38:21.37#ibcon#read 5, iclass 39, count 2 2006.217.07:38:21.37#ibcon#about to read 6, iclass 39, count 2 2006.217.07:38:21.37#ibcon#read 6, iclass 39, count 2 2006.217.07:38:21.37#ibcon#end of sib2, iclass 39, count 2 2006.217.07:38:21.37#ibcon#*after write, iclass 39, count 2 2006.217.07:38:21.37#ibcon#*before return 0, iclass 39, count 2 2006.217.07:38:21.37#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.217.07:38:21.37#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.217.07:38:21.37#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.217.07:38:21.37#ibcon#ireg 7 cls_cnt 0 2006.217.07:38:21.37#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.217.07:38:21.49#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.217.07:38:21.49#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.217.07:38:21.49#ibcon#enter wrdev, iclass 39, count 0 2006.217.07:38:21.49#ibcon#first serial, iclass 39, count 0 2006.217.07:38:21.49#ibcon#enter sib2, iclass 39, count 0 2006.217.07:38:21.49#ibcon#flushed, iclass 39, count 0 2006.217.07:38:21.49#ibcon#about to write, iclass 39, count 0 2006.217.07:38:21.49#ibcon#wrote, iclass 39, count 0 2006.217.07:38:21.49#ibcon#about to read 3, iclass 39, count 0 2006.217.07:38:21.51#ibcon#read 3, iclass 39, count 0 2006.217.07:38:21.51#ibcon#about to read 4, iclass 39, count 0 2006.217.07:38:21.51#ibcon#read 4, iclass 39, count 0 2006.217.07:38:21.51#ibcon#about to read 5, iclass 39, count 0 2006.217.07:38:21.51#ibcon#read 5, iclass 39, count 0 2006.217.07:38:21.51#ibcon#about to read 6, iclass 39, count 0 2006.217.07:38:21.51#ibcon#read 6, iclass 39, count 0 2006.217.07:38:21.51#ibcon#end of sib2, iclass 39, count 0 2006.217.07:38:21.51#ibcon#*mode == 0, iclass 39, count 0 2006.217.07:38:21.51#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.217.07:38:21.51#ibcon#[27=USB\r\n] 2006.217.07:38:21.51#ibcon#*before write, iclass 39, count 0 2006.217.07:38:21.51#ibcon#enter sib2, iclass 39, count 0 2006.217.07:38:21.51#ibcon#flushed, iclass 39, count 0 2006.217.07:38:21.51#ibcon#about to write, iclass 39, count 0 2006.217.07:38:21.51#ibcon#wrote, iclass 39, count 0 2006.217.07:38:21.51#ibcon#about to read 3, iclass 39, count 0 2006.217.07:38:21.54#ibcon#read 3, iclass 39, count 0 2006.217.07:38:21.54#ibcon#about to read 4, iclass 39, count 0 2006.217.07:38:21.54#ibcon#read 4, iclass 39, count 0 2006.217.07:38:21.54#ibcon#about to read 5, iclass 39, count 0 2006.217.07:38:21.54#ibcon#read 5, iclass 39, count 0 2006.217.07:38:21.54#ibcon#about to read 6, iclass 39, count 0 2006.217.07:38:21.54#ibcon#read 6, iclass 39, count 0 2006.217.07:38:21.54#ibcon#end of sib2, iclass 39, count 0 2006.217.07:38:21.54#ibcon#*after write, iclass 39, count 0 2006.217.07:38:21.54#ibcon#*before return 0, iclass 39, count 0 2006.217.07:38:21.54#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.217.07:38:21.54#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.217.07:38:21.54#ibcon#about to clear, iclass 39 cls_cnt 0 2006.217.07:38:21.54#ibcon#cleared, iclass 39 cls_cnt 0 2006.217.07:38:21.54$vc4f8/vblo=4,712.99 2006.217.07:38:21.54#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.217.07:38:21.54#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.217.07:38:21.54#ibcon#ireg 17 cls_cnt 0 2006.217.07:38:21.54#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.217.07:38:21.54#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.217.07:38:21.54#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.217.07:38:21.54#ibcon#enter wrdev, iclass 3, count 0 2006.217.07:38:21.54#ibcon#first serial, iclass 3, count 0 2006.217.07:38:21.54#ibcon#enter sib2, iclass 3, count 0 2006.217.07:38:21.54#ibcon#flushed, iclass 3, count 0 2006.217.07:38:21.54#ibcon#about to write, iclass 3, count 0 2006.217.07:38:21.54#ibcon#wrote, iclass 3, count 0 2006.217.07:38:21.54#ibcon#about to read 3, iclass 3, count 0 2006.217.07:38:21.56#ibcon#read 3, iclass 3, count 0 2006.217.07:38:21.56#ibcon#about to read 4, iclass 3, count 0 2006.217.07:38:21.56#ibcon#read 4, iclass 3, count 0 2006.217.07:38:21.56#ibcon#about to read 5, iclass 3, count 0 2006.217.07:38:21.56#ibcon#read 5, iclass 3, count 0 2006.217.07:38:21.56#ibcon#about to read 6, iclass 3, count 0 2006.217.07:38:21.56#ibcon#read 6, iclass 3, count 0 2006.217.07:38:21.56#ibcon#end of sib2, iclass 3, count 0 2006.217.07:38:21.56#ibcon#*mode == 0, iclass 3, count 0 2006.217.07:38:21.56#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.217.07:38:21.56#ibcon#[28=FRQ=04,712.99\r\n] 2006.217.07:38:21.56#ibcon#*before write, iclass 3, count 0 2006.217.07:38:21.56#ibcon#enter sib2, iclass 3, count 0 2006.217.07:38:21.56#ibcon#flushed, iclass 3, count 0 2006.217.07:38:21.56#ibcon#about to write, iclass 3, count 0 2006.217.07:38:21.56#ibcon#wrote, iclass 3, count 0 2006.217.07:38:21.56#ibcon#about to read 3, iclass 3, count 0 2006.217.07:38:21.60#ibcon#read 3, iclass 3, count 0 2006.217.07:38:21.60#ibcon#about to read 4, iclass 3, count 0 2006.217.07:38:21.60#ibcon#read 4, iclass 3, count 0 2006.217.07:38:21.60#ibcon#about to read 5, iclass 3, count 0 2006.217.07:38:21.60#ibcon#read 5, iclass 3, count 0 2006.217.07:38:21.60#ibcon#about to read 6, iclass 3, count 0 2006.217.07:38:21.60#ibcon#read 6, iclass 3, count 0 2006.217.07:38:21.60#ibcon#end of sib2, iclass 3, count 0 2006.217.07:38:21.60#ibcon#*after write, iclass 3, count 0 2006.217.07:38:21.60#ibcon#*before return 0, iclass 3, count 0 2006.217.07:38:21.60#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.217.07:38:21.60#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.217.07:38:21.60#ibcon#about to clear, iclass 3 cls_cnt 0 2006.217.07:38:21.60#ibcon#cleared, iclass 3 cls_cnt 0 2006.217.07:38:21.60$vc4f8/vb=4,4 2006.217.07:38:21.60#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.217.07:38:21.60#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.217.07:38:21.60#ibcon#ireg 11 cls_cnt 2 2006.217.07:38:21.60#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.217.07:38:21.66#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.217.07:38:21.66#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.217.07:38:21.66#ibcon#enter wrdev, iclass 5, count 2 2006.217.07:38:21.66#ibcon#first serial, iclass 5, count 2 2006.217.07:38:21.66#ibcon#enter sib2, iclass 5, count 2 2006.217.07:38:21.66#ibcon#flushed, iclass 5, count 2 2006.217.07:38:21.66#ibcon#about to write, iclass 5, count 2 2006.217.07:38:21.66#ibcon#wrote, iclass 5, count 2 2006.217.07:38:21.66#ibcon#about to read 3, iclass 5, count 2 2006.217.07:38:21.68#ibcon#read 3, iclass 5, count 2 2006.217.07:38:21.68#ibcon#about to read 4, iclass 5, count 2 2006.217.07:38:21.68#ibcon#read 4, iclass 5, count 2 2006.217.07:38:21.68#ibcon#about to read 5, iclass 5, count 2 2006.217.07:38:21.68#ibcon#read 5, iclass 5, count 2 2006.217.07:38:21.68#ibcon#about to read 6, iclass 5, count 2 2006.217.07:38:21.68#ibcon#read 6, iclass 5, count 2 2006.217.07:38:21.68#ibcon#end of sib2, iclass 5, count 2 2006.217.07:38:21.68#ibcon#*mode == 0, iclass 5, count 2 2006.217.07:38:21.68#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.217.07:38:21.68#ibcon#[27=AT04-04\r\n] 2006.217.07:38:21.68#ibcon#*before write, iclass 5, count 2 2006.217.07:38:21.68#ibcon#enter sib2, iclass 5, count 2 2006.217.07:38:21.68#ibcon#flushed, iclass 5, count 2 2006.217.07:38:21.68#ibcon#about to write, iclass 5, count 2 2006.217.07:38:21.68#ibcon#wrote, iclass 5, count 2 2006.217.07:38:21.68#ibcon#about to read 3, iclass 5, count 2 2006.217.07:38:21.71#ibcon#read 3, iclass 5, count 2 2006.217.07:38:21.71#ibcon#about to read 4, iclass 5, count 2 2006.217.07:38:21.71#ibcon#read 4, iclass 5, count 2 2006.217.07:38:21.71#ibcon#about to read 5, iclass 5, count 2 2006.217.07:38:21.71#ibcon#read 5, iclass 5, count 2 2006.217.07:38:21.71#ibcon#about to read 6, iclass 5, count 2 2006.217.07:38:21.71#ibcon#read 6, iclass 5, count 2 2006.217.07:38:21.71#ibcon#end of sib2, iclass 5, count 2 2006.217.07:38:21.71#ibcon#*after write, iclass 5, count 2 2006.217.07:38:21.71#ibcon#*before return 0, iclass 5, count 2 2006.217.07:38:21.71#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.217.07:38:21.71#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.217.07:38:21.71#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.217.07:38:21.71#ibcon#ireg 7 cls_cnt 0 2006.217.07:38:21.71#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.217.07:38:21.83#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.217.07:38:21.83#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.217.07:38:21.83#ibcon#enter wrdev, iclass 5, count 0 2006.217.07:38:21.83#ibcon#first serial, iclass 5, count 0 2006.217.07:38:21.83#ibcon#enter sib2, iclass 5, count 0 2006.217.07:38:21.83#ibcon#flushed, iclass 5, count 0 2006.217.07:38:21.83#ibcon#about to write, iclass 5, count 0 2006.217.07:38:21.83#ibcon#wrote, iclass 5, count 0 2006.217.07:38:21.83#ibcon#about to read 3, iclass 5, count 0 2006.217.07:38:21.85#ibcon#read 3, iclass 5, count 0 2006.217.07:38:21.85#ibcon#about to read 4, iclass 5, count 0 2006.217.07:38:21.85#ibcon#read 4, iclass 5, count 0 2006.217.07:38:21.85#ibcon#about to read 5, iclass 5, count 0 2006.217.07:38:21.85#ibcon#read 5, iclass 5, count 0 2006.217.07:38:21.85#ibcon#about to read 6, iclass 5, count 0 2006.217.07:38:21.85#ibcon#read 6, iclass 5, count 0 2006.217.07:38:21.85#ibcon#end of sib2, iclass 5, count 0 2006.217.07:38:21.85#ibcon#*mode == 0, iclass 5, count 0 2006.217.07:38:21.85#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.217.07:38:21.85#ibcon#[27=USB\r\n] 2006.217.07:38:21.85#ibcon#*before write, iclass 5, count 0 2006.217.07:38:21.85#ibcon#enter sib2, iclass 5, count 0 2006.217.07:38:21.85#ibcon#flushed, iclass 5, count 0 2006.217.07:38:21.85#ibcon#about to write, iclass 5, count 0 2006.217.07:38:21.85#ibcon#wrote, iclass 5, count 0 2006.217.07:38:21.85#ibcon#about to read 3, iclass 5, count 0 2006.217.07:38:21.88#ibcon#read 3, iclass 5, count 0 2006.217.07:38:21.88#ibcon#about to read 4, iclass 5, count 0 2006.217.07:38:21.88#ibcon#read 4, iclass 5, count 0 2006.217.07:38:21.88#ibcon#about to read 5, iclass 5, count 0 2006.217.07:38:21.88#ibcon#read 5, iclass 5, count 0 2006.217.07:38:21.88#ibcon#about to read 6, iclass 5, count 0 2006.217.07:38:21.88#ibcon#read 6, iclass 5, count 0 2006.217.07:38:21.88#ibcon#end of sib2, iclass 5, count 0 2006.217.07:38:21.88#ibcon#*after write, iclass 5, count 0 2006.217.07:38:21.88#ibcon#*before return 0, iclass 5, count 0 2006.217.07:38:21.88#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.217.07:38:21.88#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.217.07:38:21.88#ibcon#about to clear, iclass 5 cls_cnt 0 2006.217.07:38:21.88#ibcon#cleared, iclass 5 cls_cnt 0 2006.217.07:38:21.88$vc4f8/vblo=5,744.99 2006.217.07:38:21.88#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.217.07:38:21.88#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.217.07:38:21.88#ibcon#ireg 17 cls_cnt 0 2006.217.07:38:21.88#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.217.07:38:21.88#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.217.07:38:21.88#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.217.07:38:21.88#ibcon#enter wrdev, iclass 7, count 0 2006.217.07:38:21.88#ibcon#first serial, iclass 7, count 0 2006.217.07:38:21.88#ibcon#enter sib2, iclass 7, count 0 2006.217.07:38:21.88#ibcon#flushed, iclass 7, count 0 2006.217.07:38:21.88#ibcon#about to write, iclass 7, count 0 2006.217.07:38:21.88#ibcon#wrote, iclass 7, count 0 2006.217.07:38:21.88#ibcon#about to read 3, iclass 7, count 0 2006.217.07:38:21.90#ibcon#read 3, iclass 7, count 0 2006.217.07:38:21.90#ibcon#about to read 4, iclass 7, count 0 2006.217.07:38:21.90#ibcon#read 4, iclass 7, count 0 2006.217.07:38:21.90#ibcon#about to read 5, iclass 7, count 0 2006.217.07:38:21.90#ibcon#read 5, iclass 7, count 0 2006.217.07:38:21.90#ibcon#about to read 6, iclass 7, count 0 2006.217.07:38:21.90#ibcon#read 6, iclass 7, count 0 2006.217.07:38:21.90#ibcon#end of sib2, iclass 7, count 0 2006.217.07:38:21.90#ibcon#*mode == 0, iclass 7, count 0 2006.217.07:38:21.90#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.217.07:38:21.90#ibcon#[28=FRQ=05,744.99\r\n] 2006.217.07:38:21.90#ibcon#*before write, iclass 7, count 0 2006.217.07:38:21.90#ibcon#enter sib2, iclass 7, count 0 2006.217.07:38:21.90#ibcon#flushed, iclass 7, count 0 2006.217.07:38:21.90#ibcon#about to write, iclass 7, count 0 2006.217.07:38:21.90#ibcon#wrote, iclass 7, count 0 2006.217.07:38:21.90#ibcon#about to read 3, iclass 7, count 0 2006.217.07:38:21.94#ibcon#read 3, iclass 7, count 0 2006.217.07:38:21.94#ibcon#about to read 4, iclass 7, count 0 2006.217.07:38:21.94#ibcon#read 4, iclass 7, count 0 2006.217.07:38:21.94#ibcon#about to read 5, iclass 7, count 0 2006.217.07:38:21.94#ibcon#read 5, iclass 7, count 0 2006.217.07:38:21.94#ibcon#about to read 6, iclass 7, count 0 2006.217.07:38:21.94#ibcon#read 6, iclass 7, count 0 2006.217.07:38:21.94#ibcon#end of sib2, iclass 7, count 0 2006.217.07:38:21.94#ibcon#*after write, iclass 7, count 0 2006.217.07:38:21.94#ibcon#*before return 0, iclass 7, count 0 2006.217.07:38:21.94#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.217.07:38:21.94#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.217.07:38:21.94#ibcon#about to clear, iclass 7 cls_cnt 0 2006.217.07:38:21.94#ibcon#cleared, iclass 7 cls_cnt 0 2006.217.07:38:21.94$vc4f8/vb=5,4 2006.217.07:38:21.94#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.217.07:38:21.94#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.217.07:38:21.94#ibcon#ireg 11 cls_cnt 2 2006.217.07:38:21.94#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.217.07:38:22.00#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.217.07:38:22.00#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.217.07:38:22.00#ibcon#enter wrdev, iclass 11, count 2 2006.217.07:38:22.00#ibcon#first serial, iclass 11, count 2 2006.217.07:38:22.00#ibcon#enter sib2, iclass 11, count 2 2006.217.07:38:22.00#ibcon#flushed, iclass 11, count 2 2006.217.07:38:22.00#ibcon#about to write, iclass 11, count 2 2006.217.07:38:22.00#ibcon#wrote, iclass 11, count 2 2006.217.07:38:22.00#ibcon#about to read 3, iclass 11, count 2 2006.217.07:38:22.02#ibcon#read 3, iclass 11, count 2 2006.217.07:38:22.02#ibcon#about to read 4, iclass 11, count 2 2006.217.07:38:22.02#ibcon#read 4, iclass 11, count 2 2006.217.07:38:22.02#ibcon#about to read 5, iclass 11, count 2 2006.217.07:38:22.02#ibcon#read 5, iclass 11, count 2 2006.217.07:38:22.02#ibcon#about to read 6, iclass 11, count 2 2006.217.07:38:22.02#ibcon#read 6, iclass 11, count 2 2006.217.07:38:22.02#ibcon#end of sib2, iclass 11, count 2 2006.217.07:38:22.02#ibcon#*mode == 0, iclass 11, count 2 2006.217.07:38:22.02#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.217.07:38:22.02#ibcon#[27=AT05-04\r\n] 2006.217.07:38:22.02#ibcon#*before write, iclass 11, count 2 2006.217.07:38:22.02#ibcon#enter sib2, iclass 11, count 2 2006.217.07:38:22.02#ibcon#flushed, iclass 11, count 2 2006.217.07:38:22.02#ibcon#about to write, iclass 11, count 2 2006.217.07:38:22.02#ibcon#wrote, iclass 11, count 2 2006.217.07:38:22.02#ibcon#about to read 3, iclass 11, count 2 2006.217.07:38:22.05#ibcon#read 3, iclass 11, count 2 2006.217.07:38:22.05#ibcon#about to read 4, iclass 11, count 2 2006.217.07:38:22.05#ibcon#read 4, iclass 11, count 2 2006.217.07:38:22.05#ibcon#about to read 5, iclass 11, count 2 2006.217.07:38:22.05#ibcon#read 5, iclass 11, count 2 2006.217.07:38:22.05#ibcon#about to read 6, iclass 11, count 2 2006.217.07:38:22.05#ibcon#read 6, iclass 11, count 2 2006.217.07:38:22.05#ibcon#end of sib2, iclass 11, count 2 2006.217.07:38:22.05#ibcon#*after write, iclass 11, count 2 2006.217.07:38:22.05#ibcon#*before return 0, iclass 11, count 2 2006.217.07:38:22.05#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.217.07:38:22.05#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.217.07:38:22.05#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.217.07:38:22.05#ibcon#ireg 7 cls_cnt 0 2006.217.07:38:22.05#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.217.07:38:22.17#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.217.07:38:22.17#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.217.07:38:22.17#ibcon#enter wrdev, iclass 11, count 0 2006.217.07:38:22.17#ibcon#first serial, iclass 11, count 0 2006.217.07:38:22.17#ibcon#enter sib2, iclass 11, count 0 2006.217.07:38:22.17#ibcon#flushed, iclass 11, count 0 2006.217.07:38:22.17#ibcon#about to write, iclass 11, count 0 2006.217.07:38:22.17#ibcon#wrote, iclass 11, count 0 2006.217.07:38:22.17#ibcon#about to read 3, iclass 11, count 0 2006.217.07:38:22.19#ibcon#read 3, iclass 11, count 0 2006.217.07:38:22.19#ibcon#about to read 4, iclass 11, count 0 2006.217.07:38:22.19#ibcon#read 4, iclass 11, count 0 2006.217.07:38:22.19#ibcon#about to read 5, iclass 11, count 0 2006.217.07:38:22.19#ibcon#read 5, iclass 11, count 0 2006.217.07:38:22.19#ibcon#about to read 6, iclass 11, count 0 2006.217.07:38:22.19#ibcon#read 6, iclass 11, count 0 2006.217.07:38:22.19#ibcon#end of sib2, iclass 11, count 0 2006.217.07:38:22.19#ibcon#*mode == 0, iclass 11, count 0 2006.217.07:38:22.19#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.217.07:38:22.19#ibcon#[27=USB\r\n] 2006.217.07:38:22.19#ibcon#*before write, iclass 11, count 0 2006.217.07:38:22.19#ibcon#enter sib2, iclass 11, count 0 2006.217.07:38:22.19#ibcon#flushed, iclass 11, count 0 2006.217.07:38:22.19#ibcon#about to write, iclass 11, count 0 2006.217.07:38:22.19#ibcon#wrote, iclass 11, count 0 2006.217.07:38:22.19#ibcon#about to read 3, iclass 11, count 0 2006.217.07:38:22.22#ibcon#read 3, iclass 11, count 0 2006.217.07:38:22.22#ibcon#about to read 4, iclass 11, count 0 2006.217.07:38:22.22#ibcon#read 4, iclass 11, count 0 2006.217.07:38:22.22#ibcon#about to read 5, iclass 11, count 0 2006.217.07:38:22.22#ibcon#read 5, iclass 11, count 0 2006.217.07:38:22.22#ibcon#about to read 6, iclass 11, count 0 2006.217.07:38:22.22#ibcon#read 6, iclass 11, count 0 2006.217.07:38:22.22#ibcon#end of sib2, iclass 11, count 0 2006.217.07:38:22.22#ibcon#*after write, iclass 11, count 0 2006.217.07:38:22.22#ibcon#*before return 0, iclass 11, count 0 2006.217.07:38:22.22#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.217.07:38:22.22#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.217.07:38:22.22#ibcon#about to clear, iclass 11 cls_cnt 0 2006.217.07:38:22.22#ibcon#cleared, iclass 11 cls_cnt 0 2006.217.07:38:22.22$vc4f8/vblo=6,752.99 2006.217.07:38:22.22#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.217.07:38:22.22#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.217.07:38:22.22#ibcon#ireg 17 cls_cnt 0 2006.217.07:38:22.22#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.217.07:38:22.22#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.217.07:38:22.22#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.217.07:38:22.22#ibcon#enter wrdev, iclass 13, count 0 2006.217.07:38:22.22#ibcon#first serial, iclass 13, count 0 2006.217.07:38:22.22#ibcon#enter sib2, iclass 13, count 0 2006.217.07:38:22.22#ibcon#flushed, iclass 13, count 0 2006.217.07:38:22.22#ibcon#about to write, iclass 13, count 0 2006.217.07:38:22.22#ibcon#wrote, iclass 13, count 0 2006.217.07:38:22.22#ibcon#about to read 3, iclass 13, count 0 2006.217.07:38:22.24#ibcon#read 3, iclass 13, count 0 2006.217.07:38:22.24#ibcon#about to read 4, iclass 13, count 0 2006.217.07:38:22.24#ibcon#read 4, iclass 13, count 0 2006.217.07:38:22.24#ibcon#about to read 5, iclass 13, count 0 2006.217.07:38:22.24#ibcon#read 5, iclass 13, count 0 2006.217.07:38:22.24#ibcon#about to read 6, iclass 13, count 0 2006.217.07:38:22.24#ibcon#read 6, iclass 13, count 0 2006.217.07:38:22.24#ibcon#end of sib2, iclass 13, count 0 2006.217.07:38:22.24#ibcon#*mode == 0, iclass 13, count 0 2006.217.07:38:22.24#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.217.07:38:22.24#ibcon#[28=FRQ=06,752.99\r\n] 2006.217.07:38:22.24#ibcon#*before write, iclass 13, count 0 2006.217.07:38:22.24#ibcon#enter sib2, iclass 13, count 0 2006.217.07:38:22.24#ibcon#flushed, iclass 13, count 0 2006.217.07:38:22.24#ibcon#about to write, iclass 13, count 0 2006.217.07:38:22.24#ibcon#wrote, iclass 13, count 0 2006.217.07:38:22.24#ibcon#about to read 3, iclass 13, count 0 2006.217.07:38:22.28#ibcon#read 3, iclass 13, count 0 2006.217.07:38:22.28#ibcon#about to read 4, iclass 13, count 0 2006.217.07:38:22.28#ibcon#read 4, iclass 13, count 0 2006.217.07:38:22.28#ibcon#about to read 5, iclass 13, count 0 2006.217.07:38:22.28#ibcon#read 5, iclass 13, count 0 2006.217.07:38:22.28#ibcon#about to read 6, iclass 13, count 0 2006.217.07:38:22.28#ibcon#read 6, iclass 13, count 0 2006.217.07:38:22.28#ibcon#end of sib2, iclass 13, count 0 2006.217.07:38:22.28#ibcon#*after write, iclass 13, count 0 2006.217.07:38:22.28#ibcon#*before return 0, iclass 13, count 0 2006.217.07:38:22.28#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.217.07:38:22.28#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.217.07:38:22.28#ibcon#about to clear, iclass 13 cls_cnt 0 2006.217.07:38:22.28#ibcon#cleared, iclass 13 cls_cnt 0 2006.217.07:38:22.28$vc4f8/vb=6,4 2006.217.07:38:22.28#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.217.07:38:22.28#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.217.07:38:22.28#ibcon#ireg 11 cls_cnt 2 2006.217.07:38:22.28#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.217.07:38:22.34#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.217.07:38:22.34#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.217.07:38:22.34#ibcon#enter wrdev, iclass 15, count 2 2006.217.07:38:22.34#ibcon#first serial, iclass 15, count 2 2006.217.07:38:22.34#ibcon#enter sib2, iclass 15, count 2 2006.217.07:38:22.34#ibcon#flushed, iclass 15, count 2 2006.217.07:38:22.34#ibcon#about to write, iclass 15, count 2 2006.217.07:38:22.34#ibcon#wrote, iclass 15, count 2 2006.217.07:38:22.34#ibcon#about to read 3, iclass 15, count 2 2006.217.07:38:22.36#ibcon#read 3, iclass 15, count 2 2006.217.07:38:22.36#ibcon#about to read 4, iclass 15, count 2 2006.217.07:38:22.36#ibcon#read 4, iclass 15, count 2 2006.217.07:38:22.36#ibcon#about to read 5, iclass 15, count 2 2006.217.07:38:22.36#ibcon#read 5, iclass 15, count 2 2006.217.07:38:22.36#ibcon#about to read 6, iclass 15, count 2 2006.217.07:38:22.36#ibcon#read 6, iclass 15, count 2 2006.217.07:38:22.36#ibcon#end of sib2, iclass 15, count 2 2006.217.07:38:22.36#ibcon#*mode == 0, iclass 15, count 2 2006.217.07:38:22.36#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.217.07:38:22.36#ibcon#[27=AT06-04\r\n] 2006.217.07:38:22.36#ibcon#*before write, iclass 15, count 2 2006.217.07:38:22.36#ibcon#enter sib2, iclass 15, count 2 2006.217.07:38:22.36#ibcon#flushed, iclass 15, count 2 2006.217.07:38:22.36#ibcon#about to write, iclass 15, count 2 2006.217.07:38:22.36#ibcon#wrote, iclass 15, count 2 2006.217.07:38:22.36#ibcon#about to read 3, iclass 15, count 2 2006.217.07:38:22.39#ibcon#read 3, iclass 15, count 2 2006.217.07:38:22.39#ibcon#about to read 4, iclass 15, count 2 2006.217.07:38:22.39#ibcon#read 4, iclass 15, count 2 2006.217.07:38:22.39#ibcon#about to read 5, iclass 15, count 2 2006.217.07:38:22.39#ibcon#read 5, iclass 15, count 2 2006.217.07:38:22.39#ibcon#about to read 6, iclass 15, count 2 2006.217.07:38:22.39#ibcon#read 6, iclass 15, count 2 2006.217.07:38:22.39#ibcon#end of sib2, iclass 15, count 2 2006.217.07:38:22.39#ibcon#*after write, iclass 15, count 2 2006.217.07:38:22.39#ibcon#*before return 0, iclass 15, count 2 2006.217.07:38:22.39#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.217.07:38:22.39#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.217.07:38:22.39#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.217.07:38:22.39#ibcon#ireg 7 cls_cnt 0 2006.217.07:38:22.39#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.217.07:38:22.51#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.217.07:38:22.51#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.217.07:38:22.51#ibcon#enter wrdev, iclass 15, count 0 2006.217.07:38:22.51#ibcon#first serial, iclass 15, count 0 2006.217.07:38:22.51#ibcon#enter sib2, iclass 15, count 0 2006.217.07:38:22.51#ibcon#flushed, iclass 15, count 0 2006.217.07:38:22.51#ibcon#about to write, iclass 15, count 0 2006.217.07:38:22.51#ibcon#wrote, iclass 15, count 0 2006.217.07:38:22.51#ibcon#about to read 3, iclass 15, count 0 2006.217.07:38:22.53#ibcon#read 3, iclass 15, count 0 2006.217.07:38:22.53#ibcon#about to read 4, iclass 15, count 0 2006.217.07:38:22.53#ibcon#read 4, iclass 15, count 0 2006.217.07:38:22.53#ibcon#about to read 5, iclass 15, count 0 2006.217.07:38:22.53#ibcon#read 5, iclass 15, count 0 2006.217.07:38:22.53#ibcon#about to read 6, iclass 15, count 0 2006.217.07:38:22.53#ibcon#read 6, iclass 15, count 0 2006.217.07:38:22.53#ibcon#end of sib2, iclass 15, count 0 2006.217.07:38:22.53#ibcon#*mode == 0, iclass 15, count 0 2006.217.07:38:22.53#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.217.07:38:22.53#ibcon#[27=USB\r\n] 2006.217.07:38:22.53#ibcon#*before write, iclass 15, count 0 2006.217.07:38:22.53#ibcon#enter sib2, iclass 15, count 0 2006.217.07:38:22.53#ibcon#flushed, iclass 15, count 0 2006.217.07:38:22.53#ibcon#about to write, iclass 15, count 0 2006.217.07:38:22.53#ibcon#wrote, iclass 15, count 0 2006.217.07:38:22.53#ibcon#about to read 3, iclass 15, count 0 2006.217.07:38:22.56#ibcon#read 3, iclass 15, count 0 2006.217.07:38:22.56#ibcon#about to read 4, iclass 15, count 0 2006.217.07:38:22.56#ibcon#read 4, iclass 15, count 0 2006.217.07:38:22.56#ibcon#about to read 5, iclass 15, count 0 2006.217.07:38:22.56#ibcon#read 5, iclass 15, count 0 2006.217.07:38:22.56#ibcon#about to read 6, iclass 15, count 0 2006.217.07:38:22.56#ibcon#read 6, iclass 15, count 0 2006.217.07:38:22.56#ibcon#end of sib2, iclass 15, count 0 2006.217.07:38:22.56#ibcon#*after write, iclass 15, count 0 2006.217.07:38:22.56#ibcon#*before return 0, iclass 15, count 0 2006.217.07:38:22.56#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.217.07:38:22.56#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.217.07:38:22.56#ibcon#about to clear, iclass 15 cls_cnt 0 2006.217.07:38:22.56#ibcon#cleared, iclass 15 cls_cnt 0 2006.217.07:38:22.56$vc4f8/vabw=wide 2006.217.07:38:22.56#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.217.07:38:22.56#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.217.07:38:22.56#ibcon#ireg 8 cls_cnt 0 2006.217.07:38:22.56#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.217.07:38:22.56#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.217.07:38:22.56#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.217.07:38:22.56#ibcon#enter wrdev, iclass 17, count 0 2006.217.07:38:22.56#ibcon#first serial, iclass 17, count 0 2006.217.07:38:22.56#ibcon#enter sib2, iclass 17, count 0 2006.217.07:38:22.56#ibcon#flushed, iclass 17, count 0 2006.217.07:38:22.56#ibcon#about to write, iclass 17, count 0 2006.217.07:38:22.56#ibcon#wrote, iclass 17, count 0 2006.217.07:38:22.56#ibcon#about to read 3, iclass 17, count 0 2006.217.07:38:22.58#ibcon#read 3, iclass 17, count 0 2006.217.07:38:22.58#ibcon#about to read 4, iclass 17, count 0 2006.217.07:38:22.58#ibcon#read 4, iclass 17, count 0 2006.217.07:38:22.58#ibcon#about to read 5, iclass 17, count 0 2006.217.07:38:22.58#ibcon#read 5, iclass 17, count 0 2006.217.07:38:22.58#ibcon#about to read 6, iclass 17, count 0 2006.217.07:38:22.58#ibcon#read 6, iclass 17, count 0 2006.217.07:38:22.58#ibcon#end of sib2, iclass 17, count 0 2006.217.07:38:22.58#ibcon#*mode == 0, iclass 17, count 0 2006.217.07:38:22.58#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.217.07:38:22.58#ibcon#[25=BW32\r\n] 2006.217.07:38:22.58#ibcon#*before write, iclass 17, count 0 2006.217.07:38:22.58#ibcon#enter sib2, iclass 17, count 0 2006.217.07:38:22.58#ibcon#flushed, iclass 17, count 0 2006.217.07:38:22.58#ibcon#about to write, iclass 17, count 0 2006.217.07:38:22.58#ibcon#wrote, iclass 17, count 0 2006.217.07:38:22.58#ibcon#about to read 3, iclass 17, count 0 2006.217.07:38:22.61#ibcon#read 3, iclass 17, count 0 2006.217.07:38:22.61#ibcon#about to read 4, iclass 17, count 0 2006.217.07:38:22.61#ibcon#read 4, iclass 17, count 0 2006.217.07:38:22.61#ibcon#about to read 5, iclass 17, count 0 2006.217.07:38:22.61#ibcon#read 5, iclass 17, count 0 2006.217.07:38:22.61#ibcon#about to read 6, iclass 17, count 0 2006.217.07:38:22.61#ibcon#read 6, iclass 17, count 0 2006.217.07:38:22.61#ibcon#end of sib2, iclass 17, count 0 2006.217.07:38:22.61#ibcon#*after write, iclass 17, count 0 2006.217.07:38:22.61#ibcon#*before return 0, iclass 17, count 0 2006.217.07:38:22.61#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.217.07:38:22.61#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.217.07:38:22.61#ibcon#about to clear, iclass 17 cls_cnt 0 2006.217.07:38:22.61#ibcon#cleared, iclass 17 cls_cnt 0 2006.217.07:38:22.61$vc4f8/vbbw=wide 2006.217.07:38:22.61#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.217.07:38:22.61#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.217.07:38:22.61#ibcon#ireg 8 cls_cnt 0 2006.217.07:38:22.61#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.217.07:38:22.68#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.217.07:38:22.68#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.217.07:38:22.68#ibcon#enter wrdev, iclass 19, count 0 2006.217.07:38:22.68#ibcon#first serial, iclass 19, count 0 2006.217.07:38:22.68#ibcon#enter sib2, iclass 19, count 0 2006.217.07:38:22.68#ibcon#flushed, iclass 19, count 0 2006.217.07:38:22.68#ibcon#about to write, iclass 19, count 0 2006.217.07:38:22.68#ibcon#wrote, iclass 19, count 0 2006.217.07:38:22.68#ibcon#about to read 3, iclass 19, count 0 2006.217.07:38:22.70#ibcon#read 3, iclass 19, count 0 2006.217.07:38:22.70#ibcon#about to read 4, iclass 19, count 0 2006.217.07:38:22.70#ibcon#read 4, iclass 19, count 0 2006.217.07:38:22.70#ibcon#about to read 5, iclass 19, count 0 2006.217.07:38:22.70#ibcon#read 5, iclass 19, count 0 2006.217.07:38:22.70#ibcon#about to read 6, iclass 19, count 0 2006.217.07:38:22.70#ibcon#read 6, iclass 19, count 0 2006.217.07:38:22.70#ibcon#end of sib2, iclass 19, count 0 2006.217.07:38:22.70#ibcon#*mode == 0, iclass 19, count 0 2006.217.07:38:22.70#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.217.07:38:22.70#ibcon#[27=BW32\r\n] 2006.217.07:38:22.70#ibcon#*before write, iclass 19, count 0 2006.217.07:38:22.70#ibcon#enter sib2, iclass 19, count 0 2006.217.07:38:22.70#ibcon#flushed, iclass 19, count 0 2006.217.07:38:22.70#ibcon#about to write, iclass 19, count 0 2006.217.07:38:22.70#ibcon#wrote, iclass 19, count 0 2006.217.07:38:22.70#ibcon#about to read 3, iclass 19, count 0 2006.217.07:38:22.73#ibcon#read 3, iclass 19, count 0 2006.217.07:38:22.73#ibcon#about to read 4, iclass 19, count 0 2006.217.07:38:22.73#ibcon#read 4, iclass 19, count 0 2006.217.07:38:22.73#ibcon#about to read 5, iclass 19, count 0 2006.217.07:38:22.73#ibcon#read 5, iclass 19, count 0 2006.217.07:38:22.73#ibcon#about to read 6, iclass 19, count 0 2006.217.07:38:22.73#ibcon#read 6, iclass 19, count 0 2006.217.07:38:22.73#ibcon#end of sib2, iclass 19, count 0 2006.217.07:38:22.73#ibcon#*after write, iclass 19, count 0 2006.217.07:38:22.73#ibcon#*before return 0, iclass 19, count 0 2006.217.07:38:22.73#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.217.07:38:22.73#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.217.07:38:22.73#ibcon#about to clear, iclass 19 cls_cnt 0 2006.217.07:38:22.73#ibcon#cleared, iclass 19 cls_cnt 0 2006.217.07:38:22.73$4f8m12a/ifd4f 2006.217.07:38:22.73$ifd4f/lo= 2006.217.07:38:22.73$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.217.07:38:22.73$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.217.07:38:22.73$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.217.07:38:22.73$ifd4f/patch= 2006.217.07:38:22.73$ifd4f/patch=lo1,a1,a2,a3,a4 2006.217.07:38:22.73$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.217.07:38:22.73$ifd4f/patch=lo3,a5,a6,a7,a8 2006.217.07:38:22.73$4f8m12a/"form=m,16.000,1:2 2006.217.07:38:22.73$4f8m12a/"tpicd 2006.217.07:38:22.73$4f8m12a/echo=off 2006.217.07:38:22.73$4f8m12a/xlog=off 2006.217.07:38:22.73:!2006.217.07:38:50 2006.217.07:38:31.14#trakl#Source acquired 2006.217.07:38:32.14#flagr#flagr/antenna,acquired 2006.217.07:38:50.00:preob 2006.217.07:38:51.14/onsource/TRACKING 2006.217.07:38:51.14:!2006.217.07:39:00 2006.217.07:39:00.00:data_valid=on 2006.217.07:39:00.00:midob 2006.217.07:39:00.14/onsource/TRACKING 2006.217.07:39:00.14/wx/31.30,1008.6,60 2006.217.07:39:00.26/cable/+6.3864E-03 2006.217.07:39:01.35/va/01,05,usb,yes,31,33 2006.217.07:39:01.35/va/02,04,usb,yes,29,31 2006.217.07:39:01.35/va/03,04,usb,yes,27,28 2006.217.07:39:01.35/va/04,04,usb,yes,31,33 2006.217.07:39:01.35/va/05,07,usb,yes,33,34 2006.217.07:39:01.35/va/06,06,usb,yes,32,32 2006.217.07:39:01.35/va/07,06,usb,yes,32,32 2006.217.07:39:01.35/va/08,07,usb,yes,31,30 2006.217.07:39:01.58/valo/01,532.99,yes,locked 2006.217.07:39:01.58/valo/02,572.99,yes,locked 2006.217.07:39:01.58/valo/03,672.99,yes,locked 2006.217.07:39:01.58/valo/04,832.99,yes,locked 2006.217.07:39:01.58/valo/05,652.99,yes,locked 2006.217.07:39:01.58/valo/06,772.99,yes,locked 2006.217.07:39:01.58/valo/07,832.99,yes,locked 2006.217.07:39:01.58/valo/08,852.99,yes,locked 2006.217.07:39:02.67/vb/01,04,usb,yes,30,29 2006.217.07:39:02.67/vb/02,04,usb,yes,32,33 2006.217.07:39:02.67/vb/03,04,usb,yes,28,32 2006.217.07:39:02.67/vb/04,04,usb,yes,29,29 2006.217.07:39:02.67/vb/05,04,usb,yes,28,32 2006.217.07:39:02.67/vb/06,04,usb,yes,28,31 2006.217.07:39:02.67/vb/07,04,usb,yes,31,31 2006.217.07:39:02.67/vb/08,04,usb,yes,28,32 2006.217.07:39:02.91/vblo/01,632.99,yes,locked 2006.217.07:39:02.91/vblo/02,640.99,yes,locked 2006.217.07:39:02.91/vblo/03,656.99,yes,locked 2006.217.07:39:02.91/vblo/04,712.99,yes,locked 2006.217.07:39:02.91/vblo/05,744.99,yes,locked 2006.217.07:39:02.91/vblo/06,752.99,yes,locked 2006.217.07:39:02.91/vblo/07,734.99,yes,locked 2006.217.07:39:02.91/vblo/08,744.99,yes,locked 2006.217.07:39:03.06/vabw/8 2006.217.07:39:03.21/vbbw/8 2006.217.07:39:03.42/xfe/off,on,15.0 2006.217.07:39:03.80/ifatt/23,28,28,28 2006.217.07:39:04.07/fmout-gps/S +4.38E-07 2006.217.07:39:04.11:!2006.217.07:40:00 2006.217.07:40:00.00:data_valid=off 2006.217.07:40:00.00:postob 2006.217.07:40:00.15/cable/+6.3860E-03 2006.217.07:40:00.15/wx/31.29,1008.6,60 2006.217.07:40:01.07/fmout-gps/S +4.37E-07 2006.217.07:40:01.07:scan_name=217-0740,k06217,60 2006.217.07:40:01.07:source=1418+546,141946.60,542314.8,2000.0,cw 2006.217.07:40:01.14#flagr#flagr/antenna,new-source 2006.217.07:40:02.14:checkk5 2006.217.07:40:02.51/chk_autoobs//k5ts1/ autoobs is running! 2006.217.07:40:02.89/chk_autoobs//k5ts2/ autoobs is running! 2006.217.07:40:03.26/chk_autoobs//k5ts3/ autoobs is running! 2006.217.07:40:03.64/chk_autoobs//k5ts4/ autoobs is running! 2006.217.07:40:04.01/chk_obsdata//k5ts1/T2170739??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:40:04.38/chk_obsdata//k5ts2/T2170739??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:40:04.74/chk_obsdata//k5ts3/T2170739??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:40:05.11/chk_obsdata//k5ts4/T2170739??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:40:05.80/k5log//k5ts1_log_newline 2006.217.07:40:06.49/k5log//k5ts2_log_newline 2006.217.07:40:07.17/k5log//k5ts3_log_newline 2006.217.07:40:07.86/k5log//k5ts4_log_newline 2006.217.07:40:07.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.217.07:40:07.88:4f8m12a=1 2006.217.07:40:07.88$4f8m12a/echo=on 2006.217.07:40:07.88$4f8m12a/pcalon 2006.217.07:40:07.88$pcalon/"no phase cal control is implemented here 2006.217.07:40:07.88$4f8m12a/"tpicd=stop 2006.217.07:40:07.88$4f8m12a/vc4f8 2006.217.07:40:07.88$vc4f8/valo=1,532.99 2006.217.07:40:07.89#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.217.07:40:07.89#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.217.07:40:07.89#ibcon#ireg 17 cls_cnt 0 2006.217.07:40:07.89#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.217.07:40:07.89#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.217.07:40:07.89#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.217.07:40:07.89#ibcon#enter wrdev, iclass 26, count 0 2006.217.07:40:07.89#ibcon#first serial, iclass 26, count 0 2006.217.07:40:07.89#ibcon#enter sib2, iclass 26, count 0 2006.217.07:40:07.89#ibcon#flushed, iclass 26, count 0 2006.217.07:40:07.89#ibcon#about to write, iclass 26, count 0 2006.217.07:40:07.89#ibcon#wrote, iclass 26, count 0 2006.217.07:40:07.89#ibcon#about to read 3, iclass 26, count 0 2006.217.07:40:07.93#ibcon#read 3, iclass 26, count 0 2006.217.07:40:07.93#ibcon#about to read 4, iclass 26, count 0 2006.217.07:40:07.93#ibcon#read 4, iclass 26, count 0 2006.217.07:40:07.93#ibcon#about to read 5, iclass 26, count 0 2006.217.07:40:07.93#ibcon#read 5, iclass 26, count 0 2006.217.07:40:07.93#ibcon#about to read 6, iclass 26, count 0 2006.217.07:40:07.93#ibcon#read 6, iclass 26, count 0 2006.217.07:40:07.93#ibcon#end of sib2, iclass 26, count 0 2006.217.07:40:07.93#ibcon#*mode == 0, iclass 26, count 0 2006.217.07:40:07.93#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.217.07:40:07.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.217.07:40:07.93#ibcon#*before write, iclass 26, count 0 2006.217.07:40:07.93#ibcon#enter sib2, iclass 26, count 0 2006.217.07:40:07.93#ibcon#flushed, iclass 26, count 0 2006.217.07:40:07.93#ibcon#about to write, iclass 26, count 0 2006.217.07:40:07.93#ibcon#wrote, iclass 26, count 0 2006.217.07:40:07.93#ibcon#about to read 3, iclass 26, count 0 2006.217.07:40:07.97#ibcon#read 3, iclass 26, count 0 2006.217.07:40:07.97#ibcon#about to read 4, iclass 26, count 0 2006.217.07:40:07.97#ibcon#read 4, iclass 26, count 0 2006.217.07:40:07.97#ibcon#about to read 5, iclass 26, count 0 2006.217.07:40:07.98#ibcon#read 5, iclass 26, count 0 2006.217.07:40:07.98#ibcon#about to read 6, iclass 26, count 0 2006.217.07:40:07.98#ibcon#read 6, iclass 26, count 0 2006.217.07:40:07.98#ibcon#end of sib2, iclass 26, count 0 2006.217.07:40:07.98#ibcon#*after write, iclass 26, count 0 2006.217.07:40:07.98#ibcon#*before return 0, iclass 26, count 0 2006.217.07:40:07.98#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.217.07:40:07.98#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.217.07:40:07.98#ibcon#about to clear, iclass 26 cls_cnt 0 2006.217.07:40:07.98#ibcon#cleared, iclass 26 cls_cnt 0 2006.217.07:40:07.98$vc4f8/va=1,5 2006.217.07:40:07.98#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.217.07:40:07.98#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.217.07:40:07.98#ibcon#ireg 11 cls_cnt 2 2006.217.07:40:07.98#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.217.07:40:07.98#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.217.07:40:07.98#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.217.07:40:07.98#ibcon#enter wrdev, iclass 28, count 2 2006.217.07:40:07.98#ibcon#first serial, iclass 28, count 2 2006.217.07:40:07.98#ibcon#enter sib2, iclass 28, count 2 2006.217.07:40:07.98#ibcon#flushed, iclass 28, count 2 2006.217.07:40:07.98#ibcon#about to write, iclass 28, count 2 2006.217.07:40:07.98#ibcon#wrote, iclass 28, count 2 2006.217.07:40:07.98#ibcon#about to read 3, iclass 28, count 2 2006.217.07:40:08.00#ibcon#read 3, iclass 28, count 2 2006.217.07:40:08.00#ibcon#about to read 4, iclass 28, count 2 2006.217.07:40:08.00#ibcon#read 4, iclass 28, count 2 2006.217.07:40:08.00#ibcon#about to read 5, iclass 28, count 2 2006.217.07:40:08.00#ibcon#read 5, iclass 28, count 2 2006.217.07:40:08.00#ibcon#about to read 6, iclass 28, count 2 2006.217.07:40:08.00#ibcon#read 6, iclass 28, count 2 2006.217.07:40:08.00#ibcon#end of sib2, iclass 28, count 2 2006.217.07:40:08.00#ibcon#*mode == 0, iclass 28, count 2 2006.217.07:40:08.00#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.217.07:40:08.00#ibcon#[25=AT01-05\r\n] 2006.217.07:40:08.00#ibcon#*before write, iclass 28, count 2 2006.217.07:40:08.00#ibcon#enter sib2, iclass 28, count 2 2006.217.07:40:08.00#ibcon#flushed, iclass 28, count 2 2006.217.07:40:08.00#ibcon#about to write, iclass 28, count 2 2006.217.07:40:08.00#ibcon#wrote, iclass 28, count 2 2006.217.07:40:08.00#ibcon#about to read 3, iclass 28, count 2 2006.217.07:40:08.03#ibcon#read 3, iclass 28, count 2 2006.217.07:40:08.03#ibcon#about to read 4, iclass 28, count 2 2006.217.07:40:08.03#ibcon#read 4, iclass 28, count 2 2006.217.07:40:08.03#ibcon#about to read 5, iclass 28, count 2 2006.217.07:40:08.03#ibcon#read 5, iclass 28, count 2 2006.217.07:40:08.03#ibcon#about to read 6, iclass 28, count 2 2006.217.07:40:08.03#ibcon#read 6, iclass 28, count 2 2006.217.07:40:08.03#ibcon#end of sib2, iclass 28, count 2 2006.217.07:40:08.03#ibcon#*after write, iclass 28, count 2 2006.217.07:40:08.03#ibcon#*before return 0, iclass 28, count 2 2006.217.07:40:08.03#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.217.07:40:08.03#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.217.07:40:08.03#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.217.07:40:08.03#ibcon#ireg 7 cls_cnt 0 2006.217.07:40:08.03#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.217.07:40:08.14#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.217.07:40:08.14#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.217.07:40:08.14#ibcon#enter wrdev, iclass 28, count 0 2006.217.07:40:08.14#ibcon#first serial, iclass 28, count 0 2006.217.07:40:08.14#ibcon#enter sib2, iclass 28, count 0 2006.217.07:40:08.14#ibcon#flushed, iclass 28, count 0 2006.217.07:40:08.14#ibcon#about to write, iclass 28, count 0 2006.217.07:40:08.15#ibcon#wrote, iclass 28, count 0 2006.217.07:40:08.15#ibcon#about to read 3, iclass 28, count 0 2006.217.07:40:08.16#ibcon#read 3, iclass 28, count 0 2006.217.07:40:08.16#ibcon#about to read 4, iclass 28, count 0 2006.217.07:40:08.16#ibcon#read 4, iclass 28, count 0 2006.217.07:40:08.16#ibcon#about to read 5, iclass 28, count 0 2006.217.07:40:08.17#ibcon#read 5, iclass 28, count 0 2006.217.07:40:08.17#ibcon#about to read 6, iclass 28, count 0 2006.217.07:40:08.17#ibcon#read 6, iclass 28, count 0 2006.217.07:40:08.17#ibcon#end of sib2, iclass 28, count 0 2006.217.07:40:08.17#ibcon#*mode == 0, iclass 28, count 0 2006.217.07:40:08.17#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.217.07:40:08.17#ibcon#[25=USB\r\n] 2006.217.07:40:08.17#ibcon#*before write, iclass 28, count 0 2006.217.07:40:08.17#ibcon#enter sib2, iclass 28, count 0 2006.217.07:40:08.17#ibcon#flushed, iclass 28, count 0 2006.217.07:40:08.17#ibcon#about to write, iclass 28, count 0 2006.217.07:40:08.17#ibcon#wrote, iclass 28, count 0 2006.217.07:40:08.17#ibcon#about to read 3, iclass 28, count 0 2006.217.07:40:08.19#ibcon#read 3, iclass 28, count 0 2006.217.07:40:08.20#ibcon#about to read 4, iclass 28, count 0 2006.217.07:40:08.20#ibcon#read 4, iclass 28, count 0 2006.217.07:40:08.20#ibcon#about to read 5, iclass 28, count 0 2006.217.07:40:08.20#ibcon#read 5, iclass 28, count 0 2006.217.07:40:08.20#ibcon#about to read 6, iclass 28, count 0 2006.217.07:40:08.20#ibcon#read 6, iclass 28, count 0 2006.217.07:40:08.20#ibcon#end of sib2, iclass 28, count 0 2006.217.07:40:08.20#ibcon#*after write, iclass 28, count 0 2006.217.07:40:08.20#ibcon#*before return 0, iclass 28, count 0 2006.217.07:40:08.20#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.217.07:40:08.20#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.217.07:40:08.20#ibcon#about to clear, iclass 28 cls_cnt 0 2006.217.07:40:08.20#ibcon#cleared, iclass 28 cls_cnt 0 2006.217.07:40:08.20$vc4f8/valo=2,572.99 2006.217.07:40:08.20#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.217.07:40:08.20#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.217.07:40:08.20#ibcon#ireg 17 cls_cnt 0 2006.217.07:40:08.20#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.217.07:40:08.20#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.217.07:40:08.20#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.217.07:40:08.20#ibcon#enter wrdev, iclass 30, count 0 2006.217.07:40:08.20#ibcon#first serial, iclass 30, count 0 2006.217.07:40:08.20#ibcon#enter sib2, iclass 30, count 0 2006.217.07:40:08.20#ibcon#flushed, iclass 30, count 0 2006.217.07:40:08.20#ibcon#about to write, iclass 30, count 0 2006.217.07:40:08.20#ibcon#wrote, iclass 30, count 0 2006.217.07:40:08.20#ibcon#about to read 3, iclass 30, count 0 2006.217.07:40:08.22#ibcon#read 3, iclass 30, count 0 2006.217.07:40:08.22#ibcon#about to read 4, iclass 30, count 0 2006.217.07:40:08.22#ibcon#read 4, iclass 30, count 0 2006.217.07:40:08.22#ibcon#about to read 5, iclass 30, count 0 2006.217.07:40:08.22#ibcon#read 5, iclass 30, count 0 2006.217.07:40:08.22#ibcon#about to read 6, iclass 30, count 0 2006.217.07:40:08.22#ibcon#read 6, iclass 30, count 0 2006.217.07:40:08.22#ibcon#end of sib2, iclass 30, count 0 2006.217.07:40:08.22#ibcon#*mode == 0, iclass 30, count 0 2006.217.07:40:08.22#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.217.07:40:08.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.217.07:40:08.22#ibcon#*before write, iclass 30, count 0 2006.217.07:40:08.22#ibcon#enter sib2, iclass 30, count 0 2006.217.07:40:08.22#ibcon#flushed, iclass 30, count 0 2006.217.07:40:08.22#ibcon#about to write, iclass 30, count 0 2006.217.07:40:08.22#ibcon#wrote, iclass 30, count 0 2006.217.07:40:08.22#ibcon#about to read 3, iclass 30, count 0 2006.217.07:40:08.25#ibcon#read 3, iclass 30, count 0 2006.217.07:40:08.25#ibcon#about to read 4, iclass 30, count 0 2006.217.07:40:08.25#ibcon#read 4, iclass 30, count 0 2006.217.07:40:08.25#ibcon#about to read 5, iclass 30, count 0 2006.217.07:40:08.26#ibcon#read 5, iclass 30, count 0 2006.217.07:40:08.26#ibcon#about to read 6, iclass 30, count 0 2006.217.07:40:08.26#ibcon#read 6, iclass 30, count 0 2006.217.07:40:08.26#ibcon#end of sib2, iclass 30, count 0 2006.217.07:40:08.26#ibcon#*after write, iclass 30, count 0 2006.217.07:40:08.26#ibcon#*before return 0, iclass 30, count 0 2006.217.07:40:08.26#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.217.07:40:08.26#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.217.07:40:08.26#ibcon#about to clear, iclass 30 cls_cnt 0 2006.217.07:40:08.26#ibcon#cleared, iclass 30 cls_cnt 0 2006.217.07:40:08.26$vc4f8/va=2,4 2006.217.07:40:08.26#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.217.07:40:08.26#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.217.07:40:08.26#ibcon#ireg 11 cls_cnt 2 2006.217.07:40:08.26#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.217.07:40:08.31#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.217.07:40:08.31#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.217.07:40:08.31#ibcon#enter wrdev, iclass 32, count 2 2006.217.07:40:08.31#ibcon#first serial, iclass 32, count 2 2006.217.07:40:08.31#ibcon#enter sib2, iclass 32, count 2 2006.217.07:40:08.32#ibcon#flushed, iclass 32, count 2 2006.217.07:40:08.32#ibcon#about to write, iclass 32, count 2 2006.217.07:40:08.32#ibcon#wrote, iclass 32, count 2 2006.217.07:40:08.32#ibcon#about to read 3, iclass 32, count 2 2006.217.07:40:08.33#ibcon#read 3, iclass 32, count 2 2006.217.07:40:08.33#ibcon#about to read 4, iclass 32, count 2 2006.217.07:40:08.34#ibcon#read 4, iclass 32, count 2 2006.217.07:40:08.34#ibcon#about to read 5, iclass 32, count 2 2006.217.07:40:08.34#ibcon#read 5, iclass 32, count 2 2006.217.07:40:08.34#ibcon#about to read 6, iclass 32, count 2 2006.217.07:40:08.34#ibcon#read 6, iclass 32, count 2 2006.217.07:40:08.34#ibcon#end of sib2, iclass 32, count 2 2006.217.07:40:08.34#ibcon#*mode == 0, iclass 32, count 2 2006.217.07:40:08.34#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.217.07:40:08.34#ibcon#[25=AT02-04\r\n] 2006.217.07:40:08.34#ibcon#*before write, iclass 32, count 2 2006.217.07:40:08.34#ibcon#enter sib2, iclass 32, count 2 2006.217.07:40:08.34#ibcon#flushed, iclass 32, count 2 2006.217.07:40:08.34#ibcon#about to write, iclass 32, count 2 2006.217.07:40:08.34#ibcon#wrote, iclass 32, count 2 2006.217.07:40:08.34#ibcon#about to read 3, iclass 32, count 2 2006.217.07:40:08.36#ibcon#read 3, iclass 32, count 2 2006.217.07:40:08.36#ibcon#about to read 4, iclass 32, count 2 2006.217.07:40:08.36#ibcon#read 4, iclass 32, count 2 2006.217.07:40:08.36#ibcon#about to read 5, iclass 32, count 2 2006.217.07:40:08.37#ibcon#read 5, iclass 32, count 2 2006.217.07:40:08.37#ibcon#about to read 6, iclass 32, count 2 2006.217.07:40:08.37#ibcon#read 6, iclass 32, count 2 2006.217.07:40:08.37#ibcon#end of sib2, iclass 32, count 2 2006.217.07:40:08.37#ibcon#*after write, iclass 32, count 2 2006.217.07:40:08.37#ibcon#*before return 0, iclass 32, count 2 2006.217.07:40:08.37#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.217.07:40:08.37#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.217.07:40:08.37#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.217.07:40:08.37#ibcon#ireg 7 cls_cnt 0 2006.217.07:40:08.37#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.217.07:40:08.49#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.217.07:40:08.49#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.217.07:40:08.49#ibcon#enter wrdev, iclass 32, count 0 2006.217.07:40:08.49#ibcon#first serial, iclass 32, count 0 2006.217.07:40:08.49#ibcon#enter sib2, iclass 32, count 0 2006.217.07:40:08.49#ibcon#flushed, iclass 32, count 0 2006.217.07:40:08.49#ibcon#about to write, iclass 32, count 0 2006.217.07:40:08.49#ibcon#wrote, iclass 32, count 0 2006.217.07:40:08.49#ibcon#about to read 3, iclass 32, count 0 2006.217.07:40:08.51#ibcon#read 3, iclass 32, count 0 2006.217.07:40:08.51#ibcon#about to read 4, iclass 32, count 0 2006.217.07:40:08.51#ibcon#read 4, iclass 32, count 0 2006.217.07:40:08.51#ibcon#about to read 5, iclass 32, count 0 2006.217.07:40:08.51#ibcon#read 5, iclass 32, count 0 2006.217.07:40:08.51#ibcon#about to read 6, iclass 32, count 0 2006.217.07:40:08.51#ibcon#read 6, iclass 32, count 0 2006.217.07:40:08.51#ibcon#end of sib2, iclass 32, count 0 2006.217.07:40:08.51#ibcon#*mode == 0, iclass 32, count 0 2006.217.07:40:08.51#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.217.07:40:08.51#ibcon#[25=USB\r\n] 2006.217.07:40:08.51#ibcon#*before write, iclass 32, count 0 2006.217.07:40:08.51#ibcon#enter sib2, iclass 32, count 0 2006.217.07:40:08.51#ibcon#flushed, iclass 32, count 0 2006.217.07:40:08.51#ibcon#about to write, iclass 32, count 0 2006.217.07:40:08.51#ibcon#wrote, iclass 32, count 0 2006.217.07:40:08.51#ibcon#about to read 3, iclass 32, count 0 2006.217.07:40:08.53#ibcon#read 3, iclass 32, count 0 2006.217.07:40:08.53#ibcon#about to read 4, iclass 32, count 0 2006.217.07:40:08.53#ibcon#read 4, iclass 32, count 0 2006.217.07:40:08.53#ibcon#about to read 5, iclass 32, count 0 2006.217.07:40:08.54#ibcon#read 5, iclass 32, count 0 2006.217.07:40:08.54#ibcon#about to read 6, iclass 32, count 0 2006.217.07:40:08.54#ibcon#read 6, iclass 32, count 0 2006.217.07:40:08.54#ibcon#end of sib2, iclass 32, count 0 2006.217.07:40:08.54#ibcon#*after write, iclass 32, count 0 2006.217.07:40:08.54#ibcon#*before return 0, iclass 32, count 0 2006.217.07:40:08.54#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.217.07:40:08.54#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.217.07:40:08.54#ibcon#about to clear, iclass 32 cls_cnt 0 2006.217.07:40:08.54#ibcon#cleared, iclass 32 cls_cnt 0 2006.217.07:40:08.54$vc4f8/valo=3,672.99 2006.217.07:40:08.54#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.217.07:40:08.54#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.217.07:40:08.54#ibcon#ireg 17 cls_cnt 0 2006.217.07:40:08.54#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.217.07:40:08.54#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.217.07:40:08.54#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.217.07:40:08.54#ibcon#enter wrdev, iclass 34, count 0 2006.217.07:40:08.54#ibcon#first serial, iclass 34, count 0 2006.217.07:40:08.54#ibcon#enter sib2, iclass 34, count 0 2006.217.07:40:08.54#ibcon#flushed, iclass 34, count 0 2006.217.07:40:08.54#ibcon#about to write, iclass 34, count 0 2006.217.07:40:08.54#ibcon#wrote, iclass 34, count 0 2006.217.07:40:08.54#ibcon#about to read 3, iclass 34, count 0 2006.217.07:40:08.56#ibcon#read 3, iclass 34, count 0 2006.217.07:40:08.56#ibcon#about to read 4, iclass 34, count 0 2006.217.07:40:08.56#ibcon#read 4, iclass 34, count 0 2006.217.07:40:08.56#ibcon#about to read 5, iclass 34, count 0 2006.217.07:40:08.56#ibcon#read 5, iclass 34, count 0 2006.217.07:40:08.56#ibcon#about to read 6, iclass 34, count 0 2006.217.07:40:08.56#ibcon#read 6, iclass 34, count 0 2006.217.07:40:08.56#ibcon#end of sib2, iclass 34, count 0 2006.217.07:40:08.56#ibcon#*mode == 0, iclass 34, count 0 2006.217.07:40:08.56#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.217.07:40:08.56#ibcon#[26=FRQ=03,672.99\r\n] 2006.217.07:40:08.56#ibcon#*before write, iclass 34, count 0 2006.217.07:40:08.56#ibcon#enter sib2, iclass 34, count 0 2006.217.07:40:08.56#ibcon#flushed, iclass 34, count 0 2006.217.07:40:08.56#ibcon#about to write, iclass 34, count 0 2006.217.07:40:08.56#ibcon#wrote, iclass 34, count 0 2006.217.07:40:08.56#ibcon#about to read 3, iclass 34, count 0 2006.217.07:40:08.60#ibcon#read 3, iclass 34, count 0 2006.217.07:40:08.60#ibcon#about to read 4, iclass 34, count 0 2006.217.07:40:08.60#ibcon#read 4, iclass 34, count 0 2006.217.07:40:08.60#ibcon#about to read 5, iclass 34, count 0 2006.217.07:40:08.60#ibcon#read 5, iclass 34, count 0 2006.217.07:40:08.60#ibcon#about to read 6, iclass 34, count 0 2006.217.07:40:08.60#ibcon#read 6, iclass 34, count 0 2006.217.07:40:08.60#ibcon#end of sib2, iclass 34, count 0 2006.217.07:40:08.60#ibcon#*after write, iclass 34, count 0 2006.217.07:40:08.60#ibcon#*before return 0, iclass 34, count 0 2006.217.07:40:08.60#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.217.07:40:08.60#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.217.07:40:08.60#ibcon#about to clear, iclass 34 cls_cnt 0 2006.217.07:40:08.60#ibcon#cleared, iclass 34 cls_cnt 0 2006.217.07:40:08.60$vc4f8/va=3,4 2006.217.07:40:08.60#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.217.07:40:08.60#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.217.07:40:08.60#ibcon#ireg 11 cls_cnt 2 2006.217.07:40:08.60#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.217.07:40:08.65#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.217.07:40:08.65#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.217.07:40:08.65#ibcon#enter wrdev, iclass 36, count 2 2006.217.07:40:08.65#ibcon#first serial, iclass 36, count 2 2006.217.07:40:08.65#ibcon#enter sib2, iclass 36, count 2 2006.217.07:40:08.66#ibcon#flushed, iclass 36, count 2 2006.217.07:40:08.66#ibcon#about to write, iclass 36, count 2 2006.217.07:40:08.66#ibcon#wrote, iclass 36, count 2 2006.217.07:40:08.66#ibcon#about to read 3, iclass 36, count 2 2006.217.07:40:08.68#ibcon#read 3, iclass 36, count 2 2006.217.07:40:08.68#ibcon#about to read 4, iclass 36, count 2 2006.217.07:40:08.68#ibcon#read 4, iclass 36, count 2 2006.217.07:40:08.68#ibcon#about to read 5, iclass 36, count 2 2006.217.07:40:08.68#ibcon#read 5, iclass 36, count 2 2006.217.07:40:08.68#ibcon#about to read 6, iclass 36, count 2 2006.217.07:40:08.68#ibcon#read 6, iclass 36, count 2 2006.217.07:40:08.68#ibcon#end of sib2, iclass 36, count 2 2006.217.07:40:08.68#ibcon#*mode == 0, iclass 36, count 2 2006.217.07:40:08.68#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.217.07:40:08.68#ibcon#[25=AT03-04\r\n] 2006.217.07:40:08.68#ibcon#*before write, iclass 36, count 2 2006.217.07:40:08.68#ibcon#enter sib2, iclass 36, count 2 2006.217.07:40:08.68#ibcon#flushed, iclass 36, count 2 2006.217.07:40:08.68#ibcon#about to write, iclass 36, count 2 2006.217.07:40:08.68#ibcon#wrote, iclass 36, count 2 2006.217.07:40:08.68#ibcon#about to read 3, iclass 36, count 2 2006.217.07:40:08.71#ibcon#read 3, iclass 36, count 2 2006.217.07:40:08.71#ibcon#about to read 4, iclass 36, count 2 2006.217.07:40:08.72#ibcon#read 4, iclass 36, count 2 2006.217.07:40:08.72#ibcon#about to read 5, iclass 36, count 2 2006.217.07:40:08.72#ibcon#read 5, iclass 36, count 2 2006.217.07:40:08.72#ibcon#about to read 6, iclass 36, count 2 2006.217.07:40:08.72#ibcon#read 6, iclass 36, count 2 2006.217.07:40:08.72#ibcon#end of sib2, iclass 36, count 2 2006.217.07:40:08.72#ibcon#*after write, iclass 36, count 2 2006.217.07:40:08.72#ibcon#*before return 0, iclass 36, count 2 2006.217.07:40:08.72#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.217.07:40:08.72#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.217.07:40:08.72#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.217.07:40:08.72#ibcon#ireg 7 cls_cnt 0 2006.217.07:40:08.72#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.217.07:40:08.83#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.217.07:40:08.83#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.217.07:40:08.83#ibcon#enter wrdev, iclass 36, count 0 2006.217.07:40:08.83#ibcon#first serial, iclass 36, count 0 2006.217.07:40:08.83#ibcon#enter sib2, iclass 36, count 0 2006.217.07:40:08.83#ibcon#flushed, iclass 36, count 0 2006.217.07:40:08.84#ibcon#about to write, iclass 36, count 0 2006.217.07:40:08.84#ibcon#wrote, iclass 36, count 0 2006.217.07:40:08.84#ibcon#about to read 3, iclass 36, count 0 2006.217.07:40:08.85#ibcon#read 3, iclass 36, count 0 2006.217.07:40:08.85#ibcon#about to read 4, iclass 36, count 0 2006.217.07:40:08.85#ibcon#read 4, iclass 36, count 0 2006.217.07:40:08.85#ibcon#about to read 5, iclass 36, count 0 2006.217.07:40:08.86#ibcon#read 5, iclass 36, count 0 2006.217.07:40:08.86#ibcon#about to read 6, iclass 36, count 0 2006.217.07:40:08.86#ibcon#read 6, iclass 36, count 0 2006.217.07:40:08.86#ibcon#end of sib2, iclass 36, count 0 2006.217.07:40:08.86#ibcon#*mode == 0, iclass 36, count 0 2006.217.07:40:08.86#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.217.07:40:08.86#ibcon#[25=USB\r\n] 2006.217.07:40:08.86#ibcon#*before write, iclass 36, count 0 2006.217.07:40:08.86#ibcon#enter sib2, iclass 36, count 0 2006.217.07:40:08.86#ibcon#flushed, iclass 36, count 0 2006.217.07:40:08.86#ibcon#about to write, iclass 36, count 0 2006.217.07:40:08.86#ibcon#wrote, iclass 36, count 0 2006.217.07:40:08.86#ibcon#about to read 3, iclass 36, count 0 2006.217.07:40:08.88#ibcon#read 3, iclass 36, count 0 2006.217.07:40:08.88#ibcon#about to read 4, iclass 36, count 0 2006.217.07:40:08.88#ibcon#read 4, iclass 36, count 0 2006.217.07:40:08.88#ibcon#about to read 5, iclass 36, count 0 2006.217.07:40:08.89#ibcon#read 5, iclass 36, count 0 2006.217.07:40:08.89#ibcon#about to read 6, iclass 36, count 0 2006.217.07:40:08.89#ibcon#read 6, iclass 36, count 0 2006.217.07:40:08.89#ibcon#end of sib2, iclass 36, count 0 2006.217.07:40:08.89#ibcon#*after write, iclass 36, count 0 2006.217.07:40:08.89#ibcon#*before return 0, iclass 36, count 0 2006.217.07:40:08.89#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.217.07:40:08.89#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.217.07:40:08.89#ibcon#about to clear, iclass 36 cls_cnt 0 2006.217.07:40:08.89#ibcon#cleared, iclass 36 cls_cnt 0 2006.217.07:40:08.89$vc4f8/valo=4,832.99 2006.217.07:40:08.89#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.217.07:40:08.89#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.217.07:40:08.89#ibcon#ireg 17 cls_cnt 0 2006.217.07:40:08.89#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.217.07:40:08.89#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.217.07:40:08.89#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.217.07:40:08.89#ibcon#enter wrdev, iclass 38, count 0 2006.217.07:40:08.89#ibcon#first serial, iclass 38, count 0 2006.217.07:40:08.89#ibcon#enter sib2, iclass 38, count 0 2006.217.07:40:08.89#ibcon#flushed, iclass 38, count 0 2006.217.07:40:08.89#ibcon#about to write, iclass 38, count 0 2006.217.07:40:08.89#ibcon#wrote, iclass 38, count 0 2006.217.07:40:08.89#ibcon#about to read 3, iclass 38, count 0 2006.217.07:40:08.90#ibcon#read 3, iclass 38, count 0 2006.217.07:40:08.90#ibcon#about to read 4, iclass 38, count 0 2006.217.07:40:08.90#ibcon#read 4, iclass 38, count 0 2006.217.07:40:08.90#ibcon#about to read 5, iclass 38, count 0 2006.217.07:40:08.91#ibcon#read 5, iclass 38, count 0 2006.217.07:40:08.91#ibcon#about to read 6, iclass 38, count 0 2006.217.07:40:08.91#ibcon#read 6, iclass 38, count 0 2006.217.07:40:08.91#ibcon#end of sib2, iclass 38, count 0 2006.217.07:40:08.91#ibcon#*mode == 0, iclass 38, count 0 2006.217.07:40:08.91#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.217.07:40:08.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.217.07:40:08.91#ibcon#*before write, iclass 38, count 0 2006.217.07:40:08.91#ibcon#enter sib2, iclass 38, count 0 2006.217.07:40:08.91#ibcon#flushed, iclass 38, count 0 2006.217.07:40:08.91#ibcon#about to write, iclass 38, count 0 2006.217.07:40:08.91#ibcon#wrote, iclass 38, count 0 2006.217.07:40:08.91#ibcon#about to read 3, iclass 38, count 0 2006.217.07:40:08.94#ibcon#read 3, iclass 38, count 0 2006.217.07:40:08.94#ibcon#about to read 4, iclass 38, count 0 2006.217.07:40:08.94#ibcon#read 4, iclass 38, count 0 2006.217.07:40:08.95#ibcon#about to read 5, iclass 38, count 0 2006.217.07:40:08.95#ibcon#read 5, iclass 38, count 0 2006.217.07:40:08.95#ibcon#about to read 6, iclass 38, count 0 2006.217.07:40:08.95#ibcon#read 6, iclass 38, count 0 2006.217.07:40:08.95#ibcon#end of sib2, iclass 38, count 0 2006.217.07:40:08.95#ibcon#*after write, iclass 38, count 0 2006.217.07:40:08.95#ibcon#*before return 0, iclass 38, count 0 2006.217.07:40:08.95#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.217.07:40:08.95#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.217.07:40:08.95#ibcon#about to clear, iclass 38 cls_cnt 0 2006.217.07:40:08.95#ibcon#cleared, iclass 38 cls_cnt 0 2006.217.07:40:08.95$vc4f8/va=4,4 2006.217.07:40:08.95#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.217.07:40:08.95#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.217.07:40:08.95#ibcon#ireg 11 cls_cnt 2 2006.217.07:40:08.95#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.217.07:40:09.01#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.217.07:40:09.01#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.217.07:40:09.01#ibcon#enter wrdev, iclass 40, count 2 2006.217.07:40:09.01#ibcon#first serial, iclass 40, count 2 2006.217.07:40:09.01#ibcon#enter sib2, iclass 40, count 2 2006.217.07:40:09.01#ibcon#flushed, iclass 40, count 2 2006.217.07:40:09.01#ibcon#about to write, iclass 40, count 2 2006.217.07:40:09.01#ibcon#wrote, iclass 40, count 2 2006.217.07:40:09.01#ibcon#about to read 3, iclass 40, count 2 2006.217.07:40:09.02#ibcon#read 3, iclass 40, count 2 2006.217.07:40:09.02#ibcon#about to read 4, iclass 40, count 2 2006.217.07:40:09.02#ibcon#read 4, iclass 40, count 2 2006.217.07:40:09.02#ibcon#about to read 5, iclass 40, count 2 2006.217.07:40:09.03#ibcon#read 5, iclass 40, count 2 2006.217.07:40:09.03#ibcon#about to read 6, iclass 40, count 2 2006.217.07:40:09.03#ibcon#read 6, iclass 40, count 2 2006.217.07:40:09.03#ibcon#end of sib2, iclass 40, count 2 2006.217.07:40:09.03#ibcon#*mode == 0, iclass 40, count 2 2006.217.07:40:09.03#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.217.07:40:09.03#ibcon#[25=AT04-04\r\n] 2006.217.07:40:09.03#ibcon#*before write, iclass 40, count 2 2006.217.07:40:09.03#ibcon#enter sib2, iclass 40, count 2 2006.217.07:40:09.03#ibcon#flushed, iclass 40, count 2 2006.217.07:40:09.03#ibcon#about to write, iclass 40, count 2 2006.217.07:40:09.03#ibcon#wrote, iclass 40, count 2 2006.217.07:40:09.03#ibcon#about to read 3, iclass 40, count 2 2006.217.07:40:09.05#ibcon#read 3, iclass 40, count 2 2006.217.07:40:09.05#ibcon#about to read 4, iclass 40, count 2 2006.217.07:40:09.06#ibcon#read 4, iclass 40, count 2 2006.217.07:40:09.06#ibcon#about to read 5, iclass 40, count 2 2006.217.07:40:09.06#ibcon#read 5, iclass 40, count 2 2006.217.07:40:09.06#ibcon#about to read 6, iclass 40, count 2 2006.217.07:40:09.06#ibcon#read 6, iclass 40, count 2 2006.217.07:40:09.06#ibcon#end of sib2, iclass 40, count 2 2006.217.07:40:09.06#ibcon#*after write, iclass 40, count 2 2006.217.07:40:09.06#ibcon#*before return 0, iclass 40, count 2 2006.217.07:40:09.06#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.217.07:40:09.06#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.217.07:40:09.06#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.217.07:40:09.06#ibcon#ireg 7 cls_cnt 0 2006.217.07:40:09.06#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.217.07:40:09.17#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.217.07:40:09.17#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.217.07:40:09.17#ibcon#enter wrdev, iclass 40, count 0 2006.217.07:40:09.17#ibcon#first serial, iclass 40, count 0 2006.217.07:40:09.17#ibcon#enter sib2, iclass 40, count 0 2006.217.07:40:09.17#ibcon#flushed, iclass 40, count 0 2006.217.07:40:09.17#ibcon#about to write, iclass 40, count 0 2006.217.07:40:09.18#ibcon#wrote, iclass 40, count 0 2006.217.07:40:09.18#ibcon#about to read 3, iclass 40, count 0 2006.217.07:40:09.19#ibcon#read 3, iclass 40, count 0 2006.217.07:40:09.19#ibcon#about to read 4, iclass 40, count 0 2006.217.07:40:09.19#ibcon#read 4, iclass 40, count 0 2006.217.07:40:09.19#ibcon#about to read 5, iclass 40, count 0 2006.217.07:40:09.19#ibcon#read 5, iclass 40, count 0 2006.217.07:40:09.20#ibcon#about to read 6, iclass 40, count 0 2006.217.07:40:09.20#ibcon#read 6, iclass 40, count 0 2006.217.07:40:09.20#ibcon#end of sib2, iclass 40, count 0 2006.217.07:40:09.20#ibcon#*mode == 0, iclass 40, count 0 2006.217.07:40:09.20#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.217.07:40:09.20#ibcon#[25=USB\r\n] 2006.217.07:40:09.20#ibcon#*before write, iclass 40, count 0 2006.217.07:40:09.20#ibcon#enter sib2, iclass 40, count 0 2006.217.07:40:09.20#ibcon#flushed, iclass 40, count 0 2006.217.07:40:09.20#ibcon#about to write, iclass 40, count 0 2006.217.07:40:09.20#ibcon#wrote, iclass 40, count 0 2006.217.07:40:09.20#ibcon#about to read 3, iclass 40, count 0 2006.217.07:40:09.22#ibcon#read 3, iclass 40, count 0 2006.217.07:40:09.22#ibcon#about to read 4, iclass 40, count 0 2006.217.07:40:09.23#ibcon#read 4, iclass 40, count 0 2006.217.07:40:09.23#ibcon#about to read 5, iclass 40, count 0 2006.217.07:40:09.23#ibcon#read 5, iclass 40, count 0 2006.217.07:40:09.23#ibcon#about to read 6, iclass 40, count 0 2006.217.07:40:09.23#ibcon#read 6, iclass 40, count 0 2006.217.07:40:09.23#ibcon#end of sib2, iclass 40, count 0 2006.217.07:40:09.23#ibcon#*after write, iclass 40, count 0 2006.217.07:40:09.23#ibcon#*before return 0, iclass 40, count 0 2006.217.07:40:09.23#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.217.07:40:09.23#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.217.07:40:09.23#ibcon#about to clear, iclass 40 cls_cnt 0 2006.217.07:40:09.23#ibcon#cleared, iclass 40 cls_cnt 0 2006.217.07:40:09.23$vc4f8/valo=5,652.99 2006.217.07:40:09.23#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.217.07:40:09.23#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.217.07:40:09.23#ibcon#ireg 17 cls_cnt 0 2006.217.07:40:09.23#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.217.07:40:09.23#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.217.07:40:09.23#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.217.07:40:09.23#ibcon#enter wrdev, iclass 4, count 0 2006.217.07:40:09.23#ibcon#first serial, iclass 4, count 0 2006.217.07:40:09.23#ibcon#enter sib2, iclass 4, count 0 2006.217.07:40:09.23#ibcon#flushed, iclass 4, count 0 2006.217.07:40:09.23#ibcon#about to write, iclass 4, count 0 2006.217.07:40:09.23#ibcon#wrote, iclass 4, count 0 2006.217.07:40:09.23#ibcon#about to read 3, iclass 4, count 0 2006.217.07:40:09.24#ibcon#read 3, iclass 4, count 0 2006.217.07:40:09.24#ibcon#about to read 4, iclass 4, count 0 2006.217.07:40:09.24#ibcon#read 4, iclass 4, count 0 2006.217.07:40:09.24#ibcon#about to read 5, iclass 4, count 0 2006.217.07:40:09.25#ibcon#read 5, iclass 4, count 0 2006.217.07:40:09.25#ibcon#about to read 6, iclass 4, count 0 2006.217.07:40:09.25#ibcon#read 6, iclass 4, count 0 2006.217.07:40:09.25#ibcon#end of sib2, iclass 4, count 0 2006.217.07:40:09.25#ibcon#*mode == 0, iclass 4, count 0 2006.217.07:40:09.25#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.217.07:40:09.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.217.07:40:09.25#ibcon#*before write, iclass 4, count 0 2006.217.07:40:09.25#ibcon#enter sib2, iclass 4, count 0 2006.217.07:40:09.25#ibcon#flushed, iclass 4, count 0 2006.217.07:40:09.25#ibcon#about to write, iclass 4, count 0 2006.217.07:40:09.25#ibcon#wrote, iclass 4, count 0 2006.217.07:40:09.25#ibcon#about to read 3, iclass 4, count 0 2006.217.07:40:09.28#ibcon#read 3, iclass 4, count 0 2006.217.07:40:09.28#ibcon#about to read 4, iclass 4, count 0 2006.217.07:40:09.28#ibcon#read 4, iclass 4, count 0 2006.217.07:40:09.28#ibcon#about to read 5, iclass 4, count 0 2006.217.07:40:09.29#ibcon#read 5, iclass 4, count 0 2006.217.07:40:09.29#ibcon#about to read 6, iclass 4, count 0 2006.217.07:40:09.29#ibcon#read 6, iclass 4, count 0 2006.217.07:40:09.29#ibcon#end of sib2, iclass 4, count 0 2006.217.07:40:09.29#ibcon#*after write, iclass 4, count 0 2006.217.07:40:09.29#ibcon#*before return 0, iclass 4, count 0 2006.217.07:40:09.29#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.217.07:40:09.29#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.217.07:40:09.29#ibcon#about to clear, iclass 4 cls_cnt 0 2006.217.07:40:09.29#ibcon#cleared, iclass 4 cls_cnt 0 2006.217.07:40:09.29$vc4f8/va=5,7 2006.217.07:40:09.29#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.217.07:40:09.29#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.217.07:40:09.29#ibcon#ireg 11 cls_cnt 2 2006.217.07:40:09.29#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.217.07:40:09.34#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.217.07:40:09.34#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.217.07:40:09.34#ibcon#enter wrdev, iclass 6, count 2 2006.217.07:40:09.34#ibcon#first serial, iclass 6, count 2 2006.217.07:40:09.34#ibcon#enter sib2, iclass 6, count 2 2006.217.07:40:09.35#ibcon#flushed, iclass 6, count 2 2006.217.07:40:09.35#ibcon#about to write, iclass 6, count 2 2006.217.07:40:09.35#ibcon#wrote, iclass 6, count 2 2006.217.07:40:09.35#ibcon#about to read 3, iclass 6, count 2 2006.217.07:40:09.36#ibcon#read 3, iclass 6, count 2 2006.217.07:40:09.36#ibcon#about to read 4, iclass 6, count 2 2006.217.07:40:09.36#ibcon#read 4, iclass 6, count 2 2006.217.07:40:09.36#ibcon#about to read 5, iclass 6, count 2 2006.217.07:40:09.37#ibcon#read 5, iclass 6, count 2 2006.217.07:40:09.37#ibcon#about to read 6, iclass 6, count 2 2006.217.07:40:09.37#ibcon#read 6, iclass 6, count 2 2006.217.07:40:09.37#ibcon#end of sib2, iclass 6, count 2 2006.217.07:40:09.37#ibcon#*mode == 0, iclass 6, count 2 2006.217.07:40:09.37#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.217.07:40:09.37#ibcon#[25=AT05-07\r\n] 2006.217.07:40:09.37#ibcon#*before write, iclass 6, count 2 2006.217.07:40:09.37#ibcon#enter sib2, iclass 6, count 2 2006.217.07:40:09.37#ibcon#flushed, iclass 6, count 2 2006.217.07:40:09.37#ibcon#about to write, iclass 6, count 2 2006.217.07:40:09.37#ibcon#wrote, iclass 6, count 2 2006.217.07:40:09.37#ibcon#about to read 3, iclass 6, count 2 2006.217.07:40:09.39#ibcon#read 3, iclass 6, count 2 2006.217.07:40:09.40#ibcon#about to read 4, iclass 6, count 2 2006.217.07:40:09.40#ibcon#read 4, iclass 6, count 2 2006.217.07:40:09.40#ibcon#about to read 5, iclass 6, count 2 2006.217.07:40:09.40#ibcon#read 5, iclass 6, count 2 2006.217.07:40:09.40#ibcon#about to read 6, iclass 6, count 2 2006.217.07:40:09.40#ibcon#read 6, iclass 6, count 2 2006.217.07:40:09.40#ibcon#end of sib2, iclass 6, count 2 2006.217.07:40:09.40#ibcon#*after write, iclass 6, count 2 2006.217.07:40:09.40#ibcon#*before return 0, iclass 6, count 2 2006.217.07:40:09.40#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.217.07:40:09.40#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.217.07:40:09.40#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.217.07:40:09.40#ibcon#ireg 7 cls_cnt 0 2006.217.07:40:09.40#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.217.07:40:09.51#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.217.07:40:09.51#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.217.07:40:09.51#ibcon#enter wrdev, iclass 6, count 0 2006.217.07:40:09.51#ibcon#first serial, iclass 6, count 0 2006.217.07:40:09.51#ibcon#enter sib2, iclass 6, count 0 2006.217.07:40:09.51#ibcon#flushed, iclass 6, count 0 2006.217.07:40:09.52#ibcon#about to write, iclass 6, count 0 2006.217.07:40:09.52#ibcon#wrote, iclass 6, count 0 2006.217.07:40:09.52#ibcon#about to read 3, iclass 6, count 0 2006.217.07:40:09.53#ibcon#read 3, iclass 6, count 0 2006.217.07:40:09.53#ibcon#about to read 4, iclass 6, count 0 2006.217.07:40:09.53#ibcon#read 4, iclass 6, count 0 2006.217.07:40:09.53#ibcon#about to read 5, iclass 6, count 0 2006.217.07:40:09.54#ibcon#read 5, iclass 6, count 0 2006.217.07:40:09.54#ibcon#about to read 6, iclass 6, count 0 2006.217.07:40:09.54#ibcon#read 6, iclass 6, count 0 2006.217.07:40:09.54#ibcon#end of sib2, iclass 6, count 0 2006.217.07:40:09.54#ibcon#*mode == 0, iclass 6, count 0 2006.217.07:40:09.54#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.217.07:40:09.54#ibcon#[25=USB\r\n] 2006.217.07:40:09.54#ibcon#*before write, iclass 6, count 0 2006.217.07:40:09.54#ibcon#enter sib2, iclass 6, count 0 2006.217.07:40:09.54#ibcon#flushed, iclass 6, count 0 2006.217.07:40:09.54#ibcon#about to write, iclass 6, count 0 2006.217.07:40:09.54#ibcon#wrote, iclass 6, count 0 2006.217.07:40:09.54#ibcon#about to read 3, iclass 6, count 0 2006.217.07:40:09.56#ibcon#read 3, iclass 6, count 0 2006.217.07:40:09.56#ibcon#about to read 4, iclass 6, count 0 2006.217.07:40:09.56#ibcon#read 4, iclass 6, count 0 2006.217.07:40:09.56#ibcon#about to read 5, iclass 6, count 0 2006.217.07:40:09.57#ibcon#read 5, iclass 6, count 0 2006.217.07:40:09.57#ibcon#about to read 6, iclass 6, count 0 2006.217.07:40:09.57#ibcon#read 6, iclass 6, count 0 2006.217.07:40:09.57#ibcon#end of sib2, iclass 6, count 0 2006.217.07:40:09.57#ibcon#*after write, iclass 6, count 0 2006.217.07:40:09.57#ibcon#*before return 0, iclass 6, count 0 2006.217.07:40:09.57#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.217.07:40:09.57#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.217.07:40:09.57#ibcon#about to clear, iclass 6 cls_cnt 0 2006.217.07:40:09.57#ibcon#cleared, iclass 6 cls_cnt 0 2006.217.07:40:09.57$vc4f8/valo=6,772.99 2006.217.07:40:09.57#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.217.07:40:09.57#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.217.07:40:09.57#ibcon#ireg 17 cls_cnt 0 2006.217.07:40:09.57#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.217.07:40:09.57#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.217.07:40:09.57#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.217.07:40:09.57#ibcon#enter wrdev, iclass 10, count 0 2006.217.07:40:09.57#ibcon#first serial, iclass 10, count 0 2006.217.07:40:09.57#ibcon#enter sib2, iclass 10, count 0 2006.217.07:40:09.57#ibcon#flushed, iclass 10, count 0 2006.217.07:40:09.57#ibcon#about to write, iclass 10, count 0 2006.217.07:40:09.57#ibcon#wrote, iclass 10, count 0 2006.217.07:40:09.57#ibcon#about to read 3, iclass 10, count 0 2006.217.07:40:09.58#ibcon#read 3, iclass 10, count 0 2006.217.07:40:09.58#ibcon#about to read 4, iclass 10, count 0 2006.217.07:40:09.58#ibcon#read 4, iclass 10, count 0 2006.217.07:40:09.58#ibcon#about to read 5, iclass 10, count 0 2006.217.07:40:09.59#ibcon#read 5, iclass 10, count 0 2006.217.07:40:09.59#ibcon#about to read 6, iclass 10, count 0 2006.217.07:40:09.59#ibcon#read 6, iclass 10, count 0 2006.217.07:40:09.59#ibcon#end of sib2, iclass 10, count 0 2006.217.07:40:09.59#ibcon#*mode == 0, iclass 10, count 0 2006.217.07:40:09.59#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.217.07:40:09.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.217.07:40:09.59#ibcon#*before write, iclass 10, count 0 2006.217.07:40:09.59#ibcon#enter sib2, iclass 10, count 0 2006.217.07:40:09.59#ibcon#flushed, iclass 10, count 0 2006.217.07:40:09.59#ibcon#about to write, iclass 10, count 0 2006.217.07:40:09.59#ibcon#wrote, iclass 10, count 0 2006.217.07:40:09.59#ibcon#about to read 3, iclass 10, count 0 2006.217.07:40:09.62#ibcon#read 3, iclass 10, count 0 2006.217.07:40:09.63#ibcon#about to read 4, iclass 10, count 0 2006.217.07:40:09.63#ibcon#read 4, iclass 10, count 0 2006.217.07:40:09.63#ibcon#about to read 5, iclass 10, count 0 2006.217.07:40:09.63#ibcon#read 5, iclass 10, count 0 2006.217.07:40:09.63#ibcon#about to read 6, iclass 10, count 0 2006.217.07:40:09.63#ibcon#read 6, iclass 10, count 0 2006.217.07:40:09.63#ibcon#end of sib2, iclass 10, count 0 2006.217.07:40:09.63#ibcon#*after write, iclass 10, count 0 2006.217.07:40:09.63#ibcon#*before return 0, iclass 10, count 0 2006.217.07:40:09.63#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.217.07:40:09.63#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.217.07:40:09.63#ibcon#about to clear, iclass 10 cls_cnt 0 2006.217.07:40:09.63#ibcon#cleared, iclass 10 cls_cnt 0 2006.217.07:40:09.63$vc4f8/va=6,6 2006.217.07:40:09.63#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.217.07:40:09.63#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.217.07:40:09.63#ibcon#ireg 11 cls_cnt 2 2006.217.07:40:09.63#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.217.07:40:09.69#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.217.07:40:09.69#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.217.07:40:09.69#ibcon#enter wrdev, iclass 12, count 2 2006.217.07:40:09.69#ibcon#first serial, iclass 12, count 2 2006.217.07:40:09.69#ibcon#enter sib2, iclass 12, count 2 2006.217.07:40:09.69#ibcon#flushed, iclass 12, count 2 2006.217.07:40:09.69#ibcon#about to write, iclass 12, count 2 2006.217.07:40:09.69#ibcon#wrote, iclass 12, count 2 2006.217.07:40:09.69#ibcon#about to read 3, iclass 12, count 2 2006.217.07:40:09.70#ibcon#read 3, iclass 12, count 2 2006.217.07:40:09.70#ibcon#about to read 4, iclass 12, count 2 2006.217.07:40:09.70#ibcon#read 4, iclass 12, count 2 2006.217.07:40:09.71#ibcon#about to read 5, iclass 12, count 2 2006.217.07:40:09.71#ibcon#read 5, iclass 12, count 2 2006.217.07:40:09.71#ibcon#about to read 6, iclass 12, count 2 2006.217.07:40:09.71#ibcon#read 6, iclass 12, count 2 2006.217.07:40:09.71#ibcon#end of sib2, iclass 12, count 2 2006.217.07:40:09.71#ibcon#*mode == 0, iclass 12, count 2 2006.217.07:40:09.71#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.217.07:40:09.71#ibcon#[25=AT06-06\r\n] 2006.217.07:40:09.71#ibcon#*before write, iclass 12, count 2 2006.217.07:40:09.71#ibcon#enter sib2, iclass 12, count 2 2006.217.07:40:09.71#ibcon#flushed, iclass 12, count 2 2006.217.07:40:09.71#ibcon#about to write, iclass 12, count 2 2006.217.07:40:09.71#ibcon#wrote, iclass 12, count 2 2006.217.07:40:09.71#ibcon#about to read 3, iclass 12, count 2 2006.217.07:40:09.73#ibcon#read 3, iclass 12, count 2 2006.217.07:40:09.73#ibcon#about to read 4, iclass 12, count 2 2006.217.07:40:09.74#ibcon#read 4, iclass 12, count 2 2006.217.07:40:09.74#ibcon#about to read 5, iclass 12, count 2 2006.217.07:40:09.74#ibcon#read 5, iclass 12, count 2 2006.217.07:40:09.74#ibcon#about to read 6, iclass 12, count 2 2006.217.07:40:09.74#ibcon#read 6, iclass 12, count 2 2006.217.07:40:09.74#ibcon#end of sib2, iclass 12, count 2 2006.217.07:40:09.74#ibcon#*after write, iclass 12, count 2 2006.217.07:40:09.74#ibcon#*before return 0, iclass 12, count 2 2006.217.07:40:09.74#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.217.07:40:09.74#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.217.07:40:09.74#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.217.07:40:09.74#ibcon#ireg 7 cls_cnt 0 2006.217.07:40:09.74#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.217.07:40:09.85#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.217.07:40:09.85#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.217.07:40:09.85#ibcon#enter wrdev, iclass 12, count 0 2006.217.07:40:09.85#ibcon#first serial, iclass 12, count 0 2006.217.07:40:09.85#ibcon#enter sib2, iclass 12, count 0 2006.217.07:40:09.85#ibcon#flushed, iclass 12, count 0 2006.217.07:40:09.86#ibcon#about to write, iclass 12, count 0 2006.217.07:40:09.86#ibcon#wrote, iclass 12, count 0 2006.217.07:40:09.86#ibcon#about to read 3, iclass 12, count 0 2006.217.07:40:09.87#ibcon#read 3, iclass 12, count 0 2006.217.07:40:09.87#ibcon#about to read 4, iclass 12, count 0 2006.217.07:40:09.87#ibcon#read 4, iclass 12, count 0 2006.217.07:40:09.87#ibcon#about to read 5, iclass 12, count 0 2006.217.07:40:09.88#ibcon#read 5, iclass 12, count 0 2006.217.07:40:09.88#ibcon#about to read 6, iclass 12, count 0 2006.217.07:40:09.88#ibcon#read 6, iclass 12, count 0 2006.217.07:40:09.88#ibcon#end of sib2, iclass 12, count 0 2006.217.07:40:09.88#ibcon#*mode == 0, iclass 12, count 0 2006.217.07:40:09.88#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.217.07:40:09.88#ibcon#[25=USB\r\n] 2006.217.07:40:09.88#ibcon#*before write, iclass 12, count 0 2006.217.07:40:09.88#ibcon#enter sib2, iclass 12, count 0 2006.217.07:40:09.88#ibcon#flushed, iclass 12, count 0 2006.217.07:40:09.88#ibcon#about to write, iclass 12, count 0 2006.217.07:40:09.88#ibcon#wrote, iclass 12, count 0 2006.217.07:40:09.88#ibcon#about to read 3, iclass 12, count 0 2006.217.07:40:09.90#ibcon#read 3, iclass 12, count 0 2006.217.07:40:09.90#ibcon#about to read 4, iclass 12, count 0 2006.217.07:40:09.90#ibcon#read 4, iclass 12, count 0 2006.217.07:40:09.90#ibcon#about to read 5, iclass 12, count 0 2006.217.07:40:09.91#ibcon#read 5, iclass 12, count 0 2006.217.07:40:09.91#ibcon#about to read 6, iclass 12, count 0 2006.217.07:40:09.91#ibcon#read 6, iclass 12, count 0 2006.217.07:40:09.91#ibcon#end of sib2, iclass 12, count 0 2006.217.07:40:09.91#ibcon#*after write, iclass 12, count 0 2006.217.07:40:09.91#ibcon#*before return 0, iclass 12, count 0 2006.217.07:40:09.91#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.217.07:40:09.91#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.217.07:40:09.91#ibcon#about to clear, iclass 12 cls_cnt 0 2006.217.07:40:09.91#ibcon#cleared, iclass 12 cls_cnt 0 2006.217.07:40:09.91$vc4f8/valo=7,832.99 2006.217.07:40:09.91#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.217.07:40:09.91#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.217.07:40:09.91#ibcon#ireg 17 cls_cnt 0 2006.217.07:40:09.91#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.217.07:40:09.91#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.217.07:40:09.91#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.217.07:40:09.91#ibcon#enter wrdev, iclass 14, count 0 2006.217.07:40:09.91#ibcon#first serial, iclass 14, count 0 2006.217.07:40:09.91#ibcon#enter sib2, iclass 14, count 0 2006.217.07:40:09.91#ibcon#flushed, iclass 14, count 0 2006.217.07:40:09.91#ibcon#about to write, iclass 14, count 0 2006.217.07:40:09.91#ibcon#wrote, iclass 14, count 0 2006.217.07:40:09.91#ibcon#about to read 3, iclass 14, count 0 2006.217.07:40:09.92#ibcon#read 3, iclass 14, count 0 2006.217.07:40:09.92#ibcon#about to read 4, iclass 14, count 0 2006.217.07:40:09.92#ibcon#read 4, iclass 14, count 0 2006.217.07:40:09.92#ibcon#about to read 5, iclass 14, count 0 2006.217.07:40:09.93#ibcon#read 5, iclass 14, count 0 2006.217.07:40:09.93#ibcon#about to read 6, iclass 14, count 0 2006.217.07:40:09.93#ibcon#read 6, iclass 14, count 0 2006.217.07:40:09.93#ibcon#end of sib2, iclass 14, count 0 2006.217.07:40:09.93#ibcon#*mode == 0, iclass 14, count 0 2006.217.07:40:09.93#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.217.07:40:09.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.217.07:40:09.93#ibcon#*before write, iclass 14, count 0 2006.217.07:40:09.93#ibcon#enter sib2, iclass 14, count 0 2006.217.07:40:09.93#ibcon#flushed, iclass 14, count 0 2006.217.07:40:09.93#ibcon#about to write, iclass 14, count 0 2006.217.07:40:09.93#ibcon#wrote, iclass 14, count 0 2006.217.07:40:09.93#ibcon#about to read 3, iclass 14, count 0 2006.217.07:40:09.96#ibcon#read 3, iclass 14, count 0 2006.217.07:40:09.96#ibcon#about to read 4, iclass 14, count 0 2006.217.07:40:09.96#ibcon#read 4, iclass 14, count 0 2006.217.07:40:09.96#ibcon#about to read 5, iclass 14, count 0 2006.217.07:40:09.97#ibcon#read 5, iclass 14, count 0 2006.217.07:40:09.97#ibcon#about to read 6, iclass 14, count 0 2006.217.07:40:09.97#ibcon#read 6, iclass 14, count 0 2006.217.07:40:09.97#ibcon#end of sib2, iclass 14, count 0 2006.217.07:40:09.97#ibcon#*after write, iclass 14, count 0 2006.217.07:40:09.97#ibcon#*before return 0, iclass 14, count 0 2006.217.07:40:09.97#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.217.07:40:09.97#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.217.07:40:09.97#ibcon#about to clear, iclass 14 cls_cnt 0 2006.217.07:40:09.97#ibcon#cleared, iclass 14 cls_cnt 0 2006.217.07:40:09.97$vc4f8/va=7,6 2006.217.07:40:09.97#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.217.07:40:09.97#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.217.07:40:09.97#ibcon#ireg 11 cls_cnt 2 2006.217.07:40:09.97#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.217.07:40:10.02#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.217.07:40:10.02#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.217.07:40:10.02#ibcon#enter wrdev, iclass 16, count 2 2006.217.07:40:10.02#ibcon#first serial, iclass 16, count 2 2006.217.07:40:10.02#ibcon#enter sib2, iclass 16, count 2 2006.217.07:40:10.03#ibcon#flushed, iclass 16, count 2 2006.217.07:40:10.03#ibcon#about to write, iclass 16, count 2 2006.217.07:40:10.03#ibcon#wrote, iclass 16, count 2 2006.217.07:40:10.03#ibcon#about to read 3, iclass 16, count 2 2006.217.07:40:10.04#ibcon#read 3, iclass 16, count 2 2006.217.07:40:10.04#ibcon#about to read 4, iclass 16, count 2 2006.217.07:40:10.04#ibcon#read 4, iclass 16, count 2 2006.217.07:40:10.04#ibcon#about to read 5, iclass 16, count 2 2006.217.07:40:10.05#ibcon#read 5, iclass 16, count 2 2006.217.07:40:10.05#ibcon#about to read 6, iclass 16, count 2 2006.217.07:40:10.05#ibcon#read 6, iclass 16, count 2 2006.217.07:40:10.05#ibcon#end of sib2, iclass 16, count 2 2006.217.07:40:10.05#ibcon#*mode == 0, iclass 16, count 2 2006.217.07:40:10.05#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.217.07:40:10.05#ibcon#[25=AT07-06\r\n] 2006.217.07:40:10.05#ibcon#*before write, iclass 16, count 2 2006.217.07:40:10.05#ibcon#enter sib2, iclass 16, count 2 2006.217.07:40:10.05#ibcon#flushed, iclass 16, count 2 2006.217.07:40:10.05#ibcon#about to write, iclass 16, count 2 2006.217.07:40:10.05#ibcon#wrote, iclass 16, count 2 2006.217.07:40:10.05#ibcon#about to read 3, iclass 16, count 2 2006.217.07:40:10.07#ibcon#read 3, iclass 16, count 2 2006.217.07:40:10.07#ibcon#about to read 4, iclass 16, count 2 2006.217.07:40:10.07#ibcon#read 4, iclass 16, count 2 2006.217.07:40:10.07#ibcon#about to read 5, iclass 16, count 2 2006.217.07:40:10.08#ibcon#read 5, iclass 16, count 2 2006.217.07:40:10.08#ibcon#about to read 6, iclass 16, count 2 2006.217.07:40:10.08#ibcon#read 6, iclass 16, count 2 2006.217.07:40:10.08#ibcon#end of sib2, iclass 16, count 2 2006.217.07:40:10.08#ibcon#*after write, iclass 16, count 2 2006.217.07:40:10.08#ibcon#*before return 0, iclass 16, count 2 2006.217.07:40:10.08#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.217.07:40:10.08#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.217.07:40:10.08#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.217.07:40:10.08#ibcon#ireg 7 cls_cnt 0 2006.217.07:40:10.08#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.217.07:40:10.19#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.217.07:40:10.19#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.217.07:40:10.19#ibcon#enter wrdev, iclass 16, count 0 2006.217.07:40:10.19#ibcon#first serial, iclass 16, count 0 2006.217.07:40:10.19#ibcon#enter sib2, iclass 16, count 0 2006.217.07:40:10.19#ibcon#flushed, iclass 16, count 0 2006.217.07:40:10.20#ibcon#about to write, iclass 16, count 0 2006.217.07:40:10.20#ibcon#wrote, iclass 16, count 0 2006.217.07:40:10.20#ibcon#about to read 3, iclass 16, count 0 2006.217.07:40:10.21#ibcon#read 3, iclass 16, count 0 2006.217.07:40:10.21#ibcon#about to read 4, iclass 16, count 0 2006.217.07:40:10.21#ibcon#read 4, iclass 16, count 0 2006.217.07:40:10.21#ibcon#about to read 5, iclass 16, count 0 2006.217.07:40:10.21#ibcon#read 5, iclass 16, count 0 2006.217.07:40:10.22#ibcon#about to read 6, iclass 16, count 0 2006.217.07:40:10.22#ibcon#read 6, iclass 16, count 0 2006.217.07:40:10.22#ibcon#end of sib2, iclass 16, count 0 2006.217.07:40:10.22#ibcon#*mode == 0, iclass 16, count 0 2006.217.07:40:10.22#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.217.07:40:10.22#ibcon#[25=USB\r\n] 2006.217.07:40:10.22#ibcon#*before write, iclass 16, count 0 2006.217.07:40:10.22#ibcon#enter sib2, iclass 16, count 0 2006.217.07:40:10.22#ibcon#flushed, iclass 16, count 0 2006.217.07:40:10.22#ibcon#about to write, iclass 16, count 0 2006.217.07:40:10.22#ibcon#wrote, iclass 16, count 0 2006.217.07:40:10.22#ibcon#about to read 3, iclass 16, count 0 2006.217.07:40:10.24#ibcon#read 3, iclass 16, count 0 2006.217.07:40:10.24#ibcon#about to read 4, iclass 16, count 0 2006.217.07:40:10.25#ibcon#read 4, iclass 16, count 0 2006.217.07:40:10.25#ibcon#about to read 5, iclass 16, count 0 2006.217.07:40:10.25#ibcon#read 5, iclass 16, count 0 2006.217.07:40:10.25#ibcon#about to read 6, iclass 16, count 0 2006.217.07:40:10.25#ibcon#read 6, iclass 16, count 0 2006.217.07:40:10.25#ibcon#end of sib2, iclass 16, count 0 2006.217.07:40:10.25#ibcon#*after write, iclass 16, count 0 2006.217.07:40:10.25#ibcon#*before return 0, iclass 16, count 0 2006.217.07:40:10.25#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.217.07:40:10.25#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.217.07:40:10.25#ibcon#about to clear, iclass 16 cls_cnt 0 2006.217.07:40:10.25#ibcon#cleared, iclass 16 cls_cnt 0 2006.217.07:40:10.25$vc4f8/valo=8,852.99 2006.217.07:40:10.25#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.217.07:40:10.25#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.217.07:40:10.25#ibcon#ireg 17 cls_cnt 0 2006.217.07:40:10.25#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.217.07:40:10.25#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.217.07:40:10.25#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.217.07:40:10.25#ibcon#enter wrdev, iclass 18, count 0 2006.217.07:40:10.25#ibcon#first serial, iclass 18, count 0 2006.217.07:40:10.25#ibcon#enter sib2, iclass 18, count 0 2006.217.07:40:10.25#ibcon#flushed, iclass 18, count 0 2006.217.07:40:10.25#ibcon#about to write, iclass 18, count 0 2006.217.07:40:10.25#ibcon#wrote, iclass 18, count 0 2006.217.07:40:10.25#ibcon#about to read 3, iclass 18, count 0 2006.217.07:40:10.26#ibcon#read 3, iclass 18, count 0 2006.217.07:40:10.26#ibcon#about to read 4, iclass 18, count 0 2006.217.07:40:10.26#ibcon#read 4, iclass 18, count 0 2006.217.07:40:10.26#ibcon#about to read 5, iclass 18, count 0 2006.217.07:40:10.27#ibcon#read 5, iclass 18, count 0 2006.217.07:40:10.27#ibcon#about to read 6, iclass 18, count 0 2006.217.07:40:10.27#ibcon#read 6, iclass 18, count 0 2006.217.07:40:10.27#ibcon#end of sib2, iclass 18, count 0 2006.217.07:40:10.27#ibcon#*mode == 0, iclass 18, count 0 2006.217.07:40:10.27#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.217.07:40:10.27#ibcon#[26=FRQ=08,852.99\r\n] 2006.217.07:40:10.27#ibcon#*before write, iclass 18, count 0 2006.217.07:40:10.27#ibcon#enter sib2, iclass 18, count 0 2006.217.07:40:10.27#ibcon#flushed, iclass 18, count 0 2006.217.07:40:10.27#ibcon#about to write, iclass 18, count 0 2006.217.07:40:10.27#ibcon#wrote, iclass 18, count 0 2006.217.07:40:10.27#ibcon#about to read 3, iclass 18, count 0 2006.217.07:40:10.30#ibcon#read 3, iclass 18, count 0 2006.217.07:40:10.30#ibcon#about to read 4, iclass 18, count 0 2006.217.07:40:10.30#ibcon#read 4, iclass 18, count 0 2006.217.07:40:10.30#ibcon#about to read 5, iclass 18, count 0 2006.217.07:40:10.31#ibcon#read 5, iclass 18, count 0 2006.217.07:40:10.31#ibcon#about to read 6, iclass 18, count 0 2006.217.07:40:10.31#ibcon#read 6, iclass 18, count 0 2006.217.07:40:10.31#ibcon#end of sib2, iclass 18, count 0 2006.217.07:40:10.31#ibcon#*after write, iclass 18, count 0 2006.217.07:40:10.31#ibcon#*before return 0, iclass 18, count 0 2006.217.07:40:10.31#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.217.07:40:10.31#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.217.07:40:10.31#ibcon#about to clear, iclass 18 cls_cnt 0 2006.217.07:40:10.31#ibcon#cleared, iclass 18 cls_cnt 0 2006.217.07:40:10.31$vc4f8/va=8,7 2006.217.07:40:10.31#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.217.07:40:10.31#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.217.07:40:10.31#ibcon#ireg 11 cls_cnt 2 2006.217.07:40:10.31#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.217.07:40:10.36#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.217.07:40:10.36#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.217.07:40:10.36#ibcon#enter wrdev, iclass 20, count 2 2006.217.07:40:10.37#ibcon#first serial, iclass 20, count 2 2006.217.07:40:10.37#ibcon#enter sib2, iclass 20, count 2 2006.217.07:40:10.37#ibcon#flushed, iclass 20, count 2 2006.217.07:40:10.37#ibcon#about to write, iclass 20, count 2 2006.217.07:40:10.37#ibcon#wrote, iclass 20, count 2 2006.217.07:40:10.37#ibcon#about to read 3, iclass 20, count 2 2006.217.07:40:10.39#ibcon#read 3, iclass 20, count 2 2006.217.07:40:10.39#ibcon#about to read 4, iclass 20, count 2 2006.217.07:40:10.39#ibcon#read 4, iclass 20, count 2 2006.217.07:40:10.39#ibcon#about to read 5, iclass 20, count 2 2006.217.07:40:10.39#ibcon#read 5, iclass 20, count 2 2006.217.07:40:10.39#ibcon#about to read 6, iclass 20, count 2 2006.217.07:40:10.39#ibcon#read 6, iclass 20, count 2 2006.217.07:40:10.39#ibcon#end of sib2, iclass 20, count 2 2006.217.07:40:10.39#ibcon#*mode == 0, iclass 20, count 2 2006.217.07:40:10.39#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.217.07:40:10.39#ibcon#[25=AT08-07\r\n] 2006.217.07:40:10.39#ibcon#*before write, iclass 20, count 2 2006.217.07:40:10.39#ibcon#enter sib2, iclass 20, count 2 2006.217.07:40:10.39#ibcon#flushed, iclass 20, count 2 2006.217.07:40:10.39#ibcon#about to write, iclass 20, count 2 2006.217.07:40:10.39#ibcon#wrote, iclass 20, count 2 2006.217.07:40:10.39#ibcon#about to read 3, iclass 20, count 2 2006.217.07:40:10.42#ibcon#read 3, iclass 20, count 2 2006.217.07:40:10.42#ibcon#about to read 4, iclass 20, count 2 2006.217.07:40:10.42#ibcon#read 4, iclass 20, count 2 2006.217.07:40:10.42#ibcon#about to read 5, iclass 20, count 2 2006.217.07:40:10.43#ibcon#read 5, iclass 20, count 2 2006.217.07:40:10.43#ibcon#about to read 6, iclass 20, count 2 2006.217.07:40:10.43#ibcon#read 6, iclass 20, count 2 2006.217.07:40:10.43#ibcon#end of sib2, iclass 20, count 2 2006.217.07:40:10.43#ibcon#*after write, iclass 20, count 2 2006.217.07:40:10.43#ibcon#*before return 0, iclass 20, count 2 2006.217.07:40:10.43#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.217.07:40:10.43#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.217.07:40:10.43#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.217.07:40:10.43#ibcon#ireg 7 cls_cnt 0 2006.217.07:40:10.43#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.217.07:40:10.54#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.217.07:40:10.54#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.217.07:40:10.54#ibcon#enter wrdev, iclass 20, count 0 2006.217.07:40:10.54#ibcon#first serial, iclass 20, count 0 2006.217.07:40:10.54#ibcon#enter sib2, iclass 20, count 0 2006.217.07:40:10.54#ibcon#flushed, iclass 20, count 0 2006.217.07:40:10.55#ibcon#about to write, iclass 20, count 0 2006.217.07:40:10.55#ibcon#wrote, iclass 20, count 0 2006.217.07:40:10.55#ibcon#about to read 3, iclass 20, count 0 2006.217.07:40:10.56#ibcon#read 3, iclass 20, count 0 2006.217.07:40:10.56#ibcon#about to read 4, iclass 20, count 0 2006.217.07:40:10.56#ibcon#read 4, iclass 20, count 0 2006.217.07:40:10.56#ibcon#about to read 5, iclass 20, count 0 2006.217.07:40:10.56#ibcon#read 5, iclass 20, count 0 2006.217.07:40:10.57#ibcon#about to read 6, iclass 20, count 0 2006.217.07:40:10.57#ibcon#read 6, iclass 20, count 0 2006.217.07:40:10.57#ibcon#end of sib2, iclass 20, count 0 2006.217.07:40:10.57#ibcon#*mode == 0, iclass 20, count 0 2006.217.07:40:10.57#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.217.07:40:10.57#ibcon#[25=USB\r\n] 2006.217.07:40:10.57#ibcon#*before write, iclass 20, count 0 2006.217.07:40:10.57#ibcon#enter sib2, iclass 20, count 0 2006.217.07:40:10.57#ibcon#flushed, iclass 20, count 0 2006.217.07:40:10.57#ibcon#about to write, iclass 20, count 0 2006.217.07:40:10.57#ibcon#wrote, iclass 20, count 0 2006.217.07:40:10.57#ibcon#about to read 3, iclass 20, count 0 2006.217.07:40:10.59#ibcon#read 3, iclass 20, count 0 2006.217.07:40:10.59#ibcon#about to read 4, iclass 20, count 0 2006.217.07:40:10.59#ibcon#read 4, iclass 20, count 0 2006.217.07:40:10.59#ibcon#about to read 5, iclass 20, count 0 2006.217.07:40:10.60#ibcon#read 5, iclass 20, count 0 2006.217.07:40:10.60#ibcon#about to read 6, iclass 20, count 0 2006.217.07:40:10.60#ibcon#read 6, iclass 20, count 0 2006.217.07:40:10.60#ibcon#end of sib2, iclass 20, count 0 2006.217.07:40:10.60#ibcon#*after write, iclass 20, count 0 2006.217.07:40:10.60#ibcon#*before return 0, iclass 20, count 0 2006.217.07:40:10.60#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.217.07:40:10.60#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.217.07:40:10.60#ibcon#about to clear, iclass 20 cls_cnt 0 2006.217.07:40:10.60#ibcon#cleared, iclass 20 cls_cnt 0 2006.217.07:40:10.60$vc4f8/vblo=1,632.99 2006.217.07:40:10.60#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.217.07:40:10.60#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.217.07:40:10.60#ibcon#ireg 17 cls_cnt 0 2006.217.07:40:10.60#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.217.07:40:10.60#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.217.07:40:10.60#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.217.07:40:10.60#ibcon#enter wrdev, iclass 22, count 0 2006.217.07:40:10.60#ibcon#first serial, iclass 22, count 0 2006.217.07:40:10.60#ibcon#enter sib2, iclass 22, count 0 2006.217.07:40:10.60#ibcon#flushed, iclass 22, count 0 2006.217.07:40:10.60#ibcon#about to write, iclass 22, count 0 2006.217.07:40:10.60#ibcon#wrote, iclass 22, count 0 2006.217.07:40:10.60#ibcon#about to read 3, iclass 22, count 0 2006.217.07:40:10.61#ibcon#read 3, iclass 22, count 0 2006.217.07:40:10.61#ibcon#about to read 4, iclass 22, count 0 2006.217.07:40:10.61#ibcon#read 4, iclass 22, count 0 2006.217.07:40:10.61#ibcon#about to read 5, iclass 22, count 0 2006.217.07:40:10.62#ibcon#read 5, iclass 22, count 0 2006.217.07:40:10.62#ibcon#about to read 6, iclass 22, count 0 2006.217.07:40:10.62#ibcon#read 6, iclass 22, count 0 2006.217.07:40:10.62#ibcon#end of sib2, iclass 22, count 0 2006.217.07:40:10.62#ibcon#*mode == 0, iclass 22, count 0 2006.217.07:40:10.62#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.217.07:40:10.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.217.07:40:10.62#ibcon#*before write, iclass 22, count 0 2006.217.07:40:10.62#ibcon#enter sib2, iclass 22, count 0 2006.217.07:40:10.62#ibcon#flushed, iclass 22, count 0 2006.217.07:40:10.62#ibcon#about to write, iclass 22, count 0 2006.217.07:40:10.62#ibcon#wrote, iclass 22, count 0 2006.217.07:40:10.62#ibcon#about to read 3, iclass 22, count 0 2006.217.07:40:10.65#ibcon#read 3, iclass 22, count 0 2006.217.07:40:10.65#ibcon#about to read 4, iclass 22, count 0 2006.217.07:40:10.65#ibcon#read 4, iclass 22, count 0 2006.217.07:40:10.65#ibcon#about to read 5, iclass 22, count 0 2006.217.07:40:10.66#ibcon#read 5, iclass 22, count 0 2006.217.07:40:10.66#ibcon#about to read 6, iclass 22, count 0 2006.217.07:40:10.66#ibcon#read 6, iclass 22, count 0 2006.217.07:40:10.66#ibcon#end of sib2, iclass 22, count 0 2006.217.07:40:10.66#ibcon#*after write, iclass 22, count 0 2006.217.07:40:10.66#ibcon#*before return 0, iclass 22, count 0 2006.217.07:40:10.66#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.217.07:40:10.66#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.217.07:40:10.66#ibcon#about to clear, iclass 22 cls_cnt 0 2006.217.07:40:10.66#ibcon#cleared, iclass 22 cls_cnt 0 2006.217.07:40:10.66$vc4f8/vb=1,4 2006.217.07:40:10.66#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.217.07:40:10.66#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.217.07:40:10.66#ibcon#ireg 11 cls_cnt 2 2006.217.07:40:10.66#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.217.07:40:10.66#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.217.07:40:10.66#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.217.07:40:10.66#ibcon#enter wrdev, iclass 24, count 2 2006.217.07:40:10.66#ibcon#first serial, iclass 24, count 2 2006.217.07:40:10.66#ibcon#enter sib2, iclass 24, count 2 2006.217.07:40:10.66#ibcon#flushed, iclass 24, count 2 2006.217.07:40:10.66#ibcon#about to write, iclass 24, count 2 2006.217.07:40:10.66#ibcon#wrote, iclass 24, count 2 2006.217.07:40:10.66#ibcon#about to read 3, iclass 24, count 2 2006.217.07:40:10.67#ibcon#read 3, iclass 24, count 2 2006.217.07:40:10.67#ibcon#about to read 4, iclass 24, count 2 2006.217.07:40:10.67#ibcon#read 4, iclass 24, count 2 2006.217.07:40:10.67#ibcon#about to read 5, iclass 24, count 2 2006.217.07:40:10.68#ibcon#read 5, iclass 24, count 2 2006.217.07:40:10.68#ibcon#about to read 6, iclass 24, count 2 2006.217.07:40:10.68#ibcon#read 6, iclass 24, count 2 2006.217.07:40:10.68#ibcon#end of sib2, iclass 24, count 2 2006.217.07:40:10.68#ibcon#*mode == 0, iclass 24, count 2 2006.217.07:40:10.68#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.217.07:40:10.68#ibcon#[27=AT01-04\r\n] 2006.217.07:40:10.68#ibcon#*before write, iclass 24, count 2 2006.217.07:40:10.68#ibcon#enter sib2, iclass 24, count 2 2006.217.07:40:10.68#ibcon#flushed, iclass 24, count 2 2006.217.07:40:10.68#ibcon#about to write, iclass 24, count 2 2006.217.07:40:10.68#ibcon#wrote, iclass 24, count 2 2006.217.07:40:10.68#ibcon#about to read 3, iclass 24, count 2 2006.217.07:40:10.70#ibcon#read 3, iclass 24, count 2 2006.217.07:40:10.70#ibcon#about to read 4, iclass 24, count 2 2006.217.07:40:10.70#ibcon#read 4, iclass 24, count 2 2006.217.07:40:10.70#ibcon#about to read 5, iclass 24, count 2 2006.217.07:40:10.71#ibcon#read 5, iclass 24, count 2 2006.217.07:40:10.71#ibcon#about to read 6, iclass 24, count 2 2006.217.07:40:10.71#ibcon#read 6, iclass 24, count 2 2006.217.07:40:10.71#ibcon#end of sib2, iclass 24, count 2 2006.217.07:40:10.71#ibcon#*after write, iclass 24, count 2 2006.217.07:40:10.71#ibcon#*before return 0, iclass 24, count 2 2006.217.07:40:10.71#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.217.07:40:10.71#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.217.07:40:10.71#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.217.07:40:10.71#ibcon#ireg 7 cls_cnt 0 2006.217.07:40:10.71#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.217.07:40:10.82#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.217.07:40:10.82#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.217.07:40:10.82#ibcon#enter wrdev, iclass 24, count 0 2006.217.07:40:10.82#ibcon#first serial, iclass 24, count 0 2006.217.07:40:10.82#ibcon#enter sib2, iclass 24, count 0 2006.217.07:40:10.82#ibcon#flushed, iclass 24, count 0 2006.217.07:40:10.83#ibcon#about to write, iclass 24, count 0 2006.217.07:40:10.83#ibcon#wrote, iclass 24, count 0 2006.217.07:40:10.83#ibcon#about to read 3, iclass 24, count 0 2006.217.07:40:10.84#ibcon#read 3, iclass 24, count 0 2006.217.07:40:10.84#ibcon#about to read 4, iclass 24, count 0 2006.217.07:40:10.84#ibcon#read 4, iclass 24, count 0 2006.217.07:40:10.84#ibcon#about to read 5, iclass 24, count 0 2006.217.07:40:10.84#ibcon#read 5, iclass 24, count 0 2006.217.07:40:10.85#ibcon#about to read 6, iclass 24, count 0 2006.217.07:40:10.85#ibcon#read 6, iclass 24, count 0 2006.217.07:40:10.85#ibcon#end of sib2, iclass 24, count 0 2006.217.07:40:10.85#ibcon#*mode == 0, iclass 24, count 0 2006.217.07:40:10.85#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.217.07:40:10.85#ibcon#[27=USB\r\n] 2006.217.07:40:10.85#ibcon#*before write, iclass 24, count 0 2006.217.07:40:10.85#ibcon#enter sib2, iclass 24, count 0 2006.217.07:40:10.85#ibcon#flushed, iclass 24, count 0 2006.217.07:40:10.85#ibcon#about to write, iclass 24, count 0 2006.217.07:40:10.85#ibcon#wrote, iclass 24, count 0 2006.217.07:40:10.85#ibcon#about to read 3, iclass 24, count 0 2006.217.07:40:10.87#ibcon#read 3, iclass 24, count 0 2006.217.07:40:10.87#ibcon#about to read 4, iclass 24, count 0 2006.217.07:40:10.87#ibcon#read 4, iclass 24, count 0 2006.217.07:40:10.87#ibcon#about to read 5, iclass 24, count 0 2006.217.07:40:10.88#ibcon#read 5, iclass 24, count 0 2006.217.07:40:10.88#ibcon#about to read 6, iclass 24, count 0 2006.217.07:40:10.88#ibcon#read 6, iclass 24, count 0 2006.217.07:40:10.88#ibcon#end of sib2, iclass 24, count 0 2006.217.07:40:10.88#ibcon#*after write, iclass 24, count 0 2006.217.07:40:10.88#ibcon#*before return 0, iclass 24, count 0 2006.217.07:40:10.88#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.217.07:40:10.88#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.217.07:40:10.88#ibcon#about to clear, iclass 24 cls_cnt 0 2006.217.07:40:10.88#ibcon#cleared, iclass 24 cls_cnt 0 2006.217.07:40:10.88$vc4f8/vblo=2,640.99 2006.217.07:40:10.88#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.217.07:40:10.88#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.217.07:40:10.88#ibcon#ireg 17 cls_cnt 0 2006.217.07:40:10.88#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.217.07:40:10.88#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.217.07:40:10.88#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.217.07:40:10.88#ibcon#enter wrdev, iclass 26, count 0 2006.217.07:40:10.88#ibcon#first serial, iclass 26, count 0 2006.217.07:40:10.88#ibcon#enter sib2, iclass 26, count 0 2006.217.07:40:10.88#ibcon#flushed, iclass 26, count 0 2006.217.07:40:10.88#ibcon#about to write, iclass 26, count 0 2006.217.07:40:10.88#ibcon#wrote, iclass 26, count 0 2006.217.07:40:10.88#ibcon#about to read 3, iclass 26, count 0 2006.217.07:40:10.89#ibcon#read 3, iclass 26, count 0 2006.217.07:40:10.89#ibcon#about to read 4, iclass 26, count 0 2006.217.07:40:10.89#ibcon#read 4, iclass 26, count 0 2006.217.07:40:10.89#ibcon#about to read 5, iclass 26, count 0 2006.217.07:40:10.90#ibcon#read 5, iclass 26, count 0 2006.217.07:40:10.90#ibcon#about to read 6, iclass 26, count 0 2006.217.07:40:10.90#ibcon#read 6, iclass 26, count 0 2006.217.07:40:10.90#ibcon#end of sib2, iclass 26, count 0 2006.217.07:40:10.90#ibcon#*mode == 0, iclass 26, count 0 2006.217.07:40:10.90#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.217.07:40:10.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.217.07:40:10.90#ibcon#*before write, iclass 26, count 0 2006.217.07:40:10.90#ibcon#enter sib2, iclass 26, count 0 2006.217.07:40:10.90#ibcon#flushed, iclass 26, count 0 2006.217.07:40:10.90#ibcon#about to write, iclass 26, count 0 2006.217.07:40:10.90#ibcon#wrote, iclass 26, count 0 2006.217.07:40:10.90#ibcon#about to read 3, iclass 26, count 0 2006.217.07:40:10.93#ibcon#read 3, iclass 26, count 0 2006.217.07:40:10.93#ibcon#about to read 4, iclass 26, count 0 2006.217.07:40:10.93#ibcon#read 4, iclass 26, count 0 2006.217.07:40:10.93#ibcon#about to read 5, iclass 26, count 0 2006.217.07:40:10.94#ibcon#read 5, iclass 26, count 0 2006.217.07:40:10.94#ibcon#about to read 6, iclass 26, count 0 2006.217.07:40:10.94#ibcon#read 6, iclass 26, count 0 2006.217.07:40:10.94#ibcon#end of sib2, iclass 26, count 0 2006.217.07:40:10.94#ibcon#*after write, iclass 26, count 0 2006.217.07:40:10.94#ibcon#*before return 0, iclass 26, count 0 2006.217.07:40:10.94#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.217.07:40:10.94#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.217.07:40:10.94#ibcon#about to clear, iclass 26 cls_cnt 0 2006.217.07:40:10.94#ibcon#cleared, iclass 26 cls_cnt 0 2006.217.07:40:10.94$vc4f8/vb=2,4 2006.217.07:40:10.94#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.217.07:40:10.94#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.217.07:40:10.94#ibcon#ireg 11 cls_cnt 2 2006.217.07:40:10.94#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.217.07:40:10.99#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.217.07:40:10.99#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.217.07:40:10.99#ibcon#enter wrdev, iclass 28, count 2 2006.217.07:40:10.99#ibcon#first serial, iclass 28, count 2 2006.217.07:40:10.99#ibcon#enter sib2, iclass 28, count 2 2006.217.07:40:10.99#ibcon#flushed, iclass 28, count 2 2006.217.07:40:11.00#ibcon#about to write, iclass 28, count 2 2006.217.07:40:11.00#ibcon#wrote, iclass 28, count 2 2006.217.07:40:11.00#ibcon#about to read 3, iclass 28, count 2 2006.217.07:40:11.01#ibcon#read 3, iclass 28, count 2 2006.217.07:40:11.01#ibcon#about to read 4, iclass 28, count 2 2006.217.07:40:11.01#ibcon#read 4, iclass 28, count 2 2006.217.07:40:11.01#ibcon#about to read 5, iclass 28, count 2 2006.217.07:40:11.01#ibcon#read 5, iclass 28, count 2 2006.217.07:40:11.01#ibcon#about to read 6, iclass 28, count 2 2006.217.07:40:11.02#ibcon#read 6, iclass 28, count 2 2006.217.07:40:11.02#ibcon#end of sib2, iclass 28, count 2 2006.217.07:40:11.02#ibcon#*mode == 0, iclass 28, count 2 2006.217.07:40:11.02#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.217.07:40:11.02#ibcon#[27=AT02-04\r\n] 2006.217.07:40:11.02#ibcon#*before write, iclass 28, count 2 2006.217.07:40:11.02#ibcon#enter sib2, iclass 28, count 2 2006.217.07:40:11.02#ibcon#flushed, iclass 28, count 2 2006.217.07:40:11.02#ibcon#about to write, iclass 28, count 2 2006.217.07:40:11.02#ibcon#wrote, iclass 28, count 2 2006.217.07:40:11.02#ibcon#about to read 3, iclass 28, count 2 2006.217.07:40:11.04#ibcon#read 3, iclass 28, count 2 2006.217.07:40:11.04#ibcon#about to read 4, iclass 28, count 2 2006.217.07:40:11.04#ibcon#read 4, iclass 28, count 2 2006.217.07:40:11.04#ibcon#about to read 5, iclass 28, count 2 2006.217.07:40:11.05#ibcon#read 5, iclass 28, count 2 2006.217.07:40:11.05#ibcon#about to read 6, iclass 28, count 2 2006.217.07:40:11.05#ibcon#read 6, iclass 28, count 2 2006.217.07:40:11.05#ibcon#end of sib2, iclass 28, count 2 2006.217.07:40:11.05#ibcon#*after write, iclass 28, count 2 2006.217.07:40:11.05#ibcon#*before return 0, iclass 28, count 2 2006.217.07:40:11.05#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.217.07:40:11.05#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.217.07:40:11.05#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.217.07:40:11.05#ibcon#ireg 7 cls_cnt 0 2006.217.07:40:11.05#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.217.07:40:11.16#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.217.07:40:11.16#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.217.07:40:11.16#ibcon#enter wrdev, iclass 28, count 0 2006.217.07:40:11.16#ibcon#first serial, iclass 28, count 0 2006.217.07:40:11.16#ibcon#enter sib2, iclass 28, count 0 2006.217.07:40:11.16#ibcon#flushed, iclass 28, count 0 2006.217.07:40:11.16#ibcon#about to write, iclass 28, count 0 2006.217.07:40:11.17#ibcon#wrote, iclass 28, count 0 2006.217.07:40:11.17#ibcon#about to read 3, iclass 28, count 0 2006.217.07:40:11.18#ibcon#read 3, iclass 28, count 0 2006.217.07:40:11.18#ibcon#about to read 4, iclass 28, count 0 2006.217.07:40:11.18#ibcon#read 4, iclass 28, count 0 2006.217.07:40:11.18#ibcon#about to read 5, iclass 28, count 0 2006.217.07:40:11.18#ibcon#read 5, iclass 28, count 0 2006.217.07:40:11.19#ibcon#about to read 6, iclass 28, count 0 2006.217.07:40:11.19#ibcon#read 6, iclass 28, count 0 2006.217.07:40:11.19#ibcon#end of sib2, iclass 28, count 0 2006.217.07:40:11.19#ibcon#*mode == 0, iclass 28, count 0 2006.217.07:40:11.19#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.217.07:40:11.19#ibcon#[27=USB\r\n] 2006.217.07:40:11.19#ibcon#*before write, iclass 28, count 0 2006.217.07:40:11.19#ibcon#enter sib2, iclass 28, count 0 2006.217.07:40:11.19#ibcon#flushed, iclass 28, count 0 2006.217.07:40:11.19#ibcon#about to write, iclass 28, count 0 2006.217.07:40:11.19#ibcon#wrote, iclass 28, count 0 2006.217.07:40:11.19#ibcon#about to read 3, iclass 28, count 0 2006.217.07:40:11.21#ibcon#read 3, iclass 28, count 0 2006.217.07:40:11.21#ibcon#about to read 4, iclass 28, count 0 2006.217.07:40:11.21#ibcon#read 4, iclass 28, count 0 2006.217.07:40:11.21#ibcon#about to read 5, iclass 28, count 0 2006.217.07:40:11.21#ibcon#read 5, iclass 28, count 0 2006.217.07:40:11.22#ibcon#about to read 6, iclass 28, count 0 2006.217.07:40:11.22#ibcon#read 6, iclass 28, count 0 2006.217.07:40:11.22#ibcon#end of sib2, iclass 28, count 0 2006.217.07:40:11.22#ibcon#*after write, iclass 28, count 0 2006.217.07:40:11.22#ibcon#*before return 0, iclass 28, count 0 2006.217.07:40:11.22#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.217.07:40:11.22#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.217.07:40:11.22#ibcon#about to clear, iclass 28 cls_cnt 0 2006.217.07:40:11.22#ibcon#cleared, iclass 28 cls_cnt 0 2006.217.07:40:11.22$vc4f8/vblo=3,656.99 2006.217.07:40:11.22#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.217.07:40:11.22#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.217.07:40:11.22#ibcon#ireg 17 cls_cnt 0 2006.217.07:40:11.22#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.217.07:40:11.22#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.217.07:40:11.22#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.217.07:40:11.22#ibcon#enter wrdev, iclass 30, count 0 2006.217.07:40:11.22#ibcon#first serial, iclass 30, count 0 2006.217.07:40:11.22#ibcon#enter sib2, iclass 30, count 0 2006.217.07:40:11.22#ibcon#flushed, iclass 30, count 0 2006.217.07:40:11.22#ibcon#about to write, iclass 30, count 0 2006.217.07:40:11.22#ibcon#wrote, iclass 30, count 0 2006.217.07:40:11.22#ibcon#about to read 3, iclass 30, count 0 2006.217.07:40:11.23#ibcon#read 3, iclass 30, count 0 2006.217.07:40:11.23#ibcon#about to read 4, iclass 30, count 0 2006.217.07:40:11.23#ibcon#read 4, iclass 30, count 0 2006.217.07:40:11.23#ibcon#about to read 5, iclass 30, count 0 2006.217.07:40:11.24#ibcon#read 5, iclass 30, count 0 2006.217.07:40:11.24#ibcon#about to read 6, iclass 30, count 0 2006.217.07:40:11.24#ibcon#read 6, iclass 30, count 0 2006.217.07:40:11.24#ibcon#end of sib2, iclass 30, count 0 2006.217.07:40:11.24#ibcon#*mode == 0, iclass 30, count 0 2006.217.07:40:11.24#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.217.07:40:11.24#ibcon#[28=FRQ=03,656.99\r\n] 2006.217.07:40:11.24#ibcon#*before write, iclass 30, count 0 2006.217.07:40:11.24#ibcon#enter sib2, iclass 30, count 0 2006.217.07:40:11.24#ibcon#flushed, iclass 30, count 0 2006.217.07:40:11.24#ibcon#about to write, iclass 30, count 0 2006.217.07:40:11.24#ibcon#wrote, iclass 30, count 0 2006.217.07:40:11.24#ibcon#about to read 3, iclass 30, count 0 2006.217.07:40:11.27#ibcon#read 3, iclass 30, count 0 2006.217.07:40:11.27#ibcon#about to read 4, iclass 30, count 0 2006.217.07:40:11.27#ibcon#read 4, iclass 30, count 0 2006.217.07:40:11.28#ibcon#about to read 5, iclass 30, count 0 2006.217.07:40:11.28#ibcon#read 5, iclass 30, count 0 2006.217.07:40:11.28#ibcon#about to read 6, iclass 30, count 0 2006.217.07:40:11.28#ibcon#read 6, iclass 30, count 0 2006.217.07:40:11.28#ibcon#end of sib2, iclass 30, count 0 2006.217.07:40:11.28#ibcon#*after write, iclass 30, count 0 2006.217.07:40:11.28#ibcon#*before return 0, iclass 30, count 0 2006.217.07:40:11.28#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.217.07:40:11.28#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.217.07:40:11.28#ibcon#about to clear, iclass 30 cls_cnt 0 2006.217.07:40:11.28#ibcon#cleared, iclass 30 cls_cnt 0 2006.217.07:40:11.28$vc4f8/vb=3,4 2006.217.07:40:11.28#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.217.07:40:11.28#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.217.07:40:11.28#ibcon#ireg 11 cls_cnt 2 2006.217.07:40:11.28#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.217.07:40:11.33#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.217.07:40:11.33#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.217.07:40:11.33#ibcon#enter wrdev, iclass 32, count 2 2006.217.07:40:11.34#ibcon#first serial, iclass 32, count 2 2006.217.07:40:11.34#ibcon#enter sib2, iclass 32, count 2 2006.217.07:40:11.34#ibcon#flushed, iclass 32, count 2 2006.217.07:40:11.34#ibcon#about to write, iclass 32, count 2 2006.217.07:40:11.34#ibcon#wrote, iclass 32, count 2 2006.217.07:40:11.34#ibcon#about to read 3, iclass 32, count 2 2006.217.07:40:11.35#ibcon#read 3, iclass 32, count 2 2006.217.07:40:11.35#ibcon#about to read 4, iclass 32, count 2 2006.217.07:40:11.35#ibcon#read 4, iclass 32, count 2 2006.217.07:40:11.35#ibcon#about to read 5, iclass 32, count 2 2006.217.07:40:11.35#ibcon#read 5, iclass 32, count 2 2006.217.07:40:11.36#ibcon#about to read 6, iclass 32, count 2 2006.217.07:40:11.36#ibcon#read 6, iclass 32, count 2 2006.217.07:40:11.36#ibcon#end of sib2, iclass 32, count 2 2006.217.07:40:11.36#ibcon#*mode == 0, iclass 32, count 2 2006.217.07:40:11.36#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.217.07:40:11.36#ibcon#[27=AT03-04\r\n] 2006.217.07:40:11.36#ibcon#*before write, iclass 32, count 2 2006.217.07:40:11.36#ibcon#enter sib2, iclass 32, count 2 2006.217.07:40:11.36#ibcon#flushed, iclass 32, count 2 2006.217.07:40:11.36#ibcon#about to write, iclass 32, count 2 2006.217.07:40:11.36#ibcon#wrote, iclass 32, count 2 2006.217.07:40:11.36#ibcon#about to read 3, iclass 32, count 2 2006.217.07:40:11.38#ibcon#read 3, iclass 32, count 2 2006.217.07:40:11.38#ibcon#about to read 4, iclass 32, count 2 2006.217.07:40:11.39#ibcon#read 4, iclass 32, count 2 2006.217.07:40:11.39#ibcon#about to read 5, iclass 32, count 2 2006.217.07:40:11.39#ibcon#read 5, iclass 32, count 2 2006.217.07:40:11.39#ibcon#about to read 6, iclass 32, count 2 2006.217.07:40:11.39#ibcon#read 6, iclass 32, count 2 2006.217.07:40:11.39#ibcon#end of sib2, iclass 32, count 2 2006.217.07:40:11.39#ibcon#*after write, iclass 32, count 2 2006.217.07:40:11.39#ibcon#*before return 0, iclass 32, count 2 2006.217.07:40:11.39#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.217.07:40:11.39#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.217.07:40:11.39#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.217.07:40:11.39#ibcon#ireg 7 cls_cnt 0 2006.217.07:40:11.39#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.217.07:40:11.50#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.217.07:40:11.50#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.217.07:40:11.50#ibcon#enter wrdev, iclass 32, count 0 2006.217.07:40:11.50#ibcon#first serial, iclass 32, count 0 2006.217.07:40:11.51#ibcon#enter sib2, iclass 32, count 0 2006.217.07:40:11.51#ibcon#flushed, iclass 32, count 0 2006.217.07:40:11.51#ibcon#about to write, iclass 32, count 0 2006.217.07:40:11.51#ibcon#wrote, iclass 32, count 0 2006.217.07:40:11.51#ibcon#about to read 3, iclass 32, count 0 2006.217.07:40:11.51#abcon#<5=/05 4.1 8.9 31.29 601008.6\r\n> 2006.217.07:40:11.52#ibcon#read 3, iclass 32, count 0 2006.217.07:40:11.52#ibcon#about to read 4, iclass 32, count 0 2006.217.07:40:11.52#ibcon#read 4, iclass 32, count 0 2006.217.07:40:11.52#ibcon#about to read 5, iclass 32, count 0 2006.217.07:40:11.53#ibcon#read 5, iclass 32, count 0 2006.217.07:40:11.53#ibcon#about to read 6, iclass 32, count 0 2006.217.07:40:11.53#ibcon#read 6, iclass 32, count 0 2006.217.07:40:11.53#ibcon#end of sib2, iclass 32, count 0 2006.217.07:40:11.53#ibcon#*mode == 0, iclass 32, count 0 2006.217.07:40:11.53#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.217.07:40:11.53#ibcon#[27=USB\r\n] 2006.217.07:40:11.53#ibcon#*before write, iclass 32, count 0 2006.217.07:40:11.53#ibcon#enter sib2, iclass 32, count 0 2006.217.07:40:11.53#ibcon#flushed, iclass 32, count 0 2006.217.07:40:11.53#ibcon#about to write, iclass 32, count 0 2006.217.07:40:11.53#ibcon#wrote, iclass 32, count 0 2006.217.07:40:11.53#ibcon#about to read 3, iclass 32, count 0 2006.217.07:40:11.53#abcon#{5=INTERFACE CLEAR} 2006.217.07:40:11.55#ibcon#read 3, iclass 32, count 0 2006.217.07:40:11.55#ibcon#about to read 4, iclass 32, count 0 2006.217.07:40:11.55#ibcon#read 4, iclass 32, count 0 2006.217.07:40:11.55#ibcon#about to read 5, iclass 32, count 0 2006.217.07:40:11.55#ibcon#read 5, iclass 32, count 0 2006.217.07:40:11.56#ibcon#about to read 6, iclass 32, count 0 2006.217.07:40:11.56#ibcon#read 6, iclass 32, count 0 2006.217.07:40:11.56#ibcon#end of sib2, iclass 32, count 0 2006.217.07:40:11.56#ibcon#*after write, iclass 32, count 0 2006.217.07:40:11.56#ibcon#*before return 0, iclass 32, count 0 2006.217.07:40:11.56#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.217.07:40:11.56#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.217.07:40:11.56#ibcon#about to clear, iclass 32 cls_cnt 0 2006.217.07:40:11.56#ibcon#cleared, iclass 32 cls_cnt 0 2006.217.07:40:11.56$vc4f8/vblo=4,712.99 2006.217.07:40:11.56#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.217.07:40:11.56#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.217.07:40:11.56#ibcon#ireg 17 cls_cnt 0 2006.217.07:40:11.56#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.217.07:40:11.56#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.217.07:40:11.56#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.217.07:40:11.56#ibcon#enter wrdev, iclass 37, count 0 2006.217.07:40:11.56#ibcon#first serial, iclass 37, count 0 2006.217.07:40:11.56#ibcon#enter sib2, iclass 37, count 0 2006.217.07:40:11.56#ibcon#flushed, iclass 37, count 0 2006.217.07:40:11.56#ibcon#about to write, iclass 37, count 0 2006.217.07:40:11.56#ibcon#wrote, iclass 37, count 0 2006.217.07:40:11.56#ibcon#about to read 3, iclass 37, count 0 2006.217.07:40:11.57#ibcon#read 3, iclass 37, count 0 2006.217.07:40:11.57#ibcon#about to read 4, iclass 37, count 0 2006.217.07:40:11.57#ibcon#read 4, iclass 37, count 0 2006.217.07:40:11.57#ibcon#about to read 5, iclass 37, count 0 2006.217.07:40:11.58#ibcon#read 5, iclass 37, count 0 2006.217.07:40:11.58#ibcon#about to read 6, iclass 37, count 0 2006.217.07:40:11.58#ibcon#read 6, iclass 37, count 0 2006.217.07:40:11.58#ibcon#end of sib2, iclass 37, count 0 2006.217.07:40:11.58#ibcon#*mode == 0, iclass 37, count 0 2006.217.07:40:11.58#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.217.07:40:11.58#ibcon#[28=FRQ=04,712.99\r\n] 2006.217.07:40:11.58#ibcon#*before write, iclass 37, count 0 2006.217.07:40:11.58#ibcon#enter sib2, iclass 37, count 0 2006.217.07:40:11.58#ibcon#flushed, iclass 37, count 0 2006.217.07:40:11.58#ibcon#about to write, iclass 37, count 0 2006.217.07:40:11.58#ibcon#wrote, iclass 37, count 0 2006.217.07:40:11.58#ibcon#about to read 3, iclass 37, count 0 2006.217.07:40:11.59#abcon#[5=S1D000X0/0*\r\n] 2006.217.07:40:11.61#ibcon#read 3, iclass 37, count 0 2006.217.07:40:11.61#ibcon#about to read 4, iclass 37, count 0 2006.217.07:40:11.61#ibcon#read 4, iclass 37, count 0 2006.217.07:40:11.61#ibcon#about to read 5, iclass 37, count 0 2006.217.07:40:11.62#ibcon#read 5, iclass 37, count 0 2006.217.07:40:11.62#ibcon#about to read 6, iclass 37, count 0 2006.217.07:40:11.62#ibcon#read 6, iclass 37, count 0 2006.217.07:40:11.62#ibcon#end of sib2, iclass 37, count 0 2006.217.07:40:11.62#ibcon#*after write, iclass 37, count 0 2006.217.07:40:11.62#ibcon#*before return 0, iclass 37, count 0 2006.217.07:40:11.62#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.217.07:40:11.62#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.217.07:40:11.62#ibcon#about to clear, iclass 37 cls_cnt 0 2006.217.07:40:11.62#ibcon#cleared, iclass 37 cls_cnt 0 2006.217.07:40:11.62$vc4f8/vb=4,4 2006.217.07:40:11.62#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.217.07:40:11.62#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.217.07:40:11.62#ibcon#ireg 11 cls_cnt 2 2006.217.07:40:11.62#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.217.07:40:11.67#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.217.07:40:11.67#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.217.07:40:11.67#ibcon#enter wrdev, iclass 40, count 2 2006.217.07:40:11.67#ibcon#first serial, iclass 40, count 2 2006.217.07:40:11.67#ibcon#enter sib2, iclass 40, count 2 2006.217.07:40:11.67#ibcon#flushed, iclass 40, count 2 2006.217.07:40:11.68#ibcon#about to write, iclass 40, count 2 2006.217.07:40:11.68#ibcon#wrote, iclass 40, count 2 2006.217.07:40:11.68#ibcon#about to read 3, iclass 40, count 2 2006.217.07:40:11.69#ibcon#read 3, iclass 40, count 2 2006.217.07:40:11.69#ibcon#about to read 4, iclass 40, count 2 2006.217.07:40:11.69#ibcon#read 4, iclass 40, count 2 2006.217.07:40:11.69#ibcon#about to read 5, iclass 40, count 2 2006.217.07:40:11.69#ibcon#read 5, iclass 40, count 2 2006.217.07:40:11.70#ibcon#about to read 6, iclass 40, count 2 2006.217.07:40:11.70#ibcon#read 6, iclass 40, count 2 2006.217.07:40:11.70#ibcon#end of sib2, iclass 40, count 2 2006.217.07:40:11.70#ibcon#*mode == 0, iclass 40, count 2 2006.217.07:40:11.70#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.217.07:40:11.70#ibcon#[27=AT04-04\r\n] 2006.217.07:40:11.70#ibcon#*before write, iclass 40, count 2 2006.217.07:40:11.70#ibcon#enter sib2, iclass 40, count 2 2006.217.07:40:11.70#ibcon#flushed, iclass 40, count 2 2006.217.07:40:11.70#ibcon#about to write, iclass 40, count 2 2006.217.07:40:11.70#ibcon#wrote, iclass 40, count 2 2006.217.07:40:11.70#ibcon#about to read 3, iclass 40, count 2 2006.217.07:40:11.72#ibcon#read 3, iclass 40, count 2 2006.217.07:40:11.72#ibcon#about to read 4, iclass 40, count 2 2006.217.07:40:11.72#ibcon#read 4, iclass 40, count 2 2006.217.07:40:11.72#ibcon#about to read 5, iclass 40, count 2 2006.217.07:40:11.72#ibcon#read 5, iclass 40, count 2 2006.217.07:40:11.73#ibcon#about to read 6, iclass 40, count 2 2006.217.07:40:11.73#ibcon#read 6, iclass 40, count 2 2006.217.07:40:11.73#ibcon#end of sib2, iclass 40, count 2 2006.217.07:40:11.73#ibcon#*after write, iclass 40, count 2 2006.217.07:40:11.73#ibcon#*before return 0, iclass 40, count 2 2006.217.07:40:11.73#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.217.07:40:11.73#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.217.07:40:11.73#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.217.07:40:11.73#ibcon#ireg 7 cls_cnt 0 2006.217.07:40:11.73#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.217.07:40:11.84#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.217.07:40:11.84#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.217.07:40:11.84#ibcon#enter wrdev, iclass 40, count 0 2006.217.07:40:11.84#ibcon#first serial, iclass 40, count 0 2006.217.07:40:11.84#ibcon#enter sib2, iclass 40, count 0 2006.217.07:40:11.84#ibcon#flushed, iclass 40, count 0 2006.217.07:40:11.84#ibcon#about to write, iclass 40, count 0 2006.217.07:40:11.85#ibcon#wrote, iclass 40, count 0 2006.217.07:40:11.85#ibcon#about to read 3, iclass 40, count 0 2006.217.07:40:11.86#ibcon#read 3, iclass 40, count 0 2006.217.07:40:11.86#ibcon#about to read 4, iclass 40, count 0 2006.217.07:40:11.86#ibcon#read 4, iclass 40, count 0 2006.217.07:40:11.86#ibcon#about to read 5, iclass 40, count 0 2006.217.07:40:11.86#ibcon#read 5, iclass 40, count 0 2006.217.07:40:11.87#ibcon#about to read 6, iclass 40, count 0 2006.217.07:40:11.87#ibcon#read 6, iclass 40, count 0 2006.217.07:40:11.87#ibcon#end of sib2, iclass 40, count 0 2006.217.07:40:11.87#ibcon#*mode == 0, iclass 40, count 0 2006.217.07:40:11.87#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.217.07:40:11.87#ibcon#[27=USB\r\n] 2006.217.07:40:11.87#ibcon#*before write, iclass 40, count 0 2006.217.07:40:11.87#ibcon#enter sib2, iclass 40, count 0 2006.217.07:40:11.87#ibcon#flushed, iclass 40, count 0 2006.217.07:40:11.87#ibcon#about to write, iclass 40, count 0 2006.217.07:40:11.87#ibcon#wrote, iclass 40, count 0 2006.217.07:40:11.87#ibcon#about to read 3, iclass 40, count 0 2006.217.07:40:11.89#ibcon#read 3, iclass 40, count 0 2006.217.07:40:11.89#ibcon#about to read 4, iclass 40, count 0 2006.217.07:40:11.89#ibcon#read 4, iclass 40, count 0 2006.217.07:40:11.89#ibcon#about to read 5, iclass 40, count 0 2006.217.07:40:11.89#ibcon#read 5, iclass 40, count 0 2006.217.07:40:11.90#ibcon#about to read 6, iclass 40, count 0 2006.217.07:40:11.90#ibcon#read 6, iclass 40, count 0 2006.217.07:40:11.90#ibcon#end of sib2, iclass 40, count 0 2006.217.07:40:11.90#ibcon#*after write, iclass 40, count 0 2006.217.07:40:11.90#ibcon#*before return 0, iclass 40, count 0 2006.217.07:40:11.90#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.217.07:40:11.90#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.217.07:40:11.90#ibcon#about to clear, iclass 40 cls_cnt 0 2006.217.07:40:11.90#ibcon#cleared, iclass 40 cls_cnt 0 2006.217.07:40:11.90$vc4f8/vblo=5,744.99 2006.217.07:40:11.90#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.217.07:40:11.90#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.217.07:40:11.90#ibcon#ireg 17 cls_cnt 0 2006.217.07:40:11.90#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.217.07:40:11.90#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.217.07:40:11.90#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.217.07:40:11.90#ibcon#enter wrdev, iclass 4, count 0 2006.217.07:40:11.90#ibcon#first serial, iclass 4, count 0 2006.217.07:40:11.90#ibcon#enter sib2, iclass 4, count 0 2006.217.07:40:11.90#ibcon#flushed, iclass 4, count 0 2006.217.07:40:11.90#ibcon#about to write, iclass 4, count 0 2006.217.07:40:11.90#ibcon#wrote, iclass 4, count 0 2006.217.07:40:11.90#ibcon#about to read 3, iclass 4, count 0 2006.217.07:40:11.91#ibcon#read 3, iclass 4, count 0 2006.217.07:40:11.91#ibcon#about to read 4, iclass 4, count 0 2006.217.07:40:11.91#ibcon#read 4, iclass 4, count 0 2006.217.07:40:11.91#ibcon#about to read 5, iclass 4, count 0 2006.217.07:40:11.91#ibcon#read 5, iclass 4, count 0 2006.217.07:40:11.92#ibcon#about to read 6, iclass 4, count 0 2006.217.07:40:11.92#ibcon#read 6, iclass 4, count 0 2006.217.07:40:11.92#ibcon#end of sib2, iclass 4, count 0 2006.217.07:40:11.92#ibcon#*mode == 0, iclass 4, count 0 2006.217.07:40:11.92#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.217.07:40:11.92#ibcon#[28=FRQ=05,744.99\r\n] 2006.217.07:40:11.92#ibcon#*before write, iclass 4, count 0 2006.217.07:40:11.92#ibcon#enter sib2, iclass 4, count 0 2006.217.07:40:11.92#ibcon#flushed, iclass 4, count 0 2006.217.07:40:11.92#ibcon#about to write, iclass 4, count 0 2006.217.07:40:11.92#ibcon#wrote, iclass 4, count 0 2006.217.07:40:11.92#ibcon#about to read 3, iclass 4, count 0 2006.217.07:40:11.95#ibcon#read 3, iclass 4, count 0 2006.217.07:40:11.95#ibcon#about to read 4, iclass 4, count 0 2006.217.07:40:11.95#ibcon#read 4, iclass 4, count 0 2006.217.07:40:11.95#ibcon#about to read 5, iclass 4, count 0 2006.217.07:40:11.96#ibcon#read 5, iclass 4, count 0 2006.217.07:40:11.96#ibcon#about to read 6, iclass 4, count 0 2006.217.07:40:11.96#ibcon#read 6, iclass 4, count 0 2006.217.07:40:11.96#ibcon#end of sib2, iclass 4, count 0 2006.217.07:40:11.96#ibcon#*after write, iclass 4, count 0 2006.217.07:40:11.96#ibcon#*before return 0, iclass 4, count 0 2006.217.07:40:11.96#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.217.07:40:11.96#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.217.07:40:11.96#ibcon#about to clear, iclass 4 cls_cnt 0 2006.217.07:40:11.96#ibcon#cleared, iclass 4 cls_cnt 0 2006.217.07:40:11.96$vc4f8/vb=5,4 2006.217.07:40:11.96#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.217.07:40:11.96#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.217.07:40:11.96#ibcon#ireg 11 cls_cnt 2 2006.217.07:40:11.96#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.217.07:40:12.01#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.217.07:40:12.01#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.217.07:40:12.01#ibcon#enter wrdev, iclass 6, count 2 2006.217.07:40:12.01#ibcon#first serial, iclass 6, count 2 2006.217.07:40:12.01#ibcon#enter sib2, iclass 6, count 2 2006.217.07:40:12.01#ibcon#flushed, iclass 6, count 2 2006.217.07:40:12.02#ibcon#about to write, iclass 6, count 2 2006.217.07:40:12.02#ibcon#wrote, iclass 6, count 2 2006.217.07:40:12.02#ibcon#about to read 3, iclass 6, count 2 2006.217.07:40:12.03#ibcon#read 3, iclass 6, count 2 2006.217.07:40:12.03#ibcon#about to read 4, iclass 6, count 2 2006.217.07:40:12.03#ibcon#read 4, iclass 6, count 2 2006.217.07:40:12.03#ibcon#about to read 5, iclass 6, count 2 2006.217.07:40:12.03#ibcon#read 5, iclass 6, count 2 2006.217.07:40:12.03#ibcon#about to read 6, iclass 6, count 2 2006.217.07:40:12.04#ibcon#read 6, iclass 6, count 2 2006.217.07:40:12.04#ibcon#end of sib2, iclass 6, count 2 2006.217.07:40:12.04#ibcon#*mode == 0, iclass 6, count 2 2006.217.07:40:12.04#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.217.07:40:12.04#ibcon#[27=AT05-04\r\n] 2006.217.07:40:12.04#ibcon#*before write, iclass 6, count 2 2006.217.07:40:12.04#ibcon#enter sib2, iclass 6, count 2 2006.217.07:40:12.04#ibcon#flushed, iclass 6, count 2 2006.217.07:40:12.04#ibcon#about to write, iclass 6, count 2 2006.217.07:40:12.04#ibcon#wrote, iclass 6, count 2 2006.217.07:40:12.04#ibcon#about to read 3, iclass 6, count 2 2006.217.07:40:12.06#ibcon#read 3, iclass 6, count 2 2006.217.07:40:12.06#ibcon#about to read 4, iclass 6, count 2 2006.217.07:40:12.06#ibcon#read 4, iclass 6, count 2 2006.217.07:40:12.06#ibcon#about to read 5, iclass 6, count 2 2006.217.07:40:12.06#ibcon#read 5, iclass 6, count 2 2006.217.07:40:12.07#ibcon#about to read 6, iclass 6, count 2 2006.217.07:40:12.07#ibcon#read 6, iclass 6, count 2 2006.217.07:40:12.07#ibcon#end of sib2, iclass 6, count 2 2006.217.07:40:12.07#ibcon#*after write, iclass 6, count 2 2006.217.07:40:12.07#ibcon#*before return 0, iclass 6, count 2 2006.217.07:40:12.07#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.217.07:40:12.07#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.217.07:40:12.07#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.217.07:40:12.07#ibcon#ireg 7 cls_cnt 0 2006.217.07:40:12.07#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.217.07:40:12.18#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.217.07:40:12.18#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.217.07:40:12.18#ibcon#enter wrdev, iclass 6, count 0 2006.217.07:40:12.18#ibcon#first serial, iclass 6, count 0 2006.217.07:40:12.18#ibcon#enter sib2, iclass 6, count 0 2006.217.07:40:12.18#ibcon#flushed, iclass 6, count 0 2006.217.07:40:12.18#ibcon#about to write, iclass 6, count 0 2006.217.07:40:12.19#ibcon#wrote, iclass 6, count 0 2006.217.07:40:12.19#ibcon#about to read 3, iclass 6, count 0 2006.217.07:40:12.22#ibcon#read 3, iclass 6, count 0 2006.217.07:40:12.22#ibcon#about to read 4, iclass 6, count 0 2006.217.07:40:12.22#ibcon#read 4, iclass 6, count 0 2006.217.07:40:12.22#ibcon#about to read 5, iclass 6, count 0 2006.217.07:40:12.22#ibcon#read 5, iclass 6, count 0 2006.217.07:40:12.22#ibcon#about to read 6, iclass 6, count 0 2006.217.07:40:12.22#ibcon#read 6, iclass 6, count 0 2006.217.07:40:12.22#ibcon#end of sib2, iclass 6, count 0 2006.217.07:40:12.22#ibcon#*mode == 0, iclass 6, count 0 2006.217.07:40:12.22#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.217.07:40:12.22#ibcon#[27=USB\r\n] 2006.217.07:40:12.22#ibcon#*before write, iclass 6, count 0 2006.217.07:40:12.22#ibcon#enter sib2, iclass 6, count 0 2006.217.07:40:12.22#ibcon#flushed, iclass 6, count 0 2006.217.07:40:12.22#ibcon#about to write, iclass 6, count 0 2006.217.07:40:12.22#ibcon#wrote, iclass 6, count 0 2006.217.07:40:12.22#ibcon#about to read 3, iclass 6, count 0 2006.217.07:40:12.24#ibcon#read 3, iclass 6, count 0 2006.217.07:40:12.24#ibcon#about to read 4, iclass 6, count 0 2006.217.07:40:12.24#ibcon#read 4, iclass 6, count 0 2006.217.07:40:12.24#ibcon#about to read 5, iclass 6, count 0 2006.217.07:40:12.24#ibcon#read 5, iclass 6, count 0 2006.217.07:40:12.25#ibcon#about to read 6, iclass 6, count 0 2006.217.07:40:12.25#ibcon#read 6, iclass 6, count 0 2006.217.07:40:12.25#ibcon#end of sib2, iclass 6, count 0 2006.217.07:40:12.25#ibcon#*after write, iclass 6, count 0 2006.217.07:40:12.25#ibcon#*before return 0, iclass 6, count 0 2006.217.07:40:12.25#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.217.07:40:12.25#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.217.07:40:12.25#ibcon#about to clear, iclass 6 cls_cnt 0 2006.217.07:40:12.25#ibcon#cleared, iclass 6 cls_cnt 0 2006.217.07:40:12.25$vc4f8/vblo=6,752.99 2006.217.07:40:12.25#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.217.07:40:12.25#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.217.07:40:12.25#ibcon#ireg 17 cls_cnt 0 2006.217.07:40:12.25#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.217.07:40:12.25#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.217.07:40:12.25#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.217.07:40:12.25#ibcon#enter wrdev, iclass 10, count 0 2006.217.07:40:12.25#ibcon#first serial, iclass 10, count 0 2006.217.07:40:12.25#ibcon#enter sib2, iclass 10, count 0 2006.217.07:40:12.25#ibcon#flushed, iclass 10, count 0 2006.217.07:40:12.25#ibcon#about to write, iclass 10, count 0 2006.217.07:40:12.25#ibcon#wrote, iclass 10, count 0 2006.217.07:40:12.25#ibcon#about to read 3, iclass 10, count 0 2006.217.07:40:12.26#ibcon#read 3, iclass 10, count 0 2006.217.07:40:12.26#ibcon#about to read 4, iclass 10, count 0 2006.217.07:40:12.26#ibcon#read 4, iclass 10, count 0 2006.217.07:40:12.26#ibcon#about to read 5, iclass 10, count 0 2006.217.07:40:12.27#ibcon#read 5, iclass 10, count 0 2006.217.07:40:12.27#ibcon#about to read 6, iclass 10, count 0 2006.217.07:40:12.27#ibcon#read 6, iclass 10, count 0 2006.217.07:40:12.27#ibcon#end of sib2, iclass 10, count 0 2006.217.07:40:12.27#ibcon#*mode == 0, iclass 10, count 0 2006.217.07:40:12.27#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.217.07:40:12.27#ibcon#[28=FRQ=06,752.99\r\n] 2006.217.07:40:12.27#ibcon#*before write, iclass 10, count 0 2006.217.07:40:12.27#ibcon#enter sib2, iclass 10, count 0 2006.217.07:40:12.27#ibcon#flushed, iclass 10, count 0 2006.217.07:40:12.27#ibcon#about to write, iclass 10, count 0 2006.217.07:40:12.27#ibcon#wrote, iclass 10, count 0 2006.217.07:40:12.27#ibcon#about to read 3, iclass 10, count 0 2006.217.07:40:12.30#ibcon#read 3, iclass 10, count 0 2006.217.07:40:12.30#ibcon#about to read 4, iclass 10, count 0 2006.217.07:40:12.30#ibcon#read 4, iclass 10, count 0 2006.217.07:40:12.30#ibcon#about to read 5, iclass 10, count 0 2006.217.07:40:12.30#ibcon#read 5, iclass 10, count 0 2006.217.07:40:12.31#ibcon#about to read 6, iclass 10, count 0 2006.217.07:40:12.31#ibcon#read 6, iclass 10, count 0 2006.217.07:40:12.31#ibcon#end of sib2, iclass 10, count 0 2006.217.07:40:12.31#ibcon#*after write, iclass 10, count 0 2006.217.07:40:12.31#ibcon#*before return 0, iclass 10, count 0 2006.217.07:40:12.31#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.217.07:40:12.31#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.217.07:40:12.31#ibcon#about to clear, iclass 10 cls_cnt 0 2006.217.07:40:12.31#ibcon#cleared, iclass 10 cls_cnt 0 2006.217.07:40:12.31$vc4f8/vb=6,4 2006.217.07:40:12.31#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.217.07:40:12.31#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.217.07:40:12.31#ibcon#ireg 11 cls_cnt 2 2006.217.07:40:12.31#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.217.07:40:12.36#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.217.07:40:12.36#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.217.07:40:12.36#ibcon#enter wrdev, iclass 12, count 2 2006.217.07:40:12.37#ibcon#first serial, iclass 12, count 2 2006.217.07:40:12.37#ibcon#enter sib2, iclass 12, count 2 2006.217.07:40:12.37#ibcon#flushed, iclass 12, count 2 2006.217.07:40:12.37#ibcon#about to write, iclass 12, count 2 2006.217.07:40:12.37#ibcon#wrote, iclass 12, count 2 2006.217.07:40:12.37#ibcon#about to read 3, iclass 12, count 2 2006.217.07:40:12.38#ibcon#read 3, iclass 12, count 2 2006.217.07:40:12.38#ibcon#about to read 4, iclass 12, count 2 2006.217.07:40:12.38#ibcon#read 4, iclass 12, count 2 2006.217.07:40:12.38#ibcon#about to read 5, iclass 12, count 2 2006.217.07:40:12.39#ibcon#read 5, iclass 12, count 2 2006.217.07:40:12.39#ibcon#about to read 6, iclass 12, count 2 2006.217.07:40:12.39#ibcon#read 6, iclass 12, count 2 2006.217.07:40:12.39#ibcon#end of sib2, iclass 12, count 2 2006.217.07:40:12.39#ibcon#*mode == 0, iclass 12, count 2 2006.217.07:40:12.39#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.217.07:40:12.39#ibcon#[27=AT06-04\r\n] 2006.217.07:40:12.39#ibcon#*before write, iclass 12, count 2 2006.217.07:40:12.39#ibcon#enter sib2, iclass 12, count 2 2006.217.07:40:12.39#ibcon#flushed, iclass 12, count 2 2006.217.07:40:12.39#ibcon#about to write, iclass 12, count 2 2006.217.07:40:12.39#ibcon#wrote, iclass 12, count 2 2006.217.07:40:12.39#ibcon#about to read 3, iclass 12, count 2 2006.217.07:40:12.41#ibcon#read 3, iclass 12, count 2 2006.217.07:40:12.41#ibcon#about to read 4, iclass 12, count 2 2006.217.07:40:12.41#ibcon#read 4, iclass 12, count 2 2006.217.07:40:12.41#ibcon#about to read 5, iclass 12, count 2 2006.217.07:40:12.41#ibcon#read 5, iclass 12, count 2 2006.217.07:40:12.42#ibcon#about to read 6, iclass 12, count 2 2006.217.07:40:12.42#ibcon#read 6, iclass 12, count 2 2006.217.07:40:12.42#ibcon#end of sib2, iclass 12, count 2 2006.217.07:40:12.42#ibcon#*after write, iclass 12, count 2 2006.217.07:40:12.42#ibcon#*before return 0, iclass 12, count 2 2006.217.07:40:12.42#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.217.07:40:12.42#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.217.07:40:12.42#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.217.07:40:12.42#ibcon#ireg 7 cls_cnt 0 2006.217.07:40:12.42#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.217.07:40:12.53#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.217.07:40:12.53#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.217.07:40:12.53#ibcon#enter wrdev, iclass 12, count 0 2006.217.07:40:12.53#ibcon#first serial, iclass 12, count 0 2006.217.07:40:12.53#ibcon#enter sib2, iclass 12, count 0 2006.217.07:40:12.53#ibcon#flushed, iclass 12, count 0 2006.217.07:40:12.53#ibcon#about to write, iclass 12, count 0 2006.217.07:40:12.54#ibcon#wrote, iclass 12, count 0 2006.217.07:40:12.54#ibcon#about to read 3, iclass 12, count 0 2006.217.07:40:12.55#ibcon#read 3, iclass 12, count 0 2006.217.07:40:12.55#ibcon#about to read 4, iclass 12, count 0 2006.217.07:40:12.55#ibcon#read 4, iclass 12, count 0 2006.217.07:40:12.55#ibcon#about to read 5, iclass 12, count 0 2006.217.07:40:12.55#ibcon#read 5, iclass 12, count 0 2006.217.07:40:12.56#ibcon#about to read 6, iclass 12, count 0 2006.217.07:40:12.56#ibcon#read 6, iclass 12, count 0 2006.217.07:40:12.56#ibcon#end of sib2, iclass 12, count 0 2006.217.07:40:12.56#ibcon#*mode == 0, iclass 12, count 0 2006.217.07:40:12.56#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.217.07:40:12.56#ibcon#[27=USB\r\n] 2006.217.07:40:12.56#ibcon#*before write, iclass 12, count 0 2006.217.07:40:12.56#ibcon#enter sib2, iclass 12, count 0 2006.217.07:40:12.56#ibcon#flushed, iclass 12, count 0 2006.217.07:40:12.56#ibcon#about to write, iclass 12, count 0 2006.217.07:40:12.56#ibcon#wrote, iclass 12, count 0 2006.217.07:40:12.56#ibcon#about to read 3, iclass 12, count 0 2006.217.07:40:12.58#ibcon#read 3, iclass 12, count 0 2006.217.07:40:12.58#ibcon#about to read 4, iclass 12, count 0 2006.217.07:40:12.58#ibcon#read 4, iclass 12, count 0 2006.217.07:40:12.58#ibcon#about to read 5, iclass 12, count 0 2006.217.07:40:12.58#ibcon#read 5, iclass 12, count 0 2006.217.07:40:12.59#ibcon#about to read 6, iclass 12, count 0 2006.217.07:40:12.59#ibcon#read 6, iclass 12, count 0 2006.217.07:40:12.59#ibcon#end of sib2, iclass 12, count 0 2006.217.07:40:12.59#ibcon#*after write, iclass 12, count 0 2006.217.07:40:12.59#ibcon#*before return 0, iclass 12, count 0 2006.217.07:40:12.59#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.217.07:40:12.59#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.217.07:40:12.59#ibcon#about to clear, iclass 12 cls_cnt 0 2006.217.07:40:12.59#ibcon#cleared, iclass 12 cls_cnt 0 2006.217.07:40:12.59$vc4f8/vabw=wide 2006.217.07:40:12.59#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.217.07:40:12.59#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.217.07:40:12.59#ibcon#ireg 8 cls_cnt 0 2006.217.07:40:12.59#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.217.07:40:12.59#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.217.07:40:12.59#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.217.07:40:12.59#ibcon#enter wrdev, iclass 14, count 0 2006.217.07:40:12.59#ibcon#first serial, iclass 14, count 0 2006.217.07:40:12.59#ibcon#enter sib2, iclass 14, count 0 2006.217.07:40:12.59#ibcon#flushed, iclass 14, count 0 2006.217.07:40:12.59#ibcon#about to write, iclass 14, count 0 2006.217.07:40:12.59#ibcon#wrote, iclass 14, count 0 2006.217.07:40:12.59#ibcon#about to read 3, iclass 14, count 0 2006.217.07:40:12.60#ibcon#read 3, iclass 14, count 0 2006.217.07:40:12.60#ibcon#about to read 4, iclass 14, count 0 2006.217.07:40:12.60#ibcon#read 4, iclass 14, count 0 2006.217.07:40:12.60#ibcon#about to read 5, iclass 14, count 0 2006.217.07:40:12.60#ibcon#read 5, iclass 14, count 0 2006.217.07:40:12.61#ibcon#about to read 6, iclass 14, count 0 2006.217.07:40:12.61#ibcon#read 6, iclass 14, count 0 2006.217.07:40:12.61#ibcon#end of sib2, iclass 14, count 0 2006.217.07:40:12.61#ibcon#*mode == 0, iclass 14, count 0 2006.217.07:40:12.61#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.217.07:40:12.61#ibcon#[25=BW32\r\n] 2006.217.07:40:12.61#ibcon#*before write, iclass 14, count 0 2006.217.07:40:12.61#ibcon#enter sib2, iclass 14, count 0 2006.217.07:40:12.61#ibcon#flushed, iclass 14, count 0 2006.217.07:40:12.61#ibcon#about to write, iclass 14, count 0 2006.217.07:40:12.61#ibcon#wrote, iclass 14, count 0 2006.217.07:40:12.61#ibcon#about to read 3, iclass 14, count 0 2006.217.07:40:12.63#ibcon#read 3, iclass 14, count 0 2006.217.07:40:12.63#ibcon#about to read 4, iclass 14, count 0 2006.217.07:40:12.64#ibcon#read 4, iclass 14, count 0 2006.217.07:40:12.64#ibcon#about to read 5, iclass 14, count 0 2006.217.07:40:12.64#ibcon#read 5, iclass 14, count 0 2006.217.07:40:12.64#ibcon#about to read 6, iclass 14, count 0 2006.217.07:40:12.64#ibcon#read 6, iclass 14, count 0 2006.217.07:40:12.64#ibcon#end of sib2, iclass 14, count 0 2006.217.07:40:12.64#ibcon#*after write, iclass 14, count 0 2006.217.07:40:12.64#ibcon#*before return 0, iclass 14, count 0 2006.217.07:40:12.64#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.217.07:40:12.64#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.217.07:40:12.64#ibcon#about to clear, iclass 14 cls_cnt 0 2006.217.07:40:12.64#ibcon#cleared, iclass 14 cls_cnt 0 2006.217.07:40:12.64$vc4f8/vbbw=wide 2006.217.07:40:12.64#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.217.07:40:12.64#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.217.07:40:12.64#ibcon#ireg 8 cls_cnt 0 2006.217.07:40:12.64#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.217.07:40:12.70#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.217.07:40:12.70#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.217.07:40:12.70#ibcon#enter wrdev, iclass 16, count 0 2006.217.07:40:12.70#ibcon#first serial, iclass 16, count 0 2006.217.07:40:12.70#ibcon#enter sib2, iclass 16, count 0 2006.217.07:40:12.70#ibcon#flushed, iclass 16, count 0 2006.217.07:40:12.71#ibcon#about to write, iclass 16, count 0 2006.217.07:40:12.71#ibcon#wrote, iclass 16, count 0 2006.217.07:40:12.71#ibcon#about to read 3, iclass 16, count 0 2006.217.07:40:12.72#ibcon#read 3, iclass 16, count 0 2006.217.07:40:12.72#ibcon#about to read 4, iclass 16, count 0 2006.217.07:40:12.72#ibcon#read 4, iclass 16, count 0 2006.217.07:40:12.72#ibcon#about to read 5, iclass 16, count 0 2006.217.07:40:12.73#ibcon#read 5, iclass 16, count 0 2006.217.07:40:12.73#ibcon#about to read 6, iclass 16, count 0 2006.217.07:40:12.73#ibcon#read 6, iclass 16, count 0 2006.217.07:40:12.73#ibcon#end of sib2, iclass 16, count 0 2006.217.07:40:12.73#ibcon#*mode == 0, iclass 16, count 0 2006.217.07:40:12.73#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.217.07:40:12.73#ibcon#[27=BW32\r\n] 2006.217.07:40:12.73#ibcon#*before write, iclass 16, count 0 2006.217.07:40:12.73#ibcon#enter sib2, iclass 16, count 0 2006.217.07:40:12.73#ibcon#flushed, iclass 16, count 0 2006.217.07:40:12.73#ibcon#about to write, iclass 16, count 0 2006.217.07:40:12.73#ibcon#wrote, iclass 16, count 0 2006.217.07:40:12.73#ibcon#about to read 3, iclass 16, count 0 2006.217.07:40:12.75#ibcon#read 3, iclass 16, count 0 2006.217.07:40:12.75#ibcon#about to read 4, iclass 16, count 0 2006.217.07:40:12.75#ibcon#read 4, iclass 16, count 0 2006.217.07:40:12.75#ibcon#about to read 5, iclass 16, count 0 2006.217.07:40:12.75#ibcon#read 5, iclass 16, count 0 2006.217.07:40:12.76#ibcon#about to read 6, iclass 16, count 0 2006.217.07:40:12.76#ibcon#read 6, iclass 16, count 0 2006.217.07:40:12.76#ibcon#end of sib2, iclass 16, count 0 2006.217.07:40:12.76#ibcon#*after write, iclass 16, count 0 2006.217.07:40:12.76#ibcon#*before return 0, iclass 16, count 0 2006.217.07:40:12.76#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.217.07:40:12.76#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.217.07:40:12.76#ibcon#about to clear, iclass 16 cls_cnt 0 2006.217.07:40:12.76#ibcon#cleared, iclass 16 cls_cnt 0 2006.217.07:40:12.76$4f8m12a/ifd4f 2006.217.07:40:12.76$ifd4f/lo= 2006.217.07:40:12.76$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.217.07:40:12.76$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.217.07:40:12.76$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.217.07:40:12.76$ifd4f/patch= 2006.217.07:40:12.76$ifd4f/patch=lo1,a1,a2,a3,a4 2006.217.07:40:12.76$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.217.07:40:12.76$ifd4f/patch=lo3,a5,a6,a7,a8 2006.217.07:40:12.76$4f8m12a/"form=m,16.000,1:2 2006.217.07:40:12.76$4f8m12a/"tpicd 2006.217.07:40:12.76$4f8m12a/echo=off 2006.217.07:40:12.76$4f8m12a/xlog=off 2006.217.07:40:12.76:!2006.217.07:40:40 2006.217.07:40:23.14#trakl#Source acquired 2006.217.07:40:25.15#flagr#flagr/antenna,acquired 2006.217.07:40:40.02:preob 2006.217.07:40:41.14/onsource/TRACKING 2006.217.07:40:41.14:!2006.217.07:40:50 2006.217.07:40:50.02:data_valid=on 2006.217.07:40:50.02:midob 2006.217.07:40:51.14/onsource/TRACKING 2006.217.07:40:51.14/wx/31.28,1008.6,61 2006.217.07:40:51.18/cable/+6.3837E-03 2006.217.07:40:52.27/va/01,05,usb,yes,31,33 2006.217.07:40:52.27/va/02,04,usb,yes,29,30 2006.217.07:40:52.27/va/03,04,usb,yes,27,27 2006.217.07:40:52.27/va/04,04,usb,yes,30,33 2006.217.07:40:52.27/va/05,07,usb,yes,32,34 2006.217.07:40:52.27/va/06,06,usb,yes,31,31 2006.217.07:40:52.27/va/07,06,usb,yes,32,32 2006.217.07:40:52.27/va/08,07,usb,yes,30,30 2006.217.07:40:52.50/valo/01,532.99,yes,locked 2006.217.07:40:52.50/valo/02,572.99,yes,locked 2006.217.07:40:52.50/valo/03,672.99,yes,locked 2006.217.07:40:52.50/valo/04,832.99,yes,locked 2006.217.07:40:52.50/valo/05,652.99,yes,locked 2006.217.07:40:52.51/valo/06,772.99,yes,locked 2006.217.07:40:52.51/valo/07,832.99,yes,locked 2006.217.07:40:52.51/valo/08,852.99,yes,locked 2006.217.07:40:53.59/vb/01,04,usb,yes,30,29 2006.217.07:40:53.59/vb/02,04,usb,yes,32,33 2006.217.07:40:53.59/vb/03,04,usb,yes,28,32 2006.217.07:40:53.59/vb/04,04,usb,yes,29,29 2006.217.07:40:53.59/vb/05,04,usb,yes,27,31 2006.217.07:40:53.59/vb/06,04,usb,yes,28,31 2006.217.07:40:53.59/vb/07,04,usb,yes,30,30 2006.217.07:40:53.59/vb/08,04,usb,yes,28,31 2006.217.07:40:53.82/vblo/01,632.99,yes,locked 2006.217.07:40:53.82/vblo/02,640.99,yes,locked 2006.217.07:40:53.82/vblo/03,656.99,yes,locked 2006.217.07:40:53.82/vblo/04,712.99,yes,locked 2006.217.07:40:53.82/vblo/05,744.99,yes,locked 2006.217.07:40:53.82/vblo/06,752.99,yes,locked 2006.217.07:40:53.83/vblo/07,734.99,yes,locked 2006.217.07:40:53.83/vblo/08,744.99,yes,locked 2006.217.07:40:53.97/vabw/8 2006.217.07:40:54.12/vbbw/8 2006.217.07:40:54.21/xfe/off,on,14.7 2006.217.07:40:54.58/ifatt/23,28,28,28 2006.217.07:40:55.06/fmout-gps/S +4.34E-07 2006.217.07:40:55.14:!2006.217.07:41:50 2006.217.07:41:50.02:data_valid=off 2006.217.07:41:50.02:postob 2006.217.07:41:50.17/cable/+6.3855E-03 2006.217.07:41:50.21/wx/31.28,1008.6,61 2006.217.07:41:51.07/fmout-gps/S +4.33E-07 2006.217.07:41:51.08:scan_name=217-0742,k06217,60 2006.217.07:41:51.08:source=1739+522,174036.98,521143.4,2000.0,cw 2006.217.07:41:52.14#flagr#flagr/antenna,new-source 2006.217.07:41:52.14:checkk5 2006.217.07:41:52.52/chk_autoobs//k5ts1/ autoobs is running! 2006.217.07:41:52.89/chk_autoobs//k5ts2/ autoobs is running! 2006.217.07:41:53.28/chk_autoobs//k5ts3/ autoobs is running! 2006.217.07:41:53.65/chk_autoobs//k5ts4/ autoobs is running! 2006.217.07:41:54.02/chk_obsdata//k5ts1/T2170740??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:41:54.38/chk_obsdata//k5ts2/T2170740??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:41:54.75/chk_obsdata//k5ts3/T2170740??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:41:55.11/chk_obsdata//k5ts4/T2170740??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:41:55.80/k5log//k5ts1_log_newline 2006.217.07:41:56.49/k5log//k5ts2_log_newline 2006.217.07:41:57.17/k5log//k5ts3_log_newline 2006.217.07:41:57.86/k5log//k5ts4_log_newline 2006.217.07:41:57.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.217.07:41:57.88:4f8m12a=1 2006.217.07:41:57.88$4f8m12a/echo=on 2006.217.07:41:57.88$4f8m12a/pcalon 2006.217.07:41:57.88$pcalon/"no phase cal control is implemented here 2006.217.07:41:57.88$4f8m12a/"tpicd=stop 2006.217.07:41:57.88$4f8m12a/vc4f8 2006.217.07:41:57.88$vc4f8/valo=1,532.99 2006.217.07:41:57.89#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.217.07:41:57.89#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.217.07:41:57.89#ibcon#ireg 17 cls_cnt 0 2006.217.07:41:57.89#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.217.07:41:57.89#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.217.07:41:57.89#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.217.07:41:57.89#ibcon#enter wrdev, iclass 23, count 0 2006.217.07:41:57.89#ibcon#first serial, iclass 23, count 0 2006.217.07:41:57.89#ibcon#enter sib2, iclass 23, count 0 2006.217.07:41:57.89#ibcon#flushed, iclass 23, count 0 2006.217.07:41:57.89#ibcon#about to write, iclass 23, count 0 2006.217.07:41:57.89#ibcon#wrote, iclass 23, count 0 2006.217.07:41:57.89#ibcon#about to read 3, iclass 23, count 0 2006.217.07:41:57.93#ibcon#read 3, iclass 23, count 0 2006.217.07:41:57.93#ibcon#about to read 4, iclass 23, count 0 2006.217.07:41:57.93#ibcon#read 4, iclass 23, count 0 2006.217.07:41:57.93#ibcon#about to read 5, iclass 23, count 0 2006.217.07:41:57.93#ibcon#read 5, iclass 23, count 0 2006.217.07:41:57.93#ibcon#about to read 6, iclass 23, count 0 2006.217.07:41:57.93#ibcon#read 6, iclass 23, count 0 2006.217.07:41:57.93#ibcon#end of sib2, iclass 23, count 0 2006.217.07:41:57.93#ibcon#*mode == 0, iclass 23, count 0 2006.217.07:41:57.93#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.217.07:41:57.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.217.07:41:57.93#ibcon#*before write, iclass 23, count 0 2006.217.07:41:57.93#ibcon#enter sib2, iclass 23, count 0 2006.217.07:41:57.93#ibcon#flushed, iclass 23, count 0 2006.217.07:41:57.93#ibcon#about to write, iclass 23, count 0 2006.217.07:41:57.93#ibcon#wrote, iclass 23, count 0 2006.217.07:41:57.93#ibcon#about to read 3, iclass 23, count 0 2006.217.07:41:57.97#ibcon#read 3, iclass 23, count 0 2006.217.07:41:57.97#ibcon#about to read 4, iclass 23, count 0 2006.217.07:41:57.97#ibcon#read 4, iclass 23, count 0 2006.217.07:41:57.97#ibcon#about to read 5, iclass 23, count 0 2006.217.07:41:57.97#ibcon#read 5, iclass 23, count 0 2006.217.07:41:57.97#ibcon#about to read 6, iclass 23, count 0 2006.217.07:41:57.97#ibcon#read 6, iclass 23, count 0 2006.217.07:41:57.97#ibcon#end of sib2, iclass 23, count 0 2006.217.07:41:57.97#ibcon#*after write, iclass 23, count 0 2006.217.07:41:57.97#ibcon#*before return 0, iclass 23, count 0 2006.217.07:41:57.97#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.217.07:41:57.97#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.217.07:41:57.97#ibcon#about to clear, iclass 23 cls_cnt 0 2006.217.07:41:57.97#ibcon#cleared, iclass 23 cls_cnt 0 2006.217.07:41:57.98$vc4f8/va=1,5 2006.217.07:41:57.98#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.217.07:41:57.98#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.217.07:41:57.98#ibcon#ireg 11 cls_cnt 2 2006.217.07:41:57.98#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.217.07:41:57.98#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.217.07:41:57.98#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.217.07:41:57.98#ibcon#enter wrdev, iclass 25, count 2 2006.217.07:41:57.98#ibcon#first serial, iclass 25, count 2 2006.217.07:41:57.98#ibcon#enter sib2, iclass 25, count 2 2006.217.07:41:57.98#ibcon#flushed, iclass 25, count 2 2006.217.07:41:57.98#ibcon#about to write, iclass 25, count 2 2006.217.07:41:57.98#ibcon#wrote, iclass 25, count 2 2006.217.07:41:57.98#ibcon#about to read 3, iclass 25, count 2 2006.217.07:41:57.99#ibcon#read 3, iclass 25, count 2 2006.217.07:41:57.99#ibcon#about to read 4, iclass 25, count 2 2006.217.07:41:57.99#ibcon#read 4, iclass 25, count 2 2006.217.07:41:57.99#ibcon#about to read 5, iclass 25, count 2 2006.217.07:41:57.99#ibcon#read 5, iclass 25, count 2 2006.217.07:41:57.99#ibcon#about to read 6, iclass 25, count 2 2006.217.07:41:57.99#ibcon#read 6, iclass 25, count 2 2006.217.07:41:57.99#ibcon#end of sib2, iclass 25, count 2 2006.217.07:41:57.99#ibcon#*mode == 0, iclass 25, count 2 2006.217.07:41:57.99#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.217.07:41:57.99#ibcon#[25=AT01-05\r\n] 2006.217.07:41:57.99#ibcon#*before write, iclass 25, count 2 2006.217.07:41:57.99#ibcon#enter sib2, iclass 25, count 2 2006.217.07:41:57.99#ibcon#flushed, iclass 25, count 2 2006.217.07:41:57.99#ibcon#about to write, iclass 25, count 2 2006.217.07:41:57.99#ibcon#wrote, iclass 25, count 2 2006.217.07:41:57.99#ibcon#about to read 3, iclass 25, count 2 2006.217.07:41:58.03#ibcon#read 3, iclass 25, count 2 2006.217.07:41:58.03#ibcon#about to read 4, iclass 25, count 2 2006.217.07:41:58.03#ibcon#read 4, iclass 25, count 2 2006.217.07:41:58.03#ibcon#about to read 5, iclass 25, count 2 2006.217.07:41:58.03#ibcon#read 5, iclass 25, count 2 2006.217.07:41:58.03#ibcon#about to read 6, iclass 25, count 2 2006.217.07:41:58.03#ibcon#read 6, iclass 25, count 2 2006.217.07:41:58.03#ibcon#end of sib2, iclass 25, count 2 2006.217.07:41:58.03#ibcon#*after write, iclass 25, count 2 2006.217.07:41:58.03#ibcon#*before return 0, iclass 25, count 2 2006.217.07:41:58.03#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.217.07:41:58.03#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.217.07:41:58.03#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.217.07:41:58.03#ibcon#ireg 7 cls_cnt 0 2006.217.07:41:58.03#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.217.07:41:58.15#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.217.07:41:58.15#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.217.07:41:58.15#ibcon#enter wrdev, iclass 25, count 0 2006.217.07:41:58.15#ibcon#first serial, iclass 25, count 0 2006.217.07:41:58.15#ibcon#enter sib2, iclass 25, count 0 2006.217.07:41:58.15#ibcon#flushed, iclass 25, count 0 2006.217.07:41:58.15#ibcon#about to write, iclass 25, count 0 2006.217.07:41:58.15#ibcon#wrote, iclass 25, count 0 2006.217.07:41:58.15#ibcon#about to read 3, iclass 25, count 0 2006.217.07:41:58.16#ibcon#read 3, iclass 25, count 0 2006.217.07:41:58.16#ibcon#about to read 4, iclass 25, count 0 2006.217.07:41:58.16#ibcon#read 4, iclass 25, count 0 2006.217.07:41:58.16#ibcon#about to read 5, iclass 25, count 0 2006.217.07:41:58.16#ibcon#read 5, iclass 25, count 0 2006.217.07:41:58.16#ibcon#about to read 6, iclass 25, count 0 2006.217.07:41:58.16#ibcon#read 6, iclass 25, count 0 2006.217.07:41:58.16#ibcon#end of sib2, iclass 25, count 0 2006.217.07:41:58.16#ibcon#*mode == 0, iclass 25, count 0 2006.217.07:41:58.16#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.217.07:41:58.16#ibcon#[25=USB\r\n] 2006.217.07:41:58.16#ibcon#*before write, iclass 25, count 0 2006.217.07:41:58.16#ibcon#enter sib2, iclass 25, count 0 2006.217.07:41:58.16#ibcon#flushed, iclass 25, count 0 2006.217.07:41:58.16#ibcon#about to write, iclass 25, count 0 2006.217.07:41:58.16#ibcon#wrote, iclass 25, count 0 2006.217.07:41:58.16#ibcon#about to read 3, iclass 25, count 0 2006.217.07:41:58.19#ibcon#read 3, iclass 25, count 0 2006.217.07:41:58.19#ibcon#about to read 4, iclass 25, count 0 2006.217.07:41:58.19#ibcon#read 4, iclass 25, count 0 2006.217.07:41:58.19#ibcon#about to read 5, iclass 25, count 0 2006.217.07:41:58.19#ibcon#read 5, iclass 25, count 0 2006.217.07:41:58.19#ibcon#about to read 6, iclass 25, count 0 2006.217.07:41:58.19#ibcon#read 6, iclass 25, count 0 2006.217.07:41:58.19#ibcon#end of sib2, iclass 25, count 0 2006.217.07:41:58.19#ibcon#*after write, iclass 25, count 0 2006.217.07:41:58.19#ibcon#*before return 0, iclass 25, count 0 2006.217.07:41:58.19#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.217.07:41:58.19#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.217.07:41:58.19#ibcon#about to clear, iclass 25 cls_cnt 0 2006.217.07:41:58.19#ibcon#cleared, iclass 25 cls_cnt 0 2006.217.07:41:58.20$vc4f8/valo=2,572.99 2006.217.07:41:58.20#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.217.07:41:58.20#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.217.07:41:58.20#ibcon#ireg 17 cls_cnt 0 2006.217.07:41:58.20#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.217.07:41:58.20#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.217.07:41:58.20#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.217.07:41:58.20#ibcon#enter wrdev, iclass 27, count 0 2006.217.07:41:58.20#ibcon#first serial, iclass 27, count 0 2006.217.07:41:58.20#ibcon#enter sib2, iclass 27, count 0 2006.217.07:41:58.20#ibcon#flushed, iclass 27, count 0 2006.217.07:41:58.20#ibcon#about to write, iclass 27, count 0 2006.217.07:41:58.20#ibcon#wrote, iclass 27, count 0 2006.217.07:41:58.20#ibcon#about to read 3, iclass 27, count 0 2006.217.07:41:58.22#ibcon#read 3, iclass 27, count 0 2006.217.07:41:58.22#ibcon#about to read 4, iclass 27, count 0 2006.217.07:41:58.22#ibcon#read 4, iclass 27, count 0 2006.217.07:41:58.22#ibcon#about to read 5, iclass 27, count 0 2006.217.07:41:58.22#ibcon#read 5, iclass 27, count 0 2006.217.07:41:58.22#ibcon#about to read 6, iclass 27, count 0 2006.217.07:41:58.22#ibcon#read 6, iclass 27, count 0 2006.217.07:41:58.22#ibcon#end of sib2, iclass 27, count 0 2006.217.07:41:58.22#ibcon#*mode == 0, iclass 27, count 0 2006.217.07:41:58.22#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.217.07:41:58.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.217.07:41:58.22#ibcon#*before write, iclass 27, count 0 2006.217.07:41:58.22#ibcon#enter sib2, iclass 27, count 0 2006.217.07:41:58.22#ibcon#flushed, iclass 27, count 0 2006.217.07:41:58.22#ibcon#about to write, iclass 27, count 0 2006.217.07:41:58.22#ibcon#wrote, iclass 27, count 0 2006.217.07:41:58.22#ibcon#about to read 3, iclass 27, count 0 2006.217.07:41:58.26#ibcon#read 3, iclass 27, count 0 2006.217.07:41:58.26#ibcon#about to read 4, iclass 27, count 0 2006.217.07:41:58.26#ibcon#read 4, iclass 27, count 0 2006.217.07:41:58.26#ibcon#about to read 5, iclass 27, count 0 2006.217.07:41:58.26#ibcon#read 5, iclass 27, count 0 2006.217.07:41:58.26#ibcon#about to read 6, iclass 27, count 0 2006.217.07:41:58.26#ibcon#read 6, iclass 27, count 0 2006.217.07:41:58.26#ibcon#end of sib2, iclass 27, count 0 2006.217.07:41:58.26#ibcon#*after write, iclass 27, count 0 2006.217.07:41:58.26#ibcon#*before return 0, iclass 27, count 0 2006.217.07:41:58.26#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.217.07:41:58.26#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.217.07:41:58.26#ibcon#about to clear, iclass 27 cls_cnt 0 2006.217.07:41:58.26#ibcon#cleared, iclass 27 cls_cnt 0 2006.217.07:41:58.27$vc4f8/va=2,4 2006.217.07:41:58.27#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.217.07:41:58.27#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.217.07:41:58.27#ibcon#ireg 11 cls_cnt 2 2006.217.07:41:58.27#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.217.07:41:58.30#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.217.07:41:58.30#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.217.07:41:58.30#ibcon#enter wrdev, iclass 29, count 2 2006.217.07:41:58.30#ibcon#first serial, iclass 29, count 2 2006.217.07:41:58.30#ibcon#enter sib2, iclass 29, count 2 2006.217.07:41:58.30#ibcon#flushed, iclass 29, count 2 2006.217.07:41:58.30#ibcon#about to write, iclass 29, count 2 2006.217.07:41:58.30#ibcon#wrote, iclass 29, count 2 2006.217.07:41:58.30#ibcon#about to read 3, iclass 29, count 2 2006.217.07:41:58.33#ibcon#read 3, iclass 29, count 2 2006.217.07:41:58.33#ibcon#about to read 4, iclass 29, count 2 2006.217.07:41:58.33#ibcon#read 4, iclass 29, count 2 2006.217.07:41:58.33#ibcon#about to read 5, iclass 29, count 2 2006.217.07:41:58.33#ibcon#read 5, iclass 29, count 2 2006.217.07:41:58.33#ibcon#about to read 6, iclass 29, count 2 2006.217.07:41:58.33#ibcon#read 6, iclass 29, count 2 2006.217.07:41:58.33#ibcon#end of sib2, iclass 29, count 2 2006.217.07:41:58.33#ibcon#*mode == 0, iclass 29, count 2 2006.217.07:41:58.33#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.217.07:41:58.33#ibcon#[25=AT02-04\r\n] 2006.217.07:41:58.33#ibcon#*before write, iclass 29, count 2 2006.217.07:41:58.33#ibcon#enter sib2, iclass 29, count 2 2006.217.07:41:58.33#ibcon#flushed, iclass 29, count 2 2006.217.07:41:58.33#ibcon#about to write, iclass 29, count 2 2006.217.07:41:58.33#ibcon#wrote, iclass 29, count 2 2006.217.07:41:58.33#ibcon#about to read 3, iclass 29, count 2 2006.217.07:41:58.36#ibcon#read 3, iclass 29, count 2 2006.217.07:41:58.36#ibcon#about to read 4, iclass 29, count 2 2006.217.07:41:58.36#ibcon#read 4, iclass 29, count 2 2006.217.07:41:58.36#ibcon#about to read 5, iclass 29, count 2 2006.217.07:41:58.36#ibcon#read 5, iclass 29, count 2 2006.217.07:41:58.36#ibcon#about to read 6, iclass 29, count 2 2006.217.07:41:58.36#ibcon#read 6, iclass 29, count 2 2006.217.07:41:58.36#ibcon#end of sib2, iclass 29, count 2 2006.217.07:41:58.36#ibcon#*after write, iclass 29, count 2 2006.217.07:41:58.36#ibcon#*before return 0, iclass 29, count 2 2006.217.07:41:58.36#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.217.07:41:58.36#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.217.07:41:58.36#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.217.07:41:58.36#ibcon#ireg 7 cls_cnt 0 2006.217.07:41:58.36#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.217.07:41:58.48#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.217.07:41:58.48#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.217.07:41:58.48#ibcon#enter wrdev, iclass 29, count 0 2006.217.07:41:58.48#ibcon#first serial, iclass 29, count 0 2006.217.07:41:58.48#ibcon#enter sib2, iclass 29, count 0 2006.217.07:41:58.48#ibcon#flushed, iclass 29, count 0 2006.217.07:41:58.48#ibcon#about to write, iclass 29, count 0 2006.217.07:41:58.48#ibcon#wrote, iclass 29, count 0 2006.217.07:41:58.48#ibcon#about to read 3, iclass 29, count 0 2006.217.07:41:58.50#ibcon#read 3, iclass 29, count 0 2006.217.07:41:58.50#ibcon#about to read 4, iclass 29, count 0 2006.217.07:41:58.50#ibcon#read 4, iclass 29, count 0 2006.217.07:41:58.50#ibcon#about to read 5, iclass 29, count 0 2006.217.07:41:58.50#ibcon#read 5, iclass 29, count 0 2006.217.07:41:58.50#ibcon#about to read 6, iclass 29, count 0 2006.217.07:41:58.50#ibcon#read 6, iclass 29, count 0 2006.217.07:41:58.50#ibcon#end of sib2, iclass 29, count 0 2006.217.07:41:58.50#ibcon#*mode == 0, iclass 29, count 0 2006.217.07:41:58.50#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.217.07:41:58.50#ibcon#[25=USB\r\n] 2006.217.07:41:58.50#ibcon#*before write, iclass 29, count 0 2006.217.07:41:58.50#ibcon#enter sib2, iclass 29, count 0 2006.217.07:41:58.50#ibcon#flushed, iclass 29, count 0 2006.217.07:41:58.50#ibcon#about to write, iclass 29, count 0 2006.217.07:41:58.50#ibcon#wrote, iclass 29, count 0 2006.217.07:41:58.50#ibcon#about to read 3, iclass 29, count 0 2006.217.07:41:58.53#ibcon#read 3, iclass 29, count 0 2006.217.07:41:58.53#ibcon#about to read 4, iclass 29, count 0 2006.217.07:41:58.53#ibcon#read 4, iclass 29, count 0 2006.217.07:41:58.53#ibcon#about to read 5, iclass 29, count 0 2006.217.07:41:58.53#ibcon#read 5, iclass 29, count 0 2006.217.07:41:58.53#ibcon#about to read 6, iclass 29, count 0 2006.217.07:41:58.53#ibcon#read 6, iclass 29, count 0 2006.217.07:41:58.53#ibcon#end of sib2, iclass 29, count 0 2006.217.07:41:58.53#ibcon#*after write, iclass 29, count 0 2006.217.07:41:58.53#ibcon#*before return 0, iclass 29, count 0 2006.217.07:41:58.53#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.217.07:41:58.53#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.217.07:41:58.53#ibcon#about to clear, iclass 29 cls_cnt 0 2006.217.07:41:58.53#ibcon#cleared, iclass 29 cls_cnt 0 2006.217.07:41:58.54$vc4f8/valo=3,672.99 2006.217.07:41:58.54#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.217.07:41:58.54#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.217.07:41:58.54#ibcon#ireg 17 cls_cnt 0 2006.217.07:41:58.54#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.217.07:41:58.54#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.217.07:41:58.54#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.217.07:41:58.54#ibcon#enter wrdev, iclass 31, count 0 2006.217.07:41:58.54#ibcon#first serial, iclass 31, count 0 2006.217.07:41:58.54#ibcon#enter sib2, iclass 31, count 0 2006.217.07:41:58.54#ibcon#flushed, iclass 31, count 0 2006.217.07:41:58.54#ibcon#about to write, iclass 31, count 0 2006.217.07:41:58.54#ibcon#wrote, iclass 31, count 0 2006.217.07:41:58.54#ibcon#about to read 3, iclass 31, count 0 2006.217.07:41:58.56#ibcon#read 3, iclass 31, count 0 2006.217.07:41:58.56#ibcon#about to read 4, iclass 31, count 0 2006.217.07:41:58.56#ibcon#read 4, iclass 31, count 0 2006.217.07:41:58.56#ibcon#about to read 5, iclass 31, count 0 2006.217.07:41:58.56#ibcon#read 5, iclass 31, count 0 2006.217.07:41:58.56#ibcon#about to read 6, iclass 31, count 0 2006.217.07:41:58.56#ibcon#read 6, iclass 31, count 0 2006.217.07:41:58.56#ibcon#end of sib2, iclass 31, count 0 2006.217.07:41:58.56#ibcon#*mode == 0, iclass 31, count 0 2006.217.07:41:58.56#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.217.07:41:58.56#ibcon#[26=FRQ=03,672.99\r\n] 2006.217.07:41:58.56#ibcon#*before write, iclass 31, count 0 2006.217.07:41:58.56#ibcon#enter sib2, iclass 31, count 0 2006.217.07:41:58.56#ibcon#flushed, iclass 31, count 0 2006.217.07:41:58.56#ibcon#about to write, iclass 31, count 0 2006.217.07:41:58.56#ibcon#wrote, iclass 31, count 0 2006.217.07:41:58.56#ibcon#about to read 3, iclass 31, count 0 2006.217.07:41:58.60#ibcon#read 3, iclass 31, count 0 2006.217.07:41:58.60#ibcon#about to read 4, iclass 31, count 0 2006.217.07:41:58.60#ibcon#read 4, iclass 31, count 0 2006.217.07:41:58.60#ibcon#about to read 5, iclass 31, count 0 2006.217.07:41:58.60#ibcon#read 5, iclass 31, count 0 2006.217.07:41:58.60#ibcon#about to read 6, iclass 31, count 0 2006.217.07:41:58.60#ibcon#read 6, iclass 31, count 0 2006.217.07:41:58.60#ibcon#end of sib2, iclass 31, count 0 2006.217.07:41:58.60#ibcon#*after write, iclass 31, count 0 2006.217.07:41:58.60#ibcon#*before return 0, iclass 31, count 0 2006.217.07:41:58.60#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.217.07:41:58.60#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.217.07:41:58.60#ibcon#about to clear, iclass 31 cls_cnt 0 2006.217.07:41:58.60#ibcon#cleared, iclass 31 cls_cnt 0 2006.217.07:41:58.61$vc4f8/va=3,4 2006.217.07:41:58.61#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.217.07:41:58.61#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.217.07:41:58.61#ibcon#ireg 11 cls_cnt 2 2006.217.07:41:58.61#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.217.07:41:58.64#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.217.07:41:58.64#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.217.07:41:58.64#ibcon#enter wrdev, iclass 33, count 2 2006.217.07:41:58.64#ibcon#first serial, iclass 33, count 2 2006.217.07:41:58.64#ibcon#enter sib2, iclass 33, count 2 2006.217.07:41:58.64#ibcon#flushed, iclass 33, count 2 2006.217.07:41:58.64#ibcon#about to write, iclass 33, count 2 2006.217.07:41:58.64#ibcon#wrote, iclass 33, count 2 2006.217.07:41:58.64#ibcon#about to read 3, iclass 33, count 2 2006.217.07:41:58.67#ibcon#read 3, iclass 33, count 2 2006.217.07:41:58.67#ibcon#about to read 4, iclass 33, count 2 2006.217.07:41:58.67#ibcon#read 4, iclass 33, count 2 2006.217.07:41:58.67#ibcon#about to read 5, iclass 33, count 2 2006.217.07:41:58.67#ibcon#read 5, iclass 33, count 2 2006.217.07:41:58.67#ibcon#about to read 6, iclass 33, count 2 2006.217.07:41:58.67#ibcon#read 6, iclass 33, count 2 2006.217.07:41:58.67#ibcon#end of sib2, iclass 33, count 2 2006.217.07:41:58.67#ibcon#*mode == 0, iclass 33, count 2 2006.217.07:41:58.67#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.217.07:41:58.67#ibcon#[25=AT03-04\r\n] 2006.217.07:41:58.67#ibcon#*before write, iclass 33, count 2 2006.217.07:41:58.67#ibcon#enter sib2, iclass 33, count 2 2006.217.07:41:58.67#ibcon#flushed, iclass 33, count 2 2006.217.07:41:58.67#ibcon#about to write, iclass 33, count 2 2006.217.07:41:58.67#ibcon#wrote, iclass 33, count 2 2006.217.07:41:58.67#ibcon#about to read 3, iclass 33, count 2 2006.217.07:41:58.70#ibcon#read 3, iclass 33, count 2 2006.217.07:41:58.70#ibcon#about to read 4, iclass 33, count 2 2006.217.07:41:58.70#ibcon#read 4, iclass 33, count 2 2006.217.07:41:58.70#ibcon#about to read 5, iclass 33, count 2 2006.217.07:41:58.70#ibcon#read 5, iclass 33, count 2 2006.217.07:41:58.70#ibcon#about to read 6, iclass 33, count 2 2006.217.07:41:58.70#ibcon#read 6, iclass 33, count 2 2006.217.07:41:58.70#ibcon#end of sib2, iclass 33, count 2 2006.217.07:41:58.70#ibcon#*after write, iclass 33, count 2 2006.217.07:41:58.70#ibcon#*before return 0, iclass 33, count 2 2006.217.07:41:58.70#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.217.07:41:58.70#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.217.07:41:58.70#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.217.07:41:58.70#ibcon#ireg 7 cls_cnt 0 2006.217.07:41:58.70#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.217.07:41:58.82#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.217.07:41:58.82#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.217.07:41:58.82#ibcon#enter wrdev, iclass 33, count 0 2006.217.07:41:58.82#ibcon#first serial, iclass 33, count 0 2006.217.07:41:58.82#ibcon#enter sib2, iclass 33, count 0 2006.217.07:41:58.82#ibcon#flushed, iclass 33, count 0 2006.217.07:41:58.82#ibcon#about to write, iclass 33, count 0 2006.217.07:41:58.82#ibcon#wrote, iclass 33, count 0 2006.217.07:41:58.82#ibcon#about to read 3, iclass 33, count 0 2006.217.07:41:58.84#ibcon#read 3, iclass 33, count 0 2006.217.07:41:58.84#ibcon#about to read 4, iclass 33, count 0 2006.217.07:41:58.84#ibcon#read 4, iclass 33, count 0 2006.217.07:41:58.84#ibcon#about to read 5, iclass 33, count 0 2006.217.07:41:58.84#ibcon#read 5, iclass 33, count 0 2006.217.07:41:58.84#ibcon#about to read 6, iclass 33, count 0 2006.217.07:41:58.84#ibcon#read 6, iclass 33, count 0 2006.217.07:41:58.84#ibcon#end of sib2, iclass 33, count 0 2006.217.07:41:58.84#ibcon#*mode == 0, iclass 33, count 0 2006.217.07:41:58.84#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.217.07:41:58.84#ibcon#[25=USB\r\n] 2006.217.07:41:58.84#ibcon#*before write, iclass 33, count 0 2006.217.07:41:58.84#ibcon#enter sib2, iclass 33, count 0 2006.217.07:41:58.84#ibcon#flushed, iclass 33, count 0 2006.217.07:41:58.84#ibcon#about to write, iclass 33, count 0 2006.217.07:41:58.84#ibcon#wrote, iclass 33, count 0 2006.217.07:41:58.84#ibcon#about to read 3, iclass 33, count 0 2006.217.07:41:58.87#ibcon#read 3, iclass 33, count 0 2006.217.07:41:58.87#ibcon#about to read 4, iclass 33, count 0 2006.217.07:41:58.87#ibcon#read 4, iclass 33, count 0 2006.217.07:41:58.87#ibcon#about to read 5, iclass 33, count 0 2006.217.07:41:58.87#ibcon#read 5, iclass 33, count 0 2006.217.07:41:58.87#ibcon#about to read 6, iclass 33, count 0 2006.217.07:41:58.87#ibcon#read 6, iclass 33, count 0 2006.217.07:41:58.87#ibcon#end of sib2, iclass 33, count 0 2006.217.07:41:58.87#ibcon#*after write, iclass 33, count 0 2006.217.07:41:58.87#ibcon#*before return 0, iclass 33, count 0 2006.217.07:41:58.87#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.217.07:41:58.87#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.217.07:41:58.87#ibcon#about to clear, iclass 33 cls_cnt 0 2006.217.07:41:58.87#ibcon#cleared, iclass 33 cls_cnt 0 2006.217.07:41:58.88$vc4f8/valo=4,832.99 2006.217.07:41:58.88#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.217.07:41:58.88#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.217.07:41:58.88#ibcon#ireg 17 cls_cnt 0 2006.217.07:41:58.88#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.217.07:41:58.88#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.217.07:41:58.88#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.217.07:41:58.88#ibcon#enter wrdev, iclass 35, count 0 2006.217.07:41:58.88#ibcon#first serial, iclass 35, count 0 2006.217.07:41:58.88#ibcon#enter sib2, iclass 35, count 0 2006.217.07:41:58.88#ibcon#flushed, iclass 35, count 0 2006.217.07:41:58.88#ibcon#about to write, iclass 35, count 0 2006.217.07:41:58.88#ibcon#wrote, iclass 35, count 0 2006.217.07:41:58.88#ibcon#about to read 3, iclass 35, count 0 2006.217.07:41:58.90#ibcon#read 3, iclass 35, count 0 2006.217.07:41:58.90#ibcon#about to read 4, iclass 35, count 0 2006.217.07:41:58.90#ibcon#read 4, iclass 35, count 0 2006.217.07:41:58.90#ibcon#about to read 5, iclass 35, count 0 2006.217.07:41:58.90#ibcon#read 5, iclass 35, count 0 2006.217.07:41:58.90#ibcon#about to read 6, iclass 35, count 0 2006.217.07:41:58.90#ibcon#read 6, iclass 35, count 0 2006.217.07:41:58.90#ibcon#end of sib2, iclass 35, count 0 2006.217.07:41:58.90#ibcon#*mode == 0, iclass 35, count 0 2006.217.07:41:58.90#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.217.07:41:58.90#ibcon#[26=FRQ=04,832.99\r\n] 2006.217.07:41:58.90#ibcon#*before write, iclass 35, count 0 2006.217.07:41:58.90#ibcon#enter sib2, iclass 35, count 0 2006.217.07:41:58.90#ibcon#flushed, iclass 35, count 0 2006.217.07:41:58.90#ibcon#about to write, iclass 35, count 0 2006.217.07:41:58.90#ibcon#wrote, iclass 35, count 0 2006.217.07:41:58.90#ibcon#about to read 3, iclass 35, count 0 2006.217.07:41:58.94#ibcon#read 3, iclass 35, count 0 2006.217.07:41:58.94#ibcon#about to read 4, iclass 35, count 0 2006.217.07:41:58.94#ibcon#read 4, iclass 35, count 0 2006.217.07:41:58.94#ibcon#about to read 5, iclass 35, count 0 2006.217.07:41:58.94#ibcon#read 5, iclass 35, count 0 2006.217.07:41:58.94#ibcon#about to read 6, iclass 35, count 0 2006.217.07:41:58.94#ibcon#read 6, iclass 35, count 0 2006.217.07:41:58.94#ibcon#end of sib2, iclass 35, count 0 2006.217.07:41:58.94#ibcon#*after write, iclass 35, count 0 2006.217.07:41:58.94#ibcon#*before return 0, iclass 35, count 0 2006.217.07:41:58.94#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.217.07:41:58.94#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.217.07:41:58.94#ibcon#about to clear, iclass 35 cls_cnt 0 2006.217.07:41:58.94#ibcon#cleared, iclass 35 cls_cnt 0 2006.217.07:41:58.95$vc4f8/va=4,4 2006.217.07:41:58.95#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.217.07:41:58.95#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.217.07:41:58.95#ibcon#ireg 11 cls_cnt 2 2006.217.07:41:58.95#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.217.07:41:58.98#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.217.07:41:58.98#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.217.07:41:58.98#ibcon#enter wrdev, iclass 37, count 2 2006.217.07:41:58.98#ibcon#first serial, iclass 37, count 2 2006.217.07:41:58.98#ibcon#enter sib2, iclass 37, count 2 2006.217.07:41:58.98#ibcon#flushed, iclass 37, count 2 2006.217.07:41:58.98#ibcon#about to write, iclass 37, count 2 2006.217.07:41:58.98#ibcon#wrote, iclass 37, count 2 2006.217.07:41:58.98#ibcon#about to read 3, iclass 37, count 2 2006.217.07:41:59.00#ibcon#read 3, iclass 37, count 2 2006.217.07:41:59.00#ibcon#about to read 4, iclass 37, count 2 2006.217.07:41:59.00#ibcon#read 4, iclass 37, count 2 2006.217.07:41:59.00#ibcon#about to read 5, iclass 37, count 2 2006.217.07:41:59.00#ibcon#read 5, iclass 37, count 2 2006.217.07:41:59.00#ibcon#about to read 6, iclass 37, count 2 2006.217.07:41:59.00#ibcon#read 6, iclass 37, count 2 2006.217.07:41:59.00#ibcon#end of sib2, iclass 37, count 2 2006.217.07:41:59.00#ibcon#*mode == 0, iclass 37, count 2 2006.217.07:41:59.00#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.217.07:41:59.00#ibcon#[25=AT04-04\r\n] 2006.217.07:41:59.00#ibcon#*before write, iclass 37, count 2 2006.217.07:41:59.00#ibcon#enter sib2, iclass 37, count 2 2006.217.07:41:59.00#ibcon#flushed, iclass 37, count 2 2006.217.07:41:59.00#ibcon#about to write, iclass 37, count 2 2006.217.07:41:59.00#ibcon#wrote, iclass 37, count 2 2006.217.07:41:59.00#ibcon#about to read 3, iclass 37, count 2 2006.217.07:41:59.03#ibcon#read 3, iclass 37, count 2 2006.217.07:41:59.03#ibcon#about to read 4, iclass 37, count 2 2006.217.07:41:59.03#ibcon#read 4, iclass 37, count 2 2006.217.07:41:59.03#ibcon#about to read 5, iclass 37, count 2 2006.217.07:41:59.03#ibcon#read 5, iclass 37, count 2 2006.217.07:41:59.03#ibcon#about to read 6, iclass 37, count 2 2006.217.07:41:59.03#ibcon#read 6, iclass 37, count 2 2006.217.07:41:59.03#ibcon#end of sib2, iclass 37, count 2 2006.217.07:41:59.03#ibcon#*after write, iclass 37, count 2 2006.217.07:41:59.03#ibcon#*before return 0, iclass 37, count 2 2006.217.07:41:59.03#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.217.07:41:59.03#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.217.07:41:59.03#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.217.07:41:59.03#ibcon#ireg 7 cls_cnt 0 2006.217.07:41:59.03#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.217.07:41:59.15#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.217.07:41:59.15#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.217.07:41:59.15#ibcon#enter wrdev, iclass 37, count 0 2006.217.07:41:59.15#ibcon#first serial, iclass 37, count 0 2006.217.07:41:59.15#ibcon#enter sib2, iclass 37, count 0 2006.217.07:41:59.15#ibcon#flushed, iclass 37, count 0 2006.217.07:41:59.15#ibcon#about to write, iclass 37, count 0 2006.217.07:41:59.15#ibcon#wrote, iclass 37, count 0 2006.217.07:41:59.15#ibcon#about to read 3, iclass 37, count 0 2006.217.07:41:59.17#ibcon#read 3, iclass 37, count 0 2006.217.07:41:59.17#ibcon#about to read 4, iclass 37, count 0 2006.217.07:41:59.17#ibcon#read 4, iclass 37, count 0 2006.217.07:41:59.17#ibcon#about to read 5, iclass 37, count 0 2006.217.07:41:59.17#ibcon#read 5, iclass 37, count 0 2006.217.07:41:59.17#ibcon#about to read 6, iclass 37, count 0 2006.217.07:41:59.17#ibcon#read 6, iclass 37, count 0 2006.217.07:41:59.17#ibcon#end of sib2, iclass 37, count 0 2006.217.07:41:59.17#ibcon#*mode == 0, iclass 37, count 0 2006.217.07:41:59.17#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.217.07:41:59.17#ibcon#[25=USB\r\n] 2006.217.07:41:59.17#ibcon#*before write, iclass 37, count 0 2006.217.07:41:59.17#ibcon#enter sib2, iclass 37, count 0 2006.217.07:41:59.17#ibcon#flushed, iclass 37, count 0 2006.217.07:41:59.17#ibcon#about to write, iclass 37, count 0 2006.217.07:41:59.17#ibcon#wrote, iclass 37, count 0 2006.217.07:41:59.17#ibcon#about to read 3, iclass 37, count 0 2006.217.07:41:59.20#ibcon#read 3, iclass 37, count 0 2006.217.07:41:59.20#ibcon#about to read 4, iclass 37, count 0 2006.217.07:41:59.20#ibcon#read 4, iclass 37, count 0 2006.217.07:41:59.20#ibcon#about to read 5, iclass 37, count 0 2006.217.07:41:59.20#ibcon#read 5, iclass 37, count 0 2006.217.07:41:59.20#ibcon#about to read 6, iclass 37, count 0 2006.217.07:41:59.20#ibcon#read 6, iclass 37, count 0 2006.217.07:41:59.20#ibcon#end of sib2, iclass 37, count 0 2006.217.07:41:59.20#ibcon#*after write, iclass 37, count 0 2006.217.07:41:59.20#ibcon#*before return 0, iclass 37, count 0 2006.217.07:41:59.20#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.217.07:41:59.20#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.217.07:41:59.20#ibcon#about to clear, iclass 37 cls_cnt 0 2006.217.07:41:59.20#ibcon#cleared, iclass 37 cls_cnt 0 2006.217.07:41:59.21$vc4f8/valo=5,652.99 2006.217.07:41:59.21#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.217.07:41:59.21#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.217.07:41:59.21#ibcon#ireg 17 cls_cnt 0 2006.217.07:41:59.21#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.217.07:41:59.21#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.217.07:41:59.21#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.217.07:41:59.21#ibcon#enter wrdev, iclass 39, count 0 2006.217.07:41:59.21#ibcon#first serial, iclass 39, count 0 2006.217.07:41:59.21#ibcon#enter sib2, iclass 39, count 0 2006.217.07:41:59.21#ibcon#flushed, iclass 39, count 0 2006.217.07:41:59.21#ibcon#about to write, iclass 39, count 0 2006.217.07:41:59.21#ibcon#wrote, iclass 39, count 0 2006.217.07:41:59.21#ibcon#about to read 3, iclass 39, count 0 2006.217.07:41:59.22#ibcon#read 3, iclass 39, count 0 2006.217.07:41:59.22#ibcon#about to read 4, iclass 39, count 0 2006.217.07:41:59.22#ibcon#read 4, iclass 39, count 0 2006.217.07:41:59.22#ibcon#about to read 5, iclass 39, count 0 2006.217.07:41:59.22#ibcon#read 5, iclass 39, count 0 2006.217.07:41:59.22#ibcon#about to read 6, iclass 39, count 0 2006.217.07:41:59.22#ibcon#read 6, iclass 39, count 0 2006.217.07:41:59.22#ibcon#end of sib2, iclass 39, count 0 2006.217.07:41:59.22#ibcon#*mode == 0, iclass 39, count 0 2006.217.07:41:59.22#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.217.07:41:59.22#ibcon#[26=FRQ=05,652.99\r\n] 2006.217.07:41:59.22#ibcon#*before write, iclass 39, count 0 2006.217.07:41:59.22#ibcon#enter sib2, iclass 39, count 0 2006.217.07:41:59.22#ibcon#flushed, iclass 39, count 0 2006.217.07:41:59.22#ibcon#about to write, iclass 39, count 0 2006.217.07:41:59.22#ibcon#wrote, iclass 39, count 0 2006.217.07:41:59.22#ibcon#about to read 3, iclass 39, count 0 2006.217.07:41:59.26#ibcon#read 3, iclass 39, count 0 2006.217.07:41:59.26#ibcon#about to read 4, iclass 39, count 0 2006.217.07:41:59.26#ibcon#read 4, iclass 39, count 0 2006.217.07:41:59.26#ibcon#about to read 5, iclass 39, count 0 2006.217.07:41:59.26#ibcon#read 5, iclass 39, count 0 2006.217.07:41:59.26#ibcon#about to read 6, iclass 39, count 0 2006.217.07:41:59.26#ibcon#read 6, iclass 39, count 0 2006.217.07:41:59.26#ibcon#end of sib2, iclass 39, count 0 2006.217.07:41:59.26#ibcon#*after write, iclass 39, count 0 2006.217.07:41:59.26#ibcon#*before return 0, iclass 39, count 0 2006.217.07:41:59.26#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.217.07:41:59.26#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.217.07:41:59.26#ibcon#about to clear, iclass 39 cls_cnt 0 2006.217.07:41:59.26#ibcon#cleared, iclass 39 cls_cnt 0 2006.217.07:41:59.27$vc4f8/va=5,7 2006.217.07:41:59.27#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.217.07:41:59.27#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.217.07:41:59.27#ibcon#ireg 11 cls_cnt 2 2006.217.07:41:59.27#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.217.07:41:59.31#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.217.07:41:59.31#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.217.07:41:59.31#ibcon#enter wrdev, iclass 3, count 2 2006.217.07:41:59.31#ibcon#first serial, iclass 3, count 2 2006.217.07:41:59.31#ibcon#enter sib2, iclass 3, count 2 2006.217.07:41:59.31#ibcon#flushed, iclass 3, count 2 2006.217.07:41:59.31#ibcon#about to write, iclass 3, count 2 2006.217.07:41:59.31#ibcon#wrote, iclass 3, count 2 2006.217.07:41:59.31#ibcon#about to read 3, iclass 3, count 2 2006.217.07:41:59.33#ibcon#read 3, iclass 3, count 2 2006.217.07:41:59.33#ibcon#about to read 4, iclass 3, count 2 2006.217.07:41:59.33#ibcon#read 4, iclass 3, count 2 2006.217.07:41:59.33#ibcon#about to read 5, iclass 3, count 2 2006.217.07:41:59.33#ibcon#read 5, iclass 3, count 2 2006.217.07:41:59.33#ibcon#about to read 6, iclass 3, count 2 2006.217.07:41:59.33#ibcon#read 6, iclass 3, count 2 2006.217.07:41:59.33#ibcon#end of sib2, iclass 3, count 2 2006.217.07:41:59.33#ibcon#*mode == 0, iclass 3, count 2 2006.217.07:41:59.33#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.217.07:41:59.33#ibcon#[25=AT05-07\r\n] 2006.217.07:41:59.33#ibcon#*before write, iclass 3, count 2 2006.217.07:41:59.33#ibcon#enter sib2, iclass 3, count 2 2006.217.07:41:59.33#ibcon#flushed, iclass 3, count 2 2006.217.07:41:59.33#ibcon#about to write, iclass 3, count 2 2006.217.07:41:59.33#ibcon#wrote, iclass 3, count 2 2006.217.07:41:59.33#ibcon#about to read 3, iclass 3, count 2 2006.217.07:41:59.36#ibcon#read 3, iclass 3, count 2 2006.217.07:41:59.36#ibcon#about to read 4, iclass 3, count 2 2006.217.07:41:59.36#ibcon#read 4, iclass 3, count 2 2006.217.07:41:59.36#ibcon#about to read 5, iclass 3, count 2 2006.217.07:41:59.36#ibcon#read 5, iclass 3, count 2 2006.217.07:41:59.36#ibcon#about to read 6, iclass 3, count 2 2006.217.07:41:59.36#ibcon#read 6, iclass 3, count 2 2006.217.07:41:59.36#ibcon#end of sib2, iclass 3, count 2 2006.217.07:41:59.36#ibcon#*after write, iclass 3, count 2 2006.217.07:41:59.36#ibcon#*before return 0, iclass 3, count 2 2006.217.07:41:59.36#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.217.07:41:59.36#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.217.07:41:59.36#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.217.07:41:59.36#ibcon#ireg 7 cls_cnt 0 2006.217.07:41:59.36#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.217.07:41:59.48#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.217.07:41:59.48#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.217.07:41:59.48#ibcon#enter wrdev, iclass 3, count 0 2006.217.07:41:59.48#ibcon#first serial, iclass 3, count 0 2006.217.07:41:59.48#ibcon#enter sib2, iclass 3, count 0 2006.217.07:41:59.48#ibcon#flushed, iclass 3, count 0 2006.217.07:41:59.48#ibcon#about to write, iclass 3, count 0 2006.217.07:41:59.48#ibcon#wrote, iclass 3, count 0 2006.217.07:41:59.48#ibcon#about to read 3, iclass 3, count 0 2006.217.07:41:59.50#ibcon#read 3, iclass 3, count 0 2006.217.07:41:59.50#ibcon#about to read 4, iclass 3, count 0 2006.217.07:41:59.50#ibcon#read 4, iclass 3, count 0 2006.217.07:41:59.50#ibcon#about to read 5, iclass 3, count 0 2006.217.07:41:59.50#ibcon#read 5, iclass 3, count 0 2006.217.07:41:59.50#ibcon#about to read 6, iclass 3, count 0 2006.217.07:41:59.50#ibcon#read 6, iclass 3, count 0 2006.217.07:41:59.50#ibcon#end of sib2, iclass 3, count 0 2006.217.07:41:59.50#ibcon#*mode == 0, iclass 3, count 0 2006.217.07:41:59.50#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.217.07:41:59.50#ibcon#[25=USB\r\n] 2006.217.07:41:59.50#ibcon#*before write, iclass 3, count 0 2006.217.07:41:59.50#ibcon#enter sib2, iclass 3, count 0 2006.217.07:41:59.50#ibcon#flushed, iclass 3, count 0 2006.217.07:41:59.50#ibcon#about to write, iclass 3, count 0 2006.217.07:41:59.50#ibcon#wrote, iclass 3, count 0 2006.217.07:41:59.50#ibcon#about to read 3, iclass 3, count 0 2006.217.07:41:59.53#ibcon#read 3, iclass 3, count 0 2006.217.07:41:59.53#ibcon#about to read 4, iclass 3, count 0 2006.217.07:41:59.53#ibcon#read 4, iclass 3, count 0 2006.217.07:41:59.53#ibcon#about to read 5, iclass 3, count 0 2006.217.07:41:59.53#ibcon#read 5, iclass 3, count 0 2006.217.07:41:59.53#ibcon#about to read 6, iclass 3, count 0 2006.217.07:41:59.53#ibcon#read 6, iclass 3, count 0 2006.217.07:41:59.53#ibcon#end of sib2, iclass 3, count 0 2006.217.07:41:59.53#ibcon#*after write, iclass 3, count 0 2006.217.07:41:59.53#ibcon#*before return 0, iclass 3, count 0 2006.217.07:41:59.53#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.217.07:41:59.53#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.217.07:41:59.53#ibcon#about to clear, iclass 3 cls_cnt 0 2006.217.07:41:59.53#ibcon#cleared, iclass 3 cls_cnt 0 2006.217.07:41:59.54$vc4f8/valo=6,772.99 2006.217.07:41:59.54#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.217.07:41:59.54#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.217.07:41:59.54#ibcon#ireg 17 cls_cnt 0 2006.217.07:41:59.54#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.217.07:41:59.54#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.217.07:41:59.54#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.217.07:41:59.54#ibcon#enter wrdev, iclass 5, count 0 2006.217.07:41:59.54#ibcon#first serial, iclass 5, count 0 2006.217.07:41:59.54#ibcon#enter sib2, iclass 5, count 0 2006.217.07:41:59.54#ibcon#flushed, iclass 5, count 0 2006.217.07:41:59.54#ibcon#about to write, iclass 5, count 0 2006.217.07:41:59.54#ibcon#wrote, iclass 5, count 0 2006.217.07:41:59.54#ibcon#about to read 3, iclass 5, count 0 2006.217.07:41:59.56#ibcon#read 3, iclass 5, count 0 2006.217.07:41:59.56#ibcon#about to read 4, iclass 5, count 0 2006.217.07:41:59.56#ibcon#read 4, iclass 5, count 0 2006.217.07:41:59.56#ibcon#about to read 5, iclass 5, count 0 2006.217.07:41:59.56#ibcon#read 5, iclass 5, count 0 2006.217.07:41:59.56#ibcon#about to read 6, iclass 5, count 0 2006.217.07:41:59.56#ibcon#read 6, iclass 5, count 0 2006.217.07:41:59.56#ibcon#end of sib2, iclass 5, count 0 2006.217.07:41:59.56#ibcon#*mode == 0, iclass 5, count 0 2006.217.07:41:59.56#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.217.07:41:59.56#ibcon#[26=FRQ=06,772.99\r\n] 2006.217.07:41:59.56#ibcon#*before write, iclass 5, count 0 2006.217.07:41:59.56#ibcon#enter sib2, iclass 5, count 0 2006.217.07:41:59.56#ibcon#flushed, iclass 5, count 0 2006.217.07:41:59.56#ibcon#about to write, iclass 5, count 0 2006.217.07:41:59.56#ibcon#wrote, iclass 5, count 0 2006.217.07:41:59.56#ibcon#about to read 3, iclass 5, count 0 2006.217.07:41:59.60#ibcon#read 3, iclass 5, count 0 2006.217.07:41:59.60#ibcon#about to read 4, iclass 5, count 0 2006.217.07:41:59.60#ibcon#read 4, iclass 5, count 0 2006.217.07:41:59.60#ibcon#about to read 5, iclass 5, count 0 2006.217.07:41:59.60#ibcon#read 5, iclass 5, count 0 2006.217.07:41:59.60#ibcon#about to read 6, iclass 5, count 0 2006.217.07:41:59.60#ibcon#read 6, iclass 5, count 0 2006.217.07:41:59.60#ibcon#end of sib2, iclass 5, count 0 2006.217.07:41:59.60#ibcon#*after write, iclass 5, count 0 2006.217.07:41:59.60#ibcon#*before return 0, iclass 5, count 0 2006.217.07:41:59.60#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.217.07:41:59.60#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.217.07:41:59.60#ibcon#about to clear, iclass 5 cls_cnt 0 2006.217.07:41:59.60#ibcon#cleared, iclass 5 cls_cnt 0 2006.217.07:41:59.61$vc4f8/va=6,6 2006.217.07:41:59.61#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.217.07:41:59.61#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.217.07:41:59.61#ibcon#ireg 11 cls_cnt 2 2006.217.07:41:59.61#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.217.07:41:59.64#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.217.07:41:59.64#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.217.07:41:59.64#ibcon#enter wrdev, iclass 7, count 2 2006.217.07:41:59.64#ibcon#first serial, iclass 7, count 2 2006.217.07:41:59.64#ibcon#enter sib2, iclass 7, count 2 2006.217.07:41:59.64#ibcon#flushed, iclass 7, count 2 2006.217.07:41:59.64#ibcon#about to write, iclass 7, count 2 2006.217.07:41:59.64#ibcon#wrote, iclass 7, count 2 2006.217.07:41:59.64#ibcon#about to read 3, iclass 7, count 2 2006.217.07:41:59.67#ibcon#read 3, iclass 7, count 2 2006.217.07:41:59.67#ibcon#about to read 4, iclass 7, count 2 2006.217.07:41:59.67#ibcon#read 4, iclass 7, count 2 2006.217.07:41:59.67#ibcon#about to read 5, iclass 7, count 2 2006.217.07:41:59.67#ibcon#read 5, iclass 7, count 2 2006.217.07:41:59.67#ibcon#about to read 6, iclass 7, count 2 2006.217.07:41:59.67#ibcon#read 6, iclass 7, count 2 2006.217.07:41:59.67#ibcon#end of sib2, iclass 7, count 2 2006.217.07:41:59.67#ibcon#*mode == 0, iclass 7, count 2 2006.217.07:41:59.67#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.217.07:41:59.67#ibcon#[25=AT06-06\r\n] 2006.217.07:41:59.67#ibcon#*before write, iclass 7, count 2 2006.217.07:41:59.67#ibcon#enter sib2, iclass 7, count 2 2006.217.07:41:59.67#ibcon#flushed, iclass 7, count 2 2006.217.07:41:59.67#ibcon#about to write, iclass 7, count 2 2006.217.07:41:59.67#ibcon#wrote, iclass 7, count 2 2006.217.07:41:59.67#ibcon#about to read 3, iclass 7, count 2 2006.217.07:41:59.70#ibcon#read 3, iclass 7, count 2 2006.217.07:41:59.70#ibcon#about to read 4, iclass 7, count 2 2006.217.07:41:59.70#ibcon#read 4, iclass 7, count 2 2006.217.07:41:59.70#ibcon#about to read 5, iclass 7, count 2 2006.217.07:41:59.70#ibcon#read 5, iclass 7, count 2 2006.217.07:41:59.70#ibcon#about to read 6, iclass 7, count 2 2006.217.07:41:59.70#ibcon#read 6, iclass 7, count 2 2006.217.07:41:59.70#ibcon#end of sib2, iclass 7, count 2 2006.217.07:41:59.70#ibcon#*after write, iclass 7, count 2 2006.217.07:41:59.70#ibcon#*before return 0, iclass 7, count 2 2006.217.07:41:59.70#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.217.07:41:59.70#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.217.07:41:59.70#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.217.07:41:59.70#ibcon#ireg 7 cls_cnt 0 2006.217.07:41:59.70#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.217.07:41:59.82#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.217.07:41:59.82#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.217.07:41:59.82#ibcon#enter wrdev, iclass 7, count 0 2006.217.07:41:59.82#ibcon#first serial, iclass 7, count 0 2006.217.07:41:59.82#ibcon#enter sib2, iclass 7, count 0 2006.217.07:41:59.82#ibcon#flushed, iclass 7, count 0 2006.217.07:41:59.82#ibcon#about to write, iclass 7, count 0 2006.217.07:41:59.82#ibcon#wrote, iclass 7, count 0 2006.217.07:41:59.82#ibcon#about to read 3, iclass 7, count 0 2006.217.07:41:59.84#ibcon#read 3, iclass 7, count 0 2006.217.07:41:59.84#ibcon#about to read 4, iclass 7, count 0 2006.217.07:41:59.84#ibcon#read 4, iclass 7, count 0 2006.217.07:41:59.84#ibcon#about to read 5, iclass 7, count 0 2006.217.07:41:59.84#ibcon#read 5, iclass 7, count 0 2006.217.07:41:59.84#ibcon#about to read 6, iclass 7, count 0 2006.217.07:41:59.84#ibcon#read 6, iclass 7, count 0 2006.217.07:41:59.84#ibcon#end of sib2, iclass 7, count 0 2006.217.07:41:59.84#ibcon#*mode == 0, iclass 7, count 0 2006.217.07:41:59.84#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.217.07:41:59.84#ibcon#[25=USB\r\n] 2006.217.07:41:59.84#ibcon#*before write, iclass 7, count 0 2006.217.07:41:59.84#ibcon#enter sib2, iclass 7, count 0 2006.217.07:41:59.84#ibcon#flushed, iclass 7, count 0 2006.217.07:41:59.84#ibcon#about to write, iclass 7, count 0 2006.217.07:41:59.84#ibcon#wrote, iclass 7, count 0 2006.217.07:41:59.84#ibcon#about to read 3, iclass 7, count 0 2006.217.07:41:59.87#ibcon#read 3, iclass 7, count 0 2006.217.07:41:59.87#ibcon#about to read 4, iclass 7, count 0 2006.217.07:41:59.87#ibcon#read 4, iclass 7, count 0 2006.217.07:41:59.87#ibcon#about to read 5, iclass 7, count 0 2006.217.07:41:59.87#ibcon#read 5, iclass 7, count 0 2006.217.07:41:59.87#ibcon#about to read 6, iclass 7, count 0 2006.217.07:41:59.87#ibcon#read 6, iclass 7, count 0 2006.217.07:41:59.87#ibcon#end of sib2, iclass 7, count 0 2006.217.07:41:59.87#ibcon#*after write, iclass 7, count 0 2006.217.07:41:59.87#ibcon#*before return 0, iclass 7, count 0 2006.217.07:41:59.87#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.217.07:41:59.87#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.217.07:41:59.87#ibcon#about to clear, iclass 7 cls_cnt 0 2006.217.07:41:59.87#ibcon#cleared, iclass 7 cls_cnt 0 2006.217.07:41:59.87$vc4f8/valo=7,832.99 2006.217.07:41:59.88#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.217.07:41:59.88#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.217.07:41:59.88#ibcon#ireg 17 cls_cnt 0 2006.217.07:41:59.88#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.217.07:41:59.88#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.217.07:41:59.88#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.217.07:41:59.88#ibcon#enter wrdev, iclass 11, count 0 2006.217.07:41:59.88#ibcon#first serial, iclass 11, count 0 2006.217.07:41:59.88#ibcon#enter sib2, iclass 11, count 0 2006.217.07:41:59.88#ibcon#flushed, iclass 11, count 0 2006.217.07:41:59.88#ibcon#about to write, iclass 11, count 0 2006.217.07:41:59.88#ibcon#wrote, iclass 11, count 0 2006.217.07:41:59.88#ibcon#about to read 3, iclass 11, count 0 2006.217.07:41:59.89#ibcon#read 3, iclass 11, count 0 2006.217.07:41:59.89#ibcon#about to read 4, iclass 11, count 0 2006.217.07:41:59.89#ibcon#read 4, iclass 11, count 0 2006.217.07:41:59.89#ibcon#about to read 5, iclass 11, count 0 2006.217.07:41:59.89#ibcon#read 5, iclass 11, count 0 2006.217.07:41:59.89#ibcon#about to read 6, iclass 11, count 0 2006.217.07:41:59.89#ibcon#read 6, iclass 11, count 0 2006.217.07:41:59.89#ibcon#end of sib2, iclass 11, count 0 2006.217.07:41:59.89#ibcon#*mode == 0, iclass 11, count 0 2006.217.07:41:59.89#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.217.07:41:59.89#ibcon#[26=FRQ=07,832.99\r\n] 2006.217.07:41:59.89#ibcon#*before write, iclass 11, count 0 2006.217.07:41:59.89#ibcon#enter sib2, iclass 11, count 0 2006.217.07:41:59.89#ibcon#flushed, iclass 11, count 0 2006.217.07:41:59.89#ibcon#about to write, iclass 11, count 0 2006.217.07:41:59.89#ibcon#wrote, iclass 11, count 0 2006.217.07:41:59.89#ibcon#about to read 3, iclass 11, count 0 2006.217.07:41:59.93#ibcon#read 3, iclass 11, count 0 2006.217.07:41:59.93#ibcon#about to read 4, iclass 11, count 0 2006.217.07:41:59.93#ibcon#read 4, iclass 11, count 0 2006.217.07:41:59.93#ibcon#about to read 5, iclass 11, count 0 2006.217.07:41:59.93#ibcon#read 5, iclass 11, count 0 2006.217.07:41:59.93#ibcon#about to read 6, iclass 11, count 0 2006.217.07:41:59.93#ibcon#read 6, iclass 11, count 0 2006.217.07:41:59.93#ibcon#end of sib2, iclass 11, count 0 2006.217.07:41:59.93#ibcon#*after write, iclass 11, count 0 2006.217.07:41:59.93#ibcon#*before return 0, iclass 11, count 0 2006.217.07:41:59.93#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.217.07:41:59.93#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.217.07:41:59.93#ibcon#about to clear, iclass 11 cls_cnt 0 2006.217.07:41:59.93#ibcon#cleared, iclass 11 cls_cnt 0 2006.217.07:41:59.93$vc4f8/va=7,6 2006.217.07:41:59.94#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.217.07:41:59.94#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.217.07:41:59.94#ibcon#ireg 11 cls_cnt 2 2006.217.07:41:59.94#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.217.07:41:59.98#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.217.07:41:59.98#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.217.07:41:59.98#ibcon#enter wrdev, iclass 13, count 2 2006.217.07:41:59.98#ibcon#first serial, iclass 13, count 2 2006.217.07:41:59.98#ibcon#enter sib2, iclass 13, count 2 2006.217.07:41:59.98#ibcon#flushed, iclass 13, count 2 2006.217.07:41:59.98#ibcon#about to write, iclass 13, count 2 2006.217.07:41:59.98#ibcon#wrote, iclass 13, count 2 2006.217.07:41:59.98#ibcon#about to read 3, iclass 13, count 2 2006.217.07:42:00.00#ibcon#read 3, iclass 13, count 2 2006.217.07:42:00.00#ibcon#about to read 4, iclass 13, count 2 2006.217.07:42:00.00#ibcon#read 4, iclass 13, count 2 2006.217.07:42:00.00#ibcon#about to read 5, iclass 13, count 2 2006.217.07:42:00.00#ibcon#read 5, iclass 13, count 2 2006.217.07:42:00.00#ibcon#about to read 6, iclass 13, count 2 2006.217.07:42:00.00#ibcon#read 6, iclass 13, count 2 2006.217.07:42:00.00#ibcon#end of sib2, iclass 13, count 2 2006.217.07:42:00.00#ibcon#*mode == 0, iclass 13, count 2 2006.217.07:42:00.00#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.217.07:42:00.00#ibcon#[25=AT07-06\r\n] 2006.217.07:42:00.00#ibcon#*before write, iclass 13, count 2 2006.217.07:42:00.00#ibcon#enter sib2, iclass 13, count 2 2006.217.07:42:00.00#ibcon#flushed, iclass 13, count 2 2006.217.07:42:00.00#ibcon#about to write, iclass 13, count 2 2006.217.07:42:00.00#ibcon#wrote, iclass 13, count 2 2006.217.07:42:00.00#ibcon#about to read 3, iclass 13, count 2 2006.217.07:42:00.03#ibcon#read 3, iclass 13, count 2 2006.217.07:42:00.03#ibcon#about to read 4, iclass 13, count 2 2006.217.07:42:00.03#ibcon#read 4, iclass 13, count 2 2006.217.07:42:00.03#ibcon#about to read 5, iclass 13, count 2 2006.217.07:42:00.03#ibcon#read 5, iclass 13, count 2 2006.217.07:42:00.03#ibcon#about to read 6, iclass 13, count 2 2006.217.07:42:00.03#ibcon#read 6, iclass 13, count 2 2006.217.07:42:00.03#ibcon#end of sib2, iclass 13, count 2 2006.217.07:42:00.03#ibcon#*after write, iclass 13, count 2 2006.217.07:42:00.03#ibcon#*before return 0, iclass 13, count 2 2006.217.07:42:00.03#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.217.07:42:00.03#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.217.07:42:00.03#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.217.07:42:00.03#ibcon#ireg 7 cls_cnt 0 2006.217.07:42:00.03#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.217.07:42:00.15#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.217.07:42:00.15#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.217.07:42:00.15#ibcon#enter wrdev, iclass 13, count 0 2006.217.07:42:00.15#ibcon#first serial, iclass 13, count 0 2006.217.07:42:00.15#ibcon#enter sib2, iclass 13, count 0 2006.217.07:42:00.15#ibcon#flushed, iclass 13, count 0 2006.217.07:42:00.15#ibcon#about to write, iclass 13, count 0 2006.217.07:42:00.15#ibcon#wrote, iclass 13, count 0 2006.217.07:42:00.15#ibcon#about to read 3, iclass 13, count 0 2006.217.07:42:00.17#ibcon#read 3, iclass 13, count 0 2006.217.07:42:00.17#ibcon#about to read 4, iclass 13, count 0 2006.217.07:42:00.17#ibcon#read 4, iclass 13, count 0 2006.217.07:42:00.17#ibcon#about to read 5, iclass 13, count 0 2006.217.07:42:00.17#ibcon#read 5, iclass 13, count 0 2006.217.07:42:00.17#ibcon#about to read 6, iclass 13, count 0 2006.217.07:42:00.17#ibcon#read 6, iclass 13, count 0 2006.217.07:42:00.17#ibcon#end of sib2, iclass 13, count 0 2006.217.07:42:00.17#ibcon#*mode == 0, iclass 13, count 0 2006.217.07:42:00.17#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.217.07:42:00.17#ibcon#[25=USB\r\n] 2006.217.07:42:00.17#ibcon#*before write, iclass 13, count 0 2006.217.07:42:00.17#ibcon#enter sib2, iclass 13, count 0 2006.217.07:42:00.17#ibcon#flushed, iclass 13, count 0 2006.217.07:42:00.17#ibcon#about to write, iclass 13, count 0 2006.217.07:42:00.17#ibcon#wrote, iclass 13, count 0 2006.217.07:42:00.17#ibcon#about to read 3, iclass 13, count 0 2006.217.07:42:00.20#ibcon#read 3, iclass 13, count 0 2006.217.07:42:00.20#ibcon#about to read 4, iclass 13, count 0 2006.217.07:42:00.20#ibcon#read 4, iclass 13, count 0 2006.217.07:42:00.20#ibcon#about to read 5, iclass 13, count 0 2006.217.07:42:00.20#ibcon#read 5, iclass 13, count 0 2006.217.07:42:00.20#ibcon#about to read 6, iclass 13, count 0 2006.217.07:42:00.20#ibcon#read 6, iclass 13, count 0 2006.217.07:42:00.20#ibcon#end of sib2, iclass 13, count 0 2006.217.07:42:00.20#ibcon#*after write, iclass 13, count 0 2006.217.07:42:00.20#ibcon#*before return 0, iclass 13, count 0 2006.217.07:42:00.20#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.217.07:42:00.20#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.217.07:42:00.20#ibcon#about to clear, iclass 13 cls_cnt 0 2006.217.07:42:00.20#ibcon#cleared, iclass 13 cls_cnt 0 2006.217.07:42:00.20$vc4f8/valo=8,852.99 2006.217.07:42:00.21#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.217.07:42:00.21#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.217.07:42:00.21#ibcon#ireg 17 cls_cnt 0 2006.217.07:42:00.21#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.217.07:42:00.21#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.217.07:42:00.21#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.217.07:42:00.21#ibcon#enter wrdev, iclass 15, count 0 2006.217.07:42:00.21#ibcon#first serial, iclass 15, count 0 2006.217.07:42:00.21#ibcon#enter sib2, iclass 15, count 0 2006.217.07:42:00.21#ibcon#flushed, iclass 15, count 0 2006.217.07:42:00.21#ibcon#about to write, iclass 15, count 0 2006.217.07:42:00.21#ibcon#wrote, iclass 15, count 0 2006.217.07:42:00.21#ibcon#about to read 3, iclass 15, count 0 2006.217.07:42:00.22#ibcon#read 3, iclass 15, count 0 2006.217.07:42:00.22#ibcon#about to read 4, iclass 15, count 0 2006.217.07:42:00.22#ibcon#read 4, iclass 15, count 0 2006.217.07:42:00.22#ibcon#about to read 5, iclass 15, count 0 2006.217.07:42:00.22#ibcon#read 5, iclass 15, count 0 2006.217.07:42:00.22#ibcon#about to read 6, iclass 15, count 0 2006.217.07:42:00.22#ibcon#read 6, iclass 15, count 0 2006.217.07:42:00.22#ibcon#end of sib2, iclass 15, count 0 2006.217.07:42:00.22#ibcon#*mode == 0, iclass 15, count 0 2006.217.07:42:00.22#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.217.07:42:00.22#ibcon#[26=FRQ=08,852.99\r\n] 2006.217.07:42:00.23#ibcon#*before write, iclass 15, count 0 2006.217.07:42:00.23#ibcon#enter sib2, iclass 15, count 0 2006.217.07:42:00.23#ibcon#flushed, iclass 15, count 0 2006.217.07:42:00.23#ibcon#about to write, iclass 15, count 0 2006.217.07:42:00.23#ibcon#wrote, iclass 15, count 0 2006.217.07:42:00.23#ibcon#about to read 3, iclass 15, count 0 2006.217.07:42:00.26#ibcon#read 3, iclass 15, count 0 2006.217.07:42:00.26#ibcon#about to read 4, iclass 15, count 0 2006.217.07:42:00.26#ibcon#read 4, iclass 15, count 0 2006.217.07:42:00.26#ibcon#about to read 5, iclass 15, count 0 2006.217.07:42:00.26#ibcon#read 5, iclass 15, count 0 2006.217.07:42:00.26#ibcon#about to read 6, iclass 15, count 0 2006.217.07:42:00.26#ibcon#read 6, iclass 15, count 0 2006.217.07:42:00.26#ibcon#end of sib2, iclass 15, count 0 2006.217.07:42:00.26#ibcon#*after write, iclass 15, count 0 2006.217.07:42:00.26#ibcon#*before return 0, iclass 15, count 0 2006.217.07:42:00.26#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.217.07:42:00.26#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.217.07:42:00.26#ibcon#about to clear, iclass 15 cls_cnt 0 2006.217.07:42:00.26#ibcon#cleared, iclass 15 cls_cnt 0 2006.217.07:42:00.26$vc4f8/va=8,7 2006.217.07:42:00.27#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.217.07:42:00.27#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.217.07:42:00.27#ibcon#ireg 11 cls_cnt 2 2006.217.07:42:00.27#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.217.07:42:00.31#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.217.07:42:00.31#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.217.07:42:00.31#ibcon#enter wrdev, iclass 17, count 2 2006.217.07:42:00.31#ibcon#first serial, iclass 17, count 2 2006.217.07:42:00.31#ibcon#enter sib2, iclass 17, count 2 2006.217.07:42:00.31#ibcon#flushed, iclass 17, count 2 2006.217.07:42:00.31#ibcon#about to write, iclass 17, count 2 2006.217.07:42:00.31#ibcon#wrote, iclass 17, count 2 2006.217.07:42:00.31#ibcon#about to read 3, iclass 17, count 2 2006.217.07:42:00.33#ibcon#read 3, iclass 17, count 2 2006.217.07:42:00.33#ibcon#about to read 4, iclass 17, count 2 2006.217.07:42:00.33#ibcon#read 4, iclass 17, count 2 2006.217.07:42:00.33#ibcon#about to read 5, iclass 17, count 2 2006.217.07:42:00.33#ibcon#read 5, iclass 17, count 2 2006.217.07:42:00.33#ibcon#about to read 6, iclass 17, count 2 2006.217.07:42:00.33#ibcon#read 6, iclass 17, count 2 2006.217.07:42:00.33#ibcon#end of sib2, iclass 17, count 2 2006.217.07:42:00.33#ibcon#*mode == 0, iclass 17, count 2 2006.217.07:42:00.33#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.217.07:42:00.33#ibcon#[25=AT08-07\r\n] 2006.217.07:42:00.33#ibcon#*before write, iclass 17, count 2 2006.217.07:42:00.33#ibcon#enter sib2, iclass 17, count 2 2006.217.07:42:00.33#ibcon#flushed, iclass 17, count 2 2006.217.07:42:00.33#ibcon#about to write, iclass 17, count 2 2006.217.07:42:00.33#ibcon#wrote, iclass 17, count 2 2006.217.07:42:00.33#ibcon#about to read 3, iclass 17, count 2 2006.217.07:42:00.36#ibcon#read 3, iclass 17, count 2 2006.217.07:42:00.36#ibcon#about to read 4, iclass 17, count 2 2006.217.07:42:00.36#ibcon#read 4, iclass 17, count 2 2006.217.07:42:00.36#ibcon#about to read 5, iclass 17, count 2 2006.217.07:42:00.36#ibcon#read 5, iclass 17, count 2 2006.217.07:42:00.36#ibcon#about to read 6, iclass 17, count 2 2006.217.07:42:00.36#ibcon#read 6, iclass 17, count 2 2006.217.07:42:00.36#ibcon#end of sib2, iclass 17, count 2 2006.217.07:42:00.36#ibcon#*after write, iclass 17, count 2 2006.217.07:42:00.36#ibcon#*before return 0, iclass 17, count 2 2006.217.07:42:00.36#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.217.07:42:00.36#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.217.07:42:00.36#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.217.07:42:00.36#ibcon#ireg 7 cls_cnt 0 2006.217.07:42:00.36#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.217.07:42:00.48#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.217.07:42:00.48#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.217.07:42:00.48#ibcon#enter wrdev, iclass 17, count 0 2006.217.07:42:00.48#ibcon#first serial, iclass 17, count 0 2006.217.07:42:00.48#ibcon#enter sib2, iclass 17, count 0 2006.217.07:42:00.48#ibcon#flushed, iclass 17, count 0 2006.217.07:42:00.48#ibcon#about to write, iclass 17, count 0 2006.217.07:42:00.48#ibcon#wrote, iclass 17, count 0 2006.217.07:42:00.48#ibcon#about to read 3, iclass 17, count 0 2006.217.07:42:00.50#ibcon#read 3, iclass 17, count 0 2006.217.07:42:00.50#ibcon#about to read 4, iclass 17, count 0 2006.217.07:42:00.50#ibcon#read 4, iclass 17, count 0 2006.217.07:42:00.50#ibcon#about to read 5, iclass 17, count 0 2006.217.07:42:00.50#ibcon#read 5, iclass 17, count 0 2006.217.07:42:00.50#ibcon#about to read 6, iclass 17, count 0 2006.217.07:42:00.50#ibcon#read 6, iclass 17, count 0 2006.217.07:42:00.50#ibcon#end of sib2, iclass 17, count 0 2006.217.07:42:00.50#ibcon#*mode == 0, iclass 17, count 0 2006.217.07:42:00.50#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.217.07:42:00.50#ibcon#[25=USB\r\n] 2006.217.07:42:00.50#ibcon#*before write, iclass 17, count 0 2006.217.07:42:00.50#ibcon#enter sib2, iclass 17, count 0 2006.217.07:42:00.50#ibcon#flushed, iclass 17, count 0 2006.217.07:42:00.50#ibcon#about to write, iclass 17, count 0 2006.217.07:42:00.50#ibcon#wrote, iclass 17, count 0 2006.217.07:42:00.50#ibcon#about to read 3, iclass 17, count 0 2006.217.07:42:00.53#ibcon#read 3, iclass 17, count 0 2006.217.07:42:00.53#ibcon#about to read 4, iclass 17, count 0 2006.217.07:42:00.53#ibcon#read 4, iclass 17, count 0 2006.217.07:42:00.53#ibcon#about to read 5, iclass 17, count 0 2006.217.07:42:00.53#ibcon#read 5, iclass 17, count 0 2006.217.07:42:00.53#ibcon#about to read 6, iclass 17, count 0 2006.217.07:42:00.53#ibcon#read 6, iclass 17, count 0 2006.217.07:42:00.53#ibcon#end of sib2, iclass 17, count 0 2006.217.07:42:00.53#ibcon#*after write, iclass 17, count 0 2006.217.07:42:00.53#ibcon#*before return 0, iclass 17, count 0 2006.217.07:42:00.53#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.217.07:42:00.53#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.217.07:42:00.53#ibcon#about to clear, iclass 17 cls_cnt 0 2006.217.07:42:00.53#ibcon#cleared, iclass 17 cls_cnt 0 2006.217.07:42:00.53$vc4f8/vblo=1,632.99 2006.217.07:42:00.54#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.217.07:42:00.54#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.217.07:42:00.54#ibcon#ireg 17 cls_cnt 0 2006.217.07:42:00.54#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.217.07:42:00.54#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.217.07:42:00.54#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.217.07:42:00.54#ibcon#enter wrdev, iclass 19, count 0 2006.217.07:42:00.54#ibcon#first serial, iclass 19, count 0 2006.217.07:42:00.54#ibcon#enter sib2, iclass 19, count 0 2006.217.07:42:00.54#ibcon#flushed, iclass 19, count 0 2006.217.07:42:00.54#ibcon#about to write, iclass 19, count 0 2006.217.07:42:00.54#ibcon#wrote, iclass 19, count 0 2006.217.07:42:00.54#ibcon#about to read 3, iclass 19, count 0 2006.217.07:42:00.55#ibcon#read 3, iclass 19, count 0 2006.217.07:42:00.55#ibcon#about to read 4, iclass 19, count 0 2006.217.07:42:00.55#ibcon#read 4, iclass 19, count 0 2006.217.07:42:00.55#ibcon#about to read 5, iclass 19, count 0 2006.217.07:42:00.55#ibcon#read 5, iclass 19, count 0 2006.217.07:42:00.55#ibcon#about to read 6, iclass 19, count 0 2006.217.07:42:00.55#ibcon#read 6, iclass 19, count 0 2006.217.07:42:00.55#ibcon#end of sib2, iclass 19, count 0 2006.217.07:42:00.55#ibcon#*mode == 0, iclass 19, count 0 2006.217.07:42:00.55#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.217.07:42:00.55#ibcon#[28=FRQ=01,632.99\r\n] 2006.217.07:42:00.55#ibcon#*before write, iclass 19, count 0 2006.217.07:42:00.55#ibcon#enter sib2, iclass 19, count 0 2006.217.07:42:00.55#ibcon#flushed, iclass 19, count 0 2006.217.07:42:00.55#ibcon#about to write, iclass 19, count 0 2006.217.07:42:00.55#ibcon#wrote, iclass 19, count 0 2006.217.07:42:00.55#ibcon#about to read 3, iclass 19, count 0 2006.217.07:42:00.59#ibcon#read 3, iclass 19, count 0 2006.217.07:42:00.59#ibcon#about to read 4, iclass 19, count 0 2006.217.07:42:00.59#ibcon#read 4, iclass 19, count 0 2006.217.07:42:00.59#ibcon#about to read 5, iclass 19, count 0 2006.217.07:42:00.59#ibcon#read 5, iclass 19, count 0 2006.217.07:42:00.59#ibcon#about to read 6, iclass 19, count 0 2006.217.07:42:00.59#ibcon#read 6, iclass 19, count 0 2006.217.07:42:00.59#ibcon#end of sib2, iclass 19, count 0 2006.217.07:42:00.59#ibcon#*after write, iclass 19, count 0 2006.217.07:42:00.59#ibcon#*before return 0, iclass 19, count 0 2006.217.07:42:00.59#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.217.07:42:00.59#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.217.07:42:00.59#ibcon#about to clear, iclass 19 cls_cnt 0 2006.217.07:42:00.59#ibcon#cleared, iclass 19 cls_cnt 0 2006.217.07:42:00.59$vc4f8/vb=1,4 2006.217.07:42:00.60#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.217.07:42:00.60#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.217.07:42:00.60#ibcon#ireg 11 cls_cnt 2 2006.217.07:42:00.60#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.217.07:42:00.60#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.217.07:42:00.60#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.217.07:42:00.60#ibcon#enter wrdev, iclass 21, count 2 2006.217.07:42:00.60#ibcon#first serial, iclass 21, count 2 2006.217.07:42:00.60#ibcon#enter sib2, iclass 21, count 2 2006.217.07:42:00.60#ibcon#flushed, iclass 21, count 2 2006.217.07:42:00.60#ibcon#about to write, iclass 21, count 2 2006.217.07:42:00.60#ibcon#wrote, iclass 21, count 2 2006.217.07:42:00.60#ibcon#about to read 3, iclass 21, count 2 2006.217.07:42:00.61#ibcon#read 3, iclass 21, count 2 2006.217.07:42:00.61#ibcon#about to read 4, iclass 21, count 2 2006.217.07:42:00.61#ibcon#read 4, iclass 21, count 2 2006.217.07:42:00.61#ibcon#about to read 5, iclass 21, count 2 2006.217.07:42:00.61#ibcon#read 5, iclass 21, count 2 2006.217.07:42:00.61#ibcon#about to read 6, iclass 21, count 2 2006.217.07:42:00.61#ibcon#read 6, iclass 21, count 2 2006.217.07:42:00.61#ibcon#end of sib2, iclass 21, count 2 2006.217.07:42:00.61#ibcon#*mode == 0, iclass 21, count 2 2006.217.07:42:00.61#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.217.07:42:00.61#ibcon#[27=AT01-04\r\n] 2006.217.07:42:00.61#ibcon#*before write, iclass 21, count 2 2006.217.07:42:00.61#ibcon#enter sib2, iclass 21, count 2 2006.217.07:42:00.61#ibcon#flushed, iclass 21, count 2 2006.217.07:42:00.61#ibcon#about to write, iclass 21, count 2 2006.217.07:42:00.61#ibcon#wrote, iclass 21, count 2 2006.217.07:42:00.61#ibcon#about to read 3, iclass 21, count 2 2006.217.07:42:00.64#ibcon#read 3, iclass 21, count 2 2006.217.07:42:00.64#ibcon#about to read 4, iclass 21, count 2 2006.217.07:42:00.64#ibcon#read 4, iclass 21, count 2 2006.217.07:42:00.64#ibcon#about to read 5, iclass 21, count 2 2006.217.07:42:00.64#ibcon#read 5, iclass 21, count 2 2006.217.07:42:00.64#ibcon#about to read 6, iclass 21, count 2 2006.217.07:42:00.64#ibcon#read 6, iclass 21, count 2 2006.217.07:42:00.64#ibcon#end of sib2, iclass 21, count 2 2006.217.07:42:00.64#ibcon#*after write, iclass 21, count 2 2006.217.07:42:00.64#ibcon#*before return 0, iclass 21, count 2 2006.217.07:42:00.64#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.217.07:42:00.64#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.217.07:42:00.64#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.217.07:42:00.64#ibcon#ireg 7 cls_cnt 0 2006.217.07:42:00.64#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.217.07:42:00.76#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.217.07:42:00.76#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.217.07:42:00.76#ibcon#enter wrdev, iclass 21, count 0 2006.217.07:42:00.76#ibcon#first serial, iclass 21, count 0 2006.217.07:42:00.76#ibcon#enter sib2, iclass 21, count 0 2006.217.07:42:00.76#ibcon#flushed, iclass 21, count 0 2006.217.07:42:00.76#ibcon#about to write, iclass 21, count 0 2006.217.07:42:00.76#ibcon#wrote, iclass 21, count 0 2006.217.07:42:00.76#ibcon#about to read 3, iclass 21, count 0 2006.217.07:42:00.78#ibcon#read 3, iclass 21, count 0 2006.217.07:42:00.78#ibcon#about to read 4, iclass 21, count 0 2006.217.07:42:00.78#ibcon#read 4, iclass 21, count 0 2006.217.07:42:00.78#ibcon#about to read 5, iclass 21, count 0 2006.217.07:42:00.78#ibcon#read 5, iclass 21, count 0 2006.217.07:42:00.78#ibcon#about to read 6, iclass 21, count 0 2006.217.07:42:00.78#ibcon#read 6, iclass 21, count 0 2006.217.07:42:00.78#ibcon#end of sib2, iclass 21, count 0 2006.217.07:42:00.78#ibcon#*mode == 0, iclass 21, count 0 2006.217.07:42:00.78#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.217.07:42:00.78#ibcon#[27=USB\r\n] 2006.217.07:42:00.78#ibcon#*before write, iclass 21, count 0 2006.217.07:42:00.78#ibcon#enter sib2, iclass 21, count 0 2006.217.07:42:00.78#ibcon#flushed, iclass 21, count 0 2006.217.07:42:00.78#ibcon#about to write, iclass 21, count 0 2006.217.07:42:00.78#ibcon#wrote, iclass 21, count 0 2006.217.07:42:00.78#ibcon#about to read 3, iclass 21, count 0 2006.217.07:42:00.81#ibcon#read 3, iclass 21, count 0 2006.217.07:42:00.81#ibcon#about to read 4, iclass 21, count 0 2006.217.07:42:00.81#ibcon#read 4, iclass 21, count 0 2006.217.07:42:00.81#ibcon#about to read 5, iclass 21, count 0 2006.217.07:42:00.81#ibcon#read 5, iclass 21, count 0 2006.217.07:42:00.81#ibcon#about to read 6, iclass 21, count 0 2006.217.07:42:00.81#ibcon#read 6, iclass 21, count 0 2006.217.07:42:00.81#ibcon#end of sib2, iclass 21, count 0 2006.217.07:42:00.81#ibcon#*after write, iclass 21, count 0 2006.217.07:42:00.81#ibcon#*before return 0, iclass 21, count 0 2006.217.07:42:00.81#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.217.07:42:00.81#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.217.07:42:00.81#ibcon#about to clear, iclass 21 cls_cnt 0 2006.217.07:42:00.81#ibcon#cleared, iclass 21 cls_cnt 0 2006.217.07:42:00.81$vc4f8/vblo=2,640.99 2006.217.07:42:00.82#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.217.07:42:00.82#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.217.07:42:00.82#ibcon#ireg 17 cls_cnt 0 2006.217.07:42:00.82#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.217.07:42:00.82#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.217.07:42:00.82#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.217.07:42:00.82#ibcon#enter wrdev, iclass 23, count 0 2006.217.07:42:00.82#ibcon#first serial, iclass 23, count 0 2006.217.07:42:00.82#ibcon#enter sib2, iclass 23, count 0 2006.217.07:42:00.82#ibcon#flushed, iclass 23, count 0 2006.217.07:42:00.82#ibcon#about to write, iclass 23, count 0 2006.217.07:42:00.82#ibcon#wrote, iclass 23, count 0 2006.217.07:42:00.82#ibcon#about to read 3, iclass 23, count 0 2006.217.07:42:00.83#ibcon#read 3, iclass 23, count 0 2006.217.07:42:00.83#ibcon#about to read 4, iclass 23, count 0 2006.217.07:42:00.83#ibcon#read 4, iclass 23, count 0 2006.217.07:42:00.83#ibcon#about to read 5, iclass 23, count 0 2006.217.07:42:00.83#ibcon#read 5, iclass 23, count 0 2006.217.07:42:00.83#ibcon#about to read 6, iclass 23, count 0 2006.217.07:42:00.83#ibcon#read 6, iclass 23, count 0 2006.217.07:42:00.83#ibcon#end of sib2, iclass 23, count 0 2006.217.07:42:00.83#ibcon#*mode == 0, iclass 23, count 0 2006.217.07:42:00.83#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.217.07:42:00.83#ibcon#[28=FRQ=02,640.99\r\n] 2006.217.07:42:00.83#ibcon#*before write, iclass 23, count 0 2006.217.07:42:00.83#ibcon#enter sib2, iclass 23, count 0 2006.217.07:42:00.83#ibcon#flushed, iclass 23, count 0 2006.217.07:42:00.83#ibcon#about to write, iclass 23, count 0 2006.217.07:42:00.83#ibcon#wrote, iclass 23, count 0 2006.217.07:42:00.83#ibcon#about to read 3, iclass 23, count 0 2006.217.07:42:00.87#ibcon#read 3, iclass 23, count 0 2006.217.07:42:00.87#ibcon#about to read 4, iclass 23, count 0 2006.217.07:42:00.87#ibcon#read 4, iclass 23, count 0 2006.217.07:42:00.87#ibcon#about to read 5, iclass 23, count 0 2006.217.07:42:00.87#ibcon#read 5, iclass 23, count 0 2006.217.07:42:00.87#ibcon#about to read 6, iclass 23, count 0 2006.217.07:42:00.87#ibcon#read 6, iclass 23, count 0 2006.217.07:42:00.87#ibcon#end of sib2, iclass 23, count 0 2006.217.07:42:00.87#ibcon#*after write, iclass 23, count 0 2006.217.07:42:00.87#ibcon#*before return 0, iclass 23, count 0 2006.217.07:42:00.87#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.217.07:42:00.87#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.217.07:42:00.87#ibcon#about to clear, iclass 23 cls_cnt 0 2006.217.07:42:00.87#ibcon#cleared, iclass 23 cls_cnt 0 2006.217.07:42:00.87$vc4f8/vb=2,4 2006.217.07:42:00.88#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.217.07:42:00.88#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.217.07:42:00.88#ibcon#ireg 11 cls_cnt 2 2006.217.07:42:00.88#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.217.07:42:00.92#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.217.07:42:00.92#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.217.07:42:00.92#ibcon#enter wrdev, iclass 25, count 2 2006.217.07:42:00.92#ibcon#first serial, iclass 25, count 2 2006.217.07:42:00.92#ibcon#enter sib2, iclass 25, count 2 2006.217.07:42:00.92#ibcon#flushed, iclass 25, count 2 2006.217.07:42:00.92#ibcon#about to write, iclass 25, count 2 2006.217.07:42:00.92#ibcon#wrote, iclass 25, count 2 2006.217.07:42:00.92#ibcon#about to read 3, iclass 25, count 2 2006.217.07:42:00.94#ibcon#read 3, iclass 25, count 2 2006.217.07:42:00.94#ibcon#about to read 4, iclass 25, count 2 2006.217.07:42:00.94#ibcon#read 4, iclass 25, count 2 2006.217.07:42:00.94#ibcon#about to read 5, iclass 25, count 2 2006.217.07:42:00.94#ibcon#read 5, iclass 25, count 2 2006.217.07:42:00.94#ibcon#about to read 6, iclass 25, count 2 2006.217.07:42:00.94#ibcon#read 6, iclass 25, count 2 2006.217.07:42:00.94#ibcon#end of sib2, iclass 25, count 2 2006.217.07:42:00.94#ibcon#*mode == 0, iclass 25, count 2 2006.217.07:42:00.94#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.217.07:42:00.94#ibcon#[27=AT02-04\r\n] 2006.217.07:42:00.94#ibcon#*before write, iclass 25, count 2 2006.217.07:42:00.94#ibcon#enter sib2, iclass 25, count 2 2006.217.07:42:00.94#ibcon#flushed, iclass 25, count 2 2006.217.07:42:00.94#ibcon#about to write, iclass 25, count 2 2006.217.07:42:00.94#ibcon#wrote, iclass 25, count 2 2006.217.07:42:00.94#ibcon#about to read 3, iclass 25, count 2 2006.217.07:42:00.97#ibcon#read 3, iclass 25, count 2 2006.217.07:42:00.97#ibcon#about to read 4, iclass 25, count 2 2006.217.07:42:00.97#ibcon#read 4, iclass 25, count 2 2006.217.07:42:00.97#ibcon#about to read 5, iclass 25, count 2 2006.217.07:42:00.97#ibcon#read 5, iclass 25, count 2 2006.217.07:42:00.97#ibcon#about to read 6, iclass 25, count 2 2006.217.07:42:00.97#ibcon#read 6, iclass 25, count 2 2006.217.07:42:00.97#ibcon#end of sib2, iclass 25, count 2 2006.217.07:42:00.97#ibcon#*after write, iclass 25, count 2 2006.217.07:42:00.97#ibcon#*before return 0, iclass 25, count 2 2006.217.07:42:00.97#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.217.07:42:00.97#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.217.07:42:00.97#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.217.07:42:00.97#ibcon#ireg 7 cls_cnt 0 2006.217.07:42:00.97#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.217.07:42:01.09#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.217.07:42:01.09#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.217.07:42:01.09#ibcon#enter wrdev, iclass 25, count 0 2006.217.07:42:01.09#ibcon#first serial, iclass 25, count 0 2006.217.07:42:01.09#ibcon#enter sib2, iclass 25, count 0 2006.217.07:42:01.09#ibcon#flushed, iclass 25, count 0 2006.217.07:42:01.09#ibcon#about to write, iclass 25, count 0 2006.217.07:42:01.09#ibcon#wrote, iclass 25, count 0 2006.217.07:42:01.09#ibcon#about to read 3, iclass 25, count 0 2006.217.07:42:01.11#ibcon#read 3, iclass 25, count 0 2006.217.07:42:01.11#ibcon#about to read 4, iclass 25, count 0 2006.217.07:42:01.11#ibcon#read 4, iclass 25, count 0 2006.217.07:42:01.11#ibcon#about to read 5, iclass 25, count 0 2006.217.07:42:01.11#ibcon#read 5, iclass 25, count 0 2006.217.07:42:01.11#ibcon#about to read 6, iclass 25, count 0 2006.217.07:42:01.11#ibcon#read 6, iclass 25, count 0 2006.217.07:42:01.11#ibcon#end of sib2, iclass 25, count 0 2006.217.07:42:01.11#ibcon#*mode == 0, iclass 25, count 0 2006.217.07:42:01.11#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.217.07:42:01.11#ibcon#[27=USB\r\n] 2006.217.07:42:01.11#ibcon#*before write, iclass 25, count 0 2006.217.07:42:01.11#ibcon#enter sib2, iclass 25, count 0 2006.217.07:42:01.11#ibcon#flushed, iclass 25, count 0 2006.217.07:42:01.11#ibcon#about to write, iclass 25, count 0 2006.217.07:42:01.11#ibcon#wrote, iclass 25, count 0 2006.217.07:42:01.11#ibcon#about to read 3, iclass 25, count 0 2006.217.07:42:01.14#ibcon#read 3, iclass 25, count 0 2006.217.07:42:01.14#ibcon#about to read 4, iclass 25, count 0 2006.217.07:42:01.14#ibcon#read 4, iclass 25, count 0 2006.217.07:42:01.14#ibcon#about to read 5, iclass 25, count 0 2006.217.07:42:01.14#ibcon#read 5, iclass 25, count 0 2006.217.07:42:01.14#ibcon#about to read 6, iclass 25, count 0 2006.217.07:42:01.14#ibcon#read 6, iclass 25, count 0 2006.217.07:42:01.14#ibcon#end of sib2, iclass 25, count 0 2006.217.07:42:01.14#ibcon#*after write, iclass 25, count 0 2006.217.07:42:01.14#ibcon#*before return 0, iclass 25, count 0 2006.217.07:42:01.14#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.217.07:42:01.14#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.217.07:42:01.14#ibcon#about to clear, iclass 25 cls_cnt 0 2006.217.07:42:01.14#ibcon#cleared, iclass 25 cls_cnt 0 2006.217.07:42:01.14$vc4f8/vblo=3,656.99 2006.217.07:42:01.15#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.217.07:42:01.15#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.217.07:42:01.15#ibcon#ireg 17 cls_cnt 0 2006.217.07:42:01.15#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.217.07:42:01.15#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.217.07:42:01.15#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.217.07:42:01.15#ibcon#enter wrdev, iclass 27, count 0 2006.217.07:42:01.15#ibcon#first serial, iclass 27, count 0 2006.217.07:42:01.15#ibcon#enter sib2, iclass 27, count 0 2006.217.07:42:01.15#ibcon#flushed, iclass 27, count 0 2006.217.07:42:01.15#ibcon#about to write, iclass 27, count 0 2006.217.07:42:01.15#ibcon#wrote, iclass 27, count 0 2006.217.07:42:01.15#ibcon#about to read 3, iclass 27, count 0 2006.217.07:42:01.16#ibcon#read 3, iclass 27, count 0 2006.217.07:42:01.16#ibcon#about to read 4, iclass 27, count 0 2006.217.07:42:01.16#ibcon#read 4, iclass 27, count 0 2006.217.07:42:01.16#ibcon#about to read 5, iclass 27, count 0 2006.217.07:42:01.16#ibcon#read 5, iclass 27, count 0 2006.217.07:42:01.16#ibcon#about to read 6, iclass 27, count 0 2006.217.07:42:01.16#ibcon#read 6, iclass 27, count 0 2006.217.07:42:01.16#ibcon#end of sib2, iclass 27, count 0 2006.217.07:42:01.16#ibcon#*mode == 0, iclass 27, count 0 2006.217.07:42:01.16#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.217.07:42:01.16#ibcon#[28=FRQ=03,656.99\r\n] 2006.217.07:42:01.16#ibcon#*before write, iclass 27, count 0 2006.217.07:42:01.16#ibcon#enter sib2, iclass 27, count 0 2006.217.07:42:01.16#ibcon#flushed, iclass 27, count 0 2006.217.07:42:01.16#ibcon#about to write, iclass 27, count 0 2006.217.07:42:01.16#ibcon#wrote, iclass 27, count 0 2006.217.07:42:01.16#ibcon#about to read 3, iclass 27, count 0 2006.217.07:42:01.20#ibcon#read 3, iclass 27, count 0 2006.217.07:42:01.20#ibcon#about to read 4, iclass 27, count 0 2006.217.07:42:01.20#ibcon#read 4, iclass 27, count 0 2006.217.07:42:01.20#ibcon#about to read 5, iclass 27, count 0 2006.217.07:42:01.20#ibcon#read 5, iclass 27, count 0 2006.217.07:42:01.20#ibcon#about to read 6, iclass 27, count 0 2006.217.07:42:01.20#ibcon#read 6, iclass 27, count 0 2006.217.07:42:01.20#ibcon#end of sib2, iclass 27, count 0 2006.217.07:42:01.20#ibcon#*after write, iclass 27, count 0 2006.217.07:42:01.20#ibcon#*before return 0, iclass 27, count 0 2006.217.07:42:01.20#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.217.07:42:01.20#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.217.07:42:01.20#ibcon#about to clear, iclass 27 cls_cnt 0 2006.217.07:42:01.20#ibcon#cleared, iclass 27 cls_cnt 0 2006.217.07:42:01.20$vc4f8/vb=3,4 2006.217.07:42:01.21#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.217.07:42:01.21#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.217.07:42:01.21#ibcon#ireg 11 cls_cnt 2 2006.217.07:42:01.21#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.217.07:42:01.25#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.217.07:42:01.25#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.217.07:42:01.25#ibcon#enter wrdev, iclass 29, count 2 2006.217.07:42:01.25#ibcon#first serial, iclass 29, count 2 2006.217.07:42:01.25#ibcon#enter sib2, iclass 29, count 2 2006.217.07:42:01.25#ibcon#flushed, iclass 29, count 2 2006.217.07:42:01.25#ibcon#about to write, iclass 29, count 2 2006.217.07:42:01.25#ibcon#wrote, iclass 29, count 2 2006.217.07:42:01.25#ibcon#about to read 3, iclass 29, count 2 2006.217.07:42:01.27#ibcon#read 3, iclass 29, count 2 2006.217.07:42:01.27#ibcon#about to read 4, iclass 29, count 2 2006.217.07:42:01.27#ibcon#read 4, iclass 29, count 2 2006.217.07:42:01.27#ibcon#about to read 5, iclass 29, count 2 2006.217.07:42:01.27#ibcon#read 5, iclass 29, count 2 2006.217.07:42:01.27#ibcon#about to read 6, iclass 29, count 2 2006.217.07:42:01.27#ibcon#read 6, iclass 29, count 2 2006.217.07:42:01.27#ibcon#end of sib2, iclass 29, count 2 2006.217.07:42:01.27#ibcon#*mode == 0, iclass 29, count 2 2006.217.07:42:01.27#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.217.07:42:01.27#ibcon#[27=AT03-04\r\n] 2006.217.07:42:01.27#ibcon#*before write, iclass 29, count 2 2006.217.07:42:01.27#ibcon#enter sib2, iclass 29, count 2 2006.217.07:42:01.27#ibcon#flushed, iclass 29, count 2 2006.217.07:42:01.27#ibcon#about to write, iclass 29, count 2 2006.217.07:42:01.27#ibcon#wrote, iclass 29, count 2 2006.217.07:42:01.27#ibcon#about to read 3, iclass 29, count 2 2006.217.07:42:01.30#ibcon#read 3, iclass 29, count 2 2006.217.07:42:01.30#ibcon#about to read 4, iclass 29, count 2 2006.217.07:42:01.30#ibcon#read 4, iclass 29, count 2 2006.217.07:42:01.30#ibcon#about to read 5, iclass 29, count 2 2006.217.07:42:01.30#ibcon#read 5, iclass 29, count 2 2006.217.07:42:01.30#ibcon#about to read 6, iclass 29, count 2 2006.217.07:42:01.30#ibcon#read 6, iclass 29, count 2 2006.217.07:42:01.30#ibcon#end of sib2, iclass 29, count 2 2006.217.07:42:01.30#ibcon#*after write, iclass 29, count 2 2006.217.07:42:01.30#ibcon#*before return 0, iclass 29, count 2 2006.217.07:42:01.30#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.217.07:42:01.30#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.217.07:42:01.30#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.217.07:42:01.30#ibcon#ireg 7 cls_cnt 0 2006.217.07:42:01.30#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.217.07:42:01.42#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.217.07:42:01.42#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.217.07:42:01.42#ibcon#enter wrdev, iclass 29, count 0 2006.217.07:42:01.42#ibcon#first serial, iclass 29, count 0 2006.217.07:42:01.42#ibcon#enter sib2, iclass 29, count 0 2006.217.07:42:01.42#ibcon#flushed, iclass 29, count 0 2006.217.07:42:01.42#ibcon#about to write, iclass 29, count 0 2006.217.07:42:01.42#ibcon#wrote, iclass 29, count 0 2006.217.07:42:01.42#ibcon#about to read 3, iclass 29, count 0 2006.217.07:42:01.44#ibcon#read 3, iclass 29, count 0 2006.217.07:42:01.44#ibcon#about to read 4, iclass 29, count 0 2006.217.07:42:01.44#ibcon#read 4, iclass 29, count 0 2006.217.07:42:01.44#ibcon#about to read 5, iclass 29, count 0 2006.217.07:42:01.44#ibcon#read 5, iclass 29, count 0 2006.217.07:42:01.44#ibcon#about to read 6, iclass 29, count 0 2006.217.07:42:01.44#ibcon#read 6, iclass 29, count 0 2006.217.07:42:01.44#ibcon#end of sib2, iclass 29, count 0 2006.217.07:42:01.44#ibcon#*mode == 0, iclass 29, count 0 2006.217.07:42:01.44#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.217.07:42:01.44#ibcon#[27=USB\r\n] 2006.217.07:42:01.44#ibcon#*before write, iclass 29, count 0 2006.217.07:42:01.44#ibcon#enter sib2, iclass 29, count 0 2006.217.07:42:01.44#ibcon#flushed, iclass 29, count 0 2006.217.07:42:01.44#ibcon#about to write, iclass 29, count 0 2006.217.07:42:01.44#ibcon#wrote, iclass 29, count 0 2006.217.07:42:01.44#ibcon#about to read 3, iclass 29, count 0 2006.217.07:42:01.47#ibcon#read 3, iclass 29, count 0 2006.217.07:42:01.47#ibcon#about to read 4, iclass 29, count 0 2006.217.07:42:01.47#ibcon#read 4, iclass 29, count 0 2006.217.07:42:01.47#ibcon#about to read 5, iclass 29, count 0 2006.217.07:42:01.47#ibcon#read 5, iclass 29, count 0 2006.217.07:42:01.47#ibcon#about to read 6, iclass 29, count 0 2006.217.07:42:01.47#ibcon#read 6, iclass 29, count 0 2006.217.07:42:01.47#ibcon#end of sib2, iclass 29, count 0 2006.217.07:42:01.47#ibcon#*after write, iclass 29, count 0 2006.217.07:42:01.47#ibcon#*before return 0, iclass 29, count 0 2006.217.07:42:01.47#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.217.07:42:01.47#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.217.07:42:01.47#ibcon#about to clear, iclass 29 cls_cnt 0 2006.217.07:42:01.47#ibcon#cleared, iclass 29 cls_cnt 0 2006.217.07:42:01.47$vc4f8/vblo=4,712.99 2006.217.07:42:01.48#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.217.07:42:01.48#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.217.07:42:01.48#ibcon#ireg 17 cls_cnt 0 2006.217.07:42:01.48#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.217.07:42:01.48#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.217.07:42:01.48#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.217.07:42:01.48#ibcon#enter wrdev, iclass 31, count 0 2006.217.07:42:01.48#ibcon#first serial, iclass 31, count 0 2006.217.07:42:01.48#ibcon#enter sib2, iclass 31, count 0 2006.217.07:42:01.48#ibcon#flushed, iclass 31, count 0 2006.217.07:42:01.48#ibcon#about to write, iclass 31, count 0 2006.217.07:42:01.48#ibcon#wrote, iclass 31, count 0 2006.217.07:42:01.48#ibcon#about to read 3, iclass 31, count 0 2006.217.07:42:01.49#ibcon#read 3, iclass 31, count 0 2006.217.07:42:01.49#ibcon#about to read 4, iclass 31, count 0 2006.217.07:42:01.49#ibcon#read 4, iclass 31, count 0 2006.217.07:42:01.49#ibcon#about to read 5, iclass 31, count 0 2006.217.07:42:01.49#ibcon#read 5, iclass 31, count 0 2006.217.07:42:01.49#ibcon#about to read 6, iclass 31, count 0 2006.217.07:42:01.49#ibcon#read 6, iclass 31, count 0 2006.217.07:42:01.49#ibcon#end of sib2, iclass 31, count 0 2006.217.07:42:01.49#ibcon#*mode == 0, iclass 31, count 0 2006.217.07:42:01.49#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.217.07:42:01.49#ibcon#[28=FRQ=04,712.99\r\n] 2006.217.07:42:01.49#ibcon#*before write, iclass 31, count 0 2006.217.07:42:01.49#ibcon#enter sib2, iclass 31, count 0 2006.217.07:42:01.49#ibcon#flushed, iclass 31, count 0 2006.217.07:42:01.49#ibcon#about to write, iclass 31, count 0 2006.217.07:42:01.49#ibcon#wrote, iclass 31, count 0 2006.217.07:42:01.49#ibcon#about to read 3, iclass 31, count 0 2006.217.07:42:01.53#ibcon#read 3, iclass 31, count 0 2006.217.07:42:01.53#ibcon#about to read 4, iclass 31, count 0 2006.217.07:42:01.53#ibcon#read 4, iclass 31, count 0 2006.217.07:42:01.53#ibcon#about to read 5, iclass 31, count 0 2006.217.07:42:01.53#ibcon#read 5, iclass 31, count 0 2006.217.07:42:01.53#ibcon#about to read 6, iclass 31, count 0 2006.217.07:42:01.53#ibcon#read 6, iclass 31, count 0 2006.217.07:42:01.53#ibcon#end of sib2, iclass 31, count 0 2006.217.07:42:01.53#ibcon#*after write, iclass 31, count 0 2006.217.07:42:01.53#ibcon#*before return 0, iclass 31, count 0 2006.217.07:42:01.53#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.217.07:42:01.53#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.217.07:42:01.53#ibcon#about to clear, iclass 31 cls_cnt 0 2006.217.07:42:01.53#ibcon#cleared, iclass 31 cls_cnt 0 2006.217.07:42:01.53$vc4f8/vb=4,4 2006.217.07:42:01.54#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.217.07:42:01.54#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.217.07:42:01.54#ibcon#ireg 11 cls_cnt 2 2006.217.07:42:01.54#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.217.07:42:01.58#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.217.07:42:01.58#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.217.07:42:01.58#ibcon#enter wrdev, iclass 33, count 2 2006.217.07:42:01.58#ibcon#first serial, iclass 33, count 2 2006.217.07:42:01.58#ibcon#enter sib2, iclass 33, count 2 2006.217.07:42:01.58#ibcon#flushed, iclass 33, count 2 2006.217.07:42:01.58#ibcon#about to write, iclass 33, count 2 2006.217.07:42:01.58#ibcon#wrote, iclass 33, count 2 2006.217.07:42:01.58#ibcon#about to read 3, iclass 33, count 2 2006.217.07:42:01.60#ibcon#read 3, iclass 33, count 2 2006.217.07:42:01.60#ibcon#about to read 4, iclass 33, count 2 2006.217.07:42:01.60#ibcon#read 4, iclass 33, count 2 2006.217.07:42:01.60#ibcon#about to read 5, iclass 33, count 2 2006.217.07:42:01.60#ibcon#read 5, iclass 33, count 2 2006.217.07:42:01.60#ibcon#about to read 6, iclass 33, count 2 2006.217.07:42:01.60#ibcon#read 6, iclass 33, count 2 2006.217.07:42:01.60#ibcon#end of sib2, iclass 33, count 2 2006.217.07:42:01.60#ibcon#*mode == 0, iclass 33, count 2 2006.217.07:42:01.60#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.217.07:42:01.60#ibcon#[27=AT04-04\r\n] 2006.217.07:42:01.60#ibcon#*before write, iclass 33, count 2 2006.217.07:42:01.60#ibcon#enter sib2, iclass 33, count 2 2006.217.07:42:01.60#ibcon#flushed, iclass 33, count 2 2006.217.07:42:01.60#ibcon#about to write, iclass 33, count 2 2006.217.07:42:01.60#ibcon#wrote, iclass 33, count 2 2006.217.07:42:01.60#ibcon#about to read 3, iclass 33, count 2 2006.217.07:42:01.63#ibcon#read 3, iclass 33, count 2 2006.217.07:42:01.63#ibcon#about to read 4, iclass 33, count 2 2006.217.07:42:01.63#ibcon#read 4, iclass 33, count 2 2006.217.07:42:01.63#ibcon#about to read 5, iclass 33, count 2 2006.217.07:42:01.63#ibcon#read 5, iclass 33, count 2 2006.217.07:42:01.63#ibcon#about to read 6, iclass 33, count 2 2006.217.07:42:01.63#ibcon#read 6, iclass 33, count 2 2006.217.07:42:01.63#ibcon#end of sib2, iclass 33, count 2 2006.217.07:42:01.63#ibcon#*after write, iclass 33, count 2 2006.217.07:42:01.63#ibcon#*before return 0, iclass 33, count 2 2006.217.07:42:01.63#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.217.07:42:01.63#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.217.07:42:01.63#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.217.07:42:01.63#ibcon#ireg 7 cls_cnt 0 2006.217.07:42:01.63#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.217.07:42:01.75#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.217.07:42:01.75#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.217.07:42:01.75#ibcon#enter wrdev, iclass 33, count 0 2006.217.07:42:01.75#ibcon#first serial, iclass 33, count 0 2006.217.07:42:01.75#ibcon#enter sib2, iclass 33, count 0 2006.217.07:42:01.75#ibcon#flushed, iclass 33, count 0 2006.217.07:42:01.75#ibcon#about to write, iclass 33, count 0 2006.217.07:42:01.75#ibcon#wrote, iclass 33, count 0 2006.217.07:42:01.75#ibcon#about to read 3, iclass 33, count 0 2006.217.07:42:01.77#ibcon#read 3, iclass 33, count 0 2006.217.07:42:01.77#ibcon#about to read 4, iclass 33, count 0 2006.217.07:42:01.77#ibcon#read 4, iclass 33, count 0 2006.217.07:42:01.77#ibcon#about to read 5, iclass 33, count 0 2006.217.07:42:01.77#ibcon#read 5, iclass 33, count 0 2006.217.07:42:01.77#ibcon#about to read 6, iclass 33, count 0 2006.217.07:42:01.77#ibcon#read 6, iclass 33, count 0 2006.217.07:42:01.77#ibcon#end of sib2, iclass 33, count 0 2006.217.07:42:01.77#ibcon#*mode == 0, iclass 33, count 0 2006.217.07:42:01.77#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.217.07:42:01.77#ibcon#[27=USB\r\n] 2006.217.07:42:01.77#ibcon#*before write, iclass 33, count 0 2006.217.07:42:01.77#ibcon#enter sib2, iclass 33, count 0 2006.217.07:42:01.77#ibcon#flushed, iclass 33, count 0 2006.217.07:42:01.77#ibcon#about to write, iclass 33, count 0 2006.217.07:42:01.77#ibcon#wrote, iclass 33, count 0 2006.217.07:42:01.77#ibcon#about to read 3, iclass 33, count 0 2006.217.07:42:01.80#ibcon#read 3, iclass 33, count 0 2006.217.07:42:01.80#ibcon#about to read 4, iclass 33, count 0 2006.217.07:42:01.80#ibcon#read 4, iclass 33, count 0 2006.217.07:42:01.80#ibcon#about to read 5, iclass 33, count 0 2006.217.07:42:01.80#ibcon#read 5, iclass 33, count 0 2006.217.07:42:01.80#ibcon#about to read 6, iclass 33, count 0 2006.217.07:42:01.80#ibcon#read 6, iclass 33, count 0 2006.217.07:42:01.80#ibcon#end of sib2, iclass 33, count 0 2006.217.07:42:01.80#ibcon#*after write, iclass 33, count 0 2006.217.07:42:01.80#ibcon#*before return 0, iclass 33, count 0 2006.217.07:42:01.80#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.217.07:42:01.80#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.217.07:42:01.80#ibcon#about to clear, iclass 33 cls_cnt 0 2006.217.07:42:01.80#ibcon#cleared, iclass 33 cls_cnt 0 2006.217.07:42:01.80$vc4f8/vblo=5,744.99 2006.217.07:42:01.81#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.217.07:42:01.81#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.217.07:42:01.81#ibcon#ireg 17 cls_cnt 0 2006.217.07:42:01.81#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.217.07:42:01.81#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.217.07:42:01.81#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.217.07:42:01.81#ibcon#enter wrdev, iclass 35, count 0 2006.217.07:42:01.81#ibcon#first serial, iclass 35, count 0 2006.217.07:42:01.81#ibcon#enter sib2, iclass 35, count 0 2006.217.07:42:01.81#ibcon#flushed, iclass 35, count 0 2006.217.07:42:01.81#ibcon#about to write, iclass 35, count 0 2006.217.07:42:01.81#ibcon#wrote, iclass 35, count 0 2006.217.07:42:01.81#ibcon#about to read 3, iclass 35, count 0 2006.217.07:42:01.82#ibcon#read 3, iclass 35, count 0 2006.217.07:42:01.82#ibcon#about to read 4, iclass 35, count 0 2006.217.07:42:01.82#ibcon#read 4, iclass 35, count 0 2006.217.07:42:01.82#ibcon#about to read 5, iclass 35, count 0 2006.217.07:42:01.82#ibcon#read 5, iclass 35, count 0 2006.217.07:42:01.82#ibcon#about to read 6, iclass 35, count 0 2006.217.07:42:01.82#ibcon#read 6, iclass 35, count 0 2006.217.07:42:01.82#ibcon#end of sib2, iclass 35, count 0 2006.217.07:42:01.82#ibcon#*mode == 0, iclass 35, count 0 2006.217.07:42:01.82#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.217.07:42:01.82#ibcon#[28=FRQ=05,744.99\r\n] 2006.217.07:42:01.82#ibcon#*before write, iclass 35, count 0 2006.217.07:42:01.82#ibcon#enter sib2, iclass 35, count 0 2006.217.07:42:01.82#ibcon#flushed, iclass 35, count 0 2006.217.07:42:01.82#ibcon#about to write, iclass 35, count 0 2006.217.07:42:01.82#ibcon#wrote, iclass 35, count 0 2006.217.07:42:01.82#ibcon#about to read 3, iclass 35, count 0 2006.217.07:42:01.86#ibcon#read 3, iclass 35, count 0 2006.217.07:42:01.86#ibcon#about to read 4, iclass 35, count 0 2006.217.07:42:01.86#ibcon#read 4, iclass 35, count 0 2006.217.07:42:01.86#ibcon#about to read 5, iclass 35, count 0 2006.217.07:42:01.86#ibcon#read 5, iclass 35, count 0 2006.217.07:42:01.86#ibcon#about to read 6, iclass 35, count 0 2006.217.07:42:01.86#ibcon#read 6, iclass 35, count 0 2006.217.07:42:01.86#ibcon#end of sib2, iclass 35, count 0 2006.217.07:42:01.86#ibcon#*after write, iclass 35, count 0 2006.217.07:42:01.86#ibcon#*before return 0, iclass 35, count 0 2006.217.07:42:01.86#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.217.07:42:01.86#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.217.07:42:01.86#ibcon#about to clear, iclass 35 cls_cnt 0 2006.217.07:42:01.86#ibcon#cleared, iclass 35 cls_cnt 0 2006.217.07:42:01.86$vc4f8/vb=5,4 2006.217.07:42:01.87#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.217.07:42:01.87#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.217.07:42:01.87#ibcon#ireg 11 cls_cnt 2 2006.217.07:42:01.87#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.217.07:42:01.91#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.217.07:42:01.91#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.217.07:42:01.91#ibcon#enter wrdev, iclass 37, count 2 2006.217.07:42:01.91#ibcon#first serial, iclass 37, count 2 2006.217.07:42:01.91#ibcon#enter sib2, iclass 37, count 2 2006.217.07:42:01.91#ibcon#flushed, iclass 37, count 2 2006.217.07:42:01.91#ibcon#about to write, iclass 37, count 2 2006.217.07:42:01.91#ibcon#wrote, iclass 37, count 2 2006.217.07:42:01.91#ibcon#about to read 3, iclass 37, count 2 2006.217.07:42:01.93#ibcon#read 3, iclass 37, count 2 2006.217.07:42:01.93#ibcon#about to read 4, iclass 37, count 2 2006.217.07:42:01.93#ibcon#read 4, iclass 37, count 2 2006.217.07:42:01.93#ibcon#about to read 5, iclass 37, count 2 2006.217.07:42:01.93#ibcon#read 5, iclass 37, count 2 2006.217.07:42:01.93#ibcon#about to read 6, iclass 37, count 2 2006.217.07:42:01.93#ibcon#read 6, iclass 37, count 2 2006.217.07:42:01.93#ibcon#end of sib2, iclass 37, count 2 2006.217.07:42:01.93#ibcon#*mode == 0, iclass 37, count 2 2006.217.07:42:01.93#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.217.07:42:01.93#ibcon#[27=AT05-04\r\n] 2006.217.07:42:01.93#ibcon#*before write, iclass 37, count 2 2006.217.07:42:01.93#ibcon#enter sib2, iclass 37, count 2 2006.217.07:42:01.93#ibcon#flushed, iclass 37, count 2 2006.217.07:42:01.93#ibcon#about to write, iclass 37, count 2 2006.217.07:42:01.93#ibcon#wrote, iclass 37, count 2 2006.217.07:42:01.93#ibcon#about to read 3, iclass 37, count 2 2006.217.07:42:01.96#ibcon#read 3, iclass 37, count 2 2006.217.07:42:01.96#ibcon#about to read 4, iclass 37, count 2 2006.217.07:42:01.96#ibcon#read 4, iclass 37, count 2 2006.217.07:42:01.96#ibcon#about to read 5, iclass 37, count 2 2006.217.07:42:01.96#ibcon#read 5, iclass 37, count 2 2006.217.07:42:01.96#ibcon#about to read 6, iclass 37, count 2 2006.217.07:42:01.96#ibcon#read 6, iclass 37, count 2 2006.217.07:42:01.96#ibcon#end of sib2, iclass 37, count 2 2006.217.07:42:01.96#ibcon#*after write, iclass 37, count 2 2006.217.07:42:01.96#ibcon#*before return 0, iclass 37, count 2 2006.217.07:42:01.96#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.217.07:42:01.96#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.217.07:42:01.96#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.217.07:42:01.96#ibcon#ireg 7 cls_cnt 0 2006.217.07:42:01.96#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.217.07:42:02.08#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.217.07:42:02.08#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.217.07:42:02.08#ibcon#enter wrdev, iclass 37, count 0 2006.217.07:42:02.08#ibcon#first serial, iclass 37, count 0 2006.217.07:42:02.08#ibcon#enter sib2, iclass 37, count 0 2006.217.07:42:02.08#ibcon#flushed, iclass 37, count 0 2006.217.07:42:02.08#ibcon#about to write, iclass 37, count 0 2006.217.07:42:02.08#ibcon#wrote, iclass 37, count 0 2006.217.07:42:02.08#ibcon#about to read 3, iclass 37, count 0 2006.217.07:42:02.10#ibcon#read 3, iclass 37, count 0 2006.217.07:42:02.10#ibcon#about to read 4, iclass 37, count 0 2006.217.07:42:02.10#ibcon#read 4, iclass 37, count 0 2006.217.07:42:02.10#ibcon#about to read 5, iclass 37, count 0 2006.217.07:42:02.10#ibcon#read 5, iclass 37, count 0 2006.217.07:42:02.10#ibcon#about to read 6, iclass 37, count 0 2006.217.07:42:02.10#ibcon#read 6, iclass 37, count 0 2006.217.07:42:02.10#ibcon#end of sib2, iclass 37, count 0 2006.217.07:42:02.10#ibcon#*mode == 0, iclass 37, count 0 2006.217.07:42:02.10#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.217.07:42:02.10#ibcon#[27=USB\r\n] 2006.217.07:42:02.10#ibcon#*before write, iclass 37, count 0 2006.217.07:42:02.10#ibcon#enter sib2, iclass 37, count 0 2006.217.07:42:02.10#ibcon#flushed, iclass 37, count 0 2006.217.07:42:02.10#ibcon#about to write, iclass 37, count 0 2006.217.07:42:02.10#ibcon#wrote, iclass 37, count 0 2006.217.07:42:02.10#ibcon#about to read 3, iclass 37, count 0 2006.217.07:42:02.13#ibcon#read 3, iclass 37, count 0 2006.217.07:42:02.13#ibcon#about to read 4, iclass 37, count 0 2006.217.07:42:02.13#ibcon#read 4, iclass 37, count 0 2006.217.07:42:02.13#ibcon#about to read 5, iclass 37, count 0 2006.217.07:42:02.13#ibcon#read 5, iclass 37, count 0 2006.217.07:42:02.13#ibcon#about to read 6, iclass 37, count 0 2006.217.07:42:02.13#ibcon#read 6, iclass 37, count 0 2006.217.07:42:02.13#ibcon#end of sib2, iclass 37, count 0 2006.217.07:42:02.13#ibcon#*after write, iclass 37, count 0 2006.217.07:42:02.13#ibcon#*before return 0, iclass 37, count 0 2006.217.07:42:02.13#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.217.07:42:02.13#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.217.07:42:02.13#ibcon#about to clear, iclass 37 cls_cnt 0 2006.217.07:42:02.13#ibcon#cleared, iclass 37 cls_cnt 0 2006.217.07:42:02.13$vc4f8/vblo=6,752.99 2006.217.07:42:02.14#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.217.07:42:02.14#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.217.07:42:02.14#ibcon#ireg 17 cls_cnt 0 2006.217.07:42:02.14#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.217.07:42:02.14#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.217.07:42:02.14#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.217.07:42:02.14#ibcon#enter wrdev, iclass 39, count 0 2006.217.07:42:02.14#ibcon#first serial, iclass 39, count 0 2006.217.07:42:02.14#ibcon#enter sib2, iclass 39, count 0 2006.217.07:42:02.14#ibcon#flushed, iclass 39, count 0 2006.217.07:42:02.14#ibcon#about to write, iclass 39, count 0 2006.217.07:42:02.14#ibcon#wrote, iclass 39, count 0 2006.217.07:42:02.14#ibcon#about to read 3, iclass 39, count 0 2006.217.07:42:02.15#ibcon#read 3, iclass 39, count 0 2006.217.07:42:02.15#ibcon#about to read 4, iclass 39, count 0 2006.217.07:42:02.15#ibcon#read 4, iclass 39, count 0 2006.217.07:42:02.15#ibcon#about to read 5, iclass 39, count 0 2006.217.07:42:02.15#ibcon#read 5, iclass 39, count 0 2006.217.07:42:02.15#ibcon#about to read 6, iclass 39, count 0 2006.217.07:42:02.15#ibcon#read 6, iclass 39, count 0 2006.217.07:42:02.15#ibcon#end of sib2, iclass 39, count 0 2006.217.07:42:02.15#ibcon#*mode == 0, iclass 39, count 0 2006.217.07:42:02.15#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.217.07:42:02.15#ibcon#[28=FRQ=06,752.99\r\n] 2006.217.07:42:02.15#ibcon#*before write, iclass 39, count 0 2006.217.07:42:02.15#ibcon#enter sib2, iclass 39, count 0 2006.217.07:42:02.15#ibcon#flushed, iclass 39, count 0 2006.217.07:42:02.15#ibcon#about to write, iclass 39, count 0 2006.217.07:42:02.15#ibcon#wrote, iclass 39, count 0 2006.217.07:42:02.15#ibcon#about to read 3, iclass 39, count 0 2006.217.07:42:02.19#ibcon#read 3, iclass 39, count 0 2006.217.07:42:02.19#ibcon#about to read 4, iclass 39, count 0 2006.217.07:42:02.19#ibcon#read 4, iclass 39, count 0 2006.217.07:42:02.19#ibcon#about to read 5, iclass 39, count 0 2006.217.07:42:02.19#ibcon#read 5, iclass 39, count 0 2006.217.07:42:02.19#ibcon#about to read 6, iclass 39, count 0 2006.217.07:42:02.19#ibcon#read 6, iclass 39, count 0 2006.217.07:42:02.19#ibcon#end of sib2, iclass 39, count 0 2006.217.07:42:02.19#ibcon#*after write, iclass 39, count 0 2006.217.07:42:02.19#ibcon#*before return 0, iclass 39, count 0 2006.217.07:42:02.19#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.217.07:42:02.19#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.217.07:42:02.19#ibcon#about to clear, iclass 39 cls_cnt 0 2006.217.07:42:02.19#ibcon#cleared, iclass 39 cls_cnt 0 2006.217.07:42:02.19$vc4f8/vb=6,4 2006.217.07:42:02.20#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.217.07:42:02.20#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.217.07:42:02.20#ibcon#ireg 11 cls_cnt 2 2006.217.07:42:02.20#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.217.07:42:02.24#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.217.07:42:02.24#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.217.07:42:02.24#ibcon#enter wrdev, iclass 3, count 2 2006.217.07:42:02.24#ibcon#first serial, iclass 3, count 2 2006.217.07:42:02.24#ibcon#enter sib2, iclass 3, count 2 2006.217.07:42:02.24#ibcon#flushed, iclass 3, count 2 2006.217.07:42:02.24#ibcon#about to write, iclass 3, count 2 2006.217.07:42:02.24#ibcon#wrote, iclass 3, count 2 2006.217.07:42:02.24#ibcon#about to read 3, iclass 3, count 2 2006.217.07:42:02.26#ibcon#read 3, iclass 3, count 2 2006.217.07:42:02.26#ibcon#about to read 4, iclass 3, count 2 2006.217.07:42:02.26#ibcon#read 4, iclass 3, count 2 2006.217.07:42:02.26#ibcon#about to read 5, iclass 3, count 2 2006.217.07:42:02.26#ibcon#read 5, iclass 3, count 2 2006.217.07:42:02.26#ibcon#about to read 6, iclass 3, count 2 2006.217.07:42:02.26#ibcon#read 6, iclass 3, count 2 2006.217.07:42:02.26#ibcon#end of sib2, iclass 3, count 2 2006.217.07:42:02.26#ibcon#*mode == 0, iclass 3, count 2 2006.217.07:42:02.26#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.217.07:42:02.26#ibcon#[27=AT06-04\r\n] 2006.217.07:42:02.26#ibcon#*before write, iclass 3, count 2 2006.217.07:42:02.26#ibcon#enter sib2, iclass 3, count 2 2006.217.07:42:02.26#ibcon#flushed, iclass 3, count 2 2006.217.07:42:02.26#ibcon#about to write, iclass 3, count 2 2006.217.07:42:02.26#ibcon#wrote, iclass 3, count 2 2006.217.07:42:02.26#ibcon#about to read 3, iclass 3, count 2 2006.217.07:42:02.29#ibcon#read 3, iclass 3, count 2 2006.217.07:42:02.29#ibcon#about to read 4, iclass 3, count 2 2006.217.07:42:02.29#ibcon#read 4, iclass 3, count 2 2006.217.07:42:02.29#ibcon#about to read 5, iclass 3, count 2 2006.217.07:42:02.29#ibcon#read 5, iclass 3, count 2 2006.217.07:42:02.29#ibcon#about to read 6, iclass 3, count 2 2006.217.07:42:02.29#ibcon#read 6, iclass 3, count 2 2006.217.07:42:02.29#ibcon#end of sib2, iclass 3, count 2 2006.217.07:42:02.29#ibcon#*after write, iclass 3, count 2 2006.217.07:42:02.29#ibcon#*before return 0, iclass 3, count 2 2006.217.07:42:02.29#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.217.07:42:02.29#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.217.07:42:02.29#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.217.07:42:02.29#ibcon#ireg 7 cls_cnt 0 2006.217.07:42:02.29#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.217.07:42:02.41#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.217.07:42:02.41#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.217.07:42:02.41#ibcon#enter wrdev, iclass 3, count 0 2006.217.07:42:02.41#ibcon#first serial, iclass 3, count 0 2006.217.07:42:02.41#ibcon#enter sib2, iclass 3, count 0 2006.217.07:42:02.41#ibcon#flushed, iclass 3, count 0 2006.217.07:42:02.41#ibcon#about to write, iclass 3, count 0 2006.217.07:42:02.41#ibcon#wrote, iclass 3, count 0 2006.217.07:42:02.41#ibcon#about to read 3, iclass 3, count 0 2006.217.07:42:02.43#ibcon#read 3, iclass 3, count 0 2006.217.07:42:02.43#ibcon#about to read 4, iclass 3, count 0 2006.217.07:42:02.43#ibcon#read 4, iclass 3, count 0 2006.217.07:42:02.43#ibcon#about to read 5, iclass 3, count 0 2006.217.07:42:02.43#ibcon#read 5, iclass 3, count 0 2006.217.07:42:02.43#ibcon#about to read 6, iclass 3, count 0 2006.217.07:42:02.43#ibcon#read 6, iclass 3, count 0 2006.217.07:42:02.43#ibcon#end of sib2, iclass 3, count 0 2006.217.07:42:02.43#ibcon#*mode == 0, iclass 3, count 0 2006.217.07:42:02.43#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.217.07:42:02.43#ibcon#[27=USB\r\n] 2006.217.07:42:02.43#ibcon#*before write, iclass 3, count 0 2006.217.07:42:02.43#ibcon#enter sib2, iclass 3, count 0 2006.217.07:42:02.43#ibcon#flushed, iclass 3, count 0 2006.217.07:42:02.43#ibcon#about to write, iclass 3, count 0 2006.217.07:42:02.43#ibcon#wrote, iclass 3, count 0 2006.217.07:42:02.43#ibcon#about to read 3, iclass 3, count 0 2006.217.07:42:02.46#ibcon#read 3, iclass 3, count 0 2006.217.07:42:02.46#ibcon#about to read 4, iclass 3, count 0 2006.217.07:42:02.46#ibcon#read 4, iclass 3, count 0 2006.217.07:42:02.46#ibcon#about to read 5, iclass 3, count 0 2006.217.07:42:02.46#ibcon#read 5, iclass 3, count 0 2006.217.07:42:02.46#ibcon#about to read 6, iclass 3, count 0 2006.217.07:42:02.46#ibcon#read 6, iclass 3, count 0 2006.217.07:42:02.46#ibcon#end of sib2, iclass 3, count 0 2006.217.07:42:02.46#ibcon#*after write, iclass 3, count 0 2006.217.07:42:02.46#ibcon#*before return 0, iclass 3, count 0 2006.217.07:42:02.46#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.217.07:42:02.46#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.217.07:42:02.46#ibcon#about to clear, iclass 3 cls_cnt 0 2006.217.07:42:02.46#ibcon#cleared, iclass 3 cls_cnt 0 2006.217.07:42:02.46$vc4f8/vabw=wide 2006.217.07:42:02.47#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.217.07:42:02.47#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.217.07:42:02.47#ibcon#ireg 8 cls_cnt 0 2006.217.07:42:02.47#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.217.07:42:02.47#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.217.07:42:02.47#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.217.07:42:02.47#ibcon#enter wrdev, iclass 5, count 0 2006.217.07:42:02.47#ibcon#first serial, iclass 5, count 0 2006.217.07:42:02.47#ibcon#enter sib2, iclass 5, count 0 2006.217.07:42:02.47#ibcon#flushed, iclass 5, count 0 2006.217.07:42:02.47#ibcon#about to write, iclass 5, count 0 2006.217.07:42:02.47#ibcon#wrote, iclass 5, count 0 2006.217.07:42:02.47#ibcon#about to read 3, iclass 5, count 0 2006.217.07:42:02.48#ibcon#read 3, iclass 5, count 0 2006.217.07:42:02.48#ibcon#about to read 4, iclass 5, count 0 2006.217.07:42:02.48#ibcon#read 4, iclass 5, count 0 2006.217.07:42:02.48#ibcon#about to read 5, iclass 5, count 0 2006.217.07:42:02.48#ibcon#read 5, iclass 5, count 0 2006.217.07:42:02.48#ibcon#about to read 6, iclass 5, count 0 2006.217.07:42:02.48#ibcon#read 6, iclass 5, count 0 2006.217.07:42:02.48#ibcon#end of sib2, iclass 5, count 0 2006.217.07:42:02.48#ibcon#*mode == 0, iclass 5, count 0 2006.217.07:42:02.48#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.217.07:42:02.48#ibcon#[25=BW32\r\n] 2006.217.07:42:02.48#ibcon#*before write, iclass 5, count 0 2006.217.07:42:02.48#ibcon#enter sib2, iclass 5, count 0 2006.217.07:42:02.48#ibcon#flushed, iclass 5, count 0 2006.217.07:42:02.48#ibcon#about to write, iclass 5, count 0 2006.217.07:42:02.48#ibcon#wrote, iclass 5, count 0 2006.217.07:42:02.48#ibcon#about to read 3, iclass 5, count 0 2006.217.07:42:02.51#ibcon#read 3, iclass 5, count 0 2006.217.07:42:02.51#ibcon#about to read 4, iclass 5, count 0 2006.217.07:42:02.51#ibcon#read 4, iclass 5, count 0 2006.217.07:42:02.51#ibcon#about to read 5, iclass 5, count 0 2006.217.07:42:02.51#ibcon#read 5, iclass 5, count 0 2006.217.07:42:02.51#ibcon#about to read 6, iclass 5, count 0 2006.217.07:42:02.51#ibcon#read 6, iclass 5, count 0 2006.217.07:42:02.51#ibcon#end of sib2, iclass 5, count 0 2006.217.07:42:02.51#ibcon#*after write, iclass 5, count 0 2006.217.07:42:02.51#ibcon#*before return 0, iclass 5, count 0 2006.217.07:42:02.51#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.217.07:42:02.51#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.217.07:42:02.51#ibcon#about to clear, iclass 5 cls_cnt 0 2006.217.07:42:02.51#ibcon#cleared, iclass 5 cls_cnt 0 2006.217.07:42:02.51$vc4f8/vbbw=wide 2006.217.07:42:02.52#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.217.07:42:02.52#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.217.07:42:02.52#ibcon#ireg 8 cls_cnt 0 2006.217.07:42:02.52#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.217.07:42:02.57#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.217.07:42:02.57#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.217.07:42:02.57#ibcon#enter wrdev, iclass 7, count 0 2006.217.07:42:02.57#ibcon#first serial, iclass 7, count 0 2006.217.07:42:02.57#ibcon#enter sib2, iclass 7, count 0 2006.217.07:42:02.57#ibcon#flushed, iclass 7, count 0 2006.217.07:42:02.57#ibcon#about to write, iclass 7, count 0 2006.217.07:42:02.57#ibcon#wrote, iclass 7, count 0 2006.217.07:42:02.57#ibcon#about to read 3, iclass 7, count 0 2006.217.07:42:02.59#ibcon#read 3, iclass 7, count 0 2006.217.07:42:02.59#ibcon#about to read 4, iclass 7, count 0 2006.217.07:42:02.59#ibcon#read 4, iclass 7, count 0 2006.217.07:42:02.59#ibcon#about to read 5, iclass 7, count 0 2006.217.07:42:02.59#ibcon#read 5, iclass 7, count 0 2006.217.07:42:02.59#ibcon#about to read 6, iclass 7, count 0 2006.217.07:42:02.59#ibcon#read 6, iclass 7, count 0 2006.217.07:42:02.59#ibcon#end of sib2, iclass 7, count 0 2006.217.07:42:02.59#ibcon#*mode == 0, iclass 7, count 0 2006.217.07:42:02.59#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.217.07:42:02.59#ibcon#[27=BW32\r\n] 2006.217.07:42:02.59#ibcon#*before write, iclass 7, count 0 2006.217.07:42:02.59#ibcon#enter sib2, iclass 7, count 0 2006.217.07:42:02.59#ibcon#flushed, iclass 7, count 0 2006.217.07:42:02.59#ibcon#about to write, iclass 7, count 0 2006.217.07:42:02.59#ibcon#wrote, iclass 7, count 0 2006.217.07:42:02.59#ibcon#about to read 3, iclass 7, count 0 2006.217.07:42:02.62#ibcon#read 3, iclass 7, count 0 2006.217.07:42:02.62#ibcon#about to read 4, iclass 7, count 0 2006.217.07:42:02.62#ibcon#read 4, iclass 7, count 0 2006.217.07:42:02.62#ibcon#about to read 5, iclass 7, count 0 2006.217.07:42:02.62#ibcon#read 5, iclass 7, count 0 2006.217.07:42:02.62#ibcon#about to read 6, iclass 7, count 0 2006.217.07:42:02.62#ibcon#read 6, iclass 7, count 0 2006.217.07:42:02.62#ibcon#end of sib2, iclass 7, count 0 2006.217.07:42:02.62#ibcon#*after write, iclass 7, count 0 2006.217.07:42:02.62#ibcon#*before return 0, iclass 7, count 0 2006.217.07:42:02.62#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.217.07:42:02.62#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.217.07:42:02.62#ibcon#about to clear, iclass 7 cls_cnt 0 2006.217.07:42:02.62#ibcon#cleared, iclass 7 cls_cnt 0 2006.217.07:42:02.63$4f8m12a/ifd4f 2006.217.07:42:02.63$ifd4f/lo= 2006.217.07:42:02.63$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.217.07:42:02.63$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.217.07:42:02.63$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.217.07:42:02.63$ifd4f/patch= 2006.217.07:42:02.63$ifd4f/patch=lo1,a1,a2,a3,a4 2006.217.07:42:02.63$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.217.07:42:02.63$ifd4f/patch=lo3,a5,a6,a7,a8 2006.217.07:42:02.63$4f8m12a/"form=m,16.000,1:2 2006.217.07:42:02.63$4f8m12a/"tpicd 2006.217.07:42:02.63$4f8m12a/echo=off 2006.217.07:42:02.63$4f8m12a/xlog=off 2006.217.07:42:02.63:!2006.217.07:42:30 2006.217.07:42:14.13#trakl#Source acquired 2006.217.07:42:15.13#flagr#flagr/antenna,acquired 2006.217.07:42:30.01:preob 2006.217.07:42:31.13/onsource/TRACKING 2006.217.07:42:31.14:!2006.217.07:42:40 2006.217.07:42:40.01:data_valid=on 2006.217.07:42:40.02:midob 2006.217.07:42:41.14/onsource/TRACKING 2006.217.07:42:41.15/wx/31.28,1008.6,62 2006.217.07:42:41.29/cable/+6.3838E-03 2006.217.07:42:42.38/va/01,05,usb,yes,31,33 2006.217.07:42:42.38/va/02,04,usb,yes,29,31 2006.217.07:42:42.38/va/03,04,usb,yes,28,28 2006.217.07:42:42.38/va/04,04,usb,yes,31,33 2006.217.07:42:42.38/va/05,07,usb,yes,33,35 2006.217.07:42:42.38/va/06,06,usb,yes,32,32 2006.217.07:42:42.38/va/07,06,usb,yes,33,32 2006.217.07:42:42.38/va/08,07,usb,yes,31,30 2006.217.07:42:42.61/valo/01,532.99,yes,locked 2006.217.07:42:42.61/valo/02,572.99,yes,locked 2006.217.07:42:42.61/valo/03,672.99,yes,locked 2006.217.07:42:42.61/valo/04,832.99,yes,locked 2006.217.07:42:42.61/valo/05,652.99,yes,locked 2006.217.07:42:42.61/valo/06,772.99,yes,locked 2006.217.07:42:42.61/valo/07,832.99,yes,locked 2006.217.07:42:42.61/valo/08,852.99,yes,locked 2006.217.07:42:43.70/vb/01,04,usb,yes,30,29 2006.217.07:42:43.70/vb/02,04,usb,yes,32,33 2006.217.07:42:43.70/vb/03,04,usb,yes,28,32 2006.217.07:42:43.70/vb/04,04,usb,yes,29,29 2006.217.07:42:43.70/vb/05,04,usb,yes,28,32 2006.217.07:42:43.70/vb/06,04,usb,yes,29,32 2006.217.07:42:43.70/vb/07,04,usb,yes,31,31 2006.217.07:42:43.70/vb/08,04,usb,yes,28,32 2006.217.07:42:43.93/vblo/01,632.99,yes,locked 2006.217.07:42:43.93/vblo/02,640.99,yes,locked 2006.217.07:42:43.93/vblo/03,656.99,yes,locked 2006.217.07:42:43.93/vblo/04,712.99,yes,locked 2006.217.07:42:43.93/vblo/05,744.99,yes,locked 2006.217.07:42:43.93/vblo/06,752.99,yes,locked 2006.217.07:42:43.93/vblo/07,734.99,yes,locked 2006.217.07:42:43.93/vblo/08,744.99,yes,locked 2006.217.07:42:44.08/vabw/8 2006.217.07:42:44.23/vbbw/8 2006.217.07:42:44.32/xfe/off,on,15.0 2006.217.07:42:44.69/ifatt/23,28,28,28 2006.217.07:42:45.07/fmout-gps/S +4.31E-07 2006.217.07:42:45.12:!2006.217.07:43:40 2006.217.07:43:40.00:data_valid=off 2006.217.07:43:40.01:postob 2006.217.07:43:40.09/cable/+6.3837E-03 2006.217.07:43:40.09/wx/31.28,1008.6,63 2006.217.07:43:41.06/fmout-gps/S +4.28E-07 2006.217.07:43:41.07:scan_name=217-0744,k06217,60 2006.217.07:43:41.07:source=3c371,180650.68,694928.1,2000.0,cw 2006.217.07:43:42.14#flagr#flagr/antenna,new-source 2006.217.07:43:42.15:checkk5 2006.217.07:43:42.52/chk_autoobs//k5ts1/ autoobs is running! 2006.217.07:43:42.91/chk_autoobs//k5ts2/ autoobs is running! 2006.217.07:43:43.29/chk_autoobs//k5ts3/ autoobs is running! 2006.217.07:43:43.67/chk_autoobs//k5ts4/ autoobs is running! 2006.217.07:43:44.03/chk_obsdata//k5ts1/T2170742??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:43:44.40/chk_obsdata//k5ts2/T2170742??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:43:44.76/chk_obsdata//k5ts3/T2170742??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:43:45.13/chk_obsdata//k5ts4/T2170742??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:43:45.83/k5log//k5ts1_log_newline 2006.217.07:43:46.54/k5log//k5ts2_log_newline 2006.217.07:43:47.23/k5log//k5ts3_log_newline 2006.217.07:43:47.92/k5log//k5ts4_log_newline 2006.217.07:43:47.94/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.217.07:43:47.94:4f8m12a=1 2006.217.07:43:47.94$4f8m12a/echo=on 2006.217.07:43:47.94$4f8m12a/pcalon 2006.217.07:43:47.94$pcalon/"no phase cal control is implemented here 2006.217.07:43:47.94$4f8m12a/"tpicd=stop 2006.217.07:43:47.94$4f8m12a/vc4f8 2006.217.07:43:47.94$vc4f8/valo=1,532.99 2006.217.07:43:47.95#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.217.07:43:47.95#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.217.07:43:47.95#ibcon#ireg 17 cls_cnt 0 2006.217.07:43:47.95#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.217.07:43:47.95#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.217.07:43:47.95#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.217.07:43:47.95#ibcon#enter wrdev, iclass 20, count 0 2006.217.07:43:47.95#ibcon#first serial, iclass 20, count 0 2006.217.07:43:47.95#ibcon#enter sib2, iclass 20, count 0 2006.217.07:43:47.95#ibcon#flushed, iclass 20, count 0 2006.217.07:43:47.95#ibcon#about to write, iclass 20, count 0 2006.217.07:43:47.95#ibcon#wrote, iclass 20, count 0 2006.217.07:43:47.95#ibcon#about to read 3, iclass 20, count 0 2006.217.07:43:47.99#ibcon#read 3, iclass 20, count 0 2006.217.07:43:47.99#ibcon#about to read 4, iclass 20, count 0 2006.217.07:43:47.99#ibcon#read 4, iclass 20, count 0 2006.217.07:43:47.99#ibcon#about to read 5, iclass 20, count 0 2006.217.07:43:47.99#ibcon#read 5, iclass 20, count 0 2006.217.07:43:47.99#ibcon#about to read 6, iclass 20, count 0 2006.217.07:43:47.99#ibcon#read 6, iclass 20, count 0 2006.217.07:43:47.99#ibcon#end of sib2, iclass 20, count 0 2006.217.07:43:47.99#ibcon#*mode == 0, iclass 20, count 0 2006.217.07:43:47.99#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.217.07:43:47.99#ibcon#[26=FRQ=01,532.99\r\n] 2006.217.07:43:47.99#ibcon#*before write, iclass 20, count 0 2006.217.07:43:47.99#ibcon#enter sib2, iclass 20, count 0 2006.217.07:43:47.99#ibcon#flushed, iclass 20, count 0 2006.217.07:43:47.99#ibcon#about to write, iclass 20, count 0 2006.217.07:43:47.99#ibcon#wrote, iclass 20, count 0 2006.217.07:43:47.99#ibcon#about to read 3, iclass 20, count 0 2006.217.07:43:48.03#ibcon#read 3, iclass 20, count 0 2006.217.07:43:48.03#ibcon#about to read 4, iclass 20, count 0 2006.217.07:43:48.03#ibcon#read 4, iclass 20, count 0 2006.217.07:43:48.03#ibcon#about to read 5, iclass 20, count 0 2006.217.07:43:48.03#ibcon#read 5, iclass 20, count 0 2006.217.07:43:48.03#ibcon#about to read 6, iclass 20, count 0 2006.217.07:43:48.03#ibcon#read 6, iclass 20, count 0 2006.217.07:43:48.03#ibcon#end of sib2, iclass 20, count 0 2006.217.07:43:48.03#ibcon#*after write, iclass 20, count 0 2006.217.07:43:48.03#ibcon#*before return 0, iclass 20, count 0 2006.217.07:43:48.03#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.217.07:43:48.03#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.217.07:43:48.03#ibcon#about to clear, iclass 20 cls_cnt 0 2006.217.07:43:48.03#ibcon#cleared, iclass 20 cls_cnt 0 2006.217.07:43:48.03$vc4f8/va=1,5 2006.217.07:43:48.03#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.217.07:43:48.03#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.217.07:43:48.03#ibcon#ireg 11 cls_cnt 2 2006.217.07:43:48.03#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.217.07:43:48.03#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.217.07:43:48.03#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.217.07:43:48.03#ibcon#enter wrdev, iclass 22, count 2 2006.217.07:43:48.03#ibcon#first serial, iclass 22, count 2 2006.217.07:43:48.04#ibcon#enter sib2, iclass 22, count 2 2006.217.07:43:48.04#ibcon#flushed, iclass 22, count 2 2006.217.07:43:48.04#ibcon#about to write, iclass 22, count 2 2006.217.07:43:48.04#ibcon#wrote, iclass 22, count 2 2006.217.07:43:48.04#ibcon#about to read 3, iclass 22, count 2 2006.217.07:43:48.06#ibcon#read 3, iclass 22, count 2 2006.217.07:43:48.06#ibcon#about to read 4, iclass 22, count 2 2006.217.07:43:48.06#ibcon#read 4, iclass 22, count 2 2006.217.07:43:48.06#ibcon#about to read 5, iclass 22, count 2 2006.217.07:43:48.06#ibcon#read 5, iclass 22, count 2 2006.217.07:43:48.06#ibcon#about to read 6, iclass 22, count 2 2006.217.07:43:48.06#ibcon#read 6, iclass 22, count 2 2006.217.07:43:48.06#ibcon#end of sib2, iclass 22, count 2 2006.217.07:43:48.06#ibcon#*mode == 0, iclass 22, count 2 2006.217.07:43:48.06#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.217.07:43:48.06#ibcon#[25=AT01-05\r\n] 2006.217.07:43:48.06#ibcon#*before write, iclass 22, count 2 2006.217.07:43:48.06#ibcon#enter sib2, iclass 22, count 2 2006.217.07:43:48.06#ibcon#flushed, iclass 22, count 2 2006.217.07:43:48.06#ibcon#about to write, iclass 22, count 2 2006.217.07:43:48.06#ibcon#wrote, iclass 22, count 2 2006.217.07:43:48.06#ibcon#about to read 3, iclass 22, count 2 2006.217.07:43:48.09#ibcon#read 3, iclass 22, count 2 2006.217.07:43:48.09#ibcon#about to read 4, iclass 22, count 2 2006.217.07:43:48.09#ibcon#read 4, iclass 22, count 2 2006.217.07:43:48.09#ibcon#about to read 5, iclass 22, count 2 2006.217.07:43:48.09#ibcon#read 5, iclass 22, count 2 2006.217.07:43:48.09#ibcon#about to read 6, iclass 22, count 2 2006.217.07:43:48.09#ibcon#read 6, iclass 22, count 2 2006.217.07:43:48.09#ibcon#end of sib2, iclass 22, count 2 2006.217.07:43:48.09#ibcon#*after write, iclass 22, count 2 2006.217.07:43:48.09#ibcon#*before return 0, iclass 22, count 2 2006.217.07:43:48.09#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.217.07:43:48.09#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.217.07:43:48.09#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.217.07:43:48.09#ibcon#ireg 7 cls_cnt 0 2006.217.07:43:48.09#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.217.07:43:48.20#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.217.07:43:48.20#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.217.07:43:48.20#ibcon#enter wrdev, iclass 22, count 0 2006.217.07:43:48.20#ibcon#first serial, iclass 22, count 0 2006.217.07:43:48.20#ibcon#enter sib2, iclass 22, count 0 2006.217.07:43:48.20#ibcon#flushed, iclass 22, count 0 2006.217.07:43:48.20#ibcon#about to write, iclass 22, count 0 2006.217.07:43:48.20#ibcon#wrote, iclass 22, count 0 2006.217.07:43:48.20#ibcon#about to read 3, iclass 22, count 0 2006.217.07:43:48.22#ibcon#read 3, iclass 22, count 0 2006.217.07:43:48.22#ibcon#about to read 4, iclass 22, count 0 2006.217.07:43:48.22#ibcon#read 4, iclass 22, count 0 2006.217.07:43:48.22#ibcon#about to read 5, iclass 22, count 0 2006.217.07:43:48.22#ibcon#read 5, iclass 22, count 0 2006.217.07:43:48.22#ibcon#about to read 6, iclass 22, count 0 2006.217.07:43:48.22#ibcon#read 6, iclass 22, count 0 2006.217.07:43:48.22#ibcon#end of sib2, iclass 22, count 0 2006.217.07:43:48.22#ibcon#*mode == 0, iclass 22, count 0 2006.217.07:43:48.22#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.217.07:43:48.22#ibcon#[25=USB\r\n] 2006.217.07:43:48.22#ibcon#*before write, iclass 22, count 0 2006.217.07:43:48.22#ibcon#enter sib2, iclass 22, count 0 2006.217.07:43:48.22#ibcon#flushed, iclass 22, count 0 2006.217.07:43:48.22#ibcon#about to write, iclass 22, count 0 2006.217.07:43:48.22#ibcon#wrote, iclass 22, count 0 2006.217.07:43:48.22#ibcon#about to read 3, iclass 22, count 0 2006.217.07:43:48.25#ibcon#read 3, iclass 22, count 0 2006.217.07:43:48.25#ibcon#about to read 4, iclass 22, count 0 2006.217.07:43:48.25#ibcon#read 4, iclass 22, count 0 2006.217.07:43:48.25#ibcon#about to read 5, iclass 22, count 0 2006.217.07:43:48.25#ibcon#read 5, iclass 22, count 0 2006.217.07:43:48.25#ibcon#about to read 6, iclass 22, count 0 2006.217.07:43:48.25#ibcon#read 6, iclass 22, count 0 2006.217.07:43:48.25#ibcon#end of sib2, iclass 22, count 0 2006.217.07:43:48.25#ibcon#*after write, iclass 22, count 0 2006.217.07:43:48.25#ibcon#*before return 0, iclass 22, count 0 2006.217.07:43:48.25#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.217.07:43:48.25#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.217.07:43:48.25#ibcon#about to clear, iclass 22 cls_cnt 0 2006.217.07:43:48.25#ibcon#cleared, iclass 22 cls_cnt 0 2006.217.07:43:48.25$vc4f8/valo=2,572.99 2006.217.07:43:48.25#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.217.07:43:48.25#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.217.07:43:48.25#ibcon#ireg 17 cls_cnt 0 2006.217.07:43:48.25#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.217.07:43:48.25#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.217.07:43:48.25#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.217.07:43:48.25#ibcon#enter wrdev, iclass 24, count 0 2006.217.07:43:48.26#ibcon#first serial, iclass 24, count 0 2006.217.07:43:48.26#ibcon#enter sib2, iclass 24, count 0 2006.217.07:43:48.26#ibcon#flushed, iclass 24, count 0 2006.217.07:43:48.26#ibcon#about to write, iclass 24, count 0 2006.217.07:43:48.26#ibcon#wrote, iclass 24, count 0 2006.217.07:43:48.26#ibcon#about to read 3, iclass 24, count 0 2006.217.07:43:48.28#ibcon#read 3, iclass 24, count 0 2006.217.07:43:48.28#ibcon#about to read 4, iclass 24, count 0 2006.217.07:43:48.28#ibcon#read 4, iclass 24, count 0 2006.217.07:43:48.28#ibcon#about to read 5, iclass 24, count 0 2006.217.07:43:48.28#ibcon#read 5, iclass 24, count 0 2006.217.07:43:48.28#ibcon#about to read 6, iclass 24, count 0 2006.217.07:43:48.28#ibcon#read 6, iclass 24, count 0 2006.217.07:43:48.28#ibcon#end of sib2, iclass 24, count 0 2006.217.07:43:48.28#ibcon#*mode == 0, iclass 24, count 0 2006.217.07:43:48.28#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.217.07:43:48.28#ibcon#[26=FRQ=02,572.99\r\n] 2006.217.07:43:48.28#ibcon#*before write, iclass 24, count 0 2006.217.07:43:48.28#ibcon#enter sib2, iclass 24, count 0 2006.217.07:43:48.28#ibcon#flushed, iclass 24, count 0 2006.217.07:43:48.28#ibcon#about to write, iclass 24, count 0 2006.217.07:43:48.28#ibcon#wrote, iclass 24, count 0 2006.217.07:43:48.28#ibcon#about to read 3, iclass 24, count 0 2006.217.07:43:48.32#ibcon#read 3, iclass 24, count 0 2006.217.07:43:48.32#ibcon#about to read 4, iclass 24, count 0 2006.217.07:43:48.32#ibcon#read 4, iclass 24, count 0 2006.217.07:43:48.32#ibcon#about to read 5, iclass 24, count 0 2006.217.07:43:48.32#ibcon#read 5, iclass 24, count 0 2006.217.07:43:48.32#ibcon#about to read 6, iclass 24, count 0 2006.217.07:43:48.32#ibcon#read 6, iclass 24, count 0 2006.217.07:43:48.32#ibcon#end of sib2, iclass 24, count 0 2006.217.07:43:48.32#ibcon#*after write, iclass 24, count 0 2006.217.07:43:48.32#ibcon#*before return 0, iclass 24, count 0 2006.217.07:43:48.32#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.217.07:43:48.32#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.217.07:43:48.32#ibcon#about to clear, iclass 24 cls_cnt 0 2006.217.07:43:48.32#ibcon#cleared, iclass 24 cls_cnt 0 2006.217.07:43:48.32$vc4f8/va=2,4 2006.217.07:43:48.32#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.217.07:43:48.32#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.217.07:43:48.32#ibcon#ireg 11 cls_cnt 2 2006.217.07:43:48.32#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.217.07:43:48.38#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.217.07:43:48.38#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.217.07:43:48.38#ibcon#enter wrdev, iclass 26, count 2 2006.217.07:43:48.38#ibcon#first serial, iclass 26, count 2 2006.217.07:43:48.38#ibcon#enter sib2, iclass 26, count 2 2006.217.07:43:48.38#ibcon#flushed, iclass 26, count 2 2006.217.07:43:48.38#ibcon#about to write, iclass 26, count 2 2006.217.07:43:48.38#ibcon#wrote, iclass 26, count 2 2006.217.07:43:48.38#ibcon#about to read 3, iclass 26, count 2 2006.217.07:43:48.39#ibcon#read 3, iclass 26, count 2 2006.217.07:43:48.39#ibcon#about to read 4, iclass 26, count 2 2006.217.07:43:48.39#ibcon#read 4, iclass 26, count 2 2006.217.07:43:48.39#ibcon#about to read 5, iclass 26, count 2 2006.217.07:43:48.39#ibcon#read 5, iclass 26, count 2 2006.217.07:43:48.39#ibcon#about to read 6, iclass 26, count 2 2006.217.07:43:48.39#ibcon#read 6, iclass 26, count 2 2006.217.07:43:48.39#ibcon#end of sib2, iclass 26, count 2 2006.217.07:43:48.39#ibcon#*mode == 0, iclass 26, count 2 2006.217.07:43:48.39#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.217.07:43:48.39#ibcon#[25=AT02-04\r\n] 2006.217.07:43:48.39#ibcon#*before write, iclass 26, count 2 2006.217.07:43:48.39#ibcon#enter sib2, iclass 26, count 2 2006.217.07:43:48.39#ibcon#flushed, iclass 26, count 2 2006.217.07:43:48.39#ibcon#about to write, iclass 26, count 2 2006.217.07:43:48.39#ibcon#wrote, iclass 26, count 2 2006.217.07:43:48.39#ibcon#about to read 3, iclass 26, count 2 2006.217.07:43:48.42#ibcon#read 3, iclass 26, count 2 2006.217.07:43:48.42#ibcon#about to read 4, iclass 26, count 2 2006.217.07:43:48.42#ibcon#read 4, iclass 26, count 2 2006.217.07:43:48.42#ibcon#about to read 5, iclass 26, count 2 2006.217.07:43:48.42#ibcon#read 5, iclass 26, count 2 2006.217.07:43:48.42#ibcon#about to read 6, iclass 26, count 2 2006.217.07:43:48.42#ibcon#read 6, iclass 26, count 2 2006.217.07:43:48.42#ibcon#end of sib2, iclass 26, count 2 2006.217.07:43:48.42#ibcon#*after write, iclass 26, count 2 2006.217.07:43:48.42#ibcon#*before return 0, iclass 26, count 2 2006.217.07:43:48.42#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.217.07:43:48.42#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.217.07:43:48.42#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.217.07:43:48.42#ibcon#ireg 7 cls_cnt 0 2006.217.07:43:48.42#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.217.07:43:48.54#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.217.07:43:48.54#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.217.07:43:48.54#ibcon#enter wrdev, iclass 26, count 0 2006.217.07:43:48.54#ibcon#first serial, iclass 26, count 0 2006.217.07:43:48.54#ibcon#enter sib2, iclass 26, count 0 2006.217.07:43:48.54#ibcon#flushed, iclass 26, count 0 2006.217.07:43:48.54#ibcon#about to write, iclass 26, count 0 2006.217.07:43:48.54#ibcon#wrote, iclass 26, count 0 2006.217.07:43:48.54#ibcon#about to read 3, iclass 26, count 0 2006.217.07:43:48.56#ibcon#read 3, iclass 26, count 0 2006.217.07:43:48.56#ibcon#about to read 4, iclass 26, count 0 2006.217.07:43:48.56#ibcon#read 4, iclass 26, count 0 2006.217.07:43:48.56#ibcon#about to read 5, iclass 26, count 0 2006.217.07:43:48.56#ibcon#read 5, iclass 26, count 0 2006.217.07:43:48.56#ibcon#about to read 6, iclass 26, count 0 2006.217.07:43:48.56#ibcon#read 6, iclass 26, count 0 2006.217.07:43:48.56#ibcon#end of sib2, iclass 26, count 0 2006.217.07:43:48.56#ibcon#*mode == 0, iclass 26, count 0 2006.217.07:43:48.56#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.217.07:43:48.56#ibcon#[25=USB\r\n] 2006.217.07:43:48.56#ibcon#*before write, iclass 26, count 0 2006.217.07:43:48.56#ibcon#enter sib2, iclass 26, count 0 2006.217.07:43:48.56#ibcon#flushed, iclass 26, count 0 2006.217.07:43:48.56#ibcon#about to write, iclass 26, count 0 2006.217.07:43:48.56#ibcon#wrote, iclass 26, count 0 2006.217.07:43:48.56#ibcon#about to read 3, iclass 26, count 0 2006.217.07:43:48.59#ibcon#read 3, iclass 26, count 0 2006.217.07:43:48.59#ibcon#about to read 4, iclass 26, count 0 2006.217.07:43:48.59#ibcon#read 4, iclass 26, count 0 2006.217.07:43:48.59#ibcon#about to read 5, iclass 26, count 0 2006.217.07:43:48.59#ibcon#read 5, iclass 26, count 0 2006.217.07:43:48.59#ibcon#about to read 6, iclass 26, count 0 2006.217.07:43:48.59#ibcon#read 6, iclass 26, count 0 2006.217.07:43:48.59#ibcon#end of sib2, iclass 26, count 0 2006.217.07:43:48.59#ibcon#*after write, iclass 26, count 0 2006.217.07:43:48.59#ibcon#*before return 0, iclass 26, count 0 2006.217.07:43:48.59#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.217.07:43:48.59#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.217.07:43:48.59#ibcon#about to clear, iclass 26 cls_cnt 0 2006.217.07:43:48.59#ibcon#cleared, iclass 26 cls_cnt 0 2006.217.07:43:48.59$vc4f8/valo=3,672.99 2006.217.07:43:48.59#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.217.07:43:48.59#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.217.07:43:48.59#ibcon#ireg 17 cls_cnt 0 2006.217.07:43:48.59#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.217.07:43:48.59#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.217.07:43:48.59#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.217.07:43:48.59#ibcon#enter wrdev, iclass 28, count 0 2006.217.07:43:48.59#ibcon#first serial, iclass 28, count 0 2006.217.07:43:48.59#ibcon#enter sib2, iclass 28, count 0 2006.217.07:43:48.59#ibcon#flushed, iclass 28, count 0 2006.217.07:43:48.59#ibcon#about to write, iclass 28, count 0 2006.217.07:43:48.59#ibcon#wrote, iclass 28, count 0 2006.217.07:43:48.59#ibcon#about to read 3, iclass 28, count 0 2006.217.07:43:48.62#ibcon#read 3, iclass 28, count 0 2006.217.07:43:48.62#ibcon#about to read 4, iclass 28, count 0 2006.217.07:43:48.62#ibcon#read 4, iclass 28, count 0 2006.217.07:43:48.62#ibcon#about to read 5, iclass 28, count 0 2006.217.07:43:48.62#ibcon#read 5, iclass 28, count 0 2006.217.07:43:48.62#ibcon#about to read 6, iclass 28, count 0 2006.217.07:43:48.62#ibcon#read 6, iclass 28, count 0 2006.217.07:43:48.62#ibcon#end of sib2, iclass 28, count 0 2006.217.07:43:48.62#ibcon#*mode == 0, iclass 28, count 0 2006.217.07:43:48.62#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.217.07:43:48.62#ibcon#[26=FRQ=03,672.99\r\n] 2006.217.07:43:48.62#ibcon#*before write, iclass 28, count 0 2006.217.07:43:48.62#ibcon#enter sib2, iclass 28, count 0 2006.217.07:43:48.62#ibcon#flushed, iclass 28, count 0 2006.217.07:43:48.62#ibcon#about to write, iclass 28, count 0 2006.217.07:43:48.62#ibcon#wrote, iclass 28, count 0 2006.217.07:43:48.62#ibcon#about to read 3, iclass 28, count 0 2006.217.07:43:48.66#ibcon#read 3, iclass 28, count 0 2006.217.07:43:48.66#ibcon#about to read 4, iclass 28, count 0 2006.217.07:43:48.66#ibcon#read 4, iclass 28, count 0 2006.217.07:43:48.66#ibcon#about to read 5, iclass 28, count 0 2006.217.07:43:48.66#ibcon#read 5, iclass 28, count 0 2006.217.07:43:48.66#ibcon#about to read 6, iclass 28, count 0 2006.217.07:43:48.66#ibcon#read 6, iclass 28, count 0 2006.217.07:43:48.66#ibcon#end of sib2, iclass 28, count 0 2006.217.07:43:48.66#ibcon#*after write, iclass 28, count 0 2006.217.07:43:48.66#ibcon#*before return 0, iclass 28, count 0 2006.217.07:43:48.66#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.217.07:43:48.66#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.217.07:43:48.66#ibcon#about to clear, iclass 28 cls_cnt 0 2006.217.07:43:48.66#ibcon#cleared, iclass 28 cls_cnt 0 2006.217.07:43:48.66$vc4f8/va=3,4 2006.217.07:43:48.66#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.217.07:43:48.66#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.217.07:43:48.66#ibcon#ireg 11 cls_cnt 2 2006.217.07:43:48.66#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.217.07:43:48.72#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.217.07:43:48.72#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.217.07:43:48.72#ibcon#enter wrdev, iclass 30, count 2 2006.217.07:43:48.72#ibcon#first serial, iclass 30, count 2 2006.217.07:43:48.72#ibcon#enter sib2, iclass 30, count 2 2006.217.07:43:48.72#ibcon#flushed, iclass 30, count 2 2006.217.07:43:48.72#ibcon#about to write, iclass 30, count 2 2006.217.07:43:48.72#ibcon#wrote, iclass 30, count 2 2006.217.07:43:48.72#ibcon#about to read 3, iclass 30, count 2 2006.217.07:43:48.73#ibcon#read 3, iclass 30, count 2 2006.217.07:43:48.73#ibcon#about to read 4, iclass 30, count 2 2006.217.07:43:48.73#ibcon#read 4, iclass 30, count 2 2006.217.07:43:48.73#ibcon#about to read 5, iclass 30, count 2 2006.217.07:43:48.73#ibcon#read 5, iclass 30, count 2 2006.217.07:43:48.73#ibcon#about to read 6, iclass 30, count 2 2006.217.07:43:48.73#ibcon#read 6, iclass 30, count 2 2006.217.07:43:48.73#ibcon#end of sib2, iclass 30, count 2 2006.217.07:43:48.73#ibcon#*mode == 0, iclass 30, count 2 2006.217.07:43:48.73#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.217.07:43:48.73#ibcon#[25=AT03-04\r\n] 2006.217.07:43:48.73#ibcon#*before write, iclass 30, count 2 2006.217.07:43:48.73#ibcon#enter sib2, iclass 30, count 2 2006.217.07:43:48.73#ibcon#flushed, iclass 30, count 2 2006.217.07:43:48.73#ibcon#about to write, iclass 30, count 2 2006.217.07:43:48.73#ibcon#wrote, iclass 30, count 2 2006.217.07:43:48.73#ibcon#about to read 3, iclass 30, count 2 2006.217.07:43:48.76#ibcon#read 3, iclass 30, count 2 2006.217.07:43:48.76#ibcon#about to read 4, iclass 30, count 2 2006.217.07:43:48.76#ibcon#read 4, iclass 30, count 2 2006.217.07:43:48.76#ibcon#about to read 5, iclass 30, count 2 2006.217.07:43:48.76#ibcon#read 5, iclass 30, count 2 2006.217.07:43:48.76#ibcon#about to read 6, iclass 30, count 2 2006.217.07:43:48.76#ibcon#read 6, iclass 30, count 2 2006.217.07:43:48.76#ibcon#end of sib2, iclass 30, count 2 2006.217.07:43:48.76#ibcon#*after write, iclass 30, count 2 2006.217.07:43:48.76#ibcon#*before return 0, iclass 30, count 2 2006.217.07:43:48.76#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.217.07:43:48.76#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.217.07:43:48.76#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.217.07:43:48.76#ibcon#ireg 7 cls_cnt 0 2006.217.07:43:48.76#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.217.07:43:48.88#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.217.07:43:48.88#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.217.07:43:48.88#ibcon#enter wrdev, iclass 30, count 0 2006.217.07:43:48.88#ibcon#first serial, iclass 30, count 0 2006.217.07:43:48.88#ibcon#enter sib2, iclass 30, count 0 2006.217.07:43:48.88#ibcon#flushed, iclass 30, count 0 2006.217.07:43:48.88#ibcon#about to write, iclass 30, count 0 2006.217.07:43:48.88#ibcon#wrote, iclass 30, count 0 2006.217.07:43:48.88#ibcon#about to read 3, iclass 30, count 0 2006.217.07:43:48.90#ibcon#read 3, iclass 30, count 0 2006.217.07:43:48.90#ibcon#about to read 4, iclass 30, count 0 2006.217.07:43:48.90#ibcon#read 4, iclass 30, count 0 2006.217.07:43:48.90#ibcon#about to read 5, iclass 30, count 0 2006.217.07:43:48.90#ibcon#read 5, iclass 30, count 0 2006.217.07:43:48.90#ibcon#about to read 6, iclass 30, count 0 2006.217.07:43:48.90#ibcon#read 6, iclass 30, count 0 2006.217.07:43:48.90#ibcon#end of sib2, iclass 30, count 0 2006.217.07:43:48.90#ibcon#*mode == 0, iclass 30, count 0 2006.217.07:43:48.90#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.217.07:43:48.90#ibcon#[25=USB\r\n] 2006.217.07:43:48.90#ibcon#*before write, iclass 30, count 0 2006.217.07:43:48.90#ibcon#enter sib2, iclass 30, count 0 2006.217.07:43:48.90#ibcon#flushed, iclass 30, count 0 2006.217.07:43:48.90#ibcon#about to write, iclass 30, count 0 2006.217.07:43:48.90#ibcon#wrote, iclass 30, count 0 2006.217.07:43:48.90#ibcon#about to read 3, iclass 30, count 0 2006.217.07:43:48.93#ibcon#read 3, iclass 30, count 0 2006.217.07:43:48.93#ibcon#about to read 4, iclass 30, count 0 2006.217.07:43:48.93#ibcon#read 4, iclass 30, count 0 2006.217.07:43:48.93#ibcon#about to read 5, iclass 30, count 0 2006.217.07:43:48.93#ibcon#read 5, iclass 30, count 0 2006.217.07:43:48.93#ibcon#about to read 6, iclass 30, count 0 2006.217.07:43:48.93#ibcon#read 6, iclass 30, count 0 2006.217.07:43:48.93#ibcon#end of sib2, iclass 30, count 0 2006.217.07:43:48.93#ibcon#*after write, iclass 30, count 0 2006.217.07:43:48.93#ibcon#*before return 0, iclass 30, count 0 2006.217.07:43:48.93#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.217.07:43:48.93#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.217.07:43:48.93#ibcon#about to clear, iclass 30 cls_cnt 0 2006.217.07:43:48.93#ibcon#cleared, iclass 30 cls_cnt 0 2006.217.07:43:48.93$vc4f8/valo=4,832.99 2006.217.07:43:48.93#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.217.07:43:48.93#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.217.07:43:48.93#ibcon#ireg 17 cls_cnt 0 2006.217.07:43:48.93#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.217.07:43:48.93#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.217.07:43:48.93#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.217.07:43:48.93#ibcon#enter wrdev, iclass 32, count 0 2006.217.07:43:48.93#ibcon#first serial, iclass 32, count 0 2006.217.07:43:48.93#ibcon#enter sib2, iclass 32, count 0 2006.217.07:43:48.93#ibcon#flushed, iclass 32, count 0 2006.217.07:43:48.93#ibcon#about to write, iclass 32, count 0 2006.217.07:43:48.93#ibcon#wrote, iclass 32, count 0 2006.217.07:43:48.93#ibcon#about to read 3, iclass 32, count 0 2006.217.07:43:48.96#ibcon#read 3, iclass 32, count 0 2006.217.07:43:48.96#ibcon#about to read 4, iclass 32, count 0 2006.217.07:43:48.96#ibcon#read 4, iclass 32, count 0 2006.217.07:43:48.96#ibcon#about to read 5, iclass 32, count 0 2006.217.07:43:48.96#ibcon#read 5, iclass 32, count 0 2006.217.07:43:48.96#ibcon#about to read 6, iclass 32, count 0 2006.217.07:43:48.96#ibcon#read 6, iclass 32, count 0 2006.217.07:43:48.96#ibcon#end of sib2, iclass 32, count 0 2006.217.07:43:48.96#ibcon#*mode == 0, iclass 32, count 0 2006.217.07:43:48.96#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.217.07:43:48.96#ibcon#[26=FRQ=04,832.99\r\n] 2006.217.07:43:48.96#ibcon#*before write, iclass 32, count 0 2006.217.07:43:48.96#ibcon#enter sib2, iclass 32, count 0 2006.217.07:43:48.96#ibcon#flushed, iclass 32, count 0 2006.217.07:43:48.96#ibcon#about to write, iclass 32, count 0 2006.217.07:43:48.96#ibcon#wrote, iclass 32, count 0 2006.217.07:43:48.96#ibcon#about to read 3, iclass 32, count 0 2006.217.07:43:49.00#ibcon#read 3, iclass 32, count 0 2006.217.07:43:49.00#ibcon#about to read 4, iclass 32, count 0 2006.217.07:43:49.00#ibcon#read 4, iclass 32, count 0 2006.217.07:43:49.00#ibcon#about to read 5, iclass 32, count 0 2006.217.07:43:49.00#ibcon#read 5, iclass 32, count 0 2006.217.07:43:49.00#ibcon#about to read 6, iclass 32, count 0 2006.217.07:43:49.00#ibcon#read 6, iclass 32, count 0 2006.217.07:43:49.00#ibcon#end of sib2, iclass 32, count 0 2006.217.07:43:49.00#ibcon#*after write, iclass 32, count 0 2006.217.07:43:49.00#ibcon#*before return 0, iclass 32, count 0 2006.217.07:43:49.00#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.217.07:43:49.00#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.217.07:43:49.00#ibcon#about to clear, iclass 32 cls_cnt 0 2006.217.07:43:49.00#ibcon#cleared, iclass 32 cls_cnt 0 2006.217.07:43:49.00$vc4f8/va=4,4 2006.217.07:43:49.00#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.217.07:43:49.00#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.217.07:43:49.00#ibcon#ireg 11 cls_cnt 2 2006.217.07:43:49.00#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.217.07:43:49.05#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.217.07:43:49.05#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.217.07:43:49.05#ibcon#enter wrdev, iclass 34, count 2 2006.217.07:43:49.05#ibcon#first serial, iclass 34, count 2 2006.217.07:43:49.05#ibcon#enter sib2, iclass 34, count 2 2006.217.07:43:49.05#ibcon#flushed, iclass 34, count 2 2006.217.07:43:49.05#ibcon#about to write, iclass 34, count 2 2006.217.07:43:49.05#ibcon#wrote, iclass 34, count 2 2006.217.07:43:49.05#ibcon#about to read 3, iclass 34, count 2 2006.217.07:43:49.07#ibcon#read 3, iclass 34, count 2 2006.217.07:43:49.07#ibcon#about to read 4, iclass 34, count 2 2006.217.07:43:49.07#ibcon#read 4, iclass 34, count 2 2006.217.07:43:49.07#ibcon#about to read 5, iclass 34, count 2 2006.217.07:43:49.07#ibcon#read 5, iclass 34, count 2 2006.217.07:43:49.07#ibcon#about to read 6, iclass 34, count 2 2006.217.07:43:49.07#ibcon#read 6, iclass 34, count 2 2006.217.07:43:49.07#ibcon#end of sib2, iclass 34, count 2 2006.217.07:43:49.07#ibcon#*mode == 0, iclass 34, count 2 2006.217.07:43:49.07#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.217.07:43:49.07#ibcon#[25=AT04-04\r\n] 2006.217.07:43:49.07#ibcon#*before write, iclass 34, count 2 2006.217.07:43:49.07#ibcon#enter sib2, iclass 34, count 2 2006.217.07:43:49.07#ibcon#flushed, iclass 34, count 2 2006.217.07:43:49.07#ibcon#about to write, iclass 34, count 2 2006.217.07:43:49.07#ibcon#wrote, iclass 34, count 2 2006.217.07:43:49.07#ibcon#about to read 3, iclass 34, count 2 2006.217.07:43:49.10#ibcon#read 3, iclass 34, count 2 2006.217.07:43:49.10#ibcon#about to read 4, iclass 34, count 2 2006.217.07:43:49.10#ibcon#read 4, iclass 34, count 2 2006.217.07:43:49.10#ibcon#about to read 5, iclass 34, count 2 2006.217.07:43:49.10#ibcon#read 5, iclass 34, count 2 2006.217.07:43:49.10#ibcon#about to read 6, iclass 34, count 2 2006.217.07:43:49.10#ibcon#read 6, iclass 34, count 2 2006.217.07:43:49.10#ibcon#end of sib2, iclass 34, count 2 2006.217.07:43:49.10#ibcon#*after write, iclass 34, count 2 2006.217.07:43:49.10#ibcon#*before return 0, iclass 34, count 2 2006.217.07:43:49.10#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.217.07:43:49.10#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.217.07:43:49.10#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.217.07:43:49.10#ibcon#ireg 7 cls_cnt 0 2006.217.07:43:49.10#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.217.07:43:49.22#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.217.07:43:49.22#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.217.07:43:49.22#ibcon#enter wrdev, iclass 34, count 0 2006.217.07:43:49.22#ibcon#first serial, iclass 34, count 0 2006.217.07:43:49.22#ibcon#enter sib2, iclass 34, count 0 2006.217.07:43:49.22#ibcon#flushed, iclass 34, count 0 2006.217.07:43:49.22#ibcon#about to write, iclass 34, count 0 2006.217.07:43:49.22#ibcon#wrote, iclass 34, count 0 2006.217.07:43:49.22#ibcon#about to read 3, iclass 34, count 0 2006.217.07:43:49.24#ibcon#read 3, iclass 34, count 0 2006.217.07:43:49.24#ibcon#about to read 4, iclass 34, count 0 2006.217.07:43:49.24#ibcon#read 4, iclass 34, count 0 2006.217.07:43:49.24#ibcon#about to read 5, iclass 34, count 0 2006.217.07:43:49.24#ibcon#read 5, iclass 34, count 0 2006.217.07:43:49.24#ibcon#about to read 6, iclass 34, count 0 2006.217.07:43:49.24#ibcon#read 6, iclass 34, count 0 2006.217.07:43:49.24#ibcon#end of sib2, iclass 34, count 0 2006.217.07:43:49.24#ibcon#*mode == 0, iclass 34, count 0 2006.217.07:43:49.24#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.217.07:43:49.24#ibcon#[25=USB\r\n] 2006.217.07:43:49.24#ibcon#*before write, iclass 34, count 0 2006.217.07:43:49.24#ibcon#enter sib2, iclass 34, count 0 2006.217.07:43:49.24#ibcon#flushed, iclass 34, count 0 2006.217.07:43:49.24#ibcon#about to write, iclass 34, count 0 2006.217.07:43:49.24#ibcon#wrote, iclass 34, count 0 2006.217.07:43:49.24#ibcon#about to read 3, iclass 34, count 0 2006.217.07:43:49.27#ibcon#read 3, iclass 34, count 0 2006.217.07:43:49.27#ibcon#about to read 4, iclass 34, count 0 2006.217.07:43:49.27#ibcon#read 4, iclass 34, count 0 2006.217.07:43:49.27#ibcon#about to read 5, iclass 34, count 0 2006.217.07:43:49.27#ibcon#read 5, iclass 34, count 0 2006.217.07:43:49.27#ibcon#about to read 6, iclass 34, count 0 2006.217.07:43:49.27#ibcon#read 6, iclass 34, count 0 2006.217.07:43:49.27#ibcon#end of sib2, iclass 34, count 0 2006.217.07:43:49.27#ibcon#*after write, iclass 34, count 0 2006.217.07:43:49.27#ibcon#*before return 0, iclass 34, count 0 2006.217.07:43:49.27#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.217.07:43:49.27#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.217.07:43:49.27#ibcon#about to clear, iclass 34 cls_cnt 0 2006.217.07:43:49.27#ibcon#cleared, iclass 34 cls_cnt 0 2006.217.07:43:49.27$vc4f8/valo=5,652.99 2006.217.07:43:49.27#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.217.07:43:49.27#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.217.07:43:49.27#ibcon#ireg 17 cls_cnt 0 2006.217.07:43:49.27#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.217.07:43:49.27#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.217.07:43:49.27#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.217.07:43:49.27#ibcon#enter wrdev, iclass 36, count 0 2006.217.07:43:49.27#ibcon#first serial, iclass 36, count 0 2006.217.07:43:49.27#ibcon#enter sib2, iclass 36, count 0 2006.217.07:43:49.27#ibcon#flushed, iclass 36, count 0 2006.217.07:43:49.27#ibcon#about to write, iclass 36, count 0 2006.217.07:43:49.27#ibcon#wrote, iclass 36, count 0 2006.217.07:43:49.27#ibcon#about to read 3, iclass 36, count 0 2006.217.07:43:49.29#ibcon#read 3, iclass 36, count 0 2006.217.07:43:49.29#ibcon#about to read 4, iclass 36, count 0 2006.217.07:43:49.29#ibcon#read 4, iclass 36, count 0 2006.217.07:43:49.29#ibcon#about to read 5, iclass 36, count 0 2006.217.07:43:49.29#ibcon#read 5, iclass 36, count 0 2006.217.07:43:49.29#ibcon#about to read 6, iclass 36, count 0 2006.217.07:43:49.29#ibcon#read 6, iclass 36, count 0 2006.217.07:43:49.29#ibcon#end of sib2, iclass 36, count 0 2006.217.07:43:49.29#ibcon#*mode == 0, iclass 36, count 0 2006.217.07:43:49.29#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.217.07:43:49.29#ibcon#[26=FRQ=05,652.99\r\n] 2006.217.07:43:49.29#ibcon#*before write, iclass 36, count 0 2006.217.07:43:49.29#ibcon#enter sib2, iclass 36, count 0 2006.217.07:43:49.29#ibcon#flushed, iclass 36, count 0 2006.217.07:43:49.29#ibcon#about to write, iclass 36, count 0 2006.217.07:43:49.29#ibcon#wrote, iclass 36, count 0 2006.217.07:43:49.29#ibcon#about to read 3, iclass 36, count 0 2006.217.07:43:49.33#ibcon#read 3, iclass 36, count 0 2006.217.07:43:49.33#ibcon#about to read 4, iclass 36, count 0 2006.217.07:43:49.33#ibcon#read 4, iclass 36, count 0 2006.217.07:43:49.33#ibcon#about to read 5, iclass 36, count 0 2006.217.07:43:49.33#ibcon#read 5, iclass 36, count 0 2006.217.07:43:49.33#ibcon#about to read 6, iclass 36, count 0 2006.217.07:43:49.33#ibcon#read 6, iclass 36, count 0 2006.217.07:43:49.33#ibcon#end of sib2, iclass 36, count 0 2006.217.07:43:49.33#ibcon#*after write, iclass 36, count 0 2006.217.07:43:49.33#ibcon#*before return 0, iclass 36, count 0 2006.217.07:43:49.33#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.217.07:43:49.33#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.217.07:43:49.33#ibcon#about to clear, iclass 36 cls_cnt 0 2006.217.07:43:49.33#ibcon#cleared, iclass 36 cls_cnt 0 2006.217.07:43:49.33$vc4f8/va=5,7 2006.217.07:43:49.33#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.217.07:43:49.33#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.217.07:43:49.33#ibcon#ireg 11 cls_cnt 2 2006.217.07:43:49.33#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.217.07:43:49.39#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.217.07:43:49.39#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.217.07:43:49.39#ibcon#enter wrdev, iclass 38, count 2 2006.217.07:43:49.39#ibcon#first serial, iclass 38, count 2 2006.217.07:43:49.39#ibcon#enter sib2, iclass 38, count 2 2006.217.07:43:49.39#ibcon#flushed, iclass 38, count 2 2006.217.07:43:49.39#ibcon#about to write, iclass 38, count 2 2006.217.07:43:49.39#ibcon#wrote, iclass 38, count 2 2006.217.07:43:49.39#ibcon#about to read 3, iclass 38, count 2 2006.217.07:43:49.41#ibcon#read 3, iclass 38, count 2 2006.217.07:43:49.41#ibcon#about to read 4, iclass 38, count 2 2006.217.07:43:49.41#ibcon#read 4, iclass 38, count 2 2006.217.07:43:49.41#ibcon#about to read 5, iclass 38, count 2 2006.217.07:43:49.41#ibcon#read 5, iclass 38, count 2 2006.217.07:43:49.41#ibcon#about to read 6, iclass 38, count 2 2006.217.07:43:49.41#ibcon#read 6, iclass 38, count 2 2006.217.07:43:49.41#ibcon#end of sib2, iclass 38, count 2 2006.217.07:43:49.41#ibcon#*mode == 0, iclass 38, count 2 2006.217.07:43:49.41#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.217.07:43:49.41#ibcon#[25=AT05-07\r\n] 2006.217.07:43:49.41#ibcon#*before write, iclass 38, count 2 2006.217.07:43:49.41#ibcon#enter sib2, iclass 38, count 2 2006.217.07:43:49.41#ibcon#flushed, iclass 38, count 2 2006.217.07:43:49.41#ibcon#about to write, iclass 38, count 2 2006.217.07:43:49.41#ibcon#wrote, iclass 38, count 2 2006.217.07:43:49.41#ibcon#about to read 3, iclass 38, count 2 2006.217.07:43:49.44#ibcon#read 3, iclass 38, count 2 2006.217.07:43:49.44#ibcon#about to read 4, iclass 38, count 2 2006.217.07:43:49.44#ibcon#read 4, iclass 38, count 2 2006.217.07:43:49.44#ibcon#about to read 5, iclass 38, count 2 2006.217.07:43:49.44#ibcon#read 5, iclass 38, count 2 2006.217.07:43:49.44#ibcon#about to read 6, iclass 38, count 2 2006.217.07:43:49.44#ibcon#read 6, iclass 38, count 2 2006.217.07:43:49.44#ibcon#end of sib2, iclass 38, count 2 2006.217.07:43:49.44#ibcon#*after write, iclass 38, count 2 2006.217.07:43:49.44#ibcon#*before return 0, iclass 38, count 2 2006.217.07:43:49.44#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.217.07:43:49.44#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.217.07:43:49.44#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.217.07:43:49.44#ibcon#ireg 7 cls_cnt 0 2006.217.07:43:49.44#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.217.07:43:49.56#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.217.07:43:49.56#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.217.07:43:49.56#ibcon#enter wrdev, iclass 38, count 0 2006.217.07:43:49.56#ibcon#first serial, iclass 38, count 0 2006.217.07:43:49.56#ibcon#enter sib2, iclass 38, count 0 2006.217.07:43:49.56#ibcon#flushed, iclass 38, count 0 2006.217.07:43:49.56#ibcon#about to write, iclass 38, count 0 2006.217.07:43:49.56#ibcon#wrote, iclass 38, count 0 2006.217.07:43:49.56#ibcon#about to read 3, iclass 38, count 0 2006.217.07:43:49.58#ibcon#read 3, iclass 38, count 0 2006.217.07:43:49.58#ibcon#about to read 4, iclass 38, count 0 2006.217.07:43:49.58#ibcon#read 4, iclass 38, count 0 2006.217.07:43:49.58#ibcon#about to read 5, iclass 38, count 0 2006.217.07:43:49.58#ibcon#read 5, iclass 38, count 0 2006.217.07:43:49.58#ibcon#about to read 6, iclass 38, count 0 2006.217.07:43:49.58#ibcon#read 6, iclass 38, count 0 2006.217.07:43:49.58#ibcon#end of sib2, iclass 38, count 0 2006.217.07:43:49.58#ibcon#*mode == 0, iclass 38, count 0 2006.217.07:43:49.58#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.217.07:43:49.58#ibcon#[25=USB\r\n] 2006.217.07:43:49.58#ibcon#*before write, iclass 38, count 0 2006.217.07:43:49.58#ibcon#enter sib2, iclass 38, count 0 2006.217.07:43:49.58#ibcon#flushed, iclass 38, count 0 2006.217.07:43:49.58#ibcon#about to write, iclass 38, count 0 2006.217.07:43:49.58#ibcon#wrote, iclass 38, count 0 2006.217.07:43:49.58#ibcon#about to read 3, iclass 38, count 0 2006.217.07:43:49.61#ibcon#read 3, iclass 38, count 0 2006.217.07:43:49.61#ibcon#about to read 4, iclass 38, count 0 2006.217.07:43:49.61#ibcon#read 4, iclass 38, count 0 2006.217.07:43:49.61#ibcon#about to read 5, iclass 38, count 0 2006.217.07:43:49.61#ibcon#read 5, iclass 38, count 0 2006.217.07:43:49.61#ibcon#about to read 6, iclass 38, count 0 2006.217.07:43:49.61#ibcon#read 6, iclass 38, count 0 2006.217.07:43:49.61#ibcon#end of sib2, iclass 38, count 0 2006.217.07:43:49.61#ibcon#*after write, iclass 38, count 0 2006.217.07:43:49.61#ibcon#*before return 0, iclass 38, count 0 2006.217.07:43:49.61#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.217.07:43:49.61#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.217.07:43:49.61#ibcon#about to clear, iclass 38 cls_cnt 0 2006.217.07:43:49.61#ibcon#cleared, iclass 38 cls_cnt 0 2006.217.07:43:49.61$vc4f8/valo=6,772.99 2006.217.07:43:49.61#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.217.07:43:49.61#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.217.07:43:49.61#ibcon#ireg 17 cls_cnt 0 2006.217.07:43:49.61#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.217.07:43:49.61#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.217.07:43:49.61#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.217.07:43:49.61#ibcon#enter wrdev, iclass 40, count 0 2006.217.07:43:49.61#ibcon#first serial, iclass 40, count 0 2006.217.07:43:49.61#ibcon#enter sib2, iclass 40, count 0 2006.217.07:43:49.61#ibcon#flushed, iclass 40, count 0 2006.217.07:43:49.61#ibcon#about to write, iclass 40, count 0 2006.217.07:43:49.61#ibcon#wrote, iclass 40, count 0 2006.217.07:43:49.61#ibcon#about to read 3, iclass 40, count 0 2006.217.07:43:49.63#ibcon#read 3, iclass 40, count 0 2006.217.07:43:49.63#ibcon#about to read 4, iclass 40, count 0 2006.217.07:43:49.63#ibcon#read 4, iclass 40, count 0 2006.217.07:43:49.63#ibcon#about to read 5, iclass 40, count 0 2006.217.07:43:49.63#ibcon#read 5, iclass 40, count 0 2006.217.07:43:49.63#ibcon#about to read 6, iclass 40, count 0 2006.217.07:43:49.63#ibcon#read 6, iclass 40, count 0 2006.217.07:43:49.63#ibcon#end of sib2, iclass 40, count 0 2006.217.07:43:49.63#ibcon#*mode == 0, iclass 40, count 0 2006.217.07:43:49.63#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.217.07:43:49.63#ibcon#[26=FRQ=06,772.99\r\n] 2006.217.07:43:49.63#ibcon#*before write, iclass 40, count 0 2006.217.07:43:49.63#ibcon#enter sib2, iclass 40, count 0 2006.217.07:43:49.63#ibcon#flushed, iclass 40, count 0 2006.217.07:43:49.63#ibcon#about to write, iclass 40, count 0 2006.217.07:43:49.63#ibcon#wrote, iclass 40, count 0 2006.217.07:43:49.63#ibcon#about to read 3, iclass 40, count 0 2006.217.07:43:49.67#ibcon#read 3, iclass 40, count 0 2006.217.07:43:49.67#ibcon#about to read 4, iclass 40, count 0 2006.217.07:43:49.67#ibcon#read 4, iclass 40, count 0 2006.217.07:43:49.67#ibcon#about to read 5, iclass 40, count 0 2006.217.07:43:49.67#ibcon#read 5, iclass 40, count 0 2006.217.07:43:49.67#ibcon#about to read 6, iclass 40, count 0 2006.217.07:43:49.67#ibcon#read 6, iclass 40, count 0 2006.217.07:43:49.67#ibcon#end of sib2, iclass 40, count 0 2006.217.07:43:49.67#ibcon#*after write, iclass 40, count 0 2006.217.07:43:49.67#ibcon#*before return 0, iclass 40, count 0 2006.217.07:43:49.67#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.217.07:43:49.67#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.217.07:43:49.67#ibcon#about to clear, iclass 40 cls_cnt 0 2006.217.07:43:49.67#ibcon#cleared, iclass 40 cls_cnt 0 2006.217.07:43:49.67$vc4f8/va=6,6 2006.217.07:43:49.67#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.217.07:43:49.67#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.217.07:43:49.67#ibcon#ireg 11 cls_cnt 2 2006.217.07:43:49.67#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.217.07:43:49.74#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.217.07:43:49.74#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.217.07:43:49.74#ibcon#enter wrdev, iclass 4, count 2 2006.217.07:43:49.74#ibcon#first serial, iclass 4, count 2 2006.217.07:43:49.74#ibcon#enter sib2, iclass 4, count 2 2006.217.07:43:49.74#ibcon#flushed, iclass 4, count 2 2006.217.07:43:49.74#ibcon#about to write, iclass 4, count 2 2006.217.07:43:49.74#ibcon#wrote, iclass 4, count 2 2006.217.07:43:49.74#ibcon#about to read 3, iclass 4, count 2 2006.217.07:43:49.75#ibcon#read 3, iclass 4, count 2 2006.217.07:43:49.75#ibcon#about to read 4, iclass 4, count 2 2006.217.07:43:49.75#ibcon#read 4, iclass 4, count 2 2006.217.07:43:49.75#ibcon#about to read 5, iclass 4, count 2 2006.217.07:43:49.75#ibcon#read 5, iclass 4, count 2 2006.217.07:43:49.75#ibcon#about to read 6, iclass 4, count 2 2006.217.07:43:49.75#ibcon#read 6, iclass 4, count 2 2006.217.07:43:49.75#ibcon#end of sib2, iclass 4, count 2 2006.217.07:43:49.75#ibcon#*mode == 0, iclass 4, count 2 2006.217.07:43:49.75#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.217.07:43:49.75#ibcon#[25=AT06-06\r\n] 2006.217.07:43:49.75#ibcon#*before write, iclass 4, count 2 2006.217.07:43:49.75#ibcon#enter sib2, iclass 4, count 2 2006.217.07:43:49.75#ibcon#flushed, iclass 4, count 2 2006.217.07:43:49.75#ibcon#about to write, iclass 4, count 2 2006.217.07:43:49.75#ibcon#wrote, iclass 4, count 2 2006.217.07:43:49.75#ibcon#about to read 3, iclass 4, count 2 2006.217.07:43:49.78#ibcon#read 3, iclass 4, count 2 2006.217.07:43:49.78#ibcon#about to read 4, iclass 4, count 2 2006.217.07:43:49.78#ibcon#read 4, iclass 4, count 2 2006.217.07:43:49.78#ibcon#about to read 5, iclass 4, count 2 2006.217.07:43:49.78#ibcon#read 5, iclass 4, count 2 2006.217.07:43:49.78#ibcon#about to read 6, iclass 4, count 2 2006.217.07:43:49.78#ibcon#read 6, iclass 4, count 2 2006.217.07:43:49.78#ibcon#end of sib2, iclass 4, count 2 2006.217.07:43:49.78#ibcon#*after write, iclass 4, count 2 2006.217.07:43:49.78#ibcon#*before return 0, iclass 4, count 2 2006.217.07:43:49.78#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.217.07:43:49.78#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.217.07:43:49.78#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.217.07:43:49.78#ibcon#ireg 7 cls_cnt 0 2006.217.07:43:49.78#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.217.07:43:49.90#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.217.07:43:49.90#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.217.07:43:49.90#ibcon#enter wrdev, iclass 4, count 0 2006.217.07:43:49.90#ibcon#first serial, iclass 4, count 0 2006.217.07:43:49.90#ibcon#enter sib2, iclass 4, count 0 2006.217.07:43:49.90#ibcon#flushed, iclass 4, count 0 2006.217.07:43:49.90#ibcon#about to write, iclass 4, count 0 2006.217.07:43:49.90#ibcon#wrote, iclass 4, count 0 2006.217.07:43:49.90#ibcon#about to read 3, iclass 4, count 0 2006.217.07:43:49.92#ibcon#read 3, iclass 4, count 0 2006.217.07:43:49.92#ibcon#about to read 4, iclass 4, count 0 2006.217.07:43:49.92#ibcon#read 4, iclass 4, count 0 2006.217.07:43:49.92#ibcon#about to read 5, iclass 4, count 0 2006.217.07:43:49.92#ibcon#read 5, iclass 4, count 0 2006.217.07:43:49.92#ibcon#about to read 6, iclass 4, count 0 2006.217.07:43:49.92#ibcon#read 6, iclass 4, count 0 2006.217.07:43:49.92#ibcon#end of sib2, iclass 4, count 0 2006.217.07:43:49.92#ibcon#*mode == 0, iclass 4, count 0 2006.217.07:43:49.92#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.217.07:43:49.92#ibcon#[25=USB\r\n] 2006.217.07:43:49.92#ibcon#*before write, iclass 4, count 0 2006.217.07:43:49.92#ibcon#enter sib2, iclass 4, count 0 2006.217.07:43:49.92#ibcon#flushed, iclass 4, count 0 2006.217.07:43:49.92#ibcon#about to write, iclass 4, count 0 2006.217.07:43:49.92#ibcon#wrote, iclass 4, count 0 2006.217.07:43:49.92#ibcon#about to read 3, iclass 4, count 0 2006.217.07:43:49.95#ibcon#read 3, iclass 4, count 0 2006.217.07:43:49.95#ibcon#about to read 4, iclass 4, count 0 2006.217.07:43:49.95#ibcon#read 4, iclass 4, count 0 2006.217.07:43:49.95#ibcon#about to read 5, iclass 4, count 0 2006.217.07:43:49.95#ibcon#read 5, iclass 4, count 0 2006.217.07:43:49.95#ibcon#about to read 6, iclass 4, count 0 2006.217.07:43:49.95#ibcon#read 6, iclass 4, count 0 2006.217.07:43:49.95#ibcon#end of sib2, iclass 4, count 0 2006.217.07:43:49.95#ibcon#*after write, iclass 4, count 0 2006.217.07:43:49.95#ibcon#*before return 0, iclass 4, count 0 2006.217.07:43:49.95#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.217.07:43:49.95#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.217.07:43:49.95#ibcon#about to clear, iclass 4 cls_cnt 0 2006.217.07:43:49.95#ibcon#cleared, iclass 4 cls_cnt 0 2006.217.07:43:49.95$vc4f8/valo=7,832.99 2006.217.07:43:49.95#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.217.07:43:49.95#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.217.07:43:49.95#ibcon#ireg 17 cls_cnt 0 2006.217.07:43:49.95#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.217.07:43:49.95#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.217.07:43:49.95#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.217.07:43:49.95#ibcon#enter wrdev, iclass 6, count 0 2006.217.07:43:49.95#ibcon#first serial, iclass 6, count 0 2006.217.07:43:49.95#ibcon#enter sib2, iclass 6, count 0 2006.217.07:43:49.95#ibcon#flushed, iclass 6, count 0 2006.217.07:43:49.95#ibcon#about to write, iclass 6, count 0 2006.217.07:43:49.95#ibcon#wrote, iclass 6, count 0 2006.217.07:43:49.95#ibcon#about to read 3, iclass 6, count 0 2006.217.07:43:49.97#ibcon#read 3, iclass 6, count 0 2006.217.07:43:49.97#ibcon#about to read 4, iclass 6, count 0 2006.217.07:43:49.97#ibcon#read 4, iclass 6, count 0 2006.217.07:43:49.97#ibcon#about to read 5, iclass 6, count 0 2006.217.07:43:49.97#ibcon#read 5, iclass 6, count 0 2006.217.07:43:49.97#ibcon#about to read 6, iclass 6, count 0 2006.217.07:43:49.97#ibcon#read 6, iclass 6, count 0 2006.217.07:43:49.97#ibcon#end of sib2, iclass 6, count 0 2006.217.07:43:49.97#ibcon#*mode == 0, iclass 6, count 0 2006.217.07:43:49.97#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.217.07:43:49.97#ibcon#[26=FRQ=07,832.99\r\n] 2006.217.07:43:49.97#ibcon#*before write, iclass 6, count 0 2006.217.07:43:49.97#ibcon#enter sib2, iclass 6, count 0 2006.217.07:43:49.97#ibcon#flushed, iclass 6, count 0 2006.217.07:43:49.97#ibcon#about to write, iclass 6, count 0 2006.217.07:43:49.97#ibcon#wrote, iclass 6, count 0 2006.217.07:43:49.97#ibcon#about to read 3, iclass 6, count 0 2006.217.07:43:50.01#ibcon#read 3, iclass 6, count 0 2006.217.07:43:50.01#ibcon#about to read 4, iclass 6, count 0 2006.217.07:43:50.01#ibcon#read 4, iclass 6, count 0 2006.217.07:43:50.01#ibcon#about to read 5, iclass 6, count 0 2006.217.07:43:50.01#ibcon#read 5, iclass 6, count 0 2006.217.07:43:50.01#ibcon#about to read 6, iclass 6, count 0 2006.217.07:43:50.01#ibcon#read 6, iclass 6, count 0 2006.217.07:43:50.01#ibcon#end of sib2, iclass 6, count 0 2006.217.07:43:50.01#ibcon#*after write, iclass 6, count 0 2006.217.07:43:50.01#ibcon#*before return 0, iclass 6, count 0 2006.217.07:43:50.01#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.217.07:43:50.01#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.217.07:43:50.01#ibcon#about to clear, iclass 6 cls_cnt 0 2006.217.07:43:50.01#ibcon#cleared, iclass 6 cls_cnt 0 2006.217.07:43:50.01$vc4f8/va=7,6 2006.217.07:43:50.01#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.217.07:43:50.01#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.217.07:43:50.01#ibcon#ireg 11 cls_cnt 2 2006.217.07:43:50.01#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.217.07:43:50.07#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.217.07:43:50.07#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.217.07:43:50.07#ibcon#enter wrdev, iclass 10, count 2 2006.217.07:43:50.07#ibcon#first serial, iclass 10, count 2 2006.217.07:43:50.07#ibcon#enter sib2, iclass 10, count 2 2006.217.07:43:50.07#ibcon#flushed, iclass 10, count 2 2006.217.07:43:50.07#ibcon#about to write, iclass 10, count 2 2006.217.07:43:50.07#ibcon#wrote, iclass 10, count 2 2006.217.07:43:50.07#ibcon#about to read 3, iclass 10, count 2 2006.217.07:43:50.09#ibcon#read 3, iclass 10, count 2 2006.217.07:43:50.09#ibcon#about to read 4, iclass 10, count 2 2006.217.07:43:50.09#ibcon#read 4, iclass 10, count 2 2006.217.07:43:50.09#ibcon#about to read 5, iclass 10, count 2 2006.217.07:43:50.09#ibcon#read 5, iclass 10, count 2 2006.217.07:43:50.09#ibcon#about to read 6, iclass 10, count 2 2006.217.07:43:50.09#ibcon#read 6, iclass 10, count 2 2006.217.07:43:50.09#ibcon#end of sib2, iclass 10, count 2 2006.217.07:43:50.09#ibcon#*mode == 0, iclass 10, count 2 2006.217.07:43:50.09#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.217.07:43:50.09#ibcon#[25=AT07-06\r\n] 2006.217.07:43:50.09#ibcon#*before write, iclass 10, count 2 2006.217.07:43:50.09#ibcon#enter sib2, iclass 10, count 2 2006.217.07:43:50.09#ibcon#flushed, iclass 10, count 2 2006.217.07:43:50.09#ibcon#about to write, iclass 10, count 2 2006.217.07:43:50.09#ibcon#wrote, iclass 10, count 2 2006.217.07:43:50.09#ibcon#about to read 3, iclass 10, count 2 2006.217.07:43:50.12#ibcon#read 3, iclass 10, count 2 2006.217.07:43:50.12#ibcon#about to read 4, iclass 10, count 2 2006.217.07:43:50.12#ibcon#read 4, iclass 10, count 2 2006.217.07:43:50.12#ibcon#about to read 5, iclass 10, count 2 2006.217.07:43:50.12#ibcon#read 5, iclass 10, count 2 2006.217.07:43:50.12#ibcon#about to read 6, iclass 10, count 2 2006.217.07:43:50.12#ibcon#read 6, iclass 10, count 2 2006.217.07:43:50.12#ibcon#end of sib2, iclass 10, count 2 2006.217.07:43:50.12#ibcon#*after write, iclass 10, count 2 2006.217.07:43:50.12#ibcon#*before return 0, iclass 10, count 2 2006.217.07:43:50.12#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.217.07:43:50.12#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.217.07:43:50.12#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.217.07:43:50.12#ibcon#ireg 7 cls_cnt 0 2006.217.07:43:50.12#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.217.07:43:50.24#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.217.07:43:50.24#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.217.07:43:50.24#ibcon#enter wrdev, iclass 10, count 0 2006.217.07:43:50.24#ibcon#first serial, iclass 10, count 0 2006.217.07:43:50.24#ibcon#enter sib2, iclass 10, count 0 2006.217.07:43:50.24#ibcon#flushed, iclass 10, count 0 2006.217.07:43:50.24#ibcon#about to write, iclass 10, count 0 2006.217.07:43:50.24#ibcon#wrote, iclass 10, count 0 2006.217.07:43:50.24#ibcon#about to read 3, iclass 10, count 0 2006.217.07:43:50.26#ibcon#read 3, iclass 10, count 0 2006.217.07:43:50.26#ibcon#about to read 4, iclass 10, count 0 2006.217.07:43:50.26#ibcon#read 4, iclass 10, count 0 2006.217.07:43:50.26#ibcon#about to read 5, iclass 10, count 0 2006.217.07:43:50.26#ibcon#read 5, iclass 10, count 0 2006.217.07:43:50.26#ibcon#about to read 6, iclass 10, count 0 2006.217.07:43:50.26#ibcon#read 6, iclass 10, count 0 2006.217.07:43:50.26#ibcon#end of sib2, iclass 10, count 0 2006.217.07:43:50.26#ibcon#*mode == 0, iclass 10, count 0 2006.217.07:43:50.26#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.217.07:43:50.26#ibcon#[25=USB\r\n] 2006.217.07:43:50.26#ibcon#*before write, iclass 10, count 0 2006.217.07:43:50.26#ibcon#enter sib2, iclass 10, count 0 2006.217.07:43:50.26#ibcon#flushed, iclass 10, count 0 2006.217.07:43:50.26#ibcon#about to write, iclass 10, count 0 2006.217.07:43:50.26#ibcon#wrote, iclass 10, count 0 2006.217.07:43:50.26#ibcon#about to read 3, iclass 10, count 0 2006.217.07:43:50.29#ibcon#read 3, iclass 10, count 0 2006.217.07:43:50.29#ibcon#about to read 4, iclass 10, count 0 2006.217.07:43:50.29#ibcon#read 4, iclass 10, count 0 2006.217.07:43:50.29#ibcon#about to read 5, iclass 10, count 0 2006.217.07:43:50.29#ibcon#read 5, iclass 10, count 0 2006.217.07:43:50.29#ibcon#about to read 6, iclass 10, count 0 2006.217.07:43:50.29#ibcon#read 6, iclass 10, count 0 2006.217.07:43:50.29#ibcon#end of sib2, iclass 10, count 0 2006.217.07:43:50.29#ibcon#*after write, iclass 10, count 0 2006.217.07:43:50.29#ibcon#*before return 0, iclass 10, count 0 2006.217.07:43:50.29#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.217.07:43:50.29#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.217.07:43:50.29#ibcon#about to clear, iclass 10 cls_cnt 0 2006.217.07:43:50.29#ibcon#cleared, iclass 10 cls_cnt 0 2006.217.07:43:50.29$vc4f8/valo=8,852.99 2006.217.07:43:50.29#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.217.07:43:50.29#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.217.07:43:50.29#ibcon#ireg 17 cls_cnt 0 2006.217.07:43:50.29#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.217.07:43:50.29#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.217.07:43:50.29#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.217.07:43:50.29#ibcon#enter wrdev, iclass 12, count 0 2006.217.07:43:50.29#ibcon#first serial, iclass 12, count 0 2006.217.07:43:50.29#ibcon#enter sib2, iclass 12, count 0 2006.217.07:43:50.29#ibcon#flushed, iclass 12, count 0 2006.217.07:43:50.29#ibcon#about to write, iclass 12, count 0 2006.217.07:43:50.29#ibcon#wrote, iclass 12, count 0 2006.217.07:43:50.29#ibcon#about to read 3, iclass 12, count 0 2006.217.07:43:50.31#ibcon#read 3, iclass 12, count 0 2006.217.07:43:50.31#ibcon#about to read 4, iclass 12, count 0 2006.217.07:43:50.31#ibcon#read 4, iclass 12, count 0 2006.217.07:43:50.31#ibcon#about to read 5, iclass 12, count 0 2006.217.07:43:50.31#ibcon#read 5, iclass 12, count 0 2006.217.07:43:50.31#ibcon#about to read 6, iclass 12, count 0 2006.217.07:43:50.31#ibcon#read 6, iclass 12, count 0 2006.217.07:43:50.31#ibcon#end of sib2, iclass 12, count 0 2006.217.07:43:50.31#ibcon#*mode == 0, iclass 12, count 0 2006.217.07:43:50.31#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.217.07:43:50.31#ibcon#[26=FRQ=08,852.99\r\n] 2006.217.07:43:50.31#ibcon#*before write, iclass 12, count 0 2006.217.07:43:50.31#ibcon#enter sib2, iclass 12, count 0 2006.217.07:43:50.31#ibcon#flushed, iclass 12, count 0 2006.217.07:43:50.31#ibcon#about to write, iclass 12, count 0 2006.217.07:43:50.31#ibcon#wrote, iclass 12, count 0 2006.217.07:43:50.31#ibcon#about to read 3, iclass 12, count 0 2006.217.07:43:50.35#ibcon#read 3, iclass 12, count 0 2006.217.07:43:50.35#ibcon#about to read 4, iclass 12, count 0 2006.217.07:43:50.35#ibcon#read 4, iclass 12, count 0 2006.217.07:43:50.35#ibcon#about to read 5, iclass 12, count 0 2006.217.07:43:50.35#ibcon#read 5, iclass 12, count 0 2006.217.07:43:50.35#ibcon#about to read 6, iclass 12, count 0 2006.217.07:43:50.35#ibcon#read 6, iclass 12, count 0 2006.217.07:43:50.35#ibcon#end of sib2, iclass 12, count 0 2006.217.07:43:50.35#ibcon#*after write, iclass 12, count 0 2006.217.07:43:50.35#ibcon#*before return 0, iclass 12, count 0 2006.217.07:43:50.35#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.217.07:43:50.35#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.217.07:43:50.35#ibcon#about to clear, iclass 12 cls_cnt 0 2006.217.07:43:50.35#ibcon#cleared, iclass 12 cls_cnt 0 2006.217.07:43:50.35$vc4f8/va=8,7 2006.217.07:43:50.35#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.217.07:43:50.35#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.217.07:43:50.35#ibcon#ireg 11 cls_cnt 2 2006.217.07:43:50.35#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.217.07:43:50.41#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.217.07:43:50.41#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.217.07:43:50.41#ibcon#enter wrdev, iclass 14, count 2 2006.217.07:43:50.41#ibcon#first serial, iclass 14, count 2 2006.217.07:43:50.41#ibcon#enter sib2, iclass 14, count 2 2006.217.07:43:50.41#ibcon#flushed, iclass 14, count 2 2006.217.07:43:50.41#ibcon#about to write, iclass 14, count 2 2006.217.07:43:50.41#ibcon#wrote, iclass 14, count 2 2006.217.07:43:50.41#ibcon#about to read 3, iclass 14, count 2 2006.217.07:43:50.43#ibcon#read 3, iclass 14, count 2 2006.217.07:43:50.43#ibcon#about to read 4, iclass 14, count 2 2006.217.07:43:50.43#ibcon#read 4, iclass 14, count 2 2006.217.07:43:50.43#ibcon#about to read 5, iclass 14, count 2 2006.217.07:43:50.43#ibcon#read 5, iclass 14, count 2 2006.217.07:43:50.43#ibcon#about to read 6, iclass 14, count 2 2006.217.07:43:50.43#ibcon#read 6, iclass 14, count 2 2006.217.07:43:50.43#ibcon#end of sib2, iclass 14, count 2 2006.217.07:43:50.43#ibcon#*mode == 0, iclass 14, count 2 2006.217.07:43:50.43#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.217.07:43:50.43#ibcon#[25=AT08-07\r\n] 2006.217.07:43:50.43#ibcon#*before write, iclass 14, count 2 2006.217.07:43:50.43#ibcon#enter sib2, iclass 14, count 2 2006.217.07:43:50.43#ibcon#flushed, iclass 14, count 2 2006.217.07:43:50.43#ibcon#about to write, iclass 14, count 2 2006.217.07:43:50.43#ibcon#wrote, iclass 14, count 2 2006.217.07:43:50.43#ibcon#about to read 3, iclass 14, count 2 2006.217.07:43:50.46#ibcon#read 3, iclass 14, count 2 2006.217.07:43:50.46#ibcon#about to read 4, iclass 14, count 2 2006.217.07:43:50.46#ibcon#read 4, iclass 14, count 2 2006.217.07:43:50.46#ibcon#about to read 5, iclass 14, count 2 2006.217.07:43:50.46#ibcon#read 5, iclass 14, count 2 2006.217.07:43:50.46#ibcon#about to read 6, iclass 14, count 2 2006.217.07:43:50.46#ibcon#read 6, iclass 14, count 2 2006.217.07:43:50.46#ibcon#end of sib2, iclass 14, count 2 2006.217.07:43:50.46#ibcon#*after write, iclass 14, count 2 2006.217.07:43:50.46#ibcon#*before return 0, iclass 14, count 2 2006.217.07:43:50.46#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.217.07:43:50.46#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.217.07:43:50.46#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.217.07:43:50.46#ibcon#ireg 7 cls_cnt 0 2006.217.07:43:50.46#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.217.07:43:50.58#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.217.07:43:50.58#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.217.07:43:50.58#ibcon#enter wrdev, iclass 14, count 0 2006.217.07:43:50.58#ibcon#first serial, iclass 14, count 0 2006.217.07:43:50.58#ibcon#enter sib2, iclass 14, count 0 2006.217.07:43:50.58#ibcon#flushed, iclass 14, count 0 2006.217.07:43:50.58#ibcon#about to write, iclass 14, count 0 2006.217.07:43:50.58#ibcon#wrote, iclass 14, count 0 2006.217.07:43:50.58#ibcon#about to read 3, iclass 14, count 0 2006.217.07:43:50.60#ibcon#read 3, iclass 14, count 0 2006.217.07:43:50.60#ibcon#about to read 4, iclass 14, count 0 2006.217.07:43:50.60#ibcon#read 4, iclass 14, count 0 2006.217.07:43:50.60#ibcon#about to read 5, iclass 14, count 0 2006.217.07:43:50.60#ibcon#read 5, iclass 14, count 0 2006.217.07:43:50.60#ibcon#about to read 6, iclass 14, count 0 2006.217.07:43:50.60#ibcon#read 6, iclass 14, count 0 2006.217.07:43:50.60#ibcon#end of sib2, iclass 14, count 0 2006.217.07:43:50.60#ibcon#*mode == 0, iclass 14, count 0 2006.217.07:43:50.60#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.217.07:43:50.60#ibcon#[25=USB\r\n] 2006.217.07:43:50.60#ibcon#*before write, iclass 14, count 0 2006.217.07:43:50.60#ibcon#enter sib2, iclass 14, count 0 2006.217.07:43:50.60#ibcon#flushed, iclass 14, count 0 2006.217.07:43:50.60#ibcon#about to write, iclass 14, count 0 2006.217.07:43:50.60#ibcon#wrote, iclass 14, count 0 2006.217.07:43:50.60#ibcon#about to read 3, iclass 14, count 0 2006.217.07:43:50.63#ibcon#read 3, iclass 14, count 0 2006.217.07:43:50.63#ibcon#about to read 4, iclass 14, count 0 2006.217.07:43:50.63#ibcon#read 4, iclass 14, count 0 2006.217.07:43:50.63#ibcon#about to read 5, iclass 14, count 0 2006.217.07:43:50.63#ibcon#read 5, iclass 14, count 0 2006.217.07:43:50.63#ibcon#about to read 6, iclass 14, count 0 2006.217.07:43:50.63#ibcon#read 6, iclass 14, count 0 2006.217.07:43:50.63#ibcon#end of sib2, iclass 14, count 0 2006.217.07:43:50.63#ibcon#*after write, iclass 14, count 0 2006.217.07:43:50.63#ibcon#*before return 0, iclass 14, count 0 2006.217.07:43:50.63#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.217.07:43:50.63#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.217.07:43:50.63#ibcon#about to clear, iclass 14 cls_cnt 0 2006.217.07:43:50.63#ibcon#cleared, iclass 14 cls_cnt 0 2006.217.07:43:50.63$vc4f8/vblo=1,632.99 2006.217.07:43:50.63#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.217.07:43:50.63#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.217.07:43:50.63#ibcon#ireg 17 cls_cnt 0 2006.217.07:43:50.63#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.217.07:43:50.63#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.217.07:43:50.63#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.217.07:43:50.63#ibcon#enter wrdev, iclass 16, count 0 2006.217.07:43:50.63#ibcon#first serial, iclass 16, count 0 2006.217.07:43:50.63#ibcon#enter sib2, iclass 16, count 0 2006.217.07:43:50.63#ibcon#flushed, iclass 16, count 0 2006.217.07:43:50.63#ibcon#about to write, iclass 16, count 0 2006.217.07:43:50.63#ibcon#wrote, iclass 16, count 0 2006.217.07:43:50.63#ibcon#about to read 3, iclass 16, count 0 2006.217.07:43:50.66#ibcon#read 3, iclass 16, count 0 2006.217.07:43:50.66#ibcon#about to read 4, iclass 16, count 0 2006.217.07:43:50.66#ibcon#read 4, iclass 16, count 0 2006.217.07:43:50.66#ibcon#about to read 5, iclass 16, count 0 2006.217.07:43:50.66#ibcon#read 5, iclass 16, count 0 2006.217.07:43:50.66#ibcon#about to read 6, iclass 16, count 0 2006.217.07:43:50.66#ibcon#read 6, iclass 16, count 0 2006.217.07:43:50.66#ibcon#end of sib2, iclass 16, count 0 2006.217.07:43:50.66#ibcon#*mode == 0, iclass 16, count 0 2006.217.07:43:50.66#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.217.07:43:50.66#ibcon#[28=FRQ=01,632.99\r\n] 2006.217.07:43:50.66#ibcon#*before write, iclass 16, count 0 2006.217.07:43:50.66#ibcon#enter sib2, iclass 16, count 0 2006.217.07:43:50.66#ibcon#flushed, iclass 16, count 0 2006.217.07:43:50.66#ibcon#about to write, iclass 16, count 0 2006.217.07:43:50.66#ibcon#wrote, iclass 16, count 0 2006.217.07:43:50.66#ibcon#about to read 3, iclass 16, count 0 2006.217.07:43:50.70#ibcon#read 3, iclass 16, count 0 2006.217.07:43:50.70#ibcon#about to read 4, iclass 16, count 0 2006.217.07:43:50.70#ibcon#read 4, iclass 16, count 0 2006.217.07:43:50.70#ibcon#about to read 5, iclass 16, count 0 2006.217.07:43:50.70#ibcon#read 5, iclass 16, count 0 2006.217.07:43:50.70#ibcon#about to read 6, iclass 16, count 0 2006.217.07:43:50.70#ibcon#read 6, iclass 16, count 0 2006.217.07:43:50.70#ibcon#end of sib2, iclass 16, count 0 2006.217.07:43:50.70#ibcon#*after write, iclass 16, count 0 2006.217.07:43:50.70#ibcon#*before return 0, iclass 16, count 0 2006.217.07:43:50.70#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.217.07:43:50.70#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.217.07:43:50.70#ibcon#about to clear, iclass 16 cls_cnt 0 2006.217.07:43:50.70#ibcon#cleared, iclass 16 cls_cnt 0 2006.217.07:43:50.70$vc4f8/vb=1,4 2006.217.07:43:50.70#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.217.07:43:50.70#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.217.07:43:50.70#ibcon#ireg 11 cls_cnt 2 2006.217.07:43:50.70#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.217.07:43:50.70#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.217.07:43:50.70#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.217.07:43:50.70#ibcon#enter wrdev, iclass 18, count 2 2006.217.07:43:50.70#ibcon#first serial, iclass 18, count 2 2006.217.07:43:50.70#ibcon#enter sib2, iclass 18, count 2 2006.217.07:43:50.70#ibcon#flushed, iclass 18, count 2 2006.217.07:43:50.70#ibcon#about to write, iclass 18, count 2 2006.217.07:43:50.70#ibcon#wrote, iclass 18, count 2 2006.217.07:43:50.70#ibcon#about to read 3, iclass 18, count 2 2006.217.07:43:50.72#ibcon#read 3, iclass 18, count 2 2006.217.07:43:50.72#ibcon#about to read 4, iclass 18, count 2 2006.217.07:43:50.72#ibcon#read 4, iclass 18, count 2 2006.217.07:43:50.72#ibcon#about to read 5, iclass 18, count 2 2006.217.07:43:50.72#ibcon#read 5, iclass 18, count 2 2006.217.07:43:50.72#ibcon#about to read 6, iclass 18, count 2 2006.217.07:43:50.72#ibcon#read 6, iclass 18, count 2 2006.217.07:43:50.72#ibcon#end of sib2, iclass 18, count 2 2006.217.07:43:50.72#ibcon#*mode == 0, iclass 18, count 2 2006.217.07:43:50.72#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.217.07:43:50.72#ibcon#[27=AT01-04\r\n] 2006.217.07:43:50.72#ibcon#*before write, iclass 18, count 2 2006.217.07:43:50.72#ibcon#enter sib2, iclass 18, count 2 2006.217.07:43:50.72#ibcon#flushed, iclass 18, count 2 2006.217.07:43:50.72#ibcon#about to write, iclass 18, count 2 2006.217.07:43:50.72#ibcon#wrote, iclass 18, count 2 2006.217.07:43:50.72#ibcon#about to read 3, iclass 18, count 2 2006.217.07:43:50.75#ibcon#read 3, iclass 18, count 2 2006.217.07:43:50.75#ibcon#about to read 4, iclass 18, count 2 2006.217.07:43:50.75#ibcon#read 4, iclass 18, count 2 2006.217.07:43:50.75#ibcon#about to read 5, iclass 18, count 2 2006.217.07:43:50.75#ibcon#read 5, iclass 18, count 2 2006.217.07:43:50.75#ibcon#about to read 6, iclass 18, count 2 2006.217.07:43:50.75#ibcon#read 6, iclass 18, count 2 2006.217.07:43:50.75#ibcon#end of sib2, iclass 18, count 2 2006.217.07:43:50.75#ibcon#*after write, iclass 18, count 2 2006.217.07:43:50.75#ibcon#*before return 0, iclass 18, count 2 2006.217.07:43:50.75#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.217.07:43:50.75#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.217.07:43:50.75#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.217.07:43:50.75#ibcon#ireg 7 cls_cnt 0 2006.217.07:43:50.75#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.217.07:43:50.87#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.217.07:43:50.87#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.217.07:43:50.87#ibcon#enter wrdev, iclass 18, count 0 2006.217.07:43:50.87#ibcon#first serial, iclass 18, count 0 2006.217.07:43:50.87#ibcon#enter sib2, iclass 18, count 0 2006.217.07:43:50.87#ibcon#flushed, iclass 18, count 0 2006.217.07:43:50.87#ibcon#about to write, iclass 18, count 0 2006.217.07:43:50.87#ibcon#wrote, iclass 18, count 0 2006.217.07:43:50.87#ibcon#about to read 3, iclass 18, count 0 2006.217.07:43:50.89#ibcon#read 3, iclass 18, count 0 2006.217.07:43:50.89#ibcon#about to read 4, iclass 18, count 0 2006.217.07:43:50.89#ibcon#read 4, iclass 18, count 0 2006.217.07:43:50.89#ibcon#about to read 5, iclass 18, count 0 2006.217.07:43:50.89#ibcon#read 5, iclass 18, count 0 2006.217.07:43:50.89#ibcon#about to read 6, iclass 18, count 0 2006.217.07:43:50.89#ibcon#read 6, iclass 18, count 0 2006.217.07:43:50.89#ibcon#end of sib2, iclass 18, count 0 2006.217.07:43:50.89#ibcon#*mode == 0, iclass 18, count 0 2006.217.07:43:50.89#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.217.07:43:50.89#ibcon#[27=USB\r\n] 2006.217.07:43:50.89#ibcon#*before write, iclass 18, count 0 2006.217.07:43:50.89#ibcon#enter sib2, iclass 18, count 0 2006.217.07:43:50.89#ibcon#flushed, iclass 18, count 0 2006.217.07:43:50.89#ibcon#about to write, iclass 18, count 0 2006.217.07:43:50.89#ibcon#wrote, iclass 18, count 0 2006.217.07:43:50.89#ibcon#about to read 3, iclass 18, count 0 2006.217.07:43:50.92#ibcon#read 3, iclass 18, count 0 2006.217.07:43:50.92#ibcon#about to read 4, iclass 18, count 0 2006.217.07:43:50.92#ibcon#read 4, iclass 18, count 0 2006.217.07:43:50.92#ibcon#about to read 5, iclass 18, count 0 2006.217.07:43:50.92#ibcon#read 5, iclass 18, count 0 2006.217.07:43:50.92#ibcon#about to read 6, iclass 18, count 0 2006.217.07:43:50.92#ibcon#read 6, iclass 18, count 0 2006.217.07:43:50.92#ibcon#end of sib2, iclass 18, count 0 2006.217.07:43:50.92#ibcon#*after write, iclass 18, count 0 2006.217.07:43:50.92#ibcon#*before return 0, iclass 18, count 0 2006.217.07:43:50.92#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.217.07:43:50.92#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.217.07:43:50.92#ibcon#about to clear, iclass 18 cls_cnt 0 2006.217.07:43:50.92#ibcon#cleared, iclass 18 cls_cnt 0 2006.217.07:43:50.92$vc4f8/vblo=2,640.99 2006.217.07:43:50.92#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.217.07:43:50.92#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.217.07:43:50.92#ibcon#ireg 17 cls_cnt 0 2006.217.07:43:50.92#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.217.07:43:50.92#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.217.07:43:50.92#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.217.07:43:50.92#ibcon#enter wrdev, iclass 20, count 0 2006.217.07:43:50.92#ibcon#first serial, iclass 20, count 0 2006.217.07:43:50.92#ibcon#enter sib2, iclass 20, count 0 2006.217.07:43:50.92#ibcon#flushed, iclass 20, count 0 2006.217.07:43:50.92#ibcon#about to write, iclass 20, count 0 2006.217.07:43:50.92#ibcon#wrote, iclass 20, count 0 2006.217.07:43:50.92#ibcon#about to read 3, iclass 20, count 0 2006.217.07:43:50.94#ibcon#read 3, iclass 20, count 0 2006.217.07:43:50.94#ibcon#about to read 4, iclass 20, count 0 2006.217.07:43:50.94#ibcon#read 4, iclass 20, count 0 2006.217.07:43:50.94#ibcon#about to read 5, iclass 20, count 0 2006.217.07:43:50.94#ibcon#read 5, iclass 20, count 0 2006.217.07:43:50.94#ibcon#about to read 6, iclass 20, count 0 2006.217.07:43:50.94#ibcon#read 6, iclass 20, count 0 2006.217.07:43:50.94#ibcon#end of sib2, iclass 20, count 0 2006.217.07:43:50.94#ibcon#*mode == 0, iclass 20, count 0 2006.217.07:43:50.94#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.217.07:43:50.94#ibcon#[28=FRQ=02,640.99\r\n] 2006.217.07:43:50.94#ibcon#*before write, iclass 20, count 0 2006.217.07:43:50.94#ibcon#enter sib2, iclass 20, count 0 2006.217.07:43:50.94#ibcon#flushed, iclass 20, count 0 2006.217.07:43:50.94#ibcon#about to write, iclass 20, count 0 2006.217.07:43:50.94#ibcon#wrote, iclass 20, count 0 2006.217.07:43:50.94#ibcon#about to read 3, iclass 20, count 0 2006.217.07:43:50.98#ibcon#read 3, iclass 20, count 0 2006.217.07:43:50.98#ibcon#about to read 4, iclass 20, count 0 2006.217.07:43:50.98#ibcon#read 4, iclass 20, count 0 2006.217.07:43:50.98#ibcon#about to read 5, iclass 20, count 0 2006.217.07:43:50.98#ibcon#read 5, iclass 20, count 0 2006.217.07:43:50.98#ibcon#about to read 6, iclass 20, count 0 2006.217.07:43:50.98#ibcon#read 6, iclass 20, count 0 2006.217.07:43:50.98#ibcon#end of sib2, iclass 20, count 0 2006.217.07:43:50.98#ibcon#*after write, iclass 20, count 0 2006.217.07:43:50.98#ibcon#*before return 0, iclass 20, count 0 2006.217.07:43:50.98#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.217.07:43:50.98#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.217.07:43:50.98#ibcon#about to clear, iclass 20 cls_cnt 0 2006.217.07:43:50.98#ibcon#cleared, iclass 20 cls_cnt 0 2006.217.07:43:50.98$vc4f8/vb=2,4 2006.217.07:43:50.98#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.217.07:43:50.98#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.217.07:43:50.98#ibcon#ireg 11 cls_cnt 2 2006.217.07:43:50.98#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.217.07:43:51.04#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.217.07:43:51.04#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.217.07:43:51.04#ibcon#enter wrdev, iclass 22, count 2 2006.217.07:43:51.04#ibcon#first serial, iclass 22, count 2 2006.217.07:43:51.04#ibcon#enter sib2, iclass 22, count 2 2006.217.07:43:51.04#ibcon#flushed, iclass 22, count 2 2006.217.07:43:51.04#ibcon#about to write, iclass 22, count 2 2006.217.07:43:51.04#ibcon#wrote, iclass 22, count 2 2006.217.07:43:51.04#ibcon#about to read 3, iclass 22, count 2 2006.217.07:43:51.06#ibcon#read 3, iclass 22, count 2 2006.217.07:43:51.06#ibcon#about to read 4, iclass 22, count 2 2006.217.07:43:51.06#ibcon#read 4, iclass 22, count 2 2006.217.07:43:51.06#ibcon#about to read 5, iclass 22, count 2 2006.217.07:43:51.06#ibcon#read 5, iclass 22, count 2 2006.217.07:43:51.06#ibcon#about to read 6, iclass 22, count 2 2006.217.07:43:51.06#ibcon#read 6, iclass 22, count 2 2006.217.07:43:51.06#ibcon#end of sib2, iclass 22, count 2 2006.217.07:43:51.06#ibcon#*mode == 0, iclass 22, count 2 2006.217.07:43:51.06#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.217.07:43:51.06#ibcon#[27=AT02-04\r\n] 2006.217.07:43:51.06#ibcon#*before write, iclass 22, count 2 2006.217.07:43:51.06#ibcon#enter sib2, iclass 22, count 2 2006.217.07:43:51.06#ibcon#flushed, iclass 22, count 2 2006.217.07:43:51.06#ibcon#about to write, iclass 22, count 2 2006.217.07:43:51.06#ibcon#wrote, iclass 22, count 2 2006.217.07:43:51.06#ibcon#about to read 3, iclass 22, count 2 2006.217.07:43:51.09#ibcon#read 3, iclass 22, count 2 2006.217.07:43:51.09#ibcon#about to read 4, iclass 22, count 2 2006.217.07:43:51.09#ibcon#read 4, iclass 22, count 2 2006.217.07:43:51.09#ibcon#about to read 5, iclass 22, count 2 2006.217.07:43:51.09#ibcon#read 5, iclass 22, count 2 2006.217.07:43:51.09#ibcon#about to read 6, iclass 22, count 2 2006.217.07:43:51.09#ibcon#read 6, iclass 22, count 2 2006.217.07:43:51.09#ibcon#end of sib2, iclass 22, count 2 2006.217.07:43:51.09#ibcon#*after write, iclass 22, count 2 2006.217.07:43:51.09#ibcon#*before return 0, iclass 22, count 2 2006.217.07:43:51.09#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.217.07:43:51.09#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.217.07:43:51.09#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.217.07:43:51.09#ibcon#ireg 7 cls_cnt 0 2006.217.07:43:51.09#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.217.07:43:51.21#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.217.07:43:51.21#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.217.07:43:51.21#ibcon#enter wrdev, iclass 22, count 0 2006.217.07:43:51.21#ibcon#first serial, iclass 22, count 0 2006.217.07:43:51.21#ibcon#enter sib2, iclass 22, count 0 2006.217.07:43:51.21#ibcon#flushed, iclass 22, count 0 2006.217.07:43:51.21#ibcon#about to write, iclass 22, count 0 2006.217.07:43:51.21#ibcon#wrote, iclass 22, count 0 2006.217.07:43:51.21#ibcon#about to read 3, iclass 22, count 0 2006.217.07:43:51.23#ibcon#read 3, iclass 22, count 0 2006.217.07:43:51.23#ibcon#about to read 4, iclass 22, count 0 2006.217.07:43:51.23#ibcon#read 4, iclass 22, count 0 2006.217.07:43:51.23#ibcon#about to read 5, iclass 22, count 0 2006.217.07:43:51.23#ibcon#read 5, iclass 22, count 0 2006.217.07:43:51.23#ibcon#about to read 6, iclass 22, count 0 2006.217.07:43:51.23#ibcon#read 6, iclass 22, count 0 2006.217.07:43:51.23#ibcon#end of sib2, iclass 22, count 0 2006.217.07:43:51.23#ibcon#*mode == 0, iclass 22, count 0 2006.217.07:43:51.23#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.217.07:43:51.23#ibcon#[27=USB\r\n] 2006.217.07:43:51.23#ibcon#*before write, iclass 22, count 0 2006.217.07:43:51.23#ibcon#enter sib2, iclass 22, count 0 2006.217.07:43:51.23#ibcon#flushed, iclass 22, count 0 2006.217.07:43:51.23#ibcon#about to write, iclass 22, count 0 2006.217.07:43:51.23#ibcon#wrote, iclass 22, count 0 2006.217.07:43:51.23#ibcon#about to read 3, iclass 22, count 0 2006.217.07:43:51.26#ibcon#read 3, iclass 22, count 0 2006.217.07:43:51.26#ibcon#about to read 4, iclass 22, count 0 2006.217.07:43:51.26#ibcon#read 4, iclass 22, count 0 2006.217.07:43:51.26#ibcon#about to read 5, iclass 22, count 0 2006.217.07:43:51.26#ibcon#read 5, iclass 22, count 0 2006.217.07:43:51.26#ibcon#about to read 6, iclass 22, count 0 2006.217.07:43:51.26#ibcon#read 6, iclass 22, count 0 2006.217.07:43:51.26#ibcon#end of sib2, iclass 22, count 0 2006.217.07:43:51.26#ibcon#*after write, iclass 22, count 0 2006.217.07:43:51.26#ibcon#*before return 0, iclass 22, count 0 2006.217.07:43:51.26#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.217.07:43:51.26#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.217.07:43:51.26#ibcon#about to clear, iclass 22 cls_cnt 0 2006.217.07:43:51.26#ibcon#cleared, iclass 22 cls_cnt 0 2006.217.07:43:51.26$vc4f8/vblo=3,656.99 2006.217.07:43:51.26#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.217.07:43:51.26#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.217.07:43:51.26#ibcon#ireg 17 cls_cnt 0 2006.217.07:43:51.26#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.217.07:43:51.26#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.217.07:43:51.26#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.217.07:43:51.26#ibcon#enter wrdev, iclass 24, count 0 2006.217.07:43:51.26#ibcon#first serial, iclass 24, count 0 2006.217.07:43:51.26#ibcon#enter sib2, iclass 24, count 0 2006.217.07:43:51.26#ibcon#flushed, iclass 24, count 0 2006.217.07:43:51.26#ibcon#about to write, iclass 24, count 0 2006.217.07:43:51.26#ibcon#wrote, iclass 24, count 0 2006.217.07:43:51.26#ibcon#about to read 3, iclass 24, count 0 2006.217.07:43:51.28#ibcon#read 3, iclass 24, count 0 2006.217.07:43:51.28#ibcon#about to read 4, iclass 24, count 0 2006.217.07:43:51.28#ibcon#read 4, iclass 24, count 0 2006.217.07:43:51.28#ibcon#about to read 5, iclass 24, count 0 2006.217.07:43:51.28#ibcon#read 5, iclass 24, count 0 2006.217.07:43:51.28#ibcon#about to read 6, iclass 24, count 0 2006.217.07:43:51.28#ibcon#read 6, iclass 24, count 0 2006.217.07:43:51.28#ibcon#end of sib2, iclass 24, count 0 2006.217.07:43:51.28#ibcon#*mode == 0, iclass 24, count 0 2006.217.07:43:51.28#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.217.07:43:51.28#ibcon#[28=FRQ=03,656.99\r\n] 2006.217.07:43:51.28#ibcon#*before write, iclass 24, count 0 2006.217.07:43:51.28#ibcon#enter sib2, iclass 24, count 0 2006.217.07:43:51.28#ibcon#flushed, iclass 24, count 0 2006.217.07:43:51.28#ibcon#about to write, iclass 24, count 0 2006.217.07:43:51.28#ibcon#wrote, iclass 24, count 0 2006.217.07:43:51.28#ibcon#about to read 3, iclass 24, count 0 2006.217.07:43:51.32#ibcon#read 3, iclass 24, count 0 2006.217.07:43:51.32#ibcon#about to read 4, iclass 24, count 0 2006.217.07:43:51.32#ibcon#read 4, iclass 24, count 0 2006.217.07:43:51.32#ibcon#about to read 5, iclass 24, count 0 2006.217.07:43:51.32#ibcon#read 5, iclass 24, count 0 2006.217.07:43:51.32#ibcon#about to read 6, iclass 24, count 0 2006.217.07:43:51.32#ibcon#read 6, iclass 24, count 0 2006.217.07:43:51.32#ibcon#end of sib2, iclass 24, count 0 2006.217.07:43:51.32#ibcon#*after write, iclass 24, count 0 2006.217.07:43:51.32#ibcon#*before return 0, iclass 24, count 0 2006.217.07:43:51.32#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.217.07:43:51.32#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.217.07:43:51.32#ibcon#about to clear, iclass 24 cls_cnt 0 2006.217.07:43:51.32#ibcon#cleared, iclass 24 cls_cnt 0 2006.217.07:43:51.32$vc4f8/vb=3,4 2006.217.07:43:51.32#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.217.07:43:51.32#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.217.07:43:51.32#ibcon#ireg 11 cls_cnt 2 2006.217.07:43:51.32#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.217.07:43:51.38#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.217.07:43:51.38#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.217.07:43:51.38#ibcon#enter wrdev, iclass 26, count 2 2006.217.07:43:51.38#ibcon#first serial, iclass 26, count 2 2006.217.07:43:51.38#ibcon#enter sib2, iclass 26, count 2 2006.217.07:43:51.38#ibcon#flushed, iclass 26, count 2 2006.217.07:43:51.38#ibcon#about to write, iclass 26, count 2 2006.217.07:43:51.38#ibcon#wrote, iclass 26, count 2 2006.217.07:43:51.38#ibcon#about to read 3, iclass 26, count 2 2006.217.07:43:51.40#ibcon#read 3, iclass 26, count 2 2006.217.07:43:51.40#ibcon#about to read 4, iclass 26, count 2 2006.217.07:43:51.40#ibcon#read 4, iclass 26, count 2 2006.217.07:43:51.40#ibcon#about to read 5, iclass 26, count 2 2006.217.07:43:51.40#ibcon#read 5, iclass 26, count 2 2006.217.07:43:51.40#ibcon#about to read 6, iclass 26, count 2 2006.217.07:43:51.40#ibcon#read 6, iclass 26, count 2 2006.217.07:43:51.40#ibcon#end of sib2, iclass 26, count 2 2006.217.07:43:51.40#ibcon#*mode == 0, iclass 26, count 2 2006.217.07:43:51.40#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.217.07:43:51.40#ibcon#[27=AT03-04\r\n] 2006.217.07:43:51.40#ibcon#*before write, iclass 26, count 2 2006.217.07:43:51.40#ibcon#enter sib2, iclass 26, count 2 2006.217.07:43:51.40#ibcon#flushed, iclass 26, count 2 2006.217.07:43:51.40#ibcon#about to write, iclass 26, count 2 2006.217.07:43:51.40#ibcon#wrote, iclass 26, count 2 2006.217.07:43:51.40#ibcon#about to read 3, iclass 26, count 2 2006.217.07:43:51.43#ibcon#read 3, iclass 26, count 2 2006.217.07:43:51.43#ibcon#about to read 4, iclass 26, count 2 2006.217.07:43:51.43#ibcon#read 4, iclass 26, count 2 2006.217.07:43:51.43#ibcon#about to read 5, iclass 26, count 2 2006.217.07:43:51.43#ibcon#read 5, iclass 26, count 2 2006.217.07:43:51.43#ibcon#about to read 6, iclass 26, count 2 2006.217.07:43:51.43#ibcon#read 6, iclass 26, count 2 2006.217.07:43:51.43#ibcon#end of sib2, iclass 26, count 2 2006.217.07:43:51.43#ibcon#*after write, iclass 26, count 2 2006.217.07:43:51.43#ibcon#*before return 0, iclass 26, count 2 2006.217.07:43:51.43#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.217.07:43:51.43#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.217.07:43:51.43#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.217.07:43:51.43#ibcon#ireg 7 cls_cnt 0 2006.217.07:43:51.43#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.217.07:43:51.55#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.217.07:43:51.55#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.217.07:43:51.55#ibcon#enter wrdev, iclass 26, count 0 2006.217.07:43:51.55#ibcon#first serial, iclass 26, count 0 2006.217.07:43:51.55#ibcon#enter sib2, iclass 26, count 0 2006.217.07:43:51.55#ibcon#flushed, iclass 26, count 0 2006.217.07:43:51.55#ibcon#about to write, iclass 26, count 0 2006.217.07:43:51.55#ibcon#wrote, iclass 26, count 0 2006.217.07:43:51.55#ibcon#about to read 3, iclass 26, count 0 2006.217.07:43:51.57#ibcon#read 3, iclass 26, count 0 2006.217.07:43:51.57#ibcon#about to read 4, iclass 26, count 0 2006.217.07:43:51.57#ibcon#read 4, iclass 26, count 0 2006.217.07:43:51.57#ibcon#about to read 5, iclass 26, count 0 2006.217.07:43:51.57#ibcon#read 5, iclass 26, count 0 2006.217.07:43:51.57#ibcon#about to read 6, iclass 26, count 0 2006.217.07:43:51.57#ibcon#read 6, iclass 26, count 0 2006.217.07:43:51.57#ibcon#end of sib2, iclass 26, count 0 2006.217.07:43:51.57#ibcon#*mode == 0, iclass 26, count 0 2006.217.07:43:51.57#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.217.07:43:51.57#ibcon#[27=USB\r\n] 2006.217.07:43:51.57#ibcon#*before write, iclass 26, count 0 2006.217.07:43:51.57#ibcon#enter sib2, iclass 26, count 0 2006.217.07:43:51.57#ibcon#flushed, iclass 26, count 0 2006.217.07:43:51.57#ibcon#about to write, iclass 26, count 0 2006.217.07:43:51.57#ibcon#wrote, iclass 26, count 0 2006.217.07:43:51.57#ibcon#about to read 3, iclass 26, count 0 2006.217.07:43:51.60#ibcon#read 3, iclass 26, count 0 2006.217.07:43:51.60#ibcon#about to read 4, iclass 26, count 0 2006.217.07:43:51.60#ibcon#read 4, iclass 26, count 0 2006.217.07:43:51.60#ibcon#about to read 5, iclass 26, count 0 2006.217.07:43:51.60#ibcon#read 5, iclass 26, count 0 2006.217.07:43:51.60#ibcon#about to read 6, iclass 26, count 0 2006.217.07:43:51.60#ibcon#read 6, iclass 26, count 0 2006.217.07:43:51.60#ibcon#end of sib2, iclass 26, count 0 2006.217.07:43:51.60#ibcon#*after write, iclass 26, count 0 2006.217.07:43:51.60#ibcon#*before return 0, iclass 26, count 0 2006.217.07:43:51.60#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.217.07:43:51.60#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.217.07:43:51.60#ibcon#about to clear, iclass 26 cls_cnt 0 2006.217.07:43:51.60#ibcon#cleared, iclass 26 cls_cnt 0 2006.217.07:43:51.60$vc4f8/vblo=4,712.99 2006.217.07:43:51.60#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.217.07:43:51.60#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.217.07:43:51.60#ibcon#ireg 17 cls_cnt 0 2006.217.07:43:51.60#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.217.07:43:51.60#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.217.07:43:51.60#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.217.07:43:51.60#ibcon#enter wrdev, iclass 28, count 0 2006.217.07:43:51.60#ibcon#first serial, iclass 28, count 0 2006.217.07:43:51.60#ibcon#enter sib2, iclass 28, count 0 2006.217.07:43:51.60#ibcon#flushed, iclass 28, count 0 2006.217.07:43:51.60#ibcon#about to write, iclass 28, count 0 2006.217.07:43:51.60#ibcon#wrote, iclass 28, count 0 2006.217.07:43:51.60#ibcon#about to read 3, iclass 28, count 0 2006.217.07:43:51.62#ibcon#read 3, iclass 28, count 0 2006.217.07:43:51.62#ibcon#about to read 4, iclass 28, count 0 2006.217.07:43:51.62#ibcon#read 4, iclass 28, count 0 2006.217.07:43:51.62#ibcon#about to read 5, iclass 28, count 0 2006.217.07:43:51.62#ibcon#read 5, iclass 28, count 0 2006.217.07:43:51.62#ibcon#about to read 6, iclass 28, count 0 2006.217.07:43:51.62#ibcon#read 6, iclass 28, count 0 2006.217.07:43:51.62#ibcon#end of sib2, iclass 28, count 0 2006.217.07:43:51.62#ibcon#*mode == 0, iclass 28, count 0 2006.217.07:43:51.62#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.217.07:43:51.62#ibcon#[28=FRQ=04,712.99\r\n] 2006.217.07:43:51.62#ibcon#*before write, iclass 28, count 0 2006.217.07:43:51.62#ibcon#enter sib2, iclass 28, count 0 2006.217.07:43:51.62#ibcon#flushed, iclass 28, count 0 2006.217.07:43:51.62#ibcon#about to write, iclass 28, count 0 2006.217.07:43:51.62#ibcon#wrote, iclass 28, count 0 2006.217.07:43:51.62#ibcon#about to read 3, iclass 28, count 0 2006.217.07:43:51.66#ibcon#read 3, iclass 28, count 0 2006.217.07:43:51.66#ibcon#about to read 4, iclass 28, count 0 2006.217.07:43:51.66#ibcon#read 4, iclass 28, count 0 2006.217.07:43:51.66#ibcon#about to read 5, iclass 28, count 0 2006.217.07:43:51.66#ibcon#read 5, iclass 28, count 0 2006.217.07:43:51.66#ibcon#about to read 6, iclass 28, count 0 2006.217.07:43:51.66#ibcon#read 6, iclass 28, count 0 2006.217.07:43:51.66#ibcon#end of sib2, iclass 28, count 0 2006.217.07:43:51.66#ibcon#*after write, iclass 28, count 0 2006.217.07:43:51.66#ibcon#*before return 0, iclass 28, count 0 2006.217.07:43:51.66#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.217.07:43:51.66#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.217.07:43:51.66#ibcon#about to clear, iclass 28 cls_cnt 0 2006.217.07:43:51.66#ibcon#cleared, iclass 28 cls_cnt 0 2006.217.07:43:51.66$vc4f8/vb=4,4 2006.217.07:43:51.66#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.217.07:43:51.66#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.217.07:43:51.66#ibcon#ireg 11 cls_cnt 2 2006.217.07:43:51.66#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.217.07:43:51.72#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.217.07:43:51.72#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.217.07:43:51.72#ibcon#enter wrdev, iclass 30, count 2 2006.217.07:43:51.72#ibcon#first serial, iclass 30, count 2 2006.217.07:43:51.72#ibcon#enter sib2, iclass 30, count 2 2006.217.07:43:51.72#ibcon#flushed, iclass 30, count 2 2006.217.07:43:51.72#ibcon#about to write, iclass 30, count 2 2006.217.07:43:51.72#ibcon#wrote, iclass 30, count 2 2006.217.07:43:51.72#ibcon#about to read 3, iclass 30, count 2 2006.217.07:43:51.74#ibcon#read 3, iclass 30, count 2 2006.217.07:43:51.74#ibcon#about to read 4, iclass 30, count 2 2006.217.07:43:51.74#ibcon#read 4, iclass 30, count 2 2006.217.07:43:51.74#ibcon#about to read 5, iclass 30, count 2 2006.217.07:43:51.74#ibcon#read 5, iclass 30, count 2 2006.217.07:43:51.74#ibcon#about to read 6, iclass 30, count 2 2006.217.07:43:51.74#ibcon#read 6, iclass 30, count 2 2006.217.07:43:51.74#ibcon#end of sib2, iclass 30, count 2 2006.217.07:43:51.74#ibcon#*mode == 0, iclass 30, count 2 2006.217.07:43:51.74#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.217.07:43:51.74#ibcon#[27=AT04-04\r\n] 2006.217.07:43:51.74#ibcon#*before write, iclass 30, count 2 2006.217.07:43:51.74#ibcon#enter sib2, iclass 30, count 2 2006.217.07:43:51.74#ibcon#flushed, iclass 30, count 2 2006.217.07:43:51.74#ibcon#about to write, iclass 30, count 2 2006.217.07:43:51.74#ibcon#wrote, iclass 30, count 2 2006.217.07:43:51.74#ibcon#about to read 3, iclass 30, count 2 2006.217.07:43:51.77#ibcon#read 3, iclass 30, count 2 2006.217.07:43:51.77#ibcon#about to read 4, iclass 30, count 2 2006.217.07:43:51.77#ibcon#read 4, iclass 30, count 2 2006.217.07:43:51.77#ibcon#about to read 5, iclass 30, count 2 2006.217.07:43:51.77#ibcon#read 5, iclass 30, count 2 2006.217.07:43:51.77#ibcon#about to read 6, iclass 30, count 2 2006.217.07:43:51.77#ibcon#read 6, iclass 30, count 2 2006.217.07:43:51.77#ibcon#end of sib2, iclass 30, count 2 2006.217.07:43:51.77#ibcon#*after write, iclass 30, count 2 2006.217.07:43:51.77#ibcon#*before return 0, iclass 30, count 2 2006.217.07:43:51.77#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.217.07:43:51.77#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.217.07:43:51.77#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.217.07:43:51.77#ibcon#ireg 7 cls_cnt 0 2006.217.07:43:51.77#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.217.07:43:51.89#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.217.07:43:51.89#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.217.07:43:51.89#ibcon#enter wrdev, iclass 30, count 0 2006.217.07:43:51.89#ibcon#first serial, iclass 30, count 0 2006.217.07:43:51.89#ibcon#enter sib2, iclass 30, count 0 2006.217.07:43:51.89#ibcon#flushed, iclass 30, count 0 2006.217.07:43:51.89#ibcon#about to write, iclass 30, count 0 2006.217.07:43:51.89#ibcon#wrote, iclass 30, count 0 2006.217.07:43:51.89#ibcon#about to read 3, iclass 30, count 0 2006.217.07:43:51.91#ibcon#read 3, iclass 30, count 0 2006.217.07:43:51.91#ibcon#about to read 4, iclass 30, count 0 2006.217.07:43:51.91#ibcon#read 4, iclass 30, count 0 2006.217.07:43:51.91#ibcon#about to read 5, iclass 30, count 0 2006.217.07:43:51.91#ibcon#read 5, iclass 30, count 0 2006.217.07:43:51.91#ibcon#about to read 6, iclass 30, count 0 2006.217.07:43:51.91#ibcon#read 6, iclass 30, count 0 2006.217.07:43:51.91#ibcon#end of sib2, iclass 30, count 0 2006.217.07:43:51.91#ibcon#*mode == 0, iclass 30, count 0 2006.217.07:43:51.91#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.217.07:43:51.91#ibcon#[27=USB\r\n] 2006.217.07:43:51.91#ibcon#*before write, iclass 30, count 0 2006.217.07:43:51.91#ibcon#enter sib2, iclass 30, count 0 2006.217.07:43:51.91#ibcon#flushed, iclass 30, count 0 2006.217.07:43:51.91#ibcon#about to write, iclass 30, count 0 2006.217.07:43:51.91#ibcon#wrote, iclass 30, count 0 2006.217.07:43:51.91#ibcon#about to read 3, iclass 30, count 0 2006.217.07:43:51.94#ibcon#read 3, iclass 30, count 0 2006.217.07:43:51.94#ibcon#about to read 4, iclass 30, count 0 2006.217.07:43:51.94#ibcon#read 4, iclass 30, count 0 2006.217.07:43:51.94#ibcon#about to read 5, iclass 30, count 0 2006.217.07:43:51.94#ibcon#read 5, iclass 30, count 0 2006.217.07:43:51.94#ibcon#about to read 6, iclass 30, count 0 2006.217.07:43:51.94#ibcon#read 6, iclass 30, count 0 2006.217.07:43:51.94#ibcon#end of sib2, iclass 30, count 0 2006.217.07:43:51.94#ibcon#*after write, iclass 30, count 0 2006.217.07:43:51.94#ibcon#*before return 0, iclass 30, count 0 2006.217.07:43:51.94#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.217.07:43:51.94#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.217.07:43:51.94#ibcon#about to clear, iclass 30 cls_cnt 0 2006.217.07:43:51.94#ibcon#cleared, iclass 30 cls_cnt 0 2006.217.07:43:51.94$vc4f8/vblo=5,744.99 2006.217.07:43:51.94#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.217.07:43:51.94#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.217.07:43:51.94#ibcon#ireg 17 cls_cnt 0 2006.217.07:43:51.94#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.217.07:43:51.94#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.217.07:43:51.94#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.217.07:43:51.94#ibcon#enter wrdev, iclass 32, count 0 2006.217.07:43:51.94#ibcon#first serial, iclass 32, count 0 2006.217.07:43:51.94#ibcon#enter sib2, iclass 32, count 0 2006.217.07:43:51.94#ibcon#flushed, iclass 32, count 0 2006.217.07:43:51.94#ibcon#about to write, iclass 32, count 0 2006.217.07:43:51.94#ibcon#wrote, iclass 32, count 0 2006.217.07:43:51.94#ibcon#about to read 3, iclass 32, count 0 2006.217.07:43:51.96#ibcon#read 3, iclass 32, count 0 2006.217.07:43:51.96#ibcon#about to read 4, iclass 32, count 0 2006.217.07:43:51.96#ibcon#read 4, iclass 32, count 0 2006.217.07:43:51.96#ibcon#about to read 5, iclass 32, count 0 2006.217.07:43:51.96#ibcon#read 5, iclass 32, count 0 2006.217.07:43:51.96#ibcon#about to read 6, iclass 32, count 0 2006.217.07:43:51.96#ibcon#read 6, iclass 32, count 0 2006.217.07:43:51.96#ibcon#end of sib2, iclass 32, count 0 2006.217.07:43:51.96#ibcon#*mode == 0, iclass 32, count 0 2006.217.07:43:51.96#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.217.07:43:51.96#ibcon#[28=FRQ=05,744.99\r\n] 2006.217.07:43:51.96#ibcon#*before write, iclass 32, count 0 2006.217.07:43:51.96#ibcon#enter sib2, iclass 32, count 0 2006.217.07:43:51.96#ibcon#flushed, iclass 32, count 0 2006.217.07:43:51.96#ibcon#about to write, iclass 32, count 0 2006.217.07:43:51.96#ibcon#wrote, iclass 32, count 0 2006.217.07:43:51.96#ibcon#about to read 3, iclass 32, count 0 2006.217.07:43:52.00#ibcon#read 3, iclass 32, count 0 2006.217.07:43:52.00#ibcon#about to read 4, iclass 32, count 0 2006.217.07:43:52.00#ibcon#read 4, iclass 32, count 0 2006.217.07:43:52.00#ibcon#about to read 5, iclass 32, count 0 2006.217.07:43:52.00#ibcon#read 5, iclass 32, count 0 2006.217.07:43:52.00#ibcon#about to read 6, iclass 32, count 0 2006.217.07:43:52.00#ibcon#read 6, iclass 32, count 0 2006.217.07:43:52.00#ibcon#end of sib2, iclass 32, count 0 2006.217.07:43:52.00#ibcon#*after write, iclass 32, count 0 2006.217.07:43:52.00#ibcon#*before return 0, iclass 32, count 0 2006.217.07:43:52.00#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.217.07:43:52.00#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.217.07:43:52.00#ibcon#about to clear, iclass 32 cls_cnt 0 2006.217.07:43:52.00#ibcon#cleared, iclass 32 cls_cnt 0 2006.217.07:43:52.00$vc4f8/vb=5,4 2006.217.07:43:52.00#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.217.07:43:52.00#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.217.07:43:52.00#ibcon#ireg 11 cls_cnt 2 2006.217.07:43:52.00#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.217.07:43:52.06#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.217.07:43:52.06#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.217.07:43:52.06#ibcon#enter wrdev, iclass 34, count 2 2006.217.07:43:52.06#ibcon#first serial, iclass 34, count 2 2006.217.07:43:52.06#ibcon#enter sib2, iclass 34, count 2 2006.217.07:43:52.06#ibcon#flushed, iclass 34, count 2 2006.217.07:43:52.06#ibcon#about to write, iclass 34, count 2 2006.217.07:43:52.06#ibcon#wrote, iclass 34, count 2 2006.217.07:43:52.06#ibcon#about to read 3, iclass 34, count 2 2006.217.07:43:52.08#ibcon#read 3, iclass 34, count 2 2006.217.07:43:52.08#ibcon#about to read 4, iclass 34, count 2 2006.217.07:43:52.08#ibcon#read 4, iclass 34, count 2 2006.217.07:43:52.08#ibcon#about to read 5, iclass 34, count 2 2006.217.07:43:52.08#ibcon#read 5, iclass 34, count 2 2006.217.07:43:52.08#ibcon#about to read 6, iclass 34, count 2 2006.217.07:43:52.08#ibcon#read 6, iclass 34, count 2 2006.217.07:43:52.08#ibcon#end of sib2, iclass 34, count 2 2006.217.07:43:52.08#ibcon#*mode == 0, iclass 34, count 2 2006.217.07:43:52.08#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.217.07:43:52.08#ibcon#[27=AT05-04\r\n] 2006.217.07:43:52.08#ibcon#*before write, iclass 34, count 2 2006.217.07:43:52.08#ibcon#enter sib2, iclass 34, count 2 2006.217.07:43:52.08#ibcon#flushed, iclass 34, count 2 2006.217.07:43:52.08#ibcon#about to write, iclass 34, count 2 2006.217.07:43:52.08#ibcon#wrote, iclass 34, count 2 2006.217.07:43:52.08#ibcon#about to read 3, iclass 34, count 2 2006.217.07:43:52.11#ibcon#read 3, iclass 34, count 2 2006.217.07:43:52.11#ibcon#about to read 4, iclass 34, count 2 2006.217.07:43:52.11#ibcon#read 4, iclass 34, count 2 2006.217.07:43:52.11#ibcon#about to read 5, iclass 34, count 2 2006.217.07:43:52.11#ibcon#read 5, iclass 34, count 2 2006.217.07:43:52.11#ibcon#about to read 6, iclass 34, count 2 2006.217.07:43:52.11#ibcon#read 6, iclass 34, count 2 2006.217.07:43:52.11#ibcon#end of sib2, iclass 34, count 2 2006.217.07:43:52.11#ibcon#*after write, iclass 34, count 2 2006.217.07:43:52.11#ibcon#*before return 0, iclass 34, count 2 2006.217.07:43:52.11#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.217.07:43:52.11#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.217.07:43:52.11#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.217.07:43:52.11#ibcon#ireg 7 cls_cnt 0 2006.217.07:43:52.11#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.217.07:43:52.23#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.217.07:43:52.23#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.217.07:43:52.23#ibcon#enter wrdev, iclass 34, count 0 2006.217.07:43:52.23#ibcon#first serial, iclass 34, count 0 2006.217.07:43:52.23#ibcon#enter sib2, iclass 34, count 0 2006.217.07:43:52.23#ibcon#flushed, iclass 34, count 0 2006.217.07:43:52.23#ibcon#about to write, iclass 34, count 0 2006.217.07:43:52.23#ibcon#wrote, iclass 34, count 0 2006.217.07:43:52.23#ibcon#about to read 3, iclass 34, count 0 2006.217.07:43:52.25#ibcon#read 3, iclass 34, count 0 2006.217.07:43:52.25#ibcon#about to read 4, iclass 34, count 0 2006.217.07:43:52.25#ibcon#read 4, iclass 34, count 0 2006.217.07:43:52.25#ibcon#about to read 5, iclass 34, count 0 2006.217.07:43:52.25#ibcon#read 5, iclass 34, count 0 2006.217.07:43:52.25#ibcon#about to read 6, iclass 34, count 0 2006.217.07:43:52.25#ibcon#read 6, iclass 34, count 0 2006.217.07:43:52.25#ibcon#end of sib2, iclass 34, count 0 2006.217.07:43:52.25#ibcon#*mode == 0, iclass 34, count 0 2006.217.07:43:52.25#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.217.07:43:52.25#ibcon#[27=USB\r\n] 2006.217.07:43:52.25#ibcon#*before write, iclass 34, count 0 2006.217.07:43:52.25#ibcon#enter sib2, iclass 34, count 0 2006.217.07:43:52.25#ibcon#flushed, iclass 34, count 0 2006.217.07:43:52.25#ibcon#about to write, iclass 34, count 0 2006.217.07:43:52.25#ibcon#wrote, iclass 34, count 0 2006.217.07:43:52.25#ibcon#about to read 3, iclass 34, count 0 2006.217.07:43:52.28#ibcon#read 3, iclass 34, count 0 2006.217.07:43:52.28#ibcon#about to read 4, iclass 34, count 0 2006.217.07:43:52.28#ibcon#read 4, iclass 34, count 0 2006.217.07:43:52.28#ibcon#about to read 5, iclass 34, count 0 2006.217.07:43:52.28#ibcon#read 5, iclass 34, count 0 2006.217.07:43:52.28#ibcon#about to read 6, iclass 34, count 0 2006.217.07:43:52.28#ibcon#read 6, iclass 34, count 0 2006.217.07:43:52.28#ibcon#end of sib2, iclass 34, count 0 2006.217.07:43:52.28#ibcon#*after write, iclass 34, count 0 2006.217.07:43:52.28#ibcon#*before return 0, iclass 34, count 0 2006.217.07:43:52.28#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.217.07:43:52.28#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.217.07:43:52.28#ibcon#about to clear, iclass 34 cls_cnt 0 2006.217.07:43:52.28#ibcon#cleared, iclass 34 cls_cnt 0 2006.217.07:43:52.28$vc4f8/vblo=6,752.99 2006.217.07:43:52.28#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.217.07:43:52.28#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.217.07:43:52.28#ibcon#ireg 17 cls_cnt 0 2006.217.07:43:52.28#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.217.07:43:52.28#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.217.07:43:52.28#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.217.07:43:52.28#ibcon#enter wrdev, iclass 36, count 0 2006.217.07:43:52.28#ibcon#first serial, iclass 36, count 0 2006.217.07:43:52.28#ibcon#enter sib2, iclass 36, count 0 2006.217.07:43:52.28#ibcon#flushed, iclass 36, count 0 2006.217.07:43:52.28#ibcon#about to write, iclass 36, count 0 2006.217.07:43:52.28#ibcon#wrote, iclass 36, count 0 2006.217.07:43:52.28#ibcon#about to read 3, iclass 36, count 0 2006.217.07:43:52.30#ibcon#read 3, iclass 36, count 0 2006.217.07:43:52.30#ibcon#about to read 4, iclass 36, count 0 2006.217.07:43:52.30#ibcon#read 4, iclass 36, count 0 2006.217.07:43:52.30#ibcon#about to read 5, iclass 36, count 0 2006.217.07:43:52.30#ibcon#read 5, iclass 36, count 0 2006.217.07:43:52.30#ibcon#about to read 6, iclass 36, count 0 2006.217.07:43:52.30#ibcon#read 6, iclass 36, count 0 2006.217.07:43:52.30#ibcon#end of sib2, iclass 36, count 0 2006.217.07:43:52.30#ibcon#*mode == 0, iclass 36, count 0 2006.217.07:43:52.30#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.217.07:43:52.30#ibcon#[28=FRQ=06,752.99\r\n] 2006.217.07:43:52.30#ibcon#*before write, iclass 36, count 0 2006.217.07:43:52.30#ibcon#enter sib2, iclass 36, count 0 2006.217.07:43:52.30#ibcon#flushed, iclass 36, count 0 2006.217.07:43:52.30#ibcon#about to write, iclass 36, count 0 2006.217.07:43:52.30#ibcon#wrote, iclass 36, count 0 2006.217.07:43:52.30#ibcon#about to read 3, iclass 36, count 0 2006.217.07:43:52.34#ibcon#read 3, iclass 36, count 0 2006.217.07:43:52.34#ibcon#about to read 4, iclass 36, count 0 2006.217.07:43:52.34#ibcon#read 4, iclass 36, count 0 2006.217.07:43:52.34#ibcon#about to read 5, iclass 36, count 0 2006.217.07:43:52.34#ibcon#read 5, iclass 36, count 0 2006.217.07:43:52.34#ibcon#about to read 6, iclass 36, count 0 2006.217.07:43:52.34#ibcon#read 6, iclass 36, count 0 2006.217.07:43:52.34#ibcon#end of sib2, iclass 36, count 0 2006.217.07:43:52.34#ibcon#*after write, iclass 36, count 0 2006.217.07:43:52.34#ibcon#*before return 0, iclass 36, count 0 2006.217.07:43:52.34#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.217.07:43:52.34#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.217.07:43:52.34#ibcon#about to clear, iclass 36 cls_cnt 0 2006.217.07:43:52.34#ibcon#cleared, iclass 36 cls_cnt 0 2006.217.07:43:52.34$vc4f8/vb=6,4 2006.217.07:43:52.34#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.217.07:43:52.34#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.217.07:43:52.34#ibcon#ireg 11 cls_cnt 2 2006.217.07:43:52.34#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.217.07:43:52.41#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.217.07:43:52.41#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.217.07:43:52.41#ibcon#enter wrdev, iclass 38, count 2 2006.217.07:43:52.41#ibcon#first serial, iclass 38, count 2 2006.217.07:43:52.41#ibcon#enter sib2, iclass 38, count 2 2006.217.07:43:52.41#ibcon#flushed, iclass 38, count 2 2006.217.07:43:52.41#ibcon#about to write, iclass 38, count 2 2006.217.07:43:52.41#ibcon#wrote, iclass 38, count 2 2006.217.07:43:52.41#ibcon#about to read 3, iclass 38, count 2 2006.217.07:43:52.42#ibcon#read 3, iclass 38, count 2 2006.217.07:43:52.42#ibcon#about to read 4, iclass 38, count 2 2006.217.07:43:52.42#ibcon#read 4, iclass 38, count 2 2006.217.07:43:52.42#ibcon#about to read 5, iclass 38, count 2 2006.217.07:43:52.42#ibcon#read 5, iclass 38, count 2 2006.217.07:43:52.42#ibcon#about to read 6, iclass 38, count 2 2006.217.07:43:52.42#ibcon#read 6, iclass 38, count 2 2006.217.07:43:52.42#ibcon#end of sib2, iclass 38, count 2 2006.217.07:43:52.42#ibcon#*mode == 0, iclass 38, count 2 2006.217.07:43:52.42#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.217.07:43:52.42#ibcon#[27=AT06-04\r\n] 2006.217.07:43:52.42#ibcon#*before write, iclass 38, count 2 2006.217.07:43:52.42#ibcon#enter sib2, iclass 38, count 2 2006.217.07:43:52.42#ibcon#flushed, iclass 38, count 2 2006.217.07:43:52.42#ibcon#about to write, iclass 38, count 2 2006.217.07:43:52.42#ibcon#wrote, iclass 38, count 2 2006.217.07:43:52.42#ibcon#about to read 3, iclass 38, count 2 2006.217.07:43:52.45#ibcon#read 3, iclass 38, count 2 2006.217.07:43:52.45#ibcon#about to read 4, iclass 38, count 2 2006.217.07:43:52.45#ibcon#read 4, iclass 38, count 2 2006.217.07:43:52.45#ibcon#about to read 5, iclass 38, count 2 2006.217.07:43:52.45#ibcon#read 5, iclass 38, count 2 2006.217.07:43:52.45#ibcon#about to read 6, iclass 38, count 2 2006.217.07:43:52.45#ibcon#read 6, iclass 38, count 2 2006.217.07:43:52.45#ibcon#end of sib2, iclass 38, count 2 2006.217.07:43:52.45#ibcon#*after write, iclass 38, count 2 2006.217.07:43:52.45#ibcon#*before return 0, iclass 38, count 2 2006.217.07:43:52.45#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.217.07:43:52.45#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.217.07:43:52.45#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.217.07:43:52.45#ibcon#ireg 7 cls_cnt 0 2006.217.07:43:52.45#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.217.07:43:52.57#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.217.07:43:52.57#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.217.07:43:52.57#ibcon#enter wrdev, iclass 38, count 0 2006.217.07:43:52.57#ibcon#first serial, iclass 38, count 0 2006.217.07:43:52.57#ibcon#enter sib2, iclass 38, count 0 2006.217.07:43:52.57#ibcon#flushed, iclass 38, count 0 2006.217.07:43:52.57#ibcon#about to write, iclass 38, count 0 2006.217.07:43:52.57#ibcon#wrote, iclass 38, count 0 2006.217.07:43:52.57#ibcon#about to read 3, iclass 38, count 0 2006.217.07:43:52.59#ibcon#read 3, iclass 38, count 0 2006.217.07:43:52.59#ibcon#about to read 4, iclass 38, count 0 2006.217.07:43:52.59#ibcon#read 4, iclass 38, count 0 2006.217.07:43:52.59#ibcon#about to read 5, iclass 38, count 0 2006.217.07:43:52.59#ibcon#read 5, iclass 38, count 0 2006.217.07:43:52.59#ibcon#about to read 6, iclass 38, count 0 2006.217.07:43:52.59#ibcon#read 6, iclass 38, count 0 2006.217.07:43:52.59#ibcon#end of sib2, iclass 38, count 0 2006.217.07:43:52.59#ibcon#*mode == 0, iclass 38, count 0 2006.217.07:43:52.59#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.217.07:43:52.59#ibcon#[27=USB\r\n] 2006.217.07:43:52.59#ibcon#*before write, iclass 38, count 0 2006.217.07:43:52.59#ibcon#enter sib2, iclass 38, count 0 2006.217.07:43:52.59#ibcon#flushed, iclass 38, count 0 2006.217.07:43:52.59#ibcon#about to write, iclass 38, count 0 2006.217.07:43:52.59#ibcon#wrote, iclass 38, count 0 2006.217.07:43:52.59#ibcon#about to read 3, iclass 38, count 0 2006.217.07:43:52.62#ibcon#read 3, iclass 38, count 0 2006.217.07:43:52.62#ibcon#about to read 4, iclass 38, count 0 2006.217.07:43:52.62#ibcon#read 4, iclass 38, count 0 2006.217.07:43:52.62#ibcon#about to read 5, iclass 38, count 0 2006.217.07:43:52.62#ibcon#read 5, iclass 38, count 0 2006.217.07:43:52.62#ibcon#about to read 6, iclass 38, count 0 2006.217.07:43:52.62#ibcon#read 6, iclass 38, count 0 2006.217.07:43:52.62#ibcon#end of sib2, iclass 38, count 0 2006.217.07:43:52.62#ibcon#*after write, iclass 38, count 0 2006.217.07:43:52.62#ibcon#*before return 0, iclass 38, count 0 2006.217.07:43:52.62#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.217.07:43:52.62#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.217.07:43:52.62#ibcon#about to clear, iclass 38 cls_cnt 0 2006.217.07:43:52.62#ibcon#cleared, iclass 38 cls_cnt 0 2006.217.07:43:52.62$vc4f8/vabw=wide 2006.217.07:43:52.62#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.217.07:43:52.62#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.217.07:43:52.62#ibcon#ireg 8 cls_cnt 0 2006.217.07:43:52.62#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.217.07:43:52.62#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.217.07:43:52.62#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.217.07:43:52.62#ibcon#enter wrdev, iclass 40, count 0 2006.217.07:43:52.62#ibcon#first serial, iclass 40, count 0 2006.217.07:43:52.62#ibcon#enter sib2, iclass 40, count 0 2006.217.07:43:52.62#ibcon#flushed, iclass 40, count 0 2006.217.07:43:52.62#ibcon#about to write, iclass 40, count 0 2006.217.07:43:52.62#ibcon#wrote, iclass 40, count 0 2006.217.07:43:52.62#ibcon#about to read 3, iclass 40, count 0 2006.217.07:43:52.64#ibcon#read 3, iclass 40, count 0 2006.217.07:43:52.64#ibcon#about to read 4, iclass 40, count 0 2006.217.07:43:52.64#ibcon#read 4, iclass 40, count 0 2006.217.07:43:52.64#ibcon#about to read 5, iclass 40, count 0 2006.217.07:43:52.64#ibcon#read 5, iclass 40, count 0 2006.217.07:43:52.64#ibcon#about to read 6, iclass 40, count 0 2006.217.07:43:52.64#ibcon#read 6, iclass 40, count 0 2006.217.07:43:52.64#ibcon#end of sib2, iclass 40, count 0 2006.217.07:43:52.64#ibcon#*mode == 0, iclass 40, count 0 2006.217.07:43:52.64#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.217.07:43:52.64#ibcon#[25=BW32\r\n] 2006.217.07:43:52.64#ibcon#*before write, iclass 40, count 0 2006.217.07:43:52.64#ibcon#enter sib2, iclass 40, count 0 2006.217.07:43:52.64#ibcon#flushed, iclass 40, count 0 2006.217.07:43:52.64#ibcon#about to write, iclass 40, count 0 2006.217.07:43:52.64#ibcon#wrote, iclass 40, count 0 2006.217.07:43:52.64#ibcon#about to read 3, iclass 40, count 0 2006.217.07:43:52.67#ibcon#read 3, iclass 40, count 0 2006.217.07:43:52.67#ibcon#about to read 4, iclass 40, count 0 2006.217.07:43:52.67#ibcon#read 4, iclass 40, count 0 2006.217.07:43:52.67#ibcon#about to read 5, iclass 40, count 0 2006.217.07:43:52.67#ibcon#read 5, iclass 40, count 0 2006.217.07:43:52.67#ibcon#about to read 6, iclass 40, count 0 2006.217.07:43:52.67#ibcon#read 6, iclass 40, count 0 2006.217.07:43:52.67#ibcon#end of sib2, iclass 40, count 0 2006.217.07:43:52.67#ibcon#*after write, iclass 40, count 0 2006.217.07:43:52.67#ibcon#*before return 0, iclass 40, count 0 2006.217.07:43:52.67#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.217.07:43:52.67#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.217.07:43:52.67#ibcon#about to clear, iclass 40 cls_cnt 0 2006.217.07:43:52.67#ibcon#cleared, iclass 40 cls_cnt 0 2006.217.07:43:52.67$vc4f8/vbbw=wide 2006.217.07:43:52.67#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.217.07:43:52.67#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.217.07:43:52.67#ibcon#ireg 8 cls_cnt 0 2006.217.07:43:52.67#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.217.07:43:52.74#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.217.07:43:52.74#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.217.07:43:52.74#ibcon#enter wrdev, iclass 4, count 0 2006.217.07:43:52.74#ibcon#first serial, iclass 4, count 0 2006.217.07:43:52.74#ibcon#enter sib2, iclass 4, count 0 2006.217.07:43:52.74#ibcon#flushed, iclass 4, count 0 2006.217.07:43:52.74#ibcon#about to write, iclass 4, count 0 2006.217.07:43:52.74#ibcon#wrote, iclass 4, count 0 2006.217.07:43:52.74#ibcon#about to read 3, iclass 4, count 0 2006.217.07:43:52.76#ibcon#read 3, iclass 4, count 0 2006.217.07:43:52.76#ibcon#about to read 4, iclass 4, count 0 2006.217.07:43:52.76#ibcon#read 4, iclass 4, count 0 2006.217.07:43:52.76#ibcon#about to read 5, iclass 4, count 0 2006.217.07:43:52.76#ibcon#read 5, iclass 4, count 0 2006.217.07:43:52.76#ibcon#about to read 6, iclass 4, count 0 2006.217.07:43:52.76#ibcon#read 6, iclass 4, count 0 2006.217.07:43:52.76#ibcon#end of sib2, iclass 4, count 0 2006.217.07:43:52.76#ibcon#*mode == 0, iclass 4, count 0 2006.217.07:43:52.76#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.217.07:43:52.76#ibcon#[27=BW32\r\n] 2006.217.07:43:52.76#ibcon#*before write, iclass 4, count 0 2006.217.07:43:52.76#ibcon#enter sib2, iclass 4, count 0 2006.217.07:43:52.76#ibcon#flushed, iclass 4, count 0 2006.217.07:43:52.76#ibcon#about to write, iclass 4, count 0 2006.217.07:43:52.76#ibcon#wrote, iclass 4, count 0 2006.217.07:43:52.76#ibcon#about to read 3, iclass 4, count 0 2006.217.07:43:52.79#ibcon#read 3, iclass 4, count 0 2006.217.07:43:52.79#ibcon#about to read 4, iclass 4, count 0 2006.217.07:43:52.79#ibcon#read 4, iclass 4, count 0 2006.217.07:43:52.79#ibcon#about to read 5, iclass 4, count 0 2006.217.07:43:52.79#ibcon#read 5, iclass 4, count 0 2006.217.07:43:52.79#ibcon#about to read 6, iclass 4, count 0 2006.217.07:43:52.79#ibcon#read 6, iclass 4, count 0 2006.217.07:43:52.79#ibcon#end of sib2, iclass 4, count 0 2006.217.07:43:52.79#ibcon#*after write, iclass 4, count 0 2006.217.07:43:52.79#ibcon#*before return 0, iclass 4, count 0 2006.217.07:43:52.79#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.217.07:43:52.79#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.217.07:43:52.79#ibcon#about to clear, iclass 4 cls_cnt 0 2006.217.07:43:52.79#ibcon#cleared, iclass 4 cls_cnt 0 2006.217.07:43:52.79$4f8m12a/ifd4f 2006.217.07:43:52.79$ifd4f/lo= 2006.217.07:43:52.79$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.217.07:43:52.80$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.217.07:43:52.80$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.217.07:43:52.80$ifd4f/patch= 2006.217.07:43:52.80$ifd4f/patch=lo1,a1,a2,a3,a4 2006.217.07:43:52.80$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.217.07:43:52.80$ifd4f/patch=lo3,a5,a6,a7,a8 2006.217.07:43:52.80$4f8m12a/"form=m,16.000,1:2 2006.217.07:43:52.80$4f8m12a/"tpicd 2006.217.07:43:52.80$4f8m12a/echo=off 2006.217.07:43:52.80$4f8m12a/xlog=off 2006.217.07:43:52.80:!2006.217.07:44:20 2006.217.07:43:59.14#trakl#Source acquired 2006.217.07:43:59.14#flagr#flagr/antenna,acquired 2006.217.07:44:20.01:preob 2006.217.07:44:21.14/onsource/TRACKING 2006.217.07:44:21.14:!2006.217.07:44:30 2006.217.07:44:30.00:data_valid=on 2006.217.07:44:30.00:midob 2006.217.07:44:30.14/onsource/TRACKING 2006.217.07:44:30.15/wx/31.28,1008.6,62 2006.217.07:44:30.22/cable/+6.3848E-03 2006.217.07:44:31.31/va/01,05,usb,yes,32,33 2006.217.07:44:31.31/va/02,04,usb,yes,29,31 2006.217.07:44:31.31/va/03,04,usb,yes,28,28 2006.217.07:44:31.31/va/04,04,usb,yes,31,33 2006.217.07:44:31.31/va/05,07,usb,yes,33,35 2006.217.07:44:31.31/va/06,06,usb,yes,32,32 2006.217.07:44:31.31/va/07,06,usb,yes,33,32 2006.217.07:44:31.31/va/08,07,usb,yes,31,30 2006.217.07:44:31.54/valo/01,532.99,yes,locked 2006.217.07:44:31.54/valo/02,572.99,yes,locked 2006.217.07:44:31.54/valo/03,672.99,yes,locked 2006.217.07:44:31.54/valo/04,832.99,yes,locked 2006.217.07:44:31.54/valo/05,652.99,yes,locked 2006.217.07:44:31.54/valo/06,772.99,yes,locked 2006.217.07:44:31.54/valo/07,832.99,yes,locked 2006.217.07:44:31.54/valo/08,852.99,yes,locked 2006.217.07:44:32.63/vb/01,04,usb,yes,31,29 2006.217.07:44:32.63/vb/02,04,usb,yes,32,34 2006.217.07:44:32.63/vb/03,04,usb,yes,29,32 2006.217.07:44:32.63/vb/04,04,usb,yes,29,30 2006.217.07:44:32.63/vb/05,04,usb,yes,28,32 2006.217.07:44:32.63/vb/06,04,usb,yes,29,32 2006.217.07:44:32.63/vb/07,04,usb,yes,31,31 2006.217.07:44:32.63/vb/08,04,usb,yes,28,32 2006.217.07:44:32.86/vblo/01,632.99,yes,locked 2006.217.07:44:32.86/vblo/02,640.99,yes,locked 2006.217.07:44:32.86/vblo/03,656.99,yes,locked 2006.217.07:44:32.86/vblo/04,712.99,yes,locked 2006.217.07:44:32.86/vblo/05,744.99,yes,locked 2006.217.07:44:32.86/vblo/06,752.99,yes,locked 2006.217.07:44:32.86/vblo/07,734.99,yes,locked 2006.217.07:44:32.86/vblo/08,744.99,yes,locked 2006.217.07:44:33.01/vabw/8 2006.217.07:44:33.16/vbbw/8 2006.217.07:44:33.25/xfe/off,on,15.2 2006.217.07:44:33.62/ifatt/23,28,28,28 2006.217.07:44:34.07/fmout-gps/S +4.27E-07 2006.217.07:44:34.12:!2006.217.07:45:30 2006.217.07:45:30.01:data_valid=off 2006.217.07:45:30.01:postob 2006.217.07:45:30.10/cable/+6.3854E-03 2006.217.07:45:30.10/wx/31.28,1008.6,62 2006.217.07:45:31.06/fmout-gps/S +4.23E-07 2006.217.07:45:31.06:scan_name=217-0746,k06217,100 2006.217.07:45:31.06:source=1004+141,100741.50,135629.6,2000.0,ccw 2006.217.07:45:31.14#flagr#flagr/antenna,new-source 2006.217.07:45:32.14:checkk5 2006.217.07:45:32.53/chk_autoobs//k5ts1/ autoobs is running! 2006.217.07:45:32.90/chk_autoobs//k5ts2/ autoobs is running! 2006.217.07:45:33.28/chk_autoobs//k5ts3/ autoobs is running! 2006.217.07:45:33.65/chk_autoobs//k5ts4/ autoobs is running! 2006.217.07:45:34.01/chk_obsdata//k5ts1/T2170744??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:45:34.38/chk_obsdata//k5ts2/T2170744??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:45:34.75/chk_obsdata//k5ts3/T2170744??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:45:35.11/chk_obsdata//k5ts4/T2170744??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:45:35.80/k5log//k5ts1_log_newline 2006.217.07:45:36.50/k5log//k5ts2_log_newline 2006.217.07:45:37.19/k5log//k5ts3_log_newline 2006.217.07:45:37.90/k5log//k5ts4_log_newline 2006.217.07:45:37.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.217.07:45:37.92:4f8m12a=1 2006.217.07:45:37.92$4f8m12a/echo=on 2006.217.07:45:37.92$4f8m12a/pcalon 2006.217.07:45:37.92$pcalon/"no phase cal control is implemented here 2006.217.07:45:37.92$4f8m12a/"tpicd=stop 2006.217.07:45:37.92$4f8m12a/vc4f8 2006.217.07:45:37.92$vc4f8/valo=1,532.99 2006.217.07:45:37.93#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.217.07:45:37.93#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.217.07:45:37.93#ibcon#ireg 17 cls_cnt 0 2006.217.07:45:37.93#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.217.07:45:37.93#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.217.07:45:37.93#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.217.07:45:37.93#ibcon#enter wrdev, iclass 17, count 0 2006.217.07:45:37.93#ibcon#first serial, iclass 17, count 0 2006.217.07:45:37.93#ibcon#enter sib2, iclass 17, count 0 2006.217.07:45:37.93#ibcon#flushed, iclass 17, count 0 2006.217.07:45:37.93#ibcon#about to write, iclass 17, count 0 2006.217.07:45:37.93#ibcon#wrote, iclass 17, count 0 2006.217.07:45:37.93#ibcon#about to read 3, iclass 17, count 0 2006.217.07:45:37.97#ibcon#read 3, iclass 17, count 0 2006.217.07:45:37.97#ibcon#about to read 4, iclass 17, count 0 2006.217.07:45:37.97#ibcon#read 4, iclass 17, count 0 2006.217.07:45:37.97#ibcon#about to read 5, iclass 17, count 0 2006.217.07:45:37.97#ibcon#read 5, iclass 17, count 0 2006.217.07:45:37.97#ibcon#about to read 6, iclass 17, count 0 2006.217.07:45:37.97#ibcon#read 6, iclass 17, count 0 2006.217.07:45:37.97#ibcon#end of sib2, iclass 17, count 0 2006.217.07:45:37.97#ibcon#*mode == 0, iclass 17, count 0 2006.217.07:45:37.97#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.217.07:45:37.97#ibcon#[26=FRQ=01,532.99\r\n] 2006.217.07:45:37.97#ibcon#*before write, iclass 17, count 0 2006.217.07:45:37.97#ibcon#enter sib2, iclass 17, count 0 2006.217.07:45:37.97#ibcon#flushed, iclass 17, count 0 2006.217.07:45:37.97#ibcon#about to write, iclass 17, count 0 2006.217.07:45:37.97#ibcon#wrote, iclass 17, count 0 2006.217.07:45:37.97#ibcon#about to read 3, iclass 17, count 0 2006.217.07:45:38.01#ibcon#read 3, iclass 17, count 0 2006.217.07:45:38.01#ibcon#about to read 4, iclass 17, count 0 2006.217.07:45:38.01#ibcon#read 4, iclass 17, count 0 2006.217.07:45:38.01#ibcon#about to read 5, iclass 17, count 0 2006.217.07:45:38.01#ibcon#read 5, iclass 17, count 0 2006.217.07:45:38.01#ibcon#about to read 6, iclass 17, count 0 2006.217.07:45:38.01#ibcon#read 6, iclass 17, count 0 2006.217.07:45:38.01#ibcon#end of sib2, iclass 17, count 0 2006.217.07:45:38.01#ibcon#*after write, iclass 17, count 0 2006.217.07:45:38.01#ibcon#*before return 0, iclass 17, count 0 2006.217.07:45:38.01#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.217.07:45:38.01#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.217.07:45:38.01#ibcon#about to clear, iclass 17 cls_cnt 0 2006.217.07:45:38.01#ibcon#cleared, iclass 17 cls_cnt 0 2006.217.07:45:38.01$vc4f8/va=1,5 2006.217.07:45:38.01#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.217.07:45:38.01#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.217.07:45:38.01#ibcon#ireg 11 cls_cnt 2 2006.217.07:45:38.01#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.217.07:45:38.01#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.217.07:45:38.01#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.217.07:45:38.01#ibcon#enter wrdev, iclass 19, count 2 2006.217.07:45:38.01#ibcon#first serial, iclass 19, count 2 2006.217.07:45:38.01#ibcon#enter sib2, iclass 19, count 2 2006.217.07:45:38.01#ibcon#flushed, iclass 19, count 2 2006.217.07:45:38.01#ibcon#about to write, iclass 19, count 2 2006.217.07:45:38.01#ibcon#wrote, iclass 19, count 2 2006.217.07:45:38.01#ibcon#about to read 3, iclass 19, count 2 2006.217.07:45:38.04#ibcon#read 3, iclass 19, count 2 2006.217.07:45:38.04#ibcon#about to read 4, iclass 19, count 2 2006.217.07:45:38.04#ibcon#read 4, iclass 19, count 2 2006.217.07:45:38.04#ibcon#about to read 5, iclass 19, count 2 2006.217.07:45:38.04#ibcon#read 5, iclass 19, count 2 2006.217.07:45:38.04#ibcon#about to read 6, iclass 19, count 2 2006.217.07:45:38.04#ibcon#read 6, iclass 19, count 2 2006.217.07:45:38.04#ibcon#end of sib2, iclass 19, count 2 2006.217.07:45:38.04#ibcon#*mode == 0, iclass 19, count 2 2006.217.07:45:38.04#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.217.07:45:38.04#ibcon#[25=AT01-05\r\n] 2006.217.07:45:38.04#ibcon#*before write, iclass 19, count 2 2006.217.07:45:38.04#ibcon#enter sib2, iclass 19, count 2 2006.217.07:45:38.04#ibcon#flushed, iclass 19, count 2 2006.217.07:45:38.04#ibcon#about to write, iclass 19, count 2 2006.217.07:45:38.04#ibcon#wrote, iclass 19, count 2 2006.217.07:45:38.04#ibcon#about to read 3, iclass 19, count 2 2006.217.07:45:38.07#ibcon#read 3, iclass 19, count 2 2006.217.07:45:38.07#ibcon#about to read 4, iclass 19, count 2 2006.217.07:45:38.07#ibcon#read 4, iclass 19, count 2 2006.217.07:45:38.07#ibcon#about to read 5, iclass 19, count 2 2006.217.07:45:38.07#ibcon#read 5, iclass 19, count 2 2006.217.07:45:38.07#ibcon#about to read 6, iclass 19, count 2 2006.217.07:45:38.07#ibcon#read 6, iclass 19, count 2 2006.217.07:45:38.07#ibcon#end of sib2, iclass 19, count 2 2006.217.07:45:38.07#ibcon#*after write, iclass 19, count 2 2006.217.07:45:38.07#ibcon#*before return 0, iclass 19, count 2 2006.217.07:45:38.07#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.217.07:45:38.07#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.217.07:45:38.07#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.217.07:45:38.07#ibcon#ireg 7 cls_cnt 0 2006.217.07:45:38.07#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.217.07:45:38.18#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.217.07:45:38.18#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.217.07:45:38.18#ibcon#enter wrdev, iclass 19, count 0 2006.217.07:45:38.18#ibcon#first serial, iclass 19, count 0 2006.217.07:45:38.18#ibcon#enter sib2, iclass 19, count 0 2006.217.07:45:38.18#ibcon#flushed, iclass 19, count 0 2006.217.07:45:38.18#ibcon#about to write, iclass 19, count 0 2006.217.07:45:38.18#ibcon#wrote, iclass 19, count 0 2006.217.07:45:38.18#ibcon#about to read 3, iclass 19, count 0 2006.217.07:45:38.20#ibcon#read 3, iclass 19, count 0 2006.217.07:45:38.20#ibcon#about to read 4, iclass 19, count 0 2006.217.07:45:38.20#ibcon#read 4, iclass 19, count 0 2006.217.07:45:38.20#ibcon#about to read 5, iclass 19, count 0 2006.217.07:45:38.20#ibcon#read 5, iclass 19, count 0 2006.217.07:45:38.20#ibcon#about to read 6, iclass 19, count 0 2006.217.07:45:38.20#ibcon#read 6, iclass 19, count 0 2006.217.07:45:38.20#ibcon#end of sib2, iclass 19, count 0 2006.217.07:45:38.20#ibcon#*mode == 0, iclass 19, count 0 2006.217.07:45:38.20#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.217.07:45:38.20#ibcon#[25=USB\r\n] 2006.217.07:45:38.20#ibcon#*before write, iclass 19, count 0 2006.217.07:45:38.20#ibcon#enter sib2, iclass 19, count 0 2006.217.07:45:38.20#ibcon#flushed, iclass 19, count 0 2006.217.07:45:38.20#ibcon#about to write, iclass 19, count 0 2006.217.07:45:38.20#ibcon#wrote, iclass 19, count 0 2006.217.07:45:38.20#ibcon#about to read 3, iclass 19, count 0 2006.217.07:45:38.23#ibcon#read 3, iclass 19, count 0 2006.217.07:45:38.23#ibcon#about to read 4, iclass 19, count 0 2006.217.07:45:38.23#ibcon#read 4, iclass 19, count 0 2006.217.07:45:38.23#ibcon#about to read 5, iclass 19, count 0 2006.217.07:45:38.23#ibcon#read 5, iclass 19, count 0 2006.217.07:45:38.23#ibcon#about to read 6, iclass 19, count 0 2006.217.07:45:38.23#ibcon#read 6, iclass 19, count 0 2006.217.07:45:38.23#ibcon#end of sib2, iclass 19, count 0 2006.217.07:45:38.23#ibcon#*after write, iclass 19, count 0 2006.217.07:45:38.23#ibcon#*before return 0, iclass 19, count 0 2006.217.07:45:38.23#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.217.07:45:38.23#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.217.07:45:38.23#ibcon#about to clear, iclass 19 cls_cnt 0 2006.217.07:45:38.23#ibcon#cleared, iclass 19 cls_cnt 0 2006.217.07:45:38.23$vc4f8/valo=2,572.99 2006.217.07:45:38.23#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.217.07:45:38.23#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.217.07:45:38.23#ibcon#ireg 17 cls_cnt 0 2006.217.07:45:38.23#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.217.07:45:38.23#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.217.07:45:38.23#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.217.07:45:38.23#ibcon#enter wrdev, iclass 21, count 0 2006.217.07:45:38.23#ibcon#first serial, iclass 21, count 0 2006.217.07:45:38.23#ibcon#enter sib2, iclass 21, count 0 2006.217.07:45:38.23#ibcon#flushed, iclass 21, count 0 2006.217.07:45:38.23#ibcon#about to write, iclass 21, count 0 2006.217.07:45:38.23#ibcon#wrote, iclass 21, count 0 2006.217.07:45:38.23#ibcon#about to read 3, iclass 21, count 0 2006.217.07:45:38.25#ibcon#read 3, iclass 21, count 0 2006.217.07:45:38.25#ibcon#about to read 4, iclass 21, count 0 2006.217.07:45:38.25#ibcon#read 4, iclass 21, count 0 2006.217.07:45:38.25#ibcon#about to read 5, iclass 21, count 0 2006.217.07:45:38.25#ibcon#read 5, iclass 21, count 0 2006.217.07:45:38.25#ibcon#about to read 6, iclass 21, count 0 2006.217.07:45:38.25#ibcon#read 6, iclass 21, count 0 2006.217.07:45:38.25#ibcon#end of sib2, iclass 21, count 0 2006.217.07:45:38.25#ibcon#*mode == 0, iclass 21, count 0 2006.217.07:45:38.25#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.217.07:45:38.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.217.07:45:38.25#ibcon#*before write, iclass 21, count 0 2006.217.07:45:38.25#ibcon#enter sib2, iclass 21, count 0 2006.217.07:45:38.25#ibcon#flushed, iclass 21, count 0 2006.217.07:45:38.25#ibcon#about to write, iclass 21, count 0 2006.217.07:45:38.25#ibcon#wrote, iclass 21, count 0 2006.217.07:45:38.25#ibcon#about to read 3, iclass 21, count 0 2006.217.07:45:38.29#ibcon#read 3, iclass 21, count 0 2006.217.07:45:38.29#ibcon#about to read 4, iclass 21, count 0 2006.217.07:45:38.29#ibcon#read 4, iclass 21, count 0 2006.217.07:45:38.29#ibcon#about to read 5, iclass 21, count 0 2006.217.07:45:38.29#ibcon#read 5, iclass 21, count 0 2006.217.07:45:38.29#ibcon#about to read 6, iclass 21, count 0 2006.217.07:45:38.29#ibcon#read 6, iclass 21, count 0 2006.217.07:45:38.29#ibcon#end of sib2, iclass 21, count 0 2006.217.07:45:38.29#ibcon#*after write, iclass 21, count 0 2006.217.07:45:38.29#ibcon#*before return 0, iclass 21, count 0 2006.217.07:45:38.29#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.217.07:45:38.29#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.217.07:45:38.29#ibcon#about to clear, iclass 21 cls_cnt 0 2006.217.07:45:38.29#ibcon#cleared, iclass 21 cls_cnt 0 2006.217.07:45:38.29$vc4f8/va=2,4 2006.217.07:45:38.29#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.217.07:45:38.29#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.217.07:45:38.29#ibcon#ireg 11 cls_cnt 2 2006.217.07:45:38.29#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.217.07:45:38.35#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.217.07:45:38.35#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.217.07:45:38.35#ibcon#enter wrdev, iclass 23, count 2 2006.217.07:45:38.35#ibcon#first serial, iclass 23, count 2 2006.217.07:45:38.35#ibcon#enter sib2, iclass 23, count 2 2006.217.07:45:38.35#ibcon#flushed, iclass 23, count 2 2006.217.07:45:38.35#ibcon#about to write, iclass 23, count 2 2006.217.07:45:38.35#ibcon#wrote, iclass 23, count 2 2006.217.07:45:38.35#ibcon#about to read 3, iclass 23, count 2 2006.217.07:45:38.37#ibcon#read 3, iclass 23, count 2 2006.217.07:45:38.37#ibcon#about to read 4, iclass 23, count 2 2006.217.07:45:38.37#ibcon#read 4, iclass 23, count 2 2006.217.07:45:38.37#ibcon#about to read 5, iclass 23, count 2 2006.217.07:45:38.37#ibcon#read 5, iclass 23, count 2 2006.217.07:45:38.37#ibcon#about to read 6, iclass 23, count 2 2006.217.07:45:38.37#ibcon#read 6, iclass 23, count 2 2006.217.07:45:38.37#ibcon#end of sib2, iclass 23, count 2 2006.217.07:45:38.37#ibcon#*mode == 0, iclass 23, count 2 2006.217.07:45:38.37#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.217.07:45:38.37#ibcon#[25=AT02-04\r\n] 2006.217.07:45:38.37#ibcon#*before write, iclass 23, count 2 2006.217.07:45:38.37#ibcon#enter sib2, iclass 23, count 2 2006.217.07:45:38.37#ibcon#flushed, iclass 23, count 2 2006.217.07:45:38.37#ibcon#about to write, iclass 23, count 2 2006.217.07:45:38.37#ibcon#wrote, iclass 23, count 2 2006.217.07:45:38.37#ibcon#about to read 3, iclass 23, count 2 2006.217.07:45:38.40#ibcon#read 3, iclass 23, count 2 2006.217.07:45:38.40#ibcon#about to read 4, iclass 23, count 2 2006.217.07:45:38.40#ibcon#read 4, iclass 23, count 2 2006.217.07:45:38.40#ibcon#about to read 5, iclass 23, count 2 2006.217.07:45:38.40#ibcon#read 5, iclass 23, count 2 2006.217.07:45:38.40#ibcon#about to read 6, iclass 23, count 2 2006.217.07:45:38.40#ibcon#read 6, iclass 23, count 2 2006.217.07:45:38.40#ibcon#end of sib2, iclass 23, count 2 2006.217.07:45:38.40#ibcon#*after write, iclass 23, count 2 2006.217.07:45:38.40#ibcon#*before return 0, iclass 23, count 2 2006.217.07:45:38.40#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.217.07:45:38.40#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.217.07:45:38.40#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.217.07:45:38.40#ibcon#ireg 7 cls_cnt 0 2006.217.07:45:38.40#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.217.07:45:38.52#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.217.07:45:38.52#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.217.07:45:38.52#ibcon#enter wrdev, iclass 23, count 0 2006.217.07:45:38.52#ibcon#first serial, iclass 23, count 0 2006.217.07:45:38.52#ibcon#enter sib2, iclass 23, count 0 2006.217.07:45:38.52#ibcon#flushed, iclass 23, count 0 2006.217.07:45:38.52#ibcon#about to write, iclass 23, count 0 2006.217.07:45:38.52#ibcon#wrote, iclass 23, count 0 2006.217.07:45:38.52#ibcon#about to read 3, iclass 23, count 0 2006.217.07:45:38.55#ibcon#read 3, iclass 23, count 0 2006.217.07:45:38.55#ibcon#about to read 4, iclass 23, count 0 2006.217.07:45:38.55#ibcon#read 4, iclass 23, count 0 2006.217.07:45:38.55#ibcon#about to read 5, iclass 23, count 0 2006.217.07:45:38.55#ibcon#read 5, iclass 23, count 0 2006.217.07:45:38.55#ibcon#about to read 6, iclass 23, count 0 2006.217.07:45:38.55#ibcon#read 6, iclass 23, count 0 2006.217.07:45:38.55#ibcon#end of sib2, iclass 23, count 0 2006.217.07:45:38.55#ibcon#*mode == 0, iclass 23, count 0 2006.217.07:45:38.55#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.217.07:45:38.55#ibcon#[25=USB\r\n] 2006.217.07:45:38.55#ibcon#*before write, iclass 23, count 0 2006.217.07:45:38.55#ibcon#enter sib2, iclass 23, count 0 2006.217.07:45:38.55#ibcon#flushed, iclass 23, count 0 2006.217.07:45:38.55#ibcon#about to write, iclass 23, count 0 2006.217.07:45:38.55#ibcon#wrote, iclass 23, count 0 2006.217.07:45:38.55#ibcon#about to read 3, iclass 23, count 0 2006.217.07:45:38.57#ibcon#read 3, iclass 23, count 0 2006.217.07:45:38.57#ibcon#about to read 4, iclass 23, count 0 2006.217.07:45:38.57#ibcon#read 4, iclass 23, count 0 2006.217.07:45:38.57#ibcon#about to read 5, iclass 23, count 0 2006.217.07:45:38.57#ibcon#read 5, iclass 23, count 0 2006.217.07:45:38.57#ibcon#about to read 6, iclass 23, count 0 2006.217.07:45:38.57#ibcon#read 6, iclass 23, count 0 2006.217.07:45:38.57#ibcon#end of sib2, iclass 23, count 0 2006.217.07:45:38.57#ibcon#*after write, iclass 23, count 0 2006.217.07:45:38.57#ibcon#*before return 0, iclass 23, count 0 2006.217.07:45:38.57#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.217.07:45:38.57#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.217.07:45:38.57#ibcon#about to clear, iclass 23 cls_cnt 0 2006.217.07:45:38.57#ibcon#cleared, iclass 23 cls_cnt 0 2006.217.07:45:38.57$vc4f8/valo=3,672.99 2006.217.07:45:38.57#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.217.07:45:38.57#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.217.07:45:38.57#ibcon#ireg 17 cls_cnt 0 2006.217.07:45:38.57#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.217.07:45:38.57#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.217.07:45:38.57#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.217.07:45:38.57#ibcon#enter wrdev, iclass 25, count 0 2006.217.07:45:38.57#ibcon#first serial, iclass 25, count 0 2006.217.07:45:38.57#ibcon#enter sib2, iclass 25, count 0 2006.217.07:45:38.57#ibcon#flushed, iclass 25, count 0 2006.217.07:45:38.57#ibcon#about to write, iclass 25, count 0 2006.217.07:45:38.57#ibcon#wrote, iclass 25, count 0 2006.217.07:45:38.57#ibcon#about to read 3, iclass 25, count 0 2006.217.07:45:38.59#ibcon#read 3, iclass 25, count 0 2006.217.07:45:38.59#ibcon#about to read 4, iclass 25, count 0 2006.217.07:45:38.59#ibcon#read 4, iclass 25, count 0 2006.217.07:45:38.59#ibcon#about to read 5, iclass 25, count 0 2006.217.07:45:38.59#ibcon#read 5, iclass 25, count 0 2006.217.07:45:38.59#ibcon#about to read 6, iclass 25, count 0 2006.217.07:45:38.59#ibcon#read 6, iclass 25, count 0 2006.217.07:45:38.59#ibcon#end of sib2, iclass 25, count 0 2006.217.07:45:38.59#ibcon#*mode == 0, iclass 25, count 0 2006.217.07:45:38.59#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.217.07:45:38.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.217.07:45:38.59#ibcon#*before write, iclass 25, count 0 2006.217.07:45:38.59#ibcon#enter sib2, iclass 25, count 0 2006.217.07:45:38.59#ibcon#flushed, iclass 25, count 0 2006.217.07:45:38.59#ibcon#about to write, iclass 25, count 0 2006.217.07:45:38.59#ibcon#wrote, iclass 25, count 0 2006.217.07:45:38.59#ibcon#about to read 3, iclass 25, count 0 2006.217.07:45:38.64#ibcon#read 3, iclass 25, count 0 2006.217.07:45:38.64#ibcon#about to read 4, iclass 25, count 0 2006.217.07:45:38.64#ibcon#read 4, iclass 25, count 0 2006.217.07:45:38.64#ibcon#about to read 5, iclass 25, count 0 2006.217.07:45:38.64#ibcon#read 5, iclass 25, count 0 2006.217.07:45:38.64#ibcon#about to read 6, iclass 25, count 0 2006.217.07:45:38.64#ibcon#read 6, iclass 25, count 0 2006.217.07:45:38.64#ibcon#end of sib2, iclass 25, count 0 2006.217.07:45:38.64#ibcon#*after write, iclass 25, count 0 2006.217.07:45:38.64#ibcon#*before return 0, iclass 25, count 0 2006.217.07:45:38.64#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.217.07:45:38.64#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.217.07:45:38.64#ibcon#about to clear, iclass 25 cls_cnt 0 2006.217.07:45:38.64#ibcon#cleared, iclass 25 cls_cnt 0 2006.217.07:45:38.64$vc4f8/va=3,4 2006.217.07:45:38.64#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.217.07:45:38.64#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.217.07:45:38.64#ibcon#ireg 11 cls_cnt 2 2006.217.07:45:38.64#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.217.07:45:38.68#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.217.07:45:38.68#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.217.07:45:38.68#ibcon#enter wrdev, iclass 27, count 2 2006.217.07:45:38.68#ibcon#first serial, iclass 27, count 2 2006.217.07:45:38.68#ibcon#enter sib2, iclass 27, count 2 2006.217.07:45:38.68#ibcon#flushed, iclass 27, count 2 2006.217.07:45:38.68#ibcon#about to write, iclass 27, count 2 2006.217.07:45:38.68#ibcon#wrote, iclass 27, count 2 2006.217.07:45:38.68#ibcon#about to read 3, iclass 27, count 2 2006.217.07:45:38.70#ibcon#read 3, iclass 27, count 2 2006.217.07:45:38.70#ibcon#about to read 4, iclass 27, count 2 2006.217.07:45:38.70#ibcon#read 4, iclass 27, count 2 2006.217.07:45:38.70#ibcon#about to read 5, iclass 27, count 2 2006.217.07:45:38.70#ibcon#read 5, iclass 27, count 2 2006.217.07:45:38.70#ibcon#about to read 6, iclass 27, count 2 2006.217.07:45:38.70#ibcon#read 6, iclass 27, count 2 2006.217.07:45:38.70#ibcon#end of sib2, iclass 27, count 2 2006.217.07:45:38.70#ibcon#*mode == 0, iclass 27, count 2 2006.217.07:45:38.70#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.217.07:45:38.70#ibcon#[25=AT03-04\r\n] 2006.217.07:45:38.70#ibcon#*before write, iclass 27, count 2 2006.217.07:45:38.70#ibcon#enter sib2, iclass 27, count 2 2006.217.07:45:38.70#ibcon#flushed, iclass 27, count 2 2006.217.07:45:38.70#ibcon#about to write, iclass 27, count 2 2006.217.07:45:38.70#ibcon#wrote, iclass 27, count 2 2006.217.07:45:38.70#ibcon#about to read 3, iclass 27, count 2 2006.217.07:45:38.73#ibcon#read 3, iclass 27, count 2 2006.217.07:45:38.73#ibcon#about to read 4, iclass 27, count 2 2006.217.07:45:38.73#ibcon#read 4, iclass 27, count 2 2006.217.07:45:38.73#ibcon#about to read 5, iclass 27, count 2 2006.217.07:45:38.73#ibcon#read 5, iclass 27, count 2 2006.217.07:45:38.73#ibcon#about to read 6, iclass 27, count 2 2006.217.07:45:38.73#ibcon#read 6, iclass 27, count 2 2006.217.07:45:38.73#ibcon#end of sib2, iclass 27, count 2 2006.217.07:45:38.73#ibcon#*after write, iclass 27, count 2 2006.217.07:45:38.73#ibcon#*before return 0, iclass 27, count 2 2006.217.07:45:38.73#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.217.07:45:38.73#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.217.07:45:38.73#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.217.07:45:38.73#ibcon#ireg 7 cls_cnt 0 2006.217.07:45:38.73#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.217.07:45:38.85#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.217.07:45:38.85#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.217.07:45:38.85#ibcon#enter wrdev, iclass 27, count 0 2006.217.07:45:38.85#ibcon#first serial, iclass 27, count 0 2006.217.07:45:38.85#ibcon#enter sib2, iclass 27, count 0 2006.217.07:45:38.85#ibcon#flushed, iclass 27, count 0 2006.217.07:45:38.85#ibcon#about to write, iclass 27, count 0 2006.217.07:45:38.85#ibcon#wrote, iclass 27, count 0 2006.217.07:45:38.85#ibcon#about to read 3, iclass 27, count 0 2006.217.07:45:38.87#ibcon#read 3, iclass 27, count 0 2006.217.07:45:38.87#ibcon#about to read 4, iclass 27, count 0 2006.217.07:45:38.87#ibcon#read 4, iclass 27, count 0 2006.217.07:45:38.87#ibcon#about to read 5, iclass 27, count 0 2006.217.07:45:38.87#ibcon#read 5, iclass 27, count 0 2006.217.07:45:38.87#ibcon#about to read 6, iclass 27, count 0 2006.217.07:45:38.87#ibcon#read 6, iclass 27, count 0 2006.217.07:45:38.87#ibcon#end of sib2, iclass 27, count 0 2006.217.07:45:38.87#ibcon#*mode == 0, iclass 27, count 0 2006.217.07:45:38.87#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.217.07:45:38.87#ibcon#[25=USB\r\n] 2006.217.07:45:38.87#ibcon#*before write, iclass 27, count 0 2006.217.07:45:38.87#ibcon#enter sib2, iclass 27, count 0 2006.217.07:45:38.87#ibcon#flushed, iclass 27, count 0 2006.217.07:45:38.87#ibcon#about to write, iclass 27, count 0 2006.217.07:45:38.87#ibcon#wrote, iclass 27, count 0 2006.217.07:45:38.87#ibcon#about to read 3, iclass 27, count 0 2006.217.07:45:38.90#ibcon#read 3, iclass 27, count 0 2006.217.07:45:38.90#ibcon#about to read 4, iclass 27, count 0 2006.217.07:45:38.90#ibcon#read 4, iclass 27, count 0 2006.217.07:45:38.90#ibcon#about to read 5, iclass 27, count 0 2006.217.07:45:38.90#ibcon#read 5, iclass 27, count 0 2006.217.07:45:38.90#ibcon#about to read 6, iclass 27, count 0 2006.217.07:45:38.90#ibcon#read 6, iclass 27, count 0 2006.217.07:45:38.90#ibcon#end of sib2, iclass 27, count 0 2006.217.07:45:38.90#ibcon#*after write, iclass 27, count 0 2006.217.07:45:38.90#ibcon#*before return 0, iclass 27, count 0 2006.217.07:45:38.90#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.217.07:45:38.90#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.217.07:45:38.90#ibcon#about to clear, iclass 27 cls_cnt 0 2006.217.07:45:38.90#ibcon#cleared, iclass 27 cls_cnt 0 2006.217.07:45:38.90$vc4f8/valo=4,832.99 2006.217.07:45:38.90#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.217.07:45:38.90#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.217.07:45:38.90#ibcon#ireg 17 cls_cnt 0 2006.217.07:45:38.90#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.217.07:45:38.90#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.217.07:45:38.90#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.217.07:45:38.90#ibcon#enter wrdev, iclass 29, count 0 2006.217.07:45:38.90#ibcon#first serial, iclass 29, count 0 2006.217.07:45:38.90#ibcon#enter sib2, iclass 29, count 0 2006.217.07:45:38.90#ibcon#flushed, iclass 29, count 0 2006.217.07:45:38.90#ibcon#about to write, iclass 29, count 0 2006.217.07:45:38.90#ibcon#wrote, iclass 29, count 0 2006.217.07:45:38.90#ibcon#about to read 3, iclass 29, count 0 2006.217.07:45:38.92#ibcon#read 3, iclass 29, count 0 2006.217.07:45:38.92#ibcon#about to read 4, iclass 29, count 0 2006.217.07:45:38.92#ibcon#read 4, iclass 29, count 0 2006.217.07:45:38.92#ibcon#about to read 5, iclass 29, count 0 2006.217.07:45:38.92#ibcon#read 5, iclass 29, count 0 2006.217.07:45:38.92#ibcon#about to read 6, iclass 29, count 0 2006.217.07:45:38.92#ibcon#read 6, iclass 29, count 0 2006.217.07:45:38.92#ibcon#end of sib2, iclass 29, count 0 2006.217.07:45:38.92#ibcon#*mode == 0, iclass 29, count 0 2006.217.07:45:38.92#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.217.07:45:38.92#ibcon#[26=FRQ=04,832.99\r\n] 2006.217.07:45:38.92#ibcon#*before write, iclass 29, count 0 2006.217.07:45:38.92#ibcon#enter sib2, iclass 29, count 0 2006.217.07:45:38.92#ibcon#flushed, iclass 29, count 0 2006.217.07:45:38.92#ibcon#about to write, iclass 29, count 0 2006.217.07:45:38.92#ibcon#wrote, iclass 29, count 0 2006.217.07:45:38.92#ibcon#about to read 3, iclass 29, count 0 2006.217.07:45:38.96#ibcon#read 3, iclass 29, count 0 2006.217.07:45:38.96#ibcon#about to read 4, iclass 29, count 0 2006.217.07:45:38.96#ibcon#read 4, iclass 29, count 0 2006.217.07:45:38.96#ibcon#about to read 5, iclass 29, count 0 2006.217.07:45:38.96#ibcon#read 5, iclass 29, count 0 2006.217.07:45:38.96#ibcon#about to read 6, iclass 29, count 0 2006.217.07:45:38.96#ibcon#read 6, iclass 29, count 0 2006.217.07:45:38.96#ibcon#end of sib2, iclass 29, count 0 2006.217.07:45:38.96#ibcon#*after write, iclass 29, count 0 2006.217.07:45:38.96#ibcon#*before return 0, iclass 29, count 0 2006.217.07:45:38.96#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.217.07:45:38.96#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.217.07:45:38.96#ibcon#about to clear, iclass 29 cls_cnt 0 2006.217.07:45:38.96#ibcon#cleared, iclass 29 cls_cnt 0 2006.217.07:45:38.96$vc4f8/va=4,4 2006.217.07:45:38.96#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.217.07:45:38.96#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.217.07:45:38.96#ibcon#ireg 11 cls_cnt 2 2006.217.07:45:38.96#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.217.07:45:39.02#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.217.07:45:39.02#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.217.07:45:39.02#ibcon#enter wrdev, iclass 31, count 2 2006.217.07:45:39.02#ibcon#first serial, iclass 31, count 2 2006.217.07:45:39.02#ibcon#enter sib2, iclass 31, count 2 2006.217.07:45:39.02#ibcon#flushed, iclass 31, count 2 2006.217.07:45:39.02#ibcon#about to write, iclass 31, count 2 2006.217.07:45:39.02#ibcon#wrote, iclass 31, count 2 2006.217.07:45:39.02#ibcon#about to read 3, iclass 31, count 2 2006.217.07:45:39.04#ibcon#read 3, iclass 31, count 2 2006.217.07:45:39.04#ibcon#about to read 4, iclass 31, count 2 2006.217.07:45:39.04#ibcon#read 4, iclass 31, count 2 2006.217.07:45:39.04#ibcon#about to read 5, iclass 31, count 2 2006.217.07:45:39.04#ibcon#read 5, iclass 31, count 2 2006.217.07:45:39.04#ibcon#about to read 6, iclass 31, count 2 2006.217.07:45:39.04#ibcon#read 6, iclass 31, count 2 2006.217.07:45:39.04#ibcon#end of sib2, iclass 31, count 2 2006.217.07:45:39.04#ibcon#*mode == 0, iclass 31, count 2 2006.217.07:45:39.04#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.217.07:45:39.04#ibcon#[25=AT04-04\r\n] 2006.217.07:45:39.04#ibcon#*before write, iclass 31, count 2 2006.217.07:45:39.04#ibcon#enter sib2, iclass 31, count 2 2006.217.07:45:39.04#ibcon#flushed, iclass 31, count 2 2006.217.07:45:39.04#ibcon#about to write, iclass 31, count 2 2006.217.07:45:39.04#ibcon#wrote, iclass 31, count 2 2006.217.07:45:39.04#ibcon#about to read 3, iclass 31, count 2 2006.217.07:45:39.07#ibcon#read 3, iclass 31, count 2 2006.217.07:45:39.07#ibcon#about to read 4, iclass 31, count 2 2006.217.07:45:39.07#ibcon#read 4, iclass 31, count 2 2006.217.07:45:39.07#ibcon#about to read 5, iclass 31, count 2 2006.217.07:45:39.07#ibcon#read 5, iclass 31, count 2 2006.217.07:45:39.07#ibcon#about to read 6, iclass 31, count 2 2006.217.07:45:39.07#ibcon#read 6, iclass 31, count 2 2006.217.07:45:39.07#ibcon#end of sib2, iclass 31, count 2 2006.217.07:45:39.07#ibcon#*after write, iclass 31, count 2 2006.217.07:45:39.07#ibcon#*before return 0, iclass 31, count 2 2006.217.07:45:39.07#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.217.07:45:39.07#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.217.07:45:39.07#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.217.07:45:39.07#ibcon#ireg 7 cls_cnt 0 2006.217.07:45:39.07#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.217.07:45:39.19#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.217.07:45:39.19#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.217.07:45:39.19#ibcon#enter wrdev, iclass 31, count 0 2006.217.07:45:39.19#ibcon#first serial, iclass 31, count 0 2006.217.07:45:39.19#ibcon#enter sib2, iclass 31, count 0 2006.217.07:45:39.19#ibcon#flushed, iclass 31, count 0 2006.217.07:45:39.19#ibcon#about to write, iclass 31, count 0 2006.217.07:45:39.19#ibcon#wrote, iclass 31, count 0 2006.217.07:45:39.19#ibcon#about to read 3, iclass 31, count 0 2006.217.07:45:39.21#ibcon#read 3, iclass 31, count 0 2006.217.07:45:39.21#ibcon#about to read 4, iclass 31, count 0 2006.217.07:45:39.21#ibcon#read 4, iclass 31, count 0 2006.217.07:45:39.21#ibcon#about to read 5, iclass 31, count 0 2006.217.07:45:39.21#ibcon#read 5, iclass 31, count 0 2006.217.07:45:39.21#ibcon#about to read 6, iclass 31, count 0 2006.217.07:45:39.21#ibcon#read 6, iclass 31, count 0 2006.217.07:45:39.21#ibcon#end of sib2, iclass 31, count 0 2006.217.07:45:39.21#ibcon#*mode == 0, iclass 31, count 0 2006.217.07:45:39.21#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.217.07:45:39.21#ibcon#[25=USB\r\n] 2006.217.07:45:39.21#ibcon#*before write, iclass 31, count 0 2006.217.07:45:39.21#ibcon#enter sib2, iclass 31, count 0 2006.217.07:45:39.21#ibcon#flushed, iclass 31, count 0 2006.217.07:45:39.21#ibcon#about to write, iclass 31, count 0 2006.217.07:45:39.21#ibcon#wrote, iclass 31, count 0 2006.217.07:45:39.21#ibcon#about to read 3, iclass 31, count 0 2006.217.07:45:39.24#ibcon#read 3, iclass 31, count 0 2006.217.07:45:39.24#ibcon#about to read 4, iclass 31, count 0 2006.217.07:45:39.24#ibcon#read 4, iclass 31, count 0 2006.217.07:45:39.24#ibcon#about to read 5, iclass 31, count 0 2006.217.07:45:39.24#ibcon#read 5, iclass 31, count 0 2006.217.07:45:39.24#ibcon#about to read 6, iclass 31, count 0 2006.217.07:45:39.24#ibcon#read 6, iclass 31, count 0 2006.217.07:45:39.24#ibcon#end of sib2, iclass 31, count 0 2006.217.07:45:39.24#ibcon#*after write, iclass 31, count 0 2006.217.07:45:39.24#ibcon#*before return 0, iclass 31, count 0 2006.217.07:45:39.24#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.217.07:45:39.24#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.217.07:45:39.24#ibcon#about to clear, iclass 31 cls_cnt 0 2006.217.07:45:39.24#ibcon#cleared, iclass 31 cls_cnt 0 2006.217.07:45:39.24$vc4f8/valo=5,652.99 2006.217.07:45:39.24#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.217.07:45:39.24#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.217.07:45:39.24#ibcon#ireg 17 cls_cnt 0 2006.217.07:45:39.24#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.217.07:45:39.24#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.217.07:45:39.24#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.217.07:45:39.24#ibcon#enter wrdev, iclass 33, count 0 2006.217.07:45:39.24#ibcon#first serial, iclass 33, count 0 2006.217.07:45:39.24#ibcon#enter sib2, iclass 33, count 0 2006.217.07:45:39.24#ibcon#flushed, iclass 33, count 0 2006.217.07:45:39.24#ibcon#about to write, iclass 33, count 0 2006.217.07:45:39.24#ibcon#wrote, iclass 33, count 0 2006.217.07:45:39.24#ibcon#about to read 3, iclass 33, count 0 2006.217.07:45:39.26#ibcon#read 3, iclass 33, count 0 2006.217.07:45:39.26#ibcon#about to read 4, iclass 33, count 0 2006.217.07:45:39.26#ibcon#read 4, iclass 33, count 0 2006.217.07:45:39.26#ibcon#about to read 5, iclass 33, count 0 2006.217.07:45:39.26#ibcon#read 5, iclass 33, count 0 2006.217.07:45:39.26#ibcon#about to read 6, iclass 33, count 0 2006.217.07:45:39.26#ibcon#read 6, iclass 33, count 0 2006.217.07:45:39.26#ibcon#end of sib2, iclass 33, count 0 2006.217.07:45:39.26#ibcon#*mode == 0, iclass 33, count 0 2006.217.07:45:39.26#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.217.07:45:39.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.217.07:45:39.26#ibcon#*before write, iclass 33, count 0 2006.217.07:45:39.26#ibcon#enter sib2, iclass 33, count 0 2006.217.07:45:39.26#ibcon#flushed, iclass 33, count 0 2006.217.07:45:39.26#ibcon#about to write, iclass 33, count 0 2006.217.07:45:39.26#ibcon#wrote, iclass 33, count 0 2006.217.07:45:39.26#ibcon#about to read 3, iclass 33, count 0 2006.217.07:45:39.30#ibcon#read 3, iclass 33, count 0 2006.217.07:45:39.30#ibcon#about to read 4, iclass 33, count 0 2006.217.07:45:39.30#ibcon#read 4, iclass 33, count 0 2006.217.07:45:39.30#ibcon#about to read 5, iclass 33, count 0 2006.217.07:45:39.30#ibcon#read 5, iclass 33, count 0 2006.217.07:45:39.30#ibcon#about to read 6, iclass 33, count 0 2006.217.07:45:39.30#ibcon#read 6, iclass 33, count 0 2006.217.07:45:39.30#ibcon#end of sib2, iclass 33, count 0 2006.217.07:45:39.30#ibcon#*after write, iclass 33, count 0 2006.217.07:45:39.30#ibcon#*before return 0, iclass 33, count 0 2006.217.07:45:39.30#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.217.07:45:39.30#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.217.07:45:39.30#ibcon#about to clear, iclass 33 cls_cnt 0 2006.217.07:45:39.30#ibcon#cleared, iclass 33 cls_cnt 0 2006.217.07:45:39.30$vc4f8/va=5,7 2006.217.07:45:39.30#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.217.07:45:39.30#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.217.07:45:39.30#ibcon#ireg 11 cls_cnt 2 2006.217.07:45:39.30#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.217.07:45:39.36#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.217.07:45:39.36#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.217.07:45:39.36#ibcon#enter wrdev, iclass 35, count 2 2006.217.07:45:39.36#ibcon#first serial, iclass 35, count 2 2006.217.07:45:39.36#ibcon#enter sib2, iclass 35, count 2 2006.217.07:45:39.36#ibcon#flushed, iclass 35, count 2 2006.217.07:45:39.36#ibcon#about to write, iclass 35, count 2 2006.217.07:45:39.36#ibcon#wrote, iclass 35, count 2 2006.217.07:45:39.36#ibcon#about to read 3, iclass 35, count 2 2006.217.07:45:39.38#ibcon#read 3, iclass 35, count 2 2006.217.07:45:39.38#ibcon#about to read 4, iclass 35, count 2 2006.217.07:45:39.38#ibcon#read 4, iclass 35, count 2 2006.217.07:45:39.38#ibcon#about to read 5, iclass 35, count 2 2006.217.07:45:39.38#ibcon#read 5, iclass 35, count 2 2006.217.07:45:39.38#ibcon#about to read 6, iclass 35, count 2 2006.217.07:45:39.38#ibcon#read 6, iclass 35, count 2 2006.217.07:45:39.38#ibcon#end of sib2, iclass 35, count 2 2006.217.07:45:39.38#ibcon#*mode == 0, iclass 35, count 2 2006.217.07:45:39.38#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.217.07:45:39.38#ibcon#[25=AT05-07\r\n] 2006.217.07:45:39.38#ibcon#*before write, iclass 35, count 2 2006.217.07:45:39.38#ibcon#enter sib2, iclass 35, count 2 2006.217.07:45:39.38#ibcon#flushed, iclass 35, count 2 2006.217.07:45:39.38#ibcon#about to write, iclass 35, count 2 2006.217.07:45:39.38#ibcon#wrote, iclass 35, count 2 2006.217.07:45:39.38#ibcon#about to read 3, iclass 35, count 2 2006.217.07:45:39.41#ibcon#read 3, iclass 35, count 2 2006.217.07:45:39.41#ibcon#about to read 4, iclass 35, count 2 2006.217.07:45:39.41#ibcon#read 4, iclass 35, count 2 2006.217.07:45:39.41#ibcon#about to read 5, iclass 35, count 2 2006.217.07:45:39.41#ibcon#read 5, iclass 35, count 2 2006.217.07:45:39.41#ibcon#about to read 6, iclass 35, count 2 2006.217.07:45:39.41#ibcon#read 6, iclass 35, count 2 2006.217.07:45:39.41#ibcon#end of sib2, iclass 35, count 2 2006.217.07:45:39.41#ibcon#*after write, iclass 35, count 2 2006.217.07:45:39.41#ibcon#*before return 0, iclass 35, count 2 2006.217.07:45:39.41#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.217.07:45:39.41#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.217.07:45:39.41#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.217.07:45:39.41#ibcon#ireg 7 cls_cnt 0 2006.217.07:45:39.41#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.217.07:45:39.53#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.217.07:45:39.53#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.217.07:45:39.53#ibcon#enter wrdev, iclass 35, count 0 2006.217.07:45:39.53#ibcon#first serial, iclass 35, count 0 2006.217.07:45:39.53#ibcon#enter sib2, iclass 35, count 0 2006.217.07:45:39.53#ibcon#flushed, iclass 35, count 0 2006.217.07:45:39.53#ibcon#about to write, iclass 35, count 0 2006.217.07:45:39.53#ibcon#wrote, iclass 35, count 0 2006.217.07:45:39.53#ibcon#about to read 3, iclass 35, count 0 2006.217.07:45:39.55#ibcon#read 3, iclass 35, count 0 2006.217.07:45:39.55#ibcon#about to read 4, iclass 35, count 0 2006.217.07:45:39.55#ibcon#read 4, iclass 35, count 0 2006.217.07:45:39.55#ibcon#about to read 5, iclass 35, count 0 2006.217.07:45:39.55#ibcon#read 5, iclass 35, count 0 2006.217.07:45:39.55#ibcon#about to read 6, iclass 35, count 0 2006.217.07:45:39.55#ibcon#read 6, iclass 35, count 0 2006.217.07:45:39.55#ibcon#end of sib2, iclass 35, count 0 2006.217.07:45:39.55#ibcon#*mode == 0, iclass 35, count 0 2006.217.07:45:39.55#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.217.07:45:39.55#ibcon#[25=USB\r\n] 2006.217.07:45:39.55#ibcon#*before write, iclass 35, count 0 2006.217.07:45:39.55#ibcon#enter sib2, iclass 35, count 0 2006.217.07:45:39.55#ibcon#flushed, iclass 35, count 0 2006.217.07:45:39.55#ibcon#about to write, iclass 35, count 0 2006.217.07:45:39.55#ibcon#wrote, iclass 35, count 0 2006.217.07:45:39.55#ibcon#about to read 3, iclass 35, count 0 2006.217.07:45:39.58#ibcon#read 3, iclass 35, count 0 2006.217.07:45:39.58#ibcon#about to read 4, iclass 35, count 0 2006.217.07:45:39.58#ibcon#read 4, iclass 35, count 0 2006.217.07:45:39.58#ibcon#about to read 5, iclass 35, count 0 2006.217.07:45:39.58#ibcon#read 5, iclass 35, count 0 2006.217.07:45:39.58#ibcon#about to read 6, iclass 35, count 0 2006.217.07:45:39.58#ibcon#read 6, iclass 35, count 0 2006.217.07:45:39.58#ibcon#end of sib2, iclass 35, count 0 2006.217.07:45:39.58#ibcon#*after write, iclass 35, count 0 2006.217.07:45:39.58#ibcon#*before return 0, iclass 35, count 0 2006.217.07:45:39.58#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.217.07:45:39.58#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.217.07:45:39.58#ibcon#about to clear, iclass 35 cls_cnt 0 2006.217.07:45:39.58#ibcon#cleared, iclass 35 cls_cnt 0 2006.217.07:45:39.58$vc4f8/valo=6,772.99 2006.217.07:45:39.58#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.217.07:45:39.58#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.217.07:45:39.58#ibcon#ireg 17 cls_cnt 0 2006.217.07:45:39.58#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.217.07:45:39.58#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.217.07:45:39.58#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.217.07:45:39.58#ibcon#enter wrdev, iclass 37, count 0 2006.217.07:45:39.58#ibcon#first serial, iclass 37, count 0 2006.217.07:45:39.58#ibcon#enter sib2, iclass 37, count 0 2006.217.07:45:39.58#ibcon#flushed, iclass 37, count 0 2006.217.07:45:39.58#ibcon#about to write, iclass 37, count 0 2006.217.07:45:39.58#ibcon#wrote, iclass 37, count 0 2006.217.07:45:39.58#ibcon#about to read 3, iclass 37, count 0 2006.217.07:45:39.60#ibcon#read 3, iclass 37, count 0 2006.217.07:45:39.60#ibcon#about to read 4, iclass 37, count 0 2006.217.07:45:39.60#ibcon#read 4, iclass 37, count 0 2006.217.07:45:39.60#ibcon#about to read 5, iclass 37, count 0 2006.217.07:45:39.60#ibcon#read 5, iclass 37, count 0 2006.217.07:45:39.60#ibcon#about to read 6, iclass 37, count 0 2006.217.07:45:39.60#ibcon#read 6, iclass 37, count 0 2006.217.07:45:39.60#ibcon#end of sib2, iclass 37, count 0 2006.217.07:45:39.60#ibcon#*mode == 0, iclass 37, count 0 2006.217.07:45:39.60#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.217.07:45:39.60#ibcon#[26=FRQ=06,772.99\r\n] 2006.217.07:45:39.60#ibcon#*before write, iclass 37, count 0 2006.217.07:45:39.60#ibcon#enter sib2, iclass 37, count 0 2006.217.07:45:39.60#ibcon#flushed, iclass 37, count 0 2006.217.07:45:39.60#ibcon#about to write, iclass 37, count 0 2006.217.07:45:39.60#ibcon#wrote, iclass 37, count 0 2006.217.07:45:39.60#ibcon#about to read 3, iclass 37, count 0 2006.217.07:45:39.64#ibcon#read 3, iclass 37, count 0 2006.217.07:45:39.64#ibcon#about to read 4, iclass 37, count 0 2006.217.07:45:39.64#ibcon#read 4, iclass 37, count 0 2006.217.07:45:39.64#ibcon#about to read 5, iclass 37, count 0 2006.217.07:45:39.64#ibcon#read 5, iclass 37, count 0 2006.217.07:45:39.64#ibcon#about to read 6, iclass 37, count 0 2006.217.07:45:39.64#ibcon#read 6, iclass 37, count 0 2006.217.07:45:39.64#ibcon#end of sib2, iclass 37, count 0 2006.217.07:45:39.64#ibcon#*after write, iclass 37, count 0 2006.217.07:45:39.64#ibcon#*before return 0, iclass 37, count 0 2006.217.07:45:39.64#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.217.07:45:39.64#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.217.07:45:39.64#ibcon#about to clear, iclass 37 cls_cnt 0 2006.217.07:45:39.64#ibcon#cleared, iclass 37 cls_cnt 0 2006.217.07:45:39.64$vc4f8/va=6,6 2006.217.07:45:39.64#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.217.07:45:39.64#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.217.07:45:39.64#ibcon#ireg 11 cls_cnt 2 2006.217.07:45:39.64#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.217.07:45:39.70#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.217.07:45:39.70#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.217.07:45:39.70#ibcon#enter wrdev, iclass 39, count 2 2006.217.07:45:39.70#ibcon#first serial, iclass 39, count 2 2006.217.07:45:39.70#ibcon#enter sib2, iclass 39, count 2 2006.217.07:45:39.70#ibcon#flushed, iclass 39, count 2 2006.217.07:45:39.70#ibcon#about to write, iclass 39, count 2 2006.217.07:45:39.70#ibcon#wrote, iclass 39, count 2 2006.217.07:45:39.70#ibcon#about to read 3, iclass 39, count 2 2006.217.07:45:39.72#ibcon#read 3, iclass 39, count 2 2006.217.07:45:39.72#ibcon#about to read 4, iclass 39, count 2 2006.217.07:45:39.72#ibcon#read 4, iclass 39, count 2 2006.217.07:45:39.72#ibcon#about to read 5, iclass 39, count 2 2006.217.07:45:39.72#ibcon#read 5, iclass 39, count 2 2006.217.07:45:39.72#ibcon#about to read 6, iclass 39, count 2 2006.217.07:45:39.72#ibcon#read 6, iclass 39, count 2 2006.217.07:45:39.72#ibcon#end of sib2, iclass 39, count 2 2006.217.07:45:39.72#ibcon#*mode == 0, iclass 39, count 2 2006.217.07:45:39.72#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.217.07:45:39.72#ibcon#[25=AT06-06\r\n] 2006.217.07:45:39.72#ibcon#*before write, iclass 39, count 2 2006.217.07:45:39.72#ibcon#enter sib2, iclass 39, count 2 2006.217.07:45:39.72#ibcon#flushed, iclass 39, count 2 2006.217.07:45:39.72#ibcon#about to write, iclass 39, count 2 2006.217.07:45:39.72#ibcon#wrote, iclass 39, count 2 2006.217.07:45:39.72#ibcon#about to read 3, iclass 39, count 2 2006.217.07:45:39.75#ibcon#read 3, iclass 39, count 2 2006.217.07:45:39.75#ibcon#about to read 4, iclass 39, count 2 2006.217.07:45:39.75#ibcon#read 4, iclass 39, count 2 2006.217.07:45:39.75#ibcon#about to read 5, iclass 39, count 2 2006.217.07:45:39.75#ibcon#read 5, iclass 39, count 2 2006.217.07:45:39.75#ibcon#about to read 6, iclass 39, count 2 2006.217.07:45:39.75#ibcon#read 6, iclass 39, count 2 2006.217.07:45:39.75#ibcon#end of sib2, iclass 39, count 2 2006.217.07:45:39.75#ibcon#*after write, iclass 39, count 2 2006.217.07:45:39.75#ibcon#*before return 0, iclass 39, count 2 2006.217.07:45:39.75#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.217.07:45:39.75#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.217.07:45:39.75#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.217.07:45:39.75#ibcon#ireg 7 cls_cnt 0 2006.217.07:45:39.75#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.217.07:45:39.87#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.217.07:45:39.87#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.217.07:45:39.87#ibcon#enter wrdev, iclass 39, count 0 2006.217.07:45:39.87#ibcon#first serial, iclass 39, count 0 2006.217.07:45:39.87#ibcon#enter sib2, iclass 39, count 0 2006.217.07:45:39.87#ibcon#flushed, iclass 39, count 0 2006.217.07:45:39.87#ibcon#about to write, iclass 39, count 0 2006.217.07:45:39.87#ibcon#wrote, iclass 39, count 0 2006.217.07:45:39.87#ibcon#about to read 3, iclass 39, count 0 2006.217.07:45:39.89#ibcon#read 3, iclass 39, count 0 2006.217.07:45:39.89#ibcon#about to read 4, iclass 39, count 0 2006.217.07:45:39.89#ibcon#read 4, iclass 39, count 0 2006.217.07:45:39.89#ibcon#about to read 5, iclass 39, count 0 2006.217.07:45:39.89#ibcon#read 5, iclass 39, count 0 2006.217.07:45:39.89#ibcon#about to read 6, iclass 39, count 0 2006.217.07:45:39.89#ibcon#read 6, iclass 39, count 0 2006.217.07:45:39.89#ibcon#end of sib2, iclass 39, count 0 2006.217.07:45:39.89#ibcon#*mode == 0, iclass 39, count 0 2006.217.07:45:39.89#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.217.07:45:39.89#ibcon#[25=USB\r\n] 2006.217.07:45:39.89#ibcon#*before write, iclass 39, count 0 2006.217.07:45:39.89#ibcon#enter sib2, iclass 39, count 0 2006.217.07:45:39.89#ibcon#flushed, iclass 39, count 0 2006.217.07:45:39.89#ibcon#about to write, iclass 39, count 0 2006.217.07:45:39.89#ibcon#wrote, iclass 39, count 0 2006.217.07:45:39.89#ibcon#about to read 3, iclass 39, count 0 2006.217.07:45:39.92#ibcon#read 3, iclass 39, count 0 2006.217.07:45:39.92#ibcon#about to read 4, iclass 39, count 0 2006.217.07:45:39.92#ibcon#read 4, iclass 39, count 0 2006.217.07:45:39.92#ibcon#about to read 5, iclass 39, count 0 2006.217.07:45:39.92#ibcon#read 5, iclass 39, count 0 2006.217.07:45:39.92#ibcon#about to read 6, iclass 39, count 0 2006.217.07:45:39.92#ibcon#read 6, iclass 39, count 0 2006.217.07:45:39.92#ibcon#end of sib2, iclass 39, count 0 2006.217.07:45:39.92#ibcon#*after write, iclass 39, count 0 2006.217.07:45:39.92#ibcon#*before return 0, iclass 39, count 0 2006.217.07:45:39.92#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.217.07:45:39.92#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.217.07:45:39.92#ibcon#about to clear, iclass 39 cls_cnt 0 2006.217.07:45:39.92#ibcon#cleared, iclass 39 cls_cnt 0 2006.217.07:45:39.92$vc4f8/valo=7,832.99 2006.217.07:45:39.92#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.217.07:45:39.92#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.217.07:45:39.92#ibcon#ireg 17 cls_cnt 0 2006.217.07:45:39.92#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.217.07:45:39.92#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.217.07:45:39.92#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.217.07:45:39.92#ibcon#enter wrdev, iclass 3, count 0 2006.217.07:45:39.92#ibcon#first serial, iclass 3, count 0 2006.217.07:45:39.92#ibcon#enter sib2, iclass 3, count 0 2006.217.07:45:39.92#ibcon#flushed, iclass 3, count 0 2006.217.07:45:39.92#ibcon#about to write, iclass 3, count 0 2006.217.07:45:39.92#ibcon#wrote, iclass 3, count 0 2006.217.07:45:39.92#ibcon#about to read 3, iclass 3, count 0 2006.217.07:45:39.94#ibcon#read 3, iclass 3, count 0 2006.217.07:45:39.94#ibcon#about to read 4, iclass 3, count 0 2006.217.07:45:39.94#ibcon#read 4, iclass 3, count 0 2006.217.07:45:39.94#ibcon#about to read 5, iclass 3, count 0 2006.217.07:45:39.94#ibcon#read 5, iclass 3, count 0 2006.217.07:45:39.94#ibcon#about to read 6, iclass 3, count 0 2006.217.07:45:39.94#ibcon#read 6, iclass 3, count 0 2006.217.07:45:39.94#ibcon#end of sib2, iclass 3, count 0 2006.217.07:45:39.94#ibcon#*mode == 0, iclass 3, count 0 2006.217.07:45:39.94#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.217.07:45:39.94#ibcon#[26=FRQ=07,832.99\r\n] 2006.217.07:45:39.94#ibcon#*before write, iclass 3, count 0 2006.217.07:45:39.94#ibcon#enter sib2, iclass 3, count 0 2006.217.07:45:39.94#ibcon#flushed, iclass 3, count 0 2006.217.07:45:39.94#ibcon#about to write, iclass 3, count 0 2006.217.07:45:39.94#ibcon#wrote, iclass 3, count 0 2006.217.07:45:39.94#ibcon#about to read 3, iclass 3, count 0 2006.217.07:45:39.98#ibcon#read 3, iclass 3, count 0 2006.217.07:45:39.98#ibcon#about to read 4, iclass 3, count 0 2006.217.07:45:39.98#ibcon#read 4, iclass 3, count 0 2006.217.07:45:39.98#ibcon#about to read 5, iclass 3, count 0 2006.217.07:45:39.98#ibcon#read 5, iclass 3, count 0 2006.217.07:45:39.98#ibcon#about to read 6, iclass 3, count 0 2006.217.07:45:39.98#ibcon#read 6, iclass 3, count 0 2006.217.07:45:39.98#ibcon#end of sib2, iclass 3, count 0 2006.217.07:45:39.98#ibcon#*after write, iclass 3, count 0 2006.217.07:45:39.98#ibcon#*before return 0, iclass 3, count 0 2006.217.07:45:39.98#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.217.07:45:39.98#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.217.07:45:39.98#ibcon#about to clear, iclass 3 cls_cnt 0 2006.217.07:45:39.98#ibcon#cleared, iclass 3 cls_cnt 0 2006.217.07:45:39.98$vc4f8/va=7,6 2006.217.07:45:39.98#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.217.07:45:39.98#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.217.07:45:39.98#ibcon#ireg 11 cls_cnt 2 2006.217.07:45:39.98#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.217.07:45:40.04#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.217.07:45:40.04#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.217.07:45:40.04#ibcon#enter wrdev, iclass 5, count 2 2006.217.07:45:40.04#ibcon#first serial, iclass 5, count 2 2006.217.07:45:40.04#ibcon#enter sib2, iclass 5, count 2 2006.217.07:45:40.04#ibcon#flushed, iclass 5, count 2 2006.217.07:45:40.04#ibcon#about to write, iclass 5, count 2 2006.217.07:45:40.04#ibcon#wrote, iclass 5, count 2 2006.217.07:45:40.04#ibcon#about to read 3, iclass 5, count 2 2006.217.07:45:40.06#ibcon#read 3, iclass 5, count 2 2006.217.07:45:40.06#ibcon#about to read 4, iclass 5, count 2 2006.217.07:45:40.06#ibcon#read 4, iclass 5, count 2 2006.217.07:45:40.06#ibcon#about to read 5, iclass 5, count 2 2006.217.07:45:40.06#ibcon#read 5, iclass 5, count 2 2006.217.07:45:40.06#ibcon#about to read 6, iclass 5, count 2 2006.217.07:45:40.06#ibcon#read 6, iclass 5, count 2 2006.217.07:45:40.06#ibcon#end of sib2, iclass 5, count 2 2006.217.07:45:40.06#ibcon#*mode == 0, iclass 5, count 2 2006.217.07:45:40.06#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.217.07:45:40.06#ibcon#[25=AT07-06\r\n] 2006.217.07:45:40.06#ibcon#*before write, iclass 5, count 2 2006.217.07:45:40.06#ibcon#enter sib2, iclass 5, count 2 2006.217.07:45:40.06#ibcon#flushed, iclass 5, count 2 2006.217.07:45:40.06#ibcon#about to write, iclass 5, count 2 2006.217.07:45:40.06#ibcon#wrote, iclass 5, count 2 2006.217.07:45:40.06#ibcon#about to read 3, iclass 5, count 2 2006.217.07:45:40.09#ibcon#read 3, iclass 5, count 2 2006.217.07:45:40.09#ibcon#about to read 4, iclass 5, count 2 2006.217.07:45:40.09#ibcon#read 4, iclass 5, count 2 2006.217.07:45:40.09#ibcon#about to read 5, iclass 5, count 2 2006.217.07:45:40.09#ibcon#read 5, iclass 5, count 2 2006.217.07:45:40.09#ibcon#about to read 6, iclass 5, count 2 2006.217.07:45:40.09#ibcon#read 6, iclass 5, count 2 2006.217.07:45:40.09#ibcon#end of sib2, iclass 5, count 2 2006.217.07:45:40.09#ibcon#*after write, iclass 5, count 2 2006.217.07:45:40.09#ibcon#*before return 0, iclass 5, count 2 2006.217.07:45:40.09#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.217.07:45:40.09#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.217.07:45:40.09#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.217.07:45:40.09#ibcon#ireg 7 cls_cnt 0 2006.217.07:45:40.09#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.217.07:45:40.21#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.217.07:45:40.21#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.217.07:45:40.21#ibcon#enter wrdev, iclass 5, count 0 2006.217.07:45:40.21#ibcon#first serial, iclass 5, count 0 2006.217.07:45:40.21#ibcon#enter sib2, iclass 5, count 0 2006.217.07:45:40.21#ibcon#flushed, iclass 5, count 0 2006.217.07:45:40.21#ibcon#about to write, iclass 5, count 0 2006.217.07:45:40.21#ibcon#wrote, iclass 5, count 0 2006.217.07:45:40.21#ibcon#about to read 3, iclass 5, count 0 2006.217.07:45:40.23#ibcon#read 3, iclass 5, count 0 2006.217.07:45:40.23#ibcon#about to read 4, iclass 5, count 0 2006.217.07:45:40.23#ibcon#read 4, iclass 5, count 0 2006.217.07:45:40.23#ibcon#about to read 5, iclass 5, count 0 2006.217.07:45:40.23#ibcon#read 5, iclass 5, count 0 2006.217.07:45:40.23#ibcon#about to read 6, iclass 5, count 0 2006.217.07:45:40.23#ibcon#read 6, iclass 5, count 0 2006.217.07:45:40.23#ibcon#end of sib2, iclass 5, count 0 2006.217.07:45:40.23#ibcon#*mode == 0, iclass 5, count 0 2006.217.07:45:40.23#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.217.07:45:40.23#ibcon#[25=USB\r\n] 2006.217.07:45:40.23#ibcon#*before write, iclass 5, count 0 2006.217.07:45:40.23#ibcon#enter sib2, iclass 5, count 0 2006.217.07:45:40.23#ibcon#flushed, iclass 5, count 0 2006.217.07:45:40.23#ibcon#about to write, iclass 5, count 0 2006.217.07:45:40.23#ibcon#wrote, iclass 5, count 0 2006.217.07:45:40.23#ibcon#about to read 3, iclass 5, count 0 2006.217.07:45:40.26#ibcon#read 3, iclass 5, count 0 2006.217.07:45:40.26#ibcon#about to read 4, iclass 5, count 0 2006.217.07:45:40.26#ibcon#read 4, iclass 5, count 0 2006.217.07:45:40.26#ibcon#about to read 5, iclass 5, count 0 2006.217.07:45:40.26#ibcon#read 5, iclass 5, count 0 2006.217.07:45:40.26#ibcon#about to read 6, iclass 5, count 0 2006.217.07:45:40.26#ibcon#read 6, iclass 5, count 0 2006.217.07:45:40.26#ibcon#end of sib2, iclass 5, count 0 2006.217.07:45:40.26#ibcon#*after write, iclass 5, count 0 2006.217.07:45:40.26#ibcon#*before return 0, iclass 5, count 0 2006.217.07:45:40.26#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.217.07:45:40.26#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.217.07:45:40.26#ibcon#about to clear, iclass 5 cls_cnt 0 2006.217.07:45:40.26#ibcon#cleared, iclass 5 cls_cnt 0 2006.217.07:45:40.26$vc4f8/valo=8,852.99 2006.217.07:45:40.26#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.217.07:45:40.26#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.217.07:45:40.26#ibcon#ireg 17 cls_cnt 0 2006.217.07:45:40.26#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.217.07:45:40.26#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.217.07:45:40.26#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.217.07:45:40.26#ibcon#enter wrdev, iclass 7, count 0 2006.217.07:45:40.26#ibcon#first serial, iclass 7, count 0 2006.217.07:45:40.26#ibcon#enter sib2, iclass 7, count 0 2006.217.07:45:40.26#ibcon#flushed, iclass 7, count 0 2006.217.07:45:40.26#ibcon#about to write, iclass 7, count 0 2006.217.07:45:40.26#ibcon#wrote, iclass 7, count 0 2006.217.07:45:40.26#ibcon#about to read 3, iclass 7, count 0 2006.217.07:45:40.28#ibcon#read 3, iclass 7, count 0 2006.217.07:45:40.28#ibcon#about to read 4, iclass 7, count 0 2006.217.07:45:40.28#ibcon#read 4, iclass 7, count 0 2006.217.07:45:40.28#ibcon#about to read 5, iclass 7, count 0 2006.217.07:45:40.28#ibcon#read 5, iclass 7, count 0 2006.217.07:45:40.28#ibcon#about to read 6, iclass 7, count 0 2006.217.07:45:40.28#ibcon#read 6, iclass 7, count 0 2006.217.07:45:40.28#ibcon#end of sib2, iclass 7, count 0 2006.217.07:45:40.28#ibcon#*mode == 0, iclass 7, count 0 2006.217.07:45:40.28#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.217.07:45:40.28#ibcon#[26=FRQ=08,852.99\r\n] 2006.217.07:45:40.28#ibcon#*before write, iclass 7, count 0 2006.217.07:45:40.28#ibcon#enter sib2, iclass 7, count 0 2006.217.07:45:40.28#ibcon#flushed, iclass 7, count 0 2006.217.07:45:40.28#ibcon#about to write, iclass 7, count 0 2006.217.07:45:40.28#ibcon#wrote, iclass 7, count 0 2006.217.07:45:40.28#ibcon#about to read 3, iclass 7, count 0 2006.217.07:45:40.32#ibcon#read 3, iclass 7, count 0 2006.217.07:45:40.32#ibcon#about to read 4, iclass 7, count 0 2006.217.07:45:40.32#ibcon#read 4, iclass 7, count 0 2006.217.07:45:40.32#ibcon#about to read 5, iclass 7, count 0 2006.217.07:45:40.32#ibcon#read 5, iclass 7, count 0 2006.217.07:45:40.32#ibcon#about to read 6, iclass 7, count 0 2006.217.07:45:40.32#ibcon#read 6, iclass 7, count 0 2006.217.07:45:40.32#ibcon#end of sib2, iclass 7, count 0 2006.217.07:45:40.32#ibcon#*after write, iclass 7, count 0 2006.217.07:45:40.32#ibcon#*before return 0, iclass 7, count 0 2006.217.07:45:40.32#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.217.07:45:40.32#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.217.07:45:40.32#ibcon#about to clear, iclass 7 cls_cnt 0 2006.217.07:45:40.32#ibcon#cleared, iclass 7 cls_cnt 0 2006.217.07:45:40.32$vc4f8/va=8,7 2006.217.07:45:40.32#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.217.07:45:40.32#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.217.07:45:40.32#ibcon#ireg 11 cls_cnt 2 2006.217.07:45:40.32#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.217.07:45:40.38#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.217.07:45:40.38#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.217.07:45:40.38#ibcon#enter wrdev, iclass 11, count 2 2006.217.07:45:40.38#ibcon#first serial, iclass 11, count 2 2006.217.07:45:40.38#ibcon#enter sib2, iclass 11, count 2 2006.217.07:45:40.38#ibcon#flushed, iclass 11, count 2 2006.217.07:45:40.38#ibcon#about to write, iclass 11, count 2 2006.217.07:45:40.38#ibcon#wrote, iclass 11, count 2 2006.217.07:45:40.38#ibcon#about to read 3, iclass 11, count 2 2006.217.07:45:40.40#ibcon#read 3, iclass 11, count 2 2006.217.07:45:40.40#ibcon#about to read 4, iclass 11, count 2 2006.217.07:45:40.40#ibcon#read 4, iclass 11, count 2 2006.217.07:45:40.40#ibcon#about to read 5, iclass 11, count 2 2006.217.07:45:40.40#ibcon#read 5, iclass 11, count 2 2006.217.07:45:40.40#ibcon#about to read 6, iclass 11, count 2 2006.217.07:45:40.40#ibcon#read 6, iclass 11, count 2 2006.217.07:45:40.40#ibcon#end of sib2, iclass 11, count 2 2006.217.07:45:40.40#ibcon#*mode == 0, iclass 11, count 2 2006.217.07:45:40.40#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.217.07:45:40.40#ibcon#[25=AT08-07\r\n] 2006.217.07:45:40.40#ibcon#*before write, iclass 11, count 2 2006.217.07:45:40.40#ibcon#enter sib2, iclass 11, count 2 2006.217.07:45:40.40#ibcon#flushed, iclass 11, count 2 2006.217.07:45:40.40#ibcon#about to write, iclass 11, count 2 2006.217.07:45:40.40#ibcon#wrote, iclass 11, count 2 2006.217.07:45:40.40#ibcon#about to read 3, iclass 11, count 2 2006.217.07:45:40.43#ibcon#read 3, iclass 11, count 2 2006.217.07:45:40.43#ibcon#about to read 4, iclass 11, count 2 2006.217.07:45:40.43#ibcon#read 4, iclass 11, count 2 2006.217.07:45:40.43#ibcon#about to read 5, iclass 11, count 2 2006.217.07:45:40.43#ibcon#read 5, iclass 11, count 2 2006.217.07:45:40.43#ibcon#about to read 6, iclass 11, count 2 2006.217.07:45:40.43#ibcon#read 6, iclass 11, count 2 2006.217.07:45:40.43#ibcon#end of sib2, iclass 11, count 2 2006.217.07:45:40.43#ibcon#*after write, iclass 11, count 2 2006.217.07:45:40.43#ibcon#*before return 0, iclass 11, count 2 2006.217.07:45:40.43#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.217.07:45:40.43#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.217.07:45:40.43#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.217.07:45:40.43#ibcon#ireg 7 cls_cnt 0 2006.217.07:45:40.43#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.217.07:45:40.55#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.217.07:45:40.55#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.217.07:45:40.55#ibcon#enter wrdev, iclass 11, count 0 2006.217.07:45:40.55#ibcon#first serial, iclass 11, count 0 2006.217.07:45:40.55#ibcon#enter sib2, iclass 11, count 0 2006.217.07:45:40.55#ibcon#flushed, iclass 11, count 0 2006.217.07:45:40.55#ibcon#about to write, iclass 11, count 0 2006.217.07:45:40.55#ibcon#wrote, iclass 11, count 0 2006.217.07:45:40.55#ibcon#about to read 3, iclass 11, count 0 2006.217.07:45:40.57#ibcon#read 3, iclass 11, count 0 2006.217.07:45:40.57#ibcon#about to read 4, iclass 11, count 0 2006.217.07:45:40.57#ibcon#read 4, iclass 11, count 0 2006.217.07:45:40.57#ibcon#about to read 5, iclass 11, count 0 2006.217.07:45:40.57#ibcon#read 5, iclass 11, count 0 2006.217.07:45:40.57#ibcon#about to read 6, iclass 11, count 0 2006.217.07:45:40.57#ibcon#read 6, iclass 11, count 0 2006.217.07:45:40.57#ibcon#end of sib2, iclass 11, count 0 2006.217.07:45:40.57#ibcon#*mode == 0, iclass 11, count 0 2006.217.07:45:40.57#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.217.07:45:40.57#ibcon#[25=USB\r\n] 2006.217.07:45:40.57#ibcon#*before write, iclass 11, count 0 2006.217.07:45:40.57#ibcon#enter sib2, iclass 11, count 0 2006.217.07:45:40.57#ibcon#flushed, iclass 11, count 0 2006.217.07:45:40.57#ibcon#about to write, iclass 11, count 0 2006.217.07:45:40.57#ibcon#wrote, iclass 11, count 0 2006.217.07:45:40.57#ibcon#about to read 3, iclass 11, count 0 2006.217.07:45:40.60#ibcon#read 3, iclass 11, count 0 2006.217.07:45:40.60#ibcon#about to read 4, iclass 11, count 0 2006.217.07:45:40.60#ibcon#read 4, iclass 11, count 0 2006.217.07:45:40.60#ibcon#about to read 5, iclass 11, count 0 2006.217.07:45:40.60#ibcon#read 5, iclass 11, count 0 2006.217.07:45:40.60#ibcon#about to read 6, iclass 11, count 0 2006.217.07:45:40.60#ibcon#read 6, iclass 11, count 0 2006.217.07:45:40.60#ibcon#end of sib2, iclass 11, count 0 2006.217.07:45:40.60#ibcon#*after write, iclass 11, count 0 2006.217.07:45:40.60#ibcon#*before return 0, iclass 11, count 0 2006.217.07:45:40.60#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.217.07:45:40.60#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.217.07:45:40.60#ibcon#about to clear, iclass 11 cls_cnt 0 2006.217.07:45:40.60#ibcon#cleared, iclass 11 cls_cnt 0 2006.217.07:45:40.60$vc4f8/vblo=1,632.99 2006.217.07:45:40.60#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.217.07:45:40.60#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.217.07:45:40.60#ibcon#ireg 17 cls_cnt 0 2006.217.07:45:40.60#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.217.07:45:40.60#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.217.07:45:40.60#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.217.07:45:40.60#ibcon#enter wrdev, iclass 13, count 0 2006.217.07:45:40.60#ibcon#first serial, iclass 13, count 0 2006.217.07:45:40.60#ibcon#enter sib2, iclass 13, count 0 2006.217.07:45:40.60#ibcon#flushed, iclass 13, count 0 2006.217.07:45:40.60#ibcon#about to write, iclass 13, count 0 2006.217.07:45:40.60#ibcon#wrote, iclass 13, count 0 2006.217.07:45:40.60#ibcon#about to read 3, iclass 13, count 0 2006.217.07:45:40.62#ibcon#read 3, iclass 13, count 0 2006.217.07:45:40.62#ibcon#about to read 4, iclass 13, count 0 2006.217.07:45:40.62#ibcon#read 4, iclass 13, count 0 2006.217.07:45:40.62#ibcon#about to read 5, iclass 13, count 0 2006.217.07:45:40.62#ibcon#read 5, iclass 13, count 0 2006.217.07:45:40.62#ibcon#about to read 6, iclass 13, count 0 2006.217.07:45:40.62#ibcon#read 6, iclass 13, count 0 2006.217.07:45:40.62#ibcon#end of sib2, iclass 13, count 0 2006.217.07:45:40.62#ibcon#*mode == 0, iclass 13, count 0 2006.217.07:45:40.62#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.217.07:45:40.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.217.07:45:40.62#ibcon#*before write, iclass 13, count 0 2006.217.07:45:40.62#ibcon#enter sib2, iclass 13, count 0 2006.217.07:45:40.62#ibcon#flushed, iclass 13, count 0 2006.217.07:45:40.62#ibcon#about to write, iclass 13, count 0 2006.217.07:45:40.62#ibcon#wrote, iclass 13, count 0 2006.217.07:45:40.62#ibcon#about to read 3, iclass 13, count 0 2006.217.07:45:40.66#ibcon#read 3, iclass 13, count 0 2006.217.07:45:40.66#ibcon#about to read 4, iclass 13, count 0 2006.217.07:45:40.66#ibcon#read 4, iclass 13, count 0 2006.217.07:45:40.66#ibcon#about to read 5, iclass 13, count 0 2006.217.07:45:40.66#ibcon#read 5, iclass 13, count 0 2006.217.07:45:40.66#ibcon#about to read 6, iclass 13, count 0 2006.217.07:45:40.66#ibcon#read 6, iclass 13, count 0 2006.217.07:45:40.66#ibcon#end of sib2, iclass 13, count 0 2006.217.07:45:40.66#ibcon#*after write, iclass 13, count 0 2006.217.07:45:40.66#ibcon#*before return 0, iclass 13, count 0 2006.217.07:45:40.66#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.217.07:45:40.66#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.217.07:45:40.66#ibcon#about to clear, iclass 13 cls_cnt 0 2006.217.07:45:40.66#ibcon#cleared, iclass 13 cls_cnt 0 2006.217.07:45:40.66$vc4f8/vb=1,4 2006.217.07:45:40.66#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.217.07:45:40.66#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.217.07:45:40.66#ibcon#ireg 11 cls_cnt 2 2006.217.07:45:40.66#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.217.07:45:40.66#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.217.07:45:40.66#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.217.07:45:40.66#ibcon#enter wrdev, iclass 15, count 2 2006.217.07:45:40.66#ibcon#first serial, iclass 15, count 2 2006.217.07:45:40.66#ibcon#enter sib2, iclass 15, count 2 2006.217.07:45:40.66#ibcon#flushed, iclass 15, count 2 2006.217.07:45:40.66#ibcon#about to write, iclass 15, count 2 2006.217.07:45:40.66#ibcon#wrote, iclass 15, count 2 2006.217.07:45:40.66#ibcon#about to read 3, iclass 15, count 2 2006.217.07:45:40.68#ibcon#read 3, iclass 15, count 2 2006.217.07:45:40.68#ibcon#about to read 4, iclass 15, count 2 2006.217.07:45:40.68#ibcon#read 4, iclass 15, count 2 2006.217.07:45:40.68#ibcon#about to read 5, iclass 15, count 2 2006.217.07:45:40.68#ibcon#read 5, iclass 15, count 2 2006.217.07:45:40.68#ibcon#about to read 6, iclass 15, count 2 2006.217.07:45:40.68#ibcon#read 6, iclass 15, count 2 2006.217.07:45:40.68#ibcon#end of sib2, iclass 15, count 2 2006.217.07:45:40.68#ibcon#*mode == 0, iclass 15, count 2 2006.217.07:45:40.68#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.217.07:45:40.68#ibcon#[27=AT01-04\r\n] 2006.217.07:45:40.68#ibcon#*before write, iclass 15, count 2 2006.217.07:45:40.68#ibcon#enter sib2, iclass 15, count 2 2006.217.07:45:40.68#ibcon#flushed, iclass 15, count 2 2006.217.07:45:40.68#ibcon#about to write, iclass 15, count 2 2006.217.07:45:40.68#ibcon#wrote, iclass 15, count 2 2006.217.07:45:40.68#ibcon#about to read 3, iclass 15, count 2 2006.217.07:45:40.71#ibcon#read 3, iclass 15, count 2 2006.217.07:45:40.71#ibcon#about to read 4, iclass 15, count 2 2006.217.07:45:40.71#ibcon#read 4, iclass 15, count 2 2006.217.07:45:40.71#ibcon#about to read 5, iclass 15, count 2 2006.217.07:45:40.71#ibcon#read 5, iclass 15, count 2 2006.217.07:45:40.71#ibcon#about to read 6, iclass 15, count 2 2006.217.07:45:40.71#ibcon#read 6, iclass 15, count 2 2006.217.07:45:40.71#ibcon#end of sib2, iclass 15, count 2 2006.217.07:45:40.71#ibcon#*after write, iclass 15, count 2 2006.217.07:45:40.71#ibcon#*before return 0, iclass 15, count 2 2006.217.07:45:40.71#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.217.07:45:40.71#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.217.07:45:40.71#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.217.07:45:40.71#ibcon#ireg 7 cls_cnt 0 2006.217.07:45:40.71#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.217.07:45:40.83#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.217.07:45:40.83#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.217.07:45:40.83#ibcon#enter wrdev, iclass 15, count 0 2006.217.07:45:40.83#ibcon#first serial, iclass 15, count 0 2006.217.07:45:40.83#ibcon#enter sib2, iclass 15, count 0 2006.217.07:45:40.83#ibcon#flushed, iclass 15, count 0 2006.217.07:45:40.83#ibcon#about to write, iclass 15, count 0 2006.217.07:45:40.83#ibcon#wrote, iclass 15, count 0 2006.217.07:45:40.83#ibcon#about to read 3, iclass 15, count 0 2006.217.07:45:40.85#ibcon#read 3, iclass 15, count 0 2006.217.07:45:40.85#ibcon#about to read 4, iclass 15, count 0 2006.217.07:45:40.85#ibcon#read 4, iclass 15, count 0 2006.217.07:45:40.85#ibcon#about to read 5, iclass 15, count 0 2006.217.07:45:40.85#ibcon#read 5, iclass 15, count 0 2006.217.07:45:40.85#ibcon#about to read 6, iclass 15, count 0 2006.217.07:45:40.85#ibcon#read 6, iclass 15, count 0 2006.217.07:45:40.85#ibcon#end of sib2, iclass 15, count 0 2006.217.07:45:40.85#ibcon#*mode == 0, iclass 15, count 0 2006.217.07:45:40.85#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.217.07:45:40.85#ibcon#[27=USB\r\n] 2006.217.07:45:40.85#ibcon#*before write, iclass 15, count 0 2006.217.07:45:40.85#ibcon#enter sib2, iclass 15, count 0 2006.217.07:45:40.85#ibcon#flushed, iclass 15, count 0 2006.217.07:45:40.85#ibcon#about to write, iclass 15, count 0 2006.217.07:45:40.85#ibcon#wrote, iclass 15, count 0 2006.217.07:45:40.85#ibcon#about to read 3, iclass 15, count 0 2006.217.07:45:40.88#ibcon#read 3, iclass 15, count 0 2006.217.07:45:40.88#ibcon#about to read 4, iclass 15, count 0 2006.217.07:45:40.88#ibcon#read 4, iclass 15, count 0 2006.217.07:45:40.88#ibcon#about to read 5, iclass 15, count 0 2006.217.07:45:40.88#ibcon#read 5, iclass 15, count 0 2006.217.07:45:40.88#ibcon#about to read 6, iclass 15, count 0 2006.217.07:45:40.88#ibcon#read 6, iclass 15, count 0 2006.217.07:45:40.88#ibcon#end of sib2, iclass 15, count 0 2006.217.07:45:40.88#ibcon#*after write, iclass 15, count 0 2006.217.07:45:40.88#ibcon#*before return 0, iclass 15, count 0 2006.217.07:45:40.88#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.217.07:45:40.88#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.217.07:45:40.88#ibcon#about to clear, iclass 15 cls_cnt 0 2006.217.07:45:40.88#ibcon#cleared, iclass 15 cls_cnt 0 2006.217.07:45:40.88$vc4f8/vblo=2,640.99 2006.217.07:45:40.88#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.217.07:45:40.88#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.217.07:45:40.88#ibcon#ireg 17 cls_cnt 0 2006.217.07:45:40.88#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.217.07:45:40.88#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.217.07:45:40.88#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.217.07:45:40.88#ibcon#enter wrdev, iclass 17, count 0 2006.217.07:45:40.88#ibcon#first serial, iclass 17, count 0 2006.217.07:45:40.88#ibcon#enter sib2, iclass 17, count 0 2006.217.07:45:40.88#ibcon#flushed, iclass 17, count 0 2006.217.07:45:40.88#ibcon#about to write, iclass 17, count 0 2006.217.07:45:40.88#ibcon#wrote, iclass 17, count 0 2006.217.07:45:40.88#ibcon#about to read 3, iclass 17, count 0 2006.217.07:45:40.90#ibcon#read 3, iclass 17, count 0 2006.217.07:45:40.90#ibcon#about to read 4, iclass 17, count 0 2006.217.07:45:40.90#ibcon#read 4, iclass 17, count 0 2006.217.07:45:40.90#ibcon#about to read 5, iclass 17, count 0 2006.217.07:45:40.90#ibcon#read 5, iclass 17, count 0 2006.217.07:45:40.90#ibcon#about to read 6, iclass 17, count 0 2006.217.07:45:40.90#ibcon#read 6, iclass 17, count 0 2006.217.07:45:40.90#ibcon#end of sib2, iclass 17, count 0 2006.217.07:45:40.90#ibcon#*mode == 0, iclass 17, count 0 2006.217.07:45:40.90#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.217.07:45:40.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.217.07:45:40.90#ibcon#*before write, iclass 17, count 0 2006.217.07:45:40.90#ibcon#enter sib2, iclass 17, count 0 2006.217.07:45:40.90#ibcon#flushed, iclass 17, count 0 2006.217.07:45:40.90#ibcon#about to write, iclass 17, count 0 2006.217.07:45:40.90#ibcon#wrote, iclass 17, count 0 2006.217.07:45:40.90#ibcon#about to read 3, iclass 17, count 0 2006.217.07:45:40.94#ibcon#read 3, iclass 17, count 0 2006.217.07:45:40.94#ibcon#about to read 4, iclass 17, count 0 2006.217.07:45:40.94#ibcon#read 4, iclass 17, count 0 2006.217.07:45:40.94#ibcon#about to read 5, iclass 17, count 0 2006.217.07:45:40.94#ibcon#read 5, iclass 17, count 0 2006.217.07:45:40.94#ibcon#about to read 6, iclass 17, count 0 2006.217.07:45:40.94#ibcon#read 6, iclass 17, count 0 2006.217.07:45:40.94#ibcon#end of sib2, iclass 17, count 0 2006.217.07:45:40.94#ibcon#*after write, iclass 17, count 0 2006.217.07:45:40.94#ibcon#*before return 0, iclass 17, count 0 2006.217.07:45:40.94#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.217.07:45:40.94#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.217.07:45:40.94#ibcon#about to clear, iclass 17 cls_cnt 0 2006.217.07:45:40.94#ibcon#cleared, iclass 17 cls_cnt 0 2006.217.07:45:40.94$vc4f8/vb=2,4 2006.217.07:45:40.94#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.217.07:45:40.94#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.217.07:45:40.94#ibcon#ireg 11 cls_cnt 2 2006.217.07:45:40.94#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.217.07:45:41.00#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.217.07:45:41.00#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.217.07:45:41.00#ibcon#enter wrdev, iclass 19, count 2 2006.217.07:45:41.00#ibcon#first serial, iclass 19, count 2 2006.217.07:45:41.00#ibcon#enter sib2, iclass 19, count 2 2006.217.07:45:41.00#ibcon#flushed, iclass 19, count 2 2006.217.07:45:41.00#ibcon#about to write, iclass 19, count 2 2006.217.07:45:41.00#ibcon#wrote, iclass 19, count 2 2006.217.07:45:41.00#ibcon#about to read 3, iclass 19, count 2 2006.217.07:45:41.02#ibcon#read 3, iclass 19, count 2 2006.217.07:45:41.02#ibcon#about to read 4, iclass 19, count 2 2006.217.07:45:41.02#ibcon#read 4, iclass 19, count 2 2006.217.07:45:41.02#ibcon#about to read 5, iclass 19, count 2 2006.217.07:45:41.02#ibcon#read 5, iclass 19, count 2 2006.217.07:45:41.02#ibcon#about to read 6, iclass 19, count 2 2006.217.07:45:41.02#ibcon#read 6, iclass 19, count 2 2006.217.07:45:41.02#ibcon#end of sib2, iclass 19, count 2 2006.217.07:45:41.02#ibcon#*mode == 0, iclass 19, count 2 2006.217.07:45:41.02#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.217.07:45:41.02#ibcon#[27=AT02-04\r\n] 2006.217.07:45:41.02#ibcon#*before write, iclass 19, count 2 2006.217.07:45:41.02#ibcon#enter sib2, iclass 19, count 2 2006.217.07:45:41.02#ibcon#flushed, iclass 19, count 2 2006.217.07:45:41.02#ibcon#about to write, iclass 19, count 2 2006.217.07:45:41.02#ibcon#wrote, iclass 19, count 2 2006.217.07:45:41.02#ibcon#about to read 3, iclass 19, count 2 2006.217.07:45:41.05#ibcon#read 3, iclass 19, count 2 2006.217.07:45:41.05#ibcon#about to read 4, iclass 19, count 2 2006.217.07:45:41.05#ibcon#read 4, iclass 19, count 2 2006.217.07:45:41.05#ibcon#about to read 5, iclass 19, count 2 2006.217.07:45:41.05#ibcon#read 5, iclass 19, count 2 2006.217.07:45:41.05#ibcon#about to read 6, iclass 19, count 2 2006.217.07:45:41.05#ibcon#read 6, iclass 19, count 2 2006.217.07:45:41.05#ibcon#end of sib2, iclass 19, count 2 2006.217.07:45:41.05#ibcon#*after write, iclass 19, count 2 2006.217.07:45:41.05#ibcon#*before return 0, iclass 19, count 2 2006.217.07:45:41.05#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.217.07:45:41.05#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.217.07:45:41.05#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.217.07:45:41.05#ibcon#ireg 7 cls_cnt 0 2006.217.07:45:41.05#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.217.07:45:41.17#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.217.07:45:41.17#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.217.07:45:41.17#ibcon#enter wrdev, iclass 19, count 0 2006.217.07:45:41.17#ibcon#first serial, iclass 19, count 0 2006.217.07:45:41.17#ibcon#enter sib2, iclass 19, count 0 2006.217.07:45:41.17#ibcon#flushed, iclass 19, count 0 2006.217.07:45:41.17#ibcon#about to write, iclass 19, count 0 2006.217.07:45:41.17#ibcon#wrote, iclass 19, count 0 2006.217.07:45:41.17#ibcon#about to read 3, iclass 19, count 0 2006.217.07:45:41.19#ibcon#read 3, iclass 19, count 0 2006.217.07:45:41.19#ibcon#about to read 4, iclass 19, count 0 2006.217.07:45:41.19#ibcon#read 4, iclass 19, count 0 2006.217.07:45:41.19#ibcon#about to read 5, iclass 19, count 0 2006.217.07:45:41.19#ibcon#read 5, iclass 19, count 0 2006.217.07:45:41.19#ibcon#about to read 6, iclass 19, count 0 2006.217.07:45:41.19#ibcon#read 6, iclass 19, count 0 2006.217.07:45:41.19#ibcon#end of sib2, iclass 19, count 0 2006.217.07:45:41.19#ibcon#*mode == 0, iclass 19, count 0 2006.217.07:45:41.19#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.217.07:45:41.19#ibcon#[27=USB\r\n] 2006.217.07:45:41.19#ibcon#*before write, iclass 19, count 0 2006.217.07:45:41.19#ibcon#enter sib2, iclass 19, count 0 2006.217.07:45:41.19#ibcon#flushed, iclass 19, count 0 2006.217.07:45:41.19#ibcon#about to write, iclass 19, count 0 2006.217.07:45:41.19#ibcon#wrote, iclass 19, count 0 2006.217.07:45:41.19#ibcon#about to read 3, iclass 19, count 0 2006.217.07:45:41.22#ibcon#read 3, iclass 19, count 0 2006.217.07:45:41.22#ibcon#about to read 4, iclass 19, count 0 2006.217.07:45:41.22#ibcon#read 4, iclass 19, count 0 2006.217.07:45:41.22#ibcon#about to read 5, iclass 19, count 0 2006.217.07:45:41.22#ibcon#read 5, iclass 19, count 0 2006.217.07:45:41.22#ibcon#about to read 6, iclass 19, count 0 2006.217.07:45:41.22#ibcon#read 6, iclass 19, count 0 2006.217.07:45:41.22#ibcon#end of sib2, iclass 19, count 0 2006.217.07:45:41.22#ibcon#*after write, iclass 19, count 0 2006.217.07:45:41.22#ibcon#*before return 0, iclass 19, count 0 2006.217.07:45:41.22#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.217.07:45:41.22#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.217.07:45:41.22#ibcon#about to clear, iclass 19 cls_cnt 0 2006.217.07:45:41.22#ibcon#cleared, iclass 19 cls_cnt 0 2006.217.07:45:41.22$vc4f8/vblo=3,656.99 2006.217.07:45:41.22#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.217.07:45:41.22#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.217.07:45:41.22#ibcon#ireg 17 cls_cnt 0 2006.217.07:45:41.22#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.217.07:45:41.22#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.217.07:45:41.22#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.217.07:45:41.22#ibcon#enter wrdev, iclass 21, count 0 2006.217.07:45:41.22#ibcon#first serial, iclass 21, count 0 2006.217.07:45:41.22#ibcon#enter sib2, iclass 21, count 0 2006.217.07:45:41.22#ibcon#flushed, iclass 21, count 0 2006.217.07:45:41.22#ibcon#about to write, iclass 21, count 0 2006.217.07:45:41.22#ibcon#wrote, iclass 21, count 0 2006.217.07:45:41.22#ibcon#about to read 3, iclass 21, count 0 2006.217.07:45:41.24#ibcon#read 3, iclass 21, count 0 2006.217.07:45:41.24#ibcon#about to read 4, iclass 21, count 0 2006.217.07:45:41.24#ibcon#read 4, iclass 21, count 0 2006.217.07:45:41.24#ibcon#about to read 5, iclass 21, count 0 2006.217.07:45:41.24#ibcon#read 5, iclass 21, count 0 2006.217.07:45:41.24#ibcon#about to read 6, iclass 21, count 0 2006.217.07:45:41.24#ibcon#read 6, iclass 21, count 0 2006.217.07:45:41.24#ibcon#end of sib2, iclass 21, count 0 2006.217.07:45:41.24#ibcon#*mode == 0, iclass 21, count 0 2006.217.07:45:41.24#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.217.07:45:41.24#ibcon#[28=FRQ=03,656.99\r\n] 2006.217.07:45:41.24#ibcon#*before write, iclass 21, count 0 2006.217.07:45:41.24#ibcon#enter sib2, iclass 21, count 0 2006.217.07:45:41.24#ibcon#flushed, iclass 21, count 0 2006.217.07:45:41.24#ibcon#about to write, iclass 21, count 0 2006.217.07:45:41.24#ibcon#wrote, iclass 21, count 0 2006.217.07:45:41.24#ibcon#about to read 3, iclass 21, count 0 2006.217.07:45:41.28#ibcon#read 3, iclass 21, count 0 2006.217.07:45:41.28#ibcon#about to read 4, iclass 21, count 0 2006.217.07:45:41.28#ibcon#read 4, iclass 21, count 0 2006.217.07:45:41.28#ibcon#about to read 5, iclass 21, count 0 2006.217.07:45:41.28#ibcon#read 5, iclass 21, count 0 2006.217.07:45:41.28#ibcon#about to read 6, iclass 21, count 0 2006.217.07:45:41.28#ibcon#read 6, iclass 21, count 0 2006.217.07:45:41.28#ibcon#end of sib2, iclass 21, count 0 2006.217.07:45:41.28#ibcon#*after write, iclass 21, count 0 2006.217.07:45:41.28#ibcon#*before return 0, iclass 21, count 0 2006.217.07:45:41.28#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.217.07:45:41.28#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.217.07:45:41.28#ibcon#about to clear, iclass 21 cls_cnt 0 2006.217.07:45:41.28#ibcon#cleared, iclass 21 cls_cnt 0 2006.217.07:45:41.28$vc4f8/vb=3,4 2006.217.07:45:41.28#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.217.07:45:41.28#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.217.07:45:41.28#ibcon#ireg 11 cls_cnt 2 2006.217.07:45:41.28#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.217.07:45:41.35#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.217.07:45:41.35#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.217.07:45:41.35#ibcon#enter wrdev, iclass 23, count 2 2006.217.07:45:41.35#ibcon#first serial, iclass 23, count 2 2006.217.07:45:41.35#ibcon#enter sib2, iclass 23, count 2 2006.217.07:45:41.35#ibcon#flushed, iclass 23, count 2 2006.217.07:45:41.35#ibcon#about to write, iclass 23, count 2 2006.217.07:45:41.35#ibcon#wrote, iclass 23, count 2 2006.217.07:45:41.35#ibcon#about to read 3, iclass 23, count 2 2006.217.07:45:41.36#ibcon#read 3, iclass 23, count 2 2006.217.07:45:41.36#ibcon#about to read 4, iclass 23, count 2 2006.217.07:45:41.36#ibcon#read 4, iclass 23, count 2 2006.217.07:45:41.36#ibcon#about to read 5, iclass 23, count 2 2006.217.07:45:41.36#ibcon#read 5, iclass 23, count 2 2006.217.07:45:41.36#ibcon#about to read 6, iclass 23, count 2 2006.217.07:45:41.36#ibcon#read 6, iclass 23, count 2 2006.217.07:45:41.36#ibcon#end of sib2, iclass 23, count 2 2006.217.07:45:41.36#ibcon#*mode == 0, iclass 23, count 2 2006.217.07:45:41.36#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.217.07:45:41.36#ibcon#[27=AT03-04\r\n] 2006.217.07:45:41.36#ibcon#*before write, iclass 23, count 2 2006.217.07:45:41.36#ibcon#enter sib2, iclass 23, count 2 2006.217.07:45:41.36#ibcon#flushed, iclass 23, count 2 2006.217.07:45:41.36#ibcon#about to write, iclass 23, count 2 2006.217.07:45:41.36#ibcon#wrote, iclass 23, count 2 2006.217.07:45:41.36#ibcon#about to read 3, iclass 23, count 2 2006.217.07:45:41.39#ibcon#read 3, iclass 23, count 2 2006.217.07:45:41.39#ibcon#about to read 4, iclass 23, count 2 2006.217.07:45:41.39#ibcon#read 4, iclass 23, count 2 2006.217.07:45:41.39#ibcon#about to read 5, iclass 23, count 2 2006.217.07:45:41.39#ibcon#read 5, iclass 23, count 2 2006.217.07:45:41.39#ibcon#about to read 6, iclass 23, count 2 2006.217.07:45:41.39#ibcon#read 6, iclass 23, count 2 2006.217.07:45:41.39#ibcon#end of sib2, iclass 23, count 2 2006.217.07:45:41.39#ibcon#*after write, iclass 23, count 2 2006.217.07:45:41.39#ibcon#*before return 0, iclass 23, count 2 2006.217.07:45:41.39#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.217.07:45:41.39#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.217.07:45:41.39#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.217.07:45:41.39#ibcon#ireg 7 cls_cnt 0 2006.217.07:45:41.39#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.217.07:45:41.51#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.217.07:45:41.51#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.217.07:45:41.51#ibcon#enter wrdev, iclass 23, count 0 2006.217.07:45:41.51#ibcon#first serial, iclass 23, count 0 2006.217.07:45:41.51#ibcon#enter sib2, iclass 23, count 0 2006.217.07:45:41.51#ibcon#flushed, iclass 23, count 0 2006.217.07:45:41.51#ibcon#about to write, iclass 23, count 0 2006.217.07:45:41.51#ibcon#wrote, iclass 23, count 0 2006.217.07:45:41.51#ibcon#about to read 3, iclass 23, count 0 2006.217.07:45:41.53#ibcon#read 3, iclass 23, count 0 2006.217.07:45:41.53#ibcon#about to read 4, iclass 23, count 0 2006.217.07:45:41.53#ibcon#read 4, iclass 23, count 0 2006.217.07:45:41.53#ibcon#about to read 5, iclass 23, count 0 2006.217.07:45:41.53#ibcon#read 5, iclass 23, count 0 2006.217.07:45:41.53#ibcon#about to read 6, iclass 23, count 0 2006.217.07:45:41.53#ibcon#read 6, iclass 23, count 0 2006.217.07:45:41.53#ibcon#end of sib2, iclass 23, count 0 2006.217.07:45:41.53#ibcon#*mode == 0, iclass 23, count 0 2006.217.07:45:41.53#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.217.07:45:41.53#ibcon#[27=USB\r\n] 2006.217.07:45:41.53#ibcon#*before write, iclass 23, count 0 2006.217.07:45:41.53#ibcon#enter sib2, iclass 23, count 0 2006.217.07:45:41.53#ibcon#flushed, iclass 23, count 0 2006.217.07:45:41.53#ibcon#about to write, iclass 23, count 0 2006.217.07:45:41.53#ibcon#wrote, iclass 23, count 0 2006.217.07:45:41.53#ibcon#about to read 3, iclass 23, count 0 2006.217.07:45:41.56#ibcon#read 3, iclass 23, count 0 2006.217.07:45:41.56#ibcon#about to read 4, iclass 23, count 0 2006.217.07:45:41.56#ibcon#read 4, iclass 23, count 0 2006.217.07:45:41.56#ibcon#about to read 5, iclass 23, count 0 2006.217.07:45:41.56#ibcon#read 5, iclass 23, count 0 2006.217.07:45:41.56#ibcon#about to read 6, iclass 23, count 0 2006.217.07:45:41.56#ibcon#read 6, iclass 23, count 0 2006.217.07:45:41.56#ibcon#end of sib2, iclass 23, count 0 2006.217.07:45:41.56#ibcon#*after write, iclass 23, count 0 2006.217.07:45:41.56#ibcon#*before return 0, iclass 23, count 0 2006.217.07:45:41.56#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.217.07:45:41.56#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.217.07:45:41.56#ibcon#about to clear, iclass 23 cls_cnt 0 2006.217.07:45:41.56#ibcon#cleared, iclass 23 cls_cnt 0 2006.217.07:45:41.56$vc4f8/vblo=4,712.99 2006.217.07:45:41.56#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.217.07:45:41.56#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.217.07:45:41.56#ibcon#ireg 17 cls_cnt 0 2006.217.07:45:41.56#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.217.07:45:41.56#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.217.07:45:41.56#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.217.07:45:41.56#ibcon#enter wrdev, iclass 25, count 0 2006.217.07:45:41.56#ibcon#first serial, iclass 25, count 0 2006.217.07:45:41.56#ibcon#enter sib2, iclass 25, count 0 2006.217.07:45:41.56#ibcon#flushed, iclass 25, count 0 2006.217.07:45:41.56#ibcon#about to write, iclass 25, count 0 2006.217.07:45:41.56#ibcon#wrote, iclass 25, count 0 2006.217.07:45:41.56#ibcon#about to read 3, iclass 25, count 0 2006.217.07:45:41.58#ibcon#read 3, iclass 25, count 0 2006.217.07:45:41.58#ibcon#about to read 4, iclass 25, count 0 2006.217.07:45:41.58#ibcon#read 4, iclass 25, count 0 2006.217.07:45:41.58#ibcon#about to read 5, iclass 25, count 0 2006.217.07:45:41.58#ibcon#read 5, iclass 25, count 0 2006.217.07:45:41.58#ibcon#about to read 6, iclass 25, count 0 2006.217.07:45:41.58#ibcon#read 6, iclass 25, count 0 2006.217.07:45:41.58#ibcon#end of sib2, iclass 25, count 0 2006.217.07:45:41.58#ibcon#*mode == 0, iclass 25, count 0 2006.217.07:45:41.58#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.217.07:45:41.58#ibcon#[28=FRQ=04,712.99\r\n] 2006.217.07:45:41.58#ibcon#*before write, iclass 25, count 0 2006.217.07:45:41.58#ibcon#enter sib2, iclass 25, count 0 2006.217.07:45:41.58#ibcon#flushed, iclass 25, count 0 2006.217.07:45:41.58#ibcon#about to write, iclass 25, count 0 2006.217.07:45:41.58#ibcon#wrote, iclass 25, count 0 2006.217.07:45:41.58#ibcon#about to read 3, iclass 25, count 0 2006.217.07:45:41.62#ibcon#read 3, iclass 25, count 0 2006.217.07:45:41.62#ibcon#about to read 4, iclass 25, count 0 2006.217.07:45:41.62#ibcon#read 4, iclass 25, count 0 2006.217.07:45:41.62#ibcon#about to read 5, iclass 25, count 0 2006.217.07:45:41.62#ibcon#read 5, iclass 25, count 0 2006.217.07:45:41.62#ibcon#about to read 6, iclass 25, count 0 2006.217.07:45:41.62#ibcon#read 6, iclass 25, count 0 2006.217.07:45:41.62#ibcon#end of sib2, iclass 25, count 0 2006.217.07:45:41.62#ibcon#*after write, iclass 25, count 0 2006.217.07:45:41.62#ibcon#*before return 0, iclass 25, count 0 2006.217.07:45:41.62#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.217.07:45:41.62#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.217.07:45:41.62#ibcon#about to clear, iclass 25 cls_cnt 0 2006.217.07:45:41.62#ibcon#cleared, iclass 25 cls_cnt 0 2006.217.07:45:41.62$vc4f8/vb=4,4 2006.217.07:45:41.62#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.217.07:45:41.62#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.217.07:45:41.62#ibcon#ireg 11 cls_cnt 2 2006.217.07:45:41.62#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.217.07:45:41.68#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.217.07:45:41.68#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.217.07:45:41.68#ibcon#enter wrdev, iclass 27, count 2 2006.217.07:45:41.68#ibcon#first serial, iclass 27, count 2 2006.217.07:45:41.68#ibcon#enter sib2, iclass 27, count 2 2006.217.07:45:41.68#ibcon#flushed, iclass 27, count 2 2006.217.07:45:41.68#ibcon#about to write, iclass 27, count 2 2006.217.07:45:41.68#ibcon#wrote, iclass 27, count 2 2006.217.07:45:41.68#ibcon#about to read 3, iclass 27, count 2 2006.217.07:45:41.70#ibcon#read 3, iclass 27, count 2 2006.217.07:45:41.70#ibcon#about to read 4, iclass 27, count 2 2006.217.07:45:41.70#ibcon#read 4, iclass 27, count 2 2006.217.07:45:41.70#ibcon#about to read 5, iclass 27, count 2 2006.217.07:45:41.70#ibcon#read 5, iclass 27, count 2 2006.217.07:45:41.70#ibcon#about to read 6, iclass 27, count 2 2006.217.07:45:41.70#ibcon#read 6, iclass 27, count 2 2006.217.07:45:41.70#ibcon#end of sib2, iclass 27, count 2 2006.217.07:45:41.70#ibcon#*mode == 0, iclass 27, count 2 2006.217.07:45:41.70#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.217.07:45:41.70#ibcon#[27=AT04-04\r\n] 2006.217.07:45:41.70#ibcon#*before write, iclass 27, count 2 2006.217.07:45:41.70#ibcon#enter sib2, iclass 27, count 2 2006.217.07:45:41.70#ibcon#flushed, iclass 27, count 2 2006.217.07:45:41.70#ibcon#about to write, iclass 27, count 2 2006.217.07:45:41.70#ibcon#wrote, iclass 27, count 2 2006.217.07:45:41.70#ibcon#about to read 3, iclass 27, count 2 2006.217.07:45:41.73#ibcon#read 3, iclass 27, count 2 2006.217.07:45:41.73#ibcon#about to read 4, iclass 27, count 2 2006.217.07:45:41.73#ibcon#read 4, iclass 27, count 2 2006.217.07:45:41.73#ibcon#about to read 5, iclass 27, count 2 2006.217.07:45:41.73#ibcon#read 5, iclass 27, count 2 2006.217.07:45:41.73#ibcon#about to read 6, iclass 27, count 2 2006.217.07:45:41.73#ibcon#read 6, iclass 27, count 2 2006.217.07:45:41.73#ibcon#end of sib2, iclass 27, count 2 2006.217.07:45:41.73#ibcon#*after write, iclass 27, count 2 2006.217.07:45:41.73#ibcon#*before return 0, iclass 27, count 2 2006.217.07:45:41.73#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.217.07:45:41.73#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.217.07:45:41.73#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.217.07:45:41.73#ibcon#ireg 7 cls_cnt 0 2006.217.07:45:41.73#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.217.07:45:41.85#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.217.07:45:41.85#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.217.07:45:41.85#ibcon#enter wrdev, iclass 27, count 0 2006.217.07:45:41.85#ibcon#first serial, iclass 27, count 0 2006.217.07:45:41.85#ibcon#enter sib2, iclass 27, count 0 2006.217.07:45:41.85#ibcon#flushed, iclass 27, count 0 2006.217.07:45:41.85#ibcon#about to write, iclass 27, count 0 2006.217.07:45:41.85#ibcon#wrote, iclass 27, count 0 2006.217.07:45:41.85#ibcon#about to read 3, iclass 27, count 0 2006.217.07:45:41.87#ibcon#read 3, iclass 27, count 0 2006.217.07:45:41.87#ibcon#about to read 4, iclass 27, count 0 2006.217.07:45:41.87#ibcon#read 4, iclass 27, count 0 2006.217.07:45:41.87#ibcon#about to read 5, iclass 27, count 0 2006.217.07:45:41.87#ibcon#read 5, iclass 27, count 0 2006.217.07:45:41.87#ibcon#about to read 6, iclass 27, count 0 2006.217.07:45:41.87#ibcon#read 6, iclass 27, count 0 2006.217.07:45:41.87#ibcon#end of sib2, iclass 27, count 0 2006.217.07:45:41.87#ibcon#*mode == 0, iclass 27, count 0 2006.217.07:45:41.87#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.217.07:45:41.87#ibcon#[27=USB\r\n] 2006.217.07:45:41.87#ibcon#*before write, iclass 27, count 0 2006.217.07:45:41.87#ibcon#enter sib2, iclass 27, count 0 2006.217.07:45:41.87#ibcon#flushed, iclass 27, count 0 2006.217.07:45:41.87#ibcon#about to write, iclass 27, count 0 2006.217.07:45:41.87#ibcon#wrote, iclass 27, count 0 2006.217.07:45:41.87#ibcon#about to read 3, iclass 27, count 0 2006.217.07:45:41.90#ibcon#read 3, iclass 27, count 0 2006.217.07:45:41.90#ibcon#about to read 4, iclass 27, count 0 2006.217.07:45:41.90#ibcon#read 4, iclass 27, count 0 2006.217.07:45:41.90#ibcon#about to read 5, iclass 27, count 0 2006.217.07:45:41.90#ibcon#read 5, iclass 27, count 0 2006.217.07:45:41.90#ibcon#about to read 6, iclass 27, count 0 2006.217.07:45:41.90#ibcon#read 6, iclass 27, count 0 2006.217.07:45:41.90#ibcon#end of sib2, iclass 27, count 0 2006.217.07:45:41.90#ibcon#*after write, iclass 27, count 0 2006.217.07:45:41.90#ibcon#*before return 0, iclass 27, count 0 2006.217.07:45:41.90#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.217.07:45:41.90#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.217.07:45:41.90#ibcon#about to clear, iclass 27 cls_cnt 0 2006.217.07:45:41.90#ibcon#cleared, iclass 27 cls_cnt 0 2006.217.07:45:41.90$vc4f8/vblo=5,744.99 2006.217.07:45:41.90#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.217.07:45:41.90#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.217.07:45:41.90#ibcon#ireg 17 cls_cnt 0 2006.217.07:45:41.90#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.217.07:45:41.90#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.217.07:45:41.90#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.217.07:45:41.90#ibcon#enter wrdev, iclass 29, count 0 2006.217.07:45:41.90#ibcon#first serial, iclass 29, count 0 2006.217.07:45:41.90#ibcon#enter sib2, iclass 29, count 0 2006.217.07:45:41.90#ibcon#flushed, iclass 29, count 0 2006.217.07:45:41.90#ibcon#about to write, iclass 29, count 0 2006.217.07:45:41.90#ibcon#wrote, iclass 29, count 0 2006.217.07:45:41.90#ibcon#about to read 3, iclass 29, count 0 2006.217.07:45:41.92#ibcon#read 3, iclass 29, count 0 2006.217.07:45:41.92#ibcon#about to read 4, iclass 29, count 0 2006.217.07:45:41.92#ibcon#read 4, iclass 29, count 0 2006.217.07:45:41.92#ibcon#about to read 5, iclass 29, count 0 2006.217.07:45:41.92#ibcon#read 5, iclass 29, count 0 2006.217.07:45:41.92#ibcon#about to read 6, iclass 29, count 0 2006.217.07:45:41.92#ibcon#read 6, iclass 29, count 0 2006.217.07:45:41.92#ibcon#end of sib2, iclass 29, count 0 2006.217.07:45:41.92#ibcon#*mode == 0, iclass 29, count 0 2006.217.07:45:41.92#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.217.07:45:41.92#ibcon#[28=FRQ=05,744.99\r\n] 2006.217.07:45:41.92#ibcon#*before write, iclass 29, count 0 2006.217.07:45:41.92#ibcon#enter sib2, iclass 29, count 0 2006.217.07:45:41.92#ibcon#flushed, iclass 29, count 0 2006.217.07:45:41.92#ibcon#about to write, iclass 29, count 0 2006.217.07:45:41.92#ibcon#wrote, iclass 29, count 0 2006.217.07:45:41.92#ibcon#about to read 3, iclass 29, count 0 2006.217.07:45:41.96#ibcon#read 3, iclass 29, count 0 2006.217.07:45:41.96#ibcon#about to read 4, iclass 29, count 0 2006.217.07:45:41.96#ibcon#read 4, iclass 29, count 0 2006.217.07:45:41.96#ibcon#about to read 5, iclass 29, count 0 2006.217.07:45:41.96#ibcon#read 5, iclass 29, count 0 2006.217.07:45:41.96#ibcon#about to read 6, iclass 29, count 0 2006.217.07:45:41.96#ibcon#read 6, iclass 29, count 0 2006.217.07:45:41.96#ibcon#end of sib2, iclass 29, count 0 2006.217.07:45:41.96#ibcon#*after write, iclass 29, count 0 2006.217.07:45:41.96#ibcon#*before return 0, iclass 29, count 0 2006.217.07:45:41.96#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.217.07:45:41.96#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.217.07:45:41.96#ibcon#about to clear, iclass 29 cls_cnt 0 2006.217.07:45:41.96#ibcon#cleared, iclass 29 cls_cnt 0 2006.217.07:45:41.96$vc4f8/vb=5,4 2006.217.07:45:41.96#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.217.07:45:41.96#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.217.07:45:41.96#ibcon#ireg 11 cls_cnt 2 2006.217.07:45:41.96#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.217.07:45:42.02#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.217.07:45:42.02#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.217.07:45:42.02#ibcon#enter wrdev, iclass 31, count 2 2006.217.07:45:42.02#ibcon#first serial, iclass 31, count 2 2006.217.07:45:42.02#ibcon#enter sib2, iclass 31, count 2 2006.217.07:45:42.02#ibcon#flushed, iclass 31, count 2 2006.217.07:45:42.02#ibcon#about to write, iclass 31, count 2 2006.217.07:45:42.02#ibcon#wrote, iclass 31, count 2 2006.217.07:45:42.02#ibcon#about to read 3, iclass 31, count 2 2006.217.07:45:42.04#ibcon#read 3, iclass 31, count 2 2006.217.07:45:42.04#ibcon#about to read 4, iclass 31, count 2 2006.217.07:45:42.04#ibcon#read 4, iclass 31, count 2 2006.217.07:45:42.04#ibcon#about to read 5, iclass 31, count 2 2006.217.07:45:42.04#ibcon#read 5, iclass 31, count 2 2006.217.07:45:42.04#ibcon#about to read 6, iclass 31, count 2 2006.217.07:45:42.04#ibcon#read 6, iclass 31, count 2 2006.217.07:45:42.04#ibcon#end of sib2, iclass 31, count 2 2006.217.07:45:42.04#ibcon#*mode == 0, iclass 31, count 2 2006.217.07:45:42.04#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.217.07:45:42.04#ibcon#[27=AT05-04\r\n] 2006.217.07:45:42.04#ibcon#*before write, iclass 31, count 2 2006.217.07:45:42.04#ibcon#enter sib2, iclass 31, count 2 2006.217.07:45:42.04#ibcon#flushed, iclass 31, count 2 2006.217.07:45:42.05#ibcon#about to write, iclass 31, count 2 2006.217.07:45:42.05#ibcon#wrote, iclass 31, count 2 2006.217.07:45:42.05#ibcon#about to read 3, iclass 31, count 2 2006.217.07:45:42.07#ibcon#read 3, iclass 31, count 2 2006.217.07:45:42.07#ibcon#about to read 4, iclass 31, count 2 2006.217.07:45:42.07#ibcon#read 4, iclass 31, count 2 2006.217.07:45:42.07#ibcon#about to read 5, iclass 31, count 2 2006.217.07:45:42.07#ibcon#read 5, iclass 31, count 2 2006.217.07:45:42.07#ibcon#about to read 6, iclass 31, count 2 2006.217.07:45:42.07#ibcon#read 6, iclass 31, count 2 2006.217.07:45:42.07#ibcon#end of sib2, iclass 31, count 2 2006.217.07:45:42.07#ibcon#*after write, iclass 31, count 2 2006.217.07:45:42.07#ibcon#*before return 0, iclass 31, count 2 2006.217.07:45:42.07#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.217.07:45:42.07#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.217.07:45:42.07#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.217.07:45:42.07#ibcon#ireg 7 cls_cnt 0 2006.217.07:45:42.07#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.217.07:45:42.19#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.217.07:45:42.19#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.217.07:45:42.19#ibcon#enter wrdev, iclass 31, count 0 2006.217.07:45:42.19#ibcon#first serial, iclass 31, count 0 2006.217.07:45:42.19#ibcon#enter sib2, iclass 31, count 0 2006.217.07:45:42.19#ibcon#flushed, iclass 31, count 0 2006.217.07:45:42.19#ibcon#about to write, iclass 31, count 0 2006.217.07:45:42.19#ibcon#wrote, iclass 31, count 0 2006.217.07:45:42.19#ibcon#about to read 3, iclass 31, count 0 2006.217.07:45:42.21#ibcon#read 3, iclass 31, count 0 2006.217.07:45:42.21#ibcon#about to read 4, iclass 31, count 0 2006.217.07:45:42.21#ibcon#read 4, iclass 31, count 0 2006.217.07:45:42.21#ibcon#about to read 5, iclass 31, count 0 2006.217.07:45:42.21#ibcon#read 5, iclass 31, count 0 2006.217.07:45:42.21#ibcon#about to read 6, iclass 31, count 0 2006.217.07:45:42.21#ibcon#read 6, iclass 31, count 0 2006.217.07:45:42.21#ibcon#end of sib2, iclass 31, count 0 2006.217.07:45:42.21#ibcon#*mode == 0, iclass 31, count 0 2006.217.07:45:42.21#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.217.07:45:42.21#ibcon#[27=USB\r\n] 2006.217.07:45:42.21#ibcon#*before write, iclass 31, count 0 2006.217.07:45:42.21#ibcon#enter sib2, iclass 31, count 0 2006.217.07:45:42.21#ibcon#flushed, iclass 31, count 0 2006.217.07:45:42.21#ibcon#about to write, iclass 31, count 0 2006.217.07:45:42.21#ibcon#wrote, iclass 31, count 0 2006.217.07:45:42.21#ibcon#about to read 3, iclass 31, count 0 2006.217.07:45:42.24#ibcon#read 3, iclass 31, count 0 2006.217.07:45:42.24#ibcon#about to read 4, iclass 31, count 0 2006.217.07:45:42.24#ibcon#read 4, iclass 31, count 0 2006.217.07:45:42.24#ibcon#about to read 5, iclass 31, count 0 2006.217.07:45:42.24#ibcon#read 5, iclass 31, count 0 2006.217.07:45:42.24#ibcon#about to read 6, iclass 31, count 0 2006.217.07:45:42.24#ibcon#read 6, iclass 31, count 0 2006.217.07:45:42.24#ibcon#end of sib2, iclass 31, count 0 2006.217.07:45:42.24#ibcon#*after write, iclass 31, count 0 2006.217.07:45:42.24#ibcon#*before return 0, iclass 31, count 0 2006.217.07:45:42.24#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.217.07:45:42.24#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.217.07:45:42.24#ibcon#about to clear, iclass 31 cls_cnt 0 2006.217.07:45:42.24#ibcon#cleared, iclass 31 cls_cnt 0 2006.217.07:45:42.24$vc4f8/vblo=6,752.99 2006.217.07:45:42.24#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.217.07:45:42.24#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.217.07:45:42.24#ibcon#ireg 17 cls_cnt 0 2006.217.07:45:42.24#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.217.07:45:42.24#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.217.07:45:42.24#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.217.07:45:42.24#ibcon#enter wrdev, iclass 33, count 0 2006.217.07:45:42.24#ibcon#first serial, iclass 33, count 0 2006.217.07:45:42.24#ibcon#enter sib2, iclass 33, count 0 2006.217.07:45:42.24#ibcon#flushed, iclass 33, count 0 2006.217.07:45:42.24#ibcon#about to write, iclass 33, count 0 2006.217.07:45:42.24#ibcon#wrote, iclass 33, count 0 2006.217.07:45:42.24#ibcon#about to read 3, iclass 33, count 0 2006.217.07:45:42.26#ibcon#read 3, iclass 33, count 0 2006.217.07:45:42.26#ibcon#about to read 4, iclass 33, count 0 2006.217.07:45:42.26#ibcon#read 4, iclass 33, count 0 2006.217.07:45:42.26#ibcon#about to read 5, iclass 33, count 0 2006.217.07:45:42.26#ibcon#read 5, iclass 33, count 0 2006.217.07:45:42.26#ibcon#about to read 6, iclass 33, count 0 2006.217.07:45:42.26#ibcon#read 6, iclass 33, count 0 2006.217.07:45:42.26#ibcon#end of sib2, iclass 33, count 0 2006.217.07:45:42.26#ibcon#*mode == 0, iclass 33, count 0 2006.217.07:45:42.26#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.217.07:45:42.26#ibcon#[28=FRQ=06,752.99\r\n] 2006.217.07:45:42.26#ibcon#*before write, iclass 33, count 0 2006.217.07:45:42.26#ibcon#enter sib2, iclass 33, count 0 2006.217.07:45:42.26#ibcon#flushed, iclass 33, count 0 2006.217.07:45:42.26#ibcon#about to write, iclass 33, count 0 2006.217.07:45:42.26#ibcon#wrote, iclass 33, count 0 2006.217.07:45:42.26#ibcon#about to read 3, iclass 33, count 0 2006.217.07:45:42.30#ibcon#read 3, iclass 33, count 0 2006.217.07:45:42.30#ibcon#about to read 4, iclass 33, count 0 2006.217.07:45:42.30#ibcon#read 4, iclass 33, count 0 2006.217.07:45:42.30#ibcon#about to read 5, iclass 33, count 0 2006.217.07:45:42.30#ibcon#read 5, iclass 33, count 0 2006.217.07:45:42.30#ibcon#about to read 6, iclass 33, count 0 2006.217.07:45:42.30#ibcon#read 6, iclass 33, count 0 2006.217.07:45:42.30#ibcon#end of sib2, iclass 33, count 0 2006.217.07:45:42.30#ibcon#*after write, iclass 33, count 0 2006.217.07:45:42.30#ibcon#*before return 0, iclass 33, count 0 2006.217.07:45:42.30#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.217.07:45:42.30#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.217.07:45:42.30#ibcon#about to clear, iclass 33 cls_cnt 0 2006.217.07:45:42.30#ibcon#cleared, iclass 33 cls_cnt 0 2006.217.07:45:42.30$vc4f8/vb=6,4 2006.217.07:45:42.30#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.217.07:45:42.30#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.217.07:45:42.30#ibcon#ireg 11 cls_cnt 2 2006.217.07:45:42.30#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.217.07:45:42.36#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.217.07:45:42.36#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.217.07:45:42.36#ibcon#enter wrdev, iclass 35, count 2 2006.217.07:45:42.36#ibcon#first serial, iclass 35, count 2 2006.217.07:45:42.36#ibcon#enter sib2, iclass 35, count 2 2006.217.07:45:42.36#ibcon#flushed, iclass 35, count 2 2006.217.07:45:42.36#ibcon#about to write, iclass 35, count 2 2006.217.07:45:42.36#ibcon#wrote, iclass 35, count 2 2006.217.07:45:42.36#ibcon#about to read 3, iclass 35, count 2 2006.217.07:45:42.38#ibcon#read 3, iclass 35, count 2 2006.217.07:45:42.38#ibcon#about to read 4, iclass 35, count 2 2006.217.07:45:42.38#ibcon#read 4, iclass 35, count 2 2006.217.07:45:42.38#ibcon#about to read 5, iclass 35, count 2 2006.217.07:45:42.38#ibcon#read 5, iclass 35, count 2 2006.217.07:45:42.38#ibcon#about to read 6, iclass 35, count 2 2006.217.07:45:42.38#ibcon#read 6, iclass 35, count 2 2006.217.07:45:42.38#ibcon#end of sib2, iclass 35, count 2 2006.217.07:45:42.38#ibcon#*mode == 0, iclass 35, count 2 2006.217.07:45:42.38#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.217.07:45:42.38#ibcon#[27=AT06-04\r\n] 2006.217.07:45:42.38#ibcon#*before write, iclass 35, count 2 2006.217.07:45:42.38#ibcon#enter sib2, iclass 35, count 2 2006.217.07:45:42.38#ibcon#flushed, iclass 35, count 2 2006.217.07:45:42.38#ibcon#about to write, iclass 35, count 2 2006.217.07:45:42.38#ibcon#wrote, iclass 35, count 2 2006.217.07:45:42.38#ibcon#about to read 3, iclass 35, count 2 2006.217.07:45:42.41#ibcon#read 3, iclass 35, count 2 2006.217.07:45:42.41#ibcon#about to read 4, iclass 35, count 2 2006.217.07:45:42.41#ibcon#read 4, iclass 35, count 2 2006.217.07:45:42.41#ibcon#about to read 5, iclass 35, count 2 2006.217.07:45:42.41#ibcon#read 5, iclass 35, count 2 2006.217.07:45:42.41#ibcon#about to read 6, iclass 35, count 2 2006.217.07:45:42.41#ibcon#read 6, iclass 35, count 2 2006.217.07:45:42.41#ibcon#end of sib2, iclass 35, count 2 2006.217.07:45:42.41#ibcon#*after write, iclass 35, count 2 2006.217.07:45:42.41#ibcon#*before return 0, iclass 35, count 2 2006.217.07:45:42.41#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.217.07:45:42.41#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.217.07:45:42.41#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.217.07:45:42.41#ibcon#ireg 7 cls_cnt 0 2006.217.07:45:42.41#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.217.07:45:42.53#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.217.07:45:42.53#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.217.07:45:42.53#ibcon#enter wrdev, iclass 35, count 0 2006.217.07:45:42.53#ibcon#first serial, iclass 35, count 0 2006.217.07:45:42.53#ibcon#enter sib2, iclass 35, count 0 2006.217.07:45:42.53#ibcon#flushed, iclass 35, count 0 2006.217.07:45:42.53#ibcon#about to write, iclass 35, count 0 2006.217.07:45:42.53#ibcon#wrote, iclass 35, count 0 2006.217.07:45:42.53#ibcon#about to read 3, iclass 35, count 0 2006.217.07:45:42.55#ibcon#read 3, iclass 35, count 0 2006.217.07:45:42.55#ibcon#about to read 4, iclass 35, count 0 2006.217.07:45:42.55#ibcon#read 4, iclass 35, count 0 2006.217.07:45:42.55#ibcon#about to read 5, iclass 35, count 0 2006.217.07:45:42.55#ibcon#read 5, iclass 35, count 0 2006.217.07:45:42.55#ibcon#about to read 6, iclass 35, count 0 2006.217.07:45:42.55#ibcon#read 6, iclass 35, count 0 2006.217.07:45:42.55#ibcon#end of sib2, iclass 35, count 0 2006.217.07:45:42.55#ibcon#*mode == 0, iclass 35, count 0 2006.217.07:45:42.55#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.217.07:45:42.55#ibcon#[27=USB\r\n] 2006.217.07:45:42.55#ibcon#*before write, iclass 35, count 0 2006.217.07:45:42.55#ibcon#enter sib2, iclass 35, count 0 2006.217.07:45:42.55#ibcon#flushed, iclass 35, count 0 2006.217.07:45:42.55#ibcon#about to write, iclass 35, count 0 2006.217.07:45:42.55#ibcon#wrote, iclass 35, count 0 2006.217.07:45:42.55#ibcon#about to read 3, iclass 35, count 0 2006.217.07:45:42.58#ibcon#read 3, iclass 35, count 0 2006.217.07:45:42.58#ibcon#about to read 4, iclass 35, count 0 2006.217.07:45:42.58#ibcon#read 4, iclass 35, count 0 2006.217.07:45:42.58#ibcon#about to read 5, iclass 35, count 0 2006.217.07:45:42.58#ibcon#read 5, iclass 35, count 0 2006.217.07:45:42.58#ibcon#about to read 6, iclass 35, count 0 2006.217.07:45:42.58#ibcon#read 6, iclass 35, count 0 2006.217.07:45:42.58#ibcon#end of sib2, iclass 35, count 0 2006.217.07:45:42.58#ibcon#*after write, iclass 35, count 0 2006.217.07:45:42.58#ibcon#*before return 0, iclass 35, count 0 2006.217.07:45:42.58#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.217.07:45:42.58#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.217.07:45:42.58#ibcon#about to clear, iclass 35 cls_cnt 0 2006.217.07:45:42.58#ibcon#cleared, iclass 35 cls_cnt 0 2006.217.07:45:42.58$vc4f8/vabw=wide 2006.217.07:45:42.58#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.217.07:45:42.58#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.217.07:45:42.58#ibcon#ireg 8 cls_cnt 0 2006.217.07:45:42.58#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.217.07:45:42.58#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.217.07:45:42.58#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.217.07:45:42.58#ibcon#enter wrdev, iclass 37, count 0 2006.217.07:45:42.58#ibcon#first serial, iclass 37, count 0 2006.217.07:45:42.58#ibcon#enter sib2, iclass 37, count 0 2006.217.07:45:42.58#ibcon#flushed, iclass 37, count 0 2006.217.07:45:42.58#ibcon#about to write, iclass 37, count 0 2006.217.07:45:42.58#ibcon#wrote, iclass 37, count 0 2006.217.07:45:42.58#ibcon#about to read 3, iclass 37, count 0 2006.217.07:45:42.60#ibcon#read 3, iclass 37, count 0 2006.217.07:45:42.60#ibcon#about to read 4, iclass 37, count 0 2006.217.07:45:42.60#ibcon#read 4, iclass 37, count 0 2006.217.07:45:42.60#ibcon#about to read 5, iclass 37, count 0 2006.217.07:45:42.60#ibcon#read 5, iclass 37, count 0 2006.217.07:45:42.60#ibcon#about to read 6, iclass 37, count 0 2006.217.07:45:42.60#ibcon#read 6, iclass 37, count 0 2006.217.07:45:42.60#ibcon#end of sib2, iclass 37, count 0 2006.217.07:45:42.60#ibcon#*mode == 0, iclass 37, count 0 2006.217.07:45:42.60#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.217.07:45:42.60#ibcon#[25=BW32\r\n] 2006.217.07:45:42.60#ibcon#*before write, iclass 37, count 0 2006.217.07:45:42.60#ibcon#enter sib2, iclass 37, count 0 2006.217.07:45:42.60#ibcon#flushed, iclass 37, count 0 2006.217.07:45:42.60#ibcon#about to write, iclass 37, count 0 2006.217.07:45:42.60#ibcon#wrote, iclass 37, count 0 2006.217.07:45:42.60#ibcon#about to read 3, iclass 37, count 0 2006.217.07:45:42.63#ibcon#read 3, iclass 37, count 0 2006.217.07:45:42.63#ibcon#about to read 4, iclass 37, count 0 2006.217.07:45:42.63#ibcon#read 4, iclass 37, count 0 2006.217.07:45:42.63#ibcon#about to read 5, iclass 37, count 0 2006.217.07:45:42.63#ibcon#read 5, iclass 37, count 0 2006.217.07:45:42.63#ibcon#about to read 6, iclass 37, count 0 2006.217.07:45:42.63#ibcon#read 6, iclass 37, count 0 2006.217.07:45:42.63#ibcon#end of sib2, iclass 37, count 0 2006.217.07:45:42.63#ibcon#*after write, iclass 37, count 0 2006.217.07:45:42.63#ibcon#*before return 0, iclass 37, count 0 2006.217.07:45:42.63#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.217.07:45:42.63#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.217.07:45:42.63#ibcon#about to clear, iclass 37 cls_cnt 0 2006.217.07:45:42.63#ibcon#cleared, iclass 37 cls_cnt 0 2006.217.07:45:42.63$vc4f8/vbbw=wide 2006.217.07:45:42.63#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.217.07:45:42.63#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.217.07:45:42.63#ibcon#ireg 8 cls_cnt 0 2006.217.07:45:42.63#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.217.07:45:42.70#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.217.07:45:42.70#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.217.07:45:42.70#ibcon#enter wrdev, iclass 39, count 0 2006.217.07:45:42.70#ibcon#first serial, iclass 39, count 0 2006.217.07:45:42.70#ibcon#enter sib2, iclass 39, count 0 2006.217.07:45:42.70#ibcon#flushed, iclass 39, count 0 2006.217.07:45:42.70#ibcon#about to write, iclass 39, count 0 2006.217.07:45:42.70#ibcon#wrote, iclass 39, count 0 2006.217.07:45:42.70#ibcon#about to read 3, iclass 39, count 0 2006.217.07:45:42.72#ibcon#read 3, iclass 39, count 0 2006.217.07:45:42.72#ibcon#about to read 4, iclass 39, count 0 2006.217.07:45:42.72#ibcon#read 4, iclass 39, count 0 2006.217.07:45:42.72#ibcon#about to read 5, iclass 39, count 0 2006.217.07:45:42.72#ibcon#read 5, iclass 39, count 0 2006.217.07:45:42.72#ibcon#about to read 6, iclass 39, count 0 2006.217.07:45:42.72#ibcon#read 6, iclass 39, count 0 2006.217.07:45:42.72#ibcon#end of sib2, iclass 39, count 0 2006.217.07:45:42.72#ibcon#*mode == 0, iclass 39, count 0 2006.217.07:45:42.72#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.217.07:45:42.72#ibcon#[27=BW32\r\n] 2006.217.07:45:42.72#ibcon#*before write, iclass 39, count 0 2006.217.07:45:42.72#ibcon#enter sib2, iclass 39, count 0 2006.217.07:45:42.72#ibcon#flushed, iclass 39, count 0 2006.217.07:45:42.72#ibcon#about to write, iclass 39, count 0 2006.217.07:45:42.72#ibcon#wrote, iclass 39, count 0 2006.217.07:45:42.72#ibcon#about to read 3, iclass 39, count 0 2006.217.07:45:42.75#ibcon#read 3, iclass 39, count 0 2006.217.07:45:42.75#ibcon#about to read 4, iclass 39, count 0 2006.217.07:45:42.75#ibcon#read 4, iclass 39, count 0 2006.217.07:45:42.75#ibcon#about to read 5, iclass 39, count 0 2006.217.07:45:42.75#ibcon#read 5, iclass 39, count 0 2006.217.07:45:42.75#ibcon#about to read 6, iclass 39, count 0 2006.217.07:45:42.75#ibcon#read 6, iclass 39, count 0 2006.217.07:45:42.75#ibcon#end of sib2, iclass 39, count 0 2006.217.07:45:42.75#ibcon#*after write, iclass 39, count 0 2006.217.07:45:42.75#ibcon#*before return 0, iclass 39, count 0 2006.217.07:45:42.75#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.217.07:45:42.75#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.217.07:45:42.75#ibcon#about to clear, iclass 39 cls_cnt 0 2006.217.07:45:42.75#ibcon#cleared, iclass 39 cls_cnt 0 2006.217.07:45:42.75$4f8m12a/ifd4f 2006.217.07:45:42.75$ifd4f/lo= 2006.217.07:45:42.75$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.217.07:45:42.75$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.217.07:45:42.75$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.217.07:45:42.75$ifd4f/patch= 2006.217.07:45:42.75$ifd4f/patch=lo1,a1,a2,a3,a4 2006.217.07:45:42.76$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.217.07:45:42.76$ifd4f/patch=lo3,a5,a6,a7,a8 2006.217.07:45:42.76$4f8m12a/"form=m,16.000,1:2 2006.217.07:45:42.76$4f8m12a/"tpicd 2006.217.07:45:42.76$4f8m12a/echo=off 2006.217.07:45:42.76$4f8m12a/xlog=off 2006.217.07:45:42.76:!2006.217.07:46:40 2006.217.07:46:19.14#trakl#Source acquired 2006.217.07:46:19.14#flagr#flagr/antenna,acquired 2006.217.07:46:40.01:preob 2006.217.07:46:41.14/onsource/TRACKING 2006.217.07:46:41.14:!2006.217.07:46:50 2006.217.07:46:50.00:data_valid=on 2006.217.07:46:50.00:midob 2006.217.07:46:50.14/onsource/TRACKING 2006.217.07:46:50.14/wx/31.27,1008.6,62 2006.217.07:46:50.34/cable/+6.3865E-03 2006.217.07:46:51.43/va/01,05,usb,yes,32,34 2006.217.07:46:51.43/va/02,04,usb,yes,30,31 2006.217.07:46:51.43/va/03,04,usb,yes,28,28 2006.217.07:46:51.43/va/04,04,usb,yes,31,34 2006.217.07:46:51.43/va/05,07,usb,yes,33,35 2006.217.07:46:51.43/va/06,06,usb,yes,32,32 2006.217.07:46:51.43/va/07,06,usb,yes,33,32 2006.217.07:46:51.43/va/08,07,usb,yes,31,30 2006.217.07:46:51.66/valo/01,532.99,yes,locked 2006.217.07:46:51.66/valo/02,572.99,yes,locked 2006.217.07:46:51.66/valo/03,672.99,yes,locked 2006.217.07:46:51.66/valo/04,832.99,yes,locked 2006.217.07:46:51.66/valo/05,652.99,yes,locked 2006.217.07:46:51.66/valo/06,772.99,yes,locked 2006.217.07:46:51.66/valo/07,832.99,yes,locked 2006.217.07:46:51.66/valo/08,852.99,yes,locked 2006.217.07:46:52.75/vb/01,04,usb,yes,31,29 2006.217.07:46:52.75/vb/02,04,usb,yes,32,34 2006.217.07:46:52.75/vb/03,04,usb,yes,29,33 2006.217.07:46:52.75/vb/04,04,usb,yes,30,30 2006.217.07:46:52.75/vb/05,04,usb,yes,28,32 2006.217.07:46:52.75/vb/06,04,usb,yes,29,32 2006.217.07:46:52.75/vb/07,04,usb,yes,31,31 2006.217.07:46:52.75/vb/08,04,usb,yes,29,32 2006.217.07:46:52.99/vblo/01,632.99,yes,locked 2006.217.07:46:52.99/vblo/02,640.99,yes,locked 2006.217.07:46:52.99/vblo/03,656.99,yes,locked 2006.217.07:46:52.99/vblo/04,712.99,yes,locked 2006.217.07:46:52.99/vblo/05,744.99,yes,locked 2006.217.07:46:52.99/vblo/06,752.99,yes,locked 2006.217.07:46:52.99/vblo/07,734.99,yes,locked 2006.217.07:46:52.99/vblo/08,744.99,yes,locked 2006.217.07:46:53.14/vabw/8 2006.217.07:46:53.29/vbbw/8 2006.217.07:46:53.38/xfe/off,on,15.0 2006.217.07:46:53.76/ifatt/23,28,28,28 2006.217.07:46:54.07/fmout-gps/S +4.21E-07 2006.217.07:46:54.15:!2006.217.07:48:30 2006.217.07:48:30.01:data_valid=off 2006.217.07:48:30.02:postob 2006.217.07:48:30.14/cable/+6.3870E-03 2006.217.07:48:30.15/wx/31.25,1008.6,63 2006.217.07:48:31.07/fmout-gps/S +4.18E-07 2006.217.07:48:31.08:scan_name=217-0749,k06217,60 2006.217.07:48:31.08:source=0743+259,074625.87,254902.1,2000.0,ccw 2006.217.07:48:32.14#flagr#flagr/antenna,new-source 2006.217.07:48:32.15:checkk5 2006.217.07:48:32.53/chk_autoobs//k5ts1/ autoobs is running! 2006.217.07:48:32.91/chk_autoobs//k5ts2/ autoobs is running! 2006.217.07:48:33.29/chk_autoobs//k5ts3/ autoobs is running! 2006.217.07:48:33.66/chk_autoobs//k5ts4/ autoobs is running! 2006.217.07:48:34.03/chk_obsdata//k5ts1/T2170746??a.dat file size is correct (nominal:800MB, actual:792MB). 2006.217.07:48:34.40/chk_obsdata//k5ts2/T2170746??b.dat file size is correct (nominal:800MB, actual:792MB). 2006.217.07:48:34.77/chk_obsdata//k5ts3/T2170746??c.dat file size is correct (nominal:800MB, actual:792MB). 2006.217.07:48:35.14/chk_obsdata//k5ts4/T2170746??d.dat file size is correct (nominal:800MB, actual:792MB). 2006.217.07:48:35.83/k5log//k5ts1_log_newline 2006.217.07:48:36.52/k5log//k5ts2_log_newline 2006.217.07:48:37.21/k5log//k5ts3_log_newline 2006.217.07:48:37.89/k5log//k5ts4_log_newline 2006.217.07:48:37.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.217.07:48:37.92:4f8m12a=1 2006.217.07:48:37.92$4f8m12a/echo=on 2006.217.07:48:37.92$4f8m12a/pcalon 2006.217.07:48:37.92$pcalon/"no phase cal control is implemented here 2006.217.07:48:37.92$4f8m12a/"tpicd=stop 2006.217.07:48:37.92$4f8m12a/vc4f8 2006.217.07:48:37.92$vc4f8/valo=1,532.99 2006.217.07:48:37.92#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.217.07:48:37.92#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.217.07:48:37.92#ibcon#ireg 17 cls_cnt 0 2006.217.07:48:37.92#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.217.07:48:37.92#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.217.07:48:37.92#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.217.07:48:37.92#ibcon#enter wrdev, iclass 38, count 0 2006.217.07:48:37.92#ibcon#first serial, iclass 38, count 0 2006.217.07:48:37.92#ibcon#enter sib2, iclass 38, count 0 2006.217.07:48:37.92#ibcon#flushed, iclass 38, count 0 2006.217.07:48:37.92#ibcon#about to write, iclass 38, count 0 2006.217.07:48:37.92#ibcon#wrote, iclass 38, count 0 2006.217.07:48:37.92#ibcon#about to read 3, iclass 38, count 0 2006.217.07:48:37.93#ibcon#read 3, iclass 38, count 0 2006.217.07:48:37.93#ibcon#about to read 4, iclass 38, count 0 2006.217.07:48:37.93#ibcon#read 4, iclass 38, count 0 2006.217.07:48:37.93#ibcon#about to read 5, iclass 38, count 0 2006.217.07:48:37.93#ibcon#read 5, iclass 38, count 0 2006.217.07:48:37.93#ibcon#about to read 6, iclass 38, count 0 2006.217.07:48:37.93#ibcon#read 6, iclass 38, count 0 2006.217.07:48:37.93#ibcon#end of sib2, iclass 38, count 0 2006.217.07:48:37.93#ibcon#*mode == 0, iclass 38, count 0 2006.217.07:48:37.93#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.217.07:48:37.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.217.07:48:37.93#ibcon#*before write, iclass 38, count 0 2006.217.07:48:37.93#ibcon#enter sib2, iclass 38, count 0 2006.217.07:48:37.93#ibcon#flushed, iclass 38, count 0 2006.217.07:48:37.93#ibcon#about to write, iclass 38, count 0 2006.217.07:48:37.93#ibcon#wrote, iclass 38, count 0 2006.217.07:48:37.93#ibcon#about to read 3, iclass 38, count 0 2006.217.07:48:37.98#ibcon#read 3, iclass 38, count 0 2006.217.07:48:37.98#ibcon#about to read 4, iclass 38, count 0 2006.217.07:48:37.98#ibcon#read 4, iclass 38, count 0 2006.217.07:48:37.98#ibcon#about to read 5, iclass 38, count 0 2006.217.07:48:37.98#ibcon#read 5, iclass 38, count 0 2006.217.07:48:37.98#ibcon#about to read 6, iclass 38, count 0 2006.217.07:48:37.98#ibcon#read 6, iclass 38, count 0 2006.217.07:48:37.98#ibcon#end of sib2, iclass 38, count 0 2006.217.07:48:37.98#ibcon#*after write, iclass 38, count 0 2006.217.07:48:37.98#ibcon#*before return 0, iclass 38, count 0 2006.217.07:48:37.98#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.217.07:48:37.98#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.217.07:48:37.98#ibcon#about to clear, iclass 38 cls_cnt 0 2006.217.07:48:37.98#ibcon#cleared, iclass 38 cls_cnt 0 2006.217.07:48:37.98$vc4f8/va=1,5 2006.217.07:48:37.98#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.217.07:48:37.98#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.217.07:48:37.98#ibcon#ireg 11 cls_cnt 2 2006.217.07:48:37.98#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.217.07:48:37.98#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.217.07:48:37.98#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.217.07:48:37.98#ibcon#enter wrdev, iclass 40, count 2 2006.217.07:48:37.98#ibcon#first serial, iclass 40, count 2 2006.217.07:48:37.98#ibcon#enter sib2, iclass 40, count 2 2006.217.07:48:37.98#ibcon#flushed, iclass 40, count 2 2006.217.07:48:37.98#ibcon#about to write, iclass 40, count 2 2006.217.07:48:37.98#ibcon#wrote, iclass 40, count 2 2006.217.07:48:37.98#ibcon#about to read 3, iclass 40, count 2 2006.217.07:48:38.00#ibcon#read 3, iclass 40, count 2 2006.217.07:48:38.00#ibcon#about to read 4, iclass 40, count 2 2006.217.07:48:38.00#ibcon#read 4, iclass 40, count 2 2006.217.07:48:38.00#ibcon#about to read 5, iclass 40, count 2 2006.217.07:48:38.00#ibcon#read 5, iclass 40, count 2 2006.217.07:48:38.00#ibcon#about to read 6, iclass 40, count 2 2006.217.07:48:38.00#ibcon#read 6, iclass 40, count 2 2006.217.07:48:38.00#ibcon#end of sib2, iclass 40, count 2 2006.217.07:48:38.00#ibcon#*mode == 0, iclass 40, count 2 2006.217.07:48:38.00#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.217.07:48:38.00#ibcon#[25=AT01-05\r\n] 2006.217.07:48:38.00#ibcon#*before write, iclass 40, count 2 2006.217.07:48:38.00#ibcon#enter sib2, iclass 40, count 2 2006.217.07:48:38.00#ibcon#flushed, iclass 40, count 2 2006.217.07:48:38.00#ibcon#about to write, iclass 40, count 2 2006.217.07:48:38.00#ibcon#wrote, iclass 40, count 2 2006.217.07:48:38.00#ibcon#about to read 3, iclass 40, count 2 2006.217.07:48:38.03#ibcon#read 3, iclass 40, count 2 2006.217.07:48:38.03#ibcon#about to read 4, iclass 40, count 2 2006.217.07:48:38.03#ibcon#read 4, iclass 40, count 2 2006.217.07:48:38.03#ibcon#about to read 5, iclass 40, count 2 2006.217.07:48:38.03#ibcon#read 5, iclass 40, count 2 2006.217.07:48:38.03#ibcon#about to read 6, iclass 40, count 2 2006.217.07:48:38.03#ibcon#read 6, iclass 40, count 2 2006.217.07:48:38.03#ibcon#end of sib2, iclass 40, count 2 2006.217.07:48:38.03#ibcon#*after write, iclass 40, count 2 2006.217.07:48:38.03#ibcon#*before return 0, iclass 40, count 2 2006.217.07:48:38.03#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.217.07:48:38.03#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.217.07:48:38.03#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.217.07:48:38.03#ibcon#ireg 7 cls_cnt 0 2006.217.07:48:38.03#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.217.07:48:38.16#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.217.07:48:38.16#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.217.07:48:38.16#ibcon#enter wrdev, iclass 40, count 0 2006.217.07:48:38.16#ibcon#first serial, iclass 40, count 0 2006.217.07:48:38.16#ibcon#enter sib2, iclass 40, count 0 2006.217.07:48:38.16#ibcon#flushed, iclass 40, count 0 2006.217.07:48:38.16#ibcon#about to write, iclass 40, count 0 2006.217.07:48:38.16#ibcon#wrote, iclass 40, count 0 2006.217.07:48:38.16#ibcon#about to read 3, iclass 40, count 0 2006.217.07:48:38.17#ibcon#read 3, iclass 40, count 0 2006.217.07:48:38.17#ibcon#about to read 4, iclass 40, count 0 2006.217.07:48:38.17#ibcon#read 4, iclass 40, count 0 2006.217.07:48:38.17#ibcon#about to read 5, iclass 40, count 0 2006.217.07:48:38.17#ibcon#read 5, iclass 40, count 0 2006.217.07:48:38.17#ibcon#about to read 6, iclass 40, count 0 2006.217.07:48:38.17#ibcon#read 6, iclass 40, count 0 2006.217.07:48:38.17#ibcon#end of sib2, iclass 40, count 0 2006.217.07:48:38.17#ibcon#*mode == 0, iclass 40, count 0 2006.217.07:48:38.17#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.217.07:48:38.17#ibcon#[25=USB\r\n] 2006.217.07:48:38.17#ibcon#*before write, iclass 40, count 0 2006.217.07:48:38.17#ibcon#enter sib2, iclass 40, count 0 2006.217.07:48:38.17#ibcon#flushed, iclass 40, count 0 2006.217.07:48:38.17#ibcon#about to write, iclass 40, count 0 2006.217.07:48:38.17#ibcon#wrote, iclass 40, count 0 2006.217.07:48:38.17#ibcon#about to read 3, iclass 40, count 0 2006.217.07:48:38.20#ibcon#read 3, iclass 40, count 0 2006.217.07:48:38.20#ibcon#about to read 4, iclass 40, count 0 2006.217.07:48:38.20#ibcon#read 4, iclass 40, count 0 2006.217.07:48:38.20#ibcon#about to read 5, iclass 40, count 0 2006.217.07:48:38.20#ibcon#read 5, iclass 40, count 0 2006.217.07:48:38.20#ibcon#about to read 6, iclass 40, count 0 2006.217.07:48:38.20#ibcon#read 6, iclass 40, count 0 2006.217.07:48:38.20#ibcon#end of sib2, iclass 40, count 0 2006.217.07:48:38.20#ibcon#*after write, iclass 40, count 0 2006.217.07:48:38.20#ibcon#*before return 0, iclass 40, count 0 2006.217.07:48:38.20#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.217.07:48:38.20#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.217.07:48:38.20#ibcon#about to clear, iclass 40 cls_cnt 0 2006.217.07:48:38.20#ibcon#cleared, iclass 40 cls_cnt 0 2006.217.07:48:38.20$vc4f8/valo=2,572.99 2006.217.07:48:38.20#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.217.07:48:38.20#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.217.07:48:38.20#ibcon#ireg 17 cls_cnt 0 2006.217.07:48:38.20#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.217.07:48:38.20#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.217.07:48:38.20#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.217.07:48:38.20#ibcon#enter wrdev, iclass 4, count 0 2006.217.07:48:38.20#ibcon#first serial, iclass 4, count 0 2006.217.07:48:38.20#ibcon#enter sib2, iclass 4, count 0 2006.217.07:48:38.20#ibcon#flushed, iclass 4, count 0 2006.217.07:48:38.20#ibcon#about to write, iclass 4, count 0 2006.217.07:48:38.20#ibcon#wrote, iclass 4, count 0 2006.217.07:48:38.20#ibcon#about to read 3, iclass 4, count 0 2006.217.07:48:38.23#ibcon#read 3, iclass 4, count 0 2006.217.07:48:38.23#ibcon#about to read 4, iclass 4, count 0 2006.217.07:48:38.23#ibcon#read 4, iclass 4, count 0 2006.217.07:48:38.23#ibcon#about to read 5, iclass 4, count 0 2006.217.07:48:38.23#ibcon#read 5, iclass 4, count 0 2006.217.07:48:38.23#ibcon#about to read 6, iclass 4, count 0 2006.217.07:48:38.23#ibcon#read 6, iclass 4, count 0 2006.217.07:48:38.23#ibcon#end of sib2, iclass 4, count 0 2006.217.07:48:38.23#ibcon#*mode == 0, iclass 4, count 0 2006.217.07:48:38.23#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.217.07:48:38.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.217.07:48:38.23#ibcon#*before write, iclass 4, count 0 2006.217.07:48:38.23#ibcon#enter sib2, iclass 4, count 0 2006.217.07:48:38.23#ibcon#flushed, iclass 4, count 0 2006.217.07:48:38.23#ibcon#about to write, iclass 4, count 0 2006.217.07:48:38.23#ibcon#wrote, iclass 4, count 0 2006.217.07:48:38.23#ibcon#about to read 3, iclass 4, count 0 2006.217.07:48:38.27#ibcon#read 3, iclass 4, count 0 2006.217.07:48:38.27#ibcon#about to read 4, iclass 4, count 0 2006.217.07:48:38.27#ibcon#read 4, iclass 4, count 0 2006.217.07:48:38.27#ibcon#about to read 5, iclass 4, count 0 2006.217.07:48:38.27#ibcon#read 5, iclass 4, count 0 2006.217.07:48:38.27#ibcon#about to read 6, iclass 4, count 0 2006.217.07:48:38.27#ibcon#read 6, iclass 4, count 0 2006.217.07:48:38.27#ibcon#end of sib2, iclass 4, count 0 2006.217.07:48:38.27#ibcon#*after write, iclass 4, count 0 2006.217.07:48:38.27#ibcon#*before return 0, iclass 4, count 0 2006.217.07:48:38.27#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.217.07:48:38.27#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.217.07:48:38.27#ibcon#about to clear, iclass 4 cls_cnt 0 2006.217.07:48:38.27#ibcon#cleared, iclass 4 cls_cnt 0 2006.217.07:48:38.27$vc4f8/va=2,4 2006.217.07:48:38.27#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.217.07:48:38.27#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.217.07:48:38.27#ibcon#ireg 11 cls_cnt 2 2006.217.07:48:38.27#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.217.07:48:38.32#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.217.07:48:38.32#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.217.07:48:38.32#ibcon#enter wrdev, iclass 6, count 2 2006.217.07:48:38.32#ibcon#first serial, iclass 6, count 2 2006.217.07:48:38.32#ibcon#enter sib2, iclass 6, count 2 2006.217.07:48:38.32#ibcon#flushed, iclass 6, count 2 2006.217.07:48:38.32#ibcon#about to write, iclass 6, count 2 2006.217.07:48:38.32#ibcon#wrote, iclass 6, count 2 2006.217.07:48:38.32#ibcon#about to read 3, iclass 6, count 2 2006.217.07:48:38.34#ibcon#read 3, iclass 6, count 2 2006.217.07:48:38.34#ibcon#about to read 4, iclass 6, count 2 2006.217.07:48:38.34#ibcon#read 4, iclass 6, count 2 2006.217.07:48:38.34#ibcon#about to read 5, iclass 6, count 2 2006.217.07:48:38.34#ibcon#read 5, iclass 6, count 2 2006.217.07:48:38.34#ibcon#about to read 6, iclass 6, count 2 2006.217.07:48:38.34#ibcon#read 6, iclass 6, count 2 2006.217.07:48:38.34#ibcon#end of sib2, iclass 6, count 2 2006.217.07:48:38.34#ibcon#*mode == 0, iclass 6, count 2 2006.217.07:48:38.34#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.217.07:48:38.34#ibcon#[25=AT02-04\r\n] 2006.217.07:48:38.34#ibcon#*before write, iclass 6, count 2 2006.217.07:48:38.34#ibcon#enter sib2, iclass 6, count 2 2006.217.07:48:38.34#ibcon#flushed, iclass 6, count 2 2006.217.07:48:38.34#ibcon#about to write, iclass 6, count 2 2006.217.07:48:38.34#ibcon#wrote, iclass 6, count 2 2006.217.07:48:38.34#ibcon#about to read 3, iclass 6, count 2 2006.217.07:48:38.37#ibcon#read 3, iclass 6, count 2 2006.217.07:48:38.37#ibcon#about to read 4, iclass 6, count 2 2006.217.07:48:38.37#ibcon#read 4, iclass 6, count 2 2006.217.07:48:38.37#ibcon#about to read 5, iclass 6, count 2 2006.217.07:48:38.37#ibcon#read 5, iclass 6, count 2 2006.217.07:48:38.37#ibcon#about to read 6, iclass 6, count 2 2006.217.07:48:38.37#ibcon#read 6, iclass 6, count 2 2006.217.07:48:38.37#ibcon#end of sib2, iclass 6, count 2 2006.217.07:48:38.37#ibcon#*after write, iclass 6, count 2 2006.217.07:48:38.37#ibcon#*before return 0, iclass 6, count 2 2006.217.07:48:38.37#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.217.07:48:38.37#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.217.07:48:38.37#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.217.07:48:38.37#ibcon#ireg 7 cls_cnt 0 2006.217.07:48:38.37#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.217.07:48:38.49#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.217.07:48:38.49#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.217.07:48:38.49#ibcon#enter wrdev, iclass 6, count 0 2006.217.07:48:38.49#ibcon#first serial, iclass 6, count 0 2006.217.07:48:38.49#ibcon#enter sib2, iclass 6, count 0 2006.217.07:48:38.49#ibcon#flushed, iclass 6, count 0 2006.217.07:48:38.49#ibcon#about to write, iclass 6, count 0 2006.217.07:48:38.49#ibcon#wrote, iclass 6, count 0 2006.217.07:48:38.49#ibcon#about to read 3, iclass 6, count 0 2006.217.07:48:38.51#ibcon#read 3, iclass 6, count 0 2006.217.07:48:38.51#ibcon#about to read 4, iclass 6, count 0 2006.217.07:48:38.51#ibcon#read 4, iclass 6, count 0 2006.217.07:48:38.51#ibcon#about to read 5, iclass 6, count 0 2006.217.07:48:38.51#ibcon#read 5, iclass 6, count 0 2006.217.07:48:38.51#ibcon#about to read 6, iclass 6, count 0 2006.217.07:48:38.51#ibcon#read 6, iclass 6, count 0 2006.217.07:48:38.51#ibcon#end of sib2, iclass 6, count 0 2006.217.07:48:38.51#ibcon#*mode == 0, iclass 6, count 0 2006.217.07:48:38.51#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.217.07:48:38.51#ibcon#[25=USB\r\n] 2006.217.07:48:38.51#ibcon#*before write, iclass 6, count 0 2006.217.07:48:38.51#ibcon#enter sib2, iclass 6, count 0 2006.217.07:48:38.51#ibcon#flushed, iclass 6, count 0 2006.217.07:48:38.51#ibcon#about to write, iclass 6, count 0 2006.217.07:48:38.51#ibcon#wrote, iclass 6, count 0 2006.217.07:48:38.51#ibcon#about to read 3, iclass 6, count 0 2006.217.07:48:38.54#ibcon#read 3, iclass 6, count 0 2006.217.07:48:38.54#ibcon#about to read 4, iclass 6, count 0 2006.217.07:48:38.54#ibcon#read 4, iclass 6, count 0 2006.217.07:48:38.54#ibcon#about to read 5, iclass 6, count 0 2006.217.07:48:38.54#ibcon#read 5, iclass 6, count 0 2006.217.07:48:38.54#ibcon#about to read 6, iclass 6, count 0 2006.217.07:48:38.54#ibcon#read 6, iclass 6, count 0 2006.217.07:48:38.54#ibcon#end of sib2, iclass 6, count 0 2006.217.07:48:38.54#ibcon#*after write, iclass 6, count 0 2006.217.07:48:38.54#ibcon#*before return 0, iclass 6, count 0 2006.217.07:48:38.54#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.217.07:48:38.54#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.217.07:48:38.54#ibcon#about to clear, iclass 6 cls_cnt 0 2006.217.07:48:38.54#ibcon#cleared, iclass 6 cls_cnt 0 2006.217.07:48:38.54$vc4f8/valo=3,672.99 2006.217.07:48:38.54#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.217.07:48:38.54#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.217.07:48:38.54#ibcon#ireg 17 cls_cnt 0 2006.217.07:48:38.54#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.217.07:48:38.54#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.217.07:48:38.54#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.217.07:48:38.54#ibcon#enter wrdev, iclass 10, count 0 2006.217.07:48:38.54#ibcon#first serial, iclass 10, count 0 2006.217.07:48:38.54#ibcon#enter sib2, iclass 10, count 0 2006.217.07:48:38.54#ibcon#flushed, iclass 10, count 0 2006.217.07:48:38.54#ibcon#about to write, iclass 10, count 0 2006.217.07:48:38.54#ibcon#wrote, iclass 10, count 0 2006.217.07:48:38.54#ibcon#about to read 3, iclass 10, count 0 2006.217.07:48:38.57#ibcon#read 3, iclass 10, count 0 2006.217.07:48:38.57#ibcon#about to read 4, iclass 10, count 0 2006.217.07:48:38.57#ibcon#read 4, iclass 10, count 0 2006.217.07:48:38.57#ibcon#about to read 5, iclass 10, count 0 2006.217.07:48:38.57#ibcon#read 5, iclass 10, count 0 2006.217.07:48:38.57#ibcon#about to read 6, iclass 10, count 0 2006.217.07:48:38.57#ibcon#read 6, iclass 10, count 0 2006.217.07:48:38.57#ibcon#end of sib2, iclass 10, count 0 2006.217.07:48:38.57#ibcon#*mode == 0, iclass 10, count 0 2006.217.07:48:38.57#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.217.07:48:38.57#ibcon#[26=FRQ=03,672.99\r\n] 2006.217.07:48:38.57#ibcon#*before write, iclass 10, count 0 2006.217.07:48:38.57#ibcon#enter sib2, iclass 10, count 0 2006.217.07:48:38.57#ibcon#flushed, iclass 10, count 0 2006.217.07:48:38.57#ibcon#about to write, iclass 10, count 0 2006.217.07:48:38.57#ibcon#wrote, iclass 10, count 0 2006.217.07:48:38.57#ibcon#about to read 3, iclass 10, count 0 2006.217.07:48:38.61#ibcon#read 3, iclass 10, count 0 2006.217.07:48:38.61#ibcon#about to read 4, iclass 10, count 0 2006.217.07:48:38.61#ibcon#read 4, iclass 10, count 0 2006.217.07:48:38.61#ibcon#about to read 5, iclass 10, count 0 2006.217.07:48:38.61#ibcon#read 5, iclass 10, count 0 2006.217.07:48:38.61#ibcon#about to read 6, iclass 10, count 0 2006.217.07:48:38.61#ibcon#read 6, iclass 10, count 0 2006.217.07:48:38.61#ibcon#end of sib2, iclass 10, count 0 2006.217.07:48:38.61#ibcon#*after write, iclass 10, count 0 2006.217.07:48:38.61#ibcon#*before return 0, iclass 10, count 0 2006.217.07:48:38.61#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.217.07:48:38.61#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.217.07:48:38.61#ibcon#about to clear, iclass 10 cls_cnt 0 2006.217.07:48:38.61#ibcon#cleared, iclass 10 cls_cnt 0 2006.217.07:48:38.61$vc4f8/va=3,4 2006.217.07:48:38.61#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.217.07:48:38.61#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.217.07:48:38.61#ibcon#ireg 11 cls_cnt 2 2006.217.07:48:38.61#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.217.07:48:38.66#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.217.07:48:38.66#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.217.07:48:38.66#ibcon#enter wrdev, iclass 12, count 2 2006.217.07:48:38.66#ibcon#first serial, iclass 12, count 2 2006.217.07:48:38.66#ibcon#enter sib2, iclass 12, count 2 2006.217.07:48:38.66#ibcon#flushed, iclass 12, count 2 2006.217.07:48:38.66#ibcon#about to write, iclass 12, count 2 2006.217.07:48:38.66#ibcon#wrote, iclass 12, count 2 2006.217.07:48:38.66#ibcon#about to read 3, iclass 12, count 2 2006.217.07:48:38.68#ibcon#read 3, iclass 12, count 2 2006.217.07:48:38.68#ibcon#about to read 4, iclass 12, count 2 2006.217.07:48:38.68#ibcon#read 4, iclass 12, count 2 2006.217.07:48:38.68#ibcon#about to read 5, iclass 12, count 2 2006.217.07:48:38.68#ibcon#read 5, iclass 12, count 2 2006.217.07:48:38.68#ibcon#about to read 6, iclass 12, count 2 2006.217.07:48:38.68#ibcon#read 6, iclass 12, count 2 2006.217.07:48:38.68#ibcon#end of sib2, iclass 12, count 2 2006.217.07:48:38.68#ibcon#*mode == 0, iclass 12, count 2 2006.217.07:48:38.68#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.217.07:48:38.68#ibcon#[25=AT03-04\r\n] 2006.217.07:48:38.68#ibcon#*before write, iclass 12, count 2 2006.217.07:48:38.68#ibcon#enter sib2, iclass 12, count 2 2006.217.07:48:38.68#ibcon#flushed, iclass 12, count 2 2006.217.07:48:38.68#ibcon#about to write, iclass 12, count 2 2006.217.07:48:38.68#ibcon#wrote, iclass 12, count 2 2006.217.07:48:38.68#ibcon#about to read 3, iclass 12, count 2 2006.217.07:48:38.71#ibcon#read 3, iclass 12, count 2 2006.217.07:48:38.71#ibcon#about to read 4, iclass 12, count 2 2006.217.07:48:38.71#ibcon#read 4, iclass 12, count 2 2006.217.07:48:38.71#ibcon#about to read 5, iclass 12, count 2 2006.217.07:48:38.71#ibcon#read 5, iclass 12, count 2 2006.217.07:48:38.71#ibcon#about to read 6, iclass 12, count 2 2006.217.07:48:38.71#ibcon#read 6, iclass 12, count 2 2006.217.07:48:38.71#ibcon#end of sib2, iclass 12, count 2 2006.217.07:48:38.71#ibcon#*after write, iclass 12, count 2 2006.217.07:48:38.71#ibcon#*before return 0, iclass 12, count 2 2006.217.07:48:38.71#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.217.07:48:38.71#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.217.07:48:38.71#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.217.07:48:38.71#ibcon#ireg 7 cls_cnt 0 2006.217.07:48:38.71#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.217.07:48:38.83#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.217.07:48:38.83#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.217.07:48:38.83#ibcon#enter wrdev, iclass 12, count 0 2006.217.07:48:38.83#ibcon#first serial, iclass 12, count 0 2006.217.07:48:38.83#ibcon#enter sib2, iclass 12, count 0 2006.217.07:48:38.83#ibcon#flushed, iclass 12, count 0 2006.217.07:48:38.83#ibcon#about to write, iclass 12, count 0 2006.217.07:48:38.83#ibcon#wrote, iclass 12, count 0 2006.217.07:48:38.83#ibcon#about to read 3, iclass 12, count 0 2006.217.07:48:38.85#ibcon#read 3, iclass 12, count 0 2006.217.07:48:38.85#ibcon#about to read 4, iclass 12, count 0 2006.217.07:48:38.85#ibcon#read 4, iclass 12, count 0 2006.217.07:48:38.85#ibcon#about to read 5, iclass 12, count 0 2006.217.07:48:38.85#ibcon#read 5, iclass 12, count 0 2006.217.07:48:38.85#ibcon#about to read 6, iclass 12, count 0 2006.217.07:48:38.85#ibcon#read 6, iclass 12, count 0 2006.217.07:48:38.85#ibcon#end of sib2, iclass 12, count 0 2006.217.07:48:38.85#ibcon#*mode == 0, iclass 12, count 0 2006.217.07:48:38.85#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.217.07:48:38.85#ibcon#[25=USB\r\n] 2006.217.07:48:38.85#ibcon#*before write, iclass 12, count 0 2006.217.07:48:38.85#ibcon#enter sib2, iclass 12, count 0 2006.217.07:48:38.85#ibcon#flushed, iclass 12, count 0 2006.217.07:48:38.85#ibcon#about to write, iclass 12, count 0 2006.217.07:48:38.85#ibcon#wrote, iclass 12, count 0 2006.217.07:48:38.85#ibcon#about to read 3, iclass 12, count 0 2006.217.07:48:38.88#ibcon#read 3, iclass 12, count 0 2006.217.07:48:38.88#ibcon#about to read 4, iclass 12, count 0 2006.217.07:48:38.88#ibcon#read 4, iclass 12, count 0 2006.217.07:48:38.88#ibcon#about to read 5, iclass 12, count 0 2006.217.07:48:38.88#ibcon#read 5, iclass 12, count 0 2006.217.07:48:38.88#ibcon#about to read 6, iclass 12, count 0 2006.217.07:48:38.88#ibcon#read 6, iclass 12, count 0 2006.217.07:48:38.88#ibcon#end of sib2, iclass 12, count 0 2006.217.07:48:38.88#ibcon#*after write, iclass 12, count 0 2006.217.07:48:38.88#ibcon#*before return 0, iclass 12, count 0 2006.217.07:48:38.88#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.217.07:48:38.88#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.217.07:48:38.88#ibcon#about to clear, iclass 12 cls_cnt 0 2006.217.07:48:38.88#ibcon#cleared, iclass 12 cls_cnt 0 2006.217.07:48:38.88$vc4f8/valo=4,832.99 2006.217.07:48:38.88#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.217.07:48:38.88#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.217.07:48:38.88#ibcon#ireg 17 cls_cnt 0 2006.217.07:48:38.88#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.217.07:48:38.88#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.217.07:48:38.88#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.217.07:48:38.88#ibcon#enter wrdev, iclass 14, count 0 2006.217.07:48:38.88#ibcon#first serial, iclass 14, count 0 2006.217.07:48:38.88#ibcon#enter sib2, iclass 14, count 0 2006.217.07:48:38.88#ibcon#flushed, iclass 14, count 0 2006.217.07:48:38.88#ibcon#about to write, iclass 14, count 0 2006.217.07:48:38.88#ibcon#wrote, iclass 14, count 0 2006.217.07:48:38.88#ibcon#about to read 3, iclass 14, count 0 2006.217.07:48:38.91#ibcon#read 3, iclass 14, count 0 2006.217.07:48:38.91#ibcon#about to read 4, iclass 14, count 0 2006.217.07:48:38.91#ibcon#read 4, iclass 14, count 0 2006.217.07:48:38.91#ibcon#about to read 5, iclass 14, count 0 2006.217.07:48:38.91#ibcon#read 5, iclass 14, count 0 2006.217.07:48:38.91#ibcon#about to read 6, iclass 14, count 0 2006.217.07:48:38.91#ibcon#read 6, iclass 14, count 0 2006.217.07:48:38.91#ibcon#end of sib2, iclass 14, count 0 2006.217.07:48:38.91#ibcon#*mode == 0, iclass 14, count 0 2006.217.07:48:38.91#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.217.07:48:38.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.217.07:48:38.91#ibcon#*before write, iclass 14, count 0 2006.217.07:48:38.91#ibcon#enter sib2, iclass 14, count 0 2006.217.07:48:38.91#ibcon#flushed, iclass 14, count 0 2006.217.07:48:38.91#ibcon#about to write, iclass 14, count 0 2006.217.07:48:38.91#ibcon#wrote, iclass 14, count 0 2006.217.07:48:38.91#ibcon#about to read 3, iclass 14, count 0 2006.217.07:48:38.95#ibcon#read 3, iclass 14, count 0 2006.217.07:48:38.95#ibcon#about to read 4, iclass 14, count 0 2006.217.07:48:38.95#ibcon#read 4, iclass 14, count 0 2006.217.07:48:38.95#ibcon#about to read 5, iclass 14, count 0 2006.217.07:48:38.95#ibcon#read 5, iclass 14, count 0 2006.217.07:48:38.95#ibcon#about to read 6, iclass 14, count 0 2006.217.07:48:38.95#ibcon#read 6, iclass 14, count 0 2006.217.07:48:38.95#ibcon#end of sib2, iclass 14, count 0 2006.217.07:48:38.95#ibcon#*after write, iclass 14, count 0 2006.217.07:48:38.95#ibcon#*before return 0, iclass 14, count 0 2006.217.07:48:38.95#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.217.07:48:38.95#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.217.07:48:38.95#ibcon#about to clear, iclass 14 cls_cnt 0 2006.217.07:48:38.95#ibcon#cleared, iclass 14 cls_cnt 0 2006.217.07:48:38.95$vc4f8/va=4,4 2006.217.07:48:38.95#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.217.07:48:38.95#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.217.07:48:38.95#ibcon#ireg 11 cls_cnt 2 2006.217.07:48:38.95#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.217.07:48:39.00#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.217.07:48:39.00#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.217.07:48:39.00#ibcon#enter wrdev, iclass 16, count 2 2006.217.07:48:39.00#ibcon#first serial, iclass 16, count 2 2006.217.07:48:39.00#ibcon#enter sib2, iclass 16, count 2 2006.217.07:48:39.00#ibcon#flushed, iclass 16, count 2 2006.217.07:48:39.00#ibcon#about to write, iclass 16, count 2 2006.217.07:48:39.00#ibcon#wrote, iclass 16, count 2 2006.217.07:48:39.00#ibcon#about to read 3, iclass 16, count 2 2006.217.07:48:39.02#ibcon#read 3, iclass 16, count 2 2006.217.07:48:39.02#ibcon#about to read 4, iclass 16, count 2 2006.217.07:48:39.02#ibcon#read 4, iclass 16, count 2 2006.217.07:48:39.02#ibcon#about to read 5, iclass 16, count 2 2006.217.07:48:39.02#ibcon#read 5, iclass 16, count 2 2006.217.07:48:39.02#ibcon#about to read 6, iclass 16, count 2 2006.217.07:48:39.02#ibcon#read 6, iclass 16, count 2 2006.217.07:48:39.02#ibcon#end of sib2, iclass 16, count 2 2006.217.07:48:39.02#ibcon#*mode == 0, iclass 16, count 2 2006.217.07:48:39.02#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.217.07:48:39.02#ibcon#[25=AT04-04\r\n] 2006.217.07:48:39.02#ibcon#*before write, iclass 16, count 2 2006.217.07:48:39.02#ibcon#enter sib2, iclass 16, count 2 2006.217.07:48:39.02#ibcon#flushed, iclass 16, count 2 2006.217.07:48:39.02#ibcon#about to write, iclass 16, count 2 2006.217.07:48:39.02#ibcon#wrote, iclass 16, count 2 2006.217.07:48:39.02#ibcon#about to read 3, iclass 16, count 2 2006.217.07:48:39.05#ibcon#read 3, iclass 16, count 2 2006.217.07:48:39.05#ibcon#about to read 4, iclass 16, count 2 2006.217.07:48:39.05#ibcon#read 4, iclass 16, count 2 2006.217.07:48:39.05#ibcon#about to read 5, iclass 16, count 2 2006.217.07:48:39.05#ibcon#read 5, iclass 16, count 2 2006.217.07:48:39.05#ibcon#about to read 6, iclass 16, count 2 2006.217.07:48:39.05#ibcon#read 6, iclass 16, count 2 2006.217.07:48:39.05#ibcon#end of sib2, iclass 16, count 2 2006.217.07:48:39.05#ibcon#*after write, iclass 16, count 2 2006.217.07:48:39.05#ibcon#*before return 0, iclass 16, count 2 2006.217.07:48:39.05#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.217.07:48:39.05#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.217.07:48:39.05#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.217.07:48:39.05#ibcon#ireg 7 cls_cnt 0 2006.217.07:48:39.05#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.217.07:48:39.17#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.217.07:48:39.17#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.217.07:48:39.17#ibcon#enter wrdev, iclass 16, count 0 2006.217.07:48:39.17#ibcon#first serial, iclass 16, count 0 2006.217.07:48:39.17#ibcon#enter sib2, iclass 16, count 0 2006.217.07:48:39.17#ibcon#flushed, iclass 16, count 0 2006.217.07:48:39.17#ibcon#about to write, iclass 16, count 0 2006.217.07:48:39.17#ibcon#wrote, iclass 16, count 0 2006.217.07:48:39.17#ibcon#about to read 3, iclass 16, count 0 2006.217.07:48:39.19#ibcon#read 3, iclass 16, count 0 2006.217.07:48:39.19#ibcon#about to read 4, iclass 16, count 0 2006.217.07:48:39.19#ibcon#read 4, iclass 16, count 0 2006.217.07:48:39.19#ibcon#about to read 5, iclass 16, count 0 2006.217.07:48:39.19#ibcon#read 5, iclass 16, count 0 2006.217.07:48:39.19#ibcon#about to read 6, iclass 16, count 0 2006.217.07:48:39.19#ibcon#read 6, iclass 16, count 0 2006.217.07:48:39.19#ibcon#end of sib2, iclass 16, count 0 2006.217.07:48:39.19#ibcon#*mode == 0, iclass 16, count 0 2006.217.07:48:39.19#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.217.07:48:39.19#ibcon#[25=USB\r\n] 2006.217.07:48:39.19#ibcon#*before write, iclass 16, count 0 2006.217.07:48:39.19#ibcon#enter sib2, iclass 16, count 0 2006.217.07:48:39.19#ibcon#flushed, iclass 16, count 0 2006.217.07:48:39.19#ibcon#about to write, iclass 16, count 0 2006.217.07:48:39.19#ibcon#wrote, iclass 16, count 0 2006.217.07:48:39.19#ibcon#about to read 3, iclass 16, count 0 2006.217.07:48:39.22#ibcon#read 3, iclass 16, count 0 2006.217.07:48:39.22#ibcon#about to read 4, iclass 16, count 0 2006.217.07:48:39.22#ibcon#read 4, iclass 16, count 0 2006.217.07:48:39.22#ibcon#about to read 5, iclass 16, count 0 2006.217.07:48:39.22#ibcon#read 5, iclass 16, count 0 2006.217.07:48:39.22#ibcon#about to read 6, iclass 16, count 0 2006.217.07:48:39.22#ibcon#read 6, iclass 16, count 0 2006.217.07:48:39.22#ibcon#end of sib2, iclass 16, count 0 2006.217.07:48:39.22#ibcon#*after write, iclass 16, count 0 2006.217.07:48:39.22#ibcon#*before return 0, iclass 16, count 0 2006.217.07:48:39.22#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.217.07:48:39.22#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.217.07:48:39.22#ibcon#about to clear, iclass 16 cls_cnt 0 2006.217.07:48:39.22#ibcon#cleared, iclass 16 cls_cnt 0 2006.217.07:48:39.22$vc4f8/valo=5,652.99 2006.217.07:48:39.22#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.217.07:48:39.22#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.217.07:48:39.22#ibcon#ireg 17 cls_cnt 0 2006.217.07:48:39.22#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.217.07:48:39.22#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.217.07:48:39.22#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.217.07:48:39.22#ibcon#enter wrdev, iclass 18, count 0 2006.217.07:48:39.22#ibcon#first serial, iclass 18, count 0 2006.217.07:48:39.22#ibcon#enter sib2, iclass 18, count 0 2006.217.07:48:39.22#ibcon#flushed, iclass 18, count 0 2006.217.07:48:39.22#ibcon#about to write, iclass 18, count 0 2006.217.07:48:39.22#ibcon#wrote, iclass 18, count 0 2006.217.07:48:39.22#ibcon#about to read 3, iclass 18, count 0 2006.217.07:48:39.24#ibcon#read 3, iclass 18, count 0 2006.217.07:48:39.24#ibcon#about to read 4, iclass 18, count 0 2006.217.07:48:39.24#ibcon#read 4, iclass 18, count 0 2006.217.07:48:39.24#ibcon#about to read 5, iclass 18, count 0 2006.217.07:48:39.24#ibcon#read 5, iclass 18, count 0 2006.217.07:48:39.24#ibcon#about to read 6, iclass 18, count 0 2006.217.07:48:39.24#ibcon#read 6, iclass 18, count 0 2006.217.07:48:39.24#ibcon#end of sib2, iclass 18, count 0 2006.217.07:48:39.24#ibcon#*mode == 0, iclass 18, count 0 2006.217.07:48:39.24#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.217.07:48:39.24#ibcon#[26=FRQ=05,652.99\r\n] 2006.217.07:48:39.24#ibcon#*before write, iclass 18, count 0 2006.217.07:48:39.24#ibcon#enter sib2, iclass 18, count 0 2006.217.07:48:39.24#ibcon#flushed, iclass 18, count 0 2006.217.07:48:39.24#ibcon#about to write, iclass 18, count 0 2006.217.07:48:39.24#ibcon#wrote, iclass 18, count 0 2006.217.07:48:39.24#ibcon#about to read 3, iclass 18, count 0 2006.217.07:48:39.28#ibcon#read 3, iclass 18, count 0 2006.217.07:48:39.28#ibcon#about to read 4, iclass 18, count 0 2006.217.07:48:39.28#ibcon#read 4, iclass 18, count 0 2006.217.07:48:39.28#ibcon#about to read 5, iclass 18, count 0 2006.217.07:48:39.28#ibcon#read 5, iclass 18, count 0 2006.217.07:48:39.28#ibcon#about to read 6, iclass 18, count 0 2006.217.07:48:39.28#ibcon#read 6, iclass 18, count 0 2006.217.07:48:39.28#ibcon#end of sib2, iclass 18, count 0 2006.217.07:48:39.28#ibcon#*after write, iclass 18, count 0 2006.217.07:48:39.28#ibcon#*before return 0, iclass 18, count 0 2006.217.07:48:39.28#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.217.07:48:39.28#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.217.07:48:39.28#ibcon#about to clear, iclass 18 cls_cnt 0 2006.217.07:48:39.28#ibcon#cleared, iclass 18 cls_cnt 0 2006.217.07:48:39.28$vc4f8/va=5,7 2006.217.07:48:39.28#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.217.07:48:39.28#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.217.07:48:39.28#ibcon#ireg 11 cls_cnt 2 2006.217.07:48:39.28#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.217.07:48:39.34#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.217.07:48:39.34#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.217.07:48:39.34#ibcon#enter wrdev, iclass 20, count 2 2006.217.07:48:39.34#ibcon#first serial, iclass 20, count 2 2006.217.07:48:39.34#ibcon#enter sib2, iclass 20, count 2 2006.217.07:48:39.34#ibcon#flushed, iclass 20, count 2 2006.217.07:48:39.34#ibcon#about to write, iclass 20, count 2 2006.217.07:48:39.34#ibcon#wrote, iclass 20, count 2 2006.217.07:48:39.34#ibcon#about to read 3, iclass 20, count 2 2006.217.07:48:39.36#ibcon#read 3, iclass 20, count 2 2006.217.07:48:39.36#ibcon#about to read 4, iclass 20, count 2 2006.217.07:48:39.36#ibcon#read 4, iclass 20, count 2 2006.217.07:48:39.36#ibcon#about to read 5, iclass 20, count 2 2006.217.07:48:39.36#ibcon#read 5, iclass 20, count 2 2006.217.07:48:39.36#ibcon#about to read 6, iclass 20, count 2 2006.217.07:48:39.36#ibcon#read 6, iclass 20, count 2 2006.217.07:48:39.36#ibcon#end of sib2, iclass 20, count 2 2006.217.07:48:39.36#ibcon#*mode == 0, iclass 20, count 2 2006.217.07:48:39.36#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.217.07:48:39.36#ibcon#[25=AT05-07\r\n] 2006.217.07:48:39.36#ibcon#*before write, iclass 20, count 2 2006.217.07:48:39.36#ibcon#enter sib2, iclass 20, count 2 2006.217.07:48:39.36#ibcon#flushed, iclass 20, count 2 2006.217.07:48:39.36#ibcon#about to write, iclass 20, count 2 2006.217.07:48:39.36#ibcon#wrote, iclass 20, count 2 2006.217.07:48:39.36#ibcon#about to read 3, iclass 20, count 2 2006.217.07:48:39.39#ibcon#read 3, iclass 20, count 2 2006.217.07:48:39.39#ibcon#about to read 4, iclass 20, count 2 2006.217.07:48:39.39#ibcon#read 4, iclass 20, count 2 2006.217.07:48:39.39#ibcon#about to read 5, iclass 20, count 2 2006.217.07:48:39.39#ibcon#read 5, iclass 20, count 2 2006.217.07:48:39.39#ibcon#about to read 6, iclass 20, count 2 2006.217.07:48:39.39#ibcon#read 6, iclass 20, count 2 2006.217.07:48:39.39#ibcon#end of sib2, iclass 20, count 2 2006.217.07:48:39.39#ibcon#*after write, iclass 20, count 2 2006.217.07:48:39.39#ibcon#*before return 0, iclass 20, count 2 2006.217.07:48:39.39#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.217.07:48:39.39#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.217.07:48:39.39#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.217.07:48:39.39#ibcon#ireg 7 cls_cnt 0 2006.217.07:48:39.39#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.217.07:48:39.51#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.217.07:48:39.51#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.217.07:48:39.51#ibcon#enter wrdev, iclass 20, count 0 2006.217.07:48:39.51#ibcon#first serial, iclass 20, count 0 2006.217.07:48:39.51#ibcon#enter sib2, iclass 20, count 0 2006.217.07:48:39.51#ibcon#flushed, iclass 20, count 0 2006.217.07:48:39.51#ibcon#about to write, iclass 20, count 0 2006.217.07:48:39.51#ibcon#wrote, iclass 20, count 0 2006.217.07:48:39.51#ibcon#about to read 3, iclass 20, count 0 2006.217.07:48:39.53#ibcon#read 3, iclass 20, count 0 2006.217.07:48:39.53#ibcon#about to read 4, iclass 20, count 0 2006.217.07:48:39.53#ibcon#read 4, iclass 20, count 0 2006.217.07:48:39.53#ibcon#about to read 5, iclass 20, count 0 2006.217.07:48:39.53#ibcon#read 5, iclass 20, count 0 2006.217.07:48:39.53#ibcon#about to read 6, iclass 20, count 0 2006.217.07:48:39.53#ibcon#read 6, iclass 20, count 0 2006.217.07:48:39.53#ibcon#end of sib2, iclass 20, count 0 2006.217.07:48:39.53#ibcon#*mode == 0, iclass 20, count 0 2006.217.07:48:39.53#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.217.07:48:39.53#ibcon#[25=USB\r\n] 2006.217.07:48:39.53#ibcon#*before write, iclass 20, count 0 2006.217.07:48:39.53#ibcon#enter sib2, iclass 20, count 0 2006.217.07:48:39.53#ibcon#flushed, iclass 20, count 0 2006.217.07:48:39.53#ibcon#about to write, iclass 20, count 0 2006.217.07:48:39.53#ibcon#wrote, iclass 20, count 0 2006.217.07:48:39.53#ibcon#about to read 3, iclass 20, count 0 2006.217.07:48:39.56#ibcon#read 3, iclass 20, count 0 2006.217.07:48:39.56#ibcon#about to read 4, iclass 20, count 0 2006.217.07:48:39.56#ibcon#read 4, iclass 20, count 0 2006.217.07:48:39.56#ibcon#about to read 5, iclass 20, count 0 2006.217.07:48:39.56#ibcon#read 5, iclass 20, count 0 2006.217.07:48:39.56#ibcon#about to read 6, iclass 20, count 0 2006.217.07:48:39.56#ibcon#read 6, iclass 20, count 0 2006.217.07:48:39.56#ibcon#end of sib2, iclass 20, count 0 2006.217.07:48:39.56#ibcon#*after write, iclass 20, count 0 2006.217.07:48:39.56#ibcon#*before return 0, iclass 20, count 0 2006.217.07:48:39.56#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.217.07:48:39.56#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.217.07:48:39.56#ibcon#about to clear, iclass 20 cls_cnt 0 2006.217.07:48:39.56#ibcon#cleared, iclass 20 cls_cnt 0 2006.217.07:48:39.56$vc4f8/valo=6,772.99 2006.217.07:48:39.56#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.217.07:48:39.56#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.217.07:48:39.56#ibcon#ireg 17 cls_cnt 0 2006.217.07:48:39.56#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.217.07:48:39.56#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.217.07:48:39.56#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.217.07:48:39.56#ibcon#enter wrdev, iclass 22, count 0 2006.217.07:48:39.56#ibcon#first serial, iclass 22, count 0 2006.217.07:48:39.56#ibcon#enter sib2, iclass 22, count 0 2006.217.07:48:39.56#ibcon#flushed, iclass 22, count 0 2006.217.07:48:39.56#ibcon#about to write, iclass 22, count 0 2006.217.07:48:39.56#ibcon#wrote, iclass 22, count 0 2006.217.07:48:39.56#ibcon#about to read 3, iclass 22, count 0 2006.217.07:48:39.58#ibcon#read 3, iclass 22, count 0 2006.217.07:48:39.58#ibcon#about to read 4, iclass 22, count 0 2006.217.07:48:39.58#ibcon#read 4, iclass 22, count 0 2006.217.07:48:39.58#ibcon#about to read 5, iclass 22, count 0 2006.217.07:48:39.58#ibcon#read 5, iclass 22, count 0 2006.217.07:48:39.58#ibcon#about to read 6, iclass 22, count 0 2006.217.07:48:39.58#ibcon#read 6, iclass 22, count 0 2006.217.07:48:39.58#ibcon#end of sib2, iclass 22, count 0 2006.217.07:48:39.58#ibcon#*mode == 0, iclass 22, count 0 2006.217.07:48:39.58#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.217.07:48:39.58#ibcon#[26=FRQ=06,772.99\r\n] 2006.217.07:48:39.58#ibcon#*before write, iclass 22, count 0 2006.217.07:48:39.58#ibcon#enter sib2, iclass 22, count 0 2006.217.07:48:39.58#ibcon#flushed, iclass 22, count 0 2006.217.07:48:39.58#ibcon#about to write, iclass 22, count 0 2006.217.07:48:39.58#ibcon#wrote, iclass 22, count 0 2006.217.07:48:39.58#ibcon#about to read 3, iclass 22, count 0 2006.217.07:48:39.62#ibcon#read 3, iclass 22, count 0 2006.217.07:48:39.62#ibcon#about to read 4, iclass 22, count 0 2006.217.07:48:39.62#ibcon#read 4, iclass 22, count 0 2006.217.07:48:39.62#ibcon#about to read 5, iclass 22, count 0 2006.217.07:48:39.62#ibcon#read 5, iclass 22, count 0 2006.217.07:48:39.62#ibcon#about to read 6, iclass 22, count 0 2006.217.07:48:39.62#ibcon#read 6, iclass 22, count 0 2006.217.07:48:39.62#ibcon#end of sib2, iclass 22, count 0 2006.217.07:48:39.62#ibcon#*after write, iclass 22, count 0 2006.217.07:48:39.62#ibcon#*before return 0, iclass 22, count 0 2006.217.07:48:39.62#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.217.07:48:39.62#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.217.07:48:39.62#ibcon#about to clear, iclass 22 cls_cnt 0 2006.217.07:48:39.62#ibcon#cleared, iclass 22 cls_cnt 0 2006.217.07:48:39.62$vc4f8/va=6,6 2006.217.07:48:39.62#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.217.07:48:39.62#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.217.07:48:39.62#ibcon#ireg 11 cls_cnt 2 2006.217.07:48:39.62#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.217.07:48:39.68#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.217.07:48:39.68#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.217.07:48:39.68#ibcon#enter wrdev, iclass 24, count 2 2006.217.07:48:39.68#ibcon#first serial, iclass 24, count 2 2006.217.07:48:39.68#ibcon#enter sib2, iclass 24, count 2 2006.217.07:48:39.68#ibcon#flushed, iclass 24, count 2 2006.217.07:48:39.68#ibcon#about to write, iclass 24, count 2 2006.217.07:48:39.68#ibcon#wrote, iclass 24, count 2 2006.217.07:48:39.68#ibcon#about to read 3, iclass 24, count 2 2006.217.07:48:39.70#ibcon#read 3, iclass 24, count 2 2006.217.07:48:39.70#ibcon#about to read 4, iclass 24, count 2 2006.217.07:48:39.70#ibcon#read 4, iclass 24, count 2 2006.217.07:48:39.70#ibcon#about to read 5, iclass 24, count 2 2006.217.07:48:39.70#ibcon#read 5, iclass 24, count 2 2006.217.07:48:39.70#ibcon#about to read 6, iclass 24, count 2 2006.217.07:48:39.70#ibcon#read 6, iclass 24, count 2 2006.217.07:48:39.70#ibcon#end of sib2, iclass 24, count 2 2006.217.07:48:39.70#ibcon#*mode == 0, iclass 24, count 2 2006.217.07:48:39.70#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.217.07:48:39.70#ibcon#[25=AT06-06\r\n] 2006.217.07:48:39.70#ibcon#*before write, iclass 24, count 2 2006.217.07:48:39.70#ibcon#enter sib2, iclass 24, count 2 2006.217.07:48:39.70#ibcon#flushed, iclass 24, count 2 2006.217.07:48:39.70#ibcon#about to write, iclass 24, count 2 2006.217.07:48:39.70#ibcon#wrote, iclass 24, count 2 2006.217.07:48:39.70#ibcon#about to read 3, iclass 24, count 2 2006.217.07:48:39.73#ibcon#read 3, iclass 24, count 2 2006.217.07:48:39.73#ibcon#about to read 4, iclass 24, count 2 2006.217.07:48:39.73#ibcon#read 4, iclass 24, count 2 2006.217.07:48:39.73#ibcon#about to read 5, iclass 24, count 2 2006.217.07:48:39.73#ibcon#read 5, iclass 24, count 2 2006.217.07:48:39.73#ibcon#about to read 6, iclass 24, count 2 2006.217.07:48:39.73#ibcon#read 6, iclass 24, count 2 2006.217.07:48:39.73#ibcon#end of sib2, iclass 24, count 2 2006.217.07:48:39.73#ibcon#*after write, iclass 24, count 2 2006.217.07:48:39.73#ibcon#*before return 0, iclass 24, count 2 2006.217.07:48:39.73#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.217.07:48:39.73#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.217.07:48:39.73#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.217.07:48:39.73#ibcon#ireg 7 cls_cnt 0 2006.217.07:48:39.73#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.217.07:48:39.85#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.217.07:48:39.85#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.217.07:48:39.85#ibcon#enter wrdev, iclass 24, count 0 2006.217.07:48:39.85#ibcon#first serial, iclass 24, count 0 2006.217.07:48:39.85#ibcon#enter sib2, iclass 24, count 0 2006.217.07:48:39.85#ibcon#flushed, iclass 24, count 0 2006.217.07:48:39.85#ibcon#about to write, iclass 24, count 0 2006.217.07:48:39.85#ibcon#wrote, iclass 24, count 0 2006.217.07:48:39.85#ibcon#about to read 3, iclass 24, count 0 2006.217.07:48:39.87#ibcon#read 3, iclass 24, count 0 2006.217.07:48:39.87#ibcon#about to read 4, iclass 24, count 0 2006.217.07:48:39.87#ibcon#read 4, iclass 24, count 0 2006.217.07:48:39.87#ibcon#about to read 5, iclass 24, count 0 2006.217.07:48:39.87#ibcon#read 5, iclass 24, count 0 2006.217.07:48:39.87#ibcon#about to read 6, iclass 24, count 0 2006.217.07:48:39.87#ibcon#read 6, iclass 24, count 0 2006.217.07:48:39.87#ibcon#end of sib2, iclass 24, count 0 2006.217.07:48:39.87#ibcon#*mode == 0, iclass 24, count 0 2006.217.07:48:39.87#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.217.07:48:39.87#ibcon#[25=USB\r\n] 2006.217.07:48:39.87#ibcon#*before write, iclass 24, count 0 2006.217.07:48:39.87#ibcon#enter sib2, iclass 24, count 0 2006.217.07:48:39.87#ibcon#flushed, iclass 24, count 0 2006.217.07:48:39.87#ibcon#about to write, iclass 24, count 0 2006.217.07:48:39.87#ibcon#wrote, iclass 24, count 0 2006.217.07:48:39.87#ibcon#about to read 3, iclass 24, count 0 2006.217.07:48:39.90#ibcon#read 3, iclass 24, count 0 2006.217.07:48:39.90#ibcon#about to read 4, iclass 24, count 0 2006.217.07:48:39.90#ibcon#read 4, iclass 24, count 0 2006.217.07:48:39.90#ibcon#about to read 5, iclass 24, count 0 2006.217.07:48:39.90#ibcon#read 5, iclass 24, count 0 2006.217.07:48:39.90#ibcon#about to read 6, iclass 24, count 0 2006.217.07:48:39.90#ibcon#read 6, iclass 24, count 0 2006.217.07:48:39.90#ibcon#end of sib2, iclass 24, count 0 2006.217.07:48:39.90#ibcon#*after write, iclass 24, count 0 2006.217.07:48:39.90#ibcon#*before return 0, iclass 24, count 0 2006.217.07:48:39.90#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.217.07:48:39.90#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.217.07:48:39.90#ibcon#about to clear, iclass 24 cls_cnt 0 2006.217.07:48:39.90#ibcon#cleared, iclass 24 cls_cnt 0 2006.217.07:48:39.90$vc4f8/valo=7,832.99 2006.217.07:48:39.90#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.217.07:48:39.90#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.217.07:48:39.90#ibcon#ireg 17 cls_cnt 0 2006.217.07:48:39.90#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.217.07:48:39.90#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.217.07:48:39.90#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.217.07:48:39.90#ibcon#enter wrdev, iclass 26, count 0 2006.217.07:48:39.90#ibcon#first serial, iclass 26, count 0 2006.217.07:48:39.90#ibcon#enter sib2, iclass 26, count 0 2006.217.07:48:39.90#ibcon#flushed, iclass 26, count 0 2006.217.07:48:39.90#ibcon#about to write, iclass 26, count 0 2006.217.07:48:39.90#ibcon#wrote, iclass 26, count 0 2006.217.07:48:39.90#ibcon#about to read 3, iclass 26, count 0 2006.217.07:48:39.92#ibcon#read 3, iclass 26, count 0 2006.217.07:48:39.92#ibcon#about to read 4, iclass 26, count 0 2006.217.07:48:39.92#ibcon#read 4, iclass 26, count 0 2006.217.07:48:39.92#ibcon#about to read 5, iclass 26, count 0 2006.217.07:48:39.92#ibcon#read 5, iclass 26, count 0 2006.217.07:48:39.92#ibcon#about to read 6, iclass 26, count 0 2006.217.07:48:39.92#ibcon#read 6, iclass 26, count 0 2006.217.07:48:39.92#ibcon#end of sib2, iclass 26, count 0 2006.217.07:48:39.92#ibcon#*mode == 0, iclass 26, count 0 2006.217.07:48:39.92#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.217.07:48:39.92#ibcon#[26=FRQ=07,832.99\r\n] 2006.217.07:48:39.92#ibcon#*before write, iclass 26, count 0 2006.217.07:48:39.92#ibcon#enter sib2, iclass 26, count 0 2006.217.07:48:39.92#ibcon#flushed, iclass 26, count 0 2006.217.07:48:39.92#ibcon#about to write, iclass 26, count 0 2006.217.07:48:39.92#ibcon#wrote, iclass 26, count 0 2006.217.07:48:39.92#ibcon#about to read 3, iclass 26, count 0 2006.217.07:48:39.96#ibcon#read 3, iclass 26, count 0 2006.217.07:48:39.96#ibcon#about to read 4, iclass 26, count 0 2006.217.07:48:39.96#ibcon#read 4, iclass 26, count 0 2006.217.07:48:39.96#ibcon#about to read 5, iclass 26, count 0 2006.217.07:48:39.96#ibcon#read 5, iclass 26, count 0 2006.217.07:48:39.96#ibcon#about to read 6, iclass 26, count 0 2006.217.07:48:39.96#ibcon#read 6, iclass 26, count 0 2006.217.07:48:39.96#ibcon#end of sib2, iclass 26, count 0 2006.217.07:48:39.96#ibcon#*after write, iclass 26, count 0 2006.217.07:48:39.96#ibcon#*before return 0, iclass 26, count 0 2006.217.07:48:39.96#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.217.07:48:39.96#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.217.07:48:39.96#ibcon#about to clear, iclass 26 cls_cnt 0 2006.217.07:48:39.96#ibcon#cleared, iclass 26 cls_cnt 0 2006.217.07:48:39.96$vc4f8/va=7,6 2006.217.07:48:39.96#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.217.07:48:39.96#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.217.07:48:39.96#ibcon#ireg 11 cls_cnt 2 2006.217.07:48:39.96#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.217.07:48:40.02#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.217.07:48:40.02#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.217.07:48:40.02#ibcon#enter wrdev, iclass 28, count 2 2006.217.07:48:40.02#ibcon#first serial, iclass 28, count 2 2006.217.07:48:40.02#ibcon#enter sib2, iclass 28, count 2 2006.217.07:48:40.02#ibcon#flushed, iclass 28, count 2 2006.217.07:48:40.02#ibcon#about to write, iclass 28, count 2 2006.217.07:48:40.02#ibcon#wrote, iclass 28, count 2 2006.217.07:48:40.02#ibcon#about to read 3, iclass 28, count 2 2006.217.07:48:40.04#ibcon#read 3, iclass 28, count 2 2006.217.07:48:40.04#ibcon#about to read 4, iclass 28, count 2 2006.217.07:48:40.04#ibcon#read 4, iclass 28, count 2 2006.217.07:48:40.04#ibcon#about to read 5, iclass 28, count 2 2006.217.07:48:40.04#ibcon#read 5, iclass 28, count 2 2006.217.07:48:40.04#ibcon#about to read 6, iclass 28, count 2 2006.217.07:48:40.04#ibcon#read 6, iclass 28, count 2 2006.217.07:48:40.04#ibcon#end of sib2, iclass 28, count 2 2006.217.07:48:40.04#ibcon#*mode == 0, iclass 28, count 2 2006.217.07:48:40.04#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.217.07:48:40.04#ibcon#[25=AT07-06\r\n] 2006.217.07:48:40.04#ibcon#*before write, iclass 28, count 2 2006.217.07:48:40.04#ibcon#enter sib2, iclass 28, count 2 2006.217.07:48:40.04#ibcon#flushed, iclass 28, count 2 2006.217.07:48:40.04#ibcon#about to write, iclass 28, count 2 2006.217.07:48:40.04#ibcon#wrote, iclass 28, count 2 2006.217.07:48:40.04#ibcon#about to read 3, iclass 28, count 2 2006.217.07:48:40.07#ibcon#read 3, iclass 28, count 2 2006.217.07:48:40.07#ibcon#about to read 4, iclass 28, count 2 2006.217.07:48:40.07#ibcon#read 4, iclass 28, count 2 2006.217.07:48:40.07#ibcon#about to read 5, iclass 28, count 2 2006.217.07:48:40.07#ibcon#read 5, iclass 28, count 2 2006.217.07:48:40.07#ibcon#about to read 6, iclass 28, count 2 2006.217.07:48:40.07#ibcon#read 6, iclass 28, count 2 2006.217.07:48:40.07#ibcon#end of sib2, iclass 28, count 2 2006.217.07:48:40.07#ibcon#*after write, iclass 28, count 2 2006.217.07:48:40.07#ibcon#*before return 0, iclass 28, count 2 2006.217.07:48:40.07#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.217.07:48:40.07#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.217.07:48:40.07#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.217.07:48:40.07#ibcon#ireg 7 cls_cnt 0 2006.217.07:48:40.07#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.217.07:48:40.13#abcon#<5=/05 3.2 8.5 31.25 631008.6\r\n> 2006.217.07:48:40.15#abcon#{5=INTERFACE CLEAR} 2006.217.07:48:40.19#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.217.07:48:40.19#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.217.07:48:40.19#ibcon#enter wrdev, iclass 28, count 0 2006.217.07:48:40.19#ibcon#first serial, iclass 28, count 0 2006.217.07:48:40.19#ibcon#enter sib2, iclass 28, count 0 2006.217.07:48:40.19#ibcon#flushed, iclass 28, count 0 2006.217.07:48:40.19#ibcon#about to write, iclass 28, count 0 2006.217.07:48:40.19#ibcon#wrote, iclass 28, count 0 2006.217.07:48:40.19#ibcon#about to read 3, iclass 28, count 0 2006.217.07:48:40.21#ibcon#read 3, iclass 28, count 0 2006.217.07:48:40.21#ibcon#about to read 4, iclass 28, count 0 2006.217.07:48:40.21#ibcon#read 4, iclass 28, count 0 2006.217.07:48:40.21#ibcon#about to read 5, iclass 28, count 0 2006.217.07:48:40.21#ibcon#read 5, iclass 28, count 0 2006.217.07:48:40.21#ibcon#about to read 6, iclass 28, count 0 2006.217.07:48:40.21#ibcon#read 6, iclass 28, count 0 2006.217.07:48:40.21#ibcon#end of sib2, iclass 28, count 0 2006.217.07:48:40.21#ibcon#*mode == 0, iclass 28, count 0 2006.217.07:48:40.21#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.217.07:48:40.21#ibcon#[25=USB\r\n] 2006.217.07:48:40.21#ibcon#*before write, iclass 28, count 0 2006.217.07:48:40.21#ibcon#enter sib2, iclass 28, count 0 2006.217.07:48:40.21#ibcon#flushed, iclass 28, count 0 2006.217.07:48:40.21#ibcon#about to write, iclass 28, count 0 2006.217.07:48:40.21#ibcon#wrote, iclass 28, count 0 2006.217.07:48:40.21#ibcon#about to read 3, iclass 28, count 0 2006.217.07:48:40.21#abcon#[5=S1D000X0/0*\r\n] 2006.217.07:48:40.24#ibcon#read 3, iclass 28, count 0 2006.217.07:48:40.24#ibcon#about to read 4, iclass 28, count 0 2006.217.07:48:40.24#ibcon#read 4, iclass 28, count 0 2006.217.07:48:40.24#ibcon#about to read 5, iclass 28, count 0 2006.217.07:48:40.24#ibcon#read 5, iclass 28, count 0 2006.217.07:48:40.24#ibcon#about to read 6, iclass 28, count 0 2006.217.07:48:40.24#ibcon#read 6, iclass 28, count 0 2006.217.07:48:40.24#ibcon#end of sib2, iclass 28, count 0 2006.217.07:48:40.24#ibcon#*after write, iclass 28, count 0 2006.217.07:48:40.24#ibcon#*before return 0, iclass 28, count 0 2006.217.07:48:40.24#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.217.07:48:40.24#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.217.07:48:40.24#ibcon#about to clear, iclass 28 cls_cnt 0 2006.217.07:48:40.24#ibcon#cleared, iclass 28 cls_cnt 0 2006.217.07:48:40.24$vc4f8/valo=8,852.99 2006.217.07:48:40.24#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.217.07:48:40.24#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.217.07:48:40.24#ibcon#ireg 17 cls_cnt 0 2006.217.07:48:40.24#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.217.07:48:40.24#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.217.07:48:40.24#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.217.07:48:40.24#ibcon#enter wrdev, iclass 34, count 0 2006.217.07:48:40.24#ibcon#first serial, iclass 34, count 0 2006.217.07:48:40.24#ibcon#enter sib2, iclass 34, count 0 2006.217.07:48:40.24#ibcon#flushed, iclass 34, count 0 2006.217.07:48:40.24#ibcon#about to write, iclass 34, count 0 2006.217.07:48:40.24#ibcon#wrote, iclass 34, count 0 2006.217.07:48:40.24#ibcon#about to read 3, iclass 34, count 0 2006.217.07:48:40.26#ibcon#read 3, iclass 34, count 0 2006.217.07:48:40.26#ibcon#about to read 4, iclass 34, count 0 2006.217.07:48:40.26#ibcon#read 4, iclass 34, count 0 2006.217.07:48:40.26#ibcon#about to read 5, iclass 34, count 0 2006.217.07:48:40.26#ibcon#read 5, iclass 34, count 0 2006.217.07:48:40.26#ibcon#about to read 6, iclass 34, count 0 2006.217.07:48:40.26#ibcon#read 6, iclass 34, count 0 2006.217.07:48:40.26#ibcon#end of sib2, iclass 34, count 0 2006.217.07:48:40.26#ibcon#*mode == 0, iclass 34, count 0 2006.217.07:48:40.26#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.217.07:48:40.26#ibcon#[26=FRQ=08,852.99\r\n] 2006.217.07:48:40.26#ibcon#*before write, iclass 34, count 0 2006.217.07:48:40.26#ibcon#enter sib2, iclass 34, count 0 2006.217.07:48:40.26#ibcon#flushed, iclass 34, count 0 2006.217.07:48:40.26#ibcon#about to write, iclass 34, count 0 2006.217.07:48:40.26#ibcon#wrote, iclass 34, count 0 2006.217.07:48:40.26#ibcon#about to read 3, iclass 34, count 0 2006.217.07:48:40.31#ibcon#read 3, iclass 34, count 0 2006.217.07:48:40.31#ibcon#about to read 4, iclass 34, count 0 2006.217.07:48:40.31#ibcon#read 4, iclass 34, count 0 2006.217.07:48:40.31#ibcon#about to read 5, iclass 34, count 0 2006.217.07:48:40.31#ibcon#read 5, iclass 34, count 0 2006.217.07:48:40.31#ibcon#about to read 6, iclass 34, count 0 2006.217.07:48:40.31#ibcon#read 6, iclass 34, count 0 2006.217.07:48:40.31#ibcon#end of sib2, iclass 34, count 0 2006.217.07:48:40.31#ibcon#*after write, iclass 34, count 0 2006.217.07:48:40.31#ibcon#*before return 0, iclass 34, count 0 2006.217.07:48:40.31#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.217.07:48:40.31#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.217.07:48:40.31#ibcon#about to clear, iclass 34 cls_cnt 0 2006.217.07:48:40.31#ibcon#cleared, iclass 34 cls_cnt 0 2006.217.07:48:40.31$vc4f8/va=8,7 2006.217.07:48:40.31#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.217.07:48:40.31#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.217.07:48:40.31#ibcon#ireg 11 cls_cnt 2 2006.217.07:48:40.31#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.217.07:48:40.35#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.217.07:48:40.35#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.217.07:48:40.35#ibcon#enter wrdev, iclass 36, count 2 2006.217.07:48:40.35#ibcon#first serial, iclass 36, count 2 2006.217.07:48:40.35#ibcon#enter sib2, iclass 36, count 2 2006.217.07:48:40.35#ibcon#flushed, iclass 36, count 2 2006.217.07:48:40.35#ibcon#about to write, iclass 36, count 2 2006.217.07:48:40.35#ibcon#wrote, iclass 36, count 2 2006.217.07:48:40.35#ibcon#about to read 3, iclass 36, count 2 2006.217.07:48:40.37#ibcon#read 3, iclass 36, count 2 2006.217.07:48:40.37#ibcon#about to read 4, iclass 36, count 2 2006.217.07:48:40.37#ibcon#read 4, iclass 36, count 2 2006.217.07:48:40.37#ibcon#about to read 5, iclass 36, count 2 2006.217.07:48:40.37#ibcon#read 5, iclass 36, count 2 2006.217.07:48:40.37#ibcon#about to read 6, iclass 36, count 2 2006.217.07:48:40.37#ibcon#read 6, iclass 36, count 2 2006.217.07:48:40.37#ibcon#end of sib2, iclass 36, count 2 2006.217.07:48:40.37#ibcon#*mode == 0, iclass 36, count 2 2006.217.07:48:40.37#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.217.07:48:40.37#ibcon#[25=AT08-07\r\n] 2006.217.07:48:40.37#ibcon#*before write, iclass 36, count 2 2006.217.07:48:40.37#ibcon#enter sib2, iclass 36, count 2 2006.217.07:48:40.37#ibcon#flushed, iclass 36, count 2 2006.217.07:48:40.37#ibcon#about to write, iclass 36, count 2 2006.217.07:48:40.37#ibcon#wrote, iclass 36, count 2 2006.217.07:48:40.37#ibcon#about to read 3, iclass 36, count 2 2006.217.07:48:40.40#ibcon#read 3, iclass 36, count 2 2006.217.07:48:40.40#ibcon#about to read 4, iclass 36, count 2 2006.217.07:48:40.40#ibcon#read 4, iclass 36, count 2 2006.217.07:48:40.40#ibcon#about to read 5, iclass 36, count 2 2006.217.07:48:40.40#ibcon#read 5, iclass 36, count 2 2006.217.07:48:40.40#ibcon#about to read 6, iclass 36, count 2 2006.217.07:48:40.40#ibcon#read 6, iclass 36, count 2 2006.217.07:48:40.40#ibcon#end of sib2, iclass 36, count 2 2006.217.07:48:40.40#ibcon#*after write, iclass 36, count 2 2006.217.07:48:40.40#ibcon#*before return 0, iclass 36, count 2 2006.217.07:48:40.40#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.217.07:48:40.40#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.217.07:48:40.40#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.217.07:48:40.40#ibcon#ireg 7 cls_cnt 0 2006.217.07:48:40.40#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.217.07:48:40.52#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.217.07:48:40.52#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.217.07:48:40.52#ibcon#enter wrdev, iclass 36, count 0 2006.217.07:48:40.52#ibcon#first serial, iclass 36, count 0 2006.217.07:48:40.52#ibcon#enter sib2, iclass 36, count 0 2006.217.07:48:40.52#ibcon#flushed, iclass 36, count 0 2006.217.07:48:40.52#ibcon#about to write, iclass 36, count 0 2006.217.07:48:40.52#ibcon#wrote, iclass 36, count 0 2006.217.07:48:40.52#ibcon#about to read 3, iclass 36, count 0 2006.217.07:48:40.54#ibcon#read 3, iclass 36, count 0 2006.217.07:48:40.54#ibcon#about to read 4, iclass 36, count 0 2006.217.07:48:40.54#ibcon#read 4, iclass 36, count 0 2006.217.07:48:40.54#ibcon#about to read 5, iclass 36, count 0 2006.217.07:48:40.54#ibcon#read 5, iclass 36, count 0 2006.217.07:48:40.54#ibcon#about to read 6, iclass 36, count 0 2006.217.07:48:40.54#ibcon#read 6, iclass 36, count 0 2006.217.07:48:40.54#ibcon#end of sib2, iclass 36, count 0 2006.217.07:48:40.54#ibcon#*mode == 0, iclass 36, count 0 2006.217.07:48:40.54#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.217.07:48:40.54#ibcon#[25=USB\r\n] 2006.217.07:48:40.54#ibcon#*before write, iclass 36, count 0 2006.217.07:48:40.54#ibcon#enter sib2, iclass 36, count 0 2006.217.07:48:40.54#ibcon#flushed, iclass 36, count 0 2006.217.07:48:40.54#ibcon#about to write, iclass 36, count 0 2006.217.07:48:40.54#ibcon#wrote, iclass 36, count 0 2006.217.07:48:40.54#ibcon#about to read 3, iclass 36, count 0 2006.217.07:48:40.57#ibcon#read 3, iclass 36, count 0 2006.217.07:48:40.57#ibcon#about to read 4, iclass 36, count 0 2006.217.07:48:40.57#ibcon#read 4, iclass 36, count 0 2006.217.07:48:40.57#ibcon#about to read 5, iclass 36, count 0 2006.217.07:48:40.57#ibcon#read 5, iclass 36, count 0 2006.217.07:48:40.57#ibcon#about to read 6, iclass 36, count 0 2006.217.07:48:40.57#ibcon#read 6, iclass 36, count 0 2006.217.07:48:40.57#ibcon#end of sib2, iclass 36, count 0 2006.217.07:48:40.57#ibcon#*after write, iclass 36, count 0 2006.217.07:48:40.57#ibcon#*before return 0, iclass 36, count 0 2006.217.07:48:40.57#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.217.07:48:40.57#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.217.07:48:40.57#ibcon#about to clear, iclass 36 cls_cnt 0 2006.217.07:48:40.57#ibcon#cleared, iclass 36 cls_cnt 0 2006.217.07:48:40.57$vc4f8/vblo=1,632.99 2006.217.07:48:40.57#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.217.07:48:40.57#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.217.07:48:40.57#ibcon#ireg 17 cls_cnt 0 2006.217.07:48:40.57#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.217.07:48:40.57#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.217.07:48:40.57#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.217.07:48:40.57#ibcon#enter wrdev, iclass 38, count 0 2006.217.07:48:40.57#ibcon#first serial, iclass 38, count 0 2006.217.07:48:40.57#ibcon#enter sib2, iclass 38, count 0 2006.217.07:48:40.57#ibcon#flushed, iclass 38, count 0 2006.217.07:48:40.57#ibcon#about to write, iclass 38, count 0 2006.217.07:48:40.57#ibcon#wrote, iclass 38, count 0 2006.217.07:48:40.57#ibcon#about to read 3, iclass 38, count 0 2006.217.07:48:40.59#ibcon#read 3, iclass 38, count 0 2006.217.07:48:40.59#ibcon#about to read 4, iclass 38, count 0 2006.217.07:48:40.59#ibcon#read 4, iclass 38, count 0 2006.217.07:48:40.59#ibcon#about to read 5, iclass 38, count 0 2006.217.07:48:40.59#ibcon#read 5, iclass 38, count 0 2006.217.07:48:40.59#ibcon#about to read 6, iclass 38, count 0 2006.217.07:48:40.59#ibcon#read 6, iclass 38, count 0 2006.217.07:48:40.59#ibcon#end of sib2, iclass 38, count 0 2006.217.07:48:40.59#ibcon#*mode == 0, iclass 38, count 0 2006.217.07:48:40.59#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.217.07:48:40.59#ibcon#[28=FRQ=01,632.99\r\n] 2006.217.07:48:40.59#ibcon#*before write, iclass 38, count 0 2006.217.07:48:40.59#ibcon#enter sib2, iclass 38, count 0 2006.217.07:48:40.59#ibcon#flushed, iclass 38, count 0 2006.217.07:48:40.59#ibcon#about to write, iclass 38, count 0 2006.217.07:48:40.59#ibcon#wrote, iclass 38, count 0 2006.217.07:48:40.59#ibcon#about to read 3, iclass 38, count 0 2006.217.07:48:40.63#ibcon#read 3, iclass 38, count 0 2006.217.07:48:40.63#ibcon#about to read 4, iclass 38, count 0 2006.217.07:48:40.63#ibcon#read 4, iclass 38, count 0 2006.217.07:48:40.63#ibcon#about to read 5, iclass 38, count 0 2006.217.07:48:40.63#ibcon#read 5, iclass 38, count 0 2006.217.07:48:40.63#ibcon#about to read 6, iclass 38, count 0 2006.217.07:48:40.63#ibcon#read 6, iclass 38, count 0 2006.217.07:48:40.63#ibcon#end of sib2, iclass 38, count 0 2006.217.07:48:40.63#ibcon#*after write, iclass 38, count 0 2006.217.07:48:40.63#ibcon#*before return 0, iclass 38, count 0 2006.217.07:48:40.63#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.217.07:48:40.63#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.217.07:48:40.63#ibcon#about to clear, iclass 38 cls_cnt 0 2006.217.07:48:40.63#ibcon#cleared, iclass 38 cls_cnt 0 2006.217.07:48:40.63$vc4f8/vb=1,4 2006.217.07:48:40.63#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.217.07:48:40.63#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.217.07:48:40.63#ibcon#ireg 11 cls_cnt 2 2006.217.07:48:40.63#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.217.07:48:40.63#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.217.07:48:40.63#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.217.07:48:40.63#ibcon#enter wrdev, iclass 40, count 2 2006.217.07:48:40.63#ibcon#first serial, iclass 40, count 2 2006.217.07:48:40.63#ibcon#enter sib2, iclass 40, count 2 2006.217.07:48:40.63#ibcon#flushed, iclass 40, count 2 2006.217.07:48:40.63#ibcon#about to write, iclass 40, count 2 2006.217.07:48:40.63#ibcon#wrote, iclass 40, count 2 2006.217.07:48:40.63#ibcon#about to read 3, iclass 40, count 2 2006.217.07:48:40.65#ibcon#read 3, iclass 40, count 2 2006.217.07:48:40.65#ibcon#about to read 4, iclass 40, count 2 2006.217.07:48:40.65#ibcon#read 4, iclass 40, count 2 2006.217.07:48:40.65#ibcon#about to read 5, iclass 40, count 2 2006.217.07:48:40.65#ibcon#read 5, iclass 40, count 2 2006.217.07:48:40.65#ibcon#about to read 6, iclass 40, count 2 2006.217.07:48:40.65#ibcon#read 6, iclass 40, count 2 2006.217.07:48:40.65#ibcon#end of sib2, iclass 40, count 2 2006.217.07:48:40.65#ibcon#*mode == 0, iclass 40, count 2 2006.217.07:48:40.65#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.217.07:48:40.65#ibcon#[27=AT01-04\r\n] 2006.217.07:48:40.65#ibcon#*before write, iclass 40, count 2 2006.217.07:48:40.65#ibcon#enter sib2, iclass 40, count 2 2006.217.07:48:40.65#ibcon#flushed, iclass 40, count 2 2006.217.07:48:40.65#ibcon#about to write, iclass 40, count 2 2006.217.07:48:40.65#ibcon#wrote, iclass 40, count 2 2006.217.07:48:40.65#ibcon#about to read 3, iclass 40, count 2 2006.217.07:48:40.68#ibcon#read 3, iclass 40, count 2 2006.217.07:48:40.68#ibcon#about to read 4, iclass 40, count 2 2006.217.07:48:40.68#ibcon#read 4, iclass 40, count 2 2006.217.07:48:40.68#ibcon#about to read 5, iclass 40, count 2 2006.217.07:48:40.68#ibcon#read 5, iclass 40, count 2 2006.217.07:48:40.68#ibcon#about to read 6, iclass 40, count 2 2006.217.07:48:40.68#ibcon#read 6, iclass 40, count 2 2006.217.07:48:40.68#ibcon#end of sib2, iclass 40, count 2 2006.217.07:48:40.68#ibcon#*after write, iclass 40, count 2 2006.217.07:48:40.68#ibcon#*before return 0, iclass 40, count 2 2006.217.07:48:40.68#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.217.07:48:40.68#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.217.07:48:40.68#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.217.07:48:40.68#ibcon#ireg 7 cls_cnt 0 2006.217.07:48:40.68#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.217.07:48:40.80#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.217.07:48:40.80#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.217.07:48:40.80#ibcon#enter wrdev, iclass 40, count 0 2006.217.07:48:40.80#ibcon#first serial, iclass 40, count 0 2006.217.07:48:40.80#ibcon#enter sib2, iclass 40, count 0 2006.217.07:48:40.80#ibcon#flushed, iclass 40, count 0 2006.217.07:48:40.80#ibcon#about to write, iclass 40, count 0 2006.217.07:48:40.80#ibcon#wrote, iclass 40, count 0 2006.217.07:48:40.80#ibcon#about to read 3, iclass 40, count 0 2006.217.07:48:40.82#ibcon#read 3, iclass 40, count 0 2006.217.07:48:40.82#ibcon#about to read 4, iclass 40, count 0 2006.217.07:48:40.82#ibcon#read 4, iclass 40, count 0 2006.217.07:48:40.82#ibcon#about to read 5, iclass 40, count 0 2006.217.07:48:40.82#ibcon#read 5, iclass 40, count 0 2006.217.07:48:40.82#ibcon#about to read 6, iclass 40, count 0 2006.217.07:48:40.82#ibcon#read 6, iclass 40, count 0 2006.217.07:48:40.82#ibcon#end of sib2, iclass 40, count 0 2006.217.07:48:40.82#ibcon#*mode == 0, iclass 40, count 0 2006.217.07:48:40.82#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.217.07:48:40.82#ibcon#[27=USB\r\n] 2006.217.07:48:40.82#ibcon#*before write, iclass 40, count 0 2006.217.07:48:40.82#ibcon#enter sib2, iclass 40, count 0 2006.217.07:48:40.82#ibcon#flushed, iclass 40, count 0 2006.217.07:48:40.82#ibcon#about to write, iclass 40, count 0 2006.217.07:48:40.82#ibcon#wrote, iclass 40, count 0 2006.217.07:48:40.82#ibcon#about to read 3, iclass 40, count 0 2006.217.07:48:40.85#ibcon#read 3, iclass 40, count 0 2006.217.07:48:40.85#ibcon#about to read 4, iclass 40, count 0 2006.217.07:48:40.85#ibcon#read 4, iclass 40, count 0 2006.217.07:48:40.85#ibcon#about to read 5, iclass 40, count 0 2006.217.07:48:40.85#ibcon#read 5, iclass 40, count 0 2006.217.07:48:40.85#ibcon#about to read 6, iclass 40, count 0 2006.217.07:48:40.85#ibcon#read 6, iclass 40, count 0 2006.217.07:48:40.85#ibcon#end of sib2, iclass 40, count 0 2006.217.07:48:40.85#ibcon#*after write, iclass 40, count 0 2006.217.07:48:40.85#ibcon#*before return 0, iclass 40, count 0 2006.217.07:48:40.85#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.217.07:48:40.85#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.217.07:48:40.85#ibcon#about to clear, iclass 40 cls_cnt 0 2006.217.07:48:40.85#ibcon#cleared, iclass 40 cls_cnt 0 2006.217.07:48:40.85$vc4f8/vblo=2,640.99 2006.217.07:48:40.85#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.217.07:48:40.85#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.217.07:48:40.85#ibcon#ireg 17 cls_cnt 0 2006.217.07:48:40.85#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.217.07:48:40.85#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.217.07:48:40.85#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.217.07:48:40.85#ibcon#enter wrdev, iclass 4, count 0 2006.217.07:48:40.85#ibcon#first serial, iclass 4, count 0 2006.217.07:48:40.85#ibcon#enter sib2, iclass 4, count 0 2006.217.07:48:40.85#ibcon#flushed, iclass 4, count 0 2006.217.07:48:40.85#ibcon#about to write, iclass 4, count 0 2006.217.07:48:40.85#ibcon#wrote, iclass 4, count 0 2006.217.07:48:40.85#ibcon#about to read 3, iclass 4, count 0 2006.217.07:48:40.87#ibcon#read 3, iclass 4, count 0 2006.217.07:48:40.87#ibcon#about to read 4, iclass 4, count 0 2006.217.07:48:40.87#ibcon#read 4, iclass 4, count 0 2006.217.07:48:40.87#ibcon#about to read 5, iclass 4, count 0 2006.217.07:48:40.87#ibcon#read 5, iclass 4, count 0 2006.217.07:48:40.87#ibcon#about to read 6, iclass 4, count 0 2006.217.07:48:40.87#ibcon#read 6, iclass 4, count 0 2006.217.07:48:40.87#ibcon#end of sib2, iclass 4, count 0 2006.217.07:48:40.87#ibcon#*mode == 0, iclass 4, count 0 2006.217.07:48:40.87#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.217.07:48:40.87#ibcon#[28=FRQ=02,640.99\r\n] 2006.217.07:48:40.87#ibcon#*before write, iclass 4, count 0 2006.217.07:48:40.87#ibcon#enter sib2, iclass 4, count 0 2006.217.07:48:40.87#ibcon#flushed, iclass 4, count 0 2006.217.07:48:40.87#ibcon#about to write, iclass 4, count 0 2006.217.07:48:40.87#ibcon#wrote, iclass 4, count 0 2006.217.07:48:40.87#ibcon#about to read 3, iclass 4, count 0 2006.217.07:48:40.91#ibcon#read 3, iclass 4, count 0 2006.217.07:48:40.91#ibcon#about to read 4, iclass 4, count 0 2006.217.07:48:40.91#ibcon#read 4, iclass 4, count 0 2006.217.07:48:40.91#ibcon#about to read 5, iclass 4, count 0 2006.217.07:48:40.91#ibcon#read 5, iclass 4, count 0 2006.217.07:48:40.91#ibcon#about to read 6, iclass 4, count 0 2006.217.07:48:40.91#ibcon#read 6, iclass 4, count 0 2006.217.07:48:40.91#ibcon#end of sib2, iclass 4, count 0 2006.217.07:48:40.91#ibcon#*after write, iclass 4, count 0 2006.217.07:48:40.91#ibcon#*before return 0, iclass 4, count 0 2006.217.07:48:40.91#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.217.07:48:40.91#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.217.07:48:40.91#ibcon#about to clear, iclass 4 cls_cnt 0 2006.217.07:48:40.91#ibcon#cleared, iclass 4 cls_cnt 0 2006.217.07:48:40.91$vc4f8/vb=2,4 2006.217.07:48:40.91#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.217.07:48:40.91#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.217.07:48:40.91#ibcon#ireg 11 cls_cnt 2 2006.217.07:48:40.91#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.217.07:48:40.97#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.217.07:48:40.97#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.217.07:48:40.97#ibcon#enter wrdev, iclass 6, count 2 2006.217.07:48:40.97#ibcon#first serial, iclass 6, count 2 2006.217.07:48:40.97#ibcon#enter sib2, iclass 6, count 2 2006.217.07:48:40.97#ibcon#flushed, iclass 6, count 2 2006.217.07:48:40.97#ibcon#about to write, iclass 6, count 2 2006.217.07:48:40.97#ibcon#wrote, iclass 6, count 2 2006.217.07:48:40.97#ibcon#about to read 3, iclass 6, count 2 2006.217.07:48:40.99#ibcon#read 3, iclass 6, count 2 2006.217.07:48:40.99#ibcon#about to read 4, iclass 6, count 2 2006.217.07:48:40.99#ibcon#read 4, iclass 6, count 2 2006.217.07:48:40.99#ibcon#about to read 5, iclass 6, count 2 2006.217.07:48:40.99#ibcon#read 5, iclass 6, count 2 2006.217.07:48:40.99#ibcon#about to read 6, iclass 6, count 2 2006.217.07:48:40.99#ibcon#read 6, iclass 6, count 2 2006.217.07:48:40.99#ibcon#end of sib2, iclass 6, count 2 2006.217.07:48:40.99#ibcon#*mode == 0, iclass 6, count 2 2006.217.07:48:40.99#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.217.07:48:40.99#ibcon#[27=AT02-04\r\n] 2006.217.07:48:40.99#ibcon#*before write, iclass 6, count 2 2006.217.07:48:40.99#ibcon#enter sib2, iclass 6, count 2 2006.217.07:48:40.99#ibcon#flushed, iclass 6, count 2 2006.217.07:48:40.99#ibcon#about to write, iclass 6, count 2 2006.217.07:48:40.99#ibcon#wrote, iclass 6, count 2 2006.217.07:48:40.99#ibcon#about to read 3, iclass 6, count 2 2006.217.07:48:41.02#ibcon#read 3, iclass 6, count 2 2006.217.07:48:41.02#ibcon#about to read 4, iclass 6, count 2 2006.217.07:48:41.02#ibcon#read 4, iclass 6, count 2 2006.217.07:48:41.02#ibcon#about to read 5, iclass 6, count 2 2006.217.07:48:41.02#ibcon#read 5, iclass 6, count 2 2006.217.07:48:41.02#ibcon#about to read 6, iclass 6, count 2 2006.217.07:48:41.02#ibcon#read 6, iclass 6, count 2 2006.217.07:48:41.02#ibcon#end of sib2, iclass 6, count 2 2006.217.07:48:41.02#ibcon#*after write, iclass 6, count 2 2006.217.07:48:41.02#ibcon#*before return 0, iclass 6, count 2 2006.217.07:48:41.02#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.217.07:48:41.02#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.217.07:48:41.02#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.217.07:48:41.02#ibcon#ireg 7 cls_cnt 0 2006.217.07:48:41.02#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.217.07:48:41.14#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.217.07:48:41.14#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.217.07:48:41.14#ibcon#enter wrdev, iclass 6, count 0 2006.217.07:48:41.14#ibcon#first serial, iclass 6, count 0 2006.217.07:48:41.14#ibcon#enter sib2, iclass 6, count 0 2006.217.07:48:41.14#ibcon#flushed, iclass 6, count 0 2006.217.07:48:41.14#ibcon#about to write, iclass 6, count 0 2006.217.07:48:41.14#ibcon#wrote, iclass 6, count 0 2006.217.07:48:41.14#ibcon#about to read 3, iclass 6, count 0 2006.217.07:48:41.16#ibcon#read 3, iclass 6, count 0 2006.217.07:48:41.16#ibcon#about to read 4, iclass 6, count 0 2006.217.07:48:41.16#ibcon#read 4, iclass 6, count 0 2006.217.07:48:41.16#ibcon#about to read 5, iclass 6, count 0 2006.217.07:48:41.16#ibcon#read 5, iclass 6, count 0 2006.217.07:48:41.16#ibcon#about to read 6, iclass 6, count 0 2006.217.07:48:41.16#ibcon#read 6, iclass 6, count 0 2006.217.07:48:41.16#ibcon#end of sib2, iclass 6, count 0 2006.217.07:48:41.16#ibcon#*mode == 0, iclass 6, count 0 2006.217.07:48:41.16#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.217.07:48:41.16#ibcon#[27=USB\r\n] 2006.217.07:48:41.16#ibcon#*before write, iclass 6, count 0 2006.217.07:48:41.16#ibcon#enter sib2, iclass 6, count 0 2006.217.07:48:41.16#ibcon#flushed, iclass 6, count 0 2006.217.07:48:41.16#ibcon#about to write, iclass 6, count 0 2006.217.07:48:41.16#ibcon#wrote, iclass 6, count 0 2006.217.07:48:41.16#ibcon#about to read 3, iclass 6, count 0 2006.217.07:48:41.19#ibcon#read 3, iclass 6, count 0 2006.217.07:48:41.19#ibcon#about to read 4, iclass 6, count 0 2006.217.07:48:41.19#ibcon#read 4, iclass 6, count 0 2006.217.07:48:41.19#ibcon#about to read 5, iclass 6, count 0 2006.217.07:48:41.19#ibcon#read 5, iclass 6, count 0 2006.217.07:48:41.19#ibcon#about to read 6, iclass 6, count 0 2006.217.07:48:41.19#ibcon#read 6, iclass 6, count 0 2006.217.07:48:41.19#ibcon#end of sib2, iclass 6, count 0 2006.217.07:48:41.19#ibcon#*after write, iclass 6, count 0 2006.217.07:48:41.19#ibcon#*before return 0, iclass 6, count 0 2006.217.07:48:41.19#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.217.07:48:41.19#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.217.07:48:41.19#ibcon#about to clear, iclass 6 cls_cnt 0 2006.217.07:48:41.19#ibcon#cleared, iclass 6 cls_cnt 0 2006.217.07:48:41.19$vc4f8/vblo=3,656.99 2006.217.07:48:41.19#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.217.07:48:41.19#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.217.07:48:41.19#ibcon#ireg 17 cls_cnt 0 2006.217.07:48:41.19#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.217.07:48:41.19#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.217.07:48:41.19#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.217.07:48:41.19#ibcon#enter wrdev, iclass 10, count 0 2006.217.07:48:41.19#ibcon#first serial, iclass 10, count 0 2006.217.07:48:41.19#ibcon#enter sib2, iclass 10, count 0 2006.217.07:48:41.19#ibcon#flushed, iclass 10, count 0 2006.217.07:48:41.19#ibcon#about to write, iclass 10, count 0 2006.217.07:48:41.19#ibcon#wrote, iclass 10, count 0 2006.217.07:48:41.19#ibcon#about to read 3, iclass 10, count 0 2006.217.07:48:41.22#ibcon#read 3, iclass 10, count 0 2006.217.07:48:41.22#ibcon#about to read 4, iclass 10, count 0 2006.217.07:48:41.22#ibcon#read 4, iclass 10, count 0 2006.217.07:48:41.22#ibcon#about to read 5, iclass 10, count 0 2006.217.07:48:41.22#ibcon#read 5, iclass 10, count 0 2006.217.07:48:41.22#ibcon#about to read 6, iclass 10, count 0 2006.217.07:48:41.22#ibcon#read 6, iclass 10, count 0 2006.217.07:48:41.22#ibcon#end of sib2, iclass 10, count 0 2006.217.07:48:41.22#ibcon#*mode == 0, iclass 10, count 0 2006.217.07:48:41.22#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.217.07:48:41.22#ibcon#[28=FRQ=03,656.99\r\n] 2006.217.07:48:41.22#ibcon#*before write, iclass 10, count 0 2006.217.07:48:41.22#ibcon#enter sib2, iclass 10, count 0 2006.217.07:48:41.22#ibcon#flushed, iclass 10, count 0 2006.217.07:48:41.22#ibcon#about to write, iclass 10, count 0 2006.217.07:48:41.22#ibcon#wrote, iclass 10, count 0 2006.217.07:48:41.22#ibcon#about to read 3, iclass 10, count 0 2006.217.07:48:41.26#ibcon#read 3, iclass 10, count 0 2006.217.07:48:41.26#ibcon#about to read 4, iclass 10, count 0 2006.217.07:48:41.26#ibcon#read 4, iclass 10, count 0 2006.217.07:48:41.26#ibcon#about to read 5, iclass 10, count 0 2006.217.07:48:41.26#ibcon#read 5, iclass 10, count 0 2006.217.07:48:41.26#ibcon#about to read 6, iclass 10, count 0 2006.217.07:48:41.26#ibcon#read 6, iclass 10, count 0 2006.217.07:48:41.26#ibcon#end of sib2, iclass 10, count 0 2006.217.07:48:41.26#ibcon#*after write, iclass 10, count 0 2006.217.07:48:41.26#ibcon#*before return 0, iclass 10, count 0 2006.217.07:48:41.26#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.217.07:48:41.26#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.217.07:48:41.26#ibcon#about to clear, iclass 10 cls_cnt 0 2006.217.07:48:41.26#ibcon#cleared, iclass 10 cls_cnt 0 2006.217.07:48:41.26$vc4f8/vb=3,4 2006.217.07:48:41.26#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.217.07:48:41.26#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.217.07:48:41.26#ibcon#ireg 11 cls_cnt 2 2006.217.07:48:41.26#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.217.07:48:41.31#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.217.07:48:41.31#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.217.07:48:41.31#ibcon#enter wrdev, iclass 12, count 2 2006.217.07:48:41.31#ibcon#first serial, iclass 12, count 2 2006.217.07:48:41.31#ibcon#enter sib2, iclass 12, count 2 2006.217.07:48:41.31#ibcon#flushed, iclass 12, count 2 2006.217.07:48:41.31#ibcon#about to write, iclass 12, count 2 2006.217.07:48:41.31#ibcon#wrote, iclass 12, count 2 2006.217.07:48:41.31#ibcon#about to read 3, iclass 12, count 2 2006.217.07:48:41.33#ibcon#read 3, iclass 12, count 2 2006.217.07:48:41.33#ibcon#about to read 4, iclass 12, count 2 2006.217.07:48:41.33#ibcon#read 4, iclass 12, count 2 2006.217.07:48:41.33#ibcon#about to read 5, iclass 12, count 2 2006.217.07:48:41.33#ibcon#read 5, iclass 12, count 2 2006.217.07:48:41.33#ibcon#about to read 6, iclass 12, count 2 2006.217.07:48:41.33#ibcon#read 6, iclass 12, count 2 2006.217.07:48:41.33#ibcon#end of sib2, iclass 12, count 2 2006.217.07:48:41.33#ibcon#*mode == 0, iclass 12, count 2 2006.217.07:48:41.33#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.217.07:48:41.33#ibcon#[27=AT03-04\r\n] 2006.217.07:48:41.33#ibcon#*before write, iclass 12, count 2 2006.217.07:48:41.33#ibcon#enter sib2, iclass 12, count 2 2006.217.07:48:41.33#ibcon#flushed, iclass 12, count 2 2006.217.07:48:41.33#ibcon#about to write, iclass 12, count 2 2006.217.07:48:41.33#ibcon#wrote, iclass 12, count 2 2006.217.07:48:41.33#ibcon#about to read 3, iclass 12, count 2 2006.217.07:48:41.36#ibcon#read 3, iclass 12, count 2 2006.217.07:48:41.36#ibcon#about to read 4, iclass 12, count 2 2006.217.07:48:41.36#ibcon#read 4, iclass 12, count 2 2006.217.07:48:41.36#ibcon#about to read 5, iclass 12, count 2 2006.217.07:48:41.36#ibcon#read 5, iclass 12, count 2 2006.217.07:48:41.36#ibcon#about to read 6, iclass 12, count 2 2006.217.07:48:41.36#ibcon#read 6, iclass 12, count 2 2006.217.07:48:41.36#ibcon#end of sib2, iclass 12, count 2 2006.217.07:48:41.36#ibcon#*after write, iclass 12, count 2 2006.217.07:48:41.36#ibcon#*before return 0, iclass 12, count 2 2006.217.07:48:41.36#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.217.07:48:41.36#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.217.07:48:41.36#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.217.07:48:41.36#ibcon#ireg 7 cls_cnt 0 2006.217.07:48:41.36#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.217.07:48:41.48#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.217.07:48:41.48#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.217.07:48:41.48#ibcon#enter wrdev, iclass 12, count 0 2006.217.07:48:41.48#ibcon#first serial, iclass 12, count 0 2006.217.07:48:41.48#ibcon#enter sib2, iclass 12, count 0 2006.217.07:48:41.48#ibcon#flushed, iclass 12, count 0 2006.217.07:48:41.48#ibcon#about to write, iclass 12, count 0 2006.217.07:48:41.48#ibcon#wrote, iclass 12, count 0 2006.217.07:48:41.48#ibcon#about to read 3, iclass 12, count 0 2006.217.07:48:41.50#ibcon#read 3, iclass 12, count 0 2006.217.07:48:41.50#ibcon#about to read 4, iclass 12, count 0 2006.217.07:48:41.50#ibcon#read 4, iclass 12, count 0 2006.217.07:48:41.50#ibcon#about to read 5, iclass 12, count 0 2006.217.07:48:41.50#ibcon#read 5, iclass 12, count 0 2006.217.07:48:41.50#ibcon#about to read 6, iclass 12, count 0 2006.217.07:48:41.50#ibcon#read 6, iclass 12, count 0 2006.217.07:48:41.50#ibcon#end of sib2, iclass 12, count 0 2006.217.07:48:41.50#ibcon#*mode == 0, iclass 12, count 0 2006.217.07:48:41.50#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.217.07:48:41.50#ibcon#[27=USB\r\n] 2006.217.07:48:41.50#ibcon#*before write, iclass 12, count 0 2006.217.07:48:41.50#ibcon#enter sib2, iclass 12, count 0 2006.217.07:48:41.50#ibcon#flushed, iclass 12, count 0 2006.217.07:48:41.50#ibcon#about to write, iclass 12, count 0 2006.217.07:48:41.50#ibcon#wrote, iclass 12, count 0 2006.217.07:48:41.50#ibcon#about to read 3, iclass 12, count 0 2006.217.07:48:41.53#ibcon#read 3, iclass 12, count 0 2006.217.07:48:41.53#ibcon#about to read 4, iclass 12, count 0 2006.217.07:48:41.53#ibcon#read 4, iclass 12, count 0 2006.217.07:48:41.53#ibcon#about to read 5, iclass 12, count 0 2006.217.07:48:41.53#ibcon#read 5, iclass 12, count 0 2006.217.07:48:41.53#ibcon#about to read 6, iclass 12, count 0 2006.217.07:48:41.53#ibcon#read 6, iclass 12, count 0 2006.217.07:48:41.53#ibcon#end of sib2, iclass 12, count 0 2006.217.07:48:41.53#ibcon#*after write, iclass 12, count 0 2006.217.07:48:41.53#ibcon#*before return 0, iclass 12, count 0 2006.217.07:48:41.53#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.217.07:48:41.53#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.217.07:48:41.53#ibcon#about to clear, iclass 12 cls_cnt 0 2006.217.07:48:41.53#ibcon#cleared, iclass 12 cls_cnt 0 2006.217.07:48:41.53$vc4f8/vblo=4,712.99 2006.217.07:48:41.53#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.217.07:48:41.53#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.217.07:48:41.53#ibcon#ireg 17 cls_cnt 0 2006.217.07:48:41.53#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.217.07:48:41.53#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.217.07:48:41.53#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.217.07:48:41.53#ibcon#enter wrdev, iclass 14, count 0 2006.217.07:48:41.53#ibcon#first serial, iclass 14, count 0 2006.217.07:48:41.53#ibcon#enter sib2, iclass 14, count 0 2006.217.07:48:41.53#ibcon#flushed, iclass 14, count 0 2006.217.07:48:41.53#ibcon#about to write, iclass 14, count 0 2006.217.07:48:41.53#ibcon#wrote, iclass 14, count 0 2006.217.07:48:41.53#ibcon#about to read 3, iclass 14, count 0 2006.217.07:48:41.55#ibcon#read 3, iclass 14, count 0 2006.217.07:48:41.55#ibcon#about to read 4, iclass 14, count 0 2006.217.07:48:41.55#ibcon#read 4, iclass 14, count 0 2006.217.07:48:41.55#ibcon#about to read 5, iclass 14, count 0 2006.217.07:48:41.55#ibcon#read 5, iclass 14, count 0 2006.217.07:48:41.55#ibcon#about to read 6, iclass 14, count 0 2006.217.07:48:41.55#ibcon#read 6, iclass 14, count 0 2006.217.07:48:41.55#ibcon#end of sib2, iclass 14, count 0 2006.217.07:48:41.55#ibcon#*mode == 0, iclass 14, count 0 2006.217.07:48:41.55#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.217.07:48:41.55#ibcon#[28=FRQ=04,712.99\r\n] 2006.217.07:48:41.55#ibcon#*before write, iclass 14, count 0 2006.217.07:48:41.55#ibcon#enter sib2, iclass 14, count 0 2006.217.07:48:41.55#ibcon#flushed, iclass 14, count 0 2006.217.07:48:41.55#ibcon#about to write, iclass 14, count 0 2006.217.07:48:41.55#ibcon#wrote, iclass 14, count 0 2006.217.07:48:41.55#ibcon#about to read 3, iclass 14, count 0 2006.217.07:48:41.59#ibcon#read 3, iclass 14, count 0 2006.217.07:48:41.59#ibcon#about to read 4, iclass 14, count 0 2006.217.07:48:41.59#ibcon#read 4, iclass 14, count 0 2006.217.07:48:41.59#ibcon#about to read 5, iclass 14, count 0 2006.217.07:48:41.59#ibcon#read 5, iclass 14, count 0 2006.217.07:48:41.59#ibcon#about to read 6, iclass 14, count 0 2006.217.07:48:41.59#ibcon#read 6, iclass 14, count 0 2006.217.07:48:41.59#ibcon#end of sib2, iclass 14, count 0 2006.217.07:48:41.59#ibcon#*after write, iclass 14, count 0 2006.217.07:48:41.59#ibcon#*before return 0, iclass 14, count 0 2006.217.07:48:41.59#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.217.07:48:41.59#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.217.07:48:41.59#ibcon#about to clear, iclass 14 cls_cnt 0 2006.217.07:48:41.59#ibcon#cleared, iclass 14 cls_cnt 0 2006.217.07:48:41.59$vc4f8/vb=4,4 2006.217.07:48:41.59#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.217.07:48:41.59#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.217.07:48:41.59#ibcon#ireg 11 cls_cnt 2 2006.217.07:48:41.59#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.217.07:48:41.65#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.217.07:48:41.65#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.217.07:48:41.65#ibcon#enter wrdev, iclass 16, count 2 2006.217.07:48:41.65#ibcon#first serial, iclass 16, count 2 2006.217.07:48:41.65#ibcon#enter sib2, iclass 16, count 2 2006.217.07:48:41.65#ibcon#flushed, iclass 16, count 2 2006.217.07:48:41.65#ibcon#about to write, iclass 16, count 2 2006.217.07:48:41.65#ibcon#wrote, iclass 16, count 2 2006.217.07:48:41.65#ibcon#about to read 3, iclass 16, count 2 2006.217.07:48:41.67#ibcon#read 3, iclass 16, count 2 2006.217.07:48:41.67#ibcon#about to read 4, iclass 16, count 2 2006.217.07:48:41.67#ibcon#read 4, iclass 16, count 2 2006.217.07:48:41.67#ibcon#about to read 5, iclass 16, count 2 2006.217.07:48:41.67#ibcon#read 5, iclass 16, count 2 2006.217.07:48:41.67#ibcon#about to read 6, iclass 16, count 2 2006.217.07:48:41.67#ibcon#read 6, iclass 16, count 2 2006.217.07:48:41.67#ibcon#end of sib2, iclass 16, count 2 2006.217.07:48:41.67#ibcon#*mode == 0, iclass 16, count 2 2006.217.07:48:41.67#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.217.07:48:41.67#ibcon#[27=AT04-04\r\n] 2006.217.07:48:41.67#ibcon#*before write, iclass 16, count 2 2006.217.07:48:41.67#ibcon#enter sib2, iclass 16, count 2 2006.217.07:48:41.67#ibcon#flushed, iclass 16, count 2 2006.217.07:48:41.67#ibcon#about to write, iclass 16, count 2 2006.217.07:48:41.67#ibcon#wrote, iclass 16, count 2 2006.217.07:48:41.67#ibcon#about to read 3, iclass 16, count 2 2006.217.07:48:41.70#ibcon#read 3, iclass 16, count 2 2006.217.07:48:41.70#ibcon#about to read 4, iclass 16, count 2 2006.217.07:48:41.70#ibcon#read 4, iclass 16, count 2 2006.217.07:48:41.70#ibcon#about to read 5, iclass 16, count 2 2006.217.07:48:41.70#ibcon#read 5, iclass 16, count 2 2006.217.07:48:41.70#ibcon#about to read 6, iclass 16, count 2 2006.217.07:48:41.70#ibcon#read 6, iclass 16, count 2 2006.217.07:48:41.70#ibcon#end of sib2, iclass 16, count 2 2006.217.07:48:41.70#ibcon#*after write, iclass 16, count 2 2006.217.07:48:41.70#ibcon#*before return 0, iclass 16, count 2 2006.217.07:48:41.70#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.217.07:48:41.70#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.217.07:48:41.70#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.217.07:48:41.70#ibcon#ireg 7 cls_cnt 0 2006.217.07:48:41.70#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.217.07:48:41.82#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.217.07:48:41.82#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.217.07:48:41.82#ibcon#enter wrdev, iclass 16, count 0 2006.217.07:48:41.82#ibcon#first serial, iclass 16, count 0 2006.217.07:48:41.82#ibcon#enter sib2, iclass 16, count 0 2006.217.07:48:41.82#ibcon#flushed, iclass 16, count 0 2006.217.07:48:41.82#ibcon#about to write, iclass 16, count 0 2006.217.07:48:41.82#ibcon#wrote, iclass 16, count 0 2006.217.07:48:41.82#ibcon#about to read 3, iclass 16, count 0 2006.217.07:48:41.84#ibcon#read 3, iclass 16, count 0 2006.217.07:48:41.84#ibcon#about to read 4, iclass 16, count 0 2006.217.07:48:41.84#ibcon#read 4, iclass 16, count 0 2006.217.07:48:41.84#ibcon#about to read 5, iclass 16, count 0 2006.217.07:48:41.84#ibcon#read 5, iclass 16, count 0 2006.217.07:48:41.84#ibcon#about to read 6, iclass 16, count 0 2006.217.07:48:41.84#ibcon#read 6, iclass 16, count 0 2006.217.07:48:41.84#ibcon#end of sib2, iclass 16, count 0 2006.217.07:48:41.84#ibcon#*mode == 0, iclass 16, count 0 2006.217.07:48:41.84#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.217.07:48:41.84#ibcon#[27=USB\r\n] 2006.217.07:48:41.84#ibcon#*before write, iclass 16, count 0 2006.217.07:48:41.84#ibcon#enter sib2, iclass 16, count 0 2006.217.07:48:41.84#ibcon#flushed, iclass 16, count 0 2006.217.07:48:41.84#ibcon#about to write, iclass 16, count 0 2006.217.07:48:41.84#ibcon#wrote, iclass 16, count 0 2006.217.07:48:41.84#ibcon#about to read 3, iclass 16, count 0 2006.217.07:48:41.87#ibcon#read 3, iclass 16, count 0 2006.217.07:48:41.87#ibcon#about to read 4, iclass 16, count 0 2006.217.07:48:41.87#ibcon#read 4, iclass 16, count 0 2006.217.07:48:41.87#ibcon#about to read 5, iclass 16, count 0 2006.217.07:48:41.87#ibcon#read 5, iclass 16, count 0 2006.217.07:48:41.87#ibcon#about to read 6, iclass 16, count 0 2006.217.07:48:41.87#ibcon#read 6, iclass 16, count 0 2006.217.07:48:41.87#ibcon#end of sib2, iclass 16, count 0 2006.217.07:48:41.87#ibcon#*after write, iclass 16, count 0 2006.217.07:48:41.87#ibcon#*before return 0, iclass 16, count 0 2006.217.07:48:41.87#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.217.07:48:41.87#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.217.07:48:41.87#ibcon#about to clear, iclass 16 cls_cnt 0 2006.217.07:48:41.87#ibcon#cleared, iclass 16 cls_cnt 0 2006.217.07:48:41.87$vc4f8/vblo=5,744.99 2006.217.07:48:41.87#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.217.07:48:41.87#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.217.07:48:41.87#ibcon#ireg 17 cls_cnt 0 2006.217.07:48:41.87#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.217.07:48:41.87#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.217.07:48:41.87#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.217.07:48:41.87#ibcon#enter wrdev, iclass 18, count 0 2006.217.07:48:41.87#ibcon#first serial, iclass 18, count 0 2006.217.07:48:41.87#ibcon#enter sib2, iclass 18, count 0 2006.217.07:48:41.87#ibcon#flushed, iclass 18, count 0 2006.217.07:48:41.87#ibcon#about to write, iclass 18, count 0 2006.217.07:48:41.87#ibcon#wrote, iclass 18, count 0 2006.217.07:48:41.87#ibcon#about to read 3, iclass 18, count 0 2006.217.07:48:41.90#ibcon#read 3, iclass 18, count 0 2006.217.07:48:41.90#ibcon#about to read 4, iclass 18, count 0 2006.217.07:48:41.90#ibcon#read 4, iclass 18, count 0 2006.217.07:48:41.90#ibcon#about to read 5, iclass 18, count 0 2006.217.07:48:41.90#ibcon#read 5, iclass 18, count 0 2006.217.07:48:41.90#ibcon#about to read 6, iclass 18, count 0 2006.217.07:48:41.90#ibcon#read 6, iclass 18, count 0 2006.217.07:48:41.90#ibcon#end of sib2, iclass 18, count 0 2006.217.07:48:41.90#ibcon#*mode == 0, iclass 18, count 0 2006.217.07:48:41.90#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.217.07:48:41.90#ibcon#[28=FRQ=05,744.99\r\n] 2006.217.07:48:41.90#ibcon#*before write, iclass 18, count 0 2006.217.07:48:41.90#ibcon#enter sib2, iclass 18, count 0 2006.217.07:48:41.90#ibcon#flushed, iclass 18, count 0 2006.217.07:48:41.90#ibcon#about to write, iclass 18, count 0 2006.217.07:48:41.90#ibcon#wrote, iclass 18, count 0 2006.217.07:48:41.90#ibcon#about to read 3, iclass 18, count 0 2006.217.07:48:41.94#ibcon#read 3, iclass 18, count 0 2006.217.07:48:41.94#ibcon#about to read 4, iclass 18, count 0 2006.217.07:48:41.94#ibcon#read 4, iclass 18, count 0 2006.217.07:48:41.94#ibcon#about to read 5, iclass 18, count 0 2006.217.07:48:41.94#ibcon#read 5, iclass 18, count 0 2006.217.07:48:41.94#ibcon#about to read 6, iclass 18, count 0 2006.217.07:48:41.94#ibcon#read 6, iclass 18, count 0 2006.217.07:48:41.94#ibcon#end of sib2, iclass 18, count 0 2006.217.07:48:41.94#ibcon#*after write, iclass 18, count 0 2006.217.07:48:41.94#ibcon#*before return 0, iclass 18, count 0 2006.217.07:48:41.94#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.217.07:48:41.94#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.217.07:48:41.94#ibcon#about to clear, iclass 18 cls_cnt 0 2006.217.07:48:41.94#ibcon#cleared, iclass 18 cls_cnt 0 2006.217.07:48:41.94$vc4f8/vb=5,4 2006.217.07:48:41.94#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.217.07:48:41.94#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.217.07:48:41.94#ibcon#ireg 11 cls_cnt 2 2006.217.07:48:41.94#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.217.07:48:41.99#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.217.07:48:41.99#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.217.07:48:41.99#ibcon#enter wrdev, iclass 20, count 2 2006.217.07:48:41.99#ibcon#first serial, iclass 20, count 2 2006.217.07:48:41.99#ibcon#enter sib2, iclass 20, count 2 2006.217.07:48:41.99#ibcon#flushed, iclass 20, count 2 2006.217.07:48:41.99#ibcon#about to write, iclass 20, count 2 2006.217.07:48:41.99#ibcon#wrote, iclass 20, count 2 2006.217.07:48:41.99#ibcon#about to read 3, iclass 20, count 2 2006.217.07:48:42.01#ibcon#read 3, iclass 20, count 2 2006.217.07:48:42.01#ibcon#about to read 4, iclass 20, count 2 2006.217.07:48:42.01#ibcon#read 4, iclass 20, count 2 2006.217.07:48:42.01#ibcon#about to read 5, iclass 20, count 2 2006.217.07:48:42.01#ibcon#read 5, iclass 20, count 2 2006.217.07:48:42.01#ibcon#about to read 6, iclass 20, count 2 2006.217.07:48:42.01#ibcon#read 6, iclass 20, count 2 2006.217.07:48:42.01#ibcon#end of sib2, iclass 20, count 2 2006.217.07:48:42.01#ibcon#*mode == 0, iclass 20, count 2 2006.217.07:48:42.01#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.217.07:48:42.01#ibcon#[27=AT05-04\r\n] 2006.217.07:48:42.01#ibcon#*before write, iclass 20, count 2 2006.217.07:48:42.01#ibcon#enter sib2, iclass 20, count 2 2006.217.07:48:42.01#ibcon#flushed, iclass 20, count 2 2006.217.07:48:42.01#ibcon#about to write, iclass 20, count 2 2006.217.07:48:42.01#ibcon#wrote, iclass 20, count 2 2006.217.07:48:42.01#ibcon#about to read 3, iclass 20, count 2 2006.217.07:48:42.04#ibcon#read 3, iclass 20, count 2 2006.217.07:48:42.04#ibcon#about to read 4, iclass 20, count 2 2006.217.07:48:42.04#ibcon#read 4, iclass 20, count 2 2006.217.07:48:42.04#ibcon#about to read 5, iclass 20, count 2 2006.217.07:48:42.04#ibcon#read 5, iclass 20, count 2 2006.217.07:48:42.04#ibcon#about to read 6, iclass 20, count 2 2006.217.07:48:42.04#ibcon#read 6, iclass 20, count 2 2006.217.07:48:42.04#ibcon#end of sib2, iclass 20, count 2 2006.217.07:48:42.04#ibcon#*after write, iclass 20, count 2 2006.217.07:48:42.04#ibcon#*before return 0, iclass 20, count 2 2006.217.07:48:42.04#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.217.07:48:42.04#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.217.07:48:42.04#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.217.07:48:42.04#ibcon#ireg 7 cls_cnt 0 2006.217.07:48:42.04#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.217.07:48:42.16#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.217.07:48:42.16#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.217.07:48:42.16#ibcon#enter wrdev, iclass 20, count 0 2006.217.07:48:42.16#ibcon#first serial, iclass 20, count 0 2006.217.07:48:42.16#ibcon#enter sib2, iclass 20, count 0 2006.217.07:48:42.16#ibcon#flushed, iclass 20, count 0 2006.217.07:48:42.16#ibcon#about to write, iclass 20, count 0 2006.217.07:48:42.16#ibcon#wrote, iclass 20, count 0 2006.217.07:48:42.16#ibcon#about to read 3, iclass 20, count 0 2006.217.07:48:42.18#ibcon#read 3, iclass 20, count 0 2006.217.07:48:42.18#ibcon#about to read 4, iclass 20, count 0 2006.217.07:48:42.18#ibcon#read 4, iclass 20, count 0 2006.217.07:48:42.18#ibcon#about to read 5, iclass 20, count 0 2006.217.07:48:42.18#ibcon#read 5, iclass 20, count 0 2006.217.07:48:42.18#ibcon#about to read 6, iclass 20, count 0 2006.217.07:48:42.18#ibcon#read 6, iclass 20, count 0 2006.217.07:48:42.18#ibcon#end of sib2, iclass 20, count 0 2006.217.07:48:42.18#ibcon#*mode == 0, iclass 20, count 0 2006.217.07:48:42.18#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.217.07:48:42.18#ibcon#[27=USB\r\n] 2006.217.07:48:42.18#ibcon#*before write, iclass 20, count 0 2006.217.07:48:42.18#ibcon#enter sib2, iclass 20, count 0 2006.217.07:48:42.18#ibcon#flushed, iclass 20, count 0 2006.217.07:48:42.18#ibcon#about to write, iclass 20, count 0 2006.217.07:48:42.18#ibcon#wrote, iclass 20, count 0 2006.217.07:48:42.18#ibcon#about to read 3, iclass 20, count 0 2006.217.07:48:42.21#ibcon#read 3, iclass 20, count 0 2006.217.07:48:42.21#ibcon#about to read 4, iclass 20, count 0 2006.217.07:48:42.21#ibcon#read 4, iclass 20, count 0 2006.217.07:48:42.21#ibcon#about to read 5, iclass 20, count 0 2006.217.07:48:42.21#ibcon#read 5, iclass 20, count 0 2006.217.07:48:42.21#ibcon#about to read 6, iclass 20, count 0 2006.217.07:48:42.21#ibcon#read 6, iclass 20, count 0 2006.217.07:48:42.21#ibcon#end of sib2, iclass 20, count 0 2006.217.07:48:42.21#ibcon#*after write, iclass 20, count 0 2006.217.07:48:42.21#ibcon#*before return 0, iclass 20, count 0 2006.217.07:48:42.21#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.217.07:48:42.21#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.217.07:48:42.21#ibcon#about to clear, iclass 20 cls_cnt 0 2006.217.07:48:42.21#ibcon#cleared, iclass 20 cls_cnt 0 2006.217.07:48:42.21$vc4f8/vblo=6,752.99 2006.217.07:48:42.21#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.217.07:48:42.21#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.217.07:48:42.21#ibcon#ireg 17 cls_cnt 0 2006.217.07:48:42.21#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.217.07:48:42.21#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.217.07:48:42.21#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.217.07:48:42.21#ibcon#enter wrdev, iclass 22, count 0 2006.217.07:48:42.21#ibcon#first serial, iclass 22, count 0 2006.217.07:48:42.21#ibcon#enter sib2, iclass 22, count 0 2006.217.07:48:42.21#ibcon#flushed, iclass 22, count 0 2006.217.07:48:42.21#ibcon#about to write, iclass 22, count 0 2006.217.07:48:42.21#ibcon#wrote, iclass 22, count 0 2006.217.07:48:42.21#ibcon#about to read 3, iclass 22, count 0 2006.217.07:48:42.23#ibcon#read 3, iclass 22, count 0 2006.217.07:48:42.23#ibcon#about to read 4, iclass 22, count 0 2006.217.07:48:42.23#ibcon#read 4, iclass 22, count 0 2006.217.07:48:42.23#ibcon#about to read 5, iclass 22, count 0 2006.217.07:48:42.23#ibcon#read 5, iclass 22, count 0 2006.217.07:48:42.23#ibcon#about to read 6, iclass 22, count 0 2006.217.07:48:42.23#ibcon#read 6, iclass 22, count 0 2006.217.07:48:42.23#ibcon#end of sib2, iclass 22, count 0 2006.217.07:48:42.23#ibcon#*mode == 0, iclass 22, count 0 2006.217.07:48:42.23#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.217.07:48:42.23#ibcon#[28=FRQ=06,752.99\r\n] 2006.217.07:48:42.23#ibcon#*before write, iclass 22, count 0 2006.217.07:48:42.23#ibcon#enter sib2, iclass 22, count 0 2006.217.07:48:42.23#ibcon#flushed, iclass 22, count 0 2006.217.07:48:42.23#ibcon#about to write, iclass 22, count 0 2006.217.07:48:42.23#ibcon#wrote, iclass 22, count 0 2006.217.07:48:42.23#ibcon#about to read 3, iclass 22, count 0 2006.217.07:48:42.27#ibcon#read 3, iclass 22, count 0 2006.217.07:48:42.27#ibcon#about to read 4, iclass 22, count 0 2006.217.07:48:42.27#ibcon#read 4, iclass 22, count 0 2006.217.07:48:42.27#ibcon#about to read 5, iclass 22, count 0 2006.217.07:48:42.27#ibcon#read 5, iclass 22, count 0 2006.217.07:48:42.27#ibcon#about to read 6, iclass 22, count 0 2006.217.07:48:42.27#ibcon#read 6, iclass 22, count 0 2006.217.07:48:42.27#ibcon#end of sib2, iclass 22, count 0 2006.217.07:48:42.27#ibcon#*after write, iclass 22, count 0 2006.217.07:48:42.27#ibcon#*before return 0, iclass 22, count 0 2006.217.07:48:42.27#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.217.07:48:42.27#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.217.07:48:42.27#ibcon#about to clear, iclass 22 cls_cnt 0 2006.217.07:48:42.27#ibcon#cleared, iclass 22 cls_cnt 0 2006.217.07:48:42.27$vc4f8/vb=6,4 2006.217.07:48:42.27#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.217.07:48:42.27#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.217.07:48:42.27#ibcon#ireg 11 cls_cnt 2 2006.217.07:48:42.27#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.217.07:48:42.33#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.217.07:48:42.33#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.217.07:48:42.33#ibcon#enter wrdev, iclass 24, count 2 2006.217.07:48:42.33#ibcon#first serial, iclass 24, count 2 2006.217.07:48:42.33#ibcon#enter sib2, iclass 24, count 2 2006.217.07:48:42.33#ibcon#flushed, iclass 24, count 2 2006.217.07:48:42.33#ibcon#about to write, iclass 24, count 2 2006.217.07:48:42.33#ibcon#wrote, iclass 24, count 2 2006.217.07:48:42.33#ibcon#about to read 3, iclass 24, count 2 2006.217.07:48:42.35#ibcon#read 3, iclass 24, count 2 2006.217.07:48:42.35#ibcon#about to read 4, iclass 24, count 2 2006.217.07:48:42.35#ibcon#read 4, iclass 24, count 2 2006.217.07:48:42.35#ibcon#about to read 5, iclass 24, count 2 2006.217.07:48:42.35#ibcon#read 5, iclass 24, count 2 2006.217.07:48:42.35#ibcon#about to read 6, iclass 24, count 2 2006.217.07:48:42.35#ibcon#read 6, iclass 24, count 2 2006.217.07:48:42.35#ibcon#end of sib2, iclass 24, count 2 2006.217.07:48:42.35#ibcon#*mode == 0, iclass 24, count 2 2006.217.07:48:42.35#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.217.07:48:42.35#ibcon#[27=AT06-04\r\n] 2006.217.07:48:42.35#ibcon#*before write, iclass 24, count 2 2006.217.07:48:42.35#ibcon#enter sib2, iclass 24, count 2 2006.217.07:48:42.35#ibcon#flushed, iclass 24, count 2 2006.217.07:48:42.35#ibcon#about to write, iclass 24, count 2 2006.217.07:48:42.35#ibcon#wrote, iclass 24, count 2 2006.217.07:48:42.35#ibcon#about to read 3, iclass 24, count 2 2006.217.07:48:42.38#ibcon#read 3, iclass 24, count 2 2006.217.07:48:42.38#ibcon#about to read 4, iclass 24, count 2 2006.217.07:48:42.38#ibcon#read 4, iclass 24, count 2 2006.217.07:48:42.38#ibcon#about to read 5, iclass 24, count 2 2006.217.07:48:42.38#ibcon#read 5, iclass 24, count 2 2006.217.07:48:42.38#ibcon#about to read 6, iclass 24, count 2 2006.217.07:48:42.38#ibcon#read 6, iclass 24, count 2 2006.217.07:48:42.38#ibcon#end of sib2, iclass 24, count 2 2006.217.07:48:42.38#ibcon#*after write, iclass 24, count 2 2006.217.07:48:42.38#ibcon#*before return 0, iclass 24, count 2 2006.217.07:48:42.38#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.217.07:48:42.38#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.217.07:48:42.38#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.217.07:48:42.38#ibcon#ireg 7 cls_cnt 0 2006.217.07:48:42.38#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.217.07:48:42.50#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.217.07:48:42.50#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.217.07:48:42.50#ibcon#enter wrdev, iclass 24, count 0 2006.217.07:48:42.50#ibcon#first serial, iclass 24, count 0 2006.217.07:48:42.50#ibcon#enter sib2, iclass 24, count 0 2006.217.07:48:42.50#ibcon#flushed, iclass 24, count 0 2006.217.07:48:42.50#ibcon#about to write, iclass 24, count 0 2006.217.07:48:42.50#ibcon#wrote, iclass 24, count 0 2006.217.07:48:42.50#ibcon#about to read 3, iclass 24, count 0 2006.217.07:48:42.52#ibcon#read 3, iclass 24, count 0 2006.217.07:48:42.52#ibcon#about to read 4, iclass 24, count 0 2006.217.07:48:42.52#ibcon#read 4, iclass 24, count 0 2006.217.07:48:42.52#ibcon#about to read 5, iclass 24, count 0 2006.217.07:48:42.52#ibcon#read 5, iclass 24, count 0 2006.217.07:48:42.52#ibcon#about to read 6, iclass 24, count 0 2006.217.07:48:42.52#ibcon#read 6, iclass 24, count 0 2006.217.07:48:42.52#ibcon#end of sib2, iclass 24, count 0 2006.217.07:48:42.52#ibcon#*mode == 0, iclass 24, count 0 2006.217.07:48:42.52#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.217.07:48:42.52#ibcon#[27=USB\r\n] 2006.217.07:48:42.52#ibcon#*before write, iclass 24, count 0 2006.217.07:48:42.52#ibcon#enter sib2, iclass 24, count 0 2006.217.07:48:42.52#ibcon#flushed, iclass 24, count 0 2006.217.07:48:42.52#ibcon#about to write, iclass 24, count 0 2006.217.07:48:42.52#ibcon#wrote, iclass 24, count 0 2006.217.07:48:42.52#ibcon#about to read 3, iclass 24, count 0 2006.217.07:48:42.55#ibcon#read 3, iclass 24, count 0 2006.217.07:48:42.55#ibcon#about to read 4, iclass 24, count 0 2006.217.07:48:42.55#ibcon#read 4, iclass 24, count 0 2006.217.07:48:42.55#ibcon#about to read 5, iclass 24, count 0 2006.217.07:48:42.55#ibcon#read 5, iclass 24, count 0 2006.217.07:48:42.55#ibcon#about to read 6, iclass 24, count 0 2006.217.07:48:42.55#ibcon#read 6, iclass 24, count 0 2006.217.07:48:42.55#ibcon#end of sib2, iclass 24, count 0 2006.217.07:48:42.55#ibcon#*after write, iclass 24, count 0 2006.217.07:48:42.55#ibcon#*before return 0, iclass 24, count 0 2006.217.07:48:42.55#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.217.07:48:42.55#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.217.07:48:42.55#ibcon#about to clear, iclass 24 cls_cnt 0 2006.217.07:48:42.55#ibcon#cleared, iclass 24 cls_cnt 0 2006.217.07:48:42.55$vc4f8/vabw=wide 2006.217.07:48:42.55#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.217.07:48:42.55#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.217.07:48:42.55#ibcon#ireg 8 cls_cnt 0 2006.217.07:48:42.55#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.217.07:48:42.55#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.217.07:48:42.55#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.217.07:48:42.55#ibcon#enter wrdev, iclass 26, count 0 2006.217.07:48:42.55#ibcon#first serial, iclass 26, count 0 2006.217.07:48:42.55#ibcon#enter sib2, iclass 26, count 0 2006.217.07:48:42.55#ibcon#flushed, iclass 26, count 0 2006.217.07:48:42.55#ibcon#about to write, iclass 26, count 0 2006.217.07:48:42.55#ibcon#wrote, iclass 26, count 0 2006.217.07:48:42.55#ibcon#about to read 3, iclass 26, count 0 2006.217.07:48:42.57#ibcon#read 3, iclass 26, count 0 2006.217.07:48:42.57#ibcon#about to read 4, iclass 26, count 0 2006.217.07:48:42.57#ibcon#read 4, iclass 26, count 0 2006.217.07:48:42.57#ibcon#about to read 5, iclass 26, count 0 2006.217.07:48:42.57#ibcon#read 5, iclass 26, count 0 2006.217.07:48:42.57#ibcon#about to read 6, iclass 26, count 0 2006.217.07:48:42.57#ibcon#read 6, iclass 26, count 0 2006.217.07:48:42.57#ibcon#end of sib2, iclass 26, count 0 2006.217.07:48:42.57#ibcon#*mode == 0, iclass 26, count 0 2006.217.07:48:42.57#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.217.07:48:42.57#ibcon#[25=BW32\r\n] 2006.217.07:48:42.57#ibcon#*before write, iclass 26, count 0 2006.217.07:48:42.57#ibcon#enter sib2, iclass 26, count 0 2006.217.07:48:42.57#ibcon#flushed, iclass 26, count 0 2006.217.07:48:42.57#ibcon#about to write, iclass 26, count 0 2006.217.07:48:42.57#ibcon#wrote, iclass 26, count 0 2006.217.07:48:42.57#ibcon#about to read 3, iclass 26, count 0 2006.217.07:48:42.60#ibcon#read 3, iclass 26, count 0 2006.217.07:48:42.60#ibcon#about to read 4, iclass 26, count 0 2006.217.07:48:42.60#ibcon#read 4, iclass 26, count 0 2006.217.07:48:42.60#ibcon#about to read 5, iclass 26, count 0 2006.217.07:48:42.60#ibcon#read 5, iclass 26, count 0 2006.217.07:48:42.60#ibcon#about to read 6, iclass 26, count 0 2006.217.07:48:42.60#ibcon#read 6, iclass 26, count 0 2006.217.07:48:42.60#ibcon#end of sib2, iclass 26, count 0 2006.217.07:48:42.60#ibcon#*after write, iclass 26, count 0 2006.217.07:48:42.60#ibcon#*before return 0, iclass 26, count 0 2006.217.07:48:42.60#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.217.07:48:42.60#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.217.07:48:42.60#ibcon#about to clear, iclass 26 cls_cnt 0 2006.217.07:48:42.60#ibcon#cleared, iclass 26 cls_cnt 0 2006.217.07:48:42.60$vc4f8/vbbw=wide 2006.217.07:48:42.60#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.217.07:48:42.60#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.217.07:48:42.60#ibcon#ireg 8 cls_cnt 0 2006.217.07:48:42.60#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.217.07:48:42.67#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.217.07:48:42.67#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.217.07:48:42.67#ibcon#enter wrdev, iclass 28, count 0 2006.217.07:48:42.67#ibcon#first serial, iclass 28, count 0 2006.217.07:48:42.67#ibcon#enter sib2, iclass 28, count 0 2006.217.07:48:42.67#ibcon#flushed, iclass 28, count 0 2006.217.07:48:42.67#ibcon#about to write, iclass 28, count 0 2006.217.07:48:42.67#ibcon#wrote, iclass 28, count 0 2006.217.07:48:42.67#ibcon#about to read 3, iclass 28, count 0 2006.217.07:48:42.69#ibcon#read 3, iclass 28, count 0 2006.217.07:48:42.69#ibcon#about to read 4, iclass 28, count 0 2006.217.07:48:42.69#ibcon#read 4, iclass 28, count 0 2006.217.07:48:42.69#ibcon#about to read 5, iclass 28, count 0 2006.217.07:48:42.69#ibcon#read 5, iclass 28, count 0 2006.217.07:48:42.69#ibcon#about to read 6, iclass 28, count 0 2006.217.07:48:42.69#ibcon#read 6, iclass 28, count 0 2006.217.07:48:42.69#ibcon#end of sib2, iclass 28, count 0 2006.217.07:48:42.69#ibcon#*mode == 0, iclass 28, count 0 2006.217.07:48:42.69#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.217.07:48:42.69#ibcon#[27=BW32\r\n] 2006.217.07:48:42.69#ibcon#*before write, iclass 28, count 0 2006.217.07:48:42.69#ibcon#enter sib2, iclass 28, count 0 2006.217.07:48:42.69#ibcon#flushed, iclass 28, count 0 2006.217.07:48:42.69#ibcon#about to write, iclass 28, count 0 2006.217.07:48:42.69#ibcon#wrote, iclass 28, count 0 2006.217.07:48:42.69#ibcon#about to read 3, iclass 28, count 0 2006.217.07:48:42.72#ibcon#read 3, iclass 28, count 0 2006.217.07:48:42.72#ibcon#about to read 4, iclass 28, count 0 2006.217.07:48:42.72#ibcon#read 4, iclass 28, count 0 2006.217.07:48:42.72#ibcon#about to read 5, iclass 28, count 0 2006.217.07:48:42.72#ibcon#read 5, iclass 28, count 0 2006.217.07:48:42.72#ibcon#about to read 6, iclass 28, count 0 2006.217.07:48:42.72#ibcon#read 6, iclass 28, count 0 2006.217.07:48:42.72#ibcon#end of sib2, iclass 28, count 0 2006.217.07:48:42.72#ibcon#*after write, iclass 28, count 0 2006.217.07:48:42.72#ibcon#*before return 0, iclass 28, count 0 2006.217.07:48:42.72#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.217.07:48:42.72#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.217.07:48:42.72#ibcon#about to clear, iclass 28 cls_cnt 0 2006.217.07:48:42.72#ibcon#cleared, iclass 28 cls_cnt 0 2006.217.07:48:42.72$4f8m12a/ifd4f 2006.217.07:48:42.72$ifd4f/lo= 2006.217.07:48:42.72$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.217.07:48:42.72$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.217.07:48:42.72$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.217.07:48:42.72$ifd4f/patch= 2006.217.07:48:42.72$ifd4f/patch=lo1,a1,a2,a3,a4 2006.217.07:48:42.72$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.217.07:48:42.72$ifd4f/patch=lo3,a5,a6,a7,a8 2006.217.07:48:42.72$4f8m12a/"form=m,16.000,1:2 2006.217.07:48:42.72$4f8m12a/"tpicd 2006.217.07:48:42.72$4f8m12a/echo=off 2006.217.07:48:42.73$4f8m12a/xlog=off 2006.217.07:48:42.73:!2006.217.07:49:10 2006.217.07:48:51.14#trakl#Source acquired 2006.217.07:48:51.14#flagr#flagr/antenna,acquired 2006.217.07:49:10.01:preob 2006.217.07:49:11.13/onsource/TRACKING 2006.217.07:49:11.13:!2006.217.07:49:20 2006.217.07:49:20.00:data_valid=on 2006.217.07:49:20.00:midob 2006.217.07:49:20.13/onsource/TRACKING 2006.217.07:49:20.13/wx/31.25,1008.6,63 2006.217.07:49:20.21/cable/+6.3859E-03 2006.217.07:49:21.30/va/01,05,usb,yes,37,39 2006.217.07:49:21.30/va/02,04,usb,yes,34,36 2006.217.07:49:21.30/va/03,04,usb,yes,32,33 2006.217.07:49:21.30/va/04,04,usb,yes,36,39 2006.217.07:49:21.30/va/05,07,usb,yes,39,41 2006.217.07:49:21.30/va/06,06,usb,yes,38,38 2006.217.07:49:21.30/va/07,06,usb,yes,38,38 2006.217.07:49:21.30/va/08,07,usb,yes,36,36 2006.217.07:49:21.53/valo/01,532.99,yes,locked 2006.217.07:49:21.53/valo/02,572.99,yes,locked 2006.217.07:49:21.53/valo/03,672.99,yes,locked 2006.217.07:49:21.53/valo/04,832.99,yes,locked 2006.217.07:49:21.53/valo/05,652.99,yes,locked 2006.217.07:49:21.53/valo/06,772.99,yes,locked 2006.217.07:49:21.53/valo/07,832.99,yes,locked 2006.217.07:49:21.53/valo/08,852.99,yes,locked 2006.217.07:49:22.62/vb/01,04,usb,yes,33,32 2006.217.07:49:22.62/vb/02,04,usb,yes,35,36 2006.217.07:49:22.62/vb/03,04,usb,yes,31,35 2006.217.07:49:22.62/vb/04,04,usb,yes,32,32 2006.217.07:49:22.62/vb/05,04,usb,yes,30,35 2006.217.07:49:22.62/vb/06,04,usb,yes,31,35 2006.217.07:49:22.62/vb/07,04,usb,yes,34,34 2006.217.07:49:22.62/vb/08,04,usb,yes,31,35 2006.217.07:49:22.86/vblo/01,632.99,yes,locked 2006.217.07:49:22.86/vblo/02,640.99,yes,locked 2006.217.07:49:22.86/vblo/03,656.99,yes,locked 2006.217.07:49:22.86/vblo/04,712.99,yes,locked 2006.217.07:49:22.86/vblo/05,744.99,yes,locked 2006.217.07:49:22.86/vblo/06,752.99,yes,locked 2006.217.07:49:22.86/vblo/07,734.99,yes,locked 2006.217.07:49:22.86/vblo/08,744.99,yes,locked 2006.217.07:49:23.01/vabw/8 2006.217.07:49:23.16/vbbw/8 2006.217.07:49:23.25/xfe/off,on,14.7 2006.217.07:49:23.63/ifatt/23,28,28,28 2006.217.07:49:24.07/fmout-gps/S +4.17E-07 2006.217.07:49:24.11:!2006.217.07:50:20 2006.217.07:50:20.00:data_valid=off 2006.217.07:50:20.01:postob 2006.217.07:50:20.18/cable/+6.3866E-03 2006.217.07:50:20.19/wx/31.23,1008.6,64 2006.217.07:50:21.07/fmout-gps/S +4.16E-07 2006.217.07:50:21.08:scan_name=217-0751,k06217,60 2006.217.07:50:21.08:source=0804+499,080839.67,495036.5,2000.0,ccw 2006.217.07:50:22.13#flagr#flagr/antenna,new-source 2006.217.07:50:22.14:checkk5 2006.217.07:50:22.51/chk_autoobs//k5ts1/ autoobs is running! 2006.217.07:50:22.89/chk_autoobs//k5ts2/ autoobs is running! 2006.217.07:50:23.27/chk_autoobs//k5ts3/ autoobs is running! 2006.217.07:50:23.65/chk_autoobs//k5ts4/ autoobs is running! 2006.217.07:50:24.02/chk_obsdata//k5ts1/T2170749??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:50:24.38/chk_obsdata//k5ts2/T2170749??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:50:24.75/chk_obsdata//k5ts3/T2170749??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:50:25.12/chk_obsdata//k5ts4/T2170749??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:50:25.82/k5log//k5ts1_log_newline 2006.217.07:50:26.51/k5log//k5ts2_log_newline 2006.217.07:50:27.20/k5log//k5ts3_log_newline 2006.217.07:50:27.89/k5log//k5ts4_log_newline 2006.217.07:50:27.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.217.07:50:27.92:4f8m12a=1 2006.217.07:50:27.92$4f8m12a/echo=on 2006.217.07:50:27.92$4f8m12a/pcalon 2006.217.07:50:27.92$pcalon/"no phase cal control is implemented here 2006.217.07:50:27.92$4f8m12a/"tpicd=stop 2006.217.07:50:27.92$4f8m12a/vc4f8 2006.217.07:50:27.92$vc4f8/valo=1,532.99 2006.217.07:50:27.92#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.217.07:50:27.92#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.217.07:50:27.92#ibcon#ireg 17 cls_cnt 0 2006.217.07:50:27.92#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.217.07:50:27.92#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.217.07:50:27.92#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.217.07:50:27.92#ibcon#enter wrdev, iclass 35, count 0 2006.217.07:50:27.92#ibcon#first serial, iclass 35, count 0 2006.217.07:50:27.92#ibcon#enter sib2, iclass 35, count 0 2006.217.07:50:27.92#ibcon#flushed, iclass 35, count 0 2006.217.07:50:27.92#ibcon#about to write, iclass 35, count 0 2006.217.07:50:27.92#ibcon#wrote, iclass 35, count 0 2006.217.07:50:27.92#ibcon#about to read 3, iclass 35, count 0 2006.217.07:50:27.93#ibcon#read 3, iclass 35, count 0 2006.217.07:50:27.93#ibcon#about to read 4, iclass 35, count 0 2006.217.07:50:27.93#ibcon#read 4, iclass 35, count 0 2006.217.07:50:27.93#ibcon#about to read 5, iclass 35, count 0 2006.217.07:50:27.93#ibcon#read 5, iclass 35, count 0 2006.217.07:50:27.93#ibcon#about to read 6, iclass 35, count 0 2006.217.07:50:27.93#ibcon#read 6, iclass 35, count 0 2006.217.07:50:27.93#ibcon#end of sib2, iclass 35, count 0 2006.217.07:50:27.93#ibcon#*mode == 0, iclass 35, count 0 2006.217.07:50:27.93#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.217.07:50:27.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.217.07:50:27.93#ibcon#*before write, iclass 35, count 0 2006.217.07:50:27.93#ibcon#enter sib2, iclass 35, count 0 2006.217.07:50:27.93#ibcon#flushed, iclass 35, count 0 2006.217.07:50:27.93#ibcon#about to write, iclass 35, count 0 2006.217.07:50:27.93#ibcon#wrote, iclass 35, count 0 2006.217.07:50:27.93#ibcon#about to read 3, iclass 35, count 0 2006.217.07:50:27.98#ibcon#read 3, iclass 35, count 0 2006.217.07:50:27.98#ibcon#about to read 4, iclass 35, count 0 2006.217.07:50:27.98#ibcon#read 4, iclass 35, count 0 2006.217.07:50:27.98#ibcon#about to read 5, iclass 35, count 0 2006.217.07:50:27.98#ibcon#read 5, iclass 35, count 0 2006.217.07:50:27.98#ibcon#about to read 6, iclass 35, count 0 2006.217.07:50:27.98#ibcon#read 6, iclass 35, count 0 2006.217.07:50:27.98#ibcon#end of sib2, iclass 35, count 0 2006.217.07:50:27.98#ibcon#*after write, iclass 35, count 0 2006.217.07:50:27.98#ibcon#*before return 0, iclass 35, count 0 2006.217.07:50:27.98#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.217.07:50:27.98#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.217.07:50:27.98#ibcon#about to clear, iclass 35 cls_cnt 0 2006.217.07:50:27.98#ibcon#cleared, iclass 35 cls_cnt 0 2006.217.07:50:27.98$vc4f8/va=1,5 2006.217.07:50:27.98#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.217.07:50:27.98#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.217.07:50:27.98#ibcon#ireg 11 cls_cnt 2 2006.217.07:50:27.98#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.217.07:50:27.98#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.217.07:50:27.98#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.217.07:50:27.98#ibcon#enter wrdev, iclass 37, count 2 2006.217.07:50:27.98#ibcon#first serial, iclass 37, count 2 2006.217.07:50:27.98#ibcon#enter sib2, iclass 37, count 2 2006.217.07:50:27.98#ibcon#flushed, iclass 37, count 2 2006.217.07:50:27.98#ibcon#about to write, iclass 37, count 2 2006.217.07:50:27.98#ibcon#wrote, iclass 37, count 2 2006.217.07:50:27.98#ibcon#about to read 3, iclass 37, count 2 2006.217.07:50:28.00#ibcon#read 3, iclass 37, count 2 2006.217.07:50:28.00#ibcon#about to read 4, iclass 37, count 2 2006.217.07:50:28.00#ibcon#read 4, iclass 37, count 2 2006.217.07:50:28.00#ibcon#about to read 5, iclass 37, count 2 2006.217.07:50:28.00#ibcon#read 5, iclass 37, count 2 2006.217.07:50:28.00#ibcon#about to read 6, iclass 37, count 2 2006.217.07:50:28.00#ibcon#read 6, iclass 37, count 2 2006.217.07:50:28.00#ibcon#end of sib2, iclass 37, count 2 2006.217.07:50:28.00#ibcon#*mode == 0, iclass 37, count 2 2006.217.07:50:28.00#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.217.07:50:28.00#ibcon#[25=AT01-05\r\n] 2006.217.07:50:28.00#ibcon#*before write, iclass 37, count 2 2006.217.07:50:28.00#ibcon#enter sib2, iclass 37, count 2 2006.217.07:50:28.00#ibcon#flushed, iclass 37, count 2 2006.217.07:50:28.00#ibcon#about to write, iclass 37, count 2 2006.217.07:50:28.00#ibcon#wrote, iclass 37, count 2 2006.217.07:50:28.00#ibcon#about to read 3, iclass 37, count 2 2006.217.07:50:28.04#ibcon#read 3, iclass 37, count 2 2006.217.07:50:28.04#ibcon#about to read 4, iclass 37, count 2 2006.217.07:50:28.04#ibcon#read 4, iclass 37, count 2 2006.217.07:50:28.04#ibcon#about to read 5, iclass 37, count 2 2006.217.07:50:28.04#ibcon#read 5, iclass 37, count 2 2006.217.07:50:28.04#ibcon#about to read 6, iclass 37, count 2 2006.217.07:50:28.04#ibcon#read 6, iclass 37, count 2 2006.217.07:50:28.04#ibcon#end of sib2, iclass 37, count 2 2006.217.07:50:28.04#ibcon#*after write, iclass 37, count 2 2006.217.07:50:28.04#ibcon#*before return 0, iclass 37, count 2 2006.217.07:50:28.04#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.217.07:50:28.04#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.217.07:50:28.04#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.217.07:50:28.04#ibcon#ireg 7 cls_cnt 0 2006.217.07:50:28.04#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.217.07:50:28.15#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.217.07:50:28.15#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.217.07:50:28.15#ibcon#enter wrdev, iclass 37, count 0 2006.217.07:50:28.15#ibcon#first serial, iclass 37, count 0 2006.217.07:50:28.15#ibcon#enter sib2, iclass 37, count 0 2006.217.07:50:28.15#ibcon#flushed, iclass 37, count 0 2006.217.07:50:28.15#ibcon#about to write, iclass 37, count 0 2006.217.07:50:28.15#ibcon#wrote, iclass 37, count 0 2006.217.07:50:28.15#ibcon#about to read 3, iclass 37, count 0 2006.217.07:50:28.17#ibcon#read 3, iclass 37, count 0 2006.217.07:50:28.17#ibcon#about to read 4, iclass 37, count 0 2006.217.07:50:28.17#ibcon#read 4, iclass 37, count 0 2006.217.07:50:28.17#ibcon#about to read 5, iclass 37, count 0 2006.217.07:50:28.17#ibcon#read 5, iclass 37, count 0 2006.217.07:50:28.17#ibcon#about to read 6, iclass 37, count 0 2006.217.07:50:28.17#ibcon#read 6, iclass 37, count 0 2006.217.07:50:28.17#ibcon#end of sib2, iclass 37, count 0 2006.217.07:50:28.17#ibcon#*mode == 0, iclass 37, count 0 2006.217.07:50:28.17#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.217.07:50:28.17#ibcon#[25=USB\r\n] 2006.217.07:50:28.17#ibcon#*before write, iclass 37, count 0 2006.217.07:50:28.17#ibcon#enter sib2, iclass 37, count 0 2006.217.07:50:28.17#ibcon#flushed, iclass 37, count 0 2006.217.07:50:28.17#ibcon#about to write, iclass 37, count 0 2006.217.07:50:28.17#ibcon#wrote, iclass 37, count 0 2006.217.07:50:28.17#ibcon#about to read 3, iclass 37, count 0 2006.217.07:50:28.20#ibcon#read 3, iclass 37, count 0 2006.217.07:50:28.20#ibcon#about to read 4, iclass 37, count 0 2006.217.07:50:28.20#ibcon#read 4, iclass 37, count 0 2006.217.07:50:28.20#ibcon#about to read 5, iclass 37, count 0 2006.217.07:50:28.20#ibcon#read 5, iclass 37, count 0 2006.217.07:50:28.20#ibcon#about to read 6, iclass 37, count 0 2006.217.07:50:28.20#ibcon#read 6, iclass 37, count 0 2006.217.07:50:28.20#ibcon#end of sib2, iclass 37, count 0 2006.217.07:50:28.20#ibcon#*after write, iclass 37, count 0 2006.217.07:50:28.20#ibcon#*before return 0, iclass 37, count 0 2006.217.07:50:28.20#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.217.07:50:28.20#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.217.07:50:28.20#ibcon#about to clear, iclass 37 cls_cnt 0 2006.217.07:50:28.20#ibcon#cleared, iclass 37 cls_cnt 0 2006.217.07:50:28.20$vc4f8/valo=2,572.99 2006.217.07:50:28.20#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.217.07:50:28.20#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.217.07:50:28.20#ibcon#ireg 17 cls_cnt 0 2006.217.07:50:28.20#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.217.07:50:28.20#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.217.07:50:28.20#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.217.07:50:28.20#ibcon#enter wrdev, iclass 39, count 0 2006.217.07:50:28.20#ibcon#first serial, iclass 39, count 0 2006.217.07:50:28.20#ibcon#enter sib2, iclass 39, count 0 2006.217.07:50:28.20#ibcon#flushed, iclass 39, count 0 2006.217.07:50:28.20#ibcon#about to write, iclass 39, count 0 2006.217.07:50:28.20#ibcon#wrote, iclass 39, count 0 2006.217.07:50:28.20#ibcon#about to read 3, iclass 39, count 0 2006.217.07:50:28.23#ibcon#read 3, iclass 39, count 0 2006.217.07:50:28.23#ibcon#about to read 4, iclass 39, count 0 2006.217.07:50:28.23#ibcon#read 4, iclass 39, count 0 2006.217.07:50:28.23#ibcon#about to read 5, iclass 39, count 0 2006.217.07:50:28.23#ibcon#read 5, iclass 39, count 0 2006.217.07:50:28.23#ibcon#about to read 6, iclass 39, count 0 2006.217.07:50:28.23#ibcon#read 6, iclass 39, count 0 2006.217.07:50:28.23#ibcon#end of sib2, iclass 39, count 0 2006.217.07:50:28.23#ibcon#*mode == 0, iclass 39, count 0 2006.217.07:50:28.23#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.217.07:50:28.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.217.07:50:28.23#ibcon#*before write, iclass 39, count 0 2006.217.07:50:28.23#ibcon#enter sib2, iclass 39, count 0 2006.217.07:50:28.23#ibcon#flushed, iclass 39, count 0 2006.217.07:50:28.23#ibcon#about to write, iclass 39, count 0 2006.217.07:50:28.23#ibcon#wrote, iclass 39, count 0 2006.217.07:50:28.23#ibcon#about to read 3, iclass 39, count 0 2006.217.07:50:28.27#ibcon#read 3, iclass 39, count 0 2006.217.07:50:28.27#ibcon#about to read 4, iclass 39, count 0 2006.217.07:50:28.27#ibcon#read 4, iclass 39, count 0 2006.217.07:50:28.27#ibcon#about to read 5, iclass 39, count 0 2006.217.07:50:28.27#ibcon#read 5, iclass 39, count 0 2006.217.07:50:28.27#ibcon#about to read 6, iclass 39, count 0 2006.217.07:50:28.27#ibcon#read 6, iclass 39, count 0 2006.217.07:50:28.27#ibcon#end of sib2, iclass 39, count 0 2006.217.07:50:28.27#ibcon#*after write, iclass 39, count 0 2006.217.07:50:28.27#ibcon#*before return 0, iclass 39, count 0 2006.217.07:50:28.27#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.217.07:50:28.27#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.217.07:50:28.27#ibcon#about to clear, iclass 39 cls_cnt 0 2006.217.07:50:28.27#ibcon#cleared, iclass 39 cls_cnt 0 2006.217.07:50:28.27$vc4f8/va=2,4 2006.217.07:50:28.27#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.217.07:50:28.27#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.217.07:50:28.27#ibcon#ireg 11 cls_cnt 2 2006.217.07:50:28.27#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.217.07:50:28.32#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.217.07:50:28.32#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.217.07:50:28.32#ibcon#enter wrdev, iclass 3, count 2 2006.217.07:50:28.32#ibcon#first serial, iclass 3, count 2 2006.217.07:50:28.32#ibcon#enter sib2, iclass 3, count 2 2006.217.07:50:28.32#ibcon#flushed, iclass 3, count 2 2006.217.07:50:28.32#ibcon#about to write, iclass 3, count 2 2006.217.07:50:28.32#ibcon#wrote, iclass 3, count 2 2006.217.07:50:28.32#ibcon#about to read 3, iclass 3, count 2 2006.217.07:50:28.34#ibcon#read 3, iclass 3, count 2 2006.217.07:50:28.34#ibcon#about to read 4, iclass 3, count 2 2006.217.07:50:28.34#ibcon#read 4, iclass 3, count 2 2006.217.07:50:28.34#ibcon#about to read 5, iclass 3, count 2 2006.217.07:50:28.34#ibcon#read 5, iclass 3, count 2 2006.217.07:50:28.34#ibcon#about to read 6, iclass 3, count 2 2006.217.07:50:28.34#ibcon#read 6, iclass 3, count 2 2006.217.07:50:28.34#ibcon#end of sib2, iclass 3, count 2 2006.217.07:50:28.34#ibcon#*mode == 0, iclass 3, count 2 2006.217.07:50:28.34#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.217.07:50:28.34#ibcon#[25=AT02-04\r\n] 2006.217.07:50:28.34#ibcon#*before write, iclass 3, count 2 2006.217.07:50:28.34#ibcon#enter sib2, iclass 3, count 2 2006.217.07:50:28.34#ibcon#flushed, iclass 3, count 2 2006.217.07:50:28.34#ibcon#about to write, iclass 3, count 2 2006.217.07:50:28.34#ibcon#wrote, iclass 3, count 2 2006.217.07:50:28.34#ibcon#about to read 3, iclass 3, count 2 2006.217.07:50:28.37#ibcon#read 3, iclass 3, count 2 2006.217.07:50:28.37#ibcon#about to read 4, iclass 3, count 2 2006.217.07:50:28.37#ibcon#read 4, iclass 3, count 2 2006.217.07:50:28.37#ibcon#about to read 5, iclass 3, count 2 2006.217.07:50:28.37#ibcon#read 5, iclass 3, count 2 2006.217.07:50:28.37#ibcon#about to read 6, iclass 3, count 2 2006.217.07:50:28.37#ibcon#read 6, iclass 3, count 2 2006.217.07:50:28.37#ibcon#end of sib2, iclass 3, count 2 2006.217.07:50:28.37#ibcon#*after write, iclass 3, count 2 2006.217.07:50:28.37#ibcon#*before return 0, iclass 3, count 2 2006.217.07:50:28.37#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.217.07:50:28.37#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.217.07:50:28.37#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.217.07:50:28.37#ibcon#ireg 7 cls_cnt 0 2006.217.07:50:28.37#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.217.07:50:28.49#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.217.07:50:28.49#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.217.07:50:28.49#ibcon#enter wrdev, iclass 3, count 0 2006.217.07:50:28.49#ibcon#first serial, iclass 3, count 0 2006.217.07:50:28.49#ibcon#enter sib2, iclass 3, count 0 2006.217.07:50:28.49#ibcon#flushed, iclass 3, count 0 2006.217.07:50:28.49#ibcon#about to write, iclass 3, count 0 2006.217.07:50:28.49#ibcon#wrote, iclass 3, count 0 2006.217.07:50:28.49#ibcon#about to read 3, iclass 3, count 0 2006.217.07:50:28.51#ibcon#read 3, iclass 3, count 0 2006.217.07:50:28.51#ibcon#about to read 4, iclass 3, count 0 2006.217.07:50:28.51#ibcon#read 4, iclass 3, count 0 2006.217.07:50:28.51#ibcon#about to read 5, iclass 3, count 0 2006.217.07:50:28.51#ibcon#read 5, iclass 3, count 0 2006.217.07:50:28.51#ibcon#about to read 6, iclass 3, count 0 2006.217.07:50:28.51#ibcon#read 6, iclass 3, count 0 2006.217.07:50:28.51#ibcon#end of sib2, iclass 3, count 0 2006.217.07:50:28.51#ibcon#*mode == 0, iclass 3, count 0 2006.217.07:50:28.51#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.217.07:50:28.51#ibcon#[25=USB\r\n] 2006.217.07:50:28.51#ibcon#*before write, iclass 3, count 0 2006.217.07:50:28.51#ibcon#enter sib2, iclass 3, count 0 2006.217.07:50:28.51#ibcon#flushed, iclass 3, count 0 2006.217.07:50:28.51#ibcon#about to write, iclass 3, count 0 2006.217.07:50:28.51#ibcon#wrote, iclass 3, count 0 2006.217.07:50:28.51#ibcon#about to read 3, iclass 3, count 0 2006.217.07:50:28.54#ibcon#read 3, iclass 3, count 0 2006.217.07:50:28.54#ibcon#about to read 4, iclass 3, count 0 2006.217.07:50:28.54#ibcon#read 4, iclass 3, count 0 2006.217.07:50:28.54#ibcon#about to read 5, iclass 3, count 0 2006.217.07:50:28.54#ibcon#read 5, iclass 3, count 0 2006.217.07:50:28.54#ibcon#about to read 6, iclass 3, count 0 2006.217.07:50:28.54#ibcon#read 6, iclass 3, count 0 2006.217.07:50:28.54#ibcon#end of sib2, iclass 3, count 0 2006.217.07:50:28.54#ibcon#*after write, iclass 3, count 0 2006.217.07:50:28.54#ibcon#*before return 0, iclass 3, count 0 2006.217.07:50:28.54#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.217.07:50:28.54#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.217.07:50:28.54#ibcon#about to clear, iclass 3 cls_cnt 0 2006.217.07:50:28.54#ibcon#cleared, iclass 3 cls_cnt 0 2006.217.07:50:28.54$vc4f8/valo=3,672.99 2006.217.07:50:28.54#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.217.07:50:28.54#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.217.07:50:28.54#ibcon#ireg 17 cls_cnt 0 2006.217.07:50:28.54#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.217.07:50:28.54#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.217.07:50:28.54#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.217.07:50:28.54#ibcon#enter wrdev, iclass 5, count 0 2006.217.07:50:28.54#ibcon#first serial, iclass 5, count 0 2006.217.07:50:28.54#ibcon#enter sib2, iclass 5, count 0 2006.217.07:50:28.54#ibcon#flushed, iclass 5, count 0 2006.217.07:50:28.54#ibcon#about to write, iclass 5, count 0 2006.217.07:50:28.54#ibcon#wrote, iclass 5, count 0 2006.217.07:50:28.54#ibcon#about to read 3, iclass 5, count 0 2006.217.07:50:28.57#ibcon#read 3, iclass 5, count 0 2006.217.07:50:28.57#ibcon#about to read 4, iclass 5, count 0 2006.217.07:50:28.57#ibcon#read 4, iclass 5, count 0 2006.217.07:50:28.57#ibcon#about to read 5, iclass 5, count 0 2006.217.07:50:28.57#ibcon#read 5, iclass 5, count 0 2006.217.07:50:28.57#ibcon#about to read 6, iclass 5, count 0 2006.217.07:50:28.57#ibcon#read 6, iclass 5, count 0 2006.217.07:50:28.57#ibcon#end of sib2, iclass 5, count 0 2006.217.07:50:28.57#ibcon#*mode == 0, iclass 5, count 0 2006.217.07:50:28.57#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.217.07:50:28.57#ibcon#[26=FRQ=03,672.99\r\n] 2006.217.07:50:28.57#ibcon#*before write, iclass 5, count 0 2006.217.07:50:28.57#ibcon#enter sib2, iclass 5, count 0 2006.217.07:50:28.57#ibcon#flushed, iclass 5, count 0 2006.217.07:50:28.57#ibcon#about to write, iclass 5, count 0 2006.217.07:50:28.57#ibcon#wrote, iclass 5, count 0 2006.217.07:50:28.57#ibcon#about to read 3, iclass 5, count 0 2006.217.07:50:28.61#ibcon#read 3, iclass 5, count 0 2006.217.07:50:28.61#ibcon#about to read 4, iclass 5, count 0 2006.217.07:50:28.61#ibcon#read 4, iclass 5, count 0 2006.217.07:50:28.61#ibcon#about to read 5, iclass 5, count 0 2006.217.07:50:28.61#ibcon#read 5, iclass 5, count 0 2006.217.07:50:28.61#ibcon#about to read 6, iclass 5, count 0 2006.217.07:50:28.61#ibcon#read 6, iclass 5, count 0 2006.217.07:50:28.61#ibcon#end of sib2, iclass 5, count 0 2006.217.07:50:28.61#ibcon#*after write, iclass 5, count 0 2006.217.07:50:28.61#ibcon#*before return 0, iclass 5, count 0 2006.217.07:50:28.61#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.217.07:50:28.61#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.217.07:50:28.61#ibcon#about to clear, iclass 5 cls_cnt 0 2006.217.07:50:28.61#ibcon#cleared, iclass 5 cls_cnt 0 2006.217.07:50:28.61$vc4f8/va=3,4 2006.217.07:50:28.61#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.217.07:50:28.61#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.217.07:50:28.61#ibcon#ireg 11 cls_cnt 2 2006.217.07:50:28.61#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.217.07:50:28.66#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.217.07:50:28.66#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.217.07:50:28.66#ibcon#enter wrdev, iclass 7, count 2 2006.217.07:50:28.66#ibcon#first serial, iclass 7, count 2 2006.217.07:50:28.66#ibcon#enter sib2, iclass 7, count 2 2006.217.07:50:28.66#ibcon#flushed, iclass 7, count 2 2006.217.07:50:28.66#ibcon#about to write, iclass 7, count 2 2006.217.07:50:28.66#ibcon#wrote, iclass 7, count 2 2006.217.07:50:28.66#ibcon#about to read 3, iclass 7, count 2 2006.217.07:50:28.68#ibcon#read 3, iclass 7, count 2 2006.217.07:50:28.68#ibcon#about to read 4, iclass 7, count 2 2006.217.07:50:28.68#ibcon#read 4, iclass 7, count 2 2006.217.07:50:28.68#ibcon#about to read 5, iclass 7, count 2 2006.217.07:50:28.68#ibcon#read 5, iclass 7, count 2 2006.217.07:50:28.68#ibcon#about to read 6, iclass 7, count 2 2006.217.07:50:28.68#ibcon#read 6, iclass 7, count 2 2006.217.07:50:28.68#ibcon#end of sib2, iclass 7, count 2 2006.217.07:50:28.68#ibcon#*mode == 0, iclass 7, count 2 2006.217.07:50:28.68#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.217.07:50:28.68#ibcon#[25=AT03-04\r\n] 2006.217.07:50:28.68#ibcon#*before write, iclass 7, count 2 2006.217.07:50:28.68#ibcon#enter sib2, iclass 7, count 2 2006.217.07:50:28.68#ibcon#flushed, iclass 7, count 2 2006.217.07:50:28.68#ibcon#about to write, iclass 7, count 2 2006.217.07:50:28.68#ibcon#wrote, iclass 7, count 2 2006.217.07:50:28.68#ibcon#about to read 3, iclass 7, count 2 2006.217.07:50:28.71#ibcon#read 3, iclass 7, count 2 2006.217.07:50:28.71#ibcon#about to read 4, iclass 7, count 2 2006.217.07:50:28.71#ibcon#read 4, iclass 7, count 2 2006.217.07:50:28.71#ibcon#about to read 5, iclass 7, count 2 2006.217.07:50:28.71#ibcon#read 5, iclass 7, count 2 2006.217.07:50:28.71#ibcon#about to read 6, iclass 7, count 2 2006.217.07:50:28.71#ibcon#read 6, iclass 7, count 2 2006.217.07:50:28.71#ibcon#end of sib2, iclass 7, count 2 2006.217.07:50:28.71#ibcon#*after write, iclass 7, count 2 2006.217.07:50:28.71#ibcon#*before return 0, iclass 7, count 2 2006.217.07:50:28.71#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.217.07:50:28.71#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.217.07:50:28.71#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.217.07:50:28.71#ibcon#ireg 7 cls_cnt 0 2006.217.07:50:28.71#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.217.07:50:28.83#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.217.07:50:28.83#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.217.07:50:28.83#ibcon#enter wrdev, iclass 7, count 0 2006.217.07:50:28.83#ibcon#first serial, iclass 7, count 0 2006.217.07:50:28.83#ibcon#enter sib2, iclass 7, count 0 2006.217.07:50:28.83#ibcon#flushed, iclass 7, count 0 2006.217.07:50:28.83#ibcon#about to write, iclass 7, count 0 2006.217.07:50:28.83#ibcon#wrote, iclass 7, count 0 2006.217.07:50:28.83#ibcon#about to read 3, iclass 7, count 0 2006.217.07:50:28.85#ibcon#read 3, iclass 7, count 0 2006.217.07:50:28.85#ibcon#about to read 4, iclass 7, count 0 2006.217.07:50:28.85#ibcon#read 4, iclass 7, count 0 2006.217.07:50:28.85#ibcon#about to read 5, iclass 7, count 0 2006.217.07:50:28.85#ibcon#read 5, iclass 7, count 0 2006.217.07:50:28.85#ibcon#about to read 6, iclass 7, count 0 2006.217.07:50:28.85#ibcon#read 6, iclass 7, count 0 2006.217.07:50:28.85#ibcon#end of sib2, iclass 7, count 0 2006.217.07:50:28.85#ibcon#*mode == 0, iclass 7, count 0 2006.217.07:50:28.85#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.217.07:50:28.85#ibcon#[25=USB\r\n] 2006.217.07:50:28.85#ibcon#*before write, iclass 7, count 0 2006.217.07:50:28.85#ibcon#enter sib2, iclass 7, count 0 2006.217.07:50:28.85#ibcon#flushed, iclass 7, count 0 2006.217.07:50:28.85#ibcon#about to write, iclass 7, count 0 2006.217.07:50:28.85#ibcon#wrote, iclass 7, count 0 2006.217.07:50:28.85#ibcon#about to read 3, iclass 7, count 0 2006.217.07:50:28.88#ibcon#read 3, iclass 7, count 0 2006.217.07:50:28.88#ibcon#about to read 4, iclass 7, count 0 2006.217.07:50:28.88#ibcon#read 4, iclass 7, count 0 2006.217.07:50:28.88#ibcon#about to read 5, iclass 7, count 0 2006.217.07:50:28.88#ibcon#read 5, iclass 7, count 0 2006.217.07:50:28.88#ibcon#about to read 6, iclass 7, count 0 2006.217.07:50:28.88#ibcon#read 6, iclass 7, count 0 2006.217.07:50:28.88#ibcon#end of sib2, iclass 7, count 0 2006.217.07:50:28.88#ibcon#*after write, iclass 7, count 0 2006.217.07:50:28.88#ibcon#*before return 0, iclass 7, count 0 2006.217.07:50:28.88#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.217.07:50:28.88#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.217.07:50:28.88#ibcon#about to clear, iclass 7 cls_cnt 0 2006.217.07:50:28.88#ibcon#cleared, iclass 7 cls_cnt 0 2006.217.07:50:28.88$vc4f8/valo=4,832.99 2006.217.07:50:28.88#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.217.07:50:28.88#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.217.07:50:28.88#ibcon#ireg 17 cls_cnt 0 2006.217.07:50:28.88#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.217.07:50:28.88#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.217.07:50:28.88#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.217.07:50:28.88#ibcon#enter wrdev, iclass 11, count 0 2006.217.07:50:28.88#ibcon#first serial, iclass 11, count 0 2006.217.07:50:28.88#ibcon#enter sib2, iclass 11, count 0 2006.217.07:50:28.88#ibcon#flushed, iclass 11, count 0 2006.217.07:50:28.88#ibcon#about to write, iclass 11, count 0 2006.217.07:50:28.88#ibcon#wrote, iclass 11, count 0 2006.217.07:50:28.88#ibcon#about to read 3, iclass 11, count 0 2006.217.07:50:28.91#ibcon#read 3, iclass 11, count 0 2006.217.07:50:28.91#ibcon#about to read 4, iclass 11, count 0 2006.217.07:50:28.91#ibcon#read 4, iclass 11, count 0 2006.217.07:50:28.91#ibcon#about to read 5, iclass 11, count 0 2006.217.07:50:28.91#ibcon#read 5, iclass 11, count 0 2006.217.07:50:28.91#ibcon#about to read 6, iclass 11, count 0 2006.217.07:50:28.91#ibcon#read 6, iclass 11, count 0 2006.217.07:50:28.91#ibcon#end of sib2, iclass 11, count 0 2006.217.07:50:28.91#ibcon#*mode == 0, iclass 11, count 0 2006.217.07:50:28.91#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.217.07:50:28.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.217.07:50:28.91#ibcon#*before write, iclass 11, count 0 2006.217.07:50:28.91#ibcon#enter sib2, iclass 11, count 0 2006.217.07:50:28.91#ibcon#flushed, iclass 11, count 0 2006.217.07:50:28.91#ibcon#about to write, iclass 11, count 0 2006.217.07:50:28.91#ibcon#wrote, iclass 11, count 0 2006.217.07:50:28.91#ibcon#about to read 3, iclass 11, count 0 2006.217.07:50:28.95#ibcon#read 3, iclass 11, count 0 2006.217.07:50:28.95#ibcon#about to read 4, iclass 11, count 0 2006.217.07:50:28.95#ibcon#read 4, iclass 11, count 0 2006.217.07:50:28.95#ibcon#about to read 5, iclass 11, count 0 2006.217.07:50:28.95#ibcon#read 5, iclass 11, count 0 2006.217.07:50:28.95#ibcon#about to read 6, iclass 11, count 0 2006.217.07:50:28.95#ibcon#read 6, iclass 11, count 0 2006.217.07:50:28.95#ibcon#end of sib2, iclass 11, count 0 2006.217.07:50:28.95#ibcon#*after write, iclass 11, count 0 2006.217.07:50:28.95#ibcon#*before return 0, iclass 11, count 0 2006.217.07:50:28.95#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.217.07:50:28.95#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.217.07:50:28.95#ibcon#about to clear, iclass 11 cls_cnt 0 2006.217.07:50:28.95#ibcon#cleared, iclass 11 cls_cnt 0 2006.217.07:50:28.95$vc4f8/va=4,4 2006.217.07:50:28.95#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.217.07:50:28.95#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.217.07:50:28.95#ibcon#ireg 11 cls_cnt 2 2006.217.07:50:28.95#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.217.07:50:29.00#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.217.07:50:29.00#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.217.07:50:29.00#ibcon#enter wrdev, iclass 13, count 2 2006.217.07:50:29.00#ibcon#first serial, iclass 13, count 2 2006.217.07:50:29.00#ibcon#enter sib2, iclass 13, count 2 2006.217.07:50:29.00#ibcon#flushed, iclass 13, count 2 2006.217.07:50:29.00#ibcon#about to write, iclass 13, count 2 2006.217.07:50:29.00#ibcon#wrote, iclass 13, count 2 2006.217.07:50:29.00#ibcon#about to read 3, iclass 13, count 2 2006.217.07:50:29.02#ibcon#read 3, iclass 13, count 2 2006.217.07:50:29.02#ibcon#about to read 4, iclass 13, count 2 2006.217.07:50:29.02#ibcon#read 4, iclass 13, count 2 2006.217.07:50:29.02#ibcon#about to read 5, iclass 13, count 2 2006.217.07:50:29.02#ibcon#read 5, iclass 13, count 2 2006.217.07:50:29.02#ibcon#about to read 6, iclass 13, count 2 2006.217.07:50:29.02#ibcon#read 6, iclass 13, count 2 2006.217.07:50:29.02#ibcon#end of sib2, iclass 13, count 2 2006.217.07:50:29.02#ibcon#*mode == 0, iclass 13, count 2 2006.217.07:50:29.02#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.217.07:50:29.02#ibcon#[25=AT04-04\r\n] 2006.217.07:50:29.02#ibcon#*before write, iclass 13, count 2 2006.217.07:50:29.02#ibcon#enter sib2, iclass 13, count 2 2006.217.07:50:29.02#ibcon#flushed, iclass 13, count 2 2006.217.07:50:29.02#ibcon#about to write, iclass 13, count 2 2006.217.07:50:29.02#ibcon#wrote, iclass 13, count 2 2006.217.07:50:29.02#ibcon#about to read 3, iclass 13, count 2 2006.217.07:50:29.05#ibcon#read 3, iclass 13, count 2 2006.217.07:50:29.05#ibcon#about to read 4, iclass 13, count 2 2006.217.07:50:29.05#ibcon#read 4, iclass 13, count 2 2006.217.07:50:29.05#ibcon#about to read 5, iclass 13, count 2 2006.217.07:50:29.05#ibcon#read 5, iclass 13, count 2 2006.217.07:50:29.05#ibcon#about to read 6, iclass 13, count 2 2006.217.07:50:29.05#ibcon#read 6, iclass 13, count 2 2006.217.07:50:29.05#ibcon#end of sib2, iclass 13, count 2 2006.217.07:50:29.05#ibcon#*after write, iclass 13, count 2 2006.217.07:50:29.05#ibcon#*before return 0, iclass 13, count 2 2006.217.07:50:29.05#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.217.07:50:29.05#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.217.07:50:29.05#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.217.07:50:29.05#ibcon#ireg 7 cls_cnt 0 2006.217.07:50:29.05#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.217.07:50:29.17#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.217.07:50:29.17#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.217.07:50:29.17#ibcon#enter wrdev, iclass 13, count 0 2006.217.07:50:29.17#ibcon#first serial, iclass 13, count 0 2006.217.07:50:29.17#ibcon#enter sib2, iclass 13, count 0 2006.217.07:50:29.17#ibcon#flushed, iclass 13, count 0 2006.217.07:50:29.17#ibcon#about to write, iclass 13, count 0 2006.217.07:50:29.17#ibcon#wrote, iclass 13, count 0 2006.217.07:50:29.17#ibcon#about to read 3, iclass 13, count 0 2006.217.07:50:29.19#ibcon#read 3, iclass 13, count 0 2006.217.07:50:29.19#ibcon#about to read 4, iclass 13, count 0 2006.217.07:50:29.19#ibcon#read 4, iclass 13, count 0 2006.217.07:50:29.19#ibcon#about to read 5, iclass 13, count 0 2006.217.07:50:29.19#ibcon#read 5, iclass 13, count 0 2006.217.07:50:29.19#ibcon#about to read 6, iclass 13, count 0 2006.217.07:50:29.19#ibcon#read 6, iclass 13, count 0 2006.217.07:50:29.19#ibcon#end of sib2, iclass 13, count 0 2006.217.07:50:29.19#ibcon#*mode == 0, iclass 13, count 0 2006.217.07:50:29.19#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.217.07:50:29.19#ibcon#[25=USB\r\n] 2006.217.07:50:29.19#ibcon#*before write, iclass 13, count 0 2006.217.07:50:29.19#ibcon#enter sib2, iclass 13, count 0 2006.217.07:50:29.19#ibcon#flushed, iclass 13, count 0 2006.217.07:50:29.19#ibcon#about to write, iclass 13, count 0 2006.217.07:50:29.19#ibcon#wrote, iclass 13, count 0 2006.217.07:50:29.19#ibcon#about to read 3, iclass 13, count 0 2006.217.07:50:29.22#ibcon#read 3, iclass 13, count 0 2006.217.07:50:29.22#ibcon#about to read 4, iclass 13, count 0 2006.217.07:50:29.22#ibcon#read 4, iclass 13, count 0 2006.217.07:50:29.22#ibcon#about to read 5, iclass 13, count 0 2006.217.07:50:29.22#ibcon#read 5, iclass 13, count 0 2006.217.07:50:29.22#ibcon#about to read 6, iclass 13, count 0 2006.217.07:50:29.22#ibcon#read 6, iclass 13, count 0 2006.217.07:50:29.22#ibcon#end of sib2, iclass 13, count 0 2006.217.07:50:29.22#ibcon#*after write, iclass 13, count 0 2006.217.07:50:29.22#ibcon#*before return 0, iclass 13, count 0 2006.217.07:50:29.22#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.217.07:50:29.22#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.217.07:50:29.22#ibcon#about to clear, iclass 13 cls_cnt 0 2006.217.07:50:29.22#ibcon#cleared, iclass 13 cls_cnt 0 2006.217.07:50:29.22$vc4f8/valo=5,652.99 2006.217.07:50:29.22#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.217.07:50:29.22#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.217.07:50:29.22#ibcon#ireg 17 cls_cnt 0 2006.217.07:50:29.22#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.217.07:50:29.22#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.217.07:50:29.22#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.217.07:50:29.22#ibcon#enter wrdev, iclass 15, count 0 2006.217.07:50:29.22#ibcon#first serial, iclass 15, count 0 2006.217.07:50:29.22#ibcon#enter sib2, iclass 15, count 0 2006.217.07:50:29.22#ibcon#flushed, iclass 15, count 0 2006.217.07:50:29.22#ibcon#about to write, iclass 15, count 0 2006.217.07:50:29.22#ibcon#wrote, iclass 15, count 0 2006.217.07:50:29.22#ibcon#about to read 3, iclass 15, count 0 2006.217.07:50:29.24#ibcon#read 3, iclass 15, count 0 2006.217.07:50:29.24#ibcon#about to read 4, iclass 15, count 0 2006.217.07:50:29.24#ibcon#read 4, iclass 15, count 0 2006.217.07:50:29.24#ibcon#about to read 5, iclass 15, count 0 2006.217.07:50:29.24#ibcon#read 5, iclass 15, count 0 2006.217.07:50:29.24#ibcon#about to read 6, iclass 15, count 0 2006.217.07:50:29.24#ibcon#read 6, iclass 15, count 0 2006.217.07:50:29.24#ibcon#end of sib2, iclass 15, count 0 2006.217.07:50:29.24#ibcon#*mode == 0, iclass 15, count 0 2006.217.07:50:29.24#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.217.07:50:29.24#ibcon#[26=FRQ=05,652.99\r\n] 2006.217.07:50:29.24#ibcon#*before write, iclass 15, count 0 2006.217.07:50:29.24#ibcon#enter sib2, iclass 15, count 0 2006.217.07:50:29.24#ibcon#flushed, iclass 15, count 0 2006.217.07:50:29.24#ibcon#about to write, iclass 15, count 0 2006.217.07:50:29.24#ibcon#wrote, iclass 15, count 0 2006.217.07:50:29.24#ibcon#about to read 3, iclass 15, count 0 2006.217.07:50:29.28#ibcon#read 3, iclass 15, count 0 2006.217.07:50:29.28#ibcon#about to read 4, iclass 15, count 0 2006.217.07:50:29.28#ibcon#read 4, iclass 15, count 0 2006.217.07:50:29.28#ibcon#about to read 5, iclass 15, count 0 2006.217.07:50:29.28#ibcon#read 5, iclass 15, count 0 2006.217.07:50:29.28#ibcon#about to read 6, iclass 15, count 0 2006.217.07:50:29.28#ibcon#read 6, iclass 15, count 0 2006.217.07:50:29.28#ibcon#end of sib2, iclass 15, count 0 2006.217.07:50:29.28#ibcon#*after write, iclass 15, count 0 2006.217.07:50:29.28#ibcon#*before return 0, iclass 15, count 0 2006.217.07:50:29.28#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.217.07:50:29.28#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.217.07:50:29.28#ibcon#about to clear, iclass 15 cls_cnt 0 2006.217.07:50:29.28#ibcon#cleared, iclass 15 cls_cnt 0 2006.217.07:50:29.28$vc4f8/va=5,7 2006.217.07:50:29.28#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.217.07:50:29.28#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.217.07:50:29.28#ibcon#ireg 11 cls_cnt 2 2006.217.07:50:29.28#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.217.07:50:29.34#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.217.07:50:29.34#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.217.07:50:29.34#ibcon#enter wrdev, iclass 17, count 2 2006.217.07:50:29.34#ibcon#first serial, iclass 17, count 2 2006.217.07:50:29.34#ibcon#enter sib2, iclass 17, count 2 2006.217.07:50:29.34#ibcon#flushed, iclass 17, count 2 2006.217.07:50:29.34#ibcon#about to write, iclass 17, count 2 2006.217.07:50:29.34#ibcon#wrote, iclass 17, count 2 2006.217.07:50:29.34#ibcon#about to read 3, iclass 17, count 2 2006.217.07:50:29.36#ibcon#read 3, iclass 17, count 2 2006.217.07:50:29.36#ibcon#about to read 4, iclass 17, count 2 2006.217.07:50:29.36#ibcon#read 4, iclass 17, count 2 2006.217.07:50:29.36#ibcon#about to read 5, iclass 17, count 2 2006.217.07:50:29.36#ibcon#read 5, iclass 17, count 2 2006.217.07:50:29.36#ibcon#about to read 6, iclass 17, count 2 2006.217.07:50:29.36#ibcon#read 6, iclass 17, count 2 2006.217.07:50:29.36#ibcon#end of sib2, iclass 17, count 2 2006.217.07:50:29.36#ibcon#*mode == 0, iclass 17, count 2 2006.217.07:50:29.36#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.217.07:50:29.36#ibcon#[25=AT05-07\r\n] 2006.217.07:50:29.36#ibcon#*before write, iclass 17, count 2 2006.217.07:50:29.36#ibcon#enter sib2, iclass 17, count 2 2006.217.07:50:29.36#ibcon#flushed, iclass 17, count 2 2006.217.07:50:29.36#ibcon#about to write, iclass 17, count 2 2006.217.07:50:29.36#ibcon#wrote, iclass 17, count 2 2006.217.07:50:29.36#ibcon#about to read 3, iclass 17, count 2 2006.217.07:50:29.39#ibcon#read 3, iclass 17, count 2 2006.217.07:50:29.39#ibcon#about to read 4, iclass 17, count 2 2006.217.07:50:29.39#ibcon#read 4, iclass 17, count 2 2006.217.07:50:29.39#ibcon#about to read 5, iclass 17, count 2 2006.217.07:50:29.39#ibcon#read 5, iclass 17, count 2 2006.217.07:50:29.39#ibcon#about to read 6, iclass 17, count 2 2006.217.07:50:29.39#ibcon#read 6, iclass 17, count 2 2006.217.07:50:29.39#ibcon#end of sib2, iclass 17, count 2 2006.217.07:50:29.39#ibcon#*after write, iclass 17, count 2 2006.217.07:50:29.39#ibcon#*before return 0, iclass 17, count 2 2006.217.07:50:29.39#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.217.07:50:29.39#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.217.07:50:29.39#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.217.07:50:29.39#ibcon#ireg 7 cls_cnt 0 2006.217.07:50:29.39#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.217.07:50:29.51#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.217.07:50:29.51#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.217.07:50:29.51#ibcon#enter wrdev, iclass 17, count 0 2006.217.07:50:29.51#ibcon#first serial, iclass 17, count 0 2006.217.07:50:29.51#ibcon#enter sib2, iclass 17, count 0 2006.217.07:50:29.51#ibcon#flushed, iclass 17, count 0 2006.217.07:50:29.51#ibcon#about to write, iclass 17, count 0 2006.217.07:50:29.51#ibcon#wrote, iclass 17, count 0 2006.217.07:50:29.51#ibcon#about to read 3, iclass 17, count 0 2006.217.07:50:29.53#ibcon#read 3, iclass 17, count 0 2006.217.07:50:29.53#ibcon#about to read 4, iclass 17, count 0 2006.217.07:50:29.53#ibcon#read 4, iclass 17, count 0 2006.217.07:50:29.53#ibcon#about to read 5, iclass 17, count 0 2006.217.07:50:29.53#ibcon#read 5, iclass 17, count 0 2006.217.07:50:29.53#ibcon#about to read 6, iclass 17, count 0 2006.217.07:50:29.53#ibcon#read 6, iclass 17, count 0 2006.217.07:50:29.53#ibcon#end of sib2, iclass 17, count 0 2006.217.07:50:29.53#ibcon#*mode == 0, iclass 17, count 0 2006.217.07:50:29.53#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.217.07:50:29.53#ibcon#[25=USB\r\n] 2006.217.07:50:29.53#ibcon#*before write, iclass 17, count 0 2006.217.07:50:29.53#ibcon#enter sib2, iclass 17, count 0 2006.217.07:50:29.53#ibcon#flushed, iclass 17, count 0 2006.217.07:50:29.53#ibcon#about to write, iclass 17, count 0 2006.217.07:50:29.53#ibcon#wrote, iclass 17, count 0 2006.217.07:50:29.53#ibcon#about to read 3, iclass 17, count 0 2006.217.07:50:29.56#ibcon#read 3, iclass 17, count 0 2006.217.07:50:29.56#ibcon#about to read 4, iclass 17, count 0 2006.217.07:50:29.56#ibcon#read 4, iclass 17, count 0 2006.217.07:50:29.56#ibcon#about to read 5, iclass 17, count 0 2006.217.07:50:29.56#ibcon#read 5, iclass 17, count 0 2006.217.07:50:29.56#ibcon#about to read 6, iclass 17, count 0 2006.217.07:50:29.56#ibcon#read 6, iclass 17, count 0 2006.217.07:50:29.56#ibcon#end of sib2, iclass 17, count 0 2006.217.07:50:29.56#ibcon#*after write, iclass 17, count 0 2006.217.07:50:29.56#ibcon#*before return 0, iclass 17, count 0 2006.217.07:50:29.56#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.217.07:50:29.56#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.217.07:50:29.56#ibcon#about to clear, iclass 17 cls_cnt 0 2006.217.07:50:29.56#ibcon#cleared, iclass 17 cls_cnt 0 2006.217.07:50:29.56$vc4f8/valo=6,772.99 2006.217.07:50:29.56#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.217.07:50:29.56#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.217.07:50:29.56#ibcon#ireg 17 cls_cnt 0 2006.217.07:50:29.56#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.217.07:50:29.56#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.217.07:50:29.56#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.217.07:50:29.56#ibcon#enter wrdev, iclass 19, count 0 2006.217.07:50:29.56#ibcon#first serial, iclass 19, count 0 2006.217.07:50:29.56#ibcon#enter sib2, iclass 19, count 0 2006.217.07:50:29.56#ibcon#flushed, iclass 19, count 0 2006.217.07:50:29.56#ibcon#about to write, iclass 19, count 0 2006.217.07:50:29.56#ibcon#wrote, iclass 19, count 0 2006.217.07:50:29.56#ibcon#about to read 3, iclass 19, count 0 2006.217.07:50:29.59#ibcon#read 3, iclass 19, count 0 2006.217.07:50:29.59#ibcon#about to read 4, iclass 19, count 0 2006.217.07:50:29.59#ibcon#read 4, iclass 19, count 0 2006.217.07:50:29.59#ibcon#about to read 5, iclass 19, count 0 2006.217.07:50:29.59#ibcon#read 5, iclass 19, count 0 2006.217.07:50:29.59#ibcon#about to read 6, iclass 19, count 0 2006.217.07:50:29.59#ibcon#read 6, iclass 19, count 0 2006.217.07:50:29.59#ibcon#end of sib2, iclass 19, count 0 2006.217.07:50:29.59#ibcon#*mode == 0, iclass 19, count 0 2006.217.07:50:29.59#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.217.07:50:29.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.217.07:50:29.59#ibcon#*before write, iclass 19, count 0 2006.217.07:50:29.59#ibcon#enter sib2, iclass 19, count 0 2006.217.07:50:29.59#ibcon#flushed, iclass 19, count 0 2006.217.07:50:29.59#ibcon#about to write, iclass 19, count 0 2006.217.07:50:29.59#ibcon#wrote, iclass 19, count 0 2006.217.07:50:29.59#ibcon#about to read 3, iclass 19, count 0 2006.217.07:50:29.63#ibcon#read 3, iclass 19, count 0 2006.217.07:50:29.63#ibcon#about to read 4, iclass 19, count 0 2006.217.07:50:29.63#ibcon#read 4, iclass 19, count 0 2006.217.07:50:29.63#ibcon#about to read 5, iclass 19, count 0 2006.217.07:50:29.63#ibcon#read 5, iclass 19, count 0 2006.217.07:50:29.63#ibcon#about to read 6, iclass 19, count 0 2006.217.07:50:29.63#ibcon#read 6, iclass 19, count 0 2006.217.07:50:29.63#ibcon#end of sib2, iclass 19, count 0 2006.217.07:50:29.63#ibcon#*after write, iclass 19, count 0 2006.217.07:50:29.63#ibcon#*before return 0, iclass 19, count 0 2006.217.07:50:29.63#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.217.07:50:29.63#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.217.07:50:29.63#ibcon#about to clear, iclass 19 cls_cnt 0 2006.217.07:50:29.63#ibcon#cleared, iclass 19 cls_cnt 0 2006.217.07:50:29.63$vc4f8/va=6,6 2006.217.07:50:29.63#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.217.07:50:29.63#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.217.07:50:29.63#ibcon#ireg 11 cls_cnt 2 2006.217.07:50:29.63#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.217.07:50:29.68#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.217.07:50:29.68#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.217.07:50:29.68#ibcon#enter wrdev, iclass 21, count 2 2006.217.07:50:29.68#ibcon#first serial, iclass 21, count 2 2006.217.07:50:29.68#ibcon#enter sib2, iclass 21, count 2 2006.217.07:50:29.68#ibcon#flushed, iclass 21, count 2 2006.217.07:50:29.68#ibcon#about to write, iclass 21, count 2 2006.217.07:50:29.68#ibcon#wrote, iclass 21, count 2 2006.217.07:50:29.68#ibcon#about to read 3, iclass 21, count 2 2006.217.07:50:29.70#ibcon#read 3, iclass 21, count 2 2006.217.07:50:29.70#ibcon#about to read 4, iclass 21, count 2 2006.217.07:50:29.70#ibcon#read 4, iclass 21, count 2 2006.217.07:50:29.70#ibcon#about to read 5, iclass 21, count 2 2006.217.07:50:29.70#ibcon#read 5, iclass 21, count 2 2006.217.07:50:29.70#ibcon#about to read 6, iclass 21, count 2 2006.217.07:50:29.70#ibcon#read 6, iclass 21, count 2 2006.217.07:50:29.70#ibcon#end of sib2, iclass 21, count 2 2006.217.07:50:29.70#ibcon#*mode == 0, iclass 21, count 2 2006.217.07:50:29.70#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.217.07:50:29.70#ibcon#[25=AT06-06\r\n] 2006.217.07:50:29.70#ibcon#*before write, iclass 21, count 2 2006.217.07:50:29.70#ibcon#enter sib2, iclass 21, count 2 2006.217.07:50:29.70#ibcon#flushed, iclass 21, count 2 2006.217.07:50:29.70#ibcon#about to write, iclass 21, count 2 2006.217.07:50:29.70#ibcon#wrote, iclass 21, count 2 2006.217.07:50:29.70#ibcon#about to read 3, iclass 21, count 2 2006.217.07:50:29.73#ibcon#read 3, iclass 21, count 2 2006.217.07:50:29.73#ibcon#about to read 4, iclass 21, count 2 2006.217.07:50:29.73#ibcon#read 4, iclass 21, count 2 2006.217.07:50:29.73#ibcon#about to read 5, iclass 21, count 2 2006.217.07:50:29.73#ibcon#read 5, iclass 21, count 2 2006.217.07:50:29.73#ibcon#about to read 6, iclass 21, count 2 2006.217.07:50:29.73#ibcon#read 6, iclass 21, count 2 2006.217.07:50:29.73#ibcon#end of sib2, iclass 21, count 2 2006.217.07:50:29.73#ibcon#*after write, iclass 21, count 2 2006.217.07:50:29.73#ibcon#*before return 0, iclass 21, count 2 2006.217.07:50:29.73#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.217.07:50:29.73#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.217.07:50:29.73#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.217.07:50:29.73#ibcon#ireg 7 cls_cnt 0 2006.217.07:50:29.73#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.217.07:50:29.85#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.217.07:50:29.85#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.217.07:50:29.85#ibcon#enter wrdev, iclass 21, count 0 2006.217.07:50:29.85#ibcon#first serial, iclass 21, count 0 2006.217.07:50:29.85#ibcon#enter sib2, iclass 21, count 0 2006.217.07:50:29.85#ibcon#flushed, iclass 21, count 0 2006.217.07:50:29.85#ibcon#about to write, iclass 21, count 0 2006.217.07:50:29.85#ibcon#wrote, iclass 21, count 0 2006.217.07:50:29.85#ibcon#about to read 3, iclass 21, count 0 2006.217.07:50:29.87#ibcon#read 3, iclass 21, count 0 2006.217.07:50:29.87#ibcon#about to read 4, iclass 21, count 0 2006.217.07:50:29.87#ibcon#read 4, iclass 21, count 0 2006.217.07:50:29.87#ibcon#about to read 5, iclass 21, count 0 2006.217.07:50:29.87#ibcon#read 5, iclass 21, count 0 2006.217.07:50:29.87#ibcon#about to read 6, iclass 21, count 0 2006.217.07:50:29.87#ibcon#read 6, iclass 21, count 0 2006.217.07:50:29.87#ibcon#end of sib2, iclass 21, count 0 2006.217.07:50:29.87#ibcon#*mode == 0, iclass 21, count 0 2006.217.07:50:29.87#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.217.07:50:29.87#ibcon#[25=USB\r\n] 2006.217.07:50:29.87#ibcon#*before write, iclass 21, count 0 2006.217.07:50:29.87#ibcon#enter sib2, iclass 21, count 0 2006.217.07:50:29.87#ibcon#flushed, iclass 21, count 0 2006.217.07:50:29.87#ibcon#about to write, iclass 21, count 0 2006.217.07:50:29.87#ibcon#wrote, iclass 21, count 0 2006.217.07:50:29.87#ibcon#about to read 3, iclass 21, count 0 2006.217.07:50:29.90#ibcon#read 3, iclass 21, count 0 2006.217.07:50:29.90#ibcon#about to read 4, iclass 21, count 0 2006.217.07:50:29.90#ibcon#read 4, iclass 21, count 0 2006.217.07:50:29.90#ibcon#about to read 5, iclass 21, count 0 2006.217.07:50:29.90#ibcon#read 5, iclass 21, count 0 2006.217.07:50:29.90#ibcon#about to read 6, iclass 21, count 0 2006.217.07:50:29.90#ibcon#read 6, iclass 21, count 0 2006.217.07:50:29.90#ibcon#end of sib2, iclass 21, count 0 2006.217.07:50:29.90#ibcon#*after write, iclass 21, count 0 2006.217.07:50:29.90#ibcon#*before return 0, iclass 21, count 0 2006.217.07:50:29.90#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.217.07:50:29.90#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.217.07:50:29.90#ibcon#about to clear, iclass 21 cls_cnt 0 2006.217.07:50:29.90#ibcon#cleared, iclass 21 cls_cnt 0 2006.217.07:50:29.90$vc4f8/valo=7,832.99 2006.217.07:50:29.90#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.217.07:50:29.90#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.217.07:50:29.90#ibcon#ireg 17 cls_cnt 0 2006.217.07:50:29.90#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.217.07:50:29.90#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.217.07:50:29.90#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.217.07:50:29.90#ibcon#enter wrdev, iclass 23, count 0 2006.217.07:50:29.90#ibcon#first serial, iclass 23, count 0 2006.217.07:50:29.90#ibcon#enter sib2, iclass 23, count 0 2006.217.07:50:29.90#ibcon#flushed, iclass 23, count 0 2006.217.07:50:29.90#ibcon#about to write, iclass 23, count 0 2006.217.07:50:29.90#ibcon#wrote, iclass 23, count 0 2006.217.07:50:29.90#ibcon#about to read 3, iclass 23, count 0 2006.217.07:50:29.92#ibcon#read 3, iclass 23, count 0 2006.217.07:50:29.92#ibcon#about to read 4, iclass 23, count 0 2006.217.07:50:29.92#ibcon#read 4, iclass 23, count 0 2006.217.07:50:29.92#ibcon#about to read 5, iclass 23, count 0 2006.217.07:50:29.92#ibcon#read 5, iclass 23, count 0 2006.217.07:50:29.92#ibcon#about to read 6, iclass 23, count 0 2006.217.07:50:29.92#ibcon#read 6, iclass 23, count 0 2006.217.07:50:29.92#ibcon#end of sib2, iclass 23, count 0 2006.217.07:50:29.92#ibcon#*mode == 0, iclass 23, count 0 2006.217.07:50:29.92#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.217.07:50:29.92#ibcon#[26=FRQ=07,832.99\r\n] 2006.217.07:50:29.92#ibcon#*before write, iclass 23, count 0 2006.217.07:50:29.92#ibcon#enter sib2, iclass 23, count 0 2006.217.07:50:29.92#ibcon#flushed, iclass 23, count 0 2006.217.07:50:29.92#ibcon#about to write, iclass 23, count 0 2006.217.07:50:29.92#ibcon#wrote, iclass 23, count 0 2006.217.07:50:29.92#ibcon#about to read 3, iclass 23, count 0 2006.217.07:50:29.96#ibcon#read 3, iclass 23, count 0 2006.217.07:50:29.96#ibcon#about to read 4, iclass 23, count 0 2006.217.07:50:29.96#ibcon#read 4, iclass 23, count 0 2006.217.07:50:29.96#ibcon#about to read 5, iclass 23, count 0 2006.217.07:50:29.96#ibcon#read 5, iclass 23, count 0 2006.217.07:50:29.96#ibcon#about to read 6, iclass 23, count 0 2006.217.07:50:29.96#ibcon#read 6, iclass 23, count 0 2006.217.07:50:29.96#ibcon#end of sib2, iclass 23, count 0 2006.217.07:50:29.96#ibcon#*after write, iclass 23, count 0 2006.217.07:50:29.96#ibcon#*before return 0, iclass 23, count 0 2006.217.07:50:29.96#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.217.07:50:29.96#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.217.07:50:29.96#ibcon#about to clear, iclass 23 cls_cnt 0 2006.217.07:50:29.96#ibcon#cleared, iclass 23 cls_cnt 0 2006.217.07:50:29.96$vc4f8/va=7,6 2006.217.07:50:29.96#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.217.07:50:29.96#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.217.07:50:29.96#ibcon#ireg 11 cls_cnt 2 2006.217.07:50:29.96#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.217.07:50:30.02#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.217.07:50:30.02#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.217.07:50:30.02#ibcon#enter wrdev, iclass 25, count 2 2006.217.07:50:30.02#ibcon#first serial, iclass 25, count 2 2006.217.07:50:30.02#ibcon#enter sib2, iclass 25, count 2 2006.217.07:50:30.02#ibcon#flushed, iclass 25, count 2 2006.217.07:50:30.02#ibcon#about to write, iclass 25, count 2 2006.217.07:50:30.02#ibcon#wrote, iclass 25, count 2 2006.217.07:50:30.02#ibcon#about to read 3, iclass 25, count 2 2006.217.07:50:30.04#ibcon#read 3, iclass 25, count 2 2006.217.07:50:30.04#ibcon#about to read 4, iclass 25, count 2 2006.217.07:50:30.04#ibcon#read 4, iclass 25, count 2 2006.217.07:50:30.04#ibcon#about to read 5, iclass 25, count 2 2006.217.07:50:30.04#ibcon#read 5, iclass 25, count 2 2006.217.07:50:30.04#ibcon#about to read 6, iclass 25, count 2 2006.217.07:50:30.04#ibcon#read 6, iclass 25, count 2 2006.217.07:50:30.04#ibcon#end of sib2, iclass 25, count 2 2006.217.07:50:30.04#ibcon#*mode == 0, iclass 25, count 2 2006.217.07:50:30.04#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.217.07:50:30.04#ibcon#[25=AT07-06\r\n] 2006.217.07:50:30.04#ibcon#*before write, iclass 25, count 2 2006.217.07:50:30.04#ibcon#enter sib2, iclass 25, count 2 2006.217.07:50:30.04#ibcon#flushed, iclass 25, count 2 2006.217.07:50:30.04#ibcon#about to write, iclass 25, count 2 2006.217.07:50:30.04#ibcon#wrote, iclass 25, count 2 2006.217.07:50:30.04#ibcon#about to read 3, iclass 25, count 2 2006.217.07:50:30.07#ibcon#read 3, iclass 25, count 2 2006.217.07:50:30.07#ibcon#about to read 4, iclass 25, count 2 2006.217.07:50:30.07#ibcon#read 4, iclass 25, count 2 2006.217.07:50:30.07#ibcon#about to read 5, iclass 25, count 2 2006.217.07:50:30.07#ibcon#read 5, iclass 25, count 2 2006.217.07:50:30.07#ibcon#about to read 6, iclass 25, count 2 2006.217.07:50:30.07#ibcon#read 6, iclass 25, count 2 2006.217.07:50:30.07#ibcon#end of sib2, iclass 25, count 2 2006.217.07:50:30.07#ibcon#*after write, iclass 25, count 2 2006.217.07:50:30.07#ibcon#*before return 0, iclass 25, count 2 2006.217.07:50:30.07#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.217.07:50:30.07#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.217.07:50:30.07#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.217.07:50:30.07#ibcon#ireg 7 cls_cnt 0 2006.217.07:50:30.07#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.217.07:50:30.19#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.217.07:50:30.19#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.217.07:50:30.19#ibcon#enter wrdev, iclass 25, count 0 2006.217.07:50:30.19#ibcon#first serial, iclass 25, count 0 2006.217.07:50:30.19#ibcon#enter sib2, iclass 25, count 0 2006.217.07:50:30.19#ibcon#flushed, iclass 25, count 0 2006.217.07:50:30.19#ibcon#about to write, iclass 25, count 0 2006.217.07:50:30.19#ibcon#wrote, iclass 25, count 0 2006.217.07:50:30.19#ibcon#about to read 3, iclass 25, count 0 2006.217.07:50:30.21#ibcon#read 3, iclass 25, count 0 2006.217.07:50:30.21#ibcon#about to read 4, iclass 25, count 0 2006.217.07:50:30.21#ibcon#read 4, iclass 25, count 0 2006.217.07:50:30.21#ibcon#about to read 5, iclass 25, count 0 2006.217.07:50:30.21#ibcon#read 5, iclass 25, count 0 2006.217.07:50:30.21#ibcon#about to read 6, iclass 25, count 0 2006.217.07:50:30.21#ibcon#read 6, iclass 25, count 0 2006.217.07:50:30.21#ibcon#end of sib2, iclass 25, count 0 2006.217.07:50:30.21#ibcon#*mode == 0, iclass 25, count 0 2006.217.07:50:30.21#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.217.07:50:30.21#ibcon#[25=USB\r\n] 2006.217.07:50:30.21#ibcon#*before write, iclass 25, count 0 2006.217.07:50:30.21#ibcon#enter sib2, iclass 25, count 0 2006.217.07:50:30.21#ibcon#flushed, iclass 25, count 0 2006.217.07:50:30.21#ibcon#about to write, iclass 25, count 0 2006.217.07:50:30.21#ibcon#wrote, iclass 25, count 0 2006.217.07:50:30.21#ibcon#about to read 3, iclass 25, count 0 2006.217.07:50:30.24#ibcon#read 3, iclass 25, count 0 2006.217.07:50:30.24#ibcon#about to read 4, iclass 25, count 0 2006.217.07:50:30.24#ibcon#read 4, iclass 25, count 0 2006.217.07:50:30.24#ibcon#about to read 5, iclass 25, count 0 2006.217.07:50:30.24#ibcon#read 5, iclass 25, count 0 2006.217.07:50:30.24#ibcon#about to read 6, iclass 25, count 0 2006.217.07:50:30.24#ibcon#read 6, iclass 25, count 0 2006.217.07:50:30.24#ibcon#end of sib2, iclass 25, count 0 2006.217.07:50:30.24#ibcon#*after write, iclass 25, count 0 2006.217.07:50:30.24#ibcon#*before return 0, iclass 25, count 0 2006.217.07:50:30.24#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.217.07:50:30.24#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.217.07:50:30.24#ibcon#about to clear, iclass 25 cls_cnt 0 2006.217.07:50:30.24#ibcon#cleared, iclass 25 cls_cnt 0 2006.217.07:50:30.24$vc4f8/valo=8,852.99 2006.217.07:50:30.24#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.217.07:50:30.24#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.217.07:50:30.24#ibcon#ireg 17 cls_cnt 0 2006.217.07:50:30.24#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.217.07:50:30.24#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.217.07:50:30.24#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.217.07:50:30.24#ibcon#enter wrdev, iclass 27, count 0 2006.217.07:50:30.24#ibcon#first serial, iclass 27, count 0 2006.217.07:50:30.24#ibcon#enter sib2, iclass 27, count 0 2006.217.07:50:30.24#ibcon#flushed, iclass 27, count 0 2006.217.07:50:30.24#ibcon#about to write, iclass 27, count 0 2006.217.07:50:30.24#ibcon#wrote, iclass 27, count 0 2006.217.07:50:30.24#ibcon#about to read 3, iclass 27, count 0 2006.217.07:50:30.26#ibcon#read 3, iclass 27, count 0 2006.217.07:50:30.26#ibcon#about to read 4, iclass 27, count 0 2006.217.07:50:30.26#ibcon#read 4, iclass 27, count 0 2006.217.07:50:30.26#ibcon#about to read 5, iclass 27, count 0 2006.217.07:50:30.26#ibcon#read 5, iclass 27, count 0 2006.217.07:50:30.26#ibcon#about to read 6, iclass 27, count 0 2006.217.07:50:30.26#ibcon#read 6, iclass 27, count 0 2006.217.07:50:30.26#ibcon#end of sib2, iclass 27, count 0 2006.217.07:50:30.26#ibcon#*mode == 0, iclass 27, count 0 2006.217.07:50:30.26#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.217.07:50:30.26#ibcon#[26=FRQ=08,852.99\r\n] 2006.217.07:50:30.26#ibcon#*before write, iclass 27, count 0 2006.217.07:50:30.26#ibcon#enter sib2, iclass 27, count 0 2006.217.07:50:30.26#ibcon#flushed, iclass 27, count 0 2006.217.07:50:30.26#ibcon#about to write, iclass 27, count 0 2006.217.07:50:30.26#ibcon#wrote, iclass 27, count 0 2006.217.07:50:30.26#ibcon#about to read 3, iclass 27, count 0 2006.217.07:50:30.31#ibcon#read 3, iclass 27, count 0 2006.217.07:50:30.31#ibcon#about to read 4, iclass 27, count 0 2006.217.07:50:30.31#ibcon#read 4, iclass 27, count 0 2006.217.07:50:30.31#ibcon#about to read 5, iclass 27, count 0 2006.217.07:50:30.31#ibcon#read 5, iclass 27, count 0 2006.217.07:50:30.31#ibcon#about to read 6, iclass 27, count 0 2006.217.07:50:30.31#ibcon#read 6, iclass 27, count 0 2006.217.07:50:30.31#ibcon#end of sib2, iclass 27, count 0 2006.217.07:50:30.31#ibcon#*after write, iclass 27, count 0 2006.217.07:50:30.31#ibcon#*before return 0, iclass 27, count 0 2006.217.07:50:30.31#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.217.07:50:30.31#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.217.07:50:30.31#ibcon#about to clear, iclass 27 cls_cnt 0 2006.217.07:50:30.31#ibcon#cleared, iclass 27 cls_cnt 0 2006.217.07:50:30.31$vc4f8/va=8,7 2006.217.07:50:30.31#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.217.07:50:30.31#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.217.07:50:30.31#ibcon#ireg 11 cls_cnt 2 2006.217.07:50:30.31#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.217.07:50:30.35#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.217.07:50:30.35#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.217.07:50:30.35#ibcon#enter wrdev, iclass 29, count 2 2006.217.07:50:30.35#ibcon#first serial, iclass 29, count 2 2006.217.07:50:30.35#ibcon#enter sib2, iclass 29, count 2 2006.217.07:50:30.35#ibcon#flushed, iclass 29, count 2 2006.217.07:50:30.35#ibcon#about to write, iclass 29, count 2 2006.217.07:50:30.35#ibcon#wrote, iclass 29, count 2 2006.217.07:50:30.35#ibcon#about to read 3, iclass 29, count 2 2006.217.07:50:30.37#ibcon#read 3, iclass 29, count 2 2006.217.07:50:30.37#ibcon#about to read 4, iclass 29, count 2 2006.217.07:50:30.37#ibcon#read 4, iclass 29, count 2 2006.217.07:50:30.37#ibcon#about to read 5, iclass 29, count 2 2006.217.07:50:30.37#ibcon#read 5, iclass 29, count 2 2006.217.07:50:30.37#ibcon#about to read 6, iclass 29, count 2 2006.217.07:50:30.37#ibcon#read 6, iclass 29, count 2 2006.217.07:50:30.37#ibcon#end of sib2, iclass 29, count 2 2006.217.07:50:30.37#ibcon#*mode == 0, iclass 29, count 2 2006.217.07:50:30.37#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.217.07:50:30.37#ibcon#[25=AT08-07\r\n] 2006.217.07:50:30.37#ibcon#*before write, iclass 29, count 2 2006.217.07:50:30.37#ibcon#enter sib2, iclass 29, count 2 2006.217.07:50:30.37#ibcon#flushed, iclass 29, count 2 2006.217.07:50:30.37#ibcon#about to write, iclass 29, count 2 2006.217.07:50:30.37#ibcon#wrote, iclass 29, count 2 2006.217.07:50:30.37#ibcon#about to read 3, iclass 29, count 2 2006.217.07:50:30.40#ibcon#read 3, iclass 29, count 2 2006.217.07:50:30.40#ibcon#about to read 4, iclass 29, count 2 2006.217.07:50:30.40#ibcon#read 4, iclass 29, count 2 2006.217.07:50:30.40#ibcon#about to read 5, iclass 29, count 2 2006.217.07:50:30.40#ibcon#read 5, iclass 29, count 2 2006.217.07:50:30.40#ibcon#about to read 6, iclass 29, count 2 2006.217.07:50:30.40#ibcon#read 6, iclass 29, count 2 2006.217.07:50:30.40#ibcon#end of sib2, iclass 29, count 2 2006.217.07:50:30.40#ibcon#*after write, iclass 29, count 2 2006.217.07:50:30.40#ibcon#*before return 0, iclass 29, count 2 2006.217.07:50:30.40#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.217.07:50:30.40#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.217.07:50:30.40#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.217.07:50:30.40#ibcon#ireg 7 cls_cnt 0 2006.217.07:50:30.40#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.217.07:50:30.52#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.217.07:50:30.52#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.217.07:50:30.52#ibcon#enter wrdev, iclass 29, count 0 2006.217.07:50:30.52#ibcon#first serial, iclass 29, count 0 2006.217.07:50:30.52#ibcon#enter sib2, iclass 29, count 0 2006.217.07:50:30.52#ibcon#flushed, iclass 29, count 0 2006.217.07:50:30.52#ibcon#about to write, iclass 29, count 0 2006.217.07:50:30.52#ibcon#wrote, iclass 29, count 0 2006.217.07:50:30.52#ibcon#about to read 3, iclass 29, count 0 2006.217.07:50:30.54#ibcon#read 3, iclass 29, count 0 2006.217.07:50:30.54#ibcon#about to read 4, iclass 29, count 0 2006.217.07:50:30.54#ibcon#read 4, iclass 29, count 0 2006.217.07:50:30.54#ibcon#about to read 5, iclass 29, count 0 2006.217.07:50:30.54#ibcon#read 5, iclass 29, count 0 2006.217.07:50:30.54#ibcon#about to read 6, iclass 29, count 0 2006.217.07:50:30.54#ibcon#read 6, iclass 29, count 0 2006.217.07:50:30.54#ibcon#end of sib2, iclass 29, count 0 2006.217.07:50:30.54#ibcon#*mode == 0, iclass 29, count 0 2006.217.07:50:30.54#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.217.07:50:30.54#ibcon#[25=USB\r\n] 2006.217.07:50:30.54#ibcon#*before write, iclass 29, count 0 2006.217.07:50:30.54#ibcon#enter sib2, iclass 29, count 0 2006.217.07:50:30.54#ibcon#flushed, iclass 29, count 0 2006.217.07:50:30.54#ibcon#about to write, iclass 29, count 0 2006.217.07:50:30.54#ibcon#wrote, iclass 29, count 0 2006.217.07:50:30.54#ibcon#about to read 3, iclass 29, count 0 2006.217.07:50:30.57#ibcon#read 3, iclass 29, count 0 2006.217.07:50:30.57#ibcon#about to read 4, iclass 29, count 0 2006.217.07:50:30.57#ibcon#read 4, iclass 29, count 0 2006.217.07:50:30.57#ibcon#about to read 5, iclass 29, count 0 2006.217.07:50:30.57#ibcon#read 5, iclass 29, count 0 2006.217.07:50:30.57#ibcon#about to read 6, iclass 29, count 0 2006.217.07:50:30.57#ibcon#read 6, iclass 29, count 0 2006.217.07:50:30.57#ibcon#end of sib2, iclass 29, count 0 2006.217.07:50:30.57#ibcon#*after write, iclass 29, count 0 2006.217.07:50:30.57#ibcon#*before return 0, iclass 29, count 0 2006.217.07:50:30.57#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.217.07:50:30.57#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.217.07:50:30.57#ibcon#about to clear, iclass 29 cls_cnt 0 2006.217.07:50:30.57#ibcon#cleared, iclass 29 cls_cnt 0 2006.217.07:50:30.57$vc4f8/vblo=1,632.99 2006.217.07:50:30.57#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.217.07:50:30.57#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.217.07:50:30.57#ibcon#ireg 17 cls_cnt 0 2006.217.07:50:30.57#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.217.07:50:30.57#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.217.07:50:30.57#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.217.07:50:30.57#ibcon#enter wrdev, iclass 31, count 0 2006.217.07:50:30.57#ibcon#first serial, iclass 31, count 0 2006.217.07:50:30.57#ibcon#enter sib2, iclass 31, count 0 2006.217.07:50:30.57#ibcon#flushed, iclass 31, count 0 2006.217.07:50:30.57#ibcon#about to write, iclass 31, count 0 2006.217.07:50:30.57#ibcon#wrote, iclass 31, count 0 2006.217.07:50:30.57#ibcon#about to read 3, iclass 31, count 0 2006.217.07:50:30.59#ibcon#read 3, iclass 31, count 0 2006.217.07:50:30.59#ibcon#about to read 4, iclass 31, count 0 2006.217.07:50:30.59#ibcon#read 4, iclass 31, count 0 2006.217.07:50:30.59#ibcon#about to read 5, iclass 31, count 0 2006.217.07:50:30.59#ibcon#read 5, iclass 31, count 0 2006.217.07:50:30.59#ibcon#about to read 6, iclass 31, count 0 2006.217.07:50:30.59#ibcon#read 6, iclass 31, count 0 2006.217.07:50:30.59#ibcon#end of sib2, iclass 31, count 0 2006.217.07:50:30.59#ibcon#*mode == 0, iclass 31, count 0 2006.217.07:50:30.59#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.217.07:50:30.59#ibcon#[28=FRQ=01,632.99\r\n] 2006.217.07:50:30.59#ibcon#*before write, iclass 31, count 0 2006.217.07:50:30.59#ibcon#enter sib2, iclass 31, count 0 2006.217.07:50:30.59#ibcon#flushed, iclass 31, count 0 2006.217.07:50:30.59#ibcon#about to write, iclass 31, count 0 2006.217.07:50:30.59#ibcon#wrote, iclass 31, count 0 2006.217.07:50:30.59#ibcon#about to read 3, iclass 31, count 0 2006.217.07:50:30.63#ibcon#read 3, iclass 31, count 0 2006.217.07:50:30.63#ibcon#about to read 4, iclass 31, count 0 2006.217.07:50:30.63#ibcon#read 4, iclass 31, count 0 2006.217.07:50:30.63#ibcon#about to read 5, iclass 31, count 0 2006.217.07:50:30.63#ibcon#read 5, iclass 31, count 0 2006.217.07:50:30.63#ibcon#about to read 6, iclass 31, count 0 2006.217.07:50:30.63#ibcon#read 6, iclass 31, count 0 2006.217.07:50:30.63#ibcon#end of sib2, iclass 31, count 0 2006.217.07:50:30.63#ibcon#*after write, iclass 31, count 0 2006.217.07:50:30.63#ibcon#*before return 0, iclass 31, count 0 2006.217.07:50:30.63#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.217.07:50:30.63#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.217.07:50:30.63#ibcon#about to clear, iclass 31 cls_cnt 0 2006.217.07:50:30.63#ibcon#cleared, iclass 31 cls_cnt 0 2006.217.07:50:30.63$vc4f8/vb=1,4 2006.217.07:50:30.63#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.217.07:50:30.63#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.217.07:50:30.63#ibcon#ireg 11 cls_cnt 2 2006.217.07:50:30.63#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.217.07:50:30.63#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.217.07:50:30.63#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.217.07:50:30.63#ibcon#enter wrdev, iclass 33, count 2 2006.217.07:50:30.63#ibcon#first serial, iclass 33, count 2 2006.217.07:50:30.63#ibcon#enter sib2, iclass 33, count 2 2006.217.07:50:30.63#ibcon#flushed, iclass 33, count 2 2006.217.07:50:30.63#ibcon#about to write, iclass 33, count 2 2006.217.07:50:30.63#ibcon#wrote, iclass 33, count 2 2006.217.07:50:30.63#ibcon#about to read 3, iclass 33, count 2 2006.217.07:50:30.65#ibcon#read 3, iclass 33, count 2 2006.217.07:50:30.65#ibcon#about to read 4, iclass 33, count 2 2006.217.07:50:30.65#ibcon#read 4, iclass 33, count 2 2006.217.07:50:30.65#ibcon#about to read 5, iclass 33, count 2 2006.217.07:50:30.65#ibcon#read 5, iclass 33, count 2 2006.217.07:50:30.65#ibcon#about to read 6, iclass 33, count 2 2006.217.07:50:30.65#ibcon#read 6, iclass 33, count 2 2006.217.07:50:30.65#ibcon#end of sib2, iclass 33, count 2 2006.217.07:50:30.65#ibcon#*mode == 0, iclass 33, count 2 2006.217.07:50:30.65#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.217.07:50:30.65#ibcon#[27=AT01-04\r\n] 2006.217.07:50:30.65#ibcon#*before write, iclass 33, count 2 2006.217.07:50:30.65#ibcon#enter sib2, iclass 33, count 2 2006.217.07:50:30.65#ibcon#flushed, iclass 33, count 2 2006.217.07:50:30.65#ibcon#about to write, iclass 33, count 2 2006.217.07:50:30.65#ibcon#wrote, iclass 33, count 2 2006.217.07:50:30.65#ibcon#about to read 3, iclass 33, count 2 2006.217.07:50:30.68#ibcon#read 3, iclass 33, count 2 2006.217.07:50:30.68#ibcon#about to read 4, iclass 33, count 2 2006.217.07:50:30.68#ibcon#read 4, iclass 33, count 2 2006.217.07:50:30.68#ibcon#about to read 5, iclass 33, count 2 2006.217.07:50:30.68#ibcon#read 5, iclass 33, count 2 2006.217.07:50:30.68#ibcon#about to read 6, iclass 33, count 2 2006.217.07:50:30.68#ibcon#read 6, iclass 33, count 2 2006.217.07:50:30.68#ibcon#end of sib2, iclass 33, count 2 2006.217.07:50:30.68#ibcon#*after write, iclass 33, count 2 2006.217.07:50:30.68#ibcon#*before return 0, iclass 33, count 2 2006.217.07:50:30.68#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.217.07:50:30.68#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.217.07:50:30.68#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.217.07:50:30.68#ibcon#ireg 7 cls_cnt 0 2006.217.07:50:30.68#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.217.07:50:30.80#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.217.07:50:30.80#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.217.07:50:30.80#ibcon#enter wrdev, iclass 33, count 0 2006.217.07:50:30.80#ibcon#first serial, iclass 33, count 0 2006.217.07:50:30.80#ibcon#enter sib2, iclass 33, count 0 2006.217.07:50:30.80#ibcon#flushed, iclass 33, count 0 2006.217.07:50:30.80#ibcon#about to write, iclass 33, count 0 2006.217.07:50:30.80#ibcon#wrote, iclass 33, count 0 2006.217.07:50:30.80#ibcon#about to read 3, iclass 33, count 0 2006.217.07:50:30.82#ibcon#read 3, iclass 33, count 0 2006.217.07:50:30.82#ibcon#about to read 4, iclass 33, count 0 2006.217.07:50:30.82#ibcon#read 4, iclass 33, count 0 2006.217.07:50:30.82#ibcon#about to read 5, iclass 33, count 0 2006.217.07:50:30.82#ibcon#read 5, iclass 33, count 0 2006.217.07:50:30.82#ibcon#about to read 6, iclass 33, count 0 2006.217.07:50:30.82#ibcon#read 6, iclass 33, count 0 2006.217.07:50:30.82#ibcon#end of sib2, iclass 33, count 0 2006.217.07:50:30.82#ibcon#*mode == 0, iclass 33, count 0 2006.217.07:50:30.82#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.217.07:50:30.82#ibcon#[27=USB\r\n] 2006.217.07:50:30.82#ibcon#*before write, iclass 33, count 0 2006.217.07:50:30.82#ibcon#enter sib2, iclass 33, count 0 2006.217.07:50:30.82#ibcon#flushed, iclass 33, count 0 2006.217.07:50:30.82#ibcon#about to write, iclass 33, count 0 2006.217.07:50:30.82#ibcon#wrote, iclass 33, count 0 2006.217.07:50:30.82#ibcon#about to read 3, iclass 33, count 0 2006.217.07:50:30.85#ibcon#read 3, iclass 33, count 0 2006.217.07:50:30.85#ibcon#about to read 4, iclass 33, count 0 2006.217.07:50:30.85#ibcon#read 4, iclass 33, count 0 2006.217.07:50:30.85#ibcon#about to read 5, iclass 33, count 0 2006.217.07:50:30.85#ibcon#read 5, iclass 33, count 0 2006.217.07:50:30.85#ibcon#about to read 6, iclass 33, count 0 2006.217.07:50:30.85#ibcon#read 6, iclass 33, count 0 2006.217.07:50:30.85#ibcon#end of sib2, iclass 33, count 0 2006.217.07:50:30.85#ibcon#*after write, iclass 33, count 0 2006.217.07:50:30.85#ibcon#*before return 0, iclass 33, count 0 2006.217.07:50:30.85#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.217.07:50:30.85#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.217.07:50:30.85#ibcon#about to clear, iclass 33 cls_cnt 0 2006.217.07:50:30.85#ibcon#cleared, iclass 33 cls_cnt 0 2006.217.07:50:30.85$vc4f8/vblo=2,640.99 2006.217.07:50:30.85#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.217.07:50:30.85#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.217.07:50:30.85#ibcon#ireg 17 cls_cnt 0 2006.217.07:50:30.85#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.217.07:50:30.85#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.217.07:50:30.85#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.217.07:50:30.85#ibcon#enter wrdev, iclass 35, count 0 2006.217.07:50:30.85#ibcon#first serial, iclass 35, count 0 2006.217.07:50:30.85#ibcon#enter sib2, iclass 35, count 0 2006.217.07:50:30.85#ibcon#flushed, iclass 35, count 0 2006.217.07:50:30.85#ibcon#about to write, iclass 35, count 0 2006.217.07:50:30.85#ibcon#wrote, iclass 35, count 0 2006.217.07:50:30.85#ibcon#about to read 3, iclass 35, count 0 2006.217.07:50:30.87#ibcon#read 3, iclass 35, count 0 2006.217.07:50:30.87#ibcon#about to read 4, iclass 35, count 0 2006.217.07:50:30.87#ibcon#read 4, iclass 35, count 0 2006.217.07:50:30.87#ibcon#about to read 5, iclass 35, count 0 2006.217.07:50:30.87#ibcon#read 5, iclass 35, count 0 2006.217.07:50:30.87#ibcon#about to read 6, iclass 35, count 0 2006.217.07:50:30.87#ibcon#read 6, iclass 35, count 0 2006.217.07:50:30.87#ibcon#end of sib2, iclass 35, count 0 2006.217.07:50:30.87#ibcon#*mode == 0, iclass 35, count 0 2006.217.07:50:30.87#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.217.07:50:30.87#ibcon#[28=FRQ=02,640.99\r\n] 2006.217.07:50:30.87#ibcon#*before write, iclass 35, count 0 2006.217.07:50:30.87#ibcon#enter sib2, iclass 35, count 0 2006.217.07:50:30.87#ibcon#flushed, iclass 35, count 0 2006.217.07:50:30.87#ibcon#about to write, iclass 35, count 0 2006.217.07:50:30.87#ibcon#wrote, iclass 35, count 0 2006.217.07:50:30.87#ibcon#about to read 3, iclass 35, count 0 2006.217.07:50:30.91#ibcon#read 3, iclass 35, count 0 2006.217.07:50:30.91#ibcon#about to read 4, iclass 35, count 0 2006.217.07:50:30.91#ibcon#read 4, iclass 35, count 0 2006.217.07:50:30.91#ibcon#about to read 5, iclass 35, count 0 2006.217.07:50:30.91#ibcon#read 5, iclass 35, count 0 2006.217.07:50:30.91#ibcon#about to read 6, iclass 35, count 0 2006.217.07:50:30.91#ibcon#read 6, iclass 35, count 0 2006.217.07:50:30.91#ibcon#end of sib2, iclass 35, count 0 2006.217.07:50:30.91#ibcon#*after write, iclass 35, count 0 2006.217.07:50:30.91#ibcon#*before return 0, iclass 35, count 0 2006.217.07:50:30.91#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.217.07:50:30.91#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.217.07:50:30.91#ibcon#about to clear, iclass 35 cls_cnt 0 2006.217.07:50:30.91#ibcon#cleared, iclass 35 cls_cnt 0 2006.217.07:50:30.91$vc4f8/vb=2,4 2006.217.07:50:30.91#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.217.07:50:30.91#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.217.07:50:30.91#ibcon#ireg 11 cls_cnt 2 2006.217.07:50:30.91#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.217.07:50:30.97#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.217.07:50:30.97#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.217.07:50:30.97#ibcon#enter wrdev, iclass 37, count 2 2006.217.07:50:30.97#ibcon#first serial, iclass 37, count 2 2006.217.07:50:30.97#ibcon#enter sib2, iclass 37, count 2 2006.217.07:50:30.97#ibcon#flushed, iclass 37, count 2 2006.217.07:50:30.97#ibcon#about to write, iclass 37, count 2 2006.217.07:50:30.97#ibcon#wrote, iclass 37, count 2 2006.217.07:50:30.97#ibcon#about to read 3, iclass 37, count 2 2006.217.07:50:30.99#ibcon#read 3, iclass 37, count 2 2006.217.07:50:30.99#ibcon#about to read 4, iclass 37, count 2 2006.217.07:50:30.99#ibcon#read 4, iclass 37, count 2 2006.217.07:50:30.99#ibcon#about to read 5, iclass 37, count 2 2006.217.07:50:30.99#ibcon#read 5, iclass 37, count 2 2006.217.07:50:30.99#ibcon#about to read 6, iclass 37, count 2 2006.217.07:50:30.99#ibcon#read 6, iclass 37, count 2 2006.217.07:50:30.99#ibcon#end of sib2, iclass 37, count 2 2006.217.07:50:30.99#ibcon#*mode == 0, iclass 37, count 2 2006.217.07:50:30.99#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.217.07:50:30.99#ibcon#[27=AT02-04\r\n] 2006.217.07:50:30.99#ibcon#*before write, iclass 37, count 2 2006.217.07:50:30.99#ibcon#enter sib2, iclass 37, count 2 2006.217.07:50:30.99#ibcon#flushed, iclass 37, count 2 2006.217.07:50:30.99#ibcon#about to write, iclass 37, count 2 2006.217.07:50:30.99#ibcon#wrote, iclass 37, count 2 2006.217.07:50:30.99#ibcon#about to read 3, iclass 37, count 2 2006.217.07:50:31.02#ibcon#read 3, iclass 37, count 2 2006.217.07:50:31.02#ibcon#about to read 4, iclass 37, count 2 2006.217.07:50:31.02#ibcon#read 4, iclass 37, count 2 2006.217.07:50:31.02#ibcon#about to read 5, iclass 37, count 2 2006.217.07:50:31.02#ibcon#read 5, iclass 37, count 2 2006.217.07:50:31.02#ibcon#about to read 6, iclass 37, count 2 2006.217.07:50:31.02#ibcon#read 6, iclass 37, count 2 2006.217.07:50:31.02#ibcon#end of sib2, iclass 37, count 2 2006.217.07:50:31.02#ibcon#*after write, iclass 37, count 2 2006.217.07:50:31.02#ibcon#*before return 0, iclass 37, count 2 2006.217.07:50:31.02#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.217.07:50:31.02#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.217.07:50:31.02#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.217.07:50:31.02#ibcon#ireg 7 cls_cnt 0 2006.217.07:50:31.02#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.217.07:50:31.14#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.217.07:50:31.14#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.217.07:50:31.14#ibcon#enter wrdev, iclass 37, count 0 2006.217.07:50:31.14#ibcon#first serial, iclass 37, count 0 2006.217.07:50:31.14#ibcon#enter sib2, iclass 37, count 0 2006.217.07:50:31.14#ibcon#flushed, iclass 37, count 0 2006.217.07:50:31.14#ibcon#about to write, iclass 37, count 0 2006.217.07:50:31.14#ibcon#wrote, iclass 37, count 0 2006.217.07:50:31.14#ibcon#about to read 3, iclass 37, count 0 2006.217.07:50:31.16#ibcon#read 3, iclass 37, count 0 2006.217.07:50:31.16#ibcon#about to read 4, iclass 37, count 0 2006.217.07:50:31.16#ibcon#read 4, iclass 37, count 0 2006.217.07:50:31.16#ibcon#about to read 5, iclass 37, count 0 2006.217.07:50:31.16#ibcon#read 5, iclass 37, count 0 2006.217.07:50:31.16#ibcon#about to read 6, iclass 37, count 0 2006.217.07:50:31.16#ibcon#read 6, iclass 37, count 0 2006.217.07:50:31.16#ibcon#end of sib2, iclass 37, count 0 2006.217.07:50:31.16#ibcon#*mode == 0, iclass 37, count 0 2006.217.07:50:31.16#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.217.07:50:31.16#ibcon#[27=USB\r\n] 2006.217.07:50:31.16#ibcon#*before write, iclass 37, count 0 2006.217.07:50:31.16#ibcon#enter sib2, iclass 37, count 0 2006.217.07:50:31.16#ibcon#flushed, iclass 37, count 0 2006.217.07:50:31.16#ibcon#about to write, iclass 37, count 0 2006.217.07:50:31.16#ibcon#wrote, iclass 37, count 0 2006.217.07:50:31.16#ibcon#about to read 3, iclass 37, count 0 2006.217.07:50:31.19#ibcon#read 3, iclass 37, count 0 2006.217.07:50:31.19#ibcon#about to read 4, iclass 37, count 0 2006.217.07:50:31.19#ibcon#read 4, iclass 37, count 0 2006.217.07:50:31.19#ibcon#about to read 5, iclass 37, count 0 2006.217.07:50:31.19#ibcon#read 5, iclass 37, count 0 2006.217.07:50:31.19#ibcon#about to read 6, iclass 37, count 0 2006.217.07:50:31.19#ibcon#read 6, iclass 37, count 0 2006.217.07:50:31.19#ibcon#end of sib2, iclass 37, count 0 2006.217.07:50:31.19#ibcon#*after write, iclass 37, count 0 2006.217.07:50:31.19#ibcon#*before return 0, iclass 37, count 0 2006.217.07:50:31.19#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.217.07:50:31.19#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.217.07:50:31.19#ibcon#about to clear, iclass 37 cls_cnt 0 2006.217.07:50:31.19#ibcon#cleared, iclass 37 cls_cnt 0 2006.217.07:50:31.19$vc4f8/vblo=3,656.99 2006.217.07:50:31.19#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.217.07:50:31.19#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.217.07:50:31.19#ibcon#ireg 17 cls_cnt 0 2006.217.07:50:31.19#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.217.07:50:31.19#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.217.07:50:31.19#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.217.07:50:31.19#ibcon#enter wrdev, iclass 39, count 0 2006.217.07:50:31.19#ibcon#first serial, iclass 39, count 0 2006.217.07:50:31.19#ibcon#enter sib2, iclass 39, count 0 2006.217.07:50:31.19#ibcon#flushed, iclass 39, count 0 2006.217.07:50:31.19#ibcon#about to write, iclass 39, count 0 2006.217.07:50:31.19#ibcon#wrote, iclass 39, count 0 2006.217.07:50:31.19#ibcon#about to read 3, iclass 39, count 0 2006.217.07:50:31.21#ibcon#read 3, iclass 39, count 0 2006.217.07:50:31.21#ibcon#about to read 4, iclass 39, count 0 2006.217.07:50:31.21#ibcon#read 4, iclass 39, count 0 2006.217.07:50:31.21#ibcon#about to read 5, iclass 39, count 0 2006.217.07:50:31.21#ibcon#read 5, iclass 39, count 0 2006.217.07:50:31.21#ibcon#about to read 6, iclass 39, count 0 2006.217.07:50:31.21#ibcon#read 6, iclass 39, count 0 2006.217.07:50:31.21#ibcon#end of sib2, iclass 39, count 0 2006.217.07:50:31.21#ibcon#*mode == 0, iclass 39, count 0 2006.217.07:50:31.21#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.217.07:50:31.21#ibcon#[28=FRQ=03,656.99\r\n] 2006.217.07:50:31.21#ibcon#*before write, iclass 39, count 0 2006.217.07:50:31.21#ibcon#enter sib2, iclass 39, count 0 2006.217.07:50:31.21#ibcon#flushed, iclass 39, count 0 2006.217.07:50:31.21#ibcon#about to write, iclass 39, count 0 2006.217.07:50:31.21#ibcon#wrote, iclass 39, count 0 2006.217.07:50:31.21#ibcon#about to read 3, iclass 39, count 0 2006.217.07:50:31.25#ibcon#read 3, iclass 39, count 0 2006.217.07:50:31.25#ibcon#about to read 4, iclass 39, count 0 2006.217.07:50:31.25#ibcon#read 4, iclass 39, count 0 2006.217.07:50:31.25#ibcon#about to read 5, iclass 39, count 0 2006.217.07:50:31.25#ibcon#read 5, iclass 39, count 0 2006.217.07:50:31.25#ibcon#about to read 6, iclass 39, count 0 2006.217.07:50:31.25#ibcon#read 6, iclass 39, count 0 2006.217.07:50:31.25#ibcon#end of sib2, iclass 39, count 0 2006.217.07:50:31.25#ibcon#*after write, iclass 39, count 0 2006.217.07:50:31.25#ibcon#*before return 0, iclass 39, count 0 2006.217.07:50:31.25#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.217.07:50:31.25#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.217.07:50:31.25#ibcon#about to clear, iclass 39 cls_cnt 0 2006.217.07:50:31.25#ibcon#cleared, iclass 39 cls_cnt 0 2006.217.07:50:31.25$vc4f8/vb=3,4 2006.217.07:50:31.25#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.217.07:50:31.25#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.217.07:50:31.25#ibcon#ireg 11 cls_cnt 2 2006.217.07:50:31.25#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.217.07:50:31.31#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.217.07:50:31.31#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.217.07:50:31.31#ibcon#enter wrdev, iclass 3, count 2 2006.217.07:50:31.31#ibcon#first serial, iclass 3, count 2 2006.217.07:50:31.31#ibcon#enter sib2, iclass 3, count 2 2006.217.07:50:31.31#ibcon#flushed, iclass 3, count 2 2006.217.07:50:31.31#ibcon#about to write, iclass 3, count 2 2006.217.07:50:31.31#ibcon#wrote, iclass 3, count 2 2006.217.07:50:31.31#ibcon#about to read 3, iclass 3, count 2 2006.217.07:50:31.33#ibcon#read 3, iclass 3, count 2 2006.217.07:50:31.33#ibcon#about to read 4, iclass 3, count 2 2006.217.07:50:31.33#ibcon#read 4, iclass 3, count 2 2006.217.07:50:31.33#ibcon#about to read 5, iclass 3, count 2 2006.217.07:50:31.33#ibcon#read 5, iclass 3, count 2 2006.217.07:50:31.33#ibcon#about to read 6, iclass 3, count 2 2006.217.07:50:31.33#ibcon#read 6, iclass 3, count 2 2006.217.07:50:31.33#ibcon#end of sib2, iclass 3, count 2 2006.217.07:50:31.33#ibcon#*mode == 0, iclass 3, count 2 2006.217.07:50:31.33#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.217.07:50:31.33#ibcon#[27=AT03-04\r\n] 2006.217.07:50:31.33#ibcon#*before write, iclass 3, count 2 2006.217.07:50:31.33#ibcon#enter sib2, iclass 3, count 2 2006.217.07:50:31.33#ibcon#flushed, iclass 3, count 2 2006.217.07:50:31.33#ibcon#about to write, iclass 3, count 2 2006.217.07:50:31.33#ibcon#wrote, iclass 3, count 2 2006.217.07:50:31.33#ibcon#about to read 3, iclass 3, count 2 2006.217.07:50:31.36#ibcon#read 3, iclass 3, count 2 2006.217.07:50:31.36#ibcon#about to read 4, iclass 3, count 2 2006.217.07:50:31.36#ibcon#read 4, iclass 3, count 2 2006.217.07:50:31.36#ibcon#about to read 5, iclass 3, count 2 2006.217.07:50:31.36#ibcon#read 5, iclass 3, count 2 2006.217.07:50:31.36#ibcon#about to read 6, iclass 3, count 2 2006.217.07:50:31.36#ibcon#read 6, iclass 3, count 2 2006.217.07:50:31.36#ibcon#end of sib2, iclass 3, count 2 2006.217.07:50:31.36#ibcon#*after write, iclass 3, count 2 2006.217.07:50:31.36#ibcon#*before return 0, iclass 3, count 2 2006.217.07:50:31.36#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.217.07:50:31.36#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.217.07:50:31.36#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.217.07:50:31.36#ibcon#ireg 7 cls_cnt 0 2006.217.07:50:31.36#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.217.07:50:31.48#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.217.07:50:31.48#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.217.07:50:31.48#ibcon#enter wrdev, iclass 3, count 0 2006.217.07:50:31.48#ibcon#first serial, iclass 3, count 0 2006.217.07:50:31.48#ibcon#enter sib2, iclass 3, count 0 2006.217.07:50:31.48#ibcon#flushed, iclass 3, count 0 2006.217.07:50:31.48#ibcon#about to write, iclass 3, count 0 2006.217.07:50:31.48#ibcon#wrote, iclass 3, count 0 2006.217.07:50:31.48#ibcon#about to read 3, iclass 3, count 0 2006.217.07:50:31.50#ibcon#read 3, iclass 3, count 0 2006.217.07:50:31.50#ibcon#about to read 4, iclass 3, count 0 2006.217.07:50:31.50#ibcon#read 4, iclass 3, count 0 2006.217.07:50:31.50#ibcon#about to read 5, iclass 3, count 0 2006.217.07:50:31.50#ibcon#read 5, iclass 3, count 0 2006.217.07:50:31.50#ibcon#about to read 6, iclass 3, count 0 2006.217.07:50:31.50#ibcon#read 6, iclass 3, count 0 2006.217.07:50:31.50#ibcon#end of sib2, iclass 3, count 0 2006.217.07:50:31.50#ibcon#*mode == 0, iclass 3, count 0 2006.217.07:50:31.50#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.217.07:50:31.50#ibcon#[27=USB\r\n] 2006.217.07:50:31.50#ibcon#*before write, iclass 3, count 0 2006.217.07:50:31.50#ibcon#enter sib2, iclass 3, count 0 2006.217.07:50:31.50#ibcon#flushed, iclass 3, count 0 2006.217.07:50:31.50#ibcon#about to write, iclass 3, count 0 2006.217.07:50:31.50#ibcon#wrote, iclass 3, count 0 2006.217.07:50:31.50#ibcon#about to read 3, iclass 3, count 0 2006.217.07:50:31.53#ibcon#read 3, iclass 3, count 0 2006.217.07:50:31.53#ibcon#about to read 4, iclass 3, count 0 2006.217.07:50:31.53#ibcon#read 4, iclass 3, count 0 2006.217.07:50:31.53#ibcon#about to read 5, iclass 3, count 0 2006.217.07:50:31.53#ibcon#read 5, iclass 3, count 0 2006.217.07:50:31.53#ibcon#about to read 6, iclass 3, count 0 2006.217.07:50:31.53#ibcon#read 6, iclass 3, count 0 2006.217.07:50:31.53#ibcon#end of sib2, iclass 3, count 0 2006.217.07:50:31.53#ibcon#*after write, iclass 3, count 0 2006.217.07:50:31.53#ibcon#*before return 0, iclass 3, count 0 2006.217.07:50:31.53#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.217.07:50:31.53#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.217.07:50:31.53#ibcon#about to clear, iclass 3 cls_cnt 0 2006.217.07:50:31.53#ibcon#cleared, iclass 3 cls_cnt 0 2006.217.07:50:31.53$vc4f8/vblo=4,712.99 2006.217.07:50:31.53#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.217.07:50:31.53#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.217.07:50:31.53#ibcon#ireg 17 cls_cnt 0 2006.217.07:50:31.53#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.217.07:50:31.53#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.217.07:50:31.53#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.217.07:50:31.53#ibcon#enter wrdev, iclass 5, count 0 2006.217.07:50:31.53#ibcon#first serial, iclass 5, count 0 2006.217.07:50:31.53#ibcon#enter sib2, iclass 5, count 0 2006.217.07:50:31.53#ibcon#flushed, iclass 5, count 0 2006.217.07:50:31.53#ibcon#about to write, iclass 5, count 0 2006.217.07:50:31.53#ibcon#wrote, iclass 5, count 0 2006.217.07:50:31.53#ibcon#about to read 3, iclass 5, count 0 2006.217.07:50:31.55#ibcon#read 3, iclass 5, count 0 2006.217.07:50:31.55#ibcon#about to read 4, iclass 5, count 0 2006.217.07:50:31.55#ibcon#read 4, iclass 5, count 0 2006.217.07:50:31.55#ibcon#about to read 5, iclass 5, count 0 2006.217.07:50:31.55#ibcon#read 5, iclass 5, count 0 2006.217.07:50:31.55#ibcon#about to read 6, iclass 5, count 0 2006.217.07:50:31.55#ibcon#read 6, iclass 5, count 0 2006.217.07:50:31.55#ibcon#end of sib2, iclass 5, count 0 2006.217.07:50:31.55#ibcon#*mode == 0, iclass 5, count 0 2006.217.07:50:31.55#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.217.07:50:31.55#ibcon#[28=FRQ=04,712.99\r\n] 2006.217.07:50:31.55#ibcon#*before write, iclass 5, count 0 2006.217.07:50:31.55#ibcon#enter sib2, iclass 5, count 0 2006.217.07:50:31.55#ibcon#flushed, iclass 5, count 0 2006.217.07:50:31.55#ibcon#about to write, iclass 5, count 0 2006.217.07:50:31.55#ibcon#wrote, iclass 5, count 0 2006.217.07:50:31.55#ibcon#about to read 3, iclass 5, count 0 2006.217.07:50:31.59#ibcon#read 3, iclass 5, count 0 2006.217.07:50:31.59#ibcon#about to read 4, iclass 5, count 0 2006.217.07:50:31.59#ibcon#read 4, iclass 5, count 0 2006.217.07:50:31.59#ibcon#about to read 5, iclass 5, count 0 2006.217.07:50:31.59#ibcon#read 5, iclass 5, count 0 2006.217.07:50:31.59#ibcon#about to read 6, iclass 5, count 0 2006.217.07:50:31.59#ibcon#read 6, iclass 5, count 0 2006.217.07:50:31.59#ibcon#end of sib2, iclass 5, count 0 2006.217.07:50:31.59#ibcon#*after write, iclass 5, count 0 2006.217.07:50:31.59#ibcon#*before return 0, iclass 5, count 0 2006.217.07:50:31.59#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.217.07:50:31.59#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.217.07:50:31.59#ibcon#about to clear, iclass 5 cls_cnt 0 2006.217.07:50:31.59#ibcon#cleared, iclass 5 cls_cnt 0 2006.217.07:50:31.59$vc4f8/vb=4,4 2006.217.07:50:31.59#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.217.07:50:31.59#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.217.07:50:31.59#ibcon#ireg 11 cls_cnt 2 2006.217.07:50:31.59#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.217.07:50:31.65#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.217.07:50:31.65#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.217.07:50:31.65#ibcon#enter wrdev, iclass 7, count 2 2006.217.07:50:31.65#ibcon#first serial, iclass 7, count 2 2006.217.07:50:31.65#ibcon#enter sib2, iclass 7, count 2 2006.217.07:50:31.65#ibcon#flushed, iclass 7, count 2 2006.217.07:50:31.65#ibcon#about to write, iclass 7, count 2 2006.217.07:50:31.65#ibcon#wrote, iclass 7, count 2 2006.217.07:50:31.65#ibcon#about to read 3, iclass 7, count 2 2006.217.07:50:31.67#ibcon#read 3, iclass 7, count 2 2006.217.07:50:31.67#ibcon#about to read 4, iclass 7, count 2 2006.217.07:50:31.67#ibcon#read 4, iclass 7, count 2 2006.217.07:50:31.67#ibcon#about to read 5, iclass 7, count 2 2006.217.07:50:31.67#ibcon#read 5, iclass 7, count 2 2006.217.07:50:31.67#ibcon#about to read 6, iclass 7, count 2 2006.217.07:50:31.67#ibcon#read 6, iclass 7, count 2 2006.217.07:50:31.67#ibcon#end of sib2, iclass 7, count 2 2006.217.07:50:31.67#ibcon#*mode == 0, iclass 7, count 2 2006.217.07:50:31.67#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.217.07:50:31.67#ibcon#[27=AT04-04\r\n] 2006.217.07:50:31.67#ibcon#*before write, iclass 7, count 2 2006.217.07:50:31.67#ibcon#enter sib2, iclass 7, count 2 2006.217.07:50:31.67#ibcon#flushed, iclass 7, count 2 2006.217.07:50:31.67#ibcon#about to write, iclass 7, count 2 2006.217.07:50:31.67#ibcon#wrote, iclass 7, count 2 2006.217.07:50:31.67#ibcon#about to read 3, iclass 7, count 2 2006.217.07:50:31.70#ibcon#read 3, iclass 7, count 2 2006.217.07:50:31.70#ibcon#about to read 4, iclass 7, count 2 2006.217.07:50:31.70#ibcon#read 4, iclass 7, count 2 2006.217.07:50:31.70#ibcon#about to read 5, iclass 7, count 2 2006.217.07:50:31.70#ibcon#read 5, iclass 7, count 2 2006.217.07:50:31.70#ibcon#about to read 6, iclass 7, count 2 2006.217.07:50:31.70#ibcon#read 6, iclass 7, count 2 2006.217.07:50:31.70#ibcon#end of sib2, iclass 7, count 2 2006.217.07:50:31.70#ibcon#*after write, iclass 7, count 2 2006.217.07:50:31.70#ibcon#*before return 0, iclass 7, count 2 2006.217.07:50:31.70#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.217.07:50:31.70#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.217.07:50:31.70#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.217.07:50:31.70#ibcon#ireg 7 cls_cnt 0 2006.217.07:50:31.70#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.217.07:50:31.82#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.217.07:50:31.82#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.217.07:50:31.82#ibcon#enter wrdev, iclass 7, count 0 2006.217.07:50:31.82#ibcon#first serial, iclass 7, count 0 2006.217.07:50:31.82#ibcon#enter sib2, iclass 7, count 0 2006.217.07:50:31.82#ibcon#flushed, iclass 7, count 0 2006.217.07:50:31.82#ibcon#about to write, iclass 7, count 0 2006.217.07:50:31.82#ibcon#wrote, iclass 7, count 0 2006.217.07:50:31.82#ibcon#about to read 3, iclass 7, count 0 2006.217.07:50:31.84#ibcon#read 3, iclass 7, count 0 2006.217.07:50:31.84#ibcon#about to read 4, iclass 7, count 0 2006.217.07:50:31.84#ibcon#read 4, iclass 7, count 0 2006.217.07:50:31.84#ibcon#about to read 5, iclass 7, count 0 2006.217.07:50:31.84#ibcon#read 5, iclass 7, count 0 2006.217.07:50:31.84#ibcon#about to read 6, iclass 7, count 0 2006.217.07:50:31.84#ibcon#read 6, iclass 7, count 0 2006.217.07:50:31.84#ibcon#end of sib2, iclass 7, count 0 2006.217.07:50:31.84#ibcon#*mode == 0, iclass 7, count 0 2006.217.07:50:31.84#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.217.07:50:31.84#ibcon#[27=USB\r\n] 2006.217.07:50:31.84#ibcon#*before write, iclass 7, count 0 2006.217.07:50:31.84#ibcon#enter sib2, iclass 7, count 0 2006.217.07:50:31.84#ibcon#flushed, iclass 7, count 0 2006.217.07:50:31.84#ibcon#about to write, iclass 7, count 0 2006.217.07:50:31.84#ibcon#wrote, iclass 7, count 0 2006.217.07:50:31.84#ibcon#about to read 3, iclass 7, count 0 2006.217.07:50:31.87#ibcon#read 3, iclass 7, count 0 2006.217.07:50:31.87#ibcon#about to read 4, iclass 7, count 0 2006.217.07:50:31.87#ibcon#read 4, iclass 7, count 0 2006.217.07:50:31.87#ibcon#about to read 5, iclass 7, count 0 2006.217.07:50:31.87#ibcon#read 5, iclass 7, count 0 2006.217.07:50:31.87#ibcon#about to read 6, iclass 7, count 0 2006.217.07:50:31.87#ibcon#read 6, iclass 7, count 0 2006.217.07:50:31.87#ibcon#end of sib2, iclass 7, count 0 2006.217.07:50:31.87#ibcon#*after write, iclass 7, count 0 2006.217.07:50:31.87#ibcon#*before return 0, iclass 7, count 0 2006.217.07:50:31.87#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.217.07:50:31.87#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.217.07:50:31.87#ibcon#about to clear, iclass 7 cls_cnt 0 2006.217.07:50:31.87#ibcon#cleared, iclass 7 cls_cnt 0 2006.217.07:50:31.87$vc4f8/vblo=5,744.99 2006.217.07:50:31.87#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.217.07:50:31.87#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.217.07:50:31.87#ibcon#ireg 17 cls_cnt 0 2006.217.07:50:31.87#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.217.07:50:31.87#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.217.07:50:31.87#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.217.07:50:31.87#ibcon#enter wrdev, iclass 11, count 0 2006.217.07:50:31.87#ibcon#first serial, iclass 11, count 0 2006.217.07:50:31.87#ibcon#enter sib2, iclass 11, count 0 2006.217.07:50:31.87#ibcon#flushed, iclass 11, count 0 2006.217.07:50:31.87#ibcon#about to write, iclass 11, count 0 2006.217.07:50:31.87#ibcon#wrote, iclass 11, count 0 2006.217.07:50:31.87#ibcon#about to read 3, iclass 11, count 0 2006.217.07:50:31.90#ibcon#read 3, iclass 11, count 0 2006.217.07:50:31.90#ibcon#about to read 4, iclass 11, count 0 2006.217.07:50:31.90#ibcon#read 4, iclass 11, count 0 2006.217.07:50:31.90#ibcon#about to read 5, iclass 11, count 0 2006.217.07:50:31.90#ibcon#read 5, iclass 11, count 0 2006.217.07:50:31.90#ibcon#about to read 6, iclass 11, count 0 2006.217.07:50:31.90#ibcon#read 6, iclass 11, count 0 2006.217.07:50:31.90#ibcon#end of sib2, iclass 11, count 0 2006.217.07:50:31.90#ibcon#*mode == 0, iclass 11, count 0 2006.217.07:50:31.90#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.217.07:50:31.90#ibcon#[28=FRQ=05,744.99\r\n] 2006.217.07:50:31.90#ibcon#*before write, iclass 11, count 0 2006.217.07:50:31.90#ibcon#enter sib2, iclass 11, count 0 2006.217.07:50:31.90#ibcon#flushed, iclass 11, count 0 2006.217.07:50:31.90#ibcon#about to write, iclass 11, count 0 2006.217.07:50:31.90#ibcon#wrote, iclass 11, count 0 2006.217.07:50:31.90#ibcon#about to read 3, iclass 11, count 0 2006.217.07:50:31.94#ibcon#read 3, iclass 11, count 0 2006.217.07:50:31.94#ibcon#about to read 4, iclass 11, count 0 2006.217.07:50:31.94#ibcon#read 4, iclass 11, count 0 2006.217.07:50:31.94#ibcon#about to read 5, iclass 11, count 0 2006.217.07:50:31.94#ibcon#read 5, iclass 11, count 0 2006.217.07:50:31.94#ibcon#about to read 6, iclass 11, count 0 2006.217.07:50:31.94#ibcon#read 6, iclass 11, count 0 2006.217.07:50:31.94#ibcon#end of sib2, iclass 11, count 0 2006.217.07:50:31.94#ibcon#*after write, iclass 11, count 0 2006.217.07:50:31.94#ibcon#*before return 0, iclass 11, count 0 2006.217.07:50:31.94#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.217.07:50:31.94#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.217.07:50:31.94#ibcon#about to clear, iclass 11 cls_cnt 0 2006.217.07:50:31.94#ibcon#cleared, iclass 11 cls_cnt 0 2006.217.07:50:31.94$vc4f8/vb=5,4 2006.217.07:50:31.94#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.217.07:50:31.94#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.217.07:50:31.94#ibcon#ireg 11 cls_cnt 2 2006.217.07:50:31.94#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.217.07:50:31.99#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.217.07:50:31.99#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.217.07:50:31.99#ibcon#enter wrdev, iclass 13, count 2 2006.217.07:50:31.99#ibcon#first serial, iclass 13, count 2 2006.217.07:50:31.99#ibcon#enter sib2, iclass 13, count 2 2006.217.07:50:31.99#ibcon#flushed, iclass 13, count 2 2006.217.07:50:31.99#ibcon#about to write, iclass 13, count 2 2006.217.07:50:31.99#ibcon#wrote, iclass 13, count 2 2006.217.07:50:31.99#ibcon#about to read 3, iclass 13, count 2 2006.217.07:50:32.00#abcon#<5=/05 3.2 8.5 31.22 641008.6\r\n> 2006.217.07:50:32.01#ibcon#read 3, iclass 13, count 2 2006.217.07:50:32.01#ibcon#about to read 4, iclass 13, count 2 2006.217.07:50:32.01#ibcon#read 4, iclass 13, count 2 2006.217.07:50:32.01#ibcon#about to read 5, iclass 13, count 2 2006.217.07:50:32.01#ibcon#read 5, iclass 13, count 2 2006.217.07:50:32.01#ibcon#about to read 6, iclass 13, count 2 2006.217.07:50:32.01#ibcon#read 6, iclass 13, count 2 2006.217.07:50:32.01#ibcon#end of sib2, iclass 13, count 2 2006.217.07:50:32.01#ibcon#*mode == 0, iclass 13, count 2 2006.217.07:50:32.01#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.217.07:50:32.01#ibcon#[27=AT05-04\r\n] 2006.217.07:50:32.01#ibcon#*before write, iclass 13, count 2 2006.217.07:50:32.01#ibcon#enter sib2, iclass 13, count 2 2006.217.07:50:32.01#ibcon#flushed, iclass 13, count 2 2006.217.07:50:32.01#ibcon#about to write, iclass 13, count 2 2006.217.07:50:32.01#ibcon#wrote, iclass 13, count 2 2006.217.07:50:32.01#ibcon#about to read 3, iclass 13, count 2 2006.217.07:50:32.02#abcon#{5=INTERFACE CLEAR} 2006.217.07:50:32.04#ibcon#read 3, iclass 13, count 2 2006.217.07:50:32.04#ibcon#about to read 4, iclass 13, count 2 2006.217.07:50:32.04#ibcon#read 4, iclass 13, count 2 2006.217.07:50:32.04#ibcon#about to read 5, iclass 13, count 2 2006.217.07:50:32.04#ibcon#read 5, iclass 13, count 2 2006.217.07:50:32.04#ibcon#about to read 6, iclass 13, count 2 2006.217.07:50:32.04#ibcon#read 6, iclass 13, count 2 2006.217.07:50:32.04#ibcon#end of sib2, iclass 13, count 2 2006.217.07:50:32.04#ibcon#*after write, iclass 13, count 2 2006.217.07:50:32.04#ibcon#*before return 0, iclass 13, count 2 2006.217.07:50:32.04#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.217.07:50:32.04#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.217.07:50:32.04#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.217.07:50:32.04#ibcon#ireg 7 cls_cnt 0 2006.217.07:50:32.04#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.217.07:50:32.08#abcon#[5=S1D000X0/0*\r\n] 2006.217.07:50:32.16#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.217.07:50:32.16#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.217.07:50:32.16#ibcon#enter wrdev, iclass 13, count 0 2006.217.07:50:32.16#ibcon#first serial, iclass 13, count 0 2006.217.07:50:32.16#ibcon#enter sib2, iclass 13, count 0 2006.217.07:50:32.16#ibcon#flushed, iclass 13, count 0 2006.217.07:50:32.16#ibcon#about to write, iclass 13, count 0 2006.217.07:50:32.16#ibcon#wrote, iclass 13, count 0 2006.217.07:50:32.16#ibcon#about to read 3, iclass 13, count 0 2006.217.07:50:32.18#ibcon#read 3, iclass 13, count 0 2006.217.07:50:32.18#ibcon#about to read 4, iclass 13, count 0 2006.217.07:50:32.18#ibcon#read 4, iclass 13, count 0 2006.217.07:50:32.18#ibcon#about to read 5, iclass 13, count 0 2006.217.07:50:32.18#ibcon#read 5, iclass 13, count 0 2006.217.07:50:32.18#ibcon#about to read 6, iclass 13, count 0 2006.217.07:50:32.18#ibcon#read 6, iclass 13, count 0 2006.217.07:50:32.18#ibcon#end of sib2, iclass 13, count 0 2006.217.07:50:32.18#ibcon#*mode == 0, iclass 13, count 0 2006.217.07:50:32.18#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.217.07:50:32.18#ibcon#[27=USB\r\n] 2006.217.07:50:32.18#ibcon#*before write, iclass 13, count 0 2006.217.07:50:32.18#ibcon#enter sib2, iclass 13, count 0 2006.217.07:50:32.18#ibcon#flushed, iclass 13, count 0 2006.217.07:50:32.18#ibcon#about to write, iclass 13, count 0 2006.217.07:50:32.18#ibcon#wrote, iclass 13, count 0 2006.217.07:50:32.18#ibcon#about to read 3, iclass 13, count 0 2006.217.07:50:32.21#ibcon#read 3, iclass 13, count 0 2006.217.07:50:32.21#ibcon#about to read 4, iclass 13, count 0 2006.217.07:50:32.21#ibcon#read 4, iclass 13, count 0 2006.217.07:50:32.21#ibcon#about to read 5, iclass 13, count 0 2006.217.07:50:32.21#ibcon#read 5, iclass 13, count 0 2006.217.07:50:32.21#ibcon#about to read 6, iclass 13, count 0 2006.217.07:50:32.21#ibcon#read 6, iclass 13, count 0 2006.217.07:50:32.21#ibcon#end of sib2, iclass 13, count 0 2006.217.07:50:32.21#ibcon#*after write, iclass 13, count 0 2006.217.07:50:32.21#ibcon#*before return 0, iclass 13, count 0 2006.217.07:50:32.21#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.217.07:50:32.21#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.217.07:50:32.21#ibcon#about to clear, iclass 13 cls_cnt 0 2006.217.07:50:32.21#ibcon#cleared, iclass 13 cls_cnt 0 2006.217.07:50:32.21$vc4f8/vblo=6,752.99 2006.217.07:50:32.21#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.217.07:50:32.21#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.217.07:50:32.21#ibcon#ireg 17 cls_cnt 0 2006.217.07:50:32.21#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.217.07:50:32.21#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.217.07:50:32.21#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.217.07:50:32.21#ibcon#enter wrdev, iclass 19, count 0 2006.217.07:50:32.21#ibcon#first serial, iclass 19, count 0 2006.217.07:50:32.21#ibcon#enter sib2, iclass 19, count 0 2006.217.07:50:32.21#ibcon#flushed, iclass 19, count 0 2006.217.07:50:32.21#ibcon#about to write, iclass 19, count 0 2006.217.07:50:32.21#ibcon#wrote, iclass 19, count 0 2006.217.07:50:32.21#ibcon#about to read 3, iclass 19, count 0 2006.217.07:50:32.23#ibcon#read 3, iclass 19, count 0 2006.217.07:50:32.23#ibcon#about to read 4, iclass 19, count 0 2006.217.07:50:32.23#ibcon#read 4, iclass 19, count 0 2006.217.07:50:32.23#ibcon#about to read 5, iclass 19, count 0 2006.217.07:50:32.23#ibcon#read 5, iclass 19, count 0 2006.217.07:50:32.23#ibcon#about to read 6, iclass 19, count 0 2006.217.07:50:32.23#ibcon#read 6, iclass 19, count 0 2006.217.07:50:32.23#ibcon#end of sib2, iclass 19, count 0 2006.217.07:50:32.23#ibcon#*mode == 0, iclass 19, count 0 2006.217.07:50:32.23#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.217.07:50:32.23#ibcon#[28=FRQ=06,752.99\r\n] 2006.217.07:50:32.23#ibcon#*before write, iclass 19, count 0 2006.217.07:50:32.23#ibcon#enter sib2, iclass 19, count 0 2006.217.07:50:32.23#ibcon#flushed, iclass 19, count 0 2006.217.07:50:32.23#ibcon#about to write, iclass 19, count 0 2006.217.07:50:32.23#ibcon#wrote, iclass 19, count 0 2006.217.07:50:32.23#ibcon#about to read 3, iclass 19, count 0 2006.217.07:50:32.27#ibcon#read 3, iclass 19, count 0 2006.217.07:50:32.27#ibcon#about to read 4, iclass 19, count 0 2006.217.07:50:32.27#ibcon#read 4, iclass 19, count 0 2006.217.07:50:32.27#ibcon#about to read 5, iclass 19, count 0 2006.217.07:50:32.27#ibcon#read 5, iclass 19, count 0 2006.217.07:50:32.27#ibcon#about to read 6, iclass 19, count 0 2006.217.07:50:32.27#ibcon#read 6, iclass 19, count 0 2006.217.07:50:32.27#ibcon#end of sib2, iclass 19, count 0 2006.217.07:50:32.27#ibcon#*after write, iclass 19, count 0 2006.217.07:50:32.27#ibcon#*before return 0, iclass 19, count 0 2006.217.07:50:32.27#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.217.07:50:32.27#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.217.07:50:32.27#ibcon#about to clear, iclass 19 cls_cnt 0 2006.217.07:50:32.27#ibcon#cleared, iclass 19 cls_cnt 0 2006.217.07:50:32.27$vc4f8/vb=6,4 2006.217.07:50:32.27#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.217.07:50:32.27#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.217.07:50:32.27#ibcon#ireg 11 cls_cnt 2 2006.217.07:50:32.27#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.217.07:50:32.33#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.217.07:50:32.33#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.217.07:50:32.33#ibcon#enter wrdev, iclass 21, count 2 2006.217.07:50:32.33#ibcon#first serial, iclass 21, count 2 2006.217.07:50:32.33#ibcon#enter sib2, iclass 21, count 2 2006.217.07:50:32.33#ibcon#flushed, iclass 21, count 2 2006.217.07:50:32.33#ibcon#about to write, iclass 21, count 2 2006.217.07:50:32.33#ibcon#wrote, iclass 21, count 2 2006.217.07:50:32.33#ibcon#about to read 3, iclass 21, count 2 2006.217.07:50:32.35#ibcon#read 3, iclass 21, count 2 2006.217.07:50:32.35#ibcon#about to read 4, iclass 21, count 2 2006.217.07:50:32.35#ibcon#read 4, iclass 21, count 2 2006.217.07:50:32.35#ibcon#about to read 5, iclass 21, count 2 2006.217.07:50:32.35#ibcon#read 5, iclass 21, count 2 2006.217.07:50:32.35#ibcon#about to read 6, iclass 21, count 2 2006.217.07:50:32.35#ibcon#read 6, iclass 21, count 2 2006.217.07:50:32.35#ibcon#end of sib2, iclass 21, count 2 2006.217.07:50:32.35#ibcon#*mode == 0, iclass 21, count 2 2006.217.07:50:32.35#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.217.07:50:32.35#ibcon#[27=AT06-04\r\n] 2006.217.07:50:32.35#ibcon#*before write, iclass 21, count 2 2006.217.07:50:32.35#ibcon#enter sib2, iclass 21, count 2 2006.217.07:50:32.35#ibcon#flushed, iclass 21, count 2 2006.217.07:50:32.35#ibcon#about to write, iclass 21, count 2 2006.217.07:50:32.35#ibcon#wrote, iclass 21, count 2 2006.217.07:50:32.35#ibcon#about to read 3, iclass 21, count 2 2006.217.07:50:32.38#ibcon#read 3, iclass 21, count 2 2006.217.07:50:32.38#ibcon#about to read 4, iclass 21, count 2 2006.217.07:50:32.38#ibcon#read 4, iclass 21, count 2 2006.217.07:50:32.38#ibcon#about to read 5, iclass 21, count 2 2006.217.07:50:32.38#ibcon#read 5, iclass 21, count 2 2006.217.07:50:32.38#ibcon#about to read 6, iclass 21, count 2 2006.217.07:50:32.38#ibcon#read 6, iclass 21, count 2 2006.217.07:50:32.38#ibcon#end of sib2, iclass 21, count 2 2006.217.07:50:32.38#ibcon#*after write, iclass 21, count 2 2006.217.07:50:32.38#ibcon#*before return 0, iclass 21, count 2 2006.217.07:50:32.38#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.217.07:50:32.38#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.217.07:50:32.38#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.217.07:50:32.38#ibcon#ireg 7 cls_cnt 0 2006.217.07:50:32.38#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.217.07:50:32.50#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.217.07:50:32.50#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.217.07:50:32.50#ibcon#enter wrdev, iclass 21, count 0 2006.217.07:50:32.50#ibcon#first serial, iclass 21, count 0 2006.217.07:50:32.50#ibcon#enter sib2, iclass 21, count 0 2006.217.07:50:32.50#ibcon#flushed, iclass 21, count 0 2006.217.07:50:32.50#ibcon#about to write, iclass 21, count 0 2006.217.07:50:32.50#ibcon#wrote, iclass 21, count 0 2006.217.07:50:32.50#ibcon#about to read 3, iclass 21, count 0 2006.217.07:50:32.52#ibcon#read 3, iclass 21, count 0 2006.217.07:50:32.52#ibcon#about to read 4, iclass 21, count 0 2006.217.07:50:32.52#ibcon#read 4, iclass 21, count 0 2006.217.07:50:32.52#ibcon#about to read 5, iclass 21, count 0 2006.217.07:50:32.52#ibcon#read 5, iclass 21, count 0 2006.217.07:50:32.52#ibcon#about to read 6, iclass 21, count 0 2006.217.07:50:32.52#ibcon#read 6, iclass 21, count 0 2006.217.07:50:32.52#ibcon#end of sib2, iclass 21, count 0 2006.217.07:50:32.52#ibcon#*mode == 0, iclass 21, count 0 2006.217.07:50:32.52#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.217.07:50:32.52#ibcon#[27=USB\r\n] 2006.217.07:50:32.52#ibcon#*before write, iclass 21, count 0 2006.217.07:50:32.52#ibcon#enter sib2, iclass 21, count 0 2006.217.07:50:32.52#ibcon#flushed, iclass 21, count 0 2006.217.07:50:32.52#ibcon#about to write, iclass 21, count 0 2006.217.07:50:32.52#ibcon#wrote, iclass 21, count 0 2006.217.07:50:32.52#ibcon#about to read 3, iclass 21, count 0 2006.217.07:50:32.55#ibcon#read 3, iclass 21, count 0 2006.217.07:50:32.55#ibcon#about to read 4, iclass 21, count 0 2006.217.07:50:32.55#ibcon#read 4, iclass 21, count 0 2006.217.07:50:32.55#ibcon#about to read 5, iclass 21, count 0 2006.217.07:50:32.55#ibcon#read 5, iclass 21, count 0 2006.217.07:50:32.55#ibcon#about to read 6, iclass 21, count 0 2006.217.07:50:32.55#ibcon#read 6, iclass 21, count 0 2006.217.07:50:32.55#ibcon#end of sib2, iclass 21, count 0 2006.217.07:50:32.55#ibcon#*after write, iclass 21, count 0 2006.217.07:50:32.55#ibcon#*before return 0, iclass 21, count 0 2006.217.07:50:32.55#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.217.07:50:32.55#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.217.07:50:32.55#ibcon#about to clear, iclass 21 cls_cnt 0 2006.217.07:50:32.55#ibcon#cleared, iclass 21 cls_cnt 0 2006.217.07:50:32.55$vc4f8/vabw=wide 2006.217.07:50:32.55#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.217.07:50:32.55#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.217.07:50:32.55#ibcon#ireg 8 cls_cnt 0 2006.217.07:50:32.55#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.217.07:50:32.55#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.217.07:50:32.55#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.217.07:50:32.55#ibcon#enter wrdev, iclass 23, count 0 2006.217.07:50:32.55#ibcon#first serial, iclass 23, count 0 2006.217.07:50:32.55#ibcon#enter sib2, iclass 23, count 0 2006.217.07:50:32.55#ibcon#flushed, iclass 23, count 0 2006.217.07:50:32.55#ibcon#about to write, iclass 23, count 0 2006.217.07:50:32.55#ibcon#wrote, iclass 23, count 0 2006.217.07:50:32.55#ibcon#about to read 3, iclass 23, count 0 2006.217.07:50:32.57#ibcon#read 3, iclass 23, count 0 2006.217.07:50:32.57#ibcon#about to read 4, iclass 23, count 0 2006.217.07:50:32.57#ibcon#read 4, iclass 23, count 0 2006.217.07:50:32.57#ibcon#about to read 5, iclass 23, count 0 2006.217.07:50:32.57#ibcon#read 5, iclass 23, count 0 2006.217.07:50:32.57#ibcon#about to read 6, iclass 23, count 0 2006.217.07:50:32.57#ibcon#read 6, iclass 23, count 0 2006.217.07:50:32.57#ibcon#end of sib2, iclass 23, count 0 2006.217.07:50:32.57#ibcon#*mode == 0, iclass 23, count 0 2006.217.07:50:32.57#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.217.07:50:32.57#ibcon#[25=BW32\r\n] 2006.217.07:50:32.57#ibcon#*before write, iclass 23, count 0 2006.217.07:50:32.57#ibcon#enter sib2, iclass 23, count 0 2006.217.07:50:32.57#ibcon#flushed, iclass 23, count 0 2006.217.07:50:32.57#ibcon#about to write, iclass 23, count 0 2006.217.07:50:32.57#ibcon#wrote, iclass 23, count 0 2006.217.07:50:32.57#ibcon#about to read 3, iclass 23, count 0 2006.217.07:50:32.60#ibcon#read 3, iclass 23, count 0 2006.217.07:50:32.60#ibcon#about to read 4, iclass 23, count 0 2006.217.07:50:32.60#ibcon#read 4, iclass 23, count 0 2006.217.07:50:32.60#ibcon#about to read 5, iclass 23, count 0 2006.217.07:50:32.60#ibcon#read 5, iclass 23, count 0 2006.217.07:50:32.60#ibcon#about to read 6, iclass 23, count 0 2006.217.07:50:32.60#ibcon#read 6, iclass 23, count 0 2006.217.07:50:32.60#ibcon#end of sib2, iclass 23, count 0 2006.217.07:50:32.60#ibcon#*after write, iclass 23, count 0 2006.217.07:50:32.60#ibcon#*before return 0, iclass 23, count 0 2006.217.07:50:32.60#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.217.07:50:32.60#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.217.07:50:32.60#ibcon#about to clear, iclass 23 cls_cnt 0 2006.217.07:50:32.60#ibcon#cleared, iclass 23 cls_cnt 0 2006.217.07:50:32.60$vc4f8/vbbw=wide 2006.217.07:50:32.60#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.217.07:50:32.60#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.217.07:50:32.60#ibcon#ireg 8 cls_cnt 0 2006.217.07:50:32.60#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.217.07:50:32.67#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.217.07:50:32.67#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.217.07:50:32.67#ibcon#enter wrdev, iclass 25, count 0 2006.217.07:50:32.67#ibcon#first serial, iclass 25, count 0 2006.217.07:50:32.67#ibcon#enter sib2, iclass 25, count 0 2006.217.07:50:32.67#ibcon#flushed, iclass 25, count 0 2006.217.07:50:32.67#ibcon#about to write, iclass 25, count 0 2006.217.07:50:32.67#ibcon#wrote, iclass 25, count 0 2006.217.07:50:32.67#ibcon#about to read 3, iclass 25, count 0 2006.217.07:50:32.69#ibcon#read 3, iclass 25, count 0 2006.217.07:50:32.69#ibcon#about to read 4, iclass 25, count 0 2006.217.07:50:32.69#ibcon#read 4, iclass 25, count 0 2006.217.07:50:32.69#ibcon#about to read 5, iclass 25, count 0 2006.217.07:50:32.69#ibcon#read 5, iclass 25, count 0 2006.217.07:50:32.69#ibcon#about to read 6, iclass 25, count 0 2006.217.07:50:32.69#ibcon#read 6, iclass 25, count 0 2006.217.07:50:32.69#ibcon#end of sib2, iclass 25, count 0 2006.217.07:50:32.69#ibcon#*mode == 0, iclass 25, count 0 2006.217.07:50:32.69#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.217.07:50:32.69#ibcon#[27=BW32\r\n] 2006.217.07:50:32.69#ibcon#*before write, iclass 25, count 0 2006.217.07:50:32.69#ibcon#enter sib2, iclass 25, count 0 2006.217.07:50:32.69#ibcon#flushed, iclass 25, count 0 2006.217.07:50:32.69#ibcon#about to write, iclass 25, count 0 2006.217.07:50:32.69#ibcon#wrote, iclass 25, count 0 2006.217.07:50:32.69#ibcon#about to read 3, iclass 25, count 0 2006.217.07:50:32.72#ibcon#read 3, iclass 25, count 0 2006.217.07:50:32.72#ibcon#about to read 4, iclass 25, count 0 2006.217.07:50:32.72#ibcon#read 4, iclass 25, count 0 2006.217.07:50:32.72#ibcon#about to read 5, iclass 25, count 0 2006.217.07:50:32.72#ibcon#read 5, iclass 25, count 0 2006.217.07:50:32.72#ibcon#about to read 6, iclass 25, count 0 2006.217.07:50:32.72#ibcon#read 6, iclass 25, count 0 2006.217.07:50:32.72#ibcon#end of sib2, iclass 25, count 0 2006.217.07:50:32.72#ibcon#*after write, iclass 25, count 0 2006.217.07:50:32.72#ibcon#*before return 0, iclass 25, count 0 2006.217.07:50:32.72#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.217.07:50:32.72#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.217.07:50:32.72#ibcon#about to clear, iclass 25 cls_cnt 0 2006.217.07:50:32.72#ibcon#cleared, iclass 25 cls_cnt 0 2006.217.07:50:32.72$4f8m12a/ifd4f 2006.217.07:50:32.72$ifd4f/lo= 2006.217.07:50:32.72$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.217.07:50:32.72$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.217.07:50:32.72$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.217.07:50:32.72$ifd4f/patch= 2006.217.07:50:32.72$ifd4f/patch=lo1,a1,a2,a3,a4 2006.217.07:50:32.72$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.217.07:50:32.72$ifd4f/patch=lo3,a5,a6,a7,a8 2006.217.07:50:32.72$4f8m12a/"form=m,16.000,1:2 2006.217.07:50:32.72$4f8m12a/"tpicd 2006.217.07:50:32.72$4f8m12a/echo=off 2006.217.07:50:32.72$4f8m12a/xlog=off 2006.217.07:50:32.72:!2006.217.07:51:00 2006.217.07:50:39.13#trakl#Source acquired 2006.217.07:50:41.13#flagr#flagr/antenna,acquired 2006.217.07:51:00.00:preob 2006.217.07:51:00.14/onsource/TRACKING 2006.217.07:51:00.14:!2006.217.07:51:10 2006.217.07:51:10.00:data_valid=on 2006.217.07:51:10.00:midob 2006.217.07:51:11.14/onsource/TRACKING 2006.217.07:51:11.14/wx/31.22,1008.6,64 2006.217.07:51:11.34/cable/+6.3874E-03 2006.217.07:51:12.43/va/01,05,usb,yes,33,34 2006.217.07:51:12.43/va/02,04,usb,yes,30,32 2006.217.07:51:12.43/va/03,04,usb,yes,29,29 2006.217.07:51:12.43/va/04,04,usb,yes,32,34 2006.217.07:51:12.43/va/05,07,usb,yes,34,36 2006.217.07:51:12.43/va/06,06,usb,yes,33,33 2006.217.07:51:12.43/va/07,06,usb,yes,34,34 2006.217.07:51:12.43/va/08,07,usb,yes,32,32 2006.217.07:51:12.66/valo/01,532.99,yes,locked 2006.217.07:51:12.66/valo/02,572.99,yes,locked 2006.217.07:51:12.66/valo/03,672.99,yes,locked 2006.217.07:51:12.66/valo/04,832.99,yes,locked 2006.217.07:51:12.66/valo/05,652.99,yes,locked 2006.217.07:51:12.66/valo/06,772.99,yes,locked 2006.217.07:51:12.66/valo/07,832.99,yes,locked 2006.217.07:51:12.66/valo/08,852.99,yes,locked 2006.217.07:51:13.75/vb/01,04,usb,yes,31,29 2006.217.07:51:13.75/vb/02,04,usb,yes,33,34 2006.217.07:51:13.75/vb/03,04,usb,yes,29,33 2006.217.07:51:13.75/vb/04,04,usb,yes,30,30 2006.217.07:51:13.75/vb/05,04,usb,yes,28,32 2006.217.07:51:13.75/vb/06,04,usb,yes,29,32 2006.217.07:51:13.75/vb/07,04,usb,yes,32,31 2006.217.07:51:13.75/vb/08,04,usb,yes,29,32 2006.217.07:51:13.98/vblo/01,632.99,yes,locked 2006.217.07:51:13.98/vblo/02,640.99,yes,locked 2006.217.07:51:13.98/vblo/03,656.99,yes,locked 2006.217.07:51:13.98/vblo/04,712.99,yes,locked 2006.217.07:51:13.98/vblo/05,744.99,yes,locked 2006.217.07:51:13.98/vblo/06,752.99,yes,locked 2006.217.07:51:13.98/vblo/07,734.99,yes,locked 2006.217.07:51:13.98/vblo/08,744.99,yes,locked 2006.217.07:51:14.13/vabw/8 2006.217.07:51:14.28/vbbw/8 2006.217.07:51:14.37/xfe/off,on,15.0 2006.217.07:51:14.74/ifatt/23,28,28,28 2006.217.07:51:15.07/fmout-gps/S +4.16E-07 2006.217.07:51:15.15:!2006.217.07:52:10 2006.217.07:52:10.01:data_valid=off 2006.217.07:52:10.02:postob 2006.217.07:52:10.17/cable/+6.3860E-03 2006.217.07:52:10.18/wx/31.20,1008.5,64 2006.217.07:52:11.07/fmout-gps/S +4.20E-07 2006.217.07:52:11.08:scan_name=217-0753,k06217,60 2006.217.07:52:11.08:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.217.07:52:11.14#flagr#flagr/antenna,new-source 2006.217.07:52:12.14:checkk5 2006.217.07:52:12.52/chk_autoobs//k5ts1/ autoobs is running! 2006.217.07:52:12.91/chk_autoobs//k5ts2/ autoobs is running! 2006.217.07:52:13.28/chk_autoobs//k5ts3/ autoobs is running! 2006.217.07:52:13.66/chk_autoobs//k5ts4/ autoobs is running! 2006.217.07:52:14.03/chk_obsdata//k5ts1/T2170751??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:52:14.40/chk_obsdata//k5ts2/T2170751??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:52:14.76/chk_obsdata//k5ts3/T2170751??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:52:15.12/chk_obsdata//k5ts4/T2170751??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:52:15.81/k5log//k5ts1_log_newline 2006.217.07:52:16.50/k5log//k5ts2_log_newline 2006.217.07:52:17.20/k5log//k5ts3_log_newline 2006.217.07:52:17.91/k5log//k5ts4_log_newline 2006.217.07:52:17.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.217.07:52:17.93:4f8m12a=1 2006.217.07:52:17.93$4f8m12a/echo=on 2006.217.07:52:17.93$4f8m12a/pcalon 2006.217.07:52:17.93$pcalon/"no phase cal control is implemented here 2006.217.07:52:17.93$4f8m12a/"tpicd=stop 2006.217.07:52:17.93$4f8m12a/vc4f8 2006.217.07:52:17.93$vc4f8/valo=1,532.99 2006.217.07:52:17.93#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.217.07:52:17.93#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.217.07:52:17.93#ibcon#ireg 17 cls_cnt 0 2006.217.07:52:17.93#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.217.07:52:17.93#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.217.07:52:17.93#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.217.07:52:17.93#ibcon#enter wrdev, iclass 32, count 0 2006.217.07:52:17.93#ibcon#first serial, iclass 32, count 0 2006.217.07:52:17.94#ibcon#enter sib2, iclass 32, count 0 2006.217.07:52:17.94#ibcon#flushed, iclass 32, count 0 2006.217.07:52:17.94#ibcon#about to write, iclass 32, count 0 2006.217.07:52:17.94#ibcon#wrote, iclass 32, count 0 2006.217.07:52:17.94#ibcon#about to read 3, iclass 32, count 0 2006.217.07:52:17.98#ibcon#read 3, iclass 32, count 0 2006.217.07:52:17.98#ibcon#about to read 4, iclass 32, count 0 2006.217.07:52:17.98#ibcon#read 4, iclass 32, count 0 2006.217.07:52:17.98#ibcon#about to read 5, iclass 32, count 0 2006.217.07:52:17.98#ibcon#read 5, iclass 32, count 0 2006.217.07:52:17.98#ibcon#about to read 6, iclass 32, count 0 2006.217.07:52:17.98#ibcon#read 6, iclass 32, count 0 2006.217.07:52:17.98#ibcon#end of sib2, iclass 32, count 0 2006.217.07:52:17.98#ibcon#*mode == 0, iclass 32, count 0 2006.217.07:52:17.98#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.217.07:52:17.98#ibcon#[26=FRQ=01,532.99\r\n] 2006.217.07:52:17.98#ibcon#*before write, iclass 32, count 0 2006.217.07:52:17.98#ibcon#enter sib2, iclass 32, count 0 2006.217.07:52:17.98#ibcon#flushed, iclass 32, count 0 2006.217.07:52:17.98#ibcon#about to write, iclass 32, count 0 2006.217.07:52:17.98#ibcon#wrote, iclass 32, count 0 2006.217.07:52:17.98#ibcon#about to read 3, iclass 32, count 0 2006.217.07:52:18.02#ibcon#read 3, iclass 32, count 0 2006.217.07:52:18.02#ibcon#about to read 4, iclass 32, count 0 2006.217.07:52:18.02#ibcon#read 4, iclass 32, count 0 2006.217.07:52:18.02#ibcon#about to read 5, iclass 32, count 0 2006.217.07:52:18.02#ibcon#read 5, iclass 32, count 0 2006.217.07:52:18.02#ibcon#about to read 6, iclass 32, count 0 2006.217.07:52:18.02#ibcon#read 6, iclass 32, count 0 2006.217.07:52:18.02#ibcon#end of sib2, iclass 32, count 0 2006.217.07:52:18.02#ibcon#*after write, iclass 32, count 0 2006.217.07:52:18.02#ibcon#*before return 0, iclass 32, count 0 2006.217.07:52:18.02#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.217.07:52:18.02#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.217.07:52:18.02#ibcon#about to clear, iclass 32 cls_cnt 0 2006.217.07:52:18.02#ibcon#cleared, iclass 32 cls_cnt 0 2006.217.07:52:18.02$vc4f8/va=1,5 2006.217.07:52:18.02#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.217.07:52:18.02#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.217.07:52:18.02#ibcon#ireg 11 cls_cnt 2 2006.217.07:52:18.02#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.217.07:52:18.02#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.217.07:52:18.02#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.217.07:52:18.02#ibcon#enter wrdev, iclass 34, count 2 2006.217.07:52:18.02#ibcon#first serial, iclass 34, count 2 2006.217.07:52:18.02#ibcon#enter sib2, iclass 34, count 2 2006.217.07:52:18.02#ibcon#flushed, iclass 34, count 2 2006.217.07:52:18.02#ibcon#about to write, iclass 34, count 2 2006.217.07:52:18.02#ibcon#wrote, iclass 34, count 2 2006.217.07:52:18.02#ibcon#about to read 3, iclass 34, count 2 2006.217.07:52:18.04#ibcon#read 3, iclass 34, count 2 2006.217.07:52:18.04#ibcon#about to read 4, iclass 34, count 2 2006.217.07:52:18.04#ibcon#read 4, iclass 34, count 2 2006.217.07:52:18.04#ibcon#about to read 5, iclass 34, count 2 2006.217.07:52:18.04#ibcon#read 5, iclass 34, count 2 2006.217.07:52:18.04#ibcon#about to read 6, iclass 34, count 2 2006.217.07:52:18.04#ibcon#read 6, iclass 34, count 2 2006.217.07:52:18.04#ibcon#end of sib2, iclass 34, count 2 2006.217.07:52:18.04#ibcon#*mode == 0, iclass 34, count 2 2006.217.07:52:18.04#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.217.07:52:18.04#ibcon#[25=AT01-05\r\n] 2006.217.07:52:18.04#ibcon#*before write, iclass 34, count 2 2006.217.07:52:18.04#ibcon#enter sib2, iclass 34, count 2 2006.217.07:52:18.04#ibcon#flushed, iclass 34, count 2 2006.217.07:52:18.04#ibcon#about to write, iclass 34, count 2 2006.217.07:52:18.04#ibcon#wrote, iclass 34, count 2 2006.217.07:52:18.04#ibcon#about to read 3, iclass 34, count 2 2006.217.07:52:18.07#ibcon#read 3, iclass 34, count 2 2006.217.07:52:18.07#ibcon#about to read 4, iclass 34, count 2 2006.217.07:52:18.07#ibcon#read 4, iclass 34, count 2 2006.217.07:52:18.07#ibcon#about to read 5, iclass 34, count 2 2006.217.07:52:18.07#ibcon#read 5, iclass 34, count 2 2006.217.07:52:18.07#ibcon#about to read 6, iclass 34, count 2 2006.217.07:52:18.07#ibcon#read 6, iclass 34, count 2 2006.217.07:52:18.07#ibcon#end of sib2, iclass 34, count 2 2006.217.07:52:18.07#ibcon#*after write, iclass 34, count 2 2006.217.07:52:18.07#ibcon#*before return 0, iclass 34, count 2 2006.217.07:52:18.07#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.217.07:52:18.07#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.217.07:52:18.07#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.217.07:52:18.07#ibcon#ireg 7 cls_cnt 0 2006.217.07:52:18.07#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.217.07:52:18.19#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.217.07:52:18.19#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.217.07:52:18.19#ibcon#enter wrdev, iclass 34, count 0 2006.217.07:52:18.19#ibcon#first serial, iclass 34, count 0 2006.217.07:52:18.19#ibcon#enter sib2, iclass 34, count 0 2006.217.07:52:18.19#ibcon#flushed, iclass 34, count 0 2006.217.07:52:18.19#ibcon#about to write, iclass 34, count 0 2006.217.07:52:18.19#ibcon#wrote, iclass 34, count 0 2006.217.07:52:18.19#ibcon#about to read 3, iclass 34, count 0 2006.217.07:52:18.21#ibcon#read 3, iclass 34, count 0 2006.217.07:52:18.21#ibcon#about to read 4, iclass 34, count 0 2006.217.07:52:18.21#ibcon#read 4, iclass 34, count 0 2006.217.07:52:18.21#ibcon#about to read 5, iclass 34, count 0 2006.217.07:52:18.21#ibcon#read 5, iclass 34, count 0 2006.217.07:52:18.21#ibcon#about to read 6, iclass 34, count 0 2006.217.07:52:18.21#ibcon#read 6, iclass 34, count 0 2006.217.07:52:18.21#ibcon#end of sib2, iclass 34, count 0 2006.217.07:52:18.21#ibcon#*mode == 0, iclass 34, count 0 2006.217.07:52:18.21#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.217.07:52:18.21#ibcon#[25=USB\r\n] 2006.217.07:52:18.21#ibcon#*before write, iclass 34, count 0 2006.217.07:52:18.21#ibcon#enter sib2, iclass 34, count 0 2006.217.07:52:18.21#ibcon#flushed, iclass 34, count 0 2006.217.07:52:18.21#ibcon#about to write, iclass 34, count 0 2006.217.07:52:18.21#ibcon#wrote, iclass 34, count 0 2006.217.07:52:18.21#ibcon#about to read 3, iclass 34, count 0 2006.217.07:52:18.24#ibcon#read 3, iclass 34, count 0 2006.217.07:52:18.24#ibcon#about to read 4, iclass 34, count 0 2006.217.07:52:18.24#ibcon#read 4, iclass 34, count 0 2006.217.07:52:18.24#ibcon#about to read 5, iclass 34, count 0 2006.217.07:52:18.24#ibcon#read 5, iclass 34, count 0 2006.217.07:52:18.24#ibcon#about to read 6, iclass 34, count 0 2006.217.07:52:18.24#ibcon#read 6, iclass 34, count 0 2006.217.07:52:18.24#ibcon#end of sib2, iclass 34, count 0 2006.217.07:52:18.24#ibcon#*after write, iclass 34, count 0 2006.217.07:52:18.24#ibcon#*before return 0, iclass 34, count 0 2006.217.07:52:18.24#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.217.07:52:18.24#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.217.07:52:18.24#ibcon#about to clear, iclass 34 cls_cnt 0 2006.217.07:52:18.24#ibcon#cleared, iclass 34 cls_cnt 0 2006.217.07:52:18.24$vc4f8/valo=2,572.99 2006.217.07:52:18.24#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.217.07:52:18.24#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.217.07:52:18.24#ibcon#ireg 17 cls_cnt 0 2006.217.07:52:18.24#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.217.07:52:18.24#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.217.07:52:18.24#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.217.07:52:18.24#ibcon#enter wrdev, iclass 36, count 0 2006.217.07:52:18.24#ibcon#first serial, iclass 36, count 0 2006.217.07:52:18.24#ibcon#enter sib2, iclass 36, count 0 2006.217.07:52:18.24#ibcon#flushed, iclass 36, count 0 2006.217.07:52:18.24#ibcon#about to write, iclass 36, count 0 2006.217.07:52:18.24#ibcon#wrote, iclass 36, count 0 2006.217.07:52:18.24#ibcon#about to read 3, iclass 36, count 0 2006.217.07:52:18.26#ibcon#read 3, iclass 36, count 0 2006.217.07:52:18.26#ibcon#about to read 4, iclass 36, count 0 2006.217.07:52:18.26#ibcon#read 4, iclass 36, count 0 2006.217.07:52:18.26#ibcon#about to read 5, iclass 36, count 0 2006.217.07:52:18.26#ibcon#read 5, iclass 36, count 0 2006.217.07:52:18.26#ibcon#about to read 6, iclass 36, count 0 2006.217.07:52:18.26#ibcon#read 6, iclass 36, count 0 2006.217.07:52:18.26#ibcon#end of sib2, iclass 36, count 0 2006.217.07:52:18.26#ibcon#*mode == 0, iclass 36, count 0 2006.217.07:52:18.26#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.217.07:52:18.26#ibcon#[26=FRQ=02,572.99\r\n] 2006.217.07:52:18.26#ibcon#*before write, iclass 36, count 0 2006.217.07:52:18.26#ibcon#enter sib2, iclass 36, count 0 2006.217.07:52:18.26#ibcon#flushed, iclass 36, count 0 2006.217.07:52:18.26#ibcon#about to write, iclass 36, count 0 2006.217.07:52:18.26#ibcon#wrote, iclass 36, count 0 2006.217.07:52:18.26#ibcon#about to read 3, iclass 36, count 0 2006.217.07:52:18.30#ibcon#read 3, iclass 36, count 0 2006.217.07:52:18.30#ibcon#about to read 4, iclass 36, count 0 2006.217.07:52:18.30#ibcon#read 4, iclass 36, count 0 2006.217.07:52:18.30#ibcon#about to read 5, iclass 36, count 0 2006.217.07:52:18.30#ibcon#read 5, iclass 36, count 0 2006.217.07:52:18.30#ibcon#about to read 6, iclass 36, count 0 2006.217.07:52:18.30#ibcon#read 6, iclass 36, count 0 2006.217.07:52:18.30#ibcon#end of sib2, iclass 36, count 0 2006.217.07:52:18.30#ibcon#*after write, iclass 36, count 0 2006.217.07:52:18.30#ibcon#*before return 0, iclass 36, count 0 2006.217.07:52:18.30#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.217.07:52:18.30#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.217.07:52:18.30#ibcon#about to clear, iclass 36 cls_cnt 0 2006.217.07:52:18.30#ibcon#cleared, iclass 36 cls_cnt 0 2006.217.07:52:18.30$vc4f8/va=2,4 2006.217.07:52:18.30#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.217.07:52:18.30#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.217.07:52:18.30#ibcon#ireg 11 cls_cnt 2 2006.217.07:52:18.30#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.217.07:52:18.36#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.217.07:52:18.36#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.217.07:52:18.36#ibcon#enter wrdev, iclass 38, count 2 2006.217.07:52:18.36#ibcon#first serial, iclass 38, count 2 2006.217.07:52:18.36#ibcon#enter sib2, iclass 38, count 2 2006.217.07:52:18.36#ibcon#flushed, iclass 38, count 2 2006.217.07:52:18.36#ibcon#about to write, iclass 38, count 2 2006.217.07:52:18.36#ibcon#wrote, iclass 38, count 2 2006.217.07:52:18.36#ibcon#about to read 3, iclass 38, count 2 2006.217.07:52:18.38#ibcon#read 3, iclass 38, count 2 2006.217.07:52:18.38#ibcon#about to read 4, iclass 38, count 2 2006.217.07:52:18.38#ibcon#read 4, iclass 38, count 2 2006.217.07:52:18.38#ibcon#about to read 5, iclass 38, count 2 2006.217.07:52:18.38#ibcon#read 5, iclass 38, count 2 2006.217.07:52:18.38#ibcon#about to read 6, iclass 38, count 2 2006.217.07:52:18.38#ibcon#read 6, iclass 38, count 2 2006.217.07:52:18.38#ibcon#end of sib2, iclass 38, count 2 2006.217.07:52:18.38#ibcon#*mode == 0, iclass 38, count 2 2006.217.07:52:18.38#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.217.07:52:18.38#ibcon#[25=AT02-04\r\n] 2006.217.07:52:18.38#ibcon#*before write, iclass 38, count 2 2006.217.07:52:18.38#ibcon#enter sib2, iclass 38, count 2 2006.217.07:52:18.38#ibcon#flushed, iclass 38, count 2 2006.217.07:52:18.38#ibcon#about to write, iclass 38, count 2 2006.217.07:52:18.38#ibcon#wrote, iclass 38, count 2 2006.217.07:52:18.38#ibcon#about to read 3, iclass 38, count 2 2006.217.07:52:18.41#ibcon#read 3, iclass 38, count 2 2006.217.07:52:18.41#ibcon#about to read 4, iclass 38, count 2 2006.217.07:52:18.41#ibcon#read 4, iclass 38, count 2 2006.217.07:52:18.41#ibcon#about to read 5, iclass 38, count 2 2006.217.07:52:18.41#ibcon#read 5, iclass 38, count 2 2006.217.07:52:18.41#ibcon#about to read 6, iclass 38, count 2 2006.217.07:52:18.41#ibcon#read 6, iclass 38, count 2 2006.217.07:52:18.41#ibcon#end of sib2, iclass 38, count 2 2006.217.07:52:18.41#ibcon#*after write, iclass 38, count 2 2006.217.07:52:18.41#ibcon#*before return 0, iclass 38, count 2 2006.217.07:52:18.41#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.217.07:52:18.41#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.217.07:52:18.41#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.217.07:52:18.41#ibcon#ireg 7 cls_cnt 0 2006.217.07:52:18.41#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.217.07:52:18.53#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.217.07:52:18.53#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.217.07:52:18.53#ibcon#enter wrdev, iclass 38, count 0 2006.217.07:52:18.53#ibcon#first serial, iclass 38, count 0 2006.217.07:52:18.53#ibcon#enter sib2, iclass 38, count 0 2006.217.07:52:18.53#ibcon#flushed, iclass 38, count 0 2006.217.07:52:18.53#ibcon#about to write, iclass 38, count 0 2006.217.07:52:18.53#ibcon#wrote, iclass 38, count 0 2006.217.07:52:18.53#ibcon#about to read 3, iclass 38, count 0 2006.217.07:52:18.55#ibcon#read 3, iclass 38, count 0 2006.217.07:52:18.55#ibcon#about to read 4, iclass 38, count 0 2006.217.07:52:18.55#ibcon#read 4, iclass 38, count 0 2006.217.07:52:18.55#ibcon#about to read 5, iclass 38, count 0 2006.217.07:52:18.55#ibcon#read 5, iclass 38, count 0 2006.217.07:52:18.55#ibcon#about to read 6, iclass 38, count 0 2006.217.07:52:18.55#ibcon#read 6, iclass 38, count 0 2006.217.07:52:18.55#ibcon#end of sib2, iclass 38, count 0 2006.217.07:52:18.55#ibcon#*mode == 0, iclass 38, count 0 2006.217.07:52:18.55#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.217.07:52:18.55#ibcon#[25=USB\r\n] 2006.217.07:52:18.55#ibcon#*before write, iclass 38, count 0 2006.217.07:52:18.55#ibcon#enter sib2, iclass 38, count 0 2006.217.07:52:18.55#ibcon#flushed, iclass 38, count 0 2006.217.07:52:18.55#ibcon#about to write, iclass 38, count 0 2006.217.07:52:18.55#ibcon#wrote, iclass 38, count 0 2006.217.07:52:18.55#ibcon#about to read 3, iclass 38, count 0 2006.217.07:52:18.58#ibcon#read 3, iclass 38, count 0 2006.217.07:52:18.58#ibcon#about to read 4, iclass 38, count 0 2006.217.07:52:18.58#ibcon#read 4, iclass 38, count 0 2006.217.07:52:18.58#ibcon#about to read 5, iclass 38, count 0 2006.217.07:52:18.58#ibcon#read 5, iclass 38, count 0 2006.217.07:52:18.58#ibcon#about to read 6, iclass 38, count 0 2006.217.07:52:18.58#ibcon#read 6, iclass 38, count 0 2006.217.07:52:18.58#ibcon#end of sib2, iclass 38, count 0 2006.217.07:52:18.58#ibcon#*after write, iclass 38, count 0 2006.217.07:52:18.58#ibcon#*before return 0, iclass 38, count 0 2006.217.07:52:18.58#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.217.07:52:18.58#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.217.07:52:18.58#ibcon#about to clear, iclass 38 cls_cnt 0 2006.217.07:52:18.58#ibcon#cleared, iclass 38 cls_cnt 0 2006.217.07:52:18.58$vc4f8/valo=3,672.99 2006.217.07:52:18.58#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.217.07:52:18.58#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.217.07:52:18.58#ibcon#ireg 17 cls_cnt 0 2006.217.07:52:18.58#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.217.07:52:18.58#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.217.07:52:18.58#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.217.07:52:18.58#ibcon#enter wrdev, iclass 40, count 0 2006.217.07:52:18.58#ibcon#first serial, iclass 40, count 0 2006.217.07:52:18.58#ibcon#enter sib2, iclass 40, count 0 2006.217.07:52:18.58#ibcon#flushed, iclass 40, count 0 2006.217.07:52:18.58#ibcon#about to write, iclass 40, count 0 2006.217.07:52:18.58#ibcon#wrote, iclass 40, count 0 2006.217.07:52:18.58#ibcon#about to read 3, iclass 40, count 0 2006.217.07:52:18.60#ibcon#read 3, iclass 40, count 0 2006.217.07:52:18.60#ibcon#about to read 4, iclass 40, count 0 2006.217.07:52:18.60#ibcon#read 4, iclass 40, count 0 2006.217.07:52:18.60#ibcon#about to read 5, iclass 40, count 0 2006.217.07:52:18.60#ibcon#read 5, iclass 40, count 0 2006.217.07:52:18.60#ibcon#about to read 6, iclass 40, count 0 2006.217.07:52:18.60#ibcon#read 6, iclass 40, count 0 2006.217.07:52:18.60#ibcon#end of sib2, iclass 40, count 0 2006.217.07:52:18.60#ibcon#*mode == 0, iclass 40, count 0 2006.217.07:52:18.60#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.217.07:52:18.60#ibcon#[26=FRQ=03,672.99\r\n] 2006.217.07:52:18.60#ibcon#*before write, iclass 40, count 0 2006.217.07:52:18.60#ibcon#enter sib2, iclass 40, count 0 2006.217.07:52:18.60#ibcon#flushed, iclass 40, count 0 2006.217.07:52:18.60#ibcon#about to write, iclass 40, count 0 2006.217.07:52:18.60#ibcon#wrote, iclass 40, count 0 2006.217.07:52:18.60#ibcon#about to read 3, iclass 40, count 0 2006.217.07:52:18.64#ibcon#read 3, iclass 40, count 0 2006.217.07:52:18.64#ibcon#about to read 4, iclass 40, count 0 2006.217.07:52:18.64#ibcon#read 4, iclass 40, count 0 2006.217.07:52:18.64#ibcon#about to read 5, iclass 40, count 0 2006.217.07:52:18.64#ibcon#read 5, iclass 40, count 0 2006.217.07:52:18.64#ibcon#about to read 6, iclass 40, count 0 2006.217.07:52:18.64#ibcon#read 6, iclass 40, count 0 2006.217.07:52:18.64#ibcon#end of sib2, iclass 40, count 0 2006.217.07:52:18.64#ibcon#*after write, iclass 40, count 0 2006.217.07:52:18.64#ibcon#*before return 0, iclass 40, count 0 2006.217.07:52:18.64#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.217.07:52:18.64#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.217.07:52:18.64#ibcon#about to clear, iclass 40 cls_cnt 0 2006.217.07:52:18.64#ibcon#cleared, iclass 40 cls_cnt 0 2006.217.07:52:18.64$vc4f8/va=3,4 2006.217.07:52:18.64#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.217.07:52:18.64#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.217.07:52:18.64#ibcon#ireg 11 cls_cnt 2 2006.217.07:52:18.64#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.217.07:52:18.70#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.217.07:52:18.70#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.217.07:52:18.70#ibcon#enter wrdev, iclass 4, count 2 2006.217.07:52:18.70#ibcon#first serial, iclass 4, count 2 2006.217.07:52:18.70#ibcon#enter sib2, iclass 4, count 2 2006.217.07:52:18.70#ibcon#flushed, iclass 4, count 2 2006.217.07:52:18.70#ibcon#about to write, iclass 4, count 2 2006.217.07:52:18.70#ibcon#wrote, iclass 4, count 2 2006.217.07:52:18.70#ibcon#about to read 3, iclass 4, count 2 2006.217.07:52:18.73#ibcon#read 3, iclass 4, count 2 2006.217.07:52:18.73#ibcon#about to read 4, iclass 4, count 2 2006.217.07:52:18.73#ibcon#read 4, iclass 4, count 2 2006.217.07:52:18.73#ibcon#about to read 5, iclass 4, count 2 2006.217.07:52:18.73#ibcon#read 5, iclass 4, count 2 2006.217.07:52:18.73#ibcon#about to read 6, iclass 4, count 2 2006.217.07:52:18.73#ibcon#read 6, iclass 4, count 2 2006.217.07:52:18.73#ibcon#end of sib2, iclass 4, count 2 2006.217.07:52:18.73#ibcon#*mode == 0, iclass 4, count 2 2006.217.07:52:18.73#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.217.07:52:18.73#ibcon#[25=AT03-04\r\n] 2006.217.07:52:18.73#ibcon#*before write, iclass 4, count 2 2006.217.07:52:18.73#ibcon#enter sib2, iclass 4, count 2 2006.217.07:52:18.73#ibcon#flushed, iclass 4, count 2 2006.217.07:52:18.73#ibcon#about to write, iclass 4, count 2 2006.217.07:52:18.73#ibcon#wrote, iclass 4, count 2 2006.217.07:52:18.73#ibcon#about to read 3, iclass 4, count 2 2006.217.07:52:18.76#ibcon#read 3, iclass 4, count 2 2006.217.07:52:18.76#ibcon#about to read 4, iclass 4, count 2 2006.217.07:52:18.76#ibcon#read 4, iclass 4, count 2 2006.217.07:52:18.76#ibcon#about to read 5, iclass 4, count 2 2006.217.07:52:18.76#ibcon#read 5, iclass 4, count 2 2006.217.07:52:18.76#ibcon#about to read 6, iclass 4, count 2 2006.217.07:52:18.76#ibcon#read 6, iclass 4, count 2 2006.217.07:52:18.76#ibcon#end of sib2, iclass 4, count 2 2006.217.07:52:18.76#ibcon#*after write, iclass 4, count 2 2006.217.07:52:18.76#ibcon#*before return 0, iclass 4, count 2 2006.217.07:52:18.76#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.217.07:52:18.76#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.217.07:52:18.76#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.217.07:52:18.76#ibcon#ireg 7 cls_cnt 0 2006.217.07:52:18.76#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.217.07:52:18.88#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.217.07:52:18.88#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.217.07:52:18.88#ibcon#enter wrdev, iclass 4, count 0 2006.217.07:52:18.88#ibcon#first serial, iclass 4, count 0 2006.217.07:52:18.88#ibcon#enter sib2, iclass 4, count 0 2006.217.07:52:18.88#ibcon#flushed, iclass 4, count 0 2006.217.07:52:18.88#ibcon#about to write, iclass 4, count 0 2006.217.07:52:18.88#ibcon#wrote, iclass 4, count 0 2006.217.07:52:18.88#ibcon#about to read 3, iclass 4, count 0 2006.217.07:52:18.90#ibcon#read 3, iclass 4, count 0 2006.217.07:52:18.90#ibcon#about to read 4, iclass 4, count 0 2006.217.07:52:18.90#ibcon#read 4, iclass 4, count 0 2006.217.07:52:18.90#ibcon#about to read 5, iclass 4, count 0 2006.217.07:52:18.90#ibcon#read 5, iclass 4, count 0 2006.217.07:52:18.90#ibcon#about to read 6, iclass 4, count 0 2006.217.07:52:18.90#ibcon#read 6, iclass 4, count 0 2006.217.07:52:18.90#ibcon#end of sib2, iclass 4, count 0 2006.217.07:52:18.90#ibcon#*mode == 0, iclass 4, count 0 2006.217.07:52:18.90#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.217.07:52:18.90#ibcon#[25=USB\r\n] 2006.217.07:52:18.90#ibcon#*before write, iclass 4, count 0 2006.217.07:52:18.90#ibcon#enter sib2, iclass 4, count 0 2006.217.07:52:18.90#ibcon#flushed, iclass 4, count 0 2006.217.07:52:18.90#ibcon#about to write, iclass 4, count 0 2006.217.07:52:18.90#ibcon#wrote, iclass 4, count 0 2006.217.07:52:18.90#ibcon#about to read 3, iclass 4, count 0 2006.217.07:52:18.93#ibcon#read 3, iclass 4, count 0 2006.217.07:52:18.93#ibcon#about to read 4, iclass 4, count 0 2006.217.07:52:18.93#ibcon#read 4, iclass 4, count 0 2006.217.07:52:18.93#ibcon#about to read 5, iclass 4, count 0 2006.217.07:52:18.93#ibcon#read 5, iclass 4, count 0 2006.217.07:52:18.93#ibcon#about to read 6, iclass 4, count 0 2006.217.07:52:18.93#ibcon#read 6, iclass 4, count 0 2006.217.07:52:18.93#ibcon#end of sib2, iclass 4, count 0 2006.217.07:52:18.93#ibcon#*after write, iclass 4, count 0 2006.217.07:52:18.93#ibcon#*before return 0, iclass 4, count 0 2006.217.07:52:18.93#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.217.07:52:18.93#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.217.07:52:18.93#ibcon#about to clear, iclass 4 cls_cnt 0 2006.217.07:52:18.93#ibcon#cleared, iclass 4 cls_cnt 0 2006.217.07:52:18.93$vc4f8/valo=4,832.99 2006.217.07:52:18.93#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.217.07:52:18.93#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.217.07:52:18.93#ibcon#ireg 17 cls_cnt 0 2006.217.07:52:18.93#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.217.07:52:18.93#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.217.07:52:18.93#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.217.07:52:18.93#ibcon#enter wrdev, iclass 6, count 0 2006.217.07:52:18.93#ibcon#first serial, iclass 6, count 0 2006.217.07:52:18.93#ibcon#enter sib2, iclass 6, count 0 2006.217.07:52:18.93#ibcon#flushed, iclass 6, count 0 2006.217.07:52:18.93#ibcon#about to write, iclass 6, count 0 2006.217.07:52:18.93#ibcon#wrote, iclass 6, count 0 2006.217.07:52:18.93#ibcon#about to read 3, iclass 6, count 0 2006.217.07:52:18.95#ibcon#read 3, iclass 6, count 0 2006.217.07:52:18.95#ibcon#about to read 4, iclass 6, count 0 2006.217.07:52:18.95#ibcon#read 4, iclass 6, count 0 2006.217.07:52:18.95#ibcon#about to read 5, iclass 6, count 0 2006.217.07:52:18.95#ibcon#read 5, iclass 6, count 0 2006.217.07:52:18.95#ibcon#about to read 6, iclass 6, count 0 2006.217.07:52:18.95#ibcon#read 6, iclass 6, count 0 2006.217.07:52:18.95#ibcon#end of sib2, iclass 6, count 0 2006.217.07:52:18.95#ibcon#*mode == 0, iclass 6, count 0 2006.217.07:52:18.95#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.217.07:52:18.95#ibcon#[26=FRQ=04,832.99\r\n] 2006.217.07:52:18.95#ibcon#*before write, iclass 6, count 0 2006.217.07:52:18.95#ibcon#enter sib2, iclass 6, count 0 2006.217.07:52:18.95#ibcon#flushed, iclass 6, count 0 2006.217.07:52:18.95#ibcon#about to write, iclass 6, count 0 2006.217.07:52:18.95#ibcon#wrote, iclass 6, count 0 2006.217.07:52:18.95#ibcon#about to read 3, iclass 6, count 0 2006.217.07:52:18.99#ibcon#read 3, iclass 6, count 0 2006.217.07:52:18.99#ibcon#about to read 4, iclass 6, count 0 2006.217.07:52:18.99#ibcon#read 4, iclass 6, count 0 2006.217.07:52:18.99#ibcon#about to read 5, iclass 6, count 0 2006.217.07:52:18.99#ibcon#read 5, iclass 6, count 0 2006.217.07:52:18.99#ibcon#about to read 6, iclass 6, count 0 2006.217.07:52:18.99#ibcon#read 6, iclass 6, count 0 2006.217.07:52:18.99#ibcon#end of sib2, iclass 6, count 0 2006.217.07:52:18.99#ibcon#*after write, iclass 6, count 0 2006.217.07:52:18.99#ibcon#*before return 0, iclass 6, count 0 2006.217.07:52:18.99#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.217.07:52:18.99#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.217.07:52:18.99#ibcon#about to clear, iclass 6 cls_cnt 0 2006.217.07:52:18.99#ibcon#cleared, iclass 6 cls_cnt 0 2006.217.07:52:18.99$vc4f8/va=4,4 2006.217.07:52:18.99#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.217.07:52:18.99#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.217.07:52:18.99#ibcon#ireg 11 cls_cnt 2 2006.217.07:52:18.99#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.217.07:52:19.05#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.217.07:52:19.05#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.217.07:52:19.05#ibcon#enter wrdev, iclass 10, count 2 2006.217.07:52:19.05#ibcon#first serial, iclass 10, count 2 2006.217.07:52:19.05#ibcon#enter sib2, iclass 10, count 2 2006.217.07:52:19.05#ibcon#flushed, iclass 10, count 2 2006.217.07:52:19.05#ibcon#about to write, iclass 10, count 2 2006.217.07:52:19.05#ibcon#wrote, iclass 10, count 2 2006.217.07:52:19.05#ibcon#about to read 3, iclass 10, count 2 2006.217.07:52:19.07#ibcon#read 3, iclass 10, count 2 2006.217.07:52:19.07#ibcon#about to read 4, iclass 10, count 2 2006.217.07:52:19.07#ibcon#read 4, iclass 10, count 2 2006.217.07:52:19.07#ibcon#about to read 5, iclass 10, count 2 2006.217.07:52:19.07#ibcon#read 5, iclass 10, count 2 2006.217.07:52:19.07#ibcon#about to read 6, iclass 10, count 2 2006.217.07:52:19.07#ibcon#read 6, iclass 10, count 2 2006.217.07:52:19.07#ibcon#end of sib2, iclass 10, count 2 2006.217.07:52:19.07#ibcon#*mode == 0, iclass 10, count 2 2006.217.07:52:19.07#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.217.07:52:19.07#ibcon#[25=AT04-04\r\n] 2006.217.07:52:19.07#ibcon#*before write, iclass 10, count 2 2006.217.07:52:19.07#ibcon#enter sib2, iclass 10, count 2 2006.217.07:52:19.07#ibcon#flushed, iclass 10, count 2 2006.217.07:52:19.07#ibcon#about to write, iclass 10, count 2 2006.217.07:52:19.07#ibcon#wrote, iclass 10, count 2 2006.217.07:52:19.07#ibcon#about to read 3, iclass 10, count 2 2006.217.07:52:19.10#ibcon#read 3, iclass 10, count 2 2006.217.07:52:19.10#ibcon#about to read 4, iclass 10, count 2 2006.217.07:52:19.10#ibcon#read 4, iclass 10, count 2 2006.217.07:52:19.10#ibcon#about to read 5, iclass 10, count 2 2006.217.07:52:19.10#ibcon#read 5, iclass 10, count 2 2006.217.07:52:19.10#ibcon#about to read 6, iclass 10, count 2 2006.217.07:52:19.10#ibcon#read 6, iclass 10, count 2 2006.217.07:52:19.10#ibcon#end of sib2, iclass 10, count 2 2006.217.07:52:19.10#ibcon#*after write, iclass 10, count 2 2006.217.07:52:19.10#ibcon#*before return 0, iclass 10, count 2 2006.217.07:52:19.10#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.217.07:52:19.10#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.217.07:52:19.10#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.217.07:52:19.10#ibcon#ireg 7 cls_cnt 0 2006.217.07:52:19.10#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.217.07:52:19.22#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.217.07:52:19.22#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.217.07:52:19.22#ibcon#enter wrdev, iclass 10, count 0 2006.217.07:52:19.22#ibcon#first serial, iclass 10, count 0 2006.217.07:52:19.22#ibcon#enter sib2, iclass 10, count 0 2006.217.07:52:19.22#ibcon#flushed, iclass 10, count 0 2006.217.07:52:19.22#ibcon#about to write, iclass 10, count 0 2006.217.07:52:19.22#ibcon#wrote, iclass 10, count 0 2006.217.07:52:19.22#ibcon#about to read 3, iclass 10, count 0 2006.217.07:52:19.24#ibcon#read 3, iclass 10, count 0 2006.217.07:52:19.24#ibcon#about to read 4, iclass 10, count 0 2006.217.07:52:19.24#ibcon#read 4, iclass 10, count 0 2006.217.07:52:19.24#ibcon#about to read 5, iclass 10, count 0 2006.217.07:52:19.24#ibcon#read 5, iclass 10, count 0 2006.217.07:52:19.24#ibcon#about to read 6, iclass 10, count 0 2006.217.07:52:19.24#ibcon#read 6, iclass 10, count 0 2006.217.07:52:19.24#ibcon#end of sib2, iclass 10, count 0 2006.217.07:52:19.24#ibcon#*mode == 0, iclass 10, count 0 2006.217.07:52:19.24#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.217.07:52:19.24#ibcon#[25=USB\r\n] 2006.217.07:52:19.24#ibcon#*before write, iclass 10, count 0 2006.217.07:52:19.24#ibcon#enter sib2, iclass 10, count 0 2006.217.07:52:19.24#ibcon#flushed, iclass 10, count 0 2006.217.07:52:19.24#ibcon#about to write, iclass 10, count 0 2006.217.07:52:19.24#ibcon#wrote, iclass 10, count 0 2006.217.07:52:19.24#ibcon#about to read 3, iclass 10, count 0 2006.217.07:52:19.27#ibcon#read 3, iclass 10, count 0 2006.217.07:52:19.27#ibcon#about to read 4, iclass 10, count 0 2006.217.07:52:19.27#ibcon#read 4, iclass 10, count 0 2006.217.07:52:19.27#ibcon#about to read 5, iclass 10, count 0 2006.217.07:52:19.27#ibcon#read 5, iclass 10, count 0 2006.217.07:52:19.27#ibcon#about to read 6, iclass 10, count 0 2006.217.07:52:19.27#ibcon#read 6, iclass 10, count 0 2006.217.07:52:19.27#ibcon#end of sib2, iclass 10, count 0 2006.217.07:52:19.27#ibcon#*after write, iclass 10, count 0 2006.217.07:52:19.27#ibcon#*before return 0, iclass 10, count 0 2006.217.07:52:19.27#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.217.07:52:19.27#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.217.07:52:19.27#ibcon#about to clear, iclass 10 cls_cnt 0 2006.217.07:52:19.27#ibcon#cleared, iclass 10 cls_cnt 0 2006.217.07:52:19.27$vc4f8/valo=5,652.99 2006.217.07:52:19.27#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.217.07:52:19.27#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.217.07:52:19.27#ibcon#ireg 17 cls_cnt 0 2006.217.07:52:19.27#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.217.07:52:19.27#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.217.07:52:19.27#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.217.07:52:19.27#ibcon#enter wrdev, iclass 12, count 0 2006.217.07:52:19.27#ibcon#first serial, iclass 12, count 0 2006.217.07:52:19.27#ibcon#enter sib2, iclass 12, count 0 2006.217.07:52:19.27#ibcon#flushed, iclass 12, count 0 2006.217.07:52:19.27#ibcon#about to write, iclass 12, count 0 2006.217.07:52:19.27#ibcon#wrote, iclass 12, count 0 2006.217.07:52:19.27#ibcon#about to read 3, iclass 12, count 0 2006.217.07:52:19.29#ibcon#read 3, iclass 12, count 0 2006.217.07:52:19.29#ibcon#about to read 4, iclass 12, count 0 2006.217.07:52:19.29#ibcon#read 4, iclass 12, count 0 2006.217.07:52:19.29#ibcon#about to read 5, iclass 12, count 0 2006.217.07:52:19.29#ibcon#read 5, iclass 12, count 0 2006.217.07:52:19.29#ibcon#about to read 6, iclass 12, count 0 2006.217.07:52:19.29#ibcon#read 6, iclass 12, count 0 2006.217.07:52:19.29#ibcon#end of sib2, iclass 12, count 0 2006.217.07:52:19.29#ibcon#*mode == 0, iclass 12, count 0 2006.217.07:52:19.29#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.217.07:52:19.29#ibcon#[26=FRQ=05,652.99\r\n] 2006.217.07:52:19.29#ibcon#*before write, iclass 12, count 0 2006.217.07:52:19.29#ibcon#enter sib2, iclass 12, count 0 2006.217.07:52:19.29#ibcon#flushed, iclass 12, count 0 2006.217.07:52:19.29#ibcon#about to write, iclass 12, count 0 2006.217.07:52:19.29#ibcon#wrote, iclass 12, count 0 2006.217.07:52:19.29#ibcon#about to read 3, iclass 12, count 0 2006.217.07:52:19.33#ibcon#read 3, iclass 12, count 0 2006.217.07:52:19.33#ibcon#about to read 4, iclass 12, count 0 2006.217.07:52:19.33#ibcon#read 4, iclass 12, count 0 2006.217.07:52:19.33#ibcon#about to read 5, iclass 12, count 0 2006.217.07:52:19.33#ibcon#read 5, iclass 12, count 0 2006.217.07:52:19.33#ibcon#about to read 6, iclass 12, count 0 2006.217.07:52:19.33#ibcon#read 6, iclass 12, count 0 2006.217.07:52:19.33#ibcon#end of sib2, iclass 12, count 0 2006.217.07:52:19.33#ibcon#*after write, iclass 12, count 0 2006.217.07:52:19.33#ibcon#*before return 0, iclass 12, count 0 2006.217.07:52:19.33#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.217.07:52:19.33#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.217.07:52:19.33#ibcon#about to clear, iclass 12 cls_cnt 0 2006.217.07:52:19.33#ibcon#cleared, iclass 12 cls_cnt 0 2006.217.07:52:19.33$vc4f8/va=5,7 2006.217.07:52:19.33#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.217.07:52:19.33#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.217.07:52:19.33#ibcon#ireg 11 cls_cnt 2 2006.217.07:52:19.33#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.217.07:52:19.39#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.217.07:52:19.39#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.217.07:52:19.39#ibcon#enter wrdev, iclass 14, count 2 2006.217.07:52:19.39#ibcon#first serial, iclass 14, count 2 2006.217.07:52:19.39#ibcon#enter sib2, iclass 14, count 2 2006.217.07:52:19.39#ibcon#flushed, iclass 14, count 2 2006.217.07:52:19.39#ibcon#about to write, iclass 14, count 2 2006.217.07:52:19.39#ibcon#wrote, iclass 14, count 2 2006.217.07:52:19.39#ibcon#about to read 3, iclass 14, count 2 2006.217.07:52:19.41#ibcon#read 3, iclass 14, count 2 2006.217.07:52:19.41#ibcon#about to read 4, iclass 14, count 2 2006.217.07:52:19.41#ibcon#read 4, iclass 14, count 2 2006.217.07:52:19.41#ibcon#about to read 5, iclass 14, count 2 2006.217.07:52:19.41#ibcon#read 5, iclass 14, count 2 2006.217.07:52:19.41#ibcon#about to read 6, iclass 14, count 2 2006.217.07:52:19.41#ibcon#read 6, iclass 14, count 2 2006.217.07:52:19.41#ibcon#end of sib2, iclass 14, count 2 2006.217.07:52:19.41#ibcon#*mode == 0, iclass 14, count 2 2006.217.07:52:19.41#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.217.07:52:19.41#ibcon#[25=AT05-07\r\n] 2006.217.07:52:19.41#ibcon#*before write, iclass 14, count 2 2006.217.07:52:19.41#ibcon#enter sib2, iclass 14, count 2 2006.217.07:52:19.41#ibcon#flushed, iclass 14, count 2 2006.217.07:52:19.41#ibcon#about to write, iclass 14, count 2 2006.217.07:52:19.41#ibcon#wrote, iclass 14, count 2 2006.217.07:52:19.41#ibcon#about to read 3, iclass 14, count 2 2006.217.07:52:19.44#ibcon#read 3, iclass 14, count 2 2006.217.07:52:19.44#ibcon#about to read 4, iclass 14, count 2 2006.217.07:52:19.44#ibcon#read 4, iclass 14, count 2 2006.217.07:52:19.44#ibcon#about to read 5, iclass 14, count 2 2006.217.07:52:19.44#ibcon#read 5, iclass 14, count 2 2006.217.07:52:19.44#ibcon#about to read 6, iclass 14, count 2 2006.217.07:52:19.44#ibcon#read 6, iclass 14, count 2 2006.217.07:52:19.44#ibcon#end of sib2, iclass 14, count 2 2006.217.07:52:19.44#ibcon#*after write, iclass 14, count 2 2006.217.07:52:19.44#ibcon#*before return 0, iclass 14, count 2 2006.217.07:52:19.44#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.217.07:52:19.44#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.217.07:52:19.44#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.217.07:52:19.44#ibcon#ireg 7 cls_cnt 0 2006.217.07:52:19.44#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.217.07:52:19.56#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.217.07:52:19.56#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.217.07:52:19.56#ibcon#enter wrdev, iclass 14, count 0 2006.217.07:52:19.56#ibcon#first serial, iclass 14, count 0 2006.217.07:52:19.56#ibcon#enter sib2, iclass 14, count 0 2006.217.07:52:19.56#ibcon#flushed, iclass 14, count 0 2006.217.07:52:19.56#ibcon#about to write, iclass 14, count 0 2006.217.07:52:19.56#ibcon#wrote, iclass 14, count 0 2006.217.07:52:19.56#ibcon#about to read 3, iclass 14, count 0 2006.217.07:52:19.58#ibcon#read 3, iclass 14, count 0 2006.217.07:52:19.58#ibcon#about to read 4, iclass 14, count 0 2006.217.07:52:19.58#ibcon#read 4, iclass 14, count 0 2006.217.07:52:19.58#ibcon#about to read 5, iclass 14, count 0 2006.217.07:52:19.58#ibcon#read 5, iclass 14, count 0 2006.217.07:52:19.58#ibcon#about to read 6, iclass 14, count 0 2006.217.07:52:19.58#ibcon#read 6, iclass 14, count 0 2006.217.07:52:19.58#ibcon#end of sib2, iclass 14, count 0 2006.217.07:52:19.58#ibcon#*mode == 0, iclass 14, count 0 2006.217.07:52:19.58#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.217.07:52:19.58#ibcon#[25=USB\r\n] 2006.217.07:52:19.58#ibcon#*before write, iclass 14, count 0 2006.217.07:52:19.58#ibcon#enter sib2, iclass 14, count 0 2006.217.07:52:19.58#ibcon#flushed, iclass 14, count 0 2006.217.07:52:19.58#ibcon#about to write, iclass 14, count 0 2006.217.07:52:19.58#ibcon#wrote, iclass 14, count 0 2006.217.07:52:19.58#ibcon#about to read 3, iclass 14, count 0 2006.217.07:52:19.61#ibcon#read 3, iclass 14, count 0 2006.217.07:52:19.61#ibcon#about to read 4, iclass 14, count 0 2006.217.07:52:19.61#ibcon#read 4, iclass 14, count 0 2006.217.07:52:19.61#ibcon#about to read 5, iclass 14, count 0 2006.217.07:52:19.61#ibcon#read 5, iclass 14, count 0 2006.217.07:52:19.61#ibcon#about to read 6, iclass 14, count 0 2006.217.07:52:19.61#ibcon#read 6, iclass 14, count 0 2006.217.07:52:19.61#ibcon#end of sib2, iclass 14, count 0 2006.217.07:52:19.61#ibcon#*after write, iclass 14, count 0 2006.217.07:52:19.61#ibcon#*before return 0, iclass 14, count 0 2006.217.07:52:19.61#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.217.07:52:19.61#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.217.07:52:19.61#ibcon#about to clear, iclass 14 cls_cnt 0 2006.217.07:52:19.61#ibcon#cleared, iclass 14 cls_cnt 0 2006.217.07:52:19.61$vc4f8/valo=6,772.99 2006.217.07:52:19.61#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.217.07:52:19.61#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.217.07:52:19.61#ibcon#ireg 17 cls_cnt 0 2006.217.07:52:19.61#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.217.07:52:19.61#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.217.07:52:19.61#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.217.07:52:19.61#ibcon#enter wrdev, iclass 16, count 0 2006.217.07:52:19.61#ibcon#first serial, iclass 16, count 0 2006.217.07:52:19.61#ibcon#enter sib2, iclass 16, count 0 2006.217.07:52:19.61#ibcon#flushed, iclass 16, count 0 2006.217.07:52:19.61#ibcon#about to write, iclass 16, count 0 2006.217.07:52:19.61#ibcon#wrote, iclass 16, count 0 2006.217.07:52:19.61#ibcon#about to read 3, iclass 16, count 0 2006.217.07:52:19.63#ibcon#read 3, iclass 16, count 0 2006.217.07:52:19.63#ibcon#about to read 4, iclass 16, count 0 2006.217.07:52:19.63#ibcon#read 4, iclass 16, count 0 2006.217.07:52:19.63#ibcon#about to read 5, iclass 16, count 0 2006.217.07:52:19.63#ibcon#read 5, iclass 16, count 0 2006.217.07:52:19.63#ibcon#about to read 6, iclass 16, count 0 2006.217.07:52:19.63#ibcon#read 6, iclass 16, count 0 2006.217.07:52:19.63#ibcon#end of sib2, iclass 16, count 0 2006.217.07:52:19.63#ibcon#*mode == 0, iclass 16, count 0 2006.217.07:52:19.63#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.217.07:52:19.63#ibcon#[26=FRQ=06,772.99\r\n] 2006.217.07:52:19.63#ibcon#*before write, iclass 16, count 0 2006.217.07:52:19.63#ibcon#enter sib2, iclass 16, count 0 2006.217.07:52:19.63#ibcon#flushed, iclass 16, count 0 2006.217.07:52:19.63#ibcon#about to write, iclass 16, count 0 2006.217.07:52:19.63#ibcon#wrote, iclass 16, count 0 2006.217.07:52:19.63#ibcon#about to read 3, iclass 16, count 0 2006.217.07:52:19.67#ibcon#read 3, iclass 16, count 0 2006.217.07:52:19.67#ibcon#about to read 4, iclass 16, count 0 2006.217.07:52:19.67#ibcon#read 4, iclass 16, count 0 2006.217.07:52:19.67#ibcon#about to read 5, iclass 16, count 0 2006.217.07:52:19.67#ibcon#read 5, iclass 16, count 0 2006.217.07:52:19.67#ibcon#about to read 6, iclass 16, count 0 2006.217.07:52:19.67#ibcon#read 6, iclass 16, count 0 2006.217.07:52:19.67#ibcon#end of sib2, iclass 16, count 0 2006.217.07:52:19.67#ibcon#*after write, iclass 16, count 0 2006.217.07:52:19.67#ibcon#*before return 0, iclass 16, count 0 2006.217.07:52:19.67#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.217.07:52:19.67#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.217.07:52:19.67#ibcon#about to clear, iclass 16 cls_cnt 0 2006.217.07:52:19.67#ibcon#cleared, iclass 16 cls_cnt 0 2006.217.07:52:19.67$vc4f8/va=6,6 2006.217.07:52:19.67#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.217.07:52:19.67#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.217.07:52:19.67#ibcon#ireg 11 cls_cnt 2 2006.217.07:52:19.67#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.217.07:52:19.73#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.217.07:52:19.73#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.217.07:52:19.73#ibcon#enter wrdev, iclass 18, count 2 2006.217.07:52:19.73#ibcon#first serial, iclass 18, count 2 2006.217.07:52:19.73#ibcon#enter sib2, iclass 18, count 2 2006.217.07:52:19.73#ibcon#flushed, iclass 18, count 2 2006.217.07:52:19.73#ibcon#about to write, iclass 18, count 2 2006.217.07:52:19.73#ibcon#wrote, iclass 18, count 2 2006.217.07:52:19.73#ibcon#about to read 3, iclass 18, count 2 2006.217.07:52:19.75#ibcon#read 3, iclass 18, count 2 2006.217.07:52:19.75#ibcon#about to read 4, iclass 18, count 2 2006.217.07:52:19.75#ibcon#read 4, iclass 18, count 2 2006.217.07:52:19.75#ibcon#about to read 5, iclass 18, count 2 2006.217.07:52:19.75#ibcon#read 5, iclass 18, count 2 2006.217.07:52:19.75#ibcon#about to read 6, iclass 18, count 2 2006.217.07:52:19.75#ibcon#read 6, iclass 18, count 2 2006.217.07:52:19.75#ibcon#end of sib2, iclass 18, count 2 2006.217.07:52:19.75#ibcon#*mode == 0, iclass 18, count 2 2006.217.07:52:19.75#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.217.07:52:19.75#ibcon#[25=AT06-06\r\n] 2006.217.07:52:19.75#ibcon#*before write, iclass 18, count 2 2006.217.07:52:19.75#ibcon#enter sib2, iclass 18, count 2 2006.217.07:52:19.75#ibcon#flushed, iclass 18, count 2 2006.217.07:52:19.75#ibcon#about to write, iclass 18, count 2 2006.217.07:52:19.75#ibcon#wrote, iclass 18, count 2 2006.217.07:52:19.75#ibcon#about to read 3, iclass 18, count 2 2006.217.07:52:19.78#ibcon#read 3, iclass 18, count 2 2006.217.07:52:19.78#ibcon#about to read 4, iclass 18, count 2 2006.217.07:52:19.78#ibcon#read 4, iclass 18, count 2 2006.217.07:52:19.78#ibcon#about to read 5, iclass 18, count 2 2006.217.07:52:19.78#ibcon#read 5, iclass 18, count 2 2006.217.07:52:19.78#ibcon#about to read 6, iclass 18, count 2 2006.217.07:52:19.78#ibcon#read 6, iclass 18, count 2 2006.217.07:52:19.78#ibcon#end of sib2, iclass 18, count 2 2006.217.07:52:19.78#ibcon#*after write, iclass 18, count 2 2006.217.07:52:19.78#ibcon#*before return 0, iclass 18, count 2 2006.217.07:52:19.78#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.217.07:52:19.78#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.217.07:52:19.78#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.217.07:52:19.78#ibcon#ireg 7 cls_cnt 0 2006.217.07:52:19.78#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.217.07:52:19.90#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.217.07:52:19.90#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.217.07:52:19.90#ibcon#enter wrdev, iclass 18, count 0 2006.217.07:52:19.90#ibcon#first serial, iclass 18, count 0 2006.217.07:52:19.90#ibcon#enter sib2, iclass 18, count 0 2006.217.07:52:19.90#ibcon#flushed, iclass 18, count 0 2006.217.07:52:19.90#ibcon#about to write, iclass 18, count 0 2006.217.07:52:19.90#ibcon#wrote, iclass 18, count 0 2006.217.07:52:19.90#ibcon#about to read 3, iclass 18, count 0 2006.217.07:52:19.92#ibcon#read 3, iclass 18, count 0 2006.217.07:52:19.92#ibcon#about to read 4, iclass 18, count 0 2006.217.07:52:19.92#ibcon#read 4, iclass 18, count 0 2006.217.07:52:19.92#ibcon#about to read 5, iclass 18, count 0 2006.217.07:52:19.92#ibcon#read 5, iclass 18, count 0 2006.217.07:52:19.92#ibcon#about to read 6, iclass 18, count 0 2006.217.07:52:19.92#ibcon#read 6, iclass 18, count 0 2006.217.07:52:19.92#ibcon#end of sib2, iclass 18, count 0 2006.217.07:52:19.92#ibcon#*mode == 0, iclass 18, count 0 2006.217.07:52:19.92#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.217.07:52:19.92#ibcon#[25=USB\r\n] 2006.217.07:52:19.92#ibcon#*before write, iclass 18, count 0 2006.217.07:52:19.92#ibcon#enter sib2, iclass 18, count 0 2006.217.07:52:19.92#ibcon#flushed, iclass 18, count 0 2006.217.07:52:19.92#ibcon#about to write, iclass 18, count 0 2006.217.07:52:19.92#ibcon#wrote, iclass 18, count 0 2006.217.07:52:19.92#ibcon#about to read 3, iclass 18, count 0 2006.217.07:52:19.95#ibcon#read 3, iclass 18, count 0 2006.217.07:52:19.95#ibcon#about to read 4, iclass 18, count 0 2006.217.07:52:19.95#ibcon#read 4, iclass 18, count 0 2006.217.07:52:19.95#ibcon#about to read 5, iclass 18, count 0 2006.217.07:52:19.95#ibcon#read 5, iclass 18, count 0 2006.217.07:52:19.95#ibcon#about to read 6, iclass 18, count 0 2006.217.07:52:19.95#ibcon#read 6, iclass 18, count 0 2006.217.07:52:19.95#ibcon#end of sib2, iclass 18, count 0 2006.217.07:52:19.95#ibcon#*after write, iclass 18, count 0 2006.217.07:52:19.95#ibcon#*before return 0, iclass 18, count 0 2006.217.07:52:19.95#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.217.07:52:19.95#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.217.07:52:19.95#ibcon#about to clear, iclass 18 cls_cnt 0 2006.217.07:52:19.95#ibcon#cleared, iclass 18 cls_cnt 0 2006.217.07:52:19.95$vc4f8/valo=7,832.99 2006.217.07:52:19.95#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.217.07:52:19.95#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.217.07:52:19.95#ibcon#ireg 17 cls_cnt 0 2006.217.07:52:19.95#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.217.07:52:19.95#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.217.07:52:19.95#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.217.07:52:19.95#ibcon#enter wrdev, iclass 20, count 0 2006.217.07:52:19.95#ibcon#first serial, iclass 20, count 0 2006.217.07:52:19.95#ibcon#enter sib2, iclass 20, count 0 2006.217.07:52:19.95#ibcon#flushed, iclass 20, count 0 2006.217.07:52:19.95#ibcon#about to write, iclass 20, count 0 2006.217.07:52:19.95#ibcon#wrote, iclass 20, count 0 2006.217.07:52:19.95#ibcon#about to read 3, iclass 20, count 0 2006.217.07:52:19.97#ibcon#read 3, iclass 20, count 0 2006.217.07:52:19.97#ibcon#about to read 4, iclass 20, count 0 2006.217.07:52:19.97#ibcon#read 4, iclass 20, count 0 2006.217.07:52:19.97#ibcon#about to read 5, iclass 20, count 0 2006.217.07:52:19.97#ibcon#read 5, iclass 20, count 0 2006.217.07:52:19.97#ibcon#about to read 6, iclass 20, count 0 2006.217.07:52:19.97#ibcon#read 6, iclass 20, count 0 2006.217.07:52:19.97#ibcon#end of sib2, iclass 20, count 0 2006.217.07:52:19.97#ibcon#*mode == 0, iclass 20, count 0 2006.217.07:52:19.97#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.217.07:52:19.97#ibcon#[26=FRQ=07,832.99\r\n] 2006.217.07:52:19.97#ibcon#*before write, iclass 20, count 0 2006.217.07:52:19.97#ibcon#enter sib2, iclass 20, count 0 2006.217.07:52:19.97#ibcon#flushed, iclass 20, count 0 2006.217.07:52:19.97#ibcon#about to write, iclass 20, count 0 2006.217.07:52:19.97#ibcon#wrote, iclass 20, count 0 2006.217.07:52:19.97#ibcon#about to read 3, iclass 20, count 0 2006.217.07:52:20.01#ibcon#read 3, iclass 20, count 0 2006.217.07:52:20.01#ibcon#about to read 4, iclass 20, count 0 2006.217.07:52:20.01#ibcon#read 4, iclass 20, count 0 2006.217.07:52:20.01#ibcon#about to read 5, iclass 20, count 0 2006.217.07:52:20.01#ibcon#read 5, iclass 20, count 0 2006.217.07:52:20.01#ibcon#about to read 6, iclass 20, count 0 2006.217.07:52:20.01#ibcon#read 6, iclass 20, count 0 2006.217.07:52:20.01#ibcon#end of sib2, iclass 20, count 0 2006.217.07:52:20.01#ibcon#*after write, iclass 20, count 0 2006.217.07:52:20.01#ibcon#*before return 0, iclass 20, count 0 2006.217.07:52:20.01#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.217.07:52:20.01#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.217.07:52:20.01#ibcon#about to clear, iclass 20 cls_cnt 0 2006.217.07:52:20.01#ibcon#cleared, iclass 20 cls_cnt 0 2006.217.07:52:20.01$vc4f8/va=7,6 2006.217.07:52:20.01#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.217.07:52:20.01#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.217.07:52:20.01#ibcon#ireg 11 cls_cnt 2 2006.217.07:52:20.01#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.217.07:52:20.07#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.217.07:52:20.07#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.217.07:52:20.07#ibcon#enter wrdev, iclass 22, count 2 2006.217.07:52:20.07#ibcon#first serial, iclass 22, count 2 2006.217.07:52:20.07#ibcon#enter sib2, iclass 22, count 2 2006.217.07:52:20.07#ibcon#flushed, iclass 22, count 2 2006.217.07:52:20.07#ibcon#about to write, iclass 22, count 2 2006.217.07:52:20.07#ibcon#wrote, iclass 22, count 2 2006.217.07:52:20.07#ibcon#about to read 3, iclass 22, count 2 2006.217.07:52:20.09#ibcon#read 3, iclass 22, count 2 2006.217.07:52:20.09#ibcon#about to read 4, iclass 22, count 2 2006.217.07:52:20.09#ibcon#read 4, iclass 22, count 2 2006.217.07:52:20.09#ibcon#about to read 5, iclass 22, count 2 2006.217.07:52:20.09#ibcon#read 5, iclass 22, count 2 2006.217.07:52:20.09#ibcon#about to read 6, iclass 22, count 2 2006.217.07:52:20.09#ibcon#read 6, iclass 22, count 2 2006.217.07:52:20.09#ibcon#end of sib2, iclass 22, count 2 2006.217.07:52:20.09#ibcon#*mode == 0, iclass 22, count 2 2006.217.07:52:20.09#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.217.07:52:20.09#ibcon#[25=AT07-06\r\n] 2006.217.07:52:20.09#ibcon#*before write, iclass 22, count 2 2006.217.07:52:20.09#ibcon#enter sib2, iclass 22, count 2 2006.217.07:52:20.09#ibcon#flushed, iclass 22, count 2 2006.217.07:52:20.09#ibcon#about to write, iclass 22, count 2 2006.217.07:52:20.09#ibcon#wrote, iclass 22, count 2 2006.217.07:52:20.09#ibcon#about to read 3, iclass 22, count 2 2006.217.07:52:20.12#ibcon#read 3, iclass 22, count 2 2006.217.07:52:20.12#ibcon#about to read 4, iclass 22, count 2 2006.217.07:52:20.12#ibcon#read 4, iclass 22, count 2 2006.217.07:52:20.12#ibcon#about to read 5, iclass 22, count 2 2006.217.07:52:20.12#ibcon#read 5, iclass 22, count 2 2006.217.07:52:20.12#ibcon#about to read 6, iclass 22, count 2 2006.217.07:52:20.12#ibcon#read 6, iclass 22, count 2 2006.217.07:52:20.12#ibcon#end of sib2, iclass 22, count 2 2006.217.07:52:20.12#ibcon#*after write, iclass 22, count 2 2006.217.07:52:20.12#ibcon#*before return 0, iclass 22, count 2 2006.217.07:52:20.12#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.217.07:52:20.12#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.217.07:52:20.12#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.217.07:52:20.12#ibcon#ireg 7 cls_cnt 0 2006.217.07:52:20.12#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.217.07:52:20.24#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.217.07:52:20.24#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.217.07:52:20.24#ibcon#enter wrdev, iclass 22, count 0 2006.217.07:52:20.24#ibcon#first serial, iclass 22, count 0 2006.217.07:52:20.24#ibcon#enter sib2, iclass 22, count 0 2006.217.07:52:20.24#ibcon#flushed, iclass 22, count 0 2006.217.07:52:20.24#ibcon#about to write, iclass 22, count 0 2006.217.07:52:20.24#ibcon#wrote, iclass 22, count 0 2006.217.07:52:20.24#ibcon#about to read 3, iclass 22, count 0 2006.217.07:52:20.26#ibcon#read 3, iclass 22, count 0 2006.217.07:52:20.26#ibcon#about to read 4, iclass 22, count 0 2006.217.07:52:20.26#ibcon#read 4, iclass 22, count 0 2006.217.07:52:20.26#ibcon#about to read 5, iclass 22, count 0 2006.217.07:52:20.26#ibcon#read 5, iclass 22, count 0 2006.217.07:52:20.26#ibcon#about to read 6, iclass 22, count 0 2006.217.07:52:20.26#ibcon#read 6, iclass 22, count 0 2006.217.07:52:20.26#ibcon#end of sib2, iclass 22, count 0 2006.217.07:52:20.26#ibcon#*mode == 0, iclass 22, count 0 2006.217.07:52:20.26#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.217.07:52:20.26#ibcon#[25=USB\r\n] 2006.217.07:52:20.26#ibcon#*before write, iclass 22, count 0 2006.217.07:52:20.26#ibcon#enter sib2, iclass 22, count 0 2006.217.07:52:20.26#ibcon#flushed, iclass 22, count 0 2006.217.07:52:20.26#ibcon#about to write, iclass 22, count 0 2006.217.07:52:20.26#ibcon#wrote, iclass 22, count 0 2006.217.07:52:20.26#ibcon#about to read 3, iclass 22, count 0 2006.217.07:52:20.29#ibcon#read 3, iclass 22, count 0 2006.217.07:52:20.29#ibcon#about to read 4, iclass 22, count 0 2006.217.07:52:20.29#ibcon#read 4, iclass 22, count 0 2006.217.07:52:20.29#ibcon#about to read 5, iclass 22, count 0 2006.217.07:52:20.29#ibcon#read 5, iclass 22, count 0 2006.217.07:52:20.29#ibcon#about to read 6, iclass 22, count 0 2006.217.07:52:20.29#ibcon#read 6, iclass 22, count 0 2006.217.07:52:20.29#ibcon#end of sib2, iclass 22, count 0 2006.217.07:52:20.29#ibcon#*after write, iclass 22, count 0 2006.217.07:52:20.29#ibcon#*before return 0, iclass 22, count 0 2006.217.07:52:20.29#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.217.07:52:20.29#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.217.07:52:20.29#ibcon#about to clear, iclass 22 cls_cnt 0 2006.217.07:52:20.29#ibcon#cleared, iclass 22 cls_cnt 0 2006.217.07:52:20.29$vc4f8/valo=8,852.99 2006.217.07:52:20.29#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.217.07:52:20.29#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.217.07:52:20.29#ibcon#ireg 17 cls_cnt 0 2006.217.07:52:20.29#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.217.07:52:20.29#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.217.07:52:20.29#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.217.07:52:20.29#ibcon#enter wrdev, iclass 24, count 0 2006.217.07:52:20.29#ibcon#first serial, iclass 24, count 0 2006.217.07:52:20.29#ibcon#enter sib2, iclass 24, count 0 2006.217.07:52:20.29#ibcon#flushed, iclass 24, count 0 2006.217.07:52:20.29#ibcon#about to write, iclass 24, count 0 2006.217.07:52:20.29#ibcon#wrote, iclass 24, count 0 2006.217.07:52:20.29#ibcon#about to read 3, iclass 24, count 0 2006.217.07:52:20.31#ibcon#read 3, iclass 24, count 0 2006.217.07:52:20.31#ibcon#about to read 4, iclass 24, count 0 2006.217.07:52:20.31#ibcon#read 4, iclass 24, count 0 2006.217.07:52:20.31#ibcon#about to read 5, iclass 24, count 0 2006.217.07:52:20.31#ibcon#read 5, iclass 24, count 0 2006.217.07:52:20.31#ibcon#about to read 6, iclass 24, count 0 2006.217.07:52:20.31#ibcon#read 6, iclass 24, count 0 2006.217.07:52:20.31#ibcon#end of sib2, iclass 24, count 0 2006.217.07:52:20.31#ibcon#*mode == 0, iclass 24, count 0 2006.217.07:52:20.31#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.217.07:52:20.31#ibcon#[26=FRQ=08,852.99\r\n] 2006.217.07:52:20.31#ibcon#*before write, iclass 24, count 0 2006.217.07:52:20.31#ibcon#enter sib2, iclass 24, count 0 2006.217.07:52:20.31#ibcon#flushed, iclass 24, count 0 2006.217.07:52:20.31#ibcon#about to write, iclass 24, count 0 2006.217.07:52:20.31#ibcon#wrote, iclass 24, count 0 2006.217.07:52:20.31#ibcon#about to read 3, iclass 24, count 0 2006.217.07:52:20.35#ibcon#read 3, iclass 24, count 0 2006.217.07:52:20.35#ibcon#about to read 4, iclass 24, count 0 2006.217.07:52:20.35#ibcon#read 4, iclass 24, count 0 2006.217.07:52:20.35#ibcon#about to read 5, iclass 24, count 0 2006.217.07:52:20.35#ibcon#read 5, iclass 24, count 0 2006.217.07:52:20.35#ibcon#about to read 6, iclass 24, count 0 2006.217.07:52:20.35#ibcon#read 6, iclass 24, count 0 2006.217.07:52:20.35#ibcon#end of sib2, iclass 24, count 0 2006.217.07:52:20.35#ibcon#*after write, iclass 24, count 0 2006.217.07:52:20.35#ibcon#*before return 0, iclass 24, count 0 2006.217.07:52:20.35#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.217.07:52:20.35#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.217.07:52:20.35#ibcon#about to clear, iclass 24 cls_cnt 0 2006.217.07:52:20.35#ibcon#cleared, iclass 24 cls_cnt 0 2006.217.07:52:20.35$vc4f8/va=8,7 2006.217.07:52:20.35#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.217.07:52:20.35#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.217.07:52:20.35#ibcon#ireg 11 cls_cnt 2 2006.217.07:52:20.35#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.217.07:52:20.41#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.217.07:52:20.41#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.217.07:52:20.41#ibcon#enter wrdev, iclass 26, count 2 2006.217.07:52:20.41#ibcon#first serial, iclass 26, count 2 2006.217.07:52:20.41#ibcon#enter sib2, iclass 26, count 2 2006.217.07:52:20.41#ibcon#flushed, iclass 26, count 2 2006.217.07:52:20.41#ibcon#about to write, iclass 26, count 2 2006.217.07:52:20.41#ibcon#wrote, iclass 26, count 2 2006.217.07:52:20.41#ibcon#about to read 3, iclass 26, count 2 2006.217.07:52:20.43#ibcon#read 3, iclass 26, count 2 2006.217.07:52:20.43#ibcon#about to read 4, iclass 26, count 2 2006.217.07:52:20.43#ibcon#read 4, iclass 26, count 2 2006.217.07:52:20.43#ibcon#about to read 5, iclass 26, count 2 2006.217.07:52:20.43#ibcon#read 5, iclass 26, count 2 2006.217.07:52:20.43#ibcon#about to read 6, iclass 26, count 2 2006.217.07:52:20.43#ibcon#read 6, iclass 26, count 2 2006.217.07:52:20.43#ibcon#end of sib2, iclass 26, count 2 2006.217.07:52:20.43#ibcon#*mode == 0, iclass 26, count 2 2006.217.07:52:20.43#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.217.07:52:20.43#ibcon#[25=AT08-07\r\n] 2006.217.07:52:20.43#ibcon#*before write, iclass 26, count 2 2006.217.07:52:20.43#ibcon#enter sib2, iclass 26, count 2 2006.217.07:52:20.43#ibcon#flushed, iclass 26, count 2 2006.217.07:52:20.43#ibcon#about to write, iclass 26, count 2 2006.217.07:52:20.43#ibcon#wrote, iclass 26, count 2 2006.217.07:52:20.43#ibcon#about to read 3, iclass 26, count 2 2006.217.07:52:20.46#ibcon#read 3, iclass 26, count 2 2006.217.07:52:20.46#ibcon#about to read 4, iclass 26, count 2 2006.217.07:52:20.46#ibcon#read 4, iclass 26, count 2 2006.217.07:52:20.46#ibcon#about to read 5, iclass 26, count 2 2006.217.07:52:20.46#ibcon#read 5, iclass 26, count 2 2006.217.07:52:20.46#ibcon#about to read 6, iclass 26, count 2 2006.217.07:52:20.46#ibcon#read 6, iclass 26, count 2 2006.217.07:52:20.46#ibcon#end of sib2, iclass 26, count 2 2006.217.07:52:20.46#ibcon#*after write, iclass 26, count 2 2006.217.07:52:20.46#ibcon#*before return 0, iclass 26, count 2 2006.217.07:52:20.46#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.217.07:52:20.46#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.217.07:52:20.46#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.217.07:52:20.46#ibcon#ireg 7 cls_cnt 0 2006.217.07:52:20.46#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.217.07:52:20.58#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.217.07:52:20.58#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.217.07:52:20.58#ibcon#enter wrdev, iclass 26, count 0 2006.217.07:52:20.58#ibcon#first serial, iclass 26, count 0 2006.217.07:52:20.58#ibcon#enter sib2, iclass 26, count 0 2006.217.07:52:20.58#ibcon#flushed, iclass 26, count 0 2006.217.07:52:20.58#ibcon#about to write, iclass 26, count 0 2006.217.07:52:20.58#ibcon#wrote, iclass 26, count 0 2006.217.07:52:20.58#ibcon#about to read 3, iclass 26, count 0 2006.217.07:52:20.60#ibcon#read 3, iclass 26, count 0 2006.217.07:52:20.60#ibcon#about to read 4, iclass 26, count 0 2006.217.07:52:20.60#ibcon#read 4, iclass 26, count 0 2006.217.07:52:20.60#ibcon#about to read 5, iclass 26, count 0 2006.217.07:52:20.60#ibcon#read 5, iclass 26, count 0 2006.217.07:52:20.60#ibcon#about to read 6, iclass 26, count 0 2006.217.07:52:20.60#ibcon#read 6, iclass 26, count 0 2006.217.07:52:20.60#ibcon#end of sib2, iclass 26, count 0 2006.217.07:52:20.60#ibcon#*mode == 0, iclass 26, count 0 2006.217.07:52:20.60#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.217.07:52:20.60#ibcon#[25=USB\r\n] 2006.217.07:52:20.60#ibcon#*before write, iclass 26, count 0 2006.217.07:52:20.60#ibcon#enter sib2, iclass 26, count 0 2006.217.07:52:20.60#ibcon#flushed, iclass 26, count 0 2006.217.07:52:20.60#ibcon#about to write, iclass 26, count 0 2006.217.07:52:20.60#ibcon#wrote, iclass 26, count 0 2006.217.07:52:20.60#ibcon#about to read 3, iclass 26, count 0 2006.217.07:52:20.63#ibcon#read 3, iclass 26, count 0 2006.217.07:52:20.63#ibcon#about to read 4, iclass 26, count 0 2006.217.07:52:20.63#ibcon#read 4, iclass 26, count 0 2006.217.07:52:20.63#ibcon#about to read 5, iclass 26, count 0 2006.217.07:52:20.63#ibcon#read 5, iclass 26, count 0 2006.217.07:52:20.63#ibcon#about to read 6, iclass 26, count 0 2006.217.07:52:20.63#ibcon#read 6, iclass 26, count 0 2006.217.07:52:20.63#ibcon#end of sib2, iclass 26, count 0 2006.217.07:52:20.63#ibcon#*after write, iclass 26, count 0 2006.217.07:52:20.63#ibcon#*before return 0, iclass 26, count 0 2006.217.07:52:20.63#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.217.07:52:20.63#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.217.07:52:20.63#ibcon#about to clear, iclass 26 cls_cnt 0 2006.217.07:52:20.63#ibcon#cleared, iclass 26 cls_cnt 0 2006.217.07:52:20.63$vc4f8/vblo=1,632.99 2006.217.07:52:20.63#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.217.07:52:20.63#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.217.07:52:20.63#ibcon#ireg 17 cls_cnt 0 2006.217.07:52:20.63#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.217.07:52:20.63#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.217.07:52:20.63#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.217.07:52:20.63#ibcon#enter wrdev, iclass 28, count 0 2006.217.07:52:20.63#ibcon#first serial, iclass 28, count 0 2006.217.07:52:20.63#ibcon#enter sib2, iclass 28, count 0 2006.217.07:52:20.63#ibcon#flushed, iclass 28, count 0 2006.217.07:52:20.63#ibcon#about to write, iclass 28, count 0 2006.217.07:52:20.63#ibcon#wrote, iclass 28, count 0 2006.217.07:52:20.63#ibcon#about to read 3, iclass 28, count 0 2006.217.07:52:20.66#ibcon#read 3, iclass 28, count 0 2006.217.07:52:20.66#ibcon#about to read 4, iclass 28, count 0 2006.217.07:52:20.66#ibcon#read 4, iclass 28, count 0 2006.217.07:52:20.66#ibcon#about to read 5, iclass 28, count 0 2006.217.07:52:20.66#ibcon#read 5, iclass 28, count 0 2006.217.07:52:20.66#ibcon#about to read 6, iclass 28, count 0 2006.217.07:52:20.66#ibcon#read 6, iclass 28, count 0 2006.217.07:52:20.66#ibcon#end of sib2, iclass 28, count 0 2006.217.07:52:20.66#ibcon#*mode == 0, iclass 28, count 0 2006.217.07:52:20.66#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.217.07:52:20.66#ibcon#[28=FRQ=01,632.99\r\n] 2006.217.07:52:20.66#ibcon#*before write, iclass 28, count 0 2006.217.07:52:20.66#ibcon#enter sib2, iclass 28, count 0 2006.217.07:52:20.66#ibcon#flushed, iclass 28, count 0 2006.217.07:52:20.66#ibcon#about to write, iclass 28, count 0 2006.217.07:52:20.66#ibcon#wrote, iclass 28, count 0 2006.217.07:52:20.66#ibcon#about to read 3, iclass 28, count 0 2006.217.07:52:20.70#ibcon#read 3, iclass 28, count 0 2006.217.07:52:20.70#ibcon#about to read 4, iclass 28, count 0 2006.217.07:52:20.70#ibcon#read 4, iclass 28, count 0 2006.217.07:52:20.70#ibcon#about to read 5, iclass 28, count 0 2006.217.07:52:20.70#ibcon#read 5, iclass 28, count 0 2006.217.07:52:20.70#ibcon#about to read 6, iclass 28, count 0 2006.217.07:52:20.70#ibcon#read 6, iclass 28, count 0 2006.217.07:52:20.70#ibcon#end of sib2, iclass 28, count 0 2006.217.07:52:20.70#ibcon#*after write, iclass 28, count 0 2006.217.07:52:20.70#ibcon#*before return 0, iclass 28, count 0 2006.217.07:52:20.70#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.217.07:52:20.70#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.217.07:52:20.70#ibcon#about to clear, iclass 28 cls_cnt 0 2006.217.07:52:20.70#ibcon#cleared, iclass 28 cls_cnt 0 2006.217.07:52:20.70$vc4f8/vb=1,4 2006.217.07:52:20.70#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.217.07:52:20.70#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.217.07:52:20.70#ibcon#ireg 11 cls_cnt 2 2006.217.07:52:20.70#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.217.07:52:20.70#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.217.07:52:20.70#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.217.07:52:20.70#ibcon#enter wrdev, iclass 30, count 2 2006.217.07:52:20.70#ibcon#first serial, iclass 30, count 2 2006.217.07:52:20.70#ibcon#enter sib2, iclass 30, count 2 2006.217.07:52:20.70#ibcon#flushed, iclass 30, count 2 2006.217.07:52:20.70#ibcon#about to write, iclass 30, count 2 2006.217.07:52:20.70#ibcon#wrote, iclass 30, count 2 2006.217.07:52:20.70#ibcon#about to read 3, iclass 30, count 2 2006.217.07:52:20.72#ibcon#read 3, iclass 30, count 2 2006.217.07:52:20.72#ibcon#about to read 4, iclass 30, count 2 2006.217.07:52:20.72#ibcon#read 4, iclass 30, count 2 2006.217.07:52:20.72#ibcon#about to read 5, iclass 30, count 2 2006.217.07:52:20.72#ibcon#read 5, iclass 30, count 2 2006.217.07:52:20.72#ibcon#about to read 6, iclass 30, count 2 2006.217.07:52:20.72#ibcon#read 6, iclass 30, count 2 2006.217.07:52:20.72#ibcon#end of sib2, iclass 30, count 2 2006.217.07:52:20.72#ibcon#*mode == 0, iclass 30, count 2 2006.217.07:52:20.72#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.217.07:52:20.72#ibcon#[27=AT01-04\r\n] 2006.217.07:52:20.72#ibcon#*before write, iclass 30, count 2 2006.217.07:52:20.72#ibcon#enter sib2, iclass 30, count 2 2006.217.07:52:20.72#ibcon#flushed, iclass 30, count 2 2006.217.07:52:20.72#ibcon#about to write, iclass 30, count 2 2006.217.07:52:20.72#ibcon#wrote, iclass 30, count 2 2006.217.07:52:20.72#ibcon#about to read 3, iclass 30, count 2 2006.217.07:52:20.75#ibcon#read 3, iclass 30, count 2 2006.217.07:52:20.75#ibcon#about to read 4, iclass 30, count 2 2006.217.07:52:20.75#ibcon#read 4, iclass 30, count 2 2006.217.07:52:20.75#ibcon#about to read 5, iclass 30, count 2 2006.217.07:52:20.75#ibcon#read 5, iclass 30, count 2 2006.217.07:52:20.75#ibcon#about to read 6, iclass 30, count 2 2006.217.07:52:20.75#ibcon#read 6, iclass 30, count 2 2006.217.07:52:20.75#ibcon#end of sib2, iclass 30, count 2 2006.217.07:52:20.75#ibcon#*after write, iclass 30, count 2 2006.217.07:52:20.75#ibcon#*before return 0, iclass 30, count 2 2006.217.07:52:20.75#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.217.07:52:20.75#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.217.07:52:20.75#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.217.07:52:20.75#ibcon#ireg 7 cls_cnt 0 2006.217.07:52:20.75#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.217.07:52:20.87#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.217.07:52:20.87#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.217.07:52:20.87#ibcon#enter wrdev, iclass 30, count 0 2006.217.07:52:20.87#ibcon#first serial, iclass 30, count 0 2006.217.07:52:20.87#ibcon#enter sib2, iclass 30, count 0 2006.217.07:52:20.87#ibcon#flushed, iclass 30, count 0 2006.217.07:52:20.87#ibcon#about to write, iclass 30, count 0 2006.217.07:52:20.87#ibcon#wrote, iclass 30, count 0 2006.217.07:52:20.87#ibcon#about to read 3, iclass 30, count 0 2006.217.07:52:20.89#ibcon#read 3, iclass 30, count 0 2006.217.07:52:20.89#ibcon#about to read 4, iclass 30, count 0 2006.217.07:52:20.89#ibcon#read 4, iclass 30, count 0 2006.217.07:52:20.89#ibcon#about to read 5, iclass 30, count 0 2006.217.07:52:20.89#ibcon#read 5, iclass 30, count 0 2006.217.07:52:20.89#ibcon#about to read 6, iclass 30, count 0 2006.217.07:52:20.89#ibcon#read 6, iclass 30, count 0 2006.217.07:52:20.89#ibcon#end of sib2, iclass 30, count 0 2006.217.07:52:20.89#ibcon#*mode == 0, iclass 30, count 0 2006.217.07:52:20.89#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.217.07:52:20.89#ibcon#[27=USB\r\n] 2006.217.07:52:20.89#ibcon#*before write, iclass 30, count 0 2006.217.07:52:20.89#ibcon#enter sib2, iclass 30, count 0 2006.217.07:52:20.89#ibcon#flushed, iclass 30, count 0 2006.217.07:52:20.89#ibcon#about to write, iclass 30, count 0 2006.217.07:52:20.89#ibcon#wrote, iclass 30, count 0 2006.217.07:52:20.89#ibcon#about to read 3, iclass 30, count 0 2006.217.07:52:20.92#ibcon#read 3, iclass 30, count 0 2006.217.07:52:20.92#ibcon#about to read 4, iclass 30, count 0 2006.217.07:52:20.92#ibcon#read 4, iclass 30, count 0 2006.217.07:52:20.92#ibcon#about to read 5, iclass 30, count 0 2006.217.07:52:20.92#ibcon#read 5, iclass 30, count 0 2006.217.07:52:20.92#ibcon#about to read 6, iclass 30, count 0 2006.217.07:52:20.92#ibcon#read 6, iclass 30, count 0 2006.217.07:52:20.92#ibcon#end of sib2, iclass 30, count 0 2006.217.07:52:20.92#ibcon#*after write, iclass 30, count 0 2006.217.07:52:20.92#ibcon#*before return 0, iclass 30, count 0 2006.217.07:52:20.92#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.217.07:52:20.92#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.217.07:52:20.92#ibcon#about to clear, iclass 30 cls_cnt 0 2006.217.07:52:20.92#ibcon#cleared, iclass 30 cls_cnt 0 2006.217.07:52:20.92$vc4f8/vblo=2,640.99 2006.217.07:52:20.92#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.217.07:52:20.92#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.217.07:52:20.92#ibcon#ireg 17 cls_cnt 0 2006.217.07:52:20.92#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.217.07:52:20.92#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.217.07:52:20.92#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.217.07:52:20.92#ibcon#enter wrdev, iclass 32, count 0 2006.217.07:52:20.92#ibcon#first serial, iclass 32, count 0 2006.217.07:52:20.92#ibcon#enter sib2, iclass 32, count 0 2006.217.07:52:20.92#ibcon#flushed, iclass 32, count 0 2006.217.07:52:20.92#ibcon#about to write, iclass 32, count 0 2006.217.07:52:20.92#ibcon#wrote, iclass 32, count 0 2006.217.07:52:20.92#ibcon#about to read 3, iclass 32, count 0 2006.217.07:52:20.94#ibcon#read 3, iclass 32, count 0 2006.217.07:52:20.94#ibcon#about to read 4, iclass 32, count 0 2006.217.07:52:20.94#ibcon#read 4, iclass 32, count 0 2006.217.07:52:20.94#ibcon#about to read 5, iclass 32, count 0 2006.217.07:52:20.94#ibcon#read 5, iclass 32, count 0 2006.217.07:52:20.94#ibcon#about to read 6, iclass 32, count 0 2006.217.07:52:20.94#ibcon#read 6, iclass 32, count 0 2006.217.07:52:20.94#ibcon#end of sib2, iclass 32, count 0 2006.217.07:52:20.94#ibcon#*mode == 0, iclass 32, count 0 2006.217.07:52:20.94#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.217.07:52:20.94#ibcon#[28=FRQ=02,640.99\r\n] 2006.217.07:52:20.94#ibcon#*before write, iclass 32, count 0 2006.217.07:52:20.94#ibcon#enter sib2, iclass 32, count 0 2006.217.07:52:20.94#ibcon#flushed, iclass 32, count 0 2006.217.07:52:20.94#ibcon#about to write, iclass 32, count 0 2006.217.07:52:20.94#ibcon#wrote, iclass 32, count 0 2006.217.07:52:20.94#ibcon#about to read 3, iclass 32, count 0 2006.217.07:52:20.98#ibcon#read 3, iclass 32, count 0 2006.217.07:52:20.98#ibcon#about to read 4, iclass 32, count 0 2006.217.07:52:20.98#ibcon#read 4, iclass 32, count 0 2006.217.07:52:20.98#ibcon#about to read 5, iclass 32, count 0 2006.217.07:52:20.98#ibcon#read 5, iclass 32, count 0 2006.217.07:52:20.98#ibcon#about to read 6, iclass 32, count 0 2006.217.07:52:20.98#ibcon#read 6, iclass 32, count 0 2006.217.07:52:20.98#ibcon#end of sib2, iclass 32, count 0 2006.217.07:52:20.98#ibcon#*after write, iclass 32, count 0 2006.217.07:52:20.98#ibcon#*before return 0, iclass 32, count 0 2006.217.07:52:20.98#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.217.07:52:20.98#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.217.07:52:20.98#ibcon#about to clear, iclass 32 cls_cnt 0 2006.217.07:52:20.98#ibcon#cleared, iclass 32 cls_cnt 0 2006.217.07:52:20.98$vc4f8/vb=2,4 2006.217.07:52:20.98#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.217.07:52:20.98#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.217.07:52:20.98#ibcon#ireg 11 cls_cnt 2 2006.217.07:52:20.98#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.217.07:52:21.04#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.217.07:52:21.04#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.217.07:52:21.04#ibcon#enter wrdev, iclass 34, count 2 2006.217.07:52:21.04#ibcon#first serial, iclass 34, count 2 2006.217.07:52:21.04#ibcon#enter sib2, iclass 34, count 2 2006.217.07:52:21.04#ibcon#flushed, iclass 34, count 2 2006.217.07:52:21.04#ibcon#about to write, iclass 34, count 2 2006.217.07:52:21.04#ibcon#wrote, iclass 34, count 2 2006.217.07:52:21.04#ibcon#about to read 3, iclass 34, count 2 2006.217.07:52:21.06#ibcon#read 3, iclass 34, count 2 2006.217.07:52:21.06#ibcon#about to read 4, iclass 34, count 2 2006.217.07:52:21.06#ibcon#read 4, iclass 34, count 2 2006.217.07:52:21.06#ibcon#about to read 5, iclass 34, count 2 2006.217.07:52:21.06#ibcon#read 5, iclass 34, count 2 2006.217.07:52:21.06#ibcon#about to read 6, iclass 34, count 2 2006.217.07:52:21.06#ibcon#read 6, iclass 34, count 2 2006.217.07:52:21.06#ibcon#end of sib2, iclass 34, count 2 2006.217.07:52:21.06#ibcon#*mode == 0, iclass 34, count 2 2006.217.07:52:21.06#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.217.07:52:21.06#ibcon#[27=AT02-04\r\n] 2006.217.07:52:21.06#ibcon#*before write, iclass 34, count 2 2006.217.07:52:21.06#ibcon#enter sib2, iclass 34, count 2 2006.217.07:52:21.06#ibcon#flushed, iclass 34, count 2 2006.217.07:52:21.06#ibcon#about to write, iclass 34, count 2 2006.217.07:52:21.06#ibcon#wrote, iclass 34, count 2 2006.217.07:52:21.06#ibcon#about to read 3, iclass 34, count 2 2006.217.07:52:21.09#ibcon#read 3, iclass 34, count 2 2006.217.07:52:21.09#ibcon#about to read 4, iclass 34, count 2 2006.217.07:52:21.09#ibcon#read 4, iclass 34, count 2 2006.217.07:52:21.09#ibcon#about to read 5, iclass 34, count 2 2006.217.07:52:21.09#ibcon#read 5, iclass 34, count 2 2006.217.07:52:21.09#ibcon#about to read 6, iclass 34, count 2 2006.217.07:52:21.09#ibcon#read 6, iclass 34, count 2 2006.217.07:52:21.09#ibcon#end of sib2, iclass 34, count 2 2006.217.07:52:21.09#ibcon#*after write, iclass 34, count 2 2006.217.07:52:21.09#ibcon#*before return 0, iclass 34, count 2 2006.217.07:52:21.09#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.217.07:52:21.09#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.217.07:52:21.09#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.217.07:52:21.09#ibcon#ireg 7 cls_cnt 0 2006.217.07:52:21.09#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.217.07:52:21.21#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.217.07:52:21.21#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.217.07:52:21.21#ibcon#enter wrdev, iclass 34, count 0 2006.217.07:52:21.21#ibcon#first serial, iclass 34, count 0 2006.217.07:52:21.21#ibcon#enter sib2, iclass 34, count 0 2006.217.07:52:21.21#ibcon#flushed, iclass 34, count 0 2006.217.07:52:21.21#ibcon#about to write, iclass 34, count 0 2006.217.07:52:21.21#ibcon#wrote, iclass 34, count 0 2006.217.07:52:21.21#ibcon#about to read 3, iclass 34, count 0 2006.217.07:52:21.23#ibcon#read 3, iclass 34, count 0 2006.217.07:52:21.23#ibcon#about to read 4, iclass 34, count 0 2006.217.07:52:21.23#ibcon#read 4, iclass 34, count 0 2006.217.07:52:21.23#ibcon#about to read 5, iclass 34, count 0 2006.217.07:52:21.23#ibcon#read 5, iclass 34, count 0 2006.217.07:52:21.23#ibcon#about to read 6, iclass 34, count 0 2006.217.07:52:21.23#ibcon#read 6, iclass 34, count 0 2006.217.07:52:21.23#ibcon#end of sib2, iclass 34, count 0 2006.217.07:52:21.23#ibcon#*mode == 0, iclass 34, count 0 2006.217.07:52:21.23#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.217.07:52:21.23#ibcon#[27=USB\r\n] 2006.217.07:52:21.23#ibcon#*before write, iclass 34, count 0 2006.217.07:52:21.23#ibcon#enter sib2, iclass 34, count 0 2006.217.07:52:21.23#ibcon#flushed, iclass 34, count 0 2006.217.07:52:21.23#ibcon#about to write, iclass 34, count 0 2006.217.07:52:21.23#ibcon#wrote, iclass 34, count 0 2006.217.07:52:21.23#ibcon#about to read 3, iclass 34, count 0 2006.217.07:52:21.26#ibcon#read 3, iclass 34, count 0 2006.217.07:52:21.26#ibcon#about to read 4, iclass 34, count 0 2006.217.07:52:21.26#ibcon#read 4, iclass 34, count 0 2006.217.07:52:21.26#ibcon#about to read 5, iclass 34, count 0 2006.217.07:52:21.26#ibcon#read 5, iclass 34, count 0 2006.217.07:52:21.26#ibcon#about to read 6, iclass 34, count 0 2006.217.07:52:21.26#ibcon#read 6, iclass 34, count 0 2006.217.07:52:21.26#ibcon#end of sib2, iclass 34, count 0 2006.217.07:52:21.26#ibcon#*after write, iclass 34, count 0 2006.217.07:52:21.26#ibcon#*before return 0, iclass 34, count 0 2006.217.07:52:21.26#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.217.07:52:21.26#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.217.07:52:21.26#ibcon#about to clear, iclass 34 cls_cnt 0 2006.217.07:52:21.26#ibcon#cleared, iclass 34 cls_cnt 0 2006.217.07:52:21.26$vc4f8/vblo=3,656.99 2006.217.07:52:21.26#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.217.07:52:21.26#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.217.07:52:21.26#ibcon#ireg 17 cls_cnt 0 2006.217.07:52:21.26#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.217.07:52:21.26#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.217.07:52:21.26#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.217.07:52:21.26#ibcon#enter wrdev, iclass 36, count 0 2006.217.07:52:21.26#ibcon#first serial, iclass 36, count 0 2006.217.07:52:21.26#ibcon#enter sib2, iclass 36, count 0 2006.217.07:52:21.26#ibcon#flushed, iclass 36, count 0 2006.217.07:52:21.26#ibcon#about to write, iclass 36, count 0 2006.217.07:52:21.26#ibcon#wrote, iclass 36, count 0 2006.217.07:52:21.26#ibcon#about to read 3, iclass 36, count 0 2006.217.07:52:21.28#ibcon#read 3, iclass 36, count 0 2006.217.07:52:21.28#ibcon#about to read 4, iclass 36, count 0 2006.217.07:52:21.28#ibcon#read 4, iclass 36, count 0 2006.217.07:52:21.28#ibcon#about to read 5, iclass 36, count 0 2006.217.07:52:21.28#ibcon#read 5, iclass 36, count 0 2006.217.07:52:21.28#ibcon#about to read 6, iclass 36, count 0 2006.217.07:52:21.28#ibcon#read 6, iclass 36, count 0 2006.217.07:52:21.28#ibcon#end of sib2, iclass 36, count 0 2006.217.07:52:21.28#ibcon#*mode == 0, iclass 36, count 0 2006.217.07:52:21.28#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.217.07:52:21.28#ibcon#[28=FRQ=03,656.99\r\n] 2006.217.07:52:21.28#ibcon#*before write, iclass 36, count 0 2006.217.07:52:21.28#ibcon#enter sib2, iclass 36, count 0 2006.217.07:52:21.28#ibcon#flushed, iclass 36, count 0 2006.217.07:52:21.28#ibcon#about to write, iclass 36, count 0 2006.217.07:52:21.28#ibcon#wrote, iclass 36, count 0 2006.217.07:52:21.28#ibcon#about to read 3, iclass 36, count 0 2006.217.07:52:21.32#ibcon#read 3, iclass 36, count 0 2006.217.07:52:21.32#ibcon#about to read 4, iclass 36, count 0 2006.217.07:52:21.32#ibcon#read 4, iclass 36, count 0 2006.217.07:52:21.32#ibcon#about to read 5, iclass 36, count 0 2006.217.07:52:21.32#ibcon#read 5, iclass 36, count 0 2006.217.07:52:21.32#ibcon#about to read 6, iclass 36, count 0 2006.217.07:52:21.32#ibcon#read 6, iclass 36, count 0 2006.217.07:52:21.32#ibcon#end of sib2, iclass 36, count 0 2006.217.07:52:21.32#ibcon#*after write, iclass 36, count 0 2006.217.07:52:21.32#ibcon#*before return 0, iclass 36, count 0 2006.217.07:52:21.32#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.217.07:52:21.32#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.217.07:52:21.32#ibcon#about to clear, iclass 36 cls_cnt 0 2006.217.07:52:21.32#ibcon#cleared, iclass 36 cls_cnt 0 2006.217.07:52:21.32$vc4f8/vb=3,4 2006.217.07:52:21.32#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.217.07:52:21.32#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.217.07:52:21.32#ibcon#ireg 11 cls_cnt 2 2006.217.07:52:21.32#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.217.07:52:21.38#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.217.07:52:21.38#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.217.07:52:21.38#ibcon#enter wrdev, iclass 38, count 2 2006.217.07:52:21.38#ibcon#first serial, iclass 38, count 2 2006.217.07:52:21.38#ibcon#enter sib2, iclass 38, count 2 2006.217.07:52:21.38#ibcon#flushed, iclass 38, count 2 2006.217.07:52:21.38#ibcon#about to write, iclass 38, count 2 2006.217.07:52:21.38#ibcon#wrote, iclass 38, count 2 2006.217.07:52:21.38#ibcon#about to read 3, iclass 38, count 2 2006.217.07:52:21.40#ibcon#read 3, iclass 38, count 2 2006.217.07:52:21.40#ibcon#about to read 4, iclass 38, count 2 2006.217.07:52:21.40#ibcon#read 4, iclass 38, count 2 2006.217.07:52:21.40#ibcon#about to read 5, iclass 38, count 2 2006.217.07:52:21.40#ibcon#read 5, iclass 38, count 2 2006.217.07:52:21.40#ibcon#about to read 6, iclass 38, count 2 2006.217.07:52:21.40#ibcon#read 6, iclass 38, count 2 2006.217.07:52:21.40#ibcon#end of sib2, iclass 38, count 2 2006.217.07:52:21.40#ibcon#*mode == 0, iclass 38, count 2 2006.217.07:52:21.40#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.217.07:52:21.40#ibcon#[27=AT03-04\r\n] 2006.217.07:52:21.40#ibcon#*before write, iclass 38, count 2 2006.217.07:52:21.40#ibcon#enter sib2, iclass 38, count 2 2006.217.07:52:21.40#ibcon#flushed, iclass 38, count 2 2006.217.07:52:21.40#ibcon#about to write, iclass 38, count 2 2006.217.07:52:21.40#ibcon#wrote, iclass 38, count 2 2006.217.07:52:21.40#ibcon#about to read 3, iclass 38, count 2 2006.217.07:52:21.43#ibcon#read 3, iclass 38, count 2 2006.217.07:52:21.43#ibcon#about to read 4, iclass 38, count 2 2006.217.07:52:21.43#ibcon#read 4, iclass 38, count 2 2006.217.07:52:21.43#ibcon#about to read 5, iclass 38, count 2 2006.217.07:52:21.43#ibcon#read 5, iclass 38, count 2 2006.217.07:52:21.43#ibcon#about to read 6, iclass 38, count 2 2006.217.07:52:21.43#ibcon#read 6, iclass 38, count 2 2006.217.07:52:21.43#ibcon#end of sib2, iclass 38, count 2 2006.217.07:52:21.43#ibcon#*after write, iclass 38, count 2 2006.217.07:52:21.43#ibcon#*before return 0, iclass 38, count 2 2006.217.07:52:21.43#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.217.07:52:21.43#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.217.07:52:21.43#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.217.07:52:21.43#ibcon#ireg 7 cls_cnt 0 2006.217.07:52:21.43#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.217.07:52:21.55#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.217.07:52:21.55#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.217.07:52:21.55#ibcon#enter wrdev, iclass 38, count 0 2006.217.07:52:21.55#ibcon#first serial, iclass 38, count 0 2006.217.07:52:21.55#ibcon#enter sib2, iclass 38, count 0 2006.217.07:52:21.55#ibcon#flushed, iclass 38, count 0 2006.217.07:52:21.55#ibcon#about to write, iclass 38, count 0 2006.217.07:52:21.55#ibcon#wrote, iclass 38, count 0 2006.217.07:52:21.55#ibcon#about to read 3, iclass 38, count 0 2006.217.07:52:21.57#ibcon#read 3, iclass 38, count 0 2006.217.07:52:21.57#ibcon#about to read 4, iclass 38, count 0 2006.217.07:52:21.57#ibcon#read 4, iclass 38, count 0 2006.217.07:52:21.57#ibcon#about to read 5, iclass 38, count 0 2006.217.07:52:21.57#ibcon#read 5, iclass 38, count 0 2006.217.07:52:21.57#ibcon#about to read 6, iclass 38, count 0 2006.217.07:52:21.57#ibcon#read 6, iclass 38, count 0 2006.217.07:52:21.57#ibcon#end of sib2, iclass 38, count 0 2006.217.07:52:21.57#ibcon#*mode == 0, iclass 38, count 0 2006.217.07:52:21.57#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.217.07:52:21.57#ibcon#[27=USB\r\n] 2006.217.07:52:21.57#ibcon#*before write, iclass 38, count 0 2006.217.07:52:21.57#ibcon#enter sib2, iclass 38, count 0 2006.217.07:52:21.57#ibcon#flushed, iclass 38, count 0 2006.217.07:52:21.57#ibcon#about to write, iclass 38, count 0 2006.217.07:52:21.57#ibcon#wrote, iclass 38, count 0 2006.217.07:52:21.57#ibcon#about to read 3, iclass 38, count 0 2006.217.07:52:21.60#ibcon#read 3, iclass 38, count 0 2006.217.07:52:21.60#ibcon#about to read 4, iclass 38, count 0 2006.217.07:52:21.60#ibcon#read 4, iclass 38, count 0 2006.217.07:52:21.60#ibcon#about to read 5, iclass 38, count 0 2006.217.07:52:21.60#ibcon#read 5, iclass 38, count 0 2006.217.07:52:21.60#ibcon#about to read 6, iclass 38, count 0 2006.217.07:52:21.60#ibcon#read 6, iclass 38, count 0 2006.217.07:52:21.60#ibcon#end of sib2, iclass 38, count 0 2006.217.07:52:21.60#ibcon#*after write, iclass 38, count 0 2006.217.07:52:21.60#ibcon#*before return 0, iclass 38, count 0 2006.217.07:52:21.60#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.217.07:52:21.60#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.217.07:52:21.60#ibcon#about to clear, iclass 38 cls_cnt 0 2006.217.07:52:21.60#ibcon#cleared, iclass 38 cls_cnt 0 2006.217.07:52:21.60$vc4f8/vblo=4,712.99 2006.217.07:52:21.60#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.217.07:52:21.60#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.217.07:52:21.60#ibcon#ireg 17 cls_cnt 0 2006.217.07:52:21.60#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.217.07:52:21.60#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.217.07:52:21.60#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.217.07:52:21.60#ibcon#enter wrdev, iclass 40, count 0 2006.217.07:52:21.60#ibcon#first serial, iclass 40, count 0 2006.217.07:52:21.60#ibcon#enter sib2, iclass 40, count 0 2006.217.07:52:21.60#ibcon#flushed, iclass 40, count 0 2006.217.07:52:21.60#ibcon#about to write, iclass 40, count 0 2006.217.07:52:21.60#ibcon#wrote, iclass 40, count 0 2006.217.07:52:21.60#ibcon#about to read 3, iclass 40, count 0 2006.217.07:52:21.62#ibcon#read 3, iclass 40, count 0 2006.217.07:52:21.62#ibcon#about to read 4, iclass 40, count 0 2006.217.07:52:21.62#ibcon#read 4, iclass 40, count 0 2006.217.07:52:21.62#ibcon#about to read 5, iclass 40, count 0 2006.217.07:52:21.62#ibcon#read 5, iclass 40, count 0 2006.217.07:52:21.62#ibcon#about to read 6, iclass 40, count 0 2006.217.07:52:21.62#ibcon#read 6, iclass 40, count 0 2006.217.07:52:21.62#ibcon#end of sib2, iclass 40, count 0 2006.217.07:52:21.62#ibcon#*mode == 0, iclass 40, count 0 2006.217.07:52:21.62#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.217.07:52:21.62#ibcon#[28=FRQ=04,712.99\r\n] 2006.217.07:52:21.62#ibcon#*before write, iclass 40, count 0 2006.217.07:52:21.62#ibcon#enter sib2, iclass 40, count 0 2006.217.07:52:21.62#ibcon#flushed, iclass 40, count 0 2006.217.07:52:21.62#ibcon#about to write, iclass 40, count 0 2006.217.07:52:21.62#ibcon#wrote, iclass 40, count 0 2006.217.07:52:21.62#ibcon#about to read 3, iclass 40, count 0 2006.217.07:52:21.66#ibcon#read 3, iclass 40, count 0 2006.217.07:52:21.66#ibcon#about to read 4, iclass 40, count 0 2006.217.07:52:21.66#ibcon#read 4, iclass 40, count 0 2006.217.07:52:21.66#ibcon#about to read 5, iclass 40, count 0 2006.217.07:52:21.66#ibcon#read 5, iclass 40, count 0 2006.217.07:52:21.66#ibcon#about to read 6, iclass 40, count 0 2006.217.07:52:21.66#ibcon#read 6, iclass 40, count 0 2006.217.07:52:21.66#ibcon#end of sib2, iclass 40, count 0 2006.217.07:52:21.66#ibcon#*after write, iclass 40, count 0 2006.217.07:52:21.66#ibcon#*before return 0, iclass 40, count 0 2006.217.07:52:21.66#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.217.07:52:21.66#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.217.07:52:21.66#ibcon#about to clear, iclass 40 cls_cnt 0 2006.217.07:52:21.66#ibcon#cleared, iclass 40 cls_cnt 0 2006.217.07:52:21.66$vc4f8/vb=4,4 2006.217.07:52:21.66#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.217.07:52:21.66#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.217.07:52:21.66#ibcon#ireg 11 cls_cnt 2 2006.217.07:52:21.66#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.217.07:52:21.72#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.217.07:52:21.72#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.217.07:52:21.72#ibcon#enter wrdev, iclass 4, count 2 2006.217.07:52:21.72#ibcon#first serial, iclass 4, count 2 2006.217.07:52:21.72#ibcon#enter sib2, iclass 4, count 2 2006.217.07:52:21.72#ibcon#flushed, iclass 4, count 2 2006.217.07:52:21.72#ibcon#about to write, iclass 4, count 2 2006.217.07:52:21.72#ibcon#wrote, iclass 4, count 2 2006.217.07:52:21.72#ibcon#about to read 3, iclass 4, count 2 2006.217.07:52:21.74#ibcon#read 3, iclass 4, count 2 2006.217.07:52:21.74#ibcon#about to read 4, iclass 4, count 2 2006.217.07:52:21.74#ibcon#read 4, iclass 4, count 2 2006.217.07:52:21.74#ibcon#about to read 5, iclass 4, count 2 2006.217.07:52:21.74#ibcon#read 5, iclass 4, count 2 2006.217.07:52:21.74#ibcon#about to read 6, iclass 4, count 2 2006.217.07:52:21.74#ibcon#read 6, iclass 4, count 2 2006.217.07:52:21.74#ibcon#end of sib2, iclass 4, count 2 2006.217.07:52:21.74#ibcon#*mode == 0, iclass 4, count 2 2006.217.07:52:21.74#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.217.07:52:21.74#ibcon#[27=AT04-04\r\n] 2006.217.07:52:21.74#ibcon#*before write, iclass 4, count 2 2006.217.07:52:21.74#ibcon#enter sib2, iclass 4, count 2 2006.217.07:52:21.74#ibcon#flushed, iclass 4, count 2 2006.217.07:52:21.74#ibcon#about to write, iclass 4, count 2 2006.217.07:52:21.74#ibcon#wrote, iclass 4, count 2 2006.217.07:52:21.74#ibcon#about to read 3, iclass 4, count 2 2006.217.07:52:21.77#ibcon#read 3, iclass 4, count 2 2006.217.07:52:21.77#ibcon#about to read 4, iclass 4, count 2 2006.217.07:52:21.77#ibcon#read 4, iclass 4, count 2 2006.217.07:52:21.77#ibcon#about to read 5, iclass 4, count 2 2006.217.07:52:21.77#ibcon#read 5, iclass 4, count 2 2006.217.07:52:21.77#ibcon#about to read 6, iclass 4, count 2 2006.217.07:52:21.77#ibcon#read 6, iclass 4, count 2 2006.217.07:52:21.77#ibcon#end of sib2, iclass 4, count 2 2006.217.07:52:21.77#ibcon#*after write, iclass 4, count 2 2006.217.07:52:21.77#ibcon#*before return 0, iclass 4, count 2 2006.217.07:52:21.77#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.217.07:52:21.77#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.217.07:52:21.77#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.217.07:52:21.77#ibcon#ireg 7 cls_cnt 0 2006.217.07:52:21.77#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.217.07:52:21.89#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.217.07:52:21.89#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.217.07:52:21.89#ibcon#enter wrdev, iclass 4, count 0 2006.217.07:52:21.89#ibcon#first serial, iclass 4, count 0 2006.217.07:52:21.89#ibcon#enter sib2, iclass 4, count 0 2006.217.07:52:21.89#ibcon#flushed, iclass 4, count 0 2006.217.07:52:21.89#ibcon#about to write, iclass 4, count 0 2006.217.07:52:21.89#ibcon#wrote, iclass 4, count 0 2006.217.07:52:21.89#ibcon#about to read 3, iclass 4, count 0 2006.217.07:52:21.91#ibcon#read 3, iclass 4, count 0 2006.217.07:52:21.91#ibcon#about to read 4, iclass 4, count 0 2006.217.07:52:21.91#ibcon#read 4, iclass 4, count 0 2006.217.07:52:21.91#ibcon#about to read 5, iclass 4, count 0 2006.217.07:52:21.91#ibcon#read 5, iclass 4, count 0 2006.217.07:52:21.91#ibcon#about to read 6, iclass 4, count 0 2006.217.07:52:21.91#ibcon#read 6, iclass 4, count 0 2006.217.07:52:21.91#ibcon#end of sib2, iclass 4, count 0 2006.217.07:52:21.91#ibcon#*mode == 0, iclass 4, count 0 2006.217.07:52:21.91#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.217.07:52:21.91#ibcon#[27=USB\r\n] 2006.217.07:52:21.91#ibcon#*before write, iclass 4, count 0 2006.217.07:52:21.91#ibcon#enter sib2, iclass 4, count 0 2006.217.07:52:21.91#ibcon#flushed, iclass 4, count 0 2006.217.07:52:21.91#ibcon#about to write, iclass 4, count 0 2006.217.07:52:21.91#ibcon#wrote, iclass 4, count 0 2006.217.07:52:21.91#ibcon#about to read 3, iclass 4, count 0 2006.217.07:52:21.94#ibcon#read 3, iclass 4, count 0 2006.217.07:52:21.94#ibcon#about to read 4, iclass 4, count 0 2006.217.07:52:21.94#ibcon#read 4, iclass 4, count 0 2006.217.07:52:21.94#ibcon#about to read 5, iclass 4, count 0 2006.217.07:52:21.94#ibcon#read 5, iclass 4, count 0 2006.217.07:52:21.94#ibcon#about to read 6, iclass 4, count 0 2006.217.07:52:21.94#ibcon#read 6, iclass 4, count 0 2006.217.07:52:21.94#ibcon#end of sib2, iclass 4, count 0 2006.217.07:52:21.94#ibcon#*after write, iclass 4, count 0 2006.217.07:52:21.94#ibcon#*before return 0, iclass 4, count 0 2006.217.07:52:21.94#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.217.07:52:21.94#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.217.07:52:21.94#ibcon#about to clear, iclass 4 cls_cnt 0 2006.217.07:52:21.94#ibcon#cleared, iclass 4 cls_cnt 0 2006.217.07:52:21.94$vc4f8/vblo=5,744.99 2006.217.07:52:21.94#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.217.07:52:21.94#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.217.07:52:21.94#ibcon#ireg 17 cls_cnt 0 2006.217.07:52:21.94#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.217.07:52:21.94#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.217.07:52:21.94#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.217.07:52:21.94#ibcon#enter wrdev, iclass 6, count 0 2006.217.07:52:21.94#ibcon#first serial, iclass 6, count 0 2006.217.07:52:21.94#ibcon#enter sib2, iclass 6, count 0 2006.217.07:52:21.94#ibcon#flushed, iclass 6, count 0 2006.217.07:52:21.94#ibcon#about to write, iclass 6, count 0 2006.217.07:52:21.94#ibcon#wrote, iclass 6, count 0 2006.217.07:52:21.94#ibcon#about to read 3, iclass 6, count 0 2006.217.07:52:21.96#ibcon#read 3, iclass 6, count 0 2006.217.07:52:21.96#ibcon#about to read 4, iclass 6, count 0 2006.217.07:52:21.96#ibcon#read 4, iclass 6, count 0 2006.217.07:52:21.96#ibcon#about to read 5, iclass 6, count 0 2006.217.07:52:21.96#ibcon#read 5, iclass 6, count 0 2006.217.07:52:21.96#ibcon#about to read 6, iclass 6, count 0 2006.217.07:52:21.96#ibcon#read 6, iclass 6, count 0 2006.217.07:52:21.96#ibcon#end of sib2, iclass 6, count 0 2006.217.07:52:21.96#ibcon#*mode == 0, iclass 6, count 0 2006.217.07:52:21.96#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.217.07:52:21.96#ibcon#[28=FRQ=05,744.99\r\n] 2006.217.07:52:21.96#ibcon#*before write, iclass 6, count 0 2006.217.07:52:21.96#ibcon#enter sib2, iclass 6, count 0 2006.217.07:52:21.96#ibcon#flushed, iclass 6, count 0 2006.217.07:52:21.96#ibcon#about to write, iclass 6, count 0 2006.217.07:52:21.96#ibcon#wrote, iclass 6, count 0 2006.217.07:52:21.96#ibcon#about to read 3, iclass 6, count 0 2006.217.07:52:22.00#ibcon#read 3, iclass 6, count 0 2006.217.07:52:22.00#ibcon#about to read 4, iclass 6, count 0 2006.217.07:52:22.00#ibcon#read 4, iclass 6, count 0 2006.217.07:52:22.00#ibcon#about to read 5, iclass 6, count 0 2006.217.07:52:22.00#ibcon#read 5, iclass 6, count 0 2006.217.07:52:22.00#ibcon#about to read 6, iclass 6, count 0 2006.217.07:52:22.00#ibcon#read 6, iclass 6, count 0 2006.217.07:52:22.00#ibcon#end of sib2, iclass 6, count 0 2006.217.07:52:22.00#ibcon#*after write, iclass 6, count 0 2006.217.07:52:22.00#ibcon#*before return 0, iclass 6, count 0 2006.217.07:52:22.00#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.217.07:52:22.00#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.217.07:52:22.00#ibcon#about to clear, iclass 6 cls_cnt 0 2006.217.07:52:22.00#ibcon#cleared, iclass 6 cls_cnt 0 2006.217.07:52:22.00$vc4f8/vb=5,4 2006.217.07:52:22.00#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.217.07:52:22.00#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.217.07:52:22.00#ibcon#ireg 11 cls_cnt 2 2006.217.07:52:22.00#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.217.07:52:22.06#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.217.07:52:22.06#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.217.07:52:22.06#ibcon#enter wrdev, iclass 10, count 2 2006.217.07:52:22.06#ibcon#first serial, iclass 10, count 2 2006.217.07:52:22.06#ibcon#enter sib2, iclass 10, count 2 2006.217.07:52:22.06#ibcon#flushed, iclass 10, count 2 2006.217.07:52:22.06#ibcon#about to write, iclass 10, count 2 2006.217.07:52:22.06#ibcon#wrote, iclass 10, count 2 2006.217.07:52:22.06#ibcon#about to read 3, iclass 10, count 2 2006.217.07:52:22.08#ibcon#read 3, iclass 10, count 2 2006.217.07:52:22.08#ibcon#about to read 4, iclass 10, count 2 2006.217.07:52:22.08#ibcon#read 4, iclass 10, count 2 2006.217.07:52:22.08#ibcon#about to read 5, iclass 10, count 2 2006.217.07:52:22.08#ibcon#read 5, iclass 10, count 2 2006.217.07:52:22.08#ibcon#about to read 6, iclass 10, count 2 2006.217.07:52:22.08#ibcon#read 6, iclass 10, count 2 2006.217.07:52:22.08#ibcon#end of sib2, iclass 10, count 2 2006.217.07:52:22.08#ibcon#*mode == 0, iclass 10, count 2 2006.217.07:52:22.08#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.217.07:52:22.08#ibcon#[27=AT05-04\r\n] 2006.217.07:52:22.08#ibcon#*before write, iclass 10, count 2 2006.217.07:52:22.08#ibcon#enter sib2, iclass 10, count 2 2006.217.07:52:22.08#ibcon#flushed, iclass 10, count 2 2006.217.07:52:22.08#ibcon#about to write, iclass 10, count 2 2006.217.07:52:22.08#ibcon#wrote, iclass 10, count 2 2006.217.07:52:22.08#ibcon#about to read 3, iclass 10, count 2 2006.217.07:52:22.11#ibcon#read 3, iclass 10, count 2 2006.217.07:52:22.11#ibcon#about to read 4, iclass 10, count 2 2006.217.07:52:22.11#ibcon#read 4, iclass 10, count 2 2006.217.07:52:22.11#ibcon#about to read 5, iclass 10, count 2 2006.217.07:52:22.11#ibcon#read 5, iclass 10, count 2 2006.217.07:52:22.11#ibcon#about to read 6, iclass 10, count 2 2006.217.07:52:22.11#ibcon#read 6, iclass 10, count 2 2006.217.07:52:22.11#ibcon#end of sib2, iclass 10, count 2 2006.217.07:52:22.11#ibcon#*after write, iclass 10, count 2 2006.217.07:52:22.11#ibcon#*before return 0, iclass 10, count 2 2006.217.07:52:22.11#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.217.07:52:22.11#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.217.07:52:22.11#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.217.07:52:22.11#ibcon#ireg 7 cls_cnt 0 2006.217.07:52:22.11#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.217.07:52:22.23#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.217.07:52:22.23#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.217.07:52:22.23#ibcon#enter wrdev, iclass 10, count 0 2006.217.07:52:22.23#ibcon#first serial, iclass 10, count 0 2006.217.07:52:22.23#ibcon#enter sib2, iclass 10, count 0 2006.217.07:52:22.23#ibcon#flushed, iclass 10, count 0 2006.217.07:52:22.23#ibcon#about to write, iclass 10, count 0 2006.217.07:52:22.23#ibcon#wrote, iclass 10, count 0 2006.217.07:52:22.23#ibcon#about to read 3, iclass 10, count 0 2006.217.07:52:22.25#ibcon#read 3, iclass 10, count 0 2006.217.07:52:22.25#ibcon#about to read 4, iclass 10, count 0 2006.217.07:52:22.25#ibcon#read 4, iclass 10, count 0 2006.217.07:52:22.25#ibcon#about to read 5, iclass 10, count 0 2006.217.07:52:22.25#ibcon#read 5, iclass 10, count 0 2006.217.07:52:22.25#ibcon#about to read 6, iclass 10, count 0 2006.217.07:52:22.25#ibcon#read 6, iclass 10, count 0 2006.217.07:52:22.25#ibcon#end of sib2, iclass 10, count 0 2006.217.07:52:22.25#ibcon#*mode == 0, iclass 10, count 0 2006.217.07:52:22.25#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.217.07:52:22.25#ibcon#[27=USB\r\n] 2006.217.07:52:22.25#ibcon#*before write, iclass 10, count 0 2006.217.07:52:22.25#ibcon#enter sib2, iclass 10, count 0 2006.217.07:52:22.25#ibcon#flushed, iclass 10, count 0 2006.217.07:52:22.25#ibcon#about to write, iclass 10, count 0 2006.217.07:52:22.25#ibcon#wrote, iclass 10, count 0 2006.217.07:52:22.25#ibcon#about to read 3, iclass 10, count 0 2006.217.07:52:22.28#ibcon#read 3, iclass 10, count 0 2006.217.07:52:22.28#ibcon#about to read 4, iclass 10, count 0 2006.217.07:52:22.28#ibcon#read 4, iclass 10, count 0 2006.217.07:52:22.28#ibcon#about to read 5, iclass 10, count 0 2006.217.07:52:22.28#ibcon#read 5, iclass 10, count 0 2006.217.07:52:22.28#ibcon#about to read 6, iclass 10, count 0 2006.217.07:52:22.28#ibcon#read 6, iclass 10, count 0 2006.217.07:52:22.28#ibcon#end of sib2, iclass 10, count 0 2006.217.07:52:22.28#ibcon#*after write, iclass 10, count 0 2006.217.07:52:22.28#ibcon#*before return 0, iclass 10, count 0 2006.217.07:52:22.28#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.217.07:52:22.28#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.217.07:52:22.28#ibcon#about to clear, iclass 10 cls_cnt 0 2006.217.07:52:22.28#ibcon#cleared, iclass 10 cls_cnt 0 2006.217.07:52:22.28$vc4f8/vblo=6,752.99 2006.217.07:52:22.28#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.217.07:52:22.28#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.217.07:52:22.28#ibcon#ireg 17 cls_cnt 0 2006.217.07:52:22.28#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.217.07:52:22.28#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.217.07:52:22.28#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.217.07:52:22.28#ibcon#enter wrdev, iclass 12, count 0 2006.217.07:52:22.28#ibcon#first serial, iclass 12, count 0 2006.217.07:52:22.28#ibcon#enter sib2, iclass 12, count 0 2006.217.07:52:22.28#ibcon#flushed, iclass 12, count 0 2006.217.07:52:22.28#ibcon#about to write, iclass 12, count 0 2006.217.07:52:22.28#ibcon#wrote, iclass 12, count 0 2006.217.07:52:22.28#ibcon#about to read 3, iclass 12, count 0 2006.217.07:52:22.30#ibcon#read 3, iclass 12, count 0 2006.217.07:52:22.30#ibcon#about to read 4, iclass 12, count 0 2006.217.07:52:22.30#ibcon#read 4, iclass 12, count 0 2006.217.07:52:22.30#ibcon#about to read 5, iclass 12, count 0 2006.217.07:52:22.30#ibcon#read 5, iclass 12, count 0 2006.217.07:52:22.30#ibcon#about to read 6, iclass 12, count 0 2006.217.07:52:22.30#ibcon#read 6, iclass 12, count 0 2006.217.07:52:22.30#ibcon#end of sib2, iclass 12, count 0 2006.217.07:52:22.30#ibcon#*mode == 0, iclass 12, count 0 2006.217.07:52:22.30#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.217.07:52:22.30#ibcon#[28=FRQ=06,752.99\r\n] 2006.217.07:52:22.30#ibcon#*before write, iclass 12, count 0 2006.217.07:52:22.30#ibcon#enter sib2, iclass 12, count 0 2006.217.07:52:22.30#ibcon#flushed, iclass 12, count 0 2006.217.07:52:22.30#ibcon#about to write, iclass 12, count 0 2006.217.07:52:22.30#ibcon#wrote, iclass 12, count 0 2006.217.07:52:22.30#ibcon#about to read 3, iclass 12, count 0 2006.217.07:52:22.34#ibcon#read 3, iclass 12, count 0 2006.217.07:52:22.34#ibcon#about to read 4, iclass 12, count 0 2006.217.07:52:22.34#ibcon#read 4, iclass 12, count 0 2006.217.07:52:22.34#ibcon#about to read 5, iclass 12, count 0 2006.217.07:52:22.34#ibcon#read 5, iclass 12, count 0 2006.217.07:52:22.34#ibcon#about to read 6, iclass 12, count 0 2006.217.07:52:22.34#ibcon#read 6, iclass 12, count 0 2006.217.07:52:22.34#ibcon#end of sib2, iclass 12, count 0 2006.217.07:52:22.34#ibcon#*after write, iclass 12, count 0 2006.217.07:52:22.34#ibcon#*before return 0, iclass 12, count 0 2006.217.07:52:22.34#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.217.07:52:22.34#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.217.07:52:22.34#ibcon#about to clear, iclass 12 cls_cnt 0 2006.217.07:52:22.34#ibcon#cleared, iclass 12 cls_cnt 0 2006.217.07:52:22.34$vc4f8/vb=6,4 2006.217.07:52:22.34#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.217.07:52:22.34#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.217.07:52:22.34#ibcon#ireg 11 cls_cnt 2 2006.217.07:52:22.34#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.217.07:52:22.40#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.217.07:52:22.40#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.217.07:52:22.40#ibcon#enter wrdev, iclass 14, count 2 2006.217.07:52:22.40#ibcon#first serial, iclass 14, count 2 2006.217.07:52:22.40#ibcon#enter sib2, iclass 14, count 2 2006.217.07:52:22.40#ibcon#flushed, iclass 14, count 2 2006.217.07:52:22.40#ibcon#about to write, iclass 14, count 2 2006.217.07:52:22.40#ibcon#wrote, iclass 14, count 2 2006.217.07:52:22.40#ibcon#about to read 3, iclass 14, count 2 2006.217.07:52:22.42#ibcon#read 3, iclass 14, count 2 2006.217.07:52:22.42#ibcon#about to read 4, iclass 14, count 2 2006.217.07:52:22.42#ibcon#read 4, iclass 14, count 2 2006.217.07:52:22.42#ibcon#about to read 5, iclass 14, count 2 2006.217.07:52:22.42#ibcon#read 5, iclass 14, count 2 2006.217.07:52:22.42#ibcon#about to read 6, iclass 14, count 2 2006.217.07:52:22.42#ibcon#read 6, iclass 14, count 2 2006.217.07:52:22.42#ibcon#end of sib2, iclass 14, count 2 2006.217.07:52:22.42#ibcon#*mode == 0, iclass 14, count 2 2006.217.07:52:22.42#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.217.07:52:22.42#ibcon#[27=AT06-04\r\n] 2006.217.07:52:22.42#ibcon#*before write, iclass 14, count 2 2006.217.07:52:22.42#ibcon#enter sib2, iclass 14, count 2 2006.217.07:52:22.42#ibcon#flushed, iclass 14, count 2 2006.217.07:52:22.42#ibcon#about to write, iclass 14, count 2 2006.217.07:52:22.42#ibcon#wrote, iclass 14, count 2 2006.217.07:52:22.42#ibcon#about to read 3, iclass 14, count 2 2006.217.07:52:22.45#ibcon#read 3, iclass 14, count 2 2006.217.07:52:22.45#ibcon#about to read 4, iclass 14, count 2 2006.217.07:52:22.45#ibcon#read 4, iclass 14, count 2 2006.217.07:52:22.45#ibcon#about to read 5, iclass 14, count 2 2006.217.07:52:22.45#ibcon#read 5, iclass 14, count 2 2006.217.07:52:22.45#ibcon#about to read 6, iclass 14, count 2 2006.217.07:52:22.45#ibcon#read 6, iclass 14, count 2 2006.217.07:52:22.45#ibcon#end of sib2, iclass 14, count 2 2006.217.07:52:22.45#ibcon#*after write, iclass 14, count 2 2006.217.07:52:22.45#ibcon#*before return 0, iclass 14, count 2 2006.217.07:52:22.45#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.217.07:52:22.45#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.217.07:52:22.45#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.217.07:52:22.45#ibcon#ireg 7 cls_cnt 0 2006.217.07:52:22.45#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.217.07:52:22.57#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.217.07:52:22.57#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.217.07:52:22.57#ibcon#enter wrdev, iclass 14, count 0 2006.217.07:52:22.57#ibcon#first serial, iclass 14, count 0 2006.217.07:52:22.57#ibcon#enter sib2, iclass 14, count 0 2006.217.07:52:22.57#ibcon#flushed, iclass 14, count 0 2006.217.07:52:22.57#ibcon#about to write, iclass 14, count 0 2006.217.07:52:22.57#ibcon#wrote, iclass 14, count 0 2006.217.07:52:22.57#ibcon#about to read 3, iclass 14, count 0 2006.217.07:52:22.59#ibcon#read 3, iclass 14, count 0 2006.217.07:52:22.59#ibcon#about to read 4, iclass 14, count 0 2006.217.07:52:22.59#ibcon#read 4, iclass 14, count 0 2006.217.07:52:22.59#ibcon#about to read 5, iclass 14, count 0 2006.217.07:52:22.59#ibcon#read 5, iclass 14, count 0 2006.217.07:52:22.59#ibcon#about to read 6, iclass 14, count 0 2006.217.07:52:22.59#ibcon#read 6, iclass 14, count 0 2006.217.07:52:22.59#ibcon#end of sib2, iclass 14, count 0 2006.217.07:52:22.59#ibcon#*mode == 0, iclass 14, count 0 2006.217.07:52:22.59#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.217.07:52:22.59#ibcon#[27=USB\r\n] 2006.217.07:52:22.59#ibcon#*before write, iclass 14, count 0 2006.217.07:52:22.59#ibcon#enter sib2, iclass 14, count 0 2006.217.07:52:22.59#ibcon#flushed, iclass 14, count 0 2006.217.07:52:22.59#ibcon#about to write, iclass 14, count 0 2006.217.07:52:22.59#ibcon#wrote, iclass 14, count 0 2006.217.07:52:22.59#ibcon#about to read 3, iclass 14, count 0 2006.217.07:52:22.62#ibcon#read 3, iclass 14, count 0 2006.217.07:52:22.62#ibcon#about to read 4, iclass 14, count 0 2006.217.07:52:22.62#ibcon#read 4, iclass 14, count 0 2006.217.07:52:22.62#ibcon#about to read 5, iclass 14, count 0 2006.217.07:52:22.62#ibcon#read 5, iclass 14, count 0 2006.217.07:52:22.62#ibcon#about to read 6, iclass 14, count 0 2006.217.07:52:22.62#ibcon#read 6, iclass 14, count 0 2006.217.07:52:22.62#ibcon#end of sib2, iclass 14, count 0 2006.217.07:52:22.62#ibcon#*after write, iclass 14, count 0 2006.217.07:52:22.62#ibcon#*before return 0, iclass 14, count 0 2006.217.07:52:22.62#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.217.07:52:22.62#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.217.07:52:22.62#ibcon#about to clear, iclass 14 cls_cnt 0 2006.217.07:52:22.62#ibcon#cleared, iclass 14 cls_cnt 0 2006.217.07:52:22.62$vc4f8/vabw=wide 2006.217.07:52:22.62#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.217.07:52:22.62#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.217.07:52:22.62#ibcon#ireg 8 cls_cnt 0 2006.217.07:52:22.62#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.217.07:52:22.62#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.217.07:52:22.62#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.217.07:52:22.62#ibcon#enter wrdev, iclass 16, count 0 2006.217.07:52:22.62#ibcon#first serial, iclass 16, count 0 2006.217.07:52:22.62#ibcon#enter sib2, iclass 16, count 0 2006.217.07:52:22.62#ibcon#flushed, iclass 16, count 0 2006.217.07:52:22.62#ibcon#about to write, iclass 16, count 0 2006.217.07:52:22.62#ibcon#wrote, iclass 16, count 0 2006.217.07:52:22.62#ibcon#about to read 3, iclass 16, count 0 2006.217.07:52:22.64#ibcon#read 3, iclass 16, count 0 2006.217.07:52:22.64#ibcon#about to read 4, iclass 16, count 0 2006.217.07:52:22.64#ibcon#read 4, iclass 16, count 0 2006.217.07:52:22.64#ibcon#about to read 5, iclass 16, count 0 2006.217.07:52:22.64#ibcon#read 5, iclass 16, count 0 2006.217.07:52:22.64#ibcon#about to read 6, iclass 16, count 0 2006.217.07:52:22.64#ibcon#read 6, iclass 16, count 0 2006.217.07:52:22.64#ibcon#end of sib2, iclass 16, count 0 2006.217.07:52:22.64#ibcon#*mode == 0, iclass 16, count 0 2006.217.07:52:22.64#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.217.07:52:22.64#ibcon#[25=BW32\r\n] 2006.217.07:52:22.64#ibcon#*before write, iclass 16, count 0 2006.217.07:52:22.64#ibcon#enter sib2, iclass 16, count 0 2006.217.07:52:22.64#ibcon#flushed, iclass 16, count 0 2006.217.07:52:22.64#ibcon#about to write, iclass 16, count 0 2006.217.07:52:22.64#ibcon#wrote, iclass 16, count 0 2006.217.07:52:22.64#ibcon#about to read 3, iclass 16, count 0 2006.217.07:52:22.67#ibcon#read 3, iclass 16, count 0 2006.217.07:52:22.67#ibcon#about to read 4, iclass 16, count 0 2006.217.07:52:22.67#ibcon#read 4, iclass 16, count 0 2006.217.07:52:22.67#ibcon#about to read 5, iclass 16, count 0 2006.217.07:52:22.67#ibcon#read 5, iclass 16, count 0 2006.217.07:52:22.67#ibcon#about to read 6, iclass 16, count 0 2006.217.07:52:22.67#ibcon#read 6, iclass 16, count 0 2006.217.07:52:22.67#ibcon#end of sib2, iclass 16, count 0 2006.217.07:52:22.67#ibcon#*after write, iclass 16, count 0 2006.217.07:52:22.67#ibcon#*before return 0, iclass 16, count 0 2006.217.07:52:22.67#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.217.07:52:22.67#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.217.07:52:22.67#ibcon#about to clear, iclass 16 cls_cnt 0 2006.217.07:52:22.67#ibcon#cleared, iclass 16 cls_cnt 0 2006.217.07:52:22.67$vc4f8/vbbw=wide 2006.217.07:52:22.67#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.217.07:52:22.67#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.217.07:52:22.67#ibcon#ireg 8 cls_cnt 0 2006.217.07:52:22.67#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.217.07:52:22.74#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.217.07:52:22.74#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.217.07:52:22.74#ibcon#enter wrdev, iclass 18, count 0 2006.217.07:52:22.74#ibcon#first serial, iclass 18, count 0 2006.217.07:52:22.74#ibcon#enter sib2, iclass 18, count 0 2006.217.07:52:22.74#ibcon#flushed, iclass 18, count 0 2006.217.07:52:22.74#ibcon#about to write, iclass 18, count 0 2006.217.07:52:22.74#ibcon#wrote, iclass 18, count 0 2006.217.07:52:22.74#ibcon#about to read 3, iclass 18, count 0 2006.217.07:52:22.76#ibcon#read 3, iclass 18, count 0 2006.217.07:52:22.76#ibcon#about to read 4, iclass 18, count 0 2006.217.07:52:22.76#ibcon#read 4, iclass 18, count 0 2006.217.07:52:22.76#ibcon#about to read 5, iclass 18, count 0 2006.217.07:52:22.76#ibcon#read 5, iclass 18, count 0 2006.217.07:52:22.76#ibcon#about to read 6, iclass 18, count 0 2006.217.07:52:22.76#ibcon#read 6, iclass 18, count 0 2006.217.07:52:22.76#ibcon#end of sib2, iclass 18, count 0 2006.217.07:52:22.76#ibcon#*mode == 0, iclass 18, count 0 2006.217.07:52:22.76#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.217.07:52:22.76#ibcon#[27=BW32\r\n] 2006.217.07:52:22.76#ibcon#*before write, iclass 18, count 0 2006.217.07:52:22.76#ibcon#enter sib2, iclass 18, count 0 2006.217.07:52:22.76#ibcon#flushed, iclass 18, count 0 2006.217.07:52:22.76#ibcon#about to write, iclass 18, count 0 2006.217.07:52:22.76#ibcon#wrote, iclass 18, count 0 2006.217.07:52:22.76#ibcon#about to read 3, iclass 18, count 0 2006.217.07:52:22.79#ibcon#read 3, iclass 18, count 0 2006.217.07:52:22.79#ibcon#about to read 4, iclass 18, count 0 2006.217.07:52:22.79#ibcon#read 4, iclass 18, count 0 2006.217.07:52:22.79#ibcon#about to read 5, iclass 18, count 0 2006.217.07:52:22.79#ibcon#read 5, iclass 18, count 0 2006.217.07:52:22.79#ibcon#about to read 6, iclass 18, count 0 2006.217.07:52:22.79#ibcon#read 6, iclass 18, count 0 2006.217.07:52:22.79#ibcon#end of sib2, iclass 18, count 0 2006.217.07:52:22.79#ibcon#*after write, iclass 18, count 0 2006.217.07:52:22.79#ibcon#*before return 0, iclass 18, count 0 2006.217.07:52:22.79#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.217.07:52:22.79#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.217.07:52:22.79#ibcon#about to clear, iclass 18 cls_cnt 0 2006.217.07:52:22.79#ibcon#cleared, iclass 18 cls_cnt 0 2006.217.07:52:22.79$4f8m12a/ifd4f 2006.217.07:52:22.79$ifd4f/lo= 2006.217.07:52:22.79$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.217.07:52:22.79$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.217.07:52:22.79$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.217.07:52:22.79$ifd4f/patch= 2006.217.07:52:22.79$ifd4f/patch=lo1,a1,a2,a3,a4 2006.217.07:52:22.79$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.217.07:52:22.79$ifd4f/patch=lo3,a5,a6,a7,a8 2006.217.07:52:22.79$4f8m12a/"form=m,16.000,1:2 2006.217.07:52:22.79$4f8m12a/"tpicd 2006.217.07:52:22.79$4f8m12a/echo=off 2006.217.07:52:22.79$4f8m12a/xlog=off 2006.217.07:52:22.79:!2006.217.07:52:50 2006.217.07:52:34.14#trakl#Source acquired 2006.217.07:52:35.14#flagr#flagr/antenna,acquired 2006.217.07:52:50.00:preob 2006.217.07:52:51.14/onsource/TRACKING 2006.217.07:52:51.14:!2006.217.07:53:00 2006.217.07:53:00.00:data_valid=on 2006.217.07:53:00.00:midob 2006.217.07:53:00.14/onsource/TRACKING 2006.217.07:53:00.14/wx/31.19,1008.6,64 2006.217.07:53:00.27/cable/+6.3860E-03 2006.217.07:53:01.36/va/01,05,usb,yes,31,33 2006.217.07:53:01.36/va/02,04,usb,yes,29,30 2006.217.07:53:01.36/va/03,04,usb,yes,27,28 2006.217.07:53:01.36/va/04,04,usb,yes,31,33 2006.217.07:53:01.36/va/05,07,usb,yes,32,34 2006.217.07:53:01.36/va/06,06,usb,yes,31,31 2006.217.07:53:01.36/va/07,06,usb,yes,32,32 2006.217.07:53:01.36/va/08,07,usb,yes,30,30 2006.217.07:53:01.59/valo/01,532.99,yes,locked 2006.217.07:53:01.59/valo/02,572.99,yes,locked 2006.217.07:53:01.59/valo/03,672.99,yes,locked 2006.217.07:53:01.59/valo/04,832.99,yes,locked 2006.217.07:53:01.59/valo/05,652.99,yes,locked 2006.217.07:53:01.59/valo/06,772.99,yes,locked 2006.217.07:53:01.59/valo/07,832.99,yes,locked 2006.217.07:53:01.59/valo/08,852.99,yes,locked 2006.217.07:53:02.68/vb/01,04,usb,yes,30,29 2006.217.07:53:02.68/vb/02,04,usb,yes,32,33 2006.217.07:53:02.68/vb/03,04,usb,yes,28,32 2006.217.07:53:02.68/vb/04,04,usb,yes,29,29 2006.217.07:53:02.68/vb/05,04,usb,yes,27,31 2006.217.07:53:02.68/vb/06,04,usb,yes,28,31 2006.217.07:53:02.68/vb/07,04,usb,yes,31,30 2006.217.07:53:02.68/vb/08,04,usb,yes,28,31 2006.217.07:53:02.92/vblo/01,632.99,yes,locked 2006.217.07:53:02.92/vblo/02,640.99,yes,locked 2006.217.07:53:02.92/vblo/03,656.99,yes,locked 2006.217.07:53:02.92/vblo/04,712.99,yes,locked 2006.217.07:53:02.92/vblo/05,744.99,yes,locked 2006.217.07:53:02.92/vblo/06,752.99,yes,locked 2006.217.07:53:02.92/vblo/07,734.99,yes,locked 2006.217.07:53:02.92/vblo/08,744.99,yes,locked 2006.217.07:53:03.07/vabw/8 2006.217.07:53:03.22/vbbw/8 2006.217.07:53:03.40/xfe/off,on,15.2 2006.217.07:53:03.81/ifatt/23,28,28,28 2006.217.07:53:04.07/fmout-gps/S +4.23E-07 2006.217.07:53:04.11:!2006.217.07:54:00 2006.217.07:54:00.00:data_valid=off 2006.217.07:54:00.01:postob 2006.217.07:54:00.08/cable/+6.3869E-03 2006.217.07:54:00.09/wx/31.16,1008.6,63 2006.217.07:54:01.07/fmout-gps/S +4.23E-07 2006.217.07:54:01.07:scan_name=217-0755,k06217,60 2006.217.07:54:01.08:source=3c418,203837.03,511912.7,2000.0,cw 2006.217.07:54:01.14#flagr#flagr/antenna,new-source 2006.217.07:54:02.14:checkk5 2006.217.07:54:02.52/chk_autoobs//k5ts1/ autoobs is running! 2006.217.07:54:02.89/chk_autoobs//k5ts2/ autoobs is running! 2006.217.07:54:03.26/chk_autoobs//k5ts3/ autoobs is running! 2006.217.07:54:03.64/chk_autoobs//k5ts4/ autoobs is running! 2006.217.07:54:04.00/chk_obsdata//k5ts1/T2170753??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:54:04.37/chk_obsdata//k5ts2/T2170753??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:54:04.76/chk_obsdata//k5ts3/T2170753??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:54:05.12/chk_obsdata//k5ts4/T2170753??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:54:05.81/k5log//k5ts1_log_newline 2006.217.07:54:06.51/k5log//k5ts2_log_newline 2006.217.07:54:07.20/k5log//k5ts3_log_newline 2006.217.07:54:07.89/k5log//k5ts4_log_newline 2006.217.07:54:07.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.217.07:54:07.91:4f8m12a=2 2006.217.07:54:07.91$4f8m12a/echo=on 2006.217.07:54:07.91$4f8m12a/pcalon 2006.217.07:54:07.91$pcalon/"no phase cal control is implemented here 2006.217.07:54:07.91$4f8m12a/"tpicd=stop 2006.217.07:54:07.91$4f8m12a/vc4f8 2006.217.07:54:07.91$vc4f8/valo=1,532.99 2006.217.07:54:07.92#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.217.07:54:07.92#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.217.07:54:07.92#ibcon#ireg 17 cls_cnt 0 2006.217.07:54:07.92#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.217.07:54:07.92#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.217.07:54:07.92#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.217.07:54:07.92#ibcon#enter wrdev, iclass 29, count 0 2006.217.07:54:07.92#ibcon#first serial, iclass 29, count 0 2006.217.07:54:07.92#ibcon#enter sib2, iclass 29, count 0 2006.217.07:54:07.92#ibcon#flushed, iclass 29, count 0 2006.217.07:54:07.92#ibcon#about to write, iclass 29, count 0 2006.217.07:54:07.92#ibcon#wrote, iclass 29, count 0 2006.217.07:54:07.92#ibcon#about to read 3, iclass 29, count 0 2006.217.07:54:07.96#ibcon#read 3, iclass 29, count 0 2006.217.07:54:07.96#ibcon#about to read 4, iclass 29, count 0 2006.217.07:54:07.96#ibcon#read 4, iclass 29, count 0 2006.217.07:54:07.96#ibcon#about to read 5, iclass 29, count 0 2006.217.07:54:07.96#ibcon#read 5, iclass 29, count 0 2006.217.07:54:07.96#ibcon#about to read 6, iclass 29, count 0 2006.217.07:54:07.96#ibcon#read 6, iclass 29, count 0 2006.217.07:54:07.96#ibcon#end of sib2, iclass 29, count 0 2006.217.07:54:07.96#ibcon#*mode == 0, iclass 29, count 0 2006.217.07:54:07.96#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.217.07:54:07.96#ibcon#[26=FRQ=01,532.99\r\n] 2006.217.07:54:07.96#ibcon#*before write, iclass 29, count 0 2006.217.07:54:07.96#ibcon#enter sib2, iclass 29, count 0 2006.217.07:54:07.96#ibcon#flushed, iclass 29, count 0 2006.217.07:54:07.96#ibcon#about to write, iclass 29, count 0 2006.217.07:54:07.96#ibcon#wrote, iclass 29, count 0 2006.217.07:54:07.96#ibcon#about to read 3, iclass 29, count 0 2006.217.07:54:08.00#ibcon#read 3, iclass 29, count 0 2006.217.07:54:08.00#ibcon#about to read 4, iclass 29, count 0 2006.217.07:54:08.00#ibcon#read 4, iclass 29, count 0 2006.217.07:54:08.00#ibcon#about to read 5, iclass 29, count 0 2006.217.07:54:08.00#ibcon#read 5, iclass 29, count 0 2006.217.07:54:08.00#ibcon#about to read 6, iclass 29, count 0 2006.217.07:54:08.00#ibcon#read 6, iclass 29, count 0 2006.217.07:54:08.00#ibcon#end of sib2, iclass 29, count 0 2006.217.07:54:08.00#ibcon#*after write, iclass 29, count 0 2006.217.07:54:08.00#ibcon#*before return 0, iclass 29, count 0 2006.217.07:54:08.00#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.217.07:54:08.00#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.217.07:54:08.00#ibcon#about to clear, iclass 29 cls_cnt 0 2006.217.07:54:08.00#ibcon#cleared, iclass 29 cls_cnt 0 2006.217.07:54:08.00$vc4f8/va=1,5 2006.217.07:54:08.00#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.217.07:54:08.00#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.217.07:54:08.00#ibcon#ireg 11 cls_cnt 2 2006.217.07:54:08.00#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.217.07:54:08.00#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.217.07:54:08.00#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.217.07:54:08.00#ibcon#enter wrdev, iclass 31, count 2 2006.217.07:54:08.00#ibcon#first serial, iclass 31, count 2 2006.217.07:54:08.00#ibcon#enter sib2, iclass 31, count 2 2006.217.07:54:08.00#ibcon#flushed, iclass 31, count 2 2006.217.07:54:08.00#ibcon#about to write, iclass 31, count 2 2006.217.07:54:08.00#ibcon#wrote, iclass 31, count 2 2006.217.07:54:08.00#ibcon#about to read 3, iclass 31, count 2 2006.217.07:54:08.02#ibcon#read 3, iclass 31, count 2 2006.217.07:54:08.02#ibcon#about to read 4, iclass 31, count 2 2006.217.07:54:08.02#ibcon#read 4, iclass 31, count 2 2006.217.07:54:08.02#ibcon#about to read 5, iclass 31, count 2 2006.217.07:54:08.02#ibcon#read 5, iclass 31, count 2 2006.217.07:54:08.02#ibcon#about to read 6, iclass 31, count 2 2006.217.07:54:08.02#ibcon#read 6, iclass 31, count 2 2006.217.07:54:08.02#ibcon#end of sib2, iclass 31, count 2 2006.217.07:54:08.02#ibcon#*mode == 0, iclass 31, count 2 2006.217.07:54:08.02#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.217.07:54:08.02#ibcon#[25=AT01-05\r\n] 2006.217.07:54:08.02#ibcon#*before write, iclass 31, count 2 2006.217.07:54:08.02#ibcon#enter sib2, iclass 31, count 2 2006.217.07:54:08.02#ibcon#flushed, iclass 31, count 2 2006.217.07:54:08.02#ibcon#about to write, iclass 31, count 2 2006.217.07:54:08.02#ibcon#wrote, iclass 31, count 2 2006.217.07:54:08.02#ibcon#about to read 3, iclass 31, count 2 2006.217.07:54:08.05#ibcon#read 3, iclass 31, count 2 2006.217.07:54:08.05#ibcon#about to read 4, iclass 31, count 2 2006.217.07:54:08.05#ibcon#read 4, iclass 31, count 2 2006.217.07:54:08.05#ibcon#about to read 5, iclass 31, count 2 2006.217.07:54:08.05#ibcon#read 5, iclass 31, count 2 2006.217.07:54:08.05#ibcon#about to read 6, iclass 31, count 2 2006.217.07:54:08.05#ibcon#read 6, iclass 31, count 2 2006.217.07:54:08.05#ibcon#end of sib2, iclass 31, count 2 2006.217.07:54:08.05#ibcon#*after write, iclass 31, count 2 2006.217.07:54:08.05#ibcon#*before return 0, iclass 31, count 2 2006.217.07:54:08.05#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.217.07:54:08.05#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.217.07:54:08.05#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.217.07:54:08.05#ibcon#ireg 7 cls_cnt 0 2006.217.07:54:08.05#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.217.07:54:08.17#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.217.07:54:08.17#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.217.07:54:08.17#ibcon#enter wrdev, iclass 31, count 0 2006.217.07:54:08.17#ibcon#first serial, iclass 31, count 0 2006.217.07:54:08.17#ibcon#enter sib2, iclass 31, count 0 2006.217.07:54:08.17#ibcon#flushed, iclass 31, count 0 2006.217.07:54:08.17#ibcon#about to write, iclass 31, count 0 2006.217.07:54:08.17#ibcon#wrote, iclass 31, count 0 2006.217.07:54:08.17#ibcon#about to read 3, iclass 31, count 0 2006.217.07:54:08.19#ibcon#read 3, iclass 31, count 0 2006.217.07:54:08.19#ibcon#about to read 4, iclass 31, count 0 2006.217.07:54:08.19#ibcon#read 4, iclass 31, count 0 2006.217.07:54:08.19#ibcon#about to read 5, iclass 31, count 0 2006.217.07:54:08.19#ibcon#read 5, iclass 31, count 0 2006.217.07:54:08.19#ibcon#about to read 6, iclass 31, count 0 2006.217.07:54:08.19#ibcon#read 6, iclass 31, count 0 2006.217.07:54:08.19#ibcon#end of sib2, iclass 31, count 0 2006.217.07:54:08.19#ibcon#*mode == 0, iclass 31, count 0 2006.217.07:54:08.19#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.217.07:54:08.19#ibcon#[25=USB\r\n] 2006.217.07:54:08.19#ibcon#*before write, iclass 31, count 0 2006.217.07:54:08.19#ibcon#enter sib2, iclass 31, count 0 2006.217.07:54:08.19#ibcon#flushed, iclass 31, count 0 2006.217.07:54:08.19#ibcon#about to write, iclass 31, count 0 2006.217.07:54:08.19#ibcon#wrote, iclass 31, count 0 2006.217.07:54:08.19#ibcon#about to read 3, iclass 31, count 0 2006.217.07:54:08.22#ibcon#read 3, iclass 31, count 0 2006.217.07:54:08.22#ibcon#about to read 4, iclass 31, count 0 2006.217.07:54:08.22#ibcon#read 4, iclass 31, count 0 2006.217.07:54:08.22#ibcon#about to read 5, iclass 31, count 0 2006.217.07:54:08.22#ibcon#read 5, iclass 31, count 0 2006.217.07:54:08.22#ibcon#about to read 6, iclass 31, count 0 2006.217.07:54:08.22#ibcon#read 6, iclass 31, count 0 2006.217.07:54:08.22#ibcon#end of sib2, iclass 31, count 0 2006.217.07:54:08.22#ibcon#*after write, iclass 31, count 0 2006.217.07:54:08.22#ibcon#*before return 0, iclass 31, count 0 2006.217.07:54:08.22#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.217.07:54:08.22#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.217.07:54:08.22#ibcon#about to clear, iclass 31 cls_cnt 0 2006.217.07:54:08.22#ibcon#cleared, iclass 31 cls_cnt 0 2006.217.07:54:08.22$vc4f8/valo=2,572.99 2006.217.07:54:08.22#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.217.07:54:08.22#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.217.07:54:08.22#ibcon#ireg 17 cls_cnt 0 2006.217.07:54:08.22#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.217.07:54:08.22#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.217.07:54:08.22#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.217.07:54:08.22#ibcon#enter wrdev, iclass 33, count 0 2006.217.07:54:08.22#ibcon#first serial, iclass 33, count 0 2006.217.07:54:08.22#ibcon#enter sib2, iclass 33, count 0 2006.217.07:54:08.22#ibcon#flushed, iclass 33, count 0 2006.217.07:54:08.22#ibcon#about to write, iclass 33, count 0 2006.217.07:54:08.22#ibcon#wrote, iclass 33, count 0 2006.217.07:54:08.22#ibcon#about to read 3, iclass 33, count 0 2006.217.07:54:08.24#ibcon#read 3, iclass 33, count 0 2006.217.07:54:08.24#ibcon#about to read 4, iclass 33, count 0 2006.217.07:54:08.24#ibcon#read 4, iclass 33, count 0 2006.217.07:54:08.24#ibcon#about to read 5, iclass 33, count 0 2006.217.07:54:08.24#ibcon#read 5, iclass 33, count 0 2006.217.07:54:08.24#ibcon#about to read 6, iclass 33, count 0 2006.217.07:54:08.24#ibcon#read 6, iclass 33, count 0 2006.217.07:54:08.24#ibcon#end of sib2, iclass 33, count 0 2006.217.07:54:08.24#ibcon#*mode == 0, iclass 33, count 0 2006.217.07:54:08.24#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.217.07:54:08.24#ibcon#[26=FRQ=02,572.99\r\n] 2006.217.07:54:08.24#ibcon#*before write, iclass 33, count 0 2006.217.07:54:08.24#ibcon#enter sib2, iclass 33, count 0 2006.217.07:54:08.24#ibcon#flushed, iclass 33, count 0 2006.217.07:54:08.24#ibcon#about to write, iclass 33, count 0 2006.217.07:54:08.24#ibcon#wrote, iclass 33, count 0 2006.217.07:54:08.24#ibcon#about to read 3, iclass 33, count 0 2006.217.07:54:08.28#ibcon#read 3, iclass 33, count 0 2006.217.07:54:08.28#ibcon#about to read 4, iclass 33, count 0 2006.217.07:54:08.28#ibcon#read 4, iclass 33, count 0 2006.217.07:54:08.28#ibcon#about to read 5, iclass 33, count 0 2006.217.07:54:08.28#ibcon#read 5, iclass 33, count 0 2006.217.07:54:08.28#ibcon#about to read 6, iclass 33, count 0 2006.217.07:54:08.28#ibcon#read 6, iclass 33, count 0 2006.217.07:54:08.28#ibcon#end of sib2, iclass 33, count 0 2006.217.07:54:08.28#ibcon#*after write, iclass 33, count 0 2006.217.07:54:08.28#ibcon#*before return 0, iclass 33, count 0 2006.217.07:54:08.28#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.217.07:54:08.28#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.217.07:54:08.28#ibcon#about to clear, iclass 33 cls_cnt 0 2006.217.07:54:08.28#ibcon#cleared, iclass 33 cls_cnt 0 2006.217.07:54:08.28$vc4f8/va=2,4 2006.217.07:54:08.28#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.217.07:54:08.28#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.217.07:54:08.28#ibcon#ireg 11 cls_cnt 2 2006.217.07:54:08.28#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.217.07:54:08.34#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.217.07:54:08.34#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.217.07:54:08.34#ibcon#enter wrdev, iclass 35, count 2 2006.217.07:54:08.34#ibcon#first serial, iclass 35, count 2 2006.217.07:54:08.34#ibcon#enter sib2, iclass 35, count 2 2006.217.07:54:08.34#ibcon#flushed, iclass 35, count 2 2006.217.07:54:08.34#ibcon#about to write, iclass 35, count 2 2006.217.07:54:08.34#ibcon#wrote, iclass 35, count 2 2006.217.07:54:08.34#ibcon#about to read 3, iclass 35, count 2 2006.217.07:54:08.36#ibcon#read 3, iclass 35, count 2 2006.217.07:54:08.36#ibcon#about to read 4, iclass 35, count 2 2006.217.07:54:08.36#ibcon#read 4, iclass 35, count 2 2006.217.07:54:08.36#ibcon#about to read 5, iclass 35, count 2 2006.217.07:54:08.36#ibcon#read 5, iclass 35, count 2 2006.217.07:54:08.36#ibcon#about to read 6, iclass 35, count 2 2006.217.07:54:08.36#ibcon#read 6, iclass 35, count 2 2006.217.07:54:08.36#ibcon#end of sib2, iclass 35, count 2 2006.217.07:54:08.36#ibcon#*mode == 0, iclass 35, count 2 2006.217.07:54:08.36#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.217.07:54:08.36#ibcon#[25=AT02-04\r\n] 2006.217.07:54:08.36#ibcon#*before write, iclass 35, count 2 2006.217.07:54:08.36#ibcon#enter sib2, iclass 35, count 2 2006.217.07:54:08.36#ibcon#flushed, iclass 35, count 2 2006.217.07:54:08.36#ibcon#about to write, iclass 35, count 2 2006.217.07:54:08.36#ibcon#wrote, iclass 35, count 2 2006.217.07:54:08.36#ibcon#about to read 3, iclass 35, count 2 2006.217.07:54:08.39#ibcon#read 3, iclass 35, count 2 2006.217.07:54:08.39#ibcon#about to read 4, iclass 35, count 2 2006.217.07:54:08.39#ibcon#read 4, iclass 35, count 2 2006.217.07:54:08.39#ibcon#about to read 5, iclass 35, count 2 2006.217.07:54:08.39#ibcon#read 5, iclass 35, count 2 2006.217.07:54:08.39#ibcon#about to read 6, iclass 35, count 2 2006.217.07:54:08.39#ibcon#read 6, iclass 35, count 2 2006.217.07:54:08.39#ibcon#end of sib2, iclass 35, count 2 2006.217.07:54:08.39#ibcon#*after write, iclass 35, count 2 2006.217.07:54:08.39#ibcon#*before return 0, iclass 35, count 2 2006.217.07:54:08.39#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.217.07:54:08.39#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.217.07:54:08.39#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.217.07:54:08.39#ibcon#ireg 7 cls_cnt 0 2006.217.07:54:08.39#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.217.07:54:08.51#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.217.07:54:08.51#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.217.07:54:08.51#ibcon#enter wrdev, iclass 35, count 0 2006.217.07:54:08.51#ibcon#first serial, iclass 35, count 0 2006.217.07:54:08.51#ibcon#enter sib2, iclass 35, count 0 2006.217.07:54:08.51#ibcon#flushed, iclass 35, count 0 2006.217.07:54:08.51#ibcon#about to write, iclass 35, count 0 2006.217.07:54:08.51#ibcon#wrote, iclass 35, count 0 2006.217.07:54:08.51#ibcon#about to read 3, iclass 35, count 0 2006.217.07:54:08.53#ibcon#read 3, iclass 35, count 0 2006.217.07:54:08.53#ibcon#about to read 4, iclass 35, count 0 2006.217.07:54:08.53#ibcon#read 4, iclass 35, count 0 2006.217.07:54:08.53#ibcon#about to read 5, iclass 35, count 0 2006.217.07:54:08.53#ibcon#read 5, iclass 35, count 0 2006.217.07:54:08.53#ibcon#about to read 6, iclass 35, count 0 2006.217.07:54:08.53#ibcon#read 6, iclass 35, count 0 2006.217.07:54:08.53#ibcon#end of sib2, iclass 35, count 0 2006.217.07:54:08.53#ibcon#*mode == 0, iclass 35, count 0 2006.217.07:54:08.53#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.217.07:54:08.53#ibcon#[25=USB\r\n] 2006.217.07:54:08.53#ibcon#*before write, iclass 35, count 0 2006.217.07:54:08.53#ibcon#enter sib2, iclass 35, count 0 2006.217.07:54:08.53#ibcon#flushed, iclass 35, count 0 2006.217.07:54:08.53#ibcon#about to write, iclass 35, count 0 2006.217.07:54:08.53#ibcon#wrote, iclass 35, count 0 2006.217.07:54:08.53#ibcon#about to read 3, iclass 35, count 0 2006.217.07:54:08.56#ibcon#read 3, iclass 35, count 0 2006.217.07:54:08.56#ibcon#about to read 4, iclass 35, count 0 2006.217.07:54:08.56#ibcon#read 4, iclass 35, count 0 2006.217.07:54:08.56#ibcon#about to read 5, iclass 35, count 0 2006.217.07:54:08.56#ibcon#read 5, iclass 35, count 0 2006.217.07:54:08.56#ibcon#about to read 6, iclass 35, count 0 2006.217.07:54:08.56#ibcon#read 6, iclass 35, count 0 2006.217.07:54:08.56#ibcon#end of sib2, iclass 35, count 0 2006.217.07:54:08.56#ibcon#*after write, iclass 35, count 0 2006.217.07:54:08.56#ibcon#*before return 0, iclass 35, count 0 2006.217.07:54:08.56#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.217.07:54:08.56#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.217.07:54:08.56#ibcon#about to clear, iclass 35 cls_cnt 0 2006.217.07:54:08.56#ibcon#cleared, iclass 35 cls_cnt 0 2006.217.07:54:08.56$vc4f8/valo=3,672.99 2006.217.07:54:08.56#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.217.07:54:08.56#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.217.07:54:08.56#ibcon#ireg 17 cls_cnt 0 2006.217.07:54:08.56#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.217.07:54:08.56#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.217.07:54:08.56#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.217.07:54:08.56#ibcon#enter wrdev, iclass 37, count 0 2006.217.07:54:08.56#ibcon#first serial, iclass 37, count 0 2006.217.07:54:08.56#ibcon#enter sib2, iclass 37, count 0 2006.217.07:54:08.56#ibcon#flushed, iclass 37, count 0 2006.217.07:54:08.56#ibcon#about to write, iclass 37, count 0 2006.217.07:54:08.56#ibcon#wrote, iclass 37, count 0 2006.217.07:54:08.56#ibcon#about to read 3, iclass 37, count 0 2006.217.07:54:08.58#ibcon#read 3, iclass 37, count 0 2006.217.07:54:08.58#ibcon#about to read 4, iclass 37, count 0 2006.217.07:54:08.58#ibcon#read 4, iclass 37, count 0 2006.217.07:54:08.58#ibcon#about to read 5, iclass 37, count 0 2006.217.07:54:08.58#ibcon#read 5, iclass 37, count 0 2006.217.07:54:08.58#ibcon#about to read 6, iclass 37, count 0 2006.217.07:54:08.58#ibcon#read 6, iclass 37, count 0 2006.217.07:54:08.58#ibcon#end of sib2, iclass 37, count 0 2006.217.07:54:08.58#ibcon#*mode == 0, iclass 37, count 0 2006.217.07:54:08.58#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.217.07:54:08.58#ibcon#[26=FRQ=03,672.99\r\n] 2006.217.07:54:08.58#ibcon#*before write, iclass 37, count 0 2006.217.07:54:08.58#ibcon#enter sib2, iclass 37, count 0 2006.217.07:54:08.58#ibcon#flushed, iclass 37, count 0 2006.217.07:54:08.58#ibcon#about to write, iclass 37, count 0 2006.217.07:54:08.58#ibcon#wrote, iclass 37, count 0 2006.217.07:54:08.58#ibcon#about to read 3, iclass 37, count 0 2006.217.07:54:08.62#ibcon#read 3, iclass 37, count 0 2006.217.07:54:08.62#ibcon#about to read 4, iclass 37, count 0 2006.217.07:54:08.62#ibcon#read 4, iclass 37, count 0 2006.217.07:54:08.62#ibcon#about to read 5, iclass 37, count 0 2006.217.07:54:08.62#ibcon#read 5, iclass 37, count 0 2006.217.07:54:08.62#ibcon#about to read 6, iclass 37, count 0 2006.217.07:54:08.62#ibcon#read 6, iclass 37, count 0 2006.217.07:54:08.62#ibcon#end of sib2, iclass 37, count 0 2006.217.07:54:08.62#ibcon#*after write, iclass 37, count 0 2006.217.07:54:08.62#ibcon#*before return 0, iclass 37, count 0 2006.217.07:54:08.62#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.217.07:54:08.62#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.217.07:54:08.62#ibcon#about to clear, iclass 37 cls_cnt 0 2006.217.07:54:08.62#ibcon#cleared, iclass 37 cls_cnt 0 2006.217.07:54:08.63$vc4f8/va=3,4 2006.217.07:54:08.63#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.217.07:54:08.63#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.217.07:54:08.63#ibcon#ireg 11 cls_cnt 2 2006.217.07:54:08.63#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.217.07:54:08.67#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.217.07:54:08.67#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.217.07:54:08.67#ibcon#enter wrdev, iclass 39, count 2 2006.217.07:54:08.67#ibcon#first serial, iclass 39, count 2 2006.217.07:54:08.67#ibcon#enter sib2, iclass 39, count 2 2006.217.07:54:08.67#ibcon#flushed, iclass 39, count 2 2006.217.07:54:08.67#ibcon#about to write, iclass 39, count 2 2006.217.07:54:08.67#ibcon#wrote, iclass 39, count 2 2006.217.07:54:08.67#ibcon#about to read 3, iclass 39, count 2 2006.217.07:54:08.70#ibcon#read 3, iclass 39, count 2 2006.217.07:54:08.70#ibcon#about to read 4, iclass 39, count 2 2006.217.07:54:08.70#ibcon#read 4, iclass 39, count 2 2006.217.07:54:08.70#ibcon#about to read 5, iclass 39, count 2 2006.217.07:54:08.70#ibcon#read 5, iclass 39, count 2 2006.217.07:54:08.70#ibcon#about to read 6, iclass 39, count 2 2006.217.07:54:08.70#ibcon#read 6, iclass 39, count 2 2006.217.07:54:08.70#ibcon#end of sib2, iclass 39, count 2 2006.217.07:54:08.70#ibcon#*mode == 0, iclass 39, count 2 2006.217.07:54:08.70#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.217.07:54:08.70#ibcon#[25=AT03-04\r\n] 2006.217.07:54:08.70#ibcon#*before write, iclass 39, count 2 2006.217.07:54:08.70#ibcon#enter sib2, iclass 39, count 2 2006.217.07:54:08.70#ibcon#flushed, iclass 39, count 2 2006.217.07:54:08.70#ibcon#about to write, iclass 39, count 2 2006.217.07:54:08.70#ibcon#wrote, iclass 39, count 2 2006.217.07:54:08.70#ibcon#about to read 3, iclass 39, count 2 2006.217.07:54:08.73#ibcon#read 3, iclass 39, count 2 2006.217.07:54:08.73#ibcon#about to read 4, iclass 39, count 2 2006.217.07:54:08.73#ibcon#read 4, iclass 39, count 2 2006.217.07:54:08.73#ibcon#about to read 5, iclass 39, count 2 2006.217.07:54:08.73#ibcon#read 5, iclass 39, count 2 2006.217.07:54:08.73#ibcon#about to read 6, iclass 39, count 2 2006.217.07:54:08.73#ibcon#read 6, iclass 39, count 2 2006.217.07:54:08.73#ibcon#end of sib2, iclass 39, count 2 2006.217.07:54:08.73#ibcon#*after write, iclass 39, count 2 2006.217.07:54:08.73#ibcon#*before return 0, iclass 39, count 2 2006.217.07:54:08.73#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.217.07:54:08.73#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.217.07:54:08.73#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.217.07:54:08.73#ibcon#ireg 7 cls_cnt 0 2006.217.07:54:08.73#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.217.07:54:08.85#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.217.07:54:08.85#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.217.07:54:08.85#ibcon#enter wrdev, iclass 39, count 0 2006.217.07:54:08.85#ibcon#first serial, iclass 39, count 0 2006.217.07:54:08.85#ibcon#enter sib2, iclass 39, count 0 2006.217.07:54:08.85#ibcon#flushed, iclass 39, count 0 2006.217.07:54:08.85#ibcon#about to write, iclass 39, count 0 2006.217.07:54:08.85#ibcon#wrote, iclass 39, count 0 2006.217.07:54:08.85#ibcon#about to read 3, iclass 39, count 0 2006.217.07:54:08.87#ibcon#read 3, iclass 39, count 0 2006.217.07:54:08.87#ibcon#about to read 4, iclass 39, count 0 2006.217.07:54:08.87#ibcon#read 4, iclass 39, count 0 2006.217.07:54:08.87#ibcon#about to read 5, iclass 39, count 0 2006.217.07:54:08.87#ibcon#read 5, iclass 39, count 0 2006.217.07:54:08.87#ibcon#about to read 6, iclass 39, count 0 2006.217.07:54:08.87#ibcon#read 6, iclass 39, count 0 2006.217.07:54:08.87#ibcon#end of sib2, iclass 39, count 0 2006.217.07:54:08.87#ibcon#*mode == 0, iclass 39, count 0 2006.217.07:54:08.87#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.217.07:54:08.87#ibcon#[25=USB\r\n] 2006.217.07:54:08.87#ibcon#*before write, iclass 39, count 0 2006.217.07:54:08.87#ibcon#enter sib2, iclass 39, count 0 2006.217.07:54:08.87#ibcon#flushed, iclass 39, count 0 2006.217.07:54:08.87#ibcon#about to write, iclass 39, count 0 2006.217.07:54:08.87#ibcon#wrote, iclass 39, count 0 2006.217.07:54:08.87#ibcon#about to read 3, iclass 39, count 0 2006.217.07:54:08.90#ibcon#read 3, iclass 39, count 0 2006.217.07:54:08.90#ibcon#about to read 4, iclass 39, count 0 2006.217.07:54:08.90#ibcon#read 4, iclass 39, count 0 2006.217.07:54:08.90#ibcon#about to read 5, iclass 39, count 0 2006.217.07:54:08.90#ibcon#read 5, iclass 39, count 0 2006.217.07:54:08.90#ibcon#about to read 6, iclass 39, count 0 2006.217.07:54:08.90#ibcon#read 6, iclass 39, count 0 2006.217.07:54:08.90#ibcon#end of sib2, iclass 39, count 0 2006.217.07:54:08.90#ibcon#*after write, iclass 39, count 0 2006.217.07:54:08.90#ibcon#*before return 0, iclass 39, count 0 2006.217.07:54:08.90#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.217.07:54:08.90#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.217.07:54:08.90#ibcon#about to clear, iclass 39 cls_cnt 0 2006.217.07:54:08.90#ibcon#cleared, iclass 39 cls_cnt 0 2006.217.07:54:08.90$vc4f8/valo=4,832.99 2006.217.07:54:08.90#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.217.07:54:08.90#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.217.07:54:08.90#ibcon#ireg 17 cls_cnt 0 2006.217.07:54:08.90#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.217.07:54:08.90#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.217.07:54:08.90#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.217.07:54:08.90#ibcon#enter wrdev, iclass 3, count 0 2006.217.07:54:08.90#ibcon#first serial, iclass 3, count 0 2006.217.07:54:08.90#ibcon#enter sib2, iclass 3, count 0 2006.217.07:54:08.90#ibcon#flushed, iclass 3, count 0 2006.217.07:54:08.90#ibcon#about to write, iclass 3, count 0 2006.217.07:54:08.90#ibcon#wrote, iclass 3, count 0 2006.217.07:54:08.90#ibcon#about to read 3, iclass 3, count 0 2006.217.07:54:08.92#ibcon#read 3, iclass 3, count 0 2006.217.07:54:08.92#ibcon#about to read 4, iclass 3, count 0 2006.217.07:54:08.92#ibcon#read 4, iclass 3, count 0 2006.217.07:54:08.92#ibcon#about to read 5, iclass 3, count 0 2006.217.07:54:08.92#ibcon#read 5, iclass 3, count 0 2006.217.07:54:08.92#ibcon#about to read 6, iclass 3, count 0 2006.217.07:54:08.92#ibcon#read 6, iclass 3, count 0 2006.217.07:54:08.92#ibcon#end of sib2, iclass 3, count 0 2006.217.07:54:08.92#ibcon#*mode == 0, iclass 3, count 0 2006.217.07:54:08.92#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.217.07:54:08.92#ibcon#[26=FRQ=04,832.99\r\n] 2006.217.07:54:08.92#ibcon#*before write, iclass 3, count 0 2006.217.07:54:08.92#ibcon#enter sib2, iclass 3, count 0 2006.217.07:54:08.92#ibcon#flushed, iclass 3, count 0 2006.217.07:54:08.92#ibcon#about to write, iclass 3, count 0 2006.217.07:54:08.92#ibcon#wrote, iclass 3, count 0 2006.217.07:54:08.92#ibcon#about to read 3, iclass 3, count 0 2006.217.07:54:08.96#ibcon#read 3, iclass 3, count 0 2006.217.07:54:08.96#ibcon#about to read 4, iclass 3, count 0 2006.217.07:54:08.96#ibcon#read 4, iclass 3, count 0 2006.217.07:54:08.96#ibcon#about to read 5, iclass 3, count 0 2006.217.07:54:08.96#ibcon#read 5, iclass 3, count 0 2006.217.07:54:08.96#ibcon#about to read 6, iclass 3, count 0 2006.217.07:54:08.96#ibcon#read 6, iclass 3, count 0 2006.217.07:54:08.96#ibcon#end of sib2, iclass 3, count 0 2006.217.07:54:08.96#ibcon#*after write, iclass 3, count 0 2006.217.07:54:08.96#ibcon#*before return 0, iclass 3, count 0 2006.217.07:54:08.96#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.217.07:54:08.96#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.217.07:54:08.96#ibcon#about to clear, iclass 3 cls_cnt 0 2006.217.07:54:08.96#ibcon#cleared, iclass 3 cls_cnt 0 2006.217.07:54:08.96$vc4f8/va=4,4 2006.217.07:54:08.96#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.217.07:54:08.96#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.217.07:54:08.96#ibcon#ireg 11 cls_cnt 2 2006.217.07:54:08.96#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.217.07:54:09.02#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.217.07:54:09.02#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.217.07:54:09.02#ibcon#enter wrdev, iclass 5, count 2 2006.217.07:54:09.02#ibcon#first serial, iclass 5, count 2 2006.217.07:54:09.02#ibcon#enter sib2, iclass 5, count 2 2006.217.07:54:09.02#ibcon#flushed, iclass 5, count 2 2006.217.07:54:09.02#ibcon#about to write, iclass 5, count 2 2006.217.07:54:09.02#ibcon#wrote, iclass 5, count 2 2006.217.07:54:09.02#ibcon#about to read 3, iclass 5, count 2 2006.217.07:54:09.04#ibcon#read 3, iclass 5, count 2 2006.217.07:54:09.04#ibcon#about to read 4, iclass 5, count 2 2006.217.07:54:09.04#ibcon#read 4, iclass 5, count 2 2006.217.07:54:09.04#ibcon#about to read 5, iclass 5, count 2 2006.217.07:54:09.04#ibcon#read 5, iclass 5, count 2 2006.217.07:54:09.04#ibcon#about to read 6, iclass 5, count 2 2006.217.07:54:09.04#ibcon#read 6, iclass 5, count 2 2006.217.07:54:09.04#ibcon#end of sib2, iclass 5, count 2 2006.217.07:54:09.04#ibcon#*mode == 0, iclass 5, count 2 2006.217.07:54:09.04#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.217.07:54:09.04#ibcon#[25=AT04-04\r\n] 2006.217.07:54:09.04#ibcon#*before write, iclass 5, count 2 2006.217.07:54:09.04#ibcon#enter sib2, iclass 5, count 2 2006.217.07:54:09.04#ibcon#flushed, iclass 5, count 2 2006.217.07:54:09.04#ibcon#about to write, iclass 5, count 2 2006.217.07:54:09.04#ibcon#wrote, iclass 5, count 2 2006.217.07:54:09.04#ibcon#about to read 3, iclass 5, count 2 2006.217.07:54:09.07#ibcon#read 3, iclass 5, count 2 2006.217.07:54:09.07#ibcon#about to read 4, iclass 5, count 2 2006.217.07:54:09.07#ibcon#read 4, iclass 5, count 2 2006.217.07:54:09.07#ibcon#about to read 5, iclass 5, count 2 2006.217.07:54:09.07#ibcon#read 5, iclass 5, count 2 2006.217.07:54:09.07#ibcon#about to read 6, iclass 5, count 2 2006.217.07:54:09.07#ibcon#read 6, iclass 5, count 2 2006.217.07:54:09.07#ibcon#end of sib2, iclass 5, count 2 2006.217.07:54:09.07#ibcon#*after write, iclass 5, count 2 2006.217.07:54:09.07#ibcon#*before return 0, iclass 5, count 2 2006.217.07:54:09.07#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.217.07:54:09.07#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.217.07:54:09.07#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.217.07:54:09.07#ibcon#ireg 7 cls_cnt 0 2006.217.07:54:09.07#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.217.07:54:09.19#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.217.07:54:09.19#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.217.07:54:09.19#ibcon#enter wrdev, iclass 5, count 0 2006.217.07:54:09.19#ibcon#first serial, iclass 5, count 0 2006.217.07:54:09.19#ibcon#enter sib2, iclass 5, count 0 2006.217.07:54:09.19#ibcon#flushed, iclass 5, count 0 2006.217.07:54:09.19#ibcon#about to write, iclass 5, count 0 2006.217.07:54:09.19#ibcon#wrote, iclass 5, count 0 2006.217.07:54:09.19#ibcon#about to read 3, iclass 5, count 0 2006.217.07:54:09.21#ibcon#read 3, iclass 5, count 0 2006.217.07:54:09.21#ibcon#about to read 4, iclass 5, count 0 2006.217.07:54:09.21#ibcon#read 4, iclass 5, count 0 2006.217.07:54:09.21#ibcon#about to read 5, iclass 5, count 0 2006.217.07:54:09.21#ibcon#read 5, iclass 5, count 0 2006.217.07:54:09.21#ibcon#about to read 6, iclass 5, count 0 2006.217.07:54:09.21#ibcon#read 6, iclass 5, count 0 2006.217.07:54:09.21#ibcon#end of sib2, iclass 5, count 0 2006.217.07:54:09.21#ibcon#*mode == 0, iclass 5, count 0 2006.217.07:54:09.21#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.217.07:54:09.21#ibcon#[25=USB\r\n] 2006.217.07:54:09.21#ibcon#*before write, iclass 5, count 0 2006.217.07:54:09.21#ibcon#enter sib2, iclass 5, count 0 2006.217.07:54:09.21#ibcon#flushed, iclass 5, count 0 2006.217.07:54:09.21#ibcon#about to write, iclass 5, count 0 2006.217.07:54:09.21#ibcon#wrote, iclass 5, count 0 2006.217.07:54:09.21#ibcon#about to read 3, iclass 5, count 0 2006.217.07:54:09.24#ibcon#read 3, iclass 5, count 0 2006.217.07:54:09.24#ibcon#about to read 4, iclass 5, count 0 2006.217.07:54:09.24#ibcon#read 4, iclass 5, count 0 2006.217.07:54:09.24#ibcon#about to read 5, iclass 5, count 0 2006.217.07:54:09.24#ibcon#read 5, iclass 5, count 0 2006.217.07:54:09.24#ibcon#about to read 6, iclass 5, count 0 2006.217.07:54:09.24#ibcon#read 6, iclass 5, count 0 2006.217.07:54:09.24#ibcon#end of sib2, iclass 5, count 0 2006.217.07:54:09.24#ibcon#*after write, iclass 5, count 0 2006.217.07:54:09.24#ibcon#*before return 0, iclass 5, count 0 2006.217.07:54:09.24#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.217.07:54:09.24#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.217.07:54:09.24#ibcon#about to clear, iclass 5 cls_cnt 0 2006.217.07:54:09.24#ibcon#cleared, iclass 5 cls_cnt 0 2006.217.07:54:09.24$vc4f8/valo=5,652.99 2006.217.07:54:09.24#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.217.07:54:09.24#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.217.07:54:09.24#ibcon#ireg 17 cls_cnt 0 2006.217.07:54:09.24#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.217.07:54:09.24#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.217.07:54:09.24#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.217.07:54:09.24#ibcon#enter wrdev, iclass 7, count 0 2006.217.07:54:09.24#ibcon#first serial, iclass 7, count 0 2006.217.07:54:09.24#ibcon#enter sib2, iclass 7, count 0 2006.217.07:54:09.24#ibcon#flushed, iclass 7, count 0 2006.217.07:54:09.24#ibcon#about to write, iclass 7, count 0 2006.217.07:54:09.24#ibcon#wrote, iclass 7, count 0 2006.217.07:54:09.24#ibcon#about to read 3, iclass 7, count 0 2006.217.07:54:09.26#ibcon#read 3, iclass 7, count 0 2006.217.07:54:09.26#ibcon#about to read 4, iclass 7, count 0 2006.217.07:54:09.26#ibcon#read 4, iclass 7, count 0 2006.217.07:54:09.26#ibcon#about to read 5, iclass 7, count 0 2006.217.07:54:09.26#ibcon#read 5, iclass 7, count 0 2006.217.07:54:09.26#ibcon#about to read 6, iclass 7, count 0 2006.217.07:54:09.26#ibcon#read 6, iclass 7, count 0 2006.217.07:54:09.26#ibcon#end of sib2, iclass 7, count 0 2006.217.07:54:09.26#ibcon#*mode == 0, iclass 7, count 0 2006.217.07:54:09.26#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.217.07:54:09.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.217.07:54:09.26#ibcon#*before write, iclass 7, count 0 2006.217.07:54:09.26#ibcon#enter sib2, iclass 7, count 0 2006.217.07:54:09.26#ibcon#flushed, iclass 7, count 0 2006.217.07:54:09.26#ibcon#about to write, iclass 7, count 0 2006.217.07:54:09.26#ibcon#wrote, iclass 7, count 0 2006.217.07:54:09.26#ibcon#about to read 3, iclass 7, count 0 2006.217.07:54:09.30#ibcon#read 3, iclass 7, count 0 2006.217.07:54:09.30#ibcon#about to read 4, iclass 7, count 0 2006.217.07:54:09.30#ibcon#read 4, iclass 7, count 0 2006.217.07:54:09.30#ibcon#about to read 5, iclass 7, count 0 2006.217.07:54:09.30#ibcon#read 5, iclass 7, count 0 2006.217.07:54:09.30#ibcon#about to read 6, iclass 7, count 0 2006.217.07:54:09.30#ibcon#read 6, iclass 7, count 0 2006.217.07:54:09.30#ibcon#end of sib2, iclass 7, count 0 2006.217.07:54:09.30#ibcon#*after write, iclass 7, count 0 2006.217.07:54:09.30#ibcon#*before return 0, iclass 7, count 0 2006.217.07:54:09.30#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.217.07:54:09.30#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.217.07:54:09.30#ibcon#about to clear, iclass 7 cls_cnt 0 2006.217.07:54:09.30#ibcon#cleared, iclass 7 cls_cnt 0 2006.217.07:54:09.30$vc4f8/va=5,7 2006.217.07:54:09.30#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.217.07:54:09.30#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.217.07:54:09.30#ibcon#ireg 11 cls_cnt 2 2006.217.07:54:09.30#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.217.07:54:09.36#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.217.07:54:09.36#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.217.07:54:09.36#ibcon#enter wrdev, iclass 11, count 2 2006.217.07:54:09.36#ibcon#first serial, iclass 11, count 2 2006.217.07:54:09.36#ibcon#enter sib2, iclass 11, count 2 2006.217.07:54:09.36#ibcon#flushed, iclass 11, count 2 2006.217.07:54:09.36#ibcon#about to write, iclass 11, count 2 2006.217.07:54:09.36#ibcon#wrote, iclass 11, count 2 2006.217.07:54:09.36#ibcon#about to read 3, iclass 11, count 2 2006.217.07:54:09.38#ibcon#read 3, iclass 11, count 2 2006.217.07:54:09.38#ibcon#about to read 4, iclass 11, count 2 2006.217.07:54:09.38#ibcon#read 4, iclass 11, count 2 2006.217.07:54:09.38#ibcon#about to read 5, iclass 11, count 2 2006.217.07:54:09.38#ibcon#read 5, iclass 11, count 2 2006.217.07:54:09.38#ibcon#about to read 6, iclass 11, count 2 2006.217.07:54:09.38#ibcon#read 6, iclass 11, count 2 2006.217.07:54:09.38#ibcon#end of sib2, iclass 11, count 2 2006.217.07:54:09.38#ibcon#*mode == 0, iclass 11, count 2 2006.217.07:54:09.38#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.217.07:54:09.38#ibcon#[25=AT05-07\r\n] 2006.217.07:54:09.38#ibcon#*before write, iclass 11, count 2 2006.217.07:54:09.38#ibcon#enter sib2, iclass 11, count 2 2006.217.07:54:09.38#ibcon#flushed, iclass 11, count 2 2006.217.07:54:09.38#ibcon#about to write, iclass 11, count 2 2006.217.07:54:09.38#ibcon#wrote, iclass 11, count 2 2006.217.07:54:09.38#ibcon#about to read 3, iclass 11, count 2 2006.217.07:54:09.41#ibcon#read 3, iclass 11, count 2 2006.217.07:54:09.41#ibcon#about to read 4, iclass 11, count 2 2006.217.07:54:09.41#ibcon#read 4, iclass 11, count 2 2006.217.07:54:09.41#ibcon#about to read 5, iclass 11, count 2 2006.217.07:54:09.41#ibcon#read 5, iclass 11, count 2 2006.217.07:54:09.41#ibcon#about to read 6, iclass 11, count 2 2006.217.07:54:09.41#ibcon#read 6, iclass 11, count 2 2006.217.07:54:09.41#ibcon#end of sib2, iclass 11, count 2 2006.217.07:54:09.41#ibcon#*after write, iclass 11, count 2 2006.217.07:54:09.41#ibcon#*before return 0, iclass 11, count 2 2006.217.07:54:09.41#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.217.07:54:09.41#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.217.07:54:09.41#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.217.07:54:09.41#ibcon#ireg 7 cls_cnt 0 2006.217.07:54:09.41#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.217.07:54:09.53#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.217.07:54:09.53#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.217.07:54:09.53#ibcon#enter wrdev, iclass 11, count 0 2006.217.07:54:09.53#ibcon#first serial, iclass 11, count 0 2006.217.07:54:09.53#ibcon#enter sib2, iclass 11, count 0 2006.217.07:54:09.53#ibcon#flushed, iclass 11, count 0 2006.217.07:54:09.53#ibcon#about to write, iclass 11, count 0 2006.217.07:54:09.53#ibcon#wrote, iclass 11, count 0 2006.217.07:54:09.53#ibcon#about to read 3, iclass 11, count 0 2006.217.07:54:09.55#ibcon#read 3, iclass 11, count 0 2006.217.07:54:09.55#ibcon#about to read 4, iclass 11, count 0 2006.217.07:54:09.55#ibcon#read 4, iclass 11, count 0 2006.217.07:54:09.55#ibcon#about to read 5, iclass 11, count 0 2006.217.07:54:09.55#ibcon#read 5, iclass 11, count 0 2006.217.07:54:09.55#ibcon#about to read 6, iclass 11, count 0 2006.217.07:54:09.55#ibcon#read 6, iclass 11, count 0 2006.217.07:54:09.55#ibcon#end of sib2, iclass 11, count 0 2006.217.07:54:09.55#ibcon#*mode == 0, iclass 11, count 0 2006.217.07:54:09.55#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.217.07:54:09.55#ibcon#[25=USB\r\n] 2006.217.07:54:09.55#ibcon#*before write, iclass 11, count 0 2006.217.07:54:09.55#ibcon#enter sib2, iclass 11, count 0 2006.217.07:54:09.55#ibcon#flushed, iclass 11, count 0 2006.217.07:54:09.55#ibcon#about to write, iclass 11, count 0 2006.217.07:54:09.55#ibcon#wrote, iclass 11, count 0 2006.217.07:54:09.55#ibcon#about to read 3, iclass 11, count 0 2006.217.07:54:09.58#ibcon#read 3, iclass 11, count 0 2006.217.07:54:09.58#ibcon#about to read 4, iclass 11, count 0 2006.217.07:54:09.58#ibcon#read 4, iclass 11, count 0 2006.217.07:54:09.58#ibcon#about to read 5, iclass 11, count 0 2006.217.07:54:09.58#ibcon#read 5, iclass 11, count 0 2006.217.07:54:09.58#ibcon#about to read 6, iclass 11, count 0 2006.217.07:54:09.58#ibcon#read 6, iclass 11, count 0 2006.217.07:54:09.58#ibcon#end of sib2, iclass 11, count 0 2006.217.07:54:09.58#ibcon#*after write, iclass 11, count 0 2006.217.07:54:09.58#ibcon#*before return 0, iclass 11, count 0 2006.217.07:54:09.58#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.217.07:54:09.58#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.217.07:54:09.58#ibcon#about to clear, iclass 11 cls_cnt 0 2006.217.07:54:09.58#ibcon#cleared, iclass 11 cls_cnt 0 2006.217.07:54:09.58$vc4f8/valo=6,772.99 2006.217.07:54:09.58#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.217.07:54:09.58#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.217.07:54:09.58#ibcon#ireg 17 cls_cnt 0 2006.217.07:54:09.58#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.217.07:54:09.58#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.217.07:54:09.58#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.217.07:54:09.58#ibcon#enter wrdev, iclass 13, count 0 2006.217.07:54:09.58#ibcon#first serial, iclass 13, count 0 2006.217.07:54:09.58#ibcon#enter sib2, iclass 13, count 0 2006.217.07:54:09.58#ibcon#flushed, iclass 13, count 0 2006.217.07:54:09.58#ibcon#about to write, iclass 13, count 0 2006.217.07:54:09.58#ibcon#wrote, iclass 13, count 0 2006.217.07:54:09.58#ibcon#about to read 3, iclass 13, count 0 2006.217.07:54:09.61#ibcon#read 3, iclass 13, count 0 2006.217.07:54:09.61#ibcon#about to read 4, iclass 13, count 0 2006.217.07:54:09.61#ibcon#read 4, iclass 13, count 0 2006.217.07:54:09.61#ibcon#about to read 5, iclass 13, count 0 2006.217.07:54:09.61#ibcon#read 5, iclass 13, count 0 2006.217.07:54:09.61#ibcon#about to read 6, iclass 13, count 0 2006.217.07:54:09.61#ibcon#read 6, iclass 13, count 0 2006.217.07:54:09.61#ibcon#end of sib2, iclass 13, count 0 2006.217.07:54:09.61#ibcon#*mode == 0, iclass 13, count 0 2006.217.07:54:09.61#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.217.07:54:09.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.217.07:54:09.61#ibcon#*before write, iclass 13, count 0 2006.217.07:54:09.61#ibcon#enter sib2, iclass 13, count 0 2006.217.07:54:09.61#ibcon#flushed, iclass 13, count 0 2006.217.07:54:09.61#ibcon#about to write, iclass 13, count 0 2006.217.07:54:09.61#ibcon#wrote, iclass 13, count 0 2006.217.07:54:09.61#ibcon#about to read 3, iclass 13, count 0 2006.217.07:54:09.65#ibcon#read 3, iclass 13, count 0 2006.217.07:54:09.65#ibcon#about to read 4, iclass 13, count 0 2006.217.07:54:09.65#ibcon#read 4, iclass 13, count 0 2006.217.07:54:09.65#ibcon#about to read 5, iclass 13, count 0 2006.217.07:54:09.65#ibcon#read 5, iclass 13, count 0 2006.217.07:54:09.65#ibcon#about to read 6, iclass 13, count 0 2006.217.07:54:09.65#ibcon#read 6, iclass 13, count 0 2006.217.07:54:09.65#ibcon#end of sib2, iclass 13, count 0 2006.217.07:54:09.65#ibcon#*after write, iclass 13, count 0 2006.217.07:54:09.65#ibcon#*before return 0, iclass 13, count 0 2006.217.07:54:09.65#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.217.07:54:09.65#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.217.07:54:09.65#ibcon#about to clear, iclass 13 cls_cnt 0 2006.217.07:54:09.65#ibcon#cleared, iclass 13 cls_cnt 0 2006.217.07:54:09.65$vc4f8/va=6,6 2006.217.07:54:09.65#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.217.07:54:09.65#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.217.07:54:09.65#ibcon#ireg 11 cls_cnt 2 2006.217.07:54:09.65#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.217.07:54:09.70#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.217.07:54:09.70#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.217.07:54:09.70#ibcon#enter wrdev, iclass 15, count 2 2006.217.07:54:09.70#ibcon#first serial, iclass 15, count 2 2006.217.07:54:09.70#ibcon#enter sib2, iclass 15, count 2 2006.217.07:54:09.70#ibcon#flushed, iclass 15, count 2 2006.217.07:54:09.70#ibcon#about to write, iclass 15, count 2 2006.217.07:54:09.70#ibcon#wrote, iclass 15, count 2 2006.217.07:54:09.70#ibcon#about to read 3, iclass 15, count 2 2006.217.07:54:09.72#ibcon#read 3, iclass 15, count 2 2006.217.07:54:09.72#ibcon#about to read 4, iclass 15, count 2 2006.217.07:54:09.72#ibcon#read 4, iclass 15, count 2 2006.217.07:54:09.72#ibcon#about to read 5, iclass 15, count 2 2006.217.07:54:09.72#ibcon#read 5, iclass 15, count 2 2006.217.07:54:09.72#ibcon#about to read 6, iclass 15, count 2 2006.217.07:54:09.72#ibcon#read 6, iclass 15, count 2 2006.217.07:54:09.72#ibcon#end of sib2, iclass 15, count 2 2006.217.07:54:09.72#ibcon#*mode == 0, iclass 15, count 2 2006.217.07:54:09.72#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.217.07:54:09.72#ibcon#[25=AT06-06\r\n] 2006.217.07:54:09.72#ibcon#*before write, iclass 15, count 2 2006.217.07:54:09.72#ibcon#enter sib2, iclass 15, count 2 2006.217.07:54:09.72#ibcon#flushed, iclass 15, count 2 2006.217.07:54:09.72#ibcon#about to write, iclass 15, count 2 2006.217.07:54:09.72#ibcon#wrote, iclass 15, count 2 2006.217.07:54:09.72#ibcon#about to read 3, iclass 15, count 2 2006.217.07:54:09.75#ibcon#read 3, iclass 15, count 2 2006.217.07:54:09.75#ibcon#about to read 4, iclass 15, count 2 2006.217.07:54:09.75#ibcon#read 4, iclass 15, count 2 2006.217.07:54:09.75#ibcon#about to read 5, iclass 15, count 2 2006.217.07:54:09.75#ibcon#read 5, iclass 15, count 2 2006.217.07:54:09.75#ibcon#about to read 6, iclass 15, count 2 2006.217.07:54:09.75#ibcon#read 6, iclass 15, count 2 2006.217.07:54:09.75#ibcon#end of sib2, iclass 15, count 2 2006.217.07:54:09.75#ibcon#*after write, iclass 15, count 2 2006.217.07:54:09.75#ibcon#*before return 0, iclass 15, count 2 2006.217.07:54:09.75#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.217.07:54:09.75#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.217.07:54:09.75#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.217.07:54:09.75#ibcon#ireg 7 cls_cnt 0 2006.217.07:54:09.75#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.217.07:54:09.87#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.217.07:54:09.87#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.217.07:54:09.87#ibcon#enter wrdev, iclass 15, count 0 2006.217.07:54:09.87#ibcon#first serial, iclass 15, count 0 2006.217.07:54:09.87#ibcon#enter sib2, iclass 15, count 0 2006.217.07:54:09.87#ibcon#flushed, iclass 15, count 0 2006.217.07:54:09.87#ibcon#about to write, iclass 15, count 0 2006.217.07:54:09.87#ibcon#wrote, iclass 15, count 0 2006.217.07:54:09.87#ibcon#about to read 3, iclass 15, count 0 2006.217.07:54:09.89#ibcon#read 3, iclass 15, count 0 2006.217.07:54:09.89#ibcon#about to read 4, iclass 15, count 0 2006.217.07:54:09.89#ibcon#read 4, iclass 15, count 0 2006.217.07:54:09.89#ibcon#about to read 5, iclass 15, count 0 2006.217.07:54:09.89#ibcon#read 5, iclass 15, count 0 2006.217.07:54:09.89#ibcon#about to read 6, iclass 15, count 0 2006.217.07:54:09.89#ibcon#read 6, iclass 15, count 0 2006.217.07:54:09.89#ibcon#end of sib2, iclass 15, count 0 2006.217.07:54:09.89#ibcon#*mode == 0, iclass 15, count 0 2006.217.07:54:09.89#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.217.07:54:09.89#ibcon#[25=USB\r\n] 2006.217.07:54:09.89#ibcon#*before write, iclass 15, count 0 2006.217.07:54:09.89#ibcon#enter sib2, iclass 15, count 0 2006.217.07:54:09.89#ibcon#flushed, iclass 15, count 0 2006.217.07:54:09.89#ibcon#about to write, iclass 15, count 0 2006.217.07:54:09.89#ibcon#wrote, iclass 15, count 0 2006.217.07:54:09.89#ibcon#about to read 3, iclass 15, count 0 2006.217.07:54:09.92#ibcon#read 3, iclass 15, count 0 2006.217.07:54:09.92#ibcon#about to read 4, iclass 15, count 0 2006.217.07:54:09.92#ibcon#read 4, iclass 15, count 0 2006.217.07:54:09.92#ibcon#about to read 5, iclass 15, count 0 2006.217.07:54:09.92#ibcon#read 5, iclass 15, count 0 2006.217.07:54:09.92#ibcon#about to read 6, iclass 15, count 0 2006.217.07:54:09.92#ibcon#read 6, iclass 15, count 0 2006.217.07:54:09.92#ibcon#end of sib2, iclass 15, count 0 2006.217.07:54:09.92#ibcon#*after write, iclass 15, count 0 2006.217.07:54:09.92#ibcon#*before return 0, iclass 15, count 0 2006.217.07:54:09.92#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.217.07:54:09.92#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.217.07:54:09.92#ibcon#about to clear, iclass 15 cls_cnt 0 2006.217.07:54:09.92#ibcon#cleared, iclass 15 cls_cnt 0 2006.217.07:54:09.92$vc4f8/valo=7,832.99 2006.217.07:54:09.92#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.217.07:54:09.92#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.217.07:54:09.92#ibcon#ireg 17 cls_cnt 0 2006.217.07:54:09.92#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.217.07:54:09.92#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.217.07:54:09.92#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.217.07:54:09.92#ibcon#enter wrdev, iclass 17, count 0 2006.217.07:54:09.92#ibcon#first serial, iclass 17, count 0 2006.217.07:54:09.92#ibcon#enter sib2, iclass 17, count 0 2006.217.07:54:09.92#ibcon#flushed, iclass 17, count 0 2006.217.07:54:09.92#ibcon#about to write, iclass 17, count 0 2006.217.07:54:09.92#ibcon#wrote, iclass 17, count 0 2006.217.07:54:09.92#ibcon#about to read 3, iclass 17, count 0 2006.217.07:54:09.94#ibcon#read 3, iclass 17, count 0 2006.217.07:54:09.94#ibcon#about to read 4, iclass 17, count 0 2006.217.07:54:09.94#ibcon#read 4, iclass 17, count 0 2006.217.07:54:09.94#ibcon#about to read 5, iclass 17, count 0 2006.217.07:54:09.94#ibcon#read 5, iclass 17, count 0 2006.217.07:54:09.94#ibcon#about to read 6, iclass 17, count 0 2006.217.07:54:09.94#ibcon#read 6, iclass 17, count 0 2006.217.07:54:09.94#ibcon#end of sib2, iclass 17, count 0 2006.217.07:54:09.94#ibcon#*mode == 0, iclass 17, count 0 2006.217.07:54:09.94#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.217.07:54:09.94#ibcon#[26=FRQ=07,832.99\r\n] 2006.217.07:54:09.94#ibcon#*before write, iclass 17, count 0 2006.217.07:54:09.94#ibcon#enter sib2, iclass 17, count 0 2006.217.07:54:09.94#ibcon#flushed, iclass 17, count 0 2006.217.07:54:09.94#ibcon#about to write, iclass 17, count 0 2006.217.07:54:09.94#ibcon#wrote, iclass 17, count 0 2006.217.07:54:09.94#ibcon#about to read 3, iclass 17, count 0 2006.217.07:54:09.98#ibcon#read 3, iclass 17, count 0 2006.217.07:54:09.98#ibcon#about to read 4, iclass 17, count 0 2006.217.07:54:09.98#ibcon#read 4, iclass 17, count 0 2006.217.07:54:09.98#ibcon#about to read 5, iclass 17, count 0 2006.217.07:54:09.98#ibcon#read 5, iclass 17, count 0 2006.217.07:54:09.98#ibcon#about to read 6, iclass 17, count 0 2006.217.07:54:09.98#ibcon#read 6, iclass 17, count 0 2006.217.07:54:09.98#ibcon#end of sib2, iclass 17, count 0 2006.217.07:54:09.98#ibcon#*after write, iclass 17, count 0 2006.217.07:54:09.98#ibcon#*before return 0, iclass 17, count 0 2006.217.07:54:09.98#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.217.07:54:09.98#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.217.07:54:09.98#ibcon#about to clear, iclass 17 cls_cnt 0 2006.217.07:54:09.98#ibcon#cleared, iclass 17 cls_cnt 0 2006.217.07:54:09.98$vc4f8/va=7,6 2006.217.07:54:09.98#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.217.07:54:09.98#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.217.07:54:09.98#ibcon#ireg 11 cls_cnt 2 2006.217.07:54:09.98#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.217.07:54:10.04#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.217.07:54:10.04#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.217.07:54:10.04#ibcon#enter wrdev, iclass 19, count 2 2006.217.07:54:10.04#ibcon#first serial, iclass 19, count 2 2006.217.07:54:10.04#ibcon#enter sib2, iclass 19, count 2 2006.217.07:54:10.04#ibcon#flushed, iclass 19, count 2 2006.217.07:54:10.04#ibcon#about to write, iclass 19, count 2 2006.217.07:54:10.04#ibcon#wrote, iclass 19, count 2 2006.217.07:54:10.04#ibcon#about to read 3, iclass 19, count 2 2006.217.07:54:10.06#ibcon#read 3, iclass 19, count 2 2006.217.07:54:10.06#ibcon#about to read 4, iclass 19, count 2 2006.217.07:54:10.06#ibcon#read 4, iclass 19, count 2 2006.217.07:54:10.06#ibcon#about to read 5, iclass 19, count 2 2006.217.07:54:10.06#ibcon#read 5, iclass 19, count 2 2006.217.07:54:10.06#ibcon#about to read 6, iclass 19, count 2 2006.217.07:54:10.06#ibcon#read 6, iclass 19, count 2 2006.217.07:54:10.06#ibcon#end of sib2, iclass 19, count 2 2006.217.07:54:10.06#ibcon#*mode == 0, iclass 19, count 2 2006.217.07:54:10.06#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.217.07:54:10.06#ibcon#[25=AT07-06\r\n] 2006.217.07:54:10.06#ibcon#*before write, iclass 19, count 2 2006.217.07:54:10.06#ibcon#enter sib2, iclass 19, count 2 2006.217.07:54:10.06#ibcon#flushed, iclass 19, count 2 2006.217.07:54:10.06#ibcon#about to write, iclass 19, count 2 2006.217.07:54:10.06#ibcon#wrote, iclass 19, count 2 2006.217.07:54:10.06#ibcon#about to read 3, iclass 19, count 2 2006.217.07:54:10.09#ibcon#read 3, iclass 19, count 2 2006.217.07:54:10.09#ibcon#about to read 4, iclass 19, count 2 2006.217.07:54:10.09#ibcon#read 4, iclass 19, count 2 2006.217.07:54:10.09#ibcon#about to read 5, iclass 19, count 2 2006.217.07:54:10.09#ibcon#read 5, iclass 19, count 2 2006.217.07:54:10.09#ibcon#about to read 6, iclass 19, count 2 2006.217.07:54:10.09#ibcon#read 6, iclass 19, count 2 2006.217.07:54:10.09#ibcon#end of sib2, iclass 19, count 2 2006.217.07:54:10.09#ibcon#*after write, iclass 19, count 2 2006.217.07:54:10.09#ibcon#*before return 0, iclass 19, count 2 2006.217.07:54:10.09#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.217.07:54:10.09#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.217.07:54:10.09#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.217.07:54:10.09#ibcon#ireg 7 cls_cnt 0 2006.217.07:54:10.09#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.217.07:54:10.21#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.217.07:54:10.21#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.217.07:54:10.21#ibcon#enter wrdev, iclass 19, count 0 2006.217.07:54:10.21#ibcon#first serial, iclass 19, count 0 2006.217.07:54:10.21#ibcon#enter sib2, iclass 19, count 0 2006.217.07:54:10.21#ibcon#flushed, iclass 19, count 0 2006.217.07:54:10.21#ibcon#about to write, iclass 19, count 0 2006.217.07:54:10.21#ibcon#wrote, iclass 19, count 0 2006.217.07:54:10.21#ibcon#about to read 3, iclass 19, count 0 2006.217.07:54:10.23#ibcon#read 3, iclass 19, count 0 2006.217.07:54:10.23#ibcon#about to read 4, iclass 19, count 0 2006.217.07:54:10.23#ibcon#read 4, iclass 19, count 0 2006.217.07:54:10.23#ibcon#about to read 5, iclass 19, count 0 2006.217.07:54:10.23#ibcon#read 5, iclass 19, count 0 2006.217.07:54:10.23#ibcon#about to read 6, iclass 19, count 0 2006.217.07:54:10.23#ibcon#read 6, iclass 19, count 0 2006.217.07:54:10.23#ibcon#end of sib2, iclass 19, count 0 2006.217.07:54:10.23#ibcon#*mode == 0, iclass 19, count 0 2006.217.07:54:10.23#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.217.07:54:10.23#ibcon#[25=USB\r\n] 2006.217.07:54:10.23#ibcon#*before write, iclass 19, count 0 2006.217.07:54:10.23#ibcon#enter sib2, iclass 19, count 0 2006.217.07:54:10.23#ibcon#flushed, iclass 19, count 0 2006.217.07:54:10.23#ibcon#about to write, iclass 19, count 0 2006.217.07:54:10.23#ibcon#wrote, iclass 19, count 0 2006.217.07:54:10.23#ibcon#about to read 3, iclass 19, count 0 2006.217.07:54:10.26#ibcon#read 3, iclass 19, count 0 2006.217.07:54:10.26#ibcon#about to read 4, iclass 19, count 0 2006.217.07:54:10.26#ibcon#read 4, iclass 19, count 0 2006.217.07:54:10.26#ibcon#about to read 5, iclass 19, count 0 2006.217.07:54:10.26#ibcon#read 5, iclass 19, count 0 2006.217.07:54:10.26#ibcon#about to read 6, iclass 19, count 0 2006.217.07:54:10.26#ibcon#read 6, iclass 19, count 0 2006.217.07:54:10.26#ibcon#end of sib2, iclass 19, count 0 2006.217.07:54:10.26#ibcon#*after write, iclass 19, count 0 2006.217.07:54:10.26#ibcon#*before return 0, iclass 19, count 0 2006.217.07:54:10.26#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.217.07:54:10.26#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.217.07:54:10.26#ibcon#about to clear, iclass 19 cls_cnt 0 2006.217.07:54:10.26#ibcon#cleared, iclass 19 cls_cnt 0 2006.217.07:54:10.26$vc4f8/valo=8,852.99 2006.217.07:54:10.26#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.217.07:54:10.26#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.217.07:54:10.26#ibcon#ireg 17 cls_cnt 0 2006.217.07:54:10.26#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.217.07:54:10.26#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.217.07:54:10.26#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.217.07:54:10.26#ibcon#enter wrdev, iclass 21, count 0 2006.217.07:54:10.26#ibcon#first serial, iclass 21, count 0 2006.217.07:54:10.26#ibcon#enter sib2, iclass 21, count 0 2006.217.07:54:10.26#ibcon#flushed, iclass 21, count 0 2006.217.07:54:10.26#ibcon#about to write, iclass 21, count 0 2006.217.07:54:10.26#ibcon#wrote, iclass 21, count 0 2006.217.07:54:10.26#ibcon#about to read 3, iclass 21, count 0 2006.217.07:54:10.28#ibcon#read 3, iclass 21, count 0 2006.217.07:54:10.28#ibcon#about to read 4, iclass 21, count 0 2006.217.07:54:10.28#ibcon#read 4, iclass 21, count 0 2006.217.07:54:10.28#ibcon#about to read 5, iclass 21, count 0 2006.217.07:54:10.28#ibcon#read 5, iclass 21, count 0 2006.217.07:54:10.28#ibcon#about to read 6, iclass 21, count 0 2006.217.07:54:10.28#ibcon#read 6, iclass 21, count 0 2006.217.07:54:10.28#ibcon#end of sib2, iclass 21, count 0 2006.217.07:54:10.28#ibcon#*mode == 0, iclass 21, count 0 2006.217.07:54:10.28#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.217.07:54:10.28#ibcon#[26=FRQ=08,852.99\r\n] 2006.217.07:54:10.28#ibcon#*before write, iclass 21, count 0 2006.217.07:54:10.28#ibcon#enter sib2, iclass 21, count 0 2006.217.07:54:10.28#ibcon#flushed, iclass 21, count 0 2006.217.07:54:10.28#ibcon#about to write, iclass 21, count 0 2006.217.07:54:10.28#ibcon#wrote, iclass 21, count 0 2006.217.07:54:10.28#ibcon#about to read 3, iclass 21, count 0 2006.217.07:54:10.32#ibcon#read 3, iclass 21, count 0 2006.217.07:54:10.32#ibcon#about to read 4, iclass 21, count 0 2006.217.07:54:10.32#ibcon#read 4, iclass 21, count 0 2006.217.07:54:10.32#ibcon#about to read 5, iclass 21, count 0 2006.217.07:54:10.32#ibcon#read 5, iclass 21, count 0 2006.217.07:54:10.32#ibcon#about to read 6, iclass 21, count 0 2006.217.07:54:10.32#ibcon#read 6, iclass 21, count 0 2006.217.07:54:10.32#ibcon#end of sib2, iclass 21, count 0 2006.217.07:54:10.32#ibcon#*after write, iclass 21, count 0 2006.217.07:54:10.32#ibcon#*before return 0, iclass 21, count 0 2006.217.07:54:10.32#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.217.07:54:10.32#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.217.07:54:10.32#ibcon#about to clear, iclass 21 cls_cnt 0 2006.217.07:54:10.32#ibcon#cleared, iclass 21 cls_cnt 0 2006.217.07:54:10.32$vc4f8/va=8,7 2006.217.07:54:10.32#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.217.07:54:10.32#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.217.07:54:10.32#ibcon#ireg 11 cls_cnt 2 2006.217.07:54:10.32#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.217.07:54:10.38#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.217.07:54:10.38#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.217.07:54:10.38#ibcon#enter wrdev, iclass 23, count 2 2006.217.07:54:10.38#ibcon#first serial, iclass 23, count 2 2006.217.07:54:10.38#ibcon#enter sib2, iclass 23, count 2 2006.217.07:54:10.38#ibcon#flushed, iclass 23, count 2 2006.217.07:54:10.38#ibcon#about to write, iclass 23, count 2 2006.217.07:54:10.38#ibcon#wrote, iclass 23, count 2 2006.217.07:54:10.38#ibcon#about to read 3, iclass 23, count 2 2006.217.07:54:10.40#ibcon#read 3, iclass 23, count 2 2006.217.07:54:10.40#ibcon#about to read 4, iclass 23, count 2 2006.217.07:54:10.40#ibcon#read 4, iclass 23, count 2 2006.217.07:54:10.40#ibcon#about to read 5, iclass 23, count 2 2006.217.07:54:10.40#ibcon#read 5, iclass 23, count 2 2006.217.07:54:10.40#ibcon#about to read 6, iclass 23, count 2 2006.217.07:54:10.40#ibcon#read 6, iclass 23, count 2 2006.217.07:54:10.40#ibcon#end of sib2, iclass 23, count 2 2006.217.07:54:10.40#ibcon#*mode == 0, iclass 23, count 2 2006.217.07:54:10.40#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.217.07:54:10.40#ibcon#[25=AT08-07\r\n] 2006.217.07:54:10.40#ibcon#*before write, iclass 23, count 2 2006.217.07:54:10.40#ibcon#enter sib2, iclass 23, count 2 2006.217.07:54:10.40#ibcon#flushed, iclass 23, count 2 2006.217.07:54:10.40#ibcon#about to write, iclass 23, count 2 2006.217.07:54:10.40#ibcon#wrote, iclass 23, count 2 2006.217.07:54:10.40#ibcon#about to read 3, iclass 23, count 2 2006.217.07:54:10.43#ibcon#read 3, iclass 23, count 2 2006.217.07:54:10.43#ibcon#about to read 4, iclass 23, count 2 2006.217.07:54:10.43#ibcon#read 4, iclass 23, count 2 2006.217.07:54:10.43#ibcon#about to read 5, iclass 23, count 2 2006.217.07:54:10.43#ibcon#read 5, iclass 23, count 2 2006.217.07:54:10.43#ibcon#about to read 6, iclass 23, count 2 2006.217.07:54:10.43#ibcon#read 6, iclass 23, count 2 2006.217.07:54:10.43#ibcon#end of sib2, iclass 23, count 2 2006.217.07:54:10.43#ibcon#*after write, iclass 23, count 2 2006.217.07:54:10.43#ibcon#*before return 0, iclass 23, count 2 2006.217.07:54:10.43#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.217.07:54:10.43#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.217.07:54:10.43#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.217.07:54:10.43#ibcon#ireg 7 cls_cnt 0 2006.217.07:54:10.43#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.217.07:54:10.55#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.217.07:54:10.55#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.217.07:54:10.55#ibcon#enter wrdev, iclass 23, count 0 2006.217.07:54:10.55#ibcon#first serial, iclass 23, count 0 2006.217.07:54:10.55#ibcon#enter sib2, iclass 23, count 0 2006.217.07:54:10.55#ibcon#flushed, iclass 23, count 0 2006.217.07:54:10.55#ibcon#about to write, iclass 23, count 0 2006.217.07:54:10.55#ibcon#wrote, iclass 23, count 0 2006.217.07:54:10.55#ibcon#about to read 3, iclass 23, count 0 2006.217.07:54:10.57#ibcon#read 3, iclass 23, count 0 2006.217.07:54:10.57#ibcon#about to read 4, iclass 23, count 0 2006.217.07:54:10.57#ibcon#read 4, iclass 23, count 0 2006.217.07:54:10.57#ibcon#about to read 5, iclass 23, count 0 2006.217.07:54:10.57#ibcon#read 5, iclass 23, count 0 2006.217.07:54:10.57#ibcon#about to read 6, iclass 23, count 0 2006.217.07:54:10.57#ibcon#read 6, iclass 23, count 0 2006.217.07:54:10.57#ibcon#end of sib2, iclass 23, count 0 2006.217.07:54:10.57#ibcon#*mode == 0, iclass 23, count 0 2006.217.07:54:10.57#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.217.07:54:10.57#ibcon#[25=USB\r\n] 2006.217.07:54:10.57#ibcon#*before write, iclass 23, count 0 2006.217.07:54:10.57#ibcon#enter sib2, iclass 23, count 0 2006.217.07:54:10.57#ibcon#flushed, iclass 23, count 0 2006.217.07:54:10.57#ibcon#about to write, iclass 23, count 0 2006.217.07:54:10.57#ibcon#wrote, iclass 23, count 0 2006.217.07:54:10.57#ibcon#about to read 3, iclass 23, count 0 2006.217.07:54:10.60#ibcon#read 3, iclass 23, count 0 2006.217.07:54:10.60#ibcon#about to read 4, iclass 23, count 0 2006.217.07:54:10.60#ibcon#read 4, iclass 23, count 0 2006.217.07:54:10.60#ibcon#about to read 5, iclass 23, count 0 2006.217.07:54:10.60#ibcon#read 5, iclass 23, count 0 2006.217.07:54:10.60#ibcon#about to read 6, iclass 23, count 0 2006.217.07:54:10.60#ibcon#read 6, iclass 23, count 0 2006.217.07:54:10.60#ibcon#end of sib2, iclass 23, count 0 2006.217.07:54:10.60#ibcon#*after write, iclass 23, count 0 2006.217.07:54:10.60#ibcon#*before return 0, iclass 23, count 0 2006.217.07:54:10.60#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.217.07:54:10.60#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.217.07:54:10.60#ibcon#about to clear, iclass 23 cls_cnt 0 2006.217.07:54:10.60#ibcon#cleared, iclass 23 cls_cnt 0 2006.217.07:54:10.60$vc4f8/vblo=1,632.99 2006.217.07:54:10.60#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.217.07:54:10.60#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.217.07:54:10.60#ibcon#ireg 17 cls_cnt 0 2006.217.07:54:10.60#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.217.07:54:10.60#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.217.07:54:10.60#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.217.07:54:10.60#ibcon#enter wrdev, iclass 25, count 0 2006.217.07:54:10.60#ibcon#first serial, iclass 25, count 0 2006.217.07:54:10.60#ibcon#enter sib2, iclass 25, count 0 2006.217.07:54:10.60#ibcon#flushed, iclass 25, count 0 2006.217.07:54:10.60#ibcon#about to write, iclass 25, count 0 2006.217.07:54:10.60#ibcon#wrote, iclass 25, count 0 2006.217.07:54:10.60#ibcon#about to read 3, iclass 25, count 0 2006.217.07:54:10.62#ibcon#read 3, iclass 25, count 0 2006.217.07:54:10.62#ibcon#about to read 4, iclass 25, count 0 2006.217.07:54:10.62#ibcon#read 4, iclass 25, count 0 2006.217.07:54:10.62#ibcon#about to read 5, iclass 25, count 0 2006.217.07:54:10.62#ibcon#read 5, iclass 25, count 0 2006.217.07:54:10.62#ibcon#about to read 6, iclass 25, count 0 2006.217.07:54:10.62#ibcon#read 6, iclass 25, count 0 2006.217.07:54:10.62#ibcon#end of sib2, iclass 25, count 0 2006.217.07:54:10.62#ibcon#*mode == 0, iclass 25, count 0 2006.217.07:54:10.62#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.217.07:54:10.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.217.07:54:10.62#ibcon#*before write, iclass 25, count 0 2006.217.07:54:10.62#ibcon#enter sib2, iclass 25, count 0 2006.217.07:54:10.62#ibcon#flushed, iclass 25, count 0 2006.217.07:54:10.62#ibcon#about to write, iclass 25, count 0 2006.217.07:54:10.62#ibcon#wrote, iclass 25, count 0 2006.217.07:54:10.62#ibcon#about to read 3, iclass 25, count 0 2006.217.07:54:10.66#ibcon#read 3, iclass 25, count 0 2006.217.07:54:10.66#ibcon#about to read 4, iclass 25, count 0 2006.217.07:54:10.66#ibcon#read 4, iclass 25, count 0 2006.217.07:54:10.66#ibcon#about to read 5, iclass 25, count 0 2006.217.07:54:10.66#ibcon#read 5, iclass 25, count 0 2006.217.07:54:10.66#ibcon#about to read 6, iclass 25, count 0 2006.217.07:54:10.66#ibcon#read 6, iclass 25, count 0 2006.217.07:54:10.66#ibcon#end of sib2, iclass 25, count 0 2006.217.07:54:10.66#ibcon#*after write, iclass 25, count 0 2006.217.07:54:10.66#ibcon#*before return 0, iclass 25, count 0 2006.217.07:54:10.66#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.217.07:54:10.66#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.217.07:54:10.66#ibcon#about to clear, iclass 25 cls_cnt 0 2006.217.07:54:10.66#ibcon#cleared, iclass 25 cls_cnt 0 2006.217.07:54:10.66$vc4f8/vb=1,4 2006.217.07:54:10.66#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.217.07:54:10.66#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.217.07:54:10.66#ibcon#ireg 11 cls_cnt 2 2006.217.07:54:10.66#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.217.07:54:10.66#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.217.07:54:10.66#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.217.07:54:10.66#ibcon#enter wrdev, iclass 27, count 2 2006.217.07:54:10.66#ibcon#first serial, iclass 27, count 2 2006.217.07:54:10.66#ibcon#enter sib2, iclass 27, count 2 2006.217.07:54:10.66#ibcon#flushed, iclass 27, count 2 2006.217.07:54:10.66#ibcon#about to write, iclass 27, count 2 2006.217.07:54:10.66#ibcon#wrote, iclass 27, count 2 2006.217.07:54:10.66#ibcon#about to read 3, iclass 27, count 2 2006.217.07:54:10.68#ibcon#read 3, iclass 27, count 2 2006.217.07:54:10.68#ibcon#about to read 4, iclass 27, count 2 2006.217.07:54:10.68#ibcon#read 4, iclass 27, count 2 2006.217.07:54:10.68#ibcon#about to read 5, iclass 27, count 2 2006.217.07:54:10.68#ibcon#read 5, iclass 27, count 2 2006.217.07:54:10.68#ibcon#about to read 6, iclass 27, count 2 2006.217.07:54:10.68#ibcon#read 6, iclass 27, count 2 2006.217.07:54:10.68#ibcon#end of sib2, iclass 27, count 2 2006.217.07:54:10.68#ibcon#*mode == 0, iclass 27, count 2 2006.217.07:54:10.68#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.217.07:54:10.68#ibcon#[27=AT01-04\r\n] 2006.217.07:54:10.68#ibcon#*before write, iclass 27, count 2 2006.217.07:54:10.68#ibcon#enter sib2, iclass 27, count 2 2006.217.07:54:10.68#ibcon#flushed, iclass 27, count 2 2006.217.07:54:10.68#ibcon#about to write, iclass 27, count 2 2006.217.07:54:10.68#ibcon#wrote, iclass 27, count 2 2006.217.07:54:10.68#ibcon#about to read 3, iclass 27, count 2 2006.217.07:54:10.71#ibcon#read 3, iclass 27, count 2 2006.217.07:54:10.71#ibcon#about to read 4, iclass 27, count 2 2006.217.07:54:10.71#ibcon#read 4, iclass 27, count 2 2006.217.07:54:10.71#ibcon#about to read 5, iclass 27, count 2 2006.217.07:54:10.71#ibcon#read 5, iclass 27, count 2 2006.217.07:54:10.71#ibcon#about to read 6, iclass 27, count 2 2006.217.07:54:10.71#ibcon#read 6, iclass 27, count 2 2006.217.07:54:10.71#ibcon#end of sib2, iclass 27, count 2 2006.217.07:54:10.71#ibcon#*after write, iclass 27, count 2 2006.217.07:54:10.71#ibcon#*before return 0, iclass 27, count 2 2006.217.07:54:10.71#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.217.07:54:10.71#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.217.07:54:10.71#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.217.07:54:10.71#ibcon#ireg 7 cls_cnt 0 2006.217.07:54:10.71#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.217.07:54:10.83#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.217.07:54:10.83#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.217.07:54:10.83#ibcon#enter wrdev, iclass 27, count 0 2006.217.07:54:10.83#ibcon#first serial, iclass 27, count 0 2006.217.07:54:10.83#ibcon#enter sib2, iclass 27, count 0 2006.217.07:54:10.83#ibcon#flushed, iclass 27, count 0 2006.217.07:54:10.83#ibcon#about to write, iclass 27, count 0 2006.217.07:54:10.83#ibcon#wrote, iclass 27, count 0 2006.217.07:54:10.83#ibcon#about to read 3, iclass 27, count 0 2006.217.07:54:10.85#ibcon#read 3, iclass 27, count 0 2006.217.07:54:10.85#ibcon#about to read 4, iclass 27, count 0 2006.217.07:54:10.85#ibcon#read 4, iclass 27, count 0 2006.217.07:54:10.85#ibcon#about to read 5, iclass 27, count 0 2006.217.07:54:10.85#ibcon#read 5, iclass 27, count 0 2006.217.07:54:10.85#ibcon#about to read 6, iclass 27, count 0 2006.217.07:54:10.85#ibcon#read 6, iclass 27, count 0 2006.217.07:54:10.85#ibcon#end of sib2, iclass 27, count 0 2006.217.07:54:10.85#ibcon#*mode == 0, iclass 27, count 0 2006.217.07:54:10.85#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.217.07:54:10.85#ibcon#[27=USB\r\n] 2006.217.07:54:10.85#ibcon#*before write, iclass 27, count 0 2006.217.07:54:10.85#ibcon#enter sib2, iclass 27, count 0 2006.217.07:54:10.85#ibcon#flushed, iclass 27, count 0 2006.217.07:54:10.85#ibcon#about to write, iclass 27, count 0 2006.217.07:54:10.85#ibcon#wrote, iclass 27, count 0 2006.217.07:54:10.85#ibcon#about to read 3, iclass 27, count 0 2006.217.07:54:10.88#ibcon#read 3, iclass 27, count 0 2006.217.07:54:10.88#ibcon#about to read 4, iclass 27, count 0 2006.217.07:54:10.88#ibcon#read 4, iclass 27, count 0 2006.217.07:54:10.88#ibcon#about to read 5, iclass 27, count 0 2006.217.07:54:10.88#ibcon#read 5, iclass 27, count 0 2006.217.07:54:10.88#ibcon#about to read 6, iclass 27, count 0 2006.217.07:54:10.88#ibcon#read 6, iclass 27, count 0 2006.217.07:54:10.88#ibcon#end of sib2, iclass 27, count 0 2006.217.07:54:10.88#ibcon#*after write, iclass 27, count 0 2006.217.07:54:10.88#ibcon#*before return 0, iclass 27, count 0 2006.217.07:54:10.88#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.217.07:54:10.88#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.217.07:54:10.88#ibcon#about to clear, iclass 27 cls_cnt 0 2006.217.07:54:10.88#ibcon#cleared, iclass 27 cls_cnt 0 2006.217.07:54:10.88$vc4f8/vblo=2,640.99 2006.217.07:54:10.88#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.217.07:54:10.88#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.217.07:54:10.88#ibcon#ireg 17 cls_cnt 0 2006.217.07:54:10.88#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.217.07:54:10.88#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.217.07:54:10.88#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.217.07:54:10.88#ibcon#enter wrdev, iclass 29, count 0 2006.217.07:54:10.88#ibcon#first serial, iclass 29, count 0 2006.217.07:54:10.88#ibcon#enter sib2, iclass 29, count 0 2006.217.07:54:10.88#ibcon#flushed, iclass 29, count 0 2006.217.07:54:10.88#ibcon#about to write, iclass 29, count 0 2006.217.07:54:10.88#ibcon#wrote, iclass 29, count 0 2006.217.07:54:10.88#ibcon#about to read 3, iclass 29, count 0 2006.217.07:54:10.90#ibcon#read 3, iclass 29, count 0 2006.217.07:54:10.90#ibcon#about to read 4, iclass 29, count 0 2006.217.07:54:10.90#ibcon#read 4, iclass 29, count 0 2006.217.07:54:10.90#ibcon#about to read 5, iclass 29, count 0 2006.217.07:54:10.90#ibcon#read 5, iclass 29, count 0 2006.217.07:54:10.90#ibcon#about to read 6, iclass 29, count 0 2006.217.07:54:10.90#ibcon#read 6, iclass 29, count 0 2006.217.07:54:10.90#ibcon#end of sib2, iclass 29, count 0 2006.217.07:54:10.90#ibcon#*mode == 0, iclass 29, count 0 2006.217.07:54:10.90#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.217.07:54:10.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.217.07:54:10.90#ibcon#*before write, iclass 29, count 0 2006.217.07:54:10.90#ibcon#enter sib2, iclass 29, count 0 2006.217.07:54:10.90#ibcon#flushed, iclass 29, count 0 2006.217.07:54:10.90#ibcon#about to write, iclass 29, count 0 2006.217.07:54:10.90#ibcon#wrote, iclass 29, count 0 2006.217.07:54:10.90#ibcon#about to read 3, iclass 29, count 0 2006.217.07:54:10.94#ibcon#read 3, iclass 29, count 0 2006.217.07:54:10.94#ibcon#about to read 4, iclass 29, count 0 2006.217.07:54:10.94#ibcon#read 4, iclass 29, count 0 2006.217.07:54:10.94#ibcon#about to read 5, iclass 29, count 0 2006.217.07:54:10.94#ibcon#read 5, iclass 29, count 0 2006.217.07:54:10.94#ibcon#about to read 6, iclass 29, count 0 2006.217.07:54:10.94#ibcon#read 6, iclass 29, count 0 2006.217.07:54:10.94#ibcon#end of sib2, iclass 29, count 0 2006.217.07:54:10.94#ibcon#*after write, iclass 29, count 0 2006.217.07:54:10.94#ibcon#*before return 0, iclass 29, count 0 2006.217.07:54:10.94#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.217.07:54:10.94#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.217.07:54:10.94#ibcon#about to clear, iclass 29 cls_cnt 0 2006.217.07:54:10.94#ibcon#cleared, iclass 29 cls_cnt 0 2006.217.07:54:10.94$vc4f8/vb=2,4 2006.217.07:54:10.94#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.217.07:54:10.94#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.217.07:54:10.94#ibcon#ireg 11 cls_cnt 2 2006.217.07:54:10.94#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.217.07:54:11.00#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.217.07:54:11.00#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.217.07:54:11.00#ibcon#enter wrdev, iclass 31, count 2 2006.217.07:54:11.00#ibcon#first serial, iclass 31, count 2 2006.217.07:54:11.00#ibcon#enter sib2, iclass 31, count 2 2006.217.07:54:11.00#ibcon#flushed, iclass 31, count 2 2006.217.07:54:11.00#ibcon#about to write, iclass 31, count 2 2006.217.07:54:11.00#ibcon#wrote, iclass 31, count 2 2006.217.07:54:11.00#ibcon#about to read 3, iclass 31, count 2 2006.217.07:54:11.02#ibcon#read 3, iclass 31, count 2 2006.217.07:54:11.02#ibcon#about to read 4, iclass 31, count 2 2006.217.07:54:11.02#ibcon#read 4, iclass 31, count 2 2006.217.07:54:11.02#ibcon#about to read 5, iclass 31, count 2 2006.217.07:54:11.02#ibcon#read 5, iclass 31, count 2 2006.217.07:54:11.02#ibcon#about to read 6, iclass 31, count 2 2006.217.07:54:11.02#ibcon#read 6, iclass 31, count 2 2006.217.07:54:11.02#ibcon#end of sib2, iclass 31, count 2 2006.217.07:54:11.02#ibcon#*mode == 0, iclass 31, count 2 2006.217.07:54:11.02#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.217.07:54:11.02#ibcon#[27=AT02-04\r\n] 2006.217.07:54:11.02#ibcon#*before write, iclass 31, count 2 2006.217.07:54:11.02#ibcon#enter sib2, iclass 31, count 2 2006.217.07:54:11.02#ibcon#flushed, iclass 31, count 2 2006.217.07:54:11.02#ibcon#about to write, iclass 31, count 2 2006.217.07:54:11.02#ibcon#wrote, iclass 31, count 2 2006.217.07:54:11.02#ibcon#about to read 3, iclass 31, count 2 2006.217.07:54:11.05#ibcon#read 3, iclass 31, count 2 2006.217.07:54:11.05#ibcon#about to read 4, iclass 31, count 2 2006.217.07:54:11.05#ibcon#read 4, iclass 31, count 2 2006.217.07:54:11.05#ibcon#about to read 5, iclass 31, count 2 2006.217.07:54:11.05#ibcon#read 5, iclass 31, count 2 2006.217.07:54:11.05#ibcon#about to read 6, iclass 31, count 2 2006.217.07:54:11.05#ibcon#read 6, iclass 31, count 2 2006.217.07:54:11.05#ibcon#end of sib2, iclass 31, count 2 2006.217.07:54:11.05#ibcon#*after write, iclass 31, count 2 2006.217.07:54:11.05#ibcon#*before return 0, iclass 31, count 2 2006.217.07:54:11.05#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.217.07:54:11.05#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.217.07:54:11.05#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.217.07:54:11.05#ibcon#ireg 7 cls_cnt 0 2006.217.07:54:11.05#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.217.07:54:11.17#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.217.07:54:11.17#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.217.07:54:11.17#ibcon#enter wrdev, iclass 31, count 0 2006.217.07:54:11.17#ibcon#first serial, iclass 31, count 0 2006.217.07:54:11.17#ibcon#enter sib2, iclass 31, count 0 2006.217.07:54:11.17#ibcon#flushed, iclass 31, count 0 2006.217.07:54:11.17#ibcon#about to write, iclass 31, count 0 2006.217.07:54:11.17#ibcon#wrote, iclass 31, count 0 2006.217.07:54:11.17#ibcon#about to read 3, iclass 31, count 0 2006.217.07:54:11.19#ibcon#read 3, iclass 31, count 0 2006.217.07:54:11.19#ibcon#about to read 4, iclass 31, count 0 2006.217.07:54:11.19#ibcon#read 4, iclass 31, count 0 2006.217.07:54:11.19#ibcon#about to read 5, iclass 31, count 0 2006.217.07:54:11.19#ibcon#read 5, iclass 31, count 0 2006.217.07:54:11.19#ibcon#about to read 6, iclass 31, count 0 2006.217.07:54:11.19#ibcon#read 6, iclass 31, count 0 2006.217.07:54:11.19#ibcon#end of sib2, iclass 31, count 0 2006.217.07:54:11.19#ibcon#*mode == 0, iclass 31, count 0 2006.217.07:54:11.19#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.217.07:54:11.19#ibcon#[27=USB\r\n] 2006.217.07:54:11.19#ibcon#*before write, iclass 31, count 0 2006.217.07:54:11.19#ibcon#enter sib2, iclass 31, count 0 2006.217.07:54:11.19#ibcon#flushed, iclass 31, count 0 2006.217.07:54:11.19#ibcon#about to write, iclass 31, count 0 2006.217.07:54:11.19#ibcon#wrote, iclass 31, count 0 2006.217.07:54:11.19#ibcon#about to read 3, iclass 31, count 0 2006.217.07:54:11.22#ibcon#read 3, iclass 31, count 0 2006.217.07:54:11.22#ibcon#about to read 4, iclass 31, count 0 2006.217.07:54:11.22#ibcon#read 4, iclass 31, count 0 2006.217.07:54:11.22#ibcon#about to read 5, iclass 31, count 0 2006.217.07:54:11.22#ibcon#read 5, iclass 31, count 0 2006.217.07:54:11.22#ibcon#about to read 6, iclass 31, count 0 2006.217.07:54:11.22#ibcon#read 6, iclass 31, count 0 2006.217.07:54:11.22#ibcon#end of sib2, iclass 31, count 0 2006.217.07:54:11.22#ibcon#*after write, iclass 31, count 0 2006.217.07:54:11.22#ibcon#*before return 0, iclass 31, count 0 2006.217.07:54:11.22#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.217.07:54:11.22#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.217.07:54:11.22#ibcon#about to clear, iclass 31 cls_cnt 0 2006.217.07:54:11.22#ibcon#cleared, iclass 31 cls_cnt 0 2006.217.07:54:11.22$vc4f8/vblo=3,656.99 2006.217.07:54:11.22#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.217.07:54:11.22#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.217.07:54:11.22#ibcon#ireg 17 cls_cnt 0 2006.217.07:54:11.22#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.217.07:54:11.22#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.217.07:54:11.22#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.217.07:54:11.22#ibcon#enter wrdev, iclass 33, count 0 2006.217.07:54:11.22#ibcon#first serial, iclass 33, count 0 2006.217.07:54:11.22#ibcon#enter sib2, iclass 33, count 0 2006.217.07:54:11.22#ibcon#flushed, iclass 33, count 0 2006.217.07:54:11.22#ibcon#about to write, iclass 33, count 0 2006.217.07:54:11.22#ibcon#wrote, iclass 33, count 0 2006.217.07:54:11.22#ibcon#about to read 3, iclass 33, count 0 2006.217.07:54:11.24#ibcon#read 3, iclass 33, count 0 2006.217.07:54:11.24#ibcon#about to read 4, iclass 33, count 0 2006.217.07:54:11.24#ibcon#read 4, iclass 33, count 0 2006.217.07:54:11.24#ibcon#about to read 5, iclass 33, count 0 2006.217.07:54:11.24#ibcon#read 5, iclass 33, count 0 2006.217.07:54:11.24#ibcon#about to read 6, iclass 33, count 0 2006.217.07:54:11.24#ibcon#read 6, iclass 33, count 0 2006.217.07:54:11.24#ibcon#end of sib2, iclass 33, count 0 2006.217.07:54:11.24#ibcon#*mode == 0, iclass 33, count 0 2006.217.07:54:11.24#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.217.07:54:11.24#ibcon#[28=FRQ=03,656.99\r\n] 2006.217.07:54:11.24#ibcon#*before write, iclass 33, count 0 2006.217.07:54:11.24#ibcon#enter sib2, iclass 33, count 0 2006.217.07:54:11.24#ibcon#flushed, iclass 33, count 0 2006.217.07:54:11.24#ibcon#about to write, iclass 33, count 0 2006.217.07:54:11.24#ibcon#wrote, iclass 33, count 0 2006.217.07:54:11.24#ibcon#about to read 3, iclass 33, count 0 2006.217.07:54:11.28#ibcon#read 3, iclass 33, count 0 2006.217.07:54:11.28#ibcon#about to read 4, iclass 33, count 0 2006.217.07:54:11.28#ibcon#read 4, iclass 33, count 0 2006.217.07:54:11.28#ibcon#about to read 5, iclass 33, count 0 2006.217.07:54:11.28#ibcon#read 5, iclass 33, count 0 2006.217.07:54:11.28#ibcon#about to read 6, iclass 33, count 0 2006.217.07:54:11.28#ibcon#read 6, iclass 33, count 0 2006.217.07:54:11.28#ibcon#end of sib2, iclass 33, count 0 2006.217.07:54:11.28#ibcon#*after write, iclass 33, count 0 2006.217.07:54:11.28#ibcon#*before return 0, iclass 33, count 0 2006.217.07:54:11.28#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.217.07:54:11.28#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.217.07:54:11.28#ibcon#about to clear, iclass 33 cls_cnt 0 2006.217.07:54:11.28#ibcon#cleared, iclass 33 cls_cnt 0 2006.217.07:54:11.28$vc4f8/vb=3,4 2006.217.07:54:11.28#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.217.07:54:11.28#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.217.07:54:11.28#ibcon#ireg 11 cls_cnt 2 2006.217.07:54:11.28#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.217.07:54:11.34#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.217.07:54:11.34#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.217.07:54:11.34#ibcon#enter wrdev, iclass 35, count 2 2006.217.07:54:11.34#ibcon#first serial, iclass 35, count 2 2006.217.07:54:11.34#ibcon#enter sib2, iclass 35, count 2 2006.217.07:54:11.34#ibcon#flushed, iclass 35, count 2 2006.217.07:54:11.34#ibcon#about to write, iclass 35, count 2 2006.217.07:54:11.34#ibcon#wrote, iclass 35, count 2 2006.217.07:54:11.34#ibcon#about to read 3, iclass 35, count 2 2006.217.07:54:11.36#ibcon#read 3, iclass 35, count 2 2006.217.07:54:11.36#ibcon#about to read 4, iclass 35, count 2 2006.217.07:54:11.36#ibcon#read 4, iclass 35, count 2 2006.217.07:54:11.36#ibcon#about to read 5, iclass 35, count 2 2006.217.07:54:11.36#ibcon#read 5, iclass 35, count 2 2006.217.07:54:11.36#ibcon#about to read 6, iclass 35, count 2 2006.217.07:54:11.36#ibcon#read 6, iclass 35, count 2 2006.217.07:54:11.36#ibcon#end of sib2, iclass 35, count 2 2006.217.07:54:11.36#ibcon#*mode == 0, iclass 35, count 2 2006.217.07:54:11.36#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.217.07:54:11.36#ibcon#[27=AT03-04\r\n] 2006.217.07:54:11.36#ibcon#*before write, iclass 35, count 2 2006.217.07:54:11.36#ibcon#enter sib2, iclass 35, count 2 2006.217.07:54:11.36#ibcon#flushed, iclass 35, count 2 2006.217.07:54:11.36#ibcon#about to write, iclass 35, count 2 2006.217.07:54:11.36#ibcon#wrote, iclass 35, count 2 2006.217.07:54:11.36#ibcon#about to read 3, iclass 35, count 2 2006.217.07:54:11.39#ibcon#read 3, iclass 35, count 2 2006.217.07:54:11.39#ibcon#about to read 4, iclass 35, count 2 2006.217.07:54:11.39#ibcon#read 4, iclass 35, count 2 2006.217.07:54:11.39#ibcon#about to read 5, iclass 35, count 2 2006.217.07:54:11.39#ibcon#read 5, iclass 35, count 2 2006.217.07:54:11.39#ibcon#about to read 6, iclass 35, count 2 2006.217.07:54:11.39#ibcon#read 6, iclass 35, count 2 2006.217.07:54:11.39#ibcon#end of sib2, iclass 35, count 2 2006.217.07:54:11.39#ibcon#*after write, iclass 35, count 2 2006.217.07:54:11.39#ibcon#*before return 0, iclass 35, count 2 2006.217.07:54:11.39#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.217.07:54:11.39#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.217.07:54:11.39#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.217.07:54:11.39#ibcon#ireg 7 cls_cnt 0 2006.217.07:54:11.39#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.217.07:54:11.51#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.217.07:54:11.51#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.217.07:54:11.51#ibcon#enter wrdev, iclass 35, count 0 2006.217.07:54:11.51#ibcon#first serial, iclass 35, count 0 2006.217.07:54:11.51#ibcon#enter sib2, iclass 35, count 0 2006.217.07:54:11.51#ibcon#flushed, iclass 35, count 0 2006.217.07:54:11.51#ibcon#about to write, iclass 35, count 0 2006.217.07:54:11.51#ibcon#wrote, iclass 35, count 0 2006.217.07:54:11.51#ibcon#about to read 3, iclass 35, count 0 2006.217.07:54:11.53#ibcon#read 3, iclass 35, count 0 2006.217.07:54:11.53#ibcon#about to read 4, iclass 35, count 0 2006.217.07:54:11.53#ibcon#read 4, iclass 35, count 0 2006.217.07:54:11.53#ibcon#about to read 5, iclass 35, count 0 2006.217.07:54:11.53#ibcon#read 5, iclass 35, count 0 2006.217.07:54:11.53#ibcon#about to read 6, iclass 35, count 0 2006.217.07:54:11.53#ibcon#read 6, iclass 35, count 0 2006.217.07:54:11.53#ibcon#end of sib2, iclass 35, count 0 2006.217.07:54:11.53#ibcon#*mode == 0, iclass 35, count 0 2006.217.07:54:11.53#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.217.07:54:11.53#ibcon#[27=USB\r\n] 2006.217.07:54:11.53#ibcon#*before write, iclass 35, count 0 2006.217.07:54:11.53#ibcon#enter sib2, iclass 35, count 0 2006.217.07:54:11.53#ibcon#flushed, iclass 35, count 0 2006.217.07:54:11.53#ibcon#about to write, iclass 35, count 0 2006.217.07:54:11.53#ibcon#wrote, iclass 35, count 0 2006.217.07:54:11.53#ibcon#about to read 3, iclass 35, count 0 2006.217.07:54:11.56#ibcon#read 3, iclass 35, count 0 2006.217.07:54:11.56#ibcon#about to read 4, iclass 35, count 0 2006.217.07:54:11.56#ibcon#read 4, iclass 35, count 0 2006.217.07:54:11.56#ibcon#about to read 5, iclass 35, count 0 2006.217.07:54:11.56#ibcon#read 5, iclass 35, count 0 2006.217.07:54:11.56#ibcon#about to read 6, iclass 35, count 0 2006.217.07:54:11.56#ibcon#read 6, iclass 35, count 0 2006.217.07:54:11.56#ibcon#end of sib2, iclass 35, count 0 2006.217.07:54:11.56#ibcon#*after write, iclass 35, count 0 2006.217.07:54:11.56#ibcon#*before return 0, iclass 35, count 0 2006.217.07:54:11.56#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.217.07:54:11.56#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.217.07:54:11.56#ibcon#about to clear, iclass 35 cls_cnt 0 2006.217.07:54:11.56#ibcon#cleared, iclass 35 cls_cnt 0 2006.217.07:54:11.56$vc4f8/vblo=4,712.99 2006.217.07:54:11.56#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.217.07:54:11.56#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.217.07:54:11.56#ibcon#ireg 17 cls_cnt 0 2006.217.07:54:11.56#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.217.07:54:11.56#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.217.07:54:11.56#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.217.07:54:11.56#ibcon#enter wrdev, iclass 37, count 0 2006.217.07:54:11.56#ibcon#first serial, iclass 37, count 0 2006.217.07:54:11.56#ibcon#enter sib2, iclass 37, count 0 2006.217.07:54:11.56#ibcon#flushed, iclass 37, count 0 2006.217.07:54:11.56#ibcon#about to write, iclass 37, count 0 2006.217.07:54:11.56#ibcon#wrote, iclass 37, count 0 2006.217.07:54:11.56#ibcon#about to read 3, iclass 37, count 0 2006.217.07:54:11.58#ibcon#read 3, iclass 37, count 0 2006.217.07:54:11.58#ibcon#about to read 4, iclass 37, count 0 2006.217.07:54:11.58#ibcon#read 4, iclass 37, count 0 2006.217.07:54:11.58#ibcon#about to read 5, iclass 37, count 0 2006.217.07:54:11.58#ibcon#read 5, iclass 37, count 0 2006.217.07:54:11.58#ibcon#about to read 6, iclass 37, count 0 2006.217.07:54:11.58#ibcon#read 6, iclass 37, count 0 2006.217.07:54:11.58#ibcon#end of sib2, iclass 37, count 0 2006.217.07:54:11.58#ibcon#*mode == 0, iclass 37, count 0 2006.217.07:54:11.58#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.217.07:54:11.58#ibcon#[28=FRQ=04,712.99\r\n] 2006.217.07:54:11.58#ibcon#*before write, iclass 37, count 0 2006.217.07:54:11.58#ibcon#enter sib2, iclass 37, count 0 2006.217.07:54:11.58#ibcon#flushed, iclass 37, count 0 2006.217.07:54:11.58#ibcon#about to write, iclass 37, count 0 2006.217.07:54:11.58#ibcon#wrote, iclass 37, count 0 2006.217.07:54:11.58#ibcon#about to read 3, iclass 37, count 0 2006.217.07:54:11.62#ibcon#read 3, iclass 37, count 0 2006.217.07:54:11.62#ibcon#about to read 4, iclass 37, count 0 2006.217.07:54:11.62#ibcon#read 4, iclass 37, count 0 2006.217.07:54:11.62#ibcon#about to read 5, iclass 37, count 0 2006.217.07:54:11.62#ibcon#read 5, iclass 37, count 0 2006.217.07:54:11.62#ibcon#about to read 6, iclass 37, count 0 2006.217.07:54:11.62#ibcon#read 6, iclass 37, count 0 2006.217.07:54:11.62#ibcon#end of sib2, iclass 37, count 0 2006.217.07:54:11.62#ibcon#*after write, iclass 37, count 0 2006.217.07:54:11.62#ibcon#*before return 0, iclass 37, count 0 2006.217.07:54:11.62#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.217.07:54:11.62#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.217.07:54:11.62#ibcon#about to clear, iclass 37 cls_cnt 0 2006.217.07:54:11.62#ibcon#cleared, iclass 37 cls_cnt 0 2006.217.07:54:11.62$vc4f8/vb=4,4 2006.217.07:54:11.62#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.217.07:54:11.62#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.217.07:54:11.62#ibcon#ireg 11 cls_cnt 2 2006.217.07:54:11.62#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.217.07:54:11.68#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.217.07:54:11.68#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.217.07:54:11.68#ibcon#enter wrdev, iclass 39, count 2 2006.217.07:54:11.68#ibcon#first serial, iclass 39, count 2 2006.217.07:54:11.68#ibcon#enter sib2, iclass 39, count 2 2006.217.07:54:11.68#ibcon#flushed, iclass 39, count 2 2006.217.07:54:11.68#ibcon#about to write, iclass 39, count 2 2006.217.07:54:11.68#ibcon#wrote, iclass 39, count 2 2006.217.07:54:11.68#ibcon#about to read 3, iclass 39, count 2 2006.217.07:54:11.70#ibcon#read 3, iclass 39, count 2 2006.217.07:54:11.70#ibcon#about to read 4, iclass 39, count 2 2006.217.07:54:11.70#ibcon#read 4, iclass 39, count 2 2006.217.07:54:11.70#ibcon#about to read 5, iclass 39, count 2 2006.217.07:54:11.70#ibcon#read 5, iclass 39, count 2 2006.217.07:54:11.70#ibcon#about to read 6, iclass 39, count 2 2006.217.07:54:11.70#ibcon#read 6, iclass 39, count 2 2006.217.07:54:11.70#ibcon#end of sib2, iclass 39, count 2 2006.217.07:54:11.70#ibcon#*mode == 0, iclass 39, count 2 2006.217.07:54:11.70#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.217.07:54:11.70#ibcon#[27=AT04-04\r\n] 2006.217.07:54:11.70#ibcon#*before write, iclass 39, count 2 2006.217.07:54:11.70#ibcon#enter sib2, iclass 39, count 2 2006.217.07:54:11.70#ibcon#flushed, iclass 39, count 2 2006.217.07:54:11.70#ibcon#about to write, iclass 39, count 2 2006.217.07:54:11.70#ibcon#wrote, iclass 39, count 2 2006.217.07:54:11.70#ibcon#about to read 3, iclass 39, count 2 2006.217.07:54:11.73#ibcon#read 3, iclass 39, count 2 2006.217.07:54:11.73#ibcon#about to read 4, iclass 39, count 2 2006.217.07:54:11.73#ibcon#read 4, iclass 39, count 2 2006.217.07:54:11.73#ibcon#about to read 5, iclass 39, count 2 2006.217.07:54:11.73#ibcon#read 5, iclass 39, count 2 2006.217.07:54:11.73#ibcon#about to read 6, iclass 39, count 2 2006.217.07:54:11.73#ibcon#read 6, iclass 39, count 2 2006.217.07:54:11.73#ibcon#end of sib2, iclass 39, count 2 2006.217.07:54:11.73#ibcon#*after write, iclass 39, count 2 2006.217.07:54:11.73#ibcon#*before return 0, iclass 39, count 2 2006.217.07:54:11.73#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.217.07:54:11.73#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.217.07:54:11.73#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.217.07:54:11.73#ibcon#ireg 7 cls_cnt 0 2006.217.07:54:11.73#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.217.07:54:11.85#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.217.07:54:11.85#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.217.07:54:11.85#ibcon#enter wrdev, iclass 39, count 0 2006.217.07:54:11.85#ibcon#first serial, iclass 39, count 0 2006.217.07:54:11.85#ibcon#enter sib2, iclass 39, count 0 2006.217.07:54:11.85#ibcon#flushed, iclass 39, count 0 2006.217.07:54:11.85#ibcon#about to write, iclass 39, count 0 2006.217.07:54:11.85#ibcon#wrote, iclass 39, count 0 2006.217.07:54:11.85#ibcon#about to read 3, iclass 39, count 0 2006.217.07:54:11.87#ibcon#read 3, iclass 39, count 0 2006.217.07:54:11.87#ibcon#about to read 4, iclass 39, count 0 2006.217.07:54:11.87#ibcon#read 4, iclass 39, count 0 2006.217.07:54:11.87#ibcon#about to read 5, iclass 39, count 0 2006.217.07:54:11.87#ibcon#read 5, iclass 39, count 0 2006.217.07:54:11.87#ibcon#about to read 6, iclass 39, count 0 2006.217.07:54:11.87#ibcon#read 6, iclass 39, count 0 2006.217.07:54:11.87#ibcon#end of sib2, iclass 39, count 0 2006.217.07:54:11.87#ibcon#*mode == 0, iclass 39, count 0 2006.217.07:54:11.87#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.217.07:54:11.87#ibcon#[27=USB\r\n] 2006.217.07:54:11.87#ibcon#*before write, iclass 39, count 0 2006.217.07:54:11.87#ibcon#enter sib2, iclass 39, count 0 2006.217.07:54:11.87#ibcon#flushed, iclass 39, count 0 2006.217.07:54:11.87#ibcon#about to write, iclass 39, count 0 2006.217.07:54:11.87#ibcon#wrote, iclass 39, count 0 2006.217.07:54:11.87#ibcon#about to read 3, iclass 39, count 0 2006.217.07:54:11.90#ibcon#read 3, iclass 39, count 0 2006.217.07:54:11.90#ibcon#about to read 4, iclass 39, count 0 2006.217.07:54:11.90#ibcon#read 4, iclass 39, count 0 2006.217.07:54:11.90#ibcon#about to read 5, iclass 39, count 0 2006.217.07:54:11.90#ibcon#read 5, iclass 39, count 0 2006.217.07:54:11.90#ibcon#about to read 6, iclass 39, count 0 2006.217.07:54:11.90#ibcon#read 6, iclass 39, count 0 2006.217.07:54:11.90#ibcon#end of sib2, iclass 39, count 0 2006.217.07:54:11.90#ibcon#*after write, iclass 39, count 0 2006.217.07:54:11.90#ibcon#*before return 0, iclass 39, count 0 2006.217.07:54:11.90#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.217.07:54:11.90#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.217.07:54:11.90#ibcon#about to clear, iclass 39 cls_cnt 0 2006.217.07:54:11.90#ibcon#cleared, iclass 39 cls_cnt 0 2006.217.07:54:11.90$vc4f8/vblo=5,744.99 2006.217.07:54:11.90#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.217.07:54:11.90#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.217.07:54:11.90#ibcon#ireg 17 cls_cnt 0 2006.217.07:54:11.90#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.217.07:54:11.90#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.217.07:54:11.90#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.217.07:54:11.90#ibcon#enter wrdev, iclass 3, count 0 2006.217.07:54:11.90#ibcon#first serial, iclass 3, count 0 2006.217.07:54:11.90#ibcon#enter sib2, iclass 3, count 0 2006.217.07:54:11.90#ibcon#flushed, iclass 3, count 0 2006.217.07:54:11.90#ibcon#about to write, iclass 3, count 0 2006.217.07:54:11.90#ibcon#wrote, iclass 3, count 0 2006.217.07:54:11.90#ibcon#about to read 3, iclass 3, count 0 2006.217.07:54:11.92#ibcon#read 3, iclass 3, count 0 2006.217.07:54:11.92#ibcon#about to read 4, iclass 3, count 0 2006.217.07:54:11.92#ibcon#read 4, iclass 3, count 0 2006.217.07:54:11.92#ibcon#about to read 5, iclass 3, count 0 2006.217.07:54:11.92#ibcon#read 5, iclass 3, count 0 2006.217.07:54:11.92#ibcon#about to read 6, iclass 3, count 0 2006.217.07:54:11.92#ibcon#read 6, iclass 3, count 0 2006.217.07:54:11.92#ibcon#end of sib2, iclass 3, count 0 2006.217.07:54:11.92#ibcon#*mode == 0, iclass 3, count 0 2006.217.07:54:11.92#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.217.07:54:11.92#ibcon#[28=FRQ=05,744.99\r\n] 2006.217.07:54:11.92#ibcon#*before write, iclass 3, count 0 2006.217.07:54:11.92#ibcon#enter sib2, iclass 3, count 0 2006.217.07:54:11.92#ibcon#flushed, iclass 3, count 0 2006.217.07:54:11.92#ibcon#about to write, iclass 3, count 0 2006.217.07:54:11.92#ibcon#wrote, iclass 3, count 0 2006.217.07:54:11.92#ibcon#about to read 3, iclass 3, count 0 2006.217.07:54:11.96#ibcon#read 3, iclass 3, count 0 2006.217.07:54:11.96#ibcon#about to read 4, iclass 3, count 0 2006.217.07:54:11.96#ibcon#read 4, iclass 3, count 0 2006.217.07:54:11.96#ibcon#about to read 5, iclass 3, count 0 2006.217.07:54:11.96#ibcon#read 5, iclass 3, count 0 2006.217.07:54:11.96#ibcon#about to read 6, iclass 3, count 0 2006.217.07:54:11.96#ibcon#read 6, iclass 3, count 0 2006.217.07:54:11.96#ibcon#end of sib2, iclass 3, count 0 2006.217.07:54:11.96#ibcon#*after write, iclass 3, count 0 2006.217.07:54:11.96#ibcon#*before return 0, iclass 3, count 0 2006.217.07:54:11.96#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.217.07:54:11.96#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.217.07:54:11.96#ibcon#about to clear, iclass 3 cls_cnt 0 2006.217.07:54:11.96#ibcon#cleared, iclass 3 cls_cnt 0 2006.217.07:54:11.96$vc4f8/vb=5,4 2006.217.07:54:11.96#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.217.07:54:11.96#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.217.07:54:11.96#ibcon#ireg 11 cls_cnt 2 2006.217.07:54:11.96#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.217.07:54:12.02#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.217.07:54:12.02#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.217.07:54:12.02#ibcon#enter wrdev, iclass 5, count 2 2006.217.07:54:12.02#ibcon#first serial, iclass 5, count 2 2006.217.07:54:12.02#ibcon#enter sib2, iclass 5, count 2 2006.217.07:54:12.02#ibcon#flushed, iclass 5, count 2 2006.217.07:54:12.02#ibcon#about to write, iclass 5, count 2 2006.217.07:54:12.02#ibcon#wrote, iclass 5, count 2 2006.217.07:54:12.02#ibcon#about to read 3, iclass 5, count 2 2006.217.07:54:12.04#ibcon#read 3, iclass 5, count 2 2006.217.07:54:12.04#ibcon#about to read 4, iclass 5, count 2 2006.217.07:54:12.04#ibcon#read 4, iclass 5, count 2 2006.217.07:54:12.04#ibcon#about to read 5, iclass 5, count 2 2006.217.07:54:12.04#ibcon#read 5, iclass 5, count 2 2006.217.07:54:12.04#ibcon#about to read 6, iclass 5, count 2 2006.217.07:54:12.04#ibcon#read 6, iclass 5, count 2 2006.217.07:54:12.04#ibcon#end of sib2, iclass 5, count 2 2006.217.07:54:12.04#ibcon#*mode == 0, iclass 5, count 2 2006.217.07:54:12.04#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.217.07:54:12.04#ibcon#[27=AT05-04\r\n] 2006.217.07:54:12.04#ibcon#*before write, iclass 5, count 2 2006.217.07:54:12.04#ibcon#enter sib2, iclass 5, count 2 2006.217.07:54:12.04#ibcon#flushed, iclass 5, count 2 2006.217.07:54:12.04#ibcon#about to write, iclass 5, count 2 2006.217.07:54:12.04#ibcon#wrote, iclass 5, count 2 2006.217.07:54:12.04#ibcon#about to read 3, iclass 5, count 2 2006.217.07:54:12.07#ibcon#read 3, iclass 5, count 2 2006.217.07:54:12.07#ibcon#about to read 4, iclass 5, count 2 2006.217.07:54:12.07#ibcon#read 4, iclass 5, count 2 2006.217.07:54:12.07#ibcon#about to read 5, iclass 5, count 2 2006.217.07:54:12.07#ibcon#read 5, iclass 5, count 2 2006.217.07:54:12.07#ibcon#about to read 6, iclass 5, count 2 2006.217.07:54:12.07#ibcon#read 6, iclass 5, count 2 2006.217.07:54:12.07#ibcon#end of sib2, iclass 5, count 2 2006.217.07:54:12.07#ibcon#*after write, iclass 5, count 2 2006.217.07:54:12.07#ibcon#*before return 0, iclass 5, count 2 2006.217.07:54:12.07#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.217.07:54:12.07#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.217.07:54:12.07#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.217.07:54:12.07#ibcon#ireg 7 cls_cnt 0 2006.217.07:54:12.07#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.217.07:54:12.19#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.217.07:54:12.19#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.217.07:54:12.19#ibcon#enter wrdev, iclass 5, count 0 2006.217.07:54:12.19#ibcon#first serial, iclass 5, count 0 2006.217.07:54:12.19#ibcon#enter sib2, iclass 5, count 0 2006.217.07:54:12.19#ibcon#flushed, iclass 5, count 0 2006.217.07:54:12.19#ibcon#about to write, iclass 5, count 0 2006.217.07:54:12.19#ibcon#wrote, iclass 5, count 0 2006.217.07:54:12.19#ibcon#about to read 3, iclass 5, count 0 2006.217.07:54:12.21#ibcon#read 3, iclass 5, count 0 2006.217.07:54:12.21#ibcon#about to read 4, iclass 5, count 0 2006.217.07:54:12.21#ibcon#read 4, iclass 5, count 0 2006.217.07:54:12.21#ibcon#about to read 5, iclass 5, count 0 2006.217.07:54:12.21#ibcon#read 5, iclass 5, count 0 2006.217.07:54:12.21#ibcon#about to read 6, iclass 5, count 0 2006.217.07:54:12.21#ibcon#read 6, iclass 5, count 0 2006.217.07:54:12.21#ibcon#end of sib2, iclass 5, count 0 2006.217.07:54:12.21#ibcon#*mode == 0, iclass 5, count 0 2006.217.07:54:12.21#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.217.07:54:12.21#ibcon#[27=USB\r\n] 2006.217.07:54:12.21#ibcon#*before write, iclass 5, count 0 2006.217.07:54:12.21#ibcon#enter sib2, iclass 5, count 0 2006.217.07:54:12.21#ibcon#flushed, iclass 5, count 0 2006.217.07:54:12.21#ibcon#about to write, iclass 5, count 0 2006.217.07:54:12.21#ibcon#wrote, iclass 5, count 0 2006.217.07:54:12.21#ibcon#about to read 3, iclass 5, count 0 2006.217.07:54:12.24#ibcon#read 3, iclass 5, count 0 2006.217.07:54:12.24#ibcon#about to read 4, iclass 5, count 0 2006.217.07:54:12.24#ibcon#read 4, iclass 5, count 0 2006.217.07:54:12.24#ibcon#about to read 5, iclass 5, count 0 2006.217.07:54:12.24#ibcon#read 5, iclass 5, count 0 2006.217.07:54:12.24#ibcon#about to read 6, iclass 5, count 0 2006.217.07:54:12.24#ibcon#read 6, iclass 5, count 0 2006.217.07:54:12.24#ibcon#end of sib2, iclass 5, count 0 2006.217.07:54:12.24#ibcon#*after write, iclass 5, count 0 2006.217.07:54:12.24#ibcon#*before return 0, iclass 5, count 0 2006.217.07:54:12.24#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.217.07:54:12.24#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.217.07:54:12.24#ibcon#about to clear, iclass 5 cls_cnt 0 2006.217.07:54:12.24#ibcon#cleared, iclass 5 cls_cnt 0 2006.217.07:54:12.24$vc4f8/vblo=6,752.99 2006.217.07:54:12.24#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.217.07:54:12.24#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.217.07:54:12.24#ibcon#ireg 17 cls_cnt 0 2006.217.07:54:12.24#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.217.07:54:12.24#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.217.07:54:12.24#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.217.07:54:12.24#ibcon#enter wrdev, iclass 7, count 0 2006.217.07:54:12.24#ibcon#first serial, iclass 7, count 0 2006.217.07:54:12.24#ibcon#enter sib2, iclass 7, count 0 2006.217.07:54:12.24#ibcon#flushed, iclass 7, count 0 2006.217.07:54:12.24#ibcon#about to write, iclass 7, count 0 2006.217.07:54:12.24#ibcon#wrote, iclass 7, count 0 2006.217.07:54:12.24#ibcon#about to read 3, iclass 7, count 0 2006.217.07:54:12.26#ibcon#read 3, iclass 7, count 0 2006.217.07:54:12.26#ibcon#about to read 4, iclass 7, count 0 2006.217.07:54:12.26#ibcon#read 4, iclass 7, count 0 2006.217.07:54:12.26#ibcon#about to read 5, iclass 7, count 0 2006.217.07:54:12.26#ibcon#read 5, iclass 7, count 0 2006.217.07:54:12.26#ibcon#about to read 6, iclass 7, count 0 2006.217.07:54:12.26#ibcon#read 6, iclass 7, count 0 2006.217.07:54:12.26#ibcon#end of sib2, iclass 7, count 0 2006.217.07:54:12.26#ibcon#*mode == 0, iclass 7, count 0 2006.217.07:54:12.26#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.217.07:54:12.26#ibcon#[28=FRQ=06,752.99\r\n] 2006.217.07:54:12.26#ibcon#*before write, iclass 7, count 0 2006.217.07:54:12.26#ibcon#enter sib2, iclass 7, count 0 2006.217.07:54:12.26#ibcon#flushed, iclass 7, count 0 2006.217.07:54:12.26#ibcon#about to write, iclass 7, count 0 2006.217.07:54:12.26#ibcon#wrote, iclass 7, count 0 2006.217.07:54:12.26#ibcon#about to read 3, iclass 7, count 0 2006.217.07:54:12.30#ibcon#read 3, iclass 7, count 0 2006.217.07:54:12.30#ibcon#about to read 4, iclass 7, count 0 2006.217.07:54:12.30#ibcon#read 4, iclass 7, count 0 2006.217.07:54:12.30#ibcon#about to read 5, iclass 7, count 0 2006.217.07:54:12.30#ibcon#read 5, iclass 7, count 0 2006.217.07:54:12.30#ibcon#about to read 6, iclass 7, count 0 2006.217.07:54:12.30#ibcon#read 6, iclass 7, count 0 2006.217.07:54:12.30#ibcon#end of sib2, iclass 7, count 0 2006.217.07:54:12.30#ibcon#*after write, iclass 7, count 0 2006.217.07:54:12.30#ibcon#*before return 0, iclass 7, count 0 2006.217.07:54:12.30#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.217.07:54:12.30#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.217.07:54:12.30#ibcon#about to clear, iclass 7 cls_cnt 0 2006.217.07:54:12.30#ibcon#cleared, iclass 7 cls_cnt 0 2006.217.07:54:12.30$vc4f8/vb=6,4 2006.217.07:54:12.30#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.217.07:54:12.30#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.217.07:54:12.30#ibcon#ireg 11 cls_cnt 2 2006.217.07:54:12.30#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.217.07:54:12.36#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.217.07:54:12.36#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.217.07:54:12.36#ibcon#enter wrdev, iclass 11, count 2 2006.217.07:54:12.36#ibcon#first serial, iclass 11, count 2 2006.217.07:54:12.36#ibcon#enter sib2, iclass 11, count 2 2006.217.07:54:12.36#ibcon#flushed, iclass 11, count 2 2006.217.07:54:12.36#ibcon#about to write, iclass 11, count 2 2006.217.07:54:12.36#ibcon#wrote, iclass 11, count 2 2006.217.07:54:12.36#ibcon#about to read 3, iclass 11, count 2 2006.217.07:54:12.38#ibcon#read 3, iclass 11, count 2 2006.217.07:54:12.38#ibcon#about to read 4, iclass 11, count 2 2006.217.07:54:12.38#ibcon#read 4, iclass 11, count 2 2006.217.07:54:12.38#ibcon#about to read 5, iclass 11, count 2 2006.217.07:54:12.38#ibcon#read 5, iclass 11, count 2 2006.217.07:54:12.38#ibcon#about to read 6, iclass 11, count 2 2006.217.07:54:12.38#ibcon#read 6, iclass 11, count 2 2006.217.07:54:12.38#ibcon#end of sib2, iclass 11, count 2 2006.217.07:54:12.38#ibcon#*mode == 0, iclass 11, count 2 2006.217.07:54:12.38#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.217.07:54:12.38#ibcon#[27=AT06-04\r\n] 2006.217.07:54:12.38#ibcon#*before write, iclass 11, count 2 2006.217.07:54:12.38#ibcon#enter sib2, iclass 11, count 2 2006.217.07:54:12.38#ibcon#flushed, iclass 11, count 2 2006.217.07:54:12.38#ibcon#about to write, iclass 11, count 2 2006.217.07:54:12.38#ibcon#wrote, iclass 11, count 2 2006.217.07:54:12.38#ibcon#about to read 3, iclass 11, count 2 2006.217.07:54:12.41#ibcon#read 3, iclass 11, count 2 2006.217.07:54:12.41#ibcon#about to read 4, iclass 11, count 2 2006.217.07:54:12.41#ibcon#read 4, iclass 11, count 2 2006.217.07:54:12.41#ibcon#about to read 5, iclass 11, count 2 2006.217.07:54:12.41#ibcon#read 5, iclass 11, count 2 2006.217.07:54:12.41#ibcon#about to read 6, iclass 11, count 2 2006.217.07:54:12.41#ibcon#read 6, iclass 11, count 2 2006.217.07:54:12.41#ibcon#end of sib2, iclass 11, count 2 2006.217.07:54:12.41#ibcon#*after write, iclass 11, count 2 2006.217.07:54:12.41#ibcon#*before return 0, iclass 11, count 2 2006.217.07:54:12.41#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.217.07:54:12.41#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.217.07:54:12.41#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.217.07:54:12.41#ibcon#ireg 7 cls_cnt 0 2006.217.07:54:12.41#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.217.07:54:12.53#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.217.07:54:12.53#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.217.07:54:12.53#ibcon#enter wrdev, iclass 11, count 0 2006.217.07:54:12.53#ibcon#first serial, iclass 11, count 0 2006.217.07:54:12.53#ibcon#enter sib2, iclass 11, count 0 2006.217.07:54:12.53#ibcon#flushed, iclass 11, count 0 2006.217.07:54:12.53#ibcon#about to write, iclass 11, count 0 2006.217.07:54:12.53#ibcon#wrote, iclass 11, count 0 2006.217.07:54:12.53#ibcon#about to read 3, iclass 11, count 0 2006.217.07:54:12.55#ibcon#read 3, iclass 11, count 0 2006.217.07:54:12.55#ibcon#about to read 4, iclass 11, count 0 2006.217.07:54:12.55#ibcon#read 4, iclass 11, count 0 2006.217.07:54:12.55#ibcon#about to read 5, iclass 11, count 0 2006.217.07:54:12.55#ibcon#read 5, iclass 11, count 0 2006.217.07:54:12.55#ibcon#about to read 6, iclass 11, count 0 2006.217.07:54:12.55#ibcon#read 6, iclass 11, count 0 2006.217.07:54:12.55#ibcon#end of sib2, iclass 11, count 0 2006.217.07:54:12.55#ibcon#*mode == 0, iclass 11, count 0 2006.217.07:54:12.55#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.217.07:54:12.55#ibcon#[27=USB\r\n] 2006.217.07:54:12.55#ibcon#*before write, iclass 11, count 0 2006.217.07:54:12.55#ibcon#enter sib2, iclass 11, count 0 2006.217.07:54:12.55#ibcon#flushed, iclass 11, count 0 2006.217.07:54:12.55#ibcon#about to write, iclass 11, count 0 2006.217.07:54:12.55#ibcon#wrote, iclass 11, count 0 2006.217.07:54:12.55#ibcon#about to read 3, iclass 11, count 0 2006.217.07:54:12.58#ibcon#read 3, iclass 11, count 0 2006.217.07:54:12.58#ibcon#about to read 4, iclass 11, count 0 2006.217.07:54:12.58#ibcon#read 4, iclass 11, count 0 2006.217.07:54:12.58#ibcon#about to read 5, iclass 11, count 0 2006.217.07:54:12.58#ibcon#read 5, iclass 11, count 0 2006.217.07:54:12.58#ibcon#about to read 6, iclass 11, count 0 2006.217.07:54:12.58#ibcon#read 6, iclass 11, count 0 2006.217.07:54:12.58#ibcon#end of sib2, iclass 11, count 0 2006.217.07:54:12.58#ibcon#*after write, iclass 11, count 0 2006.217.07:54:12.58#ibcon#*before return 0, iclass 11, count 0 2006.217.07:54:12.58#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.217.07:54:12.58#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.217.07:54:12.58#ibcon#about to clear, iclass 11 cls_cnt 0 2006.217.07:54:12.58#ibcon#cleared, iclass 11 cls_cnt 0 2006.217.07:54:12.58$vc4f8/vabw=wide 2006.217.07:54:12.58#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.217.07:54:12.58#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.217.07:54:12.58#ibcon#ireg 8 cls_cnt 0 2006.217.07:54:12.58#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.217.07:54:12.58#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.217.07:54:12.58#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.217.07:54:12.58#ibcon#enter wrdev, iclass 13, count 0 2006.217.07:54:12.58#ibcon#first serial, iclass 13, count 0 2006.217.07:54:12.58#ibcon#enter sib2, iclass 13, count 0 2006.217.07:54:12.58#ibcon#flushed, iclass 13, count 0 2006.217.07:54:12.58#ibcon#about to write, iclass 13, count 0 2006.217.07:54:12.58#ibcon#wrote, iclass 13, count 0 2006.217.07:54:12.58#ibcon#about to read 3, iclass 13, count 0 2006.217.07:54:12.60#ibcon#read 3, iclass 13, count 0 2006.217.07:54:12.60#ibcon#about to read 4, iclass 13, count 0 2006.217.07:54:12.60#ibcon#read 4, iclass 13, count 0 2006.217.07:54:12.60#ibcon#about to read 5, iclass 13, count 0 2006.217.07:54:12.60#ibcon#read 5, iclass 13, count 0 2006.217.07:54:12.60#ibcon#about to read 6, iclass 13, count 0 2006.217.07:54:12.60#ibcon#read 6, iclass 13, count 0 2006.217.07:54:12.60#ibcon#end of sib2, iclass 13, count 0 2006.217.07:54:12.60#ibcon#*mode == 0, iclass 13, count 0 2006.217.07:54:12.60#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.217.07:54:12.60#ibcon#[25=BW32\r\n] 2006.217.07:54:12.60#ibcon#*before write, iclass 13, count 0 2006.217.07:54:12.60#ibcon#enter sib2, iclass 13, count 0 2006.217.07:54:12.60#ibcon#flushed, iclass 13, count 0 2006.217.07:54:12.60#ibcon#about to write, iclass 13, count 0 2006.217.07:54:12.60#ibcon#wrote, iclass 13, count 0 2006.217.07:54:12.60#ibcon#about to read 3, iclass 13, count 0 2006.217.07:54:12.63#ibcon#read 3, iclass 13, count 0 2006.217.07:54:12.63#ibcon#about to read 4, iclass 13, count 0 2006.217.07:54:12.63#ibcon#read 4, iclass 13, count 0 2006.217.07:54:12.63#ibcon#about to read 5, iclass 13, count 0 2006.217.07:54:12.63#ibcon#read 5, iclass 13, count 0 2006.217.07:54:12.63#ibcon#about to read 6, iclass 13, count 0 2006.217.07:54:12.63#ibcon#read 6, iclass 13, count 0 2006.217.07:54:12.63#ibcon#end of sib2, iclass 13, count 0 2006.217.07:54:12.63#ibcon#*after write, iclass 13, count 0 2006.217.07:54:12.63#ibcon#*before return 0, iclass 13, count 0 2006.217.07:54:12.63#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.217.07:54:12.63#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.217.07:54:12.63#ibcon#about to clear, iclass 13 cls_cnt 0 2006.217.07:54:12.63#ibcon#cleared, iclass 13 cls_cnt 0 2006.217.07:54:12.63$vc4f8/vbbw=wide 2006.217.07:54:12.63#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.217.07:54:12.63#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.217.07:54:12.63#ibcon#ireg 8 cls_cnt 0 2006.217.07:54:12.63#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.217.07:54:12.70#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.217.07:54:12.70#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.217.07:54:12.70#ibcon#enter wrdev, iclass 15, count 0 2006.217.07:54:12.70#ibcon#first serial, iclass 15, count 0 2006.217.07:54:12.70#ibcon#enter sib2, iclass 15, count 0 2006.217.07:54:12.70#ibcon#flushed, iclass 15, count 0 2006.217.07:54:12.70#ibcon#about to write, iclass 15, count 0 2006.217.07:54:12.70#ibcon#wrote, iclass 15, count 0 2006.217.07:54:12.70#ibcon#about to read 3, iclass 15, count 0 2006.217.07:54:12.72#ibcon#read 3, iclass 15, count 0 2006.217.07:54:12.72#ibcon#about to read 4, iclass 15, count 0 2006.217.07:54:12.72#ibcon#read 4, iclass 15, count 0 2006.217.07:54:12.72#ibcon#about to read 5, iclass 15, count 0 2006.217.07:54:12.72#ibcon#read 5, iclass 15, count 0 2006.217.07:54:12.72#ibcon#about to read 6, iclass 15, count 0 2006.217.07:54:12.72#ibcon#read 6, iclass 15, count 0 2006.217.07:54:12.72#ibcon#end of sib2, iclass 15, count 0 2006.217.07:54:12.72#ibcon#*mode == 0, iclass 15, count 0 2006.217.07:54:12.72#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.217.07:54:12.72#ibcon#[27=BW32\r\n] 2006.217.07:54:12.72#ibcon#*before write, iclass 15, count 0 2006.217.07:54:12.72#ibcon#enter sib2, iclass 15, count 0 2006.217.07:54:12.72#ibcon#flushed, iclass 15, count 0 2006.217.07:54:12.72#ibcon#about to write, iclass 15, count 0 2006.217.07:54:12.72#ibcon#wrote, iclass 15, count 0 2006.217.07:54:12.72#ibcon#about to read 3, iclass 15, count 0 2006.217.07:54:12.75#ibcon#read 3, iclass 15, count 0 2006.217.07:54:12.75#ibcon#about to read 4, iclass 15, count 0 2006.217.07:54:12.75#ibcon#read 4, iclass 15, count 0 2006.217.07:54:12.75#ibcon#about to read 5, iclass 15, count 0 2006.217.07:54:12.75#ibcon#read 5, iclass 15, count 0 2006.217.07:54:12.75#ibcon#about to read 6, iclass 15, count 0 2006.217.07:54:12.75#ibcon#read 6, iclass 15, count 0 2006.217.07:54:12.75#ibcon#end of sib2, iclass 15, count 0 2006.217.07:54:12.75#ibcon#*after write, iclass 15, count 0 2006.217.07:54:12.75#ibcon#*before return 0, iclass 15, count 0 2006.217.07:54:12.75#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.217.07:54:12.75#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.217.07:54:12.75#ibcon#about to clear, iclass 15 cls_cnt 0 2006.217.07:54:12.75#ibcon#cleared, iclass 15 cls_cnt 0 2006.217.07:54:12.75$4f8m12a/ifd4f 2006.217.07:54:12.75$ifd4f/lo= 2006.217.07:54:12.75$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.217.07:54:12.75$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.217.07:54:12.75$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.217.07:54:12.75$ifd4f/patch= 2006.217.07:54:12.75$ifd4f/patch=lo1,a1,a2,a3,a4 2006.217.07:54:12.75$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.217.07:54:12.75$ifd4f/patch=lo3,a5,a6,a7,a8 2006.217.07:54:12.75$4f8m12a/"form=m,16.000,1:2 2006.217.07:54:12.75$4f8m12a/"tpicd 2006.217.07:54:12.75$4f8m12a/echo=off 2006.217.07:54:12.75$4f8m12a/xlog=off 2006.217.07:54:12.75:!2006.217.07:55:10 2006.217.07:54:48.14#trakl#Source acquired 2006.217.07:54:49.14#flagr#flagr/antenna,acquired 2006.217.07:55:10.00:preob 2006.217.07:55:11.14/onsource/TRACKING 2006.217.07:55:11.14:!2006.217.07:55:20 2006.217.07:55:20.00:data_valid=on 2006.217.07:55:20.00:midob 2006.217.07:55:20.14/onsource/TRACKING 2006.217.07:55:20.14/wx/31.13,1008.6,64 2006.217.07:55:20.34/cable/+6.3854E-03 2006.217.07:55:21.43/va/01,05,usb,yes,33,35 2006.217.07:55:21.43/va/02,04,usb,yes,31,32 2006.217.07:55:21.43/va/03,04,usb,yes,29,29 2006.217.07:55:21.43/va/04,04,usb,yes,33,35 2006.217.07:55:21.43/va/05,07,usb,yes,35,37 2006.217.07:55:21.43/va/06,06,usb,yes,34,34 2006.217.07:55:21.43/va/07,06,usb,yes,35,34 2006.217.07:55:21.43/va/08,07,usb,yes,33,32 2006.217.07:55:21.66/valo/01,532.99,yes,locked 2006.217.07:55:21.66/valo/02,572.99,yes,locked 2006.217.07:55:21.66/valo/03,672.99,yes,locked 2006.217.07:55:21.66/valo/04,832.99,yes,locked 2006.217.07:55:21.66/valo/05,652.99,yes,locked 2006.217.07:55:21.66/valo/06,772.99,yes,locked 2006.217.07:55:21.66/valo/07,832.99,yes,locked 2006.217.07:55:21.66/valo/08,852.99,yes,locked 2006.217.07:55:22.75/vb/01,04,usb,yes,32,30 2006.217.07:55:22.75/vb/02,04,usb,yes,34,35 2006.217.07:55:22.75/vb/03,04,usb,yes,30,34 2006.217.07:55:22.75/vb/04,04,usb,yes,31,31 2006.217.07:55:22.75/vb/05,04,usb,yes,29,33 2006.217.07:55:22.75/vb/06,04,usb,yes,30,33 2006.217.07:55:22.75/vb/07,04,usb,yes,32,32 2006.217.07:55:22.75/vb/08,04,usb,yes,30,33 2006.217.07:55:22.99/vblo/01,632.99,yes,locked 2006.217.07:55:22.99/vblo/02,640.99,yes,locked 2006.217.07:55:22.99/vblo/03,656.99,yes,locked 2006.217.07:55:22.99/vblo/04,712.99,yes,locked 2006.217.07:55:22.99/vblo/05,744.99,yes,locked 2006.217.07:55:22.99/vblo/06,752.99,yes,locked 2006.217.07:55:22.99/vblo/07,734.99,yes,locked 2006.217.07:55:22.99/vblo/08,744.99,yes,locked 2006.217.07:55:23.14/vabw/8 2006.217.07:55:23.29/vbbw/8 2006.217.07:55:23.38/xfe/off,on,15.0 2006.217.07:55:23.76/ifatt/23,28,28,28 2006.217.07:55:24.07/fmout-gps/S +4.23E-07 2006.217.07:55:24.15:!2006.217.07:56:20 2006.217.07:56:20.01:data_valid=off 2006.217.07:56:20.01:postob 2006.217.07:56:20.10/cable/+6.3869E-03 2006.217.07:56:20.10/wx/31.10,1008.6,64 2006.217.07:56:21.07/fmout-gps/S +4.23E-07 2006.217.07:56:21.07:scan_name=217-0758,k06217,60 2006.217.07:56:21.08:source=1417+385,141946.61,382148.5,2000.0,cw 2006.217.07:56:21.14#flagr#flagr/antenna,new-source 2006.217.07:56:22.14:checkk5 2006.217.07:56:22.52/chk_autoobs//k5ts1/ autoobs is running! 2006.217.07:56:22.90/chk_autoobs//k5ts2/ autoobs is running! 2006.217.07:56:23.27/chk_autoobs//k5ts3/ autoobs is running! 2006.217.07:56:23.65/chk_autoobs//k5ts4/ autoobs is running! 2006.217.07:56:24.02/chk_obsdata//k5ts1/T2170755??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:56:24.39/chk_obsdata//k5ts2/T2170755??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:56:24.76/chk_obsdata//k5ts3/T2170755??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:56:25.13/chk_obsdata//k5ts4/T2170755??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:56:25.82/k5log//k5ts1_log_newline 2006.217.07:56:26.51/k5log//k5ts2_log_newline 2006.217.07:56:27.21/k5log//k5ts3_log_newline 2006.217.07:56:27.92/k5log//k5ts4_log_newline 2006.217.07:56:27.94/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.217.07:56:27.95:4f8m12a=2 2006.217.07:56:27.95$4f8m12a/echo=on 2006.217.07:56:27.95$4f8m12a/pcalon 2006.217.07:56:27.95$pcalon/"no phase cal control is implemented here 2006.217.07:56:27.95$4f8m12a/"tpicd=stop 2006.217.07:56:27.95$4f8m12a/vc4f8 2006.217.07:56:27.95$vc4f8/valo=1,532.99 2006.217.07:56:27.95#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.217.07:56:27.95#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.217.07:56:27.95#ibcon#ireg 17 cls_cnt 0 2006.217.07:56:27.95#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.217.07:56:27.95#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.217.07:56:27.95#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.217.07:56:27.95#ibcon#enter wrdev, iclass 34, count 0 2006.217.07:56:27.95#ibcon#first serial, iclass 34, count 0 2006.217.07:56:27.95#ibcon#enter sib2, iclass 34, count 0 2006.217.07:56:27.95#ibcon#flushed, iclass 34, count 0 2006.217.07:56:27.95#ibcon#about to write, iclass 34, count 0 2006.217.07:56:27.95#ibcon#wrote, iclass 34, count 0 2006.217.07:56:27.95#ibcon#about to read 3, iclass 34, count 0 2006.217.07:56:27.99#ibcon#read 3, iclass 34, count 0 2006.217.07:56:27.99#ibcon#about to read 4, iclass 34, count 0 2006.217.07:56:27.99#ibcon#read 4, iclass 34, count 0 2006.217.07:56:27.99#ibcon#about to read 5, iclass 34, count 0 2006.217.07:56:27.99#ibcon#read 5, iclass 34, count 0 2006.217.07:56:27.99#ibcon#about to read 6, iclass 34, count 0 2006.217.07:56:27.99#ibcon#read 6, iclass 34, count 0 2006.217.07:56:27.99#ibcon#end of sib2, iclass 34, count 0 2006.217.07:56:27.99#ibcon#*mode == 0, iclass 34, count 0 2006.217.07:56:27.99#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.217.07:56:27.99#ibcon#[26=FRQ=01,532.99\r\n] 2006.217.07:56:27.99#ibcon#*before write, iclass 34, count 0 2006.217.07:56:27.99#ibcon#enter sib2, iclass 34, count 0 2006.217.07:56:27.99#ibcon#flushed, iclass 34, count 0 2006.217.07:56:27.99#ibcon#about to write, iclass 34, count 0 2006.217.07:56:27.99#ibcon#wrote, iclass 34, count 0 2006.217.07:56:27.99#ibcon#about to read 3, iclass 34, count 0 2006.217.07:56:28.03#ibcon#read 3, iclass 34, count 0 2006.217.07:56:28.03#ibcon#about to read 4, iclass 34, count 0 2006.217.07:56:28.03#ibcon#read 4, iclass 34, count 0 2006.217.07:56:28.03#ibcon#about to read 5, iclass 34, count 0 2006.217.07:56:28.03#ibcon#read 5, iclass 34, count 0 2006.217.07:56:28.03#ibcon#about to read 6, iclass 34, count 0 2006.217.07:56:28.03#ibcon#read 6, iclass 34, count 0 2006.217.07:56:28.03#ibcon#end of sib2, iclass 34, count 0 2006.217.07:56:28.03#ibcon#*after write, iclass 34, count 0 2006.217.07:56:28.03#ibcon#*before return 0, iclass 34, count 0 2006.217.07:56:28.03#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.217.07:56:28.03#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.217.07:56:28.03#ibcon#about to clear, iclass 34 cls_cnt 0 2006.217.07:56:28.03#ibcon#cleared, iclass 34 cls_cnt 0 2006.217.07:56:28.03$vc4f8/va=1,5 2006.217.07:56:28.03#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.217.07:56:28.03#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.217.07:56:28.03#ibcon#ireg 11 cls_cnt 2 2006.217.07:56:28.03#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.217.07:56:28.03#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.217.07:56:28.03#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.217.07:56:28.03#ibcon#enter wrdev, iclass 36, count 2 2006.217.07:56:28.03#ibcon#first serial, iclass 36, count 2 2006.217.07:56:28.03#ibcon#enter sib2, iclass 36, count 2 2006.217.07:56:28.03#ibcon#flushed, iclass 36, count 2 2006.217.07:56:28.03#ibcon#about to write, iclass 36, count 2 2006.217.07:56:28.03#ibcon#wrote, iclass 36, count 2 2006.217.07:56:28.03#ibcon#about to read 3, iclass 36, count 2 2006.217.07:56:28.05#ibcon#read 3, iclass 36, count 2 2006.217.07:56:28.05#ibcon#about to read 4, iclass 36, count 2 2006.217.07:56:28.05#ibcon#read 4, iclass 36, count 2 2006.217.07:56:28.05#ibcon#about to read 5, iclass 36, count 2 2006.217.07:56:28.05#ibcon#read 5, iclass 36, count 2 2006.217.07:56:28.05#ibcon#about to read 6, iclass 36, count 2 2006.217.07:56:28.05#ibcon#read 6, iclass 36, count 2 2006.217.07:56:28.05#ibcon#end of sib2, iclass 36, count 2 2006.217.07:56:28.05#ibcon#*mode == 0, iclass 36, count 2 2006.217.07:56:28.05#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.217.07:56:28.05#ibcon#[25=AT01-05\r\n] 2006.217.07:56:28.05#ibcon#*before write, iclass 36, count 2 2006.217.07:56:28.05#ibcon#enter sib2, iclass 36, count 2 2006.217.07:56:28.05#ibcon#flushed, iclass 36, count 2 2006.217.07:56:28.05#ibcon#about to write, iclass 36, count 2 2006.217.07:56:28.05#ibcon#wrote, iclass 36, count 2 2006.217.07:56:28.05#ibcon#about to read 3, iclass 36, count 2 2006.217.07:56:28.09#abcon#<5=/05 3.7 7.2 31.09 641008.6\r\n> 2006.217.07:56:28.09#ibcon#read 3, iclass 36, count 2 2006.217.07:56:28.09#ibcon#about to read 4, iclass 36, count 2 2006.217.07:56:28.09#ibcon#read 4, iclass 36, count 2 2006.217.07:56:28.09#ibcon#about to read 5, iclass 36, count 2 2006.217.07:56:28.09#ibcon#read 5, iclass 36, count 2 2006.217.07:56:28.09#ibcon#about to read 6, iclass 36, count 2 2006.217.07:56:28.09#ibcon#read 6, iclass 36, count 2 2006.217.07:56:28.09#ibcon#end of sib2, iclass 36, count 2 2006.217.07:56:28.09#ibcon#*after write, iclass 36, count 2 2006.217.07:56:28.09#ibcon#*before return 0, iclass 36, count 2 2006.217.07:56:28.09#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.217.07:56:28.09#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.217.07:56:28.09#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.217.07:56:28.09#ibcon#ireg 7 cls_cnt 0 2006.217.07:56:28.09#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.217.07:56:28.10#abcon#{5=INTERFACE CLEAR} 2006.217.07:56:28.16#abcon#[5=S1D000X0/0*\r\n] 2006.217.07:56:28.20#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.217.07:56:28.20#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.217.07:56:28.20#ibcon#enter wrdev, iclass 36, count 0 2006.217.07:56:28.20#ibcon#first serial, iclass 36, count 0 2006.217.07:56:28.20#ibcon#enter sib2, iclass 36, count 0 2006.217.07:56:28.20#ibcon#flushed, iclass 36, count 0 2006.217.07:56:28.20#ibcon#about to write, iclass 36, count 0 2006.217.07:56:28.20#ibcon#wrote, iclass 36, count 0 2006.217.07:56:28.20#ibcon#about to read 3, iclass 36, count 0 2006.217.07:56:28.22#ibcon#read 3, iclass 36, count 0 2006.217.07:56:28.22#ibcon#about to read 4, iclass 36, count 0 2006.217.07:56:28.22#ibcon#read 4, iclass 36, count 0 2006.217.07:56:28.22#ibcon#about to read 5, iclass 36, count 0 2006.217.07:56:28.22#ibcon#read 5, iclass 36, count 0 2006.217.07:56:28.22#ibcon#about to read 6, iclass 36, count 0 2006.217.07:56:28.22#ibcon#read 6, iclass 36, count 0 2006.217.07:56:28.22#ibcon#end of sib2, iclass 36, count 0 2006.217.07:56:28.22#ibcon#*mode == 0, iclass 36, count 0 2006.217.07:56:28.22#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.217.07:56:28.22#ibcon#[25=USB\r\n] 2006.217.07:56:28.22#ibcon#*before write, iclass 36, count 0 2006.217.07:56:28.22#ibcon#enter sib2, iclass 36, count 0 2006.217.07:56:28.22#ibcon#flushed, iclass 36, count 0 2006.217.07:56:28.22#ibcon#about to write, iclass 36, count 0 2006.217.07:56:28.22#ibcon#wrote, iclass 36, count 0 2006.217.07:56:28.22#ibcon#about to read 3, iclass 36, count 0 2006.217.07:56:28.26#ibcon#read 3, iclass 36, count 0 2006.217.07:56:28.26#ibcon#about to read 4, iclass 36, count 0 2006.217.07:56:28.26#ibcon#read 4, iclass 36, count 0 2006.217.07:56:28.26#ibcon#about to read 5, iclass 36, count 0 2006.217.07:56:28.26#ibcon#read 5, iclass 36, count 0 2006.217.07:56:28.26#ibcon#about to read 6, iclass 36, count 0 2006.217.07:56:28.26#ibcon#read 6, iclass 36, count 0 2006.217.07:56:28.26#ibcon#end of sib2, iclass 36, count 0 2006.217.07:56:28.26#ibcon#*after write, iclass 36, count 0 2006.217.07:56:28.26#ibcon#*before return 0, iclass 36, count 0 2006.217.07:56:28.26#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.217.07:56:28.26#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.217.07:56:28.26#ibcon#about to clear, iclass 36 cls_cnt 0 2006.217.07:56:28.26#ibcon#cleared, iclass 36 cls_cnt 0 2006.217.07:56:28.26$vc4f8/valo=2,572.99 2006.217.07:56:28.26#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.217.07:56:28.26#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.217.07:56:28.26#ibcon#ireg 17 cls_cnt 0 2006.217.07:56:28.26#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.217.07:56:28.26#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.217.07:56:28.26#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.217.07:56:28.26#ibcon#enter wrdev, iclass 4, count 0 2006.217.07:56:28.26#ibcon#first serial, iclass 4, count 0 2006.217.07:56:28.26#ibcon#enter sib2, iclass 4, count 0 2006.217.07:56:28.26#ibcon#flushed, iclass 4, count 0 2006.217.07:56:28.26#ibcon#about to write, iclass 4, count 0 2006.217.07:56:28.26#ibcon#wrote, iclass 4, count 0 2006.217.07:56:28.26#ibcon#about to read 3, iclass 4, count 0 2006.217.07:56:28.27#ibcon#read 3, iclass 4, count 0 2006.217.07:56:28.27#ibcon#about to read 4, iclass 4, count 0 2006.217.07:56:28.27#ibcon#read 4, iclass 4, count 0 2006.217.07:56:28.27#ibcon#about to read 5, iclass 4, count 0 2006.217.07:56:28.27#ibcon#read 5, iclass 4, count 0 2006.217.07:56:28.27#ibcon#about to read 6, iclass 4, count 0 2006.217.07:56:28.27#ibcon#read 6, iclass 4, count 0 2006.217.07:56:28.27#ibcon#end of sib2, iclass 4, count 0 2006.217.07:56:28.27#ibcon#*mode == 0, iclass 4, count 0 2006.217.07:56:28.27#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.217.07:56:28.27#ibcon#[26=FRQ=02,572.99\r\n] 2006.217.07:56:28.27#ibcon#*before write, iclass 4, count 0 2006.217.07:56:28.27#ibcon#enter sib2, iclass 4, count 0 2006.217.07:56:28.27#ibcon#flushed, iclass 4, count 0 2006.217.07:56:28.27#ibcon#about to write, iclass 4, count 0 2006.217.07:56:28.28#ibcon#wrote, iclass 4, count 0 2006.217.07:56:28.28#ibcon#about to read 3, iclass 4, count 0 2006.217.07:56:28.32#ibcon#read 3, iclass 4, count 0 2006.217.07:56:28.32#ibcon#about to read 4, iclass 4, count 0 2006.217.07:56:28.32#ibcon#read 4, iclass 4, count 0 2006.217.07:56:28.32#ibcon#about to read 5, iclass 4, count 0 2006.217.07:56:28.32#ibcon#read 5, iclass 4, count 0 2006.217.07:56:28.32#ibcon#about to read 6, iclass 4, count 0 2006.217.07:56:28.32#ibcon#read 6, iclass 4, count 0 2006.217.07:56:28.32#ibcon#end of sib2, iclass 4, count 0 2006.217.07:56:28.32#ibcon#*after write, iclass 4, count 0 2006.217.07:56:28.32#ibcon#*before return 0, iclass 4, count 0 2006.217.07:56:28.32#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.217.07:56:28.32#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.217.07:56:28.32#ibcon#about to clear, iclass 4 cls_cnt 0 2006.217.07:56:28.32#ibcon#cleared, iclass 4 cls_cnt 0 2006.217.07:56:28.32$vc4f8/va=2,4 2006.217.07:56:28.32#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.217.07:56:28.32#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.217.07:56:28.32#ibcon#ireg 11 cls_cnt 2 2006.217.07:56:28.32#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.217.07:56:28.38#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.217.07:56:28.38#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.217.07:56:28.38#ibcon#enter wrdev, iclass 6, count 2 2006.217.07:56:28.38#ibcon#first serial, iclass 6, count 2 2006.217.07:56:28.38#ibcon#enter sib2, iclass 6, count 2 2006.217.07:56:28.38#ibcon#flushed, iclass 6, count 2 2006.217.07:56:28.38#ibcon#about to write, iclass 6, count 2 2006.217.07:56:28.38#ibcon#wrote, iclass 6, count 2 2006.217.07:56:28.38#ibcon#about to read 3, iclass 6, count 2 2006.217.07:56:28.40#ibcon#read 3, iclass 6, count 2 2006.217.07:56:28.40#ibcon#about to read 4, iclass 6, count 2 2006.217.07:56:28.40#ibcon#read 4, iclass 6, count 2 2006.217.07:56:28.40#ibcon#about to read 5, iclass 6, count 2 2006.217.07:56:28.40#ibcon#read 5, iclass 6, count 2 2006.217.07:56:28.40#ibcon#about to read 6, iclass 6, count 2 2006.217.07:56:28.40#ibcon#read 6, iclass 6, count 2 2006.217.07:56:28.40#ibcon#end of sib2, iclass 6, count 2 2006.217.07:56:28.40#ibcon#*mode == 0, iclass 6, count 2 2006.217.07:56:28.40#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.217.07:56:28.40#ibcon#[25=AT02-04\r\n] 2006.217.07:56:28.40#ibcon#*before write, iclass 6, count 2 2006.217.07:56:28.40#ibcon#enter sib2, iclass 6, count 2 2006.217.07:56:28.40#ibcon#flushed, iclass 6, count 2 2006.217.07:56:28.40#ibcon#about to write, iclass 6, count 2 2006.217.07:56:28.40#ibcon#wrote, iclass 6, count 2 2006.217.07:56:28.40#ibcon#about to read 3, iclass 6, count 2 2006.217.07:56:28.43#ibcon#read 3, iclass 6, count 2 2006.217.07:56:28.43#ibcon#about to read 4, iclass 6, count 2 2006.217.07:56:28.43#ibcon#read 4, iclass 6, count 2 2006.217.07:56:28.43#ibcon#about to read 5, iclass 6, count 2 2006.217.07:56:28.43#ibcon#read 5, iclass 6, count 2 2006.217.07:56:28.43#ibcon#about to read 6, iclass 6, count 2 2006.217.07:56:28.43#ibcon#read 6, iclass 6, count 2 2006.217.07:56:28.43#ibcon#end of sib2, iclass 6, count 2 2006.217.07:56:28.43#ibcon#*after write, iclass 6, count 2 2006.217.07:56:28.43#ibcon#*before return 0, iclass 6, count 2 2006.217.07:56:28.43#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.217.07:56:28.43#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.217.07:56:28.43#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.217.07:56:28.43#ibcon#ireg 7 cls_cnt 0 2006.217.07:56:28.43#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.217.07:56:28.56#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.217.07:56:28.56#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.217.07:56:28.56#ibcon#enter wrdev, iclass 6, count 0 2006.217.07:56:28.56#ibcon#first serial, iclass 6, count 0 2006.217.07:56:28.56#ibcon#enter sib2, iclass 6, count 0 2006.217.07:56:28.56#ibcon#flushed, iclass 6, count 0 2006.217.07:56:28.56#ibcon#about to write, iclass 6, count 0 2006.217.07:56:28.56#ibcon#wrote, iclass 6, count 0 2006.217.07:56:28.56#ibcon#about to read 3, iclass 6, count 0 2006.217.07:56:28.57#ibcon#read 3, iclass 6, count 0 2006.217.07:56:28.57#ibcon#about to read 4, iclass 6, count 0 2006.217.07:56:28.57#ibcon#read 4, iclass 6, count 0 2006.217.07:56:28.57#ibcon#about to read 5, iclass 6, count 0 2006.217.07:56:28.57#ibcon#read 5, iclass 6, count 0 2006.217.07:56:28.57#ibcon#about to read 6, iclass 6, count 0 2006.217.07:56:28.57#ibcon#read 6, iclass 6, count 0 2006.217.07:56:28.57#ibcon#end of sib2, iclass 6, count 0 2006.217.07:56:28.57#ibcon#*mode == 0, iclass 6, count 0 2006.217.07:56:28.57#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.217.07:56:28.57#ibcon#[25=USB\r\n] 2006.217.07:56:28.57#ibcon#*before write, iclass 6, count 0 2006.217.07:56:28.57#ibcon#enter sib2, iclass 6, count 0 2006.217.07:56:28.57#ibcon#flushed, iclass 6, count 0 2006.217.07:56:28.57#ibcon#about to write, iclass 6, count 0 2006.217.07:56:28.57#ibcon#wrote, iclass 6, count 0 2006.217.07:56:28.57#ibcon#about to read 3, iclass 6, count 0 2006.217.07:56:28.60#ibcon#read 3, iclass 6, count 0 2006.217.07:56:28.60#ibcon#about to read 4, iclass 6, count 0 2006.217.07:56:28.60#ibcon#read 4, iclass 6, count 0 2006.217.07:56:28.60#ibcon#about to read 5, iclass 6, count 0 2006.217.07:56:28.60#ibcon#read 5, iclass 6, count 0 2006.217.07:56:28.60#ibcon#about to read 6, iclass 6, count 0 2006.217.07:56:28.60#ibcon#read 6, iclass 6, count 0 2006.217.07:56:28.60#ibcon#end of sib2, iclass 6, count 0 2006.217.07:56:28.60#ibcon#*after write, iclass 6, count 0 2006.217.07:56:28.60#ibcon#*before return 0, iclass 6, count 0 2006.217.07:56:28.60#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.217.07:56:28.60#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.217.07:56:28.60#ibcon#about to clear, iclass 6 cls_cnt 0 2006.217.07:56:28.60#ibcon#cleared, iclass 6 cls_cnt 0 2006.217.07:56:28.60$vc4f8/valo=3,672.99 2006.217.07:56:28.60#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.217.07:56:28.60#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.217.07:56:28.60#ibcon#ireg 17 cls_cnt 0 2006.217.07:56:28.60#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.217.07:56:28.60#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.217.07:56:28.60#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.217.07:56:28.60#ibcon#enter wrdev, iclass 10, count 0 2006.217.07:56:28.60#ibcon#first serial, iclass 10, count 0 2006.217.07:56:28.60#ibcon#enter sib2, iclass 10, count 0 2006.217.07:56:28.60#ibcon#flushed, iclass 10, count 0 2006.217.07:56:28.60#ibcon#about to write, iclass 10, count 0 2006.217.07:56:28.60#ibcon#wrote, iclass 10, count 0 2006.217.07:56:28.60#ibcon#about to read 3, iclass 10, count 0 2006.217.07:56:28.63#ibcon#read 3, iclass 10, count 0 2006.217.07:56:28.63#ibcon#about to read 4, iclass 10, count 0 2006.217.07:56:28.63#ibcon#read 4, iclass 10, count 0 2006.217.07:56:28.63#ibcon#about to read 5, iclass 10, count 0 2006.217.07:56:28.63#ibcon#read 5, iclass 10, count 0 2006.217.07:56:28.63#ibcon#about to read 6, iclass 10, count 0 2006.217.07:56:28.63#ibcon#read 6, iclass 10, count 0 2006.217.07:56:28.63#ibcon#end of sib2, iclass 10, count 0 2006.217.07:56:28.63#ibcon#*mode == 0, iclass 10, count 0 2006.217.07:56:28.63#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.217.07:56:28.63#ibcon#[26=FRQ=03,672.99\r\n] 2006.217.07:56:28.63#ibcon#*before write, iclass 10, count 0 2006.217.07:56:28.63#ibcon#enter sib2, iclass 10, count 0 2006.217.07:56:28.63#ibcon#flushed, iclass 10, count 0 2006.217.07:56:28.63#ibcon#about to write, iclass 10, count 0 2006.217.07:56:28.63#ibcon#wrote, iclass 10, count 0 2006.217.07:56:28.63#ibcon#about to read 3, iclass 10, count 0 2006.217.07:56:28.67#ibcon#read 3, iclass 10, count 0 2006.217.07:56:28.67#ibcon#about to read 4, iclass 10, count 0 2006.217.07:56:28.67#ibcon#read 4, iclass 10, count 0 2006.217.07:56:28.67#ibcon#about to read 5, iclass 10, count 0 2006.217.07:56:28.67#ibcon#read 5, iclass 10, count 0 2006.217.07:56:28.67#ibcon#about to read 6, iclass 10, count 0 2006.217.07:56:28.67#ibcon#read 6, iclass 10, count 0 2006.217.07:56:28.67#ibcon#end of sib2, iclass 10, count 0 2006.217.07:56:28.67#ibcon#*after write, iclass 10, count 0 2006.217.07:56:28.67#ibcon#*before return 0, iclass 10, count 0 2006.217.07:56:28.67#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.217.07:56:28.67#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.217.07:56:28.67#ibcon#about to clear, iclass 10 cls_cnt 0 2006.217.07:56:28.67#ibcon#cleared, iclass 10 cls_cnt 0 2006.217.07:56:28.67$vc4f8/va=3,4 2006.217.07:56:28.67#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.217.07:56:28.67#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.217.07:56:28.67#ibcon#ireg 11 cls_cnt 2 2006.217.07:56:28.67#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.217.07:56:28.72#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.217.07:56:28.72#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.217.07:56:28.72#ibcon#enter wrdev, iclass 12, count 2 2006.217.07:56:28.72#ibcon#first serial, iclass 12, count 2 2006.217.07:56:28.72#ibcon#enter sib2, iclass 12, count 2 2006.217.07:56:28.72#ibcon#flushed, iclass 12, count 2 2006.217.07:56:28.72#ibcon#about to write, iclass 12, count 2 2006.217.07:56:28.72#ibcon#wrote, iclass 12, count 2 2006.217.07:56:28.72#ibcon#about to read 3, iclass 12, count 2 2006.217.07:56:28.74#ibcon#read 3, iclass 12, count 2 2006.217.07:56:28.74#ibcon#about to read 4, iclass 12, count 2 2006.217.07:56:28.74#ibcon#read 4, iclass 12, count 2 2006.217.07:56:28.74#ibcon#about to read 5, iclass 12, count 2 2006.217.07:56:28.74#ibcon#read 5, iclass 12, count 2 2006.217.07:56:28.74#ibcon#about to read 6, iclass 12, count 2 2006.217.07:56:28.74#ibcon#read 6, iclass 12, count 2 2006.217.07:56:28.74#ibcon#end of sib2, iclass 12, count 2 2006.217.07:56:28.74#ibcon#*mode == 0, iclass 12, count 2 2006.217.07:56:28.74#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.217.07:56:28.74#ibcon#[25=AT03-04\r\n] 2006.217.07:56:28.74#ibcon#*before write, iclass 12, count 2 2006.217.07:56:28.74#ibcon#enter sib2, iclass 12, count 2 2006.217.07:56:28.74#ibcon#flushed, iclass 12, count 2 2006.217.07:56:28.74#ibcon#about to write, iclass 12, count 2 2006.217.07:56:28.74#ibcon#wrote, iclass 12, count 2 2006.217.07:56:28.74#ibcon#about to read 3, iclass 12, count 2 2006.217.07:56:28.77#ibcon#read 3, iclass 12, count 2 2006.217.07:56:28.77#ibcon#about to read 4, iclass 12, count 2 2006.217.07:56:28.77#ibcon#read 4, iclass 12, count 2 2006.217.07:56:28.77#ibcon#about to read 5, iclass 12, count 2 2006.217.07:56:28.77#ibcon#read 5, iclass 12, count 2 2006.217.07:56:28.77#ibcon#about to read 6, iclass 12, count 2 2006.217.07:56:28.77#ibcon#read 6, iclass 12, count 2 2006.217.07:56:28.77#ibcon#end of sib2, iclass 12, count 2 2006.217.07:56:28.77#ibcon#*after write, iclass 12, count 2 2006.217.07:56:28.77#ibcon#*before return 0, iclass 12, count 2 2006.217.07:56:28.77#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.217.07:56:28.77#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.217.07:56:28.77#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.217.07:56:28.77#ibcon#ireg 7 cls_cnt 0 2006.217.07:56:28.77#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.217.07:56:28.89#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.217.07:56:28.89#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.217.07:56:28.89#ibcon#enter wrdev, iclass 12, count 0 2006.217.07:56:28.89#ibcon#first serial, iclass 12, count 0 2006.217.07:56:28.89#ibcon#enter sib2, iclass 12, count 0 2006.217.07:56:28.89#ibcon#flushed, iclass 12, count 0 2006.217.07:56:28.89#ibcon#about to write, iclass 12, count 0 2006.217.07:56:28.89#ibcon#wrote, iclass 12, count 0 2006.217.07:56:28.89#ibcon#about to read 3, iclass 12, count 0 2006.217.07:56:28.91#ibcon#read 3, iclass 12, count 0 2006.217.07:56:28.91#ibcon#about to read 4, iclass 12, count 0 2006.217.07:56:28.91#ibcon#read 4, iclass 12, count 0 2006.217.07:56:28.91#ibcon#about to read 5, iclass 12, count 0 2006.217.07:56:28.91#ibcon#read 5, iclass 12, count 0 2006.217.07:56:28.91#ibcon#about to read 6, iclass 12, count 0 2006.217.07:56:28.91#ibcon#read 6, iclass 12, count 0 2006.217.07:56:28.91#ibcon#end of sib2, iclass 12, count 0 2006.217.07:56:28.91#ibcon#*mode == 0, iclass 12, count 0 2006.217.07:56:28.91#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.217.07:56:28.91#ibcon#[25=USB\r\n] 2006.217.07:56:28.91#ibcon#*before write, iclass 12, count 0 2006.217.07:56:28.91#ibcon#enter sib2, iclass 12, count 0 2006.217.07:56:28.91#ibcon#flushed, iclass 12, count 0 2006.217.07:56:28.91#ibcon#about to write, iclass 12, count 0 2006.217.07:56:28.91#ibcon#wrote, iclass 12, count 0 2006.217.07:56:28.91#ibcon#about to read 3, iclass 12, count 0 2006.217.07:56:28.94#ibcon#read 3, iclass 12, count 0 2006.217.07:56:28.94#ibcon#about to read 4, iclass 12, count 0 2006.217.07:56:28.94#ibcon#read 4, iclass 12, count 0 2006.217.07:56:28.94#ibcon#about to read 5, iclass 12, count 0 2006.217.07:56:28.94#ibcon#read 5, iclass 12, count 0 2006.217.07:56:28.94#ibcon#about to read 6, iclass 12, count 0 2006.217.07:56:28.94#ibcon#read 6, iclass 12, count 0 2006.217.07:56:28.94#ibcon#end of sib2, iclass 12, count 0 2006.217.07:56:28.94#ibcon#*after write, iclass 12, count 0 2006.217.07:56:28.94#ibcon#*before return 0, iclass 12, count 0 2006.217.07:56:28.94#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.217.07:56:28.94#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.217.07:56:28.94#ibcon#about to clear, iclass 12 cls_cnt 0 2006.217.07:56:28.94#ibcon#cleared, iclass 12 cls_cnt 0 2006.217.07:56:28.94$vc4f8/valo=4,832.99 2006.217.07:56:28.94#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.217.07:56:28.94#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.217.07:56:28.94#ibcon#ireg 17 cls_cnt 0 2006.217.07:56:28.94#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.217.07:56:28.94#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.217.07:56:28.94#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.217.07:56:28.94#ibcon#enter wrdev, iclass 14, count 0 2006.217.07:56:28.94#ibcon#first serial, iclass 14, count 0 2006.217.07:56:28.94#ibcon#enter sib2, iclass 14, count 0 2006.217.07:56:28.94#ibcon#flushed, iclass 14, count 0 2006.217.07:56:28.94#ibcon#about to write, iclass 14, count 0 2006.217.07:56:28.94#ibcon#wrote, iclass 14, count 0 2006.217.07:56:28.94#ibcon#about to read 3, iclass 14, count 0 2006.217.07:56:28.96#ibcon#read 3, iclass 14, count 0 2006.217.07:56:28.96#ibcon#about to read 4, iclass 14, count 0 2006.217.07:56:28.96#ibcon#read 4, iclass 14, count 0 2006.217.07:56:28.96#ibcon#about to read 5, iclass 14, count 0 2006.217.07:56:28.96#ibcon#read 5, iclass 14, count 0 2006.217.07:56:28.96#ibcon#about to read 6, iclass 14, count 0 2006.217.07:56:28.96#ibcon#read 6, iclass 14, count 0 2006.217.07:56:28.96#ibcon#end of sib2, iclass 14, count 0 2006.217.07:56:28.96#ibcon#*mode == 0, iclass 14, count 0 2006.217.07:56:28.96#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.217.07:56:28.96#ibcon#[26=FRQ=04,832.99\r\n] 2006.217.07:56:28.96#ibcon#*before write, iclass 14, count 0 2006.217.07:56:28.96#ibcon#enter sib2, iclass 14, count 0 2006.217.07:56:28.96#ibcon#flushed, iclass 14, count 0 2006.217.07:56:28.96#ibcon#about to write, iclass 14, count 0 2006.217.07:56:28.96#ibcon#wrote, iclass 14, count 0 2006.217.07:56:28.96#ibcon#about to read 3, iclass 14, count 0 2006.217.07:56:29.00#ibcon#read 3, iclass 14, count 0 2006.217.07:56:29.00#ibcon#about to read 4, iclass 14, count 0 2006.217.07:56:29.00#ibcon#read 4, iclass 14, count 0 2006.217.07:56:29.00#ibcon#about to read 5, iclass 14, count 0 2006.217.07:56:29.00#ibcon#read 5, iclass 14, count 0 2006.217.07:56:29.00#ibcon#about to read 6, iclass 14, count 0 2006.217.07:56:29.00#ibcon#read 6, iclass 14, count 0 2006.217.07:56:29.00#ibcon#end of sib2, iclass 14, count 0 2006.217.07:56:29.00#ibcon#*after write, iclass 14, count 0 2006.217.07:56:29.00#ibcon#*before return 0, iclass 14, count 0 2006.217.07:56:29.00#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.217.07:56:29.00#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.217.07:56:29.00#ibcon#about to clear, iclass 14 cls_cnt 0 2006.217.07:56:29.00#ibcon#cleared, iclass 14 cls_cnt 0 2006.217.07:56:29.00$vc4f8/va=4,4 2006.217.07:56:29.00#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.217.07:56:29.00#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.217.07:56:29.00#ibcon#ireg 11 cls_cnt 2 2006.217.07:56:29.00#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.217.07:56:29.06#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.217.07:56:29.06#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.217.07:56:29.06#ibcon#enter wrdev, iclass 16, count 2 2006.217.07:56:29.06#ibcon#first serial, iclass 16, count 2 2006.217.07:56:29.06#ibcon#enter sib2, iclass 16, count 2 2006.217.07:56:29.06#ibcon#flushed, iclass 16, count 2 2006.217.07:56:29.06#ibcon#about to write, iclass 16, count 2 2006.217.07:56:29.06#ibcon#wrote, iclass 16, count 2 2006.217.07:56:29.06#ibcon#about to read 3, iclass 16, count 2 2006.217.07:56:29.08#ibcon#read 3, iclass 16, count 2 2006.217.07:56:29.08#ibcon#about to read 4, iclass 16, count 2 2006.217.07:56:29.08#ibcon#read 4, iclass 16, count 2 2006.217.07:56:29.08#ibcon#about to read 5, iclass 16, count 2 2006.217.07:56:29.08#ibcon#read 5, iclass 16, count 2 2006.217.07:56:29.08#ibcon#about to read 6, iclass 16, count 2 2006.217.07:56:29.08#ibcon#read 6, iclass 16, count 2 2006.217.07:56:29.08#ibcon#end of sib2, iclass 16, count 2 2006.217.07:56:29.08#ibcon#*mode == 0, iclass 16, count 2 2006.217.07:56:29.08#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.217.07:56:29.08#ibcon#[25=AT04-04\r\n] 2006.217.07:56:29.08#ibcon#*before write, iclass 16, count 2 2006.217.07:56:29.08#ibcon#enter sib2, iclass 16, count 2 2006.217.07:56:29.08#ibcon#flushed, iclass 16, count 2 2006.217.07:56:29.08#ibcon#about to write, iclass 16, count 2 2006.217.07:56:29.08#ibcon#wrote, iclass 16, count 2 2006.217.07:56:29.08#ibcon#about to read 3, iclass 16, count 2 2006.217.07:56:29.11#ibcon#read 3, iclass 16, count 2 2006.217.07:56:29.11#ibcon#about to read 4, iclass 16, count 2 2006.217.07:56:29.11#ibcon#read 4, iclass 16, count 2 2006.217.07:56:29.11#ibcon#about to read 5, iclass 16, count 2 2006.217.07:56:29.11#ibcon#read 5, iclass 16, count 2 2006.217.07:56:29.11#ibcon#about to read 6, iclass 16, count 2 2006.217.07:56:29.11#ibcon#read 6, iclass 16, count 2 2006.217.07:56:29.11#ibcon#end of sib2, iclass 16, count 2 2006.217.07:56:29.11#ibcon#*after write, iclass 16, count 2 2006.217.07:56:29.11#ibcon#*before return 0, iclass 16, count 2 2006.217.07:56:29.11#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.217.07:56:29.11#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.217.07:56:29.11#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.217.07:56:29.11#ibcon#ireg 7 cls_cnt 0 2006.217.07:56:29.11#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.217.07:56:29.23#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.217.07:56:29.23#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.217.07:56:29.23#ibcon#enter wrdev, iclass 16, count 0 2006.217.07:56:29.23#ibcon#first serial, iclass 16, count 0 2006.217.07:56:29.23#ibcon#enter sib2, iclass 16, count 0 2006.217.07:56:29.23#ibcon#flushed, iclass 16, count 0 2006.217.07:56:29.23#ibcon#about to write, iclass 16, count 0 2006.217.07:56:29.23#ibcon#wrote, iclass 16, count 0 2006.217.07:56:29.23#ibcon#about to read 3, iclass 16, count 0 2006.217.07:56:29.25#ibcon#read 3, iclass 16, count 0 2006.217.07:56:29.25#ibcon#about to read 4, iclass 16, count 0 2006.217.07:56:29.25#ibcon#read 4, iclass 16, count 0 2006.217.07:56:29.25#ibcon#about to read 5, iclass 16, count 0 2006.217.07:56:29.25#ibcon#read 5, iclass 16, count 0 2006.217.07:56:29.25#ibcon#about to read 6, iclass 16, count 0 2006.217.07:56:29.25#ibcon#read 6, iclass 16, count 0 2006.217.07:56:29.25#ibcon#end of sib2, iclass 16, count 0 2006.217.07:56:29.25#ibcon#*mode == 0, iclass 16, count 0 2006.217.07:56:29.25#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.217.07:56:29.25#ibcon#[25=USB\r\n] 2006.217.07:56:29.25#ibcon#*before write, iclass 16, count 0 2006.217.07:56:29.25#ibcon#enter sib2, iclass 16, count 0 2006.217.07:56:29.25#ibcon#flushed, iclass 16, count 0 2006.217.07:56:29.25#ibcon#about to write, iclass 16, count 0 2006.217.07:56:29.25#ibcon#wrote, iclass 16, count 0 2006.217.07:56:29.25#ibcon#about to read 3, iclass 16, count 0 2006.217.07:56:29.28#ibcon#read 3, iclass 16, count 0 2006.217.07:56:29.28#ibcon#about to read 4, iclass 16, count 0 2006.217.07:56:29.28#ibcon#read 4, iclass 16, count 0 2006.217.07:56:29.28#ibcon#about to read 5, iclass 16, count 0 2006.217.07:56:29.28#ibcon#read 5, iclass 16, count 0 2006.217.07:56:29.28#ibcon#about to read 6, iclass 16, count 0 2006.217.07:56:29.28#ibcon#read 6, iclass 16, count 0 2006.217.07:56:29.28#ibcon#end of sib2, iclass 16, count 0 2006.217.07:56:29.28#ibcon#*after write, iclass 16, count 0 2006.217.07:56:29.28#ibcon#*before return 0, iclass 16, count 0 2006.217.07:56:29.28#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.217.07:56:29.28#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.217.07:56:29.28#ibcon#about to clear, iclass 16 cls_cnt 0 2006.217.07:56:29.28#ibcon#cleared, iclass 16 cls_cnt 0 2006.217.07:56:29.28$vc4f8/valo=5,652.99 2006.217.07:56:29.28#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.217.07:56:29.28#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.217.07:56:29.28#ibcon#ireg 17 cls_cnt 0 2006.217.07:56:29.28#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.217.07:56:29.28#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.217.07:56:29.28#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.217.07:56:29.28#ibcon#enter wrdev, iclass 18, count 0 2006.217.07:56:29.28#ibcon#first serial, iclass 18, count 0 2006.217.07:56:29.28#ibcon#enter sib2, iclass 18, count 0 2006.217.07:56:29.28#ibcon#flushed, iclass 18, count 0 2006.217.07:56:29.28#ibcon#about to write, iclass 18, count 0 2006.217.07:56:29.28#ibcon#wrote, iclass 18, count 0 2006.217.07:56:29.28#ibcon#about to read 3, iclass 18, count 0 2006.217.07:56:29.30#ibcon#read 3, iclass 18, count 0 2006.217.07:56:29.30#ibcon#about to read 4, iclass 18, count 0 2006.217.07:56:29.30#ibcon#read 4, iclass 18, count 0 2006.217.07:56:29.30#ibcon#about to read 5, iclass 18, count 0 2006.217.07:56:29.30#ibcon#read 5, iclass 18, count 0 2006.217.07:56:29.30#ibcon#about to read 6, iclass 18, count 0 2006.217.07:56:29.30#ibcon#read 6, iclass 18, count 0 2006.217.07:56:29.30#ibcon#end of sib2, iclass 18, count 0 2006.217.07:56:29.30#ibcon#*mode == 0, iclass 18, count 0 2006.217.07:56:29.30#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.217.07:56:29.30#ibcon#[26=FRQ=05,652.99\r\n] 2006.217.07:56:29.30#ibcon#*before write, iclass 18, count 0 2006.217.07:56:29.30#ibcon#enter sib2, iclass 18, count 0 2006.217.07:56:29.30#ibcon#flushed, iclass 18, count 0 2006.217.07:56:29.30#ibcon#about to write, iclass 18, count 0 2006.217.07:56:29.30#ibcon#wrote, iclass 18, count 0 2006.217.07:56:29.30#ibcon#about to read 3, iclass 18, count 0 2006.217.07:56:29.34#ibcon#read 3, iclass 18, count 0 2006.217.07:56:29.34#ibcon#about to read 4, iclass 18, count 0 2006.217.07:56:29.34#ibcon#read 4, iclass 18, count 0 2006.217.07:56:29.34#ibcon#about to read 5, iclass 18, count 0 2006.217.07:56:29.34#ibcon#read 5, iclass 18, count 0 2006.217.07:56:29.34#ibcon#about to read 6, iclass 18, count 0 2006.217.07:56:29.34#ibcon#read 6, iclass 18, count 0 2006.217.07:56:29.34#ibcon#end of sib2, iclass 18, count 0 2006.217.07:56:29.34#ibcon#*after write, iclass 18, count 0 2006.217.07:56:29.34#ibcon#*before return 0, iclass 18, count 0 2006.217.07:56:29.34#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.217.07:56:29.34#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.217.07:56:29.34#ibcon#about to clear, iclass 18 cls_cnt 0 2006.217.07:56:29.34#ibcon#cleared, iclass 18 cls_cnt 0 2006.217.07:56:29.34$vc4f8/va=5,7 2006.217.07:56:29.34#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.217.07:56:29.34#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.217.07:56:29.34#ibcon#ireg 11 cls_cnt 2 2006.217.07:56:29.34#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.217.07:56:29.40#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.217.07:56:29.40#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.217.07:56:29.40#ibcon#enter wrdev, iclass 20, count 2 2006.217.07:56:29.40#ibcon#first serial, iclass 20, count 2 2006.217.07:56:29.40#ibcon#enter sib2, iclass 20, count 2 2006.217.07:56:29.40#ibcon#flushed, iclass 20, count 2 2006.217.07:56:29.40#ibcon#about to write, iclass 20, count 2 2006.217.07:56:29.40#ibcon#wrote, iclass 20, count 2 2006.217.07:56:29.40#ibcon#about to read 3, iclass 20, count 2 2006.217.07:56:29.42#ibcon#read 3, iclass 20, count 2 2006.217.07:56:29.42#ibcon#about to read 4, iclass 20, count 2 2006.217.07:56:29.42#ibcon#read 4, iclass 20, count 2 2006.217.07:56:29.42#ibcon#about to read 5, iclass 20, count 2 2006.217.07:56:29.42#ibcon#read 5, iclass 20, count 2 2006.217.07:56:29.42#ibcon#about to read 6, iclass 20, count 2 2006.217.07:56:29.42#ibcon#read 6, iclass 20, count 2 2006.217.07:56:29.42#ibcon#end of sib2, iclass 20, count 2 2006.217.07:56:29.42#ibcon#*mode == 0, iclass 20, count 2 2006.217.07:56:29.42#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.217.07:56:29.42#ibcon#[25=AT05-07\r\n] 2006.217.07:56:29.42#ibcon#*before write, iclass 20, count 2 2006.217.07:56:29.42#ibcon#enter sib2, iclass 20, count 2 2006.217.07:56:29.42#ibcon#flushed, iclass 20, count 2 2006.217.07:56:29.42#ibcon#about to write, iclass 20, count 2 2006.217.07:56:29.42#ibcon#wrote, iclass 20, count 2 2006.217.07:56:29.42#ibcon#about to read 3, iclass 20, count 2 2006.217.07:56:29.45#ibcon#read 3, iclass 20, count 2 2006.217.07:56:29.45#ibcon#about to read 4, iclass 20, count 2 2006.217.07:56:29.45#ibcon#read 4, iclass 20, count 2 2006.217.07:56:29.45#ibcon#about to read 5, iclass 20, count 2 2006.217.07:56:29.45#ibcon#read 5, iclass 20, count 2 2006.217.07:56:29.45#ibcon#about to read 6, iclass 20, count 2 2006.217.07:56:29.45#ibcon#read 6, iclass 20, count 2 2006.217.07:56:29.45#ibcon#end of sib2, iclass 20, count 2 2006.217.07:56:29.45#ibcon#*after write, iclass 20, count 2 2006.217.07:56:29.45#ibcon#*before return 0, iclass 20, count 2 2006.217.07:56:29.45#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.217.07:56:29.45#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.217.07:56:29.45#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.217.07:56:29.45#ibcon#ireg 7 cls_cnt 0 2006.217.07:56:29.45#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.217.07:56:29.57#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.217.07:56:29.57#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.217.07:56:29.57#ibcon#enter wrdev, iclass 20, count 0 2006.217.07:56:29.57#ibcon#first serial, iclass 20, count 0 2006.217.07:56:29.57#ibcon#enter sib2, iclass 20, count 0 2006.217.07:56:29.57#ibcon#flushed, iclass 20, count 0 2006.217.07:56:29.57#ibcon#about to write, iclass 20, count 0 2006.217.07:56:29.57#ibcon#wrote, iclass 20, count 0 2006.217.07:56:29.57#ibcon#about to read 3, iclass 20, count 0 2006.217.07:56:29.59#ibcon#read 3, iclass 20, count 0 2006.217.07:56:29.59#ibcon#about to read 4, iclass 20, count 0 2006.217.07:56:29.59#ibcon#read 4, iclass 20, count 0 2006.217.07:56:29.59#ibcon#about to read 5, iclass 20, count 0 2006.217.07:56:29.59#ibcon#read 5, iclass 20, count 0 2006.217.07:56:29.59#ibcon#about to read 6, iclass 20, count 0 2006.217.07:56:29.59#ibcon#read 6, iclass 20, count 0 2006.217.07:56:29.59#ibcon#end of sib2, iclass 20, count 0 2006.217.07:56:29.59#ibcon#*mode == 0, iclass 20, count 0 2006.217.07:56:29.59#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.217.07:56:29.59#ibcon#[25=USB\r\n] 2006.217.07:56:29.59#ibcon#*before write, iclass 20, count 0 2006.217.07:56:29.59#ibcon#enter sib2, iclass 20, count 0 2006.217.07:56:29.59#ibcon#flushed, iclass 20, count 0 2006.217.07:56:29.59#ibcon#about to write, iclass 20, count 0 2006.217.07:56:29.59#ibcon#wrote, iclass 20, count 0 2006.217.07:56:29.59#ibcon#about to read 3, iclass 20, count 0 2006.217.07:56:29.62#ibcon#read 3, iclass 20, count 0 2006.217.07:56:29.62#ibcon#about to read 4, iclass 20, count 0 2006.217.07:56:29.62#ibcon#read 4, iclass 20, count 0 2006.217.07:56:29.62#ibcon#about to read 5, iclass 20, count 0 2006.217.07:56:29.62#ibcon#read 5, iclass 20, count 0 2006.217.07:56:29.62#ibcon#about to read 6, iclass 20, count 0 2006.217.07:56:29.62#ibcon#read 6, iclass 20, count 0 2006.217.07:56:29.62#ibcon#end of sib2, iclass 20, count 0 2006.217.07:56:29.62#ibcon#*after write, iclass 20, count 0 2006.217.07:56:29.62#ibcon#*before return 0, iclass 20, count 0 2006.217.07:56:29.62#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.217.07:56:29.62#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.217.07:56:29.62#ibcon#about to clear, iclass 20 cls_cnt 0 2006.217.07:56:29.62#ibcon#cleared, iclass 20 cls_cnt 0 2006.217.07:56:29.62$vc4f8/valo=6,772.99 2006.217.07:56:29.62#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.217.07:56:29.62#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.217.07:56:29.62#ibcon#ireg 17 cls_cnt 0 2006.217.07:56:29.62#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.217.07:56:29.62#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.217.07:56:29.62#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.217.07:56:29.62#ibcon#enter wrdev, iclass 22, count 0 2006.217.07:56:29.62#ibcon#first serial, iclass 22, count 0 2006.217.07:56:29.62#ibcon#enter sib2, iclass 22, count 0 2006.217.07:56:29.62#ibcon#flushed, iclass 22, count 0 2006.217.07:56:29.62#ibcon#about to write, iclass 22, count 0 2006.217.07:56:29.62#ibcon#wrote, iclass 22, count 0 2006.217.07:56:29.62#ibcon#about to read 3, iclass 22, count 0 2006.217.07:56:29.64#ibcon#read 3, iclass 22, count 0 2006.217.07:56:29.64#ibcon#about to read 4, iclass 22, count 0 2006.217.07:56:29.64#ibcon#read 4, iclass 22, count 0 2006.217.07:56:29.64#ibcon#about to read 5, iclass 22, count 0 2006.217.07:56:29.64#ibcon#read 5, iclass 22, count 0 2006.217.07:56:29.64#ibcon#about to read 6, iclass 22, count 0 2006.217.07:56:29.64#ibcon#read 6, iclass 22, count 0 2006.217.07:56:29.64#ibcon#end of sib2, iclass 22, count 0 2006.217.07:56:29.64#ibcon#*mode == 0, iclass 22, count 0 2006.217.07:56:29.64#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.217.07:56:29.64#ibcon#[26=FRQ=06,772.99\r\n] 2006.217.07:56:29.64#ibcon#*before write, iclass 22, count 0 2006.217.07:56:29.64#ibcon#enter sib2, iclass 22, count 0 2006.217.07:56:29.64#ibcon#flushed, iclass 22, count 0 2006.217.07:56:29.64#ibcon#about to write, iclass 22, count 0 2006.217.07:56:29.64#ibcon#wrote, iclass 22, count 0 2006.217.07:56:29.64#ibcon#about to read 3, iclass 22, count 0 2006.217.07:56:29.68#ibcon#read 3, iclass 22, count 0 2006.217.07:56:29.68#ibcon#about to read 4, iclass 22, count 0 2006.217.07:56:29.68#ibcon#read 4, iclass 22, count 0 2006.217.07:56:29.68#ibcon#about to read 5, iclass 22, count 0 2006.217.07:56:29.68#ibcon#read 5, iclass 22, count 0 2006.217.07:56:29.68#ibcon#about to read 6, iclass 22, count 0 2006.217.07:56:29.68#ibcon#read 6, iclass 22, count 0 2006.217.07:56:29.68#ibcon#end of sib2, iclass 22, count 0 2006.217.07:56:29.68#ibcon#*after write, iclass 22, count 0 2006.217.07:56:29.68#ibcon#*before return 0, iclass 22, count 0 2006.217.07:56:29.68#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.217.07:56:29.68#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.217.07:56:29.68#ibcon#about to clear, iclass 22 cls_cnt 0 2006.217.07:56:29.68#ibcon#cleared, iclass 22 cls_cnt 0 2006.217.07:56:29.68$vc4f8/va=6,6 2006.217.07:56:29.68#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.217.07:56:29.68#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.217.07:56:29.68#ibcon#ireg 11 cls_cnt 2 2006.217.07:56:29.68#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.217.07:56:29.74#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.217.07:56:29.74#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.217.07:56:29.74#ibcon#enter wrdev, iclass 24, count 2 2006.217.07:56:29.74#ibcon#first serial, iclass 24, count 2 2006.217.07:56:29.74#ibcon#enter sib2, iclass 24, count 2 2006.217.07:56:29.74#ibcon#flushed, iclass 24, count 2 2006.217.07:56:29.74#ibcon#about to write, iclass 24, count 2 2006.217.07:56:29.74#ibcon#wrote, iclass 24, count 2 2006.217.07:56:29.74#ibcon#about to read 3, iclass 24, count 2 2006.217.07:56:29.76#ibcon#read 3, iclass 24, count 2 2006.217.07:56:29.76#ibcon#about to read 4, iclass 24, count 2 2006.217.07:56:29.76#ibcon#read 4, iclass 24, count 2 2006.217.07:56:29.76#ibcon#about to read 5, iclass 24, count 2 2006.217.07:56:29.76#ibcon#read 5, iclass 24, count 2 2006.217.07:56:29.76#ibcon#about to read 6, iclass 24, count 2 2006.217.07:56:29.76#ibcon#read 6, iclass 24, count 2 2006.217.07:56:29.76#ibcon#end of sib2, iclass 24, count 2 2006.217.07:56:29.76#ibcon#*mode == 0, iclass 24, count 2 2006.217.07:56:29.76#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.217.07:56:29.76#ibcon#[25=AT06-06\r\n] 2006.217.07:56:29.76#ibcon#*before write, iclass 24, count 2 2006.217.07:56:29.76#ibcon#enter sib2, iclass 24, count 2 2006.217.07:56:29.76#ibcon#flushed, iclass 24, count 2 2006.217.07:56:29.76#ibcon#about to write, iclass 24, count 2 2006.217.07:56:29.76#ibcon#wrote, iclass 24, count 2 2006.217.07:56:29.76#ibcon#about to read 3, iclass 24, count 2 2006.217.07:56:29.79#ibcon#read 3, iclass 24, count 2 2006.217.07:56:29.79#ibcon#about to read 4, iclass 24, count 2 2006.217.07:56:29.79#ibcon#read 4, iclass 24, count 2 2006.217.07:56:29.79#ibcon#about to read 5, iclass 24, count 2 2006.217.07:56:29.79#ibcon#read 5, iclass 24, count 2 2006.217.07:56:29.79#ibcon#about to read 6, iclass 24, count 2 2006.217.07:56:29.79#ibcon#read 6, iclass 24, count 2 2006.217.07:56:29.79#ibcon#end of sib2, iclass 24, count 2 2006.217.07:56:29.79#ibcon#*after write, iclass 24, count 2 2006.217.07:56:29.79#ibcon#*before return 0, iclass 24, count 2 2006.217.07:56:29.79#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.217.07:56:29.79#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.217.07:56:29.79#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.217.07:56:29.79#ibcon#ireg 7 cls_cnt 0 2006.217.07:56:29.79#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.217.07:56:29.91#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.217.07:56:29.91#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.217.07:56:29.91#ibcon#enter wrdev, iclass 24, count 0 2006.217.07:56:29.91#ibcon#first serial, iclass 24, count 0 2006.217.07:56:29.91#ibcon#enter sib2, iclass 24, count 0 2006.217.07:56:29.91#ibcon#flushed, iclass 24, count 0 2006.217.07:56:29.91#ibcon#about to write, iclass 24, count 0 2006.217.07:56:29.91#ibcon#wrote, iclass 24, count 0 2006.217.07:56:29.91#ibcon#about to read 3, iclass 24, count 0 2006.217.07:56:29.93#ibcon#read 3, iclass 24, count 0 2006.217.07:56:29.93#ibcon#about to read 4, iclass 24, count 0 2006.217.07:56:29.93#ibcon#read 4, iclass 24, count 0 2006.217.07:56:29.93#ibcon#about to read 5, iclass 24, count 0 2006.217.07:56:29.93#ibcon#read 5, iclass 24, count 0 2006.217.07:56:29.93#ibcon#about to read 6, iclass 24, count 0 2006.217.07:56:29.93#ibcon#read 6, iclass 24, count 0 2006.217.07:56:29.93#ibcon#end of sib2, iclass 24, count 0 2006.217.07:56:29.93#ibcon#*mode == 0, iclass 24, count 0 2006.217.07:56:29.93#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.217.07:56:29.93#ibcon#[25=USB\r\n] 2006.217.07:56:29.93#ibcon#*before write, iclass 24, count 0 2006.217.07:56:29.93#ibcon#enter sib2, iclass 24, count 0 2006.217.07:56:29.93#ibcon#flushed, iclass 24, count 0 2006.217.07:56:29.93#ibcon#about to write, iclass 24, count 0 2006.217.07:56:29.93#ibcon#wrote, iclass 24, count 0 2006.217.07:56:29.93#ibcon#about to read 3, iclass 24, count 0 2006.217.07:56:29.96#ibcon#read 3, iclass 24, count 0 2006.217.07:56:29.96#ibcon#about to read 4, iclass 24, count 0 2006.217.07:56:29.96#ibcon#read 4, iclass 24, count 0 2006.217.07:56:29.96#ibcon#about to read 5, iclass 24, count 0 2006.217.07:56:29.96#ibcon#read 5, iclass 24, count 0 2006.217.07:56:29.96#ibcon#about to read 6, iclass 24, count 0 2006.217.07:56:29.96#ibcon#read 6, iclass 24, count 0 2006.217.07:56:29.96#ibcon#end of sib2, iclass 24, count 0 2006.217.07:56:29.96#ibcon#*after write, iclass 24, count 0 2006.217.07:56:29.96#ibcon#*before return 0, iclass 24, count 0 2006.217.07:56:29.96#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.217.07:56:29.96#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.217.07:56:29.96#ibcon#about to clear, iclass 24 cls_cnt 0 2006.217.07:56:29.96#ibcon#cleared, iclass 24 cls_cnt 0 2006.217.07:56:29.96$vc4f8/valo=7,832.99 2006.217.07:56:29.96#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.217.07:56:29.96#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.217.07:56:29.96#ibcon#ireg 17 cls_cnt 0 2006.217.07:56:29.96#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.217.07:56:29.96#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.217.07:56:29.96#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.217.07:56:29.96#ibcon#enter wrdev, iclass 26, count 0 2006.217.07:56:29.96#ibcon#first serial, iclass 26, count 0 2006.217.07:56:29.96#ibcon#enter sib2, iclass 26, count 0 2006.217.07:56:29.96#ibcon#flushed, iclass 26, count 0 2006.217.07:56:29.96#ibcon#about to write, iclass 26, count 0 2006.217.07:56:29.96#ibcon#wrote, iclass 26, count 0 2006.217.07:56:29.96#ibcon#about to read 3, iclass 26, count 0 2006.217.07:56:29.98#ibcon#read 3, iclass 26, count 0 2006.217.07:56:29.98#ibcon#about to read 4, iclass 26, count 0 2006.217.07:56:29.98#ibcon#read 4, iclass 26, count 0 2006.217.07:56:29.98#ibcon#about to read 5, iclass 26, count 0 2006.217.07:56:29.98#ibcon#read 5, iclass 26, count 0 2006.217.07:56:29.98#ibcon#about to read 6, iclass 26, count 0 2006.217.07:56:29.98#ibcon#read 6, iclass 26, count 0 2006.217.07:56:29.98#ibcon#end of sib2, iclass 26, count 0 2006.217.07:56:29.98#ibcon#*mode == 0, iclass 26, count 0 2006.217.07:56:29.98#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.217.07:56:29.98#ibcon#[26=FRQ=07,832.99\r\n] 2006.217.07:56:29.98#ibcon#*before write, iclass 26, count 0 2006.217.07:56:29.98#ibcon#enter sib2, iclass 26, count 0 2006.217.07:56:29.98#ibcon#flushed, iclass 26, count 0 2006.217.07:56:29.98#ibcon#about to write, iclass 26, count 0 2006.217.07:56:29.98#ibcon#wrote, iclass 26, count 0 2006.217.07:56:29.98#ibcon#about to read 3, iclass 26, count 0 2006.217.07:56:30.02#ibcon#read 3, iclass 26, count 0 2006.217.07:56:30.02#ibcon#about to read 4, iclass 26, count 0 2006.217.07:56:30.02#ibcon#read 4, iclass 26, count 0 2006.217.07:56:30.02#ibcon#about to read 5, iclass 26, count 0 2006.217.07:56:30.02#ibcon#read 5, iclass 26, count 0 2006.217.07:56:30.02#ibcon#about to read 6, iclass 26, count 0 2006.217.07:56:30.02#ibcon#read 6, iclass 26, count 0 2006.217.07:56:30.02#ibcon#end of sib2, iclass 26, count 0 2006.217.07:56:30.02#ibcon#*after write, iclass 26, count 0 2006.217.07:56:30.02#ibcon#*before return 0, iclass 26, count 0 2006.217.07:56:30.02#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.217.07:56:30.02#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.217.07:56:30.02#ibcon#about to clear, iclass 26 cls_cnt 0 2006.217.07:56:30.02#ibcon#cleared, iclass 26 cls_cnt 0 2006.217.07:56:30.02$vc4f8/va=7,6 2006.217.07:56:30.02#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.217.07:56:30.02#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.217.07:56:30.02#ibcon#ireg 11 cls_cnt 2 2006.217.07:56:30.02#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.217.07:56:30.08#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.217.07:56:30.08#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.217.07:56:30.08#ibcon#enter wrdev, iclass 28, count 2 2006.217.07:56:30.08#ibcon#first serial, iclass 28, count 2 2006.217.07:56:30.08#ibcon#enter sib2, iclass 28, count 2 2006.217.07:56:30.08#ibcon#flushed, iclass 28, count 2 2006.217.07:56:30.08#ibcon#about to write, iclass 28, count 2 2006.217.07:56:30.08#ibcon#wrote, iclass 28, count 2 2006.217.07:56:30.08#ibcon#about to read 3, iclass 28, count 2 2006.217.07:56:30.10#ibcon#read 3, iclass 28, count 2 2006.217.07:56:30.10#ibcon#about to read 4, iclass 28, count 2 2006.217.07:56:30.10#ibcon#read 4, iclass 28, count 2 2006.217.07:56:30.10#ibcon#about to read 5, iclass 28, count 2 2006.217.07:56:30.10#ibcon#read 5, iclass 28, count 2 2006.217.07:56:30.10#ibcon#about to read 6, iclass 28, count 2 2006.217.07:56:30.10#ibcon#read 6, iclass 28, count 2 2006.217.07:56:30.10#ibcon#end of sib2, iclass 28, count 2 2006.217.07:56:30.10#ibcon#*mode == 0, iclass 28, count 2 2006.217.07:56:30.10#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.217.07:56:30.10#ibcon#[25=AT07-06\r\n] 2006.217.07:56:30.10#ibcon#*before write, iclass 28, count 2 2006.217.07:56:30.10#ibcon#enter sib2, iclass 28, count 2 2006.217.07:56:30.10#ibcon#flushed, iclass 28, count 2 2006.217.07:56:30.10#ibcon#about to write, iclass 28, count 2 2006.217.07:56:30.10#ibcon#wrote, iclass 28, count 2 2006.217.07:56:30.10#ibcon#about to read 3, iclass 28, count 2 2006.217.07:56:30.13#ibcon#read 3, iclass 28, count 2 2006.217.07:56:30.13#ibcon#about to read 4, iclass 28, count 2 2006.217.07:56:30.13#ibcon#read 4, iclass 28, count 2 2006.217.07:56:30.13#ibcon#about to read 5, iclass 28, count 2 2006.217.07:56:30.13#ibcon#read 5, iclass 28, count 2 2006.217.07:56:30.13#ibcon#about to read 6, iclass 28, count 2 2006.217.07:56:30.13#ibcon#read 6, iclass 28, count 2 2006.217.07:56:30.13#ibcon#end of sib2, iclass 28, count 2 2006.217.07:56:30.13#ibcon#*after write, iclass 28, count 2 2006.217.07:56:30.13#ibcon#*before return 0, iclass 28, count 2 2006.217.07:56:30.13#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.217.07:56:30.13#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.217.07:56:30.13#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.217.07:56:30.13#ibcon#ireg 7 cls_cnt 0 2006.217.07:56:30.13#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.217.07:56:30.25#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.217.07:56:30.25#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.217.07:56:30.25#ibcon#enter wrdev, iclass 28, count 0 2006.217.07:56:30.25#ibcon#first serial, iclass 28, count 0 2006.217.07:56:30.25#ibcon#enter sib2, iclass 28, count 0 2006.217.07:56:30.25#ibcon#flushed, iclass 28, count 0 2006.217.07:56:30.25#ibcon#about to write, iclass 28, count 0 2006.217.07:56:30.25#ibcon#wrote, iclass 28, count 0 2006.217.07:56:30.25#ibcon#about to read 3, iclass 28, count 0 2006.217.07:56:30.27#ibcon#read 3, iclass 28, count 0 2006.217.07:56:30.27#ibcon#about to read 4, iclass 28, count 0 2006.217.07:56:30.27#ibcon#read 4, iclass 28, count 0 2006.217.07:56:30.27#ibcon#about to read 5, iclass 28, count 0 2006.217.07:56:30.27#ibcon#read 5, iclass 28, count 0 2006.217.07:56:30.27#ibcon#about to read 6, iclass 28, count 0 2006.217.07:56:30.27#ibcon#read 6, iclass 28, count 0 2006.217.07:56:30.27#ibcon#end of sib2, iclass 28, count 0 2006.217.07:56:30.27#ibcon#*mode == 0, iclass 28, count 0 2006.217.07:56:30.27#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.217.07:56:30.27#ibcon#[25=USB\r\n] 2006.217.07:56:30.27#ibcon#*before write, iclass 28, count 0 2006.217.07:56:30.27#ibcon#enter sib2, iclass 28, count 0 2006.217.07:56:30.27#ibcon#flushed, iclass 28, count 0 2006.217.07:56:30.27#ibcon#about to write, iclass 28, count 0 2006.217.07:56:30.27#ibcon#wrote, iclass 28, count 0 2006.217.07:56:30.27#ibcon#about to read 3, iclass 28, count 0 2006.217.07:56:30.30#ibcon#read 3, iclass 28, count 0 2006.217.07:56:30.30#ibcon#about to read 4, iclass 28, count 0 2006.217.07:56:30.30#ibcon#read 4, iclass 28, count 0 2006.217.07:56:30.30#ibcon#about to read 5, iclass 28, count 0 2006.217.07:56:30.30#ibcon#read 5, iclass 28, count 0 2006.217.07:56:30.30#ibcon#about to read 6, iclass 28, count 0 2006.217.07:56:30.30#ibcon#read 6, iclass 28, count 0 2006.217.07:56:30.30#ibcon#end of sib2, iclass 28, count 0 2006.217.07:56:30.30#ibcon#*after write, iclass 28, count 0 2006.217.07:56:30.30#ibcon#*before return 0, iclass 28, count 0 2006.217.07:56:30.30#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.217.07:56:30.30#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.217.07:56:30.30#ibcon#about to clear, iclass 28 cls_cnt 0 2006.217.07:56:30.30#ibcon#cleared, iclass 28 cls_cnt 0 2006.217.07:56:30.30$vc4f8/valo=8,852.99 2006.217.07:56:30.30#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.217.07:56:30.30#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.217.07:56:30.30#ibcon#ireg 17 cls_cnt 0 2006.217.07:56:30.30#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.217.07:56:30.30#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.217.07:56:30.30#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.217.07:56:30.30#ibcon#enter wrdev, iclass 30, count 0 2006.217.07:56:30.30#ibcon#first serial, iclass 30, count 0 2006.217.07:56:30.30#ibcon#enter sib2, iclass 30, count 0 2006.217.07:56:30.30#ibcon#flushed, iclass 30, count 0 2006.217.07:56:30.30#ibcon#about to write, iclass 30, count 0 2006.217.07:56:30.30#ibcon#wrote, iclass 30, count 0 2006.217.07:56:30.30#ibcon#about to read 3, iclass 30, count 0 2006.217.07:56:30.32#ibcon#read 3, iclass 30, count 0 2006.217.07:56:30.32#ibcon#about to read 4, iclass 30, count 0 2006.217.07:56:30.32#ibcon#read 4, iclass 30, count 0 2006.217.07:56:30.32#ibcon#about to read 5, iclass 30, count 0 2006.217.07:56:30.32#ibcon#read 5, iclass 30, count 0 2006.217.07:56:30.32#ibcon#about to read 6, iclass 30, count 0 2006.217.07:56:30.32#ibcon#read 6, iclass 30, count 0 2006.217.07:56:30.32#ibcon#end of sib2, iclass 30, count 0 2006.217.07:56:30.32#ibcon#*mode == 0, iclass 30, count 0 2006.217.07:56:30.32#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.217.07:56:30.32#ibcon#[26=FRQ=08,852.99\r\n] 2006.217.07:56:30.32#ibcon#*before write, iclass 30, count 0 2006.217.07:56:30.32#ibcon#enter sib2, iclass 30, count 0 2006.217.07:56:30.32#ibcon#flushed, iclass 30, count 0 2006.217.07:56:30.32#ibcon#about to write, iclass 30, count 0 2006.217.07:56:30.32#ibcon#wrote, iclass 30, count 0 2006.217.07:56:30.32#ibcon#about to read 3, iclass 30, count 0 2006.217.07:56:30.36#ibcon#read 3, iclass 30, count 0 2006.217.07:56:30.36#ibcon#about to read 4, iclass 30, count 0 2006.217.07:56:30.36#ibcon#read 4, iclass 30, count 0 2006.217.07:56:30.36#ibcon#about to read 5, iclass 30, count 0 2006.217.07:56:30.36#ibcon#read 5, iclass 30, count 0 2006.217.07:56:30.36#ibcon#about to read 6, iclass 30, count 0 2006.217.07:56:30.36#ibcon#read 6, iclass 30, count 0 2006.217.07:56:30.36#ibcon#end of sib2, iclass 30, count 0 2006.217.07:56:30.36#ibcon#*after write, iclass 30, count 0 2006.217.07:56:30.36#ibcon#*before return 0, iclass 30, count 0 2006.217.07:56:30.36#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.217.07:56:30.36#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.217.07:56:30.36#ibcon#about to clear, iclass 30 cls_cnt 0 2006.217.07:56:30.36#ibcon#cleared, iclass 30 cls_cnt 0 2006.217.07:56:30.36$vc4f8/va=8,7 2006.217.07:56:30.36#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.217.07:56:30.36#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.217.07:56:30.36#ibcon#ireg 11 cls_cnt 2 2006.217.07:56:30.36#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.217.07:56:30.43#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.217.07:56:30.43#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.217.07:56:30.43#ibcon#enter wrdev, iclass 32, count 2 2006.217.07:56:30.43#ibcon#first serial, iclass 32, count 2 2006.217.07:56:30.43#ibcon#enter sib2, iclass 32, count 2 2006.217.07:56:30.43#ibcon#flushed, iclass 32, count 2 2006.217.07:56:30.43#ibcon#about to write, iclass 32, count 2 2006.217.07:56:30.43#ibcon#wrote, iclass 32, count 2 2006.217.07:56:30.43#ibcon#about to read 3, iclass 32, count 2 2006.217.07:56:30.44#ibcon#read 3, iclass 32, count 2 2006.217.07:56:30.44#ibcon#about to read 4, iclass 32, count 2 2006.217.07:56:30.44#ibcon#read 4, iclass 32, count 2 2006.217.07:56:30.44#ibcon#about to read 5, iclass 32, count 2 2006.217.07:56:30.44#ibcon#read 5, iclass 32, count 2 2006.217.07:56:30.44#ibcon#about to read 6, iclass 32, count 2 2006.217.07:56:30.44#ibcon#read 6, iclass 32, count 2 2006.217.07:56:30.44#ibcon#end of sib2, iclass 32, count 2 2006.217.07:56:30.44#ibcon#*mode == 0, iclass 32, count 2 2006.217.07:56:30.44#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.217.07:56:30.44#ibcon#[25=AT08-07\r\n] 2006.217.07:56:30.44#ibcon#*before write, iclass 32, count 2 2006.217.07:56:30.44#ibcon#enter sib2, iclass 32, count 2 2006.217.07:56:30.44#ibcon#flushed, iclass 32, count 2 2006.217.07:56:30.44#ibcon#about to write, iclass 32, count 2 2006.217.07:56:30.44#ibcon#wrote, iclass 32, count 2 2006.217.07:56:30.44#ibcon#about to read 3, iclass 32, count 2 2006.217.07:56:30.47#ibcon#read 3, iclass 32, count 2 2006.217.07:56:30.47#ibcon#about to read 4, iclass 32, count 2 2006.217.07:56:30.47#ibcon#read 4, iclass 32, count 2 2006.217.07:56:30.47#ibcon#about to read 5, iclass 32, count 2 2006.217.07:56:30.47#ibcon#read 5, iclass 32, count 2 2006.217.07:56:30.47#ibcon#about to read 6, iclass 32, count 2 2006.217.07:56:30.47#ibcon#read 6, iclass 32, count 2 2006.217.07:56:30.47#ibcon#end of sib2, iclass 32, count 2 2006.217.07:56:30.47#ibcon#*after write, iclass 32, count 2 2006.217.07:56:30.47#ibcon#*before return 0, iclass 32, count 2 2006.217.07:56:30.47#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.217.07:56:30.47#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.217.07:56:30.47#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.217.07:56:30.47#ibcon#ireg 7 cls_cnt 0 2006.217.07:56:30.47#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.217.07:56:30.59#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.217.07:56:30.59#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.217.07:56:30.59#ibcon#enter wrdev, iclass 32, count 0 2006.217.07:56:30.59#ibcon#first serial, iclass 32, count 0 2006.217.07:56:30.59#ibcon#enter sib2, iclass 32, count 0 2006.217.07:56:30.59#ibcon#flushed, iclass 32, count 0 2006.217.07:56:30.59#ibcon#about to write, iclass 32, count 0 2006.217.07:56:30.59#ibcon#wrote, iclass 32, count 0 2006.217.07:56:30.59#ibcon#about to read 3, iclass 32, count 0 2006.217.07:56:30.61#ibcon#read 3, iclass 32, count 0 2006.217.07:56:30.61#ibcon#about to read 4, iclass 32, count 0 2006.217.07:56:30.61#ibcon#read 4, iclass 32, count 0 2006.217.07:56:30.61#ibcon#about to read 5, iclass 32, count 0 2006.217.07:56:30.61#ibcon#read 5, iclass 32, count 0 2006.217.07:56:30.61#ibcon#about to read 6, iclass 32, count 0 2006.217.07:56:30.61#ibcon#read 6, iclass 32, count 0 2006.217.07:56:30.61#ibcon#end of sib2, iclass 32, count 0 2006.217.07:56:30.61#ibcon#*mode == 0, iclass 32, count 0 2006.217.07:56:30.61#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.217.07:56:30.61#ibcon#[25=USB\r\n] 2006.217.07:56:30.61#ibcon#*before write, iclass 32, count 0 2006.217.07:56:30.61#ibcon#enter sib2, iclass 32, count 0 2006.217.07:56:30.61#ibcon#flushed, iclass 32, count 0 2006.217.07:56:30.61#ibcon#about to write, iclass 32, count 0 2006.217.07:56:30.61#ibcon#wrote, iclass 32, count 0 2006.217.07:56:30.61#ibcon#about to read 3, iclass 32, count 0 2006.217.07:56:30.64#ibcon#read 3, iclass 32, count 0 2006.217.07:56:30.64#ibcon#about to read 4, iclass 32, count 0 2006.217.07:56:30.64#ibcon#read 4, iclass 32, count 0 2006.217.07:56:30.64#ibcon#about to read 5, iclass 32, count 0 2006.217.07:56:30.64#ibcon#read 5, iclass 32, count 0 2006.217.07:56:30.64#ibcon#about to read 6, iclass 32, count 0 2006.217.07:56:30.64#ibcon#read 6, iclass 32, count 0 2006.217.07:56:30.64#ibcon#end of sib2, iclass 32, count 0 2006.217.07:56:30.64#ibcon#*after write, iclass 32, count 0 2006.217.07:56:30.64#ibcon#*before return 0, iclass 32, count 0 2006.217.07:56:30.64#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.217.07:56:30.64#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.217.07:56:30.64#ibcon#about to clear, iclass 32 cls_cnt 0 2006.217.07:56:30.64#ibcon#cleared, iclass 32 cls_cnt 0 2006.217.07:56:30.64$vc4f8/vblo=1,632.99 2006.217.07:56:30.64#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.217.07:56:30.64#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.217.07:56:30.64#ibcon#ireg 17 cls_cnt 0 2006.217.07:56:30.64#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.217.07:56:30.64#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.217.07:56:30.64#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.217.07:56:30.64#ibcon#enter wrdev, iclass 34, count 0 2006.217.07:56:30.64#ibcon#first serial, iclass 34, count 0 2006.217.07:56:30.64#ibcon#enter sib2, iclass 34, count 0 2006.217.07:56:30.64#ibcon#flushed, iclass 34, count 0 2006.217.07:56:30.64#ibcon#about to write, iclass 34, count 0 2006.217.07:56:30.64#ibcon#wrote, iclass 34, count 0 2006.217.07:56:30.64#ibcon#about to read 3, iclass 34, count 0 2006.217.07:56:30.66#ibcon#read 3, iclass 34, count 0 2006.217.07:56:30.66#ibcon#about to read 4, iclass 34, count 0 2006.217.07:56:30.66#ibcon#read 4, iclass 34, count 0 2006.217.07:56:30.66#ibcon#about to read 5, iclass 34, count 0 2006.217.07:56:30.66#ibcon#read 5, iclass 34, count 0 2006.217.07:56:30.66#ibcon#about to read 6, iclass 34, count 0 2006.217.07:56:30.66#ibcon#read 6, iclass 34, count 0 2006.217.07:56:30.66#ibcon#end of sib2, iclass 34, count 0 2006.217.07:56:30.66#ibcon#*mode == 0, iclass 34, count 0 2006.217.07:56:30.66#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.217.07:56:30.66#ibcon#[28=FRQ=01,632.99\r\n] 2006.217.07:56:30.66#ibcon#*before write, iclass 34, count 0 2006.217.07:56:30.66#ibcon#enter sib2, iclass 34, count 0 2006.217.07:56:30.66#ibcon#flushed, iclass 34, count 0 2006.217.07:56:30.66#ibcon#about to write, iclass 34, count 0 2006.217.07:56:30.66#ibcon#wrote, iclass 34, count 0 2006.217.07:56:30.66#ibcon#about to read 3, iclass 34, count 0 2006.217.07:56:30.70#ibcon#read 3, iclass 34, count 0 2006.217.07:56:30.70#ibcon#about to read 4, iclass 34, count 0 2006.217.07:56:30.70#ibcon#read 4, iclass 34, count 0 2006.217.07:56:30.70#ibcon#about to read 5, iclass 34, count 0 2006.217.07:56:30.70#ibcon#read 5, iclass 34, count 0 2006.217.07:56:30.70#ibcon#about to read 6, iclass 34, count 0 2006.217.07:56:30.70#ibcon#read 6, iclass 34, count 0 2006.217.07:56:30.70#ibcon#end of sib2, iclass 34, count 0 2006.217.07:56:30.70#ibcon#*after write, iclass 34, count 0 2006.217.07:56:30.70#ibcon#*before return 0, iclass 34, count 0 2006.217.07:56:30.70#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.217.07:56:30.70#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.217.07:56:30.70#ibcon#about to clear, iclass 34 cls_cnt 0 2006.217.07:56:30.70#ibcon#cleared, iclass 34 cls_cnt 0 2006.217.07:56:30.70$vc4f8/vb=1,4 2006.217.07:56:30.70#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.217.07:56:30.70#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.217.07:56:30.70#ibcon#ireg 11 cls_cnt 2 2006.217.07:56:30.70#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.217.07:56:30.70#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.217.07:56:30.70#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.217.07:56:30.70#ibcon#enter wrdev, iclass 36, count 2 2006.217.07:56:30.70#ibcon#first serial, iclass 36, count 2 2006.217.07:56:30.70#ibcon#enter sib2, iclass 36, count 2 2006.217.07:56:30.70#ibcon#flushed, iclass 36, count 2 2006.217.07:56:30.70#ibcon#about to write, iclass 36, count 2 2006.217.07:56:30.70#ibcon#wrote, iclass 36, count 2 2006.217.07:56:30.70#ibcon#about to read 3, iclass 36, count 2 2006.217.07:56:30.72#ibcon#read 3, iclass 36, count 2 2006.217.07:56:30.72#ibcon#about to read 4, iclass 36, count 2 2006.217.07:56:30.72#ibcon#read 4, iclass 36, count 2 2006.217.07:56:30.72#ibcon#about to read 5, iclass 36, count 2 2006.217.07:56:30.72#ibcon#read 5, iclass 36, count 2 2006.217.07:56:30.72#ibcon#about to read 6, iclass 36, count 2 2006.217.07:56:30.72#ibcon#read 6, iclass 36, count 2 2006.217.07:56:30.72#ibcon#end of sib2, iclass 36, count 2 2006.217.07:56:30.72#ibcon#*mode == 0, iclass 36, count 2 2006.217.07:56:30.72#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.217.07:56:30.72#ibcon#[27=AT01-04\r\n] 2006.217.07:56:30.72#ibcon#*before write, iclass 36, count 2 2006.217.07:56:30.72#ibcon#enter sib2, iclass 36, count 2 2006.217.07:56:30.72#ibcon#flushed, iclass 36, count 2 2006.217.07:56:30.72#ibcon#about to write, iclass 36, count 2 2006.217.07:56:30.72#ibcon#wrote, iclass 36, count 2 2006.217.07:56:30.72#ibcon#about to read 3, iclass 36, count 2 2006.217.07:56:30.75#ibcon#read 3, iclass 36, count 2 2006.217.07:56:30.75#ibcon#about to read 4, iclass 36, count 2 2006.217.07:56:30.75#ibcon#read 4, iclass 36, count 2 2006.217.07:56:30.75#ibcon#about to read 5, iclass 36, count 2 2006.217.07:56:30.75#ibcon#read 5, iclass 36, count 2 2006.217.07:56:30.75#ibcon#about to read 6, iclass 36, count 2 2006.217.07:56:30.75#ibcon#read 6, iclass 36, count 2 2006.217.07:56:30.75#ibcon#end of sib2, iclass 36, count 2 2006.217.07:56:30.75#ibcon#*after write, iclass 36, count 2 2006.217.07:56:30.75#ibcon#*before return 0, iclass 36, count 2 2006.217.07:56:30.75#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.217.07:56:30.75#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.217.07:56:30.75#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.217.07:56:30.75#ibcon#ireg 7 cls_cnt 0 2006.217.07:56:30.75#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.217.07:56:30.87#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.217.07:56:30.87#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.217.07:56:30.87#ibcon#enter wrdev, iclass 36, count 0 2006.217.07:56:30.87#ibcon#first serial, iclass 36, count 0 2006.217.07:56:30.87#ibcon#enter sib2, iclass 36, count 0 2006.217.07:56:30.87#ibcon#flushed, iclass 36, count 0 2006.217.07:56:30.87#ibcon#about to write, iclass 36, count 0 2006.217.07:56:30.87#ibcon#wrote, iclass 36, count 0 2006.217.07:56:30.87#ibcon#about to read 3, iclass 36, count 0 2006.217.07:56:30.89#ibcon#read 3, iclass 36, count 0 2006.217.07:56:30.89#ibcon#about to read 4, iclass 36, count 0 2006.217.07:56:30.89#ibcon#read 4, iclass 36, count 0 2006.217.07:56:30.89#ibcon#about to read 5, iclass 36, count 0 2006.217.07:56:30.89#ibcon#read 5, iclass 36, count 0 2006.217.07:56:30.89#ibcon#about to read 6, iclass 36, count 0 2006.217.07:56:30.89#ibcon#read 6, iclass 36, count 0 2006.217.07:56:30.89#ibcon#end of sib2, iclass 36, count 0 2006.217.07:56:30.89#ibcon#*mode == 0, iclass 36, count 0 2006.217.07:56:30.89#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.217.07:56:30.89#ibcon#[27=USB\r\n] 2006.217.07:56:30.89#ibcon#*before write, iclass 36, count 0 2006.217.07:56:30.89#ibcon#enter sib2, iclass 36, count 0 2006.217.07:56:30.89#ibcon#flushed, iclass 36, count 0 2006.217.07:56:30.89#ibcon#about to write, iclass 36, count 0 2006.217.07:56:30.89#ibcon#wrote, iclass 36, count 0 2006.217.07:56:30.89#ibcon#about to read 3, iclass 36, count 0 2006.217.07:56:30.92#ibcon#read 3, iclass 36, count 0 2006.217.07:56:30.92#ibcon#about to read 4, iclass 36, count 0 2006.217.07:56:30.92#ibcon#read 4, iclass 36, count 0 2006.217.07:56:30.92#ibcon#about to read 5, iclass 36, count 0 2006.217.07:56:30.92#ibcon#read 5, iclass 36, count 0 2006.217.07:56:30.92#ibcon#about to read 6, iclass 36, count 0 2006.217.07:56:30.92#ibcon#read 6, iclass 36, count 0 2006.217.07:56:30.92#ibcon#end of sib2, iclass 36, count 0 2006.217.07:56:30.92#ibcon#*after write, iclass 36, count 0 2006.217.07:56:30.92#ibcon#*before return 0, iclass 36, count 0 2006.217.07:56:30.92#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.217.07:56:30.92#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.217.07:56:30.92#ibcon#about to clear, iclass 36 cls_cnt 0 2006.217.07:56:30.92#ibcon#cleared, iclass 36 cls_cnt 0 2006.217.07:56:30.92$vc4f8/vblo=2,640.99 2006.217.07:56:30.92#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.217.07:56:30.92#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.217.07:56:30.92#ibcon#ireg 17 cls_cnt 0 2006.217.07:56:30.92#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.217.07:56:30.92#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.217.07:56:30.92#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.217.07:56:30.92#ibcon#enter wrdev, iclass 38, count 0 2006.217.07:56:30.92#ibcon#first serial, iclass 38, count 0 2006.217.07:56:30.92#ibcon#enter sib2, iclass 38, count 0 2006.217.07:56:30.92#ibcon#flushed, iclass 38, count 0 2006.217.07:56:30.92#ibcon#about to write, iclass 38, count 0 2006.217.07:56:30.92#ibcon#wrote, iclass 38, count 0 2006.217.07:56:30.92#ibcon#about to read 3, iclass 38, count 0 2006.217.07:56:30.94#ibcon#read 3, iclass 38, count 0 2006.217.07:56:30.94#ibcon#about to read 4, iclass 38, count 0 2006.217.07:56:30.94#ibcon#read 4, iclass 38, count 0 2006.217.07:56:30.94#ibcon#about to read 5, iclass 38, count 0 2006.217.07:56:30.94#ibcon#read 5, iclass 38, count 0 2006.217.07:56:30.94#ibcon#about to read 6, iclass 38, count 0 2006.217.07:56:30.94#ibcon#read 6, iclass 38, count 0 2006.217.07:56:30.94#ibcon#end of sib2, iclass 38, count 0 2006.217.07:56:30.94#ibcon#*mode == 0, iclass 38, count 0 2006.217.07:56:30.94#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.217.07:56:30.94#ibcon#[28=FRQ=02,640.99\r\n] 2006.217.07:56:30.94#ibcon#*before write, iclass 38, count 0 2006.217.07:56:30.94#ibcon#enter sib2, iclass 38, count 0 2006.217.07:56:30.94#ibcon#flushed, iclass 38, count 0 2006.217.07:56:30.94#ibcon#about to write, iclass 38, count 0 2006.217.07:56:30.94#ibcon#wrote, iclass 38, count 0 2006.217.07:56:30.94#ibcon#about to read 3, iclass 38, count 0 2006.217.07:56:30.98#ibcon#read 3, iclass 38, count 0 2006.217.07:56:30.98#ibcon#about to read 4, iclass 38, count 0 2006.217.07:56:30.98#ibcon#read 4, iclass 38, count 0 2006.217.07:56:30.98#ibcon#about to read 5, iclass 38, count 0 2006.217.07:56:30.98#ibcon#read 5, iclass 38, count 0 2006.217.07:56:30.98#ibcon#about to read 6, iclass 38, count 0 2006.217.07:56:30.98#ibcon#read 6, iclass 38, count 0 2006.217.07:56:30.98#ibcon#end of sib2, iclass 38, count 0 2006.217.07:56:30.98#ibcon#*after write, iclass 38, count 0 2006.217.07:56:30.98#ibcon#*before return 0, iclass 38, count 0 2006.217.07:56:30.98#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.217.07:56:30.98#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.217.07:56:30.98#ibcon#about to clear, iclass 38 cls_cnt 0 2006.217.07:56:30.98#ibcon#cleared, iclass 38 cls_cnt 0 2006.217.07:56:30.98$vc4f8/vb=2,4 2006.217.07:56:30.98#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.217.07:56:30.98#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.217.07:56:30.98#ibcon#ireg 11 cls_cnt 2 2006.217.07:56:30.98#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.217.07:56:31.04#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.217.07:56:31.04#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.217.07:56:31.04#ibcon#enter wrdev, iclass 40, count 2 2006.217.07:56:31.04#ibcon#first serial, iclass 40, count 2 2006.217.07:56:31.04#ibcon#enter sib2, iclass 40, count 2 2006.217.07:56:31.04#ibcon#flushed, iclass 40, count 2 2006.217.07:56:31.04#ibcon#about to write, iclass 40, count 2 2006.217.07:56:31.04#ibcon#wrote, iclass 40, count 2 2006.217.07:56:31.04#ibcon#about to read 3, iclass 40, count 2 2006.217.07:56:31.06#ibcon#read 3, iclass 40, count 2 2006.217.07:56:31.06#ibcon#about to read 4, iclass 40, count 2 2006.217.07:56:31.06#ibcon#read 4, iclass 40, count 2 2006.217.07:56:31.06#ibcon#about to read 5, iclass 40, count 2 2006.217.07:56:31.06#ibcon#read 5, iclass 40, count 2 2006.217.07:56:31.06#ibcon#about to read 6, iclass 40, count 2 2006.217.07:56:31.06#ibcon#read 6, iclass 40, count 2 2006.217.07:56:31.06#ibcon#end of sib2, iclass 40, count 2 2006.217.07:56:31.06#ibcon#*mode == 0, iclass 40, count 2 2006.217.07:56:31.06#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.217.07:56:31.06#ibcon#[27=AT02-04\r\n] 2006.217.07:56:31.06#ibcon#*before write, iclass 40, count 2 2006.217.07:56:31.06#ibcon#enter sib2, iclass 40, count 2 2006.217.07:56:31.06#ibcon#flushed, iclass 40, count 2 2006.217.07:56:31.06#ibcon#about to write, iclass 40, count 2 2006.217.07:56:31.06#ibcon#wrote, iclass 40, count 2 2006.217.07:56:31.06#ibcon#about to read 3, iclass 40, count 2 2006.217.07:56:31.09#ibcon#read 3, iclass 40, count 2 2006.217.07:56:31.09#ibcon#about to read 4, iclass 40, count 2 2006.217.07:56:31.09#ibcon#read 4, iclass 40, count 2 2006.217.07:56:31.09#ibcon#about to read 5, iclass 40, count 2 2006.217.07:56:31.09#ibcon#read 5, iclass 40, count 2 2006.217.07:56:31.09#ibcon#about to read 6, iclass 40, count 2 2006.217.07:56:31.09#ibcon#read 6, iclass 40, count 2 2006.217.07:56:31.09#ibcon#end of sib2, iclass 40, count 2 2006.217.07:56:31.09#ibcon#*after write, iclass 40, count 2 2006.217.07:56:31.09#ibcon#*before return 0, iclass 40, count 2 2006.217.07:56:31.09#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.217.07:56:31.09#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.217.07:56:31.09#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.217.07:56:31.09#ibcon#ireg 7 cls_cnt 0 2006.217.07:56:31.09#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.217.07:56:31.21#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.217.07:56:31.21#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.217.07:56:31.21#ibcon#enter wrdev, iclass 40, count 0 2006.217.07:56:31.21#ibcon#first serial, iclass 40, count 0 2006.217.07:56:31.21#ibcon#enter sib2, iclass 40, count 0 2006.217.07:56:31.21#ibcon#flushed, iclass 40, count 0 2006.217.07:56:31.21#ibcon#about to write, iclass 40, count 0 2006.217.07:56:31.21#ibcon#wrote, iclass 40, count 0 2006.217.07:56:31.21#ibcon#about to read 3, iclass 40, count 0 2006.217.07:56:31.23#ibcon#read 3, iclass 40, count 0 2006.217.07:56:31.23#ibcon#about to read 4, iclass 40, count 0 2006.217.07:56:31.23#ibcon#read 4, iclass 40, count 0 2006.217.07:56:31.23#ibcon#about to read 5, iclass 40, count 0 2006.217.07:56:31.23#ibcon#read 5, iclass 40, count 0 2006.217.07:56:31.23#ibcon#about to read 6, iclass 40, count 0 2006.217.07:56:31.23#ibcon#read 6, iclass 40, count 0 2006.217.07:56:31.23#ibcon#end of sib2, iclass 40, count 0 2006.217.07:56:31.23#ibcon#*mode == 0, iclass 40, count 0 2006.217.07:56:31.23#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.217.07:56:31.23#ibcon#[27=USB\r\n] 2006.217.07:56:31.23#ibcon#*before write, iclass 40, count 0 2006.217.07:56:31.23#ibcon#enter sib2, iclass 40, count 0 2006.217.07:56:31.23#ibcon#flushed, iclass 40, count 0 2006.217.07:56:31.23#ibcon#about to write, iclass 40, count 0 2006.217.07:56:31.23#ibcon#wrote, iclass 40, count 0 2006.217.07:56:31.23#ibcon#about to read 3, iclass 40, count 0 2006.217.07:56:31.26#ibcon#read 3, iclass 40, count 0 2006.217.07:56:31.26#ibcon#about to read 4, iclass 40, count 0 2006.217.07:56:31.26#ibcon#read 4, iclass 40, count 0 2006.217.07:56:31.26#ibcon#about to read 5, iclass 40, count 0 2006.217.07:56:31.26#ibcon#read 5, iclass 40, count 0 2006.217.07:56:31.26#ibcon#about to read 6, iclass 40, count 0 2006.217.07:56:31.26#ibcon#read 6, iclass 40, count 0 2006.217.07:56:31.26#ibcon#end of sib2, iclass 40, count 0 2006.217.07:56:31.26#ibcon#*after write, iclass 40, count 0 2006.217.07:56:31.26#ibcon#*before return 0, iclass 40, count 0 2006.217.07:56:31.26#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.217.07:56:31.26#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.217.07:56:31.26#ibcon#about to clear, iclass 40 cls_cnt 0 2006.217.07:56:31.26#ibcon#cleared, iclass 40 cls_cnt 0 2006.217.07:56:31.26$vc4f8/vblo=3,656.99 2006.217.07:56:31.26#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.217.07:56:31.26#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.217.07:56:31.26#ibcon#ireg 17 cls_cnt 0 2006.217.07:56:31.26#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.217.07:56:31.26#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.217.07:56:31.26#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.217.07:56:31.26#ibcon#enter wrdev, iclass 4, count 0 2006.217.07:56:31.26#ibcon#first serial, iclass 4, count 0 2006.217.07:56:31.26#ibcon#enter sib2, iclass 4, count 0 2006.217.07:56:31.26#ibcon#flushed, iclass 4, count 0 2006.217.07:56:31.26#ibcon#about to write, iclass 4, count 0 2006.217.07:56:31.26#ibcon#wrote, iclass 4, count 0 2006.217.07:56:31.26#ibcon#about to read 3, iclass 4, count 0 2006.217.07:56:31.28#ibcon#read 3, iclass 4, count 0 2006.217.07:56:31.28#ibcon#about to read 4, iclass 4, count 0 2006.217.07:56:31.28#ibcon#read 4, iclass 4, count 0 2006.217.07:56:31.28#ibcon#about to read 5, iclass 4, count 0 2006.217.07:56:31.28#ibcon#read 5, iclass 4, count 0 2006.217.07:56:31.28#ibcon#about to read 6, iclass 4, count 0 2006.217.07:56:31.28#ibcon#read 6, iclass 4, count 0 2006.217.07:56:31.28#ibcon#end of sib2, iclass 4, count 0 2006.217.07:56:31.28#ibcon#*mode == 0, iclass 4, count 0 2006.217.07:56:31.28#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.217.07:56:31.28#ibcon#[28=FRQ=03,656.99\r\n] 2006.217.07:56:31.28#ibcon#*before write, iclass 4, count 0 2006.217.07:56:31.28#ibcon#enter sib2, iclass 4, count 0 2006.217.07:56:31.28#ibcon#flushed, iclass 4, count 0 2006.217.07:56:31.28#ibcon#about to write, iclass 4, count 0 2006.217.07:56:31.28#ibcon#wrote, iclass 4, count 0 2006.217.07:56:31.28#ibcon#about to read 3, iclass 4, count 0 2006.217.07:56:31.32#ibcon#read 3, iclass 4, count 0 2006.217.07:56:31.32#ibcon#about to read 4, iclass 4, count 0 2006.217.07:56:31.32#ibcon#read 4, iclass 4, count 0 2006.217.07:56:31.32#ibcon#about to read 5, iclass 4, count 0 2006.217.07:56:31.32#ibcon#read 5, iclass 4, count 0 2006.217.07:56:31.32#ibcon#about to read 6, iclass 4, count 0 2006.217.07:56:31.32#ibcon#read 6, iclass 4, count 0 2006.217.07:56:31.32#ibcon#end of sib2, iclass 4, count 0 2006.217.07:56:31.32#ibcon#*after write, iclass 4, count 0 2006.217.07:56:31.32#ibcon#*before return 0, iclass 4, count 0 2006.217.07:56:31.32#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.217.07:56:31.32#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.217.07:56:31.32#ibcon#about to clear, iclass 4 cls_cnt 0 2006.217.07:56:31.32#ibcon#cleared, iclass 4 cls_cnt 0 2006.217.07:56:31.32$vc4f8/vb=3,4 2006.217.07:56:31.32#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.217.07:56:31.32#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.217.07:56:31.32#ibcon#ireg 11 cls_cnt 2 2006.217.07:56:31.32#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.217.07:56:31.38#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.217.07:56:31.38#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.217.07:56:31.38#ibcon#enter wrdev, iclass 6, count 2 2006.217.07:56:31.38#ibcon#first serial, iclass 6, count 2 2006.217.07:56:31.38#ibcon#enter sib2, iclass 6, count 2 2006.217.07:56:31.38#ibcon#flushed, iclass 6, count 2 2006.217.07:56:31.38#ibcon#about to write, iclass 6, count 2 2006.217.07:56:31.38#ibcon#wrote, iclass 6, count 2 2006.217.07:56:31.38#ibcon#about to read 3, iclass 6, count 2 2006.217.07:56:31.40#ibcon#read 3, iclass 6, count 2 2006.217.07:56:31.40#ibcon#about to read 4, iclass 6, count 2 2006.217.07:56:31.40#ibcon#read 4, iclass 6, count 2 2006.217.07:56:31.40#ibcon#about to read 5, iclass 6, count 2 2006.217.07:56:31.40#ibcon#read 5, iclass 6, count 2 2006.217.07:56:31.40#ibcon#about to read 6, iclass 6, count 2 2006.217.07:56:31.40#ibcon#read 6, iclass 6, count 2 2006.217.07:56:31.40#ibcon#end of sib2, iclass 6, count 2 2006.217.07:56:31.40#ibcon#*mode == 0, iclass 6, count 2 2006.217.07:56:31.40#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.217.07:56:31.40#ibcon#[27=AT03-04\r\n] 2006.217.07:56:31.40#ibcon#*before write, iclass 6, count 2 2006.217.07:56:31.40#ibcon#enter sib2, iclass 6, count 2 2006.217.07:56:31.40#ibcon#flushed, iclass 6, count 2 2006.217.07:56:31.40#ibcon#about to write, iclass 6, count 2 2006.217.07:56:31.40#ibcon#wrote, iclass 6, count 2 2006.217.07:56:31.40#ibcon#about to read 3, iclass 6, count 2 2006.217.07:56:31.43#ibcon#read 3, iclass 6, count 2 2006.217.07:56:31.43#ibcon#about to read 4, iclass 6, count 2 2006.217.07:56:31.43#ibcon#read 4, iclass 6, count 2 2006.217.07:56:31.43#ibcon#about to read 5, iclass 6, count 2 2006.217.07:56:31.43#ibcon#read 5, iclass 6, count 2 2006.217.07:56:31.43#ibcon#about to read 6, iclass 6, count 2 2006.217.07:56:31.43#ibcon#read 6, iclass 6, count 2 2006.217.07:56:31.43#ibcon#end of sib2, iclass 6, count 2 2006.217.07:56:31.43#ibcon#*after write, iclass 6, count 2 2006.217.07:56:31.43#ibcon#*before return 0, iclass 6, count 2 2006.217.07:56:31.43#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.217.07:56:31.43#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.217.07:56:31.43#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.217.07:56:31.43#ibcon#ireg 7 cls_cnt 0 2006.217.07:56:31.43#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.217.07:56:31.55#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.217.07:56:31.55#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.217.07:56:31.55#ibcon#enter wrdev, iclass 6, count 0 2006.217.07:56:31.55#ibcon#first serial, iclass 6, count 0 2006.217.07:56:31.55#ibcon#enter sib2, iclass 6, count 0 2006.217.07:56:31.55#ibcon#flushed, iclass 6, count 0 2006.217.07:56:31.55#ibcon#about to write, iclass 6, count 0 2006.217.07:56:31.55#ibcon#wrote, iclass 6, count 0 2006.217.07:56:31.55#ibcon#about to read 3, iclass 6, count 0 2006.217.07:56:31.57#ibcon#read 3, iclass 6, count 0 2006.217.07:56:31.57#ibcon#about to read 4, iclass 6, count 0 2006.217.07:56:31.57#ibcon#read 4, iclass 6, count 0 2006.217.07:56:31.57#ibcon#about to read 5, iclass 6, count 0 2006.217.07:56:31.57#ibcon#read 5, iclass 6, count 0 2006.217.07:56:31.57#ibcon#about to read 6, iclass 6, count 0 2006.217.07:56:31.57#ibcon#read 6, iclass 6, count 0 2006.217.07:56:31.57#ibcon#end of sib2, iclass 6, count 0 2006.217.07:56:31.57#ibcon#*mode == 0, iclass 6, count 0 2006.217.07:56:31.57#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.217.07:56:31.57#ibcon#[27=USB\r\n] 2006.217.07:56:31.57#ibcon#*before write, iclass 6, count 0 2006.217.07:56:31.57#ibcon#enter sib2, iclass 6, count 0 2006.217.07:56:31.57#ibcon#flushed, iclass 6, count 0 2006.217.07:56:31.57#ibcon#about to write, iclass 6, count 0 2006.217.07:56:31.57#ibcon#wrote, iclass 6, count 0 2006.217.07:56:31.57#ibcon#about to read 3, iclass 6, count 0 2006.217.07:56:31.60#ibcon#read 3, iclass 6, count 0 2006.217.07:56:31.60#ibcon#about to read 4, iclass 6, count 0 2006.217.07:56:31.60#ibcon#read 4, iclass 6, count 0 2006.217.07:56:31.60#ibcon#about to read 5, iclass 6, count 0 2006.217.07:56:31.60#ibcon#read 5, iclass 6, count 0 2006.217.07:56:31.60#ibcon#about to read 6, iclass 6, count 0 2006.217.07:56:31.60#ibcon#read 6, iclass 6, count 0 2006.217.07:56:31.60#ibcon#end of sib2, iclass 6, count 0 2006.217.07:56:31.60#ibcon#*after write, iclass 6, count 0 2006.217.07:56:31.60#ibcon#*before return 0, iclass 6, count 0 2006.217.07:56:31.60#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.217.07:56:31.60#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.217.07:56:31.60#ibcon#about to clear, iclass 6 cls_cnt 0 2006.217.07:56:31.60#ibcon#cleared, iclass 6 cls_cnt 0 2006.217.07:56:31.60$vc4f8/vblo=4,712.99 2006.217.07:56:31.60#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.217.07:56:31.60#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.217.07:56:31.60#ibcon#ireg 17 cls_cnt 0 2006.217.07:56:31.60#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.217.07:56:31.60#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.217.07:56:31.60#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.217.07:56:31.60#ibcon#enter wrdev, iclass 10, count 0 2006.217.07:56:31.60#ibcon#first serial, iclass 10, count 0 2006.217.07:56:31.60#ibcon#enter sib2, iclass 10, count 0 2006.217.07:56:31.60#ibcon#flushed, iclass 10, count 0 2006.217.07:56:31.60#ibcon#about to write, iclass 10, count 0 2006.217.07:56:31.60#ibcon#wrote, iclass 10, count 0 2006.217.07:56:31.60#ibcon#about to read 3, iclass 10, count 0 2006.217.07:56:31.62#ibcon#read 3, iclass 10, count 0 2006.217.07:56:31.62#ibcon#about to read 4, iclass 10, count 0 2006.217.07:56:31.62#ibcon#read 4, iclass 10, count 0 2006.217.07:56:31.62#ibcon#about to read 5, iclass 10, count 0 2006.217.07:56:31.62#ibcon#read 5, iclass 10, count 0 2006.217.07:56:31.62#ibcon#about to read 6, iclass 10, count 0 2006.217.07:56:31.62#ibcon#read 6, iclass 10, count 0 2006.217.07:56:31.62#ibcon#end of sib2, iclass 10, count 0 2006.217.07:56:31.62#ibcon#*mode == 0, iclass 10, count 0 2006.217.07:56:31.62#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.217.07:56:31.62#ibcon#[28=FRQ=04,712.99\r\n] 2006.217.07:56:31.62#ibcon#*before write, iclass 10, count 0 2006.217.07:56:31.62#ibcon#enter sib2, iclass 10, count 0 2006.217.07:56:31.62#ibcon#flushed, iclass 10, count 0 2006.217.07:56:31.62#ibcon#about to write, iclass 10, count 0 2006.217.07:56:31.62#ibcon#wrote, iclass 10, count 0 2006.217.07:56:31.62#ibcon#about to read 3, iclass 10, count 0 2006.217.07:56:31.66#ibcon#read 3, iclass 10, count 0 2006.217.07:56:31.66#ibcon#about to read 4, iclass 10, count 0 2006.217.07:56:31.66#ibcon#read 4, iclass 10, count 0 2006.217.07:56:31.66#ibcon#about to read 5, iclass 10, count 0 2006.217.07:56:31.66#ibcon#read 5, iclass 10, count 0 2006.217.07:56:31.66#ibcon#about to read 6, iclass 10, count 0 2006.217.07:56:31.66#ibcon#read 6, iclass 10, count 0 2006.217.07:56:31.66#ibcon#end of sib2, iclass 10, count 0 2006.217.07:56:31.66#ibcon#*after write, iclass 10, count 0 2006.217.07:56:31.66#ibcon#*before return 0, iclass 10, count 0 2006.217.07:56:31.66#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.217.07:56:31.66#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.217.07:56:31.66#ibcon#about to clear, iclass 10 cls_cnt 0 2006.217.07:56:31.66#ibcon#cleared, iclass 10 cls_cnt 0 2006.217.07:56:31.66$vc4f8/vb=4,4 2006.217.07:56:31.66#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.217.07:56:31.66#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.217.07:56:31.66#ibcon#ireg 11 cls_cnt 2 2006.217.07:56:31.66#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.217.07:56:31.72#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.217.07:56:31.72#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.217.07:56:31.72#ibcon#enter wrdev, iclass 12, count 2 2006.217.07:56:31.72#ibcon#first serial, iclass 12, count 2 2006.217.07:56:31.72#ibcon#enter sib2, iclass 12, count 2 2006.217.07:56:31.72#ibcon#flushed, iclass 12, count 2 2006.217.07:56:31.72#ibcon#about to write, iclass 12, count 2 2006.217.07:56:31.72#ibcon#wrote, iclass 12, count 2 2006.217.07:56:31.72#ibcon#about to read 3, iclass 12, count 2 2006.217.07:56:31.74#ibcon#read 3, iclass 12, count 2 2006.217.07:56:31.74#ibcon#about to read 4, iclass 12, count 2 2006.217.07:56:31.74#ibcon#read 4, iclass 12, count 2 2006.217.07:56:31.74#ibcon#about to read 5, iclass 12, count 2 2006.217.07:56:31.74#ibcon#read 5, iclass 12, count 2 2006.217.07:56:31.74#ibcon#about to read 6, iclass 12, count 2 2006.217.07:56:31.74#ibcon#read 6, iclass 12, count 2 2006.217.07:56:31.74#ibcon#end of sib2, iclass 12, count 2 2006.217.07:56:31.74#ibcon#*mode == 0, iclass 12, count 2 2006.217.07:56:31.74#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.217.07:56:31.74#ibcon#[27=AT04-04\r\n] 2006.217.07:56:31.74#ibcon#*before write, iclass 12, count 2 2006.217.07:56:31.74#ibcon#enter sib2, iclass 12, count 2 2006.217.07:56:31.74#ibcon#flushed, iclass 12, count 2 2006.217.07:56:31.74#ibcon#about to write, iclass 12, count 2 2006.217.07:56:31.74#ibcon#wrote, iclass 12, count 2 2006.217.07:56:31.74#ibcon#about to read 3, iclass 12, count 2 2006.217.07:56:31.77#ibcon#read 3, iclass 12, count 2 2006.217.07:56:31.77#ibcon#about to read 4, iclass 12, count 2 2006.217.07:56:31.77#ibcon#read 4, iclass 12, count 2 2006.217.07:56:31.77#ibcon#about to read 5, iclass 12, count 2 2006.217.07:56:31.77#ibcon#read 5, iclass 12, count 2 2006.217.07:56:31.77#ibcon#about to read 6, iclass 12, count 2 2006.217.07:56:31.77#ibcon#read 6, iclass 12, count 2 2006.217.07:56:31.77#ibcon#end of sib2, iclass 12, count 2 2006.217.07:56:31.77#ibcon#*after write, iclass 12, count 2 2006.217.07:56:31.77#ibcon#*before return 0, iclass 12, count 2 2006.217.07:56:31.77#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.217.07:56:31.77#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.217.07:56:31.77#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.217.07:56:31.77#ibcon#ireg 7 cls_cnt 0 2006.217.07:56:31.77#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.217.07:56:31.89#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.217.07:56:31.89#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.217.07:56:31.89#ibcon#enter wrdev, iclass 12, count 0 2006.217.07:56:31.89#ibcon#first serial, iclass 12, count 0 2006.217.07:56:31.89#ibcon#enter sib2, iclass 12, count 0 2006.217.07:56:31.89#ibcon#flushed, iclass 12, count 0 2006.217.07:56:31.89#ibcon#about to write, iclass 12, count 0 2006.217.07:56:31.89#ibcon#wrote, iclass 12, count 0 2006.217.07:56:31.89#ibcon#about to read 3, iclass 12, count 0 2006.217.07:56:31.91#ibcon#read 3, iclass 12, count 0 2006.217.07:56:31.91#ibcon#about to read 4, iclass 12, count 0 2006.217.07:56:31.91#ibcon#read 4, iclass 12, count 0 2006.217.07:56:31.91#ibcon#about to read 5, iclass 12, count 0 2006.217.07:56:31.91#ibcon#read 5, iclass 12, count 0 2006.217.07:56:31.91#ibcon#about to read 6, iclass 12, count 0 2006.217.07:56:31.91#ibcon#read 6, iclass 12, count 0 2006.217.07:56:31.91#ibcon#end of sib2, iclass 12, count 0 2006.217.07:56:31.91#ibcon#*mode == 0, iclass 12, count 0 2006.217.07:56:31.91#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.217.07:56:31.91#ibcon#[27=USB\r\n] 2006.217.07:56:31.91#ibcon#*before write, iclass 12, count 0 2006.217.07:56:31.91#ibcon#enter sib2, iclass 12, count 0 2006.217.07:56:31.91#ibcon#flushed, iclass 12, count 0 2006.217.07:56:31.91#ibcon#about to write, iclass 12, count 0 2006.217.07:56:31.91#ibcon#wrote, iclass 12, count 0 2006.217.07:56:31.91#ibcon#about to read 3, iclass 12, count 0 2006.217.07:56:31.94#ibcon#read 3, iclass 12, count 0 2006.217.07:56:31.94#ibcon#about to read 4, iclass 12, count 0 2006.217.07:56:31.94#ibcon#read 4, iclass 12, count 0 2006.217.07:56:31.94#ibcon#about to read 5, iclass 12, count 0 2006.217.07:56:31.94#ibcon#read 5, iclass 12, count 0 2006.217.07:56:31.94#ibcon#about to read 6, iclass 12, count 0 2006.217.07:56:31.94#ibcon#read 6, iclass 12, count 0 2006.217.07:56:31.94#ibcon#end of sib2, iclass 12, count 0 2006.217.07:56:31.94#ibcon#*after write, iclass 12, count 0 2006.217.07:56:31.94#ibcon#*before return 0, iclass 12, count 0 2006.217.07:56:31.94#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.217.07:56:31.94#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.217.07:56:31.94#ibcon#about to clear, iclass 12 cls_cnt 0 2006.217.07:56:31.94#ibcon#cleared, iclass 12 cls_cnt 0 2006.217.07:56:31.94$vc4f8/vblo=5,744.99 2006.217.07:56:31.94#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.217.07:56:31.94#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.217.07:56:31.94#ibcon#ireg 17 cls_cnt 0 2006.217.07:56:31.94#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.217.07:56:31.94#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.217.07:56:31.94#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.217.07:56:31.94#ibcon#enter wrdev, iclass 14, count 0 2006.217.07:56:31.94#ibcon#first serial, iclass 14, count 0 2006.217.07:56:31.94#ibcon#enter sib2, iclass 14, count 0 2006.217.07:56:31.94#ibcon#flushed, iclass 14, count 0 2006.217.07:56:31.94#ibcon#about to write, iclass 14, count 0 2006.217.07:56:31.94#ibcon#wrote, iclass 14, count 0 2006.217.07:56:31.94#ibcon#about to read 3, iclass 14, count 0 2006.217.07:56:31.96#ibcon#read 3, iclass 14, count 0 2006.217.07:56:31.96#ibcon#about to read 4, iclass 14, count 0 2006.217.07:56:31.96#ibcon#read 4, iclass 14, count 0 2006.217.07:56:31.96#ibcon#about to read 5, iclass 14, count 0 2006.217.07:56:31.96#ibcon#read 5, iclass 14, count 0 2006.217.07:56:31.96#ibcon#about to read 6, iclass 14, count 0 2006.217.07:56:31.96#ibcon#read 6, iclass 14, count 0 2006.217.07:56:31.96#ibcon#end of sib2, iclass 14, count 0 2006.217.07:56:31.96#ibcon#*mode == 0, iclass 14, count 0 2006.217.07:56:31.96#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.217.07:56:31.96#ibcon#[28=FRQ=05,744.99\r\n] 2006.217.07:56:31.96#ibcon#*before write, iclass 14, count 0 2006.217.07:56:31.96#ibcon#enter sib2, iclass 14, count 0 2006.217.07:56:31.96#ibcon#flushed, iclass 14, count 0 2006.217.07:56:31.96#ibcon#about to write, iclass 14, count 0 2006.217.07:56:31.96#ibcon#wrote, iclass 14, count 0 2006.217.07:56:31.96#ibcon#about to read 3, iclass 14, count 0 2006.217.07:56:32.00#ibcon#read 3, iclass 14, count 0 2006.217.07:56:32.00#ibcon#about to read 4, iclass 14, count 0 2006.217.07:56:32.00#ibcon#read 4, iclass 14, count 0 2006.217.07:56:32.00#ibcon#about to read 5, iclass 14, count 0 2006.217.07:56:32.00#ibcon#read 5, iclass 14, count 0 2006.217.07:56:32.00#ibcon#about to read 6, iclass 14, count 0 2006.217.07:56:32.00#ibcon#read 6, iclass 14, count 0 2006.217.07:56:32.00#ibcon#end of sib2, iclass 14, count 0 2006.217.07:56:32.00#ibcon#*after write, iclass 14, count 0 2006.217.07:56:32.00#ibcon#*before return 0, iclass 14, count 0 2006.217.07:56:32.00#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.217.07:56:32.00#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.217.07:56:32.00#ibcon#about to clear, iclass 14 cls_cnt 0 2006.217.07:56:32.00#ibcon#cleared, iclass 14 cls_cnt 0 2006.217.07:56:32.00$vc4f8/vb=5,4 2006.217.07:56:32.00#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.217.07:56:32.00#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.217.07:56:32.00#ibcon#ireg 11 cls_cnt 2 2006.217.07:56:32.00#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.217.07:56:32.06#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.217.07:56:32.06#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.217.07:56:32.06#ibcon#enter wrdev, iclass 16, count 2 2006.217.07:56:32.06#ibcon#first serial, iclass 16, count 2 2006.217.07:56:32.06#ibcon#enter sib2, iclass 16, count 2 2006.217.07:56:32.06#ibcon#flushed, iclass 16, count 2 2006.217.07:56:32.06#ibcon#about to write, iclass 16, count 2 2006.217.07:56:32.06#ibcon#wrote, iclass 16, count 2 2006.217.07:56:32.06#ibcon#about to read 3, iclass 16, count 2 2006.217.07:56:32.08#ibcon#read 3, iclass 16, count 2 2006.217.07:56:32.08#ibcon#about to read 4, iclass 16, count 2 2006.217.07:56:32.08#ibcon#read 4, iclass 16, count 2 2006.217.07:56:32.08#ibcon#about to read 5, iclass 16, count 2 2006.217.07:56:32.08#ibcon#read 5, iclass 16, count 2 2006.217.07:56:32.08#ibcon#about to read 6, iclass 16, count 2 2006.217.07:56:32.08#ibcon#read 6, iclass 16, count 2 2006.217.07:56:32.08#ibcon#end of sib2, iclass 16, count 2 2006.217.07:56:32.08#ibcon#*mode == 0, iclass 16, count 2 2006.217.07:56:32.08#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.217.07:56:32.08#ibcon#[27=AT05-04\r\n] 2006.217.07:56:32.08#ibcon#*before write, iclass 16, count 2 2006.217.07:56:32.08#ibcon#enter sib2, iclass 16, count 2 2006.217.07:56:32.08#ibcon#flushed, iclass 16, count 2 2006.217.07:56:32.08#ibcon#about to write, iclass 16, count 2 2006.217.07:56:32.08#ibcon#wrote, iclass 16, count 2 2006.217.07:56:32.08#ibcon#about to read 3, iclass 16, count 2 2006.217.07:56:32.11#ibcon#read 3, iclass 16, count 2 2006.217.07:56:32.11#ibcon#about to read 4, iclass 16, count 2 2006.217.07:56:32.11#ibcon#read 4, iclass 16, count 2 2006.217.07:56:32.11#ibcon#about to read 5, iclass 16, count 2 2006.217.07:56:32.11#ibcon#read 5, iclass 16, count 2 2006.217.07:56:32.11#ibcon#about to read 6, iclass 16, count 2 2006.217.07:56:32.11#ibcon#read 6, iclass 16, count 2 2006.217.07:56:32.11#ibcon#end of sib2, iclass 16, count 2 2006.217.07:56:32.11#ibcon#*after write, iclass 16, count 2 2006.217.07:56:32.11#ibcon#*before return 0, iclass 16, count 2 2006.217.07:56:32.11#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.217.07:56:32.11#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.217.07:56:32.11#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.217.07:56:32.11#ibcon#ireg 7 cls_cnt 0 2006.217.07:56:32.11#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.217.07:56:32.23#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.217.07:56:32.23#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.217.07:56:32.23#ibcon#enter wrdev, iclass 16, count 0 2006.217.07:56:32.23#ibcon#first serial, iclass 16, count 0 2006.217.07:56:32.23#ibcon#enter sib2, iclass 16, count 0 2006.217.07:56:32.23#ibcon#flushed, iclass 16, count 0 2006.217.07:56:32.23#ibcon#about to write, iclass 16, count 0 2006.217.07:56:32.23#ibcon#wrote, iclass 16, count 0 2006.217.07:56:32.23#ibcon#about to read 3, iclass 16, count 0 2006.217.07:56:32.25#ibcon#read 3, iclass 16, count 0 2006.217.07:56:32.25#ibcon#about to read 4, iclass 16, count 0 2006.217.07:56:32.25#ibcon#read 4, iclass 16, count 0 2006.217.07:56:32.25#ibcon#about to read 5, iclass 16, count 0 2006.217.07:56:32.25#ibcon#read 5, iclass 16, count 0 2006.217.07:56:32.25#ibcon#about to read 6, iclass 16, count 0 2006.217.07:56:32.25#ibcon#read 6, iclass 16, count 0 2006.217.07:56:32.25#ibcon#end of sib2, iclass 16, count 0 2006.217.07:56:32.25#ibcon#*mode == 0, iclass 16, count 0 2006.217.07:56:32.25#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.217.07:56:32.25#ibcon#[27=USB\r\n] 2006.217.07:56:32.25#ibcon#*before write, iclass 16, count 0 2006.217.07:56:32.25#ibcon#enter sib2, iclass 16, count 0 2006.217.07:56:32.25#ibcon#flushed, iclass 16, count 0 2006.217.07:56:32.25#ibcon#about to write, iclass 16, count 0 2006.217.07:56:32.25#ibcon#wrote, iclass 16, count 0 2006.217.07:56:32.25#ibcon#about to read 3, iclass 16, count 0 2006.217.07:56:32.28#ibcon#read 3, iclass 16, count 0 2006.217.07:56:32.28#ibcon#about to read 4, iclass 16, count 0 2006.217.07:56:32.28#ibcon#read 4, iclass 16, count 0 2006.217.07:56:32.28#ibcon#about to read 5, iclass 16, count 0 2006.217.07:56:32.28#ibcon#read 5, iclass 16, count 0 2006.217.07:56:32.28#ibcon#about to read 6, iclass 16, count 0 2006.217.07:56:32.28#ibcon#read 6, iclass 16, count 0 2006.217.07:56:32.28#ibcon#end of sib2, iclass 16, count 0 2006.217.07:56:32.28#ibcon#*after write, iclass 16, count 0 2006.217.07:56:32.28#ibcon#*before return 0, iclass 16, count 0 2006.217.07:56:32.28#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.217.07:56:32.28#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.217.07:56:32.28#ibcon#about to clear, iclass 16 cls_cnt 0 2006.217.07:56:32.28#ibcon#cleared, iclass 16 cls_cnt 0 2006.217.07:56:32.28$vc4f8/vblo=6,752.99 2006.217.07:56:32.28#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.217.07:56:32.28#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.217.07:56:32.28#ibcon#ireg 17 cls_cnt 0 2006.217.07:56:32.28#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.217.07:56:32.28#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.217.07:56:32.28#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.217.07:56:32.28#ibcon#enter wrdev, iclass 18, count 0 2006.217.07:56:32.28#ibcon#first serial, iclass 18, count 0 2006.217.07:56:32.28#ibcon#enter sib2, iclass 18, count 0 2006.217.07:56:32.28#ibcon#flushed, iclass 18, count 0 2006.217.07:56:32.28#ibcon#about to write, iclass 18, count 0 2006.217.07:56:32.28#ibcon#wrote, iclass 18, count 0 2006.217.07:56:32.28#ibcon#about to read 3, iclass 18, count 0 2006.217.07:56:32.30#ibcon#read 3, iclass 18, count 0 2006.217.07:56:32.30#ibcon#about to read 4, iclass 18, count 0 2006.217.07:56:32.30#ibcon#read 4, iclass 18, count 0 2006.217.07:56:32.30#ibcon#about to read 5, iclass 18, count 0 2006.217.07:56:32.30#ibcon#read 5, iclass 18, count 0 2006.217.07:56:32.30#ibcon#about to read 6, iclass 18, count 0 2006.217.07:56:32.30#ibcon#read 6, iclass 18, count 0 2006.217.07:56:32.30#ibcon#end of sib2, iclass 18, count 0 2006.217.07:56:32.30#ibcon#*mode == 0, iclass 18, count 0 2006.217.07:56:32.30#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.217.07:56:32.30#ibcon#[28=FRQ=06,752.99\r\n] 2006.217.07:56:32.30#ibcon#*before write, iclass 18, count 0 2006.217.07:56:32.30#ibcon#enter sib2, iclass 18, count 0 2006.217.07:56:32.30#ibcon#flushed, iclass 18, count 0 2006.217.07:56:32.30#ibcon#about to write, iclass 18, count 0 2006.217.07:56:32.30#ibcon#wrote, iclass 18, count 0 2006.217.07:56:32.30#ibcon#about to read 3, iclass 18, count 0 2006.217.07:56:32.34#ibcon#read 3, iclass 18, count 0 2006.217.07:56:32.34#ibcon#about to read 4, iclass 18, count 0 2006.217.07:56:32.34#ibcon#read 4, iclass 18, count 0 2006.217.07:56:32.34#ibcon#about to read 5, iclass 18, count 0 2006.217.07:56:32.34#ibcon#read 5, iclass 18, count 0 2006.217.07:56:32.34#ibcon#about to read 6, iclass 18, count 0 2006.217.07:56:32.34#ibcon#read 6, iclass 18, count 0 2006.217.07:56:32.34#ibcon#end of sib2, iclass 18, count 0 2006.217.07:56:32.34#ibcon#*after write, iclass 18, count 0 2006.217.07:56:32.34#ibcon#*before return 0, iclass 18, count 0 2006.217.07:56:32.34#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.217.07:56:32.34#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.217.07:56:32.34#ibcon#about to clear, iclass 18 cls_cnt 0 2006.217.07:56:32.34#ibcon#cleared, iclass 18 cls_cnt 0 2006.217.07:56:32.34$vc4f8/vb=6,4 2006.217.07:56:32.34#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.217.07:56:32.34#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.217.07:56:32.34#ibcon#ireg 11 cls_cnt 2 2006.217.07:56:32.34#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.217.07:56:32.40#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.217.07:56:32.40#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.217.07:56:32.40#ibcon#enter wrdev, iclass 20, count 2 2006.217.07:56:32.40#ibcon#first serial, iclass 20, count 2 2006.217.07:56:32.40#ibcon#enter sib2, iclass 20, count 2 2006.217.07:56:32.40#ibcon#flushed, iclass 20, count 2 2006.217.07:56:32.40#ibcon#about to write, iclass 20, count 2 2006.217.07:56:32.40#ibcon#wrote, iclass 20, count 2 2006.217.07:56:32.40#ibcon#about to read 3, iclass 20, count 2 2006.217.07:56:32.42#ibcon#read 3, iclass 20, count 2 2006.217.07:56:32.42#ibcon#about to read 4, iclass 20, count 2 2006.217.07:56:32.42#ibcon#read 4, iclass 20, count 2 2006.217.07:56:32.42#ibcon#about to read 5, iclass 20, count 2 2006.217.07:56:32.42#ibcon#read 5, iclass 20, count 2 2006.217.07:56:32.42#ibcon#about to read 6, iclass 20, count 2 2006.217.07:56:32.42#ibcon#read 6, iclass 20, count 2 2006.217.07:56:32.42#ibcon#end of sib2, iclass 20, count 2 2006.217.07:56:32.42#ibcon#*mode == 0, iclass 20, count 2 2006.217.07:56:32.42#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.217.07:56:32.42#ibcon#[27=AT06-04\r\n] 2006.217.07:56:32.42#ibcon#*before write, iclass 20, count 2 2006.217.07:56:32.42#ibcon#enter sib2, iclass 20, count 2 2006.217.07:56:32.42#ibcon#flushed, iclass 20, count 2 2006.217.07:56:32.42#ibcon#about to write, iclass 20, count 2 2006.217.07:56:32.42#ibcon#wrote, iclass 20, count 2 2006.217.07:56:32.42#ibcon#about to read 3, iclass 20, count 2 2006.217.07:56:32.45#ibcon#read 3, iclass 20, count 2 2006.217.07:56:32.45#ibcon#about to read 4, iclass 20, count 2 2006.217.07:56:32.45#ibcon#read 4, iclass 20, count 2 2006.217.07:56:32.45#ibcon#about to read 5, iclass 20, count 2 2006.217.07:56:32.45#ibcon#read 5, iclass 20, count 2 2006.217.07:56:32.45#ibcon#about to read 6, iclass 20, count 2 2006.217.07:56:32.45#ibcon#read 6, iclass 20, count 2 2006.217.07:56:32.45#ibcon#end of sib2, iclass 20, count 2 2006.217.07:56:32.45#ibcon#*after write, iclass 20, count 2 2006.217.07:56:32.45#ibcon#*before return 0, iclass 20, count 2 2006.217.07:56:32.45#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.217.07:56:32.45#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.217.07:56:32.45#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.217.07:56:32.45#ibcon#ireg 7 cls_cnt 0 2006.217.07:56:32.45#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.217.07:56:32.57#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.217.07:56:32.57#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.217.07:56:32.57#ibcon#enter wrdev, iclass 20, count 0 2006.217.07:56:32.57#ibcon#first serial, iclass 20, count 0 2006.217.07:56:32.57#ibcon#enter sib2, iclass 20, count 0 2006.217.07:56:32.57#ibcon#flushed, iclass 20, count 0 2006.217.07:56:32.57#ibcon#about to write, iclass 20, count 0 2006.217.07:56:32.57#ibcon#wrote, iclass 20, count 0 2006.217.07:56:32.57#ibcon#about to read 3, iclass 20, count 0 2006.217.07:56:32.59#ibcon#read 3, iclass 20, count 0 2006.217.07:56:32.59#ibcon#about to read 4, iclass 20, count 0 2006.217.07:56:32.59#ibcon#read 4, iclass 20, count 0 2006.217.07:56:32.59#ibcon#about to read 5, iclass 20, count 0 2006.217.07:56:32.59#ibcon#read 5, iclass 20, count 0 2006.217.07:56:32.59#ibcon#about to read 6, iclass 20, count 0 2006.217.07:56:32.59#ibcon#read 6, iclass 20, count 0 2006.217.07:56:32.59#ibcon#end of sib2, iclass 20, count 0 2006.217.07:56:32.59#ibcon#*mode == 0, iclass 20, count 0 2006.217.07:56:32.59#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.217.07:56:32.59#ibcon#[27=USB\r\n] 2006.217.07:56:32.59#ibcon#*before write, iclass 20, count 0 2006.217.07:56:32.59#ibcon#enter sib2, iclass 20, count 0 2006.217.07:56:32.59#ibcon#flushed, iclass 20, count 0 2006.217.07:56:32.59#ibcon#about to write, iclass 20, count 0 2006.217.07:56:32.59#ibcon#wrote, iclass 20, count 0 2006.217.07:56:32.59#ibcon#about to read 3, iclass 20, count 0 2006.217.07:56:32.62#ibcon#read 3, iclass 20, count 0 2006.217.07:56:32.62#ibcon#about to read 4, iclass 20, count 0 2006.217.07:56:32.62#ibcon#read 4, iclass 20, count 0 2006.217.07:56:32.62#ibcon#about to read 5, iclass 20, count 0 2006.217.07:56:32.62#ibcon#read 5, iclass 20, count 0 2006.217.07:56:32.62#ibcon#about to read 6, iclass 20, count 0 2006.217.07:56:32.62#ibcon#read 6, iclass 20, count 0 2006.217.07:56:32.62#ibcon#end of sib2, iclass 20, count 0 2006.217.07:56:32.62#ibcon#*after write, iclass 20, count 0 2006.217.07:56:32.62#ibcon#*before return 0, iclass 20, count 0 2006.217.07:56:32.62#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.217.07:56:32.62#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.217.07:56:32.62#ibcon#about to clear, iclass 20 cls_cnt 0 2006.217.07:56:32.62#ibcon#cleared, iclass 20 cls_cnt 0 2006.217.07:56:32.62$vc4f8/vabw=wide 2006.217.07:56:32.62#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.217.07:56:32.62#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.217.07:56:32.62#ibcon#ireg 8 cls_cnt 0 2006.217.07:56:32.62#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.217.07:56:32.62#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.217.07:56:32.62#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.217.07:56:32.62#ibcon#enter wrdev, iclass 22, count 0 2006.217.07:56:32.62#ibcon#first serial, iclass 22, count 0 2006.217.07:56:32.62#ibcon#enter sib2, iclass 22, count 0 2006.217.07:56:32.62#ibcon#flushed, iclass 22, count 0 2006.217.07:56:32.62#ibcon#about to write, iclass 22, count 0 2006.217.07:56:32.62#ibcon#wrote, iclass 22, count 0 2006.217.07:56:32.62#ibcon#about to read 3, iclass 22, count 0 2006.217.07:56:32.64#ibcon#read 3, iclass 22, count 0 2006.217.07:56:32.64#ibcon#about to read 4, iclass 22, count 0 2006.217.07:56:32.64#ibcon#read 4, iclass 22, count 0 2006.217.07:56:32.64#ibcon#about to read 5, iclass 22, count 0 2006.217.07:56:32.64#ibcon#read 5, iclass 22, count 0 2006.217.07:56:32.64#ibcon#about to read 6, iclass 22, count 0 2006.217.07:56:32.64#ibcon#read 6, iclass 22, count 0 2006.217.07:56:32.64#ibcon#end of sib2, iclass 22, count 0 2006.217.07:56:32.64#ibcon#*mode == 0, iclass 22, count 0 2006.217.07:56:32.64#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.217.07:56:32.64#ibcon#[25=BW32\r\n] 2006.217.07:56:32.64#ibcon#*before write, iclass 22, count 0 2006.217.07:56:32.64#ibcon#enter sib2, iclass 22, count 0 2006.217.07:56:32.64#ibcon#flushed, iclass 22, count 0 2006.217.07:56:32.64#ibcon#about to write, iclass 22, count 0 2006.217.07:56:32.64#ibcon#wrote, iclass 22, count 0 2006.217.07:56:32.64#ibcon#about to read 3, iclass 22, count 0 2006.217.07:56:32.67#ibcon#read 3, iclass 22, count 0 2006.217.07:56:32.67#ibcon#about to read 4, iclass 22, count 0 2006.217.07:56:32.67#ibcon#read 4, iclass 22, count 0 2006.217.07:56:32.67#ibcon#about to read 5, iclass 22, count 0 2006.217.07:56:32.67#ibcon#read 5, iclass 22, count 0 2006.217.07:56:32.67#ibcon#about to read 6, iclass 22, count 0 2006.217.07:56:32.67#ibcon#read 6, iclass 22, count 0 2006.217.07:56:32.67#ibcon#end of sib2, iclass 22, count 0 2006.217.07:56:32.67#ibcon#*after write, iclass 22, count 0 2006.217.07:56:32.67#ibcon#*before return 0, iclass 22, count 0 2006.217.07:56:32.67#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.217.07:56:32.67#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.217.07:56:32.67#ibcon#about to clear, iclass 22 cls_cnt 0 2006.217.07:56:32.67#ibcon#cleared, iclass 22 cls_cnt 0 2006.217.07:56:32.67$vc4f8/vbbw=wide 2006.217.07:56:32.67#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.217.07:56:32.67#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.217.07:56:32.67#ibcon#ireg 8 cls_cnt 0 2006.217.07:56:32.67#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.217.07:56:32.75#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.217.07:56:32.75#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.217.07:56:32.75#ibcon#enter wrdev, iclass 24, count 0 2006.217.07:56:32.75#ibcon#first serial, iclass 24, count 0 2006.217.07:56:32.75#ibcon#enter sib2, iclass 24, count 0 2006.217.07:56:32.75#ibcon#flushed, iclass 24, count 0 2006.217.07:56:32.75#ibcon#about to write, iclass 24, count 0 2006.217.07:56:32.75#ibcon#wrote, iclass 24, count 0 2006.217.07:56:32.75#ibcon#about to read 3, iclass 24, count 0 2006.217.07:56:32.76#ibcon#read 3, iclass 24, count 0 2006.217.07:56:32.76#ibcon#about to read 4, iclass 24, count 0 2006.217.07:56:32.76#ibcon#read 4, iclass 24, count 0 2006.217.07:56:32.76#ibcon#about to read 5, iclass 24, count 0 2006.217.07:56:32.76#ibcon#read 5, iclass 24, count 0 2006.217.07:56:32.76#ibcon#about to read 6, iclass 24, count 0 2006.217.07:56:32.76#ibcon#read 6, iclass 24, count 0 2006.217.07:56:32.76#ibcon#end of sib2, iclass 24, count 0 2006.217.07:56:32.76#ibcon#*mode == 0, iclass 24, count 0 2006.217.07:56:32.76#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.217.07:56:32.76#ibcon#[27=BW32\r\n] 2006.217.07:56:32.76#ibcon#*before write, iclass 24, count 0 2006.217.07:56:32.76#ibcon#enter sib2, iclass 24, count 0 2006.217.07:56:32.76#ibcon#flushed, iclass 24, count 0 2006.217.07:56:32.76#ibcon#about to write, iclass 24, count 0 2006.217.07:56:32.76#ibcon#wrote, iclass 24, count 0 2006.217.07:56:32.76#ibcon#about to read 3, iclass 24, count 0 2006.217.07:56:32.79#ibcon#read 3, iclass 24, count 0 2006.217.07:56:32.79#ibcon#about to read 4, iclass 24, count 0 2006.217.07:56:32.79#ibcon#read 4, iclass 24, count 0 2006.217.07:56:32.79#ibcon#about to read 5, iclass 24, count 0 2006.217.07:56:32.79#ibcon#read 5, iclass 24, count 0 2006.217.07:56:32.79#ibcon#about to read 6, iclass 24, count 0 2006.217.07:56:32.79#ibcon#read 6, iclass 24, count 0 2006.217.07:56:32.79#ibcon#end of sib2, iclass 24, count 0 2006.217.07:56:32.79#ibcon#*after write, iclass 24, count 0 2006.217.07:56:32.79#ibcon#*before return 0, iclass 24, count 0 2006.217.07:56:32.79#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.217.07:56:32.79#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.217.07:56:32.79#ibcon#about to clear, iclass 24 cls_cnt 0 2006.217.07:56:32.79#ibcon#cleared, iclass 24 cls_cnt 0 2006.217.07:56:32.79$4f8m12a/ifd4f 2006.217.07:56:32.79$ifd4f/lo= 2006.217.07:56:32.79$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.217.07:56:32.79$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.217.07:56:32.79$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.217.07:56:32.79$ifd4f/patch= 2006.217.07:56:32.79$ifd4f/patch=lo1,a1,a2,a3,a4 2006.217.07:56:32.79$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.217.07:56:32.79$ifd4f/patch=lo3,a5,a6,a7,a8 2006.217.07:56:32.79$4f8m12a/"form=m,16.000,1:2 2006.217.07:56:32.79$4f8m12a/"tpicd 2006.217.07:56:32.79$4f8m12a/echo=off 2006.217.07:56:32.79$4f8m12a/xlog=off 2006.217.07:56:32.79:!2006.217.07:58:40 2006.217.07:56:51.14#trakl#Source acquired 2006.217.07:56:51.14#flagr#flagr/antenna,acquired 2006.217.07:58:40.00:preob 2006.217.07:58:40.13/onsource/TRACKING 2006.217.07:58:40.13:!2006.217.07:58:50 2006.217.07:58:50.00:data_valid=on 2006.217.07:58:50.00:midob 2006.217.07:58:51.13/onsource/TRACKING 2006.217.07:58:51.13/wx/31.01,1008.6,64 2006.217.07:58:51.30/cable/+6.3850E-03 2006.217.07:58:52.39/va/01,05,usb,yes,31,33 2006.217.07:58:52.39/va/02,04,usb,yes,29,30 2006.217.07:58:52.39/va/03,04,usb,yes,27,27 2006.217.07:58:52.39/va/04,04,usb,yes,30,33 2006.217.07:58:52.39/va/05,07,usb,yes,33,34 2006.217.07:58:52.39/va/06,06,usb,yes,32,31 2006.217.07:58:52.39/va/07,06,usb,yes,32,32 2006.217.07:58:52.39/va/08,07,usb,yes,30,30 2006.217.07:58:52.62/valo/01,532.99,yes,locked 2006.217.07:58:52.62/valo/02,572.99,yes,locked 2006.217.07:58:52.62/valo/03,672.99,yes,locked 2006.217.07:58:52.62/valo/04,832.99,yes,locked 2006.217.07:58:52.62/valo/05,652.99,yes,locked 2006.217.07:58:52.62/valo/06,772.99,yes,locked 2006.217.07:58:52.62/valo/07,832.99,yes,locked 2006.217.07:58:52.62/valo/08,852.99,yes,locked 2006.217.07:58:53.71/vb/01,04,usb,yes,30,29 2006.217.07:58:53.71/vb/02,04,usb,yes,32,33 2006.217.07:58:53.71/vb/03,04,usb,yes,28,32 2006.217.07:58:53.71/vb/04,04,usb,yes,29,29 2006.217.07:58:53.71/vb/05,04,usb,yes,28,32 2006.217.07:58:53.71/vb/06,04,usb,yes,28,31 2006.217.07:58:53.71/vb/07,04,usb,yes,31,31 2006.217.07:58:53.71/vb/08,04,usb,yes,28,32 2006.217.07:58:53.95/vblo/01,632.99,yes,locked 2006.217.07:58:53.95/vblo/02,640.99,yes,locked 2006.217.07:58:53.95/vblo/03,656.99,yes,locked 2006.217.07:58:53.95/vblo/04,712.99,yes,locked 2006.217.07:58:53.95/vblo/05,744.99,yes,locked 2006.217.07:58:53.95/vblo/06,752.99,yes,locked 2006.217.07:58:53.95/vblo/07,734.99,yes,locked 2006.217.07:58:53.95/vblo/08,744.99,yes,locked 2006.217.07:58:54.10/vabw/8 2006.217.07:58:54.25/vbbw/8 2006.217.07:58:54.34/xfe/off,on,14.7 2006.217.07:58:54.73/ifatt/23,28,28,28 2006.217.07:58:55.07/fmout-gps/S +4.30E-07 2006.217.07:58:55.15:!2006.217.07:59:50 2006.217.07:59:50.01:data_valid=off 2006.217.07:59:50.01:postob 2006.217.07:59:50.18/cable/+6.3842E-03 2006.217.07:59:50.18/wx/30.99,1008.6,64 2006.217.07:59:51.08/fmout-gps/S +4.31E-07 2006.217.07:59:51.08:scan_name=217-0800,k06217,60 2006.217.07:59:51.09:source=1357+769,135755.37,764321.1,2000.0,neutral 2006.217.07:59:51.16#flagr#flagr/antenna,new-source 2006.217.07:59:52.12:checkk5 2006.217.07:59:52.50/chk_autoobs//k5ts1/ autoobs is running! 2006.217.07:59:52.87/chk_autoobs//k5ts2/ autoobs is running! 2006.217.07:59:53.25/chk_autoobs//k5ts3/ autoobs is running! 2006.217.07:59:53.63/chk_autoobs//k5ts4/ autoobs is running! 2006.217.07:59:54.00/chk_obsdata//k5ts1/T2170758??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:59:54.36/chk_obsdata//k5ts2/T2170758??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:59:54.73/chk_obsdata//k5ts3/T2170758??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:59:55.10/chk_obsdata//k5ts4/T2170758??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.07:59:55.79/k5log//k5ts1_log_newline 2006.217.07:59:56.49/k5log//k5ts2_log_newline 2006.217.07:59:57.18/k5log//k5ts3_log_newline 2006.217.07:59:57.86/k5log//k5ts4_log_newline 2006.217.07:59:57.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.217.07:59:57.89:4f8m12a=2 2006.217.07:59:57.89$4f8m12a/echo=on 2006.217.07:59:57.89$4f8m12a/pcalon 2006.217.07:59:57.89$pcalon/"no phase cal control is implemented here 2006.217.07:59:57.89$4f8m12a/"tpicd=stop 2006.217.07:59:57.89$4f8m12a/vc4f8 2006.217.07:59:57.89$vc4f8/valo=1,532.99 2006.217.07:59:57.89#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.217.07:59:57.89#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.217.07:59:57.89#ibcon#ireg 17 cls_cnt 0 2006.217.07:59:57.89#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.217.07:59:57.89#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.217.07:59:57.89#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.217.07:59:57.89#ibcon#enter wrdev, iclass 35, count 0 2006.217.07:59:57.89#ibcon#first serial, iclass 35, count 0 2006.217.07:59:57.89#ibcon#enter sib2, iclass 35, count 0 2006.217.07:59:57.89#ibcon#flushed, iclass 35, count 0 2006.217.07:59:57.89#ibcon#about to write, iclass 35, count 0 2006.217.07:59:57.89#ibcon#wrote, iclass 35, count 0 2006.217.07:59:57.89#ibcon#about to read 3, iclass 35, count 0 2006.217.07:59:57.93#ibcon#read 3, iclass 35, count 0 2006.217.07:59:57.93#ibcon#about to read 4, iclass 35, count 0 2006.217.07:59:57.93#ibcon#read 4, iclass 35, count 0 2006.217.07:59:57.93#ibcon#about to read 5, iclass 35, count 0 2006.217.07:59:57.93#ibcon#read 5, iclass 35, count 0 2006.217.07:59:57.93#ibcon#about to read 6, iclass 35, count 0 2006.217.07:59:57.93#ibcon#read 6, iclass 35, count 0 2006.217.07:59:57.93#ibcon#end of sib2, iclass 35, count 0 2006.217.07:59:57.93#ibcon#*mode == 0, iclass 35, count 0 2006.217.07:59:57.93#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.217.07:59:57.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.217.07:59:57.93#ibcon#*before write, iclass 35, count 0 2006.217.07:59:57.93#ibcon#enter sib2, iclass 35, count 0 2006.217.07:59:57.93#ibcon#flushed, iclass 35, count 0 2006.217.07:59:57.93#ibcon#about to write, iclass 35, count 0 2006.217.07:59:57.93#ibcon#wrote, iclass 35, count 0 2006.217.07:59:57.93#ibcon#about to read 3, iclass 35, count 0 2006.217.07:59:57.98#ibcon#read 3, iclass 35, count 0 2006.217.07:59:57.98#ibcon#about to read 4, iclass 35, count 0 2006.217.07:59:57.98#ibcon#read 4, iclass 35, count 0 2006.217.07:59:57.98#ibcon#about to read 5, iclass 35, count 0 2006.217.07:59:57.98#ibcon#read 5, iclass 35, count 0 2006.217.07:59:57.98#ibcon#about to read 6, iclass 35, count 0 2006.217.07:59:57.98#ibcon#read 6, iclass 35, count 0 2006.217.07:59:57.98#ibcon#end of sib2, iclass 35, count 0 2006.217.07:59:57.98#ibcon#*after write, iclass 35, count 0 2006.217.07:59:57.98#ibcon#*before return 0, iclass 35, count 0 2006.217.07:59:57.98#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.217.07:59:57.98#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.217.07:59:57.98#ibcon#about to clear, iclass 35 cls_cnt 0 2006.217.07:59:57.98#ibcon#cleared, iclass 35 cls_cnt 0 2006.217.07:59:57.98$vc4f8/va=1,5 2006.217.07:59:57.98#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.217.07:59:57.98#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.217.07:59:57.98#ibcon#ireg 11 cls_cnt 2 2006.217.07:59:57.98#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.217.07:59:57.98#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.217.07:59:57.98#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.217.07:59:57.98#ibcon#enter wrdev, iclass 37, count 2 2006.217.07:59:57.98#ibcon#first serial, iclass 37, count 2 2006.217.07:59:57.98#ibcon#enter sib2, iclass 37, count 2 2006.217.07:59:57.98#ibcon#flushed, iclass 37, count 2 2006.217.07:59:57.98#ibcon#about to write, iclass 37, count 2 2006.217.07:59:57.98#ibcon#wrote, iclass 37, count 2 2006.217.07:59:57.98#ibcon#about to read 3, iclass 37, count 2 2006.217.07:59:58.00#ibcon#read 3, iclass 37, count 2 2006.217.07:59:58.00#ibcon#about to read 4, iclass 37, count 2 2006.217.07:59:58.00#ibcon#read 4, iclass 37, count 2 2006.217.07:59:58.00#ibcon#about to read 5, iclass 37, count 2 2006.217.07:59:58.00#ibcon#read 5, iclass 37, count 2 2006.217.07:59:58.00#ibcon#about to read 6, iclass 37, count 2 2006.217.07:59:58.00#ibcon#read 6, iclass 37, count 2 2006.217.07:59:58.00#ibcon#end of sib2, iclass 37, count 2 2006.217.07:59:58.00#ibcon#*mode == 0, iclass 37, count 2 2006.217.07:59:58.00#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.217.07:59:58.00#ibcon#[25=AT01-05\r\n] 2006.217.07:59:58.00#ibcon#*before write, iclass 37, count 2 2006.217.07:59:58.00#ibcon#enter sib2, iclass 37, count 2 2006.217.07:59:58.00#ibcon#flushed, iclass 37, count 2 2006.217.07:59:58.00#ibcon#about to write, iclass 37, count 2 2006.217.07:59:58.00#ibcon#wrote, iclass 37, count 2 2006.217.07:59:58.00#ibcon#about to read 3, iclass 37, count 2 2006.217.07:59:58.03#ibcon#read 3, iclass 37, count 2 2006.217.07:59:58.03#ibcon#about to read 4, iclass 37, count 2 2006.217.07:59:58.03#ibcon#read 4, iclass 37, count 2 2006.217.07:59:58.03#ibcon#about to read 5, iclass 37, count 2 2006.217.07:59:58.03#ibcon#read 5, iclass 37, count 2 2006.217.07:59:58.03#ibcon#about to read 6, iclass 37, count 2 2006.217.07:59:58.03#ibcon#read 6, iclass 37, count 2 2006.217.07:59:58.03#ibcon#end of sib2, iclass 37, count 2 2006.217.07:59:58.03#ibcon#*after write, iclass 37, count 2 2006.217.07:59:58.03#ibcon#*before return 0, iclass 37, count 2 2006.217.07:59:58.03#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.217.07:59:58.03#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.217.07:59:58.03#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.217.07:59:58.03#ibcon#ireg 7 cls_cnt 0 2006.217.07:59:58.03#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.217.07:59:58.15#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.217.07:59:58.15#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.217.07:59:58.15#ibcon#enter wrdev, iclass 37, count 0 2006.217.07:59:58.15#ibcon#first serial, iclass 37, count 0 2006.217.07:59:58.15#ibcon#enter sib2, iclass 37, count 0 2006.217.07:59:58.15#ibcon#flushed, iclass 37, count 0 2006.217.07:59:58.15#ibcon#about to write, iclass 37, count 0 2006.217.07:59:58.15#ibcon#wrote, iclass 37, count 0 2006.217.07:59:58.15#ibcon#about to read 3, iclass 37, count 0 2006.217.07:59:58.17#ibcon#read 3, iclass 37, count 0 2006.217.07:59:58.17#ibcon#about to read 4, iclass 37, count 0 2006.217.07:59:58.17#ibcon#read 4, iclass 37, count 0 2006.217.07:59:58.17#ibcon#about to read 5, iclass 37, count 0 2006.217.07:59:58.17#ibcon#read 5, iclass 37, count 0 2006.217.07:59:58.17#ibcon#about to read 6, iclass 37, count 0 2006.217.07:59:58.17#ibcon#read 6, iclass 37, count 0 2006.217.07:59:58.17#ibcon#end of sib2, iclass 37, count 0 2006.217.07:59:58.17#ibcon#*mode == 0, iclass 37, count 0 2006.217.07:59:58.17#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.217.07:59:58.17#ibcon#[25=USB\r\n] 2006.217.07:59:58.17#ibcon#*before write, iclass 37, count 0 2006.217.07:59:58.17#ibcon#enter sib2, iclass 37, count 0 2006.217.07:59:58.17#ibcon#flushed, iclass 37, count 0 2006.217.07:59:58.17#ibcon#about to write, iclass 37, count 0 2006.217.07:59:58.17#ibcon#wrote, iclass 37, count 0 2006.217.07:59:58.17#ibcon#about to read 3, iclass 37, count 0 2006.217.07:59:58.20#ibcon#read 3, iclass 37, count 0 2006.217.07:59:58.20#ibcon#about to read 4, iclass 37, count 0 2006.217.07:59:58.20#ibcon#read 4, iclass 37, count 0 2006.217.07:59:58.20#ibcon#about to read 5, iclass 37, count 0 2006.217.07:59:58.20#ibcon#read 5, iclass 37, count 0 2006.217.07:59:58.20#ibcon#about to read 6, iclass 37, count 0 2006.217.07:59:58.20#ibcon#read 6, iclass 37, count 0 2006.217.07:59:58.20#ibcon#end of sib2, iclass 37, count 0 2006.217.07:59:58.20#ibcon#*after write, iclass 37, count 0 2006.217.07:59:58.20#ibcon#*before return 0, iclass 37, count 0 2006.217.07:59:58.20#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.217.07:59:58.20#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.217.07:59:58.20#ibcon#about to clear, iclass 37 cls_cnt 0 2006.217.07:59:58.20#ibcon#cleared, iclass 37 cls_cnt 0 2006.217.07:59:58.20$vc4f8/valo=2,572.99 2006.217.07:59:58.20#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.217.07:59:58.20#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.217.07:59:58.20#ibcon#ireg 17 cls_cnt 0 2006.217.07:59:58.20#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.217.07:59:58.20#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.217.07:59:58.20#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.217.07:59:58.20#ibcon#enter wrdev, iclass 39, count 0 2006.217.07:59:58.20#ibcon#first serial, iclass 39, count 0 2006.217.07:59:58.20#ibcon#enter sib2, iclass 39, count 0 2006.217.07:59:58.20#ibcon#flushed, iclass 39, count 0 2006.217.07:59:58.20#ibcon#about to write, iclass 39, count 0 2006.217.07:59:58.20#ibcon#wrote, iclass 39, count 0 2006.217.07:59:58.20#ibcon#about to read 3, iclass 39, count 0 2006.217.07:59:58.22#ibcon#read 3, iclass 39, count 0 2006.217.07:59:58.22#ibcon#about to read 4, iclass 39, count 0 2006.217.07:59:58.22#ibcon#read 4, iclass 39, count 0 2006.217.07:59:58.22#ibcon#about to read 5, iclass 39, count 0 2006.217.07:59:58.22#ibcon#read 5, iclass 39, count 0 2006.217.07:59:58.22#ibcon#about to read 6, iclass 39, count 0 2006.217.07:59:58.22#ibcon#read 6, iclass 39, count 0 2006.217.07:59:58.22#ibcon#end of sib2, iclass 39, count 0 2006.217.07:59:58.22#ibcon#*mode == 0, iclass 39, count 0 2006.217.07:59:58.22#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.217.07:59:58.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.217.07:59:58.22#ibcon#*before write, iclass 39, count 0 2006.217.07:59:58.22#ibcon#enter sib2, iclass 39, count 0 2006.217.07:59:58.22#ibcon#flushed, iclass 39, count 0 2006.217.07:59:58.22#ibcon#about to write, iclass 39, count 0 2006.217.07:59:58.22#ibcon#wrote, iclass 39, count 0 2006.217.07:59:58.22#ibcon#about to read 3, iclass 39, count 0 2006.217.07:59:58.26#ibcon#read 3, iclass 39, count 0 2006.217.07:59:58.26#ibcon#about to read 4, iclass 39, count 0 2006.217.07:59:58.26#ibcon#read 4, iclass 39, count 0 2006.217.07:59:58.26#ibcon#about to read 5, iclass 39, count 0 2006.217.07:59:58.26#ibcon#read 5, iclass 39, count 0 2006.217.07:59:58.26#ibcon#about to read 6, iclass 39, count 0 2006.217.07:59:58.26#ibcon#read 6, iclass 39, count 0 2006.217.07:59:58.26#ibcon#end of sib2, iclass 39, count 0 2006.217.07:59:58.26#ibcon#*after write, iclass 39, count 0 2006.217.07:59:58.26#ibcon#*before return 0, iclass 39, count 0 2006.217.07:59:58.26#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.217.07:59:58.26#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.217.07:59:58.26#ibcon#about to clear, iclass 39 cls_cnt 0 2006.217.07:59:58.26#ibcon#cleared, iclass 39 cls_cnt 0 2006.217.07:59:58.26$vc4f8/va=2,4 2006.217.07:59:58.26#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.217.07:59:58.26#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.217.07:59:58.26#ibcon#ireg 11 cls_cnt 2 2006.217.07:59:58.26#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.217.07:59:58.32#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.217.07:59:58.32#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.217.07:59:58.32#ibcon#enter wrdev, iclass 3, count 2 2006.217.07:59:58.32#ibcon#first serial, iclass 3, count 2 2006.217.07:59:58.32#ibcon#enter sib2, iclass 3, count 2 2006.217.07:59:58.32#ibcon#flushed, iclass 3, count 2 2006.217.07:59:58.32#ibcon#about to write, iclass 3, count 2 2006.217.07:59:58.32#ibcon#wrote, iclass 3, count 2 2006.217.07:59:58.32#ibcon#about to read 3, iclass 3, count 2 2006.217.07:59:58.34#ibcon#read 3, iclass 3, count 2 2006.217.07:59:58.34#ibcon#about to read 4, iclass 3, count 2 2006.217.07:59:58.34#ibcon#read 4, iclass 3, count 2 2006.217.07:59:58.34#ibcon#about to read 5, iclass 3, count 2 2006.217.07:59:58.34#ibcon#read 5, iclass 3, count 2 2006.217.07:59:58.34#ibcon#about to read 6, iclass 3, count 2 2006.217.07:59:58.34#ibcon#read 6, iclass 3, count 2 2006.217.07:59:58.34#ibcon#end of sib2, iclass 3, count 2 2006.217.07:59:58.34#ibcon#*mode == 0, iclass 3, count 2 2006.217.07:59:58.34#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.217.07:59:58.34#ibcon#[25=AT02-04\r\n] 2006.217.07:59:58.34#ibcon#*before write, iclass 3, count 2 2006.217.07:59:58.34#ibcon#enter sib2, iclass 3, count 2 2006.217.07:59:58.34#ibcon#flushed, iclass 3, count 2 2006.217.07:59:58.34#ibcon#about to write, iclass 3, count 2 2006.217.07:59:58.34#ibcon#wrote, iclass 3, count 2 2006.217.07:59:58.34#ibcon#about to read 3, iclass 3, count 2 2006.217.07:59:58.37#ibcon#read 3, iclass 3, count 2 2006.217.07:59:58.37#ibcon#about to read 4, iclass 3, count 2 2006.217.07:59:58.37#ibcon#read 4, iclass 3, count 2 2006.217.07:59:58.37#ibcon#about to read 5, iclass 3, count 2 2006.217.07:59:58.37#ibcon#read 5, iclass 3, count 2 2006.217.07:59:58.37#ibcon#about to read 6, iclass 3, count 2 2006.217.07:59:58.37#ibcon#read 6, iclass 3, count 2 2006.217.07:59:58.37#ibcon#end of sib2, iclass 3, count 2 2006.217.07:59:58.37#ibcon#*after write, iclass 3, count 2 2006.217.07:59:58.37#ibcon#*before return 0, iclass 3, count 2 2006.217.07:59:58.37#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.217.07:59:58.37#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.217.07:59:58.37#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.217.07:59:58.37#ibcon#ireg 7 cls_cnt 0 2006.217.07:59:58.37#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.217.07:59:58.49#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.217.07:59:58.49#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.217.07:59:58.49#ibcon#enter wrdev, iclass 3, count 0 2006.217.07:59:58.49#ibcon#first serial, iclass 3, count 0 2006.217.07:59:58.49#ibcon#enter sib2, iclass 3, count 0 2006.217.07:59:58.49#ibcon#flushed, iclass 3, count 0 2006.217.07:59:58.49#ibcon#about to write, iclass 3, count 0 2006.217.07:59:58.49#ibcon#wrote, iclass 3, count 0 2006.217.07:59:58.49#ibcon#about to read 3, iclass 3, count 0 2006.217.07:59:58.51#ibcon#read 3, iclass 3, count 0 2006.217.07:59:58.51#ibcon#about to read 4, iclass 3, count 0 2006.217.07:59:58.51#ibcon#read 4, iclass 3, count 0 2006.217.07:59:58.51#ibcon#about to read 5, iclass 3, count 0 2006.217.07:59:58.51#ibcon#read 5, iclass 3, count 0 2006.217.07:59:58.51#ibcon#about to read 6, iclass 3, count 0 2006.217.07:59:58.51#ibcon#read 6, iclass 3, count 0 2006.217.07:59:58.51#ibcon#end of sib2, iclass 3, count 0 2006.217.07:59:58.51#ibcon#*mode == 0, iclass 3, count 0 2006.217.07:59:58.51#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.217.07:59:58.51#ibcon#[25=USB\r\n] 2006.217.07:59:58.51#ibcon#*before write, iclass 3, count 0 2006.217.07:59:58.51#ibcon#enter sib2, iclass 3, count 0 2006.217.07:59:58.51#ibcon#flushed, iclass 3, count 0 2006.217.07:59:58.51#ibcon#about to write, iclass 3, count 0 2006.217.07:59:58.51#ibcon#wrote, iclass 3, count 0 2006.217.07:59:58.51#ibcon#about to read 3, iclass 3, count 0 2006.217.07:59:58.54#ibcon#read 3, iclass 3, count 0 2006.217.07:59:58.54#ibcon#about to read 4, iclass 3, count 0 2006.217.07:59:58.54#ibcon#read 4, iclass 3, count 0 2006.217.07:59:58.54#ibcon#about to read 5, iclass 3, count 0 2006.217.07:59:58.54#ibcon#read 5, iclass 3, count 0 2006.217.07:59:58.54#ibcon#about to read 6, iclass 3, count 0 2006.217.07:59:58.54#ibcon#read 6, iclass 3, count 0 2006.217.07:59:58.54#ibcon#end of sib2, iclass 3, count 0 2006.217.07:59:58.54#ibcon#*after write, iclass 3, count 0 2006.217.07:59:58.54#ibcon#*before return 0, iclass 3, count 0 2006.217.07:59:58.54#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.217.07:59:58.54#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.217.07:59:58.54#ibcon#about to clear, iclass 3 cls_cnt 0 2006.217.07:59:58.54#ibcon#cleared, iclass 3 cls_cnt 0 2006.217.07:59:58.54$vc4f8/valo=3,672.99 2006.217.07:59:58.54#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.217.07:59:58.54#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.217.07:59:58.54#ibcon#ireg 17 cls_cnt 0 2006.217.07:59:58.54#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.217.07:59:58.54#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.217.07:59:58.54#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.217.07:59:58.54#ibcon#enter wrdev, iclass 5, count 0 2006.217.07:59:58.54#ibcon#first serial, iclass 5, count 0 2006.217.07:59:58.54#ibcon#enter sib2, iclass 5, count 0 2006.217.07:59:58.54#ibcon#flushed, iclass 5, count 0 2006.217.07:59:58.54#ibcon#about to write, iclass 5, count 0 2006.217.07:59:58.54#ibcon#wrote, iclass 5, count 0 2006.217.07:59:58.54#ibcon#about to read 3, iclass 5, count 0 2006.217.07:59:58.56#ibcon#read 3, iclass 5, count 0 2006.217.07:59:58.56#ibcon#about to read 4, iclass 5, count 0 2006.217.07:59:58.56#ibcon#read 4, iclass 5, count 0 2006.217.07:59:58.56#ibcon#about to read 5, iclass 5, count 0 2006.217.07:59:58.56#ibcon#read 5, iclass 5, count 0 2006.217.07:59:58.56#ibcon#about to read 6, iclass 5, count 0 2006.217.07:59:58.56#ibcon#read 6, iclass 5, count 0 2006.217.07:59:58.56#ibcon#end of sib2, iclass 5, count 0 2006.217.07:59:58.56#ibcon#*mode == 0, iclass 5, count 0 2006.217.07:59:58.56#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.217.07:59:58.56#ibcon#[26=FRQ=03,672.99\r\n] 2006.217.07:59:58.56#ibcon#*before write, iclass 5, count 0 2006.217.07:59:58.56#ibcon#enter sib2, iclass 5, count 0 2006.217.07:59:58.56#ibcon#flushed, iclass 5, count 0 2006.217.07:59:58.56#ibcon#about to write, iclass 5, count 0 2006.217.07:59:58.56#ibcon#wrote, iclass 5, count 0 2006.217.07:59:58.56#ibcon#about to read 3, iclass 5, count 0 2006.217.07:59:58.60#ibcon#read 3, iclass 5, count 0 2006.217.07:59:58.60#ibcon#about to read 4, iclass 5, count 0 2006.217.07:59:58.60#ibcon#read 4, iclass 5, count 0 2006.217.07:59:58.60#ibcon#about to read 5, iclass 5, count 0 2006.217.07:59:58.60#ibcon#read 5, iclass 5, count 0 2006.217.07:59:58.60#ibcon#about to read 6, iclass 5, count 0 2006.217.07:59:58.60#ibcon#read 6, iclass 5, count 0 2006.217.07:59:58.60#ibcon#end of sib2, iclass 5, count 0 2006.217.07:59:58.60#ibcon#*after write, iclass 5, count 0 2006.217.07:59:58.60#ibcon#*before return 0, iclass 5, count 0 2006.217.07:59:58.60#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.217.07:59:58.60#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.217.07:59:58.60#ibcon#about to clear, iclass 5 cls_cnt 0 2006.217.07:59:58.60#ibcon#cleared, iclass 5 cls_cnt 0 2006.217.07:59:58.60$vc4f8/va=3,4 2006.217.07:59:58.60#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.217.07:59:58.60#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.217.07:59:58.60#ibcon#ireg 11 cls_cnt 2 2006.217.07:59:58.60#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.217.07:59:58.66#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.217.07:59:58.66#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.217.07:59:58.66#ibcon#enter wrdev, iclass 7, count 2 2006.217.07:59:58.66#ibcon#first serial, iclass 7, count 2 2006.217.07:59:58.66#ibcon#enter sib2, iclass 7, count 2 2006.217.07:59:58.66#ibcon#flushed, iclass 7, count 2 2006.217.07:59:58.66#ibcon#about to write, iclass 7, count 2 2006.217.07:59:58.66#ibcon#wrote, iclass 7, count 2 2006.217.07:59:58.66#ibcon#about to read 3, iclass 7, count 2 2006.217.07:59:58.69#ibcon#read 3, iclass 7, count 2 2006.217.07:59:58.69#ibcon#about to read 4, iclass 7, count 2 2006.217.07:59:58.69#ibcon#read 4, iclass 7, count 2 2006.217.07:59:58.69#ibcon#about to read 5, iclass 7, count 2 2006.217.07:59:58.69#ibcon#read 5, iclass 7, count 2 2006.217.07:59:58.69#ibcon#about to read 6, iclass 7, count 2 2006.217.07:59:58.69#ibcon#read 6, iclass 7, count 2 2006.217.07:59:58.69#ibcon#end of sib2, iclass 7, count 2 2006.217.07:59:58.69#ibcon#*mode == 0, iclass 7, count 2 2006.217.07:59:58.69#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.217.07:59:58.69#ibcon#[25=AT03-04\r\n] 2006.217.07:59:58.69#ibcon#*before write, iclass 7, count 2 2006.217.07:59:58.69#ibcon#enter sib2, iclass 7, count 2 2006.217.07:59:58.69#ibcon#flushed, iclass 7, count 2 2006.217.07:59:58.69#ibcon#about to write, iclass 7, count 2 2006.217.07:59:58.69#ibcon#wrote, iclass 7, count 2 2006.217.07:59:58.69#ibcon#about to read 3, iclass 7, count 2 2006.217.07:59:58.72#ibcon#read 3, iclass 7, count 2 2006.217.07:59:58.72#ibcon#about to read 4, iclass 7, count 2 2006.217.07:59:58.72#ibcon#read 4, iclass 7, count 2 2006.217.07:59:58.72#ibcon#about to read 5, iclass 7, count 2 2006.217.07:59:58.72#ibcon#read 5, iclass 7, count 2 2006.217.07:59:58.72#ibcon#about to read 6, iclass 7, count 2 2006.217.07:59:58.72#ibcon#read 6, iclass 7, count 2 2006.217.07:59:58.72#ibcon#end of sib2, iclass 7, count 2 2006.217.07:59:58.72#ibcon#*after write, iclass 7, count 2 2006.217.07:59:58.72#ibcon#*before return 0, iclass 7, count 2 2006.217.07:59:58.72#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.217.07:59:58.72#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.217.07:59:58.72#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.217.07:59:58.72#ibcon#ireg 7 cls_cnt 0 2006.217.07:59:58.72#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.217.07:59:58.84#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.217.07:59:58.84#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.217.07:59:58.84#ibcon#enter wrdev, iclass 7, count 0 2006.217.07:59:58.84#ibcon#first serial, iclass 7, count 0 2006.217.07:59:58.84#ibcon#enter sib2, iclass 7, count 0 2006.217.07:59:58.84#ibcon#flushed, iclass 7, count 0 2006.217.07:59:58.84#ibcon#about to write, iclass 7, count 0 2006.217.07:59:58.84#ibcon#wrote, iclass 7, count 0 2006.217.07:59:58.84#ibcon#about to read 3, iclass 7, count 0 2006.217.07:59:58.86#ibcon#read 3, iclass 7, count 0 2006.217.07:59:58.86#ibcon#about to read 4, iclass 7, count 0 2006.217.07:59:58.86#ibcon#read 4, iclass 7, count 0 2006.217.07:59:58.86#ibcon#about to read 5, iclass 7, count 0 2006.217.07:59:58.86#ibcon#read 5, iclass 7, count 0 2006.217.07:59:58.86#ibcon#about to read 6, iclass 7, count 0 2006.217.07:59:58.86#ibcon#read 6, iclass 7, count 0 2006.217.07:59:58.86#ibcon#end of sib2, iclass 7, count 0 2006.217.07:59:58.86#ibcon#*mode == 0, iclass 7, count 0 2006.217.07:59:58.86#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.217.07:59:58.86#ibcon#[25=USB\r\n] 2006.217.07:59:58.86#ibcon#*before write, iclass 7, count 0 2006.217.07:59:58.86#ibcon#enter sib2, iclass 7, count 0 2006.217.07:59:58.86#ibcon#flushed, iclass 7, count 0 2006.217.07:59:58.86#ibcon#about to write, iclass 7, count 0 2006.217.07:59:58.86#ibcon#wrote, iclass 7, count 0 2006.217.07:59:58.86#ibcon#about to read 3, iclass 7, count 0 2006.217.07:59:58.89#ibcon#read 3, iclass 7, count 0 2006.217.07:59:58.89#ibcon#about to read 4, iclass 7, count 0 2006.217.07:59:58.89#ibcon#read 4, iclass 7, count 0 2006.217.07:59:58.89#ibcon#about to read 5, iclass 7, count 0 2006.217.07:59:58.89#ibcon#read 5, iclass 7, count 0 2006.217.07:59:58.89#ibcon#about to read 6, iclass 7, count 0 2006.217.07:59:58.89#ibcon#read 6, iclass 7, count 0 2006.217.07:59:58.89#ibcon#end of sib2, iclass 7, count 0 2006.217.07:59:58.89#ibcon#*after write, iclass 7, count 0 2006.217.07:59:58.89#ibcon#*before return 0, iclass 7, count 0 2006.217.07:59:58.89#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.217.07:59:58.89#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.217.07:59:58.89#ibcon#about to clear, iclass 7 cls_cnt 0 2006.217.07:59:58.89#ibcon#cleared, iclass 7 cls_cnt 0 2006.217.07:59:58.89$vc4f8/valo=4,832.99 2006.217.07:59:58.89#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.217.07:59:58.89#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.217.07:59:58.89#ibcon#ireg 17 cls_cnt 0 2006.217.07:59:58.89#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.217.07:59:58.89#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.217.07:59:58.89#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.217.07:59:58.89#ibcon#enter wrdev, iclass 11, count 0 2006.217.07:59:58.89#ibcon#first serial, iclass 11, count 0 2006.217.07:59:58.89#ibcon#enter sib2, iclass 11, count 0 2006.217.07:59:58.89#ibcon#flushed, iclass 11, count 0 2006.217.07:59:58.89#ibcon#about to write, iclass 11, count 0 2006.217.07:59:58.89#ibcon#wrote, iclass 11, count 0 2006.217.07:59:58.89#ibcon#about to read 3, iclass 11, count 0 2006.217.07:59:58.91#ibcon#read 3, iclass 11, count 0 2006.217.07:59:58.91#ibcon#about to read 4, iclass 11, count 0 2006.217.07:59:58.91#ibcon#read 4, iclass 11, count 0 2006.217.07:59:58.91#ibcon#about to read 5, iclass 11, count 0 2006.217.07:59:58.91#ibcon#read 5, iclass 11, count 0 2006.217.07:59:58.91#ibcon#about to read 6, iclass 11, count 0 2006.217.07:59:58.91#ibcon#read 6, iclass 11, count 0 2006.217.07:59:58.91#ibcon#end of sib2, iclass 11, count 0 2006.217.07:59:58.91#ibcon#*mode == 0, iclass 11, count 0 2006.217.07:59:58.91#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.217.07:59:58.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.217.07:59:58.91#ibcon#*before write, iclass 11, count 0 2006.217.07:59:58.91#ibcon#enter sib2, iclass 11, count 0 2006.217.07:59:58.91#ibcon#flushed, iclass 11, count 0 2006.217.07:59:58.91#ibcon#about to write, iclass 11, count 0 2006.217.07:59:58.91#ibcon#wrote, iclass 11, count 0 2006.217.07:59:58.91#ibcon#about to read 3, iclass 11, count 0 2006.217.07:59:58.95#ibcon#read 3, iclass 11, count 0 2006.217.07:59:58.95#ibcon#about to read 4, iclass 11, count 0 2006.217.07:59:58.95#ibcon#read 4, iclass 11, count 0 2006.217.07:59:58.95#ibcon#about to read 5, iclass 11, count 0 2006.217.07:59:58.95#ibcon#read 5, iclass 11, count 0 2006.217.07:59:58.95#ibcon#about to read 6, iclass 11, count 0 2006.217.07:59:58.95#ibcon#read 6, iclass 11, count 0 2006.217.07:59:58.95#ibcon#end of sib2, iclass 11, count 0 2006.217.07:59:58.95#ibcon#*after write, iclass 11, count 0 2006.217.07:59:58.95#ibcon#*before return 0, iclass 11, count 0 2006.217.07:59:58.95#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.217.07:59:58.95#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.217.07:59:58.95#ibcon#about to clear, iclass 11 cls_cnt 0 2006.217.07:59:58.95#ibcon#cleared, iclass 11 cls_cnt 0 2006.217.07:59:58.95$vc4f8/va=4,4 2006.217.07:59:58.95#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.217.07:59:58.95#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.217.07:59:58.95#ibcon#ireg 11 cls_cnt 2 2006.217.07:59:58.95#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.217.07:59:59.01#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.217.07:59:59.01#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.217.07:59:59.01#ibcon#enter wrdev, iclass 13, count 2 2006.217.07:59:59.01#ibcon#first serial, iclass 13, count 2 2006.217.07:59:59.01#ibcon#enter sib2, iclass 13, count 2 2006.217.07:59:59.01#ibcon#flushed, iclass 13, count 2 2006.217.07:59:59.01#ibcon#about to write, iclass 13, count 2 2006.217.07:59:59.01#ibcon#wrote, iclass 13, count 2 2006.217.07:59:59.01#ibcon#about to read 3, iclass 13, count 2 2006.217.07:59:59.03#ibcon#read 3, iclass 13, count 2 2006.217.07:59:59.03#ibcon#about to read 4, iclass 13, count 2 2006.217.07:59:59.03#ibcon#read 4, iclass 13, count 2 2006.217.07:59:59.03#ibcon#about to read 5, iclass 13, count 2 2006.217.07:59:59.03#ibcon#read 5, iclass 13, count 2 2006.217.07:59:59.03#ibcon#about to read 6, iclass 13, count 2 2006.217.07:59:59.03#ibcon#read 6, iclass 13, count 2 2006.217.07:59:59.03#ibcon#end of sib2, iclass 13, count 2 2006.217.07:59:59.03#ibcon#*mode == 0, iclass 13, count 2 2006.217.07:59:59.03#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.217.07:59:59.03#ibcon#[25=AT04-04\r\n] 2006.217.07:59:59.03#ibcon#*before write, iclass 13, count 2 2006.217.07:59:59.03#ibcon#enter sib2, iclass 13, count 2 2006.217.07:59:59.03#ibcon#flushed, iclass 13, count 2 2006.217.07:59:59.03#ibcon#about to write, iclass 13, count 2 2006.217.07:59:59.03#ibcon#wrote, iclass 13, count 2 2006.217.07:59:59.03#ibcon#about to read 3, iclass 13, count 2 2006.217.07:59:59.06#ibcon#read 3, iclass 13, count 2 2006.217.07:59:59.06#ibcon#about to read 4, iclass 13, count 2 2006.217.07:59:59.06#ibcon#read 4, iclass 13, count 2 2006.217.07:59:59.06#ibcon#about to read 5, iclass 13, count 2 2006.217.07:59:59.06#ibcon#read 5, iclass 13, count 2 2006.217.07:59:59.06#ibcon#about to read 6, iclass 13, count 2 2006.217.07:59:59.06#ibcon#read 6, iclass 13, count 2 2006.217.07:59:59.06#ibcon#end of sib2, iclass 13, count 2 2006.217.07:59:59.06#ibcon#*after write, iclass 13, count 2 2006.217.07:59:59.06#ibcon#*before return 0, iclass 13, count 2 2006.217.07:59:59.06#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.217.07:59:59.06#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.217.07:59:59.06#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.217.07:59:59.06#ibcon#ireg 7 cls_cnt 0 2006.217.07:59:59.06#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.217.07:59:59.18#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.217.07:59:59.18#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.217.07:59:59.18#ibcon#enter wrdev, iclass 13, count 0 2006.217.07:59:59.18#ibcon#first serial, iclass 13, count 0 2006.217.07:59:59.18#ibcon#enter sib2, iclass 13, count 0 2006.217.07:59:59.18#ibcon#flushed, iclass 13, count 0 2006.217.07:59:59.18#ibcon#about to write, iclass 13, count 0 2006.217.07:59:59.18#ibcon#wrote, iclass 13, count 0 2006.217.07:59:59.18#ibcon#about to read 3, iclass 13, count 0 2006.217.07:59:59.20#ibcon#read 3, iclass 13, count 0 2006.217.07:59:59.20#ibcon#about to read 4, iclass 13, count 0 2006.217.07:59:59.20#ibcon#read 4, iclass 13, count 0 2006.217.07:59:59.20#ibcon#about to read 5, iclass 13, count 0 2006.217.07:59:59.20#ibcon#read 5, iclass 13, count 0 2006.217.07:59:59.20#ibcon#about to read 6, iclass 13, count 0 2006.217.07:59:59.20#ibcon#read 6, iclass 13, count 0 2006.217.07:59:59.20#ibcon#end of sib2, iclass 13, count 0 2006.217.07:59:59.20#ibcon#*mode == 0, iclass 13, count 0 2006.217.07:59:59.20#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.217.07:59:59.20#ibcon#[25=USB\r\n] 2006.217.07:59:59.20#ibcon#*before write, iclass 13, count 0 2006.217.07:59:59.20#ibcon#enter sib2, iclass 13, count 0 2006.217.07:59:59.20#ibcon#flushed, iclass 13, count 0 2006.217.07:59:59.20#ibcon#about to write, iclass 13, count 0 2006.217.07:59:59.20#ibcon#wrote, iclass 13, count 0 2006.217.07:59:59.20#ibcon#about to read 3, iclass 13, count 0 2006.217.07:59:59.23#ibcon#read 3, iclass 13, count 0 2006.217.07:59:59.23#ibcon#about to read 4, iclass 13, count 0 2006.217.07:59:59.23#ibcon#read 4, iclass 13, count 0 2006.217.07:59:59.23#ibcon#about to read 5, iclass 13, count 0 2006.217.07:59:59.23#ibcon#read 5, iclass 13, count 0 2006.217.07:59:59.23#ibcon#about to read 6, iclass 13, count 0 2006.217.07:59:59.23#ibcon#read 6, iclass 13, count 0 2006.217.07:59:59.23#ibcon#end of sib2, iclass 13, count 0 2006.217.07:59:59.23#ibcon#*after write, iclass 13, count 0 2006.217.07:59:59.23#ibcon#*before return 0, iclass 13, count 0 2006.217.07:59:59.23#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.217.07:59:59.23#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.217.07:59:59.23#ibcon#about to clear, iclass 13 cls_cnt 0 2006.217.07:59:59.23#ibcon#cleared, iclass 13 cls_cnt 0 2006.217.07:59:59.23$vc4f8/valo=5,652.99 2006.217.07:59:59.23#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.217.07:59:59.23#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.217.07:59:59.23#ibcon#ireg 17 cls_cnt 0 2006.217.07:59:59.23#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.217.07:59:59.23#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.217.07:59:59.23#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.217.07:59:59.23#ibcon#enter wrdev, iclass 15, count 0 2006.217.07:59:59.23#ibcon#first serial, iclass 15, count 0 2006.217.07:59:59.23#ibcon#enter sib2, iclass 15, count 0 2006.217.07:59:59.23#ibcon#flushed, iclass 15, count 0 2006.217.07:59:59.23#ibcon#about to write, iclass 15, count 0 2006.217.07:59:59.23#ibcon#wrote, iclass 15, count 0 2006.217.07:59:59.23#ibcon#about to read 3, iclass 15, count 0 2006.217.07:59:59.25#ibcon#read 3, iclass 15, count 0 2006.217.07:59:59.25#ibcon#about to read 4, iclass 15, count 0 2006.217.07:59:59.25#ibcon#read 4, iclass 15, count 0 2006.217.07:59:59.25#ibcon#about to read 5, iclass 15, count 0 2006.217.07:59:59.25#ibcon#read 5, iclass 15, count 0 2006.217.07:59:59.25#ibcon#about to read 6, iclass 15, count 0 2006.217.07:59:59.25#ibcon#read 6, iclass 15, count 0 2006.217.07:59:59.25#ibcon#end of sib2, iclass 15, count 0 2006.217.07:59:59.25#ibcon#*mode == 0, iclass 15, count 0 2006.217.07:59:59.25#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.217.07:59:59.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.217.07:59:59.25#ibcon#*before write, iclass 15, count 0 2006.217.07:59:59.25#ibcon#enter sib2, iclass 15, count 0 2006.217.07:59:59.25#ibcon#flushed, iclass 15, count 0 2006.217.07:59:59.25#ibcon#about to write, iclass 15, count 0 2006.217.07:59:59.25#ibcon#wrote, iclass 15, count 0 2006.217.07:59:59.25#ibcon#about to read 3, iclass 15, count 0 2006.217.07:59:59.29#ibcon#read 3, iclass 15, count 0 2006.217.07:59:59.29#ibcon#about to read 4, iclass 15, count 0 2006.217.07:59:59.29#ibcon#read 4, iclass 15, count 0 2006.217.07:59:59.29#ibcon#about to read 5, iclass 15, count 0 2006.217.07:59:59.29#ibcon#read 5, iclass 15, count 0 2006.217.07:59:59.29#ibcon#about to read 6, iclass 15, count 0 2006.217.07:59:59.29#ibcon#read 6, iclass 15, count 0 2006.217.07:59:59.29#ibcon#end of sib2, iclass 15, count 0 2006.217.07:59:59.29#ibcon#*after write, iclass 15, count 0 2006.217.07:59:59.29#ibcon#*before return 0, iclass 15, count 0 2006.217.07:59:59.29#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.217.07:59:59.29#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.217.07:59:59.29#ibcon#about to clear, iclass 15 cls_cnt 0 2006.217.07:59:59.29#ibcon#cleared, iclass 15 cls_cnt 0 2006.217.07:59:59.29$vc4f8/va=5,7 2006.217.07:59:59.29#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.217.07:59:59.29#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.217.07:59:59.29#ibcon#ireg 11 cls_cnt 2 2006.217.07:59:59.29#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.217.07:59:59.35#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.217.07:59:59.35#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.217.07:59:59.35#ibcon#enter wrdev, iclass 17, count 2 2006.217.07:59:59.35#ibcon#first serial, iclass 17, count 2 2006.217.07:59:59.35#ibcon#enter sib2, iclass 17, count 2 2006.217.07:59:59.35#ibcon#flushed, iclass 17, count 2 2006.217.07:59:59.35#ibcon#about to write, iclass 17, count 2 2006.217.07:59:59.35#ibcon#wrote, iclass 17, count 2 2006.217.07:59:59.35#ibcon#about to read 3, iclass 17, count 2 2006.217.07:59:59.37#ibcon#read 3, iclass 17, count 2 2006.217.07:59:59.37#ibcon#about to read 4, iclass 17, count 2 2006.217.07:59:59.37#ibcon#read 4, iclass 17, count 2 2006.217.07:59:59.37#ibcon#about to read 5, iclass 17, count 2 2006.217.07:59:59.37#ibcon#read 5, iclass 17, count 2 2006.217.07:59:59.37#ibcon#about to read 6, iclass 17, count 2 2006.217.07:59:59.37#ibcon#read 6, iclass 17, count 2 2006.217.07:59:59.37#ibcon#end of sib2, iclass 17, count 2 2006.217.07:59:59.37#ibcon#*mode == 0, iclass 17, count 2 2006.217.07:59:59.37#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.217.07:59:59.37#ibcon#[25=AT05-07\r\n] 2006.217.07:59:59.37#ibcon#*before write, iclass 17, count 2 2006.217.07:59:59.37#ibcon#enter sib2, iclass 17, count 2 2006.217.07:59:59.37#ibcon#flushed, iclass 17, count 2 2006.217.07:59:59.37#ibcon#about to write, iclass 17, count 2 2006.217.07:59:59.37#ibcon#wrote, iclass 17, count 2 2006.217.07:59:59.37#ibcon#about to read 3, iclass 17, count 2 2006.217.07:59:59.40#ibcon#read 3, iclass 17, count 2 2006.217.07:59:59.40#ibcon#about to read 4, iclass 17, count 2 2006.217.07:59:59.40#ibcon#read 4, iclass 17, count 2 2006.217.07:59:59.40#ibcon#about to read 5, iclass 17, count 2 2006.217.07:59:59.40#ibcon#read 5, iclass 17, count 2 2006.217.07:59:59.40#ibcon#about to read 6, iclass 17, count 2 2006.217.07:59:59.40#ibcon#read 6, iclass 17, count 2 2006.217.07:59:59.40#ibcon#end of sib2, iclass 17, count 2 2006.217.07:59:59.40#ibcon#*after write, iclass 17, count 2 2006.217.07:59:59.40#ibcon#*before return 0, iclass 17, count 2 2006.217.07:59:59.40#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.217.07:59:59.40#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.217.07:59:59.40#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.217.07:59:59.40#ibcon#ireg 7 cls_cnt 0 2006.217.07:59:59.40#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.217.07:59:59.52#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.217.07:59:59.52#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.217.07:59:59.52#ibcon#enter wrdev, iclass 17, count 0 2006.217.07:59:59.52#ibcon#first serial, iclass 17, count 0 2006.217.07:59:59.52#ibcon#enter sib2, iclass 17, count 0 2006.217.07:59:59.52#ibcon#flushed, iclass 17, count 0 2006.217.07:59:59.52#ibcon#about to write, iclass 17, count 0 2006.217.07:59:59.52#ibcon#wrote, iclass 17, count 0 2006.217.07:59:59.52#ibcon#about to read 3, iclass 17, count 0 2006.217.07:59:59.54#ibcon#read 3, iclass 17, count 0 2006.217.07:59:59.54#ibcon#about to read 4, iclass 17, count 0 2006.217.07:59:59.54#ibcon#read 4, iclass 17, count 0 2006.217.07:59:59.54#ibcon#about to read 5, iclass 17, count 0 2006.217.07:59:59.54#ibcon#read 5, iclass 17, count 0 2006.217.07:59:59.54#ibcon#about to read 6, iclass 17, count 0 2006.217.07:59:59.54#ibcon#read 6, iclass 17, count 0 2006.217.07:59:59.54#ibcon#end of sib2, iclass 17, count 0 2006.217.07:59:59.54#ibcon#*mode == 0, iclass 17, count 0 2006.217.07:59:59.54#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.217.07:59:59.54#ibcon#[25=USB\r\n] 2006.217.07:59:59.54#ibcon#*before write, iclass 17, count 0 2006.217.07:59:59.54#ibcon#enter sib2, iclass 17, count 0 2006.217.07:59:59.54#ibcon#flushed, iclass 17, count 0 2006.217.07:59:59.54#ibcon#about to write, iclass 17, count 0 2006.217.07:59:59.54#ibcon#wrote, iclass 17, count 0 2006.217.07:59:59.54#ibcon#about to read 3, iclass 17, count 0 2006.217.07:59:59.57#ibcon#read 3, iclass 17, count 0 2006.217.07:59:59.57#ibcon#about to read 4, iclass 17, count 0 2006.217.07:59:59.57#ibcon#read 4, iclass 17, count 0 2006.217.07:59:59.57#ibcon#about to read 5, iclass 17, count 0 2006.217.07:59:59.57#ibcon#read 5, iclass 17, count 0 2006.217.07:59:59.57#ibcon#about to read 6, iclass 17, count 0 2006.217.07:59:59.57#ibcon#read 6, iclass 17, count 0 2006.217.07:59:59.57#ibcon#end of sib2, iclass 17, count 0 2006.217.07:59:59.57#ibcon#*after write, iclass 17, count 0 2006.217.07:59:59.57#ibcon#*before return 0, iclass 17, count 0 2006.217.07:59:59.57#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.217.07:59:59.57#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.217.07:59:59.57#ibcon#about to clear, iclass 17 cls_cnt 0 2006.217.07:59:59.57#ibcon#cleared, iclass 17 cls_cnt 0 2006.217.07:59:59.57$vc4f8/valo=6,772.99 2006.217.07:59:59.57#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.217.07:59:59.57#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.217.07:59:59.57#ibcon#ireg 17 cls_cnt 0 2006.217.07:59:59.57#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.217.07:59:59.57#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.217.07:59:59.57#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.217.07:59:59.57#ibcon#enter wrdev, iclass 19, count 0 2006.217.07:59:59.57#ibcon#first serial, iclass 19, count 0 2006.217.07:59:59.57#ibcon#enter sib2, iclass 19, count 0 2006.217.07:59:59.57#ibcon#flushed, iclass 19, count 0 2006.217.07:59:59.57#ibcon#about to write, iclass 19, count 0 2006.217.07:59:59.57#ibcon#wrote, iclass 19, count 0 2006.217.07:59:59.57#ibcon#about to read 3, iclass 19, count 0 2006.217.07:59:59.59#ibcon#read 3, iclass 19, count 0 2006.217.07:59:59.59#ibcon#about to read 4, iclass 19, count 0 2006.217.07:59:59.59#ibcon#read 4, iclass 19, count 0 2006.217.07:59:59.59#ibcon#about to read 5, iclass 19, count 0 2006.217.07:59:59.59#ibcon#read 5, iclass 19, count 0 2006.217.07:59:59.59#ibcon#about to read 6, iclass 19, count 0 2006.217.07:59:59.59#ibcon#read 6, iclass 19, count 0 2006.217.07:59:59.59#ibcon#end of sib2, iclass 19, count 0 2006.217.07:59:59.59#ibcon#*mode == 0, iclass 19, count 0 2006.217.07:59:59.59#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.217.07:59:59.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.217.07:59:59.59#ibcon#*before write, iclass 19, count 0 2006.217.07:59:59.59#ibcon#enter sib2, iclass 19, count 0 2006.217.07:59:59.59#ibcon#flushed, iclass 19, count 0 2006.217.07:59:59.59#ibcon#about to write, iclass 19, count 0 2006.217.07:59:59.59#ibcon#wrote, iclass 19, count 0 2006.217.07:59:59.59#ibcon#about to read 3, iclass 19, count 0 2006.217.07:59:59.63#ibcon#read 3, iclass 19, count 0 2006.217.07:59:59.63#ibcon#about to read 4, iclass 19, count 0 2006.217.07:59:59.63#ibcon#read 4, iclass 19, count 0 2006.217.07:59:59.63#ibcon#about to read 5, iclass 19, count 0 2006.217.07:59:59.63#ibcon#read 5, iclass 19, count 0 2006.217.07:59:59.63#ibcon#about to read 6, iclass 19, count 0 2006.217.07:59:59.63#ibcon#read 6, iclass 19, count 0 2006.217.07:59:59.63#ibcon#end of sib2, iclass 19, count 0 2006.217.07:59:59.63#ibcon#*after write, iclass 19, count 0 2006.217.07:59:59.63#ibcon#*before return 0, iclass 19, count 0 2006.217.07:59:59.63#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.217.07:59:59.63#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.217.07:59:59.63#ibcon#about to clear, iclass 19 cls_cnt 0 2006.217.07:59:59.63#ibcon#cleared, iclass 19 cls_cnt 0 2006.217.07:59:59.63$vc4f8/va=6,6 2006.217.07:59:59.63#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.217.07:59:59.63#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.217.07:59:59.63#ibcon#ireg 11 cls_cnt 2 2006.217.07:59:59.63#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.217.07:59:59.69#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.217.07:59:59.69#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.217.07:59:59.69#ibcon#enter wrdev, iclass 21, count 2 2006.217.07:59:59.69#ibcon#first serial, iclass 21, count 2 2006.217.07:59:59.69#ibcon#enter sib2, iclass 21, count 2 2006.217.07:59:59.69#ibcon#flushed, iclass 21, count 2 2006.217.07:59:59.69#ibcon#about to write, iclass 21, count 2 2006.217.07:59:59.69#ibcon#wrote, iclass 21, count 2 2006.217.07:59:59.69#ibcon#about to read 3, iclass 21, count 2 2006.217.07:59:59.71#ibcon#read 3, iclass 21, count 2 2006.217.07:59:59.71#ibcon#about to read 4, iclass 21, count 2 2006.217.07:59:59.71#ibcon#read 4, iclass 21, count 2 2006.217.07:59:59.71#ibcon#about to read 5, iclass 21, count 2 2006.217.07:59:59.71#ibcon#read 5, iclass 21, count 2 2006.217.07:59:59.71#ibcon#about to read 6, iclass 21, count 2 2006.217.07:59:59.71#ibcon#read 6, iclass 21, count 2 2006.217.07:59:59.71#ibcon#end of sib2, iclass 21, count 2 2006.217.07:59:59.71#ibcon#*mode == 0, iclass 21, count 2 2006.217.07:59:59.71#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.217.07:59:59.71#ibcon#[25=AT06-06\r\n] 2006.217.07:59:59.71#ibcon#*before write, iclass 21, count 2 2006.217.07:59:59.71#ibcon#enter sib2, iclass 21, count 2 2006.217.07:59:59.71#ibcon#flushed, iclass 21, count 2 2006.217.07:59:59.71#ibcon#about to write, iclass 21, count 2 2006.217.07:59:59.71#ibcon#wrote, iclass 21, count 2 2006.217.07:59:59.71#ibcon#about to read 3, iclass 21, count 2 2006.217.07:59:59.74#ibcon#read 3, iclass 21, count 2 2006.217.07:59:59.74#ibcon#about to read 4, iclass 21, count 2 2006.217.07:59:59.74#ibcon#read 4, iclass 21, count 2 2006.217.07:59:59.74#ibcon#about to read 5, iclass 21, count 2 2006.217.07:59:59.74#ibcon#read 5, iclass 21, count 2 2006.217.07:59:59.74#ibcon#about to read 6, iclass 21, count 2 2006.217.07:59:59.74#ibcon#read 6, iclass 21, count 2 2006.217.07:59:59.74#ibcon#end of sib2, iclass 21, count 2 2006.217.07:59:59.74#ibcon#*after write, iclass 21, count 2 2006.217.07:59:59.74#ibcon#*before return 0, iclass 21, count 2 2006.217.07:59:59.74#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.217.07:59:59.74#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.217.07:59:59.74#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.217.07:59:59.74#ibcon#ireg 7 cls_cnt 0 2006.217.07:59:59.74#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.217.07:59:59.86#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.217.07:59:59.86#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.217.07:59:59.86#ibcon#enter wrdev, iclass 21, count 0 2006.217.07:59:59.86#ibcon#first serial, iclass 21, count 0 2006.217.07:59:59.86#ibcon#enter sib2, iclass 21, count 0 2006.217.07:59:59.86#ibcon#flushed, iclass 21, count 0 2006.217.07:59:59.86#ibcon#about to write, iclass 21, count 0 2006.217.07:59:59.86#ibcon#wrote, iclass 21, count 0 2006.217.07:59:59.86#ibcon#about to read 3, iclass 21, count 0 2006.217.07:59:59.88#ibcon#read 3, iclass 21, count 0 2006.217.07:59:59.88#ibcon#about to read 4, iclass 21, count 0 2006.217.07:59:59.88#ibcon#read 4, iclass 21, count 0 2006.217.07:59:59.88#ibcon#about to read 5, iclass 21, count 0 2006.217.07:59:59.88#ibcon#read 5, iclass 21, count 0 2006.217.07:59:59.88#ibcon#about to read 6, iclass 21, count 0 2006.217.07:59:59.88#ibcon#read 6, iclass 21, count 0 2006.217.07:59:59.88#ibcon#end of sib2, iclass 21, count 0 2006.217.07:59:59.88#ibcon#*mode == 0, iclass 21, count 0 2006.217.07:59:59.88#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.217.07:59:59.88#ibcon#[25=USB\r\n] 2006.217.07:59:59.88#ibcon#*before write, iclass 21, count 0 2006.217.07:59:59.88#ibcon#enter sib2, iclass 21, count 0 2006.217.07:59:59.88#ibcon#flushed, iclass 21, count 0 2006.217.07:59:59.88#ibcon#about to write, iclass 21, count 0 2006.217.07:59:59.88#ibcon#wrote, iclass 21, count 0 2006.217.07:59:59.88#ibcon#about to read 3, iclass 21, count 0 2006.217.07:59:59.91#ibcon#read 3, iclass 21, count 0 2006.217.07:59:59.91#ibcon#about to read 4, iclass 21, count 0 2006.217.07:59:59.91#ibcon#read 4, iclass 21, count 0 2006.217.07:59:59.91#ibcon#about to read 5, iclass 21, count 0 2006.217.07:59:59.91#ibcon#read 5, iclass 21, count 0 2006.217.07:59:59.91#ibcon#about to read 6, iclass 21, count 0 2006.217.07:59:59.91#ibcon#read 6, iclass 21, count 0 2006.217.07:59:59.91#ibcon#end of sib2, iclass 21, count 0 2006.217.07:59:59.91#ibcon#*after write, iclass 21, count 0 2006.217.07:59:59.91#ibcon#*before return 0, iclass 21, count 0 2006.217.07:59:59.91#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.217.07:59:59.91#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.217.07:59:59.91#ibcon#about to clear, iclass 21 cls_cnt 0 2006.217.07:59:59.91#ibcon#cleared, iclass 21 cls_cnt 0 2006.217.07:59:59.91$vc4f8/valo=7,832.99 2006.217.07:59:59.91#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.217.07:59:59.91#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.217.07:59:59.91#ibcon#ireg 17 cls_cnt 0 2006.217.07:59:59.91#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.217.07:59:59.91#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.217.07:59:59.91#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.217.07:59:59.91#ibcon#enter wrdev, iclass 23, count 0 2006.217.07:59:59.91#ibcon#first serial, iclass 23, count 0 2006.217.07:59:59.91#ibcon#enter sib2, iclass 23, count 0 2006.217.07:59:59.91#ibcon#flushed, iclass 23, count 0 2006.217.07:59:59.91#ibcon#about to write, iclass 23, count 0 2006.217.07:59:59.91#ibcon#wrote, iclass 23, count 0 2006.217.07:59:59.91#ibcon#about to read 3, iclass 23, count 0 2006.217.07:59:59.93#ibcon#read 3, iclass 23, count 0 2006.217.07:59:59.93#ibcon#about to read 4, iclass 23, count 0 2006.217.07:59:59.93#ibcon#read 4, iclass 23, count 0 2006.217.07:59:59.93#ibcon#about to read 5, iclass 23, count 0 2006.217.07:59:59.93#ibcon#read 5, iclass 23, count 0 2006.217.07:59:59.93#ibcon#about to read 6, iclass 23, count 0 2006.217.07:59:59.93#ibcon#read 6, iclass 23, count 0 2006.217.07:59:59.93#ibcon#end of sib2, iclass 23, count 0 2006.217.07:59:59.93#ibcon#*mode == 0, iclass 23, count 0 2006.217.07:59:59.93#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.217.07:59:59.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.217.07:59:59.93#ibcon#*before write, iclass 23, count 0 2006.217.07:59:59.93#ibcon#enter sib2, iclass 23, count 0 2006.217.07:59:59.93#ibcon#flushed, iclass 23, count 0 2006.217.07:59:59.93#ibcon#about to write, iclass 23, count 0 2006.217.07:59:59.93#ibcon#wrote, iclass 23, count 0 2006.217.07:59:59.93#ibcon#about to read 3, iclass 23, count 0 2006.217.07:59:59.97#ibcon#read 3, iclass 23, count 0 2006.217.07:59:59.97#ibcon#about to read 4, iclass 23, count 0 2006.217.07:59:59.97#ibcon#read 4, iclass 23, count 0 2006.217.07:59:59.97#ibcon#about to read 5, iclass 23, count 0 2006.217.07:59:59.97#ibcon#read 5, iclass 23, count 0 2006.217.07:59:59.97#ibcon#about to read 6, iclass 23, count 0 2006.217.07:59:59.97#ibcon#read 6, iclass 23, count 0 2006.217.07:59:59.97#ibcon#end of sib2, iclass 23, count 0 2006.217.07:59:59.97#ibcon#*after write, iclass 23, count 0 2006.217.07:59:59.97#ibcon#*before return 0, iclass 23, count 0 2006.217.07:59:59.97#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.217.07:59:59.97#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.217.07:59:59.97#ibcon#about to clear, iclass 23 cls_cnt 0 2006.217.07:59:59.97#ibcon#cleared, iclass 23 cls_cnt 0 2006.217.07:59:59.97$vc4f8/va=7,6 2006.217.07:59:59.97#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.217.07:59:59.97#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.217.07:59:59.97#ibcon#ireg 11 cls_cnt 2 2006.217.07:59:59.97#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.217.08:00:00.03#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.217.08:00:00.03#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.217.08:00:00.03#ibcon#enter wrdev, iclass 25, count 2 2006.217.08:00:00.03#ibcon#first serial, iclass 25, count 2 2006.217.08:00:00.03#ibcon#enter sib2, iclass 25, count 2 2006.217.08:00:00.03#ibcon#flushed, iclass 25, count 2 2006.217.08:00:00.03#ibcon#about to write, iclass 25, count 2 2006.217.08:00:00.03#ibcon#wrote, iclass 25, count 2 2006.217.08:00:00.03#ibcon#about to read 3, iclass 25, count 2 2006.217.08:00:00.05#ibcon#read 3, iclass 25, count 2 2006.217.08:00:00.05#ibcon#about to read 4, iclass 25, count 2 2006.217.08:00:00.05#ibcon#read 4, iclass 25, count 2 2006.217.08:00:00.05#ibcon#about to read 5, iclass 25, count 2 2006.217.08:00:00.05#ibcon#read 5, iclass 25, count 2 2006.217.08:00:00.05#ibcon#about to read 6, iclass 25, count 2 2006.217.08:00:00.05#ibcon#read 6, iclass 25, count 2 2006.217.08:00:00.05#ibcon#end of sib2, iclass 25, count 2 2006.217.08:00:00.05#ibcon#*mode == 0, iclass 25, count 2 2006.217.08:00:00.05#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.217.08:00:00.05#ibcon#[25=AT07-06\r\n] 2006.217.08:00:00.05#ibcon#*before write, iclass 25, count 2 2006.217.08:00:00.05#ibcon#enter sib2, iclass 25, count 2 2006.217.08:00:00.05#ibcon#flushed, iclass 25, count 2 2006.217.08:00:00.05#ibcon#about to write, iclass 25, count 2 2006.217.08:00:00.05#ibcon#wrote, iclass 25, count 2 2006.217.08:00:00.05#ibcon#about to read 3, iclass 25, count 2 2006.217.08:00:00.08#ibcon#read 3, iclass 25, count 2 2006.217.08:00:00.08#ibcon#about to read 4, iclass 25, count 2 2006.217.08:00:00.08#ibcon#read 4, iclass 25, count 2 2006.217.08:00:00.08#ibcon#about to read 5, iclass 25, count 2 2006.217.08:00:00.08#ibcon#read 5, iclass 25, count 2 2006.217.08:00:00.08#ibcon#about to read 6, iclass 25, count 2 2006.217.08:00:00.08#ibcon#read 6, iclass 25, count 2 2006.217.08:00:00.08#ibcon#end of sib2, iclass 25, count 2 2006.217.08:00:00.08#ibcon#*after write, iclass 25, count 2 2006.217.08:00:00.08#ibcon#*before return 0, iclass 25, count 2 2006.217.08:00:00.08#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.217.08:00:00.08#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.217.08:00:00.08#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.217.08:00:00.08#ibcon#ireg 7 cls_cnt 0 2006.217.08:00:00.08#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.217.08:00:00.20#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.217.08:00:00.20#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.217.08:00:00.20#ibcon#enter wrdev, iclass 25, count 0 2006.217.08:00:00.20#ibcon#first serial, iclass 25, count 0 2006.217.08:00:00.20#ibcon#enter sib2, iclass 25, count 0 2006.217.08:00:00.20#ibcon#flushed, iclass 25, count 0 2006.217.08:00:00.20#ibcon#about to write, iclass 25, count 0 2006.217.08:00:00.20#ibcon#wrote, iclass 25, count 0 2006.217.08:00:00.20#ibcon#about to read 3, iclass 25, count 0 2006.217.08:00:00.22#ibcon#read 3, iclass 25, count 0 2006.217.08:00:00.22#ibcon#about to read 4, iclass 25, count 0 2006.217.08:00:00.22#ibcon#read 4, iclass 25, count 0 2006.217.08:00:00.22#ibcon#about to read 5, iclass 25, count 0 2006.217.08:00:00.22#ibcon#read 5, iclass 25, count 0 2006.217.08:00:00.22#ibcon#about to read 6, iclass 25, count 0 2006.217.08:00:00.22#ibcon#read 6, iclass 25, count 0 2006.217.08:00:00.22#ibcon#end of sib2, iclass 25, count 0 2006.217.08:00:00.22#ibcon#*mode == 0, iclass 25, count 0 2006.217.08:00:00.22#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.217.08:00:00.22#ibcon#[25=USB\r\n] 2006.217.08:00:00.22#ibcon#*before write, iclass 25, count 0 2006.217.08:00:00.22#ibcon#enter sib2, iclass 25, count 0 2006.217.08:00:00.22#ibcon#flushed, iclass 25, count 0 2006.217.08:00:00.22#ibcon#about to write, iclass 25, count 0 2006.217.08:00:00.22#ibcon#wrote, iclass 25, count 0 2006.217.08:00:00.22#ibcon#about to read 3, iclass 25, count 0 2006.217.08:00:00.25#ibcon#read 3, iclass 25, count 0 2006.217.08:00:00.25#ibcon#about to read 4, iclass 25, count 0 2006.217.08:00:00.25#ibcon#read 4, iclass 25, count 0 2006.217.08:00:00.25#ibcon#about to read 5, iclass 25, count 0 2006.217.08:00:00.25#ibcon#read 5, iclass 25, count 0 2006.217.08:00:00.25#ibcon#about to read 6, iclass 25, count 0 2006.217.08:00:00.25#ibcon#read 6, iclass 25, count 0 2006.217.08:00:00.25#ibcon#end of sib2, iclass 25, count 0 2006.217.08:00:00.25#ibcon#*after write, iclass 25, count 0 2006.217.08:00:00.25#ibcon#*before return 0, iclass 25, count 0 2006.217.08:00:00.25#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.217.08:00:00.25#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.217.08:00:00.25#ibcon#about to clear, iclass 25 cls_cnt 0 2006.217.08:00:00.25#ibcon#cleared, iclass 25 cls_cnt 0 2006.217.08:00:00.25$vc4f8/valo=8,852.99 2006.217.08:00:00.25#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.217.08:00:00.25#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.217.08:00:00.25#ibcon#ireg 17 cls_cnt 0 2006.217.08:00:00.25#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.217.08:00:00.25#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.217.08:00:00.25#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.217.08:00:00.25#ibcon#enter wrdev, iclass 27, count 0 2006.217.08:00:00.25#ibcon#first serial, iclass 27, count 0 2006.217.08:00:00.25#ibcon#enter sib2, iclass 27, count 0 2006.217.08:00:00.25#ibcon#flushed, iclass 27, count 0 2006.217.08:00:00.25#ibcon#about to write, iclass 27, count 0 2006.217.08:00:00.25#ibcon#wrote, iclass 27, count 0 2006.217.08:00:00.25#ibcon#about to read 3, iclass 27, count 0 2006.217.08:00:00.27#ibcon#read 3, iclass 27, count 0 2006.217.08:00:00.27#ibcon#about to read 4, iclass 27, count 0 2006.217.08:00:00.27#ibcon#read 4, iclass 27, count 0 2006.217.08:00:00.27#ibcon#about to read 5, iclass 27, count 0 2006.217.08:00:00.27#ibcon#read 5, iclass 27, count 0 2006.217.08:00:00.27#ibcon#about to read 6, iclass 27, count 0 2006.217.08:00:00.27#ibcon#read 6, iclass 27, count 0 2006.217.08:00:00.27#ibcon#end of sib2, iclass 27, count 0 2006.217.08:00:00.27#ibcon#*mode == 0, iclass 27, count 0 2006.217.08:00:00.27#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.217.08:00:00.27#ibcon#[26=FRQ=08,852.99\r\n] 2006.217.08:00:00.27#ibcon#*before write, iclass 27, count 0 2006.217.08:00:00.27#ibcon#enter sib2, iclass 27, count 0 2006.217.08:00:00.27#ibcon#flushed, iclass 27, count 0 2006.217.08:00:00.27#ibcon#about to write, iclass 27, count 0 2006.217.08:00:00.27#ibcon#wrote, iclass 27, count 0 2006.217.08:00:00.27#ibcon#about to read 3, iclass 27, count 0 2006.217.08:00:00.31#ibcon#read 3, iclass 27, count 0 2006.217.08:00:00.31#ibcon#about to read 4, iclass 27, count 0 2006.217.08:00:00.31#ibcon#read 4, iclass 27, count 0 2006.217.08:00:00.31#ibcon#about to read 5, iclass 27, count 0 2006.217.08:00:00.31#ibcon#read 5, iclass 27, count 0 2006.217.08:00:00.31#ibcon#about to read 6, iclass 27, count 0 2006.217.08:00:00.31#ibcon#read 6, iclass 27, count 0 2006.217.08:00:00.31#ibcon#end of sib2, iclass 27, count 0 2006.217.08:00:00.31#ibcon#*after write, iclass 27, count 0 2006.217.08:00:00.31#ibcon#*before return 0, iclass 27, count 0 2006.217.08:00:00.31#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.217.08:00:00.31#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.217.08:00:00.31#ibcon#about to clear, iclass 27 cls_cnt 0 2006.217.08:00:00.31#ibcon#cleared, iclass 27 cls_cnt 0 2006.217.08:00:00.31$vc4f8/va=8,7 2006.217.08:00:00.31#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.217.08:00:00.31#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.217.08:00:00.31#ibcon#ireg 11 cls_cnt 2 2006.217.08:00:00.31#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.217.08:00:00.37#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.217.08:00:00.37#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.217.08:00:00.37#ibcon#enter wrdev, iclass 29, count 2 2006.217.08:00:00.37#ibcon#first serial, iclass 29, count 2 2006.217.08:00:00.37#ibcon#enter sib2, iclass 29, count 2 2006.217.08:00:00.37#ibcon#flushed, iclass 29, count 2 2006.217.08:00:00.37#ibcon#about to write, iclass 29, count 2 2006.217.08:00:00.37#ibcon#wrote, iclass 29, count 2 2006.217.08:00:00.37#ibcon#about to read 3, iclass 29, count 2 2006.217.08:00:00.39#ibcon#read 3, iclass 29, count 2 2006.217.08:00:00.39#ibcon#about to read 4, iclass 29, count 2 2006.217.08:00:00.39#ibcon#read 4, iclass 29, count 2 2006.217.08:00:00.39#ibcon#about to read 5, iclass 29, count 2 2006.217.08:00:00.39#ibcon#read 5, iclass 29, count 2 2006.217.08:00:00.39#ibcon#about to read 6, iclass 29, count 2 2006.217.08:00:00.39#ibcon#read 6, iclass 29, count 2 2006.217.08:00:00.39#ibcon#end of sib2, iclass 29, count 2 2006.217.08:00:00.39#ibcon#*mode == 0, iclass 29, count 2 2006.217.08:00:00.39#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.217.08:00:00.39#ibcon#[25=AT08-07\r\n] 2006.217.08:00:00.39#ibcon#*before write, iclass 29, count 2 2006.217.08:00:00.39#ibcon#enter sib2, iclass 29, count 2 2006.217.08:00:00.39#ibcon#flushed, iclass 29, count 2 2006.217.08:00:00.39#ibcon#about to write, iclass 29, count 2 2006.217.08:00:00.39#ibcon#wrote, iclass 29, count 2 2006.217.08:00:00.39#ibcon#about to read 3, iclass 29, count 2 2006.217.08:00:00.42#ibcon#read 3, iclass 29, count 2 2006.217.08:00:00.42#ibcon#about to read 4, iclass 29, count 2 2006.217.08:00:00.42#ibcon#read 4, iclass 29, count 2 2006.217.08:00:00.42#ibcon#about to read 5, iclass 29, count 2 2006.217.08:00:00.42#ibcon#read 5, iclass 29, count 2 2006.217.08:00:00.42#ibcon#about to read 6, iclass 29, count 2 2006.217.08:00:00.42#ibcon#read 6, iclass 29, count 2 2006.217.08:00:00.42#ibcon#end of sib2, iclass 29, count 2 2006.217.08:00:00.42#ibcon#*after write, iclass 29, count 2 2006.217.08:00:00.42#ibcon#*before return 0, iclass 29, count 2 2006.217.08:00:00.42#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.217.08:00:00.42#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.217.08:00:00.42#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.217.08:00:00.42#ibcon#ireg 7 cls_cnt 0 2006.217.08:00:00.42#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.217.08:00:00.54#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.217.08:00:00.54#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.217.08:00:00.54#ibcon#enter wrdev, iclass 29, count 0 2006.217.08:00:00.54#ibcon#first serial, iclass 29, count 0 2006.217.08:00:00.54#ibcon#enter sib2, iclass 29, count 0 2006.217.08:00:00.54#ibcon#flushed, iclass 29, count 0 2006.217.08:00:00.54#ibcon#about to write, iclass 29, count 0 2006.217.08:00:00.54#ibcon#wrote, iclass 29, count 0 2006.217.08:00:00.54#ibcon#about to read 3, iclass 29, count 0 2006.217.08:00:00.56#ibcon#read 3, iclass 29, count 0 2006.217.08:00:00.56#ibcon#about to read 4, iclass 29, count 0 2006.217.08:00:00.56#ibcon#read 4, iclass 29, count 0 2006.217.08:00:00.56#ibcon#about to read 5, iclass 29, count 0 2006.217.08:00:00.56#ibcon#read 5, iclass 29, count 0 2006.217.08:00:00.56#ibcon#about to read 6, iclass 29, count 0 2006.217.08:00:00.56#ibcon#read 6, iclass 29, count 0 2006.217.08:00:00.56#ibcon#end of sib2, iclass 29, count 0 2006.217.08:00:00.56#ibcon#*mode == 0, iclass 29, count 0 2006.217.08:00:00.56#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.217.08:00:00.56#ibcon#[25=USB\r\n] 2006.217.08:00:00.56#ibcon#*before write, iclass 29, count 0 2006.217.08:00:00.56#ibcon#enter sib2, iclass 29, count 0 2006.217.08:00:00.56#ibcon#flushed, iclass 29, count 0 2006.217.08:00:00.56#ibcon#about to write, iclass 29, count 0 2006.217.08:00:00.56#ibcon#wrote, iclass 29, count 0 2006.217.08:00:00.56#ibcon#about to read 3, iclass 29, count 0 2006.217.08:00:00.59#ibcon#read 3, iclass 29, count 0 2006.217.08:00:00.59#ibcon#about to read 4, iclass 29, count 0 2006.217.08:00:00.59#ibcon#read 4, iclass 29, count 0 2006.217.08:00:00.59#ibcon#about to read 5, iclass 29, count 0 2006.217.08:00:00.59#ibcon#read 5, iclass 29, count 0 2006.217.08:00:00.59#ibcon#about to read 6, iclass 29, count 0 2006.217.08:00:00.59#ibcon#read 6, iclass 29, count 0 2006.217.08:00:00.59#ibcon#end of sib2, iclass 29, count 0 2006.217.08:00:00.59#ibcon#*after write, iclass 29, count 0 2006.217.08:00:00.59#ibcon#*before return 0, iclass 29, count 0 2006.217.08:00:00.59#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.217.08:00:00.59#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.217.08:00:00.59#ibcon#about to clear, iclass 29 cls_cnt 0 2006.217.08:00:00.59#ibcon#cleared, iclass 29 cls_cnt 0 2006.217.08:00:00.59$vc4f8/vblo=1,632.99 2006.217.08:00:00.59#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.217.08:00:00.59#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.217.08:00:00.59#ibcon#ireg 17 cls_cnt 0 2006.217.08:00:00.59#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.217.08:00:00.59#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.217.08:00:00.59#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.217.08:00:00.59#ibcon#enter wrdev, iclass 31, count 0 2006.217.08:00:00.59#ibcon#first serial, iclass 31, count 0 2006.217.08:00:00.59#ibcon#enter sib2, iclass 31, count 0 2006.217.08:00:00.59#ibcon#flushed, iclass 31, count 0 2006.217.08:00:00.59#ibcon#about to write, iclass 31, count 0 2006.217.08:00:00.59#ibcon#wrote, iclass 31, count 0 2006.217.08:00:00.59#ibcon#about to read 3, iclass 31, count 0 2006.217.08:00:00.61#ibcon#read 3, iclass 31, count 0 2006.217.08:00:00.61#ibcon#about to read 4, iclass 31, count 0 2006.217.08:00:00.61#ibcon#read 4, iclass 31, count 0 2006.217.08:00:00.61#ibcon#about to read 5, iclass 31, count 0 2006.217.08:00:00.61#ibcon#read 5, iclass 31, count 0 2006.217.08:00:00.61#ibcon#about to read 6, iclass 31, count 0 2006.217.08:00:00.61#ibcon#read 6, iclass 31, count 0 2006.217.08:00:00.61#ibcon#end of sib2, iclass 31, count 0 2006.217.08:00:00.61#ibcon#*mode == 0, iclass 31, count 0 2006.217.08:00:00.61#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.217.08:00:00.61#ibcon#[28=FRQ=01,632.99\r\n] 2006.217.08:00:00.61#ibcon#*before write, iclass 31, count 0 2006.217.08:00:00.61#ibcon#enter sib2, iclass 31, count 0 2006.217.08:00:00.61#ibcon#flushed, iclass 31, count 0 2006.217.08:00:00.61#ibcon#about to write, iclass 31, count 0 2006.217.08:00:00.61#ibcon#wrote, iclass 31, count 0 2006.217.08:00:00.61#ibcon#about to read 3, iclass 31, count 0 2006.217.08:00:00.65#ibcon#read 3, iclass 31, count 0 2006.217.08:00:00.65#ibcon#about to read 4, iclass 31, count 0 2006.217.08:00:00.65#ibcon#read 4, iclass 31, count 0 2006.217.08:00:00.65#ibcon#about to read 5, iclass 31, count 0 2006.217.08:00:00.65#ibcon#read 5, iclass 31, count 0 2006.217.08:00:00.65#ibcon#about to read 6, iclass 31, count 0 2006.217.08:00:00.65#ibcon#read 6, iclass 31, count 0 2006.217.08:00:00.65#ibcon#end of sib2, iclass 31, count 0 2006.217.08:00:00.65#ibcon#*after write, iclass 31, count 0 2006.217.08:00:00.65#ibcon#*before return 0, iclass 31, count 0 2006.217.08:00:00.65#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.217.08:00:00.65#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.217.08:00:00.65#ibcon#about to clear, iclass 31 cls_cnt 0 2006.217.08:00:00.65#ibcon#cleared, iclass 31 cls_cnt 0 2006.217.08:00:00.65$vc4f8/vb=1,4 2006.217.08:00:00.65#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.217.08:00:00.65#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.217.08:00:00.65#ibcon#ireg 11 cls_cnt 2 2006.217.08:00:00.65#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.217.08:00:00.65#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.217.08:00:00.65#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.217.08:00:00.65#ibcon#enter wrdev, iclass 33, count 2 2006.217.08:00:00.65#ibcon#first serial, iclass 33, count 2 2006.217.08:00:00.65#ibcon#enter sib2, iclass 33, count 2 2006.217.08:00:00.65#ibcon#flushed, iclass 33, count 2 2006.217.08:00:00.65#ibcon#about to write, iclass 33, count 2 2006.217.08:00:00.65#ibcon#wrote, iclass 33, count 2 2006.217.08:00:00.65#ibcon#about to read 3, iclass 33, count 2 2006.217.08:00:00.67#ibcon#read 3, iclass 33, count 2 2006.217.08:00:00.67#ibcon#about to read 4, iclass 33, count 2 2006.217.08:00:00.67#ibcon#read 4, iclass 33, count 2 2006.217.08:00:00.67#ibcon#about to read 5, iclass 33, count 2 2006.217.08:00:00.67#ibcon#read 5, iclass 33, count 2 2006.217.08:00:00.67#ibcon#about to read 6, iclass 33, count 2 2006.217.08:00:00.67#ibcon#read 6, iclass 33, count 2 2006.217.08:00:00.67#ibcon#end of sib2, iclass 33, count 2 2006.217.08:00:00.67#ibcon#*mode == 0, iclass 33, count 2 2006.217.08:00:00.67#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.217.08:00:00.67#ibcon#[27=AT01-04\r\n] 2006.217.08:00:00.67#ibcon#*before write, iclass 33, count 2 2006.217.08:00:00.67#ibcon#enter sib2, iclass 33, count 2 2006.217.08:00:00.67#ibcon#flushed, iclass 33, count 2 2006.217.08:00:00.67#ibcon#about to write, iclass 33, count 2 2006.217.08:00:00.67#ibcon#wrote, iclass 33, count 2 2006.217.08:00:00.67#ibcon#about to read 3, iclass 33, count 2 2006.217.08:00:00.70#ibcon#read 3, iclass 33, count 2 2006.217.08:00:00.70#ibcon#about to read 4, iclass 33, count 2 2006.217.08:00:00.70#ibcon#read 4, iclass 33, count 2 2006.217.08:00:00.70#ibcon#about to read 5, iclass 33, count 2 2006.217.08:00:00.70#ibcon#read 5, iclass 33, count 2 2006.217.08:00:00.70#ibcon#about to read 6, iclass 33, count 2 2006.217.08:00:00.70#ibcon#read 6, iclass 33, count 2 2006.217.08:00:00.70#ibcon#end of sib2, iclass 33, count 2 2006.217.08:00:00.70#ibcon#*after write, iclass 33, count 2 2006.217.08:00:00.70#ibcon#*before return 0, iclass 33, count 2 2006.217.08:00:00.70#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.217.08:00:00.70#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.217.08:00:00.70#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.217.08:00:00.70#ibcon#ireg 7 cls_cnt 0 2006.217.08:00:00.70#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.217.08:00:00.82#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.217.08:00:00.82#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.217.08:00:00.82#ibcon#enter wrdev, iclass 33, count 0 2006.217.08:00:00.82#ibcon#first serial, iclass 33, count 0 2006.217.08:00:00.82#ibcon#enter sib2, iclass 33, count 0 2006.217.08:00:00.82#ibcon#flushed, iclass 33, count 0 2006.217.08:00:00.82#ibcon#about to write, iclass 33, count 0 2006.217.08:00:00.82#ibcon#wrote, iclass 33, count 0 2006.217.08:00:00.82#ibcon#about to read 3, iclass 33, count 0 2006.217.08:00:00.84#ibcon#read 3, iclass 33, count 0 2006.217.08:00:00.84#ibcon#about to read 4, iclass 33, count 0 2006.217.08:00:00.84#ibcon#read 4, iclass 33, count 0 2006.217.08:00:00.84#ibcon#about to read 5, iclass 33, count 0 2006.217.08:00:00.84#ibcon#read 5, iclass 33, count 0 2006.217.08:00:00.84#ibcon#about to read 6, iclass 33, count 0 2006.217.08:00:00.84#ibcon#read 6, iclass 33, count 0 2006.217.08:00:00.84#ibcon#end of sib2, iclass 33, count 0 2006.217.08:00:00.84#ibcon#*mode == 0, iclass 33, count 0 2006.217.08:00:00.84#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.217.08:00:00.84#ibcon#[27=USB\r\n] 2006.217.08:00:00.84#ibcon#*before write, iclass 33, count 0 2006.217.08:00:00.84#ibcon#enter sib2, iclass 33, count 0 2006.217.08:00:00.84#ibcon#flushed, iclass 33, count 0 2006.217.08:00:00.84#ibcon#about to write, iclass 33, count 0 2006.217.08:00:00.84#ibcon#wrote, iclass 33, count 0 2006.217.08:00:00.84#ibcon#about to read 3, iclass 33, count 0 2006.217.08:00:00.87#ibcon#read 3, iclass 33, count 0 2006.217.08:00:00.87#ibcon#about to read 4, iclass 33, count 0 2006.217.08:00:00.87#ibcon#read 4, iclass 33, count 0 2006.217.08:00:00.87#ibcon#about to read 5, iclass 33, count 0 2006.217.08:00:00.87#ibcon#read 5, iclass 33, count 0 2006.217.08:00:00.87#ibcon#about to read 6, iclass 33, count 0 2006.217.08:00:00.87#ibcon#read 6, iclass 33, count 0 2006.217.08:00:00.87#ibcon#end of sib2, iclass 33, count 0 2006.217.08:00:00.87#ibcon#*after write, iclass 33, count 0 2006.217.08:00:00.87#ibcon#*before return 0, iclass 33, count 0 2006.217.08:00:00.87#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.217.08:00:00.87#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.217.08:00:00.87#ibcon#about to clear, iclass 33 cls_cnt 0 2006.217.08:00:00.87#ibcon#cleared, iclass 33 cls_cnt 0 2006.217.08:00:00.87$vc4f8/vblo=2,640.99 2006.217.08:00:00.87#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.217.08:00:00.87#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.217.08:00:00.87#ibcon#ireg 17 cls_cnt 0 2006.217.08:00:00.87#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.217.08:00:00.87#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.217.08:00:00.87#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.217.08:00:00.87#ibcon#enter wrdev, iclass 35, count 0 2006.217.08:00:00.87#ibcon#first serial, iclass 35, count 0 2006.217.08:00:00.87#ibcon#enter sib2, iclass 35, count 0 2006.217.08:00:00.87#ibcon#flushed, iclass 35, count 0 2006.217.08:00:00.87#ibcon#about to write, iclass 35, count 0 2006.217.08:00:00.87#ibcon#wrote, iclass 35, count 0 2006.217.08:00:00.87#ibcon#about to read 3, iclass 35, count 0 2006.217.08:00:00.89#ibcon#read 3, iclass 35, count 0 2006.217.08:00:00.89#ibcon#about to read 4, iclass 35, count 0 2006.217.08:00:00.89#ibcon#read 4, iclass 35, count 0 2006.217.08:00:00.89#ibcon#about to read 5, iclass 35, count 0 2006.217.08:00:00.89#ibcon#read 5, iclass 35, count 0 2006.217.08:00:00.89#ibcon#about to read 6, iclass 35, count 0 2006.217.08:00:00.89#ibcon#read 6, iclass 35, count 0 2006.217.08:00:00.89#ibcon#end of sib2, iclass 35, count 0 2006.217.08:00:00.89#ibcon#*mode == 0, iclass 35, count 0 2006.217.08:00:00.89#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.217.08:00:00.89#ibcon#[28=FRQ=02,640.99\r\n] 2006.217.08:00:00.89#ibcon#*before write, iclass 35, count 0 2006.217.08:00:00.89#ibcon#enter sib2, iclass 35, count 0 2006.217.08:00:00.89#ibcon#flushed, iclass 35, count 0 2006.217.08:00:00.89#ibcon#about to write, iclass 35, count 0 2006.217.08:00:00.89#ibcon#wrote, iclass 35, count 0 2006.217.08:00:00.89#ibcon#about to read 3, iclass 35, count 0 2006.217.08:00:00.93#ibcon#read 3, iclass 35, count 0 2006.217.08:00:00.93#ibcon#about to read 4, iclass 35, count 0 2006.217.08:00:00.93#ibcon#read 4, iclass 35, count 0 2006.217.08:00:00.93#ibcon#about to read 5, iclass 35, count 0 2006.217.08:00:00.93#ibcon#read 5, iclass 35, count 0 2006.217.08:00:00.93#ibcon#about to read 6, iclass 35, count 0 2006.217.08:00:00.93#ibcon#read 6, iclass 35, count 0 2006.217.08:00:00.93#ibcon#end of sib2, iclass 35, count 0 2006.217.08:00:00.93#ibcon#*after write, iclass 35, count 0 2006.217.08:00:00.93#ibcon#*before return 0, iclass 35, count 0 2006.217.08:00:00.93#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.217.08:00:00.93#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.217.08:00:00.93#ibcon#about to clear, iclass 35 cls_cnt 0 2006.217.08:00:00.93#ibcon#cleared, iclass 35 cls_cnt 0 2006.217.08:00:00.93$vc4f8/vb=2,4 2006.217.08:00:00.93#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.217.08:00:00.93#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.217.08:00:00.93#ibcon#ireg 11 cls_cnt 2 2006.217.08:00:00.93#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.217.08:00:00.99#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.217.08:00:00.99#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.217.08:00:00.99#ibcon#enter wrdev, iclass 37, count 2 2006.217.08:00:00.99#ibcon#first serial, iclass 37, count 2 2006.217.08:00:00.99#ibcon#enter sib2, iclass 37, count 2 2006.217.08:00:00.99#ibcon#flushed, iclass 37, count 2 2006.217.08:00:00.99#ibcon#about to write, iclass 37, count 2 2006.217.08:00:00.99#ibcon#wrote, iclass 37, count 2 2006.217.08:00:00.99#ibcon#about to read 3, iclass 37, count 2 2006.217.08:00:01.01#ibcon#read 3, iclass 37, count 2 2006.217.08:00:01.01#ibcon#about to read 4, iclass 37, count 2 2006.217.08:00:01.01#ibcon#read 4, iclass 37, count 2 2006.217.08:00:01.01#ibcon#about to read 5, iclass 37, count 2 2006.217.08:00:01.01#ibcon#read 5, iclass 37, count 2 2006.217.08:00:01.01#ibcon#about to read 6, iclass 37, count 2 2006.217.08:00:01.01#ibcon#read 6, iclass 37, count 2 2006.217.08:00:01.01#ibcon#end of sib2, iclass 37, count 2 2006.217.08:00:01.01#ibcon#*mode == 0, iclass 37, count 2 2006.217.08:00:01.01#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.217.08:00:01.01#ibcon#[27=AT02-04\r\n] 2006.217.08:00:01.01#ibcon#*before write, iclass 37, count 2 2006.217.08:00:01.01#ibcon#enter sib2, iclass 37, count 2 2006.217.08:00:01.01#ibcon#flushed, iclass 37, count 2 2006.217.08:00:01.01#ibcon#about to write, iclass 37, count 2 2006.217.08:00:01.01#ibcon#wrote, iclass 37, count 2 2006.217.08:00:01.01#ibcon#about to read 3, iclass 37, count 2 2006.217.08:00:01.04#ibcon#read 3, iclass 37, count 2 2006.217.08:00:01.04#ibcon#about to read 4, iclass 37, count 2 2006.217.08:00:01.04#ibcon#read 4, iclass 37, count 2 2006.217.08:00:01.04#ibcon#about to read 5, iclass 37, count 2 2006.217.08:00:01.04#ibcon#read 5, iclass 37, count 2 2006.217.08:00:01.04#ibcon#about to read 6, iclass 37, count 2 2006.217.08:00:01.04#ibcon#read 6, iclass 37, count 2 2006.217.08:00:01.04#ibcon#end of sib2, iclass 37, count 2 2006.217.08:00:01.04#ibcon#*after write, iclass 37, count 2 2006.217.08:00:01.04#ibcon#*before return 0, iclass 37, count 2 2006.217.08:00:01.04#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.217.08:00:01.04#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.217.08:00:01.04#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.217.08:00:01.04#ibcon#ireg 7 cls_cnt 0 2006.217.08:00:01.04#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.217.08:00:01.16#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.217.08:00:01.16#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.217.08:00:01.16#ibcon#enter wrdev, iclass 37, count 0 2006.217.08:00:01.16#ibcon#first serial, iclass 37, count 0 2006.217.08:00:01.16#ibcon#enter sib2, iclass 37, count 0 2006.217.08:00:01.16#ibcon#flushed, iclass 37, count 0 2006.217.08:00:01.16#ibcon#about to write, iclass 37, count 0 2006.217.08:00:01.16#ibcon#wrote, iclass 37, count 0 2006.217.08:00:01.16#ibcon#about to read 3, iclass 37, count 0 2006.217.08:00:01.18#ibcon#read 3, iclass 37, count 0 2006.217.08:00:01.18#ibcon#about to read 4, iclass 37, count 0 2006.217.08:00:01.18#ibcon#read 4, iclass 37, count 0 2006.217.08:00:01.18#ibcon#about to read 5, iclass 37, count 0 2006.217.08:00:01.18#ibcon#read 5, iclass 37, count 0 2006.217.08:00:01.18#ibcon#about to read 6, iclass 37, count 0 2006.217.08:00:01.18#ibcon#read 6, iclass 37, count 0 2006.217.08:00:01.18#ibcon#end of sib2, iclass 37, count 0 2006.217.08:00:01.18#ibcon#*mode == 0, iclass 37, count 0 2006.217.08:00:01.18#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.217.08:00:01.18#ibcon#[27=USB\r\n] 2006.217.08:00:01.18#ibcon#*before write, iclass 37, count 0 2006.217.08:00:01.18#ibcon#enter sib2, iclass 37, count 0 2006.217.08:00:01.18#ibcon#flushed, iclass 37, count 0 2006.217.08:00:01.18#ibcon#about to write, iclass 37, count 0 2006.217.08:00:01.18#ibcon#wrote, iclass 37, count 0 2006.217.08:00:01.18#ibcon#about to read 3, iclass 37, count 0 2006.217.08:00:01.21#ibcon#read 3, iclass 37, count 0 2006.217.08:00:01.21#ibcon#about to read 4, iclass 37, count 0 2006.217.08:00:01.21#ibcon#read 4, iclass 37, count 0 2006.217.08:00:01.21#ibcon#about to read 5, iclass 37, count 0 2006.217.08:00:01.21#ibcon#read 5, iclass 37, count 0 2006.217.08:00:01.21#ibcon#about to read 6, iclass 37, count 0 2006.217.08:00:01.21#ibcon#read 6, iclass 37, count 0 2006.217.08:00:01.21#ibcon#end of sib2, iclass 37, count 0 2006.217.08:00:01.21#ibcon#*after write, iclass 37, count 0 2006.217.08:00:01.21#ibcon#*before return 0, iclass 37, count 0 2006.217.08:00:01.21#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.217.08:00:01.21#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.217.08:00:01.21#ibcon#about to clear, iclass 37 cls_cnt 0 2006.217.08:00:01.21#ibcon#cleared, iclass 37 cls_cnt 0 2006.217.08:00:01.21$vc4f8/vblo=3,656.99 2006.217.08:00:01.21#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.217.08:00:01.21#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.217.08:00:01.21#ibcon#ireg 17 cls_cnt 0 2006.217.08:00:01.21#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.217.08:00:01.21#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.217.08:00:01.21#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.217.08:00:01.21#ibcon#enter wrdev, iclass 39, count 0 2006.217.08:00:01.21#ibcon#first serial, iclass 39, count 0 2006.217.08:00:01.21#ibcon#enter sib2, iclass 39, count 0 2006.217.08:00:01.21#ibcon#flushed, iclass 39, count 0 2006.217.08:00:01.21#ibcon#about to write, iclass 39, count 0 2006.217.08:00:01.21#ibcon#wrote, iclass 39, count 0 2006.217.08:00:01.21#ibcon#about to read 3, iclass 39, count 0 2006.217.08:00:01.23#ibcon#read 3, iclass 39, count 0 2006.217.08:00:01.23#ibcon#about to read 4, iclass 39, count 0 2006.217.08:00:01.23#ibcon#read 4, iclass 39, count 0 2006.217.08:00:01.23#ibcon#about to read 5, iclass 39, count 0 2006.217.08:00:01.23#ibcon#read 5, iclass 39, count 0 2006.217.08:00:01.23#ibcon#about to read 6, iclass 39, count 0 2006.217.08:00:01.23#ibcon#read 6, iclass 39, count 0 2006.217.08:00:01.23#ibcon#end of sib2, iclass 39, count 0 2006.217.08:00:01.23#ibcon#*mode == 0, iclass 39, count 0 2006.217.08:00:01.23#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.217.08:00:01.23#ibcon#[28=FRQ=03,656.99\r\n] 2006.217.08:00:01.23#ibcon#*before write, iclass 39, count 0 2006.217.08:00:01.23#ibcon#enter sib2, iclass 39, count 0 2006.217.08:00:01.23#ibcon#flushed, iclass 39, count 0 2006.217.08:00:01.23#ibcon#about to write, iclass 39, count 0 2006.217.08:00:01.23#ibcon#wrote, iclass 39, count 0 2006.217.08:00:01.23#ibcon#about to read 3, iclass 39, count 0 2006.217.08:00:01.27#ibcon#read 3, iclass 39, count 0 2006.217.08:00:01.27#ibcon#about to read 4, iclass 39, count 0 2006.217.08:00:01.27#ibcon#read 4, iclass 39, count 0 2006.217.08:00:01.27#ibcon#about to read 5, iclass 39, count 0 2006.217.08:00:01.27#ibcon#read 5, iclass 39, count 0 2006.217.08:00:01.27#ibcon#about to read 6, iclass 39, count 0 2006.217.08:00:01.27#ibcon#read 6, iclass 39, count 0 2006.217.08:00:01.27#ibcon#end of sib2, iclass 39, count 0 2006.217.08:00:01.27#ibcon#*after write, iclass 39, count 0 2006.217.08:00:01.27#ibcon#*before return 0, iclass 39, count 0 2006.217.08:00:01.27#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.217.08:00:01.27#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.217.08:00:01.27#ibcon#about to clear, iclass 39 cls_cnt 0 2006.217.08:00:01.27#ibcon#cleared, iclass 39 cls_cnt 0 2006.217.08:00:01.27$vc4f8/vb=3,4 2006.217.08:00:01.27#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.217.08:00:01.27#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.217.08:00:01.27#ibcon#ireg 11 cls_cnt 2 2006.217.08:00:01.27#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.217.08:00:01.33#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.217.08:00:01.33#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.217.08:00:01.33#ibcon#enter wrdev, iclass 3, count 2 2006.217.08:00:01.33#ibcon#first serial, iclass 3, count 2 2006.217.08:00:01.33#ibcon#enter sib2, iclass 3, count 2 2006.217.08:00:01.33#ibcon#flushed, iclass 3, count 2 2006.217.08:00:01.33#ibcon#about to write, iclass 3, count 2 2006.217.08:00:01.33#ibcon#wrote, iclass 3, count 2 2006.217.08:00:01.33#ibcon#about to read 3, iclass 3, count 2 2006.217.08:00:01.35#ibcon#read 3, iclass 3, count 2 2006.217.08:00:01.35#ibcon#about to read 4, iclass 3, count 2 2006.217.08:00:01.35#ibcon#read 4, iclass 3, count 2 2006.217.08:00:01.35#ibcon#about to read 5, iclass 3, count 2 2006.217.08:00:01.35#ibcon#read 5, iclass 3, count 2 2006.217.08:00:01.35#ibcon#about to read 6, iclass 3, count 2 2006.217.08:00:01.35#ibcon#read 6, iclass 3, count 2 2006.217.08:00:01.35#ibcon#end of sib2, iclass 3, count 2 2006.217.08:00:01.35#ibcon#*mode == 0, iclass 3, count 2 2006.217.08:00:01.35#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.217.08:00:01.35#ibcon#[27=AT03-04\r\n] 2006.217.08:00:01.35#ibcon#*before write, iclass 3, count 2 2006.217.08:00:01.35#ibcon#enter sib2, iclass 3, count 2 2006.217.08:00:01.35#ibcon#flushed, iclass 3, count 2 2006.217.08:00:01.35#ibcon#about to write, iclass 3, count 2 2006.217.08:00:01.35#ibcon#wrote, iclass 3, count 2 2006.217.08:00:01.35#ibcon#about to read 3, iclass 3, count 2 2006.217.08:00:01.38#ibcon#read 3, iclass 3, count 2 2006.217.08:00:01.38#ibcon#about to read 4, iclass 3, count 2 2006.217.08:00:01.38#ibcon#read 4, iclass 3, count 2 2006.217.08:00:01.38#ibcon#about to read 5, iclass 3, count 2 2006.217.08:00:01.38#ibcon#read 5, iclass 3, count 2 2006.217.08:00:01.38#ibcon#about to read 6, iclass 3, count 2 2006.217.08:00:01.38#ibcon#read 6, iclass 3, count 2 2006.217.08:00:01.38#ibcon#end of sib2, iclass 3, count 2 2006.217.08:00:01.38#ibcon#*after write, iclass 3, count 2 2006.217.08:00:01.38#ibcon#*before return 0, iclass 3, count 2 2006.217.08:00:01.38#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.217.08:00:01.38#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.217.08:00:01.38#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.217.08:00:01.38#ibcon#ireg 7 cls_cnt 0 2006.217.08:00:01.38#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.217.08:00:01.50#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.217.08:00:01.50#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.217.08:00:01.50#ibcon#enter wrdev, iclass 3, count 0 2006.217.08:00:01.50#ibcon#first serial, iclass 3, count 0 2006.217.08:00:01.50#ibcon#enter sib2, iclass 3, count 0 2006.217.08:00:01.50#ibcon#flushed, iclass 3, count 0 2006.217.08:00:01.50#ibcon#about to write, iclass 3, count 0 2006.217.08:00:01.50#ibcon#wrote, iclass 3, count 0 2006.217.08:00:01.50#ibcon#about to read 3, iclass 3, count 0 2006.217.08:00:01.52#ibcon#read 3, iclass 3, count 0 2006.217.08:00:01.52#ibcon#about to read 4, iclass 3, count 0 2006.217.08:00:01.52#ibcon#read 4, iclass 3, count 0 2006.217.08:00:01.52#ibcon#about to read 5, iclass 3, count 0 2006.217.08:00:01.52#ibcon#read 5, iclass 3, count 0 2006.217.08:00:01.52#ibcon#about to read 6, iclass 3, count 0 2006.217.08:00:01.52#ibcon#read 6, iclass 3, count 0 2006.217.08:00:01.52#ibcon#end of sib2, iclass 3, count 0 2006.217.08:00:01.52#ibcon#*mode == 0, iclass 3, count 0 2006.217.08:00:01.52#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.217.08:00:01.52#ibcon#[27=USB\r\n] 2006.217.08:00:01.52#ibcon#*before write, iclass 3, count 0 2006.217.08:00:01.52#ibcon#enter sib2, iclass 3, count 0 2006.217.08:00:01.52#ibcon#flushed, iclass 3, count 0 2006.217.08:00:01.52#ibcon#about to write, iclass 3, count 0 2006.217.08:00:01.52#ibcon#wrote, iclass 3, count 0 2006.217.08:00:01.52#ibcon#about to read 3, iclass 3, count 0 2006.217.08:00:01.55#ibcon#read 3, iclass 3, count 0 2006.217.08:00:01.55#ibcon#about to read 4, iclass 3, count 0 2006.217.08:00:01.55#ibcon#read 4, iclass 3, count 0 2006.217.08:00:01.55#ibcon#about to read 5, iclass 3, count 0 2006.217.08:00:01.55#ibcon#read 5, iclass 3, count 0 2006.217.08:00:01.55#ibcon#about to read 6, iclass 3, count 0 2006.217.08:00:01.55#ibcon#read 6, iclass 3, count 0 2006.217.08:00:01.55#ibcon#end of sib2, iclass 3, count 0 2006.217.08:00:01.55#ibcon#*after write, iclass 3, count 0 2006.217.08:00:01.55#ibcon#*before return 0, iclass 3, count 0 2006.217.08:00:01.55#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.217.08:00:01.55#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.217.08:00:01.55#ibcon#about to clear, iclass 3 cls_cnt 0 2006.217.08:00:01.55#ibcon#cleared, iclass 3 cls_cnt 0 2006.217.08:00:01.55$vc4f8/vblo=4,712.99 2006.217.08:00:01.55#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.217.08:00:01.55#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.217.08:00:01.55#ibcon#ireg 17 cls_cnt 0 2006.217.08:00:01.55#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.217.08:00:01.55#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.217.08:00:01.55#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.217.08:00:01.55#ibcon#enter wrdev, iclass 5, count 0 2006.217.08:00:01.55#ibcon#first serial, iclass 5, count 0 2006.217.08:00:01.55#ibcon#enter sib2, iclass 5, count 0 2006.217.08:00:01.55#ibcon#flushed, iclass 5, count 0 2006.217.08:00:01.55#ibcon#about to write, iclass 5, count 0 2006.217.08:00:01.55#ibcon#wrote, iclass 5, count 0 2006.217.08:00:01.55#ibcon#about to read 3, iclass 5, count 0 2006.217.08:00:01.57#ibcon#read 3, iclass 5, count 0 2006.217.08:00:01.57#ibcon#about to read 4, iclass 5, count 0 2006.217.08:00:01.57#ibcon#read 4, iclass 5, count 0 2006.217.08:00:01.57#ibcon#about to read 5, iclass 5, count 0 2006.217.08:00:01.57#ibcon#read 5, iclass 5, count 0 2006.217.08:00:01.57#ibcon#about to read 6, iclass 5, count 0 2006.217.08:00:01.57#ibcon#read 6, iclass 5, count 0 2006.217.08:00:01.57#ibcon#end of sib2, iclass 5, count 0 2006.217.08:00:01.57#ibcon#*mode == 0, iclass 5, count 0 2006.217.08:00:01.57#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.217.08:00:01.57#ibcon#[28=FRQ=04,712.99\r\n] 2006.217.08:00:01.57#ibcon#*before write, iclass 5, count 0 2006.217.08:00:01.57#ibcon#enter sib2, iclass 5, count 0 2006.217.08:00:01.57#ibcon#flushed, iclass 5, count 0 2006.217.08:00:01.57#ibcon#about to write, iclass 5, count 0 2006.217.08:00:01.57#ibcon#wrote, iclass 5, count 0 2006.217.08:00:01.57#ibcon#about to read 3, iclass 5, count 0 2006.217.08:00:01.61#ibcon#read 3, iclass 5, count 0 2006.217.08:00:01.61#ibcon#about to read 4, iclass 5, count 0 2006.217.08:00:01.61#ibcon#read 4, iclass 5, count 0 2006.217.08:00:01.61#ibcon#about to read 5, iclass 5, count 0 2006.217.08:00:01.61#ibcon#read 5, iclass 5, count 0 2006.217.08:00:01.61#ibcon#about to read 6, iclass 5, count 0 2006.217.08:00:01.61#ibcon#read 6, iclass 5, count 0 2006.217.08:00:01.61#ibcon#end of sib2, iclass 5, count 0 2006.217.08:00:01.61#ibcon#*after write, iclass 5, count 0 2006.217.08:00:01.61#ibcon#*before return 0, iclass 5, count 0 2006.217.08:00:01.61#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.217.08:00:01.61#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.217.08:00:01.61#ibcon#about to clear, iclass 5 cls_cnt 0 2006.217.08:00:01.61#ibcon#cleared, iclass 5 cls_cnt 0 2006.217.08:00:01.61$vc4f8/vb=4,4 2006.217.08:00:01.61#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.217.08:00:01.61#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.217.08:00:01.61#ibcon#ireg 11 cls_cnt 2 2006.217.08:00:01.61#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.217.08:00:01.65#abcon#<5=/05 4.1 7.7 30.98 641008.7\r\n> 2006.217.08:00:01.67#abcon#{5=INTERFACE CLEAR} 2006.217.08:00:01.67#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.217.08:00:01.67#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.217.08:00:01.67#ibcon#enter wrdev, iclass 10, count 2 2006.217.08:00:01.67#ibcon#first serial, iclass 10, count 2 2006.217.08:00:01.67#ibcon#enter sib2, iclass 10, count 2 2006.217.08:00:01.67#ibcon#flushed, iclass 10, count 2 2006.217.08:00:01.67#ibcon#about to write, iclass 10, count 2 2006.217.08:00:01.67#ibcon#wrote, iclass 10, count 2 2006.217.08:00:01.67#ibcon#about to read 3, iclass 10, count 2 2006.217.08:00:01.69#ibcon#read 3, iclass 10, count 2 2006.217.08:00:01.69#ibcon#about to read 4, iclass 10, count 2 2006.217.08:00:01.69#ibcon#read 4, iclass 10, count 2 2006.217.08:00:01.69#ibcon#about to read 5, iclass 10, count 2 2006.217.08:00:01.69#ibcon#read 5, iclass 10, count 2 2006.217.08:00:01.69#ibcon#about to read 6, iclass 10, count 2 2006.217.08:00:01.69#ibcon#read 6, iclass 10, count 2 2006.217.08:00:01.69#ibcon#end of sib2, iclass 10, count 2 2006.217.08:00:01.69#ibcon#*mode == 0, iclass 10, count 2 2006.217.08:00:01.69#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.217.08:00:01.69#ibcon#[27=AT04-04\r\n] 2006.217.08:00:01.69#ibcon#*before write, iclass 10, count 2 2006.217.08:00:01.69#ibcon#enter sib2, iclass 10, count 2 2006.217.08:00:01.69#ibcon#flushed, iclass 10, count 2 2006.217.08:00:01.69#ibcon#about to write, iclass 10, count 2 2006.217.08:00:01.69#ibcon#wrote, iclass 10, count 2 2006.217.08:00:01.69#ibcon#about to read 3, iclass 10, count 2 2006.217.08:00:01.72#ibcon#read 3, iclass 10, count 2 2006.217.08:00:01.72#ibcon#about to read 4, iclass 10, count 2 2006.217.08:00:01.72#ibcon#read 4, iclass 10, count 2 2006.217.08:00:01.72#ibcon#about to read 5, iclass 10, count 2 2006.217.08:00:01.72#ibcon#read 5, iclass 10, count 2 2006.217.08:00:01.72#ibcon#about to read 6, iclass 10, count 2 2006.217.08:00:01.72#ibcon#read 6, iclass 10, count 2 2006.217.08:00:01.72#ibcon#end of sib2, iclass 10, count 2 2006.217.08:00:01.72#ibcon#*after write, iclass 10, count 2 2006.217.08:00:01.72#ibcon#*before return 0, iclass 10, count 2 2006.217.08:00:01.72#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.217.08:00:01.72#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.217.08:00:01.72#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.217.08:00:01.72#ibcon#ireg 7 cls_cnt 0 2006.217.08:00:01.72#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.217.08:00:01.73#abcon#[5=S1D000X0/0*\r\n] 2006.217.08:00:01.84#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.217.08:00:01.84#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.217.08:00:01.84#ibcon#enter wrdev, iclass 10, count 0 2006.217.08:00:01.84#ibcon#first serial, iclass 10, count 0 2006.217.08:00:01.84#ibcon#enter sib2, iclass 10, count 0 2006.217.08:00:01.84#ibcon#flushed, iclass 10, count 0 2006.217.08:00:01.84#ibcon#about to write, iclass 10, count 0 2006.217.08:00:01.84#ibcon#wrote, iclass 10, count 0 2006.217.08:00:01.84#ibcon#about to read 3, iclass 10, count 0 2006.217.08:00:01.86#ibcon#read 3, iclass 10, count 0 2006.217.08:00:01.86#ibcon#about to read 4, iclass 10, count 0 2006.217.08:00:01.86#ibcon#read 4, iclass 10, count 0 2006.217.08:00:01.86#ibcon#about to read 5, iclass 10, count 0 2006.217.08:00:01.86#ibcon#read 5, iclass 10, count 0 2006.217.08:00:01.86#ibcon#about to read 6, iclass 10, count 0 2006.217.08:00:01.86#ibcon#read 6, iclass 10, count 0 2006.217.08:00:01.86#ibcon#end of sib2, iclass 10, count 0 2006.217.08:00:01.86#ibcon#*mode == 0, iclass 10, count 0 2006.217.08:00:01.86#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.217.08:00:01.86#ibcon#[27=USB\r\n] 2006.217.08:00:01.86#ibcon#*before write, iclass 10, count 0 2006.217.08:00:01.86#ibcon#enter sib2, iclass 10, count 0 2006.217.08:00:01.86#ibcon#flushed, iclass 10, count 0 2006.217.08:00:01.86#ibcon#about to write, iclass 10, count 0 2006.217.08:00:01.86#ibcon#wrote, iclass 10, count 0 2006.217.08:00:01.86#ibcon#about to read 3, iclass 10, count 0 2006.217.08:00:01.89#ibcon#read 3, iclass 10, count 0 2006.217.08:00:01.89#ibcon#about to read 4, iclass 10, count 0 2006.217.08:00:01.89#ibcon#read 4, iclass 10, count 0 2006.217.08:00:01.89#ibcon#about to read 5, iclass 10, count 0 2006.217.08:00:01.89#ibcon#read 5, iclass 10, count 0 2006.217.08:00:01.89#ibcon#about to read 6, iclass 10, count 0 2006.217.08:00:01.89#ibcon#read 6, iclass 10, count 0 2006.217.08:00:01.89#ibcon#end of sib2, iclass 10, count 0 2006.217.08:00:01.89#ibcon#*after write, iclass 10, count 0 2006.217.08:00:01.89#ibcon#*before return 0, iclass 10, count 0 2006.217.08:00:01.89#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.217.08:00:01.89#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.217.08:00:01.89#ibcon#about to clear, iclass 10 cls_cnt 0 2006.217.08:00:01.89#ibcon#cleared, iclass 10 cls_cnt 0 2006.217.08:00:01.89$vc4f8/vblo=5,744.99 2006.217.08:00:01.89#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.217.08:00:01.89#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.217.08:00:01.89#ibcon#ireg 17 cls_cnt 0 2006.217.08:00:01.89#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.217.08:00:01.89#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.217.08:00:01.89#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.217.08:00:01.89#ibcon#enter wrdev, iclass 15, count 0 2006.217.08:00:01.89#ibcon#first serial, iclass 15, count 0 2006.217.08:00:01.89#ibcon#enter sib2, iclass 15, count 0 2006.217.08:00:01.89#ibcon#flushed, iclass 15, count 0 2006.217.08:00:01.89#ibcon#about to write, iclass 15, count 0 2006.217.08:00:01.89#ibcon#wrote, iclass 15, count 0 2006.217.08:00:01.89#ibcon#about to read 3, iclass 15, count 0 2006.217.08:00:01.91#ibcon#read 3, iclass 15, count 0 2006.217.08:00:01.91#ibcon#about to read 4, iclass 15, count 0 2006.217.08:00:01.91#ibcon#read 4, iclass 15, count 0 2006.217.08:00:01.91#ibcon#about to read 5, iclass 15, count 0 2006.217.08:00:01.91#ibcon#read 5, iclass 15, count 0 2006.217.08:00:01.91#ibcon#about to read 6, iclass 15, count 0 2006.217.08:00:01.91#ibcon#read 6, iclass 15, count 0 2006.217.08:00:01.91#ibcon#end of sib2, iclass 15, count 0 2006.217.08:00:01.91#ibcon#*mode == 0, iclass 15, count 0 2006.217.08:00:01.91#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.217.08:00:01.91#ibcon#[28=FRQ=05,744.99\r\n] 2006.217.08:00:01.91#ibcon#*before write, iclass 15, count 0 2006.217.08:00:01.91#ibcon#enter sib2, iclass 15, count 0 2006.217.08:00:01.91#ibcon#flushed, iclass 15, count 0 2006.217.08:00:01.91#ibcon#about to write, iclass 15, count 0 2006.217.08:00:01.91#ibcon#wrote, iclass 15, count 0 2006.217.08:00:01.91#ibcon#about to read 3, iclass 15, count 0 2006.217.08:00:01.95#ibcon#read 3, iclass 15, count 0 2006.217.08:00:01.95#ibcon#about to read 4, iclass 15, count 0 2006.217.08:00:01.95#ibcon#read 4, iclass 15, count 0 2006.217.08:00:01.95#ibcon#about to read 5, iclass 15, count 0 2006.217.08:00:01.95#ibcon#read 5, iclass 15, count 0 2006.217.08:00:01.95#ibcon#about to read 6, iclass 15, count 0 2006.217.08:00:01.95#ibcon#read 6, iclass 15, count 0 2006.217.08:00:01.95#ibcon#end of sib2, iclass 15, count 0 2006.217.08:00:01.95#ibcon#*after write, iclass 15, count 0 2006.217.08:00:01.95#ibcon#*before return 0, iclass 15, count 0 2006.217.08:00:01.95#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.217.08:00:01.95#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.217.08:00:01.95#ibcon#about to clear, iclass 15 cls_cnt 0 2006.217.08:00:01.95#ibcon#cleared, iclass 15 cls_cnt 0 2006.217.08:00:01.95$vc4f8/vb=5,4 2006.217.08:00:01.95#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.217.08:00:01.95#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.217.08:00:01.95#ibcon#ireg 11 cls_cnt 2 2006.217.08:00:01.95#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.217.08:00:02.01#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.217.08:00:02.01#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.217.08:00:02.01#ibcon#enter wrdev, iclass 17, count 2 2006.217.08:00:02.01#ibcon#first serial, iclass 17, count 2 2006.217.08:00:02.01#ibcon#enter sib2, iclass 17, count 2 2006.217.08:00:02.01#ibcon#flushed, iclass 17, count 2 2006.217.08:00:02.01#ibcon#about to write, iclass 17, count 2 2006.217.08:00:02.01#ibcon#wrote, iclass 17, count 2 2006.217.08:00:02.01#ibcon#about to read 3, iclass 17, count 2 2006.217.08:00:02.03#ibcon#read 3, iclass 17, count 2 2006.217.08:00:02.03#ibcon#about to read 4, iclass 17, count 2 2006.217.08:00:02.03#ibcon#read 4, iclass 17, count 2 2006.217.08:00:02.03#ibcon#about to read 5, iclass 17, count 2 2006.217.08:00:02.03#ibcon#read 5, iclass 17, count 2 2006.217.08:00:02.03#ibcon#about to read 6, iclass 17, count 2 2006.217.08:00:02.03#ibcon#read 6, iclass 17, count 2 2006.217.08:00:02.03#ibcon#end of sib2, iclass 17, count 2 2006.217.08:00:02.03#ibcon#*mode == 0, iclass 17, count 2 2006.217.08:00:02.03#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.217.08:00:02.03#ibcon#[27=AT05-04\r\n] 2006.217.08:00:02.03#ibcon#*before write, iclass 17, count 2 2006.217.08:00:02.03#ibcon#enter sib2, iclass 17, count 2 2006.217.08:00:02.03#ibcon#flushed, iclass 17, count 2 2006.217.08:00:02.03#ibcon#about to write, iclass 17, count 2 2006.217.08:00:02.03#ibcon#wrote, iclass 17, count 2 2006.217.08:00:02.03#ibcon#about to read 3, iclass 17, count 2 2006.217.08:00:02.06#ibcon#read 3, iclass 17, count 2 2006.217.08:00:02.06#ibcon#about to read 4, iclass 17, count 2 2006.217.08:00:02.06#ibcon#read 4, iclass 17, count 2 2006.217.08:00:02.06#ibcon#about to read 5, iclass 17, count 2 2006.217.08:00:02.06#ibcon#read 5, iclass 17, count 2 2006.217.08:00:02.06#ibcon#about to read 6, iclass 17, count 2 2006.217.08:00:02.06#ibcon#read 6, iclass 17, count 2 2006.217.08:00:02.06#ibcon#end of sib2, iclass 17, count 2 2006.217.08:00:02.06#ibcon#*after write, iclass 17, count 2 2006.217.08:00:02.06#ibcon#*before return 0, iclass 17, count 2 2006.217.08:00:02.06#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.217.08:00:02.06#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.217.08:00:02.06#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.217.08:00:02.06#ibcon#ireg 7 cls_cnt 0 2006.217.08:00:02.06#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.217.08:00:02.18#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.217.08:00:02.18#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.217.08:00:02.18#ibcon#enter wrdev, iclass 17, count 0 2006.217.08:00:02.18#ibcon#first serial, iclass 17, count 0 2006.217.08:00:02.18#ibcon#enter sib2, iclass 17, count 0 2006.217.08:00:02.18#ibcon#flushed, iclass 17, count 0 2006.217.08:00:02.18#ibcon#about to write, iclass 17, count 0 2006.217.08:00:02.18#ibcon#wrote, iclass 17, count 0 2006.217.08:00:02.18#ibcon#about to read 3, iclass 17, count 0 2006.217.08:00:02.20#ibcon#read 3, iclass 17, count 0 2006.217.08:00:02.20#ibcon#about to read 4, iclass 17, count 0 2006.217.08:00:02.20#ibcon#read 4, iclass 17, count 0 2006.217.08:00:02.20#ibcon#about to read 5, iclass 17, count 0 2006.217.08:00:02.20#ibcon#read 5, iclass 17, count 0 2006.217.08:00:02.20#ibcon#about to read 6, iclass 17, count 0 2006.217.08:00:02.20#ibcon#read 6, iclass 17, count 0 2006.217.08:00:02.20#ibcon#end of sib2, iclass 17, count 0 2006.217.08:00:02.20#ibcon#*mode == 0, iclass 17, count 0 2006.217.08:00:02.20#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.217.08:00:02.20#ibcon#[27=USB\r\n] 2006.217.08:00:02.20#ibcon#*before write, iclass 17, count 0 2006.217.08:00:02.20#ibcon#enter sib2, iclass 17, count 0 2006.217.08:00:02.20#ibcon#flushed, iclass 17, count 0 2006.217.08:00:02.20#ibcon#about to write, iclass 17, count 0 2006.217.08:00:02.20#ibcon#wrote, iclass 17, count 0 2006.217.08:00:02.20#ibcon#about to read 3, iclass 17, count 0 2006.217.08:00:02.23#ibcon#read 3, iclass 17, count 0 2006.217.08:00:02.23#ibcon#about to read 4, iclass 17, count 0 2006.217.08:00:02.23#ibcon#read 4, iclass 17, count 0 2006.217.08:00:02.23#ibcon#about to read 5, iclass 17, count 0 2006.217.08:00:02.23#ibcon#read 5, iclass 17, count 0 2006.217.08:00:02.23#ibcon#about to read 6, iclass 17, count 0 2006.217.08:00:02.23#ibcon#read 6, iclass 17, count 0 2006.217.08:00:02.23#ibcon#end of sib2, iclass 17, count 0 2006.217.08:00:02.23#ibcon#*after write, iclass 17, count 0 2006.217.08:00:02.23#ibcon#*before return 0, iclass 17, count 0 2006.217.08:00:02.23#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.217.08:00:02.23#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.217.08:00:02.23#ibcon#about to clear, iclass 17 cls_cnt 0 2006.217.08:00:02.23#ibcon#cleared, iclass 17 cls_cnt 0 2006.217.08:00:02.23$vc4f8/vblo=6,752.99 2006.217.08:00:02.23#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.217.08:00:02.23#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.217.08:00:02.23#ibcon#ireg 17 cls_cnt 0 2006.217.08:00:02.23#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.217.08:00:02.23#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.217.08:00:02.23#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.217.08:00:02.23#ibcon#enter wrdev, iclass 19, count 0 2006.217.08:00:02.23#ibcon#first serial, iclass 19, count 0 2006.217.08:00:02.23#ibcon#enter sib2, iclass 19, count 0 2006.217.08:00:02.23#ibcon#flushed, iclass 19, count 0 2006.217.08:00:02.23#ibcon#about to write, iclass 19, count 0 2006.217.08:00:02.23#ibcon#wrote, iclass 19, count 0 2006.217.08:00:02.23#ibcon#about to read 3, iclass 19, count 0 2006.217.08:00:02.25#ibcon#read 3, iclass 19, count 0 2006.217.08:00:02.25#ibcon#about to read 4, iclass 19, count 0 2006.217.08:00:02.25#ibcon#read 4, iclass 19, count 0 2006.217.08:00:02.25#ibcon#about to read 5, iclass 19, count 0 2006.217.08:00:02.25#ibcon#read 5, iclass 19, count 0 2006.217.08:00:02.25#ibcon#about to read 6, iclass 19, count 0 2006.217.08:00:02.25#ibcon#read 6, iclass 19, count 0 2006.217.08:00:02.25#ibcon#end of sib2, iclass 19, count 0 2006.217.08:00:02.25#ibcon#*mode == 0, iclass 19, count 0 2006.217.08:00:02.25#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.217.08:00:02.25#ibcon#[28=FRQ=06,752.99\r\n] 2006.217.08:00:02.25#ibcon#*before write, iclass 19, count 0 2006.217.08:00:02.25#ibcon#enter sib2, iclass 19, count 0 2006.217.08:00:02.25#ibcon#flushed, iclass 19, count 0 2006.217.08:00:02.25#ibcon#about to write, iclass 19, count 0 2006.217.08:00:02.25#ibcon#wrote, iclass 19, count 0 2006.217.08:00:02.25#ibcon#about to read 3, iclass 19, count 0 2006.217.08:00:02.30#ibcon#read 3, iclass 19, count 0 2006.217.08:00:02.30#ibcon#about to read 4, iclass 19, count 0 2006.217.08:00:02.30#ibcon#read 4, iclass 19, count 0 2006.217.08:00:02.30#ibcon#about to read 5, iclass 19, count 0 2006.217.08:00:02.30#ibcon#read 5, iclass 19, count 0 2006.217.08:00:02.30#ibcon#about to read 6, iclass 19, count 0 2006.217.08:00:02.30#ibcon#read 6, iclass 19, count 0 2006.217.08:00:02.30#ibcon#end of sib2, iclass 19, count 0 2006.217.08:00:02.30#ibcon#*after write, iclass 19, count 0 2006.217.08:00:02.30#ibcon#*before return 0, iclass 19, count 0 2006.217.08:00:02.30#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.217.08:00:02.30#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.217.08:00:02.30#ibcon#about to clear, iclass 19 cls_cnt 0 2006.217.08:00:02.30#ibcon#cleared, iclass 19 cls_cnt 0 2006.217.08:00:02.30$vc4f8/vb=6,4 2006.217.08:00:02.30#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.217.08:00:02.30#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.217.08:00:02.30#ibcon#ireg 11 cls_cnt 2 2006.217.08:00:02.30#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.217.08:00:02.34#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.217.08:00:02.34#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.217.08:00:02.34#ibcon#enter wrdev, iclass 21, count 2 2006.217.08:00:02.34#ibcon#first serial, iclass 21, count 2 2006.217.08:00:02.34#ibcon#enter sib2, iclass 21, count 2 2006.217.08:00:02.34#ibcon#flushed, iclass 21, count 2 2006.217.08:00:02.34#ibcon#about to write, iclass 21, count 2 2006.217.08:00:02.34#ibcon#wrote, iclass 21, count 2 2006.217.08:00:02.34#ibcon#about to read 3, iclass 21, count 2 2006.217.08:00:02.36#ibcon#read 3, iclass 21, count 2 2006.217.08:00:02.36#ibcon#about to read 4, iclass 21, count 2 2006.217.08:00:02.36#ibcon#read 4, iclass 21, count 2 2006.217.08:00:02.36#ibcon#about to read 5, iclass 21, count 2 2006.217.08:00:02.36#ibcon#read 5, iclass 21, count 2 2006.217.08:00:02.36#ibcon#about to read 6, iclass 21, count 2 2006.217.08:00:02.36#ibcon#read 6, iclass 21, count 2 2006.217.08:00:02.36#ibcon#end of sib2, iclass 21, count 2 2006.217.08:00:02.36#ibcon#*mode == 0, iclass 21, count 2 2006.217.08:00:02.36#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.217.08:00:02.36#ibcon#[27=AT06-04\r\n] 2006.217.08:00:02.36#ibcon#*before write, iclass 21, count 2 2006.217.08:00:02.36#ibcon#enter sib2, iclass 21, count 2 2006.217.08:00:02.36#ibcon#flushed, iclass 21, count 2 2006.217.08:00:02.36#ibcon#about to write, iclass 21, count 2 2006.217.08:00:02.36#ibcon#wrote, iclass 21, count 2 2006.217.08:00:02.36#ibcon#about to read 3, iclass 21, count 2 2006.217.08:00:02.39#ibcon#read 3, iclass 21, count 2 2006.217.08:00:02.39#ibcon#about to read 4, iclass 21, count 2 2006.217.08:00:02.39#ibcon#read 4, iclass 21, count 2 2006.217.08:00:02.39#ibcon#about to read 5, iclass 21, count 2 2006.217.08:00:02.39#ibcon#read 5, iclass 21, count 2 2006.217.08:00:02.39#ibcon#about to read 6, iclass 21, count 2 2006.217.08:00:02.39#ibcon#read 6, iclass 21, count 2 2006.217.08:00:02.39#ibcon#end of sib2, iclass 21, count 2 2006.217.08:00:02.39#ibcon#*after write, iclass 21, count 2 2006.217.08:00:02.39#ibcon#*before return 0, iclass 21, count 2 2006.217.08:00:02.39#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.217.08:00:02.39#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.217.08:00:02.39#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.217.08:00:02.39#ibcon#ireg 7 cls_cnt 0 2006.217.08:00:02.39#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.217.08:00:02.51#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.217.08:00:02.51#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.217.08:00:02.51#ibcon#enter wrdev, iclass 21, count 0 2006.217.08:00:02.51#ibcon#first serial, iclass 21, count 0 2006.217.08:00:02.51#ibcon#enter sib2, iclass 21, count 0 2006.217.08:00:02.51#ibcon#flushed, iclass 21, count 0 2006.217.08:00:02.51#ibcon#about to write, iclass 21, count 0 2006.217.08:00:02.51#ibcon#wrote, iclass 21, count 0 2006.217.08:00:02.51#ibcon#about to read 3, iclass 21, count 0 2006.217.08:00:02.53#ibcon#read 3, iclass 21, count 0 2006.217.08:00:02.53#ibcon#about to read 4, iclass 21, count 0 2006.217.08:00:02.53#ibcon#read 4, iclass 21, count 0 2006.217.08:00:02.53#ibcon#about to read 5, iclass 21, count 0 2006.217.08:00:02.53#ibcon#read 5, iclass 21, count 0 2006.217.08:00:02.53#ibcon#about to read 6, iclass 21, count 0 2006.217.08:00:02.53#ibcon#read 6, iclass 21, count 0 2006.217.08:00:02.53#ibcon#end of sib2, iclass 21, count 0 2006.217.08:00:02.53#ibcon#*mode == 0, iclass 21, count 0 2006.217.08:00:02.53#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.217.08:00:02.53#ibcon#[27=USB\r\n] 2006.217.08:00:02.53#ibcon#*before write, iclass 21, count 0 2006.217.08:00:02.53#ibcon#enter sib2, iclass 21, count 0 2006.217.08:00:02.53#ibcon#flushed, iclass 21, count 0 2006.217.08:00:02.53#ibcon#about to write, iclass 21, count 0 2006.217.08:00:02.53#ibcon#wrote, iclass 21, count 0 2006.217.08:00:02.53#ibcon#about to read 3, iclass 21, count 0 2006.217.08:00:02.56#ibcon#read 3, iclass 21, count 0 2006.217.08:00:02.56#ibcon#about to read 4, iclass 21, count 0 2006.217.08:00:02.56#ibcon#read 4, iclass 21, count 0 2006.217.08:00:02.56#ibcon#about to read 5, iclass 21, count 0 2006.217.08:00:02.56#ibcon#read 5, iclass 21, count 0 2006.217.08:00:02.56#ibcon#about to read 6, iclass 21, count 0 2006.217.08:00:02.56#ibcon#read 6, iclass 21, count 0 2006.217.08:00:02.56#ibcon#end of sib2, iclass 21, count 0 2006.217.08:00:02.56#ibcon#*after write, iclass 21, count 0 2006.217.08:00:02.56#ibcon#*before return 0, iclass 21, count 0 2006.217.08:00:02.56#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.217.08:00:02.56#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.217.08:00:02.56#ibcon#about to clear, iclass 21 cls_cnt 0 2006.217.08:00:02.56#ibcon#cleared, iclass 21 cls_cnt 0 2006.217.08:00:02.56$vc4f8/vabw=wide 2006.217.08:00:02.56#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.217.08:00:02.56#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.217.08:00:02.56#ibcon#ireg 8 cls_cnt 0 2006.217.08:00:02.56#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.217.08:00:02.56#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.217.08:00:02.56#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.217.08:00:02.56#ibcon#enter wrdev, iclass 23, count 0 2006.217.08:00:02.56#ibcon#first serial, iclass 23, count 0 2006.217.08:00:02.56#ibcon#enter sib2, iclass 23, count 0 2006.217.08:00:02.56#ibcon#flushed, iclass 23, count 0 2006.217.08:00:02.56#ibcon#about to write, iclass 23, count 0 2006.217.08:00:02.56#ibcon#wrote, iclass 23, count 0 2006.217.08:00:02.56#ibcon#about to read 3, iclass 23, count 0 2006.217.08:00:02.58#ibcon#read 3, iclass 23, count 0 2006.217.08:00:02.58#ibcon#about to read 4, iclass 23, count 0 2006.217.08:00:02.58#ibcon#read 4, iclass 23, count 0 2006.217.08:00:02.58#ibcon#about to read 5, iclass 23, count 0 2006.217.08:00:02.58#ibcon#read 5, iclass 23, count 0 2006.217.08:00:02.58#ibcon#about to read 6, iclass 23, count 0 2006.217.08:00:02.58#ibcon#read 6, iclass 23, count 0 2006.217.08:00:02.58#ibcon#end of sib2, iclass 23, count 0 2006.217.08:00:02.58#ibcon#*mode == 0, iclass 23, count 0 2006.217.08:00:02.58#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.217.08:00:02.58#ibcon#[25=BW32\r\n] 2006.217.08:00:02.58#ibcon#*before write, iclass 23, count 0 2006.217.08:00:02.58#ibcon#enter sib2, iclass 23, count 0 2006.217.08:00:02.58#ibcon#flushed, iclass 23, count 0 2006.217.08:00:02.58#ibcon#about to write, iclass 23, count 0 2006.217.08:00:02.58#ibcon#wrote, iclass 23, count 0 2006.217.08:00:02.58#ibcon#about to read 3, iclass 23, count 0 2006.217.08:00:02.61#ibcon#read 3, iclass 23, count 0 2006.217.08:00:02.61#ibcon#about to read 4, iclass 23, count 0 2006.217.08:00:02.61#ibcon#read 4, iclass 23, count 0 2006.217.08:00:02.61#ibcon#about to read 5, iclass 23, count 0 2006.217.08:00:02.61#ibcon#read 5, iclass 23, count 0 2006.217.08:00:02.61#ibcon#about to read 6, iclass 23, count 0 2006.217.08:00:02.61#ibcon#read 6, iclass 23, count 0 2006.217.08:00:02.61#ibcon#end of sib2, iclass 23, count 0 2006.217.08:00:02.61#ibcon#*after write, iclass 23, count 0 2006.217.08:00:02.61#ibcon#*before return 0, iclass 23, count 0 2006.217.08:00:02.61#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.217.08:00:02.61#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.217.08:00:02.61#ibcon#about to clear, iclass 23 cls_cnt 0 2006.217.08:00:02.61#ibcon#cleared, iclass 23 cls_cnt 0 2006.217.08:00:02.61$vc4f8/vbbw=wide 2006.217.08:00:02.61#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.217.08:00:02.61#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.217.08:00:02.61#ibcon#ireg 8 cls_cnt 0 2006.217.08:00:02.61#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.217.08:00:02.68#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.217.08:00:02.68#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.217.08:00:02.68#ibcon#enter wrdev, iclass 25, count 0 2006.217.08:00:02.68#ibcon#first serial, iclass 25, count 0 2006.217.08:00:02.68#ibcon#enter sib2, iclass 25, count 0 2006.217.08:00:02.68#ibcon#flushed, iclass 25, count 0 2006.217.08:00:02.68#ibcon#about to write, iclass 25, count 0 2006.217.08:00:02.68#ibcon#wrote, iclass 25, count 0 2006.217.08:00:02.68#ibcon#about to read 3, iclass 25, count 0 2006.217.08:00:02.70#ibcon#read 3, iclass 25, count 0 2006.217.08:00:02.70#ibcon#about to read 4, iclass 25, count 0 2006.217.08:00:02.70#ibcon#read 4, iclass 25, count 0 2006.217.08:00:02.70#ibcon#about to read 5, iclass 25, count 0 2006.217.08:00:02.70#ibcon#read 5, iclass 25, count 0 2006.217.08:00:02.70#ibcon#about to read 6, iclass 25, count 0 2006.217.08:00:02.70#ibcon#read 6, iclass 25, count 0 2006.217.08:00:02.70#ibcon#end of sib2, iclass 25, count 0 2006.217.08:00:02.70#ibcon#*mode == 0, iclass 25, count 0 2006.217.08:00:02.70#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.217.08:00:02.70#ibcon#[27=BW32\r\n] 2006.217.08:00:02.70#ibcon#*before write, iclass 25, count 0 2006.217.08:00:02.70#ibcon#enter sib2, iclass 25, count 0 2006.217.08:00:02.70#ibcon#flushed, iclass 25, count 0 2006.217.08:00:02.70#ibcon#about to write, iclass 25, count 0 2006.217.08:00:02.70#ibcon#wrote, iclass 25, count 0 2006.217.08:00:02.70#ibcon#about to read 3, iclass 25, count 0 2006.217.08:00:02.73#ibcon#read 3, iclass 25, count 0 2006.217.08:00:02.73#ibcon#about to read 4, iclass 25, count 0 2006.217.08:00:02.73#ibcon#read 4, iclass 25, count 0 2006.217.08:00:02.73#ibcon#about to read 5, iclass 25, count 0 2006.217.08:00:02.73#ibcon#read 5, iclass 25, count 0 2006.217.08:00:02.73#ibcon#about to read 6, iclass 25, count 0 2006.217.08:00:02.73#ibcon#read 6, iclass 25, count 0 2006.217.08:00:02.73#ibcon#end of sib2, iclass 25, count 0 2006.217.08:00:02.73#ibcon#*after write, iclass 25, count 0 2006.217.08:00:02.73#ibcon#*before return 0, iclass 25, count 0 2006.217.08:00:02.73#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.217.08:00:02.73#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.217.08:00:02.73#ibcon#about to clear, iclass 25 cls_cnt 0 2006.217.08:00:02.73#ibcon#cleared, iclass 25 cls_cnt 0 2006.217.08:00:02.73$4f8m12a/ifd4f 2006.217.08:00:02.73$ifd4f/lo= 2006.217.08:00:02.73$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.217.08:00:02.73$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.217.08:00:02.73$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.217.08:00:02.73$ifd4f/patch= 2006.217.08:00:02.73$ifd4f/patch=lo1,a1,a2,a3,a4 2006.217.08:00:02.73$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.217.08:00:02.73$ifd4f/patch=lo3,a5,a6,a7,a8 2006.217.08:00:02.73$4f8m12a/"form=m,16.000,1:2 2006.217.08:00:02.73$4f8m12a/"tpicd 2006.217.08:00:02.73$4f8m12a/echo=off 2006.217.08:00:02.73$4f8m12a/xlog=off 2006.217.08:00:02.73:!2006.217.08:00:30 2006.217.08:00:16.14#trakl#Source acquired 2006.217.08:00:18.14#flagr#flagr/antenna,acquired 2006.217.08:00:30.00:preob 2006.217.08:00:31.14/onsource/TRACKING 2006.217.08:00:31.14:!2006.217.08:00:40 2006.217.08:00:40.00:data_valid=on 2006.217.08:00:40.00:midob 2006.217.08:00:40.14/onsource/TRACKING 2006.217.08:00:40.14/wx/30.97,1008.6,64 2006.217.08:00:40.38/cable/+6.3863E-03 2006.217.08:00:41.47/va/01,05,usb,yes,31,33 2006.217.08:00:41.47/va/02,04,usb,yes,29,31 2006.217.08:00:41.47/va/03,04,usb,yes,27,28 2006.217.08:00:41.47/va/04,04,usb,yes,31,33 2006.217.08:00:41.47/va/05,07,usb,yes,32,34 2006.217.08:00:41.47/va/06,06,usb,yes,32,31 2006.217.08:00:41.47/va/07,06,usb,yes,32,32 2006.217.08:00:41.47/va/08,07,usb,yes,30,30 2006.217.08:00:41.70/valo/01,532.99,yes,locked 2006.217.08:00:41.70/valo/02,572.99,yes,locked 2006.217.08:00:41.70/valo/03,672.99,yes,locked 2006.217.08:00:41.70/valo/04,832.99,yes,locked 2006.217.08:00:41.70/valo/05,652.99,yes,locked 2006.217.08:00:41.70/valo/06,772.99,yes,locked 2006.217.08:00:41.70/valo/07,832.99,yes,locked 2006.217.08:00:41.70/valo/08,852.99,yes,locked 2006.217.08:00:42.79/vb/01,04,usb,yes,30,29 2006.217.08:00:42.79/vb/02,04,usb,yes,32,33 2006.217.08:00:42.79/vb/03,04,usb,yes,28,32 2006.217.08:00:42.79/vb/04,04,usb,yes,29,29 2006.217.08:00:42.79/vb/05,04,usb,yes,28,32 2006.217.08:00:42.79/vb/06,04,usb,yes,28,31 2006.217.08:00:42.79/vb/07,04,usb,yes,31,31 2006.217.08:00:42.79/vb/08,04,usb,yes,28,32 2006.217.08:00:43.02/vblo/01,632.99,yes,locked 2006.217.08:00:43.02/vblo/02,640.99,yes,locked 2006.217.08:00:43.02/vblo/03,656.99,yes,locked 2006.217.08:00:43.02/vblo/04,712.99,yes,locked 2006.217.08:00:43.02/vblo/05,744.99,yes,locked 2006.217.08:00:43.02/vblo/06,752.99,yes,locked 2006.217.08:00:43.02/vblo/07,734.99,yes,locked 2006.217.08:00:43.02/vblo/08,744.99,yes,locked 2006.217.08:00:43.17/vabw/8 2006.217.08:00:43.32/vbbw/8 2006.217.08:00:43.41/xfe/off,on,15.0 2006.217.08:00:43.79/ifatt/23,28,28,28 2006.217.08:00:44.07/fmout-gps/S +4.34E-07 2006.217.08:00:44.11:!2006.217.08:01:40 2006.217.08:01:40.00:data_valid=off 2006.217.08:01:40.00:postob 2006.217.08:01:40.09/cable/+6.3835E-03 2006.217.08:01:40.09/wx/30.94,1008.7,65 2006.217.08:01:41.07/fmout-gps/S +4.35E-07 2006.217.08:01:41.07:scan_name=217-0802,k06217,60 2006.217.08:01:41.08:source=3c371,180650.68,694928.1,2000.0,cw 2006.217.08:01:41.14#flagr#flagr/antenna,new-source 2006.217.08:01:42.14:checkk5 2006.217.08:01:42.52/chk_autoobs//k5ts1/ autoobs is running! 2006.217.08:01:42.97/chk_autoobs//k5ts2/ autoobs is running! 2006.217.08:01:43.35/chk_autoobs//k5ts3/ autoobs is running! 2006.217.08:01:43.72/chk_autoobs//k5ts4/ autoobs is running! 2006.217.08:01:44.09/chk_obsdata//k5ts1/T2170800??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.08:01:44.45/chk_obsdata//k5ts2/T2170800??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.08:01:44.81/chk_obsdata//k5ts3/T2170800??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.08:01:45.18/chk_obsdata//k5ts4/T2170800??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.08:01:45.90/k5log//k5ts1_log_newline 2006.217.08:01:46.60/k5log//k5ts2_log_newline 2006.217.08:01:47.30/k5log//k5ts3_log_newline 2006.217.08:01:47.98/k5log//k5ts4_log_newline 2006.217.08:01:48.01/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.217.08:01:48.01:4f8m12a=2 2006.217.08:01:48.01$4f8m12a/echo=on 2006.217.08:01:48.01$4f8m12a/pcalon 2006.217.08:01:48.01$pcalon/"no phase cal control is implemented here 2006.217.08:01:48.01$4f8m12a/"tpicd=stop 2006.217.08:01:48.01$4f8m12a/vc4f8 2006.217.08:01:48.01$vc4f8/valo=1,532.99 2006.217.08:01:48.01#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.217.08:01:48.01#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.217.08:01:48.01#ibcon#ireg 17 cls_cnt 0 2006.217.08:01:48.01#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.217.08:01:48.01#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.217.08:01:48.01#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.217.08:01:48.01#ibcon#enter wrdev, iclass 32, count 0 2006.217.08:01:48.01#ibcon#first serial, iclass 32, count 0 2006.217.08:01:48.01#ibcon#enter sib2, iclass 32, count 0 2006.217.08:01:48.01#ibcon#flushed, iclass 32, count 0 2006.217.08:01:48.01#ibcon#about to write, iclass 32, count 0 2006.217.08:01:48.01#ibcon#wrote, iclass 32, count 0 2006.217.08:01:48.01#ibcon#about to read 3, iclass 32, count 0 2006.217.08:01:48.05#ibcon#read 3, iclass 32, count 0 2006.217.08:01:48.05#ibcon#about to read 4, iclass 32, count 0 2006.217.08:01:48.05#ibcon#read 4, iclass 32, count 0 2006.217.08:01:48.05#ibcon#about to read 5, iclass 32, count 0 2006.217.08:01:48.05#ibcon#read 5, iclass 32, count 0 2006.217.08:01:48.05#ibcon#about to read 6, iclass 32, count 0 2006.217.08:01:48.05#ibcon#read 6, iclass 32, count 0 2006.217.08:01:48.05#ibcon#end of sib2, iclass 32, count 0 2006.217.08:01:48.05#ibcon#*mode == 0, iclass 32, count 0 2006.217.08:01:48.05#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.217.08:01:48.05#ibcon#[26=FRQ=01,532.99\r\n] 2006.217.08:01:48.05#ibcon#*before write, iclass 32, count 0 2006.217.08:01:48.05#ibcon#enter sib2, iclass 32, count 0 2006.217.08:01:48.05#ibcon#flushed, iclass 32, count 0 2006.217.08:01:48.05#ibcon#about to write, iclass 32, count 0 2006.217.08:01:48.05#ibcon#wrote, iclass 32, count 0 2006.217.08:01:48.05#ibcon#about to read 3, iclass 32, count 0 2006.217.08:01:48.10#ibcon#read 3, iclass 32, count 0 2006.217.08:01:48.10#ibcon#about to read 4, iclass 32, count 0 2006.217.08:01:48.10#ibcon#read 4, iclass 32, count 0 2006.217.08:01:48.10#ibcon#about to read 5, iclass 32, count 0 2006.217.08:01:48.10#ibcon#read 5, iclass 32, count 0 2006.217.08:01:48.10#ibcon#about to read 6, iclass 32, count 0 2006.217.08:01:48.10#ibcon#read 6, iclass 32, count 0 2006.217.08:01:48.10#ibcon#end of sib2, iclass 32, count 0 2006.217.08:01:48.10#ibcon#*after write, iclass 32, count 0 2006.217.08:01:48.10#ibcon#*before return 0, iclass 32, count 0 2006.217.08:01:48.10#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.217.08:01:48.10#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.217.08:01:48.10#ibcon#about to clear, iclass 32 cls_cnt 0 2006.217.08:01:48.10#ibcon#cleared, iclass 32 cls_cnt 0 2006.217.08:01:48.10$vc4f8/va=1,5 2006.217.08:01:48.10#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.217.08:01:48.10#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.217.08:01:48.10#ibcon#ireg 11 cls_cnt 2 2006.217.08:01:48.10#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.217.08:01:48.10#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.217.08:01:48.10#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.217.08:01:48.10#ibcon#enter wrdev, iclass 34, count 2 2006.217.08:01:48.10#ibcon#first serial, iclass 34, count 2 2006.217.08:01:48.10#ibcon#enter sib2, iclass 34, count 2 2006.217.08:01:48.10#ibcon#flushed, iclass 34, count 2 2006.217.08:01:48.10#ibcon#about to write, iclass 34, count 2 2006.217.08:01:48.10#ibcon#wrote, iclass 34, count 2 2006.217.08:01:48.10#ibcon#about to read 3, iclass 34, count 2 2006.217.08:01:48.12#ibcon#read 3, iclass 34, count 2 2006.217.08:01:48.12#ibcon#about to read 4, iclass 34, count 2 2006.217.08:01:48.12#ibcon#read 4, iclass 34, count 2 2006.217.08:01:48.12#ibcon#about to read 5, iclass 34, count 2 2006.217.08:01:48.12#ibcon#read 5, iclass 34, count 2 2006.217.08:01:48.12#ibcon#about to read 6, iclass 34, count 2 2006.217.08:01:48.12#ibcon#read 6, iclass 34, count 2 2006.217.08:01:48.12#ibcon#end of sib2, iclass 34, count 2 2006.217.08:01:48.12#ibcon#*mode == 0, iclass 34, count 2 2006.217.08:01:48.12#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.217.08:01:48.12#ibcon#[25=AT01-05\r\n] 2006.217.08:01:48.12#ibcon#*before write, iclass 34, count 2 2006.217.08:01:48.12#ibcon#enter sib2, iclass 34, count 2 2006.217.08:01:48.12#ibcon#flushed, iclass 34, count 2 2006.217.08:01:48.12#ibcon#about to write, iclass 34, count 2 2006.217.08:01:48.12#ibcon#wrote, iclass 34, count 2 2006.217.08:01:48.12#ibcon#about to read 3, iclass 34, count 2 2006.217.08:01:48.16#ibcon#read 3, iclass 34, count 2 2006.217.08:01:48.16#ibcon#about to read 4, iclass 34, count 2 2006.217.08:01:48.16#ibcon#read 4, iclass 34, count 2 2006.217.08:01:48.16#ibcon#about to read 5, iclass 34, count 2 2006.217.08:01:48.16#ibcon#read 5, iclass 34, count 2 2006.217.08:01:48.16#ibcon#about to read 6, iclass 34, count 2 2006.217.08:01:48.16#ibcon#read 6, iclass 34, count 2 2006.217.08:01:48.16#ibcon#end of sib2, iclass 34, count 2 2006.217.08:01:48.16#ibcon#*after write, iclass 34, count 2 2006.217.08:01:48.16#ibcon#*before return 0, iclass 34, count 2 2006.217.08:01:48.16#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.217.08:01:48.16#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.217.08:01:48.16#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.217.08:01:48.16#ibcon#ireg 7 cls_cnt 0 2006.217.08:01:48.16#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.217.08:01:48.28#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.217.08:01:48.28#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.217.08:01:48.28#ibcon#enter wrdev, iclass 34, count 0 2006.217.08:01:48.28#ibcon#first serial, iclass 34, count 0 2006.217.08:01:48.28#ibcon#enter sib2, iclass 34, count 0 2006.217.08:01:48.28#ibcon#flushed, iclass 34, count 0 2006.217.08:01:48.28#ibcon#about to write, iclass 34, count 0 2006.217.08:01:48.28#ibcon#wrote, iclass 34, count 0 2006.217.08:01:48.28#ibcon#about to read 3, iclass 34, count 0 2006.217.08:01:48.30#ibcon#read 3, iclass 34, count 0 2006.217.08:01:48.30#ibcon#about to read 4, iclass 34, count 0 2006.217.08:01:48.30#ibcon#read 4, iclass 34, count 0 2006.217.08:01:48.30#ibcon#about to read 5, iclass 34, count 0 2006.217.08:01:48.30#ibcon#read 5, iclass 34, count 0 2006.217.08:01:48.30#ibcon#about to read 6, iclass 34, count 0 2006.217.08:01:48.30#ibcon#read 6, iclass 34, count 0 2006.217.08:01:48.30#ibcon#end of sib2, iclass 34, count 0 2006.217.08:01:48.30#ibcon#*mode == 0, iclass 34, count 0 2006.217.08:01:48.30#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.217.08:01:48.30#ibcon#[25=USB\r\n] 2006.217.08:01:48.30#ibcon#*before write, iclass 34, count 0 2006.217.08:01:48.30#ibcon#enter sib2, iclass 34, count 0 2006.217.08:01:48.30#ibcon#flushed, iclass 34, count 0 2006.217.08:01:48.30#ibcon#about to write, iclass 34, count 0 2006.217.08:01:48.30#ibcon#wrote, iclass 34, count 0 2006.217.08:01:48.30#ibcon#about to read 3, iclass 34, count 0 2006.217.08:01:48.33#ibcon#read 3, iclass 34, count 0 2006.217.08:01:48.33#ibcon#about to read 4, iclass 34, count 0 2006.217.08:01:48.33#ibcon#read 4, iclass 34, count 0 2006.217.08:01:48.33#ibcon#about to read 5, iclass 34, count 0 2006.217.08:01:48.33#ibcon#read 5, iclass 34, count 0 2006.217.08:01:48.33#ibcon#about to read 6, iclass 34, count 0 2006.217.08:01:48.33#ibcon#read 6, iclass 34, count 0 2006.217.08:01:48.33#ibcon#end of sib2, iclass 34, count 0 2006.217.08:01:48.33#ibcon#*after write, iclass 34, count 0 2006.217.08:01:48.33#ibcon#*before return 0, iclass 34, count 0 2006.217.08:01:48.33#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.217.08:01:48.33#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.217.08:01:48.33#ibcon#about to clear, iclass 34 cls_cnt 0 2006.217.08:01:48.33#ibcon#cleared, iclass 34 cls_cnt 0 2006.217.08:01:48.33$vc4f8/valo=2,572.99 2006.217.08:01:48.33#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.217.08:01:48.33#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.217.08:01:48.33#ibcon#ireg 17 cls_cnt 0 2006.217.08:01:48.33#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.217.08:01:48.33#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.217.08:01:48.33#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.217.08:01:48.33#ibcon#enter wrdev, iclass 36, count 0 2006.217.08:01:48.33#ibcon#first serial, iclass 36, count 0 2006.217.08:01:48.33#ibcon#enter sib2, iclass 36, count 0 2006.217.08:01:48.33#ibcon#flushed, iclass 36, count 0 2006.217.08:01:48.33#ibcon#about to write, iclass 36, count 0 2006.217.08:01:48.33#ibcon#wrote, iclass 36, count 0 2006.217.08:01:48.33#ibcon#about to read 3, iclass 36, count 0 2006.217.08:01:48.36#ibcon#read 3, iclass 36, count 0 2006.217.08:01:48.36#ibcon#about to read 4, iclass 36, count 0 2006.217.08:01:48.36#ibcon#read 4, iclass 36, count 0 2006.217.08:01:48.36#ibcon#about to read 5, iclass 36, count 0 2006.217.08:01:48.36#ibcon#read 5, iclass 36, count 0 2006.217.08:01:48.36#ibcon#about to read 6, iclass 36, count 0 2006.217.08:01:48.36#ibcon#read 6, iclass 36, count 0 2006.217.08:01:48.36#ibcon#end of sib2, iclass 36, count 0 2006.217.08:01:48.36#ibcon#*mode == 0, iclass 36, count 0 2006.217.08:01:48.36#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.217.08:01:48.36#ibcon#[26=FRQ=02,572.99\r\n] 2006.217.08:01:48.36#ibcon#*before write, iclass 36, count 0 2006.217.08:01:48.36#ibcon#enter sib2, iclass 36, count 0 2006.217.08:01:48.36#ibcon#flushed, iclass 36, count 0 2006.217.08:01:48.36#ibcon#about to write, iclass 36, count 0 2006.217.08:01:48.36#ibcon#wrote, iclass 36, count 0 2006.217.08:01:48.36#ibcon#about to read 3, iclass 36, count 0 2006.217.08:01:48.40#ibcon#read 3, iclass 36, count 0 2006.217.08:01:48.40#ibcon#about to read 4, iclass 36, count 0 2006.217.08:01:48.40#ibcon#read 4, iclass 36, count 0 2006.217.08:01:48.40#ibcon#about to read 5, iclass 36, count 0 2006.217.08:01:48.40#ibcon#read 5, iclass 36, count 0 2006.217.08:01:48.40#ibcon#about to read 6, iclass 36, count 0 2006.217.08:01:48.40#ibcon#read 6, iclass 36, count 0 2006.217.08:01:48.40#ibcon#end of sib2, iclass 36, count 0 2006.217.08:01:48.40#ibcon#*after write, iclass 36, count 0 2006.217.08:01:48.40#ibcon#*before return 0, iclass 36, count 0 2006.217.08:01:48.40#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.217.08:01:48.40#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.217.08:01:48.40#ibcon#about to clear, iclass 36 cls_cnt 0 2006.217.08:01:48.40#ibcon#cleared, iclass 36 cls_cnt 0 2006.217.08:01:48.40$vc4f8/va=2,4 2006.217.08:01:48.40#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.217.08:01:48.40#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.217.08:01:48.40#ibcon#ireg 11 cls_cnt 2 2006.217.08:01:48.40#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.217.08:01:48.45#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.217.08:01:48.45#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.217.08:01:48.45#ibcon#enter wrdev, iclass 38, count 2 2006.217.08:01:48.45#ibcon#first serial, iclass 38, count 2 2006.217.08:01:48.45#ibcon#enter sib2, iclass 38, count 2 2006.217.08:01:48.45#ibcon#flushed, iclass 38, count 2 2006.217.08:01:48.45#ibcon#about to write, iclass 38, count 2 2006.217.08:01:48.45#ibcon#wrote, iclass 38, count 2 2006.217.08:01:48.45#ibcon#about to read 3, iclass 38, count 2 2006.217.08:01:48.47#ibcon#read 3, iclass 38, count 2 2006.217.08:01:48.47#ibcon#about to read 4, iclass 38, count 2 2006.217.08:01:48.47#ibcon#read 4, iclass 38, count 2 2006.217.08:01:48.47#ibcon#about to read 5, iclass 38, count 2 2006.217.08:01:48.47#ibcon#read 5, iclass 38, count 2 2006.217.08:01:48.47#ibcon#about to read 6, iclass 38, count 2 2006.217.08:01:48.47#ibcon#read 6, iclass 38, count 2 2006.217.08:01:48.47#ibcon#end of sib2, iclass 38, count 2 2006.217.08:01:48.47#ibcon#*mode == 0, iclass 38, count 2 2006.217.08:01:48.47#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.217.08:01:48.47#ibcon#[25=AT02-04\r\n] 2006.217.08:01:48.47#ibcon#*before write, iclass 38, count 2 2006.217.08:01:48.47#ibcon#enter sib2, iclass 38, count 2 2006.217.08:01:48.47#ibcon#flushed, iclass 38, count 2 2006.217.08:01:48.47#ibcon#about to write, iclass 38, count 2 2006.217.08:01:48.47#ibcon#wrote, iclass 38, count 2 2006.217.08:01:48.47#ibcon#about to read 3, iclass 38, count 2 2006.217.08:01:48.50#ibcon#read 3, iclass 38, count 2 2006.217.08:01:48.50#ibcon#about to read 4, iclass 38, count 2 2006.217.08:01:48.50#ibcon#read 4, iclass 38, count 2 2006.217.08:01:48.50#ibcon#about to read 5, iclass 38, count 2 2006.217.08:01:48.50#ibcon#read 5, iclass 38, count 2 2006.217.08:01:48.50#ibcon#about to read 6, iclass 38, count 2 2006.217.08:01:48.50#ibcon#read 6, iclass 38, count 2 2006.217.08:01:48.50#ibcon#end of sib2, iclass 38, count 2 2006.217.08:01:48.50#ibcon#*after write, iclass 38, count 2 2006.217.08:01:48.50#ibcon#*before return 0, iclass 38, count 2 2006.217.08:01:48.50#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.217.08:01:48.50#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.217.08:01:48.50#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.217.08:01:48.50#ibcon#ireg 7 cls_cnt 0 2006.217.08:01:48.50#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.217.08:01:48.62#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.217.08:01:48.62#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.217.08:01:48.62#ibcon#enter wrdev, iclass 38, count 0 2006.217.08:01:48.62#ibcon#first serial, iclass 38, count 0 2006.217.08:01:48.62#ibcon#enter sib2, iclass 38, count 0 2006.217.08:01:48.62#ibcon#flushed, iclass 38, count 0 2006.217.08:01:48.62#ibcon#about to write, iclass 38, count 0 2006.217.08:01:48.62#ibcon#wrote, iclass 38, count 0 2006.217.08:01:48.62#ibcon#about to read 3, iclass 38, count 0 2006.217.08:01:48.64#ibcon#read 3, iclass 38, count 0 2006.217.08:01:48.64#ibcon#about to read 4, iclass 38, count 0 2006.217.08:01:48.64#ibcon#read 4, iclass 38, count 0 2006.217.08:01:48.64#ibcon#about to read 5, iclass 38, count 0 2006.217.08:01:48.64#ibcon#read 5, iclass 38, count 0 2006.217.08:01:48.64#ibcon#about to read 6, iclass 38, count 0 2006.217.08:01:48.64#ibcon#read 6, iclass 38, count 0 2006.217.08:01:48.64#ibcon#end of sib2, iclass 38, count 0 2006.217.08:01:48.64#ibcon#*mode == 0, iclass 38, count 0 2006.217.08:01:48.64#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.217.08:01:48.64#ibcon#[25=USB\r\n] 2006.217.08:01:48.64#ibcon#*before write, iclass 38, count 0 2006.217.08:01:48.64#ibcon#enter sib2, iclass 38, count 0 2006.217.08:01:48.64#ibcon#flushed, iclass 38, count 0 2006.217.08:01:48.64#ibcon#about to write, iclass 38, count 0 2006.217.08:01:48.64#ibcon#wrote, iclass 38, count 0 2006.217.08:01:48.64#ibcon#about to read 3, iclass 38, count 0 2006.217.08:01:48.67#ibcon#read 3, iclass 38, count 0 2006.217.08:01:48.67#ibcon#about to read 4, iclass 38, count 0 2006.217.08:01:48.67#ibcon#read 4, iclass 38, count 0 2006.217.08:01:48.67#ibcon#about to read 5, iclass 38, count 0 2006.217.08:01:48.67#ibcon#read 5, iclass 38, count 0 2006.217.08:01:48.67#ibcon#about to read 6, iclass 38, count 0 2006.217.08:01:48.67#ibcon#read 6, iclass 38, count 0 2006.217.08:01:48.67#ibcon#end of sib2, iclass 38, count 0 2006.217.08:01:48.67#ibcon#*after write, iclass 38, count 0 2006.217.08:01:48.67#ibcon#*before return 0, iclass 38, count 0 2006.217.08:01:48.67#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.217.08:01:48.67#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.217.08:01:48.67#ibcon#about to clear, iclass 38 cls_cnt 0 2006.217.08:01:48.67#ibcon#cleared, iclass 38 cls_cnt 0 2006.217.08:01:48.67$vc4f8/valo=3,672.99 2006.217.08:01:48.67#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.217.08:01:48.67#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.217.08:01:48.67#ibcon#ireg 17 cls_cnt 0 2006.217.08:01:48.67#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.217.08:01:48.67#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.217.08:01:48.67#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.217.08:01:48.67#ibcon#enter wrdev, iclass 40, count 0 2006.217.08:01:48.67#ibcon#first serial, iclass 40, count 0 2006.217.08:01:48.67#ibcon#enter sib2, iclass 40, count 0 2006.217.08:01:48.67#ibcon#flushed, iclass 40, count 0 2006.217.08:01:48.67#ibcon#about to write, iclass 40, count 0 2006.217.08:01:48.67#ibcon#wrote, iclass 40, count 0 2006.217.08:01:48.67#ibcon#about to read 3, iclass 40, count 0 2006.217.08:01:48.70#ibcon#read 3, iclass 40, count 0 2006.217.08:01:48.70#ibcon#about to read 4, iclass 40, count 0 2006.217.08:01:48.70#ibcon#read 4, iclass 40, count 0 2006.217.08:01:48.70#ibcon#about to read 5, iclass 40, count 0 2006.217.08:01:48.70#ibcon#read 5, iclass 40, count 0 2006.217.08:01:48.70#ibcon#about to read 6, iclass 40, count 0 2006.217.08:01:48.70#ibcon#read 6, iclass 40, count 0 2006.217.08:01:48.70#ibcon#end of sib2, iclass 40, count 0 2006.217.08:01:48.70#ibcon#*mode == 0, iclass 40, count 0 2006.217.08:01:48.70#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.217.08:01:48.70#ibcon#[26=FRQ=03,672.99\r\n] 2006.217.08:01:48.70#ibcon#*before write, iclass 40, count 0 2006.217.08:01:48.70#ibcon#enter sib2, iclass 40, count 0 2006.217.08:01:48.70#ibcon#flushed, iclass 40, count 0 2006.217.08:01:48.70#ibcon#about to write, iclass 40, count 0 2006.217.08:01:48.70#ibcon#wrote, iclass 40, count 0 2006.217.08:01:48.70#ibcon#about to read 3, iclass 40, count 0 2006.217.08:01:48.74#ibcon#read 3, iclass 40, count 0 2006.217.08:01:48.74#ibcon#about to read 4, iclass 40, count 0 2006.217.08:01:48.74#ibcon#read 4, iclass 40, count 0 2006.217.08:01:48.74#ibcon#about to read 5, iclass 40, count 0 2006.217.08:01:48.74#ibcon#read 5, iclass 40, count 0 2006.217.08:01:48.74#ibcon#about to read 6, iclass 40, count 0 2006.217.08:01:48.74#ibcon#read 6, iclass 40, count 0 2006.217.08:01:48.74#ibcon#end of sib2, iclass 40, count 0 2006.217.08:01:48.74#ibcon#*after write, iclass 40, count 0 2006.217.08:01:48.74#ibcon#*before return 0, iclass 40, count 0 2006.217.08:01:48.74#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.217.08:01:48.74#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.217.08:01:48.74#ibcon#about to clear, iclass 40 cls_cnt 0 2006.217.08:01:48.74#ibcon#cleared, iclass 40 cls_cnt 0 2006.217.08:01:48.74$vc4f8/va=3,4 2006.217.08:01:48.74#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.217.08:01:48.74#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.217.08:01:48.74#ibcon#ireg 11 cls_cnt 2 2006.217.08:01:48.74#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.217.08:01:48.79#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.217.08:01:48.79#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.217.08:01:48.79#ibcon#enter wrdev, iclass 4, count 2 2006.217.08:01:48.79#ibcon#first serial, iclass 4, count 2 2006.217.08:01:48.79#ibcon#enter sib2, iclass 4, count 2 2006.217.08:01:48.79#ibcon#flushed, iclass 4, count 2 2006.217.08:01:48.79#ibcon#about to write, iclass 4, count 2 2006.217.08:01:48.79#ibcon#wrote, iclass 4, count 2 2006.217.08:01:48.79#ibcon#about to read 3, iclass 4, count 2 2006.217.08:01:48.81#ibcon#read 3, iclass 4, count 2 2006.217.08:01:48.81#ibcon#about to read 4, iclass 4, count 2 2006.217.08:01:48.81#ibcon#read 4, iclass 4, count 2 2006.217.08:01:48.81#ibcon#about to read 5, iclass 4, count 2 2006.217.08:01:48.81#ibcon#read 5, iclass 4, count 2 2006.217.08:01:48.81#ibcon#about to read 6, iclass 4, count 2 2006.217.08:01:48.81#ibcon#read 6, iclass 4, count 2 2006.217.08:01:48.81#ibcon#end of sib2, iclass 4, count 2 2006.217.08:01:48.81#ibcon#*mode == 0, iclass 4, count 2 2006.217.08:01:48.81#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.217.08:01:48.81#ibcon#[25=AT03-04\r\n] 2006.217.08:01:48.81#ibcon#*before write, iclass 4, count 2 2006.217.08:01:48.81#ibcon#enter sib2, iclass 4, count 2 2006.217.08:01:48.81#ibcon#flushed, iclass 4, count 2 2006.217.08:01:48.81#ibcon#about to write, iclass 4, count 2 2006.217.08:01:48.81#ibcon#wrote, iclass 4, count 2 2006.217.08:01:48.81#ibcon#about to read 3, iclass 4, count 2 2006.217.08:01:48.84#ibcon#read 3, iclass 4, count 2 2006.217.08:01:48.84#ibcon#about to read 4, iclass 4, count 2 2006.217.08:01:48.84#ibcon#read 4, iclass 4, count 2 2006.217.08:01:48.84#ibcon#about to read 5, iclass 4, count 2 2006.217.08:01:48.84#ibcon#read 5, iclass 4, count 2 2006.217.08:01:48.84#ibcon#about to read 6, iclass 4, count 2 2006.217.08:01:48.84#ibcon#read 6, iclass 4, count 2 2006.217.08:01:48.84#ibcon#end of sib2, iclass 4, count 2 2006.217.08:01:48.84#ibcon#*after write, iclass 4, count 2 2006.217.08:01:48.84#ibcon#*before return 0, iclass 4, count 2 2006.217.08:01:48.84#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.217.08:01:48.84#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.217.08:01:48.84#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.217.08:01:48.84#ibcon#ireg 7 cls_cnt 0 2006.217.08:01:48.84#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.217.08:01:48.96#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.217.08:01:48.96#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.217.08:01:48.96#ibcon#enter wrdev, iclass 4, count 0 2006.217.08:01:48.96#ibcon#first serial, iclass 4, count 0 2006.217.08:01:48.96#ibcon#enter sib2, iclass 4, count 0 2006.217.08:01:48.96#ibcon#flushed, iclass 4, count 0 2006.217.08:01:48.96#ibcon#about to write, iclass 4, count 0 2006.217.08:01:48.96#ibcon#wrote, iclass 4, count 0 2006.217.08:01:48.96#ibcon#about to read 3, iclass 4, count 0 2006.217.08:01:48.98#ibcon#read 3, iclass 4, count 0 2006.217.08:01:48.98#ibcon#about to read 4, iclass 4, count 0 2006.217.08:01:48.98#ibcon#read 4, iclass 4, count 0 2006.217.08:01:48.98#ibcon#about to read 5, iclass 4, count 0 2006.217.08:01:48.98#ibcon#read 5, iclass 4, count 0 2006.217.08:01:48.98#ibcon#about to read 6, iclass 4, count 0 2006.217.08:01:48.98#ibcon#read 6, iclass 4, count 0 2006.217.08:01:48.98#ibcon#end of sib2, iclass 4, count 0 2006.217.08:01:48.98#ibcon#*mode == 0, iclass 4, count 0 2006.217.08:01:48.98#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.217.08:01:48.98#ibcon#[25=USB\r\n] 2006.217.08:01:48.98#ibcon#*before write, iclass 4, count 0 2006.217.08:01:48.98#ibcon#enter sib2, iclass 4, count 0 2006.217.08:01:48.98#ibcon#flushed, iclass 4, count 0 2006.217.08:01:48.98#ibcon#about to write, iclass 4, count 0 2006.217.08:01:48.98#ibcon#wrote, iclass 4, count 0 2006.217.08:01:48.98#ibcon#about to read 3, iclass 4, count 0 2006.217.08:01:49.01#ibcon#read 3, iclass 4, count 0 2006.217.08:01:49.01#ibcon#about to read 4, iclass 4, count 0 2006.217.08:01:49.01#ibcon#read 4, iclass 4, count 0 2006.217.08:01:49.01#ibcon#about to read 5, iclass 4, count 0 2006.217.08:01:49.01#ibcon#read 5, iclass 4, count 0 2006.217.08:01:49.01#ibcon#about to read 6, iclass 4, count 0 2006.217.08:01:49.01#ibcon#read 6, iclass 4, count 0 2006.217.08:01:49.01#ibcon#end of sib2, iclass 4, count 0 2006.217.08:01:49.01#ibcon#*after write, iclass 4, count 0 2006.217.08:01:49.01#ibcon#*before return 0, iclass 4, count 0 2006.217.08:01:49.01#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.217.08:01:49.01#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.217.08:01:49.01#ibcon#about to clear, iclass 4 cls_cnt 0 2006.217.08:01:49.01#ibcon#cleared, iclass 4 cls_cnt 0 2006.217.08:01:49.01$vc4f8/valo=4,832.99 2006.217.08:01:49.01#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.217.08:01:49.01#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.217.08:01:49.01#ibcon#ireg 17 cls_cnt 0 2006.217.08:01:49.01#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.217.08:01:49.01#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.217.08:01:49.01#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.217.08:01:49.01#ibcon#enter wrdev, iclass 6, count 0 2006.217.08:01:49.01#ibcon#first serial, iclass 6, count 0 2006.217.08:01:49.01#ibcon#enter sib2, iclass 6, count 0 2006.217.08:01:49.01#ibcon#flushed, iclass 6, count 0 2006.217.08:01:49.01#ibcon#about to write, iclass 6, count 0 2006.217.08:01:49.01#ibcon#wrote, iclass 6, count 0 2006.217.08:01:49.01#ibcon#about to read 3, iclass 6, count 0 2006.217.08:01:49.03#ibcon#read 3, iclass 6, count 0 2006.217.08:01:49.03#ibcon#about to read 4, iclass 6, count 0 2006.217.08:01:49.03#ibcon#read 4, iclass 6, count 0 2006.217.08:01:49.03#ibcon#about to read 5, iclass 6, count 0 2006.217.08:01:49.03#ibcon#read 5, iclass 6, count 0 2006.217.08:01:49.03#ibcon#about to read 6, iclass 6, count 0 2006.217.08:01:49.03#ibcon#read 6, iclass 6, count 0 2006.217.08:01:49.03#ibcon#end of sib2, iclass 6, count 0 2006.217.08:01:49.03#ibcon#*mode == 0, iclass 6, count 0 2006.217.08:01:49.03#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.217.08:01:49.03#ibcon#[26=FRQ=04,832.99\r\n] 2006.217.08:01:49.03#ibcon#*before write, iclass 6, count 0 2006.217.08:01:49.03#ibcon#enter sib2, iclass 6, count 0 2006.217.08:01:49.03#ibcon#flushed, iclass 6, count 0 2006.217.08:01:49.03#ibcon#about to write, iclass 6, count 0 2006.217.08:01:49.03#ibcon#wrote, iclass 6, count 0 2006.217.08:01:49.03#ibcon#about to read 3, iclass 6, count 0 2006.217.08:01:49.07#ibcon#read 3, iclass 6, count 0 2006.217.08:01:49.07#ibcon#about to read 4, iclass 6, count 0 2006.217.08:01:49.07#ibcon#read 4, iclass 6, count 0 2006.217.08:01:49.07#ibcon#about to read 5, iclass 6, count 0 2006.217.08:01:49.07#ibcon#read 5, iclass 6, count 0 2006.217.08:01:49.07#ibcon#about to read 6, iclass 6, count 0 2006.217.08:01:49.07#ibcon#read 6, iclass 6, count 0 2006.217.08:01:49.07#ibcon#end of sib2, iclass 6, count 0 2006.217.08:01:49.07#ibcon#*after write, iclass 6, count 0 2006.217.08:01:49.07#ibcon#*before return 0, iclass 6, count 0 2006.217.08:01:49.07#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.217.08:01:49.07#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.217.08:01:49.07#ibcon#about to clear, iclass 6 cls_cnt 0 2006.217.08:01:49.07#ibcon#cleared, iclass 6 cls_cnt 0 2006.217.08:01:49.07$vc4f8/va=4,4 2006.217.08:01:49.07#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.217.08:01:49.07#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.217.08:01:49.07#ibcon#ireg 11 cls_cnt 2 2006.217.08:01:49.07#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.217.08:01:49.13#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.217.08:01:49.13#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.217.08:01:49.13#ibcon#enter wrdev, iclass 10, count 2 2006.217.08:01:49.13#ibcon#first serial, iclass 10, count 2 2006.217.08:01:49.13#ibcon#enter sib2, iclass 10, count 2 2006.217.08:01:49.13#ibcon#flushed, iclass 10, count 2 2006.217.08:01:49.13#ibcon#about to write, iclass 10, count 2 2006.217.08:01:49.13#ibcon#wrote, iclass 10, count 2 2006.217.08:01:49.13#ibcon#about to read 3, iclass 10, count 2 2006.217.08:01:49.15#ibcon#read 3, iclass 10, count 2 2006.217.08:01:49.15#ibcon#about to read 4, iclass 10, count 2 2006.217.08:01:49.15#ibcon#read 4, iclass 10, count 2 2006.217.08:01:49.15#ibcon#about to read 5, iclass 10, count 2 2006.217.08:01:49.15#ibcon#read 5, iclass 10, count 2 2006.217.08:01:49.15#ibcon#about to read 6, iclass 10, count 2 2006.217.08:01:49.15#ibcon#read 6, iclass 10, count 2 2006.217.08:01:49.15#ibcon#end of sib2, iclass 10, count 2 2006.217.08:01:49.15#ibcon#*mode == 0, iclass 10, count 2 2006.217.08:01:49.15#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.217.08:01:49.15#ibcon#[25=AT04-04\r\n] 2006.217.08:01:49.15#ibcon#*before write, iclass 10, count 2 2006.217.08:01:49.15#ibcon#enter sib2, iclass 10, count 2 2006.217.08:01:49.15#ibcon#flushed, iclass 10, count 2 2006.217.08:01:49.15#ibcon#about to write, iclass 10, count 2 2006.217.08:01:49.15#ibcon#wrote, iclass 10, count 2 2006.217.08:01:49.15#ibcon#about to read 3, iclass 10, count 2 2006.217.08:01:49.18#ibcon#read 3, iclass 10, count 2 2006.217.08:01:49.18#ibcon#about to read 4, iclass 10, count 2 2006.217.08:01:49.18#ibcon#read 4, iclass 10, count 2 2006.217.08:01:49.18#ibcon#about to read 5, iclass 10, count 2 2006.217.08:01:49.18#ibcon#read 5, iclass 10, count 2 2006.217.08:01:49.18#ibcon#about to read 6, iclass 10, count 2 2006.217.08:01:49.18#ibcon#read 6, iclass 10, count 2 2006.217.08:01:49.18#ibcon#end of sib2, iclass 10, count 2 2006.217.08:01:49.18#ibcon#*after write, iclass 10, count 2 2006.217.08:01:49.18#ibcon#*before return 0, iclass 10, count 2 2006.217.08:01:49.18#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.217.08:01:49.18#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.217.08:01:49.18#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.217.08:01:49.18#ibcon#ireg 7 cls_cnt 0 2006.217.08:01:49.18#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.217.08:01:49.30#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.217.08:01:49.30#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.217.08:01:49.30#ibcon#enter wrdev, iclass 10, count 0 2006.217.08:01:49.30#ibcon#first serial, iclass 10, count 0 2006.217.08:01:49.30#ibcon#enter sib2, iclass 10, count 0 2006.217.08:01:49.30#ibcon#flushed, iclass 10, count 0 2006.217.08:01:49.30#ibcon#about to write, iclass 10, count 0 2006.217.08:01:49.30#ibcon#wrote, iclass 10, count 0 2006.217.08:01:49.30#ibcon#about to read 3, iclass 10, count 0 2006.217.08:01:49.32#ibcon#read 3, iclass 10, count 0 2006.217.08:01:49.32#ibcon#about to read 4, iclass 10, count 0 2006.217.08:01:49.32#ibcon#read 4, iclass 10, count 0 2006.217.08:01:49.32#ibcon#about to read 5, iclass 10, count 0 2006.217.08:01:49.32#ibcon#read 5, iclass 10, count 0 2006.217.08:01:49.32#ibcon#about to read 6, iclass 10, count 0 2006.217.08:01:49.32#ibcon#read 6, iclass 10, count 0 2006.217.08:01:49.32#ibcon#end of sib2, iclass 10, count 0 2006.217.08:01:49.32#ibcon#*mode == 0, iclass 10, count 0 2006.217.08:01:49.32#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.217.08:01:49.32#ibcon#[25=USB\r\n] 2006.217.08:01:49.32#ibcon#*before write, iclass 10, count 0 2006.217.08:01:49.32#ibcon#enter sib2, iclass 10, count 0 2006.217.08:01:49.32#ibcon#flushed, iclass 10, count 0 2006.217.08:01:49.32#ibcon#about to write, iclass 10, count 0 2006.217.08:01:49.32#ibcon#wrote, iclass 10, count 0 2006.217.08:01:49.32#ibcon#about to read 3, iclass 10, count 0 2006.217.08:01:49.35#ibcon#read 3, iclass 10, count 0 2006.217.08:01:49.35#ibcon#about to read 4, iclass 10, count 0 2006.217.08:01:49.35#ibcon#read 4, iclass 10, count 0 2006.217.08:01:49.35#ibcon#about to read 5, iclass 10, count 0 2006.217.08:01:49.35#ibcon#read 5, iclass 10, count 0 2006.217.08:01:49.35#ibcon#about to read 6, iclass 10, count 0 2006.217.08:01:49.35#ibcon#read 6, iclass 10, count 0 2006.217.08:01:49.35#ibcon#end of sib2, iclass 10, count 0 2006.217.08:01:49.35#ibcon#*after write, iclass 10, count 0 2006.217.08:01:49.35#ibcon#*before return 0, iclass 10, count 0 2006.217.08:01:49.35#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.217.08:01:49.35#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.217.08:01:49.35#ibcon#about to clear, iclass 10 cls_cnt 0 2006.217.08:01:49.35#ibcon#cleared, iclass 10 cls_cnt 0 2006.217.08:01:49.35$vc4f8/valo=5,652.99 2006.217.08:01:49.35#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.217.08:01:49.35#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.217.08:01:49.35#ibcon#ireg 17 cls_cnt 0 2006.217.08:01:49.35#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.217.08:01:49.35#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.217.08:01:49.35#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.217.08:01:49.35#ibcon#enter wrdev, iclass 12, count 0 2006.217.08:01:49.35#ibcon#first serial, iclass 12, count 0 2006.217.08:01:49.35#ibcon#enter sib2, iclass 12, count 0 2006.217.08:01:49.35#ibcon#flushed, iclass 12, count 0 2006.217.08:01:49.35#ibcon#about to write, iclass 12, count 0 2006.217.08:01:49.35#ibcon#wrote, iclass 12, count 0 2006.217.08:01:49.35#ibcon#about to read 3, iclass 12, count 0 2006.217.08:01:49.37#ibcon#read 3, iclass 12, count 0 2006.217.08:01:49.37#ibcon#about to read 4, iclass 12, count 0 2006.217.08:01:49.37#ibcon#read 4, iclass 12, count 0 2006.217.08:01:49.37#ibcon#about to read 5, iclass 12, count 0 2006.217.08:01:49.37#ibcon#read 5, iclass 12, count 0 2006.217.08:01:49.37#ibcon#about to read 6, iclass 12, count 0 2006.217.08:01:49.37#ibcon#read 6, iclass 12, count 0 2006.217.08:01:49.37#ibcon#end of sib2, iclass 12, count 0 2006.217.08:01:49.37#ibcon#*mode == 0, iclass 12, count 0 2006.217.08:01:49.37#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.217.08:01:49.37#ibcon#[26=FRQ=05,652.99\r\n] 2006.217.08:01:49.37#ibcon#*before write, iclass 12, count 0 2006.217.08:01:49.37#ibcon#enter sib2, iclass 12, count 0 2006.217.08:01:49.37#ibcon#flushed, iclass 12, count 0 2006.217.08:01:49.37#ibcon#about to write, iclass 12, count 0 2006.217.08:01:49.37#ibcon#wrote, iclass 12, count 0 2006.217.08:01:49.37#ibcon#about to read 3, iclass 12, count 0 2006.217.08:01:49.41#ibcon#read 3, iclass 12, count 0 2006.217.08:01:49.41#ibcon#about to read 4, iclass 12, count 0 2006.217.08:01:49.41#ibcon#read 4, iclass 12, count 0 2006.217.08:01:49.41#ibcon#about to read 5, iclass 12, count 0 2006.217.08:01:49.41#ibcon#read 5, iclass 12, count 0 2006.217.08:01:49.41#ibcon#about to read 6, iclass 12, count 0 2006.217.08:01:49.41#ibcon#read 6, iclass 12, count 0 2006.217.08:01:49.41#ibcon#end of sib2, iclass 12, count 0 2006.217.08:01:49.41#ibcon#*after write, iclass 12, count 0 2006.217.08:01:49.41#ibcon#*before return 0, iclass 12, count 0 2006.217.08:01:49.41#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.217.08:01:49.41#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.217.08:01:49.41#ibcon#about to clear, iclass 12 cls_cnt 0 2006.217.08:01:49.41#ibcon#cleared, iclass 12 cls_cnt 0 2006.217.08:01:49.41$vc4f8/va=5,7 2006.217.08:01:49.41#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.217.08:01:49.41#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.217.08:01:49.41#ibcon#ireg 11 cls_cnt 2 2006.217.08:01:49.41#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.217.08:01:49.47#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.217.08:01:49.47#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.217.08:01:49.47#ibcon#enter wrdev, iclass 14, count 2 2006.217.08:01:49.47#ibcon#first serial, iclass 14, count 2 2006.217.08:01:49.47#ibcon#enter sib2, iclass 14, count 2 2006.217.08:01:49.47#ibcon#flushed, iclass 14, count 2 2006.217.08:01:49.47#ibcon#about to write, iclass 14, count 2 2006.217.08:01:49.47#ibcon#wrote, iclass 14, count 2 2006.217.08:01:49.47#ibcon#about to read 3, iclass 14, count 2 2006.217.08:01:49.49#ibcon#read 3, iclass 14, count 2 2006.217.08:01:49.49#ibcon#about to read 4, iclass 14, count 2 2006.217.08:01:49.49#ibcon#read 4, iclass 14, count 2 2006.217.08:01:49.49#ibcon#about to read 5, iclass 14, count 2 2006.217.08:01:49.49#ibcon#read 5, iclass 14, count 2 2006.217.08:01:49.49#ibcon#about to read 6, iclass 14, count 2 2006.217.08:01:49.49#ibcon#read 6, iclass 14, count 2 2006.217.08:01:49.49#ibcon#end of sib2, iclass 14, count 2 2006.217.08:01:49.49#ibcon#*mode == 0, iclass 14, count 2 2006.217.08:01:49.49#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.217.08:01:49.49#ibcon#[25=AT05-07\r\n] 2006.217.08:01:49.49#ibcon#*before write, iclass 14, count 2 2006.217.08:01:49.49#ibcon#enter sib2, iclass 14, count 2 2006.217.08:01:49.49#ibcon#flushed, iclass 14, count 2 2006.217.08:01:49.49#ibcon#about to write, iclass 14, count 2 2006.217.08:01:49.49#ibcon#wrote, iclass 14, count 2 2006.217.08:01:49.49#ibcon#about to read 3, iclass 14, count 2 2006.217.08:01:49.52#ibcon#read 3, iclass 14, count 2 2006.217.08:01:49.52#ibcon#about to read 4, iclass 14, count 2 2006.217.08:01:49.52#ibcon#read 4, iclass 14, count 2 2006.217.08:01:49.52#ibcon#about to read 5, iclass 14, count 2 2006.217.08:01:49.52#ibcon#read 5, iclass 14, count 2 2006.217.08:01:49.52#ibcon#about to read 6, iclass 14, count 2 2006.217.08:01:49.52#ibcon#read 6, iclass 14, count 2 2006.217.08:01:49.52#ibcon#end of sib2, iclass 14, count 2 2006.217.08:01:49.52#ibcon#*after write, iclass 14, count 2 2006.217.08:01:49.52#ibcon#*before return 0, iclass 14, count 2 2006.217.08:01:49.52#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.217.08:01:49.52#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.217.08:01:49.52#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.217.08:01:49.52#ibcon#ireg 7 cls_cnt 0 2006.217.08:01:49.52#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.217.08:01:49.64#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.217.08:01:49.64#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.217.08:01:49.64#ibcon#enter wrdev, iclass 14, count 0 2006.217.08:01:49.64#ibcon#first serial, iclass 14, count 0 2006.217.08:01:49.64#ibcon#enter sib2, iclass 14, count 0 2006.217.08:01:49.64#ibcon#flushed, iclass 14, count 0 2006.217.08:01:49.64#ibcon#about to write, iclass 14, count 0 2006.217.08:01:49.64#ibcon#wrote, iclass 14, count 0 2006.217.08:01:49.64#ibcon#about to read 3, iclass 14, count 0 2006.217.08:01:49.66#ibcon#read 3, iclass 14, count 0 2006.217.08:01:49.66#ibcon#about to read 4, iclass 14, count 0 2006.217.08:01:49.66#ibcon#read 4, iclass 14, count 0 2006.217.08:01:49.66#ibcon#about to read 5, iclass 14, count 0 2006.217.08:01:49.66#ibcon#read 5, iclass 14, count 0 2006.217.08:01:49.66#ibcon#about to read 6, iclass 14, count 0 2006.217.08:01:49.66#ibcon#read 6, iclass 14, count 0 2006.217.08:01:49.66#ibcon#end of sib2, iclass 14, count 0 2006.217.08:01:49.66#ibcon#*mode == 0, iclass 14, count 0 2006.217.08:01:49.66#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.217.08:01:49.66#ibcon#[25=USB\r\n] 2006.217.08:01:49.66#ibcon#*before write, iclass 14, count 0 2006.217.08:01:49.66#ibcon#enter sib2, iclass 14, count 0 2006.217.08:01:49.66#ibcon#flushed, iclass 14, count 0 2006.217.08:01:49.66#ibcon#about to write, iclass 14, count 0 2006.217.08:01:49.66#ibcon#wrote, iclass 14, count 0 2006.217.08:01:49.66#ibcon#about to read 3, iclass 14, count 0 2006.217.08:01:49.69#ibcon#read 3, iclass 14, count 0 2006.217.08:01:49.69#ibcon#about to read 4, iclass 14, count 0 2006.217.08:01:49.69#ibcon#read 4, iclass 14, count 0 2006.217.08:01:49.69#ibcon#about to read 5, iclass 14, count 0 2006.217.08:01:49.69#ibcon#read 5, iclass 14, count 0 2006.217.08:01:49.69#ibcon#about to read 6, iclass 14, count 0 2006.217.08:01:49.69#ibcon#read 6, iclass 14, count 0 2006.217.08:01:49.69#ibcon#end of sib2, iclass 14, count 0 2006.217.08:01:49.69#ibcon#*after write, iclass 14, count 0 2006.217.08:01:49.69#ibcon#*before return 0, iclass 14, count 0 2006.217.08:01:49.69#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.217.08:01:49.69#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.217.08:01:49.69#ibcon#about to clear, iclass 14 cls_cnt 0 2006.217.08:01:49.69#ibcon#cleared, iclass 14 cls_cnt 0 2006.217.08:01:49.69$vc4f8/valo=6,772.99 2006.217.08:01:49.69#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.217.08:01:49.69#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.217.08:01:49.69#ibcon#ireg 17 cls_cnt 0 2006.217.08:01:49.69#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.217.08:01:49.69#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.217.08:01:49.69#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.217.08:01:49.69#ibcon#enter wrdev, iclass 16, count 0 2006.217.08:01:49.69#ibcon#first serial, iclass 16, count 0 2006.217.08:01:49.69#ibcon#enter sib2, iclass 16, count 0 2006.217.08:01:49.69#ibcon#flushed, iclass 16, count 0 2006.217.08:01:49.69#ibcon#about to write, iclass 16, count 0 2006.217.08:01:49.69#ibcon#wrote, iclass 16, count 0 2006.217.08:01:49.69#ibcon#about to read 3, iclass 16, count 0 2006.217.08:01:49.72#ibcon#read 3, iclass 16, count 0 2006.217.08:01:49.72#ibcon#about to read 4, iclass 16, count 0 2006.217.08:01:49.72#ibcon#read 4, iclass 16, count 0 2006.217.08:01:49.72#ibcon#about to read 5, iclass 16, count 0 2006.217.08:01:49.72#ibcon#read 5, iclass 16, count 0 2006.217.08:01:49.72#ibcon#about to read 6, iclass 16, count 0 2006.217.08:01:49.72#ibcon#read 6, iclass 16, count 0 2006.217.08:01:49.72#ibcon#end of sib2, iclass 16, count 0 2006.217.08:01:49.72#ibcon#*mode == 0, iclass 16, count 0 2006.217.08:01:49.72#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.217.08:01:49.72#ibcon#[26=FRQ=06,772.99\r\n] 2006.217.08:01:49.72#ibcon#*before write, iclass 16, count 0 2006.217.08:01:49.72#ibcon#enter sib2, iclass 16, count 0 2006.217.08:01:49.72#ibcon#flushed, iclass 16, count 0 2006.217.08:01:49.72#ibcon#about to write, iclass 16, count 0 2006.217.08:01:49.72#ibcon#wrote, iclass 16, count 0 2006.217.08:01:49.72#ibcon#about to read 3, iclass 16, count 0 2006.217.08:01:49.76#ibcon#read 3, iclass 16, count 0 2006.217.08:01:49.76#ibcon#about to read 4, iclass 16, count 0 2006.217.08:01:49.76#ibcon#read 4, iclass 16, count 0 2006.217.08:01:49.76#ibcon#about to read 5, iclass 16, count 0 2006.217.08:01:49.76#ibcon#read 5, iclass 16, count 0 2006.217.08:01:49.76#ibcon#about to read 6, iclass 16, count 0 2006.217.08:01:49.76#ibcon#read 6, iclass 16, count 0 2006.217.08:01:49.76#ibcon#end of sib2, iclass 16, count 0 2006.217.08:01:49.76#ibcon#*after write, iclass 16, count 0 2006.217.08:01:49.76#ibcon#*before return 0, iclass 16, count 0 2006.217.08:01:49.76#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.217.08:01:49.76#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.217.08:01:49.76#ibcon#about to clear, iclass 16 cls_cnt 0 2006.217.08:01:49.76#ibcon#cleared, iclass 16 cls_cnt 0 2006.217.08:01:49.76$vc4f8/va=6,6 2006.217.08:01:49.76#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.217.08:01:49.76#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.217.08:01:49.76#ibcon#ireg 11 cls_cnt 2 2006.217.08:01:49.76#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.217.08:01:49.81#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.217.08:01:49.81#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.217.08:01:49.81#ibcon#enter wrdev, iclass 18, count 2 2006.217.08:01:49.81#ibcon#first serial, iclass 18, count 2 2006.217.08:01:49.81#ibcon#enter sib2, iclass 18, count 2 2006.217.08:01:49.81#ibcon#flushed, iclass 18, count 2 2006.217.08:01:49.81#ibcon#about to write, iclass 18, count 2 2006.217.08:01:49.81#ibcon#wrote, iclass 18, count 2 2006.217.08:01:49.81#ibcon#about to read 3, iclass 18, count 2 2006.217.08:01:49.83#ibcon#read 3, iclass 18, count 2 2006.217.08:01:49.83#ibcon#about to read 4, iclass 18, count 2 2006.217.08:01:49.83#ibcon#read 4, iclass 18, count 2 2006.217.08:01:49.83#ibcon#about to read 5, iclass 18, count 2 2006.217.08:01:49.83#ibcon#read 5, iclass 18, count 2 2006.217.08:01:49.83#ibcon#about to read 6, iclass 18, count 2 2006.217.08:01:49.83#ibcon#read 6, iclass 18, count 2 2006.217.08:01:49.83#ibcon#end of sib2, iclass 18, count 2 2006.217.08:01:49.83#ibcon#*mode == 0, iclass 18, count 2 2006.217.08:01:49.83#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.217.08:01:49.83#ibcon#[25=AT06-06\r\n] 2006.217.08:01:49.83#ibcon#*before write, iclass 18, count 2 2006.217.08:01:49.83#ibcon#enter sib2, iclass 18, count 2 2006.217.08:01:49.83#ibcon#flushed, iclass 18, count 2 2006.217.08:01:49.83#ibcon#about to write, iclass 18, count 2 2006.217.08:01:49.83#ibcon#wrote, iclass 18, count 2 2006.217.08:01:49.83#ibcon#about to read 3, iclass 18, count 2 2006.217.08:01:49.86#ibcon#read 3, iclass 18, count 2 2006.217.08:01:49.86#ibcon#about to read 4, iclass 18, count 2 2006.217.08:01:49.86#ibcon#read 4, iclass 18, count 2 2006.217.08:01:49.86#ibcon#about to read 5, iclass 18, count 2 2006.217.08:01:49.86#ibcon#read 5, iclass 18, count 2 2006.217.08:01:49.86#ibcon#about to read 6, iclass 18, count 2 2006.217.08:01:49.86#ibcon#read 6, iclass 18, count 2 2006.217.08:01:49.86#ibcon#end of sib2, iclass 18, count 2 2006.217.08:01:49.86#ibcon#*after write, iclass 18, count 2 2006.217.08:01:49.86#ibcon#*before return 0, iclass 18, count 2 2006.217.08:01:49.86#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.217.08:01:49.86#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.217.08:01:49.86#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.217.08:01:49.86#ibcon#ireg 7 cls_cnt 0 2006.217.08:01:49.86#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.217.08:01:49.98#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.217.08:01:49.98#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.217.08:01:49.98#ibcon#enter wrdev, iclass 18, count 0 2006.217.08:01:49.98#ibcon#first serial, iclass 18, count 0 2006.217.08:01:49.98#ibcon#enter sib2, iclass 18, count 0 2006.217.08:01:49.98#ibcon#flushed, iclass 18, count 0 2006.217.08:01:49.98#ibcon#about to write, iclass 18, count 0 2006.217.08:01:49.98#ibcon#wrote, iclass 18, count 0 2006.217.08:01:49.98#ibcon#about to read 3, iclass 18, count 0 2006.217.08:01:50.00#ibcon#read 3, iclass 18, count 0 2006.217.08:01:50.00#ibcon#about to read 4, iclass 18, count 0 2006.217.08:01:50.00#ibcon#read 4, iclass 18, count 0 2006.217.08:01:50.00#ibcon#about to read 5, iclass 18, count 0 2006.217.08:01:50.00#ibcon#read 5, iclass 18, count 0 2006.217.08:01:50.00#ibcon#about to read 6, iclass 18, count 0 2006.217.08:01:50.00#ibcon#read 6, iclass 18, count 0 2006.217.08:01:50.00#ibcon#end of sib2, iclass 18, count 0 2006.217.08:01:50.00#ibcon#*mode == 0, iclass 18, count 0 2006.217.08:01:50.00#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.217.08:01:50.00#ibcon#[25=USB\r\n] 2006.217.08:01:50.00#ibcon#*before write, iclass 18, count 0 2006.217.08:01:50.00#ibcon#enter sib2, iclass 18, count 0 2006.217.08:01:50.00#ibcon#flushed, iclass 18, count 0 2006.217.08:01:50.00#ibcon#about to write, iclass 18, count 0 2006.217.08:01:50.00#ibcon#wrote, iclass 18, count 0 2006.217.08:01:50.00#ibcon#about to read 3, iclass 18, count 0 2006.217.08:01:50.03#ibcon#read 3, iclass 18, count 0 2006.217.08:01:50.03#ibcon#about to read 4, iclass 18, count 0 2006.217.08:01:50.03#ibcon#read 4, iclass 18, count 0 2006.217.08:01:50.03#ibcon#about to read 5, iclass 18, count 0 2006.217.08:01:50.03#ibcon#read 5, iclass 18, count 0 2006.217.08:01:50.03#ibcon#about to read 6, iclass 18, count 0 2006.217.08:01:50.03#ibcon#read 6, iclass 18, count 0 2006.217.08:01:50.03#ibcon#end of sib2, iclass 18, count 0 2006.217.08:01:50.03#ibcon#*after write, iclass 18, count 0 2006.217.08:01:50.03#ibcon#*before return 0, iclass 18, count 0 2006.217.08:01:50.03#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.217.08:01:50.03#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.217.08:01:50.03#ibcon#about to clear, iclass 18 cls_cnt 0 2006.217.08:01:50.03#ibcon#cleared, iclass 18 cls_cnt 0 2006.217.08:01:50.03$vc4f8/valo=7,832.99 2006.217.08:01:50.03#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.217.08:01:50.03#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.217.08:01:50.03#ibcon#ireg 17 cls_cnt 0 2006.217.08:01:50.03#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.217.08:01:50.03#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.217.08:01:50.03#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.217.08:01:50.03#ibcon#enter wrdev, iclass 20, count 0 2006.217.08:01:50.03#ibcon#first serial, iclass 20, count 0 2006.217.08:01:50.03#ibcon#enter sib2, iclass 20, count 0 2006.217.08:01:50.03#ibcon#flushed, iclass 20, count 0 2006.217.08:01:50.03#ibcon#about to write, iclass 20, count 0 2006.217.08:01:50.03#ibcon#wrote, iclass 20, count 0 2006.217.08:01:50.03#ibcon#about to read 3, iclass 20, count 0 2006.217.08:01:50.05#ibcon#read 3, iclass 20, count 0 2006.217.08:01:50.05#ibcon#about to read 4, iclass 20, count 0 2006.217.08:01:50.05#ibcon#read 4, iclass 20, count 0 2006.217.08:01:50.05#ibcon#about to read 5, iclass 20, count 0 2006.217.08:01:50.05#ibcon#read 5, iclass 20, count 0 2006.217.08:01:50.05#ibcon#about to read 6, iclass 20, count 0 2006.217.08:01:50.05#ibcon#read 6, iclass 20, count 0 2006.217.08:01:50.05#ibcon#end of sib2, iclass 20, count 0 2006.217.08:01:50.05#ibcon#*mode == 0, iclass 20, count 0 2006.217.08:01:50.05#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.217.08:01:50.05#ibcon#[26=FRQ=07,832.99\r\n] 2006.217.08:01:50.05#ibcon#*before write, iclass 20, count 0 2006.217.08:01:50.05#ibcon#enter sib2, iclass 20, count 0 2006.217.08:01:50.05#ibcon#flushed, iclass 20, count 0 2006.217.08:01:50.05#ibcon#about to write, iclass 20, count 0 2006.217.08:01:50.05#ibcon#wrote, iclass 20, count 0 2006.217.08:01:50.05#ibcon#about to read 3, iclass 20, count 0 2006.217.08:01:50.09#ibcon#read 3, iclass 20, count 0 2006.217.08:01:50.09#ibcon#about to read 4, iclass 20, count 0 2006.217.08:01:50.09#ibcon#read 4, iclass 20, count 0 2006.217.08:01:50.09#ibcon#about to read 5, iclass 20, count 0 2006.217.08:01:50.09#ibcon#read 5, iclass 20, count 0 2006.217.08:01:50.09#ibcon#about to read 6, iclass 20, count 0 2006.217.08:01:50.09#ibcon#read 6, iclass 20, count 0 2006.217.08:01:50.09#ibcon#end of sib2, iclass 20, count 0 2006.217.08:01:50.09#ibcon#*after write, iclass 20, count 0 2006.217.08:01:50.09#ibcon#*before return 0, iclass 20, count 0 2006.217.08:01:50.09#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.217.08:01:50.09#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.217.08:01:50.09#ibcon#about to clear, iclass 20 cls_cnt 0 2006.217.08:01:50.09#ibcon#cleared, iclass 20 cls_cnt 0 2006.217.08:01:50.09$vc4f8/va=7,6 2006.217.08:01:50.09#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.217.08:01:50.09#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.217.08:01:50.09#ibcon#ireg 11 cls_cnt 2 2006.217.08:01:50.09#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.217.08:01:50.15#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.217.08:01:50.15#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.217.08:01:50.15#ibcon#enter wrdev, iclass 22, count 2 2006.217.08:01:50.15#ibcon#first serial, iclass 22, count 2 2006.217.08:01:50.15#ibcon#enter sib2, iclass 22, count 2 2006.217.08:01:50.15#ibcon#flushed, iclass 22, count 2 2006.217.08:01:50.15#ibcon#about to write, iclass 22, count 2 2006.217.08:01:50.15#ibcon#wrote, iclass 22, count 2 2006.217.08:01:50.15#ibcon#about to read 3, iclass 22, count 2 2006.217.08:01:50.17#ibcon#read 3, iclass 22, count 2 2006.217.08:01:50.17#ibcon#about to read 4, iclass 22, count 2 2006.217.08:01:50.17#ibcon#read 4, iclass 22, count 2 2006.217.08:01:50.17#ibcon#about to read 5, iclass 22, count 2 2006.217.08:01:50.17#ibcon#read 5, iclass 22, count 2 2006.217.08:01:50.17#ibcon#about to read 6, iclass 22, count 2 2006.217.08:01:50.17#ibcon#read 6, iclass 22, count 2 2006.217.08:01:50.17#ibcon#end of sib2, iclass 22, count 2 2006.217.08:01:50.17#ibcon#*mode == 0, iclass 22, count 2 2006.217.08:01:50.17#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.217.08:01:50.17#ibcon#[25=AT07-06\r\n] 2006.217.08:01:50.17#ibcon#*before write, iclass 22, count 2 2006.217.08:01:50.17#ibcon#enter sib2, iclass 22, count 2 2006.217.08:01:50.17#ibcon#flushed, iclass 22, count 2 2006.217.08:01:50.17#ibcon#about to write, iclass 22, count 2 2006.217.08:01:50.17#ibcon#wrote, iclass 22, count 2 2006.217.08:01:50.17#ibcon#about to read 3, iclass 22, count 2 2006.217.08:01:50.20#ibcon#read 3, iclass 22, count 2 2006.217.08:01:50.20#ibcon#about to read 4, iclass 22, count 2 2006.217.08:01:50.20#ibcon#read 4, iclass 22, count 2 2006.217.08:01:50.20#ibcon#about to read 5, iclass 22, count 2 2006.217.08:01:50.20#ibcon#read 5, iclass 22, count 2 2006.217.08:01:50.20#ibcon#about to read 6, iclass 22, count 2 2006.217.08:01:50.20#ibcon#read 6, iclass 22, count 2 2006.217.08:01:50.20#ibcon#end of sib2, iclass 22, count 2 2006.217.08:01:50.20#ibcon#*after write, iclass 22, count 2 2006.217.08:01:50.20#ibcon#*before return 0, iclass 22, count 2 2006.217.08:01:50.20#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.217.08:01:50.20#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.217.08:01:50.20#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.217.08:01:50.20#ibcon#ireg 7 cls_cnt 0 2006.217.08:01:50.20#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.217.08:01:50.32#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.217.08:01:50.32#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.217.08:01:50.32#ibcon#enter wrdev, iclass 22, count 0 2006.217.08:01:50.32#ibcon#first serial, iclass 22, count 0 2006.217.08:01:50.32#ibcon#enter sib2, iclass 22, count 0 2006.217.08:01:50.32#ibcon#flushed, iclass 22, count 0 2006.217.08:01:50.32#ibcon#about to write, iclass 22, count 0 2006.217.08:01:50.32#ibcon#wrote, iclass 22, count 0 2006.217.08:01:50.32#ibcon#about to read 3, iclass 22, count 0 2006.217.08:01:50.34#ibcon#read 3, iclass 22, count 0 2006.217.08:01:50.34#ibcon#about to read 4, iclass 22, count 0 2006.217.08:01:50.34#ibcon#read 4, iclass 22, count 0 2006.217.08:01:50.34#ibcon#about to read 5, iclass 22, count 0 2006.217.08:01:50.34#ibcon#read 5, iclass 22, count 0 2006.217.08:01:50.34#ibcon#about to read 6, iclass 22, count 0 2006.217.08:01:50.34#ibcon#read 6, iclass 22, count 0 2006.217.08:01:50.34#ibcon#end of sib2, iclass 22, count 0 2006.217.08:01:50.34#ibcon#*mode == 0, iclass 22, count 0 2006.217.08:01:50.34#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.217.08:01:50.34#ibcon#[25=USB\r\n] 2006.217.08:01:50.34#ibcon#*before write, iclass 22, count 0 2006.217.08:01:50.34#ibcon#enter sib2, iclass 22, count 0 2006.217.08:01:50.34#ibcon#flushed, iclass 22, count 0 2006.217.08:01:50.34#ibcon#about to write, iclass 22, count 0 2006.217.08:01:50.34#ibcon#wrote, iclass 22, count 0 2006.217.08:01:50.34#ibcon#about to read 3, iclass 22, count 0 2006.217.08:01:50.37#ibcon#read 3, iclass 22, count 0 2006.217.08:01:50.37#ibcon#about to read 4, iclass 22, count 0 2006.217.08:01:50.37#ibcon#read 4, iclass 22, count 0 2006.217.08:01:50.37#ibcon#about to read 5, iclass 22, count 0 2006.217.08:01:50.37#ibcon#read 5, iclass 22, count 0 2006.217.08:01:50.37#ibcon#about to read 6, iclass 22, count 0 2006.217.08:01:50.37#ibcon#read 6, iclass 22, count 0 2006.217.08:01:50.37#ibcon#end of sib2, iclass 22, count 0 2006.217.08:01:50.37#ibcon#*after write, iclass 22, count 0 2006.217.08:01:50.37#ibcon#*before return 0, iclass 22, count 0 2006.217.08:01:50.37#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.217.08:01:50.37#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.217.08:01:50.37#ibcon#about to clear, iclass 22 cls_cnt 0 2006.217.08:01:50.37#ibcon#cleared, iclass 22 cls_cnt 0 2006.217.08:01:50.37$vc4f8/valo=8,852.99 2006.217.08:01:50.37#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.217.08:01:50.37#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.217.08:01:50.37#ibcon#ireg 17 cls_cnt 0 2006.217.08:01:50.37#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.217.08:01:50.37#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.217.08:01:50.37#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.217.08:01:50.37#ibcon#enter wrdev, iclass 24, count 0 2006.217.08:01:50.37#ibcon#first serial, iclass 24, count 0 2006.217.08:01:50.37#ibcon#enter sib2, iclass 24, count 0 2006.217.08:01:50.37#ibcon#flushed, iclass 24, count 0 2006.217.08:01:50.37#ibcon#about to write, iclass 24, count 0 2006.217.08:01:50.37#ibcon#wrote, iclass 24, count 0 2006.217.08:01:50.37#ibcon#about to read 3, iclass 24, count 0 2006.217.08:01:50.39#ibcon#read 3, iclass 24, count 0 2006.217.08:01:50.39#ibcon#about to read 4, iclass 24, count 0 2006.217.08:01:50.39#ibcon#read 4, iclass 24, count 0 2006.217.08:01:50.39#ibcon#about to read 5, iclass 24, count 0 2006.217.08:01:50.39#ibcon#read 5, iclass 24, count 0 2006.217.08:01:50.39#ibcon#about to read 6, iclass 24, count 0 2006.217.08:01:50.39#ibcon#read 6, iclass 24, count 0 2006.217.08:01:50.39#ibcon#end of sib2, iclass 24, count 0 2006.217.08:01:50.39#ibcon#*mode == 0, iclass 24, count 0 2006.217.08:01:50.39#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.217.08:01:50.39#ibcon#[26=FRQ=08,852.99\r\n] 2006.217.08:01:50.39#ibcon#*before write, iclass 24, count 0 2006.217.08:01:50.39#ibcon#enter sib2, iclass 24, count 0 2006.217.08:01:50.39#ibcon#flushed, iclass 24, count 0 2006.217.08:01:50.39#ibcon#about to write, iclass 24, count 0 2006.217.08:01:50.39#ibcon#wrote, iclass 24, count 0 2006.217.08:01:50.39#ibcon#about to read 3, iclass 24, count 0 2006.217.08:01:50.43#ibcon#read 3, iclass 24, count 0 2006.217.08:01:50.43#ibcon#about to read 4, iclass 24, count 0 2006.217.08:01:50.43#ibcon#read 4, iclass 24, count 0 2006.217.08:01:50.43#ibcon#about to read 5, iclass 24, count 0 2006.217.08:01:50.43#ibcon#read 5, iclass 24, count 0 2006.217.08:01:50.43#ibcon#about to read 6, iclass 24, count 0 2006.217.08:01:50.43#ibcon#read 6, iclass 24, count 0 2006.217.08:01:50.43#ibcon#end of sib2, iclass 24, count 0 2006.217.08:01:50.43#ibcon#*after write, iclass 24, count 0 2006.217.08:01:50.43#ibcon#*before return 0, iclass 24, count 0 2006.217.08:01:50.43#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.217.08:01:50.43#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.217.08:01:50.43#ibcon#about to clear, iclass 24 cls_cnt 0 2006.217.08:01:50.43#ibcon#cleared, iclass 24 cls_cnt 0 2006.217.08:01:50.43$vc4f8/va=8,7 2006.217.08:01:50.43#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.217.08:01:50.43#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.217.08:01:50.43#ibcon#ireg 11 cls_cnt 2 2006.217.08:01:50.43#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.217.08:01:50.49#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.217.08:01:50.49#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.217.08:01:50.49#ibcon#enter wrdev, iclass 26, count 2 2006.217.08:01:50.49#ibcon#first serial, iclass 26, count 2 2006.217.08:01:50.49#ibcon#enter sib2, iclass 26, count 2 2006.217.08:01:50.49#ibcon#flushed, iclass 26, count 2 2006.217.08:01:50.49#ibcon#about to write, iclass 26, count 2 2006.217.08:01:50.49#ibcon#wrote, iclass 26, count 2 2006.217.08:01:50.49#ibcon#about to read 3, iclass 26, count 2 2006.217.08:01:50.51#ibcon#read 3, iclass 26, count 2 2006.217.08:01:50.51#ibcon#about to read 4, iclass 26, count 2 2006.217.08:01:50.51#ibcon#read 4, iclass 26, count 2 2006.217.08:01:50.51#ibcon#about to read 5, iclass 26, count 2 2006.217.08:01:50.51#ibcon#read 5, iclass 26, count 2 2006.217.08:01:50.51#ibcon#about to read 6, iclass 26, count 2 2006.217.08:01:50.51#ibcon#read 6, iclass 26, count 2 2006.217.08:01:50.51#ibcon#end of sib2, iclass 26, count 2 2006.217.08:01:50.51#ibcon#*mode == 0, iclass 26, count 2 2006.217.08:01:50.51#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.217.08:01:50.51#ibcon#[25=AT08-07\r\n] 2006.217.08:01:50.51#ibcon#*before write, iclass 26, count 2 2006.217.08:01:50.51#ibcon#enter sib2, iclass 26, count 2 2006.217.08:01:50.51#ibcon#flushed, iclass 26, count 2 2006.217.08:01:50.51#ibcon#about to write, iclass 26, count 2 2006.217.08:01:50.51#ibcon#wrote, iclass 26, count 2 2006.217.08:01:50.51#ibcon#about to read 3, iclass 26, count 2 2006.217.08:01:50.54#ibcon#read 3, iclass 26, count 2 2006.217.08:01:50.54#ibcon#about to read 4, iclass 26, count 2 2006.217.08:01:50.54#ibcon#read 4, iclass 26, count 2 2006.217.08:01:50.54#ibcon#about to read 5, iclass 26, count 2 2006.217.08:01:50.54#ibcon#read 5, iclass 26, count 2 2006.217.08:01:50.54#ibcon#about to read 6, iclass 26, count 2 2006.217.08:01:50.54#ibcon#read 6, iclass 26, count 2 2006.217.08:01:50.54#ibcon#end of sib2, iclass 26, count 2 2006.217.08:01:50.54#ibcon#*after write, iclass 26, count 2 2006.217.08:01:50.54#ibcon#*before return 0, iclass 26, count 2 2006.217.08:01:50.54#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.217.08:01:50.54#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.217.08:01:50.54#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.217.08:01:50.54#ibcon#ireg 7 cls_cnt 0 2006.217.08:01:50.54#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.217.08:01:50.66#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.217.08:01:50.66#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.217.08:01:50.66#ibcon#enter wrdev, iclass 26, count 0 2006.217.08:01:50.66#ibcon#first serial, iclass 26, count 0 2006.217.08:01:50.66#ibcon#enter sib2, iclass 26, count 0 2006.217.08:01:50.66#ibcon#flushed, iclass 26, count 0 2006.217.08:01:50.66#ibcon#about to write, iclass 26, count 0 2006.217.08:01:50.66#ibcon#wrote, iclass 26, count 0 2006.217.08:01:50.66#ibcon#about to read 3, iclass 26, count 0 2006.217.08:01:50.68#ibcon#read 3, iclass 26, count 0 2006.217.08:01:50.68#ibcon#about to read 4, iclass 26, count 0 2006.217.08:01:50.68#ibcon#read 4, iclass 26, count 0 2006.217.08:01:50.68#ibcon#about to read 5, iclass 26, count 0 2006.217.08:01:50.68#ibcon#read 5, iclass 26, count 0 2006.217.08:01:50.68#ibcon#about to read 6, iclass 26, count 0 2006.217.08:01:50.68#ibcon#read 6, iclass 26, count 0 2006.217.08:01:50.68#ibcon#end of sib2, iclass 26, count 0 2006.217.08:01:50.68#ibcon#*mode == 0, iclass 26, count 0 2006.217.08:01:50.68#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.217.08:01:50.68#ibcon#[25=USB\r\n] 2006.217.08:01:50.68#ibcon#*before write, iclass 26, count 0 2006.217.08:01:50.68#ibcon#enter sib2, iclass 26, count 0 2006.217.08:01:50.68#ibcon#flushed, iclass 26, count 0 2006.217.08:01:50.68#ibcon#about to write, iclass 26, count 0 2006.217.08:01:50.68#ibcon#wrote, iclass 26, count 0 2006.217.08:01:50.68#ibcon#about to read 3, iclass 26, count 0 2006.217.08:01:50.71#ibcon#read 3, iclass 26, count 0 2006.217.08:01:50.71#ibcon#about to read 4, iclass 26, count 0 2006.217.08:01:50.71#ibcon#read 4, iclass 26, count 0 2006.217.08:01:50.71#ibcon#about to read 5, iclass 26, count 0 2006.217.08:01:50.71#ibcon#read 5, iclass 26, count 0 2006.217.08:01:50.71#ibcon#about to read 6, iclass 26, count 0 2006.217.08:01:50.71#ibcon#read 6, iclass 26, count 0 2006.217.08:01:50.71#ibcon#end of sib2, iclass 26, count 0 2006.217.08:01:50.71#ibcon#*after write, iclass 26, count 0 2006.217.08:01:50.71#ibcon#*before return 0, iclass 26, count 0 2006.217.08:01:50.71#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.217.08:01:50.71#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.217.08:01:50.71#ibcon#about to clear, iclass 26 cls_cnt 0 2006.217.08:01:50.71#ibcon#cleared, iclass 26 cls_cnt 0 2006.217.08:01:50.71$vc4f8/vblo=1,632.99 2006.217.08:01:50.71#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.217.08:01:50.71#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.217.08:01:50.71#ibcon#ireg 17 cls_cnt 0 2006.217.08:01:50.71#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.217.08:01:50.71#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.217.08:01:50.71#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.217.08:01:50.71#ibcon#enter wrdev, iclass 28, count 0 2006.217.08:01:50.71#ibcon#first serial, iclass 28, count 0 2006.217.08:01:50.71#ibcon#enter sib2, iclass 28, count 0 2006.217.08:01:50.71#ibcon#flushed, iclass 28, count 0 2006.217.08:01:50.71#ibcon#about to write, iclass 28, count 0 2006.217.08:01:50.71#ibcon#wrote, iclass 28, count 0 2006.217.08:01:50.71#ibcon#about to read 3, iclass 28, count 0 2006.217.08:01:50.73#ibcon#read 3, iclass 28, count 0 2006.217.08:01:50.73#ibcon#about to read 4, iclass 28, count 0 2006.217.08:01:50.73#ibcon#read 4, iclass 28, count 0 2006.217.08:01:50.73#ibcon#about to read 5, iclass 28, count 0 2006.217.08:01:50.73#ibcon#read 5, iclass 28, count 0 2006.217.08:01:50.73#ibcon#about to read 6, iclass 28, count 0 2006.217.08:01:50.73#ibcon#read 6, iclass 28, count 0 2006.217.08:01:50.73#ibcon#end of sib2, iclass 28, count 0 2006.217.08:01:50.73#ibcon#*mode == 0, iclass 28, count 0 2006.217.08:01:50.73#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.217.08:01:50.73#ibcon#[28=FRQ=01,632.99\r\n] 2006.217.08:01:50.73#ibcon#*before write, iclass 28, count 0 2006.217.08:01:50.73#ibcon#enter sib2, iclass 28, count 0 2006.217.08:01:50.73#ibcon#flushed, iclass 28, count 0 2006.217.08:01:50.73#ibcon#about to write, iclass 28, count 0 2006.217.08:01:50.73#ibcon#wrote, iclass 28, count 0 2006.217.08:01:50.73#ibcon#about to read 3, iclass 28, count 0 2006.217.08:01:50.77#ibcon#read 3, iclass 28, count 0 2006.217.08:01:50.77#ibcon#about to read 4, iclass 28, count 0 2006.217.08:01:50.77#ibcon#read 4, iclass 28, count 0 2006.217.08:01:50.77#ibcon#about to read 5, iclass 28, count 0 2006.217.08:01:50.77#ibcon#read 5, iclass 28, count 0 2006.217.08:01:50.77#ibcon#about to read 6, iclass 28, count 0 2006.217.08:01:50.77#ibcon#read 6, iclass 28, count 0 2006.217.08:01:50.77#ibcon#end of sib2, iclass 28, count 0 2006.217.08:01:50.77#ibcon#*after write, iclass 28, count 0 2006.217.08:01:50.77#ibcon#*before return 0, iclass 28, count 0 2006.217.08:01:50.77#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.217.08:01:50.77#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.217.08:01:50.77#ibcon#about to clear, iclass 28 cls_cnt 0 2006.217.08:01:50.77#ibcon#cleared, iclass 28 cls_cnt 0 2006.217.08:01:50.77$vc4f8/vb=1,4 2006.217.08:01:50.77#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.217.08:01:50.77#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.217.08:01:50.77#ibcon#ireg 11 cls_cnt 2 2006.217.08:01:50.77#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.217.08:01:50.77#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.217.08:01:50.77#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.217.08:01:50.77#ibcon#enter wrdev, iclass 30, count 2 2006.217.08:01:50.77#ibcon#first serial, iclass 30, count 2 2006.217.08:01:50.77#ibcon#enter sib2, iclass 30, count 2 2006.217.08:01:50.77#ibcon#flushed, iclass 30, count 2 2006.217.08:01:50.77#ibcon#about to write, iclass 30, count 2 2006.217.08:01:50.77#ibcon#wrote, iclass 30, count 2 2006.217.08:01:50.77#ibcon#about to read 3, iclass 30, count 2 2006.217.08:01:50.79#ibcon#read 3, iclass 30, count 2 2006.217.08:01:50.79#ibcon#about to read 4, iclass 30, count 2 2006.217.08:01:50.79#ibcon#read 4, iclass 30, count 2 2006.217.08:01:50.79#ibcon#about to read 5, iclass 30, count 2 2006.217.08:01:50.79#ibcon#read 5, iclass 30, count 2 2006.217.08:01:50.79#ibcon#about to read 6, iclass 30, count 2 2006.217.08:01:50.79#ibcon#read 6, iclass 30, count 2 2006.217.08:01:50.79#ibcon#end of sib2, iclass 30, count 2 2006.217.08:01:50.79#ibcon#*mode == 0, iclass 30, count 2 2006.217.08:01:50.79#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.217.08:01:50.79#ibcon#[27=AT01-04\r\n] 2006.217.08:01:50.79#ibcon#*before write, iclass 30, count 2 2006.217.08:01:50.79#ibcon#enter sib2, iclass 30, count 2 2006.217.08:01:50.79#ibcon#flushed, iclass 30, count 2 2006.217.08:01:50.79#ibcon#about to write, iclass 30, count 2 2006.217.08:01:50.79#ibcon#wrote, iclass 30, count 2 2006.217.08:01:50.79#ibcon#about to read 3, iclass 30, count 2 2006.217.08:01:50.82#ibcon#read 3, iclass 30, count 2 2006.217.08:01:50.82#ibcon#about to read 4, iclass 30, count 2 2006.217.08:01:50.82#ibcon#read 4, iclass 30, count 2 2006.217.08:01:50.82#ibcon#about to read 5, iclass 30, count 2 2006.217.08:01:50.82#ibcon#read 5, iclass 30, count 2 2006.217.08:01:50.82#ibcon#about to read 6, iclass 30, count 2 2006.217.08:01:50.82#ibcon#read 6, iclass 30, count 2 2006.217.08:01:50.82#ibcon#end of sib2, iclass 30, count 2 2006.217.08:01:50.82#ibcon#*after write, iclass 30, count 2 2006.217.08:01:50.82#ibcon#*before return 0, iclass 30, count 2 2006.217.08:01:50.82#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.217.08:01:50.82#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.217.08:01:50.82#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.217.08:01:50.82#ibcon#ireg 7 cls_cnt 0 2006.217.08:01:50.82#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.217.08:01:50.94#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.217.08:01:50.94#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.217.08:01:50.94#ibcon#enter wrdev, iclass 30, count 0 2006.217.08:01:50.94#ibcon#first serial, iclass 30, count 0 2006.217.08:01:50.94#ibcon#enter sib2, iclass 30, count 0 2006.217.08:01:50.94#ibcon#flushed, iclass 30, count 0 2006.217.08:01:50.94#ibcon#about to write, iclass 30, count 0 2006.217.08:01:50.94#ibcon#wrote, iclass 30, count 0 2006.217.08:01:50.94#ibcon#about to read 3, iclass 30, count 0 2006.217.08:01:50.96#ibcon#read 3, iclass 30, count 0 2006.217.08:01:50.96#ibcon#about to read 4, iclass 30, count 0 2006.217.08:01:50.96#ibcon#read 4, iclass 30, count 0 2006.217.08:01:50.96#ibcon#about to read 5, iclass 30, count 0 2006.217.08:01:50.96#ibcon#read 5, iclass 30, count 0 2006.217.08:01:50.96#ibcon#about to read 6, iclass 30, count 0 2006.217.08:01:50.96#ibcon#read 6, iclass 30, count 0 2006.217.08:01:50.96#ibcon#end of sib2, iclass 30, count 0 2006.217.08:01:50.96#ibcon#*mode == 0, iclass 30, count 0 2006.217.08:01:50.96#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.217.08:01:50.96#ibcon#[27=USB\r\n] 2006.217.08:01:50.96#ibcon#*before write, iclass 30, count 0 2006.217.08:01:50.96#ibcon#enter sib2, iclass 30, count 0 2006.217.08:01:50.96#ibcon#flushed, iclass 30, count 0 2006.217.08:01:50.96#ibcon#about to write, iclass 30, count 0 2006.217.08:01:50.96#ibcon#wrote, iclass 30, count 0 2006.217.08:01:50.96#ibcon#about to read 3, iclass 30, count 0 2006.217.08:01:50.99#ibcon#read 3, iclass 30, count 0 2006.217.08:01:50.99#ibcon#about to read 4, iclass 30, count 0 2006.217.08:01:50.99#ibcon#read 4, iclass 30, count 0 2006.217.08:01:50.99#ibcon#about to read 5, iclass 30, count 0 2006.217.08:01:50.99#ibcon#read 5, iclass 30, count 0 2006.217.08:01:50.99#ibcon#about to read 6, iclass 30, count 0 2006.217.08:01:50.99#ibcon#read 6, iclass 30, count 0 2006.217.08:01:50.99#ibcon#end of sib2, iclass 30, count 0 2006.217.08:01:50.99#ibcon#*after write, iclass 30, count 0 2006.217.08:01:50.99#ibcon#*before return 0, iclass 30, count 0 2006.217.08:01:50.99#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.217.08:01:50.99#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.217.08:01:50.99#ibcon#about to clear, iclass 30 cls_cnt 0 2006.217.08:01:50.99#ibcon#cleared, iclass 30 cls_cnt 0 2006.217.08:01:50.99$vc4f8/vblo=2,640.99 2006.217.08:01:50.99#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.217.08:01:50.99#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.217.08:01:50.99#ibcon#ireg 17 cls_cnt 0 2006.217.08:01:50.99#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.217.08:01:50.99#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.217.08:01:50.99#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.217.08:01:50.99#ibcon#enter wrdev, iclass 32, count 0 2006.217.08:01:50.99#ibcon#first serial, iclass 32, count 0 2006.217.08:01:50.99#ibcon#enter sib2, iclass 32, count 0 2006.217.08:01:50.99#ibcon#flushed, iclass 32, count 0 2006.217.08:01:50.99#ibcon#about to write, iclass 32, count 0 2006.217.08:01:50.99#ibcon#wrote, iclass 32, count 0 2006.217.08:01:50.99#ibcon#about to read 3, iclass 32, count 0 2006.217.08:01:51.01#ibcon#read 3, iclass 32, count 0 2006.217.08:01:51.01#ibcon#about to read 4, iclass 32, count 0 2006.217.08:01:51.01#ibcon#read 4, iclass 32, count 0 2006.217.08:01:51.01#ibcon#about to read 5, iclass 32, count 0 2006.217.08:01:51.01#ibcon#read 5, iclass 32, count 0 2006.217.08:01:51.01#ibcon#about to read 6, iclass 32, count 0 2006.217.08:01:51.01#ibcon#read 6, iclass 32, count 0 2006.217.08:01:51.01#ibcon#end of sib2, iclass 32, count 0 2006.217.08:01:51.01#ibcon#*mode == 0, iclass 32, count 0 2006.217.08:01:51.01#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.217.08:01:51.01#ibcon#[28=FRQ=02,640.99\r\n] 2006.217.08:01:51.01#ibcon#*before write, iclass 32, count 0 2006.217.08:01:51.01#ibcon#enter sib2, iclass 32, count 0 2006.217.08:01:51.01#ibcon#flushed, iclass 32, count 0 2006.217.08:01:51.01#ibcon#about to write, iclass 32, count 0 2006.217.08:01:51.01#ibcon#wrote, iclass 32, count 0 2006.217.08:01:51.01#ibcon#about to read 3, iclass 32, count 0 2006.217.08:01:51.05#ibcon#read 3, iclass 32, count 0 2006.217.08:01:51.05#ibcon#about to read 4, iclass 32, count 0 2006.217.08:01:51.05#ibcon#read 4, iclass 32, count 0 2006.217.08:01:51.05#ibcon#about to read 5, iclass 32, count 0 2006.217.08:01:51.05#ibcon#read 5, iclass 32, count 0 2006.217.08:01:51.05#ibcon#about to read 6, iclass 32, count 0 2006.217.08:01:51.05#ibcon#read 6, iclass 32, count 0 2006.217.08:01:51.05#ibcon#end of sib2, iclass 32, count 0 2006.217.08:01:51.05#ibcon#*after write, iclass 32, count 0 2006.217.08:01:51.05#ibcon#*before return 0, iclass 32, count 0 2006.217.08:01:51.05#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.217.08:01:51.05#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.217.08:01:51.05#ibcon#about to clear, iclass 32 cls_cnt 0 2006.217.08:01:51.05#ibcon#cleared, iclass 32 cls_cnt 0 2006.217.08:01:51.05$vc4f8/vb=2,4 2006.217.08:01:51.05#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.217.08:01:51.05#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.217.08:01:51.05#ibcon#ireg 11 cls_cnt 2 2006.217.08:01:51.05#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.217.08:01:51.11#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.217.08:01:51.11#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.217.08:01:51.11#ibcon#enter wrdev, iclass 34, count 2 2006.217.08:01:51.11#ibcon#first serial, iclass 34, count 2 2006.217.08:01:51.11#ibcon#enter sib2, iclass 34, count 2 2006.217.08:01:51.11#ibcon#flushed, iclass 34, count 2 2006.217.08:01:51.11#ibcon#about to write, iclass 34, count 2 2006.217.08:01:51.11#ibcon#wrote, iclass 34, count 2 2006.217.08:01:51.11#ibcon#about to read 3, iclass 34, count 2 2006.217.08:01:51.13#ibcon#read 3, iclass 34, count 2 2006.217.08:01:51.13#ibcon#about to read 4, iclass 34, count 2 2006.217.08:01:51.13#ibcon#read 4, iclass 34, count 2 2006.217.08:01:51.13#ibcon#about to read 5, iclass 34, count 2 2006.217.08:01:51.13#ibcon#read 5, iclass 34, count 2 2006.217.08:01:51.13#ibcon#about to read 6, iclass 34, count 2 2006.217.08:01:51.13#ibcon#read 6, iclass 34, count 2 2006.217.08:01:51.13#ibcon#end of sib2, iclass 34, count 2 2006.217.08:01:51.13#ibcon#*mode == 0, iclass 34, count 2 2006.217.08:01:51.13#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.217.08:01:51.13#ibcon#[27=AT02-04\r\n] 2006.217.08:01:51.13#ibcon#*before write, iclass 34, count 2 2006.217.08:01:51.13#ibcon#enter sib2, iclass 34, count 2 2006.217.08:01:51.13#ibcon#flushed, iclass 34, count 2 2006.217.08:01:51.13#ibcon#about to write, iclass 34, count 2 2006.217.08:01:51.13#ibcon#wrote, iclass 34, count 2 2006.217.08:01:51.13#ibcon#about to read 3, iclass 34, count 2 2006.217.08:01:51.16#ibcon#read 3, iclass 34, count 2 2006.217.08:01:51.16#ibcon#about to read 4, iclass 34, count 2 2006.217.08:01:51.16#ibcon#read 4, iclass 34, count 2 2006.217.08:01:51.16#ibcon#about to read 5, iclass 34, count 2 2006.217.08:01:51.16#ibcon#read 5, iclass 34, count 2 2006.217.08:01:51.16#ibcon#about to read 6, iclass 34, count 2 2006.217.08:01:51.16#ibcon#read 6, iclass 34, count 2 2006.217.08:01:51.16#ibcon#end of sib2, iclass 34, count 2 2006.217.08:01:51.16#ibcon#*after write, iclass 34, count 2 2006.217.08:01:51.16#ibcon#*before return 0, iclass 34, count 2 2006.217.08:01:51.16#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.217.08:01:51.16#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.217.08:01:51.16#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.217.08:01:51.16#ibcon#ireg 7 cls_cnt 0 2006.217.08:01:51.16#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.217.08:01:51.28#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.217.08:01:51.28#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.217.08:01:51.28#ibcon#enter wrdev, iclass 34, count 0 2006.217.08:01:51.28#ibcon#first serial, iclass 34, count 0 2006.217.08:01:51.28#ibcon#enter sib2, iclass 34, count 0 2006.217.08:01:51.28#ibcon#flushed, iclass 34, count 0 2006.217.08:01:51.28#ibcon#about to write, iclass 34, count 0 2006.217.08:01:51.28#ibcon#wrote, iclass 34, count 0 2006.217.08:01:51.28#ibcon#about to read 3, iclass 34, count 0 2006.217.08:01:51.30#ibcon#read 3, iclass 34, count 0 2006.217.08:01:51.30#ibcon#about to read 4, iclass 34, count 0 2006.217.08:01:51.30#ibcon#read 4, iclass 34, count 0 2006.217.08:01:51.30#ibcon#about to read 5, iclass 34, count 0 2006.217.08:01:51.30#ibcon#read 5, iclass 34, count 0 2006.217.08:01:51.30#ibcon#about to read 6, iclass 34, count 0 2006.217.08:01:51.30#ibcon#read 6, iclass 34, count 0 2006.217.08:01:51.30#ibcon#end of sib2, iclass 34, count 0 2006.217.08:01:51.30#ibcon#*mode == 0, iclass 34, count 0 2006.217.08:01:51.30#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.217.08:01:51.30#ibcon#[27=USB\r\n] 2006.217.08:01:51.30#ibcon#*before write, iclass 34, count 0 2006.217.08:01:51.30#ibcon#enter sib2, iclass 34, count 0 2006.217.08:01:51.30#ibcon#flushed, iclass 34, count 0 2006.217.08:01:51.30#ibcon#about to write, iclass 34, count 0 2006.217.08:01:51.30#ibcon#wrote, iclass 34, count 0 2006.217.08:01:51.30#ibcon#about to read 3, iclass 34, count 0 2006.217.08:01:51.33#ibcon#read 3, iclass 34, count 0 2006.217.08:01:51.33#ibcon#about to read 4, iclass 34, count 0 2006.217.08:01:51.33#ibcon#read 4, iclass 34, count 0 2006.217.08:01:51.33#ibcon#about to read 5, iclass 34, count 0 2006.217.08:01:51.33#ibcon#read 5, iclass 34, count 0 2006.217.08:01:51.33#ibcon#about to read 6, iclass 34, count 0 2006.217.08:01:51.33#ibcon#read 6, iclass 34, count 0 2006.217.08:01:51.33#ibcon#end of sib2, iclass 34, count 0 2006.217.08:01:51.33#ibcon#*after write, iclass 34, count 0 2006.217.08:01:51.33#ibcon#*before return 0, iclass 34, count 0 2006.217.08:01:51.33#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.217.08:01:51.33#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.217.08:01:51.33#ibcon#about to clear, iclass 34 cls_cnt 0 2006.217.08:01:51.33#ibcon#cleared, iclass 34 cls_cnt 0 2006.217.08:01:51.33$vc4f8/vblo=3,656.99 2006.217.08:01:51.33#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.217.08:01:51.33#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.217.08:01:51.33#ibcon#ireg 17 cls_cnt 0 2006.217.08:01:51.33#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.217.08:01:51.33#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.217.08:01:51.33#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.217.08:01:51.33#ibcon#enter wrdev, iclass 36, count 0 2006.217.08:01:51.33#ibcon#first serial, iclass 36, count 0 2006.217.08:01:51.33#ibcon#enter sib2, iclass 36, count 0 2006.217.08:01:51.33#ibcon#flushed, iclass 36, count 0 2006.217.08:01:51.33#ibcon#about to write, iclass 36, count 0 2006.217.08:01:51.33#ibcon#wrote, iclass 36, count 0 2006.217.08:01:51.33#ibcon#about to read 3, iclass 36, count 0 2006.217.08:01:51.36#ibcon#read 3, iclass 36, count 0 2006.217.08:01:51.36#ibcon#about to read 4, iclass 36, count 0 2006.217.08:01:51.36#ibcon#read 4, iclass 36, count 0 2006.217.08:01:51.36#ibcon#about to read 5, iclass 36, count 0 2006.217.08:01:51.36#ibcon#read 5, iclass 36, count 0 2006.217.08:01:51.36#ibcon#about to read 6, iclass 36, count 0 2006.217.08:01:51.36#ibcon#read 6, iclass 36, count 0 2006.217.08:01:51.36#ibcon#end of sib2, iclass 36, count 0 2006.217.08:01:51.36#ibcon#*mode == 0, iclass 36, count 0 2006.217.08:01:51.36#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.217.08:01:51.36#ibcon#[28=FRQ=03,656.99\r\n] 2006.217.08:01:51.36#ibcon#*before write, iclass 36, count 0 2006.217.08:01:51.36#ibcon#enter sib2, iclass 36, count 0 2006.217.08:01:51.36#ibcon#flushed, iclass 36, count 0 2006.217.08:01:51.36#ibcon#about to write, iclass 36, count 0 2006.217.08:01:51.36#ibcon#wrote, iclass 36, count 0 2006.217.08:01:51.36#ibcon#about to read 3, iclass 36, count 0 2006.217.08:01:51.40#ibcon#read 3, iclass 36, count 0 2006.217.08:01:51.40#ibcon#about to read 4, iclass 36, count 0 2006.217.08:01:51.40#ibcon#read 4, iclass 36, count 0 2006.217.08:01:51.40#ibcon#about to read 5, iclass 36, count 0 2006.217.08:01:51.40#ibcon#read 5, iclass 36, count 0 2006.217.08:01:51.40#ibcon#about to read 6, iclass 36, count 0 2006.217.08:01:51.40#ibcon#read 6, iclass 36, count 0 2006.217.08:01:51.40#ibcon#end of sib2, iclass 36, count 0 2006.217.08:01:51.40#ibcon#*after write, iclass 36, count 0 2006.217.08:01:51.40#ibcon#*before return 0, iclass 36, count 0 2006.217.08:01:51.40#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.217.08:01:51.40#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.217.08:01:51.40#ibcon#about to clear, iclass 36 cls_cnt 0 2006.217.08:01:51.40#ibcon#cleared, iclass 36 cls_cnt 0 2006.217.08:01:51.40$vc4f8/vb=3,4 2006.217.08:01:51.40#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.217.08:01:51.40#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.217.08:01:51.40#ibcon#ireg 11 cls_cnt 2 2006.217.08:01:51.40#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.217.08:01:51.45#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.217.08:01:51.45#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.217.08:01:51.45#ibcon#enter wrdev, iclass 38, count 2 2006.217.08:01:51.45#ibcon#first serial, iclass 38, count 2 2006.217.08:01:51.45#ibcon#enter sib2, iclass 38, count 2 2006.217.08:01:51.45#ibcon#flushed, iclass 38, count 2 2006.217.08:01:51.45#ibcon#about to write, iclass 38, count 2 2006.217.08:01:51.45#ibcon#wrote, iclass 38, count 2 2006.217.08:01:51.45#ibcon#about to read 3, iclass 38, count 2 2006.217.08:01:51.47#ibcon#read 3, iclass 38, count 2 2006.217.08:01:51.47#ibcon#about to read 4, iclass 38, count 2 2006.217.08:01:51.47#ibcon#read 4, iclass 38, count 2 2006.217.08:01:51.47#ibcon#about to read 5, iclass 38, count 2 2006.217.08:01:51.47#ibcon#read 5, iclass 38, count 2 2006.217.08:01:51.47#ibcon#about to read 6, iclass 38, count 2 2006.217.08:01:51.47#ibcon#read 6, iclass 38, count 2 2006.217.08:01:51.47#ibcon#end of sib2, iclass 38, count 2 2006.217.08:01:51.47#ibcon#*mode == 0, iclass 38, count 2 2006.217.08:01:51.47#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.217.08:01:51.47#ibcon#[27=AT03-04\r\n] 2006.217.08:01:51.47#ibcon#*before write, iclass 38, count 2 2006.217.08:01:51.47#ibcon#enter sib2, iclass 38, count 2 2006.217.08:01:51.47#ibcon#flushed, iclass 38, count 2 2006.217.08:01:51.47#ibcon#about to write, iclass 38, count 2 2006.217.08:01:51.47#ibcon#wrote, iclass 38, count 2 2006.217.08:01:51.47#ibcon#about to read 3, iclass 38, count 2 2006.217.08:01:51.50#ibcon#read 3, iclass 38, count 2 2006.217.08:01:51.50#ibcon#about to read 4, iclass 38, count 2 2006.217.08:01:51.50#ibcon#read 4, iclass 38, count 2 2006.217.08:01:51.50#ibcon#about to read 5, iclass 38, count 2 2006.217.08:01:51.50#ibcon#read 5, iclass 38, count 2 2006.217.08:01:51.50#ibcon#about to read 6, iclass 38, count 2 2006.217.08:01:51.50#ibcon#read 6, iclass 38, count 2 2006.217.08:01:51.50#ibcon#end of sib2, iclass 38, count 2 2006.217.08:01:51.50#ibcon#*after write, iclass 38, count 2 2006.217.08:01:51.50#ibcon#*before return 0, iclass 38, count 2 2006.217.08:01:51.50#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.217.08:01:51.50#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.217.08:01:51.50#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.217.08:01:51.50#ibcon#ireg 7 cls_cnt 0 2006.217.08:01:51.50#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.217.08:01:51.62#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.217.08:01:51.62#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.217.08:01:51.62#ibcon#enter wrdev, iclass 38, count 0 2006.217.08:01:51.62#ibcon#first serial, iclass 38, count 0 2006.217.08:01:51.62#ibcon#enter sib2, iclass 38, count 0 2006.217.08:01:51.62#ibcon#flushed, iclass 38, count 0 2006.217.08:01:51.62#ibcon#about to write, iclass 38, count 0 2006.217.08:01:51.62#ibcon#wrote, iclass 38, count 0 2006.217.08:01:51.62#ibcon#about to read 3, iclass 38, count 0 2006.217.08:01:51.64#ibcon#read 3, iclass 38, count 0 2006.217.08:01:51.64#ibcon#about to read 4, iclass 38, count 0 2006.217.08:01:51.64#ibcon#read 4, iclass 38, count 0 2006.217.08:01:51.64#ibcon#about to read 5, iclass 38, count 0 2006.217.08:01:51.64#ibcon#read 5, iclass 38, count 0 2006.217.08:01:51.64#ibcon#about to read 6, iclass 38, count 0 2006.217.08:01:51.64#ibcon#read 6, iclass 38, count 0 2006.217.08:01:51.64#ibcon#end of sib2, iclass 38, count 0 2006.217.08:01:51.64#ibcon#*mode == 0, iclass 38, count 0 2006.217.08:01:51.64#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.217.08:01:51.64#ibcon#[27=USB\r\n] 2006.217.08:01:51.64#ibcon#*before write, iclass 38, count 0 2006.217.08:01:51.64#ibcon#enter sib2, iclass 38, count 0 2006.217.08:01:51.64#ibcon#flushed, iclass 38, count 0 2006.217.08:01:51.64#ibcon#about to write, iclass 38, count 0 2006.217.08:01:51.64#ibcon#wrote, iclass 38, count 0 2006.217.08:01:51.64#ibcon#about to read 3, iclass 38, count 0 2006.217.08:01:51.67#ibcon#read 3, iclass 38, count 0 2006.217.08:01:51.67#ibcon#about to read 4, iclass 38, count 0 2006.217.08:01:51.67#ibcon#read 4, iclass 38, count 0 2006.217.08:01:51.67#ibcon#about to read 5, iclass 38, count 0 2006.217.08:01:51.67#ibcon#read 5, iclass 38, count 0 2006.217.08:01:51.67#ibcon#about to read 6, iclass 38, count 0 2006.217.08:01:51.67#ibcon#read 6, iclass 38, count 0 2006.217.08:01:51.67#ibcon#end of sib2, iclass 38, count 0 2006.217.08:01:51.67#ibcon#*after write, iclass 38, count 0 2006.217.08:01:51.67#ibcon#*before return 0, iclass 38, count 0 2006.217.08:01:51.67#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.217.08:01:51.67#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.217.08:01:51.67#ibcon#about to clear, iclass 38 cls_cnt 0 2006.217.08:01:51.67#ibcon#cleared, iclass 38 cls_cnt 0 2006.217.08:01:51.67$vc4f8/vblo=4,712.99 2006.217.08:01:51.67#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.217.08:01:51.67#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.217.08:01:51.67#ibcon#ireg 17 cls_cnt 0 2006.217.08:01:51.67#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.217.08:01:51.67#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.217.08:01:51.67#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.217.08:01:51.67#ibcon#enter wrdev, iclass 40, count 0 2006.217.08:01:51.67#ibcon#first serial, iclass 40, count 0 2006.217.08:01:51.67#ibcon#enter sib2, iclass 40, count 0 2006.217.08:01:51.67#ibcon#flushed, iclass 40, count 0 2006.217.08:01:51.67#ibcon#about to write, iclass 40, count 0 2006.217.08:01:51.67#ibcon#wrote, iclass 40, count 0 2006.217.08:01:51.67#ibcon#about to read 3, iclass 40, count 0 2006.217.08:01:51.69#ibcon#read 3, iclass 40, count 0 2006.217.08:01:51.69#ibcon#about to read 4, iclass 40, count 0 2006.217.08:01:51.69#ibcon#read 4, iclass 40, count 0 2006.217.08:01:51.69#ibcon#about to read 5, iclass 40, count 0 2006.217.08:01:51.69#ibcon#read 5, iclass 40, count 0 2006.217.08:01:51.69#ibcon#about to read 6, iclass 40, count 0 2006.217.08:01:51.69#ibcon#read 6, iclass 40, count 0 2006.217.08:01:51.69#ibcon#end of sib2, iclass 40, count 0 2006.217.08:01:51.69#ibcon#*mode == 0, iclass 40, count 0 2006.217.08:01:51.69#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.217.08:01:51.69#ibcon#[28=FRQ=04,712.99\r\n] 2006.217.08:01:51.69#ibcon#*before write, iclass 40, count 0 2006.217.08:01:51.69#ibcon#enter sib2, iclass 40, count 0 2006.217.08:01:51.69#ibcon#flushed, iclass 40, count 0 2006.217.08:01:51.69#ibcon#about to write, iclass 40, count 0 2006.217.08:01:51.69#ibcon#wrote, iclass 40, count 0 2006.217.08:01:51.69#ibcon#about to read 3, iclass 40, count 0 2006.217.08:01:51.73#ibcon#read 3, iclass 40, count 0 2006.217.08:01:51.73#ibcon#about to read 4, iclass 40, count 0 2006.217.08:01:51.73#ibcon#read 4, iclass 40, count 0 2006.217.08:01:51.73#ibcon#about to read 5, iclass 40, count 0 2006.217.08:01:51.73#ibcon#read 5, iclass 40, count 0 2006.217.08:01:51.73#ibcon#about to read 6, iclass 40, count 0 2006.217.08:01:51.73#ibcon#read 6, iclass 40, count 0 2006.217.08:01:51.73#ibcon#end of sib2, iclass 40, count 0 2006.217.08:01:51.73#ibcon#*after write, iclass 40, count 0 2006.217.08:01:51.73#ibcon#*before return 0, iclass 40, count 0 2006.217.08:01:51.73#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.217.08:01:51.73#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.217.08:01:51.73#ibcon#about to clear, iclass 40 cls_cnt 0 2006.217.08:01:51.73#ibcon#cleared, iclass 40 cls_cnt 0 2006.217.08:01:51.73$vc4f8/vb=4,4 2006.217.08:01:51.73#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.217.08:01:51.73#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.217.08:01:51.73#ibcon#ireg 11 cls_cnt 2 2006.217.08:01:51.73#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.217.08:01:51.79#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.217.08:01:51.79#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.217.08:01:51.79#ibcon#enter wrdev, iclass 4, count 2 2006.217.08:01:51.79#ibcon#first serial, iclass 4, count 2 2006.217.08:01:51.79#ibcon#enter sib2, iclass 4, count 2 2006.217.08:01:51.79#ibcon#flushed, iclass 4, count 2 2006.217.08:01:51.79#ibcon#about to write, iclass 4, count 2 2006.217.08:01:51.79#ibcon#wrote, iclass 4, count 2 2006.217.08:01:51.79#ibcon#about to read 3, iclass 4, count 2 2006.217.08:01:51.81#ibcon#read 3, iclass 4, count 2 2006.217.08:01:51.81#ibcon#about to read 4, iclass 4, count 2 2006.217.08:01:51.81#ibcon#read 4, iclass 4, count 2 2006.217.08:01:51.81#ibcon#about to read 5, iclass 4, count 2 2006.217.08:01:51.81#ibcon#read 5, iclass 4, count 2 2006.217.08:01:51.81#ibcon#about to read 6, iclass 4, count 2 2006.217.08:01:51.81#ibcon#read 6, iclass 4, count 2 2006.217.08:01:51.81#ibcon#end of sib2, iclass 4, count 2 2006.217.08:01:51.81#ibcon#*mode == 0, iclass 4, count 2 2006.217.08:01:51.81#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.217.08:01:51.81#ibcon#[27=AT04-04\r\n] 2006.217.08:01:51.81#ibcon#*before write, iclass 4, count 2 2006.217.08:01:51.81#ibcon#enter sib2, iclass 4, count 2 2006.217.08:01:51.81#ibcon#flushed, iclass 4, count 2 2006.217.08:01:51.81#ibcon#about to write, iclass 4, count 2 2006.217.08:01:51.81#ibcon#wrote, iclass 4, count 2 2006.217.08:01:51.81#ibcon#about to read 3, iclass 4, count 2 2006.217.08:01:51.84#ibcon#read 3, iclass 4, count 2 2006.217.08:01:51.84#ibcon#about to read 4, iclass 4, count 2 2006.217.08:01:51.84#ibcon#read 4, iclass 4, count 2 2006.217.08:01:51.84#ibcon#about to read 5, iclass 4, count 2 2006.217.08:01:51.84#ibcon#read 5, iclass 4, count 2 2006.217.08:01:51.84#ibcon#about to read 6, iclass 4, count 2 2006.217.08:01:51.84#ibcon#read 6, iclass 4, count 2 2006.217.08:01:51.84#ibcon#end of sib2, iclass 4, count 2 2006.217.08:01:51.84#ibcon#*after write, iclass 4, count 2 2006.217.08:01:51.84#ibcon#*before return 0, iclass 4, count 2 2006.217.08:01:51.84#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.217.08:01:51.84#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.217.08:01:51.84#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.217.08:01:51.84#ibcon#ireg 7 cls_cnt 0 2006.217.08:01:51.84#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.217.08:01:51.96#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.217.08:01:51.96#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.217.08:01:51.96#ibcon#enter wrdev, iclass 4, count 0 2006.217.08:01:51.96#ibcon#first serial, iclass 4, count 0 2006.217.08:01:51.96#ibcon#enter sib2, iclass 4, count 0 2006.217.08:01:51.96#ibcon#flushed, iclass 4, count 0 2006.217.08:01:51.96#ibcon#about to write, iclass 4, count 0 2006.217.08:01:51.96#ibcon#wrote, iclass 4, count 0 2006.217.08:01:51.96#ibcon#about to read 3, iclass 4, count 0 2006.217.08:01:51.98#ibcon#read 3, iclass 4, count 0 2006.217.08:01:51.98#ibcon#about to read 4, iclass 4, count 0 2006.217.08:01:51.98#ibcon#read 4, iclass 4, count 0 2006.217.08:01:51.98#ibcon#about to read 5, iclass 4, count 0 2006.217.08:01:51.98#ibcon#read 5, iclass 4, count 0 2006.217.08:01:51.98#ibcon#about to read 6, iclass 4, count 0 2006.217.08:01:51.98#ibcon#read 6, iclass 4, count 0 2006.217.08:01:51.98#ibcon#end of sib2, iclass 4, count 0 2006.217.08:01:51.98#ibcon#*mode == 0, iclass 4, count 0 2006.217.08:01:51.98#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.217.08:01:51.98#ibcon#[27=USB\r\n] 2006.217.08:01:51.98#ibcon#*before write, iclass 4, count 0 2006.217.08:01:51.98#ibcon#enter sib2, iclass 4, count 0 2006.217.08:01:51.98#ibcon#flushed, iclass 4, count 0 2006.217.08:01:51.98#ibcon#about to write, iclass 4, count 0 2006.217.08:01:51.98#ibcon#wrote, iclass 4, count 0 2006.217.08:01:51.98#ibcon#about to read 3, iclass 4, count 0 2006.217.08:01:52.01#ibcon#read 3, iclass 4, count 0 2006.217.08:01:52.01#ibcon#about to read 4, iclass 4, count 0 2006.217.08:01:52.01#ibcon#read 4, iclass 4, count 0 2006.217.08:01:52.01#ibcon#about to read 5, iclass 4, count 0 2006.217.08:01:52.01#ibcon#read 5, iclass 4, count 0 2006.217.08:01:52.01#ibcon#about to read 6, iclass 4, count 0 2006.217.08:01:52.01#ibcon#read 6, iclass 4, count 0 2006.217.08:01:52.01#ibcon#end of sib2, iclass 4, count 0 2006.217.08:01:52.01#ibcon#*after write, iclass 4, count 0 2006.217.08:01:52.01#ibcon#*before return 0, iclass 4, count 0 2006.217.08:01:52.01#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.217.08:01:52.01#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.217.08:01:52.01#ibcon#about to clear, iclass 4 cls_cnt 0 2006.217.08:01:52.01#ibcon#cleared, iclass 4 cls_cnt 0 2006.217.08:01:52.01$vc4f8/vblo=5,744.99 2006.217.08:01:52.01#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.217.08:01:52.01#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.217.08:01:52.01#ibcon#ireg 17 cls_cnt 0 2006.217.08:01:52.01#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.217.08:01:52.01#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.217.08:01:52.01#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.217.08:01:52.01#ibcon#enter wrdev, iclass 6, count 0 2006.217.08:01:52.01#ibcon#first serial, iclass 6, count 0 2006.217.08:01:52.01#ibcon#enter sib2, iclass 6, count 0 2006.217.08:01:52.01#ibcon#flushed, iclass 6, count 0 2006.217.08:01:52.01#ibcon#about to write, iclass 6, count 0 2006.217.08:01:52.01#ibcon#wrote, iclass 6, count 0 2006.217.08:01:52.01#ibcon#about to read 3, iclass 6, count 0 2006.217.08:01:52.04#ibcon#read 3, iclass 6, count 0 2006.217.08:01:52.04#ibcon#about to read 4, iclass 6, count 0 2006.217.08:01:52.04#ibcon#read 4, iclass 6, count 0 2006.217.08:01:52.04#ibcon#about to read 5, iclass 6, count 0 2006.217.08:01:52.04#ibcon#read 5, iclass 6, count 0 2006.217.08:01:52.04#ibcon#about to read 6, iclass 6, count 0 2006.217.08:01:52.04#ibcon#read 6, iclass 6, count 0 2006.217.08:01:52.04#ibcon#end of sib2, iclass 6, count 0 2006.217.08:01:52.04#ibcon#*mode == 0, iclass 6, count 0 2006.217.08:01:52.04#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.217.08:01:52.04#ibcon#[28=FRQ=05,744.99\r\n] 2006.217.08:01:52.04#ibcon#*before write, iclass 6, count 0 2006.217.08:01:52.04#ibcon#enter sib2, iclass 6, count 0 2006.217.08:01:52.04#ibcon#flushed, iclass 6, count 0 2006.217.08:01:52.04#ibcon#about to write, iclass 6, count 0 2006.217.08:01:52.04#ibcon#wrote, iclass 6, count 0 2006.217.08:01:52.04#ibcon#about to read 3, iclass 6, count 0 2006.217.08:01:52.08#ibcon#read 3, iclass 6, count 0 2006.217.08:01:52.08#ibcon#about to read 4, iclass 6, count 0 2006.217.08:01:52.08#ibcon#read 4, iclass 6, count 0 2006.217.08:01:52.08#ibcon#about to read 5, iclass 6, count 0 2006.217.08:01:52.08#ibcon#read 5, iclass 6, count 0 2006.217.08:01:52.08#ibcon#about to read 6, iclass 6, count 0 2006.217.08:01:52.08#ibcon#read 6, iclass 6, count 0 2006.217.08:01:52.08#ibcon#end of sib2, iclass 6, count 0 2006.217.08:01:52.08#ibcon#*after write, iclass 6, count 0 2006.217.08:01:52.08#ibcon#*before return 0, iclass 6, count 0 2006.217.08:01:52.08#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.217.08:01:52.08#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.217.08:01:52.08#ibcon#about to clear, iclass 6 cls_cnt 0 2006.217.08:01:52.08#ibcon#cleared, iclass 6 cls_cnt 0 2006.217.08:01:52.08$vc4f8/vb=5,4 2006.217.08:01:52.08#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.217.08:01:52.08#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.217.08:01:52.08#ibcon#ireg 11 cls_cnt 2 2006.217.08:01:52.08#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.217.08:01:52.13#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.217.08:01:52.13#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.217.08:01:52.13#ibcon#enter wrdev, iclass 10, count 2 2006.217.08:01:52.13#ibcon#first serial, iclass 10, count 2 2006.217.08:01:52.13#ibcon#enter sib2, iclass 10, count 2 2006.217.08:01:52.13#ibcon#flushed, iclass 10, count 2 2006.217.08:01:52.13#ibcon#about to write, iclass 10, count 2 2006.217.08:01:52.13#ibcon#wrote, iclass 10, count 2 2006.217.08:01:52.13#ibcon#about to read 3, iclass 10, count 2 2006.217.08:01:52.15#ibcon#read 3, iclass 10, count 2 2006.217.08:01:52.15#ibcon#about to read 4, iclass 10, count 2 2006.217.08:01:52.15#ibcon#read 4, iclass 10, count 2 2006.217.08:01:52.15#ibcon#about to read 5, iclass 10, count 2 2006.217.08:01:52.15#ibcon#read 5, iclass 10, count 2 2006.217.08:01:52.15#ibcon#about to read 6, iclass 10, count 2 2006.217.08:01:52.15#ibcon#read 6, iclass 10, count 2 2006.217.08:01:52.15#ibcon#end of sib2, iclass 10, count 2 2006.217.08:01:52.15#ibcon#*mode == 0, iclass 10, count 2 2006.217.08:01:52.15#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.217.08:01:52.15#ibcon#[27=AT05-04\r\n] 2006.217.08:01:52.15#ibcon#*before write, iclass 10, count 2 2006.217.08:01:52.15#ibcon#enter sib2, iclass 10, count 2 2006.217.08:01:52.15#ibcon#flushed, iclass 10, count 2 2006.217.08:01:52.15#ibcon#about to write, iclass 10, count 2 2006.217.08:01:52.15#ibcon#wrote, iclass 10, count 2 2006.217.08:01:52.15#ibcon#about to read 3, iclass 10, count 2 2006.217.08:01:52.18#ibcon#read 3, iclass 10, count 2 2006.217.08:01:52.18#ibcon#about to read 4, iclass 10, count 2 2006.217.08:01:52.18#ibcon#read 4, iclass 10, count 2 2006.217.08:01:52.18#ibcon#about to read 5, iclass 10, count 2 2006.217.08:01:52.18#ibcon#read 5, iclass 10, count 2 2006.217.08:01:52.18#ibcon#about to read 6, iclass 10, count 2 2006.217.08:01:52.18#ibcon#read 6, iclass 10, count 2 2006.217.08:01:52.18#ibcon#end of sib2, iclass 10, count 2 2006.217.08:01:52.18#ibcon#*after write, iclass 10, count 2 2006.217.08:01:52.18#ibcon#*before return 0, iclass 10, count 2 2006.217.08:01:52.18#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.217.08:01:52.18#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.217.08:01:52.18#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.217.08:01:52.18#ibcon#ireg 7 cls_cnt 0 2006.217.08:01:52.18#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.217.08:01:52.30#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.217.08:01:52.30#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.217.08:01:52.30#ibcon#enter wrdev, iclass 10, count 0 2006.217.08:01:52.30#ibcon#first serial, iclass 10, count 0 2006.217.08:01:52.30#ibcon#enter sib2, iclass 10, count 0 2006.217.08:01:52.30#ibcon#flushed, iclass 10, count 0 2006.217.08:01:52.30#ibcon#about to write, iclass 10, count 0 2006.217.08:01:52.30#ibcon#wrote, iclass 10, count 0 2006.217.08:01:52.30#ibcon#about to read 3, iclass 10, count 0 2006.217.08:01:52.32#ibcon#read 3, iclass 10, count 0 2006.217.08:01:52.32#ibcon#about to read 4, iclass 10, count 0 2006.217.08:01:52.32#ibcon#read 4, iclass 10, count 0 2006.217.08:01:52.32#ibcon#about to read 5, iclass 10, count 0 2006.217.08:01:52.32#ibcon#read 5, iclass 10, count 0 2006.217.08:01:52.32#ibcon#about to read 6, iclass 10, count 0 2006.217.08:01:52.32#ibcon#read 6, iclass 10, count 0 2006.217.08:01:52.32#ibcon#end of sib2, iclass 10, count 0 2006.217.08:01:52.32#ibcon#*mode == 0, iclass 10, count 0 2006.217.08:01:52.32#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.217.08:01:52.32#ibcon#[27=USB\r\n] 2006.217.08:01:52.32#ibcon#*before write, iclass 10, count 0 2006.217.08:01:52.32#ibcon#enter sib2, iclass 10, count 0 2006.217.08:01:52.32#ibcon#flushed, iclass 10, count 0 2006.217.08:01:52.32#ibcon#about to write, iclass 10, count 0 2006.217.08:01:52.32#ibcon#wrote, iclass 10, count 0 2006.217.08:01:52.32#ibcon#about to read 3, iclass 10, count 0 2006.217.08:01:52.35#ibcon#read 3, iclass 10, count 0 2006.217.08:01:52.35#ibcon#about to read 4, iclass 10, count 0 2006.217.08:01:52.35#ibcon#read 4, iclass 10, count 0 2006.217.08:01:52.35#ibcon#about to read 5, iclass 10, count 0 2006.217.08:01:52.35#ibcon#read 5, iclass 10, count 0 2006.217.08:01:52.35#ibcon#about to read 6, iclass 10, count 0 2006.217.08:01:52.35#ibcon#read 6, iclass 10, count 0 2006.217.08:01:52.35#ibcon#end of sib2, iclass 10, count 0 2006.217.08:01:52.35#ibcon#*after write, iclass 10, count 0 2006.217.08:01:52.35#ibcon#*before return 0, iclass 10, count 0 2006.217.08:01:52.35#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.217.08:01:52.35#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.217.08:01:52.35#ibcon#about to clear, iclass 10 cls_cnt 0 2006.217.08:01:52.35#ibcon#cleared, iclass 10 cls_cnt 0 2006.217.08:01:52.35$vc4f8/vblo=6,752.99 2006.217.08:01:52.35#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.217.08:01:52.35#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.217.08:01:52.35#ibcon#ireg 17 cls_cnt 0 2006.217.08:01:52.35#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.217.08:01:52.35#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.217.08:01:52.35#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.217.08:01:52.35#ibcon#enter wrdev, iclass 12, count 0 2006.217.08:01:52.35#ibcon#first serial, iclass 12, count 0 2006.217.08:01:52.35#ibcon#enter sib2, iclass 12, count 0 2006.217.08:01:52.35#ibcon#flushed, iclass 12, count 0 2006.217.08:01:52.35#ibcon#about to write, iclass 12, count 0 2006.217.08:01:52.35#ibcon#wrote, iclass 12, count 0 2006.217.08:01:52.35#ibcon#about to read 3, iclass 12, count 0 2006.217.08:01:52.37#ibcon#read 3, iclass 12, count 0 2006.217.08:01:52.37#ibcon#about to read 4, iclass 12, count 0 2006.217.08:01:52.37#ibcon#read 4, iclass 12, count 0 2006.217.08:01:52.37#ibcon#about to read 5, iclass 12, count 0 2006.217.08:01:52.37#ibcon#read 5, iclass 12, count 0 2006.217.08:01:52.37#ibcon#about to read 6, iclass 12, count 0 2006.217.08:01:52.37#ibcon#read 6, iclass 12, count 0 2006.217.08:01:52.37#ibcon#end of sib2, iclass 12, count 0 2006.217.08:01:52.37#ibcon#*mode == 0, iclass 12, count 0 2006.217.08:01:52.37#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.217.08:01:52.37#ibcon#[28=FRQ=06,752.99\r\n] 2006.217.08:01:52.37#ibcon#*before write, iclass 12, count 0 2006.217.08:01:52.37#ibcon#enter sib2, iclass 12, count 0 2006.217.08:01:52.37#ibcon#flushed, iclass 12, count 0 2006.217.08:01:52.37#ibcon#about to write, iclass 12, count 0 2006.217.08:01:52.37#ibcon#wrote, iclass 12, count 0 2006.217.08:01:52.37#ibcon#about to read 3, iclass 12, count 0 2006.217.08:01:52.41#ibcon#read 3, iclass 12, count 0 2006.217.08:01:52.41#ibcon#about to read 4, iclass 12, count 0 2006.217.08:01:52.41#ibcon#read 4, iclass 12, count 0 2006.217.08:01:52.41#ibcon#about to read 5, iclass 12, count 0 2006.217.08:01:52.41#ibcon#read 5, iclass 12, count 0 2006.217.08:01:52.41#ibcon#about to read 6, iclass 12, count 0 2006.217.08:01:52.41#ibcon#read 6, iclass 12, count 0 2006.217.08:01:52.41#ibcon#end of sib2, iclass 12, count 0 2006.217.08:01:52.41#ibcon#*after write, iclass 12, count 0 2006.217.08:01:52.41#ibcon#*before return 0, iclass 12, count 0 2006.217.08:01:52.41#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.217.08:01:52.41#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.217.08:01:52.41#ibcon#about to clear, iclass 12 cls_cnt 0 2006.217.08:01:52.41#ibcon#cleared, iclass 12 cls_cnt 0 2006.217.08:01:52.41$vc4f8/vb=6,4 2006.217.08:01:52.41#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.217.08:01:52.41#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.217.08:01:52.41#ibcon#ireg 11 cls_cnt 2 2006.217.08:01:52.41#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.217.08:01:52.47#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.217.08:01:52.47#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.217.08:01:52.47#ibcon#enter wrdev, iclass 14, count 2 2006.217.08:01:52.47#ibcon#first serial, iclass 14, count 2 2006.217.08:01:52.47#ibcon#enter sib2, iclass 14, count 2 2006.217.08:01:52.47#ibcon#flushed, iclass 14, count 2 2006.217.08:01:52.47#ibcon#about to write, iclass 14, count 2 2006.217.08:01:52.47#ibcon#wrote, iclass 14, count 2 2006.217.08:01:52.47#ibcon#about to read 3, iclass 14, count 2 2006.217.08:01:52.49#ibcon#read 3, iclass 14, count 2 2006.217.08:01:52.49#ibcon#about to read 4, iclass 14, count 2 2006.217.08:01:52.49#ibcon#read 4, iclass 14, count 2 2006.217.08:01:52.49#ibcon#about to read 5, iclass 14, count 2 2006.217.08:01:52.49#ibcon#read 5, iclass 14, count 2 2006.217.08:01:52.49#ibcon#about to read 6, iclass 14, count 2 2006.217.08:01:52.49#ibcon#read 6, iclass 14, count 2 2006.217.08:01:52.49#ibcon#end of sib2, iclass 14, count 2 2006.217.08:01:52.49#ibcon#*mode == 0, iclass 14, count 2 2006.217.08:01:52.49#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.217.08:01:52.49#ibcon#[27=AT06-04\r\n] 2006.217.08:01:52.49#ibcon#*before write, iclass 14, count 2 2006.217.08:01:52.49#ibcon#enter sib2, iclass 14, count 2 2006.217.08:01:52.49#ibcon#flushed, iclass 14, count 2 2006.217.08:01:52.49#ibcon#about to write, iclass 14, count 2 2006.217.08:01:52.49#ibcon#wrote, iclass 14, count 2 2006.217.08:01:52.49#ibcon#about to read 3, iclass 14, count 2 2006.217.08:01:52.52#ibcon#read 3, iclass 14, count 2 2006.217.08:01:52.52#ibcon#about to read 4, iclass 14, count 2 2006.217.08:01:52.52#ibcon#read 4, iclass 14, count 2 2006.217.08:01:52.52#ibcon#about to read 5, iclass 14, count 2 2006.217.08:01:52.52#ibcon#read 5, iclass 14, count 2 2006.217.08:01:52.52#ibcon#about to read 6, iclass 14, count 2 2006.217.08:01:52.52#ibcon#read 6, iclass 14, count 2 2006.217.08:01:52.52#ibcon#end of sib2, iclass 14, count 2 2006.217.08:01:52.52#ibcon#*after write, iclass 14, count 2 2006.217.08:01:52.52#ibcon#*before return 0, iclass 14, count 2 2006.217.08:01:52.52#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.217.08:01:52.52#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.217.08:01:52.52#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.217.08:01:52.52#ibcon#ireg 7 cls_cnt 0 2006.217.08:01:52.52#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.217.08:01:52.64#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.217.08:01:52.64#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.217.08:01:52.64#ibcon#enter wrdev, iclass 14, count 0 2006.217.08:01:52.64#ibcon#first serial, iclass 14, count 0 2006.217.08:01:52.64#ibcon#enter sib2, iclass 14, count 0 2006.217.08:01:52.64#ibcon#flushed, iclass 14, count 0 2006.217.08:01:52.64#ibcon#about to write, iclass 14, count 0 2006.217.08:01:52.64#ibcon#wrote, iclass 14, count 0 2006.217.08:01:52.64#ibcon#about to read 3, iclass 14, count 0 2006.217.08:01:52.66#ibcon#read 3, iclass 14, count 0 2006.217.08:01:52.66#ibcon#about to read 4, iclass 14, count 0 2006.217.08:01:52.66#ibcon#read 4, iclass 14, count 0 2006.217.08:01:52.66#ibcon#about to read 5, iclass 14, count 0 2006.217.08:01:52.66#ibcon#read 5, iclass 14, count 0 2006.217.08:01:52.66#ibcon#about to read 6, iclass 14, count 0 2006.217.08:01:52.66#ibcon#read 6, iclass 14, count 0 2006.217.08:01:52.66#ibcon#end of sib2, iclass 14, count 0 2006.217.08:01:52.66#ibcon#*mode == 0, iclass 14, count 0 2006.217.08:01:52.66#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.217.08:01:52.66#ibcon#[27=USB\r\n] 2006.217.08:01:52.66#ibcon#*before write, iclass 14, count 0 2006.217.08:01:52.66#ibcon#enter sib2, iclass 14, count 0 2006.217.08:01:52.66#ibcon#flushed, iclass 14, count 0 2006.217.08:01:52.66#ibcon#about to write, iclass 14, count 0 2006.217.08:01:52.66#ibcon#wrote, iclass 14, count 0 2006.217.08:01:52.66#ibcon#about to read 3, iclass 14, count 0 2006.217.08:01:52.69#ibcon#read 3, iclass 14, count 0 2006.217.08:01:52.69#ibcon#about to read 4, iclass 14, count 0 2006.217.08:01:52.69#ibcon#read 4, iclass 14, count 0 2006.217.08:01:52.69#ibcon#about to read 5, iclass 14, count 0 2006.217.08:01:52.69#ibcon#read 5, iclass 14, count 0 2006.217.08:01:52.69#ibcon#about to read 6, iclass 14, count 0 2006.217.08:01:52.69#ibcon#read 6, iclass 14, count 0 2006.217.08:01:52.69#ibcon#end of sib2, iclass 14, count 0 2006.217.08:01:52.69#ibcon#*after write, iclass 14, count 0 2006.217.08:01:52.69#ibcon#*before return 0, iclass 14, count 0 2006.217.08:01:52.69#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.217.08:01:52.69#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.217.08:01:52.69#ibcon#about to clear, iclass 14 cls_cnt 0 2006.217.08:01:52.69#ibcon#cleared, iclass 14 cls_cnt 0 2006.217.08:01:52.69$vc4f8/vabw=wide 2006.217.08:01:52.69#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.217.08:01:52.69#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.217.08:01:52.69#ibcon#ireg 8 cls_cnt 0 2006.217.08:01:52.69#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.217.08:01:52.69#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.217.08:01:52.69#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.217.08:01:52.69#ibcon#enter wrdev, iclass 16, count 0 2006.217.08:01:52.69#ibcon#first serial, iclass 16, count 0 2006.217.08:01:52.69#ibcon#enter sib2, iclass 16, count 0 2006.217.08:01:52.69#ibcon#flushed, iclass 16, count 0 2006.217.08:01:52.69#ibcon#about to write, iclass 16, count 0 2006.217.08:01:52.69#ibcon#wrote, iclass 16, count 0 2006.217.08:01:52.69#ibcon#about to read 3, iclass 16, count 0 2006.217.08:01:52.71#ibcon#read 3, iclass 16, count 0 2006.217.08:01:52.71#ibcon#about to read 4, iclass 16, count 0 2006.217.08:01:52.71#ibcon#read 4, iclass 16, count 0 2006.217.08:01:52.71#ibcon#about to read 5, iclass 16, count 0 2006.217.08:01:52.71#ibcon#read 5, iclass 16, count 0 2006.217.08:01:52.71#ibcon#about to read 6, iclass 16, count 0 2006.217.08:01:52.71#ibcon#read 6, iclass 16, count 0 2006.217.08:01:52.71#ibcon#end of sib2, iclass 16, count 0 2006.217.08:01:52.71#ibcon#*mode == 0, iclass 16, count 0 2006.217.08:01:52.71#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.217.08:01:52.71#ibcon#[25=BW32\r\n] 2006.217.08:01:52.71#ibcon#*before write, iclass 16, count 0 2006.217.08:01:52.71#ibcon#enter sib2, iclass 16, count 0 2006.217.08:01:52.71#ibcon#flushed, iclass 16, count 0 2006.217.08:01:52.71#ibcon#about to write, iclass 16, count 0 2006.217.08:01:52.71#ibcon#wrote, iclass 16, count 0 2006.217.08:01:52.71#ibcon#about to read 3, iclass 16, count 0 2006.217.08:01:52.74#ibcon#read 3, iclass 16, count 0 2006.217.08:01:52.74#ibcon#about to read 4, iclass 16, count 0 2006.217.08:01:52.74#ibcon#read 4, iclass 16, count 0 2006.217.08:01:52.74#ibcon#about to read 5, iclass 16, count 0 2006.217.08:01:52.74#ibcon#read 5, iclass 16, count 0 2006.217.08:01:52.74#ibcon#about to read 6, iclass 16, count 0 2006.217.08:01:52.74#ibcon#read 6, iclass 16, count 0 2006.217.08:01:52.74#ibcon#end of sib2, iclass 16, count 0 2006.217.08:01:52.74#ibcon#*after write, iclass 16, count 0 2006.217.08:01:52.74#ibcon#*before return 0, iclass 16, count 0 2006.217.08:01:52.74#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.217.08:01:52.74#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.217.08:01:52.74#ibcon#about to clear, iclass 16 cls_cnt 0 2006.217.08:01:52.74#ibcon#cleared, iclass 16 cls_cnt 0 2006.217.08:01:52.74$vc4f8/vbbw=wide 2006.217.08:01:52.74#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.217.08:01:52.74#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.217.08:01:52.74#ibcon#ireg 8 cls_cnt 0 2006.217.08:01:52.74#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.217.08:01:52.81#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.217.08:01:52.81#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.217.08:01:52.81#ibcon#enter wrdev, iclass 18, count 0 2006.217.08:01:52.81#ibcon#first serial, iclass 18, count 0 2006.217.08:01:52.81#ibcon#enter sib2, iclass 18, count 0 2006.217.08:01:52.81#ibcon#flushed, iclass 18, count 0 2006.217.08:01:52.81#ibcon#about to write, iclass 18, count 0 2006.217.08:01:52.81#ibcon#wrote, iclass 18, count 0 2006.217.08:01:52.81#ibcon#about to read 3, iclass 18, count 0 2006.217.08:01:52.83#ibcon#read 3, iclass 18, count 0 2006.217.08:01:52.83#ibcon#about to read 4, iclass 18, count 0 2006.217.08:01:52.83#ibcon#read 4, iclass 18, count 0 2006.217.08:01:52.83#ibcon#about to read 5, iclass 18, count 0 2006.217.08:01:52.83#ibcon#read 5, iclass 18, count 0 2006.217.08:01:52.83#ibcon#about to read 6, iclass 18, count 0 2006.217.08:01:52.83#ibcon#read 6, iclass 18, count 0 2006.217.08:01:52.83#ibcon#end of sib2, iclass 18, count 0 2006.217.08:01:52.83#ibcon#*mode == 0, iclass 18, count 0 2006.217.08:01:52.83#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.217.08:01:52.83#ibcon#[27=BW32\r\n] 2006.217.08:01:52.83#ibcon#*before write, iclass 18, count 0 2006.217.08:01:52.83#ibcon#enter sib2, iclass 18, count 0 2006.217.08:01:52.83#ibcon#flushed, iclass 18, count 0 2006.217.08:01:52.83#ibcon#about to write, iclass 18, count 0 2006.217.08:01:52.83#ibcon#wrote, iclass 18, count 0 2006.217.08:01:52.83#ibcon#about to read 3, iclass 18, count 0 2006.217.08:01:52.86#ibcon#read 3, iclass 18, count 0 2006.217.08:01:52.86#ibcon#about to read 4, iclass 18, count 0 2006.217.08:01:52.86#ibcon#read 4, iclass 18, count 0 2006.217.08:01:52.86#ibcon#about to read 5, iclass 18, count 0 2006.217.08:01:52.86#ibcon#read 5, iclass 18, count 0 2006.217.08:01:52.86#ibcon#about to read 6, iclass 18, count 0 2006.217.08:01:52.86#ibcon#read 6, iclass 18, count 0 2006.217.08:01:52.86#ibcon#end of sib2, iclass 18, count 0 2006.217.08:01:52.86#ibcon#*after write, iclass 18, count 0 2006.217.08:01:52.86#ibcon#*before return 0, iclass 18, count 0 2006.217.08:01:52.86#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.217.08:01:52.86#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.217.08:01:52.86#ibcon#about to clear, iclass 18 cls_cnt 0 2006.217.08:01:52.86#ibcon#cleared, iclass 18 cls_cnt 0 2006.217.08:01:52.86$4f8m12a/ifd4f 2006.217.08:01:52.86$ifd4f/lo= 2006.217.08:01:52.86$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.217.08:01:52.86$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.217.08:01:52.86$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.217.08:01:52.86$ifd4f/patch= 2006.217.08:01:52.86$ifd4f/patch=lo1,a1,a2,a3,a4 2006.217.08:01:52.86$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.217.08:01:52.86$ifd4f/patch=lo3,a5,a6,a7,a8 2006.217.08:01:52.86$4f8m12a/"form=m,16.000,1:2 2006.217.08:01:52.86$4f8m12a/"tpicd 2006.217.08:01:52.86$4f8m12a/echo=off 2006.217.08:01:52.86$4f8m12a/xlog=off 2006.217.08:01:52.86:!2006.217.08:02:20 2006.217.08:02:00.14#trakl#Source acquired 2006.217.08:02:02.14#flagr#flagr/antenna,acquired 2006.217.08:02:20.00:preob 2006.217.08:02:21.14/onsource/TRACKING 2006.217.08:02:21.14:!2006.217.08:02:30 2006.217.08:02:30.00:data_valid=on 2006.217.08:02:30.00:midob 2006.217.08:02:30.14/onsource/TRACKING 2006.217.08:02:30.14/wx/30.91,1008.6,63 2006.217.08:02:30.23/cable/+6.3837E-03 2006.217.08:02:31.32/va/01,05,usb,yes,32,33 2006.217.08:02:31.32/va/02,04,usb,yes,29,31 2006.217.08:02:31.32/va/03,04,usb,yes,28,28 2006.217.08:02:31.32/va/04,04,usb,yes,31,33 2006.217.08:02:31.32/va/05,07,usb,yes,33,35 2006.217.08:02:31.32/va/06,06,usb,yes,32,32 2006.217.08:02:31.32/va/07,06,usb,yes,33,32 2006.217.08:02:31.32/va/08,07,usb,yes,31,30 2006.217.08:02:31.55/valo/01,532.99,yes,locked 2006.217.08:02:31.55/valo/02,572.99,yes,locked 2006.217.08:02:31.55/valo/03,672.99,yes,locked 2006.217.08:02:31.55/valo/04,832.99,yes,locked 2006.217.08:02:31.55/valo/05,652.99,yes,locked 2006.217.08:02:31.55/valo/06,772.99,yes,locked 2006.217.08:02:31.55/valo/07,832.99,yes,locked 2006.217.08:02:31.55/valo/08,852.99,yes,locked 2006.217.08:02:32.64/vb/01,04,usb,yes,31,29 2006.217.08:02:32.64/vb/02,04,usb,yes,32,34 2006.217.08:02:32.64/vb/03,04,usb,yes,29,32 2006.217.08:02:32.64/vb/04,04,usb,yes,29,30 2006.217.08:02:32.64/vb/05,04,usb,yes,28,32 2006.217.08:02:32.64/vb/06,04,usb,yes,29,32 2006.217.08:02:32.64/vb/07,04,usb,yes,31,31 2006.217.08:02:32.64/vb/08,04,usb,yes,28,32 2006.217.08:02:32.88/vblo/01,632.99,yes,locked 2006.217.08:02:32.88/vblo/02,640.99,yes,locked 2006.217.08:02:32.88/vblo/03,656.99,yes,locked 2006.217.08:02:32.88/vblo/04,712.99,yes,locked 2006.217.08:02:32.88/vblo/05,744.99,yes,locked 2006.217.08:02:32.88/vblo/06,752.99,yes,locked 2006.217.08:02:32.88/vblo/07,734.99,yes,locked 2006.217.08:02:32.88/vblo/08,744.99,yes,locked 2006.217.08:02:33.03/vabw/8 2006.217.08:02:33.18/vbbw/8 2006.217.08:02:33.27/xfe/off,on,15.0 2006.217.08:02:33.67/ifatt/23,28,28,28 2006.217.08:02:34.07/fmout-gps/S +4.34E-07 2006.217.08:02:34.14:!2006.217.08:03:30 2006.217.08:03:30.01:data_valid=off 2006.217.08:03:30.01:postob 2006.217.08:03:30.18/cable/+6.3857E-03 2006.217.08:03:30.21/wx/30.87,1008.6,64 2006.217.08:03:31.07/fmout-gps/S +4.36E-07 2006.217.08:03:31.07:scan_name=217-0805,k06217,70 2006.217.08:03:31.08:source=1116+128,111857.30,123441.7,2000.0,ccw 2006.217.08:03:31.14#flagr#flagr/antenna,new-source 2006.217.08:03:32.14:checkk5 2006.217.08:03:32.52/chk_autoobs//k5ts1/ autoobs is running! 2006.217.08:03:32.89/chk_autoobs//k5ts2/ autoobs is running! 2006.217.08:03:33.27/chk_autoobs//k5ts3/ autoobs is running! 2006.217.08:03:33.64/chk_autoobs//k5ts4/ autoobs is running! 2006.217.08:03:34.01/chk_obsdata//k5ts1/T2170802??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.08:03:34.38/chk_obsdata//k5ts2/T2170802??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.08:03:34.75/chk_obsdata//k5ts3/T2170802??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.08:03:35.11/chk_obsdata//k5ts4/T2170802??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.08:03:35.81/k5log//k5ts1_log_newline 2006.217.08:03:36.51/k5log//k5ts2_log_newline 2006.217.08:03:37.20/k5log//k5ts3_log_newline 2006.217.08:03:37.88/k5log//k5ts4_log_newline 2006.217.08:03:37.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.217.08:03:37.91:4f8m12a=2 2006.217.08:03:37.91$4f8m12a/echo=on 2006.217.08:03:37.91$4f8m12a/pcalon 2006.217.08:03:37.91$pcalon/"no phase cal control is implemented here 2006.217.08:03:37.91$4f8m12a/"tpicd=stop 2006.217.08:03:37.91$4f8m12a/vc4f8 2006.217.08:03:37.91$vc4f8/valo=1,532.99 2006.217.08:03:37.92#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.217.08:03:37.92#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.217.08:03:37.92#ibcon#ireg 17 cls_cnt 0 2006.217.08:03:37.92#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.217.08:03:37.92#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.217.08:03:37.92#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.217.08:03:37.92#ibcon#enter wrdev, iclass 29, count 0 2006.217.08:03:37.92#ibcon#first serial, iclass 29, count 0 2006.217.08:03:37.92#ibcon#enter sib2, iclass 29, count 0 2006.217.08:03:37.92#ibcon#flushed, iclass 29, count 0 2006.217.08:03:37.92#ibcon#about to write, iclass 29, count 0 2006.217.08:03:37.92#ibcon#wrote, iclass 29, count 0 2006.217.08:03:37.92#ibcon#about to read 3, iclass 29, count 0 2006.217.08:03:37.95#ibcon#read 3, iclass 29, count 0 2006.217.08:03:37.95#ibcon#about to read 4, iclass 29, count 0 2006.217.08:03:37.95#ibcon#read 4, iclass 29, count 0 2006.217.08:03:37.95#ibcon#about to read 5, iclass 29, count 0 2006.217.08:03:37.95#ibcon#read 5, iclass 29, count 0 2006.217.08:03:37.95#ibcon#about to read 6, iclass 29, count 0 2006.217.08:03:37.95#ibcon#read 6, iclass 29, count 0 2006.217.08:03:37.95#ibcon#end of sib2, iclass 29, count 0 2006.217.08:03:37.95#ibcon#*mode == 0, iclass 29, count 0 2006.217.08:03:37.95#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.217.08:03:37.95#ibcon#[26=FRQ=01,532.99\r\n] 2006.217.08:03:37.95#ibcon#*before write, iclass 29, count 0 2006.217.08:03:37.95#ibcon#enter sib2, iclass 29, count 0 2006.217.08:03:37.95#ibcon#flushed, iclass 29, count 0 2006.217.08:03:37.95#ibcon#about to write, iclass 29, count 0 2006.217.08:03:37.95#ibcon#wrote, iclass 29, count 0 2006.217.08:03:37.95#ibcon#about to read 3, iclass 29, count 0 2006.217.08:03:38.00#ibcon#read 3, iclass 29, count 0 2006.217.08:03:38.00#ibcon#about to read 4, iclass 29, count 0 2006.217.08:03:38.00#ibcon#read 4, iclass 29, count 0 2006.217.08:03:38.00#ibcon#about to read 5, iclass 29, count 0 2006.217.08:03:38.00#ibcon#read 5, iclass 29, count 0 2006.217.08:03:38.00#ibcon#about to read 6, iclass 29, count 0 2006.217.08:03:38.00#ibcon#read 6, iclass 29, count 0 2006.217.08:03:38.00#ibcon#end of sib2, iclass 29, count 0 2006.217.08:03:38.00#ibcon#*after write, iclass 29, count 0 2006.217.08:03:38.00#ibcon#*before return 0, iclass 29, count 0 2006.217.08:03:38.00#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.217.08:03:38.00#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.217.08:03:38.00#ibcon#about to clear, iclass 29 cls_cnt 0 2006.217.08:03:38.00#ibcon#cleared, iclass 29 cls_cnt 0 2006.217.08:03:38.00$vc4f8/va=1,5 2006.217.08:03:38.00#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.217.08:03:38.00#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.217.08:03:38.00#ibcon#ireg 11 cls_cnt 2 2006.217.08:03:38.00#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.217.08:03:38.00#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.217.08:03:38.00#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.217.08:03:38.00#ibcon#enter wrdev, iclass 31, count 2 2006.217.08:03:38.00#ibcon#first serial, iclass 31, count 2 2006.217.08:03:38.00#ibcon#enter sib2, iclass 31, count 2 2006.217.08:03:38.00#ibcon#flushed, iclass 31, count 2 2006.217.08:03:38.00#ibcon#about to write, iclass 31, count 2 2006.217.08:03:38.00#ibcon#wrote, iclass 31, count 2 2006.217.08:03:38.00#ibcon#about to read 3, iclass 31, count 2 2006.217.08:03:38.02#ibcon#read 3, iclass 31, count 2 2006.217.08:03:38.02#ibcon#about to read 4, iclass 31, count 2 2006.217.08:03:38.02#ibcon#read 4, iclass 31, count 2 2006.217.08:03:38.02#ibcon#about to read 5, iclass 31, count 2 2006.217.08:03:38.02#ibcon#read 5, iclass 31, count 2 2006.217.08:03:38.02#ibcon#about to read 6, iclass 31, count 2 2006.217.08:03:38.02#ibcon#read 6, iclass 31, count 2 2006.217.08:03:38.02#ibcon#end of sib2, iclass 31, count 2 2006.217.08:03:38.02#ibcon#*mode == 0, iclass 31, count 2 2006.217.08:03:38.02#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.217.08:03:38.02#ibcon#[25=AT01-05\r\n] 2006.217.08:03:38.02#ibcon#*before write, iclass 31, count 2 2006.217.08:03:38.02#ibcon#enter sib2, iclass 31, count 2 2006.217.08:03:38.02#ibcon#flushed, iclass 31, count 2 2006.217.08:03:38.02#ibcon#about to write, iclass 31, count 2 2006.217.08:03:38.02#ibcon#wrote, iclass 31, count 2 2006.217.08:03:38.02#ibcon#about to read 3, iclass 31, count 2 2006.217.08:03:38.05#ibcon#read 3, iclass 31, count 2 2006.217.08:03:38.05#ibcon#about to read 4, iclass 31, count 2 2006.217.08:03:38.05#ibcon#read 4, iclass 31, count 2 2006.217.08:03:38.05#ibcon#about to read 5, iclass 31, count 2 2006.217.08:03:38.05#ibcon#read 5, iclass 31, count 2 2006.217.08:03:38.05#ibcon#about to read 6, iclass 31, count 2 2006.217.08:03:38.05#ibcon#read 6, iclass 31, count 2 2006.217.08:03:38.05#ibcon#end of sib2, iclass 31, count 2 2006.217.08:03:38.05#ibcon#*after write, iclass 31, count 2 2006.217.08:03:38.05#ibcon#*before return 0, iclass 31, count 2 2006.217.08:03:38.05#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.217.08:03:38.05#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.217.08:03:38.05#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.217.08:03:38.05#ibcon#ireg 7 cls_cnt 0 2006.217.08:03:38.05#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.217.08:03:38.17#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.217.08:03:38.17#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.217.08:03:38.17#ibcon#enter wrdev, iclass 31, count 0 2006.217.08:03:38.17#ibcon#first serial, iclass 31, count 0 2006.217.08:03:38.17#ibcon#enter sib2, iclass 31, count 0 2006.217.08:03:38.17#ibcon#flushed, iclass 31, count 0 2006.217.08:03:38.17#ibcon#about to write, iclass 31, count 0 2006.217.08:03:38.17#ibcon#wrote, iclass 31, count 0 2006.217.08:03:38.17#ibcon#about to read 3, iclass 31, count 0 2006.217.08:03:38.19#ibcon#read 3, iclass 31, count 0 2006.217.08:03:38.19#ibcon#about to read 4, iclass 31, count 0 2006.217.08:03:38.19#ibcon#read 4, iclass 31, count 0 2006.217.08:03:38.19#ibcon#about to read 5, iclass 31, count 0 2006.217.08:03:38.19#ibcon#read 5, iclass 31, count 0 2006.217.08:03:38.19#ibcon#about to read 6, iclass 31, count 0 2006.217.08:03:38.19#ibcon#read 6, iclass 31, count 0 2006.217.08:03:38.19#ibcon#end of sib2, iclass 31, count 0 2006.217.08:03:38.19#ibcon#*mode == 0, iclass 31, count 0 2006.217.08:03:38.19#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.217.08:03:38.19#ibcon#[25=USB\r\n] 2006.217.08:03:38.19#ibcon#*before write, iclass 31, count 0 2006.217.08:03:38.19#ibcon#enter sib2, iclass 31, count 0 2006.217.08:03:38.19#ibcon#flushed, iclass 31, count 0 2006.217.08:03:38.19#ibcon#about to write, iclass 31, count 0 2006.217.08:03:38.19#ibcon#wrote, iclass 31, count 0 2006.217.08:03:38.19#ibcon#about to read 3, iclass 31, count 0 2006.217.08:03:38.22#ibcon#read 3, iclass 31, count 0 2006.217.08:03:38.22#ibcon#about to read 4, iclass 31, count 0 2006.217.08:03:38.22#ibcon#read 4, iclass 31, count 0 2006.217.08:03:38.22#ibcon#about to read 5, iclass 31, count 0 2006.217.08:03:38.22#ibcon#read 5, iclass 31, count 0 2006.217.08:03:38.22#ibcon#about to read 6, iclass 31, count 0 2006.217.08:03:38.22#ibcon#read 6, iclass 31, count 0 2006.217.08:03:38.22#ibcon#end of sib2, iclass 31, count 0 2006.217.08:03:38.22#ibcon#*after write, iclass 31, count 0 2006.217.08:03:38.22#ibcon#*before return 0, iclass 31, count 0 2006.217.08:03:38.22#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.217.08:03:38.22#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.217.08:03:38.22#ibcon#about to clear, iclass 31 cls_cnt 0 2006.217.08:03:38.22#ibcon#cleared, iclass 31 cls_cnt 0 2006.217.08:03:38.22$vc4f8/valo=2,572.99 2006.217.08:03:38.22#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.217.08:03:38.22#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.217.08:03:38.22#ibcon#ireg 17 cls_cnt 0 2006.217.08:03:38.22#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.217.08:03:38.22#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.217.08:03:38.22#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.217.08:03:38.22#ibcon#enter wrdev, iclass 33, count 0 2006.217.08:03:38.22#ibcon#first serial, iclass 33, count 0 2006.217.08:03:38.22#ibcon#enter sib2, iclass 33, count 0 2006.217.08:03:38.22#ibcon#flushed, iclass 33, count 0 2006.217.08:03:38.22#ibcon#about to write, iclass 33, count 0 2006.217.08:03:38.22#ibcon#wrote, iclass 33, count 0 2006.217.08:03:38.22#ibcon#about to read 3, iclass 33, count 0 2006.217.08:03:38.24#ibcon#read 3, iclass 33, count 0 2006.217.08:03:38.24#ibcon#about to read 4, iclass 33, count 0 2006.217.08:03:38.24#ibcon#read 4, iclass 33, count 0 2006.217.08:03:38.24#ibcon#about to read 5, iclass 33, count 0 2006.217.08:03:38.24#ibcon#read 5, iclass 33, count 0 2006.217.08:03:38.24#ibcon#about to read 6, iclass 33, count 0 2006.217.08:03:38.24#ibcon#read 6, iclass 33, count 0 2006.217.08:03:38.24#ibcon#end of sib2, iclass 33, count 0 2006.217.08:03:38.24#ibcon#*mode == 0, iclass 33, count 0 2006.217.08:03:38.24#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.217.08:03:38.24#ibcon#[26=FRQ=02,572.99\r\n] 2006.217.08:03:38.24#ibcon#*before write, iclass 33, count 0 2006.217.08:03:38.24#ibcon#enter sib2, iclass 33, count 0 2006.217.08:03:38.24#ibcon#flushed, iclass 33, count 0 2006.217.08:03:38.24#ibcon#about to write, iclass 33, count 0 2006.217.08:03:38.24#ibcon#wrote, iclass 33, count 0 2006.217.08:03:38.24#ibcon#about to read 3, iclass 33, count 0 2006.217.08:03:38.28#ibcon#read 3, iclass 33, count 0 2006.217.08:03:38.28#ibcon#about to read 4, iclass 33, count 0 2006.217.08:03:38.28#ibcon#read 4, iclass 33, count 0 2006.217.08:03:38.28#ibcon#about to read 5, iclass 33, count 0 2006.217.08:03:38.28#ibcon#read 5, iclass 33, count 0 2006.217.08:03:38.28#ibcon#about to read 6, iclass 33, count 0 2006.217.08:03:38.28#ibcon#read 6, iclass 33, count 0 2006.217.08:03:38.28#ibcon#end of sib2, iclass 33, count 0 2006.217.08:03:38.28#ibcon#*after write, iclass 33, count 0 2006.217.08:03:38.28#ibcon#*before return 0, iclass 33, count 0 2006.217.08:03:38.28#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.217.08:03:38.28#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.217.08:03:38.28#ibcon#about to clear, iclass 33 cls_cnt 0 2006.217.08:03:38.28#ibcon#cleared, iclass 33 cls_cnt 0 2006.217.08:03:38.28$vc4f8/va=2,4 2006.217.08:03:38.28#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.217.08:03:38.28#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.217.08:03:38.28#ibcon#ireg 11 cls_cnt 2 2006.217.08:03:38.28#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.217.08:03:38.34#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.217.08:03:38.34#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.217.08:03:38.34#ibcon#enter wrdev, iclass 35, count 2 2006.217.08:03:38.34#ibcon#first serial, iclass 35, count 2 2006.217.08:03:38.34#ibcon#enter sib2, iclass 35, count 2 2006.217.08:03:38.34#ibcon#flushed, iclass 35, count 2 2006.217.08:03:38.34#ibcon#about to write, iclass 35, count 2 2006.217.08:03:38.34#ibcon#wrote, iclass 35, count 2 2006.217.08:03:38.34#ibcon#about to read 3, iclass 35, count 2 2006.217.08:03:38.36#ibcon#read 3, iclass 35, count 2 2006.217.08:03:38.36#ibcon#about to read 4, iclass 35, count 2 2006.217.08:03:38.36#ibcon#read 4, iclass 35, count 2 2006.217.08:03:38.36#ibcon#about to read 5, iclass 35, count 2 2006.217.08:03:38.36#ibcon#read 5, iclass 35, count 2 2006.217.08:03:38.36#ibcon#about to read 6, iclass 35, count 2 2006.217.08:03:38.36#ibcon#read 6, iclass 35, count 2 2006.217.08:03:38.36#ibcon#end of sib2, iclass 35, count 2 2006.217.08:03:38.36#ibcon#*mode == 0, iclass 35, count 2 2006.217.08:03:38.36#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.217.08:03:38.36#ibcon#[25=AT02-04\r\n] 2006.217.08:03:38.36#ibcon#*before write, iclass 35, count 2 2006.217.08:03:38.36#ibcon#enter sib2, iclass 35, count 2 2006.217.08:03:38.36#ibcon#flushed, iclass 35, count 2 2006.217.08:03:38.36#ibcon#about to write, iclass 35, count 2 2006.217.08:03:38.36#ibcon#wrote, iclass 35, count 2 2006.217.08:03:38.36#ibcon#about to read 3, iclass 35, count 2 2006.217.08:03:38.39#ibcon#read 3, iclass 35, count 2 2006.217.08:03:38.39#ibcon#about to read 4, iclass 35, count 2 2006.217.08:03:38.39#ibcon#read 4, iclass 35, count 2 2006.217.08:03:38.39#ibcon#about to read 5, iclass 35, count 2 2006.217.08:03:38.39#ibcon#read 5, iclass 35, count 2 2006.217.08:03:38.39#ibcon#about to read 6, iclass 35, count 2 2006.217.08:03:38.39#ibcon#read 6, iclass 35, count 2 2006.217.08:03:38.39#ibcon#end of sib2, iclass 35, count 2 2006.217.08:03:38.39#ibcon#*after write, iclass 35, count 2 2006.217.08:03:38.39#ibcon#*before return 0, iclass 35, count 2 2006.217.08:03:38.39#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.217.08:03:38.39#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.217.08:03:38.39#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.217.08:03:38.39#ibcon#ireg 7 cls_cnt 0 2006.217.08:03:38.39#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.217.08:03:38.51#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.217.08:03:38.51#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.217.08:03:38.51#ibcon#enter wrdev, iclass 35, count 0 2006.217.08:03:38.51#ibcon#first serial, iclass 35, count 0 2006.217.08:03:38.51#ibcon#enter sib2, iclass 35, count 0 2006.217.08:03:38.51#ibcon#flushed, iclass 35, count 0 2006.217.08:03:38.51#ibcon#about to write, iclass 35, count 0 2006.217.08:03:38.51#ibcon#wrote, iclass 35, count 0 2006.217.08:03:38.51#ibcon#about to read 3, iclass 35, count 0 2006.217.08:03:38.53#ibcon#read 3, iclass 35, count 0 2006.217.08:03:38.53#ibcon#about to read 4, iclass 35, count 0 2006.217.08:03:38.53#ibcon#read 4, iclass 35, count 0 2006.217.08:03:38.53#ibcon#about to read 5, iclass 35, count 0 2006.217.08:03:38.53#ibcon#read 5, iclass 35, count 0 2006.217.08:03:38.53#ibcon#about to read 6, iclass 35, count 0 2006.217.08:03:38.53#ibcon#read 6, iclass 35, count 0 2006.217.08:03:38.53#ibcon#end of sib2, iclass 35, count 0 2006.217.08:03:38.53#ibcon#*mode == 0, iclass 35, count 0 2006.217.08:03:38.53#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.217.08:03:38.53#ibcon#[25=USB\r\n] 2006.217.08:03:38.53#ibcon#*before write, iclass 35, count 0 2006.217.08:03:38.53#ibcon#enter sib2, iclass 35, count 0 2006.217.08:03:38.53#ibcon#flushed, iclass 35, count 0 2006.217.08:03:38.53#ibcon#about to write, iclass 35, count 0 2006.217.08:03:38.53#ibcon#wrote, iclass 35, count 0 2006.217.08:03:38.53#ibcon#about to read 3, iclass 35, count 0 2006.217.08:03:38.56#ibcon#read 3, iclass 35, count 0 2006.217.08:03:38.56#ibcon#about to read 4, iclass 35, count 0 2006.217.08:03:38.56#ibcon#read 4, iclass 35, count 0 2006.217.08:03:38.56#ibcon#about to read 5, iclass 35, count 0 2006.217.08:03:38.56#ibcon#read 5, iclass 35, count 0 2006.217.08:03:38.56#ibcon#about to read 6, iclass 35, count 0 2006.217.08:03:38.56#ibcon#read 6, iclass 35, count 0 2006.217.08:03:38.56#ibcon#end of sib2, iclass 35, count 0 2006.217.08:03:38.56#ibcon#*after write, iclass 35, count 0 2006.217.08:03:38.56#ibcon#*before return 0, iclass 35, count 0 2006.217.08:03:38.56#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.217.08:03:38.56#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.217.08:03:38.56#ibcon#about to clear, iclass 35 cls_cnt 0 2006.217.08:03:38.56#ibcon#cleared, iclass 35 cls_cnt 0 2006.217.08:03:38.56$vc4f8/valo=3,672.99 2006.217.08:03:38.56#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.217.08:03:38.56#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.217.08:03:38.56#ibcon#ireg 17 cls_cnt 0 2006.217.08:03:38.56#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.217.08:03:38.56#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.217.08:03:38.56#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.217.08:03:38.56#ibcon#enter wrdev, iclass 37, count 0 2006.217.08:03:38.56#ibcon#first serial, iclass 37, count 0 2006.217.08:03:38.56#ibcon#enter sib2, iclass 37, count 0 2006.217.08:03:38.56#ibcon#flushed, iclass 37, count 0 2006.217.08:03:38.56#ibcon#about to write, iclass 37, count 0 2006.217.08:03:38.56#ibcon#wrote, iclass 37, count 0 2006.217.08:03:38.56#ibcon#about to read 3, iclass 37, count 0 2006.217.08:03:38.58#ibcon#read 3, iclass 37, count 0 2006.217.08:03:38.58#ibcon#about to read 4, iclass 37, count 0 2006.217.08:03:38.58#ibcon#read 4, iclass 37, count 0 2006.217.08:03:38.58#ibcon#about to read 5, iclass 37, count 0 2006.217.08:03:38.58#ibcon#read 5, iclass 37, count 0 2006.217.08:03:38.58#ibcon#about to read 6, iclass 37, count 0 2006.217.08:03:38.58#ibcon#read 6, iclass 37, count 0 2006.217.08:03:38.58#ibcon#end of sib2, iclass 37, count 0 2006.217.08:03:38.58#ibcon#*mode == 0, iclass 37, count 0 2006.217.08:03:38.58#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.217.08:03:38.58#ibcon#[26=FRQ=03,672.99\r\n] 2006.217.08:03:38.58#ibcon#*before write, iclass 37, count 0 2006.217.08:03:38.58#ibcon#enter sib2, iclass 37, count 0 2006.217.08:03:38.58#ibcon#flushed, iclass 37, count 0 2006.217.08:03:38.58#ibcon#about to write, iclass 37, count 0 2006.217.08:03:38.58#ibcon#wrote, iclass 37, count 0 2006.217.08:03:38.58#ibcon#about to read 3, iclass 37, count 0 2006.217.08:03:38.62#ibcon#read 3, iclass 37, count 0 2006.217.08:03:38.62#ibcon#about to read 4, iclass 37, count 0 2006.217.08:03:38.62#ibcon#read 4, iclass 37, count 0 2006.217.08:03:38.62#ibcon#about to read 5, iclass 37, count 0 2006.217.08:03:38.62#ibcon#read 5, iclass 37, count 0 2006.217.08:03:38.62#ibcon#about to read 6, iclass 37, count 0 2006.217.08:03:38.62#ibcon#read 6, iclass 37, count 0 2006.217.08:03:38.62#ibcon#end of sib2, iclass 37, count 0 2006.217.08:03:38.62#ibcon#*after write, iclass 37, count 0 2006.217.08:03:38.62#ibcon#*before return 0, iclass 37, count 0 2006.217.08:03:38.62#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.217.08:03:38.62#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.217.08:03:38.62#ibcon#about to clear, iclass 37 cls_cnt 0 2006.217.08:03:38.62#ibcon#cleared, iclass 37 cls_cnt 0 2006.217.08:03:38.62$vc4f8/va=3,4 2006.217.08:03:38.62#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.217.08:03:38.62#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.217.08:03:38.62#ibcon#ireg 11 cls_cnt 2 2006.217.08:03:38.62#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.217.08:03:38.68#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.217.08:03:38.68#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.217.08:03:38.68#ibcon#enter wrdev, iclass 39, count 2 2006.217.08:03:38.68#ibcon#first serial, iclass 39, count 2 2006.217.08:03:38.68#ibcon#enter sib2, iclass 39, count 2 2006.217.08:03:38.68#ibcon#flushed, iclass 39, count 2 2006.217.08:03:38.68#ibcon#about to write, iclass 39, count 2 2006.217.08:03:38.68#ibcon#wrote, iclass 39, count 2 2006.217.08:03:38.68#ibcon#about to read 3, iclass 39, count 2 2006.217.08:03:38.71#ibcon#read 3, iclass 39, count 2 2006.217.08:03:38.71#ibcon#about to read 4, iclass 39, count 2 2006.217.08:03:38.71#ibcon#read 4, iclass 39, count 2 2006.217.08:03:38.71#ibcon#about to read 5, iclass 39, count 2 2006.217.08:03:38.71#ibcon#read 5, iclass 39, count 2 2006.217.08:03:38.71#ibcon#about to read 6, iclass 39, count 2 2006.217.08:03:38.71#ibcon#read 6, iclass 39, count 2 2006.217.08:03:38.71#ibcon#end of sib2, iclass 39, count 2 2006.217.08:03:38.71#ibcon#*mode == 0, iclass 39, count 2 2006.217.08:03:38.71#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.217.08:03:38.71#ibcon#[25=AT03-04\r\n] 2006.217.08:03:38.71#ibcon#*before write, iclass 39, count 2 2006.217.08:03:38.71#ibcon#enter sib2, iclass 39, count 2 2006.217.08:03:38.71#ibcon#flushed, iclass 39, count 2 2006.217.08:03:38.71#ibcon#about to write, iclass 39, count 2 2006.217.08:03:38.71#ibcon#wrote, iclass 39, count 2 2006.217.08:03:38.71#ibcon#about to read 3, iclass 39, count 2 2006.217.08:03:38.74#ibcon#read 3, iclass 39, count 2 2006.217.08:03:38.74#ibcon#about to read 4, iclass 39, count 2 2006.217.08:03:38.74#ibcon#read 4, iclass 39, count 2 2006.217.08:03:38.74#ibcon#about to read 5, iclass 39, count 2 2006.217.08:03:38.74#ibcon#read 5, iclass 39, count 2 2006.217.08:03:38.74#ibcon#about to read 6, iclass 39, count 2 2006.217.08:03:38.74#ibcon#read 6, iclass 39, count 2 2006.217.08:03:38.74#ibcon#end of sib2, iclass 39, count 2 2006.217.08:03:38.74#ibcon#*after write, iclass 39, count 2 2006.217.08:03:38.74#ibcon#*before return 0, iclass 39, count 2 2006.217.08:03:38.74#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.217.08:03:38.74#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.217.08:03:38.74#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.217.08:03:38.74#ibcon#ireg 7 cls_cnt 0 2006.217.08:03:38.74#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.217.08:03:38.86#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.217.08:03:38.86#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.217.08:03:38.86#ibcon#enter wrdev, iclass 39, count 0 2006.217.08:03:38.86#ibcon#first serial, iclass 39, count 0 2006.217.08:03:38.86#ibcon#enter sib2, iclass 39, count 0 2006.217.08:03:38.86#ibcon#flushed, iclass 39, count 0 2006.217.08:03:38.86#ibcon#about to write, iclass 39, count 0 2006.217.08:03:38.86#ibcon#wrote, iclass 39, count 0 2006.217.08:03:38.86#ibcon#about to read 3, iclass 39, count 0 2006.217.08:03:38.88#ibcon#read 3, iclass 39, count 0 2006.217.08:03:38.88#ibcon#about to read 4, iclass 39, count 0 2006.217.08:03:38.88#ibcon#read 4, iclass 39, count 0 2006.217.08:03:38.88#ibcon#about to read 5, iclass 39, count 0 2006.217.08:03:38.88#ibcon#read 5, iclass 39, count 0 2006.217.08:03:38.88#ibcon#about to read 6, iclass 39, count 0 2006.217.08:03:38.88#ibcon#read 6, iclass 39, count 0 2006.217.08:03:38.88#ibcon#end of sib2, iclass 39, count 0 2006.217.08:03:38.88#ibcon#*mode == 0, iclass 39, count 0 2006.217.08:03:38.88#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.217.08:03:38.88#ibcon#[25=USB\r\n] 2006.217.08:03:38.88#ibcon#*before write, iclass 39, count 0 2006.217.08:03:38.88#ibcon#enter sib2, iclass 39, count 0 2006.217.08:03:38.88#ibcon#flushed, iclass 39, count 0 2006.217.08:03:38.88#ibcon#about to write, iclass 39, count 0 2006.217.08:03:38.88#ibcon#wrote, iclass 39, count 0 2006.217.08:03:38.88#ibcon#about to read 3, iclass 39, count 0 2006.217.08:03:38.91#ibcon#read 3, iclass 39, count 0 2006.217.08:03:38.91#ibcon#about to read 4, iclass 39, count 0 2006.217.08:03:38.91#ibcon#read 4, iclass 39, count 0 2006.217.08:03:38.91#ibcon#about to read 5, iclass 39, count 0 2006.217.08:03:38.91#ibcon#read 5, iclass 39, count 0 2006.217.08:03:38.91#ibcon#about to read 6, iclass 39, count 0 2006.217.08:03:38.91#ibcon#read 6, iclass 39, count 0 2006.217.08:03:38.91#ibcon#end of sib2, iclass 39, count 0 2006.217.08:03:38.91#ibcon#*after write, iclass 39, count 0 2006.217.08:03:38.91#ibcon#*before return 0, iclass 39, count 0 2006.217.08:03:38.91#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.217.08:03:38.91#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.217.08:03:38.91#ibcon#about to clear, iclass 39 cls_cnt 0 2006.217.08:03:38.91#ibcon#cleared, iclass 39 cls_cnt 0 2006.217.08:03:38.91$vc4f8/valo=4,832.99 2006.217.08:03:38.91#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.217.08:03:38.91#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.217.08:03:38.91#ibcon#ireg 17 cls_cnt 0 2006.217.08:03:38.91#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.217.08:03:38.91#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.217.08:03:38.91#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.217.08:03:38.91#ibcon#enter wrdev, iclass 3, count 0 2006.217.08:03:38.91#ibcon#first serial, iclass 3, count 0 2006.217.08:03:38.91#ibcon#enter sib2, iclass 3, count 0 2006.217.08:03:38.91#ibcon#flushed, iclass 3, count 0 2006.217.08:03:38.91#ibcon#about to write, iclass 3, count 0 2006.217.08:03:38.91#ibcon#wrote, iclass 3, count 0 2006.217.08:03:38.91#ibcon#about to read 3, iclass 3, count 0 2006.217.08:03:38.93#ibcon#read 3, iclass 3, count 0 2006.217.08:03:38.93#ibcon#about to read 4, iclass 3, count 0 2006.217.08:03:38.93#ibcon#read 4, iclass 3, count 0 2006.217.08:03:38.93#ibcon#about to read 5, iclass 3, count 0 2006.217.08:03:38.93#ibcon#read 5, iclass 3, count 0 2006.217.08:03:38.93#ibcon#about to read 6, iclass 3, count 0 2006.217.08:03:38.93#ibcon#read 6, iclass 3, count 0 2006.217.08:03:38.93#ibcon#end of sib2, iclass 3, count 0 2006.217.08:03:38.93#ibcon#*mode == 0, iclass 3, count 0 2006.217.08:03:38.93#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.217.08:03:38.93#ibcon#[26=FRQ=04,832.99\r\n] 2006.217.08:03:38.93#ibcon#*before write, iclass 3, count 0 2006.217.08:03:38.93#ibcon#enter sib2, iclass 3, count 0 2006.217.08:03:38.93#ibcon#flushed, iclass 3, count 0 2006.217.08:03:38.93#ibcon#about to write, iclass 3, count 0 2006.217.08:03:38.93#ibcon#wrote, iclass 3, count 0 2006.217.08:03:38.93#ibcon#about to read 3, iclass 3, count 0 2006.217.08:03:38.97#ibcon#read 3, iclass 3, count 0 2006.217.08:03:38.97#ibcon#about to read 4, iclass 3, count 0 2006.217.08:03:38.97#ibcon#read 4, iclass 3, count 0 2006.217.08:03:38.97#ibcon#about to read 5, iclass 3, count 0 2006.217.08:03:38.97#ibcon#read 5, iclass 3, count 0 2006.217.08:03:38.97#ibcon#about to read 6, iclass 3, count 0 2006.217.08:03:38.97#ibcon#read 6, iclass 3, count 0 2006.217.08:03:38.97#ibcon#end of sib2, iclass 3, count 0 2006.217.08:03:38.97#ibcon#*after write, iclass 3, count 0 2006.217.08:03:38.97#ibcon#*before return 0, iclass 3, count 0 2006.217.08:03:38.97#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.217.08:03:38.97#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.217.08:03:38.97#ibcon#about to clear, iclass 3 cls_cnt 0 2006.217.08:03:38.97#ibcon#cleared, iclass 3 cls_cnt 0 2006.217.08:03:38.97$vc4f8/va=4,4 2006.217.08:03:38.97#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.217.08:03:38.97#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.217.08:03:38.97#ibcon#ireg 11 cls_cnt 2 2006.217.08:03:38.97#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.217.08:03:39.03#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.217.08:03:39.03#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.217.08:03:39.03#ibcon#enter wrdev, iclass 5, count 2 2006.217.08:03:39.03#ibcon#first serial, iclass 5, count 2 2006.217.08:03:39.03#ibcon#enter sib2, iclass 5, count 2 2006.217.08:03:39.03#ibcon#flushed, iclass 5, count 2 2006.217.08:03:39.03#ibcon#about to write, iclass 5, count 2 2006.217.08:03:39.03#ibcon#wrote, iclass 5, count 2 2006.217.08:03:39.03#ibcon#about to read 3, iclass 5, count 2 2006.217.08:03:39.05#ibcon#read 3, iclass 5, count 2 2006.217.08:03:39.05#ibcon#about to read 4, iclass 5, count 2 2006.217.08:03:39.05#ibcon#read 4, iclass 5, count 2 2006.217.08:03:39.05#ibcon#about to read 5, iclass 5, count 2 2006.217.08:03:39.05#ibcon#read 5, iclass 5, count 2 2006.217.08:03:39.05#ibcon#about to read 6, iclass 5, count 2 2006.217.08:03:39.05#ibcon#read 6, iclass 5, count 2 2006.217.08:03:39.05#ibcon#end of sib2, iclass 5, count 2 2006.217.08:03:39.05#ibcon#*mode == 0, iclass 5, count 2 2006.217.08:03:39.05#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.217.08:03:39.05#ibcon#[25=AT04-04\r\n] 2006.217.08:03:39.05#ibcon#*before write, iclass 5, count 2 2006.217.08:03:39.05#ibcon#enter sib2, iclass 5, count 2 2006.217.08:03:39.05#ibcon#flushed, iclass 5, count 2 2006.217.08:03:39.05#ibcon#about to write, iclass 5, count 2 2006.217.08:03:39.05#ibcon#wrote, iclass 5, count 2 2006.217.08:03:39.05#ibcon#about to read 3, iclass 5, count 2 2006.217.08:03:39.08#ibcon#read 3, iclass 5, count 2 2006.217.08:03:39.08#ibcon#about to read 4, iclass 5, count 2 2006.217.08:03:39.08#ibcon#read 4, iclass 5, count 2 2006.217.08:03:39.08#ibcon#about to read 5, iclass 5, count 2 2006.217.08:03:39.08#ibcon#read 5, iclass 5, count 2 2006.217.08:03:39.08#ibcon#about to read 6, iclass 5, count 2 2006.217.08:03:39.08#ibcon#read 6, iclass 5, count 2 2006.217.08:03:39.08#ibcon#end of sib2, iclass 5, count 2 2006.217.08:03:39.08#ibcon#*after write, iclass 5, count 2 2006.217.08:03:39.08#ibcon#*before return 0, iclass 5, count 2 2006.217.08:03:39.08#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.217.08:03:39.08#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.217.08:03:39.08#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.217.08:03:39.08#ibcon#ireg 7 cls_cnt 0 2006.217.08:03:39.08#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.217.08:03:39.20#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.217.08:03:39.20#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.217.08:03:39.20#ibcon#enter wrdev, iclass 5, count 0 2006.217.08:03:39.20#ibcon#first serial, iclass 5, count 0 2006.217.08:03:39.20#ibcon#enter sib2, iclass 5, count 0 2006.217.08:03:39.20#ibcon#flushed, iclass 5, count 0 2006.217.08:03:39.20#ibcon#about to write, iclass 5, count 0 2006.217.08:03:39.20#ibcon#wrote, iclass 5, count 0 2006.217.08:03:39.20#ibcon#about to read 3, iclass 5, count 0 2006.217.08:03:39.22#ibcon#read 3, iclass 5, count 0 2006.217.08:03:39.22#ibcon#about to read 4, iclass 5, count 0 2006.217.08:03:39.22#ibcon#read 4, iclass 5, count 0 2006.217.08:03:39.22#ibcon#about to read 5, iclass 5, count 0 2006.217.08:03:39.22#ibcon#read 5, iclass 5, count 0 2006.217.08:03:39.22#ibcon#about to read 6, iclass 5, count 0 2006.217.08:03:39.22#ibcon#read 6, iclass 5, count 0 2006.217.08:03:39.22#ibcon#end of sib2, iclass 5, count 0 2006.217.08:03:39.22#ibcon#*mode == 0, iclass 5, count 0 2006.217.08:03:39.22#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.217.08:03:39.22#ibcon#[25=USB\r\n] 2006.217.08:03:39.22#ibcon#*before write, iclass 5, count 0 2006.217.08:03:39.22#ibcon#enter sib2, iclass 5, count 0 2006.217.08:03:39.22#ibcon#flushed, iclass 5, count 0 2006.217.08:03:39.22#ibcon#about to write, iclass 5, count 0 2006.217.08:03:39.22#ibcon#wrote, iclass 5, count 0 2006.217.08:03:39.22#ibcon#about to read 3, iclass 5, count 0 2006.217.08:03:39.25#ibcon#read 3, iclass 5, count 0 2006.217.08:03:39.25#ibcon#about to read 4, iclass 5, count 0 2006.217.08:03:39.25#ibcon#read 4, iclass 5, count 0 2006.217.08:03:39.25#ibcon#about to read 5, iclass 5, count 0 2006.217.08:03:39.25#ibcon#read 5, iclass 5, count 0 2006.217.08:03:39.25#ibcon#about to read 6, iclass 5, count 0 2006.217.08:03:39.25#ibcon#read 6, iclass 5, count 0 2006.217.08:03:39.25#ibcon#end of sib2, iclass 5, count 0 2006.217.08:03:39.25#ibcon#*after write, iclass 5, count 0 2006.217.08:03:39.25#ibcon#*before return 0, iclass 5, count 0 2006.217.08:03:39.25#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.217.08:03:39.25#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.217.08:03:39.25#ibcon#about to clear, iclass 5 cls_cnt 0 2006.217.08:03:39.25#ibcon#cleared, iclass 5 cls_cnt 0 2006.217.08:03:39.25$vc4f8/valo=5,652.99 2006.217.08:03:39.25#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.217.08:03:39.25#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.217.08:03:39.25#ibcon#ireg 17 cls_cnt 0 2006.217.08:03:39.25#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.217.08:03:39.25#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.217.08:03:39.25#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.217.08:03:39.25#ibcon#enter wrdev, iclass 7, count 0 2006.217.08:03:39.25#ibcon#first serial, iclass 7, count 0 2006.217.08:03:39.25#ibcon#enter sib2, iclass 7, count 0 2006.217.08:03:39.25#ibcon#flushed, iclass 7, count 0 2006.217.08:03:39.25#ibcon#about to write, iclass 7, count 0 2006.217.08:03:39.25#ibcon#wrote, iclass 7, count 0 2006.217.08:03:39.25#ibcon#about to read 3, iclass 7, count 0 2006.217.08:03:39.27#ibcon#read 3, iclass 7, count 0 2006.217.08:03:39.27#ibcon#about to read 4, iclass 7, count 0 2006.217.08:03:39.27#ibcon#read 4, iclass 7, count 0 2006.217.08:03:39.27#ibcon#about to read 5, iclass 7, count 0 2006.217.08:03:39.27#ibcon#read 5, iclass 7, count 0 2006.217.08:03:39.27#ibcon#about to read 6, iclass 7, count 0 2006.217.08:03:39.27#ibcon#read 6, iclass 7, count 0 2006.217.08:03:39.27#ibcon#end of sib2, iclass 7, count 0 2006.217.08:03:39.27#ibcon#*mode == 0, iclass 7, count 0 2006.217.08:03:39.27#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.217.08:03:39.27#ibcon#[26=FRQ=05,652.99\r\n] 2006.217.08:03:39.27#ibcon#*before write, iclass 7, count 0 2006.217.08:03:39.27#ibcon#enter sib2, iclass 7, count 0 2006.217.08:03:39.27#ibcon#flushed, iclass 7, count 0 2006.217.08:03:39.27#ibcon#about to write, iclass 7, count 0 2006.217.08:03:39.27#ibcon#wrote, iclass 7, count 0 2006.217.08:03:39.27#ibcon#about to read 3, iclass 7, count 0 2006.217.08:03:39.31#ibcon#read 3, iclass 7, count 0 2006.217.08:03:39.31#ibcon#about to read 4, iclass 7, count 0 2006.217.08:03:39.31#ibcon#read 4, iclass 7, count 0 2006.217.08:03:39.31#ibcon#about to read 5, iclass 7, count 0 2006.217.08:03:39.31#ibcon#read 5, iclass 7, count 0 2006.217.08:03:39.31#ibcon#about to read 6, iclass 7, count 0 2006.217.08:03:39.31#ibcon#read 6, iclass 7, count 0 2006.217.08:03:39.31#ibcon#end of sib2, iclass 7, count 0 2006.217.08:03:39.31#ibcon#*after write, iclass 7, count 0 2006.217.08:03:39.31#ibcon#*before return 0, iclass 7, count 0 2006.217.08:03:39.31#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.217.08:03:39.31#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.217.08:03:39.31#ibcon#about to clear, iclass 7 cls_cnt 0 2006.217.08:03:39.31#ibcon#cleared, iclass 7 cls_cnt 0 2006.217.08:03:39.31$vc4f8/va=5,7 2006.217.08:03:39.31#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.217.08:03:39.31#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.217.08:03:39.31#ibcon#ireg 11 cls_cnt 2 2006.217.08:03:39.31#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.217.08:03:39.37#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.217.08:03:39.37#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.217.08:03:39.37#ibcon#enter wrdev, iclass 11, count 2 2006.217.08:03:39.37#ibcon#first serial, iclass 11, count 2 2006.217.08:03:39.37#ibcon#enter sib2, iclass 11, count 2 2006.217.08:03:39.37#ibcon#flushed, iclass 11, count 2 2006.217.08:03:39.37#ibcon#about to write, iclass 11, count 2 2006.217.08:03:39.37#ibcon#wrote, iclass 11, count 2 2006.217.08:03:39.37#ibcon#about to read 3, iclass 11, count 2 2006.217.08:03:39.39#ibcon#read 3, iclass 11, count 2 2006.217.08:03:39.39#ibcon#about to read 4, iclass 11, count 2 2006.217.08:03:39.39#ibcon#read 4, iclass 11, count 2 2006.217.08:03:39.39#ibcon#about to read 5, iclass 11, count 2 2006.217.08:03:39.39#ibcon#read 5, iclass 11, count 2 2006.217.08:03:39.39#ibcon#about to read 6, iclass 11, count 2 2006.217.08:03:39.39#ibcon#read 6, iclass 11, count 2 2006.217.08:03:39.39#ibcon#end of sib2, iclass 11, count 2 2006.217.08:03:39.39#ibcon#*mode == 0, iclass 11, count 2 2006.217.08:03:39.39#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.217.08:03:39.39#ibcon#[25=AT05-07\r\n] 2006.217.08:03:39.39#ibcon#*before write, iclass 11, count 2 2006.217.08:03:39.39#ibcon#enter sib2, iclass 11, count 2 2006.217.08:03:39.39#ibcon#flushed, iclass 11, count 2 2006.217.08:03:39.39#ibcon#about to write, iclass 11, count 2 2006.217.08:03:39.39#ibcon#wrote, iclass 11, count 2 2006.217.08:03:39.39#ibcon#about to read 3, iclass 11, count 2 2006.217.08:03:39.42#ibcon#read 3, iclass 11, count 2 2006.217.08:03:39.42#ibcon#about to read 4, iclass 11, count 2 2006.217.08:03:39.42#ibcon#read 4, iclass 11, count 2 2006.217.08:03:39.42#ibcon#about to read 5, iclass 11, count 2 2006.217.08:03:39.42#ibcon#read 5, iclass 11, count 2 2006.217.08:03:39.42#ibcon#about to read 6, iclass 11, count 2 2006.217.08:03:39.42#ibcon#read 6, iclass 11, count 2 2006.217.08:03:39.42#ibcon#end of sib2, iclass 11, count 2 2006.217.08:03:39.42#ibcon#*after write, iclass 11, count 2 2006.217.08:03:39.42#ibcon#*before return 0, iclass 11, count 2 2006.217.08:03:39.42#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.217.08:03:39.42#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.217.08:03:39.42#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.217.08:03:39.42#ibcon#ireg 7 cls_cnt 0 2006.217.08:03:39.42#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.217.08:03:39.54#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.217.08:03:39.54#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.217.08:03:39.54#ibcon#enter wrdev, iclass 11, count 0 2006.217.08:03:39.54#ibcon#first serial, iclass 11, count 0 2006.217.08:03:39.54#ibcon#enter sib2, iclass 11, count 0 2006.217.08:03:39.54#ibcon#flushed, iclass 11, count 0 2006.217.08:03:39.54#ibcon#about to write, iclass 11, count 0 2006.217.08:03:39.54#ibcon#wrote, iclass 11, count 0 2006.217.08:03:39.54#ibcon#about to read 3, iclass 11, count 0 2006.217.08:03:39.56#ibcon#read 3, iclass 11, count 0 2006.217.08:03:39.56#ibcon#about to read 4, iclass 11, count 0 2006.217.08:03:39.56#ibcon#read 4, iclass 11, count 0 2006.217.08:03:39.56#ibcon#about to read 5, iclass 11, count 0 2006.217.08:03:39.56#ibcon#read 5, iclass 11, count 0 2006.217.08:03:39.56#ibcon#about to read 6, iclass 11, count 0 2006.217.08:03:39.56#ibcon#read 6, iclass 11, count 0 2006.217.08:03:39.56#ibcon#end of sib2, iclass 11, count 0 2006.217.08:03:39.56#ibcon#*mode == 0, iclass 11, count 0 2006.217.08:03:39.56#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.217.08:03:39.56#ibcon#[25=USB\r\n] 2006.217.08:03:39.56#ibcon#*before write, iclass 11, count 0 2006.217.08:03:39.56#ibcon#enter sib2, iclass 11, count 0 2006.217.08:03:39.56#ibcon#flushed, iclass 11, count 0 2006.217.08:03:39.56#ibcon#about to write, iclass 11, count 0 2006.217.08:03:39.56#ibcon#wrote, iclass 11, count 0 2006.217.08:03:39.56#ibcon#about to read 3, iclass 11, count 0 2006.217.08:03:39.59#ibcon#read 3, iclass 11, count 0 2006.217.08:03:39.59#ibcon#about to read 4, iclass 11, count 0 2006.217.08:03:39.59#ibcon#read 4, iclass 11, count 0 2006.217.08:03:39.59#ibcon#about to read 5, iclass 11, count 0 2006.217.08:03:39.59#ibcon#read 5, iclass 11, count 0 2006.217.08:03:39.59#ibcon#about to read 6, iclass 11, count 0 2006.217.08:03:39.59#ibcon#read 6, iclass 11, count 0 2006.217.08:03:39.59#ibcon#end of sib2, iclass 11, count 0 2006.217.08:03:39.59#ibcon#*after write, iclass 11, count 0 2006.217.08:03:39.59#ibcon#*before return 0, iclass 11, count 0 2006.217.08:03:39.59#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.217.08:03:39.59#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.217.08:03:39.59#ibcon#about to clear, iclass 11 cls_cnt 0 2006.217.08:03:39.59#ibcon#cleared, iclass 11 cls_cnt 0 2006.217.08:03:39.59$vc4f8/valo=6,772.99 2006.217.08:03:39.59#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.217.08:03:39.59#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.217.08:03:39.59#ibcon#ireg 17 cls_cnt 0 2006.217.08:03:39.59#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.217.08:03:39.59#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.217.08:03:39.59#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.217.08:03:39.59#ibcon#enter wrdev, iclass 13, count 0 2006.217.08:03:39.59#ibcon#first serial, iclass 13, count 0 2006.217.08:03:39.59#ibcon#enter sib2, iclass 13, count 0 2006.217.08:03:39.59#ibcon#flushed, iclass 13, count 0 2006.217.08:03:39.59#ibcon#about to write, iclass 13, count 0 2006.217.08:03:39.59#ibcon#wrote, iclass 13, count 0 2006.217.08:03:39.59#ibcon#about to read 3, iclass 13, count 0 2006.217.08:03:39.61#ibcon#read 3, iclass 13, count 0 2006.217.08:03:39.61#ibcon#about to read 4, iclass 13, count 0 2006.217.08:03:39.61#ibcon#read 4, iclass 13, count 0 2006.217.08:03:39.61#ibcon#about to read 5, iclass 13, count 0 2006.217.08:03:39.61#ibcon#read 5, iclass 13, count 0 2006.217.08:03:39.61#ibcon#about to read 6, iclass 13, count 0 2006.217.08:03:39.61#ibcon#read 6, iclass 13, count 0 2006.217.08:03:39.61#ibcon#end of sib2, iclass 13, count 0 2006.217.08:03:39.61#ibcon#*mode == 0, iclass 13, count 0 2006.217.08:03:39.61#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.217.08:03:39.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.217.08:03:39.61#ibcon#*before write, iclass 13, count 0 2006.217.08:03:39.61#ibcon#enter sib2, iclass 13, count 0 2006.217.08:03:39.61#ibcon#flushed, iclass 13, count 0 2006.217.08:03:39.61#ibcon#about to write, iclass 13, count 0 2006.217.08:03:39.61#ibcon#wrote, iclass 13, count 0 2006.217.08:03:39.61#ibcon#about to read 3, iclass 13, count 0 2006.217.08:03:39.65#ibcon#read 3, iclass 13, count 0 2006.217.08:03:39.65#ibcon#about to read 4, iclass 13, count 0 2006.217.08:03:39.65#ibcon#read 4, iclass 13, count 0 2006.217.08:03:39.65#ibcon#about to read 5, iclass 13, count 0 2006.217.08:03:39.65#ibcon#read 5, iclass 13, count 0 2006.217.08:03:39.65#ibcon#about to read 6, iclass 13, count 0 2006.217.08:03:39.65#ibcon#read 6, iclass 13, count 0 2006.217.08:03:39.65#ibcon#end of sib2, iclass 13, count 0 2006.217.08:03:39.65#ibcon#*after write, iclass 13, count 0 2006.217.08:03:39.65#ibcon#*before return 0, iclass 13, count 0 2006.217.08:03:39.65#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.217.08:03:39.65#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.217.08:03:39.65#ibcon#about to clear, iclass 13 cls_cnt 0 2006.217.08:03:39.65#ibcon#cleared, iclass 13 cls_cnt 0 2006.217.08:03:39.65$vc4f8/va=6,6 2006.217.08:03:39.65#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.217.08:03:39.65#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.217.08:03:39.65#ibcon#ireg 11 cls_cnt 2 2006.217.08:03:39.65#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.217.08:03:39.71#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.217.08:03:39.71#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.217.08:03:39.71#ibcon#enter wrdev, iclass 15, count 2 2006.217.08:03:39.71#ibcon#first serial, iclass 15, count 2 2006.217.08:03:39.71#ibcon#enter sib2, iclass 15, count 2 2006.217.08:03:39.71#ibcon#flushed, iclass 15, count 2 2006.217.08:03:39.71#ibcon#about to write, iclass 15, count 2 2006.217.08:03:39.71#ibcon#wrote, iclass 15, count 2 2006.217.08:03:39.72#ibcon#about to read 3, iclass 15, count 2 2006.217.08:03:39.73#ibcon#read 3, iclass 15, count 2 2006.217.08:03:39.73#ibcon#about to read 4, iclass 15, count 2 2006.217.08:03:39.73#ibcon#read 4, iclass 15, count 2 2006.217.08:03:39.73#ibcon#about to read 5, iclass 15, count 2 2006.217.08:03:39.73#ibcon#read 5, iclass 15, count 2 2006.217.08:03:39.73#ibcon#about to read 6, iclass 15, count 2 2006.217.08:03:39.73#ibcon#read 6, iclass 15, count 2 2006.217.08:03:39.73#ibcon#end of sib2, iclass 15, count 2 2006.217.08:03:39.73#ibcon#*mode == 0, iclass 15, count 2 2006.217.08:03:39.73#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.217.08:03:39.73#ibcon#[25=AT06-06\r\n] 2006.217.08:03:39.73#ibcon#*before write, iclass 15, count 2 2006.217.08:03:39.73#ibcon#enter sib2, iclass 15, count 2 2006.217.08:03:39.73#ibcon#flushed, iclass 15, count 2 2006.217.08:03:39.73#ibcon#about to write, iclass 15, count 2 2006.217.08:03:39.73#ibcon#wrote, iclass 15, count 2 2006.217.08:03:39.73#ibcon#about to read 3, iclass 15, count 2 2006.217.08:03:39.76#ibcon#read 3, iclass 15, count 2 2006.217.08:03:39.76#ibcon#about to read 4, iclass 15, count 2 2006.217.08:03:39.76#ibcon#read 4, iclass 15, count 2 2006.217.08:03:39.76#ibcon#about to read 5, iclass 15, count 2 2006.217.08:03:39.76#ibcon#read 5, iclass 15, count 2 2006.217.08:03:39.76#ibcon#about to read 6, iclass 15, count 2 2006.217.08:03:39.76#ibcon#read 6, iclass 15, count 2 2006.217.08:03:39.76#ibcon#end of sib2, iclass 15, count 2 2006.217.08:03:39.76#ibcon#*after write, iclass 15, count 2 2006.217.08:03:39.76#ibcon#*before return 0, iclass 15, count 2 2006.217.08:03:39.76#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.217.08:03:39.76#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.217.08:03:39.76#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.217.08:03:39.76#ibcon#ireg 7 cls_cnt 0 2006.217.08:03:39.76#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.217.08:03:39.88#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.217.08:03:39.88#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.217.08:03:39.88#ibcon#enter wrdev, iclass 15, count 0 2006.217.08:03:39.88#ibcon#first serial, iclass 15, count 0 2006.217.08:03:39.88#ibcon#enter sib2, iclass 15, count 0 2006.217.08:03:39.88#ibcon#flushed, iclass 15, count 0 2006.217.08:03:39.88#ibcon#about to write, iclass 15, count 0 2006.217.08:03:39.88#ibcon#wrote, iclass 15, count 0 2006.217.08:03:39.88#ibcon#about to read 3, iclass 15, count 0 2006.217.08:03:39.90#ibcon#read 3, iclass 15, count 0 2006.217.08:03:39.90#ibcon#about to read 4, iclass 15, count 0 2006.217.08:03:39.90#ibcon#read 4, iclass 15, count 0 2006.217.08:03:39.90#ibcon#about to read 5, iclass 15, count 0 2006.217.08:03:39.90#ibcon#read 5, iclass 15, count 0 2006.217.08:03:39.90#ibcon#about to read 6, iclass 15, count 0 2006.217.08:03:39.90#ibcon#read 6, iclass 15, count 0 2006.217.08:03:39.90#ibcon#end of sib2, iclass 15, count 0 2006.217.08:03:39.90#ibcon#*mode == 0, iclass 15, count 0 2006.217.08:03:39.90#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.217.08:03:39.90#ibcon#[25=USB\r\n] 2006.217.08:03:39.90#ibcon#*before write, iclass 15, count 0 2006.217.08:03:39.90#ibcon#enter sib2, iclass 15, count 0 2006.217.08:03:39.90#ibcon#flushed, iclass 15, count 0 2006.217.08:03:39.90#ibcon#about to write, iclass 15, count 0 2006.217.08:03:39.90#ibcon#wrote, iclass 15, count 0 2006.217.08:03:39.90#ibcon#about to read 3, iclass 15, count 0 2006.217.08:03:39.93#ibcon#read 3, iclass 15, count 0 2006.217.08:03:39.93#ibcon#about to read 4, iclass 15, count 0 2006.217.08:03:39.93#ibcon#read 4, iclass 15, count 0 2006.217.08:03:39.93#ibcon#about to read 5, iclass 15, count 0 2006.217.08:03:39.93#ibcon#read 5, iclass 15, count 0 2006.217.08:03:39.93#ibcon#about to read 6, iclass 15, count 0 2006.217.08:03:39.93#ibcon#read 6, iclass 15, count 0 2006.217.08:03:39.93#ibcon#end of sib2, iclass 15, count 0 2006.217.08:03:39.93#ibcon#*after write, iclass 15, count 0 2006.217.08:03:39.93#ibcon#*before return 0, iclass 15, count 0 2006.217.08:03:39.93#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.217.08:03:39.93#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.217.08:03:39.93#ibcon#about to clear, iclass 15 cls_cnt 0 2006.217.08:03:39.93#ibcon#cleared, iclass 15 cls_cnt 0 2006.217.08:03:39.93$vc4f8/valo=7,832.99 2006.217.08:03:39.93#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.217.08:03:39.93#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.217.08:03:39.93#ibcon#ireg 17 cls_cnt 0 2006.217.08:03:39.93#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.217.08:03:39.93#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.217.08:03:39.93#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.217.08:03:39.93#ibcon#enter wrdev, iclass 17, count 0 2006.217.08:03:39.93#ibcon#first serial, iclass 17, count 0 2006.217.08:03:39.93#ibcon#enter sib2, iclass 17, count 0 2006.217.08:03:39.93#ibcon#flushed, iclass 17, count 0 2006.217.08:03:39.93#ibcon#about to write, iclass 17, count 0 2006.217.08:03:39.93#ibcon#wrote, iclass 17, count 0 2006.217.08:03:39.93#ibcon#about to read 3, iclass 17, count 0 2006.217.08:03:39.95#ibcon#read 3, iclass 17, count 0 2006.217.08:03:39.95#ibcon#about to read 4, iclass 17, count 0 2006.217.08:03:39.95#ibcon#read 4, iclass 17, count 0 2006.217.08:03:39.95#ibcon#about to read 5, iclass 17, count 0 2006.217.08:03:39.95#ibcon#read 5, iclass 17, count 0 2006.217.08:03:39.95#ibcon#about to read 6, iclass 17, count 0 2006.217.08:03:39.95#ibcon#read 6, iclass 17, count 0 2006.217.08:03:39.95#ibcon#end of sib2, iclass 17, count 0 2006.217.08:03:39.95#ibcon#*mode == 0, iclass 17, count 0 2006.217.08:03:39.95#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.217.08:03:39.95#ibcon#[26=FRQ=07,832.99\r\n] 2006.217.08:03:39.95#ibcon#*before write, iclass 17, count 0 2006.217.08:03:39.95#ibcon#enter sib2, iclass 17, count 0 2006.217.08:03:39.95#ibcon#flushed, iclass 17, count 0 2006.217.08:03:39.95#ibcon#about to write, iclass 17, count 0 2006.217.08:03:39.95#ibcon#wrote, iclass 17, count 0 2006.217.08:03:39.95#ibcon#about to read 3, iclass 17, count 0 2006.217.08:03:39.99#ibcon#read 3, iclass 17, count 0 2006.217.08:03:39.99#ibcon#about to read 4, iclass 17, count 0 2006.217.08:03:39.99#ibcon#read 4, iclass 17, count 0 2006.217.08:03:39.99#ibcon#about to read 5, iclass 17, count 0 2006.217.08:03:39.99#ibcon#read 5, iclass 17, count 0 2006.217.08:03:39.99#ibcon#about to read 6, iclass 17, count 0 2006.217.08:03:39.99#ibcon#read 6, iclass 17, count 0 2006.217.08:03:39.99#ibcon#end of sib2, iclass 17, count 0 2006.217.08:03:39.99#ibcon#*after write, iclass 17, count 0 2006.217.08:03:39.99#ibcon#*before return 0, iclass 17, count 0 2006.217.08:03:39.99#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.217.08:03:39.99#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.217.08:03:39.99#ibcon#about to clear, iclass 17 cls_cnt 0 2006.217.08:03:39.99#ibcon#cleared, iclass 17 cls_cnt 0 2006.217.08:03:39.99$vc4f8/va=7,6 2006.217.08:03:39.99#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.217.08:03:39.99#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.217.08:03:39.99#ibcon#ireg 11 cls_cnt 2 2006.217.08:03:39.99#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.217.08:03:40.05#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.217.08:03:40.05#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.217.08:03:40.05#ibcon#enter wrdev, iclass 19, count 2 2006.217.08:03:40.05#ibcon#first serial, iclass 19, count 2 2006.217.08:03:40.05#ibcon#enter sib2, iclass 19, count 2 2006.217.08:03:40.05#ibcon#flushed, iclass 19, count 2 2006.217.08:03:40.05#ibcon#about to write, iclass 19, count 2 2006.217.08:03:40.05#ibcon#wrote, iclass 19, count 2 2006.217.08:03:40.05#ibcon#about to read 3, iclass 19, count 2 2006.217.08:03:40.07#ibcon#read 3, iclass 19, count 2 2006.217.08:03:40.07#ibcon#about to read 4, iclass 19, count 2 2006.217.08:03:40.07#ibcon#read 4, iclass 19, count 2 2006.217.08:03:40.07#ibcon#about to read 5, iclass 19, count 2 2006.217.08:03:40.07#ibcon#read 5, iclass 19, count 2 2006.217.08:03:40.07#ibcon#about to read 6, iclass 19, count 2 2006.217.08:03:40.07#ibcon#read 6, iclass 19, count 2 2006.217.08:03:40.07#ibcon#end of sib2, iclass 19, count 2 2006.217.08:03:40.07#ibcon#*mode == 0, iclass 19, count 2 2006.217.08:03:40.07#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.217.08:03:40.07#ibcon#[25=AT07-06\r\n] 2006.217.08:03:40.07#ibcon#*before write, iclass 19, count 2 2006.217.08:03:40.07#ibcon#enter sib2, iclass 19, count 2 2006.217.08:03:40.07#ibcon#flushed, iclass 19, count 2 2006.217.08:03:40.07#ibcon#about to write, iclass 19, count 2 2006.217.08:03:40.07#ibcon#wrote, iclass 19, count 2 2006.217.08:03:40.07#ibcon#about to read 3, iclass 19, count 2 2006.217.08:03:40.10#ibcon#read 3, iclass 19, count 2 2006.217.08:03:40.10#ibcon#about to read 4, iclass 19, count 2 2006.217.08:03:40.10#ibcon#read 4, iclass 19, count 2 2006.217.08:03:40.10#ibcon#about to read 5, iclass 19, count 2 2006.217.08:03:40.10#ibcon#read 5, iclass 19, count 2 2006.217.08:03:40.10#ibcon#about to read 6, iclass 19, count 2 2006.217.08:03:40.10#ibcon#read 6, iclass 19, count 2 2006.217.08:03:40.10#ibcon#end of sib2, iclass 19, count 2 2006.217.08:03:40.10#ibcon#*after write, iclass 19, count 2 2006.217.08:03:40.10#ibcon#*before return 0, iclass 19, count 2 2006.217.08:03:40.10#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.217.08:03:40.10#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.217.08:03:40.10#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.217.08:03:40.10#ibcon#ireg 7 cls_cnt 0 2006.217.08:03:40.10#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.217.08:03:40.22#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.217.08:03:40.22#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.217.08:03:40.22#ibcon#enter wrdev, iclass 19, count 0 2006.217.08:03:40.22#ibcon#first serial, iclass 19, count 0 2006.217.08:03:40.22#ibcon#enter sib2, iclass 19, count 0 2006.217.08:03:40.22#ibcon#flushed, iclass 19, count 0 2006.217.08:03:40.22#ibcon#about to write, iclass 19, count 0 2006.217.08:03:40.22#ibcon#wrote, iclass 19, count 0 2006.217.08:03:40.22#ibcon#about to read 3, iclass 19, count 0 2006.217.08:03:40.24#ibcon#read 3, iclass 19, count 0 2006.217.08:03:40.24#ibcon#about to read 4, iclass 19, count 0 2006.217.08:03:40.24#ibcon#read 4, iclass 19, count 0 2006.217.08:03:40.24#ibcon#about to read 5, iclass 19, count 0 2006.217.08:03:40.24#ibcon#read 5, iclass 19, count 0 2006.217.08:03:40.24#ibcon#about to read 6, iclass 19, count 0 2006.217.08:03:40.24#ibcon#read 6, iclass 19, count 0 2006.217.08:03:40.24#ibcon#end of sib2, iclass 19, count 0 2006.217.08:03:40.24#ibcon#*mode == 0, iclass 19, count 0 2006.217.08:03:40.24#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.217.08:03:40.24#ibcon#[25=USB\r\n] 2006.217.08:03:40.24#ibcon#*before write, iclass 19, count 0 2006.217.08:03:40.24#ibcon#enter sib2, iclass 19, count 0 2006.217.08:03:40.24#ibcon#flushed, iclass 19, count 0 2006.217.08:03:40.24#ibcon#about to write, iclass 19, count 0 2006.217.08:03:40.24#ibcon#wrote, iclass 19, count 0 2006.217.08:03:40.24#ibcon#about to read 3, iclass 19, count 0 2006.217.08:03:40.27#ibcon#read 3, iclass 19, count 0 2006.217.08:03:40.27#ibcon#about to read 4, iclass 19, count 0 2006.217.08:03:40.27#ibcon#read 4, iclass 19, count 0 2006.217.08:03:40.27#ibcon#about to read 5, iclass 19, count 0 2006.217.08:03:40.27#ibcon#read 5, iclass 19, count 0 2006.217.08:03:40.27#ibcon#about to read 6, iclass 19, count 0 2006.217.08:03:40.27#ibcon#read 6, iclass 19, count 0 2006.217.08:03:40.27#ibcon#end of sib2, iclass 19, count 0 2006.217.08:03:40.27#ibcon#*after write, iclass 19, count 0 2006.217.08:03:40.27#ibcon#*before return 0, iclass 19, count 0 2006.217.08:03:40.27#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.217.08:03:40.27#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.217.08:03:40.27#ibcon#about to clear, iclass 19 cls_cnt 0 2006.217.08:03:40.27#ibcon#cleared, iclass 19 cls_cnt 0 2006.217.08:03:40.27$vc4f8/valo=8,852.99 2006.217.08:03:40.27#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.217.08:03:40.27#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.217.08:03:40.27#ibcon#ireg 17 cls_cnt 0 2006.217.08:03:40.27#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.217.08:03:40.27#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.217.08:03:40.27#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.217.08:03:40.27#ibcon#enter wrdev, iclass 21, count 0 2006.217.08:03:40.27#ibcon#first serial, iclass 21, count 0 2006.217.08:03:40.27#ibcon#enter sib2, iclass 21, count 0 2006.217.08:03:40.27#ibcon#flushed, iclass 21, count 0 2006.217.08:03:40.27#ibcon#about to write, iclass 21, count 0 2006.217.08:03:40.27#ibcon#wrote, iclass 21, count 0 2006.217.08:03:40.27#ibcon#about to read 3, iclass 21, count 0 2006.217.08:03:40.29#ibcon#read 3, iclass 21, count 0 2006.217.08:03:40.29#ibcon#about to read 4, iclass 21, count 0 2006.217.08:03:40.29#ibcon#read 4, iclass 21, count 0 2006.217.08:03:40.29#ibcon#about to read 5, iclass 21, count 0 2006.217.08:03:40.29#ibcon#read 5, iclass 21, count 0 2006.217.08:03:40.29#ibcon#about to read 6, iclass 21, count 0 2006.217.08:03:40.29#ibcon#read 6, iclass 21, count 0 2006.217.08:03:40.29#ibcon#end of sib2, iclass 21, count 0 2006.217.08:03:40.29#ibcon#*mode == 0, iclass 21, count 0 2006.217.08:03:40.29#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.217.08:03:40.29#ibcon#[26=FRQ=08,852.99\r\n] 2006.217.08:03:40.29#ibcon#*before write, iclass 21, count 0 2006.217.08:03:40.29#ibcon#enter sib2, iclass 21, count 0 2006.217.08:03:40.29#ibcon#flushed, iclass 21, count 0 2006.217.08:03:40.29#ibcon#about to write, iclass 21, count 0 2006.217.08:03:40.29#ibcon#wrote, iclass 21, count 0 2006.217.08:03:40.29#ibcon#about to read 3, iclass 21, count 0 2006.217.08:03:40.33#ibcon#read 3, iclass 21, count 0 2006.217.08:03:40.33#ibcon#about to read 4, iclass 21, count 0 2006.217.08:03:40.33#ibcon#read 4, iclass 21, count 0 2006.217.08:03:40.33#ibcon#about to read 5, iclass 21, count 0 2006.217.08:03:40.33#ibcon#read 5, iclass 21, count 0 2006.217.08:03:40.33#ibcon#about to read 6, iclass 21, count 0 2006.217.08:03:40.33#ibcon#read 6, iclass 21, count 0 2006.217.08:03:40.33#ibcon#end of sib2, iclass 21, count 0 2006.217.08:03:40.33#ibcon#*after write, iclass 21, count 0 2006.217.08:03:40.33#ibcon#*before return 0, iclass 21, count 0 2006.217.08:03:40.33#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.217.08:03:40.33#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.217.08:03:40.33#ibcon#about to clear, iclass 21 cls_cnt 0 2006.217.08:03:40.33#ibcon#cleared, iclass 21 cls_cnt 0 2006.217.08:03:40.33$vc4f8/va=8,7 2006.217.08:03:40.33#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.217.08:03:40.33#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.217.08:03:40.33#ibcon#ireg 11 cls_cnt 2 2006.217.08:03:40.33#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.217.08:03:40.39#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.217.08:03:40.39#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.217.08:03:40.39#ibcon#enter wrdev, iclass 23, count 2 2006.217.08:03:40.39#ibcon#first serial, iclass 23, count 2 2006.217.08:03:40.39#ibcon#enter sib2, iclass 23, count 2 2006.217.08:03:40.39#ibcon#flushed, iclass 23, count 2 2006.217.08:03:40.39#ibcon#about to write, iclass 23, count 2 2006.217.08:03:40.39#ibcon#wrote, iclass 23, count 2 2006.217.08:03:40.39#ibcon#about to read 3, iclass 23, count 2 2006.217.08:03:40.41#ibcon#read 3, iclass 23, count 2 2006.217.08:03:40.41#ibcon#about to read 4, iclass 23, count 2 2006.217.08:03:40.41#ibcon#read 4, iclass 23, count 2 2006.217.08:03:40.41#ibcon#about to read 5, iclass 23, count 2 2006.217.08:03:40.41#ibcon#read 5, iclass 23, count 2 2006.217.08:03:40.41#ibcon#about to read 6, iclass 23, count 2 2006.217.08:03:40.41#ibcon#read 6, iclass 23, count 2 2006.217.08:03:40.41#ibcon#end of sib2, iclass 23, count 2 2006.217.08:03:40.41#ibcon#*mode == 0, iclass 23, count 2 2006.217.08:03:40.41#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.217.08:03:40.41#ibcon#[25=AT08-07\r\n] 2006.217.08:03:40.41#ibcon#*before write, iclass 23, count 2 2006.217.08:03:40.41#ibcon#enter sib2, iclass 23, count 2 2006.217.08:03:40.41#ibcon#flushed, iclass 23, count 2 2006.217.08:03:40.41#ibcon#about to write, iclass 23, count 2 2006.217.08:03:40.41#ibcon#wrote, iclass 23, count 2 2006.217.08:03:40.41#ibcon#about to read 3, iclass 23, count 2 2006.217.08:03:40.44#ibcon#read 3, iclass 23, count 2 2006.217.08:03:40.44#ibcon#about to read 4, iclass 23, count 2 2006.217.08:03:40.44#ibcon#read 4, iclass 23, count 2 2006.217.08:03:40.44#ibcon#about to read 5, iclass 23, count 2 2006.217.08:03:40.44#ibcon#read 5, iclass 23, count 2 2006.217.08:03:40.44#ibcon#about to read 6, iclass 23, count 2 2006.217.08:03:40.44#ibcon#read 6, iclass 23, count 2 2006.217.08:03:40.44#ibcon#end of sib2, iclass 23, count 2 2006.217.08:03:40.44#ibcon#*after write, iclass 23, count 2 2006.217.08:03:40.44#ibcon#*before return 0, iclass 23, count 2 2006.217.08:03:40.44#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.217.08:03:40.44#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.217.08:03:40.44#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.217.08:03:40.44#ibcon#ireg 7 cls_cnt 0 2006.217.08:03:40.44#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.217.08:03:40.56#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.217.08:03:40.56#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.217.08:03:40.56#ibcon#enter wrdev, iclass 23, count 0 2006.217.08:03:40.56#ibcon#first serial, iclass 23, count 0 2006.217.08:03:40.56#ibcon#enter sib2, iclass 23, count 0 2006.217.08:03:40.56#ibcon#flushed, iclass 23, count 0 2006.217.08:03:40.56#ibcon#about to write, iclass 23, count 0 2006.217.08:03:40.56#ibcon#wrote, iclass 23, count 0 2006.217.08:03:40.56#ibcon#about to read 3, iclass 23, count 0 2006.217.08:03:40.58#ibcon#read 3, iclass 23, count 0 2006.217.08:03:40.58#ibcon#about to read 4, iclass 23, count 0 2006.217.08:03:40.58#ibcon#read 4, iclass 23, count 0 2006.217.08:03:40.58#ibcon#about to read 5, iclass 23, count 0 2006.217.08:03:40.58#ibcon#read 5, iclass 23, count 0 2006.217.08:03:40.58#ibcon#about to read 6, iclass 23, count 0 2006.217.08:03:40.58#ibcon#read 6, iclass 23, count 0 2006.217.08:03:40.58#ibcon#end of sib2, iclass 23, count 0 2006.217.08:03:40.58#ibcon#*mode == 0, iclass 23, count 0 2006.217.08:03:40.58#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.217.08:03:40.58#ibcon#[25=USB\r\n] 2006.217.08:03:40.58#ibcon#*before write, iclass 23, count 0 2006.217.08:03:40.58#ibcon#enter sib2, iclass 23, count 0 2006.217.08:03:40.58#ibcon#flushed, iclass 23, count 0 2006.217.08:03:40.58#ibcon#about to write, iclass 23, count 0 2006.217.08:03:40.58#ibcon#wrote, iclass 23, count 0 2006.217.08:03:40.58#ibcon#about to read 3, iclass 23, count 0 2006.217.08:03:40.61#ibcon#read 3, iclass 23, count 0 2006.217.08:03:40.61#ibcon#about to read 4, iclass 23, count 0 2006.217.08:03:40.61#ibcon#read 4, iclass 23, count 0 2006.217.08:03:40.61#ibcon#about to read 5, iclass 23, count 0 2006.217.08:03:40.61#ibcon#read 5, iclass 23, count 0 2006.217.08:03:40.61#ibcon#about to read 6, iclass 23, count 0 2006.217.08:03:40.61#ibcon#read 6, iclass 23, count 0 2006.217.08:03:40.61#ibcon#end of sib2, iclass 23, count 0 2006.217.08:03:40.61#ibcon#*after write, iclass 23, count 0 2006.217.08:03:40.61#ibcon#*before return 0, iclass 23, count 0 2006.217.08:03:40.61#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.217.08:03:40.61#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.217.08:03:40.61#ibcon#about to clear, iclass 23 cls_cnt 0 2006.217.08:03:40.61#ibcon#cleared, iclass 23 cls_cnt 0 2006.217.08:03:40.61$vc4f8/vblo=1,632.99 2006.217.08:03:40.61#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.217.08:03:40.61#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.217.08:03:40.61#ibcon#ireg 17 cls_cnt 0 2006.217.08:03:40.61#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.217.08:03:40.61#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.217.08:03:40.61#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.217.08:03:40.61#ibcon#enter wrdev, iclass 25, count 0 2006.217.08:03:40.61#ibcon#first serial, iclass 25, count 0 2006.217.08:03:40.61#ibcon#enter sib2, iclass 25, count 0 2006.217.08:03:40.61#ibcon#flushed, iclass 25, count 0 2006.217.08:03:40.61#ibcon#about to write, iclass 25, count 0 2006.217.08:03:40.61#ibcon#wrote, iclass 25, count 0 2006.217.08:03:40.61#ibcon#about to read 3, iclass 25, count 0 2006.217.08:03:40.63#ibcon#read 3, iclass 25, count 0 2006.217.08:03:40.63#ibcon#about to read 4, iclass 25, count 0 2006.217.08:03:40.63#ibcon#read 4, iclass 25, count 0 2006.217.08:03:40.63#ibcon#about to read 5, iclass 25, count 0 2006.217.08:03:40.63#ibcon#read 5, iclass 25, count 0 2006.217.08:03:40.63#ibcon#about to read 6, iclass 25, count 0 2006.217.08:03:40.63#ibcon#read 6, iclass 25, count 0 2006.217.08:03:40.63#ibcon#end of sib2, iclass 25, count 0 2006.217.08:03:40.63#ibcon#*mode == 0, iclass 25, count 0 2006.217.08:03:40.63#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.217.08:03:40.63#ibcon#[28=FRQ=01,632.99\r\n] 2006.217.08:03:40.63#ibcon#*before write, iclass 25, count 0 2006.217.08:03:40.63#ibcon#enter sib2, iclass 25, count 0 2006.217.08:03:40.63#ibcon#flushed, iclass 25, count 0 2006.217.08:03:40.63#ibcon#about to write, iclass 25, count 0 2006.217.08:03:40.63#ibcon#wrote, iclass 25, count 0 2006.217.08:03:40.63#ibcon#about to read 3, iclass 25, count 0 2006.217.08:03:40.67#ibcon#read 3, iclass 25, count 0 2006.217.08:03:40.67#ibcon#about to read 4, iclass 25, count 0 2006.217.08:03:40.67#ibcon#read 4, iclass 25, count 0 2006.217.08:03:40.67#ibcon#about to read 5, iclass 25, count 0 2006.217.08:03:40.67#ibcon#read 5, iclass 25, count 0 2006.217.08:03:40.67#ibcon#about to read 6, iclass 25, count 0 2006.217.08:03:40.67#ibcon#read 6, iclass 25, count 0 2006.217.08:03:40.67#ibcon#end of sib2, iclass 25, count 0 2006.217.08:03:40.67#ibcon#*after write, iclass 25, count 0 2006.217.08:03:40.67#ibcon#*before return 0, iclass 25, count 0 2006.217.08:03:40.67#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.217.08:03:40.67#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.217.08:03:40.67#ibcon#about to clear, iclass 25 cls_cnt 0 2006.217.08:03:40.67#ibcon#cleared, iclass 25 cls_cnt 0 2006.217.08:03:40.67$vc4f8/vb=1,4 2006.217.08:03:40.67#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.217.08:03:40.67#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.217.08:03:40.67#ibcon#ireg 11 cls_cnt 2 2006.217.08:03:40.67#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.217.08:03:40.67#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.217.08:03:40.67#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.217.08:03:40.67#ibcon#enter wrdev, iclass 27, count 2 2006.217.08:03:40.67#ibcon#first serial, iclass 27, count 2 2006.217.08:03:40.67#ibcon#enter sib2, iclass 27, count 2 2006.217.08:03:40.67#ibcon#flushed, iclass 27, count 2 2006.217.08:03:40.67#ibcon#about to write, iclass 27, count 2 2006.217.08:03:40.67#ibcon#wrote, iclass 27, count 2 2006.217.08:03:40.67#ibcon#about to read 3, iclass 27, count 2 2006.217.08:03:40.69#ibcon#read 3, iclass 27, count 2 2006.217.08:03:40.69#ibcon#about to read 4, iclass 27, count 2 2006.217.08:03:40.69#ibcon#read 4, iclass 27, count 2 2006.217.08:03:40.69#ibcon#about to read 5, iclass 27, count 2 2006.217.08:03:40.69#ibcon#read 5, iclass 27, count 2 2006.217.08:03:40.69#ibcon#about to read 6, iclass 27, count 2 2006.217.08:03:40.69#ibcon#read 6, iclass 27, count 2 2006.217.08:03:40.69#ibcon#end of sib2, iclass 27, count 2 2006.217.08:03:40.69#ibcon#*mode == 0, iclass 27, count 2 2006.217.08:03:40.69#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.217.08:03:40.69#ibcon#[27=AT01-04\r\n] 2006.217.08:03:40.69#ibcon#*before write, iclass 27, count 2 2006.217.08:03:40.69#ibcon#enter sib2, iclass 27, count 2 2006.217.08:03:40.69#ibcon#flushed, iclass 27, count 2 2006.217.08:03:40.69#ibcon#about to write, iclass 27, count 2 2006.217.08:03:40.69#ibcon#wrote, iclass 27, count 2 2006.217.08:03:40.69#ibcon#about to read 3, iclass 27, count 2 2006.217.08:03:40.72#ibcon#read 3, iclass 27, count 2 2006.217.08:03:40.72#ibcon#about to read 4, iclass 27, count 2 2006.217.08:03:40.72#ibcon#read 4, iclass 27, count 2 2006.217.08:03:40.72#ibcon#about to read 5, iclass 27, count 2 2006.217.08:03:40.72#ibcon#read 5, iclass 27, count 2 2006.217.08:03:40.72#ibcon#about to read 6, iclass 27, count 2 2006.217.08:03:40.72#ibcon#read 6, iclass 27, count 2 2006.217.08:03:40.72#ibcon#end of sib2, iclass 27, count 2 2006.217.08:03:40.72#ibcon#*after write, iclass 27, count 2 2006.217.08:03:40.72#ibcon#*before return 0, iclass 27, count 2 2006.217.08:03:40.72#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.217.08:03:40.72#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.217.08:03:40.72#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.217.08:03:40.72#ibcon#ireg 7 cls_cnt 0 2006.217.08:03:40.72#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.217.08:03:40.84#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.217.08:03:40.84#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.217.08:03:40.84#ibcon#enter wrdev, iclass 27, count 0 2006.217.08:03:40.84#ibcon#first serial, iclass 27, count 0 2006.217.08:03:40.84#ibcon#enter sib2, iclass 27, count 0 2006.217.08:03:40.84#ibcon#flushed, iclass 27, count 0 2006.217.08:03:40.84#ibcon#about to write, iclass 27, count 0 2006.217.08:03:40.84#ibcon#wrote, iclass 27, count 0 2006.217.08:03:40.84#ibcon#about to read 3, iclass 27, count 0 2006.217.08:03:40.86#ibcon#read 3, iclass 27, count 0 2006.217.08:03:40.86#ibcon#about to read 4, iclass 27, count 0 2006.217.08:03:40.86#ibcon#read 4, iclass 27, count 0 2006.217.08:03:40.86#ibcon#about to read 5, iclass 27, count 0 2006.217.08:03:40.86#ibcon#read 5, iclass 27, count 0 2006.217.08:03:40.86#ibcon#about to read 6, iclass 27, count 0 2006.217.08:03:40.86#ibcon#read 6, iclass 27, count 0 2006.217.08:03:40.86#ibcon#end of sib2, iclass 27, count 0 2006.217.08:03:40.86#ibcon#*mode == 0, iclass 27, count 0 2006.217.08:03:40.86#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.217.08:03:40.86#ibcon#[27=USB\r\n] 2006.217.08:03:40.86#ibcon#*before write, iclass 27, count 0 2006.217.08:03:40.86#ibcon#enter sib2, iclass 27, count 0 2006.217.08:03:40.86#ibcon#flushed, iclass 27, count 0 2006.217.08:03:40.86#ibcon#about to write, iclass 27, count 0 2006.217.08:03:40.86#ibcon#wrote, iclass 27, count 0 2006.217.08:03:40.86#ibcon#about to read 3, iclass 27, count 0 2006.217.08:03:40.89#ibcon#read 3, iclass 27, count 0 2006.217.08:03:40.89#ibcon#about to read 4, iclass 27, count 0 2006.217.08:03:40.89#ibcon#read 4, iclass 27, count 0 2006.217.08:03:40.89#ibcon#about to read 5, iclass 27, count 0 2006.217.08:03:40.89#ibcon#read 5, iclass 27, count 0 2006.217.08:03:40.89#ibcon#about to read 6, iclass 27, count 0 2006.217.08:03:40.89#ibcon#read 6, iclass 27, count 0 2006.217.08:03:40.89#ibcon#end of sib2, iclass 27, count 0 2006.217.08:03:40.89#ibcon#*after write, iclass 27, count 0 2006.217.08:03:40.89#ibcon#*before return 0, iclass 27, count 0 2006.217.08:03:40.89#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.217.08:03:40.89#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.217.08:03:40.89#ibcon#about to clear, iclass 27 cls_cnt 0 2006.217.08:03:40.89#ibcon#cleared, iclass 27 cls_cnt 0 2006.217.08:03:40.89$vc4f8/vblo=2,640.99 2006.217.08:03:40.89#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.217.08:03:40.89#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.217.08:03:40.89#ibcon#ireg 17 cls_cnt 0 2006.217.08:03:40.89#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.217.08:03:40.89#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.217.08:03:40.89#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.217.08:03:40.89#ibcon#enter wrdev, iclass 29, count 0 2006.217.08:03:40.89#ibcon#first serial, iclass 29, count 0 2006.217.08:03:40.89#ibcon#enter sib2, iclass 29, count 0 2006.217.08:03:40.89#ibcon#flushed, iclass 29, count 0 2006.217.08:03:40.89#ibcon#about to write, iclass 29, count 0 2006.217.08:03:40.89#ibcon#wrote, iclass 29, count 0 2006.217.08:03:40.89#ibcon#about to read 3, iclass 29, count 0 2006.217.08:03:40.91#ibcon#read 3, iclass 29, count 0 2006.217.08:03:40.91#ibcon#about to read 4, iclass 29, count 0 2006.217.08:03:40.91#ibcon#read 4, iclass 29, count 0 2006.217.08:03:40.91#ibcon#about to read 5, iclass 29, count 0 2006.217.08:03:40.91#ibcon#read 5, iclass 29, count 0 2006.217.08:03:40.91#ibcon#about to read 6, iclass 29, count 0 2006.217.08:03:40.91#ibcon#read 6, iclass 29, count 0 2006.217.08:03:40.91#ibcon#end of sib2, iclass 29, count 0 2006.217.08:03:40.91#ibcon#*mode == 0, iclass 29, count 0 2006.217.08:03:40.91#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.217.08:03:40.91#ibcon#[28=FRQ=02,640.99\r\n] 2006.217.08:03:40.91#ibcon#*before write, iclass 29, count 0 2006.217.08:03:40.91#ibcon#enter sib2, iclass 29, count 0 2006.217.08:03:40.91#ibcon#flushed, iclass 29, count 0 2006.217.08:03:40.91#ibcon#about to write, iclass 29, count 0 2006.217.08:03:40.91#ibcon#wrote, iclass 29, count 0 2006.217.08:03:40.91#ibcon#about to read 3, iclass 29, count 0 2006.217.08:03:40.95#ibcon#read 3, iclass 29, count 0 2006.217.08:03:40.95#ibcon#about to read 4, iclass 29, count 0 2006.217.08:03:40.95#ibcon#read 4, iclass 29, count 0 2006.217.08:03:40.95#ibcon#about to read 5, iclass 29, count 0 2006.217.08:03:40.95#ibcon#read 5, iclass 29, count 0 2006.217.08:03:40.95#ibcon#about to read 6, iclass 29, count 0 2006.217.08:03:40.95#ibcon#read 6, iclass 29, count 0 2006.217.08:03:40.95#ibcon#end of sib2, iclass 29, count 0 2006.217.08:03:40.95#ibcon#*after write, iclass 29, count 0 2006.217.08:03:40.95#ibcon#*before return 0, iclass 29, count 0 2006.217.08:03:40.95#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.217.08:03:40.95#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.217.08:03:40.95#ibcon#about to clear, iclass 29 cls_cnt 0 2006.217.08:03:40.95#ibcon#cleared, iclass 29 cls_cnt 0 2006.217.08:03:40.95$vc4f8/vb=2,4 2006.217.08:03:40.95#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.217.08:03:40.95#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.217.08:03:40.95#ibcon#ireg 11 cls_cnt 2 2006.217.08:03:40.95#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.217.08:03:41.01#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.217.08:03:41.01#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.217.08:03:41.01#ibcon#enter wrdev, iclass 31, count 2 2006.217.08:03:41.01#ibcon#first serial, iclass 31, count 2 2006.217.08:03:41.01#ibcon#enter sib2, iclass 31, count 2 2006.217.08:03:41.01#ibcon#flushed, iclass 31, count 2 2006.217.08:03:41.01#ibcon#about to write, iclass 31, count 2 2006.217.08:03:41.01#ibcon#wrote, iclass 31, count 2 2006.217.08:03:41.01#ibcon#about to read 3, iclass 31, count 2 2006.217.08:03:41.03#ibcon#read 3, iclass 31, count 2 2006.217.08:03:41.03#ibcon#about to read 4, iclass 31, count 2 2006.217.08:03:41.03#ibcon#read 4, iclass 31, count 2 2006.217.08:03:41.03#ibcon#about to read 5, iclass 31, count 2 2006.217.08:03:41.03#ibcon#read 5, iclass 31, count 2 2006.217.08:03:41.03#ibcon#about to read 6, iclass 31, count 2 2006.217.08:03:41.03#ibcon#read 6, iclass 31, count 2 2006.217.08:03:41.03#ibcon#end of sib2, iclass 31, count 2 2006.217.08:03:41.03#ibcon#*mode == 0, iclass 31, count 2 2006.217.08:03:41.03#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.217.08:03:41.03#ibcon#[27=AT02-04\r\n] 2006.217.08:03:41.03#ibcon#*before write, iclass 31, count 2 2006.217.08:03:41.03#ibcon#enter sib2, iclass 31, count 2 2006.217.08:03:41.03#ibcon#flushed, iclass 31, count 2 2006.217.08:03:41.03#ibcon#about to write, iclass 31, count 2 2006.217.08:03:41.03#ibcon#wrote, iclass 31, count 2 2006.217.08:03:41.03#ibcon#about to read 3, iclass 31, count 2 2006.217.08:03:41.06#ibcon#read 3, iclass 31, count 2 2006.217.08:03:41.06#ibcon#about to read 4, iclass 31, count 2 2006.217.08:03:41.06#ibcon#read 4, iclass 31, count 2 2006.217.08:03:41.06#ibcon#about to read 5, iclass 31, count 2 2006.217.08:03:41.06#ibcon#read 5, iclass 31, count 2 2006.217.08:03:41.06#ibcon#about to read 6, iclass 31, count 2 2006.217.08:03:41.06#ibcon#read 6, iclass 31, count 2 2006.217.08:03:41.06#ibcon#end of sib2, iclass 31, count 2 2006.217.08:03:41.06#ibcon#*after write, iclass 31, count 2 2006.217.08:03:41.06#ibcon#*before return 0, iclass 31, count 2 2006.217.08:03:41.06#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.217.08:03:41.06#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.217.08:03:41.06#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.217.08:03:41.06#ibcon#ireg 7 cls_cnt 0 2006.217.08:03:41.06#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.217.08:03:41.18#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.217.08:03:41.18#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.217.08:03:41.18#ibcon#enter wrdev, iclass 31, count 0 2006.217.08:03:41.18#ibcon#first serial, iclass 31, count 0 2006.217.08:03:41.18#ibcon#enter sib2, iclass 31, count 0 2006.217.08:03:41.18#ibcon#flushed, iclass 31, count 0 2006.217.08:03:41.18#ibcon#about to write, iclass 31, count 0 2006.217.08:03:41.18#ibcon#wrote, iclass 31, count 0 2006.217.08:03:41.18#ibcon#about to read 3, iclass 31, count 0 2006.217.08:03:41.20#ibcon#read 3, iclass 31, count 0 2006.217.08:03:41.20#ibcon#about to read 4, iclass 31, count 0 2006.217.08:03:41.20#ibcon#read 4, iclass 31, count 0 2006.217.08:03:41.20#ibcon#about to read 5, iclass 31, count 0 2006.217.08:03:41.20#ibcon#read 5, iclass 31, count 0 2006.217.08:03:41.20#ibcon#about to read 6, iclass 31, count 0 2006.217.08:03:41.20#ibcon#read 6, iclass 31, count 0 2006.217.08:03:41.20#ibcon#end of sib2, iclass 31, count 0 2006.217.08:03:41.20#ibcon#*mode == 0, iclass 31, count 0 2006.217.08:03:41.20#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.217.08:03:41.20#ibcon#[27=USB\r\n] 2006.217.08:03:41.20#ibcon#*before write, iclass 31, count 0 2006.217.08:03:41.20#ibcon#enter sib2, iclass 31, count 0 2006.217.08:03:41.20#ibcon#flushed, iclass 31, count 0 2006.217.08:03:41.20#ibcon#about to write, iclass 31, count 0 2006.217.08:03:41.20#ibcon#wrote, iclass 31, count 0 2006.217.08:03:41.20#ibcon#about to read 3, iclass 31, count 0 2006.217.08:03:41.23#ibcon#read 3, iclass 31, count 0 2006.217.08:03:41.23#ibcon#about to read 4, iclass 31, count 0 2006.217.08:03:41.23#ibcon#read 4, iclass 31, count 0 2006.217.08:03:41.23#ibcon#about to read 5, iclass 31, count 0 2006.217.08:03:41.23#ibcon#read 5, iclass 31, count 0 2006.217.08:03:41.23#ibcon#about to read 6, iclass 31, count 0 2006.217.08:03:41.23#ibcon#read 6, iclass 31, count 0 2006.217.08:03:41.23#ibcon#end of sib2, iclass 31, count 0 2006.217.08:03:41.23#ibcon#*after write, iclass 31, count 0 2006.217.08:03:41.23#ibcon#*before return 0, iclass 31, count 0 2006.217.08:03:41.23#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.217.08:03:41.23#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.217.08:03:41.23#ibcon#about to clear, iclass 31 cls_cnt 0 2006.217.08:03:41.23#ibcon#cleared, iclass 31 cls_cnt 0 2006.217.08:03:41.23$vc4f8/vblo=3,656.99 2006.217.08:03:41.23#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.217.08:03:41.23#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.217.08:03:41.23#ibcon#ireg 17 cls_cnt 0 2006.217.08:03:41.23#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.217.08:03:41.23#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.217.08:03:41.23#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.217.08:03:41.23#ibcon#enter wrdev, iclass 33, count 0 2006.217.08:03:41.23#ibcon#first serial, iclass 33, count 0 2006.217.08:03:41.23#ibcon#enter sib2, iclass 33, count 0 2006.217.08:03:41.23#ibcon#flushed, iclass 33, count 0 2006.217.08:03:41.23#ibcon#about to write, iclass 33, count 0 2006.217.08:03:41.23#ibcon#wrote, iclass 33, count 0 2006.217.08:03:41.23#ibcon#about to read 3, iclass 33, count 0 2006.217.08:03:41.25#ibcon#read 3, iclass 33, count 0 2006.217.08:03:41.25#ibcon#about to read 4, iclass 33, count 0 2006.217.08:03:41.25#ibcon#read 4, iclass 33, count 0 2006.217.08:03:41.25#ibcon#about to read 5, iclass 33, count 0 2006.217.08:03:41.25#ibcon#read 5, iclass 33, count 0 2006.217.08:03:41.25#ibcon#about to read 6, iclass 33, count 0 2006.217.08:03:41.25#ibcon#read 6, iclass 33, count 0 2006.217.08:03:41.25#ibcon#end of sib2, iclass 33, count 0 2006.217.08:03:41.25#ibcon#*mode == 0, iclass 33, count 0 2006.217.08:03:41.25#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.217.08:03:41.25#ibcon#[28=FRQ=03,656.99\r\n] 2006.217.08:03:41.25#ibcon#*before write, iclass 33, count 0 2006.217.08:03:41.25#ibcon#enter sib2, iclass 33, count 0 2006.217.08:03:41.25#ibcon#flushed, iclass 33, count 0 2006.217.08:03:41.25#ibcon#about to write, iclass 33, count 0 2006.217.08:03:41.25#ibcon#wrote, iclass 33, count 0 2006.217.08:03:41.25#ibcon#about to read 3, iclass 33, count 0 2006.217.08:03:41.29#ibcon#read 3, iclass 33, count 0 2006.217.08:03:41.29#ibcon#about to read 4, iclass 33, count 0 2006.217.08:03:41.29#ibcon#read 4, iclass 33, count 0 2006.217.08:03:41.29#ibcon#about to read 5, iclass 33, count 0 2006.217.08:03:41.29#ibcon#read 5, iclass 33, count 0 2006.217.08:03:41.29#ibcon#about to read 6, iclass 33, count 0 2006.217.08:03:41.29#ibcon#read 6, iclass 33, count 0 2006.217.08:03:41.29#ibcon#end of sib2, iclass 33, count 0 2006.217.08:03:41.29#ibcon#*after write, iclass 33, count 0 2006.217.08:03:41.29#ibcon#*before return 0, iclass 33, count 0 2006.217.08:03:41.29#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.217.08:03:41.29#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.217.08:03:41.29#ibcon#about to clear, iclass 33 cls_cnt 0 2006.217.08:03:41.29#ibcon#cleared, iclass 33 cls_cnt 0 2006.217.08:03:41.29$vc4f8/vb=3,4 2006.217.08:03:41.29#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.217.08:03:41.29#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.217.08:03:41.29#ibcon#ireg 11 cls_cnt 2 2006.217.08:03:41.29#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.217.08:03:41.35#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.217.08:03:41.35#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.217.08:03:41.35#ibcon#enter wrdev, iclass 35, count 2 2006.217.08:03:41.35#ibcon#first serial, iclass 35, count 2 2006.217.08:03:41.35#ibcon#enter sib2, iclass 35, count 2 2006.217.08:03:41.35#ibcon#flushed, iclass 35, count 2 2006.217.08:03:41.35#ibcon#about to write, iclass 35, count 2 2006.217.08:03:41.35#ibcon#wrote, iclass 35, count 2 2006.217.08:03:41.35#ibcon#about to read 3, iclass 35, count 2 2006.217.08:03:41.37#ibcon#read 3, iclass 35, count 2 2006.217.08:03:41.37#ibcon#about to read 4, iclass 35, count 2 2006.217.08:03:41.37#ibcon#read 4, iclass 35, count 2 2006.217.08:03:41.37#ibcon#about to read 5, iclass 35, count 2 2006.217.08:03:41.37#ibcon#read 5, iclass 35, count 2 2006.217.08:03:41.37#ibcon#about to read 6, iclass 35, count 2 2006.217.08:03:41.37#ibcon#read 6, iclass 35, count 2 2006.217.08:03:41.37#ibcon#end of sib2, iclass 35, count 2 2006.217.08:03:41.37#ibcon#*mode == 0, iclass 35, count 2 2006.217.08:03:41.37#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.217.08:03:41.37#ibcon#[27=AT03-04\r\n] 2006.217.08:03:41.37#ibcon#*before write, iclass 35, count 2 2006.217.08:03:41.37#ibcon#enter sib2, iclass 35, count 2 2006.217.08:03:41.37#ibcon#flushed, iclass 35, count 2 2006.217.08:03:41.37#ibcon#about to write, iclass 35, count 2 2006.217.08:03:41.37#ibcon#wrote, iclass 35, count 2 2006.217.08:03:41.37#ibcon#about to read 3, iclass 35, count 2 2006.217.08:03:41.40#ibcon#read 3, iclass 35, count 2 2006.217.08:03:41.40#ibcon#about to read 4, iclass 35, count 2 2006.217.08:03:41.40#ibcon#read 4, iclass 35, count 2 2006.217.08:03:41.40#ibcon#about to read 5, iclass 35, count 2 2006.217.08:03:41.40#ibcon#read 5, iclass 35, count 2 2006.217.08:03:41.40#ibcon#about to read 6, iclass 35, count 2 2006.217.08:03:41.40#ibcon#read 6, iclass 35, count 2 2006.217.08:03:41.40#ibcon#end of sib2, iclass 35, count 2 2006.217.08:03:41.40#ibcon#*after write, iclass 35, count 2 2006.217.08:03:41.40#ibcon#*before return 0, iclass 35, count 2 2006.217.08:03:41.40#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.217.08:03:41.40#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.217.08:03:41.40#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.217.08:03:41.40#ibcon#ireg 7 cls_cnt 0 2006.217.08:03:41.40#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.217.08:03:41.52#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.217.08:03:41.52#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.217.08:03:41.52#ibcon#enter wrdev, iclass 35, count 0 2006.217.08:03:41.52#ibcon#first serial, iclass 35, count 0 2006.217.08:03:41.52#ibcon#enter sib2, iclass 35, count 0 2006.217.08:03:41.52#ibcon#flushed, iclass 35, count 0 2006.217.08:03:41.52#ibcon#about to write, iclass 35, count 0 2006.217.08:03:41.52#ibcon#wrote, iclass 35, count 0 2006.217.08:03:41.52#ibcon#about to read 3, iclass 35, count 0 2006.217.08:03:41.54#ibcon#read 3, iclass 35, count 0 2006.217.08:03:41.54#ibcon#about to read 4, iclass 35, count 0 2006.217.08:03:41.54#ibcon#read 4, iclass 35, count 0 2006.217.08:03:41.54#ibcon#about to read 5, iclass 35, count 0 2006.217.08:03:41.54#ibcon#read 5, iclass 35, count 0 2006.217.08:03:41.54#ibcon#about to read 6, iclass 35, count 0 2006.217.08:03:41.54#ibcon#read 6, iclass 35, count 0 2006.217.08:03:41.54#ibcon#end of sib2, iclass 35, count 0 2006.217.08:03:41.54#ibcon#*mode == 0, iclass 35, count 0 2006.217.08:03:41.54#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.217.08:03:41.54#ibcon#[27=USB\r\n] 2006.217.08:03:41.54#ibcon#*before write, iclass 35, count 0 2006.217.08:03:41.54#ibcon#enter sib2, iclass 35, count 0 2006.217.08:03:41.54#ibcon#flushed, iclass 35, count 0 2006.217.08:03:41.54#ibcon#about to write, iclass 35, count 0 2006.217.08:03:41.54#ibcon#wrote, iclass 35, count 0 2006.217.08:03:41.54#ibcon#about to read 3, iclass 35, count 0 2006.217.08:03:41.57#ibcon#read 3, iclass 35, count 0 2006.217.08:03:41.57#ibcon#about to read 4, iclass 35, count 0 2006.217.08:03:41.57#ibcon#read 4, iclass 35, count 0 2006.217.08:03:41.57#ibcon#about to read 5, iclass 35, count 0 2006.217.08:03:41.57#ibcon#read 5, iclass 35, count 0 2006.217.08:03:41.57#ibcon#about to read 6, iclass 35, count 0 2006.217.08:03:41.57#ibcon#read 6, iclass 35, count 0 2006.217.08:03:41.57#ibcon#end of sib2, iclass 35, count 0 2006.217.08:03:41.57#ibcon#*after write, iclass 35, count 0 2006.217.08:03:41.57#ibcon#*before return 0, iclass 35, count 0 2006.217.08:03:41.57#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.217.08:03:41.57#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.217.08:03:41.57#ibcon#about to clear, iclass 35 cls_cnt 0 2006.217.08:03:41.57#ibcon#cleared, iclass 35 cls_cnt 0 2006.217.08:03:41.57$vc4f8/vblo=4,712.99 2006.217.08:03:41.57#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.217.08:03:41.57#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.217.08:03:41.57#ibcon#ireg 17 cls_cnt 0 2006.217.08:03:41.57#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.217.08:03:41.57#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.217.08:03:41.57#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.217.08:03:41.57#ibcon#enter wrdev, iclass 37, count 0 2006.217.08:03:41.57#ibcon#first serial, iclass 37, count 0 2006.217.08:03:41.57#ibcon#enter sib2, iclass 37, count 0 2006.217.08:03:41.57#ibcon#flushed, iclass 37, count 0 2006.217.08:03:41.57#ibcon#about to write, iclass 37, count 0 2006.217.08:03:41.57#ibcon#wrote, iclass 37, count 0 2006.217.08:03:41.57#ibcon#about to read 3, iclass 37, count 0 2006.217.08:03:41.59#ibcon#read 3, iclass 37, count 0 2006.217.08:03:41.59#ibcon#about to read 4, iclass 37, count 0 2006.217.08:03:41.59#ibcon#read 4, iclass 37, count 0 2006.217.08:03:41.59#ibcon#about to read 5, iclass 37, count 0 2006.217.08:03:41.59#ibcon#read 5, iclass 37, count 0 2006.217.08:03:41.59#ibcon#about to read 6, iclass 37, count 0 2006.217.08:03:41.59#ibcon#read 6, iclass 37, count 0 2006.217.08:03:41.59#ibcon#end of sib2, iclass 37, count 0 2006.217.08:03:41.59#ibcon#*mode == 0, iclass 37, count 0 2006.217.08:03:41.59#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.217.08:03:41.59#ibcon#[28=FRQ=04,712.99\r\n] 2006.217.08:03:41.59#ibcon#*before write, iclass 37, count 0 2006.217.08:03:41.59#ibcon#enter sib2, iclass 37, count 0 2006.217.08:03:41.59#ibcon#flushed, iclass 37, count 0 2006.217.08:03:41.59#ibcon#about to write, iclass 37, count 0 2006.217.08:03:41.59#ibcon#wrote, iclass 37, count 0 2006.217.08:03:41.59#ibcon#about to read 3, iclass 37, count 0 2006.217.08:03:41.63#ibcon#read 3, iclass 37, count 0 2006.217.08:03:41.63#ibcon#about to read 4, iclass 37, count 0 2006.217.08:03:41.63#ibcon#read 4, iclass 37, count 0 2006.217.08:03:41.63#ibcon#about to read 5, iclass 37, count 0 2006.217.08:03:41.63#ibcon#read 5, iclass 37, count 0 2006.217.08:03:41.63#ibcon#about to read 6, iclass 37, count 0 2006.217.08:03:41.63#ibcon#read 6, iclass 37, count 0 2006.217.08:03:41.63#ibcon#end of sib2, iclass 37, count 0 2006.217.08:03:41.63#ibcon#*after write, iclass 37, count 0 2006.217.08:03:41.63#ibcon#*before return 0, iclass 37, count 0 2006.217.08:03:41.63#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.217.08:03:41.63#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.217.08:03:41.63#ibcon#about to clear, iclass 37 cls_cnt 0 2006.217.08:03:41.63#ibcon#cleared, iclass 37 cls_cnt 0 2006.217.08:03:41.63$vc4f8/vb=4,4 2006.217.08:03:41.63#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.217.08:03:41.63#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.217.08:03:41.63#ibcon#ireg 11 cls_cnt 2 2006.217.08:03:41.63#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.217.08:03:41.69#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.217.08:03:41.69#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.217.08:03:41.69#ibcon#enter wrdev, iclass 39, count 2 2006.217.08:03:41.69#ibcon#first serial, iclass 39, count 2 2006.217.08:03:41.69#ibcon#enter sib2, iclass 39, count 2 2006.217.08:03:41.69#ibcon#flushed, iclass 39, count 2 2006.217.08:03:41.69#ibcon#about to write, iclass 39, count 2 2006.217.08:03:41.69#ibcon#wrote, iclass 39, count 2 2006.217.08:03:41.69#ibcon#about to read 3, iclass 39, count 2 2006.217.08:03:41.71#ibcon#read 3, iclass 39, count 2 2006.217.08:03:41.71#ibcon#about to read 4, iclass 39, count 2 2006.217.08:03:41.71#ibcon#read 4, iclass 39, count 2 2006.217.08:03:41.71#ibcon#about to read 5, iclass 39, count 2 2006.217.08:03:41.71#ibcon#read 5, iclass 39, count 2 2006.217.08:03:41.71#ibcon#about to read 6, iclass 39, count 2 2006.217.08:03:41.71#ibcon#read 6, iclass 39, count 2 2006.217.08:03:41.71#ibcon#end of sib2, iclass 39, count 2 2006.217.08:03:41.71#ibcon#*mode == 0, iclass 39, count 2 2006.217.08:03:41.71#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.217.08:03:41.71#ibcon#[27=AT04-04\r\n] 2006.217.08:03:41.71#ibcon#*before write, iclass 39, count 2 2006.217.08:03:41.71#ibcon#enter sib2, iclass 39, count 2 2006.217.08:03:41.71#ibcon#flushed, iclass 39, count 2 2006.217.08:03:41.71#ibcon#about to write, iclass 39, count 2 2006.217.08:03:41.71#ibcon#wrote, iclass 39, count 2 2006.217.08:03:41.71#ibcon#about to read 3, iclass 39, count 2 2006.217.08:03:41.74#ibcon#read 3, iclass 39, count 2 2006.217.08:03:41.74#ibcon#about to read 4, iclass 39, count 2 2006.217.08:03:41.74#ibcon#read 4, iclass 39, count 2 2006.217.08:03:41.74#ibcon#about to read 5, iclass 39, count 2 2006.217.08:03:41.74#ibcon#read 5, iclass 39, count 2 2006.217.08:03:41.74#ibcon#about to read 6, iclass 39, count 2 2006.217.08:03:41.74#ibcon#read 6, iclass 39, count 2 2006.217.08:03:41.74#ibcon#end of sib2, iclass 39, count 2 2006.217.08:03:41.74#ibcon#*after write, iclass 39, count 2 2006.217.08:03:41.74#ibcon#*before return 0, iclass 39, count 2 2006.217.08:03:41.74#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.217.08:03:41.74#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.217.08:03:41.74#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.217.08:03:41.74#ibcon#ireg 7 cls_cnt 0 2006.217.08:03:41.74#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.217.08:03:41.86#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.217.08:03:41.86#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.217.08:03:41.86#ibcon#enter wrdev, iclass 39, count 0 2006.217.08:03:41.86#ibcon#first serial, iclass 39, count 0 2006.217.08:03:41.86#ibcon#enter sib2, iclass 39, count 0 2006.217.08:03:41.86#ibcon#flushed, iclass 39, count 0 2006.217.08:03:41.86#ibcon#about to write, iclass 39, count 0 2006.217.08:03:41.86#ibcon#wrote, iclass 39, count 0 2006.217.08:03:41.86#ibcon#about to read 3, iclass 39, count 0 2006.217.08:03:41.88#ibcon#read 3, iclass 39, count 0 2006.217.08:03:41.88#ibcon#about to read 4, iclass 39, count 0 2006.217.08:03:41.88#ibcon#read 4, iclass 39, count 0 2006.217.08:03:41.88#ibcon#about to read 5, iclass 39, count 0 2006.217.08:03:41.88#ibcon#read 5, iclass 39, count 0 2006.217.08:03:41.88#ibcon#about to read 6, iclass 39, count 0 2006.217.08:03:41.88#ibcon#read 6, iclass 39, count 0 2006.217.08:03:41.88#ibcon#end of sib2, iclass 39, count 0 2006.217.08:03:41.88#ibcon#*mode == 0, iclass 39, count 0 2006.217.08:03:41.88#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.217.08:03:41.88#ibcon#[27=USB\r\n] 2006.217.08:03:41.88#ibcon#*before write, iclass 39, count 0 2006.217.08:03:41.88#ibcon#enter sib2, iclass 39, count 0 2006.217.08:03:41.88#ibcon#flushed, iclass 39, count 0 2006.217.08:03:41.88#ibcon#about to write, iclass 39, count 0 2006.217.08:03:41.88#ibcon#wrote, iclass 39, count 0 2006.217.08:03:41.88#ibcon#about to read 3, iclass 39, count 0 2006.217.08:03:41.91#ibcon#read 3, iclass 39, count 0 2006.217.08:03:41.91#ibcon#about to read 4, iclass 39, count 0 2006.217.08:03:41.91#ibcon#read 4, iclass 39, count 0 2006.217.08:03:41.91#ibcon#about to read 5, iclass 39, count 0 2006.217.08:03:41.91#ibcon#read 5, iclass 39, count 0 2006.217.08:03:41.91#ibcon#about to read 6, iclass 39, count 0 2006.217.08:03:41.91#ibcon#read 6, iclass 39, count 0 2006.217.08:03:41.91#ibcon#end of sib2, iclass 39, count 0 2006.217.08:03:41.91#ibcon#*after write, iclass 39, count 0 2006.217.08:03:41.91#ibcon#*before return 0, iclass 39, count 0 2006.217.08:03:41.91#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.217.08:03:41.91#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.217.08:03:41.91#ibcon#about to clear, iclass 39 cls_cnt 0 2006.217.08:03:41.91#ibcon#cleared, iclass 39 cls_cnt 0 2006.217.08:03:41.91$vc4f8/vblo=5,744.99 2006.217.08:03:41.91#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.217.08:03:41.91#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.217.08:03:41.91#ibcon#ireg 17 cls_cnt 0 2006.217.08:03:41.91#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.217.08:03:41.91#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.217.08:03:41.91#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.217.08:03:41.91#ibcon#enter wrdev, iclass 3, count 0 2006.217.08:03:41.91#ibcon#first serial, iclass 3, count 0 2006.217.08:03:41.91#ibcon#enter sib2, iclass 3, count 0 2006.217.08:03:41.91#ibcon#flushed, iclass 3, count 0 2006.217.08:03:41.91#ibcon#about to write, iclass 3, count 0 2006.217.08:03:41.91#ibcon#wrote, iclass 3, count 0 2006.217.08:03:41.91#ibcon#about to read 3, iclass 3, count 0 2006.217.08:03:41.93#ibcon#read 3, iclass 3, count 0 2006.217.08:03:41.93#ibcon#about to read 4, iclass 3, count 0 2006.217.08:03:41.93#ibcon#read 4, iclass 3, count 0 2006.217.08:03:41.93#ibcon#about to read 5, iclass 3, count 0 2006.217.08:03:41.93#ibcon#read 5, iclass 3, count 0 2006.217.08:03:41.93#ibcon#about to read 6, iclass 3, count 0 2006.217.08:03:41.93#ibcon#read 6, iclass 3, count 0 2006.217.08:03:41.93#ibcon#end of sib2, iclass 3, count 0 2006.217.08:03:41.93#ibcon#*mode == 0, iclass 3, count 0 2006.217.08:03:41.93#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.217.08:03:41.93#ibcon#[28=FRQ=05,744.99\r\n] 2006.217.08:03:41.93#ibcon#*before write, iclass 3, count 0 2006.217.08:03:41.93#ibcon#enter sib2, iclass 3, count 0 2006.217.08:03:41.93#ibcon#flushed, iclass 3, count 0 2006.217.08:03:41.93#ibcon#about to write, iclass 3, count 0 2006.217.08:03:41.93#ibcon#wrote, iclass 3, count 0 2006.217.08:03:41.93#ibcon#about to read 3, iclass 3, count 0 2006.217.08:03:41.97#ibcon#read 3, iclass 3, count 0 2006.217.08:03:41.97#ibcon#about to read 4, iclass 3, count 0 2006.217.08:03:41.97#ibcon#read 4, iclass 3, count 0 2006.217.08:03:41.97#ibcon#about to read 5, iclass 3, count 0 2006.217.08:03:41.97#ibcon#read 5, iclass 3, count 0 2006.217.08:03:41.97#ibcon#about to read 6, iclass 3, count 0 2006.217.08:03:41.97#ibcon#read 6, iclass 3, count 0 2006.217.08:03:41.97#ibcon#end of sib2, iclass 3, count 0 2006.217.08:03:41.97#ibcon#*after write, iclass 3, count 0 2006.217.08:03:41.97#ibcon#*before return 0, iclass 3, count 0 2006.217.08:03:41.97#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.217.08:03:41.97#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.217.08:03:41.97#ibcon#about to clear, iclass 3 cls_cnt 0 2006.217.08:03:41.97#ibcon#cleared, iclass 3 cls_cnt 0 2006.217.08:03:41.97$vc4f8/vb=5,4 2006.217.08:03:41.97#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.217.08:03:41.97#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.217.08:03:41.97#ibcon#ireg 11 cls_cnt 2 2006.217.08:03:41.97#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.217.08:03:42.03#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.217.08:03:42.03#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.217.08:03:42.03#ibcon#enter wrdev, iclass 5, count 2 2006.217.08:03:42.03#ibcon#first serial, iclass 5, count 2 2006.217.08:03:42.03#ibcon#enter sib2, iclass 5, count 2 2006.217.08:03:42.03#ibcon#flushed, iclass 5, count 2 2006.217.08:03:42.03#ibcon#about to write, iclass 5, count 2 2006.217.08:03:42.03#ibcon#wrote, iclass 5, count 2 2006.217.08:03:42.03#ibcon#about to read 3, iclass 5, count 2 2006.217.08:03:42.05#ibcon#read 3, iclass 5, count 2 2006.217.08:03:42.05#ibcon#about to read 4, iclass 5, count 2 2006.217.08:03:42.05#ibcon#read 4, iclass 5, count 2 2006.217.08:03:42.05#ibcon#about to read 5, iclass 5, count 2 2006.217.08:03:42.05#ibcon#read 5, iclass 5, count 2 2006.217.08:03:42.05#ibcon#about to read 6, iclass 5, count 2 2006.217.08:03:42.05#ibcon#read 6, iclass 5, count 2 2006.217.08:03:42.05#ibcon#end of sib2, iclass 5, count 2 2006.217.08:03:42.05#ibcon#*mode == 0, iclass 5, count 2 2006.217.08:03:42.05#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.217.08:03:42.05#ibcon#[27=AT05-04\r\n] 2006.217.08:03:42.05#ibcon#*before write, iclass 5, count 2 2006.217.08:03:42.05#ibcon#enter sib2, iclass 5, count 2 2006.217.08:03:42.05#ibcon#flushed, iclass 5, count 2 2006.217.08:03:42.05#ibcon#about to write, iclass 5, count 2 2006.217.08:03:42.05#ibcon#wrote, iclass 5, count 2 2006.217.08:03:42.05#ibcon#about to read 3, iclass 5, count 2 2006.217.08:03:42.08#ibcon#read 3, iclass 5, count 2 2006.217.08:03:42.08#ibcon#about to read 4, iclass 5, count 2 2006.217.08:03:42.08#ibcon#read 4, iclass 5, count 2 2006.217.08:03:42.08#ibcon#about to read 5, iclass 5, count 2 2006.217.08:03:42.08#ibcon#read 5, iclass 5, count 2 2006.217.08:03:42.08#ibcon#about to read 6, iclass 5, count 2 2006.217.08:03:42.08#ibcon#read 6, iclass 5, count 2 2006.217.08:03:42.08#ibcon#end of sib2, iclass 5, count 2 2006.217.08:03:42.08#ibcon#*after write, iclass 5, count 2 2006.217.08:03:42.08#ibcon#*before return 0, iclass 5, count 2 2006.217.08:03:42.08#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.217.08:03:42.08#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.217.08:03:42.08#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.217.08:03:42.08#ibcon#ireg 7 cls_cnt 0 2006.217.08:03:42.08#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.217.08:03:42.20#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.217.08:03:42.20#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.217.08:03:42.20#ibcon#enter wrdev, iclass 5, count 0 2006.217.08:03:42.20#ibcon#first serial, iclass 5, count 0 2006.217.08:03:42.20#ibcon#enter sib2, iclass 5, count 0 2006.217.08:03:42.20#ibcon#flushed, iclass 5, count 0 2006.217.08:03:42.20#ibcon#about to write, iclass 5, count 0 2006.217.08:03:42.20#ibcon#wrote, iclass 5, count 0 2006.217.08:03:42.20#ibcon#about to read 3, iclass 5, count 0 2006.217.08:03:42.22#ibcon#read 3, iclass 5, count 0 2006.217.08:03:42.22#ibcon#about to read 4, iclass 5, count 0 2006.217.08:03:42.22#ibcon#read 4, iclass 5, count 0 2006.217.08:03:42.22#ibcon#about to read 5, iclass 5, count 0 2006.217.08:03:42.22#ibcon#read 5, iclass 5, count 0 2006.217.08:03:42.22#ibcon#about to read 6, iclass 5, count 0 2006.217.08:03:42.22#ibcon#read 6, iclass 5, count 0 2006.217.08:03:42.22#ibcon#end of sib2, iclass 5, count 0 2006.217.08:03:42.22#ibcon#*mode == 0, iclass 5, count 0 2006.217.08:03:42.22#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.217.08:03:42.22#ibcon#[27=USB\r\n] 2006.217.08:03:42.22#ibcon#*before write, iclass 5, count 0 2006.217.08:03:42.22#ibcon#enter sib2, iclass 5, count 0 2006.217.08:03:42.22#ibcon#flushed, iclass 5, count 0 2006.217.08:03:42.22#ibcon#about to write, iclass 5, count 0 2006.217.08:03:42.22#ibcon#wrote, iclass 5, count 0 2006.217.08:03:42.22#ibcon#about to read 3, iclass 5, count 0 2006.217.08:03:42.25#ibcon#read 3, iclass 5, count 0 2006.217.08:03:42.25#ibcon#about to read 4, iclass 5, count 0 2006.217.08:03:42.25#ibcon#read 4, iclass 5, count 0 2006.217.08:03:42.25#ibcon#about to read 5, iclass 5, count 0 2006.217.08:03:42.25#ibcon#read 5, iclass 5, count 0 2006.217.08:03:42.25#ibcon#about to read 6, iclass 5, count 0 2006.217.08:03:42.25#ibcon#read 6, iclass 5, count 0 2006.217.08:03:42.25#ibcon#end of sib2, iclass 5, count 0 2006.217.08:03:42.25#ibcon#*after write, iclass 5, count 0 2006.217.08:03:42.25#ibcon#*before return 0, iclass 5, count 0 2006.217.08:03:42.25#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.217.08:03:42.25#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.217.08:03:42.25#ibcon#about to clear, iclass 5 cls_cnt 0 2006.217.08:03:42.25#ibcon#cleared, iclass 5 cls_cnt 0 2006.217.08:03:42.25$vc4f8/vblo=6,752.99 2006.217.08:03:42.25#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.217.08:03:42.25#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.217.08:03:42.25#ibcon#ireg 17 cls_cnt 0 2006.217.08:03:42.25#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.217.08:03:42.25#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.217.08:03:42.25#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.217.08:03:42.25#ibcon#enter wrdev, iclass 7, count 0 2006.217.08:03:42.25#ibcon#first serial, iclass 7, count 0 2006.217.08:03:42.25#ibcon#enter sib2, iclass 7, count 0 2006.217.08:03:42.25#ibcon#flushed, iclass 7, count 0 2006.217.08:03:42.25#ibcon#about to write, iclass 7, count 0 2006.217.08:03:42.25#ibcon#wrote, iclass 7, count 0 2006.217.08:03:42.25#ibcon#about to read 3, iclass 7, count 0 2006.217.08:03:42.27#ibcon#read 3, iclass 7, count 0 2006.217.08:03:42.27#ibcon#about to read 4, iclass 7, count 0 2006.217.08:03:42.27#ibcon#read 4, iclass 7, count 0 2006.217.08:03:42.27#ibcon#about to read 5, iclass 7, count 0 2006.217.08:03:42.27#ibcon#read 5, iclass 7, count 0 2006.217.08:03:42.27#ibcon#about to read 6, iclass 7, count 0 2006.217.08:03:42.27#ibcon#read 6, iclass 7, count 0 2006.217.08:03:42.27#ibcon#end of sib2, iclass 7, count 0 2006.217.08:03:42.27#ibcon#*mode == 0, iclass 7, count 0 2006.217.08:03:42.27#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.217.08:03:42.27#ibcon#[28=FRQ=06,752.99\r\n] 2006.217.08:03:42.27#ibcon#*before write, iclass 7, count 0 2006.217.08:03:42.27#ibcon#enter sib2, iclass 7, count 0 2006.217.08:03:42.27#ibcon#flushed, iclass 7, count 0 2006.217.08:03:42.27#ibcon#about to write, iclass 7, count 0 2006.217.08:03:42.27#ibcon#wrote, iclass 7, count 0 2006.217.08:03:42.27#ibcon#about to read 3, iclass 7, count 0 2006.217.08:03:42.32#ibcon#read 3, iclass 7, count 0 2006.217.08:03:42.32#ibcon#about to read 4, iclass 7, count 0 2006.217.08:03:42.32#ibcon#read 4, iclass 7, count 0 2006.217.08:03:42.32#ibcon#about to read 5, iclass 7, count 0 2006.217.08:03:42.32#ibcon#read 5, iclass 7, count 0 2006.217.08:03:42.32#ibcon#about to read 6, iclass 7, count 0 2006.217.08:03:42.32#ibcon#read 6, iclass 7, count 0 2006.217.08:03:42.32#ibcon#end of sib2, iclass 7, count 0 2006.217.08:03:42.32#ibcon#*after write, iclass 7, count 0 2006.217.08:03:42.32#ibcon#*before return 0, iclass 7, count 0 2006.217.08:03:42.32#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.217.08:03:42.32#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.217.08:03:42.32#ibcon#about to clear, iclass 7 cls_cnt 0 2006.217.08:03:42.32#ibcon#cleared, iclass 7 cls_cnt 0 2006.217.08:03:42.32$vc4f8/vb=6,4 2006.217.08:03:42.32#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.217.08:03:42.32#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.217.08:03:42.32#ibcon#ireg 11 cls_cnt 2 2006.217.08:03:42.32#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.217.08:03:42.36#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.217.08:03:42.36#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.217.08:03:42.36#ibcon#enter wrdev, iclass 11, count 2 2006.217.08:03:42.36#ibcon#first serial, iclass 11, count 2 2006.217.08:03:42.36#ibcon#enter sib2, iclass 11, count 2 2006.217.08:03:42.36#ibcon#flushed, iclass 11, count 2 2006.217.08:03:42.36#ibcon#about to write, iclass 11, count 2 2006.217.08:03:42.36#ibcon#wrote, iclass 11, count 2 2006.217.08:03:42.36#ibcon#about to read 3, iclass 11, count 2 2006.217.08:03:42.38#ibcon#read 3, iclass 11, count 2 2006.217.08:03:42.38#ibcon#about to read 4, iclass 11, count 2 2006.217.08:03:42.38#ibcon#read 4, iclass 11, count 2 2006.217.08:03:42.38#ibcon#about to read 5, iclass 11, count 2 2006.217.08:03:42.38#ibcon#read 5, iclass 11, count 2 2006.217.08:03:42.38#ibcon#about to read 6, iclass 11, count 2 2006.217.08:03:42.38#ibcon#read 6, iclass 11, count 2 2006.217.08:03:42.38#ibcon#end of sib2, iclass 11, count 2 2006.217.08:03:42.38#ibcon#*mode == 0, iclass 11, count 2 2006.217.08:03:42.38#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.217.08:03:42.38#ibcon#[27=AT06-04\r\n] 2006.217.08:03:42.38#ibcon#*before write, iclass 11, count 2 2006.217.08:03:42.38#ibcon#enter sib2, iclass 11, count 2 2006.217.08:03:42.38#ibcon#flushed, iclass 11, count 2 2006.217.08:03:42.38#ibcon#about to write, iclass 11, count 2 2006.217.08:03:42.38#ibcon#wrote, iclass 11, count 2 2006.217.08:03:42.38#ibcon#about to read 3, iclass 11, count 2 2006.217.08:03:42.41#ibcon#read 3, iclass 11, count 2 2006.217.08:03:42.41#ibcon#about to read 4, iclass 11, count 2 2006.217.08:03:42.41#ibcon#read 4, iclass 11, count 2 2006.217.08:03:42.41#ibcon#about to read 5, iclass 11, count 2 2006.217.08:03:42.41#ibcon#read 5, iclass 11, count 2 2006.217.08:03:42.41#ibcon#about to read 6, iclass 11, count 2 2006.217.08:03:42.41#ibcon#read 6, iclass 11, count 2 2006.217.08:03:42.41#ibcon#end of sib2, iclass 11, count 2 2006.217.08:03:42.41#ibcon#*after write, iclass 11, count 2 2006.217.08:03:42.41#ibcon#*before return 0, iclass 11, count 2 2006.217.08:03:42.41#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.217.08:03:42.41#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.217.08:03:42.41#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.217.08:03:42.41#ibcon#ireg 7 cls_cnt 0 2006.217.08:03:42.41#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.217.08:03:42.53#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.217.08:03:42.53#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.217.08:03:42.53#ibcon#enter wrdev, iclass 11, count 0 2006.217.08:03:42.53#ibcon#first serial, iclass 11, count 0 2006.217.08:03:42.53#ibcon#enter sib2, iclass 11, count 0 2006.217.08:03:42.53#ibcon#flushed, iclass 11, count 0 2006.217.08:03:42.53#ibcon#about to write, iclass 11, count 0 2006.217.08:03:42.53#ibcon#wrote, iclass 11, count 0 2006.217.08:03:42.53#ibcon#about to read 3, iclass 11, count 0 2006.217.08:03:42.55#ibcon#read 3, iclass 11, count 0 2006.217.08:03:42.55#ibcon#about to read 4, iclass 11, count 0 2006.217.08:03:42.55#ibcon#read 4, iclass 11, count 0 2006.217.08:03:42.55#ibcon#about to read 5, iclass 11, count 0 2006.217.08:03:42.55#ibcon#read 5, iclass 11, count 0 2006.217.08:03:42.55#ibcon#about to read 6, iclass 11, count 0 2006.217.08:03:42.55#ibcon#read 6, iclass 11, count 0 2006.217.08:03:42.55#ibcon#end of sib2, iclass 11, count 0 2006.217.08:03:42.55#ibcon#*mode == 0, iclass 11, count 0 2006.217.08:03:42.55#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.217.08:03:42.55#ibcon#[27=USB\r\n] 2006.217.08:03:42.55#ibcon#*before write, iclass 11, count 0 2006.217.08:03:42.55#ibcon#enter sib2, iclass 11, count 0 2006.217.08:03:42.55#ibcon#flushed, iclass 11, count 0 2006.217.08:03:42.55#ibcon#about to write, iclass 11, count 0 2006.217.08:03:42.55#ibcon#wrote, iclass 11, count 0 2006.217.08:03:42.55#ibcon#about to read 3, iclass 11, count 0 2006.217.08:03:42.58#ibcon#read 3, iclass 11, count 0 2006.217.08:03:42.58#ibcon#about to read 4, iclass 11, count 0 2006.217.08:03:42.58#ibcon#read 4, iclass 11, count 0 2006.217.08:03:42.58#ibcon#about to read 5, iclass 11, count 0 2006.217.08:03:42.58#ibcon#read 5, iclass 11, count 0 2006.217.08:03:42.58#ibcon#about to read 6, iclass 11, count 0 2006.217.08:03:42.58#ibcon#read 6, iclass 11, count 0 2006.217.08:03:42.58#ibcon#end of sib2, iclass 11, count 0 2006.217.08:03:42.58#ibcon#*after write, iclass 11, count 0 2006.217.08:03:42.58#ibcon#*before return 0, iclass 11, count 0 2006.217.08:03:42.58#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.217.08:03:42.58#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.217.08:03:42.58#ibcon#about to clear, iclass 11 cls_cnt 0 2006.217.08:03:42.58#ibcon#cleared, iclass 11 cls_cnt 0 2006.217.08:03:42.58$vc4f8/vabw=wide 2006.217.08:03:42.58#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.217.08:03:42.58#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.217.08:03:42.58#ibcon#ireg 8 cls_cnt 0 2006.217.08:03:42.58#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.217.08:03:42.58#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.217.08:03:42.58#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.217.08:03:42.58#ibcon#enter wrdev, iclass 13, count 0 2006.217.08:03:42.58#ibcon#first serial, iclass 13, count 0 2006.217.08:03:42.58#ibcon#enter sib2, iclass 13, count 0 2006.217.08:03:42.58#ibcon#flushed, iclass 13, count 0 2006.217.08:03:42.58#ibcon#about to write, iclass 13, count 0 2006.217.08:03:42.58#ibcon#wrote, iclass 13, count 0 2006.217.08:03:42.58#ibcon#about to read 3, iclass 13, count 0 2006.217.08:03:42.60#ibcon#read 3, iclass 13, count 0 2006.217.08:03:42.60#ibcon#about to read 4, iclass 13, count 0 2006.217.08:03:42.60#ibcon#read 4, iclass 13, count 0 2006.217.08:03:42.60#ibcon#about to read 5, iclass 13, count 0 2006.217.08:03:42.60#ibcon#read 5, iclass 13, count 0 2006.217.08:03:42.60#ibcon#about to read 6, iclass 13, count 0 2006.217.08:03:42.60#ibcon#read 6, iclass 13, count 0 2006.217.08:03:42.60#ibcon#end of sib2, iclass 13, count 0 2006.217.08:03:42.60#ibcon#*mode == 0, iclass 13, count 0 2006.217.08:03:42.60#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.217.08:03:42.60#ibcon#[25=BW32\r\n] 2006.217.08:03:42.60#ibcon#*before write, iclass 13, count 0 2006.217.08:03:42.60#ibcon#enter sib2, iclass 13, count 0 2006.217.08:03:42.60#ibcon#flushed, iclass 13, count 0 2006.217.08:03:42.60#ibcon#about to write, iclass 13, count 0 2006.217.08:03:42.60#ibcon#wrote, iclass 13, count 0 2006.217.08:03:42.60#ibcon#about to read 3, iclass 13, count 0 2006.217.08:03:42.63#ibcon#read 3, iclass 13, count 0 2006.217.08:03:42.63#ibcon#about to read 4, iclass 13, count 0 2006.217.08:03:42.63#ibcon#read 4, iclass 13, count 0 2006.217.08:03:42.63#ibcon#about to read 5, iclass 13, count 0 2006.217.08:03:42.63#ibcon#read 5, iclass 13, count 0 2006.217.08:03:42.63#ibcon#about to read 6, iclass 13, count 0 2006.217.08:03:42.63#ibcon#read 6, iclass 13, count 0 2006.217.08:03:42.63#ibcon#end of sib2, iclass 13, count 0 2006.217.08:03:42.63#ibcon#*after write, iclass 13, count 0 2006.217.08:03:42.63#ibcon#*before return 0, iclass 13, count 0 2006.217.08:03:42.63#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.217.08:03:42.63#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.217.08:03:42.63#ibcon#about to clear, iclass 13 cls_cnt 0 2006.217.08:03:42.63#ibcon#cleared, iclass 13 cls_cnt 0 2006.217.08:03:42.63$vc4f8/vbbw=wide 2006.217.08:03:42.63#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.217.08:03:42.63#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.217.08:03:42.63#ibcon#ireg 8 cls_cnt 0 2006.217.08:03:42.63#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.217.08:03:42.70#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.217.08:03:42.70#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.217.08:03:42.70#ibcon#enter wrdev, iclass 15, count 0 2006.217.08:03:42.70#ibcon#first serial, iclass 15, count 0 2006.217.08:03:42.70#ibcon#enter sib2, iclass 15, count 0 2006.217.08:03:42.70#ibcon#flushed, iclass 15, count 0 2006.217.08:03:42.70#ibcon#about to write, iclass 15, count 0 2006.217.08:03:42.70#ibcon#wrote, iclass 15, count 0 2006.217.08:03:42.70#ibcon#about to read 3, iclass 15, count 0 2006.217.08:03:42.72#ibcon#read 3, iclass 15, count 0 2006.217.08:03:42.72#ibcon#about to read 4, iclass 15, count 0 2006.217.08:03:42.72#ibcon#read 4, iclass 15, count 0 2006.217.08:03:42.72#ibcon#about to read 5, iclass 15, count 0 2006.217.08:03:42.72#ibcon#read 5, iclass 15, count 0 2006.217.08:03:42.72#ibcon#about to read 6, iclass 15, count 0 2006.217.08:03:42.72#ibcon#read 6, iclass 15, count 0 2006.217.08:03:42.72#ibcon#end of sib2, iclass 15, count 0 2006.217.08:03:42.72#ibcon#*mode == 0, iclass 15, count 0 2006.217.08:03:42.72#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.217.08:03:42.72#ibcon#[27=BW32\r\n] 2006.217.08:03:42.72#ibcon#*before write, iclass 15, count 0 2006.217.08:03:42.72#ibcon#enter sib2, iclass 15, count 0 2006.217.08:03:42.72#ibcon#flushed, iclass 15, count 0 2006.217.08:03:42.72#ibcon#about to write, iclass 15, count 0 2006.217.08:03:42.72#ibcon#wrote, iclass 15, count 0 2006.217.08:03:42.72#ibcon#about to read 3, iclass 15, count 0 2006.217.08:03:42.75#ibcon#read 3, iclass 15, count 0 2006.217.08:03:42.75#ibcon#about to read 4, iclass 15, count 0 2006.217.08:03:42.75#ibcon#read 4, iclass 15, count 0 2006.217.08:03:42.75#ibcon#about to read 5, iclass 15, count 0 2006.217.08:03:42.75#ibcon#read 5, iclass 15, count 0 2006.217.08:03:42.75#ibcon#about to read 6, iclass 15, count 0 2006.217.08:03:42.75#ibcon#read 6, iclass 15, count 0 2006.217.08:03:42.75#ibcon#end of sib2, iclass 15, count 0 2006.217.08:03:42.75#ibcon#*after write, iclass 15, count 0 2006.217.08:03:42.75#ibcon#*before return 0, iclass 15, count 0 2006.217.08:03:42.75#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.217.08:03:42.75#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.217.08:03:42.75#ibcon#about to clear, iclass 15 cls_cnt 0 2006.217.08:03:42.75#ibcon#cleared, iclass 15 cls_cnt 0 2006.217.08:03:42.75$4f8m12a/ifd4f 2006.217.08:03:42.75$ifd4f/lo= 2006.217.08:03:42.75$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.217.08:03:42.75$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.217.08:03:42.75$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.217.08:03:42.75$ifd4f/patch= 2006.217.08:03:42.75$ifd4f/patch=lo1,a1,a2,a3,a4 2006.217.08:03:42.75$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.217.08:03:42.75$ifd4f/patch=lo3,a5,a6,a7,a8 2006.217.08:03:42.75$4f8m12a/"form=m,16.000,1:2 2006.217.08:03:42.75$4f8m12a/"tpicd 2006.217.08:03:42.75$4f8m12a/echo=off 2006.217.08:03:42.75$4f8m12a/xlog=off 2006.217.08:03:42.75:!2006.217.08:04:50 2006.217.08:04:23.14#trakl#Source acquired 2006.217.08:04:25.14#flagr#flagr/antenna,acquired 2006.217.08:04:50.00:preob 2006.217.08:04:50.14/onsource/TRACKING 2006.217.08:04:50.14:!2006.217.08:05:00 2006.217.08:05:00.00:data_valid=on 2006.217.08:05:00.00:midob 2006.217.08:05:01.14/onsource/TRACKING 2006.217.08:05:01.14/wx/30.82,1008.6,63 2006.217.08:05:01.29/cable/+6.3861E-03 2006.217.08:05:02.38/va/01,05,usb,yes,32,33 2006.217.08:05:02.38/va/02,04,usb,yes,29,31 2006.217.08:05:02.38/va/03,04,usb,yes,28,28 2006.217.08:05:02.38/va/04,04,usb,yes,31,33 2006.217.08:05:02.38/va/05,07,usb,yes,33,34 2006.217.08:05:02.38/va/06,06,usb,yes,32,31 2006.217.08:05:02.38/va/07,06,usb,yes,32,32 2006.217.08:05:02.38/va/08,07,usb,yes,30,30 2006.217.08:05:02.61/valo/01,532.99,yes,locked 2006.217.08:05:02.61/valo/02,572.99,yes,locked 2006.217.08:05:02.61/valo/03,672.99,yes,locked 2006.217.08:05:02.61/valo/04,832.99,yes,locked 2006.217.08:05:02.61/valo/05,652.99,yes,locked 2006.217.08:05:02.61/valo/06,772.99,yes,locked 2006.217.08:05:02.61/valo/07,832.99,yes,locked 2006.217.08:05:02.61/valo/08,852.99,yes,locked 2006.217.08:05:03.70/vb/01,04,usb,yes,30,29 2006.217.08:05:03.70/vb/02,04,usb,yes,32,34 2006.217.08:05:03.70/vb/03,04,usb,yes,28,32 2006.217.08:05:03.70/vb/04,04,usb,yes,29,29 2006.217.08:05:03.70/vb/05,04,usb,yes,28,32 2006.217.08:05:03.70/vb/06,04,usb,yes,29,31 2006.217.08:05:03.70/vb/07,04,usb,yes,31,31 2006.217.08:05:03.70/vb/08,04,usb,yes,28,32 2006.217.08:05:03.94/vblo/01,632.99,yes,locked 2006.217.08:05:03.94/vblo/02,640.99,yes,locked 2006.217.08:05:03.94/vblo/03,656.99,yes,locked 2006.217.08:05:03.94/vblo/04,712.99,yes,locked 2006.217.08:05:03.94/vblo/05,744.99,yes,locked 2006.217.08:05:03.94/vblo/06,752.99,yes,locked 2006.217.08:05:03.94/vblo/07,734.99,yes,locked 2006.217.08:05:03.94/vblo/08,744.99,yes,locked 2006.217.08:05:04.09/vabw/8 2006.217.08:05:04.24/vbbw/8 2006.217.08:05:04.33/xfe/off,on,15.0 2006.217.08:05:04.71/ifatt/23,28,28,28 2006.217.08:05:05.07/fmout-gps/S +4.37E-07 2006.217.08:05:05.14:!2006.217.08:06:10 2006.217.08:06:10.01:data_valid=off 2006.217.08:06:10.01:postob 2006.217.08:06:10.09/cable/+6.3867E-03 2006.217.08:06:10.10/wx/30.79,1008.6,65 2006.217.08:06:11.08/fmout-gps/S +4.37E-07 2006.217.08:06:11.08:scan_name=217-0807,k06217,60 2006.217.08:06:11.08:source=1300+580,130252.47,574837.6,2000.0,ccw 2006.217.08:06:12.13#flagr#flagr/antenna,new-source 2006.217.08:06:12.13:checkk5 2006.217.08:06:12.51/chk_autoobs//k5ts1/ autoobs is running! 2006.217.08:06:12.89/chk_autoobs//k5ts2/ autoobs is running! 2006.217.08:06:13.26/chk_autoobs//k5ts3/ autoobs is running! 2006.217.08:06:13.63/chk_autoobs//k5ts4/ autoobs is running! 2006.217.08:06:13.99/chk_obsdata//k5ts1/T2170805??a.dat file size is correct (nominal:560MB, actual:560MB). 2006.217.08:06:14.36/chk_obsdata//k5ts2/T2170805??b.dat file size is correct (nominal:560MB, actual:560MB). 2006.217.08:06:14.73/chk_obsdata//k5ts3/T2170805??c.dat file size is correct (nominal:560MB, actual:560MB). 2006.217.08:06:15.10/chk_obsdata//k5ts4/T2170805??d.dat file size is correct (nominal:560MB, actual:560MB). 2006.217.08:06:15.78/k5log//k5ts1_log_newline 2006.217.08:06:16.48/k5log//k5ts2_log_newline 2006.217.08:06:17.17/k5log//k5ts3_log_newline 2006.217.08:06:17.86/k5log//k5ts4_log_newline 2006.217.08:06:17.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.217.08:06:17.89:4f8m12a=2 2006.217.08:06:17.89$4f8m12a/echo=on 2006.217.08:06:17.89$4f8m12a/pcalon 2006.217.08:06:17.89$pcalon/"no phase cal control is implemented here 2006.217.08:06:17.89$4f8m12a/"tpicd=stop 2006.217.08:06:17.89$4f8m12a/vc4f8 2006.217.08:06:17.89$vc4f8/valo=1,532.99 2006.217.08:06:17.90#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.217.08:06:17.90#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.217.08:06:17.90#ibcon#ireg 17 cls_cnt 0 2006.217.08:06:17.90#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.217.08:06:17.90#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.217.08:06:17.90#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.217.08:06:17.90#ibcon#enter wrdev, iclass 4, count 0 2006.217.08:06:17.90#ibcon#first serial, iclass 4, count 0 2006.217.08:06:17.90#ibcon#enter sib2, iclass 4, count 0 2006.217.08:06:17.90#ibcon#flushed, iclass 4, count 0 2006.217.08:06:17.90#ibcon#about to write, iclass 4, count 0 2006.217.08:06:17.90#ibcon#wrote, iclass 4, count 0 2006.217.08:06:17.90#ibcon#about to read 3, iclass 4, count 0 2006.217.08:06:17.93#ibcon#read 3, iclass 4, count 0 2006.217.08:06:17.93#ibcon#about to read 4, iclass 4, count 0 2006.217.08:06:17.93#ibcon#read 4, iclass 4, count 0 2006.217.08:06:17.93#ibcon#about to read 5, iclass 4, count 0 2006.217.08:06:17.93#ibcon#read 5, iclass 4, count 0 2006.217.08:06:17.93#ibcon#about to read 6, iclass 4, count 0 2006.217.08:06:17.93#ibcon#read 6, iclass 4, count 0 2006.217.08:06:17.93#ibcon#end of sib2, iclass 4, count 0 2006.217.08:06:17.93#ibcon#*mode == 0, iclass 4, count 0 2006.217.08:06:17.93#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.217.08:06:17.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.217.08:06:17.93#ibcon#*before write, iclass 4, count 0 2006.217.08:06:17.93#ibcon#enter sib2, iclass 4, count 0 2006.217.08:06:17.93#ibcon#flushed, iclass 4, count 0 2006.217.08:06:17.93#ibcon#about to write, iclass 4, count 0 2006.217.08:06:17.93#ibcon#wrote, iclass 4, count 0 2006.217.08:06:17.93#ibcon#about to read 3, iclass 4, count 0 2006.217.08:06:17.98#ibcon#read 3, iclass 4, count 0 2006.217.08:06:17.98#ibcon#about to read 4, iclass 4, count 0 2006.217.08:06:17.98#ibcon#read 4, iclass 4, count 0 2006.217.08:06:17.98#ibcon#about to read 5, iclass 4, count 0 2006.217.08:06:17.98#ibcon#read 5, iclass 4, count 0 2006.217.08:06:17.98#ibcon#about to read 6, iclass 4, count 0 2006.217.08:06:17.98#ibcon#read 6, iclass 4, count 0 2006.217.08:06:17.98#ibcon#end of sib2, iclass 4, count 0 2006.217.08:06:17.98#ibcon#*after write, iclass 4, count 0 2006.217.08:06:17.98#ibcon#*before return 0, iclass 4, count 0 2006.217.08:06:17.98#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.217.08:06:17.98#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.217.08:06:17.98#ibcon#about to clear, iclass 4 cls_cnt 0 2006.217.08:06:17.98#ibcon#cleared, iclass 4 cls_cnt 0 2006.217.08:06:17.98$vc4f8/va=1,5 2006.217.08:06:17.98#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.217.08:06:17.98#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.217.08:06:17.98#ibcon#ireg 11 cls_cnt 2 2006.217.08:06:17.98#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.217.08:06:17.98#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.217.08:06:17.98#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.217.08:06:17.98#ibcon#enter wrdev, iclass 6, count 2 2006.217.08:06:17.98#ibcon#first serial, iclass 6, count 2 2006.217.08:06:17.98#ibcon#enter sib2, iclass 6, count 2 2006.217.08:06:17.98#ibcon#flushed, iclass 6, count 2 2006.217.08:06:17.98#ibcon#about to write, iclass 6, count 2 2006.217.08:06:17.98#ibcon#wrote, iclass 6, count 2 2006.217.08:06:17.98#ibcon#about to read 3, iclass 6, count 2 2006.217.08:06:18.00#ibcon#read 3, iclass 6, count 2 2006.217.08:06:18.00#ibcon#about to read 4, iclass 6, count 2 2006.217.08:06:18.00#ibcon#read 4, iclass 6, count 2 2006.217.08:06:18.00#ibcon#about to read 5, iclass 6, count 2 2006.217.08:06:18.00#ibcon#read 5, iclass 6, count 2 2006.217.08:06:18.00#ibcon#about to read 6, iclass 6, count 2 2006.217.08:06:18.00#ibcon#read 6, iclass 6, count 2 2006.217.08:06:18.00#ibcon#end of sib2, iclass 6, count 2 2006.217.08:06:18.00#ibcon#*mode == 0, iclass 6, count 2 2006.217.08:06:18.00#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.217.08:06:18.00#ibcon#[25=AT01-05\r\n] 2006.217.08:06:18.00#ibcon#*before write, iclass 6, count 2 2006.217.08:06:18.00#ibcon#enter sib2, iclass 6, count 2 2006.217.08:06:18.00#ibcon#flushed, iclass 6, count 2 2006.217.08:06:18.00#ibcon#about to write, iclass 6, count 2 2006.217.08:06:18.00#ibcon#wrote, iclass 6, count 2 2006.217.08:06:18.00#ibcon#about to read 3, iclass 6, count 2 2006.217.08:06:18.03#ibcon#read 3, iclass 6, count 2 2006.217.08:06:18.03#ibcon#about to read 4, iclass 6, count 2 2006.217.08:06:18.03#ibcon#read 4, iclass 6, count 2 2006.217.08:06:18.03#ibcon#about to read 5, iclass 6, count 2 2006.217.08:06:18.03#ibcon#read 5, iclass 6, count 2 2006.217.08:06:18.03#ibcon#about to read 6, iclass 6, count 2 2006.217.08:06:18.03#ibcon#read 6, iclass 6, count 2 2006.217.08:06:18.03#ibcon#end of sib2, iclass 6, count 2 2006.217.08:06:18.03#ibcon#*after write, iclass 6, count 2 2006.217.08:06:18.03#ibcon#*before return 0, iclass 6, count 2 2006.217.08:06:18.03#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.217.08:06:18.03#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.217.08:06:18.03#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.217.08:06:18.03#ibcon#ireg 7 cls_cnt 0 2006.217.08:06:18.03#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.217.08:06:18.09#abcon#<5=/05 4.5 7.7 30.78 651008.6\r\n> 2006.217.08:06:18.11#abcon#{5=INTERFACE CLEAR} 2006.217.08:06:18.15#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.217.08:06:18.15#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.217.08:06:18.15#ibcon#enter wrdev, iclass 6, count 0 2006.217.08:06:18.15#ibcon#first serial, iclass 6, count 0 2006.217.08:06:18.15#ibcon#enter sib2, iclass 6, count 0 2006.217.08:06:18.15#ibcon#flushed, iclass 6, count 0 2006.217.08:06:18.15#ibcon#about to write, iclass 6, count 0 2006.217.08:06:18.15#ibcon#wrote, iclass 6, count 0 2006.217.08:06:18.15#ibcon#about to read 3, iclass 6, count 0 2006.217.08:06:18.17#ibcon#read 3, iclass 6, count 0 2006.217.08:06:18.17#ibcon#about to read 4, iclass 6, count 0 2006.217.08:06:18.17#ibcon#read 4, iclass 6, count 0 2006.217.08:06:18.17#ibcon#about to read 5, iclass 6, count 0 2006.217.08:06:18.17#ibcon#read 5, iclass 6, count 0 2006.217.08:06:18.17#ibcon#about to read 6, iclass 6, count 0 2006.217.08:06:18.17#ibcon#read 6, iclass 6, count 0 2006.217.08:06:18.17#ibcon#end of sib2, iclass 6, count 0 2006.217.08:06:18.17#ibcon#*mode == 0, iclass 6, count 0 2006.217.08:06:18.17#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.217.08:06:18.17#ibcon#[25=USB\r\n] 2006.217.08:06:18.17#ibcon#*before write, iclass 6, count 0 2006.217.08:06:18.17#ibcon#enter sib2, iclass 6, count 0 2006.217.08:06:18.17#ibcon#flushed, iclass 6, count 0 2006.217.08:06:18.17#ibcon#about to write, iclass 6, count 0 2006.217.08:06:18.17#ibcon#wrote, iclass 6, count 0 2006.217.08:06:18.17#ibcon#about to read 3, iclass 6, count 0 2006.217.08:06:18.17#abcon#[5=S1D000X0/0*\r\n] 2006.217.08:06:18.20#ibcon#read 3, iclass 6, count 0 2006.217.08:06:18.20#ibcon#about to read 4, iclass 6, count 0 2006.217.08:06:18.20#ibcon#read 4, iclass 6, count 0 2006.217.08:06:18.20#ibcon#about to read 5, iclass 6, count 0 2006.217.08:06:18.20#ibcon#read 5, iclass 6, count 0 2006.217.08:06:18.20#ibcon#about to read 6, iclass 6, count 0 2006.217.08:06:18.20#ibcon#read 6, iclass 6, count 0 2006.217.08:06:18.20#ibcon#end of sib2, iclass 6, count 0 2006.217.08:06:18.20#ibcon#*after write, iclass 6, count 0 2006.217.08:06:18.20#ibcon#*before return 0, iclass 6, count 0 2006.217.08:06:18.20#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.217.08:06:18.20#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.217.08:06:18.20#ibcon#about to clear, iclass 6 cls_cnt 0 2006.217.08:06:18.20#ibcon#cleared, iclass 6 cls_cnt 0 2006.217.08:06:18.20$vc4f8/valo=2,572.99 2006.217.08:06:18.20#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.217.08:06:18.20#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.217.08:06:18.20#ibcon#ireg 17 cls_cnt 0 2006.217.08:06:18.20#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.217.08:06:18.20#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.217.08:06:18.20#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.217.08:06:18.20#ibcon#enter wrdev, iclass 14, count 0 2006.217.08:06:18.20#ibcon#first serial, iclass 14, count 0 2006.217.08:06:18.20#ibcon#enter sib2, iclass 14, count 0 2006.217.08:06:18.20#ibcon#flushed, iclass 14, count 0 2006.217.08:06:18.20#ibcon#about to write, iclass 14, count 0 2006.217.08:06:18.20#ibcon#wrote, iclass 14, count 0 2006.217.08:06:18.20#ibcon#about to read 3, iclass 14, count 0 2006.217.08:06:18.22#ibcon#read 3, iclass 14, count 0 2006.217.08:06:18.22#ibcon#about to read 4, iclass 14, count 0 2006.217.08:06:18.22#ibcon#read 4, iclass 14, count 0 2006.217.08:06:18.22#ibcon#about to read 5, iclass 14, count 0 2006.217.08:06:18.22#ibcon#read 5, iclass 14, count 0 2006.217.08:06:18.22#ibcon#about to read 6, iclass 14, count 0 2006.217.08:06:18.22#ibcon#read 6, iclass 14, count 0 2006.217.08:06:18.22#ibcon#end of sib2, iclass 14, count 0 2006.217.08:06:18.22#ibcon#*mode == 0, iclass 14, count 0 2006.217.08:06:18.22#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.217.08:06:18.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.217.08:06:18.22#ibcon#*before write, iclass 14, count 0 2006.217.08:06:18.22#ibcon#enter sib2, iclass 14, count 0 2006.217.08:06:18.22#ibcon#flushed, iclass 14, count 0 2006.217.08:06:18.22#ibcon#about to write, iclass 14, count 0 2006.217.08:06:18.22#ibcon#wrote, iclass 14, count 0 2006.217.08:06:18.22#ibcon#about to read 3, iclass 14, count 0 2006.217.08:06:18.26#ibcon#read 3, iclass 14, count 0 2006.217.08:06:18.26#ibcon#about to read 4, iclass 14, count 0 2006.217.08:06:18.26#ibcon#read 4, iclass 14, count 0 2006.217.08:06:18.26#ibcon#about to read 5, iclass 14, count 0 2006.217.08:06:18.26#ibcon#read 5, iclass 14, count 0 2006.217.08:06:18.26#ibcon#about to read 6, iclass 14, count 0 2006.217.08:06:18.26#ibcon#read 6, iclass 14, count 0 2006.217.08:06:18.26#ibcon#end of sib2, iclass 14, count 0 2006.217.08:06:18.26#ibcon#*after write, iclass 14, count 0 2006.217.08:06:18.26#ibcon#*before return 0, iclass 14, count 0 2006.217.08:06:18.26#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.217.08:06:18.26#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.217.08:06:18.26#ibcon#about to clear, iclass 14 cls_cnt 0 2006.217.08:06:18.26#ibcon#cleared, iclass 14 cls_cnt 0 2006.217.08:06:18.26$vc4f8/va=2,4 2006.217.08:06:18.26#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.217.08:06:18.26#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.217.08:06:18.26#ibcon#ireg 11 cls_cnt 2 2006.217.08:06:18.26#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.217.08:06:18.32#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.217.08:06:18.32#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.217.08:06:18.32#ibcon#enter wrdev, iclass 16, count 2 2006.217.08:06:18.32#ibcon#first serial, iclass 16, count 2 2006.217.08:06:18.32#ibcon#enter sib2, iclass 16, count 2 2006.217.08:06:18.32#ibcon#flushed, iclass 16, count 2 2006.217.08:06:18.32#ibcon#about to write, iclass 16, count 2 2006.217.08:06:18.32#ibcon#wrote, iclass 16, count 2 2006.217.08:06:18.32#ibcon#about to read 3, iclass 16, count 2 2006.217.08:06:18.34#ibcon#read 3, iclass 16, count 2 2006.217.08:06:18.34#ibcon#about to read 4, iclass 16, count 2 2006.217.08:06:18.34#ibcon#read 4, iclass 16, count 2 2006.217.08:06:18.34#ibcon#about to read 5, iclass 16, count 2 2006.217.08:06:18.34#ibcon#read 5, iclass 16, count 2 2006.217.08:06:18.34#ibcon#about to read 6, iclass 16, count 2 2006.217.08:06:18.34#ibcon#read 6, iclass 16, count 2 2006.217.08:06:18.34#ibcon#end of sib2, iclass 16, count 2 2006.217.08:06:18.34#ibcon#*mode == 0, iclass 16, count 2 2006.217.08:06:18.34#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.217.08:06:18.34#ibcon#[25=AT02-04\r\n] 2006.217.08:06:18.34#ibcon#*before write, iclass 16, count 2 2006.217.08:06:18.34#ibcon#enter sib2, iclass 16, count 2 2006.217.08:06:18.34#ibcon#flushed, iclass 16, count 2 2006.217.08:06:18.34#ibcon#about to write, iclass 16, count 2 2006.217.08:06:18.34#ibcon#wrote, iclass 16, count 2 2006.217.08:06:18.34#ibcon#about to read 3, iclass 16, count 2 2006.217.08:06:18.37#ibcon#read 3, iclass 16, count 2 2006.217.08:06:18.37#ibcon#about to read 4, iclass 16, count 2 2006.217.08:06:18.37#ibcon#read 4, iclass 16, count 2 2006.217.08:06:18.37#ibcon#about to read 5, iclass 16, count 2 2006.217.08:06:18.37#ibcon#read 5, iclass 16, count 2 2006.217.08:06:18.37#ibcon#about to read 6, iclass 16, count 2 2006.217.08:06:18.37#ibcon#read 6, iclass 16, count 2 2006.217.08:06:18.37#ibcon#end of sib2, iclass 16, count 2 2006.217.08:06:18.37#ibcon#*after write, iclass 16, count 2 2006.217.08:06:18.37#ibcon#*before return 0, iclass 16, count 2 2006.217.08:06:18.37#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.217.08:06:18.37#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.217.08:06:18.37#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.217.08:06:18.37#ibcon#ireg 7 cls_cnt 0 2006.217.08:06:18.37#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.217.08:06:18.49#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.217.08:06:18.49#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.217.08:06:18.49#ibcon#enter wrdev, iclass 16, count 0 2006.217.08:06:18.49#ibcon#first serial, iclass 16, count 0 2006.217.08:06:18.49#ibcon#enter sib2, iclass 16, count 0 2006.217.08:06:18.49#ibcon#flushed, iclass 16, count 0 2006.217.08:06:18.49#ibcon#about to write, iclass 16, count 0 2006.217.08:06:18.49#ibcon#wrote, iclass 16, count 0 2006.217.08:06:18.49#ibcon#about to read 3, iclass 16, count 0 2006.217.08:06:18.51#ibcon#read 3, iclass 16, count 0 2006.217.08:06:18.51#ibcon#about to read 4, iclass 16, count 0 2006.217.08:06:18.51#ibcon#read 4, iclass 16, count 0 2006.217.08:06:18.51#ibcon#about to read 5, iclass 16, count 0 2006.217.08:06:18.51#ibcon#read 5, iclass 16, count 0 2006.217.08:06:18.51#ibcon#about to read 6, iclass 16, count 0 2006.217.08:06:18.51#ibcon#read 6, iclass 16, count 0 2006.217.08:06:18.51#ibcon#end of sib2, iclass 16, count 0 2006.217.08:06:18.51#ibcon#*mode == 0, iclass 16, count 0 2006.217.08:06:18.51#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.217.08:06:18.51#ibcon#[25=USB\r\n] 2006.217.08:06:18.51#ibcon#*before write, iclass 16, count 0 2006.217.08:06:18.51#ibcon#enter sib2, iclass 16, count 0 2006.217.08:06:18.51#ibcon#flushed, iclass 16, count 0 2006.217.08:06:18.51#ibcon#about to write, iclass 16, count 0 2006.217.08:06:18.51#ibcon#wrote, iclass 16, count 0 2006.217.08:06:18.51#ibcon#about to read 3, iclass 16, count 0 2006.217.08:06:18.54#ibcon#read 3, iclass 16, count 0 2006.217.08:06:18.54#ibcon#about to read 4, iclass 16, count 0 2006.217.08:06:18.54#ibcon#read 4, iclass 16, count 0 2006.217.08:06:18.54#ibcon#about to read 5, iclass 16, count 0 2006.217.08:06:18.54#ibcon#read 5, iclass 16, count 0 2006.217.08:06:18.54#ibcon#about to read 6, iclass 16, count 0 2006.217.08:06:18.54#ibcon#read 6, iclass 16, count 0 2006.217.08:06:18.54#ibcon#end of sib2, iclass 16, count 0 2006.217.08:06:18.54#ibcon#*after write, iclass 16, count 0 2006.217.08:06:18.54#ibcon#*before return 0, iclass 16, count 0 2006.217.08:06:18.54#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.217.08:06:18.54#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.217.08:06:18.54#ibcon#about to clear, iclass 16 cls_cnt 0 2006.217.08:06:18.54#ibcon#cleared, iclass 16 cls_cnt 0 2006.217.08:06:18.54$vc4f8/valo=3,672.99 2006.217.08:06:18.54#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.217.08:06:18.54#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.217.08:06:18.54#ibcon#ireg 17 cls_cnt 0 2006.217.08:06:18.54#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.217.08:06:18.54#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.217.08:06:18.54#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.217.08:06:18.54#ibcon#enter wrdev, iclass 18, count 0 2006.217.08:06:18.54#ibcon#first serial, iclass 18, count 0 2006.217.08:06:18.54#ibcon#enter sib2, iclass 18, count 0 2006.217.08:06:18.54#ibcon#flushed, iclass 18, count 0 2006.217.08:06:18.54#ibcon#about to write, iclass 18, count 0 2006.217.08:06:18.54#ibcon#wrote, iclass 18, count 0 2006.217.08:06:18.54#ibcon#about to read 3, iclass 18, count 0 2006.217.08:06:18.56#ibcon#read 3, iclass 18, count 0 2006.217.08:06:18.56#ibcon#about to read 4, iclass 18, count 0 2006.217.08:06:18.56#ibcon#read 4, iclass 18, count 0 2006.217.08:06:18.56#ibcon#about to read 5, iclass 18, count 0 2006.217.08:06:18.56#ibcon#read 5, iclass 18, count 0 2006.217.08:06:18.56#ibcon#about to read 6, iclass 18, count 0 2006.217.08:06:18.56#ibcon#read 6, iclass 18, count 0 2006.217.08:06:18.56#ibcon#end of sib2, iclass 18, count 0 2006.217.08:06:18.56#ibcon#*mode == 0, iclass 18, count 0 2006.217.08:06:18.56#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.217.08:06:18.56#ibcon#[26=FRQ=03,672.99\r\n] 2006.217.08:06:18.56#ibcon#*before write, iclass 18, count 0 2006.217.08:06:18.56#ibcon#enter sib2, iclass 18, count 0 2006.217.08:06:18.56#ibcon#flushed, iclass 18, count 0 2006.217.08:06:18.56#ibcon#about to write, iclass 18, count 0 2006.217.08:06:18.56#ibcon#wrote, iclass 18, count 0 2006.217.08:06:18.56#ibcon#about to read 3, iclass 18, count 0 2006.217.08:06:18.60#ibcon#read 3, iclass 18, count 0 2006.217.08:06:18.60#ibcon#about to read 4, iclass 18, count 0 2006.217.08:06:18.60#ibcon#read 4, iclass 18, count 0 2006.217.08:06:18.60#ibcon#about to read 5, iclass 18, count 0 2006.217.08:06:18.60#ibcon#read 5, iclass 18, count 0 2006.217.08:06:18.60#ibcon#about to read 6, iclass 18, count 0 2006.217.08:06:18.60#ibcon#read 6, iclass 18, count 0 2006.217.08:06:18.60#ibcon#end of sib2, iclass 18, count 0 2006.217.08:06:18.60#ibcon#*after write, iclass 18, count 0 2006.217.08:06:18.60#ibcon#*before return 0, iclass 18, count 0 2006.217.08:06:18.60#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.217.08:06:18.60#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.217.08:06:18.60#ibcon#about to clear, iclass 18 cls_cnt 0 2006.217.08:06:18.60#ibcon#cleared, iclass 18 cls_cnt 0 2006.217.08:06:18.60$vc4f8/va=3,4 2006.217.08:06:18.60#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.217.08:06:18.60#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.217.08:06:18.60#ibcon#ireg 11 cls_cnt 2 2006.217.08:06:18.60#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.217.08:06:18.66#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.217.08:06:18.66#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.217.08:06:18.66#ibcon#enter wrdev, iclass 20, count 2 2006.217.08:06:18.66#ibcon#first serial, iclass 20, count 2 2006.217.08:06:18.66#ibcon#enter sib2, iclass 20, count 2 2006.217.08:06:18.66#ibcon#flushed, iclass 20, count 2 2006.217.08:06:18.66#ibcon#about to write, iclass 20, count 2 2006.217.08:06:18.66#ibcon#wrote, iclass 20, count 2 2006.217.08:06:18.66#ibcon#about to read 3, iclass 20, count 2 2006.217.08:06:18.68#ibcon#read 3, iclass 20, count 2 2006.217.08:06:18.68#ibcon#about to read 4, iclass 20, count 2 2006.217.08:06:18.68#ibcon#read 4, iclass 20, count 2 2006.217.08:06:18.68#ibcon#about to read 5, iclass 20, count 2 2006.217.08:06:18.68#ibcon#read 5, iclass 20, count 2 2006.217.08:06:18.68#ibcon#about to read 6, iclass 20, count 2 2006.217.08:06:18.68#ibcon#read 6, iclass 20, count 2 2006.217.08:06:18.68#ibcon#end of sib2, iclass 20, count 2 2006.217.08:06:18.68#ibcon#*mode == 0, iclass 20, count 2 2006.217.08:06:18.68#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.217.08:06:18.68#ibcon#[25=AT03-04\r\n] 2006.217.08:06:18.68#ibcon#*before write, iclass 20, count 2 2006.217.08:06:18.68#ibcon#enter sib2, iclass 20, count 2 2006.217.08:06:18.68#ibcon#flushed, iclass 20, count 2 2006.217.08:06:18.68#ibcon#about to write, iclass 20, count 2 2006.217.08:06:18.68#ibcon#wrote, iclass 20, count 2 2006.217.08:06:18.68#ibcon#about to read 3, iclass 20, count 2 2006.217.08:06:18.71#ibcon#read 3, iclass 20, count 2 2006.217.08:06:18.71#ibcon#about to read 4, iclass 20, count 2 2006.217.08:06:18.71#ibcon#read 4, iclass 20, count 2 2006.217.08:06:18.71#ibcon#about to read 5, iclass 20, count 2 2006.217.08:06:18.71#ibcon#read 5, iclass 20, count 2 2006.217.08:06:18.71#ibcon#about to read 6, iclass 20, count 2 2006.217.08:06:18.71#ibcon#read 6, iclass 20, count 2 2006.217.08:06:18.71#ibcon#end of sib2, iclass 20, count 2 2006.217.08:06:18.71#ibcon#*after write, iclass 20, count 2 2006.217.08:06:18.71#ibcon#*before return 0, iclass 20, count 2 2006.217.08:06:18.71#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.217.08:06:18.71#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.217.08:06:18.71#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.217.08:06:18.71#ibcon#ireg 7 cls_cnt 0 2006.217.08:06:18.71#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.217.08:06:18.83#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.217.08:06:18.83#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.217.08:06:18.83#ibcon#enter wrdev, iclass 20, count 0 2006.217.08:06:18.83#ibcon#first serial, iclass 20, count 0 2006.217.08:06:18.83#ibcon#enter sib2, iclass 20, count 0 2006.217.08:06:18.83#ibcon#flushed, iclass 20, count 0 2006.217.08:06:18.83#ibcon#about to write, iclass 20, count 0 2006.217.08:06:18.83#ibcon#wrote, iclass 20, count 0 2006.217.08:06:18.83#ibcon#about to read 3, iclass 20, count 0 2006.217.08:06:18.85#ibcon#read 3, iclass 20, count 0 2006.217.08:06:18.85#ibcon#about to read 4, iclass 20, count 0 2006.217.08:06:18.85#ibcon#read 4, iclass 20, count 0 2006.217.08:06:18.85#ibcon#about to read 5, iclass 20, count 0 2006.217.08:06:18.85#ibcon#read 5, iclass 20, count 0 2006.217.08:06:18.85#ibcon#about to read 6, iclass 20, count 0 2006.217.08:06:18.85#ibcon#read 6, iclass 20, count 0 2006.217.08:06:18.85#ibcon#end of sib2, iclass 20, count 0 2006.217.08:06:18.85#ibcon#*mode == 0, iclass 20, count 0 2006.217.08:06:18.85#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.217.08:06:18.85#ibcon#[25=USB\r\n] 2006.217.08:06:18.85#ibcon#*before write, iclass 20, count 0 2006.217.08:06:18.85#ibcon#enter sib2, iclass 20, count 0 2006.217.08:06:18.85#ibcon#flushed, iclass 20, count 0 2006.217.08:06:18.85#ibcon#about to write, iclass 20, count 0 2006.217.08:06:18.85#ibcon#wrote, iclass 20, count 0 2006.217.08:06:18.85#ibcon#about to read 3, iclass 20, count 0 2006.217.08:06:18.88#ibcon#read 3, iclass 20, count 0 2006.217.08:06:18.88#ibcon#about to read 4, iclass 20, count 0 2006.217.08:06:18.88#ibcon#read 4, iclass 20, count 0 2006.217.08:06:18.88#ibcon#about to read 5, iclass 20, count 0 2006.217.08:06:18.88#ibcon#read 5, iclass 20, count 0 2006.217.08:06:18.88#ibcon#about to read 6, iclass 20, count 0 2006.217.08:06:18.88#ibcon#read 6, iclass 20, count 0 2006.217.08:06:18.88#ibcon#end of sib2, iclass 20, count 0 2006.217.08:06:18.88#ibcon#*after write, iclass 20, count 0 2006.217.08:06:18.88#ibcon#*before return 0, iclass 20, count 0 2006.217.08:06:18.88#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.217.08:06:18.88#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.217.08:06:18.88#ibcon#about to clear, iclass 20 cls_cnt 0 2006.217.08:06:18.88#ibcon#cleared, iclass 20 cls_cnt 0 2006.217.08:06:18.88$vc4f8/valo=4,832.99 2006.217.08:06:18.88#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.217.08:06:18.88#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.217.08:06:18.88#ibcon#ireg 17 cls_cnt 0 2006.217.08:06:18.88#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.217.08:06:18.88#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.217.08:06:18.88#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.217.08:06:18.88#ibcon#enter wrdev, iclass 22, count 0 2006.217.08:06:18.88#ibcon#first serial, iclass 22, count 0 2006.217.08:06:18.88#ibcon#enter sib2, iclass 22, count 0 2006.217.08:06:18.88#ibcon#flushed, iclass 22, count 0 2006.217.08:06:18.88#ibcon#about to write, iclass 22, count 0 2006.217.08:06:18.88#ibcon#wrote, iclass 22, count 0 2006.217.08:06:18.88#ibcon#about to read 3, iclass 22, count 0 2006.217.08:06:18.90#ibcon#read 3, iclass 22, count 0 2006.217.08:06:18.90#ibcon#about to read 4, iclass 22, count 0 2006.217.08:06:18.90#ibcon#read 4, iclass 22, count 0 2006.217.08:06:18.90#ibcon#about to read 5, iclass 22, count 0 2006.217.08:06:18.90#ibcon#read 5, iclass 22, count 0 2006.217.08:06:18.90#ibcon#about to read 6, iclass 22, count 0 2006.217.08:06:18.90#ibcon#read 6, iclass 22, count 0 2006.217.08:06:18.90#ibcon#end of sib2, iclass 22, count 0 2006.217.08:06:18.90#ibcon#*mode == 0, iclass 22, count 0 2006.217.08:06:18.90#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.217.08:06:18.90#ibcon#[26=FRQ=04,832.99\r\n] 2006.217.08:06:18.90#ibcon#*before write, iclass 22, count 0 2006.217.08:06:18.90#ibcon#enter sib2, iclass 22, count 0 2006.217.08:06:18.90#ibcon#flushed, iclass 22, count 0 2006.217.08:06:18.90#ibcon#about to write, iclass 22, count 0 2006.217.08:06:18.90#ibcon#wrote, iclass 22, count 0 2006.217.08:06:18.90#ibcon#about to read 3, iclass 22, count 0 2006.217.08:06:18.94#ibcon#read 3, iclass 22, count 0 2006.217.08:06:18.94#ibcon#about to read 4, iclass 22, count 0 2006.217.08:06:18.94#ibcon#read 4, iclass 22, count 0 2006.217.08:06:18.94#ibcon#about to read 5, iclass 22, count 0 2006.217.08:06:18.94#ibcon#read 5, iclass 22, count 0 2006.217.08:06:18.94#ibcon#about to read 6, iclass 22, count 0 2006.217.08:06:18.94#ibcon#read 6, iclass 22, count 0 2006.217.08:06:18.94#ibcon#end of sib2, iclass 22, count 0 2006.217.08:06:18.94#ibcon#*after write, iclass 22, count 0 2006.217.08:06:18.94#ibcon#*before return 0, iclass 22, count 0 2006.217.08:06:18.94#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.217.08:06:18.94#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.217.08:06:18.94#ibcon#about to clear, iclass 22 cls_cnt 0 2006.217.08:06:18.94#ibcon#cleared, iclass 22 cls_cnt 0 2006.217.08:06:18.94$vc4f8/va=4,4 2006.217.08:06:18.94#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.217.08:06:18.94#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.217.08:06:18.94#ibcon#ireg 11 cls_cnt 2 2006.217.08:06:18.94#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.217.08:06:19.00#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.217.08:06:19.00#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.217.08:06:19.00#ibcon#enter wrdev, iclass 24, count 2 2006.217.08:06:19.00#ibcon#first serial, iclass 24, count 2 2006.217.08:06:19.00#ibcon#enter sib2, iclass 24, count 2 2006.217.08:06:19.00#ibcon#flushed, iclass 24, count 2 2006.217.08:06:19.00#ibcon#about to write, iclass 24, count 2 2006.217.08:06:19.00#ibcon#wrote, iclass 24, count 2 2006.217.08:06:19.00#ibcon#about to read 3, iclass 24, count 2 2006.217.08:06:19.02#ibcon#read 3, iclass 24, count 2 2006.217.08:06:19.02#ibcon#about to read 4, iclass 24, count 2 2006.217.08:06:19.02#ibcon#read 4, iclass 24, count 2 2006.217.08:06:19.02#ibcon#about to read 5, iclass 24, count 2 2006.217.08:06:19.02#ibcon#read 5, iclass 24, count 2 2006.217.08:06:19.02#ibcon#about to read 6, iclass 24, count 2 2006.217.08:06:19.02#ibcon#read 6, iclass 24, count 2 2006.217.08:06:19.02#ibcon#end of sib2, iclass 24, count 2 2006.217.08:06:19.02#ibcon#*mode == 0, iclass 24, count 2 2006.217.08:06:19.02#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.217.08:06:19.02#ibcon#[25=AT04-04\r\n] 2006.217.08:06:19.02#ibcon#*before write, iclass 24, count 2 2006.217.08:06:19.02#ibcon#enter sib2, iclass 24, count 2 2006.217.08:06:19.02#ibcon#flushed, iclass 24, count 2 2006.217.08:06:19.02#ibcon#about to write, iclass 24, count 2 2006.217.08:06:19.02#ibcon#wrote, iclass 24, count 2 2006.217.08:06:19.02#ibcon#about to read 3, iclass 24, count 2 2006.217.08:06:19.05#ibcon#read 3, iclass 24, count 2 2006.217.08:06:19.05#ibcon#about to read 4, iclass 24, count 2 2006.217.08:06:19.05#ibcon#read 4, iclass 24, count 2 2006.217.08:06:19.05#ibcon#about to read 5, iclass 24, count 2 2006.217.08:06:19.05#ibcon#read 5, iclass 24, count 2 2006.217.08:06:19.05#ibcon#about to read 6, iclass 24, count 2 2006.217.08:06:19.05#ibcon#read 6, iclass 24, count 2 2006.217.08:06:19.05#ibcon#end of sib2, iclass 24, count 2 2006.217.08:06:19.05#ibcon#*after write, iclass 24, count 2 2006.217.08:06:19.05#ibcon#*before return 0, iclass 24, count 2 2006.217.08:06:19.05#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.217.08:06:19.05#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.217.08:06:19.05#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.217.08:06:19.05#ibcon#ireg 7 cls_cnt 0 2006.217.08:06:19.05#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.217.08:06:19.17#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.217.08:06:19.17#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.217.08:06:19.17#ibcon#enter wrdev, iclass 24, count 0 2006.217.08:06:19.17#ibcon#first serial, iclass 24, count 0 2006.217.08:06:19.17#ibcon#enter sib2, iclass 24, count 0 2006.217.08:06:19.17#ibcon#flushed, iclass 24, count 0 2006.217.08:06:19.17#ibcon#about to write, iclass 24, count 0 2006.217.08:06:19.17#ibcon#wrote, iclass 24, count 0 2006.217.08:06:19.17#ibcon#about to read 3, iclass 24, count 0 2006.217.08:06:19.19#ibcon#read 3, iclass 24, count 0 2006.217.08:06:19.19#ibcon#about to read 4, iclass 24, count 0 2006.217.08:06:19.19#ibcon#read 4, iclass 24, count 0 2006.217.08:06:19.19#ibcon#about to read 5, iclass 24, count 0 2006.217.08:06:19.19#ibcon#read 5, iclass 24, count 0 2006.217.08:06:19.19#ibcon#about to read 6, iclass 24, count 0 2006.217.08:06:19.19#ibcon#read 6, iclass 24, count 0 2006.217.08:06:19.19#ibcon#end of sib2, iclass 24, count 0 2006.217.08:06:19.19#ibcon#*mode == 0, iclass 24, count 0 2006.217.08:06:19.19#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.217.08:06:19.19#ibcon#[25=USB\r\n] 2006.217.08:06:19.19#ibcon#*before write, iclass 24, count 0 2006.217.08:06:19.19#ibcon#enter sib2, iclass 24, count 0 2006.217.08:06:19.19#ibcon#flushed, iclass 24, count 0 2006.217.08:06:19.19#ibcon#about to write, iclass 24, count 0 2006.217.08:06:19.19#ibcon#wrote, iclass 24, count 0 2006.217.08:06:19.19#ibcon#about to read 3, iclass 24, count 0 2006.217.08:06:19.22#ibcon#read 3, iclass 24, count 0 2006.217.08:06:19.22#ibcon#about to read 4, iclass 24, count 0 2006.217.08:06:19.22#ibcon#read 4, iclass 24, count 0 2006.217.08:06:19.22#ibcon#about to read 5, iclass 24, count 0 2006.217.08:06:19.22#ibcon#read 5, iclass 24, count 0 2006.217.08:06:19.22#ibcon#about to read 6, iclass 24, count 0 2006.217.08:06:19.22#ibcon#read 6, iclass 24, count 0 2006.217.08:06:19.22#ibcon#end of sib2, iclass 24, count 0 2006.217.08:06:19.22#ibcon#*after write, iclass 24, count 0 2006.217.08:06:19.22#ibcon#*before return 0, iclass 24, count 0 2006.217.08:06:19.22#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.217.08:06:19.22#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.217.08:06:19.22#ibcon#about to clear, iclass 24 cls_cnt 0 2006.217.08:06:19.22#ibcon#cleared, iclass 24 cls_cnt 0 2006.217.08:06:19.22$vc4f8/valo=5,652.99 2006.217.08:06:19.22#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.217.08:06:19.22#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.217.08:06:19.22#ibcon#ireg 17 cls_cnt 0 2006.217.08:06:19.22#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.217.08:06:19.22#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.217.08:06:19.22#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.217.08:06:19.22#ibcon#enter wrdev, iclass 26, count 0 2006.217.08:06:19.22#ibcon#first serial, iclass 26, count 0 2006.217.08:06:19.22#ibcon#enter sib2, iclass 26, count 0 2006.217.08:06:19.22#ibcon#flushed, iclass 26, count 0 2006.217.08:06:19.22#ibcon#about to write, iclass 26, count 0 2006.217.08:06:19.22#ibcon#wrote, iclass 26, count 0 2006.217.08:06:19.22#ibcon#about to read 3, iclass 26, count 0 2006.217.08:06:19.24#ibcon#read 3, iclass 26, count 0 2006.217.08:06:19.24#ibcon#about to read 4, iclass 26, count 0 2006.217.08:06:19.24#ibcon#read 4, iclass 26, count 0 2006.217.08:06:19.24#ibcon#about to read 5, iclass 26, count 0 2006.217.08:06:19.24#ibcon#read 5, iclass 26, count 0 2006.217.08:06:19.24#ibcon#about to read 6, iclass 26, count 0 2006.217.08:06:19.24#ibcon#read 6, iclass 26, count 0 2006.217.08:06:19.24#ibcon#end of sib2, iclass 26, count 0 2006.217.08:06:19.24#ibcon#*mode == 0, iclass 26, count 0 2006.217.08:06:19.24#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.217.08:06:19.24#ibcon#[26=FRQ=05,652.99\r\n] 2006.217.08:06:19.24#ibcon#*before write, iclass 26, count 0 2006.217.08:06:19.24#ibcon#enter sib2, iclass 26, count 0 2006.217.08:06:19.24#ibcon#flushed, iclass 26, count 0 2006.217.08:06:19.24#ibcon#about to write, iclass 26, count 0 2006.217.08:06:19.24#ibcon#wrote, iclass 26, count 0 2006.217.08:06:19.24#ibcon#about to read 3, iclass 26, count 0 2006.217.08:06:19.28#ibcon#read 3, iclass 26, count 0 2006.217.08:06:19.28#ibcon#about to read 4, iclass 26, count 0 2006.217.08:06:19.28#ibcon#read 4, iclass 26, count 0 2006.217.08:06:19.28#ibcon#about to read 5, iclass 26, count 0 2006.217.08:06:19.28#ibcon#read 5, iclass 26, count 0 2006.217.08:06:19.28#ibcon#about to read 6, iclass 26, count 0 2006.217.08:06:19.28#ibcon#read 6, iclass 26, count 0 2006.217.08:06:19.28#ibcon#end of sib2, iclass 26, count 0 2006.217.08:06:19.28#ibcon#*after write, iclass 26, count 0 2006.217.08:06:19.28#ibcon#*before return 0, iclass 26, count 0 2006.217.08:06:19.28#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.217.08:06:19.28#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.217.08:06:19.28#ibcon#about to clear, iclass 26 cls_cnt 0 2006.217.08:06:19.28#ibcon#cleared, iclass 26 cls_cnt 0 2006.217.08:06:19.28$vc4f8/va=5,7 2006.217.08:06:19.28#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.217.08:06:19.28#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.217.08:06:19.28#ibcon#ireg 11 cls_cnt 2 2006.217.08:06:19.28#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.217.08:06:19.34#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.217.08:06:19.34#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.217.08:06:19.34#ibcon#enter wrdev, iclass 28, count 2 2006.217.08:06:19.34#ibcon#first serial, iclass 28, count 2 2006.217.08:06:19.34#ibcon#enter sib2, iclass 28, count 2 2006.217.08:06:19.34#ibcon#flushed, iclass 28, count 2 2006.217.08:06:19.34#ibcon#about to write, iclass 28, count 2 2006.217.08:06:19.34#ibcon#wrote, iclass 28, count 2 2006.217.08:06:19.34#ibcon#about to read 3, iclass 28, count 2 2006.217.08:06:19.36#ibcon#read 3, iclass 28, count 2 2006.217.08:06:19.36#ibcon#about to read 4, iclass 28, count 2 2006.217.08:06:19.36#ibcon#read 4, iclass 28, count 2 2006.217.08:06:19.36#ibcon#about to read 5, iclass 28, count 2 2006.217.08:06:19.36#ibcon#read 5, iclass 28, count 2 2006.217.08:06:19.36#ibcon#about to read 6, iclass 28, count 2 2006.217.08:06:19.36#ibcon#read 6, iclass 28, count 2 2006.217.08:06:19.36#ibcon#end of sib2, iclass 28, count 2 2006.217.08:06:19.36#ibcon#*mode == 0, iclass 28, count 2 2006.217.08:06:19.36#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.217.08:06:19.36#ibcon#[25=AT05-07\r\n] 2006.217.08:06:19.36#ibcon#*before write, iclass 28, count 2 2006.217.08:06:19.36#ibcon#enter sib2, iclass 28, count 2 2006.217.08:06:19.36#ibcon#flushed, iclass 28, count 2 2006.217.08:06:19.36#ibcon#about to write, iclass 28, count 2 2006.217.08:06:19.36#ibcon#wrote, iclass 28, count 2 2006.217.08:06:19.36#ibcon#about to read 3, iclass 28, count 2 2006.217.08:06:19.39#ibcon#read 3, iclass 28, count 2 2006.217.08:06:19.39#ibcon#about to read 4, iclass 28, count 2 2006.217.08:06:19.39#ibcon#read 4, iclass 28, count 2 2006.217.08:06:19.39#ibcon#about to read 5, iclass 28, count 2 2006.217.08:06:19.39#ibcon#read 5, iclass 28, count 2 2006.217.08:06:19.39#ibcon#about to read 6, iclass 28, count 2 2006.217.08:06:19.39#ibcon#read 6, iclass 28, count 2 2006.217.08:06:19.39#ibcon#end of sib2, iclass 28, count 2 2006.217.08:06:19.39#ibcon#*after write, iclass 28, count 2 2006.217.08:06:19.39#ibcon#*before return 0, iclass 28, count 2 2006.217.08:06:19.39#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.217.08:06:19.39#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.217.08:06:19.39#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.217.08:06:19.39#ibcon#ireg 7 cls_cnt 0 2006.217.08:06:19.39#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.217.08:06:19.51#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.217.08:06:19.51#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.217.08:06:19.51#ibcon#enter wrdev, iclass 28, count 0 2006.217.08:06:19.51#ibcon#first serial, iclass 28, count 0 2006.217.08:06:19.51#ibcon#enter sib2, iclass 28, count 0 2006.217.08:06:19.51#ibcon#flushed, iclass 28, count 0 2006.217.08:06:19.51#ibcon#about to write, iclass 28, count 0 2006.217.08:06:19.51#ibcon#wrote, iclass 28, count 0 2006.217.08:06:19.51#ibcon#about to read 3, iclass 28, count 0 2006.217.08:06:19.53#ibcon#read 3, iclass 28, count 0 2006.217.08:06:19.53#ibcon#about to read 4, iclass 28, count 0 2006.217.08:06:19.53#ibcon#read 4, iclass 28, count 0 2006.217.08:06:19.53#ibcon#about to read 5, iclass 28, count 0 2006.217.08:06:19.53#ibcon#read 5, iclass 28, count 0 2006.217.08:06:19.53#ibcon#about to read 6, iclass 28, count 0 2006.217.08:06:19.53#ibcon#read 6, iclass 28, count 0 2006.217.08:06:19.53#ibcon#end of sib2, iclass 28, count 0 2006.217.08:06:19.53#ibcon#*mode == 0, iclass 28, count 0 2006.217.08:06:19.53#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.217.08:06:19.53#ibcon#[25=USB\r\n] 2006.217.08:06:19.53#ibcon#*before write, iclass 28, count 0 2006.217.08:06:19.53#ibcon#enter sib2, iclass 28, count 0 2006.217.08:06:19.53#ibcon#flushed, iclass 28, count 0 2006.217.08:06:19.53#ibcon#about to write, iclass 28, count 0 2006.217.08:06:19.53#ibcon#wrote, iclass 28, count 0 2006.217.08:06:19.53#ibcon#about to read 3, iclass 28, count 0 2006.217.08:06:19.56#ibcon#read 3, iclass 28, count 0 2006.217.08:06:19.56#ibcon#about to read 4, iclass 28, count 0 2006.217.08:06:19.56#ibcon#read 4, iclass 28, count 0 2006.217.08:06:19.56#ibcon#about to read 5, iclass 28, count 0 2006.217.08:06:19.56#ibcon#read 5, iclass 28, count 0 2006.217.08:06:19.56#ibcon#about to read 6, iclass 28, count 0 2006.217.08:06:19.56#ibcon#read 6, iclass 28, count 0 2006.217.08:06:19.56#ibcon#end of sib2, iclass 28, count 0 2006.217.08:06:19.56#ibcon#*after write, iclass 28, count 0 2006.217.08:06:19.56#ibcon#*before return 0, iclass 28, count 0 2006.217.08:06:19.56#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.217.08:06:19.56#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.217.08:06:19.56#ibcon#about to clear, iclass 28 cls_cnt 0 2006.217.08:06:19.56#ibcon#cleared, iclass 28 cls_cnt 0 2006.217.08:06:19.56$vc4f8/valo=6,772.99 2006.217.08:06:19.56#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.217.08:06:19.56#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.217.08:06:19.56#ibcon#ireg 17 cls_cnt 0 2006.217.08:06:19.56#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.217.08:06:19.56#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.217.08:06:19.56#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.217.08:06:19.56#ibcon#enter wrdev, iclass 30, count 0 2006.217.08:06:19.56#ibcon#first serial, iclass 30, count 0 2006.217.08:06:19.56#ibcon#enter sib2, iclass 30, count 0 2006.217.08:06:19.56#ibcon#flushed, iclass 30, count 0 2006.217.08:06:19.56#ibcon#about to write, iclass 30, count 0 2006.217.08:06:19.56#ibcon#wrote, iclass 30, count 0 2006.217.08:06:19.56#ibcon#about to read 3, iclass 30, count 0 2006.217.08:06:19.58#ibcon#read 3, iclass 30, count 0 2006.217.08:06:19.58#ibcon#about to read 4, iclass 30, count 0 2006.217.08:06:19.58#ibcon#read 4, iclass 30, count 0 2006.217.08:06:19.58#ibcon#about to read 5, iclass 30, count 0 2006.217.08:06:19.58#ibcon#read 5, iclass 30, count 0 2006.217.08:06:19.58#ibcon#about to read 6, iclass 30, count 0 2006.217.08:06:19.58#ibcon#read 6, iclass 30, count 0 2006.217.08:06:19.58#ibcon#end of sib2, iclass 30, count 0 2006.217.08:06:19.58#ibcon#*mode == 0, iclass 30, count 0 2006.217.08:06:19.58#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.217.08:06:19.58#ibcon#[26=FRQ=06,772.99\r\n] 2006.217.08:06:19.58#ibcon#*before write, iclass 30, count 0 2006.217.08:06:19.58#ibcon#enter sib2, iclass 30, count 0 2006.217.08:06:19.58#ibcon#flushed, iclass 30, count 0 2006.217.08:06:19.58#ibcon#about to write, iclass 30, count 0 2006.217.08:06:19.58#ibcon#wrote, iclass 30, count 0 2006.217.08:06:19.58#ibcon#about to read 3, iclass 30, count 0 2006.217.08:06:19.62#ibcon#read 3, iclass 30, count 0 2006.217.08:06:19.62#ibcon#about to read 4, iclass 30, count 0 2006.217.08:06:19.62#ibcon#read 4, iclass 30, count 0 2006.217.08:06:19.62#ibcon#about to read 5, iclass 30, count 0 2006.217.08:06:19.62#ibcon#read 5, iclass 30, count 0 2006.217.08:06:19.62#ibcon#about to read 6, iclass 30, count 0 2006.217.08:06:19.62#ibcon#read 6, iclass 30, count 0 2006.217.08:06:19.62#ibcon#end of sib2, iclass 30, count 0 2006.217.08:06:19.62#ibcon#*after write, iclass 30, count 0 2006.217.08:06:19.62#ibcon#*before return 0, iclass 30, count 0 2006.217.08:06:19.62#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.217.08:06:19.62#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.217.08:06:19.62#ibcon#about to clear, iclass 30 cls_cnt 0 2006.217.08:06:19.62#ibcon#cleared, iclass 30 cls_cnt 0 2006.217.08:06:19.62$vc4f8/va=6,6 2006.217.08:06:19.62#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.217.08:06:19.62#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.217.08:06:19.62#ibcon#ireg 11 cls_cnt 2 2006.217.08:06:19.62#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.217.08:06:19.68#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.217.08:06:19.68#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.217.08:06:19.68#ibcon#enter wrdev, iclass 32, count 2 2006.217.08:06:19.68#ibcon#first serial, iclass 32, count 2 2006.217.08:06:19.68#ibcon#enter sib2, iclass 32, count 2 2006.217.08:06:19.68#ibcon#flushed, iclass 32, count 2 2006.217.08:06:19.68#ibcon#about to write, iclass 32, count 2 2006.217.08:06:19.68#ibcon#wrote, iclass 32, count 2 2006.217.08:06:19.68#ibcon#about to read 3, iclass 32, count 2 2006.217.08:06:19.70#ibcon#read 3, iclass 32, count 2 2006.217.08:06:19.70#ibcon#about to read 4, iclass 32, count 2 2006.217.08:06:19.70#ibcon#read 4, iclass 32, count 2 2006.217.08:06:19.70#ibcon#about to read 5, iclass 32, count 2 2006.217.08:06:19.70#ibcon#read 5, iclass 32, count 2 2006.217.08:06:19.70#ibcon#about to read 6, iclass 32, count 2 2006.217.08:06:19.70#ibcon#read 6, iclass 32, count 2 2006.217.08:06:19.70#ibcon#end of sib2, iclass 32, count 2 2006.217.08:06:19.70#ibcon#*mode == 0, iclass 32, count 2 2006.217.08:06:19.70#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.217.08:06:19.70#ibcon#[25=AT06-06\r\n] 2006.217.08:06:19.70#ibcon#*before write, iclass 32, count 2 2006.217.08:06:19.70#ibcon#enter sib2, iclass 32, count 2 2006.217.08:06:19.70#ibcon#flushed, iclass 32, count 2 2006.217.08:06:19.70#ibcon#about to write, iclass 32, count 2 2006.217.08:06:19.70#ibcon#wrote, iclass 32, count 2 2006.217.08:06:19.70#ibcon#about to read 3, iclass 32, count 2 2006.217.08:06:19.73#ibcon#read 3, iclass 32, count 2 2006.217.08:06:19.73#ibcon#about to read 4, iclass 32, count 2 2006.217.08:06:19.73#ibcon#read 4, iclass 32, count 2 2006.217.08:06:19.73#ibcon#about to read 5, iclass 32, count 2 2006.217.08:06:19.73#ibcon#read 5, iclass 32, count 2 2006.217.08:06:19.73#ibcon#about to read 6, iclass 32, count 2 2006.217.08:06:19.73#ibcon#read 6, iclass 32, count 2 2006.217.08:06:19.73#ibcon#end of sib2, iclass 32, count 2 2006.217.08:06:19.73#ibcon#*after write, iclass 32, count 2 2006.217.08:06:19.73#ibcon#*before return 0, iclass 32, count 2 2006.217.08:06:19.73#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.217.08:06:19.73#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.217.08:06:19.73#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.217.08:06:19.73#ibcon#ireg 7 cls_cnt 0 2006.217.08:06:19.73#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.217.08:06:19.85#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.217.08:06:19.85#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.217.08:06:19.85#ibcon#enter wrdev, iclass 32, count 0 2006.217.08:06:19.85#ibcon#first serial, iclass 32, count 0 2006.217.08:06:19.85#ibcon#enter sib2, iclass 32, count 0 2006.217.08:06:19.85#ibcon#flushed, iclass 32, count 0 2006.217.08:06:19.85#ibcon#about to write, iclass 32, count 0 2006.217.08:06:19.85#ibcon#wrote, iclass 32, count 0 2006.217.08:06:19.85#ibcon#about to read 3, iclass 32, count 0 2006.217.08:06:19.87#ibcon#read 3, iclass 32, count 0 2006.217.08:06:19.87#ibcon#about to read 4, iclass 32, count 0 2006.217.08:06:19.87#ibcon#read 4, iclass 32, count 0 2006.217.08:06:19.87#ibcon#about to read 5, iclass 32, count 0 2006.217.08:06:19.87#ibcon#read 5, iclass 32, count 0 2006.217.08:06:19.87#ibcon#about to read 6, iclass 32, count 0 2006.217.08:06:19.87#ibcon#read 6, iclass 32, count 0 2006.217.08:06:19.87#ibcon#end of sib2, iclass 32, count 0 2006.217.08:06:19.87#ibcon#*mode == 0, iclass 32, count 0 2006.217.08:06:19.87#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.217.08:06:19.87#ibcon#[25=USB\r\n] 2006.217.08:06:19.87#ibcon#*before write, iclass 32, count 0 2006.217.08:06:19.87#ibcon#enter sib2, iclass 32, count 0 2006.217.08:06:19.87#ibcon#flushed, iclass 32, count 0 2006.217.08:06:19.87#ibcon#about to write, iclass 32, count 0 2006.217.08:06:19.87#ibcon#wrote, iclass 32, count 0 2006.217.08:06:19.87#ibcon#about to read 3, iclass 32, count 0 2006.217.08:06:19.90#ibcon#read 3, iclass 32, count 0 2006.217.08:06:19.90#ibcon#about to read 4, iclass 32, count 0 2006.217.08:06:19.90#ibcon#read 4, iclass 32, count 0 2006.217.08:06:19.90#ibcon#about to read 5, iclass 32, count 0 2006.217.08:06:19.90#ibcon#read 5, iclass 32, count 0 2006.217.08:06:19.90#ibcon#about to read 6, iclass 32, count 0 2006.217.08:06:19.90#ibcon#read 6, iclass 32, count 0 2006.217.08:06:19.90#ibcon#end of sib2, iclass 32, count 0 2006.217.08:06:19.90#ibcon#*after write, iclass 32, count 0 2006.217.08:06:19.90#ibcon#*before return 0, iclass 32, count 0 2006.217.08:06:19.90#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.217.08:06:19.90#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.217.08:06:19.90#ibcon#about to clear, iclass 32 cls_cnt 0 2006.217.08:06:19.90#ibcon#cleared, iclass 32 cls_cnt 0 2006.217.08:06:19.90$vc4f8/valo=7,832.99 2006.217.08:06:19.90#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.217.08:06:19.90#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.217.08:06:19.90#ibcon#ireg 17 cls_cnt 0 2006.217.08:06:19.90#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.217.08:06:19.90#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.217.08:06:19.90#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.217.08:06:19.90#ibcon#enter wrdev, iclass 34, count 0 2006.217.08:06:19.90#ibcon#first serial, iclass 34, count 0 2006.217.08:06:19.90#ibcon#enter sib2, iclass 34, count 0 2006.217.08:06:19.90#ibcon#flushed, iclass 34, count 0 2006.217.08:06:19.90#ibcon#about to write, iclass 34, count 0 2006.217.08:06:19.90#ibcon#wrote, iclass 34, count 0 2006.217.08:06:19.90#ibcon#about to read 3, iclass 34, count 0 2006.217.08:06:19.92#ibcon#read 3, iclass 34, count 0 2006.217.08:06:19.92#ibcon#about to read 4, iclass 34, count 0 2006.217.08:06:19.92#ibcon#read 4, iclass 34, count 0 2006.217.08:06:19.92#ibcon#about to read 5, iclass 34, count 0 2006.217.08:06:19.92#ibcon#read 5, iclass 34, count 0 2006.217.08:06:19.92#ibcon#about to read 6, iclass 34, count 0 2006.217.08:06:19.92#ibcon#read 6, iclass 34, count 0 2006.217.08:06:19.92#ibcon#end of sib2, iclass 34, count 0 2006.217.08:06:19.92#ibcon#*mode == 0, iclass 34, count 0 2006.217.08:06:19.92#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.217.08:06:19.92#ibcon#[26=FRQ=07,832.99\r\n] 2006.217.08:06:19.92#ibcon#*before write, iclass 34, count 0 2006.217.08:06:19.92#ibcon#enter sib2, iclass 34, count 0 2006.217.08:06:19.92#ibcon#flushed, iclass 34, count 0 2006.217.08:06:19.92#ibcon#about to write, iclass 34, count 0 2006.217.08:06:19.92#ibcon#wrote, iclass 34, count 0 2006.217.08:06:19.92#ibcon#about to read 3, iclass 34, count 0 2006.217.08:06:19.96#ibcon#read 3, iclass 34, count 0 2006.217.08:06:19.96#ibcon#about to read 4, iclass 34, count 0 2006.217.08:06:19.96#ibcon#read 4, iclass 34, count 0 2006.217.08:06:19.96#ibcon#about to read 5, iclass 34, count 0 2006.217.08:06:19.96#ibcon#read 5, iclass 34, count 0 2006.217.08:06:19.96#ibcon#about to read 6, iclass 34, count 0 2006.217.08:06:19.96#ibcon#read 6, iclass 34, count 0 2006.217.08:06:19.96#ibcon#end of sib2, iclass 34, count 0 2006.217.08:06:19.96#ibcon#*after write, iclass 34, count 0 2006.217.08:06:19.96#ibcon#*before return 0, iclass 34, count 0 2006.217.08:06:19.96#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.217.08:06:19.96#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.217.08:06:19.96#ibcon#about to clear, iclass 34 cls_cnt 0 2006.217.08:06:19.96#ibcon#cleared, iclass 34 cls_cnt 0 2006.217.08:06:19.96$vc4f8/va=7,6 2006.217.08:06:19.96#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.217.08:06:19.96#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.217.08:06:19.96#ibcon#ireg 11 cls_cnt 2 2006.217.08:06:19.96#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.217.08:06:20.02#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.217.08:06:20.02#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.217.08:06:20.02#ibcon#enter wrdev, iclass 36, count 2 2006.217.08:06:20.02#ibcon#first serial, iclass 36, count 2 2006.217.08:06:20.02#ibcon#enter sib2, iclass 36, count 2 2006.217.08:06:20.02#ibcon#flushed, iclass 36, count 2 2006.217.08:06:20.02#ibcon#about to write, iclass 36, count 2 2006.217.08:06:20.02#ibcon#wrote, iclass 36, count 2 2006.217.08:06:20.02#ibcon#about to read 3, iclass 36, count 2 2006.217.08:06:20.04#ibcon#read 3, iclass 36, count 2 2006.217.08:06:20.04#ibcon#about to read 4, iclass 36, count 2 2006.217.08:06:20.04#ibcon#read 4, iclass 36, count 2 2006.217.08:06:20.04#ibcon#about to read 5, iclass 36, count 2 2006.217.08:06:20.04#ibcon#read 5, iclass 36, count 2 2006.217.08:06:20.04#ibcon#about to read 6, iclass 36, count 2 2006.217.08:06:20.04#ibcon#read 6, iclass 36, count 2 2006.217.08:06:20.04#ibcon#end of sib2, iclass 36, count 2 2006.217.08:06:20.04#ibcon#*mode == 0, iclass 36, count 2 2006.217.08:06:20.04#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.217.08:06:20.04#ibcon#[25=AT07-06\r\n] 2006.217.08:06:20.04#ibcon#*before write, iclass 36, count 2 2006.217.08:06:20.04#ibcon#enter sib2, iclass 36, count 2 2006.217.08:06:20.04#ibcon#flushed, iclass 36, count 2 2006.217.08:06:20.04#ibcon#about to write, iclass 36, count 2 2006.217.08:06:20.04#ibcon#wrote, iclass 36, count 2 2006.217.08:06:20.04#ibcon#about to read 3, iclass 36, count 2 2006.217.08:06:20.07#ibcon#read 3, iclass 36, count 2 2006.217.08:06:20.07#ibcon#about to read 4, iclass 36, count 2 2006.217.08:06:20.07#ibcon#read 4, iclass 36, count 2 2006.217.08:06:20.07#ibcon#about to read 5, iclass 36, count 2 2006.217.08:06:20.07#ibcon#read 5, iclass 36, count 2 2006.217.08:06:20.07#ibcon#about to read 6, iclass 36, count 2 2006.217.08:06:20.07#ibcon#read 6, iclass 36, count 2 2006.217.08:06:20.07#ibcon#end of sib2, iclass 36, count 2 2006.217.08:06:20.07#ibcon#*after write, iclass 36, count 2 2006.217.08:06:20.07#ibcon#*before return 0, iclass 36, count 2 2006.217.08:06:20.07#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.217.08:06:20.07#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.217.08:06:20.07#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.217.08:06:20.07#ibcon#ireg 7 cls_cnt 0 2006.217.08:06:20.07#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.217.08:06:20.19#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.217.08:06:20.19#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.217.08:06:20.19#ibcon#enter wrdev, iclass 36, count 0 2006.217.08:06:20.19#ibcon#first serial, iclass 36, count 0 2006.217.08:06:20.19#ibcon#enter sib2, iclass 36, count 0 2006.217.08:06:20.19#ibcon#flushed, iclass 36, count 0 2006.217.08:06:20.19#ibcon#about to write, iclass 36, count 0 2006.217.08:06:20.19#ibcon#wrote, iclass 36, count 0 2006.217.08:06:20.19#ibcon#about to read 3, iclass 36, count 0 2006.217.08:06:20.21#ibcon#read 3, iclass 36, count 0 2006.217.08:06:20.21#ibcon#about to read 4, iclass 36, count 0 2006.217.08:06:20.21#ibcon#read 4, iclass 36, count 0 2006.217.08:06:20.21#ibcon#about to read 5, iclass 36, count 0 2006.217.08:06:20.21#ibcon#read 5, iclass 36, count 0 2006.217.08:06:20.21#ibcon#about to read 6, iclass 36, count 0 2006.217.08:06:20.21#ibcon#read 6, iclass 36, count 0 2006.217.08:06:20.21#ibcon#end of sib2, iclass 36, count 0 2006.217.08:06:20.21#ibcon#*mode == 0, iclass 36, count 0 2006.217.08:06:20.21#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.217.08:06:20.21#ibcon#[25=USB\r\n] 2006.217.08:06:20.21#ibcon#*before write, iclass 36, count 0 2006.217.08:06:20.21#ibcon#enter sib2, iclass 36, count 0 2006.217.08:06:20.21#ibcon#flushed, iclass 36, count 0 2006.217.08:06:20.21#ibcon#about to write, iclass 36, count 0 2006.217.08:06:20.21#ibcon#wrote, iclass 36, count 0 2006.217.08:06:20.21#ibcon#about to read 3, iclass 36, count 0 2006.217.08:06:20.24#ibcon#read 3, iclass 36, count 0 2006.217.08:06:20.24#ibcon#about to read 4, iclass 36, count 0 2006.217.08:06:20.24#ibcon#read 4, iclass 36, count 0 2006.217.08:06:20.24#ibcon#about to read 5, iclass 36, count 0 2006.217.08:06:20.24#ibcon#read 5, iclass 36, count 0 2006.217.08:06:20.24#ibcon#about to read 6, iclass 36, count 0 2006.217.08:06:20.24#ibcon#read 6, iclass 36, count 0 2006.217.08:06:20.24#ibcon#end of sib2, iclass 36, count 0 2006.217.08:06:20.24#ibcon#*after write, iclass 36, count 0 2006.217.08:06:20.24#ibcon#*before return 0, iclass 36, count 0 2006.217.08:06:20.24#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.217.08:06:20.24#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.217.08:06:20.24#ibcon#about to clear, iclass 36 cls_cnt 0 2006.217.08:06:20.24#ibcon#cleared, iclass 36 cls_cnt 0 2006.217.08:06:20.24$vc4f8/valo=8,852.99 2006.217.08:06:20.24#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.217.08:06:20.24#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.217.08:06:20.24#ibcon#ireg 17 cls_cnt 0 2006.217.08:06:20.24#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.217.08:06:20.24#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.217.08:06:20.24#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.217.08:06:20.24#ibcon#enter wrdev, iclass 38, count 0 2006.217.08:06:20.24#ibcon#first serial, iclass 38, count 0 2006.217.08:06:20.24#ibcon#enter sib2, iclass 38, count 0 2006.217.08:06:20.24#ibcon#flushed, iclass 38, count 0 2006.217.08:06:20.24#ibcon#about to write, iclass 38, count 0 2006.217.08:06:20.24#ibcon#wrote, iclass 38, count 0 2006.217.08:06:20.24#ibcon#about to read 3, iclass 38, count 0 2006.217.08:06:20.26#ibcon#read 3, iclass 38, count 0 2006.217.08:06:20.26#ibcon#about to read 4, iclass 38, count 0 2006.217.08:06:20.26#ibcon#read 4, iclass 38, count 0 2006.217.08:06:20.26#ibcon#about to read 5, iclass 38, count 0 2006.217.08:06:20.26#ibcon#read 5, iclass 38, count 0 2006.217.08:06:20.26#ibcon#about to read 6, iclass 38, count 0 2006.217.08:06:20.26#ibcon#read 6, iclass 38, count 0 2006.217.08:06:20.26#ibcon#end of sib2, iclass 38, count 0 2006.217.08:06:20.26#ibcon#*mode == 0, iclass 38, count 0 2006.217.08:06:20.26#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.217.08:06:20.26#ibcon#[26=FRQ=08,852.99\r\n] 2006.217.08:06:20.26#ibcon#*before write, iclass 38, count 0 2006.217.08:06:20.26#ibcon#enter sib2, iclass 38, count 0 2006.217.08:06:20.26#ibcon#flushed, iclass 38, count 0 2006.217.08:06:20.26#ibcon#about to write, iclass 38, count 0 2006.217.08:06:20.26#ibcon#wrote, iclass 38, count 0 2006.217.08:06:20.26#ibcon#about to read 3, iclass 38, count 0 2006.217.08:06:20.30#ibcon#read 3, iclass 38, count 0 2006.217.08:06:20.30#ibcon#about to read 4, iclass 38, count 0 2006.217.08:06:20.30#ibcon#read 4, iclass 38, count 0 2006.217.08:06:20.30#ibcon#about to read 5, iclass 38, count 0 2006.217.08:06:20.30#ibcon#read 5, iclass 38, count 0 2006.217.08:06:20.30#ibcon#about to read 6, iclass 38, count 0 2006.217.08:06:20.30#ibcon#read 6, iclass 38, count 0 2006.217.08:06:20.30#ibcon#end of sib2, iclass 38, count 0 2006.217.08:06:20.30#ibcon#*after write, iclass 38, count 0 2006.217.08:06:20.30#ibcon#*before return 0, iclass 38, count 0 2006.217.08:06:20.30#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.217.08:06:20.30#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.217.08:06:20.30#ibcon#about to clear, iclass 38 cls_cnt 0 2006.217.08:06:20.30#ibcon#cleared, iclass 38 cls_cnt 0 2006.217.08:06:20.30$vc4f8/va=8,7 2006.217.08:06:20.30#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.217.08:06:20.30#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.217.08:06:20.30#ibcon#ireg 11 cls_cnt 2 2006.217.08:06:20.30#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.217.08:06:20.36#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.217.08:06:20.36#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.217.08:06:20.36#ibcon#enter wrdev, iclass 40, count 2 2006.217.08:06:20.36#ibcon#first serial, iclass 40, count 2 2006.217.08:06:20.36#ibcon#enter sib2, iclass 40, count 2 2006.217.08:06:20.36#ibcon#flushed, iclass 40, count 2 2006.217.08:06:20.36#ibcon#about to write, iclass 40, count 2 2006.217.08:06:20.36#ibcon#wrote, iclass 40, count 2 2006.217.08:06:20.36#ibcon#about to read 3, iclass 40, count 2 2006.217.08:06:20.38#ibcon#read 3, iclass 40, count 2 2006.217.08:06:20.38#ibcon#about to read 4, iclass 40, count 2 2006.217.08:06:20.38#ibcon#read 4, iclass 40, count 2 2006.217.08:06:20.38#ibcon#about to read 5, iclass 40, count 2 2006.217.08:06:20.38#ibcon#read 5, iclass 40, count 2 2006.217.08:06:20.38#ibcon#about to read 6, iclass 40, count 2 2006.217.08:06:20.38#ibcon#read 6, iclass 40, count 2 2006.217.08:06:20.38#ibcon#end of sib2, iclass 40, count 2 2006.217.08:06:20.38#ibcon#*mode == 0, iclass 40, count 2 2006.217.08:06:20.38#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.217.08:06:20.38#ibcon#[25=AT08-07\r\n] 2006.217.08:06:20.38#ibcon#*before write, iclass 40, count 2 2006.217.08:06:20.38#ibcon#enter sib2, iclass 40, count 2 2006.217.08:06:20.38#ibcon#flushed, iclass 40, count 2 2006.217.08:06:20.38#ibcon#about to write, iclass 40, count 2 2006.217.08:06:20.38#ibcon#wrote, iclass 40, count 2 2006.217.08:06:20.38#ibcon#about to read 3, iclass 40, count 2 2006.217.08:06:20.41#ibcon#read 3, iclass 40, count 2 2006.217.08:06:20.41#ibcon#about to read 4, iclass 40, count 2 2006.217.08:06:20.41#ibcon#read 4, iclass 40, count 2 2006.217.08:06:20.41#ibcon#about to read 5, iclass 40, count 2 2006.217.08:06:20.41#ibcon#read 5, iclass 40, count 2 2006.217.08:06:20.41#ibcon#about to read 6, iclass 40, count 2 2006.217.08:06:20.41#ibcon#read 6, iclass 40, count 2 2006.217.08:06:20.41#ibcon#end of sib2, iclass 40, count 2 2006.217.08:06:20.41#ibcon#*after write, iclass 40, count 2 2006.217.08:06:20.41#ibcon#*before return 0, iclass 40, count 2 2006.217.08:06:20.41#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.217.08:06:20.41#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.217.08:06:20.41#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.217.08:06:20.41#ibcon#ireg 7 cls_cnt 0 2006.217.08:06:20.41#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.217.08:06:20.53#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.217.08:06:20.53#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.217.08:06:20.53#ibcon#enter wrdev, iclass 40, count 0 2006.217.08:06:20.53#ibcon#first serial, iclass 40, count 0 2006.217.08:06:20.53#ibcon#enter sib2, iclass 40, count 0 2006.217.08:06:20.53#ibcon#flushed, iclass 40, count 0 2006.217.08:06:20.53#ibcon#about to write, iclass 40, count 0 2006.217.08:06:20.53#ibcon#wrote, iclass 40, count 0 2006.217.08:06:20.53#ibcon#about to read 3, iclass 40, count 0 2006.217.08:06:20.55#ibcon#read 3, iclass 40, count 0 2006.217.08:06:20.55#ibcon#about to read 4, iclass 40, count 0 2006.217.08:06:20.55#ibcon#read 4, iclass 40, count 0 2006.217.08:06:20.55#ibcon#about to read 5, iclass 40, count 0 2006.217.08:06:20.55#ibcon#read 5, iclass 40, count 0 2006.217.08:06:20.55#ibcon#about to read 6, iclass 40, count 0 2006.217.08:06:20.55#ibcon#read 6, iclass 40, count 0 2006.217.08:06:20.55#ibcon#end of sib2, iclass 40, count 0 2006.217.08:06:20.55#ibcon#*mode == 0, iclass 40, count 0 2006.217.08:06:20.55#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.217.08:06:20.55#ibcon#[25=USB\r\n] 2006.217.08:06:20.55#ibcon#*before write, iclass 40, count 0 2006.217.08:06:20.55#ibcon#enter sib2, iclass 40, count 0 2006.217.08:06:20.55#ibcon#flushed, iclass 40, count 0 2006.217.08:06:20.55#ibcon#about to write, iclass 40, count 0 2006.217.08:06:20.55#ibcon#wrote, iclass 40, count 0 2006.217.08:06:20.55#ibcon#about to read 3, iclass 40, count 0 2006.217.08:06:20.58#ibcon#read 3, iclass 40, count 0 2006.217.08:06:20.58#ibcon#about to read 4, iclass 40, count 0 2006.217.08:06:20.58#ibcon#read 4, iclass 40, count 0 2006.217.08:06:20.58#ibcon#about to read 5, iclass 40, count 0 2006.217.08:06:20.58#ibcon#read 5, iclass 40, count 0 2006.217.08:06:20.58#ibcon#about to read 6, iclass 40, count 0 2006.217.08:06:20.58#ibcon#read 6, iclass 40, count 0 2006.217.08:06:20.58#ibcon#end of sib2, iclass 40, count 0 2006.217.08:06:20.58#ibcon#*after write, iclass 40, count 0 2006.217.08:06:20.58#ibcon#*before return 0, iclass 40, count 0 2006.217.08:06:20.58#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.217.08:06:20.58#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.217.08:06:20.58#ibcon#about to clear, iclass 40 cls_cnt 0 2006.217.08:06:20.58#ibcon#cleared, iclass 40 cls_cnt 0 2006.217.08:06:20.58$vc4f8/vblo=1,632.99 2006.217.08:06:20.58#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.217.08:06:20.58#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.217.08:06:20.58#ibcon#ireg 17 cls_cnt 0 2006.217.08:06:20.58#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.217.08:06:20.58#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.217.08:06:20.58#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.217.08:06:20.58#ibcon#enter wrdev, iclass 4, count 0 2006.217.08:06:20.58#ibcon#first serial, iclass 4, count 0 2006.217.08:06:20.58#ibcon#enter sib2, iclass 4, count 0 2006.217.08:06:20.58#ibcon#flushed, iclass 4, count 0 2006.217.08:06:20.58#ibcon#about to write, iclass 4, count 0 2006.217.08:06:20.58#ibcon#wrote, iclass 4, count 0 2006.217.08:06:20.58#ibcon#about to read 3, iclass 4, count 0 2006.217.08:06:20.60#ibcon#read 3, iclass 4, count 0 2006.217.08:06:20.60#ibcon#about to read 4, iclass 4, count 0 2006.217.08:06:20.60#ibcon#read 4, iclass 4, count 0 2006.217.08:06:20.60#ibcon#about to read 5, iclass 4, count 0 2006.217.08:06:20.60#ibcon#read 5, iclass 4, count 0 2006.217.08:06:20.60#ibcon#about to read 6, iclass 4, count 0 2006.217.08:06:20.60#ibcon#read 6, iclass 4, count 0 2006.217.08:06:20.60#ibcon#end of sib2, iclass 4, count 0 2006.217.08:06:20.60#ibcon#*mode == 0, iclass 4, count 0 2006.217.08:06:20.60#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.217.08:06:20.60#ibcon#[28=FRQ=01,632.99\r\n] 2006.217.08:06:20.60#ibcon#*before write, iclass 4, count 0 2006.217.08:06:20.60#ibcon#enter sib2, iclass 4, count 0 2006.217.08:06:20.60#ibcon#flushed, iclass 4, count 0 2006.217.08:06:20.60#ibcon#about to write, iclass 4, count 0 2006.217.08:06:20.60#ibcon#wrote, iclass 4, count 0 2006.217.08:06:20.60#ibcon#about to read 3, iclass 4, count 0 2006.217.08:06:20.64#ibcon#read 3, iclass 4, count 0 2006.217.08:06:20.64#ibcon#about to read 4, iclass 4, count 0 2006.217.08:06:20.64#ibcon#read 4, iclass 4, count 0 2006.217.08:06:20.64#ibcon#about to read 5, iclass 4, count 0 2006.217.08:06:20.64#ibcon#read 5, iclass 4, count 0 2006.217.08:06:20.64#ibcon#about to read 6, iclass 4, count 0 2006.217.08:06:20.64#ibcon#read 6, iclass 4, count 0 2006.217.08:06:20.64#ibcon#end of sib2, iclass 4, count 0 2006.217.08:06:20.64#ibcon#*after write, iclass 4, count 0 2006.217.08:06:20.64#ibcon#*before return 0, iclass 4, count 0 2006.217.08:06:20.64#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.217.08:06:20.64#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.217.08:06:20.64#ibcon#about to clear, iclass 4 cls_cnt 0 2006.217.08:06:20.64#ibcon#cleared, iclass 4 cls_cnt 0 2006.217.08:06:20.64$vc4f8/vb=1,4 2006.217.08:06:20.64#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.217.08:06:20.64#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.217.08:06:20.64#ibcon#ireg 11 cls_cnt 2 2006.217.08:06:20.64#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.217.08:06:20.64#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.217.08:06:20.64#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.217.08:06:20.64#ibcon#enter wrdev, iclass 6, count 2 2006.217.08:06:20.64#ibcon#first serial, iclass 6, count 2 2006.217.08:06:20.64#ibcon#enter sib2, iclass 6, count 2 2006.217.08:06:20.64#ibcon#flushed, iclass 6, count 2 2006.217.08:06:20.64#ibcon#about to write, iclass 6, count 2 2006.217.08:06:20.64#ibcon#wrote, iclass 6, count 2 2006.217.08:06:20.64#ibcon#about to read 3, iclass 6, count 2 2006.217.08:06:20.66#ibcon#read 3, iclass 6, count 2 2006.217.08:06:20.66#ibcon#about to read 4, iclass 6, count 2 2006.217.08:06:20.66#ibcon#read 4, iclass 6, count 2 2006.217.08:06:20.66#ibcon#about to read 5, iclass 6, count 2 2006.217.08:06:20.66#ibcon#read 5, iclass 6, count 2 2006.217.08:06:20.66#ibcon#about to read 6, iclass 6, count 2 2006.217.08:06:20.66#ibcon#read 6, iclass 6, count 2 2006.217.08:06:20.66#ibcon#end of sib2, iclass 6, count 2 2006.217.08:06:20.66#ibcon#*mode == 0, iclass 6, count 2 2006.217.08:06:20.66#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.217.08:06:20.66#ibcon#[27=AT01-04\r\n] 2006.217.08:06:20.66#ibcon#*before write, iclass 6, count 2 2006.217.08:06:20.66#ibcon#enter sib2, iclass 6, count 2 2006.217.08:06:20.66#ibcon#flushed, iclass 6, count 2 2006.217.08:06:20.66#ibcon#about to write, iclass 6, count 2 2006.217.08:06:20.66#ibcon#wrote, iclass 6, count 2 2006.217.08:06:20.66#ibcon#about to read 3, iclass 6, count 2 2006.217.08:06:20.69#ibcon#read 3, iclass 6, count 2 2006.217.08:06:20.69#ibcon#about to read 4, iclass 6, count 2 2006.217.08:06:20.69#ibcon#read 4, iclass 6, count 2 2006.217.08:06:20.69#ibcon#about to read 5, iclass 6, count 2 2006.217.08:06:20.69#ibcon#read 5, iclass 6, count 2 2006.217.08:06:20.69#ibcon#about to read 6, iclass 6, count 2 2006.217.08:06:20.69#ibcon#read 6, iclass 6, count 2 2006.217.08:06:20.69#ibcon#end of sib2, iclass 6, count 2 2006.217.08:06:20.69#ibcon#*after write, iclass 6, count 2 2006.217.08:06:20.69#ibcon#*before return 0, iclass 6, count 2 2006.217.08:06:20.69#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.217.08:06:20.69#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.217.08:06:20.69#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.217.08:06:20.69#ibcon#ireg 7 cls_cnt 0 2006.217.08:06:20.69#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.217.08:06:20.81#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.217.08:06:20.81#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.217.08:06:20.81#ibcon#enter wrdev, iclass 6, count 0 2006.217.08:06:20.81#ibcon#first serial, iclass 6, count 0 2006.217.08:06:20.81#ibcon#enter sib2, iclass 6, count 0 2006.217.08:06:20.81#ibcon#flushed, iclass 6, count 0 2006.217.08:06:20.81#ibcon#about to write, iclass 6, count 0 2006.217.08:06:20.81#ibcon#wrote, iclass 6, count 0 2006.217.08:06:20.81#ibcon#about to read 3, iclass 6, count 0 2006.217.08:06:20.83#ibcon#read 3, iclass 6, count 0 2006.217.08:06:20.83#ibcon#about to read 4, iclass 6, count 0 2006.217.08:06:20.83#ibcon#read 4, iclass 6, count 0 2006.217.08:06:20.83#ibcon#about to read 5, iclass 6, count 0 2006.217.08:06:20.83#ibcon#read 5, iclass 6, count 0 2006.217.08:06:20.83#ibcon#about to read 6, iclass 6, count 0 2006.217.08:06:20.83#ibcon#read 6, iclass 6, count 0 2006.217.08:06:20.83#ibcon#end of sib2, iclass 6, count 0 2006.217.08:06:20.83#ibcon#*mode == 0, iclass 6, count 0 2006.217.08:06:20.83#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.217.08:06:20.83#ibcon#[27=USB\r\n] 2006.217.08:06:20.83#ibcon#*before write, iclass 6, count 0 2006.217.08:06:20.83#ibcon#enter sib2, iclass 6, count 0 2006.217.08:06:20.83#ibcon#flushed, iclass 6, count 0 2006.217.08:06:20.83#ibcon#about to write, iclass 6, count 0 2006.217.08:06:20.83#ibcon#wrote, iclass 6, count 0 2006.217.08:06:20.83#ibcon#about to read 3, iclass 6, count 0 2006.217.08:06:20.86#ibcon#read 3, iclass 6, count 0 2006.217.08:06:20.86#ibcon#about to read 4, iclass 6, count 0 2006.217.08:06:20.86#ibcon#read 4, iclass 6, count 0 2006.217.08:06:20.86#ibcon#about to read 5, iclass 6, count 0 2006.217.08:06:20.86#ibcon#read 5, iclass 6, count 0 2006.217.08:06:20.86#ibcon#about to read 6, iclass 6, count 0 2006.217.08:06:20.86#ibcon#read 6, iclass 6, count 0 2006.217.08:06:20.86#ibcon#end of sib2, iclass 6, count 0 2006.217.08:06:20.86#ibcon#*after write, iclass 6, count 0 2006.217.08:06:20.86#ibcon#*before return 0, iclass 6, count 0 2006.217.08:06:20.86#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.217.08:06:20.86#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.217.08:06:20.86#ibcon#about to clear, iclass 6 cls_cnt 0 2006.217.08:06:20.86#ibcon#cleared, iclass 6 cls_cnt 0 2006.217.08:06:20.86$vc4f8/vblo=2,640.99 2006.217.08:06:20.86#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.217.08:06:20.86#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.217.08:06:20.86#ibcon#ireg 17 cls_cnt 0 2006.217.08:06:20.86#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.217.08:06:20.86#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.217.08:06:20.86#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.217.08:06:20.86#ibcon#enter wrdev, iclass 10, count 0 2006.217.08:06:20.86#ibcon#first serial, iclass 10, count 0 2006.217.08:06:20.86#ibcon#enter sib2, iclass 10, count 0 2006.217.08:06:20.86#ibcon#flushed, iclass 10, count 0 2006.217.08:06:20.86#ibcon#about to write, iclass 10, count 0 2006.217.08:06:20.86#ibcon#wrote, iclass 10, count 0 2006.217.08:06:20.86#ibcon#about to read 3, iclass 10, count 0 2006.217.08:06:20.88#ibcon#read 3, iclass 10, count 0 2006.217.08:06:20.88#ibcon#about to read 4, iclass 10, count 0 2006.217.08:06:20.88#ibcon#read 4, iclass 10, count 0 2006.217.08:06:20.88#ibcon#about to read 5, iclass 10, count 0 2006.217.08:06:20.88#ibcon#read 5, iclass 10, count 0 2006.217.08:06:20.88#ibcon#about to read 6, iclass 10, count 0 2006.217.08:06:20.88#ibcon#read 6, iclass 10, count 0 2006.217.08:06:20.88#ibcon#end of sib2, iclass 10, count 0 2006.217.08:06:20.88#ibcon#*mode == 0, iclass 10, count 0 2006.217.08:06:20.88#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.217.08:06:20.88#ibcon#[28=FRQ=02,640.99\r\n] 2006.217.08:06:20.88#ibcon#*before write, iclass 10, count 0 2006.217.08:06:20.88#ibcon#enter sib2, iclass 10, count 0 2006.217.08:06:20.88#ibcon#flushed, iclass 10, count 0 2006.217.08:06:20.88#ibcon#about to write, iclass 10, count 0 2006.217.08:06:20.88#ibcon#wrote, iclass 10, count 0 2006.217.08:06:20.88#ibcon#about to read 3, iclass 10, count 0 2006.217.08:06:20.92#ibcon#read 3, iclass 10, count 0 2006.217.08:06:20.92#ibcon#about to read 4, iclass 10, count 0 2006.217.08:06:20.92#ibcon#read 4, iclass 10, count 0 2006.217.08:06:20.92#ibcon#about to read 5, iclass 10, count 0 2006.217.08:06:20.92#ibcon#read 5, iclass 10, count 0 2006.217.08:06:20.92#ibcon#about to read 6, iclass 10, count 0 2006.217.08:06:20.92#ibcon#read 6, iclass 10, count 0 2006.217.08:06:20.92#ibcon#end of sib2, iclass 10, count 0 2006.217.08:06:20.92#ibcon#*after write, iclass 10, count 0 2006.217.08:06:20.92#ibcon#*before return 0, iclass 10, count 0 2006.217.08:06:20.92#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.217.08:06:20.92#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.217.08:06:20.92#ibcon#about to clear, iclass 10 cls_cnt 0 2006.217.08:06:20.92#ibcon#cleared, iclass 10 cls_cnt 0 2006.217.08:06:20.92$vc4f8/vb=2,4 2006.217.08:06:20.92#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.217.08:06:20.92#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.217.08:06:20.92#ibcon#ireg 11 cls_cnt 2 2006.217.08:06:20.92#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.217.08:06:20.98#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.217.08:06:20.98#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.217.08:06:20.98#ibcon#enter wrdev, iclass 12, count 2 2006.217.08:06:20.98#ibcon#first serial, iclass 12, count 2 2006.217.08:06:20.98#ibcon#enter sib2, iclass 12, count 2 2006.217.08:06:20.98#ibcon#flushed, iclass 12, count 2 2006.217.08:06:20.98#ibcon#about to write, iclass 12, count 2 2006.217.08:06:20.98#ibcon#wrote, iclass 12, count 2 2006.217.08:06:20.98#ibcon#about to read 3, iclass 12, count 2 2006.217.08:06:21.00#ibcon#read 3, iclass 12, count 2 2006.217.08:06:21.00#ibcon#about to read 4, iclass 12, count 2 2006.217.08:06:21.00#ibcon#read 4, iclass 12, count 2 2006.217.08:06:21.00#ibcon#about to read 5, iclass 12, count 2 2006.217.08:06:21.00#ibcon#read 5, iclass 12, count 2 2006.217.08:06:21.00#ibcon#about to read 6, iclass 12, count 2 2006.217.08:06:21.00#ibcon#read 6, iclass 12, count 2 2006.217.08:06:21.00#ibcon#end of sib2, iclass 12, count 2 2006.217.08:06:21.00#ibcon#*mode == 0, iclass 12, count 2 2006.217.08:06:21.00#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.217.08:06:21.00#ibcon#[27=AT02-04\r\n] 2006.217.08:06:21.00#ibcon#*before write, iclass 12, count 2 2006.217.08:06:21.00#ibcon#enter sib2, iclass 12, count 2 2006.217.08:06:21.00#ibcon#flushed, iclass 12, count 2 2006.217.08:06:21.00#ibcon#about to write, iclass 12, count 2 2006.217.08:06:21.00#ibcon#wrote, iclass 12, count 2 2006.217.08:06:21.00#ibcon#about to read 3, iclass 12, count 2 2006.217.08:06:21.03#ibcon#read 3, iclass 12, count 2 2006.217.08:06:21.03#ibcon#about to read 4, iclass 12, count 2 2006.217.08:06:21.03#ibcon#read 4, iclass 12, count 2 2006.217.08:06:21.03#ibcon#about to read 5, iclass 12, count 2 2006.217.08:06:21.03#ibcon#read 5, iclass 12, count 2 2006.217.08:06:21.03#ibcon#about to read 6, iclass 12, count 2 2006.217.08:06:21.03#ibcon#read 6, iclass 12, count 2 2006.217.08:06:21.03#ibcon#end of sib2, iclass 12, count 2 2006.217.08:06:21.03#ibcon#*after write, iclass 12, count 2 2006.217.08:06:21.03#ibcon#*before return 0, iclass 12, count 2 2006.217.08:06:21.03#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.217.08:06:21.03#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.217.08:06:21.03#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.217.08:06:21.03#ibcon#ireg 7 cls_cnt 0 2006.217.08:06:21.03#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.217.08:06:21.15#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.217.08:06:21.15#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.217.08:06:21.15#ibcon#enter wrdev, iclass 12, count 0 2006.217.08:06:21.15#ibcon#first serial, iclass 12, count 0 2006.217.08:06:21.15#ibcon#enter sib2, iclass 12, count 0 2006.217.08:06:21.15#ibcon#flushed, iclass 12, count 0 2006.217.08:06:21.15#ibcon#about to write, iclass 12, count 0 2006.217.08:06:21.15#ibcon#wrote, iclass 12, count 0 2006.217.08:06:21.15#ibcon#about to read 3, iclass 12, count 0 2006.217.08:06:21.17#ibcon#read 3, iclass 12, count 0 2006.217.08:06:21.17#ibcon#about to read 4, iclass 12, count 0 2006.217.08:06:21.17#ibcon#read 4, iclass 12, count 0 2006.217.08:06:21.17#ibcon#about to read 5, iclass 12, count 0 2006.217.08:06:21.17#ibcon#read 5, iclass 12, count 0 2006.217.08:06:21.17#ibcon#about to read 6, iclass 12, count 0 2006.217.08:06:21.17#ibcon#read 6, iclass 12, count 0 2006.217.08:06:21.17#ibcon#end of sib2, iclass 12, count 0 2006.217.08:06:21.17#ibcon#*mode == 0, iclass 12, count 0 2006.217.08:06:21.17#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.217.08:06:21.17#ibcon#[27=USB\r\n] 2006.217.08:06:21.17#ibcon#*before write, iclass 12, count 0 2006.217.08:06:21.17#ibcon#enter sib2, iclass 12, count 0 2006.217.08:06:21.17#ibcon#flushed, iclass 12, count 0 2006.217.08:06:21.17#ibcon#about to write, iclass 12, count 0 2006.217.08:06:21.17#ibcon#wrote, iclass 12, count 0 2006.217.08:06:21.17#ibcon#about to read 3, iclass 12, count 0 2006.217.08:06:21.20#ibcon#read 3, iclass 12, count 0 2006.217.08:06:21.20#ibcon#about to read 4, iclass 12, count 0 2006.217.08:06:21.20#ibcon#read 4, iclass 12, count 0 2006.217.08:06:21.20#ibcon#about to read 5, iclass 12, count 0 2006.217.08:06:21.20#ibcon#read 5, iclass 12, count 0 2006.217.08:06:21.20#ibcon#about to read 6, iclass 12, count 0 2006.217.08:06:21.20#ibcon#read 6, iclass 12, count 0 2006.217.08:06:21.20#ibcon#end of sib2, iclass 12, count 0 2006.217.08:06:21.20#ibcon#*after write, iclass 12, count 0 2006.217.08:06:21.20#ibcon#*before return 0, iclass 12, count 0 2006.217.08:06:21.20#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.217.08:06:21.20#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.217.08:06:21.20#ibcon#about to clear, iclass 12 cls_cnt 0 2006.217.08:06:21.20#ibcon#cleared, iclass 12 cls_cnt 0 2006.217.08:06:21.20$vc4f8/vblo=3,656.99 2006.217.08:06:21.20#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.217.08:06:21.20#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.217.08:06:21.20#ibcon#ireg 17 cls_cnt 0 2006.217.08:06:21.20#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.217.08:06:21.20#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.217.08:06:21.20#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.217.08:06:21.20#ibcon#enter wrdev, iclass 14, count 0 2006.217.08:06:21.20#ibcon#first serial, iclass 14, count 0 2006.217.08:06:21.20#ibcon#enter sib2, iclass 14, count 0 2006.217.08:06:21.20#ibcon#flushed, iclass 14, count 0 2006.217.08:06:21.20#ibcon#about to write, iclass 14, count 0 2006.217.08:06:21.20#ibcon#wrote, iclass 14, count 0 2006.217.08:06:21.20#ibcon#about to read 3, iclass 14, count 0 2006.217.08:06:21.22#ibcon#read 3, iclass 14, count 0 2006.217.08:06:21.22#ibcon#about to read 4, iclass 14, count 0 2006.217.08:06:21.22#ibcon#read 4, iclass 14, count 0 2006.217.08:06:21.22#ibcon#about to read 5, iclass 14, count 0 2006.217.08:06:21.22#ibcon#read 5, iclass 14, count 0 2006.217.08:06:21.22#ibcon#about to read 6, iclass 14, count 0 2006.217.08:06:21.22#ibcon#read 6, iclass 14, count 0 2006.217.08:06:21.22#ibcon#end of sib2, iclass 14, count 0 2006.217.08:06:21.22#ibcon#*mode == 0, iclass 14, count 0 2006.217.08:06:21.22#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.217.08:06:21.22#ibcon#[28=FRQ=03,656.99\r\n] 2006.217.08:06:21.22#ibcon#*before write, iclass 14, count 0 2006.217.08:06:21.22#ibcon#enter sib2, iclass 14, count 0 2006.217.08:06:21.22#ibcon#flushed, iclass 14, count 0 2006.217.08:06:21.22#ibcon#about to write, iclass 14, count 0 2006.217.08:06:21.22#ibcon#wrote, iclass 14, count 0 2006.217.08:06:21.22#ibcon#about to read 3, iclass 14, count 0 2006.217.08:06:21.26#ibcon#read 3, iclass 14, count 0 2006.217.08:06:21.26#ibcon#about to read 4, iclass 14, count 0 2006.217.08:06:21.26#ibcon#read 4, iclass 14, count 0 2006.217.08:06:21.26#ibcon#about to read 5, iclass 14, count 0 2006.217.08:06:21.26#ibcon#read 5, iclass 14, count 0 2006.217.08:06:21.26#ibcon#about to read 6, iclass 14, count 0 2006.217.08:06:21.26#ibcon#read 6, iclass 14, count 0 2006.217.08:06:21.26#ibcon#end of sib2, iclass 14, count 0 2006.217.08:06:21.26#ibcon#*after write, iclass 14, count 0 2006.217.08:06:21.26#ibcon#*before return 0, iclass 14, count 0 2006.217.08:06:21.26#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.217.08:06:21.26#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.217.08:06:21.26#ibcon#about to clear, iclass 14 cls_cnt 0 2006.217.08:06:21.26#ibcon#cleared, iclass 14 cls_cnt 0 2006.217.08:06:21.26$vc4f8/vb=3,4 2006.217.08:06:21.26#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.217.08:06:21.26#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.217.08:06:21.26#ibcon#ireg 11 cls_cnt 2 2006.217.08:06:21.26#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.217.08:06:21.32#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.217.08:06:21.32#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.217.08:06:21.32#ibcon#enter wrdev, iclass 16, count 2 2006.217.08:06:21.32#ibcon#first serial, iclass 16, count 2 2006.217.08:06:21.32#ibcon#enter sib2, iclass 16, count 2 2006.217.08:06:21.32#ibcon#flushed, iclass 16, count 2 2006.217.08:06:21.32#ibcon#about to write, iclass 16, count 2 2006.217.08:06:21.32#ibcon#wrote, iclass 16, count 2 2006.217.08:06:21.32#ibcon#about to read 3, iclass 16, count 2 2006.217.08:06:21.34#ibcon#read 3, iclass 16, count 2 2006.217.08:06:21.34#ibcon#about to read 4, iclass 16, count 2 2006.217.08:06:21.34#ibcon#read 4, iclass 16, count 2 2006.217.08:06:21.34#ibcon#about to read 5, iclass 16, count 2 2006.217.08:06:21.34#ibcon#read 5, iclass 16, count 2 2006.217.08:06:21.34#ibcon#about to read 6, iclass 16, count 2 2006.217.08:06:21.34#ibcon#read 6, iclass 16, count 2 2006.217.08:06:21.34#ibcon#end of sib2, iclass 16, count 2 2006.217.08:06:21.34#ibcon#*mode == 0, iclass 16, count 2 2006.217.08:06:21.34#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.217.08:06:21.34#ibcon#[27=AT03-04\r\n] 2006.217.08:06:21.34#ibcon#*before write, iclass 16, count 2 2006.217.08:06:21.34#ibcon#enter sib2, iclass 16, count 2 2006.217.08:06:21.34#ibcon#flushed, iclass 16, count 2 2006.217.08:06:21.34#ibcon#about to write, iclass 16, count 2 2006.217.08:06:21.34#ibcon#wrote, iclass 16, count 2 2006.217.08:06:21.34#ibcon#about to read 3, iclass 16, count 2 2006.217.08:06:21.37#ibcon#read 3, iclass 16, count 2 2006.217.08:06:21.37#ibcon#about to read 4, iclass 16, count 2 2006.217.08:06:21.37#ibcon#read 4, iclass 16, count 2 2006.217.08:06:21.37#ibcon#about to read 5, iclass 16, count 2 2006.217.08:06:21.37#ibcon#read 5, iclass 16, count 2 2006.217.08:06:21.37#ibcon#about to read 6, iclass 16, count 2 2006.217.08:06:21.37#ibcon#read 6, iclass 16, count 2 2006.217.08:06:21.37#ibcon#end of sib2, iclass 16, count 2 2006.217.08:06:21.37#ibcon#*after write, iclass 16, count 2 2006.217.08:06:21.37#ibcon#*before return 0, iclass 16, count 2 2006.217.08:06:21.37#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.217.08:06:21.37#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.217.08:06:21.37#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.217.08:06:21.37#ibcon#ireg 7 cls_cnt 0 2006.217.08:06:21.37#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.217.08:06:21.49#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.217.08:06:21.49#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.217.08:06:21.49#ibcon#enter wrdev, iclass 16, count 0 2006.217.08:06:21.49#ibcon#first serial, iclass 16, count 0 2006.217.08:06:21.49#ibcon#enter sib2, iclass 16, count 0 2006.217.08:06:21.49#ibcon#flushed, iclass 16, count 0 2006.217.08:06:21.49#ibcon#about to write, iclass 16, count 0 2006.217.08:06:21.49#ibcon#wrote, iclass 16, count 0 2006.217.08:06:21.49#ibcon#about to read 3, iclass 16, count 0 2006.217.08:06:21.51#ibcon#read 3, iclass 16, count 0 2006.217.08:06:21.51#ibcon#about to read 4, iclass 16, count 0 2006.217.08:06:21.51#ibcon#read 4, iclass 16, count 0 2006.217.08:06:21.51#ibcon#about to read 5, iclass 16, count 0 2006.217.08:06:21.51#ibcon#read 5, iclass 16, count 0 2006.217.08:06:21.51#ibcon#about to read 6, iclass 16, count 0 2006.217.08:06:21.51#ibcon#read 6, iclass 16, count 0 2006.217.08:06:21.51#ibcon#end of sib2, iclass 16, count 0 2006.217.08:06:21.51#ibcon#*mode == 0, iclass 16, count 0 2006.217.08:06:21.51#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.217.08:06:21.51#ibcon#[27=USB\r\n] 2006.217.08:06:21.51#ibcon#*before write, iclass 16, count 0 2006.217.08:06:21.51#ibcon#enter sib2, iclass 16, count 0 2006.217.08:06:21.51#ibcon#flushed, iclass 16, count 0 2006.217.08:06:21.51#ibcon#about to write, iclass 16, count 0 2006.217.08:06:21.51#ibcon#wrote, iclass 16, count 0 2006.217.08:06:21.51#ibcon#about to read 3, iclass 16, count 0 2006.217.08:06:21.54#ibcon#read 3, iclass 16, count 0 2006.217.08:06:21.54#ibcon#about to read 4, iclass 16, count 0 2006.217.08:06:21.54#ibcon#read 4, iclass 16, count 0 2006.217.08:06:21.54#ibcon#about to read 5, iclass 16, count 0 2006.217.08:06:21.54#ibcon#read 5, iclass 16, count 0 2006.217.08:06:21.54#ibcon#about to read 6, iclass 16, count 0 2006.217.08:06:21.54#ibcon#read 6, iclass 16, count 0 2006.217.08:06:21.54#ibcon#end of sib2, iclass 16, count 0 2006.217.08:06:21.54#ibcon#*after write, iclass 16, count 0 2006.217.08:06:21.54#ibcon#*before return 0, iclass 16, count 0 2006.217.08:06:21.54#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.217.08:06:21.54#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.217.08:06:21.54#ibcon#about to clear, iclass 16 cls_cnt 0 2006.217.08:06:21.54#ibcon#cleared, iclass 16 cls_cnt 0 2006.217.08:06:21.54$vc4f8/vblo=4,712.99 2006.217.08:06:21.54#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.217.08:06:21.54#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.217.08:06:21.54#ibcon#ireg 17 cls_cnt 0 2006.217.08:06:21.54#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.217.08:06:21.54#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.217.08:06:21.54#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.217.08:06:21.54#ibcon#enter wrdev, iclass 18, count 0 2006.217.08:06:21.54#ibcon#first serial, iclass 18, count 0 2006.217.08:06:21.54#ibcon#enter sib2, iclass 18, count 0 2006.217.08:06:21.54#ibcon#flushed, iclass 18, count 0 2006.217.08:06:21.54#ibcon#about to write, iclass 18, count 0 2006.217.08:06:21.54#ibcon#wrote, iclass 18, count 0 2006.217.08:06:21.54#ibcon#about to read 3, iclass 18, count 0 2006.217.08:06:21.56#ibcon#read 3, iclass 18, count 0 2006.217.08:06:21.56#ibcon#about to read 4, iclass 18, count 0 2006.217.08:06:21.56#ibcon#read 4, iclass 18, count 0 2006.217.08:06:21.56#ibcon#about to read 5, iclass 18, count 0 2006.217.08:06:21.56#ibcon#read 5, iclass 18, count 0 2006.217.08:06:21.56#ibcon#about to read 6, iclass 18, count 0 2006.217.08:06:21.56#ibcon#read 6, iclass 18, count 0 2006.217.08:06:21.56#ibcon#end of sib2, iclass 18, count 0 2006.217.08:06:21.56#ibcon#*mode == 0, iclass 18, count 0 2006.217.08:06:21.56#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.217.08:06:21.56#ibcon#[28=FRQ=04,712.99\r\n] 2006.217.08:06:21.56#ibcon#*before write, iclass 18, count 0 2006.217.08:06:21.56#ibcon#enter sib2, iclass 18, count 0 2006.217.08:06:21.56#ibcon#flushed, iclass 18, count 0 2006.217.08:06:21.56#ibcon#about to write, iclass 18, count 0 2006.217.08:06:21.56#ibcon#wrote, iclass 18, count 0 2006.217.08:06:21.56#ibcon#about to read 3, iclass 18, count 0 2006.217.08:06:21.60#ibcon#read 3, iclass 18, count 0 2006.217.08:06:21.60#ibcon#about to read 4, iclass 18, count 0 2006.217.08:06:21.60#ibcon#read 4, iclass 18, count 0 2006.217.08:06:21.60#ibcon#about to read 5, iclass 18, count 0 2006.217.08:06:21.60#ibcon#read 5, iclass 18, count 0 2006.217.08:06:21.60#ibcon#about to read 6, iclass 18, count 0 2006.217.08:06:21.60#ibcon#read 6, iclass 18, count 0 2006.217.08:06:21.60#ibcon#end of sib2, iclass 18, count 0 2006.217.08:06:21.60#ibcon#*after write, iclass 18, count 0 2006.217.08:06:21.60#ibcon#*before return 0, iclass 18, count 0 2006.217.08:06:21.60#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.217.08:06:21.60#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.217.08:06:21.60#ibcon#about to clear, iclass 18 cls_cnt 0 2006.217.08:06:21.60#ibcon#cleared, iclass 18 cls_cnt 0 2006.217.08:06:21.60$vc4f8/vb=4,4 2006.217.08:06:21.60#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.217.08:06:21.60#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.217.08:06:21.60#ibcon#ireg 11 cls_cnt 2 2006.217.08:06:21.60#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.217.08:06:21.66#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.217.08:06:21.66#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.217.08:06:21.66#ibcon#enter wrdev, iclass 20, count 2 2006.217.08:06:21.66#ibcon#first serial, iclass 20, count 2 2006.217.08:06:21.66#ibcon#enter sib2, iclass 20, count 2 2006.217.08:06:21.66#ibcon#flushed, iclass 20, count 2 2006.217.08:06:21.66#ibcon#about to write, iclass 20, count 2 2006.217.08:06:21.66#ibcon#wrote, iclass 20, count 2 2006.217.08:06:21.66#ibcon#about to read 3, iclass 20, count 2 2006.217.08:06:21.68#ibcon#read 3, iclass 20, count 2 2006.217.08:06:21.68#ibcon#about to read 4, iclass 20, count 2 2006.217.08:06:21.68#ibcon#read 4, iclass 20, count 2 2006.217.08:06:21.68#ibcon#about to read 5, iclass 20, count 2 2006.217.08:06:21.68#ibcon#read 5, iclass 20, count 2 2006.217.08:06:21.68#ibcon#about to read 6, iclass 20, count 2 2006.217.08:06:21.68#ibcon#read 6, iclass 20, count 2 2006.217.08:06:21.68#ibcon#end of sib2, iclass 20, count 2 2006.217.08:06:21.68#ibcon#*mode == 0, iclass 20, count 2 2006.217.08:06:21.68#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.217.08:06:21.68#ibcon#[27=AT04-04\r\n] 2006.217.08:06:21.68#ibcon#*before write, iclass 20, count 2 2006.217.08:06:21.68#ibcon#enter sib2, iclass 20, count 2 2006.217.08:06:21.68#ibcon#flushed, iclass 20, count 2 2006.217.08:06:21.68#ibcon#about to write, iclass 20, count 2 2006.217.08:06:21.68#ibcon#wrote, iclass 20, count 2 2006.217.08:06:21.68#ibcon#about to read 3, iclass 20, count 2 2006.217.08:06:21.71#ibcon#read 3, iclass 20, count 2 2006.217.08:06:21.71#ibcon#about to read 4, iclass 20, count 2 2006.217.08:06:21.71#ibcon#read 4, iclass 20, count 2 2006.217.08:06:21.71#ibcon#about to read 5, iclass 20, count 2 2006.217.08:06:21.71#ibcon#read 5, iclass 20, count 2 2006.217.08:06:21.71#ibcon#about to read 6, iclass 20, count 2 2006.217.08:06:21.71#ibcon#read 6, iclass 20, count 2 2006.217.08:06:21.71#ibcon#end of sib2, iclass 20, count 2 2006.217.08:06:21.71#ibcon#*after write, iclass 20, count 2 2006.217.08:06:21.71#ibcon#*before return 0, iclass 20, count 2 2006.217.08:06:21.71#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.217.08:06:21.71#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.217.08:06:21.71#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.217.08:06:21.71#ibcon#ireg 7 cls_cnt 0 2006.217.08:06:21.71#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.217.08:06:21.83#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.217.08:06:21.83#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.217.08:06:21.83#ibcon#enter wrdev, iclass 20, count 0 2006.217.08:06:21.83#ibcon#first serial, iclass 20, count 0 2006.217.08:06:21.83#ibcon#enter sib2, iclass 20, count 0 2006.217.08:06:21.83#ibcon#flushed, iclass 20, count 0 2006.217.08:06:21.83#ibcon#about to write, iclass 20, count 0 2006.217.08:06:21.83#ibcon#wrote, iclass 20, count 0 2006.217.08:06:21.83#ibcon#about to read 3, iclass 20, count 0 2006.217.08:06:21.85#ibcon#read 3, iclass 20, count 0 2006.217.08:06:21.85#ibcon#about to read 4, iclass 20, count 0 2006.217.08:06:21.85#ibcon#read 4, iclass 20, count 0 2006.217.08:06:21.85#ibcon#about to read 5, iclass 20, count 0 2006.217.08:06:21.85#ibcon#read 5, iclass 20, count 0 2006.217.08:06:21.85#ibcon#about to read 6, iclass 20, count 0 2006.217.08:06:21.85#ibcon#read 6, iclass 20, count 0 2006.217.08:06:21.85#ibcon#end of sib2, iclass 20, count 0 2006.217.08:06:21.85#ibcon#*mode == 0, iclass 20, count 0 2006.217.08:06:21.85#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.217.08:06:21.85#ibcon#[27=USB\r\n] 2006.217.08:06:21.85#ibcon#*before write, iclass 20, count 0 2006.217.08:06:21.85#ibcon#enter sib2, iclass 20, count 0 2006.217.08:06:21.85#ibcon#flushed, iclass 20, count 0 2006.217.08:06:21.85#ibcon#about to write, iclass 20, count 0 2006.217.08:06:21.85#ibcon#wrote, iclass 20, count 0 2006.217.08:06:21.85#ibcon#about to read 3, iclass 20, count 0 2006.217.08:06:21.88#ibcon#read 3, iclass 20, count 0 2006.217.08:06:21.88#ibcon#about to read 4, iclass 20, count 0 2006.217.08:06:21.88#ibcon#read 4, iclass 20, count 0 2006.217.08:06:21.88#ibcon#about to read 5, iclass 20, count 0 2006.217.08:06:21.88#ibcon#read 5, iclass 20, count 0 2006.217.08:06:21.88#ibcon#about to read 6, iclass 20, count 0 2006.217.08:06:21.88#ibcon#read 6, iclass 20, count 0 2006.217.08:06:21.88#ibcon#end of sib2, iclass 20, count 0 2006.217.08:06:21.88#ibcon#*after write, iclass 20, count 0 2006.217.08:06:21.88#ibcon#*before return 0, iclass 20, count 0 2006.217.08:06:21.88#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.217.08:06:21.88#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.217.08:06:21.88#ibcon#about to clear, iclass 20 cls_cnt 0 2006.217.08:06:21.88#ibcon#cleared, iclass 20 cls_cnt 0 2006.217.08:06:21.88$vc4f8/vblo=5,744.99 2006.217.08:06:21.88#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.217.08:06:21.88#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.217.08:06:21.88#ibcon#ireg 17 cls_cnt 0 2006.217.08:06:21.88#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.217.08:06:21.88#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.217.08:06:21.88#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.217.08:06:21.88#ibcon#enter wrdev, iclass 22, count 0 2006.217.08:06:21.88#ibcon#first serial, iclass 22, count 0 2006.217.08:06:21.88#ibcon#enter sib2, iclass 22, count 0 2006.217.08:06:21.88#ibcon#flushed, iclass 22, count 0 2006.217.08:06:21.88#ibcon#about to write, iclass 22, count 0 2006.217.08:06:21.88#ibcon#wrote, iclass 22, count 0 2006.217.08:06:21.88#ibcon#about to read 3, iclass 22, count 0 2006.217.08:06:21.90#ibcon#read 3, iclass 22, count 0 2006.217.08:06:21.90#ibcon#about to read 4, iclass 22, count 0 2006.217.08:06:21.90#ibcon#read 4, iclass 22, count 0 2006.217.08:06:21.90#ibcon#about to read 5, iclass 22, count 0 2006.217.08:06:21.90#ibcon#read 5, iclass 22, count 0 2006.217.08:06:21.90#ibcon#about to read 6, iclass 22, count 0 2006.217.08:06:21.90#ibcon#read 6, iclass 22, count 0 2006.217.08:06:21.90#ibcon#end of sib2, iclass 22, count 0 2006.217.08:06:21.90#ibcon#*mode == 0, iclass 22, count 0 2006.217.08:06:21.90#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.217.08:06:21.90#ibcon#[28=FRQ=05,744.99\r\n] 2006.217.08:06:21.90#ibcon#*before write, iclass 22, count 0 2006.217.08:06:21.90#ibcon#enter sib2, iclass 22, count 0 2006.217.08:06:21.90#ibcon#flushed, iclass 22, count 0 2006.217.08:06:21.90#ibcon#about to write, iclass 22, count 0 2006.217.08:06:21.90#ibcon#wrote, iclass 22, count 0 2006.217.08:06:21.90#ibcon#about to read 3, iclass 22, count 0 2006.217.08:06:21.94#ibcon#read 3, iclass 22, count 0 2006.217.08:06:21.94#ibcon#about to read 4, iclass 22, count 0 2006.217.08:06:21.94#ibcon#read 4, iclass 22, count 0 2006.217.08:06:21.94#ibcon#about to read 5, iclass 22, count 0 2006.217.08:06:21.94#ibcon#read 5, iclass 22, count 0 2006.217.08:06:21.94#ibcon#about to read 6, iclass 22, count 0 2006.217.08:06:21.94#ibcon#read 6, iclass 22, count 0 2006.217.08:06:21.94#ibcon#end of sib2, iclass 22, count 0 2006.217.08:06:21.94#ibcon#*after write, iclass 22, count 0 2006.217.08:06:21.94#ibcon#*before return 0, iclass 22, count 0 2006.217.08:06:21.94#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.217.08:06:21.94#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.217.08:06:21.94#ibcon#about to clear, iclass 22 cls_cnt 0 2006.217.08:06:21.94#ibcon#cleared, iclass 22 cls_cnt 0 2006.217.08:06:21.94$vc4f8/vb=5,4 2006.217.08:06:21.94#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.217.08:06:21.94#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.217.08:06:21.94#ibcon#ireg 11 cls_cnt 2 2006.217.08:06:21.94#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.217.08:06:22.00#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.217.08:06:22.00#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.217.08:06:22.00#ibcon#enter wrdev, iclass 24, count 2 2006.217.08:06:22.00#ibcon#first serial, iclass 24, count 2 2006.217.08:06:22.00#ibcon#enter sib2, iclass 24, count 2 2006.217.08:06:22.00#ibcon#flushed, iclass 24, count 2 2006.217.08:06:22.00#ibcon#about to write, iclass 24, count 2 2006.217.08:06:22.00#ibcon#wrote, iclass 24, count 2 2006.217.08:06:22.00#ibcon#about to read 3, iclass 24, count 2 2006.217.08:06:22.02#ibcon#read 3, iclass 24, count 2 2006.217.08:06:22.02#ibcon#about to read 4, iclass 24, count 2 2006.217.08:06:22.02#ibcon#read 4, iclass 24, count 2 2006.217.08:06:22.02#ibcon#about to read 5, iclass 24, count 2 2006.217.08:06:22.02#ibcon#read 5, iclass 24, count 2 2006.217.08:06:22.02#ibcon#about to read 6, iclass 24, count 2 2006.217.08:06:22.02#ibcon#read 6, iclass 24, count 2 2006.217.08:06:22.02#ibcon#end of sib2, iclass 24, count 2 2006.217.08:06:22.02#ibcon#*mode == 0, iclass 24, count 2 2006.217.08:06:22.02#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.217.08:06:22.02#ibcon#[27=AT05-04\r\n] 2006.217.08:06:22.02#ibcon#*before write, iclass 24, count 2 2006.217.08:06:22.02#ibcon#enter sib2, iclass 24, count 2 2006.217.08:06:22.02#ibcon#flushed, iclass 24, count 2 2006.217.08:06:22.02#ibcon#about to write, iclass 24, count 2 2006.217.08:06:22.02#ibcon#wrote, iclass 24, count 2 2006.217.08:06:22.02#ibcon#about to read 3, iclass 24, count 2 2006.217.08:06:22.05#ibcon#read 3, iclass 24, count 2 2006.217.08:06:22.05#ibcon#about to read 4, iclass 24, count 2 2006.217.08:06:22.05#ibcon#read 4, iclass 24, count 2 2006.217.08:06:22.05#ibcon#about to read 5, iclass 24, count 2 2006.217.08:06:22.05#ibcon#read 5, iclass 24, count 2 2006.217.08:06:22.05#ibcon#about to read 6, iclass 24, count 2 2006.217.08:06:22.05#ibcon#read 6, iclass 24, count 2 2006.217.08:06:22.05#ibcon#end of sib2, iclass 24, count 2 2006.217.08:06:22.05#ibcon#*after write, iclass 24, count 2 2006.217.08:06:22.05#ibcon#*before return 0, iclass 24, count 2 2006.217.08:06:22.05#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.217.08:06:22.05#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.217.08:06:22.05#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.217.08:06:22.05#ibcon#ireg 7 cls_cnt 0 2006.217.08:06:22.05#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.217.08:06:22.17#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.217.08:06:22.17#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.217.08:06:22.17#ibcon#enter wrdev, iclass 24, count 0 2006.217.08:06:22.17#ibcon#first serial, iclass 24, count 0 2006.217.08:06:22.17#ibcon#enter sib2, iclass 24, count 0 2006.217.08:06:22.17#ibcon#flushed, iclass 24, count 0 2006.217.08:06:22.17#ibcon#about to write, iclass 24, count 0 2006.217.08:06:22.17#ibcon#wrote, iclass 24, count 0 2006.217.08:06:22.17#ibcon#about to read 3, iclass 24, count 0 2006.217.08:06:22.19#ibcon#read 3, iclass 24, count 0 2006.217.08:06:22.19#ibcon#about to read 4, iclass 24, count 0 2006.217.08:06:22.19#ibcon#read 4, iclass 24, count 0 2006.217.08:06:22.19#ibcon#about to read 5, iclass 24, count 0 2006.217.08:06:22.19#ibcon#read 5, iclass 24, count 0 2006.217.08:06:22.19#ibcon#about to read 6, iclass 24, count 0 2006.217.08:06:22.19#ibcon#read 6, iclass 24, count 0 2006.217.08:06:22.19#ibcon#end of sib2, iclass 24, count 0 2006.217.08:06:22.19#ibcon#*mode == 0, iclass 24, count 0 2006.217.08:06:22.19#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.217.08:06:22.19#ibcon#[27=USB\r\n] 2006.217.08:06:22.19#ibcon#*before write, iclass 24, count 0 2006.217.08:06:22.19#ibcon#enter sib2, iclass 24, count 0 2006.217.08:06:22.19#ibcon#flushed, iclass 24, count 0 2006.217.08:06:22.19#ibcon#about to write, iclass 24, count 0 2006.217.08:06:22.19#ibcon#wrote, iclass 24, count 0 2006.217.08:06:22.19#ibcon#about to read 3, iclass 24, count 0 2006.217.08:06:22.22#ibcon#read 3, iclass 24, count 0 2006.217.08:06:22.22#ibcon#about to read 4, iclass 24, count 0 2006.217.08:06:22.22#ibcon#read 4, iclass 24, count 0 2006.217.08:06:22.22#ibcon#about to read 5, iclass 24, count 0 2006.217.08:06:22.22#ibcon#read 5, iclass 24, count 0 2006.217.08:06:22.22#ibcon#about to read 6, iclass 24, count 0 2006.217.08:06:22.22#ibcon#read 6, iclass 24, count 0 2006.217.08:06:22.22#ibcon#end of sib2, iclass 24, count 0 2006.217.08:06:22.22#ibcon#*after write, iclass 24, count 0 2006.217.08:06:22.22#ibcon#*before return 0, iclass 24, count 0 2006.217.08:06:22.22#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.217.08:06:22.22#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.217.08:06:22.22#ibcon#about to clear, iclass 24 cls_cnt 0 2006.217.08:06:22.22#ibcon#cleared, iclass 24 cls_cnt 0 2006.217.08:06:22.22$vc4f8/vblo=6,752.99 2006.217.08:06:22.22#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.217.08:06:22.22#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.217.08:06:22.22#ibcon#ireg 17 cls_cnt 0 2006.217.08:06:22.22#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.217.08:06:22.22#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.217.08:06:22.22#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.217.08:06:22.22#ibcon#enter wrdev, iclass 26, count 0 2006.217.08:06:22.22#ibcon#first serial, iclass 26, count 0 2006.217.08:06:22.22#ibcon#enter sib2, iclass 26, count 0 2006.217.08:06:22.22#ibcon#flushed, iclass 26, count 0 2006.217.08:06:22.22#ibcon#about to write, iclass 26, count 0 2006.217.08:06:22.22#ibcon#wrote, iclass 26, count 0 2006.217.08:06:22.22#ibcon#about to read 3, iclass 26, count 0 2006.217.08:06:22.24#ibcon#read 3, iclass 26, count 0 2006.217.08:06:22.24#ibcon#about to read 4, iclass 26, count 0 2006.217.08:06:22.24#ibcon#read 4, iclass 26, count 0 2006.217.08:06:22.24#ibcon#about to read 5, iclass 26, count 0 2006.217.08:06:22.24#ibcon#read 5, iclass 26, count 0 2006.217.08:06:22.24#ibcon#about to read 6, iclass 26, count 0 2006.217.08:06:22.24#ibcon#read 6, iclass 26, count 0 2006.217.08:06:22.24#ibcon#end of sib2, iclass 26, count 0 2006.217.08:06:22.24#ibcon#*mode == 0, iclass 26, count 0 2006.217.08:06:22.24#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.217.08:06:22.24#ibcon#[28=FRQ=06,752.99\r\n] 2006.217.08:06:22.24#ibcon#*before write, iclass 26, count 0 2006.217.08:06:22.24#ibcon#enter sib2, iclass 26, count 0 2006.217.08:06:22.24#ibcon#flushed, iclass 26, count 0 2006.217.08:06:22.24#ibcon#about to write, iclass 26, count 0 2006.217.08:06:22.24#ibcon#wrote, iclass 26, count 0 2006.217.08:06:22.24#ibcon#about to read 3, iclass 26, count 0 2006.217.08:06:22.28#ibcon#read 3, iclass 26, count 0 2006.217.08:06:22.28#ibcon#about to read 4, iclass 26, count 0 2006.217.08:06:22.28#ibcon#read 4, iclass 26, count 0 2006.217.08:06:22.28#ibcon#about to read 5, iclass 26, count 0 2006.217.08:06:22.28#ibcon#read 5, iclass 26, count 0 2006.217.08:06:22.28#ibcon#about to read 6, iclass 26, count 0 2006.217.08:06:22.28#ibcon#read 6, iclass 26, count 0 2006.217.08:06:22.28#ibcon#end of sib2, iclass 26, count 0 2006.217.08:06:22.28#ibcon#*after write, iclass 26, count 0 2006.217.08:06:22.28#ibcon#*before return 0, iclass 26, count 0 2006.217.08:06:22.28#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.217.08:06:22.28#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.217.08:06:22.28#ibcon#about to clear, iclass 26 cls_cnt 0 2006.217.08:06:22.28#ibcon#cleared, iclass 26 cls_cnt 0 2006.217.08:06:22.28$vc4f8/vb=6,4 2006.217.08:06:22.28#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.217.08:06:22.28#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.217.08:06:22.28#ibcon#ireg 11 cls_cnt 2 2006.217.08:06:22.28#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.217.08:06:22.34#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.217.08:06:22.34#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.217.08:06:22.34#ibcon#enter wrdev, iclass 28, count 2 2006.217.08:06:22.34#ibcon#first serial, iclass 28, count 2 2006.217.08:06:22.34#ibcon#enter sib2, iclass 28, count 2 2006.217.08:06:22.34#ibcon#flushed, iclass 28, count 2 2006.217.08:06:22.34#ibcon#about to write, iclass 28, count 2 2006.217.08:06:22.34#ibcon#wrote, iclass 28, count 2 2006.217.08:06:22.34#ibcon#about to read 3, iclass 28, count 2 2006.217.08:06:22.36#ibcon#read 3, iclass 28, count 2 2006.217.08:06:22.36#ibcon#about to read 4, iclass 28, count 2 2006.217.08:06:22.36#ibcon#read 4, iclass 28, count 2 2006.217.08:06:22.36#ibcon#about to read 5, iclass 28, count 2 2006.217.08:06:22.36#ibcon#read 5, iclass 28, count 2 2006.217.08:06:22.36#ibcon#about to read 6, iclass 28, count 2 2006.217.08:06:22.36#ibcon#read 6, iclass 28, count 2 2006.217.08:06:22.36#ibcon#end of sib2, iclass 28, count 2 2006.217.08:06:22.36#ibcon#*mode == 0, iclass 28, count 2 2006.217.08:06:22.36#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.217.08:06:22.36#ibcon#[27=AT06-04\r\n] 2006.217.08:06:22.36#ibcon#*before write, iclass 28, count 2 2006.217.08:06:22.36#ibcon#enter sib2, iclass 28, count 2 2006.217.08:06:22.36#ibcon#flushed, iclass 28, count 2 2006.217.08:06:22.36#ibcon#about to write, iclass 28, count 2 2006.217.08:06:22.36#ibcon#wrote, iclass 28, count 2 2006.217.08:06:22.36#ibcon#about to read 3, iclass 28, count 2 2006.217.08:06:22.39#ibcon#read 3, iclass 28, count 2 2006.217.08:06:22.39#ibcon#about to read 4, iclass 28, count 2 2006.217.08:06:22.39#ibcon#read 4, iclass 28, count 2 2006.217.08:06:22.39#ibcon#about to read 5, iclass 28, count 2 2006.217.08:06:22.39#ibcon#read 5, iclass 28, count 2 2006.217.08:06:22.39#ibcon#about to read 6, iclass 28, count 2 2006.217.08:06:22.39#ibcon#read 6, iclass 28, count 2 2006.217.08:06:22.39#ibcon#end of sib2, iclass 28, count 2 2006.217.08:06:22.39#ibcon#*after write, iclass 28, count 2 2006.217.08:06:22.39#ibcon#*before return 0, iclass 28, count 2 2006.217.08:06:22.39#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.217.08:06:22.39#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.217.08:06:22.39#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.217.08:06:22.39#ibcon#ireg 7 cls_cnt 0 2006.217.08:06:22.39#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.217.08:06:22.51#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.217.08:06:22.51#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.217.08:06:22.51#ibcon#enter wrdev, iclass 28, count 0 2006.217.08:06:22.51#ibcon#first serial, iclass 28, count 0 2006.217.08:06:22.51#ibcon#enter sib2, iclass 28, count 0 2006.217.08:06:22.51#ibcon#flushed, iclass 28, count 0 2006.217.08:06:22.51#ibcon#about to write, iclass 28, count 0 2006.217.08:06:22.51#ibcon#wrote, iclass 28, count 0 2006.217.08:06:22.51#ibcon#about to read 3, iclass 28, count 0 2006.217.08:06:22.53#ibcon#read 3, iclass 28, count 0 2006.217.08:06:22.53#ibcon#about to read 4, iclass 28, count 0 2006.217.08:06:22.53#ibcon#read 4, iclass 28, count 0 2006.217.08:06:22.53#ibcon#about to read 5, iclass 28, count 0 2006.217.08:06:22.53#ibcon#read 5, iclass 28, count 0 2006.217.08:06:22.53#ibcon#about to read 6, iclass 28, count 0 2006.217.08:06:22.53#ibcon#read 6, iclass 28, count 0 2006.217.08:06:22.53#ibcon#end of sib2, iclass 28, count 0 2006.217.08:06:22.53#ibcon#*mode == 0, iclass 28, count 0 2006.217.08:06:22.53#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.217.08:06:22.53#ibcon#[27=USB\r\n] 2006.217.08:06:22.53#ibcon#*before write, iclass 28, count 0 2006.217.08:06:22.53#ibcon#enter sib2, iclass 28, count 0 2006.217.08:06:22.53#ibcon#flushed, iclass 28, count 0 2006.217.08:06:22.53#ibcon#about to write, iclass 28, count 0 2006.217.08:06:22.53#ibcon#wrote, iclass 28, count 0 2006.217.08:06:22.53#ibcon#about to read 3, iclass 28, count 0 2006.217.08:06:22.56#ibcon#read 3, iclass 28, count 0 2006.217.08:06:22.56#ibcon#about to read 4, iclass 28, count 0 2006.217.08:06:22.56#ibcon#read 4, iclass 28, count 0 2006.217.08:06:22.56#ibcon#about to read 5, iclass 28, count 0 2006.217.08:06:22.56#ibcon#read 5, iclass 28, count 0 2006.217.08:06:22.56#ibcon#about to read 6, iclass 28, count 0 2006.217.08:06:22.56#ibcon#read 6, iclass 28, count 0 2006.217.08:06:22.56#ibcon#end of sib2, iclass 28, count 0 2006.217.08:06:22.56#ibcon#*after write, iclass 28, count 0 2006.217.08:06:22.56#ibcon#*before return 0, iclass 28, count 0 2006.217.08:06:22.56#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.217.08:06:22.56#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.217.08:06:22.56#ibcon#about to clear, iclass 28 cls_cnt 0 2006.217.08:06:22.56#ibcon#cleared, iclass 28 cls_cnt 0 2006.217.08:06:22.56$vc4f8/vabw=wide 2006.217.08:06:22.56#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.217.08:06:22.56#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.217.08:06:22.56#ibcon#ireg 8 cls_cnt 0 2006.217.08:06:22.56#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.217.08:06:22.56#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.217.08:06:22.56#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.217.08:06:22.56#ibcon#enter wrdev, iclass 30, count 0 2006.217.08:06:22.56#ibcon#first serial, iclass 30, count 0 2006.217.08:06:22.56#ibcon#enter sib2, iclass 30, count 0 2006.217.08:06:22.56#ibcon#flushed, iclass 30, count 0 2006.217.08:06:22.56#ibcon#about to write, iclass 30, count 0 2006.217.08:06:22.56#ibcon#wrote, iclass 30, count 0 2006.217.08:06:22.56#ibcon#about to read 3, iclass 30, count 0 2006.217.08:06:22.58#ibcon#read 3, iclass 30, count 0 2006.217.08:06:22.58#ibcon#about to read 4, iclass 30, count 0 2006.217.08:06:22.58#ibcon#read 4, iclass 30, count 0 2006.217.08:06:22.58#ibcon#about to read 5, iclass 30, count 0 2006.217.08:06:22.58#ibcon#read 5, iclass 30, count 0 2006.217.08:06:22.58#ibcon#about to read 6, iclass 30, count 0 2006.217.08:06:22.58#ibcon#read 6, iclass 30, count 0 2006.217.08:06:22.58#ibcon#end of sib2, iclass 30, count 0 2006.217.08:06:22.58#ibcon#*mode == 0, iclass 30, count 0 2006.217.08:06:22.58#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.217.08:06:22.58#ibcon#[25=BW32\r\n] 2006.217.08:06:22.58#ibcon#*before write, iclass 30, count 0 2006.217.08:06:22.58#ibcon#enter sib2, iclass 30, count 0 2006.217.08:06:22.58#ibcon#flushed, iclass 30, count 0 2006.217.08:06:22.58#ibcon#about to write, iclass 30, count 0 2006.217.08:06:22.58#ibcon#wrote, iclass 30, count 0 2006.217.08:06:22.58#ibcon#about to read 3, iclass 30, count 0 2006.217.08:06:22.61#ibcon#read 3, iclass 30, count 0 2006.217.08:06:22.61#ibcon#about to read 4, iclass 30, count 0 2006.217.08:06:22.61#ibcon#read 4, iclass 30, count 0 2006.217.08:06:22.61#ibcon#about to read 5, iclass 30, count 0 2006.217.08:06:22.61#ibcon#read 5, iclass 30, count 0 2006.217.08:06:22.61#ibcon#about to read 6, iclass 30, count 0 2006.217.08:06:22.61#ibcon#read 6, iclass 30, count 0 2006.217.08:06:22.61#ibcon#end of sib2, iclass 30, count 0 2006.217.08:06:22.61#ibcon#*after write, iclass 30, count 0 2006.217.08:06:22.61#ibcon#*before return 0, iclass 30, count 0 2006.217.08:06:22.61#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.217.08:06:22.61#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.217.08:06:22.61#ibcon#about to clear, iclass 30 cls_cnt 0 2006.217.08:06:22.61#ibcon#cleared, iclass 30 cls_cnt 0 2006.217.08:06:22.61$vc4f8/vbbw=wide 2006.217.08:06:22.61#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.217.08:06:22.61#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.217.08:06:22.61#ibcon#ireg 8 cls_cnt 0 2006.217.08:06:22.61#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.217.08:06:22.68#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.217.08:06:22.68#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.217.08:06:22.68#ibcon#enter wrdev, iclass 32, count 0 2006.217.08:06:22.68#ibcon#first serial, iclass 32, count 0 2006.217.08:06:22.68#ibcon#enter sib2, iclass 32, count 0 2006.217.08:06:22.68#ibcon#flushed, iclass 32, count 0 2006.217.08:06:22.68#ibcon#about to write, iclass 32, count 0 2006.217.08:06:22.68#ibcon#wrote, iclass 32, count 0 2006.217.08:06:22.68#ibcon#about to read 3, iclass 32, count 0 2006.217.08:06:22.70#ibcon#read 3, iclass 32, count 0 2006.217.08:06:22.70#ibcon#about to read 4, iclass 32, count 0 2006.217.08:06:22.70#ibcon#read 4, iclass 32, count 0 2006.217.08:06:22.70#ibcon#about to read 5, iclass 32, count 0 2006.217.08:06:22.70#ibcon#read 5, iclass 32, count 0 2006.217.08:06:22.70#ibcon#about to read 6, iclass 32, count 0 2006.217.08:06:22.70#ibcon#read 6, iclass 32, count 0 2006.217.08:06:22.70#ibcon#end of sib2, iclass 32, count 0 2006.217.08:06:22.70#ibcon#*mode == 0, iclass 32, count 0 2006.217.08:06:22.70#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.217.08:06:22.70#ibcon#[27=BW32\r\n] 2006.217.08:06:22.70#ibcon#*before write, iclass 32, count 0 2006.217.08:06:22.70#ibcon#enter sib2, iclass 32, count 0 2006.217.08:06:22.70#ibcon#flushed, iclass 32, count 0 2006.217.08:06:22.70#ibcon#about to write, iclass 32, count 0 2006.217.08:06:22.70#ibcon#wrote, iclass 32, count 0 2006.217.08:06:22.70#ibcon#about to read 3, iclass 32, count 0 2006.217.08:06:22.73#ibcon#read 3, iclass 32, count 0 2006.217.08:06:22.73#ibcon#about to read 4, iclass 32, count 0 2006.217.08:06:22.73#ibcon#read 4, iclass 32, count 0 2006.217.08:06:22.73#ibcon#about to read 5, iclass 32, count 0 2006.217.08:06:22.73#ibcon#read 5, iclass 32, count 0 2006.217.08:06:22.73#ibcon#about to read 6, iclass 32, count 0 2006.217.08:06:22.73#ibcon#read 6, iclass 32, count 0 2006.217.08:06:22.73#ibcon#end of sib2, iclass 32, count 0 2006.217.08:06:22.73#ibcon#*after write, iclass 32, count 0 2006.217.08:06:22.73#ibcon#*before return 0, iclass 32, count 0 2006.217.08:06:22.73#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.217.08:06:22.73#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.217.08:06:22.73#ibcon#about to clear, iclass 32 cls_cnt 0 2006.217.08:06:22.73#ibcon#cleared, iclass 32 cls_cnt 0 2006.217.08:06:22.73$4f8m12a/ifd4f 2006.217.08:06:22.73$ifd4f/lo= 2006.217.08:06:22.73$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.217.08:06:22.73$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.217.08:06:22.73$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.217.08:06:22.73$ifd4f/patch= 2006.217.08:06:22.73$ifd4f/patch=lo1,a1,a2,a3,a4 2006.217.08:06:22.73$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.217.08:06:22.73$ifd4f/patch=lo3,a5,a6,a7,a8 2006.217.08:06:22.73$4f8m12a/"form=m,16.000,1:2 2006.217.08:06:22.73$4f8m12a/"tpicd 2006.217.08:06:22.73$4f8m12a/echo=off 2006.217.08:06:22.73$4f8m12a/xlog=off 2006.217.08:06:22.73:!2006.217.08:07:10 2006.217.08:06:48.13#trakl#Source acquired 2006.217.08:06:49.13#flagr#flagr/antenna,acquired 2006.217.08:07:10.00:preob 2006.217.08:07:11.13/onsource/TRACKING 2006.217.08:07:11.13:!2006.217.08:07:20 2006.217.08:07:20.00:data_valid=on 2006.217.08:07:20.00:midob 2006.217.08:07:20.13/onsource/TRACKING 2006.217.08:07:20.13/wx/30.75,1008.6,65 2006.217.08:07:20.22/cable/+6.3878E-03 2006.217.08:07:21.31/va/01,05,usb,yes,31,33 2006.217.08:07:21.31/va/02,04,usb,yes,29,30 2006.217.08:07:21.31/va/03,04,usb,yes,27,27 2006.217.08:07:21.31/va/04,04,usb,yes,30,33 2006.217.08:07:21.31/va/05,07,usb,yes,32,34 2006.217.08:07:21.31/va/06,06,usb,yes,31,31 2006.217.08:07:21.31/va/07,06,usb,yes,32,32 2006.217.08:07:21.31/va/08,07,usb,yes,30,30 2006.217.08:07:21.54/valo/01,532.99,yes,locked 2006.217.08:07:21.54/valo/02,572.99,yes,locked 2006.217.08:07:21.54/valo/03,672.99,yes,locked 2006.217.08:07:21.54/valo/04,832.99,yes,locked 2006.217.08:07:21.54/valo/05,652.99,yes,locked 2006.217.08:07:21.54/valo/06,772.99,yes,locked 2006.217.08:07:21.54/valo/07,832.99,yes,locked 2006.217.08:07:21.54/valo/08,852.99,yes,locked 2006.217.08:07:22.63/vb/01,04,usb,yes,30,29 2006.217.08:07:22.63/vb/02,04,usb,yes,32,33 2006.217.08:07:22.63/vb/03,04,usb,yes,28,32 2006.217.08:07:22.63/vb/04,04,usb,yes,29,29 2006.217.08:07:22.63/vb/05,04,usb,yes,27,31 2006.217.08:07:22.63/vb/06,04,usb,yes,28,31 2006.217.08:07:22.63/vb/07,04,usb,yes,30,30 2006.217.08:07:22.63/vb/08,04,usb,yes,28,31 2006.217.08:07:22.87/vblo/01,632.99,yes,locked 2006.217.08:07:22.87/vblo/02,640.99,yes,locked 2006.217.08:07:22.87/vblo/03,656.99,yes,locked 2006.217.08:07:22.87/vblo/04,712.99,yes,locked 2006.217.08:07:22.87/vblo/05,744.99,yes,locked 2006.217.08:07:22.87/vblo/06,752.99,yes,locked 2006.217.08:07:22.87/vblo/07,734.99,yes,locked 2006.217.08:07:22.87/vblo/08,744.99,yes,locked 2006.217.08:07:23.02/vabw/8 2006.217.08:07:23.17/vbbw/8 2006.217.08:07:23.26/xfe/off,on,15.0 2006.217.08:07:23.65/ifatt/23,28,28,28 2006.217.08:07:24.07/fmout-gps/S +4.37E-07 2006.217.08:07:24.11:!2006.217.08:08:20 2006.217.08:08:20.00:data_valid=off 2006.217.08:08:20.00:postob 2006.217.08:08:20.07/cable/+6.3863E-03 2006.217.08:08:20.07/wx/30.74,1008.6,64 2006.217.08:08:21.07/fmout-gps/S +4.40E-07 2006.217.08:08:21.07:scan_name=217-0809,k06217,60 2006.217.08:08:21.07:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.217.08:08:21.14#flagr#flagr/antenna,new-source 2006.217.08:08:22.13:checkk5 2006.217.08:08:22.50/chk_autoobs//k5ts1/ autoobs is running! 2006.217.08:08:22.86/chk_autoobs//k5ts2/ autoobs is running! 2006.217.08:08:23.24/chk_autoobs//k5ts3/ autoobs is running! 2006.217.08:08:23.61/chk_autoobs//k5ts4/ autoobs is running! 2006.217.08:08:23.97/chk_obsdata//k5ts1/T2170807??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.08:08:24.34/chk_obsdata//k5ts2/T2170807??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.08:08:24.71/chk_obsdata//k5ts3/T2170807??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.08:08:25.07/chk_obsdata//k5ts4/T2170807??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.08:08:25.78/k5log//k5ts1_log_newline 2006.217.08:08:26.48/k5log//k5ts2_log_newline 2006.217.08:08:27.16/k5log//k5ts3_log_newline 2006.217.08:08:27.85/k5log//k5ts4_log_newline 2006.217.08:08:27.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.217.08:08:27.88:4f8m12a=2 2006.217.08:08:27.88$4f8m12a/echo=on 2006.217.08:08:27.88$4f8m12a/pcalon 2006.217.08:08:27.88$pcalon/"no phase cal control is implemented here 2006.217.08:08:27.88$4f8m12a/"tpicd=stop 2006.217.08:08:27.88$4f8m12a/vc4f8 2006.217.08:08:27.88$vc4f8/valo=1,532.99 2006.217.08:08:27.89#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.217.08:08:27.89#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.217.08:08:27.89#ibcon#ireg 17 cls_cnt 0 2006.217.08:08:27.89#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.217.08:08:27.89#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.217.08:08:27.89#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.217.08:08:27.89#ibcon#enter wrdev, iclass 11, count 0 2006.217.08:08:27.89#ibcon#first serial, iclass 11, count 0 2006.217.08:08:27.89#ibcon#enter sib2, iclass 11, count 0 2006.217.08:08:27.89#ibcon#flushed, iclass 11, count 0 2006.217.08:08:27.89#ibcon#about to write, iclass 11, count 0 2006.217.08:08:27.89#ibcon#wrote, iclass 11, count 0 2006.217.08:08:27.89#ibcon#about to read 3, iclass 11, count 0 2006.217.08:08:27.92#ibcon#read 3, iclass 11, count 0 2006.217.08:08:27.92#ibcon#about to read 4, iclass 11, count 0 2006.217.08:08:27.92#ibcon#read 4, iclass 11, count 0 2006.217.08:08:27.92#ibcon#about to read 5, iclass 11, count 0 2006.217.08:08:27.92#ibcon#read 5, iclass 11, count 0 2006.217.08:08:27.92#ibcon#about to read 6, iclass 11, count 0 2006.217.08:08:27.92#ibcon#read 6, iclass 11, count 0 2006.217.08:08:27.92#ibcon#end of sib2, iclass 11, count 0 2006.217.08:08:27.92#ibcon#*mode == 0, iclass 11, count 0 2006.217.08:08:27.92#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.217.08:08:27.92#ibcon#[26=FRQ=01,532.99\r\n] 2006.217.08:08:27.92#ibcon#*before write, iclass 11, count 0 2006.217.08:08:27.92#ibcon#enter sib2, iclass 11, count 0 2006.217.08:08:27.92#ibcon#flushed, iclass 11, count 0 2006.217.08:08:27.92#ibcon#about to write, iclass 11, count 0 2006.217.08:08:27.92#ibcon#wrote, iclass 11, count 0 2006.217.08:08:27.92#ibcon#about to read 3, iclass 11, count 0 2006.217.08:08:27.97#ibcon#read 3, iclass 11, count 0 2006.217.08:08:27.97#ibcon#about to read 4, iclass 11, count 0 2006.217.08:08:27.97#ibcon#read 4, iclass 11, count 0 2006.217.08:08:27.97#ibcon#about to read 5, iclass 11, count 0 2006.217.08:08:27.97#ibcon#read 5, iclass 11, count 0 2006.217.08:08:27.97#ibcon#about to read 6, iclass 11, count 0 2006.217.08:08:27.97#ibcon#read 6, iclass 11, count 0 2006.217.08:08:27.97#ibcon#end of sib2, iclass 11, count 0 2006.217.08:08:27.97#ibcon#*after write, iclass 11, count 0 2006.217.08:08:27.97#ibcon#*before return 0, iclass 11, count 0 2006.217.08:08:27.97#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.217.08:08:27.97#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.217.08:08:27.97#ibcon#about to clear, iclass 11 cls_cnt 0 2006.217.08:08:27.97#ibcon#cleared, iclass 11 cls_cnt 0 2006.217.08:08:27.97$vc4f8/va=1,5 2006.217.08:08:27.97#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.217.08:08:27.97#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.217.08:08:27.97#ibcon#ireg 11 cls_cnt 2 2006.217.08:08:27.97#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.217.08:08:27.97#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.217.08:08:27.97#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.217.08:08:27.97#ibcon#enter wrdev, iclass 13, count 2 2006.217.08:08:27.97#ibcon#first serial, iclass 13, count 2 2006.217.08:08:27.97#ibcon#enter sib2, iclass 13, count 2 2006.217.08:08:27.97#ibcon#flushed, iclass 13, count 2 2006.217.08:08:27.97#ibcon#about to write, iclass 13, count 2 2006.217.08:08:27.97#ibcon#wrote, iclass 13, count 2 2006.217.08:08:27.97#ibcon#about to read 3, iclass 13, count 2 2006.217.08:08:27.99#ibcon#read 3, iclass 13, count 2 2006.217.08:08:27.99#ibcon#about to read 4, iclass 13, count 2 2006.217.08:08:27.99#ibcon#read 4, iclass 13, count 2 2006.217.08:08:27.99#ibcon#about to read 5, iclass 13, count 2 2006.217.08:08:27.99#ibcon#read 5, iclass 13, count 2 2006.217.08:08:27.99#ibcon#about to read 6, iclass 13, count 2 2006.217.08:08:27.99#ibcon#read 6, iclass 13, count 2 2006.217.08:08:27.99#ibcon#end of sib2, iclass 13, count 2 2006.217.08:08:27.99#ibcon#*mode == 0, iclass 13, count 2 2006.217.08:08:27.99#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.217.08:08:27.99#ibcon#[25=AT01-05\r\n] 2006.217.08:08:27.99#ibcon#*before write, iclass 13, count 2 2006.217.08:08:27.99#ibcon#enter sib2, iclass 13, count 2 2006.217.08:08:27.99#ibcon#flushed, iclass 13, count 2 2006.217.08:08:27.99#ibcon#about to write, iclass 13, count 2 2006.217.08:08:27.99#ibcon#wrote, iclass 13, count 2 2006.217.08:08:27.99#ibcon#about to read 3, iclass 13, count 2 2006.217.08:08:28.02#ibcon#read 3, iclass 13, count 2 2006.217.08:08:28.02#ibcon#about to read 4, iclass 13, count 2 2006.217.08:08:28.02#ibcon#read 4, iclass 13, count 2 2006.217.08:08:28.02#ibcon#about to read 5, iclass 13, count 2 2006.217.08:08:28.02#ibcon#read 5, iclass 13, count 2 2006.217.08:08:28.02#ibcon#about to read 6, iclass 13, count 2 2006.217.08:08:28.02#ibcon#read 6, iclass 13, count 2 2006.217.08:08:28.02#ibcon#end of sib2, iclass 13, count 2 2006.217.08:08:28.02#ibcon#*after write, iclass 13, count 2 2006.217.08:08:28.02#ibcon#*before return 0, iclass 13, count 2 2006.217.08:08:28.02#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.217.08:08:28.02#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.217.08:08:28.02#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.217.08:08:28.02#ibcon#ireg 7 cls_cnt 0 2006.217.08:08:28.02#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.217.08:08:28.14#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.217.08:08:28.14#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.217.08:08:28.14#ibcon#enter wrdev, iclass 13, count 0 2006.217.08:08:28.14#ibcon#first serial, iclass 13, count 0 2006.217.08:08:28.14#ibcon#enter sib2, iclass 13, count 0 2006.217.08:08:28.14#ibcon#flushed, iclass 13, count 0 2006.217.08:08:28.14#ibcon#about to write, iclass 13, count 0 2006.217.08:08:28.14#ibcon#wrote, iclass 13, count 0 2006.217.08:08:28.14#ibcon#about to read 3, iclass 13, count 0 2006.217.08:08:28.16#ibcon#read 3, iclass 13, count 0 2006.217.08:08:28.16#ibcon#about to read 4, iclass 13, count 0 2006.217.08:08:28.16#ibcon#read 4, iclass 13, count 0 2006.217.08:08:28.16#ibcon#about to read 5, iclass 13, count 0 2006.217.08:08:28.16#ibcon#read 5, iclass 13, count 0 2006.217.08:08:28.16#ibcon#about to read 6, iclass 13, count 0 2006.217.08:08:28.16#ibcon#read 6, iclass 13, count 0 2006.217.08:08:28.16#ibcon#end of sib2, iclass 13, count 0 2006.217.08:08:28.16#ibcon#*mode == 0, iclass 13, count 0 2006.217.08:08:28.16#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.217.08:08:28.16#ibcon#[25=USB\r\n] 2006.217.08:08:28.16#ibcon#*before write, iclass 13, count 0 2006.217.08:08:28.16#ibcon#enter sib2, iclass 13, count 0 2006.217.08:08:28.16#ibcon#flushed, iclass 13, count 0 2006.217.08:08:28.16#ibcon#about to write, iclass 13, count 0 2006.217.08:08:28.16#ibcon#wrote, iclass 13, count 0 2006.217.08:08:28.16#ibcon#about to read 3, iclass 13, count 0 2006.217.08:08:28.19#ibcon#read 3, iclass 13, count 0 2006.217.08:08:28.19#ibcon#about to read 4, iclass 13, count 0 2006.217.08:08:28.19#ibcon#read 4, iclass 13, count 0 2006.217.08:08:28.19#ibcon#about to read 5, iclass 13, count 0 2006.217.08:08:28.19#ibcon#read 5, iclass 13, count 0 2006.217.08:08:28.19#ibcon#about to read 6, iclass 13, count 0 2006.217.08:08:28.19#ibcon#read 6, iclass 13, count 0 2006.217.08:08:28.19#ibcon#end of sib2, iclass 13, count 0 2006.217.08:08:28.19#ibcon#*after write, iclass 13, count 0 2006.217.08:08:28.19#ibcon#*before return 0, iclass 13, count 0 2006.217.08:08:28.19#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.217.08:08:28.19#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.217.08:08:28.19#ibcon#about to clear, iclass 13 cls_cnt 0 2006.217.08:08:28.19#ibcon#cleared, iclass 13 cls_cnt 0 2006.217.08:08:28.19$vc4f8/valo=2,572.99 2006.217.08:08:28.19#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.217.08:08:28.19#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.217.08:08:28.19#ibcon#ireg 17 cls_cnt 0 2006.217.08:08:28.19#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.217.08:08:28.19#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.217.08:08:28.19#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.217.08:08:28.19#ibcon#enter wrdev, iclass 15, count 0 2006.217.08:08:28.19#ibcon#first serial, iclass 15, count 0 2006.217.08:08:28.19#ibcon#enter sib2, iclass 15, count 0 2006.217.08:08:28.19#ibcon#flushed, iclass 15, count 0 2006.217.08:08:28.19#ibcon#about to write, iclass 15, count 0 2006.217.08:08:28.19#ibcon#wrote, iclass 15, count 0 2006.217.08:08:28.19#ibcon#about to read 3, iclass 15, count 0 2006.217.08:08:28.21#ibcon#read 3, iclass 15, count 0 2006.217.08:08:28.21#ibcon#about to read 4, iclass 15, count 0 2006.217.08:08:28.21#ibcon#read 4, iclass 15, count 0 2006.217.08:08:28.21#ibcon#about to read 5, iclass 15, count 0 2006.217.08:08:28.21#ibcon#read 5, iclass 15, count 0 2006.217.08:08:28.21#ibcon#about to read 6, iclass 15, count 0 2006.217.08:08:28.21#ibcon#read 6, iclass 15, count 0 2006.217.08:08:28.21#ibcon#end of sib2, iclass 15, count 0 2006.217.08:08:28.21#ibcon#*mode == 0, iclass 15, count 0 2006.217.08:08:28.21#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.217.08:08:28.21#ibcon#[26=FRQ=02,572.99\r\n] 2006.217.08:08:28.21#ibcon#*before write, iclass 15, count 0 2006.217.08:08:28.21#ibcon#enter sib2, iclass 15, count 0 2006.217.08:08:28.21#ibcon#flushed, iclass 15, count 0 2006.217.08:08:28.21#ibcon#about to write, iclass 15, count 0 2006.217.08:08:28.21#ibcon#wrote, iclass 15, count 0 2006.217.08:08:28.21#ibcon#about to read 3, iclass 15, count 0 2006.217.08:08:28.26#ibcon#read 3, iclass 15, count 0 2006.217.08:08:28.26#ibcon#about to read 4, iclass 15, count 0 2006.217.08:08:28.26#ibcon#read 4, iclass 15, count 0 2006.217.08:08:28.26#ibcon#about to read 5, iclass 15, count 0 2006.217.08:08:28.26#ibcon#read 5, iclass 15, count 0 2006.217.08:08:28.26#ibcon#about to read 6, iclass 15, count 0 2006.217.08:08:28.26#ibcon#read 6, iclass 15, count 0 2006.217.08:08:28.26#ibcon#end of sib2, iclass 15, count 0 2006.217.08:08:28.26#ibcon#*after write, iclass 15, count 0 2006.217.08:08:28.26#ibcon#*before return 0, iclass 15, count 0 2006.217.08:08:28.26#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.217.08:08:28.26#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.217.08:08:28.26#ibcon#about to clear, iclass 15 cls_cnt 0 2006.217.08:08:28.26#ibcon#cleared, iclass 15 cls_cnt 0 2006.217.08:08:28.26$vc4f8/va=2,4 2006.217.08:08:28.26#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.217.08:08:28.26#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.217.08:08:28.26#ibcon#ireg 11 cls_cnt 2 2006.217.08:08:28.26#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.217.08:08:28.31#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.217.08:08:28.31#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.217.08:08:28.31#ibcon#enter wrdev, iclass 17, count 2 2006.217.08:08:28.31#ibcon#first serial, iclass 17, count 2 2006.217.08:08:28.31#ibcon#enter sib2, iclass 17, count 2 2006.217.08:08:28.31#ibcon#flushed, iclass 17, count 2 2006.217.08:08:28.31#ibcon#about to write, iclass 17, count 2 2006.217.08:08:28.31#ibcon#wrote, iclass 17, count 2 2006.217.08:08:28.31#ibcon#about to read 3, iclass 17, count 2 2006.217.08:08:28.33#ibcon#read 3, iclass 17, count 2 2006.217.08:08:28.33#ibcon#about to read 4, iclass 17, count 2 2006.217.08:08:28.33#ibcon#read 4, iclass 17, count 2 2006.217.08:08:28.33#ibcon#about to read 5, iclass 17, count 2 2006.217.08:08:28.33#ibcon#read 5, iclass 17, count 2 2006.217.08:08:28.33#ibcon#about to read 6, iclass 17, count 2 2006.217.08:08:28.33#ibcon#read 6, iclass 17, count 2 2006.217.08:08:28.33#ibcon#end of sib2, iclass 17, count 2 2006.217.08:08:28.33#ibcon#*mode == 0, iclass 17, count 2 2006.217.08:08:28.33#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.217.08:08:28.33#ibcon#[25=AT02-04\r\n] 2006.217.08:08:28.33#ibcon#*before write, iclass 17, count 2 2006.217.08:08:28.33#ibcon#enter sib2, iclass 17, count 2 2006.217.08:08:28.33#ibcon#flushed, iclass 17, count 2 2006.217.08:08:28.33#ibcon#about to write, iclass 17, count 2 2006.217.08:08:28.33#ibcon#wrote, iclass 17, count 2 2006.217.08:08:28.33#ibcon#about to read 3, iclass 17, count 2 2006.217.08:08:28.36#ibcon#read 3, iclass 17, count 2 2006.217.08:08:28.36#ibcon#about to read 4, iclass 17, count 2 2006.217.08:08:28.36#ibcon#read 4, iclass 17, count 2 2006.217.08:08:28.36#ibcon#about to read 5, iclass 17, count 2 2006.217.08:08:28.36#ibcon#read 5, iclass 17, count 2 2006.217.08:08:28.36#ibcon#about to read 6, iclass 17, count 2 2006.217.08:08:28.36#ibcon#read 6, iclass 17, count 2 2006.217.08:08:28.36#ibcon#end of sib2, iclass 17, count 2 2006.217.08:08:28.36#ibcon#*after write, iclass 17, count 2 2006.217.08:08:28.36#ibcon#*before return 0, iclass 17, count 2 2006.217.08:08:28.36#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.217.08:08:28.36#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.217.08:08:28.36#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.217.08:08:28.36#ibcon#ireg 7 cls_cnt 0 2006.217.08:08:28.36#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.217.08:08:28.48#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.217.08:08:28.48#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.217.08:08:28.48#ibcon#enter wrdev, iclass 17, count 0 2006.217.08:08:28.48#ibcon#first serial, iclass 17, count 0 2006.217.08:08:28.48#ibcon#enter sib2, iclass 17, count 0 2006.217.08:08:28.48#ibcon#flushed, iclass 17, count 0 2006.217.08:08:28.48#ibcon#about to write, iclass 17, count 0 2006.217.08:08:28.48#ibcon#wrote, iclass 17, count 0 2006.217.08:08:28.48#ibcon#about to read 3, iclass 17, count 0 2006.217.08:08:28.50#ibcon#read 3, iclass 17, count 0 2006.217.08:08:28.50#ibcon#about to read 4, iclass 17, count 0 2006.217.08:08:28.50#ibcon#read 4, iclass 17, count 0 2006.217.08:08:28.50#ibcon#about to read 5, iclass 17, count 0 2006.217.08:08:28.50#ibcon#read 5, iclass 17, count 0 2006.217.08:08:28.50#ibcon#about to read 6, iclass 17, count 0 2006.217.08:08:28.50#ibcon#read 6, iclass 17, count 0 2006.217.08:08:28.50#ibcon#end of sib2, iclass 17, count 0 2006.217.08:08:28.50#ibcon#*mode == 0, iclass 17, count 0 2006.217.08:08:28.50#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.217.08:08:28.50#ibcon#[25=USB\r\n] 2006.217.08:08:28.50#ibcon#*before write, iclass 17, count 0 2006.217.08:08:28.50#ibcon#enter sib2, iclass 17, count 0 2006.217.08:08:28.50#ibcon#flushed, iclass 17, count 0 2006.217.08:08:28.50#ibcon#about to write, iclass 17, count 0 2006.217.08:08:28.50#ibcon#wrote, iclass 17, count 0 2006.217.08:08:28.50#ibcon#about to read 3, iclass 17, count 0 2006.217.08:08:28.53#ibcon#read 3, iclass 17, count 0 2006.217.08:08:28.53#ibcon#about to read 4, iclass 17, count 0 2006.217.08:08:28.53#ibcon#read 4, iclass 17, count 0 2006.217.08:08:28.53#ibcon#about to read 5, iclass 17, count 0 2006.217.08:08:28.53#ibcon#read 5, iclass 17, count 0 2006.217.08:08:28.53#ibcon#about to read 6, iclass 17, count 0 2006.217.08:08:28.53#ibcon#read 6, iclass 17, count 0 2006.217.08:08:28.53#ibcon#end of sib2, iclass 17, count 0 2006.217.08:08:28.53#ibcon#*after write, iclass 17, count 0 2006.217.08:08:28.53#ibcon#*before return 0, iclass 17, count 0 2006.217.08:08:28.53#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.217.08:08:28.53#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.217.08:08:28.53#ibcon#about to clear, iclass 17 cls_cnt 0 2006.217.08:08:28.53#ibcon#cleared, iclass 17 cls_cnt 0 2006.217.08:08:28.53$vc4f8/valo=3,672.99 2006.217.08:08:28.53#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.217.08:08:28.53#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.217.08:08:28.53#ibcon#ireg 17 cls_cnt 0 2006.217.08:08:28.53#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.217.08:08:28.53#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.217.08:08:28.53#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.217.08:08:28.53#ibcon#enter wrdev, iclass 19, count 0 2006.217.08:08:28.53#ibcon#first serial, iclass 19, count 0 2006.217.08:08:28.53#ibcon#enter sib2, iclass 19, count 0 2006.217.08:08:28.53#ibcon#flushed, iclass 19, count 0 2006.217.08:08:28.53#ibcon#about to write, iclass 19, count 0 2006.217.08:08:28.53#ibcon#wrote, iclass 19, count 0 2006.217.08:08:28.53#ibcon#about to read 3, iclass 19, count 0 2006.217.08:08:28.55#ibcon#read 3, iclass 19, count 0 2006.217.08:08:28.55#ibcon#about to read 4, iclass 19, count 0 2006.217.08:08:28.55#ibcon#read 4, iclass 19, count 0 2006.217.08:08:28.55#ibcon#about to read 5, iclass 19, count 0 2006.217.08:08:28.55#ibcon#read 5, iclass 19, count 0 2006.217.08:08:28.55#ibcon#about to read 6, iclass 19, count 0 2006.217.08:08:28.55#ibcon#read 6, iclass 19, count 0 2006.217.08:08:28.55#ibcon#end of sib2, iclass 19, count 0 2006.217.08:08:28.55#ibcon#*mode == 0, iclass 19, count 0 2006.217.08:08:28.55#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.217.08:08:28.55#ibcon#[26=FRQ=03,672.99\r\n] 2006.217.08:08:28.55#ibcon#*before write, iclass 19, count 0 2006.217.08:08:28.55#ibcon#enter sib2, iclass 19, count 0 2006.217.08:08:28.55#ibcon#flushed, iclass 19, count 0 2006.217.08:08:28.55#ibcon#about to write, iclass 19, count 0 2006.217.08:08:28.55#ibcon#wrote, iclass 19, count 0 2006.217.08:08:28.55#ibcon#about to read 3, iclass 19, count 0 2006.217.08:08:28.60#ibcon#read 3, iclass 19, count 0 2006.217.08:08:28.60#ibcon#about to read 4, iclass 19, count 0 2006.217.08:08:28.60#ibcon#read 4, iclass 19, count 0 2006.217.08:08:28.60#ibcon#about to read 5, iclass 19, count 0 2006.217.08:08:28.60#ibcon#read 5, iclass 19, count 0 2006.217.08:08:28.60#ibcon#about to read 6, iclass 19, count 0 2006.217.08:08:28.60#ibcon#read 6, iclass 19, count 0 2006.217.08:08:28.60#ibcon#end of sib2, iclass 19, count 0 2006.217.08:08:28.60#ibcon#*after write, iclass 19, count 0 2006.217.08:08:28.60#ibcon#*before return 0, iclass 19, count 0 2006.217.08:08:28.60#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.217.08:08:28.60#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.217.08:08:28.60#ibcon#about to clear, iclass 19 cls_cnt 0 2006.217.08:08:28.60#ibcon#cleared, iclass 19 cls_cnt 0 2006.217.08:08:28.60$vc4f8/va=3,4 2006.217.08:08:28.60#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.217.08:08:28.60#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.217.08:08:28.60#ibcon#ireg 11 cls_cnt 2 2006.217.08:08:28.60#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.217.08:08:28.65#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.217.08:08:28.65#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.217.08:08:28.65#ibcon#enter wrdev, iclass 21, count 2 2006.217.08:08:28.65#ibcon#first serial, iclass 21, count 2 2006.217.08:08:28.65#ibcon#enter sib2, iclass 21, count 2 2006.217.08:08:28.65#ibcon#flushed, iclass 21, count 2 2006.217.08:08:28.65#ibcon#about to write, iclass 21, count 2 2006.217.08:08:28.65#ibcon#wrote, iclass 21, count 2 2006.217.08:08:28.65#ibcon#about to read 3, iclass 21, count 2 2006.217.08:08:28.67#ibcon#read 3, iclass 21, count 2 2006.217.08:08:28.67#ibcon#about to read 4, iclass 21, count 2 2006.217.08:08:28.67#ibcon#read 4, iclass 21, count 2 2006.217.08:08:28.67#ibcon#about to read 5, iclass 21, count 2 2006.217.08:08:28.67#ibcon#read 5, iclass 21, count 2 2006.217.08:08:28.67#ibcon#about to read 6, iclass 21, count 2 2006.217.08:08:28.67#ibcon#read 6, iclass 21, count 2 2006.217.08:08:28.67#ibcon#end of sib2, iclass 21, count 2 2006.217.08:08:28.67#ibcon#*mode == 0, iclass 21, count 2 2006.217.08:08:28.67#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.217.08:08:28.67#ibcon#[25=AT03-04\r\n] 2006.217.08:08:28.67#ibcon#*before write, iclass 21, count 2 2006.217.08:08:28.67#ibcon#enter sib2, iclass 21, count 2 2006.217.08:08:28.67#ibcon#flushed, iclass 21, count 2 2006.217.08:08:28.67#ibcon#about to write, iclass 21, count 2 2006.217.08:08:28.67#ibcon#wrote, iclass 21, count 2 2006.217.08:08:28.67#ibcon#about to read 3, iclass 21, count 2 2006.217.08:08:28.70#ibcon#read 3, iclass 21, count 2 2006.217.08:08:28.70#ibcon#about to read 4, iclass 21, count 2 2006.217.08:08:28.70#ibcon#read 4, iclass 21, count 2 2006.217.08:08:28.70#ibcon#about to read 5, iclass 21, count 2 2006.217.08:08:28.70#ibcon#read 5, iclass 21, count 2 2006.217.08:08:28.70#ibcon#about to read 6, iclass 21, count 2 2006.217.08:08:28.70#ibcon#read 6, iclass 21, count 2 2006.217.08:08:28.70#ibcon#end of sib2, iclass 21, count 2 2006.217.08:08:28.70#ibcon#*after write, iclass 21, count 2 2006.217.08:08:28.70#ibcon#*before return 0, iclass 21, count 2 2006.217.08:08:28.70#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.217.08:08:28.70#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.217.08:08:28.70#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.217.08:08:28.70#ibcon#ireg 7 cls_cnt 0 2006.217.08:08:28.70#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.217.08:08:28.82#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.217.08:08:28.82#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.217.08:08:28.82#ibcon#enter wrdev, iclass 21, count 0 2006.217.08:08:28.82#ibcon#first serial, iclass 21, count 0 2006.217.08:08:28.82#ibcon#enter sib2, iclass 21, count 0 2006.217.08:08:28.82#ibcon#flushed, iclass 21, count 0 2006.217.08:08:28.82#ibcon#about to write, iclass 21, count 0 2006.217.08:08:28.82#ibcon#wrote, iclass 21, count 0 2006.217.08:08:28.82#ibcon#about to read 3, iclass 21, count 0 2006.217.08:08:28.84#ibcon#read 3, iclass 21, count 0 2006.217.08:08:28.84#ibcon#about to read 4, iclass 21, count 0 2006.217.08:08:28.84#ibcon#read 4, iclass 21, count 0 2006.217.08:08:28.84#ibcon#about to read 5, iclass 21, count 0 2006.217.08:08:28.84#ibcon#read 5, iclass 21, count 0 2006.217.08:08:28.84#ibcon#about to read 6, iclass 21, count 0 2006.217.08:08:28.84#ibcon#read 6, iclass 21, count 0 2006.217.08:08:28.84#ibcon#end of sib2, iclass 21, count 0 2006.217.08:08:28.84#ibcon#*mode == 0, iclass 21, count 0 2006.217.08:08:28.84#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.217.08:08:28.84#ibcon#[25=USB\r\n] 2006.217.08:08:28.84#ibcon#*before write, iclass 21, count 0 2006.217.08:08:28.84#ibcon#enter sib2, iclass 21, count 0 2006.217.08:08:28.84#ibcon#flushed, iclass 21, count 0 2006.217.08:08:28.84#ibcon#about to write, iclass 21, count 0 2006.217.08:08:28.84#ibcon#wrote, iclass 21, count 0 2006.217.08:08:28.84#ibcon#about to read 3, iclass 21, count 0 2006.217.08:08:28.87#ibcon#read 3, iclass 21, count 0 2006.217.08:08:28.87#ibcon#about to read 4, iclass 21, count 0 2006.217.08:08:28.87#ibcon#read 4, iclass 21, count 0 2006.217.08:08:28.87#ibcon#about to read 5, iclass 21, count 0 2006.217.08:08:28.87#ibcon#read 5, iclass 21, count 0 2006.217.08:08:28.87#ibcon#about to read 6, iclass 21, count 0 2006.217.08:08:28.87#ibcon#read 6, iclass 21, count 0 2006.217.08:08:28.87#ibcon#end of sib2, iclass 21, count 0 2006.217.08:08:28.87#ibcon#*after write, iclass 21, count 0 2006.217.08:08:28.87#ibcon#*before return 0, iclass 21, count 0 2006.217.08:08:28.87#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.217.08:08:28.87#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.217.08:08:28.87#ibcon#about to clear, iclass 21 cls_cnt 0 2006.217.08:08:28.87#ibcon#cleared, iclass 21 cls_cnt 0 2006.217.08:08:28.87$vc4f8/valo=4,832.99 2006.217.08:08:28.87#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.217.08:08:28.87#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.217.08:08:28.87#ibcon#ireg 17 cls_cnt 0 2006.217.08:08:28.87#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.217.08:08:28.87#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.217.08:08:28.87#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.217.08:08:28.87#ibcon#enter wrdev, iclass 23, count 0 2006.217.08:08:28.87#ibcon#first serial, iclass 23, count 0 2006.217.08:08:28.87#ibcon#enter sib2, iclass 23, count 0 2006.217.08:08:28.87#ibcon#flushed, iclass 23, count 0 2006.217.08:08:28.87#ibcon#about to write, iclass 23, count 0 2006.217.08:08:28.87#ibcon#wrote, iclass 23, count 0 2006.217.08:08:28.87#ibcon#about to read 3, iclass 23, count 0 2006.217.08:08:28.89#ibcon#read 3, iclass 23, count 0 2006.217.08:08:28.89#ibcon#about to read 4, iclass 23, count 0 2006.217.08:08:28.89#ibcon#read 4, iclass 23, count 0 2006.217.08:08:28.89#ibcon#about to read 5, iclass 23, count 0 2006.217.08:08:28.89#ibcon#read 5, iclass 23, count 0 2006.217.08:08:28.89#ibcon#about to read 6, iclass 23, count 0 2006.217.08:08:28.89#ibcon#read 6, iclass 23, count 0 2006.217.08:08:28.89#ibcon#end of sib2, iclass 23, count 0 2006.217.08:08:28.89#ibcon#*mode == 0, iclass 23, count 0 2006.217.08:08:28.89#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.217.08:08:28.89#ibcon#[26=FRQ=04,832.99\r\n] 2006.217.08:08:28.89#ibcon#*before write, iclass 23, count 0 2006.217.08:08:28.89#ibcon#enter sib2, iclass 23, count 0 2006.217.08:08:28.89#ibcon#flushed, iclass 23, count 0 2006.217.08:08:28.89#ibcon#about to write, iclass 23, count 0 2006.217.08:08:28.89#ibcon#wrote, iclass 23, count 0 2006.217.08:08:28.89#ibcon#about to read 3, iclass 23, count 0 2006.217.08:08:28.94#ibcon#read 3, iclass 23, count 0 2006.217.08:08:28.94#ibcon#about to read 4, iclass 23, count 0 2006.217.08:08:28.94#ibcon#read 4, iclass 23, count 0 2006.217.08:08:28.94#ibcon#about to read 5, iclass 23, count 0 2006.217.08:08:28.94#ibcon#read 5, iclass 23, count 0 2006.217.08:08:28.94#ibcon#about to read 6, iclass 23, count 0 2006.217.08:08:28.94#ibcon#read 6, iclass 23, count 0 2006.217.08:08:28.94#ibcon#end of sib2, iclass 23, count 0 2006.217.08:08:28.94#ibcon#*after write, iclass 23, count 0 2006.217.08:08:28.94#ibcon#*before return 0, iclass 23, count 0 2006.217.08:08:28.94#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.217.08:08:28.94#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.217.08:08:28.94#ibcon#about to clear, iclass 23 cls_cnt 0 2006.217.08:08:28.94#ibcon#cleared, iclass 23 cls_cnt 0 2006.217.08:08:28.94$vc4f8/va=4,4 2006.217.08:08:28.94#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.217.08:08:28.94#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.217.08:08:28.94#ibcon#ireg 11 cls_cnt 2 2006.217.08:08:28.94#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.217.08:08:28.99#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.217.08:08:28.99#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.217.08:08:28.99#ibcon#enter wrdev, iclass 25, count 2 2006.217.08:08:28.99#ibcon#first serial, iclass 25, count 2 2006.217.08:08:28.99#ibcon#enter sib2, iclass 25, count 2 2006.217.08:08:28.99#ibcon#flushed, iclass 25, count 2 2006.217.08:08:28.99#ibcon#about to write, iclass 25, count 2 2006.217.08:08:28.99#ibcon#wrote, iclass 25, count 2 2006.217.08:08:28.99#ibcon#about to read 3, iclass 25, count 2 2006.217.08:08:29.01#ibcon#read 3, iclass 25, count 2 2006.217.08:08:29.01#ibcon#about to read 4, iclass 25, count 2 2006.217.08:08:29.01#ibcon#read 4, iclass 25, count 2 2006.217.08:08:29.01#ibcon#about to read 5, iclass 25, count 2 2006.217.08:08:29.01#ibcon#read 5, iclass 25, count 2 2006.217.08:08:29.01#ibcon#about to read 6, iclass 25, count 2 2006.217.08:08:29.01#ibcon#read 6, iclass 25, count 2 2006.217.08:08:29.01#ibcon#end of sib2, iclass 25, count 2 2006.217.08:08:29.01#ibcon#*mode == 0, iclass 25, count 2 2006.217.08:08:29.01#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.217.08:08:29.01#ibcon#[25=AT04-04\r\n] 2006.217.08:08:29.01#ibcon#*before write, iclass 25, count 2 2006.217.08:08:29.01#ibcon#enter sib2, iclass 25, count 2 2006.217.08:08:29.01#ibcon#flushed, iclass 25, count 2 2006.217.08:08:29.01#ibcon#about to write, iclass 25, count 2 2006.217.08:08:29.01#ibcon#wrote, iclass 25, count 2 2006.217.08:08:29.01#ibcon#about to read 3, iclass 25, count 2 2006.217.08:08:29.04#ibcon#read 3, iclass 25, count 2 2006.217.08:08:29.04#ibcon#about to read 4, iclass 25, count 2 2006.217.08:08:29.04#ibcon#read 4, iclass 25, count 2 2006.217.08:08:29.04#ibcon#about to read 5, iclass 25, count 2 2006.217.08:08:29.04#ibcon#read 5, iclass 25, count 2 2006.217.08:08:29.04#ibcon#about to read 6, iclass 25, count 2 2006.217.08:08:29.04#ibcon#read 6, iclass 25, count 2 2006.217.08:08:29.04#ibcon#end of sib2, iclass 25, count 2 2006.217.08:08:29.04#ibcon#*after write, iclass 25, count 2 2006.217.08:08:29.04#ibcon#*before return 0, iclass 25, count 2 2006.217.08:08:29.04#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.217.08:08:29.04#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.217.08:08:29.04#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.217.08:08:29.04#ibcon#ireg 7 cls_cnt 0 2006.217.08:08:29.04#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.217.08:08:29.16#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.217.08:08:29.16#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.217.08:08:29.16#ibcon#enter wrdev, iclass 25, count 0 2006.217.08:08:29.16#ibcon#first serial, iclass 25, count 0 2006.217.08:08:29.16#ibcon#enter sib2, iclass 25, count 0 2006.217.08:08:29.16#ibcon#flushed, iclass 25, count 0 2006.217.08:08:29.16#ibcon#about to write, iclass 25, count 0 2006.217.08:08:29.16#ibcon#wrote, iclass 25, count 0 2006.217.08:08:29.16#ibcon#about to read 3, iclass 25, count 0 2006.217.08:08:29.18#ibcon#read 3, iclass 25, count 0 2006.217.08:08:29.18#ibcon#about to read 4, iclass 25, count 0 2006.217.08:08:29.18#ibcon#read 4, iclass 25, count 0 2006.217.08:08:29.18#ibcon#about to read 5, iclass 25, count 0 2006.217.08:08:29.18#ibcon#read 5, iclass 25, count 0 2006.217.08:08:29.18#ibcon#about to read 6, iclass 25, count 0 2006.217.08:08:29.18#ibcon#read 6, iclass 25, count 0 2006.217.08:08:29.18#ibcon#end of sib2, iclass 25, count 0 2006.217.08:08:29.18#ibcon#*mode == 0, iclass 25, count 0 2006.217.08:08:29.18#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.217.08:08:29.18#ibcon#[25=USB\r\n] 2006.217.08:08:29.18#ibcon#*before write, iclass 25, count 0 2006.217.08:08:29.18#ibcon#enter sib2, iclass 25, count 0 2006.217.08:08:29.18#ibcon#flushed, iclass 25, count 0 2006.217.08:08:29.18#ibcon#about to write, iclass 25, count 0 2006.217.08:08:29.18#ibcon#wrote, iclass 25, count 0 2006.217.08:08:29.18#ibcon#about to read 3, iclass 25, count 0 2006.217.08:08:29.21#ibcon#read 3, iclass 25, count 0 2006.217.08:08:29.21#ibcon#about to read 4, iclass 25, count 0 2006.217.08:08:29.21#ibcon#read 4, iclass 25, count 0 2006.217.08:08:29.21#ibcon#about to read 5, iclass 25, count 0 2006.217.08:08:29.21#ibcon#read 5, iclass 25, count 0 2006.217.08:08:29.21#ibcon#about to read 6, iclass 25, count 0 2006.217.08:08:29.21#ibcon#read 6, iclass 25, count 0 2006.217.08:08:29.21#ibcon#end of sib2, iclass 25, count 0 2006.217.08:08:29.21#ibcon#*after write, iclass 25, count 0 2006.217.08:08:29.21#ibcon#*before return 0, iclass 25, count 0 2006.217.08:08:29.21#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.217.08:08:29.21#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.217.08:08:29.21#ibcon#about to clear, iclass 25 cls_cnt 0 2006.217.08:08:29.21#ibcon#cleared, iclass 25 cls_cnt 0 2006.217.08:08:29.21$vc4f8/valo=5,652.99 2006.217.08:08:29.21#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.217.08:08:29.21#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.217.08:08:29.21#ibcon#ireg 17 cls_cnt 0 2006.217.08:08:29.21#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.217.08:08:29.21#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.217.08:08:29.21#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.217.08:08:29.21#ibcon#enter wrdev, iclass 27, count 0 2006.217.08:08:29.21#ibcon#first serial, iclass 27, count 0 2006.217.08:08:29.21#ibcon#enter sib2, iclass 27, count 0 2006.217.08:08:29.21#ibcon#flushed, iclass 27, count 0 2006.217.08:08:29.21#ibcon#about to write, iclass 27, count 0 2006.217.08:08:29.21#ibcon#wrote, iclass 27, count 0 2006.217.08:08:29.21#ibcon#about to read 3, iclass 27, count 0 2006.217.08:08:29.23#ibcon#read 3, iclass 27, count 0 2006.217.08:08:29.23#ibcon#about to read 4, iclass 27, count 0 2006.217.08:08:29.23#ibcon#read 4, iclass 27, count 0 2006.217.08:08:29.23#ibcon#about to read 5, iclass 27, count 0 2006.217.08:08:29.23#ibcon#read 5, iclass 27, count 0 2006.217.08:08:29.23#ibcon#about to read 6, iclass 27, count 0 2006.217.08:08:29.23#ibcon#read 6, iclass 27, count 0 2006.217.08:08:29.23#ibcon#end of sib2, iclass 27, count 0 2006.217.08:08:29.23#ibcon#*mode == 0, iclass 27, count 0 2006.217.08:08:29.23#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.217.08:08:29.23#ibcon#[26=FRQ=05,652.99\r\n] 2006.217.08:08:29.23#ibcon#*before write, iclass 27, count 0 2006.217.08:08:29.23#ibcon#enter sib2, iclass 27, count 0 2006.217.08:08:29.23#ibcon#flushed, iclass 27, count 0 2006.217.08:08:29.23#ibcon#about to write, iclass 27, count 0 2006.217.08:08:29.23#ibcon#wrote, iclass 27, count 0 2006.217.08:08:29.23#ibcon#about to read 3, iclass 27, count 0 2006.217.08:08:29.27#ibcon#read 3, iclass 27, count 0 2006.217.08:08:29.27#ibcon#about to read 4, iclass 27, count 0 2006.217.08:08:29.27#ibcon#read 4, iclass 27, count 0 2006.217.08:08:29.27#ibcon#about to read 5, iclass 27, count 0 2006.217.08:08:29.27#ibcon#read 5, iclass 27, count 0 2006.217.08:08:29.27#ibcon#about to read 6, iclass 27, count 0 2006.217.08:08:29.27#ibcon#read 6, iclass 27, count 0 2006.217.08:08:29.27#ibcon#end of sib2, iclass 27, count 0 2006.217.08:08:29.27#ibcon#*after write, iclass 27, count 0 2006.217.08:08:29.27#ibcon#*before return 0, iclass 27, count 0 2006.217.08:08:29.27#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.217.08:08:29.27#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.217.08:08:29.27#ibcon#about to clear, iclass 27 cls_cnt 0 2006.217.08:08:29.27#ibcon#cleared, iclass 27 cls_cnt 0 2006.217.08:08:29.27$vc4f8/va=5,7 2006.217.08:08:29.27#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.217.08:08:29.27#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.217.08:08:29.27#ibcon#ireg 11 cls_cnt 2 2006.217.08:08:29.27#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.217.08:08:29.33#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.217.08:08:29.33#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.217.08:08:29.33#ibcon#enter wrdev, iclass 29, count 2 2006.217.08:08:29.33#ibcon#first serial, iclass 29, count 2 2006.217.08:08:29.33#ibcon#enter sib2, iclass 29, count 2 2006.217.08:08:29.33#ibcon#flushed, iclass 29, count 2 2006.217.08:08:29.33#ibcon#about to write, iclass 29, count 2 2006.217.08:08:29.33#ibcon#wrote, iclass 29, count 2 2006.217.08:08:29.33#ibcon#about to read 3, iclass 29, count 2 2006.217.08:08:29.35#ibcon#read 3, iclass 29, count 2 2006.217.08:08:29.35#ibcon#about to read 4, iclass 29, count 2 2006.217.08:08:29.35#ibcon#read 4, iclass 29, count 2 2006.217.08:08:29.35#ibcon#about to read 5, iclass 29, count 2 2006.217.08:08:29.35#ibcon#read 5, iclass 29, count 2 2006.217.08:08:29.35#ibcon#about to read 6, iclass 29, count 2 2006.217.08:08:29.35#ibcon#read 6, iclass 29, count 2 2006.217.08:08:29.35#ibcon#end of sib2, iclass 29, count 2 2006.217.08:08:29.35#ibcon#*mode == 0, iclass 29, count 2 2006.217.08:08:29.35#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.217.08:08:29.35#ibcon#[25=AT05-07\r\n] 2006.217.08:08:29.35#ibcon#*before write, iclass 29, count 2 2006.217.08:08:29.35#ibcon#enter sib2, iclass 29, count 2 2006.217.08:08:29.35#ibcon#flushed, iclass 29, count 2 2006.217.08:08:29.35#ibcon#about to write, iclass 29, count 2 2006.217.08:08:29.35#ibcon#wrote, iclass 29, count 2 2006.217.08:08:29.35#ibcon#about to read 3, iclass 29, count 2 2006.217.08:08:29.38#ibcon#read 3, iclass 29, count 2 2006.217.08:08:29.38#ibcon#about to read 4, iclass 29, count 2 2006.217.08:08:29.38#ibcon#read 4, iclass 29, count 2 2006.217.08:08:29.38#ibcon#about to read 5, iclass 29, count 2 2006.217.08:08:29.38#ibcon#read 5, iclass 29, count 2 2006.217.08:08:29.38#ibcon#about to read 6, iclass 29, count 2 2006.217.08:08:29.38#ibcon#read 6, iclass 29, count 2 2006.217.08:08:29.38#ibcon#end of sib2, iclass 29, count 2 2006.217.08:08:29.38#ibcon#*after write, iclass 29, count 2 2006.217.08:08:29.38#ibcon#*before return 0, iclass 29, count 2 2006.217.08:08:29.38#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.217.08:08:29.38#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.217.08:08:29.38#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.217.08:08:29.38#ibcon#ireg 7 cls_cnt 0 2006.217.08:08:29.38#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.217.08:08:29.50#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.217.08:08:29.50#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.217.08:08:29.50#ibcon#enter wrdev, iclass 29, count 0 2006.217.08:08:29.50#ibcon#first serial, iclass 29, count 0 2006.217.08:08:29.50#ibcon#enter sib2, iclass 29, count 0 2006.217.08:08:29.50#ibcon#flushed, iclass 29, count 0 2006.217.08:08:29.50#ibcon#about to write, iclass 29, count 0 2006.217.08:08:29.50#ibcon#wrote, iclass 29, count 0 2006.217.08:08:29.50#ibcon#about to read 3, iclass 29, count 0 2006.217.08:08:29.52#ibcon#read 3, iclass 29, count 0 2006.217.08:08:29.52#ibcon#about to read 4, iclass 29, count 0 2006.217.08:08:29.52#ibcon#read 4, iclass 29, count 0 2006.217.08:08:29.52#ibcon#about to read 5, iclass 29, count 0 2006.217.08:08:29.52#ibcon#read 5, iclass 29, count 0 2006.217.08:08:29.52#ibcon#about to read 6, iclass 29, count 0 2006.217.08:08:29.52#ibcon#read 6, iclass 29, count 0 2006.217.08:08:29.52#ibcon#end of sib2, iclass 29, count 0 2006.217.08:08:29.52#ibcon#*mode == 0, iclass 29, count 0 2006.217.08:08:29.52#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.217.08:08:29.52#ibcon#[25=USB\r\n] 2006.217.08:08:29.52#ibcon#*before write, iclass 29, count 0 2006.217.08:08:29.52#ibcon#enter sib2, iclass 29, count 0 2006.217.08:08:29.52#ibcon#flushed, iclass 29, count 0 2006.217.08:08:29.52#ibcon#about to write, iclass 29, count 0 2006.217.08:08:29.52#ibcon#wrote, iclass 29, count 0 2006.217.08:08:29.52#ibcon#about to read 3, iclass 29, count 0 2006.217.08:08:29.55#ibcon#read 3, iclass 29, count 0 2006.217.08:08:29.55#ibcon#about to read 4, iclass 29, count 0 2006.217.08:08:29.55#ibcon#read 4, iclass 29, count 0 2006.217.08:08:29.55#ibcon#about to read 5, iclass 29, count 0 2006.217.08:08:29.55#ibcon#read 5, iclass 29, count 0 2006.217.08:08:29.55#ibcon#about to read 6, iclass 29, count 0 2006.217.08:08:29.55#ibcon#read 6, iclass 29, count 0 2006.217.08:08:29.55#ibcon#end of sib2, iclass 29, count 0 2006.217.08:08:29.55#ibcon#*after write, iclass 29, count 0 2006.217.08:08:29.55#ibcon#*before return 0, iclass 29, count 0 2006.217.08:08:29.55#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.217.08:08:29.55#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.217.08:08:29.55#ibcon#about to clear, iclass 29 cls_cnt 0 2006.217.08:08:29.55#ibcon#cleared, iclass 29 cls_cnt 0 2006.217.08:08:29.55$vc4f8/valo=6,772.99 2006.217.08:08:29.55#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.217.08:08:29.55#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.217.08:08:29.55#ibcon#ireg 17 cls_cnt 0 2006.217.08:08:29.55#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.217.08:08:29.55#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.217.08:08:29.55#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.217.08:08:29.55#ibcon#enter wrdev, iclass 31, count 0 2006.217.08:08:29.55#ibcon#first serial, iclass 31, count 0 2006.217.08:08:29.55#ibcon#enter sib2, iclass 31, count 0 2006.217.08:08:29.55#ibcon#flushed, iclass 31, count 0 2006.217.08:08:29.55#ibcon#about to write, iclass 31, count 0 2006.217.08:08:29.55#ibcon#wrote, iclass 31, count 0 2006.217.08:08:29.55#ibcon#about to read 3, iclass 31, count 0 2006.217.08:08:29.57#ibcon#read 3, iclass 31, count 0 2006.217.08:08:29.57#ibcon#about to read 4, iclass 31, count 0 2006.217.08:08:29.57#ibcon#read 4, iclass 31, count 0 2006.217.08:08:29.57#ibcon#about to read 5, iclass 31, count 0 2006.217.08:08:29.57#ibcon#read 5, iclass 31, count 0 2006.217.08:08:29.57#ibcon#about to read 6, iclass 31, count 0 2006.217.08:08:29.57#ibcon#read 6, iclass 31, count 0 2006.217.08:08:29.57#ibcon#end of sib2, iclass 31, count 0 2006.217.08:08:29.57#ibcon#*mode == 0, iclass 31, count 0 2006.217.08:08:29.57#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.217.08:08:29.57#ibcon#[26=FRQ=06,772.99\r\n] 2006.217.08:08:29.57#ibcon#*before write, iclass 31, count 0 2006.217.08:08:29.57#ibcon#enter sib2, iclass 31, count 0 2006.217.08:08:29.57#ibcon#flushed, iclass 31, count 0 2006.217.08:08:29.57#ibcon#about to write, iclass 31, count 0 2006.217.08:08:29.57#ibcon#wrote, iclass 31, count 0 2006.217.08:08:29.57#ibcon#about to read 3, iclass 31, count 0 2006.217.08:08:29.62#ibcon#read 3, iclass 31, count 0 2006.217.08:08:29.62#ibcon#about to read 4, iclass 31, count 0 2006.217.08:08:29.62#ibcon#read 4, iclass 31, count 0 2006.217.08:08:29.62#ibcon#about to read 5, iclass 31, count 0 2006.217.08:08:29.62#ibcon#read 5, iclass 31, count 0 2006.217.08:08:29.62#ibcon#about to read 6, iclass 31, count 0 2006.217.08:08:29.62#ibcon#read 6, iclass 31, count 0 2006.217.08:08:29.62#ibcon#end of sib2, iclass 31, count 0 2006.217.08:08:29.62#ibcon#*after write, iclass 31, count 0 2006.217.08:08:29.62#ibcon#*before return 0, iclass 31, count 0 2006.217.08:08:29.62#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.217.08:08:29.62#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.217.08:08:29.62#ibcon#about to clear, iclass 31 cls_cnt 0 2006.217.08:08:29.62#ibcon#cleared, iclass 31 cls_cnt 0 2006.217.08:08:29.62$vc4f8/va=6,6 2006.217.08:08:29.62#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.217.08:08:29.62#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.217.08:08:29.62#ibcon#ireg 11 cls_cnt 2 2006.217.08:08:29.62#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.217.08:08:29.67#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.217.08:08:29.67#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.217.08:08:29.67#ibcon#enter wrdev, iclass 33, count 2 2006.217.08:08:29.67#ibcon#first serial, iclass 33, count 2 2006.217.08:08:29.67#ibcon#enter sib2, iclass 33, count 2 2006.217.08:08:29.67#ibcon#flushed, iclass 33, count 2 2006.217.08:08:29.67#ibcon#about to write, iclass 33, count 2 2006.217.08:08:29.67#ibcon#wrote, iclass 33, count 2 2006.217.08:08:29.67#ibcon#about to read 3, iclass 33, count 2 2006.217.08:08:29.69#ibcon#read 3, iclass 33, count 2 2006.217.08:08:29.69#ibcon#about to read 4, iclass 33, count 2 2006.217.08:08:29.69#ibcon#read 4, iclass 33, count 2 2006.217.08:08:29.69#ibcon#about to read 5, iclass 33, count 2 2006.217.08:08:29.69#ibcon#read 5, iclass 33, count 2 2006.217.08:08:29.69#ibcon#about to read 6, iclass 33, count 2 2006.217.08:08:29.69#ibcon#read 6, iclass 33, count 2 2006.217.08:08:29.69#ibcon#end of sib2, iclass 33, count 2 2006.217.08:08:29.69#ibcon#*mode == 0, iclass 33, count 2 2006.217.08:08:29.69#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.217.08:08:29.69#ibcon#[25=AT06-06\r\n] 2006.217.08:08:29.69#ibcon#*before write, iclass 33, count 2 2006.217.08:08:29.69#ibcon#enter sib2, iclass 33, count 2 2006.217.08:08:29.69#ibcon#flushed, iclass 33, count 2 2006.217.08:08:29.69#ibcon#about to write, iclass 33, count 2 2006.217.08:08:29.69#ibcon#wrote, iclass 33, count 2 2006.217.08:08:29.69#ibcon#about to read 3, iclass 33, count 2 2006.217.08:08:29.72#ibcon#read 3, iclass 33, count 2 2006.217.08:08:29.72#ibcon#about to read 4, iclass 33, count 2 2006.217.08:08:29.72#ibcon#read 4, iclass 33, count 2 2006.217.08:08:29.72#ibcon#about to read 5, iclass 33, count 2 2006.217.08:08:29.72#ibcon#read 5, iclass 33, count 2 2006.217.08:08:29.72#ibcon#about to read 6, iclass 33, count 2 2006.217.08:08:29.72#ibcon#read 6, iclass 33, count 2 2006.217.08:08:29.72#ibcon#end of sib2, iclass 33, count 2 2006.217.08:08:29.72#ibcon#*after write, iclass 33, count 2 2006.217.08:08:29.72#ibcon#*before return 0, iclass 33, count 2 2006.217.08:08:29.72#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.217.08:08:29.72#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.217.08:08:29.72#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.217.08:08:29.72#ibcon#ireg 7 cls_cnt 0 2006.217.08:08:29.72#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.217.08:08:29.84#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.217.08:08:29.84#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.217.08:08:29.84#ibcon#enter wrdev, iclass 33, count 0 2006.217.08:08:29.84#ibcon#first serial, iclass 33, count 0 2006.217.08:08:29.84#ibcon#enter sib2, iclass 33, count 0 2006.217.08:08:29.84#ibcon#flushed, iclass 33, count 0 2006.217.08:08:29.84#ibcon#about to write, iclass 33, count 0 2006.217.08:08:29.84#ibcon#wrote, iclass 33, count 0 2006.217.08:08:29.84#ibcon#about to read 3, iclass 33, count 0 2006.217.08:08:29.86#ibcon#read 3, iclass 33, count 0 2006.217.08:08:29.86#ibcon#about to read 4, iclass 33, count 0 2006.217.08:08:29.86#ibcon#read 4, iclass 33, count 0 2006.217.08:08:29.86#ibcon#about to read 5, iclass 33, count 0 2006.217.08:08:29.86#ibcon#read 5, iclass 33, count 0 2006.217.08:08:29.86#ibcon#about to read 6, iclass 33, count 0 2006.217.08:08:29.86#ibcon#read 6, iclass 33, count 0 2006.217.08:08:29.86#ibcon#end of sib2, iclass 33, count 0 2006.217.08:08:29.86#ibcon#*mode == 0, iclass 33, count 0 2006.217.08:08:29.86#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.217.08:08:29.86#ibcon#[25=USB\r\n] 2006.217.08:08:29.86#ibcon#*before write, iclass 33, count 0 2006.217.08:08:29.86#ibcon#enter sib2, iclass 33, count 0 2006.217.08:08:29.86#ibcon#flushed, iclass 33, count 0 2006.217.08:08:29.86#ibcon#about to write, iclass 33, count 0 2006.217.08:08:29.86#ibcon#wrote, iclass 33, count 0 2006.217.08:08:29.86#ibcon#about to read 3, iclass 33, count 0 2006.217.08:08:29.89#ibcon#read 3, iclass 33, count 0 2006.217.08:08:29.89#ibcon#about to read 4, iclass 33, count 0 2006.217.08:08:29.89#ibcon#read 4, iclass 33, count 0 2006.217.08:08:29.89#ibcon#about to read 5, iclass 33, count 0 2006.217.08:08:29.89#ibcon#read 5, iclass 33, count 0 2006.217.08:08:29.89#ibcon#about to read 6, iclass 33, count 0 2006.217.08:08:29.89#ibcon#read 6, iclass 33, count 0 2006.217.08:08:29.89#ibcon#end of sib2, iclass 33, count 0 2006.217.08:08:29.89#ibcon#*after write, iclass 33, count 0 2006.217.08:08:29.89#ibcon#*before return 0, iclass 33, count 0 2006.217.08:08:29.89#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.217.08:08:29.89#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.217.08:08:29.89#ibcon#about to clear, iclass 33 cls_cnt 0 2006.217.08:08:29.89#ibcon#cleared, iclass 33 cls_cnt 0 2006.217.08:08:29.89$vc4f8/valo=7,832.99 2006.217.08:08:29.89#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.217.08:08:29.89#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.217.08:08:29.89#ibcon#ireg 17 cls_cnt 0 2006.217.08:08:29.89#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.217.08:08:29.89#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.217.08:08:29.89#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.217.08:08:29.89#ibcon#enter wrdev, iclass 35, count 0 2006.217.08:08:29.89#ibcon#first serial, iclass 35, count 0 2006.217.08:08:29.89#ibcon#enter sib2, iclass 35, count 0 2006.217.08:08:29.89#ibcon#flushed, iclass 35, count 0 2006.217.08:08:29.89#ibcon#about to write, iclass 35, count 0 2006.217.08:08:29.89#ibcon#wrote, iclass 35, count 0 2006.217.08:08:29.89#ibcon#about to read 3, iclass 35, count 0 2006.217.08:08:29.91#ibcon#read 3, iclass 35, count 0 2006.217.08:08:29.91#ibcon#about to read 4, iclass 35, count 0 2006.217.08:08:29.91#ibcon#read 4, iclass 35, count 0 2006.217.08:08:29.91#ibcon#about to read 5, iclass 35, count 0 2006.217.08:08:29.91#ibcon#read 5, iclass 35, count 0 2006.217.08:08:29.91#ibcon#about to read 6, iclass 35, count 0 2006.217.08:08:29.91#ibcon#read 6, iclass 35, count 0 2006.217.08:08:29.91#ibcon#end of sib2, iclass 35, count 0 2006.217.08:08:29.91#ibcon#*mode == 0, iclass 35, count 0 2006.217.08:08:29.91#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.217.08:08:29.91#ibcon#[26=FRQ=07,832.99\r\n] 2006.217.08:08:29.91#ibcon#*before write, iclass 35, count 0 2006.217.08:08:29.91#ibcon#enter sib2, iclass 35, count 0 2006.217.08:08:29.91#ibcon#flushed, iclass 35, count 0 2006.217.08:08:29.91#ibcon#about to write, iclass 35, count 0 2006.217.08:08:29.91#ibcon#wrote, iclass 35, count 0 2006.217.08:08:29.91#ibcon#about to read 3, iclass 35, count 0 2006.217.08:08:29.95#ibcon#read 3, iclass 35, count 0 2006.217.08:08:29.95#ibcon#about to read 4, iclass 35, count 0 2006.217.08:08:29.95#ibcon#read 4, iclass 35, count 0 2006.217.08:08:29.95#ibcon#about to read 5, iclass 35, count 0 2006.217.08:08:29.95#ibcon#read 5, iclass 35, count 0 2006.217.08:08:29.95#ibcon#about to read 6, iclass 35, count 0 2006.217.08:08:29.95#ibcon#read 6, iclass 35, count 0 2006.217.08:08:29.95#ibcon#end of sib2, iclass 35, count 0 2006.217.08:08:29.95#ibcon#*after write, iclass 35, count 0 2006.217.08:08:29.95#ibcon#*before return 0, iclass 35, count 0 2006.217.08:08:29.95#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.217.08:08:29.95#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.217.08:08:29.95#ibcon#about to clear, iclass 35 cls_cnt 0 2006.217.08:08:29.95#ibcon#cleared, iclass 35 cls_cnt 0 2006.217.08:08:29.95$vc4f8/va=7,6 2006.217.08:08:29.95#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.217.08:08:29.95#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.217.08:08:29.95#ibcon#ireg 11 cls_cnt 2 2006.217.08:08:29.95#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.217.08:08:30.01#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.217.08:08:30.01#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.217.08:08:30.01#ibcon#enter wrdev, iclass 37, count 2 2006.217.08:08:30.01#ibcon#first serial, iclass 37, count 2 2006.217.08:08:30.01#ibcon#enter sib2, iclass 37, count 2 2006.217.08:08:30.01#ibcon#flushed, iclass 37, count 2 2006.217.08:08:30.01#ibcon#about to write, iclass 37, count 2 2006.217.08:08:30.01#ibcon#wrote, iclass 37, count 2 2006.217.08:08:30.01#ibcon#about to read 3, iclass 37, count 2 2006.217.08:08:30.03#ibcon#read 3, iclass 37, count 2 2006.217.08:08:30.03#ibcon#about to read 4, iclass 37, count 2 2006.217.08:08:30.03#ibcon#read 4, iclass 37, count 2 2006.217.08:08:30.03#ibcon#about to read 5, iclass 37, count 2 2006.217.08:08:30.03#ibcon#read 5, iclass 37, count 2 2006.217.08:08:30.03#ibcon#about to read 6, iclass 37, count 2 2006.217.08:08:30.03#ibcon#read 6, iclass 37, count 2 2006.217.08:08:30.03#ibcon#end of sib2, iclass 37, count 2 2006.217.08:08:30.03#ibcon#*mode == 0, iclass 37, count 2 2006.217.08:08:30.03#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.217.08:08:30.03#ibcon#[25=AT07-06\r\n] 2006.217.08:08:30.03#ibcon#*before write, iclass 37, count 2 2006.217.08:08:30.03#ibcon#enter sib2, iclass 37, count 2 2006.217.08:08:30.03#ibcon#flushed, iclass 37, count 2 2006.217.08:08:30.03#ibcon#about to write, iclass 37, count 2 2006.217.08:08:30.03#ibcon#wrote, iclass 37, count 2 2006.217.08:08:30.03#ibcon#about to read 3, iclass 37, count 2 2006.217.08:08:30.06#ibcon#read 3, iclass 37, count 2 2006.217.08:08:30.06#ibcon#about to read 4, iclass 37, count 2 2006.217.08:08:30.06#ibcon#read 4, iclass 37, count 2 2006.217.08:08:30.06#ibcon#about to read 5, iclass 37, count 2 2006.217.08:08:30.06#ibcon#read 5, iclass 37, count 2 2006.217.08:08:30.06#ibcon#about to read 6, iclass 37, count 2 2006.217.08:08:30.06#ibcon#read 6, iclass 37, count 2 2006.217.08:08:30.06#ibcon#end of sib2, iclass 37, count 2 2006.217.08:08:30.06#ibcon#*after write, iclass 37, count 2 2006.217.08:08:30.06#ibcon#*before return 0, iclass 37, count 2 2006.217.08:08:30.06#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.217.08:08:30.06#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.217.08:08:30.06#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.217.08:08:30.06#ibcon#ireg 7 cls_cnt 0 2006.217.08:08:30.06#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.217.08:08:30.18#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.217.08:08:30.18#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.217.08:08:30.18#ibcon#enter wrdev, iclass 37, count 0 2006.217.08:08:30.18#ibcon#first serial, iclass 37, count 0 2006.217.08:08:30.18#ibcon#enter sib2, iclass 37, count 0 2006.217.08:08:30.18#ibcon#flushed, iclass 37, count 0 2006.217.08:08:30.18#ibcon#about to write, iclass 37, count 0 2006.217.08:08:30.18#ibcon#wrote, iclass 37, count 0 2006.217.08:08:30.18#ibcon#about to read 3, iclass 37, count 0 2006.217.08:08:30.20#ibcon#read 3, iclass 37, count 0 2006.217.08:08:30.20#ibcon#about to read 4, iclass 37, count 0 2006.217.08:08:30.20#ibcon#read 4, iclass 37, count 0 2006.217.08:08:30.20#ibcon#about to read 5, iclass 37, count 0 2006.217.08:08:30.20#ibcon#read 5, iclass 37, count 0 2006.217.08:08:30.20#ibcon#about to read 6, iclass 37, count 0 2006.217.08:08:30.20#ibcon#read 6, iclass 37, count 0 2006.217.08:08:30.20#ibcon#end of sib2, iclass 37, count 0 2006.217.08:08:30.20#ibcon#*mode == 0, iclass 37, count 0 2006.217.08:08:30.20#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.217.08:08:30.20#ibcon#[25=USB\r\n] 2006.217.08:08:30.20#ibcon#*before write, iclass 37, count 0 2006.217.08:08:30.20#ibcon#enter sib2, iclass 37, count 0 2006.217.08:08:30.20#ibcon#flushed, iclass 37, count 0 2006.217.08:08:30.20#ibcon#about to write, iclass 37, count 0 2006.217.08:08:30.20#ibcon#wrote, iclass 37, count 0 2006.217.08:08:30.20#ibcon#about to read 3, iclass 37, count 0 2006.217.08:08:30.23#ibcon#read 3, iclass 37, count 0 2006.217.08:08:30.23#ibcon#about to read 4, iclass 37, count 0 2006.217.08:08:30.23#ibcon#read 4, iclass 37, count 0 2006.217.08:08:30.23#ibcon#about to read 5, iclass 37, count 0 2006.217.08:08:30.23#ibcon#read 5, iclass 37, count 0 2006.217.08:08:30.23#ibcon#about to read 6, iclass 37, count 0 2006.217.08:08:30.23#ibcon#read 6, iclass 37, count 0 2006.217.08:08:30.23#ibcon#end of sib2, iclass 37, count 0 2006.217.08:08:30.23#ibcon#*after write, iclass 37, count 0 2006.217.08:08:30.23#ibcon#*before return 0, iclass 37, count 0 2006.217.08:08:30.23#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.217.08:08:30.23#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.217.08:08:30.23#ibcon#about to clear, iclass 37 cls_cnt 0 2006.217.08:08:30.23#ibcon#cleared, iclass 37 cls_cnt 0 2006.217.08:08:30.23$vc4f8/valo=8,852.99 2006.217.08:08:30.23#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.217.08:08:30.23#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.217.08:08:30.23#ibcon#ireg 17 cls_cnt 0 2006.217.08:08:30.23#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.217.08:08:30.23#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.217.08:08:30.23#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.217.08:08:30.23#ibcon#enter wrdev, iclass 39, count 0 2006.217.08:08:30.23#ibcon#first serial, iclass 39, count 0 2006.217.08:08:30.23#ibcon#enter sib2, iclass 39, count 0 2006.217.08:08:30.23#ibcon#flushed, iclass 39, count 0 2006.217.08:08:30.23#ibcon#about to write, iclass 39, count 0 2006.217.08:08:30.23#ibcon#wrote, iclass 39, count 0 2006.217.08:08:30.23#ibcon#about to read 3, iclass 39, count 0 2006.217.08:08:30.25#ibcon#read 3, iclass 39, count 0 2006.217.08:08:30.25#ibcon#about to read 4, iclass 39, count 0 2006.217.08:08:30.25#ibcon#read 4, iclass 39, count 0 2006.217.08:08:30.25#ibcon#about to read 5, iclass 39, count 0 2006.217.08:08:30.25#ibcon#read 5, iclass 39, count 0 2006.217.08:08:30.25#ibcon#about to read 6, iclass 39, count 0 2006.217.08:08:30.25#ibcon#read 6, iclass 39, count 0 2006.217.08:08:30.25#ibcon#end of sib2, iclass 39, count 0 2006.217.08:08:30.25#ibcon#*mode == 0, iclass 39, count 0 2006.217.08:08:30.25#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.217.08:08:30.25#ibcon#[26=FRQ=08,852.99\r\n] 2006.217.08:08:30.25#ibcon#*before write, iclass 39, count 0 2006.217.08:08:30.25#ibcon#enter sib2, iclass 39, count 0 2006.217.08:08:30.25#ibcon#flushed, iclass 39, count 0 2006.217.08:08:30.25#ibcon#about to write, iclass 39, count 0 2006.217.08:08:30.25#ibcon#wrote, iclass 39, count 0 2006.217.08:08:30.25#ibcon#about to read 3, iclass 39, count 0 2006.217.08:08:30.29#ibcon#read 3, iclass 39, count 0 2006.217.08:08:30.29#ibcon#about to read 4, iclass 39, count 0 2006.217.08:08:30.29#ibcon#read 4, iclass 39, count 0 2006.217.08:08:30.29#ibcon#about to read 5, iclass 39, count 0 2006.217.08:08:30.29#ibcon#read 5, iclass 39, count 0 2006.217.08:08:30.29#ibcon#about to read 6, iclass 39, count 0 2006.217.08:08:30.29#ibcon#read 6, iclass 39, count 0 2006.217.08:08:30.29#ibcon#end of sib2, iclass 39, count 0 2006.217.08:08:30.29#ibcon#*after write, iclass 39, count 0 2006.217.08:08:30.29#ibcon#*before return 0, iclass 39, count 0 2006.217.08:08:30.29#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.217.08:08:30.29#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.217.08:08:30.29#ibcon#about to clear, iclass 39 cls_cnt 0 2006.217.08:08:30.29#ibcon#cleared, iclass 39 cls_cnt 0 2006.217.08:08:30.29$vc4f8/va=8,7 2006.217.08:08:30.29#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.217.08:08:30.29#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.217.08:08:30.29#ibcon#ireg 11 cls_cnt 2 2006.217.08:08:30.29#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.217.08:08:30.32#abcon#<5=/05 4.2 7.2 30.73 641008.6\r\n> 2006.217.08:08:30.34#abcon#{5=INTERFACE CLEAR} 2006.217.08:08:30.35#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.217.08:08:30.35#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.217.08:08:30.35#ibcon#enter wrdev, iclass 4, count 2 2006.217.08:08:30.35#ibcon#first serial, iclass 4, count 2 2006.217.08:08:30.35#ibcon#enter sib2, iclass 4, count 2 2006.217.08:08:30.35#ibcon#flushed, iclass 4, count 2 2006.217.08:08:30.35#ibcon#about to write, iclass 4, count 2 2006.217.08:08:30.35#ibcon#wrote, iclass 4, count 2 2006.217.08:08:30.35#ibcon#about to read 3, iclass 4, count 2 2006.217.08:08:30.37#ibcon#read 3, iclass 4, count 2 2006.217.08:08:30.37#ibcon#about to read 4, iclass 4, count 2 2006.217.08:08:30.37#ibcon#read 4, iclass 4, count 2 2006.217.08:08:30.37#ibcon#about to read 5, iclass 4, count 2 2006.217.08:08:30.37#ibcon#read 5, iclass 4, count 2 2006.217.08:08:30.37#ibcon#about to read 6, iclass 4, count 2 2006.217.08:08:30.37#ibcon#read 6, iclass 4, count 2 2006.217.08:08:30.37#ibcon#end of sib2, iclass 4, count 2 2006.217.08:08:30.37#ibcon#*mode == 0, iclass 4, count 2 2006.217.08:08:30.37#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.217.08:08:30.37#ibcon#[25=AT08-07\r\n] 2006.217.08:08:30.37#ibcon#*before write, iclass 4, count 2 2006.217.08:08:30.37#ibcon#enter sib2, iclass 4, count 2 2006.217.08:08:30.37#ibcon#flushed, iclass 4, count 2 2006.217.08:08:30.37#ibcon#about to write, iclass 4, count 2 2006.217.08:08:30.37#ibcon#wrote, iclass 4, count 2 2006.217.08:08:30.37#ibcon#about to read 3, iclass 4, count 2 2006.217.08:08:30.40#ibcon#read 3, iclass 4, count 2 2006.217.08:08:30.40#ibcon#about to read 4, iclass 4, count 2 2006.217.08:08:30.40#ibcon#read 4, iclass 4, count 2 2006.217.08:08:30.40#ibcon#about to read 5, iclass 4, count 2 2006.217.08:08:30.40#ibcon#read 5, iclass 4, count 2 2006.217.08:08:30.40#ibcon#about to read 6, iclass 4, count 2 2006.217.08:08:30.40#ibcon#read 6, iclass 4, count 2 2006.217.08:08:30.40#ibcon#end of sib2, iclass 4, count 2 2006.217.08:08:30.40#ibcon#*after write, iclass 4, count 2 2006.217.08:08:30.40#ibcon#*before return 0, iclass 4, count 2 2006.217.08:08:30.40#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.217.08:08:30.40#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.217.08:08:30.40#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.217.08:08:30.40#ibcon#ireg 7 cls_cnt 0 2006.217.08:08:30.40#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.217.08:08:30.40#abcon#[5=S1D000X0/0*\r\n] 2006.217.08:08:30.52#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.217.08:08:30.52#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.217.08:08:30.52#ibcon#enter wrdev, iclass 4, count 0 2006.217.08:08:30.52#ibcon#first serial, iclass 4, count 0 2006.217.08:08:30.52#ibcon#enter sib2, iclass 4, count 0 2006.217.08:08:30.52#ibcon#flushed, iclass 4, count 0 2006.217.08:08:30.52#ibcon#about to write, iclass 4, count 0 2006.217.08:08:30.52#ibcon#wrote, iclass 4, count 0 2006.217.08:08:30.52#ibcon#about to read 3, iclass 4, count 0 2006.217.08:08:30.54#ibcon#read 3, iclass 4, count 0 2006.217.08:08:30.54#ibcon#about to read 4, iclass 4, count 0 2006.217.08:08:30.54#ibcon#read 4, iclass 4, count 0 2006.217.08:08:30.54#ibcon#about to read 5, iclass 4, count 0 2006.217.08:08:30.54#ibcon#read 5, iclass 4, count 0 2006.217.08:08:30.54#ibcon#about to read 6, iclass 4, count 0 2006.217.08:08:30.54#ibcon#read 6, iclass 4, count 0 2006.217.08:08:30.54#ibcon#end of sib2, iclass 4, count 0 2006.217.08:08:30.54#ibcon#*mode == 0, iclass 4, count 0 2006.217.08:08:30.54#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.217.08:08:30.54#ibcon#[25=USB\r\n] 2006.217.08:08:30.54#ibcon#*before write, iclass 4, count 0 2006.217.08:08:30.54#ibcon#enter sib2, iclass 4, count 0 2006.217.08:08:30.54#ibcon#flushed, iclass 4, count 0 2006.217.08:08:30.54#ibcon#about to write, iclass 4, count 0 2006.217.08:08:30.54#ibcon#wrote, iclass 4, count 0 2006.217.08:08:30.54#ibcon#about to read 3, iclass 4, count 0 2006.217.08:08:30.57#ibcon#read 3, iclass 4, count 0 2006.217.08:08:30.57#ibcon#about to read 4, iclass 4, count 0 2006.217.08:08:30.57#ibcon#read 4, iclass 4, count 0 2006.217.08:08:30.57#ibcon#about to read 5, iclass 4, count 0 2006.217.08:08:30.57#ibcon#read 5, iclass 4, count 0 2006.217.08:08:30.57#ibcon#about to read 6, iclass 4, count 0 2006.217.08:08:30.57#ibcon#read 6, iclass 4, count 0 2006.217.08:08:30.57#ibcon#end of sib2, iclass 4, count 0 2006.217.08:08:30.57#ibcon#*after write, iclass 4, count 0 2006.217.08:08:30.57#ibcon#*before return 0, iclass 4, count 0 2006.217.08:08:30.57#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.217.08:08:30.57#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.217.08:08:30.57#ibcon#about to clear, iclass 4 cls_cnt 0 2006.217.08:08:30.57#ibcon#cleared, iclass 4 cls_cnt 0 2006.217.08:08:30.57$vc4f8/vblo=1,632.99 2006.217.08:08:30.57#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.217.08:08:30.57#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.217.08:08:30.57#ibcon#ireg 17 cls_cnt 0 2006.217.08:08:30.57#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.217.08:08:30.57#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.217.08:08:30.57#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.217.08:08:30.57#ibcon#enter wrdev, iclass 11, count 0 2006.217.08:08:30.57#ibcon#first serial, iclass 11, count 0 2006.217.08:08:30.57#ibcon#enter sib2, iclass 11, count 0 2006.217.08:08:30.57#ibcon#flushed, iclass 11, count 0 2006.217.08:08:30.57#ibcon#about to write, iclass 11, count 0 2006.217.08:08:30.57#ibcon#wrote, iclass 11, count 0 2006.217.08:08:30.57#ibcon#about to read 3, iclass 11, count 0 2006.217.08:08:30.59#ibcon#read 3, iclass 11, count 0 2006.217.08:08:30.59#ibcon#about to read 4, iclass 11, count 0 2006.217.08:08:30.59#ibcon#read 4, iclass 11, count 0 2006.217.08:08:30.59#ibcon#about to read 5, iclass 11, count 0 2006.217.08:08:30.59#ibcon#read 5, iclass 11, count 0 2006.217.08:08:30.59#ibcon#about to read 6, iclass 11, count 0 2006.217.08:08:30.59#ibcon#read 6, iclass 11, count 0 2006.217.08:08:30.59#ibcon#end of sib2, iclass 11, count 0 2006.217.08:08:30.59#ibcon#*mode == 0, iclass 11, count 0 2006.217.08:08:30.59#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.217.08:08:30.59#ibcon#[28=FRQ=01,632.99\r\n] 2006.217.08:08:30.59#ibcon#*before write, iclass 11, count 0 2006.217.08:08:30.59#ibcon#enter sib2, iclass 11, count 0 2006.217.08:08:30.59#ibcon#flushed, iclass 11, count 0 2006.217.08:08:30.59#ibcon#about to write, iclass 11, count 0 2006.217.08:08:30.59#ibcon#wrote, iclass 11, count 0 2006.217.08:08:30.59#ibcon#about to read 3, iclass 11, count 0 2006.217.08:08:30.63#ibcon#read 3, iclass 11, count 0 2006.217.08:08:30.63#ibcon#about to read 4, iclass 11, count 0 2006.217.08:08:30.63#ibcon#read 4, iclass 11, count 0 2006.217.08:08:30.63#ibcon#about to read 5, iclass 11, count 0 2006.217.08:08:30.63#ibcon#read 5, iclass 11, count 0 2006.217.08:08:30.63#ibcon#about to read 6, iclass 11, count 0 2006.217.08:08:30.63#ibcon#read 6, iclass 11, count 0 2006.217.08:08:30.63#ibcon#end of sib2, iclass 11, count 0 2006.217.08:08:30.63#ibcon#*after write, iclass 11, count 0 2006.217.08:08:30.63#ibcon#*before return 0, iclass 11, count 0 2006.217.08:08:30.63#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.217.08:08:30.63#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.217.08:08:30.63#ibcon#about to clear, iclass 11 cls_cnt 0 2006.217.08:08:30.63#ibcon#cleared, iclass 11 cls_cnt 0 2006.217.08:08:30.63$vc4f8/vb=1,4 2006.217.08:08:30.63#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.217.08:08:30.63#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.217.08:08:30.63#ibcon#ireg 11 cls_cnt 2 2006.217.08:08:30.63#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.217.08:08:30.63#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.217.08:08:30.63#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.217.08:08:30.63#ibcon#enter wrdev, iclass 13, count 2 2006.217.08:08:30.63#ibcon#first serial, iclass 13, count 2 2006.217.08:08:30.63#ibcon#enter sib2, iclass 13, count 2 2006.217.08:08:30.63#ibcon#flushed, iclass 13, count 2 2006.217.08:08:30.63#ibcon#about to write, iclass 13, count 2 2006.217.08:08:30.63#ibcon#wrote, iclass 13, count 2 2006.217.08:08:30.63#ibcon#about to read 3, iclass 13, count 2 2006.217.08:08:30.65#ibcon#read 3, iclass 13, count 2 2006.217.08:08:30.65#ibcon#about to read 4, iclass 13, count 2 2006.217.08:08:30.65#ibcon#read 4, iclass 13, count 2 2006.217.08:08:30.65#ibcon#about to read 5, iclass 13, count 2 2006.217.08:08:30.65#ibcon#read 5, iclass 13, count 2 2006.217.08:08:30.65#ibcon#about to read 6, iclass 13, count 2 2006.217.08:08:30.65#ibcon#read 6, iclass 13, count 2 2006.217.08:08:30.65#ibcon#end of sib2, iclass 13, count 2 2006.217.08:08:30.65#ibcon#*mode == 0, iclass 13, count 2 2006.217.08:08:30.65#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.217.08:08:30.65#ibcon#[27=AT01-04\r\n] 2006.217.08:08:30.65#ibcon#*before write, iclass 13, count 2 2006.217.08:08:30.65#ibcon#enter sib2, iclass 13, count 2 2006.217.08:08:30.65#ibcon#flushed, iclass 13, count 2 2006.217.08:08:30.65#ibcon#about to write, iclass 13, count 2 2006.217.08:08:30.65#ibcon#wrote, iclass 13, count 2 2006.217.08:08:30.65#ibcon#about to read 3, iclass 13, count 2 2006.217.08:08:30.68#ibcon#read 3, iclass 13, count 2 2006.217.08:08:30.68#ibcon#about to read 4, iclass 13, count 2 2006.217.08:08:30.68#ibcon#read 4, iclass 13, count 2 2006.217.08:08:30.68#ibcon#about to read 5, iclass 13, count 2 2006.217.08:08:30.68#ibcon#read 5, iclass 13, count 2 2006.217.08:08:30.68#ibcon#about to read 6, iclass 13, count 2 2006.217.08:08:30.68#ibcon#read 6, iclass 13, count 2 2006.217.08:08:30.68#ibcon#end of sib2, iclass 13, count 2 2006.217.08:08:30.68#ibcon#*after write, iclass 13, count 2 2006.217.08:08:30.68#ibcon#*before return 0, iclass 13, count 2 2006.217.08:08:30.68#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.217.08:08:30.68#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.217.08:08:30.68#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.217.08:08:30.68#ibcon#ireg 7 cls_cnt 0 2006.217.08:08:30.68#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.217.08:08:30.80#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.217.08:08:30.80#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.217.08:08:30.80#ibcon#enter wrdev, iclass 13, count 0 2006.217.08:08:30.80#ibcon#first serial, iclass 13, count 0 2006.217.08:08:30.80#ibcon#enter sib2, iclass 13, count 0 2006.217.08:08:30.80#ibcon#flushed, iclass 13, count 0 2006.217.08:08:30.80#ibcon#about to write, iclass 13, count 0 2006.217.08:08:30.80#ibcon#wrote, iclass 13, count 0 2006.217.08:08:30.80#ibcon#about to read 3, iclass 13, count 0 2006.217.08:08:30.82#ibcon#read 3, iclass 13, count 0 2006.217.08:08:30.82#ibcon#about to read 4, iclass 13, count 0 2006.217.08:08:30.82#ibcon#read 4, iclass 13, count 0 2006.217.08:08:30.82#ibcon#about to read 5, iclass 13, count 0 2006.217.08:08:30.82#ibcon#read 5, iclass 13, count 0 2006.217.08:08:30.82#ibcon#about to read 6, iclass 13, count 0 2006.217.08:08:30.82#ibcon#read 6, iclass 13, count 0 2006.217.08:08:30.82#ibcon#end of sib2, iclass 13, count 0 2006.217.08:08:30.82#ibcon#*mode == 0, iclass 13, count 0 2006.217.08:08:30.82#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.217.08:08:30.82#ibcon#[27=USB\r\n] 2006.217.08:08:30.82#ibcon#*before write, iclass 13, count 0 2006.217.08:08:30.82#ibcon#enter sib2, iclass 13, count 0 2006.217.08:08:30.82#ibcon#flushed, iclass 13, count 0 2006.217.08:08:30.82#ibcon#about to write, iclass 13, count 0 2006.217.08:08:30.82#ibcon#wrote, iclass 13, count 0 2006.217.08:08:30.82#ibcon#about to read 3, iclass 13, count 0 2006.217.08:08:30.85#ibcon#read 3, iclass 13, count 0 2006.217.08:08:30.85#ibcon#about to read 4, iclass 13, count 0 2006.217.08:08:30.85#ibcon#read 4, iclass 13, count 0 2006.217.08:08:30.85#ibcon#about to read 5, iclass 13, count 0 2006.217.08:08:30.85#ibcon#read 5, iclass 13, count 0 2006.217.08:08:30.85#ibcon#about to read 6, iclass 13, count 0 2006.217.08:08:30.85#ibcon#read 6, iclass 13, count 0 2006.217.08:08:30.85#ibcon#end of sib2, iclass 13, count 0 2006.217.08:08:30.85#ibcon#*after write, iclass 13, count 0 2006.217.08:08:30.85#ibcon#*before return 0, iclass 13, count 0 2006.217.08:08:30.85#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.217.08:08:30.85#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.217.08:08:30.85#ibcon#about to clear, iclass 13 cls_cnt 0 2006.217.08:08:30.85#ibcon#cleared, iclass 13 cls_cnt 0 2006.217.08:08:30.85$vc4f8/vblo=2,640.99 2006.217.08:08:30.85#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.217.08:08:30.85#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.217.08:08:30.85#ibcon#ireg 17 cls_cnt 0 2006.217.08:08:30.85#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.217.08:08:30.85#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.217.08:08:30.85#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.217.08:08:30.85#ibcon#enter wrdev, iclass 15, count 0 2006.217.08:08:30.85#ibcon#first serial, iclass 15, count 0 2006.217.08:08:30.85#ibcon#enter sib2, iclass 15, count 0 2006.217.08:08:30.85#ibcon#flushed, iclass 15, count 0 2006.217.08:08:30.85#ibcon#about to write, iclass 15, count 0 2006.217.08:08:30.85#ibcon#wrote, iclass 15, count 0 2006.217.08:08:30.85#ibcon#about to read 3, iclass 15, count 0 2006.217.08:08:30.87#ibcon#read 3, iclass 15, count 0 2006.217.08:08:30.87#ibcon#about to read 4, iclass 15, count 0 2006.217.08:08:30.87#ibcon#read 4, iclass 15, count 0 2006.217.08:08:30.87#ibcon#about to read 5, iclass 15, count 0 2006.217.08:08:30.87#ibcon#read 5, iclass 15, count 0 2006.217.08:08:30.87#ibcon#about to read 6, iclass 15, count 0 2006.217.08:08:30.87#ibcon#read 6, iclass 15, count 0 2006.217.08:08:30.87#ibcon#end of sib2, iclass 15, count 0 2006.217.08:08:30.87#ibcon#*mode == 0, iclass 15, count 0 2006.217.08:08:30.87#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.217.08:08:30.87#ibcon#[28=FRQ=02,640.99\r\n] 2006.217.08:08:30.87#ibcon#*before write, iclass 15, count 0 2006.217.08:08:30.87#ibcon#enter sib2, iclass 15, count 0 2006.217.08:08:30.87#ibcon#flushed, iclass 15, count 0 2006.217.08:08:30.87#ibcon#about to write, iclass 15, count 0 2006.217.08:08:30.87#ibcon#wrote, iclass 15, count 0 2006.217.08:08:30.87#ibcon#about to read 3, iclass 15, count 0 2006.217.08:08:30.91#ibcon#read 3, iclass 15, count 0 2006.217.08:08:30.91#ibcon#about to read 4, iclass 15, count 0 2006.217.08:08:30.91#ibcon#read 4, iclass 15, count 0 2006.217.08:08:30.91#ibcon#about to read 5, iclass 15, count 0 2006.217.08:08:30.91#ibcon#read 5, iclass 15, count 0 2006.217.08:08:30.91#ibcon#about to read 6, iclass 15, count 0 2006.217.08:08:30.91#ibcon#read 6, iclass 15, count 0 2006.217.08:08:30.91#ibcon#end of sib2, iclass 15, count 0 2006.217.08:08:30.91#ibcon#*after write, iclass 15, count 0 2006.217.08:08:30.91#ibcon#*before return 0, iclass 15, count 0 2006.217.08:08:30.91#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.217.08:08:30.91#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.217.08:08:30.91#ibcon#about to clear, iclass 15 cls_cnt 0 2006.217.08:08:30.91#ibcon#cleared, iclass 15 cls_cnt 0 2006.217.08:08:30.91$vc4f8/vb=2,4 2006.217.08:08:30.91#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.217.08:08:30.91#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.217.08:08:30.91#ibcon#ireg 11 cls_cnt 2 2006.217.08:08:30.91#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.217.08:08:30.97#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.217.08:08:30.97#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.217.08:08:30.97#ibcon#enter wrdev, iclass 17, count 2 2006.217.08:08:30.97#ibcon#first serial, iclass 17, count 2 2006.217.08:08:30.97#ibcon#enter sib2, iclass 17, count 2 2006.217.08:08:30.97#ibcon#flushed, iclass 17, count 2 2006.217.08:08:30.97#ibcon#about to write, iclass 17, count 2 2006.217.08:08:30.97#ibcon#wrote, iclass 17, count 2 2006.217.08:08:30.97#ibcon#about to read 3, iclass 17, count 2 2006.217.08:08:30.99#ibcon#read 3, iclass 17, count 2 2006.217.08:08:30.99#ibcon#about to read 4, iclass 17, count 2 2006.217.08:08:30.99#ibcon#read 4, iclass 17, count 2 2006.217.08:08:30.99#ibcon#about to read 5, iclass 17, count 2 2006.217.08:08:30.99#ibcon#read 5, iclass 17, count 2 2006.217.08:08:30.99#ibcon#about to read 6, iclass 17, count 2 2006.217.08:08:30.99#ibcon#read 6, iclass 17, count 2 2006.217.08:08:30.99#ibcon#end of sib2, iclass 17, count 2 2006.217.08:08:30.99#ibcon#*mode == 0, iclass 17, count 2 2006.217.08:08:30.99#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.217.08:08:30.99#ibcon#[27=AT02-04\r\n] 2006.217.08:08:30.99#ibcon#*before write, iclass 17, count 2 2006.217.08:08:30.99#ibcon#enter sib2, iclass 17, count 2 2006.217.08:08:30.99#ibcon#flushed, iclass 17, count 2 2006.217.08:08:30.99#ibcon#about to write, iclass 17, count 2 2006.217.08:08:30.99#ibcon#wrote, iclass 17, count 2 2006.217.08:08:30.99#ibcon#about to read 3, iclass 17, count 2 2006.217.08:08:31.02#ibcon#read 3, iclass 17, count 2 2006.217.08:08:31.02#ibcon#about to read 4, iclass 17, count 2 2006.217.08:08:31.02#ibcon#read 4, iclass 17, count 2 2006.217.08:08:31.02#ibcon#about to read 5, iclass 17, count 2 2006.217.08:08:31.02#ibcon#read 5, iclass 17, count 2 2006.217.08:08:31.02#ibcon#about to read 6, iclass 17, count 2 2006.217.08:08:31.02#ibcon#read 6, iclass 17, count 2 2006.217.08:08:31.02#ibcon#end of sib2, iclass 17, count 2 2006.217.08:08:31.02#ibcon#*after write, iclass 17, count 2 2006.217.08:08:31.02#ibcon#*before return 0, iclass 17, count 2 2006.217.08:08:31.02#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.217.08:08:31.02#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.217.08:08:31.02#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.217.08:08:31.02#ibcon#ireg 7 cls_cnt 0 2006.217.08:08:31.02#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.217.08:08:31.14#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.217.08:08:31.14#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.217.08:08:31.14#ibcon#enter wrdev, iclass 17, count 0 2006.217.08:08:31.14#ibcon#first serial, iclass 17, count 0 2006.217.08:08:31.14#ibcon#enter sib2, iclass 17, count 0 2006.217.08:08:31.14#ibcon#flushed, iclass 17, count 0 2006.217.08:08:31.14#ibcon#about to write, iclass 17, count 0 2006.217.08:08:31.14#ibcon#wrote, iclass 17, count 0 2006.217.08:08:31.14#ibcon#about to read 3, iclass 17, count 0 2006.217.08:08:31.16#ibcon#read 3, iclass 17, count 0 2006.217.08:08:31.16#ibcon#about to read 4, iclass 17, count 0 2006.217.08:08:31.16#ibcon#read 4, iclass 17, count 0 2006.217.08:08:31.16#ibcon#about to read 5, iclass 17, count 0 2006.217.08:08:31.16#ibcon#read 5, iclass 17, count 0 2006.217.08:08:31.16#ibcon#about to read 6, iclass 17, count 0 2006.217.08:08:31.16#ibcon#read 6, iclass 17, count 0 2006.217.08:08:31.16#ibcon#end of sib2, iclass 17, count 0 2006.217.08:08:31.16#ibcon#*mode == 0, iclass 17, count 0 2006.217.08:08:31.16#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.217.08:08:31.16#ibcon#[27=USB\r\n] 2006.217.08:08:31.16#ibcon#*before write, iclass 17, count 0 2006.217.08:08:31.16#ibcon#enter sib2, iclass 17, count 0 2006.217.08:08:31.16#ibcon#flushed, iclass 17, count 0 2006.217.08:08:31.16#ibcon#about to write, iclass 17, count 0 2006.217.08:08:31.16#ibcon#wrote, iclass 17, count 0 2006.217.08:08:31.16#ibcon#about to read 3, iclass 17, count 0 2006.217.08:08:31.19#ibcon#read 3, iclass 17, count 0 2006.217.08:08:31.19#ibcon#about to read 4, iclass 17, count 0 2006.217.08:08:31.19#ibcon#read 4, iclass 17, count 0 2006.217.08:08:31.19#ibcon#about to read 5, iclass 17, count 0 2006.217.08:08:31.19#ibcon#read 5, iclass 17, count 0 2006.217.08:08:31.19#ibcon#about to read 6, iclass 17, count 0 2006.217.08:08:31.19#ibcon#read 6, iclass 17, count 0 2006.217.08:08:31.19#ibcon#end of sib2, iclass 17, count 0 2006.217.08:08:31.19#ibcon#*after write, iclass 17, count 0 2006.217.08:08:31.19#ibcon#*before return 0, iclass 17, count 0 2006.217.08:08:31.19#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.217.08:08:31.19#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.217.08:08:31.19#ibcon#about to clear, iclass 17 cls_cnt 0 2006.217.08:08:31.19#ibcon#cleared, iclass 17 cls_cnt 0 2006.217.08:08:31.19$vc4f8/vblo=3,656.99 2006.217.08:08:31.19#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.217.08:08:31.19#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.217.08:08:31.19#ibcon#ireg 17 cls_cnt 0 2006.217.08:08:31.19#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.217.08:08:31.19#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.217.08:08:31.19#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.217.08:08:31.19#ibcon#enter wrdev, iclass 19, count 0 2006.217.08:08:31.19#ibcon#first serial, iclass 19, count 0 2006.217.08:08:31.19#ibcon#enter sib2, iclass 19, count 0 2006.217.08:08:31.19#ibcon#flushed, iclass 19, count 0 2006.217.08:08:31.19#ibcon#about to write, iclass 19, count 0 2006.217.08:08:31.19#ibcon#wrote, iclass 19, count 0 2006.217.08:08:31.19#ibcon#about to read 3, iclass 19, count 0 2006.217.08:08:31.21#ibcon#read 3, iclass 19, count 0 2006.217.08:08:31.21#ibcon#about to read 4, iclass 19, count 0 2006.217.08:08:31.21#ibcon#read 4, iclass 19, count 0 2006.217.08:08:31.21#ibcon#about to read 5, iclass 19, count 0 2006.217.08:08:31.21#ibcon#read 5, iclass 19, count 0 2006.217.08:08:31.21#ibcon#about to read 6, iclass 19, count 0 2006.217.08:08:31.21#ibcon#read 6, iclass 19, count 0 2006.217.08:08:31.21#ibcon#end of sib2, iclass 19, count 0 2006.217.08:08:31.21#ibcon#*mode == 0, iclass 19, count 0 2006.217.08:08:31.21#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.217.08:08:31.21#ibcon#[28=FRQ=03,656.99\r\n] 2006.217.08:08:31.21#ibcon#*before write, iclass 19, count 0 2006.217.08:08:31.21#ibcon#enter sib2, iclass 19, count 0 2006.217.08:08:31.21#ibcon#flushed, iclass 19, count 0 2006.217.08:08:31.21#ibcon#about to write, iclass 19, count 0 2006.217.08:08:31.21#ibcon#wrote, iclass 19, count 0 2006.217.08:08:31.21#ibcon#about to read 3, iclass 19, count 0 2006.217.08:08:31.25#ibcon#read 3, iclass 19, count 0 2006.217.08:08:31.25#ibcon#about to read 4, iclass 19, count 0 2006.217.08:08:31.25#ibcon#read 4, iclass 19, count 0 2006.217.08:08:31.25#ibcon#about to read 5, iclass 19, count 0 2006.217.08:08:31.25#ibcon#read 5, iclass 19, count 0 2006.217.08:08:31.25#ibcon#about to read 6, iclass 19, count 0 2006.217.08:08:31.25#ibcon#read 6, iclass 19, count 0 2006.217.08:08:31.25#ibcon#end of sib2, iclass 19, count 0 2006.217.08:08:31.25#ibcon#*after write, iclass 19, count 0 2006.217.08:08:31.25#ibcon#*before return 0, iclass 19, count 0 2006.217.08:08:31.25#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.217.08:08:31.25#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.217.08:08:31.25#ibcon#about to clear, iclass 19 cls_cnt 0 2006.217.08:08:31.25#ibcon#cleared, iclass 19 cls_cnt 0 2006.217.08:08:31.25$vc4f8/vb=3,4 2006.217.08:08:31.25#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.217.08:08:31.25#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.217.08:08:31.25#ibcon#ireg 11 cls_cnt 2 2006.217.08:08:31.25#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.217.08:08:31.31#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.217.08:08:31.31#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.217.08:08:31.31#ibcon#enter wrdev, iclass 21, count 2 2006.217.08:08:31.31#ibcon#first serial, iclass 21, count 2 2006.217.08:08:31.31#ibcon#enter sib2, iclass 21, count 2 2006.217.08:08:31.31#ibcon#flushed, iclass 21, count 2 2006.217.08:08:31.31#ibcon#about to write, iclass 21, count 2 2006.217.08:08:31.31#ibcon#wrote, iclass 21, count 2 2006.217.08:08:31.31#ibcon#about to read 3, iclass 21, count 2 2006.217.08:08:31.33#ibcon#read 3, iclass 21, count 2 2006.217.08:08:31.33#ibcon#about to read 4, iclass 21, count 2 2006.217.08:08:31.33#ibcon#read 4, iclass 21, count 2 2006.217.08:08:31.33#ibcon#about to read 5, iclass 21, count 2 2006.217.08:08:31.33#ibcon#read 5, iclass 21, count 2 2006.217.08:08:31.33#ibcon#about to read 6, iclass 21, count 2 2006.217.08:08:31.33#ibcon#read 6, iclass 21, count 2 2006.217.08:08:31.33#ibcon#end of sib2, iclass 21, count 2 2006.217.08:08:31.33#ibcon#*mode == 0, iclass 21, count 2 2006.217.08:08:31.33#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.217.08:08:31.33#ibcon#[27=AT03-04\r\n] 2006.217.08:08:31.33#ibcon#*before write, iclass 21, count 2 2006.217.08:08:31.33#ibcon#enter sib2, iclass 21, count 2 2006.217.08:08:31.33#ibcon#flushed, iclass 21, count 2 2006.217.08:08:31.33#ibcon#about to write, iclass 21, count 2 2006.217.08:08:31.33#ibcon#wrote, iclass 21, count 2 2006.217.08:08:31.33#ibcon#about to read 3, iclass 21, count 2 2006.217.08:08:31.36#ibcon#read 3, iclass 21, count 2 2006.217.08:08:31.36#ibcon#about to read 4, iclass 21, count 2 2006.217.08:08:31.36#ibcon#read 4, iclass 21, count 2 2006.217.08:08:31.36#ibcon#about to read 5, iclass 21, count 2 2006.217.08:08:31.36#ibcon#read 5, iclass 21, count 2 2006.217.08:08:31.36#ibcon#about to read 6, iclass 21, count 2 2006.217.08:08:31.36#ibcon#read 6, iclass 21, count 2 2006.217.08:08:31.36#ibcon#end of sib2, iclass 21, count 2 2006.217.08:08:31.36#ibcon#*after write, iclass 21, count 2 2006.217.08:08:31.36#ibcon#*before return 0, iclass 21, count 2 2006.217.08:08:31.36#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.217.08:08:31.36#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.217.08:08:31.36#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.217.08:08:31.36#ibcon#ireg 7 cls_cnt 0 2006.217.08:08:31.36#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.217.08:08:31.48#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.217.08:08:31.48#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.217.08:08:31.48#ibcon#enter wrdev, iclass 21, count 0 2006.217.08:08:31.48#ibcon#first serial, iclass 21, count 0 2006.217.08:08:31.48#ibcon#enter sib2, iclass 21, count 0 2006.217.08:08:31.48#ibcon#flushed, iclass 21, count 0 2006.217.08:08:31.48#ibcon#about to write, iclass 21, count 0 2006.217.08:08:31.48#ibcon#wrote, iclass 21, count 0 2006.217.08:08:31.48#ibcon#about to read 3, iclass 21, count 0 2006.217.08:08:31.50#ibcon#read 3, iclass 21, count 0 2006.217.08:08:31.50#ibcon#about to read 4, iclass 21, count 0 2006.217.08:08:31.50#ibcon#read 4, iclass 21, count 0 2006.217.08:08:31.50#ibcon#about to read 5, iclass 21, count 0 2006.217.08:08:31.50#ibcon#read 5, iclass 21, count 0 2006.217.08:08:31.50#ibcon#about to read 6, iclass 21, count 0 2006.217.08:08:31.50#ibcon#read 6, iclass 21, count 0 2006.217.08:08:31.50#ibcon#end of sib2, iclass 21, count 0 2006.217.08:08:31.50#ibcon#*mode == 0, iclass 21, count 0 2006.217.08:08:31.50#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.217.08:08:31.50#ibcon#[27=USB\r\n] 2006.217.08:08:31.50#ibcon#*before write, iclass 21, count 0 2006.217.08:08:31.50#ibcon#enter sib2, iclass 21, count 0 2006.217.08:08:31.50#ibcon#flushed, iclass 21, count 0 2006.217.08:08:31.50#ibcon#about to write, iclass 21, count 0 2006.217.08:08:31.50#ibcon#wrote, iclass 21, count 0 2006.217.08:08:31.50#ibcon#about to read 3, iclass 21, count 0 2006.217.08:08:31.53#ibcon#read 3, iclass 21, count 0 2006.217.08:08:31.53#ibcon#about to read 4, iclass 21, count 0 2006.217.08:08:31.53#ibcon#read 4, iclass 21, count 0 2006.217.08:08:31.53#ibcon#about to read 5, iclass 21, count 0 2006.217.08:08:31.53#ibcon#read 5, iclass 21, count 0 2006.217.08:08:31.53#ibcon#about to read 6, iclass 21, count 0 2006.217.08:08:31.53#ibcon#read 6, iclass 21, count 0 2006.217.08:08:31.53#ibcon#end of sib2, iclass 21, count 0 2006.217.08:08:31.53#ibcon#*after write, iclass 21, count 0 2006.217.08:08:31.53#ibcon#*before return 0, iclass 21, count 0 2006.217.08:08:31.53#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.217.08:08:31.53#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.217.08:08:31.53#ibcon#about to clear, iclass 21 cls_cnt 0 2006.217.08:08:31.53#ibcon#cleared, iclass 21 cls_cnt 0 2006.217.08:08:31.53$vc4f8/vblo=4,712.99 2006.217.08:08:31.53#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.217.08:08:31.53#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.217.08:08:31.53#ibcon#ireg 17 cls_cnt 0 2006.217.08:08:31.53#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.217.08:08:31.53#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.217.08:08:31.53#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.217.08:08:31.53#ibcon#enter wrdev, iclass 23, count 0 2006.217.08:08:31.53#ibcon#first serial, iclass 23, count 0 2006.217.08:08:31.53#ibcon#enter sib2, iclass 23, count 0 2006.217.08:08:31.53#ibcon#flushed, iclass 23, count 0 2006.217.08:08:31.53#ibcon#about to write, iclass 23, count 0 2006.217.08:08:31.53#ibcon#wrote, iclass 23, count 0 2006.217.08:08:31.53#ibcon#about to read 3, iclass 23, count 0 2006.217.08:08:31.55#ibcon#read 3, iclass 23, count 0 2006.217.08:08:31.55#ibcon#about to read 4, iclass 23, count 0 2006.217.08:08:31.55#ibcon#read 4, iclass 23, count 0 2006.217.08:08:31.55#ibcon#about to read 5, iclass 23, count 0 2006.217.08:08:31.55#ibcon#read 5, iclass 23, count 0 2006.217.08:08:31.55#ibcon#about to read 6, iclass 23, count 0 2006.217.08:08:31.55#ibcon#read 6, iclass 23, count 0 2006.217.08:08:31.55#ibcon#end of sib2, iclass 23, count 0 2006.217.08:08:31.55#ibcon#*mode == 0, iclass 23, count 0 2006.217.08:08:31.55#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.217.08:08:31.55#ibcon#[28=FRQ=04,712.99\r\n] 2006.217.08:08:31.55#ibcon#*before write, iclass 23, count 0 2006.217.08:08:31.55#ibcon#enter sib2, iclass 23, count 0 2006.217.08:08:31.55#ibcon#flushed, iclass 23, count 0 2006.217.08:08:31.55#ibcon#about to write, iclass 23, count 0 2006.217.08:08:31.55#ibcon#wrote, iclass 23, count 0 2006.217.08:08:31.55#ibcon#about to read 3, iclass 23, count 0 2006.217.08:08:31.59#ibcon#read 3, iclass 23, count 0 2006.217.08:08:31.59#ibcon#about to read 4, iclass 23, count 0 2006.217.08:08:31.59#ibcon#read 4, iclass 23, count 0 2006.217.08:08:31.59#ibcon#about to read 5, iclass 23, count 0 2006.217.08:08:31.59#ibcon#read 5, iclass 23, count 0 2006.217.08:08:31.59#ibcon#about to read 6, iclass 23, count 0 2006.217.08:08:31.59#ibcon#read 6, iclass 23, count 0 2006.217.08:08:31.59#ibcon#end of sib2, iclass 23, count 0 2006.217.08:08:31.59#ibcon#*after write, iclass 23, count 0 2006.217.08:08:31.59#ibcon#*before return 0, iclass 23, count 0 2006.217.08:08:31.59#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.217.08:08:31.59#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.217.08:08:31.59#ibcon#about to clear, iclass 23 cls_cnt 0 2006.217.08:08:31.59#ibcon#cleared, iclass 23 cls_cnt 0 2006.217.08:08:31.59$vc4f8/vb=4,4 2006.217.08:08:31.59#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.217.08:08:31.59#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.217.08:08:31.59#ibcon#ireg 11 cls_cnt 2 2006.217.08:08:31.59#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.217.08:08:31.65#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.217.08:08:31.65#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.217.08:08:31.65#ibcon#enter wrdev, iclass 25, count 2 2006.217.08:08:31.65#ibcon#first serial, iclass 25, count 2 2006.217.08:08:31.65#ibcon#enter sib2, iclass 25, count 2 2006.217.08:08:31.65#ibcon#flushed, iclass 25, count 2 2006.217.08:08:31.65#ibcon#about to write, iclass 25, count 2 2006.217.08:08:31.65#ibcon#wrote, iclass 25, count 2 2006.217.08:08:31.65#ibcon#about to read 3, iclass 25, count 2 2006.217.08:08:31.67#ibcon#read 3, iclass 25, count 2 2006.217.08:08:31.67#ibcon#about to read 4, iclass 25, count 2 2006.217.08:08:31.67#ibcon#read 4, iclass 25, count 2 2006.217.08:08:31.67#ibcon#about to read 5, iclass 25, count 2 2006.217.08:08:31.67#ibcon#read 5, iclass 25, count 2 2006.217.08:08:31.67#ibcon#about to read 6, iclass 25, count 2 2006.217.08:08:31.67#ibcon#read 6, iclass 25, count 2 2006.217.08:08:31.67#ibcon#end of sib2, iclass 25, count 2 2006.217.08:08:31.67#ibcon#*mode == 0, iclass 25, count 2 2006.217.08:08:31.67#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.217.08:08:31.67#ibcon#[27=AT04-04\r\n] 2006.217.08:08:31.67#ibcon#*before write, iclass 25, count 2 2006.217.08:08:31.67#ibcon#enter sib2, iclass 25, count 2 2006.217.08:08:31.67#ibcon#flushed, iclass 25, count 2 2006.217.08:08:31.67#ibcon#about to write, iclass 25, count 2 2006.217.08:08:31.67#ibcon#wrote, iclass 25, count 2 2006.217.08:08:31.67#ibcon#about to read 3, iclass 25, count 2 2006.217.08:08:31.70#ibcon#read 3, iclass 25, count 2 2006.217.08:08:31.70#ibcon#about to read 4, iclass 25, count 2 2006.217.08:08:31.70#ibcon#read 4, iclass 25, count 2 2006.217.08:08:31.70#ibcon#about to read 5, iclass 25, count 2 2006.217.08:08:31.70#ibcon#read 5, iclass 25, count 2 2006.217.08:08:31.70#ibcon#about to read 6, iclass 25, count 2 2006.217.08:08:31.70#ibcon#read 6, iclass 25, count 2 2006.217.08:08:31.70#ibcon#end of sib2, iclass 25, count 2 2006.217.08:08:31.70#ibcon#*after write, iclass 25, count 2 2006.217.08:08:31.70#ibcon#*before return 0, iclass 25, count 2 2006.217.08:08:31.70#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.217.08:08:31.70#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.217.08:08:31.70#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.217.08:08:31.70#ibcon#ireg 7 cls_cnt 0 2006.217.08:08:31.70#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.217.08:08:31.82#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.217.08:08:31.82#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.217.08:08:31.82#ibcon#enter wrdev, iclass 25, count 0 2006.217.08:08:31.82#ibcon#first serial, iclass 25, count 0 2006.217.08:08:31.82#ibcon#enter sib2, iclass 25, count 0 2006.217.08:08:31.82#ibcon#flushed, iclass 25, count 0 2006.217.08:08:31.82#ibcon#about to write, iclass 25, count 0 2006.217.08:08:31.82#ibcon#wrote, iclass 25, count 0 2006.217.08:08:31.82#ibcon#about to read 3, iclass 25, count 0 2006.217.08:08:31.84#ibcon#read 3, iclass 25, count 0 2006.217.08:08:31.84#ibcon#about to read 4, iclass 25, count 0 2006.217.08:08:31.84#ibcon#read 4, iclass 25, count 0 2006.217.08:08:31.84#ibcon#about to read 5, iclass 25, count 0 2006.217.08:08:31.84#ibcon#read 5, iclass 25, count 0 2006.217.08:08:31.84#ibcon#about to read 6, iclass 25, count 0 2006.217.08:08:31.84#ibcon#read 6, iclass 25, count 0 2006.217.08:08:31.84#ibcon#end of sib2, iclass 25, count 0 2006.217.08:08:31.84#ibcon#*mode == 0, iclass 25, count 0 2006.217.08:08:31.84#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.217.08:08:31.84#ibcon#[27=USB\r\n] 2006.217.08:08:31.84#ibcon#*before write, iclass 25, count 0 2006.217.08:08:31.84#ibcon#enter sib2, iclass 25, count 0 2006.217.08:08:31.84#ibcon#flushed, iclass 25, count 0 2006.217.08:08:31.84#ibcon#about to write, iclass 25, count 0 2006.217.08:08:31.84#ibcon#wrote, iclass 25, count 0 2006.217.08:08:31.84#ibcon#about to read 3, iclass 25, count 0 2006.217.08:08:31.87#ibcon#read 3, iclass 25, count 0 2006.217.08:08:31.87#ibcon#about to read 4, iclass 25, count 0 2006.217.08:08:31.87#ibcon#read 4, iclass 25, count 0 2006.217.08:08:31.87#ibcon#about to read 5, iclass 25, count 0 2006.217.08:08:31.87#ibcon#read 5, iclass 25, count 0 2006.217.08:08:31.87#ibcon#about to read 6, iclass 25, count 0 2006.217.08:08:31.87#ibcon#read 6, iclass 25, count 0 2006.217.08:08:31.87#ibcon#end of sib2, iclass 25, count 0 2006.217.08:08:31.87#ibcon#*after write, iclass 25, count 0 2006.217.08:08:31.87#ibcon#*before return 0, iclass 25, count 0 2006.217.08:08:31.87#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.217.08:08:31.87#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.217.08:08:31.87#ibcon#about to clear, iclass 25 cls_cnt 0 2006.217.08:08:31.87#ibcon#cleared, iclass 25 cls_cnt 0 2006.217.08:08:31.87$vc4f8/vblo=5,744.99 2006.217.08:08:31.87#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.217.08:08:31.87#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.217.08:08:31.87#ibcon#ireg 17 cls_cnt 0 2006.217.08:08:31.87#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.217.08:08:31.87#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.217.08:08:31.87#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.217.08:08:31.87#ibcon#enter wrdev, iclass 27, count 0 2006.217.08:08:31.87#ibcon#first serial, iclass 27, count 0 2006.217.08:08:31.87#ibcon#enter sib2, iclass 27, count 0 2006.217.08:08:31.87#ibcon#flushed, iclass 27, count 0 2006.217.08:08:31.87#ibcon#about to write, iclass 27, count 0 2006.217.08:08:31.87#ibcon#wrote, iclass 27, count 0 2006.217.08:08:31.87#ibcon#about to read 3, iclass 27, count 0 2006.217.08:08:31.89#ibcon#read 3, iclass 27, count 0 2006.217.08:08:31.89#ibcon#about to read 4, iclass 27, count 0 2006.217.08:08:31.89#ibcon#read 4, iclass 27, count 0 2006.217.08:08:31.89#ibcon#about to read 5, iclass 27, count 0 2006.217.08:08:31.89#ibcon#read 5, iclass 27, count 0 2006.217.08:08:31.89#ibcon#about to read 6, iclass 27, count 0 2006.217.08:08:31.89#ibcon#read 6, iclass 27, count 0 2006.217.08:08:31.89#ibcon#end of sib2, iclass 27, count 0 2006.217.08:08:31.89#ibcon#*mode == 0, iclass 27, count 0 2006.217.08:08:31.89#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.217.08:08:31.89#ibcon#[28=FRQ=05,744.99\r\n] 2006.217.08:08:31.89#ibcon#*before write, iclass 27, count 0 2006.217.08:08:31.89#ibcon#enter sib2, iclass 27, count 0 2006.217.08:08:31.89#ibcon#flushed, iclass 27, count 0 2006.217.08:08:31.89#ibcon#about to write, iclass 27, count 0 2006.217.08:08:31.89#ibcon#wrote, iclass 27, count 0 2006.217.08:08:31.89#ibcon#about to read 3, iclass 27, count 0 2006.217.08:08:31.93#ibcon#read 3, iclass 27, count 0 2006.217.08:08:31.93#ibcon#about to read 4, iclass 27, count 0 2006.217.08:08:31.93#ibcon#read 4, iclass 27, count 0 2006.217.08:08:31.93#ibcon#about to read 5, iclass 27, count 0 2006.217.08:08:31.93#ibcon#read 5, iclass 27, count 0 2006.217.08:08:31.93#ibcon#about to read 6, iclass 27, count 0 2006.217.08:08:31.93#ibcon#read 6, iclass 27, count 0 2006.217.08:08:31.93#ibcon#end of sib2, iclass 27, count 0 2006.217.08:08:31.93#ibcon#*after write, iclass 27, count 0 2006.217.08:08:31.93#ibcon#*before return 0, iclass 27, count 0 2006.217.08:08:31.93#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.217.08:08:31.93#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.217.08:08:31.93#ibcon#about to clear, iclass 27 cls_cnt 0 2006.217.08:08:31.93#ibcon#cleared, iclass 27 cls_cnt 0 2006.217.08:08:31.93$vc4f8/vb=5,4 2006.217.08:08:31.93#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.217.08:08:31.93#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.217.08:08:31.93#ibcon#ireg 11 cls_cnt 2 2006.217.08:08:31.93#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.217.08:08:31.99#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.217.08:08:31.99#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.217.08:08:31.99#ibcon#enter wrdev, iclass 29, count 2 2006.217.08:08:31.99#ibcon#first serial, iclass 29, count 2 2006.217.08:08:31.99#ibcon#enter sib2, iclass 29, count 2 2006.217.08:08:31.99#ibcon#flushed, iclass 29, count 2 2006.217.08:08:31.99#ibcon#about to write, iclass 29, count 2 2006.217.08:08:31.99#ibcon#wrote, iclass 29, count 2 2006.217.08:08:31.99#ibcon#about to read 3, iclass 29, count 2 2006.217.08:08:32.01#ibcon#read 3, iclass 29, count 2 2006.217.08:08:32.01#ibcon#about to read 4, iclass 29, count 2 2006.217.08:08:32.01#ibcon#read 4, iclass 29, count 2 2006.217.08:08:32.01#ibcon#about to read 5, iclass 29, count 2 2006.217.08:08:32.01#ibcon#read 5, iclass 29, count 2 2006.217.08:08:32.01#ibcon#about to read 6, iclass 29, count 2 2006.217.08:08:32.01#ibcon#read 6, iclass 29, count 2 2006.217.08:08:32.01#ibcon#end of sib2, iclass 29, count 2 2006.217.08:08:32.01#ibcon#*mode == 0, iclass 29, count 2 2006.217.08:08:32.01#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.217.08:08:32.01#ibcon#[27=AT05-04\r\n] 2006.217.08:08:32.01#ibcon#*before write, iclass 29, count 2 2006.217.08:08:32.01#ibcon#enter sib2, iclass 29, count 2 2006.217.08:08:32.01#ibcon#flushed, iclass 29, count 2 2006.217.08:08:32.01#ibcon#about to write, iclass 29, count 2 2006.217.08:08:32.01#ibcon#wrote, iclass 29, count 2 2006.217.08:08:32.01#ibcon#about to read 3, iclass 29, count 2 2006.217.08:08:32.04#ibcon#read 3, iclass 29, count 2 2006.217.08:08:32.04#ibcon#about to read 4, iclass 29, count 2 2006.217.08:08:32.04#ibcon#read 4, iclass 29, count 2 2006.217.08:08:32.04#ibcon#about to read 5, iclass 29, count 2 2006.217.08:08:32.04#ibcon#read 5, iclass 29, count 2 2006.217.08:08:32.04#ibcon#about to read 6, iclass 29, count 2 2006.217.08:08:32.04#ibcon#read 6, iclass 29, count 2 2006.217.08:08:32.04#ibcon#end of sib2, iclass 29, count 2 2006.217.08:08:32.04#ibcon#*after write, iclass 29, count 2 2006.217.08:08:32.04#ibcon#*before return 0, iclass 29, count 2 2006.217.08:08:32.04#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.217.08:08:32.04#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.217.08:08:32.04#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.217.08:08:32.04#ibcon#ireg 7 cls_cnt 0 2006.217.08:08:32.04#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.217.08:08:32.16#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.217.08:08:32.16#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.217.08:08:32.16#ibcon#enter wrdev, iclass 29, count 0 2006.217.08:08:32.16#ibcon#first serial, iclass 29, count 0 2006.217.08:08:32.16#ibcon#enter sib2, iclass 29, count 0 2006.217.08:08:32.16#ibcon#flushed, iclass 29, count 0 2006.217.08:08:32.16#ibcon#about to write, iclass 29, count 0 2006.217.08:08:32.16#ibcon#wrote, iclass 29, count 0 2006.217.08:08:32.16#ibcon#about to read 3, iclass 29, count 0 2006.217.08:08:32.18#ibcon#read 3, iclass 29, count 0 2006.217.08:08:32.18#ibcon#about to read 4, iclass 29, count 0 2006.217.08:08:32.18#ibcon#read 4, iclass 29, count 0 2006.217.08:08:32.18#ibcon#about to read 5, iclass 29, count 0 2006.217.08:08:32.18#ibcon#read 5, iclass 29, count 0 2006.217.08:08:32.18#ibcon#about to read 6, iclass 29, count 0 2006.217.08:08:32.18#ibcon#read 6, iclass 29, count 0 2006.217.08:08:32.18#ibcon#end of sib2, iclass 29, count 0 2006.217.08:08:32.18#ibcon#*mode == 0, iclass 29, count 0 2006.217.08:08:32.18#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.217.08:08:32.18#ibcon#[27=USB\r\n] 2006.217.08:08:32.18#ibcon#*before write, iclass 29, count 0 2006.217.08:08:32.18#ibcon#enter sib2, iclass 29, count 0 2006.217.08:08:32.18#ibcon#flushed, iclass 29, count 0 2006.217.08:08:32.18#ibcon#about to write, iclass 29, count 0 2006.217.08:08:32.18#ibcon#wrote, iclass 29, count 0 2006.217.08:08:32.18#ibcon#about to read 3, iclass 29, count 0 2006.217.08:08:32.21#ibcon#read 3, iclass 29, count 0 2006.217.08:08:32.21#ibcon#about to read 4, iclass 29, count 0 2006.217.08:08:32.21#ibcon#read 4, iclass 29, count 0 2006.217.08:08:32.21#ibcon#about to read 5, iclass 29, count 0 2006.217.08:08:32.21#ibcon#read 5, iclass 29, count 0 2006.217.08:08:32.21#ibcon#about to read 6, iclass 29, count 0 2006.217.08:08:32.21#ibcon#read 6, iclass 29, count 0 2006.217.08:08:32.21#ibcon#end of sib2, iclass 29, count 0 2006.217.08:08:32.21#ibcon#*after write, iclass 29, count 0 2006.217.08:08:32.21#ibcon#*before return 0, iclass 29, count 0 2006.217.08:08:32.21#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.217.08:08:32.21#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.217.08:08:32.21#ibcon#about to clear, iclass 29 cls_cnt 0 2006.217.08:08:32.21#ibcon#cleared, iclass 29 cls_cnt 0 2006.217.08:08:32.21$vc4f8/vblo=6,752.99 2006.217.08:08:32.21#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.217.08:08:32.21#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.217.08:08:32.21#ibcon#ireg 17 cls_cnt 0 2006.217.08:08:32.21#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.217.08:08:32.21#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.217.08:08:32.21#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.217.08:08:32.21#ibcon#enter wrdev, iclass 31, count 0 2006.217.08:08:32.21#ibcon#first serial, iclass 31, count 0 2006.217.08:08:32.21#ibcon#enter sib2, iclass 31, count 0 2006.217.08:08:32.21#ibcon#flushed, iclass 31, count 0 2006.217.08:08:32.21#ibcon#about to write, iclass 31, count 0 2006.217.08:08:32.21#ibcon#wrote, iclass 31, count 0 2006.217.08:08:32.21#ibcon#about to read 3, iclass 31, count 0 2006.217.08:08:32.23#ibcon#read 3, iclass 31, count 0 2006.217.08:08:32.23#ibcon#about to read 4, iclass 31, count 0 2006.217.08:08:32.23#ibcon#read 4, iclass 31, count 0 2006.217.08:08:32.23#ibcon#about to read 5, iclass 31, count 0 2006.217.08:08:32.23#ibcon#read 5, iclass 31, count 0 2006.217.08:08:32.23#ibcon#about to read 6, iclass 31, count 0 2006.217.08:08:32.23#ibcon#read 6, iclass 31, count 0 2006.217.08:08:32.23#ibcon#end of sib2, iclass 31, count 0 2006.217.08:08:32.23#ibcon#*mode == 0, iclass 31, count 0 2006.217.08:08:32.23#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.217.08:08:32.23#ibcon#[28=FRQ=06,752.99\r\n] 2006.217.08:08:32.23#ibcon#*before write, iclass 31, count 0 2006.217.08:08:32.23#ibcon#enter sib2, iclass 31, count 0 2006.217.08:08:32.23#ibcon#flushed, iclass 31, count 0 2006.217.08:08:32.23#ibcon#about to write, iclass 31, count 0 2006.217.08:08:32.23#ibcon#wrote, iclass 31, count 0 2006.217.08:08:32.23#ibcon#about to read 3, iclass 31, count 0 2006.217.08:08:32.27#ibcon#read 3, iclass 31, count 0 2006.217.08:08:32.27#ibcon#about to read 4, iclass 31, count 0 2006.217.08:08:32.27#ibcon#read 4, iclass 31, count 0 2006.217.08:08:32.27#ibcon#about to read 5, iclass 31, count 0 2006.217.08:08:32.27#ibcon#read 5, iclass 31, count 0 2006.217.08:08:32.27#ibcon#about to read 6, iclass 31, count 0 2006.217.08:08:32.27#ibcon#read 6, iclass 31, count 0 2006.217.08:08:32.27#ibcon#end of sib2, iclass 31, count 0 2006.217.08:08:32.27#ibcon#*after write, iclass 31, count 0 2006.217.08:08:32.27#ibcon#*before return 0, iclass 31, count 0 2006.217.08:08:32.27#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.217.08:08:32.27#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.217.08:08:32.27#ibcon#about to clear, iclass 31 cls_cnt 0 2006.217.08:08:32.27#ibcon#cleared, iclass 31 cls_cnt 0 2006.217.08:08:32.27$vc4f8/vb=6,4 2006.217.08:08:32.27#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.217.08:08:32.27#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.217.08:08:32.27#ibcon#ireg 11 cls_cnt 2 2006.217.08:08:32.27#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.217.08:08:32.33#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.217.08:08:32.33#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.217.08:08:32.33#ibcon#enter wrdev, iclass 33, count 2 2006.217.08:08:32.33#ibcon#first serial, iclass 33, count 2 2006.217.08:08:32.33#ibcon#enter sib2, iclass 33, count 2 2006.217.08:08:32.33#ibcon#flushed, iclass 33, count 2 2006.217.08:08:32.33#ibcon#about to write, iclass 33, count 2 2006.217.08:08:32.33#ibcon#wrote, iclass 33, count 2 2006.217.08:08:32.33#ibcon#about to read 3, iclass 33, count 2 2006.217.08:08:32.35#ibcon#read 3, iclass 33, count 2 2006.217.08:08:32.35#ibcon#about to read 4, iclass 33, count 2 2006.217.08:08:32.35#ibcon#read 4, iclass 33, count 2 2006.217.08:08:32.35#ibcon#about to read 5, iclass 33, count 2 2006.217.08:08:32.35#ibcon#read 5, iclass 33, count 2 2006.217.08:08:32.35#ibcon#about to read 6, iclass 33, count 2 2006.217.08:08:32.35#ibcon#read 6, iclass 33, count 2 2006.217.08:08:32.35#ibcon#end of sib2, iclass 33, count 2 2006.217.08:08:32.35#ibcon#*mode == 0, iclass 33, count 2 2006.217.08:08:32.35#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.217.08:08:32.35#ibcon#[27=AT06-04\r\n] 2006.217.08:08:32.35#ibcon#*before write, iclass 33, count 2 2006.217.08:08:32.35#ibcon#enter sib2, iclass 33, count 2 2006.217.08:08:32.35#ibcon#flushed, iclass 33, count 2 2006.217.08:08:32.35#ibcon#about to write, iclass 33, count 2 2006.217.08:08:32.35#ibcon#wrote, iclass 33, count 2 2006.217.08:08:32.35#ibcon#about to read 3, iclass 33, count 2 2006.217.08:08:32.38#ibcon#read 3, iclass 33, count 2 2006.217.08:08:32.38#ibcon#about to read 4, iclass 33, count 2 2006.217.08:08:32.38#ibcon#read 4, iclass 33, count 2 2006.217.08:08:32.38#ibcon#about to read 5, iclass 33, count 2 2006.217.08:08:32.38#ibcon#read 5, iclass 33, count 2 2006.217.08:08:32.38#ibcon#about to read 6, iclass 33, count 2 2006.217.08:08:32.38#ibcon#read 6, iclass 33, count 2 2006.217.08:08:32.38#ibcon#end of sib2, iclass 33, count 2 2006.217.08:08:32.38#ibcon#*after write, iclass 33, count 2 2006.217.08:08:32.38#ibcon#*before return 0, iclass 33, count 2 2006.217.08:08:32.38#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.217.08:08:32.38#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.217.08:08:32.38#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.217.08:08:32.38#ibcon#ireg 7 cls_cnt 0 2006.217.08:08:32.38#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.217.08:08:32.50#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.217.08:08:32.50#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.217.08:08:32.50#ibcon#enter wrdev, iclass 33, count 0 2006.217.08:08:32.50#ibcon#first serial, iclass 33, count 0 2006.217.08:08:32.50#ibcon#enter sib2, iclass 33, count 0 2006.217.08:08:32.50#ibcon#flushed, iclass 33, count 0 2006.217.08:08:32.50#ibcon#about to write, iclass 33, count 0 2006.217.08:08:32.50#ibcon#wrote, iclass 33, count 0 2006.217.08:08:32.50#ibcon#about to read 3, iclass 33, count 0 2006.217.08:08:32.52#ibcon#read 3, iclass 33, count 0 2006.217.08:08:32.52#ibcon#about to read 4, iclass 33, count 0 2006.217.08:08:32.52#ibcon#read 4, iclass 33, count 0 2006.217.08:08:32.52#ibcon#about to read 5, iclass 33, count 0 2006.217.08:08:32.52#ibcon#read 5, iclass 33, count 0 2006.217.08:08:32.52#ibcon#about to read 6, iclass 33, count 0 2006.217.08:08:32.52#ibcon#read 6, iclass 33, count 0 2006.217.08:08:32.52#ibcon#end of sib2, iclass 33, count 0 2006.217.08:08:32.52#ibcon#*mode == 0, iclass 33, count 0 2006.217.08:08:32.52#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.217.08:08:32.52#ibcon#[27=USB\r\n] 2006.217.08:08:32.52#ibcon#*before write, iclass 33, count 0 2006.217.08:08:32.52#ibcon#enter sib2, iclass 33, count 0 2006.217.08:08:32.52#ibcon#flushed, iclass 33, count 0 2006.217.08:08:32.52#ibcon#about to write, iclass 33, count 0 2006.217.08:08:32.52#ibcon#wrote, iclass 33, count 0 2006.217.08:08:32.52#ibcon#about to read 3, iclass 33, count 0 2006.217.08:08:32.55#ibcon#read 3, iclass 33, count 0 2006.217.08:08:32.55#ibcon#about to read 4, iclass 33, count 0 2006.217.08:08:32.55#ibcon#read 4, iclass 33, count 0 2006.217.08:08:32.55#ibcon#about to read 5, iclass 33, count 0 2006.217.08:08:32.55#ibcon#read 5, iclass 33, count 0 2006.217.08:08:32.55#ibcon#about to read 6, iclass 33, count 0 2006.217.08:08:32.55#ibcon#read 6, iclass 33, count 0 2006.217.08:08:32.55#ibcon#end of sib2, iclass 33, count 0 2006.217.08:08:32.55#ibcon#*after write, iclass 33, count 0 2006.217.08:08:32.55#ibcon#*before return 0, iclass 33, count 0 2006.217.08:08:32.55#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.217.08:08:32.55#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.217.08:08:32.55#ibcon#about to clear, iclass 33 cls_cnt 0 2006.217.08:08:32.55#ibcon#cleared, iclass 33 cls_cnt 0 2006.217.08:08:32.55$vc4f8/vabw=wide 2006.217.08:08:32.55#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.217.08:08:32.55#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.217.08:08:32.55#ibcon#ireg 8 cls_cnt 0 2006.217.08:08:32.55#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.217.08:08:32.55#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.217.08:08:32.55#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.217.08:08:32.55#ibcon#enter wrdev, iclass 35, count 0 2006.217.08:08:32.55#ibcon#first serial, iclass 35, count 0 2006.217.08:08:32.55#ibcon#enter sib2, iclass 35, count 0 2006.217.08:08:32.55#ibcon#flushed, iclass 35, count 0 2006.217.08:08:32.55#ibcon#about to write, iclass 35, count 0 2006.217.08:08:32.55#ibcon#wrote, iclass 35, count 0 2006.217.08:08:32.55#ibcon#about to read 3, iclass 35, count 0 2006.217.08:08:32.57#ibcon#read 3, iclass 35, count 0 2006.217.08:08:32.57#ibcon#about to read 4, iclass 35, count 0 2006.217.08:08:32.57#ibcon#read 4, iclass 35, count 0 2006.217.08:08:32.57#ibcon#about to read 5, iclass 35, count 0 2006.217.08:08:32.57#ibcon#read 5, iclass 35, count 0 2006.217.08:08:32.57#ibcon#about to read 6, iclass 35, count 0 2006.217.08:08:32.57#ibcon#read 6, iclass 35, count 0 2006.217.08:08:32.57#ibcon#end of sib2, iclass 35, count 0 2006.217.08:08:32.57#ibcon#*mode == 0, iclass 35, count 0 2006.217.08:08:32.57#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.217.08:08:32.57#ibcon#[25=BW32\r\n] 2006.217.08:08:32.57#ibcon#*before write, iclass 35, count 0 2006.217.08:08:32.57#ibcon#enter sib2, iclass 35, count 0 2006.217.08:08:32.57#ibcon#flushed, iclass 35, count 0 2006.217.08:08:32.57#ibcon#about to write, iclass 35, count 0 2006.217.08:08:32.57#ibcon#wrote, iclass 35, count 0 2006.217.08:08:32.57#ibcon#about to read 3, iclass 35, count 0 2006.217.08:08:32.60#ibcon#read 3, iclass 35, count 0 2006.217.08:08:32.60#ibcon#about to read 4, iclass 35, count 0 2006.217.08:08:32.60#ibcon#read 4, iclass 35, count 0 2006.217.08:08:32.60#ibcon#about to read 5, iclass 35, count 0 2006.217.08:08:32.60#ibcon#read 5, iclass 35, count 0 2006.217.08:08:32.60#ibcon#about to read 6, iclass 35, count 0 2006.217.08:08:32.60#ibcon#read 6, iclass 35, count 0 2006.217.08:08:32.60#ibcon#end of sib2, iclass 35, count 0 2006.217.08:08:32.60#ibcon#*after write, iclass 35, count 0 2006.217.08:08:32.60#ibcon#*before return 0, iclass 35, count 0 2006.217.08:08:32.60#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.217.08:08:32.60#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.217.08:08:32.60#ibcon#about to clear, iclass 35 cls_cnt 0 2006.217.08:08:32.60#ibcon#cleared, iclass 35 cls_cnt 0 2006.217.08:08:32.60$vc4f8/vbbw=wide 2006.217.08:08:32.60#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.217.08:08:32.60#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.217.08:08:32.60#ibcon#ireg 8 cls_cnt 0 2006.217.08:08:32.60#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.217.08:08:32.67#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.217.08:08:32.67#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.217.08:08:32.67#ibcon#enter wrdev, iclass 37, count 0 2006.217.08:08:32.67#ibcon#first serial, iclass 37, count 0 2006.217.08:08:32.67#ibcon#enter sib2, iclass 37, count 0 2006.217.08:08:32.67#ibcon#flushed, iclass 37, count 0 2006.217.08:08:32.67#ibcon#about to write, iclass 37, count 0 2006.217.08:08:32.67#ibcon#wrote, iclass 37, count 0 2006.217.08:08:32.67#ibcon#about to read 3, iclass 37, count 0 2006.217.08:08:32.69#ibcon#read 3, iclass 37, count 0 2006.217.08:08:32.69#ibcon#about to read 4, iclass 37, count 0 2006.217.08:08:32.69#ibcon#read 4, iclass 37, count 0 2006.217.08:08:32.69#ibcon#about to read 5, iclass 37, count 0 2006.217.08:08:32.69#ibcon#read 5, iclass 37, count 0 2006.217.08:08:32.69#ibcon#about to read 6, iclass 37, count 0 2006.217.08:08:32.69#ibcon#read 6, iclass 37, count 0 2006.217.08:08:32.69#ibcon#end of sib2, iclass 37, count 0 2006.217.08:08:32.69#ibcon#*mode == 0, iclass 37, count 0 2006.217.08:08:32.69#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.217.08:08:32.69#ibcon#[27=BW32\r\n] 2006.217.08:08:32.69#ibcon#*before write, iclass 37, count 0 2006.217.08:08:32.69#ibcon#enter sib2, iclass 37, count 0 2006.217.08:08:32.69#ibcon#flushed, iclass 37, count 0 2006.217.08:08:32.69#ibcon#about to write, iclass 37, count 0 2006.217.08:08:32.69#ibcon#wrote, iclass 37, count 0 2006.217.08:08:32.69#ibcon#about to read 3, iclass 37, count 0 2006.217.08:08:32.72#ibcon#read 3, iclass 37, count 0 2006.217.08:08:32.72#ibcon#about to read 4, iclass 37, count 0 2006.217.08:08:32.72#ibcon#read 4, iclass 37, count 0 2006.217.08:08:32.72#ibcon#about to read 5, iclass 37, count 0 2006.217.08:08:32.72#ibcon#read 5, iclass 37, count 0 2006.217.08:08:32.72#ibcon#about to read 6, iclass 37, count 0 2006.217.08:08:32.72#ibcon#read 6, iclass 37, count 0 2006.217.08:08:32.72#ibcon#end of sib2, iclass 37, count 0 2006.217.08:08:32.72#ibcon#*after write, iclass 37, count 0 2006.217.08:08:32.72#ibcon#*before return 0, iclass 37, count 0 2006.217.08:08:32.72#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.217.08:08:32.72#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.217.08:08:32.72#ibcon#about to clear, iclass 37 cls_cnt 0 2006.217.08:08:32.72#ibcon#cleared, iclass 37 cls_cnt 0 2006.217.08:08:32.72$4f8m12a/ifd4f 2006.217.08:08:32.72$ifd4f/lo= 2006.217.08:08:32.72$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.217.08:08:32.72$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.217.08:08:32.72$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.217.08:08:32.72$ifd4f/patch= 2006.217.08:08:32.72$ifd4f/patch=lo1,a1,a2,a3,a4 2006.217.08:08:32.72$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.217.08:08:32.72$ifd4f/patch=lo3,a5,a6,a7,a8 2006.217.08:08:32.72$4f8m12a/"form=m,16.000,1:2 2006.217.08:08:32.72$4f8m12a/"tpicd 2006.217.08:08:32.72$4f8m12a/echo=off 2006.217.08:08:32.72$4f8m12a/xlog=off 2006.217.08:08:32.72:!2006.217.08:09:00 2006.217.08:08:46.14#trakl#Source acquired 2006.217.08:08:48.14#flagr#flagr/antenna,acquired 2006.217.08:09:00.00:preob 2006.217.08:09:01.14/onsource/TRACKING 2006.217.08:09:01.14:!2006.217.08:09:10 2006.217.08:09:10.00:data_valid=on 2006.217.08:09:10.00:midob 2006.217.08:09:10.14/onsource/TRACKING 2006.217.08:09:10.14/wx/30.71,1008.6,64 2006.217.08:09:10.35/cable/+6.3870E-03 2006.217.08:09:11.44/va/01,05,usb,yes,33,35 2006.217.08:09:11.44/va/02,04,usb,yes,31,32 2006.217.08:09:11.44/va/03,04,usb,yes,29,29 2006.217.08:09:11.44/va/04,04,usb,yes,32,35 2006.217.08:09:11.44/va/05,07,usb,yes,34,36 2006.217.08:09:11.44/va/06,06,usb,yes,33,33 2006.217.08:09:11.44/va/07,06,usb,yes,34,34 2006.217.08:09:11.44/va/08,07,usb,yes,32,31 2006.217.08:09:11.67/valo/01,532.99,yes,locked 2006.217.08:09:11.67/valo/02,572.99,yes,locked 2006.217.08:09:11.67/valo/03,672.99,yes,locked 2006.217.08:09:11.67/valo/04,832.99,yes,locked 2006.217.08:09:11.67/valo/05,652.99,yes,locked 2006.217.08:09:11.67/valo/06,772.99,yes,locked 2006.217.08:09:11.67/valo/07,832.99,yes,locked 2006.217.08:09:11.67/valo/08,852.99,yes,locked 2006.217.08:09:12.76/vb/01,04,usb,yes,31,30 2006.217.08:09:12.76/vb/02,04,usb,yes,33,34 2006.217.08:09:12.76/vb/03,04,usb,yes,29,33 2006.217.08:09:12.76/vb/04,04,usb,yes,30,30 2006.217.08:09:12.76/vb/05,04,usb,yes,28,32 2006.217.08:09:12.76/vb/06,04,usb,yes,29,32 2006.217.08:09:12.76/vb/07,04,usb,yes,32,31 2006.217.08:09:12.76/vb/08,04,usb,yes,29,32 2006.217.08:09:13.00/vblo/01,632.99,yes,locked 2006.217.08:09:13.00/vblo/02,640.99,yes,locked 2006.217.08:09:13.00/vblo/03,656.99,yes,locked 2006.217.08:09:13.00/vblo/04,712.99,yes,locked 2006.217.08:09:13.00/vblo/05,744.99,yes,locked 2006.217.08:09:13.00/vblo/06,752.99,yes,locked 2006.217.08:09:13.00/vblo/07,734.99,yes,locked 2006.217.08:09:13.00/vblo/08,744.99,yes,locked 2006.217.08:09:13.15/vabw/8 2006.217.08:09:13.30/vbbw/8 2006.217.08:09:13.39/xfe/off,on,14.7 2006.217.08:09:13.77/ifatt/23,28,28,28 2006.217.08:09:14.07/fmout-gps/S +4.41E-07 2006.217.08:09:14.14:!2006.217.08:10:10 2006.217.08:10:10.01:data_valid=off 2006.217.08:10:10.01:postob 2006.217.08:10:10.19/cable/+6.3879E-03 2006.217.08:10:10.19/wx/30.69,1008.6,64 2006.217.08:10:11.07/fmout-gps/S +4.43E-07 2006.217.08:10:11.07:scan_name=217-0811,k06217,60 2006.217.08:10:11.07:source=0642+449,064632.03,445116.6,2000.0,ccw 2006.217.08:10:11.14#flagr#flagr/antenna,new-source 2006.217.08:10:12.14:checkk5 2006.217.08:10:12.51/chk_autoobs//k5ts1/ autoobs is running! 2006.217.08:10:12.88/chk_autoobs//k5ts2/ autoobs is running! 2006.217.08:10:13.26/chk_autoobs//k5ts3/ autoobs is running! 2006.217.08:10:13.63/chk_autoobs//k5ts4/ autoobs is running! 2006.217.08:10:14.00/chk_obsdata//k5ts1/T2170809??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.08:10:14.37/chk_obsdata//k5ts2/T2170809??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.08:10:14.74/chk_obsdata//k5ts3/T2170809??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.08:10:15.10/chk_obsdata//k5ts4/T2170809??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.08:10:15.80/k5log//k5ts1_log_newline 2006.217.08:10:16.49/k5log//k5ts2_log_newline 2006.217.08:10:17.17/k5log//k5ts3_log_newline 2006.217.08:10:17.86/k5log//k5ts4_log_newline 2006.217.08:10:17.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.217.08:10:17.89:4f8m12a=2 2006.217.08:10:17.89$4f8m12a/echo=on 2006.217.08:10:17.89$4f8m12a/pcalon 2006.217.08:10:17.89$pcalon/"no phase cal control is implemented here 2006.217.08:10:17.89$4f8m12a/"tpicd=stop 2006.217.08:10:17.89$4f8m12a/vc4f8 2006.217.08:10:17.89$vc4f8/valo=1,532.99 2006.217.08:10:17.89#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.217.08:10:17.89#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.217.08:10:17.89#ibcon#ireg 17 cls_cnt 0 2006.217.08:10:17.89#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.217.08:10:17.89#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.217.08:10:17.89#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.217.08:10:17.89#ibcon#enter wrdev, iclass 6, count 0 2006.217.08:10:17.89#ibcon#first serial, iclass 6, count 0 2006.217.08:10:17.89#ibcon#enter sib2, iclass 6, count 0 2006.217.08:10:17.89#ibcon#flushed, iclass 6, count 0 2006.217.08:10:17.89#ibcon#about to write, iclass 6, count 0 2006.217.08:10:17.89#ibcon#wrote, iclass 6, count 0 2006.217.08:10:17.89#ibcon#about to read 3, iclass 6, count 0 2006.217.08:10:17.91#ibcon#read 3, iclass 6, count 0 2006.217.08:10:17.91#ibcon#about to read 4, iclass 6, count 0 2006.217.08:10:17.91#ibcon#read 4, iclass 6, count 0 2006.217.08:10:17.91#ibcon#about to read 5, iclass 6, count 0 2006.217.08:10:17.91#ibcon#read 5, iclass 6, count 0 2006.217.08:10:17.91#ibcon#about to read 6, iclass 6, count 0 2006.217.08:10:17.91#ibcon#read 6, iclass 6, count 0 2006.217.08:10:17.91#ibcon#end of sib2, iclass 6, count 0 2006.217.08:10:17.91#ibcon#*mode == 0, iclass 6, count 0 2006.217.08:10:17.91#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.217.08:10:17.91#ibcon#[26=FRQ=01,532.99\r\n] 2006.217.08:10:17.91#ibcon#*before write, iclass 6, count 0 2006.217.08:10:17.91#ibcon#enter sib2, iclass 6, count 0 2006.217.08:10:17.91#ibcon#flushed, iclass 6, count 0 2006.217.08:10:17.91#ibcon#about to write, iclass 6, count 0 2006.217.08:10:17.91#ibcon#wrote, iclass 6, count 0 2006.217.08:10:17.91#ibcon#about to read 3, iclass 6, count 0 2006.217.08:10:17.96#ibcon#read 3, iclass 6, count 0 2006.217.08:10:17.96#ibcon#about to read 4, iclass 6, count 0 2006.217.08:10:17.96#ibcon#read 4, iclass 6, count 0 2006.217.08:10:17.96#ibcon#about to read 5, iclass 6, count 0 2006.217.08:10:17.96#ibcon#read 5, iclass 6, count 0 2006.217.08:10:17.96#ibcon#about to read 6, iclass 6, count 0 2006.217.08:10:17.96#ibcon#read 6, iclass 6, count 0 2006.217.08:10:17.96#ibcon#end of sib2, iclass 6, count 0 2006.217.08:10:17.96#ibcon#*after write, iclass 6, count 0 2006.217.08:10:17.96#ibcon#*before return 0, iclass 6, count 0 2006.217.08:10:17.96#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.217.08:10:17.96#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.217.08:10:17.96#ibcon#about to clear, iclass 6 cls_cnt 0 2006.217.08:10:17.96#ibcon#cleared, iclass 6 cls_cnt 0 2006.217.08:10:17.96$vc4f8/va=1,5 2006.217.08:10:17.96#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.217.08:10:17.96#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.217.08:10:17.96#ibcon#ireg 11 cls_cnt 2 2006.217.08:10:17.96#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.217.08:10:17.96#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.217.08:10:17.96#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.217.08:10:17.96#ibcon#enter wrdev, iclass 10, count 2 2006.217.08:10:17.96#ibcon#first serial, iclass 10, count 2 2006.217.08:10:17.96#ibcon#enter sib2, iclass 10, count 2 2006.217.08:10:17.96#ibcon#flushed, iclass 10, count 2 2006.217.08:10:17.96#ibcon#about to write, iclass 10, count 2 2006.217.08:10:17.96#ibcon#wrote, iclass 10, count 2 2006.217.08:10:17.96#ibcon#about to read 3, iclass 10, count 2 2006.217.08:10:17.98#ibcon#read 3, iclass 10, count 2 2006.217.08:10:17.98#ibcon#about to read 4, iclass 10, count 2 2006.217.08:10:17.98#ibcon#read 4, iclass 10, count 2 2006.217.08:10:17.98#ibcon#about to read 5, iclass 10, count 2 2006.217.08:10:17.98#ibcon#read 5, iclass 10, count 2 2006.217.08:10:17.98#ibcon#about to read 6, iclass 10, count 2 2006.217.08:10:17.98#ibcon#read 6, iclass 10, count 2 2006.217.08:10:17.98#ibcon#end of sib2, iclass 10, count 2 2006.217.08:10:17.98#ibcon#*mode == 0, iclass 10, count 2 2006.217.08:10:17.98#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.217.08:10:17.98#ibcon#[25=AT01-05\r\n] 2006.217.08:10:17.98#ibcon#*before write, iclass 10, count 2 2006.217.08:10:17.98#ibcon#enter sib2, iclass 10, count 2 2006.217.08:10:17.98#ibcon#flushed, iclass 10, count 2 2006.217.08:10:17.98#ibcon#about to write, iclass 10, count 2 2006.217.08:10:17.98#ibcon#wrote, iclass 10, count 2 2006.217.08:10:17.98#ibcon#about to read 3, iclass 10, count 2 2006.217.08:10:18.01#ibcon#read 3, iclass 10, count 2 2006.217.08:10:18.01#ibcon#about to read 4, iclass 10, count 2 2006.217.08:10:18.01#ibcon#read 4, iclass 10, count 2 2006.217.08:10:18.01#ibcon#about to read 5, iclass 10, count 2 2006.217.08:10:18.01#ibcon#read 5, iclass 10, count 2 2006.217.08:10:18.01#ibcon#about to read 6, iclass 10, count 2 2006.217.08:10:18.01#ibcon#read 6, iclass 10, count 2 2006.217.08:10:18.01#ibcon#end of sib2, iclass 10, count 2 2006.217.08:10:18.01#ibcon#*after write, iclass 10, count 2 2006.217.08:10:18.01#ibcon#*before return 0, iclass 10, count 2 2006.217.08:10:18.01#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.217.08:10:18.01#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.217.08:10:18.01#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.217.08:10:18.01#ibcon#ireg 7 cls_cnt 0 2006.217.08:10:18.01#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.217.08:10:18.13#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.217.08:10:18.13#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.217.08:10:18.13#ibcon#enter wrdev, iclass 10, count 0 2006.217.08:10:18.13#ibcon#first serial, iclass 10, count 0 2006.217.08:10:18.13#ibcon#enter sib2, iclass 10, count 0 2006.217.08:10:18.13#ibcon#flushed, iclass 10, count 0 2006.217.08:10:18.13#ibcon#about to write, iclass 10, count 0 2006.217.08:10:18.13#ibcon#wrote, iclass 10, count 0 2006.217.08:10:18.13#ibcon#about to read 3, iclass 10, count 0 2006.217.08:10:18.15#ibcon#read 3, iclass 10, count 0 2006.217.08:10:18.15#ibcon#about to read 4, iclass 10, count 0 2006.217.08:10:18.15#ibcon#read 4, iclass 10, count 0 2006.217.08:10:18.15#ibcon#about to read 5, iclass 10, count 0 2006.217.08:10:18.15#ibcon#read 5, iclass 10, count 0 2006.217.08:10:18.15#ibcon#about to read 6, iclass 10, count 0 2006.217.08:10:18.15#ibcon#read 6, iclass 10, count 0 2006.217.08:10:18.15#ibcon#end of sib2, iclass 10, count 0 2006.217.08:10:18.15#ibcon#*mode == 0, iclass 10, count 0 2006.217.08:10:18.15#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.217.08:10:18.15#ibcon#[25=USB\r\n] 2006.217.08:10:18.15#ibcon#*before write, iclass 10, count 0 2006.217.08:10:18.15#ibcon#enter sib2, iclass 10, count 0 2006.217.08:10:18.15#ibcon#flushed, iclass 10, count 0 2006.217.08:10:18.15#ibcon#about to write, iclass 10, count 0 2006.217.08:10:18.15#ibcon#wrote, iclass 10, count 0 2006.217.08:10:18.15#ibcon#about to read 3, iclass 10, count 0 2006.217.08:10:18.18#ibcon#read 3, iclass 10, count 0 2006.217.08:10:18.18#ibcon#about to read 4, iclass 10, count 0 2006.217.08:10:18.18#ibcon#read 4, iclass 10, count 0 2006.217.08:10:18.18#ibcon#about to read 5, iclass 10, count 0 2006.217.08:10:18.18#ibcon#read 5, iclass 10, count 0 2006.217.08:10:18.18#ibcon#about to read 6, iclass 10, count 0 2006.217.08:10:18.18#ibcon#read 6, iclass 10, count 0 2006.217.08:10:18.18#ibcon#end of sib2, iclass 10, count 0 2006.217.08:10:18.18#ibcon#*after write, iclass 10, count 0 2006.217.08:10:18.18#ibcon#*before return 0, iclass 10, count 0 2006.217.08:10:18.18#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.217.08:10:18.18#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.217.08:10:18.18#ibcon#about to clear, iclass 10 cls_cnt 0 2006.217.08:10:18.18#ibcon#cleared, iclass 10 cls_cnt 0 2006.217.08:10:18.18$vc4f8/valo=2,572.99 2006.217.08:10:18.18#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.217.08:10:18.18#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.217.08:10:18.18#ibcon#ireg 17 cls_cnt 0 2006.217.08:10:18.18#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.217.08:10:18.18#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.217.08:10:18.18#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.217.08:10:18.18#ibcon#enter wrdev, iclass 12, count 0 2006.217.08:10:18.18#ibcon#first serial, iclass 12, count 0 2006.217.08:10:18.18#ibcon#enter sib2, iclass 12, count 0 2006.217.08:10:18.18#ibcon#flushed, iclass 12, count 0 2006.217.08:10:18.18#ibcon#about to write, iclass 12, count 0 2006.217.08:10:18.18#ibcon#wrote, iclass 12, count 0 2006.217.08:10:18.18#ibcon#about to read 3, iclass 12, count 0 2006.217.08:10:18.20#ibcon#read 3, iclass 12, count 0 2006.217.08:10:18.20#ibcon#about to read 4, iclass 12, count 0 2006.217.08:10:18.20#ibcon#read 4, iclass 12, count 0 2006.217.08:10:18.20#ibcon#about to read 5, iclass 12, count 0 2006.217.08:10:18.20#ibcon#read 5, iclass 12, count 0 2006.217.08:10:18.20#ibcon#about to read 6, iclass 12, count 0 2006.217.08:10:18.20#ibcon#read 6, iclass 12, count 0 2006.217.08:10:18.20#ibcon#end of sib2, iclass 12, count 0 2006.217.08:10:18.20#ibcon#*mode == 0, iclass 12, count 0 2006.217.08:10:18.20#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.217.08:10:18.20#ibcon#[26=FRQ=02,572.99\r\n] 2006.217.08:10:18.20#ibcon#*before write, iclass 12, count 0 2006.217.08:10:18.20#ibcon#enter sib2, iclass 12, count 0 2006.217.08:10:18.20#ibcon#flushed, iclass 12, count 0 2006.217.08:10:18.20#ibcon#about to write, iclass 12, count 0 2006.217.08:10:18.20#ibcon#wrote, iclass 12, count 0 2006.217.08:10:18.20#ibcon#about to read 3, iclass 12, count 0 2006.217.08:10:18.25#ibcon#read 3, iclass 12, count 0 2006.217.08:10:18.25#ibcon#about to read 4, iclass 12, count 0 2006.217.08:10:18.25#ibcon#read 4, iclass 12, count 0 2006.217.08:10:18.25#ibcon#about to read 5, iclass 12, count 0 2006.217.08:10:18.25#ibcon#read 5, iclass 12, count 0 2006.217.08:10:18.25#ibcon#about to read 6, iclass 12, count 0 2006.217.08:10:18.25#ibcon#read 6, iclass 12, count 0 2006.217.08:10:18.25#ibcon#end of sib2, iclass 12, count 0 2006.217.08:10:18.25#ibcon#*after write, iclass 12, count 0 2006.217.08:10:18.25#ibcon#*before return 0, iclass 12, count 0 2006.217.08:10:18.25#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.217.08:10:18.25#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.217.08:10:18.25#ibcon#about to clear, iclass 12 cls_cnt 0 2006.217.08:10:18.25#ibcon#cleared, iclass 12 cls_cnt 0 2006.217.08:10:18.25$vc4f8/va=2,4 2006.217.08:10:18.25#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.217.08:10:18.25#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.217.08:10:18.25#ibcon#ireg 11 cls_cnt 2 2006.217.08:10:18.25#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.217.08:10:18.30#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.217.08:10:18.30#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.217.08:10:18.30#ibcon#enter wrdev, iclass 14, count 2 2006.217.08:10:18.30#ibcon#first serial, iclass 14, count 2 2006.217.08:10:18.30#ibcon#enter sib2, iclass 14, count 2 2006.217.08:10:18.30#ibcon#flushed, iclass 14, count 2 2006.217.08:10:18.30#ibcon#about to write, iclass 14, count 2 2006.217.08:10:18.30#ibcon#wrote, iclass 14, count 2 2006.217.08:10:18.30#ibcon#about to read 3, iclass 14, count 2 2006.217.08:10:18.32#ibcon#read 3, iclass 14, count 2 2006.217.08:10:18.32#ibcon#about to read 4, iclass 14, count 2 2006.217.08:10:18.32#ibcon#read 4, iclass 14, count 2 2006.217.08:10:18.32#ibcon#about to read 5, iclass 14, count 2 2006.217.08:10:18.32#ibcon#read 5, iclass 14, count 2 2006.217.08:10:18.32#ibcon#about to read 6, iclass 14, count 2 2006.217.08:10:18.32#ibcon#read 6, iclass 14, count 2 2006.217.08:10:18.32#ibcon#end of sib2, iclass 14, count 2 2006.217.08:10:18.32#ibcon#*mode == 0, iclass 14, count 2 2006.217.08:10:18.32#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.217.08:10:18.32#ibcon#[25=AT02-04\r\n] 2006.217.08:10:18.32#ibcon#*before write, iclass 14, count 2 2006.217.08:10:18.32#ibcon#enter sib2, iclass 14, count 2 2006.217.08:10:18.32#ibcon#flushed, iclass 14, count 2 2006.217.08:10:18.32#ibcon#about to write, iclass 14, count 2 2006.217.08:10:18.32#ibcon#wrote, iclass 14, count 2 2006.217.08:10:18.32#ibcon#about to read 3, iclass 14, count 2 2006.217.08:10:18.35#ibcon#read 3, iclass 14, count 2 2006.217.08:10:18.35#ibcon#about to read 4, iclass 14, count 2 2006.217.08:10:18.35#ibcon#read 4, iclass 14, count 2 2006.217.08:10:18.35#ibcon#about to read 5, iclass 14, count 2 2006.217.08:10:18.35#ibcon#read 5, iclass 14, count 2 2006.217.08:10:18.35#ibcon#about to read 6, iclass 14, count 2 2006.217.08:10:18.35#ibcon#read 6, iclass 14, count 2 2006.217.08:10:18.35#ibcon#end of sib2, iclass 14, count 2 2006.217.08:10:18.35#ibcon#*after write, iclass 14, count 2 2006.217.08:10:18.35#ibcon#*before return 0, iclass 14, count 2 2006.217.08:10:18.35#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.217.08:10:18.35#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.217.08:10:18.35#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.217.08:10:18.35#ibcon#ireg 7 cls_cnt 0 2006.217.08:10:18.35#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.217.08:10:18.47#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.217.08:10:18.47#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.217.08:10:18.47#ibcon#enter wrdev, iclass 14, count 0 2006.217.08:10:18.47#ibcon#first serial, iclass 14, count 0 2006.217.08:10:18.47#ibcon#enter sib2, iclass 14, count 0 2006.217.08:10:18.47#ibcon#flushed, iclass 14, count 0 2006.217.08:10:18.47#ibcon#about to write, iclass 14, count 0 2006.217.08:10:18.47#ibcon#wrote, iclass 14, count 0 2006.217.08:10:18.47#ibcon#about to read 3, iclass 14, count 0 2006.217.08:10:18.49#ibcon#read 3, iclass 14, count 0 2006.217.08:10:18.49#ibcon#about to read 4, iclass 14, count 0 2006.217.08:10:18.49#ibcon#read 4, iclass 14, count 0 2006.217.08:10:18.49#ibcon#about to read 5, iclass 14, count 0 2006.217.08:10:18.49#ibcon#read 5, iclass 14, count 0 2006.217.08:10:18.49#ibcon#about to read 6, iclass 14, count 0 2006.217.08:10:18.49#ibcon#read 6, iclass 14, count 0 2006.217.08:10:18.49#ibcon#end of sib2, iclass 14, count 0 2006.217.08:10:18.49#ibcon#*mode == 0, iclass 14, count 0 2006.217.08:10:18.49#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.217.08:10:18.49#ibcon#[25=USB\r\n] 2006.217.08:10:18.49#ibcon#*before write, iclass 14, count 0 2006.217.08:10:18.49#ibcon#enter sib2, iclass 14, count 0 2006.217.08:10:18.49#ibcon#flushed, iclass 14, count 0 2006.217.08:10:18.49#ibcon#about to write, iclass 14, count 0 2006.217.08:10:18.49#ibcon#wrote, iclass 14, count 0 2006.217.08:10:18.49#ibcon#about to read 3, iclass 14, count 0 2006.217.08:10:18.52#ibcon#read 3, iclass 14, count 0 2006.217.08:10:18.52#ibcon#about to read 4, iclass 14, count 0 2006.217.08:10:18.52#ibcon#read 4, iclass 14, count 0 2006.217.08:10:18.52#ibcon#about to read 5, iclass 14, count 0 2006.217.08:10:18.52#ibcon#read 5, iclass 14, count 0 2006.217.08:10:18.52#ibcon#about to read 6, iclass 14, count 0 2006.217.08:10:18.52#ibcon#read 6, iclass 14, count 0 2006.217.08:10:18.52#ibcon#end of sib2, iclass 14, count 0 2006.217.08:10:18.52#ibcon#*after write, iclass 14, count 0 2006.217.08:10:18.52#ibcon#*before return 0, iclass 14, count 0 2006.217.08:10:18.52#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.217.08:10:18.52#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.217.08:10:18.52#ibcon#about to clear, iclass 14 cls_cnt 0 2006.217.08:10:18.52#ibcon#cleared, iclass 14 cls_cnt 0 2006.217.08:10:18.52$vc4f8/valo=3,672.99 2006.217.08:10:18.52#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.217.08:10:18.52#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.217.08:10:18.52#ibcon#ireg 17 cls_cnt 0 2006.217.08:10:18.52#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.217.08:10:18.52#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.217.08:10:18.52#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.217.08:10:18.52#ibcon#enter wrdev, iclass 16, count 0 2006.217.08:10:18.52#ibcon#first serial, iclass 16, count 0 2006.217.08:10:18.52#ibcon#enter sib2, iclass 16, count 0 2006.217.08:10:18.52#ibcon#flushed, iclass 16, count 0 2006.217.08:10:18.52#ibcon#about to write, iclass 16, count 0 2006.217.08:10:18.52#ibcon#wrote, iclass 16, count 0 2006.217.08:10:18.52#ibcon#about to read 3, iclass 16, count 0 2006.217.08:10:18.54#ibcon#read 3, iclass 16, count 0 2006.217.08:10:18.54#ibcon#about to read 4, iclass 16, count 0 2006.217.08:10:18.54#ibcon#read 4, iclass 16, count 0 2006.217.08:10:18.54#ibcon#about to read 5, iclass 16, count 0 2006.217.08:10:18.54#ibcon#read 5, iclass 16, count 0 2006.217.08:10:18.54#ibcon#about to read 6, iclass 16, count 0 2006.217.08:10:18.54#ibcon#read 6, iclass 16, count 0 2006.217.08:10:18.54#ibcon#end of sib2, iclass 16, count 0 2006.217.08:10:18.54#ibcon#*mode == 0, iclass 16, count 0 2006.217.08:10:18.54#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.217.08:10:18.54#ibcon#[26=FRQ=03,672.99\r\n] 2006.217.08:10:18.54#ibcon#*before write, iclass 16, count 0 2006.217.08:10:18.54#ibcon#enter sib2, iclass 16, count 0 2006.217.08:10:18.54#ibcon#flushed, iclass 16, count 0 2006.217.08:10:18.54#ibcon#about to write, iclass 16, count 0 2006.217.08:10:18.54#ibcon#wrote, iclass 16, count 0 2006.217.08:10:18.54#ibcon#about to read 3, iclass 16, count 0 2006.217.08:10:18.59#ibcon#read 3, iclass 16, count 0 2006.217.08:10:18.59#ibcon#about to read 4, iclass 16, count 0 2006.217.08:10:18.59#ibcon#read 4, iclass 16, count 0 2006.217.08:10:18.59#ibcon#about to read 5, iclass 16, count 0 2006.217.08:10:18.59#ibcon#read 5, iclass 16, count 0 2006.217.08:10:18.59#ibcon#about to read 6, iclass 16, count 0 2006.217.08:10:18.59#ibcon#read 6, iclass 16, count 0 2006.217.08:10:18.59#ibcon#end of sib2, iclass 16, count 0 2006.217.08:10:18.59#ibcon#*after write, iclass 16, count 0 2006.217.08:10:18.59#ibcon#*before return 0, iclass 16, count 0 2006.217.08:10:18.59#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.217.08:10:18.59#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.217.08:10:18.59#ibcon#about to clear, iclass 16 cls_cnt 0 2006.217.08:10:18.59#ibcon#cleared, iclass 16 cls_cnt 0 2006.217.08:10:18.59$vc4f8/va=3,4 2006.217.08:10:18.59#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.217.08:10:18.59#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.217.08:10:18.59#ibcon#ireg 11 cls_cnt 2 2006.217.08:10:18.59#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.217.08:10:18.64#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.217.08:10:18.64#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.217.08:10:18.64#ibcon#enter wrdev, iclass 18, count 2 2006.217.08:10:18.64#ibcon#first serial, iclass 18, count 2 2006.217.08:10:18.64#ibcon#enter sib2, iclass 18, count 2 2006.217.08:10:18.64#ibcon#flushed, iclass 18, count 2 2006.217.08:10:18.64#ibcon#about to write, iclass 18, count 2 2006.217.08:10:18.64#ibcon#wrote, iclass 18, count 2 2006.217.08:10:18.64#ibcon#about to read 3, iclass 18, count 2 2006.217.08:10:18.66#ibcon#read 3, iclass 18, count 2 2006.217.08:10:18.66#ibcon#about to read 4, iclass 18, count 2 2006.217.08:10:18.66#ibcon#read 4, iclass 18, count 2 2006.217.08:10:18.66#ibcon#about to read 5, iclass 18, count 2 2006.217.08:10:18.66#ibcon#read 5, iclass 18, count 2 2006.217.08:10:18.66#ibcon#about to read 6, iclass 18, count 2 2006.217.08:10:18.66#ibcon#read 6, iclass 18, count 2 2006.217.08:10:18.66#ibcon#end of sib2, iclass 18, count 2 2006.217.08:10:18.66#ibcon#*mode == 0, iclass 18, count 2 2006.217.08:10:18.66#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.217.08:10:18.66#ibcon#[25=AT03-04\r\n] 2006.217.08:10:18.66#ibcon#*before write, iclass 18, count 2 2006.217.08:10:18.66#ibcon#enter sib2, iclass 18, count 2 2006.217.08:10:18.66#ibcon#flushed, iclass 18, count 2 2006.217.08:10:18.66#ibcon#about to write, iclass 18, count 2 2006.217.08:10:18.66#ibcon#wrote, iclass 18, count 2 2006.217.08:10:18.66#ibcon#about to read 3, iclass 18, count 2 2006.217.08:10:18.69#ibcon#read 3, iclass 18, count 2 2006.217.08:10:18.69#ibcon#about to read 4, iclass 18, count 2 2006.217.08:10:18.69#ibcon#read 4, iclass 18, count 2 2006.217.08:10:18.69#ibcon#about to read 5, iclass 18, count 2 2006.217.08:10:18.69#ibcon#read 5, iclass 18, count 2 2006.217.08:10:18.69#ibcon#about to read 6, iclass 18, count 2 2006.217.08:10:18.69#ibcon#read 6, iclass 18, count 2 2006.217.08:10:18.69#ibcon#end of sib2, iclass 18, count 2 2006.217.08:10:18.69#ibcon#*after write, iclass 18, count 2 2006.217.08:10:18.69#ibcon#*before return 0, iclass 18, count 2 2006.217.08:10:18.69#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.217.08:10:18.69#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.217.08:10:18.69#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.217.08:10:18.69#ibcon#ireg 7 cls_cnt 0 2006.217.08:10:18.69#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.217.08:10:18.81#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.217.08:10:18.81#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.217.08:10:18.81#ibcon#enter wrdev, iclass 18, count 0 2006.217.08:10:18.81#ibcon#first serial, iclass 18, count 0 2006.217.08:10:18.81#ibcon#enter sib2, iclass 18, count 0 2006.217.08:10:18.81#ibcon#flushed, iclass 18, count 0 2006.217.08:10:18.81#ibcon#about to write, iclass 18, count 0 2006.217.08:10:18.81#ibcon#wrote, iclass 18, count 0 2006.217.08:10:18.81#ibcon#about to read 3, iclass 18, count 0 2006.217.08:10:18.83#ibcon#read 3, iclass 18, count 0 2006.217.08:10:18.83#ibcon#about to read 4, iclass 18, count 0 2006.217.08:10:18.83#ibcon#read 4, iclass 18, count 0 2006.217.08:10:18.83#ibcon#about to read 5, iclass 18, count 0 2006.217.08:10:18.83#ibcon#read 5, iclass 18, count 0 2006.217.08:10:18.83#ibcon#about to read 6, iclass 18, count 0 2006.217.08:10:18.83#ibcon#read 6, iclass 18, count 0 2006.217.08:10:18.83#ibcon#end of sib2, iclass 18, count 0 2006.217.08:10:18.83#ibcon#*mode == 0, iclass 18, count 0 2006.217.08:10:18.83#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.217.08:10:18.83#ibcon#[25=USB\r\n] 2006.217.08:10:18.83#ibcon#*before write, iclass 18, count 0 2006.217.08:10:18.83#ibcon#enter sib2, iclass 18, count 0 2006.217.08:10:18.83#ibcon#flushed, iclass 18, count 0 2006.217.08:10:18.83#ibcon#about to write, iclass 18, count 0 2006.217.08:10:18.83#ibcon#wrote, iclass 18, count 0 2006.217.08:10:18.83#ibcon#about to read 3, iclass 18, count 0 2006.217.08:10:18.86#ibcon#read 3, iclass 18, count 0 2006.217.08:10:18.86#ibcon#about to read 4, iclass 18, count 0 2006.217.08:10:18.86#ibcon#read 4, iclass 18, count 0 2006.217.08:10:18.86#ibcon#about to read 5, iclass 18, count 0 2006.217.08:10:18.86#ibcon#read 5, iclass 18, count 0 2006.217.08:10:18.86#ibcon#about to read 6, iclass 18, count 0 2006.217.08:10:18.86#ibcon#read 6, iclass 18, count 0 2006.217.08:10:18.86#ibcon#end of sib2, iclass 18, count 0 2006.217.08:10:18.86#ibcon#*after write, iclass 18, count 0 2006.217.08:10:18.86#ibcon#*before return 0, iclass 18, count 0 2006.217.08:10:18.86#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.217.08:10:18.86#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.217.08:10:18.86#ibcon#about to clear, iclass 18 cls_cnt 0 2006.217.08:10:18.86#ibcon#cleared, iclass 18 cls_cnt 0 2006.217.08:10:18.86$vc4f8/valo=4,832.99 2006.217.08:10:18.86#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.217.08:10:18.86#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.217.08:10:18.86#ibcon#ireg 17 cls_cnt 0 2006.217.08:10:18.86#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.217.08:10:18.86#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.217.08:10:18.86#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.217.08:10:18.86#ibcon#enter wrdev, iclass 20, count 0 2006.217.08:10:18.86#ibcon#first serial, iclass 20, count 0 2006.217.08:10:18.86#ibcon#enter sib2, iclass 20, count 0 2006.217.08:10:18.86#ibcon#flushed, iclass 20, count 0 2006.217.08:10:18.86#ibcon#about to write, iclass 20, count 0 2006.217.08:10:18.86#ibcon#wrote, iclass 20, count 0 2006.217.08:10:18.86#ibcon#about to read 3, iclass 20, count 0 2006.217.08:10:18.88#ibcon#read 3, iclass 20, count 0 2006.217.08:10:18.88#ibcon#about to read 4, iclass 20, count 0 2006.217.08:10:18.88#ibcon#read 4, iclass 20, count 0 2006.217.08:10:18.88#ibcon#about to read 5, iclass 20, count 0 2006.217.08:10:18.88#ibcon#read 5, iclass 20, count 0 2006.217.08:10:18.88#ibcon#about to read 6, iclass 20, count 0 2006.217.08:10:18.88#ibcon#read 6, iclass 20, count 0 2006.217.08:10:18.88#ibcon#end of sib2, iclass 20, count 0 2006.217.08:10:18.88#ibcon#*mode == 0, iclass 20, count 0 2006.217.08:10:18.88#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.217.08:10:18.88#ibcon#[26=FRQ=04,832.99\r\n] 2006.217.08:10:18.88#ibcon#*before write, iclass 20, count 0 2006.217.08:10:18.88#ibcon#enter sib2, iclass 20, count 0 2006.217.08:10:18.88#ibcon#flushed, iclass 20, count 0 2006.217.08:10:18.88#ibcon#about to write, iclass 20, count 0 2006.217.08:10:18.88#ibcon#wrote, iclass 20, count 0 2006.217.08:10:18.88#ibcon#about to read 3, iclass 20, count 0 2006.217.08:10:18.93#ibcon#read 3, iclass 20, count 0 2006.217.08:10:18.93#ibcon#about to read 4, iclass 20, count 0 2006.217.08:10:18.93#ibcon#read 4, iclass 20, count 0 2006.217.08:10:18.93#ibcon#about to read 5, iclass 20, count 0 2006.217.08:10:18.93#ibcon#read 5, iclass 20, count 0 2006.217.08:10:18.93#ibcon#about to read 6, iclass 20, count 0 2006.217.08:10:18.93#ibcon#read 6, iclass 20, count 0 2006.217.08:10:18.93#ibcon#end of sib2, iclass 20, count 0 2006.217.08:10:18.93#ibcon#*after write, iclass 20, count 0 2006.217.08:10:18.93#ibcon#*before return 0, iclass 20, count 0 2006.217.08:10:18.93#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.217.08:10:18.93#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.217.08:10:18.93#ibcon#about to clear, iclass 20 cls_cnt 0 2006.217.08:10:18.93#ibcon#cleared, iclass 20 cls_cnt 0 2006.217.08:10:18.93$vc4f8/va=4,4 2006.217.08:10:18.93#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.217.08:10:18.93#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.217.08:10:18.93#ibcon#ireg 11 cls_cnt 2 2006.217.08:10:18.93#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.217.08:10:18.98#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.217.08:10:18.98#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.217.08:10:18.98#ibcon#enter wrdev, iclass 22, count 2 2006.217.08:10:18.98#ibcon#first serial, iclass 22, count 2 2006.217.08:10:18.98#ibcon#enter sib2, iclass 22, count 2 2006.217.08:10:18.98#ibcon#flushed, iclass 22, count 2 2006.217.08:10:18.98#ibcon#about to write, iclass 22, count 2 2006.217.08:10:18.98#ibcon#wrote, iclass 22, count 2 2006.217.08:10:18.98#ibcon#about to read 3, iclass 22, count 2 2006.217.08:10:19.00#ibcon#read 3, iclass 22, count 2 2006.217.08:10:19.00#ibcon#about to read 4, iclass 22, count 2 2006.217.08:10:19.00#ibcon#read 4, iclass 22, count 2 2006.217.08:10:19.00#ibcon#about to read 5, iclass 22, count 2 2006.217.08:10:19.00#ibcon#read 5, iclass 22, count 2 2006.217.08:10:19.00#ibcon#about to read 6, iclass 22, count 2 2006.217.08:10:19.00#ibcon#read 6, iclass 22, count 2 2006.217.08:10:19.00#ibcon#end of sib2, iclass 22, count 2 2006.217.08:10:19.00#ibcon#*mode == 0, iclass 22, count 2 2006.217.08:10:19.00#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.217.08:10:19.00#ibcon#[25=AT04-04\r\n] 2006.217.08:10:19.00#ibcon#*before write, iclass 22, count 2 2006.217.08:10:19.00#ibcon#enter sib2, iclass 22, count 2 2006.217.08:10:19.00#ibcon#flushed, iclass 22, count 2 2006.217.08:10:19.00#ibcon#about to write, iclass 22, count 2 2006.217.08:10:19.00#ibcon#wrote, iclass 22, count 2 2006.217.08:10:19.00#ibcon#about to read 3, iclass 22, count 2 2006.217.08:10:19.03#ibcon#read 3, iclass 22, count 2 2006.217.08:10:19.03#ibcon#about to read 4, iclass 22, count 2 2006.217.08:10:19.03#ibcon#read 4, iclass 22, count 2 2006.217.08:10:19.03#ibcon#about to read 5, iclass 22, count 2 2006.217.08:10:19.03#ibcon#read 5, iclass 22, count 2 2006.217.08:10:19.03#ibcon#about to read 6, iclass 22, count 2 2006.217.08:10:19.03#ibcon#read 6, iclass 22, count 2 2006.217.08:10:19.03#ibcon#end of sib2, iclass 22, count 2 2006.217.08:10:19.03#ibcon#*after write, iclass 22, count 2 2006.217.08:10:19.03#ibcon#*before return 0, iclass 22, count 2 2006.217.08:10:19.03#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.217.08:10:19.03#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.217.08:10:19.03#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.217.08:10:19.03#ibcon#ireg 7 cls_cnt 0 2006.217.08:10:19.03#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.217.08:10:19.15#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.217.08:10:19.15#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.217.08:10:19.15#ibcon#enter wrdev, iclass 22, count 0 2006.217.08:10:19.15#ibcon#first serial, iclass 22, count 0 2006.217.08:10:19.15#ibcon#enter sib2, iclass 22, count 0 2006.217.08:10:19.15#ibcon#flushed, iclass 22, count 0 2006.217.08:10:19.15#ibcon#about to write, iclass 22, count 0 2006.217.08:10:19.15#ibcon#wrote, iclass 22, count 0 2006.217.08:10:19.15#ibcon#about to read 3, iclass 22, count 0 2006.217.08:10:19.17#ibcon#read 3, iclass 22, count 0 2006.217.08:10:19.17#ibcon#about to read 4, iclass 22, count 0 2006.217.08:10:19.17#ibcon#read 4, iclass 22, count 0 2006.217.08:10:19.17#ibcon#about to read 5, iclass 22, count 0 2006.217.08:10:19.17#ibcon#read 5, iclass 22, count 0 2006.217.08:10:19.17#ibcon#about to read 6, iclass 22, count 0 2006.217.08:10:19.17#ibcon#read 6, iclass 22, count 0 2006.217.08:10:19.17#ibcon#end of sib2, iclass 22, count 0 2006.217.08:10:19.17#ibcon#*mode == 0, iclass 22, count 0 2006.217.08:10:19.17#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.217.08:10:19.17#ibcon#[25=USB\r\n] 2006.217.08:10:19.17#ibcon#*before write, iclass 22, count 0 2006.217.08:10:19.17#ibcon#enter sib2, iclass 22, count 0 2006.217.08:10:19.17#ibcon#flushed, iclass 22, count 0 2006.217.08:10:19.17#ibcon#about to write, iclass 22, count 0 2006.217.08:10:19.17#ibcon#wrote, iclass 22, count 0 2006.217.08:10:19.17#ibcon#about to read 3, iclass 22, count 0 2006.217.08:10:19.20#ibcon#read 3, iclass 22, count 0 2006.217.08:10:19.20#ibcon#about to read 4, iclass 22, count 0 2006.217.08:10:19.20#ibcon#read 4, iclass 22, count 0 2006.217.08:10:19.20#ibcon#about to read 5, iclass 22, count 0 2006.217.08:10:19.20#ibcon#read 5, iclass 22, count 0 2006.217.08:10:19.20#ibcon#about to read 6, iclass 22, count 0 2006.217.08:10:19.20#ibcon#read 6, iclass 22, count 0 2006.217.08:10:19.20#ibcon#end of sib2, iclass 22, count 0 2006.217.08:10:19.20#ibcon#*after write, iclass 22, count 0 2006.217.08:10:19.20#ibcon#*before return 0, iclass 22, count 0 2006.217.08:10:19.20#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.217.08:10:19.20#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.217.08:10:19.20#ibcon#about to clear, iclass 22 cls_cnt 0 2006.217.08:10:19.20#ibcon#cleared, iclass 22 cls_cnt 0 2006.217.08:10:19.20$vc4f8/valo=5,652.99 2006.217.08:10:19.20#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.217.08:10:19.20#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.217.08:10:19.20#ibcon#ireg 17 cls_cnt 0 2006.217.08:10:19.20#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.217.08:10:19.20#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.217.08:10:19.20#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.217.08:10:19.20#ibcon#enter wrdev, iclass 24, count 0 2006.217.08:10:19.20#ibcon#first serial, iclass 24, count 0 2006.217.08:10:19.20#ibcon#enter sib2, iclass 24, count 0 2006.217.08:10:19.20#ibcon#flushed, iclass 24, count 0 2006.217.08:10:19.20#ibcon#about to write, iclass 24, count 0 2006.217.08:10:19.20#ibcon#wrote, iclass 24, count 0 2006.217.08:10:19.20#ibcon#about to read 3, iclass 24, count 0 2006.217.08:10:19.22#ibcon#read 3, iclass 24, count 0 2006.217.08:10:19.22#ibcon#about to read 4, iclass 24, count 0 2006.217.08:10:19.22#ibcon#read 4, iclass 24, count 0 2006.217.08:10:19.22#ibcon#about to read 5, iclass 24, count 0 2006.217.08:10:19.22#ibcon#read 5, iclass 24, count 0 2006.217.08:10:19.22#ibcon#about to read 6, iclass 24, count 0 2006.217.08:10:19.22#ibcon#read 6, iclass 24, count 0 2006.217.08:10:19.22#ibcon#end of sib2, iclass 24, count 0 2006.217.08:10:19.22#ibcon#*mode == 0, iclass 24, count 0 2006.217.08:10:19.22#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.217.08:10:19.22#ibcon#[26=FRQ=05,652.99\r\n] 2006.217.08:10:19.22#ibcon#*before write, iclass 24, count 0 2006.217.08:10:19.22#ibcon#enter sib2, iclass 24, count 0 2006.217.08:10:19.22#ibcon#flushed, iclass 24, count 0 2006.217.08:10:19.22#ibcon#about to write, iclass 24, count 0 2006.217.08:10:19.22#ibcon#wrote, iclass 24, count 0 2006.217.08:10:19.22#ibcon#about to read 3, iclass 24, count 0 2006.217.08:10:19.26#ibcon#read 3, iclass 24, count 0 2006.217.08:10:19.26#ibcon#about to read 4, iclass 24, count 0 2006.217.08:10:19.26#ibcon#read 4, iclass 24, count 0 2006.217.08:10:19.26#ibcon#about to read 5, iclass 24, count 0 2006.217.08:10:19.26#ibcon#read 5, iclass 24, count 0 2006.217.08:10:19.26#ibcon#about to read 6, iclass 24, count 0 2006.217.08:10:19.26#ibcon#read 6, iclass 24, count 0 2006.217.08:10:19.26#ibcon#end of sib2, iclass 24, count 0 2006.217.08:10:19.26#ibcon#*after write, iclass 24, count 0 2006.217.08:10:19.26#ibcon#*before return 0, iclass 24, count 0 2006.217.08:10:19.26#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.217.08:10:19.26#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.217.08:10:19.26#ibcon#about to clear, iclass 24 cls_cnt 0 2006.217.08:10:19.26#ibcon#cleared, iclass 24 cls_cnt 0 2006.217.08:10:19.26$vc4f8/va=5,7 2006.217.08:10:19.26#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.217.08:10:19.26#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.217.08:10:19.26#ibcon#ireg 11 cls_cnt 2 2006.217.08:10:19.26#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.217.08:10:19.32#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.217.08:10:19.32#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.217.08:10:19.32#ibcon#enter wrdev, iclass 26, count 2 2006.217.08:10:19.32#ibcon#first serial, iclass 26, count 2 2006.217.08:10:19.32#ibcon#enter sib2, iclass 26, count 2 2006.217.08:10:19.32#ibcon#flushed, iclass 26, count 2 2006.217.08:10:19.32#ibcon#about to write, iclass 26, count 2 2006.217.08:10:19.32#ibcon#wrote, iclass 26, count 2 2006.217.08:10:19.32#ibcon#about to read 3, iclass 26, count 2 2006.217.08:10:19.34#ibcon#read 3, iclass 26, count 2 2006.217.08:10:19.34#ibcon#about to read 4, iclass 26, count 2 2006.217.08:10:19.34#ibcon#read 4, iclass 26, count 2 2006.217.08:10:19.34#ibcon#about to read 5, iclass 26, count 2 2006.217.08:10:19.34#ibcon#read 5, iclass 26, count 2 2006.217.08:10:19.34#ibcon#about to read 6, iclass 26, count 2 2006.217.08:10:19.34#ibcon#read 6, iclass 26, count 2 2006.217.08:10:19.34#ibcon#end of sib2, iclass 26, count 2 2006.217.08:10:19.34#ibcon#*mode == 0, iclass 26, count 2 2006.217.08:10:19.34#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.217.08:10:19.34#ibcon#[25=AT05-07\r\n] 2006.217.08:10:19.34#ibcon#*before write, iclass 26, count 2 2006.217.08:10:19.34#ibcon#enter sib2, iclass 26, count 2 2006.217.08:10:19.34#ibcon#flushed, iclass 26, count 2 2006.217.08:10:19.34#ibcon#about to write, iclass 26, count 2 2006.217.08:10:19.34#ibcon#wrote, iclass 26, count 2 2006.217.08:10:19.34#ibcon#about to read 3, iclass 26, count 2 2006.217.08:10:19.37#ibcon#read 3, iclass 26, count 2 2006.217.08:10:19.37#ibcon#about to read 4, iclass 26, count 2 2006.217.08:10:19.37#ibcon#read 4, iclass 26, count 2 2006.217.08:10:19.37#ibcon#about to read 5, iclass 26, count 2 2006.217.08:10:19.37#ibcon#read 5, iclass 26, count 2 2006.217.08:10:19.37#ibcon#about to read 6, iclass 26, count 2 2006.217.08:10:19.37#ibcon#read 6, iclass 26, count 2 2006.217.08:10:19.37#ibcon#end of sib2, iclass 26, count 2 2006.217.08:10:19.37#ibcon#*after write, iclass 26, count 2 2006.217.08:10:19.37#ibcon#*before return 0, iclass 26, count 2 2006.217.08:10:19.37#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.217.08:10:19.37#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.217.08:10:19.37#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.217.08:10:19.37#ibcon#ireg 7 cls_cnt 0 2006.217.08:10:19.37#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.217.08:10:19.49#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.217.08:10:19.49#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.217.08:10:19.49#ibcon#enter wrdev, iclass 26, count 0 2006.217.08:10:19.49#ibcon#first serial, iclass 26, count 0 2006.217.08:10:19.49#ibcon#enter sib2, iclass 26, count 0 2006.217.08:10:19.49#ibcon#flushed, iclass 26, count 0 2006.217.08:10:19.49#ibcon#about to write, iclass 26, count 0 2006.217.08:10:19.49#ibcon#wrote, iclass 26, count 0 2006.217.08:10:19.49#ibcon#about to read 3, iclass 26, count 0 2006.217.08:10:19.51#ibcon#read 3, iclass 26, count 0 2006.217.08:10:19.51#ibcon#about to read 4, iclass 26, count 0 2006.217.08:10:19.51#ibcon#read 4, iclass 26, count 0 2006.217.08:10:19.51#ibcon#about to read 5, iclass 26, count 0 2006.217.08:10:19.51#ibcon#read 5, iclass 26, count 0 2006.217.08:10:19.51#ibcon#about to read 6, iclass 26, count 0 2006.217.08:10:19.51#ibcon#read 6, iclass 26, count 0 2006.217.08:10:19.51#ibcon#end of sib2, iclass 26, count 0 2006.217.08:10:19.51#ibcon#*mode == 0, iclass 26, count 0 2006.217.08:10:19.51#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.217.08:10:19.51#ibcon#[25=USB\r\n] 2006.217.08:10:19.51#ibcon#*before write, iclass 26, count 0 2006.217.08:10:19.51#ibcon#enter sib2, iclass 26, count 0 2006.217.08:10:19.51#ibcon#flushed, iclass 26, count 0 2006.217.08:10:19.51#ibcon#about to write, iclass 26, count 0 2006.217.08:10:19.51#ibcon#wrote, iclass 26, count 0 2006.217.08:10:19.51#ibcon#about to read 3, iclass 26, count 0 2006.217.08:10:19.54#ibcon#read 3, iclass 26, count 0 2006.217.08:10:19.54#ibcon#about to read 4, iclass 26, count 0 2006.217.08:10:19.54#ibcon#read 4, iclass 26, count 0 2006.217.08:10:19.54#ibcon#about to read 5, iclass 26, count 0 2006.217.08:10:19.54#ibcon#read 5, iclass 26, count 0 2006.217.08:10:19.54#ibcon#about to read 6, iclass 26, count 0 2006.217.08:10:19.54#ibcon#read 6, iclass 26, count 0 2006.217.08:10:19.54#ibcon#end of sib2, iclass 26, count 0 2006.217.08:10:19.54#ibcon#*after write, iclass 26, count 0 2006.217.08:10:19.54#ibcon#*before return 0, iclass 26, count 0 2006.217.08:10:19.54#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.217.08:10:19.54#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.217.08:10:19.54#ibcon#about to clear, iclass 26 cls_cnt 0 2006.217.08:10:19.54#ibcon#cleared, iclass 26 cls_cnt 0 2006.217.08:10:19.54$vc4f8/valo=6,772.99 2006.217.08:10:19.54#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.217.08:10:19.54#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.217.08:10:19.54#ibcon#ireg 17 cls_cnt 0 2006.217.08:10:19.54#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.217.08:10:19.54#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.217.08:10:19.54#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.217.08:10:19.54#ibcon#enter wrdev, iclass 28, count 0 2006.217.08:10:19.54#ibcon#first serial, iclass 28, count 0 2006.217.08:10:19.54#ibcon#enter sib2, iclass 28, count 0 2006.217.08:10:19.54#ibcon#flushed, iclass 28, count 0 2006.217.08:10:19.54#ibcon#about to write, iclass 28, count 0 2006.217.08:10:19.54#ibcon#wrote, iclass 28, count 0 2006.217.08:10:19.54#ibcon#about to read 3, iclass 28, count 0 2006.217.08:10:19.56#ibcon#read 3, iclass 28, count 0 2006.217.08:10:19.56#ibcon#about to read 4, iclass 28, count 0 2006.217.08:10:19.56#ibcon#read 4, iclass 28, count 0 2006.217.08:10:19.56#ibcon#about to read 5, iclass 28, count 0 2006.217.08:10:19.56#ibcon#read 5, iclass 28, count 0 2006.217.08:10:19.56#ibcon#about to read 6, iclass 28, count 0 2006.217.08:10:19.56#ibcon#read 6, iclass 28, count 0 2006.217.08:10:19.56#ibcon#end of sib2, iclass 28, count 0 2006.217.08:10:19.56#ibcon#*mode == 0, iclass 28, count 0 2006.217.08:10:19.56#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.217.08:10:19.56#ibcon#[26=FRQ=06,772.99\r\n] 2006.217.08:10:19.56#ibcon#*before write, iclass 28, count 0 2006.217.08:10:19.56#ibcon#enter sib2, iclass 28, count 0 2006.217.08:10:19.56#ibcon#flushed, iclass 28, count 0 2006.217.08:10:19.56#ibcon#about to write, iclass 28, count 0 2006.217.08:10:19.56#ibcon#wrote, iclass 28, count 0 2006.217.08:10:19.56#ibcon#about to read 3, iclass 28, count 0 2006.217.08:10:19.60#ibcon#read 3, iclass 28, count 0 2006.217.08:10:19.60#ibcon#about to read 4, iclass 28, count 0 2006.217.08:10:19.60#ibcon#read 4, iclass 28, count 0 2006.217.08:10:19.60#ibcon#about to read 5, iclass 28, count 0 2006.217.08:10:19.60#ibcon#read 5, iclass 28, count 0 2006.217.08:10:19.60#ibcon#about to read 6, iclass 28, count 0 2006.217.08:10:19.60#ibcon#read 6, iclass 28, count 0 2006.217.08:10:19.60#ibcon#end of sib2, iclass 28, count 0 2006.217.08:10:19.60#ibcon#*after write, iclass 28, count 0 2006.217.08:10:19.60#ibcon#*before return 0, iclass 28, count 0 2006.217.08:10:19.60#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.217.08:10:19.60#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.217.08:10:19.60#ibcon#about to clear, iclass 28 cls_cnt 0 2006.217.08:10:19.60#ibcon#cleared, iclass 28 cls_cnt 0 2006.217.08:10:19.60$vc4f8/va=6,6 2006.217.08:10:19.60#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.217.08:10:19.60#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.217.08:10:19.60#ibcon#ireg 11 cls_cnt 2 2006.217.08:10:19.60#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.217.08:10:19.66#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.217.08:10:19.66#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.217.08:10:19.66#ibcon#enter wrdev, iclass 30, count 2 2006.217.08:10:19.66#ibcon#first serial, iclass 30, count 2 2006.217.08:10:19.66#ibcon#enter sib2, iclass 30, count 2 2006.217.08:10:19.66#ibcon#flushed, iclass 30, count 2 2006.217.08:10:19.66#ibcon#about to write, iclass 30, count 2 2006.217.08:10:19.66#ibcon#wrote, iclass 30, count 2 2006.217.08:10:19.66#ibcon#about to read 3, iclass 30, count 2 2006.217.08:10:19.68#ibcon#read 3, iclass 30, count 2 2006.217.08:10:19.68#ibcon#about to read 4, iclass 30, count 2 2006.217.08:10:19.68#ibcon#read 4, iclass 30, count 2 2006.217.08:10:19.68#ibcon#about to read 5, iclass 30, count 2 2006.217.08:10:19.68#ibcon#read 5, iclass 30, count 2 2006.217.08:10:19.68#ibcon#about to read 6, iclass 30, count 2 2006.217.08:10:19.68#ibcon#read 6, iclass 30, count 2 2006.217.08:10:19.68#ibcon#end of sib2, iclass 30, count 2 2006.217.08:10:19.68#ibcon#*mode == 0, iclass 30, count 2 2006.217.08:10:19.68#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.217.08:10:19.68#ibcon#[25=AT06-06\r\n] 2006.217.08:10:19.68#ibcon#*before write, iclass 30, count 2 2006.217.08:10:19.68#ibcon#enter sib2, iclass 30, count 2 2006.217.08:10:19.68#ibcon#flushed, iclass 30, count 2 2006.217.08:10:19.68#ibcon#about to write, iclass 30, count 2 2006.217.08:10:19.68#ibcon#wrote, iclass 30, count 2 2006.217.08:10:19.68#ibcon#about to read 3, iclass 30, count 2 2006.217.08:10:19.72#ibcon#read 3, iclass 30, count 2 2006.217.08:10:19.72#ibcon#about to read 4, iclass 30, count 2 2006.217.08:10:19.72#ibcon#read 4, iclass 30, count 2 2006.217.08:10:19.72#ibcon#about to read 5, iclass 30, count 2 2006.217.08:10:19.72#ibcon#read 5, iclass 30, count 2 2006.217.08:10:19.72#ibcon#about to read 6, iclass 30, count 2 2006.217.08:10:19.72#ibcon#read 6, iclass 30, count 2 2006.217.08:10:19.72#ibcon#end of sib2, iclass 30, count 2 2006.217.08:10:19.72#ibcon#*after write, iclass 30, count 2 2006.217.08:10:19.72#ibcon#*before return 0, iclass 30, count 2 2006.217.08:10:19.72#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.217.08:10:19.72#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.217.08:10:19.72#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.217.08:10:19.72#ibcon#ireg 7 cls_cnt 0 2006.217.08:10:19.72#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.217.08:10:19.84#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.217.08:10:19.84#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.217.08:10:19.84#ibcon#enter wrdev, iclass 30, count 0 2006.217.08:10:19.84#ibcon#first serial, iclass 30, count 0 2006.217.08:10:19.84#ibcon#enter sib2, iclass 30, count 0 2006.217.08:10:19.84#ibcon#flushed, iclass 30, count 0 2006.217.08:10:19.84#ibcon#about to write, iclass 30, count 0 2006.217.08:10:19.84#ibcon#wrote, iclass 30, count 0 2006.217.08:10:19.84#ibcon#about to read 3, iclass 30, count 0 2006.217.08:10:19.86#ibcon#read 3, iclass 30, count 0 2006.217.08:10:19.86#ibcon#about to read 4, iclass 30, count 0 2006.217.08:10:19.86#ibcon#read 4, iclass 30, count 0 2006.217.08:10:19.86#ibcon#about to read 5, iclass 30, count 0 2006.217.08:10:19.86#ibcon#read 5, iclass 30, count 0 2006.217.08:10:19.86#ibcon#about to read 6, iclass 30, count 0 2006.217.08:10:19.86#ibcon#read 6, iclass 30, count 0 2006.217.08:10:19.86#ibcon#end of sib2, iclass 30, count 0 2006.217.08:10:19.86#ibcon#*mode == 0, iclass 30, count 0 2006.217.08:10:19.86#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.217.08:10:19.86#ibcon#[25=USB\r\n] 2006.217.08:10:19.86#ibcon#*before write, iclass 30, count 0 2006.217.08:10:19.86#ibcon#enter sib2, iclass 30, count 0 2006.217.08:10:19.86#ibcon#flushed, iclass 30, count 0 2006.217.08:10:19.86#ibcon#about to write, iclass 30, count 0 2006.217.08:10:19.86#ibcon#wrote, iclass 30, count 0 2006.217.08:10:19.86#ibcon#about to read 3, iclass 30, count 0 2006.217.08:10:19.89#ibcon#read 3, iclass 30, count 0 2006.217.08:10:19.89#ibcon#about to read 4, iclass 30, count 0 2006.217.08:10:19.89#ibcon#read 4, iclass 30, count 0 2006.217.08:10:19.89#ibcon#about to read 5, iclass 30, count 0 2006.217.08:10:19.89#ibcon#read 5, iclass 30, count 0 2006.217.08:10:19.89#ibcon#about to read 6, iclass 30, count 0 2006.217.08:10:19.89#ibcon#read 6, iclass 30, count 0 2006.217.08:10:19.89#ibcon#end of sib2, iclass 30, count 0 2006.217.08:10:19.89#ibcon#*after write, iclass 30, count 0 2006.217.08:10:19.89#ibcon#*before return 0, iclass 30, count 0 2006.217.08:10:19.89#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.217.08:10:19.89#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.217.08:10:19.89#ibcon#about to clear, iclass 30 cls_cnt 0 2006.217.08:10:19.89#ibcon#cleared, iclass 30 cls_cnt 0 2006.217.08:10:19.89$vc4f8/valo=7,832.99 2006.217.08:10:19.89#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.217.08:10:19.89#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.217.08:10:19.89#ibcon#ireg 17 cls_cnt 0 2006.217.08:10:19.89#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.217.08:10:19.89#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.217.08:10:19.89#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.217.08:10:19.89#ibcon#enter wrdev, iclass 32, count 0 2006.217.08:10:19.89#ibcon#first serial, iclass 32, count 0 2006.217.08:10:19.89#ibcon#enter sib2, iclass 32, count 0 2006.217.08:10:19.89#ibcon#flushed, iclass 32, count 0 2006.217.08:10:19.89#ibcon#about to write, iclass 32, count 0 2006.217.08:10:19.89#ibcon#wrote, iclass 32, count 0 2006.217.08:10:19.89#ibcon#about to read 3, iclass 32, count 0 2006.217.08:10:19.91#ibcon#read 3, iclass 32, count 0 2006.217.08:10:19.91#ibcon#about to read 4, iclass 32, count 0 2006.217.08:10:19.91#ibcon#read 4, iclass 32, count 0 2006.217.08:10:19.91#ibcon#about to read 5, iclass 32, count 0 2006.217.08:10:19.91#ibcon#read 5, iclass 32, count 0 2006.217.08:10:19.91#ibcon#about to read 6, iclass 32, count 0 2006.217.08:10:19.91#ibcon#read 6, iclass 32, count 0 2006.217.08:10:19.91#ibcon#end of sib2, iclass 32, count 0 2006.217.08:10:19.91#ibcon#*mode == 0, iclass 32, count 0 2006.217.08:10:19.91#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.217.08:10:19.91#ibcon#[26=FRQ=07,832.99\r\n] 2006.217.08:10:19.91#ibcon#*before write, iclass 32, count 0 2006.217.08:10:19.91#ibcon#enter sib2, iclass 32, count 0 2006.217.08:10:19.91#ibcon#flushed, iclass 32, count 0 2006.217.08:10:19.91#ibcon#about to write, iclass 32, count 0 2006.217.08:10:19.91#ibcon#wrote, iclass 32, count 0 2006.217.08:10:19.91#ibcon#about to read 3, iclass 32, count 0 2006.217.08:10:19.95#ibcon#read 3, iclass 32, count 0 2006.217.08:10:19.95#ibcon#about to read 4, iclass 32, count 0 2006.217.08:10:19.95#ibcon#read 4, iclass 32, count 0 2006.217.08:10:19.95#ibcon#about to read 5, iclass 32, count 0 2006.217.08:10:19.95#ibcon#read 5, iclass 32, count 0 2006.217.08:10:19.95#ibcon#about to read 6, iclass 32, count 0 2006.217.08:10:19.95#ibcon#read 6, iclass 32, count 0 2006.217.08:10:19.95#ibcon#end of sib2, iclass 32, count 0 2006.217.08:10:19.95#ibcon#*after write, iclass 32, count 0 2006.217.08:10:19.95#ibcon#*before return 0, iclass 32, count 0 2006.217.08:10:19.95#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.217.08:10:19.95#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.217.08:10:19.95#ibcon#about to clear, iclass 32 cls_cnt 0 2006.217.08:10:19.95#ibcon#cleared, iclass 32 cls_cnt 0 2006.217.08:10:19.95$vc4f8/va=7,6 2006.217.08:10:19.95#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.217.08:10:19.95#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.217.08:10:19.95#ibcon#ireg 11 cls_cnt 2 2006.217.08:10:19.95#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.217.08:10:20.01#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.217.08:10:20.01#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.217.08:10:20.01#ibcon#enter wrdev, iclass 34, count 2 2006.217.08:10:20.01#ibcon#first serial, iclass 34, count 2 2006.217.08:10:20.01#ibcon#enter sib2, iclass 34, count 2 2006.217.08:10:20.01#ibcon#flushed, iclass 34, count 2 2006.217.08:10:20.01#ibcon#about to write, iclass 34, count 2 2006.217.08:10:20.01#ibcon#wrote, iclass 34, count 2 2006.217.08:10:20.01#ibcon#about to read 3, iclass 34, count 2 2006.217.08:10:20.03#ibcon#read 3, iclass 34, count 2 2006.217.08:10:20.03#ibcon#about to read 4, iclass 34, count 2 2006.217.08:10:20.03#ibcon#read 4, iclass 34, count 2 2006.217.08:10:20.03#ibcon#about to read 5, iclass 34, count 2 2006.217.08:10:20.03#ibcon#read 5, iclass 34, count 2 2006.217.08:10:20.03#ibcon#about to read 6, iclass 34, count 2 2006.217.08:10:20.03#ibcon#read 6, iclass 34, count 2 2006.217.08:10:20.03#ibcon#end of sib2, iclass 34, count 2 2006.217.08:10:20.03#ibcon#*mode == 0, iclass 34, count 2 2006.217.08:10:20.03#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.217.08:10:20.03#ibcon#[25=AT07-06\r\n] 2006.217.08:10:20.03#ibcon#*before write, iclass 34, count 2 2006.217.08:10:20.03#ibcon#enter sib2, iclass 34, count 2 2006.217.08:10:20.03#ibcon#flushed, iclass 34, count 2 2006.217.08:10:20.03#ibcon#about to write, iclass 34, count 2 2006.217.08:10:20.03#ibcon#wrote, iclass 34, count 2 2006.217.08:10:20.03#ibcon#about to read 3, iclass 34, count 2 2006.217.08:10:20.06#ibcon#read 3, iclass 34, count 2 2006.217.08:10:20.06#ibcon#about to read 4, iclass 34, count 2 2006.217.08:10:20.06#ibcon#read 4, iclass 34, count 2 2006.217.08:10:20.06#ibcon#about to read 5, iclass 34, count 2 2006.217.08:10:20.06#ibcon#read 5, iclass 34, count 2 2006.217.08:10:20.06#ibcon#about to read 6, iclass 34, count 2 2006.217.08:10:20.06#ibcon#read 6, iclass 34, count 2 2006.217.08:10:20.06#ibcon#end of sib2, iclass 34, count 2 2006.217.08:10:20.06#ibcon#*after write, iclass 34, count 2 2006.217.08:10:20.06#ibcon#*before return 0, iclass 34, count 2 2006.217.08:10:20.06#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.217.08:10:20.06#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.217.08:10:20.06#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.217.08:10:20.06#ibcon#ireg 7 cls_cnt 0 2006.217.08:10:20.06#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.217.08:10:20.18#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.217.08:10:20.18#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.217.08:10:20.18#ibcon#enter wrdev, iclass 34, count 0 2006.217.08:10:20.18#ibcon#first serial, iclass 34, count 0 2006.217.08:10:20.18#ibcon#enter sib2, iclass 34, count 0 2006.217.08:10:20.18#ibcon#flushed, iclass 34, count 0 2006.217.08:10:20.18#ibcon#about to write, iclass 34, count 0 2006.217.08:10:20.18#ibcon#wrote, iclass 34, count 0 2006.217.08:10:20.18#ibcon#about to read 3, iclass 34, count 0 2006.217.08:10:20.20#ibcon#read 3, iclass 34, count 0 2006.217.08:10:20.20#ibcon#about to read 4, iclass 34, count 0 2006.217.08:10:20.20#ibcon#read 4, iclass 34, count 0 2006.217.08:10:20.20#ibcon#about to read 5, iclass 34, count 0 2006.217.08:10:20.20#ibcon#read 5, iclass 34, count 0 2006.217.08:10:20.20#ibcon#about to read 6, iclass 34, count 0 2006.217.08:10:20.20#ibcon#read 6, iclass 34, count 0 2006.217.08:10:20.20#ibcon#end of sib2, iclass 34, count 0 2006.217.08:10:20.20#ibcon#*mode == 0, iclass 34, count 0 2006.217.08:10:20.20#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.217.08:10:20.20#ibcon#[25=USB\r\n] 2006.217.08:10:20.20#ibcon#*before write, iclass 34, count 0 2006.217.08:10:20.20#ibcon#enter sib2, iclass 34, count 0 2006.217.08:10:20.20#ibcon#flushed, iclass 34, count 0 2006.217.08:10:20.20#ibcon#about to write, iclass 34, count 0 2006.217.08:10:20.20#ibcon#wrote, iclass 34, count 0 2006.217.08:10:20.20#ibcon#about to read 3, iclass 34, count 0 2006.217.08:10:20.23#ibcon#read 3, iclass 34, count 0 2006.217.08:10:20.23#ibcon#about to read 4, iclass 34, count 0 2006.217.08:10:20.23#ibcon#read 4, iclass 34, count 0 2006.217.08:10:20.23#ibcon#about to read 5, iclass 34, count 0 2006.217.08:10:20.23#ibcon#read 5, iclass 34, count 0 2006.217.08:10:20.23#ibcon#about to read 6, iclass 34, count 0 2006.217.08:10:20.23#ibcon#read 6, iclass 34, count 0 2006.217.08:10:20.23#ibcon#end of sib2, iclass 34, count 0 2006.217.08:10:20.23#ibcon#*after write, iclass 34, count 0 2006.217.08:10:20.23#ibcon#*before return 0, iclass 34, count 0 2006.217.08:10:20.23#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.217.08:10:20.23#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.217.08:10:20.23#ibcon#about to clear, iclass 34 cls_cnt 0 2006.217.08:10:20.23#ibcon#cleared, iclass 34 cls_cnt 0 2006.217.08:10:20.23$vc4f8/valo=8,852.99 2006.217.08:10:20.23#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.217.08:10:20.23#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.217.08:10:20.23#ibcon#ireg 17 cls_cnt 0 2006.217.08:10:20.23#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.217.08:10:20.23#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.217.08:10:20.23#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.217.08:10:20.23#ibcon#enter wrdev, iclass 36, count 0 2006.217.08:10:20.23#ibcon#first serial, iclass 36, count 0 2006.217.08:10:20.23#ibcon#enter sib2, iclass 36, count 0 2006.217.08:10:20.23#ibcon#flushed, iclass 36, count 0 2006.217.08:10:20.23#ibcon#about to write, iclass 36, count 0 2006.217.08:10:20.23#ibcon#wrote, iclass 36, count 0 2006.217.08:10:20.23#ibcon#about to read 3, iclass 36, count 0 2006.217.08:10:20.25#ibcon#read 3, iclass 36, count 0 2006.217.08:10:20.25#ibcon#about to read 4, iclass 36, count 0 2006.217.08:10:20.25#ibcon#read 4, iclass 36, count 0 2006.217.08:10:20.25#ibcon#about to read 5, iclass 36, count 0 2006.217.08:10:20.25#ibcon#read 5, iclass 36, count 0 2006.217.08:10:20.25#ibcon#about to read 6, iclass 36, count 0 2006.217.08:10:20.25#ibcon#read 6, iclass 36, count 0 2006.217.08:10:20.25#ibcon#end of sib2, iclass 36, count 0 2006.217.08:10:20.25#ibcon#*mode == 0, iclass 36, count 0 2006.217.08:10:20.25#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.217.08:10:20.25#ibcon#[26=FRQ=08,852.99\r\n] 2006.217.08:10:20.25#ibcon#*before write, iclass 36, count 0 2006.217.08:10:20.25#ibcon#enter sib2, iclass 36, count 0 2006.217.08:10:20.25#ibcon#flushed, iclass 36, count 0 2006.217.08:10:20.25#ibcon#about to write, iclass 36, count 0 2006.217.08:10:20.25#ibcon#wrote, iclass 36, count 0 2006.217.08:10:20.25#ibcon#about to read 3, iclass 36, count 0 2006.217.08:10:20.29#ibcon#read 3, iclass 36, count 0 2006.217.08:10:20.29#ibcon#about to read 4, iclass 36, count 0 2006.217.08:10:20.29#ibcon#read 4, iclass 36, count 0 2006.217.08:10:20.29#ibcon#about to read 5, iclass 36, count 0 2006.217.08:10:20.29#ibcon#read 5, iclass 36, count 0 2006.217.08:10:20.29#ibcon#about to read 6, iclass 36, count 0 2006.217.08:10:20.29#ibcon#read 6, iclass 36, count 0 2006.217.08:10:20.29#ibcon#end of sib2, iclass 36, count 0 2006.217.08:10:20.29#ibcon#*after write, iclass 36, count 0 2006.217.08:10:20.29#ibcon#*before return 0, iclass 36, count 0 2006.217.08:10:20.29#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.217.08:10:20.29#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.217.08:10:20.29#ibcon#about to clear, iclass 36 cls_cnt 0 2006.217.08:10:20.29#ibcon#cleared, iclass 36 cls_cnt 0 2006.217.08:10:20.29$vc4f8/va=8,7 2006.217.08:10:20.29#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.217.08:10:20.29#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.217.08:10:20.29#ibcon#ireg 11 cls_cnt 2 2006.217.08:10:20.29#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.217.08:10:20.35#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.217.08:10:20.35#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.217.08:10:20.35#ibcon#enter wrdev, iclass 38, count 2 2006.217.08:10:20.35#ibcon#first serial, iclass 38, count 2 2006.217.08:10:20.35#ibcon#enter sib2, iclass 38, count 2 2006.217.08:10:20.35#ibcon#flushed, iclass 38, count 2 2006.217.08:10:20.35#ibcon#about to write, iclass 38, count 2 2006.217.08:10:20.35#ibcon#wrote, iclass 38, count 2 2006.217.08:10:20.35#ibcon#about to read 3, iclass 38, count 2 2006.217.08:10:20.37#ibcon#read 3, iclass 38, count 2 2006.217.08:10:20.37#ibcon#about to read 4, iclass 38, count 2 2006.217.08:10:20.37#ibcon#read 4, iclass 38, count 2 2006.217.08:10:20.37#ibcon#about to read 5, iclass 38, count 2 2006.217.08:10:20.37#ibcon#read 5, iclass 38, count 2 2006.217.08:10:20.37#ibcon#about to read 6, iclass 38, count 2 2006.217.08:10:20.37#ibcon#read 6, iclass 38, count 2 2006.217.08:10:20.37#ibcon#end of sib2, iclass 38, count 2 2006.217.08:10:20.37#ibcon#*mode == 0, iclass 38, count 2 2006.217.08:10:20.37#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.217.08:10:20.37#ibcon#[25=AT08-07\r\n] 2006.217.08:10:20.37#ibcon#*before write, iclass 38, count 2 2006.217.08:10:20.37#ibcon#enter sib2, iclass 38, count 2 2006.217.08:10:20.37#ibcon#flushed, iclass 38, count 2 2006.217.08:10:20.37#ibcon#about to write, iclass 38, count 2 2006.217.08:10:20.37#ibcon#wrote, iclass 38, count 2 2006.217.08:10:20.37#ibcon#about to read 3, iclass 38, count 2 2006.217.08:10:20.40#ibcon#read 3, iclass 38, count 2 2006.217.08:10:20.40#ibcon#about to read 4, iclass 38, count 2 2006.217.08:10:20.40#ibcon#read 4, iclass 38, count 2 2006.217.08:10:20.40#ibcon#about to read 5, iclass 38, count 2 2006.217.08:10:20.40#ibcon#read 5, iclass 38, count 2 2006.217.08:10:20.40#ibcon#about to read 6, iclass 38, count 2 2006.217.08:10:20.40#ibcon#read 6, iclass 38, count 2 2006.217.08:10:20.40#ibcon#end of sib2, iclass 38, count 2 2006.217.08:10:20.40#ibcon#*after write, iclass 38, count 2 2006.217.08:10:20.40#ibcon#*before return 0, iclass 38, count 2 2006.217.08:10:20.40#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.217.08:10:20.40#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.217.08:10:20.40#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.217.08:10:20.40#ibcon#ireg 7 cls_cnt 0 2006.217.08:10:20.40#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.217.08:10:20.52#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.217.08:10:20.52#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.217.08:10:20.52#ibcon#enter wrdev, iclass 38, count 0 2006.217.08:10:20.52#ibcon#first serial, iclass 38, count 0 2006.217.08:10:20.52#ibcon#enter sib2, iclass 38, count 0 2006.217.08:10:20.52#ibcon#flushed, iclass 38, count 0 2006.217.08:10:20.52#ibcon#about to write, iclass 38, count 0 2006.217.08:10:20.52#ibcon#wrote, iclass 38, count 0 2006.217.08:10:20.52#ibcon#about to read 3, iclass 38, count 0 2006.217.08:10:20.54#ibcon#read 3, iclass 38, count 0 2006.217.08:10:20.54#ibcon#about to read 4, iclass 38, count 0 2006.217.08:10:20.54#ibcon#read 4, iclass 38, count 0 2006.217.08:10:20.54#ibcon#about to read 5, iclass 38, count 0 2006.217.08:10:20.54#ibcon#read 5, iclass 38, count 0 2006.217.08:10:20.54#ibcon#about to read 6, iclass 38, count 0 2006.217.08:10:20.54#ibcon#read 6, iclass 38, count 0 2006.217.08:10:20.54#ibcon#end of sib2, iclass 38, count 0 2006.217.08:10:20.54#ibcon#*mode == 0, iclass 38, count 0 2006.217.08:10:20.54#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.217.08:10:20.54#ibcon#[25=USB\r\n] 2006.217.08:10:20.54#ibcon#*before write, iclass 38, count 0 2006.217.08:10:20.54#ibcon#enter sib2, iclass 38, count 0 2006.217.08:10:20.54#ibcon#flushed, iclass 38, count 0 2006.217.08:10:20.54#ibcon#about to write, iclass 38, count 0 2006.217.08:10:20.54#ibcon#wrote, iclass 38, count 0 2006.217.08:10:20.54#ibcon#about to read 3, iclass 38, count 0 2006.217.08:10:20.57#ibcon#read 3, iclass 38, count 0 2006.217.08:10:20.57#ibcon#about to read 4, iclass 38, count 0 2006.217.08:10:20.57#ibcon#read 4, iclass 38, count 0 2006.217.08:10:20.57#ibcon#about to read 5, iclass 38, count 0 2006.217.08:10:20.57#ibcon#read 5, iclass 38, count 0 2006.217.08:10:20.57#ibcon#about to read 6, iclass 38, count 0 2006.217.08:10:20.57#ibcon#read 6, iclass 38, count 0 2006.217.08:10:20.57#ibcon#end of sib2, iclass 38, count 0 2006.217.08:10:20.57#ibcon#*after write, iclass 38, count 0 2006.217.08:10:20.57#ibcon#*before return 0, iclass 38, count 0 2006.217.08:10:20.57#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.217.08:10:20.57#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.217.08:10:20.57#ibcon#about to clear, iclass 38 cls_cnt 0 2006.217.08:10:20.57#ibcon#cleared, iclass 38 cls_cnt 0 2006.217.08:10:20.57$vc4f8/vblo=1,632.99 2006.217.08:10:20.57#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.217.08:10:20.57#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.217.08:10:20.57#ibcon#ireg 17 cls_cnt 0 2006.217.08:10:20.57#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.217.08:10:20.57#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.217.08:10:20.57#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.217.08:10:20.57#ibcon#enter wrdev, iclass 40, count 0 2006.217.08:10:20.57#ibcon#first serial, iclass 40, count 0 2006.217.08:10:20.57#ibcon#enter sib2, iclass 40, count 0 2006.217.08:10:20.57#ibcon#flushed, iclass 40, count 0 2006.217.08:10:20.57#ibcon#about to write, iclass 40, count 0 2006.217.08:10:20.57#ibcon#wrote, iclass 40, count 0 2006.217.08:10:20.57#ibcon#about to read 3, iclass 40, count 0 2006.217.08:10:20.59#ibcon#read 3, iclass 40, count 0 2006.217.08:10:20.59#ibcon#about to read 4, iclass 40, count 0 2006.217.08:10:20.59#ibcon#read 4, iclass 40, count 0 2006.217.08:10:20.59#ibcon#about to read 5, iclass 40, count 0 2006.217.08:10:20.59#ibcon#read 5, iclass 40, count 0 2006.217.08:10:20.59#ibcon#about to read 6, iclass 40, count 0 2006.217.08:10:20.59#ibcon#read 6, iclass 40, count 0 2006.217.08:10:20.59#ibcon#end of sib2, iclass 40, count 0 2006.217.08:10:20.59#ibcon#*mode == 0, iclass 40, count 0 2006.217.08:10:20.59#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.217.08:10:20.59#ibcon#[28=FRQ=01,632.99\r\n] 2006.217.08:10:20.59#ibcon#*before write, iclass 40, count 0 2006.217.08:10:20.59#ibcon#enter sib2, iclass 40, count 0 2006.217.08:10:20.59#ibcon#flushed, iclass 40, count 0 2006.217.08:10:20.59#ibcon#about to write, iclass 40, count 0 2006.217.08:10:20.59#ibcon#wrote, iclass 40, count 0 2006.217.08:10:20.59#ibcon#about to read 3, iclass 40, count 0 2006.217.08:10:20.63#ibcon#read 3, iclass 40, count 0 2006.217.08:10:20.63#ibcon#about to read 4, iclass 40, count 0 2006.217.08:10:20.63#ibcon#read 4, iclass 40, count 0 2006.217.08:10:20.63#ibcon#about to read 5, iclass 40, count 0 2006.217.08:10:20.63#ibcon#read 5, iclass 40, count 0 2006.217.08:10:20.63#ibcon#about to read 6, iclass 40, count 0 2006.217.08:10:20.63#ibcon#read 6, iclass 40, count 0 2006.217.08:10:20.63#ibcon#end of sib2, iclass 40, count 0 2006.217.08:10:20.63#ibcon#*after write, iclass 40, count 0 2006.217.08:10:20.63#ibcon#*before return 0, iclass 40, count 0 2006.217.08:10:20.63#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.217.08:10:20.63#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.217.08:10:20.63#ibcon#about to clear, iclass 40 cls_cnt 0 2006.217.08:10:20.63#ibcon#cleared, iclass 40 cls_cnt 0 2006.217.08:10:20.63$vc4f8/vb=1,4 2006.217.08:10:20.63#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.217.08:10:20.63#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.217.08:10:20.63#ibcon#ireg 11 cls_cnt 2 2006.217.08:10:20.63#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.217.08:10:20.63#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.217.08:10:20.63#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.217.08:10:20.63#ibcon#enter wrdev, iclass 4, count 2 2006.217.08:10:20.63#ibcon#first serial, iclass 4, count 2 2006.217.08:10:20.63#ibcon#enter sib2, iclass 4, count 2 2006.217.08:10:20.63#ibcon#flushed, iclass 4, count 2 2006.217.08:10:20.63#ibcon#about to write, iclass 4, count 2 2006.217.08:10:20.63#ibcon#wrote, iclass 4, count 2 2006.217.08:10:20.63#ibcon#about to read 3, iclass 4, count 2 2006.217.08:10:20.65#ibcon#read 3, iclass 4, count 2 2006.217.08:10:20.65#ibcon#about to read 4, iclass 4, count 2 2006.217.08:10:20.65#ibcon#read 4, iclass 4, count 2 2006.217.08:10:20.65#ibcon#about to read 5, iclass 4, count 2 2006.217.08:10:20.65#ibcon#read 5, iclass 4, count 2 2006.217.08:10:20.65#ibcon#about to read 6, iclass 4, count 2 2006.217.08:10:20.65#ibcon#read 6, iclass 4, count 2 2006.217.08:10:20.65#ibcon#end of sib2, iclass 4, count 2 2006.217.08:10:20.65#ibcon#*mode == 0, iclass 4, count 2 2006.217.08:10:20.65#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.217.08:10:20.65#ibcon#[27=AT01-04\r\n] 2006.217.08:10:20.65#ibcon#*before write, iclass 4, count 2 2006.217.08:10:20.65#ibcon#enter sib2, iclass 4, count 2 2006.217.08:10:20.65#ibcon#flushed, iclass 4, count 2 2006.217.08:10:20.65#ibcon#about to write, iclass 4, count 2 2006.217.08:10:20.65#ibcon#wrote, iclass 4, count 2 2006.217.08:10:20.65#ibcon#about to read 3, iclass 4, count 2 2006.217.08:10:20.68#ibcon#read 3, iclass 4, count 2 2006.217.08:10:20.68#ibcon#about to read 4, iclass 4, count 2 2006.217.08:10:20.68#ibcon#read 4, iclass 4, count 2 2006.217.08:10:20.68#ibcon#about to read 5, iclass 4, count 2 2006.217.08:10:20.68#ibcon#read 5, iclass 4, count 2 2006.217.08:10:20.68#ibcon#about to read 6, iclass 4, count 2 2006.217.08:10:20.68#ibcon#read 6, iclass 4, count 2 2006.217.08:10:20.68#ibcon#end of sib2, iclass 4, count 2 2006.217.08:10:20.68#ibcon#*after write, iclass 4, count 2 2006.217.08:10:20.68#ibcon#*before return 0, iclass 4, count 2 2006.217.08:10:20.68#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.217.08:10:20.68#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.217.08:10:20.68#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.217.08:10:20.68#ibcon#ireg 7 cls_cnt 0 2006.217.08:10:20.68#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.217.08:10:20.80#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.217.08:10:20.80#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.217.08:10:20.80#ibcon#enter wrdev, iclass 4, count 0 2006.217.08:10:20.80#ibcon#first serial, iclass 4, count 0 2006.217.08:10:20.80#ibcon#enter sib2, iclass 4, count 0 2006.217.08:10:20.80#ibcon#flushed, iclass 4, count 0 2006.217.08:10:20.80#ibcon#about to write, iclass 4, count 0 2006.217.08:10:20.80#ibcon#wrote, iclass 4, count 0 2006.217.08:10:20.80#ibcon#about to read 3, iclass 4, count 0 2006.217.08:10:20.82#ibcon#read 3, iclass 4, count 0 2006.217.08:10:20.82#ibcon#about to read 4, iclass 4, count 0 2006.217.08:10:20.82#ibcon#read 4, iclass 4, count 0 2006.217.08:10:20.82#ibcon#about to read 5, iclass 4, count 0 2006.217.08:10:20.82#ibcon#read 5, iclass 4, count 0 2006.217.08:10:20.82#ibcon#about to read 6, iclass 4, count 0 2006.217.08:10:20.82#ibcon#read 6, iclass 4, count 0 2006.217.08:10:20.82#ibcon#end of sib2, iclass 4, count 0 2006.217.08:10:20.82#ibcon#*mode == 0, iclass 4, count 0 2006.217.08:10:20.82#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.217.08:10:20.82#ibcon#[27=USB\r\n] 2006.217.08:10:20.82#ibcon#*before write, iclass 4, count 0 2006.217.08:10:20.82#ibcon#enter sib2, iclass 4, count 0 2006.217.08:10:20.82#ibcon#flushed, iclass 4, count 0 2006.217.08:10:20.82#ibcon#about to write, iclass 4, count 0 2006.217.08:10:20.82#ibcon#wrote, iclass 4, count 0 2006.217.08:10:20.82#ibcon#about to read 3, iclass 4, count 0 2006.217.08:10:20.85#ibcon#read 3, iclass 4, count 0 2006.217.08:10:20.85#ibcon#about to read 4, iclass 4, count 0 2006.217.08:10:20.85#ibcon#read 4, iclass 4, count 0 2006.217.08:10:20.85#ibcon#about to read 5, iclass 4, count 0 2006.217.08:10:20.85#ibcon#read 5, iclass 4, count 0 2006.217.08:10:20.85#ibcon#about to read 6, iclass 4, count 0 2006.217.08:10:20.85#ibcon#read 6, iclass 4, count 0 2006.217.08:10:20.85#ibcon#end of sib2, iclass 4, count 0 2006.217.08:10:20.85#ibcon#*after write, iclass 4, count 0 2006.217.08:10:20.85#ibcon#*before return 0, iclass 4, count 0 2006.217.08:10:20.85#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.217.08:10:20.85#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.217.08:10:20.85#ibcon#about to clear, iclass 4 cls_cnt 0 2006.217.08:10:20.85#ibcon#cleared, iclass 4 cls_cnt 0 2006.217.08:10:20.85$vc4f8/vblo=2,640.99 2006.217.08:10:20.85#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.217.08:10:20.85#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.217.08:10:20.85#ibcon#ireg 17 cls_cnt 0 2006.217.08:10:20.85#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.217.08:10:20.85#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.217.08:10:20.85#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.217.08:10:20.85#ibcon#enter wrdev, iclass 6, count 0 2006.217.08:10:20.85#ibcon#first serial, iclass 6, count 0 2006.217.08:10:20.85#ibcon#enter sib2, iclass 6, count 0 2006.217.08:10:20.85#ibcon#flushed, iclass 6, count 0 2006.217.08:10:20.85#ibcon#about to write, iclass 6, count 0 2006.217.08:10:20.85#ibcon#wrote, iclass 6, count 0 2006.217.08:10:20.85#ibcon#about to read 3, iclass 6, count 0 2006.217.08:10:20.87#ibcon#read 3, iclass 6, count 0 2006.217.08:10:20.87#ibcon#about to read 4, iclass 6, count 0 2006.217.08:10:20.87#ibcon#read 4, iclass 6, count 0 2006.217.08:10:20.87#ibcon#about to read 5, iclass 6, count 0 2006.217.08:10:20.87#ibcon#read 5, iclass 6, count 0 2006.217.08:10:20.87#ibcon#about to read 6, iclass 6, count 0 2006.217.08:10:20.87#ibcon#read 6, iclass 6, count 0 2006.217.08:10:20.87#ibcon#end of sib2, iclass 6, count 0 2006.217.08:10:20.87#ibcon#*mode == 0, iclass 6, count 0 2006.217.08:10:20.87#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.217.08:10:20.87#ibcon#[28=FRQ=02,640.99\r\n] 2006.217.08:10:20.87#ibcon#*before write, iclass 6, count 0 2006.217.08:10:20.87#ibcon#enter sib2, iclass 6, count 0 2006.217.08:10:20.87#ibcon#flushed, iclass 6, count 0 2006.217.08:10:20.87#ibcon#about to write, iclass 6, count 0 2006.217.08:10:20.87#ibcon#wrote, iclass 6, count 0 2006.217.08:10:20.87#ibcon#about to read 3, iclass 6, count 0 2006.217.08:10:20.91#ibcon#read 3, iclass 6, count 0 2006.217.08:10:20.91#ibcon#about to read 4, iclass 6, count 0 2006.217.08:10:20.91#ibcon#read 4, iclass 6, count 0 2006.217.08:10:20.91#ibcon#about to read 5, iclass 6, count 0 2006.217.08:10:20.91#ibcon#read 5, iclass 6, count 0 2006.217.08:10:20.91#ibcon#about to read 6, iclass 6, count 0 2006.217.08:10:20.91#ibcon#read 6, iclass 6, count 0 2006.217.08:10:20.91#ibcon#end of sib2, iclass 6, count 0 2006.217.08:10:20.91#ibcon#*after write, iclass 6, count 0 2006.217.08:10:20.91#ibcon#*before return 0, iclass 6, count 0 2006.217.08:10:20.91#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.217.08:10:20.91#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.217.08:10:20.91#ibcon#about to clear, iclass 6 cls_cnt 0 2006.217.08:10:20.91#ibcon#cleared, iclass 6 cls_cnt 0 2006.217.08:10:20.91$vc4f8/vb=2,4 2006.217.08:10:20.91#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.217.08:10:20.91#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.217.08:10:20.91#ibcon#ireg 11 cls_cnt 2 2006.217.08:10:20.91#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.217.08:10:20.97#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.217.08:10:20.97#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.217.08:10:20.97#ibcon#enter wrdev, iclass 10, count 2 2006.217.08:10:20.97#ibcon#first serial, iclass 10, count 2 2006.217.08:10:20.97#ibcon#enter sib2, iclass 10, count 2 2006.217.08:10:20.97#ibcon#flushed, iclass 10, count 2 2006.217.08:10:20.97#ibcon#about to write, iclass 10, count 2 2006.217.08:10:20.97#ibcon#wrote, iclass 10, count 2 2006.217.08:10:20.97#ibcon#about to read 3, iclass 10, count 2 2006.217.08:10:20.99#ibcon#read 3, iclass 10, count 2 2006.217.08:10:20.99#ibcon#about to read 4, iclass 10, count 2 2006.217.08:10:20.99#ibcon#read 4, iclass 10, count 2 2006.217.08:10:20.99#ibcon#about to read 5, iclass 10, count 2 2006.217.08:10:20.99#ibcon#read 5, iclass 10, count 2 2006.217.08:10:20.99#ibcon#about to read 6, iclass 10, count 2 2006.217.08:10:20.99#ibcon#read 6, iclass 10, count 2 2006.217.08:10:20.99#ibcon#end of sib2, iclass 10, count 2 2006.217.08:10:20.99#ibcon#*mode == 0, iclass 10, count 2 2006.217.08:10:20.99#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.217.08:10:20.99#ibcon#[27=AT02-04\r\n] 2006.217.08:10:20.99#ibcon#*before write, iclass 10, count 2 2006.217.08:10:20.99#ibcon#enter sib2, iclass 10, count 2 2006.217.08:10:20.99#ibcon#flushed, iclass 10, count 2 2006.217.08:10:20.99#ibcon#about to write, iclass 10, count 2 2006.217.08:10:20.99#ibcon#wrote, iclass 10, count 2 2006.217.08:10:20.99#ibcon#about to read 3, iclass 10, count 2 2006.217.08:10:21.02#ibcon#read 3, iclass 10, count 2 2006.217.08:10:21.02#ibcon#about to read 4, iclass 10, count 2 2006.217.08:10:21.02#ibcon#read 4, iclass 10, count 2 2006.217.08:10:21.02#ibcon#about to read 5, iclass 10, count 2 2006.217.08:10:21.02#ibcon#read 5, iclass 10, count 2 2006.217.08:10:21.02#ibcon#about to read 6, iclass 10, count 2 2006.217.08:10:21.02#ibcon#read 6, iclass 10, count 2 2006.217.08:10:21.02#ibcon#end of sib2, iclass 10, count 2 2006.217.08:10:21.02#ibcon#*after write, iclass 10, count 2 2006.217.08:10:21.02#ibcon#*before return 0, iclass 10, count 2 2006.217.08:10:21.02#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.217.08:10:21.02#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.217.08:10:21.02#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.217.08:10:21.02#ibcon#ireg 7 cls_cnt 0 2006.217.08:10:21.02#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.217.08:10:21.14#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.217.08:10:21.14#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.217.08:10:21.14#ibcon#enter wrdev, iclass 10, count 0 2006.217.08:10:21.14#ibcon#first serial, iclass 10, count 0 2006.217.08:10:21.14#ibcon#enter sib2, iclass 10, count 0 2006.217.08:10:21.14#ibcon#flushed, iclass 10, count 0 2006.217.08:10:21.14#ibcon#about to write, iclass 10, count 0 2006.217.08:10:21.14#ibcon#wrote, iclass 10, count 0 2006.217.08:10:21.14#ibcon#about to read 3, iclass 10, count 0 2006.217.08:10:21.16#ibcon#read 3, iclass 10, count 0 2006.217.08:10:21.16#ibcon#about to read 4, iclass 10, count 0 2006.217.08:10:21.16#ibcon#read 4, iclass 10, count 0 2006.217.08:10:21.16#ibcon#about to read 5, iclass 10, count 0 2006.217.08:10:21.16#ibcon#read 5, iclass 10, count 0 2006.217.08:10:21.16#ibcon#about to read 6, iclass 10, count 0 2006.217.08:10:21.16#ibcon#read 6, iclass 10, count 0 2006.217.08:10:21.16#ibcon#end of sib2, iclass 10, count 0 2006.217.08:10:21.16#ibcon#*mode == 0, iclass 10, count 0 2006.217.08:10:21.16#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.217.08:10:21.16#ibcon#[27=USB\r\n] 2006.217.08:10:21.16#ibcon#*before write, iclass 10, count 0 2006.217.08:10:21.16#ibcon#enter sib2, iclass 10, count 0 2006.217.08:10:21.16#ibcon#flushed, iclass 10, count 0 2006.217.08:10:21.16#ibcon#about to write, iclass 10, count 0 2006.217.08:10:21.16#ibcon#wrote, iclass 10, count 0 2006.217.08:10:21.16#ibcon#about to read 3, iclass 10, count 0 2006.217.08:10:21.19#ibcon#read 3, iclass 10, count 0 2006.217.08:10:21.19#ibcon#about to read 4, iclass 10, count 0 2006.217.08:10:21.19#ibcon#read 4, iclass 10, count 0 2006.217.08:10:21.19#ibcon#about to read 5, iclass 10, count 0 2006.217.08:10:21.19#ibcon#read 5, iclass 10, count 0 2006.217.08:10:21.19#ibcon#about to read 6, iclass 10, count 0 2006.217.08:10:21.19#ibcon#read 6, iclass 10, count 0 2006.217.08:10:21.19#ibcon#end of sib2, iclass 10, count 0 2006.217.08:10:21.19#ibcon#*after write, iclass 10, count 0 2006.217.08:10:21.19#ibcon#*before return 0, iclass 10, count 0 2006.217.08:10:21.19#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.217.08:10:21.19#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.217.08:10:21.19#ibcon#about to clear, iclass 10 cls_cnt 0 2006.217.08:10:21.19#ibcon#cleared, iclass 10 cls_cnt 0 2006.217.08:10:21.19$vc4f8/vblo=3,656.99 2006.217.08:10:21.19#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.217.08:10:21.19#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.217.08:10:21.19#ibcon#ireg 17 cls_cnt 0 2006.217.08:10:21.19#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.217.08:10:21.19#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.217.08:10:21.19#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.217.08:10:21.19#ibcon#enter wrdev, iclass 12, count 0 2006.217.08:10:21.19#ibcon#first serial, iclass 12, count 0 2006.217.08:10:21.19#ibcon#enter sib2, iclass 12, count 0 2006.217.08:10:21.19#ibcon#flushed, iclass 12, count 0 2006.217.08:10:21.19#ibcon#about to write, iclass 12, count 0 2006.217.08:10:21.19#ibcon#wrote, iclass 12, count 0 2006.217.08:10:21.19#ibcon#about to read 3, iclass 12, count 0 2006.217.08:10:21.21#ibcon#read 3, iclass 12, count 0 2006.217.08:10:21.21#ibcon#about to read 4, iclass 12, count 0 2006.217.08:10:21.21#ibcon#read 4, iclass 12, count 0 2006.217.08:10:21.21#ibcon#about to read 5, iclass 12, count 0 2006.217.08:10:21.21#ibcon#read 5, iclass 12, count 0 2006.217.08:10:21.21#ibcon#about to read 6, iclass 12, count 0 2006.217.08:10:21.21#ibcon#read 6, iclass 12, count 0 2006.217.08:10:21.21#ibcon#end of sib2, iclass 12, count 0 2006.217.08:10:21.21#ibcon#*mode == 0, iclass 12, count 0 2006.217.08:10:21.21#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.217.08:10:21.21#ibcon#[28=FRQ=03,656.99\r\n] 2006.217.08:10:21.21#ibcon#*before write, iclass 12, count 0 2006.217.08:10:21.21#ibcon#enter sib2, iclass 12, count 0 2006.217.08:10:21.21#ibcon#flushed, iclass 12, count 0 2006.217.08:10:21.21#ibcon#about to write, iclass 12, count 0 2006.217.08:10:21.21#ibcon#wrote, iclass 12, count 0 2006.217.08:10:21.21#ibcon#about to read 3, iclass 12, count 0 2006.217.08:10:21.25#ibcon#read 3, iclass 12, count 0 2006.217.08:10:21.25#ibcon#about to read 4, iclass 12, count 0 2006.217.08:10:21.25#ibcon#read 4, iclass 12, count 0 2006.217.08:10:21.25#ibcon#about to read 5, iclass 12, count 0 2006.217.08:10:21.25#ibcon#read 5, iclass 12, count 0 2006.217.08:10:21.25#ibcon#about to read 6, iclass 12, count 0 2006.217.08:10:21.25#ibcon#read 6, iclass 12, count 0 2006.217.08:10:21.25#ibcon#end of sib2, iclass 12, count 0 2006.217.08:10:21.25#ibcon#*after write, iclass 12, count 0 2006.217.08:10:21.25#ibcon#*before return 0, iclass 12, count 0 2006.217.08:10:21.25#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.217.08:10:21.25#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.217.08:10:21.25#ibcon#about to clear, iclass 12 cls_cnt 0 2006.217.08:10:21.25#ibcon#cleared, iclass 12 cls_cnt 0 2006.217.08:10:21.25$vc4f8/vb=3,4 2006.217.08:10:21.25#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.217.08:10:21.25#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.217.08:10:21.25#ibcon#ireg 11 cls_cnt 2 2006.217.08:10:21.25#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.217.08:10:21.31#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.217.08:10:21.31#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.217.08:10:21.31#ibcon#enter wrdev, iclass 14, count 2 2006.217.08:10:21.31#ibcon#first serial, iclass 14, count 2 2006.217.08:10:21.31#ibcon#enter sib2, iclass 14, count 2 2006.217.08:10:21.31#ibcon#flushed, iclass 14, count 2 2006.217.08:10:21.31#ibcon#about to write, iclass 14, count 2 2006.217.08:10:21.31#ibcon#wrote, iclass 14, count 2 2006.217.08:10:21.31#ibcon#about to read 3, iclass 14, count 2 2006.217.08:10:21.33#ibcon#read 3, iclass 14, count 2 2006.217.08:10:21.33#ibcon#about to read 4, iclass 14, count 2 2006.217.08:10:21.33#ibcon#read 4, iclass 14, count 2 2006.217.08:10:21.33#ibcon#about to read 5, iclass 14, count 2 2006.217.08:10:21.33#ibcon#read 5, iclass 14, count 2 2006.217.08:10:21.33#ibcon#about to read 6, iclass 14, count 2 2006.217.08:10:21.33#ibcon#read 6, iclass 14, count 2 2006.217.08:10:21.33#ibcon#end of sib2, iclass 14, count 2 2006.217.08:10:21.33#ibcon#*mode == 0, iclass 14, count 2 2006.217.08:10:21.33#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.217.08:10:21.33#ibcon#[27=AT03-04\r\n] 2006.217.08:10:21.33#ibcon#*before write, iclass 14, count 2 2006.217.08:10:21.33#ibcon#enter sib2, iclass 14, count 2 2006.217.08:10:21.33#ibcon#flushed, iclass 14, count 2 2006.217.08:10:21.33#ibcon#about to write, iclass 14, count 2 2006.217.08:10:21.33#ibcon#wrote, iclass 14, count 2 2006.217.08:10:21.33#ibcon#about to read 3, iclass 14, count 2 2006.217.08:10:21.36#ibcon#read 3, iclass 14, count 2 2006.217.08:10:21.36#ibcon#about to read 4, iclass 14, count 2 2006.217.08:10:21.36#ibcon#read 4, iclass 14, count 2 2006.217.08:10:21.36#ibcon#about to read 5, iclass 14, count 2 2006.217.08:10:21.36#ibcon#read 5, iclass 14, count 2 2006.217.08:10:21.36#ibcon#about to read 6, iclass 14, count 2 2006.217.08:10:21.36#ibcon#read 6, iclass 14, count 2 2006.217.08:10:21.36#ibcon#end of sib2, iclass 14, count 2 2006.217.08:10:21.36#ibcon#*after write, iclass 14, count 2 2006.217.08:10:21.36#ibcon#*before return 0, iclass 14, count 2 2006.217.08:10:21.36#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.217.08:10:21.36#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.217.08:10:21.36#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.217.08:10:21.36#ibcon#ireg 7 cls_cnt 0 2006.217.08:10:21.36#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.217.08:10:21.48#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.217.08:10:21.48#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.217.08:10:21.48#ibcon#enter wrdev, iclass 14, count 0 2006.217.08:10:21.48#ibcon#first serial, iclass 14, count 0 2006.217.08:10:21.48#ibcon#enter sib2, iclass 14, count 0 2006.217.08:10:21.48#ibcon#flushed, iclass 14, count 0 2006.217.08:10:21.48#ibcon#about to write, iclass 14, count 0 2006.217.08:10:21.48#ibcon#wrote, iclass 14, count 0 2006.217.08:10:21.48#ibcon#about to read 3, iclass 14, count 0 2006.217.08:10:21.50#ibcon#read 3, iclass 14, count 0 2006.217.08:10:21.50#ibcon#about to read 4, iclass 14, count 0 2006.217.08:10:21.50#ibcon#read 4, iclass 14, count 0 2006.217.08:10:21.50#ibcon#about to read 5, iclass 14, count 0 2006.217.08:10:21.50#ibcon#read 5, iclass 14, count 0 2006.217.08:10:21.50#ibcon#about to read 6, iclass 14, count 0 2006.217.08:10:21.50#ibcon#read 6, iclass 14, count 0 2006.217.08:10:21.50#ibcon#end of sib2, iclass 14, count 0 2006.217.08:10:21.50#ibcon#*mode == 0, iclass 14, count 0 2006.217.08:10:21.50#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.217.08:10:21.50#ibcon#[27=USB\r\n] 2006.217.08:10:21.50#ibcon#*before write, iclass 14, count 0 2006.217.08:10:21.50#ibcon#enter sib2, iclass 14, count 0 2006.217.08:10:21.50#ibcon#flushed, iclass 14, count 0 2006.217.08:10:21.50#ibcon#about to write, iclass 14, count 0 2006.217.08:10:21.50#ibcon#wrote, iclass 14, count 0 2006.217.08:10:21.50#ibcon#about to read 3, iclass 14, count 0 2006.217.08:10:21.53#ibcon#read 3, iclass 14, count 0 2006.217.08:10:21.53#ibcon#about to read 4, iclass 14, count 0 2006.217.08:10:21.53#ibcon#read 4, iclass 14, count 0 2006.217.08:10:21.53#ibcon#about to read 5, iclass 14, count 0 2006.217.08:10:21.53#ibcon#read 5, iclass 14, count 0 2006.217.08:10:21.53#ibcon#about to read 6, iclass 14, count 0 2006.217.08:10:21.53#ibcon#read 6, iclass 14, count 0 2006.217.08:10:21.53#ibcon#end of sib2, iclass 14, count 0 2006.217.08:10:21.53#ibcon#*after write, iclass 14, count 0 2006.217.08:10:21.53#ibcon#*before return 0, iclass 14, count 0 2006.217.08:10:21.53#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.217.08:10:21.53#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.217.08:10:21.53#ibcon#about to clear, iclass 14 cls_cnt 0 2006.217.08:10:21.53#ibcon#cleared, iclass 14 cls_cnt 0 2006.217.08:10:21.53$vc4f8/vblo=4,712.99 2006.217.08:10:21.53#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.217.08:10:21.53#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.217.08:10:21.53#ibcon#ireg 17 cls_cnt 0 2006.217.08:10:21.53#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.217.08:10:21.53#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.217.08:10:21.53#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.217.08:10:21.53#ibcon#enter wrdev, iclass 16, count 0 2006.217.08:10:21.53#ibcon#first serial, iclass 16, count 0 2006.217.08:10:21.53#ibcon#enter sib2, iclass 16, count 0 2006.217.08:10:21.53#ibcon#flushed, iclass 16, count 0 2006.217.08:10:21.53#ibcon#about to write, iclass 16, count 0 2006.217.08:10:21.53#ibcon#wrote, iclass 16, count 0 2006.217.08:10:21.53#ibcon#about to read 3, iclass 16, count 0 2006.217.08:10:21.55#ibcon#read 3, iclass 16, count 0 2006.217.08:10:21.55#ibcon#about to read 4, iclass 16, count 0 2006.217.08:10:21.55#ibcon#read 4, iclass 16, count 0 2006.217.08:10:21.55#ibcon#about to read 5, iclass 16, count 0 2006.217.08:10:21.55#ibcon#read 5, iclass 16, count 0 2006.217.08:10:21.55#ibcon#about to read 6, iclass 16, count 0 2006.217.08:10:21.55#ibcon#read 6, iclass 16, count 0 2006.217.08:10:21.55#ibcon#end of sib2, iclass 16, count 0 2006.217.08:10:21.55#ibcon#*mode == 0, iclass 16, count 0 2006.217.08:10:21.55#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.217.08:10:21.55#ibcon#[28=FRQ=04,712.99\r\n] 2006.217.08:10:21.55#ibcon#*before write, iclass 16, count 0 2006.217.08:10:21.55#ibcon#enter sib2, iclass 16, count 0 2006.217.08:10:21.55#ibcon#flushed, iclass 16, count 0 2006.217.08:10:21.55#ibcon#about to write, iclass 16, count 0 2006.217.08:10:21.55#ibcon#wrote, iclass 16, count 0 2006.217.08:10:21.55#ibcon#about to read 3, iclass 16, count 0 2006.217.08:10:21.60#ibcon#read 3, iclass 16, count 0 2006.217.08:10:21.60#ibcon#about to read 4, iclass 16, count 0 2006.217.08:10:21.60#ibcon#read 4, iclass 16, count 0 2006.217.08:10:21.60#ibcon#about to read 5, iclass 16, count 0 2006.217.08:10:21.60#ibcon#read 5, iclass 16, count 0 2006.217.08:10:21.60#ibcon#about to read 6, iclass 16, count 0 2006.217.08:10:21.60#ibcon#read 6, iclass 16, count 0 2006.217.08:10:21.60#ibcon#end of sib2, iclass 16, count 0 2006.217.08:10:21.60#ibcon#*after write, iclass 16, count 0 2006.217.08:10:21.60#ibcon#*before return 0, iclass 16, count 0 2006.217.08:10:21.60#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.217.08:10:21.60#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.217.08:10:21.60#ibcon#about to clear, iclass 16 cls_cnt 0 2006.217.08:10:21.60#ibcon#cleared, iclass 16 cls_cnt 0 2006.217.08:10:21.60$vc4f8/vb=4,4 2006.217.08:10:21.60#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.217.08:10:21.60#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.217.08:10:21.60#ibcon#ireg 11 cls_cnt 2 2006.217.08:10:21.60#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.217.08:10:21.65#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.217.08:10:21.65#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.217.08:10:21.65#ibcon#enter wrdev, iclass 18, count 2 2006.217.08:10:21.65#ibcon#first serial, iclass 18, count 2 2006.217.08:10:21.65#ibcon#enter sib2, iclass 18, count 2 2006.217.08:10:21.65#ibcon#flushed, iclass 18, count 2 2006.217.08:10:21.65#ibcon#about to write, iclass 18, count 2 2006.217.08:10:21.65#ibcon#wrote, iclass 18, count 2 2006.217.08:10:21.65#ibcon#about to read 3, iclass 18, count 2 2006.217.08:10:21.67#ibcon#read 3, iclass 18, count 2 2006.217.08:10:21.67#ibcon#about to read 4, iclass 18, count 2 2006.217.08:10:21.67#ibcon#read 4, iclass 18, count 2 2006.217.08:10:21.67#ibcon#about to read 5, iclass 18, count 2 2006.217.08:10:21.67#ibcon#read 5, iclass 18, count 2 2006.217.08:10:21.67#ibcon#about to read 6, iclass 18, count 2 2006.217.08:10:21.67#ibcon#read 6, iclass 18, count 2 2006.217.08:10:21.67#ibcon#end of sib2, iclass 18, count 2 2006.217.08:10:21.67#ibcon#*mode == 0, iclass 18, count 2 2006.217.08:10:21.67#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.217.08:10:21.67#ibcon#[27=AT04-04\r\n] 2006.217.08:10:21.67#ibcon#*before write, iclass 18, count 2 2006.217.08:10:21.67#ibcon#enter sib2, iclass 18, count 2 2006.217.08:10:21.67#ibcon#flushed, iclass 18, count 2 2006.217.08:10:21.67#ibcon#about to write, iclass 18, count 2 2006.217.08:10:21.67#ibcon#wrote, iclass 18, count 2 2006.217.08:10:21.67#ibcon#about to read 3, iclass 18, count 2 2006.217.08:10:21.70#ibcon#read 3, iclass 18, count 2 2006.217.08:10:21.70#ibcon#about to read 4, iclass 18, count 2 2006.217.08:10:21.70#ibcon#read 4, iclass 18, count 2 2006.217.08:10:21.70#ibcon#about to read 5, iclass 18, count 2 2006.217.08:10:21.70#ibcon#read 5, iclass 18, count 2 2006.217.08:10:21.70#ibcon#about to read 6, iclass 18, count 2 2006.217.08:10:21.70#ibcon#read 6, iclass 18, count 2 2006.217.08:10:21.70#ibcon#end of sib2, iclass 18, count 2 2006.217.08:10:21.70#ibcon#*after write, iclass 18, count 2 2006.217.08:10:21.70#ibcon#*before return 0, iclass 18, count 2 2006.217.08:10:21.70#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.217.08:10:21.70#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.217.08:10:21.70#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.217.08:10:21.70#ibcon#ireg 7 cls_cnt 0 2006.217.08:10:21.70#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.217.08:10:21.82#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.217.08:10:21.82#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.217.08:10:21.82#ibcon#enter wrdev, iclass 18, count 0 2006.217.08:10:21.82#ibcon#first serial, iclass 18, count 0 2006.217.08:10:21.82#ibcon#enter sib2, iclass 18, count 0 2006.217.08:10:21.82#ibcon#flushed, iclass 18, count 0 2006.217.08:10:21.82#ibcon#about to write, iclass 18, count 0 2006.217.08:10:21.82#ibcon#wrote, iclass 18, count 0 2006.217.08:10:21.82#ibcon#about to read 3, iclass 18, count 0 2006.217.08:10:21.84#ibcon#read 3, iclass 18, count 0 2006.217.08:10:21.84#ibcon#about to read 4, iclass 18, count 0 2006.217.08:10:21.84#ibcon#read 4, iclass 18, count 0 2006.217.08:10:21.84#ibcon#about to read 5, iclass 18, count 0 2006.217.08:10:21.84#ibcon#read 5, iclass 18, count 0 2006.217.08:10:21.84#ibcon#about to read 6, iclass 18, count 0 2006.217.08:10:21.84#ibcon#read 6, iclass 18, count 0 2006.217.08:10:21.84#ibcon#end of sib2, iclass 18, count 0 2006.217.08:10:21.84#ibcon#*mode == 0, iclass 18, count 0 2006.217.08:10:21.84#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.217.08:10:21.84#ibcon#[27=USB\r\n] 2006.217.08:10:21.84#ibcon#*before write, iclass 18, count 0 2006.217.08:10:21.84#ibcon#enter sib2, iclass 18, count 0 2006.217.08:10:21.84#ibcon#flushed, iclass 18, count 0 2006.217.08:10:21.84#ibcon#about to write, iclass 18, count 0 2006.217.08:10:21.84#ibcon#wrote, iclass 18, count 0 2006.217.08:10:21.84#ibcon#about to read 3, iclass 18, count 0 2006.217.08:10:21.87#ibcon#read 3, iclass 18, count 0 2006.217.08:10:21.87#ibcon#about to read 4, iclass 18, count 0 2006.217.08:10:21.87#ibcon#read 4, iclass 18, count 0 2006.217.08:10:21.87#ibcon#about to read 5, iclass 18, count 0 2006.217.08:10:21.87#ibcon#read 5, iclass 18, count 0 2006.217.08:10:21.87#ibcon#about to read 6, iclass 18, count 0 2006.217.08:10:21.87#ibcon#read 6, iclass 18, count 0 2006.217.08:10:21.87#ibcon#end of sib2, iclass 18, count 0 2006.217.08:10:21.87#ibcon#*after write, iclass 18, count 0 2006.217.08:10:21.87#ibcon#*before return 0, iclass 18, count 0 2006.217.08:10:21.87#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.217.08:10:21.87#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.217.08:10:21.87#ibcon#about to clear, iclass 18 cls_cnt 0 2006.217.08:10:21.87#ibcon#cleared, iclass 18 cls_cnt 0 2006.217.08:10:21.87$vc4f8/vblo=5,744.99 2006.217.08:10:21.87#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.217.08:10:21.87#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.217.08:10:21.87#ibcon#ireg 17 cls_cnt 0 2006.217.08:10:21.87#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.217.08:10:21.87#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.217.08:10:21.87#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.217.08:10:21.87#ibcon#enter wrdev, iclass 20, count 0 2006.217.08:10:21.87#ibcon#first serial, iclass 20, count 0 2006.217.08:10:21.87#ibcon#enter sib2, iclass 20, count 0 2006.217.08:10:21.87#ibcon#flushed, iclass 20, count 0 2006.217.08:10:21.87#ibcon#about to write, iclass 20, count 0 2006.217.08:10:21.87#ibcon#wrote, iclass 20, count 0 2006.217.08:10:21.87#ibcon#about to read 3, iclass 20, count 0 2006.217.08:10:21.89#ibcon#read 3, iclass 20, count 0 2006.217.08:10:21.89#ibcon#about to read 4, iclass 20, count 0 2006.217.08:10:21.89#ibcon#read 4, iclass 20, count 0 2006.217.08:10:21.89#ibcon#about to read 5, iclass 20, count 0 2006.217.08:10:21.89#ibcon#read 5, iclass 20, count 0 2006.217.08:10:21.89#ibcon#about to read 6, iclass 20, count 0 2006.217.08:10:21.89#ibcon#read 6, iclass 20, count 0 2006.217.08:10:21.89#ibcon#end of sib2, iclass 20, count 0 2006.217.08:10:21.89#ibcon#*mode == 0, iclass 20, count 0 2006.217.08:10:21.89#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.217.08:10:21.89#ibcon#[28=FRQ=05,744.99\r\n] 2006.217.08:10:21.89#ibcon#*before write, iclass 20, count 0 2006.217.08:10:21.89#ibcon#enter sib2, iclass 20, count 0 2006.217.08:10:21.89#ibcon#flushed, iclass 20, count 0 2006.217.08:10:21.89#ibcon#about to write, iclass 20, count 0 2006.217.08:10:21.89#ibcon#wrote, iclass 20, count 0 2006.217.08:10:21.89#ibcon#about to read 3, iclass 20, count 0 2006.217.08:10:21.93#ibcon#read 3, iclass 20, count 0 2006.217.08:10:21.93#ibcon#about to read 4, iclass 20, count 0 2006.217.08:10:21.93#ibcon#read 4, iclass 20, count 0 2006.217.08:10:21.93#ibcon#about to read 5, iclass 20, count 0 2006.217.08:10:21.93#ibcon#read 5, iclass 20, count 0 2006.217.08:10:21.93#ibcon#about to read 6, iclass 20, count 0 2006.217.08:10:21.93#ibcon#read 6, iclass 20, count 0 2006.217.08:10:21.93#ibcon#end of sib2, iclass 20, count 0 2006.217.08:10:21.93#ibcon#*after write, iclass 20, count 0 2006.217.08:10:21.93#ibcon#*before return 0, iclass 20, count 0 2006.217.08:10:21.93#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.217.08:10:21.93#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.217.08:10:21.93#ibcon#about to clear, iclass 20 cls_cnt 0 2006.217.08:10:21.93#ibcon#cleared, iclass 20 cls_cnt 0 2006.217.08:10:21.93$vc4f8/vb=5,4 2006.217.08:10:21.93#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.217.08:10:21.93#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.217.08:10:21.93#ibcon#ireg 11 cls_cnt 2 2006.217.08:10:21.93#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.217.08:10:21.99#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.217.08:10:21.99#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.217.08:10:21.99#ibcon#enter wrdev, iclass 22, count 2 2006.217.08:10:21.99#ibcon#first serial, iclass 22, count 2 2006.217.08:10:21.99#ibcon#enter sib2, iclass 22, count 2 2006.217.08:10:21.99#ibcon#flushed, iclass 22, count 2 2006.217.08:10:21.99#ibcon#about to write, iclass 22, count 2 2006.217.08:10:21.99#ibcon#wrote, iclass 22, count 2 2006.217.08:10:21.99#ibcon#about to read 3, iclass 22, count 2 2006.217.08:10:22.01#ibcon#read 3, iclass 22, count 2 2006.217.08:10:22.01#ibcon#about to read 4, iclass 22, count 2 2006.217.08:10:22.01#ibcon#read 4, iclass 22, count 2 2006.217.08:10:22.01#ibcon#about to read 5, iclass 22, count 2 2006.217.08:10:22.01#ibcon#read 5, iclass 22, count 2 2006.217.08:10:22.01#ibcon#about to read 6, iclass 22, count 2 2006.217.08:10:22.01#ibcon#read 6, iclass 22, count 2 2006.217.08:10:22.01#ibcon#end of sib2, iclass 22, count 2 2006.217.08:10:22.01#ibcon#*mode == 0, iclass 22, count 2 2006.217.08:10:22.01#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.217.08:10:22.01#ibcon#[27=AT05-04\r\n] 2006.217.08:10:22.01#ibcon#*before write, iclass 22, count 2 2006.217.08:10:22.01#ibcon#enter sib2, iclass 22, count 2 2006.217.08:10:22.01#ibcon#flushed, iclass 22, count 2 2006.217.08:10:22.01#ibcon#about to write, iclass 22, count 2 2006.217.08:10:22.01#ibcon#wrote, iclass 22, count 2 2006.217.08:10:22.01#ibcon#about to read 3, iclass 22, count 2 2006.217.08:10:22.04#ibcon#read 3, iclass 22, count 2 2006.217.08:10:22.04#ibcon#about to read 4, iclass 22, count 2 2006.217.08:10:22.04#ibcon#read 4, iclass 22, count 2 2006.217.08:10:22.04#ibcon#about to read 5, iclass 22, count 2 2006.217.08:10:22.04#ibcon#read 5, iclass 22, count 2 2006.217.08:10:22.04#ibcon#about to read 6, iclass 22, count 2 2006.217.08:10:22.04#ibcon#read 6, iclass 22, count 2 2006.217.08:10:22.04#ibcon#end of sib2, iclass 22, count 2 2006.217.08:10:22.04#ibcon#*after write, iclass 22, count 2 2006.217.08:10:22.04#ibcon#*before return 0, iclass 22, count 2 2006.217.08:10:22.04#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.217.08:10:22.04#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.217.08:10:22.04#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.217.08:10:22.04#ibcon#ireg 7 cls_cnt 0 2006.217.08:10:22.04#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.217.08:10:22.16#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.217.08:10:22.16#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.217.08:10:22.16#ibcon#enter wrdev, iclass 22, count 0 2006.217.08:10:22.16#ibcon#first serial, iclass 22, count 0 2006.217.08:10:22.16#ibcon#enter sib2, iclass 22, count 0 2006.217.08:10:22.16#ibcon#flushed, iclass 22, count 0 2006.217.08:10:22.16#ibcon#about to write, iclass 22, count 0 2006.217.08:10:22.16#ibcon#wrote, iclass 22, count 0 2006.217.08:10:22.16#ibcon#about to read 3, iclass 22, count 0 2006.217.08:10:22.18#ibcon#read 3, iclass 22, count 0 2006.217.08:10:22.18#ibcon#about to read 4, iclass 22, count 0 2006.217.08:10:22.18#ibcon#read 4, iclass 22, count 0 2006.217.08:10:22.18#ibcon#about to read 5, iclass 22, count 0 2006.217.08:10:22.18#ibcon#read 5, iclass 22, count 0 2006.217.08:10:22.18#ibcon#about to read 6, iclass 22, count 0 2006.217.08:10:22.18#ibcon#read 6, iclass 22, count 0 2006.217.08:10:22.18#ibcon#end of sib2, iclass 22, count 0 2006.217.08:10:22.18#ibcon#*mode == 0, iclass 22, count 0 2006.217.08:10:22.18#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.217.08:10:22.18#ibcon#[27=USB\r\n] 2006.217.08:10:22.18#ibcon#*before write, iclass 22, count 0 2006.217.08:10:22.18#ibcon#enter sib2, iclass 22, count 0 2006.217.08:10:22.18#ibcon#flushed, iclass 22, count 0 2006.217.08:10:22.18#ibcon#about to write, iclass 22, count 0 2006.217.08:10:22.18#ibcon#wrote, iclass 22, count 0 2006.217.08:10:22.18#ibcon#about to read 3, iclass 22, count 0 2006.217.08:10:22.19#abcon#<5=/05 3.9 7.2 30.68 631008.6\r\n> 2006.217.08:10:22.21#abcon#{5=INTERFACE CLEAR} 2006.217.08:10:22.21#ibcon#read 3, iclass 22, count 0 2006.217.08:10:22.21#ibcon#about to read 4, iclass 22, count 0 2006.217.08:10:22.21#ibcon#read 4, iclass 22, count 0 2006.217.08:10:22.21#ibcon#about to read 5, iclass 22, count 0 2006.217.08:10:22.21#ibcon#read 5, iclass 22, count 0 2006.217.08:10:22.21#ibcon#about to read 6, iclass 22, count 0 2006.217.08:10:22.21#ibcon#read 6, iclass 22, count 0 2006.217.08:10:22.21#ibcon#end of sib2, iclass 22, count 0 2006.217.08:10:22.21#ibcon#*after write, iclass 22, count 0 2006.217.08:10:22.21#ibcon#*before return 0, iclass 22, count 0 2006.217.08:10:22.21#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.217.08:10:22.21#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.217.08:10:22.21#ibcon#about to clear, iclass 22 cls_cnt 0 2006.217.08:10:22.21#ibcon#cleared, iclass 22 cls_cnt 0 2006.217.08:10:22.21$vc4f8/vblo=6,752.99 2006.217.08:10:22.21#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.217.08:10:22.21#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.217.08:10:22.21#ibcon#ireg 17 cls_cnt 0 2006.217.08:10:22.21#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.217.08:10:22.21#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.217.08:10:22.21#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.217.08:10:22.21#ibcon#enter wrdev, iclass 27, count 0 2006.217.08:10:22.21#ibcon#first serial, iclass 27, count 0 2006.217.08:10:22.21#ibcon#enter sib2, iclass 27, count 0 2006.217.08:10:22.21#ibcon#flushed, iclass 27, count 0 2006.217.08:10:22.21#ibcon#about to write, iclass 27, count 0 2006.217.08:10:22.21#ibcon#wrote, iclass 27, count 0 2006.217.08:10:22.21#ibcon#about to read 3, iclass 27, count 0 2006.217.08:10:22.23#ibcon#read 3, iclass 27, count 0 2006.217.08:10:22.23#ibcon#about to read 4, iclass 27, count 0 2006.217.08:10:22.23#ibcon#read 4, iclass 27, count 0 2006.217.08:10:22.23#ibcon#about to read 5, iclass 27, count 0 2006.217.08:10:22.23#ibcon#read 5, iclass 27, count 0 2006.217.08:10:22.23#ibcon#about to read 6, iclass 27, count 0 2006.217.08:10:22.23#ibcon#read 6, iclass 27, count 0 2006.217.08:10:22.23#ibcon#end of sib2, iclass 27, count 0 2006.217.08:10:22.23#ibcon#*mode == 0, iclass 27, count 0 2006.217.08:10:22.23#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.217.08:10:22.23#ibcon#[28=FRQ=06,752.99\r\n] 2006.217.08:10:22.23#ibcon#*before write, iclass 27, count 0 2006.217.08:10:22.23#ibcon#enter sib2, iclass 27, count 0 2006.217.08:10:22.23#ibcon#flushed, iclass 27, count 0 2006.217.08:10:22.23#ibcon#about to write, iclass 27, count 0 2006.217.08:10:22.23#ibcon#wrote, iclass 27, count 0 2006.217.08:10:22.23#ibcon#about to read 3, iclass 27, count 0 2006.217.08:10:22.27#abcon#[5=S1D000X0/0*\r\n] 2006.217.08:10:22.27#ibcon#read 3, iclass 27, count 0 2006.217.08:10:22.27#ibcon#about to read 4, iclass 27, count 0 2006.217.08:10:22.27#ibcon#read 4, iclass 27, count 0 2006.217.08:10:22.27#ibcon#about to read 5, iclass 27, count 0 2006.217.08:10:22.27#ibcon#read 5, iclass 27, count 0 2006.217.08:10:22.27#ibcon#about to read 6, iclass 27, count 0 2006.217.08:10:22.27#ibcon#read 6, iclass 27, count 0 2006.217.08:10:22.27#ibcon#end of sib2, iclass 27, count 0 2006.217.08:10:22.27#ibcon#*after write, iclass 27, count 0 2006.217.08:10:22.27#ibcon#*before return 0, iclass 27, count 0 2006.217.08:10:22.27#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.217.08:10:22.27#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.217.08:10:22.27#ibcon#about to clear, iclass 27 cls_cnt 0 2006.217.08:10:22.27#ibcon#cleared, iclass 27 cls_cnt 0 2006.217.08:10:22.27$vc4f8/vb=6,4 2006.217.08:10:22.27#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.217.08:10:22.27#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.217.08:10:22.27#ibcon#ireg 11 cls_cnt 2 2006.217.08:10:22.27#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.217.08:10:22.33#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.217.08:10:22.33#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.217.08:10:22.33#ibcon#enter wrdev, iclass 30, count 2 2006.217.08:10:22.33#ibcon#first serial, iclass 30, count 2 2006.217.08:10:22.33#ibcon#enter sib2, iclass 30, count 2 2006.217.08:10:22.33#ibcon#flushed, iclass 30, count 2 2006.217.08:10:22.33#ibcon#about to write, iclass 30, count 2 2006.217.08:10:22.33#ibcon#wrote, iclass 30, count 2 2006.217.08:10:22.33#ibcon#about to read 3, iclass 30, count 2 2006.217.08:10:22.35#ibcon#read 3, iclass 30, count 2 2006.217.08:10:22.35#ibcon#about to read 4, iclass 30, count 2 2006.217.08:10:22.35#ibcon#read 4, iclass 30, count 2 2006.217.08:10:22.35#ibcon#about to read 5, iclass 30, count 2 2006.217.08:10:22.35#ibcon#read 5, iclass 30, count 2 2006.217.08:10:22.35#ibcon#about to read 6, iclass 30, count 2 2006.217.08:10:22.35#ibcon#read 6, iclass 30, count 2 2006.217.08:10:22.35#ibcon#end of sib2, iclass 30, count 2 2006.217.08:10:22.35#ibcon#*mode == 0, iclass 30, count 2 2006.217.08:10:22.35#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.217.08:10:22.35#ibcon#[27=AT06-04\r\n] 2006.217.08:10:22.35#ibcon#*before write, iclass 30, count 2 2006.217.08:10:22.35#ibcon#enter sib2, iclass 30, count 2 2006.217.08:10:22.35#ibcon#flushed, iclass 30, count 2 2006.217.08:10:22.35#ibcon#about to write, iclass 30, count 2 2006.217.08:10:22.35#ibcon#wrote, iclass 30, count 2 2006.217.08:10:22.35#ibcon#about to read 3, iclass 30, count 2 2006.217.08:10:22.38#ibcon#read 3, iclass 30, count 2 2006.217.08:10:22.38#ibcon#about to read 4, iclass 30, count 2 2006.217.08:10:22.38#ibcon#read 4, iclass 30, count 2 2006.217.08:10:22.38#ibcon#about to read 5, iclass 30, count 2 2006.217.08:10:22.38#ibcon#read 5, iclass 30, count 2 2006.217.08:10:22.38#ibcon#about to read 6, iclass 30, count 2 2006.217.08:10:22.38#ibcon#read 6, iclass 30, count 2 2006.217.08:10:22.38#ibcon#end of sib2, iclass 30, count 2 2006.217.08:10:22.38#ibcon#*after write, iclass 30, count 2 2006.217.08:10:22.38#ibcon#*before return 0, iclass 30, count 2 2006.217.08:10:22.38#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.217.08:10:22.38#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.217.08:10:22.38#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.217.08:10:22.38#ibcon#ireg 7 cls_cnt 0 2006.217.08:10:22.38#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.217.08:10:22.50#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.217.08:10:22.50#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.217.08:10:22.50#ibcon#enter wrdev, iclass 30, count 0 2006.217.08:10:22.50#ibcon#first serial, iclass 30, count 0 2006.217.08:10:22.50#ibcon#enter sib2, iclass 30, count 0 2006.217.08:10:22.50#ibcon#flushed, iclass 30, count 0 2006.217.08:10:22.50#ibcon#about to write, iclass 30, count 0 2006.217.08:10:22.50#ibcon#wrote, iclass 30, count 0 2006.217.08:10:22.50#ibcon#about to read 3, iclass 30, count 0 2006.217.08:10:22.52#ibcon#read 3, iclass 30, count 0 2006.217.08:10:22.52#ibcon#about to read 4, iclass 30, count 0 2006.217.08:10:22.52#ibcon#read 4, iclass 30, count 0 2006.217.08:10:22.52#ibcon#about to read 5, iclass 30, count 0 2006.217.08:10:22.52#ibcon#read 5, iclass 30, count 0 2006.217.08:10:22.52#ibcon#about to read 6, iclass 30, count 0 2006.217.08:10:22.52#ibcon#read 6, iclass 30, count 0 2006.217.08:10:22.52#ibcon#end of sib2, iclass 30, count 0 2006.217.08:10:22.52#ibcon#*mode == 0, iclass 30, count 0 2006.217.08:10:22.52#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.217.08:10:22.52#ibcon#[27=USB\r\n] 2006.217.08:10:22.52#ibcon#*before write, iclass 30, count 0 2006.217.08:10:22.52#ibcon#enter sib2, iclass 30, count 0 2006.217.08:10:22.52#ibcon#flushed, iclass 30, count 0 2006.217.08:10:22.52#ibcon#about to write, iclass 30, count 0 2006.217.08:10:22.52#ibcon#wrote, iclass 30, count 0 2006.217.08:10:22.52#ibcon#about to read 3, iclass 30, count 0 2006.217.08:10:22.55#ibcon#read 3, iclass 30, count 0 2006.217.08:10:22.55#ibcon#about to read 4, iclass 30, count 0 2006.217.08:10:22.55#ibcon#read 4, iclass 30, count 0 2006.217.08:10:22.55#ibcon#about to read 5, iclass 30, count 0 2006.217.08:10:22.55#ibcon#read 5, iclass 30, count 0 2006.217.08:10:22.55#ibcon#about to read 6, iclass 30, count 0 2006.217.08:10:22.55#ibcon#read 6, iclass 30, count 0 2006.217.08:10:22.55#ibcon#end of sib2, iclass 30, count 0 2006.217.08:10:22.55#ibcon#*after write, iclass 30, count 0 2006.217.08:10:22.55#ibcon#*before return 0, iclass 30, count 0 2006.217.08:10:22.55#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.217.08:10:22.55#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.217.08:10:22.55#ibcon#about to clear, iclass 30 cls_cnt 0 2006.217.08:10:22.55#ibcon#cleared, iclass 30 cls_cnt 0 2006.217.08:10:22.55$vc4f8/vabw=wide 2006.217.08:10:22.55#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.217.08:10:22.55#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.217.08:10:22.55#ibcon#ireg 8 cls_cnt 0 2006.217.08:10:22.55#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.217.08:10:22.55#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.217.08:10:22.55#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.217.08:10:22.55#ibcon#enter wrdev, iclass 32, count 0 2006.217.08:10:22.55#ibcon#first serial, iclass 32, count 0 2006.217.08:10:22.55#ibcon#enter sib2, iclass 32, count 0 2006.217.08:10:22.55#ibcon#flushed, iclass 32, count 0 2006.217.08:10:22.55#ibcon#about to write, iclass 32, count 0 2006.217.08:10:22.55#ibcon#wrote, iclass 32, count 0 2006.217.08:10:22.55#ibcon#about to read 3, iclass 32, count 0 2006.217.08:10:22.57#ibcon#read 3, iclass 32, count 0 2006.217.08:10:22.57#ibcon#about to read 4, iclass 32, count 0 2006.217.08:10:22.57#ibcon#read 4, iclass 32, count 0 2006.217.08:10:22.57#ibcon#about to read 5, iclass 32, count 0 2006.217.08:10:22.57#ibcon#read 5, iclass 32, count 0 2006.217.08:10:22.57#ibcon#about to read 6, iclass 32, count 0 2006.217.08:10:22.57#ibcon#read 6, iclass 32, count 0 2006.217.08:10:22.57#ibcon#end of sib2, iclass 32, count 0 2006.217.08:10:22.57#ibcon#*mode == 0, iclass 32, count 0 2006.217.08:10:22.57#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.217.08:10:22.57#ibcon#[25=BW32\r\n] 2006.217.08:10:22.57#ibcon#*before write, iclass 32, count 0 2006.217.08:10:22.57#ibcon#enter sib2, iclass 32, count 0 2006.217.08:10:22.57#ibcon#flushed, iclass 32, count 0 2006.217.08:10:22.57#ibcon#about to write, iclass 32, count 0 2006.217.08:10:22.57#ibcon#wrote, iclass 32, count 0 2006.217.08:10:22.57#ibcon#about to read 3, iclass 32, count 0 2006.217.08:10:22.60#ibcon#read 3, iclass 32, count 0 2006.217.08:10:22.60#ibcon#about to read 4, iclass 32, count 0 2006.217.08:10:22.60#ibcon#read 4, iclass 32, count 0 2006.217.08:10:22.60#ibcon#about to read 5, iclass 32, count 0 2006.217.08:10:22.60#ibcon#read 5, iclass 32, count 0 2006.217.08:10:22.60#ibcon#about to read 6, iclass 32, count 0 2006.217.08:10:22.60#ibcon#read 6, iclass 32, count 0 2006.217.08:10:22.60#ibcon#end of sib2, iclass 32, count 0 2006.217.08:10:22.60#ibcon#*after write, iclass 32, count 0 2006.217.08:10:22.60#ibcon#*before return 0, iclass 32, count 0 2006.217.08:10:22.60#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.217.08:10:22.60#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.217.08:10:22.60#ibcon#about to clear, iclass 32 cls_cnt 0 2006.217.08:10:22.60#ibcon#cleared, iclass 32 cls_cnt 0 2006.217.08:10:22.60$vc4f8/vbbw=wide 2006.217.08:10:22.60#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.217.08:10:22.60#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.217.08:10:22.60#ibcon#ireg 8 cls_cnt 0 2006.217.08:10:22.60#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.217.08:10:22.67#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.217.08:10:22.67#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.217.08:10:22.67#ibcon#enter wrdev, iclass 34, count 0 2006.217.08:10:22.67#ibcon#first serial, iclass 34, count 0 2006.217.08:10:22.67#ibcon#enter sib2, iclass 34, count 0 2006.217.08:10:22.67#ibcon#flushed, iclass 34, count 0 2006.217.08:10:22.67#ibcon#about to write, iclass 34, count 0 2006.217.08:10:22.67#ibcon#wrote, iclass 34, count 0 2006.217.08:10:22.67#ibcon#about to read 3, iclass 34, count 0 2006.217.08:10:22.69#ibcon#read 3, iclass 34, count 0 2006.217.08:10:22.69#ibcon#about to read 4, iclass 34, count 0 2006.217.08:10:22.69#ibcon#read 4, iclass 34, count 0 2006.217.08:10:22.69#ibcon#about to read 5, iclass 34, count 0 2006.217.08:10:22.69#ibcon#read 5, iclass 34, count 0 2006.217.08:10:22.69#ibcon#about to read 6, iclass 34, count 0 2006.217.08:10:22.69#ibcon#read 6, iclass 34, count 0 2006.217.08:10:22.69#ibcon#end of sib2, iclass 34, count 0 2006.217.08:10:22.69#ibcon#*mode == 0, iclass 34, count 0 2006.217.08:10:22.69#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.217.08:10:22.69#ibcon#[27=BW32\r\n] 2006.217.08:10:22.69#ibcon#*before write, iclass 34, count 0 2006.217.08:10:22.69#ibcon#enter sib2, iclass 34, count 0 2006.217.08:10:22.69#ibcon#flushed, iclass 34, count 0 2006.217.08:10:22.69#ibcon#about to write, iclass 34, count 0 2006.217.08:10:22.69#ibcon#wrote, iclass 34, count 0 2006.217.08:10:22.69#ibcon#about to read 3, iclass 34, count 0 2006.217.08:10:22.72#ibcon#read 3, iclass 34, count 0 2006.217.08:10:22.72#ibcon#about to read 4, iclass 34, count 0 2006.217.08:10:22.72#ibcon#read 4, iclass 34, count 0 2006.217.08:10:22.72#ibcon#about to read 5, iclass 34, count 0 2006.217.08:10:22.72#ibcon#read 5, iclass 34, count 0 2006.217.08:10:22.72#ibcon#about to read 6, iclass 34, count 0 2006.217.08:10:22.72#ibcon#read 6, iclass 34, count 0 2006.217.08:10:22.72#ibcon#end of sib2, iclass 34, count 0 2006.217.08:10:22.72#ibcon#*after write, iclass 34, count 0 2006.217.08:10:22.72#ibcon#*before return 0, iclass 34, count 0 2006.217.08:10:22.72#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.217.08:10:22.72#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.217.08:10:22.72#ibcon#about to clear, iclass 34 cls_cnt 0 2006.217.08:10:22.72#ibcon#cleared, iclass 34 cls_cnt 0 2006.217.08:10:22.72$4f8m12a/ifd4f 2006.217.08:10:22.72$ifd4f/lo= 2006.217.08:10:22.72$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.217.08:10:22.72$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.217.08:10:22.72$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.217.08:10:22.72$ifd4f/patch= 2006.217.08:10:22.72$ifd4f/patch=lo1,a1,a2,a3,a4 2006.217.08:10:22.72$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.217.08:10:22.72$ifd4f/patch=lo3,a5,a6,a7,a8 2006.217.08:10:22.72$4f8m12a/"form=m,16.000,1:2 2006.217.08:10:22.72$4f8m12a/"tpicd 2006.217.08:10:22.72$4f8m12a/echo=off 2006.217.08:10:22.72$4f8m12a/xlog=off 2006.217.08:10:22.72:!2006.217.08:10:50 2006.217.08:10:31.14#trakl#Source acquired 2006.217.08:10:32.14#flagr#flagr/antenna,acquired 2006.217.08:10:50.00:preob 2006.217.08:10:51.14/onsource/TRACKING 2006.217.08:10:51.14:!2006.217.08:11:00 2006.217.08:11:00.00:data_valid=on 2006.217.08:11:00.00:midob 2006.217.08:11:00.14/onsource/TRACKING 2006.217.08:11:00.14/wx/30.67,1008.6,64 2006.217.08:11:00.31/cable/+6.3879E-03 2006.217.08:11:01.40/va/01,05,usb,yes,42,44 2006.217.08:11:01.40/va/02,04,usb,yes,39,41 2006.217.08:11:01.40/va/03,04,usb,yes,37,37 2006.217.08:11:01.40/va/04,04,usb,yes,42,45 2006.217.08:11:01.40/va/05,07,usb,yes,46,48 2006.217.08:11:01.40/va/06,06,usb,yes,45,44 2006.217.08:11:01.40/va/07,06,usb,yes,45,44 2006.217.08:11:01.40/va/08,07,usb,yes,42,42 2006.217.08:11:01.63/valo/01,532.99,yes,locked 2006.217.08:11:01.63/valo/02,572.99,yes,locked 2006.217.08:11:01.63/valo/03,672.99,yes,locked 2006.217.08:11:01.63/valo/04,832.99,yes,locked 2006.217.08:11:01.63/valo/05,652.99,yes,locked 2006.217.08:11:01.63/valo/06,772.99,yes,locked 2006.217.08:11:01.63/valo/07,832.99,yes,locked 2006.217.08:11:01.63/valo/08,852.99,yes,locked 2006.217.08:11:02.72/vb/01,04,usb,yes,36,34 2006.217.08:11:02.72/vb/02,04,usb,yes,38,39 2006.217.08:11:02.72/vb/03,04,usb,yes,34,38 2006.217.08:11:02.72/vb/04,04,usb,yes,35,35 2006.217.08:11:02.72/vb/05,04,usb,yes,33,38 2006.217.08:11:02.72/vb/06,04,usb,yes,34,38 2006.217.08:11:02.72/vb/07,04,usb,yes,37,37 2006.217.08:11:02.72/vb/08,04,usb,yes,34,38 2006.217.08:11:02.95/vblo/01,632.99,yes,locked 2006.217.08:11:02.95/vblo/02,640.99,yes,locked 2006.217.08:11:02.95/vblo/03,656.99,yes,locked 2006.217.08:11:02.95/vblo/04,712.99,yes,locked 2006.217.08:11:02.95/vblo/05,744.99,yes,locked 2006.217.08:11:02.95/vblo/06,752.99,yes,locked 2006.217.08:11:02.95/vblo/07,734.99,yes,locked 2006.217.08:11:02.95/vblo/08,744.99,yes,locked 2006.217.08:11:03.10/vabw/8 2006.217.08:11:03.25/vbbw/8 2006.217.08:11:03.34/xfe/off,on,14.7 2006.217.08:11:03.72/ifatt/23,28,28,28 2006.217.08:11:04.07/fmout-gps/S +4.43E-07 2006.217.08:11:04.11:!2006.217.08:12:00 2006.217.08:12:00.00:data_valid=off 2006.217.08:12:00.00:postob 2006.217.08:12:00.19/cable/+6.3882E-03 2006.217.08:12:00.19/wx/30.65,1008.6,64 2006.217.08:12:01.07/fmout-gps/S +4.44E-07 2006.217.08:12:01.07:scan_name=217-0812,k06217,60 2006.217.08:12:01.07:source=0955+476,095819.67,472507.8,2000.0,ccw 2006.217.08:12:01.14#flagr#flagr/antenna,new-source 2006.217.08:12:02.14:checkk5 2006.217.08:12:02.52/chk_autoobs//k5ts1/ autoobs is running! 2006.217.08:12:02.88/chk_autoobs//k5ts2/ autoobs is running! 2006.217.08:12:03.26/chk_autoobs//k5ts3/ autoobs is running! 2006.217.08:12:03.63/chk_autoobs//k5ts4/ autoobs is running! 2006.217.08:12:04.00/chk_obsdata//k5ts1/T2170811??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.08:12:04.37/chk_obsdata//k5ts2/T2170811??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.08:12:04.74/chk_obsdata//k5ts3/T2170811??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.08:12:05.11/chk_obsdata//k5ts4/T2170811??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.08:12:05.81/k5log//k5ts1_log_newline 2006.217.08:12:06.50/k5log//k5ts2_log_newline 2006.217.08:12:07.18/k5log//k5ts3_log_newline 2006.217.08:12:07.87/k5log//k5ts4_log_newline 2006.217.08:12:07.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.217.08:12:07.90:4f8m12a=2 2006.217.08:12:07.90$4f8m12a/echo=on 2006.217.08:12:07.90$4f8m12a/pcalon 2006.217.08:12:07.90$pcalon/"no phase cal control is implemented here 2006.217.08:12:07.90$4f8m12a/"tpicd=stop 2006.217.08:12:07.90$4f8m12a/vc4f8 2006.217.08:12:07.90$vc4f8/valo=1,532.99 2006.217.08:12:07.90#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.217.08:12:07.90#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.217.08:12:07.90#ibcon#ireg 17 cls_cnt 0 2006.217.08:12:07.90#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.217.08:12:07.90#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.217.08:12:07.90#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.217.08:12:07.90#ibcon#enter wrdev, iclass 3, count 0 2006.217.08:12:07.90#ibcon#first serial, iclass 3, count 0 2006.217.08:12:07.90#ibcon#enter sib2, iclass 3, count 0 2006.217.08:12:07.90#ibcon#flushed, iclass 3, count 0 2006.217.08:12:07.90#ibcon#about to write, iclass 3, count 0 2006.217.08:12:07.90#ibcon#wrote, iclass 3, count 0 2006.217.08:12:07.90#ibcon#about to read 3, iclass 3, count 0 2006.217.08:12:07.92#ibcon#read 3, iclass 3, count 0 2006.217.08:12:07.92#ibcon#about to read 4, iclass 3, count 0 2006.217.08:12:07.92#ibcon#read 4, iclass 3, count 0 2006.217.08:12:07.92#ibcon#about to read 5, iclass 3, count 0 2006.217.08:12:07.92#ibcon#read 5, iclass 3, count 0 2006.217.08:12:07.92#ibcon#about to read 6, iclass 3, count 0 2006.217.08:12:07.92#ibcon#read 6, iclass 3, count 0 2006.217.08:12:07.92#ibcon#end of sib2, iclass 3, count 0 2006.217.08:12:07.92#ibcon#*mode == 0, iclass 3, count 0 2006.217.08:12:07.92#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.217.08:12:07.92#ibcon#[26=FRQ=01,532.99\r\n] 2006.217.08:12:07.92#ibcon#*before write, iclass 3, count 0 2006.217.08:12:07.92#ibcon#enter sib2, iclass 3, count 0 2006.217.08:12:07.92#ibcon#flushed, iclass 3, count 0 2006.217.08:12:07.92#ibcon#about to write, iclass 3, count 0 2006.217.08:12:07.92#ibcon#wrote, iclass 3, count 0 2006.217.08:12:07.92#ibcon#about to read 3, iclass 3, count 0 2006.217.08:12:07.97#ibcon#read 3, iclass 3, count 0 2006.217.08:12:07.97#ibcon#about to read 4, iclass 3, count 0 2006.217.08:12:07.97#ibcon#read 4, iclass 3, count 0 2006.217.08:12:07.97#ibcon#about to read 5, iclass 3, count 0 2006.217.08:12:07.97#ibcon#read 5, iclass 3, count 0 2006.217.08:12:07.97#ibcon#about to read 6, iclass 3, count 0 2006.217.08:12:07.97#ibcon#read 6, iclass 3, count 0 2006.217.08:12:07.97#ibcon#end of sib2, iclass 3, count 0 2006.217.08:12:07.97#ibcon#*after write, iclass 3, count 0 2006.217.08:12:07.97#ibcon#*before return 0, iclass 3, count 0 2006.217.08:12:07.97#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.217.08:12:07.97#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.217.08:12:07.97#ibcon#about to clear, iclass 3 cls_cnt 0 2006.217.08:12:07.97#ibcon#cleared, iclass 3 cls_cnt 0 2006.217.08:12:07.97$vc4f8/va=1,5 2006.217.08:12:07.97#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.217.08:12:07.97#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.217.08:12:07.97#ibcon#ireg 11 cls_cnt 2 2006.217.08:12:07.97#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.217.08:12:07.97#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.217.08:12:07.97#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.217.08:12:07.97#ibcon#enter wrdev, iclass 5, count 2 2006.217.08:12:07.97#ibcon#first serial, iclass 5, count 2 2006.217.08:12:07.97#ibcon#enter sib2, iclass 5, count 2 2006.217.08:12:07.97#ibcon#flushed, iclass 5, count 2 2006.217.08:12:07.97#ibcon#about to write, iclass 5, count 2 2006.217.08:12:07.97#ibcon#wrote, iclass 5, count 2 2006.217.08:12:07.97#ibcon#about to read 3, iclass 5, count 2 2006.217.08:12:07.99#ibcon#read 3, iclass 5, count 2 2006.217.08:12:07.99#ibcon#about to read 4, iclass 5, count 2 2006.217.08:12:07.99#ibcon#read 4, iclass 5, count 2 2006.217.08:12:07.99#ibcon#about to read 5, iclass 5, count 2 2006.217.08:12:07.99#ibcon#read 5, iclass 5, count 2 2006.217.08:12:07.99#ibcon#about to read 6, iclass 5, count 2 2006.217.08:12:07.99#ibcon#read 6, iclass 5, count 2 2006.217.08:12:07.99#ibcon#end of sib2, iclass 5, count 2 2006.217.08:12:07.99#ibcon#*mode == 0, iclass 5, count 2 2006.217.08:12:07.99#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.217.08:12:07.99#ibcon#[25=AT01-05\r\n] 2006.217.08:12:07.99#ibcon#*before write, iclass 5, count 2 2006.217.08:12:07.99#ibcon#enter sib2, iclass 5, count 2 2006.217.08:12:07.99#ibcon#flushed, iclass 5, count 2 2006.217.08:12:07.99#ibcon#about to write, iclass 5, count 2 2006.217.08:12:07.99#ibcon#wrote, iclass 5, count 2 2006.217.08:12:07.99#ibcon#about to read 3, iclass 5, count 2 2006.217.08:12:08.02#ibcon#read 3, iclass 5, count 2 2006.217.08:12:08.02#ibcon#about to read 4, iclass 5, count 2 2006.217.08:12:08.02#ibcon#read 4, iclass 5, count 2 2006.217.08:12:08.02#ibcon#about to read 5, iclass 5, count 2 2006.217.08:12:08.02#ibcon#read 5, iclass 5, count 2 2006.217.08:12:08.02#ibcon#about to read 6, iclass 5, count 2 2006.217.08:12:08.02#ibcon#read 6, iclass 5, count 2 2006.217.08:12:08.02#ibcon#end of sib2, iclass 5, count 2 2006.217.08:12:08.02#ibcon#*after write, iclass 5, count 2 2006.217.08:12:08.02#ibcon#*before return 0, iclass 5, count 2 2006.217.08:12:08.02#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.217.08:12:08.02#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.217.08:12:08.02#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.217.08:12:08.02#ibcon#ireg 7 cls_cnt 0 2006.217.08:12:08.02#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.217.08:12:08.14#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.217.08:12:08.14#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.217.08:12:08.14#ibcon#enter wrdev, iclass 5, count 0 2006.217.08:12:08.14#ibcon#first serial, iclass 5, count 0 2006.217.08:12:08.14#ibcon#enter sib2, iclass 5, count 0 2006.217.08:12:08.14#ibcon#flushed, iclass 5, count 0 2006.217.08:12:08.14#ibcon#about to write, iclass 5, count 0 2006.217.08:12:08.14#ibcon#wrote, iclass 5, count 0 2006.217.08:12:08.14#ibcon#about to read 3, iclass 5, count 0 2006.217.08:12:08.16#ibcon#read 3, iclass 5, count 0 2006.217.08:12:08.16#ibcon#about to read 4, iclass 5, count 0 2006.217.08:12:08.16#ibcon#read 4, iclass 5, count 0 2006.217.08:12:08.16#ibcon#about to read 5, iclass 5, count 0 2006.217.08:12:08.16#ibcon#read 5, iclass 5, count 0 2006.217.08:12:08.16#ibcon#about to read 6, iclass 5, count 0 2006.217.08:12:08.16#ibcon#read 6, iclass 5, count 0 2006.217.08:12:08.16#ibcon#end of sib2, iclass 5, count 0 2006.217.08:12:08.16#ibcon#*mode == 0, iclass 5, count 0 2006.217.08:12:08.16#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.217.08:12:08.16#ibcon#[25=USB\r\n] 2006.217.08:12:08.16#ibcon#*before write, iclass 5, count 0 2006.217.08:12:08.16#ibcon#enter sib2, iclass 5, count 0 2006.217.08:12:08.16#ibcon#flushed, iclass 5, count 0 2006.217.08:12:08.16#ibcon#about to write, iclass 5, count 0 2006.217.08:12:08.16#ibcon#wrote, iclass 5, count 0 2006.217.08:12:08.16#ibcon#about to read 3, iclass 5, count 0 2006.217.08:12:08.19#ibcon#read 3, iclass 5, count 0 2006.217.08:12:08.19#ibcon#about to read 4, iclass 5, count 0 2006.217.08:12:08.19#ibcon#read 4, iclass 5, count 0 2006.217.08:12:08.19#ibcon#about to read 5, iclass 5, count 0 2006.217.08:12:08.19#ibcon#read 5, iclass 5, count 0 2006.217.08:12:08.19#ibcon#about to read 6, iclass 5, count 0 2006.217.08:12:08.19#ibcon#read 6, iclass 5, count 0 2006.217.08:12:08.19#ibcon#end of sib2, iclass 5, count 0 2006.217.08:12:08.19#ibcon#*after write, iclass 5, count 0 2006.217.08:12:08.19#ibcon#*before return 0, iclass 5, count 0 2006.217.08:12:08.19#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.217.08:12:08.19#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.217.08:12:08.19#ibcon#about to clear, iclass 5 cls_cnt 0 2006.217.08:12:08.19#ibcon#cleared, iclass 5 cls_cnt 0 2006.217.08:12:08.19$vc4f8/valo=2,572.99 2006.217.08:12:08.19#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.217.08:12:08.19#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.217.08:12:08.19#ibcon#ireg 17 cls_cnt 0 2006.217.08:12:08.19#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.217.08:12:08.19#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.217.08:12:08.19#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.217.08:12:08.19#ibcon#enter wrdev, iclass 7, count 0 2006.217.08:12:08.19#ibcon#first serial, iclass 7, count 0 2006.217.08:12:08.19#ibcon#enter sib2, iclass 7, count 0 2006.217.08:12:08.19#ibcon#flushed, iclass 7, count 0 2006.217.08:12:08.19#ibcon#about to write, iclass 7, count 0 2006.217.08:12:08.19#ibcon#wrote, iclass 7, count 0 2006.217.08:12:08.19#ibcon#about to read 3, iclass 7, count 0 2006.217.08:12:08.21#ibcon#read 3, iclass 7, count 0 2006.217.08:12:08.21#ibcon#about to read 4, iclass 7, count 0 2006.217.08:12:08.21#ibcon#read 4, iclass 7, count 0 2006.217.08:12:08.21#ibcon#about to read 5, iclass 7, count 0 2006.217.08:12:08.21#ibcon#read 5, iclass 7, count 0 2006.217.08:12:08.21#ibcon#about to read 6, iclass 7, count 0 2006.217.08:12:08.21#ibcon#read 6, iclass 7, count 0 2006.217.08:12:08.21#ibcon#end of sib2, iclass 7, count 0 2006.217.08:12:08.21#ibcon#*mode == 0, iclass 7, count 0 2006.217.08:12:08.21#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.217.08:12:08.21#ibcon#[26=FRQ=02,572.99\r\n] 2006.217.08:12:08.21#ibcon#*before write, iclass 7, count 0 2006.217.08:12:08.21#ibcon#enter sib2, iclass 7, count 0 2006.217.08:12:08.21#ibcon#flushed, iclass 7, count 0 2006.217.08:12:08.21#ibcon#about to write, iclass 7, count 0 2006.217.08:12:08.21#ibcon#wrote, iclass 7, count 0 2006.217.08:12:08.21#ibcon#about to read 3, iclass 7, count 0 2006.217.08:12:08.26#ibcon#read 3, iclass 7, count 0 2006.217.08:12:08.26#ibcon#about to read 4, iclass 7, count 0 2006.217.08:12:08.26#ibcon#read 4, iclass 7, count 0 2006.217.08:12:08.26#ibcon#about to read 5, iclass 7, count 0 2006.217.08:12:08.26#ibcon#read 5, iclass 7, count 0 2006.217.08:12:08.26#ibcon#about to read 6, iclass 7, count 0 2006.217.08:12:08.26#ibcon#read 6, iclass 7, count 0 2006.217.08:12:08.26#ibcon#end of sib2, iclass 7, count 0 2006.217.08:12:08.26#ibcon#*after write, iclass 7, count 0 2006.217.08:12:08.26#ibcon#*before return 0, iclass 7, count 0 2006.217.08:12:08.26#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.217.08:12:08.26#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.217.08:12:08.26#ibcon#about to clear, iclass 7 cls_cnt 0 2006.217.08:12:08.26#ibcon#cleared, iclass 7 cls_cnt 0 2006.217.08:12:08.26$vc4f8/va=2,4 2006.217.08:12:08.26#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.217.08:12:08.26#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.217.08:12:08.26#ibcon#ireg 11 cls_cnt 2 2006.217.08:12:08.26#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.217.08:12:08.31#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.217.08:12:08.31#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.217.08:12:08.31#ibcon#enter wrdev, iclass 11, count 2 2006.217.08:12:08.31#ibcon#first serial, iclass 11, count 2 2006.217.08:12:08.31#ibcon#enter sib2, iclass 11, count 2 2006.217.08:12:08.31#ibcon#flushed, iclass 11, count 2 2006.217.08:12:08.31#ibcon#about to write, iclass 11, count 2 2006.217.08:12:08.31#ibcon#wrote, iclass 11, count 2 2006.217.08:12:08.31#ibcon#about to read 3, iclass 11, count 2 2006.217.08:12:08.33#ibcon#read 3, iclass 11, count 2 2006.217.08:12:08.33#ibcon#about to read 4, iclass 11, count 2 2006.217.08:12:08.33#ibcon#read 4, iclass 11, count 2 2006.217.08:12:08.33#ibcon#about to read 5, iclass 11, count 2 2006.217.08:12:08.33#ibcon#read 5, iclass 11, count 2 2006.217.08:12:08.33#ibcon#about to read 6, iclass 11, count 2 2006.217.08:12:08.33#ibcon#read 6, iclass 11, count 2 2006.217.08:12:08.33#ibcon#end of sib2, iclass 11, count 2 2006.217.08:12:08.33#ibcon#*mode == 0, iclass 11, count 2 2006.217.08:12:08.33#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.217.08:12:08.33#ibcon#[25=AT02-04\r\n] 2006.217.08:12:08.33#ibcon#*before write, iclass 11, count 2 2006.217.08:12:08.33#ibcon#enter sib2, iclass 11, count 2 2006.217.08:12:08.33#ibcon#flushed, iclass 11, count 2 2006.217.08:12:08.33#ibcon#about to write, iclass 11, count 2 2006.217.08:12:08.33#ibcon#wrote, iclass 11, count 2 2006.217.08:12:08.33#ibcon#about to read 3, iclass 11, count 2 2006.217.08:12:08.36#ibcon#read 3, iclass 11, count 2 2006.217.08:12:08.36#ibcon#about to read 4, iclass 11, count 2 2006.217.08:12:08.36#ibcon#read 4, iclass 11, count 2 2006.217.08:12:08.36#ibcon#about to read 5, iclass 11, count 2 2006.217.08:12:08.36#ibcon#read 5, iclass 11, count 2 2006.217.08:12:08.36#ibcon#about to read 6, iclass 11, count 2 2006.217.08:12:08.36#ibcon#read 6, iclass 11, count 2 2006.217.08:12:08.36#ibcon#end of sib2, iclass 11, count 2 2006.217.08:12:08.36#ibcon#*after write, iclass 11, count 2 2006.217.08:12:08.36#ibcon#*before return 0, iclass 11, count 2 2006.217.08:12:08.36#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.217.08:12:08.36#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.217.08:12:08.36#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.217.08:12:08.36#ibcon#ireg 7 cls_cnt 0 2006.217.08:12:08.36#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.217.08:12:08.48#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.217.08:12:08.48#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.217.08:12:08.48#ibcon#enter wrdev, iclass 11, count 0 2006.217.08:12:08.48#ibcon#first serial, iclass 11, count 0 2006.217.08:12:08.48#ibcon#enter sib2, iclass 11, count 0 2006.217.08:12:08.48#ibcon#flushed, iclass 11, count 0 2006.217.08:12:08.48#ibcon#about to write, iclass 11, count 0 2006.217.08:12:08.48#ibcon#wrote, iclass 11, count 0 2006.217.08:12:08.48#ibcon#about to read 3, iclass 11, count 0 2006.217.08:12:08.50#ibcon#read 3, iclass 11, count 0 2006.217.08:12:08.50#ibcon#about to read 4, iclass 11, count 0 2006.217.08:12:08.50#ibcon#read 4, iclass 11, count 0 2006.217.08:12:08.50#ibcon#about to read 5, iclass 11, count 0 2006.217.08:12:08.50#ibcon#read 5, iclass 11, count 0 2006.217.08:12:08.50#ibcon#about to read 6, iclass 11, count 0 2006.217.08:12:08.50#ibcon#read 6, iclass 11, count 0 2006.217.08:12:08.50#ibcon#end of sib2, iclass 11, count 0 2006.217.08:12:08.50#ibcon#*mode == 0, iclass 11, count 0 2006.217.08:12:08.50#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.217.08:12:08.50#ibcon#[25=USB\r\n] 2006.217.08:12:08.50#ibcon#*before write, iclass 11, count 0 2006.217.08:12:08.50#ibcon#enter sib2, iclass 11, count 0 2006.217.08:12:08.50#ibcon#flushed, iclass 11, count 0 2006.217.08:12:08.50#ibcon#about to write, iclass 11, count 0 2006.217.08:12:08.50#ibcon#wrote, iclass 11, count 0 2006.217.08:12:08.50#ibcon#about to read 3, iclass 11, count 0 2006.217.08:12:08.53#ibcon#read 3, iclass 11, count 0 2006.217.08:12:08.53#ibcon#about to read 4, iclass 11, count 0 2006.217.08:12:08.53#ibcon#read 4, iclass 11, count 0 2006.217.08:12:08.53#ibcon#about to read 5, iclass 11, count 0 2006.217.08:12:08.53#ibcon#read 5, iclass 11, count 0 2006.217.08:12:08.53#ibcon#about to read 6, iclass 11, count 0 2006.217.08:12:08.53#ibcon#read 6, iclass 11, count 0 2006.217.08:12:08.53#ibcon#end of sib2, iclass 11, count 0 2006.217.08:12:08.53#ibcon#*after write, iclass 11, count 0 2006.217.08:12:08.53#ibcon#*before return 0, iclass 11, count 0 2006.217.08:12:08.53#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.217.08:12:08.53#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.217.08:12:08.53#ibcon#about to clear, iclass 11 cls_cnt 0 2006.217.08:12:08.53#ibcon#cleared, iclass 11 cls_cnt 0 2006.217.08:12:08.53$vc4f8/valo=3,672.99 2006.217.08:12:08.53#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.217.08:12:08.53#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.217.08:12:08.53#ibcon#ireg 17 cls_cnt 0 2006.217.08:12:08.53#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.217.08:12:08.53#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.217.08:12:08.53#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.217.08:12:08.53#ibcon#enter wrdev, iclass 13, count 0 2006.217.08:12:08.53#ibcon#first serial, iclass 13, count 0 2006.217.08:12:08.53#ibcon#enter sib2, iclass 13, count 0 2006.217.08:12:08.53#ibcon#flushed, iclass 13, count 0 2006.217.08:12:08.53#ibcon#about to write, iclass 13, count 0 2006.217.08:12:08.53#ibcon#wrote, iclass 13, count 0 2006.217.08:12:08.53#ibcon#about to read 3, iclass 13, count 0 2006.217.08:12:08.55#ibcon#read 3, iclass 13, count 0 2006.217.08:12:08.55#ibcon#about to read 4, iclass 13, count 0 2006.217.08:12:08.55#ibcon#read 4, iclass 13, count 0 2006.217.08:12:08.55#ibcon#about to read 5, iclass 13, count 0 2006.217.08:12:08.55#ibcon#read 5, iclass 13, count 0 2006.217.08:12:08.55#ibcon#about to read 6, iclass 13, count 0 2006.217.08:12:08.55#ibcon#read 6, iclass 13, count 0 2006.217.08:12:08.55#ibcon#end of sib2, iclass 13, count 0 2006.217.08:12:08.55#ibcon#*mode == 0, iclass 13, count 0 2006.217.08:12:08.55#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.217.08:12:08.55#ibcon#[26=FRQ=03,672.99\r\n] 2006.217.08:12:08.55#ibcon#*before write, iclass 13, count 0 2006.217.08:12:08.55#ibcon#enter sib2, iclass 13, count 0 2006.217.08:12:08.55#ibcon#flushed, iclass 13, count 0 2006.217.08:12:08.55#ibcon#about to write, iclass 13, count 0 2006.217.08:12:08.55#ibcon#wrote, iclass 13, count 0 2006.217.08:12:08.55#ibcon#about to read 3, iclass 13, count 0 2006.217.08:12:08.60#ibcon#read 3, iclass 13, count 0 2006.217.08:12:08.60#ibcon#about to read 4, iclass 13, count 0 2006.217.08:12:08.60#ibcon#read 4, iclass 13, count 0 2006.217.08:12:08.60#ibcon#about to read 5, iclass 13, count 0 2006.217.08:12:08.60#ibcon#read 5, iclass 13, count 0 2006.217.08:12:08.60#ibcon#about to read 6, iclass 13, count 0 2006.217.08:12:08.60#ibcon#read 6, iclass 13, count 0 2006.217.08:12:08.60#ibcon#end of sib2, iclass 13, count 0 2006.217.08:12:08.60#ibcon#*after write, iclass 13, count 0 2006.217.08:12:08.60#ibcon#*before return 0, iclass 13, count 0 2006.217.08:12:08.60#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.217.08:12:08.60#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.217.08:12:08.60#ibcon#about to clear, iclass 13 cls_cnt 0 2006.217.08:12:08.60#ibcon#cleared, iclass 13 cls_cnt 0 2006.217.08:12:08.60$vc4f8/va=3,4 2006.217.08:12:08.60#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.217.08:12:08.60#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.217.08:12:08.60#ibcon#ireg 11 cls_cnt 2 2006.217.08:12:08.60#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.217.08:12:08.65#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.217.08:12:08.65#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.217.08:12:08.65#ibcon#enter wrdev, iclass 15, count 2 2006.217.08:12:08.65#ibcon#first serial, iclass 15, count 2 2006.217.08:12:08.65#ibcon#enter sib2, iclass 15, count 2 2006.217.08:12:08.65#ibcon#flushed, iclass 15, count 2 2006.217.08:12:08.65#ibcon#about to write, iclass 15, count 2 2006.217.08:12:08.65#ibcon#wrote, iclass 15, count 2 2006.217.08:12:08.65#ibcon#about to read 3, iclass 15, count 2 2006.217.08:12:08.67#ibcon#read 3, iclass 15, count 2 2006.217.08:12:08.67#ibcon#about to read 4, iclass 15, count 2 2006.217.08:12:08.67#ibcon#read 4, iclass 15, count 2 2006.217.08:12:08.67#ibcon#about to read 5, iclass 15, count 2 2006.217.08:12:08.67#ibcon#read 5, iclass 15, count 2 2006.217.08:12:08.67#ibcon#about to read 6, iclass 15, count 2 2006.217.08:12:08.67#ibcon#read 6, iclass 15, count 2 2006.217.08:12:08.67#ibcon#end of sib2, iclass 15, count 2 2006.217.08:12:08.67#ibcon#*mode == 0, iclass 15, count 2 2006.217.08:12:08.67#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.217.08:12:08.67#ibcon#[25=AT03-04\r\n] 2006.217.08:12:08.67#ibcon#*before write, iclass 15, count 2 2006.217.08:12:08.67#ibcon#enter sib2, iclass 15, count 2 2006.217.08:12:08.67#ibcon#flushed, iclass 15, count 2 2006.217.08:12:08.67#ibcon#about to write, iclass 15, count 2 2006.217.08:12:08.67#ibcon#wrote, iclass 15, count 2 2006.217.08:12:08.67#ibcon#about to read 3, iclass 15, count 2 2006.217.08:12:08.70#ibcon#read 3, iclass 15, count 2 2006.217.08:12:08.70#ibcon#about to read 4, iclass 15, count 2 2006.217.08:12:08.70#ibcon#read 4, iclass 15, count 2 2006.217.08:12:08.70#ibcon#about to read 5, iclass 15, count 2 2006.217.08:12:08.70#ibcon#read 5, iclass 15, count 2 2006.217.08:12:08.70#ibcon#about to read 6, iclass 15, count 2 2006.217.08:12:08.70#ibcon#read 6, iclass 15, count 2 2006.217.08:12:08.70#ibcon#end of sib2, iclass 15, count 2 2006.217.08:12:08.70#ibcon#*after write, iclass 15, count 2 2006.217.08:12:08.70#ibcon#*before return 0, iclass 15, count 2 2006.217.08:12:08.70#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.217.08:12:08.70#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.217.08:12:08.70#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.217.08:12:08.70#ibcon#ireg 7 cls_cnt 0 2006.217.08:12:08.70#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.217.08:12:08.82#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.217.08:12:08.82#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.217.08:12:08.82#ibcon#enter wrdev, iclass 15, count 0 2006.217.08:12:08.82#ibcon#first serial, iclass 15, count 0 2006.217.08:12:08.82#ibcon#enter sib2, iclass 15, count 0 2006.217.08:12:08.82#ibcon#flushed, iclass 15, count 0 2006.217.08:12:08.82#ibcon#about to write, iclass 15, count 0 2006.217.08:12:08.82#ibcon#wrote, iclass 15, count 0 2006.217.08:12:08.82#ibcon#about to read 3, iclass 15, count 0 2006.217.08:12:08.84#ibcon#read 3, iclass 15, count 0 2006.217.08:12:08.84#ibcon#about to read 4, iclass 15, count 0 2006.217.08:12:08.84#ibcon#read 4, iclass 15, count 0 2006.217.08:12:08.84#ibcon#about to read 5, iclass 15, count 0 2006.217.08:12:08.84#ibcon#read 5, iclass 15, count 0 2006.217.08:12:08.84#ibcon#about to read 6, iclass 15, count 0 2006.217.08:12:08.84#ibcon#read 6, iclass 15, count 0 2006.217.08:12:08.84#ibcon#end of sib2, iclass 15, count 0 2006.217.08:12:08.84#ibcon#*mode == 0, iclass 15, count 0 2006.217.08:12:08.84#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.217.08:12:08.84#ibcon#[25=USB\r\n] 2006.217.08:12:08.84#ibcon#*before write, iclass 15, count 0 2006.217.08:12:08.84#ibcon#enter sib2, iclass 15, count 0 2006.217.08:12:08.84#ibcon#flushed, iclass 15, count 0 2006.217.08:12:08.84#ibcon#about to write, iclass 15, count 0 2006.217.08:12:08.84#ibcon#wrote, iclass 15, count 0 2006.217.08:12:08.84#ibcon#about to read 3, iclass 15, count 0 2006.217.08:12:08.87#ibcon#read 3, iclass 15, count 0 2006.217.08:12:08.87#ibcon#about to read 4, iclass 15, count 0 2006.217.08:12:08.87#ibcon#read 4, iclass 15, count 0 2006.217.08:12:08.87#ibcon#about to read 5, iclass 15, count 0 2006.217.08:12:08.87#ibcon#read 5, iclass 15, count 0 2006.217.08:12:08.87#ibcon#about to read 6, iclass 15, count 0 2006.217.08:12:08.87#ibcon#read 6, iclass 15, count 0 2006.217.08:12:08.87#ibcon#end of sib2, iclass 15, count 0 2006.217.08:12:08.87#ibcon#*after write, iclass 15, count 0 2006.217.08:12:08.87#ibcon#*before return 0, iclass 15, count 0 2006.217.08:12:08.87#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.217.08:12:08.87#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.217.08:12:08.87#ibcon#about to clear, iclass 15 cls_cnt 0 2006.217.08:12:08.87#ibcon#cleared, iclass 15 cls_cnt 0 2006.217.08:12:08.87$vc4f8/valo=4,832.99 2006.217.08:12:08.87#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.217.08:12:08.87#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.217.08:12:08.87#ibcon#ireg 17 cls_cnt 0 2006.217.08:12:08.87#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.217.08:12:08.87#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.217.08:12:08.87#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.217.08:12:08.87#ibcon#enter wrdev, iclass 17, count 0 2006.217.08:12:08.87#ibcon#first serial, iclass 17, count 0 2006.217.08:12:08.87#ibcon#enter sib2, iclass 17, count 0 2006.217.08:12:08.87#ibcon#flushed, iclass 17, count 0 2006.217.08:12:08.87#ibcon#about to write, iclass 17, count 0 2006.217.08:12:08.87#ibcon#wrote, iclass 17, count 0 2006.217.08:12:08.87#ibcon#about to read 3, iclass 17, count 0 2006.217.08:12:08.89#ibcon#read 3, iclass 17, count 0 2006.217.08:12:08.89#ibcon#about to read 4, iclass 17, count 0 2006.217.08:12:08.89#ibcon#read 4, iclass 17, count 0 2006.217.08:12:08.89#ibcon#about to read 5, iclass 17, count 0 2006.217.08:12:08.89#ibcon#read 5, iclass 17, count 0 2006.217.08:12:08.89#ibcon#about to read 6, iclass 17, count 0 2006.217.08:12:08.89#ibcon#read 6, iclass 17, count 0 2006.217.08:12:08.89#ibcon#end of sib2, iclass 17, count 0 2006.217.08:12:08.89#ibcon#*mode == 0, iclass 17, count 0 2006.217.08:12:08.89#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.217.08:12:08.89#ibcon#[26=FRQ=04,832.99\r\n] 2006.217.08:12:08.89#ibcon#*before write, iclass 17, count 0 2006.217.08:12:08.89#ibcon#enter sib2, iclass 17, count 0 2006.217.08:12:08.89#ibcon#flushed, iclass 17, count 0 2006.217.08:12:08.89#ibcon#about to write, iclass 17, count 0 2006.217.08:12:08.89#ibcon#wrote, iclass 17, count 0 2006.217.08:12:08.89#ibcon#about to read 3, iclass 17, count 0 2006.217.08:12:08.94#ibcon#read 3, iclass 17, count 0 2006.217.08:12:08.94#ibcon#about to read 4, iclass 17, count 0 2006.217.08:12:08.94#ibcon#read 4, iclass 17, count 0 2006.217.08:12:08.94#ibcon#about to read 5, iclass 17, count 0 2006.217.08:12:08.94#ibcon#read 5, iclass 17, count 0 2006.217.08:12:08.94#ibcon#about to read 6, iclass 17, count 0 2006.217.08:12:08.94#ibcon#read 6, iclass 17, count 0 2006.217.08:12:08.94#ibcon#end of sib2, iclass 17, count 0 2006.217.08:12:08.94#ibcon#*after write, iclass 17, count 0 2006.217.08:12:08.94#ibcon#*before return 0, iclass 17, count 0 2006.217.08:12:08.94#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.217.08:12:08.94#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.217.08:12:08.94#ibcon#about to clear, iclass 17 cls_cnt 0 2006.217.08:12:08.94#ibcon#cleared, iclass 17 cls_cnt 0 2006.217.08:12:08.94$vc4f8/va=4,4 2006.217.08:12:08.94#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.217.08:12:08.94#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.217.08:12:08.94#ibcon#ireg 11 cls_cnt 2 2006.217.08:12:08.94#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.217.08:12:08.99#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.217.08:12:08.99#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.217.08:12:08.99#ibcon#enter wrdev, iclass 19, count 2 2006.217.08:12:08.99#ibcon#first serial, iclass 19, count 2 2006.217.08:12:08.99#ibcon#enter sib2, iclass 19, count 2 2006.217.08:12:08.99#ibcon#flushed, iclass 19, count 2 2006.217.08:12:08.99#ibcon#about to write, iclass 19, count 2 2006.217.08:12:08.99#ibcon#wrote, iclass 19, count 2 2006.217.08:12:08.99#ibcon#about to read 3, iclass 19, count 2 2006.217.08:12:09.01#ibcon#read 3, iclass 19, count 2 2006.217.08:12:09.01#ibcon#about to read 4, iclass 19, count 2 2006.217.08:12:09.01#ibcon#read 4, iclass 19, count 2 2006.217.08:12:09.01#ibcon#about to read 5, iclass 19, count 2 2006.217.08:12:09.01#ibcon#read 5, iclass 19, count 2 2006.217.08:12:09.01#ibcon#about to read 6, iclass 19, count 2 2006.217.08:12:09.01#ibcon#read 6, iclass 19, count 2 2006.217.08:12:09.01#ibcon#end of sib2, iclass 19, count 2 2006.217.08:12:09.01#ibcon#*mode == 0, iclass 19, count 2 2006.217.08:12:09.01#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.217.08:12:09.01#ibcon#[25=AT04-04\r\n] 2006.217.08:12:09.01#ibcon#*before write, iclass 19, count 2 2006.217.08:12:09.01#ibcon#enter sib2, iclass 19, count 2 2006.217.08:12:09.01#ibcon#flushed, iclass 19, count 2 2006.217.08:12:09.01#ibcon#about to write, iclass 19, count 2 2006.217.08:12:09.01#ibcon#wrote, iclass 19, count 2 2006.217.08:12:09.01#ibcon#about to read 3, iclass 19, count 2 2006.217.08:12:09.04#ibcon#read 3, iclass 19, count 2 2006.217.08:12:09.04#ibcon#about to read 4, iclass 19, count 2 2006.217.08:12:09.04#ibcon#read 4, iclass 19, count 2 2006.217.08:12:09.04#ibcon#about to read 5, iclass 19, count 2 2006.217.08:12:09.04#ibcon#read 5, iclass 19, count 2 2006.217.08:12:09.04#ibcon#about to read 6, iclass 19, count 2 2006.217.08:12:09.04#ibcon#read 6, iclass 19, count 2 2006.217.08:12:09.04#ibcon#end of sib2, iclass 19, count 2 2006.217.08:12:09.04#ibcon#*after write, iclass 19, count 2 2006.217.08:12:09.04#ibcon#*before return 0, iclass 19, count 2 2006.217.08:12:09.04#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.217.08:12:09.04#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.217.08:12:09.04#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.217.08:12:09.04#ibcon#ireg 7 cls_cnt 0 2006.217.08:12:09.04#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.217.08:12:09.16#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.217.08:12:09.16#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.217.08:12:09.16#ibcon#enter wrdev, iclass 19, count 0 2006.217.08:12:09.16#ibcon#first serial, iclass 19, count 0 2006.217.08:12:09.16#ibcon#enter sib2, iclass 19, count 0 2006.217.08:12:09.16#ibcon#flushed, iclass 19, count 0 2006.217.08:12:09.16#ibcon#about to write, iclass 19, count 0 2006.217.08:12:09.16#ibcon#wrote, iclass 19, count 0 2006.217.08:12:09.16#ibcon#about to read 3, iclass 19, count 0 2006.217.08:12:09.18#ibcon#read 3, iclass 19, count 0 2006.217.08:12:09.18#ibcon#about to read 4, iclass 19, count 0 2006.217.08:12:09.18#ibcon#read 4, iclass 19, count 0 2006.217.08:12:09.18#ibcon#about to read 5, iclass 19, count 0 2006.217.08:12:09.18#ibcon#read 5, iclass 19, count 0 2006.217.08:12:09.18#ibcon#about to read 6, iclass 19, count 0 2006.217.08:12:09.18#ibcon#read 6, iclass 19, count 0 2006.217.08:12:09.18#ibcon#end of sib2, iclass 19, count 0 2006.217.08:12:09.18#ibcon#*mode == 0, iclass 19, count 0 2006.217.08:12:09.18#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.217.08:12:09.18#ibcon#[25=USB\r\n] 2006.217.08:12:09.18#ibcon#*before write, iclass 19, count 0 2006.217.08:12:09.18#ibcon#enter sib2, iclass 19, count 0 2006.217.08:12:09.18#ibcon#flushed, iclass 19, count 0 2006.217.08:12:09.18#ibcon#about to write, iclass 19, count 0 2006.217.08:12:09.18#ibcon#wrote, iclass 19, count 0 2006.217.08:12:09.18#ibcon#about to read 3, iclass 19, count 0 2006.217.08:12:09.21#ibcon#read 3, iclass 19, count 0 2006.217.08:12:09.21#ibcon#about to read 4, iclass 19, count 0 2006.217.08:12:09.21#ibcon#read 4, iclass 19, count 0 2006.217.08:12:09.21#ibcon#about to read 5, iclass 19, count 0 2006.217.08:12:09.21#ibcon#read 5, iclass 19, count 0 2006.217.08:12:09.21#ibcon#about to read 6, iclass 19, count 0 2006.217.08:12:09.21#ibcon#read 6, iclass 19, count 0 2006.217.08:12:09.21#ibcon#end of sib2, iclass 19, count 0 2006.217.08:12:09.21#ibcon#*after write, iclass 19, count 0 2006.217.08:12:09.21#ibcon#*before return 0, iclass 19, count 0 2006.217.08:12:09.21#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.217.08:12:09.21#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.217.08:12:09.21#ibcon#about to clear, iclass 19 cls_cnt 0 2006.217.08:12:09.21#ibcon#cleared, iclass 19 cls_cnt 0 2006.217.08:12:09.21$vc4f8/valo=5,652.99 2006.217.08:12:09.21#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.217.08:12:09.21#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.217.08:12:09.21#ibcon#ireg 17 cls_cnt 0 2006.217.08:12:09.21#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.217.08:12:09.21#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.217.08:12:09.21#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.217.08:12:09.21#ibcon#enter wrdev, iclass 21, count 0 2006.217.08:12:09.21#ibcon#first serial, iclass 21, count 0 2006.217.08:12:09.21#ibcon#enter sib2, iclass 21, count 0 2006.217.08:12:09.21#ibcon#flushed, iclass 21, count 0 2006.217.08:12:09.21#ibcon#about to write, iclass 21, count 0 2006.217.08:12:09.21#ibcon#wrote, iclass 21, count 0 2006.217.08:12:09.21#ibcon#about to read 3, iclass 21, count 0 2006.217.08:12:09.23#ibcon#read 3, iclass 21, count 0 2006.217.08:12:09.23#ibcon#about to read 4, iclass 21, count 0 2006.217.08:12:09.23#ibcon#read 4, iclass 21, count 0 2006.217.08:12:09.23#ibcon#about to read 5, iclass 21, count 0 2006.217.08:12:09.23#ibcon#read 5, iclass 21, count 0 2006.217.08:12:09.23#ibcon#about to read 6, iclass 21, count 0 2006.217.08:12:09.23#ibcon#read 6, iclass 21, count 0 2006.217.08:12:09.23#ibcon#end of sib2, iclass 21, count 0 2006.217.08:12:09.23#ibcon#*mode == 0, iclass 21, count 0 2006.217.08:12:09.23#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.217.08:12:09.23#ibcon#[26=FRQ=05,652.99\r\n] 2006.217.08:12:09.23#ibcon#*before write, iclass 21, count 0 2006.217.08:12:09.23#ibcon#enter sib2, iclass 21, count 0 2006.217.08:12:09.23#ibcon#flushed, iclass 21, count 0 2006.217.08:12:09.23#ibcon#about to write, iclass 21, count 0 2006.217.08:12:09.23#ibcon#wrote, iclass 21, count 0 2006.217.08:12:09.23#ibcon#about to read 3, iclass 21, count 0 2006.217.08:12:09.27#ibcon#read 3, iclass 21, count 0 2006.217.08:12:09.27#ibcon#about to read 4, iclass 21, count 0 2006.217.08:12:09.27#ibcon#read 4, iclass 21, count 0 2006.217.08:12:09.27#ibcon#about to read 5, iclass 21, count 0 2006.217.08:12:09.27#ibcon#read 5, iclass 21, count 0 2006.217.08:12:09.27#ibcon#about to read 6, iclass 21, count 0 2006.217.08:12:09.27#ibcon#read 6, iclass 21, count 0 2006.217.08:12:09.27#ibcon#end of sib2, iclass 21, count 0 2006.217.08:12:09.27#ibcon#*after write, iclass 21, count 0 2006.217.08:12:09.27#ibcon#*before return 0, iclass 21, count 0 2006.217.08:12:09.27#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.217.08:12:09.27#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.217.08:12:09.27#ibcon#about to clear, iclass 21 cls_cnt 0 2006.217.08:12:09.27#ibcon#cleared, iclass 21 cls_cnt 0 2006.217.08:12:09.27$vc4f8/va=5,7 2006.217.08:12:09.27#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.217.08:12:09.27#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.217.08:12:09.27#ibcon#ireg 11 cls_cnt 2 2006.217.08:12:09.27#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.217.08:12:09.33#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.217.08:12:09.33#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.217.08:12:09.33#ibcon#enter wrdev, iclass 23, count 2 2006.217.08:12:09.33#ibcon#first serial, iclass 23, count 2 2006.217.08:12:09.33#ibcon#enter sib2, iclass 23, count 2 2006.217.08:12:09.33#ibcon#flushed, iclass 23, count 2 2006.217.08:12:09.33#ibcon#about to write, iclass 23, count 2 2006.217.08:12:09.33#ibcon#wrote, iclass 23, count 2 2006.217.08:12:09.33#ibcon#about to read 3, iclass 23, count 2 2006.217.08:12:09.35#ibcon#read 3, iclass 23, count 2 2006.217.08:12:09.35#ibcon#about to read 4, iclass 23, count 2 2006.217.08:12:09.35#ibcon#read 4, iclass 23, count 2 2006.217.08:12:09.35#ibcon#about to read 5, iclass 23, count 2 2006.217.08:12:09.35#ibcon#read 5, iclass 23, count 2 2006.217.08:12:09.35#ibcon#about to read 6, iclass 23, count 2 2006.217.08:12:09.35#ibcon#read 6, iclass 23, count 2 2006.217.08:12:09.35#ibcon#end of sib2, iclass 23, count 2 2006.217.08:12:09.35#ibcon#*mode == 0, iclass 23, count 2 2006.217.08:12:09.35#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.217.08:12:09.35#ibcon#[25=AT05-07\r\n] 2006.217.08:12:09.35#ibcon#*before write, iclass 23, count 2 2006.217.08:12:09.35#ibcon#enter sib2, iclass 23, count 2 2006.217.08:12:09.35#ibcon#flushed, iclass 23, count 2 2006.217.08:12:09.35#ibcon#about to write, iclass 23, count 2 2006.217.08:12:09.35#ibcon#wrote, iclass 23, count 2 2006.217.08:12:09.35#ibcon#about to read 3, iclass 23, count 2 2006.217.08:12:09.38#ibcon#read 3, iclass 23, count 2 2006.217.08:12:09.38#ibcon#about to read 4, iclass 23, count 2 2006.217.08:12:09.38#ibcon#read 4, iclass 23, count 2 2006.217.08:12:09.38#ibcon#about to read 5, iclass 23, count 2 2006.217.08:12:09.38#ibcon#read 5, iclass 23, count 2 2006.217.08:12:09.38#ibcon#about to read 6, iclass 23, count 2 2006.217.08:12:09.38#ibcon#read 6, iclass 23, count 2 2006.217.08:12:09.38#ibcon#end of sib2, iclass 23, count 2 2006.217.08:12:09.38#ibcon#*after write, iclass 23, count 2 2006.217.08:12:09.38#ibcon#*before return 0, iclass 23, count 2 2006.217.08:12:09.38#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.217.08:12:09.38#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.217.08:12:09.38#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.217.08:12:09.38#ibcon#ireg 7 cls_cnt 0 2006.217.08:12:09.38#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.217.08:12:09.50#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.217.08:12:09.50#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.217.08:12:09.50#ibcon#enter wrdev, iclass 23, count 0 2006.217.08:12:09.50#ibcon#first serial, iclass 23, count 0 2006.217.08:12:09.50#ibcon#enter sib2, iclass 23, count 0 2006.217.08:12:09.50#ibcon#flushed, iclass 23, count 0 2006.217.08:12:09.50#ibcon#about to write, iclass 23, count 0 2006.217.08:12:09.50#ibcon#wrote, iclass 23, count 0 2006.217.08:12:09.50#ibcon#about to read 3, iclass 23, count 0 2006.217.08:12:09.52#ibcon#read 3, iclass 23, count 0 2006.217.08:12:09.52#ibcon#about to read 4, iclass 23, count 0 2006.217.08:12:09.52#ibcon#read 4, iclass 23, count 0 2006.217.08:12:09.52#ibcon#about to read 5, iclass 23, count 0 2006.217.08:12:09.52#ibcon#read 5, iclass 23, count 0 2006.217.08:12:09.52#ibcon#about to read 6, iclass 23, count 0 2006.217.08:12:09.52#ibcon#read 6, iclass 23, count 0 2006.217.08:12:09.52#ibcon#end of sib2, iclass 23, count 0 2006.217.08:12:09.52#ibcon#*mode == 0, iclass 23, count 0 2006.217.08:12:09.52#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.217.08:12:09.52#ibcon#[25=USB\r\n] 2006.217.08:12:09.52#ibcon#*before write, iclass 23, count 0 2006.217.08:12:09.52#ibcon#enter sib2, iclass 23, count 0 2006.217.08:12:09.52#ibcon#flushed, iclass 23, count 0 2006.217.08:12:09.52#ibcon#about to write, iclass 23, count 0 2006.217.08:12:09.52#ibcon#wrote, iclass 23, count 0 2006.217.08:12:09.52#ibcon#about to read 3, iclass 23, count 0 2006.217.08:12:09.55#ibcon#read 3, iclass 23, count 0 2006.217.08:12:09.55#ibcon#about to read 4, iclass 23, count 0 2006.217.08:12:09.55#ibcon#read 4, iclass 23, count 0 2006.217.08:12:09.55#ibcon#about to read 5, iclass 23, count 0 2006.217.08:12:09.55#ibcon#read 5, iclass 23, count 0 2006.217.08:12:09.55#ibcon#about to read 6, iclass 23, count 0 2006.217.08:12:09.55#ibcon#read 6, iclass 23, count 0 2006.217.08:12:09.55#ibcon#end of sib2, iclass 23, count 0 2006.217.08:12:09.55#ibcon#*after write, iclass 23, count 0 2006.217.08:12:09.55#ibcon#*before return 0, iclass 23, count 0 2006.217.08:12:09.55#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.217.08:12:09.55#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.217.08:12:09.55#ibcon#about to clear, iclass 23 cls_cnt 0 2006.217.08:12:09.55#ibcon#cleared, iclass 23 cls_cnt 0 2006.217.08:12:09.55$vc4f8/valo=6,772.99 2006.217.08:12:09.55#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.217.08:12:09.55#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.217.08:12:09.55#ibcon#ireg 17 cls_cnt 0 2006.217.08:12:09.55#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.217.08:12:09.55#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.217.08:12:09.55#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.217.08:12:09.55#ibcon#enter wrdev, iclass 25, count 0 2006.217.08:12:09.55#ibcon#first serial, iclass 25, count 0 2006.217.08:12:09.55#ibcon#enter sib2, iclass 25, count 0 2006.217.08:12:09.55#ibcon#flushed, iclass 25, count 0 2006.217.08:12:09.55#ibcon#about to write, iclass 25, count 0 2006.217.08:12:09.55#ibcon#wrote, iclass 25, count 0 2006.217.08:12:09.55#ibcon#about to read 3, iclass 25, count 0 2006.217.08:12:09.57#ibcon#read 3, iclass 25, count 0 2006.217.08:12:09.57#ibcon#about to read 4, iclass 25, count 0 2006.217.08:12:09.57#ibcon#read 4, iclass 25, count 0 2006.217.08:12:09.57#ibcon#about to read 5, iclass 25, count 0 2006.217.08:12:09.57#ibcon#read 5, iclass 25, count 0 2006.217.08:12:09.57#ibcon#about to read 6, iclass 25, count 0 2006.217.08:12:09.57#ibcon#read 6, iclass 25, count 0 2006.217.08:12:09.57#ibcon#end of sib2, iclass 25, count 0 2006.217.08:12:09.57#ibcon#*mode == 0, iclass 25, count 0 2006.217.08:12:09.57#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.217.08:12:09.57#ibcon#[26=FRQ=06,772.99\r\n] 2006.217.08:12:09.57#ibcon#*before write, iclass 25, count 0 2006.217.08:12:09.57#ibcon#enter sib2, iclass 25, count 0 2006.217.08:12:09.57#ibcon#flushed, iclass 25, count 0 2006.217.08:12:09.57#ibcon#about to write, iclass 25, count 0 2006.217.08:12:09.57#ibcon#wrote, iclass 25, count 0 2006.217.08:12:09.57#ibcon#about to read 3, iclass 25, count 0 2006.217.08:12:09.62#ibcon#read 3, iclass 25, count 0 2006.217.08:12:09.62#ibcon#about to read 4, iclass 25, count 0 2006.217.08:12:09.62#ibcon#read 4, iclass 25, count 0 2006.217.08:12:09.62#ibcon#about to read 5, iclass 25, count 0 2006.217.08:12:09.62#ibcon#read 5, iclass 25, count 0 2006.217.08:12:09.62#ibcon#about to read 6, iclass 25, count 0 2006.217.08:12:09.62#ibcon#read 6, iclass 25, count 0 2006.217.08:12:09.62#ibcon#end of sib2, iclass 25, count 0 2006.217.08:12:09.62#ibcon#*after write, iclass 25, count 0 2006.217.08:12:09.62#ibcon#*before return 0, iclass 25, count 0 2006.217.08:12:09.62#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.217.08:12:09.62#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.217.08:12:09.62#ibcon#about to clear, iclass 25 cls_cnt 0 2006.217.08:12:09.62#ibcon#cleared, iclass 25 cls_cnt 0 2006.217.08:12:09.62$vc4f8/va=6,6 2006.217.08:12:09.62#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.217.08:12:09.62#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.217.08:12:09.62#ibcon#ireg 11 cls_cnt 2 2006.217.08:12:09.62#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.217.08:12:09.67#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.217.08:12:09.67#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.217.08:12:09.67#ibcon#enter wrdev, iclass 27, count 2 2006.217.08:12:09.67#ibcon#first serial, iclass 27, count 2 2006.217.08:12:09.67#ibcon#enter sib2, iclass 27, count 2 2006.217.08:12:09.67#ibcon#flushed, iclass 27, count 2 2006.217.08:12:09.67#ibcon#about to write, iclass 27, count 2 2006.217.08:12:09.67#ibcon#wrote, iclass 27, count 2 2006.217.08:12:09.67#ibcon#about to read 3, iclass 27, count 2 2006.217.08:12:09.69#ibcon#read 3, iclass 27, count 2 2006.217.08:12:09.69#ibcon#about to read 4, iclass 27, count 2 2006.217.08:12:09.69#ibcon#read 4, iclass 27, count 2 2006.217.08:12:09.69#ibcon#about to read 5, iclass 27, count 2 2006.217.08:12:09.69#ibcon#read 5, iclass 27, count 2 2006.217.08:12:09.69#ibcon#about to read 6, iclass 27, count 2 2006.217.08:12:09.69#ibcon#read 6, iclass 27, count 2 2006.217.08:12:09.69#ibcon#end of sib2, iclass 27, count 2 2006.217.08:12:09.69#ibcon#*mode == 0, iclass 27, count 2 2006.217.08:12:09.69#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.217.08:12:09.69#ibcon#[25=AT06-06\r\n] 2006.217.08:12:09.69#ibcon#*before write, iclass 27, count 2 2006.217.08:12:09.69#ibcon#enter sib2, iclass 27, count 2 2006.217.08:12:09.69#ibcon#flushed, iclass 27, count 2 2006.217.08:12:09.69#ibcon#about to write, iclass 27, count 2 2006.217.08:12:09.69#ibcon#wrote, iclass 27, count 2 2006.217.08:12:09.69#ibcon#about to read 3, iclass 27, count 2 2006.217.08:12:09.72#ibcon#read 3, iclass 27, count 2 2006.217.08:12:09.72#ibcon#about to read 4, iclass 27, count 2 2006.217.08:12:09.72#ibcon#read 4, iclass 27, count 2 2006.217.08:12:09.72#ibcon#about to read 5, iclass 27, count 2 2006.217.08:12:09.72#ibcon#read 5, iclass 27, count 2 2006.217.08:12:09.72#ibcon#about to read 6, iclass 27, count 2 2006.217.08:12:09.72#ibcon#read 6, iclass 27, count 2 2006.217.08:12:09.72#ibcon#end of sib2, iclass 27, count 2 2006.217.08:12:09.72#ibcon#*after write, iclass 27, count 2 2006.217.08:12:09.72#ibcon#*before return 0, iclass 27, count 2 2006.217.08:12:09.72#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.217.08:12:09.72#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.217.08:12:09.72#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.217.08:12:09.72#ibcon#ireg 7 cls_cnt 0 2006.217.08:12:09.72#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.217.08:12:09.84#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.217.08:12:09.84#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.217.08:12:09.84#ibcon#enter wrdev, iclass 27, count 0 2006.217.08:12:09.84#ibcon#first serial, iclass 27, count 0 2006.217.08:12:09.84#ibcon#enter sib2, iclass 27, count 0 2006.217.08:12:09.84#ibcon#flushed, iclass 27, count 0 2006.217.08:12:09.84#ibcon#about to write, iclass 27, count 0 2006.217.08:12:09.84#ibcon#wrote, iclass 27, count 0 2006.217.08:12:09.84#ibcon#about to read 3, iclass 27, count 0 2006.217.08:12:09.86#ibcon#read 3, iclass 27, count 0 2006.217.08:12:09.86#ibcon#about to read 4, iclass 27, count 0 2006.217.08:12:09.86#ibcon#read 4, iclass 27, count 0 2006.217.08:12:09.86#ibcon#about to read 5, iclass 27, count 0 2006.217.08:12:09.86#ibcon#read 5, iclass 27, count 0 2006.217.08:12:09.86#ibcon#about to read 6, iclass 27, count 0 2006.217.08:12:09.86#ibcon#read 6, iclass 27, count 0 2006.217.08:12:09.86#ibcon#end of sib2, iclass 27, count 0 2006.217.08:12:09.86#ibcon#*mode == 0, iclass 27, count 0 2006.217.08:12:09.86#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.217.08:12:09.86#ibcon#[25=USB\r\n] 2006.217.08:12:09.86#ibcon#*before write, iclass 27, count 0 2006.217.08:12:09.86#ibcon#enter sib2, iclass 27, count 0 2006.217.08:12:09.86#ibcon#flushed, iclass 27, count 0 2006.217.08:12:09.86#ibcon#about to write, iclass 27, count 0 2006.217.08:12:09.86#ibcon#wrote, iclass 27, count 0 2006.217.08:12:09.86#ibcon#about to read 3, iclass 27, count 0 2006.217.08:12:09.89#ibcon#read 3, iclass 27, count 0 2006.217.08:12:09.89#ibcon#about to read 4, iclass 27, count 0 2006.217.08:12:09.89#ibcon#read 4, iclass 27, count 0 2006.217.08:12:09.89#ibcon#about to read 5, iclass 27, count 0 2006.217.08:12:09.89#ibcon#read 5, iclass 27, count 0 2006.217.08:12:09.89#ibcon#about to read 6, iclass 27, count 0 2006.217.08:12:09.89#ibcon#read 6, iclass 27, count 0 2006.217.08:12:09.89#ibcon#end of sib2, iclass 27, count 0 2006.217.08:12:09.89#ibcon#*after write, iclass 27, count 0 2006.217.08:12:09.89#ibcon#*before return 0, iclass 27, count 0 2006.217.08:12:09.89#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.217.08:12:09.89#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.217.08:12:09.89#ibcon#about to clear, iclass 27 cls_cnt 0 2006.217.08:12:09.89#ibcon#cleared, iclass 27 cls_cnt 0 2006.217.08:12:09.89$vc4f8/valo=7,832.99 2006.217.08:12:09.89#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.217.08:12:09.89#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.217.08:12:09.89#ibcon#ireg 17 cls_cnt 0 2006.217.08:12:09.89#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.217.08:12:09.89#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.217.08:12:09.89#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.217.08:12:09.89#ibcon#enter wrdev, iclass 29, count 0 2006.217.08:12:09.89#ibcon#first serial, iclass 29, count 0 2006.217.08:12:09.89#ibcon#enter sib2, iclass 29, count 0 2006.217.08:12:09.89#ibcon#flushed, iclass 29, count 0 2006.217.08:12:09.89#ibcon#about to write, iclass 29, count 0 2006.217.08:12:09.89#ibcon#wrote, iclass 29, count 0 2006.217.08:12:09.89#ibcon#about to read 3, iclass 29, count 0 2006.217.08:12:09.91#ibcon#read 3, iclass 29, count 0 2006.217.08:12:09.91#ibcon#about to read 4, iclass 29, count 0 2006.217.08:12:09.91#ibcon#read 4, iclass 29, count 0 2006.217.08:12:09.91#ibcon#about to read 5, iclass 29, count 0 2006.217.08:12:09.91#ibcon#read 5, iclass 29, count 0 2006.217.08:12:09.91#ibcon#about to read 6, iclass 29, count 0 2006.217.08:12:09.91#ibcon#read 6, iclass 29, count 0 2006.217.08:12:09.91#ibcon#end of sib2, iclass 29, count 0 2006.217.08:12:09.91#ibcon#*mode == 0, iclass 29, count 0 2006.217.08:12:09.91#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.217.08:12:09.91#ibcon#[26=FRQ=07,832.99\r\n] 2006.217.08:12:09.91#ibcon#*before write, iclass 29, count 0 2006.217.08:12:09.91#ibcon#enter sib2, iclass 29, count 0 2006.217.08:12:09.91#ibcon#flushed, iclass 29, count 0 2006.217.08:12:09.91#ibcon#about to write, iclass 29, count 0 2006.217.08:12:09.91#ibcon#wrote, iclass 29, count 0 2006.217.08:12:09.91#ibcon#about to read 3, iclass 29, count 0 2006.217.08:12:09.95#ibcon#read 3, iclass 29, count 0 2006.217.08:12:09.95#ibcon#about to read 4, iclass 29, count 0 2006.217.08:12:09.95#ibcon#read 4, iclass 29, count 0 2006.217.08:12:09.95#ibcon#about to read 5, iclass 29, count 0 2006.217.08:12:09.95#ibcon#read 5, iclass 29, count 0 2006.217.08:12:09.95#ibcon#about to read 6, iclass 29, count 0 2006.217.08:12:09.95#ibcon#read 6, iclass 29, count 0 2006.217.08:12:09.95#ibcon#end of sib2, iclass 29, count 0 2006.217.08:12:09.95#ibcon#*after write, iclass 29, count 0 2006.217.08:12:09.95#ibcon#*before return 0, iclass 29, count 0 2006.217.08:12:09.95#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.217.08:12:09.95#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.217.08:12:09.95#ibcon#about to clear, iclass 29 cls_cnt 0 2006.217.08:12:09.95#ibcon#cleared, iclass 29 cls_cnt 0 2006.217.08:12:09.95$vc4f8/va=7,6 2006.217.08:12:09.95#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.217.08:12:09.95#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.217.08:12:09.95#ibcon#ireg 11 cls_cnt 2 2006.217.08:12:09.95#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.217.08:12:10.01#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.217.08:12:10.01#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.217.08:12:10.01#ibcon#enter wrdev, iclass 31, count 2 2006.217.08:12:10.01#ibcon#first serial, iclass 31, count 2 2006.217.08:12:10.01#ibcon#enter sib2, iclass 31, count 2 2006.217.08:12:10.01#ibcon#flushed, iclass 31, count 2 2006.217.08:12:10.01#ibcon#about to write, iclass 31, count 2 2006.217.08:12:10.01#ibcon#wrote, iclass 31, count 2 2006.217.08:12:10.01#ibcon#about to read 3, iclass 31, count 2 2006.217.08:12:10.03#ibcon#read 3, iclass 31, count 2 2006.217.08:12:10.03#ibcon#about to read 4, iclass 31, count 2 2006.217.08:12:10.03#ibcon#read 4, iclass 31, count 2 2006.217.08:12:10.03#ibcon#about to read 5, iclass 31, count 2 2006.217.08:12:10.03#ibcon#read 5, iclass 31, count 2 2006.217.08:12:10.03#ibcon#about to read 6, iclass 31, count 2 2006.217.08:12:10.03#ibcon#read 6, iclass 31, count 2 2006.217.08:12:10.03#ibcon#end of sib2, iclass 31, count 2 2006.217.08:12:10.03#ibcon#*mode == 0, iclass 31, count 2 2006.217.08:12:10.03#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.217.08:12:10.03#ibcon#[25=AT07-06\r\n] 2006.217.08:12:10.03#ibcon#*before write, iclass 31, count 2 2006.217.08:12:10.03#ibcon#enter sib2, iclass 31, count 2 2006.217.08:12:10.03#ibcon#flushed, iclass 31, count 2 2006.217.08:12:10.03#ibcon#about to write, iclass 31, count 2 2006.217.08:12:10.03#ibcon#wrote, iclass 31, count 2 2006.217.08:12:10.03#ibcon#about to read 3, iclass 31, count 2 2006.217.08:12:10.06#ibcon#read 3, iclass 31, count 2 2006.217.08:12:10.06#ibcon#about to read 4, iclass 31, count 2 2006.217.08:12:10.06#ibcon#read 4, iclass 31, count 2 2006.217.08:12:10.06#ibcon#about to read 5, iclass 31, count 2 2006.217.08:12:10.06#ibcon#read 5, iclass 31, count 2 2006.217.08:12:10.06#ibcon#about to read 6, iclass 31, count 2 2006.217.08:12:10.06#ibcon#read 6, iclass 31, count 2 2006.217.08:12:10.06#ibcon#end of sib2, iclass 31, count 2 2006.217.08:12:10.06#ibcon#*after write, iclass 31, count 2 2006.217.08:12:10.06#ibcon#*before return 0, iclass 31, count 2 2006.217.08:12:10.06#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.217.08:12:10.06#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.217.08:12:10.06#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.217.08:12:10.06#ibcon#ireg 7 cls_cnt 0 2006.217.08:12:10.06#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.217.08:12:10.18#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.217.08:12:10.18#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.217.08:12:10.18#ibcon#enter wrdev, iclass 31, count 0 2006.217.08:12:10.18#ibcon#first serial, iclass 31, count 0 2006.217.08:12:10.18#ibcon#enter sib2, iclass 31, count 0 2006.217.08:12:10.18#ibcon#flushed, iclass 31, count 0 2006.217.08:12:10.18#ibcon#about to write, iclass 31, count 0 2006.217.08:12:10.18#ibcon#wrote, iclass 31, count 0 2006.217.08:12:10.18#ibcon#about to read 3, iclass 31, count 0 2006.217.08:12:10.21#ibcon#read 3, iclass 31, count 0 2006.217.08:12:10.21#ibcon#about to read 4, iclass 31, count 0 2006.217.08:12:10.21#ibcon#read 4, iclass 31, count 0 2006.217.08:12:10.21#ibcon#about to read 5, iclass 31, count 0 2006.217.08:12:10.21#ibcon#read 5, iclass 31, count 0 2006.217.08:12:10.21#ibcon#about to read 6, iclass 31, count 0 2006.217.08:12:10.21#ibcon#read 6, iclass 31, count 0 2006.217.08:12:10.21#ibcon#end of sib2, iclass 31, count 0 2006.217.08:12:10.21#ibcon#*mode == 0, iclass 31, count 0 2006.217.08:12:10.21#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.217.08:12:10.21#ibcon#[25=USB\r\n] 2006.217.08:12:10.21#ibcon#*before write, iclass 31, count 0 2006.217.08:12:10.21#ibcon#enter sib2, iclass 31, count 0 2006.217.08:12:10.21#ibcon#flushed, iclass 31, count 0 2006.217.08:12:10.21#ibcon#about to write, iclass 31, count 0 2006.217.08:12:10.21#ibcon#wrote, iclass 31, count 0 2006.217.08:12:10.21#ibcon#about to read 3, iclass 31, count 0 2006.217.08:12:10.24#ibcon#read 3, iclass 31, count 0 2006.217.08:12:10.24#ibcon#about to read 4, iclass 31, count 0 2006.217.08:12:10.24#ibcon#read 4, iclass 31, count 0 2006.217.08:12:10.24#ibcon#about to read 5, iclass 31, count 0 2006.217.08:12:10.24#ibcon#read 5, iclass 31, count 0 2006.217.08:12:10.24#ibcon#about to read 6, iclass 31, count 0 2006.217.08:12:10.24#ibcon#read 6, iclass 31, count 0 2006.217.08:12:10.24#ibcon#end of sib2, iclass 31, count 0 2006.217.08:12:10.24#ibcon#*after write, iclass 31, count 0 2006.217.08:12:10.24#ibcon#*before return 0, iclass 31, count 0 2006.217.08:12:10.24#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.217.08:12:10.24#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.217.08:12:10.24#ibcon#about to clear, iclass 31 cls_cnt 0 2006.217.08:12:10.24#ibcon#cleared, iclass 31 cls_cnt 0 2006.217.08:12:10.24$vc4f8/valo=8,852.99 2006.217.08:12:10.24#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.217.08:12:10.24#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.217.08:12:10.24#ibcon#ireg 17 cls_cnt 0 2006.217.08:12:10.24#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.217.08:12:10.24#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.217.08:12:10.24#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.217.08:12:10.24#ibcon#enter wrdev, iclass 33, count 0 2006.217.08:12:10.24#ibcon#first serial, iclass 33, count 0 2006.217.08:12:10.24#ibcon#enter sib2, iclass 33, count 0 2006.217.08:12:10.24#ibcon#flushed, iclass 33, count 0 2006.217.08:12:10.24#ibcon#about to write, iclass 33, count 0 2006.217.08:12:10.24#ibcon#wrote, iclass 33, count 0 2006.217.08:12:10.24#ibcon#about to read 3, iclass 33, count 0 2006.217.08:12:10.26#ibcon#read 3, iclass 33, count 0 2006.217.08:12:10.26#ibcon#about to read 4, iclass 33, count 0 2006.217.08:12:10.26#ibcon#read 4, iclass 33, count 0 2006.217.08:12:10.26#ibcon#about to read 5, iclass 33, count 0 2006.217.08:12:10.26#ibcon#read 5, iclass 33, count 0 2006.217.08:12:10.26#ibcon#about to read 6, iclass 33, count 0 2006.217.08:12:10.26#ibcon#read 6, iclass 33, count 0 2006.217.08:12:10.26#ibcon#end of sib2, iclass 33, count 0 2006.217.08:12:10.26#ibcon#*mode == 0, iclass 33, count 0 2006.217.08:12:10.26#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.217.08:12:10.26#ibcon#[26=FRQ=08,852.99\r\n] 2006.217.08:12:10.26#ibcon#*before write, iclass 33, count 0 2006.217.08:12:10.26#ibcon#enter sib2, iclass 33, count 0 2006.217.08:12:10.26#ibcon#flushed, iclass 33, count 0 2006.217.08:12:10.26#ibcon#about to write, iclass 33, count 0 2006.217.08:12:10.26#ibcon#wrote, iclass 33, count 0 2006.217.08:12:10.26#ibcon#about to read 3, iclass 33, count 0 2006.217.08:12:10.30#ibcon#read 3, iclass 33, count 0 2006.217.08:12:10.30#ibcon#about to read 4, iclass 33, count 0 2006.217.08:12:10.30#ibcon#read 4, iclass 33, count 0 2006.217.08:12:10.30#ibcon#about to read 5, iclass 33, count 0 2006.217.08:12:10.30#ibcon#read 5, iclass 33, count 0 2006.217.08:12:10.30#ibcon#about to read 6, iclass 33, count 0 2006.217.08:12:10.30#ibcon#read 6, iclass 33, count 0 2006.217.08:12:10.30#ibcon#end of sib2, iclass 33, count 0 2006.217.08:12:10.30#ibcon#*after write, iclass 33, count 0 2006.217.08:12:10.30#ibcon#*before return 0, iclass 33, count 0 2006.217.08:12:10.30#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.217.08:12:10.30#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.217.08:12:10.30#ibcon#about to clear, iclass 33 cls_cnt 0 2006.217.08:12:10.30#ibcon#cleared, iclass 33 cls_cnt 0 2006.217.08:12:10.30$vc4f8/va=8,7 2006.217.08:12:10.30#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.217.08:12:10.30#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.217.08:12:10.30#ibcon#ireg 11 cls_cnt 2 2006.217.08:12:10.30#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.217.08:12:10.36#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.217.08:12:10.36#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.217.08:12:10.36#ibcon#enter wrdev, iclass 35, count 2 2006.217.08:12:10.36#ibcon#first serial, iclass 35, count 2 2006.217.08:12:10.36#ibcon#enter sib2, iclass 35, count 2 2006.217.08:12:10.36#ibcon#flushed, iclass 35, count 2 2006.217.08:12:10.36#ibcon#about to write, iclass 35, count 2 2006.217.08:12:10.36#ibcon#wrote, iclass 35, count 2 2006.217.08:12:10.36#ibcon#about to read 3, iclass 35, count 2 2006.217.08:12:10.38#ibcon#read 3, iclass 35, count 2 2006.217.08:12:10.38#ibcon#about to read 4, iclass 35, count 2 2006.217.08:12:10.38#ibcon#read 4, iclass 35, count 2 2006.217.08:12:10.38#ibcon#about to read 5, iclass 35, count 2 2006.217.08:12:10.38#ibcon#read 5, iclass 35, count 2 2006.217.08:12:10.38#ibcon#about to read 6, iclass 35, count 2 2006.217.08:12:10.38#ibcon#read 6, iclass 35, count 2 2006.217.08:12:10.38#ibcon#end of sib2, iclass 35, count 2 2006.217.08:12:10.38#ibcon#*mode == 0, iclass 35, count 2 2006.217.08:12:10.38#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.217.08:12:10.38#ibcon#[25=AT08-07\r\n] 2006.217.08:12:10.38#ibcon#*before write, iclass 35, count 2 2006.217.08:12:10.38#ibcon#enter sib2, iclass 35, count 2 2006.217.08:12:10.38#ibcon#flushed, iclass 35, count 2 2006.217.08:12:10.38#ibcon#about to write, iclass 35, count 2 2006.217.08:12:10.38#ibcon#wrote, iclass 35, count 2 2006.217.08:12:10.38#ibcon#about to read 3, iclass 35, count 2 2006.217.08:12:10.41#ibcon#read 3, iclass 35, count 2 2006.217.08:12:10.41#ibcon#about to read 4, iclass 35, count 2 2006.217.08:12:10.41#ibcon#read 4, iclass 35, count 2 2006.217.08:12:10.41#ibcon#about to read 5, iclass 35, count 2 2006.217.08:12:10.41#ibcon#read 5, iclass 35, count 2 2006.217.08:12:10.41#ibcon#about to read 6, iclass 35, count 2 2006.217.08:12:10.41#ibcon#read 6, iclass 35, count 2 2006.217.08:12:10.41#ibcon#end of sib2, iclass 35, count 2 2006.217.08:12:10.41#ibcon#*after write, iclass 35, count 2 2006.217.08:12:10.41#ibcon#*before return 0, iclass 35, count 2 2006.217.08:12:10.41#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.217.08:12:10.41#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.217.08:12:10.41#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.217.08:12:10.41#ibcon#ireg 7 cls_cnt 0 2006.217.08:12:10.41#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.217.08:12:10.53#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.217.08:12:10.53#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.217.08:12:10.53#ibcon#enter wrdev, iclass 35, count 0 2006.217.08:12:10.53#ibcon#first serial, iclass 35, count 0 2006.217.08:12:10.53#ibcon#enter sib2, iclass 35, count 0 2006.217.08:12:10.53#ibcon#flushed, iclass 35, count 0 2006.217.08:12:10.53#ibcon#about to write, iclass 35, count 0 2006.217.08:12:10.53#ibcon#wrote, iclass 35, count 0 2006.217.08:12:10.53#ibcon#about to read 3, iclass 35, count 0 2006.217.08:12:10.55#ibcon#read 3, iclass 35, count 0 2006.217.08:12:10.55#ibcon#about to read 4, iclass 35, count 0 2006.217.08:12:10.55#ibcon#read 4, iclass 35, count 0 2006.217.08:12:10.55#ibcon#about to read 5, iclass 35, count 0 2006.217.08:12:10.55#ibcon#read 5, iclass 35, count 0 2006.217.08:12:10.55#ibcon#about to read 6, iclass 35, count 0 2006.217.08:12:10.55#ibcon#read 6, iclass 35, count 0 2006.217.08:12:10.55#ibcon#end of sib2, iclass 35, count 0 2006.217.08:12:10.55#ibcon#*mode == 0, iclass 35, count 0 2006.217.08:12:10.55#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.217.08:12:10.55#ibcon#[25=USB\r\n] 2006.217.08:12:10.55#ibcon#*before write, iclass 35, count 0 2006.217.08:12:10.55#ibcon#enter sib2, iclass 35, count 0 2006.217.08:12:10.55#ibcon#flushed, iclass 35, count 0 2006.217.08:12:10.55#ibcon#about to write, iclass 35, count 0 2006.217.08:12:10.55#ibcon#wrote, iclass 35, count 0 2006.217.08:12:10.55#ibcon#about to read 3, iclass 35, count 0 2006.217.08:12:10.58#ibcon#read 3, iclass 35, count 0 2006.217.08:12:10.58#ibcon#about to read 4, iclass 35, count 0 2006.217.08:12:10.58#ibcon#read 4, iclass 35, count 0 2006.217.08:12:10.58#ibcon#about to read 5, iclass 35, count 0 2006.217.08:12:10.58#ibcon#read 5, iclass 35, count 0 2006.217.08:12:10.58#ibcon#about to read 6, iclass 35, count 0 2006.217.08:12:10.58#ibcon#read 6, iclass 35, count 0 2006.217.08:12:10.58#ibcon#end of sib2, iclass 35, count 0 2006.217.08:12:10.58#ibcon#*after write, iclass 35, count 0 2006.217.08:12:10.58#ibcon#*before return 0, iclass 35, count 0 2006.217.08:12:10.58#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.217.08:12:10.58#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.217.08:12:10.58#ibcon#about to clear, iclass 35 cls_cnt 0 2006.217.08:12:10.58#ibcon#cleared, iclass 35 cls_cnt 0 2006.217.08:12:10.58$vc4f8/vblo=1,632.99 2006.217.08:12:10.58#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.217.08:12:10.58#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.217.08:12:10.58#ibcon#ireg 17 cls_cnt 0 2006.217.08:12:10.58#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.217.08:12:10.58#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.217.08:12:10.58#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.217.08:12:10.58#ibcon#enter wrdev, iclass 37, count 0 2006.217.08:12:10.58#ibcon#first serial, iclass 37, count 0 2006.217.08:12:10.58#ibcon#enter sib2, iclass 37, count 0 2006.217.08:12:10.58#ibcon#flushed, iclass 37, count 0 2006.217.08:12:10.58#ibcon#about to write, iclass 37, count 0 2006.217.08:12:10.58#ibcon#wrote, iclass 37, count 0 2006.217.08:12:10.58#ibcon#about to read 3, iclass 37, count 0 2006.217.08:12:10.60#ibcon#read 3, iclass 37, count 0 2006.217.08:12:10.60#ibcon#about to read 4, iclass 37, count 0 2006.217.08:12:10.60#ibcon#read 4, iclass 37, count 0 2006.217.08:12:10.60#ibcon#about to read 5, iclass 37, count 0 2006.217.08:12:10.60#ibcon#read 5, iclass 37, count 0 2006.217.08:12:10.60#ibcon#about to read 6, iclass 37, count 0 2006.217.08:12:10.60#ibcon#read 6, iclass 37, count 0 2006.217.08:12:10.60#ibcon#end of sib2, iclass 37, count 0 2006.217.08:12:10.60#ibcon#*mode == 0, iclass 37, count 0 2006.217.08:12:10.60#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.217.08:12:10.60#ibcon#[28=FRQ=01,632.99\r\n] 2006.217.08:12:10.60#ibcon#*before write, iclass 37, count 0 2006.217.08:12:10.60#ibcon#enter sib2, iclass 37, count 0 2006.217.08:12:10.60#ibcon#flushed, iclass 37, count 0 2006.217.08:12:10.60#ibcon#about to write, iclass 37, count 0 2006.217.08:12:10.60#ibcon#wrote, iclass 37, count 0 2006.217.08:12:10.60#ibcon#about to read 3, iclass 37, count 0 2006.217.08:12:10.64#ibcon#read 3, iclass 37, count 0 2006.217.08:12:10.64#ibcon#about to read 4, iclass 37, count 0 2006.217.08:12:10.64#ibcon#read 4, iclass 37, count 0 2006.217.08:12:10.64#ibcon#about to read 5, iclass 37, count 0 2006.217.08:12:10.64#ibcon#read 5, iclass 37, count 0 2006.217.08:12:10.64#ibcon#about to read 6, iclass 37, count 0 2006.217.08:12:10.64#ibcon#read 6, iclass 37, count 0 2006.217.08:12:10.64#ibcon#end of sib2, iclass 37, count 0 2006.217.08:12:10.64#ibcon#*after write, iclass 37, count 0 2006.217.08:12:10.64#ibcon#*before return 0, iclass 37, count 0 2006.217.08:12:10.64#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.217.08:12:10.64#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.217.08:12:10.64#ibcon#about to clear, iclass 37 cls_cnt 0 2006.217.08:12:10.64#ibcon#cleared, iclass 37 cls_cnt 0 2006.217.08:12:10.64$vc4f8/vb=1,4 2006.217.08:12:10.64#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.217.08:12:10.64#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.217.08:12:10.64#ibcon#ireg 11 cls_cnt 2 2006.217.08:12:10.64#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.217.08:12:10.64#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.217.08:12:10.64#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.217.08:12:10.64#ibcon#enter wrdev, iclass 39, count 2 2006.217.08:12:10.64#ibcon#first serial, iclass 39, count 2 2006.217.08:12:10.64#ibcon#enter sib2, iclass 39, count 2 2006.217.08:12:10.64#ibcon#flushed, iclass 39, count 2 2006.217.08:12:10.64#ibcon#about to write, iclass 39, count 2 2006.217.08:12:10.64#ibcon#wrote, iclass 39, count 2 2006.217.08:12:10.64#ibcon#about to read 3, iclass 39, count 2 2006.217.08:12:10.66#ibcon#read 3, iclass 39, count 2 2006.217.08:12:10.66#ibcon#about to read 4, iclass 39, count 2 2006.217.08:12:10.66#ibcon#read 4, iclass 39, count 2 2006.217.08:12:10.66#ibcon#about to read 5, iclass 39, count 2 2006.217.08:12:10.66#ibcon#read 5, iclass 39, count 2 2006.217.08:12:10.66#ibcon#about to read 6, iclass 39, count 2 2006.217.08:12:10.66#ibcon#read 6, iclass 39, count 2 2006.217.08:12:10.66#ibcon#end of sib2, iclass 39, count 2 2006.217.08:12:10.66#ibcon#*mode == 0, iclass 39, count 2 2006.217.08:12:10.66#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.217.08:12:10.66#ibcon#[27=AT01-04\r\n] 2006.217.08:12:10.66#ibcon#*before write, iclass 39, count 2 2006.217.08:12:10.66#ibcon#enter sib2, iclass 39, count 2 2006.217.08:12:10.66#ibcon#flushed, iclass 39, count 2 2006.217.08:12:10.66#ibcon#about to write, iclass 39, count 2 2006.217.08:12:10.66#ibcon#wrote, iclass 39, count 2 2006.217.08:12:10.66#ibcon#about to read 3, iclass 39, count 2 2006.217.08:12:10.69#ibcon#read 3, iclass 39, count 2 2006.217.08:12:10.69#ibcon#about to read 4, iclass 39, count 2 2006.217.08:12:10.69#ibcon#read 4, iclass 39, count 2 2006.217.08:12:10.69#ibcon#about to read 5, iclass 39, count 2 2006.217.08:12:10.69#ibcon#read 5, iclass 39, count 2 2006.217.08:12:10.69#ibcon#about to read 6, iclass 39, count 2 2006.217.08:12:10.69#ibcon#read 6, iclass 39, count 2 2006.217.08:12:10.69#ibcon#end of sib2, iclass 39, count 2 2006.217.08:12:10.69#ibcon#*after write, iclass 39, count 2 2006.217.08:12:10.69#ibcon#*before return 0, iclass 39, count 2 2006.217.08:12:10.69#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.217.08:12:10.69#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.217.08:12:10.69#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.217.08:12:10.69#ibcon#ireg 7 cls_cnt 0 2006.217.08:12:10.69#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.217.08:12:10.81#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.217.08:12:10.81#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.217.08:12:10.81#ibcon#enter wrdev, iclass 39, count 0 2006.217.08:12:10.81#ibcon#first serial, iclass 39, count 0 2006.217.08:12:10.81#ibcon#enter sib2, iclass 39, count 0 2006.217.08:12:10.81#ibcon#flushed, iclass 39, count 0 2006.217.08:12:10.81#ibcon#about to write, iclass 39, count 0 2006.217.08:12:10.81#ibcon#wrote, iclass 39, count 0 2006.217.08:12:10.81#ibcon#about to read 3, iclass 39, count 0 2006.217.08:12:10.83#ibcon#read 3, iclass 39, count 0 2006.217.08:12:10.83#ibcon#about to read 4, iclass 39, count 0 2006.217.08:12:10.83#ibcon#read 4, iclass 39, count 0 2006.217.08:12:10.83#ibcon#about to read 5, iclass 39, count 0 2006.217.08:12:10.83#ibcon#read 5, iclass 39, count 0 2006.217.08:12:10.83#ibcon#about to read 6, iclass 39, count 0 2006.217.08:12:10.83#ibcon#read 6, iclass 39, count 0 2006.217.08:12:10.83#ibcon#end of sib2, iclass 39, count 0 2006.217.08:12:10.83#ibcon#*mode == 0, iclass 39, count 0 2006.217.08:12:10.83#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.217.08:12:10.83#ibcon#[27=USB\r\n] 2006.217.08:12:10.83#ibcon#*before write, iclass 39, count 0 2006.217.08:12:10.83#ibcon#enter sib2, iclass 39, count 0 2006.217.08:12:10.83#ibcon#flushed, iclass 39, count 0 2006.217.08:12:10.83#ibcon#about to write, iclass 39, count 0 2006.217.08:12:10.83#ibcon#wrote, iclass 39, count 0 2006.217.08:12:10.83#ibcon#about to read 3, iclass 39, count 0 2006.217.08:12:10.86#ibcon#read 3, iclass 39, count 0 2006.217.08:12:10.86#ibcon#about to read 4, iclass 39, count 0 2006.217.08:12:10.86#ibcon#read 4, iclass 39, count 0 2006.217.08:12:10.86#ibcon#about to read 5, iclass 39, count 0 2006.217.08:12:10.86#ibcon#read 5, iclass 39, count 0 2006.217.08:12:10.86#ibcon#about to read 6, iclass 39, count 0 2006.217.08:12:10.86#ibcon#read 6, iclass 39, count 0 2006.217.08:12:10.86#ibcon#end of sib2, iclass 39, count 0 2006.217.08:12:10.86#ibcon#*after write, iclass 39, count 0 2006.217.08:12:10.86#ibcon#*before return 0, iclass 39, count 0 2006.217.08:12:10.86#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.217.08:12:10.86#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.217.08:12:10.86#ibcon#about to clear, iclass 39 cls_cnt 0 2006.217.08:12:10.86#ibcon#cleared, iclass 39 cls_cnt 0 2006.217.08:12:10.86$vc4f8/vblo=2,640.99 2006.217.08:12:10.86#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.217.08:12:10.86#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.217.08:12:10.86#ibcon#ireg 17 cls_cnt 0 2006.217.08:12:10.86#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.217.08:12:10.86#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.217.08:12:10.86#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.217.08:12:10.86#ibcon#enter wrdev, iclass 3, count 0 2006.217.08:12:10.86#ibcon#first serial, iclass 3, count 0 2006.217.08:12:10.86#ibcon#enter sib2, iclass 3, count 0 2006.217.08:12:10.86#ibcon#flushed, iclass 3, count 0 2006.217.08:12:10.86#ibcon#about to write, iclass 3, count 0 2006.217.08:12:10.86#ibcon#wrote, iclass 3, count 0 2006.217.08:12:10.86#ibcon#about to read 3, iclass 3, count 0 2006.217.08:12:10.88#ibcon#read 3, iclass 3, count 0 2006.217.08:12:10.88#ibcon#about to read 4, iclass 3, count 0 2006.217.08:12:10.88#ibcon#read 4, iclass 3, count 0 2006.217.08:12:10.88#ibcon#about to read 5, iclass 3, count 0 2006.217.08:12:10.88#ibcon#read 5, iclass 3, count 0 2006.217.08:12:10.88#ibcon#about to read 6, iclass 3, count 0 2006.217.08:12:10.88#ibcon#read 6, iclass 3, count 0 2006.217.08:12:10.88#ibcon#end of sib2, iclass 3, count 0 2006.217.08:12:10.88#ibcon#*mode == 0, iclass 3, count 0 2006.217.08:12:10.88#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.217.08:12:10.88#ibcon#[28=FRQ=02,640.99\r\n] 2006.217.08:12:10.88#ibcon#*before write, iclass 3, count 0 2006.217.08:12:10.88#ibcon#enter sib2, iclass 3, count 0 2006.217.08:12:10.88#ibcon#flushed, iclass 3, count 0 2006.217.08:12:10.88#ibcon#about to write, iclass 3, count 0 2006.217.08:12:10.88#ibcon#wrote, iclass 3, count 0 2006.217.08:12:10.88#ibcon#about to read 3, iclass 3, count 0 2006.217.08:12:10.92#ibcon#read 3, iclass 3, count 0 2006.217.08:12:10.92#ibcon#about to read 4, iclass 3, count 0 2006.217.08:12:10.92#ibcon#read 4, iclass 3, count 0 2006.217.08:12:10.92#ibcon#about to read 5, iclass 3, count 0 2006.217.08:12:10.92#ibcon#read 5, iclass 3, count 0 2006.217.08:12:10.92#ibcon#about to read 6, iclass 3, count 0 2006.217.08:12:10.92#ibcon#read 6, iclass 3, count 0 2006.217.08:12:10.92#ibcon#end of sib2, iclass 3, count 0 2006.217.08:12:10.92#ibcon#*after write, iclass 3, count 0 2006.217.08:12:10.92#ibcon#*before return 0, iclass 3, count 0 2006.217.08:12:10.92#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.217.08:12:10.92#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.217.08:12:10.92#ibcon#about to clear, iclass 3 cls_cnt 0 2006.217.08:12:10.92#ibcon#cleared, iclass 3 cls_cnt 0 2006.217.08:12:10.92$vc4f8/vb=2,4 2006.217.08:12:10.92#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.217.08:12:10.92#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.217.08:12:10.92#ibcon#ireg 11 cls_cnt 2 2006.217.08:12:10.92#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.217.08:12:10.98#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.217.08:12:10.98#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.217.08:12:10.98#ibcon#enter wrdev, iclass 5, count 2 2006.217.08:12:10.98#ibcon#first serial, iclass 5, count 2 2006.217.08:12:10.98#ibcon#enter sib2, iclass 5, count 2 2006.217.08:12:10.98#ibcon#flushed, iclass 5, count 2 2006.217.08:12:10.98#ibcon#about to write, iclass 5, count 2 2006.217.08:12:10.98#ibcon#wrote, iclass 5, count 2 2006.217.08:12:10.98#ibcon#about to read 3, iclass 5, count 2 2006.217.08:12:11.00#ibcon#read 3, iclass 5, count 2 2006.217.08:12:11.00#ibcon#about to read 4, iclass 5, count 2 2006.217.08:12:11.00#ibcon#read 4, iclass 5, count 2 2006.217.08:12:11.00#ibcon#about to read 5, iclass 5, count 2 2006.217.08:12:11.00#ibcon#read 5, iclass 5, count 2 2006.217.08:12:11.00#ibcon#about to read 6, iclass 5, count 2 2006.217.08:12:11.00#ibcon#read 6, iclass 5, count 2 2006.217.08:12:11.00#ibcon#end of sib2, iclass 5, count 2 2006.217.08:12:11.00#ibcon#*mode == 0, iclass 5, count 2 2006.217.08:12:11.00#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.217.08:12:11.00#ibcon#[27=AT02-04\r\n] 2006.217.08:12:11.00#ibcon#*before write, iclass 5, count 2 2006.217.08:12:11.00#ibcon#enter sib2, iclass 5, count 2 2006.217.08:12:11.00#ibcon#flushed, iclass 5, count 2 2006.217.08:12:11.00#ibcon#about to write, iclass 5, count 2 2006.217.08:12:11.00#ibcon#wrote, iclass 5, count 2 2006.217.08:12:11.00#ibcon#about to read 3, iclass 5, count 2 2006.217.08:12:11.03#ibcon#read 3, iclass 5, count 2 2006.217.08:12:11.03#ibcon#about to read 4, iclass 5, count 2 2006.217.08:12:11.03#ibcon#read 4, iclass 5, count 2 2006.217.08:12:11.03#ibcon#about to read 5, iclass 5, count 2 2006.217.08:12:11.03#ibcon#read 5, iclass 5, count 2 2006.217.08:12:11.03#ibcon#about to read 6, iclass 5, count 2 2006.217.08:12:11.03#ibcon#read 6, iclass 5, count 2 2006.217.08:12:11.03#ibcon#end of sib2, iclass 5, count 2 2006.217.08:12:11.03#ibcon#*after write, iclass 5, count 2 2006.217.08:12:11.03#ibcon#*before return 0, iclass 5, count 2 2006.217.08:12:11.03#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.217.08:12:11.03#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.217.08:12:11.03#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.217.08:12:11.03#ibcon#ireg 7 cls_cnt 0 2006.217.08:12:11.03#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.217.08:12:11.15#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.217.08:12:11.15#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.217.08:12:11.15#ibcon#enter wrdev, iclass 5, count 0 2006.217.08:12:11.15#ibcon#first serial, iclass 5, count 0 2006.217.08:12:11.15#ibcon#enter sib2, iclass 5, count 0 2006.217.08:12:11.15#ibcon#flushed, iclass 5, count 0 2006.217.08:12:11.15#ibcon#about to write, iclass 5, count 0 2006.217.08:12:11.15#ibcon#wrote, iclass 5, count 0 2006.217.08:12:11.15#ibcon#about to read 3, iclass 5, count 0 2006.217.08:12:11.17#ibcon#read 3, iclass 5, count 0 2006.217.08:12:11.17#ibcon#about to read 4, iclass 5, count 0 2006.217.08:12:11.17#ibcon#read 4, iclass 5, count 0 2006.217.08:12:11.17#ibcon#about to read 5, iclass 5, count 0 2006.217.08:12:11.17#ibcon#read 5, iclass 5, count 0 2006.217.08:12:11.17#ibcon#about to read 6, iclass 5, count 0 2006.217.08:12:11.17#ibcon#read 6, iclass 5, count 0 2006.217.08:12:11.17#ibcon#end of sib2, iclass 5, count 0 2006.217.08:12:11.17#ibcon#*mode == 0, iclass 5, count 0 2006.217.08:12:11.17#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.217.08:12:11.17#ibcon#[27=USB\r\n] 2006.217.08:12:11.17#ibcon#*before write, iclass 5, count 0 2006.217.08:12:11.17#ibcon#enter sib2, iclass 5, count 0 2006.217.08:12:11.17#ibcon#flushed, iclass 5, count 0 2006.217.08:12:11.17#ibcon#about to write, iclass 5, count 0 2006.217.08:12:11.17#ibcon#wrote, iclass 5, count 0 2006.217.08:12:11.17#ibcon#about to read 3, iclass 5, count 0 2006.217.08:12:11.20#ibcon#read 3, iclass 5, count 0 2006.217.08:12:11.20#ibcon#about to read 4, iclass 5, count 0 2006.217.08:12:11.20#ibcon#read 4, iclass 5, count 0 2006.217.08:12:11.20#ibcon#about to read 5, iclass 5, count 0 2006.217.08:12:11.20#ibcon#read 5, iclass 5, count 0 2006.217.08:12:11.20#ibcon#about to read 6, iclass 5, count 0 2006.217.08:12:11.20#ibcon#read 6, iclass 5, count 0 2006.217.08:12:11.20#ibcon#end of sib2, iclass 5, count 0 2006.217.08:12:11.20#ibcon#*after write, iclass 5, count 0 2006.217.08:12:11.20#ibcon#*before return 0, iclass 5, count 0 2006.217.08:12:11.20#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.217.08:12:11.20#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.217.08:12:11.20#ibcon#about to clear, iclass 5 cls_cnt 0 2006.217.08:12:11.20#ibcon#cleared, iclass 5 cls_cnt 0 2006.217.08:12:11.20$vc4f8/vblo=3,656.99 2006.217.08:12:11.20#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.217.08:12:11.20#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.217.08:12:11.20#ibcon#ireg 17 cls_cnt 0 2006.217.08:12:11.20#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.217.08:12:11.20#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.217.08:12:11.20#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.217.08:12:11.20#ibcon#enter wrdev, iclass 7, count 0 2006.217.08:12:11.20#ibcon#first serial, iclass 7, count 0 2006.217.08:12:11.20#ibcon#enter sib2, iclass 7, count 0 2006.217.08:12:11.20#ibcon#flushed, iclass 7, count 0 2006.217.08:12:11.20#ibcon#about to write, iclass 7, count 0 2006.217.08:12:11.20#ibcon#wrote, iclass 7, count 0 2006.217.08:12:11.20#ibcon#about to read 3, iclass 7, count 0 2006.217.08:12:11.22#ibcon#read 3, iclass 7, count 0 2006.217.08:12:11.22#ibcon#about to read 4, iclass 7, count 0 2006.217.08:12:11.22#ibcon#read 4, iclass 7, count 0 2006.217.08:12:11.22#ibcon#about to read 5, iclass 7, count 0 2006.217.08:12:11.22#ibcon#read 5, iclass 7, count 0 2006.217.08:12:11.22#ibcon#about to read 6, iclass 7, count 0 2006.217.08:12:11.22#ibcon#read 6, iclass 7, count 0 2006.217.08:12:11.22#ibcon#end of sib2, iclass 7, count 0 2006.217.08:12:11.22#ibcon#*mode == 0, iclass 7, count 0 2006.217.08:12:11.22#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.217.08:12:11.22#ibcon#[28=FRQ=03,656.99\r\n] 2006.217.08:12:11.22#ibcon#*before write, iclass 7, count 0 2006.217.08:12:11.22#ibcon#enter sib2, iclass 7, count 0 2006.217.08:12:11.22#ibcon#flushed, iclass 7, count 0 2006.217.08:12:11.22#ibcon#about to write, iclass 7, count 0 2006.217.08:12:11.22#ibcon#wrote, iclass 7, count 0 2006.217.08:12:11.22#ibcon#about to read 3, iclass 7, count 0 2006.217.08:12:11.26#ibcon#read 3, iclass 7, count 0 2006.217.08:12:11.26#ibcon#about to read 4, iclass 7, count 0 2006.217.08:12:11.26#ibcon#read 4, iclass 7, count 0 2006.217.08:12:11.26#ibcon#about to read 5, iclass 7, count 0 2006.217.08:12:11.26#ibcon#read 5, iclass 7, count 0 2006.217.08:12:11.26#ibcon#about to read 6, iclass 7, count 0 2006.217.08:12:11.26#ibcon#read 6, iclass 7, count 0 2006.217.08:12:11.26#ibcon#end of sib2, iclass 7, count 0 2006.217.08:12:11.26#ibcon#*after write, iclass 7, count 0 2006.217.08:12:11.26#ibcon#*before return 0, iclass 7, count 0 2006.217.08:12:11.26#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.217.08:12:11.26#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.217.08:12:11.26#ibcon#about to clear, iclass 7 cls_cnt 0 2006.217.08:12:11.26#ibcon#cleared, iclass 7 cls_cnt 0 2006.217.08:12:11.26$vc4f8/vb=3,4 2006.217.08:12:11.26#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.217.08:12:11.26#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.217.08:12:11.26#ibcon#ireg 11 cls_cnt 2 2006.217.08:12:11.26#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.217.08:12:11.32#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.217.08:12:11.32#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.217.08:12:11.32#ibcon#enter wrdev, iclass 11, count 2 2006.217.08:12:11.32#ibcon#first serial, iclass 11, count 2 2006.217.08:12:11.32#ibcon#enter sib2, iclass 11, count 2 2006.217.08:12:11.32#ibcon#flushed, iclass 11, count 2 2006.217.08:12:11.32#ibcon#about to write, iclass 11, count 2 2006.217.08:12:11.32#ibcon#wrote, iclass 11, count 2 2006.217.08:12:11.32#ibcon#about to read 3, iclass 11, count 2 2006.217.08:12:11.34#ibcon#read 3, iclass 11, count 2 2006.217.08:12:11.34#ibcon#about to read 4, iclass 11, count 2 2006.217.08:12:11.34#ibcon#read 4, iclass 11, count 2 2006.217.08:12:11.34#ibcon#about to read 5, iclass 11, count 2 2006.217.08:12:11.34#ibcon#read 5, iclass 11, count 2 2006.217.08:12:11.34#ibcon#about to read 6, iclass 11, count 2 2006.217.08:12:11.34#ibcon#read 6, iclass 11, count 2 2006.217.08:12:11.34#ibcon#end of sib2, iclass 11, count 2 2006.217.08:12:11.34#ibcon#*mode == 0, iclass 11, count 2 2006.217.08:12:11.34#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.217.08:12:11.34#ibcon#[27=AT03-04\r\n] 2006.217.08:12:11.34#ibcon#*before write, iclass 11, count 2 2006.217.08:12:11.34#ibcon#enter sib2, iclass 11, count 2 2006.217.08:12:11.34#ibcon#flushed, iclass 11, count 2 2006.217.08:12:11.34#ibcon#about to write, iclass 11, count 2 2006.217.08:12:11.34#ibcon#wrote, iclass 11, count 2 2006.217.08:12:11.34#ibcon#about to read 3, iclass 11, count 2 2006.217.08:12:11.37#ibcon#read 3, iclass 11, count 2 2006.217.08:12:11.37#ibcon#about to read 4, iclass 11, count 2 2006.217.08:12:11.37#ibcon#read 4, iclass 11, count 2 2006.217.08:12:11.37#ibcon#about to read 5, iclass 11, count 2 2006.217.08:12:11.37#ibcon#read 5, iclass 11, count 2 2006.217.08:12:11.37#ibcon#about to read 6, iclass 11, count 2 2006.217.08:12:11.37#ibcon#read 6, iclass 11, count 2 2006.217.08:12:11.37#ibcon#end of sib2, iclass 11, count 2 2006.217.08:12:11.37#ibcon#*after write, iclass 11, count 2 2006.217.08:12:11.37#ibcon#*before return 0, iclass 11, count 2 2006.217.08:12:11.37#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.217.08:12:11.37#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.217.08:12:11.37#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.217.08:12:11.37#ibcon#ireg 7 cls_cnt 0 2006.217.08:12:11.37#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.217.08:12:11.49#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.217.08:12:11.49#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.217.08:12:11.49#ibcon#enter wrdev, iclass 11, count 0 2006.217.08:12:11.49#ibcon#first serial, iclass 11, count 0 2006.217.08:12:11.49#ibcon#enter sib2, iclass 11, count 0 2006.217.08:12:11.49#ibcon#flushed, iclass 11, count 0 2006.217.08:12:11.49#ibcon#about to write, iclass 11, count 0 2006.217.08:12:11.49#ibcon#wrote, iclass 11, count 0 2006.217.08:12:11.49#ibcon#about to read 3, iclass 11, count 0 2006.217.08:12:11.51#ibcon#read 3, iclass 11, count 0 2006.217.08:12:11.51#ibcon#about to read 4, iclass 11, count 0 2006.217.08:12:11.51#ibcon#read 4, iclass 11, count 0 2006.217.08:12:11.51#ibcon#about to read 5, iclass 11, count 0 2006.217.08:12:11.51#ibcon#read 5, iclass 11, count 0 2006.217.08:12:11.51#ibcon#about to read 6, iclass 11, count 0 2006.217.08:12:11.51#ibcon#read 6, iclass 11, count 0 2006.217.08:12:11.51#ibcon#end of sib2, iclass 11, count 0 2006.217.08:12:11.51#ibcon#*mode == 0, iclass 11, count 0 2006.217.08:12:11.51#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.217.08:12:11.51#ibcon#[27=USB\r\n] 2006.217.08:12:11.51#ibcon#*before write, iclass 11, count 0 2006.217.08:12:11.51#ibcon#enter sib2, iclass 11, count 0 2006.217.08:12:11.51#ibcon#flushed, iclass 11, count 0 2006.217.08:12:11.51#ibcon#about to write, iclass 11, count 0 2006.217.08:12:11.51#ibcon#wrote, iclass 11, count 0 2006.217.08:12:11.51#ibcon#about to read 3, iclass 11, count 0 2006.217.08:12:11.54#ibcon#read 3, iclass 11, count 0 2006.217.08:12:11.54#ibcon#about to read 4, iclass 11, count 0 2006.217.08:12:11.54#ibcon#read 4, iclass 11, count 0 2006.217.08:12:11.54#ibcon#about to read 5, iclass 11, count 0 2006.217.08:12:11.54#ibcon#read 5, iclass 11, count 0 2006.217.08:12:11.54#ibcon#about to read 6, iclass 11, count 0 2006.217.08:12:11.54#ibcon#read 6, iclass 11, count 0 2006.217.08:12:11.54#ibcon#end of sib2, iclass 11, count 0 2006.217.08:12:11.54#ibcon#*after write, iclass 11, count 0 2006.217.08:12:11.54#ibcon#*before return 0, iclass 11, count 0 2006.217.08:12:11.54#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.217.08:12:11.54#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.217.08:12:11.54#ibcon#about to clear, iclass 11 cls_cnt 0 2006.217.08:12:11.54#ibcon#cleared, iclass 11 cls_cnt 0 2006.217.08:12:11.54$vc4f8/vblo=4,712.99 2006.217.08:12:11.54#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.217.08:12:11.54#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.217.08:12:11.54#ibcon#ireg 17 cls_cnt 0 2006.217.08:12:11.54#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.217.08:12:11.54#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.217.08:12:11.54#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.217.08:12:11.54#ibcon#enter wrdev, iclass 13, count 0 2006.217.08:12:11.54#ibcon#first serial, iclass 13, count 0 2006.217.08:12:11.54#ibcon#enter sib2, iclass 13, count 0 2006.217.08:12:11.54#ibcon#flushed, iclass 13, count 0 2006.217.08:12:11.54#ibcon#about to write, iclass 13, count 0 2006.217.08:12:11.54#ibcon#wrote, iclass 13, count 0 2006.217.08:12:11.54#ibcon#about to read 3, iclass 13, count 0 2006.217.08:12:11.56#ibcon#read 3, iclass 13, count 0 2006.217.08:12:11.56#ibcon#about to read 4, iclass 13, count 0 2006.217.08:12:11.56#ibcon#read 4, iclass 13, count 0 2006.217.08:12:11.56#ibcon#about to read 5, iclass 13, count 0 2006.217.08:12:11.56#ibcon#read 5, iclass 13, count 0 2006.217.08:12:11.56#ibcon#about to read 6, iclass 13, count 0 2006.217.08:12:11.56#ibcon#read 6, iclass 13, count 0 2006.217.08:12:11.56#ibcon#end of sib2, iclass 13, count 0 2006.217.08:12:11.56#ibcon#*mode == 0, iclass 13, count 0 2006.217.08:12:11.56#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.217.08:12:11.56#ibcon#[28=FRQ=04,712.99\r\n] 2006.217.08:12:11.56#ibcon#*before write, iclass 13, count 0 2006.217.08:12:11.56#ibcon#enter sib2, iclass 13, count 0 2006.217.08:12:11.56#ibcon#flushed, iclass 13, count 0 2006.217.08:12:11.56#ibcon#about to write, iclass 13, count 0 2006.217.08:12:11.56#ibcon#wrote, iclass 13, count 0 2006.217.08:12:11.56#ibcon#about to read 3, iclass 13, count 0 2006.217.08:12:11.60#ibcon#read 3, iclass 13, count 0 2006.217.08:12:11.60#ibcon#about to read 4, iclass 13, count 0 2006.217.08:12:11.60#ibcon#read 4, iclass 13, count 0 2006.217.08:12:11.60#ibcon#about to read 5, iclass 13, count 0 2006.217.08:12:11.60#ibcon#read 5, iclass 13, count 0 2006.217.08:12:11.60#ibcon#about to read 6, iclass 13, count 0 2006.217.08:12:11.60#ibcon#read 6, iclass 13, count 0 2006.217.08:12:11.60#ibcon#end of sib2, iclass 13, count 0 2006.217.08:12:11.60#ibcon#*after write, iclass 13, count 0 2006.217.08:12:11.60#ibcon#*before return 0, iclass 13, count 0 2006.217.08:12:11.60#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.217.08:12:11.60#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.217.08:12:11.60#ibcon#about to clear, iclass 13 cls_cnt 0 2006.217.08:12:11.60#ibcon#cleared, iclass 13 cls_cnt 0 2006.217.08:12:11.60$vc4f8/vb=4,4 2006.217.08:12:11.60#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.217.08:12:11.60#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.217.08:12:11.60#ibcon#ireg 11 cls_cnt 2 2006.217.08:12:11.60#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.217.08:12:11.66#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.217.08:12:11.66#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.217.08:12:11.66#ibcon#enter wrdev, iclass 15, count 2 2006.217.08:12:11.66#ibcon#first serial, iclass 15, count 2 2006.217.08:12:11.66#ibcon#enter sib2, iclass 15, count 2 2006.217.08:12:11.66#ibcon#flushed, iclass 15, count 2 2006.217.08:12:11.66#ibcon#about to write, iclass 15, count 2 2006.217.08:12:11.66#ibcon#wrote, iclass 15, count 2 2006.217.08:12:11.66#ibcon#about to read 3, iclass 15, count 2 2006.217.08:12:11.68#ibcon#read 3, iclass 15, count 2 2006.217.08:12:11.68#ibcon#about to read 4, iclass 15, count 2 2006.217.08:12:11.68#ibcon#read 4, iclass 15, count 2 2006.217.08:12:11.68#ibcon#about to read 5, iclass 15, count 2 2006.217.08:12:11.68#ibcon#read 5, iclass 15, count 2 2006.217.08:12:11.68#ibcon#about to read 6, iclass 15, count 2 2006.217.08:12:11.68#ibcon#read 6, iclass 15, count 2 2006.217.08:12:11.68#ibcon#end of sib2, iclass 15, count 2 2006.217.08:12:11.68#ibcon#*mode == 0, iclass 15, count 2 2006.217.08:12:11.68#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.217.08:12:11.68#ibcon#[27=AT04-04\r\n] 2006.217.08:12:11.68#ibcon#*before write, iclass 15, count 2 2006.217.08:12:11.68#ibcon#enter sib2, iclass 15, count 2 2006.217.08:12:11.68#ibcon#flushed, iclass 15, count 2 2006.217.08:12:11.68#ibcon#about to write, iclass 15, count 2 2006.217.08:12:11.68#ibcon#wrote, iclass 15, count 2 2006.217.08:12:11.68#ibcon#about to read 3, iclass 15, count 2 2006.217.08:12:11.71#ibcon#read 3, iclass 15, count 2 2006.217.08:12:11.71#ibcon#about to read 4, iclass 15, count 2 2006.217.08:12:11.71#ibcon#read 4, iclass 15, count 2 2006.217.08:12:11.71#ibcon#about to read 5, iclass 15, count 2 2006.217.08:12:11.71#ibcon#read 5, iclass 15, count 2 2006.217.08:12:11.71#ibcon#about to read 6, iclass 15, count 2 2006.217.08:12:11.71#ibcon#read 6, iclass 15, count 2 2006.217.08:12:11.71#ibcon#end of sib2, iclass 15, count 2 2006.217.08:12:11.71#ibcon#*after write, iclass 15, count 2 2006.217.08:12:11.71#ibcon#*before return 0, iclass 15, count 2 2006.217.08:12:11.71#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.217.08:12:11.71#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.217.08:12:11.71#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.217.08:12:11.71#ibcon#ireg 7 cls_cnt 0 2006.217.08:12:11.71#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.217.08:12:11.83#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.217.08:12:11.83#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.217.08:12:11.83#ibcon#enter wrdev, iclass 15, count 0 2006.217.08:12:11.83#ibcon#first serial, iclass 15, count 0 2006.217.08:12:11.83#ibcon#enter sib2, iclass 15, count 0 2006.217.08:12:11.83#ibcon#flushed, iclass 15, count 0 2006.217.08:12:11.83#ibcon#about to write, iclass 15, count 0 2006.217.08:12:11.83#ibcon#wrote, iclass 15, count 0 2006.217.08:12:11.83#ibcon#about to read 3, iclass 15, count 0 2006.217.08:12:11.85#ibcon#read 3, iclass 15, count 0 2006.217.08:12:11.85#ibcon#about to read 4, iclass 15, count 0 2006.217.08:12:11.85#ibcon#read 4, iclass 15, count 0 2006.217.08:12:11.85#ibcon#about to read 5, iclass 15, count 0 2006.217.08:12:11.85#ibcon#read 5, iclass 15, count 0 2006.217.08:12:11.85#ibcon#about to read 6, iclass 15, count 0 2006.217.08:12:11.85#ibcon#read 6, iclass 15, count 0 2006.217.08:12:11.85#ibcon#end of sib2, iclass 15, count 0 2006.217.08:12:11.85#ibcon#*mode == 0, iclass 15, count 0 2006.217.08:12:11.85#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.217.08:12:11.85#ibcon#[27=USB\r\n] 2006.217.08:12:11.85#ibcon#*before write, iclass 15, count 0 2006.217.08:12:11.85#ibcon#enter sib2, iclass 15, count 0 2006.217.08:12:11.85#ibcon#flushed, iclass 15, count 0 2006.217.08:12:11.85#ibcon#about to write, iclass 15, count 0 2006.217.08:12:11.85#ibcon#wrote, iclass 15, count 0 2006.217.08:12:11.85#ibcon#about to read 3, iclass 15, count 0 2006.217.08:12:11.88#ibcon#read 3, iclass 15, count 0 2006.217.08:12:11.88#ibcon#about to read 4, iclass 15, count 0 2006.217.08:12:11.88#ibcon#read 4, iclass 15, count 0 2006.217.08:12:11.88#ibcon#about to read 5, iclass 15, count 0 2006.217.08:12:11.88#ibcon#read 5, iclass 15, count 0 2006.217.08:12:11.88#ibcon#about to read 6, iclass 15, count 0 2006.217.08:12:11.88#ibcon#read 6, iclass 15, count 0 2006.217.08:12:11.88#ibcon#end of sib2, iclass 15, count 0 2006.217.08:12:11.88#ibcon#*after write, iclass 15, count 0 2006.217.08:12:11.88#ibcon#*before return 0, iclass 15, count 0 2006.217.08:12:11.88#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.217.08:12:11.88#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.217.08:12:11.88#ibcon#about to clear, iclass 15 cls_cnt 0 2006.217.08:12:11.88#ibcon#cleared, iclass 15 cls_cnt 0 2006.217.08:12:11.88$vc4f8/vblo=5,744.99 2006.217.08:12:11.88#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.217.08:12:11.88#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.217.08:12:11.88#ibcon#ireg 17 cls_cnt 0 2006.217.08:12:11.88#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.217.08:12:11.88#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.217.08:12:11.88#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.217.08:12:11.88#ibcon#enter wrdev, iclass 17, count 0 2006.217.08:12:11.88#ibcon#first serial, iclass 17, count 0 2006.217.08:12:11.88#ibcon#enter sib2, iclass 17, count 0 2006.217.08:12:11.88#ibcon#flushed, iclass 17, count 0 2006.217.08:12:11.88#ibcon#about to write, iclass 17, count 0 2006.217.08:12:11.88#ibcon#wrote, iclass 17, count 0 2006.217.08:12:11.88#ibcon#about to read 3, iclass 17, count 0 2006.217.08:12:11.90#ibcon#read 3, iclass 17, count 0 2006.217.08:12:11.90#ibcon#about to read 4, iclass 17, count 0 2006.217.08:12:11.90#ibcon#read 4, iclass 17, count 0 2006.217.08:12:11.90#ibcon#about to read 5, iclass 17, count 0 2006.217.08:12:11.90#ibcon#read 5, iclass 17, count 0 2006.217.08:12:11.90#ibcon#about to read 6, iclass 17, count 0 2006.217.08:12:11.90#ibcon#read 6, iclass 17, count 0 2006.217.08:12:11.90#ibcon#end of sib2, iclass 17, count 0 2006.217.08:12:11.90#ibcon#*mode == 0, iclass 17, count 0 2006.217.08:12:11.90#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.217.08:12:11.90#ibcon#[28=FRQ=05,744.99\r\n] 2006.217.08:12:11.90#ibcon#*before write, iclass 17, count 0 2006.217.08:12:11.90#ibcon#enter sib2, iclass 17, count 0 2006.217.08:12:11.90#ibcon#flushed, iclass 17, count 0 2006.217.08:12:11.90#ibcon#about to write, iclass 17, count 0 2006.217.08:12:11.90#ibcon#wrote, iclass 17, count 0 2006.217.08:12:11.90#ibcon#about to read 3, iclass 17, count 0 2006.217.08:12:11.94#ibcon#read 3, iclass 17, count 0 2006.217.08:12:11.94#ibcon#about to read 4, iclass 17, count 0 2006.217.08:12:11.94#ibcon#read 4, iclass 17, count 0 2006.217.08:12:11.94#ibcon#about to read 5, iclass 17, count 0 2006.217.08:12:11.94#ibcon#read 5, iclass 17, count 0 2006.217.08:12:11.94#ibcon#about to read 6, iclass 17, count 0 2006.217.08:12:11.94#ibcon#read 6, iclass 17, count 0 2006.217.08:12:11.94#ibcon#end of sib2, iclass 17, count 0 2006.217.08:12:11.94#ibcon#*after write, iclass 17, count 0 2006.217.08:12:11.94#ibcon#*before return 0, iclass 17, count 0 2006.217.08:12:11.94#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.217.08:12:11.94#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.217.08:12:11.94#ibcon#about to clear, iclass 17 cls_cnt 0 2006.217.08:12:11.94#ibcon#cleared, iclass 17 cls_cnt 0 2006.217.08:12:11.94$vc4f8/vb=5,4 2006.217.08:12:11.94#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.217.08:12:11.94#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.217.08:12:11.94#ibcon#ireg 11 cls_cnt 2 2006.217.08:12:11.94#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.217.08:12:12.00#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.217.08:12:12.00#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.217.08:12:12.00#ibcon#enter wrdev, iclass 19, count 2 2006.217.08:12:12.00#ibcon#first serial, iclass 19, count 2 2006.217.08:12:12.00#ibcon#enter sib2, iclass 19, count 2 2006.217.08:12:12.00#ibcon#flushed, iclass 19, count 2 2006.217.08:12:12.00#ibcon#about to write, iclass 19, count 2 2006.217.08:12:12.00#ibcon#wrote, iclass 19, count 2 2006.217.08:12:12.00#ibcon#about to read 3, iclass 19, count 2 2006.217.08:12:12.02#ibcon#read 3, iclass 19, count 2 2006.217.08:12:12.02#ibcon#about to read 4, iclass 19, count 2 2006.217.08:12:12.02#ibcon#read 4, iclass 19, count 2 2006.217.08:12:12.02#ibcon#about to read 5, iclass 19, count 2 2006.217.08:12:12.02#ibcon#read 5, iclass 19, count 2 2006.217.08:12:12.02#ibcon#about to read 6, iclass 19, count 2 2006.217.08:12:12.02#ibcon#read 6, iclass 19, count 2 2006.217.08:12:12.02#ibcon#end of sib2, iclass 19, count 2 2006.217.08:12:12.02#ibcon#*mode == 0, iclass 19, count 2 2006.217.08:12:12.02#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.217.08:12:12.02#ibcon#[27=AT05-04\r\n] 2006.217.08:12:12.02#ibcon#*before write, iclass 19, count 2 2006.217.08:12:12.02#ibcon#enter sib2, iclass 19, count 2 2006.217.08:12:12.02#ibcon#flushed, iclass 19, count 2 2006.217.08:12:12.02#ibcon#about to write, iclass 19, count 2 2006.217.08:12:12.02#ibcon#wrote, iclass 19, count 2 2006.217.08:12:12.02#ibcon#about to read 3, iclass 19, count 2 2006.217.08:12:12.05#ibcon#read 3, iclass 19, count 2 2006.217.08:12:12.05#ibcon#about to read 4, iclass 19, count 2 2006.217.08:12:12.05#ibcon#read 4, iclass 19, count 2 2006.217.08:12:12.05#ibcon#about to read 5, iclass 19, count 2 2006.217.08:12:12.05#ibcon#read 5, iclass 19, count 2 2006.217.08:12:12.05#ibcon#about to read 6, iclass 19, count 2 2006.217.08:12:12.05#ibcon#read 6, iclass 19, count 2 2006.217.08:12:12.05#ibcon#end of sib2, iclass 19, count 2 2006.217.08:12:12.05#ibcon#*after write, iclass 19, count 2 2006.217.08:12:12.05#ibcon#*before return 0, iclass 19, count 2 2006.217.08:12:12.05#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.217.08:12:12.05#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.217.08:12:12.05#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.217.08:12:12.05#ibcon#ireg 7 cls_cnt 0 2006.217.08:12:12.05#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.217.08:12:12.17#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.217.08:12:12.17#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.217.08:12:12.17#ibcon#enter wrdev, iclass 19, count 0 2006.217.08:12:12.17#ibcon#first serial, iclass 19, count 0 2006.217.08:12:12.17#ibcon#enter sib2, iclass 19, count 0 2006.217.08:12:12.17#ibcon#flushed, iclass 19, count 0 2006.217.08:12:12.17#ibcon#about to write, iclass 19, count 0 2006.217.08:12:12.17#ibcon#wrote, iclass 19, count 0 2006.217.08:12:12.17#ibcon#about to read 3, iclass 19, count 0 2006.217.08:12:12.19#ibcon#read 3, iclass 19, count 0 2006.217.08:12:12.19#ibcon#about to read 4, iclass 19, count 0 2006.217.08:12:12.19#ibcon#read 4, iclass 19, count 0 2006.217.08:12:12.19#ibcon#about to read 5, iclass 19, count 0 2006.217.08:12:12.19#ibcon#read 5, iclass 19, count 0 2006.217.08:12:12.19#ibcon#about to read 6, iclass 19, count 0 2006.217.08:12:12.19#ibcon#read 6, iclass 19, count 0 2006.217.08:12:12.19#ibcon#end of sib2, iclass 19, count 0 2006.217.08:12:12.19#ibcon#*mode == 0, iclass 19, count 0 2006.217.08:12:12.19#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.217.08:12:12.19#ibcon#[27=USB\r\n] 2006.217.08:12:12.19#ibcon#*before write, iclass 19, count 0 2006.217.08:12:12.19#ibcon#enter sib2, iclass 19, count 0 2006.217.08:12:12.19#ibcon#flushed, iclass 19, count 0 2006.217.08:12:12.19#ibcon#about to write, iclass 19, count 0 2006.217.08:12:12.19#ibcon#wrote, iclass 19, count 0 2006.217.08:12:12.19#ibcon#about to read 3, iclass 19, count 0 2006.217.08:12:12.22#ibcon#read 3, iclass 19, count 0 2006.217.08:12:12.22#ibcon#about to read 4, iclass 19, count 0 2006.217.08:12:12.22#ibcon#read 4, iclass 19, count 0 2006.217.08:12:12.22#ibcon#about to read 5, iclass 19, count 0 2006.217.08:12:12.22#ibcon#read 5, iclass 19, count 0 2006.217.08:12:12.22#ibcon#about to read 6, iclass 19, count 0 2006.217.08:12:12.22#ibcon#read 6, iclass 19, count 0 2006.217.08:12:12.22#ibcon#end of sib2, iclass 19, count 0 2006.217.08:12:12.22#ibcon#*after write, iclass 19, count 0 2006.217.08:12:12.22#ibcon#*before return 0, iclass 19, count 0 2006.217.08:12:12.22#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.217.08:12:12.22#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.217.08:12:12.22#ibcon#about to clear, iclass 19 cls_cnt 0 2006.217.08:12:12.22#ibcon#cleared, iclass 19 cls_cnt 0 2006.217.08:12:12.22$vc4f8/vblo=6,752.99 2006.217.08:12:12.22#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.217.08:12:12.22#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.217.08:12:12.22#ibcon#ireg 17 cls_cnt 0 2006.217.08:12:12.22#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.217.08:12:12.22#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.217.08:12:12.22#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.217.08:12:12.22#ibcon#enter wrdev, iclass 21, count 0 2006.217.08:12:12.22#ibcon#first serial, iclass 21, count 0 2006.217.08:12:12.22#ibcon#enter sib2, iclass 21, count 0 2006.217.08:12:12.22#ibcon#flushed, iclass 21, count 0 2006.217.08:12:12.22#ibcon#about to write, iclass 21, count 0 2006.217.08:12:12.22#ibcon#wrote, iclass 21, count 0 2006.217.08:12:12.22#ibcon#about to read 3, iclass 21, count 0 2006.217.08:12:12.24#ibcon#read 3, iclass 21, count 0 2006.217.08:12:12.24#ibcon#about to read 4, iclass 21, count 0 2006.217.08:12:12.24#ibcon#read 4, iclass 21, count 0 2006.217.08:12:12.24#ibcon#about to read 5, iclass 21, count 0 2006.217.08:12:12.24#ibcon#read 5, iclass 21, count 0 2006.217.08:12:12.24#ibcon#about to read 6, iclass 21, count 0 2006.217.08:12:12.24#ibcon#read 6, iclass 21, count 0 2006.217.08:12:12.24#ibcon#end of sib2, iclass 21, count 0 2006.217.08:12:12.24#ibcon#*mode == 0, iclass 21, count 0 2006.217.08:12:12.24#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.217.08:12:12.24#ibcon#[28=FRQ=06,752.99\r\n] 2006.217.08:12:12.24#ibcon#*before write, iclass 21, count 0 2006.217.08:12:12.24#ibcon#enter sib2, iclass 21, count 0 2006.217.08:12:12.24#ibcon#flushed, iclass 21, count 0 2006.217.08:12:12.24#ibcon#about to write, iclass 21, count 0 2006.217.08:12:12.24#ibcon#wrote, iclass 21, count 0 2006.217.08:12:12.24#ibcon#about to read 3, iclass 21, count 0 2006.217.08:12:12.28#ibcon#read 3, iclass 21, count 0 2006.217.08:12:12.28#ibcon#about to read 4, iclass 21, count 0 2006.217.08:12:12.28#ibcon#read 4, iclass 21, count 0 2006.217.08:12:12.28#ibcon#about to read 5, iclass 21, count 0 2006.217.08:12:12.28#ibcon#read 5, iclass 21, count 0 2006.217.08:12:12.28#ibcon#about to read 6, iclass 21, count 0 2006.217.08:12:12.28#ibcon#read 6, iclass 21, count 0 2006.217.08:12:12.28#ibcon#end of sib2, iclass 21, count 0 2006.217.08:12:12.28#ibcon#*after write, iclass 21, count 0 2006.217.08:12:12.28#ibcon#*before return 0, iclass 21, count 0 2006.217.08:12:12.28#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.217.08:12:12.28#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.217.08:12:12.28#ibcon#about to clear, iclass 21 cls_cnt 0 2006.217.08:12:12.28#ibcon#cleared, iclass 21 cls_cnt 0 2006.217.08:12:12.28$vc4f8/vb=6,4 2006.217.08:12:12.28#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.217.08:12:12.28#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.217.08:12:12.28#ibcon#ireg 11 cls_cnt 2 2006.217.08:12:12.28#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.217.08:12:12.34#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.217.08:12:12.34#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.217.08:12:12.34#ibcon#enter wrdev, iclass 23, count 2 2006.217.08:12:12.34#ibcon#first serial, iclass 23, count 2 2006.217.08:12:12.34#ibcon#enter sib2, iclass 23, count 2 2006.217.08:12:12.34#ibcon#flushed, iclass 23, count 2 2006.217.08:12:12.34#ibcon#about to write, iclass 23, count 2 2006.217.08:12:12.34#ibcon#wrote, iclass 23, count 2 2006.217.08:12:12.34#ibcon#about to read 3, iclass 23, count 2 2006.217.08:12:12.36#ibcon#read 3, iclass 23, count 2 2006.217.08:12:12.36#ibcon#about to read 4, iclass 23, count 2 2006.217.08:12:12.36#ibcon#read 4, iclass 23, count 2 2006.217.08:12:12.36#ibcon#about to read 5, iclass 23, count 2 2006.217.08:12:12.36#ibcon#read 5, iclass 23, count 2 2006.217.08:12:12.36#ibcon#about to read 6, iclass 23, count 2 2006.217.08:12:12.36#ibcon#read 6, iclass 23, count 2 2006.217.08:12:12.36#ibcon#end of sib2, iclass 23, count 2 2006.217.08:12:12.36#ibcon#*mode == 0, iclass 23, count 2 2006.217.08:12:12.36#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.217.08:12:12.36#ibcon#[27=AT06-04\r\n] 2006.217.08:12:12.36#ibcon#*before write, iclass 23, count 2 2006.217.08:12:12.36#ibcon#enter sib2, iclass 23, count 2 2006.217.08:12:12.36#ibcon#flushed, iclass 23, count 2 2006.217.08:12:12.36#ibcon#about to write, iclass 23, count 2 2006.217.08:12:12.36#ibcon#wrote, iclass 23, count 2 2006.217.08:12:12.36#ibcon#about to read 3, iclass 23, count 2 2006.217.08:12:12.39#ibcon#read 3, iclass 23, count 2 2006.217.08:12:12.39#ibcon#about to read 4, iclass 23, count 2 2006.217.08:12:12.39#ibcon#read 4, iclass 23, count 2 2006.217.08:12:12.39#ibcon#about to read 5, iclass 23, count 2 2006.217.08:12:12.39#ibcon#read 5, iclass 23, count 2 2006.217.08:12:12.39#ibcon#about to read 6, iclass 23, count 2 2006.217.08:12:12.39#ibcon#read 6, iclass 23, count 2 2006.217.08:12:12.39#ibcon#end of sib2, iclass 23, count 2 2006.217.08:12:12.39#ibcon#*after write, iclass 23, count 2 2006.217.08:12:12.39#ibcon#*before return 0, iclass 23, count 2 2006.217.08:12:12.39#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.217.08:12:12.39#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.217.08:12:12.39#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.217.08:12:12.39#ibcon#ireg 7 cls_cnt 0 2006.217.08:12:12.39#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.217.08:12:12.51#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.217.08:12:12.51#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.217.08:12:12.51#ibcon#enter wrdev, iclass 23, count 0 2006.217.08:12:12.51#ibcon#first serial, iclass 23, count 0 2006.217.08:12:12.51#ibcon#enter sib2, iclass 23, count 0 2006.217.08:12:12.51#ibcon#flushed, iclass 23, count 0 2006.217.08:12:12.51#ibcon#about to write, iclass 23, count 0 2006.217.08:12:12.51#ibcon#wrote, iclass 23, count 0 2006.217.08:12:12.51#ibcon#about to read 3, iclass 23, count 0 2006.217.08:12:12.53#ibcon#read 3, iclass 23, count 0 2006.217.08:12:12.53#ibcon#about to read 4, iclass 23, count 0 2006.217.08:12:12.53#ibcon#read 4, iclass 23, count 0 2006.217.08:12:12.53#ibcon#about to read 5, iclass 23, count 0 2006.217.08:12:12.53#ibcon#read 5, iclass 23, count 0 2006.217.08:12:12.53#ibcon#about to read 6, iclass 23, count 0 2006.217.08:12:12.53#ibcon#read 6, iclass 23, count 0 2006.217.08:12:12.53#ibcon#end of sib2, iclass 23, count 0 2006.217.08:12:12.53#ibcon#*mode == 0, iclass 23, count 0 2006.217.08:12:12.53#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.217.08:12:12.53#ibcon#[27=USB\r\n] 2006.217.08:12:12.53#ibcon#*before write, iclass 23, count 0 2006.217.08:12:12.53#ibcon#enter sib2, iclass 23, count 0 2006.217.08:12:12.53#ibcon#flushed, iclass 23, count 0 2006.217.08:12:12.53#ibcon#about to write, iclass 23, count 0 2006.217.08:12:12.53#ibcon#wrote, iclass 23, count 0 2006.217.08:12:12.53#ibcon#about to read 3, iclass 23, count 0 2006.217.08:12:12.56#ibcon#read 3, iclass 23, count 0 2006.217.08:12:12.56#ibcon#about to read 4, iclass 23, count 0 2006.217.08:12:12.56#ibcon#read 4, iclass 23, count 0 2006.217.08:12:12.56#ibcon#about to read 5, iclass 23, count 0 2006.217.08:12:12.56#ibcon#read 5, iclass 23, count 0 2006.217.08:12:12.56#ibcon#about to read 6, iclass 23, count 0 2006.217.08:12:12.56#ibcon#read 6, iclass 23, count 0 2006.217.08:12:12.56#ibcon#end of sib2, iclass 23, count 0 2006.217.08:12:12.56#ibcon#*after write, iclass 23, count 0 2006.217.08:12:12.56#ibcon#*before return 0, iclass 23, count 0 2006.217.08:12:12.56#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.217.08:12:12.56#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.217.08:12:12.56#ibcon#about to clear, iclass 23 cls_cnt 0 2006.217.08:12:12.56#ibcon#cleared, iclass 23 cls_cnt 0 2006.217.08:12:12.56$vc4f8/vabw=wide 2006.217.08:12:12.56#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.217.08:12:12.56#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.217.08:12:12.56#ibcon#ireg 8 cls_cnt 0 2006.217.08:12:12.56#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.217.08:12:12.56#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.217.08:12:12.56#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.217.08:12:12.56#ibcon#enter wrdev, iclass 25, count 0 2006.217.08:12:12.56#ibcon#first serial, iclass 25, count 0 2006.217.08:12:12.56#ibcon#enter sib2, iclass 25, count 0 2006.217.08:12:12.56#ibcon#flushed, iclass 25, count 0 2006.217.08:12:12.56#ibcon#about to write, iclass 25, count 0 2006.217.08:12:12.56#ibcon#wrote, iclass 25, count 0 2006.217.08:12:12.56#ibcon#about to read 3, iclass 25, count 0 2006.217.08:12:12.58#ibcon#read 3, iclass 25, count 0 2006.217.08:12:12.58#ibcon#about to read 4, iclass 25, count 0 2006.217.08:12:12.58#ibcon#read 4, iclass 25, count 0 2006.217.08:12:12.58#ibcon#about to read 5, iclass 25, count 0 2006.217.08:12:12.58#ibcon#read 5, iclass 25, count 0 2006.217.08:12:12.58#ibcon#about to read 6, iclass 25, count 0 2006.217.08:12:12.58#ibcon#read 6, iclass 25, count 0 2006.217.08:12:12.58#ibcon#end of sib2, iclass 25, count 0 2006.217.08:12:12.58#ibcon#*mode == 0, iclass 25, count 0 2006.217.08:12:12.58#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.217.08:12:12.58#ibcon#[25=BW32\r\n] 2006.217.08:12:12.58#ibcon#*before write, iclass 25, count 0 2006.217.08:12:12.58#ibcon#enter sib2, iclass 25, count 0 2006.217.08:12:12.58#ibcon#flushed, iclass 25, count 0 2006.217.08:12:12.58#ibcon#about to write, iclass 25, count 0 2006.217.08:12:12.58#ibcon#wrote, iclass 25, count 0 2006.217.08:12:12.58#ibcon#about to read 3, iclass 25, count 0 2006.217.08:12:12.61#ibcon#read 3, iclass 25, count 0 2006.217.08:12:12.61#ibcon#about to read 4, iclass 25, count 0 2006.217.08:12:12.61#ibcon#read 4, iclass 25, count 0 2006.217.08:12:12.61#ibcon#about to read 5, iclass 25, count 0 2006.217.08:12:12.61#ibcon#read 5, iclass 25, count 0 2006.217.08:12:12.61#ibcon#about to read 6, iclass 25, count 0 2006.217.08:12:12.61#ibcon#read 6, iclass 25, count 0 2006.217.08:12:12.61#ibcon#end of sib2, iclass 25, count 0 2006.217.08:12:12.61#ibcon#*after write, iclass 25, count 0 2006.217.08:12:12.61#ibcon#*before return 0, iclass 25, count 0 2006.217.08:12:12.61#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.217.08:12:12.61#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.217.08:12:12.61#ibcon#about to clear, iclass 25 cls_cnt 0 2006.217.08:12:12.61#ibcon#cleared, iclass 25 cls_cnt 0 2006.217.08:12:12.61$vc4f8/vbbw=wide 2006.217.08:12:12.61#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.217.08:12:12.61#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.217.08:12:12.61#ibcon#ireg 8 cls_cnt 0 2006.217.08:12:12.61#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.217.08:12:12.68#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.217.08:12:12.68#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.217.08:12:12.68#ibcon#enter wrdev, iclass 27, count 0 2006.217.08:12:12.68#ibcon#first serial, iclass 27, count 0 2006.217.08:12:12.68#ibcon#enter sib2, iclass 27, count 0 2006.217.08:12:12.68#ibcon#flushed, iclass 27, count 0 2006.217.08:12:12.68#ibcon#about to write, iclass 27, count 0 2006.217.08:12:12.68#ibcon#wrote, iclass 27, count 0 2006.217.08:12:12.68#ibcon#about to read 3, iclass 27, count 0 2006.217.08:12:12.70#ibcon#read 3, iclass 27, count 0 2006.217.08:12:12.70#ibcon#about to read 4, iclass 27, count 0 2006.217.08:12:12.70#ibcon#read 4, iclass 27, count 0 2006.217.08:12:12.70#ibcon#about to read 5, iclass 27, count 0 2006.217.08:12:12.70#ibcon#read 5, iclass 27, count 0 2006.217.08:12:12.70#ibcon#about to read 6, iclass 27, count 0 2006.217.08:12:12.70#ibcon#read 6, iclass 27, count 0 2006.217.08:12:12.70#ibcon#end of sib2, iclass 27, count 0 2006.217.08:12:12.70#ibcon#*mode == 0, iclass 27, count 0 2006.217.08:12:12.70#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.217.08:12:12.70#ibcon#[27=BW32\r\n] 2006.217.08:12:12.70#ibcon#*before write, iclass 27, count 0 2006.217.08:12:12.70#ibcon#enter sib2, iclass 27, count 0 2006.217.08:12:12.70#ibcon#flushed, iclass 27, count 0 2006.217.08:12:12.70#ibcon#about to write, iclass 27, count 0 2006.217.08:12:12.70#ibcon#wrote, iclass 27, count 0 2006.217.08:12:12.70#ibcon#about to read 3, iclass 27, count 0 2006.217.08:12:12.73#ibcon#read 3, iclass 27, count 0 2006.217.08:12:12.73#ibcon#about to read 4, iclass 27, count 0 2006.217.08:12:12.73#ibcon#read 4, iclass 27, count 0 2006.217.08:12:12.73#ibcon#about to read 5, iclass 27, count 0 2006.217.08:12:12.73#ibcon#read 5, iclass 27, count 0 2006.217.08:12:12.73#ibcon#about to read 6, iclass 27, count 0 2006.217.08:12:12.73#ibcon#read 6, iclass 27, count 0 2006.217.08:12:12.73#ibcon#end of sib2, iclass 27, count 0 2006.217.08:12:12.73#ibcon#*after write, iclass 27, count 0 2006.217.08:12:12.73#ibcon#*before return 0, iclass 27, count 0 2006.217.08:12:12.73#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.217.08:12:12.73#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.217.08:12:12.73#ibcon#about to clear, iclass 27 cls_cnt 0 2006.217.08:12:12.73#ibcon#cleared, iclass 27 cls_cnt 0 2006.217.08:12:12.73$4f8m12a/ifd4f 2006.217.08:12:12.73$ifd4f/lo= 2006.217.08:12:12.73$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.217.08:12:12.73$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.217.08:12:12.73$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.217.08:12:12.73$ifd4f/patch= 2006.217.08:12:12.73$ifd4f/patch=lo1,a1,a2,a3,a4 2006.217.08:12:12.73$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.217.08:12:12.73$ifd4f/patch=lo3,a5,a6,a7,a8 2006.217.08:12:12.73$4f8m12a/"form=m,16.000,1:2 2006.217.08:12:12.73$4f8m12a/"tpicd 2006.217.08:12:12.73$4f8m12a/echo=off 2006.217.08:12:12.73$4f8m12a/xlog=off 2006.217.08:12:12.73:!2006.217.08:12:40 2006.217.08:12:23.14#trakl#Source acquired 2006.217.08:12:25.14#flagr#flagr/antenna,acquired 2006.217.08:12:40.00:preob 2006.217.08:12:41.14/onsource/TRACKING 2006.217.08:12:41.14:!2006.217.08:12:50 2006.217.08:12:50.00:data_valid=on 2006.217.08:12:50.00:midob 2006.217.08:12:50.14/onsource/TRACKING 2006.217.08:12:50.14/wx/30.63,1008.6,64 2006.217.08:12:50.34/cable/+6.3872E-03 2006.217.08:12:51.43/va/01,05,usb,yes,32,33 2006.217.08:12:51.43/va/02,04,usb,yes,30,31 2006.217.08:12:51.43/va/03,04,usb,yes,28,28 2006.217.08:12:51.43/va/04,04,usb,yes,31,33 2006.217.08:12:51.43/va/05,07,usb,yes,33,35 2006.217.08:12:51.43/va/06,06,usb,yes,32,32 2006.217.08:12:51.43/va/07,06,usb,yes,33,32 2006.217.08:12:51.43/va/08,07,usb,yes,31,30 2006.217.08:12:51.66/valo/01,532.99,yes,locked 2006.217.08:12:51.66/valo/02,572.99,yes,locked 2006.217.08:12:51.66/valo/03,672.99,yes,locked 2006.217.08:12:51.66/valo/04,832.99,yes,locked 2006.217.08:12:51.66/valo/05,652.99,yes,locked 2006.217.08:12:51.66/valo/06,772.99,yes,locked 2006.217.08:12:51.66/valo/07,832.99,yes,locked 2006.217.08:12:51.66/valo/08,852.99,yes,locked 2006.217.08:12:52.75/vb/01,04,usb,yes,30,29 2006.217.08:12:52.75/vb/02,04,usb,yes,32,33 2006.217.08:12:52.75/vb/03,04,usb,yes,28,32 2006.217.08:12:52.75/vb/04,04,usb,yes,29,29 2006.217.08:12:52.75/vb/05,04,usb,yes,28,32 2006.217.08:12:52.75/vb/06,04,usb,yes,29,32 2006.217.08:12:52.75/vb/07,04,usb,yes,31,31 2006.217.08:12:52.75/vb/08,04,usb,yes,28,32 2006.217.08:12:52.99/vblo/01,632.99,yes,locked 2006.217.08:12:52.99/vblo/02,640.99,yes,locked 2006.217.08:12:52.99/vblo/03,656.99,yes,locked 2006.217.08:12:52.99/vblo/04,712.99,yes,locked 2006.217.08:12:52.99/vblo/05,744.99,yes,locked 2006.217.08:12:52.99/vblo/06,752.99,yes,locked 2006.217.08:12:52.99/vblo/07,734.99,yes,locked 2006.217.08:12:52.99/vblo/08,744.99,yes,locked 2006.217.08:12:53.14/vabw/8 2006.217.08:12:53.29/vbbw/8 2006.217.08:12:53.42/xfe/off,on,15.0 2006.217.08:12:53.81/ifatt/23,28,28,28 2006.217.08:12:54.07/fmout-gps/S +4.47E-07 2006.217.08:12:54.14:!2006.217.08:13:50 2006.217.08:13:50.00:data_valid=off 2006.217.08:13:50.00:postob 2006.217.08:13:50.11/cable/+6.3871E-03 2006.217.08:13:50.11/wx/30.61,1008.6,64 2006.217.08:13:51.07/fmout-gps/S +4.48E-07 2006.217.08:13:51.07:scan_name=217-0814,k06217,60 2006.217.08:13:51.07:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.217.08:13:51.14#flagr#flagr/antenna,new-source 2006.217.08:13:52.14:checkk5 2006.217.08:13:52.52/chk_autoobs//k5ts1/ autoobs is running! 2006.217.08:13:52.89/chk_autoobs//k5ts2/ autoobs is running! 2006.217.08:13:53.27/chk_autoobs//k5ts3/ autoobs is running! 2006.217.08:13:53.64/chk_autoobs//k5ts4/ autoobs is running! 2006.217.08:13:54.01/chk_obsdata//k5ts1/T2170812??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.08:13:54.37/chk_obsdata//k5ts2/T2170812??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.08:13:54.73/chk_obsdata//k5ts3/T2170812??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.08:13:55.11/chk_obsdata//k5ts4/T2170812??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.08:13:55.80/k5log//k5ts1_log_newline 2006.217.08:13:56.49/k5log//k5ts2_log_newline 2006.217.08:13:57.18/k5log//k5ts3_log_newline 2006.217.08:13:57.86/k5log//k5ts4_log_newline 2006.217.08:13:57.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.217.08:13:57.89:4f8m12a=2 2006.217.08:13:57.89$4f8m12a/echo=on 2006.217.08:13:57.89$4f8m12a/pcalon 2006.217.08:13:57.89$pcalon/"no phase cal control is implemented here 2006.217.08:13:57.89$4f8m12a/"tpicd=stop 2006.217.08:13:57.89$4f8m12a/vc4f8 2006.217.08:13:57.89$vc4f8/valo=1,532.99 2006.217.08:13:57.89#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.217.08:13:57.89#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.217.08:13:57.89#ibcon#ireg 17 cls_cnt 0 2006.217.08:13:57.89#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.217.08:13:57.89#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.217.08:13:57.89#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.217.08:13:57.89#ibcon#enter wrdev, iclass 29, count 0 2006.217.08:13:57.89#ibcon#first serial, iclass 29, count 0 2006.217.08:13:57.89#ibcon#enter sib2, iclass 29, count 0 2006.217.08:13:57.89#ibcon#flushed, iclass 29, count 0 2006.217.08:13:57.89#ibcon#about to write, iclass 29, count 0 2006.217.08:13:57.89#ibcon#wrote, iclass 29, count 0 2006.217.08:13:57.89#ibcon#about to read 3, iclass 29, count 0 2006.217.08:13:57.91#ibcon#read 3, iclass 29, count 0 2006.217.08:13:57.91#ibcon#about to read 4, iclass 29, count 0 2006.217.08:13:57.91#ibcon#read 4, iclass 29, count 0 2006.217.08:13:57.91#ibcon#about to read 5, iclass 29, count 0 2006.217.08:13:57.91#ibcon#read 5, iclass 29, count 0 2006.217.08:13:57.91#ibcon#about to read 6, iclass 29, count 0 2006.217.08:13:57.91#ibcon#read 6, iclass 29, count 0 2006.217.08:13:57.91#ibcon#end of sib2, iclass 29, count 0 2006.217.08:13:57.91#ibcon#*mode == 0, iclass 29, count 0 2006.217.08:13:57.91#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.217.08:13:57.91#ibcon#[26=FRQ=01,532.99\r\n] 2006.217.08:13:57.91#ibcon#*before write, iclass 29, count 0 2006.217.08:13:57.91#ibcon#enter sib2, iclass 29, count 0 2006.217.08:13:57.91#ibcon#flushed, iclass 29, count 0 2006.217.08:13:57.91#ibcon#about to write, iclass 29, count 0 2006.217.08:13:57.91#ibcon#wrote, iclass 29, count 0 2006.217.08:13:57.91#ibcon#about to read 3, iclass 29, count 0 2006.217.08:13:57.96#ibcon#read 3, iclass 29, count 0 2006.217.08:13:57.96#ibcon#about to read 4, iclass 29, count 0 2006.217.08:13:57.96#ibcon#read 4, iclass 29, count 0 2006.217.08:13:57.96#ibcon#about to read 5, iclass 29, count 0 2006.217.08:13:57.96#ibcon#read 5, iclass 29, count 0 2006.217.08:13:57.96#ibcon#about to read 6, iclass 29, count 0 2006.217.08:13:57.96#ibcon#read 6, iclass 29, count 0 2006.217.08:13:57.96#ibcon#end of sib2, iclass 29, count 0 2006.217.08:13:57.96#ibcon#*after write, iclass 29, count 0 2006.217.08:13:57.96#ibcon#*before return 0, iclass 29, count 0 2006.217.08:13:57.96#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.217.08:13:57.96#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.217.08:13:57.96#ibcon#about to clear, iclass 29 cls_cnt 0 2006.217.08:13:57.96#ibcon#cleared, iclass 29 cls_cnt 0 2006.217.08:13:57.96$vc4f8/va=1,5 2006.217.08:13:57.96#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.217.08:13:57.96#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.217.08:13:57.96#ibcon#ireg 11 cls_cnt 2 2006.217.08:13:57.96#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.217.08:13:57.96#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.217.08:13:57.96#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.217.08:13:57.96#ibcon#enter wrdev, iclass 31, count 2 2006.217.08:13:57.96#ibcon#first serial, iclass 31, count 2 2006.217.08:13:57.96#ibcon#enter sib2, iclass 31, count 2 2006.217.08:13:57.96#ibcon#flushed, iclass 31, count 2 2006.217.08:13:57.96#ibcon#about to write, iclass 31, count 2 2006.217.08:13:57.96#ibcon#wrote, iclass 31, count 2 2006.217.08:13:57.96#ibcon#about to read 3, iclass 31, count 2 2006.217.08:13:57.98#ibcon#read 3, iclass 31, count 2 2006.217.08:13:57.98#ibcon#about to read 4, iclass 31, count 2 2006.217.08:13:57.98#ibcon#read 4, iclass 31, count 2 2006.217.08:13:57.98#ibcon#about to read 5, iclass 31, count 2 2006.217.08:13:57.98#ibcon#read 5, iclass 31, count 2 2006.217.08:13:57.98#ibcon#about to read 6, iclass 31, count 2 2006.217.08:13:57.98#ibcon#read 6, iclass 31, count 2 2006.217.08:13:57.98#ibcon#end of sib2, iclass 31, count 2 2006.217.08:13:57.98#ibcon#*mode == 0, iclass 31, count 2 2006.217.08:13:57.98#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.217.08:13:57.98#ibcon#[25=AT01-05\r\n] 2006.217.08:13:57.98#ibcon#*before write, iclass 31, count 2 2006.217.08:13:57.98#ibcon#enter sib2, iclass 31, count 2 2006.217.08:13:57.98#ibcon#flushed, iclass 31, count 2 2006.217.08:13:57.98#ibcon#about to write, iclass 31, count 2 2006.217.08:13:57.98#ibcon#wrote, iclass 31, count 2 2006.217.08:13:57.98#ibcon#about to read 3, iclass 31, count 2 2006.217.08:13:58.01#ibcon#read 3, iclass 31, count 2 2006.217.08:13:58.01#ibcon#about to read 4, iclass 31, count 2 2006.217.08:13:58.01#ibcon#read 4, iclass 31, count 2 2006.217.08:13:58.01#ibcon#about to read 5, iclass 31, count 2 2006.217.08:13:58.01#ibcon#read 5, iclass 31, count 2 2006.217.08:13:58.01#ibcon#about to read 6, iclass 31, count 2 2006.217.08:13:58.01#ibcon#read 6, iclass 31, count 2 2006.217.08:13:58.01#ibcon#end of sib2, iclass 31, count 2 2006.217.08:13:58.01#ibcon#*after write, iclass 31, count 2 2006.217.08:13:58.01#ibcon#*before return 0, iclass 31, count 2 2006.217.08:13:58.01#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.217.08:13:58.01#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.217.08:13:58.01#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.217.08:13:58.01#ibcon#ireg 7 cls_cnt 0 2006.217.08:13:58.01#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.217.08:13:58.13#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.217.08:13:58.13#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.217.08:13:58.13#ibcon#enter wrdev, iclass 31, count 0 2006.217.08:13:58.13#ibcon#first serial, iclass 31, count 0 2006.217.08:13:58.13#ibcon#enter sib2, iclass 31, count 0 2006.217.08:13:58.13#ibcon#flushed, iclass 31, count 0 2006.217.08:13:58.13#ibcon#about to write, iclass 31, count 0 2006.217.08:13:58.13#ibcon#wrote, iclass 31, count 0 2006.217.08:13:58.13#ibcon#about to read 3, iclass 31, count 0 2006.217.08:13:58.15#ibcon#read 3, iclass 31, count 0 2006.217.08:13:58.15#ibcon#about to read 4, iclass 31, count 0 2006.217.08:13:58.15#ibcon#read 4, iclass 31, count 0 2006.217.08:13:58.15#ibcon#about to read 5, iclass 31, count 0 2006.217.08:13:58.15#ibcon#read 5, iclass 31, count 0 2006.217.08:13:58.15#ibcon#about to read 6, iclass 31, count 0 2006.217.08:13:58.15#ibcon#read 6, iclass 31, count 0 2006.217.08:13:58.15#ibcon#end of sib2, iclass 31, count 0 2006.217.08:13:58.15#ibcon#*mode == 0, iclass 31, count 0 2006.217.08:13:58.15#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.217.08:13:58.15#ibcon#[25=USB\r\n] 2006.217.08:13:58.15#ibcon#*before write, iclass 31, count 0 2006.217.08:13:58.15#ibcon#enter sib2, iclass 31, count 0 2006.217.08:13:58.15#ibcon#flushed, iclass 31, count 0 2006.217.08:13:58.15#ibcon#about to write, iclass 31, count 0 2006.217.08:13:58.15#ibcon#wrote, iclass 31, count 0 2006.217.08:13:58.15#ibcon#about to read 3, iclass 31, count 0 2006.217.08:13:58.18#ibcon#read 3, iclass 31, count 0 2006.217.08:13:58.18#ibcon#about to read 4, iclass 31, count 0 2006.217.08:13:58.18#ibcon#read 4, iclass 31, count 0 2006.217.08:13:58.18#ibcon#about to read 5, iclass 31, count 0 2006.217.08:13:58.18#ibcon#read 5, iclass 31, count 0 2006.217.08:13:58.18#ibcon#about to read 6, iclass 31, count 0 2006.217.08:13:58.18#ibcon#read 6, iclass 31, count 0 2006.217.08:13:58.18#ibcon#end of sib2, iclass 31, count 0 2006.217.08:13:58.18#ibcon#*after write, iclass 31, count 0 2006.217.08:13:58.18#ibcon#*before return 0, iclass 31, count 0 2006.217.08:13:58.18#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.217.08:13:58.18#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.217.08:13:58.18#ibcon#about to clear, iclass 31 cls_cnt 0 2006.217.08:13:58.18#ibcon#cleared, iclass 31 cls_cnt 0 2006.217.08:13:58.18$vc4f8/valo=2,572.99 2006.217.08:13:58.18#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.217.08:13:58.18#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.217.08:13:58.18#ibcon#ireg 17 cls_cnt 0 2006.217.08:13:58.18#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.217.08:13:58.18#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.217.08:13:58.18#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.217.08:13:58.18#ibcon#enter wrdev, iclass 33, count 0 2006.217.08:13:58.18#ibcon#first serial, iclass 33, count 0 2006.217.08:13:58.18#ibcon#enter sib2, iclass 33, count 0 2006.217.08:13:58.18#ibcon#flushed, iclass 33, count 0 2006.217.08:13:58.18#ibcon#about to write, iclass 33, count 0 2006.217.08:13:58.18#ibcon#wrote, iclass 33, count 0 2006.217.08:13:58.18#ibcon#about to read 3, iclass 33, count 0 2006.217.08:13:58.20#ibcon#read 3, iclass 33, count 0 2006.217.08:13:58.20#ibcon#about to read 4, iclass 33, count 0 2006.217.08:13:58.20#ibcon#read 4, iclass 33, count 0 2006.217.08:13:58.20#ibcon#about to read 5, iclass 33, count 0 2006.217.08:13:58.20#ibcon#read 5, iclass 33, count 0 2006.217.08:13:58.20#ibcon#about to read 6, iclass 33, count 0 2006.217.08:13:58.20#ibcon#read 6, iclass 33, count 0 2006.217.08:13:58.20#ibcon#end of sib2, iclass 33, count 0 2006.217.08:13:58.20#ibcon#*mode == 0, iclass 33, count 0 2006.217.08:13:58.20#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.217.08:13:58.20#ibcon#[26=FRQ=02,572.99\r\n] 2006.217.08:13:58.20#ibcon#*before write, iclass 33, count 0 2006.217.08:13:58.20#ibcon#enter sib2, iclass 33, count 0 2006.217.08:13:58.20#ibcon#flushed, iclass 33, count 0 2006.217.08:13:58.20#ibcon#about to write, iclass 33, count 0 2006.217.08:13:58.20#ibcon#wrote, iclass 33, count 0 2006.217.08:13:58.20#ibcon#about to read 3, iclass 33, count 0 2006.217.08:13:58.25#ibcon#read 3, iclass 33, count 0 2006.217.08:13:58.25#ibcon#about to read 4, iclass 33, count 0 2006.217.08:13:58.25#ibcon#read 4, iclass 33, count 0 2006.217.08:13:58.25#ibcon#about to read 5, iclass 33, count 0 2006.217.08:13:58.25#ibcon#read 5, iclass 33, count 0 2006.217.08:13:58.25#ibcon#about to read 6, iclass 33, count 0 2006.217.08:13:58.25#ibcon#read 6, iclass 33, count 0 2006.217.08:13:58.25#ibcon#end of sib2, iclass 33, count 0 2006.217.08:13:58.25#ibcon#*after write, iclass 33, count 0 2006.217.08:13:58.25#ibcon#*before return 0, iclass 33, count 0 2006.217.08:13:58.25#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.217.08:13:58.25#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.217.08:13:58.25#ibcon#about to clear, iclass 33 cls_cnt 0 2006.217.08:13:58.25#ibcon#cleared, iclass 33 cls_cnt 0 2006.217.08:13:58.25$vc4f8/va=2,4 2006.217.08:13:58.25#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.217.08:13:58.25#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.217.08:13:58.25#ibcon#ireg 11 cls_cnt 2 2006.217.08:13:58.25#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.217.08:13:58.30#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.217.08:13:58.30#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.217.08:13:58.30#ibcon#enter wrdev, iclass 35, count 2 2006.217.08:13:58.30#ibcon#first serial, iclass 35, count 2 2006.217.08:13:58.30#ibcon#enter sib2, iclass 35, count 2 2006.217.08:13:58.30#ibcon#flushed, iclass 35, count 2 2006.217.08:13:58.30#ibcon#about to write, iclass 35, count 2 2006.217.08:13:58.30#ibcon#wrote, iclass 35, count 2 2006.217.08:13:58.30#ibcon#about to read 3, iclass 35, count 2 2006.217.08:13:58.32#ibcon#read 3, iclass 35, count 2 2006.217.08:13:58.32#ibcon#about to read 4, iclass 35, count 2 2006.217.08:13:58.32#ibcon#read 4, iclass 35, count 2 2006.217.08:13:58.32#ibcon#about to read 5, iclass 35, count 2 2006.217.08:13:58.32#ibcon#read 5, iclass 35, count 2 2006.217.08:13:58.32#ibcon#about to read 6, iclass 35, count 2 2006.217.08:13:58.32#ibcon#read 6, iclass 35, count 2 2006.217.08:13:58.32#ibcon#end of sib2, iclass 35, count 2 2006.217.08:13:58.32#ibcon#*mode == 0, iclass 35, count 2 2006.217.08:13:58.32#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.217.08:13:58.32#ibcon#[25=AT02-04\r\n] 2006.217.08:13:58.32#ibcon#*before write, iclass 35, count 2 2006.217.08:13:58.32#ibcon#enter sib2, iclass 35, count 2 2006.217.08:13:58.32#ibcon#flushed, iclass 35, count 2 2006.217.08:13:58.32#ibcon#about to write, iclass 35, count 2 2006.217.08:13:58.32#ibcon#wrote, iclass 35, count 2 2006.217.08:13:58.32#ibcon#about to read 3, iclass 35, count 2 2006.217.08:13:58.35#ibcon#read 3, iclass 35, count 2 2006.217.08:13:58.35#ibcon#about to read 4, iclass 35, count 2 2006.217.08:13:58.35#ibcon#read 4, iclass 35, count 2 2006.217.08:13:58.35#ibcon#about to read 5, iclass 35, count 2 2006.217.08:13:58.35#ibcon#read 5, iclass 35, count 2 2006.217.08:13:58.35#ibcon#about to read 6, iclass 35, count 2 2006.217.08:13:58.35#ibcon#read 6, iclass 35, count 2 2006.217.08:13:58.35#ibcon#end of sib2, iclass 35, count 2 2006.217.08:13:58.35#ibcon#*after write, iclass 35, count 2 2006.217.08:13:58.35#ibcon#*before return 0, iclass 35, count 2 2006.217.08:13:58.35#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.217.08:13:58.35#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.217.08:13:58.35#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.217.08:13:58.35#ibcon#ireg 7 cls_cnt 0 2006.217.08:13:58.35#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.217.08:13:58.47#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.217.08:13:58.47#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.217.08:13:58.47#ibcon#enter wrdev, iclass 35, count 0 2006.217.08:13:58.47#ibcon#first serial, iclass 35, count 0 2006.217.08:13:58.47#ibcon#enter sib2, iclass 35, count 0 2006.217.08:13:58.47#ibcon#flushed, iclass 35, count 0 2006.217.08:13:58.47#ibcon#about to write, iclass 35, count 0 2006.217.08:13:58.47#ibcon#wrote, iclass 35, count 0 2006.217.08:13:58.47#ibcon#about to read 3, iclass 35, count 0 2006.217.08:13:58.49#ibcon#read 3, iclass 35, count 0 2006.217.08:13:58.49#ibcon#about to read 4, iclass 35, count 0 2006.217.08:13:58.49#ibcon#read 4, iclass 35, count 0 2006.217.08:13:58.49#ibcon#about to read 5, iclass 35, count 0 2006.217.08:13:58.49#ibcon#read 5, iclass 35, count 0 2006.217.08:13:58.49#ibcon#about to read 6, iclass 35, count 0 2006.217.08:13:58.49#ibcon#read 6, iclass 35, count 0 2006.217.08:13:58.49#ibcon#end of sib2, iclass 35, count 0 2006.217.08:13:58.49#ibcon#*mode == 0, iclass 35, count 0 2006.217.08:13:58.49#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.217.08:13:58.49#ibcon#[25=USB\r\n] 2006.217.08:13:58.49#ibcon#*before write, iclass 35, count 0 2006.217.08:13:58.49#ibcon#enter sib2, iclass 35, count 0 2006.217.08:13:58.49#ibcon#flushed, iclass 35, count 0 2006.217.08:13:58.49#ibcon#about to write, iclass 35, count 0 2006.217.08:13:58.49#ibcon#wrote, iclass 35, count 0 2006.217.08:13:58.49#ibcon#about to read 3, iclass 35, count 0 2006.217.08:13:58.52#ibcon#read 3, iclass 35, count 0 2006.217.08:13:58.52#ibcon#about to read 4, iclass 35, count 0 2006.217.08:13:58.52#ibcon#read 4, iclass 35, count 0 2006.217.08:13:58.52#ibcon#about to read 5, iclass 35, count 0 2006.217.08:13:58.52#ibcon#read 5, iclass 35, count 0 2006.217.08:13:58.52#ibcon#about to read 6, iclass 35, count 0 2006.217.08:13:58.52#ibcon#read 6, iclass 35, count 0 2006.217.08:13:58.52#ibcon#end of sib2, iclass 35, count 0 2006.217.08:13:58.52#ibcon#*after write, iclass 35, count 0 2006.217.08:13:58.52#ibcon#*before return 0, iclass 35, count 0 2006.217.08:13:58.52#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.217.08:13:58.52#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.217.08:13:58.52#ibcon#about to clear, iclass 35 cls_cnt 0 2006.217.08:13:58.52#ibcon#cleared, iclass 35 cls_cnt 0 2006.217.08:13:58.52$vc4f8/valo=3,672.99 2006.217.08:13:58.52#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.217.08:13:58.52#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.217.08:13:58.52#ibcon#ireg 17 cls_cnt 0 2006.217.08:13:58.52#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.217.08:13:58.52#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.217.08:13:58.52#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.217.08:13:58.52#ibcon#enter wrdev, iclass 37, count 0 2006.217.08:13:58.52#ibcon#first serial, iclass 37, count 0 2006.217.08:13:58.52#ibcon#enter sib2, iclass 37, count 0 2006.217.08:13:58.52#ibcon#flushed, iclass 37, count 0 2006.217.08:13:58.52#ibcon#about to write, iclass 37, count 0 2006.217.08:13:58.52#ibcon#wrote, iclass 37, count 0 2006.217.08:13:58.52#ibcon#about to read 3, iclass 37, count 0 2006.217.08:13:58.54#ibcon#read 3, iclass 37, count 0 2006.217.08:13:58.54#ibcon#about to read 4, iclass 37, count 0 2006.217.08:13:58.54#ibcon#read 4, iclass 37, count 0 2006.217.08:13:58.54#ibcon#about to read 5, iclass 37, count 0 2006.217.08:13:58.54#ibcon#read 5, iclass 37, count 0 2006.217.08:13:58.54#ibcon#about to read 6, iclass 37, count 0 2006.217.08:13:58.54#ibcon#read 6, iclass 37, count 0 2006.217.08:13:58.54#ibcon#end of sib2, iclass 37, count 0 2006.217.08:13:58.54#ibcon#*mode == 0, iclass 37, count 0 2006.217.08:13:58.54#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.217.08:13:58.54#ibcon#[26=FRQ=03,672.99\r\n] 2006.217.08:13:58.54#ibcon#*before write, iclass 37, count 0 2006.217.08:13:58.54#ibcon#enter sib2, iclass 37, count 0 2006.217.08:13:58.54#ibcon#flushed, iclass 37, count 0 2006.217.08:13:58.54#ibcon#about to write, iclass 37, count 0 2006.217.08:13:58.54#ibcon#wrote, iclass 37, count 0 2006.217.08:13:58.54#ibcon#about to read 3, iclass 37, count 0 2006.217.08:13:58.59#ibcon#read 3, iclass 37, count 0 2006.217.08:13:58.59#ibcon#about to read 4, iclass 37, count 0 2006.217.08:13:58.59#ibcon#read 4, iclass 37, count 0 2006.217.08:13:58.59#ibcon#about to read 5, iclass 37, count 0 2006.217.08:13:58.59#ibcon#read 5, iclass 37, count 0 2006.217.08:13:58.59#ibcon#about to read 6, iclass 37, count 0 2006.217.08:13:58.59#ibcon#read 6, iclass 37, count 0 2006.217.08:13:58.59#ibcon#end of sib2, iclass 37, count 0 2006.217.08:13:58.59#ibcon#*after write, iclass 37, count 0 2006.217.08:13:58.59#ibcon#*before return 0, iclass 37, count 0 2006.217.08:13:58.59#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.217.08:13:58.59#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.217.08:13:58.59#ibcon#about to clear, iclass 37 cls_cnt 0 2006.217.08:13:58.59#ibcon#cleared, iclass 37 cls_cnt 0 2006.217.08:13:58.59$vc4f8/va=3,4 2006.217.08:13:58.59#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.217.08:13:58.59#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.217.08:13:58.59#ibcon#ireg 11 cls_cnt 2 2006.217.08:13:58.59#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.217.08:13:58.59#abcon#<5=/05 3.8 7.2 30.60 631008.6\r\n> 2006.217.08:13:58.61#abcon#{5=INTERFACE CLEAR} 2006.217.08:13:58.64#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.217.08:13:58.64#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.217.08:13:58.64#ibcon#enter wrdev, iclass 40, count 2 2006.217.08:13:58.64#ibcon#first serial, iclass 40, count 2 2006.217.08:13:58.64#ibcon#enter sib2, iclass 40, count 2 2006.217.08:13:58.64#ibcon#flushed, iclass 40, count 2 2006.217.08:13:58.64#ibcon#about to write, iclass 40, count 2 2006.217.08:13:58.64#ibcon#wrote, iclass 40, count 2 2006.217.08:13:58.64#ibcon#about to read 3, iclass 40, count 2 2006.217.08:13:58.66#ibcon#read 3, iclass 40, count 2 2006.217.08:13:58.66#ibcon#about to read 4, iclass 40, count 2 2006.217.08:13:58.66#ibcon#read 4, iclass 40, count 2 2006.217.08:13:58.66#ibcon#about to read 5, iclass 40, count 2 2006.217.08:13:58.66#ibcon#read 5, iclass 40, count 2 2006.217.08:13:58.66#ibcon#about to read 6, iclass 40, count 2 2006.217.08:13:58.66#ibcon#read 6, iclass 40, count 2 2006.217.08:13:58.66#ibcon#end of sib2, iclass 40, count 2 2006.217.08:13:58.66#ibcon#*mode == 0, iclass 40, count 2 2006.217.08:13:58.66#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.217.08:13:58.66#ibcon#[25=AT03-04\r\n] 2006.217.08:13:58.66#ibcon#*before write, iclass 40, count 2 2006.217.08:13:58.66#ibcon#enter sib2, iclass 40, count 2 2006.217.08:13:58.66#ibcon#flushed, iclass 40, count 2 2006.217.08:13:58.66#ibcon#about to write, iclass 40, count 2 2006.217.08:13:58.66#ibcon#wrote, iclass 40, count 2 2006.217.08:13:58.66#ibcon#about to read 3, iclass 40, count 2 2006.217.08:13:58.67#abcon#[5=S1D000X0/0*\r\n] 2006.217.08:13:58.69#ibcon#read 3, iclass 40, count 2 2006.217.08:13:58.69#ibcon#about to read 4, iclass 40, count 2 2006.217.08:13:58.69#ibcon#read 4, iclass 40, count 2 2006.217.08:13:58.69#ibcon#about to read 5, iclass 40, count 2 2006.217.08:13:58.69#ibcon#read 5, iclass 40, count 2 2006.217.08:13:58.69#ibcon#about to read 6, iclass 40, count 2 2006.217.08:13:58.69#ibcon#read 6, iclass 40, count 2 2006.217.08:13:58.69#ibcon#end of sib2, iclass 40, count 2 2006.217.08:13:58.69#ibcon#*after write, iclass 40, count 2 2006.217.08:13:58.69#ibcon#*before return 0, iclass 40, count 2 2006.217.08:13:58.69#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.217.08:13:58.69#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.217.08:13:58.69#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.217.08:13:58.69#ibcon#ireg 7 cls_cnt 0 2006.217.08:13:58.69#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.217.08:13:58.81#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.217.08:13:58.81#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.217.08:13:58.81#ibcon#enter wrdev, iclass 40, count 0 2006.217.08:13:58.81#ibcon#first serial, iclass 40, count 0 2006.217.08:13:58.81#ibcon#enter sib2, iclass 40, count 0 2006.217.08:13:58.81#ibcon#flushed, iclass 40, count 0 2006.217.08:13:58.81#ibcon#about to write, iclass 40, count 0 2006.217.08:13:58.81#ibcon#wrote, iclass 40, count 0 2006.217.08:13:58.81#ibcon#about to read 3, iclass 40, count 0 2006.217.08:13:58.83#ibcon#read 3, iclass 40, count 0 2006.217.08:13:58.83#ibcon#about to read 4, iclass 40, count 0 2006.217.08:13:58.83#ibcon#read 4, iclass 40, count 0 2006.217.08:13:58.83#ibcon#about to read 5, iclass 40, count 0 2006.217.08:13:58.83#ibcon#read 5, iclass 40, count 0 2006.217.08:13:58.83#ibcon#about to read 6, iclass 40, count 0 2006.217.08:13:58.83#ibcon#read 6, iclass 40, count 0 2006.217.08:13:58.83#ibcon#end of sib2, iclass 40, count 0 2006.217.08:13:58.83#ibcon#*mode == 0, iclass 40, count 0 2006.217.08:13:58.83#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.217.08:13:58.83#ibcon#[25=USB\r\n] 2006.217.08:13:58.83#ibcon#*before write, iclass 40, count 0 2006.217.08:13:58.83#ibcon#enter sib2, iclass 40, count 0 2006.217.08:13:58.83#ibcon#flushed, iclass 40, count 0 2006.217.08:13:58.83#ibcon#about to write, iclass 40, count 0 2006.217.08:13:58.83#ibcon#wrote, iclass 40, count 0 2006.217.08:13:58.83#ibcon#about to read 3, iclass 40, count 0 2006.217.08:13:58.86#ibcon#read 3, iclass 40, count 0 2006.217.08:13:58.86#ibcon#about to read 4, iclass 40, count 0 2006.217.08:13:58.86#ibcon#read 4, iclass 40, count 0 2006.217.08:13:58.86#ibcon#about to read 5, iclass 40, count 0 2006.217.08:13:58.86#ibcon#read 5, iclass 40, count 0 2006.217.08:13:58.86#ibcon#about to read 6, iclass 40, count 0 2006.217.08:13:58.86#ibcon#read 6, iclass 40, count 0 2006.217.08:13:58.86#ibcon#end of sib2, iclass 40, count 0 2006.217.08:13:58.86#ibcon#*after write, iclass 40, count 0 2006.217.08:13:58.86#ibcon#*before return 0, iclass 40, count 0 2006.217.08:13:58.86#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.217.08:13:58.86#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.217.08:13:58.86#ibcon#about to clear, iclass 40 cls_cnt 0 2006.217.08:13:58.86#ibcon#cleared, iclass 40 cls_cnt 0 2006.217.08:13:58.86$vc4f8/valo=4,832.99 2006.217.08:13:58.86#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.217.08:13:58.86#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.217.08:13:58.86#ibcon#ireg 17 cls_cnt 0 2006.217.08:13:58.86#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.217.08:13:58.86#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.217.08:13:58.86#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.217.08:13:58.86#ibcon#enter wrdev, iclass 7, count 0 2006.217.08:13:58.86#ibcon#first serial, iclass 7, count 0 2006.217.08:13:58.86#ibcon#enter sib2, iclass 7, count 0 2006.217.08:13:58.86#ibcon#flushed, iclass 7, count 0 2006.217.08:13:58.86#ibcon#about to write, iclass 7, count 0 2006.217.08:13:58.86#ibcon#wrote, iclass 7, count 0 2006.217.08:13:58.86#ibcon#about to read 3, iclass 7, count 0 2006.217.08:13:58.88#ibcon#read 3, iclass 7, count 0 2006.217.08:13:58.88#ibcon#about to read 4, iclass 7, count 0 2006.217.08:13:58.88#ibcon#read 4, iclass 7, count 0 2006.217.08:13:58.88#ibcon#about to read 5, iclass 7, count 0 2006.217.08:13:58.88#ibcon#read 5, iclass 7, count 0 2006.217.08:13:58.88#ibcon#about to read 6, iclass 7, count 0 2006.217.08:13:58.88#ibcon#read 6, iclass 7, count 0 2006.217.08:13:58.88#ibcon#end of sib2, iclass 7, count 0 2006.217.08:13:58.88#ibcon#*mode == 0, iclass 7, count 0 2006.217.08:13:58.88#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.217.08:13:58.88#ibcon#[26=FRQ=04,832.99\r\n] 2006.217.08:13:58.88#ibcon#*before write, iclass 7, count 0 2006.217.08:13:58.88#ibcon#enter sib2, iclass 7, count 0 2006.217.08:13:58.88#ibcon#flushed, iclass 7, count 0 2006.217.08:13:58.88#ibcon#about to write, iclass 7, count 0 2006.217.08:13:58.88#ibcon#wrote, iclass 7, count 0 2006.217.08:13:58.88#ibcon#about to read 3, iclass 7, count 0 2006.217.08:13:58.93#ibcon#read 3, iclass 7, count 0 2006.217.08:13:58.93#ibcon#about to read 4, iclass 7, count 0 2006.217.08:13:58.93#ibcon#read 4, iclass 7, count 0 2006.217.08:13:58.93#ibcon#about to read 5, iclass 7, count 0 2006.217.08:13:58.93#ibcon#read 5, iclass 7, count 0 2006.217.08:13:58.93#ibcon#about to read 6, iclass 7, count 0 2006.217.08:13:58.93#ibcon#read 6, iclass 7, count 0 2006.217.08:13:58.93#ibcon#end of sib2, iclass 7, count 0 2006.217.08:13:58.93#ibcon#*after write, iclass 7, count 0 2006.217.08:13:58.93#ibcon#*before return 0, iclass 7, count 0 2006.217.08:13:58.93#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.217.08:13:58.93#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.217.08:13:58.93#ibcon#about to clear, iclass 7 cls_cnt 0 2006.217.08:13:58.93#ibcon#cleared, iclass 7 cls_cnt 0 2006.217.08:13:58.93$vc4f8/va=4,4 2006.217.08:13:58.93#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.217.08:13:58.93#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.217.08:13:58.93#ibcon#ireg 11 cls_cnt 2 2006.217.08:13:58.93#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.217.08:13:58.98#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.217.08:13:58.98#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.217.08:13:58.98#ibcon#enter wrdev, iclass 11, count 2 2006.217.08:13:58.98#ibcon#first serial, iclass 11, count 2 2006.217.08:13:58.98#ibcon#enter sib2, iclass 11, count 2 2006.217.08:13:58.98#ibcon#flushed, iclass 11, count 2 2006.217.08:13:58.98#ibcon#about to write, iclass 11, count 2 2006.217.08:13:58.98#ibcon#wrote, iclass 11, count 2 2006.217.08:13:58.98#ibcon#about to read 3, iclass 11, count 2 2006.217.08:13:59.00#ibcon#read 3, iclass 11, count 2 2006.217.08:13:59.00#ibcon#about to read 4, iclass 11, count 2 2006.217.08:13:59.00#ibcon#read 4, iclass 11, count 2 2006.217.08:13:59.00#ibcon#about to read 5, iclass 11, count 2 2006.217.08:13:59.00#ibcon#read 5, iclass 11, count 2 2006.217.08:13:59.00#ibcon#about to read 6, iclass 11, count 2 2006.217.08:13:59.00#ibcon#read 6, iclass 11, count 2 2006.217.08:13:59.00#ibcon#end of sib2, iclass 11, count 2 2006.217.08:13:59.00#ibcon#*mode == 0, iclass 11, count 2 2006.217.08:13:59.00#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.217.08:13:59.00#ibcon#[25=AT04-04\r\n] 2006.217.08:13:59.00#ibcon#*before write, iclass 11, count 2 2006.217.08:13:59.00#ibcon#enter sib2, iclass 11, count 2 2006.217.08:13:59.00#ibcon#flushed, iclass 11, count 2 2006.217.08:13:59.00#ibcon#about to write, iclass 11, count 2 2006.217.08:13:59.00#ibcon#wrote, iclass 11, count 2 2006.217.08:13:59.00#ibcon#about to read 3, iclass 11, count 2 2006.217.08:13:59.03#ibcon#read 3, iclass 11, count 2 2006.217.08:13:59.03#ibcon#about to read 4, iclass 11, count 2 2006.217.08:13:59.03#ibcon#read 4, iclass 11, count 2 2006.217.08:13:59.03#ibcon#about to read 5, iclass 11, count 2 2006.217.08:13:59.03#ibcon#read 5, iclass 11, count 2 2006.217.08:13:59.03#ibcon#about to read 6, iclass 11, count 2 2006.217.08:13:59.03#ibcon#read 6, iclass 11, count 2 2006.217.08:13:59.03#ibcon#end of sib2, iclass 11, count 2 2006.217.08:13:59.03#ibcon#*after write, iclass 11, count 2 2006.217.08:13:59.03#ibcon#*before return 0, iclass 11, count 2 2006.217.08:13:59.03#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.217.08:13:59.03#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.217.08:13:59.03#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.217.08:13:59.03#ibcon#ireg 7 cls_cnt 0 2006.217.08:13:59.03#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.217.08:13:59.15#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.217.08:13:59.15#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.217.08:13:59.15#ibcon#enter wrdev, iclass 11, count 0 2006.217.08:13:59.15#ibcon#first serial, iclass 11, count 0 2006.217.08:13:59.15#ibcon#enter sib2, iclass 11, count 0 2006.217.08:13:59.15#ibcon#flushed, iclass 11, count 0 2006.217.08:13:59.15#ibcon#about to write, iclass 11, count 0 2006.217.08:13:59.15#ibcon#wrote, iclass 11, count 0 2006.217.08:13:59.15#ibcon#about to read 3, iclass 11, count 0 2006.217.08:13:59.17#ibcon#read 3, iclass 11, count 0 2006.217.08:13:59.17#ibcon#about to read 4, iclass 11, count 0 2006.217.08:13:59.17#ibcon#read 4, iclass 11, count 0 2006.217.08:13:59.17#ibcon#about to read 5, iclass 11, count 0 2006.217.08:13:59.17#ibcon#read 5, iclass 11, count 0 2006.217.08:13:59.17#ibcon#about to read 6, iclass 11, count 0 2006.217.08:13:59.17#ibcon#read 6, iclass 11, count 0 2006.217.08:13:59.17#ibcon#end of sib2, iclass 11, count 0 2006.217.08:13:59.17#ibcon#*mode == 0, iclass 11, count 0 2006.217.08:13:59.17#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.217.08:13:59.17#ibcon#[25=USB\r\n] 2006.217.08:13:59.17#ibcon#*before write, iclass 11, count 0 2006.217.08:13:59.17#ibcon#enter sib2, iclass 11, count 0 2006.217.08:13:59.17#ibcon#flushed, iclass 11, count 0 2006.217.08:13:59.17#ibcon#about to write, iclass 11, count 0 2006.217.08:13:59.17#ibcon#wrote, iclass 11, count 0 2006.217.08:13:59.17#ibcon#about to read 3, iclass 11, count 0 2006.217.08:13:59.20#ibcon#read 3, iclass 11, count 0 2006.217.08:13:59.20#ibcon#about to read 4, iclass 11, count 0 2006.217.08:13:59.20#ibcon#read 4, iclass 11, count 0 2006.217.08:13:59.20#ibcon#about to read 5, iclass 11, count 0 2006.217.08:13:59.20#ibcon#read 5, iclass 11, count 0 2006.217.08:13:59.20#ibcon#about to read 6, iclass 11, count 0 2006.217.08:13:59.20#ibcon#read 6, iclass 11, count 0 2006.217.08:13:59.20#ibcon#end of sib2, iclass 11, count 0 2006.217.08:13:59.20#ibcon#*after write, iclass 11, count 0 2006.217.08:13:59.20#ibcon#*before return 0, iclass 11, count 0 2006.217.08:13:59.20#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.217.08:13:59.20#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.217.08:13:59.20#ibcon#about to clear, iclass 11 cls_cnt 0 2006.217.08:13:59.20#ibcon#cleared, iclass 11 cls_cnt 0 2006.217.08:13:59.20$vc4f8/valo=5,652.99 2006.217.08:13:59.20#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.217.08:13:59.20#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.217.08:13:59.20#ibcon#ireg 17 cls_cnt 0 2006.217.08:13:59.20#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.217.08:13:59.20#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.217.08:13:59.20#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.217.08:13:59.20#ibcon#enter wrdev, iclass 13, count 0 2006.217.08:13:59.20#ibcon#first serial, iclass 13, count 0 2006.217.08:13:59.20#ibcon#enter sib2, iclass 13, count 0 2006.217.08:13:59.20#ibcon#flushed, iclass 13, count 0 2006.217.08:13:59.20#ibcon#about to write, iclass 13, count 0 2006.217.08:13:59.20#ibcon#wrote, iclass 13, count 0 2006.217.08:13:59.20#ibcon#about to read 3, iclass 13, count 0 2006.217.08:13:59.22#ibcon#read 3, iclass 13, count 0 2006.217.08:13:59.22#ibcon#about to read 4, iclass 13, count 0 2006.217.08:13:59.22#ibcon#read 4, iclass 13, count 0 2006.217.08:13:59.22#ibcon#about to read 5, iclass 13, count 0 2006.217.08:13:59.22#ibcon#read 5, iclass 13, count 0 2006.217.08:13:59.22#ibcon#about to read 6, iclass 13, count 0 2006.217.08:13:59.22#ibcon#read 6, iclass 13, count 0 2006.217.08:13:59.22#ibcon#end of sib2, iclass 13, count 0 2006.217.08:13:59.22#ibcon#*mode == 0, iclass 13, count 0 2006.217.08:13:59.22#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.217.08:13:59.22#ibcon#[26=FRQ=05,652.99\r\n] 2006.217.08:13:59.22#ibcon#*before write, iclass 13, count 0 2006.217.08:13:59.22#ibcon#enter sib2, iclass 13, count 0 2006.217.08:13:59.22#ibcon#flushed, iclass 13, count 0 2006.217.08:13:59.22#ibcon#about to write, iclass 13, count 0 2006.217.08:13:59.22#ibcon#wrote, iclass 13, count 0 2006.217.08:13:59.22#ibcon#about to read 3, iclass 13, count 0 2006.217.08:13:59.26#ibcon#read 3, iclass 13, count 0 2006.217.08:13:59.26#ibcon#about to read 4, iclass 13, count 0 2006.217.08:13:59.26#ibcon#read 4, iclass 13, count 0 2006.217.08:13:59.26#ibcon#about to read 5, iclass 13, count 0 2006.217.08:13:59.26#ibcon#read 5, iclass 13, count 0 2006.217.08:13:59.26#ibcon#about to read 6, iclass 13, count 0 2006.217.08:13:59.26#ibcon#read 6, iclass 13, count 0 2006.217.08:13:59.26#ibcon#end of sib2, iclass 13, count 0 2006.217.08:13:59.26#ibcon#*after write, iclass 13, count 0 2006.217.08:13:59.26#ibcon#*before return 0, iclass 13, count 0 2006.217.08:13:59.26#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.217.08:13:59.26#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.217.08:13:59.26#ibcon#about to clear, iclass 13 cls_cnt 0 2006.217.08:13:59.26#ibcon#cleared, iclass 13 cls_cnt 0 2006.217.08:13:59.26$vc4f8/va=5,7 2006.217.08:13:59.26#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.217.08:13:59.26#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.217.08:13:59.26#ibcon#ireg 11 cls_cnt 2 2006.217.08:13:59.26#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.217.08:13:59.32#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.217.08:13:59.32#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.217.08:13:59.32#ibcon#enter wrdev, iclass 15, count 2 2006.217.08:13:59.32#ibcon#first serial, iclass 15, count 2 2006.217.08:13:59.32#ibcon#enter sib2, iclass 15, count 2 2006.217.08:13:59.32#ibcon#flushed, iclass 15, count 2 2006.217.08:13:59.32#ibcon#about to write, iclass 15, count 2 2006.217.08:13:59.32#ibcon#wrote, iclass 15, count 2 2006.217.08:13:59.32#ibcon#about to read 3, iclass 15, count 2 2006.217.08:13:59.34#ibcon#read 3, iclass 15, count 2 2006.217.08:13:59.34#ibcon#about to read 4, iclass 15, count 2 2006.217.08:13:59.34#ibcon#read 4, iclass 15, count 2 2006.217.08:13:59.34#ibcon#about to read 5, iclass 15, count 2 2006.217.08:13:59.34#ibcon#read 5, iclass 15, count 2 2006.217.08:13:59.34#ibcon#about to read 6, iclass 15, count 2 2006.217.08:13:59.34#ibcon#read 6, iclass 15, count 2 2006.217.08:13:59.34#ibcon#end of sib2, iclass 15, count 2 2006.217.08:13:59.34#ibcon#*mode == 0, iclass 15, count 2 2006.217.08:13:59.34#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.217.08:13:59.34#ibcon#[25=AT05-07\r\n] 2006.217.08:13:59.34#ibcon#*before write, iclass 15, count 2 2006.217.08:13:59.34#ibcon#enter sib2, iclass 15, count 2 2006.217.08:13:59.34#ibcon#flushed, iclass 15, count 2 2006.217.08:13:59.34#ibcon#about to write, iclass 15, count 2 2006.217.08:13:59.34#ibcon#wrote, iclass 15, count 2 2006.217.08:13:59.34#ibcon#about to read 3, iclass 15, count 2 2006.217.08:13:59.37#ibcon#read 3, iclass 15, count 2 2006.217.08:13:59.37#ibcon#about to read 4, iclass 15, count 2 2006.217.08:13:59.37#ibcon#read 4, iclass 15, count 2 2006.217.08:13:59.37#ibcon#about to read 5, iclass 15, count 2 2006.217.08:13:59.37#ibcon#read 5, iclass 15, count 2 2006.217.08:13:59.37#ibcon#about to read 6, iclass 15, count 2 2006.217.08:13:59.37#ibcon#read 6, iclass 15, count 2 2006.217.08:13:59.37#ibcon#end of sib2, iclass 15, count 2 2006.217.08:13:59.37#ibcon#*after write, iclass 15, count 2 2006.217.08:13:59.37#ibcon#*before return 0, iclass 15, count 2 2006.217.08:13:59.37#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.217.08:13:59.37#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.217.08:13:59.37#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.217.08:13:59.37#ibcon#ireg 7 cls_cnt 0 2006.217.08:13:59.37#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.217.08:13:59.49#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.217.08:13:59.49#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.217.08:13:59.49#ibcon#enter wrdev, iclass 15, count 0 2006.217.08:13:59.49#ibcon#first serial, iclass 15, count 0 2006.217.08:13:59.49#ibcon#enter sib2, iclass 15, count 0 2006.217.08:13:59.49#ibcon#flushed, iclass 15, count 0 2006.217.08:13:59.49#ibcon#about to write, iclass 15, count 0 2006.217.08:13:59.49#ibcon#wrote, iclass 15, count 0 2006.217.08:13:59.49#ibcon#about to read 3, iclass 15, count 0 2006.217.08:13:59.51#ibcon#read 3, iclass 15, count 0 2006.217.08:13:59.51#ibcon#about to read 4, iclass 15, count 0 2006.217.08:13:59.51#ibcon#read 4, iclass 15, count 0 2006.217.08:13:59.51#ibcon#about to read 5, iclass 15, count 0 2006.217.08:13:59.51#ibcon#read 5, iclass 15, count 0 2006.217.08:13:59.51#ibcon#about to read 6, iclass 15, count 0 2006.217.08:13:59.51#ibcon#read 6, iclass 15, count 0 2006.217.08:13:59.51#ibcon#end of sib2, iclass 15, count 0 2006.217.08:13:59.51#ibcon#*mode == 0, iclass 15, count 0 2006.217.08:13:59.51#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.217.08:13:59.51#ibcon#[25=USB\r\n] 2006.217.08:13:59.51#ibcon#*before write, iclass 15, count 0 2006.217.08:13:59.51#ibcon#enter sib2, iclass 15, count 0 2006.217.08:13:59.51#ibcon#flushed, iclass 15, count 0 2006.217.08:13:59.51#ibcon#about to write, iclass 15, count 0 2006.217.08:13:59.51#ibcon#wrote, iclass 15, count 0 2006.217.08:13:59.51#ibcon#about to read 3, iclass 15, count 0 2006.217.08:13:59.54#ibcon#read 3, iclass 15, count 0 2006.217.08:13:59.54#ibcon#about to read 4, iclass 15, count 0 2006.217.08:13:59.54#ibcon#read 4, iclass 15, count 0 2006.217.08:13:59.54#ibcon#about to read 5, iclass 15, count 0 2006.217.08:13:59.54#ibcon#read 5, iclass 15, count 0 2006.217.08:13:59.54#ibcon#about to read 6, iclass 15, count 0 2006.217.08:13:59.54#ibcon#read 6, iclass 15, count 0 2006.217.08:13:59.54#ibcon#end of sib2, iclass 15, count 0 2006.217.08:13:59.54#ibcon#*after write, iclass 15, count 0 2006.217.08:13:59.54#ibcon#*before return 0, iclass 15, count 0 2006.217.08:13:59.54#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.217.08:13:59.54#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.217.08:13:59.54#ibcon#about to clear, iclass 15 cls_cnt 0 2006.217.08:13:59.54#ibcon#cleared, iclass 15 cls_cnt 0 2006.217.08:13:59.54$vc4f8/valo=6,772.99 2006.217.08:13:59.54#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.217.08:13:59.54#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.217.08:13:59.54#ibcon#ireg 17 cls_cnt 0 2006.217.08:13:59.54#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.217.08:13:59.54#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.217.08:13:59.54#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.217.08:13:59.54#ibcon#enter wrdev, iclass 17, count 0 2006.217.08:13:59.54#ibcon#first serial, iclass 17, count 0 2006.217.08:13:59.54#ibcon#enter sib2, iclass 17, count 0 2006.217.08:13:59.54#ibcon#flushed, iclass 17, count 0 2006.217.08:13:59.54#ibcon#about to write, iclass 17, count 0 2006.217.08:13:59.54#ibcon#wrote, iclass 17, count 0 2006.217.08:13:59.54#ibcon#about to read 3, iclass 17, count 0 2006.217.08:13:59.56#ibcon#read 3, iclass 17, count 0 2006.217.08:13:59.56#ibcon#about to read 4, iclass 17, count 0 2006.217.08:13:59.56#ibcon#read 4, iclass 17, count 0 2006.217.08:13:59.56#ibcon#about to read 5, iclass 17, count 0 2006.217.08:13:59.56#ibcon#read 5, iclass 17, count 0 2006.217.08:13:59.56#ibcon#about to read 6, iclass 17, count 0 2006.217.08:13:59.56#ibcon#read 6, iclass 17, count 0 2006.217.08:13:59.56#ibcon#end of sib2, iclass 17, count 0 2006.217.08:13:59.56#ibcon#*mode == 0, iclass 17, count 0 2006.217.08:13:59.56#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.217.08:13:59.56#ibcon#[26=FRQ=06,772.99\r\n] 2006.217.08:13:59.56#ibcon#*before write, iclass 17, count 0 2006.217.08:13:59.56#ibcon#enter sib2, iclass 17, count 0 2006.217.08:13:59.56#ibcon#flushed, iclass 17, count 0 2006.217.08:13:59.56#ibcon#about to write, iclass 17, count 0 2006.217.08:13:59.56#ibcon#wrote, iclass 17, count 0 2006.217.08:13:59.56#ibcon#about to read 3, iclass 17, count 0 2006.217.08:13:59.60#ibcon#read 3, iclass 17, count 0 2006.217.08:13:59.60#ibcon#about to read 4, iclass 17, count 0 2006.217.08:13:59.60#ibcon#read 4, iclass 17, count 0 2006.217.08:13:59.60#ibcon#about to read 5, iclass 17, count 0 2006.217.08:13:59.60#ibcon#read 5, iclass 17, count 0 2006.217.08:13:59.60#ibcon#about to read 6, iclass 17, count 0 2006.217.08:13:59.60#ibcon#read 6, iclass 17, count 0 2006.217.08:13:59.60#ibcon#end of sib2, iclass 17, count 0 2006.217.08:13:59.60#ibcon#*after write, iclass 17, count 0 2006.217.08:13:59.60#ibcon#*before return 0, iclass 17, count 0 2006.217.08:13:59.60#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.217.08:13:59.60#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.217.08:13:59.60#ibcon#about to clear, iclass 17 cls_cnt 0 2006.217.08:13:59.60#ibcon#cleared, iclass 17 cls_cnt 0 2006.217.08:13:59.60$vc4f8/va=6,6 2006.217.08:13:59.60#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.217.08:13:59.60#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.217.08:13:59.60#ibcon#ireg 11 cls_cnt 2 2006.217.08:13:59.60#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.217.08:13:59.66#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.217.08:13:59.66#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.217.08:13:59.66#ibcon#enter wrdev, iclass 19, count 2 2006.217.08:13:59.66#ibcon#first serial, iclass 19, count 2 2006.217.08:13:59.66#ibcon#enter sib2, iclass 19, count 2 2006.217.08:13:59.66#ibcon#flushed, iclass 19, count 2 2006.217.08:13:59.66#ibcon#about to write, iclass 19, count 2 2006.217.08:13:59.66#ibcon#wrote, iclass 19, count 2 2006.217.08:13:59.66#ibcon#about to read 3, iclass 19, count 2 2006.217.08:13:59.68#ibcon#read 3, iclass 19, count 2 2006.217.08:13:59.68#ibcon#about to read 4, iclass 19, count 2 2006.217.08:13:59.68#ibcon#read 4, iclass 19, count 2 2006.217.08:13:59.68#ibcon#about to read 5, iclass 19, count 2 2006.217.08:13:59.68#ibcon#read 5, iclass 19, count 2 2006.217.08:13:59.68#ibcon#about to read 6, iclass 19, count 2 2006.217.08:13:59.68#ibcon#read 6, iclass 19, count 2 2006.217.08:13:59.68#ibcon#end of sib2, iclass 19, count 2 2006.217.08:13:59.68#ibcon#*mode == 0, iclass 19, count 2 2006.217.08:13:59.68#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.217.08:13:59.68#ibcon#[25=AT06-06\r\n] 2006.217.08:13:59.68#ibcon#*before write, iclass 19, count 2 2006.217.08:13:59.68#ibcon#enter sib2, iclass 19, count 2 2006.217.08:13:59.68#ibcon#flushed, iclass 19, count 2 2006.217.08:13:59.68#ibcon#about to write, iclass 19, count 2 2006.217.08:13:59.68#ibcon#wrote, iclass 19, count 2 2006.217.08:13:59.68#ibcon#about to read 3, iclass 19, count 2 2006.217.08:13:59.71#ibcon#read 3, iclass 19, count 2 2006.217.08:13:59.71#ibcon#about to read 4, iclass 19, count 2 2006.217.08:13:59.71#ibcon#read 4, iclass 19, count 2 2006.217.08:13:59.71#ibcon#about to read 5, iclass 19, count 2 2006.217.08:13:59.71#ibcon#read 5, iclass 19, count 2 2006.217.08:13:59.71#ibcon#about to read 6, iclass 19, count 2 2006.217.08:13:59.71#ibcon#read 6, iclass 19, count 2 2006.217.08:13:59.71#ibcon#end of sib2, iclass 19, count 2 2006.217.08:13:59.71#ibcon#*after write, iclass 19, count 2 2006.217.08:13:59.71#ibcon#*before return 0, iclass 19, count 2 2006.217.08:13:59.71#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.217.08:13:59.71#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.217.08:13:59.71#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.217.08:13:59.71#ibcon#ireg 7 cls_cnt 0 2006.217.08:13:59.71#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.217.08:13:59.83#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.217.08:13:59.83#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.217.08:13:59.83#ibcon#enter wrdev, iclass 19, count 0 2006.217.08:13:59.83#ibcon#first serial, iclass 19, count 0 2006.217.08:13:59.83#ibcon#enter sib2, iclass 19, count 0 2006.217.08:13:59.83#ibcon#flushed, iclass 19, count 0 2006.217.08:13:59.83#ibcon#about to write, iclass 19, count 0 2006.217.08:13:59.83#ibcon#wrote, iclass 19, count 0 2006.217.08:13:59.83#ibcon#about to read 3, iclass 19, count 0 2006.217.08:13:59.85#ibcon#read 3, iclass 19, count 0 2006.217.08:13:59.85#ibcon#about to read 4, iclass 19, count 0 2006.217.08:13:59.85#ibcon#read 4, iclass 19, count 0 2006.217.08:13:59.85#ibcon#about to read 5, iclass 19, count 0 2006.217.08:13:59.85#ibcon#read 5, iclass 19, count 0 2006.217.08:13:59.85#ibcon#about to read 6, iclass 19, count 0 2006.217.08:13:59.85#ibcon#read 6, iclass 19, count 0 2006.217.08:13:59.85#ibcon#end of sib2, iclass 19, count 0 2006.217.08:13:59.85#ibcon#*mode == 0, iclass 19, count 0 2006.217.08:13:59.85#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.217.08:13:59.85#ibcon#[25=USB\r\n] 2006.217.08:13:59.85#ibcon#*before write, iclass 19, count 0 2006.217.08:13:59.85#ibcon#enter sib2, iclass 19, count 0 2006.217.08:13:59.85#ibcon#flushed, iclass 19, count 0 2006.217.08:13:59.85#ibcon#about to write, iclass 19, count 0 2006.217.08:13:59.85#ibcon#wrote, iclass 19, count 0 2006.217.08:13:59.85#ibcon#about to read 3, iclass 19, count 0 2006.217.08:13:59.88#ibcon#read 3, iclass 19, count 0 2006.217.08:13:59.88#ibcon#about to read 4, iclass 19, count 0 2006.217.08:13:59.88#ibcon#read 4, iclass 19, count 0 2006.217.08:13:59.88#ibcon#about to read 5, iclass 19, count 0 2006.217.08:13:59.88#ibcon#read 5, iclass 19, count 0 2006.217.08:13:59.88#ibcon#about to read 6, iclass 19, count 0 2006.217.08:13:59.88#ibcon#read 6, iclass 19, count 0 2006.217.08:13:59.88#ibcon#end of sib2, iclass 19, count 0 2006.217.08:13:59.88#ibcon#*after write, iclass 19, count 0 2006.217.08:13:59.88#ibcon#*before return 0, iclass 19, count 0 2006.217.08:13:59.88#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.217.08:13:59.88#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.217.08:13:59.88#ibcon#about to clear, iclass 19 cls_cnt 0 2006.217.08:13:59.88#ibcon#cleared, iclass 19 cls_cnt 0 2006.217.08:13:59.88$vc4f8/valo=7,832.99 2006.217.08:13:59.88#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.217.08:13:59.88#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.217.08:13:59.88#ibcon#ireg 17 cls_cnt 0 2006.217.08:13:59.88#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.217.08:13:59.88#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.217.08:13:59.88#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.217.08:13:59.88#ibcon#enter wrdev, iclass 21, count 0 2006.217.08:13:59.88#ibcon#first serial, iclass 21, count 0 2006.217.08:13:59.88#ibcon#enter sib2, iclass 21, count 0 2006.217.08:13:59.88#ibcon#flushed, iclass 21, count 0 2006.217.08:13:59.88#ibcon#about to write, iclass 21, count 0 2006.217.08:13:59.88#ibcon#wrote, iclass 21, count 0 2006.217.08:13:59.88#ibcon#about to read 3, iclass 21, count 0 2006.217.08:13:59.90#ibcon#read 3, iclass 21, count 0 2006.217.08:13:59.90#ibcon#about to read 4, iclass 21, count 0 2006.217.08:13:59.90#ibcon#read 4, iclass 21, count 0 2006.217.08:13:59.90#ibcon#about to read 5, iclass 21, count 0 2006.217.08:13:59.90#ibcon#read 5, iclass 21, count 0 2006.217.08:13:59.90#ibcon#about to read 6, iclass 21, count 0 2006.217.08:13:59.90#ibcon#read 6, iclass 21, count 0 2006.217.08:13:59.90#ibcon#end of sib2, iclass 21, count 0 2006.217.08:13:59.90#ibcon#*mode == 0, iclass 21, count 0 2006.217.08:13:59.90#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.217.08:13:59.90#ibcon#[26=FRQ=07,832.99\r\n] 2006.217.08:13:59.90#ibcon#*before write, iclass 21, count 0 2006.217.08:13:59.90#ibcon#enter sib2, iclass 21, count 0 2006.217.08:13:59.90#ibcon#flushed, iclass 21, count 0 2006.217.08:13:59.90#ibcon#about to write, iclass 21, count 0 2006.217.08:13:59.90#ibcon#wrote, iclass 21, count 0 2006.217.08:13:59.90#ibcon#about to read 3, iclass 21, count 0 2006.217.08:13:59.94#ibcon#read 3, iclass 21, count 0 2006.217.08:13:59.94#ibcon#about to read 4, iclass 21, count 0 2006.217.08:13:59.94#ibcon#read 4, iclass 21, count 0 2006.217.08:13:59.94#ibcon#about to read 5, iclass 21, count 0 2006.217.08:13:59.94#ibcon#read 5, iclass 21, count 0 2006.217.08:13:59.94#ibcon#about to read 6, iclass 21, count 0 2006.217.08:13:59.94#ibcon#read 6, iclass 21, count 0 2006.217.08:13:59.94#ibcon#end of sib2, iclass 21, count 0 2006.217.08:13:59.94#ibcon#*after write, iclass 21, count 0 2006.217.08:13:59.94#ibcon#*before return 0, iclass 21, count 0 2006.217.08:13:59.94#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.217.08:13:59.94#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.217.08:13:59.94#ibcon#about to clear, iclass 21 cls_cnt 0 2006.217.08:13:59.94#ibcon#cleared, iclass 21 cls_cnt 0 2006.217.08:13:59.94$vc4f8/va=7,6 2006.217.08:13:59.94#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.217.08:13:59.94#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.217.08:13:59.94#ibcon#ireg 11 cls_cnt 2 2006.217.08:13:59.94#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.217.08:14:00.00#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.217.08:14:00.00#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.217.08:14:00.00#ibcon#enter wrdev, iclass 23, count 2 2006.217.08:14:00.00#ibcon#first serial, iclass 23, count 2 2006.217.08:14:00.00#ibcon#enter sib2, iclass 23, count 2 2006.217.08:14:00.00#ibcon#flushed, iclass 23, count 2 2006.217.08:14:00.00#ibcon#about to write, iclass 23, count 2 2006.217.08:14:00.00#ibcon#wrote, iclass 23, count 2 2006.217.08:14:00.00#ibcon#about to read 3, iclass 23, count 2 2006.217.08:14:00.02#ibcon#read 3, iclass 23, count 2 2006.217.08:14:00.02#ibcon#about to read 4, iclass 23, count 2 2006.217.08:14:00.02#ibcon#read 4, iclass 23, count 2 2006.217.08:14:00.02#ibcon#about to read 5, iclass 23, count 2 2006.217.08:14:00.02#ibcon#read 5, iclass 23, count 2 2006.217.08:14:00.02#ibcon#about to read 6, iclass 23, count 2 2006.217.08:14:00.02#ibcon#read 6, iclass 23, count 2 2006.217.08:14:00.02#ibcon#end of sib2, iclass 23, count 2 2006.217.08:14:00.02#ibcon#*mode == 0, iclass 23, count 2 2006.217.08:14:00.02#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.217.08:14:00.02#ibcon#[25=AT07-06\r\n] 2006.217.08:14:00.02#ibcon#*before write, iclass 23, count 2 2006.217.08:14:00.02#ibcon#enter sib2, iclass 23, count 2 2006.217.08:14:00.02#ibcon#flushed, iclass 23, count 2 2006.217.08:14:00.02#ibcon#about to write, iclass 23, count 2 2006.217.08:14:00.02#ibcon#wrote, iclass 23, count 2 2006.217.08:14:00.02#ibcon#about to read 3, iclass 23, count 2 2006.217.08:14:00.05#ibcon#read 3, iclass 23, count 2 2006.217.08:14:00.05#ibcon#about to read 4, iclass 23, count 2 2006.217.08:14:00.05#ibcon#read 4, iclass 23, count 2 2006.217.08:14:00.05#ibcon#about to read 5, iclass 23, count 2 2006.217.08:14:00.05#ibcon#read 5, iclass 23, count 2 2006.217.08:14:00.05#ibcon#about to read 6, iclass 23, count 2 2006.217.08:14:00.05#ibcon#read 6, iclass 23, count 2 2006.217.08:14:00.05#ibcon#end of sib2, iclass 23, count 2 2006.217.08:14:00.05#ibcon#*after write, iclass 23, count 2 2006.217.08:14:00.05#ibcon#*before return 0, iclass 23, count 2 2006.217.08:14:00.05#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.217.08:14:00.05#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.217.08:14:00.05#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.217.08:14:00.05#ibcon#ireg 7 cls_cnt 0 2006.217.08:14:00.05#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.217.08:14:00.17#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.217.08:14:00.17#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.217.08:14:00.17#ibcon#enter wrdev, iclass 23, count 0 2006.217.08:14:00.17#ibcon#first serial, iclass 23, count 0 2006.217.08:14:00.17#ibcon#enter sib2, iclass 23, count 0 2006.217.08:14:00.17#ibcon#flushed, iclass 23, count 0 2006.217.08:14:00.17#ibcon#about to write, iclass 23, count 0 2006.217.08:14:00.17#ibcon#wrote, iclass 23, count 0 2006.217.08:14:00.17#ibcon#about to read 3, iclass 23, count 0 2006.217.08:14:00.20#ibcon#read 3, iclass 23, count 0 2006.217.08:14:00.20#ibcon#about to read 4, iclass 23, count 0 2006.217.08:14:00.20#ibcon#read 4, iclass 23, count 0 2006.217.08:14:00.20#ibcon#about to read 5, iclass 23, count 0 2006.217.08:14:00.20#ibcon#read 5, iclass 23, count 0 2006.217.08:14:00.20#ibcon#about to read 6, iclass 23, count 0 2006.217.08:14:00.20#ibcon#read 6, iclass 23, count 0 2006.217.08:14:00.20#ibcon#end of sib2, iclass 23, count 0 2006.217.08:14:00.20#ibcon#*mode == 0, iclass 23, count 0 2006.217.08:14:00.20#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.217.08:14:00.20#ibcon#[25=USB\r\n] 2006.217.08:14:00.20#ibcon#*before write, iclass 23, count 0 2006.217.08:14:00.20#ibcon#enter sib2, iclass 23, count 0 2006.217.08:14:00.20#ibcon#flushed, iclass 23, count 0 2006.217.08:14:00.20#ibcon#about to write, iclass 23, count 0 2006.217.08:14:00.20#ibcon#wrote, iclass 23, count 0 2006.217.08:14:00.20#ibcon#about to read 3, iclass 23, count 0 2006.217.08:14:00.23#ibcon#read 3, iclass 23, count 0 2006.217.08:14:00.23#ibcon#about to read 4, iclass 23, count 0 2006.217.08:14:00.23#ibcon#read 4, iclass 23, count 0 2006.217.08:14:00.23#ibcon#about to read 5, iclass 23, count 0 2006.217.08:14:00.23#ibcon#read 5, iclass 23, count 0 2006.217.08:14:00.23#ibcon#about to read 6, iclass 23, count 0 2006.217.08:14:00.23#ibcon#read 6, iclass 23, count 0 2006.217.08:14:00.23#ibcon#end of sib2, iclass 23, count 0 2006.217.08:14:00.23#ibcon#*after write, iclass 23, count 0 2006.217.08:14:00.23#ibcon#*before return 0, iclass 23, count 0 2006.217.08:14:00.23#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.217.08:14:00.23#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.217.08:14:00.23#ibcon#about to clear, iclass 23 cls_cnt 0 2006.217.08:14:00.23#ibcon#cleared, iclass 23 cls_cnt 0 2006.217.08:14:00.23$vc4f8/valo=8,852.99 2006.217.08:14:00.23#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.217.08:14:00.23#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.217.08:14:00.23#ibcon#ireg 17 cls_cnt 0 2006.217.08:14:00.23#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.217.08:14:00.23#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.217.08:14:00.23#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.217.08:14:00.23#ibcon#enter wrdev, iclass 25, count 0 2006.217.08:14:00.23#ibcon#first serial, iclass 25, count 0 2006.217.08:14:00.23#ibcon#enter sib2, iclass 25, count 0 2006.217.08:14:00.23#ibcon#flushed, iclass 25, count 0 2006.217.08:14:00.23#ibcon#about to write, iclass 25, count 0 2006.217.08:14:00.23#ibcon#wrote, iclass 25, count 0 2006.217.08:14:00.23#ibcon#about to read 3, iclass 25, count 0 2006.217.08:14:00.25#ibcon#read 3, iclass 25, count 0 2006.217.08:14:00.25#ibcon#about to read 4, iclass 25, count 0 2006.217.08:14:00.25#ibcon#read 4, iclass 25, count 0 2006.217.08:14:00.25#ibcon#about to read 5, iclass 25, count 0 2006.217.08:14:00.25#ibcon#read 5, iclass 25, count 0 2006.217.08:14:00.25#ibcon#about to read 6, iclass 25, count 0 2006.217.08:14:00.25#ibcon#read 6, iclass 25, count 0 2006.217.08:14:00.25#ibcon#end of sib2, iclass 25, count 0 2006.217.08:14:00.25#ibcon#*mode == 0, iclass 25, count 0 2006.217.08:14:00.25#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.217.08:14:00.25#ibcon#[26=FRQ=08,852.99\r\n] 2006.217.08:14:00.25#ibcon#*before write, iclass 25, count 0 2006.217.08:14:00.25#ibcon#enter sib2, iclass 25, count 0 2006.217.08:14:00.25#ibcon#flushed, iclass 25, count 0 2006.217.08:14:00.25#ibcon#about to write, iclass 25, count 0 2006.217.08:14:00.25#ibcon#wrote, iclass 25, count 0 2006.217.08:14:00.25#ibcon#about to read 3, iclass 25, count 0 2006.217.08:14:00.29#ibcon#read 3, iclass 25, count 0 2006.217.08:14:00.29#ibcon#about to read 4, iclass 25, count 0 2006.217.08:14:00.29#ibcon#read 4, iclass 25, count 0 2006.217.08:14:00.29#ibcon#about to read 5, iclass 25, count 0 2006.217.08:14:00.29#ibcon#read 5, iclass 25, count 0 2006.217.08:14:00.29#ibcon#about to read 6, iclass 25, count 0 2006.217.08:14:00.29#ibcon#read 6, iclass 25, count 0 2006.217.08:14:00.29#ibcon#end of sib2, iclass 25, count 0 2006.217.08:14:00.29#ibcon#*after write, iclass 25, count 0 2006.217.08:14:00.29#ibcon#*before return 0, iclass 25, count 0 2006.217.08:14:00.29#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.217.08:14:00.29#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.217.08:14:00.29#ibcon#about to clear, iclass 25 cls_cnt 0 2006.217.08:14:00.29#ibcon#cleared, iclass 25 cls_cnt 0 2006.217.08:14:00.29$vc4f8/va=8,7 2006.217.08:14:00.29#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.217.08:14:00.29#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.217.08:14:00.29#ibcon#ireg 11 cls_cnt 2 2006.217.08:14:00.29#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.217.08:14:00.35#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.217.08:14:00.35#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.217.08:14:00.35#ibcon#enter wrdev, iclass 27, count 2 2006.217.08:14:00.35#ibcon#first serial, iclass 27, count 2 2006.217.08:14:00.35#ibcon#enter sib2, iclass 27, count 2 2006.217.08:14:00.35#ibcon#flushed, iclass 27, count 2 2006.217.08:14:00.35#ibcon#about to write, iclass 27, count 2 2006.217.08:14:00.35#ibcon#wrote, iclass 27, count 2 2006.217.08:14:00.35#ibcon#about to read 3, iclass 27, count 2 2006.217.08:14:00.37#ibcon#read 3, iclass 27, count 2 2006.217.08:14:00.37#ibcon#about to read 4, iclass 27, count 2 2006.217.08:14:00.37#ibcon#read 4, iclass 27, count 2 2006.217.08:14:00.37#ibcon#about to read 5, iclass 27, count 2 2006.217.08:14:00.37#ibcon#read 5, iclass 27, count 2 2006.217.08:14:00.37#ibcon#about to read 6, iclass 27, count 2 2006.217.08:14:00.37#ibcon#read 6, iclass 27, count 2 2006.217.08:14:00.37#ibcon#end of sib2, iclass 27, count 2 2006.217.08:14:00.37#ibcon#*mode == 0, iclass 27, count 2 2006.217.08:14:00.37#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.217.08:14:00.37#ibcon#[25=AT08-07\r\n] 2006.217.08:14:00.37#ibcon#*before write, iclass 27, count 2 2006.217.08:14:00.37#ibcon#enter sib2, iclass 27, count 2 2006.217.08:14:00.37#ibcon#flushed, iclass 27, count 2 2006.217.08:14:00.37#ibcon#about to write, iclass 27, count 2 2006.217.08:14:00.37#ibcon#wrote, iclass 27, count 2 2006.217.08:14:00.37#ibcon#about to read 3, iclass 27, count 2 2006.217.08:14:00.40#ibcon#read 3, iclass 27, count 2 2006.217.08:14:00.40#ibcon#about to read 4, iclass 27, count 2 2006.217.08:14:00.40#ibcon#read 4, iclass 27, count 2 2006.217.08:14:00.40#ibcon#about to read 5, iclass 27, count 2 2006.217.08:14:00.40#ibcon#read 5, iclass 27, count 2 2006.217.08:14:00.40#ibcon#about to read 6, iclass 27, count 2 2006.217.08:14:00.40#ibcon#read 6, iclass 27, count 2 2006.217.08:14:00.40#ibcon#end of sib2, iclass 27, count 2 2006.217.08:14:00.40#ibcon#*after write, iclass 27, count 2 2006.217.08:14:00.40#ibcon#*before return 0, iclass 27, count 2 2006.217.08:14:00.40#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.217.08:14:00.40#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.217.08:14:00.40#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.217.08:14:00.40#ibcon#ireg 7 cls_cnt 0 2006.217.08:14:00.40#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.217.08:14:00.52#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.217.08:14:00.52#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.217.08:14:00.52#ibcon#enter wrdev, iclass 27, count 0 2006.217.08:14:00.52#ibcon#first serial, iclass 27, count 0 2006.217.08:14:00.52#ibcon#enter sib2, iclass 27, count 0 2006.217.08:14:00.52#ibcon#flushed, iclass 27, count 0 2006.217.08:14:00.52#ibcon#about to write, iclass 27, count 0 2006.217.08:14:00.52#ibcon#wrote, iclass 27, count 0 2006.217.08:14:00.52#ibcon#about to read 3, iclass 27, count 0 2006.217.08:14:00.54#ibcon#read 3, iclass 27, count 0 2006.217.08:14:00.54#ibcon#about to read 4, iclass 27, count 0 2006.217.08:14:00.54#ibcon#read 4, iclass 27, count 0 2006.217.08:14:00.54#ibcon#about to read 5, iclass 27, count 0 2006.217.08:14:00.54#ibcon#read 5, iclass 27, count 0 2006.217.08:14:00.54#ibcon#about to read 6, iclass 27, count 0 2006.217.08:14:00.54#ibcon#read 6, iclass 27, count 0 2006.217.08:14:00.54#ibcon#end of sib2, iclass 27, count 0 2006.217.08:14:00.54#ibcon#*mode == 0, iclass 27, count 0 2006.217.08:14:00.54#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.217.08:14:00.54#ibcon#[25=USB\r\n] 2006.217.08:14:00.54#ibcon#*before write, iclass 27, count 0 2006.217.08:14:00.54#ibcon#enter sib2, iclass 27, count 0 2006.217.08:14:00.54#ibcon#flushed, iclass 27, count 0 2006.217.08:14:00.54#ibcon#about to write, iclass 27, count 0 2006.217.08:14:00.54#ibcon#wrote, iclass 27, count 0 2006.217.08:14:00.54#ibcon#about to read 3, iclass 27, count 0 2006.217.08:14:00.57#ibcon#read 3, iclass 27, count 0 2006.217.08:14:00.57#ibcon#about to read 4, iclass 27, count 0 2006.217.08:14:00.57#ibcon#read 4, iclass 27, count 0 2006.217.08:14:00.57#ibcon#about to read 5, iclass 27, count 0 2006.217.08:14:00.57#ibcon#read 5, iclass 27, count 0 2006.217.08:14:00.57#ibcon#about to read 6, iclass 27, count 0 2006.217.08:14:00.57#ibcon#read 6, iclass 27, count 0 2006.217.08:14:00.57#ibcon#end of sib2, iclass 27, count 0 2006.217.08:14:00.57#ibcon#*after write, iclass 27, count 0 2006.217.08:14:00.57#ibcon#*before return 0, iclass 27, count 0 2006.217.08:14:00.57#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.217.08:14:00.57#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.217.08:14:00.57#ibcon#about to clear, iclass 27 cls_cnt 0 2006.217.08:14:00.57#ibcon#cleared, iclass 27 cls_cnt 0 2006.217.08:14:00.57$vc4f8/vblo=1,632.99 2006.217.08:14:00.57#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.217.08:14:00.57#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.217.08:14:00.57#ibcon#ireg 17 cls_cnt 0 2006.217.08:14:00.57#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.217.08:14:00.57#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.217.08:14:00.57#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.217.08:14:00.57#ibcon#enter wrdev, iclass 29, count 0 2006.217.08:14:00.57#ibcon#first serial, iclass 29, count 0 2006.217.08:14:00.57#ibcon#enter sib2, iclass 29, count 0 2006.217.08:14:00.57#ibcon#flushed, iclass 29, count 0 2006.217.08:14:00.57#ibcon#about to write, iclass 29, count 0 2006.217.08:14:00.57#ibcon#wrote, iclass 29, count 0 2006.217.08:14:00.57#ibcon#about to read 3, iclass 29, count 0 2006.217.08:14:00.59#ibcon#read 3, iclass 29, count 0 2006.217.08:14:00.59#ibcon#about to read 4, iclass 29, count 0 2006.217.08:14:00.59#ibcon#read 4, iclass 29, count 0 2006.217.08:14:00.59#ibcon#about to read 5, iclass 29, count 0 2006.217.08:14:00.59#ibcon#read 5, iclass 29, count 0 2006.217.08:14:00.59#ibcon#about to read 6, iclass 29, count 0 2006.217.08:14:00.59#ibcon#read 6, iclass 29, count 0 2006.217.08:14:00.59#ibcon#end of sib2, iclass 29, count 0 2006.217.08:14:00.59#ibcon#*mode == 0, iclass 29, count 0 2006.217.08:14:00.59#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.217.08:14:00.59#ibcon#[28=FRQ=01,632.99\r\n] 2006.217.08:14:00.59#ibcon#*before write, iclass 29, count 0 2006.217.08:14:00.59#ibcon#enter sib2, iclass 29, count 0 2006.217.08:14:00.59#ibcon#flushed, iclass 29, count 0 2006.217.08:14:00.59#ibcon#about to write, iclass 29, count 0 2006.217.08:14:00.59#ibcon#wrote, iclass 29, count 0 2006.217.08:14:00.59#ibcon#about to read 3, iclass 29, count 0 2006.217.08:14:00.63#ibcon#read 3, iclass 29, count 0 2006.217.08:14:00.63#ibcon#about to read 4, iclass 29, count 0 2006.217.08:14:00.63#ibcon#read 4, iclass 29, count 0 2006.217.08:14:00.63#ibcon#about to read 5, iclass 29, count 0 2006.217.08:14:00.63#ibcon#read 5, iclass 29, count 0 2006.217.08:14:00.63#ibcon#about to read 6, iclass 29, count 0 2006.217.08:14:00.63#ibcon#read 6, iclass 29, count 0 2006.217.08:14:00.63#ibcon#end of sib2, iclass 29, count 0 2006.217.08:14:00.63#ibcon#*after write, iclass 29, count 0 2006.217.08:14:00.63#ibcon#*before return 0, iclass 29, count 0 2006.217.08:14:00.63#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.217.08:14:00.63#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.217.08:14:00.63#ibcon#about to clear, iclass 29 cls_cnt 0 2006.217.08:14:00.63#ibcon#cleared, iclass 29 cls_cnt 0 2006.217.08:14:00.63$vc4f8/vb=1,4 2006.217.08:14:00.63#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.217.08:14:00.63#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.217.08:14:00.63#ibcon#ireg 11 cls_cnt 2 2006.217.08:14:00.63#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.217.08:14:00.63#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.217.08:14:00.63#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.217.08:14:00.63#ibcon#enter wrdev, iclass 31, count 2 2006.217.08:14:00.63#ibcon#first serial, iclass 31, count 2 2006.217.08:14:00.63#ibcon#enter sib2, iclass 31, count 2 2006.217.08:14:00.63#ibcon#flushed, iclass 31, count 2 2006.217.08:14:00.63#ibcon#about to write, iclass 31, count 2 2006.217.08:14:00.63#ibcon#wrote, iclass 31, count 2 2006.217.08:14:00.63#ibcon#about to read 3, iclass 31, count 2 2006.217.08:14:00.65#ibcon#read 3, iclass 31, count 2 2006.217.08:14:00.65#ibcon#about to read 4, iclass 31, count 2 2006.217.08:14:00.65#ibcon#read 4, iclass 31, count 2 2006.217.08:14:00.65#ibcon#about to read 5, iclass 31, count 2 2006.217.08:14:00.65#ibcon#read 5, iclass 31, count 2 2006.217.08:14:00.65#ibcon#about to read 6, iclass 31, count 2 2006.217.08:14:00.65#ibcon#read 6, iclass 31, count 2 2006.217.08:14:00.65#ibcon#end of sib2, iclass 31, count 2 2006.217.08:14:00.65#ibcon#*mode == 0, iclass 31, count 2 2006.217.08:14:00.65#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.217.08:14:00.65#ibcon#[27=AT01-04\r\n] 2006.217.08:14:00.65#ibcon#*before write, iclass 31, count 2 2006.217.08:14:00.65#ibcon#enter sib2, iclass 31, count 2 2006.217.08:14:00.65#ibcon#flushed, iclass 31, count 2 2006.217.08:14:00.65#ibcon#about to write, iclass 31, count 2 2006.217.08:14:00.65#ibcon#wrote, iclass 31, count 2 2006.217.08:14:00.65#ibcon#about to read 3, iclass 31, count 2 2006.217.08:14:00.68#ibcon#read 3, iclass 31, count 2 2006.217.08:14:00.68#ibcon#about to read 4, iclass 31, count 2 2006.217.08:14:00.68#ibcon#read 4, iclass 31, count 2 2006.217.08:14:00.68#ibcon#about to read 5, iclass 31, count 2 2006.217.08:14:00.68#ibcon#read 5, iclass 31, count 2 2006.217.08:14:00.68#ibcon#about to read 6, iclass 31, count 2 2006.217.08:14:00.68#ibcon#read 6, iclass 31, count 2 2006.217.08:14:00.68#ibcon#end of sib2, iclass 31, count 2 2006.217.08:14:00.68#ibcon#*after write, iclass 31, count 2 2006.217.08:14:00.68#ibcon#*before return 0, iclass 31, count 2 2006.217.08:14:00.68#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.217.08:14:00.68#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.217.08:14:00.68#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.217.08:14:00.68#ibcon#ireg 7 cls_cnt 0 2006.217.08:14:00.68#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.217.08:14:00.80#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.217.08:14:00.80#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.217.08:14:00.80#ibcon#enter wrdev, iclass 31, count 0 2006.217.08:14:00.80#ibcon#first serial, iclass 31, count 0 2006.217.08:14:00.80#ibcon#enter sib2, iclass 31, count 0 2006.217.08:14:00.80#ibcon#flushed, iclass 31, count 0 2006.217.08:14:00.80#ibcon#about to write, iclass 31, count 0 2006.217.08:14:00.80#ibcon#wrote, iclass 31, count 0 2006.217.08:14:00.80#ibcon#about to read 3, iclass 31, count 0 2006.217.08:14:00.82#ibcon#read 3, iclass 31, count 0 2006.217.08:14:00.82#ibcon#about to read 4, iclass 31, count 0 2006.217.08:14:00.82#ibcon#read 4, iclass 31, count 0 2006.217.08:14:00.82#ibcon#about to read 5, iclass 31, count 0 2006.217.08:14:00.82#ibcon#read 5, iclass 31, count 0 2006.217.08:14:00.82#ibcon#about to read 6, iclass 31, count 0 2006.217.08:14:00.82#ibcon#read 6, iclass 31, count 0 2006.217.08:14:00.82#ibcon#end of sib2, iclass 31, count 0 2006.217.08:14:00.82#ibcon#*mode == 0, iclass 31, count 0 2006.217.08:14:00.82#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.217.08:14:00.82#ibcon#[27=USB\r\n] 2006.217.08:14:00.82#ibcon#*before write, iclass 31, count 0 2006.217.08:14:00.82#ibcon#enter sib2, iclass 31, count 0 2006.217.08:14:00.82#ibcon#flushed, iclass 31, count 0 2006.217.08:14:00.82#ibcon#about to write, iclass 31, count 0 2006.217.08:14:00.82#ibcon#wrote, iclass 31, count 0 2006.217.08:14:00.82#ibcon#about to read 3, iclass 31, count 0 2006.217.08:14:00.85#ibcon#read 3, iclass 31, count 0 2006.217.08:14:00.85#ibcon#about to read 4, iclass 31, count 0 2006.217.08:14:00.85#ibcon#read 4, iclass 31, count 0 2006.217.08:14:00.85#ibcon#about to read 5, iclass 31, count 0 2006.217.08:14:00.85#ibcon#read 5, iclass 31, count 0 2006.217.08:14:00.85#ibcon#about to read 6, iclass 31, count 0 2006.217.08:14:00.85#ibcon#read 6, iclass 31, count 0 2006.217.08:14:00.85#ibcon#end of sib2, iclass 31, count 0 2006.217.08:14:00.85#ibcon#*after write, iclass 31, count 0 2006.217.08:14:00.85#ibcon#*before return 0, iclass 31, count 0 2006.217.08:14:00.85#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.217.08:14:00.85#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.217.08:14:00.85#ibcon#about to clear, iclass 31 cls_cnt 0 2006.217.08:14:00.85#ibcon#cleared, iclass 31 cls_cnt 0 2006.217.08:14:00.85$vc4f8/vblo=2,640.99 2006.217.08:14:00.85#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.217.08:14:00.85#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.217.08:14:00.85#ibcon#ireg 17 cls_cnt 0 2006.217.08:14:00.85#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.217.08:14:00.85#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.217.08:14:00.85#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.217.08:14:00.85#ibcon#enter wrdev, iclass 33, count 0 2006.217.08:14:00.85#ibcon#first serial, iclass 33, count 0 2006.217.08:14:00.85#ibcon#enter sib2, iclass 33, count 0 2006.217.08:14:00.85#ibcon#flushed, iclass 33, count 0 2006.217.08:14:00.85#ibcon#about to write, iclass 33, count 0 2006.217.08:14:00.85#ibcon#wrote, iclass 33, count 0 2006.217.08:14:00.85#ibcon#about to read 3, iclass 33, count 0 2006.217.08:14:00.87#ibcon#read 3, iclass 33, count 0 2006.217.08:14:00.87#ibcon#about to read 4, iclass 33, count 0 2006.217.08:14:00.87#ibcon#read 4, iclass 33, count 0 2006.217.08:14:00.87#ibcon#about to read 5, iclass 33, count 0 2006.217.08:14:00.87#ibcon#read 5, iclass 33, count 0 2006.217.08:14:00.87#ibcon#about to read 6, iclass 33, count 0 2006.217.08:14:00.87#ibcon#read 6, iclass 33, count 0 2006.217.08:14:00.87#ibcon#end of sib2, iclass 33, count 0 2006.217.08:14:00.87#ibcon#*mode == 0, iclass 33, count 0 2006.217.08:14:00.87#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.217.08:14:00.87#ibcon#[28=FRQ=02,640.99\r\n] 2006.217.08:14:00.87#ibcon#*before write, iclass 33, count 0 2006.217.08:14:00.87#ibcon#enter sib2, iclass 33, count 0 2006.217.08:14:00.87#ibcon#flushed, iclass 33, count 0 2006.217.08:14:00.87#ibcon#about to write, iclass 33, count 0 2006.217.08:14:00.87#ibcon#wrote, iclass 33, count 0 2006.217.08:14:00.87#ibcon#about to read 3, iclass 33, count 0 2006.217.08:14:00.91#ibcon#read 3, iclass 33, count 0 2006.217.08:14:00.91#ibcon#about to read 4, iclass 33, count 0 2006.217.08:14:00.91#ibcon#read 4, iclass 33, count 0 2006.217.08:14:00.91#ibcon#about to read 5, iclass 33, count 0 2006.217.08:14:00.91#ibcon#read 5, iclass 33, count 0 2006.217.08:14:00.91#ibcon#about to read 6, iclass 33, count 0 2006.217.08:14:00.91#ibcon#read 6, iclass 33, count 0 2006.217.08:14:00.91#ibcon#end of sib2, iclass 33, count 0 2006.217.08:14:00.91#ibcon#*after write, iclass 33, count 0 2006.217.08:14:00.91#ibcon#*before return 0, iclass 33, count 0 2006.217.08:14:00.91#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.217.08:14:00.91#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.217.08:14:00.91#ibcon#about to clear, iclass 33 cls_cnt 0 2006.217.08:14:00.91#ibcon#cleared, iclass 33 cls_cnt 0 2006.217.08:14:00.91$vc4f8/vb=2,4 2006.217.08:14:00.91#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.217.08:14:00.91#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.217.08:14:00.91#ibcon#ireg 11 cls_cnt 2 2006.217.08:14:00.91#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.217.08:14:00.97#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.217.08:14:00.97#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.217.08:14:00.97#ibcon#enter wrdev, iclass 35, count 2 2006.217.08:14:00.97#ibcon#first serial, iclass 35, count 2 2006.217.08:14:00.97#ibcon#enter sib2, iclass 35, count 2 2006.217.08:14:00.97#ibcon#flushed, iclass 35, count 2 2006.217.08:14:00.97#ibcon#about to write, iclass 35, count 2 2006.217.08:14:00.97#ibcon#wrote, iclass 35, count 2 2006.217.08:14:00.97#ibcon#about to read 3, iclass 35, count 2 2006.217.08:14:00.99#ibcon#read 3, iclass 35, count 2 2006.217.08:14:00.99#ibcon#about to read 4, iclass 35, count 2 2006.217.08:14:00.99#ibcon#read 4, iclass 35, count 2 2006.217.08:14:00.99#ibcon#about to read 5, iclass 35, count 2 2006.217.08:14:00.99#ibcon#read 5, iclass 35, count 2 2006.217.08:14:00.99#ibcon#about to read 6, iclass 35, count 2 2006.217.08:14:00.99#ibcon#read 6, iclass 35, count 2 2006.217.08:14:00.99#ibcon#end of sib2, iclass 35, count 2 2006.217.08:14:00.99#ibcon#*mode == 0, iclass 35, count 2 2006.217.08:14:00.99#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.217.08:14:00.99#ibcon#[27=AT02-04\r\n] 2006.217.08:14:00.99#ibcon#*before write, iclass 35, count 2 2006.217.08:14:00.99#ibcon#enter sib2, iclass 35, count 2 2006.217.08:14:00.99#ibcon#flushed, iclass 35, count 2 2006.217.08:14:00.99#ibcon#about to write, iclass 35, count 2 2006.217.08:14:00.99#ibcon#wrote, iclass 35, count 2 2006.217.08:14:00.99#ibcon#about to read 3, iclass 35, count 2 2006.217.08:14:01.02#ibcon#read 3, iclass 35, count 2 2006.217.08:14:01.02#ibcon#about to read 4, iclass 35, count 2 2006.217.08:14:01.02#ibcon#read 4, iclass 35, count 2 2006.217.08:14:01.02#ibcon#about to read 5, iclass 35, count 2 2006.217.08:14:01.02#ibcon#read 5, iclass 35, count 2 2006.217.08:14:01.02#ibcon#about to read 6, iclass 35, count 2 2006.217.08:14:01.02#ibcon#read 6, iclass 35, count 2 2006.217.08:14:01.02#ibcon#end of sib2, iclass 35, count 2 2006.217.08:14:01.02#ibcon#*after write, iclass 35, count 2 2006.217.08:14:01.02#ibcon#*before return 0, iclass 35, count 2 2006.217.08:14:01.02#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.217.08:14:01.02#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.217.08:14:01.02#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.217.08:14:01.02#ibcon#ireg 7 cls_cnt 0 2006.217.08:14:01.02#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.217.08:14:01.14#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.217.08:14:01.14#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.217.08:14:01.14#ibcon#enter wrdev, iclass 35, count 0 2006.217.08:14:01.14#ibcon#first serial, iclass 35, count 0 2006.217.08:14:01.14#ibcon#enter sib2, iclass 35, count 0 2006.217.08:14:01.14#ibcon#flushed, iclass 35, count 0 2006.217.08:14:01.14#ibcon#about to write, iclass 35, count 0 2006.217.08:14:01.14#ibcon#wrote, iclass 35, count 0 2006.217.08:14:01.14#ibcon#about to read 3, iclass 35, count 0 2006.217.08:14:01.16#ibcon#read 3, iclass 35, count 0 2006.217.08:14:01.16#ibcon#about to read 4, iclass 35, count 0 2006.217.08:14:01.16#ibcon#read 4, iclass 35, count 0 2006.217.08:14:01.16#ibcon#about to read 5, iclass 35, count 0 2006.217.08:14:01.16#ibcon#read 5, iclass 35, count 0 2006.217.08:14:01.16#ibcon#about to read 6, iclass 35, count 0 2006.217.08:14:01.16#ibcon#read 6, iclass 35, count 0 2006.217.08:14:01.16#ibcon#end of sib2, iclass 35, count 0 2006.217.08:14:01.16#ibcon#*mode == 0, iclass 35, count 0 2006.217.08:14:01.16#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.217.08:14:01.16#ibcon#[27=USB\r\n] 2006.217.08:14:01.16#ibcon#*before write, iclass 35, count 0 2006.217.08:14:01.16#ibcon#enter sib2, iclass 35, count 0 2006.217.08:14:01.16#ibcon#flushed, iclass 35, count 0 2006.217.08:14:01.16#ibcon#about to write, iclass 35, count 0 2006.217.08:14:01.16#ibcon#wrote, iclass 35, count 0 2006.217.08:14:01.16#ibcon#about to read 3, iclass 35, count 0 2006.217.08:14:01.19#ibcon#read 3, iclass 35, count 0 2006.217.08:14:01.19#ibcon#about to read 4, iclass 35, count 0 2006.217.08:14:01.19#ibcon#read 4, iclass 35, count 0 2006.217.08:14:01.19#ibcon#about to read 5, iclass 35, count 0 2006.217.08:14:01.19#ibcon#read 5, iclass 35, count 0 2006.217.08:14:01.19#ibcon#about to read 6, iclass 35, count 0 2006.217.08:14:01.19#ibcon#read 6, iclass 35, count 0 2006.217.08:14:01.19#ibcon#end of sib2, iclass 35, count 0 2006.217.08:14:01.19#ibcon#*after write, iclass 35, count 0 2006.217.08:14:01.19#ibcon#*before return 0, iclass 35, count 0 2006.217.08:14:01.19#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.217.08:14:01.19#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.217.08:14:01.19#ibcon#about to clear, iclass 35 cls_cnt 0 2006.217.08:14:01.19#ibcon#cleared, iclass 35 cls_cnt 0 2006.217.08:14:01.19$vc4f8/vblo=3,656.99 2006.217.08:14:01.19#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.217.08:14:01.19#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.217.08:14:01.19#ibcon#ireg 17 cls_cnt 0 2006.217.08:14:01.19#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.217.08:14:01.19#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.217.08:14:01.19#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.217.08:14:01.19#ibcon#enter wrdev, iclass 37, count 0 2006.217.08:14:01.19#ibcon#first serial, iclass 37, count 0 2006.217.08:14:01.19#ibcon#enter sib2, iclass 37, count 0 2006.217.08:14:01.19#ibcon#flushed, iclass 37, count 0 2006.217.08:14:01.19#ibcon#about to write, iclass 37, count 0 2006.217.08:14:01.19#ibcon#wrote, iclass 37, count 0 2006.217.08:14:01.19#ibcon#about to read 3, iclass 37, count 0 2006.217.08:14:01.21#ibcon#read 3, iclass 37, count 0 2006.217.08:14:01.21#ibcon#about to read 4, iclass 37, count 0 2006.217.08:14:01.21#ibcon#read 4, iclass 37, count 0 2006.217.08:14:01.21#ibcon#about to read 5, iclass 37, count 0 2006.217.08:14:01.21#ibcon#read 5, iclass 37, count 0 2006.217.08:14:01.21#ibcon#about to read 6, iclass 37, count 0 2006.217.08:14:01.21#ibcon#read 6, iclass 37, count 0 2006.217.08:14:01.21#ibcon#end of sib2, iclass 37, count 0 2006.217.08:14:01.21#ibcon#*mode == 0, iclass 37, count 0 2006.217.08:14:01.21#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.217.08:14:01.21#ibcon#[28=FRQ=03,656.99\r\n] 2006.217.08:14:01.21#ibcon#*before write, iclass 37, count 0 2006.217.08:14:01.21#ibcon#enter sib2, iclass 37, count 0 2006.217.08:14:01.21#ibcon#flushed, iclass 37, count 0 2006.217.08:14:01.21#ibcon#about to write, iclass 37, count 0 2006.217.08:14:01.21#ibcon#wrote, iclass 37, count 0 2006.217.08:14:01.21#ibcon#about to read 3, iclass 37, count 0 2006.217.08:14:01.25#ibcon#read 3, iclass 37, count 0 2006.217.08:14:01.25#ibcon#about to read 4, iclass 37, count 0 2006.217.08:14:01.25#ibcon#read 4, iclass 37, count 0 2006.217.08:14:01.25#ibcon#about to read 5, iclass 37, count 0 2006.217.08:14:01.25#ibcon#read 5, iclass 37, count 0 2006.217.08:14:01.25#ibcon#about to read 6, iclass 37, count 0 2006.217.08:14:01.25#ibcon#read 6, iclass 37, count 0 2006.217.08:14:01.25#ibcon#end of sib2, iclass 37, count 0 2006.217.08:14:01.25#ibcon#*after write, iclass 37, count 0 2006.217.08:14:01.25#ibcon#*before return 0, iclass 37, count 0 2006.217.08:14:01.25#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.217.08:14:01.25#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.217.08:14:01.25#ibcon#about to clear, iclass 37 cls_cnt 0 2006.217.08:14:01.25#ibcon#cleared, iclass 37 cls_cnt 0 2006.217.08:14:01.25$vc4f8/vb=3,4 2006.217.08:14:01.25#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.217.08:14:01.25#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.217.08:14:01.25#ibcon#ireg 11 cls_cnt 2 2006.217.08:14:01.25#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.217.08:14:01.31#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.217.08:14:01.31#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.217.08:14:01.31#ibcon#enter wrdev, iclass 39, count 2 2006.217.08:14:01.31#ibcon#first serial, iclass 39, count 2 2006.217.08:14:01.31#ibcon#enter sib2, iclass 39, count 2 2006.217.08:14:01.31#ibcon#flushed, iclass 39, count 2 2006.217.08:14:01.31#ibcon#about to write, iclass 39, count 2 2006.217.08:14:01.31#ibcon#wrote, iclass 39, count 2 2006.217.08:14:01.31#ibcon#about to read 3, iclass 39, count 2 2006.217.08:14:01.33#ibcon#read 3, iclass 39, count 2 2006.217.08:14:01.33#ibcon#about to read 4, iclass 39, count 2 2006.217.08:14:01.33#ibcon#read 4, iclass 39, count 2 2006.217.08:14:01.33#ibcon#about to read 5, iclass 39, count 2 2006.217.08:14:01.33#ibcon#read 5, iclass 39, count 2 2006.217.08:14:01.33#ibcon#about to read 6, iclass 39, count 2 2006.217.08:14:01.33#ibcon#read 6, iclass 39, count 2 2006.217.08:14:01.33#ibcon#end of sib2, iclass 39, count 2 2006.217.08:14:01.33#ibcon#*mode == 0, iclass 39, count 2 2006.217.08:14:01.33#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.217.08:14:01.33#ibcon#[27=AT03-04\r\n] 2006.217.08:14:01.33#ibcon#*before write, iclass 39, count 2 2006.217.08:14:01.33#ibcon#enter sib2, iclass 39, count 2 2006.217.08:14:01.33#ibcon#flushed, iclass 39, count 2 2006.217.08:14:01.33#ibcon#about to write, iclass 39, count 2 2006.217.08:14:01.33#ibcon#wrote, iclass 39, count 2 2006.217.08:14:01.33#ibcon#about to read 3, iclass 39, count 2 2006.217.08:14:01.36#ibcon#read 3, iclass 39, count 2 2006.217.08:14:01.36#ibcon#about to read 4, iclass 39, count 2 2006.217.08:14:01.36#ibcon#read 4, iclass 39, count 2 2006.217.08:14:01.36#ibcon#about to read 5, iclass 39, count 2 2006.217.08:14:01.36#ibcon#read 5, iclass 39, count 2 2006.217.08:14:01.36#ibcon#about to read 6, iclass 39, count 2 2006.217.08:14:01.36#ibcon#read 6, iclass 39, count 2 2006.217.08:14:01.36#ibcon#end of sib2, iclass 39, count 2 2006.217.08:14:01.36#ibcon#*after write, iclass 39, count 2 2006.217.08:14:01.36#ibcon#*before return 0, iclass 39, count 2 2006.217.08:14:01.36#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.217.08:14:01.36#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.217.08:14:01.36#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.217.08:14:01.36#ibcon#ireg 7 cls_cnt 0 2006.217.08:14:01.36#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.217.08:14:01.48#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.217.08:14:01.48#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.217.08:14:01.48#ibcon#enter wrdev, iclass 39, count 0 2006.217.08:14:01.48#ibcon#first serial, iclass 39, count 0 2006.217.08:14:01.48#ibcon#enter sib2, iclass 39, count 0 2006.217.08:14:01.48#ibcon#flushed, iclass 39, count 0 2006.217.08:14:01.48#ibcon#about to write, iclass 39, count 0 2006.217.08:14:01.48#ibcon#wrote, iclass 39, count 0 2006.217.08:14:01.48#ibcon#about to read 3, iclass 39, count 0 2006.217.08:14:01.50#ibcon#read 3, iclass 39, count 0 2006.217.08:14:01.50#ibcon#about to read 4, iclass 39, count 0 2006.217.08:14:01.50#ibcon#read 4, iclass 39, count 0 2006.217.08:14:01.50#ibcon#about to read 5, iclass 39, count 0 2006.217.08:14:01.50#ibcon#read 5, iclass 39, count 0 2006.217.08:14:01.50#ibcon#about to read 6, iclass 39, count 0 2006.217.08:14:01.50#ibcon#read 6, iclass 39, count 0 2006.217.08:14:01.50#ibcon#end of sib2, iclass 39, count 0 2006.217.08:14:01.50#ibcon#*mode == 0, iclass 39, count 0 2006.217.08:14:01.50#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.217.08:14:01.50#ibcon#[27=USB\r\n] 2006.217.08:14:01.50#ibcon#*before write, iclass 39, count 0 2006.217.08:14:01.50#ibcon#enter sib2, iclass 39, count 0 2006.217.08:14:01.50#ibcon#flushed, iclass 39, count 0 2006.217.08:14:01.50#ibcon#about to write, iclass 39, count 0 2006.217.08:14:01.50#ibcon#wrote, iclass 39, count 0 2006.217.08:14:01.50#ibcon#about to read 3, iclass 39, count 0 2006.217.08:14:01.53#ibcon#read 3, iclass 39, count 0 2006.217.08:14:01.53#ibcon#about to read 4, iclass 39, count 0 2006.217.08:14:01.53#ibcon#read 4, iclass 39, count 0 2006.217.08:14:01.53#ibcon#about to read 5, iclass 39, count 0 2006.217.08:14:01.53#ibcon#read 5, iclass 39, count 0 2006.217.08:14:01.53#ibcon#about to read 6, iclass 39, count 0 2006.217.08:14:01.53#ibcon#read 6, iclass 39, count 0 2006.217.08:14:01.53#ibcon#end of sib2, iclass 39, count 0 2006.217.08:14:01.53#ibcon#*after write, iclass 39, count 0 2006.217.08:14:01.53#ibcon#*before return 0, iclass 39, count 0 2006.217.08:14:01.53#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.217.08:14:01.53#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.217.08:14:01.53#ibcon#about to clear, iclass 39 cls_cnt 0 2006.217.08:14:01.53#ibcon#cleared, iclass 39 cls_cnt 0 2006.217.08:14:01.53$vc4f8/vblo=4,712.99 2006.217.08:14:01.53#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.217.08:14:01.53#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.217.08:14:01.53#ibcon#ireg 17 cls_cnt 0 2006.217.08:14:01.53#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.217.08:14:01.53#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.217.08:14:01.53#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.217.08:14:01.53#ibcon#enter wrdev, iclass 3, count 0 2006.217.08:14:01.53#ibcon#first serial, iclass 3, count 0 2006.217.08:14:01.53#ibcon#enter sib2, iclass 3, count 0 2006.217.08:14:01.53#ibcon#flushed, iclass 3, count 0 2006.217.08:14:01.53#ibcon#about to write, iclass 3, count 0 2006.217.08:14:01.53#ibcon#wrote, iclass 3, count 0 2006.217.08:14:01.53#ibcon#about to read 3, iclass 3, count 0 2006.217.08:14:01.55#ibcon#read 3, iclass 3, count 0 2006.217.08:14:01.55#ibcon#about to read 4, iclass 3, count 0 2006.217.08:14:01.55#ibcon#read 4, iclass 3, count 0 2006.217.08:14:01.55#ibcon#about to read 5, iclass 3, count 0 2006.217.08:14:01.55#ibcon#read 5, iclass 3, count 0 2006.217.08:14:01.55#ibcon#about to read 6, iclass 3, count 0 2006.217.08:14:01.55#ibcon#read 6, iclass 3, count 0 2006.217.08:14:01.55#ibcon#end of sib2, iclass 3, count 0 2006.217.08:14:01.55#ibcon#*mode == 0, iclass 3, count 0 2006.217.08:14:01.55#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.217.08:14:01.55#ibcon#[28=FRQ=04,712.99\r\n] 2006.217.08:14:01.55#ibcon#*before write, iclass 3, count 0 2006.217.08:14:01.55#ibcon#enter sib2, iclass 3, count 0 2006.217.08:14:01.55#ibcon#flushed, iclass 3, count 0 2006.217.08:14:01.55#ibcon#about to write, iclass 3, count 0 2006.217.08:14:01.55#ibcon#wrote, iclass 3, count 0 2006.217.08:14:01.55#ibcon#about to read 3, iclass 3, count 0 2006.217.08:14:01.59#ibcon#read 3, iclass 3, count 0 2006.217.08:14:01.59#ibcon#about to read 4, iclass 3, count 0 2006.217.08:14:01.59#ibcon#read 4, iclass 3, count 0 2006.217.08:14:01.59#ibcon#about to read 5, iclass 3, count 0 2006.217.08:14:01.59#ibcon#read 5, iclass 3, count 0 2006.217.08:14:01.59#ibcon#about to read 6, iclass 3, count 0 2006.217.08:14:01.59#ibcon#read 6, iclass 3, count 0 2006.217.08:14:01.59#ibcon#end of sib2, iclass 3, count 0 2006.217.08:14:01.59#ibcon#*after write, iclass 3, count 0 2006.217.08:14:01.59#ibcon#*before return 0, iclass 3, count 0 2006.217.08:14:01.59#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.217.08:14:01.59#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.217.08:14:01.59#ibcon#about to clear, iclass 3 cls_cnt 0 2006.217.08:14:01.59#ibcon#cleared, iclass 3 cls_cnt 0 2006.217.08:14:01.59$vc4f8/vb=4,4 2006.217.08:14:01.59#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.217.08:14:01.59#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.217.08:14:01.59#ibcon#ireg 11 cls_cnt 2 2006.217.08:14:01.59#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.217.08:14:01.65#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.217.08:14:01.65#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.217.08:14:01.65#ibcon#enter wrdev, iclass 5, count 2 2006.217.08:14:01.65#ibcon#first serial, iclass 5, count 2 2006.217.08:14:01.65#ibcon#enter sib2, iclass 5, count 2 2006.217.08:14:01.65#ibcon#flushed, iclass 5, count 2 2006.217.08:14:01.65#ibcon#about to write, iclass 5, count 2 2006.217.08:14:01.65#ibcon#wrote, iclass 5, count 2 2006.217.08:14:01.65#ibcon#about to read 3, iclass 5, count 2 2006.217.08:14:01.67#ibcon#read 3, iclass 5, count 2 2006.217.08:14:01.67#ibcon#about to read 4, iclass 5, count 2 2006.217.08:14:01.67#ibcon#read 4, iclass 5, count 2 2006.217.08:14:01.67#ibcon#about to read 5, iclass 5, count 2 2006.217.08:14:01.67#ibcon#read 5, iclass 5, count 2 2006.217.08:14:01.67#ibcon#about to read 6, iclass 5, count 2 2006.217.08:14:01.67#ibcon#read 6, iclass 5, count 2 2006.217.08:14:01.67#ibcon#end of sib2, iclass 5, count 2 2006.217.08:14:01.67#ibcon#*mode == 0, iclass 5, count 2 2006.217.08:14:01.67#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.217.08:14:01.67#ibcon#[27=AT04-04\r\n] 2006.217.08:14:01.67#ibcon#*before write, iclass 5, count 2 2006.217.08:14:01.67#ibcon#enter sib2, iclass 5, count 2 2006.217.08:14:01.67#ibcon#flushed, iclass 5, count 2 2006.217.08:14:01.67#ibcon#about to write, iclass 5, count 2 2006.217.08:14:01.67#ibcon#wrote, iclass 5, count 2 2006.217.08:14:01.67#ibcon#about to read 3, iclass 5, count 2 2006.217.08:14:01.70#ibcon#read 3, iclass 5, count 2 2006.217.08:14:01.70#ibcon#about to read 4, iclass 5, count 2 2006.217.08:14:01.70#ibcon#read 4, iclass 5, count 2 2006.217.08:14:01.70#ibcon#about to read 5, iclass 5, count 2 2006.217.08:14:01.70#ibcon#read 5, iclass 5, count 2 2006.217.08:14:01.70#ibcon#about to read 6, iclass 5, count 2 2006.217.08:14:01.70#ibcon#read 6, iclass 5, count 2 2006.217.08:14:01.70#ibcon#end of sib2, iclass 5, count 2 2006.217.08:14:01.70#ibcon#*after write, iclass 5, count 2 2006.217.08:14:01.70#ibcon#*before return 0, iclass 5, count 2 2006.217.08:14:01.70#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.217.08:14:01.70#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.217.08:14:01.70#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.217.08:14:01.70#ibcon#ireg 7 cls_cnt 0 2006.217.08:14:01.70#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.217.08:14:01.82#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.217.08:14:01.82#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.217.08:14:01.82#ibcon#enter wrdev, iclass 5, count 0 2006.217.08:14:01.82#ibcon#first serial, iclass 5, count 0 2006.217.08:14:01.82#ibcon#enter sib2, iclass 5, count 0 2006.217.08:14:01.82#ibcon#flushed, iclass 5, count 0 2006.217.08:14:01.82#ibcon#about to write, iclass 5, count 0 2006.217.08:14:01.82#ibcon#wrote, iclass 5, count 0 2006.217.08:14:01.82#ibcon#about to read 3, iclass 5, count 0 2006.217.08:14:01.84#ibcon#read 3, iclass 5, count 0 2006.217.08:14:01.84#ibcon#about to read 4, iclass 5, count 0 2006.217.08:14:01.84#ibcon#read 4, iclass 5, count 0 2006.217.08:14:01.84#ibcon#about to read 5, iclass 5, count 0 2006.217.08:14:01.84#ibcon#read 5, iclass 5, count 0 2006.217.08:14:01.84#ibcon#about to read 6, iclass 5, count 0 2006.217.08:14:01.84#ibcon#read 6, iclass 5, count 0 2006.217.08:14:01.84#ibcon#end of sib2, iclass 5, count 0 2006.217.08:14:01.84#ibcon#*mode == 0, iclass 5, count 0 2006.217.08:14:01.84#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.217.08:14:01.84#ibcon#[27=USB\r\n] 2006.217.08:14:01.84#ibcon#*before write, iclass 5, count 0 2006.217.08:14:01.84#ibcon#enter sib2, iclass 5, count 0 2006.217.08:14:01.84#ibcon#flushed, iclass 5, count 0 2006.217.08:14:01.84#ibcon#about to write, iclass 5, count 0 2006.217.08:14:01.84#ibcon#wrote, iclass 5, count 0 2006.217.08:14:01.84#ibcon#about to read 3, iclass 5, count 0 2006.217.08:14:01.87#ibcon#read 3, iclass 5, count 0 2006.217.08:14:01.87#ibcon#about to read 4, iclass 5, count 0 2006.217.08:14:01.87#ibcon#read 4, iclass 5, count 0 2006.217.08:14:01.87#ibcon#about to read 5, iclass 5, count 0 2006.217.08:14:01.87#ibcon#read 5, iclass 5, count 0 2006.217.08:14:01.87#ibcon#about to read 6, iclass 5, count 0 2006.217.08:14:01.87#ibcon#read 6, iclass 5, count 0 2006.217.08:14:01.87#ibcon#end of sib2, iclass 5, count 0 2006.217.08:14:01.87#ibcon#*after write, iclass 5, count 0 2006.217.08:14:01.87#ibcon#*before return 0, iclass 5, count 0 2006.217.08:14:01.87#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.217.08:14:01.87#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.217.08:14:01.87#ibcon#about to clear, iclass 5 cls_cnt 0 2006.217.08:14:01.87#ibcon#cleared, iclass 5 cls_cnt 0 2006.217.08:14:01.87$vc4f8/vblo=5,744.99 2006.217.08:14:01.87#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.217.08:14:01.87#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.217.08:14:01.87#ibcon#ireg 17 cls_cnt 0 2006.217.08:14:01.87#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.217.08:14:01.87#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.217.08:14:01.87#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.217.08:14:01.87#ibcon#enter wrdev, iclass 7, count 0 2006.217.08:14:01.87#ibcon#first serial, iclass 7, count 0 2006.217.08:14:01.87#ibcon#enter sib2, iclass 7, count 0 2006.217.08:14:01.87#ibcon#flushed, iclass 7, count 0 2006.217.08:14:01.87#ibcon#about to write, iclass 7, count 0 2006.217.08:14:01.87#ibcon#wrote, iclass 7, count 0 2006.217.08:14:01.87#ibcon#about to read 3, iclass 7, count 0 2006.217.08:14:01.89#ibcon#read 3, iclass 7, count 0 2006.217.08:14:01.89#ibcon#about to read 4, iclass 7, count 0 2006.217.08:14:01.89#ibcon#read 4, iclass 7, count 0 2006.217.08:14:01.89#ibcon#about to read 5, iclass 7, count 0 2006.217.08:14:01.89#ibcon#read 5, iclass 7, count 0 2006.217.08:14:01.89#ibcon#about to read 6, iclass 7, count 0 2006.217.08:14:01.89#ibcon#read 6, iclass 7, count 0 2006.217.08:14:01.89#ibcon#end of sib2, iclass 7, count 0 2006.217.08:14:01.89#ibcon#*mode == 0, iclass 7, count 0 2006.217.08:14:01.89#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.217.08:14:01.89#ibcon#[28=FRQ=05,744.99\r\n] 2006.217.08:14:01.89#ibcon#*before write, iclass 7, count 0 2006.217.08:14:01.89#ibcon#enter sib2, iclass 7, count 0 2006.217.08:14:01.89#ibcon#flushed, iclass 7, count 0 2006.217.08:14:01.89#ibcon#about to write, iclass 7, count 0 2006.217.08:14:01.89#ibcon#wrote, iclass 7, count 0 2006.217.08:14:01.89#ibcon#about to read 3, iclass 7, count 0 2006.217.08:14:01.94#ibcon#read 3, iclass 7, count 0 2006.217.08:14:01.94#ibcon#about to read 4, iclass 7, count 0 2006.217.08:14:01.94#ibcon#read 4, iclass 7, count 0 2006.217.08:14:01.94#ibcon#about to read 5, iclass 7, count 0 2006.217.08:14:01.94#ibcon#read 5, iclass 7, count 0 2006.217.08:14:01.94#ibcon#about to read 6, iclass 7, count 0 2006.217.08:14:01.94#ibcon#read 6, iclass 7, count 0 2006.217.08:14:01.94#ibcon#end of sib2, iclass 7, count 0 2006.217.08:14:01.94#ibcon#*after write, iclass 7, count 0 2006.217.08:14:01.94#ibcon#*before return 0, iclass 7, count 0 2006.217.08:14:01.94#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.217.08:14:01.94#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.217.08:14:01.94#ibcon#about to clear, iclass 7 cls_cnt 0 2006.217.08:14:01.94#ibcon#cleared, iclass 7 cls_cnt 0 2006.217.08:14:01.94$vc4f8/vb=5,4 2006.217.08:14:01.94#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.217.08:14:01.94#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.217.08:14:01.94#ibcon#ireg 11 cls_cnt 2 2006.217.08:14:01.94#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.217.08:14:01.99#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.217.08:14:01.99#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.217.08:14:01.99#ibcon#enter wrdev, iclass 11, count 2 2006.217.08:14:01.99#ibcon#first serial, iclass 11, count 2 2006.217.08:14:01.99#ibcon#enter sib2, iclass 11, count 2 2006.217.08:14:01.99#ibcon#flushed, iclass 11, count 2 2006.217.08:14:01.99#ibcon#about to write, iclass 11, count 2 2006.217.08:14:01.99#ibcon#wrote, iclass 11, count 2 2006.217.08:14:01.99#ibcon#about to read 3, iclass 11, count 2 2006.217.08:14:02.01#ibcon#read 3, iclass 11, count 2 2006.217.08:14:02.01#ibcon#about to read 4, iclass 11, count 2 2006.217.08:14:02.01#ibcon#read 4, iclass 11, count 2 2006.217.08:14:02.01#ibcon#about to read 5, iclass 11, count 2 2006.217.08:14:02.01#ibcon#read 5, iclass 11, count 2 2006.217.08:14:02.01#ibcon#about to read 6, iclass 11, count 2 2006.217.08:14:02.01#ibcon#read 6, iclass 11, count 2 2006.217.08:14:02.01#ibcon#end of sib2, iclass 11, count 2 2006.217.08:14:02.01#ibcon#*mode == 0, iclass 11, count 2 2006.217.08:14:02.01#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.217.08:14:02.01#ibcon#[27=AT05-04\r\n] 2006.217.08:14:02.01#ibcon#*before write, iclass 11, count 2 2006.217.08:14:02.01#ibcon#enter sib2, iclass 11, count 2 2006.217.08:14:02.01#ibcon#flushed, iclass 11, count 2 2006.217.08:14:02.01#ibcon#about to write, iclass 11, count 2 2006.217.08:14:02.01#ibcon#wrote, iclass 11, count 2 2006.217.08:14:02.01#ibcon#about to read 3, iclass 11, count 2 2006.217.08:14:02.04#ibcon#read 3, iclass 11, count 2 2006.217.08:14:02.04#ibcon#about to read 4, iclass 11, count 2 2006.217.08:14:02.04#ibcon#read 4, iclass 11, count 2 2006.217.08:14:02.04#ibcon#about to read 5, iclass 11, count 2 2006.217.08:14:02.04#ibcon#read 5, iclass 11, count 2 2006.217.08:14:02.04#ibcon#about to read 6, iclass 11, count 2 2006.217.08:14:02.04#ibcon#read 6, iclass 11, count 2 2006.217.08:14:02.04#ibcon#end of sib2, iclass 11, count 2 2006.217.08:14:02.04#ibcon#*after write, iclass 11, count 2 2006.217.08:14:02.04#ibcon#*before return 0, iclass 11, count 2 2006.217.08:14:02.04#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.217.08:14:02.04#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.217.08:14:02.04#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.217.08:14:02.04#ibcon#ireg 7 cls_cnt 0 2006.217.08:14:02.04#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.217.08:14:02.16#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.217.08:14:02.16#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.217.08:14:02.16#ibcon#enter wrdev, iclass 11, count 0 2006.217.08:14:02.16#ibcon#first serial, iclass 11, count 0 2006.217.08:14:02.16#ibcon#enter sib2, iclass 11, count 0 2006.217.08:14:02.16#ibcon#flushed, iclass 11, count 0 2006.217.08:14:02.16#ibcon#about to write, iclass 11, count 0 2006.217.08:14:02.16#ibcon#wrote, iclass 11, count 0 2006.217.08:14:02.16#ibcon#about to read 3, iclass 11, count 0 2006.217.08:14:02.18#ibcon#read 3, iclass 11, count 0 2006.217.08:14:02.18#ibcon#about to read 4, iclass 11, count 0 2006.217.08:14:02.18#ibcon#read 4, iclass 11, count 0 2006.217.08:14:02.18#ibcon#about to read 5, iclass 11, count 0 2006.217.08:14:02.18#ibcon#read 5, iclass 11, count 0 2006.217.08:14:02.18#ibcon#about to read 6, iclass 11, count 0 2006.217.08:14:02.18#ibcon#read 6, iclass 11, count 0 2006.217.08:14:02.18#ibcon#end of sib2, iclass 11, count 0 2006.217.08:14:02.18#ibcon#*mode == 0, iclass 11, count 0 2006.217.08:14:02.18#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.217.08:14:02.18#ibcon#[27=USB\r\n] 2006.217.08:14:02.18#ibcon#*before write, iclass 11, count 0 2006.217.08:14:02.18#ibcon#enter sib2, iclass 11, count 0 2006.217.08:14:02.18#ibcon#flushed, iclass 11, count 0 2006.217.08:14:02.18#ibcon#about to write, iclass 11, count 0 2006.217.08:14:02.18#ibcon#wrote, iclass 11, count 0 2006.217.08:14:02.18#ibcon#about to read 3, iclass 11, count 0 2006.217.08:14:02.21#ibcon#read 3, iclass 11, count 0 2006.217.08:14:02.21#ibcon#about to read 4, iclass 11, count 0 2006.217.08:14:02.21#ibcon#read 4, iclass 11, count 0 2006.217.08:14:02.21#ibcon#about to read 5, iclass 11, count 0 2006.217.08:14:02.21#ibcon#read 5, iclass 11, count 0 2006.217.08:14:02.21#ibcon#about to read 6, iclass 11, count 0 2006.217.08:14:02.21#ibcon#read 6, iclass 11, count 0 2006.217.08:14:02.21#ibcon#end of sib2, iclass 11, count 0 2006.217.08:14:02.21#ibcon#*after write, iclass 11, count 0 2006.217.08:14:02.21#ibcon#*before return 0, iclass 11, count 0 2006.217.08:14:02.21#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.217.08:14:02.21#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.217.08:14:02.21#ibcon#about to clear, iclass 11 cls_cnt 0 2006.217.08:14:02.21#ibcon#cleared, iclass 11 cls_cnt 0 2006.217.08:14:02.21$vc4f8/vblo=6,752.99 2006.217.08:14:02.21#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.217.08:14:02.21#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.217.08:14:02.21#ibcon#ireg 17 cls_cnt 0 2006.217.08:14:02.21#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.217.08:14:02.21#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.217.08:14:02.21#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.217.08:14:02.21#ibcon#enter wrdev, iclass 13, count 0 2006.217.08:14:02.21#ibcon#first serial, iclass 13, count 0 2006.217.08:14:02.21#ibcon#enter sib2, iclass 13, count 0 2006.217.08:14:02.21#ibcon#flushed, iclass 13, count 0 2006.217.08:14:02.21#ibcon#about to write, iclass 13, count 0 2006.217.08:14:02.21#ibcon#wrote, iclass 13, count 0 2006.217.08:14:02.21#ibcon#about to read 3, iclass 13, count 0 2006.217.08:14:02.23#ibcon#read 3, iclass 13, count 0 2006.217.08:14:02.23#ibcon#about to read 4, iclass 13, count 0 2006.217.08:14:02.23#ibcon#read 4, iclass 13, count 0 2006.217.08:14:02.23#ibcon#about to read 5, iclass 13, count 0 2006.217.08:14:02.23#ibcon#read 5, iclass 13, count 0 2006.217.08:14:02.23#ibcon#about to read 6, iclass 13, count 0 2006.217.08:14:02.23#ibcon#read 6, iclass 13, count 0 2006.217.08:14:02.23#ibcon#end of sib2, iclass 13, count 0 2006.217.08:14:02.23#ibcon#*mode == 0, iclass 13, count 0 2006.217.08:14:02.23#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.217.08:14:02.23#ibcon#[28=FRQ=06,752.99\r\n] 2006.217.08:14:02.23#ibcon#*before write, iclass 13, count 0 2006.217.08:14:02.23#ibcon#enter sib2, iclass 13, count 0 2006.217.08:14:02.23#ibcon#flushed, iclass 13, count 0 2006.217.08:14:02.23#ibcon#about to write, iclass 13, count 0 2006.217.08:14:02.23#ibcon#wrote, iclass 13, count 0 2006.217.08:14:02.23#ibcon#about to read 3, iclass 13, count 0 2006.217.08:14:02.27#ibcon#read 3, iclass 13, count 0 2006.217.08:14:02.27#ibcon#about to read 4, iclass 13, count 0 2006.217.08:14:02.27#ibcon#read 4, iclass 13, count 0 2006.217.08:14:02.27#ibcon#about to read 5, iclass 13, count 0 2006.217.08:14:02.27#ibcon#read 5, iclass 13, count 0 2006.217.08:14:02.27#ibcon#about to read 6, iclass 13, count 0 2006.217.08:14:02.27#ibcon#read 6, iclass 13, count 0 2006.217.08:14:02.27#ibcon#end of sib2, iclass 13, count 0 2006.217.08:14:02.27#ibcon#*after write, iclass 13, count 0 2006.217.08:14:02.27#ibcon#*before return 0, iclass 13, count 0 2006.217.08:14:02.27#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.217.08:14:02.27#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.217.08:14:02.27#ibcon#about to clear, iclass 13 cls_cnt 0 2006.217.08:14:02.27#ibcon#cleared, iclass 13 cls_cnt 0 2006.217.08:14:02.27$vc4f8/vb=6,4 2006.217.08:14:02.27#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.217.08:14:02.27#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.217.08:14:02.27#ibcon#ireg 11 cls_cnt 2 2006.217.08:14:02.27#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.217.08:14:02.33#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.217.08:14:02.33#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.217.08:14:02.33#ibcon#enter wrdev, iclass 15, count 2 2006.217.08:14:02.33#ibcon#first serial, iclass 15, count 2 2006.217.08:14:02.33#ibcon#enter sib2, iclass 15, count 2 2006.217.08:14:02.33#ibcon#flushed, iclass 15, count 2 2006.217.08:14:02.33#ibcon#about to write, iclass 15, count 2 2006.217.08:14:02.33#ibcon#wrote, iclass 15, count 2 2006.217.08:14:02.33#ibcon#about to read 3, iclass 15, count 2 2006.217.08:14:02.35#ibcon#read 3, iclass 15, count 2 2006.217.08:14:02.35#ibcon#about to read 4, iclass 15, count 2 2006.217.08:14:02.35#ibcon#read 4, iclass 15, count 2 2006.217.08:14:02.35#ibcon#about to read 5, iclass 15, count 2 2006.217.08:14:02.35#ibcon#read 5, iclass 15, count 2 2006.217.08:14:02.35#ibcon#about to read 6, iclass 15, count 2 2006.217.08:14:02.35#ibcon#read 6, iclass 15, count 2 2006.217.08:14:02.35#ibcon#end of sib2, iclass 15, count 2 2006.217.08:14:02.35#ibcon#*mode == 0, iclass 15, count 2 2006.217.08:14:02.35#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.217.08:14:02.35#ibcon#[27=AT06-04\r\n] 2006.217.08:14:02.35#ibcon#*before write, iclass 15, count 2 2006.217.08:14:02.35#ibcon#enter sib2, iclass 15, count 2 2006.217.08:14:02.35#ibcon#flushed, iclass 15, count 2 2006.217.08:14:02.35#ibcon#about to write, iclass 15, count 2 2006.217.08:14:02.35#ibcon#wrote, iclass 15, count 2 2006.217.08:14:02.35#ibcon#about to read 3, iclass 15, count 2 2006.217.08:14:02.38#ibcon#read 3, iclass 15, count 2 2006.217.08:14:02.38#ibcon#about to read 4, iclass 15, count 2 2006.217.08:14:02.38#ibcon#read 4, iclass 15, count 2 2006.217.08:14:02.38#ibcon#about to read 5, iclass 15, count 2 2006.217.08:14:02.38#ibcon#read 5, iclass 15, count 2 2006.217.08:14:02.38#ibcon#about to read 6, iclass 15, count 2 2006.217.08:14:02.38#ibcon#read 6, iclass 15, count 2 2006.217.08:14:02.38#ibcon#end of sib2, iclass 15, count 2 2006.217.08:14:02.38#ibcon#*after write, iclass 15, count 2 2006.217.08:14:02.38#ibcon#*before return 0, iclass 15, count 2 2006.217.08:14:02.38#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.217.08:14:02.38#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.217.08:14:02.38#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.217.08:14:02.38#ibcon#ireg 7 cls_cnt 0 2006.217.08:14:02.38#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.217.08:14:02.50#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.217.08:14:02.50#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.217.08:14:02.50#ibcon#enter wrdev, iclass 15, count 0 2006.217.08:14:02.50#ibcon#first serial, iclass 15, count 0 2006.217.08:14:02.50#ibcon#enter sib2, iclass 15, count 0 2006.217.08:14:02.50#ibcon#flushed, iclass 15, count 0 2006.217.08:14:02.50#ibcon#about to write, iclass 15, count 0 2006.217.08:14:02.50#ibcon#wrote, iclass 15, count 0 2006.217.08:14:02.50#ibcon#about to read 3, iclass 15, count 0 2006.217.08:14:02.52#ibcon#read 3, iclass 15, count 0 2006.217.08:14:02.52#ibcon#about to read 4, iclass 15, count 0 2006.217.08:14:02.52#ibcon#read 4, iclass 15, count 0 2006.217.08:14:02.52#ibcon#about to read 5, iclass 15, count 0 2006.217.08:14:02.52#ibcon#read 5, iclass 15, count 0 2006.217.08:14:02.52#ibcon#about to read 6, iclass 15, count 0 2006.217.08:14:02.52#ibcon#read 6, iclass 15, count 0 2006.217.08:14:02.52#ibcon#end of sib2, iclass 15, count 0 2006.217.08:14:02.52#ibcon#*mode == 0, iclass 15, count 0 2006.217.08:14:02.52#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.217.08:14:02.52#ibcon#[27=USB\r\n] 2006.217.08:14:02.52#ibcon#*before write, iclass 15, count 0 2006.217.08:14:02.52#ibcon#enter sib2, iclass 15, count 0 2006.217.08:14:02.52#ibcon#flushed, iclass 15, count 0 2006.217.08:14:02.52#ibcon#about to write, iclass 15, count 0 2006.217.08:14:02.52#ibcon#wrote, iclass 15, count 0 2006.217.08:14:02.52#ibcon#about to read 3, iclass 15, count 0 2006.217.08:14:02.55#ibcon#read 3, iclass 15, count 0 2006.217.08:14:02.55#ibcon#about to read 4, iclass 15, count 0 2006.217.08:14:02.55#ibcon#read 4, iclass 15, count 0 2006.217.08:14:02.55#ibcon#about to read 5, iclass 15, count 0 2006.217.08:14:02.55#ibcon#read 5, iclass 15, count 0 2006.217.08:14:02.55#ibcon#about to read 6, iclass 15, count 0 2006.217.08:14:02.55#ibcon#read 6, iclass 15, count 0 2006.217.08:14:02.55#ibcon#end of sib2, iclass 15, count 0 2006.217.08:14:02.55#ibcon#*after write, iclass 15, count 0 2006.217.08:14:02.55#ibcon#*before return 0, iclass 15, count 0 2006.217.08:14:02.55#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.217.08:14:02.55#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.217.08:14:02.55#ibcon#about to clear, iclass 15 cls_cnt 0 2006.217.08:14:02.55#ibcon#cleared, iclass 15 cls_cnt 0 2006.217.08:14:02.55$vc4f8/vabw=wide 2006.217.08:14:02.55#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.217.08:14:02.55#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.217.08:14:02.55#ibcon#ireg 8 cls_cnt 0 2006.217.08:14:02.55#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.217.08:14:02.55#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.217.08:14:02.55#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.217.08:14:02.55#ibcon#enter wrdev, iclass 17, count 0 2006.217.08:14:02.55#ibcon#first serial, iclass 17, count 0 2006.217.08:14:02.55#ibcon#enter sib2, iclass 17, count 0 2006.217.08:14:02.55#ibcon#flushed, iclass 17, count 0 2006.217.08:14:02.55#ibcon#about to write, iclass 17, count 0 2006.217.08:14:02.55#ibcon#wrote, iclass 17, count 0 2006.217.08:14:02.55#ibcon#about to read 3, iclass 17, count 0 2006.217.08:14:02.57#ibcon#read 3, iclass 17, count 0 2006.217.08:14:02.57#ibcon#about to read 4, iclass 17, count 0 2006.217.08:14:02.57#ibcon#read 4, iclass 17, count 0 2006.217.08:14:02.57#ibcon#about to read 5, iclass 17, count 0 2006.217.08:14:02.57#ibcon#read 5, iclass 17, count 0 2006.217.08:14:02.57#ibcon#about to read 6, iclass 17, count 0 2006.217.08:14:02.57#ibcon#read 6, iclass 17, count 0 2006.217.08:14:02.57#ibcon#end of sib2, iclass 17, count 0 2006.217.08:14:02.57#ibcon#*mode == 0, iclass 17, count 0 2006.217.08:14:02.57#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.217.08:14:02.57#ibcon#[25=BW32\r\n] 2006.217.08:14:02.57#ibcon#*before write, iclass 17, count 0 2006.217.08:14:02.57#ibcon#enter sib2, iclass 17, count 0 2006.217.08:14:02.57#ibcon#flushed, iclass 17, count 0 2006.217.08:14:02.57#ibcon#about to write, iclass 17, count 0 2006.217.08:14:02.57#ibcon#wrote, iclass 17, count 0 2006.217.08:14:02.57#ibcon#about to read 3, iclass 17, count 0 2006.217.08:14:02.60#ibcon#read 3, iclass 17, count 0 2006.217.08:14:02.60#ibcon#about to read 4, iclass 17, count 0 2006.217.08:14:02.60#ibcon#read 4, iclass 17, count 0 2006.217.08:14:02.60#ibcon#about to read 5, iclass 17, count 0 2006.217.08:14:02.60#ibcon#read 5, iclass 17, count 0 2006.217.08:14:02.60#ibcon#about to read 6, iclass 17, count 0 2006.217.08:14:02.60#ibcon#read 6, iclass 17, count 0 2006.217.08:14:02.60#ibcon#end of sib2, iclass 17, count 0 2006.217.08:14:02.60#ibcon#*after write, iclass 17, count 0 2006.217.08:14:02.60#ibcon#*before return 0, iclass 17, count 0 2006.217.08:14:02.60#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.217.08:14:02.60#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.217.08:14:02.60#ibcon#about to clear, iclass 17 cls_cnt 0 2006.217.08:14:02.60#ibcon#cleared, iclass 17 cls_cnt 0 2006.217.08:14:02.60$vc4f8/vbbw=wide 2006.217.08:14:02.60#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.217.08:14:02.60#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.217.08:14:02.60#ibcon#ireg 8 cls_cnt 0 2006.217.08:14:02.60#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.217.08:14:02.67#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.217.08:14:02.67#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.217.08:14:02.67#ibcon#enter wrdev, iclass 19, count 0 2006.217.08:14:02.67#ibcon#first serial, iclass 19, count 0 2006.217.08:14:02.67#ibcon#enter sib2, iclass 19, count 0 2006.217.08:14:02.67#ibcon#flushed, iclass 19, count 0 2006.217.08:14:02.67#ibcon#about to write, iclass 19, count 0 2006.217.08:14:02.67#ibcon#wrote, iclass 19, count 0 2006.217.08:14:02.67#ibcon#about to read 3, iclass 19, count 0 2006.217.08:14:02.69#ibcon#read 3, iclass 19, count 0 2006.217.08:14:02.69#ibcon#about to read 4, iclass 19, count 0 2006.217.08:14:02.69#ibcon#read 4, iclass 19, count 0 2006.217.08:14:02.69#ibcon#about to read 5, iclass 19, count 0 2006.217.08:14:02.69#ibcon#read 5, iclass 19, count 0 2006.217.08:14:02.69#ibcon#about to read 6, iclass 19, count 0 2006.217.08:14:02.69#ibcon#read 6, iclass 19, count 0 2006.217.08:14:02.69#ibcon#end of sib2, iclass 19, count 0 2006.217.08:14:02.69#ibcon#*mode == 0, iclass 19, count 0 2006.217.08:14:02.69#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.217.08:14:02.69#ibcon#[27=BW32\r\n] 2006.217.08:14:02.69#ibcon#*before write, iclass 19, count 0 2006.217.08:14:02.69#ibcon#enter sib2, iclass 19, count 0 2006.217.08:14:02.69#ibcon#flushed, iclass 19, count 0 2006.217.08:14:02.69#ibcon#about to write, iclass 19, count 0 2006.217.08:14:02.69#ibcon#wrote, iclass 19, count 0 2006.217.08:14:02.69#ibcon#about to read 3, iclass 19, count 0 2006.217.08:14:02.72#ibcon#read 3, iclass 19, count 0 2006.217.08:14:02.72#ibcon#about to read 4, iclass 19, count 0 2006.217.08:14:02.72#ibcon#read 4, iclass 19, count 0 2006.217.08:14:02.72#ibcon#about to read 5, iclass 19, count 0 2006.217.08:14:02.72#ibcon#read 5, iclass 19, count 0 2006.217.08:14:02.72#ibcon#about to read 6, iclass 19, count 0 2006.217.08:14:02.72#ibcon#read 6, iclass 19, count 0 2006.217.08:14:02.72#ibcon#end of sib2, iclass 19, count 0 2006.217.08:14:02.72#ibcon#*after write, iclass 19, count 0 2006.217.08:14:02.72#ibcon#*before return 0, iclass 19, count 0 2006.217.08:14:02.72#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.217.08:14:02.72#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.217.08:14:02.72#ibcon#about to clear, iclass 19 cls_cnt 0 2006.217.08:14:02.72#ibcon#cleared, iclass 19 cls_cnt 0 2006.217.08:14:02.72$4f8m12a/ifd4f 2006.217.08:14:02.72$ifd4f/lo= 2006.217.08:14:02.72$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.217.08:14:02.72$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.217.08:14:02.72$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.217.08:14:02.72$ifd4f/patch= 2006.217.08:14:02.72$ifd4f/patch=lo1,a1,a2,a3,a4 2006.217.08:14:02.72$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.217.08:14:02.72$ifd4f/patch=lo3,a5,a6,a7,a8 2006.217.08:14:02.72$4f8m12a/"form=m,16.000,1:2 2006.217.08:14:02.72$4f8m12a/"tpicd 2006.217.08:14:02.72$4f8m12a/echo=off 2006.217.08:14:02.72$4f8m12a/xlog=off 2006.217.08:14:02.72:!2006.217.08:14:30 2006.217.08:14:08.14#trakl#Source acquired 2006.217.08:14:09.13#flagr#flagr/antenna,acquired 2006.217.08:14:30.00:preob 2006.217.08:14:31.13/onsource/TRACKING 2006.217.08:14:31.13:!2006.217.08:14:40 2006.217.08:14:40.00:data_valid=on 2006.217.08:14:40.00:midob 2006.217.08:14:40.13/onsource/TRACKING 2006.217.08:14:40.13/wx/30.59,1008.6,64 2006.217.08:14:40.35/cable/+6.3874E-03 2006.217.08:14:41.44/va/01,05,usb,yes,31,33 2006.217.08:14:41.44/va/02,04,usb,yes,29,30 2006.217.08:14:41.44/va/03,04,usb,yes,27,28 2006.217.08:14:41.44/va/04,04,usb,yes,31,33 2006.217.08:14:41.44/va/05,07,usb,yes,32,34 2006.217.08:14:41.44/va/06,06,usb,yes,31,31 2006.217.08:14:41.44/va/07,06,usb,yes,32,32 2006.217.08:14:41.44/va/08,07,usb,yes,30,30 2006.217.08:14:41.67/valo/01,532.99,yes,locked 2006.217.08:14:41.67/valo/02,572.99,yes,locked 2006.217.08:14:41.67/valo/03,672.99,yes,locked 2006.217.08:14:41.67/valo/04,832.99,yes,locked 2006.217.08:14:41.67/valo/05,652.99,yes,locked 2006.217.08:14:41.67/valo/06,772.99,yes,locked 2006.217.08:14:41.67/valo/07,832.99,yes,locked 2006.217.08:14:41.67/valo/08,852.99,yes,locked 2006.217.08:14:42.76/vb/01,04,usb,yes,30,29 2006.217.08:14:42.76/vb/02,04,usb,yes,32,33 2006.217.08:14:42.76/vb/03,04,usb,yes,28,32 2006.217.08:14:42.76/vb/04,04,usb,yes,29,29 2006.217.08:14:42.76/vb/05,04,usb,yes,27,32 2006.217.08:14:42.76/vb/06,04,usb,yes,28,31 2006.217.08:14:42.76/vb/07,04,usb,yes,31,31 2006.217.08:14:42.76/vb/08,04,usb,yes,28,32 2006.217.08:14:43.00/vblo/01,632.99,yes,locked 2006.217.08:14:43.00/vblo/02,640.99,yes,locked 2006.217.08:14:43.00/vblo/03,656.99,yes,locked 2006.217.08:14:43.00/vblo/04,712.99,yes,locked 2006.217.08:14:43.00/vblo/05,744.99,yes,locked 2006.217.08:14:43.00/vblo/06,752.99,yes,locked 2006.217.08:14:43.00/vblo/07,734.99,yes,locked 2006.217.08:14:43.00/vblo/08,744.99,yes,locked 2006.217.08:14:43.15/vabw/8 2006.217.08:14:43.30/vbbw/8 2006.217.08:14:43.39/xfe/off,on,15.0 2006.217.08:14:43.77/ifatt/23,28,28,28 2006.217.08:14:44.07/fmout-gps/S +4.50E-07 2006.217.08:14:44.11:!2006.217.08:15:40 2006.217.08:15:40.00:data_valid=off 2006.217.08:15:40.00:postob 2006.217.08:15:40.08/cable/+6.3867E-03 2006.217.08:15:40.08/wx/30.58,1008.6,64 2006.217.08:15:41.07/fmout-gps/S +4.50E-07 2006.217.08:15:41.07:scan_name=217-0816,k06217,70 2006.217.08:15:41.07:source=1116+128,111857.30,123441.7,2000.0,ccw 2006.217.08:15:41.13#flagr#flagr/antenna,new-source 2006.217.08:15:42.13:checkk5 2006.217.08:15:42.50/chk_autoobs//k5ts1/ autoobs is running! 2006.217.08:15:42.88/chk_autoobs//k5ts2/ autoobs is running! 2006.217.08:15:43.25/chk_autoobs//k5ts3/ autoobs is running! 2006.217.08:15:43.62/chk_autoobs//k5ts4/ autoobs is running! 2006.217.08:15:43.99/chk_obsdata//k5ts1/T2170814??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.08:15:44.36/chk_obsdata//k5ts2/T2170814??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.08:15:44.74/chk_obsdata//k5ts3/T2170814??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.08:15:45.11/chk_obsdata//k5ts4/T2170814??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.08:15:45.81/k5log//k5ts1_log_newline 2006.217.08:15:46.51/k5log//k5ts2_log_newline 2006.217.08:15:47.21/k5log//k5ts3_log_newline 2006.217.08:15:47.90/k5log//k5ts4_log_newline 2006.217.08:15:47.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.217.08:15:47.92:4f8m12a=2 2006.217.08:15:47.92$4f8m12a/echo=on 2006.217.08:15:47.92$4f8m12a/pcalon 2006.217.08:15:47.92$pcalon/"no phase cal control is implemented here 2006.217.08:15:47.92$4f8m12a/"tpicd=stop 2006.217.08:15:47.92$4f8m12a/vc4f8 2006.217.08:15:47.92$vc4f8/valo=1,532.99 2006.217.08:15:47.93#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.217.08:15:47.93#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.217.08:15:47.93#ibcon#ireg 17 cls_cnt 0 2006.217.08:15:47.93#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.217.08:15:47.93#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.217.08:15:47.93#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.217.08:15:47.93#ibcon#enter wrdev, iclass 26, count 0 2006.217.08:15:47.93#ibcon#first serial, iclass 26, count 0 2006.217.08:15:47.93#ibcon#enter sib2, iclass 26, count 0 2006.217.08:15:47.93#ibcon#flushed, iclass 26, count 0 2006.217.08:15:47.93#ibcon#about to write, iclass 26, count 0 2006.217.08:15:47.93#ibcon#wrote, iclass 26, count 0 2006.217.08:15:47.93#ibcon#about to read 3, iclass 26, count 0 2006.217.08:15:47.96#ibcon#read 3, iclass 26, count 0 2006.217.08:15:47.96#ibcon#about to read 4, iclass 26, count 0 2006.217.08:15:47.96#ibcon#read 4, iclass 26, count 0 2006.217.08:15:47.96#ibcon#about to read 5, iclass 26, count 0 2006.217.08:15:47.96#ibcon#read 5, iclass 26, count 0 2006.217.08:15:47.96#ibcon#about to read 6, iclass 26, count 0 2006.217.08:15:47.96#ibcon#read 6, iclass 26, count 0 2006.217.08:15:47.96#ibcon#end of sib2, iclass 26, count 0 2006.217.08:15:47.96#ibcon#*mode == 0, iclass 26, count 0 2006.217.08:15:47.97#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.217.08:15:47.97#ibcon#[26=FRQ=01,532.99\r\n] 2006.217.08:15:47.97#ibcon#*before write, iclass 26, count 0 2006.217.08:15:47.97#ibcon#enter sib2, iclass 26, count 0 2006.217.08:15:47.97#ibcon#flushed, iclass 26, count 0 2006.217.08:15:47.97#ibcon#about to write, iclass 26, count 0 2006.217.08:15:47.97#ibcon#wrote, iclass 26, count 0 2006.217.08:15:47.97#ibcon#about to read 3, iclass 26, count 0 2006.217.08:15:48.01#ibcon#read 3, iclass 26, count 0 2006.217.08:15:48.02#ibcon#about to read 4, iclass 26, count 0 2006.217.08:15:48.02#ibcon#read 4, iclass 26, count 0 2006.217.08:15:48.02#ibcon#about to read 5, iclass 26, count 0 2006.217.08:15:48.02#ibcon#read 5, iclass 26, count 0 2006.217.08:15:48.02#ibcon#about to read 6, iclass 26, count 0 2006.217.08:15:48.02#ibcon#read 6, iclass 26, count 0 2006.217.08:15:48.02#ibcon#end of sib2, iclass 26, count 0 2006.217.08:15:48.02#ibcon#*after write, iclass 26, count 0 2006.217.08:15:48.02#ibcon#*before return 0, iclass 26, count 0 2006.217.08:15:48.02#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.217.08:15:48.02#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.217.08:15:48.02#ibcon#about to clear, iclass 26 cls_cnt 0 2006.217.08:15:48.02#ibcon#cleared, iclass 26 cls_cnt 0 2006.217.08:15:48.02$vc4f8/va=1,5 2006.217.08:15:48.02#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.217.08:15:48.02#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.217.08:15:48.02#ibcon#ireg 11 cls_cnt 2 2006.217.08:15:48.02#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.217.08:15:48.02#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.217.08:15:48.02#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.217.08:15:48.02#ibcon#enter wrdev, iclass 28, count 2 2006.217.08:15:48.02#ibcon#first serial, iclass 28, count 2 2006.217.08:15:48.02#ibcon#enter sib2, iclass 28, count 2 2006.217.08:15:48.02#ibcon#flushed, iclass 28, count 2 2006.217.08:15:48.02#ibcon#about to write, iclass 28, count 2 2006.217.08:15:48.02#ibcon#wrote, iclass 28, count 2 2006.217.08:15:48.02#ibcon#about to read 3, iclass 28, count 2 2006.217.08:15:48.04#ibcon#read 3, iclass 28, count 2 2006.217.08:15:48.04#ibcon#about to read 4, iclass 28, count 2 2006.217.08:15:48.04#ibcon#read 4, iclass 28, count 2 2006.217.08:15:48.04#ibcon#about to read 5, iclass 28, count 2 2006.217.08:15:48.04#ibcon#read 5, iclass 28, count 2 2006.217.08:15:48.04#ibcon#about to read 6, iclass 28, count 2 2006.217.08:15:48.04#ibcon#read 6, iclass 28, count 2 2006.217.08:15:48.04#ibcon#end of sib2, iclass 28, count 2 2006.217.08:15:48.04#ibcon#*mode == 0, iclass 28, count 2 2006.217.08:15:48.04#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.217.08:15:48.04#ibcon#[25=AT01-05\r\n] 2006.217.08:15:48.04#ibcon#*before write, iclass 28, count 2 2006.217.08:15:48.04#ibcon#enter sib2, iclass 28, count 2 2006.217.08:15:48.04#ibcon#flushed, iclass 28, count 2 2006.217.08:15:48.04#ibcon#about to write, iclass 28, count 2 2006.217.08:15:48.04#ibcon#wrote, iclass 28, count 2 2006.217.08:15:48.04#ibcon#about to read 3, iclass 28, count 2 2006.217.08:15:48.08#ibcon#read 3, iclass 28, count 2 2006.217.08:15:48.08#ibcon#about to read 4, iclass 28, count 2 2006.217.08:15:48.08#ibcon#read 4, iclass 28, count 2 2006.217.08:15:48.08#ibcon#about to read 5, iclass 28, count 2 2006.217.08:15:48.08#ibcon#read 5, iclass 28, count 2 2006.217.08:15:48.08#ibcon#about to read 6, iclass 28, count 2 2006.217.08:15:48.08#ibcon#read 6, iclass 28, count 2 2006.217.08:15:48.08#ibcon#end of sib2, iclass 28, count 2 2006.217.08:15:48.08#ibcon#*after write, iclass 28, count 2 2006.217.08:15:48.08#ibcon#*before return 0, iclass 28, count 2 2006.217.08:15:48.08#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.217.08:15:48.08#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.217.08:15:48.08#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.217.08:15:48.08#ibcon#ireg 7 cls_cnt 0 2006.217.08:15:48.08#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.217.08:15:48.19#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.217.08:15:48.19#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.217.08:15:48.20#ibcon#enter wrdev, iclass 28, count 0 2006.217.08:15:48.20#ibcon#first serial, iclass 28, count 0 2006.217.08:15:48.20#ibcon#enter sib2, iclass 28, count 0 2006.217.08:15:48.20#ibcon#flushed, iclass 28, count 0 2006.217.08:15:48.20#ibcon#about to write, iclass 28, count 0 2006.217.08:15:48.20#ibcon#wrote, iclass 28, count 0 2006.217.08:15:48.20#ibcon#about to read 3, iclass 28, count 0 2006.217.08:15:48.23#ibcon#read 3, iclass 28, count 0 2006.217.08:15:48.23#ibcon#about to read 4, iclass 28, count 0 2006.217.08:15:48.23#ibcon#read 4, iclass 28, count 0 2006.217.08:15:48.23#ibcon#about to read 5, iclass 28, count 0 2006.217.08:15:48.23#ibcon#read 5, iclass 28, count 0 2006.217.08:15:48.23#ibcon#about to read 6, iclass 28, count 0 2006.217.08:15:48.23#ibcon#read 6, iclass 28, count 0 2006.217.08:15:48.23#ibcon#end of sib2, iclass 28, count 0 2006.217.08:15:48.23#ibcon#*mode == 0, iclass 28, count 0 2006.217.08:15:48.23#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.217.08:15:48.23#ibcon#[25=USB\r\n] 2006.217.08:15:48.23#ibcon#*before write, iclass 28, count 0 2006.217.08:15:48.23#ibcon#enter sib2, iclass 28, count 0 2006.217.08:15:48.23#ibcon#flushed, iclass 28, count 0 2006.217.08:15:48.23#ibcon#about to write, iclass 28, count 0 2006.217.08:15:48.23#ibcon#wrote, iclass 28, count 0 2006.217.08:15:48.23#ibcon#about to read 3, iclass 28, count 0 2006.217.08:15:48.25#ibcon#read 3, iclass 28, count 0 2006.217.08:15:48.26#ibcon#about to read 4, iclass 28, count 0 2006.217.08:15:48.26#ibcon#read 4, iclass 28, count 0 2006.217.08:15:48.26#ibcon#about to read 5, iclass 28, count 0 2006.217.08:15:48.26#ibcon#read 5, iclass 28, count 0 2006.217.08:15:48.26#ibcon#about to read 6, iclass 28, count 0 2006.217.08:15:48.26#ibcon#read 6, iclass 28, count 0 2006.217.08:15:48.26#ibcon#end of sib2, iclass 28, count 0 2006.217.08:15:48.26#ibcon#*after write, iclass 28, count 0 2006.217.08:15:48.26#ibcon#*before return 0, iclass 28, count 0 2006.217.08:15:48.26#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.217.08:15:48.26#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.217.08:15:48.26#ibcon#about to clear, iclass 28 cls_cnt 0 2006.217.08:15:48.26#ibcon#cleared, iclass 28 cls_cnt 0 2006.217.08:15:48.26$vc4f8/valo=2,572.99 2006.217.08:15:48.26#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.217.08:15:48.26#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.217.08:15:48.26#ibcon#ireg 17 cls_cnt 0 2006.217.08:15:48.26#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.217.08:15:48.26#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.217.08:15:48.26#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.217.08:15:48.26#ibcon#enter wrdev, iclass 30, count 0 2006.217.08:15:48.26#ibcon#first serial, iclass 30, count 0 2006.217.08:15:48.26#ibcon#enter sib2, iclass 30, count 0 2006.217.08:15:48.26#ibcon#flushed, iclass 30, count 0 2006.217.08:15:48.26#ibcon#about to write, iclass 30, count 0 2006.217.08:15:48.26#ibcon#wrote, iclass 30, count 0 2006.217.08:15:48.26#ibcon#about to read 3, iclass 30, count 0 2006.217.08:15:48.27#ibcon#read 3, iclass 30, count 0 2006.217.08:15:48.28#ibcon#about to read 4, iclass 30, count 0 2006.217.08:15:48.28#ibcon#read 4, iclass 30, count 0 2006.217.08:15:48.28#ibcon#about to read 5, iclass 30, count 0 2006.217.08:15:48.28#ibcon#read 5, iclass 30, count 0 2006.217.08:15:48.28#ibcon#about to read 6, iclass 30, count 0 2006.217.08:15:48.28#ibcon#read 6, iclass 30, count 0 2006.217.08:15:48.28#ibcon#end of sib2, iclass 30, count 0 2006.217.08:15:48.28#ibcon#*mode == 0, iclass 30, count 0 2006.217.08:15:48.28#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.217.08:15:48.28#ibcon#[26=FRQ=02,572.99\r\n] 2006.217.08:15:48.28#ibcon#*before write, iclass 30, count 0 2006.217.08:15:48.28#ibcon#enter sib2, iclass 30, count 0 2006.217.08:15:48.28#ibcon#flushed, iclass 30, count 0 2006.217.08:15:48.28#ibcon#about to write, iclass 30, count 0 2006.217.08:15:48.28#ibcon#wrote, iclass 30, count 0 2006.217.08:15:48.28#ibcon#about to read 3, iclass 30, count 0 2006.217.08:15:48.32#ibcon#read 3, iclass 30, count 0 2006.217.08:15:48.32#ibcon#about to read 4, iclass 30, count 0 2006.217.08:15:48.32#ibcon#read 4, iclass 30, count 0 2006.217.08:15:48.32#ibcon#about to read 5, iclass 30, count 0 2006.217.08:15:48.32#ibcon#read 5, iclass 30, count 0 2006.217.08:15:48.32#ibcon#about to read 6, iclass 30, count 0 2006.217.08:15:48.32#ibcon#read 6, iclass 30, count 0 2006.217.08:15:48.32#ibcon#end of sib2, iclass 30, count 0 2006.217.08:15:48.32#ibcon#*after write, iclass 30, count 0 2006.217.08:15:48.32#ibcon#*before return 0, iclass 30, count 0 2006.217.08:15:48.32#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.217.08:15:48.32#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.217.08:15:48.32#ibcon#about to clear, iclass 30 cls_cnt 0 2006.217.08:15:48.32#ibcon#cleared, iclass 30 cls_cnt 0 2006.217.08:15:48.32$vc4f8/va=2,4 2006.217.08:15:48.32#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.217.08:15:48.32#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.217.08:15:48.32#ibcon#ireg 11 cls_cnt 2 2006.217.08:15:48.32#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.217.08:15:48.37#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.217.08:15:48.38#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.217.08:15:48.38#ibcon#enter wrdev, iclass 32, count 2 2006.217.08:15:48.38#ibcon#first serial, iclass 32, count 2 2006.217.08:15:48.38#ibcon#enter sib2, iclass 32, count 2 2006.217.08:15:48.38#ibcon#flushed, iclass 32, count 2 2006.217.08:15:48.38#ibcon#about to write, iclass 32, count 2 2006.217.08:15:48.38#ibcon#wrote, iclass 32, count 2 2006.217.08:15:48.38#ibcon#about to read 3, iclass 32, count 2 2006.217.08:15:48.40#ibcon#read 3, iclass 32, count 2 2006.217.08:15:48.40#ibcon#about to read 4, iclass 32, count 2 2006.217.08:15:48.40#ibcon#read 4, iclass 32, count 2 2006.217.08:15:48.40#ibcon#about to read 5, iclass 32, count 2 2006.217.08:15:48.40#ibcon#read 5, iclass 32, count 2 2006.217.08:15:48.40#ibcon#about to read 6, iclass 32, count 2 2006.217.08:15:48.40#ibcon#read 6, iclass 32, count 2 2006.217.08:15:48.40#ibcon#end of sib2, iclass 32, count 2 2006.217.08:15:48.40#ibcon#*mode == 0, iclass 32, count 2 2006.217.08:15:48.40#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.217.08:15:48.40#ibcon#[25=AT02-04\r\n] 2006.217.08:15:48.40#ibcon#*before write, iclass 32, count 2 2006.217.08:15:48.40#ibcon#enter sib2, iclass 32, count 2 2006.217.08:15:48.40#ibcon#flushed, iclass 32, count 2 2006.217.08:15:48.40#ibcon#about to write, iclass 32, count 2 2006.217.08:15:48.40#ibcon#wrote, iclass 32, count 2 2006.217.08:15:48.40#ibcon#about to read 3, iclass 32, count 2 2006.217.08:15:48.43#ibcon#read 3, iclass 32, count 2 2006.217.08:15:48.43#ibcon#about to read 4, iclass 32, count 2 2006.217.08:15:48.43#ibcon#read 4, iclass 32, count 2 2006.217.08:15:48.43#ibcon#about to read 5, iclass 32, count 2 2006.217.08:15:48.43#ibcon#read 5, iclass 32, count 2 2006.217.08:15:48.43#ibcon#about to read 6, iclass 32, count 2 2006.217.08:15:48.43#ibcon#read 6, iclass 32, count 2 2006.217.08:15:48.43#ibcon#end of sib2, iclass 32, count 2 2006.217.08:15:48.43#ibcon#*after write, iclass 32, count 2 2006.217.08:15:48.43#ibcon#*before return 0, iclass 32, count 2 2006.217.08:15:48.43#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.217.08:15:48.43#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.217.08:15:48.43#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.217.08:15:48.43#ibcon#ireg 7 cls_cnt 0 2006.217.08:15:48.43#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.217.08:15:48.54#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.217.08:15:48.54#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.217.08:15:48.55#ibcon#enter wrdev, iclass 32, count 0 2006.217.08:15:48.55#ibcon#first serial, iclass 32, count 0 2006.217.08:15:48.55#ibcon#enter sib2, iclass 32, count 0 2006.217.08:15:48.55#ibcon#flushed, iclass 32, count 0 2006.217.08:15:48.55#ibcon#about to write, iclass 32, count 0 2006.217.08:15:48.55#ibcon#wrote, iclass 32, count 0 2006.217.08:15:48.55#ibcon#about to read 3, iclass 32, count 0 2006.217.08:15:48.56#ibcon#read 3, iclass 32, count 0 2006.217.08:15:48.57#ibcon#about to read 4, iclass 32, count 0 2006.217.08:15:48.57#ibcon#read 4, iclass 32, count 0 2006.217.08:15:48.57#ibcon#about to read 5, iclass 32, count 0 2006.217.08:15:48.57#ibcon#read 5, iclass 32, count 0 2006.217.08:15:48.57#ibcon#about to read 6, iclass 32, count 0 2006.217.08:15:48.57#ibcon#read 6, iclass 32, count 0 2006.217.08:15:48.57#ibcon#end of sib2, iclass 32, count 0 2006.217.08:15:48.57#ibcon#*mode == 0, iclass 32, count 0 2006.217.08:15:48.57#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.217.08:15:48.57#ibcon#[25=USB\r\n] 2006.217.08:15:48.57#ibcon#*before write, iclass 32, count 0 2006.217.08:15:48.57#ibcon#enter sib2, iclass 32, count 0 2006.217.08:15:48.57#ibcon#flushed, iclass 32, count 0 2006.217.08:15:48.57#ibcon#about to write, iclass 32, count 0 2006.217.08:15:48.57#ibcon#wrote, iclass 32, count 0 2006.217.08:15:48.57#ibcon#about to read 3, iclass 32, count 0 2006.217.08:15:48.59#ibcon#read 3, iclass 32, count 0 2006.217.08:15:48.60#ibcon#about to read 4, iclass 32, count 0 2006.217.08:15:48.60#ibcon#read 4, iclass 32, count 0 2006.217.08:15:48.60#ibcon#about to read 5, iclass 32, count 0 2006.217.08:15:48.60#ibcon#read 5, iclass 32, count 0 2006.217.08:15:48.60#ibcon#about to read 6, iclass 32, count 0 2006.217.08:15:48.60#ibcon#read 6, iclass 32, count 0 2006.217.08:15:48.60#ibcon#end of sib2, iclass 32, count 0 2006.217.08:15:48.60#ibcon#*after write, iclass 32, count 0 2006.217.08:15:48.60#ibcon#*before return 0, iclass 32, count 0 2006.217.08:15:48.60#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.217.08:15:48.60#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.217.08:15:48.60#ibcon#about to clear, iclass 32 cls_cnt 0 2006.217.08:15:48.60#ibcon#cleared, iclass 32 cls_cnt 0 2006.217.08:15:48.60$vc4f8/valo=3,672.99 2006.217.08:15:48.60#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.217.08:15:48.60#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.217.08:15:48.60#ibcon#ireg 17 cls_cnt 0 2006.217.08:15:48.60#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.217.08:15:48.60#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.217.08:15:48.60#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.217.08:15:48.60#ibcon#enter wrdev, iclass 34, count 0 2006.217.08:15:48.60#ibcon#first serial, iclass 34, count 0 2006.217.08:15:48.60#ibcon#enter sib2, iclass 34, count 0 2006.217.08:15:48.60#ibcon#flushed, iclass 34, count 0 2006.217.08:15:48.60#ibcon#about to write, iclass 34, count 0 2006.217.08:15:48.60#ibcon#wrote, iclass 34, count 0 2006.217.08:15:48.60#ibcon#about to read 3, iclass 34, count 0 2006.217.08:15:48.62#ibcon#read 3, iclass 34, count 0 2006.217.08:15:48.62#ibcon#about to read 4, iclass 34, count 0 2006.217.08:15:48.62#ibcon#read 4, iclass 34, count 0 2006.217.08:15:48.62#ibcon#about to read 5, iclass 34, count 0 2006.217.08:15:48.62#ibcon#read 5, iclass 34, count 0 2006.217.08:15:48.62#ibcon#about to read 6, iclass 34, count 0 2006.217.08:15:48.62#ibcon#read 6, iclass 34, count 0 2006.217.08:15:48.62#ibcon#end of sib2, iclass 34, count 0 2006.217.08:15:48.62#ibcon#*mode == 0, iclass 34, count 0 2006.217.08:15:48.62#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.217.08:15:48.62#ibcon#[26=FRQ=03,672.99\r\n] 2006.217.08:15:48.62#ibcon#*before write, iclass 34, count 0 2006.217.08:15:48.62#ibcon#enter sib2, iclass 34, count 0 2006.217.08:15:48.62#ibcon#flushed, iclass 34, count 0 2006.217.08:15:48.62#ibcon#about to write, iclass 34, count 0 2006.217.08:15:48.62#ibcon#wrote, iclass 34, count 0 2006.217.08:15:48.62#ibcon#about to read 3, iclass 34, count 0 2006.217.08:15:48.67#ibcon#read 3, iclass 34, count 0 2006.217.08:15:48.67#ibcon#about to read 4, iclass 34, count 0 2006.217.08:15:48.67#ibcon#read 4, iclass 34, count 0 2006.217.08:15:48.67#ibcon#about to read 5, iclass 34, count 0 2006.217.08:15:48.67#ibcon#read 5, iclass 34, count 0 2006.217.08:15:48.67#ibcon#about to read 6, iclass 34, count 0 2006.217.08:15:48.67#ibcon#read 6, iclass 34, count 0 2006.217.08:15:48.67#ibcon#end of sib2, iclass 34, count 0 2006.217.08:15:48.67#ibcon#*after write, iclass 34, count 0 2006.217.08:15:48.67#ibcon#*before return 0, iclass 34, count 0 2006.217.08:15:48.67#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.217.08:15:48.67#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.217.08:15:48.67#ibcon#about to clear, iclass 34 cls_cnt 0 2006.217.08:15:48.67#ibcon#cleared, iclass 34 cls_cnt 0 2006.217.08:15:48.67$vc4f8/va=3,4 2006.217.08:15:48.67#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.217.08:15:48.67#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.217.08:15:48.67#ibcon#ireg 11 cls_cnt 2 2006.217.08:15:48.67#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.217.08:15:48.72#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.217.08:15:48.72#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.217.08:15:48.72#ibcon#enter wrdev, iclass 36, count 2 2006.217.08:15:48.72#ibcon#first serial, iclass 36, count 2 2006.217.08:15:48.72#ibcon#enter sib2, iclass 36, count 2 2006.217.08:15:48.72#ibcon#flushed, iclass 36, count 2 2006.217.08:15:48.72#ibcon#about to write, iclass 36, count 2 2006.217.08:15:48.72#ibcon#wrote, iclass 36, count 2 2006.217.08:15:48.72#ibcon#about to read 3, iclass 36, count 2 2006.217.08:15:48.74#ibcon#read 3, iclass 36, count 2 2006.217.08:15:48.74#ibcon#about to read 4, iclass 36, count 2 2006.217.08:15:48.74#ibcon#read 4, iclass 36, count 2 2006.217.08:15:48.74#ibcon#about to read 5, iclass 36, count 2 2006.217.08:15:48.74#ibcon#read 5, iclass 36, count 2 2006.217.08:15:48.74#ibcon#about to read 6, iclass 36, count 2 2006.217.08:15:48.74#ibcon#read 6, iclass 36, count 2 2006.217.08:15:48.74#ibcon#end of sib2, iclass 36, count 2 2006.217.08:15:48.74#ibcon#*mode == 0, iclass 36, count 2 2006.217.08:15:48.74#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.217.08:15:48.74#ibcon#[25=AT03-04\r\n] 2006.217.08:15:48.74#ibcon#*before write, iclass 36, count 2 2006.217.08:15:48.74#ibcon#enter sib2, iclass 36, count 2 2006.217.08:15:48.74#ibcon#flushed, iclass 36, count 2 2006.217.08:15:48.74#ibcon#about to write, iclass 36, count 2 2006.217.08:15:48.74#ibcon#wrote, iclass 36, count 2 2006.217.08:15:48.74#ibcon#about to read 3, iclass 36, count 2 2006.217.08:15:48.77#ibcon#read 3, iclass 36, count 2 2006.217.08:15:48.77#ibcon#about to read 4, iclass 36, count 2 2006.217.08:15:48.77#ibcon#read 4, iclass 36, count 2 2006.217.08:15:48.77#ibcon#about to read 5, iclass 36, count 2 2006.217.08:15:48.77#ibcon#read 5, iclass 36, count 2 2006.217.08:15:48.77#ibcon#about to read 6, iclass 36, count 2 2006.217.08:15:48.77#ibcon#read 6, iclass 36, count 2 2006.217.08:15:48.77#ibcon#end of sib2, iclass 36, count 2 2006.217.08:15:48.77#ibcon#*after write, iclass 36, count 2 2006.217.08:15:48.77#ibcon#*before return 0, iclass 36, count 2 2006.217.08:15:48.77#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.217.08:15:48.77#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.217.08:15:48.77#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.217.08:15:48.77#ibcon#ireg 7 cls_cnt 0 2006.217.08:15:48.77#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.217.08:15:48.88#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.217.08:15:48.88#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.217.08:15:48.89#ibcon#enter wrdev, iclass 36, count 0 2006.217.08:15:48.89#ibcon#first serial, iclass 36, count 0 2006.217.08:15:48.89#ibcon#enter sib2, iclass 36, count 0 2006.217.08:15:48.89#ibcon#flushed, iclass 36, count 0 2006.217.08:15:48.89#ibcon#about to write, iclass 36, count 0 2006.217.08:15:48.89#ibcon#wrote, iclass 36, count 0 2006.217.08:15:48.89#ibcon#about to read 3, iclass 36, count 0 2006.217.08:15:48.90#ibcon#read 3, iclass 36, count 0 2006.217.08:15:48.91#ibcon#about to read 4, iclass 36, count 0 2006.217.08:15:48.91#ibcon#read 4, iclass 36, count 0 2006.217.08:15:48.91#ibcon#about to read 5, iclass 36, count 0 2006.217.08:15:48.91#ibcon#read 5, iclass 36, count 0 2006.217.08:15:48.91#ibcon#about to read 6, iclass 36, count 0 2006.217.08:15:48.91#ibcon#read 6, iclass 36, count 0 2006.217.08:15:48.91#ibcon#end of sib2, iclass 36, count 0 2006.217.08:15:48.91#ibcon#*mode == 0, iclass 36, count 0 2006.217.08:15:48.91#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.217.08:15:48.91#ibcon#[25=USB\r\n] 2006.217.08:15:48.91#ibcon#*before write, iclass 36, count 0 2006.217.08:15:48.91#ibcon#enter sib2, iclass 36, count 0 2006.217.08:15:48.91#ibcon#flushed, iclass 36, count 0 2006.217.08:15:48.91#ibcon#about to write, iclass 36, count 0 2006.217.08:15:48.91#ibcon#wrote, iclass 36, count 0 2006.217.08:15:48.91#ibcon#about to read 3, iclass 36, count 0 2006.217.08:15:48.93#ibcon#read 3, iclass 36, count 0 2006.217.08:15:48.94#ibcon#about to read 4, iclass 36, count 0 2006.217.08:15:48.94#ibcon#read 4, iclass 36, count 0 2006.217.08:15:48.94#ibcon#about to read 5, iclass 36, count 0 2006.217.08:15:48.94#ibcon#read 5, iclass 36, count 0 2006.217.08:15:48.94#ibcon#about to read 6, iclass 36, count 0 2006.217.08:15:48.94#ibcon#read 6, iclass 36, count 0 2006.217.08:15:48.94#ibcon#end of sib2, iclass 36, count 0 2006.217.08:15:48.94#ibcon#*after write, iclass 36, count 0 2006.217.08:15:48.94#ibcon#*before return 0, iclass 36, count 0 2006.217.08:15:48.94#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.217.08:15:48.94#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.217.08:15:48.94#ibcon#about to clear, iclass 36 cls_cnt 0 2006.217.08:15:48.94#ibcon#cleared, iclass 36 cls_cnt 0 2006.217.08:15:48.94$vc4f8/valo=4,832.99 2006.217.08:15:48.94#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.217.08:15:48.94#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.217.08:15:48.94#ibcon#ireg 17 cls_cnt 0 2006.217.08:15:48.94#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.217.08:15:48.94#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.217.08:15:48.94#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.217.08:15:48.94#ibcon#enter wrdev, iclass 38, count 0 2006.217.08:15:48.94#ibcon#first serial, iclass 38, count 0 2006.217.08:15:48.94#ibcon#enter sib2, iclass 38, count 0 2006.217.08:15:48.94#ibcon#flushed, iclass 38, count 0 2006.217.08:15:48.94#ibcon#about to write, iclass 38, count 0 2006.217.08:15:48.94#ibcon#wrote, iclass 38, count 0 2006.217.08:15:48.94#ibcon#about to read 3, iclass 38, count 0 2006.217.08:15:48.95#ibcon#read 3, iclass 38, count 0 2006.217.08:15:48.96#ibcon#about to read 4, iclass 38, count 0 2006.217.08:15:48.96#ibcon#read 4, iclass 38, count 0 2006.217.08:15:48.96#ibcon#about to read 5, iclass 38, count 0 2006.217.08:15:48.96#ibcon#read 5, iclass 38, count 0 2006.217.08:15:48.96#ibcon#about to read 6, iclass 38, count 0 2006.217.08:15:48.96#ibcon#read 6, iclass 38, count 0 2006.217.08:15:48.96#ibcon#end of sib2, iclass 38, count 0 2006.217.08:15:48.96#ibcon#*mode == 0, iclass 38, count 0 2006.217.08:15:48.96#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.217.08:15:48.96#ibcon#[26=FRQ=04,832.99\r\n] 2006.217.08:15:48.96#ibcon#*before write, iclass 38, count 0 2006.217.08:15:48.96#ibcon#enter sib2, iclass 38, count 0 2006.217.08:15:48.96#ibcon#flushed, iclass 38, count 0 2006.217.08:15:48.96#ibcon#about to write, iclass 38, count 0 2006.217.08:15:48.96#ibcon#wrote, iclass 38, count 0 2006.217.08:15:48.96#ibcon#about to read 3, iclass 38, count 0 2006.217.08:15:49.00#ibcon#read 3, iclass 38, count 0 2006.217.08:15:49.00#ibcon#about to read 4, iclass 38, count 0 2006.217.08:15:49.00#ibcon#read 4, iclass 38, count 0 2006.217.08:15:49.00#ibcon#about to read 5, iclass 38, count 0 2006.217.08:15:49.00#ibcon#read 5, iclass 38, count 0 2006.217.08:15:49.00#ibcon#about to read 6, iclass 38, count 0 2006.217.08:15:49.00#ibcon#read 6, iclass 38, count 0 2006.217.08:15:49.00#ibcon#end of sib2, iclass 38, count 0 2006.217.08:15:49.00#ibcon#*after write, iclass 38, count 0 2006.217.08:15:49.00#ibcon#*before return 0, iclass 38, count 0 2006.217.08:15:49.00#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.217.08:15:49.00#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.217.08:15:49.00#ibcon#about to clear, iclass 38 cls_cnt 0 2006.217.08:15:49.00#ibcon#cleared, iclass 38 cls_cnt 0 2006.217.08:15:49.00$vc4f8/va=4,4 2006.217.08:15:49.00#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.217.08:15:49.00#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.217.08:15:49.00#ibcon#ireg 11 cls_cnt 2 2006.217.08:15:49.00#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.217.08:15:49.05#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.217.08:15:49.06#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.217.08:15:49.06#ibcon#enter wrdev, iclass 40, count 2 2006.217.08:15:49.06#ibcon#first serial, iclass 40, count 2 2006.217.08:15:49.06#ibcon#enter sib2, iclass 40, count 2 2006.217.08:15:49.06#ibcon#flushed, iclass 40, count 2 2006.217.08:15:49.06#ibcon#about to write, iclass 40, count 2 2006.217.08:15:49.06#ibcon#wrote, iclass 40, count 2 2006.217.08:15:49.06#ibcon#about to read 3, iclass 40, count 2 2006.217.08:15:49.07#ibcon#read 3, iclass 40, count 2 2006.217.08:15:49.08#ibcon#about to read 4, iclass 40, count 2 2006.217.08:15:49.08#ibcon#read 4, iclass 40, count 2 2006.217.08:15:49.08#ibcon#about to read 5, iclass 40, count 2 2006.217.08:15:49.08#ibcon#read 5, iclass 40, count 2 2006.217.08:15:49.08#ibcon#about to read 6, iclass 40, count 2 2006.217.08:15:49.08#ibcon#read 6, iclass 40, count 2 2006.217.08:15:49.08#ibcon#end of sib2, iclass 40, count 2 2006.217.08:15:49.08#ibcon#*mode == 0, iclass 40, count 2 2006.217.08:15:49.08#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.217.08:15:49.08#ibcon#[25=AT04-04\r\n] 2006.217.08:15:49.08#ibcon#*before write, iclass 40, count 2 2006.217.08:15:49.08#ibcon#enter sib2, iclass 40, count 2 2006.217.08:15:49.08#ibcon#flushed, iclass 40, count 2 2006.217.08:15:49.08#ibcon#about to write, iclass 40, count 2 2006.217.08:15:49.08#ibcon#wrote, iclass 40, count 2 2006.217.08:15:49.08#ibcon#about to read 3, iclass 40, count 2 2006.217.08:15:49.11#ibcon#read 3, iclass 40, count 2 2006.217.08:15:49.11#ibcon#about to read 4, iclass 40, count 2 2006.217.08:15:49.11#ibcon#read 4, iclass 40, count 2 2006.217.08:15:49.11#ibcon#about to read 5, iclass 40, count 2 2006.217.08:15:49.11#ibcon#read 5, iclass 40, count 2 2006.217.08:15:49.11#ibcon#about to read 6, iclass 40, count 2 2006.217.08:15:49.11#ibcon#read 6, iclass 40, count 2 2006.217.08:15:49.11#ibcon#end of sib2, iclass 40, count 2 2006.217.08:15:49.11#ibcon#*after write, iclass 40, count 2 2006.217.08:15:49.11#ibcon#*before return 0, iclass 40, count 2 2006.217.08:15:49.11#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.217.08:15:49.11#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.217.08:15:49.11#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.217.08:15:49.11#ibcon#ireg 7 cls_cnt 0 2006.217.08:15:49.11#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.217.08:15:49.23#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.217.08:15:49.23#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.217.08:15:49.23#ibcon#enter wrdev, iclass 40, count 0 2006.217.08:15:49.23#ibcon#first serial, iclass 40, count 0 2006.217.08:15:49.23#ibcon#enter sib2, iclass 40, count 0 2006.217.08:15:49.23#ibcon#flushed, iclass 40, count 0 2006.217.08:15:49.23#ibcon#about to write, iclass 40, count 0 2006.217.08:15:49.23#ibcon#wrote, iclass 40, count 0 2006.217.08:15:49.23#ibcon#about to read 3, iclass 40, count 0 2006.217.08:15:49.24#ibcon#read 3, iclass 40, count 0 2006.217.08:15:49.25#ibcon#about to read 4, iclass 40, count 0 2006.217.08:15:49.25#ibcon#read 4, iclass 40, count 0 2006.217.08:15:49.25#ibcon#about to read 5, iclass 40, count 0 2006.217.08:15:49.25#ibcon#read 5, iclass 40, count 0 2006.217.08:15:49.25#ibcon#about to read 6, iclass 40, count 0 2006.217.08:15:49.25#ibcon#read 6, iclass 40, count 0 2006.217.08:15:49.25#ibcon#end of sib2, iclass 40, count 0 2006.217.08:15:49.25#ibcon#*mode == 0, iclass 40, count 0 2006.217.08:15:49.25#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.217.08:15:49.25#ibcon#[25=USB\r\n] 2006.217.08:15:49.25#ibcon#*before write, iclass 40, count 0 2006.217.08:15:49.25#ibcon#enter sib2, iclass 40, count 0 2006.217.08:15:49.25#ibcon#flushed, iclass 40, count 0 2006.217.08:15:49.25#ibcon#about to write, iclass 40, count 0 2006.217.08:15:49.25#ibcon#wrote, iclass 40, count 0 2006.217.08:15:49.25#ibcon#about to read 3, iclass 40, count 0 2006.217.08:15:49.27#ibcon#read 3, iclass 40, count 0 2006.217.08:15:49.28#ibcon#about to read 4, iclass 40, count 0 2006.217.08:15:49.28#ibcon#read 4, iclass 40, count 0 2006.217.08:15:49.28#ibcon#about to read 5, iclass 40, count 0 2006.217.08:15:49.28#ibcon#read 5, iclass 40, count 0 2006.217.08:15:49.28#ibcon#about to read 6, iclass 40, count 0 2006.217.08:15:49.28#ibcon#read 6, iclass 40, count 0 2006.217.08:15:49.28#ibcon#end of sib2, iclass 40, count 0 2006.217.08:15:49.28#ibcon#*after write, iclass 40, count 0 2006.217.08:15:49.28#ibcon#*before return 0, iclass 40, count 0 2006.217.08:15:49.28#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.217.08:15:49.28#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.217.08:15:49.28#ibcon#about to clear, iclass 40 cls_cnt 0 2006.217.08:15:49.28#ibcon#cleared, iclass 40 cls_cnt 0 2006.217.08:15:49.28$vc4f8/valo=5,652.99 2006.217.08:15:49.28#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.217.08:15:49.28#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.217.08:15:49.28#ibcon#ireg 17 cls_cnt 0 2006.217.08:15:49.28#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.217.08:15:49.28#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.217.08:15:49.28#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.217.08:15:49.28#ibcon#enter wrdev, iclass 4, count 0 2006.217.08:15:49.28#ibcon#first serial, iclass 4, count 0 2006.217.08:15:49.28#ibcon#enter sib2, iclass 4, count 0 2006.217.08:15:49.28#ibcon#flushed, iclass 4, count 0 2006.217.08:15:49.28#ibcon#about to write, iclass 4, count 0 2006.217.08:15:49.28#ibcon#wrote, iclass 4, count 0 2006.217.08:15:49.28#ibcon#about to read 3, iclass 4, count 0 2006.217.08:15:49.29#ibcon#read 3, iclass 4, count 0 2006.217.08:15:49.30#ibcon#about to read 4, iclass 4, count 0 2006.217.08:15:49.30#ibcon#read 4, iclass 4, count 0 2006.217.08:15:49.30#ibcon#about to read 5, iclass 4, count 0 2006.217.08:15:49.30#ibcon#read 5, iclass 4, count 0 2006.217.08:15:49.30#ibcon#about to read 6, iclass 4, count 0 2006.217.08:15:49.30#ibcon#read 6, iclass 4, count 0 2006.217.08:15:49.30#ibcon#end of sib2, iclass 4, count 0 2006.217.08:15:49.30#ibcon#*mode == 0, iclass 4, count 0 2006.217.08:15:49.30#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.217.08:15:49.30#ibcon#[26=FRQ=05,652.99\r\n] 2006.217.08:15:49.30#ibcon#*before write, iclass 4, count 0 2006.217.08:15:49.30#ibcon#enter sib2, iclass 4, count 0 2006.217.08:15:49.30#ibcon#flushed, iclass 4, count 0 2006.217.08:15:49.30#ibcon#about to write, iclass 4, count 0 2006.217.08:15:49.30#ibcon#wrote, iclass 4, count 0 2006.217.08:15:49.30#ibcon#about to read 3, iclass 4, count 0 2006.217.08:15:49.33#ibcon#read 3, iclass 4, count 0 2006.217.08:15:49.34#ibcon#about to read 4, iclass 4, count 0 2006.217.08:15:49.34#ibcon#read 4, iclass 4, count 0 2006.217.08:15:49.34#ibcon#about to read 5, iclass 4, count 0 2006.217.08:15:49.34#ibcon#read 5, iclass 4, count 0 2006.217.08:15:49.34#ibcon#about to read 6, iclass 4, count 0 2006.217.08:15:49.34#ibcon#read 6, iclass 4, count 0 2006.217.08:15:49.34#ibcon#end of sib2, iclass 4, count 0 2006.217.08:15:49.34#ibcon#*after write, iclass 4, count 0 2006.217.08:15:49.34#ibcon#*before return 0, iclass 4, count 0 2006.217.08:15:49.34#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.217.08:15:49.34#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.217.08:15:49.34#ibcon#about to clear, iclass 4 cls_cnt 0 2006.217.08:15:49.34#ibcon#cleared, iclass 4 cls_cnt 0 2006.217.08:15:49.34$vc4f8/va=5,7 2006.217.08:15:49.34#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.217.08:15:49.34#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.217.08:15:49.34#ibcon#ireg 11 cls_cnt 2 2006.217.08:15:49.34#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.217.08:15:49.39#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.217.08:15:49.40#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.217.08:15:49.40#ibcon#enter wrdev, iclass 6, count 2 2006.217.08:15:49.40#ibcon#first serial, iclass 6, count 2 2006.217.08:15:49.40#ibcon#enter sib2, iclass 6, count 2 2006.217.08:15:49.40#ibcon#flushed, iclass 6, count 2 2006.217.08:15:49.40#ibcon#about to write, iclass 6, count 2 2006.217.08:15:49.40#ibcon#wrote, iclass 6, count 2 2006.217.08:15:49.40#ibcon#about to read 3, iclass 6, count 2 2006.217.08:15:49.41#ibcon#read 3, iclass 6, count 2 2006.217.08:15:49.42#ibcon#about to read 4, iclass 6, count 2 2006.217.08:15:49.42#ibcon#read 4, iclass 6, count 2 2006.217.08:15:49.42#ibcon#about to read 5, iclass 6, count 2 2006.217.08:15:49.42#ibcon#read 5, iclass 6, count 2 2006.217.08:15:49.42#ibcon#about to read 6, iclass 6, count 2 2006.217.08:15:49.42#ibcon#read 6, iclass 6, count 2 2006.217.08:15:49.42#ibcon#end of sib2, iclass 6, count 2 2006.217.08:15:49.42#ibcon#*mode == 0, iclass 6, count 2 2006.217.08:15:49.42#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.217.08:15:49.42#ibcon#[25=AT05-07\r\n] 2006.217.08:15:49.42#ibcon#*before write, iclass 6, count 2 2006.217.08:15:49.42#ibcon#enter sib2, iclass 6, count 2 2006.217.08:15:49.42#ibcon#flushed, iclass 6, count 2 2006.217.08:15:49.42#ibcon#about to write, iclass 6, count 2 2006.217.08:15:49.42#ibcon#wrote, iclass 6, count 2 2006.217.08:15:49.42#ibcon#about to read 3, iclass 6, count 2 2006.217.08:15:49.44#ibcon#read 3, iclass 6, count 2 2006.217.08:15:49.45#ibcon#about to read 4, iclass 6, count 2 2006.217.08:15:49.45#ibcon#read 4, iclass 6, count 2 2006.217.08:15:49.45#ibcon#about to read 5, iclass 6, count 2 2006.217.08:15:49.45#ibcon#read 5, iclass 6, count 2 2006.217.08:15:49.45#ibcon#about to read 6, iclass 6, count 2 2006.217.08:15:49.45#ibcon#read 6, iclass 6, count 2 2006.217.08:15:49.45#ibcon#end of sib2, iclass 6, count 2 2006.217.08:15:49.45#ibcon#*after write, iclass 6, count 2 2006.217.08:15:49.45#ibcon#*before return 0, iclass 6, count 2 2006.217.08:15:49.45#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.217.08:15:49.45#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.217.08:15:49.45#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.217.08:15:49.45#ibcon#ireg 7 cls_cnt 0 2006.217.08:15:49.45#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.217.08:15:49.56#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.217.08:15:49.56#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.217.08:15:49.57#ibcon#enter wrdev, iclass 6, count 0 2006.217.08:15:49.57#ibcon#first serial, iclass 6, count 0 2006.217.08:15:49.57#ibcon#enter sib2, iclass 6, count 0 2006.217.08:15:49.57#ibcon#flushed, iclass 6, count 0 2006.217.08:15:49.57#ibcon#about to write, iclass 6, count 0 2006.217.08:15:49.57#ibcon#wrote, iclass 6, count 0 2006.217.08:15:49.57#ibcon#about to read 3, iclass 6, count 0 2006.217.08:15:49.58#ibcon#read 3, iclass 6, count 0 2006.217.08:15:49.59#ibcon#about to read 4, iclass 6, count 0 2006.217.08:15:49.59#ibcon#read 4, iclass 6, count 0 2006.217.08:15:49.59#ibcon#about to read 5, iclass 6, count 0 2006.217.08:15:49.59#ibcon#read 5, iclass 6, count 0 2006.217.08:15:49.59#ibcon#about to read 6, iclass 6, count 0 2006.217.08:15:49.59#ibcon#read 6, iclass 6, count 0 2006.217.08:15:49.59#ibcon#end of sib2, iclass 6, count 0 2006.217.08:15:49.59#ibcon#*mode == 0, iclass 6, count 0 2006.217.08:15:49.59#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.217.08:15:49.59#ibcon#[25=USB\r\n] 2006.217.08:15:49.59#ibcon#*before write, iclass 6, count 0 2006.217.08:15:49.59#ibcon#enter sib2, iclass 6, count 0 2006.217.08:15:49.59#ibcon#flushed, iclass 6, count 0 2006.217.08:15:49.59#ibcon#about to write, iclass 6, count 0 2006.217.08:15:49.59#ibcon#wrote, iclass 6, count 0 2006.217.08:15:49.59#ibcon#about to read 3, iclass 6, count 0 2006.217.08:15:49.61#ibcon#read 3, iclass 6, count 0 2006.217.08:15:49.62#ibcon#about to read 4, iclass 6, count 0 2006.217.08:15:49.62#ibcon#read 4, iclass 6, count 0 2006.217.08:15:49.62#ibcon#about to read 5, iclass 6, count 0 2006.217.08:15:49.62#ibcon#read 5, iclass 6, count 0 2006.217.08:15:49.62#ibcon#about to read 6, iclass 6, count 0 2006.217.08:15:49.62#ibcon#read 6, iclass 6, count 0 2006.217.08:15:49.62#ibcon#end of sib2, iclass 6, count 0 2006.217.08:15:49.62#ibcon#*after write, iclass 6, count 0 2006.217.08:15:49.62#ibcon#*before return 0, iclass 6, count 0 2006.217.08:15:49.62#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.217.08:15:49.62#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.217.08:15:49.62#ibcon#about to clear, iclass 6 cls_cnt 0 2006.217.08:15:49.62#ibcon#cleared, iclass 6 cls_cnt 0 2006.217.08:15:49.62$vc4f8/valo=6,772.99 2006.217.08:15:49.62#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.217.08:15:49.62#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.217.08:15:49.62#ibcon#ireg 17 cls_cnt 0 2006.217.08:15:49.62#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.217.08:15:49.62#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.217.08:15:49.62#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.217.08:15:49.62#ibcon#enter wrdev, iclass 10, count 0 2006.217.08:15:49.62#ibcon#first serial, iclass 10, count 0 2006.217.08:15:49.62#ibcon#enter sib2, iclass 10, count 0 2006.217.08:15:49.62#ibcon#flushed, iclass 10, count 0 2006.217.08:15:49.62#ibcon#about to write, iclass 10, count 0 2006.217.08:15:49.62#ibcon#wrote, iclass 10, count 0 2006.217.08:15:49.62#ibcon#about to read 3, iclass 10, count 0 2006.217.08:15:49.63#ibcon#read 3, iclass 10, count 0 2006.217.08:15:49.64#ibcon#about to read 4, iclass 10, count 0 2006.217.08:15:49.64#ibcon#read 4, iclass 10, count 0 2006.217.08:15:49.64#ibcon#about to read 5, iclass 10, count 0 2006.217.08:15:49.64#ibcon#read 5, iclass 10, count 0 2006.217.08:15:49.64#ibcon#about to read 6, iclass 10, count 0 2006.217.08:15:49.64#ibcon#read 6, iclass 10, count 0 2006.217.08:15:49.64#ibcon#end of sib2, iclass 10, count 0 2006.217.08:15:49.64#ibcon#*mode == 0, iclass 10, count 0 2006.217.08:15:49.64#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.217.08:15:49.64#ibcon#[26=FRQ=06,772.99\r\n] 2006.217.08:15:49.64#ibcon#*before write, iclass 10, count 0 2006.217.08:15:49.64#ibcon#enter sib2, iclass 10, count 0 2006.217.08:15:49.64#ibcon#flushed, iclass 10, count 0 2006.217.08:15:49.64#ibcon#about to write, iclass 10, count 0 2006.217.08:15:49.64#ibcon#wrote, iclass 10, count 0 2006.217.08:15:49.64#ibcon#about to read 3, iclass 10, count 0 2006.217.08:15:49.67#ibcon#read 3, iclass 10, count 0 2006.217.08:15:49.68#ibcon#about to read 4, iclass 10, count 0 2006.217.08:15:49.68#ibcon#read 4, iclass 10, count 0 2006.217.08:15:49.68#ibcon#about to read 5, iclass 10, count 0 2006.217.08:15:49.68#ibcon#read 5, iclass 10, count 0 2006.217.08:15:49.68#ibcon#about to read 6, iclass 10, count 0 2006.217.08:15:49.68#ibcon#read 6, iclass 10, count 0 2006.217.08:15:49.68#ibcon#end of sib2, iclass 10, count 0 2006.217.08:15:49.68#ibcon#*after write, iclass 10, count 0 2006.217.08:15:49.68#ibcon#*before return 0, iclass 10, count 0 2006.217.08:15:49.68#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.217.08:15:49.68#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.217.08:15:49.68#ibcon#about to clear, iclass 10 cls_cnt 0 2006.217.08:15:49.68#ibcon#cleared, iclass 10 cls_cnt 0 2006.217.08:15:49.68$vc4f8/va=6,6 2006.217.08:15:49.68#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.217.08:15:49.68#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.217.08:15:49.68#ibcon#ireg 11 cls_cnt 2 2006.217.08:15:49.68#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.217.08:15:49.74#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.217.08:15:49.74#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.217.08:15:49.74#ibcon#enter wrdev, iclass 12, count 2 2006.217.08:15:49.74#ibcon#first serial, iclass 12, count 2 2006.217.08:15:49.74#ibcon#enter sib2, iclass 12, count 2 2006.217.08:15:49.74#ibcon#flushed, iclass 12, count 2 2006.217.08:15:49.74#ibcon#about to write, iclass 12, count 2 2006.217.08:15:49.74#ibcon#wrote, iclass 12, count 2 2006.217.08:15:49.74#ibcon#about to read 3, iclass 12, count 2 2006.217.08:15:49.76#ibcon#read 3, iclass 12, count 2 2006.217.08:15:49.76#ibcon#about to read 4, iclass 12, count 2 2006.217.08:15:49.76#ibcon#read 4, iclass 12, count 2 2006.217.08:15:49.76#ibcon#about to read 5, iclass 12, count 2 2006.217.08:15:49.76#ibcon#read 5, iclass 12, count 2 2006.217.08:15:49.76#ibcon#about to read 6, iclass 12, count 2 2006.217.08:15:49.76#ibcon#read 6, iclass 12, count 2 2006.217.08:15:49.76#ibcon#end of sib2, iclass 12, count 2 2006.217.08:15:49.76#ibcon#*mode == 0, iclass 12, count 2 2006.217.08:15:49.76#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.217.08:15:49.76#ibcon#[25=AT06-06\r\n] 2006.217.08:15:49.76#ibcon#*before write, iclass 12, count 2 2006.217.08:15:49.76#ibcon#enter sib2, iclass 12, count 2 2006.217.08:15:49.76#ibcon#flushed, iclass 12, count 2 2006.217.08:15:49.76#ibcon#about to write, iclass 12, count 2 2006.217.08:15:49.76#ibcon#wrote, iclass 12, count 2 2006.217.08:15:49.76#ibcon#about to read 3, iclass 12, count 2 2006.217.08:15:49.79#ibcon#read 3, iclass 12, count 2 2006.217.08:15:49.79#ibcon#about to read 4, iclass 12, count 2 2006.217.08:15:49.79#ibcon#read 4, iclass 12, count 2 2006.217.08:15:49.79#ibcon#about to read 5, iclass 12, count 2 2006.217.08:15:49.79#ibcon#read 5, iclass 12, count 2 2006.217.08:15:49.79#ibcon#about to read 6, iclass 12, count 2 2006.217.08:15:49.79#ibcon#read 6, iclass 12, count 2 2006.217.08:15:49.79#ibcon#end of sib2, iclass 12, count 2 2006.217.08:15:49.79#ibcon#*after write, iclass 12, count 2 2006.217.08:15:49.79#ibcon#*before return 0, iclass 12, count 2 2006.217.08:15:49.79#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.217.08:15:49.79#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.217.08:15:49.79#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.217.08:15:49.79#ibcon#ireg 7 cls_cnt 0 2006.217.08:15:49.79#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.217.08:15:49.90#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.217.08:15:49.90#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.217.08:15:49.91#ibcon#enter wrdev, iclass 12, count 0 2006.217.08:15:49.91#ibcon#first serial, iclass 12, count 0 2006.217.08:15:49.91#ibcon#enter sib2, iclass 12, count 0 2006.217.08:15:49.91#ibcon#flushed, iclass 12, count 0 2006.217.08:15:49.91#ibcon#about to write, iclass 12, count 0 2006.217.08:15:49.91#ibcon#wrote, iclass 12, count 0 2006.217.08:15:49.91#ibcon#about to read 3, iclass 12, count 0 2006.217.08:15:49.92#ibcon#read 3, iclass 12, count 0 2006.217.08:15:49.93#ibcon#about to read 4, iclass 12, count 0 2006.217.08:15:49.93#ibcon#read 4, iclass 12, count 0 2006.217.08:15:49.93#ibcon#about to read 5, iclass 12, count 0 2006.217.08:15:49.93#ibcon#read 5, iclass 12, count 0 2006.217.08:15:49.93#ibcon#about to read 6, iclass 12, count 0 2006.217.08:15:49.93#ibcon#read 6, iclass 12, count 0 2006.217.08:15:49.93#ibcon#end of sib2, iclass 12, count 0 2006.217.08:15:49.93#ibcon#*mode == 0, iclass 12, count 0 2006.217.08:15:49.93#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.217.08:15:49.93#ibcon#[25=USB\r\n] 2006.217.08:15:49.93#ibcon#*before write, iclass 12, count 0 2006.217.08:15:49.93#ibcon#enter sib2, iclass 12, count 0 2006.217.08:15:49.93#ibcon#flushed, iclass 12, count 0 2006.217.08:15:49.93#ibcon#about to write, iclass 12, count 0 2006.217.08:15:49.93#ibcon#wrote, iclass 12, count 0 2006.217.08:15:49.93#ibcon#about to read 3, iclass 12, count 0 2006.217.08:15:49.95#ibcon#read 3, iclass 12, count 0 2006.217.08:15:49.96#ibcon#about to read 4, iclass 12, count 0 2006.217.08:15:49.96#ibcon#read 4, iclass 12, count 0 2006.217.08:15:49.96#ibcon#about to read 5, iclass 12, count 0 2006.217.08:15:49.96#ibcon#read 5, iclass 12, count 0 2006.217.08:15:49.96#ibcon#about to read 6, iclass 12, count 0 2006.217.08:15:49.96#ibcon#read 6, iclass 12, count 0 2006.217.08:15:49.96#ibcon#end of sib2, iclass 12, count 0 2006.217.08:15:49.96#ibcon#*after write, iclass 12, count 0 2006.217.08:15:49.96#ibcon#*before return 0, iclass 12, count 0 2006.217.08:15:49.96#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.217.08:15:49.96#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.217.08:15:49.96#ibcon#about to clear, iclass 12 cls_cnt 0 2006.217.08:15:49.96#ibcon#cleared, iclass 12 cls_cnt 0 2006.217.08:15:49.96$vc4f8/valo=7,832.99 2006.217.08:15:49.96#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.217.08:15:49.96#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.217.08:15:49.96#ibcon#ireg 17 cls_cnt 0 2006.217.08:15:49.96#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.217.08:15:49.96#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.217.08:15:49.96#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.217.08:15:49.96#ibcon#enter wrdev, iclass 14, count 0 2006.217.08:15:49.96#ibcon#first serial, iclass 14, count 0 2006.217.08:15:49.96#ibcon#enter sib2, iclass 14, count 0 2006.217.08:15:49.96#ibcon#flushed, iclass 14, count 0 2006.217.08:15:49.96#ibcon#about to write, iclass 14, count 0 2006.217.08:15:49.96#ibcon#wrote, iclass 14, count 0 2006.217.08:15:49.96#ibcon#about to read 3, iclass 14, count 0 2006.217.08:15:49.97#ibcon#read 3, iclass 14, count 0 2006.217.08:15:49.98#ibcon#about to read 4, iclass 14, count 0 2006.217.08:15:49.98#ibcon#read 4, iclass 14, count 0 2006.217.08:15:49.98#ibcon#about to read 5, iclass 14, count 0 2006.217.08:15:49.98#ibcon#read 5, iclass 14, count 0 2006.217.08:15:49.98#ibcon#about to read 6, iclass 14, count 0 2006.217.08:15:49.98#ibcon#read 6, iclass 14, count 0 2006.217.08:15:49.98#ibcon#end of sib2, iclass 14, count 0 2006.217.08:15:49.98#ibcon#*mode == 0, iclass 14, count 0 2006.217.08:15:49.98#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.217.08:15:49.98#ibcon#[26=FRQ=07,832.99\r\n] 2006.217.08:15:49.98#ibcon#*before write, iclass 14, count 0 2006.217.08:15:49.98#ibcon#enter sib2, iclass 14, count 0 2006.217.08:15:49.98#ibcon#flushed, iclass 14, count 0 2006.217.08:15:49.98#ibcon#about to write, iclass 14, count 0 2006.217.08:15:49.98#ibcon#wrote, iclass 14, count 0 2006.217.08:15:49.98#ibcon#about to read 3, iclass 14, count 0 2006.217.08:15:50.01#ibcon#read 3, iclass 14, count 0 2006.217.08:15:50.02#ibcon#about to read 4, iclass 14, count 0 2006.217.08:15:50.02#ibcon#read 4, iclass 14, count 0 2006.217.08:15:50.02#ibcon#about to read 5, iclass 14, count 0 2006.217.08:15:50.02#ibcon#read 5, iclass 14, count 0 2006.217.08:15:50.02#ibcon#about to read 6, iclass 14, count 0 2006.217.08:15:50.02#ibcon#read 6, iclass 14, count 0 2006.217.08:15:50.02#ibcon#end of sib2, iclass 14, count 0 2006.217.08:15:50.02#ibcon#*after write, iclass 14, count 0 2006.217.08:15:50.02#ibcon#*before return 0, iclass 14, count 0 2006.217.08:15:50.02#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.217.08:15:50.02#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.217.08:15:50.02#ibcon#about to clear, iclass 14 cls_cnt 0 2006.217.08:15:50.02#ibcon#cleared, iclass 14 cls_cnt 0 2006.217.08:15:50.02$vc4f8/va=7,6 2006.217.08:15:50.02#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.217.08:15:50.02#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.217.08:15:50.02#ibcon#ireg 11 cls_cnt 2 2006.217.08:15:50.02#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.217.08:15:50.07#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.217.08:15:50.07#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.217.08:15:50.08#ibcon#enter wrdev, iclass 16, count 2 2006.217.08:15:50.08#ibcon#first serial, iclass 16, count 2 2006.217.08:15:50.08#ibcon#enter sib2, iclass 16, count 2 2006.217.08:15:50.08#ibcon#flushed, iclass 16, count 2 2006.217.08:15:50.08#ibcon#about to write, iclass 16, count 2 2006.217.08:15:50.08#ibcon#wrote, iclass 16, count 2 2006.217.08:15:50.08#ibcon#about to read 3, iclass 16, count 2 2006.217.08:15:50.09#ibcon#read 3, iclass 16, count 2 2006.217.08:15:50.10#ibcon#about to read 4, iclass 16, count 2 2006.217.08:15:50.10#ibcon#read 4, iclass 16, count 2 2006.217.08:15:50.10#ibcon#about to read 5, iclass 16, count 2 2006.217.08:15:50.10#ibcon#read 5, iclass 16, count 2 2006.217.08:15:50.10#ibcon#about to read 6, iclass 16, count 2 2006.217.08:15:50.10#ibcon#read 6, iclass 16, count 2 2006.217.08:15:50.10#ibcon#end of sib2, iclass 16, count 2 2006.217.08:15:50.10#ibcon#*mode == 0, iclass 16, count 2 2006.217.08:15:50.10#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.217.08:15:50.10#ibcon#[25=AT07-06\r\n] 2006.217.08:15:50.10#ibcon#*before write, iclass 16, count 2 2006.217.08:15:50.10#ibcon#enter sib2, iclass 16, count 2 2006.217.08:15:50.10#ibcon#flushed, iclass 16, count 2 2006.217.08:15:50.10#ibcon#about to write, iclass 16, count 2 2006.217.08:15:50.10#ibcon#wrote, iclass 16, count 2 2006.217.08:15:50.10#ibcon#about to read 3, iclass 16, count 2 2006.217.08:15:50.13#ibcon#read 3, iclass 16, count 2 2006.217.08:15:50.13#ibcon#about to read 4, iclass 16, count 2 2006.217.08:15:50.13#ibcon#read 4, iclass 16, count 2 2006.217.08:15:50.13#ibcon#about to read 5, iclass 16, count 2 2006.217.08:15:50.13#ibcon#read 5, iclass 16, count 2 2006.217.08:15:50.13#ibcon#about to read 6, iclass 16, count 2 2006.217.08:15:50.13#ibcon#read 6, iclass 16, count 2 2006.217.08:15:50.13#ibcon#end of sib2, iclass 16, count 2 2006.217.08:15:50.13#ibcon#*after write, iclass 16, count 2 2006.217.08:15:50.13#ibcon#*before return 0, iclass 16, count 2 2006.217.08:15:50.13#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.217.08:15:50.13#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.217.08:15:50.13#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.217.08:15:50.13#ibcon#ireg 7 cls_cnt 0 2006.217.08:15:50.13#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.217.08:15:50.24#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.217.08:15:50.24#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.217.08:15:50.25#ibcon#enter wrdev, iclass 16, count 0 2006.217.08:15:50.25#ibcon#first serial, iclass 16, count 0 2006.217.08:15:50.25#ibcon#enter sib2, iclass 16, count 0 2006.217.08:15:50.25#ibcon#flushed, iclass 16, count 0 2006.217.08:15:50.25#ibcon#about to write, iclass 16, count 0 2006.217.08:15:50.25#ibcon#wrote, iclass 16, count 0 2006.217.08:15:50.25#ibcon#about to read 3, iclass 16, count 0 2006.217.08:15:50.26#ibcon#read 3, iclass 16, count 0 2006.217.08:15:50.27#ibcon#about to read 4, iclass 16, count 0 2006.217.08:15:50.27#ibcon#read 4, iclass 16, count 0 2006.217.08:15:50.27#ibcon#about to read 5, iclass 16, count 0 2006.217.08:15:50.27#ibcon#read 5, iclass 16, count 0 2006.217.08:15:50.27#ibcon#about to read 6, iclass 16, count 0 2006.217.08:15:50.27#ibcon#read 6, iclass 16, count 0 2006.217.08:15:50.27#ibcon#end of sib2, iclass 16, count 0 2006.217.08:15:50.27#ibcon#*mode == 0, iclass 16, count 0 2006.217.08:15:50.27#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.217.08:15:50.27#ibcon#[25=USB\r\n] 2006.217.08:15:50.27#ibcon#*before write, iclass 16, count 0 2006.217.08:15:50.27#ibcon#enter sib2, iclass 16, count 0 2006.217.08:15:50.27#ibcon#flushed, iclass 16, count 0 2006.217.08:15:50.27#ibcon#about to write, iclass 16, count 0 2006.217.08:15:50.27#ibcon#wrote, iclass 16, count 0 2006.217.08:15:50.27#ibcon#about to read 3, iclass 16, count 0 2006.217.08:15:50.29#ibcon#read 3, iclass 16, count 0 2006.217.08:15:50.30#ibcon#about to read 4, iclass 16, count 0 2006.217.08:15:50.30#ibcon#read 4, iclass 16, count 0 2006.217.08:15:50.30#ibcon#about to read 5, iclass 16, count 0 2006.217.08:15:50.30#ibcon#read 5, iclass 16, count 0 2006.217.08:15:50.30#ibcon#about to read 6, iclass 16, count 0 2006.217.08:15:50.30#ibcon#read 6, iclass 16, count 0 2006.217.08:15:50.30#ibcon#end of sib2, iclass 16, count 0 2006.217.08:15:50.30#ibcon#*after write, iclass 16, count 0 2006.217.08:15:50.30#ibcon#*before return 0, iclass 16, count 0 2006.217.08:15:50.30#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.217.08:15:50.30#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.217.08:15:50.30#ibcon#about to clear, iclass 16 cls_cnt 0 2006.217.08:15:50.30#ibcon#cleared, iclass 16 cls_cnt 0 2006.217.08:15:50.30$vc4f8/valo=8,852.99 2006.217.08:15:50.30#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.217.08:15:50.30#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.217.08:15:50.30#ibcon#ireg 17 cls_cnt 0 2006.217.08:15:50.30#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.217.08:15:50.30#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.217.08:15:50.30#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.217.08:15:50.30#ibcon#enter wrdev, iclass 18, count 0 2006.217.08:15:50.30#ibcon#first serial, iclass 18, count 0 2006.217.08:15:50.30#ibcon#enter sib2, iclass 18, count 0 2006.217.08:15:50.30#ibcon#flushed, iclass 18, count 0 2006.217.08:15:50.30#ibcon#about to write, iclass 18, count 0 2006.217.08:15:50.30#ibcon#wrote, iclass 18, count 0 2006.217.08:15:50.30#ibcon#about to read 3, iclass 18, count 0 2006.217.08:15:50.31#ibcon#read 3, iclass 18, count 0 2006.217.08:15:50.32#ibcon#about to read 4, iclass 18, count 0 2006.217.08:15:50.32#ibcon#read 4, iclass 18, count 0 2006.217.08:15:50.32#ibcon#about to read 5, iclass 18, count 0 2006.217.08:15:50.32#ibcon#read 5, iclass 18, count 0 2006.217.08:15:50.32#ibcon#about to read 6, iclass 18, count 0 2006.217.08:15:50.32#ibcon#read 6, iclass 18, count 0 2006.217.08:15:50.32#ibcon#end of sib2, iclass 18, count 0 2006.217.08:15:50.32#ibcon#*mode == 0, iclass 18, count 0 2006.217.08:15:50.32#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.217.08:15:50.32#ibcon#[26=FRQ=08,852.99\r\n] 2006.217.08:15:50.32#ibcon#*before write, iclass 18, count 0 2006.217.08:15:50.32#ibcon#enter sib2, iclass 18, count 0 2006.217.08:15:50.32#ibcon#flushed, iclass 18, count 0 2006.217.08:15:50.32#ibcon#about to write, iclass 18, count 0 2006.217.08:15:50.32#ibcon#wrote, iclass 18, count 0 2006.217.08:15:50.32#ibcon#about to read 3, iclass 18, count 0 2006.217.08:15:50.35#ibcon#read 3, iclass 18, count 0 2006.217.08:15:50.36#ibcon#about to read 4, iclass 18, count 0 2006.217.08:15:50.36#ibcon#read 4, iclass 18, count 0 2006.217.08:15:50.36#ibcon#about to read 5, iclass 18, count 0 2006.217.08:15:50.36#ibcon#read 5, iclass 18, count 0 2006.217.08:15:50.36#ibcon#about to read 6, iclass 18, count 0 2006.217.08:15:50.36#ibcon#read 6, iclass 18, count 0 2006.217.08:15:50.36#ibcon#end of sib2, iclass 18, count 0 2006.217.08:15:50.36#ibcon#*after write, iclass 18, count 0 2006.217.08:15:50.36#ibcon#*before return 0, iclass 18, count 0 2006.217.08:15:50.36#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.217.08:15:50.36#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.217.08:15:50.36#ibcon#about to clear, iclass 18 cls_cnt 0 2006.217.08:15:50.36#ibcon#cleared, iclass 18 cls_cnt 0 2006.217.08:15:50.36$vc4f8/va=8,7 2006.217.08:15:50.36#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.217.08:15:50.36#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.217.08:15:50.36#ibcon#ireg 11 cls_cnt 2 2006.217.08:15:50.36#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.217.08:15:50.41#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.217.08:15:50.41#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.217.08:15:50.42#ibcon#enter wrdev, iclass 20, count 2 2006.217.08:15:50.42#ibcon#first serial, iclass 20, count 2 2006.217.08:15:50.42#ibcon#enter sib2, iclass 20, count 2 2006.217.08:15:50.42#ibcon#flushed, iclass 20, count 2 2006.217.08:15:50.42#ibcon#about to write, iclass 20, count 2 2006.217.08:15:50.42#ibcon#wrote, iclass 20, count 2 2006.217.08:15:50.42#ibcon#about to read 3, iclass 20, count 2 2006.217.08:15:50.43#ibcon#read 3, iclass 20, count 2 2006.217.08:15:50.44#ibcon#about to read 4, iclass 20, count 2 2006.217.08:15:50.44#ibcon#read 4, iclass 20, count 2 2006.217.08:15:50.44#ibcon#about to read 5, iclass 20, count 2 2006.217.08:15:50.44#ibcon#read 5, iclass 20, count 2 2006.217.08:15:50.44#ibcon#about to read 6, iclass 20, count 2 2006.217.08:15:50.44#ibcon#read 6, iclass 20, count 2 2006.217.08:15:50.44#ibcon#end of sib2, iclass 20, count 2 2006.217.08:15:50.44#ibcon#*mode == 0, iclass 20, count 2 2006.217.08:15:50.44#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.217.08:15:50.44#ibcon#[25=AT08-07\r\n] 2006.217.08:15:50.44#ibcon#*before write, iclass 20, count 2 2006.217.08:15:50.44#ibcon#enter sib2, iclass 20, count 2 2006.217.08:15:50.44#ibcon#flushed, iclass 20, count 2 2006.217.08:15:50.44#ibcon#about to write, iclass 20, count 2 2006.217.08:15:50.44#ibcon#wrote, iclass 20, count 2 2006.217.08:15:50.44#ibcon#about to read 3, iclass 20, count 2 2006.217.08:15:50.46#abcon#<5=/05 3.8 6.9 30.57 641008.6\r\n> 2006.217.08:15:50.46#ibcon#read 3, iclass 20, count 2 2006.217.08:15:50.47#ibcon#about to read 4, iclass 20, count 2 2006.217.08:15:50.47#ibcon#read 4, iclass 20, count 2 2006.217.08:15:50.47#ibcon#about to read 5, iclass 20, count 2 2006.217.08:15:50.47#ibcon#read 5, iclass 20, count 2 2006.217.08:15:50.47#ibcon#about to read 6, iclass 20, count 2 2006.217.08:15:50.47#ibcon#read 6, iclass 20, count 2 2006.217.08:15:50.47#ibcon#end of sib2, iclass 20, count 2 2006.217.08:15:50.47#ibcon#*after write, iclass 20, count 2 2006.217.08:15:50.47#ibcon#*before return 0, iclass 20, count 2 2006.217.08:15:50.47#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.217.08:15:50.47#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.217.08:15:50.47#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.217.08:15:50.47#ibcon#ireg 7 cls_cnt 0 2006.217.08:15:50.47#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.217.08:15:50.48#abcon#{5=INTERFACE CLEAR} 2006.217.08:15:50.53#abcon#[5=S1D000X0/0*\r\n] 2006.217.08:15:50.58#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.217.08:15:50.58#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.217.08:15:50.58#ibcon#enter wrdev, iclass 20, count 0 2006.217.08:15:50.59#ibcon#first serial, iclass 20, count 0 2006.217.08:15:50.59#ibcon#enter sib2, iclass 20, count 0 2006.217.08:15:50.59#ibcon#flushed, iclass 20, count 0 2006.217.08:15:50.59#ibcon#about to write, iclass 20, count 0 2006.217.08:15:50.59#ibcon#wrote, iclass 20, count 0 2006.217.08:15:50.59#ibcon#about to read 3, iclass 20, count 0 2006.217.08:15:50.60#ibcon#read 3, iclass 20, count 0 2006.217.08:15:50.61#ibcon#about to read 4, iclass 20, count 0 2006.217.08:15:50.61#ibcon#read 4, iclass 20, count 0 2006.217.08:15:50.61#ibcon#about to read 5, iclass 20, count 0 2006.217.08:15:50.61#ibcon#read 5, iclass 20, count 0 2006.217.08:15:50.61#ibcon#about to read 6, iclass 20, count 0 2006.217.08:15:50.61#ibcon#read 6, iclass 20, count 0 2006.217.08:15:50.61#ibcon#end of sib2, iclass 20, count 0 2006.217.08:15:50.61#ibcon#*mode == 0, iclass 20, count 0 2006.217.08:15:50.61#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.217.08:15:50.61#ibcon#[25=USB\r\n] 2006.217.08:15:50.61#ibcon#*before write, iclass 20, count 0 2006.217.08:15:50.61#ibcon#enter sib2, iclass 20, count 0 2006.217.08:15:50.61#ibcon#flushed, iclass 20, count 0 2006.217.08:15:50.61#ibcon#about to write, iclass 20, count 0 2006.217.08:15:50.61#ibcon#wrote, iclass 20, count 0 2006.217.08:15:50.61#ibcon#about to read 3, iclass 20, count 0 2006.217.08:15:50.64#ibcon#read 3, iclass 20, count 0 2006.217.08:15:50.64#ibcon#about to read 4, iclass 20, count 0 2006.217.08:15:50.64#ibcon#read 4, iclass 20, count 0 2006.217.08:15:50.64#ibcon#about to read 5, iclass 20, count 0 2006.217.08:15:50.64#ibcon#read 5, iclass 20, count 0 2006.217.08:15:50.64#ibcon#about to read 6, iclass 20, count 0 2006.217.08:15:50.64#ibcon#read 6, iclass 20, count 0 2006.217.08:15:50.64#ibcon#end of sib2, iclass 20, count 0 2006.217.08:15:50.64#ibcon#*after write, iclass 20, count 0 2006.217.08:15:50.64#ibcon#*before return 0, iclass 20, count 0 2006.217.08:15:50.64#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.217.08:15:50.64#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.217.08:15:50.64#ibcon#about to clear, iclass 20 cls_cnt 0 2006.217.08:15:50.64#ibcon#cleared, iclass 20 cls_cnt 0 2006.217.08:15:50.64$vc4f8/vblo=1,632.99 2006.217.08:15:50.64#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.217.08:15:50.64#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.217.08:15:50.64#ibcon#ireg 17 cls_cnt 0 2006.217.08:15:50.64#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.217.08:15:50.64#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.217.08:15:50.64#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.217.08:15:50.64#ibcon#enter wrdev, iclass 26, count 0 2006.217.08:15:50.64#ibcon#first serial, iclass 26, count 0 2006.217.08:15:50.64#ibcon#enter sib2, iclass 26, count 0 2006.217.08:15:50.64#ibcon#flushed, iclass 26, count 0 2006.217.08:15:50.64#ibcon#about to write, iclass 26, count 0 2006.217.08:15:50.64#ibcon#wrote, iclass 26, count 0 2006.217.08:15:50.64#ibcon#about to read 3, iclass 26, count 0 2006.217.08:15:50.65#ibcon#read 3, iclass 26, count 0 2006.217.08:15:50.66#ibcon#about to read 4, iclass 26, count 0 2006.217.08:15:50.66#ibcon#read 4, iclass 26, count 0 2006.217.08:15:50.66#ibcon#about to read 5, iclass 26, count 0 2006.217.08:15:50.66#ibcon#read 5, iclass 26, count 0 2006.217.08:15:50.66#ibcon#about to read 6, iclass 26, count 0 2006.217.08:15:50.66#ibcon#read 6, iclass 26, count 0 2006.217.08:15:50.66#ibcon#end of sib2, iclass 26, count 0 2006.217.08:15:50.66#ibcon#*mode == 0, iclass 26, count 0 2006.217.08:15:50.66#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.217.08:15:50.66#ibcon#[28=FRQ=01,632.99\r\n] 2006.217.08:15:50.66#ibcon#*before write, iclass 26, count 0 2006.217.08:15:50.66#ibcon#enter sib2, iclass 26, count 0 2006.217.08:15:50.66#ibcon#flushed, iclass 26, count 0 2006.217.08:15:50.66#ibcon#about to write, iclass 26, count 0 2006.217.08:15:50.66#ibcon#wrote, iclass 26, count 0 2006.217.08:15:50.66#ibcon#about to read 3, iclass 26, count 0 2006.217.08:15:50.69#ibcon#read 3, iclass 26, count 0 2006.217.08:15:50.70#ibcon#about to read 4, iclass 26, count 0 2006.217.08:15:50.70#ibcon#read 4, iclass 26, count 0 2006.217.08:15:50.70#ibcon#about to read 5, iclass 26, count 0 2006.217.08:15:50.70#ibcon#read 5, iclass 26, count 0 2006.217.08:15:50.70#ibcon#about to read 6, iclass 26, count 0 2006.217.08:15:50.70#ibcon#read 6, iclass 26, count 0 2006.217.08:15:50.70#ibcon#end of sib2, iclass 26, count 0 2006.217.08:15:50.70#ibcon#*after write, iclass 26, count 0 2006.217.08:15:50.70#ibcon#*before return 0, iclass 26, count 0 2006.217.08:15:50.70#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.217.08:15:50.70#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.217.08:15:50.70#ibcon#about to clear, iclass 26 cls_cnt 0 2006.217.08:15:50.70#ibcon#cleared, iclass 26 cls_cnt 0 2006.217.08:15:50.70$vc4f8/vb=1,4 2006.217.08:15:50.70#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.217.08:15:50.70#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.217.08:15:50.70#ibcon#ireg 11 cls_cnt 2 2006.217.08:15:50.70#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.217.08:15:50.70#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.217.08:15:50.70#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.217.08:15:50.70#ibcon#enter wrdev, iclass 28, count 2 2006.217.08:15:50.70#ibcon#first serial, iclass 28, count 2 2006.217.08:15:50.70#ibcon#enter sib2, iclass 28, count 2 2006.217.08:15:50.70#ibcon#flushed, iclass 28, count 2 2006.217.08:15:50.70#ibcon#about to write, iclass 28, count 2 2006.217.08:15:50.70#ibcon#wrote, iclass 28, count 2 2006.217.08:15:50.70#ibcon#about to read 3, iclass 28, count 2 2006.217.08:15:50.71#ibcon#read 3, iclass 28, count 2 2006.217.08:15:50.72#ibcon#about to read 4, iclass 28, count 2 2006.217.08:15:50.72#ibcon#read 4, iclass 28, count 2 2006.217.08:15:50.72#ibcon#about to read 5, iclass 28, count 2 2006.217.08:15:50.72#ibcon#read 5, iclass 28, count 2 2006.217.08:15:50.72#ibcon#about to read 6, iclass 28, count 2 2006.217.08:15:50.72#ibcon#read 6, iclass 28, count 2 2006.217.08:15:50.72#ibcon#end of sib2, iclass 28, count 2 2006.217.08:15:50.72#ibcon#*mode == 0, iclass 28, count 2 2006.217.08:15:50.72#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.217.08:15:50.72#ibcon#[27=AT01-04\r\n] 2006.217.08:15:50.72#ibcon#*before write, iclass 28, count 2 2006.217.08:15:50.72#ibcon#enter sib2, iclass 28, count 2 2006.217.08:15:50.72#ibcon#flushed, iclass 28, count 2 2006.217.08:15:50.72#ibcon#about to write, iclass 28, count 2 2006.217.08:15:50.72#ibcon#wrote, iclass 28, count 2 2006.217.08:15:50.72#ibcon#about to read 3, iclass 28, count 2 2006.217.08:15:50.74#ibcon#read 3, iclass 28, count 2 2006.217.08:15:50.75#ibcon#about to read 4, iclass 28, count 2 2006.217.08:15:50.75#ibcon#read 4, iclass 28, count 2 2006.217.08:15:50.75#ibcon#about to read 5, iclass 28, count 2 2006.217.08:15:50.75#ibcon#read 5, iclass 28, count 2 2006.217.08:15:50.75#ibcon#about to read 6, iclass 28, count 2 2006.217.08:15:50.75#ibcon#read 6, iclass 28, count 2 2006.217.08:15:50.75#ibcon#end of sib2, iclass 28, count 2 2006.217.08:15:50.75#ibcon#*after write, iclass 28, count 2 2006.217.08:15:50.75#ibcon#*before return 0, iclass 28, count 2 2006.217.08:15:50.75#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.217.08:15:50.75#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.217.08:15:50.75#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.217.08:15:50.75#ibcon#ireg 7 cls_cnt 0 2006.217.08:15:50.75#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.217.08:15:50.86#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.217.08:15:50.86#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.217.08:15:50.87#ibcon#enter wrdev, iclass 28, count 0 2006.217.08:15:50.87#ibcon#first serial, iclass 28, count 0 2006.217.08:15:50.87#ibcon#enter sib2, iclass 28, count 0 2006.217.08:15:50.87#ibcon#flushed, iclass 28, count 0 2006.217.08:15:50.87#ibcon#about to write, iclass 28, count 0 2006.217.08:15:50.87#ibcon#wrote, iclass 28, count 0 2006.217.08:15:50.87#ibcon#about to read 3, iclass 28, count 0 2006.217.08:15:50.88#ibcon#read 3, iclass 28, count 0 2006.217.08:15:50.89#ibcon#about to read 4, iclass 28, count 0 2006.217.08:15:50.89#ibcon#read 4, iclass 28, count 0 2006.217.08:15:50.89#ibcon#about to read 5, iclass 28, count 0 2006.217.08:15:50.89#ibcon#read 5, iclass 28, count 0 2006.217.08:15:50.89#ibcon#about to read 6, iclass 28, count 0 2006.217.08:15:50.89#ibcon#read 6, iclass 28, count 0 2006.217.08:15:50.89#ibcon#end of sib2, iclass 28, count 0 2006.217.08:15:50.89#ibcon#*mode == 0, iclass 28, count 0 2006.217.08:15:50.89#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.217.08:15:50.89#ibcon#[27=USB\r\n] 2006.217.08:15:50.89#ibcon#*before write, iclass 28, count 0 2006.217.08:15:50.89#ibcon#enter sib2, iclass 28, count 0 2006.217.08:15:50.89#ibcon#flushed, iclass 28, count 0 2006.217.08:15:50.89#ibcon#about to write, iclass 28, count 0 2006.217.08:15:50.89#ibcon#wrote, iclass 28, count 0 2006.217.08:15:50.89#ibcon#about to read 3, iclass 28, count 0 2006.217.08:15:50.91#ibcon#read 3, iclass 28, count 0 2006.217.08:15:50.92#ibcon#about to read 4, iclass 28, count 0 2006.217.08:15:50.92#ibcon#read 4, iclass 28, count 0 2006.217.08:15:50.92#ibcon#about to read 5, iclass 28, count 0 2006.217.08:15:50.92#ibcon#read 5, iclass 28, count 0 2006.217.08:15:50.92#ibcon#about to read 6, iclass 28, count 0 2006.217.08:15:50.92#ibcon#read 6, iclass 28, count 0 2006.217.08:15:50.92#ibcon#end of sib2, iclass 28, count 0 2006.217.08:15:50.92#ibcon#*after write, iclass 28, count 0 2006.217.08:15:50.92#ibcon#*before return 0, iclass 28, count 0 2006.217.08:15:50.92#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.217.08:15:50.92#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.217.08:15:50.92#ibcon#about to clear, iclass 28 cls_cnt 0 2006.217.08:15:50.92#ibcon#cleared, iclass 28 cls_cnt 0 2006.217.08:15:50.92$vc4f8/vblo=2,640.99 2006.217.08:15:50.92#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.217.08:15:50.92#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.217.08:15:50.92#ibcon#ireg 17 cls_cnt 0 2006.217.08:15:50.92#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.217.08:15:50.92#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.217.08:15:50.92#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.217.08:15:50.92#ibcon#enter wrdev, iclass 30, count 0 2006.217.08:15:50.92#ibcon#first serial, iclass 30, count 0 2006.217.08:15:50.92#ibcon#enter sib2, iclass 30, count 0 2006.217.08:15:50.92#ibcon#flushed, iclass 30, count 0 2006.217.08:15:50.92#ibcon#about to write, iclass 30, count 0 2006.217.08:15:50.92#ibcon#wrote, iclass 30, count 0 2006.217.08:15:50.92#ibcon#about to read 3, iclass 30, count 0 2006.217.08:15:50.93#ibcon#read 3, iclass 30, count 0 2006.217.08:15:50.94#ibcon#about to read 4, iclass 30, count 0 2006.217.08:15:50.94#ibcon#read 4, iclass 30, count 0 2006.217.08:15:50.94#ibcon#about to read 5, iclass 30, count 0 2006.217.08:15:50.94#ibcon#read 5, iclass 30, count 0 2006.217.08:15:50.94#ibcon#about to read 6, iclass 30, count 0 2006.217.08:15:50.94#ibcon#read 6, iclass 30, count 0 2006.217.08:15:50.94#ibcon#end of sib2, iclass 30, count 0 2006.217.08:15:50.94#ibcon#*mode == 0, iclass 30, count 0 2006.217.08:15:50.94#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.217.08:15:50.94#ibcon#[28=FRQ=02,640.99\r\n] 2006.217.08:15:50.94#ibcon#*before write, iclass 30, count 0 2006.217.08:15:50.94#ibcon#enter sib2, iclass 30, count 0 2006.217.08:15:50.94#ibcon#flushed, iclass 30, count 0 2006.217.08:15:50.94#ibcon#about to write, iclass 30, count 0 2006.217.08:15:50.94#ibcon#wrote, iclass 30, count 0 2006.217.08:15:50.94#ibcon#about to read 3, iclass 30, count 0 2006.217.08:15:50.97#ibcon#read 3, iclass 30, count 0 2006.217.08:15:50.98#ibcon#about to read 4, iclass 30, count 0 2006.217.08:15:50.98#ibcon#read 4, iclass 30, count 0 2006.217.08:15:50.98#ibcon#about to read 5, iclass 30, count 0 2006.217.08:15:50.98#ibcon#read 5, iclass 30, count 0 2006.217.08:15:50.98#ibcon#about to read 6, iclass 30, count 0 2006.217.08:15:50.98#ibcon#read 6, iclass 30, count 0 2006.217.08:15:50.98#ibcon#end of sib2, iclass 30, count 0 2006.217.08:15:50.98#ibcon#*after write, iclass 30, count 0 2006.217.08:15:50.98#ibcon#*before return 0, iclass 30, count 0 2006.217.08:15:50.98#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.217.08:15:50.98#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.217.08:15:50.98#ibcon#about to clear, iclass 30 cls_cnt 0 2006.217.08:15:50.98#ibcon#cleared, iclass 30 cls_cnt 0 2006.217.08:15:50.98$vc4f8/vb=2,4 2006.217.08:15:50.98#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.217.08:15:50.98#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.217.08:15:50.98#ibcon#ireg 11 cls_cnt 2 2006.217.08:15:50.98#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.217.08:15:51.03#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.217.08:15:51.03#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.217.08:15:51.04#ibcon#enter wrdev, iclass 32, count 2 2006.217.08:15:51.04#ibcon#first serial, iclass 32, count 2 2006.217.08:15:51.04#ibcon#enter sib2, iclass 32, count 2 2006.217.08:15:51.04#ibcon#flushed, iclass 32, count 2 2006.217.08:15:51.04#ibcon#about to write, iclass 32, count 2 2006.217.08:15:51.04#ibcon#wrote, iclass 32, count 2 2006.217.08:15:51.04#ibcon#about to read 3, iclass 32, count 2 2006.217.08:15:51.05#ibcon#read 3, iclass 32, count 2 2006.217.08:15:51.06#ibcon#about to read 4, iclass 32, count 2 2006.217.08:15:51.06#ibcon#read 4, iclass 32, count 2 2006.217.08:15:51.06#ibcon#about to read 5, iclass 32, count 2 2006.217.08:15:51.06#ibcon#read 5, iclass 32, count 2 2006.217.08:15:51.06#ibcon#about to read 6, iclass 32, count 2 2006.217.08:15:51.06#ibcon#read 6, iclass 32, count 2 2006.217.08:15:51.06#ibcon#end of sib2, iclass 32, count 2 2006.217.08:15:51.06#ibcon#*mode == 0, iclass 32, count 2 2006.217.08:15:51.06#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.217.08:15:51.06#ibcon#[27=AT02-04\r\n] 2006.217.08:15:51.06#ibcon#*before write, iclass 32, count 2 2006.217.08:15:51.06#ibcon#enter sib2, iclass 32, count 2 2006.217.08:15:51.06#ibcon#flushed, iclass 32, count 2 2006.217.08:15:51.06#ibcon#about to write, iclass 32, count 2 2006.217.08:15:51.06#ibcon#wrote, iclass 32, count 2 2006.217.08:15:51.06#ibcon#about to read 3, iclass 32, count 2 2006.217.08:15:51.08#ibcon#read 3, iclass 32, count 2 2006.217.08:15:51.09#ibcon#about to read 4, iclass 32, count 2 2006.217.08:15:51.09#ibcon#read 4, iclass 32, count 2 2006.217.08:15:51.09#ibcon#about to read 5, iclass 32, count 2 2006.217.08:15:51.09#ibcon#read 5, iclass 32, count 2 2006.217.08:15:51.09#ibcon#about to read 6, iclass 32, count 2 2006.217.08:15:51.09#ibcon#read 6, iclass 32, count 2 2006.217.08:15:51.09#ibcon#end of sib2, iclass 32, count 2 2006.217.08:15:51.09#ibcon#*after write, iclass 32, count 2 2006.217.08:15:51.09#ibcon#*before return 0, iclass 32, count 2 2006.217.08:15:51.09#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.217.08:15:51.09#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.217.08:15:51.09#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.217.08:15:51.09#ibcon#ireg 7 cls_cnt 0 2006.217.08:15:51.09#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.217.08:15:51.20#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.217.08:15:51.20#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.217.08:15:51.21#ibcon#enter wrdev, iclass 32, count 0 2006.217.08:15:51.21#ibcon#first serial, iclass 32, count 0 2006.217.08:15:51.21#ibcon#enter sib2, iclass 32, count 0 2006.217.08:15:51.21#ibcon#flushed, iclass 32, count 0 2006.217.08:15:51.21#ibcon#about to write, iclass 32, count 0 2006.217.08:15:51.21#ibcon#wrote, iclass 32, count 0 2006.217.08:15:51.21#ibcon#about to read 3, iclass 32, count 0 2006.217.08:15:51.22#ibcon#read 3, iclass 32, count 0 2006.217.08:15:51.23#ibcon#about to read 4, iclass 32, count 0 2006.217.08:15:51.23#ibcon#read 4, iclass 32, count 0 2006.217.08:15:51.23#ibcon#about to read 5, iclass 32, count 0 2006.217.08:15:51.23#ibcon#read 5, iclass 32, count 0 2006.217.08:15:51.23#ibcon#about to read 6, iclass 32, count 0 2006.217.08:15:51.23#ibcon#read 6, iclass 32, count 0 2006.217.08:15:51.23#ibcon#end of sib2, iclass 32, count 0 2006.217.08:15:51.23#ibcon#*mode == 0, iclass 32, count 0 2006.217.08:15:51.23#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.217.08:15:51.23#ibcon#[27=USB\r\n] 2006.217.08:15:51.23#ibcon#*before write, iclass 32, count 0 2006.217.08:15:51.23#ibcon#enter sib2, iclass 32, count 0 2006.217.08:15:51.23#ibcon#flushed, iclass 32, count 0 2006.217.08:15:51.23#ibcon#about to write, iclass 32, count 0 2006.217.08:15:51.23#ibcon#wrote, iclass 32, count 0 2006.217.08:15:51.23#ibcon#about to read 3, iclass 32, count 0 2006.217.08:15:51.26#ibcon#read 3, iclass 32, count 0 2006.217.08:15:51.26#ibcon#about to read 4, iclass 32, count 0 2006.217.08:15:51.26#ibcon#read 4, iclass 32, count 0 2006.217.08:15:51.26#ibcon#about to read 5, iclass 32, count 0 2006.217.08:15:51.26#ibcon#read 5, iclass 32, count 0 2006.217.08:15:51.26#ibcon#about to read 6, iclass 32, count 0 2006.217.08:15:51.26#ibcon#read 6, iclass 32, count 0 2006.217.08:15:51.26#ibcon#end of sib2, iclass 32, count 0 2006.217.08:15:51.26#ibcon#*after write, iclass 32, count 0 2006.217.08:15:51.26#ibcon#*before return 0, iclass 32, count 0 2006.217.08:15:51.26#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.217.08:15:51.26#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.217.08:15:51.26#ibcon#about to clear, iclass 32 cls_cnt 0 2006.217.08:15:51.26#ibcon#cleared, iclass 32 cls_cnt 0 2006.217.08:15:51.26$vc4f8/vblo=3,656.99 2006.217.08:15:51.26#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.217.08:15:51.26#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.217.08:15:51.26#ibcon#ireg 17 cls_cnt 0 2006.217.08:15:51.26#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.217.08:15:51.26#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.217.08:15:51.26#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.217.08:15:51.26#ibcon#enter wrdev, iclass 34, count 0 2006.217.08:15:51.26#ibcon#first serial, iclass 34, count 0 2006.217.08:15:51.26#ibcon#enter sib2, iclass 34, count 0 2006.217.08:15:51.26#ibcon#flushed, iclass 34, count 0 2006.217.08:15:51.26#ibcon#about to write, iclass 34, count 0 2006.217.08:15:51.26#ibcon#wrote, iclass 34, count 0 2006.217.08:15:51.26#ibcon#about to read 3, iclass 34, count 0 2006.217.08:15:51.27#ibcon#read 3, iclass 34, count 0 2006.217.08:15:51.28#ibcon#about to read 4, iclass 34, count 0 2006.217.08:15:51.28#ibcon#read 4, iclass 34, count 0 2006.217.08:15:51.28#ibcon#about to read 5, iclass 34, count 0 2006.217.08:15:51.28#ibcon#read 5, iclass 34, count 0 2006.217.08:15:51.28#ibcon#about to read 6, iclass 34, count 0 2006.217.08:15:51.28#ibcon#read 6, iclass 34, count 0 2006.217.08:15:51.28#ibcon#end of sib2, iclass 34, count 0 2006.217.08:15:51.28#ibcon#*mode == 0, iclass 34, count 0 2006.217.08:15:51.28#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.217.08:15:51.28#ibcon#[28=FRQ=03,656.99\r\n] 2006.217.08:15:51.28#ibcon#*before write, iclass 34, count 0 2006.217.08:15:51.28#ibcon#enter sib2, iclass 34, count 0 2006.217.08:15:51.28#ibcon#flushed, iclass 34, count 0 2006.217.08:15:51.28#ibcon#about to write, iclass 34, count 0 2006.217.08:15:51.28#ibcon#wrote, iclass 34, count 0 2006.217.08:15:51.28#ibcon#about to read 3, iclass 34, count 0 2006.217.08:15:51.32#ibcon#read 3, iclass 34, count 0 2006.217.08:15:51.32#ibcon#about to read 4, iclass 34, count 0 2006.217.08:15:51.32#ibcon#read 4, iclass 34, count 0 2006.217.08:15:51.32#ibcon#about to read 5, iclass 34, count 0 2006.217.08:15:51.32#ibcon#read 5, iclass 34, count 0 2006.217.08:15:51.32#ibcon#about to read 6, iclass 34, count 0 2006.217.08:15:51.32#ibcon#read 6, iclass 34, count 0 2006.217.08:15:51.32#ibcon#end of sib2, iclass 34, count 0 2006.217.08:15:51.32#ibcon#*after write, iclass 34, count 0 2006.217.08:15:51.32#ibcon#*before return 0, iclass 34, count 0 2006.217.08:15:51.32#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.217.08:15:51.32#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.217.08:15:51.32#ibcon#about to clear, iclass 34 cls_cnt 0 2006.217.08:15:51.32#ibcon#cleared, iclass 34 cls_cnt 0 2006.217.08:15:51.32$vc4f8/vb=3,4 2006.217.08:15:51.32#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.217.08:15:51.32#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.217.08:15:51.32#ibcon#ireg 11 cls_cnt 2 2006.217.08:15:51.32#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.217.08:15:51.37#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.217.08:15:51.37#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.217.08:15:51.38#ibcon#enter wrdev, iclass 36, count 2 2006.217.08:15:51.38#ibcon#first serial, iclass 36, count 2 2006.217.08:15:51.38#ibcon#enter sib2, iclass 36, count 2 2006.217.08:15:51.38#ibcon#flushed, iclass 36, count 2 2006.217.08:15:51.38#ibcon#about to write, iclass 36, count 2 2006.217.08:15:51.38#ibcon#wrote, iclass 36, count 2 2006.217.08:15:51.38#ibcon#about to read 3, iclass 36, count 2 2006.217.08:15:51.39#ibcon#read 3, iclass 36, count 2 2006.217.08:15:51.40#ibcon#about to read 4, iclass 36, count 2 2006.217.08:15:51.40#ibcon#read 4, iclass 36, count 2 2006.217.08:15:51.40#ibcon#about to read 5, iclass 36, count 2 2006.217.08:15:51.40#ibcon#read 5, iclass 36, count 2 2006.217.08:15:51.40#ibcon#about to read 6, iclass 36, count 2 2006.217.08:15:51.40#ibcon#read 6, iclass 36, count 2 2006.217.08:15:51.40#ibcon#end of sib2, iclass 36, count 2 2006.217.08:15:51.40#ibcon#*mode == 0, iclass 36, count 2 2006.217.08:15:51.40#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.217.08:15:51.40#ibcon#[27=AT03-04\r\n] 2006.217.08:15:51.40#ibcon#*before write, iclass 36, count 2 2006.217.08:15:51.40#ibcon#enter sib2, iclass 36, count 2 2006.217.08:15:51.40#ibcon#flushed, iclass 36, count 2 2006.217.08:15:51.40#ibcon#about to write, iclass 36, count 2 2006.217.08:15:51.40#ibcon#wrote, iclass 36, count 2 2006.217.08:15:51.40#ibcon#about to read 3, iclass 36, count 2 2006.217.08:15:51.42#ibcon#read 3, iclass 36, count 2 2006.217.08:15:51.43#ibcon#about to read 4, iclass 36, count 2 2006.217.08:15:51.43#ibcon#read 4, iclass 36, count 2 2006.217.08:15:51.43#ibcon#about to read 5, iclass 36, count 2 2006.217.08:15:51.43#ibcon#read 5, iclass 36, count 2 2006.217.08:15:51.43#ibcon#about to read 6, iclass 36, count 2 2006.217.08:15:51.43#ibcon#read 6, iclass 36, count 2 2006.217.08:15:51.43#ibcon#end of sib2, iclass 36, count 2 2006.217.08:15:51.43#ibcon#*after write, iclass 36, count 2 2006.217.08:15:51.43#ibcon#*before return 0, iclass 36, count 2 2006.217.08:15:51.43#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.217.08:15:51.43#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.217.08:15:51.43#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.217.08:15:51.43#ibcon#ireg 7 cls_cnt 0 2006.217.08:15:51.43#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.217.08:15:51.54#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.217.08:15:51.54#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.217.08:15:51.55#ibcon#enter wrdev, iclass 36, count 0 2006.217.08:15:51.55#ibcon#first serial, iclass 36, count 0 2006.217.08:15:51.55#ibcon#enter sib2, iclass 36, count 0 2006.217.08:15:51.55#ibcon#flushed, iclass 36, count 0 2006.217.08:15:51.55#ibcon#about to write, iclass 36, count 0 2006.217.08:15:51.55#ibcon#wrote, iclass 36, count 0 2006.217.08:15:51.55#ibcon#about to read 3, iclass 36, count 0 2006.217.08:15:51.56#ibcon#read 3, iclass 36, count 0 2006.217.08:15:51.57#ibcon#about to read 4, iclass 36, count 0 2006.217.08:15:51.57#ibcon#read 4, iclass 36, count 0 2006.217.08:15:51.57#ibcon#about to read 5, iclass 36, count 0 2006.217.08:15:51.57#ibcon#read 5, iclass 36, count 0 2006.217.08:15:51.57#ibcon#about to read 6, iclass 36, count 0 2006.217.08:15:51.57#ibcon#read 6, iclass 36, count 0 2006.217.08:15:51.57#ibcon#end of sib2, iclass 36, count 0 2006.217.08:15:51.57#ibcon#*mode == 0, iclass 36, count 0 2006.217.08:15:51.57#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.217.08:15:51.57#ibcon#[27=USB\r\n] 2006.217.08:15:51.57#ibcon#*before write, iclass 36, count 0 2006.217.08:15:51.57#ibcon#enter sib2, iclass 36, count 0 2006.217.08:15:51.57#ibcon#flushed, iclass 36, count 0 2006.217.08:15:51.57#ibcon#about to write, iclass 36, count 0 2006.217.08:15:51.57#ibcon#wrote, iclass 36, count 0 2006.217.08:15:51.57#ibcon#about to read 3, iclass 36, count 0 2006.217.08:15:51.59#ibcon#read 3, iclass 36, count 0 2006.217.08:15:51.60#ibcon#about to read 4, iclass 36, count 0 2006.217.08:15:51.60#ibcon#read 4, iclass 36, count 0 2006.217.08:15:51.60#ibcon#about to read 5, iclass 36, count 0 2006.217.08:15:51.60#ibcon#read 5, iclass 36, count 0 2006.217.08:15:51.60#ibcon#about to read 6, iclass 36, count 0 2006.217.08:15:51.60#ibcon#read 6, iclass 36, count 0 2006.217.08:15:51.60#ibcon#end of sib2, iclass 36, count 0 2006.217.08:15:51.60#ibcon#*after write, iclass 36, count 0 2006.217.08:15:51.60#ibcon#*before return 0, iclass 36, count 0 2006.217.08:15:51.60#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.217.08:15:51.60#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.217.08:15:51.60#ibcon#about to clear, iclass 36 cls_cnt 0 2006.217.08:15:51.60#ibcon#cleared, iclass 36 cls_cnt 0 2006.217.08:15:51.60$vc4f8/vblo=4,712.99 2006.217.08:15:51.60#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.217.08:15:51.60#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.217.08:15:51.60#ibcon#ireg 17 cls_cnt 0 2006.217.08:15:51.60#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.217.08:15:51.60#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.217.08:15:51.60#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.217.08:15:51.60#ibcon#enter wrdev, iclass 38, count 0 2006.217.08:15:51.60#ibcon#first serial, iclass 38, count 0 2006.217.08:15:51.60#ibcon#enter sib2, iclass 38, count 0 2006.217.08:15:51.60#ibcon#flushed, iclass 38, count 0 2006.217.08:15:51.60#ibcon#about to write, iclass 38, count 0 2006.217.08:15:51.60#ibcon#wrote, iclass 38, count 0 2006.217.08:15:51.60#ibcon#about to read 3, iclass 38, count 0 2006.217.08:15:51.61#ibcon#read 3, iclass 38, count 0 2006.217.08:15:51.62#ibcon#about to read 4, iclass 38, count 0 2006.217.08:15:51.62#ibcon#read 4, iclass 38, count 0 2006.217.08:15:51.62#ibcon#about to read 5, iclass 38, count 0 2006.217.08:15:51.62#ibcon#read 5, iclass 38, count 0 2006.217.08:15:51.62#ibcon#about to read 6, iclass 38, count 0 2006.217.08:15:51.62#ibcon#read 6, iclass 38, count 0 2006.217.08:15:51.62#ibcon#end of sib2, iclass 38, count 0 2006.217.08:15:51.62#ibcon#*mode == 0, iclass 38, count 0 2006.217.08:15:51.62#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.217.08:15:51.62#ibcon#[28=FRQ=04,712.99\r\n] 2006.217.08:15:51.62#ibcon#*before write, iclass 38, count 0 2006.217.08:15:51.62#ibcon#enter sib2, iclass 38, count 0 2006.217.08:15:51.62#ibcon#flushed, iclass 38, count 0 2006.217.08:15:51.62#ibcon#about to write, iclass 38, count 0 2006.217.08:15:51.62#ibcon#wrote, iclass 38, count 0 2006.217.08:15:51.62#ibcon#about to read 3, iclass 38, count 0 2006.217.08:15:51.65#ibcon#read 3, iclass 38, count 0 2006.217.08:15:51.66#ibcon#about to read 4, iclass 38, count 0 2006.217.08:15:51.66#ibcon#read 4, iclass 38, count 0 2006.217.08:15:51.66#ibcon#about to read 5, iclass 38, count 0 2006.217.08:15:51.66#ibcon#read 5, iclass 38, count 0 2006.217.08:15:51.66#ibcon#about to read 6, iclass 38, count 0 2006.217.08:15:51.66#ibcon#read 6, iclass 38, count 0 2006.217.08:15:51.66#ibcon#end of sib2, iclass 38, count 0 2006.217.08:15:51.66#ibcon#*after write, iclass 38, count 0 2006.217.08:15:51.66#ibcon#*before return 0, iclass 38, count 0 2006.217.08:15:51.66#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.217.08:15:51.66#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.217.08:15:51.66#ibcon#about to clear, iclass 38 cls_cnt 0 2006.217.08:15:51.66#ibcon#cleared, iclass 38 cls_cnt 0 2006.217.08:15:51.66$vc4f8/vb=4,4 2006.217.08:15:51.66#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.217.08:15:51.66#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.217.08:15:51.66#ibcon#ireg 11 cls_cnt 2 2006.217.08:15:51.66#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.217.08:15:51.71#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.217.08:15:51.71#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.217.08:15:51.72#ibcon#enter wrdev, iclass 40, count 2 2006.217.08:15:51.72#ibcon#first serial, iclass 40, count 2 2006.217.08:15:51.72#ibcon#enter sib2, iclass 40, count 2 2006.217.08:15:51.72#ibcon#flushed, iclass 40, count 2 2006.217.08:15:51.72#ibcon#about to write, iclass 40, count 2 2006.217.08:15:51.72#ibcon#wrote, iclass 40, count 2 2006.217.08:15:51.72#ibcon#about to read 3, iclass 40, count 2 2006.217.08:15:51.73#ibcon#read 3, iclass 40, count 2 2006.217.08:15:51.74#ibcon#about to read 4, iclass 40, count 2 2006.217.08:15:51.74#ibcon#read 4, iclass 40, count 2 2006.217.08:15:51.74#ibcon#about to read 5, iclass 40, count 2 2006.217.08:15:51.74#ibcon#read 5, iclass 40, count 2 2006.217.08:15:51.74#ibcon#about to read 6, iclass 40, count 2 2006.217.08:15:51.74#ibcon#read 6, iclass 40, count 2 2006.217.08:15:51.74#ibcon#end of sib2, iclass 40, count 2 2006.217.08:15:51.74#ibcon#*mode == 0, iclass 40, count 2 2006.217.08:15:51.74#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.217.08:15:51.74#ibcon#[27=AT04-04\r\n] 2006.217.08:15:51.74#ibcon#*before write, iclass 40, count 2 2006.217.08:15:51.74#ibcon#enter sib2, iclass 40, count 2 2006.217.08:15:51.74#ibcon#flushed, iclass 40, count 2 2006.217.08:15:51.74#ibcon#about to write, iclass 40, count 2 2006.217.08:15:51.74#ibcon#wrote, iclass 40, count 2 2006.217.08:15:51.74#ibcon#about to read 3, iclass 40, count 2 2006.217.08:15:51.76#ibcon#read 3, iclass 40, count 2 2006.217.08:15:51.77#ibcon#about to read 4, iclass 40, count 2 2006.217.08:15:51.77#ibcon#read 4, iclass 40, count 2 2006.217.08:15:51.77#ibcon#about to read 5, iclass 40, count 2 2006.217.08:15:51.77#ibcon#read 5, iclass 40, count 2 2006.217.08:15:51.77#ibcon#about to read 6, iclass 40, count 2 2006.217.08:15:51.77#ibcon#read 6, iclass 40, count 2 2006.217.08:15:51.77#ibcon#end of sib2, iclass 40, count 2 2006.217.08:15:51.77#ibcon#*after write, iclass 40, count 2 2006.217.08:15:51.77#ibcon#*before return 0, iclass 40, count 2 2006.217.08:15:51.77#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.217.08:15:51.77#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.217.08:15:51.77#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.217.08:15:51.77#ibcon#ireg 7 cls_cnt 0 2006.217.08:15:51.77#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.217.08:15:51.88#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.217.08:15:51.88#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.217.08:15:51.89#ibcon#enter wrdev, iclass 40, count 0 2006.217.08:15:51.89#ibcon#first serial, iclass 40, count 0 2006.217.08:15:51.89#ibcon#enter sib2, iclass 40, count 0 2006.217.08:15:51.89#ibcon#flushed, iclass 40, count 0 2006.217.08:15:51.89#ibcon#about to write, iclass 40, count 0 2006.217.08:15:51.89#ibcon#wrote, iclass 40, count 0 2006.217.08:15:51.89#ibcon#about to read 3, iclass 40, count 0 2006.217.08:15:51.90#ibcon#read 3, iclass 40, count 0 2006.217.08:15:51.91#ibcon#about to read 4, iclass 40, count 0 2006.217.08:15:51.91#ibcon#read 4, iclass 40, count 0 2006.217.08:15:51.91#ibcon#about to read 5, iclass 40, count 0 2006.217.08:15:51.91#ibcon#read 5, iclass 40, count 0 2006.217.08:15:51.91#ibcon#about to read 6, iclass 40, count 0 2006.217.08:15:51.91#ibcon#read 6, iclass 40, count 0 2006.217.08:15:51.91#ibcon#end of sib2, iclass 40, count 0 2006.217.08:15:51.91#ibcon#*mode == 0, iclass 40, count 0 2006.217.08:15:51.91#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.217.08:15:51.91#ibcon#[27=USB\r\n] 2006.217.08:15:51.91#ibcon#*before write, iclass 40, count 0 2006.217.08:15:51.91#ibcon#enter sib2, iclass 40, count 0 2006.217.08:15:51.91#ibcon#flushed, iclass 40, count 0 2006.217.08:15:51.91#ibcon#about to write, iclass 40, count 0 2006.217.08:15:51.91#ibcon#wrote, iclass 40, count 0 2006.217.08:15:51.91#ibcon#about to read 3, iclass 40, count 0 2006.217.08:15:51.93#ibcon#read 3, iclass 40, count 0 2006.217.08:15:51.94#ibcon#about to read 4, iclass 40, count 0 2006.217.08:15:51.94#ibcon#read 4, iclass 40, count 0 2006.217.08:15:51.94#ibcon#about to read 5, iclass 40, count 0 2006.217.08:15:51.94#ibcon#read 5, iclass 40, count 0 2006.217.08:15:51.94#ibcon#about to read 6, iclass 40, count 0 2006.217.08:15:51.94#ibcon#read 6, iclass 40, count 0 2006.217.08:15:51.94#ibcon#end of sib2, iclass 40, count 0 2006.217.08:15:51.94#ibcon#*after write, iclass 40, count 0 2006.217.08:15:51.94#ibcon#*before return 0, iclass 40, count 0 2006.217.08:15:51.94#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.217.08:15:51.94#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.217.08:15:51.94#ibcon#about to clear, iclass 40 cls_cnt 0 2006.217.08:15:51.94#ibcon#cleared, iclass 40 cls_cnt 0 2006.217.08:15:51.94$vc4f8/vblo=5,744.99 2006.217.08:15:51.94#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.217.08:15:51.94#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.217.08:15:51.94#ibcon#ireg 17 cls_cnt 0 2006.217.08:15:51.94#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.217.08:15:51.94#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.217.08:15:51.94#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.217.08:15:51.94#ibcon#enter wrdev, iclass 4, count 0 2006.217.08:15:51.94#ibcon#first serial, iclass 4, count 0 2006.217.08:15:51.94#ibcon#enter sib2, iclass 4, count 0 2006.217.08:15:51.94#ibcon#flushed, iclass 4, count 0 2006.217.08:15:51.94#ibcon#about to write, iclass 4, count 0 2006.217.08:15:51.94#ibcon#wrote, iclass 4, count 0 2006.217.08:15:51.94#ibcon#about to read 3, iclass 4, count 0 2006.217.08:15:51.95#ibcon#read 3, iclass 4, count 0 2006.217.08:15:51.96#ibcon#about to read 4, iclass 4, count 0 2006.217.08:15:51.96#ibcon#read 4, iclass 4, count 0 2006.217.08:15:51.96#ibcon#about to read 5, iclass 4, count 0 2006.217.08:15:51.96#ibcon#read 5, iclass 4, count 0 2006.217.08:15:51.96#ibcon#about to read 6, iclass 4, count 0 2006.217.08:15:51.96#ibcon#read 6, iclass 4, count 0 2006.217.08:15:51.96#ibcon#end of sib2, iclass 4, count 0 2006.217.08:15:51.96#ibcon#*mode == 0, iclass 4, count 0 2006.217.08:15:51.96#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.217.08:15:51.96#ibcon#[28=FRQ=05,744.99\r\n] 2006.217.08:15:51.96#ibcon#*before write, iclass 4, count 0 2006.217.08:15:51.96#ibcon#enter sib2, iclass 4, count 0 2006.217.08:15:51.96#ibcon#flushed, iclass 4, count 0 2006.217.08:15:51.96#ibcon#about to write, iclass 4, count 0 2006.217.08:15:51.96#ibcon#wrote, iclass 4, count 0 2006.217.08:15:51.96#ibcon#about to read 3, iclass 4, count 0 2006.217.08:15:51.99#ibcon#read 3, iclass 4, count 0 2006.217.08:15:52.00#ibcon#about to read 4, iclass 4, count 0 2006.217.08:15:52.00#ibcon#read 4, iclass 4, count 0 2006.217.08:15:52.00#ibcon#about to read 5, iclass 4, count 0 2006.217.08:15:52.00#ibcon#read 5, iclass 4, count 0 2006.217.08:15:52.00#ibcon#about to read 6, iclass 4, count 0 2006.217.08:15:52.00#ibcon#read 6, iclass 4, count 0 2006.217.08:15:52.00#ibcon#end of sib2, iclass 4, count 0 2006.217.08:15:52.00#ibcon#*after write, iclass 4, count 0 2006.217.08:15:52.00#ibcon#*before return 0, iclass 4, count 0 2006.217.08:15:52.00#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.217.08:15:52.00#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.217.08:15:52.00#ibcon#about to clear, iclass 4 cls_cnt 0 2006.217.08:15:52.00#ibcon#cleared, iclass 4 cls_cnt 0 2006.217.08:15:52.00$vc4f8/vb=5,4 2006.217.08:15:52.00#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.217.08:15:52.00#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.217.08:15:52.00#ibcon#ireg 11 cls_cnt 2 2006.217.08:15:52.00#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.217.08:15:52.05#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.217.08:15:52.05#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.217.08:15:52.06#ibcon#enter wrdev, iclass 6, count 2 2006.217.08:15:52.06#ibcon#first serial, iclass 6, count 2 2006.217.08:15:52.06#ibcon#enter sib2, iclass 6, count 2 2006.217.08:15:52.06#ibcon#flushed, iclass 6, count 2 2006.217.08:15:52.06#ibcon#about to write, iclass 6, count 2 2006.217.08:15:52.06#ibcon#wrote, iclass 6, count 2 2006.217.08:15:52.06#ibcon#about to read 3, iclass 6, count 2 2006.217.08:15:52.07#ibcon#read 3, iclass 6, count 2 2006.217.08:15:52.08#ibcon#about to read 4, iclass 6, count 2 2006.217.08:15:52.08#ibcon#read 4, iclass 6, count 2 2006.217.08:15:52.08#ibcon#about to read 5, iclass 6, count 2 2006.217.08:15:52.08#ibcon#read 5, iclass 6, count 2 2006.217.08:15:52.08#ibcon#about to read 6, iclass 6, count 2 2006.217.08:15:52.08#ibcon#read 6, iclass 6, count 2 2006.217.08:15:52.08#ibcon#end of sib2, iclass 6, count 2 2006.217.08:15:52.08#ibcon#*mode == 0, iclass 6, count 2 2006.217.08:15:52.08#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.217.08:15:52.08#ibcon#[27=AT05-04\r\n] 2006.217.08:15:52.08#ibcon#*before write, iclass 6, count 2 2006.217.08:15:52.08#ibcon#enter sib2, iclass 6, count 2 2006.217.08:15:52.08#ibcon#flushed, iclass 6, count 2 2006.217.08:15:52.08#ibcon#about to write, iclass 6, count 2 2006.217.08:15:52.08#ibcon#wrote, iclass 6, count 2 2006.217.08:15:52.08#ibcon#about to read 3, iclass 6, count 2 2006.217.08:15:52.10#ibcon#read 3, iclass 6, count 2 2006.217.08:15:52.11#ibcon#about to read 4, iclass 6, count 2 2006.217.08:15:52.11#ibcon#read 4, iclass 6, count 2 2006.217.08:15:52.11#ibcon#about to read 5, iclass 6, count 2 2006.217.08:15:52.11#ibcon#read 5, iclass 6, count 2 2006.217.08:15:52.11#ibcon#about to read 6, iclass 6, count 2 2006.217.08:15:52.11#ibcon#read 6, iclass 6, count 2 2006.217.08:15:52.11#ibcon#end of sib2, iclass 6, count 2 2006.217.08:15:52.11#ibcon#*after write, iclass 6, count 2 2006.217.08:15:52.11#ibcon#*before return 0, iclass 6, count 2 2006.217.08:15:52.11#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.217.08:15:52.11#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.217.08:15:52.11#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.217.08:15:52.11#ibcon#ireg 7 cls_cnt 0 2006.217.08:15:52.11#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.217.08:15:52.23#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.217.08:15:52.23#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.217.08:15:52.23#ibcon#enter wrdev, iclass 6, count 0 2006.217.08:15:52.23#ibcon#first serial, iclass 6, count 0 2006.217.08:15:52.23#ibcon#enter sib2, iclass 6, count 0 2006.217.08:15:52.23#ibcon#flushed, iclass 6, count 0 2006.217.08:15:52.23#ibcon#about to write, iclass 6, count 0 2006.217.08:15:52.23#ibcon#wrote, iclass 6, count 0 2006.217.08:15:52.23#ibcon#about to read 3, iclass 6, count 0 2006.217.08:15:52.24#ibcon#read 3, iclass 6, count 0 2006.217.08:15:52.25#ibcon#about to read 4, iclass 6, count 0 2006.217.08:15:52.25#ibcon#read 4, iclass 6, count 0 2006.217.08:15:52.25#ibcon#about to read 5, iclass 6, count 0 2006.217.08:15:52.25#ibcon#read 5, iclass 6, count 0 2006.217.08:15:52.25#ibcon#about to read 6, iclass 6, count 0 2006.217.08:15:52.25#ibcon#read 6, iclass 6, count 0 2006.217.08:15:52.25#ibcon#end of sib2, iclass 6, count 0 2006.217.08:15:52.25#ibcon#*mode == 0, iclass 6, count 0 2006.217.08:15:52.25#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.217.08:15:52.25#ibcon#[27=USB\r\n] 2006.217.08:15:52.25#ibcon#*before write, iclass 6, count 0 2006.217.08:15:52.25#ibcon#enter sib2, iclass 6, count 0 2006.217.08:15:52.25#ibcon#flushed, iclass 6, count 0 2006.217.08:15:52.25#ibcon#about to write, iclass 6, count 0 2006.217.08:15:52.25#ibcon#wrote, iclass 6, count 0 2006.217.08:15:52.25#ibcon#about to read 3, iclass 6, count 0 2006.217.08:15:52.27#ibcon#read 3, iclass 6, count 0 2006.217.08:15:52.28#ibcon#about to read 4, iclass 6, count 0 2006.217.08:15:52.28#ibcon#read 4, iclass 6, count 0 2006.217.08:15:52.28#ibcon#about to read 5, iclass 6, count 0 2006.217.08:15:52.28#ibcon#read 5, iclass 6, count 0 2006.217.08:15:52.28#ibcon#about to read 6, iclass 6, count 0 2006.217.08:15:52.28#ibcon#read 6, iclass 6, count 0 2006.217.08:15:52.28#ibcon#end of sib2, iclass 6, count 0 2006.217.08:15:52.28#ibcon#*after write, iclass 6, count 0 2006.217.08:15:52.28#ibcon#*before return 0, iclass 6, count 0 2006.217.08:15:52.28#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.217.08:15:52.28#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.217.08:15:52.28#ibcon#about to clear, iclass 6 cls_cnt 0 2006.217.08:15:52.28#ibcon#cleared, iclass 6 cls_cnt 0 2006.217.08:15:52.28$vc4f8/vblo=6,752.99 2006.217.08:15:52.28#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.217.08:15:52.28#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.217.08:15:52.28#ibcon#ireg 17 cls_cnt 0 2006.217.08:15:52.28#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.217.08:15:52.28#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.217.08:15:52.28#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.217.08:15:52.28#ibcon#enter wrdev, iclass 10, count 0 2006.217.08:15:52.28#ibcon#first serial, iclass 10, count 0 2006.217.08:15:52.28#ibcon#enter sib2, iclass 10, count 0 2006.217.08:15:52.28#ibcon#flushed, iclass 10, count 0 2006.217.08:15:52.28#ibcon#about to write, iclass 10, count 0 2006.217.08:15:52.28#ibcon#wrote, iclass 10, count 0 2006.217.08:15:52.28#ibcon#about to read 3, iclass 10, count 0 2006.217.08:15:52.29#ibcon#read 3, iclass 10, count 0 2006.217.08:15:52.30#ibcon#about to read 4, iclass 10, count 0 2006.217.08:15:52.30#ibcon#read 4, iclass 10, count 0 2006.217.08:15:52.30#ibcon#about to read 5, iclass 10, count 0 2006.217.08:15:52.30#ibcon#read 5, iclass 10, count 0 2006.217.08:15:52.30#ibcon#about to read 6, iclass 10, count 0 2006.217.08:15:52.30#ibcon#read 6, iclass 10, count 0 2006.217.08:15:52.30#ibcon#end of sib2, iclass 10, count 0 2006.217.08:15:52.30#ibcon#*mode == 0, iclass 10, count 0 2006.217.08:15:52.30#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.217.08:15:52.30#ibcon#[28=FRQ=06,752.99\r\n] 2006.217.08:15:52.30#ibcon#*before write, iclass 10, count 0 2006.217.08:15:52.30#ibcon#enter sib2, iclass 10, count 0 2006.217.08:15:52.30#ibcon#flushed, iclass 10, count 0 2006.217.08:15:52.30#ibcon#about to write, iclass 10, count 0 2006.217.08:15:52.30#ibcon#wrote, iclass 10, count 0 2006.217.08:15:52.30#ibcon#about to read 3, iclass 10, count 0 2006.217.08:15:52.33#ibcon#read 3, iclass 10, count 0 2006.217.08:15:52.34#ibcon#about to read 4, iclass 10, count 0 2006.217.08:15:52.34#ibcon#read 4, iclass 10, count 0 2006.217.08:15:52.34#ibcon#about to read 5, iclass 10, count 0 2006.217.08:15:52.34#ibcon#read 5, iclass 10, count 0 2006.217.08:15:52.34#ibcon#about to read 6, iclass 10, count 0 2006.217.08:15:52.34#ibcon#read 6, iclass 10, count 0 2006.217.08:15:52.34#ibcon#end of sib2, iclass 10, count 0 2006.217.08:15:52.34#ibcon#*after write, iclass 10, count 0 2006.217.08:15:52.34#ibcon#*before return 0, iclass 10, count 0 2006.217.08:15:52.34#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.217.08:15:52.34#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.217.08:15:52.34#ibcon#about to clear, iclass 10 cls_cnt 0 2006.217.08:15:52.34#ibcon#cleared, iclass 10 cls_cnt 0 2006.217.08:15:52.34$vc4f8/vb=6,4 2006.217.08:15:52.34#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.217.08:15:52.34#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.217.08:15:52.34#ibcon#ireg 11 cls_cnt 2 2006.217.08:15:52.34#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.217.08:15:52.39#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.217.08:15:52.39#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.217.08:15:52.40#ibcon#enter wrdev, iclass 12, count 2 2006.217.08:15:52.40#ibcon#first serial, iclass 12, count 2 2006.217.08:15:52.40#ibcon#enter sib2, iclass 12, count 2 2006.217.08:15:52.40#ibcon#flushed, iclass 12, count 2 2006.217.08:15:52.40#ibcon#about to write, iclass 12, count 2 2006.217.08:15:52.40#ibcon#wrote, iclass 12, count 2 2006.217.08:15:52.40#ibcon#about to read 3, iclass 12, count 2 2006.217.08:15:52.41#ibcon#read 3, iclass 12, count 2 2006.217.08:15:52.42#ibcon#about to read 4, iclass 12, count 2 2006.217.08:15:52.42#ibcon#read 4, iclass 12, count 2 2006.217.08:15:52.42#ibcon#about to read 5, iclass 12, count 2 2006.217.08:15:52.42#ibcon#read 5, iclass 12, count 2 2006.217.08:15:52.42#ibcon#about to read 6, iclass 12, count 2 2006.217.08:15:52.42#ibcon#read 6, iclass 12, count 2 2006.217.08:15:52.42#ibcon#end of sib2, iclass 12, count 2 2006.217.08:15:52.42#ibcon#*mode == 0, iclass 12, count 2 2006.217.08:15:52.42#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.217.08:15:52.42#ibcon#[27=AT06-04\r\n] 2006.217.08:15:52.42#ibcon#*before write, iclass 12, count 2 2006.217.08:15:52.42#ibcon#enter sib2, iclass 12, count 2 2006.217.08:15:52.42#ibcon#flushed, iclass 12, count 2 2006.217.08:15:52.42#ibcon#about to write, iclass 12, count 2 2006.217.08:15:52.42#ibcon#wrote, iclass 12, count 2 2006.217.08:15:52.42#ibcon#about to read 3, iclass 12, count 2 2006.217.08:15:52.44#ibcon#read 3, iclass 12, count 2 2006.217.08:15:52.45#ibcon#about to read 4, iclass 12, count 2 2006.217.08:15:52.45#ibcon#read 4, iclass 12, count 2 2006.217.08:15:52.45#ibcon#about to read 5, iclass 12, count 2 2006.217.08:15:52.45#ibcon#read 5, iclass 12, count 2 2006.217.08:15:52.45#ibcon#about to read 6, iclass 12, count 2 2006.217.08:15:52.45#ibcon#read 6, iclass 12, count 2 2006.217.08:15:52.45#ibcon#end of sib2, iclass 12, count 2 2006.217.08:15:52.45#ibcon#*after write, iclass 12, count 2 2006.217.08:15:52.45#ibcon#*before return 0, iclass 12, count 2 2006.217.08:15:52.45#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.217.08:15:52.45#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.217.08:15:52.45#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.217.08:15:52.45#ibcon#ireg 7 cls_cnt 0 2006.217.08:15:52.45#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.217.08:15:52.56#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.217.08:15:52.56#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.217.08:15:52.57#ibcon#enter wrdev, iclass 12, count 0 2006.217.08:15:52.57#ibcon#first serial, iclass 12, count 0 2006.217.08:15:52.57#ibcon#enter sib2, iclass 12, count 0 2006.217.08:15:52.57#ibcon#flushed, iclass 12, count 0 2006.217.08:15:52.57#ibcon#about to write, iclass 12, count 0 2006.217.08:15:52.57#ibcon#wrote, iclass 12, count 0 2006.217.08:15:52.57#ibcon#about to read 3, iclass 12, count 0 2006.217.08:15:52.58#ibcon#read 3, iclass 12, count 0 2006.217.08:15:52.59#ibcon#about to read 4, iclass 12, count 0 2006.217.08:15:52.59#ibcon#read 4, iclass 12, count 0 2006.217.08:15:52.59#ibcon#about to read 5, iclass 12, count 0 2006.217.08:15:52.59#ibcon#read 5, iclass 12, count 0 2006.217.08:15:52.59#ibcon#about to read 6, iclass 12, count 0 2006.217.08:15:52.59#ibcon#read 6, iclass 12, count 0 2006.217.08:15:52.59#ibcon#end of sib2, iclass 12, count 0 2006.217.08:15:52.59#ibcon#*mode == 0, iclass 12, count 0 2006.217.08:15:52.59#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.217.08:15:52.59#ibcon#[27=USB\r\n] 2006.217.08:15:52.59#ibcon#*before write, iclass 12, count 0 2006.217.08:15:52.59#ibcon#enter sib2, iclass 12, count 0 2006.217.08:15:52.59#ibcon#flushed, iclass 12, count 0 2006.217.08:15:52.59#ibcon#about to write, iclass 12, count 0 2006.217.08:15:52.59#ibcon#wrote, iclass 12, count 0 2006.217.08:15:52.59#ibcon#about to read 3, iclass 12, count 0 2006.217.08:15:52.61#ibcon#read 3, iclass 12, count 0 2006.217.08:15:52.62#ibcon#about to read 4, iclass 12, count 0 2006.217.08:15:52.62#ibcon#read 4, iclass 12, count 0 2006.217.08:15:52.62#ibcon#about to read 5, iclass 12, count 0 2006.217.08:15:52.62#ibcon#read 5, iclass 12, count 0 2006.217.08:15:52.62#ibcon#about to read 6, iclass 12, count 0 2006.217.08:15:52.62#ibcon#read 6, iclass 12, count 0 2006.217.08:15:52.62#ibcon#end of sib2, iclass 12, count 0 2006.217.08:15:52.62#ibcon#*after write, iclass 12, count 0 2006.217.08:15:52.62#ibcon#*before return 0, iclass 12, count 0 2006.217.08:15:52.62#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.217.08:15:52.62#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.217.08:15:52.62#ibcon#about to clear, iclass 12 cls_cnt 0 2006.217.08:15:52.62#ibcon#cleared, iclass 12 cls_cnt 0 2006.217.08:15:52.62$vc4f8/vabw=wide 2006.217.08:15:52.62#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.217.08:15:52.62#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.217.08:15:52.62#ibcon#ireg 8 cls_cnt 0 2006.217.08:15:52.62#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.217.08:15:52.62#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.217.08:15:52.62#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.217.08:15:52.62#ibcon#enter wrdev, iclass 14, count 0 2006.217.08:15:52.62#ibcon#first serial, iclass 14, count 0 2006.217.08:15:52.62#ibcon#enter sib2, iclass 14, count 0 2006.217.08:15:52.62#ibcon#flushed, iclass 14, count 0 2006.217.08:15:52.62#ibcon#about to write, iclass 14, count 0 2006.217.08:15:52.62#ibcon#wrote, iclass 14, count 0 2006.217.08:15:52.62#ibcon#about to read 3, iclass 14, count 0 2006.217.08:15:52.63#ibcon#read 3, iclass 14, count 0 2006.217.08:15:52.64#ibcon#about to read 4, iclass 14, count 0 2006.217.08:15:52.64#ibcon#read 4, iclass 14, count 0 2006.217.08:15:52.64#ibcon#about to read 5, iclass 14, count 0 2006.217.08:15:52.64#ibcon#read 5, iclass 14, count 0 2006.217.08:15:52.64#ibcon#about to read 6, iclass 14, count 0 2006.217.08:15:52.64#ibcon#read 6, iclass 14, count 0 2006.217.08:15:52.64#ibcon#end of sib2, iclass 14, count 0 2006.217.08:15:52.64#ibcon#*mode == 0, iclass 14, count 0 2006.217.08:15:52.64#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.217.08:15:52.64#ibcon#[25=BW32\r\n] 2006.217.08:15:52.64#ibcon#*before write, iclass 14, count 0 2006.217.08:15:52.64#ibcon#enter sib2, iclass 14, count 0 2006.217.08:15:52.64#ibcon#flushed, iclass 14, count 0 2006.217.08:15:52.64#ibcon#about to write, iclass 14, count 0 2006.217.08:15:52.64#ibcon#wrote, iclass 14, count 0 2006.217.08:15:52.64#ibcon#about to read 3, iclass 14, count 0 2006.217.08:15:52.66#ibcon#read 3, iclass 14, count 0 2006.217.08:15:52.67#ibcon#about to read 4, iclass 14, count 0 2006.217.08:15:52.67#ibcon#read 4, iclass 14, count 0 2006.217.08:15:52.67#ibcon#about to read 5, iclass 14, count 0 2006.217.08:15:52.67#ibcon#read 5, iclass 14, count 0 2006.217.08:15:52.67#ibcon#about to read 6, iclass 14, count 0 2006.217.08:15:52.67#ibcon#read 6, iclass 14, count 0 2006.217.08:15:52.67#ibcon#end of sib2, iclass 14, count 0 2006.217.08:15:52.67#ibcon#*after write, iclass 14, count 0 2006.217.08:15:52.67#ibcon#*before return 0, iclass 14, count 0 2006.217.08:15:52.67#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.217.08:15:52.67#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.217.08:15:52.67#ibcon#about to clear, iclass 14 cls_cnt 0 2006.217.08:15:52.67#ibcon#cleared, iclass 14 cls_cnt 0 2006.217.08:15:52.67$vc4f8/vbbw=wide 2006.217.08:15:52.67#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.217.08:15:52.67#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.217.08:15:52.67#ibcon#ireg 8 cls_cnt 0 2006.217.08:15:52.67#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.217.08:15:52.73#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.217.08:15:52.73#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.217.08:15:52.74#ibcon#enter wrdev, iclass 16, count 0 2006.217.08:15:52.74#ibcon#first serial, iclass 16, count 0 2006.217.08:15:52.74#ibcon#enter sib2, iclass 16, count 0 2006.217.08:15:52.74#ibcon#flushed, iclass 16, count 0 2006.217.08:15:52.74#ibcon#about to write, iclass 16, count 0 2006.217.08:15:52.74#ibcon#wrote, iclass 16, count 0 2006.217.08:15:52.74#ibcon#about to read 3, iclass 16, count 0 2006.217.08:15:52.75#ibcon#read 3, iclass 16, count 0 2006.217.08:15:52.76#ibcon#about to read 4, iclass 16, count 0 2006.217.08:15:52.76#ibcon#read 4, iclass 16, count 0 2006.217.08:15:52.76#ibcon#about to read 5, iclass 16, count 0 2006.217.08:15:52.76#ibcon#read 5, iclass 16, count 0 2006.217.08:15:52.76#ibcon#about to read 6, iclass 16, count 0 2006.217.08:15:52.76#ibcon#read 6, iclass 16, count 0 2006.217.08:15:52.76#ibcon#end of sib2, iclass 16, count 0 2006.217.08:15:52.76#ibcon#*mode == 0, iclass 16, count 0 2006.217.08:15:52.76#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.217.08:15:52.76#ibcon#[27=BW32\r\n] 2006.217.08:15:52.76#ibcon#*before write, iclass 16, count 0 2006.217.08:15:52.76#ibcon#enter sib2, iclass 16, count 0 2006.217.08:15:52.76#ibcon#flushed, iclass 16, count 0 2006.217.08:15:52.76#ibcon#about to write, iclass 16, count 0 2006.217.08:15:52.76#ibcon#wrote, iclass 16, count 0 2006.217.08:15:52.76#ibcon#about to read 3, iclass 16, count 0 2006.217.08:15:52.78#ibcon#read 3, iclass 16, count 0 2006.217.08:15:52.79#ibcon#about to read 4, iclass 16, count 0 2006.217.08:15:52.79#ibcon#read 4, iclass 16, count 0 2006.217.08:15:52.79#ibcon#about to read 5, iclass 16, count 0 2006.217.08:15:52.79#ibcon#read 5, iclass 16, count 0 2006.217.08:15:52.79#ibcon#about to read 6, iclass 16, count 0 2006.217.08:15:52.79#ibcon#read 6, iclass 16, count 0 2006.217.08:15:52.79#ibcon#end of sib2, iclass 16, count 0 2006.217.08:15:52.79#ibcon#*after write, iclass 16, count 0 2006.217.08:15:52.79#ibcon#*before return 0, iclass 16, count 0 2006.217.08:15:52.79#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.217.08:15:52.79#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.217.08:15:52.79#ibcon#about to clear, iclass 16 cls_cnt 0 2006.217.08:15:52.79#ibcon#cleared, iclass 16 cls_cnt 0 2006.217.08:15:52.79$4f8m12a/ifd4f 2006.217.08:15:52.79$ifd4f/lo= 2006.217.08:15:52.79$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.217.08:15:52.79$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.217.08:15:52.79$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.217.08:15:52.79$ifd4f/patch= 2006.217.08:15:52.79$ifd4f/patch=lo1,a1,a2,a3,a4 2006.217.08:15:52.79$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.217.08:15:52.79$ifd4f/patch=lo3,a5,a6,a7,a8 2006.217.08:15:52.79$4f8m12a/"form=m,16.000,1:2 2006.217.08:15:52.79$4f8m12a/"tpicd 2006.217.08:15:52.79$4f8m12a/echo=off 2006.217.08:15:52.79$4f8m12a/xlog=off 2006.217.08:15:52.79:!2006.217.08:16:20 2006.217.08:16:02.12#trakl#Source acquired 2006.217.08:16:02.13#flagr#flagr/antenna,acquired 2006.217.08:16:20.02:preob 2006.217.08:16:21.14/onsource/TRACKING 2006.217.08:16:21.14:!2006.217.08:16:30 2006.217.08:16:30.02:data_valid=on 2006.217.08:16:30.02:midob 2006.217.08:16:31.15/onsource/TRACKING 2006.217.08:16:31.15/wx/30.56,1008.6,65 2006.217.08:16:31.25/cable/+6.3860E-03 2006.217.08:16:32.34/va/01,05,usb,yes,32,33 2006.217.08:16:32.34/va/02,04,usb,yes,29,31 2006.217.08:16:32.34/va/03,04,usb,yes,28,28 2006.217.08:16:32.34/va/04,04,usb,yes,31,33 2006.217.08:16:32.34/va/05,07,usb,yes,33,34 2006.217.08:16:32.34/va/06,06,usb,yes,32,31 2006.217.08:16:32.35/va/07,06,usb,yes,32,32 2006.217.08:16:32.35/va/08,07,usb,yes,30,30 2006.217.08:16:32.58/valo/01,532.99,yes,locked 2006.217.08:16:32.58/valo/02,572.99,yes,locked 2006.217.08:16:32.58/valo/03,672.99,yes,locked 2006.217.08:16:32.58/valo/04,832.99,yes,locked 2006.217.08:16:32.58/valo/05,652.99,yes,locked 2006.217.08:16:32.58/valo/06,772.99,yes,locked 2006.217.08:16:32.58/valo/07,832.99,yes,locked 2006.217.08:16:32.58/valo/08,852.99,yes,locked 2006.217.08:16:33.66/vb/01,04,usb,yes,30,29 2006.217.08:16:33.66/vb/02,04,usb,yes,32,34 2006.217.08:16:33.66/vb/03,04,usb,yes,28,32 2006.217.08:16:33.66/vb/04,04,usb,yes,29,29 2006.217.08:16:33.66/vb/05,04,usb,yes,28,32 2006.217.08:16:33.66/vb/06,04,usb,yes,29,32 2006.217.08:16:33.67/vb/07,04,usb,yes,31,31 2006.217.08:16:33.67/vb/08,04,usb,yes,28,32 2006.217.08:16:33.91/vblo/01,632.99,yes,locked 2006.217.08:16:33.91/vblo/02,640.99,yes,locked 2006.217.08:16:33.91/vblo/03,656.99,yes,locked 2006.217.08:16:33.91/vblo/04,712.99,yes,locked 2006.217.08:16:33.91/vblo/05,744.99,yes,locked 2006.217.08:16:33.91/vblo/06,752.99,yes,locked 2006.217.08:16:33.91/vblo/07,734.99,yes,locked 2006.217.08:16:33.91/vblo/08,744.99,yes,locked 2006.217.08:16:34.05/vabw/8 2006.217.08:16:34.20/vbbw/8 2006.217.08:16:34.29/xfe/off,on,15.2 2006.217.08:16:34.66/ifatt/23,28,28,28 2006.217.08:16:35.07/fmout-gps/S +4.53E-07 2006.217.08:16:35.15:!2006.217.08:17:40 2006.217.08:17:40.02:data_valid=off 2006.217.08:17:40.02:postob 2006.217.08:17:40.23/cable/+6.3879E-03 2006.217.08:17:40.24/wx/30.54,1008.6,65 2006.217.08:17:41.07/fmout-gps/S +4.53E-07 2006.217.08:17:41.08:scan_name=217-0818,k06217,60 2006.217.08:17:41.08:source=0804+499,080839.67,495036.5,2000.0,ccw 2006.217.08:17:41.15#flagr#flagr/antenna,new-source 2006.217.08:17:42.15:checkk5 2006.217.08:17:42.52/chk_autoobs//k5ts1/ autoobs is running! 2006.217.08:17:42.94/chk_autoobs//k5ts2/ autoobs is running! 2006.217.08:17:43.31/chk_autoobs//k5ts3/ autoobs is running! 2006.217.08:17:43.69/chk_autoobs//k5ts4/ autoobs is running! 2006.217.08:17:44.05/chk_obsdata//k5ts1/T2170816??a.dat file size is correct (nominal:560MB, actual:552MB). 2006.217.08:17:44.42/chk_obsdata//k5ts2/T2170816??b.dat file size is correct (nominal:560MB, actual:552MB). 2006.217.08:17:44.79/chk_obsdata//k5ts3/T2170816??c.dat file size is correct (nominal:560MB, actual:552MB). 2006.217.08:17:45.16/chk_obsdata//k5ts4/T2170816??d.dat file size is correct (nominal:560MB, actual:552MB). 2006.217.08:17:45.85/k5log//k5ts1_log_newline 2006.217.08:17:46.55/k5log//k5ts2_log_newline 2006.217.08:17:47.25/k5log//k5ts3_log_newline 2006.217.08:17:47.95/k5log//k5ts4_log_newline 2006.217.08:17:47.97/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.217.08:17:47.97:4f8m12a=2 2006.217.08:17:47.97$4f8m12a/echo=on 2006.217.08:17:47.97$4f8m12a/pcalon 2006.217.08:17:47.97$pcalon/"no phase cal control is implemented here 2006.217.08:17:47.97$4f8m12a/"tpicd=stop 2006.217.08:17:47.97$4f8m12a/vc4f8 2006.217.08:17:47.97$vc4f8/valo=1,532.99 2006.217.08:17:47.98#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.217.08:17:47.98#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.217.08:17:47.98#ibcon#ireg 17 cls_cnt 0 2006.217.08:17:47.98#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.217.08:17:47.98#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.217.08:17:47.98#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.217.08:17:47.98#ibcon#enter wrdev, iclass 27, count 0 2006.217.08:17:47.98#ibcon#first serial, iclass 27, count 0 2006.217.08:17:47.98#ibcon#enter sib2, iclass 27, count 0 2006.217.08:17:47.98#ibcon#flushed, iclass 27, count 0 2006.217.08:17:47.98#ibcon#about to write, iclass 27, count 0 2006.217.08:17:47.98#ibcon#wrote, iclass 27, count 0 2006.217.08:17:47.98#ibcon#about to read 3, iclass 27, count 0 2006.217.08:17:48.02#ibcon#read 3, iclass 27, count 0 2006.217.08:17:48.02#ibcon#about to read 4, iclass 27, count 0 2006.217.08:17:48.02#ibcon#read 4, iclass 27, count 0 2006.217.08:17:48.02#ibcon#about to read 5, iclass 27, count 0 2006.217.08:17:48.02#ibcon#read 5, iclass 27, count 0 2006.217.08:17:48.02#ibcon#about to read 6, iclass 27, count 0 2006.217.08:17:48.02#ibcon#read 6, iclass 27, count 0 2006.217.08:17:48.02#ibcon#end of sib2, iclass 27, count 0 2006.217.08:17:48.02#ibcon#*mode == 0, iclass 27, count 0 2006.217.08:17:48.02#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.217.08:17:48.02#ibcon#[26=FRQ=01,532.99\r\n] 2006.217.08:17:48.02#ibcon#*before write, iclass 27, count 0 2006.217.08:17:48.02#ibcon#enter sib2, iclass 27, count 0 2006.217.08:17:48.02#ibcon#flushed, iclass 27, count 0 2006.217.08:17:48.02#ibcon#about to write, iclass 27, count 0 2006.217.08:17:48.02#ibcon#wrote, iclass 27, count 0 2006.217.08:17:48.02#ibcon#about to read 3, iclass 27, count 0 2006.217.08:17:48.06#ibcon#read 3, iclass 27, count 0 2006.217.08:17:48.06#ibcon#about to read 4, iclass 27, count 0 2006.217.08:17:48.06#ibcon#read 4, iclass 27, count 0 2006.217.08:17:48.06#ibcon#about to read 5, iclass 27, count 0 2006.217.08:17:48.06#ibcon#read 5, iclass 27, count 0 2006.217.08:17:48.06#ibcon#about to read 6, iclass 27, count 0 2006.217.08:17:48.06#ibcon#read 6, iclass 27, count 0 2006.217.08:17:48.06#ibcon#end of sib2, iclass 27, count 0 2006.217.08:17:48.06#ibcon#*after write, iclass 27, count 0 2006.217.08:17:48.06#ibcon#*before return 0, iclass 27, count 0 2006.217.08:17:48.06#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.217.08:17:48.06#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.217.08:17:48.06#ibcon#about to clear, iclass 27 cls_cnt 0 2006.217.08:17:48.06#ibcon#cleared, iclass 27 cls_cnt 0 2006.217.08:17:48.07$vc4f8/va=1,5 2006.217.08:17:48.07#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.217.08:17:48.07#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.217.08:17:48.07#ibcon#ireg 11 cls_cnt 2 2006.217.08:17:48.07#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.217.08:17:48.07#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.217.08:17:48.07#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.217.08:17:48.07#ibcon#enter wrdev, iclass 29, count 2 2006.217.08:17:48.07#ibcon#first serial, iclass 29, count 2 2006.217.08:17:48.07#ibcon#enter sib2, iclass 29, count 2 2006.217.08:17:48.07#ibcon#flushed, iclass 29, count 2 2006.217.08:17:48.07#ibcon#about to write, iclass 29, count 2 2006.217.08:17:48.07#ibcon#wrote, iclass 29, count 2 2006.217.08:17:48.07#ibcon#about to read 3, iclass 29, count 2 2006.217.08:17:48.09#ibcon#read 3, iclass 29, count 2 2006.217.08:17:48.09#ibcon#about to read 4, iclass 29, count 2 2006.217.08:17:48.09#ibcon#read 4, iclass 29, count 2 2006.217.08:17:48.09#ibcon#about to read 5, iclass 29, count 2 2006.217.08:17:48.09#ibcon#read 5, iclass 29, count 2 2006.217.08:17:48.09#ibcon#about to read 6, iclass 29, count 2 2006.217.08:17:48.09#ibcon#read 6, iclass 29, count 2 2006.217.08:17:48.09#ibcon#end of sib2, iclass 29, count 2 2006.217.08:17:48.09#ibcon#*mode == 0, iclass 29, count 2 2006.217.08:17:48.09#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.217.08:17:48.09#ibcon#[25=AT01-05\r\n] 2006.217.08:17:48.09#ibcon#*before write, iclass 29, count 2 2006.217.08:17:48.09#ibcon#enter sib2, iclass 29, count 2 2006.217.08:17:48.09#ibcon#flushed, iclass 29, count 2 2006.217.08:17:48.09#ibcon#about to write, iclass 29, count 2 2006.217.08:17:48.09#ibcon#wrote, iclass 29, count 2 2006.217.08:17:48.09#ibcon#about to read 3, iclass 29, count 2 2006.217.08:17:48.12#ibcon#read 3, iclass 29, count 2 2006.217.08:17:48.12#ibcon#about to read 4, iclass 29, count 2 2006.217.08:17:48.12#ibcon#read 4, iclass 29, count 2 2006.217.08:17:48.12#ibcon#about to read 5, iclass 29, count 2 2006.217.08:17:48.12#ibcon#read 5, iclass 29, count 2 2006.217.08:17:48.12#ibcon#about to read 6, iclass 29, count 2 2006.217.08:17:48.12#ibcon#read 6, iclass 29, count 2 2006.217.08:17:48.12#ibcon#end of sib2, iclass 29, count 2 2006.217.08:17:48.12#ibcon#*after write, iclass 29, count 2 2006.217.08:17:48.12#ibcon#*before return 0, iclass 29, count 2 2006.217.08:17:48.12#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.217.08:17:48.12#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.217.08:17:48.12#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.217.08:17:48.12#ibcon#ireg 7 cls_cnt 0 2006.217.08:17:48.12#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.217.08:17:48.24#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.217.08:17:48.24#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.217.08:17:48.24#ibcon#enter wrdev, iclass 29, count 0 2006.217.08:17:48.24#ibcon#first serial, iclass 29, count 0 2006.217.08:17:48.24#ibcon#enter sib2, iclass 29, count 0 2006.217.08:17:48.24#ibcon#flushed, iclass 29, count 0 2006.217.08:17:48.24#ibcon#about to write, iclass 29, count 0 2006.217.08:17:48.24#ibcon#wrote, iclass 29, count 0 2006.217.08:17:48.24#ibcon#about to read 3, iclass 29, count 0 2006.217.08:17:48.26#ibcon#read 3, iclass 29, count 0 2006.217.08:17:48.26#ibcon#about to read 4, iclass 29, count 0 2006.217.08:17:48.26#ibcon#read 4, iclass 29, count 0 2006.217.08:17:48.26#ibcon#about to read 5, iclass 29, count 0 2006.217.08:17:48.26#ibcon#read 5, iclass 29, count 0 2006.217.08:17:48.26#ibcon#about to read 6, iclass 29, count 0 2006.217.08:17:48.26#ibcon#read 6, iclass 29, count 0 2006.217.08:17:48.26#ibcon#end of sib2, iclass 29, count 0 2006.217.08:17:48.26#ibcon#*mode == 0, iclass 29, count 0 2006.217.08:17:48.26#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.217.08:17:48.26#ibcon#[25=USB\r\n] 2006.217.08:17:48.26#ibcon#*before write, iclass 29, count 0 2006.217.08:17:48.26#ibcon#enter sib2, iclass 29, count 0 2006.217.08:17:48.26#ibcon#flushed, iclass 29, count 0 2006.217.08:17:48.26#ibcon#about to write, iclass 29, count 0 2006.217.08:17:48.26#ibcon#wrote, iclass 29, count 0 2006.217.08:17:48.26#ibcon#about to read 3, iclass 29, count 0 2006.217.08:17:48.29#ibcon#read 3, iclass 29, count 0 2006.217.08:17:48.29#ibcon#about to read 4, iclass 29, count 0 2006.217.08:17:48.29#ibcon#read 4, iclass 29, count 0 2006.217.08:17:48.29#ibcon#about to read 5, iclass 29, count 0 2006.217.08:17:48.29#ibcon#read 5, iclass 29, count 0 2006.217.08:17:48.29#ibcon#about to read 6, iclass 29, count 0 2006.217.08:17:48.29#ibcon#read 6, iclass 29, count 0 2006.217.08:17:48.29#ibcon#end of sib2, iclass 29, count 0 2006.217.08:17:48.29#ibcon#*after write, iclass 29, count 0 2006.217.08:17:48.29#ibcon#*before return 0, iclass 29, count 0 2006.217.08:17:48.29#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.217.08:17:48.29#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.217.08:17:48.29#ibcon#about to clear, iclass 29 cls_cnt 0 2006.217.08:17:48.29#ibcon#cleared, iclass 29 cls_cnt 0 2006.217.08:17:48.30$vc4f8/valo=2,572.99 2006.217.08:17:48.30#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.217.08:17:48.30#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.217.08:17:48.30#ibcon#ireg 17 cls_cnt 0 2006.217.08:17:48.30#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.217.08:17:48.30#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.217.08:17:48.30#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.217.08:17:48.30#ibcon#enter wrdev, iclass 31, count 0 2006.217.08:17:48.30#ibcon#first serial, iclass 31, count 0 2006.217.08:17:48.30#ibcon#enter sib2, iclass 31, count 0 2006.217.08:17:48.30#ibcon#flushed, iclass 31, count 0 2006.217.08:17:48.30#ibcon#about to write, iclass 31, count 0 2006.217.08:17:48.30#ibcon#wrote, iclass 31, count 0 2006.217.08:17:48.30#ibcon#about to read 3, iclass 31, count 0 2006.217.08:17:48.32#ibcon#read 3, iclass 31, count 0 2006.217.08:17:48.32#ibcon#about to read 4, iclass 31, count 0 2006.217.08:17:48.32#ibcon#read 4, iclass 31, count 0 2006.217.08:17:48.32#ibcon#about to read 5, iclass 31, count 0 2006.217.08:17:48.32#ibcon#read 5, iclass 31, count 0 2006.217.08:17:48.32#ibcon#about to read 6, iclass 31, count 0 2006.217.08:17:48.32#ibcon#read 6, iclass 31, count 0 2006.217.08:17:48.32#ibcon#end of sib2, iclass 31, count 0 2006.217.08:17:48.32#ibcon#*mode == 0, iclass 31, count 0 2006.217.08:17:48.32#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.217.08:17:48.32#ibcon#[26=FRQ=02,572.99\r\n] 2006.217.08:17:48.32#ibcon#*before write, iclass 31, count 0 2006.217.08:17:48.32#ibcon#enter sib2, iclass 31, count 0 2006.217.08:17:48.32#ibcon#flushed, iclass 31, count 0 2006.217.08:17:48.32#ibcon#about to write, iclass 31, count 0 2006.217.08:17:48.32#ibcon#wrote, iclass 31, count 0 2006.217.08:17:48.32#ibcon#about to read 3, iclass 31, count 0 2006.217.08:17:48.36#ibcon#read 3, iclass 31, count 0 2006.217.08:17:48.36#ibcon#about to read 4, iclass 31, count 0 2006.217.08:17:48.36#ibcon#read 4, iclass 31, count 0 2006.217.08:17:48.36#ibcon#about to read 5, iclass 31, count 0 2006.217.08:17:48.36#ibcon#read 5, iclass 31, count 0 2006.217.08:17:48.36#ibcon#about to read 6, iclass 31, count 0 2006.217.08:17:48.36#ibcon#read 6, iclass 31, count 0 2006.217.08:17:48.36#ibcon#end of sib2, iclass 31, count 0 2006.217.08:17:48.36#ibcon#*after write, iclass 31, count 0 2006.217.08:17:48.36#ibcon#*before return 0, iclass 31, count 0 2006.217.08:17:48.36#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.217.08:17:48.36#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.217.08:17:48.36#ibcon#about to clear, iclass 31 cls_cnt 0 2006.217.08:17:48.36#ibcon#cleared, iclass 31 cls_cnt 0 2006.217.08:17:48.37$vc4f8/va=2,4 2006.217.08:17:48.37#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.217.08:17:48.37#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.217.08:17:48.37#ibcon#ireg 11 cls_cnt 2 2006.217.08:17:48.37#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.217.08:17:48.40#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.217.08:17:48.40#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.217.08:17:48.40#ibcon#enter wrdev, iclass 33, count 2 2006.217.08:17:48.40#ibcon#first serial, iclass 33, count 2 2006.217.08:17:48.40#ibcon#enter sib2, iclass 33, count 2 2006.217.08:17:48.40#ibcon#flushed, iclass 33, count 2 2006.217.08:17:48.40#ibcon#about to write, iclass 33, count 2 2006.217.08:17:48.40#ibcon#wrote, iclass 33, count 2 2006.217.08:17:48.40#ibcon#about to read 3, iclass 33, count 2 2006.217.08:17:48.43#ibcon#read 3, iclass 33, count 2 2006.217.08:17:48.43#ibcon#about to read 4, iclass 33, count 2 2006.217.08:17:48.43#ibcon#read 4, iclass 33, count 2 2006.217.08:17:48.43#ibcon#about to read 5, iclass 33, count 2 2006.217.08:17:48.43#ibcon#read 5, iclass 33, count 2 2006.217.08:17:48.43#ibcon#about to read 6, iclass 33, count 2 2006.217.08:17:48.43#ibcon#read 6, iclass 33, count 2 2006.217.08:17:48.43#ibcon#end of sib2, iclass 33, count 2 2006.217.08:17:48.43#ibcon#*mode == 0, iclass 33, count 2 2006.217.08:17:48.43#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.217.08:17:48.43#ibcon#[25=AT02-04\r\n] 2006.217.08:17:48.43#ibcon#*before write, iclass 33, count 2 2006.217.08:17:48.43#ibcon#enter sib2, iclass 33, count 2 2006.217.08:17:48.43#ibcon#flushed, iclass 33, count 2 2006.217.08:17:48.43#ibcon#about to write, iclass 33, count 2 2006.217.08:17:48.43#ibcon#wrote, iclass 33, count 2 2006.217.08:17:48.43#ibcon#about to read 3, iclass 33, count 2 2006.217.08:17:48.46#ibcon#read 3, iclass 33, count 2 2006.217.08:17:48.46#ibcon#about to read 4, iclass 33, count 2 2006.217.08:17:48.46#ibcon#read 4, iclass 33, count 2 2006.217.08:17:48.46#ibcon#about to read 5, iclass 33, count 2 2006.217.08:17:48.46#ibcon#read 5, iclass 33, count 2 2006.217.08:17:48.46#ibcon#about to read 6, iclass 33, count 2 2006.217.08:17:48.46#ibcon#read 6, iclass 33, count 2 2006.217.08:17:48.46#ibcon#end of sib2, iclass 33, count 2 2006.217.08:17:48.46#ibcon#*after write, iclass 33, count 2 2006.217.08:17:48.46#ibcon#*before return 0, iclass 33, count 2 2006.217.08:17:48.46#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.217.08:17:48.46#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.217.08:17:48.46#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.217.08:17:48.46#ibcon#ireg 7 cls_cnt 0 2006.217.08:17:48.46#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.217.08:17:48.58#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.217.08:17:48.58#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.217.08:17:48.58#ibcon#enter wrdev, iclass 33, count 0 2006.217.08:17:48.58#ibcon#first serial, iclass 33, count 0 2006.217.08:17:48.58#ibcon#enter sib2, iclass 33, count 0 2006.217.08:17:48.58#ibcon#flushed, iclass 33, count 0 2006.217.08:17:48.58#ibcon#about to write, iclass 33, count 0 2006.217.08:17:48.58#ibcon#wrote, iclass 33, count 0 2006.217.08:17:48.58#ibcon#about to read 3, iclass 33, count 0 2006.217.08:17:48.60#ibcon#read 3, iclass 33, count 0 2006.217.08:17:48.60#ibcon#about to read 4, iclass 33, count 0 2006.217.08:17:48.60#ibcon#read 4, iclass 33, count 0 2006.217.08:17:48.60#ibcon#about to read 5, iclass 33, count 0 2006.217.08:17:48.60#ibcon#read 5, iclass 33, count 0 2006.217.08:17:48.60#ibcon#about to read 6, iclass 33, count 0 2006.217.08:17:48.60#ibcon#read 6, iclass 33, count 0 2006.217.08:17:48.60#ibcon#end of sib2, iclass 33, count 0 2006.217.08:17:48.60#ibcon#*mode == 0, iclass 33, count 0 2006.217.08:17:48.60#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.217.08:17:48.60#ibcon#[25=USB\r\n] 2006.217.08:17:48.60#ibcon#*before write, iclass 33, count 0 2006.217.08:17:48.60#ibcon#enter sib2, iclass 33, count 0 2006.217.08:17:48.60#ibcon#flushed, iclass 33, count 0 2006.217.08:17:48.60#ibcon#about to write, iclass 33, count 0 2006.217.08:17:48.60#ibcon#wrote, iclass 33, count 0 2006.217.08:17:48.60#ibcon#about to read 3, iclass 33, count 0 2006.217.08:17:48.63#ibcon#read 3, iclass 33, count 0 2006.217.08:17:48.63#ibcon#about to read 4, iclass 33, count 0 2006.217.08:17:48.63#ibcon#read 4, iclass 33, count 0 2006.217.08:17:48.63#ibcon#about to read 5, iclass 33, count 0 2006.217.08:17:48.63#ibcon#read 5, iclass 33, count 0 2006.217.08:17:48.63#ibcon#about to read 6, iclass 33, count 0 2006.217.08:17:48.63#ibcon#read 6, iclass 33, count 0 2006.217.08:17:48.63#ibcon#end of sib2, iclass 33, count 0 2006.217.08:17:48.63#ibcon#*after write, iclass 33, count 0 2006.217.08:17:48.63#ibcon#*before return 0, iclass 33, count 0 2006.217.08:17:48.63#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.217.08:17:48.63#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.217.08:17:48.63#ibcon#about to clear, iclass 33 cls_cnt 0 2006.217.08:17:48.63#ibcon#cleared, iclass 33 cls_cnt 0 2006.217.08:17:48.64$vc4f8/valo=3,672.99 2006.217.08:17:48.64#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.217.08:17:48.64#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.217.08:17:48.64#ibcon#ireg 17 cls_cnt 0 2006.217.08:17:48.64#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.217.08:17:48.64#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.217.08:17:48.64#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.217.08:17:48.64#ibcon#enter wrdev, iclass 35, count 0 2006.217.08:17:48.64#ibcon#first serial, iclass 35, count 0 2006.217.08:17:48.64#ibcon#enter sib2, iclass 35, count 0 2006.217.08:17:48.64#ibcon#flushed, iclass 35, count 0 2006.217.08:17:48.64#ibcon#about to write, iclass 35, count 0 2006.217.08:17:48.64#ibcon#wrote, iclass 35, count 0 2006.217.08:17:48.64#ibcon#about to read 3, iclass 35, count 0 2006.217.08:17:48.66#ibcon#read 3, iclass 35, count 0 2006.217.08:17:48.66#ibcon#about to read 4, iclass 35, count 0 2006.217.08:17:48.66#ibcon#read 4, iclass 35, count 0 2006.217.08:17:48.66#ibcon#about to read 5, iclass 35, count 0 2006.217.08:17:48.66#ibcon#read 5, iclass 35, count 0 2006.217.08:17:48.66#ibcon#about to read 6, iclass 35, count 0 2006.217.08:17:48.66#ibcon#read 6, iclass 35, count 0 2006.217.08:17:48.66#ibcon#end of sib2, iclass 35, count 0 2006.217.08:17:48.66#ibcon#*mode == 0, iclass 35, count 0 2006.217.08:17:48.66#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.217.08:17:48.66#ibcon#[26=FRQ=03,672.99\r\n] 2006.217.08:17:48.66#ibcon#*before write, iclass 35, count 0 2006.217.08:17:48.66#ibcon#enter sib2, iclass 35, count 0 2006.217.08:17:48.66#ibcon#flushed, iclass 35, count 0 2006.217.08:17:48.66#ibcon#about to write, iclass 35, count 0 2006.217.08:17:48.66#ibcon#wrote, iclass 35, count 0 2006.217.08:17:48.66#ibcon#about to read 3, iclass 35, count 0 2006.217.08:17:48.70#ibcon#read 3, iclass 35, count 0 2006.217.08:17:48.70#ibcon#about to read 4, iclass 35, count 0 2006.217.08:17:48.70#ibcon#read 4, iclass 35, count 0 2006.217.08:17:48.70#ibcon#about to read 5, iclass 35, count 0 2006.217.08:17:48.70#ibcon#read 5, iclass 35, count 0 2006.217.08:17:48.70#ibcon#about to read 6, iclass 35, count 0 2006.217.08:17:48.70#ibcon#read 6, iclass 35, count 0 2006.217.08:17:48.70#ibcon#end of sib2, iclass 35, count 0 2006.217.08:17:48.70#ibcon#*after write, iclass 35, count 0 2006.217.08:17:48.70#ibcon#*before return 0, iclass 35, count 0 2006.217.08:17:48.70#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.217.08:17:48.70#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.217.08:17:48.70#ibcon#about to clear, iclass 35 cls_cnt 0 2006.217.08:17:48.70#ibcon#cleared, iclass 35 cls_cnt 0 2006.217.08:17:48.71$vc4f8/va=3,4 2006.217.08:17:48.71#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.217.08:17:48.71#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.217.08:17:48.71#ibcon#ireg 11 cls_cnt 2 2006.217.08:17:48.71#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.217.08:17:48.74#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.217.08:17:48.74#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.217.08:17:48.74#ibcon#enter wrdev, iclass 37, count 2 2006.217.08:17:48.74#ibcon#first serial, iclass 37, count 2 2006.217.08:17:48.74#ibcon#enter sib2, iclass 37, count 2 2006.217.08:17:48.74#ibcon#flushed, iclass 37, count 2 2006.217.08:17:48.74#ibcon#about to write, iclass 37, count 2 2006.217.08:17:48.74#ibcon#wrote, iclass 37, count 2 2006.217.08:17:48.74#ibcon#about to read 3, iclass 37, count 2 2006.217.08:17:48.77#ibcon#read 3, iclass 37, count 2 2006.217.08:17:48.77#ibcon#about to read 4, iclass 37, count 2 2006.217.08:17:48.77#ibcon#read 4, iclass 37, count 2 2006.217.08:17:48.77#ibcon#about to read 5, iclass 37, count 2 2006.217.08:17:48.77#ibcon#read 5, iclass 37, count 2 2006.217.08:17:48.77#ibcon#about to read 6, iclass 37, count 2 2006.217.08:17:48.77#ibcon#read 6, iclass 37, count 2 2006.217.08:17:48.77#ibcon#end of sib2, iclass 37, count 2 2006.217.08:17:48.77#ibcon#*mode == 0, iclass 37, count 2 2006.217.08:17:48.77#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.217.08:17:48.77#ibcon#[25=AT03-04\r\n] 2006.217.08:17:48.77#ibcon#*before write, iclass 37, count 2 2006.217.08:17:48.77#ibcon#enter sib2, iclass 37, count 2 2006.217.08:17:48.77#ibcon#flushed, iclass 37, count 2 2006.217.08:17:48.77#ibcon#about to write, iclass 37, count 2 2006.217.08:17:48.77#ibcon#wrote, iclass 37, count 2 2006.217.08:17:48.77#ibcon#about to read 3, iclass 37, count 2 2006.217.08:17:48.80#ibcon#read 3, iclass 37, count 2 2006.217.08:17:48.80#ibcon#about to read 4, iclass 37, count 2 2006.217.08:17:48.80#ibcon#read 4, iclass 37, count 2 2006.217.08:17:48.80#ibcon#about to read 5, iclass 37, count 2 2006.217.08:17:48.80#ibcon#read 5, iclass 37, count 2 2006.217.08:17:48.80#ibcon#about to read 6, iclass 37, count 2 2006.217.08:17:48.80#ibcon#read 6, iclass 37, count 2 2006.217.08:17:48.80#ibcon#end of sib2, iclass 37, count 2 2006.217.08:17:48.80#ibcon#*after write, iclass 37, count 2 2006.217.08:17:48.80#ibcon#*before return 0, iclass 37, count 2 2006.217.08:17:48.80#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.217.08:17:48.80#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.217.08:17:48.80#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.217.08:17:48.80#ibcon#ireg 7 cls_cnt 0 2006.217.08:17:48.80#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.217.08:17:48.92#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.217.08:17:48.92#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.217.08:17:48.92#ibcon#enter wrdev, iclass 37, count 0 2006.217.08:17:48.92#ibcon#first serial, iclass 37, count 0 2006.217.08:17:48.92#ibcon#enter sib2, iclass 37, count 0 2006.217.08:17:48.92#ibcon#flushed, iclass 37, count 0 2006.217.08:17:48.92#ibcon#about to write, iclass 37, count 0 2006.217.08:17:48.92#ibcon#wrote, iclass 37, count 0 2006.217.08:17:48.92#ibcon#about to read 3, iclass 37, count 0 2006.217.08:17:48.94#ibcon#read 3, iclass 37, count 0 2006.217.08:17:48.94#ibcon#about to read 4, iclass 37, count 0 2006.217.08:17:48.94#ibcon#read 4, iclass 37, count 0 2006.217.08:17:48.94#ibcon#about to read 5, iclass 37, count 0 2006.217.08:17:48.94#ibcon#read 5, iclass 37, count 0 2006.217.08:17:48.94#ibcon#about to read 6, iclass 37, count 0 2006.217.08:17:48.94#ibcon#read 6, iclass 37, count 0 2006.217.08:17:48.94#ibcon#end of sib2, iclass 37, count 0 2006.217.08:17:48.94#ibcon#*mode == 0, iclass 37, count 0 2006.217.08:17:48.94#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.217.08:17:48.94#ibcon#[25=USB\r\n] 2006.217.08:17:48.94#ibcon#*before write, iclass 37, count 0 2006.217.08:17:48.94#ibcon#enter sib2, iclass 37, count 0 2006.217.08:17:48.94#ibcon#flushed, iclass 37, count 0 2006.217.08:17:48.94#ibcon#about to write, iclass 37, count 0 2006.217.08:17:48.94#ibcon#wrote, iclass 37, count 0 2006.217.08:17:48.94#ibcon#about to read 3, iclass 37, count 0 2006.217.08:17:48.97#ibcon#read 3, iclass 37, count 0 2006.217.08:17:48.97#ibcon#about to read 4, iclass 37, count 0 2006.217.08:17:48.97#ibcon#read 4, iclass 37, count 0 2006.217.08:17:48.97#ibcon#about to read 5, iclass 37, count 0 2006.217.08:17:48.97#ibcon#read 5, iclass 37, count 0 2006.217.08:17:48.97#ibcon#about to read 6, iclass 37, count 0 2006.217.08:17:48.97#ibcon#read 6, iclass 37, count 0 2006.217.08:17:48.97#ibcon#end of sib2, iclass 37, count 0 2006.217.08:17:48.97#ibcon#*after write, iclass 37, count 0 2006.217.08:17:48.97#ibcon#*before return 0, iclass 37, count 0 2006.217.08:17:48.97#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.217.08:17:48.97#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.217.08:17:48.97#ibcon#about to clear, iclass 37 cls_cnt 0 2006.217.08:17:48.97#ibcon#cleared, iclass 37 cls_cnt 0 2006.217.08:17:48.98$vc4f8/valo=4,832.99 2006.217.08:17:48.98#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.217.08:17:48.98#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.217.08:17:48.98#ibcon#ireg 17 cls_cnt 0 2006.217.08:17:48.98#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.217.08:17:48.98#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.217.08:17:48.98#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.217.08:17:48.98#ibcon#enter wrdev, iclass 39, count 0 2006.217.08:17:48.98#ibcon#first serial, iclass 39, count 0 2006.217.08:17:48.98#ibcon#enter sib2, iclass 39, count 0 2006.217.08:17:48.98#ibcon#flushed, iclass 39, count 0 2006.217.08:17:48.98#ibcon#about to write, iclass 39, count 0 2006.217.08:17:48.98#ibcon#wrote, iclass 39, count 0 2006.217.08:17:48.98#ibcon#about to read 3, iclass 39, count 0 2006.217.08:17:48.99#ibcon#read 3, iclass 39, count 0 2006.217.08:17:48.99#ibcon#about to read 4, iclass 39, count 0 2006.217.08:17:48.99#ibcon#read 4, iclass 39, count 0 2006.217.08:17:48.99#ibcon#about to read 5, iclass 39, count 0 2006.217.08:17:48.99#ibcon#read 5, iclass 39, count 0 2006.217.08:17:48.99#ibcon#about to read 6, iclass 39, count 0 2006.217.08:17:48.99#ibcon#read 6, iclass 39, count 0 2006.217.08:17:48.99#ibcon#end of sib2, iclass 39, count 0 2006.217.08:17:48.99#ibcon#*mode == 0, iclass 39, count 0 2006.217.08:17:48.99#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.217.08:17:48.99#ibcon#[26=FRQ=04,832.99\r\n] 2006.217.08:17:48.99#ibcon#*before write, iclass 39, count 0 2006.217.08:17:48.99#ibcon#enter sib2, iclass 39, count 0 2006.217.08:17:48.99#ibcon#flushed, iclass 39, count 0 2006.217.08:17:48.99#ibcon#about to write, iclass 39, count 0 2006.217.08:17:48.99#ibcon#wrote, iclass 39, count 0 2006.217.08:17:48.99#ibcon#about to read 3, iclass 39, count 0 2006.217.08:17:49.03#ibcon#read 3, iclass 39, count 0 2006.217.08:17:49.03#ibcon#about to read 4, iclass 39, count 0 2006.217.08:17:49.03#ibcon#read 4, iclass 39, count 0 2006.217.08:17:49.03#ibcon#about to read 5, iclass 39, count 0 2006.217.08:17:49.03#ibcon#read 5, iclass 39, count 0 2006.217.08:17:49.03#ibcon#about to read 6, iclass 39, count 0 2006.217.08:17:49.03#ibcon#read 6, iclass 39, count 0 2006.217.08:17:49.03#ibcon#end of sib2, iclass 39, count 0 2006.217.08:17:49.03#ibcon#*after write, iclass 39, count 0 2006.217.08:17:49.03#ibcon#*before return 0, iclass 39, count 0 2006.217.08:17:49.03#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.217.08:17:49.03#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.217.08:17:49.03#ibcon#about to clear, iclass 39 cls_cnt 0 2006.217.08:17:49.03#ibcon#cleared, iclass 39 cls_cnt 0 2006.217.08:17:49.03$vc4f8/va=4,4 2006.217.08:17:49.04#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.217.08:17:49.04#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.217.08:17:49.04#ibcon#ireg 11 cls_cnt 2 2006.217.08:17:49.04#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.217.08:17:49.08#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.217.08:17:49.08#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.217.08:17:49.08#ibcon#enter wrdev, iclass 3, count 2 2006.217.08:17:49.08#ibcon#first serial, iclass 3, count 2 2006.217.08:17:49.08#ibcon#enter sib2, iclass 3, count 2 2006.217.08:17:49.08#ibcon#flushed, iclass 3, count 2 2006.217.08:17:49.08#ibcon#about to write, iclass 3, count 2 2006.217.08:17:49.08#ibcon#wrote, iclass 3, count 2 2006.217.08:17:49.08#ibcon#about to read 3, iclass 3, count 2 2006.217.08:17:49.10#ibcon#read 3, iclass 3, count 2 2006.217.08:17:49.10#ibcon#about to read 4, iclass 3, count 2 2006.217.08:17:49.10#ibcon#read 4, iclass 3, count 2 2006.217.08:17:49.10#ibcon#about to read 5, iclass 3, count 2 2006.217.08:17:49.10#ibcon#read 5, iclass 3, count 2 2006.217.08:17:49.10#ibcon#about to read 6, iclass 3, count 2 2006.217.08:17:49.10#ibcon#read 6, iclass 3, count 2 2006.217.08:17:49.10#ibcon#end of sib2, iclass 3, count 2 2006.217.08:17:49.10#ibcon#*mode == 0, iclass 3, count 2 2006.217.08:17:49.10#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.217.08:17:49.10#ibcon#[25=AT04-04\r\n] 2006.217.08:17:49.10#ibcon#*before write, iclass 3, count 2 2006.217.08:17:49.10#ibcon#enter sib2, iclass 3, count 2 2006.217.08:17:49.10#ibcon#flushed, iclass 3, count 2 2006.217.08:17:49.10#ibcon#about to write, iclass 3, count 2 2006.217.08:17:49.10#ibcon#wrote, iclass 3, count 2 2006.217.08:17:49.10#ibcon#about to read 3, iclass 3, count 2 2006.217.08:17:49.13#ibcon#read 3, iclass 3, count 2 2006.217.08:17:49.13#ibcon#about to read 4, iclass 3, count 2 2006.217.08:17:49.13#ibcon#read 4, iclass 3, count 2 2006.217.08:17:49.13#ibcon#about to read 5, iclass 3, count 2 2006.217.08:17:49.13#ibcon#read 5, iclass 3, count 2 2006.217.08:17:49.13#ibcon#about to read 6, iclass 3, count 2 2006.217.08:17:49.13#ibcon#read 6, iclass 3, count 2 2006.217.08:17:49.13#ibcon#end of sib2, iclass 3, count 2 2006.217.08:17:49.13#ibcon#*after write, iclass 3, count 2 2006.217.08:17:49.13#ibcon#*before return 0, iclass 3, count 2 2006.217.08:17:49.13#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.217.08:17:49.13#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.217.08:17:49.13#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.217.08:17:49.13#ibcon#ireg 7 cls_cnt 0 2006.217.08:17:49.13#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.217.08:17:49.25#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.217.08:17:49.25#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.217.08:17:49.25#ibcon#enter wrdev, iclass 3, count 0 2006.217.08:17:49.25#ibcon#first serial, iclass 3, count 0 2006.217.08:17:49.25#ibcon#enter sib2, iclass 3, count 0 2006.217.08:17:49.25#ibcon#flushed, iclass 3, count 0 2006.217.08:17:49.25#ibcon#about to write, iclass 3, count 0 2006.217.08:17:49.25#ibcon#wrote, iclass 3, count 0 2006.217.08:17:49.25#ibcon#about to read 3, iclass 3, count 0 2006.217.08:17:49.27#ibcon#read 3, iclass 3, count 0 2006.217.08:17:49.27#ibcon#about to read 4, iclass 3, count 0 2006.217.08:17:49.27#ibcon#read 4, iclass 3, count 0 2006.217.08:17:49.27#ibcon#about to read 5, iclass 3, count 0 2006.217.08:17:49.27#ibcon#read 5, iclass 3, count 0 2006.217.08:17:49.27#ibcon#about to read 6, iclass 3, count 0 2006.217.08:17:49.27#ibcon#read 6, iclass 3, count 0 2006.217.08:17:49.27#ibcon#end of sib2, iclass 3, count 0 2006.217.08:17:49.27#ibcon#*mode == 0, iclass 3, count 0 2006.217.08:17:49.27#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.217.08:17:49.27#ibcon#[25=USB\r\n] 2006.217.08:17:49.27#ibcon#*before write, iclass 3, count 0 2006.217.08:17:49.27#ibcon#enter sib2, iclass 3, count 0 2006.217.08:17:49.27#ibcon#flushed, iclass 3, count 0 2006.217.08:17:49.27#ibcon#about to write, iclass 3, count 0 2006.217.08:17:49.27#ibcon#wrote, iclass 3, count 0 2006.217.08:17:49.27#ibcon#about to read 3, iclass 3, count 0 2006.217.08:17:49.30#ibcon#read 3, iclass 3, count 0 2006.217.08:17:49.30#ibcon#about to read 4, iclass 3, count 0 2006.217.08:17:49.30#ibcon#read 4, iclass 3, count 0 2006.217.08:17:49.30#ibcon#about to read 5, iclass 3, count 0 2006.217.08:17:49.30#ibcon#read 5, iclass 3, count 0 2006.217.08:17:49.30#ibcon#about to read 6, iclass 3, count 0 2006.217.08:17:49.30#ibcon#read 6, iclass 3, count 0 2006.217.08:17:49.30#ibcon#end of sib2, iclass 3, count 0 2006.217.08:17:49.30#ibcon#*after write, iclass 3, count 0 2006.217.08:17:49.30#ibcon#*before return 0, iclass 3, count 0 2006.217.08:17:49.30#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.217.08:17:49.30#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.217.08:17:49.30#ibcon#about to clear, iclass 3 cls_cnt 0 2006.217.08:17:49.30#ibcon#cleared, iclass 3 cls_cnt 0 2006.217.08:17:49.31$vc4f8/valo=5,652.99 2006.217.08:17:49.31#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.217.08:17:49.31#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.217.08:17:49.31#ibcon#ireg 17 cls_cnt 0 2006.217.08:17:49.31#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.217.08:17:49.31#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.217.08:17:49.31#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.217.08:17:49.31#ibcon#enter wrdev, iclass 5, count 0 2006.217.08:17:49.31#ibcon#first serial, iclass 5, count 0 2006.217.08:17:49.31#ibcon#enter sib2, iclass 5, count 0 2006.217.08:17:49.31#ibcon#flushed, iclass 5, count 0 2006.217.08:17:49.31#ibcon#about to write, iclass 5, count 0 2006.217.08:17:49.31#ibcon#wrote, iclass 5, count 0 2006.217.08:17:49.31#ibcon#about to read 3, iclass 5, count 0 2006.217.08:17:49.32#ibcon#read 3, iclass 5, count 0 2006.217.08:17:49.32#ibcon#about to read 4, iclass 5, count 0 2006.217.08:17:49.32#ibcon#read 4, iclass 5, count 0 2006.217.08:17:49.32#ibcon#about to read 5, iclass 5, count 0 2006.217.08:17:49.32#ibcon#read 5, iclass 5, count 0 2006.217.08:17:49.32#ibcon#about to read 6, iclass 5, count 0 2006.217.08:17:49.32#ibcon#read 6, iclass 5, count 0 2006.217.08:17:49.32#ibcon#end of sib2, iclass 5, count 0 2006.217.08:17:49.32#ibcon#*mode == 0, iclass 5, count 0 2006.217.08:17:49.32#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.217.08:17:49.32#ibcon#[26=FRQ=05,652.99\r\n] 2006.217.08:17:49.32#ibcon#*before write, iclass 5, count 0 2006.217.08:17:49.32#ibcon#enter sib2, iclass 5, count 0 2006.217.08:17:49.32#ibcon#flushed, iclass 5, count 0 2006.217.08:17:49.32#ibcon#about to write, iclass 5, count 0 2006.217.08:17:49.32#ibcon#wrote, iclass 5, count 0 2006.217.08:17:49.32#ibcon#about to read 3, iclass 5, count 0 2006.217.08:17:49.36#ibcon#read 3, iclass 5, count 0 2006.217.08:17:49.36#ibcon#about to read 4, iclass 5, count 0 2006.217.08:17:49.36#ibcon#read 4, iclass 5, count 0 2006.217.08:17:49.36#ibcon#about to read 5, iclass 5, count 0 2006.217.08:17:49.36#ibcon#read 5, iclass 5, count 0 2006.217.08:17:49.36#ibcon#about to read 6, iclass 5, count 0 2006.217.08:17:49.36#ibcon#read 6, iclass 5, count 0 2006.217.08:17:49.36#ibcon#end of sib2, iclass 5, count 0 2006.217.08:17:49.36#ibcon#*after write, iclass 5, count 0 2006.217.08:17:49.36#ibcon#*before return 0, iclass 5, count 0 2006.217.08:17:49.36#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.217.08:17:49.36#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.217.08:17:49.36#ibcon#about to clear, iclass 5 cls_cnt 0 2006.217.08:17:49.36#ibcon#cleared, iclass 5 cls_cnt 0 2006.217.08:17:49.36$vc4f8/va=5,7 2006.217.08:17:49.37#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.217.08:17:49.37#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.217.08:17:49.37#ibcon#ireg 11 cls_cnt 2 2006.217.08:17:49.37#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.217.08:17:49.41#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.217.08:17:49.41#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.217.08:17:49.41#ibcon#enter wrdev, iclass 7, count 2 2006.217.08:17:49.41#ibcon#first serial, iclass 7, count 2 2006.217.08:17:49.41#ibcon#enter sib2, iclass 7, count 2 2006.217.08:17:49.41#ibcon#flushed, iclass 7, count 2 2006.217.08:17:49.41#ibcon#about to write, iclass 7, count 2 2006.217.08:17:49.41#ibcon#wrote, iclass 7, count 2 2006.217.08:17:49.41#ibcon#about to read 3, iclass 7, count 2 2006.217.08:17:49.44#ibcon#read 3, iclass 7, count 2 2006.217.08:17:49.44#ibcon#about to read 4, iclass 7, count 2 2006.217.08:17:49.44#ibcon#read 4, iclass 7, count 2 2006.217.08:17:49.44#ibcon#about to read 5, iclass 7, count 2 2006.217.08:17:49.44#ibcon#read 5, iclass 7, count 2 2006.217.08:17:49.44#ibcon#about to read 6, iclass 7, count 2 2006.217.08:17:49.44#ibcon#read 6, iclass 7, count 2 2006.217.08:17:49.44#ibcon#end of sib2, iclass 7, count 2 2006.217.08:17:49.44#ibcon#*mode == 0, iclass 7, count 2 2006.217.08:17:49.44#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.217.08:17:49.44#ibcon#[25=AT05-07\r\n] 2006.217.08:17:49.44#ibcon#*before write, iclass 7, count 2 2006.217.08:17:49.44#ibcon#enter sib2, iclass 7, count 2 2006.217.08:17:49.44#ibcon#flushed, iclass 7, count 2 2006.217.08:17:49.44#ibcon#about to write, iclass 7, count 2 2006.217.08:17:49.44#ibcon#wrote, iclass 7, count 2 2006.217.08:17:49.44#ibcon#about to read 3, iclass 7, count 2 2006.217.08:17:49.47#ibcon#read 3, iclass 7, count 2 2006.217.08:17:49.47#ibcon#about to read 4, iclass 7, count 2 2006.217.08:17:49.47#ibcon#read 4, iclass 7, count 2 2006.217.08:17:49.47#ibcon#about to read 5, iclass 7, count 2 2006.217.08:17:49.47#ibcon#read 5, iclass 7, count 2 2006.217.08:17:49.47#ibcon#about to read 6, iclass 7, count 2 2006.217.08:17:49.47#ibcon#read 6, iclass 7, count 2 2006.217.08:17:49.47#ibcon#end of sib2, iclass 7, count 2 2006.217.08:17:49.47#ibcon#*after write, iclass 7, count 2 2006.217.08:17:49.47#ibcon#*before return 0, iclass 7, count 2 2006.217.08:17:49.47#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.217.08:17:49.47#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.217.08:17:49.47#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.217.08:17:49.47#ibcon#ireg 7 cls_cnt 0 2006.217.08:17:49.47#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.217.08:17:49.59#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.217.08:17:49.59#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.217.08:17:49.59#ibcon#enter wrdev, iclass 7, count 0 2006.217.08:17:49.59#ibcon#first serial, iclass 7, count 0 2006.217.08:17:49.59#ibcon#enter sib2, iclass 7, count 0 2006.217.08:17:49.59#ibcon#flushed, iclass 7, count 0 2006.217.08:17:49.59#ibcon#about to write, iclass 7, count 0 2006.217.08:17:49.59#ibcon#wrote, iclass 7, count 0 2006.217.08:17:49.59#ibcon#about to read 3, iclass 7, count 0 2006.217.08:17:49.61#ibcon#read 3, iclass 7, count 0 2006.217.08:17:49.61#ibcon#about to read 4, iclass 7, count 0 2006.217.08:17:49.61#ibcon#read 4, iclass 7, count 0 2006.217.08:17:49.61#ibcon#about to read 5, iclass 7, count 0 2006.217.08:17:49.61#ibcon#read 5, iclass 7, count 0 2006.217.08:17:49.61#ibcon#about to read 6, iclass 7, count 0 2006.217.08:17:49.61#ibcon#read 6, iclass 7, count 0 2006.217.08:17:49.61#ibcon#end of sib2, iclass 7, count 0 2006.217.08:17:49.61#ibcon#*mode == 0, iclass 7, count 0 2006.217.08:17:49.61#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.217.08:17:49.61#ibcon#[25=USB\r\n] 2006.217.08:17:49.61#ibcon#*before write, iclass 7, count 0 2006.217.08:17:49.61#ibcon#enter sib2, iclass 7, count 0 2006.217.08:17:49.61#ibcon#flushed, iclass 7, count 0 2006.217.08:17:49.61#ibcon#about to write, iclass 7, count 0 2006.217.08:17:49.61#ibcon#wrote, iclass 7, count 0 2006.217.08:17:49.61#ibcon#about to read 3, iclass 7, count 0 2006.217.08:17:49.64#ibcon#read 3, iclass 7, count 0 2006.217.08:17:49.64#ibcon#about to read 4, iclass 7, count 0 2006.217.08:17:49.64#ibcon#read 4, iclass 7, count 0 2006.217.08:17:49.64#ibcon#about to read 5, iclass 7, count 0 2006.217.08:17:49.64#ibcon#read 5, iclass 7, count 0 2006.217.08:17:49.64#ibcon#about to read 6, iclass 7, count 0 2006.217.08:17:49.64#ibcon#read 6, iclass 7, count 0 2006.217.08:17:49.64#ibcon#end of sib2, iclass 7, count 0 2006.217.08:17:49.64#ibcon#*after write, iclass 7, count 0 2006.217.08:17:49.64#ibcon#*before return 0, iclass 7, count 0 2006.217.08:17:49.64#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.217.08:17:49.64#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.217.08:17:49.64#ibcon#about to clear, iclass 7 cls_cnt 0 2006.217.08:17:49.64#ibcon#cleared, iclass 7 cls_cnt 0 2006.217.08:17:49.64$vc4f8/valo=6,772.99 2006.217.08:17:49.65#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.217.08:17:49.65#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.217.08:17:49.65#ibcon#ireg 17 cls_cnt 0 2006.217.08:17:49.65#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.217.08:17:49.65#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.217.08:17:49.65#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.217.08:17:49.65#ibcon#enter wrdev, iclass 11, count 0 2006.217.08:17:49.65#ibcon#first serial, iclass 11, count 0 2006.217.08:17:49.65#ibcon#enter sib2, iclass 11, count 0 2006.217.08:17:49.65#ibcon#flushed, iclass 11, count 0 2006.217.08:17:49.65#ibcon#about to write, iclass 11, count 0 2006.217.08:17:49.65#ibcon#wrote, iclass 11, count 0 2006.217.08:17:49.65#ibcon#about to read 3, iclass 11, count 0 2006.217.08:17:49.66#ibcon#read 3, iclass 11, count 0 2006.217.08:17:49.66#ibcon#about to read 4, iclass 11, count 0 2006.217.08:17:49.66#ibcon#read 4, iclass 11, count 0 2006.217.08:17:49.66#ibcon#about to read 5, iclass 11, count 0 2006.217.08:17:49.66#ibcon#read 5, iclass 11, count 0 2006.217.08:17:49.66#ibcon#about to read 6, iclass 11, count 0 2006.217.08:17:49.66#ibcon#read 6, iclass 11, count 0 2006.217.08:17:49.66#ibcon#end of sib2, iclass 11, count 0 2006.217.08:17:49.66#ibcon#*mode == 0, iclass 11, count 0 2006.217.08:17:49.66#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.217.08:17:49.66#ibcon#[26=FRQ=06,772.99\r\n] 2006.217.08:17:49.66#ibcon#*before write, iclass 11, count 0 2006.217.08:17:49.66#ibcon#enter sib2, iclass 11, count 0 2006.217.08:17:49.66#ibcon#flushed, iclass 11, count 0 2006.217.08:17:49.66#ibcon#about to write, iclass 11, count 0 2006.217.08:17:49.66#ibcon#wrote, iclass 11, count 0 2006.217.08:17:49.66#ibcon#about to read 3, iclass 11, count 0 2006.217.08:17:49.70#ibcon#read 3, iclass 11, count 0 2006.217.08:17:49.70#ibcon#about to read 4, iclass 11, count 0 2006.217.08:17:49.70#ibcon#read 4, iclass 11, count 0 2006.217.08:17:49.70#ibcon#about to read 5, iclass 11, count 0 2006.217.08:17:49.70#ibcon#read 5, iclass 11, count 0 2006.217.08:17:49.70#ibcon#about to read 6, iclass 11, count 0 2006.217.08:17:49.70#ibcon#read 6, iclass 11, count 0 2006.217.08:17:49.70#ibcon#end of sib2, iclass 11, count 0 2006.217.08:17:49.70#ibcon#*after write, iclass 11, count 0 2006.217.08:17:49.70#ibcon#*before return 0, iclass 11, count 0 2006.217.08:17:49.70#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.217.08:17:49.70#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.217.08:17:49.70#ibcon#about to clear, iclass 11 cls_cnt 0 2006.217.08:17:49.70#ibcon#cleared, iclass 11 cls_cnt 0 2006.217.08:17:49.71$vc4f8/va=6,6 2006.217.08:17:49.71#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.217.08:17:49.71#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.217.08:17:49.71#ibcon#ireg 11 cls_cnt 2 2006.217.08:17:49.71#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.217.08:17:49.76#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.217.08:17:49.76#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.217.08:17:49.76#ibcon#enter wrdev, iclass 13, count 2 2006.217.08:17:49.76#ibcon#first serial, iclass 13, count 2 2006.217.08:17:49.76#ibcon#enter sib2, iclass 13, count 2 2006.217.08:17:49.76#ibcon#flushed, iclass 13, count 2 2006.217.08:17:49.76#ibcon#about to write, iclass 13, count 2 2006.217.08:17:49.76#ibcon#wrote, iclass 13, count 2 2006.217.08:17:49.76#ibcon#about to read 3, iclass 13, count 2 2006.217.08:17:49.77#ibcon#read 3, iclass 13, count 2 2006.217.08:17:49.77#ibcon#about to read 4, iclass 13, count 2 2006.217.08:17:49.77#ibcon#read 4, iclass 13, count 2 2006.217.08:17:49.77#ibcon#about to read 5, iclass 13, count 2 2006.217.08:17:49.77#ibcon#read 5, iclass 13, count 2 2006.217.08:17:49.77#ibcon#about to read 6, iclass 13, count 2 2006.217.08:17:49.77#ibcon#read 6, iclass 13, count 2 2006.217.08:17:49.77#ibcon#end of sib2, iclass 13, count 2 2006.217.08:17:49.77#ibcon#*mode == 0, iclass 13, count 2 2006.217.08:17:49.77#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.217.08:17:49.77#ibcon#[25=AT06-06\r\n] 2006.217.08:17:49.77#ibcon#*before write, iclass 13, count 2 2006.217.08:17:49.77#ibcon#enter sib2, iclass 13, count 2 2006.217.08:17:49.77#ibcon#flushed, iclass 13, count 2 2006.217.08:17:49.77#ibcon#about to write, iclass 13, count 2 2006.217.08:17:49.77#ibcon#wrote, iclass 13, count 2 2006.217.08:17:49.77#ibcon#about to read 3, iclass 13, count 2 2006.217.08:17:49.80#ibcon#read 3, iclass 13, count 2 2006.217.08:17:49.80#ibcon#about to read 4, iclass 13, count 2 2006.217.08:17:49.80#ibcon#read 4, iclass 13, count 2 2006.217.08:17:49.80#ibcon#about to read 5, iclass 13, count 2 2006.217.08:17:49.80#ibcon#read 5, iclass 13, count 2 2006.217.08:17:49.80#ibcon#about to read 6, iclass 13, count 2 2006.217.08:17:49.80#ibcon#read 6, iclass 13, count 2 2006.217.08:17:49.80#ibcon#end of sib2, iclass 13, count 2 2006.217.08:17:49.80#ibcon#*after write, iclass 13, count 2 2006.217.08:17:49.80#ibcon#*before return 0, iclass 13, count 2 2006.217.08:17:49.80#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.217.08:17:49.80#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.217.08:17:49.80#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.217.08:17:49.80#ibcon#ireg 7 cls_cnt 0 2006.217.08:17:49.80#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.217.08:17:49.92#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.217.08:17:49.92#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.217.08:17:49.92#ibcon#enter wrdev, iclass 13, count 0 2006.217.08:17:49.92#ibcon#first serial, iclass 13, count 0 2006.217.08:17:49.92#ibcon#enter sib2, iclass 13, count 0 2006.217.08:17:49.92#ibcon#flushed, iclass 13, count 0 2006.217.08:17:49.92#ibcon#about to write, iclass 13, count 0 2006.217.08:17:49.92#ibcon#wrote, iclass 13, count 0 2006.217.08:17:49.92#ibcon#about to read 3, iclass 13, count 0 2006.217.08:17:49.94#ibcon#read 3, iclass 13, count 0 2006.217.08:17:49.94#ibcon#about to read 4, iclass 13, count 0 2006.217.08:17:49.94#ibcon#read 4, iclass 13, count 0 2006.217.08:17:49.94#ibcon#about to read 5, iclass 13, count 0 2006.217.08:17:49.94#ibcon#read 5, iclass 13, count 0 2006.217.08:17:49.94#ibcon#about to read 6, iclass 13, count 0 2006.217.08:17:49.94#ibcon#read 6, iclass 13, count 0 2006.217.08:17:49.94#ibcon#end of sib2, iclass 13, count 0 2006.217.08:17:49.94#ibcon#*mode == 0, iclass 13, count 0 2006.217.08:17:49.94#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.217.08:17:49.94#ibcon#[25=USB\r\n] 2006.217.08:17:49.94#ibcon#*before write, iclass 13, count 0 2006.217.08:17:49.94#ibcon#enter sib2, iclass 13, count 0 2006.217.08:17:49.94#ibcon#flushed, iclass 13, count 0 2006.217.08:17:49.94#ibcon#about to write, iclass 13, count 0 2006.217.08:17:49.94#ibcon#wrote, iclass 13, count 0 2006.217.08:17:49.94#ibcon#about to read 3, iclass 13, count 0 2006.217.08:17:49.97#ibcon#read 3, iclass 13, count 0 2006.217.08:17:49.97#ibcon#about to read 4, iclass 13, count 0 2006.217.08:17:49.97#ibcon#read 4, iclass 13, count 0 2006.217.08:17:49.97#ibcon#about to read 5, iclass 13, count 0 2006.217.08:17:49.97#ibcon#read 5, iclass 13, count 0 2006.217.08:17:49.97#ibcon#about to read 6, iclass 13, count 0 2006.217.08:17:49.97#ibcon#read 6, iclass 13, count 0 2006.217.08:17:49.97#ibcon#end of sib2, iclass 13, count 0 2006.217.08:17:49.97#ibcon#*after write, iclass 13, count 0 2006.217.08:17:49.97#ibcon#*before return 0, iclass 13, count 0 2006.217.08:17:49.97#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.217.08:17:49.97#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.217.08:17:49.97#ibcon#about to clear, iclass 13 cls_cnt 0 2006.217.08:17:49.97#ibcon#cleared, iclass 13 cls_cnt 0 2006.217.08:17:49.97$vc4f8/valo=7,832.99 2006.217.08:17:49.98#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.217.08:17:49.98#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.217.08:17:49.98#ibcon#ireg 17 cls_cnt 0 2006.217.08:17:49.98#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.217.08:17:49.98#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.217.08:17:49.98#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.217.08:17:49.98#ibcon#enter wrdev, iclass 15, count 0 2006.217.08:17:49.98#ibcon#first serial, iclass 15, count 0 2006.217.08:17:49.98#ibcon#enter sib2, iclass 15, count 0 2006.217.08:17:49.98#ibcon#flushed, iclass 15, count 0 2006.217.08:17:49.98#ibcon#about to write, iclass 15, count 0 2006.217.08:17:49.98#ibcon#wrote, iclass 15, count 0 2006.217.08:17:49.98#ibcon#about to read 3, iclass 15, count 0 2006.217.08:17:49.99#ibcon#read 3, iclass 15, count 0 2006.217.08:17:49.99#ibcon#about to read 4, iclass 15, count 0 2006.217.08:17:49.99#ibcon#read 4, iclass 15, count 0 2006.217.08:17:49.99#ibcon#about to read 5, iclass 15, count 0 2006.217.08:17:49.99#ibcon#read 5, iclass 15, count 0 2006.217.08:17:49.99#ibcon#about to read 6, iclass 15, count 0 2006.217.08:17:49.99#ibcon#read 6, iclass 15, count 0 2006.217.08:17:49.99#ibcon#end of sib2, iclass 15, count 0 2006.217.08:17:49.99#ibcon#*mode == 0, iclass 15, count 0 2006.217.08:17:49.99#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.217.08:17:49.99#ibcon#[26=FRQ=07,832.99\r\n] 2006.217.08:17:49.99#ibcon#*before write, iclass 15, count 0 2006.217.08:17:49.99#ibcon#enter sib2, iclass 15, count 0 2006.217.08:17:49.99#ibcon#flushed, iclass 15, count 0 2006.217.08:17:49.99#ibcon#about to write, iclass 15, count 0 2006.217.08:17:49.99#ibcon#wrote, iclass 15, count 0 2006.217.08:17:49.99#ibcon#about to read 3, iclass 15, count 0 2006.217.08:17:50.03#ibcon#read 3, iclass 15, count 0 2006.217.08:17:50.03#ibcon#about to read 4, iclass 15, count 0 2006.217.08:17:50.03#ibcon#read 4, iclass 15, count 0 2006.217.08:17:50.03#ibcon#about to read 5, iclass 15, count 0 2006.217.08:17:50.03#ibcon#read 5, iclass 15, count 0 2006.217.08:17:50.03#ibcon#about to read 6, iclass 15, count 0 2006.217.08:17:50.03#ibcon#read 6, iclass 15, count 0 2006.217.08:17:50.03#ibcon#end of sib2, iclass 15, count 0 2006.217.08:17:50.03#ibcon#*after write, iclass 15, count 0 2006.217.08:17:50.03#ibcon#*before return 0, iclass 15, count 0 2006.217.08:17:50.03#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.217.08:17:50.03#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.217.08:17:50.03#ibcon#about to clear, iclass 15 cls_cnt 0 2006.217.08:17:50.03#ibcon#cleared, iclass 15 cls_cnt 0 2006.217.08:17:50.03$vc4f8/va=7,6 2006.217.08:17:50.04#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.217.08:17:50.04#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.217.08:17:50.04#ibcon#ireg 11 cls_cnt 2 2006.217.08:17:50.04#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.217.08:17:50.08#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.217.08:17:50.08#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.217.08:17:50.08#ibcon#enter wrdev, iclass 17, count 2 2006.217.08:17:50.08#ibcon#first serial, iclass 17, count 2 2006.217.08:17:50.08#ibcon#enter sib2, iclass 17, count 2 2006.217.08:17:50.08#ibcon#flushed, iclass 17, count 2 2006.217.08:17:50.08#ibcon#about to write, iclass 17, count 2 2006.217.08:17:50.08#ibcon#wrote, iclass 17, count 2 2006.217.08:17:50.08#ibcon#about to read 3, iclass 17, count 2 2006.217.08:17:50.10#ibcon#read 3, iclass 17, count 2 2006.217.08:17:50.10#ibcon#about to read 4, iclass 17, count 2 2006.217.08:17:50.10#ibcon#read 4, iclass 17, count 2 2006.217.08:17:50.10#ibcon#about to read 5, iclass 17, count 2 2006.217.08:17:50.10#ibcon#read 5, iclass 17, count 2 2006.217.08:17:50.10#ibcon#about to read 6, iclass 17, count 2 2006.217.08:17:50.10#ibcon#read 6, iclass 17, count 2 2006.217.08:17:50.10#ibcon#end of sib2, iclass 17, count 2 2006.217.08:17:50.10#ibcon#*mode == 0, iclass 17, count 2 2006.217.08:17:50.10#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.217.08:17:50.10#ibcon#[25=AT07-06\r\n] 2006.217.08:17:50.10#ibcon#*before write, iclass 17, count 2 2006.217.08:17:50.10#ibcon#enter sib2, iclass 17, count 2 2006.217.08:17:50.10#ibcon#flushed, iclass 17, count 2 2006.217.08:17:50.10#ibcon#about to write, iclass 17, count 2 2006.217.08:17:50.10#ibcon#wrote, iclass 17, count 2 2006.217.08:17:50.10#ibcon#about to read 3, iclass 17, count 2 2006.217.08:17:50.13#ibcon#read 3, iclass 17, count 2 2006.217.08:17:50.13#ibcon#about to read 4, iclass 17, count 2 2006.217.08:17:50.13#ibcon#read 4, iclass 17, count 2 2006.217.08:17:50.13#ibcon#about to read 5, iclass 17, count 2 2006.217.08:17:50.13#ibcon#read 5, iclass 17, count 2 2006.217.08:17:50.13#ibcon#about to read 6, iclass 17, count 2 2006.217.08:17:50.13#ibcon#read 6, iclass 17, count 2 2006.217.08:17:50.13#ibcon#end of sib2, iclass 17, count 2 2006.217.08:17:50.13#ibcon#*after write, iclass 17, count 2 2006.217.08:17:50.13#ibcon#*before return 0, iclass 17, count 2 2006.217.08:17:50.13#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.217.08:17:50.13#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.217.08:17:50.13#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.217.08:17:50.13#ibcon#ireg 7 cls_cnt 0 2006.217.08:17:50.13#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.217.08:17:50.25#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.217.08:17:50.25#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.217.08:17:50.25#ibcon#enter wrdev, iclass 17, count 0 2006.217.08:17:50.25#ibcon#first serial, iclass 17, count 0 2006.217.08:17:50.25#ibcon#enter sib2, iclass 17, count 0 2006.217.08:17:50.25#ibcon#flushed, iclass 17, count 0 2006.217.08:17:50.25#ibcon#about to write, iclass 17, count 0 2006.217.08:17:50.25#ibcon#wrote, iclass 17, count 0 2006.217.08:17:50.25#ibcon#about to read 3, iclass 17, count 0 2006.217.08:17:50.27#ibcon#read 3, iclass 17, count 0 2006.217.08:17:50.27#ibcon#about to read 4, iclass 17, count 0 2006.217.08:17:50.27#ibcon#read 4, iclass 17, count 0 2006.217.08:17:50.27#ibcon#about to read 5, iclass 17, count 0 2006.217.08:17:50.27#ibcon#read 5, iclass 17, count 0 2006.217.08:17:50.27#ibcon#about to read 6, iclass 17, count 0 2006.217.08:17:50.27#ibcon#read 6, iclass 17, count 0 2006.217.08:17:50.27#ibcon#end of sib2, iclass 17, count 0 2006.217.08:17:50.27#ibcon#*mode == 0, iclass 17, count 0 2006.217.08:17:50.27#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.217.08:17:50.27#ibcon#[25=USB\r\n] 2006.217.08:17:50.27#ibcon#*before write, iclass 17, count 0 2006.217.08:17:50.27#ibcon#enter sib2, iclass 17, count 0 2006.217.08:17:50.27#ibcon#flushed, iclass 17, count 0 2006.217.08:17:50.27#ibcon#about to write, iclass 17, count 0 2006.217.08:17:50.27#ibcon#wrote, iclass 17, count 0 2006.217.08:17:50.27#ibcon#about to read 3, iclass 17, count 0 2006.217.08:17:50.30#ibcon#read 3, iclass 17, count 0 2006.217.08:17:50.30#ibcon#about to read 4, iclass 17, count 0 2006.217.08:17:50.30#ibcon#read 4, iclass 17, count 0 2006.217.08:17:50.30#ibcon#about to read 5, iclass 17, count 0 2006.217.08:17:50.30#ibcon#read 5, iclass 17, count 0 2006.217.08:17:50.30#ibcon#about to read 6, iclass 17, count 0 2006.217.08:17:50.30#ibcon#read 6, iclass 17, count 0 2006.217.08:17:50.30#ibcon#end of sib2, iclass 17, count 0 2006.217.08:17:50.30#ibcon#*after write, iclass 17, count 0 2006.217.08:17:50.30#ibcon#*before return 0, iclass 17, count 0 2006.217.08:17:50.30#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.217.08:17:50.30#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.217.08:17:50.30#ibcon#about to clear, iclass 17 cls_cnt 0 2006.217.08:17:50.30#ibcon#cleared, iclass 17 cls_cnt 0 2006.217.08:17:50.31$vc4f8/valo=8,852.99 2006.217.08:17:50.31#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.217.08:17:50.31#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.217.08:17:50.31#ibcon#ireg 17 cls_cnt 0 2006.217.08:17:50.31#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.217.08:17:50.31#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.217.08:17:50.31#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.217.08:17:50.31#ibcon#enter wrdev, iclass 19, count 0 2006.217.08:17:50.31#ibcon#first serial, iclass 19, count 0 2006.217.08:17:50.31#ibcon#enter sib2, iclass 19, count 0 2006.217.08:17:50.31#ibcon#flushed, iclass 19, count 0 2006.217.08:17:50.31#ibcon#about to write, iclass 19, count 0 2006.217.08:17:50.31#ibcon#wrote, iclass 19, count 0 2006.217.08:17:50.31#ibcon#about to read 3, iclass 19, count 0 2006.217.08:17:50.33#ibcon#read 3, iclass 19, count 0 2006.217.08:17:50.33#ibcon#about to read 4, iclass 19, count 0 2006.217.08:17:50.33#ibcon#read 4, iclass 19, count 0 2006.217.08:17:50.33#ibcon#about to read 5, iclass 19, count 0 2006.217.08:17:50.33#ibcon#read 5, iclass 19, count 0 2006.217.08:17:50.33#ibcon#about to read 6, iclass 19, count 0 2006.217.08:17:50.33#ibcon#read 6, iclass 19, count 0 2006.217.08:17:50.33#ibcon#end of sib2, iclass 19, count 0 2006.217.08:17:50.33#ibcon#*mode == 0, iclass 19, count 0 2006.217.08:17:50.33#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.217.08:17:50.33#ibcon#[26=FRQ=08,852.99\r\n] 2006.217.08:17:50.33#ibcon#*before write, iclass 19, count 0 2006.217.08:17:50.33#ibcon#enter sib2, iclass 19, count 0 2006.217.08:17:50.33#ibcon#flushed, iclass 19, count 0 2006.217.08:17:50.33#ibcon#about to write, iclass 19, count 0 2006.217.08:17:50.33#ibcon#wrote, iclass 19, count 0 2006.217.08:17:50.33#ibcon#about to read 3, iclass 19, count 0 2006.217.08:17:50.37#ibcon#read 3, iclass 19, count 0 2006.217.08:17:50.37#ibcon#about to read 4, iclass 19, count 0 2006.217.08:17:50.37#ibcon#read 4, iclass 19, count 0 2006.217.08:17:50.37#ibcon#about to read 5, iclass 19, count 0 2006.217.08:17:50.37#ibcon#read 5, iclass 19, count 0 2006.217.08:17:50.37#ibcon#about to read 6, iclass 19, count 0 2006.217.08:17:50.37#ibcon#read 6, iclass 19, count 0 2006.217.08:17:50.37#ibcon#end of sib2, iclass 19, count 0 2006.217.08:17:50.37#ibcon#*after write, iclass 19, count 0 2006.217.08:17:50.37#ibcon#*before return 0, iclass 19, count 0 2006.217.08:17:50.37#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.217.08:17:50.37#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.217.08:17:50.37#ibcon#about to clear, iclass 19 cls_cnt 0 2006.217.08:17:50.37#ibcon#cleared, iclass 19 cls_cnt 0 2006.217.08:17:50.38$vc4f8/va=8,7 2006.217.08:17:50.38#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.217.08:17:50.38#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.217.08:17:50.38#ibcon#ireg 11 cls_cnt 2 2006.217.08:17:50.38#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.217.08:17:50.41#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.217.08:17:50.41#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.217.08:17:50.41#ibcon#enter wrdev, iclass 21, count 2 2006.217.08:17:50.41#ibcon#first serial, iclass 21, count 2 2006.217.08:17:50.41#ibcon#enter sib2, iclass 21, count 2 2006.217.08:17:50.41#ibcon#flushed, iclass 21, count 2 2006.217.08:17:50.41#ibcon#about to write, iclass 21, count 2 2006.217.08:17:50.41#ibcon#wrote, iclass 21, count 2 2006.217.08:17:50.41#ibcon#about to read 3, iclass 21, count 2 2006.217.08:17:50.44#ibcon#read 3, iclass 21, count 2 2006.217.08:17:50.44#ibcon#about to read 4, iclass 21, count 2 2006.217.08:17:50.44#ibcon#read 4, iclass 21, count 2 2006.217.08:17:50.44#ibcon#about to read 5, iclass 21, count 2 2006.217.08:17:50.44#ibcon#read 5, iclass 21, count 2 2006.217.08:17:50.44#ibcon#about to read 6, iclass 21, count 2 2006.217.08:17:50.44#ibcon#read 6, iclass 21, count 2 2006.217.08:17:50.44#ibcon#end of sib2, iclass 21, count 2 2006.217.08:17:50.44#ibcon#*mode == 0, iclass 21, count 2 2006.217.08:17:50.44#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.217.08:17:50.44#ibcon#[25=AT08-07\r\n] 2006.217.08:17:50.44#ibcon#*before write, iclass 21, count 2 2006.217.08:17:50.44#ibcon#enter sib2, iclass 21, count 2 2006.217.08:17:50.44#ibcon#flushed, iclass 21, count 2 2006.217.08:17:50.44#ibcon#about to write, iclass 21, count 2 2006.217.08:17:50.44#ibcon#wrote, iclass 21, count 2 2006.217.08:17:50.44#ibcon#about to read 3, iclass 21, count 2 2006.217.08:17:50.47#ibcon#read 3, iclass 21, count 2 2006.217.08:17:50.47#ibcon#about to read 4, iclass 21, count 2 2006.217.08:17:50.47#ibcon#read 4, iclass 21, count 2 2006.217.08:17:50.47#ibcon#about to read 5, iclass 21, count 2 2006.217.08:17:50.47#ibcon#read 5, iclass 21, count 2 2006.217.08:17:50.47#ibcon#about to read 6, iclass 21, count 2 2006.217.08:17:50.47#ibcon#read 6, iclass 21, count 2 2006.217.08:17:50.47#ibcon#end of sib2, iclass 21, count 2 2006.217.08:17:50.47#ibcon#*after write, iclass 21, count 2 2006.217.08:17:50.47#ibcon#*before return 0, iclass 21, count 2 2006.217.08:17:50.47#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.217.08:17:50.47#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.217.08:17:50.47#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.217.08:17:50.47#ibcon#ireg 7 cls_cnt 0 2006.217.08:17:50.47#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.217.08:17:50.59#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.217.08:17:50.59#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.217.08:17:50.59#ibcon#enter wrdev, iclass 21, count 0 2006.217.08:17:50.59#ibcon#first serial, iclass 21, count 0 2006.217.08:17:50.59#ibcon#enter sib2, iclass 21, count 0 2006.217.08:17:50.59#ibcon#flushed, iclass 21, count 0 2006.217.08:17:50.59#ibcon#about to write, iclass 21, count 0 2006.217.08:17:50.59#ibcon#wrote, iclass 21, count 0 2006.217.08:17:50.59#ibcon#about to read 3, iclass 21, count 0 2006.217.08:17:50.61#ibcon#read 3, iclass 21, count 0 2006.217.08:17:50.61#ibcon#about to read 4, iclass 21, count 0 2006.217.08:17:50.61#ibcon#read 4, iclass 21, count 0 2006.217.08:17:50.61#ibcon#about to read 5, iclass 21, count 0 2006.217.08:17:50.61#ibcon#read 5, iclass 21, count 0 2006.217.08:17:50.61#ibcon#about to read 6, iclass 21, count 0 2006.217.08:17:50.61#ibcon#read 6, iclass 21, count 0 2006.217.08:17:50.61#ibcon#end of sib2, iclass 21, count 0 2006.217.08:17:50.61#ibcon#*mode == 0, iclass 21, count 0 2006.217.08:17:50.61#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.217.08:17:50.61#ibcon#[25=USB\r\n] 2006.217.08:17:50.61#ibcon#*before write, iclass 21, count 0 2006.217.08:17:50.61#ibcon#enter sib2, iclass 21, count 0 2006.217.08:17:50.61#ibcon#flushed, iclass 21, count 0 2006.217.08:17:50.61#ibcon#about to write, iclass 21, count 0 2006.217.08:17:50.61#ibcon#wrote, iclass 21, count 0 2006.217.08:17:50.61#ibcon#about to read 3, iclass 21, count 0 2006.217.08:17:50.64#ibcon#read 3, iclass 21, count 0 2006.217.08:17:50.64#ibcon#about to read 4, iclass 21, count 0 2006.217.08:17:50.64#ibcon#read 4, iclass 21, count 0 2006.217.08:17:50.64#ibcon#about to read 5, iclass 21, count 0 2006.217.08:17:50.64#ibcon#read 5, iclass 21, count 0 2006.217.08:17:50.64#ibcon#about to read 6, iclass 21, count 0 2006.217.08:17:50.64#ibcon#read 6, iclass 21, count 0 2006.217.08:17:50.64#ibcon#end of sib2, iclass 21, count 0 2006.217.08:17:50.64#ibcon#*after write, iclass 21, count 0 2006.217.08:17:50.64#ibcon#*before return 0, iclass 21, count 0 2006.217.08:17:50.64#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.217.08:17:50.64#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.217.08:17:50.64#ibcon#about to clear, iclass 21 cls_cnt 0 2006.217.08:17:50.64#ibcon#cleared, iclass 21 cls_cnt 0 2006.217.08:17:50.64$vc4f8/vblo=1,632.99 2006.217.08:17:50.65#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.217.08:17:50.65#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.217.08:17:50.65#ibcon#ireg 17 cls_cnt 0 2006.217.08:17:50.65#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.217.08:17:50.65#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.217.08:17:50.65#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.217.08:17:50.65#ibcon#enter wrdev, iclass 23, count 0 2006.217.08:17:50.65#ibcon#first serial, iclass 23, count 0 2006.217.08:17:50.65#ibcon#enter sib2, iclass 23, count 0 2006.217.08:17:50.65#ibcon#flushed, iclass 23, count 0 2006.217.08:17:50.65#ibcon#about to write, iclass 23, count 0 2006.217.08:17:50.65#ibcon#wrote, iclass 23, count 0 2006.217.08:17:50.65#ibcon#about to read 3, iclass 23, count 0 2006.217.08:17:50.66#ibcon#read 3, iclass 23, count 0 2006.217.08:17:50.66#ibcon#about to read 4, iclass 23, count 0 2006.217.08:17:50.66#ibcon#read 4, iclass 23, count 0 2006.217.08:17:50.66#ibcon#about to read 5, iclass 23, count 0 2006.217.08:17:50.66#ibcon#read 5, iclass 23, count 0 2006.217.08:17:50.66#ibcon#about to read 6, iclass 23, count 0 2006.217.08:17:50.66#ibcon#read 6, iclass 23, count 0 2006.217.08:17:50.66#ibcon#end of sib2, iclass 23, count 0 2006.217.08:17:50.66#ibcon#*mode == 0, iclass 23, count 0 2006.217.08:17:50.66#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.217.08:17:50.66#ibcon#[28=FRQ=01,632.99\r\n] 2006.217.08:17:50.66#ibcon#*before write, iclass 23, count 0 2006.217.08:17:50.66#ibcon#enter sib2, iclass 23, count 0 2006.217.08:17:50.66#ibcon#flushed, iclass 23, count 0 2006.217.08:17:50.66#ibcon#about to write, iclass 23, count 0 2006.217.08:17:50.66#ibcon#wrote, iclass 23, count 0 2006.217.08:17:50.66#ibcon#about to read 3, iclass 23, count 0 2006.217.08:17:50.70#ibcon#read 3, iclass 23, count 0 2006.217.08:17:50.70#ibcon#about to read 4, iclass 23, count 0 2006.217.08:17:50.70#ibcon#read 4, iclass 23, count 0 2006.217.08:17:50.70#ibcon#about to read 5, iclass 23, count 0 2006.217.08:17:50.70#ibcon#read 5, iclass 23, count 0 2006.217.08:17:50.70#ibcon#about to read 6, iclass 23, count 0 2006.217.08:17:50.70#ibcon#read 6, iclass 23, count 0 2006.217.08:17:50.70#ibcon#end of sib2, iclass 23, count 0 2006.217.08:17:50.70#ibcon#*after write, iclass 23, count 0 2006.217.08:17:50.70#ibcon#*before return 0, iclass 23, count 0 2006.217.08:17:50.70#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.217.08:17:50.70#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.217.08:17:50.70#ibcon#about to clear, iclass 23 cls_cnt 0 2006.217.08:17:50.70#ibcon#cleared, iclass 23 cls_cnt 0 2006.217.08:17:50.70$vc4f8/vb=1,4 2006.217.08:17:50.71#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.217.08:17:50.71#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.217.08:17:50.71#ibcon#ireg 11 cls_cnt 2 2006.217.08:17:50.71#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.217.08:17:50.71#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.217.08:17:50.71#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.217.08:17:50.71#ibcon#enter wrdev, iclass 25, count 2 2006.217.08:17:50.71#ibcon#first serial, iclass 25, count 2 2006.217.08:17:50.71#ibcon#enter sib2, iclass 25, count 2 2006.217.08:17:50.71#ibcon#flushed, iclass 25, count 2 2006.217.08:17:50.71#ibcon#about to write, iclass 25, count 2 2006.217.08:17:50.71#ibcon#wrote, iclass 25, count 2 2006.217.08:17:50.71#ibcon#about to read 3, iclass 25, count 2 2006.217.08:17:50.72#ibcon#read 3, iclass 25, count 2 2006.217.08:17:50.72#ibcon#about to read 4, iclass 25, count 2 2006.217.08:17:50.72#ibcon#read 4, iclass 25, count 2 2006.217.08:17:50.72#ibcon#about to read 5, iclass 25, count 2 2006.217.08:17:50.72#ibcon#read 5, iclass 25, count 2 2006.217.08:17:50.72#ibcon#about to read 6, iclass 25, count 2 2006.217.08:17:50.72#ibcon#read 6, iclass 25, count 2 2006.217.08:17:50.72#ibcon#end of sib2, iclass 25, count 2 2006.217.08:17:50.72#ibcon#*mode == 0, iclass 25, count 2 2006.217.08:17:50.72#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.217.08:17:50.72#ibcon#[27=AT01-04\r\n] 2006.217.08:17:50.72#ibcon#*before write, iclass 25, count 2 2006.217.08:17:50.72#ibcon#enter sib2, iclass 25, count 2 2006.217.08:17:50.72#ibcon#flushed, iclass 25, count 2 2006.217.08:17:50.72#ibcon#about to write, iclass 25, count 2 2006.217.08:17:50.72#ibcon#wrote, iclass 25, count 2 2006.217.08:17:50.72#ibcon#about to read 3, iclass 25, count 2 2006.217.08:17:50.75#ibcon#read 3, iclass 25, count 2 2006.217.08:17:50.75#ibcon#about to read 4, iclass 25, count 2 2006.217.08:17:50.75#ibcon#read 4, iclass 25, count 2 2006.217.08:17:50.75#ibcon#about to read 5, iclass 25, count 2 2006.217.08:17:50.75#ibcon#read 5, iclass 25, count 2 2006.217.08:17:50.75#ibcon#about to read 6, iclass 25, count 2 2006.217.08:17:50.75#ibcon#read 6, iclass 25, count 2 2006.217.08:17:50.75#ibcon#end of sib2, iclass 25, count 2 2006.217.08:17:50.75#ibcon#*after write, iclass 25, count 2 2006.217.08:17:50.75#ibcon#*before return 0, iclass 25, count 2 2006.217.08:17:50.75#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.217.08:17:50.75#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.217.08:17:50.75#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.217.08:17:50.75#ibcon#ireg 7 cls_cnt 0 2006.217.08:17:50.75#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.217.08:17:50.87#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.217.08:17:50.87#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.217.08:17:50.87#ibcon#enter wrdev, iclass 25, count 0 2006.217.08:17:50.87#ibcon#first serial, iclass 25, count 0 2006.217.08:17:50.87#ibcon#enter sib2, iclass 25, count 0 2006.217.08:17:50.87#ibcon#flushed, iclass 25, count 0 2006.217.08:17:50.87#ibcon#about to write, iclass 25, count 0 2006.217.08:17:50.87#ibcon#wrote, iclass 25, count 0 2006.217.08:17:50.87#ibcon#about to read 3, iclass 25, count 0 2006.217.08:17:50.89#ibcon#read 3, iclass 25, count 0 2006.217.08:17:50.89#ibcon#about to read 4, iclass 25, count 0 2006.217.08:17:50.89#ibcon#read 4, iclass 25, count 0 2006.217.08:17:50.89#ibcon#about to read 5, iclass 25, count 0 2006.217.08:17:50.89#ibcon#read 5, iclass 25, count 0 2006.217.08:17:50.89#ibcon#about to read 6, iclass 25, count 0 2006.217.08:17:50.89#ibcon#read 6, iclass 25, count 0 2006.217.08:17:50.89#ibcon#end of sib2, iclass 25, count 0 2006.217.08:17:50.89#ibcon#*mode == 0, iclass 25, count 0 2006.217.08:17:50.89#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.217.08:17:50.89#ibcon#[27=USB\r\n] 2006.217.08:17:50.89#ibcon#*before write, iclass 25, count 0 2006.217.08:17:50.89#ibcon#enter sib2, iclass 25, count 0 2006.217.08:17:50.89#ibcon#flushed, iclass 25, count 0 2006.217.08:17:50.89#ibcon#about to write, iclass 25, count 0 2006.217.08:17:50.89#ibcon#wrote, iclass 25, count 0 2006.217.08:17:50.89#ibcon#about to read 3, iclass 25, count 0 2006.217.08:17:50.92#ibcon#read 3, iclass 25, count 0 2006.217.08:17:50.92#ibcon#about to read 4, iclass 25, count 0 2006.217.08:17:50.92#ibcon#read 4, iclass 25, count 0 2006.217.08:17:50.92#ibcon#about to read 5, iclass 25, count 0 2006.217.08:17:50.92#ibcon#read 5, iclass 25, count 0 2006.217.08:17:50.92#ibcon#about to read 6, iclass 25, count 0 2006.217.08:17:50.92#ibcon#read 6, iclass 25, count 0 2006.217.08:17:50.92#ibcon#end of sib2, iclass 25, count 0 2006.217.08:17:50.92#ibcon#*after write, iclass 25, count 0 2006.217.08:17:50.92#ibcon#*before return 0, iclass 25, count 0 2006.217.08:17:50.92#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.217.08:17:50.92#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.217.08:17:50.92#ibcon#about to clear, iclass 25 cls_cnt 0 2006.217.08:17:50.92#ibcon#cleared, iclass 25 cls_cnt 0 2006.217.08:17:50.92$vc4f8/vblo=2,640.99 2006.217.08:17:50.93#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.217.08:17:50.93#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.217.08:17:50.93#ibcon#ireg 17 cls_cnt 0 2006.217.08:17:50.93#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.217.08:17:50.93#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.217.08:17:50.93#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.217.08:17:50.93#ibcon#enter wrdev, iclass 27, count 0 2006.217.08:17:50.93#ibcon#first serial, iclass 27, count 0 2006.217.08:17:50.93#ibcon#enter sib2, iclass 27, count 0 2006.217.08:17:50.93#ibcon#flushed, iclass 27, count 0 2006.217.08:17:50.93#ibcon#about to write, iclass 27, count 0 2006.217.08:17:50.93#ibcon#wrote, iclass 27, count 0 2006.217.08:17:50.93#ibcon#about to read 3, iclass 27, count 0 2006.217.08:17:50.95#ibcon#read 3, iclass 27, count 0 2006.217.08:17:50.95#ibcon#about to read 4, iclass 27, count 0 2006.217.08:17:50.95#ibcon#read 4, iclass 27, count 0 2006.217.08:17:50.95#ibcon#about to read 5, iclass 27, count 0 2006.217.08:17:50.95#ibcon#read 5, iclass 27, count 0 2006.217.08:17:50.95#ibcon#about to read 6, iclass 27, count 0 2006.217.08:17:50.95#ibcon#read 6, iclass 27, count 0 2006.217.08:17:50.95#ibcon#end of sib2, iclass 27, count 0 2006.217.08:17:50.95#ibcon#*mode == 0, iclass 27, count 0 2006.217.08:17:50.95#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.217.08:17:50.95#ibcon#[28=FRQ=02,640.99\r\n] 2006.217.08:17:50.95#ibcon#*before write, iclass 27, count 0 2006.217.08:17:50.95#ibcon#enter sib2, iclass 27, count 0 2006.217.08:17:50.95#ibcon#flushed, iclass 27, count 0 2006.217.08:17:50.95#ibcon#about to write, iclass 27, count 0 2006.217.08:17:50.95#ibcon#wrote, iclass 27, count 0 2006.217.08:17:50.95#ibcon#about to read 3, iclass 27, count 0 2006.217.08:17:50.99#ibcon#read 3, iclass 27, count 0 2006.217.08:17:50.99#ibcon#about to read 4, iclass 27, count 0 2006.217.08:17:50.99#ibcon#read 4, iclass 27, count 0 2006.217.08:17:50.99#ibcon#about to read 5, iclass 27, count 0 2006.217.08:17:50.99#ibcon#read 5, iclass 27, count 0 2006.217.08:17:50.99#ibcon#about to read 6, iclass 27, count 0 2006.217.08:17:50.99#ibcon#read 6, iclass 27, count 0 2006.217.08:17:50.99#ibcon#end of sib2, iclass 27, count 0 2006.217.08:17:50.99#ibcon#*after write, iclass 27, count 0 2006.217.08:17:50.99#ibcon#*before return 0, iclass 27, count 0 2006.217.08:17:50.99#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.217.08:17:50.99#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.217.08:17:50.99#ibcon#about to clear, iclass 27 cls_cnt 0 2006.217.08:17:50.99#ibcon#cleared, iclass 27 cls_cnt 0 2006.217.08:17:51.00$vc4f8/vb=2,4 2006.217.08:17:51.00#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.217.08:17:51.00#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.217.08:17:51.00#ibcon#ireg 11 cls_cnt 2 2006.217.08:17:51.00#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.217.08:17:51.03#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.217.08:17:51.03#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.217.08:17:51.03#ibcon#enter wrdev, iclass 29, count 2 2006.217.08:17:51.03#ibcon#first serial, iclass 29, count 2 2006.217.08:17:51.03#ibcon#enter sib2, iclass 29, count 2 2006.217.08:17:51.03#ibcon#flushed, iclass 29, count 2 2006.217.08:17:51.03#ibcon#about to write, iclass 29, count 2 2006.217.08:17:51.03#ibcon#wrote, iclass 29, count 2 2006.217.08:17:51.03#ibcon#about to read 3, iclass 29, count 2 2006.217.08:17:51.06#ibcon#read 3, iclass 29, count 2 2006.217.08:17:51.06#ibcon#about to read 4, iclass 29, count 2 2006.217.08:17:51.06#ibcon#read 4, iclass 29, count 2 2006.217.08:17:51.06#ibcon#about to read 5, iclass 29, count 2 2006.217.08:17:51.06#ibcon#read 5, iclass 29, count 2 2006.217.08:17:51.06#ibcon#about to read 6, iclass 29, count 2 2006.217.08:17:51.06#ibcon#read 6, iclass 29, count 2 2006.217.08:17:51.06#ibcon#end of sib2, iclass 29, count 2 2006.217.08:17:51.06#ibcon#*mode == 0, iclass 29, count 2 2006.217.08:17:51.06#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.217.08:17:51.06#ibcon#[27=AT02-04\r\n] 2006.217.08:17:51.06#ibcon#*before write, iclass 29, count 2 2006.217.08:17:51.06#ibcon#enter sib2, iclass 29, count 2 2006.217.08:17:51.06#ibcon#flushed, iclass 29, count 2 2006.217.08:17:51.06#ibcon#about to write, iclass 29, count 2 2006.217.08:17:51.06#ibcon#wrote, iclass 29, count 2 2006.217.08:17:51.06#ibcon#about to read 3, iclass 29, count 2 2006.217.08:17:51.09#ibcon#read 3, iclass 29, count 2 2006.217.08:17:51.09#ibcon#about to read 4, iclass 29, count 2 2006.217.08:17:51.09#ibcon#read 4, iclass 29, count 2 2006.217.08:17:51.09#ibcon#about to read 5, iclass 29, count 2 2006.217.08:17:51.09#ibcon#read 5, iclass 29, count 2 2006.217.08:17:51.09#ibcon#about to read 6, iclass 29, count 2 2006.217.08:17:51.09#ibcon#read 6, iclass 29, count 2 2006.217.08:17:51.09#ibcon#end of sib2, iclass 29, count 2 2006.217.08:17:51.09#ibcon#*after write, iclass 29, count 2 2006.217.08:17:51.09#ibcon#*before return 0, iclass 29, count 2 2006.217.08:17:51.09#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.217.08:17:51.09#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.217.08:17:51.09#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.217.08:17:51.09#ibcon#ireg 7 cls_cnt 0 2006.217.08:17:51.09#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.217.08:17:51.21#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.217.08:17:51.21#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.217.08:17:51.21#ibcon#enter wrdev, iclass 29, count 0 2006.217.08:17:51.21#ibcon#first serial, iclass 29, count 0 2006.217.08:17:51.21#ibcon#enter sib2, iclass 29, count 0 2006.217.08:17:51.21#ibcon#flushed, iclass 29, count 0 2006.217.08:17:51.21#ibcon#about to write, iclass 29, count 0 2006.217.08:17:51.21#ibcon#wrote, iclass 29, count 0 2006.217.08:17:51.21#ibcon#about to read 3, iclass 29, count 0 2006.217.08:17:51.23#ibcon#read 3, iclass 29, count 0 2006.217.08:17:51.23#ibcon#about to read 4, iclass 29, count 0 2006.217.08:17:51.23#ibcon#read 4, iclass 29, count 0 2006.217.08:17:51.23#ibcon#about to read 5, iclass 29, count 0 2006.217.08:17:51.23#ibcon#read 5, iclass 29, count 0 2006.217.08:17:51.23#ibcon#about to read 6, iclass 29, count 0 2006.217.08:17:51.23#ibcon#read 6, iclass 29, count 0 2006.217.08:17:51.23#ibcon#end of sib2, iclass 29, count 0 2006.217.08:17:51.23#ibcon#*mode == 0, iclass 29, count 0 2006.217.08:17:51.23#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.217.08:17:51.23#ibcon#[27=USB\r\n] 2006.217.08:17:51.23#ibcon#*before write, iclass 29, count 0 2006.217.08:17:51.23#ibcon#enter sib2, iclass 29, count 0 2006.217.08:17:51.23#ibcon#flushed, iclass 29, count 0 2006.217.08:17:51.23#ibcon#about to write, iclass 29, count 0 2006.217.08:17:51.23#ibcon#wrote, iclass 29, count 0 2006.217.08:17:51.23#ibcon#about to read 3, iclass 29, count 0 2006.217.08:17:51.26#ibcon#read 3, iclass 29, count 0 2006.217.08:17:51.26#ibcon#about to read 4, iclass 29, count 0 2006.217.08:17:51.26#ibcon#read 4, iclass 29, count 0 2006.217.08:17:51.26#ibcon#about to read 5, iclass 29, count 0 2006.217.08:17:51.26#ibcon#read 5, iclass 29, count 0 2006.217.08:17:51.26#ibcon#about to read 6, iclass 29, count 0 2006.217.08:17:51.26#ibcon#read 6, iclass 29, count 0 2006.217.08:17:51.26#ibcon#end of sib2, iclass 29, count 0 2006.217.08:17:51.26#ibcon#*after write, iclass 29, count 0 2006.217.08:17:51.26#ibcon#*before return 0, iclass 29, count 0 2006.217.08:17:51.26#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.217.08:17:51.26#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.217.08:17:51.26#ibcon#about to clear, iclass 29 cls_cnt 0 2006.217.08:17:51.26#ibcon#cleared, iclass 29 cls_cnt 0 2006.217.08:17:51.27$vc4f8/vblo=3,656.99 2006.217.08:17:51.27#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.217.08:17:51.27#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.217.08:17:51.27#ibcon#ireg 17 cls_cnt 0 2006.217.08:17:51.27#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.217.08:17:51.27#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.217.08:17:51.27#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.217.08:17:51.27#ibcon#enter wrdev, iclass 31, count 0 2006.217.08:17:51.27#ibcon#first serial, iclass 31, count 0 2006.217.08:17:51.27#ibcon#enter sib2, iclass 31, count 0 2006.217.08:17:51.27#ibcon#flushed, iclass 31, count 0 2006.217.08:17:51.27#ibcon#about to write, iclass 31, count 0 2006.217.08:17:51.27#ibcon#wrote, iclass 31, count 0 2006.217.08:17:51.27#ibcon#about to read 3, iclass 31, count 0 2006.217.08:17:51.28#ibcon#read 3, iclass 31, count 0 2006.217.08:17:51.28#ibcon#about to read 4, iclass 31, count 0 2006.217.08:17:51.28#ibcon#read 4, iclass 31, count 0 2006.217.08:17:51.28#ibcon#about to read 5, iclass 31, count 0 2006.217.08:17:51.28#ibcon#read 5, iclass 31, count 0 2006.217.08:17:51.28#ibcon#about to read 6, iclass 31, count 0 2006.217.08:17:51.28#ibcon#read 6, iclass 31, count 0 2006.217.08:17:51.28#ibcon#end of sib2, iclass 31, count 0 2006.217.08:17:51.28#ibcon#*mode == 0, iclass 31, count 0 2006.217.08:17:51.28#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.217.08:17:51.28#ibcon#[28=FRQ=03,656.99\r\n] 2006.217.08:17:51.28#ibcon#*before write, iclass 31, count 0 2006.217.08:17:51.28#ibcon#enter sib2, iclass 31, count 0 2006.217.08:17:51.28#ibcon#flushed, iclass 31, count 0 2006.217.08:17:51.28#ibcon#about to write, iclass 31, count 0 2006.217.08:17:51.28#ibcon#wrote, iclass 31, count 0 2006.217.08:17:51.28#ibcon#about to read 3, iclass 31, count 0 2006.217.08:17:51.32#ibcon#read 3, iclass 31, count 0 2006.217.08:17:51.32#ibcon#about to read 4, iclass 31, count 0 2006.217.08:17:51.32#ibcon#read 4, iclass 31, count 0 2006.217.08:17:51.32#ibcon#about to read 5, iclass 31, count 0 2006.217.08:17:51.32#ibcon#read 5, iclass 31, count 0 2006.217.08:17:51.32#ibcon#about to read 6, iclass 31, count 0 2006.217.08:17:51.32#ibcon#read 6, iclass 31, count 0 2006.217.08:17:51.32#ibcon#end of sib2, iclass 31, count 0 2006.217.08:17:51.32#ibcon#*after write, iclass 31, count 0 2006.217.08:17:51.32#ibcon#*before return 0, iclass 31, count 0 2006.217.08:17:51.32#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.217.08:17:51.32#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.217.08:17:51.32#ibcon#about to clear, iclass 31 cls_cnt 0 2006.217.08:17:51.32#ibcon#cleared, iclass 31 cls_cnt 0 2006.217.08:17:51.32$vc4f8/vb=3,4 2006.217.08:17:51.33#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.217.08:17:51.33#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.217.08:17:51.33#ibcon#ireg 11 cls_cnt 2 2006.217.08:17:51.33#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.217.08:17:51.37#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.217.08:17:51.37#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.217.08:17:51.37#ibcon#enter wrdev, iclass 33, count 2 2006.217.08:17:51.37#ibcon#first serial, iclass 33, count 2 2006.217.08:17:51.37#ibcon#enter sib2, iclass 33, count 2 2006.217.08:17:51.37#ibcon#flushed, iclass 33, count 2 2006.217.08:17:51.37#ibcon#about to write, iclass 33, count 2 2006.217.08:17:51.37#ibcon#wrote, iclass 33, count 2 2006.217.08:17:51.37#ibcon#about to read 3, iclass 33, count 2 2006.217.08:17:51.39#ibcon#read 3, iclass 33, count 2 2006.217.08:17:51.39#ibcon#about to read 4, iclass 33, count 2 2006.217.08:17:51.39#ibcon#read 4, iclass 33, count 2 2006.217.08:17:51.39#ibcon#about to read 5, iclass 33, count 2 2006.217.08:17:51.39#ibcon#read 5, iclass 33, count 2 2006.217.08:17:51.39#ibcon#about to read 6, iclass 33, count 2 2006.217.08:17:51.39#ibcon#read 6, iclass 33, count 2 2006.217.08:17:51.39#ibcon#end of sib2, iclass 33, count 2 2006.217.08:17:51.39#ibcon#*mode == 0, iclass 33, count 2 2006.217.08:17:51.39#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.217.08:17:51.39#ibcon#[27=AT03-04\r\n] 2006.217.08:17:51.39#ibcon#*before write, iclass 33, count 2 2006.217.08:17:51.39#ibcon#enter sib2, iclass 33, count 2 2006.217.08:17:51.39#ibcon#flushed, iclass 33, count 2 2006.217.08:17:51.39#ibcon#about to write, iclass 33, count 2 2006.217.08:17:51.39#ibcon#wrote, iclass 33, count 2 2006.217.08:17:51.39#ibcon#about to read 3, iclass 33, count 2 2006.217.08:17:51.42#ibcon#read 3, iclass 33, count 2 2006.217.08:17:51.42#ibcon#about to read 4, iclass 33, count 2 2006.217.08:17:51.42#ibcon#read 4, iclass 33, count 2 2006.217.08:17:51.42#ibcon#about to read 5, iclass 33, count 2 2006.217.08:17:51.42#ibcon#read 5, iclass 33, count 2 2006.217.08:17:51.42#ibcon#about to read 6, iclass 33, count 2 2006.217.08:17:51.42#ibcon#read 6, iclass 33, count 2 2006.217.08:17:51.42#ibcon#end of sib2, iclass 33, count 2 2006.217.08:17:51.42#ibcon#*after write, iclass 33, count 2 2006.217.08:17:51.42#ibcon#*before return 0, iclass 33, count 2 2006.217.08:17:51.42#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.217.08:17:51.42#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.217.08:17:51.42#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.217.08:17:51.42#ibcon#ireg 7 cls_cnt 0 2006.217.08:17:51.42#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.217.08:17:51.54#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.217.08:17:51.54#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.217.08:17:51.54#ibcon#enter wrdev, iclass 33, count 0 2006.217.08:17:51.54#ibcon#first serial, iclass 33, count 0 2006.217.08:17:51.54#ibcon#enter sib2, iclass 33, count 0 2006.217.08:17:51.54#ibcon#flushed, iclass 33, count 0 2006.217.08:17:51.54#ibcon#about to write, iclass 33, count 0 2006.217.08:17:51.54#ibcon#wrote, iclass 33, count 0 2006.217.08:17:51.54#ibcon#about to read 3, iclass 33, count 0 2006.217.08:17:51.56#ibcon#read 3, iclass 33, count 0 2006.217.08:17:51.56#ibcon#about to read 4, iclass 33, count 0 2006.217.08:17:51.56#ibcon#read 4, iclass 33, count 0 2006.217.08:17:51.56#ibcon#about to read 5, iclass 33, count 0 2006.217.08:17:51.56#ibcon#read 5, iclass 33, count 0 2006.217.08:17:51.56#ibcon#about to read 6, iclass 33, count 0 2006.217.08:17:51.56#ibcon#read 6, iclass 33, count 0 2006.217.08:17:51.56#ibcon#end of sib2, iclass 33, count 0 2006.217.08:17:51.56#ibcon#*mode == 0, iclass 33, count 0 2006.217.08:17:51.56#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.217.08:17:51.56#ibcon#[27=USB\r\n] 2006.217.08:17:51.56#ibcon#*before write, iclass 33, count 0 2006.217.08:17:51.56#ibcon#enter sib2, iclass 33, count 0 2006.217.08:17:51.56#ibcon#flushed, iclass 33, count 0 2006.217.08:17:51.56#ibcon#about to write, iclass 33, count 0 2006.217.08:17:51.56#ibcon#wrote, iclass 33, count 0 2006.217.08:17:51.56#ibcon#about to read 3, iclass 33, count 0 2006.217.08:17:51.59#ibcon#read 3, iclass 33, count 0 2006.217.08:17:51.59#ibcon#about to read 4, iclass 33, count 0 2006.217.08:17:51.59#ibcon#read 4, iclass 33, count 0 2006.217.08:17:51.59#ibcon#about to read 5, iclass 33, count 0 2006.217.08:17:51.59#ibcon#read 5, iclass 33, count 0 2006.217.08:17:51.59#ibcon#about to read 6, iclass 33, count 0 2006.217.08:17:51.59#ibcon#read 6, iclass 33, count 0 2006.217.08:17:51.59#ibcon#end of sib2, iclass 33, count 0 2006.217.08:17:51.59#ibcon#*after write, iclass 33, count 0 2006.217.08:17:51.59#ibcon#*before return 0, iclass 33, count 0 2006.217.08:17:51.59#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.217.08:17:51.59#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.217.08:17:51.59#ibcon#about to clear, iclass 33 cls_cnt 0 2006.217.08:17:51.59#ibcon#cleared, iclass 33 cls_cnt 0 2006.217.08:17:51.59$vc4f8/vblo=4,712.99 2006.217.08:17:51.60#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.217.08:17:51.60#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.217.08:17:51.60#ibcon#ireg 17 cls_cnt 0 2006.217.08:17:51.60#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.217.08:17:51.60#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.217.08:17:51.60#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.217.08:17:51.60#ibcon#enter wrdev, iclass 35, count 0 2006.217.08:17:51.60#ibcon#first serial, iclass 35, count 0 2006.217.08:17:51.60#ibcon#enter sib2, iclass 35, count 0 2006.217.08:17:51.60#ibcon#flushed, iclass 35, count 0 2006.217.08:17:51.60#ibcon#about to write, iclass 35, count 0 2006.217.08:17:51.60#ibcon#wrote, iclass 35, count 0 2006.217.08:17:51.60#ibcon#about to read 3, iclass 35, count 0 2006.217.08:17:51.61#ibcon#read 3, iclass 35, count 0 2006.217.08:17:51.61#ibcon#about to read 4, iclass 35, count 0 2006.217.08:17:51.61#ibcon#read 4, iclass 35, count 0 2006.217.08:17:51.61#ibcon#about to read 5, iclass 35, count 0 2006.217.08:17:51.61#ibcon#read 5, iclass 35, count 0 2006.217.08:17:51.61#ibcon#about to read 6, iclass 35, count 0 2006.217.08:17:51.61#ibcon#read 6, iclass 35, count 0 2006.217.08:17:51.61#ibcon#end of sib2, iclass 35, count 0 2006.217.08:17:51.61#ibcon#*mode == 0, iclass 35, count 0 2006.217.08:17:51.61#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.217.08:17:51.61#ibcon#[28=FRQ=04,712.99\r\n] 2006.217.08:17:51.61#ibcon#*before write, iclass 35, count 0 2006.217.08:17:51.61#ibcon#enter sib2, iclass 35, count 0 2006.217.08:17:51.61#ibcon#flushed, iclass 35, count 0 2006.217.08:17:51.61#ibcon#about to write, iclass 35, count 0 2006.217.08:17:51.61#ibcon#wrote, iclass 35, count 0 2006.217.08:17:51.61#ibcon#about to read 3, iclass 35, count 0 2006.217.08:17:51.65#ibcon#read 3, iclass 35, count 0 2006.217.08:17:51.65#ibcon#about to read 4, iclass 35, count 0 2006.217.08:17:51.65#ibcon#read 4, iclass 35, count 0 2006.217.08:17:51.65#ibcon#about to read 5, iclass 35, count 0 2006.217.08:17:51.65#ibcon#read 5, iclass 35, count 0 2006.217.08:17:51.65#ibcon#about to read 6, iclass 35, count 0 2006.217.08:17:51.65#ibcon#read 6, iclass 35, count 0 2006.217.08:17:51.65#ibcon#end of sib2, iclass 35, count 0 2006.217.08:17:51.65#ibcon#*after write, iclass 35, count 0 2006.217.08:17:51.65#ibcon#*before return 0, iclass 35, count 0 2006.217.08:17:51.65#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.217.08:17:51.65#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.217.08:17:51.65#ibcon#about to clear, iclass 35 cls_cnt 0 2006.217.08:17:51.65#ibcon#cleared, iclass 35 cls_cnt 0 2006.217.08:17:51.66$vc4f8/vb=4,4 2006.217.08:17:51.66#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.217.08:17:51.66#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.217.08:17:51.66#ibcon#ireg 11 cls_cnt 2 2006.217.08:17:51.66#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.217.08:17:51.70#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.217.08:17:51.70#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.217.08:17:51.70#ibcon#enter wrdev, iclass 37, count 2 2006.217.08:17:51.70#ibcon#first serial, iclass 37, count 2 2006.217.08:17:51.70#ibcon#enter sib2, iclass 37, count 2 2006.217.08:17:51.70#ibcon#flushed, iclass 37, count 2 2006.217.08:17:51.70#ibcon#about to write, iclass 37, count 2 2006.217.08:17:51.70#ibcon#wrote, iclass 37, count 2 2006.217.08:17:51.70#ibcon#about to read 3, iclass 37, count 2 2006.217.08:17:51.72#ibcon#read 3, iclass 37, count 2 2006.217.08:17:51.72#ibcon#about to read 4, iclass 37, count 2 2006.217.08:17:51.72#ibcon#read 4, iclass 37, count 2 2006.217.08:17:51.72#ibcon#about to read 5, iclass 37, count 2 2006.217.08:17:51.72#ibcon#read 5, iclass 37, count 2 2006.217.08:17:51.72#ibcon#about to read 6, iclass 37, count 2 2006.217.08:17:51.72#ibcon#read 6, iclass 37, count 2 2006.217.08:17:51.72#ibcon#end of sib2, iclass 37, count 2 2006.217.08:17:51.72#ibcon#*mode == 0, iclass 37, count 2 2006.217.08:17:51.72#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.217.08:17:51.72#ibcon#[27=AT04-04\r\n] 2006.217.08:17:51.72#ibcon#*before write, iclass 37, count 2 2006.217.08:17:51.72#ibcon#enter sib2, iclass 37, count 2 2006.217.08:17:51.72#ibcon#flushed, iclass 37, count 2 2006.217.08:17:51.72#ibcon#about to write, iclass 37, count 2 2006.217.08:17:51.72#ibcon#wrote, iclass 37, count 2 2006.217.08:17:51.72#ibcon#about to read 3, iclass 37, count 2 2006.217.08:17:51.75#ibcon#read 3, iclass 37, count 2 2006.217.08:17:51.75#ibcon#about to read 4, iclass 37, count 2 2006.217.08:17:51.75#ibcon#read 4, iclass 37, count 2 2006.217.08:17:51.75#ibcon#about to read 5, iclass 37, count 2 2006.217.08:17:51.75#ibcon#read 5, iclass 37, count 2 2006.217.08:17:51.75#ibcon#about to read 6, iclass 37, count 2 2006.217.08:17:51.75#ibcon#read 6, iclass 37, count 2 2006.217.08:17:51.75#ibcon#end of sib2, iclass 37, count 2 2006.217.08:17:51.75#ibcon#*after write, iclass 37, count 2 2006.217.08:17:51.75#ibcon#*before return 0, iclass 37, count 2 2006.217.08:17:51.75#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.217.08:17:51.75#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.217.08:17:51.75#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.217.08:17:51.75#ibcon#ireg 7 cls_cnt 0 2006.217.08:17:51.75#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.217.08:17:51.87#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.217.08:17:51.87#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.217.08:17:51.87#ibcon#enter wrdev, iclass 37, count 0 2006.217.08:17:51.87#ibcon#first serial, iclass 37, count 0 2006.217.08:17:51.87#ibcon#enter sib2, iclass 37, count 0 2006.217.08:17:51.87#ibcon#flushed, iclass 37, count 0 2006.217.08:17:51.87#ibcon#about to write, iclass 37, count 0 2006.217.08:17:51.87#ibcon#wrote, iclass 37, count 0 2006.217.08:17:51.87#ibcon#about to read 3, iclass 37, count 0 2006.217.08:17:51.89#ibcon#read 3, iclass 37, count 0 2006.217.08:17:51.89#ibcon#about to read 4, iclass 37, count 0 2006.217.08:17:51.89#ibcon#read 4, iclass 37, count 0 2006.217.08:17:51.89#ibcon#about to read 5, iclass 37, count 0 2006.217.08:17:51.89#ibcon#read 5, iclass 37, count 0 2006.217.08:17:51.89#ibcon#about to read 6, iclass 37, count 0 2006.217.08:17:51.89#ibcon#read 6, iclass 37, count 0 2006.217.08:17:51.89#ibcon#end of sib2, iclass 37, count 0 2006.217.08:17:51.89#ibcon#*mode == 0, iclass 37, count 0 2006.217.08:17:51.89#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.217.08:17:51.89#ibcon#[27=USB\r\n] 2006.217.08:17:51.89#ibcon#*before write, iclass 37, count 0 2006.217.08:17:51.89#ibcon#enter sib2, iclass 37, count 0 2006.217.08:17:51.89#ibcon#flushed, iclass 37, count 0 2006.217.08:17:51.89#ibcon#about to write, iclass 37, count 0 2006.217.08:17:51.89#ibcon#wrote, iclass 37, count 0 2006.217.08:17:51.89#ibcon#about to read 3, iclass 37, count 0 2006.217.08:17:51.92#ibcon#read 3, iclass 37, count 0 2006.217.08:17:51.92#ibcon#about to read 4, iclass 37, count 0 2006.217.08:17:51.92#ibcon#read 4, iclass 37, count 0 2006.217.08:17:51.92#ibcon#about to read 5, iclass 37, count 0 2006.217.08:17:51.92#ibcon#read 5, iclass 37, count 0 2006.217.08:17:51.92#ibcon#about to read 6, iclass 37, count 0 2006.217.08:17:51.92#ibcon#read 6, iclass 37, count 0 2006.217.08:17:51.92#ibcon#end of sib2, iclass 37, count 0 2006.217.08:17:51.92#ibcon#*after write, iclass 37, count 0 2006.217.08:17:51.92#ibcon#*before return 0, iclass 37, count 0 2006.217.08:17:51.92#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.217.08:17:51.92#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.217.08:17:51.92#ibcon#about to clear, iclass 37 cls_cnt 0 2006.217.08:17:51.92#ibcon#cleared, iclass 37 cls_cnt 0 2006.217.08:17:51.92$vc4f8/vblo=5,744.99 2006.217.08:17:51.93#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.217.08:17:51.93#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.217.08:17:51.93#ibcon#ireg 17 cls_cnt 0 2006.217.08:17:51.93#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.217.08:17:51.93#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.217.08:17:51.93#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.217.08:17:51.93#ibcon#enter wrdev, iclass 39, count 0 2006.217.08:17:51.93#ibcon#first serial, iclass 39, count 0 2006.217.08:17:51.93#ibcon#enter sib2, iclass 39, count 0 2006.217.08:17:51.93#ibcon#flushed, iclass 39, count 0 2006.217.08:17:51.93#ibcon#about to write, iclass 39, count 0 2006.217.08:17:51.93#ibcon#wrote, iclass 39, count 0 2006.217.08:17:51.93#ibcon#about to read 3, iclass 39, count 0 2006.217.08:17:51.94#ibcon#read 3, iclass 39, count 0 2006.217.08:17:51.94#ibcon#about to read 4, iclass 39, count 0 2006.217.08:17:51.94#ibcon#read 4, iclass 39, count 0 2006.217.08:17:51.94#ibcon#about to read 5, iclass 39, count 0 2006.217.08:17:51.94#ibcon#read 5, iclass 39, count 0 2006.217.08:17:51.94#ibcon#about to read 6, iclass 39, count 0 2006.217.08:17:51.94#ibcon#read 6, iclass 39, count 0 2006.217.08:17:51.94#ibcon#end of sib2, iclass 39, count 0 2006.217.08:17:51.94#ibcon#*mode == 0, iclass 39, count 0 2006.217.08:17:51.94#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.217.08:17:51.94#ibcon#[28=FRQ=05,744.99\r\n] 2006.217.08:17:51.94#ibcon#*before write, iclass 39, count 0 2006.217.08:17:51.94#ibcon#enter sib2, iclass 39, count 0 2006.217.08:17:51.94#ibcon#flushed, iclass 39, count 0 2006.217.08:17:51.94#ibcon#about to write, iclass 39, count 0 2006.217.08:17:51.94#ibcon#wrote, iclass 39, count 0 2006.217.08:17:51.94#ibcon#about to read 3, iclass 39, count 0 2006.217.08:17:51.98#ibcon#read 3, iclass 39, count 0 2006.217.08:17:51.98#ibcon#about to read 4, iclass 39, count 0 2006.217.08:17:51.98#ibcon#read 4, iclass 39, count 0 2006.217.08:17:51.98#ibcon#about to read 5, iclass 39, count 0 2006.217.08:17:51.98#ibcon#read 5, iclass 39, count 0 2006.217.08:17:51.98#ibcon#about to read 6, iclass 39, count 0 2006.217.08:17:51.98#ibcon#read 6, iclass 39, count 0 2006.217.08:17:51.98#ibcon#end of sib2, iclass 39, count 0 2006.217.08:17:51.98#ibcon#*after write, iclass 39, count 0 2006.217.08:17:51.98#ibcon#*before return 0, iclass 39, count 0 2006.217.08:17:51.98#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.217.08:17:51.98#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.217.08:17:51.98#ibcon#about to clear, iclass 39 cls_cnt 0 2006.217.08:17:51.98#ibcon#cleared, iclass 39 cls_cnt 0 2006.217.08:17:51.98$vc4f8/vb=5,4 2006.217.08:17:51.99#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.217.08:17:51.99#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.217.08:17:51.99#ibcon#ireg 11 cls_cnt 2 2006.217.08:17:51.99#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.217.08:17:52.03#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.217.08:17:52.03#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.217.08:17:52.03#ibcon#enter wrdev, iclass 3, count 2 2006.217.08:17:52.03#ibcon#first serial, iclass 3, count 2 2006.217.08:17:52.03#ibcon#enter sib2, iclass 3, count 2 2006.217.08:17:52.03#ibcon#flushed, iclass 3, count 2 2006.217.08:17:52.03#ibcon#about to write, iclass 3, count 2 2006.217.08:17:52.03#ibcon#wrote, iclass 3, count 2 2006.217.08:17:52.03#ibcon#about to read 3, iclass 3, count 2 2006.217.08:17:52.05#ibcon#read 3, iclass 3, count 2 2006.217.08:17:52.05#ibcon#about to read 4, iclass 3, count 2 2006.217.08:17:52.05#ibcon#read 4, iclass 3, count 2 2006.217.08:17:52.05#ibcon#about to read 5, iclass 3, count 2 2006.217.08:17:52.05#ibcon#read 5, iclass 3, count 2 2006.217.08:17:52.05#ibcon#about to read 6, iclass 3, count 2 2006.217.08:17:52.05#ibcon#read 6, iclass 3, count 2 2006.217.08:17:52.05#ibcon#end of sib2, iclass 3, count 2 2006.217.08:17:52.05#ibcon#*mode == 0, iclass 3, count 2 2006.217.08:17:52.05#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.217.08:17:52.05#ibcon#[27=AT05-04\r\n] 2006.217.08:17:52.05#ibcon#*before write, iclass 3, count 2 2006.217.08:17:52.05#ibcon#enter sib2, iclass 3, count 2 2006.217.08:17:52.05#ibcon#flushed, iclass 3, count 2 2006.217.08:17:52.05#ibcon#about to write, iclass 3, count 2 2006.217.08:17:52.05#ibcon#wrote, iclass 3, count 2 2006.217.08:17:52.05#ibcon#about to read 3, iclass 3, count 2 2006.217.08:17:52.08#ibcon#read 3, iclass 3, count 2 2006.217.08:17:52.08#ibcon#about to read 4, iclass 3, count 2 2006.217.08:17:52.08#ibcon#read 4, iclass 3, count 2 2006.217.08:17:52.08#ibcon#about to read 5, iclass 3, count 2 2006.217.08:17:52.08#ibcon#read 5, iclass 3, count 2 2006.217.08:17:52.08#ibcon#about to read 6, iclass 3, count 2 2006.217.08:17:52.08#ibcon#read 6, iclass 3, count 2 2006.217.08:17:52.08#ibcon#end of sib2, iclass 3, count 2 2006.217.08:17:52.08#ibcon#*after write, iclass 3, count 2 2006.217.08:17:52.08#ibcon#*before return 0, iclass 3, count 2 2006.217.08:17:52.08#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.217.08:17:52.08#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.217.08:17:52.08#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.217.08:17:52.08#ibcon#ireg 7 cls_cnt 0 2006.217.08:17:52.08#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.217.08:17:52.20#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.217.08:17:52.20#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.217.08:17:52.20#ibcon#enter wrdev, iclass 3, count 0 2006.217.08:17:52.20#ibcon#first serial, iclass 3, count 0 2006.217.08:17:52.20#ibcon#enter sib2, iclass 3, count 0 2006.217.08:17:52.20#ibcon#flushed, iclass 3, count 0 2006.217.08:17:52.20#ibcon#about to write, iclass 3, count 0 2006.217.08:17:52.20#ibcon#wrote, iclass 3, count 0 2006.217.08:17:52.20#ibcon#about to read 3, iclass 3, count 0 2006.217.08:17:52.22#ibcon#read 3, iclass 3, count 0 2006.217.08:17:52.22#ibcon#about to read 4, iclass 3, count 0 2006.217.08:17:52.22#ibcon#read 4, iclass 3, count 0 2006.217.08:17:52.22#ibcon#about to read 5, iclass 3, count 0 2006.217.08:17:52.22#ibcon#read 5, iclass 3, count 0 2006.217.08:17:52.22#ibcon#about to read 6, iclass 3, count 0 2006.217.08:17:52.22#ibcon#read 6, iclass 3, count 0 2006.217.08:17:52.22#ibcon#end of sib2, iclass 3, count 0 2006.217.08:17:52.22#ibcon#*mode == 0, iclass 3, count 0 2006.217.08:17:52.22#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.217.08:17:52.22#ibcon#[27=USB\r\n] 2006.217.08:17:52.22#ibcon#*before write, iclass 3, count 0 2006.217.08:17:52.22#ibcon#enter sib2, iclass 3, count 0 2006.217.08:17:52.22#ibcon#flushed, iclass 3, count 0 2006.217.08:17:52.22#ibcon#about to write, iclass 3, count 0 2006.217.08:17:52.22#ibcon#wrote, iclass 3, count 0 2006.217.08:17:52.22#ibcon#about to read 3, iclass 3, count 0 2006.217.08:17:52.25#ibcon#read 3, iclass 3, count 0 2006.217.08:17:52.25#ibcon#about to read 4, iclass 3, count 0 2006.217.08:17:52.25#ibcon#read 4, iclass 3, count 0 2006.217.08:17:52.25#ibcon#about to read 5, iclass 3, count 0 2006.217.08:17:52.25#ibcon#read 5, iclass 3, count 0 2006.217.08:17:52.25#ibcon#about to read 6, iclass 3, count 0 2006.217.08:17:52.25#ibcon#read 6, iclass 3, count 0 2006.217.08:17:52.25#ibcon#end of sib2, iclass 3, count 0 2006.217.08:17:52.25#ibcon#*after write, iclass 3, count 0 2006.217.08:17:52.25#ibcon#*before return 0, iclass 3, count 0 2006.217.08:17:52.25#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.217.08:17:52.25#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.217.08:17:52.25#ibcon#about to clear, iclass 3 cls_cnt 0 2006.217.08:17:52.25#ibcon#cleared, iclass 3 cls_cnt 0 2006.217.08:17:52.25$vc4f8/vblo=6,752.99 2006.217.08:17:52.26#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.217.08:17:52.26#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.217.08:17:52.26#ibcon#ireg 17 cls_cnt 0 2006.217.08:17:52.26#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.217.08:17:52.26#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.217.08:17:52.26#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.217.08:17:52.26#ibcon#enter wrdev, iclass 5, count 0 2006.217.08:17:52.26#ibcon#first serial, iclass 5, count 0 2006.217.08:17:52.26#ibcon#enter sib2, iclass 5, count 0 2006.217.08:17:52.26#ibcon#flushed, iclass 5, count 0 2006.217.08:17:52.26#ibcon#about to write, iclass 5, count 0 2006.217.08:17:52.26#ibcon#wrote, iclass 5, count 0 2006.217.08:17:52.26#ibcon#about to read 3, iclass 5, count 0 2006.217.08:17:52.27#ibcon#read 3, iclass 5, count 0 2006.217.08:17:52.27#ibcon#about to read 4, iclass 5, count 0 2006.217.08:17:52.27#ibcon#read 4, iclass 5, count 0 2006.217.08:17:52.27#ibcon#about to read 5, iclass 5, count 0 2006.217.08:17:52.27#ibcon#read 5, iclass 5, count 0 2006.217.08:17:52.27#ibcon#about to read 6, iclass 5, count 0 2006.217.08:17:52.27#ibcon#read 6, iclass 5, count 0 2006.217.08:17:52.27#ibcon#end of sib2, iclass 5, count 0 2006.217.08:17:52.27#ibcon#*mode == 0, iclass 5, count 0 2006.217.08:17:52.27#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.217.08:17:52.27#ibcon#[28=FRQ=06,752.99\r\n] 2006.217.08:17:52.27#ibcon#*before write, iclass 5, count 0 2006.217.08:17:52.27#ibcon#enter sib2, iclass 5, count 0 2006.217.08:17:52.27#ibcon#flushed, iclass 5, count 0 2006.217.08:17:52.27#ibcon#about to write, iclass 5, count 0 2006.217.08:17:52.27#ibcon#wrote, iclass 5, count 0 2006.217.08:17:52.27#ibcon#about to read 3, iclass 5, count 0 2006.217.08:17:52.31#ibcon#read 3, iclass 5, count 0 2006.217.08:17:52.31#ibcon#about to read 4, iclass 5, count 0 2006.217.08:17:52.31#ibcon#read 4, iclass 5, count 0 2006.217.08:17:52.31#ibcon#about to read 5, iclass 5, count 0 2006.217.08:17:52.31#ibcon#read 5, iclass 5, count 0 2006.217.08:17:52.31#ibcon#about to read 6, iclass 5, count 0 2006.217.08:17:52.31#ibcon#read 6, iclass 5, count 0 2006.217.08:17:52.31#ibcon#end of sib2, iclass 5, count 0 2006.217.08:17:52.31#ibcon#*after write, iclass 5, count 0 2006.217.08:17:52.31#ibcon#*before return 0, iclass 5, count 0 2006.217.08:17:52.31#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.217.08:17:52.31#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.217.08:17:52.31#ibcon#about to clear, iclass 5 cls_cnt 0 2006.217.08:17:52.31#ibcon#cleared, iclass 5 cls_cnt 0 2006.217.08:17:52.31$vc4f8/vb=6,4 2006.217.08:17:52.32#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.217.08:17:52.32#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.217.08:17:52.32#ibcon#ireg 11 cls_cnt 2 2006.217.08:17:52.32#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.217.08:17:52.36#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.217.08:17:52.36#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.217.08:17:52.36#ibcon#enter wrdev, iclass 7, count 2 2006.217.08:17:52.36#ibcon#first serial, iclass 7, count 2 2006.217.08:17:52.36#ibcon#enter sib2, iclass 7, count 2 2006.217.08:17:52.36#ibcon#flushed, iclass 7, count 2 2006.217.08:17:52.36#ibcon#about to write, iclass 7, count 2 2006.217.08:17:52.36#ibcon#wrote, iclass 7, count 2 2006.217.08:17:52.36#ibcon#about to read 3, iclass 7, count 2 2006.217.08:17:52.38#ibcon#read 3, iclass 7, count 2 2006.217.08:17:52.38#ibcon#about to read 4, iclass 7, count 2 2006.217.08:17:52.38#ibcon#read 4, iclass 7, count 2 2006.217.08:17:52.38#ibcon#about to read 5, iclass 7, count 2 2006.217.08:17:52.38#ibcon#read 5, iclass 7, count 2 2006.217.08:17:52.38#ibcon#about to read 6, iclass 7, count 2 2006.217.08:17:52.38#ibcon#read 6, iclass 7, count 2 2006.217.08:17:52.38#ibcon#end of sib2, iclass 7, count 2 2006.217.08:17:52.38#ibcon#*mode == 0, iclass 7, count 2 2006.217.08:17:52.38#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.217.08:17:52.38#ibcon#[27=AT06-04\r\n] 2006.217.08:17:52.38#ibcon#*before write, iclass 7, count 2 2006.217.08:17:52.38#ibcon#enter sib2, iclass 7, count 2 2006.217.08:17:52.38#ibcon#flushed, iclass 7, count 2 2006.217.08:17:52.38#ibcon#about to write, iclass 7, count 2 2006.217.08:17:52.38#ibcon#wrote, iclass 7, count 2 2006.217.08:17:52.38#ibcon#about to read 3, iclass 7, count 2 2006.217.08:17:52.41#ibcon#read 3, iclass 7, count 2 2006.217.08:17:52.41#ibcon#about to read 4, iclass 7, count 2 2006.217.08:17:52.41#ibcon#read 4, iclass 7, count 2 2006.217.08:17:52.41#ibcon#about to read 5, iclass 7, count 2 2006.217.08:17:52.41#ibcon#read 5, iclass 7, count 2 2006.217.08:17:52.41#ibcon#about to read 6, iclass 7, count 2 2006.217.08:17:52.41#ibcon#read 6, iclass 7, count 2 2006.217.08:17:52.41#ibcon#end of sib2, iclass 7, count 2 2006.217.08:17:52.41#ibcon#*after write, iclass 7, count 2 2006.217.08:17:52.41#ibcon#*before return 0, iclass 7, count 2 2006.217.08:17:52.41#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.217.08:17:52.41#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.217.08:17:52.41#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.217.08:17:52.41#ibcon#ireg 7 cls_cnt 0 2006.217.08:17:52.41#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.217.08:17:52.49#abcon#<5=/05 3.8 6.9 30.54 651008.6\r\n> 2006.217.08:17:52.51#abcon#{5=INTERFACE CLEAR} 2006.217.08:17:52.53#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.217.08:17:52.53#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.217.08:17:52.53#ibcon#enter wrdev, iclass 7, count 0 2006.217.08:17:52.53#ibcon#first serial, iclass 7, count 0 2006.217.08:17:52.53#ibcon#enter sib2, iclass 7, count 0 2006.217.08:17:52.53#ibcon#flushed, iclass 7, count 0 2006.217.08:17:52.53#ibcon#about to write, iclass 7, count 0 2006.217.08:17:52.53#ibcon#wrote, iclass 7, count 0 2006.217.08:17:52.53#ibcon#about to read 3, iclass 7, count 0 2006.217.08:17:52.57#ibcon#read 3, iclass 7, count 0 2006.217.08:17:52.57#ibcon#about to read 4, iclass 7, count 0 2006.217.08:17:52.57#ibcon#read 4, iclass 7, count 0 2006.217.08:17:52.57#ibcon#about to read 5, iclass 7, count 0 2006.217.08:17:52.57#ibcon#read 5, iclass 7, count 0 2006.217.08:17:52.57#ibcon#about to read 6, iclass 7, count 0 2006.217.08:17:52.57#ibcon#read 6, iclass 7, count 0 2006.217.08:17:52.57#ibcon#end of sib2, iclass 7, count 0 2006.217.08:17:52.57#ibcon#*mode == 0, iclass 7, count 0 2006.217.08:17:52.57#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.217.08:17:52.57#ibcon#[27=USB\r\n] 2006.217.08:17:52.57#ibcon#*before write, iclass 7, count 0 2006.217.08:17:52.57#ibcon#enter sib2, iclass 7, count 0 2006.217.08:17:52.57#ibcon#flushed, iclass 7, count 0 2006.217.08:17:52.57#ibcon#about to write, iclass 7, count 0 2006.217.08:17:52.57#ibcon#wrote, iclass 7, count 0 2006.217.08:17:52.57#ibcon#about to read 3, iclass 7, count 0 2006.217.08:17:52.59#abcon#[5=S1D000X0/0*\r\n] 2006.217.08:17:52.59#ibcon#read 3, iclass 7, count 0 2006.217.08:17:52.59#ibcon#about to read 4, iclass 7, count 0 2006.217.08:17:52.59#ibcon#read 4, iclass 7, count 0 2006.217.08:17:52.59#ibcon#about to read 5, iclass 7, count 0 2006.217.08:17:52.59#ibcon#read 5, iclass 7, count 0 2006.217.08:17:52.59#ibcon#about to read 6, iclass 7, count 0 2006.217.08:17:52.59#ibcon#read 6, iclass 7, count 0 2006.217.08:17:52.59#ibcon#end of sib2, iclass 7, count 0 2006.217.08:17:52.59#ibcon#*after write, iclass 7, count 0 2006.217.08:17:52.59#ibcon#*before return 0, iclass 7, count 0 2006.217.08:17:52.59#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.217.08:17:52.59#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.217.08:17:52.59#ibcon#about to clear, iclass 7 cls_cnt 0 2006.217.08:17:52.59#ibcon#cleared, iclass 7 cls_cnt 0 2006.217.08:17:52.59$vc4f8/vabw=wide 2006.217.08:17:52.60#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.217.08:17:52.60#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.217.08:17:52.60#ibcon#ireg 8 cls_cnt 0 2006.217.08:17:52.60#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.217.08:17:52.60#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.217.08:17:52.60#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.217.08:17:52.60#ibcon#enter wrdev, iclass 15, count 0 2006.217.08:17:52.60#ibcon#first serial, iclass 15, count 0 2006.217.08:17:52.60#ibcon#enter sib2, iclass 15, count 0 2006.217.08:17:52.60#ibcon#flushed, iclass 15, count 0 2006.217.08:17:52.60#ibcon#about to write, iclass 15, count 0 2006.217.08:17:52.60#ibcon#wrote, iclass 15, count 0 2006.217.08:17:52.60#ibcon#about to read 3, iclass 15, count 0 2006.217.08:17:52.61#ibcon#read 3, iclass 15, count 0 2006.217.08:17:52.61#ibcon#about to read 4, iclass 15, count 0 2006.217.08:17:52.61#ibcon#read 4, iclass 15, count 0 2006.217.08:17:52.61#ibcon#about to read 5, iclass 15, count 0 2006.217.08:17:52.61#ibcon#read 5, iclass 15, count 0 2006.217.08:17:52.61#ibcon#about to read 6, iclass 15, count 0 2006.217.08:17:52.61#ibcon#read 6, iclass 15, count 0 2006.217.08:17:52.61#ibcon#end of sib2, iclass 15, count 0 2006.217.08:17:52.61#ibcon#*mode == 0, iclass 15, count 0 2006.217.08:17:52.61#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.217.08:17:52.61#ibcon#[25=BW32\r\n] 2006.217.08:17:52.61#ibcon#*before write, iclass 15, count 0 2006.217.08:17:52.61#ibcon#enter sib2, iclass 15, count 0 2006.217.08:17:52.61#ibcon#flushed, iclass 15, count 0 2006.217.08:17:52.61#ibcon#about to write, iclass 15, count 0 2006.217.08:17:52.61#ibcon#wrote, iclass 15, count 0 2006.217.08:17:52.61#ibcon#about to read 3, iclass 15, count 0 2006.217.08:17:52.65#ibcon#read 3, iclass 15, count 0 2006.217.08:17:52.65#ibcon#about to read 4, iclass 15, count 0 2006.217.08:17:52.65#ibcon#read 4, iclass 15, count 0 2006.217.08:17:52.65#ibcon#about to read 5, iclass 15, count 0 2006.217.08:17:52.65#ibcon#read 5, iclass 15, count 0 2006.217.08:17:52.65#ibcon#about to read 6, iclass 15, count 0 2006.217.08:17:52.65#ibcon#read 6, iclass 15, count 0 2006.217.08:17:52.65#ibcon#end of sib2, iclass 15, count 0 2006.217.08:17:52.65#ibcon#*after write, iclass 15, count 0 2006.217.08:17:52.65#ibcon#*before return 0, iclass 15, count 0 2006.217.08:17:52.65#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.217.08:17:52.65#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.217.08:17:52.65#ibcon#about to clear, iclass 15 cls_cnt 0 2006.217.08:17:52.65#ibcon#cleared, iclass 15 cls_cnt 0 2006.217.08:17:52.65$vc4f8/vbbw=wide 2006.217.08:17:52.65#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.217.08:17:52.65#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.217.08:17:52.65#ibcon#ireg 8 cls_cnt 0 2006.217.08:17:52.65#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.217.08:17:52.70#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.217.08:17:52.70#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.217.08:17:52.70#ibcon#enter wrdev, iclass 17, count 0 2006.217.08:17:52.70#ibcon#first serial, iclass 17, count 0 2006.217.08:17:52.70#ibcon#enter sib2, iclass 17, count 0 2006.217.08:17:52.70#ibcon#flushed, iclass 17, count 0 2006.217.08:17:52.70#ibcon#about to write, iclass 17, count 0 2006.217.08:17:52.70#ibcon#wrote, iclass 17, count 0 2006.217.08:17:52.70#ibcon#about to read 3, iclass 17, count 0 2006.217.08:17:52.72#ibcon#read 3, iclass 17, count 0 2006.217.08:17:52.72#ibcon#about to read 4, iclass 17, count 0 2006.217.08:17:52.72#ibcon#read 4, iclass 17, count 0 2006.217.08:17:52.72#ibcon#about to read 5, iclass 17, count 0 2006.217.08:17:52.72#ibcon#read 5, iclass 17, count 0 2006.217.08:17:52.72#ibcon#about to read 6, iclass 17, count 0 2006.217.08:17:52.72#ibcon#read 6, iclass 17, count 0 2006.217.08:17:52.72#ibcon#end of sib2, iclass 17, count 0 2006.217.08:17:52.72#ibcon#*mode == 0, iclass 17, count 0 2006.217.08:17:52.72#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.217.08:17:52.72#ibcon#[27=BW32\r\n] 2006.217.08:17:52.72#ibcon#*before write, iclass 17, count 0 2006.217.08:17:52.72#ibcon#enter sib2, iclass 17, count 0 2006.217.08:17:52.72#ibcon#flushed, iclass 17, count 0 2006.217.08:17:52.72#ibcon#about to write, iclass 17, count 0 2006.217.08:17:52.72#ibcon#wrote, iclass 17, count 0 2006.217.08:17:52.72#ibcon#about to read 3, iclass 17, count 0 2006.217.08:17:52.75#ibcon#read 3, iclass 17, count 0 2006.217.08:17:52.75#ibcon#about to read 4, iclass 17, count 0 2006.217.08:17:52.75#ibcon#read 4, iclass 17, count 0 2006.217.08:17:52.75#ibcon#about to read 5, iclass 17, count 0 2006.217.08:17:52.75#ibcon#read 5, iclass 17, count 0 2006.217.08:17:52.75#ibcon#about to read 6, iclass 17, count 0 2006.217.08:17:52.75#ibcon#read 6, iclass 17, count 0 2006.217.08:17:52.75#ibcon#end of sib2, iclass 17, count 0 2006.217.08:17:52.75#ibcon#*after write, iclass 17, count 0 2006.217.08:17:52.75#ibcon#*before return 0, iclass 17, count 0 2006.217.08:17:52.75#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.217.08:17:52.75#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.217.08:17:52.75#ibcon#about to clear, iclass 17 cls_cnt 0 2006.217.08:17:52.75#ibcon#cleared, iclass 17 cls_cnt 0 2006.217.08:17:52.76$4f8m12a/ifd4f 2006.217.08:17:52.76$ifd4f/lo= 2006.217.08:17:52.76$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.217.08:17:52.76$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.217.08:17:52.76$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.217.08:17:52.76$ifd4f/patch= 2006.217.08:17:52.76$ifd4f/patch=lo1,a1,a2,a3,a4 2006.217.08:17:52.76$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.217.08:17:52.76$ifd4f/patch=lo3,a5,a6,a7,a8 2006.217.08:17:52.76$4f8m12a/"form=m,16.000,1:2 2006.217.08:17:52.76$4f8m12a/"tpicd 2006.217.08:17:52.76$4f8m12a/echo=off 2006.217.08:17:52.76$4f8m12a/xlog=off 2006.217.08:17:52.76:!2006.217.08:18:30 2006.217.08:18:11.14#trakl#Source acquired 2006.217.08:18:11.15#flagr#flagr/antenna,acquired 2006.217.08:18:30.01:preob 2006.217.08:18:31.14/onsource/TRACKING 2006.217.08:18:31.15:!2006.217.08:18:40 2006.217.08:18:40.01:data_valid=on 2006.217.08:18:40.02:midob 2006.217.08:18:41.14/onsource/TRACKING 2006.217.08:18:41.15/wx/30.53,1008.6,64 2006.217.08:18:41.37/cable/+6.3873E-03 2006.217.08:18:42.46/va/01,05,usb,yes,33,35 2006.217.08:18:42.46/va/02,04,usb,yes,31,32 2006.217.08:18:42.46/va/03,04,usb,yes,29,29 2006.217.08:18:42.46/va/04,04,usb,yes,33,35 2006.217.08:18:42.46/va/05,07,usb,yes,35,37 2006.217.08:18:42.46/va/06,06,usb,yes,34,34 2006.217.08:18:42.46/va/07,06,usb,yes,34,34 2006.217.08:18:42.46/va/08,07,usb,yes,33,32 2006.217.08:18:42.69/valo/01,532.99,yes,locked 2006.217.08:18:42.69/valo/02,572.99,yes,locked 2006.217.08:18:42.69/valo/03,672.99,yes,locked 2006.217.08:18:42.69/valo/04,832.99,yes,locked 2006.217.08:18:42.69/valo/05,652.99,yes,locked 2006.217.08:18:42.69/valo/06,772.99,yes,locked 2006.217.08:18:42.69/valo/07,832.99,yes,locked 2006.217.08:18:42.69/valo/08,852.99,yes,locked 2006.217.08:18:43.78/vb/01,04,usb,yes,31,30 2006.217.08:18:43.78/vb/02,04,usb,yes,33,34 2006.217.08:18:43.78/vb/03,04,usb,yes,29,33 2006.217.08:18:43.78/vb/04,04,usb,yes,30,30 2006.217.08:18:43.78/vb/05,04,usb,yes,29,33 2006.217.08:18:43.78/vb/06,04,usb,yes,30,32 2006.217.08:18:43.78/vb/07,04,usb,yes,32,32 2006.217.08:18:43.78/vb/08,04,usb,yes,29,33 2006.217.08:18:44.01/vblo/01,632.99,yes,locked 2006.217.08:18:44.01/vblo/02,640.99,yes,locked 2006.217.08:18:44.01/vblo/03,656.99,yes,locked 2006.217.08:18:44.01/vblo/04,712.99,yes,locked 2006.217.08:18:44.01/vblo/05,744.99,yes,locked 2006.217.08:18:44.01/vblo/06,752.99,yes,locked 2006.217.08:18:44.01/vblo/07,734.99,yes,locked 2006.217.08:18:44.01/vblo/08,744.99,yes,locked 2006.217.08:18:44.16/vabw/8 2006.217.08:18:44.31/vbbw/8 2006.217.08:18:44.40/xfe/off,on,14.7 2006.217.08:18:44.77/ifatt/23,28,28,28 2006.217.08:18:45.07/fmout-gps/S +4.55E-07 2006.217.08:18:45.12:!2006.217.08:19:40 2006.217.08:19:40.00:data_valid=off 2006.217.08:19:40.01:postob 2006.217.08:19:40.13/cable/+6.3849E-03 2006.217.08:19:40.14/wx/30.51,1008.6,64 2006.217.08:19:41.07/fmout-gps/S +4.56E-07 2006.217.08:19:41.08:scan_name=217-0821,k06217,60 2006.217.08:19:41.08:source=3c418,203837.03,511912.7,2000.0,cw 2006.217.08:19:42.14#flagr#flagr/antenna,new-source 2006.217.08:19:42.15:checkk5 2006.217.08:19:42.52/chk_autoobs//k5ts1/ autoobs is running! 2006.217.08:19:42.90/chk_autoobs//k5ts2/ autoobs is running! 2006.217.08:19:43.28/chk_autoobs//k5ts3/ autoobs is running! 2006.217.08:19:43.65/chk_autoobs//k5ts4/ autoobs is running! 2006.217.08:19:44.02/chk_obsdata//k5ts1/T2170818??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.08:19:44.39/chk_obsdata//k5ts2/T2170818??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.08:19:44.76/chk_obsdata//k5ts3/T2170818??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.08:19:45.13/chk_obsdata//k5ts4/T2170818??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.08:19:45.82/k5log//k5ts1_log_newline 2006.217.08:19:46.52/k5log//k5ts2_log_newline 2006.217.08:19:47.22/k5log//k5ts3_log_newline 2006.217.08:19:47.90/k5log//k5ts4_log_newline 2006.217.08:19:47.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.217.08:19:47.93:4f8m12a=3 2006.217.08:19:47.93$4f8m12a/echo=on 2006.217.08:19:47.93$4f8m12a/pcalon 2006.217.08:19:47.93$pcalon/"no phase cal control is implemented here 2006.217.08:19:47.93$4f8m12a/"tpicd=stop 2006.217.08:19:47.93$4f8m12a/vc4f8 2006.217.08:19:47.93$vc4f8/valo=1,532.99 2006.217.08:19:47.93#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.217.08:19:47.93#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.217.08:19:47.93#ibcon#ireg 17 cls_cnt 0 2006.217.08:19:47.93#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.217.08:19:47.93#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.217.08:19:47.93#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.217.08:19:47.93#ibcon#enter wrdev, iclass 28, count 0 2006.217.08:19:47.93#ibcon#first serial, iclass 28, count 0 2006.217.08:19:47.93#ibcon#enter sib2, iclass 28, count 0 2006.217.08:19:47.93#ibcon#flushed, iclass 28, count 0 2006.217.08:19:47.93#ibcon#about to write, iclass 28, count 0 2006.217.08:19:47.93#ibcon#wrote, iclass 28, count 0 2006.217.08:19:47.93#ibcon#about to read 3, iclass 28, count 0 2006.217.08:19:47.94#ibcon#read 3, iclass 28, count 0 2006.217.08:19:47.94#ibcon#about to read 4, iclass 28, count 0 2006.217.08:19:47.94#ibcon#read 4, iclass 28, count 0 2006.217.08:19:47.94#ibcon#about to read 5, iclass 28, count 0 2006.217.08:19:47.94#ibcon#read 5, iclass 28, count 0 2006.217.08:19:47.94#ibcon#about to read 6, iclass 28, count 0 2006.217.08:19:47.94#ibcon#read 6, iclass 28, count 0 2006.217.08:19:47.94#ibcon#end of sib2, iclass 28, count 0 2006.217.08:19:47.94#ibcon#*mode == 0, iclass 28, count 0 2006.217.08:19:47.94#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.217.08:19:47.94#ibcon#[26=FRQ=01,532.99\r\n] 2006.217.08:19:47.94#ibcon#*before write, iclass 28, count 0 2006.217.08:19:47.94#ibcon#enter sib2, iclass 28, count 0 2006.217.08:19:47.94#ibcon#flushed, iclass 28, count 0 2006.217.08:19:47.94#ibcon#about to write, iclass 28, count 0 2006.217.08:19:47.94#ibcon#wrote, iclass 28, count 0 2006.217.08:19:47.94#ibcon#about to read 3, iclass 28, count 0 2006.217.08:19:47.99#ibcon#read 3, iclass 28, count 0 2006.217.08:19:47.99#ibcon#about to read 4, iclass 28, count 0 2006.217.08:19:47.99#ibcon#read 4, iclass 28, count 0 2006.217.08:19:47.99#ibcon#about to read 5, iclass 28, count 0 2006.217.08:19:47.99#ibcon#read 5, iclass 28, count 0 2006.217.08:19:47.99#ibcon#about to read 6, iclass 28, count 0 2006.217.08:19:47.99#ibcon#read 6, iclass 28, count 0 2006.217.08:19:47.99#ibcon#end of sib2, iclass 28, count 0 2006.217.08:19:47.99#ibcon#*after write, iclass 28, count 0 2006.217.08:19:47.99#ibcon#*before return 0, iclass 28, count 0 2006.217.08:19:47.99#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.217.08:19:47.99#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.217.08:19:47.99#ibcon#about to clear, iclass 28 cls_cnt 0 2006.217.08:19:47.99#ibcon#cleared, iclass 28 cls_cnt 0 2006.217.08:19:47.99$vc4f8/va=1,5 2006.217.08:19:47.99#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.217.08:19:47.99#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.217.08:19:47.99#ibcon#ireg 11 cls_cnt 2 2006.217.08:19:47.99#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.217.08:19:47.99#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.217.08:19:47.99#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.217.08:19:47.99#ibcon#enter wrdev, iclass 30, count 2 2006.217.08:19:47.99#ibcon#first serial, iclass 30, count 2 2006.217.08:19:47.99#ibcon#enter sib2, iclass 30, count 2 2006.217.08:19:47.99#ibcon#flushed, iclass 30, count 2 2006.217.08:19:47.99#ibcon#about to write, iclass 30, count 2 2006.217.08:19:47.99#ibcon#wrote, iclass 30, count 2 2006.217.08:19:47.99#ibcon#about to read 3, iclass 30, count 2 2006.217.08:19:48.01#ibcon#read 3, iclass 30, count 2 2006.217.08:19:48.01#ibcon#about to read 4, iclass 30, count 2 2006.217.08:19:48.01#ibcon#read 4, iclass 30, count 2 2006.217.08:19:48.01#ibcon#about to read 5, iclass 30, count 2 2006.217.08:19:48.01#ibcon#read 5, iclass 30, count 2 2006.217.08:19:48.01#ibcon#about to read 6, iclass 30, count 2 2006.217.08:19:48.01#ibcon#read 6, iclass 30, count 2 2006.217.08:19:48.01#ibcon#end of sib2, iclass 30, count 2 2006.217.08:19:48.01#ibcon#*mode == 0, iclass 30, count 2 2006.217.08:19:48.01#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.217.08:19:48.01#ibcon#[25=AT01-05\r\n] 2006.217.08:19:48.01#ibcon#*before write, iclass 30, count 2 2006.217.08:19:48.01#ibcon#enter sib2, iclass 30, count 2 2006.217.08:19:48.01#ibcon#flushed, iclass 30, count 2 2006.217.08:19:48.01#ibcon#about to write, iclass 30, count 2 2006.217.08:19:48.01#ibcon#wrote, iclass 30, count 2 2006.217.08:19:48.01#ibcon#about to read 3, iclass 30, count 2 2006.217.08:19:48.04#ibcon#read 3, iclass 30, count 2 2006.217.08:19:48.04#ibcon#about to read 4, iclass 30, count 2 2006.217.08:19:48.04#ibcon#read 4, iclass 30, count 2 2006.217.08:19:48.04#ibcon#about to read 5, iclass 30, count 2 2006.217.08:19:48.04#ibcon#read 5, iclass 30, count 2 2006.217.08:19:48.04#ibcon#about to read 6, iclass 30, count 2 2006.217.08:19:48.04#ibcon#read 6, iclass 30, count 2 2006.217.08:19:48.04#ibcon#end of sib2, iclass 30, count 2 2006.217.08:19:48.04#ibcon#*after write, iclass 30, count 2 2006.217.08:19:48.04#ibcon#*before return 0, iclass 30, count 2 2006.217.08:19:48.04#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.217.08:19:48.04#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.217.08:19:48.04#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.217.08:19:48.04#ibcon#ireg 7 cls_cnt 0 2006.217.08:19:48.04#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.217.08:19:48.16#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.217.08:19:48.16#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.217.08:19:48.16#ibcon#enter wrdev, iclass 30, count 0 2006.217.08:19:48.16#ibcon#first serial, iclass 30, count 0 2006.217.08:19:48.16#ibcon#enter sib2, iclass 30, count 0 2006.217.08:19:48.16#ibcon#flushed, iclass 30, count 0 2006.217.08:19:48.16#ibcon#about to write, iclass 30, count 0 2006.217.08:19:48.16#ibcon#wrote, iclass 30, count 0 2006.217.08:19:48.16#ibcon#about to read 3, iclass 30, count 0 2006.217.08:19:48.18#ibcon#read 3, iclass 30, count 0 2006.217.08:19:48.18#ibcon#about to read 4, iclass 30, count 0 2006.217.08:19:48.18#ibcon#read 4, iclass 30, count 0 2006.217.08:19:48.18#ibcon#about to read 5, iclass 30, count 0 2006.217.08:19:48.18#ibcon#read 5, iclass 30, count 0 2006.217.08:19:48.18#ibcon#about to read 6, iclass 30, count 0 2006.217.08:19:48.18#ibcon#read 6, iclass 30, count 0 2006.217.08:19:48.18#ibcon#end of sib2, iclass 30, count 0 2006.217.08:19:48.18#ibcon#*mode == 0, iclass 30, count 0 2006.217.08:19:48.18#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.217.08:19:48.18#ibcon#[25=USB\r\n] 2006.217.08:19:48.18#ibcon#*before write, iclass 30, count 0 2006.217.08:19:48.18#ibcon#enter sib2, iclass 30, count 0 2006.217.08:19:48.18#ibcon#flushed, iclass 30, count 0 2006.217.08:19:48.18#ibcon#about to write, iclass 30, count 0 2006.217.08:19:48.18#ibcon#wrote, iclass 30, count 0 2006.217.08:19:48.18#ibcon#about to read 3, iclass 30, count 0 2006.217.08:19:48.21#ibcon#read 3, iclass 30, count 0 2006.217.08:19:48.21#ibcon#about to read 4, iclass 30, count 0 2006.217.08:19:48.21#ibcon#read 4, iclass 30, count 0 2006.217.08:19:48.21#ibcon#about to read 5, iclass 30, count 0 2006.217.08:19:48.21#ibcon#read 5, iclass 30, count 0 2006.217.08:19:48.21#ibcon#about to read 6, iclass 30, count 0 2006.217.08:19:48.21#ibcon#read 6, iclass 30, count 0 2006.217.08:19:48.21#ibcon#end of sib2, iclass 30, count 0 2006.217.08:19:48.21#ibcon#*after write, iclass 30, count 0 2006.217.08:19:48.21#ibcon#*before return 0, iclass 30, count 0 2006.217.08:19:48.21#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.217.08:19:48.21#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.217.08:19:48.21#ibcon#about to clear, iclass 30 cls_cnt 0 2006.217.08:19:48.21#ibcon#cleared, iclass 30 cls_cnt 0 2006.217.08:19:48.21$vc4f8/valo=2,572.99 2006.217.08:19:48.21#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.217.08:19:48.21#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.217.08:19:48.21#ibcon#ireg 17 cls_cnt 0 2006.217.08:19:48.21#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.217.08:19:48.21#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.217.08:19:48.21#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.217.08:19:48.21#ibcon#enter wrdev, iclass 32, count 0 2006.217.08:19:48.21#ibcon#first serial, iclass 32, count 0 2006.217.08:19:48.21#ibcon#enter sib2, iclass 32, count 0 2006.217.08:19:48.21#ibcon#flushed, iclass 32, count 0 2006.217.08:19:48.21#ibcon#about to write, iclass 32, count 0 2006.217.08:19:48.21#ibcon#wrote, iclass 32, count 0 2006.217.08:19:48.21#ibcon#about to read 3, iclass 32, count 0 2006.217.08:19:48.24#ibcon#read 3, iclass 32, count 0 2006.217.08:19:48.24#ibcon#about to read 4, iclass 32, count 0 2006.217.08:19:48.24#ibcon#read 4, iclass 32, count 0 2006.217.08:19:48.24#ibcon#about to read 5, iclass 32, count 0 2006.217.08:19:48.24#ibcon#read 5, iclass 32, count 0 2006.217.08:19:48.24#ibcon#about to read 6, iclass 32, count 0 2006.217.08:19:48.24#ibcon#read 6, iclass 32, count 0 2006.217.08:19:48.24#ibcon#end of sib2, iclass 32, count 0 2006.217.08:19:48.24#ibcon#*mode == 0, iclass 32, count 0 2006.217.08:19:48.24#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.217.08:19:48.24#ibcon#[26=FRQ=02,572.99\r\n] 2006.217.08:19:48.24#ibcon#*before write, iclass 32, count 0 2006.217.08:19:48.24#ibcon#enter sib2, iclass 32, count 0 2006.217.08:19:48.24#ibcon#flushed, iclass 32, count 0 2006.217.08:19:48.24#ibcon#about to write, iclass 32, count 0 2006.217.08:19:48.24#ibcon#wrote, iclass 32, count 0 2006.217.08:19:48.24#ibcon#about to read 3, iclass 32, count 0 2006.217.08:19:48.28#ibcon#read 3, iclass 32, count 0 2006.217.08:19:48.28#ibcon#about to read 4, iclass 32, count 0 2006.217.08:19:48.28#ibcon#read 4, iclass 32, count 0 2006.217.08:19:48.28#ibcon#about to read 5, iclass 32, count 0 2006.217.08:19:48.28#ibcon#read 5, iclass 32, count 0 2006.217.08:19:48.28#ibcon#about to read 6, iclass 32, count 0 2006.217.08:19:48.28#ibcon#read 6, iclass 32, count 0 2006.217.08:19:48.28#ibcon#end of sib2, iclass 32, count 0 2006.217.08:19:48.28#ibcon#*after write, iclass 32, count 0 2006.217.08:19:48.28#ibcon#*before return 0, iclass 32, count 0 2006.217.08:19:48.28#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.217.08:19:48.28#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.217.08:19:48.28#ibcon#about to clear, iclass 32 cls_cnt 0 2006.217.08:19:48.28#ibcon#cleared, iclass 32 cls_cnt 0 2006.217.08:19:48.28$vc4f8/va=2,4 2006.217.08:19:48.28#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.217.08:19:48.28#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.217.08:19:48.28#ibcon#ireg 11 cls_cnt 2 2006.217.08:19:48.28#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.217.08:19:48.34#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.217.08:19:48.34#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.217.08:19:48.34#ibcon#enter wrdev, iclass 34, count 2 2006.217.08:19:48.34#ibcon#first serial, iclass 34, count 2 2006.217.08:19:48.34#ibcon#enter sib2, iclass 34, count 2 2006.217.08:19:48.34#ibcon#flushed, iclass 34, count 2 2006.217.08:19:48.34#ibcon#about to write, iclass 34, count 2 2006.217.08:19:48.34#ibcon#wrote, iclass 34, count 2 2006.217.08:19:48.34#ibcon#about to read 3, iclass 34, count 2 2006.217.08:19:48.35#ibcon#read 3, iclass 34, count 2 2006.217.08:19:48.35#ibcon#about to read 4, iclass 34, count 2 2006.217.08:19:48.35#ibcon#read 4, iclass 34, count 2 2006.217.08:19:48.35#ibcon#about to read 5, iclass 34, count 2 2006.217.08:19:48.35#ibcon#read 5, iclass 34, count 2 2006.217.08:19:48.35#ibcon#about to read 6, iclass 34, count 2 2006.217.08:19:48.35#ibcon#read 6, iclass 34, count 2 2006.217.08:19:48.35#ibcon#end of sib2, iclass 34, count 2 2006.217.08:19:48.35#ibcon#*mode == 0, iclass 34, count 2 2006.217.08:19:48.35#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.217.08:19:48.35#ibcon#[25=AT02-04\r\n] 2006.217.08:19:48.35#ibcon#*before write, iclass 34, count 2 2006.217.08:19:48.35#ibcon#enter sib2, iclass 34, count 2 2006.217.08:19:48.35#ibcon#flushed, iclass 34, count 2 2006.217.08:19:48.35#ibcon#about to write, iclass 34, count 2 2006.217.08:19:48.35#ibcon#wrote, iclass 34, count 2 2006.217.08:19:48.35#ibcon#about to read 3, iclass 34, count 2 2006.217.08:19:48.38#ibcon#read 3, iclass 34, count 2 2006.217.08:19:48.38#ibcon#about to read 4, iclass 34, count 2 2006.217.08:19:48.38#ibcon#read 4, iclass 34, count 2 2006.217.08:19:48.38#ibcon#about to read 5, iclass 34, count 2 2006.217.08:19:48.38#ibcon#read 5, iclass 34, count 2 2006.217.08:19:48.38#ibcon#about to read 6, iclass 34, count 2 2006.217.08:19:48.38#ibcon#read 6, iclass 34, count 2 2006.217.08:19:48.38#ibcon#end of sib2, iclass 34, count 2 2006.217.08:19:48.38#ibcon#*after write, iclass 34, count 2 2006.217.08:19:48.38#ibcon#*before return 0, iclass 34, count 2 2006.217.08:19:48.38#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.217.08:19:48.38#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.217.08:19:48.38#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.217.08:19:48.38#ibcon#ireg 7 cls_cnt 0 2006.217.08:19:48.38#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.217.08:19:48.50#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.217.08:19:48.50#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.217.08:19:48.50#ibcon#enter wrdev, iclass 34, count 0 2006.217.08:19:48.50#ibcon#first serial, iclass 34, count 0 2006.217.08:19:48.50#ibcon#enter sib2, iclass 34, count 0 2006.217.08:19:48.50#ibcon#flushed, iclass 34, count 0 2006.217.08:19:48.50#ibcon#about to write, iclass 34, count 0 2006.217.08:19:48.50#ibcon#wrote, iclass 34, count 0 2006.217.08:19:48.50#ibcon#about to read 3, iclass 34, count 0 2006.217.08:19:48.52#ibcon#read 3, iclass 34, count 0 2006.217.08:19:48.52#ibcon#about to read 4, iclass 34, count 0 2006.217.08:19:48.52#ibcon#read 4, iclass 34, count 0 2006.217.08:19:48.52#ibcon#about to read 5, iclass 34, count 0 2006.217.08:19:48.52#ibcon#read 5, iclass 34, count 0 2006.217.08:19:48.52#ibcon#about to read 6, iclass 34, count 0 2006.217.08:19:48.52#ibcon#read 6, iclass 34, count 0 2006.217.08:19:48.52#ibcon#end of sib2, iclass 34, count 0 2006.217.08:19:48.52#ibcon#*mode == 0, iclass 34, count 0 2006.217.08:19:48.52#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.217.08:19:48.52#ibcon#[25=USB\r\n] 2006.217.08:19:48.52#ibcon#*before write, iclass 34, count 0 2006.217.08:19:48.52#ibcon#enter sib2, iclass 34, count 0 2006.217.08:19:48.52#ibcon#flushed, iclass 34, count 0 2006.217.08:19:48.52#ibcon#about to write, iclass 34, count 0 2006.217.08:19:48.52#ibcon#wrote, iclass 34, count 0 2006.217.08:19:48.52#ibcon#about to read 3, iclass 34, count 0 2006.217.08:19:48.55#ibcon#read 3, iclass 34, count 0 2006.217.08:19:48.55#ibcon#about to read 4, iclass 34, count 0 2006.217.08:19:48.55#ibcon#read 4, iclass 34, count 0 2006.217.08:19:48.55#ibcon#about to read 5, iclass 34, count 0 2006.217.08:19:48.55#ibcon#read 5, iclass 34, count 0 2006.217.08:19:48.55#ibcon#about to read 6, iclass 34, count 0 2006.217.08:19:48.55#ibcon#read 6, iclass 34, count 0 2006.217.08:19:48.55#ibcon#end of sib2, iclass 34, count 0 2006.217.08:19:48.55#ibcon#*after write, iclass 34, count 0 2006.217.08:19:48.55#ibcon#*before return 0, iclass 34, count 0 2006.217.08:19:48.55#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.217.08:19:48.55#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.217.08:19:48.55#ibcon#about to clear, iclass 34 cls_cnt 0 2006.217.08:19:48.55#ibcon#cleared, iclass 34 cls_cnt 0 2006.217.08:19:48.55$vc4f8/valo=3,672.99 2006.217.08:19:48.55#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.217.08:19:48.55#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.217.08:19:48.55#ibcon#ireg 17 cls_cnt 0 2006.217.08:19:48.55#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.217.08:19:48.55#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.217.08:19:48.55#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.217.08:19:48.55#ibcon#enter wrdev, iclass 36, count 0 2006.217.08:19:48.55#ibcon#first serial, iclass 36, count 0 2006.217.08:19:48.55#ibcon#enter sib2, iclass 36, count 0 2006.217.08:19:48.55#ibcon#flushed, iclass 36, count 0 2006.217.08:19:48.55#ibcon#about to write, iclass 36, count 0 2006.217.08:19:48.55#ibcon#wrote, iclass 36, count 0 2006.217.08:19:48.55#ibcon#about to read 3, iclass 36, count 0 2006.217.08:19:48.58#ibcon#read 3, iclass 36, count 0 2006.217.08:19:48.58#ibcon#about to read 4, iclass 36, count 0 2006.217.08:19:48.58#ibcon#read 4, iclass 36, count 0 2006.217.08:19:48.58#ibcon#about to read 5, iclass 36, count 0 2006.217.08:19:48.58#ibcon#read 5, iclass 36, count 0 2006.217.08:19:48.58#ibcon#about to read 6, iclass 36, count 0 2006.217.08:19:48.58#ibcon#read 6, iclass 36, count 0 2006.217.08:19:48.58#ibcon#end of sib2, iclass 36, count 0 2006.217.08:19:48.58#ibcon#*mode == 0, iclass 36, count 0 2006.217.08:19:48.58#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.217.08:19:48.58#ibcon#[26=FRQ=03,672.99\r\n] 2006.217.08:19:48.58#ibcon#*before write, iclass 36, count 0 2006.217.08:19:48.58#ibcon#enter sib2, iclass 36, count 0 2006.217.08:19:48.58#ibcon#flushed, iclass 36, count 0 2006.217.08:19:48.58#ibcon#about to write, iclass 36, count 0 2006.217.08:19:48.58#ibcon#wrote, iclass 36, count 0 2006.217.08:19:48.58#ibcon#about to read 3, iclass 36, count 0 2006.217.08:19:48.62#ibcon#read 3, iclass 36, count 0 2006.217.08:19:48.62#ibcon#about to read 4, iclass 36, count 0 2006.217.08:19:48.62#ibcon#read 4, iclass 36, count 0 2006.217.08:19:48.62#ibcon#about to read 5, iclass 36, count 0 2006.217.08:19:48.62#ibcon#read 5, iclass 36, count 0 2006.217.08:19:48.62#ibcon#about to read 6, iclass 36, count 0 2006.217.08:19:48.62#ibcon#read 6, iclass 36, count 0 2006.217.08:19:48.62#ibcon#end of sib2, iclass 36, count 0 2006.217.08:19:48.62#ibcon#*after write, iclass 36, count 0 2006.217.08:19:48.62#ibcon#*before return 0, iclass 36, count 0 2006.217.08:19:48.62#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.217.08:19:48.62#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.217.08:19:48.62#ibcon#about to clear, iclass 36 cls_cnt 0 2006.217.08:19:48.62#ibcon#cleared, iclass 36 cls_cnt 0 2006.217.08:19:48.62$vc4f8/va=3,4 2006.217.08:19:48.62#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.217.08:19:48.62#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.217.08:19:48.62#ibcon#ireg 11 cls_cnt 2 2006.217.08:19:48.62#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.217.08:19:48.68#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.217.08:19:48.68#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.217.08:19:48.68#ibcon#enter wrdev, iclass 38, count 2 2006.217.08:19:48.68#ibcon#first serial, iclass 38, count 2 2006.217.08:19:48.68#ibcon#enter sib2, iclass 38, count 2 2006.217.08:19:48.68#ibcon#flushed, iclass 38, count 2 2006.217.08:19:48.68#ibcon#about to write, iclass 38, count 2 2006.217.08:19:48.68#ibcon#wrote, iclass 38, count 2 2006.217.08:19:48.68#ibcon#about to read 3, iclass 38, count 2 2006.217.08:19:48.69#ibcon#read 3, iclass 38, count 2 2006.217.08:19:48.69#ibcon#about to read 4, iclass 38, count 2 2006.217.08:19:48.69#ibcon#read 4, iclass 38, count 2 2006.217.08:19:48.69#ibcon#about to read 5, iclass 38, count 2 2006.217.08:19:48.69#ibcon#read 5, iclass 38, count 2 2006.217.08:19:48.69#ibcon#about to read 6, iclass 38, count 2 2006.217.08:19:48.69#ibcon#read 6, iclass 38, count 2 2006.217.08:19:48.69#ibcon#end of sib2, iclass 38, count 2 2006.217.08:19:48.69#ibcon#*mode == 0, iclass 38, count 2 2006.217.08:19:48.69#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.217.08:19:48.69#ibcon#[25=AT03-04\r\n] 2006.217.08:19:48.69#ibcon#*before write, iclass 38, count 2 2006.217.08:19:48.69#ibcon#enter sib2, iclass 38, count 2 2006.217.08:19:48.69#ibcon#flushed, iclass 38, count 2 2006.217.08:19:48.69#ibcon#about to write, iclass 38, count 2 2006.217.08:19:48.69#ibcon#wrote, iclass 38, count 2 2006.217.08:19:48.69#ibcon#about to read 3, iclass 38, count 2 2006.217.08:19:48.72#ibcon#read 3, iclass 38, count 2 2006.217.08:19:48.72#ibcon#about to read 4, iclass 38, count 2 2006.217.08:19:48.72#ibcon#read 4, iclass 38, count 2 2006.217.08:19:48.72#ibcon#about to read 5, iclass 38, count 2 2006.217.08:19:48.72#ibcon#read 5, iclass 38, count 2 2006.217.08:19:48.72#ibcon#about to read 6, iclass 38, count 2 2006.217.08:19:48.72#ibcon#read 6, iclass 38, count 2 2006.217.08:19:48.72#ibcon#end of sib2, iclass 38, count 2 2006.217.08:19:48.72#ibcon#*after write, iclass 38, count 2 2006.217.08:19:48.72#ibcon#*before return 0, iclass 38, count 2 2006.217.08:19:48.72#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.217.08:19:48.72#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.217.08:19:48.72#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.217.08:19:48.72#ibcon#ireg 7 cls_cnt 0 2006.217.08:19:48.72#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.217.08:19:48.84#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.217.08:19:48.84#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.217.08:19:48.84#ibcon#enter wrdev, iclass 38, count 0 2006.217.08:19:48.84#ibcon#first serial, iclass 38, count 0 2006.217.08:19:48.84#ibcon#enter sib2, iclass 38, count 0 2006.217.08:19:48.84#ibcon#flushed, iclass 38, count 0 2006.217.08:19:48.84#ibcon#about to write, iclass 38, count 0 2006.217.08:19:48.84#ibcon#wrote, iclass 38, count 0 2006.217.08:19:48.84#ibcon#about to read 3, iclass 38, count 0 2006.217.08:19:48.86#ibcon#read 3, iclass 38, count 0 2006.217.08:19:48.86#ibcon#about to read 4, iclass 38, count 0 2006.217.08:19:48.86#ibcon#read 4, iclass 38, count 0 2006.217.08:19:48.86#ibcon#about to read 5, iclass 38, count 0 2006.217.08:19:48.86#ibcon#read 5, iclass 38, count 0 2006.217.08:19:48.86#ibcon#about to read 6, iclass 38, count 0 2006.217.08:19:48.86#ibcon#read 6, iclass 38, count 0 2006.217.08:19:48.86#ibcon#end of sib2, iclass 38, count 0 2006.217.08:19:48.86#ibcon#*mode == 0, iclass 38, count 0 2006.217.08:19:48.86#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.217.08:19:48.86#ibcon#[25=USB\r\n] 2006.217.08:19:48.86#ibcon#*before write, iclass 38, count 0 2006.217.08:19:48.86#ibcon#enter sib2, iclass 38, count 0 2006.217.08:19:48.86#ibcon#flushed, iclass 38, count 0 2006.217.08:19:48.86#ibcon#about to write, iclass 38, count 0 2006.217.08:19:48.86#ibcon#wrote, iclass 38, count 0 2006.217.08:19:48.86#ibcon#about to read 3, iclass 38, count 0 2006.217.08:19:48.89#ibcon#read 3, iclass 38, count 0 2006.217.08:19:48.89#ibcon#about to read 4, iclass 38, count 0 2006.217.08:19:48.89#ibcon#read 4, iclass 38, count 0 2006.217.08:19:48.89#ibcon#about to read 5, iclass 38, count 0 2006.217.08:19:48.89#ibcon#read 5, iclass 38, count 0 2006.217.08:19:48.89#ibcon#about to read 6, iclass 38, count 0 2006.217.08:19:48.89#ibcon#read 6, iclass 38, count 0 2006.217.08:19:48.89#ibcon#end of sib2, iclass 38, count 0 2006.217.08:19:48.89#ibcon#*after write, iclass 38, count 0 2006.217.08:19:48.89#ibcon#*before return 0, iclass 38, count 0 2006.217.08:19:48.89#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.217.08:19:48.89#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.217.08:19:48.89#ibcon#about to clear, iclass 38 cls_cnt 0 2006.217.08:19:48.89#ibcon#cleared, iclass 38 cls_cnt 0 2006.217.08:19:48.89$vc4f8/valo=4,832.99 2006.217.08:19:48.89#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.217.08:19:48.89#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.217.08:19:48.89#ibcon#ireg 17 cls_cnt 0 2006.217.08:19:48.89#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.217.08:19:48.89#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.217.08:19:48.89#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.217.08:19:48.89#ibcon#enter wrdev, iclass 40, count 0 2006.217.08:19:48.89#ibcon#first serial, iclass 40, count 0 2006.217.08:19:48.89#ibcon#enter sib2, iclass 40, count 0 2006.217.08:19:48.89#ibcon#flushed, iclass 40, count 0 2006.217.08:19:48.89#ibcon#about to write, iclass 40, count 0 2006.217.08:19:48.89#ibcon#wrote, iclass 40, count 0 2006.217.08:19:48.89#ibcon#about to read 3, iclass 40, count 0 2006.217.08:19:48.92#ibcon#read 3, iclass 40, count 0 2006.217.08:19:48.92#ibcon#about to read 4, iclass 40, count 0 2006.217.08:19:48.92#ibcon#read 4, iclass 40, count 0 2006.217.08:19:48.92#ibcon#about to read 5, iclass 40, count 0 2006.217.08:19:48.92#ibcon#read 5, iclass 40, count 0 2006.217.08:19:48.92#ibcon#about to read 6, iclass 40, count 0 2006.217.08:19:48.92#ibcon#read 6, iclass 40, count 0 2006.217.08:19:48.92#ibcon#end of sib2, iclass 40, count 0 2006.217.08:19:48.92#ibcon#*mode == 0, iclass 40, count 0 2006.217.08:19:48.92#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.217.08:19:48.92#ibcon#[26=FRQ=04,832.99\r\n] 2006.217.08:19:48.92#ibcon#*before write, iclass 40, count 0 2006.217.08:19:48.92#ibcon#enter sib2, iclass 40, count 0 2006.217.08:19:48.92#ibcon#flushed, iclass 40, count 0 2006.217.08:19:48.92#ibcon#about to write, iclass 40, count 0 2006.217.08:19:48.92#ibcon#wrote, iclass 40, count 0 2006.217.08:19:48.92#ibcon#about to read 3, iclass 40, count 0 2006.217.08:19:48.96#ibcon#read 3, iclass 40, count 0 2006.217.08:19:48.96#ibcon#about to read 4, iclass 40, count 0 2006.217.08:19:48.96#ibcon#read 4, iclass 40, count 0 2006.217.08:19:48.96#ibcon#about to read 5, iclass 40, count 0 2006.217.08:19:48.96#ibcon#read 5, iclass 40, count 0 2006.217.08:19:48.96#ibcon#about to read 6, iclass 40, count 0 2006.217.08:19:48.96#ibcon#read 6, iclass 40, count 0 2006.217.08:19:48.96#ibcon#end of sib2, iclass 40, count 0 2006.217.08:19:48.96#ibcon#*after write, iclass 40, count 0 2006.217.08:19:48.96#ibcon#*before return 0, iclass 40, count 0 2006.217.08:19:48.96#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.217.08:19:48.96#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.217.08:19:48.96#ibcon#about to clear, iclass 40 cls_cnt 0 2006.217.08:19:48.96#ibcon#cleared, iclass 40 cls_cnt 0 2006.217.08:19:48.96$vc4f8/va=4,4 2006.217.08:19:48.96#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.217.08:19:48.96#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.217.08:19:48.96#ibcon#ireg 11 cls_cnt 2 2006.217.08:19:48.96#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.217.08:19:49.01#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.217.08:19:49.01#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.217.08:19:49.01#ibcon#enter wrdev, iclass 4, count 2 2006.217.08:19:49.01#ibcon#first serial, iclass 4, count 2 2006.217.08:19:49.01#ibcon#enter sib2, iclass 4, count 2 2006.217.08:19:49.01#ibcon#flushed, iclass 4, count 2 2006.217.08:19:49.01#ibcon#about to write, iclass 4, count 2 2006.217.08:19:49.01#ibcon#wrote, iclass 4, count 2 2006.217.08:19:49.01#ibcon#about to read 3, iclass 4, count 2 2006.217.08:19:49.03#ibcon#read 3, iclass 4, count 2 2006.217.08:19:49.03#ibcon#about to read 4, iclass 4, count 2 2006.217.08:19:49.03#ibcon#read 4, iclass 4, count 2 2006.217.08:19:49.03#ibcon#about to read 5, iclass 4, count 2 2006.217.08:19:49.03#ibcon#read 5, iclass 4, count 2 2006.217.08:19:49.03#ibcon#about to read 6, iclass 4, count 2 2006.217.08:19:49.03#ibcon#read 6, iclass 4, count 2 2006.217.08:19:49.03#ibcon#end of sib2, iclass 4, count 2 2006.217.08:19:49.03#ibcon#*mode == 0, iclass 4, count 2 2006.217.08:19:49.03#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.217.08:19:49.03#ibcon#[25=AT04-04\r\n] 2006.217.08:19:49.03#ibcon#*before write, iclass 4, count 2 2006.217.08:19:49.03#ibcon#enter sib2, iclass 4, count 2 2006.217.08:19:49.03#ibcon#flushed, iclass 4, count 2 2006.217.08:19:49.03#ibcon#about to write, iclass 4, count 2 2006.217.08:19:49.03#ibcon#wrote, iclass 4, count 2 2006.217.08:19:49.03#ibcon#about to read 3, iclass 4, count 2 2006.217.08:19:49.06#ibcon#read 3, iclass 4, count 2 2006.217.08:19:49.06#ibcon#about to read 4, iclass 4, count 2 2006.217.08:19:49.06#ibcon#read 4, iclass 4, count 2 2006.217.08:19:49.06#ibcon#about to read 5, iclass 4, count 2 2006.217.08:19:49.06#ibcon#read 5, iclass 4, count 2 2006.217.08:19:49.06#ibcon#about to read 6, iclass 4, count 2 2006.217.08:19:49.06#ibcon#read 6, iclass 4, count 2 2006.217.08:19:49.06#ibcon#end of sib2, iclass 4, count 2 2006.217.08:19:49.06#ibcon#*after write, iclass 4, count 2 2006.217.08:19:49.06#ibcon#*before return 0, iclass 4, count 2 2006.217.08:19:49.06#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.217.08:19:49.06#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.217.08:19:49.06#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.217.08:19:49.06#ibcon#ireg 7 cls_cnt 0 2006.217.08:19:49.06#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.217.08:19:49.18#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.217.08:19:49.18#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.217.08:19:49.18#ibcon#enter wrdev, iclass 4, count 0 2006.217.08:19:49.18#ibcon#first serial, iclass 4, count 0 2006.217.08:19:49.18#ibcon#enter sib2, iclass 4, count 0 2006.217.08:19:49.18#ibcon#flushed, iclass 4, count 0 2006.217.08:19:49.18#ibcon#about to write, iclass 4, count 0 2006.217.08:19:49.18#ibcon#wrote, iclass 4, count 0 2006.217.08:19:49.18#ibcon#about to read 3, iclass 4, count 0 2006.217.08:19:49.20#ibcon#read 3, iclass 4, count 0 2006.217.08:19:49.20#ibcon#about to read 4, iclass 4, count 0 2006.217.08:19:49.20#ibcon#read 4, iclass 4, count 0 2006.217.08:19:49.20#ibcon#about to read 5, iclass 4, count 0 2006.217.08:19:49.20#ibcon#read 5, iclass 4, count 0 2006.217.08:19:49.20#ibcon#about to read 6, iclass 4, count 0 2006.217.08:19:49.20#ibcon#read 6, iclass 4, count 0 2006.217.08:19:49.20#ibcon#end of sib2, iclass 4, count 0 2006.217.08:19:49.20#ibcon#*mode == 0, iclass 4, count 0 2006.217.08:19:49.20#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.217.08:19:49.20#ibcon#[25=USB\r\n] 2006.217.08:19:49.20#ibcon#*before write, iclass 4, count 0 2006.217.08:19:49.20#ibcon#enter sib2, iclass 4, count 0 2006.217.08:19:49.20#ibcon#flushed, iclass 4, count 0 2006.217.08:19:49.20#ibcon#about to write, iclass 4, count 0 2006.217.08:19:49.20#ibcon#wrote, iclass 4, count 0 2006.217.08:19:49.20#ibcon#about to read 3, iclass 4, count 0 2006.217.08:19:49.23#ibcon#read 3, iclass 4, count 0 2006.217.08:19:49.23#ibcon#about to read 4, iclass 4, count 0 2006.217.08:19:49.23#ibcon#read 4, iclass 4, count 0 2006.217.08:19:49.23#ibcon#about to read 5, iclass 4, count 0 2006.217.08:19:49.23#ibcon#read 5, iclass 4, count 0 2006.217.08:19:49.23#ibcon#about to read 6, iclass 4, count 0 2006.217.08:19:49.23#ibcon#read 6, iclass 4, count 0 2006.217.08:19:49.23#ibcon#end of sib2, iclass 4, count 0 2006.217.08:19:49.23#ibcon#*after write, iclass 4, count 0 2006.217.08:19:49.23#ibcon#*before return 0, iclass 4, count 0 2006.217.08:19:49.23#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.217.08:19:49.23#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.217.08:19:49.23#ibcon#about to clear, iclass 4 cls_cnt 0 2006.217.08:19:49.23#ibcon#cleared, iclass 4 cls_cnt 0 2006.217.08:19:49.23$vc4f8/valo=5,652.99 2006.217.08:19:49.23#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.217.08:19:49.23#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.217.08:19:49.23#ibcon#ireg 17 cls_cnt 0 2006.217.08:19:49.23#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.217.08:19:49.23#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.217.08:19:49.23#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.217.08:19:49.23#ibcon#enter wrdev, iclass 6, count 0 2006.217.08:19:49.23#ibcon#first serial, iclass 6, count 0 2006.217.08:19:49.23#ibcon#enter sib2, iclass 6, count 0 2006.217.08:19:49.23#ibcon#flushed, iclass 6, count 0 2006.217.08:19:49.23#ibcon#about to write, iclass 6, count 0 2006.217.08:19:49.23#ibcon#wrote, iclass 6, count 0 2006.217.08:19:49.23#ibcon#about to read 3, iclass 6, count 0 2006.217.08:19:49.25#ibcon#read 3, iclass 6, count 0 2006.217.08:19:49.25#ibcon#about to read 4, iclass 6, count 0 2006.217.08:19:49.25#ibcon#read 4, iclass 6, count 0 2006.217.08:19:49.25#ibcon#about to read 5, iclass 6, count 0 2006.217.08:19:49.25#ibcon#read 5, iclass 6, count 0 2006.217.08:19:49.25#ibcon#about to read 6, iclass 6, count 0 2006.217.08:19:49.25#ibcon#read 6, iclass 6, count 0 2006.217.08:19:49.25#ibcon#end of sib2, iclass 6, count 0 2006.217.08:19:49.25#ibcon#*mode == 0, iclass 6, count 0 2006.217.08:19:49.25#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.217.08:19:49.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.217.08:19:49.25#ibcon#*before write, iclass 6, count 0 2006.217.08:19:49.25#ibcon#enter sib2, iclass 6, count 0 2006.217.08:19:49.25#ibcon#flushed, iclass 6, count 0 2006.217.08:19:49.25#ibcon#about to write, iclass 6, count 0 2006.217.08:19:49.25#ibcon#wrote, iclass 6, count 0 2006.217.08:19:49.25#ibcon#about to read 3, iclass 6, count 0 2006.217.08:19:49.29#ibcon#read 3, iclass 6, count 0 2006.217.08:19:49.29#ibcon#about to read 4, iclass 6, count 0 2006.217.08:19:49.29#ibcon#read 4, iclass 6, count 0 2006.217.08:19:49.29#ibcon#about to read 5, iclass 6, count 0 2006.217.08:19:49.29#ibcon#read 5, iclass 6, count 0 2006.217.08:19:49.29#ibcon#about to read 6, iclass 6, count 0 2006.217.08:19:49.29#ibcon#read 6, iclass 6, count 0 2006.217.08:19:49.29#ibcon#end of sib2, iclass 6, count 0 2006.217.08:19:49.29#ibcon#*after write, iclass 6, count 0 2006.217.08:19:49.29#ibcon#*before return 0, iclass 6, count 0 2006.217.08:19:49.29#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.217.08:19:49.29#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.217.08:19:49.29#ibcon#about to clear, iclass 6 cls_cnt 0 2006.217.08:19:49.29#ibcon#cleared, iclass 6 cls_cnt 0 2006.217.08:19:49.29$vc4f8/va=5,7 2006.217.08:19:49.29#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.217.08:19:49.29#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.217.08:19:49.29#ibcon#ireg 11 cls_cnt 2 2006.217.08:19:49.29#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.217.08:19:49.35#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.217.08:19:49.35#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.217.08:19:49.35#ibcon#enter wrdev, iclass 10, count 2 2006.217.08:19:49.35#ibcon#first serial, iclass 10, count 2 2006.217.08:19:49.35#ibcon#enter sib2, iclass 10, count 2 2006.217.08:19:49.35#ibcon#flushed, iclass 10, count 2 2006.217.08:19:49.35#ibcon#about to write, iclass 10, count 2 2006.217.08:19:49.35#ibcon#wrote, iclass 10, count 2 2006.217.08:19:49.35#ibcon#about to read 3, iclass 10, count 2 2006.217.08:19:49.37#ibcon#read 3, iclass 10, count 2 2006.217.08:19:49.37#ibcon#about to read 4, iclass 10, count 2 2006.217.08:19:49.37#ibcon#read 4, iclass 10, count 2 2006.217.08:19:49.37#ibcon#about to read 5, iclass 10, count 2 2006.217.08:19:49.37#ibcon#read 5, iclass 10, count 2 2006.217.08:19:49.37#ibcon#about to read 6, iclass 10, count 2 2006.217.08:19:49.37#ibcon#read 6, iclass 10, count 2 2006.217.08:19:49.37#ibcon#end of sib2, iclass 10, count 2 2006.217.08:19:49.37#ibcon#*mode == 0, iclass 10, count 2 2006.217.08:19:49.37#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.217.08:19:49.37#ibcon#[25=AT05-07\r\n] 2006.217.08:19:49.37#ibcon#*before write, iclass 10, count 2 2006.217.08:19:49.37#ibcon#enter sib2, iclass 10, count 2 2006.217.08:19:49.37#ibcon#flushed, iclass 10, count 2 2006.217.08:19:49.37#ibcon#about to write, iclass 10, count 2 2006.217.08:19:49.37#ibcon#wrote, iclass 10, count 2 2006.217.08:19:49.37#ibcon#about to read 3, iclass 10, count 2 2006.217.08:19:49.40#ibcon#read 3, iclass 10, count 2 2006.217.08:19:49.40#ibcon#about to read 4, iclass 10, count 2 2006.217.08:19:49.40#ibcon#read 4, iclass 10, count 2 2006.217.08:19:49.40#ibcon#about to read 5, iclass 10, count 2 2006.217.08:19:49.40#ibcon#read 5, iclass 10, count 2 2006.217.08:19:49.40#ibcon#about to read 6, iclass 10, count 2 2006.217.08:19:49.40#ibcon#read 6, iclass 10, count 2 2006.217.08:19:49.40#ibcon#end of sib2, iclass 10, count 2 2006.217.08:19:49.40#ibcon#*after write, iclass 10, count 2 2006.217.08:19:49.40#ibcon#*before return 0, iclass 10, count 2 2006.217.08:19:49.40#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.217.08:19:49.40#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.217.08:19:49.40#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.217.08:19:49.40#ibcon#ireg 7 cls_cnt 0 2006.217.08:19:49.40#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.217.08:19:49.52#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.217.08:19:49.52#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.217.08:19:49.52#ibcon#enter wrdev, iclass 10, count 0 2006.217.08:19:49.52#ibcon#first serial, iclass 10, count 0 2006.217.08:19:49.52#ibcon#enter sib2, iclass 10, count 0 2006.217.08:19:49.52#ibcon#flushed, iclass 10, count 0 2006.217.08:19:49.52#ibcon#about to write, iclass 10, count 0 2006.217.08:19:49.52#ibcon#wrote, iclass 10, count 0 2006.217.08:19:49.52#ibcon#about to read 3, iclass 10, count 0 2006.217.08:19:49.54#ibcon#read 3, iclass 10, count 0 2006.217.08:19:49.54#ibcon#about to read 4, iclass 10, count 0 2006.217.08:19:49.54#ibcon#read 4, iclass 10, count 0 2006.217.08:19:49.54#ibcon#about to read 5, iclass 10, count 0 2006.217.08:19:49.54#ibcon#read 5, iclass 10, count 0 2006.217.08:19:49.54#ibcon#about to read 6, iclass 10, count 0 2006.217.08:19:49.54#ibcon#read 6, iclass 10, count 0 2006.217.08:19:49.54#ibcon#end of sib2, iclass 10, count 0 2006.217.08:19:49.54#ibcon#*mode == 0, iclass 10, count 0 2006.217.08:19:49.54#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.217.08:19:49.54#ibcon#[25=USB\r\n] 2006.217.08:19:49.54#ibcon#*before write, iclass 10, count 0 2006.217.08:19:49.54#ibcon#enter sib2, iclass 10, count 0 2006.217.08:19:49.54#ibcon#flushed, iclass 10, count 0 2006.217.08:19:49.54#ibcon#about to write, iclass 10, count 0 2006.217.08:19:49.54#ibcon#wrote, iclass 10, count 0 2006.217.08:19:49.54#ibcon#about to read 3, iclass 10, count 0 2006.217.08:19:49.57#ibcon#read 3, iclass 10, count 0 2006.217.08:19:49.57#ibcon#about to read 4, iclass 10, count 0 2006.217.08:19:49.57#ibcon#read 4, iclass 10, count 0 2006.217.08:19:49.57#ibcon#about to read 5, iclass 10, count 0 2006.217.08:19:49.57#ibcon#read 5, iclass 10, count 0 2006.217.08:19:49.57#ibcon#about to read 6, iclass 10, count 0 2006.217.08:19:49.57#ibcon#read 6, iclass 10, count 0 2006.217.08:19:49.57#ibcon#end of sib2, iclass 10, count 0 2006.217.08:19:49.57#ibcon#*after write, iclass 10, count 0 2006.217.08:19:49.57#ibcon#*before return 0, iclass 10, count 0 2006.217.08:19:49.57#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.217.08:19:49.57#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.217.08:19:49.57#ibcon#about to clear, iclass 10 cls_cnt 0 2006.217.08:19:49.57#ibcon#cleared, iclass 10 cls_cnt 0 2006.217.08:19:49.57$vc4f8/valo=6,772.99 2006.217.08:19:49.57#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.217.08:19:49.57#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.217.08:19:49.57#ibcon#ireg 17 cls_cnt 0 2006.217.08:19:49.57#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.217.08:19:49.57#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.217.08:19:49.57#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.217.08:19:49.57#ibcon#enter wrdev, iclass 12, count 0 2006.217.08:19:49.57#ibcon#first serial, iclass 12, count 0 2006.217.08:19:49.57#ibcon#enter sib2, iclass 12, count 0 2006.217.08:19:49.57#ibcon#flushed, iclass 12, count 0 2006.217.08:19:49.57#ibcon#about to write, iclass 12, count 0 2006.217.08:19:49.57#ibcon#wrote, iclass 12, count 0 2006.217.08:19:49.57#ibcon#about to read 3, iclass 12, count 0 2006.217.08:19:49.60#ibcon#read 3, iclass 12, count 0 2006.217.08:19:49.60#ibcon#about to read 4, iclass 12, count 0 2006.217.08:19:49.60#ibcon#read 4, iclass 12, count 0 2006.217.08:19:49.60#ibcon#about to read 5, iclass 12, count 0 2006.217.08:19:49.60#ibcon#read 5, iclass 12, count 0 2006.217.08:19:49.60#ibcon#about to read 6, iclass 12, count 0 2006.217.08:19:49.60#ibcon#read 6, iclass 12, count 0 2006.217.08:19:49.60#ibcon#end of sib2, iclass 12, count 0 2006.217.08:19:49.60#ibcon#*mode == 0, iclass 12, count 0 2006.217.08:19:49.60#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.217.08:19:49.60#ibcon#[26=FRQ=06,772.99\r\n] 2006.217.08:19:49.60#ibcon#*before write, iclass 12, count 0 2006.217.08:19:49.60#ibcon#enter sib2, iclass 12, count 0 2006.217.08:19:49.60#ibcon#flushed, iclass 12, count 0 2006.217.08:19:49.60#ibcon#about to write, iclass 12, count 0 2006.217.08:19:49.60#ibcon#wrote, iclass 12, count 0 2006.217.08:19:49.60#ibcon#about to read 3, iclass 12, count 0 2006.217.08:19:49.64#ibcon#read 3, iclass 12, count 0 2006.217.08:19:49.64#ibcon#about to read 4, iclass 12, count 0 2006.217.08:19:49.64#ibcon#read 4, iclass 12, count 0 2006.217.08:19:49.64#ibcon#about to read 5, iclass 12, count 0 2006.217.08:19:49.64#ibcon#read 5, iclass 12, count 0 2006.217.08:19:49.64#ibcon#about to read 6, iclass 12, count 0 2006.217.08:19:49.64#ibcon#read 6, iclass 12, count 0 2006.217.08:19:49.64#ibcon#end of sib2, iclass 12, count 0 2006.217.08:19:49.64#ibcon#*after write, iclass 12, count 0 2006.217.08:19:49.64#ibcon#*before return 0, iclass 12, count 0 2006.217.08:19:49.64#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.217.08:19:49.64#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.217.08:19:49.64#ibcon#about to clear, iclass 12 cls_cnt 0 2006.217.08:19:49.64#ibcon#cleared, iclass 12 cls_cnt 0 2006.217.08:19:49.64$vc4f8/va=6,6 2006.217.08:19:49.64#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.217.08:19:49.64#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.217.08:19:49.64#ibcon#ireg 11 cls_cnt 2 2006.217.08:19:49.64#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.217.08:19:49.70#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.217.08:19:49.70#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.217.08:19:49.70#ibcon#enter wrdev, iclass 14, count 2 2006.217.08:19:49.70#ibcon#first serial, iclass 14, count 2 2006.217.08:19:49.70#ibcon#enter sib2, iclass 14, count 2 2006.217.08:19:49.70#ibcon#flushed, iclass 14, count 2 2006.217.08:19:49.70#ibcon#about to write, iclass 14, count 2 2006.217.08:19:49.70#ibcon#wrote, iclass 14, count 2 2006.217.08:19:49.70#ibcon#about to read 3, iclass 14, count 2 2006.217.08:19:49.71#ibcon#read 3, iclass 14, count 2 2006.217.08:19:49.71#ibcon#about to read 4, iclass 14, count 2 2006.217.08:19:49.71#ibcon#read 4, iclass 14, count 2 2006.217.08:19:49.71#ibcon#about to read 5, iclass 14, count 2 2006.217.08:19:49.71#ibcon#read 5, iclass 14, count 2 2006.217.08:19:49.71#ibcon#about to read 6, iclass 14, count 2 2006.217.08:19:49.71#ibcon#read 6, iclass 14, count 2 2006.217.08:19:49.71#ibcon#end of sib2, iclass 14, count 2 2006.217.08:19:49.71#ibcon#*mode == 0, iclass 14, count 2 2006.217.08:19:49.71#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.217.08:19:49.71#ibcon#[25=AT06-06\r\n] 2006.217.08:19:49.71#ibcon#*before write, iclass 14, count 2 2006.217.08:19:49.71#ibcon#enter sib2, iclass 14, count 2 2006.217.08:19:49.71#ibcon#flushed, iclass 14, count 2 2006.217.08:19:49.71#ibcon#about to write, iclass 14, count 2 2006.217.08:19:49.71#ibcon#wrote, iclass 14, count 2 2006.217.08:19:49.71#ibcon#about to read 3, iclass 14, count 2 2006.217.08:19:49.74#ibcon#read 3, iclass 14, count 2 2006.217.08:19:49.74#ibcon#about to read 4, iclass 14, count 2 2006.217.08:19:49.74#ibcon#read 4, iclass 14, count 2 2006.217.08:19:49.74#ibcon#about to read 5, iclass 14, count 2 2006.217.08:19:49.74#ibcon#read 5, iclass 14, count 2 2006.217.08:19:49.74#ibcon#about to read 6, iclass 14, count 2 2006.217.08:19:49.74#ibcon#read 6, iclass 14, count 2 2006.217.08:19:49.74#ibcon#end of sib2, iclass 14, count 2 2006.217.08:19:49.74#ibcon#*after write, iclass 14, count 2 2006.217.08:19:49.74#ibcon#*before return 0, iclass 14, count 2 2006.217.08:19:49.74#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.217.08:19:49.74#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.217.08:19:49.74#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.217.08:19:49.74#ibcon#ireg 7 cls_cnt 0 2006.217.08:19:49.74#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.217.08:19:49.86#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.217.08:19:49.86#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.217.08:19:49.86#ibcon#enter wrdev, iclass 14, count 0 2006.217.08:19:49.86#ibcon#first serial, iclass 14, count 0 2006.217.08:19:49.86#ibcon#enter sib2, iclass 14, count 0 2006.217.08:19:49.86#ibcon#flushed, iclass 14, count 0 2006.217.08:19:49.86#ibcon#about to write, iclass 14, count 0 2006.217.08:19:49.86#ibcon#wrote, iclass 14, count 0 2006.217.08:19:49.86#ibcon#about to read 3, iclass 14, count 0 2006.217.08:19:49.88#ibcon#read 3, iclass 14, count 0 2006.217.08:19:49.88#ibcon#about to read 4, iclass 14, count 0 2006.217.08:19:49.88#ibcon#read 4, iclass 14, count 0 2006.217.08:19:49.88#ibcon#about to read 5, iclass 14, count 0 2006.217.08:19:49.88#ibcon#read 5, iclass 14, count 0 2006.217.08:19:49.88#ibcon#about to read 6, iclass 14, count 0 2006.217.08:19:49.88#ibcon#read 6, iclass 14, count 0 2006.217.08:19:49.88#ibcon#end of sib2, iclass 14, count 0 2006.217.08:19:49.88#ibcon#*mode == 0, iclass 14, count 0 2006.217.08:19:49.88#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.217.08:19:49.88#ibcon#[25=USB\r\n] 2006.217.08:19:49.88#ibcon#*before write, iclass 14, count 0 2006.217.08:19:49.88#ibcon#enter sib2, iclass 14, count 0 2006.217.08:19:49.88#ibcon#flushed, iclass 14, count 0 2006.217.08:19:49.88#ibcon#about to write, iclass 14, count 0 2006.217.08:19:49.88#ibcon#wrote, iclass 14, count 0 2006.217.08:19:49.88#ibcon#about to read 3, iclass 14, count 0 2006.217.08:19:49.91#ibcon#read 3, iclass 14, count 0 2006.217.08:19:49.91#ibcon#about to read 4, iclass 14, count 0 2006.217.08:19:49.91#ibcon#read 4, iclass 14, count 0 2006.217.08:19:49.91#ibcon#about to read 5, iclass 14, count 0 2006.217.08:19:49.91#ibcon#read 5, iclass 14, count 0 2006.217.08:19:49.91#ibcon#about to read 6, iclass 14, count 0 2006.217.08:19:49.91#ibcon#read 6, iclass 14, count 0 2006.217.08:19:49.91#ibcon#end of sib2, iclass 14, count 0 2006.217.08:19:49.91#ibcon#*after write, iclass 14, count 0 2006.217.08:19:49.91#ibcon#*before return 0, iclass 14, count 0 2006.217.08:19:49.91#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.217.08:19:49.91#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.217.08:19:49.91#ibcon#about to clear, iclass 14 cls_cnt 0 2006.217.08:19:49.91#ibcon#cleared, iclass 14 cls_cnt 0 2006.217.08:19:49.91$vc4f8/valo=7,832.99 2006.217.08:19:49.91#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.217.08:19:49.91#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.217.08:19:49.91#ibcon#ireg 17 cls_cnt 0 2006.217.08:19:49.91#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.217.08:19:49.91#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.217.08:19:49.91#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.217.08:19:49.91#ibcon#enter wrdev, iclass 16, count 0 2006.217.08:19:49.91#ibcon#first serial, iclass 16, count 0 2006.217.08:19:49.91#ibcon#enter sib2, iclass 16, count 0 2006.217.08:19:49.91#ibcon#flushed, iclass 16, count 0 2006.217.08:19:49.91#ibcon#about to write, iclass 16, count 0 2006.217.08:19:49.91#ibcon#wrote, iclass 16, count 0 2006.217.08:19:49.91#ibcon#about to read 3, iclass 16, count 0 2006.217.08:19:49.93#ibcon#read 3, iclass 16, count 0 2006.217.08:19:49.93#ibcon#about to read 4, iclass 16, count 0 2006.217.08:19:49.93#ibcon#read 4, iclass 16, count 0 2006.217.08:19:49.93#ibcon#about to read 5, iclass 16, count 0 2006.217.08:19:49.93#ibcon#read 5, iclass 16, count 0 2006.217.08:19:49.93#ibcon#about to read 6, iclass 16, count 0 2006.217.08:19:49.93#ibcon#read 6, iclass 16, count 0 2006.217.08:19:49.93#ibcon#end of sib2, iclass 16, count 0 2006.217.08:19:49.93#ibcon#*mode == 0, iclass 16, count 0 2006.217.08:19:49.93#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.217.08:19:49.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.217.08:19:49.93#ibcon#*before write, iclass 16, count 0 2006.217.08:19:49.93#ibcon#enter sib2, iclass 16, count 0 2006.217.08:19:49.93#ibcon#flushed, iclass 16, count 0 2006.217.08:19:49.93#ibcon#about to write, iclass 16, count 0 2006.217.08:19:49.93#ibcon#wrote, iclass 16, count 0 2006.217.08:19:49.93#ibcon#about to read 3, iclass 16, count 0 2006.217.08:19:49.97#ibcon#read 3, iclass 16, count 0 2006.217.08:19:49.97#ibcon#about to read 4, iclass 16, count 0 2006.217.08:19:49.97#ibcon#read 4, iclass 16, count 0 2006.217.08:19:49.97#ibcon#about to read 5, iclass 16, count 0 2006.217.08:19:49.97#ibcon#read 5, iclass 16, count 0 2006.217.08:19:49.97#ibcon#about to read 6, iclass 16, count 0 2006.217.08:19:49.97#ibcon#read 6, iclass 16, count 0 2006.217.08:19:49.97#ibcon#end of sib2, iclass 16, count 0 2006.217.08:19:49.97#ibcon#*after write, iclass 16, count 0 2006.217.08:19:49.97#ibcon#*before return 0, iclass 16, count 0 2006.217.08:19:49.97#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.217.08:19:49.97#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.217.08:19:49.97#ibcon#about to clear, iclass 16 cls_cnt 0 2006.217.08:19:49.97#ibcon#cleared, iclass 16 cls_cnt 0 2006.217.08:19:49.97$vc4f8/va=7,6 2006.217.08:19:49.97#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.217.08:19:49.97#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.217.08:19:49.97#ibcon#ireg 11 cls_cnt 2 2006.217.08:19:49.97#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.217.08:19:50.03#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.217.08:19:50.03#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.217.08:19:50.03#ibcon#enter wrdev, iclass 18, count 2 2006.217.08:19:50.03#ibcon#first serial, iclass 18, count 2 2006.217.08:19:50.03#ibcon#enter sib2, iclass 18, count 2 2006.217.08:19:50.03#ibcon#flushed, iclass 18, count 2 2006.217.08:19:50.03#ibcon#about to write, iclass 18, count 2 2006.217.08:19:50.03#ibcon#wrote, iclass 18, count 2 2006.217.08:19:50.03#ibcon#about to read 3, iclass 18, count 2 2006.217.08:19:50.05#ibcon#read 3, iclass 18, count 2 2006.217.08:19:50.05#ibcon#about to read 4, iclass 18, count 2 2006.217.08:19:50.05#ibcon#read 4, iclass 18, count 2 2006.217.08:19:50.05#ibcon#about to read 5, iclass 18, count 2 2006.217.08:19:50.05#ibcon#read 5, iclass 18, count 2 2006.217.08:19:50.05#ibcon#about to read 6, iclass 18, count 2 2006.217.08:19:50.05#ibcon#read 6, iclass 18, count 2 2006.217.08:19:50.05#ibcon#end of sib2, iclass 18, count 2 2006.217.08:19:50.05#ibcon#*mode == 0, iclass 18, count 2 2006.217.08:19:50.05#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.217.08:19:50.05#ibcon#[25=AT07-06\r\n] 2006.217.08:19:50.05#ibcon#*before write, iclass 18, count 2 2006.217.08:19:50.05#ibcon#enter sib2, iclass 18, count 2 2006.217.08:19:50.05#ibcon#flushed, iclass 18, count 2 2006.217.08:19:50.05#ibcon#about to write, iclass 18, count 2 2006.217.08:19:50.05#ibcon#wrote, iclass 18, count 2 2006.217.08:19:50.05#ibcon#about to read 3, iclass 18, count 2 2006.217.08:19:50.08#ibcon#read 3, iclass 18, count 2 2006.217.08:19:50.08#ibcon#about to read 4, iclass 18, count 2 2006.217.08:19:50.08#ibcon#read 4, iclass 18, count 2 2006.217.08:19:50.08#ibcon#about to read 5, iclass 18, count 2 2006.217.08:19:50.08#ibcon#read 5, iclass 18, count 2 2006.217.08:19:50.08#ibcon#about to read 6, iclass 18, count 2 2006.217.08:19:50.08#ibcon#read 6, iclass 18, count 2 2006.217.08:19:50.08#ibcon#end of sib2, iclass 18, count 2 2006.217.08:19:50.08#ibcon#*after write, iclass 18, count 2 2006.217.08:19:50.08#ibcon#*before return 0, iclass 18, count 2 2006.217.08:19:50.08#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.217.08:19:50.08#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.217.08:19:50.08#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.217.08:19:50.08#ibcon#ireg 7 cls_cnt 0 2006.217.08:19:50.08#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.217.08:19:50.20#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.217.08:19:50.20#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.217.08:19:50.20#ibcon#enter wrdev, iclass 18, count 0 2006.217.08:19:50.20#ibcon#first serial, iclass 18, count 0 2006.217.08:19:50.20#ibcon#enter sib2, iclass 18, count 0 2006.217.08:19:50.20#ibcon#flushed, iclass 18, count 0 2006.217.08:19:50.20#ibcon#about to write, iclass 18, count 0 2006.217.08:19:50.20#ibcon#wrote, iclass 18, count 0 2006.217.08:19:50.20#ibcon#about to read 3, iclass 18, count 0 2006.217.08:19:50.22#ibcon#read 3, iclass 18, count 0 2006.217.08:19:50.22#ibcon#about to read 4, iclass 18, count 0 2006.217.08:19:50.22#ibcon#read 4, iclass 18, count 0 2006.217.08:19:50.22#ibcon#about to read 5, iclass 18, count 0 2006.217.08:19:50.22#ibcon#read 5, iclass 18, count 0 2006.217.08:19:50.22#ibcon#about to read 6, iclass 18, count 0 2006.217.08:19:50.22#ibcon#read 6, iclass 18, count 0 2006.217.08:19:50.22#ibcon#end of sib2, iclass 18, count 0 2006.217.08:19:50.22#ibcon#*mode == 0, iclass 18, count 0 2006.217.08:19:50.22#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.217.08:19:50.22#ibcon#[25=USB\r\n] 2006.217.08:19:50.22#ibcon#*before write, iclass 18, count 0 2006.217.08:19:50.22#ibcon#enter sib2, iclass 18, count 0 2006.217.08:19:50.22#ibcon#flushed, iclass 18, count 0 2006.217.08:19:50.22#ibcon#about to write, iclass 18, count 0 2006.217.08:19:50.22#ibcon#wrote, iclass 18, count 0 2006.217.08:19:50.22#ibcon#about to read 3, iclass 18, count 0 2006.217.08:19:50.25#ibcon#read 3, iclass 18, count 0 2006.217.08:19:50.25#ibcon#about to read 4, iclass 18, count 0 2006.217.08:19:50.25#ibcon#read 4, iclass 18, count 0 2006.217.08:19:50.25#ibcon#about to read 5, iclass 18, count 0 2006.217.08:19:50.25#ibcon#read 5, iclass 18, count 0 2006.217.08:19:50.25#ibcon#about to read 6, iclass 18, count 0 2006.217.08:19:50.25#ibcon#read 6, iclass 18, count 0 2006.217.08:19:50.25#ibcon#end of sib2, iclass 18, count 0 2006.217.08:19:50.25#ibcon#*after write, iclass 18, count 0 2006.217.08:19:50.25#ibcon#*before return 0, iclass 18, count 0 2006.217.08:19:50.25#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.217.08:19:50.25#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.217.08:19:50.25#ibcon#about to clear, iclass 18 cls_cnt 0 2006.217.08:19:50.25#ibcon#cleared, iclass 18 cls_cnt 0 2006.217.08:19:50.25$vc4f8/valo=8,852.99 2006.217.08:19:50.25#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.217.08:19:50.25#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.217.08:19:50.25#ibcon#ireg 17 cls_cnt 0 2006.217.08:19:50.25#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.217.08:19:50.25#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.217.08:19:50.25#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.217.08:19:50.25#ibcon#enter wrdev, iclass 20, count 0 2006.217.08:19:50.25#ibcon#first serial, iclass 20, count 0 2006.217.08:19:50.25#ibcon#enter sib2, iclass 20, count 0 2006.217.08:19:50.25#ibcon#flushed, iclass 20, count 0 2006.217.08:19:50.25#ibcon#about to write, iclass 20, count 0 2006.217.08:19:50.25#ibcon#wrote, iclass 20, count 0 2006.217.08:19:50.25#ibcon#about to read 3, iclass 20, count 0 2006.217.08:19:50.27#ibcon#read 3, iclass 20, count 0 2006.217.08:19:50.27#ibcon#about to read 4, iclass 20, count 0 2006.217.08:19:50.27#ibcon#read 4, iclass 20, count 0 2006.217.08:19:50.27#ibcon#about to read 5, iclass 20, count 0 2006.217.08:19:50.27#ibcon#read 5, iclass 20, count 0 2006.217.08:19:50.27#ibcon#about to read 6, iclass 20, count 0 2006.217.08:19:50.27#ibcon#read 6, iclass 20, count 0 2006.217.08:19:50.27#ibcon#end of sib2, iclass 20, count 0 2006.217.08:19:50.27#ibcon#*mode == 0, iclass 20, count 0 2006.217.08:19:50.27#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.217.08:19:50.27#ibcon#[26=FRQ=08,852.99\r\n] 2006.217.08:19:50.27#ibcon#*before write, iclass 20, count 0 2006.217.08:19:50.27#ibcon#enter sib2, iclass 20, count 0 2006.217.08:19:50.27#ibcon#flushed, iclass 20, count 0 2006.217.08:19:50.27#ibcon#about to write, iclass 20, count 0 2006.217.08:19:50.27#ibcon#wrote, iclass 20, count 0 2006.217.08:19:50.27#ibcon#about to read 3, iclass 20, count 0 2006.217.08:19:50.31#ibcon#read 3, iclass 20, count 0 2006.217.08:19:50.31#ibcon#about to read 4, iclass 20, count 0 2006.217.08:19:50.31#ibcon#read 4, iclass 20, count 0 2006.217.08:19:50.31#ibcon#about to read 5, iclass 20, count 0 2006.217.08:19:50.31#ibcon#read 5, iclass 20, count 0 2006.217.08:19:50.31#ibcon#about to read 6, iclass 20, count 0 2006.217.08:19:50.31#ibcon#read 6, iclass 20, count 0 2006.217.08:19:50.31#ibcon#end of sib2, iclass 20, count 0 2006.217.08:19:50.31#ibcon#*after write, iclass 20, count 0 2006.217.08:19:50.31#ibcon#*before return 0, iclass 20, count 0 2006.217.08:19:50.31#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.217.08:19:50.31#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.217.08:19:50.31#ibcon#about to clear, iclass 20 cls_cnt 0 2006.217.08:19:50.31#ibcon#cleared, iclass 20 cls_cnt 0 2006.217.08:19:50.31$vc4f8/va=8,7 2006.217.08:19:50.31#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.217.08:19:50.31#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.217.08:19:50.31#ibcon#ireg 11 cls_cnt 2 2006.217.08:19:50.31#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.217.08:19:50.37#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.217.08:19:50.37#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.217.08:19:50.37#ibcon#enter wrdev, iclass 22, count 2 2006.217.08:19:50.37#ibcon#first serial, iclass 22, count 2 2006.217.08:19:50.37#ibcon#enter sib2, iclass 22, count 2 2006.217.08:19:50.37#ibcon#flushed, iclass 22, count 2 2006.217.08:19:50.37#ibcon#about to write, iclass 22, count 2 2006.217.08:19:50.37#ibcon#wrote, iclass 22, count 2 2006.217.08:19:50.37#ibcon#about to read 3, iclass 22, count 2 2006.217.08:19:50.40#ibcon#read 3, iclass 22, count 2 2006.217.08:19:50.40#ibcon#about to read 4, iclass 22, count 2 2006.217.08:19:50.40#ibcon#read 4, iclass 22, count 2 2006.217.08:19:50.40#ibcon#about to read 5, iclass 22, count 2 2006.217.08:19:50.40#ibcon#read 5, iclass 22, count 2 2006.217.08:19:50.40#ibcon#about to read 6, iclass 22, count 2 2006.217.08:19:50.40#ibcon#read 6, iclass 22, count 2 2006.217.08:19:50.40#ibcon#end of sib2, iclass 22, count 2 2006.217.08:19:50.40#ibcon#*mode == 0, iclass 22, count 2 2006.217.08:19:50.40#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.217.08:19:50.40#ibcon#[25=AT08-07\r\n] 2006.217.08:19:50.40#ibcon#*before write, iclass 22, count 2 2006.217.08:19:50.40#ibcon#enter sib2, iclass 22, count 2 2006.217.08:19:50.40#ibcon#flushed, iclass 22, count 2 2006.217.08:19:50.40#ibcon#about to write, iclass 22, count 2 2006.217.08:19:50.40#ibcon#wrote, iclass 22, count 2 2006.217.08:19:50.40#ibcon#about to read 3, iclass 22, count 2 2006.217.08:19:50.43#ibcon#read 3, iclass 22, count 2 2006.217.08:19:50.43#ibcon#about to read 4, iclass 22, count 2 2006.217.08:19:50.43#ibcon#read 4, iclass 22, count 2 2006.217.08:19:50.43#ibcon#about to read 5, iclass 22, count 2 2006.217.08:19:50.43#ibcon#read 5, iclass 22, count 2 2006.217.08:19:50.43#ibcon#about to read 6, iclass 22, count 2 2006.217.08:19:50.43#ibcon#read 6, iclass 22, count 2 2006.217.08:19:50.43#ibcon#end of sib2, iclass 22, count 2 2006.217.08:19:50.43#ibcon#*after write, iclass 22, count 2 2006.217.08:19:50.43#ibcon#*before return 0, iclass 22, count 2 2006.217.08:19:50.43#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.217.08:19:50.43#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.217.08:19:50.43#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.217.08:19:50.43#ibcon#ireg 7 cls_cnt 0 2006.217.08:19:50.43#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.217.08:19:50.55#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.217.08:19:50.55#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.217.08:19:50.55#ibcon#enter wrdev, iclass 22, count 0 2006.217.08:19:50.55#ibcon#first serial, iclass 22, count 0 2006.217.08:19:50.55#ibcon#enter sib2, iclass 22, count 0 2006.217.08:19:50.55#ibcon#flushed, iclass 22, count 0 2006.217.08:19:50.55#ibcon#about to write, iclass 22, count 0 2006.217.08:19:50.55#ibcon#wrote, iclass 22, count 0 2006.217.08:19:50.55#ibcon#about to read 3, iclass 22, count 0 2006.217.08:19:50.57#ibcon#read 3, iclass 22, count 0 2006.217.08:19:50.57#ibcon#about to read 4, iclass 22, count 0 2006.217.08:19:50.57#ibcon#read 4, iclass 22, count 0 2006.217.08:19:50.57#ibcon#about to read 5, iclass 22, count 0 2006.217.08:19:50.57#ibcon#read 5, iclass 22, count 0 2006.217.08:19:50.57#ibcon#about to read 6, iclass 22, count 0 2006.217.08:19:50.57#ibcon#read 6, iclass 22, count 0 2006.217.08:19:50.57#ibcon#end of sib2, iclass 22, count 0 2006.217.08:19:50.57#ibcon#*mode == 0, iclass 22, count 0 2006.217.08:19:50.57#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.217.08:19:50.57#ibcon#[25=USB\r\n] 2006.217.08:19:50.57#ibcon#*before write, iclass 22, count 0 2006.217.08:19:50.57#ibcon#enter sib2, iclass 22, count 0 2006.217.08:19:50.57#ibcon#flushed, iclass 22, count 0 2006.217.08:19:50.57#ibcon#about to write, iclass 22, count 0 2006.217.08:19:50.57#ibcon#wrote, iclass 22, count 0 2006.217.08:19:50.57#ibcon#about to read 3, iclass 22, count 0 2006.217.08:19:50.60#ibcon#read 3, iclass 22, count 0 2006.217.08:19:50.60#ibcon#about to read 4, iclass 22, count 0 2006.217.08:19:50.60#ibcon#read 4, iclass 22, count 0 2006.217.08:19:50.60#ibcon#about to read 5, iclass 22, count 0 2006.217.08:19:50.60#ibcon#read 5, iclass 22, count 0 2006.217.08:19:50.60#ibcon#about to read 6, iclass 22, count 0 2006.217.08:19:50.60#ibcon#read 6, iclass 22, count 0 2006.217.08:19:50.60#ibcon#end of sib2, iclass 22, count 0 2006.217.08:19:50.60#ibcon#*after write, iclass 22, count 0 2006.217.08:19:50.60#ibcon#*before return 0, iclass 22, count 0 2006.217.08:19:50.60#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.217.08:19:50.60#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.217.08:19:50.60#ibcon#about to clear, iclass 22 cls_cnt 0 2006.217.08:19:50.60#ibcon#cleared, iclass 22 cls_cnt 0 2006.217.08:19:50.60$vc4f8/vblo=1,632.99 2006.217.08:19:50.60#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.217.08:19:50.60#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.217.08:19:50.60#ibcon#ireg 17 cls_cnt 0 2006.217.08:19:50.60#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.217.08:19:50.60#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.217.08:19:50.60#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.217.08:19:50.60#ibcon#enter wrdev, iclass 24, count 0 2006.217.08:19:50.60#ibcon#first serial, iclass 24, count 0 2006.217.08:19:50.60#ibcon#enter sib2, iclass 24, count 0 2006.217.08:19:50.60#ibcon#flushed, iclass 24, count 0 2006.217.08:19:50.60#ibcon#about to write, iclass 24, count 0 2006.217.08:19:50.60#ibcon#wrote, iclass 24, count 0 2006.217.08:19:50.60#ibcon#about to read 3, iclass 24, count 0 2006.217.08:19:50.62#ibcon#read 3, iclass 24, count 0 2006.217.08:19:50.62#ibcon#about to read 4, iclass 24, count 0 2006.217.08:19:50.62#ibcon#read 4, iclass 24, count 0 2006.217.08:19:50.62#ibcon#about to read 5, iclass 24, count 0 2006.217.08:19:50.62#ibcon#read 5, iclass 24, count 0 2006.217.08:19:50.62#ibcon#about to read 6, iclass 24, count 0 2006.217.08:19:50.62#ibcon#read 6, iclass 24, count 0 2006.217.08:19:50.62#ibcon#end of sib2, iclass 24, count 0 2006.217.08:19:50.62#ibcon#*mode == 0, iclass 24, count 0 2006.217.08:19:50.62#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.217.08:19:50.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.217.08:19:50.62#ibcon#*before write, iclass 24, count 0 2006.217.08:19:50.62#ibcon#enter sib2, iclass 24, count 0 2006.217.08:19:50.62#ibcon#flushed, iclass 24, count 0 2006.217.08:19:50.62#ibcon#about to write, iclass 24, count 0 2006.217.08:19:50.62#ibcon#wrote, iclass 24, count 0 2006.217.08:19:50.62#ibcon#about to read 3, iclass 24, count 0 2006.217.08:19:50.66#ibcon#read 3, iclass 24, count 0 2006.217.08:19:50.66#ibcon#about to read 4, iclass 24, count 0 2006.217.08:19:50.66#ibcon#read 4, iclass 24, count 0 2006.217.08:19:50.66#ibcon#about to read 5, iclass 24, count 0 2006.217.08:19:50.66#ibcon#read 5, iclass 24, count 0 2006.217.08:19:50.66#ibcon#about to read 6, iclass 24, count 0 2006.217.08:19:50.66#ibcon#read 6, iclass 24, count 0 2006.217.08:19:50.66#ibcon#end of sib2, iclass 24, count 0 2006.217.08:19:50.66#ibcon#*after write, iclass 24, count 0 2006.217.08:19:50.66#ibcon#*before return 0, iclass 24, count 0 2006.217.08:19:50.66#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.217.08:19:50.66#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.217.08:19:50.66#ibcon#about to clear, iclass 24 cls_cnt 0 2006.217.08:19:50.66#ibcon#cleared, iclass 24 cls_cnt 0 2006.217.08:19:50.66$vc4f8/vb=1,4 2006.217.08:19:50.66#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.217.08:19:50.66#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.217.08:19:50.66#ibcon#ireg 11 cls_cnt 2 2006.217.08:19:50.66#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.217.08:19:50.66#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.217.08:19:50.66#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.217.08:19:50.66#ibcon#enter wrdev, iclass 26, count 2 2006.217.08:19:50.66#ibcon#first serial, iclass 26, count 2 2006.217.08:19:50.66#ibcon#enter sib2, iclass 26, count 2 2006.217.08:19:50.66#ibcon#flushed, iclass 26, count 2 2006.217.08:19:50.66#ibcon#about to write, iclass 26, count 2 2006.217.08:19:50.66#ibcon#wrote, iclass 26, count 2 2006.217.08:19:50.66#ibcon#about to read 3, iclass 26, count 2 2006.217.08:19:50.68#ibcon#read 3, iclass 26, count 2 2006.217.08:19:50.68#ibcon#about to read 4, iclass 26, count 2 2006.217.08:19:50.68#ibcon#read 4, iclass 26, count 2 2006.217.08:19:50.68#ibcon#about to read 5, iclass 26, count 2 2006.217.08:19:50.68#ibcon#read 5, iclass 26, count 2 2006.217.08:19:50.68#ibcon#about to read 6, iclass 26, count 2 2006.217.08:19:50.68#ibcon#read 6, iclass 26, count 2 2006.217.08:19:50.68#ibcon#end of sib2, iclass 26, count 2 2006.217.08:19:50.68#ibcon#*mode == 0, iclass 26, count 2 2006.217.08:19:50.68#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.217.08:19:50.68#ibcon#[27=AT01-04\r\n] 2006.217.08:19:50.68#ibcon#*before write, iclass 26, count 2 2006.217.08:19:50.68#ibcon#enter sib2, iclass 26, count 2 2006.217.08:19:50.68#ibcon#flushed, iclass 26, count 2 2006.217.08:19:50.68#ibcon#about to write, iclass 26, count 2 2006.217.08:19:50.68#ibcon#wrote, iclass 26, count 2 2006.217.08:19:50.68#ibcon#about to read 3, iclass 26, count 2 2006.217.08:19:50.71#ibcon#read 3, iclass 26, count 2 2006.217.08:19:50.71#ibcon#about to read 4, iclass 26, count 2 2006.217.08:19:50.71#ibcon#read 4, iclass 26, count 2 2006.217.08:19:50.71#ibcon#about to read 5, iclass 26, count 2 2006.217.08:19:50.71#ibcon#read 5, iclass 26, count 2 2006.217.08:19:50.71#ibcon#about to read 6, iclass 26, count 2 2006.217.08:19:50.71#ibcon#read 6, iclass 26, count 2 2006.217.08:19:50.71#ibcon#end of sib2, iclass 26, count 2 2006.217.08:19:50.71#ibcon#*after write, iclass 26, count 2 2006.217.08:19:50.71#ibcon#*before return 0, iclass 26, count 2 2006.217.08:19:50.71#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.217.08:19:50.71#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.217.08:19:50.71#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.217.08:19:50.71#ibcon#ireg 7 cls_cnt 0 2006.217.08:19:50.71#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.217.08:19:50.83#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.217.08:19:50.83#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.217.08:19:50.83#ibcon#enter wrdev, iclass 26, count 0 2006.217.08:19:50.83#ibcon#first serial, iclass 26, count 0 2006.217.08:19:50.83#ibcon#enter sib2, iclass 26, count 0 2006.217.08:19:50.83#ibcon#flushed, iclass 26, count 0 2006.217.08:19:50.83#ibcon#about to write, iclass 26, count 0 2006.217.08:19:50.83#ibcon#wrote, iclass 26, count 0 2006.217.08:19:50.83#ibcon#about to read 3, iclass 26, count 0 2006.217.08:19:50.85#ibcon#read 3, iclass 26, count 0 2006.217.08:19:50.85#ibcon#about to read 4, iclass 26, count 0 2006.217.08:19:50.85#ibcon#read 4, iclass 26, count 0 2006.217.08:19:50.85#ibcon#about to read 5, iclass 26, count 0 2006.217.08:19:50.85#ibcon#read 5, iclass 26, count 0 2006.217.08:19:50.85#ibcon#about to read 6, iclass 26, count 0 2006.217.08:19:50.85#ibcon#read 6, iclass 26, count 0 2006.217.08:19:50.85#ibcon#end of sib2, iclass 26, count 0 2006.217.08:19:50.85#ibcon#*mode == 0, iclass 26, count 0 2006.217.08:19:50.85#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.217.08:19:50.85#ibcon#[27=USB\r\n] 2006.217.08:19:50.85#ibcon#*before write, iclass 26, count 0 2006.217.08:19:50.85#ibcon#enter sib2, iclass 26, count 0 2006.217.08:19:50.85#ibcon#flushed, iclass 26, count 0 2006.217.08:19:50.85#ibcon#about to write, iclass 26, count 0 2006.217.08:19:50.85#ibcon#wrote, iclass 26, count 0 2006.217.08:19:50.85#ibcon#about to read 3, iclass 26, count 0 2006.217.08:19:50.88#ibcon#read 3, iclass 26, count 0 2006.217.08:19:50.88#ibcon#about to read 4, iclass 26, count 0 2006.217.08:19:50.88#ibcon#read 4, iclass 26, count 0 2006.217.08:19:50.88#ibcon#about to read 5, iclass 26, count 0 2006.217.08:19:50.88#ibcon#read 5, iclass 26, count 0 2006.217.08:19:50.88#ibcon#about to read 6, iclass 26, count 0 2006.217.08:19:50.88#ibcon#read 6, iclass 26, count 0 2006.217.08:19:50.88#ibcon#end of sib2, iclass 26, count 0 2006.217.08:19:50.88#ibcon#*after write, iclass 26, count 0 2006.217.08:19:50.88#ibcon#*before return 0, iclass 26, count 0 2006.217.08:19:50.88#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.217.08:19:50.88#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.217.08:19:50.88#ibcon#about to clear, iclass 26 cls_cnt 0 2006.217.08:19:50.88#ibcon#cleared, iclass 26 cls_cnt 0 2006.217.08:19:50.88$vc4f8/vblo=2,640.99 2006.217.08:19:50.88#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.217.08:19:50.88#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.217.08:19:50.88#ibcon#ireg 17 cls_cnt 0 2006.217.08:19:50.88#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.217.08:19:50.88#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.217.08:19:50.88#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.217.08:19:50.88#ibcon#enter wrdev, iclass 28, count 0 2006.217.08:19:50.88#ibcon#first serial, iclass 28, count 0 2006.217.08:19:50.88#ibcon#enter sib2, iclass 28, count 0 2006.217.08:19:50.88#ibcon#flushed, iclass 28, count 0 2006.217.08:19:50.88#ibcon#about to write, iclass 28, count 0 2006.217.08:19:50.88#ibcon#wrote, iclass 28, count 0 2006.217.08:19:50.88#ibcon#about to read 3, iclass 28, count 0 2006.217.08:19:50.90#ibcon#read 3, iclass 28, count 0 2006.217.08:19:50.90#ibcon#about to read 4, iclass 28, count 0 2006.217.08:19:50.90#ibcon#read 4, iclass 28, count 0 2006.217.08:19:50.90#ibcon#about to read 5, iclass 28, count 0 2006.217.08:19:50.90#ibcon#read 5, iclass 28, count 0 2006.217.08:19:50.90#ibcon#about to read 6, iclass 28, count 0 2006.217.08:19:50.90#ibcon#read 6, iclass 28, count 0 2006.217.08:19:50.90#ibcon#end of sib2, iclass 28, count 0 2006.217.08:19:50.90#ibcon#*mode == 0, iclass 28, count 0 2006.217.08:19:50.90#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.217.08:19:50.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.217.08:19:50.90#ibcon#*before write, iclass 28, count 0 2006.217.08:19:50.90#ibcon#enter sib2, iclass 28, count 0 2006.217.08:19:50.90#ibcon#flushed, iclass 28, count 0 2006.217.08:19:50.90#ibcon#about to write, iclass 28, count 0 2006.217.08:19:50.90#ibcon#wrote, iclass 28, count 0 2006.217.08:19:50.90#ibcon#about to read 3, iclass 28, count 0 2006.217.08:19:50.94#ibcon#read 3, iclass 28, count 0 2006.217.08:19:50.94#ibcon#about to read 4, iclass 28, count 0 2006.217.08:19:50.94#ibcon#read 4, iclass 28, count 0 2006.217.08:19:50.94#ibcon#about to read 5, iclass 28, count 0 2006.217.08:19:50.94#ibcon#read 5, iclass 28, count 0 2006.217.08:19:50.94#ibcon#about to read 6, iclass 28, count 0 2006.217.08:19:50.94#ibcon#read 6, iclass 28, count 0 2006.217.08:19:50.94#ibcon#end of sib2, iclass 28, count 0 2006.217.08:19:50.94#ibcon#*after write, iclass 28, count 0 2006.217.08:19:50.94#ibcon#*before return 0, iclass 28, count 0 2006.217.08:19:50.94#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.217.08:19:50.94#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.217.08:19:50.94#ibcon#about to clear, iclass 28 cls_cnt 0 2006.217.08:19:50.94#ibcon#cleared, iclass 28 cls_cnt 0 2006.217.08:19:50.94$vc4f8/vb=2,4 2006.217.08:19:50.94#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.217.08:19:50.94#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.217.08:19:50.94#ibcon#ireg 11 cls_cnt 2 2006.217.08:19:50.94#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.217.08:19:51.00#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.217.08:19:51.00#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.217.08:19:51.00#ibcon#enter wrdev, iclass 30, count 2 2006.217.08:19:51.00#ibcon#first serial, iclass 30, count 2 2006.217.08:19:51.00#ibcon#enter sib2, iclass 30, count 2 2006.217.08:19:51.00#ibcon#flushed, iclass 30, count 2 2006.217.08:19:51.00#ibcon#about to write, iclass 30, count 2 2006.217.08:19:51.00#ibcon#wrote, iclass 30, count 2 2006.217.08:19:51.00#ibcon#about to read 3, iclass 30, count 2 2006.217.08:19:51.02#ibcon#read 3, iclass 30, count 2 2006.217.08:19:51.02#ibcon#about to read 4, iclass 30, count 2 2006.217.08:19:51.02#ibcon#read 4, iclass 30, count 2 2006.217.08:19:51.02#ibcon#about to read 5, iclass 30, count 2 2006.217.08:19:51.02#ibcon#read 5, iclass 30, count 2 2006.217.08:19:51.02#ibcon#about to read 6, iclass 30, count 2 2006.217.08:19:51.02#ibcon#read 6, iclass 30, count 2 2006.217.08:19:51.02#ibcon#end of sib2, iclass 30, count 2 2006.217.08:19:51.02#ibcon#*mode == 0, iclass 30, count 2 2006.217.08:19:51.02#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.217.08:19:51.02#ibcon#[27=AT02-04\r\n] 2006.217.08:19:51.02#ibcon#*before write, iclass 30, count 2 2006.217.08:19:51.02#ibcon#enter sib2, iclass 30, count 2 2006.217.08:19:51.02#ibcon#flushed, iclass 30, count 2 2006.217.08:19:51.02#ibcon#about to write, iclass 30, count 2 2006.217.08:19:51.02#ibcon#wrote, iclass 30, count 2 2006.217.08:19:51.02#ibcon#about to read 3, iclass 30, count 2 2006.217.08:19:51.05#ibcon#read 3, iclass 30, count 2 2006.217.08:19:51.05#ibcon#about to read 4, iclass 30, count 2 2006.217.08:19:51.05#ibcon#read 4, iclass 30, count 2 2006.217.08:19:51.05#ibcon#about to read 5, iclass 30, count 2 2006.217.08:19:51.05#ibcon#read 5, iclass 30, count 2 2006.217.08:19:51.05#ibcon#about to read 6, iclass 30, count 2 2006.217.08:19:51.05#ibcon#read 6, iclass 30, count 2 2006.217.08:19:51.05#ibcon#end of sib2, iclass 30, count 2 2006.217.08:19:51.05#ibcon#*after write, iclass 30, count 2 2006.217.08:19:51.05#ibcon#*before return 0, iclass 30, count 2 2006.217.08:19:51.05#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.217.08:19:51.05#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.217.08:19:51.05#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.217.08:19:51.05#ibcon#ireg 7 cls_cnt 0 2006.217.08:19:51.05#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.217.08:19:51.17#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.217.08:19:51.17#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.217.08:19:51.17#ibcon#enter wrdev, iclass 30, count 0 2006.217.08:19:51.17#ibcon#first serial, iclass 30, count 0 2006.217.08:19:51.17#ibcon#enter sib2, iclass 30, count 0 2006.217.08:19:51.17#ibcon#flushed, iclass 30, count 0 2006.217.08:19:51.17#ibcon#about to write, iclass 30, count 0 2006.217.08:19:51.17#ibcon#wrote, iclass 30, count 0 2006.217.08:19:51.17#ibcon#about to read 3, iclass 30, count 0 2006.217.08:19:51.19#ibcon#read 3, iclass 30, count 0 2006.217.08:19:51.19#ibcon#about to read 4, iclass 30, count 0 2006.217.08:19:51.19#ibcon#read 4, iclass 30, count 0 2006.217.08:19:51.19#ibcon#about to read 5, iclass 30, count 0 2006.217.08:19:51.19#ibcon#read 5, iclass 30, count 0 2006.217.08:19:51.19#ibcon#about to read 6, iclass 30, count 0 2006.217.08:19:51.19#ibcon#read 6, iclass 30, count 0 2006.217.08:19:51.19#ibcon#end of sib2, iclass 30, count 0 2006.217.08:19:51.19#ibcon#*mode == 0, iclass 30, count 0 2006.217.08:19:51.19#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.217.08:19:51.19#ibcon#[27=USB\r\n] 2006.217.08:19:51.19#ibcon#*before write, iclass 30, count 0 2006.217.08:19:51.19#ibcon#enter sib2, iclass 30, count 0 2006.217.08:19:51.19#ibcon#flushed, iclass 30, count 0 2006.217.08:19:51.19#ibcon#about to write, iclass 30, count 0 2006.217.08:19:51.19#ibcon#wrote, iclass 30, count 0 2006.217.08:19:51.19#ibcon#about to read 3, iclass 30, count 0 2006.217.08:19:51.22#ibcon#read 3, iclass 30, count 0 2006.217.08:19:51.22#ibcon#about to read 4, iclass 30, count 0 2006.217.08:19:51.22#ibcon#read 4, iclass 30, count 0 2006.217.08:19:51.22#ibcon#about to read 5, iclass 30, count 0 2006.217.08:19:51.22#ibcon#read 5, iclass 30, count 0 2006.217.08:19:51.22#ibcon#about to read 6, iclass 30, count 0 2006.217.08:19:51.22#ibcon#read 6, iclass 30, count 0 2006.217.08:19:51.22#ibcon#end of sib2, iclass 30, count 0 2006.217.08:19:51.22#ibcon#*after write, iclass 30, count 0 2006.217.08:19:51.22#ibcon#*before return 0, iclass 30, count 0 2006.217.08:19:51.22#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.217.08:19:51.22#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.217.08:19:51.22#ibcon#about to clear, iclass 30 cls_cnt 0 2006.217.08:19:51.22#ibcon#cleared, iclass 30 cls_cnt 0 2006.217.08:19:51.22$vc4f8/vblo=3,656.99 2006.217.08:19:51.22#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.217.08:19:51.22#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.217.08:19:51.22#ibcon#ireg 17 cls_cnt 0 2006.217.08:19:51.22#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.217.08:19:51.22#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.217.08:19:51.22#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.217.08:19:51.22#ibcon#enter wrdev, iclass 32, count 0 2006.217.08:19:51.22#ibcon#first serial, iclass 32, count 0 2006.217.08:19:51.22#ibcon#enter sib2, iclass 32, count 0 2006.217.08:19:51.22#ibcon#flushed, iclass 32, count 0 2006.217.08:19:51.22#ibcon#about to write, iclass 32, count 0 2006.217.08:19:51.22#ibcon#wrote, iclass 32, count 0 2006.217.08:19:51.22#ibcon#about to read 3, iclass 32, count 0 2006.217.08:19:51.24#ibcon#read 3, iclass 32, count 0 2006.217.08:19:51.24#ibcon#about to read 4, iclass 32, count 0 2006.217.08:19:51.24#ibcon#read 4, iclass 32, count 0 2006.217.08:19:51.24#ibcon#about to read 5, iclass 32, count 0 2006.217.08:19:51.24#ibcon#read 5, iclass 32, count 0 2006.217.08:19:51.24#ibcon#about to read 6, iclass 32, count 0 2006.217.08:19:51.24#ibcon#read 6, iclass 32, count 0 2006.217.08:19:51.24#ibcon#end of sib2, iclass 32, count 0 2006.217.08:19:51.24#ibcon#*mode == 0, iclass 32, count 0 2006.217.08:19:51.24#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.217.08:19:51.24#ibcon#[28=FRQ=03,656.99\r\n] 2006.217.08:19:51.24#ibcon#*before write, iclass 32, count 0 2006.217.08:19:51.24#ibcon#enter sib2, iclass 32, count 0 2006.217.08:19:51.24#ibcon#flushed, iclass 32, count 0 2006.217.08:19:51.24#ibcon#about to write, iclass 32, count 0 2006.217.08:19:51.24#ibcon#wrote, iclass 32, count 0 2006.217.08:19:51.24#ibcon#about to read 3, iclass 32, count 0 2006.217.08:19:51.28#ibcon#read 3, iclass 32, count 0 2006.217.08:19:51.28#ibcon#about to read 4, iclass 32, count 0 2006.217.08:19:51.28#ibcon#read 4, iclass 32, count 0 2006.217.08:19:51.28#ibcon#about to read 5, iclass 32, count 0 2006.217.08:19:51.28#ibcon#read 5, iclass 32, count 0 2006.217.08:19:51.28#ibcon#about to read 6, iclass 32, count 0 2006.217.08:19:51.28#ibcon#read 6, iclass 32, count 0 2006.217.08:19:51.28#ibcon#end of sib2, iclass 32, count 0 2006.217.08:19:51.28#ibcon#*after write, iclass 32, count 0 2006.217.08:19:51.28#ibcon#*before return 0, iclass 32, count 0 2006.217.08:19:51.28#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.217.08:19:51.28#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.217.08:19:51.28#ibcon#about to clear, iclass 32 cls_cnt 0 2006.217.08:19:51.28#ibcon#cleared, iclass 32 cls_cnt 0 2006.217.08:19:51.28$vc4f8/vb=3,4 2006.217.08:19:51.28#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.217.08:19:51.28#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.217.08:19:51.28#ibcon#ireg 11 cls_cnt 2 2006.217.08:19:51.28#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.217.08:19:51.34#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.217.08:19:51.34#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.217.08:19:51.34#ibcon#enter wrdev, iclass 34, count 2 2006.217.08:19:51.34#ibcon#first serial, iclass 34, count 2 2006.217.08:19:51.34#ibcon#enter sib2, iclass 34, count 2 2006.217.08:19:51.34#ibcon#flushed, iclass 34, count 2 2006.217.08:19:51.34#ibcon#about to write, iclass 34, count 2 2006.217.08:19:51.34#ibcon#wrote, iclass 34, count 2 2006.217.08:19:51.34#ibcon#about to read 3, iclass 34, count 2 2006.217.08:19:51.36#ibcon#read 3, iclass 34, count 2 2006.217.08:19:51.36#ibcon#about to read 4, iclass 34, count 2 2006.217.08:19:51.36#ibcon#read 4, iclass 34, count 2 2006.217.08:19:51.36#ibcon#about to read 5, iclass 34, count 2 2006.217.08:19:51.36#ibcon#read 5, iclass 34, count 2 2006.217.08:19:51.36#ibcon#about to read 6, iclass 34, count 2 2006.217.08:19:51.36#ibcon#read 6, iclass 34, count 2 2006.217.08:19:51.36#ibcon#end of sib2, iclass 34, count 2 2006.217.08:19:51.36#ibcon#*mode == 0, iclass 34, count 2 2006.217.08:19:51.36#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.217.08:19:51.36#ibcon#[27=AT03-04\r\n] 2006.217.08:19:51.36#ibcon#*before write, iclass 34, count 2 2006.217.08:19:51.36#ibcon#enter sib2, iclass 34, count 2 2006.217.08:19:51.36#ibcon#flushed, iclass 34, count 2 2006.217.08:19:51.36#ibcon#about to write, iclass 34, count 2 2006.217.08:19:51.36#ibcon#wrote, iclass 34, count 2 2006.217.08:19:51.36#ibcon#about to read 3, iclass 34, count 2 2006.217.08:19:51.39#ibcon#read 3, iclass 34, count 2 2006.217.08:19:51.39#ibcon#about to read 4, iclass 34, count 2 2006.217.08:19:51.39#ibcon#read 4, iclass 34, count 2 2006.217.08:19:51.39#ibcon#about to read 5, iclass 34, count 2 2006.217.08:19:51.39#ibcon#read 5, iclass 34, count 2 2006.217.08:19:51.39#ibcon#about to read 6, iclass 34, count 2 2006.217.08:19:51.39#ibcon#read 6, iclass 34, count 2 2006.217.08:19:51.39#ibcon#end of sib2, iclass 34, count 2 2006.217.08:19:51.39#ibcon#*after write, iclass 34, count 2 2006.217.08:19:51.39#ibcon#*before return 0, iclass 34, count 2 2006.217.08:19:51.39#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.217.08:19:51.39#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.217.08:19:51.39#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.217.08:19:51.39#ibcon#ireg 7 cls_cnt 0 2006.217.08:19:51.39#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.217.08:19:51.51#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.217.08:19:51.51#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.217.08:19:51.51#ibcon#enter wrdev, iclass 34, count 0 2006.217.08:19:51.51#ibcon#first serial, iclass 34, count 0 2006.217.08:19:51.51#ibcon#enter sib2, iclass 34, count 0 2006.217.08:19:51.51#ibcon#flushed, iclass 34, count 0 2006.217.08:19:51.51#ibcon#about to write, iclass 34, count 0 2006.217.08:19:51.51#ibcon#wrote, iclass 34, count 0 2006.217.08:19:51.51#ibcon#about to read 3, iclass 34, count 0 2006.217.08:19:51.53#ibcon#read 3, iclass 34, count 0 2006.217.08:19:51.53#ibcon#about to read 4, iclass 34, count 0 2006.217.08:19:51.53#ibcon#read 4, iclass 34, count 0 2006.217.08:19:51.53#ibcon#about to read 5, iclass 34, count 0 2006.217.08:19:51.53#ibcon#read 5, iclass 34, count 0 2006.217.08:19:51.53#ibcon#about to read 6, iclass 34, count 0 2006.217.08:19:51.53#ibcon#read 6, iclass 34, count 0 2006.217.08:19:51.53#ibcon#end of sib2, iclass 34, count 0 2006.217.08:19:51.53#ibcon#*mode == 0, iclass 34, count 0 2006.217.08:19:51.53#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.217.08:19:51.53#ibcon#[27=USB\r\n] 2006.217.08:19:51.53#ibcon#*before write, iclass 34, count 0 2006.217.08:19:51.53#ibcon#enter sib2, iclass 34, count 0 2006.217.08:19:51.53#ibcon#flushed, iclass 34, count 0 2006.217.08:19:51.53#ibcon#about to write, iclass 34, count 0 2006.217.08:19:51.53#ibcon#wrote, iclass 34, count 0 2006.217.08:19:51.53#ibcon#about to read 3, iclass 34, count 0 2006.217.08:19:51.56#ibcon#read 3, iclass 34, count 0 2006.217.08:19:51.56#ibcon#about to read 4, iclass 34, count 0 2006.217.08:19:51.56#ibcon#read 4, iclass 34, count 0 2006.217.08:19:51.56#ibcon#about to read 5, iclass 34, count 0 2006.217.08:19:51.56#ibcon#read 5, iclass 34, count 0 2006.217.08:19:51.56#ibcon#about to read 6, iclass 34, count 0 2006.217.08:19:51.56#ibcon#read 6, iclass 34, count 0 2006.217.08:19:51.56#ibcon#end of sib2, iclass 34, count 0 2006.217.08:19:51.56#ibcon#*after write, iclass 34, count 0 2006.217.08:19:51.56#ibcon#*before return 0, iclass 34, count 0 2006.217.08:19:51.56#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.217.08:19:51.56#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.217.08:19:51.56#ibcon#about to clear, iclass 34 cls_cnt 0 2006.217.08:19:51.56#ibcon#cleared, iclass 34 cls_cnt 0 2006.217.08:19:51.56$vc4f8/vblo=4,712.99 2006.217.08:19:51.56#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.217.08:19:51.56#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.217.08:19:51.56#ibcon#ireg 17 cls_cnt 0 2006.217.08:19:51.56#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.217.08:19:51.56#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.217.08:19:51.56#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.217.08:19:51.56#ibcon#enter wrdev, iclass 36, count 0 2006.217.08:19:51.56#ibcon#first serial, iclass 36, count 0 2006.217.08:19:51.56#ibcon#enter sib2, iclass 36, count 0 2006.217.08:19:51.56#ibcon#flushed, iclass 36, count 0 2006.217.08:19:51.56#ibcon#about to write, iclass 36, count 0 2006.217.08:19:51.56#ibcon#wrote, iclass 36, count 0 2006.217.08:19:51.56#ibcon#about to read 3, iclass 36, count 0 2006.217.08:19:51.58#ibcon#read 3, iclass 36, count 0 2006.217.08:19:51.58#ibcon#about to read 4, iclass 36, count 0 2006.217.08:19:51.58#ibcon#read 4, iclass 36, count 0 2006.217.08:19:51.58#ibcon#about to read 5, iclass 36, count 0 2006.217.08:19:51.58#ibcon#read 5, iclass 36, count 0 2006.217.08:19:51.58#ibcon#about to read 6, iclass 36, count 0 2006.217.08:19:51.58#ibcon#read 6, iclass 36, count 0 2006.217.08:19:51.58#ibcon#end of sib2, iclass 36, count 0 2006.217.08:19:51.58#ibcon#*mode == 0, iclass 36, count 0 2006.217.08:19:51.58#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.217.08:19:51.58#ibcon#[28=FRQ=04,712.99\r\n] 2006.217.08:19:51.58#ibcon#*before write, iclass 36, count 0 2006.217.08:19:51.58#ibcon#enter sib2, iclass 36, count 0 2006.217.08:19:51.58#ibcon#flushed, iclass 36, count 0 2006.217.08:19:51.58#ibcon#about to write, iclass 36, count 0 2006.217.08:19:51.58#ibcon#wrote, iclass 36, count 0 2006.217.08:19:51.58#ibcon#about to read 3, iclass 36, count 0 2006.217.08:19:51.62#ibcon#read 3, iclass 36, count 0 2006.217.08:19:51.62#ibcon#about to read 4, iclass 36, count 0 2006.217.08:19:51.62#ibcon#read 4, iclass 36, count 0 2006.217.08:19:51.62#ibcon#about to read 5, iclass 36, count 0 2006.217.08:19:51.62#ibcon#read 5, iclass 36, count 0 2006.217.08:19:51.62#ibcon#about to read 6, iclass 36, count 0 2006.217.08:19:51.62#ibcon#read 6, iclass 36, count 0 2006.217.08:19:51.62#ibcon#end of sib2, iclass 36, count 0 2006.217.08:19:51.62#ibcon#*after write, iclass 36, count 0 2006.217.08:19:51.62#ibcon#*before return 0, iclass 36, count 0 2006.217.08:19:51.62#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.217.08:19:51.62#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.217.08:19:51.62#ibcon#about to clear, iclass 36 cls_cnt 0 2006.217.08:19:51.62#ibcon#cleared, iclass 36 cls_cnt 0 2006.217.08:19:51.62$vc4f8/vb=4,4 2006.217.08:19:51.62#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.217.08:19:51.62#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.217.08:19:51.62#ibcon#ireg 11 cls_cnt 2 2006.217.08:19:51.62#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.217.08:19:51.68#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.217.08:19:51.68#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.217.08:19:51.68#ibcon#enter wrdev, iclass 38, count 2 2006.217.08:19:51.68#ibcon#first serial, iclass 38, count 2 2006.217.08:19:51.68#ibcon#enter sib2, iclass 38, count 2 2006.217.08:19:51.68#ibcon#flushed, iclass 38, count 2 2006.217.08:19:51.68#ibcon#about to write, iclass 38, count 2 2006.217.08:19:51.68#ibcon#wrote, iclass 38, count 2 2006.217.08:19:51.68#ibcon#about to read 3, iclass 38, count 2 2006.217.08:19:51.70#ibcon#read 3, iclass 38, count 2 2006.217.08:19:51.70#ibcon#about to read 4, iclass 38, count 2 2006.217.08:19:51.70#ibcon#read 4, iclass 38, count 2 2006.217.08:19:51.70#ibcon#about to read 5, iclass 38, count 2 2006.217.08:19:51.70#ibcon#read 5, iclass 38, count 2 2006.217.08:19:51.70#ibcon#about to read 6, iclass 38, count 2 2006.217.08:19:51.70#ibcon#read 6, iclass 38, count 2 2006.217.08:19:51.70#ibcon#end of sib2, iclass 38, count 2 2006.217.08:19:51.70#ibcon#*mode == 0, iclass 38, count 2 2006.217.08:19:51.70#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.217.08:19:51.70#ibcon#[27=AT04-04\r\n] 2006.217.08:19:51.70#ibcon#*before write, iclass 38, count 2 2006.217.08:19:51.70#ibcon#enter sib2, iclass 38, count 2 2006.217.08:19:51.70#ibcon#flushed, iclass 38, count 2 2006.217.08:19:51.70#ibcon#about to write, iclass 38, count 2 2006.217.08:19:51.70#ibcon#wrote, iclass 38, count 2 2006.217.08:19:51.70#ibcon#about to read 3, iclass 38, count 2 2006.217.08:19:51.73#ibcon#read 3, iclass 38, count 2 2006.217.08:19:51.73#ibcon#about to read 4, iclass 38, count 2 2006.217.08:19:51.73#ibcon#read 4, iclass 38, count 2 2006.217.08:19:51.73#ibcon#about to read 5, iclass 38, count 2 2006.217.08:19:51.73#ibcon#read 5, iclass 38, count 2 2006.217.08:19:51.73#ibcon#about to read 6, iclass 38, count 2 2006.217.08:19:51.73#ibcon#read 6, iclass 38, count 2 2006.217.08:19:51.73#ibcon#end of sib2, iclass 38, count 2 2006.217.08:19:51.73#ibcon#*after write, iclass 38, count 2 2006.217.08:19:51.73#ibcon#*before return 0, iclass 38, count 2 2006.217.08:19:51.73#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.217.08:19:51.73#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.217.08:19:51.73#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.217.08:19:51.73#ibcon#ireg 7 cls_cnt 0 2006.217.08:19:51.73#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.217.08:19:51.85#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.217.08:19:51.85#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.217.08:19:51.85#ibcon#enter wrdev, iclass 38, count 0 2006.217.08:19:51.85#ibcon#first serial, iclass 38, count 0 2006.217.08:19:51.85#ibcon#enter sib2, iclass 38, count 0 2006.217.08:19:51.85#ibcon#flushed, iclass 38, count 0 2006.217.08:19:51.85#ibcon#about to write, iclass 38, count 0 2006.217.08:19:51.85#ibcon#wrote, iclass 38, count 0 2006.217.08:19:51.85#ibcon#about to read 3, iclass 38, count 0 2006.217.08:19:51.87#ibcon#read 3, iclass 38, count 0 2006.217.08:19:51.87#ibcon#about to read 4, iclass 38, count 0 2006.217.08:19:51.87#ibcon#read 4, iclass 38, count 0 2006.217.08:19:51.87#ibcon#about to read 5, iclass 38, count 0 2006.217.08:19:51.87#ibcon#read 5, iclass 38, count 0 2006.217.08:19:51.87#ibcon#about to read 6, iclass 38, count 0 2006.217.08:19:51.87#ibcon#read 6, iclass 38, count 0 2006.217.08:19:51.87#ibcon#end of sib2, iclass 38, count 0 2006.217.08:19:51.87#ibcon#*mode == 0, iclass 38, count 0 2006.217.08:19:51.87#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.217.08:19:51.87#ibcon#[27=USB\r\n] 2006.217.08:19:51.87#ibcon#*before write, iclass 38, count 0 2006.217.08:19:51.87#ibcon#enter sib2, iclass 38, count 0 2006.217.08:19:51.87#ibcon#flushed, iclass 38, count 0 2006.217.08:19:51.87#ibcon#about to write, iclass 38, count 0 2006.217.08:19:51.87#ibcon#wrote, iclass 38, count 0 2006.217.08:19:51.87#ibcon#about to read 3, iclass 38, count 0 2006.217.08:19:51.90#ibcon#read 3, iclass 38, count 0 2006.217.08:19:51.90#ibcon#about to read 4, iclass 38, count 0 2006.217.08:19:51.90#ibcon#read 4, iclass 38, count 0 2006.217.08:19:51.90#ibcon#about to read 5, iclass 38, count 0 2006.217.08:19:51.90#ibcon#read 5, iclass 38, count 0 2006.217.08:19:51.90#ibcon#about to read 6, iclass 38, count 0 2006.217.08:19:51.90#ibcon#read 6, iclass 38, count 0 2006.217.08:19:51.90#ibcon#end of sib2, iclass 38, count 0 2006.217.08:19:51.90#ibcon#*after write, iclass 38, count 0 2006.217.08:19:51.90#ibcon#*before return 0, iclass 38, count 0 2006.217.08:19:51.90#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.217.08:19:51.90#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.217.08:19:51.90#ibcon#about to clear, iclass 38 cls_cnt 0 2006.217.08:19:51.90#ibcon#cleared, iclass 38 cls_cnt 0 2006.217.08:19:51.90$vc4f8/vblo=5,744.99 2006.217.08:19:51.90#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.217.08:19:51.90#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.217.08:19:51.90#ibcon#ireg 17 cls_cnt 0 2006.217.08:19:51.90#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.217.08:19:51.90#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.217.08:19:51.90#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.217.08:19:51.90#ibcon#enter wrdev, iclass 40, count 0 2006.217.08:19:51.90#ibcon#first serial, iclass 40, count 0 2006.217.08:19:51.90#ibcon#enter sib2, iclass 40, count 0 2006.217.08:19:51.90#ibcon#flushed, iclass 40, count 0 2006.217.08:19:51.90#ibcon#about to write, iclass 40, count 0 2006.217.08:19:51.90#ibcon#wrote, iclass 40, count 0 2006.217.08:19:51.90#ibcon#about to read 3, iclass 40, count 0 2006.217.08:19:51.92#ibcon#read 3, iclass 40, count 0 2006.217.08:19:51.92#ibcon#about to read 4, iclass 40, count 0 2006.217.08:19:51.92#ibcon#read 4, iclass 40, count 0 2006.217.08:19:51.92#ibcon#about to read 5, iclass 40, count 0 2006.217.08:19:51.92#ibcon#read 5, iclass 40, count 0 2006.217.08:19:51.92#ibcon#about to read 6, iclass 40, count 0 2006.217.08:19:51.92#ibcon#read 6, iclass 40, count 0 2006.217.08:19:51.92#ibcon#end of sib2, iclass 40, count 0 2006.217.08:19:51.92#ibcon#*mode == 0, iclass 40, count 0 2006.217.08:19:51.92#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.217.08:19:51.92#ibcon#[28=FRQ=05,744.99\r\n] 2006.217.08:19:51.92#ibcon#*before write, iclass 40, count 0 2006.217.08:19:51.92#ibcon#enter sib2, iclass 40, count 0 2006.217.08:19:51.92#ibcon#flushed, iclass 40, count 0 2006.217.08:19:51.92#ibcon#about to write, iclass 40, count 0 2006.217.08:19:51.92#ibcon#wrote, iclass 40, count 0 2006.217.08:19:51.92#ibcon#about to read 3, iclass 40, count 0 2006.217.08:19:51.96#ibcon#read 3, iclass 40, count 0 2006.217.08:19:51.96#ibcon#about to read 4, iclass 40, count 0 2006.217.08:19:51.96#ibcon#read 4, iclass 40, count 0 2006.217.08:19:51.96#ibcon#about to read 5, iclass 40, count 0 2006.217.08:19:51.96#ibcon#read 5, iclass 40, count 0 2006.217.08:19:51.96#ibcon#about to read 6, iclass 40, count 0 2006.217.08:19:51.96#ibcon#read 6, iclass 40, count 0 2006.217.08:19:51.96#ibcon#end of sib2, iclass 40, count 0 2006.217.08:19:51.96#ibcon#*after write, iclass 40, count 0 2006.217.08:19:51.96#ibcon#*before return 0, iclass 40, count 0 2006.217.08:19:51.96#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.217.08:19:51.96#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.217.08:19:51.96#ibcon#about to clear, iclass 40 cls_cnt 0 2006.217.08:19:51.96#ibcon#cleared, iclass 40 cls_cnt 0 2006.217.08:19:51.96$vc4f8/vb=5,4 2006.217.08:19:51.96#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.217.08:19:51.96#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.217.08:19:51.96#ibcon#ireg 11 cls_cnt 2 2006.217.08:19:51.96#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.217.08:19:52.02#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.217.08:19:52.02#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.217.08:19:52.02#ibcon#enter wrdev, iclass 4, count 2 2006.217.08:19:52.02#ibcon#first serial, iclass 4, count 2 2006.217.08:19:52.02#ibcon#enter sib2, iclass 4, count 2 2006.217.08:19:52.02#ibcon#flushed, iclass 4, count 2 2006.217.08:19:52.02#ibcon#about to write, iclass 4, count 2 2006.217.08:19:52.02#ibcon#wrote, iclass 4, count 2 2006.217.08:19:52.02#ibcon#about to read 3, iclass 4, count 2 2006.217.08:19:52.04#ibcon#read 3, iclass 4, count 2 2006.217.08:19:52.04#ibcon#about to read 4, iclass 4, count 2 2006.217.08:19:52.04#ibcon#read 4, iclass 4, count 2 2006.217.08:19:52.04#ibcon#about to read 5, iclass 4, count 2 2006.217.08:19:52.04#ibcon#read 5, iclass 4, count 2 2006.217.08:19:52.04#ibcon#about to read 6, iclass 4, count 2 2006.217.08:19:52.04#ibcon#read 6, iclass 4, count 2 2006.217.08:19:52.04#ibcon#end of sib2, iclass 4, count 2 2006.217.08:19:52.04#ibcon#*mode == 0, iclass 4, count 2 2006.217.08:19:52.04#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.217.08:19:52.04#ibcon#[27=AT05-04\r\n] 2006.217.08:19:52.04#ibcon#*before write, iclass 4, count 2 2006.217.08:19:52.04#ibcon#enter sib2, iclass 4, count 2 2006.217.08:19:52.04#ibcon#flushed, iclass 4, count 2 2006.217.08:19:52.04#ibcon#about to write, iclass 4, count 2 2006.217.08:19:52.04#ibcon#wrote, iclass 4, count 2 2006.217.08:19:52.04#ibcon#about to read 3, iclass 4, count 2 2006.217.08:19:52.07#ibcon#read 3, iclass 4, count 2 2006.217.08:19:52.07#ibcon#about to read 4, iclass 4, count 2 2006.217.08:19:52.07#ibcon#read 4, iclass 4, count 2 2006.217.08:19:52.07#ibcon#about to read 5, iclass 4, count 2 2006.217.08:19:52.07#ibcon#read 5, iclass 4, count 2 2006.217.08:19:52.07#ibcon#about to read 6, iclass 4, count 2 2006.217.08:19:52.07#ibcon#read 6, iclass 4, count 2 2006.217.08:19:52.07#ibcon#end of sib2, iclass 4, count 2 2006.217.08:19:52.07#ibcon#*after write, iclass 4, count 2 2006.217.08:19:52.07#ibcon#*before return 0, iclass 4, count 2 2006.217.08:19:52.07#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.217.08:19:52.07#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.217.08:19:52.07#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.217.08:19:52.07#ibcon#ireg 7 cls_cnt 0 2006.217.08:19:52.07#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.217.08:19:52.19#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.217.08:19:52.19#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.217.08:19:52.19#ibcon#enter wrdev, iclass 4, count 0 2006.217.08:19:52.19#ibcon#first serial, iclass 4, count 0 2006.217.08:19:52.19#ibcon#enter sib2, iclass 4, count 0 2006.217.08:19:52.19#ibcon#flushed, iclass 4, count 0 2006.217.08:19:52.19#ibcon#about to write, iclass 4, count 0 2006.217.08:19:52.19#ibcon#wrote, iclass 4, count 0 2006.217.08:19:52.19#ibcon#about to read 3, iclass 4, count 0 2006.217.08:19:52.21#ibcon#read 3, iclass 4, count 0 2006.217.08:19:52.21#ibcon#about to read 4, iclass 4, count 0 2006.217.08:19:52.21#ibcon#read 4, iclass 4, count 0 2006.217.08:19:52.21#ibcon#about to read 5, iclass 4, count 0 2006.217.08:19:52.21#ibcon#read 5, iclass 4, count 0 2006.217.08:19:52.21#ibcon#about to read 6, iclass 4, count 0 2006.217.08:19:52.21#ibcon#read 6, iclass 4, count 0 2006.217.08:19:52.21#ibcon#end of sib2, iclass 4, count 0 2006.217.08:19:52.21#ibcon#*mode == 0, iclass 4, count 0 2006.217.08:19:52.21#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.217.08:19:52.21#ibcon#[27=USB\r\n] 2006.217.08:19:52.21#ibcon#*before write, iclass 4, count 0 2006.217.08:19:52.21#ibcon#enter sib2, iclass 4, count 0 2006.217.08:19:52.21#ibcon#flushed, iclass 4, count 0 2006.217.08:19:52.21#ibcon#about to write, iclass 4, count 0 2006.217.08:19:52.21#ibcon#wrote, iclass 4, count 0 2006.217.08:19:52.21#ibcon#about to read 3, iclass 4, count 0 2006.217.08:19:52.24#ibcon#read 3, iclass 4, count 0 2006.217.08:19:52.24#ibcon#about to read 4, iclass 4, count 0 2006.217.08:19:52.24#ibcon#read 4, iclass 4, count 0 2006.217.08:19:52.24#ibcon#about to read 5, iclass 4, count 0 2006.217.08:19:52.24#ibcon#read 5, iclass 4, count 0 2006.217.08:19:52.24#ibcon#about to read 6, iclass 4, count 0 2006.217.08:19:52.24#ibcon#read 6, iclass 4, count 0 2006.217.08:19:52.24#ibcon#end of sib2, iclass 4, count 0 2006.217.08:19:52.24#ibcon#*after write, iclass 4, count 0 2006.217.08:19:52.24#ibcon#*before return 0, iclass 4, count 0 2006.217.08:19:52.24#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.217.08:19:52.24#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.217.08:19:52.24#ibcon#about to clear, iclass 4 cls_cnt 0 2006.217.08:19:52.24#ibcon#cleared, iclass 4 cls_cnt 0 2006.217.08:19:52.24$vc4f8/vblo=6,752.99 2006.217.08:19:52.24#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.217.08:19:52.24#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.217.08:19:52.24#ibcon#ireg 17 cls_cnt 0 2006.217.08:19:52.24#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.217.08:19:52.24#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.217.08:19:52.24#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.217.08:19:52.24#ibcon#enter wrdev, iclass 6, count 0 2006.217.08:19:52.24#ibcon#first serial, iclass 6, count 0 2006.217.08:19:52.24#ibcon#enter sib2, iclass 6, count 0 2006.217.08:19:52.24#ibcon#flushed, iclass 6, count 0 2006.217.08:19:52.24#ibcon#about to write, iclass 6, count 0 2006.217.08:19:52.24#ibcon#wrote, iclass 6, count 0 2006.217.08:19:52.24#ibcon#about to read 3, iclass 6, count 0 2006.217.08:19:52.26#ibcon#read 3, iclass 6, count 0 2006.217.08:19:52.26#ibcon#about to read 4, iclass 6, count 0 2006.217.08:19:52.26#ibcon#read 4, iclass 6, count 0 2006.217.08:19:52.26#ibcon#about to read 5, iclass 6, count 0 2006.217.08:19:52.26#ibcon#read 5, iclass 6, count 0 2006.217.08:19:52.26#ibcon#about to read 6, iclass 6, count 0 2006.217.08:19:52.26#ibcon#read 6, iclass 6, count 0 2006.217.08:19:52.26#ibcon#end of sib2, iclass 6, count 0 2006.217.08:19:52.26#ibcon#*mode == 0, iclass 6, count 0 2006.217.08:19:52.26#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.217.08:19:52.26#ibcon#[28=FRQ=06,752.99\r\n] 2006.217.08:19:52.26#ibcon#*before write, iclass 6, count 0 2006.217.08:19:52.26#ibcon#enter sib2, iclass 6, count 0 2006.217.08:19:52.26#ibcon#flushed, iclass 6, count 0 2006.217.08:19:52.26#ibcon#about to write, iclass 6, count 0 2006.217.08:19:52.26#ibcon#wrote, iclass 6, count 0 2006.217.08:19:52.26#ibcon#about to read 3, iclass 6, count 0 2006.217.08:19:52.30#ibcon#read 3, iclass 6, count 0 2006.217.08:19:52.30#ibcon#about to read 4, iclass 6, count 0 2006.217.08:19:52.30#ibcon#read 4, iclass 6, count 0 2006.217.08:19:52.30#ibcon#about to read 5, iclass 6, count 0 2006.217.08:19:52.30#ibcon#read 5, iclass 6, count 0 2006.217.08:19:52.30#ibcon#about to read 6, iclass 6, count 0 2006.217.08:19:52.30#ibcon#read 6, iclass 6, count 0 2006.217.08:19:52.30#ibcon#end of sib2, iclass 6, count 0 2006.217.08:19:52.30#ibcon#*after write, iclass 6, count 0 2006.217.08:19:52.30#ibcon#*before return 0, iclass 6, count 0 2006.217.08:19:52.30#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.217.08:19:52.30#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.217.08:19:52.30#ibcon#about to clear, iclass 6 cls_cnt 0 2006.217.08:19:52.30#ibcon#cleared, iclass 6 cls_cnt 0 2006.217.08:19:52.30$vc4f8/vb=6,4 2006.217.08:19:52.30#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.217.08:19:52.30#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.217.08:19:52.30#ibcon#ireg 11 cls_cnt 2 2006.217.08:19:52.30#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.217.08:19:52.36#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.217.08:19:52.36#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.217.08:19:52.36#ibcon#enter wrdev, iclass 10, count 2 2006.217.08:19:52.36#ibcon#first serial, iclass 10, count 2 2006.217.08:19:52.36#ibcon#enter sib2, iclass 10, count 2 2006.217.08:19:52.36#ibcon#flushed, iclass 10, count 2 2006.217.08:19:52.36#ibcon#about to write, iclass 10, count 2 2006.217.08:19:52.36#ibcon#wrote, iclass 10, count 2 2006.217.08:19:52.36#ibcon#about to read 3, iclass 10, count 2 2006.217.08:19:52.38#ibcon#read 3, iclass 10, count 2 2006.217.08:19:52.38#ibcon#about to read 4, iclass 10, count 2 2006.217.08:19:52.38#ibcon#read 4, iclass 10, count 2 2006.217.08:19:52.38#ibcon#about to read 5, iclass 10, count 2 2006.217.08:19:52.38#ibcon#read 5, iclass 10, count 2 2006.217.08:19:52.38#ibcon#about to read 6, iclass 10, count 2 2006.217.08:19:52.38#ibcon#read 6, iclass 10, count 2 2006.217.08:19:52.38#ibcon#end of sib2, iclass 10, count 2 2006.217.08:19:52.38#ibcon#*mode == 0, iclass 10, count 2 2006.217.08:19:52.38#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.217.08:19:52.38#ibcon#[27=AT06-04\r\n] 2006.217.08:19:52.38#ibcon#*before write, iclass 10, count 2 2006.217.08:19:52.38#ibcon#enter sib2, iclass 10, count 2 2006.217.08:19:52.38#ibcon#flushed, iclass 10, count 2 2006.217.08:19:52.38#ibcon#about to write, iclass 10, count 2 2006.217.08:19:52.38#ibcon#wrote, iclass 10, count 2 2006.217.08:19:52.38#ibcon#about to read 3, iclass 10, count 2 2006.217.08:19:52.41#ibcon#read 3, iclass 10, count 2 2006.217.08:19:52.41#ibcon#about to read 4, iclass 10, count 2 2006.217.08:19:52.41#ibcon#read 4, iclass 10, count 2 2006.217.08:19:52.41#ibcon#about to read 5, iclass 10, count 2 2006.217.08:19:52.41#ibcon#read 5, iclass 10, count 2 2006.217.08:19:52.41#ibcon#about to read 6, iclass 10, count 2 2006.217.08:19:52.41#ibcon#read 6, iclass 10, count 2 2006.217.08:19:52.41#ibcon#end of sib2, iclass 10, count 2 2006.217.08:19:52.41#ibcon#*after write, iclass 10, count 2 2006.217.08:19:52.41#ibcon#*before return 0, iclass 10, count 2 2006.217.08:19:52.41#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.217.08:19:52.41#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.217.08:19:52.41#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.217.08:19:52.41#ibcon#ireg 7 cls_cnt 0 2006.217.08:19:52.41#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.217.08:19:52.53#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.217.08:19:52.53#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.217.08:19:52.53#ibcon#enter wrdev, iclass 10, count 0 2006.217.08:19:52.53#ibcon#first serial, iclass 10, count 0 2006.217.08:19:52.53#ibcon#enter sib2, iclass 10, count 0 2006.217.08:19:52.53#ibcon#flushed, iclass 10, count 0 2006.217.08:19:52.53#ibcon#about to write, iclass 10, count 0 2006.217.08:19:52.53#ibcon#wrote, iclass 10, count 0 2006.217.08:19:52.53#ibcon#about to read 3, iclass 10, count 0 2006.217.08:19:52.55#ibcon#read 3, iclass 10, count 0 2006.217.08:19:52.55#ibcon#about to read 4, iclass 10, count 0 2006.217.08:19:52.55#ibcon#read 4, iclass 10, count 0 2006.217.08:19:52.55#ibcon#about to read 5, iclass 10, count 0 2006.217.08:19:52.55#ibcon#read 5, iclass 10, count 0 2006.217.08:19:52.55#ibcon#about to read 6, iclass 10, count 0 2006.217.08:19:52.55#ibcon#read 6, iclass 10, count 0 2006.217.08:19:52.55#ibcon#end of sib2, iclass 10, count 0 2006.217.08:19:52.55#ibcon#*mode == 0, iclass 10, count 0 2006.217.08:19:52.55#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.217.08:19:52.55#ibcon#[27=USB\r\n] 2006.217.08:19:52.55#ibcon#*before write, iclass 10, count 0 2006.217.08:19:52.55#ibcon#enter sib2, iclass 10, count 0 2006.217.08:19:52.55#ibcon#flushed, iclass 10, count 0 2006.217.08:19:52.55#ibcon#about to write, iclass 10, count 0 2006.217.08:19:52.55#ibcon#wrote, iclass 10, count 0 2006.217.08:19:52.55#ibcon#about to read 3, iclass 10, count 0 2006.217.08:19:52.58#ibcon#read 3, iclass 10, count 0 2006.217.08:19:52.58#ibcon#about to read 4, iclass 10, count 0 2006.217.08:19:52.58#ibcon#read 4, iclass 10, count 0 2006.217.08:19:52.58#ibcon#about to read 5, iclass 10, count 0 2006.217.08:19:52.58#ibcon#read 5, iclass 10, count 0 2006.217.08:19:52.58#ibcon#about to read 6, iclass 10, count 0 2006.217.08:19:52.58#ibcon#read 6, iclass 10, count 0 2006.217.08:19:52.58#ibcon#end of sib2, iclass 10, count 0 2006.217.08:19:52.58#ibcon#*after write, iclass 10, count 0 2006.217.08:19:52.58#ibcon#*before return 0, iclass 10, count 0 2006.217.08:19:52.58#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.217.08:19:52.58#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.217.08:19:52.58#ibcon#about to clear, iclass 10 cls_cnt 0 2006.217.08:19:52.58#ibcon#cleared, iclass 10 cls_cnt 0 2006.217.08:19:52.58$vc4f8/vabw=wide 2006.217.08:19:52.58#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.217.08:19:52.58#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.217.08:19:52.58#ibcon#ireg 8 cls_cnt 0 2006.217.08:19:52.58#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.217.08:19:52.58#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.217.08:19:52.58#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.217.08:19:52.58#ibcon#enter wrdev, iclass 12, count 0 2006.217.08:19:52.58#ibcon#first serial, iclass 12, count 0 2006.217.08:19:52.58#ibcon#enter sib2, iclass 12, count 0 2006.217.08:19:52.58#ibcon#flushed, iclass 12, count 0 2006.217.08:19:52.58#ibcon#about to write, iclass 12, count 0 2006.217.08:19:52.58#ibcon#wrote, iclass 12, count 0 2006.217.08:19:52.58#ibcon#about to read 3, iclass 12, count 0 2006.217.08:19:52.60#ibcon#read 3, iclass 12, count 0 2006.217.08:19:52.60#ibcon#about to read 4, iclass 12, count 0 2006.217.08:19:52.60#ibcon#read 4, iclass 12, count 0 2006.217.08:19:52.60#ibcon#about to read 5, iclass 12, count 0 2006.217.08:19:52.60#ibcon#read 5, iclass 12, count 0 2006.217.08:19:52.60#ibcon#about to read 6, iclass 12, count 0 2006.217.08:19:52.60#ibcon#read 6, iclass 12, count 0 2006.217.08:19:52.60#ibcon#end of sib2, iclass 12, count 0 2006.217.08:19:52.60#ibcon#*mode == 0, iclass 12, count 0 2006.217.08:19:52.60#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.217.08:19:52.60#ibcon#[25=BW32\r\n] 2006.217.08:19:52.60#ibcon#*before write, iclass 12, count 0 2006.217.08:19:52.60#ibcon#enter sib2, iclass 12, count 0 2006.217.08:19:52.60#ibcon#flushed, iclass 12, count 0 2006.217.08:19:52.60#ibcon#about to write, iclass 12, count 0 2006.217.08:19:52.60#ibcon#wrote, iclass 12, count 0 2006.217.08:19:52.60#ibcon#about to read 3, iclass 12, count 0 2006.217.08:19:52.63#ibcon#read 3, iclass 12, count 0 2006.217.08:19:52.63#ibcon#about to read 4, iclass 12, count 0 2006.217.08:19:52.63#ibcon#read 4, iclass 12, count 0 2006.217.08:19:52.63#ibcon#about to read 5, iclass 12, count 0 2006.217.08:19:52.63#ibcon#read 5, iclass 12, count 0 2006.217.08:19:52.63#ibcon#about to read 6, iclass 12, count 0 2006.217.08:19:52.63#ibcon#read 6, iclass 12, count 0 2006.217.08:19:52.63#ibcon#end of sib2, iclass 12, count 0 2006.217.08:19:52.63#ibcon#*after write, iclass 12, count 0 2006.217.08:19:52.63#ibcon#*before return 0, iclass 12, count 0 2006.217.08:19:52.63#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.217.08:19:52.63#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.217.08:19:52.63#ibcon#about to clear, iclass 12 cls_cnt 0 2006.217.08:19:52.63#ibcon#cleared, iclass 12 cls_cnt 0 2006.217.08:19:52.63$vc4f8/vbbw=wide 2006.217.08:19:52.63#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.217.08:19:52.63#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.217.08:19:52.63#ibcon#ireg 8 cls_cnt 0 2006.217.08:19:52.63#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.217.08:19:52.70#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.217.08:19:52.70#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.217.08:19:52.70#ibcon#enter wrdev, iclass 14, count 0 2006.217.08:19:52.70#ibcon#first serial, iclass 14, count 0 2006.217.08:19:52.70#ibcon#enter sib2, iclass 14, count 0 2006.217.08:19:52.70#ibcon#flushed, iclass 14, count 0 2006.217.08:19:52.70#ibcon#about to write, iclass 14, count 0 2006.217.08:19:52.70#ibcon#wrote, iclass 14, count 0 2006.217.08:19:52.70#ibcon#about to read 3, iclass 14, count 0 2006.217.08:19:52.72#ibcon#read 3, iclass 14, count 0 2006.217.08:19:52.72#ibcon#about to read 4, iclass 14, count 0 2006.217.08:19:52.72#ibcon#read 4, iclass 14, count 0 2006.217.08:19:52.72#ibcon#about to read 5, iclass 14, count 0 2006.217.08:19:52.72#ibcon#read 5, iclass 14, count 0 2006.217.08:19:52.72#ibcon#about to read 6, iclass 14, count 0 2006.217.08:19:52.72#ibcon#read 6, iclass 14, count 0 2006.217.08:19:52.72#ibcon#end of sib2, iclass 14, count 0 2006.217.08:19:52.72#ibcon#*mode == 0, iclass 14, count 0 2006.217.08:19:52.72#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.217.08:19:52.72#ibcon#[27=BW32\r\n] 2006.217.08:19:52.72#ibcon#*before write, iclass 14, count 0 2006.217.08:19:52.72#ibcon#enter sib2, iclass 14, count 0 2006.217.08:19:52.72#ibcon#flushed, iclass 14, count 0 2006.217.08:19:52.72#ibcon#about to write, iclass 14, count 0 2006.217.08:19:52.72#ibcon#wrote, iclass 14, count 0 2006.217.08:19:52.72#ibcon#about to read 3, iclass 14, count 0 2006.217.08:19:52.75#ibcon#read 3, iclass 14, count 0 2006.217.08:19:52.75#ibcon#about to read 4, iclass 14, count 0 2006.217.08:19:52.75#ibcon#read 4, iclass 14, count 0 2006.217.08:19:52.75#ibcon#about to read 5, iclass 14, count 0 2006.217.08:19:52.75#ibcon#read 5, iclass 14, count 0 2006.217.08:19:52.75#ibcon#about to read 6, iclass 14, count 0 2006.217.08:19:52.75#ibcon#read 6, iclass 14, count 0 2006.217.08:19:52.75#ibcon#end of sib2, iclass 14, count 0 2006.217.08:19:52.75#ibcon#*after write, iclass 14, count 0 2006.217.08:19:52.75#ibcon#*before return 0, iclass 14, count 0 2006.217.08:19:52.75#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.217.08:19:52.75#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.217.08:19:52.75#ibcon#about to clear, iclass 14 cls_cnt 0 2006.217.08:19:52.75#ibcon#cleared, iclass 14 cls_cnt 0 2006.217.08:19:52.75$4f8m12a/ifd4f 2006.217.08:19:52.75$ifd4f/lo= 2006.217.08:19:52.75$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.217.08:19:52.75$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.217.08:19:52.76$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.217.08:19:52.76$ifd4f/patch= 2006.217.08:19:52.76$ifd4f/patch=lo1,a1,a2,a3,a4 2006.217.08:19:52.76$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.217.08:19:52.76$ifd4f/patch=lo3,a5,a6,a7,a8 2006.217.08:19:52.76$4f8m12a/"form=m,16.000,1:2 2006.217.08:19:52.76$4f8m12a/"tpicd 2006.217.08:19:52.76$4f8m12a/echo=off 2006.217.08:19:52.76$4f8m12a/xlog=off 2006.217.08:19:52.76:!2006.217.08:21:10 2006.217.08:20:19.14#trakl#Source acquired 2006.217.08:20:20.14#flagr#flagr/antenna,acquired 2006.217.08:21:10.01:preob 2006.217.08:21:11.14/onsource/TRACKING 2006.217.08:21:11.14:!2006.217.08:21:20 2006.217.08:21:20.00:data_valid=on 2006.217.08:21:20.00:midob 2006.217.08:21:20.14/onsource/TRACKING 2006.217.08:21:20.14/wx/30.48,1008.6,65 2006.217.08:21:20.30/cable/+6.3873E-03 2006.217.08:21:21.39/va/01,05,usb,yes,33,34 2006.217.08:21:21.39/va/02,04,usb,yes,31,32 2006.217.08:21:21.39/va/03,04,usb,yes,29,29 2006.217.08:21:21.39/va/04,04,usb,yes,32,34 2006.217.08:21:21.39/va/05,07,usb,yes,34,36 2006.217.08:21:21.39/va/06,06,usb,yes,34,33 2006.217.08:21:21.39/va/07,06,usb,yes,34,34 2006.217.08:21:21.39/va/08,07,usb,yes,32,32 2006.217.08:21:21.62/valo/01,532.99,yes,locked 2006.217.08:21:21.62/valo/02,572.99,yes,locked 2006.217.08:21:21.62/valo/03,672.99,yes,locked 2006.217.08:21:21.62/valo/04,832.99,yes,locked 2006.217.08:21:21.62/valo/05,652.99,yes,locked 2006.217.08:21:21.62/valo/06,772.99,yes,locked 2006.217.08:21:21.62/valo/07,832.99,yes,locked 2006.217.08:21:21.62/valo/08,852.99,yes,locked 2006.217.08:21:22.71/vb/01,04,usb,yes,31,30 2006.217.08:21:22.71/vb/02,04,usb,yes,33,35 2006.217.08:21:22.71/vb/03,04,usb,yes,29,33 2006.217.08:21:22.71/vb/04,04,usb,yes,30,30 2006.217.08:21:22.71/vb/05,04,usb,yes,29,33 2006.217.08:21:22.71/vb/06,04,usb,yes,30,33 2006.217.08:21:22.71/vb/07,04,usb,yes,32,32 2006.217.08:21:22.71/vb/08,04,usb,yes,29,33 2006.217.08:21:22.95/vblo/01,632.99,yes,locked 2006.217.08:21:22.95/vblo/02,640.99,yes,locked 2006.217.08:21:22.95/vblo/03,656.99,yes,locked 2006.217.08:21:22.95/vblo/04,712.99,yes,locked 2006.217.08:21:22.95/vblo/05,744.99,yes,locked 2006.217.08:21:22.95/vblo/06,752.99,yes,locked 2006.217.08:21:22.95/vblo/07,734.99,yes,locked 2006.217.08:21:22.95/vblo/08,744.99,yes,locked 2006.217.08:21:23.10/vabw/8 2006.217.08:21:23.25/vbbw/8 2006.217.08:21:23.41/xfe/off,on,14.5 2006.217.08:21:23.80/ifatt/23,28,28,28 2006.217.08:21:24.07/fmout-gps/S +4.53E-07 2006.217.08:21:24.15:!2006.217.08:22:20 2006.217.08:22:20.01:data_valid=off 2006.217.08:22:20.02:postob 2006.217.08:22:20.23/cable/+6.3880E-03 2006.217.08:22:20.24/wx/30.47,1008.6,64 2006.217.08:22:21.07/fmout-gps/S +4.51E-07 2006.217.08:22:21.08:scan_name=217-0824,k06217,60 2006.217.08:22:21.08:source=1417+385,141946.61,382148.5,2000.0,ccw 2006.217.08:22:22.14#flagr#flagr/antenna,new-source 2006.217.08:22:22.15:checkk5 2006.217.08:22:22.53/chk_autoobs//k5ts1/ autoobs is running! 2006.217.08:22:22.91/chk_autoobs//k5ts2/ autoobs is running! 2006.217.08:22:23.29/chk_autoobs//k5ts3/ autoobs is running! 2006.217.08:22:23.66/chk_autoobs//k5ts4/ autoobs is running! 2006.217.08:22:24.03/chk_obsdata//k5ts1/T2170821??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.08:22:24.40/chk_obsdata//k5ts2/T2170821??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.08:22:24.77/chk_obsdata//k5ts3/T2170821??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.08:22:25.14/chk_obsdata//k5ts4/T2170821??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.08:22:25.83/k5log//k5ts1_log_newline 2006.217.08:22:26.52/k5log//k5ts2_log_newline 2006.217.08:22:27.21/k5log//k5ts3_log_newline 2006.217.08:22:27.90/k5log//k5ts4_log_newline 2006.217.08:22:27.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.217.08:22:27.92:4f8m12a=3 2006.217.08:22:27.92$4f8m12a/echo=on 2006.217.08:22:27.92$4f8m12a/pcalon 2006.217.08:22:27.92$pcalon/"no phase cal control is implemented here 2006.217.08:22:27.92$4f8m12a/"tpicd=stop 2006.217.08:22:27.92$4f8m12a/vc4f8 2006.217.08:22:27.92$vc4f8/valo=1,532.99 2006.217.08:22:27.92#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.217.08:22:27.92#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.217.08:22:27.92#ibcon#ireg 17 cls_cnt 0 2006.217.08:22:27.92#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.217.08:22:27.92#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.217.08:22:27.92#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.217.08:22:27.92#ibcon#enter wrdev, iclass 36, count 0 2006.217.08:22:27.92#ibcon#first serial, iclass 36, count 0 2006.217.08:22:27.92#ibcon#enter sib2, iclass 36, count 0 2006.217.08:22:27.92#ibcon#flushed, iclass 36, count 0 2006.217.08:22:27.92#ibcon#about to write, iclass 36, count 0 2006.217.08:22:27.92#ibcon#wrote, iclass 36, count 0 2006.217.08:22:27.92#ibcon#about to read 3, iclass 36, count 0 2006.217.08:22:27.96#ibcon#read 3, iclass 36, count 0 2006.217.08:22:27.96#ibcon#about to read 4, iclass 36, count 0 2006.217.08:22:27.96#ibcon#read 4, iclass 36, count 0 2006.217.08:22:27.96#ibcon#about to read 5, iclass 36, count 0 2006.217.08:22:27.96#ibcon#read 5, iclass 36, count 0 2006.217.08:22:27.96#ibcon#about to read 6, iclass 36, count 0 2006.217.08:22:27.96#ibcon#read 6, iclass 36, count 0 2006.217.08:22:27.96#ibcon#end of sib2, iclass 36, count 0 2006.217.08:22:27.96#ibcon#*mode == 0, iclass 36, count 0 2006.217.08:22:27.96#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.217.08:22:27.96#ibcon#[26=FRQ=01,532.99\r\n] 2006.217.08:22:27.96#ibcon#*before write, iclass 36, count 0 2006.217.08:22:27.96#ibcon#enter sib2, iclass 36, count 0 2006.217.08:22:27.96#ibcon#flushed, iclass 36, count 0 2006.217.08:22:27.96#ibcon#about to write, iclass 36, count 0 2006.217.08:22:27.96#ibcon#wrote, iclass 36, count 0 2006.217.08:22:27.96#ibcon#about to read 3, iclass 36, count 0 2006.217.08:22:28.01#ibcon#read 3, iclass 36, count 0 2006.217.08:22:28.01#ibcon#about to read 4, iclass 36, count 0 2006.217.08:22:28.01#ibcon#read 4, iclass 36, count 0 2006.217.08:22:28.01#ibcon#about to read 5, iclass 36, count 0 2006.217.08:22:28.01#ibcon#read 5, iclass 36, count 0 2006.217.08:22:28.01#ibcon#about to read 6, iclass 36, count 0 2006.217.08:22:28.01#ibcon#read 6, iclass 36, count 0 2006.217.08:22:28.01#ibcon#end of sib2, iclass 36, count 0 2006.217.08:22:28.01#ibcon#*after write, iclass 36, count 0 2006.217.08:22:28.01#ibcon#*before return 0, iclass 36, count 0 2006.217.08:22:28.01#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.217.08:22:28.01#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.217.08:22:28.01#ibcon#about to clear, iclass 36 cls_cnt 0 2006.217.08:22:28.01#ibcon#cleared, iclass 36 cls_cnt 0 2006.217.08:22:28.01$vc4f8/va=1,5 2006.217.08:22:28.01#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.217.08:22:28.01#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.217.08:22:28.01#ibcon#ireg 11 cls_cnt 2 2006.217.08:22:28.01#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.217.08:22:28.01#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.217.08:22:28.01#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.217.08:22:28.01#ibcon#enter wrdev, iclass 38, count 2 2006.217.08:22:28.01#ibcon#first serial, iclass 38, count 2 2006.217.08:22:28.01#ibcon#enter sib2, iclass 38, count 2 2006.217.08:22:28.01#ibcon#flushed, iclass 38, count 2 2006.217.08:22:28.01#ibcon#about to write, iclass 38, count 2 2006.217.08:22:28.01#ibcon#wrote, iclass 38, count 2 2006.217.08:22:28.01#ibcon#about to read 3, iclass 38, count 2 2006.217.08:22:28.03#ibcon#read 3, iclass 38, count 2 2006.217.08:22:28.03#ibcon#about to read 4, iclass 38, count 2 2006.217.08:22:28.03#ibcon#read 4, iclass 38, count 2 2006.217.08:22:28.03#ibcon#about to read 5, iclass 38, count 2 2006.217.08:22:28.03#ibcon#read 5, iclass 38, count 2 2006.217.08:22:28.03#ibcon#about to read 6, iclass 38, count 2 2006.217.08:22:28.03#ibcon#read 6, iclass 38, count 2 2006.217.08:22:28.03#ibcon#end of sib2, iclass 38, count 2 2006.217.08:22:28.03#ibcon#*mode == 0, iclass 38, count 2 2006.217.08:22:28.03#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.217.08:22:28.03#ibcon#[25=AT01-05\r\n] 2006.217.08:22:28.03#ibcon#*before write, iclass 38, count 2 2006.217.08:22:28.03#ibcon#enter sib2, iclass 38, count 2 2006.217.08:22:28.03#ibcon#flushed, iclass 38, count 2 2006.217.08:22:28.03#ibcon#about to write, iclass 38, count 2 2006.217.08:22:28.03#ibcon#wrote, iclass 38, count 2 2006.217.08:22:28.03#ibcon#about to read 3, iclass 38, count 2 2006.217.08:22:28.07#ibcon#read 3, iclass 38, count 2 2006.217.08:22:28.07#ibcon#about to read 4, iclass 38, count 2 2006.217.08:22:28.07#ibcon#read 4, iclass 38, count 2 2006.217.08:22:28.07#ibcon#about to read 5, iclass 38, count 2 2006.217.08:22:28.07#ibcon#read 5, iclass 38, count 2 2006.217.08:22:28.07#ibcon#about to read 6, iclass 38, count 2 2006.217.08:22:28.07#ibcon#read 6, iclass 38, count 2 2006.217.08:22:28.07#ibcon#end of sib2, iclass 38, count 2 2006.217.08:22:28.07#ibcon#*after write, iclass 38, count 2 2006.217.08:22:28.07#ibcon#*before return 0, iclass 38, count 2 2006.217.08:22:28.07#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.217.08:22:28.07#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.217.08:22:28.07#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.217.08:22:28.07#ibcon#ireg 7 cls_cnt 0 2006.217.08:22:28.07#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.217.08:22:28.18#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.217.08:22:28.18#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.217.08:22:28.18#ibcon#enter wrdev, iclass 38, count 0 2006.217.08:22:28.18#ibcon#first serial, iclass 38, count 0 2006.217.08:22:28.18#ibcon#enter sib2, iclass 38, count 0 2006.217.08:22:28.18#ibcon#flushed, iclass 38, count 0 2006.217.08:22:28.18#ibcon#about to write, iclass 38, count 0 2006.217.08:22:28.18#ibcon#wrote, iclass 38, count 0 2006.217.08:22:28.18#ibcon#about to read 3, iclass 38, count 0 2006.217.08:22:28.20#ibcon#read 3, iclass 38, count 0 2006.217.08:22:28.20#ibcon#about to read 4, iclass 38, count 0 2006.217.08:22:28.20#ibcon#read 4, iclass 38, count 0 2006.217.08:22:28.20#ibcon#about to read 5, iclass 38, count 0 2006.217.08:22:28.20#ibcon#read 5, iclass 38, count 0 2006.217.08:22:28.20#ibcon#about to read 6, iclass 38, count 0 2006.217.08:22:28.20#ibcon#read 6, iclass 38, count 0 2006.217.08:22:28.20#ibcon#end of sib2, iclass 38, count 0 2006.217.08:22:28.20#ibcon#*mode == 0, iclass 38, count 0 2006.217.08:22:28.20#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.217.08:22:28.20#ibcon#[25=USB\r\n] 2006.217.08:22:28.20#ibcon#*before write, iclass 38, count 0 2006.217.08:22:28.20#ibcon#enter sib2, iclass 38, count 0 2006.217.08:22:28.20#ibcon#flushed, iclass 38, count 0 2006.217.08:22:28.20#ibcon#about to write, iclass 38, count 0 2006.217.08:22:28.20#ibcon#wrote, iclass 38, count 0 2006.217.08:22:28.20#ibcon#about to read 3, iclass 38, count 0 2006.217.08:22:28.23#ibcon#read 3, iclass 38, count 0 2006.217.08:22:28.23#ibcon#about to read 4, iclass 38, count 0 2006.217.08:22:28.23#ibcon#read 4, iclass 38, count 0 2006.217.08:22:28.23#ibcon#about to read 5, iclass 38, count 0 2006.217.08:22:28.23#ibcon#read 5, iclass 38, count 0 2006.217.08:22:28.23#ibcon#about to read 6, iclass 38, count 0 2006.217.08:22:28.23#ibcon#read 6, iclass 38, count 0 2006.217.08:22:28.23#ibcon#end of sib2, iclass 38, count 0 2006.217.08:22:28.23#ibcon#*after write, iclass 38, count 0 2006.217.08:22:28.23#ibcon#*before return 0, iclass 38, count 0 2006.217.08:22:28.23#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.217.08:22:28.23#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.217.08:22:28.23#ibcon#about to clear, iclass 38 cls_cnt 0 2006.217.08:22:28.23#ibcon#cleared, iclass 38 cls_cnt 0 2006.217.08:22:28.23$vc4f8/valo=2,572.99 2006.217.08:22:28.23#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.217.08:22:28.23#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.217.08:22:28.23#ibcon#ireg 17 cls_cnt 0 2006.217.08:22:28.23#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.217.08:22:28.23#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.217.08:22:28.23#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.217.08:22:28.23#ibcon#enter wrdev, iclass 40, count 0 2006.217.08:22:28.23#ibcon#first serial, iclass 40, count 0 2006.217.08:22:28.23#ibcon#enter sib2, iclass 40, count 0 2006.217.08:22:28.24#ibcon#flushed, iclass 40, count 0 2006.217.08:22:28.24#ibcon#about to write, iclass 40, count 0 2006.217.08:22:28.24#ibcon#wrote, iclass 40, count 0 2006.217.08:22:28.24#ibcon#about to read 3, iclass 40, count 0 2006.217.08:22:28.25#ibcon#read 3, iclass 40, count 0 2006.217.08:22:28.25#ibcon#about to read 4, iclass 40, count 0 2006.217.08:22:28.25#ibcon#read 4, iclass 40, count 0 2006.217.08:22:28.25#ibcon#about to read 5, iclass 40, count 0 2006.217.08:22:28.25#ibcon#read 5, iclass 40, count 0 2006.217.08:22:28.25#ibcon#about to read 6, iclass 40, count 0 2006.217.08:22:28.25#ibcon#read 6, iclass 40, count 0 2006.217.08:22:28.25#ibcon#end of sib2, iclass 40, count 0 2006.217.08:22:28.25#ibcon#*mode == 0, iclass 40, count 0 2006.217.08:22:28.25#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.217.08:22:28.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.217.08:22:28.25#ibcon#*before write, iclass 40, count 0 2006.217.08:22:28.25#ibcon#enter sib2, iclass 40, count 0 2006.217.08:22:28.25#ibcon#flushed, iclass 40, count 0 2006.217.08:22:28.25#ibcon#about to write, iclass 40, count 0 2006.217.08:22:28.25#ibcon#wrote, iclass 40, count 0 2006.217.08:22:28.25#ibcon#about to read 3, iclass 40, count 0 2006.217.08:22:28.29#ibcon#read 3, iclass 40, count 0 2006.217.08:22:28.29#ibcon#about to read 4, iclass 40, count 0 2006.217.08:22:28.29#ibcon#read 4, iclass 40, count 0 2006.217.08:22:28.29#ibcon#about to read 5, iclass 40, count 0 2006.217.08:22:28.29#ibcon#read 5, iclass 40, count 0 2006.217.08:22:28.29#ibcon#about to read 6, iclass 40, count 0 2006.217.08:22:28.29#ibcon#read 6, iclass 40, count 0 2006.217.08:22:28.29#ibcon#end of sib2, iclass 40, count 0 2006.217.08:22:28.29#ibcon#*after write, iclass 40, count 0 2006.217.08:22:28.29#ibcon#*before return 0, iclass 40, count 0 2006.217.08:22:28.29#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.217.08:22:28.29#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.217.08:22:28.29#ibcon#about to clear, iclass 40 cls_cnt 0 2006.217.08:22:28.29#ibcon#cleared, iclass 40 cls_cnt 0 2006.217.08:22:28.29$vc4f8/va=2,4 2006.217.08:22:28.29#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.217.08:22:28.29#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.217.08:22:28.29#ibcon#ireg 11 cls_cnt 2 2006.217.08:22:28.29#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.217.08:22:28.35#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.217.08:22:28.35#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.217.08:22:28.35#ibcon#enter wrdev, iclass 4, count 2 2006.217.08:22:28.35#ibcon#first serial, iclass 4, count 2 2006.217.08:22:28.35#ibcon#enter sib2, iclass 4, count 2 2006.217.08:22:28.35#ibcon#flushed, iclass 4, count 2 2006.217.08:22:28.35#ibcon#about to write, iclass 4, count 2 2006.217.08:22:28.35#ibcon#wrote, iclass 4, count 2 2006.217.08:22:28.35#ibcon#about to read 3, iclass 4, count 2 2006.217.08:22:28.37#ibcon#read 3, iclass 4, count 2 2006.217.08:22:28.37#ibcon#about to read 4, iclass 4, count 2 2006.217.08:22:28.37#ibcon#read 4, iclass 4, count 2 2006.217.08:22:28.37#ibcon#about to read 5, iclass 4, count 2 2006.217.08:22:28.37#ibcon#read 5, iclass 4, count 2 2006.217.08:22:28.37#ibcon#about to read 6, iclass 4, count 2 2006.217.08:22:28.37#ibcon#read 6, iclass 4, count 2 2006.217.08:22:28.37#ibcon#end of sib2, iclass 4, count 2 2006.217.08:22:28.37#ibcon#*mode == 0, iclass 4, count 2 2006.217.08:22:28.37#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.217.08:22:28.37#ibcon#[25=AT02-04\r\n] 2006.217.08:22:28.37#ibcon#*before write, iclass 4, count 2 2006.217.08:22:28.37#ibcon#enter sib2, iclass 4, count 2 2006.217.08:22:28.37#ibcon#flushed, iclass 4, count 2 2006.217.08:22:28.37#ibcon#about to write, iclass 4, count 2 2006.217.08:22:28.37#ibcon#wrote, iclass 4, count 2 2006.217.08:22:28.37#ibcon#about to read 3, iclass 4, count 2 2006.217.08:22:28.41#ibcon#read 3, iclass 4, count 2 2006.217.08:22:28.41#ibcon#about to read 4, iclass 4, count 2 2006.217.08:22:28.41#ibcon#read 4, iclass 4, count 2 2006.217.08:22:28.41#ibcon#about to read 5, iclass 4, count 2 2006.217.08:22:28.41#ibcon#read 5, iclass 4, count 2 2006.217.08:22:28.41#ibcon#about to read 6, iclass 4, count 2 2006.217.08:22:28.41#ibcon#read 6, iclass 4, count 2 2006.217.08:22:28.41#ibcon#end of sib2, iclass 4, count 2 2006.217.08:22:28.41#ibcon#*after write, iclass 4, count 2 2006.217.08:22:28.41#ibcon#*before return 0, iclass 4, count 2 2006.217.08:22:28.41#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.217.08:22:28.41#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.217.08:22:28.41#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.217.08:22:28.41#ibcon#ireg 7 cls_cnt 0 2006.217.08:22:28.41#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.217.08:22:28.52#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.217.08:22:28.52#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.217.08:22:28.52#ibcon#enter wrdev, iclass 4, count 0 2006.217.08:22:28.52#ibcon#first serial, iclass 4, count 0 2006.217.08:22:28.52#ibcon#enter sib2, iclass 4, count 0 2006.217.08:22:28.52#ibcon#flushed, iclass 4, count 0 2006.217.08:22:28.52#ibcon#about to write, iclass 4, count 0 2006.217.08:22:28.52#ibcon#wrote, iclass 4, count 0 2006.217.08:22:28.52#ibcon#about to read 3, iclass 4, count 0 2006.217.08:22:28.54#ibcon#read 3, iclass 4, count 0 2006.217.08:22:28.54#ibcon#about to read 4, iclass 4, count 0 2006.217.08:22:28.54#ibcon#read 4, iclass 4, count 0 2006.217.08:22:28.54#ibcon#about to read 5, iclass 4, count 0 2006.217.08:22:28.54#ibcon#read 5, iclass 4, count 0 2006.217.08:22:28.54#ibcon#about to read 6, iclass 4, count 0 2006.217.08:22:28.54#ibcon#read 6, iclass 4, count 0 2006.217.08:22:28.54#ibcon#end of sib2, iclass 4, count 0 2006.217.08:22:28.54#ibcon#*mode == 0, iclass 4, count 0 2006.217.08:22:28.54#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.217.08:22:28.54#ibcon#[25=USB\r\n] 2006.217.08:22:28.54#ibcon#*before write, iclass 4, count 0 2006.217.08:22:28.54#ibcon#enter sib2, iclass 4, count 0 2006.217.08:22:28.54#ibcon#flushed, iclass 4, count 0 2006.217.08:22:28.54#ibcon#about to write, iclass 4, count 0 2006.217.08:22:28.54#ibcon#wrote, iclass 4, count 0 2006.217.08:22:28.54#ibcon#about to read 3, iclass 4, count 0 2006.217.08:22:28.57#ibcon#read 3, iclass 4, count 0 2006.217.08:22:28.57#ibcon#about to read 4, iclass 4, count 0 2006.217.08:22:28.57#ibcon#read 4, iclass 4, count 0 2006.217.08:22:28.57#ibcon#about to read 5, iclass 4, count 0 2006.217.08:22:28.57#ibcon#read 5, iclass 4, count 0 2006.217.08:22:28.57#ibcon#about to read 6, iclass 4, count 0 2006.217.08:22:28.57#ibcon#read 6, iclass 4, count 0 2006.217.08:22:28.57#ibcon#end of sib2, iclass 4, count 0 2006.217.08:22:28.57#ibcon#*after write, iclass 4, count 0 2006.217.08:22:28.57#ibcon#*before return 0, iclass 4, count 0 2006.217.08:22:28.57#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.217.08:22:28.57#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.217.08:22:28.57#ibcon#about to clear, iclass 4 cls_cnt 0 2006.217.08:22:28.57#ibcon#cleared, iclass 4 cls_cnt 0 2006.217.08:22:28.57$vc4f8/valo=3,672.99 2006.217.08:22:28.57#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.217.08:22:28.57#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.217.08:22:28.57#ibcon#ireg 17 cls_cnt 0 2006.217.08:22:28.57#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.217.08:22:28.57#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.217.08:22:28.57#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.217.08:22:28.57#ibcon#enter wrdev, iclass 6, count 0 2006.217.08:22:28.57#ibcon#first serial, iclass 6, count 0 2006.217.08:22:28.57#ibcon#enter sib2, iclass 6, count 0 2006.217.08:22:28.57#ibcon#flushed, iclass 6, count 0 2006.217.08:22:28.57#ibcon#about to write, iclass 6, count 0 2006.217.08:22:28.57#ibcon#wrote, iclass 6, count 0 2006.217.08:22:28.57#ibcon#about to read 3, iclass 6, count 0 2006.217.08:22:28.60#ibcon#read 3, iclass 6, count 0 2006.217.08:22:28.60#ibcon#about to read 4, iclass 6, count 0 2006.217.08:22:28.60#ibcon#read 4, iclass 6, count 0 2006.217.08:22:28.60#ibcon#about to read 5, iclass 6, count 0 2006.217.08:22:28.60#ibcon#read 5, iclass 6, count 0 2006.217.08:22:28.60#ibcon#about to read 6, iclass 6, count 0 2006.217.08:22:28.60#ibcon#read 6, iclass 6, count 0 2006.217.08:22:28.60#ibcon#end of sib2, iclass 6, count 0 2006.217.08:22:28.60#ibcon#*mode == 0, iclass 6, count 0 2006.217.08:22:28.60#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.217.08:22:28.60#ibcon#[26=FRQ=03,672.99\r\n] 2006.217.08:22:28.60#ibcon#*before write, iclass 6, count 0 2006.217.08:22:28.60#ibcon#enter sib2, iclass 6, count 0 2006.217.08:22:28.60#ibcon#flushed, iclass 6, count 0 2006.217.08:22:28.60#ibcon#about to write, iclass 6, count 0 2006.217.08:22:28.60#ibcon#wrote, iclass 6, count 0 2006.217.08:22:28.60#ibcon#about to read 3, iclass 6, count 0 2006.217.08:22:28.64#ibcon#read 3, iclass 6, count 0 2006.217.08:22:28.64#ibcon#about to read 4, iclass 6, count 0 2006.217.08:22:28.64#ibcon#read 4, iclass 6, count 0 2006.217.08:22:28.64#ibcon#about to read 5, iclass 6, count 0 2006.217.08:22:28.64#ibcon#read 5, iclass 6, count 0 2006.217.08:22:28.64#ibcon#about to read 6, iclass 6, count 0 2006.217.08:22:28.64#ibcon#read 6, iclass 6, count 0 2006.217.08:22:28.64#ibcon#end of sib2, iclass 6, count 0 2006.217.08:22:28.64#ibcon#*after write, iclass 6, count 0 2006.217.08:22:28.64#ibcon#*before return 0, iclass 6, count 0 2006.217.08:22:28.64#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.217.08:22:28.64#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.217.08:22:28.64#ibcon#about to clear, iclass 6 cls_cnt 0 2006.217.08:22:28.64#ibcon#cleared, iclass 6 cls_cnt 0 2006.217.08:22:28.64$vc4f8/va=3,4 2006.217.08:22:28.64#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.217.08:22:28.64#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.217.08:22:28.64#ibcon#ireg 11 cls_cnt 2 2006.217.08:22:28.64#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.217.08:22:28.69#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.217.08:22:28.70#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.217.08:22:28.70#ibcon#enter wrdev, iclass 10, count 2 2006.217.08:22:28.70#ibcon#first serial, iclass 10, count 2 2006.217.08:22:28.70#ibcon#enter sib2, iclass 10, count 2 2006.217.08:22:28.70#ibcon#flushed, iclass 10, count 2 2006.217.08:22:28.70#ibcon#about to write, iclass 10, count 2 2006.217.08:22:28.70#ibcon#wrote, iclass 10, count 2 2006.217.08:22:28.70#ibcon#about to read 3, iclass 10, count 2 2006.217.08:22:28.71#ibcon#read 3, iclass 10, count 2 2006.217.08:22:28.71#ibcon#about to read 4, iclass 10, count 2 2006.217.08:22:28.71#ibcon#read 4, iclass 10, count 2 2006.217.08:22:28.71#ibcon#about to read 5, iclass 10, count 2 2006.217.08:22:28.71#ibcon#read 5, iclass 10, count 2 2006.217.08:22:28.71#ibcon#about to read 6, iclass 10, count 2 2006.217.08:22:28.71#ibcon#read 6, iclass 10, count 2 2006.217.08:22:28.71#ibcon#end of sib2, iclass 10, count 2 2006.217.08:22:28.71#ibcon#*mode == 0, iclass 10, count 2 2006.217.08:22:28.71#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.217.08:22:28.71#ibcon#[25=AT03-04\r\n] 2006.217.08:22:28.71#ibcon#*before write, iclass 10, count 2 2006.217.08:22:28.71#ibcon#enter sib2, iclass 10, count 2 2006.217.08:22:28.71#ibcon#flushed, iclass 10, count 2 2006.217.08:22:28.71#ibcon#about to write, iclass 10, count 2 2006.217.08:22:28.71#ibcon#wrote, iclass 10, count 2 2006.217.08:22:28.71#ibcon#about to read 3, iclass 10, count 2 2006.217.08:22:28.74#ibcon#read 3, iclass 10, count 2 2006.217.08:22:28.74#ibcon#about to read 4, iclass 10, count 2 2006.217.08:22:28.74#ibcon#read 4, iclass 10, count 2 2006.217.08:22:28.74#ibcon#about to read 5, iclass 10, count 2 2006.217.08:22:28.74#ibcon#read 5, iclass 10, count 2 2006.217.08:22:28.74#ibcon#about to read 6, iclass 10, count 2 2006.217.08:22:28.74#ibcon#read 6, iclass 10, count 2 2006.217.08:22:28.74#ibcon#end of sib2, iclass 10, count 2 2006.217.08:22:28.74#ibcon#*after write, iclass 10, count 2 2006.217.08:22:28.74#ibcon#*before return 0, iclass 10, count 2 2006.217.08:22:28.74#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.217.08:22:28.74#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.217.08:22:28.74#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.217.08:22:28.74#ibcon#ireg 7 cls_cnt 0 2006.217.08:22:28.74#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.217.08:22:28.86#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.217.08:22:28.86#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.217.08:22:28.86#ibcon#enter wrdev, iclass 10, count 0 2006.217.08:22:28.86#ibcon#first serial, iclass 10, count 0 2006.217.08:22:28.86#ibcon#enter sib2, iclass 10, count 0 2006.217.08:22:28.86#ibcon#flushed, iclass 10, count 0 2006.217.08:22:28.86#ibcon#about to write, iclass 10, count 0 2006.217.08:22:28.86#ibcon#wrote, iclass 10, count 0 2006.217.08:22:28.86#ibcon#about to read 3, iclass 10, count 0 2006.217.08:22:28.88#ibcon#read 3, iclass 10, count 0 2006.217.08:22:28.88#ibcon#about to read 4, iclass 10, count 0 2006.217.08:22:28.88#ibcon#read 4, iclass 10, count 0 2006.217.08:22:28.88#ibcon#about to read 5, iclass 10, count 0 2006.217.08:22:28.88#ibcon#read 5, iclass 10, count 0 2006.217.08:22:28.88#ibcon#about to read 6, iclass 10, count 0 2006.217.08:22:28.88#ibcon#read 6, iclass 10, count 0 2006.217.08:22:28.88#ibcon#end of sib2, iclass 10, count 0 2006.217.08:22:28.88#ibcon#*mode == 0, iclass 10, count 0 2006.217.08:22:28.88#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.217.08:22:28.88#ibcon#[25=USB\r\n] 2006.217.08:22:28.88#ibcon#*before write, iclass 10, count 0 2006.217.08:22:28.88#ibcon#enter sib2, iclass 10, count 0 2006.217.08:22:28.88#ibcon#flushed, iclass 10, count 0 2006.217.08:22:28.88#ibcon#about to write, iclass 10, count 0 2006.217.08:22:28.88#ibcon#wrote, iclass 10, count 0 2006.217.08:22:28.88#ibcon#about to read 3, iclass 10, count 0 2006.217.08:22:28.91#ibcon#read 3, iclass 10, count 0 2006.217.08:22:28.91#ibcon#about to read 4, iclass 10, count 0 2006.217.08:22:28.91#ibcon#read 4, iclass 10, count 0 2006.217.08:22:28.91#ibcon#about to read 5, iclass 10, count 0 2006.217.08:22:28.91#ibcon#read 5, iclass 10, count 0 2006.217.08:22:28.91#ibcon#about to read 6, iclass 10, count 0 2006.217.08:22:28.91#ibcon#read 6, iclass 10, count 0 2006.217.08:22:28.91#ibcon#end of sib2, iclass 10, count 0 2006.217.08:22:28.91#ibcon#*after write, iclass 10, count 0 2006.217.08:22:28.91#ibcon#*before return 0, iclass 10, count 0 2006.217.08:22:28.91#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.217.08:22:28.91#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.217.08:22:28.91#ibcon#about to clear, iclass 10 cls_cnt 0 2006.217.08:22:28.91#ibcon#cleared, iclass 10 cls_cnt 0 2006.217.08:22:28.91$vc4f8/valo=4,832.99 2006.217.08:22:28.91#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.217.08:22:28.91#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.217.08:22:28.91#ibcon#ireg 17 cls_cnt 0 2006.217.08:22:28.91#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.217.08:22:28.91#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.217.08:22:28.91#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.217.08:22:28.91#ibcon#enter wrdev, iclass 12, count 0 2006.217.08:22:28.91#ibcon#first serial, iclass 12, count 0 2006.217.08:22:28.91#ibcon#enter sib2, iclass 12, count 0 2006.217.08:22:28.91#ibcon#flushed, iclass 12, count 0 2006.217.08:22:28.91#ibcon#about to write, iclass 12, count 0 2006.217.08:22:28.91#ibcon#wrote, iclass 12, count 0 2006.217.08:22:28.91#ibcon#about to read 3, iclass 12, count 0 2006.217.08:22:28.93#ibcon#read 3, iclass 12, count 0 2006.217.08:22:28.93#ibcon#about to read 4, iclass 12, count 0 2006.217.08:22:28.93#ibcon#read 4, iclass 12, count 0 2006.217.08:22:28.93#ibcon#about to read 5, iclass 12, count 0 2006.217.08:22:28.93#ibcon#read 5, iclass 12, count 0 2006.217.08:22:28.93#ibcon#about to read 6, iclass 12, count 0 2006.217.08:22:28.93#ibcon#read 6, iclass 12, count 0 2006.217.08:22:28.93#ibcon#end of sib2, iclass 12, count 0 2006.217.08:22:28.93#ibcon#*mode == 0, iclass 12, count 0 2006.217.08:22:28.93#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.217.08:22:28.93#ibcon#[26=FRQ=04,832.99\r\n] 2006.217.08:22:28.93#ibcon#*before write, iclass 12, count 0 2006.217.08:22:28.93#ibcon#enter sib2, iclass 12, count 0 2006.217.08:22:28.93#ibcon#flushed, iclass 12, count 0 2006.217.08:22:28.93#ibcon#about to write, iclass 12, count 0 2006.217.08:22:28.93#ibcon#wrote, iclass 12, count 0 2006.217.08:22:28.93#ibcon#about to read 3, iclass 12, count 0 2006.217.08:22:28.97#ibcon#read 3, iclass 12, count 0 2006.217.08:22:28.97#ibcon#about to read 4, iclass 12, count 0 2006.217.08:22:28.97#ibcon#read 4, iclass 12, count 0 2006.217.08:22:28.97#ibcon#about to read 5, iclass 12, count 0 2006.217.08:22:28.97#ibcon#read 5, iclass 12, count 0 2006.217.08:22:28.97#ibcon#about to read 6, iclass 12, count 0 2006.217.08:22:28.97#ibcon#read 6, iclass 12, count 0 2006.217.08:22:28.97#ibcon#end of sib2, iclass 12, count 0 2006.217.08:22:28.97#ibcon#*after write, iclass 12, count 0 2006.217.08:22:28.97#ibcon#*before return 0, iclass 12, count 0 2006.217.08:22:28.97#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.217.08:22:28.97#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.217.08:22:28.97#ibcon#about to clear, iclass 12 cls_cnt 0 2006.217.08:22:28.97#ibcon#cleared, iclass 12 cls_cnt 0 2006.217.08:22:28.97$vc4f8/va=4,4 2006.217.08:22:28.97#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.217.08:22:28.97#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.217.08:22:28.97#ibcon#ireg 11 cls_cnt 2 2006.217.08:22:28.97#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.217.08:22:29.03#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.217.08:22:29.03#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.217.08:22:29.03#ibcon#enter wrdev, iclass 14, count 2 2006.217.08:22:29.03#ibcon#first serial, iclass 14, count 2 2006.217.08:22:29.03#ibcon#enter sib2, iclass 14, count 2 2006.217.08:22:29.03#ibcon#flushed, iclass 14, count 2 2006.217.08:22:29.03#ibcon#about to write, iclass 14, count 2 2006.217.08:22:29.03#ibcon#wrote, iclass 14, count 2 2006.217.08:22:29.03#ibcon#about to read 3, iclass 14, count 2 2006.217.08:22:29.05#ibcon#read 3, iclass 14, count 2 2006.217.08:22:29.05#ibcon#about to read 4, iclass 14, count 2 2006.217.08:22:29.05#ibcon#read 4, iclass 14, count 2 2006.217.08:22:29.05#ibcon#about to read 5, iclass 14, count 2 2006.217.08:22:29.05#ibcon#read 5, iclass 14, count 2 2006.217.08:22:29.05#ibcon#about to read 6, iclass 14, count 2 2006.217.08:22:29.05#ibcon#read 6, iclass 14, count 2 2006.217.08:22:29.05#ibcon#end of sib2, iclass 14, count 2 2006.217.08:22:29.05#ibcon#*mode == 0, iclass 14, count 2 2006.217.08:22:29.05#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.217.08:22:29.05#ibcon#[25=AT04-04\r\n] 2006.217.08:22:29.05#ibcon#*before write, iclass 14, count 2 2006.217.08:22:29.05#ibcon#enter sib2, iclass 14, count 2 2006.217.08:22:29.05#ibcon#flushed, iclass 14, count 2 2006.217.08:22:29.05#ibcon#about to write, iclass 14, count 2 2006.217.08:22:29.05#ibcon#wrote, iclass 14, count 2 2006.217.08:22:29.05#ibcon#about to read 3, iclass 14, count 2 2006.217.08:22:29.08#ibcon#read 3, iclass 14, count 2 2006.217.08:22:29.08#ibcon#about to read 4, iclass 14, count 2 2006.217.08:22:29.08#ibcon#read 4, iclass 14, count 2 2006.217.08:22:29.08#ibcon#about to read 5, iclass 14, count 2 2006.217.08:22:29.08#ibcon#read 5, iclass 14, count 2 2006.217.08:22:29.08#ibcon#about to read 6, iclass 14, count 2 2006.217.08:22:29.08#ibcon#read 6, iclass 14, count 2 2006.217.08:22:29.08#ibcon#end of sib2, iclass 14, count 2 2006.217.08:22:29.08#ibcon#*after write, iclass 14, count 2 2006.217.08:22:29.08#ibcon#*before return 0, iclass 14, count 2 2006.217.08:22:29.08#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.217.08:22:29.08#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.217.08:22:29.08#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.217.08:22:29.08#ibcon#ireg 7 cls_cnt 0 2006.217.08:22:29.08#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.217.08:22:29.20#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.217.08:22:29.20#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.217.08:22:29.20#ibcon#enter wrdev, iclass 14, count 0 2006.217.08:22:29.20#ibcon#first serial, iclass 14, count 0 2006.217.08:22:29.20#ibcon#enter sib2, iclass 14, count 0 2006.217.08:22:29.20#ibcon#flushed, iclass 14, count 0 2006.217.08:22:29.20#ibcon#about to write, iclass 14, count 0 2006.217.08:22:29.20#ibcon#wrote, iclass 14, count 0 2006.217.08:22:29.20#ibcon#about to read 3, iclass 14, count 0 2006.217.08:22:29.22#ibcon#read 3, iclass 14, count 0 2006.217.08:22:29.22#ibcon#about to read 4, iclass 14, count 0 2006.217.08:22:29.22#ibcon#read 4, iclass 14, count 0 2006.217.08:22:29.22#ibcon#about to read 5, iclass 14, count 0 2006.217.08:22:29.22#ibcon#read 5, iclass 14, count 0 2006.217.08:22:29.22#ibcon#about to read 6, iclass 14, count 0 2006.217.08:22:29.22#ibcon#read 6, iclass 14, count 0 2006.217.08:22:29.22#ibcon#end of sib2, iclass 14, count 0 2006.217.08:22:29.22#ibcon#*mode == 0, iclass 14, count 0 2006.217.08:22:29.22#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.217.08:22:29.22#ibcon#[25=USB\r\n] 2006.217.08:22:29.22#ibcon#*before write, iclass 14, count 0 2006.217.08:22:29.22#ibcon#enter sib2, iclass 14, count 0 2006.217.08:22:29.22#ibcon#flushed, iclass 14, count 0 2006.217.08:22:29.22#ibcon#about to write, iclass 14, count 0 2006.217.08:22:29.22#ibcon#wrote, iclass 14, count 0 2006.217.08:22:29.22#ibcon#about to read 3, iclass 14, count 0 2006.217.08:22:29.25#ibcon#read 3, iclass 14, count 0 2006.217.08:22:29.25#ibcon#about to read 4, iclass 14, count 0 2006.217.08:22:29.25#ibcon#read 4, iclass 14, count 0 2006.217.08:22:29.25#ibcon#about to read 5, iclass 14, count 0 2006.217.08:22:29.25#ibcon#read 5, iclass 14, count 0 2006.217.08:22:29.25#ibcon#about to read 6, iclass 14, count 0 2006.217.08:22:29.25#ibcon#read 6, iclass 14, count 0 2006.217.08:22:29.25#ibcon#end of sib2, iclass 14, count 0 2006.217.08:22:29.25#ibcon#*after write, iclass 14, count 0 2006.217.08:22:29.25#ibcon#*before return 0, iclass 14, count 0 2006.217.08:22:29.25#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.217.08:22:29.25#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.217.08:22:29.25#ibcon#about to clear, iclass 14 cls_cnt 0 2006.217.08:22:29.25#ibcon#cleared, iclass 14 cls_cnt 0 2006.217.08:22:29.25$vc4f8/valo=5,652.99 2006.217.08:22:29.25#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.217.08:22:29.25#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.217.08:22:29.25#ibcon#ireg 17 cls_cnt 0 2006.217.08:22:29.25#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.217.08:22:29.25#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.217.08:22:29.25#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.217.08:22:29.25#ibcon#enter wrdev, iclass 16, count 0 2006.217.08:22:29.25#ibcon#first serial, iclass 16, count 0 2006.217.08:22:29.25#ibcon#enter sib2, iclass 16, count 0 2006.217.08:22:29.25#ibcon#flushed, iclass 16, count 0 2006.217.08:22:29.25#ibcon#about to write, iclass 16, count 0 2006.217.08:22:29.25#ibcon#wrote, iclass 16, count 0 2006.217.08:22:29.25#ibcon#about to read 3, iclass 16, count 0 2006.217.08:22:29.27#ibcon#read 3, iclass 16, count 0 2006.217.08:22:29.27#ibcon#about to read 4, iclass 16, count 0 2006.217.08:22:29.27#ibcon#read 4, iclass 16, count 0 2006.217.08:22:29.27#ibcon#about to read 5, iclass 16, count 0 2006.217.08:22:29.27#ibcon#read 5, iclass 16, count 0 2006.217.08:22:29.27#ibcon#about to read 6, iclass 16, count 0 2006.217.08:22:29.27#ibcon#read 6, iclass 16, count 0 2006.217.08:22:29.27#ibcon#end of sib2, iclass 16, count 0 2006.217.08:22:29.27#ibcon#*mode == 0, iclass 16, count 0 2006.217.08:22:29.27#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.217.08:22:29.27#ibcon#[26=FRQ=05,652.99\r\n] 2006.217.08:22:29.27#ibcon#*before write, iclass 16, count 0 2006.217.08:22:29.27#ibcon#enter sib2, iclass 16, count 0 2006.217.08:22:29.27#ibcon#flushed, iclass 16, count 0 2006.217.08:22:29.27#ibcon#about to write, iclass 16, count 0 2006.217.08:22:29.27#ibcon#wrote, iclass 16, count 0 2006.217.08:22:29.27#ibcon#about to read 3, iclass 16, count 0 2006.217.08:22:29.31#ibcon#read 3, iclass 16, count 0 2006.217.08:22:29.31#ibcon#about to read 4, iclass 16, count 0 2006.217.08:22:29.31#ibcon#read 4, iclass 16, count 0 2006.217.08:22:29.31#ibcon#about to read 5, iclass 16, count 0 2006.217.08:22:29.31#ibcon#read 5, iclass 16, count 0 2006.217.08:22:29.31#ibcon#about to read 6, iclass 16, count 0 2006.217.08:22:29.31#ibcon#read 6, iclass 16, count 0 2006.217.08:22:29.31#ibcon#end of sib2, iclass 16, count 0 2006.217.08:22:29.31#ibcon#*after write, iclass 16, count 0 2006.217.08:22:29.31#ibcon#*before return 0, iclass 16, count 0 2006.217.08:22:29.31#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.217.08:22:29.31#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.217.08:22:29.31#ibcon#about to clear, iclass 16 cls_cnt 0 2006.217.08:22:29.31#ibcon#cleared, iclass 16 cls_cnt 0 2006.217.08:22:29.31$vc4f8/va=5,7 2006.217.08:22:29.31#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.217.08:22:29.31#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.217.08:22:29.31#ibcon#ireg 11 cls_cnt 2 2006.217.08:22:29.31#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.217.08:22:29.37#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.217.08:22:29.37#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.217.08:22:29.37#ibcon#enter wrdev, iclass 18, count 2 2006.217.08:22:29.37#ibcon#first serial, iclass 18, count 2 2006.217.08:22:29.37#ibcon#enter sib2, iclass 18, count 2 2006.217.08:22:29.37#ibcon#flushed, iclass 18, count 2 2006.217.08:22:29.37#ibcon#about to write, iclass 18, count 2 2006.217.08:22:29.37#ibcon#wrote, iclass 18, count 2 2006.217.08:22:29.37#ibcon#about to read 3, iclass 18, count 2 2006.217.08:22:29.39#ibcon#read 3, iclass 18, count 2 2006.217.08:22:29.39#ibcon#about to read 4, iclass 18, count 2 2006.217.08:22:29.39#ibcon#read 4, iclass 18, count 2 2006.217.08:22:29.39#ibcon#about to read 5, iclass 18, count 2 2006.217.08:22:29.39#ibcon#read 5, iclass 18, count 2 2006.217.08:22:29.39#ibcon#about to read 6, iclass 18, count 2 2006.217.08:22:29.39#ibcon#read 6, iclass 18, count 2 2006.217.08:22:29.39#ibcon#end of sib2, iclass 18, count 2 2006.217.08:22:29.39#ibcon#*mode == 0, iclass 18, count 2 2006.217.08:22:29.39#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.217.08:22:29.39#ibcon#[25=AT05-07\r\n] 2006.217.08:22:29.39#ibcon#*before write, iclass 18, count 2 2006.217.08:22:29.39#ibcon#enter sib2, iclass 18, count 2 2006.217.08:22:29.39#ibcon#flushed, iclass 18, count 2 2006.217.08:22:29.39#ibcon#about to write, iclass 18, count 2 2006.217.08:22:29.39#ibcon#wrote, iclass 18, count 2 2006.217.08:22:29.39#ibcon#about to read 3, iclass 18, count 2 2006.217.08:22:29.42#ibcon#read 3, iclass 18, count 2 2006.217.08:22:29.42#ibcon#about to read 4, iclass 18, count 2 2006.217.08:22:29.42#ibcon#read 4, iclass 18, count 2 2006.217.08:22:29.42#ibcon#about to read 5, iclass 18, count 2 2006.217.08:22:29.42#ibcon#read 5, iclass 18, count 2 2006.217.08:22:29.42#ibcon#about to read 6, iclass 18, count 2 2006.217.08:22:29.42#ibcon#read 6, iclass 18, count 2 2006.217.08:22:29.42#ibcon#end of sib2, iclass 18, count 2 2006.217.08:22:29.42#ibcon#*after write, iclass 18, count 2 2006.217.08:22:29.42#ibcon#*before return 0, iclass 18, count 2 2006.217.08:22:29.42#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.217.08:22:29.42#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.217.08:22:29.42#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.217.08:22:29.42#ibcon#ireg 7 cls_cnt 0 2006.217.08:22:29.42#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.217.08:22:29.54#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.217.08:22:29.54#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.217.08:22:29.54#ibcon#enter wrdev, iclass 18, count 0 2006.217.08:22:29.54#ibcon#first serial, iclass 18, count 0 2006.217.08:22:29.54#ibcon#enter sib2, iclass 18, count 0 2006.217.08:22:29.54#ibcon#flushed, iclass 18, count 0 2006.217.08:22:29.54#ibcon#about to write, iclass 18, count 0 2006.217.08:22:29.54#ibcon#wrote, iclass 18, count 0 2006.217.08:22:29.54#ibcon#about to read 3, iclass 18, count 0 2006.217.08:22:29.56#ibcon#read 3, iclass 18, count 0 2006.217.08:22:29.56#ibcon#about to read 4, iclass 18, count 0 2006.217.08:22:29.56#ibcon#read 4, iclass 18, count 0 2006.217.08:22:29.56#ibcon#about to read 5, iclass 18, count 0 2006.217.08:22:29.56#ibcon#read 5, iclass 18, count 0 2006.217.08:22:29.56#ibcon#about to read 6, iclass 18, count 0 2006.217.08:22:29.56#ibcon#read 6, iclass 18, count 0 2006.217.08:22:29.56#ibcon#end of sib2, iclass 18, count 0 2006.217.08:22:29.56#ibcon#*mode == 0, iclass 18, count 0 2006.217.08:22:29.56#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.217.08:22:29.56#ibcon#[25=USB\r\n] 2006.217.08:22:29.56#ibcon#*before write, iclass 18, count 0 2006.217.08:22:29.56#ibcon#enter sib2, iclass 18, count 0 2006.217.08:22:29.56#ibcon#flushed, iclass 18, count 0 2006.217.08:22:29.56#ibcon#about to write, iclass 18, count 0 2006.217.08:22:29.56#ibcon#wrote, iclass 18, count 0 2006.217.08:22:29.56#ibcon#about to read 3, iclass 18, count 0 2006.217.08:22:29.59#ibcon#read 3, iclass 18, count 0 2006.217.08:22:29.59#ibcon#about to read 4, iclass 18, count 0 2006.217.08:22:29.59#ibcon#read 4, iclass 18, count 0 2006.217.08:22:29.59#ibcon#about to read 5, iclass 18, count 0 2006.217.08:22:29.59#ibcon#read 5, iclass 18, count 0 2006.217.08:22:29.59#ibcon#about to read 6, iclass 18, count 0 2006.217.08:22:29.59#ibcon#read 6, iclass 18, count 0 2006.217.08:22:29.59#ibcon#end of sib2, iclass 18, count 0 2006.217.08:22:29.59#ibcon#*after write, iclass 18, count 0 2006.217.08:22:29.59#ibcon#*before return 0, iclass 18, count 0 2006.217.08:22:29.59#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.217.08:22:29.59#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.217.08:22:29.59#ibcon#about to clear, iclass 18 cls_cnt 0 2006.217.08:22:29.59#ibcon#cleared, iclass 18 cls_cnt 0 2006.217.08:22:29.59$vc4f8/valo=6,772.99 2006.217.08:22:29.59#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.217.08:22:29.59#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.217.08:22:29.59#ibcon#ireg 17 cls_cnt 0 2006.217.08:22:29.59#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.217.08:22:29.59#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.217.08:22:29.59#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.217.08:22:29.59#ibcon#enter wrdev, iclass 20, count 0 2006.217.08:22:29.59#ibcon#first serial, iclass 20, count 0 2006.217.08:22:29.59#ibcon#enter sib2, iclass 20, count 0 2006.217.08:22:29.59#ibcon#flushed, iclass 20, count 0 2006.217.08:22:29.59#ibcon#about to write, iclass 20, count 0 2006.217.08:22:29.59#ibcon#wrote, iclass 20, count 0 2006.217.08:22:29.59#ibcon#about to read 3, iclass 20, count 0 2006.217.08:22:29.61#ibcon#read 3, iclass 20, count 0 2006.217.08:22:29.61#ibcon#about to read 4, iclass 20, count 0 2006.217.08:22:29.61#ibcon#read 4, iclass 20, count 0 2006.217.08:22:29.61#ibcon#about to read 5, iclass 20, count 0 2006.217.08:22:29.61#ibcon#read 5, iclass 20, count 0 2006.217.08:22:29.61#ibcon#about to read 6, iclass 20, count 0 2006.217.08:22:29.61#ibcon#read 6, iclass 20, count 0 2006.217.08:22:29.61#ibcon#end of sib2, iclass 20, count 0 2006.217.08:22:29.61#ibcon#*mode == 0, iclass 20, count 0 2006.217.08:22:29.61#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.217.08:22:29.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.217.08:22:29.61#ibcon#*before write, iclass 20, count 0 2006.217.08:22:29.61#ibcon#enter sib2, iclass 20, count 0 2006.217.08:22:29.61#ibcon#flushed, iclass 20, count 0 2006.217.08:22:29.61#ibcon#about to write, iclass 20, count 0 2006.217.08:22:29.61#ibcon#wrote, iclass 20, count 0 2006.217.08:22:29.61#ibcon#about to read 3, iclass 20, count 0 2006.217.08:22:29.65#ibcon#read 3, iclass 20, count 0 2006.217.08:22:29.65#ibcon#about to read 4, iclass 20, count 0 2006.217.08:22:29.65#ibcon#read 4, iclass 20, count 0 2006.217.08:22:29.65#ibcon#about to read 5, iclass 20, count 0 2006.217.08:22:29.65#ibcon#read 5, iclass 20, count 0 2006.217.08:22:29.65#ibcon#about to read 6, iclass 20, count 0 2006.217.08:22:29.65#ibcon#read 6, iclass 20, count 0 2006.217.08:22:29.65#ibcon#end of sib2, iclass 20, count 0 2006.217.08:22:29.65#ibcon#*after write, iclass 20, count 0 2006.217.08:22:29.65#ibcon#*before return 0, iclass 20, count 0 2006.217.08:22:29.65#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.217.08:22:29.65#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.217.08:22:29.65#ibcon#about to clear, iclass 20 cls_cnt 0 2006.217.08:22:29.65#ibcon#cleared, iclass 20 cls_cnt 0 2006.217.08:22:29.65$vc4f8/va=6,6 2006.217.08:22:29.65#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.217.08:22:29.65#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.217.08:22:29.65#ibcon#ireg 11 cls_cnt 2 2006.217.08:22:29.65#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.217.08:22:29.71#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.217.08:22:29.71#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.217.08:22:29.71#ibcon#enter wrdev, iclass 22, count 2 2006.217.08:22:29.71#ibcon#first serial, iclass 22, count 2 2006.217.08:22:29.71#ibcon#enter sib2, iclass 22, count 2 2006.217.08:22:29.71#ibcon#flushed, iclass 22, count 2 2006.217.08:22:29.71#ibcon#about to write, iclass 22, count 2 2006.217.08:22:29.71#ibcon#wrote, iclass 22, count 2 2006.217.08:22:29.71#ibcon#about to read 3, iclass 22, count 2 2006.217.08:22:29.73#ibcon#read 3, iclass 22, count 2 2006.217.08:22:29.73#ibcon#about to read 4, iclass 22, count 2 2006.217.08:22:29.73#ibcon#read 4, iclass 22, count 2 2006.217.08:22:29.73#ibcon#about to read 5, iclass 22, count 2 2006.217.08:22:29.73#ibcon#read 5, iclass 22, count 2 2006.217.08:22:29.73#ibcon#about to read 6, iclass 22, count 2 2006.217.08:22:29.73#ibcon#read 6, iclass 22, count 2 2006.217.08:22:29.73#ibcon#end of sib2, iclass 22, count 2 2006.217.08:22:29.73#ibcon#*mode == 0, iclass 22, count 2 2006.217.08:22:29.73#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.217.08:22:29.73#ibcon#[25=AT06-06\r\n] 2006.217.08:22:29.73#ibcon#*before write, iclass 22, count 2 2006.217.08:22:29.73#ibcon#enter sib2, iclass 22, count 2 2006.217.08:22:29.73#ibcon#flushed, iclass 22, count 2 2006.217.08:22:29.73#ibcon#about to write, iclass 22, count 2 2006.217.08:22:29.73#ibcon#wrote, iclass 22, count 2 2006.217.08:22:29.73#ibcon#about to read 3, iclass 22, count 2 2006.217.08:22:29.76#ibcon#read 3, iclass 22, count 2 2006.217.08:22:29.76#ibcon#about to read 4, iclass 22, count 2 2006.217.08:22:29.76#ibcon#read 4, iclass 22, count 2 2006.217.08:22:29.76#ibcon#about to read 5, iclass 22, count 2 2006.217.08:22:29.76#ibcon#read 5, iclass 22, count 2 2006.217.08:22:29.76#ibcon#about to read 6, iclass 22, count 2 2006.217.08:22:29.76#ibcon#read 6, iclass 22, count 2 2006.217.08:22:29.76#ibcon#end of sib2, iclass 22, count 2 2006.217.08:22:29.76#ibcon#*after write, iclass 22, count 2 2006.217.08:22:29.76#ibcon#*before return 0, iclass 22, count 2 2006.217.08:22:29.76#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.217.08:22:29.76#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.217.08:22:29.76#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.217.08:22:29.76#ibcon#ireg 7 cls_cnt 0 2006.217.08:22:29.76#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.217.08:22:29.88#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.217.08:22:29.88#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.217.08:22:29.88#ibcon#enter wrdev, iclass 22, count 0 2006.217.08:22:29.88#ibcon#first serial, iclass 22, count 0 2006.217.08:22:29.88#ibcon#enter sib2, iclass 22, count 0 2006.217.08:22:29.88#ibcon#flushed, iclass 22, count 0 2006.217.08:22:29.88#ibcon#about to write, iclass 22, count 0 2006.217.08:22:29.88#ibcon#wrote, iclass 22, count 0 2006.217.08:22:29.88#ibcon#about to read 3, iclass 22, count 0 2006.217.08:22:29.90#ibcon#read 3, iclass 22, count 0 2006.217.08:22:29.90#ibcon#about to read 4, iclass 22, count 0 2006.217.08:22:29.90#ibcon#read 4, iclass 22, count 0 2006.217.08:22:29.90#ibcon#about to read 5, iclass 22, count 0 2006.217.08:22:29.90#ibcon#read 5, iclass 22, count 0 2006.217.08:22:29.90#ibcon#about to read 6, iclass 22, count 0 2006.217.08:22:29.90#ibcon#read 6, iclass 22, count 0 2006.217.08:22:29.90#ibcon#end of sib2, iclass 22, count 0 2006.217.08:22:29.90#ibcon#*mode == 0, iclass 22, count 0 2006.217.08:22:29.90#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.217.08:22:29.90#ibcon#[25=USB\r\n] 2006.217.08:22:29.90#ibcon#*before write, iclass 22, count 0 2006.217.08:22:29.90#ibcon#enter sib2, iclass 22, count 0 2006.217.08:22:29.90#ibcon#flushed, iclass 22, count 0 2006.217.08:22:29.90#ibcon#about to write, iclass 22, count 0 2006.217.08:22:29.90#ibcon#wrote, iclass 22, count 0 2006.217.08:22:29.90#ibcon#about to read 3, iclass 22, count 0 2006.217.08:22:29.93#ibcon#read 3, iclass 22, count 0 2006.217.08:22:29.93#ibcon#about to read 4, iclass 22, count 0 2006.217.08:22:29.93#ibcon#read 4, iclass 22, count 0 2006.217.08:22:29.93#ibcon#about to read 5, iclass 22, count 0 2006.217.08:22:29.93#ibcon#read 5, iclass 22, count 0 2006.217.08:22:29.93#ibcon#about to read 6, iclass 22, count 0 2006.217.08:22:29.93#ibcon#read 6, iclass 22, count 0 2006.217.08:22:29.93#ibcon#end of sib2, iclass 22, count 0 2006.217.08:22:29.93#ibcon#*after write, iclass 22, count 0 2006.217.08:22:29.93#ibcon#*before return 0, iclass 22, count 0 2006.217.08:22:29.93#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.217.08:22:29.93#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.217.08:22:29.93#ibcon#about to clear, iclass 22 cls_cnt 0 2006.217.08:22:29.93#ibcon#cleared, iclass 22 cls_cnt 0 2006.217.08:22:29.93$vc4f8/valo=7,832.99 2006.217.08:22:29.93#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.217.08:22:29.93#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.217.08:22:29.93#ibcon#ireg 17 cls_cnt 0 2006.217.08:22:29.93#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.217.08:22:29.93#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.217.08:22:29.93#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.217.08:22:29.93#ibcon#enter wrdev, iclass 24, count 0 2006.217.08:22:29.93#ibcon#first serial, iclass 24, count 0 2006.217.08:22:29.93#ibcon#enter sib2, iclass 24, count 0 2006.217.08:22:29.93#ibcon#flushed, iclass 24, count 0 2006.217.08:22:29.93#ibcon#about to write, iclass 24, count 0 2006.217.08:22:29.93#ibcon#wrote, iclass 24, count 0 2006.217.08:22:29.93#ibcon#about to read 3, iclass 24, count 0 2006.217.08:22:29.95#ibcon#read 3, iclass 24, count 0 2006.217.08:22:29.95#ibcon#about to read 4, iclass 24, count 0 2006.217.08:22:29.95#ibcon#read 4, iclass 24, count 0 2006.217.08:22:29.95#ibcon#about to read 5, iclass 24, count 0 2006.217.08:22:29.95#ibcon#read 5, iclass 24, count 0 2006.217.08:22:29.95#ibcon#about to read 6, iclass 24, count 0 2006.217.08:22:29.95#ibcon#read 6, iclass 24, count 0 2006.217.08:22:29.95#ibcon#end of sib2, iclass 24, count 0 2006.217.08:22:29.95#ibcon#*mode == 0, iclass 24, count 0 2006.217.08:22:29.95#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.217.08:22:29.95#ibcon#[26=FRQ=07,832.99\r\n] 2006.217.08:22:29.95#ibcon#*before write, iclass 24, count 0 2006.217.08:22:29.95#ibcon#enter sib2, iclass 24, count 0 2006.217.08:22:29.95#ibcon#flushed, iclass 24, count 0 2006.217.08:22:29.95#ibcon#about to write, iclass 24, count 0 2006.217.08:22:29.95#ibcon#wrote, iclass 24, count 0 2006.217.08:22:29.95#ibcon#about to read 3, iclass 24, count 0 2006.217.08:22:29.99#ibcon#read 3, iclass 24, count 0 2006.217.08:22:29.99#ibcon#about to read 4, iclass 24, count 0 2006.217.08:22:29.99#ibcon#read 4, iclass 24, count 0 2006.217.08:22:29.99#ibcon#about to read 5, iclass 24, count 0 2006.217.08:22:29.99#ibcon#read 5, iclass 24, count 0 2006.217.08:22:29.99#ibcon#about to read 6, iclass 24, count 0 2006.217.08:22:29.99#ibcon#read 6, iclass 24, count 0 2006.217.08:22:29.99#ibcon#end of sib2, iclass 24, count 0 2006.217.08:22:29.99#ibcon#*after write, iclass 24, count 0 2006.217.08:22:29.99#ibcon#*before return 0, iclass 24, count 0 2006.217.08:22:29.99#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.217.08:22:29.99#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.217.08:22:29.99#ibcon#about to clear, iclass 24 cls_cnt 0 2006.217.08:22:29.99#ibcon#cleared, iclass 24 cls_cnt 0 2006.217.08:22:29.99$vc4f8/va=7,6 2006.217.08:22:29.99#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.217.08:22:29.99#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.217.08:22:29.99#ibcon#ireg 11 cls_cnt 2 2006.217.08:22:29.99#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.217.08:22:30.02#abcon#<5=/05 3.8 6.9 30.46 651008.6\r\n> 2006.217.08:22:30.04#abcon#{5=INTERFACE CLEAR} 2006.217.08:22:30.05#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.217.08:22:30.05#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.217.08:22:30.05#ibcon#enter wrdev, iclass 27, count 2 2006.217.08:22:30.05#ibcon#first serial, iclass 27, count 2 2006.217.08:22:30.05#ibcon#enter sib2, iclass 27, count 2 2006.217.08:22:30.05#ibcon#flushed, iclass 27, count 2 2006.217.08:22:30.05#ibcon#about to write, iclass 27, count 2 2006.217.08:22:30.05#ibcon#wrote, iclass 27, count 2 2006.217.08:22:30.05#ibcon#about to read 3, iclass 27, count 2 2006.217.08:22:30.07#ibcon#read 3, iclass 27, count 2 2006.217.08:22:30.07#ibcon#about to read 4, iclass 27, count 2 2006.217.08:22:30.07#ibcon#read 4, iclass 27, count 2 2006.217.08:22:30.07#ibcon#about to read 5, iclass 27, count 2 2006.217.08:22:30.07#ibcon#read 5, iclass 27, count 2 2006.217.08:22:30.07#ibcon#about to read 6, iclass 27, count 2 2006.217.08:22:30.07#ibcon#read 6, iclass 27, count 2 2006.217.08:22:30.07#ibcon#end of sib2, iclass 27, count 2 2006.217.08:22:30.07#ibcon#*mode == 0, iclass 27, count 2 2006.217.08:22:30.07#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.217.08:22:30.07#ibcon#[25=AT07-06\r\n] 2006.217.08:22:30.07#ibcon#*before write, iclass 27, count 2 2006.217.08:22:30.07#ibcon#enter sib2, iclass 27, count 2 2006.217.08:22:30.07#ibcon#flushed, iclass 27, count 2 2006.217.08:22:30.07#ibcon#about to write, iclass 27, count 2 2006.217.08:22:30.07#ibcon#wrote, iclass 27, count 2 2006.217.08:22:30.07#ibcon#about to read 3, iclass 27, count 2 2006.217.08:22:30.10#abcon#[5=S1D000X0/0*\r\n] 2006.217.08:22:30.10#ibcon#read 3, iclass 27, count 2 2006.217.08:22:30.10#ibcon#about to read 4, iclass 27, count 2 2006.217.08:22:30.10#ibcon#read 4, iclass 27, count 2 2006.217.08:22:30.10#ibcon#about to read 5, iclass 27, count 2 2006.217.08:22:30.10#ibcon#read 5, iclass 27, count 2 2006.217.08:22:30.10#ibcon#about to read 6, iclass 27, count 2 2006.217.08:22:30.10#ibcon#read 6, iclass 27, count 2 2006.217.08:22:30.10#ibcon#end of sib2, iclass 27, count 2 2006.217.08:22:30.10#ibcon#*after write, iclass 27, count 2 2006.217.08:22:30.10#ibcon#*before return 0, iclass 27, count 2 2006.217.08:22:30.10#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.217.08:22:30.10#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.217.08:22:30.10#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.217.08:22:30.10#ibcon#ireg 7 cls_cnt 0 2006.217.08:22:30.10#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.217.08:22:30.22#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.217.08:22:30.22#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.217.08:22:30.22#ibcon#enter wrdev, iclass 27, count 0 2006.217.08:22:30.22#ibcon#first serial, iclass 27, count 0 2006.217.08:22:30.22#ibcon#enter sib2, iclass 27, count 0 2006.217.08:22:30.22#ibcon#flushed, iclass 27, count 0 2006.217.08:22:30.22#ibcon#about to write, iclass 27, count 0 2006.217.08:22:30.22#ibcon#wrote, iclass 27, count 0 2006.217.08:22:30.22#ibcon#about to read 3, iclass 27, count 0 2006.217.08:22:30.24#ibcon#read 3, iclass 27, count 0 2006.217.08:22:30.24#ibcon#about to read 4, iclass 27, count 0 2006.217.08:22:30.24#ibcon#read 4, iclass 27, count 0 2006.217.08:22:30.24#ibcon#about to read 5, iclass 27, count 0 2006.217.08:22:30.24#ibcon#read 5, iclass 27, count 0 2006.217.08:22:30.24#ibcon#about to read 6, iclass 27, count 0 2006.217.08:22:30.24#ibcon#read 6, iclass 27, count 0 2006.217.08:22:30.24#ibcon#end of sib2, iclass 27, count 0 2006.217.08:22:30.24#ibcon#*mode == 0, iclass 27, count 0 2006.217.08:22:30.24#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.217.08:22:30.24#ibcon#[25=USB\r\n] 2006.217.08:22:30.24#ibcon#*before write, iclass 27, count 0 2006.217.08:22:30.24#ibcon#enter sib2, iclass 27, count 0 2006.217.08:22:30.24#ibcon#flushed, iclass 27, count 0 2006.217.08:22:30.24#ibcon#about to write, iclass 27, count 0 2006.217.08:22:30.24#ibcon#wrote, iclass 27, count 0 2006.217.08:22:30.24#ibcon#about to read 3, iclass 27, count 0 2006.217.08:22:30.27#ibcon#read 3, iclass 27, count 0 2006.217.08:22:30.27#ibcon#about to read 4, iclass 27, count 0 2006.217.08:22:30.27#ibcon#read 4, iclass 27, count 0 2006.217.08:22:30.27#ibcon#about to read 5, iclass 27, count 0 2006.217.08:22:30.27#ibcon#read 5, iclass 27, count 0 2006.217.08:22:30.27#ibcon#about to read 6, iclass 27, count 0 2006.217.08:22:30.27#ibcon#read 6, iclass 27, count 0 2006.217.08:22:30.27#ibcon#end of sib2, iclass 27, count 0 2006.217.08:22:30.27#ibcon#*after write, iclass 27, count 0 2006.217.08:22:30.27#ibcon#*before return 0, iclass 27, count 0 2006.217.08:22:30.27#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.217.08:22:30.27#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.217.08:22:30.27#ibcon#about to clear, iclass 27 cls_cnt 0 2006.217.08:22:30.27#ibcon#cleared, iclass 27 cls_cnt 0 2006.217.08:22:30.27$vc4f8/valo=8,852.99 2006.217.08:22:30.27#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.217.08:22:30.27#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.217.08:22:30.27#ibcon#ireg 17 cls_cnt 0 2006.217.08:22:30.27#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.217.08:22:30.27#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.217.08:22:30.27#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.217.08:22:30.27#ibcon#enter wrdev, iclass 32, count 0 2006.217.08:22:30.27#ibcon#first serial, iclass 32, count 0 2006.217.08:22:30.27#ibcon#enter sib2, iclass 32, count 0 2006.217.08:22:30.27#ibcon#flushed, iclass 32, count 0 2006.217.08:22:30.27#ibcon#about to write, iclass 32, count 0 2006.217.08:22:30.27#ibcon#wrote, iclass 32, count 0 2006.217.08:22:30.27#ibcon#about to read 3, iclass 32, count 0 2006.217.08:22:30.29#ibcon#read 3, iclass 32, count 0 2006.217.08:22:30.29#ibcon#about to read 4, iclass 32, count 0 2006.217.08:22:30.29#ibcon#read 4, iclass 32, count 0 2006.217.08:22:30.29#ibcon#about to read 5, iclass 32, count 0 2006.217.08:22:30.29#ibcon#read 5, iclass 32, count 0 2006.217.08:22:30.29#ibcon#about to read 6, iclass 32, count 0 2006.217.08:22:30.29#ibcon#read 6, iclass 32, count 0 2006.217.08:22:30.29#ibcon#end of sib2, iclass 32, count 0 2006.217.08:22:30.29#ibcon#*mode == 0, iclass 32, count 0 2006.217.08:22:30.29#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.217.08:22:30.29#ibcon#[26=FRQ=08,852.99\r\n] 2006.217.08:22:30.29#ibcon#*before write, iclass 32, count 0 2006.217.08:22:30.29#ibcon#enter sib2, iclass 32, count 0 2006.217.08:22:30.29#ibcon#flushed, iclass 32, count 0 2006.217.08:22:30.29#ibcon#about to write, iclass 32, count 0 2006.217.08:22:30.29#ibcon#wrote, iclass 32, count 0 2006.217.08:22:30.29#ibcon#about to read 3, iclass 32, count 0 2006.217.08:22:30.33#ibcon#read 3, iclass 32, count 0 2006.217.08:22:30.33#ibcon#about to read 4, iclass 32, count 0 2006.217.08:22:30.33#ibcon#read 4, iclass 32, count 0 2006.217.08:22:30.33#ibcon#about to read 5, iclass 32, count 0 2006.217.08:22:30.33#ibcon#read 5, iclass 32, count 0 2006.217.08:22:30.33#ibcon#about to read 6, iclass 32, count 0 2006.217.08:22:30.33#ibcon#read 6, iclass 32, count 0 2006.217.08:22:30.33#ibcon#end of sib2, iclass 32, count 0 2006.217.08:22:30.33#ibcon#*after write, iclass 32, count 0 2006.217.08:22:30.33#ibcon#*before return 0, iclass 32, count 0 2006.217.08:22:30.33#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.217.08:22:30.33#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.217.08:22:30.33#ibcon#about to clear, iclass 32 cls_cnt 0 2006.217.08:22:30.33#ibcon#cleared, iclass 32 cls_cnt 0 2006.217.08:22:30.33$vc4f8/va=8,7 2006.217.08:22:30.33#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.217.08:22:30.33#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.217.08:22:30.33#ibcon#ireg 11 cls_cnt 2 2006.217.08:22:30.33#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.217.08:22:30.39#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.217.08:22:30.39#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.217.08:22:30.39#ibcon#enter wrdev, iclass 34, count 2 2006.217.08:22:30.39#ibcon#first serial, iclass 34, count 2 2006.217.08:22:30.39#ibcon#enter sib2, iclass 34, count 2 2006.217.08:22:30.39#ibcon#flushed, iclass 34, count 2 2006.217.08:22:30.39#ibcon#about to write, iclass 34, count 2 2006.217.08:22:30.39#ibcon#wrote, iclass 34, count 2 2006.217.08:22:30.39#ibcon#about to read 3, iclass 34, count 2 2006.217.08:22:30.41#ibcon#read 3, iclass 34, count 2 2006.217.08:22:30.41#ibcon#about to read 4, iclass 34, count 2 2006.217.08:22:30.41#ibcon#read 4, iclass 34, count 2 2006.217.08:22:30.41#ibcon#about to read 5, iclass 34, count 2 2006.217.08:22:30.41#ibcon#read 5, iclass 34, count 2 2006.217.08:22:30.41#ibcon#about to read 6, iclass 34, count 2 2006.217.08:22:30.41#ibcon#read 6, iclass 34, count 2 2006.217.08:22:30.41#ibcon#end of sib2, iclass 34, count 2 2006.217.08:22:30.41#ibcon#*mode == 0, iclass 34, count 2 2006.217.08:22:30.41#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.217.08:22:30.41#ibcon#[25=AT08-07\r\n] 2006.217.08:22:30.41#ibcon#*before write, iclass 34, count 2 2006.217.08:22:30.41#ibcon#enter sib2, iclass 34, count 2 2006.217.08:22:30.41#ibcon#flushed, iclass 34, count 2 2006.217.08:22:30.41#ibcon#about to write, iclass 34, count 2 2006.217.08:22:30.41#ibcon#wrote, iclass 34, count 2 2006.217.08:22:30.41#ibcon#about to read 3, iclass 34, count 2 2006.217.08:22:30.44#ibcon#read 3, iclass 34, count 2 2006.217.08:22:30.44#ibcon#about to read 4, iclass 34, count 2 2006.217.08:22:30.44#ibcon#read 4, iclass 34, count 2 2006.217.08:22:30.44#ibcon#about to read 5, iclass 34, count 2 2006.217.08:22:30.44#ibcon#read 5, iclass 34, count 2 2006.217.08:22:30.44#ibcon#about to read 6, iclass 34, count 2 2006.217.08:22:30.44#ibcon#read 6, iclass 34, count 2 2006.217.08:22:30.44#ibcon#end of sib2, iclass 34, count 2 2006.217.08:22:30.44#ibcon#*after write, iclass 34, count 2 2006.217.08:22:30.44#ibcon#*before return 0, iclass 34, count 2 2006.217.08:22:30.44#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.217.08:22:30.44#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.217.08:22:30.44#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.217.08:22:30.44#ibcon#ireg 7 cls_cnt 0 2006.217.08:22:30.44#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.217.08:22:30.56#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.217.08:22:30.56#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.217.08:22:30.56#ibcon#enter wrdev, iclass 34, count 0 2006.217.08:22:30.56#ibcon#first serial, iclass 34, count 0 2006.217.08:22:30.56#ibcon#enter sib2, iclass 34, count 0 2006.217.08:22:30.56#ibcon#flushed, iclass 34, count 0 2006.217.08:22:30.56#ibcon#about to write, iclass 34, count 0 2006.217.08:22:30.56#ibcon#wrote, iclass 34, count 0 2006.217.08:22:30.56#ibcon#about to read 3, iclass 34, count 0 2006.217.08:22:30.58#ibcon#read 3, iclass 34, count 0 2006.217.08:22:30.58#ibcon#about to read 4, iclass 34, count 0 2006.217.08:22:30.58#ibcon#read 4, iclass 34, count 0 2006.217.08:22:30.58#ibcon#about to read 5, iclass 34, count 0 2006.217.08:22:30.58#ibcon#read 5, iclass 34, count 0 2006.217.08:22:30.58#ibcon#about to read 6, iclass 34, count 0 2006.217.08:22:30.58#ibcon#read 6, iclass 34, count 0 2006.217.08:22:30.58#ibcon#end of sib2, iclass 34, count 0 2006.217.08:22:30.58#ibcon#*mode == 0, iclass 34, count 0 2006.217.08:22:30.58#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.217.08:22:30.58#ibcon#[25=USB\r\n] 2006.217.08:22:30.58#ibcon#*before write, iclass 34, count 0 2006.217.08:22:30.58#ibcon#enter sib2, iclass 34, count 0 2006.217.08:22:30.58#ibcon#flushed, iclass 34, count 0 2006.217.08:22:30.58#ibcon#about to write, iclass 34, count 0 2006.217.08:22:30.58#ibcon#wrote, iclass 34, count 0 2006.217.08:22:30.58#ibcon#about to read 3, iclass 34, count 0 2006.217.08:22:30.61#ibcon#read 3, iclass 34, count 0 2006.217.08:22:30.61#ibcon#about to read 4, iclass 34, count 0 2006.217.08:22:30.61#ibcon#read 4, iclass 34, count 0 2006.217.08:22:30.61#ibcon#about to read 5, iclass 34, count 0 2006.217.08:22:30.61#ibcon#read 5, iclass 34, count 0 2006.217.08:22:30.61#ibcon#about to read 6, iclass 34, count 0 2006.217.08:22:30.61#ibcon#read 6, iclass 34, count 0 2006.217.08:22:30.61#ibcon#end of sib2, iclass 34, count 0 2006.217.08:22:30.61#ibcon#*after write, iclass 34, count 0 2006.217.08:22:30.61#ibcon#*before return 0, iclass 34, count 0 2006.217.08:22:30.61#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.217.08:22:30.61#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.217.08:22:30.61#ibcon#about to clear, iclass 34 cls_cnt 0 2006.217.08:22:30.61#ibcon#cleared, iclass 34 cls_cnt 0 2006.217.08:22:30.61$vc4f8/vblo=1,632.99 2006.217.08:22:30.61#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.217.08:22:30.61#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.217.08:22:30.61#ibcon#ireg 17 cls_cnt 0 2006.217.08:22:30.61#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.217.08:22:30.61#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.217.08:22:30.61#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.217.08:22:30.61#ibcon#enter wrdev, iclass 36, count 0 2006.217.08:22:30.61#ibcon#first serial, iclass 36, count 0 2006.217.08:22:30.61#ibcon#enter sib2, iclass 36, count 0 2006.217.08:22:30.61#ibcon#flushed, iclass 36, count 0 2006.217.08:22:30.61#ibcon#about to write, iclass 36, count 0 2006.217.08:22:30.61#ibcon#wrote, iclass 36, count 0 2006.217.08:22:30.61#ibcon#about to read 3, iclass 36, count 0 2006.217.08:22:30.63#ibcon#read 3, iclass 36, count 0 2006.217.08:22:30.63#ibcon#about to read 4, iclass 36, count 0 2006.217.08:22:30.63#ibcon#read 4, iclass 36, count 0 2006.217.08:22:30.63#ibcon#about to read 5, iclass 36, count 0 2006.217.08:22:30.63#ibcon#read 5, iclass 36, count 0 2006.217.08:22:30.63#ibcon#about to read 6, iclass 36, count 0 2006.217.08:22:30.63#ibcon#read 6, iclass 36, count 0 2006.217.08:22:30.63#ibcon#end of sib2, iclass 36, count 0 2006.217.08:22:30.63#ibcon#*mode == 0, iclass 36, count 0 2006.217.08:22:30.63#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.217.08:22:30.63#ibcon#[28=FRQ=01,632.99\r\n] 2006.217.08:22:30.63#ibcon#*before write, iclass 36, count 0 2006.217.08:22:30.63#ibcon#enter sib2, iclass 36, count 0 2006.217.08:22:30.63#ibcon#flushed, iclass 36, count 0 2006.217.08:22:30.63#ibcon#about to write, iclass 36, count 0 2006.217.08:22:30.63#ibcon#wrote, iclass 36, count 0 2006.217.08:22:30.63#ibcon#about to read 3, iclass 36, count 0 2006.217.08:22:30.67#ibcon#read 3, iclass 36, count 0 2006.217.08:22:30.67#ibcon#about to read 4, iclass 36, count 0 2006.217.08:22:30.67#ibcon#read 4, iclass 36, count 0 2006.217.08:22:30.67#ibcon#about to read 5, iclass 36, count 0 2006.217.08:22:30.67#ibcon#read 5, iclass 36, count 0 2006.217.08:22:30.67#ibcon#about to read 6, iclass 36, count 0 2006.217.08:22:30.67#ibcon#read 6, iclass 36, count 0 2006.217.08:22:30.67#ibcon#end of sib2, iclass 36, count 0 2006.217.08:22:30.67#ibcon#*after write, iclass 36, count 0 2006.217.08:22:30.67#ibcon#*before return 0, iclass 36, count 0 2006.217.08:22:30.67#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.217.08:22:30.67#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.217.08:22:30.67#ibcon#about to clear, iclass 36 cls_cnt 0 2006.217.08:22:30.67#ibcon#cleared, iclass 36 cls_cnt 0 2006.217.08:22:30.67$vc4f8/vb=1,4 2006.217.08:22:30.67#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.217.08:22:30.67#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.217.08:22:30.67#ibcon#ireg 11 cls_cnt 2 2006.217.08:22:30.67#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.217.08:22:30.67#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.217.08:22:30.67#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.217.08:22:30.67#ibcon#enter wrdev, iclass 38, count 2 2006.217.08:22:30.67#ibcon#first serial, iclass 38, count 2 2006.217.08:22:30.67#ibcon#enter sib2, iclass 38, count 2 2006.217.08:22:30.67#ibcon#flushed, iclass 38, count 2 2006.217.08:22:30.67#ibcon#about to write, iclass 38, count 2 2006.217.08:22:30.67#ibcon#wrote, iclass 38, count 2 2006.217.08:22:30.67#ibcon#about to read 3, iclass 38, count 2 2006.217.08:22:30.69#ibcon#read 3, iclass 38, count 2 2006.217.08:22:30.69#ibcon#about to read 4, iclass 38, count 2 2006.217.08:22:30.69#ibcon#read 4, iclass 38, count 2 2006.217.08:22:30.69#ibcon#about to read 5, iclass 38, count 2 2006.217.08:22:30.69#ibcon#read 5, iclass 38, count 2 2006.217.08:22:30.69#ibcon#about to read 6, iclass 38, count 2 2006.217.08:22:30.69#ibcon#read 6, iclass 38, count 2 2006.217.08:22:30.69#ibcon#end of sib2, iclass 38, count 2 2006.217.08:22:30.69#ibcon#*mode == 0, iclass 38, count 2 2006.217.08:22:30.69#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.217.08:22:30.69#ibcon#[27=AT01-04\r\n] 2006.217.08:22:30.69#ibcon#*before write, iclass 38, count 2 2006.217.08:22:30.69#ibcon#enter sib2, iclass 38, count 2 2006.217.08:22:30.69#ibcon#flushed, iclass 38, count 2 2006.217.08:22:30.69#ibcon#about to write, iclass 38, count 2 2006.217.08:22:30.69#ibcon#wrote, iclass 38, count 2 2006.217.08:22:30.69#ibcon#about to read 3, iclass 38, count 2 2006.217.08:22:30.72#ibcon#read 3, iclass 38, count 2 2006.217.08:22:30.72#ibcon#about to read 4, iclass 38, count 2 2006.217.08:22:30.72#ibcon#read 4, iclass 38, count 2 2006.217.08:22:30.72#ibcon#about to read 5, iclass 38, count 2 2006.217.08:22:30.72#ibcon#read 5, iclass 38, count 2 2006.217.08:22:30.72#ibcon#about to read 6, iclass 38, count 2 2006.217.08:22:30.72#ibcon#read 6, iclass 38, count 2 2006.217.08:22:30.72#ibcon#end of sib2, iclass 38, count 2 2006.217.08:22:30.72#ibcon#*after write, iclass 38, count 2 2006.217.08:22:30.72#ibcon#*before return 0, iclass 38, count 2 2006.217.08:22:30.72#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.217.08:22:30.72#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.217.08:22:30.72#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.217.08:22:30.72#ibcon#ireg 7 cls_cnt 0 2006.217.08:22:30.72#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.217.08:22:30.84#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.217.08:22:30.84#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.217.08:22:30.84#ibcon#enter wrdev, iclass 38, count 0 2006.217.08:22:30.84#ibcon#first serial, iclass 38, count 0 2006.217.08:22:30.84#ibcon#enter sib2, iclass 38, count 0 2006.217.08:22:30.84#ibcon#flushed, iclass 38, count 0 2006.217.08:22:30.84#ibcon#about to write, iclass 38, count 0 2006.217.08:22:30.84#ibcon#wrote, iclass 38, count 0 2006.217.08:22:30.84#ibcon#about to read 3, iclass 38, count 0 2006.217.08:22:30.86#ibcon#read 3, iclass 38, count 0 2006.217.08:22:30.86#ibcon#about to read 4, iclass 38, count 0 2006.217.08:22:30.86#ibcon#read 4, iclass 38, count 0 2006.217.08:22:30.86#ibcon#about to read 5, iclass 38, count 0 2006.217.08:22:30.86#ibcon#read 5, iclass 38, count 0 2006.217.08:22:30.86#ibcon#about to read 6, iclass 38, count 0 2006.217.08:22:30.86#ibcon#read 6, iclass 38, count 0 2006.217.08:22:30.86#ibcon#end of sib2, iclass 38, count 0 2006.217.08:22:30.86#ibcon#*mode == 0, iclass 38, count 0 2006.217.08:22:30.86#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.217.08:22:30.86#ibcon#[27=USB\r\n] 2006.217.08:22:30.86#ibcon#*before write, iclass 38, count 0 2006.217.08:22:30.86#ibcon#enter sib2, iclass 38, count 0 2006.217.08:22:30.86#ibcon#flushed, iclass 38, count 0 2006.217.08:22:30.86#ibcon#about to write, iclass 38, count 0 2006.217.08:22:30.86#ibcon#wrote, iclass 38, count 0 2006.217.08:22:30.86#ibcon#about to read 3, iclass 38, count 0 2006.217.08:22:30.89#ibcon#read 3, iclass 38, count 0 2006.217.08:22:30.89#ibcon#about to read 4, iclass 38, count 0 2006.217.08:22:30.89#ibcon#read 4, iclass 38, count 0 2006.217.08:22:30.89#ibcon#about to read 5, iclass 38, count 0 2006.217.08:22:30.89#ibcon#read 5, iclass 38, count 0 2006.217.08:22:30.89#ibcon#about to read 6, iclass 38, count 0 2006.217.08:22:30.89#ibcon#read 6, iclass 38, count 0 2006.217.08:22:30.89#ibcon#end of sib2, iclass 38, count 0 2006.217.08:22:30.89#ibcon#*after write, iclass 38, count 0 2006.217.08:22:30.89#ibcon#*before return 0, iclass 38, count 0 2006.217.08:22:30.89#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.217.08:22:30.89#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.217.08:22:30.89#ibcon#about to clear, iclass 38 cls_cnt 0 2006.217.08:22:30.89#ibcon#cleared, iclass 38 cls_cnt 0 2006.217.08:22:30.89$vc4f8/vblo=2,640.99 2006.217.08:22:30.89#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.217.08:22:30.89#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.217.08:22:30.89#ibcon#ireg 17 cls_cnt 0 2006.217.08:22:30.89#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.217.08:22:30.89#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.217.08:22:30.89#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.217.08:22:30.89#ibcon#enter wrdev, iclass 40, count 0 2006.217.08:22:30.89#ibcon#first serial, iclass 40, count 0 2006.217.08:22:30.89#ibcon#enter sib2, iclass 40, count 0 2006.217.08:22:30.89#ibcon#flushed, iclass 40, count 0 2006.217.08:22:30.89#ibcon#about to write, iclass 40, count 0 2006.217.08:22:30.89#ibcon#wrote, iclass 40, count 0 2006.217.08:22:30.89#ibcon#about to read 3, iclass 40, count 0 2006.217.08:22:30.91#ibcon#read 3, iclass 40, count 0 2006.217.08:22:30.91#ibcon#about to read 4, iclass 40, count 0 2006.217.08:22:30.91#ibcon#read 4, iclass 40, count 0 2006.217.08:22:30.91#ibcon#about to read 5, iclass 40, count 0 2006.217.08:22:30.91#ibcon#read 5, iclass 40, count 0 2006.217.08:22:30.91#ibcon#about to read 6, iclass 40, count 0 2006.217.08:22:30.91#ibcon#read 6, iclass 40, count 0 2006.217.08:22:30.91#ibcon#end of sib2, iclass 40, count 0 2006.217.08:22:30.91#ibcon#*mode == 0, iclass 40, count 0 2006.217.08:22:30.91#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.217.08:22:30.91#ibcon#[28=FRQ=02,640.99\r\n] 2006.217.08:22:30.91#ibcon#*before write, iclass 40, count 0 2006.217.08:22:30.91#ibcon#enter sib2, iclass 40, count 0 2006.217.08:22:30.91#ibcon#flushed, iclass 40, count 0 2006.217.08:22:30.91#ibcon#about to write, iclass 40, count 0 2006.217.08:22:30.91#ibcon#wrote, iclass 40, count 0 2006.217.08:22:30.91#ibcon#about to read 3, iclass 40, count 0 2006.217.08:22:30.95#ibcon#read 3, iclass 40, count 0 2006.217.08:22:30.95#ibcon#about to read 4, iclass 40, count 0 2006.217.08:22:30.95#ibcon#read 4, iclass 40, count 0 2006.217.08:22:30.95#ibcon#about to read 5, iclass 40, count 0 2006.217.08:22:30.95#ibcon#read 5, iclass 40, count 0 2006.217.08:22:30.95#ibcon#about to read 6, iclass 40, count 0 2006.217.08:22:30.95#ibcon#read 6, iclass 40, count 0 2006.217.08:22:30.95#ibcon#end of sib2, iclass 40, count 0 2006.217.08:22:30.95#ibcon#*after write, iclass 40, count 0 2006.217.08:22:30.95#ibcon#*before return 0, iclass 40, count 0 2006.217.08:22:30.95#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.217.08:22:30.95#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.217.08:22:30.95#ibcon#about to clear, iclass 40 cls_cnt 0 2006.217.08:22:30.95#ibcon#cleared, iclass 40 cls_cnt 0 2006.217.08:22:30.95$vc4f8/vb=2,4 2006.217.08:22:30.95#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.217.08:22:30.95#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.217.08:22:30.95#ibcon#ireg 11 cls_cnt 2 2006.217.08:22:30.95#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.217.08:22:31.01#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.217.08:22:31.01#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.217.08:22:31.01#ibcon#enter wrdev, iclass 4, count 2 2006.217.08:22:31.01#ibcon#first serial, iclass 4, count 2 2006.217.08:22:31.01#ibcon#enter sib2, iclass 4, count 2 2006.217.08:22:31.01#ibcon#flushed, iclass 4, count 2 2006.217.08:22:31.01#ibcon#about to write, iclass 4, count 2 2006.217.08:22:31.01#ibcon#wrote, iclass 4, count 2 2006.217.08:22:31.01#ibcon#about to read 3, iclass 4, count 2 2006.217.08:22:31.03#ibcon#read 3, iclass 4, count 2 2006.217.08:22:31.03#ibcon#about to read 4, iclass 4, count 2 2006.217.08:22:31.03#ibcon#read 4, iclass 4, count 2 2006.217.08:22:31.03#ibcon#about to read 5, iclass 4, count 2 2006.217.08:22:31.03#ibcon#read 5, iclass 4, count 2 2006.217.08:22:31.03#ibcon#about to read 6, iclass 4, count 2 2006.217.08:22:31.03#ibcon#read 6, iclass 4, count 2 2006.217.08:22:31.03#ibcon#end of sib2, iclass 4, count 2 2006.217.08:22:31.03#ibcon#*mode == 0, iclass 4, count 2 2006.217.08:22:31.03#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.217.08:22:31.03#ibcon#[27=AT02-04\r\n] 2006.217.08:22:31.03#ibcon#*before write, iclass 4, count 2 2006.217.08:22:31.03#ibcon#enter sib2, iclass 4, count 2 2006.217.08:22:31.03#ibcon#flushed, iclass 4, count 2 2006.217.08:22:31.03#ibcon#about to write, iclass 4, count 2 2006.217.08:22:31.03#ibcon#wrote, iclass 4, count 2 2006.217.08:22:31.03#ibcon#about to read 3, iclass 4, count 2 2006.217.08:22:31.06#ibcon#read 3, iclass 4, count 2 2006.217.08:22:31.06#ibcon#about to read 4, iclass 4, count 2 2006.217.08:22:31.06#ibcon#read 4, iclass 4, count 2 2006.217.08:22:31.06#ibcon#about to read 5, iclass 4, count 2 2006.217.08:22:31.06#ibcon#read 5, iclass 4, count 2 2006.217.08:22:31.06#ibcon#about to read 6, iclass 4, count 2 2006.217.08:22:31.06#ibcon#read 6, iclass 4, count 2 2006.217.08:22:31.06#ibcon#end of sib2, iclass 4, count 2 2006.217.08:22:31.06#ibcon#*after write, iclass 4, count 2 2006.217.08:22:31.06#ibcon#*before return 0, iclass 4, count 2 2006.217.08:22:31.06#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.217.08:22:31.06#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.217.08:22:31.06#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.217.08:22:31.06#ibcon#ireg 7 cls_cnt 0 2006.217.08:22:31.06#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.217.08:22:31.18#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.217.08:22:31.18#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.217.08:22:31.18#ibcon#enter wrdev, iclass 4, count 0 2006.217.08:22:31.18#ibcon#first serial, iclass 4, count 0 2006.217.08:22:31.18#ibcon#enter sib2, iclass 4, count 0 2006.217.08:22:31.18#ibcon#flushed, iclass 4, count 0 2006.217.08:22:31.18#ibcon#about to write, iclass 4, count 0 2006.217.08:22:31.18#ibcon#wrote, iclass 4, count 0 2006.217.08:22:31.18#ibcon#about to read 3, iclass 4, count 0 2006.217.08:22:31.20#ibcon#read 3, iclass 4, count 0 2006.217.08:22:31.20#ibcon#about to read 4, iclass 4, count 0 2006.217.08:22:31.20#ibcon#read 4, iclass 4, count 0 2006.217.08:22:31.20#ibcon#about to read 5, iclass 4, count 0 2006.217.08:22:31.20#ibcon#read 5, iclass 4, count 0 2006.217.08:22:31.20#ibcon#about to read 6, iclass 4, count 0 2006.217.08:22:31.20#ibcon#read 6, iclass 4, count 0 2006.217.08:22:31.20#ibcon#end of sib2, iclass 4, count 0 2006.217.08:22:31.20#ibcon#*mode == 0, iclass 4, count 0 2006.217.08:22:31.20#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.217.08:22:31.20#ibcon#[27=USB\r\n] 2006.217.08:22:31.20#ibcon#*before write, iclass 4, count 0 2006.217.08:22:31.20#ibcon#enter sib2, iclass 4, count 0 2006.217.08:22:31.20#ibcon#flushed, iclass 4, count 0 2006.217.08:22:31.20#ibcon#about to write, iclass 4, count 0 2006.217.08:22:31.20#ibcon#wrote, iclass 4, count 0 2006.217.08:22:31.20#ibcon#about to read 3, iclass 4, count 0 2006.217.08:22:31.23#ibcon#read 3, iclass 4, count 0 2006.217.08:22:31.23#ibcon#about to read 4, iclass 4, count 0 2006.217.08:22:31.23#ibcon#read 4, iclass 4, count 0 2006.217.08:22:31.23#ibcon#about to read 5, iclass 4, count 0 2006.217.08:22:31.23#ibcon#read 5, iclass 4, count 0 2006.217.08:22:31.23#ibcon#about to read 6, iclass 4, count 0 2006.217.08:22:31.23#ibcon#read 6, iclass 4, count 0 2006.217.08:22:31.23#ibcon#end of sib2, iclass 4, count 0 2006.217.08:22:31.23#ibcon#*after write, iclass 4, count 0 2006.217.08:22:31.23#ibcon#*before return 0, iclass 4, count 0 2006.217.08:22:31.23#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.217.08:22:31.23#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.217.08:22:31.23#ibcon#about to clear, iclass 4 cls_cnt 0 2006.217.08:22:31.23#ibcon#cleared, iclass 4 cls_cnt 0 2006.217.08:22:31.23$vc4f8/vblo=3,656.99 2006.217.08:22:31.23#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.217.08:22:31.23#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.217.08:22:31.23#ibcon#ireg 17 cls_cnt 0 2006.217.08:22:31.23#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.217.08:22:31.23#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.217.08:22:31.23#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.217.08:22:31.23#ibcon#enter wrdev, iclass 6, count 0 2006.217.08:22:31.23#ibcon#first serial, iclass 6, count 0 2006.217.08:22:31.23#ibcon#enter sib2, iclass 6, count 0 2006.217.08:22:31.23#ibcon#flushed, iclass 6, count 0 2006.217.08:22:31.23#ibcon#about to write, iclass 6, count 0 2006.217.08:22:31.23#ibcon#wrote, iclass 6, count 0 2006.217.08:22:31.23#ibcon#about to read 3, iclass 6, count 0 2006.217.08:22:31.25#ibcon#read 3, iclass 6, count 0 2006.217.08:22:31.25#ibcon#about to read 4, iclass 6, count 0 2006.217.08:22:31.25#ibcon#read 4, iclass 6, count 0 2006.217.08:22:31.25#ibcon#about to read 5, iclass 6, count 0 2006.217.08:22:31.25#ibcon#read 5, iclass 6, count 0 2006.217.08:22:31.25#ibcon#about to read 6, iclass 6, count 0 2006.217.08:22:31.25#ibcon#read 6, iclass 6, count 0 2006.217.08:22:31.25#ibcon#end of sib2, iclass 6, count 0 2006.217.08:22:31.25#ibcon#*mode == 0, iclass 6, count 0 2006.217.08:22:31.25#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.217.08:22:31.25#ibcon#[28=FRQ=03,656.99\r\n] 2006.217.08:22:31.25#ibcon#*before write, iclass 6, count 0 2006.217.08:22:31.25#ibcon#enter sib2, iclass 6, count 0 2006.217.08:22:31.25#ibcon#flushed, iclass 6, count 0 2006.217.08:22:31.25#ibcon#about to write, iclass 6, count 0 2006.217.08:22:31.25#ibcon#wrote, iclass 6, count 0 2006.217.08:22:31.25#ibcon#about to read 3, iclass 6, count 0 2006.217.08:22:31.29#ibcon#read 3, iclass 6, count 0 2006.217.08:22:31.29#ibcon#about to read 4, iclass 6, count 0 2006.217.08:22:31.29#ibcon#read 4, iclass 6, count 0 2006.217.08:22:31.29#ibcon#about to read 5, iclass 6, count 0 2006.217.08:22:31.29#ibcon#read 5, iclass 6, count 0 2006.217.08:22:31.29#ibcon#about to read 6, iclass 6, count 0 2006.217.08:22:31.29#ibcon#read 6, iclass 6, count 0 2006.217.08:22:31.29#ibcon#end of sib2, iclass 6, count 0 2006.217.08:22:31.29#ibcon#*after write, iclass 6, count 0 2006.217.08:22:31.29#ibcon#*before return 0, iclass 6, count 0 2006.217.08:22:31.29#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.217.08:22:31.29#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.217.08:22:31.29#ibcon#about to clear, iclass 6 cls_cnt 0 2006.217.08:22:31.29#ibcon#cleared, iclass 6 cls_cnt 0 2006.217.08:22:31.29$vc4f8/vb=3,4 2006.217.08:22:31.29#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.217.08:22:31.29#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.217.08:22:31.29#ibcon#ireg 11 cls_cnt 2 2006.217.08:22:31.29#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.217.08:22:31.35#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.217.08:22:31.35#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.217.08:22:31.35#ibcon#enter wrdev, iclass 10, count 2 2006.217.08:22:31.35#ibcon#first serial, iclass 10, count 2 2006.217.08:22:31.35#ibcon#enter sib2, iclass 10, count 2 2006.217.08:22:31.35#ibcon#flushed, iclass 10, count 2 2006.217.08:22:31.35#ibcon#about to write, iclass 10, count 2 2006.217.08:22:31.35#ibcon#wrote, iclass 10, count 2 2006.217.08:22:31.35#ibcon#about to read 3, iclass 10, count 2 2006.217.08:22:31.38#ibcon#read 3, iclass 10, count 2 2006.217.08:22:31.38#ibcon#about to read 4, iclass 10, count 2 2006.217.08:22:31.38#ibcon#read 4, iclass 10, count 2 2006.217.08:22:31.38#ibcon#about to read 5, iclass 10, count 2 2006.217.08:22:31.38#ibcon#read 5, iclass 10, count 2 2006.217.08:22:31.38#ibcon#about to read 6, iclass 10, count 2 2006.217.08:22:31.38#ibcon#read 6, iclass 10, count 2 2006.217.08:22:31.38#ibcon#end of sib2, iclass 10, count 2 2006.217.08:22:31.38#ibcon#*mode == 0, iclass 10, count 2 2006.217.08:22:31.38#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.217.08:22:31.38#ibcon#[27=AT03-04\r\n] 2006.217.08:22:31.38#ibcon#*before write, iclass 10, count 2 2006.217.08:22:31.38#ibcon#enter sib2, iclass 10, count 2 2006.217.08:22:31.38#ibcon#flushed, iclass 10, count 2 2006.217.08:22:31.38#ibcon#about to write, iclass 10, count 2 2006.217.08:22:31.38#ibcon#wrote, iclass 10, count 2 2006.217.08:22:31.38#ibcon#about to read 3, iclass 10, count 2 2006.217.08:22:31.41#ibcon#read 3, iclass 10, count 2 2006.217.08:22:31.41#ibcon#about to read 4, iclass 10, count 2 2006.217.08:22:31.41#ibcon#read 4, iclass 10, count 2 2006.217.08:22:31.41#ibcon#about to read 5, iclass 10, count 2 2006.217.08:22:31.41#ibcon#read 5, iclass 10, count 2 2006.217.08:22:31.41#ibcon#about to read 6, iclass 10, count 2 2006.217.08:22:31.41#ibcon#read 6, iclass 10, count 2 2006.217.08:22:31.41#ibcon#end of sib2, iclass 10, count 2 2006.217.08:22:31.41#ibcon#*after write, iclass 10, count 2 2006.217.08:22:31.41#ibcon#*before return 0, iclass 10, count 2 2006.217.08:22:31.41#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.217.08:22:31.41#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.217.08:22:31.41#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.217.08:22:31.41#ibcon#ireg 7 cls_cnt 0 2006.217.08:22:31.41#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.217.08:22:31.53#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.217.08:22:31.53#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.217.08:22:31.53#ibcon#enter wrdev, iclass 10, count 0 2006.217.08:22:31.53#ibcon#first serial, iclass 10, count 0 2006.217.08:22:31.53#ibcon#enter sib2, iclass 10, count 0 2006.217.08:22:31.53#ibcon#flushed, iclass 10, count 0 2006.217.08:22:31.53#ibcon#about to write, iclass 10, count 0 2006.217.08:22:31.53#ibcon#wrote, iclass 10, count 0 2006.217.08:22:31.53#ibcon#about to read 3, iclass 10, count 0 2006.217.08:22:31.55#ibcon#read 3, iclass 10, count 0 2006.217.08:22:31.55#ibcon#about to read 4, iclass 10, count 0 2006.217.08:22:31.55#ibcon#read 4, iclass 10, count 0 2006.217.08:22:31.55#ibcon#about to read 5, iclass 10, count 0 2006.217.08:22:31.55#ibcon#read 5, iclass 10, count 0 2006.217.08:22:31.55#ibcon#about to read 6, iclass 10, count 0 2006.217.08:22:31.55#ibcon#read 6, iclass 10, count 0 2006.217.08:22:31.55#ibcon#end of sib2, iclass 10, count 0 2006.217.08:22:31.55#ibcon#*mode == 0, iclass 10, count 0 2006.217.08:22:31.55#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.217.08:22:31.55#ibcon#[27=USB\r\n] 2006.217.08:22:31.55#ibcon#*before write, iclass 10, count 0 2006.217.08:22:31.55#ibcon#enter sib2, iclass 10, count 0 2006.217.08:22:31.55#ibcon#flushed, iclass 10, count 0 2006.217.08:22:31.55#ibcon#about to write, iclass 10, count 0 2006.217.08:22:31.55#ibcon#wrote, iclass 10, count 0 2006.217.08:22:31.55#ibcon#about to read 3, iclass 10, count 0 2006.217.08:22:31.58#ibcon#read 3, iclass 10, count 0 2006.217.08:22:31.58#ibcon#about to read 4, iclass 10, count 0 2006.217.08:22:31.58#ibcon#read 4, iclass 10, count 0 2006.217.08:22:31.58#ibcon#about to read 5, iclass 10, count 0 2006.217.08:22:31.58#ibcon#read 5, iclass 10, count 0 2006.217.08:22:31.58#ibcon#about to read 6, iclass 10, count 0 2006.217.08:22:31.58#ibcon#read 6, iclass 10, count 0 2006.217.08:22:31.58#ibcon#end of sib2, iclass 10, count 0 2006.217.08:22:31.58#ibcon#*after write, iclass 10, count 0 2006.217.08:22:31.58#ibcon#*before return 0, iclass 10, count 0 2006.217.08:22:31.58#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.217.08:22:31.58#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.217.08:22:31.58#ibcon#about to clear, iclass 10 cls_cnt 0 2006.217.08:22:31.58#ibcon#cleared, iclass 10 cls_cnt 0 2006.217.08:22:31.58$vc4f8/vblo=4,712.99 2006.217.08:22:31.58#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.217.08:22:31.58#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.217.08:22:31.58#ibcon#ireg 17 cls_cnt 0 2006.217.08:22:31.58#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.217.08:22:31.58#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.217.08:22:31.58#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.217.08:22:31.58#ibcon#enter wrdev, iclass 12, count 0 2006.217.08:22:31.58#ibcon#first serial, iclass 12, count 0 2006.217.08:22:31.58#ibcon#enter sib2, iclass 12, count 0 2006.217.08:22:31.58#ibcon#flushed, iclass 12, count 0 2006.217.08:22:31.58#ibcon#about to write, iclass 12, count 0 2006.217.08:22:31.58#ibcon#wrote, iclass 12, count 0 2006.217.08:22:31.58#ibcon#about to read 3, iclass 12, count 0 2006.217.08:22:31.60#ibcon#read 3, iclass 12, count 0 2006.217.08:22:31.60#ibcon#about to read 4, iclass 12, count 0 2006.217.08:22:31.60#ibcon#read 4, iclass 12, count 0 2006.217.08:22:31.60#ibcon#about to read 5, iclass 12, count 0 2006.217.08:22:31.60#ibcon#read 5, iclass 12, count 0 2006.217.08:22:31.60#ibcon#about to read 6, iclass 12, count 0 2006.217.08:22:31.60#ibcon#read 6, iclass 12, count 0 2006.217.08:22:31.60#ibcon#end of sib2, iclass 12, count 0 2006.217.08:22:31.60#ibcon#*mode == 0, iclass 12, count 0 2006.217.08:22:31.60#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.217.08:22:31.60#ibcon#[28=FRQ=04,712.99\r\n] 2006.217.08:22:31.60#ibcon#*before write, iclass 12, count 0 2006.217.08:22:31.60#ibcon#enter sib2, iclass 12, count 0 2006.217.08:22:31.60#ibcon#flushed, iclass 12, count 0 2006.217.08:22:31.60#ibcon#about to write, iclass 12, count 0 2006.217.08:22:31.60#ibcon#wrote, iclass 12, count 0 2006.217.08:22:31.60#ibcon#about to read 3, iclass 12, count 0 2006.217.08:22:31.64#ibcon#read 3, iclass 12, count 0 2006.217.08:22:31.64#ibcon#about to read 4, iclass 12, count 0 2006.217.08:22:31.64#ibcon#read 4, iclass 12, count 0 2006.217.08:22:31.64#ibcon#about to read 5, iclass 12, count 0 2006.217.08:22:31.64#ibcon#read 5, iclass 12, count 0 2006.217.08:22:31.64#ibcon#about to read 6, iclass 12, count 0 2006.217.08:22:31.64#ibcon#read 6, iclass 12, count 0 2006.217.08:22:31.64#ibcon#end of sib2, iclass 12, count 0 2006.217.08:22:31.64#ibcon#*after write, iclass 12, count 0 2006.217.08:22:31.64#ibcon#*before return 0, iclass 12, count 0 2006.217.08:22:31.64#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.217.08:22:31.64#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.217.08:22:31.64#ibcon#about to clear, iclass 12 cls_cnt 0 2006.217.08:22:31.64#ibcon#cleared, iclass 12 cls_cnt 0 2006.217.08:22:31.64$vc4f8/vb=4,4 2006.217.08:22:31.64#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.217.08:22:31.64#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.217.08:22:31.64#ibcon#ireg 11 cls_cnt 2 2006.217.08:22:31.64#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.217.08:22:31.70#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.217.08:22:31.70#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.217.08:22:31.70#ibcon#enter wrdev, iclass 14, count 2 2006.217.08:22:31.70#ibcon#first serial, iclass 14, count 2 2006.217.08:22:31.70#ibcon#enter sib2, iclass 14, count 2 2006.217.08:22:31.70#ibcon#flushed, iclass 14, count 2 2006.217.08:22:31.70#ibcon#about to write, iclass 14, count 2 2006.217.08:22:31.70#ibcon#wrote, iclass 14, count 2 2006.217.08:22:31.70#ibcon#about to read 3, iclass 14, count 2 2006.217.08:22:31.72#ibcon#read 3, iclass 14, count 2 2006.217.08:22:31.72#ibcon#about to read 4, iclass 14, count 2 2006.217.08:22:31.72#ibcon#read 4, iclass 14, count 2 2006.217.08:22:31.72#ibcon#about to read 5, iclass 14, count 2 2006.217.08:22:31.72#ibcon#read 5, iclass 14, count 2 2006.217.08:22:31.72#ibcon#about to read 6, iclass 14, count 2 2006.217.08:22:31.72#ibcon#read 6, iclass 14, count 2 2006.217.08:22:31.72#ibcon#end of sib2, iclass 14, count 2 2006.217.08:22:31.72#ibcon#*mode == 0, iclass 14, count 2 2006.217.08:22:31.72#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.217.08:22:31.72#ibcon#[27=AT04-04\r\n] 2006.217.08:22:31.72#ibcon#*before write, iclass 14, count 2 2006.217.08:22:31.72#ibcon#enter sib2, iclass 14, count 2 2006.217.08:22:31.72#ibcon#flushed, iclass 14, count 2 2006.217.08:22:31.72#ibcon#about to write, iclass 14, count 2 2006.217.08:22:31.72#ibcon#wrote, iclass 14, count 2 2006.217.08:22:31.72#ibcon#about to read 3, iclass 14, count 2 2006.217.08:22:31.75#ibcon#read 3, iclass 14, count 2 2006.217.08:22:31.75#ibcon#about to read 4, iclass 14, count 2 2006.217.08:22:31.75#ibcon#read 4, iclass 14, count 2 2006.217.08:22:31.75#ibcon#about to read 5, iclass 14, count 2 2006.217.08:22:31.75#ibcon#read 5, iclass 14, count 2 2006.217.08:22:31.75#ibcon#about to read 6, iclass 14, count 2 2006.217.08:22:31.75#ibcon#read 6, iclass 14, count 2 2006.217.08:22:31.75#ibcon#end of sib2, iclass 14, count 2 2006.217.08:22:31.75#ibcon#*after write, iclass 14, count 2 2006.217.08:22:31.75#ibcon#*before return 0, iclass 14, count 2 2006.217.08:22:31.75#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.217.08:22:31.75#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.217.08:22:31.75#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.217.08:22:31.75#ibcon#ireg 7 cls_cnt 0 2006.217.08:22:31.75#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.217.08:22:31.87#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.217.08:22:31.87#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.217.08:22:31.87#ibcon#enter wrdev, iclass 14, count 0 2006.217.08:22:31.87#ibcon#first serial, iclass 14, count 0 2006.217.08:22:31.87#ibcon#enter sib2, iclass 14, count 0 2006.217.08:22:31.87#ibcon#flushed, iclass 14, count 0 2006.217.08:22:31.87#ibcon#about to write, iclass 14, count 0 2006.217.08:22:31.87#ibcon#wrote, iclass 14, count 0 2006.217.08:22:31.87#ibcon#about to read 3, iclass 14, count 0 2006.217.08:22:31.89#ibcon#read 3, iclass 14, count 0 2006.217.08:22:31.89#ibcon#about to read 4, iclass 14, count 0 2006.217.08:22:31.89#ibcon#read 4, iclass 14, count 0 2006.217.08:22:31.89#ibcon#about to read 5, iclass 14, count 0 2006.217.08:22:31.89#ibcon#read 5, iclass 14, count 0 2006.217.08:22:31.89#ibcon#about to read 6, iclass 14, count 0 2006.217.08:22:31.89#ibcon#read 6, iclass 14, count 0 2006.217.08:22:31.89#ibcon#end of sib2, iclass 14, count 0 2006.217.08:22:31.89#ibcon#*mode == 0, iclass 14, count 0 2006.217.08:22:31.89#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.217.08:22:31.89#ibcon#[27=USB\r\n] 2006.217.08:22:31.89#ibcon#*before write, iclass 14, count 0 2006.217.08:22:31.89#ibcon#enter sib2, iclass 14, count 0 2006.217.08:22:31.89#ibcon#flushed, iclass 14, count 0 2006.217.08:22:31.89#ibcon#about to write, iclass 14, count 0 2006.217.08:22:31.89#ibcon#wrote, iclass 14, count 0 2006.217.08:22:31.89#ibcon#about to read 3, iclass 14, count 0 2006.217.08:22:31.92#ibcon#read 3, iclass 14, count 0 2006.217.08:22:31.92#ibcon#about to read 4, iclass 14, count 0 2006.217.08:22:31.92#ibcon#read 4, iclass 14, count 0 2006.217.08:22:31.92#ibcon#about to read 5, iclass 14, count 0 2006.217.08:22:31.92#ibcon#read 5, iclass 14, count 0 2006.217.08:22:31.92#ibcon#about to read 6, iclass 14, count 0 2006.217.08:22:31.92#ibcon#read 6, iclass 14, count 0 2006.217.08:22:31.92#ibcon#end of sib2, iclass 14, count 0 2006.217.08:22:31.92#ibcon#*after write, iclass 14, count 0 2006.217.08:22:31.92#ibcon#*before return 0, iclass 14, count 0 2006.217.08:22:31.92#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.217.08:22:31.92#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.217.08:22:31.92#ibcon#about to clear, iclass 14 cls_cnt 0 2006.217.08:22:31.92#ibcon#cleared, iclass 14 cls_cnt 0 2006.217.08:22:31.92$vc4f8/vblo=5,744.99 2006.217.08:22:31.92#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.217.08:22:31.92#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.217.08:22:31.92#ibcon#ireg 17 cls_cnt 0 2006.217.08:22:31.92#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.217.08:22:31.92#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.217.08:22:31.92#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.217.08:22:31.92#ibcon#enter wrdev, iclass 16, count 0 2006.217.08:22:31.92#ibcon#first serial, iclass 16, count 0 2006.217.08:22:31.92#ibcon#enter sib2, iclass 16, count 0 2006.217.08:22:31.92#ibcon#flushed, iclass 16, count 0 2006.217.08:22:31.92#ibcon#about to write, iclass 16, count 0 2006.217.08:22:31.92#ibcon#wrote, iclass 16, count 0 2006.217.08:22:31.92#ibcon#about to read 3, iclass 16, count 0 2006.217.08:22:31.94#ibcon#read 3, iclass 16, count 0 2006.217.08:22:31.94#ibcon#about to read 4, iclass 16, count 0 2006.217.08:22:31.94#ibcon#read 4, iclass 16, count 0 2006.217.08:22:31.94#ibcon#about to read 5, iclass 16, count 0 2006.217.08:22:31.94#ibcon#read 5, iclass 16, count 0 2006.217.08:22:31.94#ibcon#about to read 6, iclass 16, count 0 2006.217.08:22:31.94#ibcon#read 6, iclass 16, count 0 2006.217.08:22:31.94#ibcon#end of sib2, iclass 16, count 0 2006.217.08:22:31.94#ibcon#*mode == 0, iclass 16, count 0 2006.217.08:22:31.94#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.217.08:22:31.94#ibcon#[28=FRQ=05,744.99\r\n] 2006.217.08:22:31.94#ibcon#*before write, iclass 16, count 0 2006.217.08:22:31.94#ibcon#enter sib2, iclass 16, count 0 2006.217.08:22:31.94#ibcon#flushed, iclass 16, count 0 2006.217.08:22:31.94#ibcon#about to write, iclass 16, count 0 2006.217.08:22:31.94#ibcon#wrote, iclass 16, count 0 2006.217.08:22:31.94#ibcon#about to read 3, iclass 16, count 0 2006.217.08:22:31.98#ibcon#read 3, iclass 16, count 0 2006.217.08:22:31.98#ibcon#about to read 4, iclass 16, count 0 2006.217.08:22:31.98#ibcon#read 4, iclass 16, count 0 2006.217.08:22:31.98#ibcon#about to read 5, iclass 16, count 0 2006.217.08:22:31.98#ibcon#read 5, iclass 16, count 0 2006.217.08:22:31.98#ibcon#about to read 6, iclass 16, count 0 2006.217.08:22:31.98#ibcon#read 6, iclass 16, count 0 2006.217.08:22:31.98#ibcon#end of sib2, iclass 16, count 0 2006.217.08:22:31.98#ibcon#*after write, iclass 16, count 0 2006.217.08:22:31.98#ibcon#*before return 0, iclass 16, count 0 2006.217.08:22:31.98#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.217.08:22:31.98#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.217.08:22:31.98#ibcon#about to clear, iclass 16 cls_cnt 0 2006.217.08:22:31.98#ibcon#cleared, iclass 16 cls_cnt 0 2006.217.08:22:31.98$vc4f8/vb=5,4 2006.217.08:22:31.98#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.217.08:22:31.98#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.217.08:22:31.98#ibcon#ireg 11 cls_cnt 2 2006.217.08:22:31.98#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.217.08:22:32.04#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.217.08:22:32.04#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.217.08:22:32.04#ibcon#enter wrdev, iclass 18, count 2 2006.217.08:22:32.04#ibcon#first serial, iclass 18, count 2 2006.217.08:22:32.04#ibcon#enter sib2, iclass 18, count 2 2006.217.08:22:32.04#ibcon#flushed, iclass 18, count 2 2006.217.08:22:32.04#ibcon#about to write, iclass 18, count 2 2006.217.08:22:32.04#ibcon#wrote, iclass 18, count 2 2006.217.08:22:32.04#ibcon#about to read 3, iclass 18, count 2 2006.217.08:22:32.06#ibcon#read 3, iclass 18, count 2 2006.217.08:22:32.06#ibcon#about to read 4, iclass 18, count 2 2006.217.08:22:32.06#ibcon#read 4, iclass 18, count 2 2006.217.08:22:32.06#ibcon#about to read 5, iclass 18, count 2 2006.217.08:22:32.06#ibcon#read 5, iclass 18, count 2 2006.217.08:22:32.06#ibcon#about to read 6, iclass 18, count 2 2006.217.08:22:32.06#ibcon#read 6, iclass 18, count 2 2006.217.08:22:32.06#ibcon#end of sib2, iclass 18, count 2 2006.217.08:22:32.06#ibcon#*mode == 0, iclass 18, count 2 2006.217.08:22:32.06#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.217.08:22:32.06#ibcon#[27=AT05-04\r\n] 2006.217.08:22:32.06#ibcon#*before write, iclass 18, count 2 2006.217.08:22:32.06#ibcon#enter sib2, iclass 18, count 2 2006.217.08:22:32.06#ibcon#flushed, iclass 18, count 2 2006.217.08:22:32.06#ibcon#about to write, iclass 18, count 2 2006.217.08:22:32.06#ibcon#wrote, iclass 18, count 2 2006.217.08:22:32.06#ibcon#about to read 3, iclass 18, count 2 2006.217.08:22:32.09#ibcon#read 3, iclass 18, count 2 2006.217.08:22:32.09#ibcon#about to read 4, iclass 18, count 2 2006.217.08:22:32.09#ibcon#read 4, iclass 18, count 2 2006.217.08:22:32.09#ibcon#about to read 5, iclass 18, count 2 2006.217.08:22:32.09#ibcon#read 5, iclass 18, count 2 2006.217.08:22:32.09#ibcon#about to read 6, iclass 18, count 2 2006.217.08:22:32.09#ibcon#read 6, iclass 18, count 2 2006.217.08:22:32.09#ibcon#end of sib2, iclass 18, count 2 2006.217.08:22:32.09#ibcon#*after write, iclass 18, count 2 2006.217.08:22:32.09#ibcon#*before return 0, iclass 18, count 2 2006.217.08:22:32.09#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.217.08:22:32.09#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.217.08:22:32.09#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.217.08:22:32.09#ibcon#ireg 7 cls_cnt 0 2006.217.08:22:32.09#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.217.08:22:32.21#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.217.08:22:32.21#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.217.08:22:32.21#ibcon#enter wrdev, iclass 18, count 0 2006.217.08:22:32.21#ibcon#first serial, iclass 18, count 0 2006.217.08:22:32.21#ibcon#enter sib2, iclass 18, count 0 2006.217.08:22:32.21#ibcon#flushed, iclass 18, count 0 2006.217.08:22:32.21#ibcon#about to write, iclass 18, count 0 2006.217.08:22:32.21#ibcon#wrote, iclass 18, count 0 2006.217.08:22:32.21#ibcon#about to read 3, iclass 18, count 0 2006.217.08:22:32.23#ibcon#read 3, iclass 18, count 0 2006.217.08:22:32.23#ibcon#about to read 4, iclass 18, count 0 2006.217.08:22:32.23#ibcon#read 4, iclass 18, count 0 2006.217.08:22:32.23#ibcon#about to read 5, iclass 18, count 0 2006.217.08:22:32.23#ibcon#read 5, iclass 18, count 0 2006.217.08:22:32.23#ibcon#about to read 6, iclass 18, count 0 2006.217.08:22:32.23#ibcon#read 6, iclass 18, count 0 2006.217.08:22:32.23#ibcon#end of sib2, iclass 18, count 0 2006.217.08:22:32.23#ibcon#*mode == 0, iclass 18, count 0 2006.217.08:22:32.23#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.217.08:22:32.23#ibcon#[27=USB\r\n] 2006.217.08:22:32.23#ibcon#*before write, iclass 18, count 0 2006.217.08:22:32.23#ibcon#enter sib2, iclass 18, count 0 2006.217.08:22:32.23#ibcon#flushed, iclass 18, count 0 2006.217.08:22:32.23#ibcon#about to write, iclass 18, count 0 2006.217.08:22:32.23#ibcon#wrote, iclass 18, count 0 2006.217.08:22:32.23#ibcon#about to read 3, iclass 18, count 0 2006.217.08:22:32.26#ibcon#read 3, iclass 18, count 0 2006.217.08:22:32.26#ibcon#about to read 4, iclass 18, count 0 2006.217.08:22:32.26#ibcon#read 4, iclass 18, count 0 2006.217.08:22:32.26#ibcon#about to read 5, iclass 18, count 0 2006.217.08:22:32.26#ibcon#read 5, iclass 18, count 0 2006.217.08:22:32.26#ibcon#about to read 6, iclass 18, count 0 2006.217.08:22:32.26#ibcon#read 6, iclass 18, count 0 2006.217.08:22:32.26#ibcon#end of sib2, iclass 18, count 0 2006.217.08:22:32.26#ibcon#*after write, iclass 18, count 0 2006.217.08:22:32.26#ibcon#*before return 0, iclass 18, count 0 2006.217.08:22:32.26#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.217.08:22:32.26#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.217.08:22:32.26#ibcon#about to clear, iclass 18 cls_cnt 0 2006.217.08:22:32.26#ibcon#cleared, iclass 18 cls_cnt 0 2006.217.08:22:32.26$vc4f8/vblo=6,752.99 2006.217.08:22:32.26#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.217.08:22:32.26#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.217.08:22:32.26#ibcon#ireg 17 cls_cnt 0 2006.217.08:22:32.26#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.217.08:22:32.26#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.217.08:22:32.26#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.217.08:22:32.26#ibcon#enter wrdev, iclass 20, count 0 2006.217.08:22:32.26#ibcon#first serial, iclass 20, count 0 2006.217.08:22:32.26#ibcon#enter sib2, iclass 20, count 0 2006.217.08:22:32.26#ibcon#flushed, iclass 20, count 0 2006.217.08:22:32.26#ibcon#about to write, iclass 20, count 0 2006.217.08:22:32.26#ibcon#wrote, iclass 20, count 0 2006.217.08:22:32.26#ibcon#about to read 3, iclass 20, count 0 2006.217.08:22:32.28#ibcon#read 3, iclass 20, count 0 2006.217.08:22:32.28#ibcon#about to read 4, iclass 20, count 0 2006.217.08:22:32.28#ibcon#read 4, iclass 20, count 0 2006.217.08:22:32.28#ibcon#about to read 5, iclass 20, count 0 2006.217.08:22:32.28#ibcon#read 5, iclass 20, count 0 2006.217.08:22:32.28#ibcon#about to read 6, iclass 20, count 0 2006.217.08:22:32.28#ibcon#read 6, iclass 20, count 0 2006.217.08:22:32.28#ibcon#end of sib2, iclass 20, count 0 2006.217.08:22:32.28#ibcon#*mode == 0, iclass 20, count 0 2006.217.08:22:32.28#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.217.08:22:32.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.217.08:22:32.28#ibcon#*before write, iclass 20, count 0 2006.217.08:22:32.28#ibcon#enter sib2, iclass 20, count 0 2006.217.08:22:32.28#ibcon#flushed, iclass 20, count 0 2006.217.08:22:32.28#ibcon#about to write, iclass 20, count 0 2006.217.08:22:32.28#ibcon#wrote, iclass 20, count 0 2006.217.08:22:32.28#ibcon#about to read 3, iclass 20, count 0 2006.217.08:22:32.32#ibcon#read 3, iclass 20, count 0 2006.217.08:22:32.32#ibcon#about to read 4, iclass 20, count 0 2006.217.08:22:32.32#ibcon#read 4, iclass 20, count 0 2006.217.08:22:32.32#ibcon#about to read 5, iclass 20, count 0 2006.217.08:22:32.32#ibcon#read 5, iclass 20, count 0 2006.217.08:22:32.32#ibcon#about to read 6, iclass 20, count 0 2006.217.08:22:32.32#ibcon#read 6, iclass 20, count 0 2006.217.08:22:32.32#ibcon#end of sib2, iclass 20, count 0 2006.217.08:22:32.32#ibcon#*after write, iclass 20, count 0 2006.217.08:22:32.32#ibcon#*before return 0, iclass 20, count 0 2006.217.08:22:32.32#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.217.08:22:32.32#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.217.08:22:32.32#ibcon#about to clear, iclass 20 cls_cnt 0 2006.217.08:22:32.32#ibcon#cleared, iclass 20 cls_cnt 0 2006.217.08:22:32.32$vc4f8/vb=6,4 2006.217.08:22:32.32#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.217.08:22:32.32#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.217.08:22:32.32#ibcon#ireg 11 cls_cnt 2 2006.217.08:22:32.32#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.217.08:22:32.38#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.217.08:22:32.38#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.217.08:22:32.38#ibcon#enter wrdev, iclass 22, count 2 2006.217.08:22:32.38#ibcon#first serial, iclass 22, count 2 2006.217.08:22:32.38#ibcon#enter sib2, iclass 22, count 2 2006.217.08:22:32.38#ibcon#flushed, iclass 22, count 2 2006.217.08:22:32.38#ibcon#about to write, iclass 22, count 2 2006.217.08:22:32.38#ibcon#wrote, iclass 22, count 2 2006.217.08:22:32.38#ibcon#about to read 3, iclass 22, count 2 2006.217.08:22:32.40#ibcon#read 3, iclass 22, count 2 2006.217.08:22:32.40#ibcon#about to read 4, iclass 22, count 2 2006.217.08:22:32.40#ibcon#read 4, iclass 22, count 2 2006.217.08:22:32.40#ibcon#about to read 5, iclass 22, count 2 2006.217.08:22:32.40#ibcon#read 5, iclass 22, count 2 2006.217.08:22:32.40#ibcon#about to read 6, iclass 22, count 2 2006.217.08:22:32.40#ibcon#read 6, iclass 22, count 2 2006.217.08:22:32.40#ibcon#end of sib2, iclass 22, count 2 2006.217.08:22:32.40#ibcon#*mode == 0, iclass 22, count 2 2006.217.08:22:32.40#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.217.08:22:32.40#ibcon#[27=AT06-04\r\n] 2006.217.08:22:32.40#ibcon#*before write, iclass 22, count 2 2006.217.08:22:32.40#ibcon#enter sib2, iclass 22, count 2 2006.217.08:22:32.40#ibcon#flushed, iclass 22, count 2 2006.217.08:22:32.40#ibcon#about to write, iclass 22, count 2 2006.217.08:22:32.40#ibcon#wrote, iclass 22, count 2 2006.217.08:22:32.40#ibcon#about to read 3, iclass 22, count 2 2006.217.08:22:32.43#ibcon#read 3, iclass 22, count 2 2006.217.08:22:32.43#ibcon#about to read 4, iclass 22, count 2 2006.217.08:22:32.43#ibcon#read 4, iclass 22, count 2 2006.217.08:22:32.43#ibcon#about to read 5, iclass 22, count 2 2006.217.08:22:32.43#ibcon#read 5, iclass 22, count 2 2006.217.08:22:32.43#ibcon#about to read 6, iclass 22, count 2 2006.217.08:22:32.43#ibcon#read 6, iclass 22, count 2 2006.217.08:22:32.43#ibcon#end of sib2, iclass 22, count 2 2006.217.08:22:32.43#ibcon#*after write, iclass 22, count 2 2006.217.08:22:32.43#ibcon#*before return 0, iclass 22, count 2 2006.217.08:22:32.43#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.217.08:22:32.43#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.217.08:22:32.43#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.217.08:22:32.43#ibcon#ireg 7 cls_cnt 0 2006.217.08:22:32.43#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.217.08:22:32.55#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.217.08:22:32.55#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.217.08:22:32.55#ibcon#enter wrdev, iclass 22, count 0 2006.217.08:22:32.55#ibcon#first serial, iclass 22, count 0 2006.217.08:22:32.55#ibcon#enter sib2, iclass 22, count 0 2006.217.08:22:32.55#ibcon#flushed, iclass 22, count 0 2006.217.08:22:32.55#ibcon#about to write, iclass 22, count 0 2006.217.08:22:32.55#ibcon#wrote, iclass 22, count 0 2006.217.08:22:32.55#ibcon#about to read 3, iclass 22, count 0 2006.217.08:22:32.57#ibcon#read 3, iclass 22, count 0 2006.217.08:22:32.57#ibcon#about to read 4, iclass 22, count 0 2006.217.08:22:32.57#ibcon#read 4, iclass 22, count 0 2006.217.08:22:32.57#ibcon#about to read 5, iclass 22, count 0 2006.217.08:22:32.57#ibcon#read 5, iclass 22, count 0 2006.217.08:22:32.57#ibcon#about to read 6, iclass 22, count 0 2006.217.08:22:32.57#ibcon#read 6, iclass 22, count 0 2006.217.08:22:32.57#ibcon#end of sib2, iclass 22, count 0 2006.217.08:22:32.57#ibcon#*mode == 0, iclass 22, count 0 2006.217.08:22:32.57#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.217.08:22:32.57#ibcon#[27=USB\r\n] 2006.217.08:22:32.57#ibcon#*before write, iclass 22, count 0 2006.217.08:22:32.57#ibcon#enter sib2, iclass 22, count 0 2006.217.08:22:32.57#ibcon#flushed, iclass 22, count 0 2006.217.08:22:32.57#ibcon#about to write, iclass 22, count 0 2006.217.08:22:32.57#ibcon#wrote, iclass 22, count 0 2006.217.08:22:32.57#ibcon#about to read 3, iclass 22, count 0 2006.217.08:22:32.60#ibcon#read 3, iclass 22, count 0 2006.217.08:22:32.60#ibcon#about to read 4, iclass 22, count 0 2006.217.08:22:32.60#ibcon#read 4, iclass 22, count 0 2006.217.08:22:32.60#ibcon#about to read 5, iclass 22, count 0 2006.217.08:22:32.60#ibcon#read 5, iclass 22, count 0 2006.217.08:22:32.60#ibcon#about to read 6, iclass 22, count 0 2006.217.08:22:32.60#ibcon#read 6, iclass 22, count 0 2006.217.08:22:32.60#ibcon#end of sib2, iclass 22, count 0 2006.217.08:22:32.60#ibcon#*after write, iclass 22, count 0 2006.217.08:22:32.60#ibcon#*before return 0, iclass 22, count 0 2006.217.08:22:32.60#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.217.08:22:32.60#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.217.08:22:32.60#ibcon#about to clear, iclass 22 cls_cnt 0 2006.217.08:22:32.60#ibcon#cleared, iclass 22 cls_cnt 0 2006.217.08:22:32.60$vc4f8/vabw=wide 2006.217.08:22:32.60#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.217.08:22:32.60#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.217.08:22:32.60#ibcon#ireg 8 cls_cnt 0 2006.217.08:22:32.60#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.217.08:22:32.60#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.217.08:22:32.60#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.217.08:22:32.60#ibcon#enter wrdev, iclass 24, count 0 2006.217.08:22:32.60#ibcon#first serial, iclass 24, count 0 2006.217.08:22:32.60#ibcon#enter sib2, iclass 24, count 0 2006.217.08:22:32.60#ibcon#flushed, iclass 24, count 0 2006.217.08:22:32.60#ibcon#about to write, iclass 24, count 0 2006.217.08:22:32.60#ibcon#wrote, iclass 24, count 0 2006.217.08:22:32.60#ibcon#about to read 3, iclass 24, count 0 2006.217.08:22:32.62#ibcon#read 3, iclass 24, count 0 2006.217.08:22:32.62#ibcon#about to read 4, iclass 24, count 0 2006.217.08:22:32.62#ibcon#read 4, iclass 24, count 0 2006.217.08:22:32.62#ibcon#about to read 5, iclass 24, count 0 2006.217.08:22:32.62#ibcon#read 5, iclass 24, count 0 2006.217.08:22:32.62#ibcon#about to read 6, iclass 24, count 0 2006.217.08:22:32.62#ibcon#read 6, iclass 24, count 0 2006.217.08:22:32.62#ibcon#end of sib2, iclass 24, count 0 2006.217.08:22:32.62#ibcon#*mode == 0, iclass 24, count 0 2006.217.08:22:32.62#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.217.08:22:32.62#ibcon#[25=BW32\r\n] 2006.217.08:22:32.62#ibcon#*before write, iclass 24, count 0 2006.217.08:22:32.62#ibcon#enter sib2, iclass 24, count 0 2006.217.08:22:32.62#ibcon#flushed, iclass 24, count 0 2006.217.08:22:32.62#ibcon#about to write, iclass 24, count 0 2006.217.08:22:32.62#ibcon#wrote, iclass 24, count 0 2006.217.08:22:32.62#ibcon#about to read 3, iclass 24, count 0 2006.217.08:22:32.65#ibcon#read 3, iclass 24, count 0 2006.217.08:22:32.65#ibcon#about to read 4, iclass 24, count 0 2006.217.08:22:32.65#ibcon#read 4, iclass 24, count 0 2006.217.08:22:32.65#ibcon#about to read 5, iclass 24, count 0 2006.217.08:22:32.65#ibcon#read 5, iclass 24, count 0 2006.217.08:22:32.65#ibcon#about to read 6, iclass 24, count 0 2006.217.08:22:32.65#ibcon#read 6, iclass 24, count 0 2006.217.08:22:32.65#ibcon#end of sib2, iclass 24, count 0 2006.217.08:22:32.65#ibcon#*after write, iclass 24, count 0 2006.217.08:22:32.65#ibcon#*before return 0, iclass 24, count 0 2006.217.08:22:32.65#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.217.08:22:32.65#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.217.08:22:32.65#ibcon#about to clear, iclass 24 cls_cnt 0 2006.217.08:22:32.65#ibcon#cleared, iclass 24 cls_cnt 0 2006.217.08:22:32.65$vc4f8/vbbw=wide 2006.217.08:22:32.65#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.217.08:22:32.65#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.217.08:22:32.65#ibcon#ireg 8 cls_cnt 0 2006.217.08:22:32.65#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.217.08:22:32.72#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.217.08:22:32.72#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.217.08:22:32.72#ibcon#enter wrdev, iclass 26, count 0 2006.217.08:22:32.72#ibcon#first serial, iclass 26, count 0 2006.217.08:22:32.72#ibcon#enter sib2, iclass 26, count 0 2006.217.08:22:32.72#ibcon#flushed, iclass 26, count 0 2006.217.08:22:32.72#ibcon#about to write, iclass 26, count 0 2006.217.08:22:32.72#ibcon#wrote, iclass 26, count 0 2006.217.08:22:32.72#ibcon#about to read 3, iclass 26, count 0 2006.217.08:22:32.74#ibcon#read 3, iclass 26, count 0 2006.217.08:22:32.74#ibcon#about to read 4, iclass 26, count 0 2006.217.08:22:32.74#ibcon#read 4, iclass 26, count 0 2006.217.08:22:32.74#ibcon#about to read 5, iclass 26, count 0 2006.217.08:22:32.74#ibcon#read 5, iclass 26, count 0 2006.217.08:22:32.74#ibcon#about to read 6, iclass 26, count 0 2006.217.08:22:32.74#ibcon#read 6, iclass 26, count 0 2006.217.08:22:32.74#ibcon#end of sib2, iclass 26, count 0 2006.217.08:22:32.74#ibcon#*mode == 0, iclass 26, count 0 2006.217.08:22:32.74#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.217.08:22:32.74#ibcon#[27=BW32\r\n] 2006.217.08:22:32.74#ibcon#*before write, iclass 26, count 0 2006.217.08:22:32.74#ibcon#enter sib2, iclass 26, count 0 2006.217.08:22:32.74#ibcon#flushed, iclass 26, count 0 2006.217.08:22:32.74#ibcon#about to write, iclass 26, count 0 2006.217.08:22:32.74#ibcon#wrote, iclass 26, count 0 2006.217.08:22:32.74#ibcon#about to read 3, iclass 26, count 0 2006.217.08:22:32.77#ibcon#read 3, iclass 26, count 0 2006.217.08:22:32.77#ibcon#about to read 4, iclass 26, count 0 2006.217.08:22:32.77#ibcon#read 4, iclass 26, count 0 2006.217.08:22:32.77#ibcon#about to read 5, iclass 26, count 0 2006.217.08:22:32.77#ibcon#read 5, iclass 26, count 0 2006.217.08:22:32.77#ibcon#about to read 6, iclass 26, count 0 2006.217.08:22:32.77#ibcon#read 6, iclass 26, count 0 2006.217.08:22:32.77#ibcon#end of sib2, iclass 26, count 0 2006.217.08:22:32.77#ibcon#*after write, iclass 26, count 0 2006.217.08:22:32.77#ibcon#*before return 0, iclass 26, count 0 2006.217.08:22:32.77#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.217.08:22:32.77#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.217.08:22:32.77#ibcon#about to clear, iclass 26 cls_cnt 0 2006.217.08:22:32.77#ibcon#cleared, iclass 26 cls_cnt 0 2006.217.08:22:32.77$4f8m12a/ifd4f 2006.217.08:22:32.77$ifd4f/lo= 2006.217.08:22:32.77$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.217.08:22:32.77$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.217.08:22:32.77$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.217.08:22:32.77$ifd4f/patch= 2006.217.08:22:32.77$ifd4f/patch=lo1,a1,a2,a3,a4 2006.217.08:22:32.77$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.217.08:22:32.78$ifd4f/patch=lo3,a5,a6,a7,a8 2006.217.08:22:32.78$4f8m12a/"form=m,16.000,1:2 2006.217.08:22:32.78$4f8m12a/"tpicd 2006.217.08:22:32.78$4f8m12a/echo=off 2006.217.08:22:32.78$4f8m12a/xlog=off 2006.217.08:22:32.78:!2006.217.08:24:40 2006.217.08:23:02.13#trakl#Source acquired 2006.217.08:23:02.13#flagr#flagr/antenna,acquired 2006.217.08:24:40.01:preob 2006.217.08:24:41.13/onsource/TRACKING 2006.217.08:24:41.13:!2006.217.08:24:50 2006.217.08:24:50.00:data_valid=on 2006.217.08:24:50.00:midob 2006.217.08:24:50.14/onsource/TRACKING 2006.217.08:24:50.14/wx/30.42,1008.6,64 2006.217.08:24:50.27/cable/+6.3879E-03 2006.217.08:24:51.36/va/01,05,usb,yes,31,33 2006.217.08:24:51.36/va/02,04,usb,yes,29,30 2006.217.08:24:51.36/va/03,04,usb,yes,27,27 2006.217.08:24:51.36/va/04,04,usb,yes,30,33 2006.217.08:24:51.36/va/05,07,usb,yes,32,34 2006.217.08:24:51.36/va/06,06,usb,yes,32,31 2006.217.08:24:51.36/va/07,06,usb,yes,32,32 2006.217.08:24:51.36/va/08,07,usb,yes,30,30 2006.217.08:24:51.59/valo/01,532.99,yes,locked 2006.217.08:24:51.59/valo/02,572.99,yes,locked 2006.217.08:24:51.59/valo/03,672.99,yes,locked 2006.217.08:24:51.59/valo/04,832.99,yes,locked 2006.217.08:24:51.59/valo/05,652.99,yes,locked 2006.217.08:24:51.59/valo/06,772.99,yes,locked 2006.217.08:24:51.59/valo/07,832.99,yes,locked 2006.217.08:24:51.59/valo/08,852.99,yes,locked 2006.217.08:24:52.68/vb/01,04,usb,yes,30,29 2006.217.08:24:52.68/vb/02,04,usb,yes,32,33 2006.217.08:24:52.68/vb/03,04,usb,yes,28,32 2006.217.08:24:52.68/vb/04,04,usb,yes,29,29 2006.217.08:24:52.68/vb/05,04,usb,yes,27,31 2006.217.08:24:52.68/vb/06,04,usb,yes,28,31 2006.217.08:24:52.68/vb/07,04,usb,yes,31,30 2006.217.08:24:52.68/vb/08,04,usb,yes,28,31 2006.217.08:24:52.91/vblo/01,632.99,yes,locked 2006.217.08:24:52.91/vblo/02,640.99,yes,locked 2006.217.08:24:52.91/vblo/03,656.99,yes,locked 2006.217.08:24:52.91/vblo/04,712.99,yes,locked 2006.217.08:24:52.91/vblo/05,744.99,yes,locked 2006.217.08:24:52.91/vblo/06,752.99,yes,locked 2006.217.08:24:52.91/vblo/07,734.99,yes,locked 2006.217.08:24:52.91/vblo/08,744.99,yes,locked 2006.217.08:24:53.06/vabw/8 2006.217.08:24:53.21/vbbw/8 2006.217.08:24:53.30/xfe/off,on,15.0 2006.217.08:24:53.67/ifatt/23,28,28,28 2006.217.08:24:54.07/fmout-gps/S +4.44E-07 2006.217.08:24:54.15:!2006.217.08:25:50 2006.217.08:25:50.01:data_valid=off 2006.217.08:25:50.02:postob 2006.217.08:25:50.14/cable/+6.3885E-03 2006.217.08:25:50.15/wx/30.40,1008.6,65 2006.217.08:25:51.07/fmout-gps/S +4.42E-07 2006.217.08:25:51.08:scan_name=217-0826,k06217,60 2006.217.08:25:51.08:source=1044+719,104827.62,714335.9,2000.0,ccw 2006.217.08:25:52.14#flagr#flagr/antenna,new-source 2006.217.08:25:52.15:checkk5 2006.217.08:25:52.52/chk_autoobs//k5ts1/ autoobs is running! 2006.217.08:25:52.90/chk_autoobs//k5ts2/ autoobs is running! 2006.217.08:25:53.28/chk_autoobs//k5ts3/ autoobs is running! 2006.217.08:25:53.65/chk_autoobs//k5ts4/ autoobs is running! 2006.217.08:25:54.02/chk_obsdata//k5ts1/T2170824??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.217.08:25:54.39/chk_obsdata//k5ts2/T2170824??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.217.08:25:54.76/chk_obsdata//k5ts3/T2170824??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.217.08:25:55.13/chk_obsdata//k5ts4/T2170824??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.217.08:25:55.81/k5log//k5ts1_log_newline 2006.217.08:25:56.50/k5log//k5ts2_log_newline 2006.217.08:25:57.19/k5log//k5ts3_log_newline 2006.217.08:25:57.88/k5log//k5ts4_log_newline 2006.217.08:25:57.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.217.08:25:57.90:4f8m12a=3 2006.217.08:25:57.90$4f8m12a/echo=on 2006.217.08:25:57.90$4f8m12a/pcalon 2006.217.08:25:57.90$pcalon/"no phase cal control is implemented here 2006.217.08:25:57.90$4f8m12a/"tpicd=stop 2006.217.08:25:57.90$4f8m12a/vc4f8 2006.217.08:25:57.90$vc4f8/valo=1,532.99 2006.217.08:25:57.90#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.217.08:25:57.90#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.217.08:25:57.90#ibcon#ireg 17 cls_cnt 0 2006.217.08:25:57.90#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.217.08:25:57.90#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.217.08:25:57.91#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.217.08:25:57.91#ibcon#enter wrdev, iclass 37, count 0 2006.217.08:25:57.91#ibcon#first serial, iclass 37, count 0 2006.217.08:25:57.91#ibcon#enter sib2, iclass 37, count 0 2006.217.08:25:57.91#ibcon#flushed, iclass 37, count 0 2006.217.08:25:57.91#ibcon#about to write, iclass 37, count 0 2006.217.08:25:57.91#ibcon#wrote, iclass 37, count 0 2006.217.08:25:57.91#ibcon#about to read 3, iclass 37, count 0 2006.217.08:25:57.94#ibcon#read 3, iclass 37, count 0 2006.217.08:25:57.94#ibcon#about to read 4, iclass 37, count 0 2006.217.08:25:57.94#ibcon#read 4, iclass 37, count 0 2006.217.08:25:57.94#ibcon#about to read 5, iclass 37, count 0 2006.217.08:25:57.94#ibcon#read 5, iclass 37, count 0 2006.217.08:25:57.94#ibcon#about to read 6, iclass 37, count 0 2006.217.08:25:57.94#ibcon#read 6, iclass 37, count 0 2006.217.08:25:57.94#ibcon#end of sib2, iclass 37, count 0 2006.217.08:25:57.94#ibcon#*mode == 0, iclass 37, count 0 2006.217.08:25:57.94#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.217.08:25:57.94#ibcon#[26=FRQ=01,532.99\r\n] 2006.217.08:25:57.94#ibcon#*before write, iclass 37, count 0 2006.217.08:25:57.94#ibcon#enter sib2, iclass 37, count 0 2006.217.08:25:57.94#ibcon#flushed, iclass 37, count 0 2006.217.08:25:57.94#ibcon#about to write, iclass 37, count 0 2006.217.08:25:57.94#ibcon#wrote, iclass 37, count 0 2006.217.08:25:57.94#ibcon#about to read 3, iclass 37, count 0 2006.217.08:25:57.99#ibcon#read 3, iclass 37, count 0 2006.217.08:25:57.99#ibcon#about to read 4, iclass 37, count 0 2006.217.08:25:57.99#ibcon#read 4, iclass 37, count 0 2006.217.08:25:57.99#ibcon#about to read 5, iclass 37, count 0 2006.217.08:25:57.99#ibcon#read 5, iclass 37, count 0 2006.217.08:25:57.99#ibcon#about to read 6, iclass 37, count 0 2006.217.08:25:57.99#ibcon#read 6, iclass 37, count 0 2006.217.08:25:57.99#ibcon#end of sib2, iclass 37, count 0 2006.217.08:25:57.99#ibcon#*after write, iclass 37, count 0 2006.217.08:25:57.99#ibcon#*before return 0, iclass 37, count 0 2006.217.08:25:57.99#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.217.08:25:57.99#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.217.08:25:57.99#ibcon#about to clear, iclass 37 cls_cnt 0 2006.217.08:25:57.99#ibcon#cleared, iclass 37 cls_cnt 0 2006.217.08:25:57.99$vc4f8/va=1,5 2006.217.08:25:57.99#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.217.08:25:57.99#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.217.08:25:57.99#ibcon#ireg 11 cls_cnt 2 2006.217.08:25:57.99#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.217.08:25:57.99#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.217.08:25:57.99#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.217.08:25:57.99#ibcon#enter wrdev, iclass 39, count 2 2006.217.08:25:57.99#ibcon#first serial, iclass 39, count 2 2006.217.08:25:57.99#ibcon#enter sib2, iclass 39, count 2 2006.217.08:25:57.99#ibcon#flushed, iclass 39, count 2 2006.217.08:25:57.99#ibcon#about to write, iclass 39, count 2 2006.217.08:25:57.99#ibcon#wrote, iclass 39, count 2 2006.217.08:25:57.99#ibcon#about to read 3, iclass 39, count 2 2006.217.08:25:58.01#ibcon#read 3, iclass 39, count 2 2006.217.08:25:58.01#ibcon#about to read 4, iclass 39, count 2 2006.217.08:25:58.01#ibcon#read 4, iclass 39, count 2 2006.217.08:25:58.01#ibcon#about to read 5, iclass 39, count 2 2006.217.08:25:58.01#ibcon#read 5, iclass 39, count 2 2006.217.08:25:58.01#ibcon#about to read 6, iclass 39, count 2 2006.217.08:25:58.01#ibcon#read 6, iclass 39, count 2 2006.217.08:25:58.01#ibcon#end of sib2, iclass 39, count 2 2006.217.08:25:58.01#ibcon#*mode == 0, iclass 39, count 2 2006.217.08:25:58.01#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.217.08:25:58.01#ibcon#[25=AT01-05\r\n] 2006.217.08:25:58.01#ibcon#*before write, iclass 39, count 2 2006.217.08:25:58.01#ibcon#enter sib2, iclass 39, count 2 2006.217.08:25:58.01#ibcon#flushed, iclass 39, count 2 2006.217.08:25:58.01#ibcon#about to write, iclass 39, count 2 2006.217.08:25:58.01#ibcon#wrote, iclass 39, count 2 2006.217.08:25:58.01#ibcon#about to read 3, iclass 39, count 2 2006.217.08:25:58.04#ibcon#read 3, iclass 39, count 2 2006.217.08:25:58.04#ibcon#about to read 4, iclass 39, count 2 2006.217.08:25:58.04#ibcon#read 4, iclass 39, count 2 2006.217.08:25:58.04#ibcon#about to read 5, iclass 39, count 2 2006.217.08:25:58.04#ibcon#read 5, iclass 39, count 2 2006.217.08:25:58.04#ibcon#about to read 6, iclass 39, count 2 2006.217.08:25:58.04#ibcon#read 6, iclass 39, count 2 2006.217.08:25:58.04#ibcon#end of sib2, iclass 39, count 2 2006.217.08:25:58.04#ibcon#*after write, iclass 39, count 2 2006.217.08:25:58.04#ibcon#*before return 0, iclass 39, count 2 2006.217.08:25:58.04#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.217.08:25:58.04#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.217.08:25:58.04#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.217.08:25:58.04#ibcon#ireg 7 cls_cnt 0 2006.217.08:25:58.04#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.217.08:25:58.16#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.217.08:25:58.16#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.217.08:25:58.16#ibcon#enter wrdev, iclass 39, count 0 2006.217.08:25:58.16#ibcon#first serial, iclass 39, count 0 2006.217.08:25:58.16#ibcon#enter sib2, iclass 39, count 0 2006.217.08:25:58.16#ibcon#flushed, iclass 39, count 0 2006.217.08:25:58.16#ibcon#about to write, iclass 39, count 0 2006.217.08:25:58.16#ibcon#wrote, iclass 39, count 0 2006.217.08:25:58.16#ibcon#about to read 3, iclass 39, count 0 2006.217.08:25:58.18#ibcon#read 3, iclass 39, count 0 2006.217.08:25:58.18#ibcon#about to read 4, iclass 39, count 0 2006.217.08:25:58.18#ibcon#read 4, iclass 39, count 0 2006.217.08:25:58.18#ibcon#about to read 5, iclass 39, count 0 2006.217.08:25:58.18#ibcon#read 5, iclass 39, count 0 2006.217.08:25:58.18#ibcon#about to read 6, iclass 39, count 0 2006.217.08:25:58.18#ibcon#read 6, iclass 39, count 0 2006.217.08:25:58.18#ibcon#end of sib2, iclass 39, count 0 2006.217.08:25:58.18#ibcon#*mode == 0, iclass 39, count 0 2006.217.08:25:58.18#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.217.08:25:58.18#ibcon#[25=USB\r\n] 2006.217.08:25:58.18#ibcon#*before write, iclass 39, count 0 2006.217.08:25:58.18#ibcon#enter sib2, iclass 39, count 0 2006.217.08:25:58.18#ibcon#flushed, iclass 39, count 0 2006.217.08:25:58.18#ibcon#about to write, iclass 39, count 0 2006.217.08:25:58.18#ibcon#wrote, iclass 39, count 0 2006.217.08:25:58.18#ibcon#about to read 3, iclass 39, count 0 2006.217.08:25:58.21#ibcon#read 3, iclass 39, count 0 2006.217.08:25:58.21#ibcon#about to read 4, iclass 39, count 0 2006.217.08:25:58.21#ibcon#read 4, iclass 39, count 0 2006.217.08:25:58.21#ibcon#about to read 5, iclass 39, count 0 2006.217.08:25:58.21#ibcon#read 5, iclass 39, count 0 2006.217.08:25:58.21#ibcon#about to read 6, iclass 39, count 0 2006.217.08:25:58.21#ibcon#read 6, iclass 39, count 0 2006.217.08:25:58.21#ibcon#end of sib2, iclass 39, count 0 2006.217.08:25:58.21#ibcon#*after write, iclass 39, count 0 2006.217.08:25:58.21#ibcon#*before return 0, iclass 39, count 0 2006.217.08:25:58.21#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.217.08:25:58.21#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.217.08:25:58.21#ibcon#about to clear, iclass 39 cls_cnt 0 2006.217.08:25:58.21#ibcon#cleared, iclass 39 cls_cnt 0 2006.217.08:25:58.21$vc4f8/valo=2,572.99 2006.217.08:25:58.21#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.217.08:25:58.21#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.217.08:25:58.21#ibcon#ireg 17 cls_cnt 0 2006.217.08:25:58.21#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.217.08:25:58.21#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.217.08:25:58.21#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.217.08:25:58.21#ibcon#enter wrdev, iclass 3, count 0 2006.217.08:25:58.21#ibcon#first serial, iclass 3, count 0 2006.217.08:25:58.21#ibcon#enter sib2, iclass 3, count 0 2006.217.08:25:58.21#ibcon#flushed, iclass 3, count 0 2006.217.08:25:58.21#ibcon#about to write, iclass 3, count 0 2006.217.08:25:58.21#ibcon#wrote, iclass 3, count 0 2006.217.08:25:58.21#ibcon#about to read 3, iclass 3, count 0 2006.217.08:25:58.23#ibcon#read 3, iclass 3, count 0 2006.217.08:25:58.23#ibcon#about to read 4, iclass 3, count 0 2006.217.08:25:58.23#ibcon#read 4, iclass 3, count 0 2006.217.08:25:58.23#ibcon#about to read 5, iclass 3, count 0 2006.217.08:25:58.23#ibcon#read 5, iclass 3, count 0 2006.217.08:25:58.23#ibcon#about to read 6, iclass 3, count 0 2006.217.08:25:58.23#ibcon#read 6, iclass 3, count 0 2006.217.08:25:58.23#ibcon#end of sib2, iclass 3, count 0 2006.217.08:25:58.23#ibcon#*mode == 0, iclass 3, count 0 2006.217.08:25:58.23#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.217.08:25:58.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.217.08:25:58.23#ibcon#*before write, iclass 3, count 0 2006.217.08:25:58.23#ibcon#enter sib2, iclass 3, count 0 2006.217.08:25:58.23#ibcon#flushed, iclass 3, count 0 2006.217.08:25:58.23#ibcon#about to write, iclass 3, count 0 2006.217.08:25:58.23#ibcon#wrote, iclass 3, count 0 2006.217.08:25:58.23#ibcon#about to read 3, iclass 3, count 0 2006.217.08:25:58.27#ibcon#read 3, iclass 3, count 0 2006.217.08:25:58.27#ibcon#about to read 4, iclass 3, count 0 2006.217.08:25:58.27#ibcon#read 4, iclass 3, count 0 2006.217.08:25:58.27#ibcon#about to read 5, iclass 3, count 0 2006.217.08:25:58.27#ibcon#read 5, iclass 3, count 0 2006.217.08:25:58.27#ibcon#about to read 6, iclass 3, count 0 2006.217.08:25:58.27#ibcon#read 6, iclass 3, count 0 2006.217.08:25:58.27#ibcon#end of sib2, iclass 3, count 0 2006.217.08:25:58.27#ibcon#*after write, iclass 3, count 0 2006.217.08:25:58.27#ibcon#*before return 0, iclass 3, count 0 2006.217.08:25:58.27#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.217.08:25:58.27#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.217.08:25:58.27#ibcon#about to clear, iclass 3 cls_cnt 0 2006.217.08:25:58.27#ibcon#cleared, iclass 3 cls_cnt 0 2006.217.08:25:58.27$vc4f8/va=2,4 2006.217.08:25:58.27#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.217.08:25:58.27#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.217.08:25:58.27#ibcon#ireg 11 cls_cnt 2 2006.217.08:25:58.27#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.217.08:25:58.33#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.217.08:25:58.33#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.217.08:25:58.33#ibcon#enter wrdev, iclass 5, count 2 2006.217.08:25:58.33#ibcon#first serial, iclass 5, count 2 2006.217.08:25:58.33#ibcon#enter sib2, iclass 5, count 2 2006.217.08:25:58.33#ibcon#flushed, iclass 5, count 2 2006.217.08:25:58.33#ibcon#about to write, iclass 5, count 2 2006.217.08:25:58.33#ibcon#wrote, iclass 5, count 2 2006.217.08:25:58.33#ibcon#about to read 3, iclass 5, count 2 2006.217.08:25:58.35#ibcon#read 3, iclass 5, count 2 2006.217.08:25:58.35#ibcon#about to read 4, iclass 5, count 2 2006.217.08:25:58.35#ibcon#read 4, iclass 5, count 2 2006.217.08:25:58.35#ibcon#about to read 5, iclass 5, count 2 2006.217.08:25:58.35#ibcon#read 5, iclass 5, count 2 2006.217.08:25:58.35#ibcon#about to read 6, iclass 5, count 2 2006.217.08:25:58.35#ibcon#read 6, iclass 5, count 2 2006.217.08:25:58.35#ibcon#end of sib2, iclass 5, count 2 2006.217.08:25:58.35#ibcon#*mode == 0, iclass 5, count 2 2006.217.08:25:58.35#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.217.08:25:58.35#ibcon#[25=AT02-04\r\n] 2006.217.08:25:58.35#ibcon#*before write, iclass 5, count 2 2006.217.08:25:58.35#ibcon#enter sib2, iclass 5, count 2 2006.217.08:25:58.35#ibcon#flushed, iclass 5, count 2 2006.217.08:25:58.35#ibcon#about to write, iclass 5, count 2 2006.217.08:25:58.35#ibcon#wrote, iclass 5, count 2 2006.217.08:25:58.35#ibcon#about to read 3, iclass 5, count 2 2006.217.08:25:58.38#ibcon#read 3, iclass 5, count 2 2006.217.08:25:58.38#ibcon#about to read 4, iclass 5, count 2 2006.217.08:25:58.38#ibcon#read 4, iclass 5, count 2 2006.217.08:25:58.38#ibcon#about to read 5, iclass 5, count 2 2006.217.08:25:58.38#ibcon#read 5, iclass 5, count 2 2006.217.08:25:58.38#ibcon#about to read 6, iclass 5, count 2 2006.217.08:25:58.38#ibcon#read 6, iclass 5, count 2 2006.217.08:25:58.38#ibcon#end of sib2, iclass 5, count 2 2006.217.08:25:58.38#ibcon#*after write, iclass 5, count 2 2006.217.08:25:58.38#ibcon#*before return 0, iclass 5, count 2 2006.217.08:25:58.38#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.217.08:25:58.38#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.217.08:25:58.38#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.217.08:25:58.38#ibcon#ireg 7 cls_cnt 0 2006.217.08:25:58.38#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.217.08:25:58.51#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.217.08:25:58.51#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.217.08:25:58.51#ibcon#enter wrdev, iclass 5, count 0 2006.217.08:25:58.51#ibcon#first serial, iclass 5, count 0 2006.217.08:25:58.51#ibcon#enter sib2, iclass 5, count 0 2006.217.08:25:58.51#ibcon#flushed, iclass 5, count 0 2006.217.08:25:58.51#ibcon#about to write, iclass 5, count 0 2006.217.08:25:58.51#ibcon#wrote, iclass 5, count 0 2006.217.08:25:58.51#ibcon#about to read 3, iclass 5, count 0 2006.217.08:25:58.52#ibcon#read 3, iclass 5, count 0 2006.217.08:25:58.52#ibcon#about to read 4, iclass 5, count 0 2006.217.08:25:58.52#ibcon#read 4, iclass 5, count 0 2006.217.08:25:58.52#ibcon#about to read 5, iclass 5, count 0 2006.217.08:25:58.52#ibcon#read 5, iclass 5, count 0 2006.217.08:25:58.52#ibcon#about to read 6, iclass 5, count 0 2006.217.08:25:58.52#ibcon#read 6, iclass 5, count 0 2006.217.08:25:58.52#ibcon#end of sib2, iclass 5, count 0 2006.217.08:25:58.52#ibcon#*mode == 0, iclass 5, count 0 2006.217.08:25:58.52#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.217.08:25:58.52#ibcon#[25=USB\r\n] 2006.217.08:25:58.52#ibcon#*before write, iclass 5, count 0 2006.217.08:25:58.52#ibcon#enter sib2, iclass 5, count 0 2006.217.08:25:58.52#ibcon#flushed, iclass 5, count 0 2006.217.08:25:58.52#ibcon#about to write, iclass 5, count 0 2006.217.08:25:58.52#ibcon#wrote, iclass 5, count 0 2006.217.08:25:58.52#ibcon#about to read 3, iclass 5, count 0 2006.217.08:25:58.55#ibcon#read 3, iclass 5, count 0 2006.217.08:25:58.55#ibcon#about to read 4, iclass 5, count 0 2006.217.08:25:58.55#ibcon#read 4, iclass 5, count 0 2006.217.08:25:58.55#ibcon#about to read 5, iclass 5, count 0 2006.217.08:25:58.55#ibcon#read 5, iclass 5, count 0 2006.217.08:25:58.55#ibcon#about to read 6, iclass 5, count 0 2006.217.08:25:58.55#ibcon#read 6, iclass 5, count 0 2006.217.08:25:58.55#ibcon#end of sib2, iclass 5, count 0 2006.217.08:25:58.55#ibcon#*after write, iclass 5, count 0 2006.217.08:25:58.55#ibcon#*before return 0, iclass 5, count 0 2006.217.08:25:58.55#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.217.08:25:58.55#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.217.08:25:58.55#ibcon#about to clear, iclass 5 cls_cnt 0 2006.217.08:25:58.55#ibcon#cleared, iclass 5 cls_cnt 0 2006.217.08:25:58.55$vc4f8/valo=3,672.99 2006.217.08:25:58.55#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.217.08:25:58.55#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.217.08:25:58.55#ibcon#ireg 17 cls_cnt 0 2006.217.08:25:58.55#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.217.08:25:58.55#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.217.08:25:58.55#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.217.08:25:58.55#ibcon#enter wrdev, iclass 7, count 0 2006.217.08:25:58.55#ibcon#first serial, iclass 7, count 0 2006.217.08:25:58.55#ibcon#enter sib2, iclass 7, count 0 2006.217.08:25:58.55#ibcon#flushed, iclass 7, count 0 2006.217.08:25:58.55#ibcon#about to write, iclass 7, count 0 2006.217.08:25:58.55#ibcon#wrote, iclass 7, count 0 2006.217.08:25:58.55#ibcon#about to read 3, iclass 7, count 0 2006.217.08:25:58.58#ibcon#read 3, iclass 7, count 0 2006.217.08:25:58.58#ibcon#about to read 4, iclass 7, count 0 2006.217.08:25:58.58#ibcon#read 4, iclass 7, count 0 2006.217.08:25:58.58#ibcon#about to read 5, iclass 7, count 0 2006.217.08:25:58.58#ibcon#read 5, iclass 7, count 0 2006.217.08:25:58.58#ibcon#about to read 6, iclass 7, count 0 2006.217.08:25:58.58#ibcon#read 6, iclass 7, count 0 2006.217.08:25:58.58#ibcon#end of sib2, iclass 7, count 0 2006.217.08:25:58.58#ibcon#*mode == 0, iclass 7, count 0 2006.217.08:25:58.58#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.217.08:25:58.58#ibcon#[26=FRQ=03,672.99\r\n] 2006.217.08:25:58.58#ibcon#*before write, iclass 7, count 0 2006.217.08:25:58.58#ibcon#enter sib2, iclass 7, count 0 2006.217.08:25:58.58#ibcon#flushed, iclass 7, count 0 2006.217.08:25:58.58#ibcon#about to write, iclass 7, count 0 2006.217.08:25:58.58#ibcon#wrote, iclass 7, count 0 2006.217.08:25:58.58#ibcon#about to read 3, iclass 7, count 0 2006.217.08:25:58.62#ibcon#read 3, iclass 7, count 0 2006.217.08:25:58.62#ibcon#about to read 4, iclass 7, count 0 2006.217.08:25:58.62#ibcon#read 4, iclass 7, count 0 2006.217.08:25:58.62#ibcon#about to read 5, iclass 7, count 0 2006.217.08:25:58.62#ibcon#read 5, iclass 7, count 0 2006.217.08:25:58.62#ibcon#about to read 6, iclass 7, count 0 2006.217.08:25:58.62#ibcon#read 6, iclass 7, count 0 2006.217.08:25:58.62#ibcon#end of sib2, iclass 7, count 0 2006.217.08:25:58.62#ibcon#*after write, iclass 7, count 0 2006.217.08:25:58.62#ibcon#*before return 0, iclass 7, count 0 2006.217.08:25:58.62#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.217.08:25:58.62#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.217.08:25:58.62#ibcon#about to clear, iclass 7 cls_cnt 0 2006.217.08:25:58.62#ibcon#cleared, iclass 7 cls_cnt 0 2006.217.08:25:58.62$vc4f8/va=3,4 2006.217.08:25:58.62#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.217.08:25:58.62#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.217.08:25:58.62#ibcon#ireg 11 cls_cnt 2 2006.217.08:25:58.62#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.217.08:25:58.67#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.217.08:25:58.67#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.217.08:25:58.67#ibcon#enter wrdev, iclass 11, count 2 2006.217.08:25:58.67#ibcon#first serial, iclass 11, count 2 2006.217.08:25:58.67#ibcon#enter sib2, iclass 11, count 2 2006.217.08:25:58.67#ibcon#flushed, iclass 11, count 2 2006.217.08:25:58.67#ibcon#about to write, iclass 11, count 2 2006.217.08:25:58.67#ibcon#wrote, iclass 11, count 2 2006.217.08:25:58.67#ibcon#about to read 3, iclass 11, count 2 2006.217.08:25:58.69#ibcon#read 3, iclass 11, count 2 2006.217.08:25:58.69#ibcon#about to read 4, iclass 11, count 2 2006.217.08:25:58.69#ibcon#read 4, iclass 11, count 2 2006.217.08:25:58.69#ibcon#about to read 5, iclass 11, count 2 2006.217.08:25:58.69#ibcon#read 5, iclass 11, count 2 2006.217.08:25:58.69#ibcon#about to read 6, iclass 11, count 2 2006.217.08:25:58.69#ibcon#read 6, iclass 11, count 2 2006.217.08:25:58.69#ibcon#end of sib2, iclass 11, count 2 2006.217.08:25:58.69#ibcon#*mode == 0, iclass 11, count 2 2006.217.08:25:58.69#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.217.08:25:58.69#ibcon#[25=AT03-04\r\n] 2006.217.08:25:58.69#ibcon#*before write, iclass 11, count 2 2006.217.08:25:58.69#ibcon#enter sib2, iclass 11, count 2 2006.217.08:25:58.69#ibcon#flushed, iclass 11, count 2 2006.217.08:25:58.69#ibcon#about to write, iclass 11, count 2 2006.217.08:25:58.69#ibcon#wrote, iclass 11, count 2 2006.217.08:25:58.69#ibcon#about to read 3, iclass 11, count 2 2006.217.08:25:58.72#ibcon#read 3, iclass 11, count 2 2006.217.08:25:58.72#ibcon#about to read 4, iclass 11, count 2 2006.217.08:25:58.72#ibcon#read 4, iclass 11, count 2 2006.217.08:25:58.72#ibcon#about to read 5, iclass 11, count 2 2006.217.08:25:58.72#ibcon#read 5, iclass 11, count 2 2006.217.08:25:58.72#ibcon#about to read 6, iclass 11, count 2 2006.217.08:25:58.72#ibcon#read 6, iclass 11, count 2 2006.217.08:25:58.72#ibcon#end of sib2, iclass 11, count 2 2006.217.08:25:58.72#ibcon#*after write, iclass 11, count 2 2006.217.08:25:58.72#ibcon#*before return 0, iclass 11, count 2 2006.217.08:25:58.72#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.217.08:25:58.72#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.217.08:25:58.72#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.217.08:25:58.72#ibcon#ireg 7 cls_cnt 0 2006.217.08:25:58.72#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.217.08:25:58.84#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.217.08:25:58.84#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.217.08:25:58.84#ibcon#enter wrdev, iclass 11, count 0 2006.217.08:25:58.84#ibcon#first serial, iclass 11, count 0 2006.217.08:25:58.84#ibcon#enter sib2, iclass 11, count 0 2006.217.08:25:58.84#ibcon#flushed, iclass 11, count 0 2006.217.08:25:58.84#ibcon#about to write, iclass 11, count 0 2006.217.08:25:58.84#ibcon#wrote, iclass 11, count 0 2006.217.08:25:58.84#ibcon#about to read 3, iclass 11, count 0 2006.217.08:25:58.86#ibcon#read 3, iclass 11, count 0 2006.217.08:25:58.86#ibcon#about to read 4, iclass 11, count 0 2006.217.08:25:58.86#ibcon#read 4, iclass 11, count 0 2006.217.08:25:58.86#ibcon#about to read 5, iclass 11, count 0 2006.217.08:25:58.86#ibcon#read 5, iclass 11, count 0 2006.217.08:25:58.86#ibcon#about to read 6, iclass 11, count 0 2006.217.08:25:58.86#ibcon#read 6, iclass 11, count 0 2006.217.08:25:58.86#ibcon#end of sib2, iclass 11, count 0 2006.217.08:25:58.86#ibcon#*mode == 0, iclass 11, count 0 2006.217.08:25:58.86#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.217.08:25:58.86#ibcon#[25=USB\r\n] 2006.217.08:25:58.86#ibcon#*before write, iclass 11, count 0 2006.217.08:25:58.86#ibcon#enter sib2, iclass 11, count 0 2006.217.08:25:58.86#ibcon#flushed, iclass 11, count 0 2006.217.08:25:58.86#ibcon#about to write, iclass 11, count 0 2006.217.08:25:58.86#ibcon#wrote, iclass 11, count 0 2006.217.08:25:58.86#ibcon#about to read 3, iclass 11, count 0 2006.217.08:25:58.89#ibcon#read 3, iclass 11, count 0 2006.217.08:25:58.89#ibcon#about to read 4, iclass 11, count 0 2006.217.08:25:58.89#ibcon#read 4, iclass 11, count 0 2006.217.08:25:58.89#ibcon#about to read 5, iclass 11, count 0 2006.217.08:25:58.89#ibcon#read 5, iclass 11, count 0 2006.217.08:25:58.89#ibcon#about to read 6, iclass 11, count 0 2006.217.08:25:58.89#ibcon#read 6, iclass 11, count 0 2006.217.08:25:58.89#ibcon#end of sib2, iclass 11, count 0 2006.217.08:25:58.89#ibcon#*after write, iclass 11, count 0 2006.217.08:25:58.89#ibcon#*before return 0, iclass 11, count 0 2006.217.08:25:58.89#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.217.08:25:58.89#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.217.08:25:58.89#ibcon#about to clear, iclass 11 cls_cnt 0 2006.217.08:25:58.89#ibcon#cleared, iclass 11 cls_cnt 0 2006.217.08:25:58.89$vc4f8/valo=4,832.99 2006.217.08:25:58.89#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.217.08:25:58.89#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.217.08:25:58.89#ibcon#ireg 17 cls_cnt 0 2006.217.08:25:58.89#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.217.08:25:58.89#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.217.08:25:58.89#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.217.08:25:58.89#ibcon#enter wrdev, iclass 13, count 0 2006.217.08:25:58.89#ibcon#first serial, iclass 13, count 0 2006.217.08:25:58.89#ibcon#enter sib2, iclass 13, count 0 2006.217.08:25:58.89#ibcon#flushed, iclass 13, count 0 2006.217.08:25:58.89#ibcon#about to write, iclass 13, count 0 2006.217.08:25:58.89#ibcon#wrote, iclass 13, count 0 2006.217.08:25:58.89#ibcon#about to read 3, iclass 13, count 0 2006.217.08:25:58.91#ibcon#read 3, iclass 13, count 0 2006.217.08:25:58.91#ibcon#about to read 4, iclass 13, count 0 2006.217.08:25:58.91#ibcon#read 4, iclass 13, count 0 2006.217.08:25:58.91#ibcon#about to read 5, iclass 13, count 0 2006.217.08:25:58.91#ibcon#read 5, iclass 13, count 0 2006.217.08:25:58.91#ibcon#about to read 6, iclass 13, count 0 2006.217.08:25:58.91#ibcon#read 6, iclass 13, count 0 2006.217.08:25:58.91#ibcon#end of sib2, iclass 13, count 0 2006.217.08:25:58.91#ibcon#*mode == 0, iclass 13, count 0 2006.217.08:25:58.91#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.217.08:25:58.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.217.08:25:58.91#ibcon#*before write, iclass 13, count 0 2006.217.08:25:58.91#ibcon#enter sib2, iclass 13, count 0 2006.217.08:25:58.91#ibcon#flushed, iclass 13, count 0 2006.217.08:25:58.91#ibcon#about to write, iclass 13, count 0 2006.217.08:25:58.91#ibcon#wrote, iclass 13, count 0 2006.217.08:25:58.91#ibcon#about to read 3, iclass 13, count 0 2006.217.08:25:58.95#ibcon#read 3, iclass 13, count 0 2006.217.08:25:58.95#ibcon#about to read 4, iclass 13, count 0 2006.217.08:25:58.95#ibcon#read 4, iclass 13, count 0 2006.217.08:25:58.95#ibcon#about to read 5, iclass 13, count 0 2006.217.08:25:58.95#ibcon#read 5, iclass 13, count 0 2006.217.08:25:58.95#ibcon#about to read 6, iclass 13, count 0 2006.217.08:25:58.95#ibcon#read 6, iclass 13, count 0 2006.217.08:25:58.95#ibcon#end of sib2, iclass 13, count 0 2006.217.08:25:58.95#ibcon#*after write, iclass 13, count 0 2006.217.08:25:58.95#ibcon#*before return 0, iclass 13, count 0 2006.217.08:25:58.95#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.217.08:25:58.95#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.217.08:25:58.95#ibcon#about to clear, iclass 13 cls_cnt 0 2006.217.08:25:58.95#ibcon#cleared, iclass 13 cls_cnt 0 2006.217.08:25:58.95$vc4f8/va=4,4 2006.217.08:25:58.95#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.217.08:25:58.95#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.217.08:25:58.95#ibcon#ireg 11 cls_cnt 2 2006.217.08:25:58.95#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.217.08:25:59.01#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.217.08:25:59.01#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.217.08:25:59.01#ibcon#enter wrdev, iclass 15, count 2 2006.217.08:25:59.01#ibcon#first serial, iclass 15, count 2 2006.217.08:25:59.01#ibcon#enter sib2, iclass 15, count 2 2006.217.08:25:59.01#ibcon#flushed, iclass 15, count 2 2006.217.08:25:59.01#ibcon#about to write, iclass 15, count 2 2006.217.08:25:59.01#ibcon#wrote, iclass 15, count 2 2006.217.08:25:59.01#ibcon#about to read 3, iclass 15, count 2 2006.217.08:25:59.03#ibcon#read 3, iclass 15, count 2 2006.217.08:25:59.03#ibcon#about to read 4, iclass 15, count 2 2006.217.08:25:59.03#ibcon#read 4, iclass 15, count 2 2006.217.08:25:59.03#ibcon#about to read 5, iclass 15, count 2 2006.217.08:25:59.03#ibcon#read 5, iclass 15, count 2 2006.217.08:25:59.03#ibcon#about to read 6, iclass 15, count 2 2006.217.08:25:59.03#ibcon#read 6, iclass 15, count 2 2006.217.08:25:59.03#ibcon#end of sib2, iclass 15, count 2 2006.217.08:25:59.03#ibcon#*mode == 0, iclass 15, count 2 2006.217.08:25:59.03#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.217.08:25:59.03#ibcon#[25=AT04-04\r\n] 2006.217.08:25:59.03#ibcon#*before write, iclass 15, count 2 2006.217.08:25:59.03#ibcon#enter sib2, iclass 15, count 2 2006.217.08:25:59.03#ibcon#flushed, iclass 15, count 2 2006.217.08:25:59.03#ibcon#about to write, iclass 15, count 2 2006.217.08:25:59.03#ibcon#wrote, iclass 15, count 2 2006.217.08:25:59.03#ibcon#about to read 3, iclass 15, count 2 2006.217.08:25:59.06#ibcon#read 3, iclass 15, count 2 2006.217.08:25:59.06#ibcon#about to read 4, iclass 15, count 2 2006.217.08:25:59.06#ibcon#read 4, iclass 15, count 2 2006.217.08:25:59.06#ibcon#about to read 5, iclass 15, count 2 2006.217.08:25:59.06#ibcon#read 5, iclass 15, count 2 2006.217.08:25:59.06#ibcon#about to read 6, iclass 15, count 2 2006.217.08:25:59.06#ibcon#read 6, iclass 15, count 2 2006.217.08:25:59.06#ibcon#end of sib2, iclass 15, count 2 2006.217.08:25:59.06#ibcon#*after write, iclass 15, count 2 2006.217.08:25:59.06#ibcon#*before return 0, iclass 15, count 2 2006.217.08:25:59.06#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.217.08:25:59.06#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.217.08:25:59.06#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.217.08:25:59.06#ibcon#ireg 7 cls_cnt 0 2006.217.08:25:59.06#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.217.08:25:59.18#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.217.08:25:59.18#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.217.08:25:59.18#ibcon#enter wrdev, iclass 15, count 0 2006.217.08:25:59.18#ibcon#first serial, iclass 15, count 0 2006.217.08:25:59.18#ibcon#enter sib2, iclass 15, count 0 2006.217.08:25:59.18#ibcon#flushed, iclass 15, count 0 2006.217.08:25:59.18#ibcon#about to write, iclass 15, count 0 2006.217.08:25:59.18#ibcon#wrote, iclass 15, count 0 2006.217.08:25:59.18#ibcon#about to read 3, iclass 15, count 0 2006.217.08:25:59.20#ibcon#read 3, iclass 15, count 0 2006.217.08:25:59.20#ibcon#about to read 4, iclass 15, count 0 2006.217.08:25:59.20#ibcon#read 4, iclass 15, count 0 2006.217.08:25:59.20#ibcon#about to read 5, iclass 15, count 0 2006.217.08:25:59.20#ibcon#read 5, iclass 15, count 0 2006.217.08:25:59.20#ibcon#about to read 6, iclass 15, count 0 2006.217.08:25:59.20#ibcon#read 6, iclass 15, count 0 2006.217.08:25:59.20#ibcon#end of sib2, iclass 15, count 0 2006.217.08:25:59.20#ibcon#*mode == 0, iclass 15, count 0 2006.217.08:25:59.20#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.217.08:25:59.20#ibcon#[25=USB\r\n] 2006.217.08:25:59.20#ibcon#*before write, iclass 15, count 0 2006.217.08:25:59.20#ibcon#enter sib2, iclass 15, count 0 2006.217.08:25:59.20#ibcon#flushed, iclass 15, count 0 2006.217.08:25:59.20#ibcon#about to write, iclass 15, count 0 2006.217.08:25:59.20#ibcon#wrote, iclass 15, count 0 2006.217.08:25:59.20#ibcon#about to read 3, iclass 15, count 0 2006.217.08:25:59.23#ibcon#read 3, iclass 15, count 0 2006.217.08:25:59.23#ibcon#about to read 4, iclass 15, count 0 2006.217.08:25:59.23#ibcon#read 4, iclass 15, count 0 2006.217.08:25:59.23#ibcon#about to read 5, iclass 15, count 0 2006.217.08:25:59.23#ibcon#read 5, iclass 15, count 0 2006.217.08:25:59.23#ibcon#about to read 6, iclass 15, count 0 2006.217.08:25:59.23#ibcon#read 6, iclass 15, count 0 2006.217.08:25:59.23#ibcon#end of sib2, iclass 15, count 0 2006.217.08:25:59.23#ibcon#*after write, iclass 15, count 0 2006.217.08:25:59.23#ibcon#*before return 0, iclass 15, count 0 2006.217.08:25:59.23#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.217.08:25:59.23#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.217.08:25:59.23#ibcon#about to clear, iclass 15 cls_cnt 0 2006.217.08:25:59.23#ibcon#cleared, iclass 15 cls_cnt 0 2006.217.08:25:59.23$vc4f8/valo=5,652.99 2006.217.08:25:59.23#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.217.08:25:59.23#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.217.08:25:59.23#ibcon#ireg 17 cls_cnt 0 2006.217.08:25:59.23#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.217.08:25:59.23#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.217.08:25:59.23#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.217.08:25:59.23#ibcon#enter wrdev, iclass 17, count 0 2006.217.08:25:59.23#ibcon#first serial, iclass 17, count 0 2006.217.08:25:59.23#ibcon#enter sib2, iclass 17, count 0 2006.217.08:25:59.23#ibcon#flushed, iclass 17, count 0 2006.217.08:25:59.23#ibcon#about to write, iclass 17, count 0 2006.217.08:25:59.23#ibcon#wrote, iclass 17, count 0 2006.217.08:25:59.23#ibcon#about to read 3, iclass 17, count 0 2006.217.08:25:59.25#ibcon#read 3, iclass 17, count 0 2006.217.08:25:59.25#ibcon#about to read 4, iclass 17, count 0 2006.217.08:25:59.25#ibcon#read 4, iclass 17, count 0 2006.217.08:25:59.25#ibcon#about to read 5, iclass 17, count 0 2006.217.08:25:59.25#ibcon#read 5, iclass 17, count 0 2006.217.08:25:59.25#ibcon#about to read 6, iclass 17, count 0 2006.217.08:25:59.25#ibcon#read 6, iclass 17, count 0 2006.217.08:25:59.25#ibcon#end of sib2, iclass 17, count 0 2006.217.08:25:59.25#ibcon#*mode == 0, iclass 17, count 0 2006.217.08:25:59.25#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.217.08:25:59.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.217.08:25:59.25#ibcon#*before write, iclass 17, count 0 2006.217.08:25:59.25#ibcon#enter sib2, iclass 17, count 0 2006.217.08:25:59.25#ibcon#flushed, iclass 17, count 0 2006.217.08:25:59.25#ibcon#about to write, iclass 17, count 0 2006.217.08:25:59.25#ibcon#wrote, iclass 17, count 0 2006.217.08:25:59.25#ibcon#about to read 3, iclass 17, count 0 2006.217.08:25:59.29#ibcon#read 3, iclass 17, count 0 2006.217.08:25:59.29#ibcon#about to read 4, iclass 17, count 0 2006.217.08:25:59.29#ibcon#read 4, iclass 17, count 0 2006.217.08:25:59.29#ibcon#about to read 5, iclass 17, count 0 2006.217.08:25:59.29#ibcon#read 5, iclass 17, count 0 2006.217.08:25:59.29#ibcon#about to read 6, iclass 17, count 0 2006.217.08:25:59.29#ibcon#read 6, iclass 17, count 0 2006.217.08:25:59.29#ibcon#end of sib2, iclass 17, count 0 2006.217.08:25:59.29#ibcon#*after write, iclass 17, count 0 2006.217.08:25:59.29#ibcon#*before return 0, iclass 17, count 0 2006.217.08:25:59.29#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.217.08:25:59.29#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.217.08:25:59.29#ibcon#about to clear, iclass 17 cls_cnt 0 2006.217.08:25:59.29#ibcon#cleared, iclass 17 cls_cnt 0 2006.217.08:25:59.29$vc4f8/va=5,7 2006.217.08:25:59.29#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.217.08:25:59.29#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.217.08:25:59.29#ibcon#ireg 11 cls_cnt 2 2006.217.08:25:59.29#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.217.08:25:59.35#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.217.08:25:59.35#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.217.08:25:59.35#ibcon#enter wrdev, iclass 19, count 2 2006.217.08:25:59.35#ibcon#first serial, iclass 19, count 2 2006.217.08:25:59.35#ibcon#enter sib2, iclass 19, count 2 2006.217.08:25:59.35#ibcon#flushed, iclass 19, count 2 2006.217.08:25:59.35#ibcon#about to write, iclass 19, count 2 2006.217.08:25:59.35#ibcon#wrote, iclass 19, count 2 2006.217.08:25:59.35#ibcon#about to read 3, iclass 19, count 2 2006.217.08:25:59.37#ibcon#read 3, iclass 19, count 2 2006.217.08:25:59.37#ibcon#about to read 4, iclass 19, count 2 2006.217.08:25:59.37#ibcon#read 4, iclass 19, count 2 2006.217.08:25:59.37#ibcon#about to read 5, iclass 19, count 2 2006.217.08:25:59.37#ibcon#read 5, iclass 19, count 2 2006.217.08:25:59.37#ibcon#about to read 6, iclass 19, count 2 2006.217.08:25:59.37#ibcon#read 6, iclass 19, count 2 2006.217.08:25:59.37#ibcon#end of sib2, iclass 19, count 2 2006.217.08:25:59.37#ibcon#*mode == 0, iclass 19, count 2 2006.217.08:25:59.37#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.217.08:25:59.37#ibcon#[25=AT05-07\r\n] 2006.217.08:25:59.37#ibcon#*before write, iclass 19, count 2 2006.217.08:25:59.37#ibcon#enter sib2, iclass 19, count 2 2006.217.08:25:59.37#ibcon#flushed, iclass 19, count 2 2006.217.08:25:59.37#ibcon#about to write, iclass 19, count 2 2006.217.08:25:59.37#ibcon#wrote, iclass 19, count 2 2006.217.08:25:59.37#ibcon#about to read 3, iclass 19, count 2 2006.217.08:25:59.40#ibcon#read 3, iclass 19, count 2 2006.217.08:25:59.40#ibcon#about to read 4, iclass 19, count 2 2006.217.08:25:59.40#ibcon#read 4, iclass 19, count 2 2006.217.08:25:59.40#ibcon#about to read 5, iclass 19, count 2 2006.217.08:25:59.40#ibcon#read 5, iclass 19, count 2 2006.217.08:25:59.40#ibcon#about to read 6, iclass 19, count 2 2006.217.08:25:59.40#ibcon#read 6, iclass 19, count 2 2006.217.08:25:59.40#ibcon#end of sib2, iclass 19, count 2 2006.217.08:25:59.40#ibcon#*after write, iclass 19, count 2 2006.217.08:25:59.40#ibcon#*before return 0, iclass 19, count 2 2006.217.08:25:59.40#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.217.08:25:59.40#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.217.08:25:59.40#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.217.08:25:59.40#ibcon#ireg 7 cls_cnt 0 2006.217.08:25:59.40#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.217.08:25:59.52#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.217.08:25:59.52#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.217.08:25:59.52#ibcon#enter wrdev, iclass 19, count 0 2006.217.08:25:59.52#ibcon#first serial, iclass 19, count 0 2006.217.08:25:59.52#ibcon#enter sib2, iclass 19, count 0 2006.217.08:25:59.52#ibcon#flushed, iclass 19, count 0 2006.217.08:25:59.52#ibcon#about to write, iclass 19, count 0 2006.217.08:25:59.52#ibcon#wrote, iclass 19, count 0 2006.217.08:25:59.52#ibcon#about to read 3, iclass 19, count 0 2006.217.08:25:59.54#ibcon#read 3, iclass 19, count 0 2006.217.08:25:59.54#ibcon#about to read 4, iclass 19, count 0 2006.217.08:25:59.54#ibcon#read 4, iclass 19, count 0 2006.217.08:25:59.54#ibcon#about to read 5, iclass 19, count 0 2006.217.08:25:59.54#ibcon#read 5, iclass 19, count 0 2006.217.08:25:59.54#ibcon#about to read 6, iclass 19, count 0 2006.217.08:25:59.54#ibcon#read 6, iclass 19, count 0 2006.217.08:25:59.54#ibcon#end of sib2, iclass 19, count 0 2006.217.08:25:59.54#ibcon#*mode == 0, iclass 19, count 0 2006.217.08:25:59.54#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.217.08:25:59.54#ibcon#[25=USB\r\n] 2006.217.08:25:59.54#ibcon#*before write, iclass 19, count 0 2006.217.08:25:59.54#ibcon#enter sib2, iclass 19, count 0 2006.217.08:25:59.54#ibcon#flushed, iclass 19, count 0 2006.217.08:25:59.54#ibcon#about to write, iclass 19, count 0 2006.217.08:25:59.54#ibcon#wrote, iclass 19, count 0 2006.217.08:25:59.54#ibcon#about to read 3, iclass 19, count 0 2006.217.08:25:59.57#ibcon#read 3, iclass 19, count 0 2006.217.08:25:59.57#ibcon#about to read 4, iclass 19, count 0 2006.217.08:25:59.57#ibcon#read 4, iclass 19, count 0 2006.217.08:25:59.57#ibcon#about to read 5, iclass 19, count 0 2006.217.08:25:59.57#ibcon#read 5, iclass 19, count 0 2006.217.08:25:59.57#ibcon#about to read 6, iclass 19, count 0 2006.217.08:25:59.57#ibcon#read 6, iclass 19, count 0 2006.217.08:25:59.57#ibcon#end of sib2, iclass 19, count 0 2006.217.08:25:59.57#ibcon#*after write, iclass 19, count 0 2006.217.08:25:59.57#ibcon#*before return 0, iclass 19, count 0 2006.217.08:25:59.57#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.217.08:25:59.57#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.217.08:25:59.57#ibcon#about to clear, iclass 19 cls_cnt 0 2006.217.08:25:59.57#ibcon#cleared, iclass 19 cls_cnt 0 2006.217.08:25:59.57$vc4f8/valo=6,772.99 2006.217.08:25:59.57#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.217.08:25:59.57#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.217.08:25:59.57#ibcon#ireg 17 cls_cnt 0 2006.217.08:25:59.57#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.217.08:25:59.57#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.217.08:25:59.57#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.217.08:25:59.57#ibcon#enter wrdev, iclass 21, count 0 2006.217.08:25:59.57#ibcon#first serial, iclass 21, count 0 2006.217.08:25:59.57#ibcon#enter sib2, iclass 21, count 0 2006.217.08:25:59.57#ibcon#flushed, iclass 21, count 0 2006.217.08:25:59.57#ibcon#about to write, iclass 21, count 0 2006.217.08:25:59.57#ibcon#wrote, iclass 21, count 0 2006.217.08:25:59.57#ibcon#about to read 3, iclass 21, count 0 2006.217.08:25:59.59#ibcon#read 3, iclass 21, count 0 2006.217.08:25:59.59#ibcon#about to read 4, iclass 21, count 0 2006.217.08:25:59.59#ibcon#read 4, iclass 21, count 0 2006.217.08:25:59.59#ibcon#about to read 5, iclass 21, count 0 2006.217.08:25:59.59#ibcon#read 5, iclass 21, count 0 2006.217.08:25:59.59#ibcon#about to read 6, iclass 21, count 0 2006.217.08:25:59.59#ibcon#read 6, iclass 21, count 0 2006.217.08:25:59.59#ibcon#end of sib2, iclass 21, count 0 2006.217.08:25:59.59#ibcon#*mode == 0, iclass 21, count 0 2006.217.08:25:59.59#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.217.08:25:59.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.217.08:25:59.59#ibcon#*before write, iclass 21, count 0 2006.217.08:25:59.59#ibcon#enter sib2, iclass 21, count 0 2006.217.08:25:59.59#ibcon#flushed, iclass 21, count 0 2006.217.08:25:59.59#ibcon#about to write, iclass 21, count 0 2006.217.08:25:59.59#ibcon#wrote, iclass 21, count 0 2006.217.08:25:59.59#ibcon#about to read 3, iclass 21, count 0 2006.217.08:25:59.63#ibcon#read 3, iclass 21, count 0 2006.217.08:25:59.63#ibcon#about to read 4, iclass 21, count 0 2006.217.08:25:59.63#ibcon#read 4, iclass 21, count 0 2006.217.08:25:59.63#ibcon#about to read 5, iclass 21, count 0 2006.217.08:25:59.63#ibcon#read 5, iclass 21, count 0 2006.217.08:25:59.63#ibcon#about to read 6, iclass 21, count 0 2006.217.08:25:59.63#ibcon#read 6, iclass 21, count 0 2006.217.08:25:59.63#ibcon#end of sib2, iclass 21, count 0 2006.217.08:25:59.63#ibcon#*after write, iclass 21, count 0 2006.217.08:25:59.63#ibcon#*before return 0, iclass 21, count 0 2006.217.08:25:59.63#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.217.08:25:59.63#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.217.08:25:59.63#ibcon#about to clear, iclass 21 cls_cnt 0 2006.217.08:25:59.63#ibcon#cleared, iclass 21 cls_cnt 0 2006.217.08:25:59.63$vc4f8/va=6,6 2006.217.08:25:59.63#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.217.08:25:59.63#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.217.08:25:59.63#ibcon#ireg 11 cls_cnt 2 2006.217.08:25:59.63#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.217.08:25:59.69#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.217.08:25:59.69#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.217.08:25:59.69#ibcon#enter wrdev, iclass 23, count 2 2006.217.08:25:59.69#ibcon#first serial, iclass 23, count 2 2006.217.08:25:59.69#ibcon#enter sib2, iclass 23, count 2 2006.217.08:25:59.69#ibcon#flushed, iclass 23, count 2 2006.217.08:25:59.69#ibcon#about to write, iclass 23, count 2 2006.217.08:25:59.69#ibcon#wrote, iclass 23, count 2 2006.217.08:25:59.69#ibcon#about to read 3, iclass 23, count 2 2006.217.08:25:59.71#ibcon#read 3, iclass 23, count 2 2006.217.08:25:59.71#ibcon#about to read 4, iclass 23, count 2 2006.217.08:25:59.71#ibcon#read 4, iclass 23, count 2 2006.217.08:25:59.71#ibcon#about to read 5, iclass 23, count 2 2006.217.08:25:59.71#ibcon#read 5, iclass 23, count 2 2006.217.08:25:59.71#ibcon#about to read 6, iclass 23, count 2 2006.217.08:25:59.71#ibcon#read 6, iclass 23, count 2 2006.217.08:25:59.71#ibcon#end of sib2, iclass 23, count 2 2006.217.08:25:59.71#ibcon#*mode == 0, iclass 23, count 2 2006.217.08:25:59.71#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.217.08:25:59.71#ibcon#[25=AT06-06\r\n] 2006.217.08:25:59.71#ibcon#*before write, iclass 23, count 2 2006.217.08:25:59.71#ibcon#enter sib2, iclass 23, count 2 2006.217.08:25:59.71#ibcon#flushed, iclass 23, count 2 2006.217.08:25:59.71#ibcon#about to write, iclass 23, count 2 2006.217.08:25:59.71#ibcon#wrote, iclass 23, count 2 2006.217.08:25:59.71#ibcon#about to read 3, iclass 23, count 2 2006.217.08:25:59.74#ibcon#read 3, iclass 23, count 2 2006.217.08:25:59.74#ibcon#about to read 4, iclass 23, count 2 2006.217.08:25:59.74#ibcon#read 4, iclass 23, count 2 2006.217.08:25:59.74#ibcon#about to read 5, iclass 23, count 2 2006.217.08:25:59.74#ibcon#read 5, iclass 23, count 2 2006.217.08:25:59.74#ibcon#about to read 6, iclass 23, count 2 2006.217.08:25:59.74#ibcon#read 6, iclass 23, count 2 2006.217.08:25:59.74#ibcon#end of sib2, iclass 23, count 2 2006.217.08:25:59.74#ibcon#*after write, iclass 23, count 2 2006.217.08:25:59.74#ibcon#*before return 0, iclass 23, count 2 2006.217.08:25:59.74#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.217.08:25:59.74#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.217.08:25:59.74#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.217.08:25:59.74#ibcon#ireg 7 cls_cnt 0 2006.217.08:25:59.74#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.217.08:25:59.86#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.217.08:25:59.86#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.217.08:25:59.86#ibcon#enter wrdev, iclass 23, count 0 2006.217.08:25:59.86#ibcon#first serial, iclass 23, count 0 2006.217.08:25:59.86#ibcon#enter sib2, iclass 23, count 0 2006.217.08:25:59.86#ibcon#flushed, iclass 23, count 0 2006.217.08:25:59.86#ibcon#about to write, iclass 23, count 0 2006.217.08:25:59.86#ibcon#wrote, iclass 23, count 0 2006.217.08:25:59.86#ibcon#about to read 3, iclass 23, count 0 2006.217.08:25:59.88#ibcon#read 3, iclass 23, count 0 2006.217.08:25:59.88#ibcon#about to read 4, iclass 23, count 0 2006.217.08:25:59.88#ibcon#read 4, iclass 23, count 0 2006.217.08:25:59.88#ibcon#about to read 5, iclass 23, count 0 2006.217.08:25:59.88#ibcon#read 5, iclass 23, count 0 2006.217.08:25:59.88#ibcon#about to read 6, iclass 23, count 0 2006.217.08:25:59.88#ibcon#read 6, iclass 23, count 0 2006.217.08:25:59.88#ibcon#end of sib2, iclass 23, count 0 2006.217.08:25:59.88#ibcon#*mode == 0, iclass 23, count 0 2006.217.08:25:59.88#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.217.08:25:59.88#ibcon#[25=USB\r\n] 2006.217.08:25:59.88#ibcon#*before write, iclass 23, count 0 2006.217.08:25:59.88#ibcon#enter sib2, iclass 23, count 0 2006.217.08:25:59.88#ibcon#flushed, iclass 23, count 0 2006.217.08:25:59.88#ibcon#about to write, iclass 23, count 0 2006.217.08:25:59.88#ibcon#wrote, iclass 23, count 0 2006.217.08:25:59.88#ibcon#about to read 3, iclass 23, count 0 2006.217.08:25:59.91#ibcon#read 3, iclass 23, count 0 2006.217.08:25:59.91#ibcon#about to read 4, iclass 23, count 0 2006.217.08:25:59.91#ibcon#read 4, iclass 23, count 0 2006.217.08:25:59.91#ibcon#about to read 5, iclass 23, count 0 2006.217.08:25:59.91#ibcon#read 5, iclass 23, count 0 2006.217.08:25:59.91#ibcon#about to read 6, iclass 23, count 0 2006.217.08:25:59.91#ibcon#read 6, iclass 23, count 0 2006.217.08:25:59.91#ibcon#end of sib2, iclass 23, count 0 2006.217.08:25:59.91#ibcon#*after write, iclass 23, count 0 2006.217.08:25:59.91#ibcon#*before return 0, iclass 23, count 0 2006.217.08:25:59.91#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.217.08:25:59.91#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.217.08:25:59.91#ibcon#about to clear, iclass 23 cls_cnt 0 2006.217.08:25:59.91#ibcon#cleared, iclass 23 cls_cnt 0 2006.217.08:25:59.91$vc4f8/valo=7,832.99 2006.217.08:25:59.91#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.217.08:25:59.91#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.217.08:25:59.91#ibcon#ireg 17 cls_cnt 0 2006.217.08:25:59.91#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.217.08:25:59.91#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.217.08:25:59.91#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.217.08:25:59.91#ibcon#enter wrdev, iclass 25, count 0 2006.217.08:25:59.91#ibcon#first serial, iclass 25, count 0 2006.217.08:25:59.91#ibcon#enter sib2, iclass 25, count 0 2006.217.08:25:59.91#ibcon#flushed, iclass 25, count 0 2006.217.08:25:59.91#ibcon#about to write, iclass 25, count 0 2006.217.08:25:59.91#ibcon#wrote, iclass 25, count 0 2006.217.08:25:59.91#ibcon#about to read 3, iclass 25, count 0 2006.217.08:25:59.93#ibcon#read 3, iclass 25, count 0 2006.217.08:25:59.93#ibcon#about to read 4, iclass 25, count 0 2006.217.08:25:59.93#ibcon#read 4, iclass 25, count 0 2006.217.08:25:59.93#ibcon#about to read 5, iclass 25, count 0 2006.217.08:25:59.93#ibcon#read 5, iclass 25, count 0 2006.217.08:25:59.93#ibcon#about to read 6, iclass 25, count 0 2006.217.08:25:59.93#ibcon#read 6, iclass 25, count 0 2006.217.08:25:59.93#ibcon#end of sib2, iclass 25, count 0 2006.217.08:25:59.93#ibcon#*mode == 0, iclass 25, count 0 2006.217.08:25:59.93#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.217.08:25:59.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.217.08:25:59.93#ibcon#*before write, iclass 25, count 0 2006.217.08:25:59.93#ibcon#enter sib2, iclass 25, count 0 2006.217.08:25:59.93#ibcon#flushed, iclass 25, count 0 2006.217.08:25:59.93#ibcon#about to write, iclass 25, count 0 2006.217.08:25:59.93#ibcon#wrote, iclass 25, count 0 2006.217.08:25:59.93#ibcon#about to read 3, iclass 25, count 0 2006.217.08:25:59.97#ibcon#read 3, iclass 25, count 0 2006.217.08:25:59.97#ibcon#about to read 4, iclass 25, count 0 2006.217.08:25:59.97#ibcon#read 4, iclass 25, count 0 2006.217.08:25:59.97#ibcon#about to read 5, iclass 25, count 0 2006.217.08:25:59.97#ibcon#read 5, iclass 25, count 0 2006.217.08:25:59.97#ibcon#about to read 6, iclass 25, count 0 2006.217.08:25:59.97#ibcon#read 6, iclass 25, count 0 2006.217.08:25:59.97#ibcon#end of sib2, iclass 25, count 0 2006.217.08:25:59.97#ibcon#*after write, iclass 25, count 0 2006.217.08:25:59.97#ibcon#*before return 0, iclass 25, count 0 2006.217.08:25:59.97#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.217.08:25:59.97#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.217.08:25:59.97#ibcon#about to clear, iclass 25 cls_cnt 0 2006.217.08:25:59.97#ibcon#cleared, iclass 25 cls_cnt 0 2006.217.08:25:59.97$vc4f8/va=7,6 2006.217.08:25:59.97#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.217.08:25:59.97#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.217.08:25:59.97#ibcon#ireg 11 cls_cnt 2 2006.217.08:25:59.97#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.217.08:26:00.03#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.217.08:26:00.03#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.217.08:26:00.03#ibcon#enter wrdev, iclass 27, count 2 2006.217.08:26:00.03#ibcon#first serial, iclass 27, count 2 2006.217.08:26:00.03#ibcon#enter sib2, iclass 27, count 2 2006.217.08:26:00.03#ibcon#flushed, iclass 27, count 2 2006.217.08:26:00.03#ibcon#about to write, iclass 27, count 2 2006.217.08:26:00.03#ibcon#wrote, iclass 27, count 2 2006.217.08:26:00.03#ibcon#about to read 3, iclass 27, count 2 2006.217.08:26:00.05#ibcon#read 3, iclass 27, count 2 2006.217.08:26:00.05#ibcon#about to read 4, iclass 27, count 2 2006.217.08:26:00.05#ibcon#read 4, iclass 27, count 2 2006.217.08:26:00.05#ibcon#about to read 5, iclass 27, count 2 2006.217.08:26:00.05#ibcon#read 5, iclass 27, count 2 2006.217.08:26:00.05#ibcon#about to read 6, iclass 27, count 2 2006.217.08:26:00.05#ibcon#read 6, iclass 27, count 2 2006.217.08:26:00.05#ibcon#end of sib2, iclass 27, count 2 2006.217.08:26:00.05#ibcon#*mode == 0, iclass 27, count 2 2006.217.08:26:00.05#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.217.08:26:00.05#ibcon#[25=AT07-06\r\n] 2006.217.08:26:00.05#ibcon#*before write, iclass 27, count 2 2006.217.08:26:00.05#ibcon#enter sib2, iclass 27, count 2 2006.217.08:26:00.05#ibcon#flushed, iclass 27, count 2 2006.217.08:26:00.05#ibcon#about to write, iclass 27, count 2 2006.217.08:26:00.05#ibcon#wrote, iclass 27, count 2 2006.217.08:26:00.05#ibcon#about to read 3, iclass 27, count 2 2006.217.08:26:00.08#ibcon#read 3, iclass 27, count 2 2006.217.08:26:00.08#ibcon#about to read 4, iclass 27, count 2 2006.217.08:26:00.08#ibcon#read 4, iclass 27, count 2 2006.217.08:26:00.08#ibcon#about to read 5, iclass 27, count 2 2006.217.08:26:00.08#ibcon#read 5, iclass 27, count 2 2006.217.08:26:00.08#ibcon#about to read 6, iclass 27, count 2 2006.217.08:26:00.08#ibcon#read 6, iclass 27, count 2 2006.217.08:26:00.08#ibcon#end of sib2, iclass 27, count 2 2006.217.08:26:00.08#ibcon#*after write, iclass 27, count 2 2006.217.08:26:00.08#ibcon#*before return 0, iclass 27, count 2 2006.217.08:26:00.08#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.217.08:26:00.08#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.217.08:26:00.08#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.217.08:26:00.08#ibcon#ireg 7 cls_cnt 0 2006.217.08:26:00.08#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.217.08:26:00.20#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.217.08:26:00.20#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.217.08:26:00.20#ibcon#enter wrdev, iclass 27, count 0 2006.217.08:26:00.20#ibcon#first serial, iclass 27, count 0 2006.217.08:26:00.20#ibcon#enter sib2, iclass 27, count 0 2006.217.08:26:00.20#ibcon#flushed, iclass 27, count 0 2006.217.08:26:00.20#ibcon#about to write, iclass 27, count 0 2006.217.08:26:00.20#ibcon#wrote, iclass 27, count 0 2006.217.08:26:00.20#ibcon#about to read 3, iclass 27, count 0 2006.217.08:26:00.22#ibcon#read 3, iclass 27, count 0 2006.217.08:26:00.22#ibcon#about to read 4, iclass 27, count 0 2006.217.08:26:00.22#ibcon#read 4, iclass 27, count 0 2006.217.08:26:00.22#ibcon#about to read 5, iclass 27, count 0 2006.217.08:26:00.22#ibcon#read 5, iclass 27, count 0 2006.217.08:26:00.22#ibcon#about to read 6, iclass 27, count 0 2006.217.08:26:00.22#ibcon#read 6, iclass 27, count 0 2006.217.08:26:00.22#ibcon#end of sib2, iclass 27, count 0 2006.217.08:26:00.22#ibcon#*mode == 0, iclass 27, count 0 2006.217.08:26:00.22#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.217.08:26:00.22#ibcon#[25=USB\r\n] 2006.217.08:26:00.22#ibcon#*before write, iclass 27, count 0 2006.217.08:26:00.22#ibcon#enter sib2, iclass 27, count 0 2006.217.08:26:00.22#ibcon#flushed, iclass 27, count 0 2006.217.08:26:00.22#ibcon#about to write, iclass 27, count 0 2006.217.08:26:00.22#ibcon#wrote, iclass 27, count 0 2006.217.08:26:00.22#ibcon#about to read 3, iclass 27, count 0 2006.217.08:26:00.25#ibcon#read 3, iclass 27, count 0 2006.217.08:26:00.25#ibcon#about to read 4, iclass 27, count 0 2006.217.08:26:00.25#ibcon#read 4, iclass 27, count 0 2006.217.08:26:00.25#ibcon#about to read 5, iclass 27, count 0 2006.217.08:26:00.25#ibcon#read 5, iclass 27, count 0 2006.217.08:26:00.25#ibcon#about to read 6, iclass 27, count 0 2006.217.08:26:00.25#ibcon#read 6, iclass 27, count 0 2006.217.08:26:00.25#ibcon#end of sib2, iclass 27, count 0 2006.217.08:26:00.25#ibcon#*after write, iclass 27, count 0 2006.217.08:26:00.25#ibcon#*before return 0, iclass 27, count 0 2006.217.08:26:00.25#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.217.08:26:00.25#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.217.08:26:00.25#ibcon#about to clear, iclass 27 cls_cnt 0 2006.217.08:26:00.25#ibcon#cleared, iclass 27 cls_cnt 0 2006.217.08:26:00.25$vc4f8/valo=8,852.99 2006.217.08:26:00.25#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.217.08:26:00.25#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.217.08:26:00.25#ibcon#ireg 17 cls_cnt 0 2006.217.08:26:00.25#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.217.08:26:00.25#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.217.08:26:00.25#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.217.08:26:00.25#ibcon#enter wrdev, iclass 29, count 0 2006.217.08:26:00.25#ibcon#first serial, iclass 29, count 0 2006.217.08:26:00.25#ibcon#enter sib2, iclass 29, count 0 2006.217.08:26:00.25#ibcon#flushed, iclass 29, count 0 2006.217.08:26:00.25#ibcon#about to write, iclass 29, count 0 2006.217.08:26:00.25#ibcon#wrote, iclass 29, count 0 2006.217.08:26:00.25#ibcon#about to read 3, iclass 29, count 0 2006.217.08:26:00.27#ibcon#read 3, iclass 29, count 0 2006.217.08:26:00.27#ibcon#about to read 4, iclass 29, count 0 2006.217.08:26:00.27#ibcon#read 4, iclass 29, count 0 2006.217.08:26:00.27#ibcon#about to read 5, iclass 29, count 0 2006.217.08:26:00.27#ibcon#read 5, iclass 29, count 0 2006.217.08:26:00.27#ibcon#about to read 6, iclass 29, count 0 2006.217.08:26:00.27#ibcon#read 6, iclass 29, count 0 2006.217.08:26:00.27#ibcon#end of sib2, iclass 29, count 0 2006.217.08:26:00.27#ibcon#*mode == 0, iclass 29, count 0 2006.217.08:26:00.27#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.217.08:26:00.27#ibcon#[26=FRQ=08,852.99\r\n] 2006.217.08:26:00.27#ibcon#*before write, iclass 29, count 0 2006.217.08:26:00.27#ibcon#enter sib2, iclass 29, count 0 2006.217.08:26:00.27#ibcon#flushed, iclass 29, count 0 2006.217.08:26:00.27#ibcon#about to write, iclass 29, count 0 2006.217.08:26:00.27#ibcon#wrote, iclass 29, count 0 2006.217.08:26:00.27#ibcon#about to read 3, iclass 29, count 0 2006.217.08:26:00.31#ibcon#read 3, iclass 29, count 0 2006.217.08:26:00.31#ibcon#about to read 4, iclass 29, count 0 2006.217.08:26:00.31#ibcon#read 4, iclass 29, count 0 2006.217.08:26:00.31#ibcon#about to read 5, iclass 29, count 0 2006.217.08:26:00.31#ibcon#read 5, iclass 29, count 0 2006.217.08:26:00.31#ibcon#about to read 6, iclass 29, count 0 2006.217.08:26:00.31#ibcon#read 6, iclass 29, count 0 2006.217.08:26:00.31#ibcon#end of sib2, iclass 29, count 0 2006.217.08:26:00.31#ibcon#*after write, iclass 29, count 0 2006.217.08:26:00.31#ibcon#*before return 0, iclass 29, count 0 2006.217.08:26:00.31#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.217.08:26:00.31#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.217.08:26:00.31#ibcon#about to clear, iclass 29 cls_cnt 0 2006.217.08:26:00.31#ibcon#cleared, iclass 29 cls_cnt 0 2006.217.08:26:00.31$vc4f8/va=8,7 2006.217.08:26:00.31#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.217.08:26:00.31#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.217.08:26:00.31#ibcon#ireg 11 cls_cnt 2 2006.217.08:26:00.31#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.217.08:26:00.37#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.217.08:26:00.37#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.217.08:26:00.37#ibcon#enter wrdev, iclass 31, count 2 2006.217.08:26:00.37#ibcon#first serial, iclass 31, count 2 2006.217.08:26:00.37#ibcon#enter sib2, iclass 31, count 2 2006.217.08:26:00.37#ibcon#flushed, iclass 31, count 2 2006.217.08:26:00.37#ibcon#about to write, iclass 31, count 2 2006.217.08:26:00.37#ibcon#wrote, iclass 31, count 2 2006.217.08:26:00.37#ibcon#about to read 3, iclass 31, count 2 2006.217.08:26:00.39#ibcon#read 3, iclass 31, count 2 2006.217.08:26:00.39#ibcon#about to read 4, iclass 31, count 2 2006.217.08:26:00.39#ibcon#read 4, iclass 31, count 2 2006.217.08:26:00.39#ibcon#about to read 5, iclass 31, count 2 2006.217.08:26:00.39#ibcon#read 5, iclass 31, count 2 2006.217.08:26:00.39#ibcon#about to read 6, iclass 31, count 2 2006.217.08:26:00.39#ibcon#read 6, iclass 31, count 2 2006.217.08:26:00.39#ibcon#end of sib2, iclass 31, count 2 2006.217.08:26:00.39#ibcon#*mode == 0, iclass 31, count 2 2006.217.08:26:00.39#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.217.08:26:00.39#ibcon#[25=AT08-07\r\n] 2006.217.08:26:00.39#ibcon#*before write, iclass 31, count 2 2006.217.08:26:00.39#ibcon#enter sib2, iclass 31, count 2 2006.217.08:26:00.39#ibcon#flushed, iclass 31, count 2 2006.217.08:26:00.39#ibcon#about to write, iclass 31, count 2 2006.217.08:26:00.39#ibcon#wrote, iclass 31, count 2 2006.217.08:26:00.39#ibcon#about to read 3, iclass 31, count 2 2006.217.08:26:00.42#ibcon#read 3, iclass 31, count 2 2006.217.08:26:00.42#ibcon#about to read 4, iclass 31, count 2 2006.217.08:26:00.42#ibcon#read 4, iclass 31, count 2 2006.217.08:26:00.42#ibcon#about to read 5, iclass 31, count 2 2006.217.08:26:00.42#ibcon#read 5, iclass 31, count 2 2006.217.08:26:00.42#ibcon#about to read 6, iclass 31, count 2 2006.217.08:26:00.42#ibcon#read 6, iclass 31, count 2 2006.217.08:26:00.42#ibcon#end of sib2, iclass 31, count 2 2006.217.08:26:00.42#ibcon#*after write, iclass 31, count 2 2006.217.08:26:00.42#ibcon#*before return 0, iclass 31, count 2 2006.217.08:26:00.42#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.217.08:26:00.42#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.217.08:26:00.42#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.217.08:26:00.42#ibcon#ireg 7 cls_cnt 0 2006.217.08:26:00.42#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.217.08:26:00.54#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.217.08:26:00.54#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.217.08:26:00.54#ibcon#enter wrdev, iclass 31, count 0 2006.217.08:26:00.54#ibcon#first serial, iclass 31, count 0 2006.217.08:26:00.54#ibcon#enter sib2, iclass 31, count 0 2006.217.08:26:00.54#ibcon#flushed, iclass 31, count 0 2006.217.08:26:00.54#ibcon#about to write, iclass 31, count 0 2006.217.08:26:00.54#ibcon#wrote, iclass 31, count 0 2006.217.08:26:00.54#ibcon#about to read 3, iclass 31, count 0 2006.217.08:26:00.56#ibcon#read 3, iclass 31, count 0 2006.217.08:26:00.56#ibcon#about to read 4, iclass 31, count 0 2006.217.08:26:00.56#ibcon#read 4, iclass 31, count 0 2006.217.08:26:00.56#ibcon#about to read 5, iclass 31, count 0 2006.217.08:26:00.56#ibcon#read 5, iclass 31, count 0 2006.217.08:26:00.56#ibcon#about to read 6, iclass 31, count 0 2006.217.08:26:00.56#ibcon#read 6, iclass 31, count 0 2006.217.08:26:00.56#ibcon#end of sib2, iclass 31, count 0 2006.217.08:26:00.56#ibcon#*mode == 0, iclass 31, count 0 2006.217.08:26:00.56#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.217.08:26:00.56#ibcon#[25=USB\r\n] 2006.217.08:26:00.56#ibcon#*before write, iclass 31, count 0 2006.217.08:26:00.56#ibcon#enter sib2, iclass 31, count 0 2006.217.08:26:00.56#ibcon#flushed, iclass 31, count 0 2006.217.08:26:00.56#ibcon#about to write, iclass 31, count 0 2006.217.08:26:00.56#ibcon#wrote, iclass 31, count 0 2006.217.08:26:00.56#ibcon#about to read 3, iclass 31, count 0 2006.217.08:26:00.59#ibcon#read 3, iclass 31, count 0 2006.217.08:26:00.59#ibcon#about to read 4, iclass 31, count 0 2006.217.08:26:00.59#ibcon#read 4, iclass 31, count 0 2006.217.08:26:00.59#ibcon#about to read 5, iclass 31, count 0 2006.217.08:26:00.59#ibcon#read 5, iclass 31, count 0 2006.217.08:26:00.59#ibcon#about to read 6, iclass 31, count 0 2006.217.08:26:00.59#ibcon#read 6, iclass 31, count 0 2006.217.08:26:00.59#ibcon#end of sib2, iclass 31, count 0 2006.217.08:26:00.59#ibcon#*after write, iclass 31, count 0 2006.217.08:26:00.59#ibcon#*before return 0, iclass 31, count 0 2006.217.08:26:00.59#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.217.08:26:00.59#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.217.08:26:00.59#ibcon#about to clear, iclass 31 cls_cnt 0 2006.217.08:26:00.59#ibcon#cleared, iclass 31 cls_cnt 0 2006.217.08:26:00.59$vc4f8/vblo=1,632.99 2006.217.08:26:00.59#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.217.08:26:00.59#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.217.08:26:00.59#ibcon#ireg 17 cls_cnt 0 2006.217.08:26:00.59#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.217.08:26:00.59#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.217.08:26:00.59#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.217.08:26:00.59#ibcon#enter wrdev, iclass 33, count 0 2006.217.08:26:00.59#ibcon#first serial, iclass 33, count 0 2006.217.08:26:00.59#ibcon#enter sib2, iclass 33, count 0 2006.217.08:26:00.59#ibcon#flushed, iclass 33, count 0 2006.217.08:26:00.59#ibcon#about to write, iclass 33, count 0 2006.217.08:26:00.59#ibcon#wrote, iclass 33, count 0 2006.217.08:26:00.59#ibcon#about to read 3, iclass 33, count 0 2006.217.08:26:00.61#ibcon#read 3, iclass 33, count 0 2006.217.08:26:00.61#ibcon#about to read 4, iclass 33, count 0 2006.217.08:26:00.61#ibcon#read 4, iclass 33, count 0 2006.217.08:26:00.61#ibcon#about to read 5, iclass 33, count 0 2006.217.08:26:00.61#ibcon#read 5, iclass 33, count 0 2006.217.08:26:00.61#ibcon#about to read 6, iclass 33, count 0 2006.217.08:26:00.61#ibcon#read 6, iclass 33, count 0 2006.217.08:26:00.61#ibcon#end of sib2, iclass 33, count 0 2006.217.08:26:00.61#ibcon#*mode == 0, iclass 33, count 0 2006.217.08:26:00.61#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.217.08:26:00.61#ibcon#[28=FRQ=01,632.99\r\n] 2006.217.08:26:00.61#ibcon#*before write, iclass 33, count 0 2006.217.08:26:00.61#ibcon#enter sib2, iclass 33, count 0 2006.217.08:26:00.61#ibcon#flushed, iclass 33, count 0 2006.217.08:26:00.61#ibcon#about to write, iclass 33, count 0 2006.217.08:26:00.61#ibcon#wrote, iclass 33, count 0 2006.217.08:26:00.61#ibcon#about to read 3, iclass 33, count 0 2006.217.08:26:00.65#ibcon#read 3, iclass 33, count 0 2006.217.08:26:00.65#ibcon#about to read 4, iclass 33, count 0 2006.217.08:26:00.65#ibcon#read 4, iclass 33, count 0 2006.217.08:26:00.65#ibcon#about to read 5, iclass 33, count 0 2006.217.08:26:00.65#ibcon#read 5, iclass 33, count 0 2006.217.08:26:00.65#ibcon#about to read 6, iclass 33, count 0 2006.217.08:26:00.65#ibcon#read 6, iclass 33, count 0 2006.217.08:26:00.65#ibcon#end of sib2, iclass 33, count 0 2006.217.08:26:00.65#ibcon#*after write, iclass 33, count 0 2006.217.08:26:00.65#ibcon#*before return 0, iclass 33, count 0 2006.217.08:26:00.65#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.217.08:26:00.65#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.217.08:26:00.65#ibcon#about to clear, iclass 33 cls_cnt 0 2006.217.08:26:00.65#ibcon#cleared, iclass 33 cls_cnt 0 2006.217.08:26:00.65$vc4f8/vb=1,4 2006.217.08:26:00.65#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.217.08:26:00.65#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.217.08:26:00.65#ibcon#ireg 11 cls_cnt 2 2006.217.08:26:00.65#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.217.08:26:00.65#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.217.08:26:00.65#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.217.08:26:00.65#ibcon#enter wrdev, iclass 35, count 2 2006.217.08:26:00.65#ibcon#first serial, iclass 35, count 2 2006.217.08:26:00.65#ibcon#enter sib2, iclass 35, count 2 2006.217.08:26:00.65#ibcon#flushed, iclass 35, count 2 2006.217.08:26:00.65#ibcon#about to write, iclass 35, count 2 2006.217.08:26:00.65#ibcon#wrote, iclass 35, count 2 2006.217.08:26:00.65#ibcon#about to read 3, iclass 35, count 2 2006.217.08:26:00.67#ibcon#read 3, iclass 35, count 2 2006.217.08:26:00.67#ibcon#about to read 4, iclass 35, count 2 2006.217.08:26:00.67#ibcon#read 4, iclass 35, count 2 2006.217.08:26:00.67#ibcon#about to read 5, iclass 35, count 2 2006.217.08:26:00.67#ibcon#read 5, iclass 35, count 2 2006.217.08:26:00.67#ibcon#about to read 6, iclass 35, count 2 2006.217.08:26:00.67#ibcon#read 6, iclass 35, count 2 2006.217.08:26:00.67#ibcon#end of sib2, iclass 35, count 2 2006.217.08:26:00.67#ibcon#*mode == 0, iclass 35, count 2 2006.217.08:26:00.67#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.217.08:26:00.67#ibcon#[27=AT01-04\r\n] 2006.217.08:26:00.67#ibcon#*before write, iclass 35, count 2 2006.217.08:26:00.67#ibcon#enter sib2, iclass 35, count 2 2006.217.08:26:00.67#ibcon#flushed, iclass 35, count 2 2006.217.08:26:00.67#ibcon#about to write, iclass 35, count 2 2006.217.08:26:00.67#ibcon#wrote, iclass 35, count 2 2006.217.08:26:00.67#ibcon#about to read 3, iclass 35, count 2 2006.217.08:26:00.70#ibcon#read 3, iclass 35, count 2 2006.217.08:26:00.70#ibcon#about to read 4, iclass 35, count 2 2006.217.08:26:00.70#ibcon#read 4, iclass 35, count 2 2006.217.08:26:00.70#ibcon#about to read 5, iclass 35, count 2 2006.217.08:26:00.70#ibcon#read 5, iclass 35, count 2 2006.217.08:26:00.70#ibcon#about to read 6, iclass 35, count 2 2006.217.08:26:00.70#ibcon#read 6, iclass 35, count 2 2006.217.08:26:00.70#ibcon#end of sib2, iclass 35, count 2 2006.217.08:26:00.70#ibcon#*after write, iclass 35, count 2 2006.217.08:26:00.70#ibcon#*before return 0, iclass 35, count 2 2006.217.08:26:00.70#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.217.08:26:00.70#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.217.08:26:00.70#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.217.08:26:00.70#ibcon#ireg 7 cls_cnt 0 2006.217.08:26:00.70#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.217.08:26:00.82#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.217.08:26:00.82#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.217.08:26:00.82#ibcon#enter wrdev, iclass 35, count 0 2006.217.08:26:00.82#ibcon#first serial, iclass 35, count 0 2006.217.08:26:00.82#ibcon#enter sib2, iclass 35, count 0 2006.217.08:26:00.82#ibcon#flushed, iclass 35, count 0 2006.217.08:26:00.82#ibcon#about to write, iclass 35, count 0 2006.217.08:26:00.82#ibcon#wrote, iclass 35, count 0 2006.217.08:26:00.82#ibcon#about to read 3, iclass 35, count 0 2006.217.08:26:00.84#ibcon#read 3, iclass 35, count 0 2006.217.08:26:00.84#ibcon#about to read 4, iclass 35, count 0 2006.217.08:26:00.84#ibcon#read 4, iclass 35, count 0 2006.217.08:26:00.84#ibcon#about to read 5, iclass 35, count 0 2006.217.08:26:00.84#ibcon#read 5, iclass 35, count 0 2006.217.08:26:00.84#ibcon#about to read 6, iclass 35, count 0 2006.217.08:26:00.84#ibcon#read 6, iclass 35, count 0 2006.217.08:26:00.84#ibcon#end of sib2, iclass 35, count 0 2006.217.08:26:00.84#ibcon#*mode == 0, iclass 35, count 0 2006.217.08:26:00.84#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.217.08:26:00.84#ibcon#[27=USB\r\n] 2006.217.08:26:00.84#ibcon#*before write, iclass 35, count 0 2006.217.08:26:00.84#ibcon#enter sib2, iclass 35, count 0 2006.217.08:26:00.84#ibcon#flushed, iclass 35, count 0 2006.217.08:26:00.84#ibcon#about to write, iclass 35, count 0 2006.217.08:26:00.84#ibcon#wrote, iclass 35, count 0 2006.217.08:26:00.84#ibcon#about to read 3, iclass 35, count 0 2006.217.08:26:00.87#ibcon#read 3, iclass 35, count 0 2006.217.08:26:00.87#ibcon#about to read 4, iclass 35, count 0 2006.217.08:26:00.87#ibcon#read 4, iclass 35, count 0 2006.217.08:26:00.87#ibcon#about to read 5, iclass 35, count 0 2006.217.08:26:00.87#ibcon#read 5, iclass 35, count 0 2006.217.08:26:00.87#ibcon#about to read 6, iclass 35, count 0 2006.217.08:26:00.87#ibcon#read 6, iclass 35, count 0 2006.217.08:26:00.87#ibcon#end of sib2, iclass 35, count 0 2006.217.08:26:00.87#ibcon#*after write, iclass 35, count 0 2006.217.08:26:00.87#ibcon#*before return 0, iclass 35, count 0 2006.217.08:26:00.87#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.217.08:26:00.87#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.217.08:26:00.87#ibcon#about to clear, iclass 35 cls_cnt 0 2006.217.08:26:00.87#ibcon#cleared, iclass 35 cls_cnt 0 2006.217.08:26:00.87$vc4f8/vblo=2,640.99 2006.217.08:26:00.87#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.217.08:26:00.87#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.217.08:26:00.87#ibcon#ireg 17 cls_cnt 0 2006.217.08:26:00.87#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.217.08:26:00.87#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.217.08:26:00.87#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.217.08:26:00.87#ibcon#enter wrdev, iclass 37, count 0 2006.217.08:26:00.87#ibcon#first serial, iclass 37, count 0 2006.217.08:26:00.87#ibcon#enter sib2, iclass 37, count 0 2006.217.08:26:00.87#ibcon#flushed, iclass 37, count 0 2006.217.08:26:00.87#ibcon#about to write, iclass 37, count 0 2006.217.08:26:00.87#ibcon#wrote, iclass 37, count 0 2006.217.08:26:00.87#ibcon#about to read 3, iclass 37, count 0 2006.217.08:26:00.89#ibcon#read 3, iclass 37, count 0 2006.217.08:26:00.89#ibcon#about to read 4, iclass 37, count 0 2006.217.08:26:00.89#ibcon#read 4, iclass 37, count 0 2006.217.08:26:00.89#ibcon#about to read 5, iclass 37, count 0 2006.217.08:26:00.89#ibcon#read 5, iclass 37, count 0 2006.217.08:26:00.89#ibcon#about to read 6, iclass 37, count 0 2006.217.08:26:00.89#ibcon#read 6, iclass 37, count 0 2006.217.08:26:00.89#ibcon#end of sib2, iclass 37, count 0 2006.217.08:26:00.89#ibcon#*mode == 0, iclass 37, count 0 2006.217.08:26:00.89#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.217.08:26:00.89#ibcon#[28=FRQ=02,640.99\r\n] 2006.217.08:26:00.89#ibcon#*before write, iclass 37, count 0 2006.217.08:26:00.89#ibcon#enter sib2, iclass 37, count 0 2006.217.08:26:00.89#ibcon#flushed, iclass 37, count 0 2006.217.08:26:00.89#ibcon#about to write, iclass 37, count 0 2006.217.08:26:00.89#ibcon#wrote, iclass 37, count 0 2006.217.08:26:00.89#ibcon#about to read 3, iclass 37, count 0 2006.217.08:26:00.93#ibcon#read 3, iclass 37, count 0 2006.217.08:26:00.93#ibcon#about to read 4, iclass 37, count 0 2006.217.08:26:00.93#ibcon#read 4, iclass 37, count 0 2006.217.08:26:00.93#ibcon#about to read 5, iclass 37, count 0 2006.217.08:26:00.93#ibcon#read 5, iclass 37, count 0 2006.217.08:26:00.93#ibcon#about to read 6, iclass 37, count 0 2006.217.08:26:00.93#ibcon#read 6, iclass 37, count 0 2006.217.08:26:00.93#ibcon#end of sib2, iclass 37, count 0 2006.217.08:26:00.93#ibcon#*after write, iclass 37, count 0 2006.217.08:26:00.93#ibcon#*before return 0, iclass 37, count 0 2006.217.08:26:00.93#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.217.08:26:00.93#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.217.08:26:00.93#ibcon#about to clear, iclass 37 cls_cnt 0 2006.217.08:26:00.93#ibcon#cleared, iclass 37 cls_cnt 0 2006.217.08:26:00.93$vc4f8/vb=2,4 2006.217.08:26:00.93#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.217.08:26:00.93#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.217.08:26:00.93#ibcon#ireg 11 cls_cnt 2 2006.217.08:26:00.93#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.217.08:26:00.99#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.217.08:26:00.99#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.217.08:26:00.99#ibcon#enter wrdev, iclass 39, count 2 2006.217.08:26:00.99#ibcon#first serial, iclass 39, count 2 2006.217.08:26:00.99#ibcon#enter sib2, iclass 39, count 2 2006.217.08:26:00.99#ibcon#flushed, iclass 39, count 2 2006.217.08:26:00.99#ibcon#about to write, iclass 39, count 2 2006.217.08:26:00.99#ibcon#wrote, iclass 39, count 2 2006.217.08:26:00.99#ibcon#about to read 3, iclass 39, count 2 2006.217.08:26:01.01#ibcon#read 3, iclass 39, count 2 2006.217.08:26:01.01#ibcon#about to read 4, iclass 39, count 2 2006.217.08:26:01.01#ibcon#read 4, iclass 39, count 2 2006.217.08:26:01.01#ibcon#about to read 5, iclass 39, count 2 2006.217.08:26:01.01#ibcon#read 5, iclass 39, count 2 2006.217.08:26:01.01#ibcon#about to read 6, iclass 39, count 2 2006.217.08:26:01.01#ibcon#read 6, iclass 39, count 2 2006.217.08:26:01.01#ibcon#end of sib2, iclass 39, count 2 2006.217.08:26:01.01#ibcon#*mode == 0, iclass 39, count 2 2006.217.08:26:01.01#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.217.08:26:01.01#ibcon#[27=AT02-04\r\n] 2006.217.08:26:01.01#ibcon#*before write, iclass 39, count 2 2006.217.08:26:01.01#ibcon#enter sib2, iclass 39, count 2 2006.217.08:26:01.01#ibcon#flushed, iclass 39, count 2 2006.217.08:26:01.01#ibcon#about to write, iclass 39, count 2 2006.217.08:26:01.01#ibcon#wrote, iclass 39, count 2 2006.217.08:26:01.01#ibcon#about to read 3, iclass 39, count 2 2006.217.08:26:01.04#ibcon#read 3, iclass 39, count 2 2006.217.08:26:01.04#ibcon#about to read 4, iclass 39, count 2 2006.217.08:26:01.04#ibcon#read 4, iclass 39, count 2 2006.217.08:26:01.04#ibcon#about to read 5, iclass 39, count 2 2006.217.08:26:01.04#ibcon#read 5, iclass 39, count 2 2006.217.08:26:01.04#ibcon#about to read 6, iclass 39, count 2 2006.217.08:26:01.04#ibcon#read 6, iclass 39, count 2 2006.217.08:26:01.04#ibcon#end of sib2, iclass 39, count 2 2006.217.08:26:01.04#ibcon#*after write, iclass 39, count 2 2006.217.08:26:01.04#ibcon#*before return 0, iclass 39, count 2 2006.217.08:26:01.04#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.217.08:26:01.04#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.217.08:26:01.04#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.217.08:26:01.04#ibcon#ireg 7 cls_cnt 0 2006.217.08:26:01.04#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.217.08:26:01.16#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.217.08:26:01.16#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.217.08:26:01.16#ibcon#enter wrdev, iclass 39, count 0 2006.217.08:26:01.16#ibcon#first serial, iclass 39, count 0 2006.217.08:26:01.16#ibcon#enter sib2, iclass 39, count 0 2006.217.08:26:01.16#ibcon#flushed, iclass 39, count 0 2006.217.08:26:01.16#ibcon#about to write, iclass 39, count 0 2006.217.08:26:01.16#ibcon#wrote, iclass 39, count 0 2006.217.08:26:01.16#ibcon#about to read 3, iclass 39, count 0 2006.217.08:26:01.18#ibcon#read 3, iclass 39, count 0 2006.217.08:26:01.18#ibcon#about to read 4, iclass 39, count 0 2006.217.08:26:01.18#ibcon#read 4, iclass 39, count 0 2006.217.08:26:01.18#ibcon#about to read 5, iclass 39, count 0 2006.217.08:26:01.18#ibcon#read 5, iclass 39, count 0 2006.217.08:26:01.18#ibcon#about to read 6, iclass 39, count 0 2006.217.08:26:01.18#ibcon#read 6, iclass 39, count 0 2006.217.08:26:01.18#ibcon#end of sib2, iclass 39, count 0 2006.217.08:26:01.18#ibcon#*mode == 0, iclass 39, count 0 2006.217.08:26:01.18#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.217.08:26:01.18#ibcon#[27=USB\r\n] 2006.217.08:26:01.18#ibcon#*before write, iclass 39, count 0 2006.217.08:26:01.18#ibcon#enter sib2, iclass 39, count 0 2006.217.08:26:01.18#ibcon#flushed, iclass 39, count 0 2006.217.08:26:01.18#ibcon#about to write, iclass 39, count 0 2006.217.08:26:01.18#ibcon#wrote, iclass 39, count 0 2006.217.08:26:01.18#ibcon#about to read 3, iclass 39, count 0 2006.217.08:26:01.21#ibcon#read 3, iclass 39, count 0 2006.217.08:26:01.21#ibcon#about to read 4, iclass 39, count 0 2006.217.08:26:01.21#ibcon#read 4, iclass 39, count 0 2006.217.08:26:01.21#ibcon#about to read 5, iclass 39, count 0 2006.217.08:26:01.21#ibcon#read 5, iclass 39, count 0 2006.217.08:26:01.21#ibcon#about to read 6, iclass 39, count 0 2006.217.08:26:01.21#ibcon#read 6, iclass 39, count 0 2006.217.08:26:01.21#ibcon#end of sib2, iclass 39, count 0 2006.217.08:26:01.21#ibcon#*after write, iclass 39, count 0 2006.217.08:26:01.21#ibcon#*before return 0, iclass 39, count 0 2006.217.08:26:01.21#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.217.08:26:01.21#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.217.08:26:01.21#ibcon#about to clear, iclass 39 cls_cnt 0 2006.217.08:26:01.21#ibcon#cleared, iclass 39 cls_cnt 0 2006.217.08:26:01.21$vc4f8/vblo=3,656.99 2006.217.08:26:01.21#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.217.08:26:01.21#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.217.08:26:01.21#ibcon#ireg 17 cls_cnt 0 2006.217.08:26:01.21#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.217.08:26:01.21#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.217.08:26:01.21#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.217.08:26:01.21#ibcon#enter wrdev, iclass 3, count 0 2006.217.08:26:01.21#ibcon#first serial, iclass 3, count 0 2006.217.08:26:01.21#ibcon#enter sib2, iclass 3, count 0 2006.217.08:26:01.21#ibcon#flushed, iclass 3, count 0 2006.217.08:26:01.21#ibcon#about to write, iclass 3, count 0 2006.217.08:26:01.21#ibcon#wrote, iclass 3, count 0 2006.217.08:26:01.21#ibcon#about to read 3, iclass 3, count 0 2006.217.08:26:01.23#ibcon#read 3, iclass 3, count 0 2006.217.08:26:01.23#ibcon#about to read 4, iclass 3, count 0 2006.217.08:26:01.23#ibcon#read 4, iclass 3, count 0 2006.217.08:26:01.23#ibcon#about to read 5, iclass 3, count 0 2006.217.08:26:01.23#ibcon#read 5, iclass 3, count 0 2006.217.08:26:01.23#ibcon#about to read 6, iclass 3, count 0 2006.217.08:26:01.23#ibcon#read 6, iclass 3, count 0 2006.217.08:26:01.23#ibcon#end of sib2, iclass 3, count 0 2006.217.08:26:01.23#ibcon#*mode == 0, iclass 3, count 0 2006.217.08:26:01.23#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.217.08:26:01.23#ibcon#[28=FRQ=03,656.99\r\n] 2006.217.08:26:01.23#ibcon#*before write, iclass 3, count 0 2006.217.08:26:01.23#ibcon#enter sib2, iclass 3, count 0 2006.217.08:26:01.23#ibcon#flushed, iclass 3, count 0 2006.217.08:26:01.23#ibcon#about to write, iclass 3, count 0 2006.217.08:26:01.23#ibcon#wrote, iclass 3, count 0 2006.217.08:26:01.23#ibcon#about to read 3, iclass 3, count 0 2006.217.08:26:01.27#ibcon#read 3, iclass 3, count 0 2006.217.08:26:01.27#ibcon#about to read 4, iclass 3, count 0 2006.217.08:26:01.27#ibcon#read 4, iclass 3, count 0 2006.217.08:26:01.27#ibcon#about to read 5, iclass 3, count 0 2006.217.08:26:01.27#ibcon#read 5, iclass 3, count 0 2006.217.08:26:01.27#ibcon#about to read 6, iclass 3, count 0 2006.217.08:26:01.27#ibcon#read 6, iclass 3, count 0 2006.217.08:26:01.27#ibcon#end of sib2, iclass 3, count 0 2006.217.08:26:01.27#ibcon#*after write, iclass 3, count 0 2006.217.08:26:01.27#ibcon#*before return 0, iclass 3, count 0 2006.217.08:26:01.27#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.217.08:26:01.27#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.217.08:26:01.27#ibcon#about to clear, iclass 3 cls_cnt 0 2006.217.08:26:01.27#ibcon#cleared, iclass 3 cls_cnt 0 2006.217.08:26:01.27$vc4f8/vb=3,4 2006.217.08:26:01.27#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.217.08:26:01.27#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.217.08:26:01.27#ibcon#ireg 11 cls_cnt 2 2006.217.08:26:01.27#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.217.08:26:01.33#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.217.08:26:01.33#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.217.08:26:01.33#ibcon#enter wrdev, iclass 5, count 2 2006.217.08:26:01.33#ibcon#first serial, iclass 5, count 2 2006.217.08:26:01.33#ibcon#enter sib2, iclass 5, count 2 2006.217.08:26:01.33#ibcon#flushed, iclass 5, count 2 2006.217.08:26:01.33#ibcon#about to write, iclass 5, count 2 2006.217.08:26:01.33#ibcon#wrote, iclass 5, count 2 2006.217.08:26:01.33#ibcon#about to read 3, iclass 5, count 2 2006.217.08:26:01.35#ibcon#read 3, iclass 5, count 2 2006.217.08:26:01.35#ibcon#about to read 4, iclass 5, count 2 2006.217.08:26:01.35#ibcon#read 4, iclass 5, count 2 2006.217.08:26:01.35#ibcon#about to read 5, iclass 5, count 2 2006.217.08:26:01.35#ibcon#read 5, iclass 5, count 2 2006.217.08:26:01.35#ibcon#about to read 6, iclass 5, count 2 2006.217.08:26:01.35#ibcon#read 6, iclass 5, count 2 2006.217.08:26:01.35#ibcon#end of sib2, iclass 5, count 2 2006.217.08:26:01.35#ibcon#*mode == 0, iclass 5, count 2 2006.217.08:26:01.35#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.217.08:26:01.35#ibcon#[27=AT03-04\r\n] 2006.217.08:26:01.35#ibcon#*before write, iclass 5, count 2 2006.217.08:26:01.35#ibcon#enter sib2, iclass 5, count 2 2006.217.08:26:01.35#ibcon#flushed, iclass 5, count 2 2006.217.08:26:01.35#ibcon#about to write, iclass 5, count 2 2006.217.08:26:01.35#ibcon#wrote, iclass 5, count 2 2006.217.08:26:01.35#ibcon#about to read 3, iclass 5, count 2 2006.217.08:26:01.38#ibcon#read 3, iclass 5, count 2 2006.217.08:26:01.38#ibcon#about to read 4, iclass 5, count 2 2006.217.08:26:01.38#ibcon#read 4, iclass 5, count 2 2006.217.08:26:01.38#ibcon#about to read 5, iclass 5, count 2 2006.217.08:26:01.38#ibcon#read 5, iclass 5, count 2 2006.217.08:26:01.38#ibcon#about to read 6, iclass 5, count 2 2006.217.08:26:01.38#ibcon#read 6, iclass 5, count 2 2006.217.08:26:01.38#ibcon#end of sib2, iclass 5, count 2 2006.217.08:26:01.38#ibcon#*after write, iclass 5, count 2 2006.217.08:26:01.38#ibcon#*before return 0, iclass 5, count 2 2006.217.08:26:01.38#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.217.08:26:01.38#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.217.08:26:01.38#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.217.08:26:01.38#ibcon#ireg 7 cls_cnt 0 2006.217.08:26:01.38#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.217.08:26:01.50#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.217.08:26:01.50#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.217.08:26:01.50#ibcon#enter wrdev, iclass 5, count 0 2006.217.08:26:01.50#ibcon#first serial, iclass 5, count 0 2006.217.08:26:01.50#ibcon#enter sib2, iclass 5, count 0 2006.217.08:26:01.50#ibcon#flushed, iclass 5, count 0 2006.217.08:26:01.50#ibcon#about to write, iclass 5, count 0 2006.217.08:26:01.50#ibcon#wrote, iclass 5, count 0 2006.217.08:26:01.50#ibcon#about to read 3, iclass 5, count 0 2006.217.08:26:01.52#ibcon#read 3, iclass 5, count 0 2006.217.08:26:01.52#ibcon#about to read 4, iclass 5, count 0 2006.217.08:26:01.52#ibcon#read 4, iclass 5, count 0 2006.217.08:26:01.52#ibcon#about to read 5, iclass 5, count 0 2006.217.08:26:01.52#ibcon#read 5, iclass 5, count 0 2006.217.08:26:01.52#ibcon#about to read 6, iclass 5, count 0 2006.217.08:26:01.52#ibcon#read 6, iclass 5, count 0 2006.217.08:26:01.52#ibcon#end of sib2, iclass 5, count 0 2006.217.08:26:01.52#ibcon#*mode == 0, iclass 5, count 0 2006.217.08:26:01.52#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.217.08:26:01.52#ibcon#[27=USB\r\n] 2006.217.08:26:01.52#ibcon#*before write, iclass 5, count 0 2006.217.08:26:01.52#ibcon#enter sib2, iclass 5, count 0 2006.217.08:26:01.52#ibcon#flushed, iclass 5, count 0 2006.217.08:26:01.52#ibcon#about to write, iclass 5, count 0 2006.217.08:26:01.52#ibcon#wrote, iclass 5, count 0 2006.217.08:26:01.52#ibcon#about to read 3, iclass 5, count 0 2006.217.08:26:01.55#ibcon#read 3, iclass 5, count 0 2006.217.08:26:01.55#ibcon#about to read 4, iclass 5, count 0 2006.217.08:26:01.55#ibcon#read 4, iclass 5, count 0 2006.217.08:26:01.55#ibcon#about to read 5, iclass 5, count 0 2006.217.08:26:01.55#ibcon#read 5, iclass 5, count 0 2006.217.08:26:01.55#ibcon#about to read 6, iclass 5, count 0 2006.217.08:26:01.55#ibcon#read 6, iclass 5, count 0 2006.217.08:26:01.55#ibcon#end of sib2, iclass 5, count 0 2006.217.08:26:01.55#ibcon#*after write, iclass 5, count 0 2006.217.08:26:01.55#ibcon#*before return 0, iclass 5, count 0 2006.217.08:26:01.55#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.217.08:26:01.55#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.217.08:26:01.55#ibcon#about to clear, iclass 5 cls_cnt 0 2006.217.08:26:01.55#ibcon#cleared, iclass 5 cls_cnt 0 2006.217.08:26:01.55$vc4f8/vblo=4,712.99 2006.217.08:26:01.55#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.217.08:26:01.55#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.217.08:26:01.55#ibcon#ireg 17 cls_cnt 0 2006.217.08:26:01.55#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.217.08:26:01.55#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.217.08:26:01.55#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.217.08:26:01.55#ibcon#enter wrdev, iclass 7, count 0 2006.217.08:26:01.55#ibcon#first serial, iclass 7, count 0 2006.217.08:26:01.55#ibcon#enter sib2, iclass 7, count 0 2006.217.08:26:01.55#ibcon#flushed, iclass 7, count 0 2006.217.08:26:01.55#ibcon#about to write, iclass 7, count 0 2006.217.08:26:01.55#ibcon#wrote, iclass 7, count 0 2006.217.08:26:01.55#ibcon#about to read 3, iclass 7, count 0 2006.217.08:26:01.57#ibcon#read 3, iclass 7, count 0 2006.217.08:26:01.57#ibcon#about to read 4, iclass 7, count 0 2006.217.08:26:01.57#ibcon#read 4, iclass 7, count 0 2006.217.08:26:01.57#ibcon#about to read 5, iclass 7, count 0 2006.217.08:26:01.57#ibcon#read 5, iclass 7, count 0 2006.217.08:26:01.57#ibcon#about to read 6, iclass 7, count 0 2006.217.08:26:01.57#ibcon#read 6, iclass 7, count 0 2006.217.08:26:01.57#ibcon#end of sib2, iclass 7, count 0 2006.217.08:26:01.57#ibcon#*mode == 0, iclass 7, count 0 2006.217.08:26:01.57#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.217.08:26:01.57#ibcon#[28=FRQ=04,712.99\r\n] 2006.217.08:26:01.57#ibcon#*before write, iclass 7, count 0 2006.217.08:26:01.57#ibcon#enter sib2, iclass 7, count 0 2006.217.08:26:01.57#ibcon#flushed, iclass 7, count 0 2006.217.08:26:01.57#ibcon#about to write, iclass 7, count 0 2006.217.08:26:01.57#ibcon#wrote, iclass 7, count 0 2006.217.08:26:01.57#ibcon#about to read 3, iclass 7, count 0 2006.217.08:26:01.61#ibcon#read 3, iclass 7, count 0 2006.217.08:26:01.61#ibcon#about to read 4, iclass 7, count 0 2006.217.08:26:01.61#ibcon#read 4, iclass 7, count 0 2006.217.08:26:01.61#ibcon#about to read 5, iclass 7, count 0 2006.217.08:26:01.61#ibcon#read 5, iclass 7, count 0 2006.217.08:26:01.61#ibcon#about to read 6, iclass 7, count 0 2006.217.08:26:01.61#ibcon#read 6, iclass 7, count 0 2006.217.08:26:01.61#ibcon#end of sib2, iclass 7, count 0 2006.217.08:26:01.61#ibcon#*after write, iclass 7, count 0 2006.217.08:26:01.61#ibcon#*before return 0, iclass 7, count 0 2006.217.08:26:01.61#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.217.08:26:01.61#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.217.08:26:01.61#ibcon#about to clear, iclass 7 cls_cnt 0 2006.217.08:26:01.61#ibcon#cleared, iclass 7 cls_cnt 0 2006.217.08:26:01.61$vc4f8/vb=4,4 2006.217.08:26:01.61#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.217.08:26:01.61#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.217.08:26:01.61#ibcon#ireg 11 cls_cnt 2 2006.217.08:26:01.61#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.217.08:26:01.67#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.217.08:26:01.67#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.217.08:26:01.67#ibcon#enter wrdev, iclass 11, count 2 2006.217.08:26:01.67#ibcon#first serial, iclass 11, count 2 2006.217.08:26:01.67#ibcon#enter sib2, iclass 11, count 2 2006.217.08:26:01.67#ibcon#flushed, iclass 11, count 2 2006.217.08:26:01.67#ibcon#about to write, iclass 11, count 2 2006.217.08:26:01.67#ibcon#wrote, iclass 11, count 2 2006.217.08:26:01.67#ibcon#about to read 3, iclass 11, count 2 2006.217.08:26:01.69#ibcon#read 3, iclass 11, count 2 2006.217.08:26:01.69#ibcon#about to read 4, iclass 11, count 2 2006.217.08:26:01.69#ibcon#read 4, iclass 11, count 2 2006.217.08:26:01.69#ibcon#about to read 5, iclass 11, count 2 2006.217.08:26:01.69#ibcon#read 5, iclass 11, count 2 2006.217.08:26:01.69#ibcon#about to read 6, iclass 11, count 2 2006.217.08:26:01.69#ibcon#read 6, iclass 11, count 2 2006.217.08:26:01.69#ibcon#end of sib2, iclass 11, count 2 2006.217.08:26:01.69#ibcon#*mode == 0, iclass 11, count 2 2006.217.08:26:01.69#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.217.08:26:01.69#ibcon#[27=AT04-04\r\n] 2006.217.08:26:01.69#ibcon#*before write, iclass 11, count 2 2006.217.08:26:01.69#ibcon#enter sib2, iclass 11, count 2 2006.217.08:26:01.69#ibcon#flushed, iclass 11, count 2 2006.217.08:26:01.69#ibcon#about to write, iclass 11, count 2 2006.217.08:26:01.69#ibcon#wrote, iclass 11, count 2 2006.217.08:26:01.69#ibcon#about to read 3, iclass 11, count 2 2006.217.08:26:01.72#ibcon#read 3, iclass 11, count 2 2006.217.08:26:01.72#ibcon#about to read 4, iclass 11, count 2 2006.217.08:26:01.72#ibcon#read 4, iclass 11, count 2 2006.217.08:26:01.72#ibcon#about to read 5, iclass 11, count 2 2006.217.08:26:01.72#ibcon#read 5, iclass 11, count 2 2006.217.08:26:01.72#ibcon#about to read 6, iclass 11, count 2 2006.217.08:26:01.72#ibcon#read 6, iclass 11, count 2 2006.217.08:26:01.72#ibcon#end of sib2, iclass 11, count 2 2006.217.08:26:01.72#ibcon#*after write, iclass 11, count 2 2006.217.08:26:01.72#ibcon#*before return 0, iclass 11, count 2 2006.217.08:26:01.72#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.217.08:26:01.72#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.217.08:26:01.72#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.217.08:26:01.72#ibcon#ireg 7 cls_cnt 0 2006.217.08:26:01.72#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.217.08:26:01.84#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.217.08:26:01.84#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.217.08:26:01.84#ibcon#enter wrdev, iclass 11, count 0 2006.217.08:26:01.84#ibcon#first serial, iclass 11, count 0 2006.217.08:26:01.84#ibcon#enter sib2, iclass 11, count 0 2006.217.08:26:01.84#ibcon#flushed, iclass 11, count 0 2006.217.08:26:01.84#ibcon#about to write, iclass 11, count 0 2006.217.08:26:01.84#ibcon#wrote, iclass 11, count 0 2006.217.08:26:01.84#ibcon#about to read 3, iclass 11, count 0 2006.217.08:26:01.86#ibcon#read 3, iclass 11, count 0 2006.217.08:26:01.86#ibcon#about to read 4, iclass 11, count 0 2006.217.08:26:01.86#ibcon#read 4, iclass 11, count 0 2006.217.08:26:01.86#ibcon#about to read 5, iclass 11, count 0 2006.217.08:26:01.86#ibcon#read 5, iclass 11, count 0 2006.217.08:26:01.86#ibcon#about to read 6, iclass 11, count 0 2006.217.08:26:01.86#ibcon#read 6, iclass 11, count 0 2006.217.08:26:01.86#ibcon#end of sib2, iclass 11, count 0 2006.217.08:26:01.86#ibcon#*mode == 0, iclass 11, count 0 2006.217.08:26:01.86#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.217.08:26:01.86#ibcon#[27=USB\r\n] 2006.217.08:26:01.86#ibcon#*before write, iclass 11, count 0 2006.217.08:26:01.86#ibcon#enter sib2, iclass 11, count 0 2006.217.08:26:01.86#ibcon#flushed, iclass 11, count 0 2006.217.08:26:01.86#ibcon#about to write, iclass 11, count 0 2006.217.08:26:01.86#ibcon#wrote, iclass 11, count 0 2006.217.08:26:01.86#ibcon#about to read 3, iclass 11, count 0 2006.217.08:26:01.89#ibcon#read 3, iclass 11, count 0 2006.217.08:26:01.89#ibcon#about to read 4, iclass 11, count 0 2006.217.08:26:01.89#ibcon#read 4, iclass 11, count 0 2006.217.08:26:01.89#ibcon#about to read 5, iclass 11, count 0 2006.217.08:26:01.89#ibcon#read 5, iclass 11, count 0 2006.217.08:26:01.89#ibcon#about to read 6, iclass 11, count 0 2006.217.08:26:01.89#ibcon#read 6, iclass 11, count 0 2006.217.08:26:01.89#ibcon#end of sib2, iclass 11, count 0 2006.217.08:26:01.89#ibcon#*after write, iclass 11, count 0 2006.217.08:26:01.89#ibcon#*before return 0, iclass 11, count 0 2006.217.08:26:01.89#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.217.08:26:01.89#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.217.08:26:01.89#ibcon#about to clear, iclass 11 cls_cnt 0 2006.217.08:26:01.89#ibcon#cleared, iclass 11 cls_cnt 0 2006.217.08:26:01.89$vc4f8/vblo=5,744.99 2006.217.08:26:01.89#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.217.08:26:01.89#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.217.08:26:01.89#ibcon#ireg 17 cls_cnt 0 2006.217.08:26:01.89#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.217.08:26:01.89#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.217.08:26:01.89#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.217.08:26:01.89#ibcon#enter wrdev, iclass 13, count 0 2006.217.08:26:01.89#ibcon#first serial, iclass 13, count 0 2006.217.08:26:01.89#ibcon#enter sib2, iclass 13, count 0 2006.217.08:26:01.89#ibcon#flushed, iclass 13, count 0 2006.217.08:26:01.89#ibcon#about to write, iclass 13, count 0 2006.217.08:26:01.89#ibcon#wrote, iclass 13, count 0 2006.217.08:26:01.89#ibcon#about to read 3, iclass 13, count 0 2006.217.08:26:01.91#ibcon#read 3, iclass 13, count 0 2006.217.08:26:01.91#ibcon#about to read 4, iclass 13, count 0 2006.217.08:26:01.91#ibcon#read 4, iclass 13, count 0 2006.217.08:26:01.91#ibcon#about to read 5, iclass 13, count 0 2006.217.08:26:01.91#ibcon#read 5, iclass 13, count 0 2006.217.08:26:01.91#ibcon#about to read 6, iclass 13, count 0 2006.217.08:26:01.91#ibcon#read 6, iclass 13, count 0 2006.217.08:26:01.91#ibcon#end of sib2, iclass 13, count 0 2006.217.08:26:01.91#ibcon#*mode == 0, iclass 13, count 0 2006.217.08:26:01.91#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.217.08:26:01.91#ibcon#[28=FRQ=05,744.99\r\n] 2006.217.08:26:01.91#ibcon#*before write, iclass 13, count 0 2006.217.08:26:01.91#ibcon#enter sib2, iclass 13, count 0 2006.217.08:26:01.91#ibcon#flushed, iclass 13, count 0 2006.217.08:26:01.91#ibcon#about to write, iclass 13, count 0 2006.217.08:26:01.91#ibcon#wrote, iclass 13, count 0 2006.217.08:26:01.91#ibcon#about to read 3, iclass 13, count 0 2006.217.08:26:01.95#ibcon#read 3, iclass 13, count 0 2006.217.08:26:01.95#ibcon#about to read 4, iclass 13, count 0 2006.217.08:26:01.95#ibcon#read 4, iclass 13, count 0 2006.217.08:26:01.95#ibcon#about to read 5, iclass 13, count 0 2006.217.08:26:01.95#ibcon#read 5, iclass 13, count 0 2006.217.08:26:01.95#ibcon#about to read 6, iclass 13, count 0 2006.217.08:26:01.95#ibcon#read 6, iclass 13, count 0 2006.217.08:26:01.95#ibcon#end of sib2, iclass 13, count 0 2006.217.08:26:01.95#ibcon#*after write, iclass 13, count 0 2006.217.08:26:01.95#ibcon#*before return 0, iclass 13, count 0 2006.217.08:26:01.95#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.217.08:26:01.95#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.217.08:26:01.95#ibcon#about to clear, iclass 13 cls_cnt 0 2006.217.08:26:01.95#ibcon#cleared, iclass 13 cls_cnt 0 2006.217.08:26:01.95$vc4f8/vb=5,4 2006.217.08:26:01.95#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.217.08:26:01.95#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.217.08:26:01.95#ibcon#ireg 11 cls_cnt 2 2006.217.08:26:01.95#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.217.08:26:02.02#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.217.08:26:02.02#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.217.08:26:02.02#ibcon#enter wrdev, iclass 15, count 2 2006.217.08:26:02.02#ibcon#first serial, iclass 15, count 2 2006.217.08:26:02.02#ibcon#enter sib2, iclass 15, count 2 2006.217.08:26:02.02#ibcon#flushed, iclass 15, count 2 2006.217.08:26:02.02#ibcon#about to write, iclass 15, count 2 2006.217.08:26:02.02#ibcon#wrote, iclass 15, count 2 2006.217.08:26:02.02#ibcon#about to read 3, iclass 15, count 2 2006.217.08:26:02.03#ibcon#read 3, iclass 15, count 2 2006.217.08:26:02.03#ibcon#about to read 4, iclass 15, count 2 2006.217.08:26:02.03#ibcon#read 4, iclass 15, count 2 2006.217.08:26:02.03#ibcon#about to read 5, iclass 15, count 2 2006.217.08:26:02.03#ibcon#read 5, iclass 15, count 2 2006.217.08:26:02.03#ibcon#about to read 6, iclass 15, count 2 2006.217.08:26:02.03#ibcon#read 6, iclass 15, count 2 2006.217.08:26:02.03#ibcon#end of sib2, iclass 15, count 2 2006.217.08:26:02.03#ibcon#*mode == 0, iclass 15, count 2 2006.217.08:26:02.03#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.217.08:26:02.03#ibcon#[27=AT05-04\r\n] 2006.217.08:26:02.03#ibcon#*before write, iclass 15, count 2 2006.217.08:26:02.03#ibcon#enter sib2, iclass 15, count 2 2006.217.08:26:02.03#ibcon#flushed, iclass 15, count 2 2006.217.08:26:02.03#ibcon#about to write, iclass 15, count 2 2006.217.08:26:02.03#ibcon#wrote, iclass 15, count 2 2006.217.08:26:02.03#ibcon#about to read 3, iclass 15, count 2 2006.217.08:26:02.06#ibcon#read 3, iclass 15, count 2 2006.217.08:26:02.06#ibcon#about to read 4, iclass 15, count 2 2006.217.08:26:02.06#ibcon#read 4, iclass 15, count 2 2006.217.08:26:02.06#ibcon#about to read 5, iclass 15, count 2 2006.217.08:26:02.06#ibcon#read 5, iclass 15, count 2 2006.217.08:26:02.06#ibcon#about to read 6, iclass 15, count 2 2006.217.08:26:02.06#ibcon#read 6, iclass 15, count 2 2006.217.08:26:02.06#ibcon#end of sib2, iclass 15, count 2 2006.217.08:26:02.06#ibcon#*after write, iclass 15, count 2 2006.217.08:26:02.06#ibcon#*before return 0, iclass 15, count 2 2006.217.08:26:02.06#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.217.08:26:02.06#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.217.08:26:02.06#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.217.08:26:02.06#ibcon#ireg 7 cls_cnt 0 2006.217.08:26:02.06#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.217.08:26:02.18#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.217.08:26:02.18#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.217.08:26:02.18#ibcon#enter wrdev, iclass 15, count 0 2006.217.08:26:02.18#ibcon#first serial, iclass 15, count 0 2006.217.08:26:02.18#ibcon#enter sib2, iclass 15, count 0 2006.217.08:26:02.18#ibcon#flushed, iclass 15, count 0 2006.217.08:26:02.18#ibcon#about to write, iclass 15, count 0 2006.217.08:26:02.18#ibcon#wrote, iclass 15, count 0 2006.217.08:26:02.18#ibcon#about to read 3, iclass 15, count 0 2006.217.08:26:02.22#ibcon#read 3, iclass 15, count 0 2006.217.08:26:02.22#ibcon#about to read 4, iclass 15, count 0 2006.217.08:26:02.22#ibcon#read 4, iclass 15, count 0 2006.217.08:26:02.22#ibcon#about to read 5, iclass 15, count 0 2006.217.08:26:02.22#ibcon#read 5, iclass 15, count 0 2006.217.08:26:02.22#ibcon#about to read 6, iclass 15, count 0 2006.217.08:26:02.22#ibcon#read 6, iclass 15, count 0 2006.217.08:26:02.22#ibcon#end of sib2, iclass 15, count 0 2006.217.08:26:02.22#ibcon#*mode == 0, iclass 15, count 0 2006.217.08:26:02.22#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.217.08:26:02.22#ibcon#[27=USB\r\n] 2006.217.08:26:02.22#ibcon#*before write, iclass 15, count 0 2006.217.08:26:02.22#ibcon#enter sib2, iclass 15, count 0 2006.217.08:26:02.22#ibcon#flushed, iclass 15, count 0 2006.217.08:26:02.22#ibcon#about to write, iclass 15, count 0 2006.217.08:26:02.22#ibcon#wrote, iclass 15, count 0 2006.217.08:26:02.22#ibcon#about to read 3, iclass 15, count 0 2006.217.08:26:02.24#ibcon#read 3, iclass 15, count 0 2006.217.08:26:02.24#ibcon#about to read 4, iclass 15, count 0 2006.217.08:26:02.24#ibcon#read 4, iclass 15, count 0 2006.217.08:26:02.24#ibcon#about to read 5, iclass 15, count 0 2006.217.08:26:02.24#ibcon#read 5, iclass 15, count 0 2006.217.08:26:02.24#ibcon#about to read 6, iclass 15, count 0 2006.217.08:26:02.24#ibcon#read 6, iclass 15, count 0 2006.217.08:26:02.24#ibcon#end of sib2, iclass 15, count 0 2006.217.08:26:02.24#ibcon#*after write, iclass 15, count 0 2006.217.08:26:02.24#ibcon#*before return 0, iclass 15, count 0 2006.217.08:26:02.24#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.217.08:26:02.24#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.217.08:26:02.24#ibcon#about to clear, iclass 15 cls_cnt 0 2006.217.08:26:02.24#ibcon#cleared, iclass 15 cls_cnt 0 2006.217.08:26:02.24$vc4f8/vblo=6,752.99 2006.217.08:26:02.24#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.217.08:26:02.24#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.217.08:26:02.24#ibcon#ireg 17 cls_cnt 0 2006.217.08:26:02.24#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.217.08:26:02.24#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.217.08:26:02.24#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.217.08:26:02.24#ibcon#enter wrdev, iclass 17, count 0 2006.217.08:26:02.24#ibcon#first serial, iclass 17, count 0 2006.217.08:26:02.24#ibcon#enter sib2, iclass 17, count 0 2006.217.08:26:02.24#ibcon#flushed, iclass 17, count 0 2006.217.08:26:02.24#ibcon#about to write, iclass 17, count 0 2006.217.08:26:02.24#ibcon#wrote, iclass 17, count 0 2006.217.08:26:02.24#ibcon#about to read 3, iclass 17, count 0 2006.217.08:26:02.26#ibcon#read 3, iclass 17, count 0 2006.217.08:26:02.26#ibcon#about to read 4, iclass 17, count 0 2006.217.08:26:02.26#ibcon#read 4, iclass 17, count 0 2006.217.08:26:02.26#ibcon#about to read 5, iclass 17, count 0 2006.217.08:26:02.26#ibcon#read 5, iclass 17, count 0 2006.217.08:26:02.26#ibcon#about to read 6, iclass 17, count 0 2006.217.08:26:02.26#ibcon#read 6, iclass 17, count 0 2006.217.08:26:02.26#ibcon#end of sib2, iclass 17, count 0 2006.217.08:26:02.26#ibcon#*mode == 0, iclass 17, count 0 2006.217.08:26:02.26#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.217.08:26:02.26#ibcon#[28=FRQ=06,752.99\r\n] 2006.217.08:26:02.26#ibcon#*before write, iclass 17, count 0 2006.217.08:26:02.26#ibcon#enter sib2, iclass 17, count 0 2006.217.08:26:02.26#ibcon#flushed, iclass 17, count 0 2006.217.08:26:02.26#ibcon#about to write, iclass 17, count 0 2006.217.08:26:02.26#ibcon#wrote, iclass 17, count 0 2006.217.08:26:02.26#ibcon#about to read 3, iclass 17, count 0 2006.217.08:26:02.30#ibcon#read 3, iclass 17, count 0 2006.217.08:26:02.30#ibcon#about to read 4, iclass 17, count 0 2006.217.08:26:02.30#ibcon#read 4, iclass 17, count 0 2006.217.08:26:02.30#ibcon#about to read 5, iclass 17, count 0 2006.217.08:26:02.30#ibcon#read 5, iclass 17, count 0 2006.217.08:26:02.30#ibcon#about to read 6, iclass 17, count 0 2006.217.08:26:02.30#ibcon#read 6, iclass 17, count 0 2006.217.08:26:02.30#ibcon#end of sib2, iclass 17, count 0 2006.217.08:26:02.30#ibcon#*after write, iclass 17, count 0 2006.217.08:26:02.30#ibcon#*before return 0, iclass 17, count 0 2006.217.08:26:02.30#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.217.08:26:02.30#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.217.08:26:02.30#ibcon#about to clear, iclass 17 cls_cnt 0 2006.217.08:26:02.30#ibcon#cleared, iclass 17 cls_cnt 0 2006.217.08:26:02.30$vc4f8/vb=6,4 2006.217.08:26:02.30#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.217.08:26:02.30#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.217.08:26:02.30#ibcon#ireg 11 cls_cnt 2 2006.217.08:26:02.30#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.217.08:26:02.36#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.217.08:26:02.36#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.217.08:26:02.36#ibcon#enter wrdev, iclass 19, count 2 2006.217.08:26:02.36#ibcon#first serial, iclass 19, count 2 2006.217.08:26:02.36#ibcon#enter sib2, iclass 19, count 2 2006.217.08:26:02.36#ibcon#flushed, iclass 19, count 2 2006.217.08:26:02.36#ibcon#about to write, iclass 19, count 2 2006.217.08:26:02.36#ibcon#wrote, iclass 19, count 2 2006.217.08:26:02.36#ibcon#about to read 3, iclass 19, count 2 2006.217.08:26:02.38#ibcon#read 3, iclass 19, count 2 2006.217.08:26:02.38#ibcon#about to read 4, iclass 19, count 2 2006.217.08:26:02.38#ibcon#read 4, iclass 19, count 2 2006.217.08:26:02.38#ibcon#about to read 5, iclass 19, count 2 2006.217.08:26:02.38#ibcon#read 5, iclass 19, count 2 2006.217.08:26:02.38#ibcon#about to read 6, iclass 19, count 2 2006.217.08:26:02.38#ibcon#read 6, iclass 19, count 2 2006.217.08:26:02.38#ibcon#end of sib2, iclass 19, count 2 2006.217.08:26:02.38#ibcon#*mode == 0, iclass 19, count 2 2006.217.08:26:02.38#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.217.08:26:02.38#ibcon#[27=AT06-04\r\n] 2006.217.08:26:02.38#ibcon#*before write, iclass 19, count 2 2006.217.08:26:02.38#ibcon#enter sib2, iclass 19, count 2 2006.217.08:26:02.38#ibcon#flushed, iclass 19, count 2 2006.217.08:26:02.38#ibcon#about to write, iclass 19, count 2 2006.217.08:26:02.38#ibcon#wrote, iclass 19, count 2 2006.217.08:26:02.38#ibcon#about to read 3, iclass 19, count 2 2006.217.08:26:02.41#ibcon#read 3, iclass 19, count 2 2006.217.08:26:02.41#ibcon#about to read 4, iclass 19, count 2 2006.217.08:26:02.41#ibcon#read 4, iclass 19, count 2 2006.217.08:26:02.41#ibcon#about to read 5, iclass 19, count 2 2006.217.08:26:02.41#ibcon#read 5, iclass 19, count 2 2006.217.08:26:02.41#ibcon#about to read 6, iclass 19, count 2 2006.217.08:26:02.41#ibcon#read 6, iclass 19, count 2 2006.217.08:26:02.41#ibcon#end of sib2, iclass 19, count 2 2006.217.08:26:02.41#ibcon#*after write, iclass 19, count 2 2006.217.08:26:02.41#ibcon#*before return 0, iclass 19, count 2 2006.217.08:26:02.41#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.217.08:26:02.41#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.217.08:26:02.41#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.217.08:26:02.41#ibcon#ireg 7 cls_cnt 0 2006.217.08:26:02.41#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.217.08:26:02.53#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.217.08:26:02.53#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.217.08:26:02.53#ibcon#enter wrdev, iclass 19, count 0 2006.217.08:26:02.53#ibcon#first serial, iclass 19, count 0 2006.217.08:26:02.53#ibcon#enter sib2, iclass 19, count 0 2006.217.08:26:02.53#ibcon#flushed, iclass 19, count 0 2006.217.08:26:02.53#ibcon#about to write, iclass 19, count 0 2006.217.08:26:02.53#ibcon#wrote, iclass 19, count 0 2006.217.08:26:02.53#ibcon#about to read 3, iclass 19, count 0 2006.217.08:26:02.55#ibcon#read 3, iclass 19, count 0 2006.217.08:26:02.55#ibcon#about to read 4, iclass 19, count 0 2006.217.08:26:02.55#ibcon#read 4, iclass 19, count 0 2006.217.08:26:02.55#ibcon#about to read 5, iclass 19, count 0 2006.217.08:26:02.55#ibcon#read 5, iclass 19, count 0 2006.217.08:26:02.55#ibcon#about to read 6, iclass 19, count 0 2006.217.08:26:02.55#ibcon#read 6, iclass 19, count 0 2006.217.08:26:02.55#ibcon#end of sib2, iclass 19, count 0 2006.217.08:26:02.55#ibcon#*mode == 0, iclass 19, count 0 2006.217.08:26:02.55#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.217.08:26:02.55#ibcon#[27=USB\r\n] 2006.217.08:26:02.55#ibcon#*before write, iclass 19, count 0 2006.217.08:26:02.55#ibcon#enter sib2, iclass 19, count 0 2006.217.08:26:02.55#ibcon#flushed, iclass 19, count 0 2006.217.08:26:02.55#ibcon#about to write, iclass 19, count 0 2006.217.08:26:02.55#ibcon#wrote, iclass 19, count 0 2006.217.08:26:02.55#ibcon#about to read 3, iclass 19, count 0 2006.217.08:26:02.58#ibcon#read 3, iclass 19, count 0 2006.217.08:26:02.58#ibcon#about to read 4, iclass 19, count 0 2006.217.08:26:02.58#ibcon#read 4, iclass 19, count 0 2006.217.08:26:02.58#ibcon#about to read 5, iclass 19, count 0 2006.217.08:26:02.58#ibcon#read 5, iclass 19, count 0 2006.217.08:26:02.58#ibcon#about to read 6, iclass 19, count 0 2006.217.08:26:02.58#ibcon#read 6, iclass 19, count 0 2006.217.08:26:02.58#ibcon#end of sib2, iclass 19, count 0 2006.217.08:26:02.58#ibcon#*after write, iclass 19, count 0 2006.217.08:26:02.58#ibcon#*before return 0, iclass 19, count 0 2006.217.08:26:02.58#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.217.08:26:02.58#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.217.08:26:02.58#ibcon#about to clear, iclass 19 cls_cnt 0 2006.217.08:26:02.58#ibcon#cleared, iclass 19 cls_cnt 0 2006.217.08:26:02.58$vc4f8/vabw=wide 2006.217.08:26:02.58#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.217.08:26:02.58#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.217.08:26:02.58#ibcon#ireg 8 cls_cnt 0 2006.217.08:26:02.58#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.217.08:26:02.58#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.217.08:26:02.58#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.217.08:26:02.58#ibcon#enter wrdev, iclass 21, count 0 2006.217.08:26:02.58#ibcon#first serial, iclass 21, count 0 2006.217.08:26:02.58#ibcon#enter sib2, iclass 21, count 0 2006.217.08:26:02.58#ibcon#flushed, iclass 21, count 0 2006.217.08:26:02.58#ibcon#about to write, iclass 21, count 0 2006.217.08:26:02.58#ibcon#wrote, iclass 21, count 0 2006.217.08:26:02.58#ibcon#about to read 3, iclass 21, count 0 2006.217.08:26:02.60#ibcon#read 3, iclass 21, count 0 2006.217.08:26:02.60#ibcon#about to read 4, iclass 21, count 0 2006.217.08:26:02.60#ibcon#read 4, iclass 21, count 0 2006.217.08:26:02.60#ibcon#about to read 5, iclass 21, count 0 2006.217.08:26:02.60#ibcon#read 5, iclass 21, count 0 2006.217.08:26:02.60#ibcon#about to read 6, iclass 21, count 0 2006.217.08:26:02.60#ibcon#read 6, iclass 21, count 0 2006.217.08:26:02.60#ibcon#end of sib2, iclass 21, count 0 2006.217.08:26:02.60#ibcon#*mode == 0, iclass 21, count 0 2006.217.08:26:02.60#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.217.08:26:02.60#ibcon#[25=BW32\r\n] 2006.217.08:26:02.60#ibcon#*before write, iclass 21, count 0 2006.217.08:26:02.60#ibcon#enter sib2, iclass 21, count 0 2006.217.08:26:02.60#ibcon#flushed, iclass 21, count 0 2006.217.08:26:02.60#ibcon#about to write, iclass 21, count 0 2006.217.08:26:02.60#ibcon#wrote, iclass 21, count 0 2006.217.08:26:02.60#ibcon#about to read 3, iclass 21, count 0 2006.217.08:26:02.63#ibcon#read 3, iclass 21, count 0 2006.217.08:26:02.63#ibcon#about to read 4, iclass 21, count 0 2006.217.08:26:02.63#ibcon#read 4, iclass 21, count 0 2006.217.08:26:02.63#ibcon#about to read 5, iclass 21, count 0 2006.217.08:26:02.63#ibcon#read 5, iclass 21, count 0 2006.217.08:26:02.63#ibcon#about to read 6, iclass 21, count 0 2006.217.08:26:02.63#ibcon#read 6, iclass 21, count 0 2006.217.08:26:02.63#ibcon#end of sib2, iclass 21, count 0 2006.217.08:26:02.63#ibcon#*after write, iclass 21, count 0 2006.217.08:26:02.63#ibcon#*before return 0, iclass 21, count 0 2006.217.08:26:02.63#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.217.08:26:02.63#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.217.08:26:02.63#ibcon#about to clear, iclass 21 cls_cnt 0 2006.217.08:26:02.63#ibcon#cleared, iclass 21 cls_cnt 0 2006.217.08:26:02.63$vc4f8/vbbw=wide 2006.217.08:26:02.63#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.217.08:26:02.63#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.217.08:26:02.63#ibcon#ireg 8 cls_cnt 0 2006.217.08:26:02.63#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.217.08:26:02.70#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.217.08:26:02.70#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.217.08:26:02.70#ibcon#enter wrdev, iclass 23, count 0 2006.217.08:26:02.70#ibcon#first serial, iclass 23, count 0 2006.217.08:26:02.70#ibcon#enter sib2, iclass 23, count 0 2006.217.08:26:02.70#ibcon#flushed, iclass 23, count 0 2006.217.08:26:02.70#ibcon#about to write, iclass 23, count 0 2006.217.08:26:02.70#ibcon#wrote, iclass 23, count 0 2006.217.08:26:02.70#ibcon#about to read 3, iclass 23, count 0 2006.217.08:26:02.72#ibcon#read 3, iclass 23, count 0 2006.217.08:26:02.72#ibcon#about to read 4, iclass 23, count 0 2006.217.08:26:02.72#ibcon#read 4, iclass 23, count 0 2006.217.08:26:02.72#ibcon#about to read 5, iclass 23, count 0 2006.217.08:26:02.72#ibcon#read 5, iclass 23, count 0 2006.217.08:26:02.72#ibcon#about to read 6, iclass 23, count 0 2006.217.08:26:02.72#ibcon#read 6, iclass 23, count 0 2006.217.08:26:02.72#ibcon#end of sib2, iclass 23, count 0 2006.217.08:26:02.72#ibcon#*mode == 0, iclass 23, count 0 2006.217.08:26:02.72#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.217.08:26:02.72#ibcon#[27=BW32\r\n] 2006.217.08:26:02.72#ibcon#*before write, iclass 23, count 0 2006.217.08:26:02.72#ibcon#enter sib2, iclass 23, count 0 2006.217.08:26:02.72#ibcon#flushed, iclass 23, count 0 2006.217.08:26:02.72#ibcon#about to write, iclass 23, count 0 2006.217.08:26:02.72#ibcon#wrote, iclass 23, count 0 2006.217.08:26:02.72#ibcon#about to read 3, iclass 23, count 0 2006.217.08:26:02.75#ibcon#read 3, iclass 23, count 0 2006.217.08:26:02.75#ibcon#about to read 4, iclass 23, count 0 2006.217.08:26:02.75#ibcon#read 4, iclass 23, count 0 2006.217.08:26:02.75#ibcon#about to read 5, iclass 23, count 0 2006.217.08:26:02.75#ibcon#read 5, iclass 23, count 0 2006.217.08:26:02.75#ibcon#about to read 6, iclass 23, count 0 2006.217.08:26:02.75#ibcon#read 6, iclass 23, count 0 2006.217.08:26:02.75#ibcon#end of sib2, iclass 23, count 0 2006.217.08:26:02.75#ibcon#*after write, iclass 23, count 0 2006.217.08:26:02.75#ibcon#*before return 0, iclass 23, count 0 2006.217.08:26:02.75#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.217.08:26:02.75#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.217.08:26:02.75#ibcon#about to clear, iclass 23 cls_cnt 0 2006.217.08:26:02.75#ibcon#cleared, iclass 23 cls_cnt 0 2006.217.08:26:02.75$4f8m12a/ifd4f 2006.217.08:26:02.75$ifd4f/lo= 2006.217.08:26:02.75$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.217.08:26:02.75$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.217.08:26:02.75$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.217.08:26:02.75$ifd4f/patch= 2006.217.08:26:02.75$ifd4f/patch=lo1,a1,a2,a3,a4 2006.217.08:26:02.75$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.217.08:26:02.75$ifd4f/patch=lo3,a5,a6,a7,a8 2006.217.08:26:02.75$4f8m12a/"form=m,16.000,1:2 2006.217.08:26:02.75$4f8m12a/"tpicd 2006.217.08:26:02.75$4f8m12a/echo=off 2006.217.08:26:02.75$4f8m12a/xlog=off 2006.217.08:26:02.75:!2006.217.08:26:30 2006.217.08:26:18.14#trakl#Source acquired 2006.217.08:26:20.14#flagr#flagr/antenna,acquired 2006.217.08:26:30.00:preob 2006.217.08:26:30.14/onsource/TRACKING 2006.217.08:26:30.14:!2006.217.08:26:40 2006.217.08:26:40.00:data_valid=on 2006.217.08:26:40.00:midob 2006.217.08:26:41.14/onsource/TRACKING 2006.217.08:26:41.14/wx/30.39,1008.6,65 2006.217.08:26:41.33/cable/+6.3864E-03 2006.217.08:26:42.42/va/01,05,usb,yes,32,33 2006.217.08:26:42.42/va/02,04,usb,yes,29,31 2006.217.08:26:42.42/va/03,04,usb,yes,28,28 2006.217.08:26:42.42/va/04,04,usb,yes,31,33 2006.217.08:26:42.42/va/05,07,usb,yes,33,35 2006.217.08:26:42.42/va/06,06,usb,yes,32,32 2006.217.08:26:42.42/va/07,06,usb,yes,33,32 2006.217.08:26:42.42/va/08,07,usb,yes,31,30 2006.217.08:26:42.65/valo/01,532.99,yes,locked 2006.217.08:26:42.65/valo/02,572.99,yes,locked 2006.217.08:26:42.65/valo/03,672.99,yes,locked 2006.217.08:26:42.65/valo/04,832.99,yes,locked 2006.217.08:26:42.65/valo/05,652.99,yes,locked 2006.217.08:26:42.65/valo/06,772.99,yes,locked 2006.217.08:26:42.65/valo/07,832.99,yes,locked 2006.217.08:26:42.65/valo/08,852.99,yes,locked 2006.217.08:26:43.74/vb/01,04,usb,yes,30,29 2006.217.08:26:43.74/vb/02,04,usb,yes,32,33 2006.217.08:26:43.74/vb/03,04,usb,yes,28,32 2006.217.08:26:43.74/vb/04,04,usb,yes,29,29 2006.217.08:26:43.74/vb/05,04,usb,yes,28,32 2006.217.08:26:43.74/vb/06,04,usb,yes,29,31 2006.217.08:26:43.74/vb/07,04,usb,yes,31,31 2006.217.08:26:43.74/vb/08,04,usb,yes,28,32 2006.217.08:26:43.98/vblo/01,632.99,yes,locked 2006.217.08:26:43.98/vblo/02,640.99,yes,locked 2006.217.08:26:43.98/vblo/03,656.99,yes,locked 2006.217.08:26:43.98/vblo/04,712.99,yes,locked 2006.217.08:26:43.98/vblo/05,744.99,yes,locked 2006.217.08:26:43.98/vblo/06,752.99,yes,locked 2006.217.08:26:43.98/vblo/07,734.99,yes,locked 2006.217.08:26:43.98/vblo/08,744.99,yes,locked 2006.217.08:26:44.13/vabw/8 2006.217.08:26:44.28/vbbw/8 2006.217.08:26:44.37/xfe/off,on,15.0 2006.217.08:26:44.80/ifatt/23,28,28,28 2006.217.08:26:45.07/fmout-gps/S +4.37E-07 2006.217.08:26:45.15:!2006.217.08:27:40 2006.217.08:27:40.01:data_valid=off 2006.217.08:27:40.02:postob 2006.217.08:27:40.19/cable/+6.3852E-03 2006.217.08:27:40.20/wx/30.37,1008.6,65 2006.217.08:27:41.07/fmout-gps/S +4.39E-07 2006.217.08:27:41.08:checkk5last 2006.217.08:27:41.08&checkk5last/chk_obsdata=1 2006.217.08:27:41.08&checkk5last/chk_obsdata=2 2006.217.08:27:41.09&checkk5last/chk_obsdata=3 2006.217.08:27:41.09&checkk5last/chk_obsdata=4 2006.217.08:27:41.09&checkk5last/k5log=1 2006.217.08:27:41.09&checkk5last/k5log=2 2006.217.08:27:41.10&checkk5last/k5log=3 2006.217.08:27:41.10&checkk5last/k5log=4 2006.217.08:27:41.10&checkk5last/obsinfo 2006.217.08:27:41.48/chk_obsdata//k5ts1/T2170826??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.08:27:41.84/chk_obsdata//k5ts2/T2170826??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.08:27:42.21/chk_obsdata//k5ts3/T2170826??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.08:27:42.58/chk_obsdata//k5ts4/T2170826??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.217.08:27:43.27/k5log//k5ts1_log_newline 2006.217.08:27:43.96/k5log//k5ts2_log_newline 2006.217.08:27:44.64/k5log//k5ts3_log_newline 2006.217.08:27:45.33/k5log//k5ts4_log_newline 2006.217.08:27:45.35/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.217.08:27:45.35:"sched_end 2006.217.08:27:45.35:checkk5hdd 2006.217.08:27:45.35&checkk5hdd/chk_hdd=1 2006.217.08:27:45.35&checkk5hdd/chk_hdd=2 2006.217.08:27:45.35&checkk5hdd/chk_hdd=3 2006.217.08:27:45.35&checkk5hdd/chk_hdd=4 2006.217.08:27:48.22/chk_hdd//k5ts1/GSI00275:T217073000a.dat~T217082640a.dat[13241352192Byte] 2006.217.08:27:51.02/chk_hdd//k5ts2/GSI00163:T217073000b.dat~T217082640b.dat[13241352192Byte] 2006.217.08:27:53.91/chk_hdd//k5ts3/GSI00278:T217073000c.dat~T217082640c.dat[13241352192Byte] 2006.217.08:27:56.72/chk_hdd//k5ts4/GSI00294:T217073000d.dat~T217082640d.dat[13241352192Byte] 2006.217.08:27:56.72:sy=cp /usr2/log/k06217ts.log /usr2/log_backup/ 2006.217.08:27:56.81:log=u06217ts